Honeywell_Programers_Reference_Manual_s_200_1200_1250_2200_4200_Oct68 Honeywell Programers Reference Manual S 200 1200 1250 2200 4200 Oct68
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HONEYWELL
HARDWARE
SERIES 200
PROGRAMMERS'
REFERENCE MANUAL
MODELS 200/1200
1250/2200 / 4200
SUBJECT:
The Central Processor Hardware of Series 200
Models 200, 1200, 12S0, 2 2 00, and 4200; The
. Easyc oder Assembly Language; Summary Infor mation concerning Pro g ramming Series 200
Peripheral Devices and the Scientific Unit.
SPECIAL
INSTRUCTI O NS:
This edition completely supersedes revision
of the Ser i es 200 Programmers I Referenc e
Manual (Models 200/1200/2200/4 2 00), Order No.
139, dated November 10, 1966, a n d inc orporates
the information published in Addenda #1 and #2
to that manual. The portions of this public ation
containing new and changed i nforma tion a r e
indicated on page iii.
This volume and the manua ls and bulletins per taining to the peripheral components of an i n stalled Series 200 system together c onstitute a
programmers I handbook for that system .
DATE:
October 1, 1968
OS02
SM
7.S96 9
Printed in U. S. A.
FILE NO . :
*
113. OOOS. 0000. 2-139
'~ Underscoring
denotes Order Number .
PREFACE
This manual constitutes for the programmer a reference source of detailed information
concerning the central processor hardware of Series 200 Models 200, 1200, 1250, 2200, and
4200.
The Easycoder Assembly Language, used with the Series 200/Basic Programming Sys-
tem and the Operating System -
Mod 1, is also
defined~
In addition, this volume contains sum-
mary information concerning the programming of Series 200 peripheral devices and the scientific
unit.
The hardware information presented herein is equally applicable for the programmer using
the Series 200/0perating System -
Mod 2.
However, for this usage it should be supplemented
by the information contained in Appendix C of the software manual Assembler J (Order No. 432).
Separate hardware manuals and bulletins contain detailed information about programming
and operating individual Series 200 peripheral devices.
Specific peripheral device publications
are named in the tables of input/output control characters beginning on page 8-120 of this manual.
The only prerequisite for a thorough understanding of the information presented herein is
a familiarity with basic data processing terminology.
No previous knowledge of the Series 200
is as sumed.
A programmers' handbook may be constructed by combining in a single binder this volume
and the manuals/bulletins pertaining to the peripheral components of the installed Series 200
system.
This manual and the peripheral device manuals are all published in loose-leaf format
for ease of rapid updating by means of replacement-page addenda.
The equipment characteristics reported herein remain subject to change to allow the introduction of design improvements.
Copyright 1968
Honeywell Inc.
Wellesley Hills, Massachusetts 02181
ii
#2-139
NEW AND CHANGED INFORMA TION
Extensive functional descriptions and progranuning infornlation for the Model 1250 have
been added.
New infornlation and new peripheral devices for all Series 200 processors have
been incorporated.
Likewise, the infornlation carried over fronl revision 1 has been extensively
updated to correct technical error s and to enhance its clarity.
New infornlation and changes added to this publication since the last edition are indicated
below by page nUnlber and itenl.
Page
1-8
1-9
1-11
1-12
1-22
1-23
1-24
2-4
2-5
2-6
2-7
2-10
2-17
5-19
6-8
8-15
8-17
8-21
8-23
8-24
8-26
8-43
8-55
8-58
8-60
Itenl( s)
Tables 1-1 and 1-2
Para. 3
Table 1-3 and
Para. 2
Para. 2 and 3
Table 1-7
Note 5
Note 6 and Para. 4
All
All
All
Para. 1
Table 2-2
Footnote 2
Table 2-4
Para. 5
Para. 3 - Note
Note 5
Note 5
Note 4
Note 4
Note 7
Note 9
Note 3
Exanlple
Table 8-12
Notes 4 and 5
Page
8-62
8-63
8-64
8-67
8-82
8-85
8-86
8-87
8-88
8-8.9
8-90
8-92
8-94
8-96
8-100
8-111
8-125
B-9
C-9
C-I0
C-ll
F-4
F-5
F-6
G-2
G-3
Appendix H
iii
Itenl(s)
Note 4
Para. 3 and Table 8 -15
Note 4
Note 2
Note 3
Notes 6, 7, and 8
All
All
All
All
All
Note 7
All
Note 3
Note 4
Table 8-23
Note 1
Table B-9
Table C-2
Table C-2
Table C-3
Table F-l
Table F-l
Table F-l
Para. 5
Para. 3,4, and 5
All
#2-139
TABLE OF
CONTENTS
Page
Section I
Series 200 COIl1.ponents
Central Processor
Standard Processing Mode
Interrupt Proces sing Mode
External Interr'upts .
Internal Interrupt ..•
Addressing Modes
IteIl1.-Mark Trapping Mode ...
Processing P'ower
Peripheral EquipIl1.ent
Peripheral Control o .
Punched Card EquipIl1.ent .
High Speed Printers .••
Print Buffer ..
Magnetic Tape Units
1200 BPI Recording Density ...
Disk Pack Drives ..
Disk Files ...
RandoIl1. Acces s DruIl1.s
High -Speed Dr·uIl1.s ...
Angular Position Indicator ....
Paper Tape EquipIl1.ent
Data COIl1.Il1.unication EquipIl1.ent
Cons ole EquipIl1.ent ...
Visual InforIl1.ation Projection Devices .
Teller TerIl1.inal Equipment ...
Additional Peripheral Devices .
Peripheral Data Transfer Operation
Peripheral Addresses and Unit Loads.
Read/Write Channel
Optional Features o.
Advanced PrograIl1.Il1.ing
Program Interr'upt .
Edit Instruction .
Additional Read/Write Channels, Unit Loads, and
Addres s As signments
Storage Protect
Extended Multiprogramming and 8-Bit Transfer
Scientific Unit
Feature 0191 .
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The Central Proces sor
Main MeIl1.ory
MeIl1.ory Cycle
Main MeIl1.ory in the Type 4201 Processor
MeIl1.ory Ac ce s s
Proces sing Unit .
MeIl1.ory Controller
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1-10
1-10
1-11
1-11
1-11
1-12
1-12
1-14
1-14
1-16
1-16
1-17
1-17
1-18
1-20
1-21
1-22
1-22
1-22
1-23
1-23
1-23
1-23
2-1
2-1
2-3
2-4
2-5
2-5
2-5
#2 -139
TABLE OF CONTENTS (cont)
Page
Section II (cont)
Interleaved Addressing...........................
Parity Check . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . • . • . . .
Control Menlory .•......•.•..•........ '.' . . . . • . . . . • . . . . .
Addres s Register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . .
Read/Write Counters. . . . . . . . . . . . . . . . ... . . . . • . . . • • . . . .
Arithnletic Unit .....•..•.•.....•...•..•....•...••....•
Control Unit ..•.... .' .•.•••..........•......•....•.....
Input/Output Traffic Control . . • . . . • . . . . . . . . . . . . . . . • . . . . .
Menlory Cycle Distribution ..•.........•......••.....
Prinlary and Auxiliary Read/Write Channels .....••....
Interlocking Read/Write Channels . . . . . . . . . . . . . . • . . . . .
Model 4200 Variable -Speed Read/Write Channels .•..•..
2-5
2-6
2-6
2-8
2-8
2-10
2-11
2-12
2-12
2-16
2-16
2-16
Section III
Data Fornlat . . . • . . . . . . . . . . • . • • • . • . . . . . . • . . . . . • • . . . . • . . . . .
Variable Field Length. . . . • • . • • • .. . . • . • . • . . . . . . • . . . • • . . . .
Instr'uction Fornlat ...•.••••.••....•....•.•..•..•••....
Operation Code . . . . • . . . • • . . • . . . . • . . . • . . . . . • . . . • • . . • •
A and B Addresses. . . • . • • . . • • • • . . . . . . . . . . . . . • • • . . . . .
Variant Character .....•.•.......••.•.........•.....
S'unlnlary ..............•..•.........•.........•.....
Organization of Data in Main Menlory . . • . . • . • . . . . . • • . . • . .
Fields . . . . . . • • • • . . . . . . • . . . . . . • • . • . . . • • . . • . • . . • • . . • .
Itenls ..••••......•.....•.•....•..•.•.•..•...•...•.
Records .•......•.......•......•..•. ,••....•.••.••..
S'unlnlary .......•...•...•.•......•..•........•.....
Magnetic Tape Data Fornlat ....•..•.•.....••.....•.....
P'unched Card Fornlat . . . . . . • . . • . . . . • . . • . . . . . . . . . . . . . . • .
3-1
3-1
3-2
3-2
3-2
3-3
3-3
3-4
3 -4
3-5
3-6
3-6
3-7
3-8
Section IV
Addressing .•.••....•..•......•.•.....•......•....•••.••.
Basic Concepts .....•...•.....•..••.•..•...•...•••.....
Registers Used in Addressing .....•.••...•.••....•••.•..
Sequence Register (SR) ..••.•....••••.•..•••..•••.•.•
Change Sequence Register (CSR) .. -.••..........•••.•.•
External Interrupt Register (EIR) ........•.....•••••••
Internal Interrupt Register (IIR) . . . . . . . . . . . . . . . . . . . • . .
A-Address Register (AAR) ..•..•..•.•....•••..••••.••
B -Addres s Register (BAR) ....•...•...••...•••.••.•..
S'unlnlary ..•...........•.••.•...••••..•••••••••.•..
Addressing Modes ..••......•..•.••.•...••.•..•.•••..•.
Two -Character Addres sing Mode •...•...••.•..•••.•..
Three -Character Addres sing Mode •...•.••••..•.•.•..
Four-Character Addressing Mode .•.•..•...••.•...•..
Address Modification •••••..•.....•••..•...........••..
Index Registers ...••....•..•.•.•.•.....•.......•...•
Index .Register Map ...•.•..•...•.••....•.•..•..•.•
Three-Character Address ....•...••.••.••.•.•.•.••..
Indirect Addressing ...•...•..••.•..•.•..•.•.•••..
Indexed Addressing .........•.••......•.••••.•....
4-1
4-1
4-3
4-3
4-3
4-3
4-4
4-4
4-4
4-4
4-5
4-5
4-6
4-8
4-8
4-9
4-9
4-10
4-10
4-12
v
#2-139
TABLE OF CONTENTS (cont)
Page
Section IV (cont)
Four -Character Addressing Mode .....•••........•...
Indirect Addressing .• ,.......•.......•.•••..•.•••.
Indexed Addr e s sing ..•..•....•.•..•......•...•...
Treatm.ent of Addresses Larger Than A Mem.ory's
Maxim.um. Address ...•......•.•••.•..•.••.•••.•...•.
Potential Addresses Within Address Range ...•
o •••
Potential Addresses Outside Address
Register Range . . • . . . . • . . • • . • • . . . • • • . • • • . • . . • . • •
Explicit Addressing, Im.plicit Addressing, and Chaining....
0
Section V
Section VI
•
Easycoder Program.ITling ...•••..•..•......•••••....••.•..•
Intr od'uction .....•......•......•••.•....•..•.•..••.•.••
The Sym.bolic Lang'uage ...•..•.•.....••••.•.••.•.....•.
The Assem.blers .••...•...•...••••.•.••••..•.•.••.••.••
Coding Form. .••.•.•....•......••.•...•••..•••••.•.••••
Card Num.ber (Card Colum.ns 1-5) .•..•.•.........•••.•
Type (Card Colum.n 6) •••••••••••••••••••••••••••••••
Mark (Card Colum.n 7) ••••••••••••••••••••••••••••••
Location (Card Colum.ns 8 -14) ...•...•.•..•.••.•••••••
Operation Code (Card Colum.ns 15 -20) .....••.•••......•
Operands ..•.••••....••....•.••.•....•...••.....•••
Additional Coding Rules ......•....•....••••••.••.•.•
Address Codes ...••..•.•.••.....••....•....•..•.•.••.•
Absolute ...••.•.•.....•......•.•..•.••.•..•••.•••.•
Sym.bolic ..•••..•..•......•..••..••••.....•••...••.•
Self Reference .•.•.......•......••.•....••...•.•••••
Relative .................••....•.•..•.••..••.•..•..•
Out-of-Sequence .•.....••....•..•..•...•.•.••..•.•••.
Blank. . .• . .. .• . . • . . . .. . . . . . .. . • •. . .• • . . . . . •• •. . . • .•
Literals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . • . . • . . .
Decim.al Literals ........•.....•.•.•..••.•..•.••.•
Binary Literals ........•....•.........•....••••.•
Octal Literals ....•..•..•.•.••.....••.•....••••.•
Alphanum.eric Literals ......•.......•..•••.••.••.•
Area Defining Literals ..•..•......•.•..•••••••••••
Addres s Literals ...•..•...•••.•.•.•...•••.••••••.
Variant Character ..••...•••.....•••••..••.•.•••••••
Input/Output Control Characters ...••...••.•.•..•.••.•
Addres s Modification Codes •.•..•.•...••.•.•..•••••••.•
Indexed ..••....••••.•.•••.•••••.••...•••••.••••••••
Indirect ..•..•.••••.•..•••....•.••....••••••.•••••••
Data Form.atting Statem.ents ..•••.•..••••.•.•.•••.•.•••••..
Introduction ..•.•.••••••••.•••..•••.•.•••.••••••.•••
Define Constant with Word Mark - DCW .. . . . • • . . . • • • • • • •
N'um.eric Constants. • • • . . . • • • . . . • . • • . . . . . • . • • • • . • • • • •
Decim.al Constants ..•••••.•.•••...••...••.•.••.••
BinaryConstants .•••..•••••.•..•.•.•....•..•.•.•.
Octal Constants ••.•••• . . • • • . • . . • • . • . • • • • • • • • • • • . •
vi
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4-13
4-13
4-14
4-16
4-16
4 -16
4-17
5-1
5-1
5-3
5-3
5-5
5-5
5-6
5-6
5-8
5-10
5-11
5-12
5 -12
5 -13
5-13
5-13
5-14
5-15
5-15
5 -15
5-16
5-16
5-17
5 -18
5-19
5-19
5-20
5-21
5-21
5-21
5-23
6-1
6-1
6-2
6-2
6-2
6-2
6-3
#2-139
TABLE OF CONTENTS (cont)
Page
Section VI (cont)
Alphanunleric Constants ..
Blank Constants
Floating -Point Constants.
Define Constant - DC
Reserve Area - RESV
Define Symbolic Address - DSA ...
Define Area - DA
Easycoder Card D Options o.
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Section VII
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Instructions
Introduction ...•.•••..•.•..•.•
Arithnletic Operations
Binary Addition
Binary Subtraction
De cinlal Addition.
True Add.
C onlplenlent Add .
De cinlal Subtraction
Indicator s
Multiplication.
Division .
Add - A
S·ubtract - S
Binary Add - BA .
Binary Subtract - BS ..••.
Zero and Add - ZA
0
••••
••
0.00.00.0.00
Section VIII
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Assenlbly Control Statenlents o . o • • • •
Introd·uction .•
Progranl Header - PROG o.
Segnlent Header - SEG .•.•
Execute - EX
Transfer - XFR
Origin· - ORG
Modular Origin - MORG ••
Literal Origin - LIT ORG o.
Set Address Mode - ADMODE
Equals - EQU ...
Control Equals - CEQU
Menlory DUnlp - HSM
Skip - SKIP.
Suffix - SFX
Repeat - REP ..
Generate - GEN ...
Set Line NUnlber - SET LIN o.
Set Out-of-Sequence Base - XBASE ..
Clear - CLEAR
End - END
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6-4
6-4
6-5
6-5
6-6
6-7
6-7
6-10
7-1
7-1
7-2
7-4
7-4
7-6
7-7
7-9
7-9
7-11
7-12
7-13
7-14
7-15
7 -15
7-16
7-17
7-18
7-18
7-19
7-20
8-1
8 -1
8-4
8-4
8-4
8-7
8-7
8-7
8-8
8-9
8-9
8-11
8-14
8-16
8...:17
8-19
8-20
#2-139
TABLE OF CONTENTS (cont)
Page
Section VIII (cont)
Zero and S·ubtract - ZS .•...•.....•.•.•.....•....•....
M·ultiply - M .....••.•.•.....•.•.•.••.•....•.••.•.••.
Di vide - D .....••......•.........•....•..•••.•
Logic ...••.•.•.•.•...•.........•..•..••..•...........•
Extract - EXT ....•...•......•...•....•..•••.••••••.•
Half Add - HA .•.•....••.•....•.••.•.•........•.••..••
S·ubstitute - SST .
COnlpare - C •...•.•..•..•.•.......
Branch - B .....•.......•.•.•••......•.••.•.•....•..
Branch on Condition Test - BeT ..•..•..•.••.•.........
Branch on Character Condition - BCC .•................
Branch if Character Equal - BCE ..........••..••.....•
Branch on Bit Equal .- BBE ...•.••••••.•.••••.•••.••.••
Control ....•.•.•.....•.........•....•.•........•...•.
Set Word Mark -SW ...•
Set Itenl Mark - SI ....•..•.........•....•.••.•.••....
Clear Word Mark - CW ...•.........•.......•••.••••..
Clear Itenl Mark - CI .•......•....•.....•..•......
Halt - H .................•..•......•....•.•.
No Operation - NOP ..•••.......•.•.......••....•...••
Move Characters to Word Mark - MCW ..••••.••..•••..•
Load Characters to A-Field Word Mark - LCA ...•..•.•.
Store Control Registers - SCR ..••...•..••......•....•
Load Control Registers - LCR •...•..•.••.•.•.••...•..
Change Addressing Mode - CAM ....•..•...•••.•.••..••
Change Sequencing Mode - CSM ...••..••.•..•.•..•.•..
Extended Move - EXM ...•.......•.••••.••••.•.....••
Move and Translate - MAT ...•......••.•..•.••••••.••
Move Item. and Translate - MIT ....•.•..••...•.•.••.••
Load Index/Barricade Register - LIB ..••...••••..•.•••
Store Index/Barricade Register - SIB ..•....•..•..•.•••
Table Lookup - TLU .•.•..••.•.•..•••..•.•••...•.•.•.
Move or Scan - MOS .....•.•••••..••.•••••.•.•••..•..
Interr·upt Control •.•..•••.••.•.••
Store Variant and Indicators - SVI ...•.••.•••..•.......
Restore Variant and Indicators - R VI .••..••.•.....•.•.
Monitor Call - MC .••.••••....•..•.•.•..••...
Re s·um.e N orm.al Mode - RNM ..•.•...•••.••••.•.•..•••
Editing ...•..•...•...•.•.......•....••..••.•..•....•.•
Move Characters and Edit - MCE ..••..••.•••••••••••••
Input/Outp·ut ......•...
Input/Output Control Operations •...••
Selecting RWC Assignm.ents for Use in PDT Instructions
Considerations in Selecting RWC Assignm.ents ..••..
Device Data Transfer Rate ..•....•.•..•.•.••..
The Processor Being Used ....••.••••.•......•
Input/Output Sector to Which Device is Connected.
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8-22
8-23
8-25
8-27
8-28
8-29
8-30
8-32
8-34
8-35
8-39
8-42
8-44
8-47
8-48
8-49
8-50
8 -51
8-52
-8-54
8-55
8-56
8-58
8-60
8-62
8-66
8-67
8-70
8-74
8-79
8-82
8-83
8-86
8-91
8-92
8-95
8-98
8-99
8-103
8-104
8-109
8-110
8-110
8-110
8-110
8-113
8-114
#2-139
TABLE OF CONTENTS (cont)
Page
Section VIII (cont)
Upward Compatibility ..•.•..•....•....•....•.•.
Peripheral Data Transfer - PDT ...•..............•••..
Peripheral Control and Branch - PCB .......•.•••.....•.
Types of Test and Control Operations .....•.......•.•.
8-114
8-11S
8-127
8-128
Appendix A
Octal Notation ...' ..•.•••••••.•....•.••••..........•••.•.•.
Octal-Decimal Conversion Procedure .••.....••.••.....•.
A-I
A-3
Appendix B
Miscellaneo'us Tables ...•.•.........•.••.•.......•••..•.•.
B-1
Appendix C
Instruction S'ummary .......•........•..•.•.•..•..•..•.•...
C-l
Appendix D
Interr'upt Proces sing ...•....•................•.....•....•.
External Interr'upt ..•.........•.........•.........•..•.
Internal Interr'upt ....•...................•..•........•.
Interr'upt Programming .......•.•..•......•..•.•...•.•..
Peripheral Control Interrupt ............•.....•......••.
D-l
D-l
D-2
D-3
D-S
Appendix E
Storage Protect Feature .........••........•.• ' ..........••.
Index Registers .........••..••..••••.•.•.•......••..••.
Central Processor Modes .•.••...•..•..•.......•.•.•..•.
Internal Interrupt ...••.•.......•.•....•.••••.••...••.
Violations of Storage Protection .......•..•.•..•.••.•..•.
Proceed Indicator ....•.•....•...•••••.•....••.••....••
E-l
E-l
E-l
E-2
E .. 3
E-S
Appendix F
Scientific Unit for Models 1200, 1250, 2200, and 4200 ...•.••.
Data Format. . . • • • . . . • . . . . . . . . . • . . . . . . . • . . . . • . . . . . . • • •.
Floating -Point Registers ...•...••.•.....••........•••..
Floating -Point Indicator s ...••.•.•.. . • • . • . . . . . . . . • . . . . • •
Automatic Formatting in Arithmetic Operations. • . . . . . . . ••
Symbology............................................
Tillling Note s . . . • . • . . . . . . . . . • . • • . • . . . . . • • . . . . . . • • • . . • • .
F-l
F-l
F-l
F-2
F-2
F-2
F -3
Appendix G
Extended Multiprogralllming and 8 -Bit Transfer for
Models 1200, 12S0, 2200, and 4200 ••.•..•....•..••..•..••
Storage Protection with Base Relocation. . . • • • • • • . • • . . . • • .
External Interrupt Masking ....•......•...••.•..•.....•.
Instr'uction Timeout. . . . • . . . . . . . • • • • • . . • • • • . • . . . . • • • • . • .
8-Bit Transfer Capability. • • • . • . . • . • . • . . . . • . . • • • • . . . . . •.
Privileged SCR Instruction. . . . . • • • . . . . . . . • . • . . . . . . • . • • •.
G-l
G-l
G-2
G-2
G-3
G-4
Extended Input/Output Capacity for the Model 4200 ......•..•.
Feature 1116 .....................•.•..•...............
Features 4214A and 4214B ..•.•..•....••..••.•.....•.•.•
Feature 421S .......................................... .
B'uffered Sectors. . . • . • • • • . . • . • . • • . • . • . . • . • . • . . . . • • . • . •.
B-1
B-1
B-1
B-1
B-2
0
Appendix B
ix
•
#2-139
LIST OF
ILLUSTRATIONS
Page
Figure
Figure
Figure
Figure
Figure
Figure
Figure
I-I.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
Figure 1-8.
Figure 1-9.
Type 1201 Control Panel ............•............•.•...•.
Type 220 -1 Cons ole .•....
Type 220-3 Console . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . .
Main MeIrlory Size . . . . . . . . . '..
Main MeIrlory Speed ..........•..•.......•........•.....•.
Peripheral SiIrl'ultaneity ........••........•.....•.•..•....
CustOIrler Inquiry Handling via Typical COIrl!ITunications
Network ........••....•.•....•.........•....•....•...•.
Basic Input/Output Data Path . . . . . . . . . . . . . . . . . . . . . . • . . . . . • .
Addres s As sigmnents and Unit Loads Available in
Series 200 Processors ...•.....••...............•......
Data Path During Card Read Operation .•••..•...••.•.•....•
Logical Division of Series 200 Central Processor .•.•.......
Main MeIrlory Functions . . . . . . . . . . . • . • . . . . . . . . . . . . • . . . . . . .
One MeIrlory Position . . . . • . . . . . . . . . . . • . . . . . . . . .
Representation of Characters in Magnetic Core Storage ..... .
Type 4201 MeIrlory SubsysteIrl ...•••.••......• '.' ..•....••.
Model 4200 MeIrlory Interleaving (Type 4201-9
Central Processor) ...•.••.
Typical Control Register Function ...........••....•.•..
Data Flow Between Main MeIrlory and ArithIrletic Unit .....•.
Control Unit Activities ....•....•.•...............•.•.•..•
Input/Output Traffic Control Activities .....•....••.•.•.....
Data Transfer Intervals During One Peripheral Operation ....
Logical Decision PerforIrled by Input/Output Traffic Control
SYIrlbolic Representation of Input/Output Traffic Control. •....
Conversion of SyIrlbolic Tags to Absolute MeIrlory Addresses.
Series 200 Instruction ForIrlats ....••..•..••..•..•.•....•..
SYIrlbolic Representation of Series 200 Instructions .•.•..
Consecutive Storage Locations in Main MeIrlory ....••...••..
Data Field ForIrlat in Main MeIrlory ...•.........••....•••.
Two IteIrl F orIrlats in Main MeIrlory ..•....•...........•...
Record ForIrlat in Main Menlory .•....•.........•..•..•...•
SUnlIrlary of Internal Data ForIrlats ..•....•.......•....•••.
Character Representation on Magnetic Tape ...•...••
Data Fornlat on Magnetic Tape ...•......•..•..•••..•....•.
P'unched Card Codes .•.•.......••.......•....••.•......••
Typical Add Instr'uction .....•..••...•.•••..••.•.••.•......
Extraction of Data Fields in Typical Add Instruction ..•..•...
Series 200 Index Register Map ...••••.•.•••••........•••••
Extraction of Three-Character Indirect Address ....••.•.•.•
Extraction of Indexed Address in Three-Character Mode •••..
Extraction of Indirect and Indexed Four -Character Addres ses.
Series 200 Instruction ForIrlat 1 ...•••••.•.•..
Series 200 Instruction ForIrlat 2 ..••••.•..•......•••••...••
Series 200 Instruction ForIrlat 3 ..•...••••..••••••.•.•••••.
Relationship of Source, AsseIrlbler, and Object PrograIrl ..••.
0
•••••••••••••••••••••••••••••••
0
•••••••••••••••••••••••••••
0
Figure
Figure
Figure
Figure
Figure
Figure
Figure
1-10.
2-1.
2-2.
2-3.
2-4.
2-5.
2-6.
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
F igur e
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
2-7.
2-8.
2-9.
2 -10.
2-11.
2 -12.
2 -13.
3 -1.
3 -2.
3 -3.
3 -4.
3 -5.
3 -6.
3-7.
3 -8.
3 -9.
3 - 10.
3 -II.
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
4-7.
4-8.
4-9.
5-1.
0
0
•••••
0
•••••••••
••••••••••••••••••••••
0
••
0
0
0
0
x
•
•••
••••••
••••••••••••
1-2
1-3
1-3
1-6
1-6
1-6
1-15
1-18
1-19
1-19
2-1
2-2
2-3
2-3
2-4
2-6
2-7
2-11
2-11
2-12
2-13
2-14
2-15
3-2
3-3
3-4
3-4
3-5
3-5
3-6
3-6
3-7
3-8
3-8
4-1
4-2
4-9
4-11
4-13
4-15
4-17
4-18
4-18
5-2
#2-139
LIST OF ILLUSTRATIONS (cont)
Page
Figure
Figure
Figure
Figure
Figure
5-2.
5-3.
5-4.
5-5.
5 -6.
Figure 5-7.
Figure 5-8.
Figure 5 -9.
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
D-1.
D-2.
D-3.
Two-Character Address Assembly ....•...•• ~ .••......•...
Three -Character Addres s As sembly ....••.•....•.........
Four-Character Address Assembly ....•..•.•..••.........
Easycoder Coding Form .•.•.•.•....•....•.••.•....•..•..
As sembly of Indexed Addres s in Three -Character
Addressing Mode ..•••..•.•.••.•.••.•..•.••.•..•.•..•...
Assembly of Indexed Address in Four-Character
Addres sing Mode .•..•.•.••••..•.•..•.••..•.•.•......••
As sembly of Indirect Addres s in Three -Character
Addres sing Mode .•••••.••.............................
Assembly of Indirect Address in Four-Character
Addres sing Mode ........•••.••••...•..••••.•.......••.
True Add Examples •••••........•...•••......••.......••
Complement Add Examples ..••....•••......•••.....•.•.•.
A and B Fields in Multiply Operation ....•.•..••...•..•...•
Factor Locations in Divide Operation ..•....••....•••......
Changing Addressing Modes via CAM Instruction ....•......
MAT Operation ..••..•.••........••••.......•••....•...•
MIT Operation .•.•.•..•...•.•••.•.•.....••••.......•....
T L U Operation ......••••.•.........•.•......•.....•.••..
Example of Operation Utilizing Escape Codes ...•....••.....
Sample Coding for External Interrupt Routine ..•....•......
Sample Coding for Internal Interrupt Routine ....••....•..••
Interrupt Signal Generated by Peripheral Control .......... .
5-3
5-4
5-4
5-5
5-22
5-23
5-23
5-24
8-7
8-8
8-10
8-12
8-65
8-73
8-79
8-87
8-114
D-4
D-5
D-6
•
xi
#2-139
LIST OF
TABLES
Page
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
I-I.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
1-8.
1-9.
1-10.
1-11.
1-12.
1-13.
1-14.
1-15.
2-1.
2-2.
Table 2-3.
Table 2-4.
Table 4-1.
Table 4-2.
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
4-3.
4-4.
5-1.
5-2.
6-1.
7-I.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
.
P'unched Card EquiplIlent. • . . • . • . . . . • . . . . . . . . . • . . . • • . . . . . . .
High-Speed Printers. . • . . • . • . • . . . . . . . . . • . • • . • • . • • . . . . . • . . .
Magnetic Tape Units. . . • . • . . . . • • • • . • . . • . • . . . . . . . . . . • . • . . . .
Disk Pack Drives ...••••..•...........•..•.•..•..•.......
DiskFiles .•.•.........••.••.•.••••....•...........•..•..
Random Acces s Dr'um Units .•.••.......•......•.....••..•.
High-Speed Dr'ums ...••...•.......•..••.•••......•..•....
Paper Tape Equipment ...••.....••..•.••.•..........•.•...
Data Communication Equipment ...•....•...............•...
Console Equipment ..............•....•..............•..•.
Visual Information Projection Devices .•...••...........•...
Teller Terminal Equipment ..........•••..•...............
Additional Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . • . '.
Series 200 Optional Features . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .
Model 200 Advanced Programming Feature . . . . . . . . . . . . . . . . .
Memory Configurations for Type 420 1 Processors .......... .
Size of Control Memory Registers (Models 200 / 1200/
1250/2200/4200) ,...............•...........•......•.....
Control Memory Register s ........•......•....•..•••..•..•
Summary of Central Processor Characteristics .•..••...••..
Number of Index Registers SilTIultaneously Available to
a Program ..••••...••.........•....•.•....•.......•..•.
Index Register Addresses in Three-Character
Addres sing Mode ...•.••......•....•.......•.•.......•.•
Index Register Addresses in Four-Character Addressing Mode
Active Address Bits in Series 200 Processors .•..•.•••.•••..
Set I Punctuation Indicators ..•.••.•..••..........•.•..•.•.
Set II Punctuation Indicators (Easycoder C and D Only) •••••••
Data Formatting Statements .....•....•.••••..•••.•.••.••.•
As sembI y Control Statements .••••••.•.•.•.....•.••••.•...•
Symbology Used in Series 200 Instruction Descriptions ••••.••
Series 200 Add and Subtract Operations .•.•.•.•••••••••••••.
Binary Addition Table ..••••.•••••..••.••••.••.•••.•• ' •••••
Algebraic Signs in Decimal Addition .•.•••••••.•.•.•••••.•..
Decimal Arithmetic Sign Conventions .•.•..•.••.•.••.••••••.
Multiply Sign Conventions .•••••••••....•...•..•.•.•••••.•.
Divide Sign Conventions ...••••.•.•.••.••.•.••.•.••••••••••
SENSE Switch Conditions for BCT Instruction ..••.•..•••..••
Indicator Test Conditions for BCT Instruction . . . . . . . . . . . . . . .
Basic Test Conditions for BCC Instruction .••.•.•.•.•••••.••
BCC Test Conditions with Advanced Programming Instructions
Control Register Contents Stored by SCR Instruction ...••.•..
Control Registers Stored by SCR Instruction ..•.•..•.•....•.
Control Register Contents Loaded by LCR Instruction ••••..•.
Modes Specified by Variant Character in CAM Instruction .•••
Extended Move Conditions ...•....•..•••..•••....•...••..•.
Size of Information Units in MIT Operation ....•••.....••.••.
xii
1-8
1-9
1-9
1-10
1-11
1-11
1-12
1-12
1-13
1-14
1-16
1-16
1-17
1-20
1-21
2-4
2-7
2-8
2-17
4-10
4-12
4-14
4-15
5-7
5-7
6-1
7-1
8-2
8-4
8-4
8-7
8-9
8-10
8-13
8-36
8-37
8-40
8-41
8-58
8-59
8-61
8-63
8-68
8-75
#2-139
LIST OF TABLES (cont)
Page
Table
Table
Table
Table
Table
Table
3-18.
8-19.
8-20.
8-21.
8-22.
8-23.
Table 8-24.
Table 8-25.
Table 8-26.
Table
Table
Table
Table
8-27.
8-28.
8-29.
8-30.
Correspondence Between LIB Setting and Barricade Location
Move or Scan Conditions ...••...................•........
Information Stored by SVI Instruction ............•.........
Information Restored by RVI Instruction ..........•........
Special Characters in MCE Instruction . . . . . . . . . . . . . . . . . . . . .
Minimum R WC Capacity Requirements for Series 200
Peripheral Devices ..••..•.........•...........•.....••.
Description of PDT J/O Control Character Cl ...•••.•..••..
Description of PDT I/O Character CE (Escape Code) .•...•..
Description of PDT I/O Character C2 (Peripheral Control
Designation ..•....•.•.••...............................
Summary of PDT I/O Control Characters .............•....
C3 Coding for Type 209 and 209-2 Paper Tape Readers ....•.
C3 Coding for Type 210 Paper Tape Punch .......•.........
C3 Coding for Types 206 and 222 Printers and Type 237
Bill Feed Printer Control •..••.•
C3 Coding for Type 270A Random Access Drum ..•.•...••.•.
Summary of PDT I/O Control Characters for Type 286
Multi-Channel Communication Control ...•......•.........
Type 286-1, -2, -3 Line Control Instructions .•.•..•.•....••
Summary of PCB I/O Control Characters .•.•.....•...••..•
Summary of PCB I/O Control Characters for Type 286
Multi-Channel Communication Control ...•.•...••••....•.
PCB Control Characters C5 through C15 for Type 286-4, -5
Line Control Instrouctions .•.•..•.•...••..••.•.•....•••..
Description of PCB I/O Character CE ..........•..........
Binary-Octal Equivalents .•............•....•.•....•....••
Decimal-Octal Conversion Table .......•.............•.•••
Control Register Designations ..............•.......•.....
Extended Move (EXM) Conditions ..................•..•....
Branch on Condition Test (BCT) SENSE Switch Conditions .•••
Branch on Condition Test (BCT) Indicator Conditions ...... .
Branch on Character Condition (BCC) Conditions .•..•.•....
Series 200 Character Codes ...........•.
Binary, Octal, and Decimal Equivalents ....•.......•.....•
Powers of 2 .......••...••.•.•...•••..•.•.•....••.•...•••
Move or Scan Variants .•.••.•.•....•.....•.....•.••..••..
Instruction Summary - Timing Formulas for Models 200,
1200, 1250, and 2200 .•••.•..•.•.......•..•.•.•..•.••.•.
Instruction Timings 'for the Model 4200 ...••.....••.•..•...
Timings for Decimal Multiply and Divide, Models 200,
1200, 1250,2200 and 4200 •..•...................•.•••••
Summary of Interrupt/Allow Function Control and
Test Operations ...•..•••.•..••......•.•..•....•••.•••..
Summary of Scientific Instructions .••..•••.•....•.....•...
Controls /Devices Connectable to Buffered Sectors .•.•••••..
0• • • • • • • • • • • • • • • • • • • • • • • •
Table 8-3l.
Table 8-32.
Table 8-33.
Table 8-34.
Table 8-35.
Table 8-36.
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
8-37.
A-I.
A-2.
B-1.
B-2.
B-3.
B-4.
B-5.
B-6.
B-7.
B-8.
B-9.
C-1.
Table C-2.
Table C-3.
Table D-1.
Table F-1.
Table H-1.
0
xiii
••••••••••••••••
8-80
8-88
8-92
8-96
8-105
8-111
8-116
8-118
8-118
8-120
8-124
8-124
8-125
8-125
8-126
8-126
8-130
8-146
8-148
8-149
A-I
A-2
B-1
B-2
B-3
B-4
B-5
B-7
B-8
B-8
B-9
C-4
C-7
C -11
D-7
F-4
H-2
*2-139
SERIES 200
COMPONENTS
Honeywell's Series 200 Data Processing Syste:m is a set of :modularly designed, co:mpatible
:models, five of which - the Models 200, 1200, 1250, 2200, and 4200 :manual.
are the subject of this
Each :model consists of two basic ele:ments: a central processor, and an array of
peripheral devices connected to that proces sore
The peripheral equipm.ent in the syste:m can be
attached to any processor, and the nu:mber of connectable devices is limited only by the nu:mber
of unit power loads and peripheral address as sign:ments available with the particular processor.
The initial :me:mber of Series 200 was the Model 200. The capabilities of the Model 200
processor have twice been extended since its introduction.
Thus, seven central processors are
described herein: the three processors of Model 200 (Types 201, 201-1, and 201-2); the Type
1201; the Type 1251; the Type 2201; and the Type 4201.
The processing power of anyone of
these types can be increased at any ti:me by the addition of peripheral devices and/or optional
hardware features.
This section describes:
(1) the two basic ele:ments of a Series 200 :model
(processor and peripheral devices); (2) the :manner in which these elements co:m:municate with
one another; and (3) the expansion of processing power that is possible through the addition of
optional hardware features to a processor.
CENTRAL PROCESSOR
The central processor is the co:mputing and
control center of a Series 200 :model; instructions
processed within the central processor control
the operations of the entire co:mputer.
A Series
200 processor is functionally divided into three
units:
storage, control, and arith:metic.
The
storage unit provides :magnetic core storage for
both the program instructions and the data to be
processed according to these instructions; it is
also used to contain the resultant data.
The con-
trol unit directs the operation of the entire computer by selecting, interpreting, and controlling
1-1
#2-139
SECTION 1.
the execution of all program instructions.
SERIES 200 COMPONENTS
It controls not only the flow of info rTIlati on within the
central processor but also the flow of data between the central processor and all peripheral
equipment.
The arithmetic unit performs such operations as addition, subtraction, multiplica-
tion, division, and comparison, as directed by the control unit.
Included as a part of the central processor is a control panel (see Figure 1-1) which provides for easy communication between an operator and the computer.
By using various control
switches, the operator can start and stop the machine and can load and interrogate memory locations.
The control panel also includes from four to eight SENSE switches which may be used
in conjunction with programmed instructions to stop processing or to select predetermined program paths.
The use of these switches increases the flexibility of a program, allowing it to be
used in several different applications.
mm oI~J[;J[~}[iI ~
RESET
SYSTEM
lfxTEiiNAL]PiOGRAMfPAAITvTFANl
I
I
I
HOIEYWELL 1200
Figure 1-1.
I
I
~N!~::~_~~~J:'~~A~.eL~B_J
SENSE
Type 1201 Control Panel
Another comm'UIlication medium between the operator and the central processor is the
Type 220 console, of which two versions are available.
The Type 220-1 Console (Figure 1-2)
contains a typewriter which may be used as a peripheral device, operating under program control.
or as a logging typewriter by which the operator can make essential notes about the program in
progress.
The central processor control panel remains situated on the processor cabinetry and
is used for the functions described above.
In the Type 220-3 Console (Figure 1-3), most of the
co~trol
panel functions, including that
of direct access to the processor, are performed by means of the console typewriter.
In addition,
the typewriter can perform the peripheral and logging functions described for the Type 220-1.
The central processor control panel is replaced by a smaller control panel containing only the
main power switches, the SENSE switches, and certain check condition indicators which are
located in the bottom row of the control panel shown in Figure 1,:", 1.
The Type 220 -3 control
panel contains additional indicators used with the Storage Protect Feature (see page 1-23) and
the additional SENSE switches used with the larger Series 200 processors.
1-2
#2-139
SECTION I.
Figure 1-2.
SERIES 200 COMPONENTS
Type 220-1 Console
Figure 1-3.
Type 220-3 Console
STANDARD PROCESSING MODE
The central proces sor performs arithmetic and logical operations as directed by the instructions of an internally stored program.
These instructions are read into memory from an
input medium such as punched cards, magnetic tape, or punched paper tape.
Control circuitry
within the processor then selects, interprets, and executes these instructions.
instructions are executed sequentially.
Normally, the
Branch instructions are provided, however, which make
it possible to skip over a group of instructions or otherwise c.hange the sequence of the program.
INTERRUPT PROCESSING MODE
Sequential instruction execution is changed temporarily whenever the central proc~ssor is
interrupted.
Anyone of four sources can "demand" access to the central processor by generating
an interrupt signal, which turns on a central proces sor interrupt indicator.
Once an interrupt
indicator is detected as being on, a hardware response is made: information concerning the current status of the processor (including the setting of the sequence register) is stored, and a
branch is made to a stored routine which identifies and services the demand.
tests need not be made to detect the presence of an interrupt condition -
Thus, programmed
the entire process of
detecting and responding to an interrupt signal is an automatic hardware function.
After the
stored service routine has been executed, control is returned to the interrupted routine at the
point where the interruption occurred and the previous status is restored.
Two kinds of inter-
rupts can occur in the system: external interrupts and an internal interrupt.
A detailed descrip-
tion of interrupt functions and programming for interrupt processing is presented in Appendix D.
1-3
#2-139
SECTION I.
SERIES 200 COMPONENTS
External Interrupts
The three sources of external interrupts are:
1.
Peripheral Control - The control connected to any Series 200 peripheral
device can generate an interrupt signal under program control (peripheral
controls are described on page 1-7; peripheral control interruption is
described in Appendix D. For instance, a data communication control
which services one or a number of communication lines and devices may
generate a real-tim.e demand on central processor time to handle a customer inquiry from. a remote terminal. The current operation-s of the
processor are temporarily interrupted so that the inquiry may be serviced.
A routine to read the inquiry and to answer the question from. a stored
customer file is autom.atically executed, and a response is sent back to
the te rminal.
2.
Operator's Control Panel or Console - The operator can interrupt the
central processor by pressing the INTERRUPT button on the control panel
or console. 1 The source of such "on-site" interruptions is m.ade available
to the program by the execution of a single instruction at the beginning of
the interrupt service routine.
3.
Program Instruction - One instruction in the Series 200 repertoire, the
Monitor Call instruction, is used to generate an interrupt condition. 1
For programming convenience, the activation (or "calling") of the m.onitor
program can be accomplished by means of this instruction o
Internal Interrupt
If a central processor contains the Storage Protect Feature (Types 1201, 1251, 2201, and
4201 only), an internal interrupt condition, caused by certain violations of a protected memory
area or attempts to address nonexistent m.emory locations, can also occur.
Internal interrup-
tions are of lower priority than external interrupts, so that a processor executing an external
interrupt service routine does not respond to an internal interruption until the routine is completed.
Processing of internal interrupts is described in Appendix Eo
ADDRESSING MODES
Due to the unique binary addressing system. used in referencing the individual core storage
locations within the central processor, an address portion of a machine-language instruction can
occupy two, three, or four characters of memory.
The number of character positions employed
is controlled by two instructions: the assembly control instruction ADMODE, and the Change
Addressing Mode (CAM) instruction.
Any core storage address can be referenced in any addre ss-
ing mode by having the central processor prefix the address expressed in the instruction with a
binary value previously set in an address register.
Thus, the programmer has the ability to set
the address registers to some high module, switch to the two-character addressing mode, and
still continue to address that module.
1
This utilization of the smallest num.ber of character
The Type 201 and 201-1 processors cannot be interrupted by sources 2. and 3. above.
1-4
#2-139
SECTION I.
SERIES 200 COMPONENTS
positions to expres s any core storage addres s results in a reduction in the amount of memory
required for a particular program.
ITEM-MARK TRAPPING MODE
The item-mark trapping mode, which can be set via the CAM instructIon, causes the processor to treat and execute any instruction containing an item-marked op code as if it were a
Change Sequencing Mode (CSM) instruction, which results in a transfer of control to an instruction stored at a pre specified location.
This processing mode is used extensively in Liberator
systems and can also be used to control program branching.
PROCESSING POWER
The power of any processor within Series 200 can be defined as the sum of its main memory size, its internal speed, its degree of peripheral simultaneity, and the number of optional
feature s which may be added to it.
Main memory size within the Models 200/1200/1250/2200/4200 ranges from a minimum of
2, 048 character locations (Type s 201 and 201-1) to 524, 288 locations (Type 4201).
Figure 1-4
shows the modular main memory sizes of the seven processor types.
The internal speed of a processor is measured in terms of a memory cycle (i. e., the time
required to read and restore the contents of a unit location).
The unit location used by proces-
sors other than the Type 4201 is a single, six-bit character location.
The unit location of the
Type 4201 is four successive character locations that contain a four-character word.
Memory
cycle speeds range from two microseconds per character to 750 nanoseconds per four-character
word (see Figure 1-5).
Peripheral simultaneity is a key feature of Series 200 processors.
Among the processors
described in this manual, from 3 (Model 200 processors) to 16 (Type 4201 processor) simultaneous input/ output operations can be performed concurrently with internal computing (see
Figure 1-6).
A number of optional features can be included in the Series 200 processors to provide complete flexibility in specializing anyone proces sor to a user's particular application.
Since some
of these features refer to the peripheral capabilities of a processor, they are sum.marized at the
conclusion of this section.
1-5
#2-139
SECTION I.
SERIES 200 COMPONENTS
4201 1
220i
1250
1201
II
BASIC
II
OPTIONAL
201-2
201-i
201
1
The Type 4201 moves four successive
characters in 750 nanoseconds. Anyone
of these characters is thereby moved in
188 nanoseconds.
Figure 1-5.
Main Memory Speed
4201
2201
1251
1201
201-2
201-1
II
BASIC
I!!;~!~it
OPTIONAL
201
Figure 1-4.
Main Mem.ory Size
Figure 1-6. Peripheral Simultaneity (Number
of Read/Write Channels Available to Processors)
PERIPHERAL EQUIPMENT
The array of peripheral device s available
with Series 200 processors includes over 40 units:
console typewriters, punched card equipment,
high-speed printers, magnetic tape units, paper
tape equipment, random access drum units, disk
devices, MICR reader-sorters, multiple tape
listers, teller terminals, visual information projection units, and various data communication
controls and remote terminals. Also included
are computer-to-computer adapters, an interval
1-6
#2-139
SECTION 1.
SERIES 200 COMPONENTS
ti:mer, a ti:me-of-day clock, and controls for optical source-docu:ment readers, optical journal
readers, digital plotters, and a bill feed printer.
Infor:m.ation is transferred between anyone of the se device s and the central proce s sor by
:means of a single stored-progra:m instruction -
the Peripheral Data Transfer instruction de-
.
scribed in Section VIII. By coding various control characters in this instruction, the program:mer
specifies the direction of data transfer (into or out of the proces sor), the specific device involved
in the transfer, the data path over which information is to be transferred, and any other information necessary to define the input/output operation (e. g., the nu:mber of lines to be spaced
during printer operations).
The actual co:mmunication with the central processor is not made by
the particular peripheral device but by the peripheral control connected to that deviceo
PERIPHERAL CONTROL
A peripheral control regulates the transfer of data between a processor and a peripheral
device.
The control compensates for the difference in the data transfer rates of the processor
and the peripheral device by temporarily storing each character of transmitted information until
either the processor or the device is ready to receive the character.
The control also converts
each character into the code used by the intended recipient (e. g., the card reader control converts a character fro:m Hollerith code to the internal six-bit code of the central processor).
each character is transferred to the control, it is also checked for accuracy by the control.
As
One
particularly significant feature of the peripheral control is that it operates independently of the
central processor and requires access to the main memory only when infor:mation transfers are
performed.
In particular, all of the previously mentioned activities of the control - te:mporarily
storing, converting, and checking the information way.
do not involve the central processor in any
When each character of information is transferred, one :main :memory cycle is allocated
for the transfer.
So:me peripheral devices require one peripheral control per device (e. g., a card reader).
Other devices can be connected in :multiple fashion to a single peripheral control (e. g., up to
eight 1 /2-inch magnetic tape units can be directed by a single control).
The number of Series
200 devices connectable to a peripheral control is shown in Tables 1-1 through 1-10 on the following pages.
The infor:mation listed under "Unit Loads" and "Address Assign:ments" in these
tables is used in determining the nu:mber of peripheral controls that can be connected to a Series
200 processor, as explained on page 1-17.
PUNCHED CARD EQUIPMENT
Series 200 includes a wide variety of peripheral devices not only of different kinds, but'also
on several perfor:mance levels for the same kind.
1-7
For instance, four different punched card units
#2-139
SECTION I.
SERIES 200 COMPONENTS
are offered: two card readers, a card punch, and one reader /punch.
devices available within Series 200.
Table 1-1 lists the card
Note that a card device requires either one or two "unit
loads, " depending on the number of functions the device performs.
Table 1-1.
Punched Card Equipment
223
Card Reader
800 cards /minute
1
1
1
223-2
Card Reader
1050 cards /minute
1
1
1
214-1
Card Punch
100-400 cards/minute
1
1
1
214-2
Card Reader /Punch
Read: 400 cards /rninute
Punch: 100-400 cards/
minute
1
1
2
HIGH-SPEED PRINTERS
Six types of printers (see Table 1-2) produce printed reports, listings, etc., at speeds
which vary from 450 to 1,300 lines per minute.
grammer-assigned area in memory.
Processed information is .printed from any pro-
A single program instruction - the Move Character sand
Edit instruction - allows the programmer to punctuate the output date, suppress zeros, and insert identifying symbols in the data prior to printing.
Print Buffer
With the addition of the Print Buffer (Feature 036), the amount of central processor memory cycles required for data transfer to the printer is reduced to less than 10/0.
Thus, more than
990/0 of the central processor time is available for program execution. This feature is available
only for the Type 222-3, -4, -5, and -6 Printers.
MAGNETIC TAPE UNITS
Magnetic tape is a compact and highly versatile medium for the storage of programs and
data files.
Two complete families of industry-acclaimed tape units are available with Series 200
processors (see Table 1-3): 1/2-inch tape units (10 types) transfer data at speeds ranging from
4,800 to 96,000 characters per second; three types of 3/4-inch tape units read/write from
32, 000 to 88, 800 characters per second.
The capability of processing nine-track, 1 /2-inch tape
is also provided.
1200 BPI Recording Density
The l200-bits-per-inch recording density (Feature 054) provides the Type 204B-9 Magnetic Tape Unit with the capability of reading and writing data at a density of 1200 bits per inch
1-8
#2-139
SEC TION I.
(bpi) on Dupont Crolyn magnetic tape.
SERIES 200 COMPONENTS
The 1200-bpi recording density enables the 204B-9 to
achieve a transfer rate of 144, 000 characters per second.
Table 1-2.
High-Speed Printers
222-1 (96 print positions)
650-1, 300 lines /minute
1
1
1
222-2 (108 print positions)
650-1, 300 lines /minute
1
1
1
222-3 (120 or 132 print
positions)
650-1, 300 lines/minute
1
222-4 (120 or 132 print
positions)
950 -1, 266 lines/minute
1
1
1
222-5 (120 or 132 print
positions)
450 lines/minute
1
1
1
222-6 (120 or 132 print
positions)
1
.
229 (120 or 132 print
positions)
1100 lines/minute
1
1
1
400 lines/minute
1
1
1
1
lRestricted to educational institutions.
Table 1-3.
Magnetic Tape Units
1 /2-Inch Magnetic Tape Units
204B-l
204B-2
7,200/20,000 characters/second
1-8
2
2
204B-3
204B-4
16,000/44,500 characters/second
1-8
2
2
204B-5
24,000/66,700 characters/second
1-8
2
2
204B-7
20, 000/28, 800 (or 7, 200/28, 800)
characters/second
1-8
2
2
204B-8
44, 500/64, 000 (or 16, 000/64, 000)
characters/second
1-8
2
2
204B-9
66, 700/96, 000 (or 24, 000/96, 000 or
66,700/144,000 or 96,000/144,000)
characters/second
1-8
2
2
204B-ll
204B-12
4,800/13,300 characters/second
1-4
2
2
204C-13
204C-14
28,800 characters/second
1-2
2
2
1-9
#2-139
· SECTION I.
SERIES 200 COMPONENTS
Table 1-3 (cont).
Magnetic Tape Units
3/4-Inch Magnetic Tape Units
204A-1
32,000 characters/second
1-4
2
2
204A-2
64,000 characters/second
1-4
2
2
204A-3
88,800 characters/second
1-4
2
2
DISK PACK DRIVES
Honeywell disk pack drives combine the desirable features of magnetic tape and magnetic
disk storage -
unlimited shelf storage and fast random access.
This is made possible by the
use of removable disk packs which may be recorded an, stored indefinitely (like magnetic tape),
and rapidly reinserted in an on-line drive.
Table 1-4.
The various disk pack drives are listed in Table, 1 .. 4.
Disk Pack Drives
258
4. 6 minion characters
208, 333 characters /
second
1 ... 8
1
2
259
9. 2 million characters
208, 333 characters /
second
1-8
1
2
259A 1
9. 2 million characters
147, 500 charactersl
second
1 .. 8
1
2
259B
9. 2 million characters
147,500 characters/
second
1-8
1
2
lUsed in systems with Type 201 and 201-1 Central Processors.
DISK FILES
The Iioneywell disk files are fixed-disk storage devices which provide an extremely high
on-line storage capacity (see Table 1-5). A single disk file subsystem's capacity may amount
to over 1. 2 billion characters.
Anyon-line data track can be located in a maximum time of 120
m.illiseconds, and data can be transferred at a rate of 190, 000 characters per second.
1-10
#2-139
SECTION I.
SERIES 200 COMPONENTS
Table 1-5.
Disk Files
261
150 TIlillion character s
190,000 characters/second
1-8
2
262
300 TIlillion characters
190,000 characters/second
1-4
2
RANDOM ACCESS DRUMS
The Series 200 druTIl storage capability features a druTIl control which can direct froTIl one
to eight magnetic druTIls, each capable of storing 2.6 million characters of inforTIlation (see
Table 1-6).
ters.
Thus, a single druTIl subsysteTIl can have a total capacity of over 20 TIlillion charac-
Any record stored on the druTIl can be located in 27 TIlilliseconds (average) and can be
transferred at the rate of Ill, 000 character s per second.
Table 1-6.
270A -1 2.6 TIlillion characters
through
270A-8
RandoTIl Access DruTIl Units
111,000 characters/second
1-8
2
1
HIGH-SPEED DRUMS
The high-speed druTIls are fixed-head storage devices which offer high speed performance
with fast access tiTIle.
Up to four devices can be -operated with a single drum control, and thus
a control's capacity may amount to over 16 .. 8 million characterso
Any record stored on the
drums can be located in 8.6 milliseconds (average).
Angular Position Indicator
Features 072 and 073 (Angular Position Indicator) proyide for optimum addressing of the
Type 265/266 and 267 High-Speed Drums, respectively.
Information is provided at any given
time as to the current drum position relative to 360 degrees of rotation.
Under heavy load con-
ditions with many demands waiting to be executed, the average access time of the druTIls may be
substantially reduced.
1-11
#2-139
SECTION I.
SERIES 200 COMPONENTS
Table 1-7.
High-Speed Drums
4. 2 million characters
300,000 char./second
1-4
1
2
4. 2 million character s
1,200,000 char./second
1-4
1
2
1 Used only in systems with Type 1251, 2201, or 4201 Central Processors.
2Used only in systems with Type 4201 Central Processors equipped with the High-Speed Third
Sector (Feature 4215).
PAPER TAPE EQUIPMENT
Paper tape is an ideal medium for recording data which originates at locations distant from
a central Series 200 installation and, as such, becomes particularly significant in data communication networks.
A variety of standard commercial codes may be used with this relatively
inexpensive medium.
Two paper tape devices are offered in Series 200 (see Table 1-8).
Table 1.,.8.
Paper Tape Equipment
Paper Tape Reader
600 characters / second
1
2
1
Paper Tape Punch
120 characters/second
1
2
1
The total power requirement for the combination of a 209-2 reader and a 210 punch is 3 unit loads
DATA COMMUNICATION EQUIPMENT
The immediate and automatic response to an external interrupt by the Series 200 processor
is described on page 1-3. A common source of external interruption is a communication control.
These controls allow the Series 200 processor to communicate with distant locations (e. g.,
branch offices, warehouses, etc.) by receiving and transmitting data over toll and leased lines.
Four kinds of communication controls are available in Series 200: (1) two types of single-channel
controls transfer entire messages over single lines; (2) three types of multi-channel controls
transfer messages character-by-character over as many as 63 different lines; (3) two types of
message-mode multi-channel controls transfer entire messages over a maximum of 63 lines;
and (4) two types of controls serve as interfaces with the Air Force A UTODIN network. All
1-12
#2-139
SECTION I.
SERIES 200 COMPONENTS
controls are adaptable to a broad selection of lines, speeds, and terminal devices.
One such
terminal device is Honeywell's Data Station (see Table 1-9).
Table 1-9.
Data Communication Equipment
Device
Communication Controls
281-1
and -2
Single-Channel Controls
Up to 5, 100 character s / 1 line
second
11
2
286 -1,
-2, an
-3
Multi -Channel Controls
Up to 300 characters /
second/line
1-63 lines
2
2
286-4,
_52
Message-Mode, MultiChannel Controls
Up to 7, 000 characters/ 1-63 lines
second (all lines)
2
2
287
A UTODIN Communication Control
Up to at least 4, 800
baud
1 line
2
2
287-1
(USASCII) AUTODIN
Communication Control
Up to at least 4, 800
baud
1 line
2
2
Remote Terminal Devic
288-1
Data Station Central
Control
120 characters/second
n/a
n/a
n/a
Data Station Central
Control
300 charac1:ers / second
n/a
n/a
n/a
289-2
Data Station Page
Printer & Keyboard
10 characters / second
n/a
n/a
n/a
289-2A
Keyboard
10 characters/second
n/a
n/a
n/a
289-3
Data Station Page
Printer & Keyboard
40 characters / second
n/a
n/a
n/a
289-4
Data Station Paper
Tape Reader
120 characters / second
n/a
n/a
n/a
289-5
Data Station Paper
Tape Punch
120 characters/second
n/a
n/a
n/a
289-7
Data Station Card
Reader
143 characters/second
n/a
n/a
n/a
289-8
Data Station Optical
Bar Code Reader
50 characters / second
n/a
n/a
n/a
Remote Line Printer
300 characters / second
n/a
n/a
n/a
288_3
289-9
3
3
1The Type 281-2 control requires two unit loads.
2Not available for use on the Type 201 and 201-1 Central Processors.
3Both required for operation of either unit.
1-13
#2-139
SECTION I.
SERIES 200 COMPONENTS
A major requirement of many communication networks (e. g., inquiry handling or ITlessage
switching applications) is fast access to a stored file.
Files may sometimes be stored in main
memory, but for large files main memory storage is economically unfeasible.
File storage units
(i. e., the disk pack drives or drum units) fulfill the requirements of these applications.
A typical data communication network is shown in Figure 1-7.
The pertinent components
of this system are:
(1) a Type 201-2 processor; (2) a Type 259 Disk Pack Drive; (3) a Type 281
1
Communication Control; (4) two data sets ; and (5) a Honeywell Data Station, the remote terminal
device.
Two particular devices connected to the Data Station are used in this example: a key-
board by which the inquiry is transmitted to the central processor, and a page printer which
prints the answer to the inquiry in readable form.
CONSOLE EQUIPMENT
Characteristics of the Type 220 consoles, described previously on page 1-2, are listed
in Table 1-10.
Table 1-10.
Console Equipment
Typing Speed (input); or
10 char. /sec. (output)
VISUAL INFORMATION PROJECTION DEVICES
Cathode-ray tube (CRT) display units - for businesses requiring instantaneous visual access to data stored in computer files -
are available to the Series 200 user.
These devices
operate on line to the computer, either locally via direct physical connection or from remote
locations via communication facilities.
As shown in Table 1-11, the display devices provide a
variety of keyboard arrangements: numeric, numeric/block alpha, and typewriter.
An 8-bit
code (7-bit USASCII plus parity) is used for synchronous transmission and a 10-bit code (7-bit
USASCII plus parity and start and stop bits) for asynchronous transmission.
1
A data set is required to convert the data signals used by the communication control to signals
acceptable for transmission over communication lines.
1-14
#2-139
SEC TION 1.
TYPE 288-1
DATA STATION
CENTRAL CONTROL
SERIES 200 COMPONENTS
1.
CustoIner inquiry is typed on keyboard in
form of a coded message.
2.
Message signals are converted to a form
acceptable for transmission line.
3.
Message is transmitted over transmission
line.
4.
Message signals are reconverted.
5.
Control generates interrupt signal and transfers incoming message to preassigned
memory location as directed by interrupt
service routine.
6.
Store d interrupt service routine interprets
message and issues instructions to read and
update the customer 's record in a file stored
in Type 259 Disk Pack Drive.
7.
Type 257 control directs the execution of the
instl'uctions issued by the stored interruptprogram.
8.
Customer's record is read and updated according to instructions. Record is read into
preassigned location in interrupt routine
(in central processor memory), from which
the answer to the inquiry is sent back to the
Data Station. (Answer to inquiry is printed
by page printer. )
PRINTER
DATA SET
DATA SET
TYPE 281
COMMUNICATION
CONTROL
TYPE 201- 2 PROCESSOR
TYPE 257
DISK
PACK
DRIVE
CONTROL
TYPE 259
DISK PACK DRIVE
Figure 1-7.
Customer Inquiry Handling via Typical Communications Network
1-15
#2-139
SECTION I.
Table 1-11.
303
Display Station
(Typewriter keyboard)
311
Display Station (IS-key
block numeric keyboard)
312
Display Station (43-key
numeric /block alpha
keyboard)
304
Display Station (Navcor
electronic typewriter
keyboard)
317
Display Station
(no keyboard)
318
Display Station
(no keyboard)
SERIES 200 COMPONENTS
Vi sual Information Projection Devices
1200-2400 baud
12 for
basic control, plus
12 for
each expansion
module
n/a
n/a
TELLER TERMINAL EQUIPMENT
Honeywell Teller Terminal equipment permits more efficient banking procedures through
on-the-counter, on-line processing .of all teller-assigned transactions.
The Type 370 Teller
Terminal is used by the teller for all his bank transactions, and a remote transceiver transmits
transaction information between the Type 370 and the computer.
Data is transmitted asynchro-
nously via a modified USASCII-type code permitting combinations of similarly coded peripheral
devices to share common networks.
parity bit, and a stop bit.
This code consists of a start bit, seven data bits, an 0dd
Specifications of the Type 370 are shown in Table 1-12.
Table 1-12.
370
Teller Terminal
Teller Terminal Equipment
120 characters/second 1, 2, 6, or
10
not
applicable
not
applicable
ADDITIONAL PERIPHERAL DEVICES
A number of other peripheral devices are included in the Series 200 line.
General charac-
teristics of these devices are shown in Table 1-13.
1-16
#2-139
SECTION I.
SERIES 200 COMPONENTS
Table 1-13. Additional Peripheral Devices
212
On-Line
Adapter
120, 000 characters I second
1
1
1
212-1
Central Processor Adapter
167, 000 characters / second
1
2
2
213-3
Interval Timer
Range: 100 microseconds to
200 milliseconds
1
1
1
213-4
Time -of-Day
Clock
Range: 00:00:00.0 to
23 :59:59.9 (hours,
minutes, seconds,
and tenths of seconds)
1
1
1
232
MICR ReaderSorter and
Control
Up to 600 documents /minute
1
1
1
233-2
MICR ReaderSorter Control
for Burroughs
BI03
Up to 1,560 documents/minute
1
1
1
234
Plotter Control
for Calcomp
Plotters
Plotting Speed: Up to 300
increments per second (in any
of eight directions)
1
1
1
235
Optical Journal·
Reader Control
26 or 52 line s / second
1
1
1
237
Bill Feed
Printer Control
600 lines /minute; or up to 800
cards/minute
1
2
2
PERIPHERAL DATA TRANSFER OPERATION
One of the major features of Series 200 is the degree of peripheral simultaneity that can be
achieved by the various processors.
The Model 200 processors (Types 201, 201-1, and 201-2)
and the Type 1201 processor can perform up to four peripheral operations simultaneously; the
Type 1251, 2201, and 4201 processors may perform as many as six, eight, and sixteen simultaneous peripheral operations, respectively.
While all these operations are being executed, the
central processor continues its internal processing.
The ability to perform simultaneous periph ..
eral operations derives from an internal unit of the central processor - the input/output traffic
control - which guarantees a peripheral control access to main memory when data is to be transferred.
The manner in which the traffic control does this is explained in Section II.
The data
path used by the traffic control to transfer data (see Figure 1-8) is described below.
Peripheral Addresses and Unit Loads
When installed in a Series 200 computer system, peripheral controls (and their associated
1-17
#2-139
SECTION 1.
SERIES 200 COMPONENTS
devices) are permanently connected to the system.
Each control is assigned one or two ad-
dresses, depending on the number of directions in which it can transfer data.
It is by these
peripheral addresses that the controls are designated in input/output instructions.
For example,
a card reader and its associated control can transfer data in only one direction - into the central
processor.
The reader control is therefore assigned one address by which it is always designated
in an instruction.
directions -
A combination card reader/card punch and control can transfer data in two
into and out of the processor.
It is thereby assigned two addresses:
one address
is used to specify an input (card read) operation, while the other is used to specify an output
(card punch) operation.
CENTRAL PROCESSOR
'"
PERIPH.ERAL
INTERFACE
Figure 1 .. 8.
Basic Input/Output Data Path
The number of peripheral controls which a Series 200 processor can accommodate depends
upoh four factors:
(1) the number of "unit loads" of power required by the controls to be con-
nected; (2) the number of unit loads of power available from the processor; (3) the number of
peripheral addresses required to operate the controls; and (4)the number of address assignments
which the processor provides.
A peripheral control may require either one or two unit loads of
power and either one or two addresses.
The numbers of unit loads and address assignments
available with each Series 200 processor are shown in Figure 1-9.
The numbers of unit loads and
address assignments required by each peripheral control are shown in the preceding summary
tables of the peripheral equipment (Tables 1-1 through 1-13).
Read/Write Channel
Note that the permanent connection established in Figure 1-8 is incomplete: there is no
connection across the peripheral interface.
The input/output data path is completed by one or
more "read/write channels, " inserteq in the data path when the input/output instruction is executed.
{More than one read/write channel is sometimes necessary in order to accommodate the
1-18
#2-139
SEC TION I.
SERIES 200 COMPONENTS
high data transfer rates of some devices.) A read/write channel is not permanently connected
to any peripheral control but is assigned by the programmer to specify the data path between a
control and the processor.
TYPE
4201
2201
1251
1201
201-2
201-1
201
48
OPTIONAL
Figure 1-9.
Address Assignments and Unit Loads Available in Series 200 Processors
When the program:mer codes an input/output instruction, he specifies among other things
the address of the peripheral control that is to s'end or receive data and the read/write channel{s)
over which the data transfer is to take place.
When the instruction is executed, the specified
read/write channel is automatically inserted in the peripheral interface.
For example, Figure
1-10 shows the data path formed during the. execution of an input/output instruction in which the
programmer specifies that the card reader control is to transfer data over read/write channel 2
(RWC 2).
operation.
The specified channel remains in the interface only for the duration of the card read
When the data transfer terminates, RWC2 is automatically removed from the inter-
face and is available for reassignment by another instruction.
Read/write channels are the key to the achievable sim1~ltaneity in a Series 200 model: the
number of read/write channels associated with a particular processor determin~s the number of
peripheral operations that can be performed simultaneously by that processor (see Figure 1-6).
CENTRAL PROCESSOR
Figure 1-10.
Data Path During Card Read Operation
1-19
#2-139
SECTION 1.
SERIES 200 COMPONENTS
OPTIONAL FEATURES
Table 1-14 lists the various features that can be added to the Series 200 processors described in this manual.
This table illustrates the realistic design principle of Series 200: a
Series 200 model can be specialized to meet the individual user's application; the application is
not cornpromi sed to meet the de sign of the model.
Certain features optional with some processors are standard with other larger types.
This is also part of the realistic approach to system development.
Particularly significant is
the fact that specialization of a Series 200 model can occur at any time (not just at installation
time) to meet any increased workload or applications shift that might occur.
A summary description of the optional features is given below.
Table 1-14.
Series 200 Optional Features
16 ADDITIONAL UNIT LOADS & ADDRESS
ASSIGNMENTS & 4 ADDITIONAL RWC'S
1116
16 ADDITIONAL UNIT LOADS & ADDRESS
ASSIGNMENTS & 8 ADDITIONAL RWC'S
1118
EXTENDED MULTIPROGRAMMING &
8-BIT TRANSFER
1120
EXTENDED MULTIPROGRAMMING &
8-BIT TRANSFER
n/a
n/a
n/a
1I21
EXTENDED MULT~PROGRAMMING &
8-BIT TRANSFER
n/a
n/a
n/a
4214B
TWO ADDITIONAL BUFFERED I/O
SECTORS
n/a
n/a
n/a
n/a
n/a
n/a
n/a
421
1¢iJ?'£1 ' OPTIONA L
1-20
NOT AVAILABLE
#2-139
SECTION 1.
SERIES 200 COMPONENTS
ADVANCED PROGRAMMING
Two Advanced Prograrll"Ining Features increase the basic instruction repertoire of the
Model 200 processors ..
Feature 011 is available with the Type 201 and 201-1 processors, and
Feature 010 can be added to the Type 201-2 processor.
Each feature includes the following
capabilities (see Table 1-15):
1.
Additional program instructions.
2.
The ability to modify instruction addresses via indexed or indirect addressing
(described in Section IV).
-
3.
A "read reverse" capability with magnetic and paper tape units.
Table 1-15.
Model 200 Advanced Programming Feature
Program Instructions
1.
2.
3.
4.
5.
6.
7.
8.
9.
Program Instructions
Zero and Add
Zero and Subtract
Branch if Character Equal
Change Sequencing Mode
Change Addressing Mode (expanded version)1
Extended Move
Move and Translate
Branch on Character Condition (expanded
version)
Branch on Bit Equal
1.
2.
3.
4.
5.
6.
7.
8.
9.
Address Modification
1.
2.
Indexed addres sing via 6 or 15 index
registers 3
Indirect addres sing
Zero and Add
Zero and Subtract
Branch if Character Equal
Change Sequencing Mode
Change Addressing Model
Extended Move
Move and Translate
Branch on Character Condition (expanded version)
Load Control Registers 2
Address Modification
1.
I
2.
Read Rever se
Indexed addressing via 6 or 15 index
registers 3
Indirect addressing
Read Reverse
ny Model 200 processor can read paper tape and 1 /2-inch magnetic tapes in a reverse directi
d transfer the information to the main memory in such a manner that it is oriented in the
rma1 (forward) direction.
IThe Change Addressing Mode instruction is available in Type 201 or 201-1 processors which
include either the Advanced Programming Feature or a main memory capacity greater than
4, 096 characters. In the Type 201-2 processor, the use of this instruction with 2- and 3character addressing is standard; however, its use with 4-character addressing and/or itemmark trapping requires the presence of the Advanced Programming Instructions.
2 The Load Control Registers instruction, optional with the Type 201 and 201-1 processors, is
included in the standard instruction repertoire of the Type 201-2 processor.
3 The Type 201-1 and 201-2 processors with the Advanced Progranuning Feature contain 6 index registers in the three -character addressing mode and 15 index registers in the four-character mode. The Type 201 processor with the Advanced Programming Feature contains six
index registers, regardless of addressing mode.
1-21
#2-139
SECTION 1.
SERIES 200 COMPONENTS
PROGRAM INTERRUPT
This feature, whose basic functions are described on page 1-3, is an optional feature for
the Type 201 processor and is standard for all other processors described herein.
A detailed
description of program interruption, including conditions which must be present for an interrupt
to occur, processor activities which are automatically performed when the interrupt takes place,
and the programming of interrupt service routines, is given in Appendix D.
EDIT INSTR UCTION
A comprehensive instruction -
Move Characters and Edit -
is optionally available with
the Model 200 processors and is a standard feature with the Type 1201, 1251, 2201, and 4201
processors.
Processed information is edited before being converted to an output medium (e. g.,
a printed document) by the suppression of unwanted characters and symbols and the insertion of
identifying symbols such as the dollar sign, decimal point, and asterisk.
The Move Character s
and Edit instruction is described on page 8-104.
ADDITIONAL READ/WRITE CHANNELS, UNIT LOADS, AND ADDRESS ASSIGNMENTS
As explained above, the nUITlber of peripheral operations that can be performed simultaneously by a processor depends on the number of read/write channels available, and the number
of peripheral devices connectable to a processor depends on the number of unit loads and address
assignments associated with the processor.
Four optional features allow a user to increase his
processor's peripheral flexibility by adding the following eleITlents:
1
1.
Feature 015 - Eight additional unit loads for a Model 200 proce s sor. (The
address assignITlents required to specify the additional peripheral controls
enabled by this feature already exist in the basic 200 processors.)
2.
Feature 016 - One additional (auxiliary) read/write channel for a Model 200
processor. (Auxiliary read/write channels are described on page 2-16.)
3.
Feature 1115 - A second "I/O sector" for the Type 2201 processor. 1 This
sector consists· of four additional read/write channels, 16 additional unit
loads, and 16 additional address assignments, thereby matching the peripheral capabilities of the basic I/O sector.
4.
Feature 1116 - A third I/O sector for the Type 4201 processor. 1 (The
basic 4201 proce s sor contains two I/O sector s.) The optional sector consists of four additional read/write channels, 16 additional unit loads, and 16
additional address assignments. In addition to the third sector, Feature 1116
includes two additional read/write channels to be used with sector 1 and two
additional channels to be used with sector 2. Feature 116 is described in
Appendix H.
5.
Feature 4214A and 4214B - Provides the Type 4201 processor with buffered
I/O sectors for those applications where additional computer time or a higher
input/output transfer capability is required. Feature 4214A requires the
installation of Feature 1116, and Feature 4214B requires the installation of
Feature 4214A. These features are discussed in Appendix H.
An I/O sector consists of three elements: 4 read/write channels, 16 unit loads, and 16 address
assignments.
#2-139
1-22
SECTION I.
6.
SERIES 200 COMPONENTS
Feature 4215 - A high-speed third sector for the Type 4201 proces sor. This
allows connection of I/O peripheral devices with transfer rates exceeding
500,000 characters per second to the third sector. Featur,e 4215 requires
the installation of Feature 1116. These features are discussed in Appendix H.
STORAGE PROTECT
Two Storage Protect Features, identical in nature, are offered for the Type 1201/1251, and
2201 processors as Features 1114 and 1117, respectively.
These features allow a programmer-
specified portion of the main memory (and the contents thereof) to be shielded from accidental
alteration by programs running concurrently in the memory.
An attempt to violate the protec-
tion of this area results in an "internal" processor interruption.
The program or programs
running in the protected memory area have 15 additional index registers at their disposal; these
registers can also be used by programs in the unprotected (or "open") memory area if desired.
The Storage Protect Features are described in Appendix E.
EXTENDED MULTIPROGRAMMING AND 8-BIT TRANSFER
The processing capabilities of the Models 1200, 1250, 2200, and 4200 are greatly extended
by the addition of the Extended Multiprogramming and 8-Bit Transfer Features.
These amplified
capabilities are available as Features 1120, 1121, and 1118 for the Models 1200/1250, 2200,
and 4200, respectively.
Features 1120 and 1121 require that the Models 1200/1250, and 2200 be
equipped with Storage Protect (Features 1114 and 1117, respectively); the Storage Protect capabilities are automatically included in Feature 1118 for the Model 4200.
In addition to the capa-
bilities supplied by the Storage Protect Features, extended multiprogramming provides storage
protection with memory address relocation, interrupt masking, and instruction timeout.
The 8-
bit transfer capability gives the Models 1200, 1250, 2200, and 4200 increased flexibility by allowing either 8 -bit or 6 -bit information transfers between certain peripheral controls and main
memory.
The Extended Multiprogramming and 8-Bit Transfer Features are described in detail
in Appendix G.
SCIENTIFIC UNIT
The scientific unit adds 14 scientifically oriented instructions to the Series 200 repertoire.
The two functionally identical unit s -
Feature 1100A (available with the Type 1201, 1251, and
2201 processors) and Feature 1101 (for the Type 4201) -
are summarized in Appendix F.
FEATURE 0191
Feature 0191, which is available on the 1201, 1251, and 2201 processors and standard on
the 4201 processor, enhances the instruction repertoire of the processor and affords increased
compatibility with competitive equipment.
This feature provides two additional instructions
Move or Scan (MOS) and Table Lookup (T LU) -
and also includes the
1-23
"s"
(Special) mode of
#2-139
SECTION 1.
processing.
SERIES 200 COMPONENTS
The "S" mode of processing, which is implemented by the variant character of the
Change Addressing Mode (CAM) instruction, enables the processor to manipulate the Add, Subtract, Zero Add, Zero Subtract, and Branch if Character Equal instructions in a special way.
These instructions are described in Section VIII of this manual.
The Move or Scan and Table
Lookup Instructions, which are assembled by Easycoder Assembler D, are also discussed in
Section VIII.
1-24
#2-139
THE CENTRAL
PROCESSOR
A Series 200 central processor is logically divided into five basic units (see Figure 2-1):
a main memory, a control memory, an arithmetic unit, a control unit, and an input/ output
traffic control.
MAIN MEMORV
Figure 2-1.
CONTROL MEMORV
I/O
TRAFFIC
CONTROL
Logical Division of Series 200 Central Processor
MAIN MEMORY
The main memory contains from 2, 048 to 524, 288 character locations of magnetic core
storage which are used to store program instructions and data during a program run (see
Figure 2-2).
Every character location is identified by a unique numeric address.
This means
that an instruction can designate the exact storage locations that contain the data needed for a
particular operation.
2-1
#2-139
SECTION II.
THE CENTRAL PROCESSOR
MAIN MEMORY
Figure 2-2.
Main Memory Functions
Figure 2-3 shows one character position of memory with the name of each core shown to the
right.
Each core can be individually magnetized to represent either a one or a zero, depending
upon its polarity.
Moving from bottom to top in Figure 2-3, the first six cores are used for data
storage, the seventh and eighth cores are used to define the limits of storage areas (these two
cores are frequently referred to as "punctuation" bits), and the ninth core is used for parity
checking.
Figure 2-4 shows how typical numeric, alphabetic, and special characters are stored in the
main memory.
Shaded circles represent cores containing I-bits.
Bits 1, 2, 4, and 8 in each
character position can be combined to represent the decimal values zero through nine.
four-bit representation of decimal numbers is known as binary-coded decimal (BCD).
This
Alphabetic
and special characters are represented by a combination of the numeric (1, 2, 4, and 8) and the
A and B cores.
The A and B cores correspond to zone punches on cards: the A bit represents a
12-punch, the B bit represents an II-punch, a combination of the A and B bits represents a 0punch.
A listing of the main memory formats for all valid Series 200 characters appears in
Appendix B.
The word-mark bit (WM) is used to define logical storage fields in the memory.
Informa-
tion is rarely stored in the memory as single, independent characters; instead. adjacent character positions are usually grouped to form storage fields.
As described in Section III, the word-
mark bit is instrumental in defining the size of such fields.
2-2
#2-139
SECTION II.
THE CENTRAL PROCESSOR
PARITY BIT (P)
ITEM-MARK BIT (1M)
}
B
I
PUNCTUATION BITS
WORD-MARK BIT (WM)
T
B BIT}
o
C
N
F
I
ZONE BITS
A BIT
G
8 BIT
4 BIT
U
DATA BITS
R
A
NUMERIC
BITS
T
I
o
2 BIT
N
1M
WM
0 000 0 0 0 0
00000000
Booooe~~o
Aoooeoeoo
800eOO~E>O
40eoo~oo~
2000EJOeOG
00800800
I BIT
Figure 2 -3.
Figure 2 -4. Representation of Characters
in Magnetic Core Storage
One MeIllory Position
Consecutive storage fields are frequently grouped together to forIll a unit of inforIllation
called an iteIll.
As its naIlle iIllplies, the iteIll-Illark bit (1M) is used to define the size of an
iteIll in the main IlleIllory (see Section III).
A unit of inforIllation that is to be transferred between the Illain IlleIllory and a peripheral
device is called a record.
A record can be of any length, froIll one character up to virtually the
IllaxiIlluIll nUIllber of characters in the IlleIllory.
used in
defi~ing
Both the word-Illark and iteIll-Illark bits are
the size of a record (see Section III).
The parity bit (P) is used in conjunction with an autoIllatic error-detection technique
known as parity checking.
odd nUIllber of I-bits.
Every character Illust be represented in the central processor by an
(Punctuation bits are excluded froIll this rule except in the Type 4201.)
Whenever a character is Illoved froIll one location to another it is autoIllatically checked to
deterIlline if an odd nUIllber of data I-bits has been Illoved.
In Figure 2-4, the characters 0, 9,
B, M, and { are represented by an even nUIllber of ones in the data bit positions.
Circuitry
within the central processor autoIllatically adds a one in the parity bit positions of these
characters to provide the required odd bit count.
MEMORY CYCLE
The tiIlle interval required by a processor to read or write the contents of a unit location
is terIlled meIllory cycle tiIlle.
For the processors described in this Illanual, IlleIllory cycle tiIlle
ranges from 2 Illicroseconds (Model 200) down to 750 nanoseconds (Model 4200).
2-3
#2-139
SECTION II.
THE CENTRAL PROCESSOR
MAIN MEMORY IN THE TYPE 4201 PROCESSOR
The main memory of the Type 4201 processor consists of from one to four modules of
core memory and a memory controller (see Figure 2-5).
Each module is four characters in
width and either 16,384 or 32,768 four-character groups in length.
either 65, 536 or 131,072 characters.
Thus, a module contains
Data storage capacities of main memory range from
131,072 to 524,288 characters.
MEMORY MODULES (/-4)
Figure 2-5.
Type 4201 Memory Subsystem
Table 2-1 below shows the memory configurations available with the Type 4201 processors.
Table 2-1.
Memory Configurations for Type 4201 Processors
4201-3
131,072
4201-4
196,608
4201-5
262, 144
420l-5A* (2-way
inte r Ie a ving )
262, 144
4201-6
327,680
4201-7
393,216
4201-8
458,752
524,288
(4-way
interleaving)
*Memory addresses are interleaved across modules in these
processors.
4201-9*
2-4
#2-139
SECTION II.
THE CENTRAL PROCESSOR
Memory Acce s s
The 4201 processor always reads or writes the contents of four character locations at a
time; such a four-character grouping is termed a "word."
Thus, the Model 4200 has an
effective memory cycle time of 750/4 or 188 nanoseconds per character.
Processing Unit
Although the 4201 processor always reads or writes a four-character word every memory
cycle, the portion of the accessed word actually available for processing, called a "processing
unit," varies from one to four characters, depending upon the operation being performed.
The
processing unit for a move instruction is up to four characters, whereas arithTIletic and I/O instructions process one character at a time.
MeTIlory Controller
The meTIlory controller provides maximuTIl siTIlultaneity of memory operations by its
ability to transfer data to or from memory TIlodules siTIlultaneously.
This is accomplished
by providing a set of read/write electronics for each memory module, so that access can be
made to a module independently of all other modules.
This ability allows internal processing
and input/ output operations to proceed independently and simultaneous,ly.
Simultaneous acce s s
occurs as long as the central processor and the I/O controller request access to different
modules of memory.
Whenever their requests are for the same module, the memory controller
resolves the conflict by giving priority to the input/output controller.
When memory is addressed, a 4-character group containing the addressed character is
delivered to either the central processor or the I/O controller.
The delivery of four characters
serves to significantly reduce the number of memory references for TIlany operations and greatly
increases the operating speed of the system.
Interleaved Addressing
In order to achieve optimum utilization of memory, an interleaved addressing scheme has
been incorporated in two Model 4200 central processors (Types 4201-5A and -9).
The use of the
interleaved memory permits faster program execution by allowing multiple access to separate
modules of memory to proceed simultaneously.
This method of addressing is accomplished by
assigning successive addresses to different modules so that a program written in a normal
sequential manner will address different modules as it proceeds.
For example, in the Type
4201-9 Central Processor, there are four rneTIlory TIlodules which perTIlit 4-way interleaving
of accesses.
With four modules, addresses 0, 1, 2, 3 are assigned to the first module; 4, 5, 6,
7 are assigned to the second module, etc. (see Figure 2-6).
2-5
#2-139
SECTION II.
MODULE I
THE CENTRAL PROCESSOR
MODULE 2
MODULE 3
20
21
22
23
24
25
26
27
30
0
1
2
3
4
5
6
7
10
MODULE 4
37
11
12
13
14
15
16
17
NOTE: NUMBERS WITHIN MEMORY MODULES
iNDICATE ADDRESSES (OCTAL) OF
CHARACTERS IN MEMORY
Figure 2-6.
Model 4200 Memory Interleaving {Type 4201-9 Central Processor}
In addition, interleaved addressing further increases system performance by allowing the
central processor to overlap many of its memory operations.
de sign of the addre s sing circuitry of the Model 4200.
This is accomplished by a unique
Although 750 nanoseconds are required
to cycle main memory, the addressing and data path circuitry of the processor is used only for
a portion of the cycle time (approximately 500 nanoseconds).
Therefore, the addressing
circuitry is available for another memory access before the first access is completed.
By
interleaving, the instructions and operands will have been distributed among the available
modules; therefore, the central processor is able to overlap successive fetches of both operands
and the characters within an instruction.
Parity Check
Unlike the other Series 200 processors, the 4201 includes the punctuation bits in its parity
check.
Whenever a character is moved from one location to another, it is automatically checked
to determine if an odd number of I-bits in the data and punctuation positions has been moved.
CONTROL MEMORY
The control memory is a high-speed storage unit consisting of up to 57 control registers.
(The number of registers actually available depends on the system configuration.) Normally,
control registers contain the addresses of instructions and data being processed during a program
run.
One such register, called the A-address register, is illustrated in Figure 2-7.
In this
example, the A-address register contains an address (206) designating a main memory location,
which in turn contains a unit of information (the decimal digit 7) to be added in the arithmetic unit.
2-6
#2-139
SECTION II.
THE CENTRAL PROCESSOR
REGISTER
CONTENTS OF
"'~/~I"·~'"
ADDRESS
CONTENTS OF
LOCATION 206
Figure 2-7.
Typical Control Register Function
In Series 200 processors, other than the Type 4201, that do not include the Scientific Unit
(Feature 1100A or 1101), each control register is only as large as it need be to contain the
largest, or "highest," main memory address in the user's processor.
Thus, a processor whose
main memory capacity i.s 8,192 characters contains control memory registers which are each
13 bits long (13 bits allows 8,192 addresses), while the control registers of a processor containing 131,072 characters of memory storage are each 17 bits long (see Table 2-2).
In a Type 4201
processor, all 19 control·register bits are active, regardless of main memory size.
When the
Scientific Unit is included in the system, each control register is 18 bits (three characters) long
(or 19 bits in the case of the Type 4201).
Table 2-2.
Size of Control Memory Registers (Models 200/1200/1250/2200/4200)
MAIN MEMORY
CAPACITY
(Characters)
4,096
8,192
16,384
32,768
65,536
131,072
262, 144
524,288
SIZE OF
CONTROL
MEMORY
REGISTER (Bits)
12
13
14
15
16
17
18
24>:~
*19 address bits and 5 parity bits.
Control registers can be addressed either by programmed instruction or from the operator's control panel or console.
For instance, an instruction can change the course of a pro-
gram by manipulating the contents of the control register that governs program sequence; the
operator can interrogate a control register to determine the exact location at which the program
has halted, etc.
When a register is addressed by programmed instruction, it is specified by
2-7
#2-139
SECTION II.
THE CENTRAL PROCESSOR
means of a variant character in the instruction.
A register is addres sed from the control panel
or console by using the register's octal address.
The functional name of each register and the
variant character which specifie s the register are listed in Table 2 -3.
ADDRESS REGISTERS
The A- and B-address registers, the two sequence registers, and the interrupt registers
are used to addre s s main memory during the loading and execution of instructions.
A detailed
description of these registers is presented in Section IV, "Addressing."
READ/WRITE COUNTERS
Data is transferred between the main memory and a peripheral device via a read/write
channel (described in Section I).
Associated with a read/write channel are two location counters:
a starting location counter and a current location counter.
When a peripheral transfer is to be
performed, the addre ss at which the transfer is to begin is stored in both counters.
Then, as
each successive character is transferred, the contents of the current location counter are
incremented by one so that when the transfer is completed, this counter contains the addre s s of
the character position immediately following the position that terminated the transfer, i. e., one
beyond the record-marked location (see Section III).
The availability of the starting and current addresses associated with an input/output area
greatly simplifie s the manipUlation of variable -length records.
Table 2-3.
Control Memory Registers
AAR
A-Addre ss Register
67
BAR
B -Addre ss Register
70
SR
Sequence Register
77
CLCI
Read/Write Channell
Current Location Counter
01
CLC2
Read/Write Channel 2
Cur re nt Loc ation Counte r
02
CLC3
Read/Write Channel 3
Current Location Counter
03
SLCI
Read/Write Channell -
Starting Location Counter
11
SLC2
Read/Write Channel 2 - Starting Location Counter
12
SLC3
Read/Write Channel 3 -
13
WRI
Work Register 11
WR2
Work Register 21
WR3
Work Register 3 1
Starting Location Counter
2-8
# 2 -139
SECTION II.
THE CENTRAL PROCESSOR
Table 2-3 (cent).
Centrol Memory Registers
FEATURE 010 or 011 (ADVANCED PROGRAMMING)
CSR
Change Sequence Register
64
FEATURE 012 (PROGRAM INTERRUPT)
EIR
66
CLCl'
Read/Write Channel I' - Current Location Counter
05
SLCI'
Read/Write Channel I' - Starting Location Counter
15
FEATURES IIOOA & 1101 (SCIENTIFIC UNITS)
ACO
Floating-Point Accumulator 0 2
ACI
Floating -Point Accumulator 12
AC2
Floating-Point Accum.ulator 22
AC3
Floating-Point Accum.ulator 32
REGISTERS STANDARD ON 4201, OTHERWISE NOT AVAILABLE
WR4
WR5
WR6
WR7
Work
Work
Work
Work
Register
Register
Register
Register
41
51
1
6
1
7
TURES 1114, 11
& 1118 (STOR
CLC4
CLC5
CLC6
CLC4'
Read/Write
Read/Write
Read/Write
Read/Write
Channel
Channel
Channel
Channel
4 - Current Location Counter
5 - Current Location Counter
6 - Current Location Counter
4' - Current Location Counter
21
22
23
25
SLC4
SLC5
SLC6
SLC4'
Read/Write
Read/Write
Read/Write
Read/Write
Channel
Channel
Channel
Channel
4 - Starting Location Counter
5 - Starting Location Counter
6 - Starting Location Counter
4' - Starting Location Counter
31
32
33
35
CLC5'
CLC6'
Read/Write Channel 5' - Current Location Counter
Read/Write Channel 6' - Current Location Counter
26
27
SLC5'
SLC6'
Read/Write Channel 5' - Starting Location Counter
Rea¢l./Write Channel 6' - Starting Location Counter
36
37
IIR
FEATUR
2-9
#2-139
SECTION II.
THE CENTRAL PROCESSOR
Table 2-3 (cont).
1
Control Mem.ory Registers
CLCS
CLC9
Read/Write Channel S - Current Location Counter
Read/Write Channel 9 - Current Location Counter
00
20
SLGS
SLC9
Read/Write Channel S - Starting Location Counter
Read/Write Channel 9 - Starting Location Counter
10
30
CLCS'
CLC9'
Read/Write Channel S' - Current Location Counter
Read/Write Channel 9' - Current Location Counter
04
24
SLCS'
SLC9'
Read/Write Channel S' - Starting Location Counter
Read/Write Channel 9' - Starting Location Counter
14
34
CLC2'
CLC3'
Read/Write Channel 2' - Current Location Counter
Read/Write Channel 3' - Current Location Counter
06
07
SLC2'
SLC3'
Read/Write Channel 2,' - Starting Location Counter
Read/Write Channel 3' - Starting Location Counter
16
17
These registers are available only to the processor and m.ust not be addressed by the program..
2These registers (accum.ulators) can only be addressed by the instructions included in Features
1100A or 1101 (see Appendix F).
ARITHMETIC UNIT
Arithm.etic and logical operations are perform.ed by a configuration of com.ponents com.m.only
referred to as the arithm.etic unit.
Basically, this unit is com.posed of an adder, capable of per-
form.ing both binary and decim.al arithm.etic, and two operand storage registers. 1 Each one of
these units is capable of storing a single six-bit character in processors sm.aller than the Type
4201.
The adder and operand storage registers in the 4201 processor can store four characters
2
at a tim.e. In general term.s, an arithm.etic or logic operation is perform.ed as follows (see
Figure 2-S):
1
1.
An instruction in the stored program. specifies the type of operation to be
perform.ed and the m.ain m.em.ory storage locations .of the data to be m.anipulated.
2.
The operands are transferred to the operand storage registers a character
(Models 200, 1200, 1250, and 2200) or a word (Model 4200) at a tim.e, beginning
with the rightm.ost character in each operand.
3.
In processors other than the 4201, each pair of characters (or, in the Model
4200, each pair of words) that enters the storage registers is com.bined in
the adder. The result is stored in the m.ain m.em.ory as specified by the program. instruction. If a carry is generated, it is stored in the adder and
com.bined with the next higher-order pair of characters.
4.
In the 4201 processor, the storage registers and adder are used in the sam.e
m.anner as in other processors, except when perform.ing address indexing or
The contents of these registers are not accessible to the program.m.er.
2When floating point is installed in the 4201, the adder and operand storage registers are extended to a 6 -character width in order to handle floating point operands
0
2-10
#2-139
SECTION II.
THE CENTRAL PROCESSOR
1
floating-point operations.
That is, operations other than these two types are
performed on a character-by-character basis. However, address indexing and
floating-point operations take advantage of the full width of the 4201 adder.
IX$XXXl }
t?0222J
Figure 2-8.
OPERAND.
STORAGE
REGISTERS
m}
AOOER
Data Flow Between Main Memory and Arithmetic Unit
CONTROL UNIT
The control unit is the hub of central processor activities (see Figure 2-9).
Its major
function is to select, interpret, and execute all of the instructions in the stored program.
In
carrying out these instructions, the control unit coordinates the various activities of receiving
data from input devices, transferring data within the central processor, and transferringprocessed data to the output units.
The main memory addresses used by the control unit in perform-
ing these tasks are stored in the registers of the control memory.
Figure 2-9.
Control Unit Activities
1
When floating point is installed in the 4201, the adder and operand storage registers are extended to a 6-character width in order to handle floating point operands.
2-11
#2-139
SECTION II.
THE CENTRAL PROCESSOR
INPUT /OUTPUT TRAFFIC CONTROL
The input/output traffic control is, as its name implies, the unit which regulates the flow
(or "traffic") of data transferred during input/output actiVities.
It works in. conjunction with the
central processor control unit to allocate central processor time to input/output operations and to
identify the peripheral controls which are to use that time to transfer data (see-Figure 2-10).
The I/O traffic control enables from 3 (Model 200 minimum) to
i6
(Model 4200 maximum)
simultaneou:s input/output operations to occur concurrently with the internal computations of the
processor.
In processors other than the 4201, this simultaneity is achieved by the traffic con-
trol's allocation of consecutive memory cycles to either peripheral controls or the cent,ral
processor.
In the Type 4201 processor, such allocation is not normally necessary, as independent
cycling of memory blocks allows absolute simultaneity between memory accesses for I/O and
computing operations (see page 2- 4).
Only when I/O and computing operations attempt to gain
access to the same memory block simultaneously does -the 4201 allocate memory cycles between
the two types of operations.
INPUT DEVICE
Figure 2-10.
Input/Output Traffic Control Activities
MEMORY CYCLE DISTRIBUTION
Every peripheral data transfer involves some factor which prevents the device being used
from transferring data at a rate comparable to that of the central processor.
is mechanical write head -
Usually this factor
moving a card through the read station or a magnetic tape or disk past the read/
although in data communication it is the bit rate of the communication line.
There-
fore, a peripheral device requires access to the central processor to transfer information to or
from the main memory during only a fraction of the time that the operation is proceeding.
2-12
The
#2-139
SECTION II.
THE CENTRAL PROCESSOR
periods in which the central processor is actually interrupted for data transfer are spaced over
the duration of the peripheral operation (see Figure 2-11).
L-..-_ _ _ _....L-
CENTRAL PROCESSOR TIME REQUIRED FOR DATA TRANSFER
Figure 2-11.
--L_ _ _ _ _-'--_ _ _ _- . . I
Data Transfer Intervals During One Peripheral Operation
When a peripheral operation is in progress but is not using main memory (the gray areas
in Figure 2-11), another peripheral control may gain access to the. main memory.
This second
memory acces s can in turn give way to a third acces s by another control before the original
operation requires access to the memory again, etc.
occur simultaneously with one another.
In other words, peripheral operations can
The periods of time in which peripheral controls do not
require main memory access to transfer data are given to the central processor for its internal
activities.
It is the function of the I/O traffic control to direct the sharing of main memory
cycles by the various peripheral devices and the central processor.
It was indicated on page 1-18 that in order for an I/O operation to proceed, the prog'rammer
must specify a read/write channel in the initiating peripheral instruction.
This read/write channel
completes the path between main memory and the control for the peripheral device being addressed.
Input/output sectors (see page 1-22}consist of unit power loads, address assignments, and read/
write channels. Type 1251 and2201 processors may be equipped with two I/O sectors. Where this
is the case, the read/write channel as signed to an operation must come from the sector to which the
device being addressed is connected.
Normally, this rule also applies to the 4201, which always
has at least two sectors, but in that processor it is also possible to reassign RWC's outside of
their "home" sectors by means of "sector escape codes" (see below).
The rate at which each peripheral control must transfer data over a programmer-assigned
read/write channel(s) depends on the mechanical characteristics of the device connected to the
control.
Thus, the transfer intervals shown in Figure 2-11 are spaced according to the device
being used.
For instance, the transfer rate for the disk pack drive is considerably faster than
that for the card punch; therefore, the disk pack drive will require access to the main memory
more frequently than the card punch.
for access to the main memory.
cycle should be used -
The I/O traffic control monitors and honors the requests
In processors other than the 4201, it decides how each memory
by a read/write channel or by the processor 2-13
as shown in Figure 2-13.
#2-139
SECTION II.
THE CENTRAL PROCESSOR
The traffic control offers consecutive ITleITlory cycles to read/write channels, one ITleITlory
cycle per channel.
If there is a deITland on a particular channel when the cycle is offered, the
channel is granted acces s to the ITlain ITleITlory for one cycle.
ter is transferred to or froITl meITlory.
During this cycle a single charac-
1£ the channel does not require the ITleITlory cycle, the
cycle is given to the central processor for internal data processing.
In the Type 4201 processor, if an I/O operation requires access to the saITle ITleITlory block
as the central processor, the I/O operation is given priority and the central processor stalls for
one ITleITlory cycle.
No interference (stall) occurs if the I/O operation and the central processor
are accessing different ITleITlory blocks (i. e., ITleITlory accesses are siITlultaneous).
NOTE:
In the Type 4201 processor, although a four-character word is ITloved in
one ITleITlory cycle during internal processor operations, a single six-bit
character is ITloved during input/output operations.
YES
GIVE THE PRESENT
MEMORY: CYCLE TO
THE RWC FOR
DATA TRANSFER
GIVE THE CYCLE TO
THE PROCESSOR FOR
MAIN MEMORY ACCESS
PROCEED TO
NEXT CYCLE
Figure 2 -12.
Logical Decision PerforITled by Input/ Output Traffic Control
The cyclic offering of ITlemory cycle s to read/write channels is shown in Figure 2 -13.
the
cha~nel
1£
being offered a ITlemory cycle is an optional channel (noted by an asterisk) that is not
present in the user's systeITl, the cycle is given unconditionally to the central processor.
that every fourth Model 1200 cycle is also given unconditionally to the processor.
1
Note
Note further
that ITlost channels available with the Models 200,1200, 1250, and2200 are offered main meITlory
acces s once every six ITlicroseconds. Input/output speeds up to 167, 000 characters per second can be
1
There is one exception to thi s statement: if a Model 200 doe s not include RWC I' (Feature 016),
the cycle is offered to RWC 1.
2-14
#2-139
SECTION II.
THE CENTRAL PROCESSOR
PROGRESSION OF TIME
(IN MICROSECONDS)
MODEL 200
MEMORY CYCLES:
RWC'S:
MODEL 1200
MEMORY CYCLES:
RWC'S:
MODEL 1250
MEMORY CYCLES:
SECTOR 1 RWC'S:
SECTOR 2 RWC'S:
MODEL 2200
MEMORY CYCLES:
SECTOR f RWC'S:
SECTOR 2 RWC'S:
MODEL 4200
MEMORY CYCLES:
SECTOR I RWC'S:
SECTOR 2 RWC'S:
SECTOR 3 RWC'S:
(*)cHANNEL AVAILABLE AS AN OPTIONAL FEATURE.
Figure 2-13.
Sym.bolic Representation of Input/Output Traffic Control l
1 This figure is not applicable to 4201 operations em.ploying channel transfer rates higher than the
minimum.
2 -15
#2-139
SECTION II._
THE CENTRAL PROCESSOR
maintained by accef:)sing memory at these intervals.
In processors other than 4201, transfer rates
higher than those attainable with a single read/write channel can be achieved by interlocking two
or more read/write channels, as described below.
Rather than interlocking RWC's, the Model 4200 traffic control offers variable numbers of
memory cycles per unit of time to each read/ write channel, depending upon the read/write channel
as signrnent code used in the instruction which initiates the operation.
From one to six cycles
are offered to a read/ write channel every 12 microseconds, giving channel data transfer capacities
ranging from 83, 300 to 500, 000 characters per second.
Effectively, then, the 4201 incorporates
variable -speed read/write channels.
PRIMARY AND AUXILIARY READ/WRITE CHANNELS
RWC1', RWC2', RWC3', RWC4', RWC5', RWC6', RWC8', and RWC9' are called auxiliary
read/ write channels becaus e of the manner in which they are granted acces s to the main memory
by the traffic control.
For instance, the Model 200 traffic control offers one cycle to RWC1, the
next cycle to RWC2, the next cycle to RWC3, the next cycle to RWCl "
the next cycle to RWC3, the next cycle to RWC1, etc.
the next cycle to RWC2,
In other words, memory cycle allocation
alternates between a primary channel and its auxiliary channel.
Read/write channels not accompanied by auxiliary channels (e. g., RWC's 2 and 3 in the
Model 200) are each guaranteed access to the main memory every six microseconds (giving a
transfer rate of 167,000 characters per second), as shown in Figure 2-13.
Primary channels
and auxiliary channels are each granted access every 12 microseconds, because access is
alternated between the two, thus providing a transfer rate of 83, 300 characters per second.
INTERLOCKING READ/WRITE CHANNELS
As indicated above, in order to achieve data transfer rates higher than those attainable
with a single read/write channel, it is necessary to interlock two or more read/write channels
in proces sors other than the 4201.
characters per second are possible.
In this manner, data transfer rates from 167, 000 to 500, 000
The same instruction which initiates the data transfer op-
eration specifies whether or not channels are to be interlocked.
When this procedure is used,
all of the cycles normally offered to the interlocked channels are made available to the single
data transfer operation.
The transfer rate thus provided is equal to the sum of the rates attainable
individually with the interlocked channels.
When the operation is completed, memory cycle
allocation returns to normal and channels are again offered cycles at the normal intervals.
Programming procedures for channel interlocking are described beginning on page 8-110.
MODEL 4200 VARIABLE-SPEED READ/WRITE CHANNELS
As indicated above, the 4201 is equipped with variable-speed RWC's.
2-16
No more than two
#2-139
SECTION II.
THE CENTRAL PROCESSOR
RWC's (a primary and the corresponding auxiliary) are ever made busy by a single RWC assignment.
However, a single RWC assignment can still command a data transfer capacity of up to
500,000 characters per second.
The most important advantage of this arrangement is that the
RWC's not made busy by a high;...speed transfer are available for use in other operations.
For
example, in order to handle a 250, OOO-character-per-second I/O transfer, other processors
would require the interlocking of several channels.
be tied up.
In the 4200, only one primary channel will
The other RWC's in the same sector will still be available for use in other operations,
e. g., three 83, 300-character-per-second transfers.
However, in no case can the total data
transfer rate of a single sector exceed 500,000 characters per second.
Another feature of the Model 4200 RWC's even more attractive.
the "sector escape code" - makes variable-speed
An escape code allows an RWC normally restricted to operating
in one sector to be used for I/O data transfers in another sector.
For example, an escape code
can be used to assign RWC 1, normally used only in sector 1, to sector 2 I/O operation.
Pro-
gramming procedures for Model 4200 RWC's are described in Section VIII.
Table 2 -4.
Sununary of Central Processor Characteristics
PROCESSING UNIT
Six-bit character.
INSTRUCTION FORMAT
Variable. Typical configuration: op code, two address.es, and variant
character.
ADDRESSING MODES
Two-, three-, and four-character addressing. Three- and four-character
addresses can specify indexed and indirect addressing.
MEMOR Y CAPACITY
(Characters)
2,04832,768
2,04865,536
Fourcharacter
word.
4,09665,536
MEMORY CYCLE
(microseconds)
character
address mode)
16,384131,072
32,768262,144
1.5
1.5
16,384262,144
131,072524,288
.75/word
(.188/
5-Digit
Decimal
Add
(A+B+B)
48fLs
48fLS
48fLs
35fLs
35fLS
25fLs
13fLs
5-Digit
Compare
(A:B)
38fLs
38fLS
38fLs
29fLs
29fLS
21fLs
10fLs
3-4
3-4
3-4
4
PROGRAM CONTROL
SIMULTANEOUS
OPERA TIONS POSSIBLE
2-17
4-8
8-16
#2-139
DATA FORMAT
VARIABLE FIELD LENGTH
Inforll1ation is stored in the ll1ain mell10ry in groups of characters, which are called fields.
A field is, by definition, any group of characters that is treated as a unit.
Series 200 cOll1puters
perll1it fields of any length, froll1 one character up to the ll1axill1um nUll1ber of character s in the
ll1ell1ory.
This ll1eans that an instruction or data field occupies only that nUll1ber of core storage
locations actually needed.
The use of variable-length fields requires that there be a ll1ethod of indicating the actual
lengths of instruction fields and data fields.
ll1entioned in Section 2.
This requirell1ent is fulfilled by the word-ll1ark bit
The word-ll1ark bit perforll1s the following functions:
1.
It terll1inates the retrieval of an instruction.
2.
It terll1inates the execution of an instruction.
3.
It defines the size of a data field.
Throughout this ll1anual, the presence of a word ll1ark will be indicated by a circle around
the character with which it is associated.
The following points should be noted regarding the
use of word marks:
1
1.
Word ll1arks can be set and cleared by prograll1ll1ed instructions.
2.
Word ll1arks are set by the sall1e routine that loads a prograll1 and data into
the ll1ain ll1ell1ory. Usually, word-ll1ark assignll1ents rell1ain unchanged
throughout the execution of a prograll1.
3.
An instruction is terll1inated by a word ll1ark in the storage position ill1ll1ediately
following its last (rightll1ost) character.
4.
A data field is terll1inated by a word ll1ark associated with its high-order
(leftll1ost) character. 1
The footnote on page 3-4 describes an exception.
3-1
#2-179
SECTION III.
DATA FORMAT
INSTRUCTION FORMAT
An instruction is a coded statem.ent which orders the com.puter to perform. a fundam.ental
operation.
A set of instructions suitably com.bined to perform. a specific task is called a program.
or routine.
As will be shown in Section V, the task of coding the instructions in a program. is greatly
sim.plified by the use of the Easycoder sym.bolic program.m.ing system..
The Easycoder Assem.bly
Program. converts the sym.bolic coding written by the programmer into a m.achine language which
is acceptable to the internal logic of the machine.
OPERATION CODE
Basic to all instructions is an operation code, usually referred to as an op code, that defines the fundam.ental operation to be perform.ed.
The program.m.er specifies an op code by using
a predefined m.nem.onic configuration; e. g., BA is the op code that specifies a "binary add"
operation, MCW is the op code that specifies a "m.ove characters to word m.ark" operation.
The
Easycoder Assem.bly Program. autom.atically converts a m.nem.onic op code into a single-character, m.achine-Ianguage op code and sets the word-mark bit in the character position in which it
is stored.
A AND B ADDRESSES
Most instructions also have two address portions, designated as the A address and the
B address.
The address portions indicate the starting locations of the operand fields in the
m.ain m.em.ory.
Using the Easycoder language, the program.m.er can specify m.em.ory locations by
m.eans of syrn.bolic addresses or "tags" (see Section V).
The Easycoder Assem.bly Program. autom.atically assigns absolute m.em.ory addresses to
the syrn.bolic addresses appearing in a program. (see Figure 3-1).
Thus, the program.m.er can
m.anipulate operands without regard to their actual storage locations in m.em.ory.
ABSOLUTE MEMORY
ADDRESS
SYMBOLIC ADDR.
(TAG)
Figure 3 -1.
Conversion of Sym.bolic Tags to Absolute Mem.ory Addresses
3-2
#2-139
SECTION III.
DATA FORMAT
Because of the modular design of Series 200 computers, the programmer has the facility to
specify whether a two-, three-, or four-character absolute address will be assigned to each
~ymbolic
address used in the program.
In any case, the absolute addresses assigned by the
assembly program are interpreted as pure binary numbers (see Section IV).
VARIANT CHARACTER
The variant character is used to modify the op code of an instruction.
For example, the
op code of a Branch on Condition Test instruction (BeT) specifies the fundamental operation
"branch if a tested condition is met." The condition or restriction which must be met before the
branch can occur is specified by the variant character.
A table of valid variant characters is
presented in Appendix B.
SUMMARY
Figure 3-2 shows the six basic formats in which machine-language instructions may appear.
Since the maximum number of characters in an instruction depends upon whether two-, three-,
or four-character addressing is being used, shaded boxes in the illustration indicate the format
of an instruction without specifying the number of characters in each part.
These formats are
representative of all instructions except those associated with input/output and translate opera1
tions.
For the sake of direct comparisons, Figure 3-3 illustrates each of the formats defined in
Figure 3-2 as a symbolic entry on the programmer's coding
OP CODE
I
I I
2
OP CODE
I
I I
3
OP CODE
4
OP CODE
I
I
I
I
5
OP CODE
6
OP CODE
Figure 3-2.
A ADDRESS
A ADDRESS
A ADDRESS
A ADDRESS
form~
B ADDRESS
I
VARIANT
CHARACTER(S)
B ADDRESsl
VARIANT
CHARACTER(S)
VARIANT
CHARACTER(S)
Series 200 Instruction Formats
1
The format of an input/output instruction is a modification of format 3 shown in Figure 3-2.
Specifically, the variant characters of the instruction are replaced by a field of one or more
control characters which define the input/output operation in terms of data path, direction of
data flow, control unit designation, etc. The format of a translate instruction is a modification
of format 1 shown in Figure 3 -2. In Section VIII, Series 200 instructions are described in
terms of their individual formats.
3-3
#2-139
SECTION III.
DATA FORMAT
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
fl~
LOCATION
~ ~
213 4 5 6 7 8
OPERATION
CODE
1415
I
OPERANDS
2021
6263
seE
p, LA BEL
IA
II T E.,~.'-, -rOT ~I
.0.G,
I
I
i
I
I
i :
I
i
i
I
10
1
I
I
12
13
I
I
14
1
15
I
BeT
ISZl<:o •. ~~
SW
WORI(
80
FORMAT
1
FORMAT
2
I
FORIMAT
3-.1
FORMAT
4
FORMAT
5
I
FORMAT
6
I
I
1
'CA,h\
.,
,.
I
6.G.
I
~
I
I
I
I
Figure 3-3.
Symbolic Representation of Series 200 Instructions
ORGANIZATION OF DATA IN MAIN MEMORY
Data may be stored in the main memory in any of the following variable-length formats:
•
FIELD
•
ITEM
•
RECORD
FIELDS
Consider the eight consecutive storage locations shown in Figure 3-4.
To indicate to the
machine that these eight characters are to be treated as a field, their left and right boundaries
must be defined.
The left boundary is normally defined by setting a word mark in position 990.
The right boundary is normally defined by specifying storage address 997 in the instruction that
will manipulate the field. 1 The eight-character group shown in Figure 3-5 is thus defined as a field.
STORAGE ADDRESS
CONTENTS
Figure 3-4.
Consecutive Storage Locations ih Main Memory
1 Although this is the conventional method of defining fields, the Extended Move (EXM) instruction (see Section VIII) permits a field to be defined by a word mark at either the left or'the right
boundary. The opposite boundary is then specified in the instruction.
3-4
#2-139
SECTION III.
DATA FORMAT
EASYCODER
CODING FORM
CARD
NUMBER
I
I~I~
2 3 4 !5 6 7 8
I
DATE
PROGRAMMER
PROBLEM
LOCATION
OPERATION
CODE
6263
2021
1415
IA
!
PAGE
OF
OPERANDS
~~as1'Z.
eo
,'IQ7
T1:..-----ADDRESS PORTION OF INSTRUCTION
STORAGE ADDRESS
CONTENTS
DATA FIELD
Figure 3-5.
-------I~
Data Field Format in Main Memory
ITEMS
An item consists of ,one or more consecutive storage locations whose boundaries can be
defined in either of two ways:
1.
The leftmost character position can be defined in the instruction that will operate
on the item and the rightmost character position defined by an item mark; or
2.
The rightmost character position can be defined in the instruction that will operate on the item and the leftmost character position defined by an item mark.
NOTE: An item mark is illustrated in this manual by underlining the character with
which it is associated. Fields within an item are defined by word marks.
There are only two instructions that manipulate items Extended Move.
Move Item and Translate, and
In the Move Item and Translate instruction, the leftmost character of an item
is addressed and the rightmost character contains an item mark.
In the Extended Move instruc-
tion, several different item boundaries can be specified by the variant character of the instruction.
Two items, each containing three data fields, are shown in Figure 3 -6.
ADDRESS PORTION
OF INSTR UCTION
STORAGEADDRESS~IiIlIlIlIl~IIIIII~II~II~~~II~IIUlIll
CONTENTS
ADDRESS PORTION
OF INSTRUCTION
STORAGEADDRESS~IIIIIIIIIIIIII~IIIIII~IIII
CONTENTS
ITEM MARK
1 4 - - - - - - ITEM - - - - - - - - - '
Figure 3-6.
Two Item Formats in Main Memory
3-5
#2-139
SECTION III.
DATA FORMAT
RECORDS
A record is any unit of information that is to be transferred between the main memory and
a peripheral device.
A record can be of any length, from one character up to the maximum
number of characters in the memory.
It can contain any number of items and fields.
The right-
most limit of a record is defined by a record mark in the character position following the last
character in the record (see Figure 3-7).1
NOTE: A record mark is illustrated by combining the word-mark and item-mark
symbols. The address of the leftmost character in a record is specified
in the instruction that operates on the record. 1
ADDRESS PORTION OF INSTRUCTION
STORAGE ADDRESS
CONTENTS
......- - - - - - - - - - RECORD
Figure 3-7.
-------~
RECORD
MARK
Record Format in Main Memory
SUMMARY
The foregoing data format conventions are summarized in Figure 3-8.
FIELD
ITEM
Word Mark
Address portion of instruction
Address portion of instruction
Item Mark
RECORD
®
Item mark
x
Set Item Mark
x
Addre s s portion of instruction
Record mark
Address portion of instruction
(in character position
following last character
of record) I
Figure 3-8.
1
Set WordMark
BOTH Set
Word Mark
and Set Item
Mark
Summary of Internal Data Formats
A record can also be moved internally (i .. e., from one main memory area to another) by means
of the Extended Move instruction (see Section VIII). In this case, the character containing the
record mark is considered as part of the record. This instruction can specify either the right
or left boundary of the record to be moved.
3-6
#2-139
SECTION III.
DATA FORMAT
MAGNETIC TAPE DATA FORMAT
In many applications, a major input and output medium for a Series 200 computer is magnetic
tape.
um..
The standard Series 200 magnetic tape system uses 1/2-inch tape as the recording mediA tape system using 3 14-inch tape is also available.
Information is stored on I 12-inch magnetic tape in variable -length groups of characters
called records.
The tape is divided lengthwise into seven recording channels.
tions across the tape, one position for each channel, is called a frame.
A line of bit posi-
The seven bits in a
frame correspond to the six information bits and one parity bit found in a character position in
the main memory.
Notice that no channels are provided for the storage of punctuation bits on
tape .. Unlike main memory records, which are delimited by record-mark punctuation, tape rec0rds are separated from each other by a band of blank tape, which is called an interrecord
gap.
The representation of a memory character position on magnetic tape is shown in Figure 3-9.
MAIN
MEMORY
CHARACTER
POSITION
:,~::::
V
!:'""""·
..······..... :·:··
....·,:,:":,,::,:,:,:,,,,,:t:
i::::::::,:······:::
····:,:.:::::::
...:.:.:.:.:.,:,.,.:.:.:.:.:.................
.....:.......... : :. ': .: : : ':. : :.' :. : .'.: .: : ;.:' ,:. : ;.:,. .,:. :. :.,. :.
Figure 3-9.
FRAME
Character Representation on Magnetic Tape
Characters recorded on magnetic tape are transferred from the main memory without
parity bits.
required.
At the time of recording, the magnetic tape control generates parity bits as
The programmer may specify either odd- or even-p-arity recording: in the odd-parity
mode the bit count in each frame is odd; in the even-parity mode the bit count is even.
In addition to parity bits, which are used for frame checking, the magnetic tape control
also generates a longitudinal check frame which is used for channel checking purpose s.
A check
frame is automatically appended at the end of each record stored on tape.
Recall that a record stored in memory is delimited by a record mark in the character
position following the last character in the record.
3-7
When a record is transferred to tape, the
#2-139
SECTIONllI.
DATA FORMAT
contents of the character position containing the record mark are not included as part of the record.
On the other hand, if a record mark is sensed in memory when information is being read
in from tape, the record mark will terminate the record and the character position containing
the record mark will receive a character from the tape.
Although data transfer from the tape
is terminated by the record mark, tape motion continues until an interrecord
gap is sensed.
No punctuation marks are altered in any way as a result of tape read/write operations initiated
by a program.
LONGI TUDINAL
CHECK FRAME
INTERRECORD
GAP
~
,11]
FRAME
Figure 3-10.
Data Format on Magnetic Tape
PUNCHED CARD FORMAT
Punched cards provide a convenient means of entering data into the machine.
The cards
used for this purpose are either standard 12-row, 80-column cards or 51-column cards.
Each
card column may contain a decimal digit, an alphabetic character, or a special symbol such as
a slash or an asterisk (see Figure 3-11).
0123456789
ABCDEFGHI
JKLMNOPQR STUVWXYZ
111111111
ZONE
PUNCHES
111111111
III
00000000 I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0000 UU0 0 0 0 0 011111111 00000000000 0 0 III 0 0 0 0 0 0 0 0 0 0
1 2 1 4 S 6 7 I 910111113'415 161118 192CZ~ 211324]S26 21182930JI 31JJ ~4 J) J6
1)
l8 394(1414? 4144 45 4t' 41 4& ~!'~ ~I 51 SJ~ ~S5651 ~S9606162 6J 64 O~ &66:
so 69
10 I, 12 1]1415 16 11 J8 1910
II I 111 1 11111 111111 11 11 11 1111 1 1111 I 1 111111 11 1 1 11 1 I 11 f 1 I 1111 1 I 1 1 I 1 'II 111 1 111111111 I
2222222222122222222222222221222222222122222222122212 2 2 2 2 2 2 2222222222222222222222
33333333333133333333333333331333333333133333333133333333333333133133131333333333
NUMERIC
PUNCHES
4444 444 4 4 ~ 4 414 4 4 4 4 4 4 4 4 4 4 4 4 4 4 414 444 4 4 4 :~)
in column 6.
Information inserted in this manner, while it remains as part of the
source program, does not appear in the object program; it does, however, appear in the program listing.
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~_ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ OATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I~I~
~ ~
LOCATION
1 213 415 6 7 8
I
I
:*
OPERATION
CODE
1415
OPERANDS
2021
SPECIFY CCNi.ROL
6263
80
COJLSTANT5
I
Easycoder C and D Options
For Easycoder C or D users, this column may also contain the letter T to designate a temporary remarks card, or the letter D to designate a data card.
If the programmer wishes to
enter remarks lines anywhere in the source program but does not want these remarks to become
a permanent part of the source program, a T instead of an asterisk
(>:~)
is placed in column 6.
Remarks lines inserted in this manner are used only on the first assembly (i.
e.,
when the pro-
gram is being "inserted"), and are subsequently deleted from the symbolic program tape by the
assembler.
A temporary (like a permanent) remarks statement, while it appears in the program
listing, does not appear in the object program.
A letter D in column 6 indicates a data card.
conSisting only of data cards.
All data cards must be contained in segments
In addition, any data card (or group of data cards) must be immedi-
ately preceded by a SEG card and immediately followed by either an EX, XFR, or END card.
When a data card is encountered by an assembler, columns 8 through 80 are reproduced, unaltered, on the binary run tape or machine-language punched deck.
MARK (Card Column 7)
This field, used in conjunction with data formatting operations (described in Section VI),
serves to set up required punctuation.
Two sets of punctuation indicators are available; set I may
be employed with all Easycoder assembly systems (A, B, C, and D); set II, however, may only
be used with the Easycoder C and D.
Both punctuation sets are described below.
5-6
#2-139
SECTION V.
EASYCODER PROGRAMMING
Set I, consisting of a blank (.t.), an L, and an R, establishes the position of the item mark
when defining an item (see Table 5-1).
Word marking for this first set depends upon the class of
instruction, as determined by the contents of the op code field.
NOTE: When an L is used and the leftmost (high-order) character is automatically
word marked, a record mark will result.
Table 5-1.
Set I Punctuation Indicators
~
Item Mark
L
Item Mark
R
Set II, designed for use with the Easycoder Assemblers C and D, can be employed in situations which warrant unusual punctuation requirements.
With this set (listed in Table 5-2), any
one punctuation indicator controls the complete punctuation setting for the particular instruction
or constant.
However, there is no implicit word mark setting as in the first set.
In other words,
this second set of punctuation is not dependent upon the class of instructions.
Table 5-2.
Set II Punctuation Indicators (Easycoder C and D Only)
A
Word Mark
~
B
Item Mark
~
C
Record Mark
~
D
fl
Word Mark
E
fl
Item Mark
F
~
Record Mark
G
Item Mark
Item Mark
H
Item Mark
Word Mark
I
Item Mark
Record Mark
'J
Word Mark
Item Mark
K
Word Mark
Word Mark
M
Word Mark
Record Mark
N
fl
fl
P
Record Mark
Word Mark
S
Record Mark
Item Mark
T
Record Mark
Record Mark
5-7
#2-139
SECTION V.
EASYCODER PROGRAMMING
LOCATION (Card Columns 8-14)
The location field can contain an absolute memory address or a symbolic tag, or it can be
left blank.
An absolute memory address (expressed as a decimal number) specifies that the in-
struction or data will be stored in that location.
absolute decimal number.
No leading zeros are necessary when writing an
Moreover, this type of entry does not affect the allocation of any sub-
sequent instructions.
Symbolic tags provide simple, meaningful symbolic references for storage locations, constants, and instructions that are referred to elsewhere in the program.
in the location field are assigned absolute addresses during assembly.
All symbolic tags written
When an entry is assigned
a symbolic tag, the contents of the entry can then be referred to by that tag...
This means that the
programmer can refer to data via a symbolic tag and need not be concerned with its actual main
memory address.
One to six characters make up a symbolic tag (Easycoder D, however, can
process tags of up to ten characters in length; see "Easycoder D Options" below).
These charac-
ters can be alphabetic (A to Z) or numeric (O to 9); the first character of the tag, however, must
be alphabetic.
If the location field entry is made beginning in column 8, the following rules apply:
1.
An absolute memory address assigned to an instruction refers to the leftmost
character in the instruction.
2.
An absolute memory address assigned to a constant or reserved area refers
to the rightmost character in the field.
3.
If a symbolic tag is assigned to an instruction, the address assigned to the
tag will be the address of the leftmost character in the instruction.
4.
If a symbolic tag is assigned to a constant or reserved area, the address
as signed to the tag will be the rightmo st character in the field.
The se addre s s as signment conventions can be reversed by leaving column 8 blank and
entering the first character in column 9.
In this case, the following rules apply:
1.
An absolute memory address assigned to an instruction refers to the rightmo st character in the instruction.
2.
An absolute memory address assigned to a constant or reserved area refers
to the leftmost character in: the field.
3.
If a symbolic tag is assigned to an instruction, the address assigned to the
tag will be the address of the rightmost character in the instruction.
4.
If a symbolic tag is assigned toa constant or reserved area, the address
assigned to the tag will be the leftmost character in the field.
5-8
#2-139
SECTION V.
EASYCODER PROGRAMMING
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
~~
~ ~
1 213 415 6 7
I
I
LOCATION
e
BEe:, IN.
1
i
·1
1
I
1
DATE
OPERANDS
2021
1
i
IMew
F\CA. TAX
Dew
BE6\ N
~~ ~j 1,9.1. 6 5@
Is
1
i
OPERATION
CODE
1415
eo
6263
The first instruction shown above :moves the contents of the field tagged FICA to the field
tagged TAX.
This instruction can be referred to in the operands field of another sy:mbolic pro-
gram entry via the tag BEGIN.
For instance, the second instruction cause s the program to
branch to the MCW instruction by referring to it via its symbolic tag (BEGIN).
In other words,
the address of the operation code of the MCW instruction is inserted in an object-program instruction wherever the tag BEGIN appears as an operand in a symbolic-progra:m entry.
The third
instruction defines an alphanumeric constant which can be referred to in the operand field of
another symbolic-program entry via the tag DATE.
In this case, the tag refers to the addre ss
of the rightmo st character in the constant.
Easycoder C and D Options
Users of Easycoder C or D may also include, in the location field, an apostrophe (,)1 followed by a decimal number; this procedure serves to indicate an address relative to the out-ofsequence base (OSB).
The out-of-sequence base, a value maintained by the assembler can be
set by t1;le XBASE instruction (see page 7-18).
The assembler assigns to the corresponding
statement an address equal to the sum of the decimal number and the current value of the OSB.
(Leading zeros may be omitted from the decimal number.)
The allocation of any subsequent
instructions is not affected.
If the apostrophe and decimal number are written beginning in column 8, the following
rule s apply:
1.
An address relative to the out-of-sequence base assigned to an instruction
refers to the leftmost character in the instruction.
2.
An address relative to the out-of-sequence base assigned to a constant or
reserved area refers to the rightmost character of the field.
The se addre ss conventions can be reversed by leaving column 8 blank and entering the
first character (the apostrophe) in column 9.
1
In this
case~
the following rules apply:
Card code 8, 2 (octal 12).
5-9
#2-139
SECTION V.
EASYCODER PROGRAMMING
1.
An address relative to the out-oi-sequence base assigned to an instruction
refers to the rightmost character in the instruction.
2.
An address relative to the out-ot-sequence base assigned to a constant or
reserved area refers to the leftmost character of the field.
Assume, for example, that the OSB has been set to the value 500 by the last XBASE instruction.
The following DCW statement is now encountered.
by the assembler, to locations 648 through 650.
The constant PRM is as signed,
(The value of the OSB remains 500).
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
fl~
LOCATION
~ ~
1 213 415 6 7 8
I
I
:
I'
OPERATION
CODE
1415
DeW
/.S,O
OPERANDS
2021
I
80
6263
1
~PRM@.
1
Easycoder D Options
Symbolic tags of up to ten characters in length may be employed with Easycoder D.
symbolic tags consisting of six characters or less, the standard coding format is used.
For
How-
ever, if tags of from seven to ten characters are used, the location field is modified such that
it now occupies card columns 8-18.
(This alternate format also requires that the operation code
field and operands field be modified to accommodate the increase in tag size.) The same programming conventions which apply to six-character tags apply also to ten-character tags.
NOTES: 1.
2.
The program header (PROG) card is used to denote that the
alternate format is to be employed. See page 7 - 2 for instructions on how to employ the PROG card in this mannero
Symbolic tags of more than six characters in length may not
be used if the input is to be in the form of paper tape.
OPERATION CODE (Card Columns 15-20)
This six-character field can contain a mnemonic operation code for a machine instruction,
an assembly program directive, or a data formatting code (see entries below).
must be left-justified.
of mnemonic codes.
These entries
Machine-language operation codes (in octal notation) may be used instead
These octal codes are written in columns 19 and 20 of the operation code
field, and columns 15 to 18 are left blank.
5-10
#2-139
SECTION V.
EASYCODER PROGRAMMING
Easycoder D Options
If the alternate coding format is used (i. e., the location field contains tags of from seven
to ten characters in length), the operation code field occupies card columns 19-24.
of coding mnemonic operation codes remains the same.
The method
If octal operation codes are used, they
are written in columns 23 and 24; columns 19-22 are left blank.
OPERANDS
The operands field is a variable-format field which can contain a seritfs of entries separate
by commas and terminated by the first blank following any character other than a comma or a
blank.
In general, the operands field contains such entries as the addresses (either symbolic or
absolute) of the data to be operated upon by a command in the operation code field, literals, address constants, or input/output information.
Relative, indexed, and indirect addressing can be
used in conjunction with absolute or symbolic addresses (see below).
Easycoder A and B (Operands Field: Card Column 21-62)
For either of these two assembly systems; column 62 terminates the operands field.
Any
punches appearing in columns 63-80 (of any line other than a remarks line) are ignored and do
not even appear in the object-program listing.
Remarks may be entered following the terminating
blank.
Easycoder C and D (Operands Field: Card Columns 21-80)
For users of Easycoder C or D, the operands field extends to column 80.
be entered following the terITlinating blank.
ReITlarks ITlay
One or both operands can be bypassed during as-
seITlbly by writing one or two leading COITlITlas, respectively, in the operands field.
Such a
COITlITla, or, COITlITlas, ITlust be left-justified in the operands field and ITlust be followed iITlITlediately (i. e., without intervening blanks) by any reITlaining entries, other than reITlarks.
Easycoder D Options
If the alternate coding format is used (i. e., the location field contains tags of froITl seven
to ten characters in length), the operands field occupies card coluITlns 25-80.
The ITlethod of
coding entries and reITlarks reITlains the saITle.
ExaITlples
The first saITlple instruction causes the contents of the field whose rightmost character is
stored in ITleITlory location 50 to be added algebraically to the contents of the field designated by
the tag TOTAL.
The second instruction tests the indicator specified by variant character 3 and branche s to
the address tagged EQUAL if the indicator is on.
5-11
#2-139
SECTION V.
EASYCODER PROGRAMMING
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ OATE _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
~~
LOCATION
~ ~
1 213 415 6
7 8
OPERATION
CODE
1415
OPERANDS
6263
2021
:
IA
5(6,TOTAL
I
I
!BeT
EQUAL /t5
IZA
TOTAL .. TMP ... X3
i I
IMew
ITOTAL-7~X6AGROSS
A
IAMTA c'SUM-2,)
I
I
I
I
1...
I
I :
I
80
~.
I
i
I
I
1
I
I
The third line of coding above shows an instruction in which the B address is indexed.
The
instruction causes the contents of field tagged TOTAL to be placed in the field designated by the
tag TMP as modified by the contents of index register X3.
The fourth line of coding shows relative addressing and indexing being performed on the A
address.
The instruction causes the address seven before that tagged TOTAL to be modified by
the contents of index register X6.
The resultant address specifies a field whose contents are then
placed in the field tagged GROSS.
Assuming that TOTAL corresponds to memory location 540
and index register x6 contains a value of 80, the resultant address of this instruction would be 613.
The last line of coding above illustrates an instruction with indirect addressing on the B
address.
The contents of the field tagged AMT are added algebraically to the contents of the
field whose address is stored in the field tagged SUM-2.
ADDITIONAL CODING RULES
1.
Comments and remarks can appear on any line following the last entry on that
line and separated from it by a blank space. These notes will be printed on
the program listing but will not be assembled as object-program entries. As
mentio~ed prev:i01,lsly, any line of coding containing only comments must be
designated by an asterisk (*) or the letter T in column 6.
2.
Any number of bl~!lk spaces may be used between the comma which terminates
the A operand and the first character of the B operand. Similarly, any number
of sp'aces may be used between the comma that terminates the B operand and a
variant character.
ADDRESS CODES
Several types of address codes are valid in the operands field of an Easycoder statement.
These codes are defined and illustrated below.
,
..
5-12
#2-139
SECTION V.
EASYCODER PROGRAMMING
ABSOLUTE
The actual address of a character position in the main memory can be represented as a
decimal number; leading zeros can be omitted.
The sample instruction causes the contents of
the field whose rightmost character location is 32 to be moved to the field whose rightmost
character location is 4000.
EASYCODER
CODING FORM
PROBLEM
CARD
NUMBER
I
.__
~,~
__ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
1
:
OPERANDS
2021
1415
213 415 6 7 B
I
OPERATION
CODE
LOCATION
~ ~
IMew
~21\
1
eo
6263
-.i
4(lS,00.
I
SYMBOLIC
A symbolic address, or tag, can be used in the operands field only if it appears in the location field elsewhere in the sym.bolic program.
In effect, a tag must be defined (by writing it
in the location field of a symbolic entry) in order for it to be used as an operand address.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~l~
LOCATION
~ ~
2[3 415 6 7 B
I
1
TOTAL
i
OPERATION
CODE
1415
OPERANDS
2021
A
eo
6263
..l
FICA. TOTAX
I
The instruction shown above can be referred to elsewhere in the program via its tag
(TOTAL). ' It should be noted, however, that this instruction is a valid statement only if the
symbolic addresses FICA and TOTAX have been defined in the location field elsewhere in the
source program.
SELF REFERENCE
It is sometimes convenient for an instruction to refer to itself.
A self reference is indi-
cated by an asterisk in the operands field of a source-program instruction.
The assembler
automatically replaces the asterisk with the address of the leftmost character of the instruction
in which it appears.
Address modification and relative addressing can be performed on asterisk
Jperands.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
H~
~ ~
213 415 6 7 8
I
I
I1
t
I
I
LOCATION
OPERATION
CODE
1415
Mcw
IMCW
OPERANDS
2021
1
1
1
1
6263
eo
f*+4 •.WDRk::
"
~+9 WORK
5-13
#2-139
SECTION V.
EASYCODER PROGRAMMING
In the first sample entry above, the notation )lc+4 addresses the rightmost character of the
instruction in which it appears (assuming that two-character address assembly has been specified).
Since the function of this instruction is to move the field specified by the A address to that
specified by the B address, the instruction itself will be moved to the field tagged WORK.
In the second entry, the notation *+9 refers to the rightmost character of the instruction
stored immediately to the right of the MCW instruction (assuming that two-character address
assembly has been specified).
The instruction following the MCW instruction will be moved to
the field tagged WORK when the MCW instruction is executed.
RELATIVE
Relative addressing, or address arithmetic as it is frequently called, can be used with all
absolute addresses. symbolic addresses. and the self-reference symbol ()!<) (these three types of
address codes are
referr~d
to as addressing "elements rt ).
By using relative addressing, the
programmer can refer to a source-program entry that is stored a specified number of locations
away from a particular address.
A relative address is specified by appending one or more ad-
dress modifiers, each consisting of a sign and an addressing element, to another addressing element.
The address modifier designates a memory location relative to the location specified by
the basic addressing element.
For example, the instruction below causes the contents of the field
100 characters beyond the field tagged INT to be added algebraically to the contents of the field
10 characters before the sum of the addresses defined by the tags AMTPD and ERROR.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _- - - - - - - -_ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
~I~
~ ~
12134I5 6 7
I
:
LOCATION
e
OPERATION
CODE
1415
l4,
OPERANDS
2021
6263
80
\NT~1~~.~A.MTPD~ERROR-1¢.
The number of symbolic tags required to write a program can be greatly reduced by the
use of relative addressing.
The programmer decides how many and which fields in a program
to tag and which to reference by relative addressing.
A certain amount of caution is required in the use of relative addres sing. First of all,
relative addres ses are not automatically corrected as a result of subsequent insertions or deletions in the source program.
The programmer must remember to adjust manually the address
modifiers affected by such changes.
Secondly, if relative addressing is used to refer to an
operand address in another instruction, care must be taken to insure that the address is referenced by its rightmost character.
For example, the A address of the instruction shown below
could be referred to elsewhere in the program as INST+2 or INST+3, depending on whether twoor three-character address assembly were specified.
#2-139
SECTION V.
EASYCODER PROGRAMMING
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~I~
LOCATION
~ ~
1415
2' 3 415 6 7 8
I
T
IN~T
i
OPERATION
CODE
OPERANDS
2021
IA
I
I
I
80
6263
f.>.UBT. TOTAL
I
OUT-OF-SEQUENCE
The valid address codes also include the special symbol apostrophe (printer I; keypunch
8, 2; octal 12).
This symbol is an element whose value is equal to the current value of the out-
of-sequence base (OSB).
sired operand.
It is followed by an address modifier to specify the address of the de-
The OSB is set by means of the XBASE instruction (see page 7-18).
EASYCODER
CODING FORM
PROBLEM CARD
NUMBER
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
~I~
LOCATION
213 415 6 7 8
I
OPERATION
CODE
1415
A
i
OPERANDS
2021
6263
I
80
IWORK, ' + 1 5
In the sample statement above, assume that the out-of-sequence base (OSB) has been set
to 600 (by the XBASE instruction).
The data in the field tagged WORK will be added to the data
in the field whose rightmost location is 615 (600
+ 15).
The result will then be stored in the field
whose rightmost location is 615.
BLANK
There are two conditions for which a blank operand field is valid:
1.
. The instruction does not require an operand (e. g. , the Halt and No Operation
instructions ).
2.
The operands are implicitly addressed: the A operand is specified by the
contents of the A-address register (AAR); the B operand is specified by the
contents of the B-address register (BAR).
If either or both operand addresses are to be supplied by other instructions (as illustrated
below in the description of address literals), the affected operands should be represented by
zeros; they should not be left blank.
LITERALSI
The purpose of a literal is to allow the programmer to write in the operands field of a
symbolic program statement the actual data (as opposed to the address of the field containing
1Not available with Easycoder A.
5-15
#2-139
SECTION V.
EASYCODER PROGRAMMING
the data) to be operated on by an instruction. 'Easycoder B users can code all literals, except
binary, with a maximum length of 40 characters; a binary literal can be coded with a maximum
length of six characters.
For users of Easycoder C or D, the maximum length of any literal can
be 63 characters.
The assembler automatically assigns a storage field for each literal and inserts its address
(i. e., the address of its rightmost character) in the operands field of the instruction in which it
appears.
In effect, for every literal appearing in the source program, the assembler generates
a constant containing the value of the literal, with a word mark in the leftmost character position.
NOTE: If the constant generated from a literal occupies from one to five storage
locations, it is assigned a storage address only once in the program, regardless of the number of times the literal appears in the source program.
{For Easycoder C or D, the constant is assigned a storage address only
once in the program if it occupies from one to six storage locations.} A
constant that exceeds five characters (six for Easycoder C or D) is assigned
a storage address each time the corresponding literal appears in the source
program. The latter condition can be avoided by using a DCW statement
(see page 6 - 2) whenever a long literal is to be used more than once in the
source program.
Decimal Literals
Decim.al literals are specified by writing a plus or minus sign followed by the value of the
literal •. When the literal is assigned to a storage field, the assembler places the sign in the zone
bits of the units position of the resulting constant.
Unsigned decimal values can be coded as
alphanumeric literals.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CARD
NUMBER
~~
~ ~
LOCATION
1 213 415 6 7 8
I
1
OPERATION
CODE
1415
:
S
PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
OPERANDS
6263
2021
80
+2.4-ACcUM
1
I
I
I
1
The statement above illustrates the use of a decimal literal.
The instruction causes the
value 24 to be subtracted from the contents of the field tagged ACCUM.
Binary Literals
A binary literal is represented as a decimal entry in the operands field of a symbolic instruction.
The assembler automatically converts the decimal entry into a binary value and stores
It (right-justified) in the storage field.
The programmer must specify the number of six-bit
characters used to store this value.
5-16
#=2-139
SECTION V.
EASYCODER PROGRAMMING
A binary literal is coded by writing a # sign, followed by a number which specifie show
many six-bit characters should be used to store the resulting binary value, followed by the letter
B, followed by the decimal representation of the desired binary literal.
NOTE: If the decimal representation of the binary literal is preceded by a minus
sign, the as sembler will store the binary literal in two's -complement
form.
The first instruction below causes the binary equivalent of 50 (expressed as a continuous
12- bit binary value) to be added to the contents of the field tagged BEGIN+2.
The second in-
struction has been included to illustrate how a binary literal can be used in address modification.
In effect, the first instruction modifies the A address of the second instruction by a value of +50.
The third instruction causes the binary equivalent of 2,688 (expressed as a 12-bit binary value)
to be moved to the field tagged IND7.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
LOCATION
~ ~
1 210 415 6 7 8
I
I
I
1415
1
I
BE6l f\J
I 1
I
: :
OPERATION
CODE
OPERANDS
2021
8,A
Mew
1I'2BS:~"BE6\ ~+2
'iEMA~ TOTAL
Mew
~2B26 88~ 'N 07
~
L
~
6260
80
Octal Literals
Octal literals are coded in octal notation (see Appendix A).
The programmer must specify
the number of six-bit characters required to store an octal literal.
NOTE:
Since every octal digit can be represented as three bits: each six- bit
character used to store an octal literal contains two octal digits. For
example, an octal literal composed of eight octal digits can be stored
in a four-character field.
An octal literal is coded in the same format as a binary literal except that the letter Bused
in the binary literal is replaced by the letter C.
The constant stored by the assembler is al-
ways left-justified in the storage field.
5-17
#2-139
SECTION V.
EASYCODER PROGRAMMING
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
I" 213 415 6 7 8
I
OPERATION
CODE
LOCATION
~~
1415
:
OPERANDS
2021
I1-\ A
I
I
.1
80
6263
#~,C 7777.,MA.SK
1
1
The A operand in the above statement is a four-digit octal literal.
The assembler will
store it left-justified in a three-character field, "as 777700.
Alphanumeric Literals
An alphanurn.eric literal is specified by writing the @ symbol before and after the value of
the literal.
This type of literal can contain blanks, decirn.al, alphabetic, and special charac-
ters (excluding the @ symbol).
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~I~
~ ~
213 415 6 7
I
LOCATION
e
OPERATION
CODE
1415
:
OPERANDS
2021.
IMew
I
i@>Acco UNTS
I
6263
I
The statement above illustrates the use of an alphanumeric literal.
the inforrn.ation contained within the
80
PAYABLE,~1.~/19/65~.PR'NT
~
The instruction causes
syrn.bols to be moved to the field tagged PRINT.
EASYCODER C AND D OPTIONS
In addition to the form specified above, users of Easycoder C or D have available to them
three other methods of coding alphanumeric literals.
1.
A number sign (#) is followed by a number from 1 through 63 which specifies the number of characters in the literal; this number is, in turn, followed by the letter A and the literal.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
~I~
213 415 6 7 8
I
I
:
LOCATION
OPERATION
CODE
1415
Mew
OPERANDS
2021
If/14A6
6263
I
LB5
@ 21 ¢JLB,~
PRI
80
t-JT
In the above example there are 14 characters in the literal. The instruction causes these 14 characters to be moved to the field tagged PRINT.
2.
If it is desired to set an item mark (in addition to a word mark) in the
leftmost position of the literal constant field, a number sign (#) is followed
by a number from 1 through 63 which specifies the number of characters in
the literal; following this number is the letter L and the literal (see the first
example below).
5-18
#2-139
SECTION V.
EASYCODER PROGRAMMING
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
~I~
~ ~
213 415 6 7
I
1
i
OPERATION
COOE
LOCATION
e
1415
:
I
I
I
OPERANDS
2021
1
I
Mew
#6L1965./A. STO.RE
Mew
#6.R 1965./ A. .. STORE
80
6263
If it is desired to set an item mark in the rightmost position of the literal
constant field, a number sign (#) is followed by a number from 1 through 63
which specifies the number of characters in the literal; following this number is the letter R and the literal (see the second example above).
3.
NOTE: In form (1), alphanumeric literals of six characters or less are stored
in a literal table and duplicates are eliminated. The duplicates are
not, however, eliminated in forms (2) and (3).
Area Defining Literals
An area defining literal may be used to define and reserve a working area in memory without using a separate data formatting instruction.
as a symbolic tag.
The address which defines the area is written
The size of the area to which the literal address refers is specified as a
decimal value following the literal address and separated from it by a # symbol.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~I~
LOCATION
213 415 6 7 8
I
:
OPERATION
CODE
1415
IMew
OPERANDS
80
62 63
2021
IWAG E '\ TEMPI 5
In the instruction above, the entry TEMP#5 causes the assembler to reserve a blank fivecharacter area with a word mark set in the leftmost character position.
rightmost character in this area is assigned to the tag TEMP.
The address of the
Therefore, TEMP can be used as
a symbolic address elsewhere in the source program, because both the tag and size of the area
to which it refers are defined.
The sample instruction causes the contents of the field tagged
W AGE to be moved to the field tagged TEMP.
Address Literals
An address literal enables the programmer to specify a symbolic address in the operands
field of an instruction such that the assembler will use the address as an operand.
A symbolic
address can be used as an address literal only if it is defined elsewhere in the symbolic program.
The tag used as an address literal must be preceded by a plus sign.
The length of the address
is determined by the current addressing mode (the defined address can be two" three" or four
characters long).
5-19
#2-139
SECTION V.
EASYCODER PROGRAMMING
An address literal (+AMT) is used in the first sample entry below.
Assume that AMT has
been defined elsewhere in the program and has been assigned an absolute address of 800.
The
absolute address of AMT, as opposed to the contents of the field tagged AMT, replaces the address literal.
The first instruction below causes the value 800 (the absolute address assigned
to AMT) to be moved to an address three greater than the location tagged MODIF.
entry shows how an operand address can be supplied by another instruction.
The second
Specifically, the
absolute address assigned to the tag AMT is supplied as the A address of the instruction tagged
MODIF.
This instruction causes the contents of the field tagged AMT (i. e., the field whose
rightmost character is stored in location 800) to be added algebraically to the contents of the
field tagged TOTAL.
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~~
I
i
;
I
i
I
OPERATION
CODE
LOCATION
213 415 6 7 8
1415
I~o.ol F
OPERANDS
2021
IMew
IA
6263
I
80
+AMT .. ,MODI F +3
1<6 TOTAL
VARIANT CHARACTER
A variant character can be expressed as one alphanumeric character, as two octal digits,
or as a synlbolic tag. 1 It is written following the operand entries and separated from. the last
entry by a corn.rn.a.
Octal representation of valid characters are listed in Appendix B.
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
f~
~~
213 415 6 7 8
I
1
:
.I
j
i
I
I
LOCATION
OPERATION
CODE
1415
IBeT
IBee
OPERANDS
2021
6263
80
OFLOW,,5,Q},
NE6 "SU.M I\,QJ6
I
The fir st instruction above tests an indicator specified by the variant character.
If the
indicator is on, the instruction causes the program to branch to the address tagged OFLOW.
As might be expected, the octal digits 50 represent the overflow indicator.
The second instruc-
tion causes the single character at the location tagged SUM to be examined for a particular bit
I A symbolic tag, composed of at least two characters, may be used to represent (1) a variant
character, or (2) a group of input/output control characters. The number of I/O control characters that rn.ay be represented varies from one to six (using either Easycoder A or B) or from
one to four (using other Easycoder C or D). The symbolic tag rn.ust be defined before it is used
in the input/output instruction; the Control Equals statement (CEQU) is generally used for this
purpose (see page 7-13).
5-20
#2-139
SECTION V.
EASYCODER PROGRAMMING
configuration as specified by the variant.
In this case the variant 06 specifies that the charac-
ter should be examined for a negative sign.
If the desired bit configuration is present, the pro-
gram branches to the address tagged NEG.
INPUT/ OUTPUT CONTROL CHARACTERS
Input/ output control characters can be used only in conjunction with input/ output instructions (see Section VIII). One or more of these characters may be written following the A-address
entry in an input/ output instruction, each preceded by a comma.
Input/ output control characters
may be coded as single alphanumeric characters, as pairs of octal digits, or as symbolic tags. I
ADDRESS MODIFICA TION CODES
In a system equipped with the Advanced Programming Instructions (Feature 010 or 011 in
Model 200; standard in Models 1200, 1250, 2200, and 4200), two address modification codes are
valid in the operands field of a source-program statement: indexed and indirect.
These codes
allow the modification of operand addresses without altering the instructions in which the
addresses appear.
This is in direct contrast to the permanent alteration of an instruction that
results from using a binary arithmetic instruction to modify either or both operand addresses.
INDEXED
Indexed addressing is performed by appending to the address being modified a code to indicate which of the index registers is to be used.
The code consists of a plus sign followed by an X
or Y and a decimal number from I to 15. 2
If an index register is to be specified in the operands field of an instruction for other than
indexing purposes, it is referred to by its absolute address rather than its symbolic address.
For instance, absolute address 24 is used instead of the corresponding symbolic address X6.
However, the programmer may use the symbolic address if he equates it to the absolute address
using an EQU statement (see page 7-12).
1
See footnote, page 5-20.
2Figure 4-3, page 4-9, pictures the possible locations of Series 200 index registers. Table 4-1,
page 4-10, indicates the number of index registers simultaneously available to a program.
Tables 4-2 and 4-3 on pages 4-12 and 4-14, respectively, indicate the address modifier and
absolute locations corresponding to each symbolic index-register addres s. The number of index
registers which can be referenced sumbolically also depends on the as sembler being used, as
described on page 6 - 8.
5-21
#2-139
SECTIONV.
EASYCODER PROGRAMMING
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
Ii
CARD
NUMBER
1 213 415 6 7 8
I
I
I
I
L
LOCATION
OPERATION
CODE
1415
OPERANDS
6263
2021
C
DATA +.X6... POS
t~A
SToRE 1,.. X\2,
tMeW
Qr- 6+.X, , BUFF
80
I
L
I
I i
t.x.a
The first instruction above causes the contents of the field designated by the tag DATA as
modified by the contents of index register X6 to be compared to the contents of the field tagged
POSe
The second instruction causes the contents of the field tagged STORE to be added {in
binary} to the contents of index register X12.
The use of the symbolic designation X12 implies
that an EQU statement was used to equate it to the absolute address of index register X 12. The
third instruction illustrates how an indexed address can be coded to generate an effective address which is less than the value stored in the specified index register.
The zero is used be;..
cause an operand address cannot be introduced with a plus or a minus sign.
Thus, the effective
A address of the MCW instruction will be a value six less than that stored in index register Xl
{i. e., if index register Xl contains 126, the effective A address is 120}.
Three- or four-character address assembly must be specified {see ADMODE, page 7-11}
whenever indexed addressing is to be performed.
When the assembler translates an indexed
address into a machine-language entry (see Figures 5-6 and 5-7), the translated index register
designator is automatically inserted into the address modifier bits of the assembled address.
INDEX
REGISTER
DESIGNATOR
15-BIT REPRESENTATION
OF ADDRESS ASSIGNED
TO THE TAG AMNT
OPERANDS
21
SUB,tllllllll • • • • •_
• •_~1
ASSEMBLER
BADDRESS OF
ASSEMBLED INSTRUCTION
Figure 5-6.
Assembly of Indexed Address in Three-Character Addressing Mode
5-22
#2-139
SECTION V.
EASYCODER PROGRAMMING
INDEX
REGISTER
DESIGNATOR
I:UB._
.O.P.E.R.AN.D.S.\• • •1It1
18- BIT REPRESENTATION
OF ADDRESS ASSIGNED
TO THE TAG AMNT
l-
~
ASSEMBLER
B ADDRESS OF
ASSEMBLED INSTRUCT ION
Figure 5-7.
Assembly of Indexed Address in Four-Character Addressing Mode
INDIRECT
An indirect address is specified by enclosing the address (either symbolic or absolute) in
parentheses. l For example, in the sample instruction below, the parentheses around the tag
DATA indicate to the as sembler that DAT A refers to the leftmost character of a field containing
another address.
This second address may be a direct, an indexed, or another indirect address.
If it is direct or indexed, it specifies the rightmost character of a data field.
If it is indirect, it
specifies the leftmost character of a field containing another address.
EASYCODER
COOING FORM
PROBLEM
CARD
NUMBER
PROGRAMMER
~~
~ ~
LOCATION
1 213 415 6 7 8
I
I
OPERATION
CODE
1415
:
MtW
DATE
PAGE
OF -
OPERANDS
2021
I
i
80
6263
I(DATA,) .WDR,K
1
Three - or four -character addres s as sembly must be specified whenever indirect addres sing
is to be used.
When assembler translates an indirect address into a machine-language entry
(see Figures 5-8 and 5-9), a binary value of III (three-character mode) or 10000 (four-character
mode) is automatically inserted into the address modifier bits of the assembled address.
INDICATES
INDIRECT
ADDRESS
1:l=':l=A=GE='I=j ~=: : ,.=;]!tl=;I
I
i\•••_1
IS-BIT REPRESENTATION
OF ADDRESS ASSIGNED
TO THE TAG TEMP
OPERANDS\
•••••••••
ASSEMBLER
'-----'
B ADDRESS OF
ASSEMBLED INSTRUCTION
Figure 5-8. Assembly of Indirect Address in Three-Character Addressing Mode
1The left parenthesis corresponds to keypunch symbol
to keypunch symbol 0 (card code R, 8, 4).
5-23
% (card
code 0, 8, 4), the right parenthesis
#2-139
SECTION V.
EASYCODER PROGRAMMING
IS-BIT REPRESENTATION
OF ADDRESS ASSIGNED
TO THE TAG TEMP
I~
OPERANDS\
ASSEMBLER
B ADDRESS OF
ASSEMBLED INSTRUCTION
Figure 5- 9. Assembly of Indirect Address in Four-Character Addressing Mode
5-24
#2-139
DATA
FORMATTING
STATEMENTS
INTRODUCTION
A value or quantity which m.ust remain fixed or which must be used repeatedly in a program
is called a constant.
A work area is an area in memory which is reserved for input data, cu-
mulative processing, or output data.
By employing data formatting statements, constants can
be stored and work areas can be reserved without regard to their actual locations in memory.
For instance, the programmer can use a data formatting statement to reserve an 80-character
card input area and assign it a symbolic address such as CARDIN, without knowing the actual
address of the field.
Similarly, a data formatting statement ITlakes it possible to store a con-
stant, such as 2000, and to refer to it by a sYITlbolic tag, such as CON3, without regard to the
address at which the constant is stored.
Table 6-1 lists the five data formatting statements used
with Easycoder symbolic language.
Table 6 -1.
Data Formatting Statements
DCW
Define Constant with Word Mark
DC
Define Constant without Word Mark
RESV
Reserve Area
DSA
Define SYITlbol Addre s s
DA
Define Area~:~
~:~NOTE:
The Define Area statement cannot be eITlployed
with the Easycoder A AsseITlbly System.
Although data formatting statements are coded in the same forITlat as most symbolic machine instructions (data processing statements), they are not treated as instructions by an assembler.
Instead they are treated as definitions which cause the asseITlbler to perform certain
activities but which are not executed during a program run.
Since data forITlatting statements are
not executed during a prograITl run, they should not be written in the body of the sYITlbolic program.
6-1
#2-139
SECTION VI.
I
DATA FORMATTING STATEMENTS
Define Constant with Word Mark - DCW
By use of the DCW statement, a constant can be automatically stored in a field reserved
by the assembler.
In storing the constant, the assembler automatically sets a word mark in the
leftmost character position of the storage field.
(page5-7).
Item marking may be specified as in Table 5-1
An L incolurnn 7 thus results in a record mark with a DCW statement.
NOTE: If Easycoder C or D is being used, and if unusual high- and low-order
punctuation is required, the programmer may use a set II punctuation
indicator as shown in Table 5-2 (page 5-7).
The constant can be assigned a tag.
If the tag is left-justified in the location field, it is
assigned to the address of the rightmost character of the constant.
If the tag is indented one
column, it is assigned to the address of the leftmost character of the constant.
NUMERIC CONSTANTS
Numeric constants may take anyone of three forms: binary, octal, or decimal.
For
Easycoder A and B, octal and decimal constants canbe coded with a maximum length of 40 characters, while the coding associated with a binary constant is limited to a maximum of six characters.
However, for Easycoder C and D, the maximum length of the storage field :which can be
occupied by a numeric constant is 63 characters.
Decimal Constants
Signed decimal constants are specified by writing a plus or a minus sign in the first column
of the operands field, followed by the value of the constant.
When the constant is assigned to a
storage field, the assembler places the sign in the zone bits of the rightmost character of the
constant. 1 Unsigned decimal constants are written left-justified in the operands field.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~.~
LOCATION
2J 3 41 5 6 7 8
I
I
:
DE.~
OPERATION
CODE
1415
DeW
OPERANDS
I
2021
6263
80
+22
The statement above shows the decimal value of +22 defined as a decimal constant.
Binary Constants
A binary constant is actually written as a decimal entry (maximum value of 999999) which
1 See the description of sign codes beginning on page 8-7.
6-2
#2-139
SECTION VI.
DATA FORMATTING STATEMENTS
is then automatically converted to a binary value by the assembler.
The binary value is stored
(right-justified) in the constant field.
To code a binary constant the programmer writes the following:
(1) a
# sign (in the first
column of the operands field); (2) for Easycoder A or B, a number from 1 to 6 which designates
the number of six-bit characters needed to store the resulting binary value (for Easycoder C
or D, a number from 1 to 63); (3) the letter B; and (4) the decimal representation of the desired
binary constant.
Note that if the decimal representation of the binary constant is preceded by a
minus sign, the assembler stores the binary constant in twos-complement form.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
t~
~ ~
LOCATION
213 4-'5 6 7 8
I
1
:
OPERATION
CODE
1415
C~N3
oew
OPERANDS
2021
80
6263
'i'r265"¢
The statement above shows the binary equivalent of 50 defined as a binary constant to be
stored in two consecutive character locations.
Octal Constant s
Octal constants are coded in octal notation (see Appendix A).
the programmer writes the following:
(I) a
To code an octal constant
# sign (in the first column of the operands field); (2)
a number (not to exceed 20 for Easycoder A and B; not to exceed 63 for Easycoder C and D),
which specifies the number of six-bit characters required to store the octal constant;l (3) the
letter C; (4) the constant value.
Note that the value stored by the assembler is always left-
justified in the storage field.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~Ia
~ ~
LOCATION
2/3 415 617 8
I
I
:
I OCT.7
OPERATION
CODE
1415
DeW
OPERANDS
6263
2021
80
~2C1777
I
In the statement above, the octal value of 7777 is shown defined as an octal constant to be
stored in two consecutive character locations.
1Recall that an octal digit can be represented as three bits; thus each six-bit character used to
store an octal constant contains two octal digits. For example, an octal constant composed of
six octal digits can be stored in a three -character field.
6-3
#2-139
SECTION VI.
DATA FORMATTING STATEMENTS
ALPHANUMERIC CONSTANTS
Alphanumeric constants may be coded in one of three ways:
1.
Constants (including special symbols and blanks) may be written with the
constant value enclosed in @ symbols (see the first entry below).
2.
If the @ symbol is required in the constant, this constant is enclosed in
any unused character other than blank, +, -, # (and F, for Easycoder D')
or the digits 0 through 9 (see the second entry below).
3.
A number sign (#) is followed by a number from 1 through 56 which specifies the number of alphanumeric characters contained in the constant;
this number is, in turn, followed by the letter A and the alphanumeric
constant (see the third entry below). 1
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE: _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~~
~~
LOCATION
1 213 415 6 7 8
I
:
I
I
J
OPERATION
CODE
1415
OPERANDS
2021
6263
COS!
'DeW
1\t.2., , 208 • 6¢@
L
I
RA1'=
'oew
~SIXDOLL~,~S/HR%
: I
DATE
QC.W
c:t:"4AIQ65
I
1
80
1
NOTE: The maximum number of alphanumeric characters which can be contained in the constant, of course, depends on the number of card columns available in the operands field. Thus it should be remembered
that methods I and 2, above, require two card columns to format the
constant, while method 3 requires either three or four columns.
BLANK CONSTANTS
The DeW statement may be used to reserve a field of blanks with a word mark in the leftThe programmer writes a # symbol (in the first column)
most character position of the fieldo
followed by a decimal value (from 1 to 40 for Easycoder A or B, from 1 to 63 for Easycoder C
or D) which indicates the number of blank storage positions desired.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
~ ~;
NUMBER ~~
LOCATION
1 213 41s 6 7 8
I
1
:
BlA tJK
OPERATION
CODE
1415
DeW
OPERANDS
2021
1
1
1
80
6263
~Zl
I This third method of coding alphanumeric constants is applicable only when using Easyooder
Cor D.
6-4
#2-139
SECTION VI.
DATA FORMATTING STATEMENTS
The DCW statement above defines a 21-character blank field.
The address assigned to this
field by the assembler will be inserted in an object-program instruction whenever the tag BLANK
appears in another symbolic-program entry.
FLOATING-POINT CONSTANTS
A floating-point constant is written as a decimal entry which is then automatically converted by the assembler to a fixed-length floating-point value, viz., a six-character binary
mantissa followed by a two-character power-of-two exponent.
To code a floating-point constant the programmer writes the following:
1.
The letter F.
2.
A decimal number, the mantissa which may be signed or unsigned and
which may contain amaxim.um of 11 digits with or without a decimal point.
3.
The letter E.
4.
A decim.al number, the exponent, which must be between 0 and 616, inclusive, and may be signed or unSigned.
If an exponent of zero is desired, the letter E and the decimal num.ber which follows it are not
required.
NOTE: If the m.antissa and/or the exponent is preceded by a minus sign, the
assem.bler stores the corresponding value in twos-com.plem.ent form..
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
!l
LOCATION
1 213 415 6 7 8
I
OPERATION
CODE
1415
IQew
:
FCO~I
I
I
I
I
I
FeO~3
oew
FCO~,4
:
i
FCO~5
b,ew
Dew
I
I
I
FCo~e
'oew
OPERANDS
2021
6263
80
~~.3SqE2
5:,
F+4- 3
E· I
FI
F- .d¢,¢1
F- \ E-4
The first two entries above (FCONI and FCON2) result in the sam.e floating-point value
1>
when converted by the assem.bler.
FCONI uses a decimal point while FCON2 arrives at the
sam.e result by using a negative exponent.
I
This is also true for FCON4 and FCON5.
Define Constant - DC
The DC statem.ent is functionally the same as the DCW statement, the only exception being
the absence of autom.atic word marking.
This statement may thus be used in place of the DCW
6-5
#2-139
SECTION VI.
DATA FORMATTING STATEMENTS
statement if a constant is to be stored without a word mark in its leftmost character position.
The programmer, however, may still specify item m.arking as shown in Table 5-1 (page 5-7).
NOTE: If Easycoder C or D is being used, and if unusual high- and low-order
punctuation is required, the programmer may use a set II punctuation
indicator as shown in Table 5-2 (page 5-7).
Reserve Area - RESV
Use of the RESV statement enables the programmer to reserve an area of memory.
Un-
like the DC and DCW statements (which cause data to be loaded into an area reserved by the
assembler), the RESV statement does not normally alter the contents of the area defined.
Rather,
it simply sets aside a storage area to which the programmer can refer by a symbolic tag.
The
reserved area can be cleared to zeros by means of the CLEAR statement (see page 7 -19).
The
number of characters in the reserved area must be specified in the operands field of the RESV
statement.
NOTE: When used with Easycoder A or B, the RESV statement must contain
a nonzero value in the operands field.
A symbolic tag may be written in the location field.
assigned to the rightmost location of the reserved area.
If the tag is left-justified, it is
If the tag is indented one column, it
is as signed to the leftmost location of the reserved area.
When used with Easycoder C or D, the RESV statement can not only reserve a specified
area but can also load that area with a particular character.
The character to be loaded into each
location of the reserved area is coded in the op code field immediately following a comma and the
mnemonic code.
If the mnemonic RESV is followed only by a comma, the reserved area is cleared
to blanks.
NOTE: There is no automatic word marking for the reserved areas, nor maycolumn 7 of the RESV statement be used with Easycoder A or B to set
punctuation. However, if Easycoder C or D is being used, the programmer may use a set I or II punctuation indicator (see page 5-7).
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
r~
1 213 415 6 7 8
I
1
t
I
OPERATION
CODE
LOCATION
1415
STORE
CARD
OPERANDS
2021
IRESV
1
80
6263
1
~¢
IRESV .. ~ 80
The first statement above reserves 30 consecutive character positions that can be addressed
via the tag STORE.
Note that by referring to the reserved area via a symbolic tag, the pro-
grammer need not know its actual location in memory.
The second RESV statement, assembled
by Easycoder C or D, reserves 80 consecutive locations and clears the reserved area to zeros.
6-6
#2-139
SECTION VI.
DATA FORMATTING STATEMENTS
Define Symbol Address - DSA
The DSA statement can be used to store one or two addresses, or two addresses and a
variant character, as a constant.
Any valid addres s can be stored as a constant; the length of
each address is determined by the current addres sing mode (each address will be two, three,
or four characters long).
An item mark may be specified as shown in punctuation set I, page 5-7.
In addition, the
DSA statement automatically places a word mark in the leftmost character position of the constant (thus an L in column 7 results in a record mark in this position).
NOTE: If Easycoder C or D is being used, and if unusual high- and low-order
punctuation is required, the programmer may use a set II punctuation
indicator as shown in Table 5-2 (page 5-7).
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CARD
NUMBER
~I~
t
LOCATION
~
1 213415 6 7 8
I
I
I
I
1
OPERATION
CODE
1415
PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
OPERANDS
2021
6263
.l
CODE
IQ5A
lTEM-5
STAR.
[D,~A.
lA.~G,.*
., ,•.A
80
I
i
The first statement above permits the address of the field five characters before the field
tagged ITEM to be referred to in the program by the tag CODE.
The second statement allows the stored constant consisting of the address as signed to ARG,
the address assigned to the self-reference indicator
~~,
and the variant character A (i. e., octal
21) to be referred to by the tag STAR.
Define Area - DA 1
A specified area within the main memory can be defined and reserved by using the DA
statement.
In addition to defining an area, the DA statement can also define fields and subfields
within the reserved area.
This statement can also define two or more contiguous areas if these
areas are identical in format.
In other words, the programmer uses a DA statement to provide
the as s emb1er with the following bas ic information:
1.
The number (n) and size (s) of the reserved area(s). (Both nand s can be
represented by numbers up to 4,095, depending upon the amount of memory
available. )
2.
The index register (Xm or Ym) to be associated with each reference to a
field or subfield within the reserved area(s) (optional).
1 The Define Area statement can not be employed with the Easycoder A As sembly System.
6-7
#2-139
SECTION VI.
3.
DATA FORMATTING STATEMENTS
The character R which will place a record mark one position to the
right of the rightmost reserved area (optional}.
NOTE: Additional parameters may be employed with Easycoder
C and D (see page 6-10).
A DA statement consists of a heading line which defines an area(s), plus one or more subsequent lines of coding which defines the fields and subfields within the area{s).
line can contain a symbolic tag in the location field.
The heading
If this tag begins in column B, it refers to'
the rightmost location of the entire area, exclusive of the record mark (if present); if the tag
starts in column 9, it refers to the leftmost location of the entire area. Item marks may be specified in column 7 of the heading line by using set I punctuation indicators as shown in Table 5-1
(page 5-7).
NOTE: The list of punctuation indicators specified in set II (page 5-7) cannot be
used with DA statements.
The operands field in the heading line has the following format:
~xs~_,
p
3-
R______
If a single BO-character area is to be defined, the value of nxs is IxBO.
If four identical BO-
character areas are to be defined, the value of nxs is 4xBO.
The DA statement can be indexed by writing an index register designator {from Xl through
XIS or from YI through YI5)I following the area definition.
All references to the field and sub-
fields defined in the DA statement will be automatically indexed by the specified index register,
but references to the tag assigned to the entire area will not be indexed.
For example, the state-
ment on the next page indicates that all references to the fields and subfields in the lI3-character area tagged BUFFER will be indexed by the index register X2; references to the tag BUFFER,
however, will not be indexed.
Note that the area definition nxs does not include an allowance for the character position
containing the record mark, although this position (if any) is also reserved.
will cause 320 character positions to be reserved.
For example 4xBO
If a record mark is placed one position to the
right of the last area, a total of 321 character positions is reserved.
The index register applied to a field or subfield can be changed from that specified in the
DA statement by designating a different register in the operands field pf an instruction which
1
Index registers Xl through X6 are used with Easycoder B, while index registers Xl through
XIS and Y I through Y IS can be used with Easycoder C or D.
6-B
#2-139
SECTION VI.
references the field or subfield.
DATA FORMATTING STATEMENTS
The effect of indexing on a field or subfield can be cancelled by
writing XO as the index register designator in the references in which indexing is not wanted.
As stated above, the heading line may be followed by one or more lines of coding which
define fields and subfields within the reserved area(s).
As many of these lines as necessary
may be used, and these fields and subfields may be defined in any order desired.
Positions
within each reserved area are numbered sequentially from left to right, starting with one.
The
coding line s which define fields and subfields must have blank op code fields; each such line
may contain a symbolic tag in the location field, if desired.
Fields and subfields are specified as follows:
Fields:
The lowest and highest positions of the field are written in that order in
the operands field, separated by a comma. (If a one-character field is
desired, its position number must be written twice in the operands
field, separated by a comma.) A word mark is automatically placed
in the leftmost position of the field in memory. Item marks may be
specified as shown in Table 5 -1 (page 5 -7).
Subfields: For a subfield, only the rightmost position is specified. Word marks
are not set; however, item marks may be specified as shown in Table
5-1 (page 5-7).
NOTE:
The list of punctuation indicators specified in set II (page 5-7) _can not be
used with DA statements.
The assembler does not normally clear the defined area.
However, the programmer has
the option of clearing the area to a specified character by placing a comma and the desired character after the mnemonic code DA in the op code field.
The presence of only a comma after the
op code implies that the area win be cleared to blanks.
When the defined area is cleared, all
punctuation is also cleared before setting the "field" punctuation.
The sample coding below illustrates what a DA statement might look like.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _~ PAGE_OF_
CARD
NUMBER
I
i~ II
i(DZ I
I,
~I~
~ ~
LOCATION
213 415 6 7 8
I
I
3i i
1~41
1~5:
I
i
I
r -r
i61
OPERATION
CODE
1415
SUFFE'R DA
NAME"
D,ATE
lA.GE
IY~AR
MON1H
OPERANDS
2021
6263
80
~X~8" X2,. R
\. 2fJ)~,3 29
~,I, t 2,2,
28
26
6-9
#2-139
SECTION VI.
DATA FORMATTING STATEMENTS
The heading line specifie s the following information:
1.
Four consecutive, identical areas, each 28 characters' long, will be reserved.
2.
The tags NAME, DATE, AGE, YEAR, and MONTH, when referred to in
symbolic instructions, will be indexed by index register X2.
3.
A record mark will be set in the rightmost character position of the
entire 113 -character reserved area.
4.
The entire 113-character area can be referred to via the tag BUFFER.
(This tag refers to the leftmost position of the area because it is indented. It is not automatically indexed by index register X2.)
Lines two, three, and four define fields.
each of the four identical areas.
Word marks will be set in positions 1, 21, and 23 in
Lines five and six define subfields: position 28 indicates the
year within the date, while position 26 indicates the month within the date.
EASYCODER C AND D OPTIONS
When used with Easycoder C or D, the DA statement may make use of the following parameters (in addition to the n, s, Xm, and R parameters spedfied on page 6 -8).
1.
The character P: Coding this character in the heading line of a DA statement causes the special character 728' together with an item mark, to be
placed at the end of each area as an additional character.
2.
The character G: Coding this character in the heading line causes the
special character 328' together with a record mark, to be placed one
po sition to the right of the last area.
3.
The character H: Coding this character in the heading line instructs the
a-ssembler to associate the index register (Xm or Yr:n) with each reference
to the tag in the location field of the DA statement, as well as with each
reference to a field or subfield within the reserved area(s).
NOTE: If a symbolic tag is used, it is not. automatically indexed by
the specified index register (Xm or Ym) unless parameter H
is employed. This parameter is meaningless if no index
regi ster is specified.
The format of a DA statement heading line employing all parameters is illustrated below.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.
CARD
NUMBER
I
~~
f~
LOCATION
213 415 6 7 8
I
I
:
tao..
OPERATION
CODE
1415
DA
PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
OPERANDS
2021
I
I
I
L
6263
eo
nXS.)(rn,., R.. P G ,H.
/
6-10
#2-139
ASSEMBLY
CONTROL
STATEMENTS
INTRODUCTION
Assembly control statements provide programmer control over the assembly of the source
program.
definitions.
These statements resemble data formatting statements in that they are treated as
They control such functions as the addressing mode to be used in assembling speci-
fied instructions, the assignment of absolute locations to symbolic tags, etc.
Used only during
the assembly process, assembly control statements are never executed as instructions in the
object program.
The precise function of each assembly control statement depends upon the as-
sembly system employed.
A summary of the assembly control stateITlents available with Easycoder A, B, C, and D,
together with the page where each stateITlent is defined, may be found in Table 7 -1.
In addition,
the heading of each statement in this section includes a table which indicates the assembly systems that may use that particular statement.
Table 7 -1.
Program Header
Execute
7-Z2
7- 5
As sem.bly Control Statements
Program Header
Execute
7-2
7-5
Program Header
7-3
Program Header
7-3
Segment Header
7-4
Segment Header
7-4
Execute
7-6
Execute
7-6
Transfer
7-6
Transfer
7-6
Origin
7-7
Origin
7-8
Origin
7-8
Origin
7-8
Modular Origin
7- 9
Modular Origin
7-9
Modular Origin
7-9
Modular Origin
7-9
Literal Origin
7-10
Literal Origin
7-10
Literal Origin
7-10
Admode
7-11
Admode
7-12
Admode
7-12
Admode
7-11
Equals
7- 12 Equals
7-12
Equals
7-13
Equals
7-13
Control Equals
7- 13
7-13
Control Equals
7-14
Control Equals
7-14
Memory Dump
7-14
Control Equals
7-1
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
Table 7 -1 (cont).
Assembly Control Statements
Skip
7-15
Skip
7-15
Suffix
7-15
Suffix
7-15
Repeat
7-16
Repeat
7-16
Generate
7-17
Generate
7-17
Set Line Number
7-18
Set Line Numbe r
7-18
Set Out-ofSequence Base
7-18
Set Out-ofSequence Base
7-18
Clear
7-19
Clear
7-20
Clear
7-20
Clear
7- 20
End
7-21
End
7- 21
End
7- 22
End
7- 22
Program Header
PROG
The program header must be the first entry in a symbolic program.
This statement is
coded as follows for the various assembly systems.
EASYCODER A
The letters PROG must be written in the op code field, and the operands field must contain
a name which identifies the program. (This name will appear in the program listing.) Optionally,
an "S" can be placed in column 6; this action specifies that a check is to be made on the card
number sequence of the input deck.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
I~I~ LOCATION
I~ ~
213 415 6 7 8
I
I
i~
OPERATION
CODE
1415
PR06
OPERANDS
2021
6263
80
SERIES
1
In the sample statement above, SERIES is specified as the program name, while the letter
S in column 6 designates that a sequence check is desired.
EASYCODER B
The letters PROG must be written in the op code field, and the operands field must contain
a name which identifies the program.
(This name will appear in the program listing.) Optionally,
an "S" can be placed in column 6; this action specifies that a check is to be made on the card
number sequence of the input deck.
7-2
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
In addition, the desired object-program format is specified by the entries in columns 61
and 62.
Blanks in these two columns specify that the machine -language output is to appear in
the condensed-card self-loading format.
Placing the letters BR in these columns specifies that
the machine -language program is to appear on punched cards in BR T format.
(See Easycoder
B Assembly System, Order No. OIl.)
NOTE: When BRT format is specified, a segment number of 01 is generated by
the assembler for the first segment (memory load) following the program header. If Execute statements (see page 7 - 5) appear in the symbolic program, subsequent segment names are ,generated by incrementing the previous segment number by one.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
1 213 415 6 7 8
I
1
OPERATION
CODE
LOCATION
1415
PROG
: S
OPERANDS
2021
1
1
80
6263
BR
SER I E~
I
The statement above designates SERIES as the program name and specifies that a sequence
check is to be performed.
As columns 61 and 62 contain the letters BR, the output will appear on
punched cards in BR T format.
EASYCODER
e
As used in Easycoder C, the program header provides program identification; in addition,
however, thi s statement serve s as the all-i:rnportant
II
action director" statement.
For thi s
reason, the programmer should refer to the Honeywell publication Easycoder Assemblers C and
D, Order No. 041 for a detailed description.
EASYCODER D
As used in Easycoder D, the program header provides progra:rn identification; in addition,
however, this statement serves as the all-i:rnportant "action director" state:rnent.
For this
reason, the programmer should refer to the Honeywell publication Easycoder Assemblers C and
D, Order No. 041.
If the programmer desires to use the alternate card format (which allows room for tags
consisting of up to ten characters, see page 5-10), column 75 of the program header card must
contain the letter A.
The PROG card itself, however, is
~
coded in the alternate format:
the letters PROG always appear in the op code field (columns 15 through 18), while the name of
the program always appears beginning in column 21.
7-3
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
NOTE: If the alternate format is specified, all cards following the program
header, up to and including the END ~rd, must be coded in the alternate
format.
Segment Header
A
B
SEG
Programs written for Easycoder C or D may be divided into two or more segments, each
of which is loaded into memory and executed as a unit.
It is the function of the SEG statement
to define the beginning of each segment (memory load).
Use of the SEG statement is optional,
however.
If used, a SEG statement must follow the program header, each Execute statement
and each Transfer statement.
If it is desired to omit this statement, it must be omitted from
the entire program; in this case the assembler generates segment identifications (starting with 01).
EASYCODER C AND D
The letters SEG must be placed in the op code field, while the operands field must contain
a two -character segment identification.
This segment identification becomes appended to the
program name to forIn a unique search code.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
~I~
~ ~
213 415 6 7 8
I
I
:
LOCATION
OPERATIO'N
CODE
1415
'3EG
OPERANDS
80
6263
2021
AA
1
In the example above, AA could represent the first segment of a program, in which case
this entry would follow the program header.
Execute
EX
The end of a memory load is indicated by an EX statement.
When the coding inserted by
the assembler for the EX statement is encountered during the loading process, a branch to the
location specified in the operands field results.
This operation enables portions of the program
to be executed before the entire program has been loaded.
The coding to be executed must ap-
pear prior to the EX statement.
7-4
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
EASYCODER A
The letters EX must be written in the op code field; the operands field contains a direct
address, either absolute or symbolic.
(If an EX statement is written with a blank operands field,
the machine will halt when it encounters the corresponding coding during the loading operation. )
To resume the loading operation, the last instruction in the portion of the program executed must be a Branch instruction which provides re-entry to the load routine.
In addition,
the first instruction of the executed routine should be an SCR (Store Control Registers) instruction which stores the contents of the B-address register in the A address of the return Branch
instruction.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~~
~ ~
OPERATION
CODE
LOCATION
1415
1 2[3 415 6 7 8
I
1
i
r
EX
I
OPERANDS
I
2021
80
6263
SEC3
I
I
The sample statement above illustrates an EX statement with a symbolic address in the
operands field.
When the corre sponding coding is encountered during the loading operation, pro-
gram loading is tem.porarily halted
a~d
the portion of the program. beginning at the location tagged
SEC3 is executed.
EASYCODER B
The letters EX m.ust be written in the op code field; the operands field contains a direct
address, either absolute or sym.bolic.
(If an EX statem.ent is written with a blank operands field,
the m.achine will halt when it encounters the corresponding coding during the loading operation. )
To resume the loading operation, the last instruction in the portion of the program. executed
m.ust be a Branch instruction which provides re -entry to the load routine.
In addition, the first
instruction of the executed routine should be an SCR (Store Control Registers) instruction which
stores the contents of the B-address register in the A address of the return Branch
instructio~.
Besides causing a branch to the program.m.er I s coding, use of the EX statem.ent causes any
literals us ed in the m.em.ory load to be loaded and the literal table to be cleared.
If a LITORG
statem.ent (see below) does not precede the EX statem.ent, literals are allocated im.m.ediately
following the in-line coding for the m.em.ory load.
7-5
#2-139
SECTION VII.
NOTES: 1.
2.
ASSEMBLY CONTROL STATEMENTS
Following an EX statement, a new segment number is generated as
explained above in the description of the program header.
With Easycoder B, the total of the numbers of Execute: Lite.ral
Origin, and End statements must not exceed 31.
See the sa:mple state:ment given above for Easycoder A.
EASYCODER C AND D
The letters EX must be written in the op code field; the operands field must contain a
direct address, either absolute or s'ymbolic.
When used with these assemblers, the EX state-
ment enables a progra:m to be loaded and executed one segment at a time.
the last must end with either an EX or an XFR statement.
Each segment except
When an EX state:ment is encountered,
all literals preceding the EX statement which have not been allocated to me:mory are allocated in
sequence, and the literal table is cleared.
Note that it is the responsibility of the programmer to provide re-entry to the load routine.
The :methods of returning to the applicable loader are described in the pertinent Honeywell publication - e. g., Card Loader-Monitor B (Order No. 154) or Tape Loader-Monitor C (Order No. 221).
See the sample statement giyen above for Easycoder A.
Transfer
A
B
XFR
For Easycoder C and D users, the end of a memory load may be indicated by an XFR statement instead of an EX state:ment.
Both statements perform essentially the same functions; the
one exception is that use of the XFR statement does not result in the allocation of literals or in
the clearing of the literal table.
When the coding inserted by the assembler for the XFR state:ment is encountered during
the loading process, a branch to the location specified in the operands field results.
This oper-
ationenables portions of the program to be executed before the entire program has been loaded.
EASYCODER C AND D
The letters XFR :must be written in the op code field; the operands field must contain a
direct add-ress, either absolute or symbolic.
loaded and executed one segment at a time.
Use of this statement enables a program to be
Each segment except the last must end with either
an XFR or an EX statement.
NOTE: It is the responsibility of the programmer to provide re-entry to the
load routine.
7-6
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
~I~
~ ~
LOCATION
1415
213 415 6 7 8
I
1
OPERATION
CODE
OPERANDS
XFR
1
6263
2021
80
SEC4
I
The sample statement above illustrates an XFR statement with a symbolic address in the
operands field.
When the corresponding coding is encountered during the loading operation,
program loading is temporarily halted and the portion of the program beginning at the location
tagged SEC4 is executed.
Origin
ORO
The ORG statement is used to modify the normal memory allocation process of assembly.
This statement can be inserted anywhere in the source program to indicate to the assembler
that all subsequent coding (instructions, constants, work ar,eas, etc.) should be assigned sequential memory locations starting with the location whose addres s is specified in the operands
field.
A program is normally allocated memory space beginning at location 0.
If it is desired to
assign memory space starting at some location other than 0, an ORG statement m.ust be inserted
in the program immediately foilowing the program header.
EASYCODER A
The letters ORG are written in the op code field, and an address (either absolute or symbolic) is written in the operands field.
(If the address is symbolic, the tag must appear in the
location field of a previous source-program entry.) The address specified in the operands field
is as signed the tag (if any) in the location field; if this tag appears, it must not- be indented.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
~ ~
1 2.13 4JS 6 7 8
I
1
1
J
I 1
I
LOCATION
OPERATION
CODE
1415
OPERANDS
2021
ORG
75Jl
ORe,
ORTAG
6263
1
80
I
1 1
7-7
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
The first statement above indicates to the assembler that all subsequent entries should be
assigned sequential addresses beginning with location 750.
The second statement directs the
asseinbler to assign to all subsequent entries sequential addresses beginning with the address
that is assigned to the tag ORTAG.
source-program
entry~
(ORTAG must appear in the location field of a previous
)
EASYCODER B
The letters ORG are written in the op code field, and an address (either absolute or symbolic) is written in the operands field.
(If the address is symbolic, the tag must appear in the
location field of a previous source-program entry.) The address specified in the operands field
is assigned the tag (if any) in the location field; if this tag appears, it must not be indented.
NOTE: When the BRT punched-card format is specified, an ORG statement must
be included immediately following the PROG statement with an address of
1, 000 (decimal) or above.
See the sample statements given above for Easycoder A.
EASYCODER C AND D
The letters ORG are written in the op code field, and an address (either absolute or symbolic) is written in the operands field.
If the addres s is symbolic, the tag must appear in the
location field of another (not necessarily previous) source-program entry.
be written in the location field.
written in the operands field.
A symbolic tag may
If this tag begins in column 8, it is assigned to the address
If it begins in column 9, the tag is assigned to the location at which
the next instruction would have begun had the ORG statement not been present.
NOTE:
Care must be taken so that the address in the operands field is a decimal
number of I, 000 or above if Card Loader-Monitor B is used to load the
object program. If Tape Loader-Monitor C or Drum Bootstrap-Loader
C is used, this decimal number must be 1,340 or above.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
!I~
1 213 415 6 7 8
I
I
:
LOCATION
OPERATION
CODE
1415
'DENT IQRe,
OPERANDS
2021
80
6263
7a~~
1
In the example above, assume that the instruction preceding the ORG statement was assigned to locations 5000 through 5007.
The next instruction w,ould normally begin at location 5008.
The tag IDENT, since it begins in column 9, is thus assigned to location 5008, and the next instruction is stored beginning at location 7800.
7-8
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
Modular Origin
MORG
The modular origin statement is similar to the ORG statement described above.
The
MORG statement indicates to the assembler that all subsequent entries should be assigned sequential addresses starting with the next available location whose address is a multiple of the
number written in the operands field of the MORG statement.
The entry in the operands field
must represent a power of two (e. g., 2, 4, 8, 16, 32, •••••• 4,096, etc.).
EASYCODER A AND B
The letters MORG are written in the op code field, and a number (a power of two) is placed
in the operands field.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _----'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I>ROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
~I~
~ ~
LOCATION
1 2J3 ~5 6 7 B
I
I
:
OPERATION
CODE
1415
OPERANDS
2021
IMORG
6263
80
2>2
1
The statement above indicate s to the as sembler that all subsequent entries should be assigned sequential addresses beginning with the next available location whose address is a multiple
of 32.
EASYCODER C AND D
The letters MORG are written in the op code field, and a number (a power of two) is placed
in the operands field.
A symbolic tag may be written in the location field.
colurrm 8, it is assigned to the address written in the operands field.
If this tag begins in
If it begins in column 9,
the tag is assigned to the location at which the next instruction would have begun had the MORG
statement not been present (see the sample statement given above for the ORG statement).
Literal Origin
LITORG
The literal origin statement is similar to the ORG and MORG statements described above.
The LITORG statement specifies to the assembler that all previously used literals should be
assigned sequential memory locations starting with the location specified in the operands field.
7-9
#2-139
SECTfON VII.
ASSEMBLY CONTROL STATEMENTS
Care :must be taken to ensure that literals can be referenced by the instructions which use
the:m; e. go, a literal stored in one 4K bank :may not be addressed in the two-character :mode
fro:m another bank.
EASYCODER B
Tn.e op code field :must contain the letters LITORG, while the operands field contains an
address (either absolute or symbolic).
location field of a previous entry.
literal table to be cleared.
If a sy:mbolic tag is used, it :must have appeared in the
Like the EX state:ment, the LITORG statement causes the
Also, locations below 1,000 (decimal) must not be used when BRT
punched-card output is specified in the FROG statement.
A symbolic tag may be written in the location field.
assigned to the address written in the operands field.
If this tag begins in column 8, it is
If it begins in column 9, the tag is as-
signed to the location at which the next instruction would have begun had the LITORG statement
not been present.
NOTES:
1.
In the absence of a LITORG statern.ent, all of the generated coding
associated with a :memory load is allocated immediately following
the in-line coding.
2.
With Easycoder B, the total of the number of Execute, Literal
Origin, and End state:ments :must not exceed 31.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _~_ _ PAGE _ O F _
CARD
NUMBER
~I!
LOCATION
1 2-' 3 415 6 7 8
I
!
:
LIT
OPERATION
CODE
1415
2021
OPERANDS
6263
I
80
11.,1 TORG 15$¢
I
In the LITORG statement above, the assembler is directed to assign sequential addresses
starting with location 1550 -
to all previously encountered literals.
This location is also
tagged LIT, since the tag begins in colu:mn 8.
EASYCODER C AND D
The op code field :must contain the letters LITORG, while the operands field contains an
address (either absolute or symbolic).
If a symbolic tag is used, it must have appeared in the
location field of another, not necessarily previous, entry.
state:ment causes the literal table to be cleared.
Like the EX statement, the LITORG
Also, locations below 1,340 (deci:mal) must
not be used.
A sy:mbolic tag :may be written in the location field.
assigned to the address written in the operands field.
If this tag begins in column 8, it is
If it begins in colu:mn 9, the tag is assigned
to the location at which the next instruction would have begun had the LITORG statement not
been present.
7-10
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
NOTE: In the absence of a LITORG statement, all of the generated coding
associated with a memory load - except for a memory load terminated by an XFR statement - is allocated immediately following the
in-line coding.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ . _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
I
I
i
i
OPERATION
CODE
LOCATION
~ ~
1 213 415 6 7 8
1415
LIT
OPERANDS
2021
80
6263
ILl TORG ~ 750
I
I
I
I
I
I
IDE.NT L I TORG 2000
In the first LITORG statement above, the assembler is directed to assign sequential addresses, starting with location 1750, to all previously encountered literals.
for thi s statement, LIT, begins in column 8.
Note that the tag
As sume, in the second statement above, that the
instruction preceding the LITORG statement was as signed to locations 450 through 457.
instruction would normally begin at location 458.
The next
The tag IDENT, since it begins in column 9, is
thus assigned to location 458, and previously encountered literals are assigned sequential addresses starting with location 2000.
Set Address Mode
ADMODE
This statement specifies the addressing mode into which all subsequent instructions are to
be assembled (i. e., two-, three-, or four-character).
(All machine instructions, as well as the
DSA data formatting statement, are affected by the address mode.) The mode of address assembly specified in this statement remains in effect until another ADMODE statement, specifying
a different mode of assembly, is encountered.
Because the ADMODE statement concerns itself only with the source program, it should be
used in conjunction with the CAM (Change Addressing Mode) instruction (see page 8-62).
The
CAM instruction specifies the addressing mode in which the machine is directed to interpret the
-address portions of all subsequent object-program instructions.
EASYCODER A and B
The letters ADMODE are placed in the op code field.
The operands field contains either
a 2 or a 3 to denote whether all subsequent instructions are to be assembled in the two-character
7-11
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
or the three-character addressing :mode.
If an ADMODE state:ment is not included at the begin-
ning of the source progra:m, asse:mbly begins in the two -character addressing :mode.
(It should
be a general rule, however, to include an ADMODE state:ment at the outset of every progra:m. )
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
~ ~
1 213 415 6 7 8
I
1
LOCATION
OPERATION
CODE
1415
OPERANDS
2021
80
6263
IAOMODE2
I
1
1
i i
IADMODE3
I
The asse:mbler upon encountering the first state:ment above will asse:mble the address
portions of all subsequent instructions as two-character addresses.
The second statement, if
encountered later in the sa:me source progra:m, will cause the assembler to change to threecharacter address asse:mbly.
EASYCODER C AND D
The letters ADMODE are placed in the op code field.
The operands field contains either
the nu:mbers 2, 3, 4, or a sy:mbolic tag to denote whether all subsequent instructions are to be
asse:mbled in the two-, three-, orfour-characteraddressingrnode. !fa symbolic tag is used, it
:must have been previously defined to have a value of 2, 3, or 4.
If an ADMODE statement is not
included at the beginning of the source progra:m, three-character addressing is assumed by the
assembler.
(It should be a general rule, however, to include an ADMODE statement at the outset
of every progra:m.) See the sample statements given above for Easycoder A and B.
Equals
EQU
The EQU state:ment assigns the sy:mbolic tag written in the location field to the address
(absolute or sy:mbolic) written in the operands field.
This state:ment thus :makes it possible to
use different sy:mbolic tags in different parts of the source progra:m to refer to the sa:me :me:mory
location.
EASYCODER A and B
The location field contains a sy:mbolic tag, while the op code field contains the letters EQU.
The operands field contains the address to which the sy:mbolic tag in the location field is to be
assigned. (Each sy:mbolic tag written in the operands field :must appear in the location field of
a previous source-progra:m entry. )
7-12
#2-139
SECTION VlI.
ASSEMBLY CONTROL STATEMENTS
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
1
i
r~
~ ~
LOCATION
I
I
I
OPERATION
CODE
1415
[3 415 6 7 8
OPERANDS
1
2021
TITLE
I(QU
NAME
QUA.N
EQU
IAMT-2.0.
80
6263
I
i
i
The first EQU statement above causes the assembler to assign the tag TITLE the same
location as signed the tag NAME.
to the contents of this location.
Thus, the programmer can use either of these two tags to refer
The second statement employs relative addressing.
The as-
sembler will assign the tag QUAN to the location specified by address arithmetic as AMT-20.
EASYCODER C AND D
The location field contains a symbolic tag, while the op code field contains the letters EQU.
The operands field contains the address to which the symbolic tag is to be assigned.
A symbolic
tag written in the operands field must appear in the location field of another (not necessarily
previous) source program entry.
See the sample statement given above for Easycoder A and B.
Control Equals
CEQU
The CEQU statement assigns the symbolic tag w.ritten in the location field to the value
written in the operands field.
It is frequently used to assign a tag (containing a minimum of two
characters) to a variant character or to a group of input/ output control characters.
EASYCODER A AND B
The location field contains a symbolic tag, while the op code field contains the letters
CEQU.
The operands field contains an octal value; this entry is coded as an octal constant and
may contain up to 12 octal digits.
The symbolic tag in the location field is as signed to thi sentry.
NOTE: A description of octal constants may be found under the heading "Define
Constant with Word Mark - DCW" (see page 6-2).
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
LOCATION
1 2/3 415 6 7 8
I
f
I
I
OFLOW
OPERATION
CODE
1415
CEQU
BeT
OPERANDS
2021
6263
80
~IC50.
SUB2.~
OFLOW
7-13
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
The sample coding above illustrates how a symbolic tag can be used in place of a variant
character.
value 50.
The CEQU statement directs the assembler to equate the tag OFLOW to the octal
The second line of coding contains a branch
instl~uctiun
which specifies that a program
should branch to the location tagged SUB2 if the condition specified by the variant character
tagged OFLOW is present.
EASYCODER C AND D
The location field contains a symbolic tag, while the op code field contains the letter s
CEQU.
The entry in the operands field must be a decimal, binary, octal, or alphanumeric con-
stant (the octal format is most commonly used).
Regardless of the constant used, however, the
resultant value must not exceed four characters in length.
NOTES: 1.
Instructions which refer to the tag defined by the CEQU statement
must not precede the CEQU statement.
2.
A description of constants may be found under the heading "Define
Constant with Word Mark - DCW" (see page 6-2).
See the sample statement given above for Easycoder A and B.
BCD
Memory Dump
HSM
The HSM statement may be used with Easycoder A to produce a punched card deck containing the Memory Dump routine.
This card deck can be loaded into memory to obtain a printed
listing of the contents of any portion of main memory.
This statement must be coded immediately
preceding the CLEAR and END statements in the source program (see below).
EASYCODER A
If the punched card deck {containing the Memory Dump routine} is to be loaded into a spe-
cific memory area, the start of this area can be specified by a tag in the location field of the
HSM statement.
A blank location field causes the Memory Dump routine to be loaded into the
area following the location assigned to the last character in the object program.
HSM 1p.ust be written in the op code field.
The letters
The operands field contains the addresses of the first
(low) and last (high) locations in the memory area whose contents are to be listed by the Memory
Dump routine.
7-14
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
il~
LOCATION
1 213 4.l5 6 7 8
I
I
OPERATION
CODE
1415
t
OPERANDS
2021
H5,M
J
i.
80
6263
START 3-.S.TOP
+8
,
1
The HSM statement above specifies that the area whose contents are to be listed begins at
the location tagged START and ends three locations beyond the location tagged STOP.
As the
location field is blank, the Memory Dump routine will be stored in the area following the location
assigned to the last character in the object program.
~
~
A
B
Easycoder assemblers normally single...,space an assembly listing and skip to the head of
the next form when a page becomes filled.
The SKIP statement enables the programmer to con-
trol the vertical spacing of the assembly listing by causing as many as 15 lines to be skipped.
EASYCODER C AND D
The letters SKIP are placed in the op code field.
The operands field contains either a
number from 1 to 15 (to indicate the total number of line s to be skipped) or the letter H (which
causes the printer to skip to the heacl of the next form).
NOTE:
The as sembler automatically skips to the head of the form for each
new segment.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
~ ~
1 2J3 ~5 6 7 8
I
I
1
LOCATION
OPERATION
CODE
1415
SKI P
OPERANDS
2021
-L
80
6263
9
J
In the sample coding above, the assembler is directed to skip 9 lines on the program listing.
A
Suffix
B
SFX
The SFX statement directs the assem,bler to append the single-character suffix in the
7-15
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
operands field to each tag of five characters or less contained in the following coding.
This
technique enables the programmer to assign unique tags for each segment of a program and thus
guard against double definition of a tag between distinct segments of a program.
segment referencing within a program is required, six-character tags may be assigned.
This operation continues until the occurrence of another SFX statement with a blank
operands field, or until the END statement is encountered.
EASYCODER C AND D
The letters SFX are placed in the op code field.
A single-character suffix is written in
the operands field.
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ OATE _ _ _ _ _ _ PAGE_OF_
~~
CARD
NUMBER
I
LOCATION
~ ~
1415
213 415 6 7 8
:
I
1
TOTAL
I
OPERATION
CODE
OPERANDS
2021
I
_L
I
SFX
E
A
F I C. A+ TOTAX,-
80
6263
20
In the above example, the assembler interprets the Add instruction following the SFX
statement as: TOTALE A FICAE+TOTAXE-20.
A
Repeat
B
REP
This statement directs the assembler to repeat the following data formatting statement the
number of times specified in the operands field.
The nUITlber of tiITles a stateITlent is repeated
includes the original stateITlent and may not exceed 63.
The assembler repeats the statement
without variation, except that any entry in the location field is not repeated.
EASYCODER C AND D
The letters REP are written in the op code field.
The operands field designates the num-
ber of times the following statement is to be repeated (including the original statement).
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE_OF_
CARD
NUMBER
l ~I
LOCATION
~ ~
I- 2.13 415 6 7 8
I
1
:
J
OPERATION
CODE
1415
R,EP
OC.TS6
DeW
OPERANDS
2021
I
6263
I
80
6
#2C6
7-16
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
In the sample statement above, REP is employed to define six identical constants of octal
value 6000.
A
Generate
B
GEN
This statement directs the assembler to generate the instruction which follows a specified
number of times, incrementing or decrementing the operands of the instruction as specified by
the operands field of the GEN statement.
The GEN statement can apply to machine instructions
with formats containing a single address, both addresses, a single address and one variant
character, or both addresses and one variant character (only one variant character is allowed).
EASYCODER C AND D
The letters GEN are written in the op code field.
The operands field contains the pa-
rameter specifying the number of times the statement (which follows) is to be generated, including the original statement.
statement.
This number is followed by a modifier for each operand in the model
These modifiers speci.£y the increment (froIn 0 to +63) or decrement (froIn -63 to 0)
to be applied to each of the operands each time the statement is generated. There must be a modifier for each operand in the model statement (including the variant character, if any), and the
modifiers must appear in the same order as the operands.
~ntered
If no modification is desired, 0 is
as the modifier.
EASYCODER
CODING FORM
~~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ - - - - PAGE_OF_
PROBLEM
CARD
NUMBER
~I~
LOCATION
~ ~
1415
1 213 415 6 7 8
I
I
I
I
:
I
I
I
OPERATION
CODE
GEN
ewe
BeE
TABLE IRE"SV
OPERANDS
2021
'¢. +4,. +6.0
SEL.~
~
I
TABLE
80
6263
8
160
In the example above, the GEN statement generates a series of 10 instructions that will
branch to a location SEL, SEL+4, SEL+8, ••••••• or SEL+36, provided that an 8 is present
in the first character of the corresponding item in a table containing 10 six-character items.
The tag SWC is assigned to the leftmost character of the first generated instruction.
statement itself must not be
The GEN
tagged~
NOTE: The second BCE instruction generated by the example is BCE/SEL+4,
TABLE+6,8; the third instruction generated is BCE/SEL+8, TABLE+IZ,8;
and so on. The tenth instruction generated is BCE/SEL+36, TABLE+54,8.
7-17
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
A
Set Line Number
B
SETLIN
This instruction is used to control the generation of line numbers by the assembler.
EASYCODER C AND D
The letters SETLIN are written in the op code field, while the first five colunms of the
operand field contain the de~ired line number.
The assembler replaces the contents of the line
number generation counter with the number in the operands field of the SETLIN statement.
statement is effective only when the assembler is generating line numbers.
This
It is important to
note that all of the first five columns in the operands field must be punched with a decimal number (i.
e.,
leading zeros are required).
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
t~
NUMBER ~ ~
LOCATION
I' 2 3 4 5 6 7 8
I
I
iI
:
1
OPERATION
CODE
1415
,
OPERANDS
80
6263
2021
SETLtN 100~8QS.
(/}0
8
I
In the example above, the SETLIN statement causes the instruction which follows it (B/OO)
to be assigned a line number of 00080.
A
Set Out-of-Sequence Base
B
XBASE
The XBASE stateITlent establishes the out-of-sequence base (OSB).
the OSB is a base address for the storage of out-of-sequence coding.
As its name implies,
Such coding may be allocated
or referred to (l) by means of the address code' (apostrophe) in the location field (see page 5-9);
or (2) by means of the addre,ss code' (apostrophe) in the operands field (see page 5-15).
EASYCODER C AND D
The letters XBASE are written in the op code field.
The operands field contains the value
(absolute or symbolic) to which the assembler is directed to set the out-of- sequence base (OSB).
If a symbolic tag appears in the operands field it must have appeared in the location field of a
previous source-program entry.
7-18
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
EASYCODER
CODING FORM
PROBLEM.
..
H~
CARD
NUMBER
~.~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
I
1
1415
~l
'275
I
1
OPERATION
CODE
LOCATION
~ ~
1 213 415 6 7 8
tj
OPERANDS
2021
XBASE
5fJ0
oew
@CON@
1
80
6263
1
i
In the above example, the out-of-sequence base (OSB) is set to 500 by the XBASE state-
ment.
When the second entry is encountered, the assembler assigns the rightmost character of
the constant CON to location 775 (500
+ 275).
Clear
CLEAR
The CLEAR statement enables the programmer to specify an area of memory which is to
be cleared of punctuation before the object program is loaded.
to zeros or to a given character.
The memory area is also cleared
It is not necessary to clear areas which will be used to store
the obj ect program.
EASYCODER A
The op code field contains the letters CLEAR, while the operands field contains the addresses (either absolute or symbolic) of the first (low) and last (high) locations in an area to be
cleared.
If a comma is written immediately following the second address, the character written
in the column after the comma is loaded into all locations in the cleared area.
If two addresses
are written in the operands field and are not followed by a comma and a character, the specified
area is cleared to zeros.
A number of CLEAR statements may be written (in sequence) immediately preceding the
END statement, provided that the total number of HSM, CLEAR, and END statements doe s not
exceed 10.
NOTE:
The 80-character loading area specified in the END statement must
never be cleared.
EASYCODER
CODING FORM
PROBLEM----_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
~~
1 213 415 6 7 8
I
1
I
i
I
LOCATION
OPERATION
CODE
1415
OPERANDS
2021
6263
80
CLEAR CAMT. EAMT
I
CLEAR
aa4 .. o79... J
7-19
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
The first CLEAR statement above specifies that the area beginning at the location tagged
CAMT and ending at the location tagged EAMT is to be cleared to zeros.
The second CLEAR
statement clears the area beginning at location 3-34 and ending at 379 to 46 Ji S •
EASYCODER B
The op code field contains the letters CLEAR, while the operands field contains the addresses (either absolute or symbolic) of the first (low) and last (high) locations in an area to be
cleared.
If a comma is written immediately following the second address, the character written
in the column after the comma is loaded into all locations in the cleared area.
If two addresses
are written in the operands field and are not followed by a comma and a character, the specified
area is cleared to zeros.
A maximum of nine CLEAR statements may be included in a program.
In addition, no
coding may appear between the last symbolic CLEAR statement and the END statement.
NOTE: The loading area specified in the END statement must never be cleared.
See the sample statements given above for Easycoder A.
EASYCODER C AND D
The op code field contains the le,tters CLEAR, while the operands field contains the addresses (either absolute or symbolic) of the first (low) and last
cleared.
(h~gh)
locations in an area to be
If a comma is written immediately following the second address, the character written
in the column after the comma is loaded into all locations in the cleared area.
If two addresses
are written in the operands field and are not followed by a comma and a character, the specified
area is cleared to zeros.
As many CLEAR statements as necessary can be included in a pro-
gram.
NOTE: The programmer must exercise caution in the physical placement of the
CLEAR statement, as the clearing is performed by the Loader at the
time the CLEAR statement is encountered.
See the sample statements given above for Easycoder A.
fEndl
~
The last source program instruction must be the END statement, which indicates to the
assembler that the end of the source program has been reached.
7-20
#2-139
SECTION VII.
ASSEMBLY CONTROL STATEMENTS
EASYCODER A
The location field may contain an address (either absolute or symbolic) which specifies the
initial location in an SO-character loading area.
If the lo.cation field is left blank, the asseITlbler
automatically reserves an SO-character loading area following the location assigned to the last
character in the object program.
The op code field contains the letters END.
If it is desired to execute the object program
immediately after loading, the operands field must contain the address (either absolute or
symbolic) at which the object program is to begin.
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
~I~
~ ~
LOCATION
I
OPERATION
CODE
:
OPERANDS
2021
1415
1 213 4\5 6 7 8
END
1
80
6263
I
OBJE.c:r
The END statement above specifies that the object program (beginning at the address
tagged OBJECT) is to. be executed imITlediately after loading.
Since the location field is blank,
the assembler will reserve an SO-character lo.ading area following the location assigned to the
last character in the object program.
EASYCODER B
The ITlethod of coding this statement depends on which output forITlat has been specified in
the program header stateITlent.
1.
Output in self -loading format: The location field ITlay contain an addres s
(either absolute o.r sYITlbolic) which specifies the initial location in an 80character loading area. If the location field is left blank, the as sembler
automatically as signs an 80 -character loading area following the location
assigned to the last character in the object program.
The op code field contains the letters END, while the operands field
contains the address (either absolute or symbolic) to which the Loader
branches when loading has been completed.
NOTES: 1.
The programmer should ensure that the loading
area does not span two 4K memory banks.
2.
During the loading process, the object program
must not use the loading area. However, the
area may be used following program loading.
3.
When literals are used, the programmer must
specify a loading area that does not coincide
with the memory area occupied by literals.
7-21
#2-139
SECTION VII.
2.
ASSEMBLY CONTROL STATEMENTS
Output in BR T format: The op code field contains the letters END, while
the operands field contains the address (either absolute or symbolic) to
wnich the Loader branches when loading has been completed. When BR T
forITlat is specified; all other fields of the END instruction are ignored
by the asseITlbler.
NOTES:
1.
The loading area is automatically assigned by the Loader.
2.
With Easycoder B, the total of the numbers of Execute,
Literal Origin, and End stateITlents must not exceed 31.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
f~
LOCATION
~ ~
1 213 415 6 7 8
I
1
I
:
OPERATION
CODE
1415
MAL
OPERANDS
2021
1
END
OBJECT
END
OBJECT
I
1
80
6263
I
I
The first example above illustrates the coding which may be used for self-loading format
output; the coding for BRT-format output is shown in the second example.
EASYCODER C AND D
The op code field contains the-letters END.
An address must appear in the operands field;
the Loader will branch to that address (which should be the starting location of the last segment
of the program).
NOTE: The loading area is automatically assigned by the Loader.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
f~
t
~
1 213 415 6 7 8
I
:
LOCATION
OPERATION
CODE
1415
iE;Nt>
OPERANDS
I
2021
80
6263
STARTL
The sample END statement above indicates to the assembler that the end of the source
program has been reached.
This statement is replaced by coding which specifies to the Loader
that the last (or only) segITlent begins at symbolic address STARTL.
7-22
#2-139
INSTRUCTIONS
INTRODUCTION
A Series 200 com.puter operates under the direction of instructions in the stored program..
For descriptive purposes, these instructions are classified into six functional categorie s:
(l)
Arithm.etic; (2) Logic; (3) Control; (4) Interrupt Control; (5) Editing; and (6) Input/Output.
All instructions are described in the following standard form.at:
Title:
The title describes the instruction. It appears in the left-hand
margin of a page, along with the m.nem.onic operation code used
in the Easycoder sym.bolic program.m.ing language.
If an instruction is included in an optional feature, that feature
num.ber accom.panies the title.
Form.at:
This is a tabular representation of all form.ats which m.ay be
used when coding the instruction.
Function:
The function of the instruction is described in term.s of each
form.at in which it can be coded.
Word Marks:
The effect of word m.arks with regard to data fields is specified.
Address
Registers
after
Operation:
The contents of the address registers are indicated for each of
the instruction ' s form.ats.
Notes:
This is additional inform.ation pertaining to the operation.
Exam.ples:
Practical applications of the instruction in its various form.ats
are described and illustrated as sym.bolic program. entries.
Form.ulas for calculating instruction execution tim.es are presented in Appendix C.
Table 8 -1 lists the abbreviations and symbols used in the description of the instructions.
Those sym.bols used only with specific instructions are preceded by the title of the instruction
to which they pertain.
8-1
#2-139
SECTION VIII.
Table 8-1.
INSTRUCTIONS
Symbology Used in Series 200 Instruction Descriptions
A
A addre s s of the instruction
B
B address of the instruction
Ni
Number of characters in the instruction
Na
Number of characters in the A field
Nb
Number of characters in the B field
Nw
Number of characters in the A or B field, whichever is smaller
NXT
Address of next sequential instruction
JI
Address of next instruction if a branch occurs
Ap
The previous setting of the A -address register (AAR)
Bp
The previous setting of the B -address register (BAR)
Number of digits in the dividend
Number of characters translated
Number of information units translated
Previous contents of the change sequence regi ster (CSR)
Number of six-bit character locations occupied by each A-item
information unit (lor 2)
Number of six-bit character locations occupied by each B-item
information unit (lor 2)
Load Control Registers
(A)
Contents of the field specified by the A address.
Table Lookup
L
ta
The location in the table immediately to the left of the argument
(or short field) that terminated the search.
8-2
#2-139
eADD
eSUBTRACT
eBINARY ADD
eBINARY SUBTRACT
e ZERO AND ADD
e ZERO AND SUBTRACT
eMULTIPLY
eDIVIDE
8-3
#2-139
SECTION VIII.
INSTRUCTIONS
ARITHMETIC OPERATIONS
Series 200 add operations (binary addition, decimal addition) treat the A operand as the
augend and the B operand as the addend.
The subtract operations (binary subtraction, decimal
subtraction) treat the A operand as the subtrahend and the B operand as the minuend.
result of each operation is stored in the B field.
The
These elements are summarized in Table 8-2,
where a character enclosed in parentheses indicates the contents of that field.
Table 8-2.
+
Series 200 Add and Subtract Operations
( B )
(A)
-
( B )
(A)
( B )
( B )
BINARY ADDITION
The Binary Add instruction combines the corresponding bits of the augend and addend and
produces a binary sum which is stored in the B field.
on a column-by-column basis.
This process can be most readily analyzed
For any column in the addition, three variables are significant
to the sum: the augend digit, the addend digit, and the carry from the next lower-order column.
For any column, the result is fully expressed by a sum digit (1 or 0) and either a carry or no
carry to the next higher-order column..
Table 8-3 lists all the possible combinations of these
variables.
Table 8-3.
Binary Addition Taple
0
0
0
0
I
1
I
I
0
I
1
0
0
1
1
o
0
I
0
1
0
1
o
1
0
0
1
1
1
1
o
o
0
1
0
0
0
1
1
1
BINARY SUBTRACTION
The Binary Subtract instruction performs, in effect, twos-complement arithmetic. 1 When
this instruction is executed, each six-bit character of the subtrahend is converted to its ones
2
complem ent
and added to the corresponding character in the minuend, adding from right to left.
1
The twos complement of a binary number is formed by subtracting the number from a field of
all one bits and adding one to the low-order digit of the difference.
2 The ones complement of a binary number is formed by subtracting the number from a field of
all one bits.
8-4
#2-139
SECTION VIII.
INSTRUCTIONS
In the first addition (the addition of the low-order characters of the subtrahend and the minuend)
a simulated carry is added to the result.
All subsequent characters are added with or without a
carry, depending upon the result of the previous addition.
If the length of the A
The word mark associated with the B field terminates the operation.
field equals that of the B field, the binary subtraction process continues until the high-order Bfield character has been combined with the high-order A-field character.
If the length of the A
field exceeds that of the B field, the effect is as if there were a word mark in the A-field location corresponding to the high-order B-field location (i. e., the process still terminates at the
B-field word mark).
If the length of the A field is less than that of the B field, zeros are insert-
ed where the A field terminates until the last B-field character is processed.
Each zero is con-
verted to its ones complement as above and then added to the corresponding B-field character.
In the following example, locations 294 and 295 contain the value 73 10 in 12-bit binary form,
while locations 299 and 300 contain the binary equivalent of 87 10 •
Note: Locations 294 and 299 contain word marks; the length of the A field therefore
equals that of the B field in thi s example.
EASYCODER
CODING FORM
PROBLEM
_ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~~
~ ~
LOCATION
I
OPERATION
CODE
1415
1 213 415 6 7 8
ISs
i
OPERANDS
2021
80
6263
1
2qS .. 3~fd
LOCATION ...
CONTENTS ...
(binary)
The six-bit character in location 295 is converted to its ones complement and added to the
six-bit character in location 300 (see illustration below).
carry is generated in the adder (see page 2-10).
Prior to this operation, a simulated
The result of the first addition is the binary
equivalent of 14
plus a carry. This carry remains in the adder and is added to the sum of the
10
contents of locations 294 and 299, resulting in a binary zero plus another carry. This final carry
remains in the adder and the operation terminates.
An overflow condition does not exist since
the carry remaining at the end of the operation is suppressed; consequently the next memory location (location 298) is not disturbed.
therefore 14
10
The result of the ~entire Binary Subtract instruction is
, the true difference between 87 and 73.
Table 8-3 indicates how the bits in each colunm of the ones-complement subtrahend and
the minuend are combined.
8-5
#2-139
SECTION VIII.
INSTRUCTIONS
LOCATION .... ::
CONTENTS ....
~------~~--~------~------~----~------~--~--T
ones complement
Simulated Carry
in Adder
ADDER
001110--------------------~
RESULT
(plus a carry)
First Addition
converted to
ones complement
Previous
Carry
ADDER
RESULT
oooooo------------------~
(plus a carry which
is suppres sed)
Second Addition
The result of the operation (14
73
10
) is stored in the B field as shown below.
14
10
8-6
10
#2-139
SECTION VIII.
INSTRUCTIONS
DECIMAL ADDITION
The Add instruction performs either a true add or a complement add, depending upon the
algebraic signs of the operands.
The sign of an operand is determined by the combination of
zone bits in the units position of that field.
The four possible zone bit configurations and the
signs they represent are shown in Table 8-4.
Table 8 -4.
+
o
o
I
I
o
1
Algebraic Signs in Decimal Addition
I
o
True Add
A true add is performed if the signs of the A and B fields are alike.
The result of the
addition is stored in the B field with the same zone bit configuration that was originally in the B
field (see Figure 8 -1).
zeros.
Zone bits in all B -field locations (except for the units position) are set to
A-field zone bits (except for the units position) are ignored.
(+A) + (+B)
= +R
B OPERAND
A OPERAND
+170
+244
+414 = RESULT
+244
(-A)
+
-R
(-B)
B OPERAND
-444
A OPERAND
-077
-077
-521 = RESULT
Figure 8-1.
True Add Examples
Complement Add
If the operand signs are not alike, the instruction performs a complement add: the A
operand is converted to its tens complement 1 and added to the B operand.
The machine automa-
tically initiates a test to determine whether a carry was generated by the high-order addition.
1 The tens complement of a decimal number is formed by subtracting the number from all nines
and adding one to the low-order digit of the difference.
8-7
#2-139
SECTION VIII.
INSTRUCTIONS
The presence of a carry indicates that the result in the B field is a true answer, and the operation is terminated with the normalized sign of the B field as the sign of the result (see Figure
8-2}.1 B-field zone bits (except for the units position.) art:: set to zeros.
The absence of a carry indicates that the A operand was algebraically larger than the B
operand and that the result is stored in its tens -complement form.
performed automatically to convert the result to its true form.
during this recomplement cycle.
A recomplement cycle is
The sign of the result is changed
Figure 8-2 illustrates complement add operations with and
without recomplementation.
(+A)
+ (-B)
= -R
B OPERAND
A OPERAND
+ 0 0 78
convert to
~ -0090
::IIt::)titI})::/I({ttJ tens com pIe m e nt 1ft?? r::::::\::::\:trttt)t\)i:::t):tI~ 9922
carry indicates true sum
(recomplementing is
unnecessary)
(+A) + (-B)
1 -0012 = RESULT
~
sign of B operand
= +R
A OPERAND
+0178
~
convert to
tens complement
B OPERAND
-0090
!::::/:::)t:::I\:((::nJ:::::@~ 9822
no carry i:tadicates sum is stored
in its tens-complement form;
recomplementing is necessary
~
0 -9912
I
recomplement
and change sign
•
+0088 = TRUE RESULT
Figure 8-2.
Complement Add Examples
DECIMAL SUBTRACTION
The Subtract instruction is analogous to the Add instruction with the exception that before
the operands are combined, the sign of the A operand is changed.
Thus, if the initial sign of the
A operand is equal to that of the B operand, the operands are combined by a complement add.
If,
on the other hand, the initial sign of the A operand is not equal to that of the B operand, the
operands are combined by a true add.
A summary of decimal arithmetic operations is presented in Table 8-5.
1 Normalized signs are expressed by the following zone bit configurations: plus = 01, minus = 10.
8-8
#2-139
SECTION VIII.
Table 8 - 5.
+
INSTRUCTIONS
Decimal Arithmetic Sign Conventions
+
True
+
Complement
Normalized sign of the
operand of greater value
(- = la, + = 01)
ADD
+
Complement
(Bit configuration of B)
True
True
+
+
Complement
SUBTRACT
Complement
+
True
Normalized sign of the
operand of greater value
la, + = 01)
(- =
+
(Bit configuration of B)
INDICATORS
Two indicators are set at the completion of every decimal add and subtract operation: the
overflow indicator and the zero balance indicator.
If a carry is generated beyond the limit of the
B field, the overflow indicator is turned on; if such a carry is not generated, the indicator is
unchanged. 1 The zero balance indicator signifies either a zero or a non-zero sum.
When a
decimal operation produces a result equal to zero (regardless of sign), the zero balance indicator is turned on; when the result of the operation does not equal zero, the indicator is turned off.
These indicators are also set by decimal mUltiply and divide operations.
The overflow
indicator is turned on when a Decimal Divide instruction is performed in which the divisor is
equal to zero.
The zero balance indicator is turned on if the product of a decimal multiply
operation is equal to zero.
The settings of these indicators can be tested by a Branch on Condition Test instruction
(see page 8-35).
This instruction automatically resets the overflow indicator; the zero balance
indicator is, not affected by the branch instruction used to test it but is reset only by the next
decimal arithmetic instruction.
MULTIPLICATION
The Multiply instruction causes the signed decimal integer in the A field (the multiplicand)
1 Only a "true add" operation can turn the overflow indicator on (see Table 8-5).
8-9
#2-139
SECTION VIII.
INSTRUCTIONS
to be multiplied by the signed decimal integer (the multiplier) which is stored in the leftmost locations of the B field.
The signed product is stored, right-justified, in the B field.
The B field must be large enough to insure an adequate number of locations for the development and storage of the product.
Its length is therefore defined as the number of locations in
the multiplier, plus the number of locations in the multiplicand, plus one (see Figure 8-3).
OPERATION:
X
aaaa
bbb
LOCATION ....
0
CONTENTS....
a
a
a
b
MULTIPLICAND
(4 locations)
Figure 8-3.
b
MULTIPLIER
(3 locations)
A and B Fields in Multiply Operation
Word marks are required in the leftmost locations of the multiplicand and the multiplier.
All other locations in the B field must not contain word marks.
As shown in Figure 8-3, the
rightmost location of the multiplier is defined as B - Na - 1, where B is the B address and Na
is the number of locations in the A field.
The zone bits in the units positions of the multiplier and the multiplicand indicate the signs
of the operands.
The signs of these factors indicate the sign of the product according to the
algebraic sign conventions shown in Table 8-6.
normalized form
(minus
= 10,
plus
The sign of the product is expressed in its
= 01).
Table 8 -6.
Multiply Sign Conventions
+
+
+
+
8-10
+
+
#2-139
SECTION VIII.
INSTRUCTIONS
ConsideT the following Decimal Multiply instruction.
EASYCODER
CODING FORM
\
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I~I~
I~ ~
1 213 415 6 7 8
I
OPERATION
CODE
LOCATION
:
OPERANDS
80
6263
2021
1415
5(l!(6. 7.~1JJ
1M
Location 500 is the rightmost location of a four-character fieldo
most location of an eight"character field.
Location 700 is the right-
Location 695 (i. e., 700 - 4 - 1) is the rightmost loca-
tion of the multiplier.
B ADDRESS
A ADDRESS
•
LOCATION
~
CONTENTS
...
•
The data in the A field is multiplied by the data in the field whose rightmost location is
695, and the product is stored, right-justified, in the B field.
All B-field zone bits are cleared
to zeros (except in the units position, which contains the sign of the product).
At the end of the
operation, the multiplier is no longer present in the leftmost positions of the B field, since all
B-field locations to the left of the most significant digit of the product are set to zeros.
Thus,
the multiplier should be preserved in another storage field if it is to be used more than once.
The result of the multiply operation is shown below.
A FIELD IS
NOT DISTURBED
PRODUCT IS STORED IN B FIELD, RIGHTJUSTIFIED. ALL INSIGNIFICANT HIGHORDER CHARACTERS ARE SET TO ZEROS
LOCA TION ----.. .
CONTENTS--.
-----------------~----------------PRODUCT
DIVISION
The Divide instruction causes the signed decimal integer in the A field (the divisor) to be
divided into the signed decimal integer whose leftmost location is the B address of the instruction (the dividend).
The quotient is developed and stored in the leftmost locations of the B field,
8-11
#2-139
SECTION VIII.
INSTRUCTIONS
and the remainder is stored in the rightmost locations of the B field. 1 To insure an adequate
number of storage locations for the development of the quotient, the length of the B field is
d6t6:rn1ined by adding 1 to the sum of the number of character locations in the divisor and
dividend (see Figure 8-4).
OPERATION:
xxx)yyyy
BEFORE EXECUTION
r
LOCATION
B FIELD (3+4+1=8 loc a tionS)1'
B ADDRESS
CONTENTS
DIVISOR
(3 locations)
DIVIDEND
(4 locations)
AFTER EXECUTION
B-Na +N dd -2
LOCATION
CONTENTS
x
Figure 8-4.
x
Factor Locations in Divide Operation
The leftmost location of the dividend is defined by the B address of the Divide instruction.
The rightmost location (i. e., the units position) is the first character location to the right of
the B address to have one of its zone bits not equal to zero.
As shown in Figure 8-4, all B-
field locations to the left of the dividend must contain zeros prior to the divide operation.
A word mark is required in the leftmost location of the divisor.
The dividend mayor may
not contain a word mark.
INote that the B "field" in a divide operation does not define the B operand but is a group of
storage locations within which the B operand (the dividend) is contained.
8-12
#2-139
SECTION VIII.
INSTRUCTIONS
The signs of the operands are indicated by the zone bits in the units positions of the divisor
and dividend.
8-7).
Algebraic sign control is used to determine the sign of the quotient (see Table
The sign of the quotient is expressed in its normalized form (minus
= 10,
plus
= 01).
The
sign of the remainder is always the same as that of the dividend (in value if not in bit configuration); its form is normalized if the sign of the dividend is normalized.
Table 8 -7.
Divide Sign Conventions
+
+
+
+
+
+
+
+
Since the pre sence of a signed digit in the dividend specifies its rightmost location, the
units position of the dividend must contain a normalized sign and the zone bits of all other
dividend characters must be zero.
When division is completed, the signed decimal quotient is stored in the leftmost locations
of the B field; the units position of the quotient is in location B - Na + Ndd - 2, where Na is the
number of locations in the A field and Ndd is the number of locations in the dividend.
The signed
decimal remainder appears in locations B+Ndd-1, B+Ndd -2, etc. through location B-Na+Ndd.
The character location separating the quotient and the remainder is cleared to zero (see Figure 8-4).
In the following example, the divisor is a two-character field whose rightmost location is
location 450 and the dividend is a four-character integer whose leftmost location is location 950.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
1 213 415 6 7
I
I
I
i
LOCATION
8
OPERATION
CODE
1415
~
OPERANDS
2021
6263
80
450,Q,50
I
I
The contents (+23) of the A field are divided into the contents of the field (+7347) whose
leftmost location is 950.
The rightmost boundary of the dividend is determined by the first
character location (location 953) to the right of location B whose zone bits are non-zero.
This
units position of the dividend therefore contains the sign of the dividend.
8-13
#2-139
SECTION VIII.
INSTRUCTIONS
B FIELD = 1+2+4 = 7
~
CHARACTER LOCATIONS
I
I
B ADDRESS
---------------
~
DIVISOR =
2 CHARACTER
LOCATIONS
DIVIDEND = 4
CHARACTER LOCATIONS
The quotient (+319) is stored in the leftmost character locations of the B field.
The units
position of the quotient (location 950) is equal to B-Na +Ndd -2, or 950-2+4-2. The remainder
is stored in the rightmost locations of the B field; its leftmost location (location 952) is equal to
B-Na+Ndd' or 950-2+4; its rightmost location (location 953) is equal to B+Ndd-l, or 950+4-1.
The result of the operation is shown below.
FINAL SETTING OF AAR
FINAL SETTING OF BAR
~
QUOTIENT
- -
OP CODE
FORMAT
o.
b.
c.
B ADDRESS
A ADDRESS
_
_
FUNCTION
Format a:
The signed decimal data in the A field is added algebraically to the signed decimal
data in the B field. The result is stored in the B field.
Format b:
The signed decimal data in the A field is added to itself.
A field.
Format c:
The signed decimal data specified by the contents of the A-address register (AAR) is
added algebraically to the signed decimal data specified by the contents of the B -address register (BAR). The result is stored in the B field.
8-14
The result is stored in the
#2-139
SEC TION VIII.
INS TR UC TIONS
WORD MARKS
Format a:
The B operand must have a defining word mark. It is this word mark that terminates
the operation. The A operand m.ust have a word mark only if it is shorter than the B
operand. In this case, transmission of data from the A operand stops after the Aoperand word mark is sensed. If the A field is longer than the B field, the highorder characters of the A field that exceed the field length defined by the B-operand
word mark are not processed.
Format b:
The A operand must have a defining word mark.
Format c:
The B operand must have a defining word mark.
mark only if it is shorter than the B operand •.
The A operand must have a word
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-'Nw
B-Nb
Format b:
NXT
A-Na
A-Na
Format c:
NXT
Ap-Nw
Bp-Nb
NOTES
1.
The algebraic sign control for the add operation is shown below.
Sign of B field
Normalized sign of A or B
field, whichever is greater
(-=10,+=01)
2.
All zone bits in the result field are set to zeros except for the units position.
(i. e., the sign of the result).
3.
This instruction treats both operands as signed decimal data. It will produce ambiguous results if used to manipulate non-decimal data. Particularly,
if the four numeric bits of any character have a binary numeric value of 12
or more (octal 14, 15, 16, and 17), the character is treated as if it were
a zero, though its zone bits are retained. (In Type 201 or 201-1 proces sors,
the zone and numeric bits of octal 14, 15, 16, and 17 are handled as zeros.)
The two remaining cases (octal 12 and 13) are unspecified.
4.
The overflow and zero balance indicators are set by an add operation.
5.
When the central processor is in the l1Sl1 mode o{processing, the zone bits
are not changed in any character other than the units position of the B field.
EXAMPLE
Add Bond Deductions to Total Deductions.
Description
Tag
Bond Deductions
BDED
Total Deductions
TDED
8-15
#2-139
SECTION VIII.
INSTRUCTIONS
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
iI
LI
I
CARD
NUMBER
IJI~I
I~i~i
LOCATION
I
IA
:" I
5
I OP~"06;~O ~ I
14[15
ZJ34J5L6J7!8
OPERANDS
20lz1
1
1
80
6263
laDE D. TDE' 0
SUBTRACT
FORMAT
-- -
OP CODE
o.
b.
c.
FUNCTION
A ADDRESS
B ADDRESS
ForITlat a:
The signed deciITlal data in the A field is subtracted algebraically froITl the signed
deciITlal data in the B field. The result is stored in the B field.
ForITlat b:
The signed deciITlal data in the A field is subtracted froITl itself. The result is
stored in the A field. If the A-field sign is ITlinus, the result is a ITlinus zero. If
the A-field sign is plus, the result is a plus zero (with norITlalized Sign).
ForITlat c:
The signed deciITlal data specified by the contents of the A-address register (AAR)
is subtracted algebraically froITl the signed deciITlal data specified by the contents
of the B-address register (BAR). The result is stored in the B field.
WORD MARKS
ForITlat a:
The B operand ITlust have a defining word ITlark. The A operand ITlust have a word
ITlark only if it is shorter than the B operand. In this case, transITlission of data
froITl the A operand stops after the A-operand word ITlark is sensed. If the A field
is longer than the B field, the high-order characters of the A field that exceed" the
field length defined by the B -operand word ITlark are not proces sed.
ForITlat b:
The A operand ITlust have a defining word ITlark.
ForITlat c:
The B operand ITlust have a defining word ITlark.
ITlark only if it is shorter than the B operand.
The A operand ITlust have a word
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
ForITlat a:
NXT
A-Nw
B-Nb
ForITlat b:
NXT
A-Na
A-Na
ForITlat c:
NXT
Ap-Nw
B -Nb
P
8-16
#2-139
SECTION VIII.
INSTRUCTIONS
NOTES
1.
Algebraic sign control for the subtract operation is smnrnarized below.
+
+
+
Comp
Comp
Normalized sign of
A or B field, whichever is greater
(- = 10, + = 01)
True
+
True
Sign of B fleld
2.
All zone bits in the result field are set to zeros except for the units position
(i. e., the sign of the result).
3.
This instruction treats both operands as' signed decimal data. It will produce ambiguous results if used to manipulate non-decimal data. Particularly' if the four numeric bits of any character have a binary numeric
value of 12 or more (octal 14, 15, 16, and 17), the character is treated as
if it were a zero, though its zone bits are retained. (In Type 201 or 201-1
processors, the zone and numeric bits of octal 14, 15, 16, and 17 are
handled as zeros.) The two remaining cases (octal 12 and 13) are unspecified.
4.
The overflow and zero balance indicators are set by a subtract operation.
5.
When the central processor is in the "S" mode of processing, the zone bits are
not changed in any character other than the units position of the B field.
EXAMPLE
Subtract the contents of the five-character fields starting at location 940, 945, 950,
and 955 from the contents of the eight-character fields starting at locations 648,
656, 664, and 672.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
r~
CARD
NUMBER
f
~
1 213 415 6 7 8
I
1
i
I
I BA
:
LOCATION
OPERATION
CODE
1415
S
S
S
S
I
I
I
OPERANDS
2021
62 63
1
90
955 .6.72
I
BINARY ADD
FORMAT
-- -
OP CODE
o.
b.
c.
A ADDRESS
B ADDRESS
8-17
#2-139
SECTION VIII.
INSTRUCTIONS
FUNCTION
For'mat a:
The data in the A field is added in binary fashion, character by character, to the
data in the B field. The result is stored in the B field.
Format b:
The data in the A field is added, character bycharacter, to itself.
stored in the A field.
Format c:
The data specified by the contents of the A ... address register (AAR) is added, character by character, to the data specified by the contents of the B -address register
(BAR). The result is stored in the B field.
The result is
WORD MARKS
Format a:
The B operand must have a defining word mark. It is this word mark that terminates the operation. The A operand must have a word mark only if it is shorter
than the B operand. in this case the transmission of data from the A field stops
after the A-operand word mark is sensed. If the Afield is longer than the B field,
the high-order characters of the A field that ex!=eed the field length defined by the
13 -operand word mark are not processed.
Format b:
The A operand must have a defining word mark.
Format c:
The B operand must have a defining word mark.
mark only if it is shorter than the B operand.
The A operand must have a word
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-Nw
B-Nb
Format b:
NXT
A-Na '
A-Na
Format c:
NXT
Ap-Nw
B -Nb
P
NOTES
1.
The overflow and zero balance indicators are not set by a binary add
operation.
2.
Format b of the BA instruction has the effect of doubling the value stored
in the A field; i. e., it shifts the contents of the A field one bit position
to the left.
EXAMPLE
Modify the B address of the instruction tagged B 7 by the value stored in the location
tagged TEN (assuming the use of the two-character addressing mode).
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ OATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
ll~
~~
213 415 6 7 8
I
:
LOCATION
OPERATION
CODE
1415
B,A
OPERANDS
2021
I
I
I
6263
80
TEN.~,8 7+.4.
8-18
#2-139
SEC TION VIII.
BS
INSTR UC TIONS
BINARY SUBTRACT
FORMAT
-- -
OP CODE
a.
A ADDRESS
B
ADDRESS
~
b.
c.
FUNCTION
Format a:
Each six-bit character in the A field is converted to its ones complement and added,
in binary fashion, character by character, to the data in the B field (see page 8-4).
A simulated carry is added with the characters in the units position. The result is
stored in the B field.
Format b:
Each six-bit character in the A field is converted to its ones complement and added,
character by character, to itself. A simulated carry is added with the characters
in the units position. In effect, this format of the binary subtract instruction replaces the contents of the A field with zeros.
Format c:
Each six-bit character specified by the contents of the A-address register (AAR)
is converted to its ones complement and added, character by character, to the data
specified by the contents of the B-address register {BAR}. A simulated carry is
added with the characters in the units ,position. The result is stored in the B field.
WORD MARKS
Format a:
The word mark associated with the B operand terminates the operation. The A
operand must have a word mark only ii£ it is shorter than the B operand. In this
case, transmission of data from the A field stops after the A-operand word mark
is sensed. If the A operand is longer than the B operand, the characters of the A
operand that exceed the field length defined by the B -operand word mark are not
processed.
Format b:
The A operand must have a defining word mark.
Formatc:
The B operand must have a defining word mark.
mark only if it is shorter than the B operand.
The A operand must have a word
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-Nw
B-Nb
Format b:
NXT
A-N
A-N
Format c:
NXT
A -N
P w
a
a
Bp-Nb
8-19
#=2-139
SECTION VIII.
INSTRUCTIONS
NOTES
1.
The overflow and zero balance indicators are not set by a binary subtract
operation.
2.
Formats a. and c. can produce negative results. A negative result is stored
in the B field in its twos-complement form. In this case, the absolute numerical value of the result can be obtained by recomplementing the result
stored in the B field. A negative result is detected only if the programmer
provides appropriate coding to ascertain whether or not operands .will produce such a result.
EXAMPLE
Zero the field starting at location TOTAL.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
fl~
~ ~
LOCATION
1 213 415 6 7 8
I
1
OPERATION
CODE
1415
~s
OPERANDS
6263
2021
80
TOTAL.
NOTE: Zone bits as well as numeric bits are cleared to zero by this
operation.
ZA
I ZERO AND ADD I
IFEATURES 010 & 011 1
FORMAT
-- -
OP CODE
o.
b.
c.
FUNCTION
A ADDRESS
B ADDRESS
Format a:
The data in the A field is transferred, character by character, right to left, to the
B field. Zone bits in the B field are set to zero in all positions except the units
position. The sign of the result field is based on the sign of the A field (see note 1).
If the high-order character of the A field is transferred before the operation
term~nates, the remaining B field characters are cleared to zeros.
Format b:
The data in the A field is converted to an all-numeric format; i. e., the zone bits
of all positions in the field except the units position are set to zero. The result
remains in the A field. The sign of the A field is not changed by the operation (see
note 1).
8-20
#2-139
SECTION VIII.
Format c:
INSTRUCTIONS
The data specified by the contents of the A-address register (AAR) is transferred
to the field specified by the contents of the B-address register (BAR). Zone bits
in the B field are set to zero in all positions except the units position. The sign
of the result field is based on the sign of the A 'field (see note 1). If the highorder character of the A field is transferred before the operation terminates, the
remaining B-field characters are cleared to zeros.
WORD MARKS
Format a:
The B operand must have a defining word mark. The A operand must have a word
mark only if it is shorter than the B operand. In this case, transfer of data from
the A operand stops after the A-operand word mark is sensed. If the A field is
longer than the B field, the high-order characters of the A field that exceed the
field length defined by the B-operand word mark are not processed.
Format b:
The A operand must have a defining word mark.
Format c:
The B operand must have a defining word mark.
mark only if it is shorter than the B operand.
The A operand must have a word
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-N
w
B-Nb
Format b:
NXT
A-Na
A-N
Format c:
NXT
A -N
P w
B p-Nb
a
NOTES
1.
A plus sign in the units position of the re suit field is always expre s sed in
its normalized form (01).
2.
B -field punctuation is not changed by this operation.
3.
This instruction does not set the overflow and zero balance indicators.
4.
When the central processor is in the "S" mode ofprocessing and the four numeric
bits of any character have a value of 148 or more (128 in the 4200), the character
is treated as if it were a zero. The zero balance indicator is set or reset accordingly.
EXAMPLE
Transfer the contents of the field tagged ORATE to the field tagged NRATE, setting
a1l zone bits in NRA TE (except in the units position) to zeros.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAM.MER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
l~
1 213 415 6 7 8
I
I
:
I
I
I
I
I
1
i
LOCATION
OPERATION
CODE
1415
Z,A
OPERANDS
2021
.L
I
6263
80
ORATE,~NRATE:
8-21
#2-139
SECTION VIII.
zs IZERO AND SUBTRACT I
INSTRUCTIONS
FEATURES 010 & 011
FORMAT
-- -
OP CODE
o.
b.
c.
A ADDRESS
B ADDRESS
FUNCTION
Format a:
The data in the A field is transferred to the B field with the opposite sign. Zone
bits in the B field are set to zeros in all positions except the units position. If the
high-order character of the A field is transferred before the operation terminates,
the remaining B-field characters are cleared to zeros.
Format b:
The data in the A field is converted to an all-numeric format; i. e., the zone bits
of all positions in the field except the units position are set to zero. The result remains in the A field with its sign reversed.
Format c:
The data specified by the contents of the A-address register (AAR) is transferred
with the opposite sign to the field specified by the contents of the B -address register
(BAR). Zone bits in the B field are set to zero in all positions except the units
position. If the high-order character of the A field is transferred before the operation terminates, the remaining B -field characters are cleared to zeros.
WORD MARKS
Format a:
The B operand must have a defining word mark. The A operand must have a word
mark only if it is shorter than the B operand. In this case, transfer of data from
the A operand stops after the A-operand word mark is sensed. If the A field is
longer than the B field, the high-order characters of the A field that exceed the
field length defined by the B-operand word mark are not processed.
Format b:
The A operand must have a defining word mark.
Format c:
The B ope rand must have a defining word mark.
mark only if it is shorter than the B operand.
The A operand must have a word
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-N
w
B-Nb
Format b:
NXT
A-Na
A-Na
Format c:
NXT
Ap-Nw
Bp-Nb
8-22
#2-139
SECTION VIII.
INSTRUCTIONS
NOTES
1.
A plus sign in the units position of the result field is always expressed in its
normalized form (01).
2.
B -field punctuation is not changed by this operation.
3.
This instruction does not set the overflow and zero balance indicators.
4.
When the central processor is in the "S" mode and the four numeric bits of any
character have a value of 148 or more (128 in the 4200), the character is
treated as if it were a zero. The zero balance indicator is set or reset accordingly.
EXAMPLE
Change the sign of the data in the field tagged PROFIT.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~I~
~ ~
LOCATION
1 2 3 4 5 6 7 8
OPERATION
CODE
1415
OPERANDS
2021
ZS
1
I
80
6263
PR.OF IT
-..1
M
I
MULTIPLY
I
FORMAT
-- -
OP
o.
b.
c.
FUNCTION
CODE
A ADDRESS
B ADDRESS
Format a:
The signed decimal integer in the A field is multiplied by the signed decimal integer
in the leftmost locations of the B field. The product is stored, right - justified, in
the B field.
Format b:
The signed decimal integer in the A field is multiplied by the signed decimal integer
in the leftmost locations of the field specified by the contents of the B-address register (BAR). The product is stored, right-justified, in the B field.
Format c:
The signed decimal integer in the field specified by the contents of the A-address
register (AAR) is multiplied by the signed decimal integer in the leftmost locations
of the field specified by the contents of BAR. The produ.ct is stored, right-justified,
in the B field.
WORD MARKS
Formats a, b, and c:
Word marks are required in the high-order locations of both the A and B fields.
All other B-field locations must not contain word marks.
8-23
# 2-139
SECTION VIII.
INSTRUCTIONS
\
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
'll.T"V".,.,
.L
A-Na
B-Nb
Format b:
NXT
A-Na
Bp-Nb
Format c:
NXT
Ap-N a
Bp-Nb
~'I..n..
NOTES
1.
The A address of a Decimal Multiply instruction specifies the units position
of the multiplicand. The B address specifies a location which is N a +l locations to the right of the multiplier, since the B field :must contain the
multiplier plus enough additional locations (to the right of the multiplier) to
provide for the development of the product. Thus, the total nu:mber of
character locations in the B field :must be one greater than the sum of the
number of characters in the multiplicand and the multiplier. For example,
in a multiplication operation involving a 3 -character m.ultiplier and a 5character multiplicand, 9 positions (5+3+1) m.ust be provided in the B field.
I
2.
Algebraic sign control for the multiply operation is shown below.
of the product is expressed in its normalized form (-=10, +=01).
+
+
+
+
The sign
+
+
3.
The product is stored (right-justified) in the entire B field, with the unused
high-order positions of the B field cleared to zeros. As a result of the
operation, the multiplier (initially stored in the B field) is destroyed.
Therefore, if the multiplier is to be used more than once, it should be
preserved in another storage field.
4.
The zero balance indicator is turned ON if the product of the multiply operation is equal to zero; otherwise, the indicator is turned OFF by the operation.
f
This instruction treats both operands as signed decimal data. It will produce ambiguous results if used to manipulate-non-decimal data. Particularly,
if the four numeric bits of a character have a binary numeric value of 12 or
more (octal 14, IS, 16, or 17), the character is treated as if it were a
zero. The two remaining cases (octal 12 and 13) are unspecified.
5.
6.
This instruction is standard on all processors but the Type 201, on which
it is not available.
7.
If the A & B operands overlap, then the results are unspecified.
EXAMPLE
Multiply the five-character field tagged CAND by the three-character field whose
rightmost character location is six (5+1) less than the location tagged PROD.
Store the result, right-justified, in PROD.
8-24
#2-139
SECTION VIII.
INSTRUCTIONS
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
'~l~
~ ~
OPERATION
CODE
LOCATION
1 2/3 415 6 7 8
I
1415
:
~
D
OPERANDS
2021
80
6263
CAND. PROD
i
DIVIDE
FORMAT
-- -
OP CODE
o.
b.
c.
FUNCTION
A ADDRESS
B ADDRESS
Form.at a: The signed decim.al integer who se leftm.ost location is B is divided by the signed decim.al integer in the A field. The quotient is stored in the leftm.ost locations of the B
field; the rem.ainder is stored in the rightm.ost locations of the B field (see page 8-12) •.
Form.at b: The signed decim.al integer whose leftm.ost location is specified by the contents of the
B -address register (BAR) is divided by the signed decim.al integer in the A field.
The quotient is stored in the leftm.ost locations of the B field; the rem.ainder is stored
in the rightm.ost locations of the B field (see page 8-1Z).
Form.at c: The signed decim.al integer whose leftm.ost location is specified by the contents of the
B -address register (BAR) is divided by the signed decim.al integer in the field specified by the contents of the A-address register (AAR). The quotient is stored in the
leftm.ost locations of the B field; the rem.ainder is stored in the rightm.ost locations
of the B field (see page 8-IZ).
WORD MARKS
Form.ats a, b, and c:
The A operand (the divisor) m.ust contain a word m.ark.
a word m.ark.
The B field m.ay contain
ADDRESS REGISTERS AFTER OPERATION (WHEN DIVISOR IS NOT EQUAL TO ZERO)
When the divisor is equal to zero, the contents of the address registers are unspecified (see note I).
8-Z5
#Z-139
SECTION VIII.
INSTRUCTIONS
NOTES
1.
If the divisor is equal to plus or minus zero, the overflow indicator is turned
ON, division is not performed, and no memory locations are changed.
2.
The length of the B field is determined by adding 1 to the sum of the number
of character locations in the divisor and the dividend (B -field length = 1 +
length of divisor + length of dividend).
3.
. The A field (divisor) can be signed or unsigned; if it is unsigned, the divisor
is assumed to be positive.
4.
The dividend must contain a normalized sign (- = 10, + = 01) in the units
position. The zone bits of all other characters in the dividend must be zeros.
The proper signing of the dividend is therefore insured if the dividend is
moved into the B field by a Zero and Add instruction (see page 8-20).
5.
All high-order locations of the B field which are not occupied by the dividend
must contain zeros when division begins. These zeros can be automatically
inserted if the Zero and Add instruction is used to move the dividend into
the B field as mentioned above.
6.
The sig;n of the quotient follows algebraic sign rules as shown below·.
sign of the remainder is the original sign of the dividend.
\
+
+
+
The
+
+
+
+
+
7.
This instruction treats both operands as signed decimal data. It will produce ambiguous results if used to manipulate non-decimal data. Particularly,
if the four numeric bits of a character have a binary numeric value of 12 .
or more (octal 14, 15, 16, or 17), the character is treated as if it were a
zero. The two remaining cases (octal 12 and 13) are unspecified.
8.
This instruction is standard on all processors but the Type 201, on which
it is not available.
9.
If the A & B operands overlap, then the results are unspecified.
EXAMPLE
Divide the four-character integer whose leftmost location is location 1000 by the
three-character field whose rightmost location is location 500. Store the quotient
in the leftmost locations of the field at 1000, and store the remainder in the rightmost locations of this field.
Na (number of characters in divisor)
=3
Ndd (number of characters in dividend) = 4
B (B address}
= 1000
= 1000-3+4-2 = location 999
= 1000+4-1 = location 1003
Units position of quotient (B-Na +Ndd -2)
Units position of remainder (B+N dd -l)
EASYCODER
CODING FORM
, PROBLEM
CARD
NUMBER
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
~~
~ ~
1213415 6 7 8
I
1
LOCATION
OPERATION
CODE
1415
10
OPERANDS
I
2021
6263
80
5¢¢ .. 1,0J6.oJ.
8-26
#2-139
-EXTRACT
-HALF ADD
- SUBSTITUTE
-COMPARE
-BRANCH
_ BRANCH ON CONDITION TEST
-BRANCH ON CHARACTER CONDITION
- BRANCH IF CHARACTER EQUAL
- BRANCH ON BIT EQUAL
8-27
#2-139
SECTION VIII.
INSTRUCTIONS
EXTRACT
(Logical Product)
FORMAT
-- -
OP CODE
o.
b.
c.
FUNCTION
ForIllat a:
B ADDRESS
A ADDRESS
The data in the A field is cOIllbined bit-by-bit with the data in the B field. according
to the following rules. The result is stored in the B field.
1
1
o
o
o
1
o
o
o
o
ForIllat b:
The data in the A field is cOIllbined bit-by-bit with the data specified by the contents of the B-address register (BAR). according to the rules stated above. The
re suit is stored in the B field.
Format c:
The data specified by the contents of the A-address register (AAR) is combined
bit-by-bit with the data specified by the contents of BAR, according to the rules
stated above. The re suit is stored in the B field.
WORD MARKS
ForIllats a, b, and c:
A word Illark is required for the shorter of the two operands.
terIllinates when this word Illark is sensed.
The operation
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
ForIllat a:
NXT
A-Nw
B-Nw
ForIllat b:
NXT
A-Nw
B -N
P w
ForIllat c:
NXT
A -N
P w
B -N
P w
8-28
#2-139
SECTION VIII.
INSTRUCTIONS
EXAMPLE
Remove all zone bits in the field tagged BASE by combining the contents of BASE
with the contents of the field tagged CON. Each character in CON must have the
following format:
Bit position
Contehts
BA8421
001111
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CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
~I~
LOCATION
~ ~
213 415 6 7 8
I
r
OPERATION
CODE
1415
EXT
:
OPERANDS
2021
~
6263
I
80
co N, BASE
1
HA
HALF ADD
(Exclusive Or)
FORMAT
-- -
OP CODE
o.
b,
c,
FUNCTION
Format a:
B ADDRESS
A ADDRESS
The data in the A field is combined bit-by-bit with the data in the B field, according to the following rules. The re sult is stored in the B field.
1
a
a
a
a
1
a
a
Format b:
The data in the A field is cOITlbined bit-by-bit with the data specified by the contents of the B-address registe'r (BAR), according to the rules stated above. The
re sult is stored in the B field.
Format c:
The data specified by the contents of the A-addres s register (AAR) is combined
bit-by-bit with the data specified by the contents of BAR, according to the rules
stated above. The result is stored in the B field.
#2-139
SECTION VIII.
INSTRUCTIONS
WORD MARKS
ForInats a, b, and c:
The
word :marl~ is required for the
terminates when this word mark is sensed.
J,A".
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
ForInat a:
NXT
A-Nw
B-Nw
Format b:
NXT
A-N
w
B -N
p w
ForInat c:
NXT
A -N
P w
B -N
P w
EXAMPLE
Clear all the numeric bits in the field tagged SEVEN to zero s by combining the contents of SEVEN with the contents of the field tagged TOO. Do not change the zone
bits in SEVEN. (The contents of each character in TOO are OOxxxx, where x
equals the corresponding bit in SEVEN. )
EASYCODER
COOING FORM
PRoGRAMMER
PROBLEM
CARD
NUMBER
~I~
~~
LOCATION
1 213 415 6 7 8
I
SST
OPERATION
CODE
I
1415
2021
HA
I
SUBSTITUTE
DATE
PAGE
OF
OPERANDS
1
1
6263
80
TOO .S,EVEN
I
FORMAT
-- - -
OP CODE
o.
b.
c.
d.
A ADDRESS
B ADDRESS
-
VARIANT
_
FUNCTION
Format a:
The single character specified by the A address is compared bit-by-bit with the
variant character and is moved to the location specified by the B address, according to the following rule s:
8-30
#2-139
SECTION VIII.
INSTRUCTIONS
1.
The A-character bit is transferred to the B address if the corresponding
variant bit:;: 1.
2.
The B -character bit is preserved if the corre sponding variant bit = O.
Format b:
The sIngle character specified by the A address is compared bit-by-bit with the
variant character specified in a previous instruction and is moved to the location specified by the B address, according to the rules stated above.
Format c:
The single character specified by the A address is compared bit-by-bit with the
variant character specified in a previous instruction and is moved to the location
specified by the contents of the B-address register (BAR), according to the rules
stated above ..
Format d:
The single character specified by the contents of the A-address register (AAR)
is compared bit-by-bit with the variant character specified in a previous instruction and is moved to the location specified by the contents of BAR, according to
the rule s stated above.
WORD MARKS
Formats a, b, c, and d:
Word marks are not required in either field.
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-I
B-1
Format b:
NXT
A-I
B-1
Format c:
NXT
A-I
B -1
P
Format d:
NXT
A -1
P
B -1
P
NOTE
This instruction can be coded only in formats a. and d. when programming for
the Type 201 or 201-1 processor.
EXAMPLES
1.
Move the zone bits from the location tagged STET to the location tagged
STET +20. A variant character of octal 60 provides the required variant
bit configuration (i. e., 110 000).
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CARD
NUMBER
I~
1 213 415 6 7 8
I
I
LOCATION
OPERATION
CODE
1415
~ST
PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
OPERANDS
,
2021
6263
80
STET,STET+2¢,6¢
8-31
#2-139
SECTION VIII.
2.
INSTRUCTIONS
Move the numeric portion of the character at location 256 to location 656.
A variant of octal I 7 provides the required variant bit configuration
(i.e., 001 Ill).
EASYCODER
COOING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
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NUMBER
~I~
~ ~
LOCATION
1213415 6 7 8
I
c
OPERATION
CODE
1415
i
I~ST
I
COMPARE
OPERANDS
2021
80
6263
256.656.17
I
FORMAT
-- -
OP CODE
o.
b.
C.
FUNCTION
A ADDRESS
B ADDRESS
Format a:
The data in the B field is compared bit-by-bit with the data in the A field. The comparison turns on indicators that can be interrogated by subsequent Branch instructions. The indicators are reset by the next Compare instruction.
Format b:
The data specified by the contents of the B-address register (BAR) is compared
bit-by-bit with the data in the A field. This operation turns on indicators which
can be tested by subsequent Branch instructions. The indicators are reset by the
next Compare instruction.
Format c:
The data specified by the contents of BAR is compared bit-by-bit with the data in
the field specified by th.e contents of the A-address register (AAR). The comparison turns on indicators that can be interrogated by subsequent Branch instructions. The indicators are reset by the next Compare instruction.
WORD MARKS
Formats a, b, and c:
The word mark associated with the B operand terminates the operation. The A
operand must have a word mark only if it is shorter than the B operand. In this
case, transmission of data from the A field stops after the A-operand word mark
is sensed, and the remaining characters of the B operand are compared with zeros.
If the A operand is longer than the B operand, the characters of the A operand that
exceed the field length defined by the B-operand word mark are not processed.
8-32
#2-139
SECTION VIII.
INSTRUCTIONS
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-Nw
B-Nb
Format b:
NXT
A-N
w
B -N
p
b
Format c:
NXT
A p -Nw
Bp-Nb
NOTES
1.
All characters that can appear in storage can be compared.
order of characters is listed in Appendix B.
The ascending
2.
Both fields must have exactly the same bit configurations to be equal.
example, plus zero is not equal to minus zero.
3.
Comparison results and associated branch conditions are listed below.
BA
High Compare
BfoA
Unequal Compare
B~A
High 'or Equal Compare
For
EXAMPLE
Compare item number with 4000. If item number equals 4000, continue the program
in sequence; otherwise, branch to location NITEM.
Description
Tag
Item Number
ITEM
4000
CON4
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CARD
NUMBER
I
~ ~
~ ~
213 415 6 7 8
I
LOCATION
OPERATION
CODE
1415
:
C
1
BCT
I
PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
OPERANDS
2021
CON4. ITEM
NI TEM)45
I
I
I
~L
I
6263
eo
I
8-33
#2-139
SECTION VIII.
I
B
BRANCH
FORlv1..AT
I
- -
B ADDRESS
A ADDRESS
OP CODE
FUNCTION
INSTRUCTIONS
VARIANT
The Branch instruction causes the program to branc.h to the location specified
by the A address and to store the contents of the sequence register (SR) in the Baddress register (BAR). It is used to interrupt normal program sequence and
to continue the program at any desired point, without testing for specific conditions. Thus, this instruction is frequently referred to as an "unconditional
branch."
WORD MARKS
Word marks are not affected by this instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
A
NXT
JI (A)
NOTES
1.
The A address is placed in AAR during the extraction of this instruction,
preserving any active high-order bits in AAR. When the instruction is
executed, the entire contents of AAR specify the address to which the
prograITl branches. Also, the entire contents of SR are stored in BAR
during the execution phas e.
2.
The contents of the variant register are unspecified following the execution
of this instruction. Therefore an instruction requiring a variant character
ITlust not be chained following a Branch instruction.
EXAMPLE
Select the next instruction from the location tagged SUB6.
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CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~~
~
t
1 213 415 6 7 8
I
I
I
I
:
LOCATION
OPERATION
CODE
1415
15
OPERANDS
2021
I
6263
I
eo
SU86
I
I
I
1
I !
I
:
1
I
1
1
8-34
#2-139
SEC TION VIII.
INSTR UC TIONS
I Bel I BRANCH ON CONDITION TEST I
FORMAT
-- -
A ADDRESS
OP CODE
o.
b.
FUNCTION
B ADDRESS
-
VARIANT
Format a:
The variant .character specifies a condition indicator or a SENSE switch to be
tested. If the condition being tested is present, the program branches to the location specified by the A address and the contents of the sequence register (SR)
are stored in the B -address register (BAR). If the condition specified by the
variant character is not present, the program continues in sequence. Tables 8-8
and 8-9 list the valid variant characters and the conditions they test~
Format b:
If the condition specified by the previous variant character is present, the program branches to the location specified by the contents of the A-address register
(AAR) and the contents of SR are stored in BAR. If the condition being tested is
not present, the program continues in sequence. Tables 8-8 and 8-9 list the valid
variant characters and the conditions they test.
WORD MARKS
Formats a and b:
Word marks are not affected by this instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
JI (A)
NXT
A
A
NXT
Bp
BRANCH
NO BRANCH
Format b:
JI (Ap)
NXT
A
P
A
P
NXT
BRANCH
NO BRANCH
Bp
NOTES
1.
If the overflow indicator is tested and an overflow condition exists, the
indicator is automatically reset as a result of being tested. In all other
cases, the indicator tested is not reset as a result of the test.
2.
The com.parison indicators are:
a.
set by the Compare instruction;
b.
set by the Table Lookup instruction;
c.
stored (and cleared) by the Store Variant and Indicators instruction;
8-35
:/1:2-139
SECTION VIII.
Table 8-8.
INSTRUCTIONS
SENSE Switch Test Conditions for BCT Instruction
00
Unconditional
01
SENSE Switch 1 On
02
SENSE Switch 2 On
03
SENSE Switches 1 and 2 On
04
SENSE Switch 3 On
05
SENSE Switche s 1 and 3 On
06
SENSE Switche s ·2 and 3 On
07
SENSE Switches I, 2, and 3 On
10
SENSE Switch 4 On
11
SENSE Switches 1 and 4 On
12
SENSE Switche s 2 and 4 On
13
SENSE Switches I, 2, and 4 On
14
SENSE Switche s 3 and 4 On
15
SENSE Switches I, 3, and 4 On
16
SENSE Switches 2, 3, and 4 On
17
SENSE Switche s I, 2, 3, and 4 On
20
Unconditional
21
SENSE Switch 5 On
22
SENSE Switch 6 On
23
SENSE Switche s 5 and 6 On
24
SENSE Switch 7 On
25
SENSE Switches 5 and 7 On
26
SENSE Switche s 6 and 7 On
27
SENSE Switches 5, 6, and 7 On
30
SENSE Switch 8 On
31
SENSE Switche s 5 and 8 On
32
SENSE Switches 6 and 8 On
33
SENSE Switches 5, 6, and 8 On
34
SENSE Switche s 7 and 8 On
35
SENSE Switches 5, 7, and 8 On
36
SENSE Switche s 6, 7, and 8 On
37
SENSE Switche s 5, 6, 7, and 8 On
NOTE: When testing for a multiple SENSE switch condition, a branch occurs only
if all of the specified conditions are met.
8-36
#2-139
SECTION VIII.
Table 8-9.
INSTRUCTIONS
Indicator Test Conditions for BCT Instruction
40
Do not branch
41
B < A (Low Compare)
42
B =A (Equal Compare)
43
B~
44
B >A (High Compare)
45
BfA (Unequal Compare)
46
B~
47
Unconditional
50
Overflow
51
Overflow or B< A
52
Overflow or B=A
53
Overflow or
54
Overflow or B>A
55
Overflow
56
Overflow or
57
U nc onditi orial
60
Zero Balance
61
Zero Balance or BA
65
Zero Balance or BfA
66
Zero Balance or
67
Unconditional
70
Overflow or Zero Balance
71
Overflow or Zero Balance or B< A
72
Overflow or Zero Balance or B=A
73
Overflow or Zero Balance or
74
Overflow or Zero Balance or B >A
75
Overflow or Zero Balance or BfA
76
Overflow or Zero Balance or
77
Unconditional
A (Low or Equal Compare)
A (High or Equal Compare)
~
B~
A
BfA
B~
A
B~
B~
A
A
B~A
B~A
NOTE: When testing for a multiple indicator condition, a branch occurs if any
of the specified conditions is met.
8-37
~
#2-139
SECTION VIII.
INSTRUCTIONS
d.
restored by the Restore Variant and Indicators instruction;
e.
restored by the Resume Normal Mode instruction if coming
out of the external interrupt mode (but not out of internal
interrupt Ii1.ode);
f.
stored when an external interrupt occurs.
3.
The A addres s (if any) is placed in AAR during the extraction of thi s instruction' preserving any active high-order bits in AAR. If the instruction causes
a branch (i. e., if the condition being tested is present), the entire contents
of AAR specify the address to which the program branches when the instruction is executed. Also, the entire contents of SR are stored in BAR during
the execution phase of the instruction.
4.
Consider the variant character in its six-bit form V 6 V5 V 4 V 3 V 2 VI. The
following chart may be used to determine the variant character to be used
in a BCT instruction.
00 = Test SENSE
Switches 1
through 4
SENSE
Switch 4
SENSE
Switch 3
SENSE
Switch 2
SENSE
Switch 1
01 = Test SENSE
Switches 5
through 8
SENSE
Switch 8
SENSE
Switch 7
SENSE
Switch 6
SENSE
Switch 5
Overflow
High
Compare
Equal
Compare
Low
Compare
1 = Test
Zero
Balance,
Overflow,
or Compare
Zero
Balance
5.
SENSE switche s 5 through 8 are included as a standard feature with the Type
2201 and 4201 processors and are not available with the Model 200, 1200, or
1250 processors.
6.
This instruction can be coded only in format a. when programming for the
Type 201 or 201-1 processor.
EXAMPLE
Subtract CREDIT from TOTAL and test for a zero balance. If this condition exists
branch to BZRO; otherwise continue the program in sequence.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CARD
NUMBER
I
~I~
~ ~
2\3 415 6 7 8
1
I
LOCATION
OPERATION
CODE
1415
OPERANDS
S
~REDIT.TOT.AL
I
BCT
BZRO~q¢
I·
1
1
: :
I
80
6263
2021
:
1
PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
.1
1
8-38
#2-139
SECTION VIII.
INSTRUCTIONS
BRANCH ON CHARACTER
CONDITION
FORMAT
-- -- OP CODE
o.
b.
c.
d.
FUNCTION
A ADDRESS
B ADDRESS
-
VARIANT
ForITlat a:
The single character specified by the B address is exaITlined for the condition
specified by the variant character. If the condition is present. the prograITl branches
to the location specified by the A address, and the contents of the sequence regi ster (SR) are stored in the B -addre s s register (BAR). If the condition is not
present, the prograITl continues in sequence. The valid variant characters and the
condition each represents are listed in Tables 8-10 and 8-1I.
ForITlat b:
The single character specified by the B address is exaITlined for the condition
specified by the variant character of a previous instruction. If the condition is
present, the prograITl branches to the location specified by the A address, and the
contents of SR are stored in BAR. If the condition is not present, the prograITl
continues in sequence. The valid variant characters and the condition each represents are listed in Tables 8-10 and 8-1I.
ForITlat c:
The single character specified by the contents of BAR is exaITlined for a condition
specified by the variant character of a previous instruction. If the condition is
present, the prograITl branches to the location specified by the A address, ,and the
contents of SR are stored in BAR. If the condition is not present, the prograITl
continues in sequence. The valid variant characters and the condition each represents are listed in Tables 8-10 and 8-11.
ForITlat d:
The single character specified by the contents of BAR is exaITlined for a condition
specified by the variant character of a previous instruction. If the condition is
present, the prograITl branches to the location specified by the contents of the Aaddress register (AAR), and the contents of SR are stored in BAR. If the condition
is not present, the prograITl continues in sequence. The valid variant characters
and the condition each represents are listed in Tables 8-10 and 8-11. Series 200
processors which are equipped with the advanced prograITlITling instructions (see
Table 1-11, page 1-18) can interpret any bit configuration of the variant character, ranging froITl octal 00 to octal 77:--The valid variant characters which can
be interpreted with this option are shown in Table 8-11 and expanded in Appendix B.
8'-39
#2-139
SECTION VIII.
Table 8-10.
INSTRUCTIONS
Basic Test Conditions for BCC Instruction
00
Unconditional
02
The B bit of the character at B is 1.
06
The character at B contains
B and A bits are 10).
10
The character at B contains either a word mark
or a record mark (the word-mark bit is 1).
12
The B bit is I and the word-mark bit is 1.
16
The characte r at B contains a negative sign and
the word-mark bit is 1.
20
The character at B contains either an item mark
or a record mark (the item-mark bit is 1).
22
The B bit is I and the item-mark bit is 1.
26
The character at B contains a negative sign and
the item-mark bit is 1.
--
30
The character at B contains a recQ\rd mark (the
word-mark and item-mark bits are 11).
32
The character at B contains a record mark and
the B bit is 1.
36
The ch~racter at B contains a record mark and a
negative sign.
a negative sign (the
WORD MARKS
Formats a, b, c, and d:
Word marks are not affected by this instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
JI (A)
NXT
A
A
NXT
B-1
BRANCH
NO BRANCH
Format b:
JI (A)
NXT
A
A
NXT
B-1
BRANCH
NO BRANCH
Format c:
JI (A)
NXT
A
A
NXT
Bp-l
BRANCH
NO BRANCH
Format d:
JI (Ap)
NXT
Ap
Ap
NXT
B -1
BRANCH
NO BRANCH
P
8-40
#2-139
SECTION VIII.
Table 8-11.
BCC Te st Conditions with Advanced Programming Instructions
XO
No condition.
Xl
The A bit of the character at B is 1.
XZ
The B bit of the character at B is 1.
X3
The B and A bits of the character at Bare 11.
X4
The B and A bits of the character at Bare 00.
X5
The character at B contains a positive sign (the
B and A bits are 01).
X6
The character at B contains a negative sign (the
B and A bits are 10).
X7
The B and A bits of the character at Bare 11
(same as X3 above).
OX
No condition.
IX
The word-mark bit of the character at B is 1
(either a word mark or a record mark is present).
2X
The item-mark bit of the character at B is 1
(either an item mark or a record mark is present).
3X
The character at B contains a record mark.
4X
The character at B contains no punctuation mark.
5X
The character at B contains a word mark only, not
an item mark.
The character at B contains an item mark only, not
a word mark.
This is a special case; see note 2.
6X
7X
NOTES'!
INSTRUCTIONS
1.
An X repre sents any octal digit. If both octal digits specify "no
condition" (i. e., 00), the branch occurs unconditionally. If only
one digit is 0, the branch occurs if the condition specified by the
other digit is met. If both octal digits specify conditions, the branch
occurs ifboth conditions are met. The variant character 7X is an
exception to these rules, as described in note 2.
2.
The Type 201 and 201-1 processors interpret a 7X variant as if it
were a 3X (i. e. , branch to the A addre s s if the character at B
contains a record mark and the condition specified by X is met).
All other processors interpret the 7X variant as follows:
a.
If X is 0, the branch is an unconditional branch.
b.
If X is any digit other than 0, the branch occurs if
either the condition specified by the rightmost digit is
met or the character at B contains a word mark.
8-41
#2-139
SECTION VIII.
INSTRUCTIONS
NOTES
1.
If the octal configuration of the variant character is 00 or 70, the branch
is unconditional.
2.
The A address (if any) is placed in AAR during the extraction of the BCC
instruction, preserving any active high-order bits in AAR. If the instruction causes a branch (i. e., if the condition being tested is present), the
entire contents of AAR specify the address to which the program branche s
when the instruction is executed. Also, the entire contents of SR are
placed in BAR during the execution phase.
3.
This instruction can be coded only in formats a. and d. when programming
for the Type 201 or 201-1 processor.
EXAMPLE
If the location tagged END contains a negative sign, branch to the location tagged
NFIELD. Otherwise, continue the program in sequence.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _----'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
~ ~.
~~
1 213 415 6 7 8
I
:
LOCATION
OPERATION
CODE
1415
OPERANDS
6263
2021
BCe
80
NFl ELD",END~,~6
BRANCH IF
CHARACTER EQUAL
IFEATURES 010
& 011
FORMAT'
-- -- -
OP CODE
o.
b,
c,
d.
A ADDRESS
B ADDRESS
-
VARIANT
FUNCTION
Format a:
The single character specified by the B address is compared to the variant character. If the bit configurations of the two characters are equal, the program branches
to the location specified by the A address, and the contents of the sequence register
(SR) are stored in tbe B-address register (BAR). If the bit configurations are
unequal, the program continues in sequence.
Format b:
The single character specified by the B address is compared to the variant character specified in a previous instruction. If the bit configurations of the two characters are equal, the program branches to the location specified by the A addres Sj
8-42
#2-139
SECTION VIII.
INSTRUCTIONS
and the contents of SR are stored in BAR.
the program continues in sequence.
If the bit configurations are unequal,
Format c:
The single characte r specified by the contents of BAR is compared to the variant
character specified in a previous instruction. If the bit configurations of the two
characters are equal, the program branches to the location specified by the A address, and the contents of SR are stored in BAR. If the bit configurations are
unequal, the program continues in sequence.
Format d:
The single character specified by the contents of BAR is compared to the variant
character specified in a previous instruction. If the bit configurations of the two
characters are equal, the program branches to the location specified by the contents of the A-address register (AAR), and the contents of SR are stored in BAR.
If the bit configurations are unequal, the program continues in sequence.
WORD MARKS
Formats a, b, c, and d:
A word mark in the location tested has no
effec~
on the instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
JI (A)
NXT
A
A
NXT
B-1
BRANCH
NO BRANCH
Format b:
JI (A)
NXT
A
A
NXT
B-1
BRANCH
NO BRANCH
Format c:
JI (A)
NXT
A
A
NXT
B -1
P
BRANCH
NO BRANCH
Format d:
JI (Ap)
NXT
Ap
Ap
NXT
Bp-I
BRANCH
NO BRANCH
NOTES
1.
This instruction can be coded only in formats a. and d. when programming
for the Type 201 or 201-1 processor.
2.
The A address (if any) is placed in AAR during the extraction of the BCE
instruction, preserving any active high-order bits in AAR. If the instruction causes a branch (i. e., if the condition being tested is present), the
entire contents of AAR specify the address to which the program branches
when the instruction is executed. Also, the entire contents of SR are
placed in BAR during the execution phase.
3.
When the central processor is in the "S" mode, execution of the BCE instruction sets the comparison indicators to show whether B>V, B=V, or B B+(NB u ) (Nut)} WORD MARK IN TABLE
STOPS OPERATION
BAR
ITEM MARK IN A ITEM
STOPS OPERATION
NOTES
1.
This instruction cannot be chained.
2.
The last six-bit character referenced in the translation table (whether
word-marked or not) is left in the variant register following the move
item and translate operation.
8-77
#2-139
SECTION VIII.
INSTRUCTIONS
3.
Item-mark bits as well as data bits are transferred from the translation
table to the B item.
4.
Word marks initially stored in the B item remain unchanged.
not affect the execution of this instruction.
5.
A data control character (e. g., a case-shift character in a teletype code),
rather than a translated equivalent to be transferred to, the B item, can
be stored in a word-marked location in the table. When this w'ord-marked
location is sensed, the character in that location is not moved; rather,
the contents of SR and CSR are interchanged, providing entry to the routine
whose beginning address was previously stored in CSR. Since the wordmarked character is stored in the variant register (see note 2), that character can be stored by a Store Variant and Indicators instruction (see
page 8-92) and subsequently tested for identification in the routine.
6.
The base address of the translation table must be a multiple of at least
64, due to the positions of variants 1 and 2 in the total 19-bit address.
This requirement is sufficient only for the translation of 6-bit to 6-bit
codes. If other than 6-bit codes are involved in the translation, the base
addres s of the table must be a multiple of X (where X is the product of
the number of -codes defined by active bits in the A field entries times the
number of characters in each table entry). In other words, the base address of the table must be a multiple of the table size itself. The MORG
assembly control statement (see page 7-9) can be used to assign memory
lo.cations to the translation table, starting with th~ next available memory
location whose address is a multiple of 64, 128, 256, etc., as determined
by the size of the table.
7.
This instruction is a standard feature on all processors except the Types
20 1 and 20 1-1, on which it is not available.
They do
EXAMPLE
Figure 8-7 shows how eight-bit code is translated to Series 200 six-bit character
code by means of a stored translation table. Each eight-bit information unit is
stored in two consecutive six-bit character locations in the A item tagged EIGHT.
Translate the data contents of the item tagged EIGHT using the translation table
whose base address is location 512 10 (100°8)' Store the translated values (sixbit characters) in the item tagged SIX.
A Address:
EIGHT (absolute value = location 800)
B Address:
SIX
Variant 1:
Variant 2:
:~ : }the address of table (location 512)
Variant 3:
01
(absolute value = location 650)
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:
LOCATION
OPERATION
CODE
1415
IMIT
OPERANDS
6263
2021
80
El G-}\T, •. S.lX ,,~0.. 1.~, .r1.1
8-78
#2-139
SECTION VIII.
INSTRUCTIONS
BASE ADDRESS
(001000 8 )
ITEM MARK STOPS
OPERATION
• TABLE ADDRESS
.ENTRIES
,.._.lIlI
__
·
........._.... .....--
ADDRESS
-
.B ITEM
Figure 8 -7.
I LIB
MIT Operation
I LOAD INDEX/BARRICADE REGISTER
FORMAT
-- -
OP CODE
o.
b.
A ADDRESS
B ADDRESS
I FEATURES
1114, 11 1 7 AND 1118
I FEATURES
1118, 11 20 AND 1121
FUNCTION
Format a:
Basic storage protection is provided by this instruction format; the character(s) at the location(s) specified by the A address is loaded into the index/
barricade register (IBR), specifying the number of 4, 096-character main
memory banks which are available to a program. The leftmost location of
the specified bank is the leftmost location of the protected memory area.
(The rightmost location of the protected area is the rightmost location of memory.) For processors other than the Type 4201, the single-character contents
of A are loaded into IBR. For the Type 4201 processor, a seventh bit, the
rightmost bit of the contents of A-I, is loaded into IBR. The correspondence
between the number loadeq. into IBR and the position of the barricade is in Table 8-18.
Format b:
Storage protection with bas e relocation is provided by this instruction
format; the index/barricade register (IBR) is loaded in the same manner
as for basic storage protection (format a above), but the barricade is
relocated relative to the base relocation address. Consequently, when
storage protection is in effect, data cannot be delivered to memory locations above the barricade or below the bas e relocation addres s unles s
processing is in the interrupt mode. The character(s) at the location(s)
8-79
#2-139
SECTION VIII.
INSTRUCTIONS
specified by the B addres s is loaded into the base relocation register (BRR).
specifying the number of 4, 096 -character main memory banks which are
available to a program. The number of main memory locations so designated
a'ugl1.1.eiitS all rrleniory references nladc in the standard (norJ.nterr'upt) m.ode.
For processors other than the Type 4201, the single-character contents of B
are loaded into BRR. For the Type 4201 processor, a seventh bit, the rightmost bit of the contents of B-1, is loaded into BRR. The character(s) specified
by the A address is loaded into the index/barricade register (IBR), specifying
the number of a 4, 096 -character main memory bank. The barricade is established to the left of the leftmost location in the specified bank (as augmented
by the base relocation addres s). For proces sors other than the Type 4201, the
single -character contents of A are loaded into IBR. For the Type 4201 processor, a seventh bit, the rightmost bit of the contents of A-I, is loadedinto
IBR. The correspondence between the number loaded into IBR and the position of the barricade is shown in Table 8 -18.
Table 8-18.
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
40
41
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Correspondence Between LIB Setting and Barricade Location
0
4,096
8, 192
12,288
16, 384
20,480
24, 576
28, 672
32,768
36,864
40, 960
45, 056
49,152
53,248
57, 344
61,440
65,536
69, 632
73,728
77,824
81,920
86,016
90, 112
94, 208
98, 304
102,400
106,496
110,592
114,688
118,784
122,880
126, 976
131,072
135,168
1
1
1
1
8-80
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
00
01
02
03
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
139,264
143, 360
147,456
151,552
155,648
159,744
163,840
167,936
172,032
176,128
180,224
184, 320
188,416
192,512
196,608
200,704
204,800
208,896
212,992
217,088
221, 184
225,280
229, 376
233,472
237,568
241,664
245,760
249,856
253,952
258,048
262, 144
266,240
270, 336
274,432
#2-139
SECTION VIII.
Table 8 -18 (cont).
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Correspondence Between LIB Setting and Barricade' Location
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
04
05
06
07
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34
35
36
37
1 40
1 41
INSTRUCTIONS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
278,528
282,624
286,720
290,816
294,912
299,008
303, 104
307,200
311, 296
315,392
319,488
323,584
327,680
331,776
335,872
339, 968
344,064
348, 160
352,256
356,352
360,448
364,544
368,640
372,736
376,832
380,928
385,024
389,120
393,216
397,312
1
1
1
1
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
401,408
405,504
409,600
413,696
417,792
421,888
425,984
430,080
434,176
438,272
442,368
446,464
450,560
454,656
458,752
462,848
466,944
471,040
475, 136
479,232
483,328
487,424
491,520
495,616
499, 712
503,808
507,904
512,000
516,096
520,192
WORD MARKS
Formats a and b:
Word marks are not affected by thi s instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a:
NXT
A-2
B
Format b:
NXT
A-2
B-2
P
NOTES
1.
The 15 additional index registers which are included in the Storage Protect
and Extended Multiprogramming Features are located in the first 60 character
locations to the right of the barricade position specified by this instruction.
These locations can be used as normal storage locations when they are not
being used for indexing operations.
8-81
#2-139
SECTION VIII.
INSTRUCTIONS
2.
The LIB op code is a "privileged" op code which has special significance
when storage protection is in effect with the Type 1201, 1251, 2201, or
4201 processor (see Appendix E).
3.
This instruction is intended for use in the interrupt I-ilode alld s110uld nuL
be issued in the standard Illode.
4.
The LIB instruction is not interpreted by Easycoder A sseIllbler A, B, or C.
EXAMPLE
AssuIlling that there are 131,072 storage locations in the main IlleIllory, set up the
memory in such a way that the "open" memory area consists of locations 0 through
65,535 and the protected memory area consists of locations 65,536 through
131,072. The single octal character "20" is contained in the location tagged MP2.
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1 2\3 415 6 7 8
I
i
OPERATION
CODE
1415
L 'B
OPERANDS
2021
62 63
80
M\l'l
I 5 I B ISTORE INDEX/BARRICADE REGISTER I
FORMAT
-- --
OP CODE
o.
b.
FUNCTION
A ADDRESS
B ADDRESS
_ _I
I FEATURES
1114, 1117, AND 1118
I FEATURES
1118, 1120, AND 1121
Format a:
Basic storage protection is provided by this instruction format; the contents
(up to seven bits) of the index/barricade register (IBR) are stored in the character
location(s) specified by the A address. All high-order bit positions in A which
are not used to specify the contents of the index/barricade register are cleared
to zeros. In the Type 4201 processor only, the seventh bit in IBR is stored in the
rightmost bit position of location A-I and the five remaining bit positions in A-I
are cleared to zeros.
Format b:
Storage protection with bas e relocation is provided by this instruction format;
the contents of the index/barricade register (IBR) are stored in the same manner
as for basic storage protection (format a, above); in addition, the contents of the
base relocation register (BRR) are also stored. The contents (up to seven bits)
of BRR are stored in the character location(s) specified by the B addres s. All
high-order bit positions in B which are not used to specify the contents of the
base relocation register are cleared to zeros. In the Type 4201 ?roces sor only,
the seventh bit in BRR is stored in the rightmost bit position of location B-1 and
the five remaining bit positions in B-1 are cleared to zeros. The contents (up to
seven bits) of the index/barricade register are stored in the character location(s)
specified by the A address. All high-order bit positions in A which are not used
to specify the contents of the index/barricade register are cleared to zeros. In
the Type 4201 processor only, the seventh bit in IBR is stored in the rightmost bit
position of location A-I and the five remaining bit positions in A-I are cleared to
zeros.
8-82
#2-139
SECTION VIII.
INSTRUCTIONS
WORD MARKS
Formats a and b:
Word marks are not affected by this instruction.
ADDRESS REGISTERS AFTER OPERATION
BAR
AAR
SR
Format a:
NXT
A-2
Format b:
NXT
A -2
B-2
NOTE
1.
The SIB instruction is not interpreted by Easycoder Assembler A, B, or C.
2.
This instruction is intended for use in the interrupt mode and should not be
issued in the standard mode.
EXAMPLE
Store the contents of the index/barricade register in the single character location
tagged PROT.
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1 213 415 6 7 8
I
:
I TLU
OPERATION
CODE
1415
OPERANDS
2021
SIB
i
6263
80
PROT
ITABLE LOOKUP 1 I FEATURE 0191 1
FORMAT
-- -- -
OP CODE
o.
b.
c.
d.
FUNCTION
A ADDRESS
B ADDRESS
Format a: A table in memory is a series of fields,
ment of a function and the corresponding
The Table Lookup instruction initiates a
which bears a specified relationship to a
instruction (see illustration below).
8-83
-
VARIANT
each of which normally contains an arguvalue of the function (see notes 1 and 2).
search in a stored table for an argument
search argument, which is stated in the
#2-139
SECTION VIII.
INSTRUCTIONS
The B address specifies the rightmost location of the stored table, the A address
specifies the location of the search argument, and the variant character specifies
a relationship (equal to, higher than, etco) between the desired argument in the
table and the search argument. The table is searched. trom rIgnt to lett untll thlS
relationship is found or until a table field i s found which is shorter than the search
argument. Then comparison indicators are turned on and the search terminates.
Format b: Search the table whose rightmost location is specified by B for an argument which
bears to the search argument specified by A a relationship specified by the variant
character of a previous instruction. When this relationship is found or when a
table field is found which is shorter than the search argument, turn on comparison
indicators and terminate the search.
Format c: Search the table whose rightmost location is specified by the contents of the B-address register (BAR) for an argument which bears to the search argument specified
by A a relationship specified by the variant character of a previous instruction.
When this relationship is found or when a table field is found which is shorter than
the search argument, turn on comparison indicators and terminate the search.
Format d: Search the table whose rightmost location is specified by the contents of BAR for
an argument which bears to the search argument specified by the contents of the
A-address register (AAR) a relationship specified by the variant character of a
previous instruction. When this relationship is found or when a table field is found
which is shorter than the search argument, turn on comparison indicators and
terminate the search.
WORD MARKS
Formats a, b, c, and d:
The A operand (the search argument) must have a defining word mark.
table field must also have a defining word mark.
Each
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
BAR
Format a: NXT
A-Na
L ta
Format b: NXT
A-N
a
L ta
Format c: NXT
A-Na
L ta
Format d: NXT
Ap-Na
L ta
NOTES
1.
Each value in the table is normally stored immediately to the left of the
corresponding argument, and each pair (argument plus value) constitutes
a field in the table. However, if the values in the table are longer than
three characters, it is advisable to store them in another part of memory
and to store their 2- or 3-character addresses in the table instead. Since
the timing of the TLU instruction depends on the number of characters
searched in the table, it is desirable to minimize the length of the table.
2.
The Branch on Condition Test instruction (see page 8-35) canbe used after
Table Lookup to branch to a routine which moves the located value to a work
area. Note that at the completion of the TLU instruction, the B-address
8-84
#2-139
SECTION VIII.
INSTRUCTIONS
register (BAR) contains the address of the desired value (or the address of
a location containing the address of the desired value, in the case where the
value s are too long for efficient storage in the table).
3.
The variant characters which specify the desired relationships between the
search argument and the argument to be located in the table are as follows:
01
Stored Argument < Search Argument
02
Stored Argument = Search Argument
03
Stored Argument S Search Argument
04
Stored Argument> Search Argument
05
Stored Argument
f. Search Argument
06
Stored Argument
~
Search Argument
4.
The length of each argument in the table must be equal. to the length of the
search argument. Note that a short table field (e. g., one which contains a
short argument or which contains no value) can be used to terminate the search,
which leaves the comparison indicators set to the condition "Stored Argument>
Search Argument. "
5.
The Table Lookup instruction is not interpreted by Easycoder Assembler A,
B, or C.
6.
Although the Series 200 hardware will chain the variant character of a Table
Lookup instruction, the Mod 2 Assembler permits such chaining only if the B
address of the instruction is also chained.
7.
Easycoder Assembler D and Mod 2 Assembler:
a.
b.
c.
8.
Format a must use the generic op code (TLU) along with an
explicit variant character.
Format b must use a specific op code (e. g., LEH) in order to
supply the omitted variant character.
Formats c and d always use the variant character from the
previous contents of the variant register. Therefore, the op
code used should agree with the one used previously or be the
generic form (TLU).
The Table Lookup instruction is used by the Series 200 Mod 2 Assembler to
implement a number of symbolic statements. The following table indicate s
the correspondence between the mnemonic op codes for these statements
and the TLU variants generated by the Mod 2 Assembler.
LE
Lookup Equal
02
LH
Lookup High
04
LL
Lookup Low
01
LEH
Lookup Equal or High
06
LLE
Lookup Low or Equal
03
LLH
Lookup Low or High (Unequal)
05
8-85
#2-139
SECTION VIII.
INSTRUCTIONS
EXAMPLE
1.
Figure 8 -8 shows how a stored table is searched for an argument which
bears a specified relationship to a search argument.
Search the table tagged TABLEI for the value which corresponds to the argument
(557) stored in the field tagged ARGMNT.
A Address:
ARGMNT (absolute value = location 609)
B Address:
TABLEI (absolute value = location 149)
Variant 1:
02
= (Stored Argument = Search Argument)
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i
_ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF'_
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CODE
1415
l
~
TLU
OPERANDS
2021
62 63
~
80
ARGMNT , lAB l E 1.• 02
I
I
INos I
MOVE OR SCAN
I
1 FEATURE
0191 1
FORMAT
-- -- OP CODE
o.
b.
c.
d.
FUNCTION
A ADDRESS
B ADDRESS
-
VARIANT
Format a:
The contents of the A field are moved to the B field in the manner specified
by the variant character (see Table 8-19). The programmer specifies how
the move operation is to be performed by selecting the desired conditions
from the table and encoding the resulting two octal digits as the variant character of the instruction. See note Sa.
Format b:
This format is valid in symbolic coding only when a specific op code is used
to indicate the omitted variant character. The resultant machine-language
format and functions are the same as those de scribed for format a.
Format c:
The contents of the A field are moved to the field specified by the contents
of the B-address register (BAR) in the manner specified by the variant character of a previous instruction (see Table 8 -19). See note 5c.
Format d:
The contents of the field specified by the contents of the A -address register
(AAR) are moved to the field specified by the contents of BAR in the manner
specified by the variant character of a previous instruction (see Table 8-19).
See note 5c.
8-86
#2-139
en
M
()
~
1-1
o
Z
<:
1-1
1-1
1-1
(X)
I
(X)
' - - - - - B FIELD
-.]
t-
Z
(J}
I-j
~
EQUALITY OF A-FIELD
'------TO STORED ARGUMENT
TERMINATES OPERATION
c::
()
I-j
t-
O
Z
en
"SHORT FIELD" WHICH
'--_ _ _ _ TERMINATES SEARCH IF
SPECIFIED RELATIONSHIP
IS NOT FOUND
::jj:::
N
I
.-
v.>
-..0
Figure 8-8.
TLU Operation
SECTION VIII.
Table 8-19.
INSTRUCTIONS
Move or Scan Conditions
XO
No information is moved. The A - and B -addres s registers
are incremented or decremented in accordance with the
high-order digit of the variant character.
Xl
Move A -field numeric bits to corresponding bit positions in
B field.
X2
Move A -field zone bits to corre sponding bit positions in
B field.
X3
Move A -field data and item-mark bits to corre sponding bit
positions in B field.
X4
Move A ... field word-mark bits to corre sponding bit positions
in B field.
X5
Move A-field numeric and word-mark bits to corresponding
bit positions in B field.
X6
Move A-field zone and word-mark bits to corresponding bit
positions in B field.
X7
Move A -field data, word-mark, and item-mark bits to corresponding bit positions in B field.
OX
Move one character from A to B. The A- and B-address
registers are decremented by one.
IX
Move characters from left to right (A and B addresses
specify leftmost characters in operand fields). Terminate
the operation when the first A- or B-field word mark is
sensed.
2X
Move characters from right to left (A and B addresses
specify the rightmost characters in operand fields). Terminate the operation when the first A -field word mark is
sensed.
3X
Move characters from left to right. Terminate the operation when the control character "@" (72 ) is sensed in the
8
A field.
4X
Move characters from right to left. Terminate the operation when the first B-field word mark is sensed.
5X
Move character s from left to right. Terminate the operation when the control character "; " (32 ) with a word mark
8
if?J sensed in the A field.
6X
Move characters from right to left. Terminate the operation when the first A- or B-field word mark is sensed.
7X
Move characters from left to right. Terminate the operation when either the control character ";" (32 ) with a
8
word mark or control character "@" (72 ) is sensed in
8
the A field.
8-88
#2-139
SECTION VIII.
INSTR UCTIONS
WORD MARKS
Formats a, b, c, and d:
Word marks and control characters affect the operation of the instruction as
described in the table above.
ADDRESS REGISTERS AFTER OPERATION
Format a:
Format b:
Format c:
Format d:
SR
AAR
BAR
NXT
A-I
B-1
NXT
A+N
NXT
A-N
NXT
A+N
NXT
A-N
NXT
A-N
w
NXT
A-I
NXT
A+N
NXT
A-N
NXT
A+N
NXT
B-N
VARIANT = 4X
NXT
A-N
b
A-N
B-N
VARIANT = 6X
NXT
A-I
B
-1
VARIANT = OX
B +N
p
w
B -N
p
a
B +N
p
a
B -N
p
b
B -N
p
w
VARIANT = IX
w
NXT
A-N
NXT
A+N
NXT
A-N
NXT
A-N
NXT
A
NXT
NXT
NXT
b
a
a
w
A+N
NXT
a
w
NXT
NXT
a
w
a
a
b
w
P
-1
A +N
P
w
A -N
p
a
A +N
P a
A -N
p
b
A -N
p
w
VARIANT = OX
B+N
w
B-N
B+N
VARIANT
VARIANT = 2X
a
VARIANT = (3, 5, or 7)X
a
B-N
b
B-N
VARIANT
B-1
VARIANT
w
B+N
w
B-N
B+N
= OX
VARIANT = IX
= 2X
VARIANT = (3, 5, or 7)X
a
w
B
= 4X
VARIANT = 6X
VARIANT
a
b
P
= IX
VARIANT = 2X
VARIANT = (3, 5, or 7)X
VARIANT
VARIANT
= 4X
= 6X
-1
VARIANT = OX
B +N
P w
VARIANT = IX
B
VARlANT = 2X
P
P
-N
B +N
p
a
a
VARIANT = (3, 5, or 7)X
B -N
VARIANT
= 4X
B -N
VARIANT
= 6X
p
p
b
w
NOTES:
1.
This instruction is available only on the 1201, 1251, 2201, and 4201 (standard)
central processors.
8-89
#2-139
SECTION VIII.
INSTRUCTIONS
2~
The character containing the terrninating punctuation and/or control characters is rnoved or scanned in the sarne rnanner as the rest of the field.
3.
The variant characters and the corresponding :mnemonic op codes \vhich
they represent are contained in Appendix B.
4.
The Move or Scan instruction is not interpreted by the Easycoder Assernbler
A, B, or C.
5.
Although the Series 200 hardware will chain the variant character of a Move
or Scan instruction, the Mod 2 Assernbler perrnits such chaining only if the
B address of the instruction is also chained.
6.
Easycoder Assernbler D and Mod 2 Assernbler:
a.
b.
c.
7.
Forrnat a rnust use the generic op code (MaS) with an explicit
variant character.
Forrnat b rnust use a specific op code (MLCW) to supply the
ornitted variant.
Forrnats c and d always use the variant character frorn the
previous contents of the variant register. Therefore, the op
code used should either agree with the one used previously or
be the generic forrn (MaS).
The Move or Scan instruction is used by the Series 200 Mod 2 Assernbler to
irnplernent a nurnber of syrnbolic staternents.. Table B-9 in Appendix B indicates the correspondence between the rnnemonic op codes for these statements and the MaS variants generated by the Mod 2 Assernbler.
EXAMPLE
Move only the zone bits in'the field tagged TEMP to the field tagged WORK
frorn right to left, and terrninate the operation when the fir st word rnark
in the B field is sensed.
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213 415 6 7 9
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1
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LOCATION
OPERATION
COOE
1415
!lAnA
OPERANDS
6263
2021
eo
TF"MI> ,.,l4IaRIL , ,42
1
8-90
#2-139
- STORE VARIANT AND INDICA TORS
-RESTORE VARIANT AND INDICATORS
- MONITOR CALL
- RESUME NORMAL MODE
8-91
#2-139
SECTION VIII.
SVI
INSTRUCTIONS
STORE VARIANT AND
INDICATORS
FORMAT
-
OP CODE
FUNCTION
A ADDRESS
B ADDRESS
-
VARIANT
The SVI instruction is used to store information regarding the current status of the
processor when an interrupt condition occurs. The instruction stores the designated
information in up to six consecutive locations following its own variant character.
Each bit in the six-bit variant character (V 6 V 5 V 4 V 3 V 2 VI) represents proces sor
control registers or indicators whose contents are to be stored in a single character
location. The programmer specifies the amount of information to be stored by
selecting the desired entries from Table 8-20 and encoding the resulting bit configuration as two octal digits.
Table 8-20.
x
X X X X 1
X X X X 1 X
Information Stored by'SVI Instruction
The contents of the variant register.
The settings of the arithmetic, comparison, address mode, and item-mark trap mode indicators.
This information is stored in seven bit positions
of the character location - the six data bit p.ositions and. the item-mark bit position.
The arithmetic and comparison indicators are
cleared when their contents have been stored.
XXXIXX
The contents of the auxiliary indicators register
(AIR). The contents of the arithmetic, comparison,
address mode, and item mark trap mode indicators are stored automatically, in this register
upon the occurrence of an external interrupt.
Upon executing an RNM instruction to return to
either standard or internal interrupt mode, the
specified indicators are reset automatically using
the contents of this register. The contents of
this register can be changed by using the R VI
instruction (see page 8 -95).
The auxiliary arithmetic and compari son indicators are cleared when their conterits have
been stored.
XXI
XXX
The settings of the indicators associated with the
scientific unit (see Appendix F) and the sector interrupt
masks 2 (see Appendix G). The scientific indicators are
cleared when their cant
8-92
#2-139
SECTION VIlle
Table 8-20 (cont).
INSTRUCTIONS
Information Stored by SVI Instruction
X1XXXX
The settings of the protect, 1 proceed, 1 instruction timeout
allow,2 S-mode, and relocation 2 indicators and (if the
processor is in the external interrupt mode) the setting of
the internal interrupt (II) mode indicator. 1
1XXXXX
The protect, proceed, and instruction time out allow indicators are cleared when their contents are stored.
The settings of the interrupt source indicators 1 and the
instruction time out indicator. The stored settings of the
interrupt source indicators can be tested to determine the
status of the processor a's follows:
1.
Whether the proces sor is in the external interrupt
mode, the internal interrupt mode, or the standard
processing mode.
2.
The source of the interruption if the proces sor is
in the external interrupt mode; any of three sources
can be determined - a peripheral control, the control panel (or console), or the Monitor Call instruction (seepage 8-98).
3.
Whether an external interrupt (EI) address violation
has occurred (if the processor is in the external
interrupt mode).
4.
Whether an op code violation has occurred (if the
processor is in the internal interrupt mode).
5.
Whether an internal interrupt (II) address violation
has occurred (if the processor is in the internal
interrupt mode).
The indicators referred to in 3 through 5, above, as well
as those which identify the control panel (or console) and
the Monitor Call instruction as the interrupt source, are
cleared when their contents are stored.
lThese indicators are included in a Type 1201, 1251, or 2201 processor equipped with the
Storage Protect Feature (see Appendix E) or a Type 4201 processor equipped with
the Extended Mu1tipro~gramming and 8-Bit Transfer ~eature (see Appendix G).
2These indicators are included in a Type 1201,1251, 2201, or 4201 processor equipped
with the Extended Multiprogramming and 8-Bit Transfer Feature (see Appendix G).
WORD MARKS
A word mark is required in the location following the variant character to terminate
the extraction of the SVI instruction. , Other word marks (if any) in the locations
in which information is stored are ignored and unaffected. Program operation
resumes with the next word-marked location following the stored information (the
next sequential op code).
8-93
#2-139
SECTION VIII.
INSTRUCTIONS
ADDRESS REGISTERS AFT1!;R OPERATION
SR
AAR
BAR
NXT
VI
0
V2
Trapmode:
1 =yes;
O=no.
V3
V
4
Contents of Variant Register
Address mode:
01 =2 -character;
00=3-character;
11 =4-character.
Ove
l=yes;
O=no.
Zero
Balance:
1 =yes;
O=no.
~~
A~B.:
l=yes;
O=no.
= B:
1 =yes;
O=no.
~(
*
*
Contents of AIR (identical to information stored by V2, above)
>:c
*
*
>:c
Extended
I/O Indicator
I = ON;
0= OFF.
MPO:*
1 =yes;
O=no.
DVC:*
1 =yes;
O=no.
EXO:*
1 =yes;
O=no.
Sector 0
Interrupt
Mask:
l=on;
O=off.
Sector I
Inter
Mask:
l:on;
O=off.
Sector 2
Interrupt
Mask:
1
on;
o off.
0
Protect
indicator:
l=on;
O=off.
Instruc ...
tion
Timeout
Allow:
l=on;
O=off.>!c
S mode
Proceed
indicator:
l=on;
O=off.
Relocation
Indicator:
1 =on;
O=off.
In external
interrupt
mode only:
1 =II indicator on;
otherwise, O.
Vs
~!<
~::::
=
=
Processdr is in external interrupt mode
0
V6
EI Address
violalation:
1 =yes;
O=no.
Monitor
Call:
1 =yes;
O=no.
>:c
*
II Address
violation:
l=yes;
O=no.
>.'c
Peripheral
interrupt:
1 =yes;
O=no.
1
II Mode
indicator:
l=on;
O=off.
*
in external interrupt mode
Processor is
o
Control
panel or
console
interrupt:
l=yes;
O=no.
Op code
violation:
l=yes;
O=no.
*
Instruction
Timeout
Indicator
1 =yes;
O=no.
0
o
1
>:~
)!c= Indicators that are cleared when their contents are stored.
NOTES
1.
Only the number of characters specified by the variant character are
stored. They are stored in the order listed in Table 8-20: the contents
of the variant register (if specified) are stored in the location immedi8-94
#2-139
SECTION VIII.
INSTRUCTIONS
ately fo11owing the SVI instruction, etc., using only those locations
actually required to store the requested inform.ation.
2.
Item.-m.ark and data bit positions which are not used to store inform.ation are cleared to zeros.
3.
The form.at in which inform.ation is stored by the SVI instruction is
shown in the preceding table. Indica.tors which are cleared (i. e., set
to zero) when their contents are stored are indicated by an asterisk (>.'<).
4.
Bits corresponding to indicators which are not present in the user's
processor are stored as zeros. For instance, an SVI instruction
issued in a processor which does not contain the Storage Protect
Feature wi11 store zeros in those bit positions which correspond to
indicators used only with the Storage Protect Feature.
5.
The current status of the arithm.etic, com.parison, address m.ode,
and trap m.ode indicators are not stored in the auxiliary indicators
register (AIR) when an internal interrupt occurs. The contents of
AIR should therefore not be stored by an SVI instruction in the internal
interrupt m.ode, for the contents of AIR would be m.eaningless at the
tim.e of internal interruption.
6.
The SVI op code is a "privileged" op code that has special significance
when issued in a Type 1201, 1251, 2201, or 4201 processor equipped
with the Storage Protect Feature (see Appendix E).
7.
This instruction is intended for use in the interrupt m.odeand should not
be issued in the standard m.ode.
8.
This instruction is a standard feature on a11 processors but the Types
201 and 201-1, on which it is not available.
9.
The m.ethod of coding interrupt service routines is described in
Appendix D, "Interrupt Processing. "
10.
The contents of the variant register are not altered by the execution of
this instruction; i. e., the variant character of the SVI instruction is not
stored therein.
EXAMPLE
Store the following inform.ation in the three successive m.em.ory locations which im.m.ediately follow the variant character of the instruction:
1.
The contents of the variant register;
2.
The contents of the auxiliary indicators register (AIR); and
3.
The settings of the interrupt source indicators.
The op code of the SVI instruction is tagged STORE, so that the locations of the stored
inform.ation are STORE+2, STORE+3, and STORE+4.
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:
OPERATION
CODE
LOCATION
1 213 415 6 7 8
1415
STORE
sv,
OPERANDS
2021
62 63
80
4.5.
RESTORE VARIANT AND
INDICATORS
FORMAT
-
OP CODE
A ADDRESS
B ADDRESS
-
VARIANT
8-95
#2-139
SECTION VIII.
INSTRUCTIONS
FUNCTION
Up to five consecutive characters (previously stored via an SVI instruction) are
loaded into the processor control registers and/or indicators specified by the
variant character. Characters are retrieved from. left to right, beginning with
the character specified by the A address.
The low-order five bits of the variant character specify the registers and/or
indicators whose contents are to be restored. The program.m.er specifies the
am.ount of inform.ation to be restored by selecting the desired entries from. Table
8-21 and encoding the resulting bit configurations as two octal digits.
Table 8-2l.
Inform.ation Restored by RVI Instruction
OXXXXI
The contents of the variant register.
OXXXIX
The settings of the arithm.etic, com.parison, address m.ode, and item.-m.ark trap m.ode indicators. This inform.ation is stored in the six
data bits and the iteITl-m.ark bit of a character
location.
OXXIXX
The contents of the auxiliary indicators register (AIR). Upon returning from. external interrupt m.ode to either internal interrupt or
standard ITlode, the contents of this register
are m.oved autoITlatically to the indicators specified above for V 2 •
OXIXXX
The settings of the indicators associated with the
scientific unit (see Appendix F) and the sector
interrupt Illasks2 (see Appendix G).
01XXXX
The settingsoftheprotect, 1 proceed,l instruction
tiIlleout allow, 2 S Illode, and relocation 2 indicators
and (if the processor is in the external interrupt
Illode) the setting of the internal interrupt (II) Illode
indicator. 1
IThese indicators are included in a Type 1201,1251,2201, or 4201 processor
equipped with the Storage Protect Feature (see Appendix E).
2These indicators are included in a Type 1201, 1251, 2201, or 4201 processor
equipped with Extended MultiprograIllITling and 8-Bit Transfer Feature (see Appendix G).
WORD MARKS
Word ITlarks neither affect nor are affected by this instruction.
8-96
#2-139
SECTION VIII.
INSTRUCTIONS
ADDRESS REGISTERS AFTER OPERATION
SR
AAR
NXT
A
BAR
P
NOTES
1.
Each entry in the righthand column of Table 8-21 is retrieved from a single
character location. Only the number of characters corresponding to the
selected table entries are retrieved by the R VI instruction.
2.
The RVI op code is a "privileged" op code that has special significance when
used with a Type 1201, 1251, 2201, or 4201 processor equipped with the
Storage Protect Feature (see Appendix E).
3.
This instruction is intended for use in the interrupt mode and should not be
issued in the standard mode.
4.
The format in which information is stored by an SVI instruction is
shown in the table on page 8-94. Note that the information contained
in the last character location is not restored by the R VI instruction.
5.
This instruction is a standard feature on all processors but the Types
201 and 201 .. 1, on which it is not available.
6.
The method of coding interrupt service routines is described in Appendix
D, "Interrupt Processing. "
7.
The protect and proceed indicators, when present in the user's system,
are not turned on automatically by the computer but instead must be turned
on by programmed instructions, as follows: (1) a I-bit is set in the bit
position which, when restored by the R VI instruction, indicates the status
of the indicator; and (2) an R VI instruction with a V 5 bit of 1 in the variant
character is executed, thereby turning on the appropriate indicator.
8.
Unless the contents of the variant register are explictly restored by this
instruction, they are not altered by its execution; i. e., the variant character of the R VI instruction is not stored in the variant register.
EXAMPLE
Restore the contents of the variant register and auxiliary indicators register (AIR)
that were previously stored by the SVI instruction example on page 8- 95.
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I
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OPERATION
CODE -
I~\J
OPERANDS
2021
1415
,
,
STORE t 2_..J/J.S
80
6263
~
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I
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LOCATION
i
8-97
#2-139
SECTION VIII.
INSTR UCTIONS
Mel MONITOR CALL I
FORMAT
-
A ADDRESS
OP CODE
FUNCTION
B ADDRESS
The Monitor Call instruction causes the processor to enter the external interrupt
m.ode (if the processor is not already in that m.ode). The following activities are
autom.atically perform.ed:
1.
The EI interrupt source indicators are set to show that the Monitor Call
instruction is the source of interruption, and the processor enters the
external interrupt m.ode;
2.
The settings of the arithm.etic, com.parison, address m.ode, and item.m.ark trap m.ode indicators are stored in the auxiliary indicators register (AIR);
3.
The arithm.etic indicators are cleared;
4.
The contents of the sequence register (SR) and the external interrupt
register (EIR) are interchanged, and the program. branches to the instruction whose op code address was previously stored in EIR;
5.
The processor switches to the three-character, non-trap m.ode.
WORD MARKS
Word m.arks are not affected by this instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
EIR
JI (contents
of EIR)
NXT
AAR
BAR
NOTES
1.
If this instruction is issued in the external interrupt m.ode, the results are
unspecified.
2.
The interrupt source indicators can be stored via an SYI instruction
(see page 8-92). Their stored contents can then be interrogated by
program.m.ed instruction to determ.ine the interrupt source.
3.
This instruction is a standard feature on all proce s s or s but the Type s
201 and 201-1, on which it is not available.
EXAMPLE
Interrupt the central processor and branch to MONTOR, the location of the m.onitor
program.. The address tagged MONTOR, was previously stored in EIR.
8-98
#2-139
SECTION VIII.
INSTR UCTIONS
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1 213 415 6 7 8
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6263
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SCR
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80
MON iOR. ... 6.6.
(
: I
I
OPERATION
CODE
'1415
Me
.~
I
I RNM
I
RESUME NORMAL MODE
I
FORMAT
-- -
OP CODE
o.
b.
C.
A ADDRESS
B ADDRESS
FUNCTION
Format a:
The RNM instruction causes an exit from the program being executed in the
interrupt mode (external or internal) to the program which was interrupted. The
activities performed depend on the type of interrupt mode in which the instruction
is issued.
When the RNM instruction is issued in the external interrupt mode:
1.
The EI mode indicators are turned off;
2.
The arithmetic, comparison, address mode, and item-mark trap mode
indicators are restored to the status specified by the auxiliary indicators
register (AIR);
3.
The A and B addresses of the RNM instruction are stored in the A- and
B-address registers (AAR and BAR), respectively; and
4.
The contents of the sequence register (SR) and the external interrupt register (EIR) are interchanged, and the program branches to the instruction whose op code address was initially stored in EIR when the external
interrupt occurred.
When the RNM instruction is issued in the internal interrupt mode:
1.
The II mode indicator is turned off;
2.
The A and B addresses of the RNM instruction are stored in AAR and
BAR, respectively; and
3.
The contents of SR and the internal interrupt register (IIR) are interchanged, and the program branches to the instruction whose op code addres s was initially stored in IIR when the internal interrupt occurred.
#2-139
8-99
/
/
SECTION VIII.
INSTRUCTIONS
Format b:
This format operates like format a. except that the B address of the RNM instruction is not stored in BAR. The previous contents of BAR are not changed.
Format c:
This format operates like format a. except that no instruction addres ses are stored.
The previous contents of AAR and BAR are not affected by this format.
WORD MARKS
Formats a, b, and c:
Word marks are not affected by this instruction.
ADDRESS REGISTERS AFTER OPERATION
SR
Format a:
NXT
EIR
IIR
AAR
BAR
A
B
address of op
code following
RNM instruction
n/a
NXT
n/a
address of op
code following
RNM instruction
A
B
NXT
address of op
code following
RNM instruction
n/a
A
Bp
RNM ISSUED
IN EXTERNAL
INTERRUPT
MODE
NXT
n/a
address of op
code following
RNM instruction
A
Bp
RNM ISSUED
IN INTERNAL
INTERRUPT
MODE
NXT
address ·of op
code following
RNM instruction
n/a
A
B
NXT
n/a
address of op
code following
RNM instruction
A
Format b:
Format c:
p
p
RNM ISSUED
IN EXTERNAL
INTERRUPT
MODE
RNM ISSUED
IN INTERNAL
INTERRUPT
MODE
p
Bp
RNM ISSUED
IN EXTERNAL
INTERRUPT
MODE
RNM ISSUED
IN INTERNAL
INTERRUPT
MODE
NOTES
1.
The address of the instruction which follows the RNM instruction is
stored in the appropriate interrupt register (EIR or IIR) when the RNM
instruction is executed. This register therefore contains the address
of the first instruction executed in the interrupt routine when the next
interrupt of the same type occurs. This instruction should be an SVI
instruction, which should be the first instruction executed in any
interrupt service routine.
8-100
#2-139
SECTION VIII.
INSTRUCTIONS
2.
The method of coding interrupt service routines is described in
Appendix D, lIInterrupt Processing."
3.
The RNM op code is lIprivileged ll op code which has special significance
when used with a Type 1201, 1251, 2201, or 4201 processor equipped
with the Storage Protect Feature (see Appendix E).
4.
This instruction is intended for use in the interrupt mode and should not
be issued in the standard mode.
EXAMPLE
The simplified coding below shows a convenient method of restoring the starting
address of the external interrupt routine (EXT2) in EIR when the normal program
sequence is resumed.
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OPERATION
CODE
1415
:
RESUME IR,NM
1
EX,. 2-
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6263
80
.145
SVl
i I
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OPERANDS
2021
~ INiE.~RUPT ,ROUT
Ir-\,E
)
la
RESUME.
8-101
#2-139
• MOVE CHARACTERS AND EDIT
8-103
#2-139
SECTION VIII.
INSTRUCTIONS
IMCE I MOVE CHARACTERS AND EDIT II FEATURE 0131
FORMAT
-- -
OP CODE
o.
b.
c.
A ADDRESS
8 ADDRESS
FUNCTION
Format a:
The MCE instruction is used to insert identifying symbols and punctuation and to
suppress unwanted zeros in a data field. The A field of an MCE instruction contains the information to be edited. The B field contains an edit control word which
provides a framework for the edit operation. When an MCE instruction is executed,
the data in the A field is moved to the B field where it is punctuated and formatted
according to the edit control word already stored in that field.
NOTE: An LeA instruction can be used to load the control word into the field
where the edited information will eventually go. For instance, if the edited
information is to be printed, the control word should be loaded into the print
image area and the address of this area should be used as the B address of the
MCE instruction.
Editing is performed according to the following rules:
RULE 1. Any character in the Series 200 character set can be used in the edit
control word. Those characters having special meanings are listed in Table 8-22.
Any other character, if included in the edit control word, remains in the edited
result in the position where written.
,
RULE 2. A word mark in the high-order position of the B field controls the edit
operation.
...
RULE 3. The number of replaceable characters in the edit control word must be
at least as large as the number of characters in the A field.
RULE 4. Data is transferred from the A field character by character, from right
to left. If a zero suppression symbol is not sensed in the edit control word, the
edit operation terminates when the B-field word mark is sensed. A zero suppression symbol causes the edited result field to be scanned from left to right.
During this scan, high-order zeros and commas are automatically replaced by
blanks (unless an asterisk appears immediately to the left of the zero suppression
symbol - see rule 5). Zero suppression is terminated by any of the following:
a.
a decimal digit from 1 through 9,
b.
a decimal point, or
c.
the location that initially contained the zero suppression symbol.
RULE 5. An asterisk immediately to the left of the zero suppression symbol in
the control word causes high-order zeros and commas to be replaced by asterisks
instead of blanks in a zero suppression operation. High-order blanks are also
replaced by asterisks.
8-104
#2-139
SECTION VIII.
INSTRUCTIONS
RULE 6. A dollar sign immediately to the left of the zero suppression symbol in
the control word is replaced with an A-field character and causes the edited result
to be rescanned following the zero suppression operation. During this scan, the
dollar sign is IIfloated" to the left of the high-order significant digit in the edited result.
Table 8-22.
Special Characters in MCE Instruction
b (blank)
Blanks are replaced with A-field characters such
that the rightmost character in the A field replaces the rightmost blank in the edit control word
and all higher-order A-field characters replace
successively higher-order blanks.
o (zero)
This symbol specifies zero suppression. Its 10 ..
cation in the control word is interpreted as the
rightmost limit of zero suppression. It is replaced with an A-field character.
(decimal point)
The decimal point remains in the edited field in
the position where written.
, (comma)
Gommas remain in the edited field where written
unless zero suppression is specified (see rule 4).
Commas in control word positions to the left of
the high-order cl:taracter transferred from the
A field are replaced by blanks.
C
The credit or minus symbol is undisturbed if the
sign in the units position of the A field is negative.
If the sign is positive, the credit (or minus) symbol is blanked out. A credit (or minus) symbol
transferred from the A field is not subject to
sign control.
6
R
, CR (credit)
(minus)
NOTE: 0 is printed
as a minus symbol.
37 8
* (asterisk)
$ (dollar sign)
An octal 37 is replaced by a blank in the edited
field.
The asterisk remains in the edited field in the po sition where written unless it appears immediately
to the left of the zero suppression symbol (see
rule 5).
The dollar sign remains in the edited field in the
position where written unless it appears immediately to the left of the zero suppression symbol
(see rule 6).
Format b:
The data contents of the A field are edited and stored in the field specified by the
contents of the B-address register (BAR) according to the rules outlined above.
Format c:
The data field specified by the contents of the A-address register (AAR) are
edited and stored in the field specified by the contents of BAR according to the
rule s outlined above.
8-105
#2-139
SECTION VIII.
INSTRUCTIONS
WORD MARKS
Formats a , b, and c:
Both the A field and the B field must have defining word marks. The A-field word
mark terminates the transfer of data from the A field. The B-field word mark
terminates the edit operation if no zero suppression symbol is sensed in the edit
control word or if automatic dollar sign insertion is specified in conjunction with
zero suppression. The B-field word mark is erased after terminating the edit.
If zero suppression is specified, a word mark is automatically set in the location
containing the zero suppression symbol. When this word mark is sensed during
the reverse scan associated with the zero suppression operation, it is erased
and, if automatic dollar sign insertion is not called for, the edit operation terminates.
ADDRESS REGISTERS AFTER OPERA TION
Uns pecified
NOTES
I.
The zone bits in the units position of the A field are cleared to zero when
moved to the B field. Therefore the value of the character in the units
position in the A field may change when moved to the B field. For example,
an F in the units position of the A field will appear as a 6 in the result field.
2.
Floating dollar sign insertion and automatic asterisk insertion can not be
performed in the same edit operation.
3.
The contents of the variant register are unspecified following the execution
of this instruction. Therefore, an instruction requiring a variant character
cannot be chained following an MCE instruction.
EXAMPLES 1
Data Field (A Field)
@000099
Control Word (B Field)
® bb, bbO. bb&&O
Re sult of Edit
.99
Example I.
@
Data Field (A Field)
Control Word (B Field)
5454986
@bb&bb&bbb
254 54 986
Result of Edit
Example 2.
Data Field (A Field)
@00456
Control Word (B Field)
®b, bbO. bb&CR~.c
$
Result of Edit
4. 50
~.c
Example 3.
1
The character (37 8 ) is shown as an ampersand (&) in these examples.
is not the only equivalent of 378 as shown in Table B-6.
8-106
However, the ampersand
#2-139
SECTION VIII.
INSTRUCTIONS
Data Field (A Field)
@0897445
Control Word (B Field)
®bbb, b$O. bb
$8,974.45
Result of Edit
Example 4.
Data Field (A Field)
@»10450
Control Word (B Field)
Result of Edit
@>, b~cO. bb
***104.50
Example 5.
8-107
#2-139
.PERIPHERAL DATA TRANSFER
.PERIPHERAL CONTROL AND BRANCH
8-109
#2-139
SECTION VIII.
INSTRUCTIONS
INPUT /OUTPUT CONTROL OPERATIONS
Effective control over data transfers between the central processor and peripheral units
and over the peripheral units themselves is maintained by the use of two basic instructions: Peripheral Data Transfer (PDT), and Peripheral Control and Branch (PCB).
The PDT instruction
is used to initiate data transfer operations and certain other related operations, such as backspace magnetic tape and advance the printer form.
The PCB instruction can perform four distinct functions:
(1) it initiates strictly mechanical
(non-data transfer) operations such as magnetic tape rewinds and card rejections; (2) it causes a
program branch to be performed contingent upon the settings of peripheral condition indicators;
(3) it changes the operational mode of a peripheral control; and (4) it allows a peripheral control
to interrupt (or directs the control not to interrupt) the central processor when data transfer is
completed.
Detailed programming and operating information for Series 200 peripheral devices is provided in separate publications.
The remainder of this section is a summary of the PDT and PCB
instructions, based on the assumption that the user is familiar with the contents of the applicable
documents.
In all applicable cases, the coding summary for a device is followed by a reference
to the specific Honeywell manual or information bulletin where additional information can be found.
SELECTING RWC ASSIGNMENTS FOR USE IN PDT INSTRUCTIONS
As described below, the first control character (C1) in a PDT instruction is referred to as
the "read/write channel assignment." This six-bit character specifies the read/write channel(s)
selected to complete the data path (see also pages 1-16 and 2-13).
When coding a PDT instruction,
the programmer may enter Table 8-24 to select an RWC assignment.
The following discussion
concerns the considerations involved in selecting RWC assignments and the correspondence
between achievable data transfer rates and RWC assignments.
Considerations in Selecting RWC Assignments
At least four factor s must be considered when selecting an RWC assignment.
are:
These factors
(l) the data transfer rate of the device being addressed; (2) the processor being used; (3)
the I/O sector to which the device is attached; and (4) the necessity of being upward compatible.
DEVICE DATA TRANSFER RATE
The first consideration in selecting an RWC assignment is the rated speed at which the device being addressed transfers data to or from main memory.
The one or more RWC's assigned
to an operation must receive memory accesses often enough to keep up with the I/O data transfer
8-110
#2-139
SECTION VIII.
rate of the device.
INSTRUCTIONS
For exatnple, the RWC assigntnent used in a PDT instruction which ad-
dresses a Type 258 Disk Pack Drive must designate a data transfer capacity high enough to keep
pace with the device's 208, OOO-character-per-second transfer rate.
However, due to mechanical tolerances, some devices tnay transfer data at instantaneous
rates higher than their notninat transfer rates.
In a few such cases, the devices require an
RWC asslgntnent having a greater data handling capacity than would be required if the nominal
data transfer rate were maintained.
As an example, a Type 204B-5 tape drive using a density
of 556 bits per inch requires an RWC assignment having a data handling capacity of 167, 000
characters per second, even though the notninal transfer rate for this device is les s than
83, 300 characters per second.
Table 8-23 lists the minitnum RWC capacity requirements for each Series 200 peripheral
device.
Table 8-23. Minimum. RWC Capacity Requirements for Series 200 Peripheral Devices
204A-l Magnetic Tape Unit
83.3 KC
204A- 2 Magnetic Tape Unit
167
KC
204A- 3 Magnetic Tape Unit
167
KC
204B -1, - 2 Magnetic Tape Units
200/556bpi
83.3 KC
204B - 3, -4 Magnetic Tape Units
200/556 bpi
83.3 KC
204B - 5 Magnetic Tape Unit
200 bpi
556 bpi
83.3 KC
167 KC
204B -7 Magnetic Tape Unit
200/556/800 bpi.
83.3 KC
204B-8 Magnetic Tape Unit
200/556 bpi
800 bpi
83.3 KC
167 KC
204B -9 Magnetic Tape Unit
200/556 bpi
800 bpi
1200 bpi
83.3 KC
167 KG
167 KC
204B-11, -12 Magnetic Tape Units
200/556 bpi
83.3 KC
204C-13, -14 Magnetic Tape Units
83.3 KG
206 Printer
167
214-1 Card Punch
83.3 KG
8-111
KC
#2-139
SECTION VIII.
Table 8-23 (cont).
INSTR UCTIONS
Minimum RWC Capacity Requirements for Series 200 Peripheral Devices
214-2 Card Reader/Punch
Read
Punch
1
222 Printers (All Models)
83.3 KC
83.3 KC
167 KC
223 Card Reader
223-2 Card Reader
83.3 KC
83.3 KC
224-1, -2 Card Reader/Punch
Read
Punch
227 Card Reader-Card Punch
Read
Punch
232 MICR Reader-Sorter and Control
83.3 KC
83.3 KC
167 KC
167 KC
83.3 KC
233-2 MICR Control
83.3 KC
209 Paper Tape Reader
83.3 KC
209-2 Paper Tape Reader
83.3 KC
210 Paper Tape Punch
83.3 KC
212 On-Line Adapter
212-1 Central Processor
Adapt,~r
167
KC
19 7
KC
213-4 Time-of-Day Clock
83.3 KC
220-1, -2, -3 Consoles
83.3 KC
234 Calcomp Plotter Control
83.3 KC
235 Optical Journal Reader Control
83.3 KC
237 Bill Feed Printer Control
167
KC
258 Disk Pack Drive
250
KC
259 Disk Pack Drive
250
KC
259A Disk Pack Drive
167
KC
259B Disk Pack Drive
167
KC
261 Di sk File
250
KC
262 Disk File
250
KC
270 Random Access Drum Storage
(All Models)
167
KC
281 Single -Channel Communication
Controls 2 (All Models)
83.3 KC
286-1, -2, -3 Multi-Channel Communication Controls
83.3 KC
286-4, -5 Message-Mode, Multi-C
Communication Controls 3
83.3 KC
287 A UTODIN Communication Control 2
83.3 KC
287-1 USASCII AUTODIN Communication
Control 2
83.3 KC
l When a 222-3, -4, -5, or -6 printer is equipped with the Print Buffer (Feature 036),
the transfer rate must be either 83.3 KC or 167 KC.
2The 281-2F, 287, and 287-1 controls require exclusive assignment of two 83.3 KC
RWC's when operating in full-duplex mode.
3The maximum RWC capacity that can be assigned to a 286-4 or 286-5 is 167 KC.
8-112
#2-139
SEC TION VIII.
INSTRUCTIONS
THE PROCESSOR BEING USED
Each Series 200 processor except the 1201 and 1251 comes with a basic and an expanded I/O
configuration. These I/O configurations include different numbers of RWC's. Clearly, then, the
identity of the processor being used and whether or not it is an expanded configuration will help
to determine what RWC assignments are available for use.
For example, in the basic (3-chan-
nell Type 201-2 processor, eight RWC assignments are available.
Input/output operations pro-
ceeding at rates up to 167,000 characters per second can be handled on individual channels by
designating either of two RWC assignments available for each channel.
Two RWC assignments
are provided for interlocking channels to handle rates of up to 333, 000 and 500, 000 characters
per second, respectively.
RWC assignments:
Adding Feature 016 to a Type 201-2 allows the use of two additional
one to increase I/O f1exi"~ility by permitting a fourth simultaneous I/O opera-
tion, and the other to interlock two channels in such a way as to achieve a 250, 000 -characterper-second transfer rate.
Note that the maximum data transfer rate (all channels) achievable
with the expanded I/O configuration remains 500, 000 characters per second.
As indicated in Section II, Type 4201 processors are equipped with variable-speed read/
write channels.
No more than two RWC's (a primary and the corresponding auxiliary) are ever
made busy by a single RWC assignment.
available for use in other operations.
RWC's not made busy by a high-speed transfer are
For example, in a basic 4201, a 250, OOO-character-per-
second transfer from an I/O device in sector 1 can be handled using RWC assignment 55 8 and
only RWC 3 will be tied up.
The other three sector 1 RWC's will still be available for use in
other operations, e. g., three 83, 300-character-per-second transfers.
The" sector escape" code feature of the Type 4201 (used in both PDT and PCB instructions)
make s variable - speed read/write channels even more attractive.
An escape code allows an
RWC normally restricted to operating in one sector to be used for I/O transfers in another sector.
For example, an escape code can be used to assign RWC 1, normally used only in sector
1, to a data transfer in sector 2.
This facility enables the programmer to transfer RWC's temporarily to a sector performing several low- speed operations from anothe r sector in which one or two operations are using
the sector's entire data handling capacity.
For example, escape codes could be used in a basic
4201 to perform simultaneously the operations indicated in Figure 8-9.
In this example, escape
codes are used to enable RWC' s 1 and l' to operate in sector 2.
8-113
#2-139
SECTION VIII.
1
1
2
2
2
2
2
2
1
2
3
4
5
6
7
8
Figure 8-9.
INSTRUCTIONS
167,000
333,000
83,000'
83,000
83, 000
83, 000
83, 000
83,000
2
3
1
1'
4
4'
5
6
char/sec
char/sec
char/sec
char/sec
char / sec
char / sec
char / sec
char/sec
Example of Operation Utilizing Escape Codes
INPUT /OUTPUT SECTOR TO WHICH DEVICE IS CONNECTED
Each input/output sector in a Series 200 processor has a maximum total data transfer capacity.
For Model 200, 1200, 1250, and 2200 processors, this maximum is 500, 000 characters per
second.
Sector 3 of an expanded 4201 processor can handle up to 333,000 characters per second.
The identity of the I/O sector to which the addressed device is connected also becomes a factor
when selecting RWC assignments for expanded Type 2201 processors and for all 1251 and4201 processors.
In general, the RWC assigned to an operation should be associated with the sector to
which the addressed device is connected.
However, as indicated above, this rule can be circum-
vented to advantage in 4201 processors by the use of escape codes.
UPWARD COMPATIBILITY
Because of the manner in which upward compatibility has been consistently implemented in
Series 200 processors, very little consideration need be given to this factor when selecting RWC
assignment codes.
The one case where such consideration must be given is when assigning a
primary RWC for which there is no corresponding auxiliary channel in the processor being programmed to an operation. faster than 83, 300 characters per second.
An example of such a case
is the assignment of the single channel RWC 1 to a drum read operation (102, 000 characters per
second) to be performed in a basic (3-channel) Model 200 processor.
RWC 1 can handle transfer rates up to 167, 000 characters per second.
In the basic processor,
However, in an expanded
Model 200, RWC' s 1 and l' can handle only 83, 300 characters per second apiece unless they are
interlocked.
Thus, if the attempt were made to run the basic 200 program on an expanded 200,
the RW C 1 alone would not be able to handle the drum's transfer rate.
8-114
#2-139
SECTION VIII.
INSTRUCTIONS
In order to avoid such problems, the following general rule should l?e followed:
The RWC assignment in a PDT instruction addressing a device which operates
between 83, 300 and 167, 000 characters per second should be such that it would
interlock the primary channel and its auxiliary if the program were run in a
proce s sor equipped with both channels; i. e., its high-order digit should be 5 or 7.
Clearly, there is no need to specify the "interlock" assignment if the device runs slower than
83, 300 characters per second.
Rather, in the interest of making more RWC' s available for use
in other operations, it j s often wise in such case s to specify the single -channel as signITlent.
I PDT
IPERIPHERAL DATA TRANSFERI
FORMAT
( I/O CONTROL CHARACTERS)
- - -- - - --
OP CODE
c
CI
C2
C3
Cn
- -- --,
,r-----.,
,... ,rL -______
J
'- _____ J
OP CODE
b.
A ADDRESS
A ADDRESS
CI
CE
C2
I
C3
r---- ....
Cn
r---...,
L___ J"·L ___ J
FUNCTION
ForITlat a:
The PDT instruction causes data to be transferred between a peripheral device and
the ITlain ITleITlory area whose leftITlost location is designated by the A address. Data
transfer is terITlinated according to the data ITlediuITl eITlployed. Input/output control
characters specify the data path through which the transfer is to be accoITlplished, as
indicated in Tables 8-24 and 8-26.
ForITlat b: Data is transferred between a peripheral device and the ITlain ITleITlory area who se
leftITlost location is designated by the A address. Data transfer is terITlinated according to the data ITlediuITl eITlployed. Input/output control characters and an escape
code specify the data path through which the transfer is to be accomplished, as indicated in Tables 8-24, 8-25, and 8-26.
8-115
#2-139
SECTION VIII.
Table 8-24.
INSTRUCTIONS
Description of PDT I/O Control Character Cl
(Read/Write Channel Assignment)
Type 201, 201-1 Processors
Basic
{
167,000
167,000
167,000
1
'3
83,000
83,000
167,000
ith Feature
016
51
52
53
2
1
1'
.!.!
l'
11
15
51
Type 201-2 Processor
Basic
{
ith Feature
016
167,000
167,000
167,000
333,000
500,000
1
2
3
2,~ 2
1, 2, ~
83,300
83,300
167,000
250,000
1
51
52
53
56
54
11
15
51
55
Type 1201 Processor
Same as Type 201-2 with Feature 016.
Type 1251 Processor
Sector 1
Basic
83,300
83,300
167,000
167,000
167,000
250,000
333,000
500,000
1
T'
.,!.,
l'
2
3
T',33
2,35
3
1, 1', 2, ~
11
15
51
52
53
55
56
54
Sector 2
ith Feature
1115
83,300
83,300
167,000
167,000
167,000
250,000
333,000
500,000
4
4'
±,4'
5
"6
4\ 6 4
5,64
4
4,4', 5, ~
31
35
71
72
73
75
76
74
Type 2201 Processor
Basic
With Feature
1115
Same as Type 201-2 with Feature 016.
Sector 1 same as Type 201-2 with Feature 016.
Sector 2 same as Type 1251.
8-116
#2-139
SECTION VIII.
INSTRUCTIONS
Table 8-24 (cont). Description of PDT I/O Control Character Cl
(Read/Write Channel Assignment)
Type 4201 Processor
Basic
Sector 1 same as Type 201-2 with Feature 016.
Sector 2 same as Type 2201 with Feature 1115.
Sector 1
83,300
83,000
83)000
83,000
83, 000
83,000
250,000
167,000
167,000
167,000
250,000
333,000
500,000
1
2
3"
1'
2'
3'
2
I, l'
b
~,
2'
3'
3
3"
3
11
12
13
15
16
17
50
51
52
53
55
56
54
Sector 2
With Feature
1116
6
31
32
33
35
36
37
70
71
72
73
75
76
74
8
9
8'
9'
:[,8'
,2.,9'
9
22
23
26
27
62
63
66
4
83,300
83,000
83,000
83,000
83,000
83,000
250,000
167,000
167,000
167,000
250,000
333,000
500,000
5
6
4'
5'
6'
5
i" 4'
5,5'
6,6'
6"
6"
Sector 3
83,300
83,000
83,000
83, 000
167,000
167,000
333,000
1
2
3
4
Underlined numbers identify the RWC whose corresponding starting and current location
counters (SLC and CLC) are used in the operation.
In proces sors equipped with RWC 1', that channel is also interlocked.
Uses RWC 3 for address storage during data transfer.
.
Uses RWC 6 for address storage durIng data transfer.
Note: RWC 2 cannot be active while RWC 5 is active, nor can RWC 3 be active while
RWC 6 is active.
8-117
#2-139
SECTION VIII.
INSTRUCTIONS
Escape Code (CE)
The escape code is part of format h. of the PDT instruction.
If the second control char ...
acter is one of the escape codes shown in Table 8-25, the read/write channel(s) designated by Cl
is assigned to an I/O operation in the sector indicated by the escape code.
The addressed device
must be connected to this sector.
Table 8-25.
Description of PDT I/O Character CE (Escape Code)
Sector 1
Sector 2
Sector 3
10
12
13
Table 8 .. 26.
C2
Description of PDT I/O Control Character C2 (Peripheral Control Designation)
PERIPHERAL CONTROL DESIGNATION: This six-bit character specifies the logical address of the peripheral control to be used in the data
transfer.
C2
x
'-----Peripheral Control Address Bits
~------Sector
Bits
' - - - - - - - - - Input /Output Bit
Input/Output Bit: This bit specifies the direction of data transfer when
a peripheral control capable of both reading and writing is involved in
the transfer. When such a bidirectional control is used,
o = transfer
data from memory to the peripheral control (output),
1 = transfer data to memory from the peripheral control (input).
Specific communication controls .and the Type 212 On-Line Adapter are
exceptions to this rule (see Table 8-27).
The input/output bit can be either zero or one in the logical address of
unidirectional peripheral control (e. g., a printer). However, if compatibility with the Type 8201 proces sor is desired, 1 and 0 must be
specified,respectively, for input and output devices.
Sector Bits: These bits apply only to the Models 1250, 2200, and 4200 and
specify the sector in which the peripheral control is connected. They are
specified as follows:
Sector 1
Sector 2
Sector 3
Models 1250 and 2200
Model 4200
o0
o0
1 0
1 0
1 1
8-118
#2-139
SECTION
VIn.
INSTRUCTIONS
Table 8-26 (cant). Description of PDT I/O Control Character C2
(Per
ral Control De si
tion)
C2
(cont)
Sector bits must always be zeros in Model 200 and 1200 peripheral addresses.
Peripheral Control Address Bits: These three bits, in conjunction with
the preceding three bits, identify the address of the peripheral control
involved in the operation. It is recommended that the following octal
configurations be used for control character C2 in order to provide uniformity among Series 200 installations:
Peripheral Control
Octal Addre s s 1
Magnetic Tape Control 2
00
40
41
01
02
42
07
47
04
44
Paper Tape Reader or Card Reader 3
Paper Tape Punch or Card Punch 3
Printer
Type 212 On-Line Adapter
Console
Disk Control
(output)
(input)
(output)
(input)
(output)
. ut)
lC2 configurations are made up of (1) the input/output bit and (2) the peripheral control address
bits. In Series 200 systems in which sector designations apply (viz., the Models 1250, 2200,
and 4200), the specification of the sector bits may alter these recommended configurations.
2In Series 200 installations containing both 1 /2-inch and 3/4-inch magnetic tape systems, the
recommended addresses of 00 and 40 should be assigned to the 1 /2-inch tape control.
3In Series 200 installations containing a card reader /punch unit, these recommended addresses
apply. However, if the installation contains a second card reader, the reader portion of the
card reader/punch should be assigned the address 43 8 and the second card reader assigned
the address 41 •
8
Additional Parameters (C3 through Cn)
The specific use of these control characters is dependent upon the type of peripheral device
addressed.
A summary of coding for these characters may be found in Tables 8-27 through 8-33.
PUNCTUATION MARKS
The execution of this instruction neither affects nor is affected by word marks or
item marks. However, record marks may terminate the data transfer, depending
upon the device used and the operation performed (see the specific Honeywell
publications ).
ADDRESS REGISTERS AFTER OPERATION
SR
NXT
AAR
BAR
A
8-119
#2-139
SECTION VIII.
INSTRUCTIONS
NOTES
1.
If either the read/write channel or the peripheral control (specified by
Cl and C2, respectively) is found "busy" during the extraction of a
PDT instruction, the instruction is re -extracted: the contents of SR are
set back to the address of the PDT op code, and the extraction process
begins again. This process, which allows the processor to respond to
interrupt signals that may occur while the PDT instruction is awaiting
the 'availability of a read/write channel or peripheral control, is not
performed in the Type 201 and 201-1 processors; PDT extraction in
these two processors waits until the busy channel or control is available.
2.
The PDT op code is a "privileged" op code when used in a Type 1201,1251,
2201, or 4201 processor equipped with the Storage Protect Feature (see
Appendix E).
3.
Format b. of the PDT instruction is applicable only to Type 4201 processors.
4.
Unspecified central processor activity can occur when an attempt is made
to execute a PDT instruction having a read/write channel assignment (C 1)
of zero. It is therefore imperative that every PDT instruction contain some
legal RWC assignment.
Control character C 1 of a PDT instruction is stored in the variant register.
S.
EXAMPLE
Read a card into the 80-character image area tagged CREAD. Use RWC2 and
assume that the card reader control is assigned to the logical address of octal 41.
Note that the data transfer rate in a card reading operation is less than 83, 300
characters per second.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_' OF_
CARD
NUMBER
+I~
I~ ~
1 213 415 6 7 8
I
1
:
LOCATION
OPERATION
CODE
1415
OPERANDS
2021
PD1
I
80
62 63
I
~RE.AD. \,2.4.1
I
Table 8-27.
Summ.ary of PDT I/O Control Characters
Type 223 Card Reader (Order No. 504) •. Type 214-1 Card Punch (Order No. 451). Type 214-2 Card Reader/Punch (Order No. 432). Type 224
Card Reader/Punch (Order No. 506) or Type 227 Card Reader/Punch (Order No. 564)
xx
xx
See Table
8-28 (page
8-124)
none
none
xx
xx
See Table
8-29 (page
8-124)
none
none
none
See Table
8-30 (page
8-125)
none
none
none
8-120
#2-139
SECTION VIII.
Table 8-27 (cont).
Summary of PDT I/O Control Characters
READ FORWARD
XX
Xl.X
6 D3
(D=tape driatal)
none
T T/
none
SS
Sector address numbered 0 47 (octal)
XX
X
See Table
8-31 (page
8-125)
none
none
none
XX
Xl X
See Table
8-3l (page
8-125)
none
none
none
8-121
#2-139
SECTION VIII.
Table 8-27 (cant).
INSTRUCTIONS
Sum.rn.ary of PDT I/O Control Characters
WRITE INITIAL
XX
X2 X
o0
or
1 0 *
none
none
none
EXTENDED WRITE INITIAL
XX
X2 X
20 or
3 0 *
none
none
none
WRITE
XX
X2 X
o lor
none
none
1 1 *
EXTENDED WRITE
XX
X2 X
2 lor
3 1 *
none
none
none
SEARCH AND WRITE
XX
X2 X
02 or
I 2 *
none
none
none
EXTENDED SEARCH AND
WRITE
XX
X2 X
22 or
32*
none
none
none
I't1
SEARCH AND WRITE NEXT
XX
X2 X
03 or
I 3 *
none
none
none
t:l
EXTENDED SEARCH AND
WRITE NEXT
XX
X2 X
23 or
33*
none
none
none
SEARCH AND READ
XX
Xl X
o2
or
none
none
none
I 2
,~
rJ)
~
I't1
~
S
EXTENDED SEARCH AND
READ
XX
Xl X
22 or
32*
none
none
none
SEARCH AND READ NEXT
XX
Xl X
03 or
I 3
none
none
none
EXTENDED SEARCH AND
READ NEXT
XX
Xl X
23 or
33*
none
none
none
READ INITIAL
XX
Xl X
00 or
I 0 *
none
none
none
EXTENDED READ INITIAL
XX
XIX
20 or
30*
none
none
none
READ
XX
Xl X
oI
or
none
none
none
2 I or
3 I *
none
none
none
*
~ I
EXTENDED READ
XX
Xl X
*
* Reading/writing is verified.
See: Disk Devices and Controls (Order No. 514)
8-122
#2-139
SECTION VIII.
Table 8-27 (cont).
>t
nor '_nv. , . ,
~~T';'·
VTfOT . :
::.:.
Summary of PDT I/O Control Characters
PDT I/Q "''''''''.' ....., ..... rl'of I>."D ~C:TF.R
01
II READ/WRITE
;
02
03'
CONTROL UNIT
CHANNEL
04
G5
ADDITIONAL
PARAMETERS
' ADDITIONAL
PARAMETERS
00
none
none
ADDITIONAL
'CI>."D
~
p4
READ (NO CARRIAGE
RETURN)
XX
xl X
READ (CARRIAGE RETURN)
XX
Xl X
o1
none
none
none
WRITE (NO CARRIAGE
RETURN)
XX
X2 X
00
none
none
none
X
X2 X
o1
none
none
none
ri!
H
0
INSTRUCTIONS
none
00
Z
0
U
WRITE (CARRIAGE RETURN)
Control Panels and Consoles (Models 200/1200/1250/2~00)
~
ri!
E-t
p..
~
<
ri!
Z
:::l
Z
0
Se,
«:
N
ri!U
p..U
:><~
TRANSFER ID character to
Series 200 memory.
XX
XX
4X
(X=unused)
ACCEPT the H-BOO/1BOO instruction, defined in the ID
register. 7
XX
XX
00
none
none
none
ACCEPT the H-BOO/1BOO instruction defined in the ID
register, and cause the H-BOO/
1BOO to branch to U+3 or U+5. 7
XX
XX
04
none
none
none
DO NOT ACCEPT the H-BOO/
1BOO instruction defined in the
ID register; rather, cause
the H-BOO/1BOO program to
branch to U+6 or U+7 (read
or write error). 7
XX
XX
1 U
(U = any value
from 1 - 7, octal)
none
none
none
SET the device busy indicator. 7
XX
XX
none
none
none
Model 212 On-Line Adapter (DSI-274)
:1
IK.I!A.. l!;lVl!;
TRANSMIT
XX
X2 X
none
none
none
none
TRANSFER TIME TO
MEMORY
XX
XX
none
none
none
none
XX
XX
none
none
none
none
E-t
I~
r..u
98
ri!u
~:><
E-t~
'p:;
Uri! TRANSFER DATA
P:;p..
p..<
0E-t
HO
«
P:;p:;
E-tO
Zoo
ri!oo
Uri!
Type 212-1 Central
Adapter
8-123
#2-139
SECTION VIII.
Table 8-27 (cont).
INSTRUCTIONS
Sununary of PDT I/O Control Characters
HH
~g
p:jE-<
::>z
00
""'u
Hp:j
xx
RANSFER DA TA
t
E-t
See: Type 214-2 Card Reader /Punch (Order No. 452)
N
I
p:j
rt'I
N
N
P::I
0
rt'I
N
N
P::I
.,
P::I 0
p:j
P-t
-<
:>t
E-t U
trol unit to:
Read direct transcription code (feature 044)
Offset-stack cards
with cycle-check error
8-131
#2-139
Table 8-34 (cont).
-
Sununary of PCB I/O Control Characters
Offset-stack cards
with illegal punches
XX
XX
22
Generate busy signal
if cycle-check error
XX
XX
23
Generate busy signal
if illegal punch
XX
XX
24
Offset-stack the card
currently at the read
station.
XX
XX
31
Turn the control allow function OFF
XX
XX
7 0
Turn the control allow function ON
XX
XX
7 1
Turn the control interrupt function OFF
XX
XX
7 4
Branch to A address if the control interrupt
function is ON
XX
XX
7 5
+>
$:l0
u
p:t
~
~
.:c:
~
p:t
~
p:t
.:c:
U
N
I
('I")
N
N
('I")
N
N
~
P-t
l>!
(Order No. 504)
:r:
U
Z
::>
P-t
~
.:c:
U
""
~
~
~
.:c:
~
p:t
~
~
.:c:
U
N
I
..
r-4
I
~
N
N
~
P-t
l>!
E-!
Branch to A address if device busy
XX
X
1 0
Branch to A address if echo-check or read
registration errors
XX
X3 X
4 1
Branch to A addre s s if illegal punch
XX
X3 X
4 2
Terminate punch-feed
read operations, operate in Hollerith
mode, and accept all
error cards 4
XX
X3 X
27
Convert to special co
XX
X3 X
26
Operate in direct
transcription mode
Feature 064
XX
X3 X
25
Generate busy signal
if illegal punch
XX
X3 X
24
Generate busy signal
if echo -check or read
re stration errors
XX
X3 X
23
Reject cards with
illegal punches (Fea
ture 065)
XX
X3 X
22
Reject cards with
echo-check or read
registration errors
(Feature 065)
XX
X3 X
21
Branch to A address
if device unavailable.
If available, set control unit to:
8-132
12-139
SECTION VIII.
Table 8-34 (cont).
Summary of PCB I/O Control Characters
:.:
I
...... !>.~
;~ ~~~;ali:rA ~G T;g'it§,):
•. • .• . •:• . • J) .• • • • •
ii . :.:.:. . . . :. IC34>.;'"
.:tut . (
OPERATION
:.:....
....
..
....
-
INSTRUCTIONS
.,
....:
.....<
.......:.:....
.
:..
A'Cn<
'"'
Operate in punch-feed
read mode
XX
X3 X
2 0
Reject card presently
in the punch station
XX
X3 X
3 1
Turn the control allow function OFF
XX
X3 X
7 0
Turn the control allow.function ON
XX
X3 X
7 1
,J.O
Np:j
Turn the control interrupt function OFF
XX
X3 X
7 4
XX
X3 X
7 5
E-lp:j
Branch to A address if the control interrupt
function is ON
Branch to A address if device busy
XX
XX
1 0
Branch to A address if hole-count error
XX
XX
4 1
Branch to A address if illegal punch
XX
XX
4 2
Branch to A address
if device unavailable.
If available, set control unit to:
Terminate punch-feed
read operations (Feature 062), if applicable, operate in
Hollerith mode, and
accept all error cards 4
XX
XX
2 7
0
Read special code
XX
XX
2 6
p:j
Read direct transcription code (Feature 040)
XX
XX
2 5
Reject cards with
hole-count errors
XX
XX
2 1
l'-
!:it
P-t
l>!
Reject cards with
illegal punches
XX
XX
2 2
Generate busy signal
if hole -count error
XX
XX
2 3
Generate busy signal
XX
XX
24
Place previously read
card in middle stacker
(Feature 017)
XX
XX
3 1
Place previously read
card in the read eject
stacker (Feature 017-1)
XX
XX
3 2
~
0
~
O::r::
p:jO
~Z
0::>
P-t
~O
.. p:j
-~
N!:it
!:itO
P-t!!:it
See: Type 224 Card Reader /Punch (Order No. 506)
p:j
!:it
-<
!:it
0
p:j
-<0
N
N
E-l
if illegal punch
8-133
#2-139
SECTION VIII.
Table 8-34 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters
tl:I
~
A
-<~
tl:I
A
Turn the control allow function OFF
XX
XX
7 0
Turn the control allow function ON
XX
XX
7 1
Turn the control Interrupt function OFF
XX
XX
7 4
Branch to A address if the control interrupt
function is ON
XX
XX
7 5
Branch to A address if device busy
XX
XX
1 0
Branch to A address if hole-count error (Feature 061)
XX
XX
4 1
Terminate punch-fee
read operations (Feature 062), if applicable, and punch
Hollerith code 4
XX
XX
2 7
Punch special code
XX
XX
2 6
Punch direct transcription code (Feature 060)
XX
XX
2 5
Reject cards with
illegal punches (Feature 062)
XX
XX
2 2
Reject cards with
hole-count errors
(Feature 061)
XX
XX
2 1
Punch-feed read
operations (Feature
062)
XX
XX
2 0
Place previously
punched card in
middle stacke r
(Feature 017)
XX
XX
3 1
Place previously
punched card in the
punch eject stacker
(Feature 017 -1)
XX
XX
3 2
Turn the control allow function OFF
XX
XX
7 0
Turn the control allow function ON
XX
XX
7 1
tl:I_
-<
U
~
§
r--~
N
N
~
Il!
:>t
f-!
See: T}:]2e 227 Card Reader/Punch (Order No. 564)
Branch to A address
if device unavailable.
If available, set control unit to:
::r:
U
Z
::J
Ai
A
~
<:
U
rN
N
~
Ai
:>t
f-!
8-134
#2-139
SECTION VIne
Table 8-34 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters
~
~ -
<~
o
1'::\'... :':./,.:.. :.,',. :',::"
0
U
f" -
~:r:
0
P::l
Turn the control interrupt function OFF
xx
xx
7 4
~::>
t-f ~
Branch to A addres s if the control interrupt
function is ON
xx
xx
7 5
Branch to A addre s s if device busy
xx
XX
1 0
Branch to A address if parity error
XX
XX
4 0
Rewind the tape (reverse direction)
XX
XX
3 0
Run out the tape (forward direction)
XX
XX
3 2
Turn the control allow function OFF
XX
XX
7 0
Turn the control allow function ON
XX
XX
7 1
Turn the control interrupt function OFF
XX
XX
7 4
Branch to A address if the control interrupt
function is ON
XX
XX
7 5
~z
See:
Type 227 Card Reader/Punch (Order No. 564)
Branch to A addres s
if device unavailable.
If available, set control unit to:
See: Types 209, 209-2, and 210 Paper Tape Equipment (Order No. 507)
~
P::l:r:
~O
;::~
NP::l
P::l~
Branch to A address if device busy
XX
XX
1 0
Branch to A addre s s if tape -low condition
is true
XX
XX
6 0
Turn the control allow function OFF
XX
XX
7 0
Turn the control allow function ON
XX
XX
7 1
Turn the control interrupt function OFF
XX
XX
7 4
Branch to A address if the control interrupt
function is ON
XX
XX
7 5
~<
~t-f
t-f
See: Types 209, 209-2, and 210 Paper Tape Equipment (Order No. 507)
...00::;
o P::l
Nt-f
P::l
~
Z
Branch to A addre s s if device busy
P2 Branch to A addre s s
if print error
XX
xx
1 0
xx
xx
4 0
t-f~
See: Honeywell Series 200 Equipment Operators' Manual (Order No. 040)
8-135
#2-139
SECTION VIII.
Table 8-34 (cont).
See:
INSTRUCTIONS
Summary of PCB I/O Control Characters
(,;
Type 222 Printers (Order No. 562)
Notes: PCB instructions with C3 characters 01, 02, 20, and 30 are not applicable to the basic
222-5 printer. However, the 222-5 ~quipped with Feature 1036 (8-Channel Vertical
Format Tape) can perform all of theloperations listed.
Control characters are the same with or without the presence of the Print Buffer
(Feature 036) in the printer.
Rewind
Xx.
X2 X'
2D
(D=tape drive,
o~
Rewind and release
XX
Xl X
X X
Xl X
Z
7)
2D
(D=tape drive,
0 - 7)
::J
rz1:r:
Branch to A address if read busy
~ U
0 D
(D=tape drive,
t< Branch to A address if the control interrupt
E-i
or 1 X
(X=unused)
function is ON
See: Type 270A Random Access Drum and Control (Order No. 009)
.-f
, f.il Branch to A addre s s if device busy
1 0
XX
o~
~O
til
rilZ
P-to
:>tU
E-i
See: Control Panels and Consoles (Models 200/1200/1250/2200), (Order No. 453)
N
Branch to A address if device busy
X X
X2 X
1 0
f.il~------------------------------~----------~---------+---------+----------------~
2
~ ~
O~R__
e_s_et__t_h_e_i_n_t_e_r_r_u_p_t_f_u_n_c_t_i_on
__________________~r---X--X----+_--X---X--_+--------7--6------~
X2 X
Branch to A address if the interrupt function
X X
7 7
P-t 0 is ON
N
~ ~
H
......
:>tU
E-i
See: Control Panels and Consoles (Models 200/1200/1250/2200), (Order No. 453)
8-138
#2-139
SECTION VIII.
Table 8-34 (cont).
~
INSTRUCTIONS
Summary of PCB I/O Control Characters
Branch to A addres s if device busy
XX
X2 X
1 0
Turn the allow function OFF
XX
X2 X
7 0
Turn the allow function ON8
XX
X2 X
7 1
Turn the data termination interrupt
function OFF
XX
X2 X
7 4
Branch to A address if data termination
interrupt function is ON
XX
X2 X
7 5
Turn the manual interrupt function OFF 9
XX
X2 X
7
Branch to A address if manual interrupt
function is ON9
XX
X2 X
7 7
H
0
tI)
Z
0
l)
('f1
I
0
N
N
~
Pot
~
E-t
6
See: Control Panels and Consoles (Models 200/1200/1250/2200), (Order No. 453)
p:;
~
E-t
Pot
~
Branch to A address if device busy
XX
X3 X
oX
Branch to A address if data transfer is in
progress
XX
X3 X
7X
(X=unused)
Branch to A address if error or incomplete
indicator is set
XX
X3 X
4X
Branch to A address if parity error is
XX
X3 X
5X
(X=unused)
XX
X3 X
6X
(X=unused)
XX
X3 X
or 1 X
(X=unused)
<:
~
Z stored
1-1
H
I
Z
0 Branch to A address if incomplete error is
N
stored
~
N
Place control character C4 in the ID register
Pot if data transfer is not in progress
~
E-t
~
Branch to A address unconditionally, and
clear the ID register
C3:
2 X
(X=unused)
C4:
XX
X3 X
XX
X2 X
octal character to be
placed in
ID register
3X
(X=unused)
'.
See: Model 212 On-Line Adapter (DSI-274)
~
I
Branch to A address
specified device is
busy; otherwise, set
control unit to:
ra', if
~ W8
Cl ~ :>
Seek out the cylinder
(specified by C5 and
C6) in the pack
(specified by C4).
8-139
C3:
2 D (D=device
address, 0-7)
C4:
00
#2-139
SECTION VIII.
Table 8-34 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters
C5 and C6: 0000
to 0143 for
the Type 258,
0000 to 0312
for the Type
259.
Restore the specified
device to cylinder
zero.
XX
Xl X
3D
(D=device
address, 0-7).
Continue with the next
sequential record the
operation (read or
write) being performed with the current record.
XX
Xl X
7D
{D=device
address, 0-7).
Branch to A address if
XX
X2 X
Branch to A address if device busy.
XX
X2 X
Branch to A address
if specified device is
not busy; otherwise,
set control unit to:
~
s::
1 0
C3:
o D (D=device address, 0-7)
C4:
o 0 or
another
valid C3
character
0
2
r./)
r:r.l
U
1-1
:>
r:r.l
t:)
~
r./)
1-1
t:)
Branch to A address if a general exception
condition occurred during the preceding PDT
instruction.
XX
X2 X
5 0
Branch to A address if the
XX
X2 X
6 0
Set control unit to override setting of
FORMAT WRITE PERMIT switch.
XX
X2 X
4 0
Turn control allow function OFF.
XX
X2 X
7 0
Turn control aliow function ON.
XX
X2 X
7 1
Turn drive allow function OFF.
XX
X2 X
7 2
Turn drive allow function ON.
XX
X2 X
7 3
Turn control interrupt function OFF. 7
XX
X2 X
7 4
Branch to A address ,if control interrupt
function is ON.
XX
X2 X
7 5
Turn drive interrupt function OFF.
XX
X2 X
7 6
is set.
8-140
#2-139
SECTION VIII.
Table 8-34 (cont).
...=1....:1
fAO
Zp:;
Zf-I
~5
00
r.tlZ
...:10
Zf-l
(jl-f
......
p:4
~
f-I
Z
I-f
~
I
~
..... Branch to A address if interrupt function
N
~
is ON
A4
~
f-I
See: Type 213-3 Interval Timer and Feature 071 Interval Selector (Order No. 082)
8-141
#2-139
SECTION VIII.
Table 8-34 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters
~
U
o
~H
~U
o-l~
N
~ Branch to A address if device busy
~t:l
xx
xx
1 0
xx
X6 X
o X or
Ili~
~O
~
::;g
H
E-!
Branch to A address if device busy
1 0
Branch to A address if device busy, and
reserve
XX
Branch to A address if reserve action by
this central processor was not successful
XX
X6 X
H~
<~
~E-i
E-i
C3:
2 0
C4:
o0
C3:
2 0
C4:
0 0
C5:
6 1
Ili r-----------------------------------------~--------_+----------_r----------------~
~~
xx
X6 X
Branch to A address if 212-1 is not set for
6 1
data transfer (initiator)
o-l ~ r-----------------------------------------~--------_+----------_r----------------~
'0
X6 X
N CI) Branch to A address if 212-1 is set for
XX
6 4
o-lCl)
N ~ data transfer (responder)
~ Ur_--------------------------------------~--------r_--------_r----------------~
~ ~ Turn the allow function OFF
7 0
U
,<
IliO
xx
E-! Ili r----------------------------------------*---------+----------~----------------~
Turn the allow function ON
XX
Turn the interrupt function OFF
XX
Branch to A address if allow and interrupt
functions are ON
XX
x6x
7 1
7 4
X6 X
7 5
xx
1 0
See: Type 212-1 Central Processor Adapter (Order No. 239)
H Branch to A address if control unit busy.
o
XX
~ r-----------------------------------------~--------_+----------_r----------------~
~E-i Turn the allow function OFF
MZ
N 0
XX
xx
7 0
r-----------------------------------------~--------~----------~----------------~
~U Turn the allow function ON
XX
xx
7 1
E-! E-! Turn the interrupt function OFF
XX
xx
7 4
XX
XX
7 5
Ili~f:il~r_--------------------------------------~--------r_--------_r----------------~
E-!
r_----------------------------------------~--------_r----------~----------------~
S
Ili Branch to A addre s s if interrupt function
is ON
See:
Type 234 Plotter Control (Order No. 561)
8-142
#2-139
SECTION VIII.
Table 8-34 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters
...:l Branch to A address if device busy
XX
XX
1 0
XX
XX
o1
XX
XX
7 0
XX
XX
7 1
XX
XX
7 4
XX
XX
7 5
Branch to A address if control busy
XX
XX
1 0
Select stacker designated;
Branch to A address if:
Stacker 0
XX
XX
2 0
Stacker 1
XX
XX
2 1
Stacker 2
XX
XX
2 2
Stacker 3
XX
XX
2 3
Stacker 4
XX
XX
2 4
Stacker 5
XX
XX
2 5
Stacker 6
XX
XX
2 6
Stacker 7
XX
XX
2 7
Stacker 8
XX
XX
3 0
Stacker 9
XX
XX
3 1
Stacker X
XX
XX
3 2
Stacker Y
XX
XX
3 3
Reject
Stacker
XX
XX
3 7
XX
XX
3 4
XX
XX
3 5
XX
XX
3 6
° Branch to A address if reader is not set
p::j
E-!
...:l Z
<0U
U
I-t
for data transfer or if control is busy
p::j
E-! ril Turn the allow function OFF
~ 0
0<
ril Turn the allow function ON
\.C')
~ p::j
ril ...:l Turn the interrupt function OFF
~ ~
:>-t
p::j
::> Branch to A address if interrupt function
...., is ON
E-!
°
U)
1-
the reader-sorter is not
ready; or
2.
the 10-millisecond stacker
selection period has elapsed;
or
p::j
P:.l
f-i
p::j
0U)
3.
I
p::j
ril
(:)
<
ril
p::j
4.
p::j
U
1-1
~
N
I
5.
('/")
('/")
N
rei
the leading edge of the
document to be sorted has
not passed the reading
station; or
the leading edge ha·s passed
the reading station and a
PDT instruction has not yet
been issued; or
the reader-sorter is performing an automatic rej ect
on the document in question
s:l
cd
N
Start feed. Branch to A address if feed cannot be started due to:
ril
1-
the reader-sorter not being
ready; or
2.
proper restart procedures
not followed
N
('/")
~
:>-t
E-!
Stop feed. Branch to A address if sorterreader is not ready
Set pocket-light control.
address if:
Branch to A
8-143
#2-139
SECTION VIII.
Table 8-34 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters
1.
the reader -sorter is not ready; or
2.
~ pocket-light control PCB is already
in process
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
Operate in normal mode
xx
xx
6 0
Operate in short-document mode
xx
xx
6
Branch to A address if on-us field is
complete
xx
xx
6 2
Branch to A address if last document was
a control document
xx
xx
6 3
Branch to A address if end-of-file
xx
xx
6 4
Advance batch counter one digit. Branch
to A address if the sorter-reader is not
stopped or the batch counter is currently
being advanced.
xx
x
6 5
Turn allow function OFF
xx
x
7 0
Turn allow function ON
xx
Turn interrupt function OFF
xx
x~
xx
Branch to A address if interrupt function
is ON
xx
xx
Branch
to A
address
if:
Amount field error
Proce s s control field error
Account field error
Transit field error
Auxiliary on-us field error
Device error
Pas sed document condition
40'0
4 1
4 2
4 3
44
5 0
5 1
7 1
7 4
7 5
See: Type 233-2 MICR Control (Order No. 464)
8-144
#2-139
SECTION VIII.
• t<;\C.·/.:
Table 8-34 (cont).
..
Sununary of PCB I/O Control Characters
:'>
5
'l\.·\.L./
iii...>
i > \ i i ) ': .......'.; i> ·.·.··..i·.·.·.:·.·. ··.·'.i\·.:.\:
.i.?y/.
:
.. : ( . . :. . .:.. .
......
> •........ .•. .. .
INSTRUCTIONS
'i
. :.··.ii: .
. . . . .' . . . . .
...•::.•..:....
.,:
..:
······<.i;~
'7.
y
:.:... :.....:.... :
> i'. '·".
:.. '::.
.
" - A.
.:•• '.,. c'
i
..
'ljERS
c; 3 tn1;'o1.lghCn
Device busy
XX
X3 X
1 0
Form is moving
XX
X2 X
2 0
Device busy or form is moving
XX
X3X
3 0
~
Print error or read check
XX
X3 X
4 0
~
Validity error
XX
X3X
4 1
X2 X
~
~
E-!
Z
1-1
Branch
to A
address
if:
Pot
r.1~
rilO
~o::
Branch on channel 2 (EOF) of format tape
XX
~E-l
Branch on channel 8 of format tape
XX
X2 X
o1
o2
1-10
1=0 0
Turn on validity check indicator
XX
XIX
2 0
Turn the allow function OFF
XX
X
X
7 0
Turn the allow function ON
XX
X
X
7 1
Turn the interrupt function OFF
XX
X
X
7 4
Branch to A address if read interrupt
function is ON
XX
XIX
7 5
~Z
r('i")
N
ril
Pot
~
E-l
The two operations "Branch to A address if form is moving" and II Turn on
validity check indicator" are both specified with a C3 character of 208' but
are distinguished by the high -order bit of C2.
TYEe 237 Bill Feed Printer Control (Order No. 194)
NOTE:
See:
NOTES:
l.
The high-order bit must be l.
2.
The high -order bit must be
3.
The high-order bit is set to 1 for input operations and to 0 for output operations.
4.
This control character should precede all other control characters that set the
control to perform a certain action. It is the programmer's responsibility to
set the control to the desired mode of operation at the beginning of the run.
5.
As the drum control does not permit reading from one drum file while writing
on another, it is considered busy if either a read or a write operation is in
progress. (The value of the high-order bit in C2 is thus immaterial in this
case. )
6.
The high-order bit is ignored.
7.
The interrupt functions of both the control and the disk device are automatically
turned on when a Ilnot busy" status is reached by the control or the disk device,
respectively.
For program interruption in the 201-0 central processor, the processor must
contain the Program Interrupt Feature (012).
8.
9.
o.
The manual interrupt function is applicable only in those cases where the Type
220-3 is employed with the 201-0 or 201-1 central processpr; C3 control characters 76 and 77 perform no operations with other central processors. In those
cases where the 201-0 or 201-1 is not equipped with the Program Interrupt
Feature (012), the manual interrupt function can still be tested or turned off.
Thus although the interrupt button cannot effect a manual interrupt, the corresponding' function can be tested to set up a programmed interrupt.
8-145
#2-139
SECTION VIII.
Table 8-35.
,
N
.-;'p
INST RUCTIONS
Summary of PCB I/O Control Characters for Type 286
Multi-Channel Communication Control
Branch to A address if device busy. If not busy,
set the 286 to stop scanning and continue the program in sequence
'u
~U . Turn the allow function OFF
N~
XX
XX
1 0
none
XX
XX
7 0
none
riI(\"'l
Turn the allow function ON
XX
XX
7 1
none
:>-t
E-t
Branch to A address if the interrupt was due to
the 286 requesting service
XX
XX
7 5
none
Branch to A address if device busy
XX
XX
1 0
none
Branch to A address if parity error
XX
XX
4 0
none
Branch to A address if the interrupt was due to
the 286 requesting service
XX
XX
7 5
none
Turn the allow function ON
XX
XX
7 1
none
Turn the allow function OFF
XX
XX
7 0
none
Set the 286 to the load/test state
XX
XX
2 5
none
Provide line orientation for load/test operation
XX
XX
4 1
none
p
Turn the load/test state and line orientation OFF
XX
XX
2 4
none
U
U
Turn the interrupt function OFF
XX
XX
7 4
none
Release the RWC(S) assigned to the 286
XX
XX
2 7
none
Set the halt / continue indicator to halt
XX
XX
2 0
none
Set the halt/continue indicator to continue
XX
XX
2 1
none
Turn the parity error indicator and the parity
error interrupt function OFF
XX
XX
2 6
none
Request the address of the next transfer that is
to take place from the line designated by C4, and
branch to the A address
XX
XX
3 6
C4: 00 to 77
Abort the present instruction to the line designated by C4, generate an interrupt, initiate the
next instruction to the sa:me line, and branch to
the A addre s s
XX
XX
3 3
C4: 00 to 77
A bort the present instruction to the line designated be C4, initiate the next instruction to the
same line, and branch to the A address
XX
XX
3 2
C4: 00 to 77
Reset synchronization for the line designated by
C4, and branch to the A address
XX
XX
3 7
C4: 00 to 77
Activate the special strobe line to the 285 adapter
designated by C4, and branch to the A address
XX
XX
3 4
C4: 00 to 77
Deliver to the 286 the information specified by
C5 et seq. for the next instruction to the line
designated by C4, and branch to the A address
XX
XX
3 0
C4: 00 to 77
(See Table 8-36
for C5 et seq.)
Pi.
~
riI
~
0
~,
riI
a
-t
E-t
8-146
#2-139
SECTION VIII.
Table 8-35 (cont).
INSTRUCTIONS
Summary of PCB I/O Control Characters for Type 286
Multi-Channel Communication Control
Deliver to the 286 the information specified by
C5 et seq. for the next instruction to the line
designated by C4; then abort the present instruction to that line, generate an interrupt,
initiate the next instruction to the same line,
and branch to the A address
xx
xx
3 3
C4: 00 to 77
(See Table 8-36
for C5 et seq.)
Deliver to the 286 the information specified by
C5 et seq. for the next instruction to the line
designated by C4, then abort the present instruction to that line, initiate the next instruction to the same line, and branch to the A
address
xx
xx
3 2
C4: 00 to 77
(See Table 8 -36
for C5 et seq.)
Table 8-36.
C5
C6
C7
PCB Control Characters C5 through C15 for Type 286-4, -5
Line Control Instructions
C5
C6
XX
XX
'--v--'
most significant
six bits
C8
C9
C7
'--v--'
middle six bits
XX
'--v--'
least significant
six bits
C8
C9
XX
XX
Bits 6 and 5 specify
mode-of op~ration of
the line:
6
5
0
0
1
1
0
1
0
1
-
Inhibit
Receive
Transmit
Transmit
Repeat
Bit 4 is the Allow
Timer bit
Bit §. is the response bit
o -
no interrupt is
allowed at termination of the instruction.
1 -
an interrupt is
allowed.
Address to be loaded
into RWC counters (SLC
and CLC) prior to data
transfer.
Control characters
which specify line
action; they are loaded
into the next instruction
section of memory.
Bits 4 and 5 are not used
and must be zero.
o -
Timer is not
allowed
1 - Timer is
allowed
8-147
#2-139
SECTION VIII.
Table 8-36 (cont).
C8
C9
(cont)
PCB Control Gharacters C5 through CI5 for Type 286-4, -5
Line Control Instructions
Bits 2. and ~ specify
character parity
3
2
a
a
Bit lis the block parity
bit
a -
no parity
1 generation or
checking is
performed
a
INSTRUCTIONS
I
block parity is
not used
- block parity is
used
a even parity
I
1
1 odd parity
Bit 2 is the command
termination bit
Bit I is the character
. transfer bit
a -
a -
one six-bit
character
transfer per
line character
1 - two six-bit
character
transfers per
line character
I
character recognized is the last
one transferred
- one more data
transfer is made
to or from the CP
after the charac"
ter recognized
and before command termination ..
Bit I defines block parity
check bit
a -
I
CIa
CIa
CII
CII
xx
XX
C12
C13
C12
C13
XX
XX
-
check bit will be
the half add sum
of the parity bit
of the preceding
characters in the
message.
block parity character will have
same parity
generated or
checked as the
data characters.
Eight bits (the loworder two bits of CIa
and all six bits of C II)
contain the fir st rec0gnition character$
Eight bits (the loworder two bits of C 12
and all six bits of C13)
contain the second ~ec
ognition character.
8-148
#2-139
~
SECTION VIII.
Table 8-36 (cont).
C14
C15
INSTRUCTIONS
PCB Control Characters C5 through CI5 for Type 286-4, -5
Line Control Instructions
.
C14
CI5
XX
XX
Table 8-37.
Eight bits (the loworder two bits of C 14
and all six bits of CIS)
contain the SIT character for asynchronous
lines.
Description of PCB I/O Character CE
10
Sector 1
12
Sector 2
13
Sector 3
8-149
. #2-139
APPENDIX
OC TAL NOT A TION
A
Octal notation is a convenient shorthand method of writing pure binary numbers.
In Series
200 programming it is used to represent such binary values as main memory addres ses, variant
characters, I/O control characters, and constants.
If a binary value is divided into groups of three bits, proceeding from right to left, each
group may be replaced by its octal equivalent as indicated in Table A-I.
Table A-I.
Binary-Octal Equivalents
000
o
001
1
010
2
011
3
100
4
101
5
110
6
III
7
Example 1.
Example 2.
The binary value
The binary value
011111000101001110
1010100111010
when divided into three -bit groups
when divided into three -bit groups
011 III 000 101001 110
1010 100 III 010,
has an octal equivalent of
has an octal equivalent of
37051 6
1 2 4 7 2
A-I
#2-139
APPENDIX A.
Table A-2.
OCTAL NOTATION
Decimal-Octal Conversion Table
DECIMAL INCREMENT
o:t:
UJCI
0-
0: 0
O...J
'c
~~
0(')
...JO
ci
Z
UJ
en
<
IrI
...J
C
::IE
(,)
UJ
0
0
1
2
3
'4
5
6
7
000 008
001. 009
002 010
003 011
004 012
005 .013
006 014
007 015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
0.33
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
095
096
097
098
099
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
H*
160 168 176 184 192
161 169 177 185 193
162 170 178 186 194
163 171 179 187 195
164 172 180 188 196
165 173 181 189 197
-i6b-i'r.-i8z--i90-1'9s-
-4 ~
>
r0
~
C5
6
:0
0
fT1
:::j :0
9 -i67-i7s-i8'-ilr-r9~- 7
0000
0200
0400
0600
0800
0
31
62
113
-144
1
32
63
114
145
2
33
64
llS
146
3
34
65
11.6
147
4
35
66
117
150
5
36
67
120
151
6
37
70
121
152
7
40
71
122
153
10
41
72
123
154
11
42
73
124
155
IZ
43
74
125
156
13
44
75
126
157
14
45
76
127
160
15
46
77
130
161
16
47
100
131
162
17
50
101
132
163
20
51
102
133
164
ZI
52
103
134
165
22
53
104
135
166
Z3
54
105
136
167
24
55
106
137
170
25
56
107
140
171
26
57
110
141
172
27
60
III
142
173
30
61
112
143
174
0000
OZOO
0400
0600
0800
1000
1200
1400
1600
1800
175
226
257
310
341
176
227
260
311
342
177
230
261
312
343
200
231
262
313
344
201
232
263
314
345
202
233
264
315
346
203
234
265
316
347
204
235
266
317
350
205
236
267
320
351
206
237
270
321
352
207
240
271
32Z
353
210
241
272
323
354
211
242
273
324
355
212
243
274
3Z5
356
213
244
275
326
357
214
245
276
327
360
215
246
277
330
361
216
247
300
331
362
Z17
Z50
301
332
363
2Z0
251
302
333
364
221
252
303
334
365
2Z2
253
304
335
366
223
254
305
336
367
224
255
306
337
370
225
256
307
340
371
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
372
423
454
505
536
373
424
455
506
537
374
425
456
507
540
375
426
457
510
541
376
427
460
!Hl
542
377
430
461
512
543
400
431
462
513
544
401
432
463
514
545
402
433
464
515
546
403
434
465
516
547
404
435
466
517
550
405
436
467
520
551
406
437
470
521
552
407
440
471
5Z2
553
410
441
472
523
554
411
442
473
524
555
412
443
474
525
556
413
444
475
526
557
414
445
476
527
560
415
446
477
530
561
416
447
500
531
562
.417
450
501
532
563
420
451
502
533
564
421
452
503
534
565
422
453
504
535
566
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
567
620
651
702
733
570
621
652
703
734
571
622
653
704
735
572
623
654
705
736
573
624
655
706
737
574
625
656
707
740
575
626
657
710
741
576
627
660
711
742
577
630
661
712
743
600
631
662
713
744
601
632
663
714
745
602
633
664
715
746
603
634
665
716
747
604
635
666
717
750
605
636
667
720
751
(;06
637
670
721
752
607
640
671
722
753
610
641
672
723
754
611
642
673
724
755
612
643
674
725
756
613
644
675
726
757
614
645
676
727
760
615
646
677
730
761
616
647
700
731
762
617
650
701
732
763
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
764
1015
1046
1077
1130
765
1016
1047
1100
1131
766
1017
1050
1101
1132
767
1020
1051
1102
1133
770
1021
1052
1103
1134
771
1022
1053
1104
1135
772
1023
1054
1105
1136
773
1024
1055
1106
1137
774
1025
1056
1107
1140
775
1026
1057
1110
1141
776
1027
1060
1111
1142
777
1030
1061
1112
1143
1000
1031
1062
1113
1144
1001
1032
1063
1114
1145
1002
1033
1064
1115
1146
1003
1034
1065
1116
1147
1004
1035
1066
1117
1150
1005
1036
1067·
1120
1151
1006
1037
1070
1121
1152
1007
1040
1071
llZ2
1153
1010
1041
1072
1123
1154
1011
1042
1073
1124
1155
1012
1043
1074
1125
1156
1013
1044
1075
1126
1157
1014
1045
1076
1127
1160
4000
4200
4400
4600
4800
5000
5200
5400
5600
5800
1161
1212
1243
1274
1325
1162
1213
1244
1275
1326
1163
1214
1245
1276
1327
1164
1215
1246
1277
1330
1165
1216
1247
1300
1331
1166
1217
1250
1301
1332
1167
1220
1251
1302
1333
1UO
1221
1252
1303
1334
1171
1222
1253
1304
1335
1172
1223
1254
1305
1336
1173
1224
1255
1306
1337
1174
1225
1256
1307
1340
1175
1226
1257
1310
1341
1176
12Z7
1260
1311
1342
1177
1230
1261
1312
1343
1200
1231
1262
1313
1344
1201
1232
1263
1314
1345
1202
1233
1264
1315'
1346
1203
1234
1265
1316
1347
1204
1235
1266
1317
1350
1205
1236
1267
1320
1351
1206
1237
1270
1321
1352
1207
1240
1271
1322
1353
1210
1241
1272
1323
1354
1211
1242
1273
1324
1355
5000
5200
5400
5600
5800
6000
6200
6400
6600
6800
1356
1407
1440
1471
1522
1357
1410
1441
1472
1523
1360
1411
1442
1473
1524
1361
1412
1443
1474
1525
1362
1413
1444
1475
1526
1363
1414
1445
1476
1527
Ij64
1415
1446
1477
1530
1365
1416
1447
1500
1531
1366
1417
1450
1501
1532
1367
1420
1451
1502
1533
1370
1421
1452
1503
1534
1371
1422
1453
1504
1535
1372
1423
1454
1505
1536
1373
14Z4
1455
1506
1537
1374
1425
1456
1507
1540
1375
1426
1457
1510
1541
1376
1427
1460
1511
1542
1377
1430
1461
1512
1543
1400
1431
1462
1513
1544
1401
1432
1463
1514
1545
1402
1433
1464
1515
1546
1403
1434
1465
1516
1547
1404
1435
1466
1517
1550
1405
1436
1467
1520
1551
1406
1437
1470
1521
1552
6000
6200
6400
6600
6800
7000
7200
7400
7600
7800
1553
1604
1635
1666
1717
1554
1605
1636
1667
1720
1555
1606
1637
1670
1721
1556
1601
1640
1671
1722
1557
1610
1641
1672
1723
1560
1611
1642
1673
1724
1561
1612
1643
1674
1725
1562
1613
1644
1675
1726
1563
1614
1645
1676
1727
1564
1615
1646
1677
1730
1565
1616
1647
1:700
1731
1566.
1617
1650
1701
1732
1567
1620
1651
1702
1733
1570
16Z1
1652
1703
1734
1571
1622
1653
1704
1735
1572
1623
1654
1705
1736
1573
1624
1655
1706
1737
1574
16Z5
1656
1707
1740
1575
1626
1657
1710
1741
1576
16Z7
1660
1711
1742
1577
1630
1661
1712
1743
1600
1631
1662
1713
1744
1601
1632
1663
1714
1745
1602
1633
1-664
1715
1746
1603
1634
1665
1716
1747
7000
7200
7400
7600
7800'
8000
8200
8400
8600
8800
1750
2001
2032
2063
2114
1751
2002
2033
2064
2115
1752
2003
Z034
2065
2116
1753
2004
2035
2066
2117
1754
2005
2036
2067
2120
1755
2006
2037
2070
2121
1756
2007
2040
2071
2122
1757
2010
2041
2072
2123
1760
2011
2042
2073
2124
1761 1762
2012 2013
2043 2044
2074 2075
2125_2126
1763
2014
2045
2076
2127
1764
2015
2046
2077
2130
1765
2016
2047
2100
2131
1766
2017
2050
2101
2132
1767
2020
2051
2102
2133
1770
2021
2052
210,3
2134
1771
2022
2053
2104
2135
1772
2023
2054
2105
2136
1773
2024
2055
2106
2137
1774
2025
2056
2107
2140
1775
2026
2057
2110
2141
1776
2027
2060
2111
2142
1777
2030
206i"
2112
2143
2000
2031
2062
2113
2144
8000
8200
8400
8600
8800
9000
9200
9400
9600
9800
2145
2176
2227
2260
2311
2146
2177
2230
2261
2312
2147
Z200
2231
2262
Z313
2150
2201
2232
2263
2314
2151
2202
2233
2264
2315
2152
2203
2234
2265
2316
2153
2204
2235
2266
2317
2154
2205
2236
2267
2320
2155
2206
2237
2270
2321
2156
2207
2240
2271
2322
2157
2210
2241
2272
2323
2160
2211
2242
2273
2324
2161
2212
2243
2274
2325
2162
2213
2244
2275
2326
2163
2214
2245
2276
~327
2164
2215
2246
2277
2330
2165
2216
2247
2300
2331
2166
2217
2250
2301
2332
2167
2220
2251
2302
2333
2170
2221
2252
2303
2334
2171
2222
2253
2304
2335
2172
2223
2254
2305
2336
2173
2224
2255
2306
2337
2174
2225
2256
2307
2340
2175
2226
2257
2310
2341
9000
9200
9400
9600
9800
10,000
10,200
10,400
10,600
10,800
2342
2373
2424
2455
2506
2343
2374
2425
2456
2507
2344
2375
2426
2457
2510
2345
2376
2427
2460
2511
2346
2377
2430
2461
2512
2347
2400
2431
2462
2513
2350
2401
2432
2463
2514
2351
2402
2433
2464
2515
2352 2353
2403 2404
2434 2435
2465 2466
2516'2517
2354
2405
2436
2467
2520
2355
2406
2417
2470
2521
2356
2407
2440
2471
2522
2357
2410
2441
2472
2360
2411
2442
2473
2~Z3 2524
2361
2412
2443
2474
2525
2362
2413
2444
2475
2526
236'3
2414
2445
2476
2527
2364
2415
2446
2477
2530
2365
2416
2447
2500
2531
2366
2417
2450
Z501
2532
2367
2420
2451
2502
2533
2370
2421
2452
2503
2534
2}71
2422
2453
2504
2535
2372
2423
2454
2505
2536
10,000
10,200
10,400
10,600
10,800
11,000
11,200
11,400
11,600
11,800
2537
2570
2621
2652
2703
2540
2571
2622
2653
2704
2541
2572
Z623
Z654
2705
2542
2573
2624
2655
2706
2543
2574
2625
2656
2707
2544
2575
2626
2657
2710
2545
2576
2627
2660
2711
2546
2577
2630
2661
2712
2547
2600
2631
2662
2713
2550
2601
2632
26.63
2714
2551
2602
2633
2664
2'215
2552
2603
2634
2665
2716
2553
2604
2635
2666
2717
2554
2605
2636
2667
2720
2555
2606
2637
2670
2721
2556
2607
2640
2671
2722
2557
2610
2641
2672
2723
2560
2611
2642
2673
2724
2561
2612
2643
2674
2725
2562
2613
2644
2675
2726
2563
2614
2645
2676
2727
2564
2615
2646
2677
2730
2565
2616
2647
2700
2731
2566
2617
2650
2701
2732
2567
2620
265.1
2702
2733
11,000
11,200
11,400
11,600
11,800
12,000
12,200
12,400
12,600
12,800
2734
2765
3016
3047
3100
2735
2766
3017
3050
3101
2736
2767
3020
3051
3102
2737
2770
3021
3052
3103
2740
2771
3022
3053
3104
2741
2772
3023
3054
3105'
2742
2773
3024
3055
3106
2743
2774
3025
3056
3107
2744
2775
3026
3057
3110
2745
2776
3027
3060
3111
2746
2777
3030
3061
3112
2747
3000
3031
3062
3113
2750
3001
3032
3063
3114
2751
3002
3033
3064
3115
2752
3003
3034
3065
3116
2753
3004
3035
3066
3117
2754
3005
3036
3067
3120
2755
3006
3037
3070
3121
2756
3007
3040
3071
3122
2757
3010
3041
3072
3123
2760
3011
3042
3073
3124
2761
3012
3043
3074
3125
2762
3013
3044
3075
3126
2763
3014
3045
3076
3127
2764
3015
3046
3077
3130
12,000
12,200
12,400
12; 600
12,800
13,000
13,200
13,400
13,600
13,800
3131
3162
3213
3244
3275
3132
3163
3214
3245
3276
3133
3164
3215
3246
3277
3134
3165
3216
3247
3300
3135
3166
3217
3250
3301
3136
3167
3220
3251
330Z
3137
3170
3221
3252
3303
3140
3171
3222
3253
3304
3141
3172
3223
3254
3305
3142
3173
3224
3255
3306
3143
3174
3225
3256
3307
3144
3175
3226
3257
3310
3145
3176
3227
3260
3311
3146
3177
3230
3261
3312
3147
3200
3231
3262
3313
3150
320 I
3232
3263
3314
3151
3202
3233
3264
3315
3152
3203
3234
3265
3316
3153
3204
3235
3266
3317
'3154
3205
3236
3267
3320
3155
3206
3237
3270
3321
3156
3207
3240
3271
33Z2
3157
3210
3241
3272
3323
3160
3211
3242
3273
3324
3161
3212
3243
3274
3325
13,000
13,200
13,400
13,600
13,800
14,000
14,200
14,400
14,600
14,800
3326
3357
3410
3441
3472
3327
3360
3411
3442
3473
3330
3361
3412
3443
3474
3331
3362
3413
3444
3475
3332 3333
3363 3364
34143415
3445 3446
3476 3477
3334
3365
3416
3447
3500
3335
3366
3417
3450
3501
3336
3367
3420
3451
3502
3337
3370
3421
3452
3503
3340
3371
342Z
3453
3504
3341
3372
3423
3454
3505
3342
3373
3424
3455
3506
3343
3374
3425
3456
3507
3344
3375
3426
3457
3510
3345
3376
3427
3460
3511
3346
3371
3430
3461
3512
3347
3400
3431
3462
3513
3350
3401
3432
3463
3514
3351
3402
3433
3464
3515
3352
3403
3434
3465
3516
3353
3404
3435
3466
3517
3354
3405
3436
3467
3520
3355
3406
3437
3470
3521
3356
3407
3440
3471
3522
14,000
14,200
14,400
14,600
14,800
15,000
15,200
15,400
15,600
15,800
3523
3554
3605
3636
3667
3524
3555
3606
3637
3670
3525
3556
3607
3640
3671
3526
3557
3610
3641
3672
3527
3560
3611
3642
3673
3531
3562
3613
3644
3675
3532
3563
3614
3645
3676
3533
3564
3615
3646
3677
3534
3565
3616
3647
3700
3535
3566
3617
3650
3701
3536
3567
3620
3651
3702
3537
3570
3621
3652
3703
3540
3571
36Z2
3653
3704
3541
3572
3623
3654
3705
354Z
3573
3624
3655
3706
3543
3574
3625
3656
3707
3544
3575
3626
3657
3710
3545
3576
3627
3660
3711
3546
3577
3630
3661
371Z
3547
3600
3631
3662
3713
3550
36.01
3632
3663
3714
3551
3602
3633
3664
3715
3552
3603
3634
3665
3716
3553
3604
3635
3666
3717
15,000
15,200
15,400
15,600
15,800
16,000
16,200
16,400
3720 3721 3722 3723 3724 3725 3726 3727 3730 3731 373Z 3733 3734 3735 3736 3737 3740 3741 3712 3743 3744 3745 3746 3747 3750
3751 3.752 3753 3754 3755 3756 3757 3760 3761 3762 3763 3764 3765 3766 3767 3770 3771 3772 3773 3774 3775 3776 3777 4(100 4001
4002 4003 4004 4005 4006 4007 4010 4011 4012 4013 4014 4015 4016 4017 4020 4021 4022 4023 4024 4025 4026 4027 4030 4031 4032
16,'000
16,200
16,400
3530
356l'
3612
3643
3674
r-
0
n 0
0
1
2
3
4
0
fT1
£'!
3:
>
ra:J
>
en
fT1
Z
9
HIGH-ORDER OCTAL DIGITS
A-2
#2-139
APPENDIX A.
OCTAL NOTATION
OCTAL-DECIMAL CONVERSION PROCEDURE
Consider the decimal number to be converted as a base and an increment.
Locate the base
(the next lower number which is evenly divisible by 200) in the margin of the lower chart and the
increment in the body of the upper chart.
The intersection of the row and column thus defined
contains the high-order digits of the octal equivalent.
gins of the upper chart opposite the increment.
is 7800 and the increment is 158.
the 7800 row below.
The low-order digit appears in the mar-
For example, to convert 7958 to octal, the base
Locate 158 in the upper chart and read down this column to
The high-order octal result is 1742.
upper chart to obtain the low-order digit of 6.
Then read out to the margin of the
Append (do not add) this digit to 1742 for an octal
equivalent of 17,426.
To convert an octal number to decimal, locate the high-order digits in the body of the
lower chart and the low-order digit in the margin of the upper chart.
Then perform the conv.erse
of the above operation.
A-3
#2-139
APPENDIX
MISCELLANEOUS TABLES
B
Table B-l.
Control Register Designations
CLC7
00
CLCI
01
CLC2
02
CLC3
03
CLC7'
04
CLCl'
05
CLC2'
06
CLC3'
07
SLC7
10
SLCI
11
SLC2
12
SLC3
13
SLC7'
14
SLCl'
15
SLC2'
16
SLC3'
17
CLC8
20
CLC4
21
CLC5
22
CLC6
23
CLC8'
24
CLC4'
25
CLC5'
26
CLC6'
27
SLC8
30
SLC4
31
SLC5
32
SLC6
33
SLC8'
34
B-1
#2-139
APPENDIX B.
Table B-1 (cont).
MISCELLANEOUS TABLES
Control Register Designations
SLC4'
35
SLC5'
36
SLC6'
37
ACO
AC1
AC2
AC3
CSR
64
EIR
66
AAR
67
BAR
70
IIR
76
SR
77
Table B-2.
Extended Move (EXM) Conditions
Type of Move
1.
2.
3.
A-field data bits _
B
A-field word-mark bits - B
A-field item-mark bits---.B
X
X
X
1
X
X
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
1
Direction of Move
1.
2.
right to left
left to right
Termination of Move
1.
2.
3.
4.
automatic after single-character move
A-field word mark
A-field item mark
A-field record mark
B-2
1
0
1
#2-139
APPENDIX B.
Table B-3.
NOTE:
MISCELLANEOUS TABLES
Branch on Condition Test (BCT) SENSE Switch Conditions
00
Unc onditional
01
SENSE Switch 1 On
02
SENSE Switch 2 On
03
SENSE Switche s 1 and 2 On
04
SENSE Switch 3 On
05
SENSE Switche s 1 and 3 On
06
SENSE Switche s 2 and 3 On
07
SENSE Switches 1, 2, and 3 On
10
SENSE Switch 4 On
11
SENSE Switche s 1 and 4 On
12
SENSE Switche s 2 and 4 On
13
SENSE Switche s 1, 2, and 4 On
14
SENSE Switche s 3 and 4 On
15
SENSE Switches 1, 3, and 4 On
16
SENSE Switches 2, 3, and 4 On
17
SENSE Switches 1, 2, 3, and 4 On
20
Unconditional
21
SENSE Switch 5 On
22
SENSE Switch 6 On
23
SENSE Switches 5 and 6 On
24
SENSE Switch 7 On
25
SENSE Switche s 5 and 7 On
26
SENSE Switche s 6 and 7 On
27
SENSE Switches 5, 6, and 7 On
30
SENSE Switch 8 On
31
SENSE Switche s 5 and 8 On
32
SENSE Switches 6 and 8 On
33
SENSE Switche s 5, 6, and 8 On
34
SENSE Switches 7 and 8 On
35
SENSE Switche s 5, 7, and 8 On
36
SENSE Switche s 6, 7, and 8 On
37
SENSE Switche s 5, 6, 7, and 8 On
When testing for a multiple SENSE switch condition, a branch
occurs only if all of the specified conditions are met.
B-3
#2-139
APPENDIX B.
Table B-4.
MISCELLANEOUS TAB LES
Branch on Condition Test (BCT) Indicator Conditions
40
Do not branch
41
B< A (Low Com.pare)
42
B=A (Equal Compare)
43
B!S A (Low or Equal Compare)
44
B > A (High Compare)
45
B#A (Unequal Compare)
46
B
47
Unconditional
50
Overflow
51
Overflow or B
52
Overflow or B=A
53
Overflow or B,:5; A
54
Overflow or B > A
55
Overflow ~ B#-A
56
Overflow or B
57
Unconditional
60
Zero Balance
61
Zero Balance or B A
65
Zero Balance or B#-A
66
Zero Balance or B 2:.A
67
Unconditional
70
Overflow or Zero Balance
71
Overflow or Zero Balance or B < A
72
Overflow or Zero Balance or B=A
73
Overflow or Zero Balance or B
74
Overflow or Zero Balance or B> A
75
Overflow or Zero Balance or B#A
76
Overflow or Zero Balance or B
77
Unconditional
~
A (High or Equal Com.pare)
Space
0
1
2
3
4
5
6
7
8
9
8,2
8,3
8,4
Blank
8,6
8,7
&
o or & R,O or R(1)
A
B
C
D
E
F
G
H
I
0
R,1
R,2
R,3
R,4
R,5
R,6
R,7
R,8
R,9
R,8,2
R,8,3
R,8,4
R,8,5
R,8,6
&
& or 0 R or R,O(1)
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
1.1.
20
010001
0100.10
010011
010100
010101
010110
010 III
011000
011001
011010
011011
011100
011101
011110
21
22
23
24
25
26
27
30
31
32
33
34
35
36
011111
37
MISCELLANEOUS TABLES
Series 200 Character Codes
0
1
2
3
4
5
6
7
8
9
oor -
=
$
Blank
J
K
L
M
N
0
P
Q
R
*
> (2)
<&)
+
- or 0
A
I
B
5
C
T
U
V
W
D
E
F
G
X
H
I
Y
Z
)
%
%
•
? (2)
X,
X,8,4
X,8,5
X,8,6
X or X, 0(1)
8,5
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
0,8,2
0,8,3
0,8,4
0,8,5
0,8,6
110001
110019
110011
110UO
110101110110,
11eHl-1
111000
111001
111010
111011
111100
111101
111110
61
62
63
64
65
66
67
70
71
72
73
74
75
76
0,8,7
111111
77
X,1
X,2
X,3
X,4
X,5
X,6
X,7
X,8
X,9
X,8,2
X~8,3
J
K
L
M
N
0
P
Q
R
#
$
*
II
I: (2)
I/Zor' (l) (3)
<
(2)
I
S
T
U
V
W
X
Y
Z
@
(
CR
0
(2)
¢
(2)
(l)Special Code (for use with H-400/1400 and H-800/ 1800 cards). The second (alternative)
card code is equivalent to the stated central processor code when control character 26
is coded in a c'ard read or punch PCB instruction.
(2)Indicates symbol which will be printed by a printer which has a 63-character drum (Type
222 printers).
(3)The exclamation point replaces the one-half symbol on a type roll' containing the Mark II
character font.
B-7
#2-139
APPENDIX B.
Table B-7.
MISCELLANEOUS TABLES
Binary, Octal, and Decimal Equivalents
Table B-8.
Powers of 2
.'>'
BIN •.. > OCT.
..
DEC. ,.
BIN.
OCT.
DEC.
0
0
0
100000
40
32
1
1
1
100001
41
33
10
2
2
100010
42
34
11
3
3
100011
43
35
100
4
4
100100
44
36
101
5
5
100101
45
37
110
6
6
100110
46
38
III
7
7
100111
47
39
1000
10
8
101000
50
40
1001
11
9
101001
51
41
1010
12
10
101010
52
42
1011
13
11
101011
53
43
1100
14
12
101100
54
44
1101
15
13
101101
55
45
1110
16
14
-tU1110
56
46
1111
17
15
101111
57
47
10000
20
16
110000
60
48
10001
21
17
110001
61
49
10010
22
18
110010
62
50
10011
23
19
110011
63
51
10100
24
20
110100
64
52
10101
25
21
110101
65
53
10110
26
22
110110
66
54
10111
27
23
110111
67
55
11000
30
24
111000
70
56
11001
31
25
111001
71
57
11010
32
26
111010
72
58
11011
33
27
111011
73
59
11100
34
28
111100
74
60
11101
35
29
111101
75
61
11110
36
30
111110
76
62
11111
37
31
111111
77
63
B-8
0
2
2
4
3
8
4
16
5
32
6
64
7
128
8
256
9
512
10
024
11
2 048
12
4 096
13
8 192
14
16 384
15
32 768
16
65 536
17
131 072
18
262 144
19
524 288
20
048 576
21
2 097 152
22
4 194 304
23
8 388 608
24
16 777 216
#2-139
APPENDIX B.
MISCELLANEOUS TABLES
Table B-9.
Move or Scan Variants
MOVE OPERATION CODES
MLC
Move Left Characters
63
MLN
Move Left NUIllerics
61
MLW
Move Left Word Marks
64
MLZ
Move Left Zone s
62
MLCA
Move Left Characters to A-Field Word Mark
23
MLCB
Move Left Characters to B-Field Word Mark
43
MLCS
Move Left Character Single
03
MLCW
Move Left Characters and Word Marks
67
MLNA
Move Left NUIllerics to A-Field Word Mark
21
MLNB
Move Left NUIllerics to B-Field Word Mark
41
MLNS
Move Left NUIlleric Single
01
MLNW
Move Left NUIllerics and Word Marks
65
MLWA
Move Left Word Marks to A-Field Word Mark
24
MLWB
Move Left Word Mark to B-Field Word Mark
44
MLWS
Move Left Word Mark Single
04
MLZA
Move Left Zones to. A-Field Word Mark
22
MLZB
Move Left Zones to B-Field Word Mark
42
MLZS
Move Left Z one Single
02
MLZW
Move Left Zones and Word Marks
66
MLCWA
Move Left Characters and Word Mark to A-Field
Word Mark
27
Move Left Characters and Word Mark to B-Field
Word Mark
47
MLCWS
Move Left Characters and Word Mark Single
07
MLNWA
Move Left NUIllerics and Word Mark to A-Field
Word Mark
25
Move Left NUIllerics and Word Mark to B-Field
Word Mark
45
MLNWS
Move Left Numeric and Word Mark Single
05
MLZWA
Move Left Zones and Word Mark to A-Field
Word Mark
26
Move Left Zones and Word Mark to B-Field
Word Mark
46
MLZWS
Move Left Zones and Word Mark Single
06
MRC
Move Ri
13
MLCWB
MLNWB
MLZWB
Characters
B-9
#2-139
APPENDIX B.
MISCELLANEOUS TABLES
Table B-9 (cont).
Move or Scan Variants
MOVE OPERATION CODES
MRN
Move Right Num.erics
11
MRW
Move Right Word Marks
14
MRZ
Move Right Zones
12
MRCG
Move Right Characters to A-Field Group MarkWord Mark
53
Move Right Characters to A-Field Record Mark or
Group Mark- Word Mark
73
MRCR
Move Right Characters to A-Field Record Mark
33
MRCW
Move Right Characters and Word Mark to A- or BField Word Mark
MRNG
Move Right Num.eric s to A -Field Group Mark-Word Mark
17
51
MRNM
Move Right Numerics to A-Field Record Mark or
Group Mark-Word Mark
71
MRNR
Move Right Numerics to A -Field Record Mark
31
MRNW
Move Right Num.erics and Word Mark to A- or BField Word Mark
15
Move Right Word Marks to A-Field Group MarkWord Mark
54
Move Right Word Marks to A-Field Record Mark or
Group Mark-Word Mark
74
MRWR
Move Right Word Marks to A-Field Record Mark
34
MRZG
Move Right Zones to A-Field Group Mark-Word
Mark
52
Move Right Z ones to A-Field Record Mark or
Group Mark-Word Mark
72
MRZR
Move Right Zones to A-Field Record Mark
32
MRZW
Move Right Zones and Word Mark to A- or B-Field
Word Mark
16
Move Right Characters and Word Marks to A-Field
Group Mark-Word Mark
57
Move Right Characters and Word Marks to A-Field
Record Mark-Group Mark-Word Mark
77
Move Right Characters and Word Marks to A-Field
Record Mark
37
Move Right Numerics and Word Marks to A-Field
Group Mark-Word Mark
55
Move Right Num.erics and Word Marks to A-Field
Record Mark-Group Mark-Word Mark
75
MRCM
MRWG
MRWM
MRZM
MRCWG
MRCWM
MRCWR
MRNWG
MRNWM
B-I0
#2-139
APPENDIX B.
MISCELLANEOUS TABLES
Table B-9 (cont).
MRNWR
MRZWG
MRZWM
MRZWR
Move or Scan Variants
Move Right Numerics and Word Marks to A-Field
Record Mark
35
Move Right Zones and Word Marks to A-Field Group
Mark- Word Mark
56
Move Right Zones and Word Marks to A-Field Record
Mark-Group Mark-Word Mark
76
Move Right Zones and Word Marks to A-Field
Record Mark
36
SCAN OPERATION CODES
SCNL
Scan Left to A- or B-Field Word Mark
60
SCNR
Scan Right to A- or B-Field Word Mark
10
SCNLA
Scan Left to A-Field Word Mark
20
SCNLB
Scan Left to B-Field Word Mark
40
SCNLS
Scan Left Single Position
00
SCNRG
Scan Right to A-Field Group Mark- Word Mark
50
SCNRM
Scan Right to A-Field Record Mark or Group
Mark-Word Mark
70
SCNRR
Scan Right to A-Field Record Mark
30
B-11
#2-139
APPENDIX
INSTRUCTION SUMMARY
c
INSTRUCTIONS FORMATS AND TIMING
Each Series 200 instruction is described in terms of its operation code, formats, and timing
formulas for the Series 200 Models 200/1200/1250/2200 in Table C-l.
In addition, reference
is made in each case to the page where the operations initiated by the instruction are described.
Preliminary timing
formula~
for the Model 4200 are given in Table C-2.
Since the internal
operation of the Model 4200 processor differs from that of the other Series 200 processors in
that data is moved in groups of four characters (a word) rather than singly, the 4200 timing
formulas differ considerably from those of the other processors.
The formulas given in both tables provide execution time in memory cycles.
Equivalent
expressions for symbols used in the tables are as follows:
SYMBOL
MEANING
A
Address of A-operand field.
B
Address of B-operand field.
h
The sum of the values of the multiplier digits which are
less than or equal to five, plus the sum of the elevens
complements of all digits whose values are -greater than
five.
N
N
a
aw
Number of characters in the A-operand field.
Number of words in the A- operand field.
Number of characters in the B-operand field.
Number of words in the B- operand field.
Number of words that the A field occupies in the B field,
whether or not the operands have been modified by an
arithmetic operation.
Number of words in the B- operand field excluding Nb 1.
Number of control characters in the instruction.
N
cn
Number of control characters following control character
3 (C3).
Number of digits in the dividend.
Number 6f character s in the instruction.
C-l
#2-139
APPENDIX C.
INSTRUCTION SUMMARY
SYMBOL
MEANING
Number of words in the item to be translated.
Number of words in the result item.
Number of translation units (6-bit or 12-bit: characters)
to be translated.
N·J
Nun;.ber of character locations bypas s ed to reach the
next sequential op code.
Number of characters moved.
Number of digits in the multiplier.
Number of digits in the quotient (=Ndd-Zld-Na +Zla+l).
Number of characters referenced.
Number of characters scanned.
Number of characters stored.
Number of characters in the A- or B-operand field, whichever is shorter.
N.
Number of words bypassed to reach the next sequential
op code.
N
Number of words stored.
wJ
ws
Number of items in the table or the number of times the
A operand is compared against some portion of the
B operand.
n
The value of the "ith" digit of the quotient.
s
Sum of all multiplier digits.
SUM
Sum of the upwards-rounded values of all multiplier digits
divided by 2.
v
w
Variant character.
W.1
Number of four-character words used to store one more
than the total number of character s in the instruction.
W
Number of words in the multiplier.
mr
Xo
Number of memory words used to store the data involved.
Zero if no second scan (zero suppression); one if the scan
is performed.
Zero if no third scan (dollar-sign insertion); one if the
scan is performed.
Z
Number of characters scanned during zero suppression.
Zla
Z
law
Number of leading zeros in the A-operand field.
Number of words containing leading zeros in the A-operand
field.
Number of leading zeros in the dividend
C-2
#2-139
APPENDIX C.
INSTRUCTION SUMMARY
SYMBOL
Z
Z
Z
Z
Z
mr
Number of zeros in the multiplier.
ta
Number of trailing zeros (i. e., consecutive low- order
zer os) in the A- operand field.
taw
Number of words containing trailing zeros in the A-operand
field.
w
z
Number of words scanned during zero suppression.
Zero if Zla = 0; one if Zla "I- O.
$
Number of character s scanned during dollar- sign insertion.
$
Number of words scanned during dollar- sign insertion.
w
NOTE:
MEANING
The timing formulas presented in Tables C-l, C-2, and C-3 are based
on the use of direct addressing. If address modification is used, the
formulas in Tables C-l and C-3 for the Models 200, 1200, 1250, and 2200
should be modified as follows:
1.
Indirect Addressing - Add one memory cycle for each character
extracted as a result of indirect addressing.
2.
Indexed Addressing - Add three memory cycles for each indexed
address.
Likewise, the use of address modification requires that the formulas
in Tables C-2 and C-3 for the Model 4200 be modified as follows:
1.
Indirect Addressing - Add 1. 16 memory cycles for each indirect
address formed plus one memory cycle for each word extracted
as -a result of indirect addressing.
2.
Indexed Addressing - Add 3. 167 memory cycles if one address is
indexed, 5. 16 memory cycles if both addresses are indexed.
C-3
#2-139
APPENDIX C.
Table C -1.
A
36
Instruction Summary -
Tim.ing Formulas for Models 200, 1200, 1250,
a. A/A,B
Decimal Add
8,6
INSTRUCTION SUMMARY
Duplicates
,
A.
operand. A
operand only if
smaller than B.
a-operand
word mark.
Yes.
8-14
S/A,B
b. S/A
SI
Duplicates
A.
B operand. A
operand only if
smaller than B.
B-operand
word mark.
Yes.
8-16
Binary Add
BA/A, B
b. BA/A
BA/
Duplicates
A.
B operand. A
operand only if
smaller than B.
B-operand
word mark.
Yes.
8-17
Bs/A,B
b. Bs/A
BS
Duplicates
A.
B operand. A
operand only if
smaller than B.
B_operand
word mark.
Yes.
8-19
ZA/A,B
ZA/A
zA/
Duplicates
A.
B operand. A
operand only if
smaller than B.
B_operand
word mark.
Yes.
8-20
ZS/A, B
ZS/A
zsl
Duplicates
A.
B operand. A
operand only if
smaller than B.
B-operand
word mark.
Yes.
8-22
M/A,B
MIA
Preserves
B.
A and B fields.
Both word
marks.
Yes.
8-23
Preserves
B.
A operand
(divisor).
A .. operand
word mark.
Yes.
8-25
b.
37
R or R,03
BA
34
R, 8, 4
BS
35
R,8,5
Binary Subtract
ZA
16
8,6
Zero and Add
Decimal
N.+2+N +2N (no
b
r€comp'fement)4
N;+2+ N w.+ 4Nb 4
A/A
AI
2200~~
(recomp~ment)
o
b.
ZS
M
17
26
8,7
R,6
a.
Zero and Subtract
F
Decimal
b.
See Table C-3.
a.
b.
MI
D
27
R,7
G
Decimal Divide
See Table C .. 3.
a. D/A,B
b. D/A
c. DI
EXT
31
R,9
HA
30
R,8
H
Extract (Logical N +l+3N
i
w
Product)
a. EXT/A,B
b. EXT/A
EXTI
Preserves
B.
Smaller oper..
and.
Word mark
of smaller
operand.
Yes.
8-28
Half Add
(Exclusive Or)
a. HA/A,B
Preserves
B.
Smaller oper ..
and.
Word mark
of smaller
operand.
Yes.
8-29
Preserves
B.
None.
Single ..
character
operation.
Yes.
8-30
preserves
B operand. A
operand only if
smaller than B.
B..operand
word mark.
Yes.
8-32
Bypasses
B.
None.
n/a
No.
8-34
Bypasses
B.
None.
n/a
Yes.
b. HA/A
HAl
SST
32
R, 8, 2
Substitute
C
33
R, 8, 3
Compare
a. SST/A,B,Y
b. SSTI A, B5
SST/A
d. SST I
B.
6
B
65
0,5
V
Branch
(Unconditional)
BCT
65
0,5
V
Branch on
Condition Test
a.
b.
BCT/A, y
BCTI
BCC
54
X,8,4
Branch on
Character
Condition
a.
b.
c.
Bcci A, B, y5
Bccl A, B
BCC/A
Preserves
B.
None.
Singlecharacter
operation.
Yes.
BCE
55
X, 8, 5
Branch if
Character Equal
a.
b.
c.
Preserves
B.
None.
Singlecharacter
operation.
Yes.
d.
BCEI A, B, V 5
BCEI A, B
BCE/A
BCEI
a.
b.
BBEI A, B, Y
BBE/A,B
Preserves
B.
None.
Single ..
character
operation.
Yes.
8-44
a. SW/A,B
b. SW/A
c. swl
Duplicates
None.
n/a
Yes.
8-48
a. S1/A,B
b. S1/A
S1/
Duplicates
None.
n/a
Yes.
8-49
BBE
56
X,8,6
Branch on Bit
Equal
N +Z
B/A
i
N +4
i
N +4
i
7
c. BBE/A
d.
sw
SI
22
20
R,2
R,Oor R3
Set Item Mark
8
8-35
8-39
9
8-42
BBEI
A.
A.
cw
23
R,3
C
Clear Word
Mark
a. CW/A,B
b. CW/A
cwl
Duplicates
A.
Word marks
are cleared.
n/a
Yes.
8-50
CI
21
R,I
A
Clear Item
CI/A,B
b. CI/A
cll
Duplicates
A.
None.
n/a
Yes.
8-51
H
45
X,5
N
Halt
a. HIll
b. H/A
c. H/A,B
d. H/A,B, Y
Preserves
B.
None.
n/a
No.
8-52
NOP
40
Nopl
Bypasses
A and B.
None.
n/a
No.
8-54
MCW
14
Mcw/A,B
MCW/A
MCW
Preserves
B.
Yes.
8-55
No Operation
8,4
b.
C-4
#2-139
APPENDIX C.
Table C-1 (cont).
INSTRUCTION SUMMARY
Instruction Summary -
Timing Formulas for Models 200, 1200, 1250, 2200*
r~~;
Op Code
'~nemol\il'
Card
Code'
'Octal
Key
Punch
. Tuuctlon
Format
Tlml",
1
.(Memory Cy.cleo)
Extraction
PathZ
:[4'" .
,~\~ iJ;,';;;~:' :'i~':'
Required Wor!! ,T'rmilia,~e~., ~n In.tr~ct~~~';
;Xle ••rl.becl.
MIIrk,",,"Byf "";"- ~e,p'~ne~r' '\~:P"~eI
CONTROL INSTRUCTIONS (cont)
LCA
15
Blank
a. LCA/A,B
b. LCA/A
c. LCAI
Space Load Characters N.t ItZN
to A-Field Word
1
a
Mark
24
R,4
D
Store Control
Registers
a. SCR/A, V
b. SCR/A
c. SCR/
LCR
25
R,5
E
Load Control
Registers
a. LCR/A, V
b. LCR/A
LCR/
CAM
42
X,2
K
Change Address- Ni+212
Ing Mode
a. CAM/V
b. CAM/
CSM
43
X,3
L
Change Sequenc- N.+3
ing Mode
1
EXM
10
8
7
7
a. CSM/ ll
b. CSM/A
c. CSM/A, B
d. CSM/A, B, V
a. EXM/ A, B, V
b. EXM/A,B
c. EXM/A
d. EXM/
Extended Move
A operand.
A-operand
word mark.
Yea.
Bypasses
B.
None.
n/a
Yes.
Bypasses
B.
None.
n/a
Yes.
Bypasses
A and B.
None.
n/a
Yes.
Preserves
B.
None.
n/a
Yes.
Preserves
See page 8-67
See page 8-6
Yes.
See page
8-70
A operand.
Word mark
in A operand
or in table.
No.
8-70
B.
7
SCR
12
Preserves
5
8-56
8
8
8
8
8
8-58
8-60
8-62
8-66
8-67
B.
MAT
60
8,5
Move and
Translate
MIT
62
0,2
Move Item and
Translate
a. MIT/A,B,
V ,V ,V
2
3
I
b. MIT/A,B, C. V I
See page
8-74
None.
A_operand
item mark or
word mark in
table.
No.
8-74
LIB
77
0,8,7
Load Index/
Barricade
Register
a. LIB/A
b. LIB/A/B
Preserves
B.
None.
Singlecharacter
operation.
Yes.
8-79
SIB
760,8,6
Store Index!
Barricade
a. 3IB/A
b. SIB/A/B
Preserves
B.
None.
Singlecharacter
operation..
Yes.
8-82
a.
b.
c.
d.
TLU/A,B,V
TLU/A,B
TLU/A
TLU
Preserves
B.
A operand.
A-operand
word mark.
Yes.
8-83
a.
b.
c.
d.
MOS/A, B, Y
MOS/A,B
MOS/A
MOS
Rcg~eter
TLU
57
MOS
13
R,6
8,3
Move or Scan
N +I+3(N ) (14)(Move)
i
m
N +I+3(N ) (1200 Scan)
sc
i
Preserves
B
See page
8-86
See page
8-86
Yes,
8-86
N +2+2(N ) (2200 Scan)
sc
i
INTERRUPT CONTROL INSTR UCTIONS
SVI
46
X,6
o
Store Variant
and Indicators
N.+2+N
1
st
+N,15
J
a. svr/V
Bypasses
A and B.
See page 8-93
See page
8-93
No.
8-92
RVI
67
0,7
X
Restore
Variant and
Indicators
a. RVI/A, V
Restores
A and
bypasses
B.
None.
Word mark
of next
instruction.
No.
8-95
MC
44
X,4
M
Monitor Call
a. MC/
Bypasses
A and B.
None.
Word mark
of next
instruction.
No.
8-98
RNM
41
X, I
a. RNM/A,B
b. RNM/A
c. RNM/
Preserves
B.
None.
n/a
No.
8-99
MCE
74
0,8,4
%
Move
Characters
and Edit
Preserves
B.
A operand and
B operand
(see page
8-106
See page
8-106
No.
8-104
PDT
66
0,6
w
Peripheral
Data
Transfer
Bypasses
B.
None.
Record mark
in memory or
unit record
length.
No.
8-IlS
Resume
Normal Mode
N +3
i
16
EDITING INSTRUCTION
a. MCE/A,B
b. MCE/A
MCE/
7
INPUT/OUTPUT INSTRUCTIONS
MODEL 200:
~i+ I + data transfer
tIme.
MODELS 1200 and 1250
~Ni-N +1) + (N +3)
c
mputfoutput cycres + I
processor cycle + data
transfer time. 17
C-5
#2-139
APPENDIX C.
Table C-l (cont).
PCB
64
0,4
INSTRUCTION SUMMARY
Instruction Summary -
U
ripheral
Control and
Branch
Timing Formulas for Models 200 1200, 1250, 2200*
None.
MODEL 200:
Ni+l {if no branch condition exists)
n/a
8-127
No.
Ni +2 (if a branch occurs)
MODELS 1200 and 1250:
(Ni-N +1) +N input/
c
c
output cycles 17
MODEL 2200:
(Ni-N +1) +2N
c
c
*All information given in this table, other than timing formulas, is applicable to the Model 4200.
F-l for information concerning Scientific Unit instructions.
Timing formulas for the 4200 are presented in Table C-2.
See Table
lExcept where otherwise indicated, add one memory cycle to each of these formulas if the instruction is being executed in a Type 2201 processor.
2The extraction path of the various instructions is defined as follows:
• Preserves B • Duplicates A • Bypasses B -
The previous contents of BAR are used as the B address when the instruction is coded in the format Op Code/A.
The contents of AAR are used as the B address when the instruction is coded in the format Op Code/A.
The contents of BAR are not used in any format.
• ByPasses A and B -
The contents of AAR and BAR are not used in any format.
3 The second (alternate) card code is in effect when control character 26 is coded in a Card Read or Punch PCB instruction.
4Subtract one memory cycle from this formula if the instruction is executed in a Type 1201 or 1251 processor.
5 This instruction can be coded only in formats a. and d. when issued in a Type 201 or 201-1 processor.
6Add two memory cycles to this formula if the instruction is executed in a Type 2201 processor.
7 This instruction can be coded only in format a. when issued in a Type 201 or 201-1 processor.
8 This instruction cannot be chained in the Type 201 or 201-1 processor.
9 This instruction can be chained in the Type 201 or 201-1 processor only if the preceding instruction is also a BCE instruction.
10Subtract one mem.ory cycle from this formula if the instruction is issued in the Type 1201 or 1251 processor in the format Op Code/A, B.
11 This instruction can be coded only in formats a., b., and c. when issued in a Type 201 or 201-1 processor.
12Subtract one memory cycle from this formula if the instruction is executed in a Type 1201 or 1251 processor.
13If the instruction is executed in a Type 2201 processor, do not add the one memory cycle mentioned in footnote 1.
14This formula applies only to the Type 120 I, 1251, and 2201 processors; this instruction is not available with the Model 200 processors.
15Subtract one memory cycle from this formula if the instruction is executed in a Model 200 processor.
16Add two memory cycles to this formula if the instruction is executed in a Type 2201 processor.
is executed in a Type 1201 or 1251 processor.
Subtract one memory cycle from the formula if the instruction
17 The "processor cycle" is the one memory cycle out of every four which is given unconditionally to the processor for internal operations; the three remaining
cycles are termed'
ut/output
s."
'
C-6
#2-139
APPENDIX C.
Table C-2.
INSTRUCTION SUMMARY
Instruction Timings for the Model 4200
Fixed- Point Arithmetic Instructions
A
Decimal Add
No Recomplernent
l
W. +N
+2N +2. 5N +K
b1
1
aw
b2
Recomplement
BC K = 5
AV K = 6.5
WC K = 7
W +N
+2. 5N
+2N +2. 5N +
bl
b2
i
aw
bw
Kl
S
Decimal
Subtract
No Recomplement
Recomplement
W i+Naw +2. 5N
+2Nbl +2. 5N +
bw
b2
Kl
BA
Binary Add
BS
Binary Subtract
ZA
Zero and Add
BC K = 5
AV K = 6.5
WC K= 7.5
Wi + 2 Nb 1+ Nb2 + K
2
Nb 1 value is even
K = 6
ZS
Zero and
Subtract
Nb 1 value is odd
K = 7
S Mode: Add 2 cycles
M
Decimal Multiply
See Table C-3.
D
Decimal Divide
See Table C-3.
Logic Instructions
EXT
Extract
HA
Half Add
Wi +3N
SST
Substitute
W.+7.34
C
Compare
Wi +2N 1 +N +K
b
b2
B
Branch
(unconditional)
W.+4.5
bl
+7
1
1
BC K = 5.5
AV K = 7
WC K = 8
1
C-7
#2-139
APPENDIX C.
Table C-2 (cont).
INSTRUCTION SUMMARY
Instruction Timings for the Model 4200
Logic Instructions (cont)
BCT
Branch on
Condition Te st
W +4.5
i
BCC
Branch on
Character
Condition
W.+6
BCE
Branch on
Character Equal
W.+6
BBE
Branch on
Bit Equal
W.+6
1
1
1
Control Instructions
SW
Set Word Mark
W.+5
SI
Set Item Mark
W.+5
1
1
CW
Clear Word Mark
W.+5
1
CI
Clear Item Mark
W.+5
H
Halt
W.+5
1
1
NOP
No Operation
W.+4
MCW
Move Characters
to Word Mark
W +2N +K2
i
b1
1
Nb 1 value is even
K =6
Nbl value is odd
K =7
LCA
SCR
LCR
CAM
Load Characters
to A-field Word
Mark
Store Control
Registers
Load Control
Registers
Change Addressing Mode
Nb1 value is even
K =5
Nb 1 value is odd
K =6
W.+W+4.33
Non-I/O register
W +W+13
I/O re ister
W.+W+4.33
Non-I/O register
1
1
W·+W+24
W.+4
1
C-B
#2-139
APPENDIX C.
Table C-2 (cont).
INSTRUCTION SUMMARY
Instruction Timings for the Model 4200
Control Instructions (cont)
CSM
Change
Sequencing Mode
EXM
Extended Move
W.+4
1
Nbl value is even K=5
Nbl value is odd K=6
MAT
Move and
Translate
W. +1. 67N. +1. 67N +N +6.5
1
la
ib ic
If A < 9+B then
N. = Number of charla
----acters in the i
to be translated.
N. = Number of chari b
----acters in the
res ult item.
MIT
Move Item and
Translate
W. +1. 67N. +1. 67N. +N +6.5
1
la
ib
ic
If B < 9+A or if the trans
lation is 6-bit to 12-bit
(or 12-bit to 6-bit) then
N. = Number of char1a
----acters in the item
to be translated.
N. = Number of charib
----acters in the
res ult item.
LIB
Load Index/Barricade Register·
Basic storage Erotection
W.+W+4.5
1
Storage Erotection with bas e
relocation
W.f2W+6
1
SIB
Store Index/Bar ...
ricade Register
Basic storage Erotection
W.+W+4
1
Storage Erotection with bas e
relocation
W.+2W+5
1
TLU
Table Lookup
W. +n(N
MOS
Move or Scan
W.+3+(3N
1
1;
aw
)+N
m
bw
+3n+9
+1)
C-9
#2-139
APPENDIX C.
INSTRUCTION SUMMARY
Instruction Timings for the Model 4200
Table C-2 (cont).
Interrupt Control Instructions
MC
Monitor Call
W.+4
SVI
Store Variant and
Indicators
W.+N +N .+8
1
ws wJ
RVI
Restore Variant
and Indicators
W.+7
RNM
Resume Normal
Mode
W.+4.5
1
1
1
Edit Instruction
MCE
Move Characters
and Edit
W.+N
1
aw
+2.3N
bW
+2Z +2$ +6+X +Y
W
woo
C-IO
#2-139
APPENDIX C.
INSTRUCTION SUMMARY
Table C- 3. Timings for Decimal Multiply and Divide, Models 200, 1200, 1250, 2200, and 4200
200
1200
and
N.+S+2N +2Z +SN
-Z
+s(N -Z )+2(N -Z )(N
-Z
)
1
a
ta
mr
m rata
a
ta
mr
mr
2200
N.+8+2N +2Z +SN
-Z
+sum(N -Z )+3(N -Z )(N
-Z
)
1
a
ta
mr
mrata
a
ta
mr
mr
Multiply
4200
200
1200
and
l2S0
W.+2N
1
aw
N. +4+2N
1
a
+
[ 1. INa - Z ta +8. 0
+2.3Z
N mr - Z mr ]
if divisor
(S)(Na -Zta)
+13
=0
N.+17.S+4.SN +IS.5Z +12.SN +lSN (Ndd-N +ZI ) if (N -ZI ) ~
la
1
a
dd
a
a
a
a
a
(N
dd
N.+7+4N
1
N.+7+2N
1
F0
) and divisor
a
a
if(N -ZI ) > (N )
a
a
dd
if divisor = 0
N +9+2Z +SN +3Z +N +ISN -2Z +18. 2S) if (Na -Zla) ~ (N -Z )
i
z
a
1d q
1a
a
dd
1d
2200
and divisor f:. 0
Divide
N
4200
W.+2N
1
aw
+ZI
aw
~1Q +2)(3N
1
aw
+2)+19
i=1
C-ll
#2-139
APPENDIX
INTERRUPT PROCESSING
D
The executioll of main-program instructions by the proces sor can be interrupted by an
external interrupt source and, if the processor is a Type 1201, 1251 or 2201 equipped with the
Storage Protect Feature (see Appendix E) or a Type 4201 equipped with the Extended Multiprogramming and 8-Bit Transfer Feature (s.ee Appendix G), by an internal interrupt source.
EXTERNAL INTERRUPT
An external interrupt signal can be generated by any or all of three sources:
1.
The operator's control panel or console;
2.
The Monitor Call instruction (see page 8-98); or
3.
A peripheral control.
The first two sources interrupt the processor directly: in the case of the control panel
or console, the operator si:mply presses the INTERRUPT button; the Monitor Call instruction
interrupts the processor when it is executed.
However, a peripheral control interrupts program
sequence as directed by the settings of two programmable storage functions contained within the
control, as described on page D-5.
The interrupt signal sets indicators to show the source (whether 1., 2., or 3., above)
and the type (external) of interruption.
These indicators can be stored and then tested by pro-
gra:mmed instruction as described further in this appendix.
The processor acts upon the in-
terrupt signal when the following conditions are present:
1.
The proces sor is in the RUN mode (i. e., the processor is executing,
without :manual intervention, stored-progra:m instructions under
control of SR).
2.
The processor is not in the external interrupt :mode.
3.
An instruction op code is about to be extracted.
4.
A me:mory cycle is allocated to the processor.
It should be noted that condition 3. above does not cause an extensive delay if a Type
201-2,
120~,
2201, or 4201 processor is attempting to extract a Peripheral Data Transfer (PDT)
instruction and the specified read/write channel or peripheral control is "busy." The atte:mpt
to is sue a PDT instruction to a busy read/write channel or peripheral control does not" stall"
the central processor.
Rather, the instruction is "re-extracted": SR is set back to the address
of the PDT op code, so that .condition 3. recurs imm.ediately after the channel or control is found
busy.
D-l
#2-139
APPENDIX D.
INTERRUPT PROCESSING
When the central processor is interrupted, it performs the following functions:
1.
Stores the current status of the arithmetic, comparison, address mode,
and trap mode indicators in the auxiliary indicators register (AIR).
2.
Clears the arithmetic indicators.
3.
Enters the three-character, non-trap mode.
4.
Interchanges the contents of SR and EIR and branches to the instruction
whose op code address was previously stored in EIR.
5.
Enters the external interrupt mode.
The interrupt signal is maintained until one of the following steps is taken:
1.
A PDT instruction is issued to the peripheral control.
2.
The Interrupt function for the peripheral control is turned off.
3.
The central processor is initialized.
INTERNAL INTERRUPT
An internal interrupt signal is generated only by a Type 1201, 1251, or 2201 processor
equipped with the Storage Protect Feature or a Type 4201 processor equipped with the Extended
Multiprogramming and 8-Bit Transfer Feature and is caused by a "violation" of storage protection.
(The nature of storage protect violations -
violation, etc. -
internal interrupt address violation, op code
is described in Appendix E.) Processor indicators are set by the internal
--'7
interrupt signal to show the ~ (e. g., op code violation) and the ~ (internal) of Jnterruption.
These indicators can be stored and then tested by programmed instruction as descriped further
in this appendix.
The processor reacts to the internal interrupt signal when the conditions described on
page D-1 are present (i. e., the processor is in the RUN mode, is not in the external interrupt
mode, is about to extract an op code, and is presently allocated a memory cycle) plus one
additional condition: the processor must not only not be in the external interrupt mode but also
must not be in the internal interrupt mode. Thus, the following levels of interrupt priority exist
in the Type 1201, 1251, 2201, or 4201 processor.
1.
If the processor is in the non-interrupt (standard) mode, normal program
sequence can be interrupted by either an external or an internal source.
2.
If the proces sor is in the internal interrupt mode, program sequence
can be interrupted only by an external interrupt source.
3.
If the processor is in the external interrupt mode, program sequence
be interrupted. 1
~
not
1
Interrupt signals generated by any or all of the three external sources (peripheral control, control panel or console, or Monitor Call instruction) may continue to occur while the processor is
in the external interrupt mode. The priority in which the interrupts are accommodated is determined by the program (i. e., according to the programmer-established sequence of interrupt
source tests).
D-2
#2-139
APPENDIX D.
INTERRUPT PROCESSING
The processor responds to an internal interrupt signal as follows:
1.
The contents of SR and IIR are interchanged, and the program branches
to the instruction whose op code address was previously stored in lIR.
2.
The processor enters the internal interrupt mode.
Note that the status of the arithmetic, comparison, address mode, and trap mode indicators
are not stored in AIR automatically when the processor responds to an internal interrupt signal.
The storing (and subsequent restoring) of the contents of these indicators is the responsibility of
the internal interrupt program.
INTERR UPT PROGRAMMING
Three of the four interrupt control instructions (pages 8-92 through 8-101) perform basic
functions in an interrupt routine:
1.
The Store Variant and Indicators instruction (SVI) stores two types of
information: (a) inforrn.ation which must be preserved for subsequent
return to the interrupted program (e. g., indicator settings, variant
register contents,l etc.); and (b) inforrn.ation required to identify the
interrupt source.
2.
The Restore Variant and Indicators instruction (RVI) restores the pertinent
information stored by the SVI instruction before returning to the interrupted
program.
3.
The Resume Normal Mode instruction (RNM) returns the processor to
continue sequencing in the interrupted program, unless the sector bits
of SR have been modified.
The fourth interrupt control instruction -
Monitor Call (MC) -
causes an external interruption
and, therefore, is not coded in the interrupt routine itself •
. Other instructions are required in the interrupt routine to store and exercise control over
address register contents, as shown in Figures D-I and D-2.
The interrupt routines in these
figures are assumed to be executed in the same sector as the interrupted prograrn.; if not, or if
interrupt processing modifies the sector bits in SR, the appropriate sector bits must be stored
upon entering the routine and restored when exiting.
For proper re-entry to the interrupted prograrn, the sarne set of indicators stored by the
SVI instruction should be restored by the RVI.
Since the RVI instruction prepares the processor
to re-enter the interrupted prograrn, it should be followed irn.rnediately by the RNM instruction.
Note that the A- and B-address register settings at the tirne of the interrupt should also be
restored before re-entering the interrupted prograrn.
The external interrupt coding shown in
Figure D-I exploits the ability to restore the address registers automatically by storing their
INa means for storing the variant register contents is provided in the Type 201 and 201-1.
processors. Therefore, when interrupt prograrnming is used with these processors (optlona1
on Type 201), variant characters rnust not be chained.
D-3
#2-139
APPENDIX D.
INTERRUPT PROCESSING
contents in the address fields of the RNM instruction.
This technique requires that variant bit
V2 of the RVI instruction (see page 8-95) be a zero in order to ensure that the RNM instruction
is executed in the maximum addres s mode of the machine.
In an internal interrupt routine, on
the other hand, the indicators associated with the V 2 must be stored and restored by the SVI/
RVI instructions.
Therefore, since the address mode of executing the RNM instruction may
not be maximum, the address fields of this instruction must not be coded.
Instead, the address
register settings must be stored in memory and restored by means of LCR instructions, as
shown in Figure D-2.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE _ O F _
CARD
NUMBER
I
~ ~
LOCATION
e
I
I
BA,~
CEQ,U
I~EQU
I
I
I
MAX
CE~U
I
I
I
1
I
I
I
, I
IAAR
ALLS
CEQU
,REIS ER'JE STOR AGE FOR \ lH> \ C ~ 'TIO.~ S
EJt\t.R MAX IM..U-,-~ At>DRESS MODE I
IEX\T +4 ... AAR
,EX \I t S ,BAR
SANE AAR
SA.'JE B.AR
SCR
~IC.R
1
I
I.
17
I
:
18
:
I
I
I
t-
I
\
)
I
I I
9
20
4
Ml\~
I
I
B-~t)ORESS RE<71S1ER
~1\'XIMU,t-J) ADD --M.ODE FO,R C .P. IS
I NPICATIORS Sl'O~ED
*nC6~
~1C75
eo
6263
REG\ STE R
~s
i
16
#'-'C7~
ADDRE~S
DeN
I
I
A-
CAM
13
'/
\tt:, C67
f# lC35
lNDiCATORS RESTORED
~E,QU
I
IADMODE 4SEJ
MAXIIUM M;)t>~LSIS,'NG IMODE
1
1
IN D I CAT 0 RS MA~ \ MUM
RES7\OR IRVI
IENl'ER +2ALLR
.RESTORE
,
tXI ;r,
.EX \T ~\TH AAR + BAR R£S1"ORE.D
tRtiM I¢ .. ,¢
E~ iER ,A.N t> s, Q,RE INDICATORS
ENTE.R ISVI
l1\llS
12
14
I
~
ALL R
I
15
OPERANDS
2021
I
: i
I
OPERATION
CODE
1415
I
I
10
~I~
2/3 415 6 7
)0
.1
ROUTINE
}
I
·1
I~
E~TERNAL
I ~JERR.\JPT
.1
IRESTO,R
Figure D-l.
-'-
I
I
B.RAN.CH 10 RES1'O.R. ,Al-tD E~ \T
Sample Coding For External Interrupt Routine
The fir st example (see Figure D-l) show s the initial and final coding to be used in an
external interrupt routine.
It is assumed that the address of the location tagged ENTER was
previously stored in EIR, so that the presence of an external interrupt signal results in the automatic branch to the location tagged ENTER.
It is assumed that the four-character addressing
mode is the maximum addressing mode of the processor for which this routine is written.
NOTE:
If the interrupt routine is not in the maximum addressing mode prior to
branching to the location tagged RESTOR, a Change Addressing Mode
instruction - CAM/MAX - must precede the R VI instruction so that
the complete contents of any necessary control memory locations may
be restored.
D-4
#2-139
APPENDIX D.
INTERRUPT PROCESSING
Figure D-2 shows the initial and final coding written for an internal interrupt routine.
It is assumed that the address of the location tagged STAR T was previously stored in IIR and
that the maximim addressing mode of the processor is the four-character mode.
The initial and concluding instructions in an internal routine are similar to those
in an external interrupt routine, except that the SVI instruction must store the indicators associated with bit V2 and must not store the contents of the auxiliary indicators register (AIR).
All
other pertinent indicators are stored by the SVI instruction and are subsequently restored by the
RVI instruction at the conclusion of the routine.
EASYCODER
CODING FORM
PROBLEM _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ PROGRAMMER _ _ _ _ _ _ DATE _ _ _ _ _ PAGE_OF_
CARD
NUMBER
I
+I~
LOCATION
~ ~
213 415 6 7 8
I
I
I
I
i
I
1
IAAR
I
BA..R,
1
IM~I
I
1
I
I
14
15
16
,.
1
I
"I
17
I
18
:
OC.w
~4C
DI~W
I
:
i
,I
20
I
I
21
i
22
I
23
1
24
I
1
~4C,
~C.R
!RVl
$1A.RT.+2 , \ ND,e,
I~VI
SET MAX,l MUM,' "DDRE 55", N,G M.OO~,
Re,sl'ORE. A(:tt..R
REISTORE BA,R
RE1S10R.EI ALL BUT "IR ANID I NT 1 ~p,.
EX\T
~u;r A\RJ 1
S:TOR~G.E FOR AU. aUT A\ R. ,\ ND,.
ElI:t,ER 1\AX, I MUM, ~O,DRESS \ ,N,G M.ODE
fl:5
t~
SICR
5,CR
SAVEAltAAR
MAX
~
N.D.•-,
SAVE. MR
SAV.E. BA.R
SAVE,a •. 6AR
:\
_1
I
Ii
I
I
I
l ~,\'ERNAL
1
I
l
l~rtE,RQI\P.T, ,ROUl \~E
I
1
I
i
L
i
)
I
1
R. ttJ D,l CATD,R.S
EN,TER.AhlD. STORE AtlL
I NOS.
pew
L
i
BU~ Al
ALL BUT. A\ R AND "~T. .\ MO,\ C~;tO ~S,
,T,EMPO,RARY, Sl'OR"GE. FOR ,AAR
,TEMPoAAR."t 510.R,f\GE FOR ,~R
.4
SAVEA..AAR
SA-VEB. RAR
J
I
ALL
80
6263
,B-AOD.RE.SS ,R-E.G I STf..R.
.MAX IMVN ADD,. MO.D,£' ,F,O,R C,P 1 S 4
ISAV,EA
ISA.V,EB
. START
I
I
L
t:t1CJ~L
":1C33
RNM
I
i
A- ADDRESS. RE G \ ST.E.R
CE.QU
RESTO.R I"",CR
I
_I
ft:1 C6.7,
IN,OS
INOR
;....Jruv..)1~
I
19
C,E,QU
CEOU
L
~1 C.6.0
~1 C.7.3.
10
13
OPERANDS
2021
C,EOU.
C,E.QU
II
12
OPERATION
CODE
1415
Ie
RESTOR
Figure D-2.
B.RA~CH T.O
RES1:QR. ANOE"IKtT
I
I
I
Sample Coding for Internal Interrupt Routine
PERIPHERAL CONTROL INTERRUPT
This description pertains to most Series 200 peripheral controls; exceptions are noted in
the various hardware manuals describing individual peripheral devices.
Generally, a peripheral control's interrupt facility includes two interrelated functions:
the Allow function and the Interrupt function.
Certain controls have more than one set of func-
tions {e. g., two sets for disk controls, but one set for magnetic tape controls}.
When a
peripheral control becomes ready to accept a PDT instruction {i. e., reaches a "not-busy"
D-5
#2-139
~NTERRUPT
APPENDIX D.
PROCESSING
status), it transm.its a signalvto turn on the Interrupt function, but this signal m.ust be com.plem.ented by one from. the Allow function (turned on by a PCB instruction) in order to com.plete the
interrupt signal for transm.ission to the central processor (see Figure D-3). 1 When the Interrupt
function is turned on, the interrupt signal is repeated continuously until the central processor is
interrupted or the signal is turned off.
..
ALLOW
FUNCTION
ON
~I---
CONTROL
STATUS
NOT-BUSY
V~
INTERRUPT
FUNCTION
ON
INTERRUPT
SIGNAL
SERIES 200
CENTRAL
PROCESSOR
PERIPHERAL CONTROL
Figure D-3.
Interrupt Signal Generated by Peripheral Control
The interrupt facility for a peripheral control can be activated or deactivated simply by
turning the Allow function on or off, respectively.
If the Allow function is off at the time the
peripheral control becomes not busy and all error information is stored, the interrupt signal
can be neither completed nor transmitted.
Another method of inhibiting the interrupt facility
is to turn off the Interrupt function; this function will not be turned on again until the control
completes another PDT instruction.
Note that if an interrupt has occurred and the Al\OW function
has then been turned off, the Allow function should not be turned on again until either ~ye Interrupt function has been turned off or a PDT instruction has been initiated by the control;: otherwise, an interrupt occurs immediately.
There are various methods of turning the Allow or Interrupt function on or off.
The Allow
function can be turned on or off by a PCB instruction; similarly, the Interrupt function can be
tested or turned off by a PCB instruction.
Also, when the peripheral control receives a PDT
instruction, its Interrupt function is turned off automatically; at completion of the PDT, a pulse
is sent to turn on the Interrupt function.
In any situation, both functions are turned off by initi-
alizing the central processor.
Specific PC B C 3 characters for individual controls are listed in Tables 8 - 34, through 8 _ 36.
The C3 character in a PCB instruction may be used wither to control or to test the status of a
lThis activity does not apply where there is no Allow function, as in the case of the Manual
Interrupt function in a Type 220-3 Console connected to a Type 201 or 201-1 processor.
D-6
#2-139
APPENDIX D.
per~pheral
control's interrupt facility.
INTERRUPT PROCESSING
The general formats of the C 3 characters relating to in-
terrupt control and test are:
1110xO - Turn off the Allow function
1110xl - Turn on the Allow function.
1111 xO - Turn off the Interrupt function.
llllxl - Branch to A if the Interrupt function is on.
The 2-bit, shown here as x, is normally zero if the control being addressed contains only one
set of Interrupt/Allow functions.
If two sets of functions are present, this bit is set to identify
the particular set being tested or controlled.
A if the device addres s ed is not operable.
All of these C3 characters resurt in a branch to
Table D-l summarizes Interrupt/Allow control and
test operations for most peripheral controls; exceptions are noted in individual device manuals.
More than one control character can be us ed to specify multiple control and/ or test operations in a PCB instruction.
these characters.
However, care must be taken in the use of certain combinations of
For example, it is entirely possible for an interrupt to occur between ex-
tractions of control characters.
In such a case, if control characters for "Branch on Interrupt"
and "Turn Off Interrupt" were specified (in that order), the Interrupt function might be turned
off without being acknowledged.
Table D-l.
Summary of Interrupt/Allow Function Control and Test -Operations
Manual
INITIALIZE Button
Turned off
Turned off
70
Turned off
None
71
Turned on
None
74
None
Turned off
75
None
Branch to A if on
Upon receipt of PDT
None
Turned off
When PDT completed
None
Turned on if Allow on
Program - PCB Control Char.
1
Peripheral Control
lAll of these PCB control characters will result in a branch to A if the device addressed is not operable.
D-7
#2-139
APPENDIX
STORAGE PROTECT FEATURE
E
When the Type 1201/1251 or 2201 processor is equipped with the Storage Protect capability
(Feature 1114 or 1117, respectively), the main m.em.ory can be logically divided into two distinct
areas: a pr otected area and an unprotected (or "open") area.
When storage protection is in
effect, the contents of the protected area are shielded from unintentional interference by any
program. operating in the standard (non-interrupt) m.ode (whether residing in the protected or
unprotected area).
The protected area is specified as follows:
1.
The programmer sets the lower boundary of the area with a Load Index/
Barricade Register (LIB) instruction specifying the num.ber of a 4, 096character m.em.ory bank (see page 8-79). The LIB instruction places this
num.ber in the index/barricade register. The lower boundary of the protected area is the leftmost (lowest) core storage location within this bank.
2.
The upper boundary of the protected area is always the highest location
in m.a in m.em.ory.
The loading of the index/barricade register rnerely sets the low-order boundary of the protected
area.
In order to put storage protection into effect, the following conditions m.ust be present:
1.
The programmer must have turned the protect indicator on by issuing a
Restore Variant and Indicators (RVI) instruction specifying the protect
indicator (s ee page 8-95).
2.
The processor m.ust be in the standard (non-interrupt) m.ode.
INDEX REGISTERS
The Storage Protect Feature provides the user with an
addit~onal
15 index registers (Yl
through YI5), which are located in the leftm.ost 60 locations of the 4, 096-character bank specified by the current contents of the index/barricade register.
Thus, these index registers are
relocated whenever the contents of the index/barricade register are altered by an LIB instruction.
These 15 registers are usable whenever the index/barricade register is loaded with a
proper bank num.ber and are not dependent upon whether storage protection is in effect or not.
Instructions whose address portions are indexed by these registers m.ust be assembled and executed in the four-character addressing mode.
The high-order bit of the five-bit address
m.odifier in a four-character address distinguishes index registers Xl through XIS from Yl
through Y15 (see page 4-14).
CENTRAL PROCESSOR MODES
As previously noted, the central processor can operate in anyone of three modes:
1.
The standard m.ode,
E-l
#2-139
APPENDIX E.
STORAGE PROTECT FEATURE
2.
The external interrupt mode (see Appendix D), or
3.
The internal interrupt mode.
Internal Interrupt
When storage protection is in effect (i. e., the protect indicator is on and the processor is
operating in the standard mode), 'Certain operations are defined as violations of that protection.
These violations are discussed below.
A violation causes a violation indicator to be set which,
in turn, causes an internal interrupt to occur at the next opportunity.
The "next opportunity"
means that moment when all of the following conditions are present:
1.
The processor is in the RUN mode (i. e., automatically executing storedprogram instructions under the control of the sequence register),
2.
The processor is about to extract an op code,
3.
A memory cycle is allocated to the processor,
4.
The processor is in the standard mode (i. e., not in external or internal
interrupt mode), and
5.
No peripheral or control panel interrupt signal is being received.
When an internal interrupt occurs, the contents of the sequence register and the internal
interrupt register are interchanged and the central processor enters the internal interrupt mode.
The status of the processor indicators are not stored automatically; therefore, the programmer
must perform this function with a Store Variant and Indicators (SVI) instruction.
The SVI in-
struction also clears the violation indicator so that an internal interrupt will not occur when a
return is made to the standard mode.
While in the internal interrupt mode, any external interrupt
will cause the processor to switch to the external interrupt mode.
If an external interrupt occurs while the processor is in the internal interrupt mode, the
I-bit of the character stored by V5 of the SVI instruction indicates the condition.
If it is desired
to revert to the standard rather than the internal interrupt mode after servicing the external
interrupt, this bit should be changed to 0 before executing the RVI instruction.
Note that three basic differences exist between the external interrupt mode and the internal
interrupt mode:
1.
A unique control memory location, the internal interrupt register (IIR),
contains the address of the subroutine which services the internal interrupt,
2.
The proce.ssor is subject to being interrupted by an external interrupt while
still in the internal interrupt mode, but the reverse is not true,
3.
No processor indicators are stored or altered (the address mode is not
changed) upon entering the internal interrupt mode.
E-2
#2-139
APPENDIX E.
STORAGE PROTECT FEATURE
VIOLATIONS OF STORAGE PROTECTION
The following operations, which constitute violations of storage protection, fallinto two
general categorie s: addre s s violations and op code violations.
1.
An attempt to transfer information internally (i. e., not via a PDT instruction) to memory locations within the protected area. This includes any
attempt to modify index registers Yl through Y15. Howeve~r, no violation
occurs when information is transferred internally from the.protected area
or when the contents of the index registers are used in add~ess modification. An internal transfer violation is detected when all of the following
conditions are present:
a.
The bank and sector bits in the A- or B-address register following instruction extraction are equal to or greater than the corresponding bits stored in the index/barricade register,
b.
The protected location is addre s sed as a re suIt location,
c.
The protect indicator is on,
d.
The program in control is operating in the standard mode, and
e.
The instruction is not a PDT.
The above conditions are checked as. the instruction is being executed. If
all of these conditions are met, the internal interrupt address violation
indicator is set, and the instruction proceeds to normal completion except
that no information is transferred into memory (i. e., the write cycle is
inhibited). The next opportunity for the internal interrupt to occur is at the
extraction of the next op code. After the internal interrupt mode is entered,
the internal interrupt register contains the address of the op code following
the instruction which caused the violation, and the A- and B-address registers continue to increment or decrement, as appropriate.
2.
An attempt to extract a PDT instruction (input £!. output) whose effective A
address references a protected memory location. Since the PDT instruction
is one of the operations normally prohibited when storage protection is in
effect (see 4., below), the proceed indicator (see page E- 5) must be set in
. order for the instruction to be extracted beyond the op code. Assuming that
the proceed indicator is set, the starting addres s of the PDT operation is
examined for address violation. Once it is determined that the effective A
address references a protected address, no operation is performed (i. e.,
the specified read/write channel is not tested and the specified peripheral
control is not addressed), the internal interrupt address violation indicator
is set, the sequence register is advanced to the next op code, and an internal
interrupt occurs.
Note that a PDT instruction is checked for possible violation during the extraction phase, while a nonperipheral instruction is checked during its execution phase (see 1., above). If a PDT instruction passes this test during
extraction, it is free to be executed and the reby cause data to be transferred. If the information being transferred extends into the protected area,
no address violation is detected. To insure that this will not occur, the
user must set a record mark immediately prior to the protected area. 1
As mentioned previously, storage protection (and the checking functions related to it) are in effect only when the processor is operating in the standard
1
If communication devices are being used, two consecutive locations should contain record marks.
E-3
#2-139
APPENDIX E.
STORAGE PROTECT FEATURE
mode. However, violations of the protected area by PDT instructions executed in either of the two interrupt modes can be detected if the proceed
indicator is set on (see page E-5).
3.
An attempt to read from a main memory location whose address is greater
than the main memory capacity actually present in the machine but within
the addressing capacity of the memory address register. 1 Such an addressing attempt results in a parity error which normally causes the machine to
halt. If storage protection is in effect and a parity error occurs, a check is
made to determine whether the error occurred above the lower boundary of
the protected area. If so, the storage protect hardware assumes that outof-range addressing has been attempted, 2 no halt occurs, nor is data
transferred; instead, the internal interrupt address violation indicator is
set, instruction execution is prematurely terminated, and an internal interrupt occurs.
An attempt to reference an address greater than the addressing capacity of
the memory address register results in a memory wraparound.
4.
An attempt to execute a privileged op code. A privileged op code is one
which is (a) not defined for the Series 200; (b) not recognized on the particular processor; (c) .an instruction format violation in any floating-point
instruction; or (d) prohibited when storage protection is in effect. The
privileged op codes in category (d) are:
a.
H (Halt)
b.
LCR (Load Control Registers)
c.
PDT (Peripheral Data Transfer)
d.
PCB (Peripheral Control and Branch)
e.
SVI (Store Variant and Indicators)
f.
RVI (Restore Variant and Indicators)
g.
RNM (Resume Normal Mode)
h.
LIB (Load Index/Barricade Register)
The above op codes are "privileged" in the sense they are allowed to be executed in either of the interrupt modes but are prohibited in the standard
mode while storage protection is in effect (one exception to this is discussed
under "Proceed Indicator" below). Such op codes are categorized by the
fact that they could possibly alter the monitor's knowledge of the status of
the system or cause some action which is intolerable under certain conditions (e. g., a halt during transfer of data from a communications device).
Since an undefined op code or one which is not installed on the user's processor would normally cause a halt due to a program check, such usage has
the same effect as that of a privileged op code.
1
2
For example, an MAR with 15 active bits can address up to 32, 768 locations; an MAR with 16
active bits can address up to 65,536 locations. A 49, 152-character memory would require 16
active bits, thus making it possible to store an address which is beyond the actual memory size.
.
The final responsibility for checking whether the parity check actually indicates out-of-range
addressing rests with the programmer.
E-4
#2-139
APPENDIX E.
STORAGE PROTECT FEATURE
NOTE: Op code "00" is defined as an Internal Interrupt Call, and falls within
the category of privileged op codes.
If a privileged op code is extracted when storage protection is in effect,
the op code violation indicator is turned on, the sequence register is set
back to the location of the op code, the operation is terminated, and an
internal interrupt occurs. Once the internal interrupt mode is entered,
the programmer has two choices: (1) if he wishes to execute the privileged
instruction, he must set the proceed indicator (see below) and issue a
Resume Normal Mode (RNM) cOITlmand; 1 (2) if he wishes to bypass the
privileged instruction, he must set the internal interrupt register to the
location of the next sequential op code and issue a Resume Normal Mode
instruction. 2
PROCEED INDICA TOR
The proceed indicator can be turned on by the Restore Variant and Indicator s (RVI) instruction.
Turning this indicator on permits the execution of one privileged instruction in the
standard mode without op code checking or item-mark trapping being performed.
is turned off following the extraction of any op code in the standard mode.
The indicator
It can also be turned
off in either of the interrupt mode s by a Store Variant and Indicators (SVI) instruction.
The proceed indicator can also be used to force the checking of the A address of a PDT
instruction executed in either the internal or external interrupt mode.
Thus, turning on this
indicator prior to the extraction of a PDT instruction in a nonstandard (interrupt) mode results
in the same address violation check as though it were extracted in the standard mode with
storage protection in effect (see 2., page E-3).
If the effective A address is found to reference
a protected area, the actions described below are performed.
1.
2.
When the violation occurs in the internal interrupt mode:
a.
The internal interrupt address violation indicator is set.
b.
Further extraction of the instruction is not performed and the sequence register is set to the location of the next sequential op code.
c.
An internal interrupt does not occur since the processor is already
in the internal interrupt mode. Instead, the condition of the internal
interrupt address violation indicator must be tested by the programmer after he has stored the status of the indicator via an SVI instruction. The SVI instruction also clear s the indicator so that it will not
cause an internal interrupt to occur when the standard mode is
entered later.
When the violation occurs in the external interrupt mode:
a.
1
2
The external interrupt address violation indicator is set.
The instruction will still not be executed if it involves an a¢l.dress violation.
.
If the internal interrupt register (which is currently set at the location of the privileged op code)
is not advanced to the next op code, the return to normal mode results in the privileged op code
again being extracted, thus causing an endless loop.
E-5
#2-139
APPENDIX E.
STORAGE PROT'ECT FEATURE
b.
Further extraction of the instruction is not performed and the sequence
register is set to the location of the next sequential op code.
c.
An internal interrupt does not occur since
the external interrupt mode. Instead, the
interrupt address violation indicator must
mer according to the method described in
E-6
this is impossible while in
condition of the external
be tested by the program1. c., above.
#2-139
APPENDIX
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200, AND 4200
F
The scientific unit (Featur,e 1100A for the Type 1201, 1251, and 2201 processors, Feature
1101 for the Type 4201) provides a repertoire of 1.2 floating-point instructions, a binary m.antissa
shift instruction, and a binary integer m.ultiply instruction. 1 This appendix is a program.m.er's
working sum.m.ary of both features, which are functionally identical;2 additional inform.ation can
be found in the hardware bulletin Scientific Unit for Models 1200/1250/2200, Feature 1100 (Order
No. 126)'.
Before referring to this appendix, the program.mer should becom.e fam.iliar with the
detailed functional and program.m.ing inform.ation contained in the hardware bulletin.
DATA FORMAT
The fixed-length floating-point word contains a 36-bit binary m.antissa and 12-bit binary
.
.
±616
exponent and is capable of expressing num.bers in the approxim.ate range ±10
CHARACTER
BIT
A-7
A-G
A-5
A-4
A-3
A-2
A-I
A
DDDDDDDD
B A 84 2 I
BIB
I
BIB
I
BIB
I
B
I
'~--------------------------~v~--------------------------J/ '~------~v~------~/
MANTISSA
EXPONENT
In control m.em.ory, a floating-point word m.ay occupy any of the four floating-point accum.ulators.
instructions.
The accum.ulators are addressed as octal digits 0, 1, 2, and 3 in the floating-point
Each accum.ulator com.prises three specific 18-bit control m.em.ory registers.
Only the low-order 12 bits of the rightm.ost register are used to express the exponent.
(In the
Type 4201 processor each accum.ulator com.prises the low-order 18 bits in each of three specific
19-bit control m.em.ory registers. )
BIT
19
18
,
I
I
18
18
/
V
MANTISSA
12
,
/
V
EXPONENT
FLOATING-POINT REGISTERS
The four addresssable floating-point accum.ulators have the control m.em.ory addresses
as shown on page F-2.
1 None of thes e instructions are interpreted by Easycoder As sem.bler A, B, or C.
2 A m.inor exception to this identity is described in connection with the Floating Divide instruction.
F-l
#2-139
APPENDIX
F~
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200, AND 4200
o
43
47
53
57
1
2
3
41
45
51
55
42
46
52
56
NOTE: In program instructions, the floating-point accumulators may be addressed only via the octal digits 0, 1, 2, and 3 in the floating-point
instructions. The instructions LCR and SCR must not be used to address these accumulators. At the control panel, the operator may
address these locations with the addresses in'the above table.
A normal zero, i. e., a floating-point word of 48 zeros, is stored in the "pseudo accumulator" for use as a floating-point operand.
The pseudo accumulator, which is addressed
by octal digit 7, may be used only as the source of a normal zero and not as the destination of
a floating-point result.
The low-order result register (LOR) in the scientific unit may contain a low-order sum,
difference, or product, or may contain the remainder of
NOTE:
a division
operation.
Floating-point instructions do not disturb the contents of the
variant register.
FLOATING-POINT INDICATORS
Exponent
Overflow:
Activated when a base-2 exponent exceeds +2047. The correct mantissa and an
exponent which is 4096 less than the correct exponent are delivered. If an exponent is less than -2048, a normal zero is delivered automatically.
Divide
Check:
Activated when a divisor is equal to zero. This indicator causes termination
of a division operation without accumulator alteration.
Multiply
Overflow:
Activated when the product of a Binary Integer Multiply instruction exceeds 24
bits in length. The low-order' 24 bits are delivered.
AUTOMATIC FORMATTING IN ARITHMETIC OPERATIONS
Prenormalization:
Mantissa of divisor (and dividend with Feature 1101) is normalized (left-shifted)
with adjusted exponent.
Equalization:
Mantissa of operand with smaller exponent is right-shifted until exponents are
equal.
Postnoxmalization:
Mantissa of result is normalized with adjusted exponent.
SYMBOLOGY
A:
A address of the instruction.
B:
B address of the instruction.
X:
Floating-point accumulator addressed in the high-order three bits of an instruction variant (usually the source of an operand).
F-2
#2-139
APPENDIX F.
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200,AND 4200
Y:
Floating-point accumulator addressed in the low-order three bits of
an instruction variant (usually the destination of a result).
(A):
Floating-point word contained in the main memory field from location A through location A -7.
(X) or (Y):
Floating-point word contained in accumulator X or Y.
LOR:
Low-order result register.
(LOR):
Floating-point word contained in LOR.
Ap:
Previous setting of A-address register.
Bp:
Previous setting of B-address register.
D:
One if there is a two-bit overflow into LOR; otherwise zero.
JI:
Address of next instruction if branch occurs.
NXT:
Next sequential instruction.
Nn :
Number of bit positions shifted for automatic formatting.
N 1:
Number of binary ones in a multiplier.
Ns
Number of shifts.
[ ] :
"smallest integer greater than"
W:
Number of memory words used to store the data involved.
X-:
In the first variant of an instruction, only the high-order three bits
specifying accumulator X are significant.
- Y:
In the first variant of an instruction, only the low-order three bits
specifying accumulator Yare significant.
SP:
Single -preci sion.
DP:
Double-precision.
SR:
Sequence register.
Ni:
Number of characters in an instruction.
Wi:
Number of words in an instruction.
TIMING NOTES
All timings shown are based on the use of direct addressing.
Three memory cycles should
be added for each indexed address and one memory cycle should be added for each character
extracted as a result of indirect addressing.
NOTES:
Floating-point instructions do not disturb the contents of the
variant register.
F-3
#2-139
APPENDIX F.
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200, AND 4200
Table F-l.
Sum.m.ary of Scientific Instructions
STORE FLOATING ACCUMULATOR
Memory to
accumulator
FMA/A, X-, 00
or
TAM/A,X-
07
Accumulator to
accumulator
FAA/XY,OO
or
TAA/XY
06
(X) is stored in A through A -7.
(X) is unaltered.
AAR: A-S
BAR: B
(X) is loaded into Y.
malization occurs
No nor-
AAR: A
BAR: BP
Ni+ll
W/7
Ni+l2
P
W i +4·5
P
LOAD FLOATING ACCUMULA TOR
Memory to
accumulator
FMA/A, -Y, 02
or
TMA/A, -Y
07
(A) is loaded into Y.
malization occurs.
No nor-
AAR: A-S
BAR: Bp
Accumulator to
accumulator
FAA/XY,02
or
TAA/XY
06
(X) is loaded into Y.
malization occurs.
No nor-
AAR: Ap
BAR: Bp
Ni+ll
WitS
Ni+l2
Wi+4·5
STORE LOW -ORDER RESULT
Memory to
accumulator
FMA/A, 00, 07
or
TLM/A
07
Accumulator to
accumulator
FAA/-y,07
or
TLA/-Y
06
(LOR) is stored in A through
No normalization
occurs.
A-7.
No nor-
(LOR) is stored in Y.
malization occurs.
AAR: A-S
BAR: B p
Ni+lO
WitS
Ni+ll
W i +4
AAR: A
BAR: B P
P
LOAD LOW -ORDER RESULT
Memory to
accumulator
FMA/A, 00, 01
or
TML/A
07
(A) is loaded into LOR.
normalization occurs.
No
AAR: A-S
BAR: Bp
Accumulator to
accumulator
FAA/X-,Ol
06
(X) is loaded into LOR.
normalization occurs.
No
AAR: Ap
BAR: Bp
Memory to
accumulator
FMA/A, XY, 10
or
AMA/A,XY
07
(A) is added to (X) and the sum
is stored in Y.
Indicator: Exponent overflow.
Formatting: Equalization,
postnormalization.
AAR: A-S
BAR: Bp
LOR: Low-order result
of operation. Sign
bit = O. Exponent =
high-order exponent
minuS 35.
Accumulator to
accumulator
FAA/XY,lO
or
AAA/XY
06
(X) is added to (Y) and the sum
is stored in Y.
Indicator: Exponent overflow.
Formatting: Equalization,
postnormalization.
AAR: A
BAR: BP
LOR: L~w.-order result
of operation. Sign
bit = O. Exponent =
high-order exponent
minus 35.
07
Twos complement of (A) is
added to (X) and the result is
stored in Y.
Indicator: Exponent overflow.
Formatting: Equalization,
postnormalization.
AAR: A-S
BAR: Bp
LOR: Low-order result
of operation. Sign
bit = O. Exponent =
high-order exponent
minus 35.
06
Twos complement of (Y) is added to (X) and the result is
stored in Y.
Indicator: Exponent overflow.
Formatting: Equalization,
po stnormalization.
AAR: A
BAR: B P
LOR: L~w-order result of
operation. Sign bit =
O. Exponent = highorder exponent minus
35.
07
(X) is multiplied by (A). The
high-order product is stored
in Y; the low-order product is
stored in LOR.
Indicator: Exponent overflow.
Formatting: Postnormalization.
Ni+lO
Wi+ 9
Ni+10
W i +4
Ni +13+ [Nn /4]
W i +lHN,/6
10+ [Nn /6]
10+ [Nn /4]
W i +8+Nn /6
Ni +13+ [Nn /6]
Ni+13+ [Nn /4]
W i +l3+Nn /6
lO+[Nn /6 ]
10+[Nn /4 ]
W i +S+Nn /6
N i +l3+
[Nn /6 ]
FLOA TING SUBTRACT
Memory to
accumulator
FMA/A, XY,ll
or
SMA/A,XY
Accumulator to
accumulator
FAA/XY,ll
or
SAA/XY
FLOATING MULTIPLY
Memory to
accumulator
Accumulator to
accumulator
FMA/A,XY,l3
or
MAM/A,XY
FAA/XY,13
or
MAA/XY
06
(X) is multiplied by (Y). The
high-order product is stored
in Y; the low-order product
is stored in LOR.
Indicator: Exponent overflow.
Po stnormalization.
F-4
[Nl4]
Max=W i +26+
AAR: A-S
BAR: Bp
LOR: Low-order product.
Sign bit = o. Exponent = high-order
exponent minus 35.
Ni+1S+ [NI/6]
N i +2l+
+ [Nn /6]
+ [Nn /4]
+Nn /6
Min=Wi+ lS • 5 +
AAR: Ap
BAR: Bp
LOR: Low-order product.
Sign bit = o. Exponent = high-order
exponent minus 35.
15+ [Nl/6]+
19+[Nl/4]+
Max=W i +21. 0+
Nn /6
16]
[N n /4]
Nn /6
Min=W i +l3.5+
N n /6
#2-139
APPENDIX F.
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200, AND 4200
Table F-1 (cont).
Summary of Scientific Instructions
FLOA TING DIVIDE
Memory to
accumulator
FMA/A, XY, 12
or
DMA/A,XY
07
(A) is divided by (X). The
quotient is stored in Y; the
remainder is stored in LOR.
Indicators: Exponent overflow,
divide check.
Formatting: Prenormalization
of divisor (and of dividend with
Feature 1101),
of quotient.
AAR: A-8
BAR: Bp
LOR" Remainder.
Sign = sign of dividend. Exponent =
exponent of normal_
ized dividend minus
35, and plus one if
the absolute value of
the dividend mantis
is greater than the
absolute value of the
mantissa of the normalized divisor.
Accumulator to
accumulator
FAA/XY,I2
or
DAA/XY
06
(Y) is divided by (X). The
quotient is stored in Y; the remainder is stored in LOR.
Indicators: Exponent overflow,
divide check.
Formatting: Prenormalization
of divisor (and of dividend with
Feature 1101),
of quotient.
AAR: A
BAR: B P
LOR: Rgmainder.
Sign = sign of dividend. Exponent =
exponent of normal_
ized dividend minus
35, and plus one if
the absolute value of
the dividend manti
is greater than the
absolute value of the
mantissa of the normalized divisor,
The II-character signed decirnal integer whose low-order
character is A is converted to
a 36-bit binary integer. The
binary integer is stored in the
mantissa portion of Y; the
exponent of (Y) is set to +35.
One- or two-bit mantissa
overflow is possible. If mantissa overflow occurs, the
low-order one or two bits are
shifted into LOR. Y then contains the high-order result of
conversion, with an exponent
of 36 or 37. Normalization
only occurs with overflow.
AAR: A-II
BAR: Bp
LOR: Low-order result
of conversion~
Sign bit = O. Exponent = high-order
eXponent minus 35.
21+[ N /6 ]
n
Max=Wi+ 25 • 5+
Nn /6
Min=W i +l7t
Nn /6
DECIMAL TO BINARY
FMA/A, -Y, 03
or
DTB/A, -Y
07
BINAR Y TO DECIMAL
FMA/A, X-, 06
or
BTD/A, X-
07
The mantissa portion of (X) is
converted from a binary integer
to a signed decimal integer.
The decimal integer is stored
in the II-character main
memory field whose low-order
character is location A. The
exponent portion of (X) is
ignored and unaltered.
AAR: A-ll
BAR: Bp
FLOA TING TEST AND BRANCH ON
ACCUMULATOR CONDITION
FMA/A, XC, 04
Or
FBA/A,XC
07
The mantissa portion of (X) is
tested for the ·condition specified
by C, the low-order octal digit
of variant 1.
C=O
C=l
C=2
C=3
C=4
C=5
C=6
C=7
no branch
(X) = 0
(X) < 0
A
BpNO BRANCH
NXT BRANCH
SR: NXT NO BRANCH
JI(A) BRANCH
Ni +3(NO
BRANCH)
W i +5
(X) SO
(X) > 0
(X) > 0
(X) lo
unconditional branch
If the condition specified by C
is satisfied, program control
branches to location A.
NOTE: (X) must be normalized.
F-5
#2-139
APPENDIX F.
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200, AND 4200
Table F-1 (cont).
Summary of Scientific Instructions
FLOA TING TEST AND BRANCH
ON INDICA TOR
FMA/A, OD, OS
or
FBI/A,OD
07
The indicators specified by D,
the low-order octal digit of
variant 1, are tested. If~
of the indicators is set, control branches to location A.
AAR: A
BAR: NXT BRANCH
SR:
~~~~~~~c;.~H
JI(A) BRANCH
Ni+2 (NO
BRANCH)
Ni+4
W +3.8
i
W i +4·3
Ni+ 2
f~~~NCH)
no branch
Multiply overflow
Exponent overflow
Exponent or multiplyoverflow
D=4 Divide check
D=S Divide check or multiply
overflow
D=6 Divide check or exponent
overflow
D=7 Divide check, exponent
overflow, or multiply
overflow.
NOTE: ~ indicator s te sted
are reset.
D=O
D=l
D=2
D=3
BINAR Y MANTISSA SHIFT
BMS/XM, V
04
If single-precision, the mantissa
of (X) is shifted in the mode
specified by M, the low-order
octal digit of the first variant.
If double-precision, the mantis
of (X) and (LOR) are shifted.
The second variant V (0$ V$ 63)
specifies the number of positions
by which bits are shifted.
AAR: A
P
BAR: B p
7+[N/6 ]
8+[N/4 ]
W i+4·S+N.'6
AAR: A-4
BAR: B-4
LOR: unspecified
N i +2l+(Nl /6]
N i +23+[ N/4]
Max=W i +21.5
M=O left, SP, rotate (end
around)
M=4 left, SP, arithmetic
M=2 left, DP, rotate
M=6 left, DP, arithmetic
M=l right, SP, rotate
M=5 right, SP, arithmetic
M=3 right, DP, rotate
M=7 right, DP, arithmetic
NOTE: The exponents of (X)
and (LOR) are set to
zero. In an arithmetic shift, the signs
of the mantissas of (X)
and (LOR) are pre-
BINARY INTEGER MULTIPLY
BIM/A, B
05
The four-character fields in
memory whose low-order char-
acters are A and B are treated
as 24-bit binary integers. The
integers are multiplied together;
the product is stored in the field
specified by the B address.
Indicator: Multiply overflow.
F-6
Min=W i +16.5
#2-139
APPENDIX
EXTENDED MULTIPROGRAMMING AND 8-BIT TRANSFER
FOR MODELS 1200, 1250, 2200, and 4200
G
The extended multiprogramming and 8-bit transfer capability is available as Feature 1120,
1121, and 1118011. the Models 1200/1250,2200, and4200, respectively. The models 1200/1250 and
2200 must be equipped with the Storage Protect Features (1114 and 1117, respectively) before
Features 1120 and 1121 can be add,ed.
Extended multiprogramming provides aprocessor with five basic capabilities required in a
multiprogramming environment and one feature requiredfor upward compatibility.
1.
Bas e relocation,
2.
Storage protection with base relocation,
3.
Interrupt masking,
4.
Instruction timeout,
5.
8-bit transfer capability, and
6.
Privileged SCR Instructions.
These are:
STORAGE PROTECTION WITH BASE RELOCATION
In a processor equipped with extended multiprogramming, storage protection operates in
either of two ways: with or without base relocation.
Storage protection without base relocation
operates as described in Appendix E.
The storage protection offered by extended multiprogramming is made possible by using
bas e relocation in conjunction with storage protection.
Bas e relocation is in effect when the
relocation indicator is set (via the SVI and RVI instructions) and the proces sor is in the standard (non-interrupt) mode.
Storage protection with base relocation places a barrier above and below the area of
memory where the active program is to operate, to prevent it from altering the contents of the
rest of memory.
The lower barrier is specified by the contents of the bas e relocation register
(BRR), which is loaded and stored via Load Index/Barricade Register (LIB) and Store Index/
Barricade Register (SIB) instructions.
When relocation is in effect, the BRR is loaded with
the bank address of the lowest memory bank (4,096 characters) available to standard mode
I
programs.
The BRR is added to each processor memory address transmitted to memory by
a standard mode progra:m. This prevents a standard mode programfrom writing into a memory
bank below that specified by the BRR.
index barricade register (IBR).
The upper barrier is specified by the contents of the
When storage protection is in effect and an attempt is made to
G-l
#2-139
APPENDIX G.
EXTENDED MULTIPROGRAMMING AND 8 .. BIT TRANSFER FEATURES
write into memory at an address greater than that stored in the IBR, a protection violation
occurs resulting in an internal interrupt.
The IBR contains the number of 4, 096-character mem-
ory banks which are available to a program.
A monitor program keeps track of the locations of the various programs stored in memory
and, via the settings of the BRR and the IBR, can relocate referenc'es to any number of 4, 096character banks of memory.
Thus, while. there may be any number of programs stored in
memory, only one program is active at anyone tim.e and all other programs are protected
from the active program when storage protection is in effect.
When, as the result of an
interrupt, the monitor program activates a different program, it simply alters the settings
of the BRR and the IBR to make available a different portion of memory.
Since all memory references are relocated via the BRR when relocation is in effect,
index registers Xl through X15 effectively reside in the 4, 096-character bank of memory
specified by the BRR.
The location of index registers Yl through Y15 is also dependent on
the setting of the relocation indicator.
When relocation is activated, the Y index registers
are also located in the 4, 096-character bank specified by the BRR, where they become identical
to index registers Xl through X15.
When relocation is in effect, each program stored, including
the monitor program, has its own set of 15 index registers when it is the active program.
The
index registers always reside in the memory area occupied by the active program.
EXTERNAL INTERRUPT MASKING
Each input I output (1/0) s ector has as sociated with it a I-bit mask.
This mask is stored
and set by Store Variant and Indicators (SVI) and Restore Variant and Indicators (RVI) instructions, respectively.
When the mask for a sector is a zero, interrupts from sources in that
sector are accepted and processed in the manner specified in Appendix D.
When the mask for a
sector is a one, then interrupts are held until the mask is altered or the interrupt function is
reset.
Control panel and Monitor Call interrupts are never masked.
Depression of the
INITIALIZE button on the control panel causes all mask bits to be reset to zeros.
INSTRUCTION TIMEOUT
It is possible for an instruction in a program to enter an infinite extraction or execution
loop which would prevent a monitor program from servicing an interrupt within a specified time.
To prevent this from occurring, a timeout function is provided which allows a maximum time
limit to be placed on the extraction and the execution of anyone instruction when the processor
is in the standard mode.
This function guarantees that a monitor program Will, at some speci-
fied time, regain control of the system.
G-2
#2-139
APPENDIX G.
EXTENDED MULTIPROGRAMMING AND 8-BIT TRANSFER FEATURES
The instruction timer is reset to zero and begins timing every time the processor starts
to extract or execute a new instruction.
If the timeout allow function is on, the protect indicator
is set, and the processor is in the standard mode when the time interval elapses, then the instruction being extracted or executed is terminated and an internal interrupt occurs.
The timeout function is enabled by a timeout allow function which is set and reset by the
SVI and RVI instructions.
Refer to pages 8-92 and 8-95 for SVI and RVI instructions.
8-BIT TRANSFER CAPABILITY
This capability allows central processor Types 1201, 1251, 2201, and 4201 to transfer
data between peripheral controls and merrlOry in either 6- or 8-bit format, as specified in the
Peripheral Data Transfer (PDT) instruction.
1.
The 6-bit mode is the standard data transfer mode used in Series 200
central processors. In this mode, only data is transferred between
memory and peripheral controls. Punctuation is preserved in memory.
2.
The 8-bit mode is used in those applications where an 8-bit transfer is
desired between the central processor and a peripheral control. In this
mode of operation, data and punctuation are transferred between the
central processor and peripheral controls. Record marks in memory do
not terminate data transfer in this mode.
When in the 8-bit mode,
th~
number of 8-bit character transfers to be performed is
determined by a 3-character count field in the PDT instruction or by control-characters associated with the PDT peripheral controls.
The high-order bit of the C3 control character in a PDT instruction is a multivariant bit
which conditions the peripheral control in its interpretation of the remainder of the instruction.
When this bit is a zero, all additional control characters beyond C3 are ignored by the control.
When the high-order bit of C3 is a one, additional control characters are present and will be
accepted by the peripheral control.' In this case, the format of the PDT instruction becomes:
Op code/A address/C1, C2, C3, C4, C5, C6, C7.
Control character C4 is always present when the multivariant bit (bit 6 of C3) is a one.
When the extended bit (bit 5 of C3) is a one, control characters C5, C6, and C7 are present.
When the extended bit is a zero, control characters C5,C6, and C7 are ignored.
The high-
order bit of C4 determines the data transfer mode; one specifies 8-bit mode and a zero specifies
6 -bit mode.
Because 8-bit mode data transfers are not affected by record marks, data transfer
is delimited by the setting of the extended bit in the C3 control character.
If this bit is a zero,
all data transfers previously terminated by a record mark are now terminated by transferring
the number of characters specified in the record header area.
G-3
If it is
a
one, all data transfers
#2-139
APPENDIX G.
EXTENDED MULTIPROGRAMMING AND 8-BIT TRANSFER FEATURES
previously terminated by a record m.ark are now terminated by transferring the number of characters specified by the count field (C5, C6, and C7) of the PDT instruction.
PRIVILEGED SCR INSTR UCTION
When a processor is in the standard mode with the storage protection indicator ON and the
proceed indicator OFF, the detection of an SCR instruction having a variant character of octal00 through octal 37 will set the op code violation indicator and cause an internal interrupt to
occur at the next opportunity.
The following status is specified at the con,clusion of the trapped SCR instruction.
1.
The internal interrupt register (IIR) contains the address of the privileged
op code.
2.
The A -addre s s regi ster (AAR) contains the addres s of the previous instruction.
3.
The main memory locations specified by the A-address are undisturbed.
4.
The variant register contains the variant character of the privileged SCR
instruction.
All S CR instructions are identically executed if the proceed indicator is ON.
G-4
#2-139
EXTENDED INPUT/OUTPUT CAPACITY FOR THE MODEL 4200
An extended
input/outpu~
APPENDIX
H
capacity for the Model 4200 is available as Features 1116, 4214A,
4214B, and 4215.
FEATURE 1116
Feature 1116 increases the peripheral flexibility of the Model 4200 by providing a third
input/output sector.
This feature includes eight additional read/write channels for a total of 16,
and facilities which allow the permanent connection of 16 additional peripheral controls for a
total of 48.
With this expanded system, up to 16 read/write channels can be used simultaneously
for data transfer operations.
Sector 3 handles up to four peripheral devices simultaneously and has a maximum data
transfer rate of 333, 333 characters per second.
Thus when feature 1116 is included, the I/O
controller can accommodate a peak data transfer rate of 1, 333, 333 characters per second.
FEATURES 4214A and 4214B
Features 4214A 1 (Two Buffered I/O Sectors) and 4214B2 (Two Additional Buffered I/O Sectors), provide the Model 4200 with buffered I/O sectors for those applications where additional
compute time or a hi-gher input/output transfer capability is required.
When both features are
included, sectors 1 and 3 remain unchanged but sector 2 is replaced with four buffered sectors.
Each buffered sector has a data transfer rate of 500, 000 characters per second, can handle up
to 6 peripheral devices simultaneously, and provides facilities to permanently attach up to 16
modate a data transfer rate of 2, 833, 333 characters per second and perform a total of 16 simultaneous input/ output operations.
In addition to increasing the I/O capability of the Model 4200,
Features 4214A and 4214B reduce the usage of available memory cycles by the I/O controller.
Consequently, the :m.e:m.ory cycles saved are available to the central processor.
FEATURE 4215
1
Feature 4215 (High-Speed Third Sector) increases the transfer rate of that sector to
1, 333, 333 characters per second. This allows connection of I/O peripheral devices with transfer
rates exceeding 500, 000 characters per second to the third sector.
1
When Feature 4215 is added
Requires the installation of Feature 1116.
2Requires the installation of Feature 4214A.
H-l
#2-139
APPENDIX H.
EXTENDED INPUT /OUTPUT CAPACITY FOR THE MODEL 4200
to the system, the data transfer rate is 2, 333, 333 characters per second.
When Feature 4215
is included as well as Features 4214A and 4214B, the I/O controller can accommodate a peak
data transfer rate of 3, 833, 333 characters per second.
BUFFERED SECTORS
A single buffered sector is equipped with six 4-character buffers.
Therefore, up to six
devices operating concurrently are provided with a 4-character storage area.
ulates up to 4 characters of data before requiring access to main memory.
A buffer accum-
The buffered sectors
may be used without their buffer areas (direct mode) but this arrangement results in a slower
data transfer rate.
Table H-l indicates whether or not a control/device can be connected to a
buffered sector in either the buffered or in the direct mode.
In order to attain optimum system performance, sectors and their maximum data transfer
rates should be taken into consideration before permanently connecting peripheral controls to
particular sectors.
Table H-l.
Type
Type
Type
Type
Type
Type
Type
Type
Type
Controls /Device s Connectable to Buffered Sector s
203 - Tape Controls (all)
206 - High-Speed Printer Control
206A - Printer Control for 822-3
207 - Card Reader Control (for Type 227)
208 - Card Punch Control (for Type 227)
208-1 - Card Punch Control (for 224-1, -2, or 214-1).
208-2 - Card Read/Punch Control (for 224-1, -2, or 214-2)
209 }
209-2 . - Paper Tape Reader and Control
Type 210 - Paper Tape Punch and Control
Type 212 - On-Line Adapter
Type 212-1 - Central Processor Adapter
Type 213-3 - Interval Timer
Type 213-4 - Time of Day Clock
Type 220 -1, - 2, -3 - Console
Type 222-1, -2, -3, -4, -5, -6 - Printer and Control
Type 223 - Card Reader and Control
Type 223-2 - C?;rd Reader and Control
Type 229 - Printer and Control
Type 232 - MICR Reader-Sorter and Control
Type 233-2 - MICR Control
Type 234 - Plotter Control
Type 235 - Optical Journal Reader Control
Type 237 - Bill Feed Printer Control
Type 238 - Optical Reader Control
Type 257 - Control for 258, 259 Disk Pack Drives
Type 257-1 - Control for 258, 259 Disk Pack Drives ( 6.and 8-bit
transfer)
H-2
Yes
No
No
No
No
Yes
Yes
No
No
No
No
No
Yes
Yes
No
Yes
Yes
No
No
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
No
No
Yes
No
Yes
Yes
No
Yes
No
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
#2-139
APPENDIX H.
EXTENDED INPUT /OUTPUT CAPACITY FOR THE MODEL 4200
Table H-1 (cont).
Controls/Devices Connectable to Buffered Sectors
Type 257A - Control for 259A Disk Pack Drive
Type 257B - Control for 259B Disk Pack Drive
Type 257B-l- Control for 259B Disk Pack Drive (-6 and 8-bit
transfer)
Type 260 - Control for 26) and 262 Disk Files
Type 260-1 - Control for 265, 266 High-Speed Drum.s
Type 260-2 - Control for 267 High-Speed Drum.s
Type 270A-l, -2, -3 - Random. Access Drum. Storage and Control
Type 281 - Single -Channel Com.m.unication Controls (all)
Type 286-1, -2, -3, -4, -5 - Multi-Channel Comm.unicatlon
Controls (all)
Type 287 - AUTODIN Comm.unication Control
Type 287-1 - USASCII A UTODIN Com.m.unication Control
H-3
No
No
No
No
No
No
Yes
Yes
No
No
No
No
No
No
No
No
Yes
No
No
No
Yes
Yes
#2-139
COMPUTER-GENERAIE~
A-ADDRESS RtGISTER (AAR), 4-4
A-FItLD WORD MAR~-LCA
LOAD ~HARACTERS TO A-fIELD wORD MAR~-LCA' 8-56
AAR
A-ADDRESS ~EGlST£k (AAR). 4-4
ABSOLUTE. 5-13
" MEMORY ADDRESSES,
CONVtRSION Of SYMBOLIC TAGS TO A~SOLUTE MEMORy
ADDRESStS. 3-2
ACCESS
" DRUM.
C3 COOING FOR TYPE 270A RANDUM ACCESS DRJM,
8-125
RANDOM ACCESS DRUMS, 1-11
" DRUM UNITS.
RANDOM ACCES~ DRUM UNITS. 1-11
MEMURY ACCtSS, 2-~
ACTIVE ADDRtSS BITS IN SERIES 200 PROCESSORS. 4-15
ACfIVITltS
CONTROL UNiT ACTIVITIES. 2-11
INPUT/OUTPUT TRAFFIC CONTROL ACtIVITIES. 2-12
ADD
COMPLEMENT ADD. 8-7
" EXAMPLt::S,
COMPLE~ENT ADD EXA~PLES, 8-8
TRUE ADD EXAMPLES. 8-7
II
INSTRUCT ION,
EXTRACTION OF DATA FIELDS iN TYPICAL ADD
lNSTRUCtION,4-2
TYPICAL ADD INSTRUCTION. 4-1
SERIES 200 ADD AND SUBTRACT OPERATIONS. 8-4
TRUt ADD. B-7
ADD-A. 8-14
ADD-SA
BINARY ADD-BA. 8-17
ADD .. HA
HALF ADD-HA. 8-29
ADD-ZA
ZERO AND ADD-ZA. 8-20
ADDll ION
BINARY ADDITION. 8-4
DECIMAL ADDITION, 8-7
ALGEBRAIC SIGNS IN DECIMAL ADDITION. 8-7
" TABLE.
BINARY ADDITION TABLE. 8-4
ADDITIONAL
II
CODING RULES. 5-12
II
PERIPHERAL DEVICES. 1-16. 1-17
II
READ/WRITE CrlANNELS. UNIT LOADS. AN~ ADD~ESS
ASSIGN~ENTS. 1-22
ADDRt;:SS
A AND B AD~RESSES, 3~2
ABSOLUTE ME~ORY ADDRESSES.
CONVERSION OF SYMBOLIC TA6S TO A~SOLUTE MEMORY
ADDRESSE:.S. 3-2
" ASSE.MBLY.
FOUR-CHARACTER ADDRESS ASSEMBLY. 5-4
THREE-CHARACTtR ADDRESS A5SE~clLY. 5-4
TWO-CHARACTER ADDRESS ASSEMBLY. ~-3
" ASSIGNMENTS.
ADDITIONAL READ/WRITE CHANNE.LS. UNIT LOADS. AND
ADDRESS ASSIGNMENTS. 1-22
ADDRESS ASSIGN~ENTS AND UNIT LOADS AVAILABL~ IN
SERIES 200 PROCESSORS. 1-19
" BITS.
AClIVE ADDRESS BITS IN SERIES 200 PROCESSORS.
4 .. 15
" CODES. 5-12
INDEX REGISTER ADDRESSES IN FUUR-CHARACTtR
ADDRESSING MODE. 4-14
INDE.JC REGISTER ADDRESSES IN THREE .. CrlARACTER
ADDRESSING MODE. 4-12
INDEXtD ADDRESS.
ASSEMBLY OF INDEXED ADDRESS IN FOUR.CHARACTER
ADDRESSING MODE. 5-23
ASSEMBLY OF INDEXED ADDRESS IN lHREE-CHARACTtR
ADDRESSING MODE. 5-22
EXTRACTION.OF INDEXED ADDRtSS l~ THREE-CHARACTER
"10DE. 4-13
INDEXED FOUR-CHARACTER ADDRESSES.
EXlRACTION OF INDIRECT AND INDEXED
FOUR-CHARACTER ADDRESSE.S. 4-15
INDIRE:.CT AvDRESS.
ASSEMBLY OF INDIRECT ADDRESS IN fOUR~CHARACTtR
ADDRESSl~G MODE. ~-24
ASSEMBLY OF INDIRECT ADDRtSS IN IHREE-CHARACfER
ADDRESSl~G MODE. 5-23
(CONT.)
INDEX
ADDRESS (CONT.)
" LITERALS. 5~19
" MODl-ADMODt..
SET ADDRESS MODE-ADMODE. 7-11
" MDDIFICATION. 4-8
II
MODI~ICATION CODES. 5-~1
PERIPHERAL ADDRESSES AND UNIT LOADS. 1-17
PDTENTIAL ADDRESSES wITHIN ADDRESS RANGE. ~-16
" RANut.
POTENTIAL ADDRESSES wiTHIN ADDRESS RANGE. 4-16
" REGISfER RANGE.
POTENTIAL ADDRESSES OUTSIDE ADDRESS REGISTER
RANGE. 4... 16
" REGISTERS. 2-8
THREE-CHARACTER ADDRESS. 4-10
THREE-CHARACTER INDIRECT ADDRESS.
E:.XTRACTION OF THREE-CHARACTER INDIRECT ADDRESS.
4-11
TREATMENT OF ADDRESSES LARGER THAN A MEMORY.S
MAXIMUM ADDRESS. 4-16
ADDRESS-DSA
DEFINE SYMBOLIC ADDRESS-DSA. 6-7
ADDRESSES UUTSIDE ADDRESS REGISTER RANGE
POTENflAL ADDRESSES aUf SIDE ADDRESS REGISTER RANGE.
4-16
ADDRtSSING. 4-1
EXPLICIT ADDRESSING. IMPLICIT ADDRESSING. AND
CHAINING. 4-17
INDEXED ADDRESSING. 4-12. 4-14
INDIRECT ADDRESSING, 4-10. 4-13
INTERLEAVED ADDRESSING, 2-5
" MODE,
ADDRESSING MODES, 1-4. 4-5
ASSEMBLY OF INDEXED ADDRESS IN FOUR.CHARACTER
ADDRESSING MUDE. 5-23
ASSEMBLY OF INDEXED ADDRESS IN THREE-CHARACTER
ADDRESSING MODE. 5-22
ASSEMBLY OF INDIRECT ADDRESS IN FOUR_CHARACTER
ADDRESSING MODE. 5-24
ASSE.MBLY OF INDIRECT ADDRESS IN THREE-CHARACTER
ADDRESSING MODE. 5-23
CHANGING ADDRESSING MODES VIA CAM INSTRUCTION.
8 .. 65
FOUR-CHARACTER ADDRESSING MODE. 4 .. 13. 4-8
lNDEX REGISTER ADDRESSES IN FOUR-CHARACTER
ADDRESSING MODE. 4-14
INDEX REGISTER ADDRESSES IN THREE-CHARACTER
ADDRESSING MODE. 4-12
rHREE-CHARACTER ADDRESSING MODE. 4-6
lWO-CHARACTER ADDRESSING MODE. 4 .. 5
" MODE-CAM.
CHANGE ADDRESSING MODE.CAM. 8-62
REGISTERS USED IN ADDRESSING. 4-3
ADVANCED PROGRAMMING. 1.21
" FEATURE.
MODEL 200 ADVANCED PROGRAM~ING FEATURE, 1~21
" INS1KUCTIONS.
bCC TEST CONDITIONS WITH ADVANCED PROGRAMMIN~
INSTRUCTIONS. 8-41
ALGEBRAIC SIGNS IN DECIMAL ADDITION. 8-7
ALPHANU"1ER1C
II CONSIANTS.
6-4
" LITERALS. 5-18
ANGULAR POSITION INDICATOR. 1-11
AREA DEFINING LITERALS~ 5~19
AREA ... DA
DEFINE AREA-DA. 6-7
AREA-RESV
RESERVE AREA-RESV. 6.6
ARITHMETIC
" OPERATIONS, 8-4
AUTOMATiC FORMATTING IN ARITHMETIC OPERATIONS.
F-2
" SIGN CONVENTIONS.
UECIMAL ARITHMETIC SIGN CONVENTIONS. 8-9
" UNIT. 2-10
UATA FLOW BETWEEN MAIN MEMORY AND ARITHMETIC
UNIT. 2-11
ASSE~I:lLER
ASSE~lBLER
S. 5... 3
RELATIONSHIP OF SOURCE. ASSEMBLER. AND OBJECT
PROGRAM. 5-2
ASSE"1BLY
" CONTROL STATEMENTS. 7-1
FOUR-CHARACTER ADDRESS ASSEMBLY, 5-4
" OF INDEXED ADDRESS IN FOUR.CHARACTER ADDRESSING
"'lODE. 5-23
(CONT.)
(CUNT.)
INUEXED ADDRES~ IN THREE-CHARA~T~~ ADDRESSING
MODE' ;-22
" O~ INDIRECT ADDRE~S IN fOUR-CHARACTE~ ADDRtSSING
MODE. 5... 24
" O~ INUIRECr ADDRESS IN THREE-CHARAClER ADDRESSIN6
MODE. 5-23
THREE-CHARACTER AUDRESS ASSEM~~Y. '-4
TWO-CHARACTER ADD~ESS ASSEMB~Y. 5-3
ASSl(jNMENTS
AUDRESS ASSIGNMEN15.
ADDITIONA~ READ/WRITE CHANNE~S. UNIT ~OADS. AND
ADDRESS ASSIGNMENTS. 1-22
ADURESS ASSIGNMENTS AND UNIT ~OADS AVAl~A~lE IN
SERIES 200 PROCESSORS. 1-19
SELECTING R~C ASSIGNMENTS.
CONSIDERATION~ IN SEL[CTIN6 RwC ASSlGNMENTS.
8 ... 110
SELECTING RwC ASSIGNMENTS fOR USE l~ PDT
INSTRUCTIONS. 8-110
AUTOMATIC fORMATTING IN ARITHMETIC OPERA110NS. F-2
AUXILIARY READ/WRITE CHANNELS
PRIMA~Y AND AUXILIA~Y READ/wRITE CHANNELS. 2-16
B-ADDRESS REGISTER (BAR). 4-4
BAR
6-ADDRESS REGISTER (BAR), 4-4
BARRICAUE LOCATION
CORRESPONDENCE BETwEEN LIB SETTIN~ AND BARRICADE
LOCATI(,)N. 8-8U
BASE RELOCATION
STORA6E PROTECTION WITH BASE RELOCAf40N. G-1
BASE-X BASE
SET OUT-Of-SEQUENCE BASE-XBASE' 7-16
BASIC
" CONCEIolTS. 4 ... 1
" INPUT/OUJP~T DATA PATH. 1_18
" TEST CONDITIONS fOR Bec INSTRUCTION, 8... 40
Bee
BRANCH ON CHARACTER CONDITION (~CC) CONDITIONS. B-5
" INSTRUCTION.
BASIC TEST CONDITIONS FOR Bec IN5TRUCTION, 8-40
n TEST CONDITIONS WITH ADVANCED IolRO~RAMMING
INSTRUCTIONS. 8-41
BeT
BRANCH ON CONDITION TEST (BCT) IN~ICArOR CONDITIONS.
ASSEMB~Y
O~
C~N1kOLS/DEVICES
"
B.. 4
BRANCH ON CONDITION TEST (BCT) SEN5c SWITCH
CONDITIONS. B-3
" INSTRUCTION,
INDICATOR TES1 C'ONDITIONS ~OR eCT INSTRUCTION,
8 .. 37
SENSE SWITCH CONDITIONS FOR BCT iNSTRUCTION,
8 .. 36
BIL~ FEED PRINTER
C3 COOIN~ FOR TYPtS 206 AND 222 ~RI~lERS AND TYPE
2~7 BILL FEED PRINTER. 8-125
BINARY
OCTAL. AND DECIMAL EQUIVALENTS. e-~.
" ADD-BA. 8... 17
" ADOll ION, 8.. 4
" ADDITION TABL~. 8-4
,. CONSTANTS, b-2
" LITERALS. ~ .. 16
" SUBTRACT-BS~ 8-19
" SUBTRACTION. 8-4
BINARY-OCTAL EQU'VALENTS. A-l
BIT EQUAL-BBE.
BRANCH ON BIT EQUAL-BBE. 8-44
BITS
ACTIVE ADDRESS BilS IN SERIES 200 PROCESSORS. 4~15
BLANK, 5"'15
,. CONSTANTS. 6-4
BPI RECORDING DENSITY
1200 BPI RECORDING DENSITY, 1-8
BRANCH
" IF CHARACTER EQUAL.BCE. 8_42
" ON BIT EQUAL-BBE. 8-44
" ON CHARACTER CONDiTION (BeC) CONDITlONS. 8-5
" ON CHARACTER CONDITION.BCC. 8~39
" ON CONDITION TEST (BCT) INDICATOR CUNDITIONS. B... 4
" ON CONDITIUN TEST (BCT) SENSE SWITCH CONDI1IONS. B-3
" ON CONDITION TEST-BCT, 8-35
BRAN'H .. B. 8-34
BRANCH .. PCB
PERIPHERAL CONTROL AND BRANCH-PCB. ~-127
BUFFER
PRINT BUfFER. 1-8
BUfFERED SELTORS. H-2
H-2
CONNECTAbLE Ta BUFFERED SECTORS.
CALL-t'IC
MONITOR CALL-MC. 9-98
CAM 11115 TRU," TlON
CHAN~lNG ADDk~S~lNG MOUES VIA CAM INSTRUCTION. 8.65
MODES SPECIFIED BY VARIANT CHARACTER IN CAM
lN5TRUCTION. 8-63
CAPABILITY
8-611 TRANSFER CAPABILITY. G~3
CAPACITY
EXTENDED INPUT/OUTPUT CAPACITY FOR THE MODEL 4200.
~1-1
CARD
" REQUIREMt:NTS.
MINIMUM RWC CAPACITY REQUIREMENTS FOR SERIES 200
pERIpHERAL DtVICES. 8-111
"
CE
CODE~.
PUNCHED CARD CODES. 3-8
" COLUMN.
MARK (CARD COLUMN 7). 5-6
lYPE (CARD COLUMN 6). 5-6
" eOlUf'iINS 1-5,
LARD NUMUER (CARD COLUMNS 1-5), 5~5
" COLUf'INS 15-20.
. OPERATION CODE (CARD COLUMNS 15-20). 5-1U
" COLUf'INS 8 .. 14,
LOCATIoN (CARD COLUMNS 8-14). 5-8
EASYCODER CARD D OPTIONS, 6-10
" EQUII-li'1ENT.
PUNCHED CARD EQUIPMENT. 1-7. 1-8
" FORNAT.
PUNCHED CARD FORMAl. 3-8
" NUMUER (CARD COLUMNS 1-5). 5-5
" READ OPERA1ION.
DATA PATH DURING CARD READ OPERATION. 1.19
PCB
1/0 CHARACTER CE.
DESCRIpTION Of PCB I/O CHARACTER CE. 8-149
PDT I/O CHARACTER CE.
DESCRIPTION OF PDT I/O CHARACTER CE (ESCAPE
CODE). 8-118
CENTRAL pRUCESSOR. 1-1. 2-1
" CHARACTERISTICS.
SUMMARY OF CENTRAL PROCESSOR CHARACTERISTICS,
2 ... 17
LOGICAL DIVISION OF SERIES 200 CENTRAL PROCESSOR.
2-1
MaDEL 4200 MEMORY INTERLEAVING (TYPE 4201 .. 9 CENTRAL
PROCESSOR),2"6
" MaDES. E.. 1
CHAINING
EXPLICIT ADDRESSING. IMPLICIT ADDRESSING. AND
CHAINING, 4-17
CHANGE
" ADDRt:SSlNG MODE-CAM. 8-62
" SEQUENC~ REGISTER (CSR). 4-3
" SEQUENCING MODE-CSM. 8-66
CHANGING ADDRESSING MODES VIA CAM INSTRUCTION. 8-65
CHANNEL
ADDITIONAL RlAD/WRITE CHANNELS. UNIT LOADS. AND
AUDRESS ASSIGNMENTS. 1-22
AJX1LIARY READ/WRITE CHANNELS,
PRIMARy AND AUXILIARY READ/WRITE CHANNELS. 2~16
INTERLOCKING READ/wRITE CHANNELS, 2~16
MODEL 4200 VARIABLE-SPEED READ/WRITE CHANNELS. 2-16
READ/WRITE CHANNEL. 1-18
TYPE 286 MULTI CHANNEL.
SUMMARY OF PDT I/O CONTROL CHARACTERS FOR TYPE
286 MULTI CHANNEL. 8-12Q
CHARACTER
II CE.
VESCRIPTION OF PCB I/O CHARACTER CE. 8~149
DESCRIPTION Of PDT I/O CHARACTER CE (ESCAPE
CODE), 8-118
" CODES.
SERIES 200 CHARACTER CODES. Bp7
" CONDiTION.
BRANCH ON CHARACTER CONDITION (BCC) CONDITIONS.
8-5
" CONt) I Tl ON ... BCC.
bRANCH ON CHARACTER CONDITION-BCC. 8-39
" Cl,
DESCRIPllON Of PDTI/o CONTROL CHARACTER C1.
1:) ... 116
" e2,
DESCRIPfiON Of PDT I/o CHARACTER C2 (PERIPHERAL
((ONT .)
COMPUfER-GENERATED INDEX
CHARACTER (LONT.)
CONTROL DESIGNATION. a-l1b
" EQUAL-BCE.
BRANCH If CHARACTER EQ~AL-BCE' 8-42
INPUT/OUTPJT CONTKOL CHARACTERS. 5-Zl
LOAU (HA~ACTERS TO A-FIELD WORO MARK-LCA. 8-56
MOVE CHA~ACTERS AND EDIT-MCE. 8-104
MOVE CHARACTERS TO WORD MARK-MCW, 8-55
PCB 110 CONTROL CHARACTERS.
SUMMARY OF PC~ 1/0 CONTROL CHARALfER5, 8-130
SUMMARY OF PCB 1/0 CONTROL CHARALTERS FOR TYPE
286, 8-146
PDT 1/0 CONTROL CHARACTERS.
SUMMARY O~ PDl 1/0 CONTROL CHARACTERS, 8.120
SUMMARY OF PDI I/O CONTROL CHARACTERS FOR TYPE
286 MULTl CHANNEL, 8-126
" REPRESENTATION ON MAGNETIC TAPE. 3-7
REPRESENTION OF CHARACTERS IN MAGNErlC CORE STURAGE'
2"3
SPECIAL CHARACTERS IN MCE INSTRUCTIJN, 8-105
VARlAN1 CHARACTER, 3-3. 5.. 20
MODES SPECIFIED BY VARIANT CHARACTER IN CAM
INSTRUCTION, 8-63
CHARACTERISTICS
CENTRAL PROCESSOR CHARACTERISTICS,
SUMMARY OF CENTRAL PROCESSOR CHARACTERISTICS.
2-17
CHARACTERS C5
PCB CONTRO~ CHARAlTERS C5 THRUUGH C!~ FOR TYPE
286-4, -5 LINE. 8-148
CHECK
CLEAR
" ITEM MARK-CI, 8-51
" ~ORD MARK ... CW, 8-50
CLEAR.CLEAR, 7-19
CODE
AODRESS CODES. 5.12
ADDRESS ~ODIFICATION CODES. 5-21
DESCRlPTION OF PDT I/O CHARACltR CE (tSCAPE COPE),
8-118
OPERATION CODE. 3-2
OPERAfION COD~ (CARD COLUMNS 15-20), 5-10
OPERATION JTIlIZING ESCAPE CODES,
EXAMPLE OF OPERATION UTIL!ZlN~ ~SCAPE CODES,
6 ... 114
PUNCHED CARD CODES. 3-8
SERIE~ 200 CHARACIER CODES. B-7
CODING
C3 COOING FOR TYPE 209 AND 209-2 PAPER TAPE READERS,
8"124
C3 CODING FOR TYPE 210 PAPER TAPE PUNCH, 8... 124
C3 CODING FOR TYPE 270A RANDOM ACCE~5 DRUM, 8-125
C3 CODING FOR TYPES 206 AND 222 PRINTERS AND TYPE
237 BILL FEED PRINTER, 8-125
" FORM, 5-5
EASYCODER CODING FORM. 5-5
" RULES.
ADDITIONAL COOING RULES, 5-12
SAMPLE CODING FOR EXTERNAL INTERRUPl ROUTINE. D-4
SAMPLE CODING FOR INTERNAL INTERRUPI ROUTINE, 0-5
COLUMN
MARK (CARD COLUMN 7), 5-6
TYPE (CARD COLUMN 6), 5-6
COLUMNS
" 1-5.
CARD NUMBER (CARD COLUMNS 1-5). 5-5
" 15 .. 20.
OPERATION CODE (CARD COLUMNS 15-20). 5-10
" 8 .. 14.
LOCATION (CARO COLUMNS 8-14), 5-8
COMMUNICATION EQUIPMENT
DATA COM~UNICATION EQUIPMENT. 1-12' 1-13
COMMUNICATIONS NETWORK
CUSTOMER INQUIRY HANDLING VIA TYPICAL COMMUNICATIONS
NETWOR(. 1-15
COMPARE"", 8-32
COMPATIBILITY
uPWARD COM~ATIBILITY, 8-114
COMP~EMENT ADD. B... 7
" EXAMPLES. 8.. 8
COMPONENTS
SERIE~ 200 COMPON~NTS. 1~1
CONCEPTS
BASIC CONCtPTS. 4"'1
CONDIT ION
BASIC TEST CONDITIONS FOR BCC INSrRJCIION, 8-40
(CONT. )
COND IT I ON (CON 1.)
BCC lEST CONDITIONS WITH ADVANCED PROGRAMMING
INSTRUCIIONS. 8-41
BRANlH ON CONDITION TE~T (BCT) INDICATOR CONDITIONS.
B .. 4
BRANCH ON CONDITION TEST (BCT) SENSE SWITCH
CONDIT IONS. B.. 3
CHARACTER CONDITION.
bRANCH ON CHARACTER CONDITION (sec) CONDITIONS,
8-5
EXTENDED MOVE (EXM) CONDITIONS, B-2
EXTENDED MOV~ CONDITIONS, 8.. 68
INDICATOR TEST ~ONDITIONS FOR BCT INSTRUCTION, 8-37
SCAN CONDITIUNS.
MOVE OR SCAN CONDITIONS. 8-88
SENSE SwITCH CONDITIONS FOR BCT INSTRUCTION. 8-36
It
TEST.
BRANCH ON CONDITION TEST (BCT) INDICATOR
CONDITIONS. 8-4
BRANCH ON CONDITION TEST (BCT) SENSE SWITCH
CONDIT IONS. i:l .. 3
" TEST-BCT,
5RANCH ON CONDITION TEST-BCT. 8-35
CONDITION-BCC
CHARACTER CONDITION-BCC,
bRANCH ON CHARACTER CONDITION-Bce. 8-39
CONFICJURATIONS
MEMORY CONFIGURATIONS fOR TYPE 4201 PROCESSORS. 2-4
CONNECTABLE
CONTROLS/DEVICES CONNECTABLE TO BUFFERED SECTORS.
H"2
CONSECUTIVE STORAGE LOCATIONS IN MAIN MEMORY, 3-4
CONSIDERATIONS IN SELECTING RWC ASSIGNMENTS. 8... 110
CONSOLE
" EQUIPMENT. 1-14
TypE 220-1 CQNSOLE, 1-3
TypE 220 ... 3 CONSOLE, 1-3
CONSTANT
ALPHANUMERIC CONSTANTS. 6-4
BINARy CONSTANTS. 6~2
BLANK CONSTANTS. 6.. 4
DECIMAL CONSTANTS, 6.2
DEFI~E CONSTANT WITH WORD MARK.DCW, 6.2
F~OArING-POINT CONSTANIS. 6-5
NUMERlC CONSTANTS, 6-2
OCTAL CONSTANTS. 6-3
eONSTANT ... D<.
DEFl~E CONSTANT ... DC, 6-5
CONIE:.NTS
" LOADf:.D,
CONTROL REGISTER CONTENTS LOADED BY LCR
INSTRUCTION. 8 ... 61
" STORt:.D,
<'ONTROl REGISTER CONTENTS SToRED BY SCR
INSTRUCTION, 8-58
CONTROL, 8-47
" ACTIVITIES.
!NPUT/OUTPUT TRAFFIC CONTROL ACTIVITIES, 2-12
" CHARACTER Cl,
DESCRIPTION OF PDTIIO CONTROL CHARACTER C1,
8-116
" CHARACTERS,
INPUTIOUTPUT CONTROL CHARACTERS, 5-21
SUMMARy OF PCB 1/0 CONTROL CHARACTERS. 8-130
SUMMARY OF PCB I/O CONTROL CHARACTERS FOR TYPE
286. 8... 146
SUMMARY OF PDT I/O CONTROL CHARACTERS, 8~120
SUMMARY OF PDT I/O CONTROL CHARACTERS FOR TYPE
28Q MULTI CHANNEL, B.126
It
CHARACTERS C5.
PCB CONTROL CHARACTERS C5 THRO~GH C15 FOR TYPE
266·4. -5 LINE, 8 ... 148
" DESICJNA lION,
DESCRIPTION OF PDT I/O CHARACTER C2 (PERIPHERAL
CONTROL DESIGNATION. 8-118
" EQUALS.CEQU. 7-13
INPUJ/OUTPUl TRAFFIC CONTROL. 2-12
LOGICAL DECISION PERFORMED BY INPUTIOUTPUT
TRAFFIC CONTROL. 2-14
~YMBOL'C REPRESENTATION OF INP~T/OUTPUT TRAFFIC
CONTROL. 2 .. 15
" INS rRUCTIONS.
TYPE 286-1. ~2. -3 LINE CONTROL INSTRUCTIONS.
8 ... 126
" INTERRUPT,
PERIPHERAL CONTROL INTERRUPT. D.5
INTERRUPT CONTROL. 8_91
(CONT. )
INDEX
CUMPUT~R-GENERATED
CONT~OL
DAIA
(COl'll.)
INTERKJPT/ALLOW FUNCTION CONTROL,
SU~MARY O~ INIEHRUPT/ALLOW FUNCIIUN CONTROL AND
lEST OPt~ATIONS, D-I
" Mt:.MORY, 2-6
" MEMURY REGISTERS, 2-8
SIZE OF CONTRUL MEMORy ~E~15rtR~ (MODELS
200/120U/1250/2200/~2UO).
(C:),,<1.)
"
"
2-7
" OPt:.RATIONS.
INPUr/JJTPUT CONTROL OPlRAIIONS. 8-110
TYPE~ OF lEST AND CONTROL Up~~ArlONS. 8-128
" PAN~L.
TYPE 1201 CONIROL PANEL. 1-2
PERIPHERAL CONTROL. 1-7
IN1ERRJPT SIGNAL GENERATED BY PERIPHERAL
CONTROL. D-6
PERIPHERAL CONTROL AND BRANCH-PCB. 8-121
" REGIST~R CONTENTS LOADED BY LCR INSTRUCTION. 8-61
" REGISTt:.R CONTENTS STORED BY SCR INSIRUCrION. 8-58
" REGlSTt:.R DESIGNATIONS. B-1
" REGISTER FJNCTION.
TYPICAL CONTRUL RE~ISTER ~UNCrIJN. 2-7
" REGIS1ER5 STORED bY SCR INSTRUCTION. 8-59
" RtGIS1ER5-LCR.
LOAD CONTROL REGISTERS-LCR. 8-60
" REGISTERS-SCR.
STORE CONTROL REGISTERS-seR. 8-58
" STATEMENTS.
ASSEMBLY CONTROL STATEMENTS. 7-1
" UNIT. 2-11
" UNIT ACTIVITIES. 2-11
CONTROLLEI'<
MEMORY CONTROLLER. 2-5
CONTROLS/DEVICES CONNEC1ABLE TO BUFfEREU SECTORS. H-2
CONVENlIONS
DECIMAL ARITHMETIC SIGN CONVENTIONS. 8-9
DIVIDE SIGN CONVENTIONS. 8-!3
MULTIPLY SIGN CONVENTIONS. 8-10
CONV~RSION
" OF SYMBOLIC TAGS 10 ABSOLUTE MEMORY ADDRESSES. 3-2
II PROCEDURE.
OlTAL-OECIMAL CONVERSION PROCEDvRE. A-3
II
TABLE.
DECIMAL-OCTAL CONVERSION TABLE. A-2
CORE STURAGE
REPRESENTION OF CHARACTERS IN MAGNETIC CORE STURAGE.
2"3
COUNTERS
READIWRITE COUNTERS, 2-8
CSR
CHANGE SEQ~ENCE RE~ISTER (CSR). 4-3
CUSTUMER INWUIRY HANDLIN~ VIA TYPICAL CUMMUNICATIONS
NETWOR<. 1... 15
CW
CLEAR WORD MARK - CW. 8-50
CYCLE
" DISTRIBUTION,
MEMORY CYCLE DISTRIBUTION. 2-12
MEMURY CYCLE. 2-3
C1
PDTI/O CONTROL CHARACTER Cl.
DESCRIPTION Of PDTIIO CONTROL CHARACTER C1,
8-116
C15
PCB CONTROL CHARACTERS (5 THROUGH C15 FOR TYPE
286-4. -5 LINE. 8-148
C2
PDT lID CHARACTER C2.
DESCRIPTION Of PDT 110 CHARACTER (2 (PERIPHERAL
CONTROL DESIGNATION. 8-118
C3 CODING
" FOR TYPE 209 AND 209-2 PAPER TAPE READERS. 8-1Z4
" FOR TYPE 210 PAPER TAPE PUNCH. 8-124
" FOR TYPE 270A RANDOM ACCESS DRUM. 8-125
" FOR TYPES 206 AND 222 PRINTERS ANU TYPE 231 BILL
FEED PRINTER. 8-125
C5
PCB CONTROL CHARACTERS C5 THROUGH Cl~ FOR TYPE
286-~. -5 LINE. 8-1~8
DATA
" COMMUNICATION EQUIPMENT. 1-12. 1-13
" FIELD FORMAT IN MAIN MEMORY. 3-~
" FIELDS.
EXTRACTION OF DATA FIELDS AN TYPICAL ADD
INSTRUCI ION, 4-2
" fLOW bETWEEN MAIN ~EMORY AND ARITrl~ErIC UNIT. 2-11
" FORMAT. F-l. 3-1
(CONT.)
"
"
"
UATA FORMAT ON MAGNETIC TAPE. 3-8
MAGNETIC TAPE DATA FORMAT. 3-7
SUMMARY OF INTERNAL DATA FORMATS. 3-6
FORMATTING STATEMENTS. 6-1
ORGANIZATION Of DATA IN MAIN MEMORY. 3~4
PATH.
, bASlC INPUT/OUTPUT DA1A PATH. 1-18
UATA PATH DURING CARD R~AD OPERATION. 1-19
TRAN~FEk l~TtRVALS DURING ONt PERIPHERAL OPERATIoN.
;::"13
TRANSfER OPERATION.
PERIPHERAL DATA TRANSFER OPERATION. 1-17
TRAN~FER RATE.
UEVICE DATA TRANSFER RATE. 8-110
" TRAN~FE.R/PDT.
PERIPHERAL DATA TRANSfER/~DT. 8-115
DEC!VlAL
"ADDITION. B-7
ALGEBRAIC SIGNS IN DECIMAL ADDITION. 8.7
" ARITHMETIC SIGN CONVENIIONS. 8-9
" CONS1ANTS. 6-2
II
EQUIVALENTS.
bINARY. UCTAL. AND DECIMAL EQUIVALENTS. B-8
" LITt.RALS. 5-16
" SUBTRACTION. 8-8
DECI~AL-OCTAL CONVERSION TABLE. A-2
DECISION
LOGICAL DECISION PERFORMED BY INPUT/OUTPUT TRAFFIC
CONTROL. Z-14
DEFINE:.
" AREA-DA. 6-7
" CONSTANT WITH WORD MARK-DCw. 6-2
" CONSTANT-DC. 6.5
" SYMBOLIC ADDRESS-DSA. 6-7
DEFINING LITERALS
AREA DEfINING LITERALS, 5-19
DENSITY
1200 BPI R~CORDING DENSITY. 1-8
DESCRIPTION
" OF PCB 1/0 CHARACTER CE. 8-149
" OF PDT 1/0 CHARACTER CE:. (ESCAPE CODE). 8-118
" OF PDT 1/0 CHARACTER C2 (PERIPHERAL CONTROL
DESIGNATION, 8-118
" OF PDTI/O CONTROL CHARACTER Cl. 8-116
SERl~S 200 INSTRUCT(ON DESCRIPTIONS.
~YMBOLOGy USED IN SERIES 200 INSTRUCTION
DESCRIPTIONS. 8~2
DE.Sl:JNATION
CONTROL REGISTER DESIGNATIONS. B"l
DESCRIPTION OF PDT 1/0 CHARACTER Cz (PERIPHERAL
CONTROL DESIGNATION. 8-118
DEVICE:.
ADDIliONAL PERIPHERAL DEVICES. 1-16. 1-17
" DATA TRANSFER RATE. 8-110
INPU1IOUTPUT SECTOR TO WHICH DEVICE IS CONNECTED.
8-114
SERI~S ZOO PERIPHERAL DEVICES.
MINIMUM RWC CAPACITY REQUIREMENTS FOR SERIES 200
PERIPHERAL D~VICES. 8-111
VIsUAL INFORMATION PROJECTION DEVICES. 1~14. 1-16
DISK
" fILES. 1-10. 1~11
" PACK DRIVES. 1-10
DISTRIBUTION
MEMORY CYCLE DISTRIBUTION. 2-12
Dl VJi)E
" OPERATION,
fACTOR LOCATIONS IN DlVIDE OPERATION. 8-12
" SIGN CONVENTIONS, 8-13
DIVIDE-D. 8-25
DIVISION. 8 .. 11
LOGICAL DIvISION OF SERIES 200 CENTRAL PROCESSOR.
2"1
DRIV~S
DRUM
DISK PACK DRIVES. 1-10
HIGH·SPEED DRUMS. 1-11. 1-12
RANDUM ACCESS DRUMS. 1-11
TYPE 210A RANDOM ACCESS DRUM.
C3 CODING FOR TYPE 270A RANDOM ACCESS DRUM.
8-125
" UNITS.
RANDOM ACCESS DRUM UNlTS. 1-11
DUMP-HS~
MEMORY DUMP-H5M. 7-14
EASYCODER
COMPUTER-GENERATEJ INDEX
(CONT.)
" CARD D OPTIONS. 6-10
" CODING FORM, 5-5
" PROGRAMMIN~. 5-1
SET 11 PJNCTUATION INDICATORS (EASYCUDER C AND D
ONLY). 5-7
EDIT INSTRUCTION. 1-22
EDIT-MCE
MOVE lHARACTERS AND EDIT-MCE, 8-104
EDlIIN:J. 8 .. 103
EIR
EXTERNAL INTERRUPI REGISTER (EIR). 4.. 3
END-I:.ND. "7-20
EQUAL-BBE
BIT EQUAL-6BE.
BRANCH ON BIT EQUAL-BBE. 8-44
EQUAL-BCE
CHARACTER EQ~AL-BtE.
BRANCH IF CHARACTER EQUAL-BCE. 8-42
EQUALS .. CEQU
CONTROL EQUAI,..S-CEuJ. 7-13
EQUALS-EUU. 7-12
EQUII->MENT
CONSOLE EQUIPMENT. 1.14
DATA COMMUNICATION EQUIPMENT. 1-12. 1-13
PAPER TAPE EQUIPMI:.NT. 1-12
PERIPHERAL EQUIPMENT. 1... 6
PUNCHED CARD EQUIPMENT. 1-7. 1-8
TELLER TERMINAL EQUIPMENT. 1-16
EQUIVALENTS
BINARY-OCTAL EQUIVALENTS. A-1
DECIMAL EQUIVALENTS.
BINA~Y. OCTAL. AND DECIMAL EQUIVALENTS. B-8
ESCAPE CODE
DESCRIPTION OF PDr 1/0 CHARACTER CE (ESCAPE CODE).
8-118
EXAMPLE OF OPERATION UTILIZING ESCAPE CODES, 8-114
EXAMPLE
COMPLEMENT ADD EXAMPLES. 8-8
" Of OPERATION UTILIZING ESCAPE CODES. 8-114
TRUE ADD EXAMPLES. 8-7
EXECUTE .. EX. 7-4
EXM
EXlENUED MOVE (EXM) CONDITIONS. B-2
EXP~lCIT ADDRESSING. IMPLICIT ADDRESSING. AND
CHAINING. 4.. 11
EXTENDED
" INpUT/OUfPUT CAPALITY FOR THE MODEL 4200. H-1
" MOVE (EXM) CONDITIONS. B-2
" MOVE CONDITIONS. 8-68
" MOVE-EXM. 8-67
" MULTI-PROGRAMMING AND 8.BIT TRANSFER, 1-23
" OF INFORMATION UNITS IN MIT OPERATION. 8w75
EXTERNAL INrERRUPT. D-l
EXTERNAL INTERRUPTS. 1-4
" MASKING. G"2
" REGISTER (EIR). 4-3
" ROUTINE.
SAMPLE CODING FOR EXTERNAL IN1ERRUPT ROUTINE.
EASYlOD~R
D.. 4
EXTRACT-EXT. 8-28
EXTRACTION
," OF DATA FIELDS IN TYPICAL AOD IN5TR~CTION. 4-2
" OF INDEXED ADDRESS IN THREE-CHARACTER MODE. 4-13
" O~ INDIRECT AND INDEXED FOUR.CHARACTER ADDRESSES.
4"15
" OF THREE-CHARACTER INDIRECT ADDRESS. 4-11
FACTOR LOCATIONS IN DIVlDE OPERATION. 8-12
FEATURE
MODEL 200 ADVANCED PROGRAMMING FEATJRE. 1-21
OPTIONAL FEATURES. 1~20
SERIES 200 OPlIONAL FEATURES. 1-20
STORAGE PROTECT FEATURE. E-1
" 0191. 1 .. 23
" 1116, H.. l
" 4215. H.. l
FEATURES 4214A AND 4214~. H-1
FEED PRINTER
(3 CODING FOR TYPES 206 AND 222 P~lN1ERS AND TYPt
237 BILL FEED PRINTER. 8-125
FIELD
" FORMAl.
DATA FIE~D FOR~AT IN MAIN MEMORY. 3-5
" ~ENGTH.
VARIABLE FIELD LENGTH, 3-1
FIELDS. 3"4
A AND B rIEL~S IN ~ULTIPLY OPERATION. 8-10
(CONT. )
Fl ELDS (CON T.)
DATA FIELDS.
EXTRACTION OF DATA FIELDS IN TYPICAL ADD
IN5TRUCTION, 4~2
FILES
DISK FILES, 1·10. 1-11
FLOATING-PUINT
" CONSTANTS. 6-5
" INDICATORS. F-2
" REGISTERS. F-l
F~OW
DATA FLOW BETWEEN MAIN MEMORY AND ARITHMETIC UNIT.
FORM
FORMAT
2-11
CODING FORM. 5-5
EASYLODER CODING FORM, 5-5
DATA FIELD FORMAT IN MAIN MEMORY, 3-5
DATA FORMAl. F.. l. 3-1
DATA FORMAT ON MAGNETIC TAPE. 3-8
INSTRUCTION FORMAT, 3-2
INTERNAL DATA FORMATS.
SUMMARY OF INTERNAL DATA FORMATS, 3-6
ITEM FORMAT S.
lWO ITEM FORMATS IN MAIN MEMORY. 3.5
MAGNETIC TAPE DATA FORMAT, 3-7
PUNCHED CARD FORMAT. 3.8
RECORD FORMAT IN MAIN MEMORY. 3-6
SERIES ZOO INSTRUCTION FORMAT 1. 4-17
SERIES 200 INSTRUCTION FORMAT 2. 4-18
SERIES ZOO INSTRUCTION FORMAT 3. 4-18
SERIES 200 INSTRUCTION FORMATS. 3-3
FORMATTING
AUTOMATIC FORMATTING IN ARITHMETIC OPERATIONS, F~2
" STATEMENTS.
OATA FORMATTING STATEMENTS, 6-1
FORMULAS MODELS ZOO
INSTRUCTION SUMMARY-TIMING FORMULAS MODELS 200,
1200. 1250. AND 2200. C~4
FOUR-CHARAC.TER
" ADDRESS ASSEMBLY. 5-4
" ADDRESSES,
EXTRACTION OF INDIRECT AND INDEXED
FOUR_CHARACTER ADDRESSES, 4-15
" ADDRESSING MODE. 4 .. 13, 4-8
ASSEMBLY OF INDEXED ADDRESS IN FOUR-CHARACTER
ADDRESSING MODE. 5-23
ASSEMBLY OF INDIRECT ADDRESS IN FOUR_CHARACTER
ADDRESSING MODE. ~-24
INDEX REGISTER ADDRESSES I~ FOUR-CHARACTER
ADDRESSING MODE. 4-14
FUNCTION
" CONTROL,
SUMMARY OF INTERRUPTIALLOW FUNCTION CONTRoL AND
TEST OPERATIONS, D-7
MAIN MEMORY FUNCTIONS. 2-2
TYPICAL CONTROL REGISTER" FUNCTION, 2-7
GENERATE-GEN. 7-17
GENERATED
INTERRUPT SIGNAL GENERATED BY PERIPHERAL CONTROL,
1)"6
HALF ADD_HA. 8-29
HALT-H. 8 .. ~2
HANDLIN:J
CUSTOMER INQUIRY HANDLING VIA TYPICAL COMMUNICATIONS
NETWORK. 1.. 15
HE.ADER-PROe:;
PRoGRAM HEADER~PROG, 7-2
HEADER .. SEG
SEGMENT HEADER~5EG. 7-4
HIGH·SPEED
" DRUM5. 1-11, 1.. 12
" PRINIERS, 1.. 9
1/0 CHARACTER
" CE,
~ESCRIPTION OF PCB 1/0 CHARACTER eE. 8-149
~ESCRIPT10N OF PDT 1/0 CHARACTER CE (ESCAPE
CODE). 8 ... 118
" C2.
DESCRIPTlON OF PDT 1/0 CHARACTER (2 (PERIPHERAL
CONTROL DESIGNATION. 8-118
1/0 CONTRO~ CHARACTERS
SUMMARY OF PCB 1/0 CONTROL CHARACTERS. 8-130
SUMMARY OF PCB 1/0 CONlROL CHARACTERS FOR TYPE 286.
8-14b
SUMMARY OF PDT 1/0 CONTROL CHARACTERS, 8-120
SUMMARy OF PDT. 1/0 CONTROL CHARACTERS FOR TYPE 286
(CONT.)
COMPUTtR-GENERATEJ INDEX
I/O CONTRoL CHARACTERS (CONT.)
MULTI ~rlANNEL. 8-126
I IR
INIt,RNAL INTERRUf>1 REGISTER (llR). 4-4
IMPLICIT ADURE~Sl~G
.
EXf>LICIT ADDRlSSINS. IMPLICIT AUDRE~~ING, AND
CHAINIIIIG. 4-11
INDEX REGISIER
II Al)l)RE!)SES,
INDEX ~EGISTfH ADDRESSES IN FUJ~-lHARAC1ER
AvDRESSING MODE. 4-14
INDEX REGISTER ADDRESSES IN TrlR~t-CHARACTER
ADDRESSING MODE. 4-1,
" '-lAP, 4-9
SlRIES 200 INDEX REGISTER MAP, 4-9
INDEX REGlSTE.R~, l-l, 4-9
" SIMULlANEOJSLY,
NU'-lBER Of INDEX REGISTERS !)1~~LrANEOUSLY
AvAILABLE TO A PROGRAM. 4-10
INDEX/BARRICADE
" REGISTER-UB.
LOAD I~Dt,X/BARRICADE REGl~IER-Ll~, 8-79
" REGISfER-SIB,
STORE IIllDEX/BARRICADE REG1STER-~lB. H-8,
INDEXED. 5-21
" AI)DRESS.
ASSEMBLY OF INDEXED ADDRESS IN rOJR-CHARACTER
ADDRESSlNG MODE. 5-23
ASSEMBLy Of INDEXED ADDRESS IN IHREE-CHARACTER
ADDRESSIIIIG MODE. 5-22
EXTRACIION OF INDEXED ADDRESS I~ rHREE-CHARACTER
1v\ODEt 4-13
" ADDRE!)SING, 4-12. 4-14
" FOUR-CHARACTER ADD~ESSES,
EXIRACTION OF INDIRECT ANI) INDEXED
FOUR-CHARACTER ADDRE~S~~. 4-15
INDl<':ATOR
ANGULAR PO~lTION INDICATOR. 1-11
" CONDITIONS.
BRANCH ON CONDITION TEST (~CT) INUICATOR
CONDITIONS. B-4
FLOATING-POINT INDICATORS. F-~
INDICATORS. 1:1-9
PROCEED INDICATOR. E-5
PUNCTUATION INDICATORS.
SET 1 PJNCTUATION INDICATORS. ~-,
SET 11 PUNCTUATION INDICArORS ItASYCODER C AND D
ONL.Y), ':>-7
" TEST <':ONDITIONS FOR BCT INSTRUCriON. 8-37
INDICATORS .. KVI
RESTOKE VARIANT AND INDICATORS-RVI. 8-95
INDICATORS-SVI
STORE VA~IANT AND INDICATORS-SVI. 8-92
INDIRECT, 5.. 23
" AI)DRESS,
ASSE~8LY OF INDIRECT ADDRES~ IN rOUR-CHARACTlR
ADDRESSING MODE. 5-24
ASSEMBLY OF INDIRECT ADDRESS IN IHREE-CHARACIER
ADDRESSING MODE. 5-23
EXTRACIION OF THREE-CHARACTtR INDIRECT ADDRESS,
4 .. 11
" ADDRESSING. 4.. 10. 4-13
EXfRAlTION or INDIRECT AND INDEXED fUUR-lHAHACTEH
AUDRESSES, 4"15
INFORMATION
" PROJE<':TION DEVICES.
VISUAL INfORMATION PROJECTION DEVICES. 1-14,
1 .. 1b
" RESTORED BY RVI INSTRUCTION. 8 .. 9b
" STORED BY SVI INSIRUCTIONS. 8-92
" UNITS.
EXTENDED OF INFORMATION UNIT~ IN ~IT OPERATION.
S.. 75
INPUT/OUTPUT. 1:1-109
" CAPAClTY.
EXTENDED INPUT/OUTPUT CAPA<.:lTY fOR THE MODEL
4200. H-l
" CONTROL. CHARACTERS, 5-21
" CONTROL OPERATIONS. 8-110
" DATA PATH,
BASIC INPUT/OUTPUT DATA PATH. 1-18
" SECTOK TO ~HICH DEVICE IS CONNE<.:TEU, 8-114
" TRAFFIC CONT~OL. 2-12
LOGICAL DECISION PERFORMED BY I~PJT/OUTPUT
TRAFFIC CONTROL. 2-14
SYMBOLIC REPRESENTATION Of INf>JI/OUTPUT TRAFrlC
CONTROL, 2-15
(CONT.)
INPU1/OUTPl,JJ (COI~I.)
" TRAF~IC CO~TkOL ACTIVITI~S. 2-12
1NQU 1RY HAI~LlLI NG
CUST0M~R INwuIHY HANDLING VIA TYPICAL COMMUNICATIONS
1~£TwORK. 1-15
INST~UCTl(JN
ADVANCED PROGRAMMING INSTRUCTIONS,
beC TE~r CONDITIONS w1TH ADVANCED PROGRAMMING
INSTRUCTIONS. 8-41
BCC lNSTRUCl10N.
bASIC rlST CONDITIONS FOR BCC INS1RUCTION, 8-40
BCT iNS1RUCTION.
INDICAToR T~ST CONDITIONS FOR BCT INSTRUCTION.
8-37
SENSE SWITCH CONDITIONS FOR BCT INSTRUCTION.
8-~b
CAM INS1RUCTION,
CHANGING ADDRESSING MUDES vIA CAM INSTRUCTION.
8-b5
MODES
SP~CIFIED BY VARIANT CHARACTER I~ CAM
INSTRUCTION. 8-63
" DE.SCk I PT IONS,
SYMBOLOGY USED IN SERltS 200 INSTRUCTION
DESCRIPTIONS. 8-2
EDIT INSTRUCIION. 1-22
" FORI"1AT, 3-2
SERIES 200 INSTRUCIION FORMAT 1, 4-11
SERIES 200 INSTRUClION FORMAT 2. 4-18
~ERIES 200 INSTRUCTION FORMAT 3. 4-18
SERIES 200 INSTKUCIION FORMAlS. 3-3
INSTRUCTIONS. 8-1
LCR 11~STRUCT ION,
(ONTROL. REGISTER CONTENTS LOADED BY LCR
INSTRUCTION. 8-b1
LINE CONTROL INSTRUCTIONS,
lYPE 2&6 .. 1. -2. -3 LINE CONTROL INSTRUcTIONS,
8"'126
MCE lNSTRUCllON,
!)PECIAL CHARACTERS IN MCE INSTRUCTION, 8-105
PDT INSTRUCrIONS.
SELECTING RWC ASSIGNME.NTS FOR USE IN PUT
INSTRUCTIONS. 8-110
PRIVILEGED SCR INSTRUCTION. G-4
RvI INSTRUCT ION,
INFORMATION RESToRED BY RVI INSTRUCTION. 8-96
SCIENTIFIC INSTRUCTIONS.
SUMMARY OF SCIENTIFIc INSTRUCTIONS, F-4
SCR INSTRUCTION.
CONTROL REGISTER CONTENTS STORED BY SCR
INSTRUCTION, 8-58
CONTROL REGISTERS STORED BY SCR INSTRUCTION.
8 .. 59
SERI~S 200 INSTRUCTIONS.
SYMBOLIC REPRESENTATION OF SERIES 200
INSTRUCTIONS. 3-4
" SUMMARY-TIMING fORMULAS MODELS 200. 1200. 1250, AND
~200.
(-4
SVI INSlRUCTIONS,
lNFORMATION STORED BY SVI INSTRUCTIONS. 8-92
" TIMEOUT, G.. 2
" TIMINGS FOR THE MODEL 4200. C-l
TypICAL ADD INSTRUCTION, 4~1
~XTRACTION OF DATA FIELDS IN TYPICAL ADD
INSTRUCTION, 4-2
INTERLEAVED ADDRESSING, 2-5
INlERLEAVING
MODEL. 4200 MEMORY INTERLEAVING (TYPE 4201-9 CENTRAL
PROCESSOR), 2 .. b
INTERLOCKING READ/wRITE CHANNELS. 2-1b
INTE~NAL
" DATA FORMATS.
SUMMARY OF INTERNAL DATA FORMATS. 3-b
" INTERRUPT. D-2. E-2. 1-4
" INTtRRUPT RE~ISTER (11k). 4-4
" INTERRUPT ROUTINE.
SAMPLE CODING FOR INTERNAL INTERRUPT ROUTINE,
D-':>
INTERRUPT
" CONTROL. 8-91
lXTERNAL INTERRUPT. Dpl
EXTERNAL INTERRUPTS. 1-4
INTE.RNAL INTERRUPT. D-2. E-2, 1-4
" MASK!NG.
EXTERNAL INTERRUPT MASKING. G-2
PERIPHERAL CONTROL INT~RRUPT, D-5
" PROC~SSING. D-1
(CONT. )
CO~~UTER-GENERATED
INTERRuPT (lONT.)
» PROCESSING MODE, 1-3
PRO~RA~ INTERRUPT, 1-22
» PRO~RAMMING, Dw3
" REGISIER,
INTE~RUpr REGISTtR (EIRJ, 4-3
INTERNAL INTERRUPT REGIST~R (lj~). 4-4
" ROUTINE,
SA~PLE CODING FOR EXTERNAL lNTERRUPT ROUTINE.
D... 4
SAMPLE CODING FOR INTERNAL INrERRUPT ROUTINE.
D.. 5
" SIGNAL GENERATED bY PERIPHERAL CONTROL, D-6
INTERRUPT/ALLOw FJNCTION CONTROL
SUMMARY OF INTERRUPT/ALLOW FUNCTION CONTROL ANU lEST
OPERATIONS, D-7
INTERVALS
DATA rRANSFER INTtRVALS DURIN~ aNt PERIPHERAL
O~ERATlON' 2-13
INTRODUCTION. 5-1. 6-1, 7-1, 8-1
ITEM
" FORMATS,
TWO ITEM FORMATS IN MAIN MEMORY. 3-5
ITEMS. 3-5
" MARK-CI,
CLEAR ITEM MARK-CI. 8-51
"MARK-51,
'
StT ITEM MARK-51, 8-49
MOVE ITEM AND TRANSLATE-MIT' 8-14
ITEM-MARK TRAPPING MODE, 1-5
LANGUAGE
SYMbOLIC LANGUAGE, 5-3
LCR INSTRUC1ION
CONTROL RE~lSTER CONTENTS LOADED bY LCR INSTRUCTION,
8-61
LENGTH
VARIAbLE FIELD LENGTH. 3-1
LIB SEllING
CORRESPONDtNCE BET~EEN LIB SEITINb AND BARRICADE
LOCA Tl~)N, 8.. 80
LINE
" CONTROL INSTRUCTIONS,
TYPE 286~1. -2. -3 LINE CONTRUL INSTRUCTIONS,
8 .. 126
" NUMBER .. SETI..IN,
StT LINE NUMBER-SETlIN, 7·18
PCB CONTROl.. CHARACTERS C5 THROUGH Cl~ FOR TYPE
2B6-4, -5 LINE, 8-148
LITERAl.. ORIGIN-LITORG, 1-9
l.ITERAI..5, 5-15
ADDRESS LITERALS, 5-19
ALPHANUMERIC LITERALS, 5-18
AREA DEFINING LITERALS, 5-19
BINARY LITtRALS, ~-16
DECIMAL LITERALS. 5-16
OCTAL LITERALS, 5-17
l.OAD
" CHARA~TE~S TO A-FIELD WORD MARK-LeA, 8-56
" CONTROL REGISTERS~LCR' 8-60
" INDEX/BARRICADE REGISTER-LIB. 8-79
l.OADED
CON1ROL REGISTER CONTENTS LOADED bY LCR INSjRUCTION,
8-61
LOADS
ADDITIONAL READ/WRITE CHANNtLS, UNIT LOADS. AND
ADDRESS ASSIGN~ENTS, 1-22
UNIT LOADS,
ADDRESS ASSIGNMENTS AND UNIT LOADS AVAILABI..E IN
SERIES 200 PROCESSORS, 1-19
PERIPHERAL ADDRESSES AND UNIT LJADS, 1-17
LOCATION
" (CARD COLUMNS 8.. 14), 5-8
BARRICADE LOCATION.
CURRESPONDENCE BETWEEN Ll~ SETT1NG AND BARRllADE
1..0CATlON, 8-80
CONSECUTIVE STORA~E LOCATIONS IN MAlN MEMORY, 3-4
FACTOR LOCATIONS IN DIVIDE OPERATION. 8-12
LOGIC, 8-27
LOGICAl..
" DECISION PERFORMED BY INPUT/OUTPUT TRAFFIC CONTROL,
2-14
" DIVISION OF SERIES 200 CENTRAL PROCESSOR, 2.. 1
LOOKUp .. TLU
TABLE LOOKJP-TLU, 8-83
~AGNETlC
STO~AGE,
REPRESENT ION OF CHARACTERS IN MAGNETIC
(CONT.)
(lONT.)
5 TORAGE. 2-3
" TAPL,
CHARACTER REPRESENTATION ON MAGNETIC TAPE. 3~7
DATA FORMAT ON MAGNETIC TAPE, 3-8
" TAPE DATA ~ORMAT. 3~7
" TAPE UNITS, 1-8, 1-9
MAIN MEMORy, 2-1
CONSlCUTIVE STORAGE LOCATIONS IN MAIN MEMORY, 3~4
DATA FIELD FORMAT IN MAIN MEMORY. 3-5
DATA FLOW BETWEEN MAIN. MEMORy AND ARITHMETIC UNIT,
MAGN~TIC
EXTE~NAL
" CORE
INDEX
COR~
~-ll
MAP
" F:JNCIIONS, 2-2
" IN THE TYPE 4201 PROCESSOR. 2-4
ORGANIZATION OF DATA IN MAIN MEMORy. 3-4
RECORD FORMAT IN MAIN MEMORY, 3-6
" 5IZE. 1-6
" SPEED. 1-6
T~O If EM FoRMATS IN MAIN MEMORY, 3-5
INDEX REGISTER MAP, 4-9
200 INDEX REGISTER MAP. 4_9
SERI~5
MARK
(CARD COLUMN 7),5-6
CLEAR WORD MARK .. CW, 8-50
MARK-CI
CLEAR ITEM MARK-CI. 8-51
MARK-DO'"
wORD MARK-DCw.
DEFINE CONSTANT wITH WORD MARK-DCw, 6-2
MARK-LCA
A-FIELD WORD MARK-LCA.
LOAD CHARACTERS TO A-FIELD WoRD MARK-LeA, 8-56
II
MARK-MC~
WORD MARK-MCw,
MOVE CHARACTERS TO WORD MARK_MCW. 8-55
MARK-51
SET ITEM MARK-51, 8-49
MARK-SW
SET WORD MARK-SW. 8-48
MASKING
EXTERNAL INTERRUPT MASKING, G-2
MAT OPERATION, 8-73
MAX I '~UM ADDRESS
TREATMENT of ADDRESSES LARGER THAN A MEMORY.S
MAXIMUM ADDRESS, 4-16
MCE INSTRUC.TION
SPECIAL CHARACTERS IN MCE INSTRUCTION, 8-105
MEMORY
" ACCESS. 2"'5
" ADDRESSES,
CONVERSION OF SYMBOLIC TAGS TO ABSOLUTE MEMORY
ADDRESSES, 3-2
" CONFIGURATIONS FOR TYPE 4201 PROCESSORS, 2-4
CONTROL MEMORY. 2-6
" CONTROLLER. 2-5
" CYCL.E., 2-3
II CYCLt DISTRIBUTION,
2-12
" DUMP-HSM, 7-14
" FUNCTIONS,
MAIN MEMORY FUNCTIONS, 2-2
" INTERLEAVING,
MODEL. 4200 MEMORY INTERLEAVING (TYPE 4201_9
CENTRAL pROCESSOR), 2-6
MAIN MEMORY, 2-1
CONSECuTIVE STORAGE L.OCATIONS IN MAIN MEMORY,
3 ... 4
FIELD FORMAT IN MAIN MEMORY. 3-5
DATA FLOW BETWEEN MAIN MEMORY AND ARITHMETIC
UNiT. 2 .. 11
URGANIZATI0N OF DATA IN MAIN MEMORY. 3-4
RECORD FORMAT IN MAIN MEMORY, 3-6
.
lWO ITEM FORMATS IN MAIN MEMORY. 3-5
MAIN MEMORY IN THE TYPE 4201 PROCESSOR. 2-4
" POSIIION,
ONE MEMORY POSITION, 2.. 3
" REGISTERS,
CONTROL MEMORY REGISTERS, 2-8
SIZE OF CONTROL MEMORY REGISTERS (MODELS
200/l200/1250/2200/4200), 2-7
II SIzE.
MAIN MEMORY SIZE, 1... 6
" SPEEu,
MAIN MEMORY SPEED, 1-6
II SUBSYSTEM,
lYPE 4201 MEMORY SUBSYSTEM, 2-4
MEMORY,S MAXIMUM ADDRESS
(CONT. )
~ATA
COMPUT~R-GENERATE~
ADDRESS (CONT.)
JF ADDR~SSES LARGLR THAN A MEMORY.S
~AXI~U~ ADDRE~S. 4-16
MINIMUM RWC CAPACITY REWJIREMENTS rUR SERI~5 200
PERI~HERAL DlVICES. 8-111
MIT OPERATION. 8-79
EXTENDED OF INFoRMATION UNITS IN Mlf OPERATION. 8-75
MODE
ADDRESSING MODES. 1-4. 4-5
CENTRAL PROCESSOR MODES. E-1
CHANGING A~DRESSIN3 MODES VIA CAM 1~SIRUCT10N. 8-65
FOUR-CHARACTER ADDRESSING MODE. 4-13. 4-8
ASSEMBLY OF INDEXED ADDRESS IN FOUR-CHARAClER
ADDRESSING MODE. 5-23
ASSE~BLY OF INDIRECT ADDRESS IN ~OUR-CHARACTER
ADDRESSING MODE. 5-24
INDEX REGISTER ADDRESSES IN ~OU~-CHARACTER
ADDRESSING MODE. 4-14
INTERRUPT PROCESSING MODE. 1-3
ITEM-MARK TRAPPIN~ MODE. 1-5
MODES SPECIFIED BY VARIANT CHARACTE~ IN CAM
INSTRUCTION. 8.63
STANDARD PROCESSIN~ MODE. 1-3
THREE-CHARACTER AUDRESSING MOUE, 4-0
ASSE~BLY OF INDEXED ADDRESS IN THREE-CHARACTER
ADDRESSING MODE. 5-22
ASSE~BLY OF INDIRECT ADDRESS IN rHRE~-CHARACTER
ADDRESSING MODE. 5 Z3
INDEX REGISTER ADDRESSES IN lH~El-CHARACTER
ADDRESSING MODE. 4-12
THREE-CHARACTER MODE.
EXTRACTION OF INDEXED ADDRESS IN fHREE-CHARACTER
"10D~. 4.13
TWO-CHARACTER ADDRESSING MODE. 4-5
MODE .. ADMODE
SET ADDRESS MODE~ADMODE. 7-11
MODE-CAM
CHANGE ADDRESSING "10DE-CAM. 8~62
MODE .. CSM
CHANGE SEOJENCING MODE-CSM. 8-66
MODE .. RNM
RESUME NORMA~ MODE_RNM, 8-99
MODEL
" ZOO ADVANCED PROGRAMMING FEATURE. 1-21
" 4200.
EXTENDED INPUT/OUTPUT CAPACITY FOR THE MODE~
4200. H... l
INSTRUCTION TIMINGS FOR THE MODEL 4200,C-7
" 4Z00 MEMORY INTERLEAVING (TYPE 4201-9 CENTRAL
PROCESSOR), 2"'6
" 4200 VARIABLE-SPE~D READ/WRITE CHANNELS. 2-16
MODELS
" 1200,
SCIENTIFIC UNIT FOR MODELS 1200. 1250, 2200. AND
4200, F-1
II ZOO.
INSTRUCTION SU"1MARY .. TIMING FORMULAS MODELS 200.
1200. 1250. AND 220Q. (-4
ME~OHY.S MAXIM~M
TR~ATMENT
p
" 200/1200/125U/2200/4200.
51lE OF CONTROL MEMORy REGJSIER~ (MODELS
200/1200/1250/2200/4200),2-7
MOOIF I CA TlON
ADDRESS MODIFICATION. 4-8
" CODES-.
ADDRESS MODIFICATION CODES. 5-21
MODULAR ORIGIN-MORG, 7-9
MONITOR CALL-MC. 9-98
MOVE
" AND TRANSLATE-MAT. 8-70
" CHARACTERS.
MOVE CHARACTERS AND EDIT-MCE. 8-104
MOVE CHARACTERS TO WORD MARK-MC~. 8-55
" CONDITIONS.
EXTENDED MOVE CONDITIONS. 8-68
EXTENDED MOVE (EXM) CONDITIONS. B~2
" ITEM AND TRANSLAT~-MIT, 8-74
" OR SCAN CONDITIONS. 8-88
" OR SCAN VARIANTS. B-9
" OR SCAN-MO~, 8-86
~OVE-EXM
EXTENDED MOVE-EX~. 8-67
MULTI CHANNEL
SUMMARY OF PDT I/O CONTROL CHARACTEKS FOR TYPE 286
MULTI CHANNEL. 8-126
~ULTI-PROGRAMMING
EXTENDED MvLTI-PROGRAMMING AND 8-BIT TRANSFER. 1-23
MULTIPLICATION' 8-9
MULTlPLY (CONT.)
INDEX
MULTIPLY
" OPLRA Tl ON.
A AND ~ FIELDS IN MULTIPLY OPERATION. 8-LO
" SIGN CONVENTIONS, 8-10
MULTIPLY-M. 8-23
Nf.I WORK
TYPI~AL COMMUNICATIONS NETWORK,
tUS10M~R INQUIRY HANDLING VIA TYPICAL
COMMUNICATIONS NETWOQK. 1-15
NORMAL MODE-RNM
RESUME NORMAL MODE-RNM. 8-99
NOTATiON
OCTAL NOTATION. A-1
NUMBER
CARD NUMBER (CARD COLUMNS 1-5). 5-5
" OF INDEX RE~lSTERS SIMULTANEOUSLY AVAILAbLE TO A
PRO~RAM. 4-10
NUMBER-SEllIN
SET LINE NUMBER-SETLIN. 1-18
NUMERIC CONSTANTS. 6-2
OBJECT PRO<:JRAM
RELATIONSHIP OF SOURCE. ASSEMBLER. ANO OBJECT
PROGRAM. 5-2
OCTAL
BINAkY. OCTAL. AND DECIMAL EQUIVALENTS. B-8
" CONSTANTS. 6-3
" LITERALS. 5-17
" NOTATION, A-l
OCTAL-DECIMAL CONVERSION PROCEDURE. A~3
OPERANDS. 5"11
OPERA T1 ON
ARITHMETIC OPERATIONS, 8-4
AUTOMATIC FORMATTING IN ARITHMETIC OPERATIONS.
F-2
CARD READ OPERATION.
DATA PATH DURING CARD READ OPERATION, 1-19
" CODE. 3-2
OPERATION CODE (CARD COLUMNS 15-20). 5-10
CONTROL OPERATIONS.
lYPES OF TEST AND CONTROL OPERATIONS. 8-128
DIVIDE OPERATION.
fACTOR LOCATIONS IN DIVIDE OPERATION. 8-12
INPU1/OUTPUT CONTROL OPERATIONS. 8.110
MAT OPERATION, 8-73
MIT OPERATION, 8-79
EXTENDED OF INFORMATION UNITS IN MIT OPERATION.
8 .. 75
MJLTlPLY OPERATION.
A AND B FIELDS IN MULTIPLY OPERATION. 8-10
PERlPHERAL DATA TRANSFtR OPERATION. 1-17
PERIPHERAL OPERATION.
DATA TRANSFER INTERVALS DURING ONE PERIPHERAL
OPERATION. 2-13
SJBTRACT OPERATIONS.
SERIES 200 ADO AND SUBTRACT OPERATIONS. 8~4
TE.ST. OPt;:RAT IONS.
SUMMARY OF INTERRUPT/ALLOw FUNCTION CONTROL AND
lEST OPERATIONS. 0-7
TLU UPERATION. 8-81
" UTILIZING ESCAPE CODES.
EXAMPLE OF OPERATION UTILIZING ESCAPE CODES.
ij-114
OPERATION-NOP
NO OPERATION-NQP, 8-54
OPTIONAL FEATURES. 1-20
SERILS 200 OPTIONAL FEATURES. 1~20
OPTIJNS
EASYCODER CARD 0 OPTIONS. 6-10
ORGANIZATION OF DATA IN MAIN MEMORY. 3-4
OR I G1N-L ITORG
LITERAL ORIGIN-LIToRG. 7-9
ORIGIN-MOR, 8-118
" C2,
DESCRIPTION Or PDT I/O CHARACTER C2 (PERIPHERAL
CONTROL DESIGNATION, 8-116
PDTI/O CONTROL CHARACTER C1
DESCRIPTION Of PD1IIO CONTROL CHARACTER C1, 8-116
PERIPHERAL
" ADDRESSES AND UNII LOADS, 1-17
II
CONTROL, 1-7
INTERRJPT SIGNAL GENERATE~ BY PERIPHERAL
CONTROL, D-6
PtRIPHERAL CONTROL AND BRANCH-PCB. 8-127
" CONTRUL DESIGNATION,
DESCRIPTION OF PDT I/O CHARACTER C2 (PERIPHERAL
CONTROL DESIGNATION. 8-118
" CONTROL INTERRUPT, D-5
" DATA TRANSFER OPERATION, 1-17
I,
DEVICES.
ADDITIONAL PERIPHERAL DEVICES, 1-16, 1-17
MINIMU~ RWC CAPACITY REQUIREMENTS FOR SERIES ZOO
PERIPHERAL DEVICES. 8-111
" EQUIPMENT, 1-6
" OPERATION,
DATA TKANSFER INTERVALS DURIN~ ONE PERIPHERAL
OPERATION, 2-13
" SIMUL1ANEITY, 1-6
POSITION
" INDICATOR,
ANGULAR POSITION INDICATOR, 1-11
MEMORY POSITION.
ONE ~EMORY POSITION, 2-3
POTENTIAL ADDRESSES
OUTSIDE ADDRESS R~GISTER RAN,
POTENTIAL ADDRESSES OUTSIDE ADDKE5S REGlSTER
RANGE, 4 .. L6
" wITHIN ADDRESS RANGE, 4-16
POWER
POWERS OF 2. B.. 8
PROCESSING POWER, 1-5
PRIMARY AND AUXILIARY READ/WRITE CHANNELS, Z~16
PRINT BUFFER, 1-8
PRINTER
HIGH-SPEED PRINTERS, 1.. 9
SPEED PRINTERS,
HIGH SPEED PRINTERS, 1-8
TYPE ,37 BILL FEED PRINTER,
C3 CODIN~ FOR TYPES 206 AND 222 PRINTERS AND
TYPE 237 BILL FEED PRINTER, 8.. 125
PRIVILE~ED SCR INSTRUCTION, G-4
PROCEDURE
OCTAL-DECIMAL CONVERSION pROCEDURE' A.. 3
PROCEED INDICATOR, E-5
PROCESSING
INTERRUPT PROCESSING, D-L
" MODE.
INTERRJPT PROCESSING MODE, 1-3
STANDARD PROCESSING MODE, 1-3
ICONT. )
II
INDEX
PRUCESSING (CONT.)
" POWER, 1-5
" UNIT, 2-5
PROCI:.SSOR
BEINb USED, 8-113
(ENTRAL PROCESSOR, 1-1. 2-1
CHARACTERISTICS,
SUMMARY of CENTRAL PROCESSOR CHARACTERISTICS.
2-17
MODEL 4200 MEMORY INTERLEAVING (TYPE 4201-9 CENTRAL
PROCESSOR), 2.. 6
MODES.
'ENTRAL PROCESSOR MODES, E-l
SERIES 200 CENTRAL PROCESSOR,
LOGICAL DIvISION OF SERIES 200 CENTRAL
PROCESSOR, 2-1
SERIES ZOO PROCESSORS,
ACTIVE ADDRESS BITS IN SERIES 200 PROCESSORS,
4 ... 15
~DDRESS ASSIGNMENTS AND UNIT LOADS AVAILABLE IN
SERIES 200 PROCESSORS, 1-19
TYPE 4201 PROCESSOR,
MAIN MEMORY IN THE TYPE 4201 PROCESSOR, 2-4
TYPE 4Z01 PROCESSORS,
MEMORY CONFIGURATIUNS FOR TYPE 4201 PROCESSORS.
2-4
PROGRAM
" HEADER.PROG. 7-2
" INTERRUPT, 1-22
NUMBER OF INDEX REGISTERS SIMULTANEOUSLY AVAILABLE
10 A PROGRAM, 4-10
OBJECT PROGRAM,
RELATIONSHIP OF SOURCE, ASSEMBLER. AND OBJECT
PROGRAM. 5-2
PROGRAMMING
ADVA~CED PROGRAMMING, 1-21
EASYCODER PROGRAMMING, 5-1
" FEATlJRE,
MODEL ~OO ADVANCED PROGRAMMING FEATURE. 1-21
" INS TRUCTI ONS,
BCC TEST CONDITIONS WITH ADVANCED PROGRAMMING
INSTRUCTIONS, 8-41
INTERRUPT PROGRAMMING, 0-3
PROJECTION DEVICES
VISUA~ INFORMATION PROJECTION DEVICES, 1-14, 1~16
PROTECT
" FEATURE,
STORAGE PROTECT FEATURE, E.. 1
STORAGE PROTECT. 1-23
PROTECTION
STORAGE PROTECTION,
VIOLATIONS OF STORAGE PROTECTION, E-3
STORAGE PROTECTION WITH BASE RELOCATIoN, G-1
PUNCH
TYPE 210 PAPER TAPE PUNCH,
(3 CODING FOR TYPE 210 PAPER TAPE PUNCH, 8-124
PUNCHED CARD
" CODEs, 3-8
" EQUIPMENT. 1-7, 1-8
" FORt-lAT, 3-8
PUNCTUATION INDICATORS
SET 1 PUNCTUATION INDICATORS. 5~7
SET 11 PUNCTUATION INDICATORS (EASYCODER C AND D
ONL y>, 5 .. 7
RANDOM ACCESS DRUM
C3 CODING FOR TYPE 270A RANDOM ACCESS DRUM. 8~125
RANDOM ACCESS DRUMS. 1.. 11
" UNITS. 1-11
RANGE
ADDRESS RANGE,
POTENTIAL ADDRESSES WITHIN ADDRESs RANGE, 4~16
POTENTIAL ADDRESSES OU1SIDE ADDRESS REGISTER RANGE.
4-16
RATE
DEVICE DATA TRANSFER RATE, 8-110
READ OPERATION
DATA PATH DURING CARD READ OPERATION, 1-19
READ/WRITE
" CHANI'lEL, 1... 18
ADDITIONAL READ/wRITE CHANNELS, UNIT LuADS, AND
ADDRESS ASSIGNMENTS, 1-22
INTERLOCKING READ/WRITE CHANNELS, 2-16
MODEL 42UO VARIABLE-SPEED READ/WRITE CHANNELS,
2 .. 16
PRIMARY AND AUXILIARY READ/WRITE CHANNELS. 2-16
" COUNTERS, 2-8
READERS
(CONT.)
CO~PUT~R-GENERATE~
READt:RS (CONT.)
209-2 PAPER TAPE READERS.
C3 CODING FOR TYPE 209 ANU 209-£ PAPER lAPe
READERS. 8-124
RECOKD rOK~AT IN ~AIN Me~ORY, 3-6
RECORDIN~ DENSITY
1200 ~PI RECORDIN~ DENSITY, I-B
RECORD~. 3-6
REFERENCE
SELf HeFEReNCE, 5-13
REGISTER
A-AUDRESS REGISTER (AAR). 4-4
AUUHESS RE~ISTERS, 2-8
" AUURESSES,
INUEX ~EGISTEH ADDRESSES IN f~J~-CHARACTER
ADDRESSING MODE. 4-14
INDEX ~EGISTER ADDRESSES IN THREE-CHARACTER
ADDRESSING MODE. 4-12
8-ADDRESS REGISTER (BAR). 4-4
CHANGE SEQJENCE REGISTER (C5R), 4-3
" CONTENTS LOADED.
CONTROL REGISTER CONTENTS LOADEU 8Y LCR
INSTRUCTION, 8-61
" CONTENTS STORED.
CONTROL REGISJER CONTENTS SfOREU 8Y SCR
INSTRUCTION. 8-58
CONTROL ~E~ORY RE~ISTERS. 2-8
SIZE OF CONTROL MEMORY RE~ISTERS (MODELS
200/1200/1250/2200/4£00), 2-1
" DESIGNATIONS.
CONTROL REGISTER DESIGNATIONS. 8-1
EXTERNAL INTERRUPl REGISTER (tIR). 4-3
FLOATING-POINT RE~ISTERS. F-1
" FUNCTION,
TYPICAL CONTROL REGISTER fUNCfI0N. 2-7
INUEX REGISTERS. e-l, 4-9
INlERNAL INTERRUPt REGISTER (IIR). 4-4
" MAIJ,
INDEX REGISTER MAP, 4-9
SeRIES 200 INUEX REGISTER MAP. 4-Y
" RANGE,
POTENTIAL ADDRESSES OUTSIDE AUUR~SS REGISTER
RANGE. 4-16
REGISTERS JSED IN ADDRESSING. 4-3
SEUUENCE REGISTER (SR). 4-3
REGISTER-LI~
LOAD INDEX/BARRICADE REGISTER-LIB. 8-19
REGISTER-SI8
STORE INDEX/BARRICADE REGISTER-SI8. B-82
REGISTERS
" SIMULTANEOJSLY,
NU~BER Of INDEX REGISTERS S!MJLTANEOUSLY
AVAILABLE TO A PROGRAM, 4-10
" STORED,
CONTROL REGISTERS STORED 8Y StR INSTRUCTION,
8 .. 59
REGISTERS-LCR
LOAD lONfROL REGISTERS .. LCR, 8-60
REGISTERS-SlR
STORE CONTROL REGISTERS-SCR, 8-5B
RELATIONSHIP Of SOURCE. ASSEMBLER, AND UBJECT PROGRAM, 5-2
RELATIVE, 5-14
RELOCATION
BASE RELOCA Tl ON.
STORAGE PROTECTION WITH BASE RELOCATION. G-l
REPEAT-REP, 1-16
REPHESENTA Tl ON
CHARACTER REPRESENTATION ON MAGNE11C rAPE, 3-7
SYMBOLIC REPRESENTATION OF INPUJ/OUrpUT TRAFFIC
CONTROL, 2-15
SYMBOLIC REPRESENTATION OF SERIE~ 200 INSTRUCTIONS,
3 .. 4
REPRESENT ION Of CHARACTeRS IN MAGNErlC (ORE STORAGE, 2-3
REQUIREMENTS
MINIMU~ RWC CAPACITY REQUIREM~NTS fOR SERIES 200
PERIPHERAL DEVICES, 8-111
RESERVE AREA-RESV, 6-6
RESTORE VARIANT AND INDICATORS-RVI, 8-95
RESTORED
INFORMATlON RESTORED BY RVI II~STRJc.:r!ON. 8-96
RESUME NOR~AL ~ODE-RNM. 8-99
ROUTINE
EXTERNAL INTERRUPI ROUTINE.
SAMPLE CODING FOR EXTERNAL INJE~RUPT ROUTINE,
J.)~4
INT~RNAL INTERRUPI
SA~PLE CODING
(CONT.>
ROUTINE.
FOR INTERNAL INTEKRUPT ROUTINE,
INDEX
ROUTINE'. (CUiH.)
RULE~
ADDIIIONAL CODINu RULE~, ~-12
RVI INSTRUCTION
INFOkMATION HESTORED BY RVI INSTRUCTION, 8-96
RWC
II ASSI(.jN~1ENTS.
CONSIDERATIONS IN SELECTING RWC ASSIGNMENTS.
8-110
SELECTING RWC ASSIGNMENTS FOR JSE IN PDT
INSTRUCTIONS. 8-110
" CAPACITY REQUIREMENTS.
MINIMUM RWC CAPACITY REQUIREMENTS FOR SERIES 200
PERIpHERAL DEVICES, 8-111
SAMPLE CODING
" FOR EXTERNAL INTERRUPT ROUTINE. D-4
" FOR INTERNAL INTERRUPT ROUTINE. D-5
SCAN
" COND1TiONS.
MOVE OR ~CAN CONDITIONS, 8-88
" VARIANTS,
MOVE OR SCAN VARIANTS. 9-9
SCAN-"IOS
MOVE OR SCAN-MOS. 8-86
SCIENTIFIC
" INSTRUCTIONS,
SUMMARY OF SCIENTIfIC INSTRUCTIONS, F-4
" UNIT,
sCIENTIFIC UNIT. 1-23
SCIENTIFIC UNIT FOR MODELS 1200. 1250. 2200. AND
4200. Fool
SCR INSTRUCTION
CON1ROL REGISTER CONTENTS STORED ~Y SCR INSTRUCTION,
b-58
CONTHOL REGl~TERS STORED BY SCR INSTRUCTION. 8-59
PRIV1LEGED SCR INSTRUCTION, G-4
SECTOR
BUFFERED SECTORS. H-2
CONTROLS/DEVICES CONNECTABLE TO BUFFERED
SECTORS. H.. 2
INPUT/OUTPUT SECTOR TO WHICH DEVICE 15 CONNECTED.
ij"1l4
SEGMENT HEADER .. SEG. 7p4
SELECTING RWC ASSIGNMENTS
CONSIDERATIONS IN SELECTING RWC ASSIGNMENTS, 8~110
~ FOR USE IN PDT INSTRUCTIONS, 8.110
SELF REFERENCE. 5-13
SENSE SWITCH CONDITIONS
BRANCH ON CONDITION TEST (BCT) SENSE SWITCH
CONDITIONS. B-3
" FOR BCT INSTRUCTION. 8-36
SEQUENCE REGISTER
" (SR). 4-3
CHAhbE SEQUENCE REGISTER (CSR), 4-3
SEUUENCING MODE-CSM
CHAN~E SEQUENCING MODE·CSM. 8-66
SERIES 200
" ADD AND SUBTRACT OPERAlIONS, 8.4
" CENTRAL PROCESSOR.
LOGICAL DIvISION Or SERIES 200 CENTRAL
PROCESSOR. 2 ... 1
" CHARACTER COPES. B-7
" COMPONENTS, 1-1
" INDEX REGISTER MAP, 4·9
" INSTRUCTION DESCRIPTIONS,
~YMBOLOGY USED IN SERIES 200 INSTRUCTION
DESCRIPTIONS, 8-2
" INSTRUCTION FORMAT,
SERIES 200 INSTRUCTION FOR~AT 1. 4.17
5ERIES 200 INSTRUCTION FORMAT 2, 4-18
SERIES 200 INSTRUCTION FORMAT 3, 4~18
SERIES 200 INSTRUCfION FORMATS, 3~3
" INSTRUCTIONS,
SYMBOLIC REPRESENTATION OF SERIES 200
INSTRUCTIONS, 3~4
" OPTIONAL FEATURES. 1-20
" PERIPHERAL UEVICES,
MINIMUM RWC CAPACITy REQUIREMENTS FOR SERIES 200
PERIPHERAL DEVICES, 8.111
II PROCESSORS.
ACTIVE ADDRES~ BITS IN SERIES 200 PROCESSORS,
4-15
ADDRESS ASSIGNMENTS AND UNIT LOADS AVAILABLE IN
SERIES 200 PROCESSORS, 1-19
SET
" ADDRE5s MODE-ADMODE. 7-11
(CONT.>
COMPUTER~GENERAIED
SET (CON r.)
" ITEM MAR(-Sl. 8-4~
" LINE NUMBE~-SETLIN, 7-18
" OUT-Of-SEQJENCE BASE-XBASE, 7-18
" WORD MAR("'Sw, 8-48
" 1 PUNCTUATION INDICATORS. 5-7
" 11 PUNCTJAflON INDICATORS (EASyeUDER C AND D ONLY>,
5"'7
SETT INCJ
LW
S!:.lTIN~.
CORRESPONDENCt BETwEEN LIB SEITING AND BARRICADE
LOCATION, 8... 80
SIGN CONVENT IONS
DECIMAL ARITHMETIC SIGN CONVENTIONS, 8-9
DIVIDE SIGN CONVENTIONS, 8-13
MULTIPLY SIGN CONVENTIONS, a ... 10
SIGNAL C,t:.NERATED
INTERRUPT SIGNAL bENERATED BY PERIPrlERAL CONTROL.
D~6
SIGNS
ALGEBRAIC SIGNS IN DECIMAL ADDllI0N. 8-1
SIMUL.TANEITY
PERIPHERAL SIMULTANEITY, 1-6
SI"1ULTANEOUSLY
INDEX REGISTERS SI~ULTANEOUSLY.
NUMBER OF INDt:.X REGISTERS SIMJL.JANEOUSLY
AVAILABL.E TO A PROGRAM. 4-10
SIZE
MAIN MEMORY SIZE. -1-6
" Of CONTROL MEMORY REGISTERS (MODEL.S
200/1200/1250/2200/4200).2-7
SK IP-SK IP. 7 .. 15
SOURCE
RELATIONSHIP OF SOJRCE. ASSEMBL.ER. AND OBJECT
PROGRA"1. 5-2
SPECIAL CHARACTERS IN MeE INSTRUCTION. 8-105
SPEEI)
MAIN MEMURY SPEED. 1-6
" PRIIHtRS.
HIGH SPEED PRINTERS. 1-8
SR
SEQUENCE REGISTER (SR). 4-3
STANDARD PROCESSING MODE, 1-3
STATtMENTS
ASSt:;;M~LY CONTROL STATEMENTS. 7-1
DATA FOR~ATTING STATEMENTS. 6-1
STORAGE
II LOCATlON5,
CONSECUTIVE STORAGE LOCATION~ IN MAIN MEMORY.
3 .. 4
MAGNETIC CORE STORAGE.
R£PRESENTION OF CHARACTER~ IN MAGNETlC CORE
STORAGE. 2... 3
"PROTECT. 1-23
" PROTECT FEATURE. E.1
" PROTECTION,'
STORAGE PROTECTION WITH BASE RELOCATION, G-l
VIOLATIONS OF STORAGE PROIEeTIUN, £-3
STORE
" CONTRUL REGISTERS-SCR, 8-58
" INDEXIBARRICADE REGISTER-SIB, 8-82
" VARIANT AND INDICATORS-SVI. 8-92
STORED
CONTROL RE~ISTER CONTENTS STORED BY SCR INSTRUCTION.
8 .. 58
CONTROL. REGISTERS STORED BY S'R INS1HUCTION. 8-59
INfORMATION STORED BY SVI INSTRUCTIONS. 8-92
SUBSTITUTt:.~SST' 8-30
SUBSYSTEM
TYPE 4201 MEMORY SUBSYSTEM. 2-4
SUBTRACT UPERATIONS
SERIES 200 ADD ANI) SUBTRACT OPERATIONS. 8-4
SUBTRACT"'~S
BINARY SUBTRACT-BS. 8-19
SUBTRACT-S. 8 .. 16
SUBTRACT .. ZS
ZERO AND SUBTRACT-ZS. 8-22
SUBTRACTION
BINARY SUBTRACTION. 8-4
DECIMAL SU8TRACTION, 8-8
SUFflX .. SFX, 7 .. 15
SUMMARY. 3-3. 3... 6. 4.. 4
INSTRUCTION SUMMARY, C-1
" OF CENTRAL PROCES~OR CHARACTERISTICS, 2-17
" Of INTERNA~ DATA FORMATS. 3-6
" OF lNTERRUPT/ALLOW fUNCTION CONTROL AND TEST
OPERATIONS. D-7
(CONT.)
INDEX
SUMMARY (CUNT.)
" OF PCS 1/0 CONTROL CHARACTERS FOR TYPE 286. 8-146
" OF PCB 1/0 CONTROL CHARACTERS. 8-130
" OF P~T 110 CONTROL CHARACTERS FOR TYPl 286 MULTI
CHANNEL. 8-126
" OF PDT 1/0 CONTHOL CHARACTERS, 8~120
" OF SCIENTIFIC INSTRUCTIONS. F-4
SUMMARY-TIMING FORMULAS MODELS 200
INSTRUCTION SUMMARY-TIMING FOR~ULAS MODELS 200.
1200, 12~0. AND 2200. C.4
SVI INSTRUCTIONS
INFORMATION STORED BY 5VI INSTRUCTIONS. 8-92
SWITCH CONDITIONS
BRANCH ON CONDITION TEST (BCT) SENSE SwITCH
CONDITIONS. B-3
SENSE SWITCH CONDITIONS FOR BCT INSTRUCTION. 8-36
SYMBOLIC. ~"13
" ADDRESS .. I.)SA.
DEFINE SYMBOLIC ADDRESS-DSA. 6-7
" LANGUAGE. 5... 3
" REPRESENTATION.
SYM~OLIC REPRESENTATION OF INPUT/OUTPUT TRAFFIC
COIHROL. 2-15
SYMBOLIC REPRESENTATION OF SERIES 200
INSTRUCTIONS. 3-4
" TAGS.
CONVERSION OF SYMBOLIC TAGS TO ABSOLUTE MEMORY
ADDRESSES. 3.. 2
SYMBOLOGY. F.. 2
" USED IN SERIES 200 INS1RUCTION DESCRIPTIONS. 8-2
TABU::
BINARY ADDITION TABLE. 8-4
DECIMAL-OCTAL CONVERSION TABLE. A-2
" LOOKUP~TLU. a... 83
MISCELLANEOUS TABLES. 8-1
TAGS
SYMBOLIC TAGS,
CONVERSION OF SYMBOLIC TAGS TO ABSOLUTE MEMORY
ADDRESSES. 3... 2
TAPE
" DATA FORMAT.
MAGNETIC TAPE DATA FORMAT. 3-7
" EGlUIPMENT,
PAPER TAPE EQUIPMENT. 1-12
MAGNUIC TAPE,
CHARACTER REPRESENTATION ON MAGNETIC TAPE. 3-7
DATA FORMAT ON MAGNETIC TAPE. 3-a
" PUNCH.
C3 CODING FOR TYPE 210 PAPER TAPE PUNCH, 8-124
" READERS.
C3 CODING FOR TYPE 209 AND 209-2 PAPER TAPE
READERS. 8.. 124
" UNIl~.
MAGNETIC TAPE UNITS. 1-8. 1-9
TELLER TERMINAL EQUIPMENT. 1~16
TERMINAL EWUIPMENT
TELLER TERMINAL EQUIPMENT, 1"16
TEST
CONDI TION n:ST,
BRANCH ON CONDITION Tt:.ST (BCT) INDICATOR
CONDITIONS. 8 .. 4
bRANCH ON CONDITION TEST (BCT) SENSE SWITCH
CONDITIONS. 8-3
" CONDlTIONS.
bASIc TEST CONDITIONS FOR BCC INSTRUCTION. 8~40
Bec TEST CONDITIONS wITH ADVANCED PROGRAMMING
INSTRUCTIONS. 8-41
INDICATOR lEST CONDITIONS FOR BeT INSTRUCTION.
8-37
" OPERATIONS.
SUMMARY OF INTERRUPT/ALLOW FUNCTION CONTROL AND
TEST OPERATIONS. D.7
TYPES OF TEST AND CONTROL OPERATIONS. 8.128
TEST-BCT
CONDITION TEST.BCT,
BRANCH ON CONDITION TEST-BCT. 8-35
THREE-CHARACTER
" ADDR~5SING MODE. 4.6
ASSEMBLY OF INDEXED ADDRESS IN THREE-CHARACTER
ADDRESSING MODE. 5-22
ASS~MBLY OF INDIRECT ADDRESS IN THREE.CHARACTER
ADDRESSING MODE. 5-23
INDEX REGISTER ADDRESSES IN THREE.CHARACTER
ADDRESSING MODE, 4-12
" INDIRECT ADDRESS.
EXTRACTION OF THREE-CHARACTER INDIRECT ADDRESS.
4 ... 11
(CONT.)
COMPUTER-GENERATED INDEX
THREE-CHARAlTE~
"
(CONT.)
~ODE,
EXTRACTION OF INDEXED ADURESS 1~ 'HR~E-CHARAlTER
"1:JDE, 4-13
THREE-CHARACTER ADDRESS, 4-10
" ASSE~t:3LY. 5.. 4
TI ~EOUl
INSTRUCTION TIMEOUT, G-2
TIMING
INSTRUCTION TIMIN~5 FOR THE MUDEL 4200. C-7
" NOTES. F"'3
TLU OPERATION. 8-81
TRAft" I C CONTROL
" ACTIVITIE.S.
INPUT/OUTPUT T~AFFIC CONTROL ACriVITIES, 2-12
INPUT/OUTPUT TRAF~IC CONTROL. 2-12
LO~1CAL DECISION PERFORMED bY INPuT/OUTPUT TRA~FIC
CONTROL. 2-14
SYMBOLIC REPRESENTATION OF INPUT/OUTPUT TRAFFIC
CONTROL. 2-15
TRANSFER
" CAPABILITY.
8-BIT TRANSFER CAPABILITY. G-3
" INTERVALS,
DATA TRANSFER INTERVALS DURIN~ JNE PERIPHERAL
OPERATIO"!, 2-13
" OPERATION,
PERIPHERAL DAfA TRANSFER OPERATION. 1-17
" RATE.
DEVICE DATA TRANSFER RATE. 8-L10
8-BIT TRANSFER.
EXTENDED MULTI-PROGRAMMIN~ ANV ti-BIT TRANS~ER.
1-23
TRANSFER-XFR. 7-~
TRANSFER/PDI
PERIPHERAL DATA TRANSFER/PD1. 8-1l5
TRANSLATE-MAT
MOVE AND TRANSLATE-MAT, 8-70
TRANSLATt:-MIT
MOVE ITEM AND TRANSLATE-MIT. 8-74
TRAPPING MODE
ITEM.MARK TRAPPING MODE. 1~5
TREATMENT O~ ADD~ESSES LARGER THAN A MEMO~Y.S MAXIMUM
ADDRESS. 4-16
TRUE ADD. 8.. 1
" EXAMPLES. 8.. 7
TWO"CHARACTER
" ADDRESS ASSEMBLY, 5-3
" ADDRESSING MODE. 4-5
TYPE
" (CARD COLUMN 6). ~-6
TYPES OF TEST AND CONTROL OPERATIONS. 8-128
" 1201 CONTROL PANEL. 1-2
" 209,
C3 CODING FOR TYPE 209 AND 209-2 PAPER TAPE
~EADERS. 8.. 124
" 210 PAPER TAPE PUNCH,
C3 CODING FOR TYPE 210 PAPER TAPE PUNCH. 8-124
" 220-1 CONSOLE. 1.. 3
" 220-3 CONSOLE. 1-3
" 237 BILL FEED PRI~TER,
C3 CODING FOR TYPES 206 AND 222 PRINTERS AND
TYPE 237 BILL FEED PRINTER. 8-125
" 270A RANDOM ACCESS DRUM.
C3 CODING FOR TYPE 270A RANDOM ACCESS DRUM.
8 .. 125
" 28~,
SUMMARY Of PC~ 1/0 CONTROL CrlARACTERS FOR TYPE
286. 8-146
" 286 ~ULTI CHANNEL.
SUMMARY OF PDT I/O CONTROL CHARACTERS fOR TYPE
28~ MULlI CHANNEL. 8-12~
" 28~-1 ... 2, -3 LINE CONTROL INSTRUCTION5, 8-126
" 28~ ... 4.
PCB CONTROL CHARACTERS C~ THROJ~H C15 FOR TYPE
286-4. -5 LINE. 8-148
" 4201 MEMORY SUBSY~TEM, 2-4
" 4201 PROCESSOR.
MAIN MEMORY IN THE TYPE 4201 PROCE5S0R~ 2-4
MEMORy CONFIGURATIONS FOR TYPE 4201 PROCESSORS.
2-4
" 4201-9 CENTRAL PROCESSOR.
MODEL 4200 MEMORY INTERLEAVIN~ (TYPE 4201-9
CENTRAL PROCESSOR). 2-6
TYPES 206
C3 CODING FOR TYPES 206 AND 222 PRI~IERS AND TYPE
237 BILL FEED PRINTER. 8-425
TYPICAL (CONT.)
TYPICAL
" ADD hlSTRUCl iON. 4-1
LXTRACTION OF DATA FIELDS IN TYPICAL AUD
lI~!:)TRUCTION. 4-2
" COMMUNICATIO~S NETWORK.
CUSTOMER INQUIRY HANDLING VIA TYPICAL
COMMUNICATIONS NETWORK. 1-15
" CONTkOL REGISTER FUNCTION. 2-7
UNIT
" ACTIVITIES,
CONTROL UNIT ACTIVITIES. 2~11
ARITHMETIC UNIT. 2-10
UATA FLOW ~ETWEEN MAIN MEMORY AND ARITHMETIC
UNIT. 2-11
CJNTHOL UNIT, 2-11
INFORMATION UNITS.
~XT~NDED OF INFORMAl ION UNITS IN MIT OPERATION,
8-i5
LDAU!;) ,
ADDITIONAL READ/WRITE CHANNELS. UNIT LOADS. AND
ADDRESS ASSIGNMENTS. 1-22
ADDRESS ASSIGN~ENT~ AND UNIT LOADS AVAILABLE IN
SERIES 200 PROCESSORS. 1-19
PERIPHERAL ADDRESSES AND UNIT LOADS. 1-17
MAGNETIC TAPE UNITS, 1-8. 1-9
PRoCESSING UNIT. 2-5
RANDOM ACCESS DRUM UNITS. 1-11
SCIE~TIFIC UNIT. 1-23
SCIENTIFIC UNIT FOR MODEL!:) 1200. 1250. 2200, AND
4200. F-1
uPWARD COMPATIBILITY. 8-114
UTILIZING ESCAPE CODES
EXAM~lE OF OPERATION UTILIZING ESCAPE CODES. 8-114
VARIABLE fIELD LENGTH. 3-1
VARIABLE-SPEED READ/WRITE CHANNELS
MODEL 4200 VARIABLE-SPEED READ/WRITE CHANNELS. 2-16
VARIANT
" CHARACTER. 3-3. 5-20
MODES SPECIFIED BY VARIANT CHARACTER IN CAM
INSTRUCTION. 8-63
RESTORE VARIANT AND INDICATORS.RVI. 8~95
SCAN VARIANTS.
MOVE OR SCAN VARIANTS. B.9
STORL VARIANT AND INDICATORS-SVI. 8.. 92
VIOLATIONS OF STORAGE PROTECTION. E.. 3
VISuAL INFORMATION PROJECTION DEVICES. 1-14, 1-16
wORD
II
MARK,
(LEAR WORD MARK .. CW. 8-50
MARK-DCW';
DEFINE CONSTANT WITH WORD ~ARK-DCW. 6-2
II
MARK-LCA.
LOAD CHARACTERS TO A-fIELD WORD MARK-LCA. 8-56
" MARK-MCw.
MOVE CHARACTERS TO WORD MARK-MCW. 8-55
" IviARK-Sw.
~ET WORD MARK-SW. 8-48
ZERO
" AND ADD-ZA. 8-20
" AND SUBTRACT-ZS. 8-22
0191
FEATURE 0191, 1-23
II
1.. 5
CARD NUMBER (CARD COLUMNS 1-5), 5-5
1116
FEATURE 1116. H-1
1200
BPI RECORDING DENSITY. 1-8
INSTRUCTION SUMMARY-TIMING FOR~ULAS MODELS 200,
1200. 1250. AND 2200. C-4
MODELS 1200.
SCIENTIFIC UNIT FOR MODELS 1200. 1250, 2200. AND
4200. Fool
1201 CONTROL PANEL
TYPE 1201 CONTROL PANEL. 1-2
1250
INSTRUCTION SUMMARY-TIMING FORMULAS MODELS 200.
1200. 1250. AND 2200. (-4
SCIENTIFIC UNIT FOR MODELS 1200. 1250. 2200, AND
4200. Fool
II
OPERATION COOt: (CARD COLUMNS 15-20). 5-10
200
" ADD.
II
SERIES 200 ADD AND SUBTRACT OPERATIONS. 8~4
ADvANCED PROijRAMMING FEATURE.
MODEL ZOO ADVANCED PROGRAMMING FEATURE, 1_21
(CONT.)
COMPUf~R-G~NERATED
200 (CONT.>
".CENTRAL ~ROCE5S0R,
LOGICAL OIVlSI~N Of SERIES 200 ~ENTRAL
PROCESSOR. 2-1
" CHARACTER CODES,
S~RIES ZOO CHARACTER COUE5, B-7
" COMPONENTS.
SERl~S ZOO COMPONENTS, 1-1
" INU~X REGISTER MAP,
SERIES 200 INDEX REGISTER MAP, 4-9
" INSTRUCTION DESCRIPTIONS.
SYMBOLOGY USED IN SERIES 200 IN~rRUCIION
DESCRIPTIONS. 8.2
" INSTRUCTION FORMAT.
SERIES ZOO INSTRUCTION FORMAT 1. 4-17
SERIES ZOO INSTRUCTION FORMAT 2. 4-18
SERIES ZOO INSTRUCTION FORMAT 3. 4-18
SERIES 200 INSTRUCTION FORMATS. 3-3
INSTRUCTION SUMMARY-TIMING FORMULAS MODELS 200.
1200. lZ50. AND 2200, C-4
" INSTRUCTIONS.
SYMBOLIC REPRESENTATION Of SERIES 200
INSTRUCTIONS. 3-4
" OPTIONAL FEATURES.
S~RIES 200 OP110NAL FEATURES. 1-20
" PERIPHERAL DEVICES,
MINIMUM RwC CAPACITY REQUIREMENfS FOR SERIES 200
PERIPHERAL DEVICES. 8-111
" PROCESSORS.
ACTIVE ADDRESS BITS I~ SERIES 200 PROCESSORS.
4 ... 15
ADDRESS ASSIGN~ENTS AND UNIT LOADS AVAILABLE IN
SERlES 200 PROCESSORS, 1-19
4200. F-l
222 PRINTERS
C3 CODl~G FOR TYPES 206 AND 222 pRINTERS AND TYPE
237 BILL FEED PRINTER. 8-125
237 BILL FEED PRINTER
(3 CODING FOR TYPES 206 AND 222 pRINTERS AND TYPE
~37 BILL FEED PRINTER. 8-125
270A RANDOM ACCESS DRUM
C3 CUDING FOR TYPE 270A RANDOM ACCESS DRUM. 8-125
286
" MJLTI CHANNEL.
SUMMARY OF PDT 1/0 CONTROL CHARACTERS FOR TYPE
286 MULTI CHANNEL. 8-126
TYPE 286.
SUMMARY OF PCB 110 CONTROL CHARACTERS FOR TYPE
286. 8-146
TYPE 286-1. -2. -3 LINE CONTROL INSTRUCTIONS. 8-126
TYpE 286-4.
4200
200/1200/1250/2200/4200
SIZE OF CONTROL MtMORY REGISTERS (MODELS
20 0 /1200/1250/2200/4200),2-7
206
209
TYPES 206.
C3 CODING FOR TYPES 206 AND 222 PRINTERS AND
TYPE 237 BILL FEED PRINTER. 8-125
TYPE 209.
C3 COOING FOR TYPE 209 AND209~2 PAPER TAPE
READERS. 8-124
209.2 PAPtR TAPE READERS
C3 COUING FOR TYPE 209 AND Z09-2 PAPEK TAPE REAvERS,
8-124
210 PAPER TAPE PJNCH
C3 CODING FOR TYPt 210 PAPER TAPE PJNCH. 8-124
220 .. 1 C;:ONSOLE
TYPE 220wl CONSOL~. 1-3
220-3 CONSOLE
TYPE 220-3 CONSOLE, 1~3
2200
INSTRUCTION SUMMARY-TIMING FORMULAS MODELS 200.
1200. 1250. AND 2200. C~4
SCIENTIFIC UNIT FOR MODELS 1200. 1250. 2200, AND
INDlX
4201
PCB CONTROL CHARACTERS C5 THROUGH (15 FOR TYPE
286~4. -5 LINE, 8~148
" MEMORY INTERLEAVING.
MODEL 4200 MEMORY INTERLEAVING (TYPE 4201.9
CENTRAL PROCtSSOR). 2-6
MODEL 4200.
lXTENOED INPUTIOUTPUT CAPACITY FOR THE MODEL
4200, H-l
INSTRUCTION TIMINGS FOR THE MODEL 4200, C.7
SCIENTIFIC UNIT FOR MODELS 1200, 1250, 2200. AND
4200, F-l
" VARIABLE-SPEED READ/WRlTE CHANNELS.
MODEL 4200 VARIABLE-SPEED READIWRITE CHANNELS.
2 ... 16
" MEMORY SUBSYSTEM,
TYPE 4201 MEMORY SUBSYSTEM. 2~4
" PRoCESSOR,
MAIN MEMORY IN THE TYPE 4201 PROCESSOR. 2"4
MEMORY CONFIGURATIONS FOR TYPE 4201 PROCESSORS,
2-4
4201-9 CENTRAL PROCESSOR
MODEL 4200 MEMORY INTERLEAVING (TYPE 4201-9 CENTRAL
PROCESSOR). 2... 6
4214A
FEA1URES 4Z14A AND 42148. H--l
4214B
FEATURES 4214A AND 42148. H.. l
4215
FEATURE 4215. H~l
a-BIT TRAN5FER
CAPAEiILITY.
(J-3
"
EXTeNDED MULTI.PROGRAMMING AND 8-BIT
8-14
LOCATION (CARD COLUMNS 8-14).5-8
Honeyw-ell
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TECHNICAL PUBLICATIONS REMARKS FORM
DATED:
TITLE: SERIES 200
PROGRAMMERS' REFERENCE MANUAL
(MODELS 200/1200/1250/2200/4200)
OCTOBER; 1968
FILE NO: 113.0005. 0000.
2~139
ERRORS NOTED IN PUBLICATION:
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SUGGESTIONS FOR IMPROVEMENT TO PUBLICATION:
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(Please Print)
FROM: NAME _ _ _ _ _ _ _ _ _ _ _ _....--_ _ __
COMPANY ______________________
TITLE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___.__.
ADDRESS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
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DATE _ _ _ __
----------------,~-------------------------------------
PERMIT NO. 39531
NEWTON HIGHLANDS
MASS.
AlliN: MAR)
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