Intel Intellec 8 Mod 80 Reference Manual Feb75

Intel_Intellec_8_Mod_80_Reference_Manual_Feb75 Intel_Intellec_8_Mod_80_Reference_Manual_Feb75

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tel INTEL

CORP . 1974

INTRODUCTION
GENERAL DESCRIPTION
SPECI FICA TlONS
THE SCOPE OF THIS MANUAL

v
v
v
vi

CHAPTER 1
THE INTELLEC® S/MOD SO SYSTEM OVERVIEW
FUNCTIONAL DESCRIPTION OF MODULES
FRONT PANEL CONSOLE OPERATIONS
MEMORY REFERENCE OPERATIONS
Memory Read Operations
Memory Write Operations
INPUT/OUTPUT OPERATIONS
I nput Operations
Output Operations
Teletype Operations
INTERRUPT OPERATIONS
PROM PROGRAMMING OPERATIONS

1
1
2
2
2
2
2
3
3
3
3
3

CHAPTER 2
THE immS-S3 CENTRAL PROCESSOR MODULE
THE FUNCTION OF A CPU
The Computer System
The Architecture of a CPU
FUNCTIONAL ORGANIZATION OF THE
CENTRAL PROCESSOR MODULE
SOSO EIGHT-BIT PARALLEL CENTRAL
PROCESSOR UNIT
Architecture of the SOSO CPU
The Processor Cycte
I nterrupt Sequences
Hoi d Sequences
Halt Sequences
Start-up of the SOSO CPU
PERIPHERAL LOGIC
Timing Logic
Instruction Fetch
Memory Reference Operations
Memory Read and Memory Write
I/O Operations

5
6
6
7
11
14
15
17
22
23
24
24
25
25
26
26
29
29

Interrupt Cycle
Hold Operations
Reset
Programmed Display
UTILIZATION
Installation
Pin List

32
32
33
33
33
33
34

CHAPTER 3
THE immS-61 INPUT/OUTPUT CARD
THE immS-61 INPUT/OUTPUT CARDGENERAL FUNCTIONAL DESCRIPTION
The Functional Units
Module and Port Select Operations
Input Operation
Output Operation
Teletype Input Operation
Teletype Output Operation
THE immS-61 INPUT/OUTPUT CARDTHEORY OF OPERATION
Module Selection
I nput Operations
Output Operations
Teletype Communications
immS-61 INPUT/OUTPUT CARDUTILIZATION
User-Available Options
I nstatlation Data
Teletype Modifications

44
44
45
45

CHAPTER 4
THE immS-63 OUTPUT CARD
GENERAL FUNCTIONAL DESCRIPTION
DETAILED FUNCTIONAL THEORY

49
49
49

Module Decoding
Port Decoding
Output Operations
CARD UTI LlZATlON
User Options

39
39
40
40
40
40
40
41
41
41
41
43
43

49
49
51
51
51

CHAPTER 5
THE imm6-28 RANDOM ACCESS MEMORY CARD
THE imm6-28 RANDOM ACCESS MEMORY
CARD -GENERAL FUNCTIONAL DESCRIPTION
The Four Functional Units
Memory Addressing Operations
Memory Write Operations
Memory Read Operations
THE Imm6-28 RANDOM ACCESS MEMORY
CARD-THEORY OF OPERATION
Physical Memory Implementation
Memory Address Decoding
Memory Read Operations
Memory Write Operations
THE imm6-28 RANDOM ACCESS MEMORY
CARD -UTI LlZATION
Memory Address Coding
I nstallation Data and Requirements
CHAPTER 6
THE imm6-26 PROGRAMMABLE READ-ONLY
MEMORY CARD
THE imm6-26 PROGRAMMABLE READONLY MEMORY CARD -GENERAL
FUNCTIONAL DESCRIPTION
The Four Functional Units
Memory Read Operation
THE imm6-26 PROGRAMMABLE READONLY MEMORY CARD -THEORY
OF OPERATION
Physical Memory Implementation
Memory Address Decoding
Memory Read Operations
Random Access Enable
THE imm6-26 PROGRAMMABLE READONLY MEMORY CARD -UTI LlZATION
Memory Address Coding
PROM Installation, Removal,
Programming and Erasure
Installation Data and Requirements
CHAPTER 7
THE INTELLEC 8/MOD 80 CONTROL CONSOLE
THE INTElLEC 8/MOD 80 CONTROL
CONSOLE-FUNCTIONAL DESCRIPTION
Data Display Operations
Manual Memory Access Operations
Manual I/O Access
Interrupt Operations
Sense Op~rations
Search-Wait Operations
Processor Control Operations
THE INTELLEC 8/MOD 80 FRONT PANEL CENTRAL CONSOLE-THEORY OF OPERATION
Data Display Operations
Manual Memory Access Operations
Manual I/O Access Operations

70
70
71
71

I nterrupt Operations
Sense Operations
Search/Wait Operations
Processor Control Operations

53
53
53
53

CHAPTER 8
THE CHASSIS, MOTHER BOARD,
AND POWER SUPPLIES

54
54
54
54
54

75

CHAPTER 9
THE imm6-76 PROM PROGRAMMER MODULE
THE 8702A PROGRAMMABLE
READ ONLY MEMORY
FUNCTIONAL DESCRIPTION
OF THE MODULE
Interface To The INTELLEC 8/MOD 80
THEORY OF OPERATION OF THE MODULE
Data Distribution
Control and Timing
Power Supply
UTILIZATION
Installation
Power Requirements
Pin List

56
56
56
56
57

59

59
59
59

77
77
78
78
80
80
81
81
83
83
83
83

CHAPTER 10
THE INTELLEC 8/MOD 80 SYSTEM UTILIZATION
INTELLEC 8/MOD 80 INSTALLATION
SYSTEM I/O INTERFACING
INTELLEC 8/MOD 80 SYSTEM
OPERATING REQUIREMENTS
EXTERNAL DEVICE CONTROLLER
INTERFACING

60
60
60
60
61

87
87
87
87

91

61
61
62
62

APPENDIX A
INSTRUCTION SET SUMMARY

65
65
65
66
67
67
67
67
68

APPENDIX B
ELECTRICAL CHARACTERISTICS OF
LOGIC ELEMENTS USED IN THE
INTELLEC 8/MOD 80 SYSTEM

APPENDIX C
ASCII TABLE

68
68
70
70

APPENDIX D
BINARY-DECIMAL-HEXADECIMAL
CONVERSION TABLES

ii

VII

XIX

XXXXI

XXXXIII

1-1

A Simplified INTELLEC® 8/MOD 80
Block Diagram

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16

Program Jump
CPU Module Functional Block
8080 CPU Package Configuration
8080 CPU Functional Block Diagram
rP1' rP2 and SYNC Timing
State Transition Diagram
Typical Fetch Machine Cycle
Interrupt Timing
Hold Operation (Read Mode)
Hold Operation (Write Mode)
Halt Timing
Oscillator-Counter Timing
Timing Generator
PROM Memory Synchronization Timing
RAM Memory Synchronization Timing
imm8-83 Central Processor Module
Schematic Diagram
I/O Functional Block Diagram
I/O Module Schematic Diagram
I/O Module Timing
Relay Circuit (Alternate)
Distributor Trip Magnet
Mode Switch
Terminal Block
Current Source Resistor

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8

3-9
3-10

TTY Modification
Teletype Layout

47
46

8
12
15
16
17
20
21
22
23
24
25
26
27
28
29

4-1
4-2
4-3

Output Module Functional Block Diagram
Output Module Schematic Diagram
Output Module Timing

49
50
51

5-1
5-2
5-3

RAM Module Functional Block Diagram
RAM Memory Module Timing
RAM Memory Module Schematic Diagram

53
54
55

6-1
6-2
6-3

PROM Memory Module Functional
Block Diagram
PROM Memory Module Timing
PROM Memory Module Schematic Diagram

59
62
63

7-1
7-2

Front Panel Logic Schematic Diagram
Front Panel Controller Schematic Diagram

73

30

8-1

INTELLEC® 8/MOD 80 Module Assignments 75

39
42
43
44
44
45
45
46

9-1
9-2
9-3
9-4

PROM Programmer Schematic Diagram
PROM Programmer Timing
Power Supply Functional Block
Voltage Regulator Loop: Simplified
Schematic Equivalent

79
80
81

INTELLEC 8/MOD 80 Rear Panel

88

10-1

iii

72

82

i-1

INTELLEC® 8/MOD 80 Specifications

vi

4-1

imm8-63 Addressing Options

51

2-1
2-2
2-3
2-4

8080 Status Hit Definitions
State Definitions
CPU Module: D.C. Signal Characteristics
CPU Module Output Connector

19
22
34
35

9-1
9-2
9-3
9-4

Pl
Jl
J2
J3

84
85
85
85

3-1

Port Addresses Enabled by
I/O Module Jumpers

41

10-1
10-2

iv

Pin
Pin
Pin
Pin

List
List
List
List

I/O Port Assignmenw-Module I/O 0
110 Module To Back Panel Interface Chart

89
91

GENERAL DESCRIPTION

SPECIFICATIONS

The INTELLEC® S/MOD SO system (imm8-84A) is
a low-cost computer system, designed to simplify the
development of microcomputer systems which employ
INTEL SOSO microprocessors.

The INTELLEC S/MOD SO system is made up of
separate modules, each of which performs a different task in
making up a complete system. These modules are:
1) The immS-S3 Central Processor Module, which op·
erCltes as the Central Processor for the INTE LLEC
S/MOD SO system. In this capacity, it performs the
following fuctions:

The INTELLEC S/MOD SO system uses the SOSO as its
central processing unit. The SOSO has a basic cycle time of
2.0 microseconds. The system contains a control co~s~le
and provides read-write program memory as a substitute for
read-only memory. Thus the SOSO chip can be accessed via
the control console, and programs can be debugged before
being enabled in read-only memory. Turn around time from
initial system concept to finished product is shortened, and
systems development costs are thus reduced.

a) It controls the execution of program instructions, sending the appropriate control signals to
the other modules which make up the INTELLEC S/MODSO system.
b) It performs all of the necessary arithmetic, logi·
cal, and data manipulation operations necessary
for program operation.
c) It controls overall system timing.

The INTE LLEC 8/MOD 80 system has its own power
supply, cabinet, display and control panel, 8192 bytes (8K)
of Random Access Memory, a Programmable Read-Only
Memory Module with 4K capacity, a PROM Programmer
Module, and an Input/Output Module which contains four
S-bit input ports and four S-bit output ports as well as
provision for serial communications interface.

2) The imm6-2S Random Access Memory Module,
which provides 4,096 S-bit words of Read/Write
memory for system use. As many as four cards can
be used in a system, for a memory capacity of 16K.
3) The imm6-26 Programmable Read-only Memory
Module, which provides up to 4,096 words of Readonly memory in increments of 256 words, and
which may be operated in parallel with the system
Random Access Memory. Again, more than one
card may be used, giving a total Read-only memory
capacity of 16K words.

The Bare Bones SO is an INTE LLEC S/MOD SO system
without the power supply, display and control console, or
cabinet, and is designed for 4K of RAM memory, rack·
mounting.
Both the INTELLEC S/MOD SO system and the Bare
Bones SO can be expanded up to 16K bytes of memory; in
addition, the I/O capability can be expanded to support sixteen input ports and sixteen output ports, or four input
ports and twenty-eight output ports.

4) The immS-61 Input/Output Module, which pro- .
vides four eight-bit input ports and four eight-bit
output ports for system Input/Output operations.
Two of the input ports and two of the output ports

The standard software for the INTELLEC S/MOD SO
system includes a resident System Monitor, a Text Editor,
and an Assembler. In addition to these INTE LLEC S/MOD
SO resident programs, there are three development programs
available, which are designed for operation on LARGE·
SCALE HOST COMPUTERS. These are a macro cross·
assembler, a microcomputer simulator (lNTERP/80), and a
pL/MT.M·compiler: PL/M is a high-level language that can
"horten program development time significantly.

may be used with integral Teletype communications circuits to provide Teletype I/O. Up to four
of these cards may be used in a system, giving a
total of sixteen input ports and sixteen output
ports.
5) TheimmS-63 Output Module, which provides eight
latching output ports for system Output operations.

v

relating to setting-up and operating the INTELLEC 8/MOD
80 system is contained in Chapter 10 of this manual, and in
the INTE LLEC 8/MOD 80 Operator's Manual.

Up to three of these cards may be used in a system, giving a total capability of twenty-four output
ports.
6) The imm6-76 PROM Programmer Card, which gives
the INTE LLEC® 8/MOD 80 system the capability
of programming INTE L 8702A Programmable
Read-Only Memory chips.

THE SCOPE OF THIS MANUAL
This manual provides an understanding of the design
concepts and capabilities of the I NTE LLEC 8/MOD 80
system as a whole and its individual modules, and in addition
provides detailed theory of operation and implementation
information for each module_

7) The Front Panel Controller and Display Console,
wh ich provides a means of controlling program execution, program debugging, and INTELLEC 8/
MOD 80 operation. It also provides displays of system status and information.

For a detailed description of INTELLEC 8/MOD 80
operating procedures, including software operation, see the
INTELLEC 8/MOD 80 Operator's Manual. For a detailed
examination of programming at an elementary level, suitable
for an engineer with no previous programming experience,
see the 8080 Assembly Language Programmer's ManuaL

8) The chassis and power supplies.
A summary of the specifications for the INTE LLEC
8/MOD 80 system is given in Table ;-1. Specific information

rNTELLEC 8/MOD 80 Specifications

SPECIFICATIONS
Word Length

8-bits

Registers

Seven 8-bit general purpose registers, two of which are used to hold Memory
Addresses during Memory Reference operations, and one used as the
accumulator.

Instruction Set

Seventy-eight instructions, including Memory-index register, index-registermemory, register-to-register, single register, immediate, and memory arithmetic
and logic instructions, as well as conditional and unconditional branch instructions, input/output, and machine instructions.

Arithmetic

8-bit parallel, binary, fixed point, two's complement.

Memory

8192 8-bit words, ReadIWrite; 4096 8-bit words, Read-only. (Expandable to
16,384 words_l

Addressing

Direct - up to 16K bytes. (up to 64K using external enclosures}

Cycle Time

2.0 microseconds

Environment

0° - 55° C.

Power Requirements

5V @ 12 A (max); 6 A (typ);
-9V @ 1.8 A (max); 0.5 A (typ);
-12V @0.03A (max); 0.016 A (typ);
(More power may be required tor expanded INTELLEC 8/MOD 80 systems.)

AC Requirement

60 Hz; 115 VAC, 200 Watts

Size

INTELLEC 8/MOD 80: 7" x 17 1/8" x 1/4"
Bare Bones 8: 6 3/4" x 17" x 12" (suitable for standard R ETMA 7" x 19"
panel space).

Weight

30 lb.

Table i-1_

vi

The INTELLEC 8/MOD 80 microcomputer development system consists of six independent functional
modules and a power supply, housed in a single chassis and
enclosure_ This section describes the interrelationship of the
INTELLEC 8/MOD 80 functional modules, and shows the
part played by each module during typical operations_

r-

FRONT PANEL
CONSOLE

-

-

0

Z
-I

-I

:;)
ID

m

:II
:II

>
a:

e"'0

0

~~
:;;
,....- t - -

MEMORY
(RAM, PROM)

+-- r=-

;: :II
m 0
;: r0

:II

-<
»

'"e

'"

0
0
m

:II

en
en

zen en'"e
-I

0

....
....«
«
c

e

-I

"'0

'--

-----t

CPU

r

e

ports. A serial communications facility, which the
INTELLEC 8/MOD 80 system uses for teletype
interface, is included in each module.

-I

-

DATA INPUT
BUS

INPUT/OUTPUT
MODULE

1) A Central Processing Unit (CPU) which performs
arithmetic, logical and data manipulation operations.

3) Input/Output module. Physically there can be up to
four Input/Output modules in an INTELLEC
8/MOD 80 system. Each Input/Output. module
provides four individually addressable 8-bit output

0
e »
C'l -I
-I »
0 0
z
:II

f--

Figure 1-1 illustrates the six functional modules of the
INTELLEC 8/MOD 80 system, and shows interconnecting
busses. The six functional modules are:

2) Memory module, which can be Programmable
Read-Only (PROM), Random Access (RAM), or a
combination of the two. Though Figure 1-'
illustrates memory as a single module, it can be
physically implemented as one or more modules,
depending on the amount of memory included in a
system. The memory module provides data and
program storage; a standard system includes two 4K
RAM modules and one 4K PROM module.

C'l

Z

'"

FUNCTIONAL DESCRIPTION OF MODULES

OUTPUT
MODULE

I
PROM
PROGRAMMER
MODULE

4) Output module. Physically there can be up to three
Output modules in an INTELLEC 8/MOD 80
system. Each Output module provides eight
individually addressable 8-bit output ports.
5) A Front Panel Display and Control Console. The

Console provides a means for manually monitoring
and controlling INTELLEC 8/MOD 80 operations.
6) PROM Programmer Module. This module provides a
timing and level shifting circuitry for programming
INTEL's 8702A PROMs.

The functional units of the INTELLEC 8/MOD 80
system are interconnected by the following busses:

Figure 1·1. A Simplified INTELLEC 8/MOD 80 Block
Diagram.

Bus (a), the Memory Address bus, carries memory

addresses from the console or the CPU to the Memory,
Input/Output and Output Modules.

Although there is no direct path for data from input
ports to the console, performing an input access operation
from the console causes the input datil to be sent through
the CPU anp onto bus (c), where it is displayed on the
console.

Bus (b) the Output Data bus, carries data from the
console or CPU to the Memory, Input/Output and Output
Modules.

There is no direct link between CPU registers and the
console. The system monitor has a register interrogation
capability.

Bus (c), the data from Memory bus, carries data
from memory tothe CPU.
Bus (d), the Data Input bus, carries data from input
ports to the CPU.
Bus (e), the Interrupt Instruction bus, allows the
console to transmit a program interrupt to the CPU.

MEMORY REFERENCE OPERATIONS

Bus (f), the Control bus, is used to control instruction
execution. Since the console is connected to the control
bus, instruction execution can be controlled from the
console.

This section describes memory reference operations as
performed by the INTELLEC 8/MOD 80 system, and is
divided into two subsections.
Memory input or read
operations, and memory output or write operations.

Since the console operates in parallel to the CPU, it
contains a considerable amount of parallel logic, including
its own data and address registers; thus there are certain
states in which the CPU remains in control and the console
temporarily suspends operations, and there are other states
in which the console completely takes over machine
operations.

Memory Read Operations
A Memory Read operation is performed in order to
obtain data from a certain Jocation in the system memory,
and to bring that data to the CPU. It is performed via the
following steps:
1) The CPU sends a Memory Address to the Memory
modules on the Memory Address bus.

Conceptually, the CPU module provides the INTEL·
LEC® 8/MOD 80 system with its "computer" capabilities.
This module performs arithmetic, logical and data mani·
pulation operations as directed by a stored program.

2) The Memory modules send the data contained in
the selected memory location to the CPU on the
Memory Data Input bus.

A stored program is a sequence of numbers (eight
binary digits per number) which encode a sequence of
individual CPU operations. (Frequently an instruction code
is written as two hexadecimal digits rather than eight binary
digits). The sequence of individual instructions that
constitute a program are stored in the Memory module. If
the memory module includes Random Access Memory
(RAM), it can also be used to store temporary data that
may be generated in the course of executing a program.

The Front Panel can perform a manual Memory Read
operation by 'taking over' the Memory Data buses, and by
sending a manually entered Memory Address, rather than a
CPU·generated Address, to the memory modules.

Memory Write Operations
A Memory Write operation is performed in order to
send data from the CPU to a certain selected location in
memory. It is performed in the following steps:

Almost all computer applications require information
to be transferred between the CPU module and external
devices. Such transfers take place via the Input/Output and
Output modules.

1) The CPU sends a Memory Address to the memory
modules on the Memory Address bus.
2) The CPU sends the data which is to be stored in
memory to the memory modules on the Memory
Output Data bus.

Communications between the INTELLEC 8/MOD 80
system and an operator occur via the Front Panel Console
and teletype.

3) The CPU sends a control srgnal to the memory
modules which causes the data to be written into
the selected memory location.
The Front Panel can perform a .manual memory write
operation by taking over the Memory Address and Memory
Output Data busses, and by sending manually entered
Memory Address and Memory Data to the memory module.

FRONT PANEL CONSOLE OPERATIONS
Consider how console operations must be performed,
given the hardware organization illustrated in Figure '·1.
Since the console has its own address and data
registers, and since there is a bi·directional bus link
(through the CPU) between the console and memory; data
can be read from memory to console, and written from
console to memory.

INPUT/OUTPUT OPERATIONS
This section describes Input and Output operations as
performed by the INTELLEC 8/MOD 80 system, and is
divided into three subsections.

2

Input Operations

INTERRUPT OPERATIONS

An Input operation is performed in order to obtain
data from some external device and to bring it into the
CPU, where it can be processed. It is performed via the
following steps:

An Interrupt operation is performed when an external
device which requires servicing sends an Interrupt signal to
the CPU. This causes the CPU to interrupt its normal
operating sequence, perform the operations required by the
external device, and then return to the point at which it
was interrupted and resume normal operations. An
Interrupt operation is performed in the following steps:

1) The CPU sends an I/O Address, which specifies
which device is to be used for the Input operation,
to the Input/Output modules on the Memory
Address bus.

1) The external device sends an Interrupt signal to the
CPU. The CPU stops its normal operation and
acknowledges the interrupt request.

2) The Input/Output module responds by sending the
data which is present on the selected Input port
back to the CPU on the Data Input bus.

2) The external device sends an Interrupt Instruction
to the CPU.

An Input operation can also be performed manually
by giving the Front Panel control over the Memory Address
bus. It then sends a manually entered I/O Address and an
I/O read command to the Input/Output modL!le.

3) The CPU executes the Interrupt Instruction exactly
as if it were a normal instruction.
Usually, the Interrupt Instruction will be a RESTART
instruction. A RESTART instruction causes the CPU to
branch to a certain location in memory, where an interrupt
service routine can be stored.

Output Operations

An Interrupt operation can be performed manually
from the Control Console. In order to accomplish this, the
Interrupt Instruction is manually entered into the Front
Panel. When an Interrupt switch is depressed, the Front
Panel will generate an Interrupt signal, and will send the
manually entered Interrupt Instruction to the CPU.

An Output operation is performed in order to send
data from the CPU to an external device. It is performed via
the following steps:
1) The CPU sends an I/O address, which specifies the
device to be used for the Output operation, to the
Input/Output and Output modules on the Memory
Address bus. At the same time, the CPU sends the
data which is to be output to the Input/Output
modules on the Output Data bus.

In the basic system, only the Control Console initiates
interrupts. The ability to interrupt may be extended,
however, to the user's peripheral devices, in order to
simplify system programming and to increase system
throughput. Some modifications to the system, however,
are necessary.

2) The CPU sends an I/O write command to the
modules.
3) The Input/Output module latches the data and
sends the data which the CPU has supplied to the
selected output device.

PROM PROGRAMMING OPERATIONS

An Output operation may also be manually executed
by giving control of the Memory Address/Data Output bus
to the Front Panel. The Front Panel sends a manually
entered I/O Address and manually entered data to the
Input/ Output and Output modules.

The INTELLEC 8/MOD 80 has been designed to offer
an easy means of programming INTEL 8702A Programmable Read-Only memory chips. This is done with the
use of the PROM Programming module, and is accomplished
by performing three successive Output operations:

Teletype Operations

1) Send the address within the PROM which is to be
programmed

Teletype operations are performed in exactly the same
fashion as normal, non-teletype Input and Output
operations, with the exception that the external device used
in the case of Teletype operations is an integral Teletype
communications circuit (UART) in the Input/Output
module. Teletype data enters the Input/Output module via
input ports 0 and 1; data being sent to the Teletype
proceeds through output ports 0 and 1 on the I/O module.
Chapter 3 explains how to install the Teletype ASR33.

2) Send the data which is to be written into the
selected address
3) Send a control word which is used by the PROM
Programmer module to initiate programming
The PROM Programmer is used as the external device
for each of these Output operations. When it receives the
control word, it causes the data specified to be written into
the PROM address selected.

3

4

Five internal status flags enable conditional jumps,
calls and returns, based on carry (overflow-underflow), sign,
zero, parity, and auxiliary carry.

The immS-33 Central Processor Module is designed
specifically to serve as the central processing unit (CPU) of
the INTELLEC® S/MOD SO Microcomputer Development
System. Its general purpose architecture permits the CPU
module to perform similar functions in any eight-bit
computer system. Thus the immS-33, like the other
INTELLEC® modules, can be furnished independently on
an OEM basis. All inputs and outputs are TTL-compatible,
to simplify the external interface.

The Central Processor Module contains a crystalcontrolled oscillator and clock generator. These provide a
stable timing reference for all circuitry on the board. The
use of a 2 MHz clock permits a basic machine cycle of two
microseconds, for those instructions that do not reference
memory during their execution.

The basic capabilities of the module are obtained
through the use of Intel's SOSO microprocessor. This
processor contains an eight-bit accumulator, six eight-bit
index registers, and an eight-bit parallel arithmetic and logic
unit (ALU). Sixteen latched address lines enable the 8080
to address 65,536 bytes of external memory. As many as
256 eight-bit input ports and 256 eight-bit output ports
may also be addressed .directly. A sixteen-bit program
counter and a sixteen-bit stack pointer permit flexible
handling of subroutines. Logic for the processing of holds
and interrupts is built into the CPU.
The 8080's internal control logic recognizes and
executes 78 different instructions. These are encoded
numerically, in a binary format consisting of one, two, or
three eight-bit bytes. Instruction categories include:
(a)

register-register transfers

(b)

register-memory transfers

(c)

arithmetic operations, including add and subtract, with and without carry or borrow

(d)

Boolean logic operations, including AND, OR,
XOR

(e)

decimal arithmetic

(f)

input/output (I/O)

(g)

stack control

(h)

interrupt control

(i)

register operate

(j)

branch control

Memory interface and control logic are included on
the board. The imm8-83 contains a fully buffered
sixteen-line address bus, which communicates with the
memory's decoding logic. An eight-line data input bus and a
buffered eight-line output bus provide for the actual data
transfers. Logic on the board monitors the status signals
from the 8080 CPU, and generates a R EAD/WR ITE (R/W)
command for the control of external memory.
I/O interface and control are also built into the
Central Processor Module. I/O peripherals share eight of the
module's sixteen address lines with memory, permitting the
processor to identify one of 256 input or 256 output
devices during execution of an I/O instruction. A separate
eight-line input bus provides communication with the input
peripherals, while output devices share the module's
eight-line data output bus with memory. Control signals
generated on the module are available at the edge connector
pins, to identify and synchronize input and output
operations.
A latched eight-bit output port is included on the
imm8-83. It is program addressable (FF I6 ), and is intended
primarily for convenience in console de-bugging.
The imm8-S3 is equipped with an asynchronous
INTERRUPT REQUEST line and with an eight-bit
interrupt port, enabling it to process external interrupts. A
peripheral device may request service by placing an
appropriate binary code on the interrupt port's lines and
simultaneously activating the INTERRUPT REQUEST line.
By doing so, the interrupting device causes the processor to

5

execute the instruction whose code appears at the port.
Any of the single byte instructions in the processor',s
repertoire may be used during an interrupt. The restart
(RST) instruction, a one-byte call, is particularly useful for
interruptive processing. A restart causes the processor to
jump to one of eight dedicated memory locations, where
service routines maybe stored. Return to the interrupted
program is accomplished by an ordinary subroutine return
(R ET), or by one of the conditional return instructions.

doing so in the sections of this book that pertain to those
modules.
The following subsections furnish a complete description of the immS-S3 Central Processor Module. The first
describes a generalized processing system, at a fairly elementary level, to provide background information for those who
are relatively unfamiliar with processors and with the
language used to describe them. Users who feel competent
to discuss processors at an advanced level should skip this
introductory section. The second section describes the
functional organization of the processor module. Detailed
information on the SOSO CPU is given in the third section.
In the fourth section we show how the peripheral logic
supports the functions that the SOSO performs. Finally, in
the fifth section, we give reference information which will
be of value to those planning to use the module outside the
INTELLEC S/MOD SO system.

The Central Processor Module is also equipped with a
HOLD REQUEST line, which enables external devices to
conduct direct memory access (DMA) transfers. During an
acknowledged HOLD REQUEST, the processor suspends its
normal activity. The module's address bus and control lines
(R/W, I/O IN, and I/O OUT) are disabled, relinquishing
control to the active peripheral. The memory input data
bus is multiplexed on to the output data bus to facilitate
write or output operations. This allows the external device
to command the busses and to effect memory transfers
directly.
A RESET input permits restarting the program from
memory location zero. Any INTERRUPT or HOLD in
progress will automatically be terminated by the RESET.
The program counter is returned to "zero". The
accumulator, status flags, and index registers are not
cleared. The H Land 0 E registers may be exchanged.

THE FUNCTION OF A CPU
This section is intended for those who are unfamiliar
with basic computer concepts. It provides background
information and definitions which may be useful in later
sections of this chapter. Those already familiar with
computers may skip this material, at their option. It is
organized to permit quick reference.

As a stand-alone CPU, the immS-S3 is almost entirely
self contained. It requires only DC power, at levels of:
+12±.5%VDC @0.06Amperes
+5±5%VDC

@" 1.5 Amperes

-9±5%VDC

@ 0.1 Amperes

The Computer System
The INTELLEC® S is a modular computer system.
This means that the processing functions, the memory
functions, and the input/output functions are built into
separate plug-in cards which are then combined to form a
system. Because the functions of each of the modules are
fairly well-defined, individual plug-ins enjoy a certain degree
of independence. They are advertised as having stand-alone
capability, meaning that they are generally capable of
performing their functions in any system similar to the
INTELLEC® S. The modular organization of this reference
manual intentionally reflects the modularity of the system
it describes.

All circuitry is mounted on a 6.1S" x 8.00" printed
circuit board, and signal and power connections enter the
module through a dual 50-pin double-sided PC edge
connector (0.125" centers). No special installation will be
necessary.
The immS-S3 may also be used as a plug-in substitute
for the imm8-S2, to update existing INTELLEC® S/MOD
SO systems. Installation of the Central Processor Module is
straightforward, and the CPU module itself requires no
changes. Minor modifications are necessary, however, in the
case of other modules.

You must keep in mind, however, that modularity
confers a very limited degree of independence. None of
these modules can. do anything useful outside a system. As
a result, the discussion of any individual mod ule must refer
continually to the activities of other modules in the same
system. It is therefore very important to know something
about the functions that each component in a system must
perform, before discussing the processor module in detail.

Although the immS-S3's edge connector pins
correspond nominally to those of the immS-S2, it has not
been possible to maintain a strict and complete logical
overlap in the address and control lines. The immS-60 I/O
Module, the immS-62 Output Module, and the Front Panel
Controller will therefore have to be modified slightly.
Intel provides a kit so simplify the conversion of existing INTELLEC S systems. This contains the immS-S3
module, an immS-61 module, a new front panel controller,
and all MOD SO software. It reduces the conversion to a
simple plug-in swap. Those who elect to modify the
modules they presently have will find the instructions for

A digital computer consists of:

6

(a)

A central processsing unit (CPU)

(b)

A memory

(c)

Input and output provisions (I/O)

This applies, in essence, to all such computers. It
applies to the INTELLEC 8.

under certain exceptional circumstances. Reading and
writing in memory are accomplished by means of program
instructions known as memory referencing instructions, so
called because they specify or imply a memory address as
an integral part of the instruction. Memory referencing
operations will be explained more fully when we describe
the CPU itself.

Memory and I/O are relatively simple functions and
are fairly easy to rationalize. The memory serves primarily
as a place to store instructions the coded pieces of data that
direct the activities of the CPU. A group of logically related
instructions stored in memory is referred to as a program.
The CPU extracts these instructions singly, in a logically
determinate sequence, and uses them to initiate processing
actions. If the program structure is coherent and logical,
processing produces intelligible and useful results.

One or more output ports permit the computer to
communicate the results of its processing to the outside
world. The output may go to a display, for use by human
operators, or it may go directly to other machines whose
responses are controlled by the processor. The output ports
are necessary in either event, if the processor is to perform
any useful function. Output ports are addressable, in much
the same manner as inputs. The input and output ports
together permit the processor to interact with the outside
world.

Processing is a complex activity, and one which
requires a lot of explanation. For now, we shall have to be
content with an intuitive understanding of what is meant
by the term. Assume for the moment that the machine
somehow manipulates data arithmetically to produce the
desired result. We shall describe the process later, in detail.

The central processor unifies the system. It controls
the functions performed by the other components. The
CPU must be able to fetch instructions from memory and
execute them, and it must be able to reference memory and
I/O ports as necessary in the execution of instructions. It
must also be able to recognize and respond to external
control signals, including INTERRUPT, HOLD, and WAIT
requests. These apparently straightforward requirements
imply a certain complexity in the way that the CPU
operates. Some of the features that enable a processor to
perform these functions are described below.

Program instructions are a form of input. The
computer can generate an output entirely on the basis of
instructions and data stored in its memory by the
programmer. In most cases, however, it is desirable to have
input provisions which augment the program as a source of
data. This is not difficult to understand. One of the most
useful. features of the computer is its speed, its abil ity to
react quickly to changes in its data environment or to
process large volumes of data. In one case, the machine
must have access to information much more rapidly than a
human operator can supply it. In the other, it requires
access to a data bank which can easily exceed its memory
capacity. Both problems can be solved partially by
providing the machine with one or more input ports. The
machine can address these ports and read the data
contained there, in a manner very similar to that used to
read from its memory. The addition of input ports enables
the computer to receive information from external
machinery, at high rates of speed and in large volumes.

The Architecture of a CPU
TIMING
The activities of the central processor are cyclical. The
processor fetches an instruction, performs the operations
required, fetches the next instruction, performs the
operations required, fetches the next instruction, and son
on. An orderly sequence of events like this requires timing,
and the CPU therefore contains a clock oscillator which
furnishes the refernce for all processor actions. The
combined fetch and execution of a single instruction is
referred to as an instruction cycle. The portion of a cycle
identified with a clearly defined activity is called a state.
And the interval between pulses of the timing oscillator is
referred to as the clock period. As a general rule, one or
more clock periods are necessary to the completion of a
state, and there are several states in an instruction cycle.

Central processing units operate so rapidly that their
responses often seem instanteneous to human operators,
but processing usually requires several stages. Many
individual instructions can intervene between the input of
data and the output of results. Consider the simple addition
of two numbers presented to two different input ports. The
machine must read the number at one port first. It stores
the value obtained in a temporary location, while it reads
the number at the second port. Then the number in
temporary storage is added to the first, to obtain the
desired result. More complex functions than this can
generate many stages of intermediate results, all requiring
temporary storage at some time during the execution of the
program. Thus a secondary function of the memory
becomes apparent, the storage of intermediate data. In the
course of a processing task, the CPU may store data
temporarily in some memory location from which it can
later be retrieved. The processor will generally write into a
portion of the memory not occupied by program
instructions, although the machine can "program itself"

PROGRAM COUNTER
The instructions that make up a program are stored in
the system's memory. The central processor examines the
contents of the memory, in order to determine what action
is appropriate. This means that the processor must know
which location contains the next instruction.
Each of the locations in memory is numbered, to
distinguish it from all other locations in memory. The

7

number which identifies a memory location is called its
address

occurs. This enables the processor later to resume execution
of the main program, when it is finished with the last
instruction of the subroutine.

The processor maintains a counter which contains the
of the next program instruction. This register is
called the program counter. The processor updates the
program counter by adding "1" ~o the counter each time it
fetches an instruction, so that the program counter is
always current.
a~dress

A subroutine is a program within a program. Usually it
is a general-purpose set of instructions that must be
executed repeatedly in the course of a main program.
Routines ehich calculate the square, the sine, or the
logarithm of a program variable are good examples of the
functions often written as subroutines. Other examples
might be programs designed for inputting or outputting
data to a particular peripheral device.

The programmer therefore stores his instructions in
numerically adjacent addresses, so that the lower addresses
contain the first instructions to be executed and the higher
addresses contain later instructions. The only time the
programmer may violate this sequential rule is when the last
instruction in one block of memroy is a jump instruction to
another block of memory.

To understand the value of subroutines, consider the
case where it is necessary to output five characters to a line
printer, in the course of a 200 step segment of the main
program. Suppose that the program which outputs the
character is the same, regardless of the actual idetity of the
character; in other words that it is possible to write a
generalized program which can output any character that
the main program supplies. And assume further that 20
steps are required for such an operation. We then have two
possible ways of coding this problem.

A jump instruction cOhtains implicitly the address of
the instruction which is supposed to follow it. Since that is
the case, the next instruction may be stored in any memory
location, as long as the programmed jump specifies the
correct address. During the execution of a jump. instruction,
the processor replaces the contents of its program counter
with the address embodied in the jump. Thus, the logical
continuity of the program is maintained.

Ohe possibility is to write the 20 output steps into the
main program, each time we desire to output a character.
The total length of the program will be 200 plus 5x20, or
300 steps in all. The other possibility is to write the 20 step
output program as a subroutine, and cause the main
program to jump to the address of the subroutine (call the
subroutine) whenever it is necessary to output a character.
In this case, the 20 step program need be stored only once.
The total number of instructions in memory will be
200+20, or 220.

Program jumps are a convenience for programmers,
and the description of their use can become complicated.
However, a basic use of the jump can be illustrated here:
that where the programmer must interleave program steps
with data upon which the processor is directed to operate:

ADDRESS

MEMORY

M

OPERATE ON M+3

M+l

OPERATE ON M+4

M+2

JUMP TO M+5

M+3

DATA FOR M

M+4

DATA FOR M+l

M+5

DO SOMETHING ELSE

r\

1\

]

PROGRAM
I NSTR UCTI ONS

}

PROGRAM
DATA

~
II

Observe that the subroutine in this example will still
be executed five times. The processor will still have to
perform 300 operations, regardless of how we choose to
code this problem. The subroutine structure, however, is
preferred. For one thing, it conserves the programmer's
time, since he need only code the output routine once. For
another, it conserves memory space, for the actual output
instructions occupy only 20 memory locations, rather than
100. These are significant advantages.

PROGRAM
INSTRUCTIONS

The processor has a special way of handling
subroutines, in order to ensure an orderly return to the
main program. When the processor receives a call
instruction, it increments the program counter and stores
the counter's contents in a reserved memory area known as
the stack. The stack thus saves the address of the
instruction to be executed after the subroutine is
completed. Then the processor stores the address specified
in the call in its program counter. The next instruction
fetched will therefore be the first step of the subroutine;

Figure 2-1. Program Jump.
If the jump at location M + 2 were omitted, the
processor would continue to operate on the assumption
thqt the pi"ogram structure was sequential. It would attempt
to fetch and execute the data in location M + 3 and M + 4
as though those locations contained instructions. The
program would most probably produce results quite
contrary to those that the programmer expected.
THE STACK

The last instruction in any subroutine is a return. Such
an instruction need specify no address. When the processor
fetches a return instruction, it simply replaces the current
contents of the program counter with the address on the
top of the stack. This causes the processor to resume

A special kind of program jump occurs when the
stored program "calls" a subroutine. In this kind of jump,
the processor is logically required to "remember" the
contents of the program counter at the time that the jump

8

execution of the calling program at the point immediately
following the original call.

particular instruction code. The enabled line can be
combined coincidentally with selected timing pulses, to
develop electrically sequential signals that can then be used
to initiate specifc actions. This translation of code into
action is performed by the instruction decoder and by the
associated control circuitry.

Subroutine~ are often nested; that is, one subroutine
will sometimes call a second subroutine. The second may
call a third, and so on. This is perfectly acceptable, as long
as the processor has enough capacity to store the necessary
return addresses, and the logical provision for doing so. In
other words, the maximum depth of nesting is determined
by the depth of the stack itself. If the stack has space for
storing three return addresses, then three levels of
subroutines may be accommodated.

MULTIPLE WORD INSTRUCTIONS
As we have just seen, an eight-bit field is more than
sufficient, in most cases, to specify a particular processing
action. There are times, however, when execution of the
instruction code requires more information than eight bits
can convey.

Processors have different ways of maintaining stacks.
Some have facilities for the storage of return addresses built
into the processor itself. Other processors use a reserved
area of memory as the stack and simply maintain a pointer
register which contains the address of the most recent stack
entry. The integral stack is usually more efficient, since
fewer steps are involved in the execution of a call or a
return. The external stack, on the other hand, allows
virturally unlimited subroutine nesting. It also permits
saving the contents of the other CPU registers, and so
provides for greater flexibility in the handling of
subroutines.

One example of this is when the instruction references
'a memory location. The basic eight-bit instruction code
identifies the operation to be performed, but cannot
specify the object address as well. In a case like this, a two
or three word instruction must be used. Successive
instruction bytes are stored in sequentially adjacent
memory locations, and the processor performs two or three
fetches in succession to obtain the full instruction. The first
byte retrieved from memory is placed in the processor's
instruction register, and subsequent bytes are placed in
temporary storage, as appropriate. When the entire
instruction has been fetched, the processor can proceed to
the execution phase.

INSTRUCTION REGISTER AND DECODER
Every computer has a word length that is characteristic of that machine. In most eight-bit systems, it is
most efficient to deal with eight-bit binary fields, and the
memory associated with such a processor is therefore
organized to store eight bits in each addressable memory
location. Data and instructions are stored in memory as
eight-bit binary numbers, or as numbers that are integral
multiples of eight bits: 16 bits, 24 bits, and so on.

MEMORY SYNCHRONIZATION
As previously stated, the activities of the processor are
referred to a master clock oscillator. The clock period
determines the timing of all processing activity.
The speed of the processing cycle, however, is limited
by the memory's access time. Once the processor has sent a
fetch address to 'memory, it cannot proceed until the
memory has had time to respond. Many memories are
capable of responding much faster than the processing cycle
requires. A few, however, cannot supply the addressed byte
within the minmum time established by the processor's
clock.

This characteristic eight bit field is sometimes referred
to as a byte.
Each operation that the processor can perform is
identified by a unique binary number known as an
instruction code. An eight-bit word used as an instruction
code can distinguish among 256 alternative actions, more
than adequate for most processors.

Therefore, many processors contain asynchtonization
provision, which permits the memory to request a wait
phase. When the memory receives a fetch address, it places
a low level on the processor's READY line, causing the CPU
to idle temporarily. After the memory has had time to
respond, it frees the processor's READY line, and the
instruction cycle proceeds.

The processor fetches an instruction in two distinct
operations. In the first, it transmits the address in its
program counter to the memory. In the second, the
memory returns the addressed byte to the processor. The
CPU stores this instruction byte in a register known as the
instruction register, and uses it to direct activities during
the remainder of the instruction cycle:

ARITHMETIC LOGIC UNIT

The mechanism by which the processor translates an
instruction code into specific processing actions requires
more elaboration than we can here afford. The concept,
however, will be intuitively clear to any experienced logic
de~igner. The eight bits stored in the instruction register can
be decoded and used to activate selectively one of a number
of output lines, in this case up to 256 lines. Each line
represents a set of activities associated with execution of a

All processors contain an arithmetic/logic unit, which
is often referred to simply as the ALU. By way of analogy,
the ALU may be thought of as a sophisticated adding
machine with its keys commanded automatically by the
control signals developed in the instruction decoder. This is
essentially how the first store-program digital computer was
conceived.

9

The ALU naturally bears little resemblance to a
desk-top adder. The major difference is that the ALU
calculates by creating an electrical analogy, rather than by
mechanical analogy. Another important difference is that
the ALU uses binary techniques, rather than decimal
methods, for representing and manipulating numbers. In
principle, however, it is convenient to think of the ALU as
an electronically controlled calculator.

processors are working simultaneously on two separate
jobs. One processor is working steadily at a low priority
job. The other is working at infrequent intervals on a high
priority assignment. The processor assigned to the high
priority task is chronically underemployed, and we may
readily improve the efficiency of this configuration, as
follows.
We use a single processor, but one which is equipped
to sense an external request for service; in other words, to
recognize and interrupt. We set this processor to work on
tbe low priority job, with the provision that it jump to a
routine designed to service the high priority channel
whenever it receives an interrupt. The processor resumes
the low priority task when it is finished handling the
interrupt. Note that this is, in principle, quite similar to a
subroutine call, except that the jump is initiated externally
rather than by the program.

The fundamental operational unit in the ALU is the
accumulator. This is the basic register in which binary
quantities are represented symbolically. Different machines
use slightly different approaches, but in general the
accumulator is both a source and a destination register. A
typical instruction will direct the ALU to add the contents
of some other register to the contents of the accumulator,
and to store the result in the accumulator itself.
The ALU must contain an adder, which is capable of
combining the contents of two registers in accordance with
the logic of binary arithmetic. The provision permits the
processor to perform arithmetic manipulations on the data
it obtains from memory and from its other inputs.

This is quite acceptable, if the low priority task does
not consume 100% of the processor's time; that is, if the
processor is not required to run at top speed continuously
in order to meet the requirements of that job. In most cases
this is not a problem, since real-time systems are generally
designed with a considerable safety margin in mind. The
average load on a properly designed system is well below its
peak capacity, to allow for statistically infrequent bursts of
activity, and to allow for some inevitable down time.

The· adder is a minimum provision, but a comprehensive one as well. Using only the basic adder, a capable
programmer can write routines wh ich will subtract,
multiply and divide, giving the machine complete
arithmetic capabilities. In practice, however, most ALUs
provide other built-in functions, includ ing hardware
subtraction, Boolean logic operations, and shift capabilities.

The interrupt feature in this simple example permits
us to increase processing efficieny up to 100%. More
complex interrupt structures are possible, in which several
interrupting devices share the same processor but have
different priority levels. Interruptive processing is an
important feature, that enables us to maximize the
utilization of a processor's inherent capacity.

The ALU contains flag bits which indicate certain
conditions that arise in the course of arithmetic
manipulations. F lags typically include carry, zero, sign, and
parity. It is possible to program jumps which are
conditionally dependent on the status of one or more of
thse flags. Thus, for example, the program may be designed
to jump to a special routine, if the carry bit is set following
an addition instruction. The example is appropriate, since
the. presence of a carry generally indicates an overflow in
the accumulator, and sometimes calls for special processing
actions.

HOLD
Another important feature that improves the throughput of a processor is the hold. The hold provision enables
direct memory access operation (DMA).
In ordinary input and output operations, the processor
itself supervises the entire transfer. Information to be
placed in memory is transferred from the input to the
processor, and the from the processor to the designated
memory location. In similar fashion, information that goes
from memory to output goes by way of the processor.

We have touched here very briefly on some of the
features of an ALU, in an attempt to explain their
provisions. However, most of. the ALU's operations are
really outside the province of the logic designer. He never
sees their results directly. It is the programmer who is
chiefly concerned with the capabilities of the ALU, since
they affect directly his ability to construct programs that
produce the. desired results. Readers who require a more
detailed explanation of the arithmetic logic unit are
referred to a good programming text, such as the
8080 Assembly Language Programmer's Manual.

Some peripheral devices, hoever, are capable of
transferring information to and from memory much faster
than the processor itself can accomplish the transfer. Ifany
appreciable quantity of data must be transferred to or from
such a device, then system throughput can be increased
substantially by having the device accomplish the transfer
directly. The processor must temporatily suspend its
operation during such a transfer, to prevent conflicts that
would arise if processor and peripheral attempted to access
memory simultaneously. It is for this reason that a hold
provision is included on some processors. By placing a hold
request, the peripheral with data to transfer can cause the

INTERRUPTS
Interrupt provisions are included on many central
processors, as a method of improving the processor's
efficiency. To understand the mechanism of an interrupt,
consider the hypothetical situation where two separate

to

processor to pause until the DMA is complete. A theoretical
improvement in I/O efficiency of up to 100% may be
gained by the judicious use of DMA.

of the fact that their inclusion is technically feasible. The
omission works to the advantage of the systems designer,
who is thereby freed to specify the speed and capacity of
his memory, the number of input and output ports in his
system, and the number and nature of control functions to
be performed by his central processor unit.

FUNCTIONAL ORGANIZATION OF THE
CENTRAL PROCESSOR MODULE

The consequence is, however, that the central
processor function is essentially a modular activity, rather
than a true chip function; that the bulk of central
processing activity can be delegated to an all-purpose chip,
but that peripheral logic will almost always be required to
round out the chip's capabilities. This is the case in the
INTEllEC S/MOD SO system.

The Intel SOSO Eight-Bit Parallel 'Central Processor
Unit is the major functional element on the immS-S3
Central Processor Module. All the other logic on the
module supports the functions which the 80S0 CPU
performs. This leads to a natural and convenient
distinction, between the "processor" and its "peripheral
logic."

The immS-S3 therefore consists of the SOSO CPU and
the logic that supports the functions of the processor.
In addition to the S080 CPU, the module contains the
following functional blocks:

There are a number of reasons for relegating certain
functions to support logic, rather than incorporating them
into the processor chip itself. The buffering of address and
data lines, for example, is a high power function, and high
power functions are fundamentally incompatible with small
package sizes. large, hot-running components not only
increase the size of the package, they increase its
susceptibility to failure. The SOSO is basically a miniature
divice, and for this reason, the buffering functions are
referred to external circuitry.

(a)

timing generator

(b)

address buffer

(c)

data buffer

(d)

input multiplexer

(e)

status latches

Much the same argument applies to multiplexing
functions. These too would logically necessitate enlargement of the package, to enable the device to dissipate the
additional power. Moreover, functions of this kind imply an
expanded number of input and output pins, and this also is
inconsistent with small package size. External logic is
therefore required for multiplexing.

(f)

command logic

(g)

wa~t

(h)

hold logic

(i)

interrupt logic

(j)

reset generator

Still other functions are not amenable to integration.
The clock reference oscillator is a prime example. It is not
yet possible to fabricate a stable frequency reference using
monolithic techniques, so that the clock function too must
be provided by peripheral logic.

(k)

output port

logic

The functional relationship between these blocks is
shown in Figure 2-2.
The SOSO CPU exercises complete control over the
rest of the logic on the module, according to the
instructions it receives from memory.

And finally, some functions are too specialized to be
included on the chip directly. One example is the
programmed display port (output port FF I6 ) which is built
into the immS-S3.
Another would be signal functions such as I/o OUT
on the immS-S3, which are dictated by the particular
application rather than by the processing function. Signals
of this kind are derived by logical conditioning of the
SOSO's basic outputs. Though the number of functions is
often modest, incorporating them into a general-purpose
device such as the SOSO would tend to limit the range of
applications which the CPU could serve. Such functions are
therefore omitted from the chip and are left to the
discretion of individual designers to provide.

The timing generator consists of a clock oscillator, a
counter section, level shifting circuitry, and gating logic.
The crystal-controlled oscillator delivers a symmetircal 32
MHz signal to the input of the counter section, which in
turn uses this input to derive two non-overlapping 2 MHz
clock phases, designated ,
f---+ 1'>:1
r-r-r--

OSC

-

RESET
LOGIC

TIMING
GEN.

CLKA

CLKB

1

INT ACK
INl

-HLT INT REO

SYNCA

1ALT ACK

1'>,

-- ll:'~"
1 "fur'" :,~
------

r---+

INTERRUPT
LOGIC

WAIT REO
RAM MOD ENBL

~ HOLD

r

--

r

MEMORY IN
DATA
f/OIN

WAIT
LOGIC

HLDA

s-=;-

r------.
r------.

ADDRESS
BUFFER
GATE

'6I/OOUT~

r

8

+

~

~'

Ifl

WR
OBI N

t

OUTPUT
PORT
FFW

STATUS
LATCHES

~

c=--

ADDRESS TO MEMORY
AND I/O PERIPHERAL

~
r----

TO CONSOLE
DISPLAY

DATA TO MEMORY
AND I/O PERIPHERAL

~

F ETCH CYCLE

liNT ACK

t-"-- )HAi:l'ACi<
( MEM READ CYCLE
STACK

DATA
BUFFER
GATE

8_

a=;:

Q.

~

I:::l

0

0

~

;;:

WR_

8_
HOLD ACK

f---+ i5BiN

rr

HOlO ACK

8-

-

-=--

WAIT
DBIN

l

DB OUT

s-=;-

SYNCA

'6-

HOLD
ACK
L..OBOUT

INPUT
MULTIPLEXER

CLKA
ClKB

CltA

HOLD
LOGIC

~
-=--

DATA -=-INTERRUPT
INSTRUCTION

WAIT

9,
¢:!

____ SYNC

:----+ INTE

INT

PROM MOD ENBL

1'>:1

osc

- - ' + WRITE
COMMAND
lOGIC

~

r---+

r-----

I/O IN
I/O OUT

DBIN
HOLD ACK
MEM WRITE CYCLE

I N JAM ENABLE

Figure 2-2. CPU Module Functional Block_

12

input peripherals, or data from the interrupt bus for input
to the processor.

during the time that the processor is idling, and serves to
acknowledge the WAIT REQUEST. A WAIT REQUEST
may be of indefinite length, but the generated WAIT
interval is always an integral multiple of the processor's
clock period.

The 8080's instruction cycle is composed of one or
more machine cycles. The number and kind of macnine
cycles in a given instruction cycle depends upon the
instruction that the processor happens to have fetched from
memory. There are nine possible kinds of machine cycles:
(a)

FETCH

(b)

MEMORY READ

(c)

MEMORY WR ITE

(d)

STACK READ

(e)

STACK WRITE

(f)

INPUT

(g)

OUTPUT

(h)

INTERRUPT

(i)

HALT

Neither the imm6-28 RAM Memory Module nor the
imm6-26 PROM Memory Module used with the INTELLEC
8/MOD 80 can respond fast enough to avoid placing the
8080 CPU in a WAIT state. The RAM Memory Module and
the PROM Memory Module have typical access times of
700 nanoseconds and 1200 nanoseconds respectively. The
RAM module therefore requires at least one full wait
interval during every memory reference. The PROM module
requires two. Circuitry in the wait logic section uses the
CPU module's 1/>1 and SYNC timing signals, in conjunction
with external RAM MOD ENBL and PROM MOD ENBL
signal, to generate an automatic WAIT REQUEST of the
desired duration whenever one of these modules is selected.
The imm8-83 is designed to respond to a PROM MOD
ENB L with an override of the delay introduced for the
imm6-28 and 6-26 boards. PROM MOD ENBL may
therefore be used to enable memories capable of responding
to the 8080 without delay:

A description of machine cycles is deferred until
Section 3.3, where we discuss the 8080 CPU. Without
getting tpo involved in a description of the processor's
activities, however, we may observe that each machine
cycle calls for a slightly different response on the part of
the peripheral logic. To aid in developing the proper control
functions, the CPU outputs status information at the
beginning of every machine cycle. Status latches are
provided to capture this data, for use by the command
logic.

The hold logic receives a HOLD REQUEST signal from
one or more peripheral devices. It also receives 1/>, and 1/>2
timing signals from the module's timing generator. When a
HOLD REQUEST coincides with the rising edge of the 1/>,
clock pulse, the hold logic forwards a HOLD to the CPU
itself. Logic within the 8080 determines when the
re-clocked hold request will be acknowledge, to ensure that
any processing functions in progress are not disrupted. The
processor will acknoWledge the HOLD within five clock
periods (2.5 microseconds), by sending a H LDA signal to
the hold logic section. After a brief delay provided by 1/>2,
the hold logic responds by:

The status latch section receives an eight-line. data
input from the module's data buffer and a CLKA strobing
pulse from the timing generator. These inputs enable the
latches to record the eight status information bits that are
published on the processor's main data bus at the beginning
of every machine cycle. Status information helps
coordinate the activities of peripheral logic, so that its
responses are appropriately keyed to the internal activities
of the processor.
The command logic obtains it principal inputs from
the status latches and from the 8080 CPU. Other inputs to
this section are the HOLD ACK from the hold logic section
and the IN JAM ENBL from t.he INTELLEC 8's Front
Panel Controller. Using these, the command logic generates
a WRITE command for the control of external memory, as
well as I/O IN and I/O OUT signals for the control of I/O
peripherals. I/O CYCLE and MEM WRITE CYCLE outputs
are available to the INTELLEC 8's console status display.
These, together with the FETCH CYCLE and the
MEMORY READ CYCLE outputs from the status latches,
enable the console logic to identify the machine cycle in
progress.

(a)

floating the module's address bus

(b)

floating the 8080's data bus

(c)

floating the WRITE output line to memory

(d)

floating the T70iN output line

(e)

floating the I/O OUT output line

This action prevents the processor from exerting any
influence on memory, via the data busses or by means of
control signals. The peripheral originating the HOLD
REQUEST is therefore free to command the memory, until
such time as the HO LD R EQU EST is retracted.
The interrupt logic monitors the INTERRUPT
-=R-=E-=Q-=-U:-::E=-=S=T and the HALT INTERRUPT REQUEST lines
from external devices. This section also receives INT ACK
and HALT ACK signals from the status latch section. The
interrupt logic uses these inputs to develop an interrupt
signal which is forwarded to the processor's INTERRUPT
input. Requests originating at the INTERRUPT REQUEST
and the HALT INTERRUPT REQUEST inputs have much
the same effect. The only significant difference between the
two inputs is that the processor responds to a HA L T

Wait logic montors the WAIT REQUEST line from the
system memory. If the memory is slow to respond to the
processor's redd or write commands, the wait logic causes
the processor to idle unitl the memory can complete the
transaction. A WAIT signal is available to external circuitry

13

INTERRUPT REQUEST only when it is stopped. Under
those circumstances, an interrupt is required to restart the
machine.

instruction. The machine may be re-started by means of an
interruptive jump to memory location 1>10 (or to some
other desired location).

The 8080 CPU provides an interrupt enabling signal
(lNTE} to the interrupt logic, indicating when the
processor's INTER RUPT input has been disabled by the
program in progress. Instructions in the CPU's repertoire
permit the explicit enabling and disabling of this input.
From the INTE signal, the interrupt logic develops an INT
DISABLE signal which flags the processor's status to
peripheral devices. No interrupt requests are recognized
unless the program· expressly enables the processor's
INTERRUPT line. A processor which has been stopped
inadvertently while the INTERRUPT input is disabled must
be reset or brought up from a cold start, in order to restore
it to operation.

Note that in the INTELLEC 8/MOD 80 system the
operator's console is the only device for which interrupt
capability is provided. Minor modifications, however, could
extend the privilege to other peripheral devices.

The processor module responds to an interrupt by
altering the sequence of events that occurs at the end of the
last instruction cycle. The processor enters an alternative
INTERRUPT machine cycle, rather than the normal
FETCH machine cycle. As it customarily does, the
processor sends out address and status information at the
beginning of the_ machine cycle, but the program counter is
not incremented. An INT A status bit identifies the machine
cycle as an INTERRUPT.
These are the only unusual events as far as the
processor itself is concerned. In all other respects, the
INTERRUPT Machine-cycle resembles an ordinary instruction fetch. Peripheral logic, however, senses the entry into
the interrupt mode. The input multiplexer responds by
selecting the interrupt instruction port instead of the
processor's memory data in port. Thus any eight-bit data
word presented to the interrupt port gets interpreted as an
instruction by the processor.
Any single-byte instruction may be inserted. There
are several possibilities. A halt (HL T) instruction may be
used to stop the processor upon completion of some task.
an external reset will be necessary for restarting the CPU.
Or an output instruction may be used to output the
accumt,lIator's contents during a critical phase of the
programming. Control and debugging are therefore two
possible useds of the interrupt feature.
But by far the most convenient instruction for use
with interrupts is the restart (RST). the RST is one byte
call instruction especially intended for use with interruptive
processing. Its binary instruction field contains three
variable digits that permit the programmer to specify a
jump to one of eight memory locations. The decimal
addresses of these dedicated locations are: 0, 8, 16, 24, 32,
40, 48, and 56. One of these locations can be used to store
the first instruction of a program designed to service the
interrupting device. Or it can store the first byte of an
ordianry three byte call (CALL), to another location where
such a program begins.
An important use of the RST instruction is the
start-up of the processor, following the execution of a halt

Reset logic permits an external device to initialize the
processor. Logic in this section also senses a power-up
sequence, and forces a RESET automatically under those
conditions. External application of a 1.5 microsecond pulse
(minimum) or the interruption of power to the module
restores the processor's program counter to zero. No other
circuitry on or around the chip is affected, except for the
interrupt request latch which is reset.
The built-in output port receives an eight-line I/O
address from the module's sixteen-line address bus
(AI s-As). It also receives an I/O OUT signal from the
command logic. These commands cause the latches in the
output port to register the contents of the module's data
out bus, whenever the decoding logic senses a coincidence
of I/O OUT and the hexadecimal address FF I6 . In the
INTELLEC 8/MOD 80 system, the port's output lines
communicate with indicators on the console panel. This
enables the operator· to examine the contents of the
processor's accumulator, during test and de-bugging
operations.

8080 EIGHT-BIT PARALLEL CENTRAL PROCESSOR UNIT
A brief description of Intel's 8080 CPU is essential to
a thorough understanding of the imm8-83 Central Processor
Module.
The 8080 is a monolithic LSI central processor,
designed for applications that use an eight-bit binary
instruction/data format. It is fabircated using N-channel
silicon gate technology and is furnished in a 40-pin dual
in-line ceramic package; The use of advanced fabrication
and layout techniques has produced an exceptionally fast
microprocessor. The basic machine cycle of the 8080 is two
microseconds, for instructions that do not reference
memory during their execution. This compares with a
twenty microsecond cycle in the ear tier 8008 CPU.
Package geometry and pin configurations are shown
in Figure 2-3. All pins, except the clock inputs, are at TTL
levels.
A list of the 8080's capabilities reads much like a
description of the imm8-83 Central Processor Module itself.
In a very real sense, it is the chip processor that determines
the character of the module. The 8080 CPU has a repertoire
of 78 basic instructions, with provisions for arithmetic and
logical operations, register-register and register-memory
transfers, subroutine handliny, I/O transactions, and
decimal arithmetic. Four internal status flags enable the

user to program conditional branches based on carry, sign,
zero, and parity.

REGISTERS
The register section consists of a static RAM array
organized into six 16-bit registers:

Using its sixteen latched address lines, the 8080 can
access 65,536 (64K) memory locations directly. As many as
256 input devices and up to 256 output devices may be
addressed during I/O operations, using either the upper or
the lower eight address lines (Ao-A? and As-A, 5 are
redundant for the purpose of I/O instructions). The 8080's
inherent addressing capability can be extended further by
the use of bank switching, where one of the output ports is
used to select among several available blocks of memory.

40
39
38
37
36
35

3
4

7

R-ESET
HOLD
INT

SYNC
+5V

10
11
12
13
14
15
16
17
18
19
20

INTEL
8080

A'3

34

As
a A7

•

Stack pointer (SP)

•

Six S-bit general purpose index registers arranged
in pairs, referred to as B,C; D,E; and H,L

•

A temporary register pair called W,Z

The six general purpose registers can be used either as
single registers (S-bit) or as register pairs (16-bit). The
temporary register pair, W,Z, are not program addressable
and are only used for the internal execution of instructions.

As

As

30

29
28
27
26
25
24
23
22
21

Program counter (PC)

The program counter maintains the memory address
of the current program instruction and is incremented
automatically during every instruction fetch. The stack
pointer maintains the address of the next available stack
location in memory. The stack pointer can be initialized
(with a LXI SP instruction) to use any portion of read-write
memory as a stack. The stack pointer is decremented when
data is "pushed" onto the stack and incremented when data
is "popped" off the stack (i.e., the stack grows
"downward").

A"
A14

33
32
31

•

A3

+12V
A2

Eight-bit data bytes can be transferred between the
internal bus and the register array via the register-select
multiplexer. Sixteen-bit transfers can proceed between the
register array and the address latch or the incrementer
/decrementer circuit. The address latch receives data from
any of the three register pairs and drives the 16 address
output buffers (Ao-A 1s ), as well as the incrementer/
decrementer circuit. The incrementer/decrementer is a
purely combinatorial circuit that receives data from the
address latch and sends it to the register array. The 16-bit
data can be incremented or decremented or simply
transferred without any operation being performed.

A,

READY

0,

HLDA

Figure 2-3. 8080 CPU Package Configuration.
The 8080 contains 6 eight-bit index registers
(scratchpad). Two of these, the H and the L registers, are
designed to double as an address pointer during the
execution of memory referencing instructions. A sixteen-bit
program counter enables the CPU to address instructions
stored in any portion of memory, and a sixteen-bit stack
pointer permits the unlimited nesting of subroutines (or
multiple-level interrupts). Built-in logic for the processing
of holds and interrupts, and a synchronization provision
for slow memories, round out the CPU's capabilities.

ARITHMETIC AND LOGIC UNIT (ALU)
The ALU contains the following registers:
•

An 8-bit accumulator {ACC and a carry/link
flip-flop (CY)

•

An 8-bit temporary accumulator (ACT) and a
temporary carry flip-flop (ACT)

•

A 5-bit flag register: zero, carry, sign, parity and
aux il iary carry

•

An 8-bit temporary register (TMP)

Architecture of the 8080 CPU
The 8080 CPU consists of the following functional

Arithmetic, logical and rotate operations are performed in the ALU. The ALU is fed by the temporary
register (TMP) and the temporary accumulator (ACT) and
carry flip-flop. The result of the operation can be
transferred to the internal bus or to the accumulator; the
ALU also feeds the flag register.

units:
•

Register array and address logic

•

Arithmetic and logic unit (ALU)

•

Instruction register and control section

•

Bidirectional, tri-state data bus buffer

The temporary register (TMP) receives information
from the internal. bus and can send all or portions of it to
the ALU, the flag register and the internal bus.

Figure 2-4 illustrates the functional blocks within the
8080 CPU.

15

decoder and external control signals feed the timing and
state control section which generates the state and cycle
timing signals.

The accumulator (ACC) can be loaded from the ALU
and the internal bus and can transfer data to the temporary
accumulator (ACT) and the internal bus. The contents of
the accumulator (ACC) and the auxiliary carry flip-flop can
be tested for decimal correction during the execution of the
DAA instruction (see Appendix A).

DATA BUS BUFFERS
This 8-bit bidirectional tri·state buffer is used to
isolate the CPU's internal bus from the external data bus
(Do through D 7 ). In the output mode, the internal bus
content is loaded into an 8-bit latch that, in turn, drives the
data bus output buffers. The output buffers are switched
off during input or non-transfer operations.

INSTRUCTION REGISTER AND CONTROL
During an instruction fetch, the first byte of an
instruction (containing the op code) is transferred from the
internal bus to the 8-bit instruction register.
The contents of the instruction register are, in turn,
available to the instruction decoder. The output of the
decoder, combined with various timing signals, provides the
control signals for the memory, ALU and data buffer
blocks. In addition, the outputs from the instruction

91

t

r

INTE

HLDA DBIN

SYNC

WR

1>2

READY INT

In the input mode, data from
is transferred to the internal bus.
precharged at the beginning .of each
for the transfer state (T3-described

the external data bus
The internal bus is
internal state, except
later in this chapter).

RESET 'HOLD

~ ~ ~ ~ ~

1

1

READ/WRITE
AND
MULTIPLEXER

WAIT

Cp Cp Cp Cp Cp

TEMPORARY REGISTER
TIMING AND
CONTROL

f--

....
u.
w
w'

W(S)

ZIS)

REGISTER

..J

DECIMAL
ARITHMETIC

III

a:
w

....

III

,---+

(3
w

ACCUMULATOR(S!

a:

H(S!

L(S!
E(8!

D(S)

C(S)

B(S!

STACK POINTER(1S)
PROGRAM COUNTER(tS!
READ/WRITE

INSTRUCTION
DECODE
AND CONTROL

-

ACCUMULATOR
LATCH(S!
INCREMENTER
DECREMENTER(1S!

-

-FLAG(S!

INSTRUCTION
REGISTER (S!

ALU(S!

-

ADDRESS LATCH(lSI

I/O BUS(S)

TEMPORARY
, REGISTER(S!

I

110 BUFFER
AND LATCH(S!

ADDRESS DRIVER(16)

CD

c~

A 15-0

Figure 2-4. 8080 CPU Functional Block Diagram.

16

-.r--

The Processor Cycle

external events and are by their nature of indeterminate
length. Observe. however, that even these exceptional states
must be synchronized with the pulses of the driving clock.
Thus the durations of all states, including these, are integral
multiples of the clock phase.

The 8080 is driven by a two-phase clock oscillator, at
a maximum frequency of 2_08 MHz_ All processing
activities are referred to the period of this clock_ The two
non-overlapping clock phases, labeled ¢l and ¢2, are
furnished by external circuitry_ The ¢l clock divides the
processing cycle into states. A state is the smallest unit of
processing activity (480 ns. when the processor is operating
at maximum speed) and is defined as the interval between
two successive positive-going transitions of the ¢1 clock.
Timing logic within the 8080 uses the clock inputs to
produce a SYNC pulse, which identifies the first state of
every machine cylcle. The SYNC pulse is triggered by the
low to high transition of ¢2, as shown in Figure 2-5.

~

To summarize them, each clock phase marks a state;
three to five states constitute a machine cycle; and one to
five machine cycles comprise an instruction cycle. A full
instruction cycle requires anywhere from four to eighteen
phases for its completion (2.0 microseconds to 9.0
microseconds), depending on the kind of instruction
involved.
MACHINE CYCLE IDENTIFICATION
With the exception of the DAD instruction there is
just one consideration that determines how many machine
cycles are required in any given instruction cycle: the
number of times that the processor must reference a memory
address, or an addressable peripheral device, in order to
fetch and execute the instruction. Like many processors,
the 8080 is so constructed that it can transmit only one
address per machine cycle. Thus, if the fetching and
execution of an instruction requires two memory
references, then the instruction cycle associated with that
instruction consists of two machine cycles. If five such
references are called for, then the instruction cycle contains
five machine cycles.

FIRST STATE OF
'EVERY MACHINE
r--CYCLEi

I

SYNC

,

+-__....J/

\1-_ _ __

-NOTE.
SYNC does not occur

In the second and third machine cycles of a DAD Instruction Since these machine cycles are only used for an Internal register-pair

add.

Every instruction cycle has at least one reference to
memory, during which the instruction is fetched. A cycle
must always have a fetch, even if the execution of the
instruction requires no further references to memory. The
first machine cycle in every instruction cycle is therefore a
F ETCH. Beyond that, there are no fast rules. It depends on
the kind of instruction.

Figure 2-5. ¢1' ¢2 and Sync Timing.

An instruction cycle consists of two functional parts,
the fetch and the execution. Each of these functional parts,
in turn, consists of a number of machine cycles. During the
fetch, a selected instruction (one, two or three bytes) is
extracted from memory and deposited in the CPU's
instruction register. During the execution part, the
instruction is decoded and translated into specific
processing activities. The fetch routine requires one
machine cycle for each byte to be fetched. The duration of
the executive portion of the instruction cycle depends upon
the kind of instruction that has been fetched. Some
instructions' do not require any machine cycles other than
those necessary to fetch the instruction; other instructions,
however, require additional machine cycles to write or read
data to/from memory or I/O devices. The DAD instruction
is an exception in that it requires ·two additional machine
cycles to complete an internal register-pair add.

Consider some examples. The add-register (ADD r)
instruction is an instruction that requires only a single
machine cycle (FETCH) for its completion. In this one-byte
instruction, the contents of one of the CPU's six index
registers is added to the pre-existing contents of the
accumulator. Since all the information necessary to execute
the command is contained in the eight bits of the
instruction code, only one memory reference is necessary:
that actually used to fetch the instruction. Three states are
used to extract the instruction from memory, and one
additional state is used to accomplish the desired addition.
The entire instruction cycle thus requires only one machine
cycle that consists of four states or four phases of the
external clock (2 microseconds).

Every instruction cycle contains one, two, three,
four, or five machine cycles. Each machine cycle, in turn,
consists of three, four, or five states. A state is defined as a
constant interval, equal in length to the period of the clock
oscillator which drives the CPU (a phase). That is, a state is
so defined in all but three cases. Exceptions to the rule are
the WAIT state, the hold (H LDA) state, and the halt
(HL TA) state, described later in this chapter. A moment's
consideration will show that this is reasonable, since the
WAIT, the HLDA, and the HLTA states depend upon

Suppose now, however, that we wish to add the
contents of a specific memory location to the pre-existing
contents of the accumulator (ADD M): Althoug this is quite
similar in principle to· the example just cited, several
additional steps will be necessary. An extra machine cycle
will be needed, in order to address the desired memory
location.
The actual sequence is as follows. First the processor

17

extracts from memory the one-byte instruction word
addressed by its program counter. This takes three states.
The eight-bit instruction word obtained during the FETCH
machine cycle is deposited in the CPU's instruction register
and used to direct activities during the remainder of the
instruction cycle. Next, the processor sends out as an
address the contents of its Hand L registers. The eight-bit
data word returned during this MEMORY READ machine
cycle is placed in a temporary register inside the 8080 CPU.
By now three more clock periods (states) have elapsed. In
the seventh and final state, the contents of the temporary
register are added to those of the accumulator. Two machine
cycles, consisting of seven states in all, complete" ADD M"
instruction cycle.

The "SHLD" instruction cycle contains five machine
cycles and takes 17 states to execute (8.5 microseconds).
Most instructions fall somewhere between the
extremes typified by the "ADD r" and the XHTL instruction which requires 18 states (9.0 microseconds). The input
(INP) and the output (OUT), for example, require three
machine cycles: a FETCH, to obtain the instruction; a
MEMORY READ, to obtain the address of the object peripheral; and an INPUT or an OUTPUT machine cycle, to
complete the transfer.
There are nine types of machine cycles that may
occur within an instruction cycle; though no one
instruction cycle will consist of more than five machine
cycles:

At the opposite extreme is the save Hand L registers
(SH LD) instruction, which requires five machine cycles.
During a "SH LD" instruction cycle, the contents of the
processor's Hand L index registers are deposited in two
sequentially adjacent memory locations; the destination is
indicated by two address bytes which are stored in the two
memory locations immediately following the operation
code byte. The following events occur:
1) A F ETCH machine cycle, consisting of four states.
During the first three states of this machine cycle,
the processor fetches the instruction indicated by
its program counter. In the fourth state, the
contents of the Hand L registers are transferred to
temporary registers within the chip, Wand Z,
respectively. Data previously held in the Hand L
registers is thus saved, thereby cleari ng Hand L to
receive incoming data.

(a)

FETCH

(b)

MEMORY READ

(c)

MEMORY WRITE

(dl

STACK READ

(e)

STACK WRITE

(f)

INPUT

(g)

OUTPUT

(h)

INTERRUPT

(i)

HALT

The machine cycles that actually do occur in a
particular instruction cycle depend upon the kind of
instruction, with the overriding stipulation that the first
machine cycle in any instruction cycle is always a FETCH.

2) A MEMORY READ machine cycle, consisting of
three states. During this machine cycle, the byte
indicated by the program counter is extracted
from memory and placed in the processor's L
register.

The processor identifies the machine cycle in
progress, by transmitting an eight-bit status signal during
the first state of every machine cycle. Updated status
information is published on the 8080's data lines (Do-D7 L
during the SYNC interval. This data may be saved in
latches, decoded, and used to develop control signals for
external circuitry. Table 2-1 shows how the positive-true
status information is distributed on the processor's data
bus.

3) Another MEMORY READ machine cycle, consisting of three states, in which the byte indicated
by the processor's program counter is deposited in
the H register.
4) A MEMORY WR ITE machine cycle, of four states,
During the first three states, the contents of the Z
register are transferred to the memory location
pointed to by the present contents of the Hand L
registers. The state following the transfer is used to
increment the Hand L pointers, so that they
indicate the next memory location to receive data.

Status signals are provided principally for the control
of external circuitry. Simplicity of interface, rather than
machine identification, dictates the logical definition of
individual status bits. You will therefore observe that
certain processor machine cycles are uniquely identified by
a single status bit, but that others are not. The M1 status bit
(D s ), for example, unambiguously identifies a FETCH
machine cycle. A STACK READ, on the other hand, is
indicated by the coincidence of STACK and MEMR signals.
Machine cycle identification data can also be valuable in the
test and de-bugging phases of system development.

5) A MEMORY WRITE machine cycle, of three
states, in which the contents of the W register are
transferred to the new memory location pointed
to by the Hand L registers.

18

8080 Status Bit Definitions

SYMBOLS

DATA BUS
BIT

DEFINITION

HLTA

03

Acknowledge signal for HALT instruction.

INTA*

DO

Acknowledge signal for INTERRUPT request. Signal should be used to
gate a restart instruction onto the data bus when DBI N is active.

INP*

D6

Indicates that the address bus contains the address of an input device
and the input data should be placed on the data bus when DBIN is active.

OUT

D4

Indicates that the address bus contains the address of an output device
and the data bus will contain the output data when WR is active.

MEMR*

D7

Designates that the data bus will be used for memory read data.

M,

D5

Provides a signal to indicate that the CPU is in the fetch cycle for the
first byte of an instruction.

STACK

D2

Indicates that the address bus holds the pushdown stack address from the
Stack Pointer.

WO

D,

Indicates that the operation in the current machine cycle will be a
WRITE memory or OUTPUT function (WO = 0). Otherwise, a READ
memory or INPUT operation will be executed.

*These three status bits can be used to control the flow of data onto the 8080 data bus.
Table 2-1.
a delay between the low-to·high transition of cf>2 and the
positive-going edge of· the SYNC pulse. There also is a
corresponding delay between the next cfh pulse and the
falling edge of the SYNC signal. Status information is
displayed on Do . D7 during this same interval. Switching
of the status signals is likewise controlled by cfh.

STATE TRANSITION SEQUENCE
Every machine cycle within an instruction cycle
consists of three to five active states (referred to as Tl, T2,
T3, T4, T5 or TW).. The actual number of states depends
upon the instruction being executed, and on the particular
machine cycle within the greater instruction cycle. The
state transition diagram in Figure 2·6 shows how the 8080
proceeds from state to state in the course of a machine
cycle. The diagram also shows how the READY, HOLD,
and INTERRUPT lines are sampled during the machine
cycle, and how the conditions on these lines may modify
the basic transition sequence. In the present discussion, we
are concerned only with the basic sequence and with the
READY function. HOLD and INTERRUPT functions will
be discussed later.

The rising edge of cfh during the Tl also loads the
processor's address lines (A o -A 15 ). These lines become
fully charged and remain charged until the first cfh pulse
after state T3. This gives the processor ample time to read
the data returned from memory.
Once the processor has sent an address to memory,
there is an opportunity for the memory to request a WAIT.
This it does by pulling the processor's READY line low
during state T2. As long as the READY line remains low,
the processor will idle, giving the memory time to respond
to the addressed data request. Refer to Figure 2-7.

The 8080 CPU does not indicate its internal state
directly, by broadcasting a "state control" output during
each state; instead, the 8080 supplies direct control ouputs
(lNTE, HLDA, DBIN, WR and WAIT) for use by external
circuitry.

The processor responds to a wait request by entering
an alternative state (TW) at the end of T2, rather than
proceeding directly to the T3 state. Entry into the T w state
is heralded by a WAIT. signal from the processor,
acknowledging the memory's request. A low-to·high
transition on the WAIT line is triggered by the rising edge
of the ct>l clock.

Recall that the 8080 passes through at least three
states in every machine cycle, with each state defined by
successive low·to-high transitions of the cf>1 clock. Figu'e
2-7 shows the timing relationships in a typical FETCH
machine cycle. Events that occur in each state are referred
to transitions of the cf>1 and cf>2 clock pulses.

A wait period may be of indefinite duration. The
processor remains in the waiting condition until its READY
line again goes high. The cycle may then proceed, beginning
with the rising edge of the next ct>l clock. A WAIT interval
will therefore consist of an integral number of T w states
and will always be a multiple of the clock period.

The SYNC signal identifies the first state (Tl) in
every machine cycle. As shown in Figure 2·7, the SYNC
signal is related to the leading edge of the ¢h clock. There is

19

RESET

READY· HLTA

READY
INT·INTE

SET HOLD F/F

SET HOLD F/F

I

I
I
I

HOLD

I

L -_ _ _+{

)<1-----...1+-

I
I
I
I
I
I
______ J

HOLD
MODE

RESET HOLD F/F

RESET HOLD FIF

RESET HLTA

HOLD
NO

RESET HOLD F/F

NO

SET INT F/F

(1)INTE F/F IS RESET IF INT F/F IS SET.
(2)1 NT F/F IS RESET IF INTE F/F IS RESET.

Figure 2-6. CPU State Transition Diagram.

20

The events that take place during the T3 state are
determined by the kind of machine cycle in progress. In a
F ETCH machine cycle, the processor interprets the data on
its main bus as an instruction. During a MEMORY READ
or a STACK READ, signals on the same bus are interpreted
as a data word. The processor itslef outputs data on this bus
during a MEMORY WR ITE machine cycle. And during I/O
operations, the processor may either transmit or receive
data, depending on whether an INPUT or an OUTPUT is
involved.

intervening between T2 and T3 of the OUTPUT machine
cycle will necessarily prolong WR, in much the same way
that DBIN is affected during input operations.
All machine cycles of at least three states: Tl, T2,
and T3 as just described. If the processor has to wait for a
response from the peripheral with which it is communicating, then the machine cycle may also contain one or more
T w states. During the three basic states, data is transferred
to or from the processor.
After the T3 state, however, it vecomes difficult to
generalize. T4 and T5 states are available, if the execution
of a particular instruction requires them. But not all
machine cycles make use of these states. It depends upon
the kind of instruction being executed, and on the
particular machine cycle within the instruction cycle. The
processor will terminate any machine cycle as soon as its
processing activities are completed, rather than proceeding
mechanically through the T4 and T5 states every time.
Thus the 8080 may exit a machine cycle following the T3,
the T4, or the T5 state and proceed directly to the Tl state
of the next machine cycle.

During the input of data to the processor, the 8080
generates a DBIN signal which may be used externally to
enable the transfer. Machine cycles in which DBIN is
available include: FETCH, MEMORY INPUT, READ,
STACK READ, AND INTERRUPT. DBIN is initiated by
the rising edge of ¢2 during state T2 and terminated by the
corresponding edge of ¢2 during T3. Any T w states
intervening between T2 and T3 will therefore prolong
DBIN by one or more clock periods.
The 8080 CPU generates a WR output for the
synchronization of external transfers, during those machine
cycles in which the processor outputs data. These include
MEMORY WRITE, STACK WRITE, and OUTPUT. The
negative-going leading edge of WR is referred to the rising
edge of the first ¢, clock pulse following T2. WR remains
low until re-triggered by the leading edge of ¢, during state
Tl of the next machine cycle. Note that any T w states

T,

 0
3 <"lJJ

~Cil

This section describes the operation and implementation of the imm8-61 Input/Output Card at three levels; first,
. the operation of the imm8-61 is described on a basic functional level; second, theory of operation is provided; third,
necessary information to effectively use the imm8-61 Card
is given. This last section covers such areas as user-available
options, signal and installation requirements, etc.

MODULE
ENABLE

OUTPUT DATA
(8 BITS)

INPUT DATA
(8 BITS)

THE immS-61 INPUT/OUTPUT CARD GENERAL FUNCTIONAL DESCRIPTION

SELECTIVE SIGNAL
ROUTING BY
MOTHER BOARD

This section describes the operations of the imm8-61
Input/Output Card in general functional terms, and is divided into six subsections. The first subsection describes
the five functional units which enable all of the operations
performed by the card. The second subsection describes
the Module Select and Port Select operations, as these two

"INVERTER CIRCUITS

MEMORY ADDRESS
DATA FROM
CENTRAL PROCESSOR
(16 BITS)

Figure 3-1.1/0 Functional Block Diagram.

39

The Functional Units

3) The Port Decode Block, on the selected card, determines which of the actual eight ports is being aQdressed by the I/O Address (0-63). It then sends
enabling signals to either the Input or the Output
block, depending on whether an Input or Output
port was addressed.

In order to describe its operation, the imm8-61 Card
can be divided into five functional units:
1) The Module Decode Block, wh ich determi nes which
card is to be utilized for an operation when more
than one card has been installed in a system.

This sequence of operations takes place before every
I/O operation.

2) The Port Decode Block, which determines which
of the 64 possible input and output ports is to be
used for an operation.

Input Operation

3) The Input Block, which contains the four input
ports and their associated logic.

An input operation is performed in order to obtain
data from an external source and to present it to the Central Processor. The imm8-61 Input/Output performs an input operation in the following steps:

4) The Output Block, which contains the four output
ports and their associated logic.

1) The data from the external device is brought into
the Input block.

5) The Teletype Control Block, which receives data
from, and transmits data to the Teletype, and
which performs the necessary conversion of the
data (serial to parallel in the case of Teletype
Input, and parallel to serial in the case of Teletype
output).

2) When the proper enabling signals are generated by
the Module Decode and Port Decode blocks, the
data which has been input from the external device
to the Input block is sent outto the Central Processor on the Input Data bus.

Each operation performed by the imm8-61 Card uses
one or more of these units in its execution.

Output Operation

A block diagram of the imm8-61 Input/Output Card,
showing the five functional units and their interrelationships, is given in Figure 3-1, and should be referred to when
reading the rest of this section.

An output operation is performed in order to receive
data which is sent out from the Central Processor and to
hold it for use by an external device. The imm8-61 Card
executes an output operation in the following steps:

Module and Port Select Operations

1) The Central Processor sends the I/O Address (0-63)
to the imm8-61 Card, and a Module and Port Select
operation is performed.

The first operation performed by the imm8-61 Card
is always a Module and Port Select operation. A Module and
Port Select operation is performed via the following steps:

2) The Central Processor sends the data wh ich is to be
output to the Output block.

1) The Central Processor (Intel imm8-83 or equivalent) sends an I/O Address to the Module Select
and Port Select Blocks. This I/O Address contains
the information necessary to specify which card
is to be used for an operation (in a multi-card system), what type of operation is to be performed
(Input or Output), and which port is to be used for
that operation. Both the complemented and noncomplemented levels on the high-order address lines
are returned to the mother-board, in turn, selectively returns either the complemented or noncomplemented level for each of the high-order address bits (depending on the card position) to the
module decoder(s), on lines DS 10,11, 14 and 15.
Thus the position of a module determines which
sixteen addresses (of a possible 64) it will respond
to. Jumpers on the I/O module's Port Decode Block
(jumping address lines 12 and 13) in turn, determine which four of these sixteen addresses are
recognized.

3) The data is placed into the selected output port,
under control of enabling signals generated during
the Module and Port Select operations.
4) The data is held in the selected output port for use
by the external device associated with that port.
Note t~at data is held in an output port until another
output operation is performed using the same output port.

Teletype Input Operation
A Teletype Input operation is performed in order to
accept information from an ASR-33 Teletype or Teletypecompatible device, and to send that data to the Central
Processor. It is performed in the following steps:
1) Data from the Teletype is sent to the Teletype
Control block.
2) The Teletype Control block converts the data to a
form useable by the Input block, and sends the data
and status signals to the Input block or input ports
o and 1.

2) The selected card is identified by the card's Module
Select Block, which generates an enable signal
which is transmitted to the rest of the card logic.

3) When the proper enabling signals are sent to the
Input block by a Module and Port Select operation

40

The high-order six address lines are input through
an inverting latch. Both the complemented and noncomplemented forms of the address bits are returned to the
motherboard. The motherboard, in turn, selectively returns
either the complemented or non-complemented form of bits
10, 11,14 and 15 (on lines DS 10, 11, 14 and 15), depending on the card position. DS 10, 11, 14 and 15 are input to
the enabling NAND gate (A16). Address lines 12 and 13 are
also input to gate A16, however, these lines are routed
through jumpers 20 and 23, respectively, on the I/O module.
The jumpers enable either the complemented or noncomplemented form of these address lines to gate A16.
These jumpers determine which four of the sixteen ports,
assigned to this card position, will actually be recognized
by the Module Decoding Circuits (see Table 3-1).

the Teletype data is sent out to the Central Processor on the Input Data bus_
Note that a Teletype Input operation differs from a
non-Teletype Input operation only in that the Teletype
Control block acts as a buffer between the Teletype and the
Input block.

Teletype Output Operation
A Teletype Output operation is performed in order to
send information from the Central Processor to the ASR-33
Teletype or Teletype-compatible device, and is performed
in the following steps:
1) The Central Processor sends an I/O Address specifying output port 0 to the imm8-61 Card, and a
Module and Port Select operation is performed as
described in Module and Port Select Operations.

If the high-order six address bits specify one of the
four port addresses recognized by the I/O module, gate A 16
generates the module select enabling signal.

2) Teletype output data is sent by the Central Processor to the Output block via the Output Data bus.

Port Addresses Enabled by I/O Module Jumpers

3) The Teletype data is placed into output port 0
under control of the enabling signals generated by
the Module and Port Decode blocks during the
Module and Port Select operation.

Jumpers
Card
Position

4) The data in output port 0 is sent to the Teletype
Control block, which converts it into a form useable
by the Teletype.
5) The Teletype Control block sends the converted
data to the Teletype.
Note that an output operation to the Teletype is equivalent to a normal non-Teletype Output operation in which
the Teletype Control block is used as the external device.

20-21
23-24

20-22
23-24

20-21
23-25

20-22
23-25

0

0-3

16-19

32-35

48-51

1

4-7

20-23

36-39

52-55

2

8-11

24-27

40-43

56-59

3

12-15

28-31

44-47

60-63

Table 3-1.

I nput Operations
Input operations on the imm8-61 Input/Output Card
are handled with the Input Circuits. These are shown on the
left in the I/O Module Schematic, Figure 3-2.

imm8-61 INPUT/OUTPUT CARD THEORY OF OPERATION

The first step in an input operation is the transmission
of an I/O Address to the imm8-61 Card from the Central
Processor. This I/O Address contains Module and Port Selection information which is necessary to determine which port
is to be used for a particular operation.

This section describes, in detail, the theory of operation of the imm8-61 I nput/Output Card. The circuit-level
implementation of the features described will be given.

Module Selection

The Module Selection information is processed by the
Module Select Circuits, and causes the Module Enable signal
to be produced. This signal is led to the Input Decoder chip,
where it is used as an enabling signal.

If more than one imm8-61 Card is present in a system, provisions must be made for an operation to select one
card. This capability is provided by the Module Decoding
Circuits.

When it is enabled by the Module Enable signal, and
the I/O IN signal sent by the Central Processor, the Input
Decoder uses the Port Selection information contained in
the I/O Address to produce one of four Port Enable signals.
The Port Selection information comes onto the imm8-61
Card on lines MAD8 and MAD9.

Module address information is brought to imm8-61
Card edge pins; the module address is complemented by a
series of inverting latches and the complemented address is
present at additional imm8-61 Card edge pins. The user
selects an address for each imm8-61 Card, and implements
the address by selecting a set of Address and Complemented
Address signals; selected signals are externally jumpered to
the Module Selection circuits, which combine the incoming
signals through a NAND gate (A 16) to provide the enabling
signal which is sent to other circuitry on the card.

The Port Enable signals are led to the four Input Port
Multiplexers, and are used to gate one set of input signals
through the Input Port Multiplexers onto the Input Data
Bus, where the data is available for use by the Central Processor. Timing is shown in Figure 3-3.

41

8

7

6

5

4

3

2

o

c

B

B

A

A

8

7

6

5

4

3

2

Output Operations

This function is performed by the Teletype Communications Circuits, shown in the upper central section of Figure
3-2.

Output operations on the imm8-61 Input/Output Card
are handled by the Output Circuits, shown on the right in
Figure 3-2.

Teletype Communications on the imm8-61 Card are
handled through Input Ports 0 and 1 and Output Ports 0
and 1. I nput Port 0 handles Teletype data which are to be
input to the Central Processor; Input Port 1 handles Teletype status information. Output Port 0 holds the data which
are output from the Central Processor to the Teletype, and
Output Port 1 holds the control data used to control Teletype communications. All Teletype input and output operations, with the exception that the on-card Teletype Communications Circuits are used as the input and output device
for Teletype operations.

An Output operation begins with the transmission of
an I/O Address to the imm8-61 Card from the Central Processor. This I/O Address contains Module and Port Selection
information which is used to determine which output port
is to be used for a particular operation.
The Module Selection information is processed by the
Module Select Circuits and cause the Module Enable signal
to be produced. This signal is led to the Outout Decoder
chip.
The Central Processor then sends the data which are
to be output to the imm8-61 Card on lines DBO-DB7. Along
with the output data is sent the I/O Ol!T signal, which is led
to the Output Decoder and is used as a second enabl ing
signal.

The heart of the Teletype Communications Circuits
of the imm8-61 Card is the Universal Asynchronous Transmitter/Receiver chip, or UART. This device receives the serial
data word which is sent by the Teletype, and converts it to
the eight-bit parallel data format used by the imm8-61 Card.
It also translates the eight-bit data output by the imm8-61
Card. It also translates the eight-bit data output by the
imm8-61 Card into the serial data word which is used by the
Teletype.

When the Output Decoder is enabled by the two
enabling signals Module Enable, and I/O OUT, it uses the
Port Selection information contained in the I/O Address to
produce one of four Port Enable signals. The Port Selection
comes into the imm8-61 Card on lines MAD8 and MAD9.

The UART requires a clock with a frequency of sixteen times the baud (bits per second) rate at which it is to
transmit. This clock is provided on the imm8-61 Card by a
crystal clock generator which provides a 4.9562 MHz signal.
This signal is used to clock a series of two synchronous
counters, each of which provides a "divide-by-sixteen" function, thus producing a 19.36 kHz signal. This signal can be
used directly, providing 1200 and 2400 baud transmission
rates suitable for Teletype-compatible high-speed terminals,
or it may be used to clock another synchronous counter.
This third counter is set up to provide a "divide-by-eleven"

The Port Enable signals are used to gate the output
data sent by the Central Processor into the proper Output
Port Latches. The data is held in the Output Port Latches
until another output operation is executed using that output
port. Timing is shown in Figure 3-3.

Teletype Communications
Teletype communications can be handled directly by
the imm8-61 Input/Output Card, rather than requiring a
separate Teletype communications interface and controller.

Tl

T2

T3

T4

T5

Tl

T2

T3

T4

1/>, CLOCK

¢> CLOCK

SYNC

CLKA

n

n

l

ADDRESS

INPUT

1/0 IN

IN0- 7

X

X

1/0 OUT
OUTPUT
OUTPUT PORT

1

X

Figure 3-3. I/O Module Timing

43

A special feature has been implemented on the
imm8-61 Card in order to simplify Teletype paper tape
reader operations. Provisions have been made to enable
strobing of the paper tape reader one character at a time .
This operation is performed when the Central Processor
outputs a 1 in the high -order bit of Output Port 1. This
signal sets a latch made up of two NAND gates, which in
turn produce a signal which is sent to the Teletype paper
tape reader as TTY R 0 R CT L. When a character is read by
the Teletype paper tape reader and transmitted to the
imm8 -61 Card, the signal generated by that transmission,
TTY XMITR, resets the latch, causing the TTY RDR CTL
signal to fall.

capability, and will provide a 1.76 kHz signal which, when
used as the UART clock, will provide a 110 baud transmission rate, the standard rate for ASR-33 Teletype com·
munications.
A Teletype input operation begins with the trans·
mission by the Teletype of a data word. This Teletype data
is brought onto the imm8·60 Card by way of edge pins as
signal TTY XMITR. Since the Teletype information is en·
coded as variations in current flow, while the UART oper·
ates with changes in voltage , the Teletype signal must be
converted to a form acceptable to the UART. This is done
with transistor 02 and its associated circuitry . The signal
from transistor 02 is led to the UART Receive Data Input,
and the UART converts it into the parallel data used by the
imm8·61 and then sends the converted data word to Input
Port O. It also sends status information to Input Port 1. This
status information includes Parity Error (PE), Overflow
Error (OE), Framing Error (FE), and Data Available (DA) .
The Central Processor can then execute a normal input
operation as described on page 40 in order to obtain
the Teletype data.

The Teletype Communications Circuits may be reset
by a system reset signal. This is done by bringing the signal
RESET onto the card, inverting it through an inverting
latch, and applying it to the Master Clear input of the
UART . This will initialize the UART, and prepare it for
further operations .

immS-61 INPUT/OUTPUT CARDUTI L IZATION

A Teletype output operation is executed simply by
sending the data which are to be output to the Teletype to
Output Port 0 via an output operation. The data which are
to be sent to the Teletype are latched into Output Port 0
Latch, and sent to the UART . The same enabling signal
which was used to latch the data into the Output Port Latch
is used to enable transmission by the UART . NOTE : Before
a transmission is attempted , Input Port 1 must be inter·
rogated to determine TTY status. The Parallel data will be
translated to the serial data' format required by the Teletype, and will then be sent to 03 and 04, where the necessary conversion from voltage to current codi ng takes place.
The converted signal is then sent to the Teletype as TTY
RCVR.

By changing a module's card position or by changing
jumper connections on an I/O module, the user can choose

Figure 3-4. Relay Circuit (Alternate)

Figure 3-5. Distributor Trip Magnet

This section describes the options available to the
user of the imm8-61 Input/Output Card , and also gives the
information necessary to the user for proper installation and
operation of the card . There is a wide range of user-available
options on the imm8-61 Card, including the choice of usable
addresses, the choice of whether or not to use the Teletype
Communications Circuits, and the choice of a 110, 1200 or
2400 baud rate for data transmissions.

User-Available Options

44

the port addresses that a particular I/O module will recognize. Recall that each I/O module has four input ports and
four output ports. For anyone combination of card position and jumper connections, the module will respond to
four addresses (one for each input or output port). but by
changing the combinations, the module can be dedicated
to respond to any address between 0 and 63. Table 3-1 lists
all of the usable combinations.

110 baud :

connect jumpers 18-19;
jumper connections 16-18 and 17-18
should be open.

1200 baud: connect jumpers 16-18;
jumper connections 18-19 and 17-18
should be open.
2400 baud : connect jumpers 17-18;
jumper connections 18-19 and 16-18
should be open.

This option allows a user to develop and debug programs that access up to 64 different input and output device
addresses, on an INTELLEC 8/MOD 80 system even though
the system actually includes only 16 input and 16 output
ports. The option allows lower hardware costs without
impeding development.

The imm8-61 Card has been designed to optionally
interface with the Intel imm6-76 PROM Programmer Card .
This card uses Input Port 2 for a PROM Data Out Port, and
Output Ports 1, 2 and 3 as PROM Control In, PROM
Address IN, and PROM Data IN, respectively. It is necessary to ensure, if this option is used, that no other device
will attempt to use these ports while PROM programming
operations are in progress.

If it is desired, the imm8-61 Input/Output Card's
internal Teletype Communications Circuits may be disabled
by removing the UART chip. If this is done, pull-up resistors (resistor pack RP1) must be added to the input data
lines on Input Ports 0 and 1. The UART may also be disabled by tying its output enable lines ROE and FOE to
+5v.

Installation Data
o

0

Operating Temperature: 0 to +70 C
DC Power Requirements : +5v ± 5%, .820A Max
-9v± 5%, .030A Max

Teletype input and output can be accomplished without the use of the UART; that is, on a serial programcontrolled basis, by positioning jumpers as follows :

Connector : Dual 50-pin, 0.125 in. centers

Output: 10-12 instead of 10-11
Input: 7-8 instead of 8-9

Teletype Modifications
The ASR -33 Teletype must receive the following
internal modifications and external connections.

When the Input/Output Module is used for the Teletype operations, the user must ensure that no device other
than the Teletype is connected to Input Ports 0 and 1 or
Output Ports 0 and 1.

Internal Modifications
1) The current source resistor value must be changed
to 1450 ohms. This is accomplished by moving a
single wire (see Figure 3-8).

The different baud rates can be chosen by positioning jumpers as follows:

Figure 3-6. Mode Switch

Figure 3-7. Terminal Block

45

2) A full duplex hook ·up must be created internally.
This is accomplished by moving two wires on a
terminal strip (see Figures 3·7 and 3·9).

spl iced into the brown wire near its connector plug.
The "line" and "local" wires must then be con·
nected to the mode switch. (See Figures 3·6 and
3·9).

3) The receiver current level must be changed from
60mA to 20mA . This is accomplished by moving a
single wire (see Figure 3· 7 and 3·9).

EXTERNAL CONNECTIONS

4) A relay circuit must be introduced into the paper
tape reader drive circuit. The circuit consists of a
relay, a resistor, a diode, a thyractor and a suitable
mounting fixture. Th is change requires the assem·
bly of a small "vector" board with the relay circuit
on it. It may be mounted in the Teletype by using
two tapped holes in the base plate (see Figure 3-4).
The relay circuit may then be added without altera·
tion of the existing circuit (see Figures 3·5, 3·6,
and 3·7). That is, wire "A" (Figure 3·9). to be
connected to the brown wire in Figure 3·5, may be

1) A two·wire receive loop must be created. This is
accomplished by the connection of two wires be·
tween the Teletype and the SYSTEM in accordance
with Figure 3 ·9.
2) A two·wire send loop similar to the receive loop
must be created. (See Figure 3·9).
3) A two·wire tape reader loop connecting the reader
control relay to the SYSTEM must be created. (See
Figure 3·9).

TOP VIEW
MODE
SWITCH
MOUNT
REEO
RELAY

CAPACITOR

I
I

I
rn i

K EY BOARD

®!

PRINTER UNIT
TAPE
PUNCH

I

CURRENT
SOURCE
RESISTOR

POWER
SUPPL Y

I
I

I
I

I
I
I

TERMINAL
STRIP

OISTRIBUTOR
TRIP MAGNET
ASSEMBLY

[;]

8

I

I
TELETYPE MODEL 33TC

Figure 3·10. Teletype Layout

Figure 3·8. Current Source Resistor

46

TAPE
READER

BLU
NOTES: UNLESS OTHERWISE SPECIFIED

II:::::>

CUSTOMER EXTERNAL CONNECTIONS

[!:::> IT~~:T~:J~~NR~~t~~~DL~ci'~I~I~A';-~~~~TS
1M IS INTERNAL MOOIFICATION
EC IS EXTERNAL CONNECTION

8

TERMINAL BLOCK 151411
SEE FIG. 3-7

VIO

I/O
MOOULE
(J1)

REAR PANEL
CINCH·JONES
(J431

RECEIVE

f,1\...----.f2\-- _____
~

""\V"""

20 mA

~-"":~:::r_-_T_-_-~~ __60_m~ _ _ _ _ _ L/""""O"-~~

FULL DUPLEX

@------0--------

CURRENT SOURCE RESISTOR
SEE FIG. 3-41

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WHT/BRN
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WHT/BLK
WHT/BLU
FULL OUPLEX

~B~R~N~/Y~E~L~~____~,

0--- ---0- -- ---- --I--I"t=~~=-=-r-=-=GRN-------SEND

RED

HALF DUPLEX

@------0------ - -1-a-;:::~r"':':~=~~t-=-i-=-=:~/~E~- ---SEEFiG.""3-=7
~-----+------+------~ ~

L-~~~~~====~B;.L~K~-----------I1~
[""

WHT
WHT
CONNECTOR
SEE FIG. 3-5

}-_-+_________....1_ _ _ _ _.!.'_-.....-_-, I

TAPE
READER
CONTROL

- - - - - - - - - -:1
GE
6RS2Q.
SP4B4

} - - - i - - - - - - - - - - - " 7I---<1>---'

(9

*ALTERNATE CONTACT PROTECTION CIRCUIT

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~-----------------~------~
MODE SWITCH
(FRONT VIEWI
SEE FIG. 3-6

Figure 3·9. TTY Modification

41

115AC
COMMON

48

The immS-63 Output Card contains logic which
enables its use as a self-contained output module with eight
(S) individually addressable output ports, each of which
holds an eight-bit byte of data sent by a Central Processor
(such as Intel's immS-63) for use by an external device. It
also contains logic which enables the use of more than one
card in any system, with each card individually addressable.

The Central Processor then sends the data which is to
be output to the immS-63 Card. The data is routed to the
Output Port block and is gated into the particular port
which was enabled previously by the Port Decode Block.
The data are then latched and held for use by the external
device associated with that output port.

GENERAL FUNCTIONAL DESCRIPTION

DETAILED FUNCTIONAL THEORY

The immS-63 Output Card may be divided into three
functional units as shown in Figure 4-1:

This section describes in detail the operation of the
immS-63 Card. Actual circuit-level implementation of the
features described as functional blocks in the previous section are given .

• The Module Decode Block
• The Port Decode Block
• The Output Port Block

Module Decoding

The Output Port Block contains eight output ports,
each of which can communicate with a separate external
device. The Port Decode Block determines which of the
eight ports is to be used for an operation.

If it is desired to use more than one immS-63 Output
Card in a given system, some provision must be made to
enable selection of the particular card which is to be used,
out of all of those available. This function is provided by the
Module Decoding Circuits, shown in detail in Figure 4-2.

During an output operation, the Central Processor or
equivalent device, sends an 1/0 Address to the Output Card.
This information is used by the Module Decode Block to
enable output operations (for the particular module being
addressed, if there is more than one in the system), and is
also used by the Port Decode Block to enable the specific
output port which is to be used for output.

As shown in Figure 4-2, the Module Address information is brought to the immS-63 Card edge pins and is led to
edge pins. The motherboard, in turn, selectively (according
to card position) return the proper set of address and inverted address signals to the OUT MOD SEL gate (A 14) in
the Module Decoding Circuits. In addition, address lines 12
and 13 are routed through jumper connections which provide either an inverted or non-inverted form of the address
12 and 13 signals to the OUT MOD SEL gate (A14). If all
the input lines to gate A 14 specify that the module is
selected, the OUT MOD SEL signal is generated.

DATA
FROM{
CPU
110 ADDRESS
OUTPUT

OUTPUT
PORTS,
(8)

Port Decoding
Once the proper module has been selected, as discussed in the previous subsection, an additional selection
must be made: that of one of the eight output ports which
are on each immS-63 Card_ This function is performed by
the Port Selection circuits, shown in detail in Figure 4-2.

Figure 4-1. Output Module Functional Block Diagram

49

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8

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6

7

5

3

4

2

1

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A

6

""rES:I. saJO JlJMPER:$ ARE M4PE

WlTU

RC. n:tAca. DASU LINES AR~
ALl"EANAl=£ JUMPER CDNN~crlOt\lS.
Z.· RESISTANcE: VALUES ARE IN
OHMS '±5%, 1/4W.

B

In order to select one of the eight output ports, three
data lines are led to the Port Decoder. When enabled by the
OUT MOD SEL signal, the Port Decoder will decode the
three incoming Port Select signals and will issue an enabling
signal to one of the eight output ports.

CARD UTILIZATION
The user has the capability of choosing which eight
addresses an imm8-63 will respond to; the user can assign
any group of addresses between 0 and 63. This section describes how to use the addressing option, and also supplies
a complete list of the imm8-63 card edge pins and their
associated signals.

Output Operations
In a typical output operation, the following steps will
be executed (refer to Figure 4-2, the Schematic Diagram):

User Options

1) The Central Processor sends an I/O Address to the
imm8-63 Module on lines MAD8-15.

A combination of card positioning and jumper connections (on the Output Modules) determines which eight
addresses each module will recognize. Table 4-1 lists the possible combinations of card position and jumper connections,
and the address groups associated with each combination.

2) The Module Decoding and Port Decoding circuits
decode the incoming I/O Address, and send enabling signal OUT STB to the proper output port.
3) The Central Processor sends the data which are to
be output to the imm8-63 Card, along with an Output enabling signal, I/O OUT. I/O OUT activates
the internal signal OUT STB.

imm8-63 Addressing Options

4) The data which have been sent to the imm8-63
Card are latched into the proper output port by
signal OUT STB, where they are held for use by
external equipment. The data are held until another
output operation using the selected port takes
place, at which time they are replaced by the new
incoming data.

Card
Position

The timing of the output operation is shown in Figure 4-3.

1-2

2-3

1-2

2-3

5-6

5-6

4-5

4-5

0

0-7

16-23

32-39

48-55

1

0-7

16-23

32-39

48-55

2

8-15

24-31

40-47

56-63

3

8-15

24-31

40-47

56-63

Table 4-1

Figure 4-3. Output Module Timing

51

Jumpers

52

The Four Functional Units

The imm6-28 Random Access Memory Card has been
designed to provide a user with a 4,096 (4K) 8-bit words of
random-access memory, which may be used as a computer
system's memory device_

In order to describe its operation, the imm6-28 card
has been divided into four functional units:
1) The Address Control Block, which determines

More than one imm6-28 card may be included in a
system, for example, the imm8-83 Central Processor card
can address up to 16,384 words of memory on four separate
imm6-28 cards.

which card is to be used for a memory operation,
and which memory location on that card is being
addressed.
2) The Operation Control Block, which controls the
execution of all operations performed by the card.

Although the imm6-28 Random Access Memory Card
has been designed to support the Intel imm8-83 Central
Processor Card, it can be used in any other system which
requires 4K x 8 bits of RAM storage.

3) The ReadlWrite Buffers, which buffer the data
which is read from or written into memory.
4) The Memory Block, which contains the actual
memory components.

THE imm6-28 RANDOM ACCESS MEMORY
CARD-GENERAL FUNCTIONAL DESCRIPTION

Each operation performed by the imm6-28 card uses
at least one of these functional units.

This section describes the operation of the imm6-28
Random Access Memory Card in general functional terms,
and is divided into four subsections.

MEMORY
(40968-BIT
WORDS)

ADDRESS

1-----+1

READ/
WRITE
BUFFERS

A block diagram of the imm6-28 card, showing the
four functional units and their interrelationship, is given in
figure 5-1, and should be referred to when readi ng the rest
of this section.

MEMORY DATA
FROM CPU (8 BITS)

Memory Addressing Operations

MEMORY DATA
TO CPU 18 BITS)

In order to send data to a memory location, or to
read data from a location, it is necessary to specify the
location which is to be accessed. This function is provided
by the memory Address, a group of signals which represent
the Central Processor. Once the Memory Address is received
to select the correct location for a Memory Read or Write
operation.

BLOCK
ENABLE

ADDRESS ~_-.! OPERATION
CONTROL
CONTROL

MEMORY ADDRESS
FROM CPU

The Address Control Block performs Memory Address
decoding on the imm6-28 card; it receives the Memory
Address, and translates it into three types of signals: Module
Enabling signals, which enable the selected 4K segment of
the memory; Block Enabling signals, which enable one 1024
word block within the larger 4K segment; and Address signals, which access one word within the 1024 word block.

READ/WRITE
CONTROL
SIGNAL
FROM CPU

Figure 5-1. RAM Module Functional Block Diagram

53

Memory Write Operations

4) The Operation Control Block generates the control
signals necessary to cause the contents of the selected memory location to be sent from the Memory Block to the Read/Write Buffer, whence they
are sent on to the Central Processor.

A Memory Write Operation is executed in order to
load data into a selected memory word; it is executed in the
following steps:
1) The Memory Address for the word which is to be
written into is sent to the imm6-28 card by the
Central Processor.

THE imm6-28 RANDOM ACCESS MEMORY
CARD-THEORY OF OPERATION

2) The Address Control Block receives the Memory
Address and generates the signals necessary to
access the addressed memory location.

This section describes the theory of operation of the
imm6-28 card in detail giving the circuit-level implementation of the features.

3) The Central Processor sends a data word to the
imm6-28 card, where it is received by the Read/
Write Buffer. The central Processor also sends control signals to the Operation Control B lock which
indicate a Memory Write operation.

Physical Memory Implementation
The actual memory of the imm6-28 card is made up
of thirty-two Intel 2102 Random Access Memory chips,
each havi ng a capacity of 1024 one bit words. Si nce the data
word used by the imm6-28 card has a total of eight bits,
the 2102 memory chips are tied together in blocks of eight,
with each of the eight chips in the block handling one of
the eight data bits; this results in a basic block of 1024
eight-bit words. Since there are four blocks per card, each
imm6-28 card has a capacity of 4096 eight-bit words.

4) The Operation Control Block generates signals
which cause data in the Read/Write Buffer to be
written into the selected memory location in the
Memory Block.

Memory Read Operations
A Memory Read operation is performed in order to
read data from a selected memory location into the Central
Processor; it is executed via the following steps:

By combining more than one card in a system, memory size can be increased in increments of 4096 words.

Memory Address Decoding

1) The Memory Address which is to be read is sent
to the imm6-28 card by the Central Processor.
2) The Address Control Block receives the Memory
Address and generates signals necessary to access
the addressed memory location.

Since more than 4096 words of memory can be addressed by a Central Processor, the imm6-28 card includes
address decoding circuits (see Figure 5-2) which allows a
Central Processor to select one imm6-28 memory card.

3) The Central Processor senc;ls control signals to the
to the Operation Control Block which indicate a
Memory Read operation.

The Memory Address which the Central Processor
sends to the imm6-28 cards consists of sixteen bits of information, organized as a sixteen digit binary number, with the

T2

Tl

T3

T4

T5

Tl

T2

rpl CLOCK
~CLDCK

SYNC

CLKA

ADDRESS

n

n

X

X

CKIP ENABLE

DATA OUT

}

X

DATA IN

READ

I

X

WRITE

R/W

Figure 5-2. RAM Memory Module Timing

54

T3

T4

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3

4
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2

low order bit on line MADO and the highest order bit on
line MAD 15. The Address Decoding Circuits use this sixteenbit address as follows:

the imm6-28 card. In its TRUE state, this signal indicates a
Write operation, therefore, during a Read operation, it will
be FALSE. Signal Write/Read is inverted and applied to a
NAND gate along with the Module Enable signal. The NAND
gate produces a signal which indicates a Read operation.
The Read operation signal is used as the second input to the
series of Output Buffer NAND gates, and causes the memory data to be gated through the Output Buffer NAND
gates and onto the Data Out Iines DATA OUTO-DAT A
OUT7. Timing is shown in Figure 5-2.

1) Since the high-order four bits of the Memory Address effectively divide the possible memory locations into sixteen units of 4096 words each, they
are used to enable the particular card which is to be
used for a given memory operation. Th is is accomplished by bringing lines MAD12-MAD15 onto the
imm6-28 card edge pins, inverting them to form
-MAD 12-MAD 15, and then sending these inverted
Memory Address signals out on another set of card
edge pins. External jumpers are then used to tie
the proper combination of Memory Address and
inverted Memory Address signals to the four input
lines to the Access Enable Gate, MOD SEL 12-MOD
SEL 15. When the proper Memory Address is sent
to the imm6-28 card by the Central Processor, the
Access Enable Gate will produce a Module Enable
signal which is used to enable all memory operations for that card.

Memory Write Operations
A Memory Write operation is initiated by the Central
Processor. It sends a sixteen bit Memory Address to the
imm6-28 card, which decodes the address to ,select one
particular memory location for access, as described in Section 6.2.2. When the memory chips receive the Memory Address, they immediately respond by sending the contents of
the addressed location to the Output Buffers, which are
series of eight NAND gates.
The Central Processor then sends the data wh ich is to
be written into memory to the imm6-28 card, where it is
led to the Input Latches. The Central Processor also sends
out signal Write/Read, which indicates a Write operation.
This signal is NANDed with the Module Enable signal to
produce signal WDENBL, which indicates that a Write
operation is taking place. This signal causes the data sent by
the Central Processor to be latched into the Input Latches.

2) The next two bits of the Memory Address, MAD1 0
and MAD 11, select one of the four 1024 word
Latches which are enabled by the Access Enable
Gate's Module Enable signal. The two signals are
then latched into the Address Latches by signal
ADR STB, sent by the Central Processor, and are
sent to a group of four NAND gates in both their
original and their inverted form. The four NAND
gates decode the two Memory Address bits into
one of four Chip Enable signals. The Chip Enable
signals are used to enable the proper block of eight
chips (1024 eight-bit words) out of the four blocks
available on each imm6-28 card.

Signal WDENBL is also used to trigger a pair of oneshot multivibrators. These multivibrators produce a delayed
Write Enable signal. The delay is necessary to ensure that the
delayed Write Enable signal becomes TRUE, the data will
be written into the selected memory location.

3) The ten low-order bits of the Memory Address,
MADO-MAD9, are tied to Address Latches which
are enabled by the Access Enable Gates. They are
then sent to all of the individual memory chips,
which use them to enable the proper location out
of the 1024 available.

THE imm6-28 RANDOM ACCESS MEMORY
CARD - UTILIZATION
This section provides the information necessary to
efficiently use the imm6-28 card in an application. In particular, the requirements for interfacing with the Intel
imm8-83 Central Processor Card are stressed.

Memory Read Operations

Memory Address Coding

A Memory Read operations is initiated by the Central
Processor. It sends a sixteen-bit Memory Address to the
imm6-28 card, which decodes the address to select one
particular memory location.

In order to enable Memory operations, the imm6-28
card must have an encoded address designation. The proper
positioning of the external jumpers for each block of memory is as follows:

The Central Processor also sends signal Write/Read to

56

Module No.

Memory Addresses

RAM 0
RAM 1
RAM 2
RAM 3
RAM4
RAM 5
RAM 6
RAM 7
RAM 8
RAM 9
RAM 10
RAM 11
RAM12
RAM13
RAM14
RAM 15

0-4095
4096-8191
8192-12287
12288-1 6383
16384-204 79
20480-24575
24576-28671
28672-32767
32768-36863
36864-40959
40960-45055
45056-49151
49152-53247
53248-57343
57344-61439
61440-65535

Memory Address Code
MAD12
MAD12
MAD12
MAD12
MAD12
MAD12
MAD12
MAD12
MAD12
MAD12
-MAD12
MAD12
MAD12
MAD12
-MAD12
MAD12

MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13
MAD13

Installation Data and Requirements
Connector: Dual 50-pin, .125 in. centers
Input Voltage: +5v± 5% @ 2.5A.
Operating Temperature: 0 0 C_ 70° C

57

MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14
MAD14

Jumpers
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15

57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-68,
58-60,

62-61,
62-61,
59-61,
59-61,
62-61,
62-61,
59-61,
59-61,
62-61,
62-61,
59-61,
59-61,
62-61,
62-61,
59-61,
59-61,

63-63,
63-64,
63-64,
63-64,
64-66,
64-66,
64-66,
64-66,
63-64,
63-64,
63-64,
63-64,
64-66,
64-66,
64-66,
64-66,

67-68
67-68
67-68
67-68
67-68
67-68
67-68
67-68
65-67
65-67
65-68
65-67
65-67
65-67
65-67
65-67

58

The imm6-26 Programmable Read-Only Memory
(PROM) Card has been designed to provide a user with
4,096 (4K) words of read-only memory, which may be
used as non-volatile program or data storage.

can address up to 16,384 words of memory on four
separate imm6-26 cards.

The imm6-26 Card uses Intel 8702A Programmable
Read-Only Memory chips as its storage medium. These
chips represent a considerable advance in the field of
read-only memory, as they can be erased and reprogrammed
as the need arises. This capability makes the imm6-26 Card
a valuable addition to a system in which the stored data is
occasionally 9.J bject to change, for example, during the
development of mask-programmed read-only memory. The
imm6-26 PROM Card can be used to store programs in final
stages of correction, before the progr:am is well enough
defined to justify th; expense of creating masks. Also, the
imm6-26 PROM Card can be used instead of read-only
memory in pre-production equipment that may have to be
shipped before mask-programmed read-only memory is
available.

Note: When used in conjunction with the imm8-83 the
8702A type used must have an access time of less
than 1.5 microsecond.

The imm6-26 Card may also be used in parallel with
an imm6-28 Random Access Memory Card.

THE imm6-26 RANDOM ACCESS MEMORY
CARD-GENERAL FUNCTIONAL DESCRIPTION
This section describes the operation of the imm6-26
Programmable Read-Only Memory Card in general functional terms, and is divided into three subsections.

The Four Functional Units
In order to describe its operation, the imm6-26 Card
had been divided into four functional units:
1) The Address Control Block, which determines
which card is to be used for a memory operation,
and which memory location on that card is being
addressed.

More than one itnm6-26 Card may be used in a
system. For example, the imm8-83 Central Processor Card

MEMORY
14096 S'BIT
WORD
CAPACITY)

BLOCK
ADORESS

MEMORY

ADDRESS

DATA

WORD
ADDRESS

i
PROM DATA OUT

3) The Memory Data Buffer, which buffers the .data
bei ng read from memory.

ADDRESS

CONTROL

MEMORY
DATA
BUFFER

1

2) The Operation Control Block, which controls the
execution of all operations performed by the card.

4) The Memory Block, which contains the actual
memory components.

MoDi
ENBL.
PROM
DISABLE

CONTROL

A block diagram of the imm6-26 Card, showing the
four functional units and their interrelationship, is given in
Figure 6-1, and should be referred to when read ing the rest
of this section.

I+-

1

Memory Read Operation

RAM ENABLE

In order t6 obtain data from a memory location, it is
necessary to perform a Memory Read operation. This
operation can be divided into two phases:

Figure 6-1_ PROM Memory Module Functional Block·
Diagram
59

1) The Addressing Phase, in which the desired memory
address 'is sent to the imm6-26 Card, where it is
decoded and used to enable the specific memory
location which is to be accessed.
2) The Data Phase, where the data is sent out from
the imm6-26 Card.
The Addressing Phase is executed in the following
steps:
al The Central Processor sends a Memory Address to
the imm6-26 Card Address Control Block.
b) The Address Control Block translates the Memory
Address into three types of signals: Module Enabling signals, which enable the selected 4K segment
of the memory; Block enabling signals, which
enable one 256 word block within the larger 4K
segment; and Address signals, which access one
word within the 256 word block.
c) The Control Block checks the selected memory
address, and determines if it exists on the imm6-26
Card. If it finds that it does not exist, it sends out
disabling signals which prevent further operations
with the imm6-26 Card. At the same time, it sends
out an enabling signal which can be used by an
imm6-28 Random Access Memory Card to enable
its operation.
The Operation Control Block generates the control
signals necessary to cause the contents of the selected
memory location to be sent from the Memory B lock to the
Memory Data Buffers, whence they are sent out to the
Centra I Processor.

THE imm6-26 PROGRAMMABLE READ-ONLY
MEMORY CARD-THEORY OF OPERATION
This section describes the theory of operation of the
imm6-26 Card in detail, giving the circuit-level implementation of the features.

Physical Memory Implementation
The actual memory of the imm6-26 Card is made up
to sixteen Intel 8702A Erasable Programmable Read-Only
Memory chips, each having a capacity of 256 eight-bit
words. This results in a basic memory block of 256 words.
Each 256 word block is a separate unit, and can be
changed by removing the existing PROM chip and installing
a new PROM, or omitted by removing the existing PROM
without replacement. NOTE: Only standard 8702A PROMs
can be used with the INTELLEC a/MOD 80 system; all
8702A PROMs must have access time less than or equal to
1.5 microsecond.
Since there are sixteen 256 word PROMs on each
imm6-26 Card, each card has a total capacity of 4,096
words. By combining more than one card in a system,
memory size can be increased in increments of 256 words.

Memory Address Decoding
Since more than 4,096 words of memory can be
addressed by a Central Processor, the imm6-26 card includes
address decoding circuits which allow a Central Processor
to select one imm6-26 memory card.
The Memory Address which the Central Processor
sends to the imm6-26 <;:ard consists of sixteen bits of information, organized as a binary number, with the low order
bit on line MADO and the high order bit on line MAD15.
The Address Decoding circuits use this sixteen-bit address
as follows:
1) Since the high order four bits of the Memory
Address effectively divide the possible memory
locations into sixteen units of 4,096 words each,
they are used to enable the particular card which is
to be used for a given memory operation. This
is accomplished by bringing lines MAD 12-MAD 15
onto the imm6-26 card edge pins, inverting them
to form MAD12-MAD15, and then sending these
inverted memory Address signals out on another
set of card edge pins. External jumpers are then
used to tie the proper combination of Memory
Address and inverted Memory Address signals to
the four inputs to the Access Enable Gate, MS12MS15. When the proper Memory Address is sent
to the imm6-26 card by the Central Processor, the
Access Enable Gate will produce a Module Enable
signal which is used to enable memory operations
for that card.
2) The next four bits of the Memory Address, MAD8MAD11, select one of the sixteen 256 word blocks.
These two signals are led to two three-to-eight line
decoders. Signal MAD11 is then used to enable
one of the two decoders, while MAD8-MAD10 are
used as inputs to the decoders. The decoders produce Chip Enable signals which are used to enable
one of the sixteen 256 word PROM chips on the
imm6-26 card.
3) The eight low-order bits of the Memory Address,
MADO-MAD7, are tied to Address Latches which
are enabled by the Module Enable Access Enable
Gate. They are then sent to all of the available
memory chips, which use them to enable the
proper location out of the 256 available.

Memory Read Operations
A Memory Read operation is initiated by the Central
Processor, which sends a sixteen bit Memory Address' to the
imm6-26 card. The address decoding circuits decode the
address to select one particular memory location.
The Central Processor also sends signal PROM MOD
ENBL to the imm6-26 card, enabling operations from that
card. This signal is used as an input to the Module Enable
Gate along with the Access Enable Gate signal MOD
DECODE, as shown in Figure 6-3. When all of the inputs to
the ModuJe Enable Gate are TRUE, it generates the PROM

by the address decoding circuits to generate chip enable
signals, are used as addressing inputs to the multiplexer. If
a PROM exists at the addressed location, the multiplexer
output will be HIGH. This output is led to the PROM
Resident Latch, which produces the PROM RESIDENT
signal. This signal is used as an enabling signal to the
Modul'e Enable Gate, and thus enables PROM operations
when there is a PROM present. Likewise, if there is no
PROM present in the addressed location, the output of the
multiplexer will be LOW, the PROM RESIDENT signal will
be FALSE, the Module Enable Gate output will be FALSE,
and imm6-26 operations will be disabled.

MOD SEL signal, which is sent to the two low-order
Address Decoders. It enables the decoders, and the proper
chip is enabled. The chip reads the low-order eight bits of
the Memory Address, and sends the data contained in the
selected memory location to the Memory Data buffers on
lines DO-D7. The Memory Buffers are also enabled by the
PROM MOD SEL signal, and will gate the data onto the
Memory Data Out lines MD1O-MD17. Timing is shown in
Figure 6-2.

Random Access Enable
Since it may be desired to mix Random Access and
Read-Only memories in a system, the imm6-26 card has
been designed to determine, for each memory operation,
whether or not PROM memory exists for the selected
Memory Address. If PROM memory does not exist for that
location, the imm6-26 card will generate an enabling signal
for Random Access memory which uses the same address.
If the two types of memories share common locations,
however, the Random Access enabling signal will not be
issued, giving the PROM memory priority.

When the Module Enable Gate output signal, PROM
MOD SEL, is FALSE, signal RAM MOD ENBL is produced
by the RAM Module Enable Latch. This signal may be used
to enable a Random Access memory device wh ich has the
same address as the PROM module.

THE imm6-26 PROGRAMMABLE READ-ONLY
MEMORY CARD - UTILIZATION
This section provides the information necessary to
efficiently use the imm6-26 card in an application.

Each PROM location on the imm6-26 card has a corresponding switch which is tied to one input of an eight
input multiplexer. In its normal position, this switch, and
thus its associated multiplexer input, is tied to +5v. When
a PROM is installed on the card, its corresponding switch is
depressed, causing the input to the multiplexer to be tied
to GROUND. When a memory operation is executed, the
four Memory Address lines MAD8-MAD11, which are used

Module No.
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Memory Addresses
0-4095
4096-8191
8192-12287
12288-16383
16384-20479
20480-24575
24576-28671
28672-32767
32768-36863
36864-40959
40960-45055
45056-49151
49152-53247
53248-57343
57344-61439
61440-65535

Memory Address Coding
In order to enable memory operations, the imm6-26
card must have an encoded address signation. The proper
positioning of external jumpers for each block of memory
as follows:

Jumper Pin Connections

Card Select Coding
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,
MAD12,

MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,
MAD13,

MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,
MAD14,

61

MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15
MAD15

---

57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,
57-58,
58-60,

61-62,
61-62,
59-61,
59-61,
61-62,
61-62,
59-61,
59-61,
61-62,
61-62,
59-61,
59-61,
61-62,
61-62,
59-61,
59-61,

63-64,
63-64,
63-64,
63-64,
64-66,
64-66,
64-66,
64-66,
63-64,
63-64,
63-64,
63-64,
64-66,
64-66,
64-66,
64-66,

67-68
67-68
67-68
67-68
67-68
67-68
67-68
67-68
65-67
65-67
65-67
65-67
65-67
65-67
65-67
65-67

PROM Installation, Removal, Programming,
and Erasure

mer card in conjunction with the Intellec 8 system. They
may be erased by exposing them to high intensity shortwave ultraviolet light at a wavelength of 2537A. After ten
minutes of such exposure, the PROM will be erased to all
zeroes. No more exposure than is necessary should be used,
to avoid damaging the PROM. (See the Intel Memory Design Handbook for more information regarding 8702A
PROM programming and erasure). CAUTION: When using
an ultraviolet source to erase the PROM, be careful not to
expose your skin or eyes to the ultraviolet rays because of
the damage which these rays can cause. In addition, shortwavelength ultraviolet light generates considerable amounts
of ozone, which is also potentially hazardous.

I n order to provide flexibility in memory assignment,
the imm6-26 card can be of any size desired, from 256
words to 4,096 words, in 256 word increments. rhis
flexibility is achieved by enabling installation and removal
of the individual PROM chips which make up the imm6-26
card's memory.
When installing PROM chips on the imm6-26 card,
the corresponding PROM Resident switch must be depressed.
If this is not done, the imm6-26 card will not be enabled
when that group of memory addresses is accessed. To install
a PROM, merely insert it into the socket provided on the
imm6-26 card. Likewise, to remove a PROM, merely pull it
from the socket. Again, if removing a PROM, ensure that
the corresponding switch is disabled. If this is not done,
faulty memory operations will ensue. If all of the sixteen
PROMs are installed on an imm6-26 card, the PROM
Resident signal can be permanently enabled by installing
the ALL RPOMS RESIDENT patch between points 1 and
2, as shown in Figure 6-3.

Note: When used in conjunction with an imm8-83 module
the 8702A type used must have an access time of
less than 1.5I1sec.

Installation Data and Requirements
Connector: Dual 50-pin, .125 in. centers
Input Voltage: +5v ± 5% @ 1.6A (max)
Operating Temperature: 0° C-70o C

The Intel 8702A PROMs used by the imm6-26 card
may be programmed by using the imm6-76 PROM Program-

SYNC

CLKA

ADDRESS

CHIP SELECT

DATA DUT

-----'

---In. . ______________..Jn

___

____

L _ _ _ _ _ _ _ __

~x~

______

"

~x~

/

_ _ _ _ _ _ _ _ _ _ _ _~X'_

______________

_______

NOTE: WAIT STATES PROVIDED BY !mm8-83

Figure 6-2. PROM Memory Module Timing

62

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64

I/O Data display operations, in which data used
for an input or output operation is displayed;

The INTELLEC S/MOD SO Control Console is designed to provide a user of the INTELLEC S/MOD 80
microcomputer development system with an easy to use
means of monitoring and controlling machine operation,
manually moving data to or from memory or input/output
devices, and running or debugging programs_ Since the
INTELLEC S System is specifically designed for microcomputer systems development, the Control Console has
several features which are not usually found on "traditional"
computer control consoles, e_g., extensive status displays
and special debugging aids_

Status display operations, which display indications of the operating mode of the Central
Processor;
Cycle display operations, which provide a continuous display of the 80S0 machine cycle;
Programmable display operations, in which the
contents of output port FF 16 are displayed_
2) Manual Memory Access operations, in which data
is read from or written into a selected memory
location from the Control Console rather than
the Central Processor.

This section describes the operation of the INTELLEC
S/MOD SO Control Console on two levels: first, on a general
functional level, second, on a more detailed theory of
operation leveL

3) Manual I/O Access operation~, in which input monitoring or output operation is performed from the
Control Console rather than the Central Processor.

Since the INTELLEC S/MOD SO Control Console has
been designed to support the imm8-S3 Central Processor
Card, many of its operations cannot be described without
referring to the operation of that card. It is an absolute
necessity, therefore, that Chapter 2 of this manual be read
and fully understood before attempting to read this section,
as it is in Chapter 2 that many of the basic concepts
necessary for a proper understanding of Control Console
operation are developed. If a more detailed description of
operational procedures using the Control Console is desired,
refer to the INTELLEC S/MOD SO Operator's ManuaL

4) Interrupt operations, in which an interrupt cycle
is initiated from the Control Console by the user.
5) Processor Control operations, which allow the user
to directly control the operation of the Central
Processor.
6) Sense operations, which allow the user to manually

enter data during a programmed input operation.
7) SearchIWait operations, which allow a selected
instruction to be executed a given number of
times, after which the Central Processor enters a
WAIT mode.

THE INTELLEC 8/MOD 80 CONTROL CONSOLE
- FUNCTIONAL DESCRIPTION

Each of these operational groups is discussed in a
separate subsection of this chapter.

This section provides a basic, functional overview of
INTELLEC S/MOD SO Control Console operation. The
operations performed by the Control Console can be
divided into seven groups, as follows:
1) Data display operations, including:

Data Display Operations

Memory Data display operations, in which the
contents of a selected memory location are displayed;

The INTELLEC 8/MOD SO Control Console can
perform five distinct data display operations_

65

• Interrupt
• Stack

• Status Display
• Cycle Display
• Address Display
• Instruction/Data Display
• Programmable Display

The eight cycle functions operate as follows:
1) The FETCH cycle display is Iit when the processor

The Status display functions provide a visual indication of the Processor's mode of operation. There exist eight
status display functions:

is executing an Instruction Fetch operation.
2) The MEM cycle display is lit when the processor
or the Control Console is executing a Memory
Access operation.

• Run
• Wait
• Halt
• Hold
• Search Complete
• Access Request
• Interrupt Request
• Interrupt Disable

3) The I/O cycle display is lit when the processor or

the Control Console is executing an I/O Access
operation.
4) The DA cycle display is lit when a Memory or I/O

Access operation is being performed from the
Control Console rather than by the processor.

The eight functions are performed in the following
manner:

5) The Read/Input cycle display is lit when either a

1) The RUN status display is lit whenever the Central

6) The Write/Output cycle display is lit when either

Memory Read or I/O Input operation is executed.
a Memory Write or I/O Output operation is
executed.

Processor is not waiting or stopped.
2) The WAIT status display is lit whenever the

7) The I NT cycle display is Iit when a processor

Processor is in a WAIT state (Le., waiting for data
to be input).

I nterrupt cycle is in progress.

3) The HALT status display

8) The STACK cycle display is lit when the processor

4) The· HOLD status display

The Address display function provides a visual display
of the address data used for a Memory or I/O operation.
There are sixteen address display lights, corresponding to
the sixteen address lines.

is lit whenever the
Processor is in a STOPPED state.

is accessing the stack.

is lit whenever the
Processor has acknowledged a Hold Request (as
for a direct memory or I/O access operation).

5) The SEARCH COMPLETE status display is lit

whenever a SearchllNait operation has been completed, and the passcounter has been counted
down to zero.

The Address display function is performed by tying
the processor memory address lines to the display lights
through a series of buffers.

6) The ACCESS REQUEST display is lit whenever a

The Instruction/Data display provides a visual indication of the instruction or data fetched from memory or the
data which is read from memory or an I/O device. There are
eight Instruction/Data display lights, tied to the processor
data bus.

Direct Memory or I/O Access request has been
made by depressing the Console Mem Access or
I/O Access switches.
7) The INTERRUPT REQUEST display is lit when-

The Programmable display function provides an indication of the contents of output port FF16.

ever an Interrupt Request has been made via the
Control Console Interrupt or Reset switches, and
is extinguished when the Processor acknowledges
the interrupt request.

Manual Memory Access Operations
A Manual Memory Access operation is performed in
order to read or write data to or from memory. It is accomplished via the following steps:

8) The INTERRUPT DISABLE display is lit when-

ever the processor has disabled its interrupt
capability.

1) The Mem Access switch on the Control Console is

The cycle display functions provide a visual indication
of the Processor machine state. There are eight cycle display
functions:
•
•

depressed, sending a control signal to the processor,
which"enters the HOLD state.
2) The memory address to be accessed is loaded into

Fetch
Memory

the Address/I nstruction/Data switches on the Control Console.

• I/O
• DA
• Read/Input
• Write/Output

3) The LOAD switch on the Control Console is de-

pressed, loading the Address/I nstruction/Data data
into the Address Register ..

66

4) The address held in the Address Register is sent to
the memory module on the memory address bus.

during the Interrupt operation is loaded into
Address/I nstruction/Data switches O· 7 on the Con·
trol Console.

5) The memory module responds by sending the data
currently held in the selected memory location to
the Control Console, where it is displayed by the
Instruction/Data display.

2) The Interrupt switch is depressed, generating an
Interrupt signal which is sent to the Central
Processor.
3) The Central Processor disables further interrupts
and enters an Interrupt cycle.

6) If it is desired to write data into memory, the
data byte to be written is loaded into the lower
eight Address/I nstruction/Data switches. Switch
DEP is then depressed, sending a control signal to
the memory module which causes the switch data
to be loaded into the memory address held by the
Address Register.

4) The Interrupt Instruction loaded into Address/
Instruction/Data switches 0·7 is sent to the Central
Processor, which executes it as a normal instruc·
tion.

Sense Operations

Note: The deposit at halt function is not implemented on
the INTELLEC 8/MOD 80.

A Sense operation is performed in order to manually
input data to the Central Processor while it is running a
user program. It is executed in the following steps:

The address held in the Address Register can be in·
cremented by one, by depressing the INC switch, or
decremented by one by depressing the DEC switch.

1) The data which is to be input is loaded into the
Address/Data 8·15 switches on the Control Con·
sole.

Manual I/O Access

2) The SENSE switch is depressed, generating a con·
trol signal which is sent to the Central Processor.

A Manual I/O Access operation is performed to allow
the user to send data to an output device, or read data from
an input device, by using the Control Console, rather than
the Central Processor. It is executed in the following steps:

3) The control signal causes the CPU to input the
data from the switches, rather than from an input
device, each time an Input instruction is executed.

1) The I/O Access switch on the Control Console is
depressed, sendi ng a control signal to the processor,
wh ich enters the HO LD state.

Search-Wait Operations
Search·Wait operations are a powerful debugging tool
which allows the user to execute a statement in his program
a certain specified number of times, from 0 to 256, and
then cause the. Central Processor to enter a WAI T "State,
wherein the contents of memory can be examined to ensure
proper program operation.

2) The I/O Address signifying the I/O device to be
used for the manual I/O access operation is loaded
into Address Data switches 8·15 on the Control
Console.
3) If an Output operation is to be performed, the
data byte which is to be output is loaded into
Address/I nstruction/Data switches 0·7.

A Search·Wait operation is executed in the following
steps:

4) The DEP switch is depressed.

1) The PASS COUNT, or number of times that an
instruction is to be executed, is loaded into
Address/I nstruction/Data switches 0·7.

5) The I/O Address and data are sent to the Input/
Output and Output modules, which then perform
the designated input or output operation.

2) The LOAD PASS switch is depressed, causing the
PASS COUNT to be loaded into the PASS register.

6) In the case of an input operation, the data from
the selected input port is displayed in the data
display light.

3) The address which is to be monitored is entered
into the Address/Instruction/Data switches and
the LOAD switch is depressed, loading the address
into the Adaress Register.

Interrupt Operations
An interrupt operation is performed in order to
cause the Central Processor to interrupt its normal sequence
of operations and to execute an interrupt instruction. Th is
instruction can be such that processor operation is directed
to a routine which will service the device originating the
interrupt.

4) Each time the referenced instruction address is
encountered by the CPU, a control signal is gen·
erated. This control signal decrements the Pass
Counter Register.
5) When the Pass Counter Register counts down to
zero, the processor will be forced into a WAIT
state if the SearchlWait switch has been depressed,
allowing the user access to the system memory.
This also causes the SRCH/COMP light to light.

A Control Console interrupt is executed in the
foil owi ng steps:
1) The Interrupt Instruction wh ich is to be executed

67

Processor Control Operations

1)
2)
3)
4)
5)
6)
7)

The Processor Control operations allow the user to
control the operation of the I NTELLEC 8/MOD 80 from
the Control Console There are eight Processor Control
functions:
1) Sense

Data Display operations
Manual Memory Access operations
Manual I/O Access operations
Interrupt operations
Processor Control Operations
Sense Operations
Search/Wait operations

2) Search/Wait

Data Display Operations

3) Deposit

There are five distinct data display operations:

4) Deposit at Halt (not used in the INTELLEC 8/
MOD 80 System)

• Status display
• Cycle display
• Address display
• Instruction/Data display
• Programmable display

5) Interrupt
6) Reset
7) Step/Continuous, which allows the user to cause
program execution to be performed one machine
cycle at a time.

All of these display operations utilize Light-Emitting
Diodes as their active display element. These diodes are
triggered by their input signal going to a LOW level.

8) Wait, which causes the processor to enter a WAIT
state.

The Status display functions are as follows:

The Wait function is executed by depressing the WAIT
switch on the Control Console. A control signal is then
produced which causes the Central Processor to enter a
WAIT state. Normal operations are resumed when the
switch is reset to its original position.

• Run
• Wait
• Hold
• Search Complete
• Access Request
• Interrupt Request
• Interrupt Disable

The Step/Cont function is dependent on the WAIT
function. Single-step operation cannot be performed unless
the WAIT mode is entered. Depressing the STEP/CaNT
switch generates a control signal which causes the CPU to
leave the WAIT state and execute one machine cycle. After
the cycle has been executed, the WAIT mode is reentered.

The display functions are executed as follows:
1) The R UN status display is Iit when the Central
Processor is running: i.e., when it is not in the
WAIT or STOPPED state. This is accomplished
by combining the two signals WAIT ACK, indicating the WAIT state, and HALT ACK, indicating a STOPPED state, through a NAND gate.
The resulting signal is inverted, producing the
RUN STATUS DISP signal which will go LOW
when the processor is running.

THE INTELLEC 8 FRONT PANEL CENTRAL
CONSOLE - THEORY OF OPERATION
This section describes the physical implementation of
the features described on page 65. Again, it is necessary that
Chapter 2 of this manual be understood in order to benefit
from this section.

2) The WAIT status display is lit when the Central
Processor is in the WAIT state. This is accomplished by using the WAIT ACK signal to produce
the WAIT STATUS DISP signal, which will go
LOW when the processor is in the WAIT state. In
normal operation, both the RUN and WAIT displays are lit simultaneously. This is because WAIT
states occur during all machine cycles, allowing
ample time for memory data to be returned to
the CPU.

The Intellec 8 Control Console is made up of three
modules:
•

The Front Panel Logic board, which holds Address
Registers, data multiplexers, data buffers, and the
Address Comparator.

•

The Display board, which holds the circuitry which
enables the Light-Emitting Diode displays.

•

The Front Panel Controller, which holds the logic
necessary to enable the proper performance of
Console function.

3) The HALT status display is lit when the Central
Processor is in the STOPPED state. This is accomplished by using the HALT ACK signal to produce
the HALT STATUS DISP signal, which goes LOW
when the processor enters the STOPPED state.

These three modules work together in order to perform all of the Control Console operations, and so in this
section they will be discussed as one unit_

4) The HOLD status display is lit when the Central
Processor has acknowledged a Hold Request. This
is indicated by the presence of signal HOLD ACK_

The seven operational groups discussed in this section
are:

68

This signal is used to form the HOLD STATUS
DISP signal, which goes LOW when a hold request
is acknowledged.

not occur simultaneously with a processor memory
access, so it is combined with DA ENBL, which
indicates a memory access in progress, and is then
tied to the same point as the two processor memory access signals.

5) The Search Complete status display is Iit whenever a Search/INait operation has been completed.
This condition is indicated by the presence of signal SRCH CMPL, which is inverted' to form
SRCH CMPL DISP.

3) The I/O Cycle display is lit when a processor or

Control Console I/O Access operation is in progress. The processor indicates this operation with
signal I/O CYCLE, which is buffered and tied to a
common point with the Console I/O Access Cycle
signal, which is produced by combining signals I/O
Access Mode and DA ENBL in a fashion similar to
that described above for memory access display
operations. This produces the I/O CYCLE DISP
signal.

6) The Access Request status display is lit whenever

a manual memory or I/O access has been requested
from the front panel. The two signals which are
produced by such requests are I/O Access Mode
and Mem Access Mode. These two signals are combined by a NOR gate and a NAND gate to produce the ACCESS REOUEST DISP signal.

4) The DA cycle display is lit during Control Console

7) The Interrupt Request status display is lit when an

memory or I/O access operation. A Control Console Access operation is always begun by requesting a HOLD operation. This fact is used to produce the proper signal by buffering the HOLD ACK
signal, which indicates a HOLD operation, to produce the DA CYCLE DISP signal.

Interrupt Request is made from the Control Console, and extinguished when the request is processed. This is accomplished by using the INT CTL
SW signal produced by the I nterrupt Request
switch, to set a D flip-flop, producing the INTR
R EO signal, indicating an interrupt request. This
signal is inverted to form INT REO DISP.

5) The Read/Input cycle display is lit whenever a

Memory Read or I/O Input operation is executed.
This is indicated by three signals: I/O IN, produced
during a Control Console I/O input operation,
MEM RD CYCLE, produced during a Processor
memory read operation, and also by the combination of the Memory Access Mode and DA ENBL
signals as described in the discussion of the Memory Cycle display. The first two of these three signals are buffered and then tied to a common point
along with the third, producing signal RD/IN
CYCLE DISP.

8) The Interrupt Disable status display is lit whenever

the CPU disables its interrupt capability. The INT
DSBL signal produces INT DSBL DISP.
When the Central Processor acknowledges the interrupt request, it enters an interrupt cycle, indicated by signal INT CYCLE. This signal is used to clear the flip-flop
set by the request, thus extinguishing the Interrupt Request
display.
The cycle display functions are:
•
•

Fetch
Memory

6) The Write/Output cycle display is lit when either a

memory write or I/O output operation is executed.
This is indicated by two signals: MEM WR CYCLE,
produced during a memory write operation, and
then the combination of I/O IN and I/O CYCLE,
which is true only during an I/O OUT cycle. These
signals are tied to a common point to produce signal WR/OUT CYCLE DISP.

• I/O
• DA
• Read/I nput
• Write/Output
• Interrupt
• Stack
The displays are as follows:

7) The Int cycle display is lit when an interrupt cycle
is in progress, which is accomplished by inverting
the INT CYCLE signal and combining it through
a NAND gate with the HOLD ACK signal which
indicates a HOLD operation, thus producing signal
INT CYCLE DISP.

1) The FETCH display is lit during a processor Instruction Fetch operation. This is indicated by the
FETCH CYCLE signal, which is passed through a
buffer to produce signal FETCH CYCLE DISP.
2) The Memory Cycle display is lit when either the
processor or the Control Console is executing a
Memory Access Operation. In the case of the processor, this is indicated by signal MEM RD CYCLE
or MEM WR CYCLE. These two signals are separately buffered and tied to a common point as
signal MEM CYCLE DISP. This is possible as both
signals cannot occur simultaneously. Similarly, the
Control Console signal MEM ACCESS MODE can-

8) The Stack cycle display is lit when the stack is being
accessed. The STACK CYCLE signal produces
STACK CYCLE DISP.
The Address display lights are lit either by the data
held in the Control Console Address Register, during a Memory Access operation, or by the data appearing on the Address/Instruction switches, during an I/O Access operation.

69

Manual 1/0 Access Operations

The choice of which set of data to use is made at a two-input
multiplexer. If neither operation is being performed, the
Address display is activated by the data on the Processor
Memory Address Lines MADO-MAD15.

A Manual I/O access operation is performed as follows:
1) The I/O Access switch on the Control Console is
depressed, causing signal HOLD REO to be generated by the Request Multiplexer and sent to the
processor.

The Instruction/Data display lights are lit by the data
appearing on the Processor Data Out lines DBO-DB7 except
during a Control Console data deposit operation, when they
reflect the contents of the first eight Address/lnstruction/
Data switches.

2) The processor gives control of the memory address
and control buses to the Control Console, and issues
signal HOLD ACK.

The Register/Flag display lights reflect the contents
of the Processor Register/Flag flip-flops.

3) The I/O Address signifying the I/O device to be accessed is loaded into AID switches 8-15. This data
is immediately gated onto the Memory Address bus,
and sent to the I/O modules. Data which appears
on the selected I/O device will be read onto the
the Data Out lines by signal I/O IN, produced by
the I/O ACCESS MODE signal, and will be
displayed.

Manual Memory Access Operations
Manual Memory Access operations are executed in
the following manner:
1) The Mem Access switch on the front panel is depressed. This causes the Request Multiplexer to
generate a HOLD REO signal, which is sent to the
Processor.

4) If an I/O Output operation is to be performed, the
data to be output is loaded into the first eight
A/I/D switches, and switch DEP is depressed. This
causes a deposit operation to be performed, except
that I/O OUT is produced rather than R/W.

2) The Processor responds to the HOLD request by
giving control of the memory address and control
buses to the Control Console, and issuing signal
HOLD ACK.

Interrupt Operations

3) The memory address to be accessed is loaded into
the Address/Instruction/Data switches on the front
panel.

An Interrupt operation is executed as follows:
1) The Interrupt Instruction wh ich is to be executed
during the Interrupt Cycle is loaded into the eight
Address/Instruction/Data switches on the Control
Console.

4) The LOAD switch on the front panel is depressed,
causing the switch data to be gated into the Address Register, a sixteen-bit up/down counter.
5) The data held by the address register are gated
through a multiplexer and fed onto the Memory
Address bus, and thence to the memory modules.

2) The Interrupt switch is depressed, producing signal
INT CTL SW, which sets the Interrupt flip-flop.
This flip-flop produces signal INT REO. This signal
causes the Request Multiplexer to issue signal INT
REO, which is sent to the processor. It is also used
to produce signal INT REOEN, which causes the
data placed in the switches to be gated through a
multiplexer and onto the Interrupt Instruction bus.

6) The memory module responds by sending the data
currently held in the addressed memory location
back on the Memory Data Input bus. The data is
then gated onto the Data Out bus, and is displayed
by the Control Console.

3) The processor entersan Interrupt Cycle, producing
signal INT CYCLE, which resets the Interrupt flipflop.

7) If it is desired to write data into memory the data
byte to be written is loaded into the lower eight
Address/Instruction/Data switches, and the DEP
switch is depressed. This causes the DEPosit flipflop to produce the DEP REO signal, which is combined with the SYNCA and MEM ACCESS mode
signals to produce the memory write signal R/W.
R/W is then used to clear the Deposit flip-flop,
producing a pulsed write signal. The data held in
the switches is gated onto the Data Out bus at the
same time, by signal DEP DAEN, produced by
combining the DEP REO and DA ENBL signals.
The data will thus be written into the selected
memory location.

Sense Operations
A sense operation is executed in the following manner:
1) The data which is to be input is loaded into the
8 Address/Data switches.
2) The Sense switch is depressed. This causes signal
SENSE REOEN to be generated, which causes the
swtich data to be placed on the Input Data bus. It
also produces signal IN JAM ENBL, which causes

70

the switch data to be input during an input operation, rather than the normal input source data.

5) When the Pass Counter reaches zero, it produces
signal SA CMP. This signal is used to set the Search
Complete flip-flop. This flip-flop's output causes
the Request Multiplexer to issue signal WAIT REO,
which causes the processor to enter a WAIT mode.

Search/Wait Operations
A Search/Wait operation is performed in the following
manner:
1) The pass count is loaded into the lower eight Address/Instruction/Data switches.

Processor Control Operations

2) The LOAD PASS switch is depressed, loading the
pass count into the Pass Counter, an eight-bit
counter.

Most of the processor control operations have been
previously discussed. Those which remain are the WAIT and
STEP/Continuous functions.

3) The address which is to be monitored is loaded into
the Address/Instruction/Data switches. The LOAD
switch is depressed, loading the switch data into
the Address Registers.

The wait function is executed by depressing the WAIT
switch on the Control Console. This produces the WAIT
MODE signal, which causes the Request Multiplexer to issue
signal WAIT REO, which causes the processor to enter the
WAIT mode.

4) The contents of the Address Register is compared
with the Memory Address buss by the SRCH ADR
comparator. Each time they coincide, signal ADR
CMP is produced. This signal is used to produce
PC STB, which is in turn used to count down the
Pass Counter by one.

If the WAIT mode is entered, the Step/Continuous
function becomes valid. Depressing the STEP/CaNT switch
causes the WAIT REOsignal to go FALSE for approximately
1 p.s., which enables the processor to execute one cycle of
operation, after which it again enters the WAIT mode.

71

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74

The INTELLEC 8 Chassis, Mother Board, and Power
Supplies are designed to provide the housing, interconnection, and power services for the INTELLEC 8/MOD 80
system.

INTELLEC 8/MOD 80 with one additional I/O or Output
module, and one additional memory module. If greater expansion is planned, maximum and typical current draw
should be totaled for all modules and the requirement for
an external supply evaluated. System Utilization has more
details concerning the use of the external power supply.

Since these three components of the INTELLEC 8
are, essentially, very simple, they will not be described in
detail.

The Mother Board is, simply, a printed circuit board
which has mounted on it the connectors which hold the
various cards which make up the INTELLEC 8/MOD 80
System. The layout of these connectors is such that certain
modules must occupy certain locations on the Mother
Board. The suggested arrangement is shown in Figure 8-1.

The INTELLEC 8/MOD 80 uses OEM power supplies.
One supplies -9V at 1.8 Amperes. A second furnishes +5V
at 12 Amperes. And the third supplies ±12V at 60 milliamperes. This is sufficient power to operate the standard

" ' - - - - - PROM, PROGRAMMER MOOULE

Figure 8·1. INTELLEC 8/MOD 80 Module Assignments.

75

76

The imm8-76 PROM Programmer Module is a standard module for the INTELLEC S/MOD SO system. When
used in conjunction with the INTELLEC 8/MOD SO System Monitor, the Programmer Module permits rapid, automatic loading of Intel 8702A Programmable Read Only
Memories.

mentary application of high amplitude pulses on selected
pins of the chip. The 8702A is cleared by a controlled
exposure to high intensity ultraviolet. The 8702A may be
reloaded as often as desired, making it suitable for use in
program development.
Programming of the 8702A requires a carefully controlled sequence of operations. The safety of the chip
demands that both the intermittent voltages and the duty
cycle of the programming pulses be maintained within specific limits. This insures against breakdown and overheating.
On the other hand, insufficient power levels will lead to
programming failures. An accurate balance is necessary.
The PROM Programmer Module is designed to provide
pulses of the correct level and duration, automatically.

The program to be transferred to a PROM is first
stored in the INTELLEC 8's program RAM memory. The
PROM to be programmed is erased, if necessary, and inserted in the programming socket on the Control and Display Panel. The PRGM PROM PWR switch is turned on, and
the console operator types a 'P' followed by parameters
which indicate the first and the last RAM addresses to be
transferred, as well as the starting address in the PROM.
The software does the rest. It transfers the eight bits
of the PROM address to output port 2. It sets up the data
to be written into the PROM, at output port 3. It pulses the
power supply the required number of times, at the required
duty cycle. And it checks the result of its programming by
reading the PROM's output through input port 2. If improper programming is indicated, the System Monitor prints
an exception notice at the teletype console. This programming cycle is repeated at each of the memory locations
bracketed by the initial and the terminal parameters. Complete programming involves the loading of 256 individual
locations, a process which requires approximately 2 minutes.
The procedure is described fully in the INTELLEC 8/MOD
80 Operator's Manual.

Appendix B of this manual contains full electrical
specifications for the Intel 8702A.
The 8702A is shipped to the customer in a "cleared"
condition; that is, with zeros in all memory locations. An
internal zero-state is indicated by a HIGH on the output
pins of an enabled chip. During progr.amming, ones are
loaded selectively into each of the chip's memory locations.
A 8702A which has been programmed previously
must be erased prior to reloading. Erasure is accomplished
by exposing the silicon die to ultraviolet light. The device is
made with a transparent quartz lid, to permit such exposure.
Conventional room light, flourescent light, and sunlight
have no measureable effect on data stored in the 8702A,
even after years of exposure. But the device is quickly
cleared by a brief exposure to high intensity ultraviolet at
a wavelength of 2537 Angstroms. The Model UVS-ll (Ultraviolet Products, Incorporated: San Gabriel, California) is a
cheap and effective source for this purpose. Its accompanying filter must first be removed. The recommended integrated does (the product of Intensity and the exposure
time) is 6W-sec/cm 2 . Ten minutes exposure to the UVS-l1,
at a distance of 1 inch, will clear the PROM completely.
Avoid unnecessary or prolonged exposures, wh ich are potentially damaging to the PROM.

The imm6-76 is designed for plug-in installation in the
INTELLEC 8/MOD 80 mainframe. It makes use of existing
connectors and other provisions. No special installation is
.necessary.

THE 8702A PROGRAMMABLE
READ ONLY MEMORY
The 8702A is a 256 x S bit electrically programmable
read-only memory, designed for use in limited quantity
OEM production. The 8702A is programmed by the mo-

77

4) 60 microseconds after the cycle begins, the address
data is switches from its complement form to its
positive-true form.

-WARNING High intensity ultraviolet can cause serious burns.
Ultraviolet radiation can also generate potentially hazardous amounts of ozone. Observe the following precautions,
when using the source to erase a PROM:

5) 155 microseconds after the cycle begins, the
PRGM signal dips from 47 Volts to approximately
9 Volts.

(1) Never expose skin or eyes to the source directly.
(2) Do not stare fixedly at an object which is under
ultraviolet illumination. The light is invisible, but
is nevertheless injurious to eye tissue.
(3) Use the source only in a well-ventilated area.

6) 3 milliseconds later, the PRGM signal returns to 47
Volts.
7) 3.25 milliseconds after the beginning of the cycle,
all voltages and signals are switched back to their
normal quiescent levels.
8) 15 milliseconds after the beginning of the first
cycle, the second cycle begins.

FUNCTIONAL DESCRIPTION
OF THE MODULE
An eight-line input, applied to the PROM's addressing
lines, specifies the location to be programmed. Data to be
written in that location is applied to the chip's eight output
lines. Then address lines, data lines, the PRGM pin, and all
four power lines (V cc , Vbb, Vgg , and VDD) are pulsed, to
fix the data in location. The procedure requires about 3
milliseconds, and the cycle is repeated 32 times at each of
the 256 memory locations. To prevent overheating of the
8702A, the Programmer Module maintains a 20% duty
cycle, and it therefore takes approximately 123 seconds to
program the entire chip.

Interface to the INTELLEC 8/MOD 80
Note that the timing relationships above are determined by control circuitry on the PROM Programmer
Module itself. The number of pulsed repetitions, however, is
determined by the controlling program. The INTELLEC
8/MOD 80 System Monitor contains a timing routine which
holds the PROM Programmer enabled for approximately
520 milliseconds, or 35 programming cycles, before stepping to the next memory location.
The ADDRESS IN lines on the Programmer Module
are connected to the INTELLEC 8/MOD 80 output port
#2. The DATA IN lines are conne<;ted internally to output
port #3. The INTELLEC 8/MOD 80 System Monitor writes
into these ports when a PROM is being programmed.

To perform the required functions, the imm6-76 contains an address driver bank, a data driver bank, four electronically controlled power supplies, and a control and
timing section.
The sequence of events is as follows:

When the Programmer Module is not actively programming a memory location, the contents of that location
are available at the module's DATA OUT pins. These
outputs are connected in turn to input port #2, so that the
INTi:LLEC 8/MOD 80 System Monitor can check the
results if its programming.

1) Data to be programmed into the PROM is placed
on the input lines, in complement (negative-true)
form.
2) Address to be programmed is placed on the address lines, in complement (negative-true) form.
3) When the programming cycle begins, the following
changes in the static conditions occur:

The PROM programmer module also has two negativetrue enabling inputs, which initiate the programming cycle.
A .LOW applied to pin #32 of the module selects a 20%
programming duty cycle. This input is used when programming8702A PROM. A LOW applied to pin#30 selects a
2% duty cycle, used when programming 8702A dllvice. In
the INTELLEC 8/MOD 80 system, pin #32 of the module
is connected to the BIT #7 line of RAM output port L1.
Pin #30 is connected to the BIT #6 line of the same output
port. The INTELLEC 8/MOD 80 System Monitor controls
the Programmer Module by writing into that port.

a) Vcc switches from 5 to 47 Volts.
. b) Vbb switches from 5 to 59 Volts.
c) Vgg switches from -9 to 12 Volts.
d) VDD switches from -9 to 0.6 Volts.
e) The programming signal (PRGM) goes from 0
to 47 Volts.
f) Address data changes from 0-5 Volts to 0-47
Volts.

78

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THEORY OF OPERATION OF
THE MODULE

leaving the imm8-76. The output will therefore be in
complementary form, as required for the programming of
the 8702A PROM.

Refer to Figure 9-1, the PROM Progra mmer SchelJlatic.

Observe that the bases of the PROM data driver
transistors are returned through pull-up resistors to the +5
Volt supply. As a result, these transistors will be conducting
whenever the input NAND-gates are inhibited. Under these
circumstances, the signal at each of the PROM's data pins
will be applied to the base of a transistor, through a divider
consisting of a 100-ohm resistor, the DC collector resistance
of a driver transistor, and a 1 K resistor. Transistors 020,
016, 012, 08, 018, 014, 010, and 06 amplify this
eight-line signal and forward it to an XOR-gate bank which
is used as an eight-line data inverter. The outputs of the
XOR-gates are applied to eight NAND-gates which have
their alternate inputs tied in common to the +5 Volt
supply. These gates are permanently enabled, and also act
as data inverters. The output of these gates is in positivetrue form. It is routed out of the assembly at J 1, through a
ribbon cable to Jl on the INTELLEC 8/MOD 80's motherboard, and terminates at input port #2. The INTELLEC
8/MOD 80 System Monitor reads this port, to determine
the results of its programming.

Data Distribution
The data to be programmed into the PROM enter
originates at output port #3. This eight-line signal enters
the Programmer Module through a ribbon cable which runs
from Jl on the I NTE LLEC 8/MOD 80 motherboard to J 1
at the top of the module. Each of the input lines is applied
to one input of an XOR-gate. The alternate inputs of these
eight gates are returned through a common line to the +5
Volt supply, so that each gate acts as an inverter to the
incoming data.
Each of the XOR-gate outputs is directed to one
input of a 7403 NAND-gate. The alternate inputs to this
bank of gates are driven in common by a signal originating
in the control and timing section of the module. At the
appropriate time in the cycle, these inputs are permitted to
swing HIGH, causing data from the XOR-gate bank to pass
through to the bases of eight driver transistors: 019, 015,
011, 07, 017, A 13, A9, and 05. The signal at the
collectors of these drivers is conducted out of the assembly
through a ribbon cable which attaches to J2 at the top of
the module. It goes from there to the programming socket
on the front panel of the INTELLEC 8/MOD 80. This data
undergoes three successive inversions, between entering and

Address data enters the module at J 1, through a
ribbon cable connecting it to Jl of the INTELLEC 8/MOD
80's motherboard. Data originating at output port #3 is
therefore applied to the eight-line XOR-gate bank, shown
on the right in Figure 9-1. The outputs of these gates are

15/150 mS
-·--3.25mS
155,.5 _ _

3.0 mS

PRGM 1#13)

---.l

Vee, 1#12)

Vbb

Vgg

1#15)

1#16)

VDD 1#24)

All (7)

ADDRESS
DATA

r

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1,.-

+47 V
+4.7 V
OV

\

+47 V

-1
-1
-1

\
\
\

+59 V

-

\

~

~
dJ'

~-------------------------

Figure 9-2. PROM Programmer Timing

80

+4.7 V

+4.7 V
+12 V
-9 V
+0.6 V
-9 V

+47V
+4.7 V
OV

directed to the bases of eight driver transistors, whose
outputs command the PROM address lines. Note that the
alternate inputs of the XOR-gates are tied in common to a
signal line from the control and timing section. This line
swings LOW when the programming cycle begins. It returns
to a HIGH condition 60 microseconds later. As a result, the
address forwarded to the PROM is in complementary form
initially. Sixty microseconds after the programming cycle
begins, the address data will switch to its positive-true form,
in accordance with the PROM's programming requirements.

3) Pulses all four power supplies.
4) Triggers a 155 microsecond cascaded one-shot
delay.
Sixty microseconds after the program cycle one-shot
fires, the negative-going pulse output at A11-7 subsides, and
the address data returns to its positive-true form.
One hundred fifty-five microseconds after the program cycle one-shot fires, A 12-9-10-11-12-13-14 fires,
causing the power supply to apply a 3 millisecond PRGM
pulse to the PROM.

Control and Timing

Three and a quarter milliseconds after the beginning
of the programming cycle, all signals return to their quiescent levels.

As shown in Figure 9-1, the programming cycle may
be initiated by a LOW applied to pin #32 or to pin #30 of
the card. The INTELLEC 8/MOD 80 System Monitor
enables the pin #32 input, selecting a duty cycle of 20% (3
mS/15 mS). The pin #30 input is set up for the 2% duty
cycle to program 8702 devices.

The Programmer Module's control timing is illustrated in Figure 9-2.

Power Supply

When a LOW is applied to pin #32 of the module, the
15 mi Ilisecond input multi vibrator re-triggers itself repetitively, until the enabling signal is removed. This provides a series of positive-going excursions with a period of
15 milliseconds, which are used to trigger the 3.25 millisecond program cycle one-shot.

The power supply section of the PROM Programmer
Module performs the level switching functions required to
program PROMs, in response to signals which are generated
in the timing and control section of the module. The power
supply contains a rectifier section, a voltage regulator
section, a regulator control section, and six output
switches. The relationship among these is shown in a
simplified form, in Figure 9-3.

The output of the program cycle one-shot:
1) Complements the address to the PROM.
2) Enables the data drivers.

VR5
035

,----t

Vbb (+5/+59 VOC)

CR11-CR12

PROG

027

(3mS)

50VAC

---

REGULATOR
030

RECTIFIER

CR7

N
VI

.. L

CR3-CR6

PRGM (+47/+9 VDC)

-

Vee (+5/+47 VDC)

~

025

r--

CS 10/+47 VDC)

BIAS
V/REG

PROTECT

VR1

A17/033

VR2/029

2~
Vgg 1-9/+12 VDC)

PRGM PROM
PWR ___
(FRONT PANEL)

BIAS

+5V

CLAMP

CLAMP

032/034

026/028

CR10

~-10V

PROG

036

CYCLE

037

(3.25 mS)

CRB

Figure 9-3_ Power Supply Functional Block

81

VDD (-9/+0.S VDC)

protected against short·circuit overloads, by a bias protec·
tion circuit consisting of 029 and the Zener diode VR2~
Under ordinary operating conditions, 029 will be off, and
the reverse voltage applied to VR2 will be insufficient to
cause this diode to conduct. In the event of a short·circuit,
however, the voltage drop across 030 will rise sharply. VR2
will begin conducting when the voltage across 030 approaches 36 Volts, applying a forward bias to 029. As a
result, the voltage at 029's collector will drop, clamping the
base of 030 to a relatively low level, and limiting the
current output from the supply.

RECTIFIER AND REGULATOR
The Programmer Module receives a 50 VAC/60 Hz
input, from two 25 Volt transformers which are located on
the INTE LLEC 8/MOD 80's chassis. The secondaries of
these transformers are connected so that their outputs are
series additive, and the 50 Volt output thus obtained is
routed to the Programmer Module through J3. A full·wave
bridge consisting of diodes CR3·CR6 rectifies the 50 Volt
input to produce a +80 Volt DC output.
The +80VDC output of the rectifier is applied to a
series regulator, 030, shown in the upper left hand corner
of Figure 9·1. The output voltage at the emitter of 030
depends upon the signal at its base. This level is determined
in turn by a regulator loop which consists of an integrated
voltage regulator (A 17), 033, and 030 itself.

SCR1 is a crowbar switch, used to protect the PROM
being programmed from an over·voltage condition in the
supply. The normal voltage level on the VCCS line (+47.6
Volts) is insufficient to cause conduction in Zener diode
VR3. Should VCCS rise above +56 Volts, however, the
diode will conduct, forward biasing the gate of the SCR.
SCRl short·circuits the output of the rectifier, and the
over·current condition blows fuse F2, interrupting AC
power to the Programmer Module. Capacitor C 16 provides
an alternate gate current path, to prevent dv/dt triggering of
the SCR when power is initially applied.

Figure 9-4 shows a simplified equivalent of the
regulator loop. Components within the broken lines are
part of the Signetics 550 monolithic voltage regulator.
The loop input is obtained from the regulator's
output, through an adjustable resistive divider (R91 and
R100). This level is applied to the non·inverting input of an
operational amplifier which is incorporated into A 17. The
output of the amplifier drives a common·emitter stage, also
contained within A 17, and the inverted output at A 17·11 is
applied externally to the emitter of 033. 033's collector
drives the base of the series regulator 030, completing the
negative feedback loop.

REGULATOR CONTROL
Refer again to Figure 9·3, the power supply functional
block. Note that the bias on 030 is subject to the condition
of a clamp. The clamp circuit consists of 032, 034, CR 10,
and associated components. These are used to switch the
regulator output on and off, producing the pulses required
for the programming of the PROM.

In a stabilized configuration such as this, the opera·
tional amplifier tends to maintain an output which results
in zero error, where the error is the potential difference
between the amplifier's inverting and non·inverting inputs.
Note that the inverting input is tied to the 550's internal
reference (approximately 1.63 Volts). In order to obtain
the desired output from the regulator, the resistive divider
is adjusted for a zero error when the regulator's output is
approximately +47.6 Volts.

The base of 034 is returned to the +80 Volt source,
through pull·up resistor R92 (refer to Figure 9·1}. Under
static conditions, this transistor will conduct through
CR10, clamping the base of 030 to a low value. As a result
of the low forward bias, 030 displays a high impedance,
and the output of the regulator will therefore drop to a
very low value.

Refer to the schematic for the PROM Programmer
Module, Figure 9·1. Observe that the series regulator 030 is

+80V - r - -_____

CR7

The PRGM PROM PWR switch is located on the
Console and Display Panel of the INTELLEC 8/MOD 80.
Contacts of the PRGM PROM PWR switch ground the base
of 034 when that switch is turned on. This turns 034 off,
enabling the regulator.

+47.S V

r-~~--~---------------- OUT

The regulator's output remains clamped, however, by
the conduction of 032. This transistor is commanded by
the control and timing section of the Programmer Module.
The 3.25 millisecond output of the program cycle one·shot
turns 032 off at the start of the programming cycle. With
both 032 and 034 disabled, the bias on 030 rises to the
stable level established by the characteristics of the regula·
tor loop. The output of the regulator rises in consequence.

11

r---- --I

~____
51~

SG 550

:

I
I

I
I

VR-S

I
I
I

OUTPUT SWITCHES
When no program cycle pulse is present, the regula·
tor's output is at a low level. Diode CR7 is reverse biased,
and the output voltage on the VCCS line is determined by
the clamp circuit consisting of 026 and 028. Under these

Figure 94. Voltage Regulator Loop: Simplified Schematic
Equivalent
82

conditions, 026 operates in the reverse beta mode, holding
VCCS to approximately +4.7 Volts. When the program
cycle begins, the control and timing section applies a
negative·going 3.25 millisecond pulse to the base of 028,
turning that transistor off. 026 now operates in a conventional manner, turned off by the low bias developed across
R88. With the clamp removed, the VCCS line is free to
follow the rising output of the regulator section. CR7
conducts, and the VCCS line rises to approximately +47
Volts.

the programming cycle, the PRGM output follows. One
hundred fifty-five microseconds after the start of the cycle,
the control and timing section sends a 3 millisecond
program pulse to the base of 027. This positive-going pulse
turns the transistor on, and the voltage at its collector falls
to approximately +9 Volts. Three milliseconds later, the
PRGM output returns to +47 Volts, where it remains until
the end of the programming cycle.

Observe that the collectors of both the address drivers
and the data drivers are returned to the VCCS line, through
their individual load resistors. Thus the normal 0 to 5 Volt
logic excursion which prevails under static conditions
changes to a 0 to 47 Volt excursion during programming.
This is an accord with the electrical requirements of the
PROMs.

UTILIZATION
This section describes the utilization of the imm6-76.

Installation
The PROM Programmer Module is designed for plugin installation in the INTELLEC 8/MOD 80. No special
installation is necessary.

As VCCS rises, 025 goes into conduction, causing the
level at the CS output to go from 0 Volts to +47 Volts.

Plug the printed circuit board into J 16 on the
INTELLEC 8/MOD 80's motherboard. A ribbon cable
connects J1 at the top of the module to J1 on the
motherboard. A second ribbon cable connects J2 on the
module to the programming socket on the front panel of
the INTELLEC 8/MOD 80.

Under static conditions, conduction through R89
holds the Vgg output to approximately -10 Volts. The 15
Volt drop across VR1 is not sufficient to induce an
avalanche in the Zener. During programming, however,
VCCS rises to +47 Volts and the diode goes into conduction. As a result, Vgg rises to +11 Volts, approximately 36
Volts below the level on the VCCS line.

An umbilical cable, permanently attached to the
module, plugs into J34 on the INTELLEC 8/MOD 80's
motherboard. This connection supplies AC power to the
Programmer Module.

The VDD output is held to a static level of -10 Volts,
by conduction through 036. When programming begins, a
negative-going program cycle signal is applied to the emitter
of 037. The negative-going transition at its collector is
coupled to the base of 036, and 036 turns off. CR8
conducts, causing VDD to rise to about 0.6 Volts.

Refer to the INTELLEC 8/MOD 80 Operator's
Manual for instructions on the programming of PROMs
using the INTELLEC 8/MOD 80 System Monitor.

Power Requirements

Under static conditions, the clamp transistor 032 is
conducting, and 035 is turned off by the low voltage
applied to its base through diode CR 12. The Vbb output
line is tied to VCCS through R87, and the quiescent voltage
I~vel at this point is approximately +4.7 Volts. When the
program cycle pulse turns 032 off, CR5 conducts, and the
voltage at the base of 035 rises to the vicinity of +60 Volts.
The emitter of 035 follows this excursion, and CR5
conducts, pulling Vbb up to a level of +59 Volts.

This module requires power at the following levels:
a) 50 VAC
b) +5 ±5% VDC@ 1.0A (max)
c) -10 ±5% VDC @ O.2A (max)
The 50 VAC source shares a fuse with the -9 Volts
supply in the INTELLEC 8/MOD 80. This 0.5 Ampere fuse,
F2, is located on the INTE LLEC 8/MOD 80's rear panel.

Pin List

The PRGM line is connected to VCCS through R78,
and the static level at this output is approximately +4.7
Volts_ When VCCS rises to +47 Volts, at the beginning of

Connector pin allocations on the PROM Programmer
Module are given in Tables 9-1, 9-2, 9-3, and 9-4.

83

Pl PIN LIST
PIN

1
2
3
4
5
6
7
8
9

PIN

SIGNAL FUNCTION

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71

GROUND
GROUND

10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

SIGNAL FUNCTION

72

73
74
75
76
77

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

R/W (1701)
R/W (1702A)

-10 VDC
-10 VDC

100

Table 9-1_

84

+5 VDC
+5 VDC

J1 PIN LIST

J2 PIN LIST

PIN

SIGNAL FUNCTION

PIN

SIGNAL FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

DATA 0 IN
ADDRESS 0
DATA 1 IN
ADDRESS 1
DATA 21N
ADDRESS 2
DATA 31N
ADDRESS 3
DATA 4 IN
ADDRESS 4
DATA 5 IN
ADDRESS 5
DATA 6 IN
ADDRESS 6
DATA 7 IN
ADDRESS 7
TEST DATA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49·
50

PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM
PROM

Table 9-2.

IN
IN
IN
IN
IN
IN
IN
IN
OUT 0

TEST DATA OUT 1
TEST DATA OUT 2
TEST DATA OUT 3
TEST DATA OUT 4
TEST DATA OUT 5
TEST DATA OUT 6
TEST DATA OUT 7
+5
+5
+5
+5
+5
+5
+5
+5

VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC

DATA OUT 0
ADDRESS OUT
DATA OUT 1
ADDRESS OUT
DATA OUT 2
ADDRESS OUT
DATA OUT 3
ADDRESS OUT
DATA OUT 4
ADDRESS OUT
DATA OUT 5
ADDRESS OUT
DATA OUT 6
ADDRESS OUT
DATA OUT 7
ADDRESS OUT

Table 9-3.

J3 PIN LIST
PIN

50 VAC (01)
0
1
2
3
4
5
6
7

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Table 9-4.

85

SIGNAL FUNCTION

50 VAC (02)
+80 VDC OUT
PROGRAM PROM POWER
GROUND

86

input ports and 16 output ports (when four imm8-61 I/O
Modules are used) or up to 4 input ports and 28 output
ports (when one imm8-61 I/O Module and three imm8-63
Output Modules are used). The ports can be assigned to
specific modules as shown (lower left)_

This section gives the information necessary to install
and operate the INTELLEC 8/MOD 80 system in an
application. It is divided into four subsections.

INTELLEC S/MOD SO INSTALLATION

All of the data ports complement data to and from
the CPU, and are TTL compatible. Note that the two input
ports (0 and 1) and two output ports (0 and 1) used for
Teletype communications are not available to the user. The
data from the other ports is brought, via flat cables, to the
back panel of the INTELLEC 8/MOD 80, where it is made
available on 37 pin jacks (see Figure 10-1). External devices
may connect to these jacks using AMP 205210-1 plugs.

Installation of the INTELLEC 8/MOD 80 is very
simple, as it is delivered in a ready-to-use condition. Simply
set it on a convenient surface, plug the 110v supply cord
into the nearest 11 Ov AC socket, and connect any desired
peripherals, and it is ready to use.
The Bare Bones 80 is almost as simple to install, as it
has been designed to mount in any standard 19-1/2 inch
RETMA panel.

The standard INTE LLEC 8/MOD 80 comes equipped
with only one Input/Output card, providing four input
ports and four output ports. A table of the data signals
associated with these ports is given in Table 10-1.

SYSTEM I/O INTERFACING
This section provides the information necessary to
properly interface external input and output equipment to
the INTELLEC 8/MOD 80. Since most of the interfacing
requirements are supplied by the internal Input/Output and
Output cards, interfacing is not a complex task; however,
there are certain procedures which must be followed in
order to assure the proper operation of any external devices
used.

In order to ensure the proper transmission of data
through a twisted cable of 12 feet (maximum), the user
should provide circuitry which will assist in reducing signal
noise. It is suggested that each output line be provided with
a filter network and pullup resistors. The filter is made up
of a 200 ohm resistor and a .001 /1f capacitor, and the
pullup resistor should be 1 K ohm.

The INTELLEC 8/MOD 80 can support up to 16
ModuleLocation
1/0#0
1/0#1
1/0#2
1/0#3
OR
* 1/0#0
OUT#l
OUT #2
OUT#3

Also, 7404-type drivers are suggested for each input
data line. These drivers should, preferably, be opencollector type devices. If input ports 2 or 3 are used,
open-collector devices must be used, as these ports are
shared with the PROM Programmer during programming,
transfer and compare PROM operations. The user must
disable his input drivers when PROM programming
operations are being performed.

Ports
Input
Input
Input
Input

ports 0-3; output ports 0-3
ports 4- 7; output ports 4-7
ports 8-11; output ports 8-11
ports 12-15; output ports 12-15
OR

Input ports 0-3; output ports 0-3
Output ports 16-23
Output ports 8-15
Output ports 24-31

INTELLEC S/MOD SO SYSTEM
OPERATING REQUIREMENTS
In order to ensure proper performance, certain requirements must be met in operating the INTELLEC
8/MOD 80.

*Note that in this configuration none of the output ports
respond to add resses 4-7.

87

6

7

8

"...c

5

4

3

Iii"

...
9...

1/'" "",,0'.'''''
(CuT)

CD

o

0
. . ... ,Pu..... ,;"'00. 'i..

z
....
m

j~

(

rj.·~~

r
r
m
(")
co

...",...

-

P 41

_

f'IA,'~

... DO

?"..l

"""-,l~

J 4'

3:
0
0

co

0
:J:I

CD
I»

...

c

C

~
::s
!i.
CIO
CIO

[J]

0
0

B

~J"

$CJ~

~

Ell

0\:':7

S\

~~~ 1_~"'"

IS
I""

::,. ...... 'l>. ... ,

el ~(

LO;:'

~t~:1

..

B

?~':]~

el
el

~

A

A

8

7

6

5

4

3

2

I/O Port Assignments-Module I/O 0

SIGNAL

SYMBOL

BACK PANEL
CONN. PIN #

COMMENTS

(3)

MODULE
PIN #
J5

UART XMIT DATA 0

(1 )

OUTPUT PORT 00, BIT 7

OPOO, 0
1
2
3
4
5
6
OPOO, 7

UART XMIT DATA 7

(1)

2
3
4
5
6
7
8
9

OUTPUT PORT 01, BIT O·
1
2
3
4
5
6
OUTPUT PORT 01, BIT 7

OP01,O
1
2
3
4
5
6
OP01,7

RDR ADV-l
PUNCH COMMAND
READER COMMAND
DATA OUT ENBL
DATA IN
DATA OUT
Rffl
RfflA

10
11
29
30
12
13
31
32

11
12
13
14
15
16
17
18

OUTPUT PORT 02, BIT 0
1
2
3
4
5
6
OUTPUT PORT 02, BIT 7

OP02,O
1
2
3
4
5
6
OP02,7

PROM ADR IN 0
1
2
3
4
5
6
PROM ADR IN 7

(2)

(2)

20
21
22
23
24
25
26
27

OUTPUT PORT 03, BIT 0
1
2
3
4
5
6
OUTPUT PORT 03, BIT 7

OP03,O
1
2
3
4
5
6
OP03,7

PROM DATA IN 0, PUNCH DATA
1,
2,
3,
4,
5,
6,
PROM DATA IN 7, PUNCH DATA

14
15
33
34
16
17
35
36

29
30
31
32
33
34
35
36

1,18,19,20,37

37-40

OUTPUTPORTOO, BITO

GROUND

NOTES:
(1) Dedicated to UART/TTY operations and unavailable to user.
(2) Dedicated to PROM Programming Operation and unavailable to user.
(3) Back Panel Connector Signals appear at both LOC 3 and LOC 4.

Table 10-1.

89

0
1
2
3
4
5
6
7

1/0 Port Assignments-Module 1/0 0

SIGNAL

SYMBOL

INPUT PORT 0, BIT 0

IPO,O

1

1
2

2

COMMENTS

BACK PANEL
CONN. PIN #

MODULE
PIN #
J4

(1)

2

TTY RCV DATA 0
1
2

3
4

5
6

3

3

3

4
5

4

4

5
6

5

7

6
TTY RCV DATA 7

8
9

6
INPUT PORT 0, BIT 7

IPO, 7

INPUT PORT 1, BIT 0
1
2
3

IP1,0
1

4

4

2
3

5

5

6
INPUT PORT 1, BIT 7

6
IP1,7

INPUT PORT 2, BIT 0

IP2,0

1
2
3
4
5

1
2
3

4
5

(1)

DATA AVAILABLE
OVERRUN ERROR
TRANSMIT BUFFER EMPTY
FRAMMING ERROR
PARITY ERROR (INHIBITED)
DATA AVAILABLE (TAPE READER)
PUNCH READY

PROM DATA OUT (J3-16)
(
15)
(
14)
(
13)
(
12)

2

11

3
21

12

24

13
14
15
16
17
18

(2)

20

22
4

5

23

21

22
23
24

11 )

25

INPUT PORT 2, BIT 7

6
IP2,7

(
10)
PROM DATA OUT (J3- 9)

26
27

INPUT PORT 3, BIT 0

IP3,0

READER DATA 0

1

1
2

1

6

2

3
4
5
6
INPUT PORT 3, BIT 7

(

(2)

2

25

29
30
31

3
4
5

3

26

32

4
5

8
9

33

6
IP3,7

6
READER DATA 7

27
28

6
7

1,18,19,20,37

GROUND

NOTES:
(1) Dedicated to UART/TTY operations and unavailable to user.
(2) Dedicated to PROM PGMR and unavailable to user.
(3) Back Panel CONNECTOR Signals appear at bothLOC 3 and LOC 4.

Table 10-1 (cont.).

90

34
35
36

37-40

1/0 Module To Back Panel Interface Chart
SIGNAL/MODULE

CONNECTOR

OUT 2

I/O 1

OUT 3

IN
(J4)

OUT
(J5)

OUTL
(J2)

OUTH
(J3)

OUTL
(J2)

OUTH
(J3)

LOC3

LOC1

LOC8

LOC6

LOC9

LOC7

IP4

OP05

OP09

OPOD

OP11

OP1C

IP4

OP05

OP09

OPOD

OP11

OP1C

-

--

OP06

- -OPOA OPOE

-OP12

OP1D

IP5

OP06

OPOA

OPOE

OP12

OP1D

--

- OPOB
OPOF

-OP1A

OP1E

OPOB

OP1A

OP1E

OP10

OP1B

OP1F

OP10

OP1B

OP1F

IP5

I
IP6

IP6
IP7

-

IP7

OP07

-OP07

OPOF

-- -- -OP08

OP08

OPOC

-OPOC

BIT

No.

91

MODULE
CONN PIN #
(Flat Cable)

0
1
2
3
4
5
6
7

2
3
21
22
4
5
23
24

2
3
4
5
6
7
8
9

0
1
2
3
4
5
6
7

6
7
25
26
8
9
27
28

11
12
13
14
15
16
17
18

0
1
2
3
4
5
6
7

10
11
29
30
12
13
31
32

20
21
22
23
24
25
26
27

0
1
2
3
4
5
6
7

14
15
33
34
16
17
35
36

29
30
31
32
33
34
35
36

GND

Table 10-2

BACK PANEL
CONN PIN #

1,18,19,20,37

37-40

EXTERNAL DEVICE CONTROLLER
INTERFACING

First, never operate the INTELLEC S/MOD SO with
the cover off. If this is done, the proper flow of air will be
disrupted, resulting in the burning-out of the internal power
supplies.

The INTELLEC S may be used with external devices
such as disks, etc., which require a Direct Memory Access
capability. This is accomplished by the TRI-State capability
of the processor memory address and control buses, which
can relinquish their control of tNTELLEC operations to an
external device.

Second, use extreme care when removing or installing
individual circuit cards in the INTELLEC S/MOD SO,
especialty Input/Output board #1. The PROM Programmer
and Teletype connectors to I/O board a are very easily
damaged, and are located very close to I/O board #1.

92

Data in the 8080 is stored in the form of 8-bit
binary integers:

• Direct - Bytes 2 and 3 of the instruction contain
the exact memory address of the data
item (the low-order bits of the address
are in byte 2, the high-order bits in style
3).

ID7 I D6 I D5 I D4 I D3 I D2 I D1 I Do I
DATA WORD
The 8080 program instructions may be one, two or
three bytes in length. Multiple byte instructions must be
stored in successive memory locations; the address of the
first byte is always used as the address of the instruction.
The exact instruction format will depend on the particular
operation to be executed.
Single Byte Instructions

ID7

Do lop Code
Two-Byte Instructions

ID7
Byte Two ID7

Byte One

I Data or

Address

Three-Byte Instructions

ID7
Byte Two ID7
Byte One

ByteThreel D7

DO
Do

It

•

Register

•

Immediate - The instruction contains the data itself. This is either an 8-bit quantity or a
16-bit quantity (least significant byte first,
most significant byte second).

Indirect - The instruction specifies a
register-pair which contains the memory
address where the data is located (the
high-order bits of the address are in the
first register of the pair, the low-order
bits in the second).

• Direct - The branch instruction contains the address of the next instruction to be executed. (Except for the 'RST' instruction,
byte 2 contains the low-order address and
byte 3the high-order address.)

I Do lop Code
I

Register - The instruction specifies the register or
register-pair in which the data is located.

Unless directed by an interrupt or branch instruction,
the execution of instructions proceeds through consecutively
increasing memory locations. A branch instruction can specify the address of the next instruction to be executed in
one of two ways:

Do lOp Code
DO

•

D,w
or

I Address

• Register Indirect - The branch instruction indicates
a register-pair which contains the address
of the next instruction to be executed.
(The high-order bits of the address are in
the first register of the pair, the low-order
bits in the second.)

Addressing Modes:
Often the data that is to be operated on is stored in
memory. When multi-byte numeric data is used, the data,
Iike instructions, is stored in successive memory locations,
with the least significant byte first, followed by increasingly
significant bytes. The 8080 has four different modes for
addressing data stored in memory or in registers.

The RST instruction is a special one-byte call instruction (usually used during interrupt sequences). RST includes
a three-bit field; program control is transferred to the instruction whose address is eight times the contents of this
three-bit field.

vii

REGISTER NAME

DOD or SSS

Condition Flags:

000
001
010
011
100
101
110

There are five condition flags associated with the
execution of instructions on the 8080. They are Zero,
Sign, Parity, Carry, and Auxiliary Carry, and are each represented by a l-bit register in the CPU. A flag is "set" by
forcing the bit to 1; "reset" by forcing the bit to O.
Unless indicated otherwise, when an instruction affects a flag, it affects it in the following manner:
rp
Zero: If the result of an instruction has the val ue 0,
this flag is set; otherwise it is reset.

SP represents the 16-bit stack pointer
register.
RP

Symbols and Abbreviations:

8-bit data quantity

data 16

16-bit data quantity

byte 2

The second byte of the instruction

byte 3

The third byte of the instruction

r.rl.r2

One of the registers A,B,C,D,E,H,L

DDD,SSS

The bit pattern for one of registers A,B,
C,D,E,H,L (DOD = destination, SSS =
source) :

REGISTER PAIR

00
01
10
11

B-C
D-E
H-L
SP

The first (high-order) register of a designated register pa ir.

rl

The second (low-order) register of a designated register pair.

PC

16-bit program counter register (PCH and
PCl are used to refer to the high-order
and low-order 8 bits respectively).

SP

16-bit stack pointer register (SPH and SPl
are used to refer to the high-order and
low-order 8 bits respectively).
Bit m of the register r (bits are number
7 through 0 from left to right).

MEANING

data

RP

rh

The following symbols and abbreviations are used in
the subsequent description of the 8080 instructions:

16-bit address quantity

The bit pattern for one of the register
pairs B,D,H,SP:
-

Auxiliary Carry: If the instruction caused a carry out
of bit 3 and into bit 4 of the resulting value,
the auxiliary carry is set; otherwise it is
reset. Th is flag is affected by single precision
additions: subtractions, increments, decrements, comparisons, and logical operations,
but is principally used with additions and
increments preceding a DAA (Decimal Adjust Accumulator) instruction.

addr

One of the register pairs:

H represents the H,L pair with H as the
high-order register and L as the low-order
register;

Carry: If the instruction resulted in a carry (from
addition or incrementation) or a borrow
(from subtraction, decrementation, or comparison) out of the high-order bit, this flag
is set; otherwise it is reset.

Register A

E
H
L

o represents the D,E pair with D as the
high-order register and E as the low-order
register;

Parity: If the modulo 2 sum of the bits of the result
of the operation is 0, (i.e., if the result has
even parity), this flag is set; otherwise it is
reset (i.e., if the result has odd parity).

Accumulator

0

B represents the B,C pair with B as the
high-order register and C as the low-order
register;

Sign: If the most significant bit of the result of the
result of the operation has the value 1, this
flag is set; otherwise it is reset.

SYMBOL

A
B
C

Z,S,P,CY,CA,

The condition flags:
Zero,
Sign,
Parity,
Carry,
and Auxiliary Carry, respectively.

viii

( )

The contents of the memory location or
registers enclosed in the parentheses.

..-

"Is transferred to"

A

logical product ("and")

-V-

Exclusive "or"

V

Inclusive "or"

+

Addition

-

Two's complement subtraction

n

The restart number 0 through 7

NNN

The binary representation 000 through
111 for restart number 0 and' 7 respectively.

MVI r, data
(r) (byte 2)
The content of byte 2 of the instruction is moved to
register r.

"Is exchanged with"
The one's complement

o I

I DI

I 1 I 0 I 0 I 0 I S I S I S
Cycles:
States:
Addressing:
Flags:

2
7
register immed.
none

MVI M, data
(Move to memory immediate)
((H) (Ll) (byte 2)
The content of byte 2 of the instruction is moved to
the memory location whose address is in registers H
and L.

MOV rl, r2
(Move)
(rl) (r2)
The content of register r2 is moved to register rl.

(r) -

0

Cycles:
States:
Addressing:
Flags:

This group of instructions transfers data to and from
registers and memory. Unless otherwise indicated, condition flags are not affected by any instructions in this group.

MOV r. M

I

data

Data Transfer Group:

o

0

data

1

Cycles:
States:
Addressing:
Flags:

5
register
none

'3
10
reg./ind. immed.
none

(Move from memory)
((H) (L))

LXI rp, data '6 (Load register pair immediate)
(byte 2)
(rh) --- (byte 3), (rI) Byte 3 of the instruction.is moved into the high·order
register (rh) of the register pair rp. Byte 2 of the instruction is moved into the low-order register (r1) of
the register pair rp.

The content of the memory location, whose address
is in registers Hand L, is moved to register r.
0111010101,1,10
Cycles:
States:
Addressing:
Flags:

2
7
reg. indirect
none

o

1

1

R

I

P 10 1 0

I 0 I 1-

high-order data
Cycles:
States:
Addressing:
Flags:

1','0IS'S'S

Cycles:
States:
Addressing:
Flags:

0

low-order data

MOV M,r
(Move to memory)
((H)(L))- (r)
The content of register r is moved to the memory
location whose address is in registers Hand L.
0'1

I

2
7
reg. indirect
none

3
10
immediate
none

LOA addr (Load Accumulator direct)
(A) ( (byte 3) (byte 2) )
The content of the memory location, whose address is
specified in byte 2 and byte 3 of the instruction, is
moved to register A.

SPHL(MoveHL to SP)
(SP) --- (H) (L)
The contents of registers Hand L ('6 bits) are moved
to register SP.

o

I 0 I 1 I 1 I 1 I 0 I 1 I 0
low-order addr
high-order addr
Cycles:
States:
Addressing:
Flags:

Cycles:
States: 5
Addressing: register
Flags: none

ix

4
13
direct
none

(registers D and E) may be specJfied.

STA addr (Store Accumulator direct)
(A)
( (byte 3) (byte 2) ) The content of the accumulator is moved to the memory location whose address is specified in byte 2 and
byte 3 of the .instruction.

o

I 0 I 1 I 1 t 0 I

o

I

o

1 I 0

low-order addr
high-order addr
Cycles:
States:
Addressing:
Flags:

4
13

direct
none

Cycles:
States:
Addressing:
Flags:

H.
I 0 I 1 I 0 I 1 I

o

I 1 I 0

high-order addr

16
direct
none

I 0 I 1 I 0 I 0 I

7

reg. indirect
none

Cycles:
States: 4
Addressing: register
Flags: none

o

Arithmetic Group:
This group of instructions performs arithmetic operations on data in registers and memory.
Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, and Carry flags according to the standard rules.

I 1 I 0

All subtraction operations are performed via two's
complement arithmetic and set the carry flag to one to
indicate a borrow and clear it to indicate no borrow.

low-order addr
high-order addr
Cycles:
States:
Addressing:
Flags:

2

5

SHLD addr (Store Hand L direct)
(L)
( (byte 3) (byte 2) ) ( (byte 3) (byte 2) +1) (H)
The content of register L is moved to the memory location whose address is specified in byte 2 and byte
3. The content of register H is moved to the succeeding memory location.

o

reg. indirect
none

XCHG
(Exchange Hand L with D and E)
(H)-(D)
IL) -(E)
The contents of registers Hand L are exchanged with
the contents of registers D and E.

low-order addr

Cycles:
States:
Addressing:
Flags:

7·

STAX rp
(Store accumutator indirect)
«rp))-(A)
The content of register A is moveo to the memory
location whose address is in the register pair rp. Note:
only register pairs rp=B (registers B and C) or rp=D
(registers D and E) may be specified.

LHLD addr (Load Hand L direct)
(L) ( (byte 3) (byte 2))
(H) ( (byte 3) (byte 2) + 1)
The content of the memory location. whose address
is specified in byte 2 and byte 3 of the instruction.
is moved to register L. The content of the memory
location at the succeeding address is moved to register

o

2

Cycles:
States:
Addressing:
Flags:

ADD r

5

(Add)

+ (r)
The content of register r is added to the content of
the accumulator. The result if placed in the accumulator.
(A) - - (A)

16
direct
none

1
LDAX rp (Load accumulator indirect)
(Al-«rp)
The content of the memory. location, whose address
is in the register pair rp, is moved to register A. Note:
only register pairs rp=B (registers B and C) or rp=D

I

0

I

0

I

0

I 0 I S I S I S

Cycles:
States: 4
Addressing: register
Flags: Z,S,P,CY,AC

x

ADD M

ACI data
(Add with carry immediate)
(A) - - (A) + (byte 2) + (CY)
The content of the second byte of the instruction and
the content of the CY flag are added to the contents
of the accumulator. The result is placed the accumulator.

(Add from memory)

(A) - - (A) + ( (H) (L) )

The content of the memory location whose address is
contained in the Hand L registers is added to the
content of the accumulator. The result is placed in
the accumulator.

,1, 1

0 1 0 1 0

Cycles:
States:
Addressing:
Flags:

0

0

data

2
7
reg. indirect
Z,S,P,CY,AC

Cycles:
States:
Addressing:
Flags:

ADI data
(Add immediate)
(A) - - (A) + (byte 2)
The content of the second byte of the instruction is
added to the content of the accumulator. The result
is placed in the accumulator.

Cycles:
States:
Addressing:
Flags:

ADC r

SUB r

2
7
immediate
Z,S,P,CY,AC

(Subtract)
(A) - - (A) - (r)

The content of register r is subtracted from the content of the accumulator. The result is placed in the
accumulator.

, 1 0 10 1 , 1 0

2
7
immediate
Z,S,P,CY,AC

I S

1 S

1 S

Cycles:
States: 4
Addressing: register
Flags: Z,S,P,CY,AC

(Add with carry)

(A) - - (A) + (r) + (CY)

SUB M

The content of register r and the content of the carry
bit are added to the content of the accumulator. The
result is placed in the accumulator.

(Subtract from memory)

(A) - - (A) - ( (H) (L) )

The content of the memory location whose address
is contained in the Hand L registers is subtracted from
the content of the accumulator. The result is placed
in the accumulator.

Cycles:
States: 4
Addressi ng: register
Flags: Z,S,P,CY,AC

ADC M

0

0

o
Cycles:
States:
Addressing:
Flags:

o

2

7
reg. indirect
Z,S,P,CY,AC

(Add from memory with carry)

(A) - - (A) + ( (H) (L) + (CY) )

The content of the memory location whose address is
contained in the Hand L registers and the content
of the CY flag are added to the accumulator. The
result is placed in the accumulator.

SUI data
(Subtract immediate)
(A) - - (A) - (byte 2)
The content of the second byte of the instruction is
subtracted from the content of the accumulator. The
result is placed in the accumulator.

10 10 I 0 I , I , I 1 I 0
Cycles:
States:
Addressing:
Flags:

, 1 , 1 0 1,1 0 1,1 1 1 0

2
7
reg. indirect
Z,S,P,CY,AC

data
Cycles:
States:
Addressing:
Flags:

xi

2
7
immediate
Z,S,P,CY,AC

SBB r

INC M

(Subtract with borrow)

(Increment memory)

+1

(A)- (A) - (r) - (CY)

( (H) (L) ) - - ( (H) (L) )

The content of register r and the content of the CY
flag are both subtracted from the accumulator The
result is placed in the accumulator.

The content of the memory location whose address is
contained in the Hand L registers is decremented by
one. Note: All condition flags except CYare affected.
010111110111010

Cycles:
States:
Addressing:
Flags:

Cycles:
States:
Addressing:
Flags:

1
4
register
Z,S,P,CY,AC
DCR r

SBa M

(Subtract from memory with borrow)
(A) __ (A) - ( (H) (L) ) - (CY)
The content of the memory location whose address
is contained in the Hand L registers and the content
of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator.
110 1 0 1 1111111
Cycles:
States:
Addressing:
Flags:

3
10
reg. indirect
Z,S,P,AC

(Decrement)

(r) - - (r)-1

The content of the memory location whose address is
contained in the Hand L registers is incremented by
one. Note: All condition flags except CY are affected.
010lDIDIDI1

1 0

Cycles:
States:
Addressing:
Flags:

2
7
reg. indirect
Z,S,P,CY,AC

DCR M

1 011

1
5
register
Z,S,P,AC

(Decrement memory)

( (H) (L) ) - - ( (H) (L) ) - 1

The content of the memory location whose address is
contained in the Hand L registers is decremented by
one. Note: All condition flags except CYare affected.

SBI data
(Subtract with borrow immediate)
(A) - - (A) - (byte 2) - (CY)
The contents of the second byte of the instruction and
the contents of the CY flag are both subtracted from
the accumulator. The result is placed in the accumulator.

1

1

o

1

0101111'0111011
Cycles:
States:
Addressing:
Flags:

o
data

Cycles:
States:
Addressing:
Flags:

3
10
reg. indirect
X,S,P,AC

INX rp
(Increment register pair)
(rh) (re) - - (RH) (R1) + 1
The content of the register pair rp is incremented by
one. Note: No condition flags are affected.

2
7
immediate
Z,S,P,CY,AC

Ol0lRIp
INC r

(Increment)
(r) - - (r) + 1
The content of register r is incremented by one. Note:
All condition flags except CY are affected.

o I

0

I

i

0101111

Cycles:
States: 5
Addressing: register
Flags: none

D 1 D 1 D 1 1 1 0 1 0

Cyctes:
States:
Addressing:
Flags:

DCX rp
(Decrement register pair)
(rh) (r1) - - (rh) (r1) -1
The content of the register pair rp is decremented by
one. Note: No condition flags are affected.

1
5
register
Z,S,P,AC

olOlRlpI1
Cycles:
States: 5
Addressing: register
Flags: none

xii

1 01111

DAD rp
(Add register pair to Hand L)
(H) (L) --- (H) (L) + (rh) (re)
The content of the register pair rp is added to the content of the register pair Hand L. The result is placed
in the register pair Hand L. Note: Only the CY is
affected. It is set if there is a carry out of the double
precision add; otherwise it is reset.

Cycles:
States:
Addressing:
Flags:

DAA

ANA M

(And from memory)

3
'0
register
CY

Cycles:
States:
Addressing:
Flags:

2
7
reg. indirect
Z,S,P,CY,AC

ANA data
(And immediate)
(A) --- (A) A (byte 2)
The content of the second byte of the instruction is
logically anded with the contents of the accumulator.
The result is placed in the accumulator. The CYand
AC flags are cleared.

data
Cycles:
States:
Addressing:
Flags:

Cycles:
States: 4
Addressing: Flags: Z,S,P,CY,AC

XRA r

2
7
immediate
Z,S,P,CY,AC

(Exclusive OR)

V

(A) --- (A)

(r)

The content of register r is exclusive-or'd with the
content of the accumulator. The result is placed in
the accumulator. The CY and AC flags are cleared.
1

0

Logical Group:

I

I

0

Cycles:
States:
Addressing:
Flags:

This group of instructions performs logical operations
on data in registers and memory and on condition flags.
Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, Auxiliary Carry, and
Carry flags according to the standard rules.

XRA M

(And)

I , I

S r S

I

S

,
4
register
Z,S,P,CY,AC

(Exclusive OR)

(A) --- (A)
(A) ___ (A)

(L) )

The contents of the memory location whose address
is contained in the Hand L registers is logically anded
with the content of the accumulator. The result is
placed in the accumulator. The CY and AC flags are
cleared.

(Decimal Adjust Accumulator)
The eight-bit number in the accumulator is adjusted
to form two four-bit binary-coded-decimal digits by
the following process:
,. If the value of the least significant 4-bits of the
accumulator is greater than 9 or if the AC flag is
set, 6 is added to the accumulator.
2. If the value of the most significant 4-bits of the
accumulator is now greater than 9, or if the CY
flag is set, 6 is added to the most significant 4-bits
of the accumulator.
All flags are affected by the additions, if performed,
otherwise they are reset.

ANA r

A ( (H)

(A) --- (A)

V ( (H)

(L) )

The content of the memory location whose address is
contained in the Hand L registers is exclusive-OR'd
with the content of the accumulator. The result is
placed in the accumulator. The CY and AC flags are
cleared.

A (r)

The content of register r is logically anded with the
content of the accumulator. The result is placed in the
accumulator. The CY and AC flags are cleared.

I

101,',IOISISIS
Cycles:
States: 4
Addressi ng: register
Flags: Z,S,P,CY,AC

0

I ., I

0

Cycles:
States:
Addressing:
Flags:

xiii

I, I , I , I
2
7
reg. indirect
Z,S,P ,CY ,AC

0

XRI data
(Exclusive or immediate)
(A) (A) V (byte 2)
The content of the second byte of the instruction is
exclusive-or'd with the content of the accumulator.
The result is placed in the accumulator. The CYand

CMP r

(COMPARE)

(A) - (r)

The content of register r is subtracted from the accumulator. The accumulator remains unchanged. The
condition flags are set as a result of the subtraction.

AC flags are cleared.

The Z flag is set to 1 if fA), = (r). The CY flag is set
to 1 if (r)t: (A).

,',','0',',',1 0

Note: 'The auxiliary carry is affected.

data

2
7
immediate
Z,S,P,CY,AC

Cycles:
States:
Addressing:
Flags:
ORA r

Cycles:
States:
Addressing:
Flags:

(OR)

(A) -

CMP M

(A) V (r)

I

0

I , I

1 f 0

Cycles:
States:
Addressing:
Flags:
ORA M

The content of the memory location whose address is
contained in the Hand L registers is subtracted from
, the accumulator. The accumulator remains unchanged.
The condition flags are set as a result of the subtraction. The Z flag is set to 1 if (A) = ( (H) (L) ).

I sis I sl

( (H) (L) )

,
4
register
Z,S,P,CY,AC

Cycles:
States:
Addressing:
Flags:

0

2
7
reg. indirect
Z,S,P,CY,AC

Cycles:
States:
Addressing:
Flags:
RLC

AC flags are cleared.

'1

Cycles:
States:
Addressing:
Flags:

, 0 , ,

I , ,

o

2
7
reg. indirect
Z,S,P,CY,AC

,',',',',1,','0

ORI data
(OR Immediate)
(A) (A) V (byte 2)
The content of the second byte of the instruction is
inclusive-OR'd with the content of the accumulator.
The result .is placed in the accumulator. The CY and

" , , I ,

I ,

CPI data
(Compare immediate)
(A) - (byte 2)
The content of the second byte of the instruction is
subtracted from the accumulator. The accumulator is
not changed. The condition flags are set by the result
of the subtraction. The Z flag is set to , if (A) = byte
2). The CY flag is set to , if byte 2) t= (A).
Note: The AC flag is affected.

cleared.

I , I , I· 0 I, , , ,

,

Cycles:
States:
Addressing:
Flags:

(A) V ((HI (L) )

, 0

A.

, 0 , l'

The content of the memory location whose address is
contained in the Hand L registers is inclusive-OR'd
with the content of the accumulator. The result is
placed in the accumulator. The 'CY and AC flags are

,

t=

Note: The AC flag is affected.

(OR from memory)

(A) -

(Compare with memory)

(A) - ((H).(L))

The content of register r is inciusive-OR'd with the
content of the accumulator. The result is placed in
the accumulator. The CY and AC flags are cleared.

1

1
4
register
Z,S,P,CY,AC

0

2
7
immediate
Z,S,P,CY,AC

2
7
immediate
Z,S,P,CY,AC

(Rotate left)
(A n+,) (An); (AO)- (A7); (CY) (A7)
The content of the. accumulator is rotated right one
position. The high order bit and the CY flag are both
set to the value shifted out of the low order bit position. Only the CY flag is affected.

Cycles: 1
"States: ,
Flags: CY

xiv

RRC

(Rotate right)
(An) - - A n -l); (A7)-(AO); (CY)-(Ao)
The content of the accumulator is rotated right one
position. The high order bit and the CY flag are both
set to the value shifted out of the low order bit position. Only the CY flag is affected.

STC

(Set carry)
(CY)--l
The CY flag is complemented. No other flaps are
affected.

a

1

a

1 1

Cycles:
States: 4
Flags: CY

Cycles:
States: 4
Flags: CY
RAL

a

(Rotate left through carry)
(A n+l)-(A n ); (CY)-(A7); (Ao) -(CY)
The content or the accumulator is rotated left one
position through the carry. The low order bit is set
equal to the CY flag and the CY flag is set to the
value shifted out of the high order bit. Only the CY
flag is affected.
Branch Group:
This group of instructions alter normal sequential
program flow.

Cycles:
States: 4
Flags: CY
RAR

Unless specified otherwise, no condition flags are affected by any instruction in this group.

(Rotate rigt.lt through carry)
(AO); (A 7 ) - (CY)
(A n )-(A n +l); (CY) -

The two types of branch instructions are unconditional and conditional. Unconditional transfers simply perform the specified operation on register PC (the program
counter). Conditional transfers examine the status of one
of the four processor flags to determine if the specified
branch is to be executed. The conditions that may be
specified are as follows:

The content of the accumulator is rotated right one
position through the CY flag. The high order bit is
the CY flag. The high-order bit is set equal to the CY
flag and the CY flag is set to the value shifted out of
the low order bit. Only the CY flag is affected.

a

10 1

a

11

'

1 '1

'1

1 1

CONDITION
C
Z
M
PE
NC
NZ
P
PO

Cycles:
States: 4
Flags: CY
CMA

(Complement accumulator)

(A)-(A)
The contents of the accumulator are complemented
(zero bits become 1, one bits become (0). No flags
are affected.

a

10 11

,

a

11

11

,

1 11

CCC

carry (CY=l)
zero (Z=l)
minus (5=1)
parity even (P=l)
no carry (CY=O)
not zero (Z=O)
plus (5=0)
parity odd (P=O)

(Complement carry)
(CY) - - (CY)
The CY flag is complemented. No other flags are
affected.

1

1

1

-T 0 1

a I a I a

low-order addr
high-order addr

a , a

1

1

000
001
010
all
100
101
110
111

JMP addr
(Jump)
(PC) (byte 3) (byte 2)
Control is transferred to the instruction whose address is specified in byte 3 and byte 2 of the current instruction.

Cycles: 1
States: 4
Flags: none
CMC

-

1 ,
Cycles:
States:
Addressi ng:
Flags:

Cycles:
States: 4
Flags: CY

xv

3
10
direct
none

I 1 I 1

RET

Jcondition addr
(Conditional jump)
If (CCC),
(PC) __ (byte 3) (byte 2)
If the specified condition is true, control is transferred to the instruction whose address is specified
in byte 3 and byte 2 of the current instruction; otherwise, control continues sequentially.
1 I 1 I

ci

C I C I

o

I 1 I 0

low-order addr
high-order addr
Cycles:
States:
Addressing:
Flags:

3
10
direct
none

Cycles:
States:
Addressing:
Flags:

CAll addr
(Call)
( (SP) - 1) - - (PCH)
( (SP) - 2) - - (PCl)
(SP) - - (SP) -2
(PC)-- (byte 3) (byte 2)
The high-order eight bits of the next instruction address is one less than the content of register SP. The
low-order eight bits of the next instruction address
are moved to the memory location whose address is
two less than the content of register SP. The content
of register SP is decremented by 2. Control is transferred to the instruction whose address is specified in
byte 3 and byte 2 of the current instruction.
1 I 1 I 0 I 0

(Return)
(PCl) - - ( (SP) )
(PCH) - - ( (SP) + 1)
(SP) - - (SP) + 2
The content of the memory location whose address is
specified in register SP is moved to the low-order eight
bits of register PC. The content of the memory location whose address is one more than the content of
register PS is moved to the high-order eight bits of
register PC. The content of register PC is incremented
by 2.

1 1 r 1

I 0

3
11
reg. indirect
none

Rcondition
(Conditioned return)
If (CC),
(PCl) - - ( (SP) )
(PCH) - - ( (SP) + 1)
(Sf') - - (SP) + 2
If the specified condition is true, the actions specified in the RET instruction (see above are performed; otherwise; control continues sequentially.
11

CICICIOIOIO
Cycles:
States:
Addressing:
Flags:

I 1

low-order addr

1/3
5/11
reg. indirect
none

high-order addr
Cycles:
States:
Addressing:
Flags:

RST n
(Restart)
( (SP) - 1) - - (PCH)
( (SP) - 2) - - (PCl)
(SP) - - (SP) - 2
(PC) - - 8* (NNN)
The high-order eight bits of the next instruction address are moved to the memory location whose address is one less than the content of register SP. The
low-order eight bits of the next instruction address are
moved to the memory location whose address is two
less than the content of register SP. The content of
register SP is decremented by two. Control is transferred to the instruction whose address is eight times
the content of (NNN).

5
17
direct
none

Ccondition addr
(Conditional call)
If ICC),
( (SP) - 1) - - (PCH)
( (SP) - 2) - - (PCl)
(SP) - - (SP) - 2
(PC) - - (byte 3) (byte 2)
If the specified condition is true, the actions spec·
ified in the CAll instruction (see above) are performed; otherwise, control continues sequentially.
1

I

11C I C

I

Cll

1

1 01 0

low-order addr

1

Cycles:
States:
Addressing:
Flags:

high-order addr
Cycles:
States:
Addressing:
Flags:

I

3/5
11/17
direct
none

xvi

3
11
direct
none

PCHl

(Jump Hand l indirect - move Hand l to PC)
(PCH)- (H)
(PCl) (L)
The content of register H is moved to the high-order
eight bits of register PC. The content of register l is
moved to the low-order eight bits of register PC.

POP rp

(Pop)
((SP))
(rh) ({SP) + 1)
(SP) (SP) + 2
The content of the memory location, whose address
specified by the content of register SP, is moved to
the content of register SP, is moved to the low-order
register of register pair rp. The content of the memory
location, whose address is one more than the content
of register SP, is moved to the high-order register of
register pair rp. The content of register PS is incre·
mented by 2.
Note: Register pair rp = SP may not be specified.
(r1) -

1111110 1 1 1 0 1 0 1 1
Cycles:
States:
Addressing:
Flags:

1

5
register
none

1111Rlp i 0101011

Stack, I/O, and Machine Control Group:

Cycles: 3
States: 10
Addressing: reg. indirect
Flags: none

This group of instructions performs I/O, manipulates
the "stack", and alters internal control flags.
Unless otherwise specified, no condition flags are affected by any instructions in this group.
PUSH rp
(Push)
((SP) - 1 ) - (rh)
((SP) - 2) (r1)
(SP) (SP) - 2
The content of the high-order register of register pair
rp is moved to the memory location whose address is
one less than the content of register SP. The content
of register pair rp is moved to the memory location
whose address is two less than the content of register
SP. The content of register SP is decremented by 2.
Note: Register pair rp = SP may not be specified.

POP PSW
(Pop processor status word)
(CY) ( (SP) )0
{PI { (SP) )2
(AC) ( (SP) )4
(Z) ((SP))6
(S) ( (SP) )7
(A) ( (SP) + 1)
(SP) ( (SP + 2)
The content of the memory location whose address is
specified by the content of register SP is used to restore the condition flags. The content of the memory location whose address is one more than the
content of register SP is moved to register A. The
content of register SP is incremented by 2.

111Rlp 1 ol11011
Cycles:
States:
Addressing:
Flags:

3
11

1

reg. indirect
none

1

I
Cycles: 3
States: 10
Addressing: reg. indirect
Flags: Z,S,P,CY,AC

PUSH PSW
(Push processor status word)
( (SP) - 1) (A)
( (SP) - 2) 0 (CY), ((SP) - 2) 1 1
( (SP) - 2) 2 (P), ( (SP) - 2) 3 0
((SP) -2) 4 (AC), ((SP) -2) 5 - 0
( (SP) -2) 6 (Z), ((SP) -2) 7 - - (S)
(SP) (SP) - 2
The content of register A is moved to the memory location whose address is one less than register SP. The
contents of the condition flags are assembled into a
processor status word and the word is moved to the
memory location whose address is two less than the
content of register SP. The content of register PS is
decremented by two.
1

I

XTHl
(Exchange stack top with Hand l)
(l)-{{SP))
(H) ({SP) + 1)
The content of the l register is exchanged with the
content of the memory location whose address is
specified by the content of register SP. The content
of the H register is exchanged with the content of the
memory location whose address is one more than the
content of register SP.

1

Cycles:
States:
Addressing:
Flags:

Cycles:
States:
Addressing:
Flags:

3
11
reg. indirect
none

xvii

5
18
reg. indirect
none

IN port
( Input)
(A) - - (data)
The data placed on the eight-bit bi-directional data bus
by the specified port is moved to register A.

01

(Disable interrupt)
The interrupt system is disabled immediately following the execution of the instruction.

1

,1,lal,I,lol,l,

I, !

Cycles: 3
States:
Addressing: direct
Flags: none

,a

HLT

(Halt)
The processor is stopped. The registers and flags are
unaffected.

OUT port
(Output)
(data) - - (A)
The content of register A is placed on the eight-bit
bi-directional data bus for transmission to the specified port.

a

I , 1

a

.1

a

Cycles: ,
States: 4
Flags: none

I , I ,

NOP

port
Cycles: 3
States:
Addressi ng: direct
Flags: none

(No op)
No operation is performed. The registers and flags are
unaffected.

a

,a

EI

1

Cycles: ,
States: 4
Flags: none

port

, I , t

I , I a I a I , I

1

I

a

1

a

I

a

1

a , a

Cycles:
States: 4
Flags: none

(Enable interrupt)
The interrupt system is enabled following the execution of the next instruction.

, ' , I, I, 11 1 a I, I ,
Cycles:
States: 4
Flags: none

xviii

1

a

1

a

xix

inter

Silicon Gate MOS 8080

SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
• 2 ILs Instruction Cycle

• Sixteen Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment

• Powerful Problem Solving
Instruction Set

• Decimal,Binary and Double
Precision Arithmetic

• Six General Purpose Registers
and an Accumulator

• Ability to Provide Priority Vectored
Interrupts

• Sixteen Bit Program Counter for
Directly Addressing up to 64K Bytes
of Memory

• 512 Directly Addressed 1/0 Ports

The Intel 8080 is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's nchannel silicon gate MOS process. This offers the user a high performance solution to control and processing applications.
The 8080 contains six 8-bit general purpose working registers and an accumulator. The six general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The 8080 has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store!
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the 8080 the ability to easily handle multiple level
priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.
This microcoprocessor has been designed to simplify systems design. Separate 16-line address and 8-line bidirecti.onal data
busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the 8080. Ultimate control of the address and data busses resides with the HOLD signal. It provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
0 7 -Do

8080 CPU FUNCTIONAL
BLOCK DIAGRAM

BI-DiRECTIONAL
DATA BUS

(BBIT)
INTERNAL DATA BUS

INSTRUCTION
DECODER
AND
MACHINE
CYCLE
ENCODING

181

181

0

181

181

REG.
H
REG.

181

E
REG.
L
REG.

STACK POINTER
PROGRAM COUNTER

181
1161
1161

1161

TIMING
AND
CONTROL
POWER1- +12V
SUPPLIES _
+5V
_-5V

-GNO
ACK

©Intel Corp. 1974

xx

REGISTER
ARRAY

SILICON GATE MOS 8080
8080 FUNCTIONAL PIN DEFINITION
The following describes the function of all of the 8080 I/O pins.
Several of the descriptions refer to internal timing periods. [1]

D.
D.
De
07
03
D.
0,0

07-00 (input/output three-state)
DATA BUS; the data bus provides bidirectional communication
between the CPU, memory, and I/O devices for instructions and
data transfers. Do is the least significant bit.

Do
-5V
RESET
HOLD
INT

SYNC (output)
SYNCHRONIZING SIGNAL; the SYNC pin provides a signal to
indicate the beginning of each machine cycle.

DBIN
WR
SYNC
+5V

DBIN (output)
DATA BUS IN; the DBIN signal indicates to external circuits that
the data bus is in the input mode. This signal should be used to
enable the gating of data onto the 8080 data bus from memory
or I/O.
READY (input)
READY; the READY signal indicates to the 8080 that valid memory or input data is available on the 8080 data bus. This signal is
used to synchronize the CPU with slower memory or I/O devices.
lfafter sending an address out the 8080 does not receive a READY
input, the 8080 will enter a WAIT state for as long as the READY
line is low.

A"
Au
Au
An

40

A,O
GND

A15.AO (output three-state)
ADDRESS BUS; the address bus provides the address to memory
(up to 64K 8-bit words) or denotes the I/O device number for up
to 256 input and 256 output devices. Ao is the least significant
address bit.

4

INTEL
10

8080

39
38
37
36
36
34
33
32
31

11

30

12
13
14
15
18
17
18
19
20

29
28
27
26
25
24
23
22
21

o

A,.
Ae
Ae

WAIT
READY
~,

HLDA

In either case, the H LOA signal appears after the rising edge of 1/11
and high impedance occurs after the rising edge of 1/12,

WAIT (output)
WAIT; the WAIT.signal acknowledges that the CPU is in a WAIT
state.

INTE (output)
INTER RUPT ENABLE; indicates the content of the internal interrupt enable flip/flop. This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and inhibits interrupts
from being accepted by the CPU when it is reset. It is automatically reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M 1) when an interrupt is accepted and is
also reset by the RESET signal.

WR (output)
WRITE; the WR signal is used for memory WRITE or I/O output
control. The data on the data bus is stable while the WR signal is
active (WR = 0).
HO LD (input)
HOLD; the HOLD signal requests the CPU to enter the HOLD
state. The HOLD state allows an external device to gain control
of the 8080 address and data bus as soon as the 8080 has completed its use of these buses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READ Y signal is active.
As a result of entering the HOLD state the CPU ADDRESS BUS
(A 1s-Ao) and DATA BUS (DrDo) will be in their high impedance
state. The CPU acknowledges its state with the HOLD ACKNOWLEDGE (HLDA) pin.

INT (input)
INTERRUPT REQUEST; the CPU recognizes an interrupt request on this line at the end of the current instruction or while
halted. If the CPU is in the HOLD state or if the Interrupt Enable
flip/flop is reset it will not honor the request.
RESET (input) [2]
RESET; while the RESET signal is activated, the content of the
program counter is cleared and the instruction register is set to O.
After RESET, the program will start at location a in memory.
The INTE and H LOA flip/flops are also reset. Note that the
flags, accumulator, and registers are not cleared.

HLDA (output)
HOLD ACKNOWLEDGE; the HLDA signal appears in response
to the HOLD signal and indicates that the data and address bus
will go to the high impedance state. The H LOA signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WR ITE memory or OUT·
PUT operation.

Ground Reference.
+12 ± 5% Volts.
+5 ± 5% Volts.
-5 ±5% Volts (substrate bias).
2 externally supplied clock phases. (non TTL compatible)

xxi

SILICON GATE MOS 8080
ABSOLUTE MAXIMUM RATINGS·

*COMMENT:
Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect device reliability.

Temperature Under Bias . . . . . . . . . . . . . . . O°C to +70° C
Storage Temperature " . . . . . . . . . . . . . -65°C to +150°C
All Input or Output Voltages
With Respect to VBB . . . . . . . . . . . . . . -0.3V to +20V
Vcc. Voo and Vss With Respect to VBB
-0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

D.C. CHARACTERISTICS

= O°C, to

TA

70°C, VOO

= +12V ± 5%, Vcc = +5V ± 5%, VBB = -5V ± 5%, Vss = OV, Unless Otherwise Noted.
Typ.

Min.

Parameter

Symbol

Max.

Unit

VILC

Clock Input Low V.ltage

VSS-1

VSS+0.6

V

VIHC

Clock Input High Voltage

Voo-1

Voo+1

V

V IL

Input Low Voltage

Vss-1

Vss+0.8

V

VIH

Input High Voltage

3.3

Vcc+ 1

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

IDD(AV)

Avg. Power Supply Current (Voo)

40

67

mA

ICC (AV)

Avg. Power Supply Current (Vcc)

60

75

mA

IBB(AV)

Avg. Power Supply Current (VBB)

.01

IlL

Input Leakage

ICL

Clock Leakage

IOL[3J

Data Bus Leakage in Input Mode

IFL

Address and Data Bus Leakage
During HOLD

+10
-100

pA

},OL
IOL
IOH

V

3.7

= 25°C

Symbol

VCC

mA

Vss ,;;;; V IN ,;;;; Vcc

±10

pA

Vss ,;;;; VCLOCK ,;;;; VOD

-100

pA

Vss ,;;;; VIN ,;;;; VCC

Max.

Unit

10

20

pf

fc = 1 MHz

CIN

Input Capacitance

5

10

pf

Unmeasured Pins

20

= VCC
= Vss

1.5,----,-----..,----.....,

Typ.

10

VAOOR/DATA
VADDR/OATA

TYPICAL SUPf>L Y CURRENT VS. [ J
TEMPERATURE, NORMALIZED. 4

Clock Capacitance

Output Capacitance

TA 25°C
TCY = .48 psec

IlA

Cq,

COUT

rp,,,,;O"
=

1

= VOD = Vss = OV, Vss = -5V ±5%

Parameter

= 1.7mA on the Data Bus
= .75mA on all other outputs
= 100pA.

±10

CAPACITANCE
TA

Test Condition

pf

Test Condition

Returned to Vss

NOTES:
1. For definitions the user is directed to the fotlowing publications:
A. Programming Manual for the 8080 Microcomputer System.
B. 8080 Microcomputer Users Manual.
C. From CPU to Software.
2. The RESET signal must be active for a minimum of 3 clock cycles.
3. When OBIN is high and VIN> VtH an active pull up of nominally 2k!l
will be switched onto the Oata Bus.
4. AI supply / AT A =-0.45%f c.

xxii

?:
~

z

w

a:
a:
:::>
u

>

~ O.51-----+----+---~

iil

O.OO!-----:-+f.
2S,...----+5Q::!::----.....,J+7·S
AMBIENT TEMPERATURE ('CI

SILICON GATE MOS 8080
A.C. CHARACTERISTICS
TA = O°C to 70°C, VOO = +12V

± 5%, VCC

Symbol

= +5V ± 5%,

Vee

= -5V ± 5%, Vss = OV, Unless Otherwise Noted

Parameter

Min.

Max.

Unit

0.48

2.0

JJ.sec

5

50

nsec

Test Condition

tCy[3]

Clock Period

t r , tf

Clock Rise and Fall Time

tq,1

4>1 Pulse Width

60

nsec

tq,2

4>2 Pulse Width

220

nsec

t01

Delay 4>1 to 4>2

0

nsec

t02

Delay 4>2 to 4>1

70

nsec

t03

Delay 4>1 to 4>2 Leading Edges

130

nsec

tOA [2]

Address Output Delay From 4>2

200

nsec

RL = 4.5kn, CL = 100pf

too [2]

Data Output Delay From 4>2

220

nsec

RL = 2.1kn, CL = 100pf

toc [2]

Signal Output Delay From 4>1, or 4>2 (SYNC, WR WAIT HLOA)

120

nsec

RL =4.5kn, CL = 50pf

tOF [2]

DBIN Delay From 4>2

140

nsec

RL = 2.1 kn, CL = 50pf

tOI[1]

Delay for Input Bus to Enter Input Mode During DBIN

tOF

nsec

tOS1

Data "Setup Time" During 4>1 and DBIN

25

TIMING WAVEFORMS [12]

-

(Note: Timing measurements are made at the fol.lowing reference voltages: CLOCK "1" = 9.5V,
"0" = 1.0V; INPUTS "1" = 3.3V, "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.)

'0,-

W-~v'"

r

f\

~,

~

1-'0,-;

"-'0,

r-\

-

I-'o.-.j

tOII-

1--'0·4

SYNC

DBIN

•

'oc

.x: _____-

~

..

-'0.--;

tOHI*-'

-- --- to:1= ~

-

~

'0,,-

I

i-'o~

WAIT

------------

--- ,..--- --',. -'.
~,

I- f----j 'w.

- --

__1

--- - --- -- - -~'w.
-'ow
DATA OUT

-',.

1'H --or i~c

~® 1:1.

- ,.:r=

'H-

-

locI--

£-f-L- :::i

~--

t RS

-

toe

I
I-

HOLD

-I

®

---I 'HS .;::-

:I
~

-

I-'H

~

toe!-- '

7:

HLDA

-

1." ,I

'''~II.
---:+

INTE

xxiii

~tH

-

.Iii. I

_
'H
"~~il,

I--tlE

'.

- -

-

~

i-'w.j

loc-

INT

~

~

'ocl-

----------READY

r\

-- -- --- --- - --'

'~:":tTAIN

-\-

,----,

~

-~

F\

F\

/\
.,....----,

-- I: ---

f---

nsec

50

-

-

,~

SILICON GATE MOS 8080
A.C. CHARACTERISTICS
TA

= O°C to 70°C. VOO

,Continued)

= +12V ± 5%. VCC

Symbol

= +5V ± 5%. VBB = -5V ± 5%. Vss = OV. Unless Otherwise Noted
Min.

Parameter

tP2

t052

Data "Setup Time" to

tOH 11]

Data "Hold Time" From

tIE [2]

INTE Output Delay From

During DBIN

150

tH

tP2 During DBIN
tP2
Ready "Setup Time" During tP2
Hold "SetupTime" to tP2
INT "Setup Time" During tP2 (During till in Halt Mode)
"Hold Time" From tP2 (Aead,(, INT, Holdl

tFO

Delay to Float During Hold (Address and OATA BUS)

tWA [2]

Address Stable From WR

tA5
tHS
tIS

tAW [2]

Address Stable Prior to WR

two [2]

Output Data Stable From WR

tow l2 ]

Output Data Stable Prior to WR

Max.

nsec

tOF
200

nsec

140

nsec

180

nsec

0

nsec

[5]

nsec

t03

nsec

16]

nsec

3. tCY = t03 + toP2 + t02 + tloP2 + troPl + tloPl .. 480n •.

TYPICAL A OUTPUT DELAY VS. A CAPACITANCE

V

w

...0

0

...:>

-10

a.
0

<1

-20

V

-100

./
-so

/

'-....SPEC

o
~

+100

+50

CAPACITANCE (pi'

(CACTUAL - C.PEcl

4. The lollowing are relevant when interfacing the B080 to devices having VIH = 3.3V:
al Maximum output rise tim.- Irom .BV to 3.3V = 140ns @ CL - SPEC.
bl· Output delay when measured to 3.0V z SPEC + 60ns @ CL = SPEC.
cl .If CL ¢ SPEC add .6ns/pl il CL > CSPEC, subtract .3ns/pl (Irom modified delay I il CL < CSPEC.
5. tAW = 2 tCY -t03 -trl/>2 -120nsec.
6. tOW· ICY -t03 -trl/>2 -l50niec.
7. Data ir\ must be stable for this period during OBIN "T3' Both tOSl and IOS2 must be satisfied.
8. Ready signal must be stable lor this period during T2 or TW' IMust be externally synchronized.I
9. Hold signal must be stable lor this period during T2 or TW when entering hold mode. and.during T3. T 4. TS
and TWH when in hold mode. (Must be externally synchronized.I
10. Interrupt signal must be stable during this period of the last clock cycle 01 any instruction to be recognized
on the following instruction. (External synchronization is not required.)

11. During halt mode only. timing is with respect 10 1/>1 falling edge.
12. This timing diagram shows timing relationships only. it dOls not represent any specific machine cycle.

xxiv

nsec

t03

8080

:>

AL =4.5kn, CL = 50pf

nsec
120

OUTPUT

> +10
<
....

nsec

120

+5V

!

Test Condition

nsec

NOTES: 1. Data input should be enablad with OBIN status. No bus conflict can then occur and data hold time is assured.
2. Loed circuit

+20

Unit

=4.5kn, CL = 100pf
AL =4.5kn, CL = 100pf
AL = 2.lkn, CL = 100pf
AL = 2.lkn, CL = l00pf
AL

SILICON GATE MOS 8080
INSTRUCTION SET
The accumulator group instructions include ARITHMETIC and
LOGICAL OPERATORS with DIRECT, INDIRECT, AND IMMEDIATE addressing modes.

and DECREMENT memory, the six general registers and the accumulator is provided as well as EXTENDED INCREMENT and
DECREMENT instructions to operate on the register pairs and
stack pointer. Further capability is provided by the ability to ROTATE the accumulator LEFT or RIGHT through or around the
carry bit.

MOVE, LOAD, and STORE instruction groups provide the ability
to move either 8 or 16 bits of data between memory, the six
working registers and the accumulator using 01 RECT, INDI RECT,
and IMMEDIATE addressing modes.

Input and output may be accomplished using memory addresses
as I/O ports or the directly addressed I/O provided for in the
8080 instruction set.

The ability to branch to different portions of the program is provided with JUMP, JUMP CONDITIONAL, and COMPUTED
JUMPS. Also the ability to CALL to and RETURN from subroutines is provided both conditionally and unconditionally. The
RESTART (or single byte call instruction) is useful for interrupt
vector operation.

The following special instruction group completes the 8080 instruction set: the NO-OP instruction, HALT to stop processor
execution and the DAA instructions provide decimal arithmetic
capability. STC allows the carry flag to be directly set, and the
CMC instruction allows it to be complemented. CMA complements the contents of the accumulator and XCHG exchanges the
contents of two 16-bit register pairs directly.

Double precision operators such as STACK manipulation and
DOUBLE ADD instructions extend both the arithmetic and interrupt handling capability of the 8080. The ability to INCREMENT

Data and Instruction Formats
Data in the 8080 is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be in the
same format.

07 Os 05 04 03 02 01 Do
DATA WORD
The program instructions may be one, two, or thfee bytes in length. Multiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions

TYPICAL INSTRUCTIONS

Two Byte Instructions

Register to register, memory reference, arithmetic or logi.cal, rotate
return, PUSH, POP, ENABLE or
DISABLE
INTERRUPT INSTRUCTIONS

I 07 Os 05
I 0 7 Os 05

I OP CODE
0 1 Do I OPERAND

04 03 O2 0 1 Do
04 03 D2

Immediate mode or I/O instructions

Three Byte Instructions

I OP CODE
Do I LOW ADDRESSOR OPERAND 1
Do I HIGH ADDRESSOR OPERAND 2

107 Os 05 04 03 O2 0 1 Do
107 Os 05 04 03 02 01
107 Os 0 5 04 03 02 01

JUMP, CALL or DIRECT LOAD
AND STORE INSTRUCTIONS

For the 8080 a logic "1" is defined as a high level and a logic "0" is defined as a low level.

xxv

SILICON GATE MOS 8080
INSTRUCTION SET
Summary of Processor Instructions

Mnemonic

MOV,',r2
MOVM,r
MOVr,M
HlT
MVlr
MVIM
INR r
OCRr
INR M
OCR M
ADDr
ADC r
SUB r
SBB r
ANAr
XRA r
ORA r
CMPr
ADD M
AOC M
SUB M
SBB M
ANAM
XRA M
ORA M
CMP M
ADI
ACI
SUI
SBI
ANI
XRI
ORI
CPI
RlC
RRC
RAl
RAR
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
CAll
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET
RC
RNt

NOTES:

Instruction Codel 1]
04 03 ~ 0,

Description

~

lis lis

Move register to register

0
0
0
0
0
0
0
0
0
0
1
1
1
1

1
1
1
0
0
0
0
0
0
0
0
0
0

Move register to memory

Move memory to register
Halt

Move immediate regis.ter
Move immediate memory
Increment register

Decrement register
Increment memory
Decrement memory
Add register to A
Add register to A with carry
Subtract register from A
Subtract register Irom A
with borrow
And register with A
Exclusive Or register with A
Or register with A
Compare register with A
Add memory to A
Add memory to A with carry
Subtract memory Irom A
Subtract memory Irom A
with borrow
And memory with A
Exclusive Or memory with A
Or memory with A
Compare memory wfth A
Add immediate to A
Add immediate to A with
carry
Subtract immediate from A
Subtract immediate from A
with borrow
And immediate with A
Exclusive Or immediate with
A
Or immediate with A
Compare immediate with A
Rotate A left
Rotate A right
Rotate A left through carry
Rotate A right through
carry
Jump uncon~itional
Jump on carry
Jump on no carry
Jump on zero
Jump on no zero
Jump on positive
Jump on minus
Jump on parity even
Jump on parity odd
Call unconditional
CaU on carry
Call on no carry
Call on zero
Call on no zero
Call on positive
CaU on- minus
Call on parity ewn
Call on- parity odd
Return
Return on carry
Return on no carry

D
1
0
1
D
1
0
D

1
1
1
0
0
0
0

D
1
D
1
D
1
D
D
1
1
0
0
1
1

D S
0 S
0 1
0 1
D 1
0 1
D 1
D 1
0 1
0 1
0 S
S
S
S

0
0
1
1
0
0
1
1

S
S
S
S
1

S
S
1
1
1
1
0
0
0
0
S
S
S
S

Do
S
S
0
0
0
0
0
1
0
1
S
S
S
S

Clockl2r
Cycles

5
7
7
7
7
10

5
5
10
10
4
4
4
4

()

0
0
1
1
0
0
0
0

1
1
0
0
0
0

1
1
0
0
0
0
0
0
0
0
0

1
1
0
0
0
0
0
1
1
1
1
(}

0
0

1
0

0

1

a
0

1
1
0
1
1
0
1
0
0
1
1
0
1
1
0

4
4
4
4
0
0
0
0
0
0
0
0
0

1
0
0
0
0
0
0
0
0
0
0
0
0

1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0

Description

RZ
RNZ
RP
RM
RPE
RPO
RST
IN
OUT
lXI B

Return

00

10
10
10
10
10
10
10
10
10
17
11117
11117
11117
11/17
11/17
11117
11117
11/17
11}

5/11
5tH

Instruction Cod,ll]
04 03 ~ 0,

lis lis

zero

0
0
1
1
1
1
A
0
0
0

Return on positive
Return on minus

1. DDS or SSS - 000 B - 001 C - 010 D - 011 E - 100 H - 101 L - 110 Memory - 111 A.
2. Two possible cycle times, (5/11} indicate instruction cycles dependent on condition flags.

xxvi

~

Return on no lero

Return on parity even
Return on parity odd
ReSIa"
Input
Output
'.oad immediate register
Pair B & C
lXIO
load immediate register
Pair 0 & E
lXIH
Load tmmediate register
Pair H & l
Load immediate stack pointer
lXI SP
PUSH B
Push register Pair B & C on
stack
PUSH 0
Push register Pair 0 & E on
stack
PUSH H
Push register Pair H & l on
stack
PUSH PSW Push A and Flags
on stack
POP B
Pop register pair B & C off
stack
POP 0
Po~ register pair 0 & E off
stack
POP H
Pop register pair H & l off
stack
POPPSW
Pop A and Flags
off stack
Store A direct
STA
lOA
load A direct


---+--+:--+---+---....j.-~

50 1----+'

AMBIENT TEMPERATURE

........
J,.--

\
SPEC.
50 r---POINTS

'i"'_ jaja-.

-.

<'

40

_u

·--1

40

~

w

t:l

II

=25°C

30




.. 40

..

...:::>
:::>

.M

"
'-

.2

.4

TA = 75OC ......
20

o

-.I

~

~ tr
TA = OOC

/,
o

-10

-t lsoJI

VIA...

,

-20

:::>

~

.

-30

o

-40

I

-50

If
A

...:::>
:::>

I- TA = ooc
= 2S"C

.6

.8

OUTPUT "LOW" VOL TAGE (V)

1.0

~Jl

DATA TRANSFER FUNCTION
S.O

TA = 7SOC

o

1.0

1 .1

vee

f;. = ~So C

TA=O"C

w

'-'
«

3.0

....

0

>

:::>

TA = 25°C2.0
TA = 75OC_

:::>

1\ ~
H--.\\
H

\

1.0

\.. \. ~

0
2.0

3.0

4.0

xxxii

5.0

\

\
l\
\ \

0

OUTPUT "HIGH" VOLTAGE (V)

-

4.0

.
.....
.

I
If

-

= 5.0V

~

I

a:
a:

~

I- TA

~

TA=O"C-

<
!
!Zw

~'f'

(.)

o

~

o

~

TA = 750C _
TA = 25"C_

OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE

o

.2

.4

.6

.8

1.0

1.2 1.4 1.6

INPUT VOLTAGE (V)

1.8 2.0

SCHOnKY BIPOLAR 8205
8205 SWITCHING CHARACTERISTICS

CONDITIONS OF TEST:

TEST LOAD:
390fl

Input pulse amplitudes: 2.5V
Input rise and fall times: 5 nsee
between 1V and 2V
Measurements are made at 1.5V
2K

All Transistors 2N2369 or Equivalent. e L = 30 pF

TEST WAVEFORMS
ADDRESS OR ENABLE
INPUT PULSE

---1_- "'I~______________:'t-'~-~--I'------,
"

,

\

\

OUTPUT

A.C. CHARACTERISTICS TA = OOC to +75°C, Vee = 5.0V ±5% unless otherwise specified.
PARAMETER

SYMBOL

MAX. LIMIT

t++
ADDRESS OR ENABLE TO
OUTPUT DELAY

t_+
t+_
---

t -<;N

UNIT

18

ns

18

ns

18

ns
ns

18

(1)

INPUT CAPACITANCE

1. This parameter

IS

perood,cally sampled and

IS

4(typ.)
5(typ,)

P8205
C8205

TEST CONDITIONS

pF
pF

f

=1

= OV
= 2.0V. T A = 250 e

MHz. Vee

vBIAS

not 100% tested.

TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE

ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
20r-----~----~----,_----~

20r-------~------~1~------,

Vee = 5,OV

vee = 5,OV
CL = 30 pF

TA = 25"C

~_ 15r-------+-------~1------_1

~111-~

t

t

.L

_____ _

- - - - - - --!.-~~:..-

~ ~

t_+

I

w..l

~~

to

:J!5
wI>.

~~
0°
«

OL-______

oL-----~----~----~----~

o

50

100

t50

5r------+--------+--------;

o

200

LOAD CAPACITANCE (pF)

~

25

______

~

______-J

50

AMBIENT TEMPERATURE (OCI

xxxiii

75

inter

Silicon Gate MOS 8702A
2048 BIT ERASABLE AND ELECTRICALLY
REPROGRAM MABLE READ ONLY MEMORY

• Access Time -1.3 J.Lsec
Max.
• Fast Programming - 2 Minutes for
All 2048 Bits

• Inputs and Outputs TTL Compatible
• Three-State Output Capability

OR-Tie

• Simple Memory Expansion Chip
Select Input Lead

• Fully Decoded, 256 x 8 Organization
• Static MOS - No Clocks Required

The 8702A is a 256 word by 8 bit electrically programmable ROM ideally suited for microcomputer system
development where fast turn-around and pattern experimentation are important. The 8702A undergoes
complete programming and functional testing on each bit position prior to shipment, thus insuring 100%
programmability.
The8702A is packaged in a 24 pin dual-in line package with a transparent quartz lid. The transparent quartz
lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be
written into the device. This procedure can be repeated as many times as required.
The circuitry of the 8702A is entirely static; no clocks are required.
A pin-for-pin metal mask programmed ROM, the Intel 8302, is ideal for large volume production runs of
systems initially using the 8702A.
The 8702A is fabricated with silicon gate technology. This low threshold technology allows the design and
production of higher performance MaS circuits and provides a higher functional density on a monolithic
chip than conventional MaS technologies.
BLOCK DIAGRAM

PIN CONFIGURATION
A2

24

voo

DATA OUT 1

AT

2

23

Vee

Ao

3

22

Vee

'DATA OUT 1

4 (LSB)

21

'DATA OUT 2

5

20

A4

'DATA OUT 3

6

19

As

'DATA OUT 4

7

18

As

'DATA OUT 5

8

17

A7

'DATA OUT 6

9

16

VGG

'DATA OUT 7

10

15

Vaa

'DATA OUT 8

11 (MSB)

14

CS

12

13

PROGRAM

CS

PROGRAM-

OUTPUT
BUFFERS

2048 BIT
PROM MATRIX
(256 X 8)

8702A

Vee

DATA OUT 8

Ao AT
'THIS PIN IS THE DATA INPUT LEAD DURING PROGRAMMING.

PIN NAMES
AO-A,

ADDRESS INPUTS

CS

CHIP SELECT INPUT

DOT- 002

DATA OUTPUTS

xxxiv

A7

SILICON GATE MOS 8702A
PIN CONNECTIONS
The external lead connections to the 8702A differ, depending on whether the device is being programmed (1) or used in read
mode. (See following table.)

~

MODE
Read

Programming

14
(CS)

15

23

(Vee)

16
(VGG )

22

(Vee)

13
(Program)

(Vee)

(Vee)

Vee

Vee

GND

Vee

VGG

Vee

Vee

GND

Program Pulse

GND

Vee

Pulsed VGG (VIL4P )

GND

GND

12

ABSOLUTE MAXIMUM RATINGS*
'COMMENT

Ambient Temperature Under Bias . . . . . . . . OOC to +70 0 C
Storage Temperature . . . . . . . . . . . . . -65°C to +125°C
Soldering Temperature of Leads (10 sec) . . . . . . . . +300 0 C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 2 Watts
Read Operation: Input Voltages and Supply

Stresses above those listed under "Absolute Maximum Rat·
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

Voltages with respect to Vee . . . . . . . . . . +0.5V to -20V
Program Operation: Input Voltages and Supply
Voltages with respect to Vee . . . . . . . . . . . . . . . . -48V

READ OPERATION
D.C. AND OPERATING CHARACTERISTICS
T A = ooe to 700 e, Vec = +5V±5%, Voo = -9V±5%, V6~ = -9V±5%, unless otherwise noted.
MIN.

TYP.(3) MAX.

UNIT

CONDITIONS

SYMBOL

TEST

III

Address and Chip Select
Input Load Current

10

fJA

V IN = O.OV

ILO

Output Leakage Current

10

fJA

V OUT = O.OV, CS = Vcc-2

1000

Power Supply Current

5

10

mA

VGG=Vee' CS=Vce- 2
10L = O.OmA, T A = 25°C

1001

Power Supply Current

35

50

mA

CS=Vee -2
10L =O.OmA, TA = 25°C

1002

Power Supply Current

32

46

mA

CS=O.O
10L =O.OmA, TA = 25°C

IDD3

Power Supply Current

38.5

60

mA

CS=Vec -2
10L =O.OmA , T A = ooC

ICF1

Output Clamp Current

8

14

mA

V OUT = -1.0V, T A = OOC

leF2

Output Clamp Current

13

mA

VOUT = -1.0V, TA = 25°C

IGG

Gate Supply Current

10

fJA

V1L1

Input Low Voltage for
TTL Interface

-1.0

VIL2

Input Low Voltage for
MOS Interface

VOO

Vee-6

V

V ee -2

Vee +0.3

V

Note 1:
Note 2:
Note 3:

V 1H

Address and Chip Select
Input High Voltage

10L

Output Sink Current

VOL

Output Low Voltage

V OH

Output High Voltage

0.65

Continuous
Operation

V

-

1.6

4
-.7

mA
0.45

3.5

V OUT = 0.45V

V

10L = 1.6mA

V

10H = -200!J.A

In the programming mode, the data inputs 1-8 are pins 4-11 respectively. es = GNO.
VGG may be clocked to reduce power dissipation. In this mode average 100 increases in proportion to VGG duty cycle. (See p. 5)
Typical values are at nominal voltages and T A = 25° e.

xxxv

SILICON GATE MOS 8702A
A.C. CHARACTERISTICS

T A = fY e to + 70 o e, Vee = +5V ±5%, Voo = -9V ±5%, VGG = -9V ±5% unless otherwise noted
MINIMUM

TEST

SYMBOL

TYPICAL

MAXIMUM

UNIT

1

MHz

Freq.

Repetition Rate

tOH

Previous read data valid

100

ns

tAe e

Address to output delay

1.3

IlS
IlS

tovGG
tes

Clocked VGG set up

I

1.0

Chip select delay

400

teo

Output delay from CS

900

too
t oHe

Output deselect

400

ns

5

IlS

i

Data out hold in clocked VGG mode (Note 1)

ns

i

ns

The output will remain valid for tOHC as long as clocked VGG is at Vee. An address change may occur as soon as the output is sensed
(clocked VGG may still be at Vee). Data becomes invalid for the old address when clocked VGG is returned to VGG.

Note 1.

CAPACITANCE*
SYMBOL

TEST

MINIMUM

C IN

Input Capacitance

COUT

Output Capacitance

C VGG

VGG Capacitance
(Clocked VGG Mode)

UNIT

TYPICAL

MAXIMUM

8

15

pF

10

15

pF

30

pF

CONDITIONS

~N'

vee}

This parameter is periodically sampled and is not 100% tested.

B)

SWITCHING CHARACTERISTICS

Clocked V GG Operation
CYCL~ TIME

J...

V'H~"O%

ADDRESS

..

~9~rn~'

Conditions of Test:
Input pulse amplitudes: 0 to 4V; t R , tF S50 ns
Output load is 1 TTL gate; measurements made
at output of TTL gate (t pD S 15 ns)

Vlt

-: t--

~

tOVGG

I I

CLOCKED

l/F REO

__________

::~ \~_______.....,.. -:.-==_,_o_"'_~
______

CS

Vee

TI~~E

e,'
.....-I

1 FREO

I

A) Constant VGG Operation
CYCLE

All
unused pins
are at A.C.
ground

CS = Vee
VOUT = Vee
VGG = Vee

I 1

DATA

OUT

V,H
ADDRESS
VOH

V
..I\.

V"

DATA

,.....- - - - - - - - - - - - - - - I
NOTE 2
--,
~ ~ Ons
I

OUT

x'----

,It - - - _.... - -

V'Hl

B

Vil

OESELECTION OF DATA OUTPUT IN OR TIE OPERATION

AD:'~SX:

DESELECTION OF DATA OUTPUT IN OR TIE OPERATION

I

--I ' -

VCC"{':
CLOCKED

Vee

t

too----.

DVGG

/

::

1

VGG

I'-I-----...J'
1

10%

-";"1---..,

' DATA OU-T

DATA

OUT
VOL

---r.(l()--:.........

-

too

V

.2' SOns

1
VOH

V OH

-7'-;---

:-"cc --\'._________
I

\

r

.1

~r--------

VOL
NOTE 1

IS at

Vee-

The output will remain valid tor tOHC as long as clocked VGG

An address change may occur as soon as- the output is sensed

(clocked VGG may still be at

Veel.

Data becomes invalid ~or the old

address when clocked VGG is returned to VGG·
NOTE 2' It CS makes a tram,ttion from VIL to VtH while clocked VGG
IS at VGG, then deselectlon of output occurs at too as shown In static
operation With constant VGG'

xxxvi

SILICON GATE MOS 8702A

TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
VDD SUPPLY VOLTAGE

100 CURRENT VS. TEMPERATURE
31

31
37
31

35

1
..

:M

z

33

a:
a:

32

.
::>
u

!

I

\.

INPUTS· Vee

"iiiz

OUTPUTS ARE MEN

."\

3'

LLl

~'Vee

" "i.

21

TT

60

10

a:
a:

Vee

70

10

'-

~ -3.&1--t-""

I

.15v I

I

VGG - -IV
VOM - O.OV

~::>

r-

o

.P-4L-_.l....-_.L-_.L-_.L-_-'-_-'---'

-

~

,....-1::-

rr

OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE

1.

AVERAGE CURRENT VS. DUTY
CYCLE FOR CLOCKED VGG
4 .0

I

C

....

- +5V

"

- z

C

!

8.0

Q
_Q

iii

6.0

5

i

V
-4

-3

...""'a:

/v

4.0

_6/

.

~

-1

Voo

30

'000
0

+'

+3

'" V 1H
=

~

~
~

I

.0

20

:--

!

--

~

L...-

~~

2SoC

+4

o

30

40

.-

50

110

70

10

90

ACCESS TIME VS.
TEMPERATURE

.400

'400

'300

;300

'200

'200

1100

1100

Iw

,OlIO

;; 1000

;::
gj

900

'2

:IE

;::
, TTL LOAD

BOO
700

Vee

= +5V

Voo • -9V
VaG • -9V

600

TA

900

~

r-r--

~

BOO

, TTL LOAD ~ 20 pf

700

Vee • +5V
Voo = -9V
VGG • -9V

&00

~

• 2S°C

-

500

500
Q

oro

20

30

40

50

110

ro

110

--

I

OUTY CYCLE C,.I

ACCESS TIME VS.
LOAD CAPACITANCE

~

i

,

OUTPUT VOLTAGE (VOLTS)

:IE

+

5

o
+2

a;

20
.5

I I
'-9V
.. -9V

TA

25

.0

V!2.0
-2

CLOCKED VOG

'00,35

VaG" -9v
TA
• 250 C -

10.0 -

. 7:)7~
-~

::>
u

1.1

!

40

'2.0 - V
OO ' - 9 V -

Z

~

45

I

I
Vee

!

o ro

9O~

LOAD CAPACITANCE CpFI

20

30

40

50

50

ro

AMBIENT TEMPERATURE (OCI

xxxvii

90

AMBIENT TEMPERATURE IOCt

yoo- -IV

"'ua:

AMBIENT TEMPERATURE lOCI

20304050110

'0

-3

a

flO

'00

I

0

~

-- ~

I
20

..

~

1 I

27

1

C

!

C$. O.OV

28

VaG- -IV

VOL· +.45Y- ,....-

'::::-. ........r-

I"

Q

.!' 30

vDO - -IV

""-

I

l'\ 1"\ 1
'''\

~

0:

a

-

VOG - -IV

"-

i

-

voo - -IV

"-

i

1 1

Vee· +5v

\.

OUTPUT CURRENT VS.
TEMPERATURE

10

90

.00

SILICON GATE MOS 8702A

PROGRAMMING OPERATION
D.C. AND OPERATING CHARACTERISTICS FOR PROGRAMMING OPERATION
TA = 25°C, Vee
SYMBOL

TEST

I Ll1 P
ILI2P
IBB
IDDp I1)
VIHP
V IL1P

------

---

VIL2P
VIL3P
VIL4P
Note 1:

= OV, VBB = +12V ± 10%, CS = OV unless otherwise noted
MIN.

Address and Data Input
Load Current
Program and VGG
Load Current
VBB Supply Load Current
Peak ID D Supply
Load Current
Input High Voltage
Pulsed Data Input
Low Voltage
Address Input Low
Voltage
Pulsed Input Low VDD
and Program Voltage
Pulsed Input Low
VGG Voltage

---~

TYP.

MAX.

UNIT

10

mA

VIN

= -48V

10

mA

VIN

= -48V

VDO
VGG

= VproV= -48V
= -35

mA
mA

.05
200

CONDITIONS

V

-46

0.3
-48

V- - - - - - -

-40

-48

V

-46

-48

V

-35

-40

V

---

----

~------

IDOP flows only during VOO. VGG on time. IDDP should not be allowed to exceed 300mA for greater than 100,"sec. Average power
supply current IDOP is typically 40mA at 20% duty cycle.

A.C. CHARACTERISTICS FOR PROGRAMMING OPERATION
TAMBIENT

= 25°C. Vee = OV, VBB

SYMBOL

=

+ 12V ± 10%. CS

TEST

MIN.

= OV unless otherwise noted

TYP.

Duty Cycle (VOO ' VGG )

MAX.

UNIT

20

%

3

ms

t¢pw

Program Pulse Width

tow

Data Set Up Ti me

25

ps

tOH

Data Hold Time

10

ps

tvw

Voo ,VGG Set Up

100

ps

tvo

VOO ' VGG Hold

10

tACW (2)

Address Complement
Set Up

25

ps

tACH (2)

Address Complement
Hold

25

ps

tATW

Address True Set Up

TO

ps

tATH

Address True Hold

10

ps

Note 2.

All

8

255)

100

CONDITIONS

VGG = -35V, Voo
Vprog = -48V

=

ps

address bits must be in the complement state when pulsed VDD and VGG move to their negatrve levels. The addresses (0 through
must be programmed as shown in the timing diagram for a minimu~ of 32 times.

xxxviii

SILICON GATE MOS 8702A
SWITCHING CHARACTERISTICS FOR PROGRAMMING OPERATION
PROGRAM OPERATION
Conditions of Test:
Input pulse rise and fall times S lJ,Lsec

CS

= OV

PROGRAM WAVEFORMS

--I tACH/-I

tAcw---~'1

I

I

I

I

o
ADDRESS

91NARY COMPLEMENADDRESS OF WORD
TO BE PROGRAMMED

BINARY ADDRESS
OF WORD TO BE
PROGRAMMED

-40 to -48

I

II

0------------.. .

----," tvo : - -

--: I--tATW
I

PULSED VOO
POWER SUPPLY

1
1

I
1

I

I

1

I

I

1

I

-46 to-48

1

1

I

1

:

I

1

~~:~pp~~

1

I

1

i

\

-35to-40

1

1

I
f' :

0 - - - - - - - - - - - -....1

1

I

1

1

~tvw'"

O--------.~I

!

,

1

1
1

I

1
1
r-ttPPW-1 1

PROGRAMMING

~

PULSE
-46to-48

} .

1
' I

r--tow-,
1

1
1

rtATH~

1 1

1

'I

1

-ltOHr--1

DATA STABLE
TIME
-46 to

PROGRAMMING OPERATION OF THE 8702A
ADDRESS
When the Data I nput for
the Program Mode is:

Then the Data Output
during the Read Mode is:

WORD
0

VILIP = --48V pulsed

Logic 1 = VOH = 'P' on tape

VIHP=- OV

Logic 0 = VOL ='N' on tape

A7

A6

A5

A4

A2

A1

AO
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

I
I

I
I

I
I

I
I

I
I

I
I

I
I

255

Address Logic Level During Read Mode:

Logic 0 = VIL (- .3V)

Logic 1 = VIH ( - 3V)

Address Logic Level During Program Mode:

Logic 0 = VIL2P (--40V)

Logic 1 = VIHP (-OV)

xxxix

A3

SILICON GATE MOS 8702A
PROGRAMMING INSTRUCTIONS
FOR THE 8702A
I. Operation of the 8702A in
Program Mode
Initially, all 2048 bits of the ROM are in
the "0" state (output low). Information
is introduced by selectively programming "1 "s (output high) in the proper
bit locations.
Word address selection is done by the
same decoding circuitry used in the
READ mode (see table on page 6 for
logic levels). All 8 address bits must be
in the binary complement state when
pulsed VDD and VGG move to their negative levels. The addresses must be held
in their binary complement state for a
minimum of 25 I(sec after VDD and VGG
have moved to their negative levels.
The addresses must then make the
transition to their true state a minimum
of 10 ,usec before the program pulse
is applied. The addresses should be
programmed in the sequence 0 through
255 for a minimum of 32 times. The
eight output terminals are used as data
inputs to determine the information
pattern in the eight bits of each word.
A low data input level (- 48V) will program a "1" and a high data input level
(ground) will leave a "0" (see table on
page 6). All eight bits of one word are
programmed simultaneously by setting
the desired bit information patterns on
the data input terminals.
During the programming, VGG , VDD and
the Program Pulse are pulsed signals.

II. Programming of the 8702A UsIng
Intel Microcomputers
Intel provides low cost program development systems which may be used to
program its electrically programmable
ROMs. Note that the programming
specifications that apply to the 8702A
are identical to those for Intel's 1702A.
A. Intellec 8
The Intellec series of program development systems, the Intellec
8/Mod 8 and Intellec 8/Mod 80, are
used as program development tools
for the 8008 and 8080 microprocessors respectively. As such, they are
equipped with a PROM programmer
card and may be used to program
Intel's electrically prog ram mabie
and ultraviolet erasable ROMs.
An ASR-33 teletype terminal is used
as the input device. Through use of
the Intellec software system monitor,
programs to be loaded into PROM
may be typed in directly or loaded
through the paper tape reader. The
system monitor allows the program
to be reviewed or altered at will
prior to actually programming the
PROM. For more complete information on these program development
systems, refer to the Intel Microcomputer Catalog or the Intellec
Spec ifications.
B. Users of the SIM8 microcomputer
programming systems may also
program the 8702A using the
MP7-03 programmer card and the
appropriate control ROMs:
SIM8 system-Control ROMs
A0860, A0861 and A0863.

xxxx

III. 8702A Erasing Procedure
The 8702A may be erased byexposure to high intensity short-wave ultraviolet light at a wavelength of 2537A.
The recommended integrated dose (i.e.,
UV intensity x exposure time) is
6W-sec/cm2. Examples of ultraviolet
sources which can erase the 8702A
in 10 to 20 minutes are the Model
UVS-54 and Model S-52 short-wave
ultraviolet lamps manufactured by
Ultra-Violet Products, Inc. (5114 Walnut
Grove Avenue, San Gabriel, California).
The lamps should be used without
short-wave filters, and the 8702A to
be erased should be placed about one
inch away from the lamp tubes.

The INTELLEC 8 uses a seven-bit ASCII code, which is the normal 8 bit ASCII code with the parity (high order) bit
always reset_

GRAPHIC OR CONTROL
NULL
SaM
EOA
EOM
EaT
WRU
RU
BELL
FE
H. Tab
Line Feed
V. Tab
Form
Return
SO
SI
DCa
X-On
Tape Aux. On
X-Off
Tape Aux. Off
Error
Sync
LEM
SO
S1
S2
S3

S4
S5
S6
S7

ASCII (HEXADECIMAL)

GRAPHIC OR CONTROL
ACK
Alt. Mode
Rubout

00
01
02
03

04

#

05
06
07

$
%
&

08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C

*

+

/

<
>
?
[

/

l
t
+-

10

@

1E
1F

blank
0

xxxxi

ASCII (HEXADECIMAL)
7C
70
7F
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
3A
3B
3C
3D
3E
3F
5B
5C
50
5E
5F
40
20
30

GRAPHIC OR CONTROL

1
2
3
4
5
6
7
8
9
A
8
C
D
E

F
G
H
I
J
K

L
M
N

0
P
Q

R

S
T
U
V

W
X
y
Z

ASCII (HEXADECIMAL)

31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
47
48
49
4A
48
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A

xxxxii

HEXADECIMAL ARITHMETIC
ADDITION TABLE
0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

1
2
3

02
03
04

03
04
05

04
05
06

05
06.
07

06
07
08

07
08
09

08
09
OA

09
OA
OB

OA
OB
OC

OB
OC
OD

OC
OD
OE

OD
OE
OF

OE
OF
10

OF
10
11

10
11
12

4
5
6

05
06
07

06
07
08

07
08
09

08
09
OA

09
OA
OB

OA
OB
OC

OB
OC
OD

OC
OD
OE

OD
OE
OF

OE
OF
10

OF
10
11

10
11
12

11
12
13

12
13
14

13
14
15

7
8
9

08
09
OA

09
OA
OB

OA
OB
OC

OB
OC
OD

OC
OD
OE

OD
OE
OF

OE
OF
10

Of
10
11

10
11
12

11
12
13

12
13
14

13
14
15

14
15
16

15
16
17

16
17
18

A
B
C

OB
OC
OD

OC
OD
OE

OD
OE
OF

OE
OF
10

OF
10
11

10
11
12

11
12
13

12
13
14

13
14
15

14
15
16

15
16
17

16
17
18

17
18
19

18
19
1A

19
1A
1B

D
E
F

OE
OF
10

OF
10
11

10
11
12

11
12
13

12
13
14

13
14
15

14
15
16

15
16
17

16
17
18

17

18
19

18
19
1A

19
1A
1B

1A
1B
1C

1B
1C

10

10

1E

1C

MULTIPLICATION TABLE
1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

2
3

04
06

06
09

08
OC

OA
OF

OC
12

OE
15

10
18

12
1B

14
1E

16
21

18
24

1A
27

1C
2A

1E
2D

4
5
6

08
OA
OC

OC
OF
12

10
14
18

14
19
1E

18
1E
24

1C
23
2A

20
28
30

24
2D
36

28
32
3C

2C
37
42

30
3C
48

34
41
4E

38
46
54

3C
4B
5A

7
8
9

OE
10
12

15
18
1B

1C
20
24

23
28
2D

2A
30
36

31
38
3F

38
40
48

3F
48
51

46 4D
50 58
5A' 63

54

60
6C

5B
68
75

62
70
7E

69
78
87

A

1E
21
24

28
2C
30

32
37
3C

3C
42
48

46
4D

5A
63
6C

64
6E
78

84

54

50
58
60

6E
79

C

14
16
18

84

90

82
8F
9C

8C
9A
A8

96
A5
B4

D
E
F

1A
1C
1E

27
2A
2D

34
38
3C

41
46
48

4E

5B
62
69

68
70
78

75
7E
87

82
8C
96

8F
9A
A5

9C
A8
B4

A9
B6
C3

B6
C4
D2

C3
D2
E1

B

54

5A

xxxxiii

78

POWERS OF TWO

1
2
4
8

0
1
2
3

1.0
0.5
0.25
0.125

16
32
64
128

4
5
6
7

0.062
0.031
0.015
0.007

256 8 0.003
512 9 0.001
1 024 10 0.000
2 048 11 0.000

1
2
4
9

5
25
625
812 5
906
953
976
488

25
125
562 5
281 25

4
8
16
32

096
192
384
768

12
13
14
15

0.000
0.000
0.000
0.000

244
122
061
030

140
070
035
517

625
312 5
156 25
578 125

65
131
262
524

536
072
144
288

16
17
18
19

0.000
0.000
0.000
0.000

015
007
003
001

258
629
814
907

789
394
697
348

062
531
265
632

5
25
625
812 5

1
2
4
8

048
097
194
388

576
152
304
608

20
21
22
23

0.000
0.000
0.000
0.000

000
000
000
000

953
476
238
119

674
837
418
209

316
158
579
289

406
203
101
550

25
125
562 5
781 25

16
33
67
134
268
536
1 073
2 147

777
554
108
217
435
870
741
483

216
432
864
728
456
912
824
648

24
25
26
27
28
29
30
31

0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000

000
000
000
000
000
000
000
000

059
029
014
007
003
001
000
000

604
802
901
450
725
862
931
465

644
322
161
580
290
645
322
661

775
387
193
596
298
149
574
287

390
695
847
923
461
230
615
307

625
312
656
828
914
957
478
739

5
25
125
062
031
515
257

5
25
625
812 5

4
8
17
34

294
589
179
359

967
934
869
738

296
592
184
368

32
33
34
35

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

232
116
058
029

830
415
207
103

643
321
660
830

653
826
913
456

869
934
467
733

628
814
407
703

906
453
226
613

25
125
562 5
281 25

68
137
274
549

719
438
877
755

476
953
906
813

736
472
944
888

36
37
38
39

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

014
007
003
001

551
275
637
818

915
957
978
989

228
614
807
403

366
183
091
545

851
425
712
856

806
903
951
475

640
320
660
830

625
312 5
156 25
078 125

1
2
4
8

099
199
398
796

511
023
046
093

627
255
511
022

776
552
104
208

40
41
42
43

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

909
454
227
113

494
747
373
686

701
350
675
837

772
886
443
721

928
464
232
616

237
118
059
029

915
957
478
739

039
519
759
379

062
531
765
882

5
25
625
812 5

17
35
70
140

592
184
368
737

186
372
744
488

044
088
177
355

416
832
664
328

44
45
46
47

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

056
028
014
007

843
421
210
105

418
709
854
427

860
430
715
357

808
404
202
601

014
007
003
001

869
434
717
858

689
844
422
711

941
970
485
242

406
703
351
675

25
125
562 5
781 25

281
562
1 125
2 251

474
949
899
799

976
953
906
813

710
421
842
685

656
312
624
248

48
49
50
51

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

003
001
000
000

552
776
888
444

713
356
178
089

678
839
419
209

800
400
700
850

500
250
125
062

929
464
232
616

355
677
338
169

621
810
905
452

337
668
334
667

890
945
472
236

625
312 5
656 25
328 125

4
9
18
36

503
007
014
028

599
199
398
797

627 370
254 740
509481
018 963

496
992
984
968

52
53
54
55

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

222
111
055
027

044
022
511
755

604
302
151
575

925
462
231
615

031
515
257
628

308
654
827
913

084
042
021
510

726
363
181
590

333
166
583
791

618
809
404
702

164
082
541
270

062 5
031 25
015625
507 812 5

72
144
288
576

057
115
230
460

594
188
376
752

037
075
151
303

927
855
711
423

936
872
744
488

56
57
58
59

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

013
OOG
003
001

877
938
469
734

787
893
446
723

807
903
951
475

814
907
953
976

456
228
614
807

755
377
188
094

295
647
823
411

395
697
848
924

851
925
962
481

135
567
783
391

253
676
813
906

906
950
476
738

25
125
562 5
281 25

152
305
611
223

921
843
686
372

504
009
018
036

606
213
427
854

846
693
387
775

976
952
904
808

60
61
62
63

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

867
433
216
108

361
680
840
420

737
868
434
217

988
994
497
248

403
201
100
550

547
773
886
443

205
602
801
400

962
981
490
745

240
120
560
280

695
347
173
086

953
976
988
994

369
684
342
171

140
570
285
142

xx)(xiv

625
312 5
156 25
578 125

TABLE OF POWERS OF SIXTEEN IO
16 n
1

o

16

4

0.10000

00000

00000

00000

x

10

0.62500

00000

00000

00000

X

10-1

256

2

0.39062

50000

00000

00000

X

10- 2

4

096

3

0.24414

06250

00000

00000

X

10- 3

65

536

4

0.15258

78906

25000

00000

X

10- 4

048

576

0.95367

43164

06250

00000

10- 6

16

777

216

5
6

X

0.59604

64477

53906

25000

X

10- 7

268

435

456

7

0.37252

90298

46191

40625

X

10-8

294

967

296

0.23283

06436

53869

62891

X

10-9

0.14551

91522

83668

51807

X

10-10

0.90949

47017

72928

23792

X

10-12
10-13
10-14

68

719

476

736

8
9

099

511

627

776

10

4

16,n

n

17

592

186

044

416

11

0.56843

41886

08080

14870

X

281

474

976

710

656

12

0.35527

13678

80050

09294

X

503

599

627

370

496

13

0.22204

46049

25031

30808

X

10-15
10-16
10-18

057

594

037

927

936

14

0.13877

78780

78144

56755

X

152 921

504

606

846

976

15

0.86736

17379

88403

54721

X

72

TABLE OF POWERS OF 10 16
n

2

o

1.0000

A

1

64

2

3E8
2710

0000

0000

0000

0.1999

9999

9999

999A

0.28F5

C28F

5C28

F5C3

X

16- 1

3

0.4189

374B

C6A7

EF9E

X

16- 2
16- 3

0.680B

8BAC

710C

B296

1

86AO

4
5

X

0.A7C5

AC47

1B47

8423

X

16-4

F

4240

6

0.10C6

F7AO

B5ED

8037

X

16-4

98

9680

7

0.1 A07

F29A

BCAF

4858

X

16- 5

16- 6

5F5

El00

0.2AF3

10C4

6118

73BF

3B9A

CAOO

8
9

X

0.44B8

2FAO

9B5A

52CC

X

16- 7

540B

E400

10

0.60F3

7F67

SEF6

EAOF

X

16-8

O.AFEB

FFOB

CB24

AAFF

X

16-9

1119

X

16-9

X

16- 10

17

4876

E800

11

E8

04A5

1000

12

0.1197

9981

20EA

918

4E72

AOOO

13

0.1 C25

C268

4976

81C2

5AF3

107 A

4000

14

0.2009

3700

4257

3604

X

16- 11
16 -12

16-\3
16 -14

3

807E

A4C6

8000

15

OA80E

BE7B

9058

5660

X

23

8652

6FCl

0000

16

0.734A

CA5F

6226

FOAE

X

163

4578

508A

0000

17

0.B877

AA32

36A4

B449

X

OEO

B6B3

A764

0000

18

0.1272

5001

0243

ABAl

X

16 -14

AC3'5

X

16 -IS

8AC7

2304

89E8

0000

19

0.1083

C94F

xxxxv

B602

HEXADECIMAL-DECIMAL INTEGER CONVERSION
The table below provides for direct conversions between hexadecimal integers in the range O-FFF and decimal integers in the
range 0-4095_ For conversion of larger integers, the table values may be added to the following figures:
Hexadecimal

Decimal

Hexadecimal

Decimal

01 000
02000
03000
04000
05000
06000
07000
08000
09000
OA 000
OB 000
OC 000
00000
OE 000
OF 000
10000
11 000
12000
13000
14000
15000
16000
17000
18000
19000
lA 000
18000
lC 000
10000
1 E 000
1 F 000

4096
8 192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61 440
65536
69632
73728
77 824
81 920
86016
90112
94208
98304
102400
106496
110592
114688
118 784
122880
126976

20000
30000
40000
50000
60000
70000
80000
90000
AD 000
BO 000
CO 000
DO 000
EO 000
FO 000
100000
200000
300000
400000
500000
600000
700000
800000
900000
AOO 000
800000
COO 000
000000
EOO 000
FOO 000
1 000000
2000000

131 072
196608
262 144
327680
393216
458752
524288
589824
655360
720896
786432
851 968
917 504
983040
1 048576
2097 152
3 145728
4194304
5242880
6291 456
7340032
8388608
9437 184
10485760
11 534336
12582912
13631 488
14680064
15728640
16777216
33554432

0

1

2

3

4

5

6

7

8

9

A

8

C

0

E

F

000
010
020
030

0000
0016
0032
0048

0001
0017
0033
0049

0002
0018
0034
0050

0003
0019
0035
0051

0004
0020
0036
0052

0005
0021
0037
0053

0006
0022
0038
0054

0007
0023
0039
0055

0008
0024
0040
0056

0009
0025
0041
0057

0010
0026
0042
0058

0011
0027
0043
0059

0012
0028
0044
0060

0013
0029
0045
0061

0014
0030
0046
0062

0015
0031
0047
0063

040
050
060
070

0064
0080
0096
0112

0065 0066
0081 0082
0097 0098
0113 0114

0067
0083
0099
0115

0068
0084
0100
0116

0069
0085
0101
0117

0070
0086
0102
0118

0071
0087
0103
0119

0072
0088
0104
0120

0073
0089
0105
0121

0074
0090
0106
0122

0075
0091
0107
0123

0076
0092
0108
0124

0077
0093
0109
0125

0078
0094
0110
0126

0079
0095
0111
0127

080
090
OAO
080

0128
0144
0160
0176

0129
0145
0161
0177

0130
0146
0162
0178

0131
0147
0163
0179

0132 0133
0148 0149
0164 0165
0180 0181

0134
0150
0166
0182

0135
0151
0167
0183

0136
0152
0168
0184

0137
0153
0169
0185

0138
0154
0170
0186

0139
0155
0171
0187

0140
0156
0172
0188

0141
0157
0173
0189

0142
0158
0174
0190

0143
0159
0175
0191

OCO
000
OED
OFO

0192
0208
0224
0240

0193
0209
0225
0241

0194
0210
0226
0242

0195
0211
0227
0243

0196
0212
0228
0244

0197
0213
0229
0245

0198
0214
0230
0246

0199
0215
0231
0247

0200
0216
0232
0248

0201
0217
0233
0249

0202
0218
0234
0250

0203
0219
0235
0251

0204
0220
0236
0252

0205
0221
0237
0253

0206
0222
0238
0254

0207
0223
0239
0255

xxxxvi

HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)

1
0257
0273
0289
0305

2
0258
0274
0290
0306

3
0259
0275
0291
0307

4
0260
0276
0292
0308

5
0261
0277
0293
0309

6
0262
0278
0294
0310

7
0263
0279
0295
0311

8
0264
0280
0296
0312

9
0265
0281
0297
0313

A
0266
0282
0298
0314

8
0267
0283
0299
0315

C
0268
0284
0300
0316

D

E

F

100
110
120
130

0
0256
0272
0288
0304

0269
0285
0301
0317

0270
0286
0302
0318

0271
0287
0303
0319

140
150
160
170

0320
0336
0352
0368

0321
0337
0353
0369

0322
0338
0354
0370

0323
0339
0355
0371

0324
0340
0356
0372

0325
0341
0357
0373

0326
0342
0358
0374

0327
0343
0359
0375

0328
0344
0360
0376

0329
0345
0361
0377

0330
0346
0362
0378

0331
0347
0363
0379

0331
0348
0364
0380

0333
0349
0365
0381

0334
0350
0366
0382

0335
0351
0367
0383

180
190
lAO
180

0384
0400
0416
0432

0385
0401
0417
0433

0386
0402
0418
0434

0387
0403
0419
0435

0388
0404
0420
0436

0389
0405
0421
0437

0390
0406
0422
0438

0391
0407
0423
0439

0392
0408
0424
0440

0393
0409
0425
0441

0394
0410
0426
0442

0395
0411
0427
0443

0396
0412
0428
0444

0397
0413
0429
0445

0398
0414
0430
0446

0399
0415
0431
0447

lCO
lDO
lEO
1 FO

0448
0464
0480
0496

0449
0465
0481
0497

0450
0466
0482
0498

0451
0467
0483
0499

0452
0468
0484
0500

0453
0469
0485
0501

0454
0470
0486
0502

0455
0471
0487
0503

0456
0472
0488
0504

0457
0473
0489
0505

0458
0474
0490
0506

0459
0475
0491
0507

0460
0476
0492
0508

0461
0477
0493
0509

0462
0478
0494
0510

0463
0479
0495
0511

200
210
220
230

0512
0528
0544
0560

0513
0529
0545
0561

0514
0530
0546
0562

0515
0531
0547
0563

0516
0532
0548
0564

0517
0533
0549
0565

0518
0534
0550
0566

0519
0535
0551
0567

0520
0536
0552
0568

0521
0537
0553
0569

0522
0538
0554
0570

0523
0539
0555
0571

0524
0540
0556
0572

0525
0541
0557
0573

0526
0542
0558
0574

0527
0543
0559
0575

240
250
260
270

0576 0577 0578
0592 0593 0594
0608 0609 0610
0624 0625 0626

0579
0595
0611
0627

0580
0596
0612
0628

0581
0597
0613
0629

0582
0598
0614
0630

0583
0599
0615
0631

0584
0600
0616
0632

0585
0601
0617
0633

0586
0602
0618
0634

0587
0603
0619
0635

0588
0604
0620
0636

0589
0605
0621
0637

0590
0606
0622
0638

0591
0607
0623
0639

280
290
2AO
2BO

0640
0656
0672
0688

0641
0657
0673
0689

0642
0658
0674
0690

0643
0659
0675
0691

0644
0660
0676
0692

0645
0661
0677
0693

0646
0662
0678
0694

0647
0663
0679
0695

0648
0664
0680
0696

0649
0665
0681
0697

0650
0666
0682
0698

0651
0667
0683
0699

0652
0668
0684
0700

0653
0669
0685
0701

0654
0670
0686
0702

0655
0671
0687
0703

2CO
2DO
2EO
2FO

0704
0720
0736
0752

0705
0721
0737
0753

0706
0722
0738
0754

0707
0723
0739
0755

0708
0724
0740
0756

0709
0725
0741
0757

0710
0726
0742
0758

0711
0727
0743
0759

0712
0728
0744
0760

0713
0729
0745
0761

0714
0730
0746
0762

0715
0731
0747
0763

0716
0732
0748
0764

0717
0733
0749
0765

0718
0734
0750
0766

0719
0735
0751
0767

300
310
320
330

0768
0784
0800
0816

0769
0785
0301
0817

0770
0786
0802
0818

0771
0787
0803
0819

0772
0788
0804
0820

0773
0789
0805
0821

0774
0790
0806
0822

0775
0791
0807
0823

0776
0792
0808
0824

0777
0793
0809
0825

0778
0794
0810
0826

0779
0795
0811
0827

0780
0796
0812
0828

0781
0797
0813
0829

0782
0798
0814
0830

0783
0799
0815
0831

340
350
360
370

0832 0833 0834
0848 0849 0850
0864 0865 0866
0880 0881 0882

0835
0851
0867
0883

0836
0852
0868
0884

0837
0853
0869
0885

0838
0854
0870
0886

0839
0855
0871
0887

0840
0856
0872
0888

0841
0857
0873
0889

0842
0858
0874
0890

0843
0859
0875
0891

0844
0860
0876
0892

0845
0861
0877
0893

0846
0862
0878
0894

0847
0863
0879
0895

380
390
3AO
380

0896
0212
0928
0944

0897
0913
0929
0945

0898
0914
0930
0946

0899
0915
0931
0947

0900
0916
0932
0948

0901
0917
0933
0949

0902
0918
0934
0950

0903
0919
0935
0951

0904
0920
0936
0952

0905
0921
0937
0953

0906
0922
0938
0954

0907
0923
0939
0955

0908
0924
0940
0956

0909
0925
0941
0957

0910
0926
0942
0958

0911
0927
0943
0959

3CO
3DO
3EO
3FO

0960 0961
0976 0977
0992 0993
1008 1009

0962
0978
0994
1010

0963
0979
0995
1011

0964
0980
0996
1012

0965
0981
0997
1013

0966
0982
0998
1014

0967
0983
0999
1015

0968
0984
1000
1016

0969
0985
1001
1017

0970
0986
1002
1018

0971
0987
1003
1019

0972
0988
1004
1020

0973
0989
1005
1021

0974
0990
1006
1022

0975
0991
1007
1023

xxxxvii

HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)

1
1025
1041
1057
1073

2
1026
1042
1058
1074

3
1027
1043
1059
1075

4
1028
1044
1060
1076

5
1029
1045
1061
1077

6
1030
1046
1062
1078

7
1031
1047
1063
1079

8
1032
1048
1064
1080

9
1033
1049
1065
1081

1036
1052
1068
1084

0
1037
1053
1069
1085

F

1034
1050
1066
1082

8
1035
1051
1067
1083

E

400
410
420
430

0
1024
1040
1056
1072

1038
1054
1070
1086

1039
1055
1071
1087

440
450
460
470

1088
1104
1120
1136

1089
1105
1121
1137

1090
1106
1122
1138

1091
1107
1123
1139

1092
1108
1124
1140

1093
1109
1125
1141

1094
1110
1126
1142

1095
1111
1127
1143

1096
1112
1128
1144

1097
1113
1129
1145

1098
1114
1130
1146

1099
1115
1131
1147

1100
1116
1132
1148

1101
1117
1133
1149

1102
1118
1134
1150

1103
1119
1135
1151

480
490
4AO
480

1152
1168
1184
1200

1153
1169
1185
1201

1154
1170
1186
1202

1155
1171
1187
1203

1156
1172
1188
1204

1157
1173
1189
1205

1158
1174
1190
1206

1159
1175
1191
1207

1160
1176
1192
1208

1161
1177
1193
1209

1162
1178
1194
1210

1163
1179
1195
1211

1164
1180
1196
1212

1165
1181
1197
1213

1166
1182
1198
1214

1167
1183
1199
1215

4CO
400
4EO
4FO

1216
1232
1248
1264

1217
1233
1249
1265

1218
1234
1250
1266

1219
1235
1251
1267

1220
1236
1252
1268

1221
1237
1253
1269

1222
1238
1254
1270

1223
1239
1255
1271

1224
1240
1256
1272

1225
1241
1257
1273

1226
1242
1258
1274

1227
1243
1259
1275

1228
1244
1260
1276

1229
1245
1261
1277

1230
1246
1262
1278

1231
1247
1263
1279

500
510
520
530

1280
1296
1312
1328

1281
1297
1313
1329

1282
1298
1314
1330

1283
1299
1315
1331

1284
1300
1316
1332

1285
1301
1317
1333

1286
1302
1318
1334

1287
1303
1319
1335

1288
1304
1320
1336

1289
1305
1321
1337

1290
1306
1322
1338

1291
1307
1323
1339

1292
1308
1324
1340

1293
1309
1325
1341

1294
1310
1326
1342

1295
1311
1327
1343

540
550
560
570

1344
1360
1376
1392

1345
1361
1377
1393

1346
1362
1378
1394

1347
1363
1379
1395

1348
1364
1380
1396

1349
1365
1381
1397

1350
1366
1382
1398

1351
1367
1383
1399

1352
1368
1384
1400

1353
1369
1385
1401

1354
1370
1386
1402

1355
1371
1387
1403

1356
1372
1388
1404

1357
1373
1389
1405

1358
1374
1390
1406

1359
1375
1391
1407

580
590
5AO
580

1408
1424
1440
1456

1409
1425
1441
1457

1410
1426
1442
1458

1411
1427
1443
1459

1412
1428
1444
1460

1413
1429
1445
1461

1414
1430
1446
1462

1415
1431
1447
1463

1416
1432
1448
1464

1417
1433
1449
1465

1418
1434
1450
1466

1419
1435
1451
1467

1420
1436
1452
1468

1421
1437
1453
1469

1422
1438
1454
1470

1423
1439
1455
1471

5CO
500
5EO
5FO

1472
1488
1504
1520

1473
1489
1505
1521

1474
1490
1506
1522

1475
1491
1507
1523

1476
1492
1508
1524

1477
1493
1509
1525

1478
1494
1510
1526

1479
1495
1511
1527

1480
1496
1512
1528

1481
1497
1513
1529

1482
1498
1514
1530

1483
1499
1515
1531

1484
1500
1516
1532

1485
1501
1517
1533

1486
1502
1518
1534

1487
1503
1519
1535

600
610
620
630

1536
1552
1568
1584

1537
1553
1569
1585

1538
1554
1570
1586

1539
1555
1571
1587

1540
1556
1572
1588

1541
1557
1573
1589

1542
1558
1574
1590

1543
1559
1575
1591

1544
1560
1576
1592

1545
1561
1577
1593

1546
1562
1578
1594

1547
1563
1579
1595

1548
1564
1580
1596

1549
1565
1581
1597

1550
1566
1582
1598

1551
1567
1583
1599

640
650
660
670

1600
1616
1632
1648

1601
1617
1633
1649

1602
1618
1634
1650

1603
1619
1635
1651

1604
1620
1636
1652

1605
1621
1637
1653

1606
1622
1638
1654

1607
1623
1639
1655

1608
1624
1640
1656

1609
1625
1641
1657

1610
1626
1642
1658

1611
1627
1643
1659

1612
1628
1644
1660

1613
1629
1645
1661

1614
1630
1646
1662

1615
1631
1647
1663

680
690
6AO
680

1664
1680
1696
1712

1665
1681
1697
1713

1666
1682
1698
1714

1667
1683
1699
1715

1668
1684
1700
1716

1669
1685
1701
1717

1670
1686
1702
1718

1671
1687
1703
1719

1672
1688
1704
1720

1673
1689
1705
1721

1674
1690
1706
1722

1675
1691
1707
1723

1676
1692
1708
1724

1677
1693
1709
1725

1678
1694
1710
1726

1679
1695
1711
1727

6CO
600
6EO
6FO

1728
1744
1760
1776

1729
1745
1761
1777

1730
1746
1762
1778

1731
1747
1763
1779

1732
1748
1764
1780

1733
1749
1765
1781

1734
1750
1766
1782

1735
1751
1767
1783

1736
1752
1768
1784

1737
1753
1769
1785

1738
1754
1770
1786

1739
1755
1771
1787

1740
1756
1772
1788

1741
1757
1773
1789

1742
1758
1774
1790

1743
1759
1775
1791

xxx xviii

A

C

HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)

0

1

2

3

4

6
1798
1814
1830
1846

7
1799
1815
1831
1847

8
1800
1816
1832
1848

9
1801
1817
1833
1849

A
1802
1818
1834
1850

8
1803
1819
1835
1851

C
1804
1820
1836
1852

D
1805
1821
1837
1853

E

F

1796
1812
1828
1844

5
1797
1813
1829
1845

1806
1822
1838
1854

1807
1823
1839
1855

700
710
720
730

1792
1808
1824
1840

1793
1809
1825
1841

1794
1810
1826
1842

1795
1811
1827
1843

740
750
760
770

1856
1872
1888
1904

1857
1873
1889
1905

1858
1874
1890
1906

1859
1875
1891
1907

1860
1876
1892
1908

1861
1877
1893
1909

1862
1878
1894
1910

1863
1879
1895
1911

1864
1880
1896
1912

1865
1881
1897
1913

1866
1882
1898
1914

1867
1883
1899
1915

1868
1884
1900
1916

1869
1885
1901
1917

1870
1886
1902
1918

1871
1887
1903
1919

780
790
7AO
780

1920
1936
1952
1968

1921
1937
1953
1969

1922
1938
1954
1970

1923
1939
1955
1971

1924
1940
1956
1972

1925
1941
1957
1973

1926
1942
1958
1974

1927
1943
1959
1975

1928
1944
1960
1976

1929
1945
1961
1977

1930
1946
1962
1978

1931
1947
1963
1979

1932
1948
1964
1980

1933
1949
1965
1981

1934
1950
1966
1982

1935
1951
1967
1983

7CO
7DO
7EO
7FO

1984
2000
2016
2032

1985
2001
2017
2033

1986
2002
2018
2034

1987
2003
2019
2035

1988
2004
2020
2036

1989
2005
2021
2037

1990
2006
2022
2038

1991
2007
2023
2039

1992
2008
2024
2040

1993
2009
2025
2041

1994
2010
2026
2042

1995
2011
2027
2043

1996
2012
2028
2044

1997
2013
2029
2045

1998
2014
2030
2046

1999
2015
2031
2047

800
810
820
830

2048
2064
2080
2096

2049
2065
2081
2097

2050
2066
2082
2098

2051
2067
2083
2099

2052
2068
2084
2100

2053
2069
2085
2101

2054
2070
2086
2102

2055
2071
2087
2103

2056
2072
2088
2104

2057
2073
2089
2105

2058
2074
2090
2106

2059
2075
2091
2107

2060
2076
2092
2108

2061
2077
2093
2109

2062
2078
2094
2110

2063
2079
2095
2111

840
850
860
870

2112
2128
2144
2160

2113
2129
2145
2161

2114
2130
2146
2162

2115
2131
2147
2163

2116
2132
2148
2164

2117
2133
2149
2165

2118
2134
2150
2166

2119
2135
2151
2167

2120
2136
2152
2168

2121
2137
2153
2169

2122
2138
2154
2170

2123
2139
2155
2171

2124
2140
2156
2172

2125
2141
2157
2173

2126
2142
2158
2174

2127
2143
2159
2175

880
890
8AO
880

2176
2192
2208
2224

2177
2193
2209
2225

2178
2194
2210
2226

2179
2195
2211
2227

2180
2196
2212
2228

2181
2197
2213
2229

2182
2198
2214
2230

2183
2199
2215
2231

2184
2200
2216
2232

2185
2201
2217
2233

2186
2202
2218
2234

2187
2203
2219
2235

2188
2204
2220
2236

2189
2205
2221
2237

2190
2206
2222
2238

2191
2207
2223
2239

8CO
8DO
8EO
8FO

2240
2256
2272
2288

2241
2257
2273
2289

2242
2258
2274
2290

2243
2259
2275
2291

2244
2260
2276
2292

2245
2261
2277
2293

2246
2262
2278
2294

2247
2263
2279
2295

2248
2264
2280
2296

2249
2265
2281
2297

2250
2266
2282
2298

2251
2267
2283
2299

2252
2268
2284
2300

2253
2269
2285
2301

2254
2270
2286
2302

2255
2271
2287
2303

900
910
920
930

2304
2320
2336
2352

2305
2321
2337
2353

2306
2322
2338
2354

2307
2323
2339
2355

2308
2324
2340
2356

2309
2325
2341
2357

2310
2326
2342
2358

2311
2327
2343
2359

2312
2328
2344
2360

2313
2329
2345
2361

2314
2330
2346
2362

2315
2331
2347
2363

2316
2332
2348
2364

2317
2333
2349
2365

2318
2334
2350
2366

2319
2335
2351
2367

940
950
960
970

2368
2384
2400
2416

2369
2385
2401
2417

2370
2386
2402
2418

2371
2387
2403
2419

2372
2388
2404
2420

2373
2389
2405
2421

2374
2390
2406
2422

2375
2391
2407
2423

2376
2392
2408
2424

2377
2393
2409
2425

2378
2394
2410
2426

2379
2395
2411
2427

2380
2396
2412
2428

2381
2397
2413
2429

2382
2398
2414
2430

2383
2399
2415
2431

980
990
9AO
980

2432
2448
2464
2480

2433
2449
2465
2481

2434
2450
2466
2482

2435
2451
2467
2483

2436
2452
2468
2484

2437
2453
2469
2485

2438
2454
2470
2486

2439
2455
2471
2487

2440
2456
2472
2488

2441
2457
2473
2489

2442
2458
2474
2490

2443
2459
2475
2491

2444
2460
2476
2492

2445
2461
2477
2493

2446
2462
2478
2494

2447
2463
2479
2495

9CO
9DO
9EO
9FO

2496
2512
2528
2544

2497
2513
2529
2545

2498
2514
2530
2546

2499
2515
2531
2547

2500
2516
2532
2548

2501
2517
2533
2549

2502
2518
2534
2550

2503
2519
2535
2551

2504
2520
2536
2552

2505
2521
2537
2553

2506
2522
2538
2554

2507
2523
2539
2555

2508
2524
2540
2556

2509
2525
2541
2557

2510
2526
2542
2558

2511
2527
2543
2559

xxxxix

HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)

0

1

2

3

4

5

AOO
Al0
A20
A30

2560
2576
2592
2608

2561
2577
2593
2609

2562
2578
2594
2610

2563
2579
2595
2611

2564
2580
2596
2612

A40
A50
A60
A70

2624
2640
2656
2672

2625
2641
2657
2673

2626
2642
2658
2674

2627
2643
2659
2675

A80
A90
AAO
ABO

2688
2704
2720
2736

2689
2705
2721
2737

2690
2706
2722
2738

ACO
ADO
AEO
AFO

2752
2768
2784
2800

2753
2769
2785
2801

BOO
Bl0
B20
B30

2816
2832
2848
2864

B40
B50
B60
B70

7

8

2565
2581
2597
2613

6
2566
2582
2598
2614

2567
2583
2599
2615

2568
2584
2600
2616

2628
2644
2660
2676

2629
2645
2661
2677

2630
2646
2662
2678

2631
2647
2663
2679

2632
2648
2664
2680

2691
2707
2723
2739

2692
2708
2724
2740

2693
2709
2725
2741

2694
2710
2726
2742

2695
2711
2727
2743

2754
2770
2786
2802

2755
2771
2787
2803

2756
2772
2788
2804

2757
2773
2789
2805

2758
2774
2790
2806

2817
2833
2849
2865

2818
2834
2850
2866

2819
2835
3851
2867

2820
2836
2852
2868

2821
2837
2853
2869

2880
2896
2912
2928

2881
2897
2913
2929

2882
2898
2914
2930

2883
2899
2915
2931

2884
2900
2916
2932

B80
B90
BAO
B80

2944
2960
2976
2992

2945
2961
2977
2993

2946
2962
2978
2994

2947
2963
2979
2995

BCO
BOO
BEO
BFO

3008
3024
3040
3056

3009
3025
3041
3057

3010
3026
3042
3058

COO
Cl0
C20
C30

3072
3088
3104
3120

3073
3089
3105
3121

C40
C50
C60
C70

3136
3152
3168
3184

C80
C90
CAO
CBO
CCO
COO
CEO
CFO

9

A

B

C

0

E

F

2569 2570 2571
2585 2586 2587
2601 2602 2603
2617 2618 2619

2572
2588
2604
2620

2573
2589
2605
2621

2574
2590
2606
2622

2575
2591
2607
2623

2633
2649
2665
2681

2634
2650
2666
2682

2635
2651
2667
2683

2636
2652
2668
2684

2637
2653
2669
2685

2638
2654
2670
2686

2639
2655
2671
2687

2696
2712
2728
2744

2697
2713
2729
2745

2698
2714
2730
2746

2699
2715
2731
2747

2700
2716
2732
2748

2701
2717
2733
2749

2702
2718
2734
2750

2703
2719
2735
2751

2759
2775
2791
2807

2760
2776
2792
2808

4761
2777
2793
2808

2762
2778
2794
2810

2763
2779
2795
2811

2764
2780
2796
2812

2765
2781
2797
2813

2766
2782
2798
2814

2767
2783
2799
2815

2822
2838
2854
2870

2823
2839
2855
2871

2824
2840
2856
2872

2825 2826 2827
2841 2842 2843
2857 2858 2859
2873 2874 2875

2828
2844
2860
2876

2829
2845
2861
2877

2830
2846
2862
2878

2831
2847
2863
2879

2885
2901
2917
2933

2866
2902
2918
2934

2887
2903
2919
2935

2888
2904
2920
2936

2889
2905
2921
2937

2890
2906
2922
2938

2891
2907
2923
2939

2892
2908
2924
2940

2893
2909
2925
2941

2894
2910
2926
2942

2895
2911
2927
2943

2948
2964
2980
2996

2949
2965
2981
2997

2950
2966
2982
2998

2951
2967
2983
2999

2952
2968
2984
3000

2953 2954
2969 2970
2985 2986
3001 3002

2955
2971
2987
3003

2956
2972
2988
3004

2957
2973
2989
3005

2958
2974
2990
3006

2959
2975
2991
3007

3011
3027
3043
3059

3012
3028
3044
3060

3013
3029
3045
3061

3014
3030
3046
3062

3015
3031
3047
3063

3016
3032
3048
3064

3017
3033
3049
3065

3018
3034
3050
3066

3019
3035
3051
3067

3020
3036
3052
,
3068

3021
3037
3053
3069

3022
3038
3054
3070

3023
3039
3055
3071

3074
3090
3106
3122

3075
3091
3107
3123

3076
3092
3108
3124

3077
3093
3109
3125

3078
3094
3110
3126

3079
3095
3111
3127

3080
3096
3112
3128

3081
3097
3113
3129

3082
3098
3114
3130

3083
3099
3115
3131

3084
3100
3116
3132

3085
3101
3117
3133

3086
3102
3118
3134

3087
3103
3119
3135

3137
3153
3169
3185

3138
3154
3170
3186

3139
3155
3171
3187

3140
3156
3172
3188

3141
3157
3173
3189

3142
3158
3174
3190

3143
3159
3175
3191

3144
3160
3176
3192

3145
3161
3177
3193

3146
3162
3178
3194

3147
3163
3179
3·195

3148
3164
3180
3196

3149
3165
3181
3197

3150
3166
3182
3198

3151
3167
3183
3199

3200
3216
3232
3248

3201
3217
3233
3249

3202
3218
3234
3250

3203
3219
3235
3251

3204
3220
3236
3252

3205
3221
3237
3253

3206
3222
3238
3254

3207
3223
3239
3255

3208
3224
3240
3256

3209
3225
3241
3257

3210
3226
3242
3258

3211
3227
3243
3259

3212
3228
3244
3260

3213
3229
3245
3261

3214
3230
3246
3262

3215
3231
3247
3263

3264
3280
3296
3312

3265
3281
3297
3313

3266
3282
3298
3314

3267
3283
3299
3315

3268
3284
3300
3316

3269
3285
3301
3317

3270
3286
3302
3318

3271
3287
3303
3319

3272
3288
3304
3320

3273
3289
3305
3321

3274
3290
3306
3322

3275
3291
3307
3323

3276
3292
3308
3324

3277
3293
3309
3325

3278
3294
3310
3326

3279
3295
3311
3327

L

HEXADECIMAL·DECIMAL INTEGER CONVERSION (Cont'd)

3
3331
3347
3363
3379

4

5

6

7

8

9

A

B

C

0

E

F

000
010
020
030

0
3328
3344
3360
3376

3332
3348
3364
3380

3333
3349
3365
3381

3334
3350
3366
3382

3335
3351
3367
3383

3336
3352
3368
3384

3337
3353
3369
3385

3338
3354
3370
3386

3339
3355
3371
3387

3340
3356
3372
3388

3341
3357
3373
3389

3342
3358
3374
3390

3343
3359
3375
3391

040
050
060
070

3392 3393 3394 3395
3408 3409 3410 3411
3424 3425 3426 3427
3440 3441 3442 3443

3396
3412
3428
3444

3397 3398 3399
3413 3414 3415
3429 3430 3431
3445 3446 3447

3400 3401
3416 3417
3432 3433
3448 3449

3402 3403
3418 3419
3434 3435
3450 3451

3404
3420
3436
3452

3405 3406 3407
3421 3422 3423
3437 3438 3439
3453 3454 3455

080
090
OAO
OBO

3456
3472
3488
3504

3457
3473
3489
3505

3458
3474
3490
3506

3459
3475
3491
3507

3460
3476
3492
3508

3461
3477
3493
3509

3462
3478
3494
3510

3463
3479
3495
3511

3464
3480
3496
3512

3465
3481
3497
3513

3466
3482
3498
3514

3467
3483
3499
3515

3468
3484
3500
3516

3469
3485
3501
3517

3470
3486
3502
3518

3471
3487
3503
3519

OCO
CCO
OEO
OFO

3520
3536
3552
3568

3521
3537
3553
3569

3522
3538
3554
3570

3523
3539
3555
3571

3524
3540
3556
3572

3525
3541
3557
3573

3526
3542
3558
3574

3527
3543
3559
3575

3528
3544
3560
3576

3529
3545
3561
3577

3530
3546
3562
3578

3531
3547
3563
3579

3532
3548
3564
3580

3533
3549
3565
3581

3534
3550
3566
3582

3535
3551
3567
3583

EOO
El0
E20
E30

3584
3600
3616
3632

3585
3601
3617
3633

3586 3587
3602 3603
3618 3619
3634 3635

3588
3604
3620
3636

3589
3605
3621
3637

3590
3606
3622
3638

3591
3607
3623
3639

3592
3608
3624
3640

3593
3609
3625
3641

3594
3610
3626
3642

3595
3611
3627
3643

3596
3612
3628
3644

3597 3598 3599
3613 3614 3615
3629 3630 3631
3645 3646 3647

E40
E50
E60
E70

3648
3664
3680
3696

3649
3665
3681
3697

3650 3651
3666 3667
3682 3683
3698 3699

3652
3668
3684
3700

3653
3669
3685
3701

3654
3670
3686
3702

3655
3671
3687
3703

3656
3672
3688
3704

3657
3673
3689
3705

3658
3674
3690
3706

3659
3675
3691
3707

3660
3676
3692
3708

3661
3677
3693
3709

3662
3678
3694
3710

3663
3679
3695
3711

E80
E90
EAO
EBO

3712
3728
3744
3760

3713
3729
3745
3761

3714
3730
3746
3762

3715
3731
3747
3763

3716
3732
3748
3764

3717
3733
3749
3765

3718
3734
3750
3766

3719
3735
3751
3767

3720
3736
3752
3768

3721
3737
3753
3769

3722
3738
3754
3770

3723
3739
3755
3771

3724
3740
3756
3772

3725
3741
3757
3773

3726
3742
3758
3774

3727
3743
3759
3775

ECO
EOO
EEO
EFO

3776
3792
3808
3824

3777
3793
3809
3825

3778
3794
3810
3826

3779
3795
3811
3827

3780
3796
3812
3828

3781
3797
3813
3829

3782
3798
3814
3830

3783
3799
3815
3831

3784
3800
3816
3832

3785
3801
3817
3833

3786
3802
3818
3834

3787
3803
3819
3835

3788
3804
3820
3836

3789
3805
3821
3837

3790
3806
3822
3838

3791
3807
3823
3839

FOO
FlO
F20
F30

3840 3841
3856 3857
3872 3873
3888 3889

3842
3858
3874
3890

3843
3859
3875
3891

3844
3860
3876
3892

3845
3861
3877
3893

3846
3862
3878
3894

3847
3863
3879
3895

3848
3864
3880
3896

3849
3865
3881
3897

3850
3866
3882
3898

3851
3867
3883
3899

3852
3868
3884
3900

3853
3869
3885
3901

3854
3870
3886
3902

3855
3871
3887
3903

F40
F50
F60
F70

3904
3920
3936
3952

3906 3907
3922 3923
3938 3939
3954 3955

3908
3924
3940
3956

3909
3925
3941
3957

3910
3926
3942
3958

3911
3927
3943
3959

3912
3928
3944
3960

3913
3929
3945
3961

3914
3930
3946
3962

3915
3931
3947
3963

3916
3932
3948
3964

3917
3933
3949
3965

3918
3934
3950
3966

3919
3935
3951
3967

F80
F90
FAO
FBO

3968 3969 3970
3984 3985 3986
4000 4001 4002
4016 4017 4018

3971
3987
4003
4019

3972
3988
4004
4020

3973
3989
4005
4021

3974
3990
4006
4022

3975
3991
4007
4023

3976 3977 3978
3992 3993 3994
4008 4009 4010
4024 4025 4026

3979
3995
4011
4027

3980
3996
4012
4028

3981
3997
4013
4029

3982
3998
4014
4030

3983
3999
4015
4031

FCO
FOO
FEO
FFO

4032
4048
4064
4080

4034
4050
4066
4082

4035
4051
4067
4083

4036
4052
4068
4084

4037 4038 4039
4053 4054 4055
4069 4070 4071
4085 4086 4087

4040 4041 4042
4056 4057 4058
4072 4073 4074
4088 4089 4090

4043
4059
4075
4091

4044
4060
4076
4092

4045
4061
4077
4093

4046
4062
4078
4094

4047
4063
4079
4095

1
3329
3345
3361
3377

3905
3921
3937
3953

4033
4049
4065
4081

2
3330
3346
3362
3378

Li

INTEL CORPORATION, 3065 Bowers Ave., Santa Clara, California 95051 (408) 246-7501

© 1975 Printed in U.S.A. MCS-307a-0275/1K



---

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