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int:eL
Intel Corporation is a leading supplier of microcomputer components,
modules and systems. When Intel first introduced the microprocessor in 1971,
it created the era of the microcomputer. Today, Intel architectures are considered
world standards. Intel products are used in a wide variety of applications including,
embedded systems such as automobiles, avionics systems and telecommunications
equipment, and as the CPU in personal computers, network servers and
supercomputers. Others bring enhanced capabilities to systems and networks.
Intel's mission is to deliver quality products through leading-edge technology.

MULTIMEDIA AND
SUPERCOMPUTING

PROCESSORS

1992

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your. , local
sales. office. to obtain the latest specifications
before placing your order.
..
.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
376, Above, ActionMedia, BITBUS, Code Builder, DeskWare, Digital
Studio, DVI, EtherExpress, ETOX, FaxBACK, Grand Challenge, i, i287,
i386, i387, i486, i487, i750, i860, i960, ICE, iLBX, Inboard, Intel, Intel287,
Intel386, Intel387, Intel486, Inte1487, intel inside., Intellec, iPSC, iRMX,
iSBC, iSBX, iWARP, LAN Print, LANSelect, LAN Shell, LANSight,
LANSpace, LANSpool, MAPNET, Matched, MCS, Media Mail, NetPort,
NetSentry, OpenNET,PR0750, ProSolver, READY-LAN, Reference Point,
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Computer Inside., TokenExpress, Visual Edge, and WYPIWYF.
MDS is an ordering code only and is not used as a product name or trademark. MDS is a registered trademark
of Mohawk Data Sciences Corporation.
CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its
FASTPATH trademark or products.
Additional copies' of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
@INTEL CORPORATION 1991

intaL
INTEL SERVICE
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Intel Service is a complete support program that provides Intel customers with hardware support, software
support, customer training, and consulting services. For detailed information conta~t your local sales offices.
Service and support are major factors in determining the success of a product or program. For Intel this
support includes an international service organization and a breadth of service programs to meet a variety of
customer needs. As you might expect, Intel service is extensive. It can start with On-Site Installation and
Maintenance for Intel and non-Intel systems and peripherals, Repair Services for Intel OEM Modules and
Platforms, Network Operating System support for Novell NetWare and Banyan VINES software, Custom
Integration Services for Intel Platforms, Customer Training, and System Engineering Consulting Services. Intel
maintains service locations worldwide. So wherever you're using Intel technology, our professional staff is
within close reach.

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Engineers throughout the world. Once installed, Intel is dedicated to keeping them running at maximum
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REPAIR SERVICES FOR INTEL OEM MODULES AND PLATFORMS
Intel offers customers of its OEM Modules and Platforms a comprehensive set of repair services that reduce
the costs of system warranty, maintenance, and ownership. Repair services include module or system testing
and repair, module exchange, and spare part sales.

NETWORK OPERATING SYSTEM SUPPORT
An Intel software support contract for Novell NetWare or Banyan VINES software means unlimited access to
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Intel Custom System Integration Services enable resellers to order completely integrated systems assembled
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int:eL
DATA SHEET DESIGNATIONS
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Contains information on products in full production. *

III

"Specifications within these data sheets are subject· to change without notice:'Verify with your local Intel sales
office that you have the latest data sheet before finalizing a design.

i750™ Microprocessor Family

i860™ Microprocessor Family

i960™ Microprocessor Family

Memories and Peripherals

Development Support Tools

Table of Contents
Alphanumeric Index .........' ......... ~ ................................... .

x

i750TM MICROPROCESSOR FAMILY
Chapter 1
i750™ PROCESSOR DATA SHEETS
82750DB Display Processor ...............................................'.
82750PB Pixel Processor ................................................. .

1-1
1-57

i860™ MICROPROCESSOR FAMILY
Chapter 2
i860TM PROCESSOR DATA SHEETS AND APPLICATION NOTES
i860 XP Microprocessor ............................. :...................... .
i860 XR 64-Bit Microprocessor ............. " .............................. .
82495XP Cache Controller/82490XP Cache RAM ............................ .
AP-434 Using i860 Microprocessor Graphics Instructions for 3-D Rendering ..... .
AP-435 Fast Fourier Transforms on the i860 Microprocessor. ....... , .......... .
AP-452 Designing a Memory Bus Controller for the 82495/82490 Cache ........ .

2-1
2-164
2-243
2-378
2-393
2-447

i960™ MICROPROCESSOR FAMILY
Chapter 3
i960TM PROCESSOR PRODUCT OVERVIEWS AND DATA SHEETS
80960SA/80960SB Embedded 32-Bit Processors with 16-Bit Burst Data Bus ..... .
i960 KA/ KB Processor Product Overview ................................... .
80960KA Embedded 32-Bit Processor ......................... ; ............ .
80960KB Embedded 32-Bit Processor with Integrated Floating-Point Unit ........ .
80960CA Product Overview ................................................ .
80960CA-33, -25, -16, 32-Bit High Performance Embedded Processor .......... .
i960™ MC Processor Product Overview ..................................... .
80960MC Embedded 32-Bit Microprocessor with Integrated Floating-Point Unit and
Memory Management Unit ............................................... .
M82965 Fault Tolerant Bus Extension Unit .................................. .

3-1
3-29
3-34
3-81
3-128
3-166
3-233
3-238
3-276

MEMORIES AND PERIPHERALS
Chapter 4
DATA SHEETS
85C960 1-Micron CHMOS 80960 K-Series Bus Control microPLD .............. .
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM .............. .
27960KX Burst Access 1M (128K x 8) CHMOS EPROM ....................... .
82596CA High-Performance 32-Bit Local Area Network Coprocessor ........... .

4-1
4-19
4-40
4-59

DEVELOPMENT SUPPORT TOOLS
Chapter 5
i960 Family of Software Debuggers ......................................... .
EXV960MC Execution Vehicle ............................................. .
80960SA/SB Development Support ........................................ .
ICE-960SB and ICE-960KB In-Circuit Emulators .............................. .
ICE-960MC In-Circuit Emulator ............................................. .
QT960 Evaluation and Prototyping Board ................................•....
DB960CADIC In-Circuit Debugger .......................................... .
Intel Development Tools Software Services .................................. .
iRMK 960 Real-Time Kernel ............................................... .
EV80960CA Evaluation Board ............................................. .
i960 SA/SB Evaluation Board .............................................. .

ix

5-1
5-6
5-8
5-15
5-25
5-33
5-36 .
5-41
5-43
5-49
5-52

Alphanume.ric Index
27960CX Pipelined Burst Access 1M (128Kx 8) CHMOS EPROM. , ............... , . . . .
27960KX Burst Access 1M (128K x 8) CHMOS EPROM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
80960CA Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . .. . . . . . . . ..
80960CA-33, -25, -16, 32-Bit High Performance Embedded Processor ... , . . . . . . . . . . . . ..
80960KA Embedded 32-Bit Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . .
80960KB Embedded 32-Bit Processor with Integrated Floating-Point Unit. . . . . . . . . . . . . . .
80960MC Embedded 32-Bit Microprocessor with Integrated Floating-Point Unit and
Memory Management Unit .......................... , .. ; ...... , . . . . . . . . . . . ... . . ..
80960SAl80960SB Embedded 32-Bit Processors with 16-Bit Burst Data Bus............
80960SAlSB Development Support ................. , ..................... , . . . . . . ..
82495XP Cache Controller 182490XP Cache RAM .. : . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . ..
82596CA High-Performance 32-Bit Local Area Network Coprocessor ..... , ... : . . . . . . . . .
82750DBDispiay Processor .... ~ ...... , . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
82750PB Pixel Processor ... , ..... ~ . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . . . . .
85C960 1-Micron CHMOS 80960 K-Series BusControlmicroPLD ................. .....
AP-434 Using i860 Microprocessor Graphics Instructions for 3-0 Rendering . . . . . . . . . . . ..
AP-435 Fast Fourier Transforms on the i860 Microprocessor ..................... . . . ..
AP-452 Designing a Memory Bus Controller for the 82495/82490 Cache. . . .. . . . . . . . . . ..
DB960CADIC In-Circuit Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EV80960CA Evaluation Board ..•...... , .......................... ; ........ , .... ; .. •
EXV960MC Execution Vehicle ....... '.: .................... ;.......... .......... .....
i860 XP Microprocessor. ................." ....... ; ..... '..•.. :, . ... . . . . . . . . . . . . . . . .
i860 XR 64-Bit Microprocessor ....................... ;............................
i960 Family of Software Debuggers '" .. , ............• '. .. .. . .•. .. . . .... . . . . . . .. . . . . .
i960 KAlKB Processor Product Overview ............................ ; ....... , . . . . ..
i960™ MC Processor· Product Overview.: ................... ; ................ , .: . . ... ..
i960 SA/SB Evaluation Board .......................................................
ICE-960MC In-Circuit Emulator .... , ..... " .. :' .. , ................. ; . . •. . . . . . . . . . .. ..
ICE-960SB and ICE-960KB In-Circuit Emulators. . . . . . . . . . . . . .. . .. . . . . . .. . . . . . . .. . . . . .
lritel Development Tools Software Services ........•..... ' ....... ;. . ... . . . . . . . . . . . . . .
iRMK 960 Real-Time Kernel........ ... .................•..........................
M82965 Fault Tolerant Bus Extension Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OT960 Evaluation and Prototyping Board ................ . . . . . . . . . . . . . . . .. . . . . . . . . . .

x

4-19
. 4-40
3-128
3-166
3-34
3-81
3-238
3-1
5-8
2-243
4-59
1-1
1-57
4-1
2-378
2-393
2-447
5-36
5-49
5-6
2-1
2-164
5-1
3-29
3-233
5-52
5-25
5-15
5-41
5-43
3-276
5-33

i750™ Microprocessor Family

1

8275008
DISPLAY PROCESSOR
•

Programmable Video Timing
- 28 MHz and 45MHz Operating Frequency
- Pixel/Line Address Range to 4096
- Fully Programmable Sync,
Equalization, and Serration
Components
- Fully Programmabl~ Blanking and
Active Display Start and Stop Times
- Genlocking Capability

•

Flexible Display Characteristics
- 8-, Pseudo 16-, 16-, and 32-BitlPixel
Modes '
- Selectable Pixel Widths of 1.0, 1.5,
2.0, 2.5, through 14 Periods of the
Input Frequency
- Support Popular Display Resolutions:
VGA, XGA, NTSC, PAL, and SECAM
- On-Chip Triple DAC for Analog RGB/
YUV Output'

- Mix Graphics and Video Images on a
Pixel by Pixel Basis
- Real Time Expansion of the Reduced
Sample Density Video Color
Components (U, V) to Full Resolution
- Three Independently Addressable
Color Palettes
- Programmable 2X Horizontal
Interpolation of Y Channel
-16 x 16 x 2-Bit Cursor Map with
Independently Programmable 2X
Expansion Factors in X and Y
Dimensions
- YUV to RGB Color Space Conversion
- 2X Vertical Replication of V, U, and V
Data for Displaying Full Motion Video
on VGA Monitor
- Register and Function Compatible
with the 82750DA

Intel's 8275008 is a custom designed VLSI chip used for processing and displaying video graphic information.
It is register and function compatible with the 827500A,
Reset inputs allow the 827500B to be genlocked to an external sync source. By programming internal control
registers, this sync can be modified to accommodate a wide variety of scanning frequencies. A large selection
of bits/pixel; pixels/line, and pixel widths are programmable, allowing a wide latitude in trading·off image
quality vs update rate and VRAM requirements.
The 827500B can operate in a'digitizing mode, wherein it generates timing and control signals to the 82750P8
and VRAM, but does not output display information. Besides digitizer support signals and video synchroniza·
tion, the 827500B outputs digital and analog RGB or YUV information and an8-bit digital word of alpha data.
This alpha channel data may be used to obtain a fractional mix of 827500B outputs with another video source.

VRAM

r,

Video

MI ••

=~7·1+~~w...J

Serial Shift
Register

Video Input

240855-.1

8275008 Subsystem Diagram

Intel Corporation assumes no responsibility for the use of any circuitry other than cirCUitry embodied in an Intel product. No other circuit patent
licenses are implied, Information contained herein supersedes previously published specifications on these devices from Intel.
February 1991
© INTEL CORPORATION, 1991
1-1
Order Number: 240855-003

8275008 Display Processor
CONTENTS

CONTENTS

PAGE

1.08275008 PIN DESCRIPTION
Pinout ...........•........................ 1-4
Quick Pin Reference ..................... 1-8

PAGE

4.0 PROGRAMMING THE 8275008
Overview ...............................
Pipeline Delay through the 82750DB .....
Programming Considerations .........
Cursor Registers ......... ~ ... . . . . .. ..
Display Timing Registers .............
VBUSCode Registers ................
Color Registers ......................
Control Registers ....................
Color Map Registers ......... ,.......
8275008 Register Summary ............

2.0 ARCHITECTURE
Overview ............................... 1-11
Sync Generation and Timing ............ 1-11
VBUS Control ........................... 1-14
VB US Code Description .............. 1-16
Pixel Processing Path ................... 1-19
VU Interpolation ......................... 1-19
Colormap Lookup Table (CLUT)
Operation . . . . . . . . . . . . .. . . . . • . . . . . . . . .. 1-20
8-BitiPixel Graphics Mode ........... 1-21
8-BitiPixel Video Mode ................ 1-21
8-BitiPixel Mixed Mode .............. 1-21
Pseudo 16-BitiPixel Graphics Mode .. 1-21
Ps.eudo 16-Bit/Pixel Video Mode ..... 1-21
Pseudo 16-BitiPixelMixed Mode ..... 1-22
16-BitiPixel Graphics Mode .......... 1-22
16-BitlPixei Video Mode ............... 1-22
16-BitiPixel Mixed Mode ............. 1-22
32-BitiPixel Graphics Mode .......... 1-22
32-BitiPixel Video Mode ............. 1-22
32-BitiPixel Mixed Mode ............. 1-22
Y Interpolator ........................... 1-23
Cursor ........................... ; ...... 1-23
YUV to RGB Converter ................. , 1-25
Output Equalization ............... ; ..... 1-26
Digital to Analog. Converters ............. 1-27

5.0. ELECTRICAL DATA
D.C. Characteristics .....................
A. C. Characteristics .....................
Digital to Analog Converter Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . ..
Output Delay and Rise Time versus Load
Capacitance ..........................

1-33
1-33
1-34
1-34
1-35

1-37
1-38
1-38
1-42
1-43

1-44
1-45
1-50
1-52

6.0 MECHANICAL DATA
Packaging Outlines and Dimensions ..... 1-53
Package Thermal Specifications .......... 1-56

FIGURES
Figure 1-1 82750DB Pinout .............. 1-4
Figure 1-2 82750DB Functional Signal
Groupings .................... 1-7
Figure 2-1 82750DB Unit Level
Diagram .................... 1-12
Figure 2-2 Horizontal Programming
Parameters ................. 1-13
Figure 2-3 Vertical Programming
Parameters ................. 1-13
Figure 2-4 82750PB/82750DB
Communication ............. 1-14
Figure 2-5 82750DB 1X Shift Clock
Operation ................... 1-15
Figure 2-6 82750DB 1;2X Shift Clock
Operation ................... 1-15
Figure 2-7 82750DB 1;3X Shift Clock
Operation ................... 1-15
Figure 2-8 . Mask Operation on CLUT
Address .. ;................. 1-20

3.0 HARDWARE INTERFACE
82750DB Reset Operations .............. 1-28
InputiOutput Transformation ............ 1-28
Genlocking on the 82750DB ............. 1-29
Digitizing Images with the 82750DB ...... 1-30

1-2

CONTENTS
Figure 2-9
Figure 3-1
Figure 3-2
Figure 3-3'
Figure 4-1
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 5-12
Figure 5-13
,

Figure 5-14

Figure 6-1

Figure 6-2

Figure 6-3

Figure 6-4

Figure 6-5

CONTENTS

PAGE
Divide by 2.5 Pixel Clock .... 1-27
Horizontal and Vertical Reset
Timing ..... " ............... 1-30
Digitizing Example .......... 1-31
Digitizing Example with Line
Replicate ....... " " ........ 1-32
Programming the Video Sync
Outputs .................... 1-36
Clock Waveforms ........... 1-47
Output Waveforms ......... 1-47
Input Waveforms ........... 1-47
1X SCLK Mode ............. 1-48
1;2X SCLK Mode ........... 1-48
1;3X SCLK Mode ........... 1-48
PIXCLK Waveforms ........ 1-49
Output Setup and Hold ..... 1-49
TEST ACT # Float Delay .... 1-49
DISDIG to Digital Output
Delay ....................... 1-50
DISDAC to Analog Output
Delay ....................... 1-50
Typical Output
Configuration ............... 1-51
Typical Output Valid Delay
Versus Load Capacitance
under Worst Case
Conditions . . . . . . . . . . . . . . . . .. 1-52
Typical Output Rise Time
Versus Load Capacitance
under Worst Case
Conditions . . . . . . . . . . . . . . . . .. 1-52
Principle Dimensions of the
82750DB in the 132-Lead PQFP
Package .................... 1-53
132-Lead PQFP Mechanical
Package Detail-Typical
Lead ...... , .... ;........... 1-54
132-Lead PQFP Mechanical
Package Detail-Protective
Bumper .................... 1-54
Detailed Dimensions of the
82750DB in the 132-Lead
PQFP Package-Molded
Details , ..... ,.............. 1-54
Detailed Dimensions of the
82750DB in the 132-Lead
PQFP Package-Terminal
Details ..................... 1-55

PAGE

TABLES
Table 1-1 Pin Cross Reference by Pin
Name ...... , ...... ,........... 1-5
Table 1-2 Pin Cross Reference QY
Location . . . . . . . . . . . . . . . . . . . . . .. 1-6
Table 1-3 Pin Descriptions .............. , 1-8
Table 1-4 Input Pins .................... 1-11
Table 2-1 VU Transfer Request
Patterns ............. , .... ,... 1-17
Table 2-2 VU Transfer Request Patterns
with Line Replicate ....... ,.,' 1-17
Table 2-3 CLUT Modes ................. 1-20
Table 2-4 Control Bit Settings and
Resulting Interpolator
Output .......... ,............ 1-23
Table 2-5 Cursor Color Registers ....... 1-24
Table 2-6 Cursor Sizes ................. 1-24
Table 2-7 82750DB Active T-Cycle
Patterns ................ , .. , .. 1-26
Table 2-8 Digital to Analog Converter
Pins .............. , ......... ,' 1-27
Table 3-1 Selecting Alpha Outputs ...... 1-29
Table 4-1 VU Sampling ................. 1-39
Table 4-2 Pixel Times ................... 1-39
Table 4-3 Number of Bits/Pixel ......... 1-40
Table 4-4 Test Mode Select Coding ..... 1-40
Table 4-5 Coding of Transfer Timing
Select Bits ... ,............... 1-42
Table 4-6 82750DB Register Space ..... 1-43
Table 5-1 Absolute Maximum
Requirements ................ 1-44
Table 5-2 D.C. Characteristics .......... 1-44

Table 5-3 A.C., Characteristics at
28 MHz ............ , ........ , 1-45
Table 5-4 A.C. Characteristics at
45 MHz ............................... 1-46
Table 5-5 DAC D.C. Characteristics ....... 1-50
Table 5-6 DAC A.C. Characteristics ........ 1-51
Table 6-1 PQFP Symbol List ...............
Table 6-2 Intel Case Outline Drawings for
PQFP at 0.025 Inch Pitch ......
Table 6-3 Thermal Resistances
(OC/W) .................................
Table 6-4 Maximum TA at Various
Airflows ..............................
1-3

1-53
1-53
1-56
1-56

82750D8

1.0 8275008 PIN DESCRIPTION

Pinout
132 130 128 126 124 122 120 118 118 114 112 110
108 ,108, 104
102 100
131 129 127 125 123 121 119 117 115 113 111 109 107 105
103 101

o

1
2
3
4
,5
8
7
8

9
10
11
12
13
14
15
18
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

0

vee VSS
VSS
vee •

o
o
oo }' _
'0

o
o
o

~oo 0 0 0 0 0 0 0 ~ I~~O 0 0 0 0 0 0 0 0 0 0 0 0
GY vee AVSS vee, VGCS\
Avee
RV VSS
BU
'
"PIXCLK
IREFIN

vee

DRV(5)

OJ

0 0

I 'I
~SS
, VSS vee
ORV[7]
"
VSS 0
DBU[3:D)
DBU[8:4) ALPHA[o)
0

SS VSS

vee

' {0
DBU[7] ALPHA[3:1)
0

DRV(8)

' ' DRV[4:o)

0

'

~O

ALPHA(4) 0
ALPHA(5) 0
vee 0

o
o
o
o

ALPHA(6) 0
~O
ALPHA(7) 0

DGY[7:o)

O~~O

8275008 Pinout
TOP VIEW

o

~

o
o

vss
VSS

BPP[o) 0

D~;~I~) ~
CB 0
vee 0

~

o
o
o
o
o
o
o
o
o
o
o
o

VBUS[3:o) {

DATAIN(31)
VSS DATAlN[18:14) 'DATAlN{21:17)
'I

'

DATAlN[25:22)

~vss-.L,vee

i'CC"

II

DATAIN[3O:26)
I

VSYNC 0
000

70
69

vss 0

- 69

,I,

I

TESTACT#

\,'

. \fCO

89
98
87
88
85
84
83
82
81
80
79
78

~o
RESETB# 0
CSYNCO
,HSYNCO

~~~SRe::ET#~~~:EQIN

ws

90

77
78
75
74
73
72
71

DATAIN[13:o)

vee
~VSS"
vss vccr----l , I

~

0'
SCLK[I) 0
VSS 0
vee 0

99
98
97
98
95
94
93
92
91

'\:

vee 0
_\vcc DISDAC

87

OOOOO~OOOOOOOOOOOOOOOOOOOOOOOOOOO

240855-2

Figure 1-1.8275008 Pinout

1-4

8275008

Table 1-1'. Pin Cross Reference by Pin Name
Location

Pin Name

Location

ACTDIS

Pin Name

87

DATAIN(15)

37

DRV(7)

114

Vee

Pin Name

Location

Pin Name

Location
82

ALPHA[7]

88

DATAIN(14)

36

DRV(6)

118

Vee

91

ALPHA[6]

90

DATAIN(13)

31

DRV[5)

119

Vee

98

ALPHA[5]

92

DATAIN(12)

30

DRV(4)

3

Vee

100

ALPHA[4]

93

DATAIN(11)

29

DRV[3]

4

Vee

104

5

Vee

109

6

Vee

116

ALPHA[3]

95

DATAIN(10)

28

DRV[2]

ALPHA[2]

96

DATAIN(9)

27

DRV(1)

ALPHA[ll

97

DATAIN(8)

26

DRV[O) .

7

Vee

123

ALPHA[O]

102

DATAIN(7)

25

FCO

61

Vee

127

AVCC

128

DATAIN(6)

24

FREQIN

64

Vee

132

AVSS

125

DATAIN[5]

23

GY

VGCS

121

69

DATAIN(4)

22

HRESET#

60

VRESET#

BPP[1]

85

DATAIN(3)

21

HYSNC

71

Vss

1

BPP[O]

86

DATAIN(2)

20

IREFIN

130

Vss

16

BU

122

DATAIN[1)

19

PIXCLK

120

CB

83

DATAIN[O)

18

RESETB#

CSYNC

72

DBU(7)

103

RV

DATAIN[31]

58

DBU[6)

105

SCLK[1]

77

DATAIN[30]

56

DBU(5)

106

SCLK[O)

74

DATAIN[29]

55

DBU(4)

107

TEST#

63

BG

)

129

59

Vss

17

73

Vss

32

126

Vss

34

Vss

39

Vss

48

Vss

57

DATAIN[28]

54

DBU[3)

110

TESTACT#

62

Vss

66

DATAIN[27]

53

DBU[2)

111

VBUS[3]

81

Vss

68

DATAIN[26]

52

DBU(1)

112

VBUS[2)

80

Vss

76

DATAIN[25]

50

DBU[O)

113

VBUS[1]

79

Vss

89

DATAIN[24]

49

DGY(7)

8

VBUS[O]

78

Vss

94

DATAIN[23]

47

DGY(6)

9

Vee

2

Vss

99

DATAIN[22]

46

DGY(5)

10

Vee

33

Vss

101

DATAIN[21]

44

DGY(4)·

11

Vee

35

Vss

108

DATAIN[20]

43

DGY[3]

12

Vee

45

Vss

115

DATAIN(19)

42

DGY[2]

13

Vee

51

Vss

117

DATAIN(18)

41

DGY(1)

14

Vee

65

Vss

124

DATAIN(17)

40

DGY[O)

15

Vee

67

Vss

131

DATAIN[16]

38

DISDAC

66

Vee

75

VSYNC

DISDIG

84

1-5

70

8275008

Table 1·2. Pin Cross Reference by Location
Location

Pin Name

Location

Pin Name

Location

Pin Name

Location

pin Name

1

VSS

34

Vss

67

Vee

100

2

Vee

35

Vee

68

Vss

101

Vss

3

DRV[4]

36

DATAIN[14]

69

BG

102

ALPHA[O]

4

DRV[3]

37

DATAIN[15]

70

VSYNC

103

DBU[7]

5

DRV[2]

38

DATAIN[16]

71

HSYNC

104

Vee

6

DRV[1]

39

Vss

72

CSYNC

105

DBU[6]

7

DRV[O]

40

DATAIN[17]

73

RESETB#

106

DBU[5]

Vee

8

DGY[7]

41

DATAIN[18]

74

SCLK[O]

107

DBU[4]

9

DGY[6]

42

DATAIN[19]

75

Vee

108

Vss

10

DGY[5]

43

DATAIN[20]

76

Vss

109

Vee

11

DGY[4]

44

DATAIN[21]

77

SCLK[1]

110

DBU[3]

12

DGY[3]

45

Vee

78

VBUS[O]

111

DBU[2]

13

DGY[2]

46

DATAIN[22]

79

VBUS[1]

112

DBU[1]

14

DGY[1]

47

DATAIN[23]

80

VBUS[2]

113

DBU[O]

15

DGY[O]

48

Vss

81

VBUS[3]

114

DRV[7]

16

VSS

49

DATAIN[24]

82

Vee

115

Vss

17

VSS

50

DATAIN[25]

83

CB

116

Vee

18

DATAIN[O]

51

Vee

84

DISDIG

117

Vss

19

DATAIN[1]

52

DATAIN[26]

85

BPP[1]

118

DRV[6]

20

DATAIN[2]

53

DATAIN[27]

86

BPP[O]

119

DRV[5]

21

DATAIN[3]

54

DATAIN[28]

87

ACTOIS

120

PIXCLK

22

DATAIN[4]

55

DATAIN[29]

88

ALPHA[7]

121

VGCS

23

DATAIN[5]

56

DATAIN[30]

89

Vss

122

BU

24

DATAIN[6]

57

Vss

90

ALPHA[6]

123

Vee

25

DATAIN[7]

58

DATAIN[31]

91

Vee

124

Vss

26

DATAIN[8]

59

VRESET#

92

ALPHA[5]

125

AVss

27

DATAIN[9]

60

HRESET#

93

ALPHA[4]

126

RV

28

DATAIN[10]

61

FCD

94

Vss

127

Vee

29

DATAIN[11]

62

TESTACT#

95

ALPHA[3]

128

AVee

30

DATAIN[12]

63

TEST#

96

ALPHA[2]

129

GY

31

FREQIN

97

IREFIN

DATAIN[13]

64

ALPHA[1]

130

32

VSS

65

98

Vee

131

33

Vee

66

99

Vss

132

1-6

I Vss
Vee

82750D8

FREQIN

HSYNC
VSYNC

VDP{
INTERFACE

<

CSYNC

VBUS[3:0]

CB

VDP COM. BUS

BG
PIXCLK

--r--VRAM
INTERFACE

<,

SCLK[l :OJ

ACTDIS

SHIFT CONTROL

GY
RV

-IANALOG
OUTPUT

BU

82750D8

ALPHA[7:0]
DATAIN[31 :0]

_J ____ _

DATA BUS

>

DATA OUT
DISPLAY
INTERFACE

DGY[7:OJ

FCO
Y/G

DATA OUT

VIR

DATA OUT

U/B

DATA OUT

DRV[7:OJ

DBY[7:OJ

DISDAC
DISDIG
RESETB#
BPP[1:0]
BITS/PIXEL
TESTACT#

0.,

82750D8 '
FREQIN
_I

SCLK[1:OJ

;_ _

--.-l:

,

TDSCLK

\

~

Y

______________.J,

:~ TACCESS -----.;

,

VRAM
data

\....._----

,

----~;------------~X~-~--------------,

,
~'".---_.~: TSETUP
240655-10

Figure 2·7. 8275008 1j.3X Shift Clock Operation

1-15

intel®

8275008

When reading data from memory during active display, the SCLK[1 :01 outputs operate at a rate required to support the programmed display rate. This
rate is determined from the following equation:
RATE = _ _ _ _ _...:(_#_o_f_bi_ts_I'-pi_xe--'I)'--_ _ __
(32-bitlword)' (# word/fetch) • (#T-cycle/pixel)

where: # bits/pixel and # T-cycles/pixel are user~
programmed
# word/fetch is: 1
The SCLK[1 :01 outputs will be the same frequency
as the input clock in the 1X shift clock mode, and
one half the input clock frequency when using the
1/2X mode. The frequency will be one third in the
input clock when using the 1/3X mode. In the 1/3X
mode the SCLK[1 :0] outputs will be high for one
T-cycle, and low for 2 T-cycles.
VBUS CODE DESCRIPTION

When the 827500B is actively fetching and displaying pixels, VUXFER, BMXIYBMNPX, and REGX are
typically sent over the VBUS. Of the three codes,
REGX has top priority, followed by VUXFER, and
last by BMXIYBMNPX. These commands may be
programmed to occur each active line during the
blanking interval for the line just completed. If a reg. ister transfer has been programmed for an active
line, it takes priority and is executed first. Otherwise,
immediately after the register. transfer, any scheduled VUXFER and BMXIYBMNPX commands are
executed. The programmer has the responsibility for
verifying that the sum of times required by these
commands does not exceed horizontal non-active
display time. The 827500B will commence fetching
pixels at the subsequent start of active display. A
detailed explanation of the different types of VBUS
commands and their corresponding codes follows.

The other parameter the programmer needs to set is
the SCLK delay. This can be found in the Pixel Control Register. It is the number of 827500B clock cycles that the DB will wait before clocking in data, out
of the VRAM, after the initiation of a transfer request
on the VB US outputs.
REGX (0010) This command requests that the
82750PB transfer 827500B register information into
the VRAM shift· registers. Besides the automatic
827500B register transfer that occurs on the second
line (line 2) of each field, the programmer can specify the next horizontal line on which another register
transfer is to take place. The transfers may be
scheduled many times during the field. On the first
transfer, the 82750PB uses the contents of its
827500Bc register as the starting address of the
827500B register data. On each subsequent access, the programmed pitch value in 82750PB's
827500Bc-PITCH register is added to the accumulated start address. The programmer must ensure
that the data is stored in VRAM at the correct address. Since the pitch remains constant, the longest
register load will determine the pitch value.

The VBUS unit performs a vertical checksum on all
the register information. Each bit in the register word
undergoes an exclusive-OR with the corresponding
bit in the previous data word. The· 827500B compares this information with the user generated
checksum, which is the last 32-bit data word read
into the 827500B during a register transfer. If the
values do not match, the 827500B will disable all of
its digital sync and data outputs, enter the reset
state, and send a SHUTDOWN code (827500BSO)
to the 82750PB over the VBUS[3:0] outputs. If the
new checksum is correct, the new register values
will take effect immediately.
VUXFER(0001) This code is used to request VU
data, providing new VU data is required by the
827500B . This command is issued only on vertically
active lines (as programmed in the register, not as
seen on the screen) and possibly the four lines after.
On each line, a row of V and/or U samples are load c
ed into the VU interpolator line stores. The pattern of
requests depends upon the mode in which the VU
interpolator is operating. In the interlaced VU mode,
one line of samples for both the V and U components are fetched during each transfer; in the non-interlaced VU mode, only one line of samples for either the V or U components is fetched. Table 2-1
illustrates the pattern of requests. M is the programmed first vertical active line, and N the last active line. The modes listed have VU transfer requests following the end of horizontal active of the
lines specified, stopping with the last line, N + 4.

Transfer Requests

The following. commands request the 82750PB to
transfer information from the VRAM array into the
VRAM shift register. When multiple requests are programmed for a given line, they are listed in the priority they are sent. When asserting a transfer request,
the programmer must be aware of two other programmed parameters, VBLEN and SCLK delay.
The VBLEN parameter is a user programmed value
whose bits lie in the General Control Register. It is
the length of time, in 827500B T-cycles, that a particular VB US code will be held at the outputs. It is
used to ensure that the asynchronously operating
82750PB chip will have enough time to recognize
and begin operating on an 827500B transfer request.
1-16

nn~

8275008

®

Table 2-1 VU Transfer Request Patterns
Mode

Active
Line

2x Non-Interlaced M
M+ 1
M+4
M+5
N+4
2x Interlaced
(Odd and Even
Fields)

M
M+4
M+5
N+4

Request VU Data
Mode
Fetch 1st Line of V
Fetch 1st Line of U
Fetch 2nd Line of V
Fetch 2nd Line of U
Fetch Last Line of V
Fetch 1st Line of V and U
Fetch 2nd Line of V and U
Fetch 3rd Line of V and U
Fetch Last Line of V and U

4x Non-Interlaced M
M+ 1
M+4
M+5
M+8
N+4

Fetch 1st Line of V
Fetch 1st Line of U
Fetch 2nd Line of V
Fetch 2nd Line of U
Fetch 3rd Line of V
Fetch Last Line of V

4x Interlaced
(Odd and Even
Fields)

Fetch
Fetch
Fetch
Fetch

M
M+4
M+6
N+4

Table 2-2. VU Transfer Request Patterns
with Line Replicate

1st Line of V and U
2nd Line of V and U
3rd Line of V and U
Last Line of V and U

The 82750PB uses another internal pointer to cause
the VRAM to load the desired VU data into its shift
registers (incrementing the pointer by a pitch value).
This command is asserted for a programmable number of T-cycles (m), as specified in the Miscellaneous Control register. Then, the 827500B fetches
them, tying up the 827500BIVRAM interface for
(n + 2) cycles, where n is % the programmable total
number of 8-bit samples of V and U fetched. Note
that one extra word, which may overlap the next
VBUS command, is fetched.
By setting a bit in the Miscellaneous Control register,
it is possible to replicate lines of V and U generated
by the interpolator for the entire field. Since each
line of VU data is displayed twice, the rate that the
VU sample map has to be fetched from VRAM is
reduced by %. Table 2-2 lists the sequence of VU
loads.
In some cases, the VU interpolator may cover only a
portion of the display. In those instances, M in the
above examples would be the first line that VU interpolation is enabled. N would be the last line that VU
interpolation is enabled. Regardless of the state of
the Line Replicate bit, there would be no vertical
pipeline delay between the loading of the first line of
samples and the second line of samples. The first
line of samples would be loaded at M-1, and the
second line at M. This reduces the delay between
switching interpolation modes during a single display.
1-17

Active
Line

Request

2x Non-Interlaced M
M +1
M+4
M+5
M+8
M+9
.N+ 4

Fetch 1st Line of V
Fetch 1sl Line of U
Fetch 2nd Line of V
Fetch 2nd Line of U
Fetch 3rd Line of V .
Fetch 3rd Line of U
Fetch Last Line of V

2x Interlaced
(Odd and Even
Fields)

Fetch 1st Line of V and U
Fetch 2nd Line of V and U
Fetch 3rd Line of V and U
Fetch Last Line of V and U

M
M+4
M+6
N+4

4x Non-Interlaced M
M+ 1
M+ 4
M+5
M +12
M + 13
N+4

Fetch 1st Line of V
Fetch 151 Line of U
Fetch 2nd Line of V
Fetch 2nd Line of U
Fetch 3rd Line of V
Fetch 3rd Line of U
Fetch Last Line of V

4x Interlaced
(Odd and Even
Fields)

Fetch
Fetch
Fetch
Fetch

M
M+ 4
M+8
N+4

.15t Line of V and U
2nd Line of V and U·
3rd Line of V and U
Last Line of V and U

BM){ (0000) This command requests a bitmap.
BMX (0000) is sent after horizontal active stops, beginning on the fifth line after vertical act!ve sta~s,
and continuing until the fifth line after vertical active
stops. (There is a vertical pipeline delay of five lines
through the 827500B, due to internal timing reqUlre.ments.) A line programmed to start at line M, wll
have its first active line displayed at line M + 5.The
82750PB uses an internal pointer to cause the
VRAM shift registers to be loaded with pixel values.
The 827500B subsequently fetches them as required for display. This command is asserted on the
VBUS for the user-programmed number of T-cycles
and must be completed before active display begins.
YBMNP){ (0100) This command performs a·Y bitmap transfer without performing a pitch calc~latio~.
When the line replicate mode is selected by Bit 22 In
the Miscellaneous Control register, this code is asserted every other display line so that the same line
of information can be used twice.

8275008

82750D8SD (1001) This command is the
827500B Shut Down code. During every register
transfer, the 827500B keeps an internal vertical exclusive-or checksum of the register data as it is read
onto the chip. The last word of data that is read
during the register transfer is the user-generated
checksum. If the two checksums match, operation
proceeds as normal. If they do not match, the
827500B enters the reset state and sends this code
to the 82750PB. The 827500B will remain reset until
the reset pin is asserted and negated by the host
processor.

Digitizer Commands
When· in the line replicate mode, and digitizing an
NTSC source. (for example, when genlocking an
NTSC source to a system that uses only a VGA
monitor),. each line of captured data is effectively
output at twice the rate. Since each line need only
be stored once in memory (it is duplicted automatically in the display mode) only one WROIGI code,
followed by aWROIGINP, is sent every other line.
On alternate lines, two WROIGINP are sent and will
select the last address that was written, without incrementing the 82750PB bitmap address pointer.
This is described in detail in Chapter 3.

REFRESH (1010) This command asks the
82750PB to generate up to 15 refresh cycles every
horizontal line. The 827500B transfer cycles have a
higher priority than refresh requests in the 82750PB.
REFRESH will not be asserted if programmed to occur at the same time as a transfer request code.

WRDIGI (0011) This command requests a write of
digitized data. The operation of this command is dependent upon the external hardware and is discussed in the section on genlocking (page 29). If
digitizing is enabled, this command is .asserted on
the VBUS for a programmable number of T-cycles.
The pointer is then incremented by a pitch value.
Since each horizontal line is·stored in a single row of
memory, this pitch value is equal to the horizontal
resolution, in bytes, for non-interlaced bitmaps. For
interlaced bitmaps, the pitch value is equal to twice
the horizontal resolution, in bytes. This allows alternate lines of data to be skipped over in successive
fields.

Video Synchronization Information

The following codes are lJsedto pass the video line
and field information from 827500B to the pixel
processor.
VEVEN (1101) This code indicates the start of an
even (i.e. second) field of a frame. This command is
sent coincident with line one of each even field.
When genlocking to an external source (see pg. 29),
the occurence of a vreset signal during programmed
horizontal active time will cause the 827500B to output a VEVEN code on the VBUS.

WRDIGINP (0111) This command allows access
to digitized data without performing a pitch calculation. WROIGINP (0111) requests that the 82750PB
perform a transfer request at the last calculated address. Note that oniy a memory transfer cycie is performed-the pitch value is. not added to this address. This will always ensure that the digitized data
is written into the last selected memory address, in
case a physical memory boundary has been
crossed. This command is asserted after the WRDIGI transfer has completed.

VODD (1100) This code indicates the start of an
odd (Le. first or only) field of a frame. This command
is always sent immediately after RESETB# is negated, and coincident with line one of the odd field.
Similarly, when genlocking, the occurence of a
vreset signal during any time other than horizontal
active time will cause the 827500B to output a
VOOO code on the VBUS.

Refresh and Control Commands
HUN (1110) This code marks every horizontal line
at a programmable point in the line. HLiN is used by
the 82750PB to increment its horizontal line counter.

The following signals are used to pass refresh requests and control information to the 82750PB.
DFL (1000) The Display Format Load command is
a maskable host processor interrupt that can be programmed to occur at any time during the display.
This is used by the 82750PB to transfer the shadow
register contents into the working register set in the
VRAM interface. This· is useful in supporting splitscreen-type applications, where it is desirable to
change the bitmap pointers at some point before the
end of the display.

1-18

Intel"

8275008

values, it is given the value of the weighted average
of the known values. Values are understood to be
non:negative integers. When the final value is outputted, any fractions are truncated or rounded to the
closest odd integer according to the programmed
value of the interpolation round flag. This process is
iterated until all pixels have assigned color values. If
the number of VU data samples loaded into the
82750DB is not enough to cover the active display
area, then the last data sample will be replicated
horizontally across the active display window.

Pixel Processing Path
This logic accepts the 32-bit word from the input
latch and divides the word into the programmed pixel format. This will result in either four 8-bit pixels,
two 16-bit pixels, one 32-bit pixel, or an 8-bit pixel
with an 8-bit alpha value (pseudo 16-bit mode). The
pixels act as addresses to the color table, or may
bypass the table completely as described below.
Pixel information may be mixed with the output of
the VU interpolator, which outputs interpolated samples derived from a reduced sample bitmap. The
least significant bit of Y or LSB of U can be programmed to act as a switch between using the explicit pixel value of YUV or using the luminance portion of the pixel with the VU portion obtained from
the interpolator. If the value of the LSB of Y (or U,
whichever is selected) is zero, the pixel data is used.
If the LSB of Y (or U) is one, the output of the VU
interpolator is used. Note that if the LSB of Y is used
as the switch flag, the luminance portion of the word
will be only 7 bits wide.

As mentioned previously in the VBUS Control discussion, each line of VU data can be used twice by
setting the Line Replicate bit in the Miscellaneous
Control register. Also, each horizontal VU sample
can be replicated by setting the VU Replicate bit in
the Pixel Control register. This will cause the V and
U pixels generated by the VU interpolator every pixel
time to be used twice. This can result in an effective
8X horizontal expansion, which is useful when horizontal blanking time is at a premium. This bit affects
the horizontal interpolation algorithm only, and will
not affect the line loading sequence for VU during
the active display.

The alpha information is also processed in this
block. The alpha data may come from one of two
sources: it may be explicitly coded in the pixel word,
as is the case in the 32-bitJpixel and pseudo 16-bitl
pixel mode, or it may be obtained by comparing the
Y portion of the pixel with a preprogrammed value
and outputting one pre programmed value if they
match and a different value if they do not match.
This latter capability is known as Alpha Trap.

When interpolation is turned on by the programmer
(by specifying a non-zero number of samples to be
fetched), VU interpolation may nevertheless be disabled for each pixel if the following conditions are
met:
1. Conditional interpolation has been selected by
the programmer,
AND
Either of the two user-programmed conditions:
a. Switching on the LSB of the U bit has been
selected, and the lowest-order bit of the U value fetched for the upper left pixel in the block
has value zero. This allows switching to occur
on a 2 x 2-pixel or 4 x 4-pixel grid, depending
on the expansion mode the user has selected.
The full 8 bits of Y and V are used, but the
usable space of U has been decreased to 7
bits.
b. Switching on the LSB of the Y bit has been
selected, and the low order bit of the Y value
for the current pixel has a value of zero.
2. Display of fetched and interpolated VU values
may also be suppressed by setting the Interpolation Output Enable bit (in the miscellaneous control register) to zero. This will allow VU data to be
loaded into the VU line stores without displaying
VU data. This is useful when a mid-screen transition is made between two interpolation modes,
to compensate for the vertical latency of the interpolation process.

VU Interpolation
When VU interpolation is enabled by the programmer, and when the display is in the active region,
"VU data" will be fetched, as required by the interpolator (by the mechanisms discussed previously in
the section titled "VB US Code Description"). This
data has the format V, V, ... , V, U, U, ... , U where
each V or U is 8 bits, and the bytes are grouped into
32-bit double-words with. earliest in lowest order.
The number, "N", of V bytes and U bytes is the
same; N is programmed to be either 256 samples, or
one of 32 to 192 samples in 32-byte increments.
The first V data and the first U data fetched on the
first line of VU interpolation supplies the VU value for
the first active pixel on that line. All the other VU
pairs. that are fetched define values for the grid of
pixels defined below and to the right of this one by
the VU expansion factor every other or every fourth
horizontally and vertically. Most other VU values are
filled in recursively by interpolation. Wherever there
is a pixel which lies between two pixels with known

1-19

intel®

827500B

For modes that require both, video and graphics to
pass through the color table, the table can be split
into two halves: one half for graphics and the other
for video pixels. By,using theSPLITCLUT bit in the
Miscellaneous Control register in conjunction, with
the LSB of Y or U, the color table address is forced
to either the video table or graphics table automatically. In this case, the masking operation is still used,
but the address is forced to either an even or odd
entry, regardless of the results of the masking operation. ,The flag bit that decides between the, two
types of pixels automatically selects the correct portion of the CLUT table for a single channel. Note the
LSB of Y or U selects the proper half of the CLUT for
that single component. The SPLIT CLUT mode assures the proper half ,of the CLUT is used for all
three components. '

Colormap Lookup Table (CLUT)
Operation
'
The 82750DB contains three 256 x 8-bit color lookup tables. The color maps can be accessed separately, or may act as one large 256 x 24-bit table.
The manner in which the tables are addressed is
determined by the programmed bits/pixel and depends on whether the pixel'is a graphics or video
pixel. Also each Y, U, and V color table address can
be masked. The masks can be used in all the bit!
pixel modes, but are most useful with the 16-bit!pixel mode. In this mode, the mask allows the YUV
values to be mapped to 8-bit values instead of 6-5-5.
Each channel (Y, U, V) has a MASK SET register
and a MASK DATA register that selects the color
lookup address bit to be changed and the new value
of the bit, respectively. A simple mask operation on
one channel is illustated in Figure 2-8.

The color table can be bypassed completely when
displaying either graphics or video, independent of
the programmed bits/pixel. This is programmed by
the user via the VIDEO PASS and GRAPHICS PASS
bits in the Miscellaneous Control register. Table 2-3
summarizes the various modes when using the
CLUT.

The CLUT address mask operation is determined by
a logical equation given by:
Result ~ (mask set and mask data)

I (mask set and data byte)

Each bit of the Result byte is determined individually
by this equation. The Result byte is then further processed in order to produce theCLUT RAM address.

Bit
MASK SET Register (0 x 41)

MASK DATA Register (0 x 42)

Result

Data Byte

240855-11

Figure 2·8. Mask Operation on CLUT Address
Table 2·3 CLUT Modes
Graphics
Pass

Video
Pass

0

LSB Y orU

SPLITCLUT

X
X

0

0

Masked Graphics Data

0

X

Graphics Pixels Bypass CLUT

X
X

0

,1

0

Masked Video Data

1

1

X

Video Pixels Bypass CLUT

0

X

0

1

Even Address Only (Graphics)

X

0

1

1

Odd Address Only (Video)

1.

1

X

X

CLUT Not Used at All

1

1-20

Colormap Address

8275008

When writing to the CLUT, the most significant byte
of the data word corresponds to the address, and
the least significant 24 bits are the YUV data (least
significant to most significant, respectively). An index register is used to allow the 6-bit address to be
mapped to an 8-bit number. (Refer to Chapter 4 for
more information.) By resetting the 827500A Disable bit, it is possible to make the CLUT look like the
reduced entry color lookup table on the 827500A.

tained from the VU interpolator. In this case each
video component is used as an address to its corresponding CLUT as described above. When the
switch flag is set to a zero, the VU values are not
used and the Y value is used as the address to all
color tables. These pixels are treated the same as in
the 8-bit/pixel graphics mode.
In this mode the applications programmer must en,
sure that the proper information has been loaded
into specific areas of the color maps. For example,
all the video pixels will use the odd address values.
By restricting the address used in the graphics and
video mode, two unique maps may coexist in the
tables. One map is used for non-linear transformations on video data, and the other for graphics color
lookup table applications.

The following paragraphs summarizes the possible
bit/pixel modes, using the LSB of Y or U switching
ability and the various graphics and video bypass
modes. Note that there are modes where the LSB of
Y or U are not used to switch between graphics and
video.

As illustrated above, the CLUT can be bypassed by
asserting either or bo!h of the bypass controls.

8-BIT/PI){EL GRAPHICS MODE

This is the graphics-only mode, in which the 8 bits
are used as inputs to all three color tables. This
makes the color maps look like a single, 256 x 24-bit
CLUT and allows 256 unique colors from a palette of
16 million to be available at any given time. If the
Graphics Pass bit is asserted, the CLUT will be bypassed and the 8-bit values of the Y, U, and V channels will be input to each channel of the converter
matrix.

PSEUDO 16-BIT/PIXEL GRAPHICS MODE

In the pseudo 16-bit/pixel graphics mode each
32-bit data word is made up of two, 16-bit pixel
words. The 827500B processes each 16-bit pixel
word, so that the least significant 8 bits correspond
to pixel information, and the most significant 8 bits
are used as alpha information. The 827500B uses
the lower 8 bits as inputs to all three color tables.
This makes the color maps look like a single, 256 x
24-bit color table. If the Graphics Pass bit is asserted, the CLUT will be bypassed and the 8-bit values
of the Y, U, and V channels will be input to each
channel of the converter matrix.

8-BIT/PI){EL VIDEO MODE

When used with subsampled VU information from
the interpolator, the 8 bits are actually a luminance
value. The Y portion addresses the Y color table, V
the V color table, and U the U color table. By using
the color table, a one-to-one mapping exists, allowing non-linear transformations to be applied to the
pixel data to enhance the quality of the reconstructed image. By asserting the VIOEOPASS bit in the
Miscellaneous Control register, the color table can
be bypassed.

PSEUDO 16-BIT/PIXEL VIDEO MODE

When used with subsampled VU information, the
least significant 8 bits of the pixel word are actually a
luminance value. The most significant 8 bits are
used as alpha information. The VU information is
generated by the 827500B interpolator. Each of the
color maps uses the corresponding 8-bit video component as an addess. By asserting the Video Pass
bit in the Miscellaneous Control register, the color
table can be bypassed.

8-BITIPIXEL MIXED MODE

In the 8-bit/pixel mixed mode the LSB of Y or U is
used as a switch flag to change the index to the
color tables. When the switch flag is set to a one,
the Y value corresponds to a luminance value, and
the VU values are the chrominance information ob-

1-21

8275008

ters. When the switch flag indicates the video mode,
the lower 8 bits of the 16-bit pixel word and the VU
values obtained from the interpolar are input to their
respective GLUTs. If the SPLITGLUT mode is seleCted, the LSB of the address is forced to either an odd
or even entry in the three color tables, depending on
whether the data is video or graphics information.

PSEUDO 16-BIT/PIXEL MIXED MODE

In this mode the LSB of Y or U is used as switch flag
to change the index to the color tables. When. the
LSB of Y or U is set to a one, the lower 8-bit value
corresponds to a luminance value, and the V and U
values are the chrominance information. In this
case, each video component of the 827500B is
used as a colormap address as described above.
When the LSB of Y or U is set to zero, the V and U
values from the interpolator are not used, and the Y
value is used as the address to all color tables.

32-BIT/PIXEL GRAPHICS MODE

Eight bits each of Y, U, and V are used as addresses
to each segment of the color table. Since the size of
the addressable color space is not increased, the
advantage of using the color map is for special effects or gamma correction. The most significant 8
bits of the 32-bit data word are used for the alpha
channel data. If the Graphics Pass bit is asserted,
the GLUT will be bypassed and the 8-bit values of
the Y, V, and U will be input to each channel of the
converter matrix.

16-BIT/PIXEL GRAPHICS MODE

The 16-bit pixel word is broken up on the 827500B
to yield 6 bits of Y, and 5 bits each of V and U. The Y
bits are the least significant, and the U bits are the
most significant. These values are then padded with
zeros in the lower order bits, to obtain an 8-bit word
for each pixel component. Each component addresses its respective GLUT. However, the Y channel may access only 64 unique locations, and 5-bit
resolution for VU restricts them to 32 unique locations each. The address range may be extended by
using the colormap mask registers to add 2 bits of
precision in the least significant bits for Y and 3 least
significant bits each for VU channels. This allows the
programmer to access all the entries in the color
table by reprogramming the MASK OATA and MASK
SET registers during the blanking interval.

32-BITIPIXEL VIDEO MODE

The Y channel contains the least significant 8 bits of
the 32-bit data word. The U and V information is
generated by the VU interpolator. The YUV channels
are input to their respective color tables. The size of
the addressable color space is not increased, but
this can be used to take advantage of a non-linear
transformation, which may aid in the decompression
process. The most significant 8 bits of the data word
are used for the alpha channel data.

16-BIT/PIXEL VIDEO MODE
32-BITIPIXEL MIXED MODE

This mode works like the 8-bit/pixel video mode described above, except that the 827500B has processed the information so that the Y channel contains the least significant 8 bits of the 16-bit data
word. The V and U information is generated by the
VU interpolator. If the SPLITGLUT mode is selected,
the LSB of the address is forced to an odd entry in
the three color tables.

When the switch flag is zero, the graphics mode is
selected, and the inputs to the GLUT are the respective 8 bits each of YUV data. These pixel values may
be masked by using the colormap mask data and
mask set registers. When the switch flag indicates
the video mode, the lower 8 bits of the pixel word
and the VU values obtained from the interpolator are
input to their respective GLUTs. If the SPLITGLUT
mode is selected, the LSB of the address is set to
either an odd or even entry in the three color tables,
depending on whether the data is video or graphics
information. The most significant 8 bits of the data
word are used for the alpha channel data.

16-BIT/PIXEL MIXED MODE

When the switch flag is zero, the graphics mode is
selected and the inputs to the GLUT are the respective YUV data in the 6-5-5 format. These pixel values
are extended by using the colormap masking regis-

1-22

intei®

8275008

Table 2-4. Control Bit Settings and
Resulting Interpolator Output

Y Interpolator
The Y Interpolator performs a 2X horizontal linear
interpolation on each line of Y values. When Y interpolation is enabled, the internal pixel clock is twice
the frequency of PIXCLK output.

Viden

Gren

V/G
Switch

0

X

X

X

Interpolator
Bypassed

1

0

0

X

Interpolator
Bypassed

1

0

1

0

Interpolate
Graphics Pixel

1

0

1

1

Do Not
Interpolate
Video Pixel

1

1

0

1

Interpolate
Video Pixel

1

1

0

0

Do Not
Interpolate
Graphics Pixel

1

1

1

X

Interpolate
Both Video
and Graphics
Pixels

827500B
Enable

NOTE:

If Y interpolation is enabled, then only the integer
values of pixel times greater than IX may be
used.

The interpolation may be separately controlled for
both video and graphics pixels, via the Viden and
Gren bits (bits 12 and 11) of the General Control
register. A video pixel is defined as one generated
using VU interpolated values. A graphics pixel does
not use the VU interpolator. The effects of setting
the control bits, the 827500B enable flag, and video/graphics pixel switch (V /G Switch) on the output
of the Interpolator are summarized in Table 2-4.
Because of the asymmetric nature of the internal
pixel clock used on 827500B, the number of T-cycles between successive Y pixels varies depending
on the programmed pixel width. When enabled
there is a pipeline delay through the Y Interpolato;
eql!al to the number of T-cycles between each internal pixel clock.
When the interpolator is bypassed as described
p.bove, there. is a fixed delay through this block. The
V and U data are delayed by one pixel clock to allow
the chroma data to line up with the luminance data.
Other control signals, such as the register address
byte (most significant byte of the 32-bit data word
read from VRAM), the pixel clock, horizontal and
~ertical active displays, composite blanking, and regIster load enable signals are also delayed by one
pixel clock in order to line up with the YUV data. The
programmer must ensure that the active display timIng IS programmed to take the appropriate delay
through the Y Interpolator into account.

1-23

Result

Cursor
Hardware support for a 16 x 16-pixel cursor has
been included on the 827500B. The cursor is capable of providing sharp color transitions, when using
subsampled VU bitmaps. Software intervention· is
minimized, leaving the host with more processing cycles to perform other operations.
Under normal operation, the XYstarting display position of the cursor is loaded into the Cursor Control
register during a 827500B register load. On the display line corresponding to the Y start position, the

8275008

cursor is displayed when the X starting position
(specified in T-cycles) is reached. On the following
15 lines, the cursor will be displayed at this X position everY line, for both interlaced and non~inter­
laced displays.

Each 2-bit cursor pixel will select one of the three
Cursor Color registers or transparency. The 24-bit
output of one of the three color registers (or the actual display pixel data if transparency is used) is input to the YUV converter.

A normal 8275008 register transfer is used to load
the entire 16 x 16 x 2 bits (16 words of 32 bits each)
of cursor data. During this register transfer, the cur- .
sor data is distinguished from normal register data
by placing the Cursor Control register immediately
before the 16 words of cursor data. When the
8275008 loads the Cursor Control register, it will interpret the next sixteen 32-bit words of register data
as the cursor bitmap, and will disable the other registers on the· 8275008 from decoding the address
field of the 32-bit data word. (The checksum of the
8275008 register data is not performed during the
loading of the cursor bitmap data.) The cursor bitmap will be loaded a line at a time, starting at line
zero and continuing in sequential order to line 15.
Each line in the cursor map actually contains sixteen
2-bit cursor pixels, with the two least significant bits
corresponding to the first cursor pixel in that line,
and the two most significant bits corresponding to
the 16th cursor pixel on that line. Each 2-bit pixel
may select one of the three Cursor Color registers or
transparency, according to the format indicated in
Table 2-5.

The cursor bitmap length is 16 lines, and the width is
16 pixels. Although the length of the cursor may be
changed dynamically by chaining register loads to
update the cursor map, the size of the cursor is dependent on the type of display. For interlaced displays, each line of cursor data will appear on the
same line of each field. This results in a cursor of
16 x 32 pixels. For non-interlaced displays, the same
line of cursor information will appear on the same
line every field. The cursor in this case will be 16 x
16 pixels. The size of the cursor may be doubled
independently in the horizontal and/or vertical direction by setting the 2X Horizontal Cursor or 2X Vertical Cursor bit in the General Control register. In this
case, no new data is loaded into the cursor map; the
data is just replicated in the corresponding dimension. Table 2-6 summarizes some of the possible
cursor sizes. Note that by loading the cursor bitmap
with different data at the start of every field, cursor
sizes not listed below may be achieved.

Table 2-5. Cursor Color Registers

Table 2-6. Cursor Sizes
2X Horz.
Cursor

2X Vert.
Cursor

Display

Cursor Size
(in Pixels)

Cursor Pixel

Output

Off

Off

Interlaced

16 x 32

00

Transparency
(CUiSOi Pixel Not Displayed)

On

Off

Interlaced

32 x32

Off

On

Interlaced

16 x 64

01

Cursor Color Register 1

On

On

Interlaced

32x64

10

Cursor Color Register 2

Off

Off

Non-Interlaced

16 x 16

11

Cursor Color Register 3

Three 24-bit color registers that hold the color information for the cursor may be written to at any time
during the register load. The cursor may be loaded
any time during the blanking intervals of the display.
For displays that do not program the cursor during
the display, the cursor bitmap may be loaded during
the vertical blanking interval.

On

Off

Non-Interlaced

32 x 16

Off

On

Non-Interlaced

16 x 32

On

On

Non-Interlaced

32x32

There is a complex relationship between the cursor
and the pixel data especially when using non-integral divisors of the pixel clocks. Since the pixel data
output from the 8275008 pixel path always changes
coincident with the rising edge of the clock, the cursor start position must be positioned on the rising
·edge of any period of the pixel clock. The programmer "must enforce the corresponding restrictions on
the start and stop position of the cursor.

When the T-cycle count equals the value programmed into the X start position of the Cursor Control register, the first cursor pixel can be displayed.

1-24

8275008

When converting the normalized analog values Y',
V', U' to digital y, v. u values, the D.C. offset and
conversion ranges are compatible with the CCIR
601 standard for digital video. The ranges for the
components and the corresponding Digital to Analog equivalent equations are given below:

YUV to RGB Converter
The following equations give the theoretical relationship between analog RGB components, R, G, B, and
analog YUV components, Y, U, V.
Y

~

V

~

U

~

+ 0.586816 G + 0.114363 B

(1 a)

0.701178 R - 0.586816G - 0.114363 B

(1 b)

0.298822 R

R-

Y~

B - Y

~

-0.298822 R - 0.586816 G + 0.885637 B

y

(1 c)

where: 0.0 < G, R, B < 1.0
0.0 < Y < 1.0
-0.701 < V < +0.701
-0.886 < U < -0.886

~

Y - 0.509228 V - 0.194888 U

v

u

B~Y+U

(2c)

where: 0.0 < G, R, B < 1.0
0.0 < Y < 1.0
-0.701 < V < +0.701
- 0.886 < U < + 0.886

V' ~ 0.5V
0.701

v' + 16

(4b)

(240 - 16) U' + 16

(4c)

+ 0.5

(3b)

~~+0.5

(3c)

16

(5a)

112V
+ 128
0.701

(5b)

112U
0.886

(5c)

~

(219)Y

v

~

--

u

~

--

+

+ 128

16 < Y < 235
16 < v, u < 240
By solving equations 5 for Y, U. V, and substituting
into Equation 2, we get the relationship between analog R, G, B and the digital DVI y, u, v data:

(3a)

0.886

~

y

G ~ 0.004566y - 0.003187 v - 0.001541 u + 0.532242

(6a)

R ~ 0.004566 Y + 0.006259 v - 0.874202

(6b)

0.004566 Y + 0.007911 u - 1.085631

(6c)

B
U'

(240 - 16)

where: 0.0 < Y < 1.0
- 0.886 < U < 0.886
-0.701 < V < 0.701

The luminance channel for the YUV inputs is presumed to swing between O.OV and 1.0V. However,
the chroma components do not and need to be normalized to a OV to 1V range. The offset binary encoding used to obtain unsigned numbers must also
be accounted for. This encoding should center the V
and U inputs at the midpoint of the voltage range.
The equations for the normalized version of Y, V,
and U (Y', V', and U' respectively) are:
Y

~

Substituting the normalized analog voltages of
Equation 3 into Equation 4, we obtain the digital version of the input data, used in the DVITM Technology
system:

(2a)
(2b)

~

(4a)

where: 16 < u < 240

R~Y+V

Y'

(235 - 16) Y' + 16

where: 16 < v < 240

Solving for G, R, B, we can obtain the inverse relationship:
G

~

where: 16 < Y < 235

~

where: 0.0 < R. G, B < 1.0
16 < Y < 235
16 < v, u < 240

where: 0.0 < Y', V' U' < 1.0
0.0 . 255 or
< 0 due to excursions in the inputs) are clipped to
255 or O.

transitions fall alternately on the active and inactive
phase of the input frequency, while the internal pixel
clock transitions always occur on the active phase.
Also .note that PIXCLK does not have a 50% duty
cycle.

= y + 1.370705 v - 191.45029

(7b)

The equalizing logiC derives a clock that has a period equal to,the programmed pixel rate, providing an
edge to sample the output information. This allows
the Digital to Analpg Converter to directly sample
the output of the pixel data path before performing
the analog conversion.

b = y + 1.732446 u - 237.75314

(7c)

Table 2-7. 8275008 Active T-Cycle Patterns

9 = Y - 0.698001 v - 0.337633 u + 116.56116
r

(7a)

where: 16 < y.< 235
16

o<

< v,

Pixel Time
(T-Cycles)

u < 240

g, r, b < 255

1
1.5

By substitution of Equation 5 into Equation 1, and by
converting G, A, and 8 to digital values, we can obtain the inverse relationship of Equation 7:

2

Pattern Of Internal
Pixel Clock
Always On
1 On/1 On/1. Off
- 1 On/1 Off

2.5

1 On/1 Off/1 On/2 Off

3

1 On/2 Off

y = +0.298822r + 0.586816g + 0.114363b + 16

(8a)

u = -0.172486r - 0.338721 g+ 0.511206b +128

(8b)

3.5

1 On/20ff/1 On/3 Off

ipv

(8c)

4

1 On/3 Off

=

+0:511545 r - 0.428112g - 0.083434 b+ 128'

where: 16 < y

< 235

16 < v, u< 240

o<

g, r, b < 255

Output Equalization
The units on the 8275008 process the pixel information at the operating frequency of the chip: If the
output pixel rate is not equal to the maximum frequency, the units have null states during which processing is suspended. This type of operation is nec,essary on the 8275008 because of the large
. amount of pipelining. Table 2-7 gives the pattern of
T-cycles on the 8275008 during which processing is
active, according to the programming shown in Table 4-2.
'

4.5

1 On/3 Offl1 On/4 Off

5

1 On/4 Off

5.5

1 On/40ff/1 On/5 Off

6

,1 On/5 Off

6.5

1 On/5 Off/1 On/6 Off

7

1 On/6 Off

7.5

1 On/6 Offl1 On/7 Off

8

10n17 Off

8.5

1 Onl7 Offl1 On/8 Off

9

1 On/8 Off

9.5

1 On/8 Off/1 On/9 Off

10
The pixel information must be. output at a rate that js
some sub-multiple of the operating frequency. The
divisor is programmed by the user, and may be from
1 to 12 times slower than the period of FAEQIN, in
increments of %. Divisors of 13 and 14 are also programmable. Because non-integral divisors are used,
it is necessary for the 82750DB to output different
information on both phases of FAEQIN. This is illustrated in Figure 2-9, which uses a 2.5 divisor for the
clock. Notice that the pixel clock output (PIXCLK)

, 10.5

1-26

"

1 On/9 Off
1 On/9 Off/1 On/10 Off

11

1 On/10 Off

11.5

1 On/10 Off/1 On/11 Off

12

1 On/11 Off

13

1 On/12 Off

14

1 On/13 Off

8275008

FREQIN
I
I
I

I

Internal
Pixel.
Clock

Y

\'-----r--'/

I
I

\'--------'/

I
I

:
PIXCLK
I

I
I

I

~: 1/2T-cyclo + td

240855-12

Figure 2-9 Divide by 2.5 Pixel Clocl(

Digital to Analog Converters
The Digital to Analog Converters (DACs) take three
channels of video information output from the pixel
data path, converting it from B-bit digital values to
analog voltage levels typically between OV and 1V.
The conversion is monotonic, and a pixel clock is
used to derive a two-phase clock internal to the
DAC. The data is sampled from the output of either
the pixel path, or the YUV to RGB matrix on the
rising edge of the internal active phase of this clock..
The DISDAC input pin can be asserted to disable the
analog outputs· and place· them into a high-impedance state.

where: Cext is the external capacitance applied and
Cout is the intrinsic capacitance of an analog output.
For high performance the objective would be to
minimize Rext and Cext. The voltage Voutfs can be
determined by any combination of Ifs and Rext, but
must not exceed 1.5V. In addition Ifs must not exceed 22 mA. The analog outputs must go through
an external buffer to drive doubly-terminated 75Q
coax line.
Table 2-B lists pins Which are used to configurethe
triple DAC.
Table 2-8. Digital To Analog Converter Pins

The analog outputs of the triple DAC are referenced
to an external current source, which must be connected to the IREFIN pin. All the analog outputs are
scaled by this current reference. The value of the
analog output full scale is as follows:

Description

Signal

IREFIN

Analog Current Reference. Must Be
Decoupled to AVCC.

VGCS

Internal Voltage Reference. Must
Be Decoupled to AVCC.

AVcc

Analog Power

where: Iref is the magnitude of the reference
current.

AVss

Analog Ground

GY, RV, BU

Analog Pixel Outputs

The output voltage generated at full scale is:

DISDIG

Disable Digital Outputs

.DISDAC

Disable Analog Outputs

Ifs = Iref • 255
18.5

Vfs = lis' Rext

NOTE:

Rext is the load resistance value.

-

A typical output load for the analog outputs (RV, BU,
GY) is 75Q. The speed of the DAC analog output
rise and fall times is determined by the time constant:
.
Rext • (Cext

+

Cout)

1-27

The digital video outpvts must be disabled by
setting DISDIG high whenever the analog outputs are used. Otherwise the A.G. and D.C. characteristics of the DAG are not guaranteed.

intei·

8275008

the beginning of a horizontal line and at the beginning of the first field sometimes referred to as line 1
of field 1. There will not be a horizontal sync pulse
on the first line after reset, but HSYNC will be generated on every line thereafter. All horizontal and vertical programming parameters as well as scheduling
of any transfer requests and control information to
be sent on the VBUS must be set up by the user
during the first register load. Included in the control
information are parameters for the 82750PB to refresh the VRAM. Refresh must occur on every line.
This requires that the line rate of the 827500B must
be at least 4 kHz to guarantee that enough refresh
cycles are generated. Additional register transfers
(up to one per line) may be programmed to occur on
any line during the field. As a result of this transfer
display characteristics and programming parameters
may be changed.

3.0 HARDWARE INTERFACE

8275008 Reset Operation
Upon power-up, the 827500B is in an indeterminate
state and must be reset. The RESETB# signal asserted by the host processor is sampled on the rising edge of FREOIN. The 827500B will enter the
reset state a maximum of four cycles after
RESETB# is sampled. The 827500B will request
the 82750PB to generate VRAM refresh cycles by
asserting a REFRESH code on the VB US for 16 Tcycles. This code is repeated every 256 T-cycles,
until RESETB# is negated.
NOTE:

The RESET8# input is an edge-triggered input.
After power-up, the host processor must set the
RESET8# input low for a minimum of ten T-cycles in order to reset the 82150D8. The host
must then set the RESETB# input high to start
normal operation.

After the first· field, automatic register transfers will
occur on the second line of each subsequent field.
Note that all register transfers will occur at 1/3 of
the operating frequency of the 827500B, unless the
1X or 1/2X SCLK mode has been programmed by
the user.

When the RESETB# input is released, a Start of
Vertical Field command (VOOO) is sent for 16 T-cycles to the 82750PB via the VBUS. This code is immediately followed by a Register Transfer Request
command (REGX) that is held for 256 T-cycles. This
256 T-cycle wait assures that the 82750PB has ample .time to honor the 827500B register transfer request. The register data is then read into the
827500B from the serial port of the VRAMs at a rate
that is equal to Va of the operating frequency. If the
register transfer does not terminate after 256 T-cycles, the 827500B will automatically stop the trans.fer, send an 827500BSO code to the a2750PB, and
re-enter the reset state.

Throughout the reset process, the states of all outputs become valid at various times. Specifically, after being held low for at least 10 T-cycles,
RESETB # must transition to a high state in order
to initiate normal operation. By the time RESETB #
reaches this low to high transition, the states of
SCLK[1:0j, VBUS[3:0], HSYNC, VSYNC, CSYNC,
and FCOare valid. 10 T-cycles following
RESETS # 's transition from iow to high, the states of
BG, CB, ACTOIS, PIXCLK, OGY[7:0j, ORV[7:0], and
OBU[7:0] become valid. ALPHA[7:0j and BPP[1:0j
signals reach a valid state 10 T-cycles following the
completion of the first register load following reset.

Ouring this register transfer, and on all subsequent
register transfers (programmed or automatic), the
827500B performs a vertical checksum on the register data. The last 32-bit word read in during a register transfer is the user-generated checksum of that
register data. If the 827500B-generated checksum
error does not match the user-generated checksum,
the 827500B sends a SHUTOOWN code to the
82750PB via the VBUS, and will automatically re-enter the reset state. The 827500B will remain in the
reset state until the RESETB# input is toggled by
the hostprocessor. Any VRAfyI requests or control
signals programmed to occur during this time will be
ignored.

Input/Output Transformation
In general, the control outputs, including the sync
signals, are delayed by pipelining effects from their
corresponding inputs. If the output sync signals are
taken as the time base, the first pixel in a line is
actually fetched by an SCLK that is up to 19 T-cycles
before its corresponding PIXCLK. Some later pixels
may be delayed by an additional number of T-cycles,
depending upon bits/pixels, pixel timing, and wheth~
er Y interpolation is enabled.
Outside of the active display region and before the
blanking output is asserted, border pixels are output.
Where the blanking region has been entered and the
display is not active, U1e output is the value contained in the Blanking Color register.

Normal programmed operations start after the first
successful register load. Frame timing will start at

1-28

Intel,

8275008

Pixel handling in the active region is defined by three
parameters:

Genlocking on the 8275006

1. The bits/pixel parameter.

The genlocking algorithm on the 8275008 uses horizontal and vertical resets, HRESET #
and
VRESET #, obtained from an external device. When
the Genlock bit in the Miscellaneous Control register
is off, the 8275008 will ignore all signals present on
it's HRESET # and VRESET # inputs. The 8275008
will resync itself when the programmed end of line
count is received. This allows the user to turn off
genlock without having to worry about the state of
the input video.

2. Whether VU interpolation is in effect or not.
3. If the 8275008 Enable bit has been selected.
VU interpolation is in effect for a given pixel if:
1. The VU interpolator is turned on (VU sample load
set to non-zero load value),
AND
2. VU interpolation display is permitted (VU interpolation display operations bit equals 1),
AND
3. One of the two following conditions is met:
a. Either the interpolation is unconditional,
OR
b. The controlling Y or the controlling U sample
for this pixel has a least significant bit of 1.
The value of the alpha output may come from one of
the following three sources:
1. It may be explicitly coded into the pixel data (32bit/pixel and pseudo 16-bit/pixel with Alpha
modes only).
2. It may be output from one of two programmable
registers, AlphaO and Alpha1.

3. Ouring the portion of the display when the border
is active, the 8 most significant bits of the 80rder
Alpha register may be output.
'
Table 3-1 illustrates how the Alpha outputs are selected;
Table 3·1. Selecting Alpha Outputs
Alpha
Enable

Alpha
Trap Select

0

X

AlphaO Register

1

0

AlphaO Register
(8,16 bpp)

1

0

MS 8yte of Pixel
(32, Pseudo 16 bpp)

1

1

Trap Match = 0,
AlphaO Register

1

1

Trap Match = 1,
Alpha1 Register

Alpha Output

1-29

When the Genlock bit is set to one, the 8275008 will,
use the external resets to reset its internal horizontal
and vertical sync counters. In this case, the width of
the active line is determined by the HRESET # signal, and the length of the field is governed by
VRESET #. The programmed values for these registers will be ignored. As shown in Figure 3-1,
when asserted VRESET # and HRESET # are effected just after the third falling edge of FREOIN.
VRESET # has no effect on the 8275008 if the first
half of the first line of an odd field or the second (and
only) half of the first line of an even field is already in
progress. HRESET # has no effect on the 8275008
if itoccur$ during the programmed first half of the
line. The user may decrease the effect of jitter by
reducing the "window" during which the vertical reset signal is supposed to occur. This can be done by
scheduling a register load to occur after the vertical
active display time has ended, thereby decreasing
the programmable horizontal active window to a size
acceptable for the video source. When VRESET# is
received during this reduced, programmed horizontal active window, the 82750D8 is reset to an
even vertical field. When VRESET# occurs at any
other time in the horizontal scan line, the 8275008
is set to ari odd field.

int'et

8275008

FREQIN

I

HRESET# \ \ . . _ _ _ _ _ _ _ _ _ _---J

~l

HSYNC

~

/

VRESET#,\\.._ _ _ _ _'-jl'/-'I_ _ _ _--'

IF
VSYNC

240855-13

Fjgure 3~1; Horizontal, and Vertical Reset Timing

Digitizing Images with the 8275008 ,',
Digitizing is enabled by setting theDigitizej::nablebit
in the Miscellaneous Control register. Note that en~
abling the digitize mode does not aytomatically enable genlocking. The Genlock bit m'ust be set separately, if it is required. When digitizing, the .827500B
is used to shift digitized data .into the VRAM shift
registers, an9 then transfer Jhis data into the VRAM
array.
The 82750DB also provides an external "digitizer
window" signal, FCD. This signal defines the vertical
active region that the digi~izer enabled. Typically, the'
user sets up the display parameters to reflect the
"window" of the display to be digitized. The horizon~
tal and vertical active window size can be selected
by programming the Active Start and Stop registers.
FCD is derived from the Vertical Start and Stop registers, and is used to enable the digitizer to drive the
VRAM bus. During the programmed vertical blanking
interval the FCD signal will be negated, and therefore, the digitizer is prohibited from driving the VRAM
bus. This will allow data to be read from the VRAM
serial data bus during the automatic register transfer
that is performed at the start of the field. Note that it
will still be possible to program the 82750DB to digitize during the vertical blanking interval, in order, for
example, to capture time codes from a VCR.

Wh~~ capturing and di~~laying NTSC data ,during
the horizontal blanking interval of the first display
line,. a WRDIGINP command is sent on the VB US to
the 82750PB. (Refer to Figure 3-2.) Recall that there
is a 5-line vertical pipeline delay through the
82750DB. If the first display line is programmed to
be n, the first display line will occur at n + 5. Similarly, if the last line is programmed to be m, then the
last display will, be line m + 5. The WRDIGINP
VB US code causes a, dummy, write transfer cycle
that" places the VRAMs in the write mode. The
827~OPB then sets the bitmap pointers to the first
line's address (LO). This code is immediately followed by another WRDIGINP command that causes
the 82750PB to perform a write transfer cycle at the
L'O address. Since no digitized data has been read
.in, invalid data is loaded into row LO of the VRAM
array.
During the aCtive display of the first display line, the
,82750DB provides shift clocks at the programmed
pixel rate. The digitized data is shifted into the
VRAMs while the user-programmed horizontal active
window, is active. During the horizontal blanking interval of the hext line, the 82750DB sends a WRDIGI
code to the 82750PB, thereby transferring the LO
data from the shift register to the VRAM array at the
LO address. The 82750PB performs a pitch calculation, pointing it to the L 1 row. After the WRDIGI

8275008

WRDIGINP

WRDIGINP

t t

WRDtGINP Place VRAUS in wr ite mode
Sel 82750PB po;nler 10 LO
WRQIGINP Transfer (]orboge to LO address

(Seled LO)

Iinen+4 l J
WRDtGI Transfer lO doto to LO address

reo Asserted

/t

WRDIGI

WRDIGINP

WROIGI

WRDIGINP

t t

Digitized Dolo LO

Set 82750PB pointer to II
WRDIGINP Transfer LO to II address
(Selecl LI)

Iinen+S l J

t t

DiqitilCd Dolo L1

WROIGI Transfer L1 dolo to 1I address
Set 82750PB pointer to L2

WRDtGINP Transfer 11 10 l2 address

(Soled L2)

linen+6 l J

WRDlGI

I

Losl Line Ot Dolo

ul .t

WROIGINP

t

WROIGllronsfer Lf doto to If address
Set 82750PB pointer to Lf+ 1
WRDIGINP Transfer U 10 If+1 address
(Seled Lt+ 1)

Iinem+slJ

reo

./t

Negoled

Iinem+6lJ
240855-14

Figure 3-2. Digitizing Example

The vertical sync pulses are buffered, so the start of
the field transfer request can be honored immediately after the previous transfer request is finished.

transfer has finished, the 82750DB issues a
WDIGINP command to the 82750PB that performs a
write transfer cycle at L1 address. This will write the
LO data into the L1 address. The next line the L1 row
will be written over with L1 data. This same procedure continues for the entire active display, until the
last active line is reached (m + 5). A final pair of
WRDIGI and WRDIGINP codes are sent to the
82750PB to load in the last line of data. At the start
of horizontal sync of the next line, the FCD signal
will be negated.

Also, captured NTSC data may be displayed on a
VGA-type monitor. This requires the 82750DB to operate at a VGA frequency (approximately 31.5 kHz),
which ·is tWice that of NTSC. Each line of captured
NTSC data is read into the 82750DB twice. Setting
the line replicate bit makes doubling of memory unnecessary. Figure 3-3 illustrates how the 82750DB
operates in such a mode. The Line Replicate, Digitizer, .and Genlock bits in the Miscellaneous Control
register are assumed to be set to one. During the
HBI of the first display line, a dummy write transfer
cycle. (WRDIGINP) places the VRAMs in the write
mode. The 82750PB then sets the bitmap pointers
to the first line's address (LO). This code is immediately followed by a WDIGINP command, causing the
82750PB to perform a write transfer cycle at the LO
address. Since no digitized data has been read in,
unknown values are loaded into row LO of the VRAM
array.

The purpose of the WDIGINP may not be apparent
at first glance. This signal ensures that the correct
data is written into the last selected VRAM address.
This is necessary when crossing the. physical boundaries of VRAM memory.
When the 82750D8 is genlocked, the digitizing
device must also provide the HRESET # and
VRESET# signals. The device must ensure that
VRESET# is never asserted during the start of the
line. This al.lows a register transfer (which shortens
the active display and is required for digitizing) to
complete before the start of a field register transfer.

1-31

8275008

WRDlGINP

Iinen+4

t t

lJ
reo Asserted

..

linen+5

linen+6

lJ
lJ

WRDlGINP

I

mgilized Data LD

I

Digi[;led 0010 LD

WRDrCINP

WRDIGINP

WROIGI

WROIGINP

WRorC:1NP

WRQIGINP

Itt

Itt

WRDIGI Place VRAUs in write mode
Set 82750PB pointer 10 LO
WRDIGINP Transfer garbage to LO address

(Select LO)

WRDIGINP Transfer
(Select
WRDIGINP Transfer
(Select

LO doto 10 LO address
LO)
lO data to LO address
LO)

WROIGI Transfer LO dota to LO address
Set B2750PB pai"ter to II
WRDIGINP Transfer LO to II address
(Select lI)

WROICINP Tronsfer II dolo to L1 address

linen+7

LJ

I

Oigilized Ooto II

Itt
WROIGI

I

Dig;{;zed Data Ll

linen+8

WROIGINP

Itt

(Select ll)
WRDICINP TrQnsfe~ L t dolo to II address

(Select ll)

WRDIGI Transfer L1 dolo to II address
Set 82750PB pointer to L2
WRDIGINP Transfer l1 to l2 address

(Select l2)

lJ

WRDIGI Transfer Lf do to

WRDIGI

I,o,t lin, Of OQI~ If

WROIGINP

t t

to

Lf address

Set 82750P8 pointer to U+'
(If WRDIGINP then select ro .... If+ I)
WRDIGINP Trar"lsfer Lf to Lf+1 oddress
(Select If. 1)

linem+5lJ

.

FCO Negated

linem+6lJ
240855-15

Figure 3-3. Digitizing Example with Line Replicate

the L1 address are sent. After the fourth line, (which
has the same data as the third line) a write operation
is performed to load L1 data into the L1 address,
and the 82750PB pointer is updated to address L2.
A WRDIGINP code is sent to select the L2 address.
This same procedure continues for the entire active
display, until the last active line is reached (m + 5).
A final pair of WRDIGI and WRDIGINP or two
WRDIGINP codes are set to the 82750PB to load in
the last line of data. At the start of horizontal sync of
the next line, the FCO signal will be negated.

At the end of the first line the 82750DB sends two
WRDIGINP codes to the 82750PB, thereby transfer·
ring the LO data from the shift register to the VRAM
array at the LOaddress. The 82750PB does not per·
form a pitch calculation, so the pointer remains at
the address for LO. After the second display line
(which has the same data as the first line),· a
WRDIGI code is sent to the 82750PB that writes the
LO data to the LO address and updates the bitmap
pointer to L1. The WRDIGINP signal immediately following this selects the L 1 address. After the third
line of data, two WRDIGINP codes that select

1-32

inlet

8275008

4.0 PROGRAMMING THE 827500B

Pipeline Delay through the 827500B
The actual horizontal pipeline delay through the
82750DB is dependent on processing elements
used to generate the output. If Y interpolation is not
used, the pipeline delay is:

Overview
All registers are loaded by the issuance of a REGX
command from the 82750DB to the 82750PB over
the VBUS. This causes the 82750PB to load a sequence of register values into the VRAM serial output registers from an address designated by a
82750DB register pointer. After the request is granted, a new 82750DB register word is read in with
each SCLK. Each 32-bit word consists of a register
address in the high byte and register values in the
rest of the word. The sequence is terminated by a
stop code that corresponds to the address byte being equal to Oxff. A variable number of 32-bit words
can be loaded. During reset, if a stop bit is not found
within 256 T-cycles, the register transfer is terminated, a SHUTDOWN code is asserted on the VBUS,
and the 82750DB returns to the reset state. All
transfer requests are terminated at the start of a new
field. This ensures that non-terminating register
transfers caused by bad register data will be halted.

Horiz. Active Pipeline Delay = 16 cycles +
SCLK Transfer Timing Delay
Here the SCLK Transfer Timing Delay is 1 for 1X, 2
for 1/2X, and 3 for 1/3X.
If Y interpolation is used, the pipeline delay is:
Horiz. Pipeline Delay = 16 cycles +
SCLK Transfer Timing Delay + Integer (Pixel Time)
The integer (Pixel Time) is simply the integer value
of the programmed pixel time. The horizontal pipeline
delay for blanking differs from that of active. When yinterpoloation is on or off, the pipeline delay for horizontal blanking is:
Horiz. Blanking Pipeline Delay = 10 cycles +
SCLK Transfer Timing Delay
The horizontal sync pipeline delay is always equal to
o cycles.

During this register transfer, and on all subsequent
register transfers (programmed or automatic), the
82750DB performs a vertical checksum on the register data. The last 32-bit word read in during a register transfer is the user-generated checksum of that
register data. If the 82750DB-generated checksum
error does not match the user-generated checksum,
the 82750DB sends out a SHUTDOWN code to the
82750PB via the VBUS, and will automatically re-enter the reset state.

Thus all horizontal parameters, (e.g. horizontal
blanking start, active stop) must be programmed to
account for the total horizontal pipeline delay. The
vertical pipeline delay. The vertical blanking and
vertical sync pipeline delay are always equal to 0
lines. All vertical parameters must be programmed
so that this delay is taken into account.

1-33

8275008

PROGRAMMING CONSIDERATIONS

The user must ensure that the 827500B is programmed correctly. Illegal or illogical combinations
of display parameters are not corrected in hardware,
and may cause the 827500B to output erroneous
display or timing information. The following list highlights some basic guidelines to follow when programming the 827500B.
1. The maximum rate that data may be read into the
827500B is determined by the type of memory
used. This in turn effects the maximum rate and
depth of data that can be displayed. If 32 bits of
data can only be read into the 827500B every
two clock cycles, only 16 bits of data may be displayed every clock cycle. The programmer
should match the transfer rate (1 X, 1/2X, or
1/3X) with the memory speed, and the display
pixel rate with the pixel depth and memory bandwidth.
2. Blanking intervals of the display are defined by
the non-active programmed time. During this portion of the display, programmed transfers take
place. If a transfer does not complete before the
start of the active display, it is terminated, and
active display data is shifted into the 827500B at
the programmed rate. During horizontal blanking
intervals, the user should allow enough time for
all programmed register, colormap, and VU data
transfers to complete.
3. When digitizing (capturing) images, no other bitmap transfers (e.g., REGX,VU) should be scheduled to occur during the active portion of the field.
4. Active start and stop times shouid not be programmed to overlap the blanking stop and start
times, taking the pipeline delay through the
827500B into account.
5. Programming the Y interpolation to occur in a
non-integral pixel width will cause the Y channel
to output incorrect data.
CURSOR REGISTERS

The following registers are used to program the
characteristics of the on-chip cursor.

Ox5b

Cursor Position Update Register
31

24
01011011

-

23

12

Vertical Position

11

Ox5a

Cursor Control Register
31

24
01011010

-

23

12

Vertical Position

11

o

Horizontal Position

Horizontal Position in units of T -cycles
Vertical Position in units of full lines

This register also gives the horizontal and vertical
position of the cursor. The cursor will extend 16-pixel
periods, starting at the prescribed horizontal position, for the next 16 lines. (Or 32-pixel periods for 32
lines if the 2X Cursor Mode bits in the General Control register are set to one.) Receipt of this address
also. causes the 827500B to interpret the next sixteen 32-bit words of register data as the 16 x 16 x
2-bit cursor map. This will cause the register address
decoding logic internal to the 827500B to be disabled, and the next 16 words of information will be
loaded into the Cursor table. Each 32-bit word will be
interpreted as a line (16 pixels) of cursor data, with
the two least significant bits corresponding to the
first cursor pixel to be displayed.
Cursor Color 3

Ox59

If the cursor is enabled and the 24 bits of data in this
register are selected, the data will be sent directly to
the YUV conversion matrix during active display. The
bits should be programmed as RGB values when the
YUV to RGB matrix is not being used.
Cursor Color 2

Ox 58

If the cursor is enabled and the 24 bits of data in this
register are selected, the data will be sent directly to
the YUV conversion matrix during active display. The
bits should be programmed as RGB values when the
YUV to RGB matrix is not being used.·
Cursor Color 1

Ox57

o

Horizontal Position

Horizontal Position in units of T-cycles
Vertical Position in units of full lines

This register gives the horizontal and vertical position of the cursor. The cursor will extend 16-pixel
periods, starting at the prescribed horizontal position, for the next 16 lines. (Or 32-pixel periods for 32
lines if the 2X Cursor Mode bits in the General Control register are set to one.
1-34

If the cursor is enabled and the 24 bits of data in ihis
register are selected, the data will be sent directly to
the YUV conversion matrix during active display. The .
bits should be programmed as RGB values when the
YUV to RGB matrix is not being used.

8275008

Each register has two, 12-bit components, listed
with. least significant bits first, followed by the 12
most significant bits. Horizontal timing is measured
in units of T-cycles (periods of the master clock)
from the start of horizontal sync. The register content defines the number of T-cycles that elapse before the event controlled by this register takes place.
The exception to this rule is the base counter, which
specifies the number of T-cycles/half line, Zero is
not an allowable value; use the total number of T-cycles per half line or full line instead. Unused bits
should be zero. Sync signals are RESET to initial
values as specified for each; "start" means to set to
1, and "stop" means to be reset to zero.

12

# of Lines/Field

-

31

11

24
01010101

-

12

23

HSYNC Stop

HSYNC Stop in units of T-cycles
VSYNC Stop in units of half lines

Ox54

31

o

11

o1 0 1 0 1 0 0
-

o

11

VSYNC Stop

Sync Starts

VSYNC Start

HSYNCStart

HSYNC Start in units of T-cycles
VSYNC Start in units of half lines

The Sync Stops and Sync Starts registers are used
in conjunction with one another to specify the start
and stop locations of the horizontal sync, HSYNC,
and vertical sync, VSYNC, output signals. VSYNC
may be programmed to start and stop at any time
during a given field as defined on a half-line interval.
Bits 23 through 12 in the Sync Starts and Sync
Stops registers are used to define the start and stop
times for VSYNC, respectively. Similarly, HSYNC
may be programmed to start and stop at any line
position as defined in units of T -cycles. Bits 11
through 0 in the Sync Starts and Sync Stops registers are used to define the start and stop positions
for HSYNC, respectively.

Ox56

Base Counter
23

Ox55

Sync Stops

DISPLAY TIMING REGISTERS

o

#of T-Cycles/Half Lines

T-cycles/Hal Line in units of T-cycles (Periods of the
master Clock)
Half Lines/Field in units of half lines

As defined by NTSC standards, vertical timing can
be measured from the start of a field in one of two
ways: either in units of half lines, or in units of full
lines. When programmed for an interlaced display,
(Le. an odd number of half lines per field) the st'art of
a field coincides with the start of a line on odd fields
and with the midpoint of a line on even fields. In the
latter case, for an event that is programmed in full
lines, the first half line is ignored, and counting begins with the first full line. With this interpretation, the
register content defines the number of half or full
lines that elapse before the event controlled by this
register takes place. The same may be said for the
horizontal component, which is defined by the number of T-cycles/half line. The hardware does not
look for nor correct illogical combinations of register
settings. The monitor should be protected from damage with external circuitry when debugging is in
progress.

The horizontal component of the Sync Stops register
also affects the composite sync, of CSYNC output. In
this case, the CSYNC output will be the same as the
HSYNC output, except during the vertical sync and
equalization interval. In the latter case, the CSYNC
output is determined by the Serration and Equalization registers.

Ox53

Blanking Stops
23
o 1 0 1 001 1

-

All of the internal timing is derived from comparing
the programmed values with the values of this register. The horizontal base counter is programmed using the least significant 12 bits. In this case the values loaded into this register should be one less than
the desired value. Bits 23 through 12 are used to
specify the number of half lines per field.

1-35

12

Vertical Blank Stop

11

o

Horizontal Blank Stop

HB Stop in units of T-cycles
VB Stop in units of half lines

The Blanking Start and Stop registers control the
composite blanking output (CB). The horizontal
blanking start and stop position, in units of T-cycles,
can be specified to occur at any time during the line.
By the same token, the vertical blanking start and
stop positions can be programmed to occur at any
half-line interval.

827500B

The CB output combines both the horizontal and
vertical· blanking pulses programmed using these
two registers. This information is independent from
the HSYNC, VSYNC, arid CSYNC outputs, so the
user must specify the proper blanking intervals for
the monitor that is being used. If .the programmer
specifies the blanking period to end before the active line starts, or start after the active line has ended, the border color is output. Due to internal pipeline delays on the 827500B, the values should be
one less than desired for VB Start and Stop. For HB
Start and Stop subtract the total horizontal pipeline
delay.

Ox52

Blanking Starts
2~

31

23

01010010

- HB' Start in units of T-cycles
- VB Start in units of half lines

Resets to 1
Resets to 1

Pr~gram values one less .than desired for VB Start
and Stop. FClr horizontal blanking start, load numbers less than the total horizontal pipeline delay.
Pre·Equalization
'Pulses
)a

I...

I

Ox51

Serration Start
31

24

12

23'

o 1 0 1 000 1

Not Used

o

11
Serration Start

- SER Start In units of T-cycles Resets to 0
- (not used)

The vertical component of the CSYNC (composite
sync) signal is ·made up of two types of pulses:
equalization and serration pulses. The window during which the serration pulses are active,is determined by the VSYNC start and stop positions, as
shown in Figure 4-1. When vertical sync (VSYNC) is
active, 'in this' case on line 3, the first serration pulse
is output on the CSYNC signal. This pulse will start
at the T-cycle count specified in Bits 11 to 0 of the
Serration Start register. The pulse will end when the
half-line count specified in the Base Counter register
has been reached. This pulse will be repeated for
every half line that the VSYNC output is programmed to be active, regardless of the position in
the field. iri Figure 4-1, this continues until half line
12, or line 6.

Serration Pulses ,

Start 01 Odd .,eld

,,~Ho"

rizontalEqualization Stop

,

f ',

Vertical Serration Start

vfical Equalization Stop

CSYNC

VSYNC

HSYNC

uneCount

~ ++
++2 ++3 ++4"++5 ++6 ++7'~4 +8 ++9 +.
1

O'

Figure 4-1_ Programming the Video Sync Outputs

1-36

240855-16

8275008

O){50

Equalization Parameters

Active Region Starts

o

1211

o

31

o 1 0 1 0 0 0 0 Vertical Equaliza1ion Stop Horizontal Equalization Stop

-

EOH Stop in units of T-cycles
EOV Stop in units of half lines

01001,110

Resets to 1
Resets to 1

-

During the vertical equalizing period, which starts at
field-beginning, an equalization, pulse is output on
the CSYNC signal at the beginning of each half line,
as shown in Figure 4-1. The width of this equalization pulse is determined by the value in bits 11 to 0
of this register. The half line on which these pulses
are to stop is programmed in bits 23 through 12 of
this register. If VSYNC is programmed to occur during the equalization interval (as it is for NTSC type
displays), the serration pulses are output on the
CSYNC signal.
Active Region Stops
31

2423
01001111

Vertical Active Stop

Horizontal Active Start

Actdis Start in units of T-cycles
Vertical Start in units of full lines

Burst Gate Stop
31

24

o 1 001
-

Ox4d
23

12

11

Vertical BG Stop

10 1

o

Horizontal BG Stop

Horizontal Stop Position in units of T-cycles
Vertical Stop Position in units of full lines

The Burst Gate Horizontal and Vertical Start and
Stop registers allow the user to program a window
into which burst can be added. This is useful when
modulating the outputs of the 827500B.

Olc4f
12 11

Ox4e

Burst Gate Start

Ox4c

o
31

Horizontal Active Stop

24

23

01001100

- Actdis Stop in units of T-cycles
- Vertical Stop in units of full lines

-

The active region window, during which pixels to be
displayed are fetched from VRAM, is defined by the
Active Region Start and Stop registers, The first display line is actually five lines after the line indicated
in the vertical region of the Active Region Start register. The position of the active region on a horizontal
line is determined by the horizontal component of
the Active Region Start register. Pixels will be
fetched, from VRAM at a rate determined by the
number of bits/pixel and pixel widths. In order for the
827500B to operate properly, the horizontal width of
the active region window must be an integral number
of display pixel widths, taking into account the horizontal pipeline delay, Also, the Active Region Start
and Stop must fall within a single line boundary, as
dictated by the Base Counter register. When,the first
pixel actually appears at the output of the 827500B,
the output is a function. of the processing elements
used as discussed above.
'

12

11

Vertical BG Start

o

Horizontal BG Start

Horizontal Start Position in units of T-cycles
Vertical Start Position in units of full lines

VBUS CODE REGIS-rERS
The following group of registers are used by the pro:
gram mer to schedule when VBUS transfer or control
codes are to be sent to the 82750PB by the
827500B.
O){4b

Display Format Load Interrupt
31

2 23
01001011

-

1211

Vertical DFL Position Horizontal DFL Positio

Horizontal Position in units of T-cycles
Vertical Position in units of full lines

This is the programmable XY interrupt, used by the
82750PB to perform a load of the Shadow Copy registers.This interrupt is sent on the VBUS when the
bits 23 to 12 match the current display line position,
and, bits 11 to 0 match the T-cycle count.

When the active region is over, the border color is
output until the programmed blanl<42

CLUT Mask Data Register

Ox5e

Not Used

Ox43

Miscellaneous Control

Ox5f

Not Used

Ox44

General Control

Ox60

Not Used

Ox45

Pixel Control

Ox61

Not Used

Ox46

Blanking Color

Ox62

Not Used

Ox47

Alpha Register

Ox63

Not Used

Ox48

Border Color

Ox64

Not Used

Ox49

Register Transfer

Ox65

Not Used

Ox4a

Line Notification and Timing

Ox66

Ox4b

DFL Load

Ox67

Ox4c

Burst Gate Start

Ox68

Not Used

,

Not Used
Not Used

Ox4d

Burst Gate Stop

Ox69-0x6e

Not Used

Ox4e

Active Region Start

Ox6f

Not Used

Ox4f

Active Region Stop

Ox70

Not Used

Ox 50

Equaliz(ition Parameters

Ox71-0x7f

Not Used

Ox51

Serration Start

Ox80-0xfe

Not Used

Ox52

Blanking Start

Oxff

Stop Code

1-43

82750D6

5.0 ELECTRICAL DATA

Maximum Ratings
Table 5-1 is a stress rating only, and functional operation
at the maximums is not guaranteed. Functional operating conditions are given in the DC and AC Characteristics (Tables 5-2, 5-3, 5-4, and 5-5).

Taible

5~1.

Exposure to the Maximum Ratings may affect device
reliability. Furthermore, aithough the 827500B contains protective circuitry to resist damage from static
electrical .. discharge, always take precautions to
avoid high static voltages or electric fields.'

Absolute Maximum Requlreinents
"Maximum

Condition

Requirement
-65·C to 110·C

Case Temperature under Bias

- '65·C to 11 O·C

Storage Temperature
Voltage on Any Pin with Respect to Ground

':'O.5Vto

Supply Voltage with Respect to Vss

-'0.5V to

Vce +

0.5V

+6.5V

DC Characteristics
Table 5-2. DC Characteristics Vcc = 5V ±10%,TcASE ;':' O°C to 95°C

Symbol

Parameter

Min

Typ

Unit

-0.3

Notes

V1L

Input LOW Voltage

VIH

InputHIGH Voltage

VOL

Output LOW Voltage

"V

IOL

VOH

Output HIGH Voltage

V

IOH

~

VSS<'-"NtA.
1-50

int:eL

8275008

Table 5-6. DAC A.C. Characteristics
Symbol

Parameter

Min

ft4~.)!;

Typ

Unit

Notes

tr, tf

Rise/Fall Time

ns

(Note 1)

ClkF

Clock Feedthrough

dB

(Note 2)

GlEn

Glitch Energy

pV-sec

(Notes 2, 3)

Skew

Output Skew

ns

Xtlk

Crosstalk

pV-sec

(Note 2)

NOTES:
1. Maximum value is for RL = 750 and CL =
2. Assumes an 80 MHz filter on output.
3. Glitch energy generated from the il)!l.
4. DISDIG must be tied high.<;;t
5. Assumes the use of 0.1 IlF capacitor be

% to 90% fuliscale transmission.

n VGCS and AVcc and 0.1 IlF and 10 IlF capacitors between IREFIN and AVcc .

IRE FIN

Ground

VGCS

8275008

Avss

Avec

Ground
f-~~---+---+--- +5V (AveC>

R
To
Monitor

G
8

R, = 750
RL = Load Resistance

C, =0.1
CL

::::

~F

Load Capacitance

tis = 255 * Iref
18.5

Vb = IfII * RL

where:

o (9)lcIA®-8®lo®1&

mm (inch)

DETAIL

J

8.28 (.18S)
8.14 (,885)

.1-.~
S CEG •
1 CEG.
DETAIL L
240855-36

Figure 6-2. 132-Lead PQFP Mechanical Package Detail-Typical Lead

.."~
,..". ",.1

E2

1.32 ('SS2)
1.22 <-0848)
. ~
8.~S (.835) MIN.
2.83 (.888)
1.'3 <'871:0)

----02 ----I
DETAILM

240855-34

mm (inch)

Figure 6~3. 132-Lead PQFP Mechanical Package Detail-Protective Bumper,

240855-33

mm (inch)

Figure 6-4. Detailed Dimensions of the 82750DB In the ·132~Lead PQFP Package-Molded Details

1-54

8275008

'1 11 0 .1.35 (0.925>1

SEE DETAIL L
,-+-.j.j...-

SEE DETAIL J

I - - - D3/E3---i
1------

D4/E4 ----~

~----D/E----~

240855-35

mm (inch)

Figure 6-5. Detailed Dimensions of the 82750D8 in the 132-Lead PQFP Packag&'-Terminal Details

NOTES,
ALL OIt'£NSIONS

»4)

TOLERANCES CONFeR< TO ANSI Yl4.5I1-1'82

rn

OATI..t1 PLANE
LOCATED AT THE I'Q.O PARTING LlN£ AND
COINCIDENT 1IITH TI-£ BOTTOH OF THE LEAD IIt£RE LEAD EXITS PLASTIC BODY
OATI..t1S ~ Ar«l
ga TO BE DETEMIIIN£O MRE CENTER LEADS EXIT
PLASTIC BOOY AT OAT\.I'I I'LANE

rn

CONTROl.LlNO OIP€NSION, INCH
OIP€NSIONS 01, 02, El AND E2 ARE Mt4SUl£O AT THE rQ.D PARTING LINE.
01 AND El 00 NOT INCLi..IJ£ AH ALLOllASl..! rQ.D PROTRUSION OF 1.18 1'91
(.817 IN> PER SIDE. 02 AND E2 00 "ilT INCLlJlE A TOTAL ALL01lAllLE
rQ.O PROTRUSION OF D.18 I9t (.BII7 INI AT I1AXII'U'I PACKAOE SIZE.
PIN 1 IDENTIFIER 18 LOCATED UITHltl

()j£

OF TI-£ niO ZONES 1r«lICATED

240855-37

1-55

·Inlel®
..

8275008

TA

Package Thermal Specifications
The 8275008 is specified for operation when Tc
(the case temperature) is within the range of ooe to
95°. Tc may be measured in any environment to determine whether the 8275008 is within specified operating range. The case temperature should be measured at the center of the top surface.

=

TC - P • fiCA

Typical values for eCA at various airflows are given
in Table 6-3 for the 132-lead PQFP package. When
using the digital outputs, Table 6-4 shows the maximum TA allowable (without exceeding Tel at various
airflows. The power dissipation (P) is calculated by
using the typical supply currents at 5V as shown in
Table 5-2.

T A (the ambient temperature) can' be calculated
from eCA (thermal resistance from case to ambient)
with the following equation:

Similarly, when using the analog outputs, the maximum TA allowed is a function of Ifs. The equation for
calculating the power is given in the following
equation which can then be used in calculating the
maximum TAP = 5V * (lCCNT + (3 * Its + 6))

Table 6-3. ThermanResistances (OCIW)
eCA Versus Airflow-ft/min (m/sec)

Package
132-Lead PQFP

0
(0)

200
(1.01 )

400
(2.02)

600
(3.04)

800
(4.06)

1000
(5.07)

26.0

17.5

14.0

11.5

9.5

8.5

Table 6-4. Maximum T A at Various Airflows

ee)

T A Versus Airflow-ft/min (m/sec)
Package

Frequency
(MHz)

0
(0)

200
(1.01)

400
(2.03)

600
(3.04)

800

1000

(4.06)

(5.07)

132-Lead PQFP

28

71

79

82

84

86

87

45

59

71

75

79

82

83

1-56

82750PB
PIXEL PROCESSOR

•
•
•
•

25 MHz Clock with Single Cycle
Execution
Zero Branch Delay
Wide Instruction Word Processor

II 512 x 48-Bit Instruction RAM

Interpolator
• Pixel
High Performance Memory Interface
II

- 32-Bit Memory Data Bus
- 50 MBytes per Second Maximum
- 25 MBytes per Second with Standard
VRAMs or DRAMs

512 x 16-Bit Data RAM

II 16 General-Purpose Registers

II Two Internal 16-Bit Buses

III 4 Gbyte Linear Address Space

II ALU with Dual-Add-With-Saturation
Mode

III 132-Pin PQFP

II Variable Length Sequence Decoder

II Compatible with the 82750PA

Intel's 82750PB is a 25 MHz wide instruction processor that generates and manipulates pixels. When paired
with its companion chip, the 82750DB, and used to implement a DVI Technology video subsystem, the
82750PB provides real time (30 images/sec) pixel processing, real time video compression, interactive motion
video playback and real time video effects.
Real time pixel manipulations, including 30 images/sec video compression, are supported by the 25 MHz
instruction rate. On-chip instruction RAM provides programmability for execution of a wide range of algorithms
that support motion video decompression, text, and 2D and 3D graphics. Inner loops are optimized with the
integration of sixteen 16-bit quad ported registers, on-chip DRAM, and two loop counters that provide zero
delay two-way branching "free" in any instruction. Two, 16-bit internal buses enable two parallel register
transfers on each 82750PB instruction, contributing to the real time performance of the video processing.
Another feature that adds to the processing power of the 82750PB is the 16-bit ALU, which includes an 8-bit
dual-add-with-saturate operation critical for pixel arithmetic. Other specialized features for pixel processing
include a 2D pixel interpolator for image processing functions and a variable length sequence decoder for
decoding compressed data.
The 827.50PB is implemented using Intel's low-power CHMOS IV Technology and is packaged in a 132-lead
space-saving, plastic quad flat pack (PQFP) package.

Video Output
CSYNC

Video

B!U

Mlxer/
Display

G/Y

Device

VRAM

R/V
ALPHA[7:0]

Seriol Shift

Register

VRESElI
HRESEl#

Video Input
240854-1

82750PB Subsystem Diagram

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
February 1991
© INTEL CORPORATION, 1991
1-57
Order Number: 240854-003

•

iniet

82750PB

82750PB Pixel Processor

CONTENTS

CONTENTS

PAGE

PAGE
VRAM Pointers ...................
1-86
,
Shadow Copy ..................... 1-86
Host Interface ........................ 1-87
Host Register.Access ............. 1-88
Host VRAM Access ............... 1-89
Host External Access ............. 1-89
Host Register Address Mapping ... 1-89
Initializing the 82750PB .............. 1-96
Performance Monitoring .............. '1-97
HostlVRAM Timing Diagrams ........ 1-97

1.0 82750PB PIN DESCRIPTION ....... 1-61

Pinout ................................ 1-61
Quick Pin Reference ................. 1-65

2.0 ARCHITECTURE ...................
Overview .............................
Registers ............................
ALU .................................
Barrel Shifter ...................... , ..
Data RAM ...........................
Loop Counters .......................
Microcode RAM ......................
Horizontal Line Counter ..............
Field.Counter ........................
Input FIFOs ............. : ............
Output FIFOs ........................
Statistical Decoder ....................
Pixel Interpolator .....................
Mode Select .......... ~ . .. . ... .. . ..
Reset .............................
Pairing ............................
Phase .... : .......................
Pipelining .........................
Reserved .........................
Signature Register ...................
Display Format Registers .............

1-68
1-68
1-68
1-69
1-70
1-70
1-70

4.0 MICROCODE INSTRUCTION

1-71

FORMAT ............................ 1-102

1-72

Overview ...........................
.Instruction Sequencing ..............
Instruction Word Field Descriptions ..
NADDR-Next Instruction Address
Field ...........................
CFSEL-Condition Flag Select
Field ............................
ASRC-A Bus Source Select
Field ...........................
ADST-A Bus Destination Select
. Field ...... , ....................
BSRC-B Bus Source Select
Field ...........................

1-72

1-72
1-73
1-74
1-79
1-80
1-80
1-80
1"80
1-80
1-81

BDST-B Bus Destination Select
Field ...........................
CNT-Decrement Loop Counter .
Bit .............................
LIT-Literal Select Bit ............
SHFT-Shift Control Field ........
ALUSS-ALU Source Select Bits .

1-81
1-81

3.0 HARDWARE INTERFACE .......... 1-82

VRAM Interface ......................
VRAM Accesses ..................
FastVRAM Cycles ............,....
VBUS Codes ......................
Priority ............................

1-82
1-83

1-102
1c102
1-102
1-102
1-102
1-103
1-103
1-103
1-103
1-103
1-103
1-104

1-104,
ALUOP-ALU Operation Code
. Field, ..... : .................... 1-104
LC-Loop Counter Select Bit· ..... 1-104

1-84
1-84
1-85

1-58

intel"

82750PB

82750PB Pixel Processor
CONTENTS

CONTENTS

PAGE

PAGE
Figure 5"1. Clock Waveforms ........... 1-112
Figure 5-2. Output Waveforms .......... 1-112

5.0 ELECTRICAL DATA ............... 1-110

D.C. Characteristics .................... 1-110
A.C. Characteristics .................... 1-111
Output Delay and Rise Time Versus Load
Capacitance ......................... 1-113

Figure 5-3. Input Wavef6rms ...........
Figure 5-4. CLKOUTWaveforms .......
Figure 5-5. Typical Output Valid Delay
Versus Load Capacitance
under Worst Case
Conditions ..................
Figure 5-6. Typical Output Rise Time
Versus Load Capacitance
under Worst Case
Conditions ..................
Figure 6-1. Principal Dimensions of the
82750PB in the 132-Lead
PQFP Package .............
Figure 6-2. Detailed Dimensions of the
82750PB in the 132-Lead
PQFP-Molding Details .....

6.0 MECHANICAL DATA .............. 1-114

Packaging Outlines and Dimensions .... 1-114
Package Thermal Specifications ........ 1-119
FIGURES
Figure 1-1. 82750PB Pinout .............
J
'
Figure 1-2. 82750PB Functional Signal
Groupings ...................
Figure 2-1. 82750PB Block Diagram .....
Figure 2-2. Input FIFO Control Register ..
Figure 2-3. Output FIFO Control
Register .....................
Figure 2-4. Statistical Decode CONTROL
Register .....................
Figure 2-5. VRAM Bitstream Decoding
Addresses ...................
Figure 2-6. Pixel Interpolation ............
Figure 2-7. Sequential-2D. Pixel
,
Interpolation .................
, Figure 2-8. Pixel Interpolator Control
Register .....................
Figure 2-9. Pixel Pair Phases ............
Figure 3-1. Access State Diagram .......
Figure 3-2. Cyclic Ordering of FIFOs .....
Figure 3-3. VRAM Addressing ...........
Figure 3-4. VRAM Read and Write
Cycles ................... . . ..
Figure 3-5. VRAM Transfer and Refresh
Cycles .......................
Figure 3-6. Host Register Read and Write
Cycles .... . . . . . . . . . . . . . . . . . ..

1-61
1-64
1-68
1-72

1-112
1-112

1-113

1-113

1-115

i -116

Figure 6-3. Detailed Dimensions of the
82750PB in the 132-Lead
PQFP-Terminal Details .... 1-116
Figure 6-4. 132-Lead PQFP Mechanical
Package Detail-Protective
Bumper ...... " ............. 1-117
Figure 6-5. 132-Lead PQFP Mechanical
Package Detail-Typical
Lead ., ...................... 1-117

1-73

1-77
1-78

1c79
1-79

TABLES
Table 1-1. Pin Cross Reference by Pin
Name ............. '.......... 1-62

1-80
1,-81
1-83

Table 1-2. Pin Cross Reference by
Location ....................
Table 1-3. Pin Descriptions .............
Table 1-4. Output Pins .................
Table 1-5. Input Pins ...................
Table 1-6. Input/Output Pins ...........
Table 2-1. Bit Assignment for cc
Register ....................

1-86
1-86
1-98
1-98
1-99

Table 2-2. ALU Opcodes ...............
Table 2-3. Circular Buffer Register .....
Table 2-4. Sample Code Description
Table .......................
Table 2-5. Decoded Values ............

Figure 3-7. Host External Cycles ........ 1-100
Figure 3-8. Host VRAM Read and Write
Cycles .................... 1-101
Figure4-1. Literal Field Mapping onto a
Bus ......................... 1-104

Table 2-6.

Figure 4-2. 82750PB Instruction, Word
Format ..................... 1-108
1-59

1-63
1-65
1-67
1-67
1-67
1-69
1-69
1-73
1-75
1-75

END Mode Decoded
Values .... , ................. 1-75

82750PB

82750PB Pixel Processor

CONTENTS
Table 2-7.
Table 2-8.

CONTENTS

PAGE
END Flag Decoded Values .. 1-76
Packed 3-Bit Field Decoded
Values ........................ 1-76

VRAM Bitstream Decoded
Values ......................
Table 2-10., Decod(ng Symbols ..........
Table 2-11. Mode Select Operating
Modes ......................
Table 2-12. Pipelining Delay for
Sequential-2D NON-PAIR
Mode ........................
Table 2-13. Signature Values ............

PAGE
Table 3-12. Bit Assignments for
PROCESSOR STATUS
Register .................... 1-93
Table 3-13. 82750PB A Bus
Source/Destination Register
Mapping .................. ,. 1-94
Table 3-14. 82750PB B Bus
Source/Destination Register
Mapping .................... 1-95

Table 2-9.

1-78
1-78
1-80

Table 3-15. VRAM Pointer RAM
Mapping .................... 1-96
Table 4-1. Mirocode Next Instruction
Selection .................. 1-102
Table 4-2. PC Load Example .......... 1-103

1-81
1-81

Table 2-14. Display Registers ........... H2
Table 3-1.
Table 3-2.

VRAM Interface Signals ..... 1-82
82750PB VRAM Access
States ....................... 1-83

Table 3-3.
Table 3-4.

VB US Codes ............... , 1-85
Priority of VRAM
Operations ................. , 1-85

Table 3-5.
Table 3-6.

Host Interface Signals ....... 1-87
Host, VRAM and External
Device Signals. , ........... , 1-87

Table 4-3.
Table 4-4.
Table 4-5.
Table 5-1.

Condition Flag Select Field
Assignments ............... 1-103
SHIFT Control Field
Coding ..................... 1-104
82750PB Source/Destination
Coding ..................... 1-106
Absolute Maximum
Requirements .............. 1-110

Table 5-2.

D.C. Characteristics., ...... 1-110
A.C. Characteristics at
25 MHz .................... 1-111
PQFP Symbol List ...... , ... 1:;14

Table 3-7.

82750PB Host Transaction
States ...................... 1-88

Table 5-3.

Table 3-8.

Host Cycle Types ., ......... 1-88

Table 6-1.

Table 3-9.

Host Address Mapping ...... 1-90

Table 6-2.

Table 3-10. Bit Assignments for
Microcode Processor
CONTROL Register ......... 1-91

Intel Case Outline Drawings
for PQFP at 0.025-lnch
Pitch ....... , ............... 1-115

Table 6-3.

Thermal Resistances

Table 6-4.

Maximum T A at Various
Airflows .................... 1-119

eC/W) ..... , ............... 1-119

Table 3-11. Bit Assignments for
INTERRUPT FLAG
Register .................... 1-92

1-60

82750PB

1.0 82750PB PIN DESCRIPTION
Pinout
131

132

129

'lO

127

'28

125

'26

123

'2'

121

122

119

120

,,~

117

118·

116

11]

",

,11

112

109

liD

107

'DB

10!t

106

103

'04

101

102

'DO

000000000000000000000000000000000
023

o

022
IISS

o IICC

0021
0020

vee
024

vee

D26

025

\ISS

02.

027

030

029

VSSi

031

•

\ISS

vee

All

ClKOUl

A29

AJO

A27

\ICC

A28

\ISS

A25
A26

vec

A23

o

o

A22

A21

o
o
.'9 o
A18
o
IItC
o
A20

0019

o 01B
0017

0016
9

0015

10

OIlSS

11

001.

12

0013

AI6

.3

0012

A'5

14

o

A14

0"

011

.~

0010

16

009

o
o

82750PB Pinout
TOP VIEW

All

o
o

o
o

o
o

.'2 o
o
o

99
98

97
96

95
9'
9)

92
91

go
89

88
87

as
05
84

17

o IISS

18

008

19

007

20

006

2'
22

01lSS

AI!

0

7t

005

07

78

23

00.

AI!

24

003

\ISS

0
0
0

.'0 o
AD

2~

o

26

002

27

Om

M

28

000

M

29
3D

J.
32

Jl

o
o

vee

IISS

AS

\ISS
HINT'

A2

NlClr5l,

H.DY'~
UROY

PM'Al'

~ :" HBUSEN'~
TAN'.'~
HAAIIIi,UAEZ' t,.::;~' T~
o
~
£b
vee b
b
b
I vee bClk'Nb WE' b
I
I
00
0
0
000 0 0
0000000
00
IICC

HR[C, B[2'

\ISS

BEJI

BED'

8Et '

\ISS

\ISS

WUs[J) 7U12:01 I HALEN' _
VCC

l1li[0'

\ISS

YCC

o

o
o
o

o
o

o
o
o
o

0)

B2
81

80

n
78

75
7.

73·
72

71
70

69

88
67

llCC \ISS

240854-2

Figure 1-1. 82750PB Pinout

1-61

82750PB.

Table 1-1. Pin Cross Reference by Pin Name
Pin
Name

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
BEO#
BE1#
BE2#

Location

71
72
73
74
77

78
79
80
81
83
84
85
86
87
88
90
92
93
95
96
97
102
103
105
106
107
110
111
112
113
44
43
42

Pin
Name

Location

Pin
Name

Location

Pin
Name

BE3#
ClKIN
ClKOUT
DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029

41
47
114
.28
27
26
24
23
22
20
19
18
16
15
14
13
12
11
9
8
7
6
5
4
3
130
129
128
126
125
122
121
120

030
031
HAlEN#
HAlT#
HBUSEN#
HINT#
HRAM#
HROY#
HREG#
HREQ#
MROY#
MREQ#
NXTFST#
PMFRZ#
RESET#
RFSH#
TEST#
TRNFR#
VBUS[O]
VBUS[1]
VBUS[2]
VBUS[3]
Vee
Vee
Vee
Vee
Vee .Vee
Vee
Vee
Vee
Vee
Vee

119
118
55
31
36
30
58
38
40
56
60
59
61
70
63
62
69
37
54
53
52
50
2
33
35
45
51
65
67
75
82
91
98

Vee
Vee
Vss
Vee
Vee
Vee
Vee
Vee
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
WE#

1-62

Location

100
104
94
109
116
123
127
132
1
32
34
39
48
57
66
68
76
89
99
101
108
115
117
124
131
10
17

21
25
29
46
64
49

82750PB

Table 1-2. Pin Cross Reference by location
location

1
2
3
4
5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

Pin
Name

location

Pin
Name

VSS
Vee
021
020
019
018
017
016
015
VSS
014
013
012
011
010
09
VSS
08
07
06
VSS
05
04
03
Vss
02
01
DO
VSS
HINT#
HAlT#
VSS
Vee

34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

VSS
Vee
HBUSEN#
TRNFR#
HROY#
VSS
HREG#
BE3#
BE2#
BE1#
BEO#
Vee
VSS
ClKIN
VSS
WE#
VBUS[3]
Vee
VBUS[2]
VBUS[1]
VBUS[O]
HALEN#
HREQ#
VSS
HRAM#
MREQ#
MROY#
NXTFST#
RFSH#
RESET#
VSS
Vee
VSS

location

67
68
69
70
71
72
73
74
75
76
77

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

1-63

Pin
Name

location

Pin
Name

Vee
Vss
TEST#
PMFRZ#
A2
A3
A4
A5
Vee
VSS
A6
A7
A8
A9
A10
Vee
A11
A12
A13
A14
A15
A16
VSS
A17
Vee
A18
A19
VSS
A20
A21
A22
Vee
VSS

100
101
102
103
104
105
106
107·
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

Vee
VSS
A23
A24
Vee
A25
A26
A27
Vss
Vee
A28
A29
A30
A31
CLKOUT
VSS
Vee
VSS
031
030
029
028
027
Vee
VSS
026
025
Vee
024
023
022
VSS
Vee

82750PB

.

AJ31:9)

ADDRESS BUS)

--

eLKIN
MREQ#

RESET#

TRNFR#

CLKOUT

VRAM

..

RFSH#
NXTFST#

INTERFACE

MRDY#

A

--

AJ8:2)

-... SHARED

ADDRESS BUS

82750PB
HREQ#

A

/BYTE ENABLE BUS

HREG#

.K

D[31:D) "-

r

HALT#

-HINT#

PMFRU

INTERFACE

---

DATA BUS

HBUSEN#

IL

VRAM
INTERFACE

HALEN#
HRDY#

VDP

BETWEEN
HOST AND

WE#

HRAM#
HOST
INTERFACE

BE#[3:D)

YBUS[3:0)

"VDP COM_ BUS)

}

VCC
VSS

MICROCODE
SIGNALS

~POWER
jCONNECTIONS

24.0854-3

Figure 1-2. 82750PB Functional Signal Groupings

1-64

intel®

82750PB

Quick Pin Reference
Table 1-3 provides descriptions of 82750PB pins.
Table 1-3. Pin Descriptions
Symbol

Type

Name and Function

ClKIN

I

ClKIN is a 1X ClOCI{ INPUT that provides the fundamental timing for the
82750PB. One cycle of ClKIN is denoted as one T-cycle.

RESET#

I

The 82750PB is reset and initialized by holding this signal active for at least t\3n
T-cycles. Refer to Initializing the 82750PB Section in Chapter 3.

HREQ#

I

The HOST REQUEST signal is a request from the host CPU to perform a read
or write access to either registers on the 82750PB, an external device, or to
VRAM shared by the 82750PB and the host. The type of access that is
requested is determined by the host access definition signals: HREG #,
HRAM#, and WE#.

HREG,#
HRAM#

I

The HOST REGISTER and HOST RAM signals, when validated by HREQ#,
are used to define three host access cycles. HRAM# active indicates the host
is requesting a VRAM read or write cycle. HREG # active indicates that the
host is requesting a 82750PB register read or register write cycle. When both
signals are inactive, a host external cycle is requested.

HBUSEN#

0

HOST BUS ENABLE is asserted by the 82750PB at the start of a host access
to indicate that the 82750PB Address and Data buses (A[31 :2], BE# [3:0], and
D[31 :0]) have been tri-stated. This allows the host to drive the same buses
either for accessing shared VRAM or the 82750PB internal registers.

HAlEN#

I

The HOST ADDRESS LATCH ENABLE signal is used to indicate to the
82750PB that the host has asserted a valid address (A[31:2], BE# [3:0]) and
write enable (WE#).

HRDY#

0

HOST READY is asserted by the 82750PB at the end of a host access to
indicate that the access cycle is ready for data transfer. For a host write cycle,
HRDY # indicates that the 82750PB is ready to accept data from the host. For
a host VRAM write cycle, HRDY # indicates that the VRAM has latched the
data from the host. For a host read cycle, HRDY # indicates that output data
from the 82750PB or VRAM is ready to be latched by the host.

HINT#

0

HOST INTERRUPT: This output is asserted when an interrupt condition is
detected by the 82750PB, and the enable bit in the PROCESSOR CONTROL
register corresponding to that interrupt condition is set to a ONE. HINT # stays
active until the host CPU reads the INTERRUPT STATUS register. If an
interrupt condition that is enabled occurs during the same cycle that the
INTERRUPT STATUS register is being read, HINT# remains active.

D[31 :0]

I/O

A[31 :9]
A[8:2]

I/O

The DATA BUS is used to transfer data between:
1. The 82750PB and VRAM, and
2. The Host CPU and internal 82750PB registers. During host VRAM accesses,
this bus is tri-stated to allow the host to share the same VRAM data bus. During
host accesses to internal 82750PB registers all 32 bits are used for data
transfer.
The ADDRESS BUS is shared between the 82750PB and the host for
addreSSing VRAM. This 30-pin bus addresses 32-bit double words in VRAM.
Byte Enable signals are used to address individual bytes or words within a
double word in VRAM. In addition, the address for host accesses to internal .
82750PB registers are communicated to the 82750PB using the lower seven
pins, A[8:2], and the BE # pins. During host access cycles to either VRAM or
82750PB internal registers, A[31 :2] are tri-stated. For internal register
accesses, as indicated by HREG# being low, the lower seven bits, A[8:21, are
used as the host address input.

ClKOUT

0

0

The CLOCK OUTPUT signal is one of the two internal clocks and is
synchronized with ClKIN. It is always driven and will have a 50% duty cycle.
1-65

82750PB

Symbol

Type

BE#[3:0]

I/O

Table 1-3. Pin Descriptions (Continued)'
Name and Function
The BYTE ENABLE BUS, is shared by the 82750PB and the host for
addressing VRAM down to the byte level. The correspondence between
the four Byte Enable pins and the D[31 :0] pins is: BE # [3]-D[31 :24],
BE# [2]-D[23:16], BE#[1l-D[15:81, and BE#[0],,-D[7:0]. During VRAM
read cycles, the 82750PB enables all four bytes. During write cycles the'
82750PB only enables those bytes that are to be written. Bytes that are
not enabled are not to be altered in VRAM. During host accesses to
82750PB on~chip registers, the BE # [0] pin is used as an input to select
whether the even or odd word is being accessed; the double word
address is provided by the host on the A[8:2] pins. BE # [0] = 0 indicates
that data is transferred on D[15:0]. BE# [0] = 1 indicates that data is
transferred on D[31:16].

MEMORY REQUEST is asserted for the first cycle, T1, of each VRAM

MREQ#

0

TRNFR#,
RFSH#

0

The MEMORY CYCLE DEFINITION SIGNALS: Transfer, Refresh and
Write Enable are asserted at the same time as MREQ #, but stay active
for the entire VRAM cycle. TRNFR # active indicates a VRAM transfer
cycle. RFSH # active indicates a VRAM refresh cycle. If neither TRNFR #
nor RFSH # are active, a VRAM data read or write cycle is requested.

I/O

The WRITE ENABLE pin is used as an output during a 82750PBIVRAM
cycle to drive the WE # signal, which defines the access as a VRAM read
cycle (when inactive) or write cycle (when active). During HostlVRAM
and Host External cycles, the 82750PB tri-states this pin to allow the host
to drive the VRAM write enable signals directly. During Host/register
cycles, this pin is used as an input for the Host Write Enable signal to
determine whether the host is reading or writing the 82750PB register.

NXTFST#

0

The NEXT FAST signal indicates that the following vram cycle can be
performed with a page-mode or bank-interleaved access. This signal is
asserted during the first of a pair of VRAM cycles that is guaranteed to be
within the same VRAM page and in opposite banks-a pair of accesses
to two sequential double wOids in VRAM ai addresses Even Address and
Even Address + 1. In other words, A[2] is a zero for the first cycle and a
one for the second cycle.

MRDY#

I

The MEMORY READY input indicates that the VRAM cycle has
progressed to the point where it is ready to perform the data transfer; For
a VRAM read cycle, the VRAM data can be latche9 by the transition of
. MRDY # to an active state. For a VRAM write cycle, MRDY # indicates
that the data has been latched into the VRAMs.

VBUS[3:0]

I

The VDP COMMUNICATION BUS is used to communicate from the
82750DB to the 82750PB. Codes sent over this bus indicate interrupt
requests, transfer requests, and status information. Since the 82750DB
and 82750PB run asynchronously, the VBUS signals are sampled on the
falling edge of ClKIN and compared with the previous sample. For a
VBUS code to be detected by the 82750PB, it must be valid for two
successive samples.

HAlT#

I

The HALT signal causes the microcode processor on the 82750PB to
halt prior to executing the next instruction. This signal does not halt the
VRAM interface. The Halt signal will allow the design of a hardware
emulator for the 82750PB based on an 82750PB chip.

TEST #

I

The TEST signal is used for test purposes only and must remain high for
normal operation.

cycle.

WE#

1-66

InteL

82750PB

Table 1-3. Pin Descriptions (Continued)
Symbol'

Type

PMFRZ#

0

Name and Function

The PERFORMANCE MONITORING AND FREEZE signal is toggled by
specific microcode instructions and can be used to determine the time
required to execute certain sections of microcode.

+ 5V D.C. supply input.

Vee

I

POWER pins provide the

Vss

I

GROUND pins provide the OV connection to which all inputs and outputs
are referenced.
Table 1-5. Input Pins

Table 1-4. Output Pins
Active
Level

Name

CLKOUT

High

When
Floated

Name

Active
Level

Synchronous/
Asynchronous

Synchronous

Always Driven

CLKIN

High

Reset', Host Cycle

RESET#

Low

Asynchronous

HBUSEN#

Low

Reset'

HREQ#

Low

Asynchronous*

HRDY#

Low

Reset'

HREG#

Low

Synchronous

HINT#

Low

Reset'

HRAM#

Low

Synchronous

A[31:9]

. High

MREQ#

Low

Reset'

MRDY#

Low

Synchronous

TRNFR#,
RFSH#

Low

Reset'

VBUS[3:0]

High

Asynchronous

NXTFST#

Low

Reset'

Low

Reset'

PMFRZ#
"The reset state

IS

HALT#

Low

Synchronous

HALEN#

Low

Asynchronous*

*Can be programmed to accept synchronous Inputs.

caused by RESET # being active low.

Table 1-6. Input/Output Pins
Name

Active Level

When Floated

Synch/Async

D[31:0]

High

Reset', Host Cycle

Synchronous

A[S:2]

High

Reset', Host Cycle

Synchronous

BE#[3:0]

Low

Reset', Host Cycle

Synchronous

WE#

Low

Reset', Host Cycle

Synchronous

"The reset state

IS

caused by RESET # being active low.

All output pins are floated when RESET is active low.

82750PB

2.0 ARCHITECTURE
Overview
The 82750PB includes a wide instruction word
processor that comprises a· number of processing,
storage, and input! output elements. The wide instruction word architecture allows a number of these
elements to operate in parallel. The 82750PB executes one instruction every internal clock cycle or
T-cycle. The various elements are connected via
two 16-bit buses, the A bus and B bus, as shown in
Figure 2-1. During each instruction execution cycle,
data can be transferred from a bus source to a bus
destination element on both buses.

Registers
IrN; N

=

0-15)

There are 16 general-purpose data registers, each
16 bits wide, that are connected to both the A bus
and B bus as both sources and destinations. These
registers are designated rO-r15. All the registers are

functionally identical except rO, which also includes
logic for bit shifting and byte swapping. A register
can source both the A bus and the B bus in the
same cycle. A register cannot be the destination of
both the A bus and the B bus in a single instruction .
. Because the registers are doubly latched, the same
register may be both a source and destination in the
same cycle. Theresult is that the data in the register
prior to the current cycle will be driven on the source
bus, and the data on the destination bus will be
latched into the register at the end of the cycle.
Register rO has additional logic to allow bit shifting
and byte swapping. The value in rO can be. shifted
left or right one bit position per instruction cycle. For
a right shift, the new MSB is equal to the old MSB; in
other words, the value is sign-extended. For left
shifting, the new LSB is equal to zero. RO can not be
shifted and loaded in the same instruction. Byte
sWapping, on the other hand, only occurs whenrO is
being loaded with a value from the A bus or B bus.
Byte swapping causes the most significant byte and
the least significant byte. of the 16-bit value being
loaded into rO to be interchanged. Refer to Chapter
4 for a description of the SHFT microcode field that
controls the shifting and swapping operations in rOo

SEQUENCER
DATA

RAM

~ICROCODE

RAM
MICROCOOE
INSTRUCTION

AlU
0[31:0]

REGISTER
FILE
BARREL
SHIFTER
COUNTERS

..--_ _ _---, A[31 :2]
VRA~

PIXEL
INTERPOLATOR

BE6[3:0]

POINTERS

HOST/VRA~

INTERFACE
240854-4

Figure 2-1. 82750PB Block Diagram

1-68

82750PB

ALU

Table 2-2. ALU Opcodes
Operation
No Operation
pass a
pass b
1's compliment of a

{atu, eel

The ALU performs 16-bit arithmetic and logic operations, and can also be operated as two independent
8-bit ALUs for the Dual-Add-with-Saturate operation.
There are two fields in the microcode instruction that
affect the operation of the ALU: the ALUOP field
specifies the operation to be performed, and the
ALUSS field specifies the source of the two ALU
inputs. Refer to Chapter 4 for further information on
these .fields.

1 's compliment of b

The two ALU operands either come from values
held in the ALU input latches or from "eavesdropping" on the A or S buses. The result of any ALU
operation is latched in the ALU output register, atu.
In a subsequent instruction this result can be transferred to any A or S destination.
The ALU has four condition flag outputs: CarryOut,
Sign, Overflow, and Zero. CarryOut is the carry out
of the most significant bit position. Sign is equal to
the value of the most significant bit of the result.
Overflow is the exclusive-OR of CarryOut and the
Carryln to the most significant bit position of the result. Zero is true (a value of1) if all 16 bits of the
ALU result are equal to zero. CarryOut and Overflow
are defined as equal to zero for all logical operations. For most ALU operations, the state of these
four condition flags are latched when the operation
is complete. There are eight operations (nop, a*, b*,
+), -I, 0*, prof and int) that are exceptions. These
operations are performed without disturbing the
condition state of the previous ALU operation.

Bit
SitO
Sit 1
Sit 2
Sit3
Sit 4
Sit 5
Sit 6
Sit 7
Sit 15:8

Condition
False (This bit of the cc is always read as
a zero.)'
ALU Carry Out
ALU Overflow
ALU Sign
ALU Zero
Loop Counter Zero'
RO LSS'
RO MSS'
RESERVED. The state of these bits is
undefined when read; write as zeros.

&
-&
&-

a+b
a+b+1
a-b

+
++
-

-a + b
2'5 compliment of a
2'5 compliment of b

-+
-a
-b

Interrupt Host
Zero
Pass a, Don't Latch Flags
Pass b, Don't Latch Flags
(NOTa) OR b
.aOR (NOT b)
Dual Sub: with Sat.
Perform. Monitor/Profile

Table 2-1. Bit Assignments for cc Register

a
b
-a
-b

aANDb
(NOTa)ANDb
aAND (NOT b)
aORb
aXORb

Incrementa
Increment b
Decrement a
Decrement b
Dual Add with Sat.
a + b + (Prev. Carry)
a - b - (Prev. Sorrow)
- a + b - (Prev. Sorrow)

Microcode routines can read and write the ALU condition flag register, cc. This can be used to save and
restore the state of these flags. The bit ordering of
the ALU condition flags within cc are given in Table
2-1.A complete list of ALU opcodes is given in Table
2-2.

Mnemonic
nop

1
A

a++
b++
a-b--

+]
+<
-<

-+<
int
0*
a'
b*

-I
1-]
prof

The Dual-Add-with~Saturate operation performs independent 8-bit ADDs on the upper and lower bytes
·of the two ALU operands. The two bytes of the A
operand are treated as unsigned binary numbers
(00:FF16 corresponds to .0:25510). The two bytes of
the S operand are treated as offset binary numbers

'These are read·only values and are not affected by writes to the cc
register.
.
.
.

1-69

82750PB

with an offset of + 128 (OO:FF16 corresponds to
-12810: 12710). The upper and lower byte results
are treated as 9-bit offset binary, including the carry
output of each byte, with a + 128 offset (000:1FF16
corresponds to -12810:38310) and are saturated to
a range of 0-25510. A result that is less than zero is
set equal to zero or 0016 and a result that is greater
than + 255 is set equal to + 255 or FF 16.
In fact, this operation is symmetric. Either the A operand or the 8 operand can be defined as the unsigned binary value, and the other operand will be
treated as the offset signed binary value ..
Dual-subtract-with-saturate is similar to dual-addwith-saturate. It calculates A - 8 + 128 on each
8-bit half of the two 16-bit inputs, and clamps the
results to 0 and 255. This can be viewed as subtracting an offset-binary signed byte (-128 to 127) from
an unsigned byte (0 to 255).

Data RAM
IdramN, 'dramN, + +, - -; N = 1-41

The Data RAM holds 512, 16-bit words that are accessed using four pointers. To access a value in a
particular location, the microcode routine must first
load a pOinter with the address to be accessed, and
then perform a read or write using the same pointer.
In parallel with the data RAM access, the pointer
can optionally be post-incremented or post-decremented. The four pOinters, referred to as dram 1dram4, can be written and read via the A bus. When
a dram pointer, which is only 9 bits wide, is read onto
the A bus, its upper seven bits are set to zeros.
NOTE:

The width of the dram pointers may change in
later versions of the 82750PB. Software should
not rely on the width of a pointer to, for example, mask the upper seven bits of a value to
zero.

The ALU opcode 'int' generates the MCINT (microcode interrupt) condition. When this condition is detected by interrupt logic in the host CPU interface,
and if the Enable MCINT bit in the PROCESSOR
CONTROL register is set to a ONE, the host interrupt output, HINT#, will be asserted. Refer to Chapter 3 for further information on host interface.

All four pointers can be used to read or write the
Data RAM from either the A or B bus. Only one Data
RAM access can be performed in any cycle. A Data
RAM access is referred to, using C language syntax,
as *dram1. The' means "the value pointed to by".
As another example, *dram3+ + means access the
Data RAM using the pointer dram3 and increment
dram3. The symbol - - in place of the + + would
indicate auto decrement.

The 'prof' opcode activates the PMFRZ# pin, and is
primarily used for performance monitoring and/or
debugging.

Barrel Shifter
(shift, shift-r, shift-r!. shift-II

Loop Counters

The barrel shifter performs a single cycle, n-bit left or
right shift. The barrel shifter operates independent of
the ALU. The three barrel shifter operations are:
Shift-r for a right shift with sign extend; Shift-rl for
right shift with zero fill; and Shift-I for a left shift with
zero fill. The shift operation is invoked by writing a
4-bit value (the shift amount) to one of three A bus
registers, depending on which of the three operations is to be performed. The operand is taken from
the B bus, and the result is stored in the barrel shifter output register, Shift. Like the ALU result register,
the value in Shift can be read onto the A bus. or B
bus in the following instruction cycle.

Icnt,cnt21

Two 16-bitloop counters are available to microcode
programs for automatically counting iterations of a
microcode loop. In parallel with other operations
performed in an instruction, either loop counter can
be decremented, and a conditional branch can be
made based on the loop counter value being equal
or not. equal to zero. Since the two loop counters
can be written and read on the A bus, as cnt and
cnt2 respectively, they can also be used fo; variable
storage when not being used as loop counters. The
loop counters can be written to and decremented
during the same instruction· cycle. The value in the
counter at the start of the next cycle will be the value
written to the counter minus one.

A barrel shifter operation does not affect any of the
condition flags.

The LC microcode bit determines the loop counter
that is selected iar decrementing and/or branching
in an instruction. The LC microcode bit does not affect the loop counter that is written or read over the
A bus, since· each loop counter is separately addressable as a A bus source or destination. Refer to
1-70

82750PB

Chapter 4 for a description of the CNT - - microcode bit that causes the select loop counter to be
decremented, and for a description of the CFSEL
microcode field that is used to perform a conditional
branch based on the selected loop counter's value.

tion to be read and then reading the three 16-bit
words of the instruction from the mcode1-mcode3
registers. Normally, this would be done by the Host
CPU while the 82750PB is halted. Since mcode1mcode3 hold the instruction pointed to by the pc (Le.
the instruction that is about to be executed), normally reading these three registers froin a microcode
routine is not useful.

Microcode RAM
{meodel-3, maddr, pel

The read registers named mcode1-mcode3 and the
write registers also named mcode1-mcode3 are in
fact different registers. Writing values into mcode1mcode3 and then reading the values of mcode1mcode3 will not read back the same values just writ·
ten. The read registers hold the instruction stored ir
the instruction latch (the instruction to be executed).
The write registers hold an instruction that is about
to be written into microcode RAM.

The 82750PB executes instructions stored in an onchip microcode RAM. This RAM holds 512 instructions and each instruction is 48 bits wide. Normally,
to start the microcode processor, the host CPU will
load a microcode program into the microcode RAM,
point the program counter, pc, to the start of the
program, and then release the HALT bit to start executing the microcode program. The microcode processor can also load its own microcode RAM to overlay new routines and therefore, qoes not require
constant intervention by the host to perform multiple
operations.

After writing to maddr to load an instruction into microcode RAM, a one cycle freeze occurs and during
the freeze a write to the microcode RAM takes
place. The instruction following the write to maddr
can either jump to the address just loaded or start
loading the mcode 1-mcode3 registers with the next
instruction to be written.

Writing an instruction into Microcode RAM is done
by first loading the three registers mcode3, mcode2,
and mcode 1 with the three 16-bit words of the instruction (the most significant word goes into
mcode1), and then loading the address where the
instruction should be written into maddr.

Here are two examples that illustrate the fact that
the. 82750PB requires at least one instruction between the write to maddr and the execution of the
instruction that is loaded by the write to maddr.

The host CPU can also read the Microcode RAM by
first loading the pc with the address of the instruc-

Example 1:
maddr = ADDRl
jmp addrl

/* load instruction */
/* jump to it, this is the extra inst. required between */
/* uriting to maddr and executing the loaded inst. */

ADDR1:
????n?????

/* here '.s where new instruction gets loaded

*/

Example 2:
maddr = INST
nop

INST:
?f?????????

/* extra instruction */

/* instruction gets loaded here */

When a microcode routine writes to pc, one more instruction is executed before the jump to the new address
takes effect. For example:
.
pc
ADDRl
rO = rl
jmp ADDR2

1* this instruction gets executed but */
/* its jump to ADDR2 is ignored. */

ADDR1:
r3 = rO

/* after this instruction executes r3

1-71

= rO =

rl */

82750PB

When the host CPU writes to the pc, the instruction
at the address that was written is loaded into the·
mcade 1-mcode3 registers and, when the microcode processor is released from its Halt condition,
this is the first instruction that will be executed.
When the host CPU reads the pc, the result returned
is the address of the instruction that will be executed
when Halt is released, that is, the address of the
instruction held in the mcade1-mcade3 registers.

Horizontal Line Counter
!lent)

The 12-bit Horizontal Line Counter is updated by
VB US codes from the 82750DB to track the horizontal display line that is currently being scanned by the
82750DB. The counter is reset by a VODD code and
incremented each time an HLiNE code is received.
A value can also be written into a Horizontal Line
Counter but this is used primarily for testing the
82750PB. The upper four bits will always read zeros.

Field Counter
{tent)

The 4-bit field counter is updated by VBUS codes
from the display processor to keep track of the field
count being displayed by 82750DB. The counter is
incremented each "time a VODD code or VEVEN code
is received. When reading the field counter, the upper 12 bits will read zeiOS. This counter wiii not be
initialized upon reset.

The mode control register for each input FIFO, designated in1-c or in2-c, contains four mode bits as
seen in Figure 2-2. The WORD/BYTE bit (bit 0) determines whether the input FIFO is in word mode
(WORD/BYTE = 0) or byte mode (WORD/BYTE =
1). In byte mode, the FIFO can start reading on any
byte boundary and in word mode on any word
boundary.
The INC/DEC bit (bit 1) determines the order that
bytes or words. are read from VRAM. In INCREMENT mode, with INC/DEC = 0, the FIFO reads
from the least significant byte or word to the most
significant byte or word of each double word and
increments through double words in VRAM. In DECREMENT mode, with INC/DEC = 1, the FIFO reads
from most significant byte or word to least significant
byte or word within a double word and decrements
through double words in VRAM.
The AHOLD bit (Bit 2) is used by the address hold
mode. When asserted, (bit 2 = 1) the automatic address increment/decrement function will be disabled
and input FIFOs will not double buffer VRAM data. In
other words, at the end of a VRAM cycle, when the
FIFO has been updated with 64 bits of VRAM data,
the input FIFO will not issue another MREQ# until
there is a write to the address-Io registers OR a rollover/roil-under read access of the input FIFO. If a
roll-over/roll-under occurs, then a memory request
will be issued to fetch data from the same VRAM
location. If there is a write to the address-Io register,
the FIFO will then fetch data from the new location.
The PREFETCH OFF bit (bit 3) specifies whether
the FIFO will automaticallyprefetch successive quad
words from VRAM or will only fetch a new quad word
when a value from that quad word is requested. In
PREFETCH-ON mode, bit 3 = 0, the input FIFO prefetches successive quad words from VRAM as necessary to keep its buffer full (either from ascending
or descending addresses, depending on the state of
the INC/DEC bit). In PREFETCH-OFF mode, the
FIFO will still prefetch the first two quad words to fill
its buffer (when started at a new address location),
but will only fetch a new quad word when a read
request is made to the FIFO for a value in the next
unfetched quad word.

Input FIFOs
(inN-1o, inN-hi, inN-e, 'inN; N = 1, 2)

There are two input channels, referred to as input
FIFOs, through which the processor can read pixels
or data from VRAM. Each channel automatically
fetches 64-bit quad words from VRAM and breaks
them into 8-bit bytes or 16-bit words that are read by
microcode. Each input FIFO operates independently
and can be programmed to automatically increment
or decrement through bytes or words in VRAM. The
FIFOs are double buffered so that while values are
being extracted from one quad word (64 bits), the
next quad word is being prefetched from VRAM.

bits:

15 ... 6
Set to Zeros

5
BY-32 tv10DE

4
CB

The CB bit (bit 4) allows circular buffers of sizes
64 Kbytes, 128 Kbytes, or 256 Kbytes to be created
in VRAM memory. The choice of different sizes of
buffers are determined by programming the least
signficant 3 bits of the circular buffer register (cir-

3
PFOFF

2
AHOLD

Figure 2-2. Input FIFO Control Register

1-72

1
INC/DEC

o
WORD/BYTE

82750PB

cbuf). To enable this feature, the CB bit has to be
set to a 1, then depending on the buffer size
selected, the appropriate address pin that goes off
chip will be forced to a 0 (register pointers remain
unchanged). Table 2-3 shows the programming
combinations of the circular buffer register.

Output FIFOs
loutN-lo, outN-hi, outN-c, 'outN, outN+

Table 2-3. Circular Buffer Register (circbuf)

000

Disabled

Effect on PB Address Bus
(If Function Enabled)

21

None

100

256 Kbytes Address Pin 18 Forced to 0

010

128 Kbytes Address Pin 17 Forced to 0

001

64 Kbytes Address Pin 16 Forced to 0

The mode control register for each output FIFO,
designated outl-c or out2-c, contains six mode bits
as shown in the Figure 2-3. The WORD/BYTE bit
(bit 0) determines whether the output FIFO is in word
mode (WORD/BYTE = 0) or byte mode (WORD/
BYTE = 1). In byte mode the FIFO can start writing
on any byte boundary in VRAM and in word mode on
any word boundary.

In "BY-32" MODE (bit 3), the pointer increments or
decrements by 32 bits, independent of whether the
FIFO is in 8-bit pixel mode or 16-bit pixel mode. This
mode was added to facilitate microcode that operates on one component of a 32-bit per pixel image.
The standard sequence for initializing an input FIFO
is to write to the control register (in-c), the high address (in-hi), and then the low address (in-fa) of the
appropriate FIFO. Refer to the access state diagram
in Chapter 3. The write to in-fa causes the FIFO to
start reading from VRAM. A byte or word is then
read from 'in. Successive reads from 'in will read
sequential bytes or words from VRAM. Writing to the
control register each time the FIFO is started at a
new address is not necessary, except to change the
FIFO's mode. Also, if the new address is within the
same 64 kByte page of VRAM, only the lo-address
needs to be written in order to start the FIFO reading
from the new address.
If microcode attempts to read a value from an empty
input FIFO, the processor is frozen prior to the execution of the instruction, until the FIFO's control logic has fetched another double word from VRAM and
extracted the next value. At this point, the processor
is released from the frozen state, and the instruction
that reads the value is executed. When the processor is frozen waiting for a particular FIFO that isn't
yet ready, that FIFO's VRAM access priority is raised
above all other FIFOs.
bits:

1,

There are two output channels, referred to as output
FIFOs, through which the graphics processor writes
pixels or data to VRAM. Each channel automatically
collects bytes or words into 64-bit quad words and
writes the quad words to VRAM. Each output FIFO
operates independently and can be programmed to
write bytes or words into sequential addresses in
VRAM (either incrementing or decrementing). The
FIFOs are double buffered so that while one quad
word is waiting to be written to VRAM, the next quad
word can be assembled from individual bytes or
words.

It is important to note that the internal address
counters themselves are not affected by the circbuf
function. Only the selected external address pin is
forced to '0'.

Bits [2:0] Buffer Size

+ .. N =

The INC/DEC bit (bit 1) determines the order that
bytes or words are written to VRAM. In INCREMENT
mode, with INC/DEC = 0, the FIFO writes from the
least significant byte or word to the most significant
byte or word in a double word and increments
through double words in VRAM. In DECREMENT
mode, with INC/DEC = 1, the FIFO writes from
most significant byte or word to least significant byte
or word within a double word and decrements
through double words in VRAM.
When the AHOLD bit (bit 2) is set, th~ output FIFO
quad word address is not incremented or decremented. In this mode, the FIFO continues to output
to a single quad word in VRAM.
The FORCE-LSB bits (bits 3 and 4) are used to force
the least significant bit of each byte written to VRAM
to either a zero or a one. This can be used, for example, to force the LSB to the correct polarity when
writing to the U bitmap during motion video decompression. In certain display modes for the 82750DB,
the LSB of the 8-bit samples in the U or Y bitmap are
used to select VIDEO or GRAPHICS display mode
for the n x n group of display pixels corresponding to
the particular U or Ysample. A one in the FORCE-

15-6
5
4
3
2
1
0
Set to Zeros BY-32 MODE FORCE-LSB FORCE-LSB AHOLD INC/DEC WORD/BYTE
ENABLE
VALUE
Figure 2.-3. Output FIFO Control Register
1-73

82750PB

LSB ENABLE bit (bit 4) enables the forcing; a zero
results in normal operation. The FORCE-LSB VALUE bit (bit 3) is used as the value to which the LSB is
forced. Whether in byte mode or word mode, the
LSB of each byte is forced to the FOR9E-LSB value.

Statistical Decoder
Istat-1o, stat-hi, stat-c, stat-ram, 'stat, 'stat# I
The Statistical Decoder (also referred to as the Huffman Decoder) is a specialized input channel that
can read a variable-length bit sequence from VRAM
and convert it into a fixed-length bit sequence that is
read by the microcode processor. In image compression, as well as in other applications such as
text compression,' certain values occur more frequently than others. A means of compressing this
data is to use fewer bits to encode more frequently
occurring values and more bits to encode less frequently occurring values. This type of encoding results in a variable-length sequence in which the
length of a symbol (the group of bits used to encode
a single value) can range for example, from one bit
to sixteen bits.

In "BY-32" MODE (bit 5), the pointer increments or
decrements by 32 bits, independent of whether the
FIFO is in 8-bit pixel mode or 16-bit pixel mode. This
mode is used to facilitate microcode that operates
on one component of a 32-bit per pixel image. The
bytes or words that are skipped over will be unchanged in VRAM.
The standard sequence for initializing an output
FIFO is to write to the control register (out-c), the
low address (out-to), and then the high address (outhi) of the appropriate FIFO. A series of bytes or
words is then written to 'out. Refer to the access
state diagram in Chapter 3 (Figure 3-1).

The statistical code that the statistical decoder can
decode is of either of the two forms: .

In order to flush any remaining data in an output
FIFO before changing its VRAM pointer, it is necessary to write to the control register. When pointing to
a new location in VRAM, if the new address is within
the same 64 kByte page of VRAM, only the lo-address needs to be written.

Ox
10x
110xxx
1110xxxxx

1x
01x
001 xxx
0001xxxxx
or

11111110xxxxxx
111111110xxxxxx

There must be one instruction between the write to
the output FIFOs low address and the first write to
·outN. Therefore, it is recommended that outN-lo be
written before outN-hi. The write to outN-hi insures
that this requirement is met. If only the outN-lo value
is being changed, it is still necessary to have one
additional instruction before the first write to ·outN.

00000001 xxxxxx
000000001 xxxxxx

Each symbol of a given length (one per line as
shown here) consists of a run-in sequence followed
by some number of x-bils. The run-in sequence is
defined as a series of zero or more ONEs followed
by a ZERO or, as in the code on the right above,
zero or more ZEROs followed by a ONE. The remainder of this description will use examples of the
code on the left. A bit in the decoder's control register determines the polarity of the run-in sequence
bits.

When writing bytes or words to VRAM through an
output FIFO, byte or word can be skipped over by
writing to outN+ + instead of 'outN. When the values are written to VRAM, any byte or word that was
skipped will retain its original value in VRAM, and its
value is not altered by the VRAM write. This can be
used when writing a series of pixels, some of which
are "transparent", allowing whatever was behind
them to show through.

a

In the example on the left, there would be two symbols of length two: 00 and 01. Each x-bit can take on
a ZERO or ONE value. The number of x-bits following a run-in sequence can range from zero to six.
Since the goal, in general, is to have a few short
codes and a larger number of long codes, typically,
codes with fewer run-in bits will have fewer x's following. However, this is not a hardware constraint. A
code of this form is completely described by a code
description table indicating: for each length of run-in
sequence, R = the number of ONEs in the run-in,
and how many x-bits follow the ZERO. The value of
R is used as an index into the code description table.
Due to the hardware implementation, the number
actually stored in the table is 2x, where x is the number of x-bits.

If the microcode routine attempts to write a value to
a full output FIFO, the processor is frozen prior to
the execution of the instruction. The processor remains frozen until the FIFO has a chance to write
one of the buffered quad words to VRAM. At that
point, the processor is released from the frozen
state, and the instruction that writes the value is executed. When the processor is frozen, waiting for a
particular FIFO that isn't yet ready, that FIFO's
VRAM access priority is raised above all other
FIFOs.

1-74

For the example above, the corresponding code description values are given in Table 2-4.

int:eL

82750PB

Table 2·4. Sample Code Description Table

R

X

2X(dec.)

2X(bin.)

0
1
2
3

1
1
3
5

2
2
8
32

0000010
0000010
0001000
0100000

6

64

1000000

where X(r) corresponds to the X value in the table
entry corresponding to R = r.
For example, in the above code:
B(O) = 0,
B (0) is always zero
B(1) = 0 + 2 = 2
B(2) = 0 + 2 + 2 = 4
B(3) = 0 + 2 + 2 + 8 = 12
B(4) = 0 + 2 + 2 + 8 + 32 = 44

...
7

This is one of the "reasons that the table holds 2x
instead of X. The calculation of B(R) are easier to
implement in logic.

Note that the table only goes up to symbols with
seven ONEs in the run-in. For symbols with more
than seven ONEs, the value of X and 2X for seven
ONEs is used for all symbols having seven or more
ONEs in the run-in sequence. For example, in the
code above a symbol with eight or more ONEs in tne
run-in sequence has six x-bits following the ZERO,
which is the same as symbols having seven ONEs.

There are two enhancements that are made to this
coding scheme in the implementation on the
82750PB. These two modes are referred to as END
mode and SHORT mode. If neither END nor SHORT
mode are enabled, the decoding is performed as described above. SHORT mode allows the decoder to
be switched easily to a simpler code format without
having to reload the code description table. In the
SHORT form, all symbols have the same number of
x-bits, as though all entries in the table had been
filled with the same value of 2x. When SHORT mode
is invoked, this value of 2x is obtained from a field in
the statistical decoder's CONTROL word, instead of
from the individual table entries.

For each different symbol, including all symbols of
the same run-in length with different x-bit values, the
decoder generates a unique fixed-length, 16-bit value. Some of the decoded values for the sample
code given above are provided in Table 2-5.
Table 2·5. Decoded Values
Symbol'

Decoded Value

00
01

1

" 100

2

101

3

110000

4

110001

5

110010

o
10x
110x

6

...

.

END mode is added in recognition of the fact that,
for codes with few symbols, some increase in efficiency is possible by not having to place a zero at
the end of the longest run-in sequence. For example, consider the code:

0

The END mode allows us to shorten the last symbol
to 11 x instead of 11 Ox. The trailing ZERO is not required because the decoder has been told that the
maximum length of a run-in is two ONEs. The resulting symbol set and corresponding decoded values
'
are given in Table 2-6.

. ..

110111

11

111000000

12

...

. ..

111011111

43

...

Table 2·6. END Mode Decoded Values
Symbol

0., •

The x·blts of the symbol are

In

0

boldface for clarity.

Th!3 algorithm for generating a decoded value from a
symbol is as follows: all symbols of a given run-in
length are assigned a base value, B; the value corresponding to a particular symbol is equal to B plus the
binary value of the x-bits in the symbol. The base
valule B for a symbol with a run-in length of R is
calculated by:
B(R)

=

SUM[2 X(rl] with r

=

0 to R - 1,

1-75

Decoded Value
0

100

1

101

2

110

3

111

4

82750PB

The number of x;bits must be. constant for all symbols of the same run-in length. Therefore, a code
such as:

Table2-S.Packed 3-Bit
Field Decoded Values
Table Entries

Code

o
10xx
11xxx +- NOT CORRECT! ... Must be 11xx.
is not allowed. The last symbol (11 xxx, in this case)
uses the same table entry for 2x as the next to last
symbol (10xx) and, therefore, the last symbol will. be
11xx.

Index
0

0

10xx

1

110xxx

2

111xxx

3
4

5

6
7

0

0

O·

4.

1

8

.. -

-

'.

-

1

1

3

5
6

,
2X

.

0

1xx

7

END Bit
I

oxx'

4

Table 2-7. END F:lag Decoded Values
Table Entries

END Bit

2

The maximum length of the run-in sequence in END
mode is specified by placing an END flag in the code
description table. For example, a code and the corresponding table is shown in Table 2-7.

Code

Index

2x
41 N

=

3, so X

-

-

-

-

-

= 21

:

-

The unpacked bits are in reverse order relative to
how they are stored in VRAM. For example, if thr!3ebifvaluesare packed in VRAM,the pattern 110in
VRAMis read from right to left and gives an un.
packed or decoded value of 3;
The CONTROL register for the statistical decoder
(stat~c) is used to specify the mode to use for decoding, as well as to invoke certain m()des for writing
and reading the ccide description table. Flefer to. the
bit aSSignments for this register below. To write to
the code description. table, the WRITE bit (bit 4) is
set to a ONE; the starting table index is reset to·
zero. Each write to the table causes the index to
increment by one. This index will wrap around from
seilen back to zero. For example, to write all eight
table entries the user would write a value of Oic10 to
stat-c register and then write eight a-bit values to the
register stat-ram. The most significant bit of each
8-bit value is the END bit, and the lower ~even bits
are the values of 2x. To read the code description
table, the TEST bit (bit 5) of the CONTROL register
is set to a one. The table entries are then read from
the decoder's data register (·stat). Reads and writes
always start at table entry zero.

-

-

The hyphens indicate that those table entries aren't
used to decode this code. Note that the symbol
111 xxx has three x-bits because of the value of 2x in
Index 2; it is not based on the 2x value in Il"!dex 3.
The SHORTED and END modes can be invoked
simultaneously, resulting in a code such as:
Ox
10x
110x
111x

NOTE:
When reading the code description table, it is
necessary to' wait one instruction time between
the write to stat-c and the first read from ·stat.
An access diagram showing all legal sequences
ior read and write' FIFO registers is shown in
Chapter 3 (Figure 3-1).

with a SHORT - 2 x value = 2 (for 1, x-bit in each
symbol) and the END bit set in Index 2.
Packed binary fields with one to seven bits per field
can be read using the statistical decoder by setting
the END bit in Index 0 and by programming the X
value to be N -1, where N is the number of bits per
field. For example, packed three-bit fields could be
decoded as shown in Table 2-8.

1-76

intel~

82750PB

The-code for reading the eight table entries into the first eight locations of data RAM would be:
dram3 = 0
cnt = 8
LOOP:

stat-c =, Ox20

Itest mode to read the stat-ram (the table)
Iwait one inst. before first read

'dram3+ + = 'stat cnt- jcp loop
Itwo inst. loop necessary to wait one inst.
Ibetween each read from ·stat.
Bits

15
POL

14
RSVD'

13
CB

12:8
SVAL

7
SHORT

6
END

5
TEST

4
WRITE

3
RSVO*

2:0
Starting
Stat-ram
ADDRESS

• Reserved: write zeros to these bits.

Figure 2·4. Statistical Decode CONTROL Register

END mode is enabled by setting the END bit (bit 6)
in the CONTROL register to a ONE. The SHORT
mode is enabled by setting the SHORT bit (bit 7) in
the CONTROL register to a ONE. When in SHORT
mode, the five SVAL bits (bits 12:8) in the CONTROL register are used as the SHORT - 2x value.

word and the fetch of the next 32-bit word may overlap. As with the input and output FIFOs, the decoder
has a VRAM pointer associated with it that points to
the location in VRAM from which it is reading data.
This pointer increments twice each time a new quad
word is read; there is no decrement mode. When the
least significant word of the decoder's pointer (statIo) is written, any data that had previously been prefetched from VRAM is ignored" and the decoder
fetches one quad word starting from this new location.

The POL bit (bit 15) determines the polarity of the
run-in sequence bits. If bit 15 = 0, then ONEs ending in ZERO (e.g., 111 Oxxx) sequence is selected. If
bit 15= 1, the ZEROs ending in ONE (e.g., 0001 xxx)
sequence is selected.
'

The 82750PB assumes that the statistically encoded
bitstream in VRAM starts with the least significant bit
of a double word. That is, the two LSBs of the address written to start-Io are ignored.

The CB bit (bit 13) allows circular buffers of sizes
64 Kbytes, 128 Kbytes, or 256 Kbytes to be created
in memory, as in the case of the input FIFO. The
choice, of different sizes of buffers are determined
by programming the least significant 3 bits of the
circular buffer register (circbuf). To enable this feature, the CB bit has to be set to a 1, then depending
on the buffer size selected, the appropriate address
pin that goes off chip will be forced to a 0 (register
pointers remain unchanged). Table 2-3 shows the
programming combination of the circular buffer
register.

The statistical decoder decodes data at a rate of
one bit per T-cycle. To a first approximation, the decode time for an N-bit symbol is:
decode time (in T-cycles) = N

+

1

Since it takes at least 64 T-cycles to decode data
from one quad word, which is the time required fo
eight quad word reads from VRAM, the decoder
should rarely run out of data. Therefore, the above
estimate should very accurately model the actual
decoding rate of the statistical decoder.

The decoding parameters may be changed between
symbols by writing to the CONTROL register and, if
necessary, writing new values into the, code description table. The correct procedure for changing the
code type or decode mode is to read the last value
from the decoder prior to the change, using *stat#
instead of *stat. This keeps the decoder from automatically starting to decode the next symbol. At this
point, the code description table and the SHORT
, and END mode bits can be changed as desired. The
next time the CONTROL register is written with both
TEST = 0 and WRITE = 0, the decoder will begin
to decode the next symbol using the new parameters.

The statistical decoder always begins to read the
bitstream from the least significant bit of the double
word found at the starting location in VRAM. That is,
the decoder does not start on a byte or word boundary as an input FIFO or output FIFO does, but only
on double word boundaries. The bitstream moves
from the least significant bit to the most significant
bit of a double word and then to the least significant
bit of the next double word (at the next higher ad-

The statistical decoder buffers one quad word read
from VRAMso that the decoding of bits in one 32-bit

1-77

iniei~

82750PB

dress location). For the x-bits. the first x-bit read
from the bitstream becomes the most significant bit
of the x-bit field when it is interpreted as a binary
number. The example below shows a code definition. a bitstream stored in VRAM. and the resulting
decoded values.
The code definition and range of values for each
symbol length are indicated in Table 2-9.
Table 2-9. VRAM Bitstream Decode Values
Symbol Values
0

Comments

0

10x

1.2

100=1.101=2

110xx

3-6

11000 = 3•...• 11011 = 6

1110xxx 7-14 1110000 = 7•...• 1110111 = 14
Decoding starts at address 0 in this example. The
two double words at addresses 0 and 1 are:
0: OxAC98E14D
1: Ox372E74CB
The bitstream in VRAM. with colons dividing the
symbols (read from right to left starting at LSB of
address 0) is shown in Figure 2-5.
Table 2-10 lists the symbols. in the order they are
encountered in the bitstream. and the corresponding
decoded values.

Address MSB

o

l1li(

Table 2-10. Decoding Syril60ts- -_.
Symbol
101

Value
2

. 100
101
0
0
0
0
1110001
100
100
11010
1110100

1
2
0
0
0
0
8
1
1
5
11

11001
0
1110011
101
0
0
1110110

4
0
10
2
0
0
13

...

. ..

Read bltstream from LSB to MSB 0(

Comments
Starts at LSB.
AddressO.
Scanning Left

Spans First and
Second Double Word

LSB

Start
1: 0 1 0 1 1 : ~ 0 1 : 00 1 : 1 0 0 0 1 1 1 : 0 : 0 : 0 : 0 : 1 0 1 : 0 0 1 : 10 1+ Here
First bit of a symbol, continued at LSB of next double word

0:0110111: 0: 0: 101: 1100111: 0: 10011 :001011
240854-5

Figure 2-5. VRAM Bitstream Decoding Addresses

82750PB

h
o

h=6~16
4

AI

B

I

0-0·

The example in Figure 2-7 shows a single row of
pixels being interpolated in Sequential-2D mode using two rows from the original (source) bitmap. The h
and v weighting are constant for ali the interpolated
pixels. In this case, the weights appear to be approximately h = 10/16 and v = 6/16.

I

12
I

15

I

·0

B

v

ABE
F
W
X
y
Z
C
D
G
H
K

4-·

B-·

-First Input Row
-Interpolated Row
--Second Input Row

Figure 2-7. Sequential-2D Pixel Interpolation
• W.

v=10/16 - - ••

The pixel interpolator is pipelined and requires some
startup sequence to fill the pipeline. Once .filled, the
pixel interpolator generates a new interpolated pixel
every two T-cycles when in Sequential-2D mode.
Source pixels are written into the interpolator as pixel pairs. In the case above, the pixel pair BA would
be written first, followed by the pixel pair DC. It would
seem more natural to refer to the pixel pair as AB,
but because of the way 8-bit pixels are arranged in
16-bit words in VRAM, the left-most pixel on the
screen is the least significant byte position. For example, if pixel A had a hex value of OxAA and B had
a value of OxBB, the 16-bit word containing pixels A
and B would have a value of OxBBAA. _

12-·

15-·

o

o

c

o

240654-6

Figure 2-6. Pil{el Interpolation

lPixellnterpolator
(Pixint-c, Pixint)

The pixel interpolator performs bilinear interpolation
on four 8-bit pixels to generate, in effect, a pixel
shifted by a fraction of a pixel position. See Figure
2-6. If the four pixels have values of A, B, C, and D;
and the horizontal weight and vertical weight are h
and v, respectively, the interpolated value W, ignoring any quantization effects, is given by: .
W = A*(1-h)(1-v)+ B*h(1-v)+C*(1-h)v+D*hv

The values of hand v are even multiples of 1/16.
Figure 2-6 illustrates pixel interpolation with an h
weight of 6/16 or 3/8 and a v weight of 10/16 or

5/8.
The pixel interpolar can operate in two modes: sequential-2D and random-2D. Sequential-2D mode is
used for motion video decoding and wheri an array
of pixels are interpolated with a common weighting.
Random-2D mode is used either when the pixel arrays to be interpolated are not adjacent pixels in two
rows or when the weight is changed for each interpolation_ (The word random is used here to mean
non-sequential.)

1-79

Then, two pixels are read from the interpolator. Because the pipeline isn't full yet, these pixels are read
and discarded. This loop of writing two pixel pairs
and reading two output pixels continues four times.
The two pixels that are read this fourth time are the
first two valid output pixels: Wand X. The interpolator may also collect output (interpolated) pixels into
pixel pairs. For exmple, pixels Wand X, instead of
being output separately, would be combined into a
16-bit pixel pair XW. Since there are two possible
phase relationships between the input pixel pairs
and output pixel pairs, the desired phasing (either X
and W paired or Y and X paired) can be specified.

intei®

82750PB

bits

13
12
11
10
9
8
7:4
3:0
15
14
'RESERVED-Write as ZERO
'Pipelining Select (1 = Fast,O = Standard)
'Phase (0 = In Phase, 1 = Opposite Phase)
'RESERVED-Write as ZERO
'Pairing (1 = Output Pixel Pairs, 0 = Single Pixels)
'Reset Bit (1 = Reset, 0 = Normal)
Mode Select Bits - - - - - - - - - - - - - - - - - - -' - - - - - - -'
Vertical Weight - - --'
Horizontal Weight - - - - - -'
Figure 2-8. Pixel Interpolator Control Register

Random-2D interpolation is used either when the
pixels to be interpolated are not in horizontal rows or
when the weight is changed for each interpolated
pixel. Examples for this are smooth warping or
smooth scaling operations. In the case of Random2D, the processing for successive interpolated pixels can not take advantage of pipelining; each pixel
is considered to be the first pixel of a Sequential
mode interpolation. The weight and the two input
pixel-pairs are written into the interpolator. After
waiting at least 10 T-cycles, the one interpolated pixel can be read. (The delay is 10 cycles when in the
standard mode (bit 14 = 0) and 6 T-cycles when in
the fast mode (bit 14 = 1).) Then, the next two input
pixel-pairs and if necessary, the new weight value,
are written, and 10 cycles later the next interpolated
pixel can be read.

RESET
Writing a ONE to bit 10 resets the pixel interpolator.
The pixel interpolator must be reset prior to changing modes.
PAIRING
A ZERO in bit 11 causes the pixel interpolator to
output individual pixels. A ONE causes the interpolator to collect adjacent pixels (in Sequential-2D
mode) into 16-bit pixel pairs. This feature assists in
motion video decoding, when combined with the
ALU's dual-add-with-saturate operation, by allowing
two pixels to be processed each cycle. The phasing
used in collecting the pixel pairs is determined by the
Phase bit described below.

The h and v weight values, the mode selection, and
other control bits are written to the pixel interpolator
contiOl register (avg-c). The bit assignment for this
register is in Figure 2-8. The least significant byte
holds the 4-bit v value (bits 7:4) and the 4-bit h value
(bits 3:0).
'

PHASE
When output pixels are collected into pixel pairs,
there are two possible alignments of the input pixel
pairs to the output pixel pairs. The Phase bit (bit 13)
selects the alignment to be used, based on the relative word alignment of the source and destination
bitmaps in VRAM. When the Phase bit is set to a
ZERO, this indicates that the bitmaps are in-phase.
In this case, the first two output pixels are grouped
into. one 16-bit pixel pair (with the first pixel in the
least significant byte). When the Phase bit is set to a
ONE, the bitmaps are out-of-phase. In this case, the
first pixel is placed in the most significant byte of the
first pixel pair, with invalid data in the least significant
byte, and the second and third output pixels are collected into the second pixel pair. This is illustrated in
Figure 2-9.

NOTE:
The values used for h and v here are numerators
of the fraction where the implied denominator is

16.

MODE SELECT
Bits 8 and 9 are used to select on of four operating
modes, of which only two are presently defined.
These modes are given in Table 2-11.
Table 2-11. Mode Select Operating Modes
Bits 9:8

Mode

00

RANDOM-2D

01

Sequential-2D

10

RESERVED

11

RESERVED

PIPELINING
A ZERO in bit 14 causes the pixel interpolator to use
the standard amount of pipeline delay. A ONE in this
field will select the fast mode that has less pipeline
delay. Table 2-12 shows the pipelining delay for both
modes. Note that the effect of the phase bit is to add
an extra pixel delay.
1-80

82750PB

In-Phase:

A_ _ B

I_ _ J

E_ _ F

W_ _ X

C_ _ O

1st Row of Input Pixels Pairs

Y_ _ Z

Output Pixel Pairs

G_ _ H

K_ _ L

2nd Row of Input Pixel Pairs

E_ _ F

I_ _ J

1st Row of Input Pixels Pairs

Out-of-Phase:
~B

?? _ _W

C_ _ O

~y

G_ _ H

Z _ _??

Output Pixel Pairs

K_ _ L

2nd Row of Input Pixel Pairs

Figure 2-9. Pixel Pair Phases
82750PA emulation mode, and the 82750PB in native mode. The currently defined signature values
given in Table 2-13.

Table 2-12. Pipelining Delay for
Sequeniial-2D NON-PAIR Mode
Pipelining
Bit
(Bit 14)

Phase
Bit
(Bit 13)

Pipeline Delay
in Output
Pillels

0

0

6

0

1

7

1

0

2

1

1

3

Table 2-13. Signature Values
Value

Definition

OxFFFE

The 82750PB Emulating the 82750PA

OXFFFC

The 82750PB in Native Mode

All other signature values are presently undefined
but may be used in the future to denote other versions of the 82750 architecture.

When in PAIR mode (with bit 11 = one), the amount
of pixel delay does not change, but half as many
reads and writes are required to fill the pipeline because each read or write of the averager transfers
two pixels. For example, when in the standard mode
(bit 14 = 0), with zero phase (bit 13 = 0) and pair
mode (bit 11 = 1), three indeterminate pixel pairs
must be read before the first good pixel pair is read.
In the same case but with the phase bit = 1, the
fourth pixel pair read contains one good pixel and
one indeterminate pixel, and the fifth pixel pair read
contains two good pixels.

Display format Registers
{yeven, yodel,

VU,

vptrl

The 82750PB's processor can write to the display
registers in the VRAM interface. These registers are
pointers and pitch values that address display bitmaps and 827500B register loads in VRAM. Pointers are 32-bit values that specify the specify the
starting byte address of a bitmap or register load
within a 4 GByte address space. The bottom two
address bits are ignored since display bitmaps and
register loads must start on a double word boundary.
Therefore, the internal representation of a pointer is
a 30-bit value. The pitch value associated with each
pointer indicates the number of bytes between the
start of two lines of a display bitmap or between the
start of two register loads. The pitch is a single 16-bit
value with its two least significant bits ignored, since
the pitch must be an integer number of double
words. Currently, there is also a restriction in the
8275008 limiting all display bitmap pitches to powers of two; so, the maximum display bitmap pitch is
± 214 Bytes = ± 16 kBytes. The display registers
are described in Table 2-14.

RESERVED
Bits 15 and 12 are reserved for future use. Write
ZEROs into these bit positions.

Signature Register
{hwid!

The signature register can be read either by the host
CPU or by microcode to determine the version of the
82750PB. The value of the signature register can be
used to distinguish between the 82750PB in the

1-81

82750PIB

Table 2·14. Display Registers
Register

Description

yeven-Io, hi

This register pair points to the start of the Y bitmap or main bitmap that
is to be displayed during an even field scan.

yodd-Io, hi

This register pair points to the start of the Y bitmap or main bitmap that
is to be displayed during the odd field scan.

ypitch

The value in this register is added to the current Y bitmap pointer value
each time a Y transfer is performed.

vu-Io, hi

This register pair points to the start of the VU bitmap. This bitmap is
read to generate the VU values for both odd and even field scans.

vupitch

This value is added to the current VU bitmap pointer value each time a
VU transfer is performed.

vptr-Io, hi

This register pair points to the start of a series of 8275008 register
loads stored in VRAM.

vpitch

This value is added to the current 8275008 register load pointer each
time a 8275008 register load is performed. The pitch is equal to the
number of bytes from the start of one register load to the start of the
next register load.

3.0 HARDWARE INTERFACE

o

Arbitrates VRAM accesses between the two input
FIFOs, the two output FIFOs, the statistical decoder, the transfer request logic, the VRAM refresh logic, and the external VRAM a~cess logic.

o

During a memory cycle, performs appropriate address arithmetic on the VRAM pointer used for
that memory cycle .

o

As a result of certain V8US codes, performs a
shadow copy that consists of copying display-related VRAM pointer values"from shadow registers
(that are loaded by the host CPU or the microcode processor) to working registers where the
various pointers are used for transfer cycles
when the 8275008 is refreshing the display
screen.

VRAM Interface
The VRAM interface performs the following operations:
• Maintains VRAM pointers for the two input FIFOs,
the two output FIFOs, the statistical decoder, the
Y (main) bitmap, the VU bitmap, and the
8275008 register load.
e

Decodes V8US codes and takes appropriate actions such as generating a transfer cycle, sched.uling refresh cycles, or generating interrupt conditions.

Table 3·1. VRAM Interface Signals
Description

Signal
MREQ#

MEMORY REQUEST is asserted during the first cycle of a VRAM
memory access.

TRNFR#

The TRANSFER output indicates the current memory cycle is a result
of a 8275008 transfer request.

RFSM#

The REFRESH output indicates the current memory cycle is a result of
a 8275008 refresh request.

NXTFST#

The NEXT FAST output indicates the next memory access will use the
same row address as the current memory access. This facilitates the
use of page mode memory accesses.

MROY#

The MEMORY READY input indicates the availability of valid data on
the 0[31 :0] pins.

1-82

intel·

82750PB

VRAM ACCESSES
The 82750PB can initiate five different types of
memory accesses: FIFO read, FIFO write, transfer
read, transfer write, and refresh. In addition, the
82750PB supports VRAM accesses by external logic. During an external access VRAM cycle, the
82750PB tri-states its VRAM address and data buses and performs a host VRAM read or host VRAM
write cycle. There is another operation performed by
the 82750PB, a shadow copy, that is not a VRAM
cycle but is arbitrated as though it were, since no
VRAMcycles can take place during a shadow copy.
The seven types of VRAM cycles initiated by the
82750PB, including host VRAM read and host
VRAM write, begin with the 82750PB asserting a
combination of its three VRAM cycle definition outputs: TRNFR#, RFSH#, and WE#. External logic
detects the state of these signals, validated by
MREQ#, and produces the appropriate sequence of
VRAM control signals (RAS, CAS, etc.) to perform
the type of memory cycle the 82750PB has requested. The 82750PB requires that each of these VRAM
cycles take a minimum of two T-cycles, or T-states,
denoted T1 and T2. External logic can insert additional T2 states in order to stretch the VRAM cycle
to more than two T-cycles. The start of a new VRAM
access cycle is signaled by the assertion of MREQ#
for the first T-cycle, T1. The VRAM access cycle

definition signals, TRNFR#, RFSH#, and WE#, are
asserted at the start of T1 and remain asserted until
the end of the last T2. Other VRAM operations can
be described similarly by sequences of T-states. Refer to Figure 3-4 and 3-5 on page 42 for timing diagrams.
Table 3-2 defines the states used for all VRAM access operations. A state diagram for the VRAMI
Host Interface is provided in Figure 3-1. This diagram includes the FIFO access states
Table 3·2. 82750PB VRAM Access States
State

Description

Ti

Idle State, No VRAM Activity

T1, TF1

First State of a VRAM FIFO Cycle

T2, TF2

Last State of a VRAM FIFO Cycle

TSC

The T-State required to perform a
shadow copy

TTX1

First State of a VRAM Transfer Cycle

TTX2

Last State of a VRAM Transfer Cycle

TRF1

First State of a VRAM Refresh Cycle

TRF2

Last State of a VRAM Refresh Cycle

FIFO ACCESS

/

/

,/

--

........

- -----------.....

HOST ACCESS

........ ,,

,'

\

I

/

I

/

//
1

1

/
,

I

\

I

1
I

I

1

I
I

1roI[1.40RY NOT
REAoY
\

\"
''- ........

I
I

_-

I

I

I

!

1
1

/

/1/

R[rRESH

CYCLE

240854-7

Figure 3·1. Access State Diagram
1-83

•

_ l!

!I

InTeD~

82750PB

Note that during successive VRAM cycles it is not
necessary to go back to the idle state, Ti, between
each cycle; the TF2 state can be followed directly by
a T1 state: starting at the next VRAM. cycle. This
results in efficient utilization of the 82750PBIVRAM
bandwidth by allowing a VRAM cycle time of 2
T-states.

The NXTFST # output signal is provided for cases
when external logic can generate a faster access for
the second access of the'two sequential accesses.
During such a pair of accesses, NXTFST # is asserted during the first of the two accesses in order to
provide sufficient time for the external logic to generate the appropriate fast memory cycle for the second access. Refer to the timing diagrams in Figures
3-4 and 3-5 (page 42) for examples illustrating the
use of the NXTFST # signal.

FAST VRAM CYCLES

When the 82750PB performs Data Read or Data
Write VRAM cycles for the input or output FIFOs, it
performs two 32-bit accesses to read or write one
54-bit value. These accesses are always performed
in a sequence of EvenAddress followed by EvenAddress + 1, which guarantees both that the two sequential accesses will be in opposite banks and that
the two accesses will be within the same VRAM
page. This allows external logic to use either bankinterleaving or a page-mode access to complete the
second access of the sequence and improve the
VRAM bandwidth. However, the second access
does not need to be handled differently from the
first. Except for the assertion of the NXTFST # signal, both accesses are treated as standard VRAM
accesses. External logic can ignore the NXTFST #
signal, though, and treat the two accesses as two
normal data read or data write cycles. Note that
NXTFST # is not asserted for transfer, refresh, or
host memory accesses.

VBUS CODES

Transfer request, interrupt, and synchronization
codes are sent over.the BUS from the 827500B to
the 82750PB. The codes recognized by the
82750PB are listed in Table 3-3, along with the actions taken by the 82750PB as a result of receiving
each code. Codes that cause TRANSFER cycles
must be asserted for at least two clock cycles of the
82750PB to insure that, in the worst case, the
82750PB completes the transfer cycle before the
code is released and the 827500B starts shifting
data from the VRAM shift registers. Other codes
must also be asserted for a minimum of two
82750PB clock cycles. Only the codes given in the
Table 3-3 are valid codes for the VBUS. Other codes
are reserved for future use and should not be used.
Once a transfer cycle code is sent to the 82750PB,
any non-transfer code may be sent immediately. A
subsequent transfer cycle code should be sent only
after the. current transfer cycle is completed.

1-84

InteL

82750PB

Table 3-3. VBUS Codes
Binary

Action

Name

+

0000

YBMX

TXRO Cycle Using Yc; Yc = Yc

0001

VUBMX

TXRO Cycle Using VUc; VUc = VUc

0010

REGX

TXRO Cycle Using Vc; Vc = Vc

0011

WROIGX

TXWR Cycle Using Yc; Yc = Yc

0100

YNPBMX

TXRO Cycle Using Yc; Yc = Yc

0101

Reserved

Reserved

0110

Reserved

Reserved

0111

WROIGNPX

TXWR Cycle Using Yc; Yc = Yc

1000

OFL

OFL Int; Shadow Copy"

1001

827500B80

827500B Shutdown Interrupt

Yp'

+ VUp

+ Vp
+ Yp

1010

REFRESH

Schedule N Refresh Cycles

1011

Reserved

Reserved

1100

VOOO

VBllnt; OF Int; Shadow Copy Odd; Hline = 0'"

1101

VEVEN

VBllnt; EF Int; Shadow Copy Even

1110

HLiNE

Icnt +

1111

NULL

No Action

+

(Increment Line Counter)

NOTES:

'Yc-Y bitmap pOinter, current; Yp-Y bitmap pitch; VU-VU bitmap; V-82750DB register load .
• 'Shadow Copy with Yc = Y-start-odd in odd field; Yc = Y-start-even in even field .
• , 'Hline-Horizontal Line Counter.

gle REFRESH code from the 827500B schedules a
number of refresh cycles, a higher priority for refresh
would cause all the refresh cycles to occur in a burst
that would lock out all lower priority requests until all
refresh cycles completed. Instead, the following
restriction applies to all request types with higher
priority than refresh: high priority requests, such as
transfer cycles, shadow copies, and external VRAM
access must occur infrequently enough to allow
proper refresh of the VRAM chips. Transfer cycles
and shadow copies, by their nature, occur infrequently so they are not generally a problem.

PRIORITY
Each time the VRAM state machine completes a
VRAM operation and returns to the Ti state, it examines all pending VRAM access requests and selects
the highest priority request for the next VRAM operation. The priority ordering of these requests are listed in Table 3-4.
Table 3-4. Priority of VRAM Operations
Request Type

Priority

Transfer Cycle

Highest

Shadow Copy

•
•
•

Host Access
VRAM Refresh
FIFO Read/Write

There is a separate priority scheme for the five FIFO
channels. The scheme used is rotating priority with
automatic override and single cycle arbitration. Rotating priority means that the priority is assigned in a
fixed cyclic order with the lowest priority given to the
FIFO channel that "won" the last FIFO access.
There is only one level of memory, so the order that
requests arrive is not a factor in the arbitration. The
cyclic order is given in Figure 3-2.

Lowest

NOTE:

The shadow copy is treated as a VRAM operation even
though it does not result in an access to VRAM.

As an example, if input FIFO 0 (abbreviated if0) was
the last channel to perform a cycle, the priority order
for the next FIFO access (from highest to lowest)
would be: if1, sd, of0, of1, and il0.

The VRAM refresh operation is placed low on the
priority list to reduce the latency in servicing transfer
requests and external VRAM requests. Since a sin1-85

II

82750PB

Automatic override that the rotating cyclic priority
can be bypassed if there is an URGENT condition
for one of the channels. A channel is urgent if the
microcode processor is frozen because the processor is waiting for that channel to be ready. The channel can be either an input channel that is empty or
an output channel that is full. In this case, the urgent
channel gets the next available cycle. However, the
priority will still be lower than non-FIFO requests,
such as refresh cycles.

If a VRAM pointer appears on the B-Bus as source
or as a destination then the following rules apply:
Rule 1

If a B-Bus destination refers to an address that is
both Even and > Ox1 f, then the source is restricted
to "-10" pointers if the source refers to a pointer.
Rule 2

Single clock cycle arbitration means that the selection of the next channel that will get an access occurs in a single T-cycle or T-state, either in a Ti state
or during the last T2 state of the previous VRAM
cycle:

If a B-Bus destination refers to an address that is
both Odd and >Ox1f, then the source is restricted to
"-hi" pointers if the source refers to a pointer.
SHADOW COPY

VRAM POINTERS

When a VODD, VEVEN, or DFL code is received
from the 82750DB over the VBUS, a shadow copy is
scheduled. The actual shadow copy will occur as
soon as the priority logic allows. Any VRAM access
in progress must complete and a pending transfer
cycle, if any, must be performed before the shadow
copy can start. During the operation, shadow registers for the Y-START, Y-PITCH, VU-START, VUPITCH, 82750DB-START, and 82750DB-PITCH are
copied into the corresponding working registers.
During display refresh, the address arithmetic is performed on the working registers. The shadow registers can be loaded by the host CPU or by a microcode routine with less critical timing constraints, and
then copied instantly by a shadow copy with it is time
to update the registers, either prior to the next field
or during the active display for split screen effects.

The VRAM interface maintains VRAM pointers for
the FIFOs, as well as display-related pointers for the
82750DB. Internally each pointer or address is
stored as a 30-bit value addressing a double word in
VRAM. The pointer values are read and written as
two 16-bit words representing a 32-bit byte address
(refer to the Figure 3-3). With a 30-bit double word
address, the 82750PB can decode a VRAM address,
space of 1G double words or 4 GBytes.
Input and output FIFOs can address down to a single word or byte in VRAM. A FIFO's pointer is postincremented or post-decremented in parallel with its
VRAM read or write cycle.
The statistical decoder can only start decoding bitstreams on double word boundaries.in VRAM and
can only increment through VRAM. The decoder's
pointer is post-incremented in parallel with each of
its VRAM read cycles.
Display-related pointers are updated by adding a
pitch value to the current value during the corresponding transfer cycle.

--+

in FIFO 1

--+

InFlFO 0

--+

outFIFO 1

--+

out FIFO 0

--+

t

Statistical Decoder

1

240854-8

Figure 3-2. Cyclic Ordering of FIFOs
31

30 29

24 23

16 15

3

2

1

0

<- - - - - - - - - - - - - - - - - - VRAM Address - - - - - - - - - - - - - - - - 30 bits - - - - - - - - - - - - >
Byte Address within Double-Word ......................................................... <- - -'>
I
<- Least Sig. Wd. of VRAM Addr.->

<- Most Sig. Word of VRAM Address. ->

Figure 3-3. VRAM Addressing

1-86

82750PB

There are actually two shadow registers for YSTART. One for start of odd fields and one for start
of even fields. A VODD code causes Y-START-ODD
to be copied into the working register Y-CURRENT.
Similarly, a VEVEN code causes the Y-STARTEVEN to be copied into Y-CURRENT. A DFL code
causes the Y-START-ODD value to be copied if the
most recent start of field code received is a VODD,
or a Y-START-EVEN value if the most recent start of
field code was a VEVEN. This allows a simple interlaced or non-interleaced display to be refreshed with
. no host CPU intervention. For more complex displays, such as split screens, the host CPU must update the shadow registers prior to each shadow
copy. A shadow copy operation requires 2 T-cycles.

Host Interface
The Host Interface provides the following functions:
" Arbitrates host CPU and 82750PB access to
VRAM.
.. Provides the host access to external devices.
o Provides the host access to 82750PB internal

registers and memories.
Signals specific to the Host Interface are listed in
Table 3-5.

Table 3-5. Host Interface Signals
Description

Signal

HREQ#

HOST REQUEST: Asynchronous request from the host for all types of
host access. Used both to request and release system buses.

HREG#

HOST REGISTER: Single-ranked control to request host access to
82750PB internal registers in concert with HRAM #.

HRAM#

HOST VRAM: Single-ranked control to request host access to VRAM in
concert with HREG #.

HALEN#

HOST ADDRESS LATCH ENABLE: Asynchronous status from the host
indicating the presence of valid address, write enable (transaction
direction control), and the byte enables at the interface of the 82750PB.

HBUSEN#

HOST BUS ENABLE: 82750PB synchronous status granting the host
access to the address, write enable, data bus, and byte enables at the
interface of the 82750PB.

HRDY#

HOST READY: 82750PB synchronous status to the host indicating the
presence of valid data appearing at the 82750PB's databus for VRAM
and register accesses and optionally for external accesses.

HINT#

HOST INTERRUPT: 82750PB synchronous interrupt to the host, set
under direct or indirect microprogram control.

Signals common to the host, VRAM, and external device interfaces are listed in Table 3-6.
Table 3-6. Host, VRAM, and External Device Interfaces
Description

Signal

A[31:2]

ADDRESS BUS: System address bus used to select unique VRAM, the
82750PB register, and external device locations that will be accessed
under host control. The lower seven bits A[8:2] are bidirectional and are
used during register accesses

0[31:0]

DATA BUS: Bidirectional system data bus used to transfer data to and
from all sources and destinations. When transferring 16-bit host register
values, the data bus MSH and LSH will both carry identical values.

WE#

WRITE ENABLE: Bidirectional, single-ranked signal used to determine
the data transfer direction. When active during host register cycles, data
flows from the host to an 82750PB destination. During host VRAM cycles,
WE# active will define the data direction to be from th,e host to VRAM.

BE[3:0]#

BYTE ENABLE: Bidirectional signals used to select the bytes that will be
modified during data transactions. All host register transactions are
performed 16 bits at a time, while VRAM may be modified 8 bits at a time.

1-87

II

82750PB

As with VRAM operations, host operations are described through a sequence of T-states. Table 3-7 defines
the T-states used to implement all host transactions with VRAM, external devices, and the 82750PB.
The master execution state diagram that defines the VRAM/Host transactions is provided in Figure 3-1.
Table 3-7. 82750PB Host Transaction States
State

Description

TA

First state of any host transaction. Entry into TA will be granted after
HREQ# has been asserted. During this state, the 82750PB will tri-state
its address, data bus, write enable, and byte enable signals to provide a
full cycle of "dead-band" before the assertion of HBUSEN #. In the state
immediately following TA HBUSEN # will assert, allowing the host to drive
the host buses.

TB

First cyCle in which the host is granted bus access for register or VRAM
transactions. The sequencerwill remain in TB until HALEN # is received,
indicating that the address write enable and byte enable signals are
stable at the 82750PB pins.

TC1

First cyclethat output data is valid.

TCn

This state is entered to wait for the completion of the current host cycle.
The cycle is defined as complete when HREQ # deasserts. HRDY # is
asserted along with valid data until the transition to state TD occurs.

TO

The last cycle of a host transaction. HBUSEN# is deasserted allowing
one dead-band cycle to allow control of the address, data, write enable,
and byte enable signals to be returned to the 82750PB.

TV1

First cycle of a Host VRAM transaction. Memory is requested and is
followed by a transition to TV2.

TV2

Last cycle of a Host VRAM transaction. The sequencer will remain in TV2
until MRDY # is received.

A single stage of .input synchronization is employed
for HREG#, HRAM#, WE#, and BE[O]#, while
HREQ# and HALEN# are programmable to have
one or two stages by bit 12 of the Microcode Processor Control Register. See Table 3-10. T-state transitions are caused by the synchronized versions of
these signals.

HOST REGISTER ACCESS
The host has access to the 82750PB's internal registers and memories to monitor and control the oper:
ation of the microcode processor, provide a means
of debugging microprogram routines, and to function
as the primary test port for production testing.

The synchronized versions of HREG# and HRAM#
must be stable before entry into T-state TA. The
synchronized versions of WE#, BE[O]#, and
HALEN # should be stable before exiting T-State
TB. Once .asserted, all of the above signals should
remain stable until the deassertion of HBUSEN #.

Register access is initiated by the host asserting
HREQ#, HREG#, and HRAM# as shown in Table
3-8 and in the timing diagrams on pages 42 through
45. After the host has been granted bus access by
an active HBUSEN# in state TB, the address, write
enable, and byte enables may be driven. After these
signals have stabilized HALEN # is asserted, enabling a read or a write operation to occur.

The type of host cycle to perform is determined by
the states of HREG # and HRAM # as indicated in
Table 3-8.
Table 3-8. Host Cvcle Types

-

HREG#

HRAM#

Host Cycle
Type

1

1

External

0

1

Register

1

0

VRAM

0

0

Reserved
1-88

82750PB

In the case of a register read, state TC1 is entered
and the data bus is driven with the internal value.
One cycle later, a transition to state TC occurs, and
HRDY # activates, signaling the presence of stabilized data at the 82750PB data pins. This state (TC)
will be maintained until the host deasserts HREQ #,
signaling the completion of the cycle that caused a
transition to state TO.

NOTE:
The host device must be able to transmit or receive
memory data in order to be valid at the trailing
edge of MRDY # at the data's destination (memory
or host).
After MRDY # becomes active, a transition from TV2
into TC1 is accomplished to allow time to propagate
data to the host. TC is then entered to await the
deassertion of HREQ# (if it has not already occurred). TO is then entered, duplicating the deadbanding previously described.

In the case of a register write, TC1 is again entered
(from TB), but the data bus may now be driven by
the host. (During host cycles, data bus drive activity
is indirectly controlled by WE # and an additional
dead-band is provided by entry into state TC1 to allow for internal WE # stabilization.) Stable data at
the 82750PB interface, as well as the completion of
the write cycle, is signaled by the deassertion of
HREQ#. As with reads, the deactivation of HRDY#
signals-the transition to state TO.

HOST EXTERNAL ACCESS
In addition to VRAM and register host access, an
external device access mechanism is provided_ During this access, upon the receipt of HREQ# with
HREQ# and HRAM# inactive, the 82750PB releases the address, data, write enable, and byte enables
in state TA.

As state TO is entered, HRDY # and HBUSEN #
deassert, the address data, write enable, and byte
enables tri-state, and bus control is returned to the
82750PB in the following cycle.

The difference here is that state TC1 is directly entered from T A, thereby ignoring any transitions of
HALEN #. Since the 82750PB also ignores the data
bus direction control (write enable) the host and an
external device may communicate unencumbered
by the 82750PB.

HOST VRAM ACCESS
Because the 82750PB is so closely coupled with
VRAM, host accesses to VRAM are arbitrated and
controlled by the 82750PB. VRAM access is initiated
by the host asserting HREQ#, HREG#, and
HRAM # as shown in the Host Cycle Table above
and in the timing diagrams on pages 42 through 45.
After the host has been granted bus access by an
active HBUSEN #, the address, write enable, and
byte enables may then be driven. After these signals
have stabilized at the memory devices (or longest
relevant propagation path), HALEI'>J # is asserted,
enabling a read or a write operation to occur.

Entry into state. TC directly follows TC1 in the expected sequence and remains there until HREQ# is
released. This is followed by entry into TO.
HBUSEN # is asserted during the timing that TC1
and TCN are active.
During an external access, HRDY # is not asserted
unless the external logic asserts MRDY # as shown
in Figure 3-7.
HOST REGISTER ADDRESS MAPPING

Because VRAM will not drive the data bus until after
a memory request, a transition into state TC1 to allow for data bus direction stabilization is not required. Instead, a transition to state TV1 occurs,
which asserts MREQ# for a single cycle and is followed by a transition to TV2. TV2 will remain the
current state until the reception of an active
MRDY#.

Table 3-9 shows the host address mapping of the
on-chip registers and memories, in terms of the offset in bytes, from the base address for 82750PB
accesses_ Note that the 82750PB only supports
word accesses to these registers. Therefore, the
least significant bit of the byte offset should be set to
zero. The 82750PB forms the register address from
inputs on the A[31 :2] pins and BE# [3:0] pins. The
A[31 :2] specify the double word address of the register, and combinations of the BE # pins determine
which of the two words with the double word is being
addressed. BE # [3:0] = 110°2 selects the least significant word within a double word, and BE # [3:0] =
00112 selects the most significant word within a
double word. These are the only two valid patterns
for BE # inputs during a host register access cycle.

In the case of a VRAM read, the memory data bus
will be driven during TV1, and valid data will appear
in state TV2. Data will be guaranteed valid coincident with the deassertion of MRDY # from memory.
In the case of a VRAM write, the memory data bus is
driven with valid data during TV1. Again the reception of MRDY # will serve to indicate the completion
of the memory operation.

1-89

II

intei®

82750PB

During an access to areas (a) or (b), bits 6:1 of the
byte offset should be set to the source or de~tina­
tion code for the register that will be read or wntten.
The coding is the same as used in the microcode
instruction word. Bit 0 is always set to a zero. Refer
to the 82750PB Source and Destination Coding
Table found in Chapter 4,

Table 3-9. Host Address Mapping
Byte
Address

OxOOO-Ox07E
Ox080-0xOFE
Ox100-0x17E
Ox180-0x1 FE

Description

(a) A source and
destination registers
(b) B source and
destination registers
(c) Microcode processor control
and status registers
(d) VRAM pointer RAM

Area (c) contains one write-only register, the CONTROL register, and two read-only registers, the INTERRUPT FLAG register and the microcode PROCESSOR STATUS register. The CONTROL register is
used to halt or single-step the microcode processor,
which enables or masks interrupts to the host CPU,
selects the signal that is output via the PMON/FRZ
pin, and enables or disables the 82750PAemulati?n
mode. The bit assignments for the CONTROL regIster are given in Table 3-10.

NOTE:
The host should only perform 16-M word reads
or writes to 82750PB registers. The 82750PB
does not support byte reads or writes or double
wordreads or writes to on-chip registers.

During reset of the 82750PB, the HALT bit is set to a
one, the six Interrupt Enable bits are reset to zero,
the Disable SYNC bit is set to zero, the PMON/FRZ
bit is set to zero (so that the FRZ signal is output),
and the Enable 82750PB bit is reset to zero (so that
on reset, the 82750PB starts in a 82750PA emulation mode).

When the host CPU reads or writes to areas (a, b, or
d) and the 82750PB is not already in a HALTstate,
the m,icrocode processor is automatically HALTED
for the one T-cycle actually required to complete the
data transfer, and then the processor is restarted
after the transfer is complete. If the 82750PB is in a
HALT state when the host access is initiated, it will
remain in the HALT state following the completion of
the access. This is transparent to both the host CPU
and the microcode processor.

1-90

82750PB

Table 3-10. Bit Assignments for Microcode Processor CONTROL
Register [Write-Only, Byte Offset = Ox1001
Bit

BitO

Name

HALT

Description

1 = Microcode Processor Halt
Microcode Processor Run

o=
Bit 1

SINGLE-STEP

Bit 2

Enable MCINT

1 = Execute One" Instruction and then Halt
(Only when Already Halted, Bit 0 = 1)
0= No Action
1 = Enable Microcode Interrupts to Host CPU
Mask Microcode Interrupts

o=
Bit 3

Enable VBI

1 = Enable Vertical Blanking Interrupt to Host CPU
Mask Vertical Blanking Interrupt

o=
Bit 4

Enable DFL

1 = Enable DFL Interrupt to Host CPU
Mask DFL Interrupt

o=
Bit 5

Enable SD

1 = Enable 82750DB Shutdown Interrupt to Host
Mask SD Interrupt

o=
Bit 6

Enable OFI

1 = Enable Odd Field Interrupt
Mask OF Interrupt

o=
Bit 7

Enable EFI

1 = Enable Even Field Interrupt
Mask EF Interrupt

o=
Bits 8-11 *
Bit 12

1 = RESERVED; Write as Zeros
Disable SYNC

1 = Disable Synchronizers for HREQ# IHALEN #
Enable Synchronizers for HREQ# IHALEN#

o=
Bit 13

PMON/FRZ

1 = Output FRZ # Signal on PMFRZ # Pin
Output PMON # Signal on PMFRZ # Pin

o=

1 = RESERVED; Write as Zero

Bit 14
Bit 15

Enable 82750PB

1 = Enable 82750PB Mode
Enable 82750PA Emulation Mode

o=

'AII other bits are reserved for future use, and should be written as zeros.

1-91

82750PB

The INTERRUPT FLAG register holds a flag for
each of the six interrupt sources. A flag bit is set to a
one when the interrupt condition is detected (independent of the state of the corresponding Interrupt
Enable/Mask bit in the CONTROL register), and all
flags are cleared to zero each time the INTERRUPT
FLAG register is read. If this register is read during
the same cycle that an interrupt condition is detected, the flag bit corresponding to that interrupt condition will remain at a one. This new interrupt condition
will then be seen by the host processor when it next
reads the INTERRUPT FLAG register. The flag insures that an interrupt is not lost if it occurs at the
same cycle that the INTERRUPT FLAG register is
read (and reset). In addition, the Microcode Interrupt
source has an overflow flag that indicates if more
than one Microcode Interrupt has occurred since the
Interrupt Flag register was last read. The bit assignments for the INTERRUPT FLAG register are listed
in Table 3-11.

The PROCESSOR STATUS register holds four
status bits: HALT, FREEZE, PMON, and SYNC
status. HALT indicates that the processor is HALTED due to a HALT bit in the CONTROL register being set to ONE or due to the HALT # pin being
asserted. FREEZE indicates that the processor is
waiting for one of the VRAM channels to become
ready or is waiting for an access to the VRAM pointer RAM. PMON is a signal that can be.toggled by a
special ALU opcode or a special B source code.
This signal can be used for performance monitoring
of microcode. SYNC status bit indicates the presence or absence of the internal synchronizers for
HREQ# -and HALEN# inputs. In addition, the Interrupt Mask bits that are written into the PROCESSOR
CONTROL register can be read from this register.
These mask bits are read in the same polarity that
they are written, but note that the bit positions and
bit ordering are not consistent with the PROCESSOR CONTROL register. The bit aSSignments for
this register are given in Table 3-12.

a

Address mapping for areas (a), (b), and (d) are given
in Tables 3-13 to 3-15.

Table 3-11. Bit Assignments for INTERRUPT FLAG Register
(Read-Only, Byte Offset = Ox100)
Bit

Description

Bit 8:0

Not Used, the State of These Bits Are Not Specified

Bit 9

EF Interrupt Flag

Bit 10

OF Interrupt Flag

Bit 11

MCINT Overflow Flag

Bit 12

82750DB Shutdown Interrupt

Bit 13

MCINT Microcode Interrupt

Bit 14

VBI Vertical Blanking Interrupt

Bit 15

DFL Display Format Load Interrupt

1-92

82750PB

Table 3·12. Bit Assignments for PROCESSOR STATUS Register
(Read·Only, Byte Offset = Ox102)
Bit

Description

=

=

BitO

HALT (1

Bit 1

FREEZE (1

Bit 2

PMON (1

Bit 3

Synchronizers on HREQ# IHALEN # (0

Bit 9:4

Not Used, the State of These Bits is Not Specified

=

Halted,O

=

Frozen, 0

Active, 0

=

Running)

=

Running)

Inactive)

Bit 10

MCINT Microcode Interrupt Mask

Bit 11

VBI Vertical Blanking Interrupt Mask

=

Bit 12

DFL Display Format Load Interrupt Mask

Bit 13

82750DB Shutdown Interrupt Mask

Bit 14

OF Interrupt Mask

Bit 15

EF Interrupt Mask

1-93

Enabled, 1

=

Disabled)

82750PB

Table 3-13. 82750PB A Bus Source/Destination AddresS Mapping

Address (Hex)

ADST

OxOOO

Null

OxOO2
OxOO4
OxOO6

ASRC

Address (Hex)

ADST

Null

Ox042

out1 + +

'in2

hwid·

Ox044

shift-hi

'stat

ee

Ox046

out1-hi

*stat#

Ox048

'out2

maddr

OxOO8

alu

Ox04A

out2+ +

OxOOA

ent

ent

Ox04C

shift-r

OxOOC

ent2

ent2

Ox04E

out2-hi

OxOOE

lent

lent

Ox050

out1-e

rO

rO

Ox052

in1-e

Ox010

ASRC

Ox012

r1

r1

Ox054

shift-I

Ox014

r2

r2

Ox056

in1-hi

Ox016

r3

r3

Ox058

out2-e

Ox018

r4

r4

Ox05A

in2-e

Ox01A

r5

r5

Ox05C

Ox01C

r6

r6

Ox05E

in2-hi

Ox01E

r7

r7

Ox060

r8

r8

Ox020

meode3

meode3

Ox062

r9

r9

Ox022

meode2

meode2

Ox064

r10

r10

Ox024

meode1

meode1

Ox066

r11

r11

Ox026

pc

pc

Ox068

r12

r12

Ox028

pixint-e

Ox06A

r13

r13

Ox02A

pixint

pixint

Ox06C

r14

r14

Ox02C

*dram1

*dram1

Ox06E

r15

r15

Ox02E

*dram2

*dram2

Ox070

ee

shift

Ox030

*dram1 + +

*dram1 + +

Ox072

fent

fent

Ox032

*dram2+ +

*dram2+ +

Ox074

*dram3

*dram3

Ox034

*dram1- -

*dram1- -

Ox076

*dram4

*dram4

Ox036

*dram2- -

*dram2- -

Ox078

*dram3+ +

*dram3+ +

Ox038

dram1

dram1

Ox07A

*dram4+ +

*dram4+ +

Ox03A

dram2

dram2

Ox07C

*dram3- -

*dram3--

Ox03C

dram3

dram3

Ox07E

*dram4- -

*dram4- -

Ox03E

dram4

dram4

Ox040

*out1

*in1

1-94

intel®

82750PB

Table 3-14. 82750PB B Bus Source/Destination Address Mapping
Address (Hex)

BDST

BSRC

Address (Hex)

BDST

OxOSO

Null

Null

OxOC2

out1 + +

alu

OxOC4

out1-lo

out1-lo

OxOS2

BSRC

OxOS4

*dram3

*dram3

OxOC6

out1-hi

out1-hi

OxOS6

*dram4

*dram4

OxOCB

*out2

stat-Io

OxOSS

*dram3+ +

*dram3+ +

OxOCA

out2+ +

stat-hi

OxOSA

*dram4+ +

*dram4+ +

OxOCC

out2-lo

out2-lo

OxOSC

*dram3- -

*dram3- -

OxOCE

out2-hi

out2-hi

OxOSE

*dram4- -

*dram4- -

OxODO

out1-c

out1-c

Ox090

rO

rO

OxOD2

in1-c

in1-c

Ox092

r1

r1

OxOD4

in1-lo

in1-lo

Ox094

r2

r2

OxOD6

in1-hi

in1-hi

Ox096

r3

r3

OxODB

out2-c

out2-c

Ox09S

r4

r4

OxODA

in2-c

in2-c

Ox09A

r5

r5

OxODC

in2-lo

in2-lo

Ox09C

r6

r6

OxODE

in2-hi

in2-hi

Ox09E

r7

r7

OxOEO

stat-ram

rB

OxOAO

rS

*in1

OxOE2

stat-c

r9

OxOA2

r9

*in2

OxOE4

stat-Io

r10

OxOA4

r10

* stat

OxOE6

stat-hi

r11

OxOA6

r11

'stat#

OxOEB

yeven-Io

r12

OxOAS

r12

circbuf

OxOEA

yeven-hi

r13

OxOAA

r13

OxOEC

yodd-Io

r14

OxOAC

r14

OxOEE

yodd-hi

r15

OxOFO

ypitch

OxOAE

r15

OxOBO

circbuf

literal 0

OxOF2

shift
stat-c

literal 1

OxOF4

vu-Io

*dram1

*dram1

literal 2

OxOF6

vu-hi

*dram2

OxOB6

*dram2

literal 3

OxOFB

vupitch

*dram1 + +

OxOBB

*dram1 + +

literal 4

OxOFA

vpitch

*dram2+ +

OxOBA

*dram2+ +

literal 5

OxOFC

vptr-Io

*dram1- -

OxOBC

*dram1- -

literal 6

OxOFE

vptr-hi

*dram2- -

OxOBE

*dram2- -

literal 7

OxOCO

'out1

prof

OxOB2
OxOB4

1-95

II

inlet

82750PB

Table 3-15. VRAM Pointer RAM Mapping
Byte Address

Description

Name

Ox180
Ox182

Yw-Io
YW-hi

Working Copy of Y Pointer

Ox184
Ox186

out1-lo
out1-hi

Output FIFO 1 Pointer

Ox188

Yw-pitch

Working Copy of Y Pitch
RESERVED

Ox18A
Ox18C
Ox18E

out2-lo
out2-hi

Output FIFO 2 Pointer

Ox190
Ox192

VUw-lo
VUw-hi

Working Copy of VU Pointer

Ox194
Ox196

in1-lo
in1-hi

Input FIFO 1 Pointer

Ox198

VUpitchw

Working Copy of VU Pitch

Ox19A

vpitchw

Working Copy of 82750DB Pitch

Ox19C
Ox19E

in2-lo
in2-hi

Input FIFO 2 Pointer

Ox1AO
Ox1A2

vptrw-Io
vptrw-hi

Working Copy of 82750DB Pointer

Ox1A4
Ox1A6

stat-Io
stat-hi

Working Copy of Statistical Decoder Pointer

Ox1A8
Ox1AA

Yeven-Io
Yeven-hi

Shadow Copy of Y Start Even Pointer

Ox1AC
Ox1AE

Yodd-Io
Yodd-hi

Shadow Copy ofY Start Odd Pointer

Ox1BO

Ypitch

Shadow Copy of Y Pitch

Ox1B2

rfcnt

RFSH Cycles per RFSH Code from 82750DB

Ox1B4
Ox1B6

VU-Io
VU-hi

Shadow Copy of VU Start Pointer

Ox1B8

VUpitch

Shadow Copy of VU Pitch

Ox1BA

vpitch

Shadow Copy of 82750DB Pitch

Ox1BC
Ox1BE

vptr-Io
vptr-hi

Shadow Copy of 82750DB Pointer

NOTE: Register rfont wnte only register and should never be read.

Initializing the 82750PB

leasing RESET #. This is referred to as the INITIAL
state. In the INITIAL state:

The 82750PB is placed in a RESET state by asserting RESET# for at least ten T-cycles. In the RESET
state, which continues until RESET # is released, all
of the 82750PB's outputs are tri-stated for compatibility with board test requirements.

• The microcode processor is halted.

Proper initialization of the 82750PB requires that the
82750PB is held in a RESET state by keeping RESET # active for at least 10 T -cycles, and then re-

• The VRAM interface is ready to service VRAM
requests; however, none of the VRAM pointers
are valid.

• All six interrupts are masked, and the interrupt
latches are cleared.
• The 82750PAl82750PB instruction format select
bit is set to the 82750PA.

1-96

int:eL

82750PB

both as external signals, multiplexed on a single output pin, and as bits in the Processor Status register.
FRZ# is active for each T-cycle when the microcode processor is frozen, waiting for access to
VRAM or to the VRAM Pointer RAM. PMON # can
be toggled by a special ALU opcode or a special B
bus source code. This allows PMON # to be used to
indicate what particular segment of microcode is being execute. The PMON/FRZ bit in the Processor
Control register selects the signal that is being output.

• The number of refresh cycles that will be generated each time a RFSH code is received from the
827500B is set to 14 cycles.
• All bidirectional I/O pins are tristated.
After the 82750PB has been initialized, i.e., placed in
the INITIAL state, but prior to releasing the
827500B's reset signal, the following operations
must be performed:
• Load the REFRESH-CYCLES-PER-LiNE register
with the appropriate value (the equation for the
value is: VALUE = (2 N - 1), where N is the Ilumber of cycles; for example, 5 refresh cycles would
result in VALUE = 25 - 1 = 3110 = 001 F16.
The refresh register is 14 bits wide and the way it
works is to generate one refresh everytime a right
shift results in a '1' bit. It continues the right sifting
until it finds a '0' bit and halts. Hence from programming point of view: 001 F16 = FFOF16 = 5 refresh
cycles per line.
o Load the shadow copies of Y, VU, and 827500B

pointers'and pitches.
• Load the appropriate 827500B Register Load list
into VRAM starting at the address pointed to by
the 827500B pointer.
Prior to releasing the microcode processor from its
HALTed state to run a microcode program, the following operations must be performed: .
• If 82750PB code is to be executed, bit 15 of the
82750PB CONTROL register must be set to a
one.
• Load a microcode program into microcode RAM
on the 82750PB by writing to the three instruction
word registers (meode 1 - the most significant
word of the instruction, meode2,
and
meode3 ~ the least significant word of the instruction, the one containing the next address
field) and then writing to maddr, the address in
microcode RAM where the instruction will be
loaded.

Freezes may indicate that the microcode routine is
not making the most efficient use of the input and
output FIFO buffering. This is particularly important
for the inner loops of graphics and video routines
that are memory-bandwidth limited. Ideally, inner
loops should be balanced so that the rate pixels are
processed is equal to the rate that they can be read
from and written to VRAM with no freezes. The buffering in the input and output FIFOs serve to make
sequential reads and writes to VRAM more efficient
by performing full 54-bit reads and writes, instead of
individual 8-bit or 15-bit accesses. This has the effect of averaging the VRAM read/write rate over a
number of instruction times. For example, if the
82750PB is performing a 54-bit read or write every 8
T-cycles, for an average 018 bits per T-cycle, a two
instruction inner loop could read one 8-bit pixel and
write one 8-bit pixel without any freezes occurring
(assuming the source pixels and the destination pixels are each sequential).
The PMON# provides a more standard performance
monitoring capability by indicating when a particular
segment of microcode, bracketed by special instructions that toggle the PMON# signal, is being executed: This allows either absolute execution-time
measurement or measurement of the fraction of the
total execution time that is required by the segment.
Either the ALU opcode'prof' or the B bus source
code 'prof' will toggle the PMON signal.

• Write to the 82750PB CONTROL register with the
HALT bit (bit 0) set to zero, causing the processor
to start executing an instruction sequence, or with
the SINGLE-STEP bit (bit 1) set to a one (keeping
HALT also set to one), causing the processor to
execute a single instruction.

An external HALT pin is provided on the 82750PB to
allow external debugging hardware to immediately
halt the microcode processor. Activating this input
causes the microcode processor to halt prior to executing the next instruction. When the processor is
halted, the VRAM interface portion of the 82750PB
continues to operate normally, performing transfer
cycles, refresh cycles, and shadow copies as requested by the 827500B.

Performance Monitoring

Host/VRAIVl Timing

Two signals, FRZ# and PMON#, w~ich are useful
for microcode performance monitoring, are available

Figures 3-4 through 3-8 are HostlVRAM Timing Oiagrams.

• Load the PC with the address in microcode RAM
of the first instruction to be executed.

1-97

Diag~ams

82750PB

1
CLK
MREQ#
A[31:3]

Ti

.1 TI

1

T2

.1 TFI 1

Tl. 1 Tl.1

TFl.l

BEiI[3:0J

WE#
NXTFST#

_ _-+1,

1

i!

1

----~lhXr------~--------~IX
!X

_ _-+~\~_____·~I~/r-----~\

O[31:0J
MROY#

I·

.I

Ti

..

1

=====~XC========blxc========b

~----,li-_ _

Ix==
i

I

!

I\
!K
c=

IX

i

----~h\~_________+I----------_4J
I! I
----~h\~_ _ _ _~iIr-----h
\
!

!

c=

I

I

TRNFR#
RFSH#

TFl

"---..~~~~

e

A[2]

Tl ,I TFI 1

------<=~!~ill~!X==!===::>--_t---<~
>
LV-,
(lfrom8l750PBK

'I--...J.(c-D..K..aK-LK':-XO-L>.K\.l.--L.1..LJKwK>-AX..aK'--"\_-L(~KO-L>.K...cKwK~'l.l

\KX\

I

~

to 8l750PB)......h. ..

a:y:y:

KKK K K\

r----------------+--------------------41.
8l750PB VRAM Write Cycle Pair
8l750PB VItAM Read Cycle Pair
(first cyde has one wait ~~te)

(zero wait states for both cycles)

240854-9

NOTES:;
1. Address pin A[2) is always ZERO for the first cycle of a cycle pair and ONE for the second cycle.
2. The two cycles of a cycle pair are both writes or both reads.

Figure 3-4 VRAM Read and Write Cycles

CLK
.. MREQ#
A[31:2]
BE#[~:O]

WE#
NXTFST#
TRNFR#
RFSH#

0[31:0J
MROY#

1 TI 1 Tal 1 Tt'l. 1 Ttxl.1 Tal .I TrfI 1 Tr12.1 Tr12 .1 Trl2.1 Tr12.1 Ti 1
~~~~~~~

_____-,~ i i i

'-------J

i i!

------"

1\

j

\~

ix:=
c=

j

___~__~---~II

----~~~

i

______+_-~----~! ____ ~:!.:~--~--~~--~_c=---(r______

-----------r----~--~I\~

I

)
IXKxxxxxK'l.l

'@

\X\

~~----+_--_+---~r---

IxxxXXl

'@

@

\X\

81750PB VItAM Refresh Cycle
NOTE: the address is held

81750PB VItAM Transfer Cycle
(Transfer Read or Write
de~ndjng on

..

~t~~~~~~~: NO~

state of

WE#signal)

output by 827S0PB; It Ii assumed

that a CAS before BAS refresh
cycle i. generated to the
DRAMIVRAM chips.

240854-10

Figure 3-5. VRAM Transfer and Refresh Cycles

1-98

82750PB

Th

Th

Tc~

TeN

,I

Td

1

Ti

eLK
HREQ#
IIREG#

\

'"

1\

\ \ \\:

/:

HRAM#
HBUSEN#

/ / /

HALEN#

/ / /

/ /

/ /; /

A[J):21

\

BE#[J:OI

WE#
0[3):01
IIROY#

\\

~

--\ \

"~~I'---

WE#
0[3):01
HROY#

Shaded areas indicate
bidircctibnal·signalis
driven by host
240854-11

NOTES:
1. MREQ#, RFSH#, TRNFR#, and NXTFST# remain inactive during Host Register Read and Write cycles.
2. If HALEN # IHREQ # synchronizers are disabled then the second Ti and Tb states will be missing.

Figure 3·6. Host Register Read and Write Cycles

1-99

1

:i"

c(
~

eLK
HREQ#

l'!

10

HREG#

...CCD

HRAM#

tf

HBUSEN#

:"I
::z::

-...
0

11/

m
)C

,

CD
:::J

..... DI

0-

°lll
CD

DI

A[31:2J
BE#[J:OJ

GI
N

WE#

en

D[JI:O]

'V

"'o"
OJ

aDI

:::J

a-

~I

0
'<

MRDY#
HRDY#
Note: HRDY# is only as.'iCrted by 827S0PB if

n

extemnllosic asserts MRDY#.IfMRDY#
is not asserted. HRDY !ltays inactive during

11/

an Extcmal cycle.

ii'

240854-12

NOTES:
1. MREQ#, RFSH# TRNFR#, and NXTFST# remain inactive during Host External Read and Write cycles.
2. If the Synchronizer on HREQ# is disabled, then the second Ti state will be missing.

_.

l
8

TI

TI

eLK
HREQ#

\

I

HREG#

:!!
cc

HRAM#

ID

HBUSEN#

Cf
9'1

HALEN#

...

c:

::E:

0

...

III

.!.
o

.....

<
::u
>
s:
::u
ID
II)

a.

II)

=
a.

:e...
=<=
ID
(')

A[31:2]
BE#[3:0]

CI

WEI

U1
Q

0[31:0]

"OJ

l\)

""-l

MREQ#
MROY#

r......

HROY#

~\

~(

'<
()

iD

III

Note: 827S0PB will stay in Tb for the maximum of:
1) one T-state. OR
2) two T-states after VALEN# goes low.
240854-13

NOTES:
1. RFSH #. TRNFR #. and NXTFST # remain inactive during Host VRAM Read and Write cycles.
2. If the Synchronizers on HREQ# IHALEN# is disabled, then the second Ti state will be missing.

iii

82750PB

4.0 MICROCODE INSTRUCTION
FORMAT
Overview
The 82750PB executes two slightly different instruction formats: one that is backward compatible with
the 82750PA and another that allows full access to
the microcode resources of the 82750PB. The
82750PAl82750PB bit in the 82750PB processor
control register determines which instruction format
is in effect (see Chapter 3). On reset, the 82750PB is
placed in 82750PA instruction format mode. In this
mode the 82750PB will execute binary microcode
originally assembled for the 82750PA in a manner
that is functionally equivalent to the 82750PA.
The following description applies to the 82750PB instruction format. Exact definitions of 82750PB instruction formats and field codings are shown in Figure 4-2 and Table 4-5.

Instruction Sequencing
The instruction word for 82750PB's microcode processor is 48 bits wide. The Microcode RAM holds 512
instructions. Nine bits of each instruction specify the
address of the next instruction to be executed. Each
instruction fetch reads two instructions (of odd address and even address pair) using the upper eight
bits of the 9-bit instruction address. Both the LSB of
the instruction address and a Condition Flag bit, selected from eight possible branching conditions, are
used to determine whether the next instruction to be
executed is the even address instruction or odd address instruction, according to the logic table shown
as Table 4-1.
Table 4-1. Microcode Next Instruction Selection
LSBof
Address

Condition
Flag State

Next
Instruction

0

o (FALSE)

EVEN

0

1 (TRUE)

EVEN

1

o (FALSE)

ODD

1

1 (TRUE)

EVEN

For an unconditional branch, the condition flag
FALSE (which is always zero) is selected; this causes the LSB of the address to be passed through to
select the next instruction: LSB = 0 selects EVEN
and LSB = 1 selects ODD. This allows unconditional branching to any of the 512 instructions in the
RAM. For a conditional branch, the LSB of the address is set to a one; this causes the state of the
condition flag to select the next instruction: FALSE
selects the ODD instruction and TRUE selects the
EVEN instruction. Therefore, a conditional branch
jumps to either the odd or even instruction of an
odd/even pair depending on the state of the condition.

Instruction Word Field Descriptions
Each field of the microcode instruction format is described in the following sections.
NADDR-NEXT INSTRUCTION ADDRESS FIELD

This field holds the address of the next instruction to
be .executed. Taking advantage of the fact that the
microcode RAM is physically organized as 256 deep
by 96 wide (two instructions are fetched per read
cycle), a zero delay two-way branch can be
achieved. The only case in which this field is not
used to determine the address of the next instruction to be executed is when an instruction writes to
the PC. (The term PC refers to the register that holds
the address of the next instruction to be executed.)
When an instruction loads the PC a one instruction
delay occurs before the load takes effect. Therefore,
the instruction pointed to by the next instruction field
of the instruction that loads the PC is executed before the jump to the new address occurs. This is
shown in Table 4-2.
There are no restrictions on the instruction following
a PC load; it will always be executed, even while
single stepping the processor or if the processor is
frozen on that instruction.
CFSEL-CONDITION FLAG SELECT FIELD

This field selects which condition flag will be used
with the LSB of NADDR to select the next instruction
from the odd/even pair. The condition flag assignment is given in Table 4-3.

1-102

82750PB

Table 4-2. PC Load Example
Addr

Instruction

NADDR

10

pc = 0

55

Load PC with zero.

55

rO = 1

X

This instruction is executed but its next
address field is ignored.

0

r1 = rO

25

PC load takes effect after a one instructon delay,
the result is that r1 = rO = 1.

Comments

Table 4-3. Condition Flag Select Field Assignments
Value

Flag

000

FALSE

Select for Unconditional Branch

001

CARRY

Carry Out from ALU Condition Flag Latch

010

OVF

Overflow from ALU Condition Flag Latch

011

SIGN

Sign from ALU Condition Flag Latch

Description

100

ZERO

Zero from ALU Condition Flag Latch

101

LCNTZ

TRUE if Selected Loop Counter = 0

110

LSB

LSB of Data Register rO

111

MSB

MSB of Data Register rO

NOTE:
The ALU condition flags (CARRY, OVF, SIGN, and ZERO) are latched in the ALU Condition Flag register. This register is
updated for most-but not all-ALU operations. The remaining flags (LCNTZ, LSB, and MSB) are updated and latched each
cycle.

ASRC-A BUS SOURCE SELECT FIELD

CNT-DECREMENT LOOP COUNTER BIT

This field selects the element that should drive its
data onto the A bus during the execution of this instruction. The mapping for this and the following
three fields is provided in Chapter 6.

A one in this bit position causes the selected Loop
Counter (selected by LC,.the loop counter select bit)
to be decremented. The new value of the loop counter and the updated LeNTZ condition flag are not
ready until the next instruction cycle. Therefore, in a
loop where the loop counter is decremented and
tested for zero in the same instruction (typically in a
one instruction loop), the start value for the loop
counter should be one less than the number of times
the loop should be executed.

ADST-A BUS DESTINATION SELECT FIELD
This field selects which element should latch data
from the A bus during the execution of this instruction. See ASRC above.

LIT-LITERAL SELECT BIT

BSRC-B BUS SOURCE SELECT FIELD

When this bit is a one, the ASRC and CFSEL fields
are replaced with a 9-bit literal value that is driven as
a source in the least significant 9 bits of the A bus. In
this case, the upper 7 bits of the A bus are forced to
zeros. The mapping of bits from the literal field to the
A bus is shown in Figure 4-1.

Same as ASRC, but for B bus. See ASRC above.
BDST-B BUS DESTINATION SELECT FIELD
Same as ADST, but for B bus. See ADST above.

NOTE
A conditional branch and a literal on the A bus are
not allowed in the same instruction. A 3-bit literal
can be placed on the B bus in any instruction.

1-103

·an'el®
+_1
A bus bits
Inst. Word Bits
ASRG Field
CFSEL Field

82750PB

15

14

13

12

·11

10

'*- - - - - - Forced to Zero - - - -

9
~

8

7

6

5

4

17
'*-

16

15

14

13

3

2

12

11

o
10

9

~

'*- --

~

Figure 4-1. Literal Field Mapping onto a Bus

on either bit causes the corresponding latch to hold
its current content. This allows the ALU operands
either to come from "eavesdropping" on the A or B
bus transfers occurring in the current instruction cycle or to be held for multiple instruction cycles in
either the A or B input latch.

SHFT-SHIFT CONTROL FIELD

This field controls the bit shifting and byte swapping
logic associated with register rO. The encoding of
this field is given in Table 4-4.
Table 4-4. SHIFT Control Field Coding
SHFT

Operation

00

No Shift or Swap Operation

01

Shift rO Right One Bit
Position, Sign Extend

10

Shift rO Left One Bit
Position, Zero Fill

11

Byte Swap the Value
Being Loaded into rO°

ALUOP-ALU OPERATION CODE FIELD

*Byte swapping only works when ro is the destination on the
A bus or the B bus. It does not swap data held in ro, only data
being loaded. In order to byte swap data in register ro, ro
must be both a source and destination for either the A or B
bus.

ALUSS-ALUSOURCE SELECT BITS

These two bits are used as enables for the two ALU
input latches. Bit 39 enables the latch that connects
to the A bus; bit 38 enables the latch connected to
the B bus. A one in either bit position causes the
corresponding input latch to latch the value on the
bus to which it is connected (the A or B bus). A zero

This field specifies the ALU instruction to be· performed during the current instruction cycle. The encoding of this field is given in Figure 4-2. Normally, at
the end of the instruction execution, the result of the
ALU operation is latched in the ALU output latch that
can be a source on either the A or B buses. However, if a Nap is selected for the ALU operation, the
ALU output latch is not latched. The data is held
from the previous instruction. In addition to Nap,
certain other ALU opcodes do not actually perform
ALU operations and therefore, do not latch the ALU
results. They are INT (microcode interrupt) and the
PROF instruction.
LC-LOOP COUNTER SELECT BIT

This bit selects which of the two loop counters is to
be used for decrementing or Loop-Gounter-Zero
conditional branching in the current instruction. A
zero selects loop counter zero and a one selects
loop counter one.
Refer to the Intel 82750PB Microcode Programming
Guide for more information on microcode programming.

1-104

82750PB

Table 4-5. 82750PB Source/Destination Coding
Address (Hex)

BDST

BSRC

OxO

Null

Null
alu

hwid

"dram3

"dram3

cc

Ox3

"dram4

*dram4

Ox4

*dram3+ +

*dram3+ +

Ox5

*dram4+ +

"dram4+ +

cnt

cnt

Ox6

*dram3- -

*dram3- -

cnt2

cnt2

Ox7

*dram4- -

*dram4- -

.Icnt

Icnt

OxB

rO

rO

rO

rO

Ox9

-r1

r1

r1

r1

OxA

r2

r2

r2

r2

Ox1
Ox2

\

ADST

ASRC

Null

Null

maddr
alu

OxB

r3

r3

r3

r3

OxC

r4·

r4

r4

r4

OxD

r5

r5

r5

r5

OxE

r6

r6

r6

r6

OxF

r7

r7

r7

r7

Ox10

rB

*in1

mcode3

mcode3

Ox11

r9

*in2

mcode2

mcode2

Ox12

. r10

"stat

mcode1

mcode1
pc

Ox13

r11

'stat#

pc

Ox14

r12

circbuf

pixint-c

Ox15

r13

pixint

pixint

Ox16

r14

"dram1

'dram1

Ox17

r15

Ox1B

circbuf

Ox19

'dram2

"dram2

literal 0

'dram1 + +

'dram1 + +

literal 1

'dram2+ +

'dram2+ +

Ox1A

*dram1

literal 2

'dram1- -

'dram1- -

Ox1B

*dram2

literal 3

'dram2- -

'dram2- -

Ox1C

*dram1 + +

literal 4

dram1

dram1

Ox1D

'dram2+

+

literal 5

dram2

dram2

Ox1E

*dram1- -

literal 6

dram3

dram3

Ox1F

*dram2- -

literal 7

dram4

dram4

Ox20

'out1

prof

'out1

. 'in1

1-106

intel~

82750PB

Table 4·5. 82750PB Source/Destination Coding (Continued)
Address (Hex)

BDST

Ox21

out1 + +

Ox22

out1-lo

Ox23
Ox24
Ox25
Ox26

BSRC

ADST

ASRC

out1 + +

"in2

out1-lo

shift-rl

"stat

out1-hi

out1-hi

out1-hi

"stat#

"out2

stat-Io

"out2

out2+ +

stat-hi

out2+ +

out2-lo

out2-lo

shift-r

Ox27

out2-hi

out2-hi

out2-hi

Ox2B

out1-c

out1-c

out1-c

Ox29

in1-c

in1-c

in1-c

Ox2A

in1-lo

in1-lo

shift-I

Ox2B

in1-hi

in1-hi

in1-hi

Ox2C

out2-c

out2-c

out2-c
in2-c

Ox2D

in2-c

in2-c

Ox2E

in2-lo

in2-lo

Ox2F

in2-hi

in2-hi

in2-hi

Ox30

stat-ram

ra

ra

ra

Ox31

stat-c

r9

r9

r9

Ox32

stat-Io

r10

r10

r10

Ox33

stat-hi

r11

r11

r11

Ox34

yeven-Io

r12

r12

r12

Ox35

yeven-hi

r13

r13

r13

Ox36

yodd-Io

r14

r14

r14

Ox37

yodd-hi

r15

r15

r15

Ox3a

ypitch

Ox39

shift

cc

shift

stat-c

fent

fent

Ox3A

vu-Io

*dram1

*dram3

*dram3

Ox3B

vU-hi

*dram2

*dram4

*dram4

Ox3C

vupitch

*dram1 + +

*dram3+ +

*dram3+ +

Ox3D

vpitch

*dram2+ +

*dram4+ +

*dram4+ +

Ox3E

vptr-Io

*dram1- -

*dram3- -

*dram3- -

Ox3F

vptr-hi

*dram2- -

*dram4- -

*dram4- -

1-107

82750PB

47

bit
coding

OxO
Oxl

~
Ox3
0X4
--::-:--

~
Ox6

OX?
0X'il
~

15
LC
SEL
1
cnt

cnt2

46

45

44

43

14
13
SHFT
CNTL
2
nop
shftr
shfll
swap

12

11

42

41

9
10
ALU
OPCODE
5
NOP
ZERO
a
b
-a
-b

40
39
38
meode 1
7
8
6
ALU
SS
2
hold
latb
tat a
both

37

38

35

34

3

2

5

4

LIT

CNT

1
nop
lit

1
nop
doc

~
axc

""""OXil
'--axE
~

r--oxw
: Oxl1

~
Ox13

I-oxi4

&
-&
&++

-I

- <

~

r--ox;-o
Iox2o

30

29

15

14

13

26
28
27
mcode2
12
11
10
8 Bus
Source
6
null
alu

'dram3
'dram4

·dramS + +
'dram4 + +
'dramS

'dram4
rO

",2

",2

r3

,3
,4
,5
,6
,7
'in1
'1n2

r9

+

,,0

'stat

a
-b

'11
,12
,13

'stat#

: OxlE
OxlF

~
Ox19

31

,0

,7
,8.

-

+ <
. +J
J

Ox17

null

r6

: Ox18
Ox1C

i

1
0
B Bus
Oesttnstion
6

,4
,5

+ <
+

a+ +
b+ +
ab
int
prof
a'
b'

: Ox15
Ox16

32

'dram3
'dram4
'dram3 + +
'dram4 + +
'dram3
'dram4

""""""OxA"""

--;:-::-

33

circbuf

'14
,15
circbuf

literatO
literal 1

'dff;lml
'dram2

literal 2
literal 3

'dram1 + +

literal 4
literalS
literale
literal 7

'dram2 + +
'dram1

'dram2
'outl

~
Ox22

out1

prof

++

out1 10
0011 hi
'out2
out2 + +
ou12 10
oul2 hi
outl
c
in1
c
in1 10
in1 - hi

~

~
Ox25

0X2'6

~
0x28
~

~
Ox28
r--oFc-

oul2 - c
in2 c
in2
10
in2
hi
stat ,am
stat c
stal 10
stat hi
yeven 10
yaven hi
yodd - 10
yodd hi
ypitch

~
Ox2E

fox2F
: Ox30
Ox31

f-ox32

: Ox33
Ox34

r-oxss

I~
Ox37

~

out1

10
hi
stat·lo
stat·hi
oul2 10
ou12 hi
outl
c
in1
c
in1
10

outl

in1 - hi
ou12
in2
in2
1n2 ,8
,9

'10
,11
,12
,13
,14
,15
shiH
stat

~
Ox3A

vu

10

0x3il
0X3C
~

vu - hi
vupilch
vpitch
vplr 10

~

vpt,

~

Figure 4·2, 82750PB Instruction Word Format
1-108

hi

c
c
10
hi

c
-dram1
·dram2
-dram1 + +
·dram2 + +
·dram1
·dram2

25

24

9

8

int:eL
23

82750PB

22

21

20

19

18

17

meade 2
7

bit

coding
OxO

6

5

4

3

ABus
Destination

2

1

I
I
o I

16

14

15

13

12

11

10

14

15

13

A Bus
Source

12

11

10

6

3

null

FALSE
CARRY

cc

OVERFLOW

moddr
alu

ZERO

Ox5

cnl

cnt

CNTO

Ox6

cnt2

cnt2

LS8rD

Ox7

lcnt

lent

MS8rD

Ox8

rO

rD

Ox9

rl

rl

OxA

r2

r2

Ox8

(.J

(.J

OxC

r4

r4

OxD

r5

r5

OxE

r6

rS

OxF

r7

r7

Oxl0

mcode3

mcode3

Ox11

mcode2
meade1

meade1

pc
pixint - c

pc

Ox14

pixint

pixin!

Ox16

'~ram1

Ox17

'dram2

'dram1
'dram2
'dram1 + +
*dram2 + +
'dram1 --

'dram1
'dram2

+ +
+ +

'dram1

Ox18

'dram2 - -

*dram2 --

OxiC

draml

Ox10

dram1
dram2

OxlE

dram3

dram3

OxlF

dram4

0)(20

'out1
oun + +

dram4
'in1
'i02
'stat
'stat#

Ox21
Ox22

0)(23
0)(24

'out2

0)(25

out2 + +

Ox26

shift - r

Ox27

out2 - hi

Ox28

outl - c

Ox29

in1 - c

Ox28

shih -I
in1
hi

Ox2C

out2 - c

Ox2D

in2 - c

6

5

3

2

1

0

9

8

4

3

2

1

0

Next

dram2

shift - rI
hi
outl

Ox2A

7

4

mcode2

0)(15

Ox19
OxlA

5

SIGN

Ox4

Ox16

6

9

6
null

hwid

Ox13

7

Address

Ox2

Ox12

8

Cond Flag
Select

Oxl
Ox3

9

meade 3

Ox2E
Ox2F

0)(30

in2 - hi
r8

r8

0)(31

r9

r9

Ox32

riO

riO

Ox33

rl1

rll

0)(34

r12

r12

0)(35

r13

r13

0)(36

r14

r14

Ox37

r15

r15

Ox38

cc

shift
fent

0)(39

tent

Ox3A

'dram3

Ox38

'dram4
'dram3 +
'dram4 +
'dram3
'dram4 -

Ox3e
Ox30
Ox3E

Ox3F

'drama

+
+

'dram4
'dram3 + +
'dram4 + +
'dram3
'dram4

-

Figure 4-2. 82750PB Instruction Word Format (Continued)
1-109

"

82750PB

Exposure to Maximum Ratings may affect device re~
liability. Furthermore, although the 82750PB con·
tains protective circuitry to resist damage from static
electrical discharge, always take precautions to
avoid high static voltages or electric fields.

5.0 ELECTRICAL DATA
Maximum Ratings
Table 5·1 is a stress rating only, and functional operation
at the maximums is not guaranteed. Functional operat·
ing conditions are given in the DC and AC Characteris·
tics (Tables 5·2, 5·3, 5·4, and 5·5).

DC Characteristics
Table 5-1. Absolute Maximum Requirements
Condition

Maximum Requirement

Case Temparature under Bias

to 110°C

Storage Temperature

to 150°C

Voltage on Any Pin with Respect to Ground

to Vee + 0.5V

Supply Voltage with Respect to Vss

V to + 6.5V

Table 5·2. DC Characteristics
Symbol

=

Parameter

O°C to 90°C
Unit

Notes

Input lOW Voltage

V

(Note 1)

Input HIGH Voltage

V

(Note 1)

Output lOW Voltage

V

IOL = 4.0 mAP)

V

IOH = -'1.0 mAP)

8.HP

150

+10

IlA

VSs<"iN

1.31 <.Bl2) -I
S.2/i1 <.SSS)

t-

=..

D4/E4--....:ot

I~.~I"=-.~211J:::--:"(~.S=-:::9~8':'"")®:::::M~I~cI~A~®=:---=B~®~IO:-:O=®IInvm.

DETAIL

DETAIL L

J

8 CEQ.
" CEG.
240854-28

mm (inch)

Figure 6-S.132-Lead PQFP Mechanical Package.Detail-Typical Lead

1-117

82750PB

NOTES.
AlL DII'£NSIONS AKl TOlERANCES CoPf"ORH TO ANSI Y14.Sf1-1982
oATI.I1 PLAAE gg LOCATED AT TI€ P10lD PARTING LItE AI'()
COIIoCIDENT 11TH THE BOTTOt1 ~ TI€ LEAD MRE LEAD EXITS PLASTIC BODY
DATI.I1S (!;II AI'() g:a
TO BE DET~ltED MAE CENTER LEADS EXIT
PLASTIC BOOYAT OA~ PLAtE 6B3
.
CONTROLLING DII'£NSION,· lloCH
Oll'ENSlciNs 01, 02, El AI'() E2 AIlE I'EA8UI£0 AT TI€ P1Ol0 PARTING LItE.
01 AKl El 00 NOT 1r«:L1AlE AN ALLOIABLE P1Ol0 PROTRUSION ~ '.18 ""
<.!J!7 !N)

PE.q

eI~.

02 A."!)

0

CO t«)T tt«:L\AJE A TOTAL ALLOIiIA8LE

P1Olo PROTRUSION r7 '.18"" <..,7 IN) AT I'1AXI/'U'I PACKAGE SIZE.

&

PIN 1 IDENTIFIER IS LOCATED 'ITHIN atE

~ TI€ TIO ZatES II'()ICATEO

240854-29

1-118

82750PB
TA (the ambient temperature) can be calculated
from eCA (thermal resistance from case to ambient)
with the following equation:

Package Thermal Specifications
The 82750PB is specified for operation when TG
(the case temperature) is within the range of O·G to
90·G. TG may be measl.lred in any environment to
determine whether the 82750PB is within specified
operation range. The case temperature should be
measured at the center of the top surface.

TA = Tc

-

P • ()CA

Typical values for eGA at various airflows are given
in Table 6-3 for the 132-lead PQFP package. Table
6-4 shows the maximum TA allowable (wihout ex-,
ceeding Td at various airflows. The power dissipation (P) is calculated by using the typical supply current at 5V as shown in Table 5-2.

Table 6·3. Thermal Resistance ("C/W)
eCA

Versus Airflow-ft/mln (m/sec)

Package

0
(0)

200
(1.01)

400
(2.03)

600
(3.04)

800
(4.06)

1000
(5.07)

132-Lead
PQFP

26.0

17.5

14.0

11.5

9.5

8.5

Table 6·4 Ma'ximum T A at Various Airflows (·C)
TA Versus Airflow-ft/min (m/sec)
Package

Frequency
(MHz)

0
(0)

200
(1.01)

400
(2.03)

600
(3.04)

800
(4.06)

1000
(5.07)

132-Lead
PQFP

25

70

76

80

81

83

84

1-119

i860™ Microprocessor Family

2

II

i860™ XP MICROPROCESSOR
•

Parallel Architecture that Supports Up
to Three Operations per Clock
- One Integer or Control Instruction
- Up to Two Floating-Point Results

•

High Performance Design
- 40/50 MHz Clock Rate
-100 Peak Single Precision MFLOPS
- 75 Peak Double Precision MFLOPS
- 64-Bit External Data Bus
- 64-Bit Internal Code Bus
-128-Bit Internal Data Bus

•

High Integration on One Chip
- 32-Bit Integer and Control Unit
- 32/64-Bit Pipelined Floating-Point
- 64-Bit 3-D Graphics Unit
- Paging Unit with 64 Four-Kbyte and
16 Four-Mbyte Pages
- 16 Kbyte Code Cache
- 16 Kbyte Data Cache

•

Compatible with Industry Standards
- ANSIIIEEE Standard 754-1985 for
Binary Floating-Point Arithmetic
-Intel 386™lintei 486™/i860TM Data
Formats and Page Table Entries
- Binary Compatible with i860™ XR
Applications Instruction Set
- Detached Concurrency Control Unit
(CCU) Supports Parallel Architecture
Extensions (PAX)
- JEDEC 262-pin Ceramic Pin Grid
Array Package
-IEEE Standard 1149.1/06 BoundaryScan Architecture

ill Easy to Use

- On-Chip Debug Register
-UNIX'/860
- APX Attached Processor Executive
- Assembler, Linker, Simulator,
Debugger, C and FORTRAN
Compilers, FORTRAN Vectorizer,
Scalar and Vector Math Libraries
- Graphics Libraries

113 Fast, Multiprocessor-Oriented Bus
- Burst Cycles Move 400 Mbyte/Sec
- Hardware Cache Snooping
- MESI Cache Consistency Protocol
- Supports Second-Level Cache
- Supports DRAM

The Intel i860 XP Microprocessor (order code A80860XP) delivers supercomputing performance in a single
VLSI component. The 32/64-bit architecture of the i860 XP microprocessor balances integer, floating point,
and graphics performance for applications such as engineering workstations, scientific computing, 3-D graphics workstations, and multiuser systems. Its parallel architecture achieves high throughput with RiSe design
techniques, multiprocessor. support, pipelined processing units, wide data paths, large on-chip caches, 2.5
million transistor design, and fast O.8-micron silicon technology.
A51- A3

D63 - DO CONTROL

240874-1

Figure 0.1. Block Diagram

'UNIX is a registered trademark of UNIX System Laboratories, Inc.
Intel, i860, Intel386 and Intel486 are trademarks of Intel Corporation.
2-1

November 1991
Order Number: 240874-002

i860™ XP MICROPROCESSOR

CONTENTS

CONTENTS

PAGE
2.4.4.6 Accessed and Dirty
Bits .......................... 2-26
2.4.4.7 Page Tables for Trap
Handlers ..................... 2-26
2.4.4.8 Combining Protection of
Both Levels of Page Tables ... 2-26
2.4.5 Address Translation
Algorithm ....................... 2-26
2.4.6 Address Translation Faults ... 2-27
2.5 Detached CCU ................... 2-27
2.5.1 DCCU Initialization ........... 2-27
2.5.2 DCCU Addressing ........... 2-27
2.5.3 DCCU Internals .............. 2-28
2.6 Instruction Set .................... 2-28
2.6.1 Pipe lined and Scalar
Operations ...................... 2-30
2.6.1.1 Scalar Mode ............ 2-31
2.6.1.2 Pipelining Status
Information ................... 2-31
2.6.1.3 Precision in the
Pipelines ..................... 2-31
2.6.1.4 Transition between
Scalar and Pipe lined
Operations ................... 2-31
2.6.1.5 Pipelined Loads ......... 2-32
2.6.2 Dual-Instruction Mode ....... 2-32
2.6.3 Dual-Operation Instructions .. 2-33
2.7 Addressing Modes ................ 2-34
2.8 Traps and Interrupts .............. 2-34
2.8.1 Trap Handler Invocation ..... 2-34
2.8.2 Instruction Fault ............. 2-34
2.8.2.1 Lock Protocol ........... 2-35
2.8.2.2 Using PT and P! Bits .... 2-35
2.8.3 Floating-Point Fault .......... 2-36
2.8.3.1 Source Exception
Faults ........................ 2-36
2.8.3.2 Result Exception
Faults ........................ 2-36 .
2.8.4 Instruction Access Fault ..... 2-37
2.8.5 Data Access Fault ........... 2-37
2.8.6 Parity Error Trap ............. 2-38
2.8.7 Bus Error Trap ............... 2-38

PAGE

1.0 FUNCTIONAL DESCRIPTION ........ 2-9

2.0 PROGRAMMING INTERFACE ...... 2-10
2.1 Data Types ....................... 2-10
2.1.1 Integer ...................... 2-10
2.1.2 Ordinal ...................... 2-10
2.1 .3 Single- and Double-Precision
Real .................... i . • . • . • . 2-10
2.1.4 Pixel ......................... 2-11
2.2 Register Set ...................... 2-12
2.2.1 Integer Register File ......... 2-12
2.2.2 Fioating-Point Register Fiie .. 2-12
2.2.3 Processor Status Register ... 2-12
2.2.4 Extended Processor Status
Register ........................ 2-14
2.2.5 Data Breakpoint Register .... 2-16
2.2.6 Directory Base Register ...... 2-16
2.2.7 Fault Instruction Register .... 2-17
2.2.8 Floating-Point Status
Register ........................ 2-17
2.2.9 KR, KI, T, and MERGE
Registers ....................... 2-19
2.2.10 Bus Error Address
Register ........................ 2-20
2.2.11 Privileged Registers ........ 2-20
2.2.12 Concurrency Control
Register ........................ 2-20
2.2.13 NEWCURR Register ........ 2-21
2.2.14 STAT Register .............. 2-21
2.3 Addressing ....................... 2-21
2.4 Virtual Addressing ................ 2-22
2.4.1 Page Frame ................. 2-22
2.4.2 Virtual Address .............. 2-23
2.4.3 Page Tables ................. 2-23
2.4.4 Page-Table Entries .......... 2-24
2.4.4.1 Page Frame Address .... 2-24
2.4.4.2 Present Bit .............. 2-25
2.4.4.3 Writable and User Bits .. 2-25
2.4.4.4 Write-Through Bit ....... 2-25
2.4.4.5 Cache Disable Bit ....... 2-25

2-2

CONTENTS

CONTENTS

PAGE
2.8.8 InterruptTrap ................ 2-38
2.8.9 Reset Trap .................. 2-38
2.9 Debugging ........................ 2-38

PAGE
4.2.11 ClK (Clock) ................ 2-51
4.2.12 CTYP (Cycle Type) ......... 2-52
4.2.13 D/C# (Data/Code) ......... 2-52
4.2.14 D63-DO (Data Pins) ........ 2-52
4.2.15 DP7 - DPO (Data Parity) ..... 2-52
4.2.16 EADS # (External Address
Status) .......................... 2-52
4.2.17 EWBE # (External Write
Buffer Empty) ................... 2-52
4.2.18 FLiNE # (Flush Line) ........ 2-52
4.2.19 HIT # (Cache Inquiry Hit) .... 2-53

3.0 ON-CHIP CACHES .................. 2-39

3.1 Address Translation Caches ......
3.2 Internal Instruction and Data
Caches ............................
3.2.1 Data Cache ..................
3.2.1.1 Data Cache Update
Policies ......................
3.2.2 Instruction Cache ............
3.2.3 Cache Replacement
Algorithm .......................
3.2.4 Cache Consistency
Protocol ........................
3.2.4.1 Data Cache States ......
3.2.4.2 Write-Once Policy .......
3.2.4.3 Locked Access .........
3.3 Internal Cache Consistency .......
3.3.1 Address Space
Consistency ....................
3.3.2 Instruction Cache
Consistency ....................
3.3.3 Page Table Consistency .....
3.3.4 Consistency of
Cacheability .....................
3.3.5 load Pipe Consistency .......
3.3.6 Summary ....................

2-39
2-41
2-42
2-42
2-43

4tFn~)H.I:.~.~.~~~t.~~~~f.i~~......... 2-53

2-43

4.2.21 HlDA (Bus Hold
Acknowledge) ...................
4.2.22 HOLD (Bus Hold) ...........
4.2.23 INV (Invalidate) .............
4.2.24 INT /CS8 (Interrupt/CodeSize Eight Bits) ..................

2-43
2-43
2-44
2-44
2-45

4.2.25 KBO, KB1 (Cache Block) ....
4.2.26 KEN # (Cache Enable) ., ....
4.2.27 lEN (Data length) ..........
4.2.28 lOCK# (Address lock) ....
4.2.29 M/IO# (Memory-I/O) .......
4.2.30 NA # (Next Address
Request) ........................
4.2.31 NENE# (Next Near) ........
4.2.32 PCD (Page Cache
Disable) .........................
4.2.33 PCHK # (Parity Check) ......
4.2.34 PCYC (Page Cycle) .........
4.2.35 PEN # (Parity Enable) .......

2-45
2-46
2-46
2-47
2-47
2-47

4.0 HARDWARE INTERFACE .......... 2-47
4.1 Pins Overview ....................
4.2 Signal Description ................
4.2.1 A31-A3 (Address Pins) ......
4.2.2 ADS # (Address Status) ......
4.2.3 AHOlD (Address Hold) ......
4.2.4 BE7#-BEO#
(Byte Enables) ..................
4.2.5 BERR (Bus Error) ............
4.2.6 BOFF # (Back-Off) ...........
4.2.7 BRDY # (Burst Ready) .......
4.2.8 BREQ (Bus Request) ........
4.2.9 BYPASS# (Bypass) .........
4.2.10 CACHE# (Cacheability) ....

2·47
2-50
2-50

4.2.36 PWT (Page
Write-Through) ..................
4.2.37 RESET (System Reset) .....
4.2.38 RSRVD, SPARE ............
4.2.39 TCK (Test Clock) ...........
4:2.40 TDI (Test Data Input) .......
4.2.41 TDO (Test Data Output) ....
4.2.42 TMS (Test Mode Select) ....
4.2.43 TRST# (Test Reset) .......
4.2.44 Vcc (System Power) and Vss
(Ground) ........................
4.2.45 VccClK (Clock Power) ......

2-50
2-50
2-50
2-50
2-50
2-51
2-51
2-51
2-51

2-3

2-53
2-53
2-53
2-53
2-54
2-54
2-54
2-54
2-55
2-55
2-55
2-55
2-55
2-56
2-56
2-56
2-56
2-56

2c 56
2-56
2-56
2-57
2-57
2-57
2-57

II

CONTENTS

CONTENTS

PAGE

PAGE

4.2.46 WB/WT # (Write-Back/
Write-Through) .................. 2-57

5.5 RESET Initialization ............... 2-86

4.2.47W/R# (Write/Read) ........ 2-57

6.0 TESTABILITy ....................... 2-87
6.1 Test Architecture ................. 2-87
6.2 Test Data Registers .............. 2-87
6.3 Instruction Register ............... 2-88
6.4 TAP Controller .................... 2-89
6.4.1 Test-Logic-Reset State ...... 2-89
6.4.2 Run-Test/Idle State .......... 2-90
6.4.3 Select-OR-Scan State ....... 2-90
6.4.4 Select-IR-Scan State ........ 2-91
6.4.5 Capture-DR State ............ 2-91
6.4.6 Shift-DR State ............... 2-91
6.4.7 Exit1-DR State ............... 2-91
6.4.8 Pause-DR State ............. 2-91
6.4.9 Exit2-DR State ............... 2-91
6.4.1 o Update-DR State ........... 2-91
6.4.11 Capture-IR State ........... 2-91
6.4.12Shift-IR State ............... 2-92
6.4.13 Exit1-IR State .............. 2-92
6.4.14 Pause-IR State ............. 2-92
6.4.15 Exit2-IR State .............. 2-92
6.4.16 Update-IR State ............ 2-92
6.5 Boundary Scan Register Cell
Ordering ........................... 2-92
6.6 TAP Controller Initialization ....... 2-94

5.0 BUS OPERATION ................... 2-57
5.1 Bus Cycles ....................... 2-57
5.1.1 Single-Transfer Cycle ........ 2-58
5.1.2 Burst Cycles ................. 2-58
5.1.3 Pipelined Cycles ............. 2-61
5.1.4 Interrupt Acknowledge
Cycles .......................... 2-63
5.1.5 Special Bus Cycles .......... 2-64
5.2 Bus Arbitration .................... 2-65
5.2.1 HOLD and HLDA
Arbitration ...................... 2-65
5.2.2 Bus Cycle Back-Off and
Restart ......................... 2-66
5.2.2.1 Cycle Back-Off .......... 2-66
5.2.2.2 Cycle Restart ...... , .... 2-67
5.2.2.3 Late Back-Off Modes ... 2-67
5.2.2.4 One-Clock Late Back-Off
Mode ........................ 2-67
5.2.2.5 Two-Clock Late Back-Off
Mode ........................ 2-69
5.3 Cache Inquiry Cycles
(Snooping) ............. , ........... 2-71
5.3.1 Inquiry Write-Back Cycles .... 2-73
5.3.2 Snooping Responsibility
Limits ........ , .................. 2-75

7.0 MECHANICAL DATA ............... 2-94

5.3.2.1 Inquiry for a Line Being
Cached ...................... 2-75

8.0 PACKAGE THERMAL
SPECiFiCATIONS ................... 2-102

5.3.2.2 Inquiry for a Line Being
Replaced .................... 2-77

9.0 ELECTRICAL DATA ............... 2-103
9.1 Absolute Maximum Ratings ...... 2-104
9.2 D.C. Characteristics ............. 2-104
9.3 A.C. Characteristics ............. 2-105
9.4 Component Buffer Model ........ 2-111
9.4.1 First Order Electrical Buffer
Model ......................... 2-111
9.4.2 First Order Electrical Model
Parameter Values .............. 2-111
9.4.3 Package Parameters ........ 2-111
9.4.4 Board.1 nterconnects ........ 2-112

5.3.3 Write Cycle Reordering Due to
Buffering ........................ 2-79
5.3.4 Strong Ordering Mode ....... 2-80
5.3.5 Scheduling Inquiry Write-Back
Cycles .......................... 2-81
5.3.5.1 Choosing between
FLlNE# and BOFF# ......... 2-81
5.3.5.2 Reordering Write-Backs
with FLlNE# ................. 2-82
5.3.5.3 Reordering Write-Backs
with BOFF # ................. 2-84
5.4 The LOCK # Cycle Attribute ....... 2-84

2-4

CONTENTS

CONTENTS

PAGE

PAGE

10.4 Instruction Characteristics ...... 2-142

10.0 INSTRUCTION SET .............. 2-120
10.1 Instruction Definitions in
Alphabetical Order ................ 2-121

10.5 Software Compatibility .......... 2-145
10.5.1 Required Changes ........ 2-145
10.5.2 Performance
Optimizations .................. 2-145

10.2 Instruction Format and
Encoding ......................... 2-130
10.2.1 REG-Format Instructions .. 2-130

10.5.3 New Features ............. 2-146
10.5.4 Notes ..................... 2-146

10.2.2 CTRL-Format
Instructions .................... 2-133

11.0 REVISION HISTORY ............. 2-146

10.2.3 Floating-Point Instruction
Encoding ...................... 2-133

INDEX .. ............................... 2-147

10.3 Instruction Timings ............. 2-136

2-5

CONTENTS

CONTENTS

PAGE

Figure 5.6

FIGURES
Figure 0.1'
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5

Block Diagram .............. 2-1
Real Number Formats ....... 2-11
Pixel Format Example .... "... 2-12
Registers and Data Paths ... 2-13
Processor Status Register ... 2-14
Extended Processor Status
Register ; ................... 2-15
Figure 2.6 Directory Base Register ..... 2-16
Figure 2.7 Floating-Point Status
Register .................... 2-18
Figure 2.8 Concurrency Control
Register .................... 2-20
Figure 2.9 . Concurrency Status
Register .................... 2-21
Figure 2.10 Little and Big Endian Memory
Transfers ................... 2-22
Figure 2.11 Formats of Virtual
Addresses .................. 2-23
Figure 2.12 Address Translation ......... 2-23
Figure 2.13 Formats of Page Table
Entries ...................... 2-24
Figure 2.14 Pipelined Instruction
Execution ................... 2-30
Figure 2.15 Dual-Instruction Mode
Transitions (1 of 2) .......... 2-32
Figure 2.15 Dual-Instruction Mode
Transitions (2 of 2) .......... 2-32
Figure 2.16 Dual-Operation Data
Paths ....................... 2-33
Figure 3.1 4K TLB Organization ........ 2-40
Figure 3.2 4M TLB Organization ....... 2-40
Figure 3.3 Cache Address Usage ...... 2-41
Figure 3.4 Data Cache Organization .... 2-42
Figure 3.5 Instruction Cache
Organization ................ 2-43
Figure 4.1 Signal Grouping ............. 2-49
Figure 5.1 Timing Diagram
Conventions ................ 2-57
Figure 5.2 Fastest Single-Transfer
Cycles ...................... 2-58
Figure 5.3 Single-Transfer Cycles with
Wait States ................. 2-59
Figure 5.4 Basic Burst Cycle ........... 2-60
Figure 5.5 Slow Burst Cycle ............ 2-60

Figure 5.7
Figure 5.8
Figure 5.9
Figure 5.10
Figure 5.11
Figure 5.12
Figure 5.13

Figure 5.14
Figure 5.15
Figure 5.16
Figure 5.17
Figure 5.18
Figure 5.19
Figu're 5.20
Figure 5.21
Figure 5.22
Figure 5.23

Figure 5.24

Figure 5.25

Figure 5.26
Figure 5.27
Figure 5.28
Figure 5.29

2-6

PAGE
Different Lengths of Burst
Cycles ...................... 2-61
Pipelined Cache Line Fills ... 2-63
Pipelined Back-to-Back Read
and Write Cycles ............ 2-64
Example Interrupt
Acknowledge Sequence .... 2-65
HOLD/HLDA Handshake ... 2-66
Normal Back-Off ............ 2-68
One-Clock Normal
Back-Off .................... 2-68
Fastest Nonpipelined Cycles
in One-Clock Late Back-Off
Mode ....................... 2-69
One-Clock Late Back-Off
Mode (Case 1) .............. 2-70
One-Clock Late Back-Off
Mode (Case 2) .............. 2-70
One-Clock Late Back-Off
Mode (Case 3) .............. 2-71
Two-Clock Late Back-Off
Mode ....................... 2-71
Inquiry Miss Cycle ........... 2-72
Fastest Inquiry Cycles
(Miss and Hit) ............... 2-73
Inquiry Hit Cycle with
Write-Back .................. 2-74
Snoop Responsibility Pickup
(Nonpipelined Cycle) ........ 2-76
Snoop Responsibility Pickup
(Pipelined Cycle) ............ 2-77
Latest Snooping of
Write-Back (Not Late
Back-Off Mode) ............. 2-78
Latest Snooping of WriteBack (One-Clock
Late Back-Off Mode) ........ 2-78
Latest Snooping of WriteBack (Two-Clock Late BackOff Mode) ................... 2-79
Write Reordering due to
Buffering .................... 2-80
Timing of EWBE# .......... 2-81
Cycle Reordering via FLlNE#
(No Ongoing Burst) ......... 2-82
Cycle Reordering via FLlNE#
(Ongoing Burst) ............. 2-83

CONTENTS

PAGE
Figure 5.30 Cycle Reordering via BOFF #
(Ongoing Burst) ............. 2-84
Figure 5.31 lOCK# Timing ............. 2-85
Figure 5.32 Reset Activities ............. 2-86
Figure 6.1 Format of DID Register ...... 2-88
Figure 6.2 logical Structure of BSR
Register .................... 2-88
Figure 6.3 TAP Controller State
Diagram .................... 2-90
Figure 6.4 Boundary Scan Register
Ordering .................... 2-93
Figure 7.1 i860TM XP Microprocessor
Pin Configuration-View from
Pin Side .................... 2-95
Figure7.2 i860TM XP Microprocessor
Pin Configuration-View from
Top Side .................... 2-96
Figure 7.3 262-lead Ceramic PGA
Package Dimensions ...... 2-101
Figure 8.1 Icc Derating with Case
Temperature ................ 2-103
Figure 9.1 ClK, Input, and Output
Timings .................... 2-107
Figure 9.2 TAP Signal Timings ........ 2-107
Figure 9.3 Typical Output Delay vs load
Capacitance ............... 2-108

CONTENTS
. Figure 9.4

Figure 9.5a

Figure 9.5b

Figure 9.6
Figure 9.7a
Figure 9.7b
Figure 9.8
Figure 9.9a
Figure 9.9b
Figure 9.10
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4

2-7

PAGE
Typical Output Delay vs.
load Capacitance under
Worst-Case Conditions .... 2-108
Typical Slew Time vs. load
Capacitance under WorstCase Conditions (Rising
Voltage) ................... 2-109
Typical Slew Time vs. load
Capacitance under WorstCase Conditions (Falling
Voltage) ................... 2-109
Typical Icc vs. Frequency .. 2-110
Output Model .............. 2-111
Input Model ................ 2-111
Package Model ............ 2-112
Output Buffer and Package
Model ..................... 2-112
Input Buffer and Package
Mod.el ..................... 2-112
Transmission Line Model ... 2-112
REG-Format Variations .... 2-131
Core Escape Instructions .. 2-132
CTRl-Format Instructions .. 2-133
Floating-Point Instruction
Encoding .................. 2-134

CONTENTS

CONTENTS

PAGE

Table5.4

TABLES

Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.9
Table 2.10
Table 2.11
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Table 5.1
Table 5.2
Table 5.3

Pixel Formats ................
Values of PS ................
Values of RB ................
ValuE;ls of RC ................
Values of RM ................
Values of LRP1 and LRPO ...
Values of CO and DO ........
CCU Addresses .............
Instruction Set (1 of 2) .......
Instruction Set (2 of 2) .......
Types of Traps ..............
Register and Cache Values
after Reset ..................
MESI Cache Line States .....
Internally Initiated Cache
State Transitions ............
Inquiry-Initiated Cache State
Transitions ..................
Summary of Cache Flushing
And Invalidation .............
Pin Summary ................
ADS# Initiated Bus Cycle
Definitions ...................
Memory Data Transfer Cycle
Types .......................
Cycle Length Definition ......
EADS# Sample Time ........
Burst Order for Cache Line
Transfers ....................
Pipeline Cycle
Compatibility ................
Encoding of Special Bus
Cycles .......................

2-11

Table 5.5

2-14

Table 6.1
Table 6.2

2-17
2-17
2-18

Table 6.3
Table 7.1

2-19
2-20
2-28

Table 7.2

2-29
2-30

Table 7.3

2-35

Table 8.;
Table 8.2

2-39
2-43
2-44

Table 9.1
Table 9.2

2-44

Table 9.3

2-47

Table 9.4

2-48
2-49

Table 9.5
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table ,1 0.6
Table 10.7
Table 10.8

2-49
2-49
2-52
2-61
2-62
2-65

2-8

PAGE
Inquiry for a Line being
Cached ..................... 2-75
Output Pin Status during
Reset ....................... 2-86
TAP Instruction Encoding .... 2-88
Registers Active by
Instruction ................... 2-89
Instruction Functions ........ 2-94
Pin Cross Reference by
Location .............. , ...... 2-97
Pin Cross Reference by Pin
Name ....................... 2-98
Ceramic PGA Package
Dimension Symbols ........ 2-100
Thermai Resistance ........ 2-102
Maximum TA at Various
Airflows .................... 2-102
D.C. Characteristics ........ 2-104
50 MHzA.C.
Characteristics ............. 2-105
Small Output Buffer First
Order Electrical Model
Parameter Values .......... 2-113
Large Output Buffer First
Order Electrical Model
Parameter Values .......... 2-114
Buffer Models ....... , ...... 2-115
Precision Specification ..... 2-120
FADDP MERGE Update .... 2-129
Register Encoding .......... 2-130
REG-Format Opcodes ...... 2-132
Core Escape Opcodes ...... '2-133
CTRL-Format Opcodes ..... 2-133
Floating-Point Opcodes ..... 2-134
DPC Encoding .............. 2-135

onte)®
1.0

i860TM XP MICROPROCESSOR

The .floating-poi~t multiplier performs floating-point
and Integer multiply as well as floating-point recipro-.
cal operations on 64- and 32-bit floating-point values. A multiplier instruction executes in three to four
clocks; however, in pipe lined mode, a new result can
be generated every clock for single-precision and
every other clock for double precision.

FUNCTIONAL DESCRIPTION

As ~hown by the block diagram on the front page,
the IB60 XP Microprocessor consists of the following
units:
1. Integer Registers and Core Execution Unit
2. Floating-Point Registers and Control Unit
3. Floating-Point Adder Unit
4. Floating-Point Multiplier l,Jnit
5. Graphics Unit
6. Paging Unit
7. Instruction Cache
B. Data Cache
9. Bus and Cache Control Unit
10. Detached Concurrency Control Unit

The graphics unit supports three-dimensional drawing i~ a graphi~s frame buffer, with color intensity
shading and hidden surface elimination via the
Z-buffer algorithm. The graphics unit recognizes the
pixel as an B-, 16-, or 32-bit integer data type. It can
compute individual red, blue, and green color intensity values within a pixel; but it does so with parallel
operations that take advantage of the 64-bit internal
word size and 64-bit external bus. The graphics features of the iB60 XP microprocessor assume that the
surface of a solid object is drawn with polygon .
patches which, like the pieces of a puzzle, collec- '
tively approximate the shape of the original object.
The color intensities of the vertices of the polygon
and their distances from the viewer are known, but
the distances and intensities of the other points
must be calculated by interpolation. The graphics instructions of the iB60 XP microprocessor directly aid
such interpolation.

EI

The core execution unit controls overall operation of
the iB60 XP microprocessor. It executes load store
integer, bit, I/O, and control-transfer operatio~s, and
fetches instructions for the floating-point unit as well.
A set of 32 x 32-bit general-purpose registers are
provided for the manipulation of integer data. Load
and store instructions move B-, 16-, and 32-bit data
to ~nd from these registers. Its full set of integer,
logical, and control-transfer instructions give the
core unit the ability to execute complete systems
software and applications programs. A trap mechanism provides rapid response to exceptions and external interrupts. Debugging is supported by the ability to trap on data or instruction reference.

The paging unit implements protected, paged, virtual
memory. The paging unit uses two four-way set-associative cache memories called TLBs (Translation
Lookaside Buffers) to perform the translation of logical address to physical address, and to check for
access violations. The access protection scheme
employs two levels of privilege: user and supervisor.
One TLB supports 4 Kbyte pages, and has 64 entries; the other supports 4 Mbyte pages, and has 16
entries.

The floating-point hardware is connected to a separate set of floating-point registers, which can be accessed as 16 x 64-bit rElgisters or as 32 x 32-bit
registers. Load and store instructions can also access these same registers as B x 12B-bit registers.
All floating-point and graphics instructions use these
registers as their source and destination operands.
The floating-point control unit controls both the float!ng-~oint adder and the floating-point multiplier, issuIng Instructions, handling all source and result exceptions, and updating status bits in the floatingpOint status register. The adder and multiplier can
operate in parallel, producing up to two results per
clock. The floating-point data types, floating-point instructions, and exception handling all support the
IEEE Standard for Binary Floating-Point Arithmetic
(ANSIIIEEE Std 754-19B5).
The floating-point adder performs addition subtraction, comparison, and conversions on 64- ~nd 32-bit
floating-point values. An adder instruction executes
in thre.e clocks; however, in pipelined mode, a new
result IS generated every clock.

The instruction cache is a four-way set-associative
memory of 16 Kbytes, with 32-byte lines. It transfers
up to 64 bits per clock (400 Mbyte/sec at 50 MHz).
. The data cache is a four-way set-associative memory of 16 Kbytes, with 32-byte lines. It transfers up to
12B bits per clock (BOO Mbyte/sec at 50 MHz). The
iB60 XP microprocessor normally uses write-back
c~ching, i.e: memory writes update the cache (if applicable) without necessarily updating memory immediately; however, under both software and hardware control, write-through and write-once policies
can be implemented, or caching can be inhibited.
The caches are transparent to applications software.
The bus and cache control unit performs data and
instruction accesses for the core unit. It receives cycle requests and specifications from the core unit,
performs the data-cache or instruction-cache miss
processing, controls TLB translation, and provides
2-9

Intei·

i860TM XP MICROPROCESSOR

the interface to the external bus. Its pipe lined structure supports up to three outstanding bus cycles. Its
burst mode transfers data at up to 400 Mbyte/sec at
50 MHz. In multiprocessor systems, .it maintains
cache consistency by monitoring bus activity in parallel with other CPU functions.
The DCCU (detached concurrency control unit) is a
compatible subset of the external CCU that expedites loop-level parallelism and synchronization in
multiprocessor systems. The DCCU consists of registers and a counter that allow a single i860 XP microprocessor to run binary code compiled for a multiprocessor system adhering to the PAX parallel applications binary interface (ASI).

2.1.1 INTEGER

An integer is a 32-bit signed value in standard two's
complement form. A 32-bit integer can represent a
value in the range -2,147,483,648 (-2 31 ) to
2,147,483,647 (+ 231 - 1), Arithmetic operations on
8- and 16-bit integers can be performed by sign-extending the 8- or 16-bit values to 32 bits, then using
the 32-bit operations.
There are also add and subtract instructions that operate on 64-bit long integers.
Load and store instructions may also reference (in
addition to the 32- and 64-bit formats previously
mentioned) 8- and 16-bit items in memory. When an
8- or 16-bit item is loaded into a register, it is converted to an integer by sign-extending the value to
32 bits. When an 8- or 16-bit item is stored from a
register, th? corresponding numb6i of low-order bits
of the register are used.

The i860 XP microprocessor may to be used with or
without an external, secondary cache built from
82495XP and 82490XP cache components. An
82495XP and 82490XP cache provides up to 512
Kbytes of high-speed storage for data and instruction combined. In most cases, an 82495XP and
82490XP cache can provide data to the CPU with
zero wait states. The larger size of an external cache
can provide an increased hit rate when the size or
number of data structures and programs exceeds
the size of the internal caches. In multiprocessor
systems, the external cache serves as local memory, and can reduce bus traffic. An external cache
also hides the processor from rest of system, which
is a double advantage:
1. The processor can be upgraded without affecting
design of the memory and other subsystems.
2. Slower and less expensive memory and I/O subsystem designs can be employed without unduly
lowering overall system performance.

2.1.2 ORDINAL

Arithmetic operations are available for 32-bit ordinals. An ordinal .is an unsigned integer. An ordinal
can represent values in the range 0 to
4,294,967,295 (+2 32 - 1).
Also, there are add and subtract instructions that operate on 64-bit ordinals.
2.1.3 SINGLE- AND DOUBLE-PRECISION REAL

Figure 2.1 shows the real number formats. A singleprecision real (also called "single real") data type is
a 32-bit binary floating-point number. Sit 31 is the
sign bit; bits 30 .. 23 are the exponent; and bits 22 .. 0
are the fraction. In accordance with ANSI/IEEE
standard 754, the value of a single-precision real is
defined as follows:
1. If e = 0 and f =/0 0 or e = 255 then generate a
floating-point source-exception trap when encountered in a floating-point operation.
2. If 0 < e ~ 255, then the value is (-1)5 X 1.f x
2 e - 127.

Refer to the 82495XP Cache Control/erl82490XP
Cache RAM Data Sheet (Intel Order #240956) for
more information.

2.0

PROGRAMMING INTERFACE

The programmer-visible aspects of the architecture
of the i860 XP microprocessor include data types,
registers, instructions, and traps.

3. If e = 0 and f= 0, then the value is signed zero.

2.1

Data Types

A double-precision real (also called "double real")
data type is a 64-bit binary floating-point number. Bit
63 is the sign bit; bits 62 .. 52 are the exponent; and
bits 51 .. 0 are the fraction. In accordance with ANSI/
IEEE standard 754, the value of a double-precision
real is defined as follows:
1. If e = 0 and f =/0 0 or e = 2047, then generate a
floating-point source-exception trap when encountered in a floating-point operation.

The i860 XP microprocessor provides operations for
integer and floating-point data. Integer operations
are performed on 32-bit operands with some support
also for 64-bit operands. Load and store instructions
can reference 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit
operands. Floating-point operations are performed
on IEEE-standard 32- and 64-bit formats. Graphics
instructions operate on arrays of 8-, 16-, or 32-bit
pixels.
2-10

int:eL

i860TM XP MICROPROCESSOR

2. If 0 < e <,2047, then the value is (-1)S x 1.1 x
2e-1023.
.
3. If e

less of the pixel size, the i860 XP microprocessor
always operates on 64 bits of pixel data at a time.
The pixel data type is used by two kinds of instructions:
• The selective pixel-store instruction that helps implement hidden surface elimination.
• The pixel add instruction that helps implement
3-0 color intensity shading.

= 0 and 1 = 0, then the value is signed zero.

The special values infinity, NaN ("Not a Number"),
indefinite, and denormal generate a trap when encountered. The trap handler implements IEEE-standard results.

A double real value occupies an even/odd pair of
floating-point registers. Bits 31 .. 0 are stored in the
even-numbered floating-point register; bits 63 .. 32
are stored in the next higher odd-numbered floatingpoint register.

To perform color intensity shading efficiently in a variety of applications, the i860 XP microprocessor defines three pixel formats according to Table 2.1.
Figure 2.2 illustrates one way of assigning meaning
to the fields of pixels. These aSSignments are for
illustration purposes only. The i860 XP microprocessor defines only the field sizes, not the specific use
of each field. Other ways of using the fields of pixels
are possible.
'

2.1.4 PIXEL

A pixel may be 8-, 16-, or 32-bits long, depending on
color and intensity resolution requirements. RegardSingle-Precision Real
31 '30 23 :22
e
f

Double-Precision Real
0

Is

2-J

SIGN
EXPONENT
FRACTION

52'51

ffi. '62

Is

I

1

0

I

e

I;

f

1

L-FRACTION
EXPONENT
SIGN

240874-2

240874-3

Figure 2.1. Real Number Formats
Table 2.1. Pixel Formats
Pixel
Size
(in bits)

Bits of
Color 1
Intensity(1)

Bits of
Color 2
Intensity(1)

Bits of
Color 3
Intensity(1)

8
16M
32

6
8

N (:0;; 8) bits of intensity(2)
6
8

4
8

J

J

I

Bits of
Other
Attribute
(Texture, Color)
8-N
0
8

NOTES:
1. The intenSity attribute fields may be assigned to colors in any order convenient to the application.
2. With a·bit pixels, up to a bits can be used for intensity; the remaining bits can be used for any other attribute, such as
color or texture. Bits that require interpolation (shading), such as those for intensity, must be the low-order bits of the pixel.

2-11

i860™ XP MICROPROCESSOR

a-BIT PIXEL

15 14 15 12 If 10 9

16-BIT PIXEL

I

RED

I

~

( _ _C_OL_O_R_--.J'I

8 7 6 5 4 .; 2

GREEN

I

1 0

BLUE

32-BIT PIXEL
Jf 30292827262524 '2322 21 20 19 18 17 16 1514131211109 B 7 6 5 4 3 2

I

RED

GREEN

BLUE

1 0

TEXTURE

240874-4

NOTE:
These aSSignments of specific meanings to the fields of pixels are for illustration only. Only the field sizes are defined,
not the specific use of each field.

Figure 2.2. Pixel Format Example
When accessing 64-bit floating-point or integer values, the i860 XP microprocessor uses an even/odd
pair of registers. When accessing 128-bit values, it
uses an aligned set of four registers (fO, f4, f8, f12,
f16, f20, f24, or f28). The instruction must designate
the lowest register number of the set of registers
containing 64- or 128-bit values. Misaligned register
numbers produce undefined results. The. register
with the lowest number contains the least significant
part of the value. For 128-bit values, the register pair
with the lower number contains the value from the
lower memory address; the register pair with the
higher number contains the value from the higher
address.

2.2 Register Set
As Figure 2.3 shows, the i860 XP microprocessor
has the following registers:
• An integer register file
o A floating-point register file
• Control registers psr, epsr, db, dirbase, fir, fsr,
bear, eer, p3, p2, p1, pO
• Special-purpose registers KR, KI, T,MERGE,
STAT, and NEW~URR
The control registers are accessible only by load
and store control-register instructions; the integer
and floating-point registers are accessed by arithmetic operations and load and store instructions. The
special-purpose registers KR, KI, and T are used by
floating-point instructions; MERGE is used by graphics instructions. NEWCURR and STAT are used for
concurrency control; they are accessed by memory
load and store instructions.

The 128-bit load and store instructions, along with
the 128-bit data path between the floating-point registers and the data cache, help to sustain an extraordinarily high rate of computation.
2.2.3 PROCESSOR STATUS REGISTER
The processor status register (psr) contains miscellaneous state information for the current process.
Figure 2.4 shows the format of the psr.
• BA (Break Read) and BW (Break Write) enable a
data access trap when the operand address
matches the address in the db register and a
read or write (respectively) occurs.

2.2.1 INTEGER REGISTER FILE
There are 32 integer registers, each 32 bits wide,
referred to as rO through r31, which are used for
address computation and scalar integer computations. Register rO always returns zero when read.

• Various instructions set CC (Condition Code) according to tests they perform. The branch-oncondition-code instructions test its value. The bla
instruction sets and tests LCC (Loop Condition
Code).

2.2.2 FLOATING-POINT REGISTER FILE
There are 32 floating-point registers, each 32-bits
wide, referred to as fO through f31, which are used
for floating-point computations. Registers fO and f1
always return zero when read. The floating-point
registers are also used by a set of integer operations, primarily for graphics computations.

• 1M (Interrupt Mode), if set, enables external interrupts on the INT pin; disables interrupts on INT if
clear. 1M does not affect parity error interrupts or
interrupts on the BEAR pin.
2-12

i860TM }(P MICROPROCESSOR

BEAR

FIR

CCR

PSR

PO

DIRBASE

PI

DB

P2

FSR

P3

EPSR

84

II

INSTRUCTION
DECODE AND FETCH
LATE BACK-OFF
I

I
16 KBYTE
INSTRUCTION CACHt

•D I• D•
L..ii_BUFFERS
_ _....1 '28

ADDRESS

32
32

D

•
••

16 KBYTE
DATA CACHE

32

••

32

240874-5

Figure 2.3. Registers and Data Paths
o FT (Floating-Point Trap),

OAT (Data Access
Trap), IAT (Instruction Access Trap), IN (Interrupt), and IT (Instruction Trap) are trap flags.
They are set when the corresponding trap condition occurs. IN is set on INT, bus error and parity
error. The trap handler examines these bits (and
other trap bits in the epsr) to determine which
condition or conditions have caused the trap.

• U (User Mode) is set when the i860 XP microprocessor is executing in user mode; it is clear
when the i860 XP microprocessor is executing in
supervisor mode. In user mode, writes to some
control registers are inhibited. This bit also controls the memory protection mechanism.
• PIM (Previous Interrupt Mode) and PU (Previous
User Mode) save the corresponding status bits
(1M and U) on a trap, because those status bits
are changed when a trap occurs. They are restored into their corresponding status bits when
returning from a trap handler with a branch indirect instruction when a trap flag is set in the psr.

o

2-13

DS (Delayed Switch) is set if a trap occurs during
the instruction before dual-instruction mode is entered or exited. If DS is set and DIM (Duallnstruction Mode) is clear, the i860 XP microprocessor
switches to dual-instruction mode one instruction

i860™ XP MICROPROCESSOR

BREAK R E A D - - - - - - - - - - - - - - - - - - - - - ,
BREAK W R I T E - - - - - - - - - - - - - - - - - - - - - ,
CONDITION CODE - - - - - - - - - - - - - - - - - - ,
LOOP CONDITION CODE - - - - - - - - - - - - - - - - ,
INTERRUPT M O D E ' - - - - - - - - - - - - - - - - - ,
PREVIOUS INTERRUPT MODE . , - - - - - - - - - - - - - - ,
USER M O D E - - - - - - - - - - - - - - - - ,
PREVIOUS USER MODE - - - - - - - - - - - - - ,
INSTRUCTION TRAP - - - - - - - - - - - - . . . . ,
INTERRUPT - - - - - - - - - - - - - - - ,
INSTRUCTION ACCESS TRAP ---~----....,
DATA ACCESS.TRAP-----------,
FLOATING-POINT TRAP - - - - - - - - - ,
DELAYED SWITCH - - - - - - - - - - ,
DUAL INSTRUCTION MODE

------,J

JJI

3130292827262524 '23222120 1918 17.16 15 14 1312 1110 9 8

I

PM

PS

? D F 2 AI I
SC'i~1 F M S T T TNT
I'.~I~

I

7 6 5 4 3 2

plul) I ~
U I 'I M M C

~

1

0

-

C B B:
C WR.

KILL NEXT FP INSTRUCTION
'------,- (RESERVED)
' - - - - - - - SHIFT COUNT
' - - - - - - - - - PIXEL SIZE
' - - - - - - - - - - - - - PIXEL MASK

ITI!I RESERVED BY INTEL CORPORATION

IllB CAN

BE CHANGED ONLY FROM SUPERVISOR LEVEL

240874-6

Figure 2.4. Processor Status Register
after returning from the trap handler. If OS and DIM
are both set, the i860 XP microprocessor switches
to single·instruction mode one instruction after returning from the trap handler.
• When a trap occurs, the i860 XP microprocessor
sets DIM if it is executing in dual-instruction
mode; it clears DIM if it is executing in single-instruction mode. If DIM is set.after returning from a
trap handler, the. i860 XP microprocessor resumes execution in dual-instruction mode.
• When KNF (Kill Next Floating-Point Instruction) is
set, the next floating-point inStriJction is suppressed (except that its dual-instruction mode bit
is interpreted). A trap handler sets KNF 'if the
trapped floating-point instruction should not be
reexecuted.
• SC (Shift Count) stores the shift count used by
the last right-shift instruction. It controls the number of shifts executed by the double-shift instruction.
• PS (Pixel Size) and PM (Pixel Mask) are used by
the pixel-store and other graphics· instructions.
The values of PS control pixel size as defined by
Table 2.2. The bits in PM correspond to pixels to
be updated by the pixel-store instruction pst.d.
The low-order bit of PM corresponds to the loworder pixel of the 64-bit source operand of pst.d.
The number of low-order bits of PM that are actually used is the number of pixels that fit into
64-bits, which depends upon PS. If a bit of PM is
set, then pst.d stores the corresponding pixel.
Refer also to the pst.d instruction in section 10.

Table 2.2. Values of PS
Value

Pixel Size
in Bits

Pixel Size
in Bytes

00
01
10
11

8
16
32
(undefined)

1
2
4
(undefined)

2.2.4 EXTENDED PROCESSOR STATUS
REGISTER
The extended processor status register (epsr) contains additional state information for the current process beyond that stored in the psr. Figure 2.5 shows
the format of the epsr.
• The processor type is 2 for the i860 XP micro, processor.
• The stepping number has a unique value that distinguishes among different revisions of the proc-

essor.
• IL (Interlock) is set if a trap occurs after a lock
instruction but before the last BRDY # of the load
or store following the subsequent unlock
instruction. IL indicates to the trap handler that a
locked sequence has been interrupted. When the
trap handler finds IL set, it should scan backwards for the lock instruction and restart at that
point. The absence of a lock instruction within
30-33 instructions of the trap indicates a programming error.
2-14

int:eL

i860™ XP MICROPROCESSOR

INTERLOCK - - - - - - - - - - - - ,
WRITE-PROTECT MODE - - - - - - - - - ,
PARITY ERROR FLAG •

-------.l

" 0/29.'28/27. 5. 5

reI S P P I
FH 0 I T I