Introduction_to_Intel_Cell Based_Design_1988 Introduction To Intel Cell Based Design 1988
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Introduction to Intel
Cell-Based Design
CELL
BASED
PRODUCTS
231816-002
Introduction to Intel
Cell-Based Design
CELL
BASED
PRODUCTS
I~
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
t
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i,
ICE, iCEL, iCS, iDBP, iDIS, 12 1CE, iLBX, im , iMDDX, iMMX, Inboard, Insite, Intel,
intel, intelBOS, Intel Certified, Intelevision, inteligent Identifier, inteligent
Programming, Intellec, Intellink, iOSP, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX,
iSDM, iSXM, KEPROM, Library Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME, MULTIBUS, MULTICHANNEL, MULTIMODULE,
MultiSERVER, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble, PROMPT,
Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80,
RUPI, Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical
suffix, 4-SITE.
MDS is an ordering code only and is not used as a product name or trademark. MDS@ is a registered trademark of Mohawk
Data Sciences Corporation .
• MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 58130
Santa Clara, CA 95052-8130
©INTEL CORPORATION 1986. 1988
CG-1/18/88
PREFACE
A growing number of system designers are turning to Application Specific Integrated Circuits
(ASICs) for the solution to their system design needs. ASIC design methodologies bridge
the gap between standard ICs and fully-customized devices. Using sophisticated software
design tools and a collection of predefined circuit elements, system designers realize the
benefits of custom ICs without incurring the high cost and long development times associated with full custom designs.
The Intel Design Environment provides a flexible system for designing and manufacturing
Intel ASIC products. ASIC designers may now choose from a broad range of products and
services under the umbrella of Intel's proven leadership in semiconductor technology,
including cell-based ICs, gate arrays, and Electrical Programmable Logic Devices (EPLDs).
The design environment includes a comprehensive set of CAE/CAD tools, design libraries
running on the Daisy and Mentor engineering workstations, and design and manufacturing
services. Intel cell-based designs are backed by a proven manufacturing capability and the
same strict adherence to quality and reliability applied to Intel standard products.
This manual introduces the Intel 1.5 Micron CHMOS III Cell Library. It provides cell data
specifications and describes Intel design services as they relate to cell-based designs executed
at Intel design centers or at the customer site. This is the second edition of the manual,
superceding those manuals dated 1986.
iii
INTRODUCTION TO CELL-BASED DESIGN
RELATED PUBLICATIONS
•
•
•
Cell-Based Design-Daisy Environment
Cell-Based Design - Mentor Environment
Introduction to Intel Gate Array Design
Programmable Logic Handbook
•
•
•
Microprocessor and Peripheral Handbook
Embedded Controller Handbook
Components Quality/Reliability Handbook
Order
Order
Order
Order
Order
Order
Order
# 83002
# 830000
# 231811
# 296083
# 230843
# 210918
# 210997
MANUAL ORGANIZATION
The Introduction to Intel Cell-Based Design manual is organized into the following chapters
and appendixes:
•
Chapter 1, "Introduction to the Intel 1.5 Micron CHMOS III Cell Library," provides
an overview of the Intel 1.5 Micron CHMOS III Cell Library, including descriptions of
the different types of cells in the library.
•
Chapter 2, "Introduction to the Intel Design Environment," describes the Intel cellbased ASIC design flow, available Computer Aided Engineering (CAE) workstation
tools and libraries, and Intel provided design support and services.
Chapter 3, "The Intel 1.5 Micron CHMOS III Cell Library," provides data sheets for
all fixed height, variable width cells in the Intel 1.5 Micron CHMOS III Cell Library,
including SSI/MSI functions, telescoping cells, and I/O cells. System specifications for
the cell library are also presented.
Chapter 4, "VLSiCEL Elements and LSI Functions," provides data sheets for
VLSiCEL elements and LSI function cells in the Intel 1.5 Micron CHMOS III Cell
Library, including the 80C51 BH Microcontroller Core cells, Microprocessor Support
Peripheral Family cells, and memory cells.
Appendix A, "Packaging," presents a matrix of standard package types available for
use with Intel cell-based ASICs.
Appendix B, "Terms and Definitions," contains definitions of cell specification parameters which appear in the Intel 1.5 Micron CHMOS III Cell Library data sheets.
•
•
•
•
Appendix C, "Cell Reference Guide," provides an index of cells in the Intel 1.5 Micron
CHMOS III Cell Library. These cells are listed alphabetically and include the cell
description, grid count, and page number of the cell data sheet.
iv
TABLE OF CONTENTS
CHAPTER 1
INTRODUCTION TO THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
Features/Benefits .................................................................................................
Cell-Based Design ................................................................................................
Why Cell-Based ASICs? ...................................................................................
Why Intel? ............ ... ..................... .............. .................... ................. ..................
What is a Standard Cell? ...............................................:..................................
An Example of a Cell-Based Design .................................................................
Cell Types .... ......................... ... ............................................................................
Standard Cells ..................................................................................................
Telescoping Cells ............................................. :................................................
Cluster Macros .................................................................................................
I/O Cells ............................................................................................................
Memory Cells .............. ....... ... ............... ...... ............................ ......... ..................
VLSiCEL Elements ........................ ............ ....... ... ......... .................. ..................
Cell Size ...............................................................................................................
Page
1-1
1-2
1-2
1-2
1-3
1-4
1-4
1-4
1-5
1-5
1-6
1-6
1-6
1-7
CHAPTER 2
INTRODUCTION TO THE INTEL DESIGN ENVIRONMENT
An Overview of the Intel Design Environment ...... ... ....................................... ......
An Overview of the Cell-Based Design Sequence ................................................
Design Phase ....................................................................................................
Layout and Verification .....................................................................................
Manufacturing Phase ........................................................................................
Packaging ............................................................................................................
Quality and Reliability ...........................................................................................
Design Support ....................................................................................................
Computer Aided Engineering (CAE) Tools ........................................................
Mainframe-Based Simulation ....... ........ ...... ................................... ....................
Intel Technology Centers ..................................................................................
2-1
2-1
2-1
2-3
2-3
2-4
2-5
2-6
2-7
2-7
2-7
CHAPTER 3
THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
Cell Library System Specifications .......................................................................
Absolute Maximum Ratings ........................ ... ...... .......... ...................... ....... ......
Recommended Operating Conditions ............... ...... ............. .............................
Measurement Conditions .....................................................................................
Interpreting Cell Data Sheets .................. .............................................................
Inverters and Buffers ... ............................ ...... ........................................... ............
INVN
Inverter, Normal Drive ........... ............................................ ....... ......
v
3-1
3-1
3-1
3-1
3-6
3-12
3-12
INTRODUCTION TO CELL-BASED DESIGN
Page
INVNH
Inverter, High Drive ........................................................................
INVTE
3-State Inverter with Active Low Output Enable, Normal Drive.....
INVTD
3-State Inverter with Active High Output Enable, Normal Drive .....
BUF
Buffer, Normal Drive ..... ........... ............................................. .........
BUFH
Buffer, High Drive ........... ......... ....... ....... .............................. ..........
BUF2
Buffer with Dual Output, Normal Drive ....................................... ...
BUFTE
3-State Buffer with Active Low Output Enable, Normal Drive ........
BUFTD
3-State Buffer with Active High Output Enable, Normal Drive .......
Gates ...................................................................................................................
NAN2
2 Input NAND, Normal Drive ..........................................................
NAN3
3 Input NAND, Normal Drive ..........................................................
NAN4
4 Input NAND, Normal Drive .... ... .... ....... ........................... ... ..........
NAN5
5 Input NAND, Normal Drive ........................... ...............................
NAN6
6 Input NAND, Normal Drive ..........................................................
NAN7
7 Input NAND, Normal Drive .... .......... ............................... ... ..........
NAN8
8 Input NAND, Normal Drive ........... ......... .............. ........... ... ..........
NOR2
2 Input NOR, Normal Drive ............................................................
NOR3
3 Input NOR, Normal Drive ............................................................
NOR4
4 Input NOR, Normal Drive ......... .......... ............................ ... ..........
NOR5
5 Input NOR, Normal Drive ... .......... ......... .............. ........... .............
NOR6
6 Input NOR, Normal Drive ..................................................... .......
NOR7
7 Input NOR, Normal Drive ............................................................
NOR8
8 Input NOR, Normal Drive ..... .... ................... ... ............ .... .............
AND2
2 Input AND, Normal Drive .. ....... ...... .... ... ......... ..... ........... ... ...... ....
AND3
3 Input AND, Normal Drive ............................................................
AND4
4 Input AND, Normal Drive ............................................................
AND5
5 Input AND, Normal Drive ............................................................
AND6
6 Input AND, Normal Drive ............................................................
AND7
7 Input AND, Normal Drive .. ....... ...... ....... ......................... ......... ....
AND8
8 Input AND, Normal Drive ............................................................
OR2
2 Input OR, Normal Drive ..............................................................
OR3
3 Input OR, Normal Drive ....................................................... .......
OR4
4 Input OR, Normal Drive ..............................................................
OR5
5 Input OR, Normal Drive ....... .... ...................... ............ .................
OR6
6 Input OR, Normal Drive .... ....... ...... ....... .................................. ....
OR7
7 Input OR, Normal Drive .... ....... ...... ....... .................................. ....
ORB
8 Input OR, Normal Drive ..............................................................
AOR22
2 AND2 into OR2, Normal Drive ....................................................
AOl22
2 AND2 into NOR2, Normal Drive ........ .... .............. ........... ......... ....
EXR2
2 Input EXCLUSIVE OR, Normal Drive ..........................................
EXN2
2 Input EXCLUSIVE NOR, Normal Drive ........................................
Flip-Flops ..............................................................................................................
FFT
Toggle Flip-Flop with Master Reset ...............................................
3-12
3-14
3-16
3-18
3-18
3-20
3-21
3-23
3-25
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
3-45
3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-57
inter
TABLE OF CONTENTS
Page
FFTE
FFJK
FLJK
FLJKT
FFD
FFDE
FLDE
FLDET
FFDM2
FLDM2
Toggle Flip-Flop with Enable and Master Reset ........................... .
JK Flip-Flop with Master Reset .............................. ~ ...................... .
JK Flip-Flop with Master Set and Master Reset .......................... ..
3-State JK Flip-Flop with Master Set and Master Reset .............. ..
D Flip-Flop with Master Reset ...................................................... .
D Flip-Flop with Enable and Master Reset .................................... .
D Flip-Flop with Enable, Master Set, and Master Reset .............. ..
3-State D Flip-Flop with Enable, Master Set, and Master Reset ... .
D Flip-Flop with 2 to 1 Data Multiplexer and Master Reset .......... .
D Flip-Flop with 2 to 1 Data Multiplexer, Master Set, and
Master Reset .............................................................................
FFDHI
Positive Edge Event Trigger with Master Reset .......................... ..
Latches ................................................................................................................
LAD
Transparent D Latch with Master Reset ...................................... ..
LSR
S-R Latch with Master Reset ....................................................... .
LASR
S-R Latch with Enable and Master Reset ..................................... .
S-R Latch with Master Reset ....................................................... .
LNSR
LANSR
S-R Latch with Enable and Master Reset .................................... ..
Multiplexers and Decoders ...................................................................................
MUX21
2-Line to 1-Line Multiplexer .......................................................... .
MUX41
4-Line to.1-Line Multiplexer ......................................................... ..
DMX2
2-Line to 4-Line Demultiplexer/Decoder with 2 Enables .............. ..
DMX3
3-Line to 8-Line Demultiplexer/Decoder ....................................... .
Arithmetic Functions ..............................................................................................
CPR
8/9-bit Parity Checker/Generator .................................................. .
Introduction to Teles'coping Cells .........................................................................
Telescoping Registers ..........................................................................................
Telescoping Register {REGC, REGB} .............................................................. .
REGC
Telescoping Register Control ........................................................ .
REGB
Telescoping Register Body .......................................................... ..
Telescoping 3-State Register {REGCT, REGBT} ............................................ ..
REGCT Telescoping 3-State Register Control .......................................... ..
REGBT Telescoping 3-State Register Body .............................................. .
Telescoping Shift Register {SHRC, SHRB} ...................................................... .
SHRC
Telescoping Shift Register Control ............................................... .
Telescoping Shift Register Body .................................................. ..
SHRB
Telescoping Shift Register With Load {SHLC, SHLB} ...................................... .
SHLC
Telescoping Shift Register with Load, Control .............................. .
Telescoping Shift Register with Load, Body ................................ ..
SHLB
Telescoping Counters ..........................................................................................
Telescoping Up Counter {CULC, CULB, CULP} .............................................. ..
CULC
Telescoping Up Counter Control .................................................. ..
CULB
Telescoping Up Counter Body ...................................................... .
3-59
3-61
3-63
3-65
3-68
3-70
3-72
3-74
3-77
3-79
3-81
3-83
3-83
3-85
3-87
3-89
3-91
3-93
3-93
3-94
3-96
3-98
3-100
3-100
3-102
3-103
3-103
3-105
3-107
3-109
3-112
3-114
3-117
3-120
3-122
3-124
3-127
3-129
3-132
3-132
3-136
3-138
inter
INTRODUCTION TO CELL-BASED DESIGN
Page
CULP
Telescoping Up Counter Carry Out Driver ..................................... 3-141
Telescoping Up/Down Counter (CUPC, CUPB, CUPP, CUPP2) ........................ 3-143
CUPC
Telescoping Up/Down Counter Control........... ... ....... .......... ... ....... 3-148
CUPB
Telescoping Up/Down Counter Body ............................................. 3-151
CUPP
Telescoping Up/Down Counter End Count Driver ... ..... .................. 3-154
CUPP2 Telescoping Up/Down Counter End Count/Carry/Borrow Driver ... 3-156
Telescoping Arithmetic Functions ......................................................................... 3-158
Telescoping Adder (ADDC, ADDB, ADDP) ....................................................... 3-158
Telescoping Adder Control..... .......... ....... ....... ..... .......... ............ .... 3-160
ADDC
Telescoping Adder Body ................................................................ 3-161
ADDB
Telescoping Adder Carry Out Driver ...... ....... ...... ......... ........... ....... 3-163
ADDP
Telescoping Magnitude Comparator (CMPC, CMPB, CMPP) ... ...... .................. 3-164
CMPC Telescoping Magnitude Comparator Control......... ...... ......... ......... 3-167
CMPB Telescoping Magnitude Comparator Body...... .... ......... ........... ....... 3-168
Telescoping Magnitude Comparator Equal/Greater Than/Less
CMPP
Than Driver ................................................................................ 3-170
Input/Output ......................................................................................................... 3-172
PCI
Non-Inverting CMOS Input Buffer, Normal Drive ... ... ... .... ........... ... 3-172
PCIH
Non-Inverting CMOS Input Buffer, High Drive ....................... ......... 3-172
PTI
Non-Inverting TTL Input Buffer, Normal Drive ................................ 3-174
PTIH
Non-Inverting TTL Input Buffer, High Drive .................................... 3-174
PTIRH
Non-Inverting TTL Input Buffer with Pull-up Resistor, High Drive .. 3-176
PISH
Non-Inverting TTL Schmitt Trigger Input Buffer, High Drive ..... ..... 3-178
PISRH
Non-Inverting TTL Schmitt Trigger Input Buffer with Pull-up Resistor,
High Drive .................................................................................. 3-180
PCO
Inverting CMOS Output Buffer, 3.2 mA ......................................... 3-182
PCNO
Non-Inverting CMOS Output Buffer, 3.2 mA .. :.............................. 3-183
3-State Inverting CMOS Output Buffer, 3.2 mA .... ..... ..... ..... ......... 3-184
PCOT
PTO
Inverting TTL Output Buffer, 3.2 rnA Sink ..................................... 3-186
PTNO
Non-Inverting TTL Output Buffer, 3.2 rnA Sink .... ..... ... ......... .... ..... 3-187
Non-Inverting TTL Output Buffer, 9.6 mA Sink ...... ...... ......... ......... 3-188
PTN03
Non-Inverting TTL Output Buffer, 16 rnA Sink ......... ............. ......... 3-190
PTN05
3-State Inverting TTL Output Buffer, 3.2 mA Sink ......................... 3-192
PTOT
PTOT3
3-State Inverting TTL Output Buffer, 9.6 mA Sink ......................... 3-194
3-State Inverting TTL Output Buffer, 16 mA Sink ....... .... ...... ......... 3-196
PTOT5
PTND
Non-Inverting TTL Open-Drain Output Buffer, 3.2 mA Sink .. ......... 3-198
PTND3
Non-Inverting TTL Open-Drain Output Buffer, 9.6 mA Sink ........... 3-199
PTND5
Non-Inverting TTL Open-Drain Output Buffer, 16 rnA Sink ... .... ..... 3-200
PCIO
CMOS I/O Buffer; Latched Non-Inverting Input, 3-State Inverting
Output, 3.2 rnA .......................................................................... 3-201
PTIO
TTL I/O Buffer; Latched Non-Inverting Input, 3-State Inverting
Output, 3.2 mA Sink .................................................... ~............. 3-203
TABLE OF CONTENTS
Page
PTI03
PTI05
TTL I/O Buffer; Latched Non-Inverting Input, 3-State Inverting
Output, 9.6 mA Sink .................... ~ ............................................. 3-205
TTL I/O Buffer; Latched Non-Inverting Input, 3-State Inverting
Output, 16 mA Sink ... ............................... ................... ....... ....... 3-207
CHAPTER 4
VLSiCEL ELEMENTS and LSI FUNCTIONS
UC51 ....................................................................................................................
4-1
UC51 00
80C51 BH Microcontroller Core with No ROM ...............................
4-1
UC5104
80C51BH Microcontroller Core with 4K Bytes ROM .....................
4-1
UC51 08
80C51 BH Microcontroller Core with 8K Bytes ROM .....................
4-1
UC5116
80C51BH Microcontroller Core with 16K Bytes ROM ...................
4-1
UC51 Companion Cells ...................................................................... .................. 4-14
PRESET Reset Input Buffer ......................................................................... 4-14
POSC
Oscillator Frequency Range to 16 MHz ................. ...... ...... ............ 4-16
PADB
Address/Data Bus I/O Buffer ......................................................... 4-18
PTNQB
Quasi-Bidirectional I/O Buffer ........................................................ 4-20
PRGPIN
Programmable I/O Buffer ....... .... ......... ...... ............ ...... ....... .... ........ 4-23
SP8237
Programmable DMA Controller .... .................................................. 4-25
SP8254
Programmable Interval Timer ......................................................... 4-41
SP8259
Programmable Interrupt Controller ................................................ 4-49
SP8284
8086/8088 Clock Generator and Driver .......................................... 4-57
SP8288
8086/8088 Bus Controller ........... ....... ...... ........... ......... ..... ... ......... 4-64
SP82284
80286 Clock Generator and Ready Interface ................................. 4-73
SP82288
80286 Bus Controller ..................................................................... 4-80
Microprocessor Support Peripheral Companion Cells .......................................... 4-92
POSC2
Oscillator, Frequency Range to 37.5 MHz ..................................... 4-92
PCN04
Non-Inverting CMOS Output Buffer, 15 mA .................................. 4-94
PC02
Inverting CMOS Output Buffer, 16 mA .......... ................... ... .... ...... 4-96
PCOT6
3-State Inverting CMOS Output Buffer with Enable, 42 rnA .......... 4-98
Fixed Configuration Memory - Static RAM ........................................................... 4-1 00
RAM64
64 x 8 Static Random Access Memory ......................................... 4-100
RAM 128 128 x 8 Static Random Access Memory ....................................... 4-105
RAM256 256 x 8 Static Random Access Memory ....................................... 4-110
RAM512 512 x 8 Static Random Access Memory ....................................... 4-115
RAM1 K
1024 x 8 Static Random Access Memory ..... ........ .... ... ...... ..... ...... 4-121
APPENDIX A
PACKAGING
APPENDIX B
TERMS AND DEFINITIONS
INTRODUCTION TO CELL-BASED DESIGN
APPENDIX C
CELL REFERENCE GUIDE
Figures
Figure
1-1
1-2
1-3
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Title
Example Standard Cell ...............................................................................
Example Cell-Based Design ........................................................................
Example 4-Bit Counter .................................. ;............................................
Design Phase Flowchart (Technology Center) ............................... .............
Layout and Verification Phase Flowchart ....................................................
Manufacturing Phase Flowchart ........................................................... ......
CMOS Input and Bi-Directional I/O Cell Input Propagation Delay Times .....
TTL Input and Bi-Directional I/O Cell Input Propagation Delay Times .........
CMOS Output and Bi-Directional I/O Cell Output Propagation Delay
Times ....................................................................................................
TTL Output and Bi-Directional I/O Cell Output Propagation Delay Times ...
CMOS 3-State Output anq Bi-Directional I/O Cell Enable and Disable
Times ......................................................................................................
TTL 3-State Output and Bi-Directional I/O Cell Enable and Disable
Times ......................................................................................................
CULB Data Sheet .......................................................................................
PCIO Data Sheet .. .................... ............. ... ..................................................
Page
1-3
1-4
1-6
2-2
2-4
2-5
3-2
3-2
3-3
3-3
3-4
3-4
3-7
3-9
Tables
Table
1-1
2-1
3-1
3-2
A-1
Title
Available I/O Cells and Associated Options ................................................
Design Sequence Responsibilities ........................................................... ...
Absolute Maximum Ratings ........................................................................
Recommended Operating Conditions .........................................................
Packages for Cell-Based ASICs ........... ...... ...... ...........................................
Page
1-7
2-6
3-1
3-1
A-1
Introduction to the
Intel 1.5 Micron CHMOS III Cell Library
1
CHAPTER 1
INTRODUCTION TO THE
INTEL 1.5 MICRON CHMOS III CELL LIBRARY
The Intel 1.5 Micron CHMOS III Cell Library provides customers with the building blocks
necessary to design complex semicustom integrated circuits. The 1.5 Micron CHMOS III
Cell Library is composed of pre-designed, fully characterized equivalents of common circuit
elements and Intel standard products. The library includes SSI, MSI, and LSI circuit
elements commonly used in system design. In addition, the library contains VLSiCEL
elements, functional equivalents of Intel standard microcontroller, microprocessor, and
microprocessor support peripheral products.
FEATURES/BENEFITS
•
•
•
•
Over 150 SSI/MSI/LSI logic functions.
A comprehensive cell library provides a wide range of cell-based ASIC solutions. The
library is highlighted by VLSiCEL elements, cell versions of popular Intel standard
microprocessors, microcontrollers, and microprocessor support peripherals. VLSiCEL
elements offer the highest level of microcomputer-based system integration. Intel's cellbased design methodology offers customers the ability to use predefined circuit elements
as building blocks to design complex circuits. The current library includes:
80C51 BH
8-Bit Microcontroller
82C37A
Programmable DMA Controller
82C54
Programmable Interval Timer
82C59A
Programmable Interrupt Controller
82C84A
8086 Clock Generator
80286 Clock Generator
82C284
82C88
8086 Bus Controller
82288
80286 Bus Controller
A complete set of test vectors is provided for each VLSiCEL building block, providing
a guaranteed 0.1 % AQL (Acceptable Quality-Level) or better.
The VC51 Emulator Design Kit facilitates hardware and software debug of 80C51 BH
core plus ASIC designs.
Vser-configurable n-bit counters, registers, multipliers, and magnitude comparators built
. from "telescoping" cells achieve high performance for repetitive functions.
CHMOS III-An advanced 1.5 micron, double-layer metal CMOS process technology
providing high performance, high density, and low power semicustom integrated circuits
with proven manufacturability:·The CHMOS III process is also used to produce Intel's
80386 and 80C51 BH high volume standard products.
•
•
0.7 ns typical gate delay for a 2-input NAND, fanout of 2.
65 MHz typical D flip-flop toggle frequency.
•
CMOS, TTL, and Schmitt Trigger compatible I/O cells available with a variety of
drive levels and ESD protection to 2000V.
inter
•
•
•
INTRODUCTION TO CELL-BASED DESIGN
A complete set of packaging options with lead counts up to 208 pins. Special packaging
configurations and higher pin count packages are available upon request.
The Intel Design Environment provides a comprehensive set of CAE/CAD tools, logic
libraries, and customer support and design services that enable users without IC design
expertise to design their own cell-based ASICs.
Intel's 1.S Micron CHMOS III Cell Library is fully supported on Mentor and Daisy
compatible engineering workstations. Mainframe simulation capability is supported
through Intel technology centers and direct dial-up to Intel factory mainframes.
CELL-BASED DESIGN
Why Cell-Based ASICs?
Semicustom integrated circuits are designed from a variety of functional building blocks
ranging in complexity from individual logic gates to LSI and VLSI functions. Cell-based
ASICs offer the highest level of semicustom integration and are capable of implementing
complex VLSI functions (microprocessors and microcontrollers). They also offer high
performance, increased functionality and better silicon utilization because the individual cells
have been hand-packed to the highest possible densities. Better silicon utilization means lowercost production in high volume. Full custom ICs can provide the same benefits as cell-based
ICs. However, while full custom designs often require years to develop, semicustom chips
can be developed in weeks or months. Well-characterized, easy-to-use automated design
methodologies also typlify semicustom chip development, making ASIC design accessible to
system engineers without specialized IC design experience. System manufacturers realize a
faster time to market, thus giving more time to concentrate on system rather than IC issues.
Why Intel?
Intel believes that to successfully serve its ASIC customers, it must provide customers with
a comprehensive product offering, advanced manufacturing capabilities, a complete CAE
tool set, and design services to support the entire ASIC design process.
•
•
•
•
Product offering. Intel's ASIC product offering includes programmable logic devices,
gate arrays and cell-based ICs, and libraries which contain ASIC versions of Intel
standard products.
Manufacturing expertise. Intel ASIC manufacturing draws on the recognized strengths
of Intel CMOS technology, advanced packaging, and a demonstrated expertise in
assembly and test.
Design tools. Customers may access the Intel libraries on a variety of platforms, including the Daisy Systems and Mentor Graphics compatible workstations. Simulations for
complex designs are supported on mainframes through Intel Technology Centers and
direct dial-up to the Intel factory. The UCS1-EDK provides emulation capability for
UCS1-based designs.
Design services. Intel provides complete documentation for ASIC product lines.
Technology centers offer comprehensive hands-on training courses. And both the gate
array and cell-based product lines are fully second sourced.
intel~
INTRODUCTION TO THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
What is a Standard Cell?
A standard cell can be thought of as a well characterized module containing an individual,
independent, logic circuit. It is a complete functional block with predesigned and precharacterized logic. Intel has designed these cells for optimum electrical performance and silicon
. utilization. The standard SSI/MSI cells in the library have been designed with a fixedheight and variable-width configuration. These cells are arranged horizontally in rows with
routing channels on either side. The height of these routing channels is variable, and is
determined by required metalization interconnect between the cells.
Customers who design with standard cells need only look at a "black box" view of the
functions. Knowledge of or training on gate/transistor level functionality is not necessary,
making the cell-based approach similar to designing with commodity logic or standard
products.
Figure 1-1 is an example of a standard cell.
Large scale functions including the VLSiCEL elements and Intel's special function cells are
designed as "both" variable-width and variable-height cell structures.
CONNECTS TO ROUTING CHANNEL
4"
I
CELL BORDER
G40208
Figure 1-1. Example Standard Cell
INTRODUCTION TO CELL-BASED DESIGN
An Example of a Cell-Based Design
Figure 1-2 depicts a 25,000 "gate" cell-based design where a gate is defined as equal to 4
transistors (the typical equivalent complexity of a 2-input NAND function). When VLSiCEL
and special function cells are used in a cell-based 'ASIC, higher densities are achieved via
the large, custom-designed cells. Intel cell-based ASICs often have 100,000 or more
transistors.
CELL TYPES
Standard Cells
The 1.5 Micron CHMOS III Cell Library is composed of over 150 hard-wired basic logic
building blocks. These standard cells represent SSI and MSI cells, and are as easy to use as
their commodity logic counterparts.
The cell library offers an extensive variety of random logic cells. Included in this category
are AND, OR, NAND, NOR, AND-OR, AND-OR-INVERT, EXCLUSIVE OR and
EXCLUSIVE NOR gates. Inverters and buffers are available with normal drive, high drive,
or 3-state outputs.
I I I I I I I I I I
I--
I
-
I
-
•
•
•
•
•
80C51 BH VLSiCEL
16,384 BYTES OF PROGRAM MEMORY
256 BYTES OF RAM
2,000 GATES OF RANDOM LOGIC
84 TO 196 PIN I/O
--
RAM 256
I
l-
I
I-
I-I--
UC5116
--
II-I--
I--
I--
I-I--
~
l-
r-
I--
I
I
I
I
;" ~
II I I I I I I I I
/
PAD RING
. . . l\
"'
RANDOM LOGIC
G40208
Figure 1-2. Example Cell-Based Design
intel~
INTRODUCTION TO THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
I
The Intel cell library contains a broad range of flip-flops and latches. Flip-flops include D,
JK, and Toggle; latches include transparent, SR, and SR. All bistable devices in the Intel
1.5 Micron CHMOS III Cell Library contain an asynchronous master reset input to aid in
system design. Flip-flop and latch configurations provide enable, 3-state, scan input, and set
functionality. Other standard cell functions in the Intel 1.5 Micron CHMOS III CeIl Library
include multiplexers, decoders/demultiplexers and a parity generator/checker.
Telescoping Cells
Registers, shift registers, counters, adders, and magnitude comparators are all available in
the Intel 1.5 Micron CHMOS III Cell Library as "telescoping" cells. Telescoping cells provide
silicon-efficient, user-configurable implementation of repetitive logic functions.
A telescoping cell is designed with all input pins and output pins on opposite sides of the
cell. Because the outputs from one telescoping cell align with the inputs of another, multistage devices can be defined by the designer without the need for routing channels. Thus,
telescoping cells enhance cell-to-cell continuity in a design, improve the performance of the
circuit, and greatly decrease the area of silicon required to implement a function.
Designjng a telescoping multistage device may require three types of telescoping cells: body
cells, control cells, anq cap cells. Body cells provide the basic function required by a telescoping component. Control cells provide an interface between a body cell and an external
network. Cap cells are used as a driver for any final output (such as carry-out) related to
the overall operation of the device. The use of cap cells is optional. .
In Figure 1-3, a 4-bit counter designed without the use of telescoping cells is compared to
an implementation which uses telescoping cells. In the example without telescoping cells the
design requires the use of 4 routing channels. The 4-bit counter which has been designed
using Intel's telescoping cells requires no routing channels. The si~icon area savings is
approximately equal to the area required to route an additional 20 gates of logic. Also, the
elimination of interconnect delays due to routing significantly improves the performance of
.
the counter c i r c u i t . ·
Cluster Macros
Intel provides customers with the capability to group cells which when placed together
perform a higher level function. During the-layout phase of the design, these cells are physically placed together on-chip-minimizing delays due to interconnect. These cell groups, or
cluster macros, are particularly useful for controlling critical path timing.
Intel
INTRODUCTION TO CELL-BASED DESIGN
4 BIT COUNTER EXAMPLE
WITHOUT TELESCOPING CELLS
USING TELESCOPING CELLS
BIT STAGES
BIT STAGES
G40208
Figure 1-3. Example 4-Bit Counter
1/0 Cells
The Intel cell library contains over 30 types of I/O buffer cells. Input, output, and I/O cells
are available in TTL or CMOS compatible configurations. Input cells are available in both
inverting or non-inverting configurations, and with Schmitt Trigger inputs. Each type of
input cell contains bonding pads as well as input static protection networks. Output cells are
also available in both inverting or non-inverting configurations and with open drain and
3-state outputs. Output cells include bonding pads and output static protection networks.
ESD protection to 2000V is provided.
Table 1-1 shows the available I/O cells and the associated options.
Memory Cells
The most popular Static RAM sizes are available as standard blocks in the cell library. All
RAM cells feature byte-wide organization, with densities ranging from 512 to 8K bits.
VLSiCEL Elements
VLSiCEL building blocks provide the customer with the ability to use Intel standard products
in their design. The VLSiCEL elements are captured· and simulated as complete functions
with fully supported simulation models. Intel has addressed the long-standing test issues that
have prevented the incorponition of embedded microprocessors and complex functions into
intel~
INTRODUCTION TO THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
Table 1-1. Available I/O Cells and Associated Options
1/ 0 Cell Types
Options
Input
TTL and CMOS compatible
Inverting/non-inverting buffers
Schmitt Trigger inputs
Pull-up resistors
Normal and high drive
Output
TTL and CMOS compatible
Inverting/non-inverting buffers
3-state, open drain, push-pull
Multiple output drive levels
Bidirectional
TTL and CMOS compatible
3-state outputs, latched inputs
Multiple output drive levels
semicustom ICs by building in elements of design for testability. All VLSiCEL building
blocks come with a pre-defined set of test vectors, assuring circuit validation and eliminating
test "bottlenecks." Complex chips can be designed in a fraction of the time required for
gate-level implementations. Complete cell descriptions are available for each function (see
Chapter 4, "VLSiCEL Elements and LSI Functions").
CELL SIZE
The standard cells (SSI, MSI) in the 1.5 Micron CHMOS III Cell Library are fixed-height,
cells. Intel expresses the size of these cells in terms of grids. Grid counts
provide a relative measure of the physical size of these cells. The grid count for each cell,
indicated on the cell data sheet, can be used to determine with circuit configuration that
yields the optimum silicon area for a given design.
v~riable-width
1-7
Introduction to the
Intel Design Environment
2
CHAPTER 2
INTRODUCTION TO THE INTEL DESIGN ENVIRONMENT
Intel's design environment provides the customer with a comprehensive set of CAE/CAD
tools, logic libraries, customer support and design services. The design environment enables
users without IC design expertise to design their own Application Specific Integrated Circuits
(ASICs). The libraries support Intel's three ASIC product lines: Cell-Based, Gate Array,
and EPLD. This chapter will focus on the design interface for Intel cell-based ASICs.
AN OVERVIEW OF THE INTEL DESIGN ENVIRONMENT
Intel's design environment includes all the design tools and services required to design cellbased ASI Cs.
The cell-based ASIC design sequence begins with the entering of the design schematic
followed by the generation of a net list (a netlist defines the interconnections between the
cells used in the design). Once a netlist has been specified, simulation tools allow the engineer
to evaluate the functionality of the design, including timing verification. The design engineer
defines the stimulus to exercise the design and verify performance during the simulation
phase. After a successful simulation, automatic place and route tools are used to layout the
design. The design is then re-simulated using the delay times that are computed from the
layout database. After a successful resimulation, prototypes are manufactured, tested, and
delivered.
During all phases of the design process, Intel provides a wide range of support services.
Dedicated regional ASIC specialists provide local design analysis and consultation. Technology centers offer comprehensive customer training and technical support, along with access
to the software toolS running on a variety of hardware platforms. Extensive documentation
is available for all software tools and libraries.
AN OVERVIEW OF THE CELL-BASED DESIGN SEQUENCE
Cell-based ASIC designs can be separated into three major phases: design, layout and verification, and manufacturing.
DESIGN PHASE
The design phase includes device specification, logic design, schematic capture, and simulation of the ASIC device. Figure 2-1 shows the typical flow of events that occur during the
design phase of a cell-based ASIC design.
After becoming familiar with the CAE tools and the Intel 1.5 Micron CHMOS III Cell
Library, the engineer begins the design process by creating a chip specification. This includes
functionality, logic partitioning, and physical requirements (Le., I/O limitations, packaging,
INTRODUCTION TO CELL-BASED DESIGN
CUSTOMER ACTIVITIES
INTEL ACTIVITIES
CUSTOMER TRAINING
OPTIONAL
r----------,
I
f - - -....
PRE-SIMULATION DESIGN REVIEW
I
IL- _ _ _ _ _ _ _ _ _ .JI
" - - -..... PRE-LAYOUT DESIGN REVIEW
G40208
Figure 2-1. Design Phase Flowchart (Technology Center)
power requirements, die size limitations, operating conditions, and performance requirements}. Intel recommends that the engineer adhere to several cell-based design guidelines
and design for testability considerations, which are covered in the Introduction to Cell-Based
Design Course (see the end of this chapter). During this phase, customers may also develop
functional and timing delay simulation vectors and identify critical paths.
Once the preliminary design is complete, an optional pre-design review can be held. The
engineer will then begin selecting cells from the Intel 1.5 Micron CHMOS III Cell Library.
Cells are organized into three general categories within the library: VLSiCEL elements,
2-2
INTRODUCTION TO THE INTEL DESIGN ENVIRONMENT
special function cells, and standard cells, as described earlier in this manual. Data specification sheets can be used to select functions the same way a component catalog is used to
evaluate standard components for board level design.
Upon completion of the chip specification and cell selection, the engineer enters the schematic
on a CAE workstation. Schematic capture can be done at an Intel technology center or on
an Intel-supported workstation at the customer site. Customers may wish to hold an optional
pre-simulation design review with Intel at this time.
A functional simulation and a full timing analysis are required to verify that the design will
meet performance requirements. Simulation may be done using workstation simulation or
Intel-supported mainframe simulators, depending on the complexity of the design. Designs
greater than the approximately 10K gates in complexity often require the computational
power of a mainframe for efficient simulation. This mainframe capability gives designers
maximum flexibility for simulating large designs such as those including VLSiCEL elements.
This phase may require several iterations.
During the design and simulation phase, it is important to consider the testability requirements for the circuit. Intel requires customers to produce designs with 100% observability
when performing an industry standard node toggle test. Fault grading is an available option.
After the design is successfully simulated, a pre-layout design review must occur before
layout can begin. Once approved by both Intel and the customer, the design progresses to
the layout and verification phase.
LAYOUT AND VERIFICATION
Figure 2-2 shows the sequence of events in the layout and verification phase. Placement and
routing of the ASIC design is performed using automatic place and route software. As a
final check Intel factors in the actual delay times as determined from the layout database
(this is called back annotation). The design is then resimulated and post- and pre-layout
simulation results are compared for consistency. When requirements are met, and both Intel
and the customer are satisfied with the results, a final design specification is approved. The
design specification becomes the governing document against which prototype and production components are evaluated. The design then enters the manufacturing phase.
MANUFACTURING PHASE
Figure 2-3 shows the sequence of events in the manufacturing phase. After the layout and
verification phase has been completed, Intel will produce prototypes. These prototypes will
be submitted to the customer for a final review and production approval.
Intel offers rapid turnaround times for its ASIC products. The ASIC circuits are fabricated,
tested, sorted, assembled into packages, and tested again as finished devices. Customer-defined
test patterns are used to verify the device, and standard parametric tests are used to confirm
performance over temperature and supply voltage extremes.
inter
INTRODUCTION TO CELL-BASED DESIGN
CUSTOMER ACTIVITIES
INTEL ACTIVITIES
PRE-LAYOUT DESIGN REVIEW
FINAL DESIGN RELEASE
G40208
Figure 2-2. Layout and Verification Phase Flowchart
PACKAGING
Intel provides a variety of standard IC packages for use with cell-based ASIC designs. Among
the available packaging options are ceramic and plastic Dual In-Line Packages (DIP) with
up to 48 pins, Plastic Leaded Chip Carriers (PLCC) with up to 84 pins, ceramic and plastic
Pin Grid Arrays (PGA) with up to 180 pins, and ceramic and plastic quad flatpacks for up
to 208 pin configurations. Special packages are available upon request. Refer to
Appendix A for more information.
2-4
inter
INTRODUCTION TO THE INTEL DESIGN ENVIRONMENT
CUSTOMER ACTIVITIES
INTEL ACTIVITIES
FINAL DESIGN RELEASE
G40208
Figure 2-3. Manufacturing Phase Flowchart
QUALITY AND RELIABILITY
Intel is committed to the highest possible standards of quality, reliability and customer satisfaction in its products. All ASIC products must meet the same quality and reliability
standards as Intel standard products. Intel insists on building-in quality and reliability for
every product from the very beginning of a technology and product development cycle. Strict
controls and monitors are applied in the manufacturing process to ensure high quality and
reliability. All processes are audited regularly to ensure that they meet specifications. For
additional details on Intel's quality and reliability programs, refer to the Components Quality/
Reliability Handbook, Order Number 210997.
2-5
INTRODUCTJON TO CELL-BASED DESIGN
Intel's cell-based products are shipped to a .1 % AQL level and less than 200 FITs (Failures
In Time).
DESIGN SUPPORT
Intel customers have the option to specify as much or as little design support as needed to
complete their ASIC. Table 2-1 describes the two preferred ASIC design interfaces: design
tasks performed at the customer's site or at an Intel technology center. Customers may also
opt for full service design support.
Intel's design environment provides the necessary design tools and services for all these design
interface alternatives. Customers who choose to develop their ASIC on-site port Intellibraries onto their own CAE systems and design the device within their own development environment. Customers who decide to use Intel technology centers for ASIC development take
advantage of Intel's on-site CAE systems, libraries, and applications support to assist them
during their design effort.
Table 2-1 lists the major steps required to execute a design and specifies the responsibilities
for each party.
Table 2-1. Design Sequence Responsibilities
Activity
Technology Center
Customer Site
Pre-design Start
Design Review
Intel/Customer
Intel/Customer
Cell Selection
Intel/Customer
Customer
Schematic Capture
Intel/Customer
Customer
Simulation
(Functional)
Intel/Customer
Customer
Simulation (Timing)
Intel/Customer
Customer
Pre-Layout Design
Review
Intel/Customer
Intel/Customer
Test Vector
Generation
Intel/Customer
Intel/Customer
Autolayout
Intel
Intel
Post-Layout
Simulation
Intel/Customer
Intel/Customer
Post-Layout
Approval
Intel/Customer
Intel/Customer
Mask Generation
Intel
Intel
Wafer Fab
Intel
Intel
Assembly/Test
Intel
Intel
Prototype Approval
Customer
Customer
2-6
inter
INTRODUCTION TO THE INTEL DESIGN ENVIRONMENT
COMPUTER AIDED ENGINEERING (CAE) TOOLS
The 1.5 Micron CHMOS III Cell Library runs on all engineering workstations from Daisy
Systems and Mentor Graphics. This wide range of compatibility gives designers the flexibility to execute cell-based designs using a variety of CAE hardware.
MAINFRAME-BASED SIMULATION
Simulation requirements for complex designs are often best served by mainframe computational power. Using an Intel mainframe simulator, customers can run simulations that are
too time consuming or not possible to do using a desktop workstation environment. An
integrated design database allows for portability between the mainframe environment and
the workstation environment.
Intel's mainframe computers may be accessed through dial-up from the customer site or via
an Intel technology center.
INTEL TECHNOLOGY CENTERS
Intel technology centers offer training classes, design consultation and technical workstation
support for semicustom chip design, cell-based design libraries, and CAE workstations as
well as access to workstations for schematic capture and simulation. Customers may use the
technology centers to take advantage of Intel's on-site systems, libraries and services. Each
center is equipped with IBM PC-ATs, and Daisy Systems and Mentor Graphics workstations. Direct access to the Intel mainframe is also available for efficient simulation of complex
designs.
Training classes and technical support are available from Intel's technology center ASIC
specialists. The Introduction to Intel Cell-Based Design Course consists of both lecture and
labs emphasizing "hands-on" experience. Lectures address Intel-specific design practices;
labs offer hands-on training in the Intel design environment. Contact the Intel technology
. center nearest you or your local Intel field sales office for scheduling.
INTEL TECHNOLOGY CENTERS
CALIFORNIA
Intel Technology Center
3065 Bowers Avenue
Santa Clara, CA 95051
Tel: (408) 765-2252
MASSACHUSETTS
Intel Technology Center
3 Carlisle Rd.
Westford, MA 01886
Tel: (617) 692-3222
UNITED KINGDOM
Intel Technology Center
Piper's Way
Swindon SN3IRJ
Wiltshire, U. K •
Tel: 0793 696000
The Intel
1.5 Micron CHMOS III Cell Library
3
CHAPTER 3
THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
This chapter provides data sheets for all fixed height, variable width cells in the Intel 1.5
Micron CHMOS III Cell Library, including SSI/MSI functions, telescoping cells, and I/O
cells. The data sheets are preceded by system specifications for the cell library. Information
provided includes Absolute Maximum Ratings and Recommended Operating Conditions,
and Measurement Conditions. A guide to interpreting the cell data sheets is also provided.
Data sheets for VLSiCEL elements and LSI functions are provided in Chapter 4.
CELL LIBRARY SYSTEM SPECIFICATIONS
Table 3-1. Absolute Maximum Ratings
Case Temperature Under Bias
Plastic ........................................................................................................... - 40°C to + 85°C
Ceramic ...................................................................................................... -55°C to +125°C
Storage Temperature ..................................................................................... -65°C to +150°C
DC Supply Voltage (VDD) ....................................................................................... 0 V to 7.0 V
Voltage to Any Pin with
Respect to Ground .......................................................................... -0.5 V to VDD + 0.5 V
Power DisSipation ...... ............................. ...... ........... ...... ... ...... ........... ......... ..... ..... ..... ... 1.0 Watt
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 3-2. Recommended Operating Conditions
DC Supply Voltage (VDD) ............................................................................. +4.5 V to +5.5 V
Case Temperature ................................................................................................ OOG to + 70°C
NOTICE: Cell performance as noted on the cell data sheets are guaranteed when the device is operated
within these parameters.
MEASUREMENT CONDITIONS
Measurement conditions for propagation delay times and 3-state enable and disable times
for I/0 buffer cells are provided in this section. Voltage waveforms are used to illustrate the
data points at which the parameters were determined. Data points were established at
3-1
INTRODUCTION TO CELL-BASED DESIGN
the following conditions over the recommended operating supply voltage and temperature
ranges:
1.
Input rise and fall times = 1 ns.
2.
For open drain output buffers, all propagation delays were measured with a 2 KQ pullup resistor to yDD on the output.
3.
For 3-state output and bi-directional I/O buffers, enable and disable times to and from
the logic low-level were measured with a 1 KQ resistance tied to VDD at the output.
Enable and disable delays to and from the logic high-level were measured with a 1 KQ
resistance tied to VSS at the output.
CMOS
INPUT
\-~~~-= :':v
J.I
I
I
OUTPUT
(OUT-OF-PHASE)
VIL
I
F::
I
~::
TPLH--i
I
I
\
,
I
I
~
TPHL-j
TPLH~
OUTPUT
(IN-PHASE)
I
I
j...=
TPHL-/
Vss
G40208
Figure 3-1. CMOS Input and Bi-Directionall/O Cell Input Propagation Delay Times
\~~~~-=
~UT ----1
I
OUTPUT
(OUT-OF-PHASE)
I
I
TPHL-j
TPLH~
OUTPUT
(IN-PHASE)
I
TPLH--i
I
\
I
~
r
I
I
I
I
TPHL-/
VIH
1.3V
VIL
F::
~::
j...=
Vss
G40208
Figure 3-2. TTL Input and Bi-Directionall/O Cell Input Propagation Delay Times
3-2
THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
INPUT
\ I =-=-=--=--= ::~
----1
I
I
CMOS
OUTPUT
(OUT-OF-PHASE)
I
TPHL-\
TPLH
CMOS
OUTPUT
(IN-PHASE)
V••
1
TPLH---t
I
\l-
,
I
I
I
I
I
TPHL-I
~:~v
~::v
~
VOL
G40208
Figure 3-3. CMOS Output and Bi-Directionall/O Cell Output Propagation Delay Times
INPUT
----1
TTL
OUTPUT
(OUT-OF-PHASE)
I
I
I
TPHL-\
TPLH
TTL
OUTPUT
(IN-PHASE)
1
\ I =-=-=--=--= :;%
V••
TPLH---t
\l-
,
I
I
I
I
I
I
TPHL-I
f-=:.:v
- VOL
~:.:v
~
VOL
G40208
Figure 3-4. TTL Output and Bi-Directionall/O Cell Output Propagation Delay Times
inter
INTRODUCTION TO CELL-BASED DESIGN
G40208
Figure 3-5. CMOS 3-State Output and Bi-Directionall/O Cell Enable and Disable Times
G40208
Figure 3-6. TTL 3-State Output and Bi-Directionall/O Cell Enable and Disable Times
3-4
inter
THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
(This page left intentionally blank)
INTRODUCTION TO CELL-BASED DESIGN
INTERPRETING CELL DATA SHEETS
This section explains how to interpret the individual cell data sheets given in this chapter.
Cell types CULB (Figure 3-7) and PCIO (Figure 3-8) are used to illustrate the various
components of the data sheets.
1. Data Sheet Heading-gives the cell name and a general functional categorization of the
cell.
2. Logic Symbol-a symbolic representation of the cell. Where possible, the symbols given
will match those presented by Intel's engineering workstation models.
3. Functional Description-a complete textual description of the cell's functionality.
4. Grid Count-Intel expresses the size of its cells in terms of grids. A cell's grid count
provides a relative measure of its physical size. Grid counts can be used to determine
optimum silicon utilization of a given design.
5. Logic Table-provides a tabulation relating all output logic states to all necessary possible combinations of input logic states to completely characterize the functionality of the
cell. The following symbols are used in cell logic tables:
LEGEND
o - low-level (steady state)
1 - high-level (steady state)
X - don't care state
Z - high impedance (off) state of a 3-state output
t - transition from low-to-high level
+ - transition from high-to-Iow level
Qo - previous level of Q before the most recent transition state
a - the steady state level at input a
na - complement state of input a
Where necessary, a descriptive representation of logic functionality is used.
6. Pin Description Table-a functional description of the cell's pins; cell pins are illustrated on the logic symbol. For telescoping cells, two categories of pins are given, external pins and telescoping interconnect pins. External pins provide the functional connection
to and from the telescoping function. Telescoping interconnect pins are used for
connecting together the various telescoping cell building blocks. These pins cannot be
used outside of a telescoping function.
inter
THE INTEL 1.5 MICRON CHMOS III CELL LIBRARY
CULB -
CD
TELESCOPING UP COUNTER BODY
~
\I
Inputs
0
NO
CIN-
MR-
-COUT
CLO-i>
ENBOLDO
----'I
DATA _ _
CIN
DATA
LDO
ENBO
1
X
0
0
t
t
t
t
t
t
t
0
X
X
X
X
X
X
1
1
1
X
X
X
X
X
X
0
0
0
0
0
0
1
X
0
0
1
1
X
X
X
X
X
X
1
0
1
0
1
0
1
1
1
X
X
1
1
X
X
MR
1
0
0
·0
0
0
0
0
0
0
0
0
0
NO
COUT
0
1
NQo
NQo
1
0
0
Qo
Qo
0
1
1
,Qo
Qo
Qo
NQo
Qo
Qo
0
0
NQ o
NQo
NQo
Qo
NQo
NQo
Qo
0
0
1
0
Qo
0
NQo
0
Qo
NOTES: -
A CLO signal transition to 1 when MR is 1 will be transparent to the user when the control cell is attached to a
group of body cells.
-
COUT = CIN • Q; a cap cell (CULP) must be used if COUT
is to be connected to circuitry external to a telescoping
block.
Telescoping Up Counter Body
338
~
Outputs
CLO
CULB Description
Function:
Grid Count:
Logic Table
---01
Inputs
Outputs
11
01
0
0
1
1
BUF Description
Buffer, Normal Drive
39
Function:
Grid Count:
BUFH Description
Buffer, High Drive
52
Function: .
Grid Count:
Pin Description·
11
01
Data Input
Output
Input Capacitance
Input Name
Max.
Units
11 BUF
0.10
pF
11 BUFH
0.20
pF
inter
INVERTERS AND BUFFERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
BUF
11 to 01
0.4
0.6
1.2
0.3
0.7
1.8
ns
BUFH
11 to 01
0.4
0.5
1.0
0.3
0.6
1.6
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
01 BUF
0.33
0.73
1.95
0.46
0.68
1.17
ns/pF
01 BUFH
0.15
0.35
0.93
0.22
0.32
0.57
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
BUF2 -
BUFFER WITH DUAL OUTPUT
Logic Table
Inputs
11
---{:L
01
Outputs
11
01
02
0
1
0
1
0
1
02
BUF2 Description
Function:
Grid Count:
Buffer with Dual Output, Normal Drive
52
Pin Description
11
01,02
Data Input
Outputs
Input Capacitance
Input Name
Max.
Units
11
0.20
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11 to 01,02
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.3
0.5
1.0
0.3
0.6
1.6
Units
ns
Load Dependent Delay
Output Name
01,02
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.95
0.46
0.68
1.17
Units
ns/pF
INVERTERS AND BUFFERS
BUFTE -
3-ST ATE BUFFER
Logic Table
Inputs
TE
11
TE
01
0
1
X
0
0
1
0
1
Z
BUFTE Description
Function:
Grid Count:
3-State Buffer with Active Low Output Enable, Normal Drive
65
Pin Description
11
Data Input
3-State Enable Input
Output
TE
01
Input Capacitance
Input Name
Max.
Units
11
0.10
pF
TE
0.40
pF
3-State Output
~apacitance
Output Name
Max.
Units
01(z)
0.25
pF
Outputs
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
Min.
Typ.
Max.
Units
Tplh
11 to 01
0.6
1.0
2.4
ns
Tphl
11 to 01
0.6
1.2
3.1
ns
Tpzh
TE to 01
0.6
1.0
2.4
ns
Tpzl
TE to 01
0.6
1.2
3.1
ns
Tphz
TE to 01
0.6
1.2
3.1
ns
Tplz
TE to 01
0.6
1.0
2.4
ns
Parameter
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
01
0.32
0.75
2.06
ns/pF
Tphl
01
0.44
0.72
1.38
ns/pF
Tpzh
'01
0.32
0.75
2.06
ns/pF
Tpzl
01
0.44
0.72
1.38
ns/pF
inter
INVERTERS AND BUFFERS
BUFTD -
3-ST ATE BUFFER
Logic Table
"y01
Inputs
TO
11
TO
01
0
1
X
1
1
0
0
1
BUFTD Description
Function:
Grid Count:
3-State Buffer with Active High Output Enable, Normal Drive
65
Pin Description
11
Oata Input
3-State Enable Input
Output
TO
01
Input Capacitance
Input Name
Max.
Units
11
0.10
pF
TO
0.25
pF
3-State Output Capacitance
Output Name
Max.
Units
01(z)
0.25
pF
Outputs
Z
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, SV+ / -10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
11 .to 01
0.6
1.1
2.5
ns
Tphl
11 to 01
0.6
1.2
3.0
ns
Tpzh
TO to 01
0.6
1.0
2.4
ns
Tpzl
TO to 01
0.6
1.2
3.1
ns
Tphz
TO to 01
0.6
1.2
3.1
ns
Tplz
TO to 01
0.6
1.0
2.4
ns
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
01
0.32
0.75
2.06
ns/pF
Tphl
01
0.44
0.72
1.38
ns/pF
Tpzh
01
0.32
0.75
2.06
ns/pF
Tpzl
01
0.44
0.72
1.38
ns/pF
inter
GATES
NAN2 -
2 INPUT NAND GATE
Logic Table
11=0-
Inputs
01
12
Outputs
11
12
01
0
X
X
0
1
1
1
0
1
NAN2 Description
Function:
Grid Count:
2 Input NAND, Normal Drive
39
Pin Description
11,12
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11,12
0.35
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11,12 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.2
0.3
0.6
0.2
0.2
0.4
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.95
0.44
0.72
1.35
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
NAN3 -
3 INPUT NAND GATE
Logic Table
Inputs
1121--1
}-
01
13-......._.....,-
Outputs
11
12
13
01
X
X
1
1
1
0
0
X
X
X
0
-X
1
1
0
1
NAN3 Description
Function:
Grid Count:
3 Input NAND, Normal Drive
65
Pin Description
11-13
01
Data Inputs
Output
Input Capacitance
InpulName
Max.
Units
11-13
0.40
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-13 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.2
0.4
1.0
0.2
0.3
0.6
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.96
0.43
0.73
1.42
Units
ns/pF
inter
NAN4 -
GATES
4 INPUT NAND GATE
Logic Table
11b-
Inputs
Outputs
11
12
13
14
01
X
X
X
1
1
1
1
0
12
13
01
14
0
X
X
X
X
0
X
X
X
X
X
1
1
1
0
0
1
NAN4 Description
Function:
Grid Count:
4 Input NAND, Normal Drive
78
Pin Description
11-14
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-14
0.45
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-14 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.3
0.6
1.6
0.2
0.3
0.7
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.97
0.40
0.70
1.38
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
NAN5 -
5 INPUT NAND GATE
11p-
Logic Table
Inputs
12
13
01
14
15
Outputs
11
12
13
14
15
01
0
X
X
X
X
1
X
0
X
X
X
1
X
X
0
X
X
1
X
X
X
0
X
1
X
X
X
X
0
1
1
1
1
1
1
0
NAN5 Description
Function:
Grid Count:
5 Input NAND, Normal Drive
104
Pin Description
Data Inputs
Output
11-15
01
Input Capacitance
Input Name
Max.
Units
11-15
0.55
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-15 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
0.9
2.4
0.2
0.5
1.0
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.75
2.00
0.39
0.70
1.39
Units
ns/pF
inter
NAN6 -
GATES
6 INPUT NAND GATE
Logic Table
Inputs
11
Outputs
11
12
13
14
15
16
01
0
X
X
X
X
X
1
X
0
X
X
X
X
1
X
X
0
X
X
X
1
X
X
X
0
X
X
1
X
X
X
X
0
X
1
X
X
X
X
X
0
1
1
1
1
1
1
1
0
12
13
01
14
15
16
NAN6 Description
6 Input NAND, Normal Drive
117
Function:
Grid Count:
Pin Description
Data Inputs
Output
11-16
01
Input Capacitance
Input Name
Max.
Units
11-16
0.60
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-16 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.5
1.2
3.3
0.3
0.6
1.3
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.34
0.76
2.03
0.37
0.68
1.36
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
NAN7 -
7 INPUT NAND GATE
Logic Table
Inputs
11
12
Outputs
11
12
13
14
15
16
17
01
X
X
X
X
X
X
1
1
1
1
1
1
1
0
1 3 - - r - -.......
14
01
1 5 -......- . . . "
16
17
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
1
1
1
1
1
1
0
0
1
NAN7 Description
Function:
Grid Count:
7 Input NAND, Normal Drive
169
Pin Description
Data Inputs
Output
11-17
01
Input Capacitance
Input Name
Max.
Units
11-17
0.11
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Signal Path
11-17 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.7
3.9
0.5
1.1
3.1
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.96
0.45
0.73
1.39
Units
ns/pF
GATES
NAN8 -
8 INPUT NAND GATE
Logic Table
Inputs
01
Outputs
11
12
13
14
15
16
17
18
01
0
X
X
X
X
X
X
X
1
X
0
X
X
X
X
X
X
1
X
X
0
X
X
X
X
X
1
X
X
X
0
X
X
X
X
1
X
X
X
X
0
X
X
X
1
X
X
X
X
X
0
X
X
1
X
X
X
X
X
X
0
X
0
X
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
0
NAN8 Description
Function:
Grid Count:
8 Input NAND, Normal Drive
182
Pin Description
11-18
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-18
0.11
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-18 to 01
Min.
Tplh
Typ.
Max.
Min •
Tphl
Typ.
Max.
0.9
1.7
3.9
0.5
1.2
3.1
Units
./
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
. Tphl
Typ.
Max.
0.33
0.73
1.96
0.45
0.73
1.39
3-31
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
NOR2 -
2 INPUT NOR GATE
Logic Table
11=L>12.
.
Inputs
01
Outputs
11
12
01
0
1
.X
0
X
1
1
0
0
NOR2 Description
Function:
Grid Count:
2 Input NOR, Normal Drive
52
Pin Description
11,12
01
I
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11,12
0.40
pF
A.C. Characteristics at 0-70°C, 5V + / -1 ooio
Intrinsic Propagation Delay
Signal Path
11, 12 to 01
Min.
Tplh
Typ.
Max.
Min.
Typ~
Max.
0.1
0.3
0.9
0.4
0.6
Q.9
Tphl
Typ.
Max.
0.68
1.19
Tphl
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
0.32
0.75
2.06
0.46
; ..
Units
ns/pF
GATES
NOR3 -
3 INPUT NOR GATE
Logic Table
>-01
:~=1
Inputs
13 - - : I______
I
_
11
12
0
1
X
X
Outputs
13
01
0
0
X
1
X
X
X
1
1
0
0
0
NOR3 Description
3 Input NOR, Normal Drive
Function:
Grid Count:
78
Pin Description
Data Inputs
Output
11-13
01
Input Capacitance
Input Name
Max.
Units
11-13
0.60
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-13to01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.2
0.6
1.8
0.7
1.1
1.7
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.30
0.72
2.01
0.47
0.70
1.25
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
NOR4 -
4 INPUT NOR GATE
Logic Table
11D12
13
.
Inputs
Outputs
11
12
0
1
0
0
0
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
13
14
01
01
14
1
0
0
O.
0
NOR4 Description
Function:
Grid Count:
4 Input NOR, Normal Drive
104
Pin Description
Data Inputs
Output
11-14
01
Input Capacitance
Input Name
Max.
Units
11-14
0.75
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-14 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
1.0
2.9
1.2
1.6
2.5
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.30
0.73
2.05
0.49
0.74
1.34
Units
ns/pF
inter
GATES
NOR5 -
5 INPUT NOR GATE
11p-
Logic Table
12
13
Outputs
Inputs
01
14
15
11
12
13
14
15
01
0
1
X
X
0
X
1
X
X
X
0
X
X
1
X
X
0
X
X
0
X
1
0
0
0
0
0
X
X
X
1
X
X
X
X
1
NOR5 Description
5 Input NOR, Normal Drive
130
Function:
Grid Count:
Pin Description
11-15
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-15
0.15
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-15 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
1.0
2.5
0.8
1.5
3.6
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.18
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
NOR6 -
6 INPUT NOR GATE
Logic Table
Inputs
11
12
Outputs
11
12
13
14
15
16
01
14
0
15
1
0
X
1
X
X
X
X
0
X
X
1
X
X
X
0
X
X
X
1
X
X
0
X
X
X
X
1
X
0
X
X
X
X
X
1
0
0
0
0
0
0
13
01
X
X
X
X
X
16
1
NOR6 Description
6 Input NOR, Normal Drive
143
Function:
Grid Count:
Pin Description
Data Inputs
Output
11-16
01
Input Capacitance
Input Name
Max.
Units
11-16
0.15
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-16 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.5
1.1
2.9
1.0
1.9
4.5
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.19
Units
ns/pF
inter
GATES
NOR7 -
7 INPUT NOR GATE
Logic Table
Inputs
Outputs
11
12
13-.......-
11
12
13
14
15
16
17
01
0
1
X
X
X
X
X
X
0
X
1
X
X
X
X
X
0
X
X
1
X
X
X
X
0
X
X
X
1
X
X
X
0
X
X
X
X
1
X
X
0
X
X
X
X
X
1
X
0
X
X
X
X
X
X
1
1
0
0
0
0
0
0
0
.........
01
14
15-....._~
16
17
NOR7 Description
Function:
Grid Count:
7 Input NOR, Normal Drive
169
Pin Description
11-17
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-17
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-17 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.5
1.3
3.6
1.1
2.1
5.0
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.32
0.75
2.07
0.46
0.68
1.18
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
NORa -
a INPUT NOR GATE
Logic Table
Inputs
01
14
Outputs
11
12
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X·
1
X
X
X
X
X
X
X
X
13
15
16
17
18
01
0
0
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
1
0
0
0
0
0
0
0
0
NORa Description
Function:
Grid Count:
8 Input NOR, Normal Drive
182
Pin Description
11-18
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-18
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-18 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.5
1.3
3.6
1.1
2.1
5.0
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.32
0.75
2.07
0.46
0.68
1.18
Units
ns/pF
GATES
AND2 -
2 INPUT AND GATE
Logic Table
11=012
Inputs
01
Outputs
11
12
01
0
X
1
X
0
1
0
0
1
AND2 Description
Function:
Grid Count:
2 Input AND, Normal Drive
52
Pin Description
11,12
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11,12
0.15
pF
A.C. Characteristics a,t 0-70°C, 5V+ /-10%
Intrinsic Propagation Delay
Signal Path
11,12 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.3
0.6
1.3
0.4
0.9
2.3
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.19
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
3 INPUT AND GATE
AND3 -
Logic Table
Inputs
:: ----3
13
)-
01
Outputs
11
12
13
01
0
X
X
1
X
0
X
1
X
X
0
1
0
0
0
1
____,,-
-~-
AND3 Description
3 Input AND, Normal Drive
65
Function:
Grid Count:
Pin Description
11-13
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-13
0.15
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-13 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.3
0.7
1.6
0.5
1.1
3.0
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.20
Units
ns/pF
inter
GATES
AND4 -
4 INPUT AND GATE
Logic Table
11b~
..
Inputs
01
13
14
.
Outputs
11
12
13
14
01
0
X
X
X
X
0
X
X
1
X
X
X
X
X
0
0
0
0
1
1
0
X
1
0
1
AND4 Description
Function:
Grid Count:
4 Input AND, Normal Drive
78
Pin Description
11-14
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-14
0.15
pF
A.C. Characteristics at 0-70°C, SV + / -10%
Intrinsic Propagation Delay
Signal Path
11-14 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
0.8
1.9
0.6
1.4
3.9
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.69
1.23
3-41
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
AND5 -
5 INPUT AND GATE
11p-
Logic Table
Inputs
Outputs
11
12
13
14
15
01
0
X
X
X
X
1
X
0
X
X
X
1
X
X
0
X
X
1
X
X
X
0
X
1
X
X
X
X
0
1
0
0
0
0
0
1
12
13
01
14
15
AND5 Description
5 Input AND, Normal Drive
104
Function:
Grid Count:
Pin Description
Data Inputs
Output
11-15
01
Input Capacitance
Input Name
Max.
Units
11-15
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-15 to Of
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.5
0.9
2.3
0.7
1.4
3.6
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.32
0.75
2.07
0.46
0.68
1.20
Units
ns/pF
GATES
AND6 -
6 INPUT AND GATE
Logic Table
Inputs
11
Outputs
11
12
13
14
15
16
01
a
x
x
x
x
x
x
a
x
x
x
x
x
x
a
x
x
x
x
x
x
a
x
x
x
x
x
x
a
x
x
x
x
x
x
a
a
a
a
a
a
a
1
1
1
1
1
1
1
12
13
01
14
15
16
AND6 Description
6 Input AND, Normal Drive
130
Function:
Grid Count:
Pin Description
Data Inputs
Output
11-16
01
Input Capacitance
Input Name
Max.
Units
11-16
0.15
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Signal Path
11-16to01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.5
1.0
2.5
0.8
1.6
4.3
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.32
0.75
2.07
0.46
0.68
1.21
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
AND7 -
7 INPUT AND GATE
Logic Table
Inputs
11
Outputs
11
12
13
14
15
16
17
01
X
X
X
X
X
X
0
0
0
0
0
0
12
1 3 -........-
.........
01
14
15--r--16
17
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
1
1
1
1
1
1
0
0
1
d
1
AND7 Description
7 Input AND, Normal Drive
169
Function:
Grid Count:
Pin Description
11-17
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
11-17
0.11
.
Units
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Signal Path
11-17 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.6
1.3
3.3
1.0
2.0
5.0
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.95
0.46
0.68
1.18
Units
~s/pF
inter
GATES
AND8 -
8 INPUT AND GATE
Logic Table
Inputs
01
Outputs
11
12
13
14
15
16
17
18
01
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
0
1
AND8 Description
Function:
Grid Count:
8 Input AND, Normal Drive
182
Pin Description
11-18
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-18
0.11
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-18 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.6
1.3
3.3
1.0
2.0
5.0
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.95
0.46
0.68
1.18
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
OR2 -
2 INPUT OR GATE
Logic Table
Inputs
11=D-
Outputs
11
12
01
0
1
X
0
X
1
0
1
1
01
12
OR2 Description
2 Input OR, Normal Drive
52
Function:
Grid Count:
Pin Description
Data Inputs
Output
11,12
01
Input Capacitance
Input Name
Max.
Units
11,12
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal.Path
11, 12 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.7
1.1
2.2
0.3
0.9
2.5
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.22
Units
ns/pF
inter
GATES
OR3 -
3 INPUT OR GATE
Logic Table
Inputs
>-0'
::=1
11
1 3 -- ---
0
1
X
X
12
Outputs
13
01
0
0
X
1
X
X
X
1
0
1
1
1
OR3 Description
Function:
Grid Count:
3 Input OR, Normal Drive
78
Pin Description
11-13
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-13
0.15
pF
A.C. Characteristics at 0-70°C,· SV + / - 10%
Intrinsic Propagation Delay
Signal Path
11-13to01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.7
1.2
2.5
0.3
0.9
2.6
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.44
0.73
1.40
Units
ns/pF
inter
OR4 -
INTRODUCTION TO CELL-BASED DESIGN
4 INPUT OR GATE
Logic Table
11D12
Inputs
Outputs
11
12
13
14
01
0
1
X
X
X
0
X
1
X
X
0
X
X
1
X
0
X
X
X
1
0
1
1
1
1
01
13
14
OR4 Description
Function:
Grid Count:
4 Input OR, Normal Drive
91
Pin Description
11-14
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-14
0.15
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-14 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.8
1.3
2.7
0.3
0.9
2.5
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.45
0.73
1.39
Units
ns/pF
GATES
ORS -
S INPUT OR GATE
11p-
Logic Table
Inputs
12
13
01
14
15
Outputs
11
12
13
14
15
01
0
1
X
X
X
X
0
X
1
X
X
X
0
X
X
1
X
X
0
X
X
X
1
X
0
X
X
X
X
1
0
1
1
1
1
1
ORS Description
Function:
Grid Count:
5 Input OR, Normal Drive
143
Pin Description
Data Inputs
Output
11-15
01
Input Capacitance
Input Name
Max.
Units
11-15
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-15 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.8
1.3
2.8
0.4
0.9
2.4
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.96
0.35
0.59
1.20
Units
ns/pF
Intel
INTRODUCTION TO CELL-BASED DESIGN
OR6 -
6 INPUT OR GATE
Logic Table
Inputs
11
12
13
13
Outputs
16
01
0
0
1
X
X
X
X
X
X
1
X
X
X
X
X
X
1
0
1
1
1
1
1
1
11
12
14
0
1
0
0
0
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
X
X
15
01
14
15
16
OR6 Description
Function:
Grid Count:
6 Input OR, Normal Drive
156
Pin Description
11-16
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-16
0.15
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11-16 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.6
3.6
0.4
1.0
2.7
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.97
0.35
0.59
1.21
Units
ns/pF
inter
OR7 -
GATES
7 INPUT OR GATE
Logic Table
Inputs
11
12
13
Outputs
11
12
0
1
0
0
0
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
14
15
16
17
01
0
0
1
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
1
0
1
1
1
1
11
1
13-......- - .
01
14
15-......._~
16
17
OR7 Description
Function:
Grid Count:
7 Input OR, Normal Drive
182
Pin Description
11-17
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11-17
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation· Delay
Signal Path
11-17 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.3
2.3
5.0
0.6
1.5
4.4
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.96
0.47
0.68
1.23
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
OR8 -
8 INPUT OR GATE
Logic Table
Inputs
01
Outputs
11
12
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
13
14
15
18
01
0
0
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
0
1
1
1
1
1
1
1
1
16
17
ORB Description
8 Input OR, Normal Drive
Function:
Grid Count:
195
Pin Description
Data Inputs
Output
11-18
01
Input Capacitance
Input Name
Max.
Units
11-18
0.15
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11-18 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.3
2.3
5.0
0.6
1.5
4.4
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.96
0.47
0.68
1.23
Units
ns/pF
GATES
AOR22 -
AND-OR GATE
Logic Table
111
Inputs
Outputs
112
01
111
112
121
122
01
1
1
X
X
1
X
X
1
Any other combination
1
1
0
121
122
AOR22 Description
Function:
Grid Count:
2 AND2 into OR2, Normal Drive
78
Pin Description
111,112,121,122
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
111,112,121,122
0.20
pF
A.C. Characteristics at 0-70°C, SV+ /-10%
Intrinsic Propagation Delay
Signal Path
111,112,121,122 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.7
1.2
2.5
0.6
1.3
3.8
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.47
0.70
1.29
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
AOl22 -
AND-OR INVERT GATE
Logic Table
111
Inputs
112
01
111
121
122
112
121
Outputs
122
01
1
1
X
X
X
X
1
1
Any other combination
0
0
1
AOl22 Description
Function:
Grid Count:
2 AND2 into NOR2, Normal Drive
78
Pin Description
111,112,121,122
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
111,112,121,122
0.50
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Signal Path
111, 112, 121, 122 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.3
0.6
1.7
0.5
0.9
1.7
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.32
0.75
2.05
0.44
0.72
1.38
Units
ns/pF
inter
EXR2 -
GATES
EXCLUSIVE OR GATE
Logic Table
Inputs
Outputs
11
12
01
0
0
1
1
0
1
0
1
0
1
1
0
EXR2 Description
Function:
Grid Count:
2 Input EXCLUSIVE OR, Normal Drive
78
Pin Description
11,12
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11,12
0.30
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
11,12 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.6
1.2
2.8
0.5
1.1
3.1
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.21
Units
ns/pF
inter
EXN2 -
INTRODUCTION TO CELL-BASED DESIGN
EXCLUSIVE NOR GATE
Logic Table
Inputs
Outputs
11
12
01
0
0
1
1
0
1
0
1
1
0
0
1
EXN2 Description
2 Input EXCLUSIVE NOR, Normal Drive
65
Function:
Grid Count:
Pin Description
11,12
01
Data Inputs
Output
Input Capacitance
Input Name
Max.
Units
11,12
0.60
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
11,12 to 01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
0.8
1.8
0.5
1.0
2.6
Units
ns
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.95
0.44
0.72
1.37
Units
ns/pF
FLIP-FLOPS
FFT -
TOGGLE FLIP-FLOP WITH RESET
Logic Table
o
NO
CL
Outputs
Inputs
CL
NMR
X
0
1
1
1
0
t
1
NMR
0
NO
0
1
00
NOo
NO o
00
00
NOo
FFT Description
Function:
Grid Count:
Toggle Flip-Flop with Master Reset
195
Pin Description
Clock Input
Master Reset Input (Asynchronous)
Output
Complemented Output
CL
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, SV + / -10%
Setup and Hold Times
Signal Path
NMR (Inactive) to CL
Min.
2.0
Setup Time
Typ.
3.0
Max.
Min.
4.0
0.6
Hold Time
Typ.
1.6
Max.
4.0
Units
ns
inter
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.7
3.9
1.0
1.9
4.6
ns
NMR to 0
-
-
-
1.1
2.4
6.1
ns
CL to NO
1.2
2.4
5.7
1.2
2.3
5.8
ns
NMR to NO
1.4
2.9
7.2
-
-
-
ns
Signal Path
CL to 0
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.94
0.46
0.68
1.19
ns/pF
Output Name
Units
inter
FLIP-FLOPS
FFTE -
TOGGLE FLIP-FLOP WITH ENABLE AND RESET
Logic Table
o
ENB
CL
Inputs
NO
CL
ENB
NMR
X
X
X
0
1
1
1
1
0
t
t
NMR
Outputs
1
0
1
X
FFTE Description
Toggle Flip-Flop with Enable and Master Reset
247
Function:
Grid Count:
Pin Description
CL
ENS
NMR
Clock Input
Gate Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
ENS
0.20
pF
NMR
0.10
pF
0
NO
0
1
00
00
NOo
NO o
NO o
00
00
NOo
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Signal Path
Setup Time
Typ.
Min.
Max.
Min.
Hold Time
Typ.
Max.
Units
ENS to CL
2.0
3.0
4.5
0.6
1.2
2.8
ns
NMR (Inactive) to CL
2.0
3.0
4.0
0.6
1.2
2.8
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.7
3.9
1.0
1.9
4.6
ns
NMR to 0
-
-
-
1.1
2.4
6.1
ns
CL to NO
1.3
2.5
6.0
1.2
2.5
6.4
ns
NMR to NO
1.4
3.0
7.6
-
-
-
ns
Signal Path
CL to 0
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.94
0.46
0.68
1.21
ns/pF
Output Name
Units
FLIP-FLOPS
FFJK -
JK FLIP-FLOP WITH RESET
Logic Table
Inputs
Outputs
o
CL
K
NO
CL
J
K
NMR
X
X
X
X
X
0
0
1
1
X
0
1
0
1
X
0
1
1
1
1
1
1
0
t
t
t
t
1
NMR
FFJK Description
Function:
Grid Count:
JK Flip-Flop with Master Reset
247
Pin Description
CL
Clock Input
Data Input
Data Input
Master Reset Input (Asynchronous)
Output
Complemented Output
J
K
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
J
0.20
pF
K
0.15
pF
NMR
0.10
pF
0
NO
0
1
00
00
NOo
NOo
0
1
1
0
NOo
00
00
NOo
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
J to CL
2.0
3.0
4.5
0.5
1.2
2.7
ns
KtoCL
2.0
3.0
4.5
0.5
1.2
2.7
ns
NMR (Inactive) to CL
2.0
3.0
4.0
·0.5
1.2
2.7
ns
Signal Path
Units
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.7
3.9
1.0
1.9
4.6
ns
NMR to 0
-
-
-
1.1
2.4
6.1
ns
CL to NO
1.3
2.5
6.0
1.2
2.5
6.3
ns
NMR to NO
1.4
3.0
7.6
-
-
-
ns
Signal Path
CL to 0
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.94
0.46
0.68
1.20
ns/pF
Output Name
Units
FLIP-FLOPS
FLJK -
JK FLIP-FLOP WITH SET AND RESET
Logic Table
Inputs
Outputs
NMS
CL
J
K
NMS
NMR
0
NO
o
X
X
X
0
X
X
X
X
t
t
t
t
0
0
1
1
0
1
0
1
X
X
0
1
0
1
1
1
1
1
1
0*
0
1
NOo
NOo
1
0
1
0
0
1
1
1
1
1
1
1
0*
1
0
NO
X
X
X
X
CL
K
NMR
00
00
0
1
NOo
00
00
NOD
NOTE: *Nonstable state (if NMS and NMR are
changed from 0 to 1 at the same time the
results are unpredictable).
FLJK Description
Function:
Grid Count:
JK Flip-Flop with Master Set and Master Reset
260
Pin Description
Clock Input
Data Input
Data Input
Master Set Input (Asynchronous)
Master Reset Input (Asynchronous)
Output
Complemented Output
CL
J
K
NMS
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.10
pF
J
0.15
pF
K
0.10
pF
NMS
0.30
pF
NMR
0.20
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
2;0
2.0
2.0
2.0
J to CL
K to CL
NMS (Inactive) to CL
NMR (Inactive) to CL
3.0
3.0
3.0
3.0
Max.
Min.
7.0
7.0
4.0
4.0
0
0
1.3
1.3
Hold Time
Typ.
0
0
3.0
3.0
Max.
0
0
6.7
6.7
Units
ns
ns
ns
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to 0
0.9
1.7
4.2
1.0
2.0
5.3
ns
NMS to 0
0.9
1.8
4.9
-
-
-
ns
NMR to 0
-
-
-
0.5
1.1
2.9
ns
CL to NO
1.2
2.4
6.1
1.1
2.3
6.0
ns
NMS to NO
-
-
-
0.4
0.9
2.4
ns
NMR to NO
0.8
1.7
4.3
-
-
-
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.97
0.46
0.68
1.23
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
1.18
ns/pF
Output Name
Units
FLIP-FLOPS
FLJKT -
3-ST ATE JK FLIP-FLOP WITH SET AND RESET
Logie Table
Inputs
Outputs
NMS
CL
J
K
x
x
x x
x x
K
X
X
X
X
TO
0
x
X
X
X
t
t
t
t
1
0
0
0
1
1
X
0
a
CL
NMR
NOTE: -
-
1
1
X
TO
NMR
x
x
0
z
0
0
0
0*
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3-State JK Flip-Flop with Master Set and Master Reset
247
Pin Description
CL
J
K
NMS
NMR
TO
a
1
0
00
00
0
1
NOo
00
*Nonstable state (if NMS and NMR are
changed from 0 to 1 at the same time the
results are unpredictable).
The internal operation of FLJKT is not
affected when TOO is O.
FLJKT Description
Function:
Grid Count:
a
NMS
Clock Input
Data Input
Data Input
Master Set Input (Asynchronous)
Master Reset Input (Asynchronous)
3-State Enable Input (Asynchronous)
Output
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
CL
0.10
pF
J
0.15
pF
K
0.10
pF
NMS
0.30
pF
NMR
0.20
pF
TO
0.25
pF
3-State Output Capacitance
Output Name
Max.
Units
Q(z)
0.25
pF
A.C. Characteristics at 0-70°C, SV + / - 10%
Setup and Hold Times
Signal Path
J to CL
K to CL
NMS (Inactive) to CL
NMR (Inactive) to CL
Min.
2.0
2.0
2.0
2.0
Setup Time
Typ.
3.0
3.0
3.0
3.0
Max.
Min.
7.0
7.0
4.0
4.0
0
0
1.3
1.3
Hold Time
Typ.
0
0
2.9
2.9
Max.
0
0
6.5
6.5
Units
ns
ns
ns
ns
inter
FLIP-FLOPS
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
Clto 0
1.0
2.1
5.5
ns
Tphl
Clto 0
1.2
2.5
6.4
ns
Tplh
NMSto 0
1.0
2.3
6.2
ns
Tphl
NMR to 0
0.7
1.5
4.0
ns
Tpzh
TOtoO
0.6
1.0
2.4
ns
Tpzl
TOtoO
0.6
1.2
3.1
ns
Tphz
TO toO
0.6
1.2
3.1
ns
Tplz
TO to 0
0.6
1.0
2.4
ns
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
0
0.32
0.75
2.07
ns/pF
Tphl
0
0.44
0.72
1.39
ns/pF
Tpzh
0
0.32
0.75
2.06
ns/pF
Tpzl
0
0.44
0.72
1.38
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
FFD -
D FLIP-FLOP WITH RESET
Logic Table
Inputs
Outputs
o
D
NO
CL
NMR
CL
0
NMR
X
0
X
X
t
t
0
1
1
X
0
1
1
1
1
0
NO
0
1
00
NO o
0
1
1
0
00
NOo
FFD Description
D Flip-Flop with Master Reset
208
Function:
Grid Count:
Pin Description
Clock Input
Data Input
Master Reset Input (Asynchronous)
Output
Complemented Output
CL
D
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
D
0.10
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Units
Dto CL
2.0
3.0
4.0
0.7
1.5
3.4
ns
NMR (Inactive) to CL
2.0
3.0
4.0
0.7
1.5
3.4
ns
inter
FLIP-FLOPS
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.1
1.9
4.4
1.1
2.1
5.0
ns
NMR to 0
-
-
-
1.1
2.4
6.0
ns
CL to NO
1.3
2.4
5.7
1.2
2.4
5.8
ns
NMR to NO
1.3
2.7
6.7
-
-
-
ns
Signal Path
CLto 0
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
1.18
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
FFDE -
D FLIP-FLOP WITH ENABLE AND RESET
Logic Table
Inputs
Outputs
o
ENS
o
NO
CL
CL
D
ENB
NMR
X
X
X
X
X
X
0
1
1
1
1
1
0
t
t
t
NMR
1
0
1
0
1
1
X
X
FFDE Description
D Flip-Flop with Enable and Master Reset
273
Function:
Grid Count:
Pin Description
CL
D
Clock Input
Data Input
Gate Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
ENB
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
D
0.20
pF
ENS
0.30
pF
NMR
0.10
pF
0
NO
0
1
00
00
NOo
NO o
0
1
1
0
00
NOo
inter
FLIP-FLOPS
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Units
Dto CL
2.0
3.0
6.0
0.3
0.7
1.5
ns
ENB to CL
2.0
3.0
6.0
0.3
0.7
1.5
ns
NMR (Inactive) to CL
2.0
3.0
4.0
0.3
0.7
1.5
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.1
1.9
4.3
1.1
2.1
5.0
ns
NMR to 0
-
-
-
1.1
2.4
6.0
ns
CL to NO
1.5
2.9
7.1
1.5
3.0
7.7
ns
NMR to NO
1.6
3.2
8.1
-
-
-
ns
Signal Path
CLto 0
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.93
0.46
0.68
1.25
ns/pF
Output Name
Units
inter
INTRODUCTION TO CELL-BASED DESIGN
FLDE -
D FLIP-FLOP WITH ENABLE, SET, AND RESET
Logic Table
Inputs
Outputs
NMS
o
ENB
D
CL
CL
D
ENB
NMS
NMR
0
NO
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0*
1
1
0*
0
0
0
1
NOo
NOo
1
1
X
1
1
1
1
1
00
00
0
1
1
1
1
1
1
0
1
1
0
NO
t
t
t
1
NMR
1
X
0
00
0
NOo
NOTE: *Nonstable state (if NMS and NMR are changed
from 0 to 1 at the same time the results are
unpredictable).
FLOE Description
Function:
Grid Count:
D Flip-Flop with Enable, Master Set, and Master Reset
260
.
Pin Description
CL
D
ENS
NMS
NMR
Clock Input
Data Input
Gate Enable Input
Master Set Input (Asynchronous)
Master Reset Input (Asynchronous)
Output
Complemented Output
o
NQ
Input Capacitance
Input Name
Max.
Units
CL
0.10
pF
D
0.20
pF
ENS
0.30
pF
NMS
0.30
pF
NMR
0.30
pF
FLIP-FLOPS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Units
D to CL
2.0
3.0
6.0
0
0
0
ns
ENS to CL
2.0
3.0
6.0
0
0
0
ns
NMS (Inactive) to CL
2.0
3.0
4.0
1.4
3.0
6.8
ns
NMR (Inactive) to CL
2.0
3.0
4.0
1.4
3.0
6.8
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to 0
0.9
1.7
4.2
1.0
2.0
5.3
ns
NMS to 0
0.8
1.8
4.8
-
-
-
ns
NMR to 0
-
-
-
0.5
1.1
2.9
ns
CL to NO
1.1
2.4
6.0
1.1
2.2
5.8
ns
NMS to NO
-
-
-
0.5
1.1
2.8
ns
NMR to NO
0.8
1.6
4.2
-
-
-
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.46
0.68
1.23
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
1.18
ns/pF
Output Name
3-73
Units
inter
INTRODUCTION TO CELL-BASED DESIGN
FLDET -
3-STATE 0 FLIP-FLOP WITH ENABLE, SET, AND
RESET
Logic Table
NMS
Outputs
Inputs
a
ENB
CL
D
ENB
NMS
NMR
TD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Q
o
CL
TO
0
t
t
t
NMR
1
0
1
0
1
1
X
X
NOTES: -
-
3-State D Flip-Flop with Enable, Master Set, and Master Reset
260
Pin Description
CL
D
ENS
NMS
NMR
TD
o
Clock Input
Data Input
Gate Enable Input
Master Set Input (Asynchronous)
Master Reset Input (Asynchronous)
3-State Enable Input (Asynchronous)
Output
3-74
00
00
0
1
00
*Nonstable state (if NMS and NMR are changed
from 0 to 1 at the same time the results are
unpredictable).
The internal operation of FLDET is not affected
when TD is O.
FLDET Description
Function:
Grid Count:
Z
0*
1
0
Intel
FLIP-FLOPS
Input Capacitance
Input Name
Max.
Units
CL
0.10
pF
D
0.20
pF
ENS
0.30
pF
NMS
0.30
pF
NMR
0.20
pF
TD
0.25
pF
3-State Output Capacitance
Output Name
Max.
Units
Q{z)
0.25
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Units
D to CL
2.0
3.0
6.0
0
0
0
ns
ENS to CL
2.0
3.0
6.0
0
0
0
ns
NMS (Inactive) to CL
2.0
3.0
4.0
1.3
2.9
6.5
ns
NMR (Inactive) to CL
2.0
3.0
4.0
1.3
2.9
6.5
ns
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
CLtoO
1.0
2.1
5.5
ns
Tphl
CL toO
1.2
2.5
6.4
ns
Tplh
NMS to 0
1.0
2.3
6.2
ns
Tphl
NMR to 0
0.7
1.5
4.0
ns
Tpzh
TDtoO
0.6
1.0
2.4
ns
Tpzl
TDtoO
0.6
1.2
3.1
ns
Tphz
TDtoO
0.6
1.2
3.1
ns
Tplz
TDtoO
0.6
1.0
2.4
ns
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
0
0.32
0.75
2.06
ns/pF
Tphl
0
0.44
0.72
1.38
ns/pF
Tpzh
0
0.32
0.75
2.06
ns/pF
Tpzl
0
0.44
0.72
1.38
ns/pF
inter
FLIP-FLOPS
FFDM2 -
0 FLIP-FLOP WITH 2 TO 1 DATA MULTIPLEXER
AND RESET
Logic Table
Inputs
o
DO
Outputs
CL
00
01
50
NMR
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
0
NO
01
SO
CL
0
NO
t
t
t
t
NMR
1
0
1
X
X
X
0
1
0
0
1
1
X
X
FFDM2 Description
Function:
Grid Count:
D Flip-Flop with 2 to 1 Data Multiplexer and Master Reset
260
Pin Description
CL
Clock Input
Data Inputs
Select Input
Master Reset Input (Asynchronous)
Output
Complemented Output
00,01
SO
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
00,01
0.20
pF
SO
0.30
pF
NMR
0.10
pF
0
1
00
NO o
0
1
0
1
1
0
1
0
00
NOo
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
00,01 to CL
2.0
3.0
6.0
0.4
0.8
1.8
ns
SO to CL
2.0
3.0
6.0
0.4
0.8
1.8
ns
NMR (Inactive) to CL
2.0
3.0
4.0
0.4
0.8
1.8
ns
Signal Path
Units
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLto 0
1.1
1.9
4.4
1.1
2.1
5.0
ns
NMR to 0
-
-
-
1.1
2.4
6.0
ns
CL to NO
1.3
2.4
5.7
1.2
2.4
5.8
ns
NMR to NO
1.3
2.7
6.8
-
-
-
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
1.18
ns/pF
Output Name
Units
FLIP-FLOPS
FLDM2 -
D FLIP-FLOP WITH 2 TO 1 DATA MUI-TIPLEXER,
SET, AND RESET
.
Logic Table
Inputs
NM5
o
DO
01
SO
CL
NO
CL
DO
D1
SO
NM5
NMR
0
NO
X
X
X
0
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
X
0
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0*
1
0
0*
0
1
NOo
1
0
1
0
NO o
t
t
t
t
NMR
Outputs
1
X
X
0
1
X
00
0
1
0
1
00
NOTE: *Nonstable state (if NMS and NMR are changed
from 0 to 1 at the same time the results are
unpredictable).
FLDM2 Description
Function:
Grid Count:
D Flip-Flop with 2: 1 Data Multiplexer, Master Set, and Master Reset
260
Pin Description
CL
00,01
SO
NMS
NMR
Clock Input
Data Inputs
Select Input
Master Set Input (Asynchronous)
Master Reset Input (Asynchronous)
Output
Complemented Output
o
NO
Input Capacitance
Input Name
Max.
Units
CL
0.10
pF
00,01
0.20
pF
SO
0.30
pF
NMS
0.30
pF
NMR
0.20
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Min.
Setup Time
"!"yp.
Max.
Min.
Hold Time
Typ.
Max.
00,01 to CL
2.0
3.0
6.0
0
0
0
ns
SO to CL
2.0
3.0
6.0
0
0
0
ns
NMS (Inactive) to CL
2.0
3.0
4.0
1.4
3.0
6.8
ns
NMR (Inactive) to CL
2.0
3.0
4.0
1.4
3.0
6.8
ns
Signal Path
Units
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to 0
0.9
1.7
4.3
1.0
2.0
5.3
ns
NMS to 0
0.8
1.7
4.5
-
-
-
ns
NMR to 0
-
-
-
0.5
1.1
2.9
ns
CL to NO
1.1
2.2
5.7
1.0
2.1
5.4
ns
NMS to NO
-
-
-
0.5
1.0
2.5
ns
NMR to NO
0.7
1.5
3.9
-
-
-
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.46
0.68
1.22
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
1.17
ns/pF
Output Name
Units
FLIP-FLOPS
FFDHI -
POSITIVE EDGE EVENT TRIGGER WITH RESET
Logic Table
Inputs
o
TRIG
NO
TRIG
NMR
X
0
1
1
1
0
t
1
NMR
Outputs
0
NO
0
1
00
NOo
1
0
00
NOo
FFDHI Description
Function:
Grid Count:
Positive Edge Event Trigger with Master Reset
195
Pin Description
TRIG
NMR
Trigger Input
Master Reset Input (Asynchronous)
Output
Complemented Output
o
NO
Input Capacitance
Input Name
Max.
Units
TRIG
0.15
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Signal Path
NMR (Inactive) to TRIG
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
2.0
3.0
4.0
0.3
0.7
1.7
Units
ns
-me
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
TRIG to 0
1.1
1.9
4.4
-
-
-
ns
NMR to 0
-
-
-
1.1
2.4
6.0
ns
TRIG to NO
-
-
-
1.2
2.4
5.8
ns
NMR to NO
1.3
2.7
6.7
-
-
-
ns
Signal Path
Tphl
Typ.
Max.
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.96
0.46
0.68
1.20
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
1.18
ns/pF
Output Name
Units
LATCHES
LAD -
TRANSPARENT D LATCH WITH RESET
Logic Table
a
LE
Inputs
D
NQ
LE
0
NMR
X
X
X
0
1
1
1
0
1
1
NMR
Outputs
0
1
0
NO
0
1
00
NOo
0
1
1
0
LAD Description
Function:
Grid Count:
Transparent D Latch with Master Reset
143
Pin Description
LE
D
NMR
Latch Enable Input
Data Input
Master Reset Input
Output
Complemented Output
o
NO
Input Capacitance
Input Name
Max.
Units
LE
0.10
pF
D
0.10
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
D to LE
2.0
3.5
7.5
0
0
0
ns
NMR (Inactive) to LE
2.0
3.0
6.0
0
0
0
ns
Signal Path
Units
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
LE to 0
1.1
2.4
6.1
1.4
2.8
7.2
ns
Oto 0
1.2
2.3
5.8
1.3
2.8
7.3
ns
NMR to 0
-
-
-
0.8
1.8
5.0
ns
LE to NO
1.1
2.2
5.3
0.9
1.9
5.0
ns
Oto NQ
1.1
2.2
5.4
0.9
1.8
4.7
ns
NMR to NO
0.6
1.2
2.8
-
-
-
ns
. Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.94
0.46
0.67
1.20
ns/pF
NO
0.33
0.73
1.96
0.47
0.69
1.25
ns/pF
Output Name
Units
Intel
LATCHES
LSR -
S':R LATCH WITH RESET
Logic Table
Inputs
s
o
R
NO
NMR
Outputs
S
R
NMR
X
X
0
0
1
1
0
1
0
1
0
1
1
1
1
0
NO
0
1
NOo
1
0
1*
00
0
1
0*
NOTE: *Pseudo stable state (if Sand
R are changed from 1 to 0 at
the same time the results are
unpredictable).
LSR Description
Function:
Grid Count:
S-R Latch with Master Reset
104
Pin Description
S
Latch Set Input
Latch Reset Input
Master Reset Input
Output
Complemented Output
R
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
S
0.15
pF
R
0.21
pF
NMR
0.10
pF
Intel
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ /-10%
Intrinsic Propagation Delay
Min.
Tplh·
Typ.
Max.
Min.
S to 0
1.2
2.5
6.3
-
-
-
ns
RtoO
0.5
1.1
3.1
0.9
1.7
4.1
ns
NMR to 0
0.9
1.8
4.9
1.3
2.7
6.4
ns
5.6
ns
Signal Path
Tphl
Typ.
I
Max.
Units
Sto NO
-
-
-
1.1
2.2
R to NO
0.8
1.3
2.6
.0.4
0.9
2.7
ns
NMR to NO
1.2 .
2.2
5.0
0.7
1.5
4.6
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
. 0.73
1.91
0.46
0.67
1.18
ns/pF
NO
0.33
0.73
1.96
0.47
0.71
0.94
ns/pF
Output Name
Units
LATCHES
LASR -
S-R LATCH WITH ENABLE AND RESET
Logic Table
Inputs
o
s
Outputs
LE
5
R
NMR
X
0
1
1
1
1
X
X
X
0
1
0
1
0
1
1
1
1
1
0
NO
0
1
NOo
NOo
1
0
0*
LE
NO
R
NMR
X
0
0
1
1
00
00
0
1
1*
NOTE: *Pseudo stable state (if Sand Rare
changed from 1 to 0 at the same
time
the
results
are
unpredictable).
LASR Description
Function:
Grid Count:
S-R Latch with Enable and Master Reset
182
Pin Description
LE
Latch Enable Input
Latch Set Input
Latch Reset Input
Master Reset Input
Output
Complemented Output
S
R
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
LE
0.10
pF
S
0.15
pF
R
0.15
pF
NMR
0.10
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, SV + / -10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Sto LE
2.0
4.0
9.0
0
0
0
ns
R to LE
2.5
5.5
12.0
0
0
0
ns
NMR (Inactive) to LE
2.0
3.0
6.0
0
0
0
ns
Signal Path
Units
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
LEto 0
1.2
2.5
6.5
1.4
2.8
7.3
Sto 0
1.4
2.7
6.7
1.3
3.0
8.3
ns
R to 0
-
-
-
1.9
3.8
9.7
ns
NMR to 0
0.8
1.7
4.3
1.1
2.4
6.2
ns
LE to NO
1.1
2.1
5.1
0.9
1.9
5.0
ns
Sto NO
1.1
2.2
5.8
1.1
2.1
5.2
ns
R to NO
1.6
3.1
7.5
-
-
-
ns
NMR to NO
0.6
1.2
2.7
0.5
1.1
3.3
ns
Signal Path
Units
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.95
0.46
0.68
1.21
ns/pF
NO
0.33
0.73
1.96
0.47
0.69
1.25
ns/pF
Output Name
Units
inter
LATCHES
LNSR -
S-R LATCH WITH RESET
Logic Table
Inputs
NS
Q
NR
NQ
NMR
Outputs
NS
NR
NMR
0
NO
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
0
0*
1
0
1
1*
0
1
NO o
00
NOTES: *Pseudo stable state (if NS and
NR are changed from 0 to 1 at
the same time the results are
unpredictable).
LNSR Description
S-R Latch with Master Reset
Function:
Grid Count:
104
Pin Description
Latch Set Input
Latch Reset Input
Master Reset Input
Output
Complemented Output
NS
NR
NMR
o
NO
Input Capacitance
Input Name
Max.
Units
NS
0.11
pF
NR
0.12
pF
NMR
0.12
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
NSto 0
0.5
1.0
2.5
-
-
-
ns
NR to 0
0.4
0.9
2.1
0.6
1.2
3.4
ns
NMR to 0
0.4
0.9
2.0
0.5
1.1
3.1
ns
NS to NO
-
-
-
0.7
1.5
3.9
ns
NR to NO
0.8
1.6
4.2
0.6
1.3
3.9
ns
NMR to NO
0.7
1.5
3.9
0.6
1.3
3.8
ns
Signal Path
Min.
Tphl
Typ.
Max.
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.94
0.46
0.67
1.17
ns/pF
NO
0.33
0.73
1.94
0.46
0.67
0.79
ns/pF
Output Name
Units
LATCHES
LANSR -
S-R LATCH WITH ENABLE AND RESET
Logic Table
Inputs
Outputs
o
NS
LE
NR
NO
NMR.
NS
NR
X
X
X
X
1
1
0
0
1
0
1
0
LE
NMR
X
0
1
1
1
1
1
0
1
1
1
1
0
NO
0
1
NOo
NOo
1
0
1*
00
00
0
1
0*
NOTE: *Pseudo stable state (if NS and NR are
changed from 0 to 1 at the same time
the results are unpredictable).
LANSR Description
S-R Latch with Enable and Master Reset
Function:
Grid Count:
182
Pin Description
LE
NS
NR
NMR
Latch Enable Input
Latch Set Input
Latch Reset Input
Master Reset Input
Output
Complemented Output
o
NO
Input Capacitance
Input Name
Max.
Units
LE
0.10
pF
NS
0.11
pF
NR
0.11
pF
NMR
0.10
pF
inter
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + /-10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
NS to LE
2.5
5.0
10.5
0
0
0
ns
NR to LE
2.0
4.0
8.5
0
0
0
ns
NMR (Inactive) to LE
2.0
3.0
6.0
0
0
0
ns
Signal Path
Units
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
LE to 0
1.2
2.5
6.4
1.4
2.9
7.6
ns
NS to 0
1.2
2.6
6.8
-
-
-
ns
NR to 0
1.1
2.4
6.2
1.4
3.1
8.2
ns
NMR to 0
0.8
1.7
4.3
1.1
2.3
6.1
ns
LE to NO
1.1
2.2
5.3
0.9
1.9
5.0
ns
NS to NO
-
-
-
0.9
2.0
5.4
ns
NR to NO
1.1
2.3
5.9
0.8
1.8
4.8
ns
NMR to NO
0.6
1.2
2.7
0.5
1.1
3.3
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.73
1.94
0.46
0.68
1.21
ns/pF
NO
0.33
0.73
1.96
0.46
0.69
1.25
ns/pF
Output Name
Units
MULTIPLEXERS AND DECODERS
MUX21 -
2-LINE TO 1-LINE MULTIPLEXER
Logic Table
Inputs
Outputs
10
01
10
11
SO
01
0
1
X
X
X
X
0
1
0
0
1
1
0
1
0
1
11
so
MUX21 Description
Function:
Grid Count:
2-Line to I-Line Multiplexer
104
Pin Description
10,11
SO
01
Data Inputs
Select Input
Output
Input Capacitance
Input Name
Max.
Units
10,11
0.20
pF
SO
0.30
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
10,11 to 01
0.7
1.2
2.4
0.5
1.1
2.9
ns
SO to 01
0.6
1.1
2.3
0.5
1.3
3.7
ns
Signal Path
Units
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.95
0.46
0.69
1.22
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
MUX41 -
4-LINE TO 1-LINE MULTIPLEXER
Logic Table
Inputs
Outputs
10
11
10
11
12
13
S1
SO
0
1
X
X
X
X
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
X
X
X
X
X
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
01
01
12
13
50
51
X
X
X
X
MUX41 Description
Function:
Grid Count:
4-Line to I-Line Multiplexer
182
Pin Description
10-13
Data Inputs
Select Input (LSB)
Select Input (MSB)
Output
SO
S1
01
Input Capacitance
Input Name
Max.
Units
10-13
0.20
pF
SO
0.35
pF
S1
0.20
pF
0
1
0
1
0
1
0
1
inter
MULTIPLEXERS AND DECODERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
10-13 to 01
1.0
1.8
4.0
0.7
1.6
4.7
ns
80 to 01
0.9
1.7
3.9
0.8
1.9
5.6
ns
81 to 01
0.9
1.7
3.9
0.8
1.9
5.6
ns
Signal Path
Units
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.97
0.47
0.72
1.35
Units
ns
INTRODUCTION TO CELL-BASED DESIGN
DMX2 ~ 2-LINE TO 4-LINE DEMULTIPLEXER/DECODER
Logic Table
00
G1
01
G2
02
Inputs
Outputs
G1
G2
S1
SO
00
01
02
03
0
X
1
1
1
1
X
0
1
1
1
1
X
X
0
0
1
X
X
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
03
S1
so
1
DMX2 Description
Function:
Grid Count:
2-Line to 4-Line Demultiplexer/Decoder with 2 Enables
299
Pin Description
Enable Input
Enable Input
Select Input (LSB)
Select Input (MSB)
Outputs
G1
G2
SO
S1
00-03
Input Capacitance
Input Name
Max.
Units
G1
0.11
pF
G2
0.11
pF
SO
0.10
pF
S1
0.10
pF
0
0
1
0
0
MULTIPLEXERS AND DECODERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
G1 to 00-03
0.7
1.4
3.2
0.9
1.9
5.0
ns
G2 to 00-03
0.7
1.4
3.2
0.9
1.9
5.0
ns
SO to 00-03
0.7
1.3
3.0
0.6
1.4
3.9
ns
S1 to 00-03
0.7
1.5
3.4
0.8
1.7
4.6
ns
Signal Path
Units
Load Dependent Delay
Output Name
00-03
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.19
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
DMX3 -
3-LINE TO a-LINE DI:MULTIPLEXER/DECODER
Logic Table
00
Inputs
Outputs
01
02
G
52
51
50
00
01
02
03
04
05
06
07
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
03
G
04
05
06
07
52
S1
SO
1
0
1
DMX3 Description
Function:
Grid Count:
3-Line to 8-Line Demultiplexer/Decoder
559
Pin Description
Enable Input
Select Input (LSB)
Select Input
Select Input (MSB)
Outputs
G
SO
S1
S2
00-07
Input Capacitance
Input Name
Max.
Units
G
0.21
pF
SO
0.10
pF
S1
0.10
pF
S2
0.20
pF
1
0
0
MULTIPLEXERS AND DECODERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
G to 00-07
0.7
1.3
3.2
0.8
1.7
4.6
ns
80 to 00-07
0.5
1.1
3.0
0.7
1.3
3.5
ns
81 to 00-07
0.6
1.2
3.2
0.8
1.5
3.8
ns
82 to 00-07
0.7
1.5
3.7
0.9
2.0
5.4
ns
Signal Path
Units
Load Dependent Delay
Output Name
00-07
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.68
1.19
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
CPR -
8/9-BIT PARITY CHECKER/GENERATOR
Logic Table
01
Inputs
Outputs
Number of Inputs 11 thru 19
that are 1
01
1,3,5,7,9
0,2,4,6,8
0
1
CPR Description
Function:
Grid Count:
8/9-Bit Parity Checker/Generator
429
Pin Description
11-18
19
01
Data Inputs
Data Input/Parity Input
Even/Odd Parity Output
Input Capacitance
Input Name
Max.
Units
11-18
0.20
pF
19
0.20
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
11-18 to 01
1.5
3.3
8.8
1.8
3.7
9.4
ns
19 to 01
0.6
1.1
2.5
0.5
1.1
3.0
ns
Signal Path
Units
ARITHMETIC FUNCTIONS
Load Dependent Delay
Output Name
01
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.74
1.96
0.46
0.69
1.24
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
INTRODUCTION TO TELESCOPING CELLS'
Telescoping cells are building blocks from which certain multi-stage logic functions can be
implemented. They are the preferred method of construction for multi-stage logic functions
because they are designed with all input and output pins on opposite sides. Assembled telescoping devices are silicon efficient because the outputs from one telescoping cell align with
the inputs of the adjacent cell, eliminating the need for routing channels. Performance of
the device is optimized because interconnect parasitics between cells is reduced.
Construction of telescoping devices requires two types of cells: body cells and control cells.
Body cells perform the basic function of a telescoping device. Each body cell equates to one
functional bit, hence the number of body cells implemented determines the size of the
completed telescoping device. Control cells provide the interface between external circuitry
and the body cells. A third type of telescoping cells, the cap cell, is available where applicable as a driver for any final output related to the overall operation of the telescoping
device. Cap cells are used when two or more telescoping devices are cascaded together to
form a larger device, or when the final output signal is to be connected to circuitry external
to the telescoping device.
Telescoping devices can be 1-12 bits in length. The 12 bit limit is due to loading limitations
on the control cells. For optimum performance, it is recommended that the length of telescoping devices be kept to a minimum. This can be achieved by splitting large telescoping
devices into multiple blocks.
The following multi-stage functions are implemented with telescoping cells:
Register-Synchronous Register (1-12 bits) with Enable and Master Reset.
•
3-State Register-3-State Synchronous Register (1-12 bits) with Enable and Master
Reset.
Shift Register-Synchronous Shift Register (1-12 bits), Serial Input, Parallel Output
with Enable and Master Reset.
•
Shift Register with Load-Synchronous Shift Register (1-12 bits), Serial Input, Parallel Input, Parallel Output with Load, Enable, and Master Reset.
Up Counter-Synchronous, Cascadable Binary Up Counter 0-12 bits) with Load,
Enable, and Master Reset.
•
•
Up/Down Counter-Synchronous, Cascadable Binary Up/Down Counter (1-12 bits)
with Load, Enable, and Master Reset.
•
•
Adder- Cas cad able Binary Ripple Adder (1-12 bits).
Magnitude Comparator-Cascadable Binary Magnitude Comparator (1-12 bits).
Data sheets for telescoping functions are presented in two ways: first for an assembled telescoping device, then for the associated individual telescoping cells. The data sheets for assembled telescoping devices should prove to be the most useful. They include logic tables and
equations for all potential device configurations for easy functional and performance
evaluation.
TELESCOPING REGISTERS
TELESCOPING REGISTER (REGC, REGB)
Example: 4-bit register
Logic Table
C'?
a
a z
C'?
V
a
a z
v
Inputs
ENB
CL
REGC
REGB
REGB
REGB
REGB
CL
On
ENB
NMR
X
0
X
X
X
0
1
X
X
X
0
1
1
X
0
1
1
1
1
1
t
t
t
1
NMR
Outputs
an
Nan
0
1
Ono
Ono
NOno
NOno
0
1
1
0
Ono
NOno
Telescoping Register Description
Synchronous Register (1 -< n -< 12 bits) with Enable and Master Reset
117 + n (221)
Function:
Grid Count:
Pin Description
CL
On
ENS
NMR
an
Nan
Clock Input
Data Input
Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
Input Capacitance
Input Name
Max.
Units
CL
0.14
pF
On
0.17
pF
ENS
0.10
pF
NMR
0.10
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Parameter
Signal Path
Min.
Typ.
Max.
Units
Setup
On to CL
1.3 - n(0.035)
2.3 - n(0.078)
5.0 - n(0.21)
ns
Hold
Dn to CL
0
0
0
ns
Setup
ENB to CL
Hold
ENB to CL
Setup
NMR (Inactive) to CL
Hold
NMR (Inactive) to CL
1.7
+ n(0.025)
3.5
+ n(0.057)
+ n(0.013)
+ n(O.15)
ns
0
0
ns
2.8 - n(0.010)
3.9 - n(O.089)
ns
0
0
ns
Max.
Units
0
1.8
8.0
0
Intrinsic Propagation Delay
Parameter
Signal Path
Typ.
Min.
Tplh
CL to an
1.3 -+- n(0.035)
2.3
+ n(0.078)
5.1
+ n(O.21)
ns
Tphl
CL to an
1.2
+ n(O.035)
2.3
+ n(0.078)
5.3
+ n(O.21)
ns
Tplh
CL to Nan
1.4
+ n(0.035)
2.7
+ n(0.078)
6;0
+ n(O.21)
ns
Tphl
CL to Nan
1.5
+ n(0.035)
2.7
+ n(0.078)
6.3
+ n(O.21)
ns
Tphl
NMR to an
1.4
+ n(0.033)
2.7
+ n(0.073)
6.2
+ n(O.20)
ns
Tplh
NMR to Nan
1.6
+ n(0.033)
3.0
+ n(O.073)
6.9
+ n(O.20j
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
an
0.33
0.74
1.96
0.46
0.68
1.19
ns/pF
Nan
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
Output Name
Units
TELESCOPING REGISTERS
REGC -
TELESCOPING REGISTER CONTROL
Logic Table
MR
Inputs
ENB
CLO
CL
ENBO
CL
ENB
NMR
CLO
ENBO
MR
X
0
X
X
X
X
0
1
0
1
1
1
X
X
1
0
X
X
X
X
0
1
1
0
0
0
X
X
t
NMR---'
Outputs
1
X
X
t
1
X
X
REGC Description
Function:
Grid Count:
Telescoping Register Control
117
Pin Description
External Pins
CL
ENS
NMR
Clock Input
Enable Input
Master Reset Input (Asynchronous, Active Low)
Telescoping Interconnect Pins
CLO
ENSO
MR
Clock Output
Enable OLitput
Master Reset Output (Asynchronous, Active High)
Input Capacitance
Input Name
Max.
Units
CL
0.14
pF
ENS
0.10
pF
NMR
0.10
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / -10%
, Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to CLO
0.7
1.2
2.5
0.4
1.0
2.8
ns
NMR to CLO
0.7
1.3
3.2
0.6
1.2
3.1
ns
ENB to ENBO
0.4
0.7
1.5
0.4
0.8
2.2
ns
NMR to MR
0.4
0.9
2.2
0.5
1.0
2.4
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
ENBO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
MR
0.33
0.73
1.95
0.47
0.68
1.18
ns/pF
Output Name
Units
IfUeI
TELESCOPING REGISTERS
REGB -
TELESCOPING' REGISTER BODY
Logic Table
Inputs
Q
Outputs
CLO
D
ENBO
MR
1
0
X
X
X
0
1
X
X
X
0
1
1
X
1
0
0
0
0
0
0
NO
NQ
MR
t
t
t
1
CLO
ENBO
0
1
00
00
NOo
NOo
0
1
1
0
00
NOo
NOTE: A CLO signal transition to 1 when MR is
1 will be transparent to the user when
the control cell is attached to a group of
body cells.
0----1
REGS Description
Telescoping Register Body
221
Function:
Grid Count:
Pin Description
External Pins
D
Data Input
Output
Complemented Output
0
NO
Telescoping Interconnect Pins
CLO
ENBO
MR
Clock Input
Enable Input
Master Reset Input (Asynchronous, Active High)
Input Capacitance
Input Name
Max.
Units
CLO
0.15
pF
D
0.17
pF
ENBO
0.26
pF
MR
0.10
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
Setup Time
Typ.
Min.
Max.
Min.
Hold Time
Typ.
Max.
Units
o to CLO
2.0
3.5
7.5
0
0
0
ns
ENBO to CLO
2.0
4.0
9.0
0
0
0
ns
MR (Inactive) to CLO
2.0
3.0
4.0
0
0
0
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO to 0
0.6
1.1
2.6
0.5
1.1
2.8
ns
MRtoO
-
-
-
1.0
1.8
4.0
ns
CLO to NO
0.7
1.5
3.5
0.8
1.5
3.8
ns
MR to NO
1.2
2.1
4.7
-
-
-
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96·
0.46
0.68
1.19
ns/pF
NO
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
Output Name
Units
TELESCOPING REGISTERS
TELESCOPING 3-STATE REGISTER (REGCT, REGBT)
Example: 4-bit 3-state register
Logic Table
Outputs
Inputs
N
a
C')
a
ENB
CL
NMR
T O - -......
CL
On
ENB
NMR
TO
an
X
X
0
t
t
t
1
X
X
X
X
0
1
X
X
X
X
0
1
1
X
X
0
1
1
1
1
1
0
1
1
1
1
1
1
Z
0
Ono
Ono
0
1
Ono
NOTE: The internal operation of the register is not
affected when TO is O.
Telescoping 3-State Register Description
Function:
3-State Synchronous Register (1
Reset
156 + n (234)
Grid Count:
<:
n
<:
12 bits) with Enable and Master
Pin Description
CL
Clock Input
Oata Input
Enable Input
Master Reset Input (Asynchronous)
3-State Enable Input (Asynchronous)
Output
On
ENS
NMR
TO
an
Input Capacitance
Input Name
Max.
Units
CL
0.14
pF
On
0.17
pF
ENS
0.10
pF
NMR
0.10
pF
TO
0.10
pF
INTRODUCTION TO CELL-BASED DESIGN
3-State Output Capacitance
Output Name
Max.
Units
On(z)
0.25
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Parameter
Signal Path
Min.
Typ.
Max.
Units
Setup
On to CL
1.3 - n(0.035)
2.3 - n(0.078)
5.0 - n(0.21)
ns
Hold
On to CL
0
0
0
ns
Setup
ENS to CL
Hold
ENS to CL
Setup
NMR (Inactive) to CL
Hold
NMR (Inactive) to CL
1.7
+ n(0.025)
3.5
+ n(0.013)
8.0
+ n(0.15)
ns
0
0
ns
2.8 - n(0.010)
3.9 - n(0.089)
ns
0
0
ns
Max.
Units
0
1.8
+ n(0.057)
0
Intrinsic Propagation Delay
Parameter
Signal Path
Typ.
Min.
Tplh
CL to an
1.5
+ n(0.035)
2.7
+ n(0.078)
6.3
+ n(0.21)
ns
Tphl
CL to an
1.5
+ n(0.035)
2.8
+ n(0.078)
6.3
+ n(0.21)
ns
Tphl
NMR to an
1.6
+ n(0.033)
3.1
+ n(0.073)
7.1
+ n(0.20)
ns
Tpzh
TO to an
1.0
+ n(0.092)
1.8
+ n(0.21)
4.0
+ n(0.55)
ns
Tpzl
TO to an
1.0
+ n(0.092)
1.9
+ n(0.21)
4.5
+ n(0.55)
ns
Tphz
TO to an
1.0
+ n(0.14)
2.0
+ n(0.20)
5.2
+ n(0.35)
ns
Tplz
TO to an
1.0
+ n(0.14)
1.9
+ n(0.20)
4.7
+ n(0.35)
ns
. 3-110
TELESCOPING REGISTERS
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
an
0.32
0.75
2.06
ns/pF
Tphl
an
0.44
0.72
1.37
ns/pF
Tpzh
an
0.32
0.75
2.06
ns/pF
Tpzl
an
0.44
0.72
1.38
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
REGCT -
TELESCOPING 3-ST ATE REGISTER CONTROL
Logic Table
Outputs
Inputs
MR
ENB
CLO
ENBO
TDO
CL
CL
ENB
NMR
TO
CLO
ENBO
MR
TOO
X
X
X
X
X
0
1
1
1
1
0
X
X
X
X
1
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
0
l'
1
NMR
TD
X
X
X
X
X
X
0
1
l'
1
X
X
X
X
X
X
REGCT Description
Telescoping 3-State Register Control
156
Function:
Grid Count:
Pin Description
External Pins
CL
ENS
NMR
TO
Clock Input
Enable Input
Master Reset Input (Asynchronous, Active Low)
3-State Enable Input (Asynchronous)
Telescoping Interconnect Pins
CLO
ENSO
MR
TOO
Clock Output
Enable Output
Master Reset Output (Asynchronous, Active High)
3-State Enable Output (Async~ronous)
Input Capacitance
I",put Name
Max.
Units
CL
0.14
pF
ENS
0.10
pF
NMR
0.10
pF
TO
0.10
pF
0
1
TELESCOPING REGISTERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to CLO
0.7
1.2
2.5
0.4
1.0
2.8
ns
NMR to CLO
0.7
1.3
3.2
0.6
1.2
3.1
ns
ENB to ENBO
0.4
0.7
1.5
0.4
0.8
2.2
ns
NMR to MR
0.4
0.9
2.2
0.5
1.0
2.4
ns
TO to TOO
0.4
0.7
1.5
0.4
0.8
2.2
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
ENBO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
MR
0.3;3
0.73
1.95
0.47
0.68
1.18
ns/pF
TOO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
REGBT -
TELESCOPING 3-STATE REGISTER BODY
Logic Table
Inputs
Outputs
r----Q
CLO
D
ENBO
MR
TDO
Q
X
1
X
X
X
X
X
X
X
X
1
0
Z
0
1
1
X
1
1
1
1
1
1
0
00
00
0
MR
CLO
ENBO
0
TOO
f
f
f
1
O---lI
1
X
NOTES: -
-
0
0
0
0
0
0
A CLO signal transition to 1 when MR is
1 will be transparent to the user when the
control cell is attached to a group of body
cells.
The internal operation of REGBT is not
affected when TOO is O.
REGBl Description
Function:
Grid Count:
Telescoping 3-State Register Body
234
Pin Description
External Pins
0
a
Data Input
Output
Telescoping Interconnect Pins
CLO
ENBO
MR
TOO
1
00
Clock Input
Enable Input
Master Reset Input (Asynchronous, Active High)
3-State Enable Input (Asynchronous)
TELESCOPING REGISTERS
Input Capacitance
Input Name
Max.
Units
CLO
0.15
pF
D
0.17
pF
ENBO
0.26
pF
MR
0.10
pF
TDO
0.40
pF
3-State Output Capacitance
Output Name
Max.
Units
a(z)
0.25
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
D to CLO
2.0
3.5
7.5
0
0
0
ns
ENBO to CLO
2.0
4.0
9.0
0
0
0
ns
MR (Inactive) to CLO
2.0
3.0
4.0
0
0
0
ns
Signal Path
Units
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
CLO to a
0.8
1.5
3.8
ns
Tphl
CLO to a
0.8
1.6
3.8
ns
Tphl
MR toa
1.2
2.2
4.9
ns
Tpzh
TDO to a
0.6
1.1
2.5
ns
Tpzl
TDO to a
0.6
1.2
3.0
ns
Tphz
TDO to a
0.6
1.2
3.0
ns
Tplz
TDO to a
0.6
1.1
2.5
ns
INTRODUCTION TO CELL-BASED DESIGN
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
Q
0.32
0.75
2.06
ns/pF
Tphl
Q
0.44
0.72
1.37
ns/pF
Tpzh
Q
0.32
0.75
2.06
ns/pF
Tpzl
Q
0.44
0.72
1.38
ns/pF
Intel
TELESCOPING REGISTERS
TELESCOPING SHIFT REGISTER (SHRC, SHRB)
Example: 4-bit shift register
oo
z
C')
N
a
~
a
S
a
z a z a z
C')
~
IN
ENB
CL
NMR
Telescoping Shift Register Description
Function:
Grid Count:
Synchronous Shift Register (1 < n < 12 bits), Serial Input, Parallel Output
with Enable and Master Reset
.
130 + n (221)
Pin Description
CL
IN
ENS
NMR
On
NOn
Clock Input
Serial Data Input
Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
Logic Table
Inputs
Outputs
CL
IN
ENB
NMR
X
0
X
X
X
0
X
X
0
t
t
t
1
1
1
1
X
X
01
N01
0
0
1
1
1
1
1
01 0
01 0
0
1
N01 0
N01 0
1
1
01 0 .
N01 0
0
02
N02
03
N03
0
1
N02 0
N02 0
N01 0
N01 0
N020
0
030
030
020
020
030
1
N03 0
N03 0
N02 0
N02 0
N030
02 0
02 0
01 0
0 10
020
...
lme
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
CL
0.14
pF
IN
0.18
pF
ENS
0.10
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Parameter
Signal Path
Min.
Typ.
Max.
Units
Setup
IN to CL
1.3 - n(0.035)
2.3 - n(0.078)
5.0 - n(0.21)
ns
Hold
IN to CL
0
0
0
ns
Setup
ENS to CL
Hold
ENS to CL
Setup
NMR (Inactive) to CL
Hold
NMR (Inactive) to CL
1.7
+ n(0.025)
3.5
0
1.8
+ n(0.013)
+ n(0.057)
8.0
+ n(0.15)
ns
0
0
ns
2.8 - n(0.010)
3.9 - n(0.089)
ns
0
0
ns
Max.
Units
0
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Tplh
CL to an
1.3
+ n(0.035)
2.3
+ n(0.078)
5.1
+ n(0.21)
ns
Tphl
CL to an
1.2
+ n(0.035)
2.3
+ n(0.078)
5.3
+ n(0.21)
ns
Tplh
CL to Nan
1.7
+ n(0.035)
3.1
+ n(0.078)
6.9
+ n(0.21)
ns
Tphl
CL to Nan
1.7
+ n(0.035)
3.2
+ n(0.078)
7.7
+ n(0.21)
ns
Tphl
NMR to an
1.4
+ n(0.033)
2.7
+ n(0.073)
6.1
+ n(0.20)
ns
Tplh
NMR to Nan
1.8
+ n(0.033)
3.4
+ n(0.073)
7.8
+ n(0.20)
ns
TELESCOPING REGISTERS
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
an
0.33
0.74
1.96
0.47
0.68
1.19
ns/pF
Nan
0.33
0.73
1.94
0.46
0.68
1.23
ns/pF
Output Name
Units
inter
INT~ODUCTION
SHRC -
TO CELL-BASED DESIGN
TELESCOPING SHIFT REGISTER CONTROL
Logic Table
Inputs
IN
MR
ENB
CLO
CL
ENBO
CL
IN
ENB
NMR
CLO
ENBO
MR
X
0
X
X
X
X
X
X
X
X
0
1
0
1
1
1
X
X
1
0
X
X
X
X
0
1
1
0
0
0
X
X
t
1
X
X
NMR---'
Outputs
X
X
t
1
X
X
SHRC Description
Function:
Grid Count:
Telescoping Shift Register Control
130
Pin Description
External Pins
CL
IN
ENB
NMR
Clock Input
Serial Data Input Feedthrough
Enable Input
Master Reset Input (Asynchronous, Active Low)
Telescoping Interconnect Pins
CLO
ENBO
MR
1·
Clock Output
Enable Output
Master Reset Output (Asynchronous, Active High)
NOTE: IN is routed dirElctly through SHRC without buffering to the Serial Data Input signal (IN) of the least
significant (shift left configuration) or most signific~nt (shift right configuration) SHRB cell.
Input
Cap~citance
Input Name
Max.
Units
CL
0.14
pF
IN
0.01
pF
ENB
0.10
pF
NMR
0.10
pF
inter
TELESCOPING REGISTERS
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to CLO
0.7
1.2
2.5
0.4
1.0
2.8
ns
NMR to CLO
0.7
1.3
3.2
0.6
1.2
3.1
ns
ENBto ENBO
0.4
0.7
1.5
0.4
0.8
2.2
ns
NMR to MR
0.4
0.9
2.2
0.5
1.0
2.4
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
.ENBO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
MR
0.33
0.73
1.95
0.47
0.68
1.18
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
SHRB -
TELESCOPING SHIFT REGISTER BODY
Logic Table
Inputs
....----Q
r----NQ
IN
OUT
MR
CLO
IN
ENBO
MR
1
0
X
X
X
X
X
1
0
0
0
0
0
t
t
t
CLO
ENBO
Outputs
1
0
1
0
1
1
X
X
0
NO
OUT
0
1
NOo
NOo
1
OUTo
OUTo
00
00
0
1
00
0
NOo
0
0
1
OUTo
NOTE: A CLO signal transition to 1 when MR is 1 will be
transparent to the user when the control cell is
attached to a group of body cells.
SHRB Description
Function:
Grid Count:
Telescoping Shift Register Body
221
Pin Description
External Pins
0
NO
Output
Complemented Output
Telescoping Interconnect Pins
CLO
IN
ENBO
MR
OUT
Clock Input
Serial Data Input
Enable Input
Master Reset Input (Asynchronous, Active High)
Serial Output
inter
TELESCOPING REGISTERS
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Signal Path
Setup Time
Typ;
Min.
Max.
Min.
Hold Time
Typ.
Max.
Units
IN to CLO
2.0
3.5
7.5
0
0
0
ns
ENBO to CLO
2.0
4.0
9.0
0
0
0
ns
MR (Inactive) to CLO
2.0
3.0
4.0
0
0
0
ns
Intrinsic Propagation Delay
/
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO to 0
0.6
1.1
2.6
0.5
1.1
2.8
ns
MR toO
-
-
-
1.0
1.8
3.9
ns
CLO to NO
1.0
1.9
4.4
1.0
2.0
5.2
ns
MR to NO
1.4
2.5
5.6
-
-
-
ns
CLO to OUT
0.6
1.1
2.6
0.5
1.1
2.8
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.47
0.68
1.19
ns/pF
NO
0.33
0.73
1.94
0.46
0.68
1.23
ns/pF
OUT
0.33
0.74
1.96
0.47
0.68
1.19
ns/pF
Output Name
Units
inter
INTRODUCTION TO CELL-BASED DESIGN
TELESCOPING SHIFT REGISTER WITH LOAD (SHLC, SHLB)
Example: 4-bit shift register with parallel load
c;
C;
N
z
0
S
z
C')
C')
0
o z
oct
oct
0
o z
Telescoping Shift Register with Load Description
Function:
Synchronous Shift Register (1 -< n -< 12 bits), Serial Input, Parallel Input,
Parallel Output with Load, Enable, and Master Reset
156 + n (312)
Grid Count:
Pin Description
Clock Input
Serial Data Input
Parallel Data Input
Load Input
Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
CL
IN
DATAn
LD
ENS
NMR
On
NOn
Logic Table
Outputs
Inputs
CL IN DATAl
X
0
t
t
t
t
1
X
X
X
X
0
1
X
X
X
X
a
X
X
X
DATA2 DATA3
X
X
X
b
'X
X
X
...
LD
X
X
X
c
X
X
X
1
X
X
X
0
0
X
ENB NMR
X
X
0
1
1
1
X
0
1
1
1
1
1
1
01
NOl
0
1
NOlo
NOlo
na
1
01 0
01 0
a
0
1
01 0
0
NOlo
02
N02
03
N03
0
1
N02 0
N020
nb
NOlo
NOlo
N02 0
0
030
030
c
02 0
02 0
030
1
N030
N030
nc
N020
N020
N030
02 0
020
b
01 0
01 0
020
...
TELESCOPING REGISTERS
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
IN
0.22
pF
DATAn
0.17
pF
LD
0.10
pF
ENS
0.10
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Parameter
Signal Path
Min.
Typ.
Max.
Units
Setup
IN to CL
2.3 - n(0.035)
4.8 - n(0.078)
10.5 - n(0.21)
ns
Hold
IN to CL
0
0
0
ns
Setup
DATAn to CL
2.3 - n(0.035)
4.8 - n(0.078)
10.5 - n(0.21)
ns
Hold
DATAn to CL
0
0
0
ns
Setup
LD to CL
Hold
LD to CL
Setup
ENS to CL
Hold
ENS to CL
Setup
NMR (Inactive) to CL
Hold
NMR (Inactive) to CL
2.7
+ n(0.025)
6.0
0
1.7
+ n(0.025)
0
1.8
+ n(0.013)
0
+ n(0.057)
13.5
0
0
3.5
+ n(0.057)
+ n(0.15)
8.0
+ n(0.15)
ns
ns
ns
0
0
ns
2.8 - n(0.010)
3.9 - n(0.088)
ns
0
0
ns
inter
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Parameter
Signal Path
Typ.
Min.
Max.
Units
Tplh
CL to an
1.4
+ n{0.035)
2.5
+ n{0.078)
5.5
+ n{0.21)
ns
Tphl
CL to an
1.3
+ n{0.035)
2.5
+ n{0.078)
5.6
+ n{0.21)
ns
Tplh
CL to Nan
1.9
+ n{0.035)
3.6
+ n{0.078)
8.0
+ n{0.21)
ns
Tphl
CL to Nan
2.0
+ n{0.035)
3.8
+ n{0.078)
8.0
+ n{0.21)
ns
Tphl
NMR to an
1.4
+ n{0.033)
2.7
+ n{0.073)
6.3
+ n{0.20)
ns
Tplh
NMR to Nan
2.1
+ n{0.033)
3.9
+ n{0.073)
8.7
+ n{0.20)
ns
.
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
an
0.33
0.74
1.96
0.46
0.68
1.19
ns/pF
Nan
0.33
0.73
1.94
0.46
0.70
1.30
ns/pF
Output Name
Units
TELESCOPING REGISTERS
SHLC -
TELESCOPING SHIFT REGISTER WITH LOAb,
CONTROL
Logic Table
Inputs
MR
CLO
LOO
ENBO
IN
ENB
CL
CL
IN
LO
ENS
NMR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
t
1
X
X
X
X
NMR
LO
Outputs
0
1
X
X
0
1
CLO
LOO
ENBO
0
1
1
1
1
X
X
X
X
0
X
X
X
X
0
1
X
X
X
X
X
X
X
X
t
1
X
X
X
X
0
1
MR
1
0
0
0
X
X
X
X
SHLC Description
Function:
Grid Count:
Telescoping Shift Register with Load, Control
156
Pin Description
External Pins
CL
IN
LD
ENB
NMR
Clock Input
Serial Data Input Feedthrough
Load Input
Enable Input
Master Reset Input (Asynchronous, Active Low)
Telescoping Interconnect Pins
CLO
LDO
ENBO
MR
Clock Output
Load Output
Enable Output
Master Reset Output (Asynchronous, Active High)
NOTE: IN is routed directly through SHLC without buffering to the Serial Data Input signal (IN) of the least
. significant (shift left configuration) or most significant (shift right configuration) SHLB cell.
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
IN
0.05
pF
LO
0.10
pF
ENB
0.10
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to CLO
0.7
1.2
2.5
0.4
1.0
2.8
ns
NMR to CLO
0.7
1.3
3.2
0.6
1.2
3.1
ns
LO to LOO
0.4
0.7
1.5
0.4
0.8
2.2
ns
ENBto ENBO
0.4
0.7
1.5
0.4
0.8
2.2
ns
NMR to MR
0.4
0.9
2.2
0.5
1.0
2.4
ns
Signal Path
Units
Load Dependent Delay
Min.
Tpih
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
LOO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
ENBO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
MR
0.33
0.73
1.95
0.47
0.68
1.17
ns/pF
Output Name
Units
TELESCOPING REGISTERS
SHIFT REGISTER WITH LOAD, BODY
SHLB -
Logic Table
Inputs
Outputs
Q
NQ
IN
OUT
MR
CLO IN DATA LDO ENBO MR
X
X
X
X
X
X
X
X
t
0
1
1
X
X
X
X
1
0
t
t
t
t
CLO
LOO
ENBO
DATA
0
1
X
X
X
1
1
X
X
0
0
0
1
1
1
1
X
X
1
0
0
0
0
0
0
0
0
NO
OUT
0
1
0
0 0 NOo OUTo
0 0 NOo OUTo
0
1
0
1
1
0
1
0
0
1
0
1
0 0 NOo OUTo
NOTE: A CLO signal transition to 1 when MR is 1 will
be transparent to the user when the control cell
is attached to a group of body cells.
SHLB Description
Function:
Grid Count:
Telescoping Shift Register with Load, Body
312
Pin Description
External Pins
DATA
0
NO
Parallel Data Input
Output
Complemented Output
Telescoping Interconnect Pins
CLO
IN
ENBO
LDO
MR
OUT
Clock Input
Serial Data Input
Enable Input
Load Input
Master Reset Input (Asynchronous, Active High)
Serial Output
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
CLO
0.15
pF
IN
0.17
pF
DATA
0.17
pF
LDO
0.26
pF
ENBO
0.26
pF
MR
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
IN to CLO
3.0
6.0
13.0
0
0
0
ns
DATA to CLO
3.0
6.0
13.0
0
0
0
ns
LDO to CLO
3.0
6.5
14.5
0
0
0
ns
ENBO to CLO
2.0
4.0
9.0
0
0
0
ns
MR (Inactive) to CLO
2.0
3.0
4.0
0
0
0
ns
Signal Path
Units
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO to 0
0.7
1.3
3.0
0.6
1.3
3.1
ns
MR toO
-
-
-
1.0
1.8
4.1
ns
CLO to NO
1.2
2.4
5.5
1.3
2.6
6.5
ns
MR to NO
1.7
3.0
6.5
-
-
-
ns
CLO to OUT
1.0
2.0
5.0
1.1
2.0
4.4
ns
MR to OUT
-
-
-
1.5
2.5
5.4
ns
Signal Path
Units
TELESCOPING REGISTERS
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.46
0.68
1.19
ns/pF
NO
0.33
0.73
1.94
0.46
0.70
1.30
ns/pF
OUT
0.33
0.73
1.94
0.46
0.70
1.30
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
TELESCOPING UP COUNTER (CULC, CULB, CULP)
Example: 4-bit up' counter
CIN
ENB
CULP
COUT
CL
NMR
LD-----"
Telescoping Up Counter Description
Function:
Grid Count:
Synchronous, Cascadable Binary Up Counter (1
Enable, and Master Reset
With CULP - 208 + n (338)
Without CULP - 169 + n (338)
<:
n
<:'
12 bits) with Load,
Pin Description
Clock Input
Carry Input
Data Input
Load Input
Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
Carry Output
CL
CIN
DATAn
LD
ENS
NMR
an
Nan
COUT
Logic Table
Inputs
CL
CIN
X
0
t
t
t
t
X
X
X
X
0
1
X
1
...
Outputs
DATA3
DATA2
DATAl
LD
ENB
NMR
X
X
X
X
X
X
X
X
X
X
X
0
X
X
0
X
c
b
a
1
X
X
X
X
X
X
X
X
X
0
0
X
1
1
X
...
03
N03
0
0
1
1
1
1
1
1
030
030
030
1
N030
N030
nc
N030
030
N030
c
02
N02
0
1
N020
N020
020
020
b
nb
020
N020
01
NOl
0
01 0
01 0
a
01 0
1
N01 0
N01 0
na
N01 0
01 0
N01 0
See Table A
020
N020
TELESCOPING COUNTERS
Table A
Previous State
...
Next State
030
N030
0 20
N020
01 0
NOlo
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
'1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
...
03
N03
02
N02
01
NOl
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
NOTES: COUT = CIN • 01 • 02 • 03 ... ; COUT is generated with combinatorial logic, thus under certain
conditions a short pulse will occur. Therefore, COUT should not be used as a clock signal or for
any other edge triggered signal. A cap cell (CULP) must be used if COUT is to be connected to
circuitry external to a telescoping block.
Input Capacitance
Input Name
Max.
Units
CL
0.14
pF
CIN
0.23
pF
DATAn
0.17
pF
LD
0.10
pF
ENS
0.10
pF
0.10
pF
NMR
-
3-133
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ / -10%
Setup and Hold Times
Parameter
Signal Path
Setup
CIN to CL
Hold
CIN to CL
Setup
Typ.
Min.
1.8
+ n(0.44)
3.8
+ n(0.95)
Max.
7.9
+ n(2.42)
Units
ns
0
0
0
ns
DATAn to CL
1.3 - n(0.035)
2.3 - n(0.078)
5.0 - n(0.21)
ns
Hold
DATAn to CL
0
0
0
ns
Setup
LD to CL
Hold
LD to CL
Setup
1.7
+ n(0.025)
3.5
+ n(0.057)
8.0
+ n(0.15)
ns
0
0
0
ns
ENS to CL
2.7 - n(0.002)
5.4 - n(0.005)
11.7 - n(0.012)
ns
Hold
ENS to CL
0
0
0
ns
Setup
NMR (Inactive) to CL
2.8 - n(0.010)
3.9 - n(0.088)
ns
Hold
NMR (Inactive) to CL
0
0
ns
Max.
Units
1.8
+ n(0.013)
0
Intrinsic Propagation Delay
Parameter
Signal Path
Typ;
Min.
Tplh
CL to an
1.3
+ n(0.035)
2.3
+ n(0.078)
5.1
+ n(0.21)
ns
Tphl
CL to an
1.2
+ n(0.035)
2.3
+ n(0.078)
5.3
+ n(0.21)
ns
Tplh
CL to Nan
1.5
+ n(0.035)
2.7
+ n(0.078)
6.2
+ n(0.21)
ns
Tphl
CL to Nan
1.5
+ n(0.035)
2.8
+ n(0.078)
6.6
+ n(0.21)
ns
Tphl
NMR to an
1.5
+ n(0.033)
2.7
+ n(O.073)
6.1
+ n(0.20)
ns
Tplh
NMR to Nan
1.6
+ n(0.033)
3.1
+ n(0.073)
7.0
+ n(0.20)
ns
Tplh
(n=1)
CL to COUT
Tplh
(2:::;n:::;12)
CL to COUT
1.7
+ n(0.51)
2.8
+ n(1.10)
Tphl
CL to COUT
1.9
+ n(0.035)
4.0
+ n(0.078)
9.1
+ n(0.21)
ns
Tphl
NMR to COUT
2.1
+ n(0.033)
4.3
+ n(0.073)
9.9
+ n(0.20)
ns
Tplh
CIN to COUT
+ n(1.02)
0.3
+ n(2.62)
ns
2.1
0.3
+ n(0.47)
3.9
0.3
9.0
6.2
+ n(2.83)
ns
ns
TELESCOPING COUNTERS
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
an
0.33
0.74
1.97
0.46
0.68
1.20
ns/pF
Nan
0.33
0.74
1.96
0.46
0.68
1.21
ns/pF
COUT
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
CULC -
TELESCOPING UP COUNTER CONTROL
Logic Table
Inputs
CIN
Outputs
MR
CLO
ENB
ENBO
CL
LDO
CL
CIN
LO
ENB
NMR
CLO
LOO
ENBO
MR
X
0
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
0
1
0
1
1
1
X
X
X
X
1
0
X
X
X
X
0
1
X
X
X
X
X
X
X
X
0
1
1
0
0
0
X
X
X
X
t
1
X
X
X
X
NMR--.....
L D - - -......
t
1
X
X
X
X
CULC Description
Function:
Grid Count:
Telescoping Up Counter Control
169
Pin Description
External Pins
CL
CIN
LO
ENS
NMR
Clock Input
Carry In Feedthrough
Load Input
Enable Input
Master Reset Input (Asynchronous, Active Low)
Telescoping Interconnect Pins
CLO
LOO
ENSO
MR
Clock Output
Load Output
Enable Output
Master Reset Output (Asynchronous, Active High)
NOTE: CIN is routed directly through CULC without buffering to the Carry Input signal (CIN) of the least
significant CULS cell. This signal must be tied high into the least significant counter block.
3-136 .
TELESCOPING COUNTERS
Input Capacitance
Input Name
Max.
Units
CL
0.14
pF
CIN
0.01
pF
LD
0.10
pF
ENB
0.10
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to CLO
0.7
1.2
2.5
0.4
1.0
2.8
ns
NMR to CLO
0.7
1.3
3.2
0.6
1.2
3.1
ns
LD to LDO
0.4
0.7
1.5
0.4
0.8
2.2
ns
ENBto ENBO
0.4
0.6
1.2
0.3
0.7
1.8
ns
NMR to MR
0.4
0.9
2.2
0.5
1.0
2.4
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
LDO
0.23
0.52
1.37
0.34
0.50
0.88
ns/pF
ENBO
0.33
0.73
1.95
0,46
0.68
1.18
ns/pF
MR
0.33
0.73
1.95
0.47
0.68
1.18
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
CULB -
TELESCOPING UP COUNTER BODY
Logic Table
Inputs
Q
NQ
CIN
COUT
MR
CLO
ENBO
LDO
DATA
Outputs
CLO
CIN
DATA
LDO
ENBO
MR
1
0
0
t
t
t
t
t
t
t
1
1
X
0
1
X
0
1
0
1
0
1
0
1
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
0
0
1
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
NO
COUT
0
0
0
1
00
00
NOo
NOo
0
1
1
1
0
0
00
00
00
NOo
NOo
NOo
NOo
00
00
00
A CLO signal transition to 1 when MR is 1 will be transparent to the user when the control cell is attached to a
group of body cells.
-
COUT = CIN • 0; a cap cell (CULP) must be used if COUT
is to be connected to circuitry external to a telescoping
block.
External Pins
Data Input
Output
Complemented Output
Telescoping Interconnect Pins
CLO
CIN
ENBO
LDO
MR
COUT
0
NOTES: -
Pin Description
NO
0
NOo
NOo
338
DATA
00
NOo
Telescoping Up Counter Body
Q
0
0
1
0
00
CULB Description
Function:
Grid Count:
00
Clock Input
Carry Input
Enable Input
Load Input
Master Reset Input (Asynchronous, Active High)
Carry Output
TELESCOPING COUNTERS
Input Capacitance
Input Name
Max.
Units
CLO
0.15
pF
CIN
0.22
pF
DATA
0.17
pF
LOa
0.26
pF
ENBO
0.10
pF
MR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Units
CIN to CLO
3.0
6.0
13.0
0
0
0
ns
DATA to CLO
2.0
3.5
7.5
0
0
0
ns
LOa to CLO
2.0
4.0
9.0
a
0
0
ns
ENBO to CLO
3.0
6.0
13.0
0
0
0
ns
MR (Inactive) to CLO
2.0
3.0
4.0
0
0
0
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO to 0
0.6
1.1
2.6
0.5
1.1
2.8
ns
MR toO
-
-
-
1.0
1.8
3.9
ns
CLO to NO
0.8
1.5
3.7
0.8
1.6
4.1
ns
MR to NO
1.2
2.2
4.8
-
-
-
ns
CIN to COUT
0.2
0.4
0.9
0.3
0.6
1.4
ns
CLOtoCOUT
0.9
1.7
4.3
0.8
1.8
4.3
ns
MR to COUT
-
-
-
1.3
2.4
5.4
ns
Signal Path
Units
INTRODUCTION TO CELL-BASED DESIGN
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.97
0.46
0.68
1.20
ns/pF
NO
0.33
0.74
1.96
0.46
0.68
1.21
ns
COUT
1.24
2.84
7.84
1.70
2.63
4.94
ns/pF
Output Name
Units
TELESCOPING COUNTERS
CULP -
TELESCOPING UP COUNTER CAP
Logic Table
CIN
COUT
Inputs
Outputs
CIN
COUT
0
0
1
1
NOTES: -
-
GOUT is generated with
combinational logic, thus
under certain conditions a
short pulse will occur.
Therefore, the carry out
signal should not be used as
a clock signal or for any
other edge triggered signal.
GUPL must be used if GOUT
is to be connected to circuitry external to a telescoping
block.
CULP Description
Function:
Grid Count:
Telescoping Up Counter Carry Out Driver
39
Pin Description
External Pins
I
GOUT
Garry Output
Telescoping Interconnect Pins
I
GIN
Input Capacitance
Input Name
Max.
Units
GIN
0.10
pF
Garry Input
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
CIN to COUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
0.6
1.2
0.3
0.7
1.8
Units
ns
Load Dependent Delay
Output Name
COUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.95
0.46
0.68
1.18
Units
ns/pF
TELESCOPING COUNTERS
TELESCOPING UP/DOWN COUNTER (CUPC, CUPB, CUPP,
CUPP2)
Example: 4-bit up/down counter
0 0z
ECI
ENB
UPON
CL
cUPC
N
0
N
C')
0
z
CUPB
C')
0
0
z
..,. 0..,.
0
z
CUPB
CUPP
EC
CUPP2
CY
NMR
LO
0 0z
CL
C')
0
z
C')
0
0
z
..,.
0
..,.
0
z
EC
ECI
ENB
UPO~
N
N
0
.
CUPC
CUPB
CUPB
BW
NMR
LO
Telescoping Up Counter Description
Synchronous, Cascadable Binary Up/Down Counter (1 -< n -< 12 bits) with
Load, Enable, and Master Reset
With CUPP - 221 + n (429)
With CUPP2 - 338 + n (429)
Without CUPP or CUPP2 - 195 + n(429)
Function:
Grid Count:
Pin Description
CL
ECI
DATAn
UPON
LD
ENB
NMR
an
Nan
EC
CY
BW
Clock Input
End Count Input
Data Input
Count Up/Down Input (Up-Active High)
Load Input
Enable Input
Master Reset Input (Asynchronous)
Output
Complemented Output
End Count Output (CUPP, CUPP2)
Carry Output (CUPP2)
Borrow Output (CUPP2)
INTRODUCTION TO CELL-BASED DESIGN
Logic Table
Outputs
Inputs
...
CL ECI
X
0
t
t
t
t
t
DATAa
DATA2
DATA 1
UPDN
LD
ENB
NMR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
X
X
X
X
0
1
1
X
1
c
b
a
X
X
X
X
X
X
X
X
X
X
X
0
x
x
x
1
X
X
X
X
)
0
0
0
X
X
...
oa
NOa
02
N02
01
N01
0
0
030
030
1
N030
N030
0
020
020
1
N020
N020
0
1
1
1
1
1
1
1
01 0
01 0
1
N01 0
N01 0
c
nc
b
nb
a
na
030
N030
020
N020
01 0
N01 0
01 0
N01 0
See Table A
See Table B
030
N030
N020
020
Table A (Count Down)
Previous State
...
Next State
03 0
N030
020
N020
01 0
N01 0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
...
03
N03
02
N02
1
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
01
N01
1
0
0
1
1
0
1
0
1
0
0
01
N01
1
0
1
0
1
0
1
0
0
1
0
1
0
1
Table B (Count Up)
Previous State
...
Next State
03 0
N03 0
020
N020
01 0
N01 0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
03
N03
02
N02
0
0
0
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
ECI· «UPON. LO)+LO)· ENB. 01 • 02· 03 ...
+ ECI· «UPON· LO· ENB)+ENB). N01 • N02· N03 ...
- CY = ECI· UPON ~ LO· ENB· 01 • 02· 03 ...
- BW = ECI • UPON • LO • ENB • N01 • N02 • N03 ...
- The various end count signals are generated with combinatorial logic, thus under certain conditions a short pulse will occur. Therefore, these signals should not be used as a clock signal or
for any other edge triggered signal.
NOTES: -
EC
0
0
...
=
3-144
inter
TELESCOPING COUNTERS
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
ECI
0.22
pF
OATAn
0.20
pF
UPON
0.20
pF
LO
0.31
pF
ENB
0.20
pF
NMR
0.10
pF
A.C.
Characteris~ics
at 0-70°C, 5V + / - 10%
Setup and H.old Times
Parameter
Signal Path
Setup
ECI to CL
Hold
ECI to CL
Setup
Typ.
Min.
2.3
+ n(0.42)
4.9
+ n(O.77)
Max.
10.4
+ n(2.17)
Units
ns
0
0
0
ns
OATAn to CL
1.3 - n(0.035)
2.3 - n(0.078)
5.0 - n(0.21)
ns
Hold
OATAn to CL
0
0
0
ns
Setup
UPON to CL
11.7 - n(0.13)
ns
Hold
UPON to CL
0
ns
Setup
LO to CL
Hold
LO to CL
Setup
ENB to CL
Hold
ENB to CL
Setup
NMR (Inactive) to CL
Hold
NMR (Inactive) to CL
2.3
+ n(0.034)
4.8
0
2.9
+ n(0.012)
0
7.5
0
3.1
+ n(0.001)
0
1.8
+ n(0.013)
0
+ n(0.024)
+ n(0.026)
14.0
0
6.8
+ n(0.026)
+ n(0.069)
0
15.2
+ n(0.069)
ns
ns
ns
0
0
ns
2.9 - n(0.010)
3.9 - n(0.088)
ns
0
0
ns
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
CL to an
1.3
+ n(0.035)
2.3
+ n(0.078)
5.1
+ n(0.21)
ns
Tphl
CL to an
1.2
+ n(0.035)
2.3
+ n(0.078)
5.3
+ n(0.21)
ns
Tplh
CL to Nan
1.5
+ n(0.035)
2.8
+ n(0.078)
6.4
+ n(0.21)
ns
Tphl
CL to Nan
1.5
+ n(0.035)
2.9
+ n(0.078)
6.8
+ n(0.21)
ns
Tphl
NMR to an
1.4
+ n(0.033)
2.7
+ n(0.073)
6.2
+ n(0.20)
ns
Tplh
NMR to Nan
1.6
+ n(0.033)
3.1
+ n(0.073)
7.2
+ n(0.20)
ns
Tplh
(n=1)
CL to EC CUPP
EC CUPP2
CY
2.3
2.4
2.7
2.7
BW
Tplh
(2~n~12)
CL to EC CUPP
EC CUPP2
CY
BW
Tphl
CL to EC CUPP
EC CUPP2
Cy
BW
Tplh
ECI to EC CUPP
EC CUPP2
CY
BW
Tplh
(n=1)
1.9
2.0
2.3
2.3
+ n(0.49)
+ n(0.49)
+ n(0.49)
+ n(0.49)
3.8
4.0
4.7
4.8
2.5
2.6
3.0
2.9
+ n(0.035)
+ n(0.035)
+ n(0.035)
+ n(0.035)
4.8
5.0
5.9
5.9
0.7
0.9
1.2
1.2
+ n(0.45)
+ n(0.45)
+ n(0.45)
+ n(0.45)
1.1
1.3
2.0
2.1
NMR to EC CUPP
EC CUPP2
CY
2.6
2.7
3.0
3.0
BW
Tplh
(2~n~12)
NMR to EC CUPP
EC CUPR2
CY
BW
Tphl
NMR to EC CUPP
EC CUPP2
CY
BW
4.7
4.9
5.6
5.7
11.2
11.6
13.6
14.2
ns
+ n(0.93)
+ n(0.93)
+ n(0.93)
+ n(0.93)
8.7
9.0
10.8
11.4
+ n(2.58)
+ n(2.58)
+ n(2.58)
+ n(2.58)
ns
+ n(0.078)
+ n(0.078)
+ n(0.078)
+ n(0.078)
11.4
12.0
14.6
14.3
+ n(0.21)
+ n(0.21)
+ n(0.21)
+ n(0.21)
ns
+ n(0.85)
+ n(0.85)
+ n(0.85)
+ n(0.85)
2.0
2.3
4.1
4.7
+ n(2.38)
+ n(2.38)
+ n(2.38)
+ n(2.38)
ns
5.0
5.2
5.9
6.0
12.3
12.7
14.5
15.1
ns
2.1
2.2
2.5
2.5
+ n(0.45)
+ n(0.45)
+ n(0.45)
+ n(0.45)
4.1
4.3
5.0
5.1
+ n(0.85)
+ n(0.85)
+ n(0.85)
+ n(0.85)
8.8
9.1
10.9
11.5
+ n(2.38)
+ n(2.38)
+ n(2.38)
+ n(2.38)
ns
2.6
2.7
3.1
2.9
+ n(0.033)
+ n(0.033)
+ n(0.033)
+ n(0.033)
4.7
4.9
5.8
5.8
+ n(0.073)
+ n(0.073)
+ n(0.073)
+ n(0.073)
11.1
11.7
14.3
14.0
+ n(0.20)
+ n(0.20)
+ n(0.20)
+ n(0.20)
ns
inter
TELESCOPING COUNTERS
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
an
0.33
0.74
1.96
0.47
0.68
1.19
ns/pF
Nan
0.33
0.74
1.96
0.46
0.68
1.20
ns/pF
EC CUPP
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
EC CUPP2
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
CY
0.33
0.74
1.95
0.46
0.68
1.18
ns/pF
BW
0.33
0.74
1.95
0.46
0.68
1.19
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
TELESCOPING UP IDOWN COUNTER CONTROL
CUPC -
Logic Table
NECI,
MR
ECI
ENB
UPDN
CL
CLO
so
S1
NMR
LD
Inputs
Outputs
CL ECI UPON LO ENB NMR
CLO NECI 50 51 MR
X
t
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
X
X
X
X
X
0
0
X
1
X
X
X
X
X
X
1
1
0
1
X
X
0
1
1
1
X
X
X
X
X
X
1
t
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
CUPC Description
Function:
Grid Count:
Telescoping Up/Down Counter Control
195
Pin Description
External Pins
CL
ECI
UPON
LD
ENS
NMR
Clock Input
End Count Input
Count Up/Down Input (Up-Active High)
Load Input
Enable Input
Master Reset Input (Asynchronous, Active Low)
Telescoping Interconnect Pins
CLO
NECI
50
51
MR
Clock Output
End Count Output
Control Output (L5B)
Control Output (M5B)
Master Reset Output (Asynchronous, Active High)
NOTE: ECI must be tied high into the least significant counter block.
X
X
X
X
0
0
1
1
X
X
X
X
X
X
0
1
0
1
X
X
1
0
0
0
X
X
X
X
X
X
TELESCOPING COUNTERS
Input Capacitance
Input Name
Max.
Units
CL
0.15
pF
ECI
0.10
pF
UPON
0.20
pF
LO
0.31
pF
ENS
0.20
pF
NMR
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CL to CLO
0.7
1.2
2.5
0.4
1.0
2.8
ns
NMR to CLO
0.7
1.3
3.2
0.6
1.2
3.1
ns
Eel to NECI
0.1
0.2
0.4
0.2
0.2
0.3
ns
LO to 80
0.6
1.0
2.0
0.4
0.9
2.5
ns
ENS to 80
0.8
1.5
3.2
0.6
1.2
3.3
ns
UPON to 81
0.5
0.8
1.7
0.5
1.0
2.7
ns
LO to 81
0:6
1.0
2.0
0.4
1.1
3.0
ns
ENS to 81
0.4
0.8
1.7
0.6
1.4
3.7
ns
NMR to MR
0.4
0.9
2.2
0.5
1.0
2.4
ns
Signal Path
Units
Intel
INTRODUCTION TO CELL-BASED DESIGN
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
NECI
1.24
2.84
7.82
1.70
2.63
4.94
ns/pF
80
0.23
0.52
1.38
0.34
0.51
0.94
ns/pF
81
0.23
0.52
1.37
0.34
0.51
0.97
ns/pF
MR
0.33
0.73
1.95
0.47
0.68
1.19
ns/pF
Output Name
Units
in1er
TELESCOPING COUNTERS
TELESCOPING UP IDOWN COUNTER BODY
CUPS -
Logic Table
Inputs
CLO
NECI
DATA
SO
51
MR
Q
NQ
1
1
1
1
NO
0
0
X
X
X
0
1
1
1
0
0
0
NEC
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
1
1
1
NOo
NOo
NO o
0
NECI
MR
CLO
1
0
0
0
t
t
t
t
t
t
t
t
t
50
51
DATA
Outputs
1
0
1
0
1
x
0
1
1
1
1
1
0
0
NOTES: -
-
X
1
X
X
X
0
0
0
0
X
0
0
0
1
1
1
1
1
1
1
X
X
X
X
X
X
X
0
1
0
0
1
1
1
1
1
1
NOo
00
00
NOo
NOo
00
00
00
00
0
NOo
NOo
NOo
1
1
1
0
0
00
00
00
NOo
NOo
NOo
Telescoping Up/Down Counter Body
429
Pin Description
External Pins
DATA
0
NO
Data Input
Output
Complemented Output
Telescoping Interconnect Pins
CLO
NECI
SO
S1
MR
NEC
1
0
1
1
00
.
NO o
NOo
1
00
1
00
1
1
0
1
1
00
NOo
A CLO signal transition to 1 when MR is 1 will be
transparent to the user when the control cell is
attached to a group of body cells.
NEC = NECI • ill:!PDN • LD) + LD) • ENB • 0 +
NECI • «UPON • LD • ENB) + ENB) • NO.
NEC cannot be used as a final end count output
signal; a cap cell (CUPP or CUPP2) must be used if
external circuitry is to be connected to an end count
signal.
CUPB Description
Function:
Grid Count:
NEC
Clock Input
End Count Input
Control Input (LSB)
Control Input (MSB)
Master Reset Input (Asynchronous, Active High)
End Count Output
inter
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
CLO
0.15
pF
NECI
0.10
pF
DATA
0.20
pF
80
0.20
pF
81
0.20
pF
MR
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
Units
NEel to CLO
3.0
6.5
14.5
0
0
0
ns
DATA to CLO
2.0
3.5
7.5
0
0
0
ns
80 to CLO
3.0
6.5
14.5
0
0
0
ns
81 to CLO
2.5
3.0
11.5
0
0
0
ns
MR (Inactive) to CLO
2.0
3.0
4.0
0
0
0
ns
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CLO to 0
0.6
1.1
2.6
0.5
1.1
2.8
ns
MRtoO
-
-
-
1.0
1.8
4.0
ns
CLO to NO
0.8
1.6
3.9
0.8
1.7
4.3
ns
MR to NO
1.2
2.2
5.0
-
-
-
ns
NEel to NEC
0.4
0.6
1.4
0.3
0.6
1.9
ns
CLO to NEC
1.3
2.6
6.4
1.1
2.5
6.9
ns
81 to NEe
0.4
0.8
1.8
0.4
0.9
3.0
ns
MR to NEC
1.7
3.1
7.2
1.6
3.1
8.3
ns
Signal Path
Units
inter
TELESCOPING COUNTERS
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0
0.33
0.74
1.96
0.47
0.68
1.19
ns/pF
NO
0.33
0.74
1.96
0.46
0.68
1.20
ns/pF
NEC
1.24
2.84
7.83
1.51
2.52
4.76
ns/pF
Output Name
Units
inter
INTRODUCTION TO CELL-BASED DESIGN
CUPP -
TELESCOPING UP IDOWN COUNTER CAP
Logic Table
NEC
Inputs
Outputs
NEC
EC
0
1
1
0
EC
NOTE: EC is generated with combinato-
rial logic, thus under certain
conditions a short pulse will
occur. Therefore, EC should not
be used as a clock signal or for
any other edge triggered signal.
cupp Description
Function:
Grid Count:
Telescoping Up/Down Counter End Count Driver
26
Pin Description
External Pins
I
EC
End Count Output
Telescoping Interconnect Pins
I
NEC
Input Capacitance
Input Name
Max.
Units
NEC
0.28
pF
End Count Input
inter
TELESCOPING COUNTERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
NEC to EC
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.1
0.2
0.3
0.2
0.2
0.3
Units
ns
Load Dependent Delay
Output Name
EC
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.95
0.46
0.68
1.18
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
TELESCOPING UP IDOWN COUNTER CAP
CUPP2 -
Logic Table
Inputs
EC .
NEC
50
cy
51
BW
Outputs
50
51
NEC
EC
CY
BW
X
X
0
0
1
1
0
1
0
1
1
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
0
NOTE: EC, CY, and BW are generated with
combinatorial logic, thus under certain
conditions a short pulse will occur.
Therefore, these signals should not be
used as a clock signal or for any other
edge triggered signal.
CUPP2 Description
Function:
Grid Count:
Telescoping Up/Down Counter End Count/Carry/Borrow Driver
143
Pin Description
External Pins
EC
CY
BW
End Count Output
Carry Output
Borrow Output
Telescoping Interconnect Pins
End Count Input
Control Input (L5B)
Control Input (M5B)
NEC
SO
51
Input Capacitance
Input Name
Max.
Units
NEC
0.36
pF
50
0.28
pF
51
0.23
pF
TELESCOPING COUNTERS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
NEC to EC
0.1
0.2
0.3
0.2
0.2
0.3
ns
NEC to CY
0.4
0.9
2.1
0.6
1.1
2.9
ns
SO to CY
0.4
1.0
2.7
0.8
1.4
3.7
ns
S1 to CY
0.6
1.1
2.8
0.7
1.4
3.7
ns
NECto BW
0.4
0.9
2.2
0.5
1.0
2.6
ns
SO to BW
0.4
0.9
2.3
0.7
1.4
3.3
ns
S1 to BW
0.4
1.0
2.6
0.9
1.6
3.7
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
EC
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
CY
0.33
0.74
1.95
0.46
0.68
1.18
ns/pF
BW
0.33
0.74
1.95
0.46
0.68
1.19
ns/pF
Output Name
Units
inter
INTRODUCTION TO CELL-BASED DESIGN
TEL.ESCOPING ADDER (ADDC, ADDB, ADDP)
Example: 4-bit adder
Logic Table
CIN
AD DC ADDB
ADDB
ADDB
(LSB)
ADDB
ADDP
COUT
(MSB)
Inputs
Outputs
CINn An Bn
SUMn COUTn
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
A1 B1 A2 B2 A3 B3 A4 B4
NOTES: -
GOUT = GOUTn(msb)
GINn(lsb)
GIN,
GINn = GOUTn-1
A cap cell (ADDP) must
be used if GOUT is to
be connected to circuitry external to a telescoping block.
Telescoping Adder Description
Function:
Grid Count:
Cascadable Binary Ripple Adder (1 -< n -< 12 bits)
With ADDP - 52 + n(169)
Without ADDP - 13 + n (169)
Pin Description
Garry Input
Data Input
Data Input
Output
Garry Output
GIN
An
Bn
SUMn
GOUT
3-158
inter
TELESCOPING ARITHMETIC FUNCTIONS
Input Capacitance
Input Name
Max.
Units
CIN
0.31
pF
An
0.26
pF
Bn
0.26
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
An, Bn to SUMn
1.3
2.4
5.6
ns
Tphl
An, Bn to SUMn
0.9
2.2
6.0
ns
Tplh
(2::sn::s12)
A1, B1 to SUMn
-0.2
+ n(0.62)
-0.3
+ n(1.24)
-1.6
+ n(3.34)
ns
Tphl
(2::sn::S12)
A1, B1 to SUMn
- 0.3
+ n(0.62)
-0.3
+ n(1.24)
-0.9
+ n(3.34)
ns
Tplh
CIN to SUMn
-0.1
+ n(0.62)
-0.3
+ n(1.24)
-1.3
+ n(3.34)
ns
Tphl
CIN to SUMn
-0.2
+ n(0.62)
-0.3
+ n(1.24)
-0.6
+ n(3.34)
ns
5.0
ns
+ n(3.34)
ns
3.8
ns
+ n(3.34)
ns
Tplh
(n=1)
A1, B1 to COUT
Tplh
(2::sn::s12)
A1, B1 to COUT
Tphl
(n=msb)
An, Bn to COUT
Tplh
1.0
0.1
+ n(0.62)
2.1
0.1
+ n(1.24)
0.8
CIN to COUT
0.2
+ n(0.62)
-0.4
1.6
0.1
+ n(1.24)
-0.1
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
SUMn
0.33
0.73
1.93
0.47
0.67
1.23
ns/pF.
COUT
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
Output Name
Units
inter
INTRODUCTION TO CELL-BASED DESIGN
ADDC -
TELESCOPING ADDER CONTROL
C1N-D
ADDC Description
Function:
Grid Count:
Telescoping Adder Control
13
Pin Description
External Pins
I
CIN
Carry Input Feedthrough
NOTE: CIN is routed directly through ADDC without buffering to the Carry Input signal (CIN) of the least
significant ADDS cell.
Input Capacitance
Input Name
Max.
Units
CIN
0.05
pF
TELESCOPING ARITHMETIC FUNCTIONS
ADDB -
TELESCOPING ADDER BODY
Logic Table
Inputs
Outputs
r----SUM
CIN
COUT
A - -....
CIN
A
B
SUM
COUT
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
1
1
1
B - - -....
NOTE: A cap cell (ADDP) must be used
if GOUT is to be connected to
circuitry external to a telescoping
block.
AD DB Description
Function:
Grid Count:
Telescoping Adder Body
169
Pin Description
External Pins
A
B
SUM
Data Input
Data Input
Output
Telescoping Interconnect Pins
GIN
GOUT
Garry Input
Garry Output
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
CIN
0.26
pF
A
0.26
pF
B
0.26
pF
A.C. Characteristics at 0-70°C, SV + / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
A to SUM
1.3
2.4
5.6
0.9
2.2
6.0
ns
Bto SUM
1.3
2.4
5.6
0.9
2.2
6.0
ns
CIN to SUM
0.5
0.9
2.0
0.4
0.9
2.7
ns
A to COUT
0.2
0.5
1.0
0.3
0.6
1.5
ns
Bto COUT
0.2
0.5
1.0
0.3
0.6
1.5
ns
CIN to COUT
0.3
0.5
1.3
0.3
0.6
1.5
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
SUM
0.33
0.73
1.93
0.47
0.67
1.23
ns/pF
COUT
1.24
2.84
7.84
1.51
2.52
4.90
ns/pF
Output Name
Units
TELESCOPING ARITHMETIC FUNCTIONS
ADDP -
TELESCOPING ADDER CAP
Logic Table
Inputs
Outputs
CIN
COUT
0
1
0
1
COUT
CIN
NOTE: ADDP must be used
if GOUT is to be connected
to circuitry external to a
telescoping block.
ADDP Description
Function:
Grid Count:
Telescoping Adder Carry Out Driver
39
Pin Description
External Pins
I
GOUT
Garry Output
Telescoping Interconnect Pins
I
GIN
Garry Input
Input Capacitance
Input Name
Max.
Units
GIN
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
GIN to GOUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.4
0.6
1.2
0.3
0.7
1.8
Units
ns
Load Dependent Delay
Output Name
GOUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.33
0.73
1.95
0.46
0.68
1.18
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
TELESCOPING MAGNITUDE COMPARATOR
(CMPC, CMPB, CMPP)
Example: 4-bit magnitude comparator
EOI
GT
GTI
CMPC CMPB
CMPB
CMPB
CMPB
CMPP
EO
LT
A4 B4 A3 B3 A2 B2 A1 B1
Telescoping Magnitude Comparator Description
Function:
Grid Count:
Cadcadable Binary Magnitude Comparator (1 -< n -< 12 bits)
With CMPP -130 + n(182)
Without CMPP -26 +n (182)
Pin Description
EOI
GTI
An
Bn
EO
GT
LT
Equal Input
Greater Than Input
Data Input
Data Input
Equal Output
Greater Than Output
Less Than Output
Logic Table
Inputs
EOI
GTI
An,Bn
...
0
0
0
1
X
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
An>Bn
AnB2
A2B1
A1=B1
1
LT
0
1
1
0
0
1
1
0
0
0
0
1
TELESCOPING ARITHMETIC FUNCTIONS
Input Capacitance
Input Name
Max.
Units
EOI
0.27
pF
GTI
0.15
pF
An
0.21
pF
Bn
0.27
pF
A.C. Characteristics at 0-70°C, 5V + /-10%
Intrinsic Propagation Delay
Parameter
Signal Path
Tplh
(n=1)
A1, B1 to EO
Tphl
(n=1)
Tplh
(2~n~12)
Tphl
(2~n~12)
A1, B1 to EO
Min.
Typ.
Max.
Units
1.4
2.9
7.5
ns
1.8
3.1
6.8
ns
A1, B1 to EO
0.9
+ n(0.47).
1.9
+ n(1.02)
4.9
+ n(2.62)
ns
A1, B1 to EO
1.1
+ n(0.67)
1.9
+ n(1.18)
4.1
+ n(2.69)
ns
Tplh
(n=1)
A1, B1 to GT
1.3
2.5
6.4
ns
Tphl
(n=1)
A1, B1 to GT
1.4
2.7
6.1
ns
Tplh
(2~n~12)
Tphl
(2~n~12)
Tplh
(n=1)
A1, B1 to GT
1.0
+ n(0.47)
2.1
+ n(1.02)
5.3
+ n(2.62)
ns
A1, B1 to GT
1.2
+ n(0.47)
2.2
+ n(1.02)
6.5
+ n(2.62)
ns
A1, B1 to LT
3.1
1.6
6.8
ns
'.
Tphl
(n=1)
Tplh
(2~n~12)
Tphl
(2~n~12)
A1, B1 to LT
A1, B1 to LT
A1, B1 to LT
2.9
1.4
7.2
ns
1.0
+ n(0.47)
1.8
+ n(1.02)
5.6
+ n(2.62)
ns
1.0
+ n(0.47)
2.1
+ n(1.02)
5.0
+ n(2.62)
ns
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay (Cont'd.)
Parameter
Signal Path
Typ.
Min.
Max.
Units
Tplh
EOI to EO
0.7
+ n(0.47)
1.4
+ n(1.02)
3.4
+ n(2.62)
ns
Tphl
EOI to EO
0.8
+ n(0.67)
1.4
+ n(1.18)
3.2
+ n(2.69)
ns
Tplh
EOI to GT
0.8
+ n(0.47)
1.6
+ n(1.02)
3.8
+ n(2.62)
ns
Tphl
EOI to GT
0.7
+ n(0.47)
1.4
+ n(1.02)
3.4
+ n(2.62)
ns
Tplh
EOI to LT
0.7
+ n(0.47)
1.4
+ n(1.02)
3.1
+ n(2.62)
ns
Tphl
EOI to LT
0.7
+ n(0.47)
1.4
+ n(1.02)
3.4
+ n(2.62)
ns
Tplh
GTI to GT
0.9
+ n(0.42)
1.7
+ n(0.78)
4.3
+ n(1.98)
ns
Tphl
GTI to GT
0.9
+ n(0.35)
1.7
+ n(0.65)
3.7
+ n(1.68)
ns
Tplh
GTI to LT
0.7
+ n(0.35)
1.3
+ n(0.65)
2.8
+ n(1.68)
ns
Tphl
GTI to LT
0.9
+ n(0.42)
1.7
+ n(0.78)
4.0
+ n(1.98)
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max;
Min.
Tphl
Typ.
Max.
EO
0.33
0.73
1.95
0.46
0.68
1.17
ns/pF
GT
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
LT
0.32
0.75
2.06
0.46
0.68
1.19
ns/pF
Output Name
Units
TELESCOPING ARITHMETIC FUNCTIONS
CMPC -
TELESCOPING MAGNITUDE COMPARATOR
CONTROL
EQI=D
GTI
CMPC Description
Telescoping Magnitude Comparator Control
Function:
Grid Count:
26
Pin Description
External Pins
EOI
GTI
Equal Input Feedthrough
Greater Than Input Feedthrough
NOTE: EOI and GTI are routed directly through CMPC without buffering to the Equal Input (EOI) and Greater
Than Input (GTI) signals respectively of the most significant CMPB cell. EOI must be tied high and
GTI must be tied low into the most significant magnitude comparator block.
Input Capacitance
Input Name
Max.
Units
EOI
0.05
pF
GTI
0.05
pF
inter
CMPB -
INTRODUCTION TO CELL-BASED DESIGN
TELESCOPING MAGNITUDE COMPARATOR BODY
Logic Table
Inputs
Outputs
EOI
GTI
A
B
EOO
GTO
0
0
1
1
1
1
0
1
0
0
0
0
X
X
0
0
1
1
X
X
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
EOO
EOI
GTI
GTO
A - -.....
B - - -......
NOTE: EOO and GTO cannot be used as final
output signals; a cap cell (CMPP) must
be used if external circuitry is, to be
connected to a final output signal.
CMPB Description
Function:
Grid Count:
Telescoping Magnitude Comparator Body
182
Pin Description
External Pins
A
B
Data Input
Data Input
Telescoping Interconnect Pins
EOI
GTI
EQO
GTO
Equal Input
Greater Than Input
Equal Output
Greater Than Output
TELESCOPING ARITHMETIC FUNCTIONS
Input Capacitance
Input Name
Max.
Units
EOI
0.22
pF
GTI
0.10
pF
A
0.21
pF
B
0.22
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
A to EOO
0.4
0.9
2.4
0.6
1.1
2.5
ns
B to EOO
0.4
0.9
2.4
0.6
1.1
2.5
ns
EOI to EOO
0.2
0.4
0.9
0.3
0.6
1.6
ns
A to GTO
0.3
0.5
1.3
0.3
0.7
1.9
ns
B to GTO
0.3
0.5
1.3
0.3
0.7
1.9
ns
EOI to GTO
0.3
0.6
1.3
0.4
0.8
3.4
ns
GTI to GTO
0.3
0.5
1.2
0.2
0.4
1.2
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
EOO
1.24
2.84
7.84
1.70
2.63
4.94
ns/pF
GTO
1.24
2.84
7.84
1.51
2.52
4.75
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
CMPP -
TELESCOPING MAGNITUDE COMPARATOR CAP
Logic Table
Inputs
Outputs
GT
EQI
EQ
GTI
LT
EOI
GTI
EO
GT
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
LT
CMPP Description
Function:
Grid Count:
Telescoping Magnitude Comparator Equal/Greater Than/Less Than Driver
104
Pin Description
External Pins
EO
GT
LT
Equal Output
Greater Than Output
Less Than Output
Telescoping Interconnect Pins
EOI
GTI
Equal Input
Greater Than Input
Input Capacitance
Input Name
Max.
Units
EOI
0.50
pF
GTI
0.50
pF
TELESCOPING ARITHMETIC FUNCTIONS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
EOI to EO
0.4
0.6
1.2
0.3
0.7
1.8
ns
GTI to GT
0.4
0.6
1.2
0.3
0.7
1.8
ns
EOI to LT
0.1
0.3
0.9
0.4
0.6
0.9
ns
GTI to LT
0.1
0.3
0.9
0.4
0.6
0.9
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
EO
0.33
0.73
1.95
0.46
0.68
1.17
ns/pF
GT
0.33
0.73
1.95
0.46
0.68
1.18
ns/pF
LT
0.32
. 0.75
2.06
0.46
0.68
1.19
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
PCI, PCIH -
NON-INVERTING CMOS INPUT BUFFERS
Logic Table
Inputs
Outputs
PAD
OUT
0
1
0
1
OUT
PAD
PCI Description
Non-Inverting CMOS Input Buffer, Normal Drive
Function:
PCIH Description
Non-Inverting CMOS Input Buffer, High Drive
Function:
Pin Description
Data Input
Output
PAD
OUT
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VIH
3.5
Typ.
Max.
Units
Test Conditions
V
VIL
1.2
V
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
Input Capacitance
Input Name
Max.
Units
PAD (PCI)
0.31
pF
PAD (PCIH)
0.40
pF
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PCI
PAD to OUT
0.5
0.4
0.6
0.4
0.8
1.6
ns
PCIH
PAD to OUT
0.7
0.6
0.9
0.5
1.0
2.1
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
OUT (PC I)
0.39
0.78
1.96
0.47
0.69
1.19
ns/pF
OUT (PCIH)
0.13
0.25
0.63
0.13
0.20
0.37
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
PTI, PTIH -
NON-INVERTING TTL INPUT BUFFERS
Logic Table
Inputs
Outputs
PAD
OUT
0
0
1
1
OUT
PAD
PTI Description
Non-Inverting TTL Input Buffer, Normal Drive
Function:
PTIH Description
Non-Inverting TTL Input Buffer, High Drive
Function:
Pin Description
Data Input
Output
PAD
OUT
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VIH
2.0
Typ.
Max.
Units
Test Conditions
V
VIL
0.8
V
IIH
10.0
uA
VIH
= VDD
ilL
-10.0
uA
VIL
= VSS'
Input Capacitance
Input Name
Max.
Units
PAD (PTI)
0.40
pF
PAD (PTIH)
0.50
pF
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PTI
PAD to OUT
0.6
0.8
1.2
0.6
1.3
3.6
ns
PTIH
PAD to OUT
0.8
1.1
1.9
0.8
1.9
5.5
ns
Si~nal
Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
OUT (PTI)
0.35
0.76
1.99
0.52
0.77
1.32
ns/pF
OUT (PTIH)
0.11
0.24
0.63
0.16
0.27
0.58
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
PTIRH -
NON-INVERTING TTL INPUT BUFFER WITH PULL-UP
RESISTOR
Logic Table
PAD
Inputs
Outputs
PAD
OUT
OUT
0
0
1
1
PTIRH Description
Function:
Non-Inverting TTL Input Buffer with Pull-Up Resistor, High Drive
Pin Description
PAD
OUT
Data Input
Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
Typ.
Pull-Up Resistance
2.1
4.1
VIH
2.0
Max.
9.4
Units
Test Conditions
kOhm
V
VIL
0.8
V
IIH
10.0
uA
VIH = VDO
ilL
-10.0
uA
VIL = VSS
Input Capacitance
Input Name
Max.
Units
PAD
0.40
pF
INPUT /OUTPUT
A.C. Characteristics at a-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
PAD to OUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.8
1.1
1.9
0.8
1.9
5.5
Units
ns
Load Dependent Delay
Output Name
OUT
Min.
Tp!h
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.11
0.24
0.63
0.16
0.27
0.58
Units
ns/pF
Intel
INTRODUCTION TO CELL-BASED DESIGN
PISH -
NON-INVERTING TTL SCHMITT TRIGGER INPUT
BUFFER
Logic Table
Inputs
Outputs
PAD
OUT
0
0
1
1
OUT
PAD
PISH Description
Function:
Non-Inverting TTL Schmitt Trigger Input Buffer, High Drive
Pin Description
PAD
OUT
Data Input
Output
D.C. Characteristics at 0-70°C, 5V + / -10%
Parameter
Min.
Typ.
VT+
2.4
2.0
2.0
V
VT-
0.8
0.9
1.0
V
Vhys
0.4
0.6
0.65
V
Max.
Units
Test Conditions
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
Input Capacitance
Input Name
Max.
Units
PAD
0.50
pF
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
PAD to OUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
2.6
3.1
5.0
1.3
3.3
11.6
Units
ns
Load Dependent Delay
Output Name
OUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.16
0.35
0.94
0.22
0.38
0.82
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PISRH -
NON-INVERTING TTL SCHMITT TRIGGER INPUT
BUFFER WITH PULL-UP RESISTOR
Logic Table
Inputs
Outputs
PAD
OUT
0
1
0
1
OUT
PAD
PISRH Description
Function:
Non-Inverting TTL Schmitt Trigger Input Buffer with Pull-Up Resistor,
High Drive
Pin Description
PAD
OUT
Data Input
Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
Typ.
Pull-Up Resistance
2.1
VT+
Max.
Units
4.1
9.4
kOhm
2.4
2.0
2.0
V
VT-
0.8
0.9
1.0
V
Vhys
0.4
0.6
0.65
V
Test Conditions
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
Input Capacitance
Input Name
Max.
Units
PAD
0.40
pF
Intel
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
PAD to OUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
2.6
3.1
5.0
1.3
3.3
11.6
Units
ns
Load Dependent Delay
Output Name
OUT
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.16
0.35
0.94
0.22
0.38
0.82
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PCO -
INVERTING CMOS OUTPUT BUFFER
Logic Table
Inputs
Outputs
IN
PAD
0
1
1
0
PAD
IN
pea Description
Function:
Inverting CMOS Output Buffer, 3.2 rnA
Pin Description
IN
PAD
Data Input
Output
D.C. Characteristics at 0-70°C, 5V + / -10%
Parameter
Min.
VOH
4.0
Typ.
Max.
VOL
Units
0.4
Test Conditions
V
IOH
=
-2.4 rnA
V
IOL
=
3.2 rnA
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.6
1.2
3.0
0.7
1.3
3.0
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.043
0.095
0.28
0.054
0.084
0.16
Units
ns/pF
INPUT /OUTPUT
PC NO -
NON-INVERTING CMOS OUTPUT BUFFER
Logic Table
IN
Inputs
Outputs
IN
PAD
PAD
0
0
1
1
peNO Description
Non-Inverting CMOS Output Buffer, 3.2 rnA
Function:
Pin Description
Data Input
Output
IN
PAD
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
4.0
Typ.
Max.
VOL
Units
0.4
Test Conditions
V
IOH
=
-2.4 rnA
V
IOL
=
3.2 rnA
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.8
1.5
3.6
0.8
1.6
3.9
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.043
0.096
0.28
0.051
0.084
0.16
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PCOT -
3-STATE INVERTING CMOS OUTPUT BUFFER
Logic Table
iNYD-.PAD
Inputs
IN
EN-----'
Outputs
EN
PAD
X
0
0
1
1
Z
1
1
0
peOT Description
3-State Inverting CMOS Output Buffer, 3.2 rnA
Function:
Pin Description
Data Input
3-State Enable Input
Output
IN
EN
PAD
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
4.0
Typ.
Max.
VOL
0.4
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
Units
Test Conditions
V
IOH
=
-2.4 rnA
V
IOL
=
3.2 rnA
inter
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
0.8
1.6
3.9
ns
Tphl
IN to PAD
0.8
1.6
4.0
ns
Tpzh
EN to PAD
0.8
1.7
4.6
ns
Tpzl
EN to PAD
0.5
1.2
2.5
ns
Tphz
EN to PAD
1.2
2.0
3.8
ns
Tplz
EN to PAD
0.8
1.2
2.1
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.055
0.13
0.35
0.064
0.11
0.23
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
PTO -
INVERTING TTL OUTPUT BUFFER
Logic Table
Inputs
Outputs
IN
PAD
0
1
1
0
PAD
IN
PTO Description
Inverting TTL Output Buffer, 3.2 rnA Sink
Function:
Pin Description
Data Input
Output
IN
PAD
D~C.
Parameter
Min.
VOH
2.4
Characteristics at 0-70°C, 5V+ / -10%
Typ.
Max.
VOL
0.45
Units
Test Conditions
V
IOH = -6.5 rnA
V
IOL =
3.2 rnA
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.6
1.2
2.8
0.7
1.4
3.2
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.026
0.058
0.16
0.072
0.12
0.23
Units
ns/pF
INPUT /OUTPUT
PTNO -
NON-INVERTING TTL OUTPUT BUFFER
Logic Table
Inputs
Outputs
IN
PAD
0
1
0
1
PAD
IN
PTNO Description
Function:
Non-Inverting TTL Output Buffer, 3.2 rnA Sink
Pin Description
IN
PAD
Data Input
Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
2.4
Typ.
Max.
VOL
Units
0.45
Test Conditions
V
IOH
= -6.5 rnA
V
IOL
=
3.2 rnA
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.7
1.4
3.4
0.8
1.7
4.1
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.029
0.059
0.16
0.068
0.11
0.23
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PTN03 -
NON-INVERTING TTL OUTPUT BUFFER
Logic Table
IN
Inputs
Outputs
IN
PAD
0
0
1
1
PAl)
PTN03 Description
Function:
Non-Inverting TTL Output Buffer, 9.6 rnA Sink
Pin Description
IN
PAD
Data Input
Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
2.4
Typ.
VOL
Max.
0.45
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
Units
Test Conditions
V
IOH
=
-2.7 rnA
V
IOL
=
9.6 rnA
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.6
3.8
0.6
1.3
3.3
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.056
0.13
0.39
0.052
0.087
0.17
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PTN05 -
NON-INVERTING TTL OUTPUT BUFFER
Logic Table
IN
Inputs
Outputs
IN
PAD
0
0
1
1
PAl)
PTN05 Description
Function:
Non-Inverting TTL Output Buffer, 16 rnA Sink
Pin Description
Data Input
Output
IN
PAD
D.C. Characteristics at 0-70°C, 5V + / -10%
Parameter
Min.
VOH
2.4
Typ.
VOL
Max.
0.45
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
Units
Test Conditions
V
IOH = -2.7 rnA
V
IOL =
16.0 rnA
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.1
2.0
4.6
0.7
1.4
3.6
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.055
0.13
0.38
0.044
0.073
0.16
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
PTOT -
3-STATE INVERTING TTL OUTPUT BUFFER
Logic Table
Inputs
lN~PAD
EN------.I
Outputs
IN
EN
PAD
X
0
Z
0
1
1
0
1
1
PTOT Description
3-State Inverting TTL Output Buffer, 3.2 rnA Sink
Function:
Pin Description
Data Input
3-State Enable Input
Output
IN
EN
PAD
D.C. Characteristics at 0-70°C, 5V + / -10%
Parameter
Min.
VOH
2.4
Typ.
Max.
0.45
VOL
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
Units
Test Conditions
V
IOH = -6.5 rnA
V
IOL =
3.2 rnA
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
0.7
1.5
3.6
ns
Tphl
IN to PAD
0.9
1.7
4.3
ns
Tpzh
EN to PAD
0.5
1.5
3.9
ns
Tpzl
EN to PAD
0.6
1.3
3.1
ns
Tphz
EN to PAD
1.2
2.0
3.8
ns
Tplz
EN to PAD
0.8
1.2
2.1
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.037
0.087
0.23
0.083
0.15
0.32
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PTOT3 -
3-ST ATE INVERTING TTL OUTPUT BUFFER
Logic Table
Outputs
Inputs
PAD
IN
IN
EN
PAD
X
0
Z
0
1
1
0
1
1
PTOT3 Description
3-State Inverting TTL Output Buffer, 9.6 rnA Sink
Function:
Pin Description
Data Input
3-State Enable Input
Output
IN
EN
PAD
D.C. Characteristics at 0-70°C, 5V+ / -10% .
Parameter
Min.
VOH
2.4
Typ.
VOL
Max.
0.45
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
Units
Test Conditions
V
IOH
=
-2.7 rnA
V
IOL
=
9.6 rnA
Intel
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
0.9
1.7
4.0
ns
Tphl
IN to PAD
0.7
1.3
3.3
ns
Tpzh
EN to PAD
0.6
1.7
4.1
ns
Tpzl
EN to PAD
0.5
1.2
3.1
ns
Tphz
EN to PAD
1.1
1.6
3.4
ns
Tplz
EN to PAD
1.1
1.8
3.0
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.060
0.15
0.42
0.063
0.12
0.26
Units
ns/pF
Intel
INTRODUCTION TO CELL-BASED DESIGN
3-STATE INVERTING TTL OUTPUT BUFFER
PTOT5 -
Logic Table
INy-Q-PAD
Inputs
EN----oi
Outputs
IN
EN
PAD
X
0
1
1
Z
0
1
1
0
PTOT5 Description
Function:
3-State Inverting TTL Output Buffer, 16 rnA Sink
Pin Description
IN
EN
Data Input
3-State Enable Input
Output
PAD
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
2.4
Typ.
VOL
Max.
0.45
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
Units
Test Conditions
V
IOH
=
V
IOL
=
-2.7 rnA
16.0 rnA
inter
INPUT /OUTPUT
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
1.2
2.1
4.8
ns
Tphl
IN to PAD
0.7
1.4
3.6
ns
Tpzh
EN to PAD
0.7
1.7
4.4
ns
Tpzl
EN to PAD
0.5
1.3
3.3
ns
Tphz
EN to PAD
1.1
1.7
3.2
ns
Tplz
EN to PAD
1.5
2.2
3.9
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.056
0.14
0.41
0.055
0.099
0.23
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
PTND -
NON-INVERTING TTL OPEN-DRAIN OUTPUT BUFFER
Logic Table
IN
Inputs
Outputs
IN
PAD
0
0
1
1
PAD
PTND Description
Non-Inverting TTL Open-Drain Output Buffer, 3.2 rnA Sink
Function:
Pin Description
Data Input
Output
IN
PAD
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Typ.
Min.
VOL
Max.
Units
0.45
V
Test Conditions
IOL
=
3.2 mA-
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.9
1.4
2.7
0.5
1.1
2.6
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.50
0.55
0.63
0.11
0.15
0.26
Units
ns/pF
INPUT /OUTPUT
PTND3 -
NON-INVERTING TTL OPEN-DRAIN OUTPUT BUFFER
Logic Table
IN
Inputs
Outputs
IN
PAD
0
1
0
1
PAD
PTND3 Description
Non-Inverting TTL Open-Drain Output Buffer, 9.6 rnA Sink
Function:
Pin Description
IN
PAD
Data Input
Output
D.C. Characteristics at 0-70°C, SV+ / -10%
Parameter
Typ.
Min.
VOL
Max.
Units
0.45
V
Test Conditions
IOL
=
9.6 rnA
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
A.C. Characteristics at 0-70°C, SV+ / -10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.1
1.9
3.6
0.5
1.2
2.9
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.54
0.61
0.70
0.051
0.079
0.15
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
PTND5 -
NON-INVERTING TTL OPEN-DRAIN OUTPUT BUFFER
Logic Table
Inputs
Outputs
IN
PAD
0
1
0
1
PAD
IN
PTND5 Description
Function:
Non-Inverting TTL Open-Drain Output Buffer, 16 rnA Sink
Pin Description
IN
PAD
Data Input
Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
Typ.
VOL
Max.
Units
0.45
V
Test Conditions
IOL
=
16.0 rnA
Input Capacitance
Input Name
Max.
Units
IN
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.5
2.4
4.5
0.6
1.3
3.3
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.53
0.61
0.71
0.039
0.068
0.14
Units
ns/pF
intel'
INPUT /OUTPUT
CMOS I/O BUFFER
PCIO -
Logic Table
IN
PAD
Inputs
EN---e
OUT
Outputs
IN
EN
PAD
PAD
OUT
0
1
X
X
1
1
0
0
1
0
0
1
1
0
Z
Z
OUTo
OUTo
0
1
pelo Description
Function:
CMOS I/O Buffer; Latched Non-Inverting Input, 3-State Inverting Output,
3.2 rnA
Pin Description
IN
EN
PAD
OUT
Internal Data Input
Enable Input
Bi-Directional Pin; External Output. External Data Input
Internal Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VIH
3.5
Typ.
Max.
Units
Test Conditions
V
VIL
1.2
V
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
V
IOH = -2.4 rnA
V
IOL =
VOH
VOL
4.0
0.4
3.2 rnA
inter
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
PAD
2.40
pF
3-State Output Capacitance
Input Name
Max.
Units
PAD(z)
2.40
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
Setup and Hold Times
Signal Path
PAD to EN
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
2.0
3.0
5.5
1.2
2.6
6.0
Units
ns
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
1.0
1.8
4.1
ns
Tphl
IN to PAD
0.9
2.0
4.8
ns
Tplh
PAD to OUT
1,.4
2.6
5.0
ns
Tphl
PAD to OUT
1.2
2.5
5:7
ns
Tpzh
EN to PAD
0.8
1.9
5.1
ns
Tpzl
EN to PAD
0.6
1.3
3.0
ns
Tphz
EN to PAD
1.2
2.2
4.5
ns
Tplz
EN to PAD
0.9
1.5
3.0
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD
0.10
0.10
0.20
0.10
0.10
0.20
ns/pF
OUT
0.40
0.80
2.10
0.40
0.70
1.20
ns/pF
Output Name
Units
INPUT /OUTPUT
TTL 1/0 BUFFER
PTIO -
Logic Table
IN
PAD
Inputs
EN--"
OUT
Outputs
IN
EN
PAD
PAD
OUT
0
1
X
X
1
1
0
0
1
0
0
1
1
0
OUTo
OUTo
0
1
Z
Z
PTIO Description
Function:
TTL I/O Buffer; Latched Non-Inverting Input, 3-State Inverting Output,
3.2 rnA Sink
Pin Description
IN
EN
PAD
OUT
Internal Data Input
Enable Input
Bi-Directional Pin; External Output, External Data Input
Internal Output
D.C. Characteristics at 0-70°C, 5V + / - 10%
Parameter
Min.
VIH
2.0
Typ.
Max.
Units
Test Conditions
V
VIL
0.8
V
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
V
IOH = -6.5 rnA
V
IOL =
VOH
VOL
2.4
0.45
3.2mA
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
I
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
PAD
2.40
pF
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
PAD to EN
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
2.0
3.0
5.5
1.2
2.6
6.0
Units
ns
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
0.8
1.6
3.8
ns
Tphl
IN to PAD
1.1
2.2
5.3
ns
Tplh
PAD to OUT
1.3
2.4
5.2
ns
Tphl
PAD to OUT
1.5
3.2
8.0
ns
Tpzh
EN to PAD
0.6
1.7
4.0
ns
Tpzl
EN to PAD
0.7
1.5
3.5
ns
Tphz
EN to PAD
1.2
2.2
4.5
ns
Tplz
EN to PAD
0.9
1.5
3.0
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD
0.10
0.10
0.20
0.10
0.10
0.20
ns/pF
OUT
0.40
0.70
2.00
0.50
0.70
1.10
. ns/pF
Output Name
Units
INPUT /OUTPUT
PTI03 -
TTL 1/0 BUFFER
Logic Table
PAD
IN
Inputs
EN--"
OUT
Outputs
IN
EN
PAD
PAD
OUT
0
1
1
1
0
0
1
0
0
1
1
0
aUTo
aUTo
0
1
x
x
Z
Z
PTI03 Description
Function:
TTL I/O Buffer; Latched Non-Inverting Input, 3-State Inverting Output,
9.6 rnA Sink
Pin Description
IN
EN
PAD
OUT
Internal Data Input
Enable Input
Bi-Directional Pin; External Data Input
Internal Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VIH
2.0
Typ.
Max.
Units
Test Conditions
V
VIL
0.8
V
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
V
IOH = -6.5 rnA
V
IOL =
VOH
VOL
2.4
0.45
9.6 rnA
inter
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
PAD
2.40
pF
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
PAD to EN
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
2.0
3.0
5.5
1.0
2.1
4.8
Units
ns
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
0.9
1.8
4.1
ns
Tphl
IN to PAD
0.7
1.4
3.4
ns
Tplh
PAD to OUT
1.2
2.0
4.4
ns
Tphl
PAD to OUT
1.4
3.0
7.1
ns
Tpzh
EN to PAD
0.7
1.8
4.5
ns
Tpzl
EN to PAD
0.6
1.4
3.5
ns
Tphz
EN to PAD
1.1
2.0
3.8
ns
Tplz
EN to PAD
1.3
2.1
4.1
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD
0.059
0.14
0.42
0.063
0.11
0.24
ns/pF
OUT
0.30
0.70
2.00
0.50
0.70
1.10
ns/pF
Output Name
Units
inter
INPUT /OUTPUT
PTI05 -
TTL 1/0 BUFFER
Logic Table
IN
PAD
Inputs
OUT
Outputs
IN
EN
PAD
PAD
OUT
0
1
1
1
0
0
1
0
0
1
1
0
OUTo
OUTo
0
1
X
X
Z
Z
PTI05 Description
Function:
TTL I/O Buffer; Latched Non-Inverting Input, 3-State Inverting Output,
16 rnA Sink
Pin Description
IN
EN
PAD
OUT
Internal Data Input
Enable Input
Bi-Directional Pin; External Output, External Data Input
Internal Output
D.C. Characteristics at 0-70°C, SV+ / -10%
Parameter
Min.
VIH
2.0
Typ.
Max.
Units
Test Conditions
V
VIL
0.8
V
IIH
10.0
uA
VIH
=
VDD
ilL
-10.0
uA
VIL
=
VSS
VOH
VOL
2.4
0.45
V
IOH
=
V
IOL
=
-
6.5 rnA
16.0 rnA
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
IN
0.20
pF
EN
0.30
pF
PAD
2.40
pF
Input Capacitance
Output Name
Max.
Units
PAD(z)
2.40
pF
A.C. Characteristics at 0-70°C, 5V+ /-10%
Setup and Hold Times
Signal Path
PAD to EN
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
2.0
3.0
5.5
1.0
2.1
4.8
Units
ns
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
1.2
2.2
4.9
ns
Tphl
IN to PAD
0.7
1.5
3.7
ns
Tplh
PAD to OUT
1.2
2.0
4.4
ns
Tphl
PAD to OUT
1.4
3.0
7.1
ns
Tpzh
EN to PAD
0.8
1.8
4.7
ns
Tpzl
EN to PAD
0.6
1.5
3.7
ns
Tphz
EN to PAD
1.2
2.0
3.8
ns
Tplz
EN to PAD
1.6
2.6
5.0
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD
0.056
0.41
0.14
0.055
0.095
0.22
ns/pF
OUT
0.30
0.70
2.00
0.50
0.70
1.10
ns/pF
Output Name
Units
VLSiCEL Elements and LSI Functions
4
CHAPTER 4
VLSiCEL ELEMENTS AND LSI FUNCTIONS
UC51 -
BOC51 BH MICROCONTROLLER CORE
RXo
TOPP2
SCLI(
TIPP2
TXo
TOPP2TO
TOPP1
INTOl
TPPC
INT1l
TIPP1
TO
TOPP1TO
T1
TAoBC
WRl
TITEST
Rol
PSENl
ALE
TAoBOE
TEST
EAl
ERST
MOoEO
RESET
TIClK
UC51XX
ClK
P2
EAoBD-7
AO·7
AoBD-7
AB·15
P2EXT
OPOO-07
OP2D-27
IPOO-07
IP2D-27
OP1D-17
OP3D-37
IP1D-17
IP3D-37
Functional Pin Diagram
G40208
•
Cell Version of the 80C51 BH Microcontroller; Code and Functional Compatibility with
the Standard Product Assured.
•
12 MHz Operation.
•
On-Chip ROM Expandable to 16K Bytes:
UC5100 UC5104 UC5108 UC5116 -
No ROM
4K Bytes ROM
8K Bytes ROM
16K Bytes ROM
•
UC52xx Cores Expand the On-Chip RAM from 128 Bytes to 256 Bytes
•
Demultiplexed I/O Ports Make Available all Functional Signals of the 80C51BH.
•
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
•
Code Development Supported with the Configurable UC51 Emulator Design Kit.
4-1
INTRODUCTION TO CELL-BASED DESIGN
UC51 DESCRIPTION
The VC51 core is the cell version of Intel's industry standard 80C51 BH Microcontroller.
The VC51 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes an
80C51BH core and design specific support logic.
The VC51 has on-chip Read Only Memory (ROM), available in 4K, 8K, and 16K byte
configurations. The use of additional ROM expands the code space of the VC51 core beyond
the 4K bytes available with the 80C51 BH standard product, in most cases alleviating the
need for external program memory. A ROM-less version of the VC51 is also available,
providing the user an 80C31 BH compatible VLSiCEL core.
All UC51xx cores contain 128 bytes of on-chip Static RAM. This RAM can be expanded
to 256 bytes via the UC52xx cores. These cores provide the additional RAM while maintaining the exact functionality of their UC51xx counterparts.
In partitioning the 80C51 BH into a cell compatible format, the standard product's
I/O drivers and pin multiplexers were eliminated. As a result, all functional pins of the
80C51BH are available to the UC51 user as "raw" I/0. This expanded I/O capability, totalling
117 user available signals, allows design flexibility not previously available to MCS-51
designers. Intel has also assured compatibility with a cell library of over 150 logic elements
while maintaining code and functional compatibility with the standard product. Designers
can, however, take advantage of the UC51 's demultiplexed I/O ports to optimize their application code.
For a complete functional description of the MCS-51 architecture, including a description
of the instruction set and a programmer's reference guide, refer to Chapters 5-7, the
"80C31 BH/80C51 BH 8-Bit Microcontrollers" data sheet in Chapter 8, and AP-252
"Designing with the 80C51 BH" in Chapter 9 of the Intel Embedded Controller Handbook.
Pin Description
Pin #
80C51BH
Name
UC51
Pin Name
UC51 Pin Description
Port 1
1-8
P1.0 to 1.7
IP10-17
(Input Port 1, Address = 90H)
An 8-bit input port. Port 1 is not used for the address
input during ROM verify or any other test modes.
Unused inputs must be connected to VSS. This port is
equivalent to the Port 1 input function of the 80C51 BH.
OP10-17
(Output Port 1, Address = 90H)
An 8-bit output port. This port is equivalent to the
Port 1 output function of the 80C51 BH.
4-2
UC51
Pin Description (Cont'd.)
Pin #
80C51BH
Name
9
RST
UC51
Pin Name
UC51 Pin Description
RESET
(Internal Reset)
A logic 1 on this pin applied for 12 oscillator periods
resets the UC51. It is provided to give the user the
ability to reset the core using on-chip logic. If only offchip reset is desired, tie RESET to VSS.
ERST
(External Reset)
MANDATORY PACKAGE PIN. This pin must be
brought off-chip and serves as the external reset signal.
A logic 1 on this pin resets the entire chip both in
normal user operation mode and in test modes. No
internal user logic should drive this line.
IP30-37
(Input Port 3, Address = BOH)
An 8-bit input port. Unused inputs must be connected
to VSS. This port is equivalent to the Port 3 input
function of the 80C51 BH.
OP30-37
(Output Port 3,'Address = BOH)
An 8-bit output port. This port is equivalent to the
Port 3 output function of the 80C51 BH.
Port 3
10-17
RXD/P3.0*RD/P3.7
10
RXD/P3.0
RXD
(Serial Input Port)
Serial port input pin for all 4 serial port modes.
11
TXD/P3.1
TXD
(Serial Output Port)
Serial port output pin for all 4 serial port modes.
SClK
(Serial Clock)
Serial port shift clock (same as Mode 0 TXD output on
the 80C51 BH). SClK is fixed at one-sixth of the input
clock (ClK or TIClK). SClK is output only during Serial
Mode O.
MODEO
(Serial Port MODEO Control Pin)
Active when Mode 0 serial port configuration is
selected. MODEO is used to recombine Port 3 with
RXD, TXD, and SClK to create an 80C51 BH-type Serial
Mode O. If MODEO is not used to recreate the 80C51 BH
type function then, in Mode 0, the serial data will enter
through RXD, exit through TXD, and SClK will output
the shift clock.
12
*INTO/P3.2
INTOl
(Interrupt 0)
External Interrupt O.
13
*INT1/P3.3
INT1l
(Interrupt 1)
External Interrupt 1.
14
TO/P3.4
TO
(Timer/Counter 0)
Timer/Counter 0 external input pin.
4-3
inter
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin #
80C51BH
Name
UC51
Pin Name
UC51 Pin Description
Port 3 (Cont'd.)
15
T1/P3.5
T1
(Timer/Counter 1)
Timer/Counter 1 external input pin.
16
*WR/P3.6
WRl
(Write Strobe)
Write strobe for external data memory.
17
*RD/P3.7
RDl
(Read Strobe)
Read strobe for external data memory.
18
19
XTAl2
XTAl1
ClK
(Input Clock)
During normal user operation, ClK is the input clock
to the UC51. The ClK signal must be supplied. If an
on-chip oscillator is required in the design, ClK should
be connected to the output of the oscillator companion cell, POSC. Otherwise, ClK can be driven by an
input pad, or by on-chip user logic.
TIClK
(Tester Input Clock)
MANDATORY PACKAGE PIN. TIClK is selected as the
input clock during test. TIClK must be driven from offchip, allowing the tester to control the UC51 frequency.
IP20-27
(Input Port 2, Address = AOH)
An 8-bit input port. Unused inputs must be connected
to VSS. This port is equivalent to the Port 2 input
function of the 80C51 BH.
P2EXT
(Port 2/A8-15 Select Signal)
P2EXT is an active high output signal. During internal
program execution (EAl high), P2EXT is active if a
MOVX @ DPTR instruction is executed. During external program execution (EAl low or when the addressing limit of the internal ROM has been exceeded),
P2EXT is always active except during a MOVX @ Ri
or a Port 2 instruction. P2EXT can be used to reconstruct the 80C51 BH Port 2 output function.
OP20-27
(Output Port 2, Address = AOH)
An 8-bit output port. This port is equivalent to the
Port 2 output function of the 80C51 BH. Unlike the
80C51 BH Port 2, OP2 is not used to output the
high-order address during fetches to internal program
memory (see P2EXT).
A8-15
(High Address Bus)
A8-15 are the 8 most significant bits of the 16-bit
address bus for external program and data memory.
This address bus is completely separate from Port 2
and can be latched (see P2EXT).
20
VSS
Port 2
21-28
P2.0-2.7/
A8-A15
4-4
UC51
Pin Description (Cont'd.)
Pin #
80C51BH
Name
UC51
Pin Name
UC51 Pin Description
29
*PSEN
PSENL
(Program Store Enable)
PSENL is an output and may be used to enable the
output drivers of external program memory.
30
ALE
ALE
(Address Latch Enable)
In conjunction with PSENL, ALE is used for external
program memory expansion. In conjunction with WRL
or RDL, ALE is used for external data memory expansion. When ALE is a logic 1, the memory address is
available on EADBO-7 and ADBO-7. The entire latched
address is available on AO-15.
31
*EA
EAL
(External Access Control)
EAL is an input. The state of this pin defines the
location of program memory (0 = external, 1 = internal). Regardless of what state EAL is, the core will fetch
instructions from the external memory if the address
is pointing to a location outside of the internal ROM
boundary. EAL is not present on the UC51 00 core.
PO.0-0.7
IPOO-07
(Input Port 0, Address = aOH)
An a-bit input port completely separate from the
address/data bus; consequently, any use of ADB and
EADB has no effect on IPOO-07. Unused inputs must
be connected to VSS.
(Output Port 0, Address = aOH)
An a-bit. output port completely separate from the
address/data bus; consequently any use of ADB or
EADB has no effect on OPOO-07.
Port 0
32-39
OPOO-07
AO-7
(Low Address Bus)
AO-A7 are the a least significant bits of the 16-bit
address bus for external program and data memory.
This address bus can be latched on ALE.
ADBO-7
(Address/Data Bus)
Bidirectional address/data bus for on-Chip connection
to user logic. During normal user operation, ADBO-7
acts as the data bus and lower a bits of address for
program and data memory (see TADBOE).
EADBO-7
(External Address/Data Bus)
MANDATORY PACKAGE PINS. Bidirectional address/
data bus to be brought off-chip for testing and for offchip program and data memory accesses. No on-chip
logic may be connected to EADBO-7. The EADB and
ADB busses are electrically connected during normal
user operation (see TADBOE).
TADBOE
(Test Address/Data Bus Output Enable Control)
TADBOE controls the direction of the PADB companion cells which are connected to EADB. A low level
TADBOE 3-states the PADB cells. TADBOE must be
combined with user logic to control PADB if user logic
is driving ADBO-7.
4-5
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin #
40
80C51BH
Name
UC51
Pin Name
UC51 Pin Description
VCC
Additional UC51 Signals
P2
(Phase 2 Clock Output)
Signal frequency V2 of ClK or TIClK;
TEST
Test is active high during all UC51 test modes.
TPPC
(Test Programmable Pin Control)
Control signal for TOPP/UOS selection to the PRGPIN1
and PRGPIN2 companion cells. TPPC is a logic 1
during test and selects the test programmable pin
outputs (TOPP) from TOPP1/UOS and TOPP2/UOS.
TPPC remains low during normal user operation and
selects the user output signals (UOS) from TOPP1 I
UOS and TOPP2/UOS.
TIPP1
(Test Programmable Pin 1 Input)
MANDATORY PACKAGE PIN - MULTIPLEXED WITH
TOPP1. Functions as the path for programmable pin 1
inputs during test. TIPP1 is input to the UC51 from the
PRGPIN1 companion cell.
TOPP1
(Test Programmable Pin 1 Output)
MANDATORY PACKAGE PIN - MULTIPLEXED WITH
TIPP1. Functions as the path for programmable pin 1
outputs during test. TOPP1 is output from the UC51
to the PRGPIN1 companion cell.
TOPP1TO
(Test Programmable Pin 1 Output Enable Control)
TOPP1 TO controls the direction of the PRGPIN1
companion cell during test. TOPP1 TO is low during
normal user operation, configuring TPP1 as an output.
TIPP2
(Test Programmable Pin 2 Input)
MANDATORY PACKAGE PIN - MULTIPLEXED WITH
TOPP2. Functions as the path for programmable pin 2
inputs during test. TIPP2 is input to the UC51 from the
PRGPIN2 companion cell.
TOPP2
(Test Programmable Pin 2 Output)
MANDATORY PACKAGE PIN - MULTIPLEXED WITH
TIPP2. Functions as the path for programmable pin 2
outputs during test. TOPP2 is output from the UC51
to the PRGPIN2 companion cell.
TOPP2TO
(Test Programmable Pin 2 Output Enable Control)
TOPP2TO controls the direction of the PRGPIN2
companion cell during test. TOPP2TO is low during
normal user operation, configuring TPP2 as an output.
4-6
UC51
Pin Description (Cont'd.)
Pin #
aOC51BH
Name
UC51
Pin Name
UC51 Pin Description
Additional UC51 Signals
(Cont'd.)
TADBC
(Test Enable Control)
Control signal for ALE/UOS selection to the
PRGPINALE companion cell. TADBC is a logic 1 during
test and selects Address Latch Enable from ALE/UOS.
TADBC remains low during normal user operation and
selects the user output signal (UOS) from ALE/UOS.
TITEST
(Test Enable Input)
MANDATORY PACKAGE PIN - MULTIPLEXED WITH
ALE. The state of this pin during reset (RESET or ERST
high) is one of the variables for defining the operating
mode of the chip. TITEST is input to the UC51 from
the PRGPINALE companion cell.
MANDATORY UC51 SIGNALS AND UC51 COMPANION CELLS
In partitioning the 80C51 BH into a cell compatible format, the I/O drivers were removed.
This allows the UC51 core to be integrated with a cell library of over 150 logic functions
into a user defined ASIC. Because of this, those UC51 signals which are required external
to the ASIC device must be buffered off-chip as package pins. Mandatory UC51 signals are
signals which require package pins for every UC51 based design.
There are thirteen mandatory UC51 signals, most of which are used for production testing
of the UC51 core and which only nominally affect the design of the user specific application
logic. Ten of these required signals are normally used in any design. The other three (TPP 1,
TPP2, and TALE) may be reconfigured by the designer as output signals during normal
user operation.
There are two types of mandatory UC51 signals: non-multiplexed and multiplexed. Most of
the mandatory signals are routed off-chip using UC51 companion cells. The major task of
the companion cells is to multiplex the applicable UC51 signals between test and normal
user operation modes and/or to act as buffers for the signals. Companion cells can also be
used to reconfigure the demultiplexed I/O ports of the UC51 into their 80C51BH standard
product equivalents. Refer to the individl:lal data sheets of the various companion cells for
more information on their operation. Refer to the "Designing with the UC51 Microcontroller Core" module in the Intel cell-based design, engineering workstation environment
documentation for more information on designing the UC51 for test and the application of
UC51 companion cells.
INTRODUCTION TO CELL-BASED DESIGN
Non-Multiplexed Signals
These two pins keep the same function whether the device is executing in test mode or normal
user operation mode.
ERST
(External Reset Input)
The ERST pin is required in all UC51 designs to allow the tester to initialize
the UC51 and is brought on-chip through the PRESET companion cell.
TICLK
(Tester Input Clock)
For testing purposes, the UC51 frequency source must be externally controlled.
If the signal CLK is to be generated externally by either a crystal or any
other clock source, TICLK and CLK should be connected to the same
package pin.
Multiplexed Signals
The function of these eleven pins depends on whether the device is executing in test mode or
normal user operation mode.
EADBO-7
(External Address/Data Bus)
EADBO-7 is accessed during production test to fully check out the UC51 core
and the application logic. EADBO-7 is brought off-chip through the PADB
companion cell. EADBO-7 is also available for those applications requiring an
off-chip address/data bus for external program and data memory.
TPPI
(TIPPI/TOPPI/UOS)
TPPI interfaces between the UC51 and the package pins through the
PRGPINI companion cell. During test, TPPI functions as an I/O path
through TIPPI and TOPPI. During normal user operation, TPPI can be
configured as a user output signal (UOS).
TPP2
(TIPP2/TOPP2/UOS)
TPP2 interfaces between the UC51 and the package pins through the
PRGPIN2 companion cell. During test, TPP2 functions as an I/O path
through TIPP2 and TOPP2. During normal user operation, TPP2 can be
configured as a user output signal (UOS).
TALE
(TITEST / ALE/UOS)
TALE interfaces between the UC51 and the package pins through the
PRGPINALE companion cell. TITEST is input to the UC51 during reset to
enable the UC51 to enter a test mode. ALE is output from the UC51 when
the UC51 is configured in any test mode requiring external memory access.
During normal user operation, TALE can be configured as a user output signal
(UOS).
inter
UC51
Input Capacitance
UC5100
Max.
UC5104
Max.
UC5108
Max.
UC5116
Max.
Units
ADBO-7
1.3
1.5
1.6
1.8
pF
elK
1.1
1.3
1.4
1.6
pF
EADBO-7
1.3
1.5
1.6
1.8
pF
EAl
-
1.3
1.4
1.6
pF
ERST
1.2
1.4
1.5
1.7
pF
INTOl
1.1
1.3
1.4
1.6
pF
INT1l
1.1
1.3
1.4
1.6
pF
IPOO-07
0.1
0.1
0.1
0.1
pF
IP10-17
0.1
0.1
0.1
0.1
pF
IP20-27
0.1
0.1
0.1
0.1
pF
IP30-37
0.1
0.1
0.1
0.1
pF
RESET
1.5
1.7
1.8
2.0
pF
RXD
1.1
1.3
1.4
1.6
pF
TO
1.1
1.3
1.4
1.6
pF
T1
1.1
1.3
1.4
1.6
pF
Input Name
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V + / -10%
NOTE: A.C. Characteristics are given to the edge of the UC51 core. Additional delays will apply in connecting UC51 signals to package pins through selected I/O buffer cells.
External Program and Data Memory Characteristics
12 MHz OSC
Symbol
Units
Min.
Max.
1/TCLCL OSCILLATOR FREQUENCY
TLHLL
TAVLL
TLLAX
TLLlV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TAVIV
TPLAZ
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TWHQX
TRLAZ
TWHLH
Variable Oscillator
Parameter
ALE PULSE WIDTH
ADDRESS VALID to ALE LOW
ADDRESS HOLD AFTER ALE LOW
ALE LOW to VALID INSTR. IN
ALE LOW to PSENL LOW
PSENL PULSE WIDTH
PSENL LOW to VALID INSTR. IN
INPUT INSTR. HOLD AFTER PSENL
INPUT INSTR. FLOAT AFTER PSENL
ADDRESS to VALID INSTR. IN
PSENL LOW to ADDRESS FLOAT
RDL PULSE WIDTH
WRL PULSE WIDTH
RDL LOW to VALID DATA IN
DATA HOLD AFTER RDL
DATA FLOAT AFTER RDL
ALE LOW to VALID DATA IN
ADDRESS to VALID DATA IN
ALE LOW to RDL or WRL LOW
ADDRESS VALID to RDL or WRL LOW
DATA VALID to WRL TRANSITION
DATA HOLD AFTER WRL
RDL LOW to ADDRESS FLOAT
RDL or WRL HIGH to ALE HIGH
166
83
84
Min.
Max.
3.5
12
2TCLCL -0.3
TCLCL -0.6
TCLCL +0.2
4TCLCL -8.1
325
85
250
TCLCL +1.2
3TCLCL
237
0
3TCLCL -12.8
0
TLCLC -5.0
5TCLCL -10.2
2.6
78
406
2.6
500
500
6TCLCL +0.5
6TCLCL +0.5
5TCLCL -7.0
410
0
230
332
83
84
68
0
165
658
740
270
0
98
2TCLCL -2.0
8TCLCL -8.1
9TCLCL -10.2
3TCLCL -20.0 3TCLCL +20.0
4TCLCL -0.8
TCLCL -0.8
TCLCL +0.3
0
TCLCL -15.0 TCLCL +15.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
inter
UC51
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
AO-7
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
A8-15
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
ADBO-7
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
ALE
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
EADBO-7
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
MODEO
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
OPOO-07
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
OP10-17
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
OP20-27
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
OP30-37
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
P2
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
P2EXT
1.8
1.9
2.2
1.7
1.8
1.8
ns/pF
PSENL
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
RDL
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
SCLK
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
TADBC
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
TADBOE
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
TPPC
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
TXD
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
WRL
0.2
0.3
0.9
0.2
0.3
0.6
ns/pF
Output Name
Units
Intel
INTRODUCTION TO CELL-BASED DESIGN
TWHLH
ALE
PSENL
I---~TLLDV
----.j
TRLRH-l----I
RDL
EADBO-7/
ADBO-7
AO-7
A8-15
External Data Memory Read Cycle
G40208
External Program Memory Read Cycle
G40208
ALE
PSENL
EADBO-7/
ADBO-7
AO-7
A8-15
4-12
UC51
TWHLH
ALE
PSENL
WRL
14-~---TQVWH--------_~~
EADBG-71
ADBG-7
DATA OUT
AG-7
A8·15
External Data Memory Write Cycle
G4020B
INSTRucnON
ALE
I--TXLXL~
CLOCK
(SCLK)
------.
~TOVXH.j
!-TXHQX
OUTPUT DATA
(TXO)
~
WRITE TO SSUF
INPUT
DATA
(RXO)
____________
~~~
__
~~~_J~~~~~~
__~~~_J~~~~~~__~~~
t
t
SETAl
CLEAR IN
Shift Register Mode Timing Waveforms
4-13
G4020B
INTRODUCTION TO CELL-BASED DESIGN
PRESET -
PAD - {
RESET INPUT BUFFER
)t---~
Logic Table
Inputs
Outputs
PAD
RESIN
0
1
0
1
RESIN
PRESET Description
Function:
Reset Input Buffer; Non-Inverting, Schmitt Trigger. This cell is used to buffer
the off-chip reset signal (ERST) into a Ve51 core.
Pin Description
PAD
RESIN
External Reset Input
Output
D.C. Characteristics at 0-70°C, 5V + / - 10%
Parameter
Min.
VIH
3.5
Typ.
Max.
Units
Test Conditions
V
VDD
=
5V
=
0V
VIL
0.9
V
VSS
IIH
10.0
uA
VIH
=
VDD
ilL
-10.0
uA
VIL
=
VSS
Input Capacitance
Input Name
Max.
Units
PAD
4.00
pF
IflteI
UC51 COMPANION CELLS
A.C. Characteristics at 0-70°C,· 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
PAD to RESIN
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
1.0
1.6
3.5
1.2
2.5
6.6
Units
ns
Load Dependent Delay
Output Name
RESIN
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.16
0.35
0.93
0.22
0.32
0.56
Units
ns/pF
InIal
INTRODUCTION TO CELL-BASED DESIGN
POSC -
OSCILLATOR
PAD1
OSCOUT
Logic Table
Inputs
Outputs
PAD1
PAD2
OSCOUT
0
1
1
0
0
1
PAD2
pose Description
Function:
Oscillator, Frequency Range to 16 MHz. This cell is used to provide the
clock input to a ve51 core (eLK) from an external crystal. In test mode,
the external tester clock is connected directly to PAD 1, with P AD2 left
unconnected. Refer to the 80e51 BH data sheet in the Intel Embedded
Controller Handbook for the recommended implementation of an external
crystal. pose is designed to function over the full range of operating
frequencies of the Ve51.
Pin Description
PAD1
PAD2
OSCOUT
Oscillator Input
Oscillator Feedback Output
Clock Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VIH
2.0
Typ.
Max.
Units
Test Conditions
V
VIL
0.8
V
IIH
10.0
uA
VIH = VDD
ilL
-10.0
uA
VIL = VSS
UC51 COMPANION CELLS
Input Capacitance
Input Name
Max.
Units
PAD1
4.77
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD1 to OSCOUT
1.4
2.6
6.2
1.2
2.4
5.7
ns
PAD1 to PAD2
0.4
0.7
1.5
0.7
0.9
1.5
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
OSCOUT
0.16
0.35
0.93
0.22
0.32
0.56
ns/pF
PAD2
0.11
0.24
0.57
0.17
0.26
0.48
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
PADB -
ADDRESS/DATA BUS I/O BUFFER
Logic Table
TADB-.----t
Inputs
Outputs
TADB TADBOE PAD
TADB PAD
PAD
TADBOE--.......-
1
1
0
0
0
1
0
1
.....
Z
Z
0
1
0
1
0
1
0
1
Z
Z
PADB Description
Function:
Address/Data Bus I/O Buffer; 3-State Non-Inverting Input, 3-State NonInverting TTL Output, 3.2 rnA sink. This cell is used to bring the external
address/data bus of the Ve51 (EADBO-7) off-chip.
Pin Description
TADBOE
TADB
PAD
Enable Input
Bi-Directional Pin; Internal Address/Data Bit
Bi-Directional Pin; External Address/Data Bit
D.C. Characteristics at 0-70°C, 5V+ /-10%
Parameter
Min.
VIH
1.9
Typ.
Max.
Units
Test Conditions
V
VDD
=
5V
=
0V
VIL
0.9
V
VSS
IIH
10.0
uA
VIH
=
VDD
ilL
-10.0
uA
VIL
=
VSS
V
IOH
=
-0.08 rnA
V
IOL
=
3.2mA
VOH
VOL
2.4
0.45
UC51 COMPANION CELLS
Input Capacitance
Input Name
Max.
Units
TADSOE
0.20
pF
TAOS
0.60
pF
PAD
2.85
pF
3-State Output Capacitance
Output Name
Max.
Units
TADS(z)
0.60
pF
PAD(z)
2.85
pF
A.C. Characteristics at 0-70c C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
TAOS to PAD
1.5
2.6
6.6
1.5
3.5
8.0
ns
PAD to TAOS
3.0
5.0
9.0
1.5
3.1
8.7
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
TAOS
0.30
0.40
0.80
0.20
0.40
0.80
ns/pF
PAD
0.10
0.10
0.20
0.10
0.10
0.20
ns/pF
Output Name
Units
INTRODUCTION TO CEll-BASED DESIGN
PTNQB -
QUASI-BIDIRECTIONAL 1/0 BUFFER
logic Table
Inputs
IN
elK
OUT
=f K}-PAD
Outputs
elK
IN
PAD
PAD
OUT
X
X
0
18
1
1
1
1
0
1
1*
1*
0
1
0
1
1*
1*
0
1
0
1
1*
1*
0
1
"-
Xb
Xb
Xb
Weak high state; after a falling
edge of ClK with IN = 1, a
weak high state will occur
internal to the cell on PAD and
OUT in the absence of an
external input signal on PAD.
This state will be overdriven by
an external input signal on
PAD.
a - This condition is valid only after
a state change at IN from 0 to
1 and prior to a falling edge of
, ClK.
b - Any state or transition of ClK
after a falling edge of ClK with
IN = 1 where IN remains equal
to one.
NOTE: * -
PTNQB Description
Quasi-Bidirectional I/0 Buffer; Non-Inverting TTL Output, 3.2 rnA Sink.
This cell is used to reconfigure DC51 input and output ports to their equivalent 80C51 BH bidirectional port structures.
Function:
Pin Description
ClK
IN '
PAD
OUT
P2 Clock Input
Internal Data Input
Bi-Directional Pin; External Output, External Data Input
Internal Output
inter
UC51 COMPANION CELLS
D.C. Characteristics at 0-70°C, 5V + / -10%
Parameter
Min.
VIH
1.9
Typ.
Max.
Units
Test Conditions
V
VDD = 5 V
Vil
0.9
V
VSS = 0 V
IIH
10.0
uA
VIH = VDD
III
-10.0
uA
Vil = VSS
V
IOH = -6.5 rnA
V
IOl=
2.4
VOH
Val
0.45
3.2 rnA
Input Capacitance
Input Name
Max.
Units
ClK
0.10
pF
IN
0.10
pF
PAD
2.30
pF
Output Capacitance
Output Name
Max.
Units
PAD
2.30
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
Setup and Hold Times
Signal Path
IN to ClK
Min.
Setup Time
Typ.
Max.
Min.
Hold Time
Typ.
Max.
14.0
30.0
67.5
0
0
0
4-21
Units
ns
INTRODUCTION TO CELL-BASED DESIGN
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
IN to PAD
1.3
2.5
6.7
1.3
3.0
7.4
ns
PAD to OUT
3.9
5.2
6.9
0.5
4.9
12.4
ns
Min.
Tphl
Typ.
Max.
Signal Path
Max.
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max. '
PAD
0.023
0.055
0.16
0.068
0.091
0.15
ns/pF
OUT
0.40
0.77
1.93
0.77
0.83
1.63
ns/pF
Output Name
Units
UC51 COMPANION CELLS
PRGPIN -
PROGRAMMABLE I/O BUFFER
Logic Table
Inputs
Outputs
UOS TESTIN TEST TRISO PAD
PAD TOUT
TESTIN
0
1
X
X
X
X
X
TEST
PAD
UOS
TOUT
TRISO
NOTE: * -
X
X
0
1
X
X
X
0
0
1
1
X
X
X
0
0
0
0
1
1
1
0
1
0
1
0*
0
1
0
1
0
1
Z
Z
Z
0
1
0
1
0*
0
1
Weak low state; with TRISO = 1, a
weak low state will occur internal to the
cell on PAD and TOUT in the absence
of an external input signal on PAD.
This state will be overdriven by ~n
external input signal on PAD.
PRGPIN Description
Function:
Programmable I/0 Buffer; 3-State Non-Inverting TTL Output, 3.2 rnA Sink.
This cell is used to multiplex a Ue51 input and output test signal pair with
a user definable output signal.
Pin Description
TESTIN
UOS
TEST
TRISO
PAD
TOUT
Test Signal Input (From UC51)
User Output Signal Input
Select Input (TESTIN or UOS)
Enable Input
Bi-Directional Pin; External Output, External Data Input
Test Signal Output (To UC51)
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
2.4
VOL
Typ.
Max.
0.45
Units
Test Conditions
V
IOH
=
-0.08 rnA
V
IOL
=
3.2 rnA
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Max.
Units
TESTIN
0.10
pF
UOS
0.10
pF
TEST
0.10
pF
TRISO
0.10
pF
PAD
2.85
pF
Input Name
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
2.85
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
UOS to PAD
1.7
3.2
7.6
1.7
3.6
8.8
ns
TESTIN to PAD
1.7
3.2
7.6
1.7
3.6
8.8
ns
PAD to TOUT
2.9
3.4
4.3
0.7
1.5
5.0
ns
Signal Path
Units
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD
0.10
0.10
0.20
0.10
0.10
0.20
ns/pF
TOUT
0.50
0.70
2.00
0.50
0.70
1.10
ns/pF
Output Name
Units
Intel
SP8237 -
SP8237
PROGRAMMABLE DMA CONTROLLER
IOWB
DBcn
MEMRB
DB7
MEMWB
DB6
READY
DBS
TREADY
DB4
HLDA
DB3
THLDA
DB2
ADSTB
DB1
AEN
DBO
HRQ
EOPBOUT
CSB
EOPBIN
TCSB
TEOPBIN
Functional Pin Diagram
•
G40208
Cell Version of the 82C37A Programmable DMA Controller; Functional Compatibility
with the Standard Product Assured.
•
12.5 MHz Operation.
•
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
•
Enable/Disable Control of Individual DMA Requests.
•
Four Independent DMA Channels.
•
Independent Auto-Initialization of all Channels.
•
Memory-to-Memory Transfers.
•
Memory Block Initialization.
•
Address Increment or Decrement.
•
Directly Expandable to any Number of Channels.
•
End of Process lnput for Terminating Transfers.
•
Software DMA Requests.
•
Independent Polarity Control for DREQ and DACK Signals.
INTRODUCTION TO CELL-BASED DESIGN
SP8237 DESCRIPTION
The Intel SP8237 is a high performance, CHMOS cell version of the industry standard
82C37A Programmable Direct Memory Access (DMA) Controller and is a peripheral interface circuit for microprocessor systems. It is designed to improve system performance by
allowing external devices to directly transfer information from the system memory. Memoryto-memory transfer capability is also provided. The SP8237 offers a wide variety of
programmable control features to enhance data throughput and system optimization and to
allow dynamic reconfiguration under program control.
The SP8237 is designed to be used in conjunction with an external 8-bit address register. It
contains four independent channels and may be expanded to any number of channels by
cascading additional controller chips.
The three basic transfer modes allow programmability of the types of DMA service by the
user. Each channel can be individually programmed to auto-initialize to its original condition following an End of Process.
Each channel has a full 64K address and word count capability.
The SP8237 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes the SP8237
and design specific support logic.
For a complete functional description of the 82C37 architecture, refer to the "82C37 A-5
CHMOS High Performance Programmable DMA Controller" data sheet in the Intel
Microprocessor and Peripheral Handbook.
Pin Description
Pin Type
Function
ClK
TCLK
I
CLOCK INPUT: Clock Input controls the internal operations of
the SP8237 and its rate of data transfers.
CSS
TCSS
I
CHIP SELECT: Chip Select is an active low input used to select
the SP8237 as an I/O device during the Idle cycle. This allows
CPU communication on the data bus.
RESET
TRESET
I
RESET: Reset is an active high input which clears the
Command, Status, Request and Temporary registers. It also
clears the first/last flip-flop and sets the Mask register.
Following a Reset the device is in the Idle cycle.
READY
TREADY
I
READY: Ready is an input used to extend the memory read
and write pulses from the SP8237 to accomodate slow
memories or I/O peripheral devices. Ready must not make
transitions during its specified setup/hold time.
Pin Name
SP8237
Pin Description (Cont'd.)
Pin Type
Function
HLDA
THLDA
I
HOLD ACKNOWLEDGE: The active high Hold Acknowledge
from the CPU indicates that is has relinquished control of the
system busses.
DREQO-3
TDREQO-3
I
DMA REQUEST: The DMA Request lines are individual
asynchronous channel request inputs used by peripheral
circuits to obtain DMA service. In fixed priority, DREQO has
the highest priority and DREQ3 has the lowest priority. A
request is generated by activating the DREQ line of a channel.
DACK will acknowledge the recognition of DREQ signal.
Polarity of DREQ is programmable. Reset initializes these lines
to active high. DREQ must be maintained until the corresponding DACK goes active.
DBO-7
I/O
DATA BUS: The Data Bus lines are bidirectional 3-state signals
connected to the system data bus. The outputs are enabled
in the Program condition during the I/O Read to output the
contents of an Address register, a Status register, the
Temporary register or a Word Count register to the CPU. The
outputs are disabled and the inputs are read during an I/O
Write cycle when the CPU is programming the SP8237 control
registers. During DMA cycles the most significant 8 bits of the
address are output onto the data bus to be strobed into an
-external latch by ADSTB. In memory-to-memory operations,
data from the memory comes into the SP8237 on the data bus
during the read-trom-memory transfer. In the write-to-memory
transfer, the data bus outputs place the data into the new
memory location.
10RB
I/O
I/O READ: I/O Read is a bidirectional active low 3-state line.
In the Idle cycle, it is an input control signal used by the CPU
to read the control registers. In the Active cycle, it is an output
control signal used by the SP8237 to access data from a
peripheral during a DMA Write transfer.
10WB
I/O
I/O WRITE: I/O Write is a bidirectional active low 3-state line.
In the Idle cycle, it is an input control signal used by the CPU
to load information into the SP8237. In the Active cycle, it is
an output control signal used by the SP8237 to load data to
the peripheral during a DMA Read transfer.
I
END OF PROCESS INPUT: End of Process Input is an active
low input signal used to terminate an active DMA service. The
reception of an active EOPBIN signal will cause the SP8237
to terminate the service, reset the request, and, if Autoinitialize is enabled, to write the base registers to the current registers of that channel. The mask bit and TC bit in the status
word will be set for the currently active channel by an active
EOPBIN signal unless the channel is programmed for Autoinitialize. In that case, the mask bit remains unchanged.
EOPBIN should be tied high if it is not used to prevent
erroneous end of process inputs.
Pin Name
EOPBIN
TEOPBIN
4-27
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
EOPBOUT
0
EOPBOUT: End of Process Output is an active low output
signal that indicates the completion of an active DMA service.
An active EOPBOUT signal is generated by the SP8237 when
the terminal count (TC) for any channel is reached. This causes
the SP8237 to terminate the service, reset the request, and, if
Autoinitialize is enabled, to write the base registers to the
current registers of that channel. The mask bit and TC bit in
the status word will be set for the currently active channel by
an active EOPBOUT signal unless the channel is programmed
for Autoinitialize. In that case, the mask bit remains unchanged.
During memory-to-memory transfers, an active EOPBOUT
signal will be output when the TC for channel 1 occurs.
AO-3
1/0
ADDRESS: The four least significant address lines are
bidirectional 3-state signals. In the Idle cycle they are inputs
and are used by the CPU to address the register to be loaded
or read. In the Active cycle they are outputs and provide the
lower 4 bits of the output address.
A4-7
0
ADDRESS: The four most significant address lines are 3-state
outputs and provide 4 bits of address. These lines are enabled
only during the DMA service.
HRQ
0
HOLD REQUEST: HRQ is an active high output signal and is
the Hold Request to the CPU. HRQ is used to request control
of the system bus. If the corresponding mask bit is clear, the
presence of any valid DREQ causes the SP8237 to issue the
HRQ. After HRQ goes active at least one clock (TCY) must
occur before HLDA goes active.
DACKO-.3
0
DMA ACKNOWLEDGE: DMA Acknowledge outputs are used
to notify the individual peripherals when one has been granted
a DMA cycle. The sense of these lines if programmable. Reset
initializes them to active low.
AEN
0
ADDRESS ENABLE: Address Enable is an active high output
used to enable an external 8-bit latch containing the upper
8 address bits onto the system address bus. AEN can also be
used to disable other system bus drivers during DMA
transfers.
ADSTB
0
ADDRESS STROBE: Address Strobe is an active high output
used to strobe the upper address byte into an external latch.
MEMRB
0
MEMORY READ: Memory Read is an active low 3-state output
used to access data from the selected memory location during
a DMA Read or memory-to-memory transfer.
MEMWB
0
MEMORY WRITE: Memory Write is an active low 3-state
output used to write data to the selected memory location
during a DMA Write or a memory-to-memory transfer.
4-28
inter
SP8237
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
DBCTL
0
DATA BUS CONTROL: The Data Bus Control signal is used
for data bus transceiver control. When this signal is high,
DBO-7 are being driven by the SP8237.
RWACTL
0
READ, WRITE, ADDRESS CONTROL: The Read, Write,
Address Control Signal is used for Read, Write and Address
Bus transceiver control. When this signal is high IORB,
MEMRB, IOWB, MEMWB, and AO-7 are being driven by the
SP8237.
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the SP8237 (see
table below). The SP8237 can operate in one of three modes:
user mode, ac,tive test mode, or inactive test mode.
TTEST
I
TMODE
TSEL
Function
0
0
1
1
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
TTEST is an input signal used only in test mode. It has no
corresponding user mode signal. TTEST is a mandatory
package pin.
NOTE: All signals Txxx are test related input signals. All test related signals except for TTEST, TMODE,
and TSEL have a user signal equivalent and are listed with their non-test counterpart. These test
signals have the identical functionality as their user signal equivalents, but are not used during normal
user operation. All test signals must be accessible through a package pin. This can be accomplished by tying the test signal to its user signal equivalent if it is directly connected to a package
pin, or to any other user input signal that is directly connected to a package pin. One package pin
for TMODE and TSEL is required per device, regardless of the number of cells implemented which
require these inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
Input Capacitance
Input Name
Max.
Units
AO
1.6
pF
A1
1.8
pF
A2
1.6
pF
A3
1.5
pF
CLK
0.8
pF
CSB
0.2
pF
4-29
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance (Cont'd.)
Input Name
Max.
Units
DBO
1.2
pF
DB1
1.1
pF
DB2
1.1
pF
DB3
1.5
pF
DB4
1.3
pF
DB5
1.1
pF
DB6
1.4
pF
DB7
1.1
pF
DREQO
0.4
pF
DREQ1
0.2
pF
DREQ2
0.2
pF
DREQ3
0.2
pF
EOPBIN
0.2
pF
HLDA
0.3
pF
IORB
0.7
pF
IOWB
0.6
pF
READY
0.2
pF
TMODE
1.0
pF
TSEL
1.0
pF
SP8237
3-State Output Capacitance
Output Name
Max.
Units
AO(z)
1.6
pF
A1 (z)
1.8
pF
A2 (z)
1.6
pF
A3 (z)
1.5
pF
A4(z)
i.5
pF
A5 (z)
1.5
pF
A6 (z)
1.4
pF
A7 (z)
1.4
pF
DBO (z)
1.2
pF
DB1 (z)
1.1
pF
DB2 (z)
1.1
pF
DB3(z)
1.5
pF
DB4 (z)
1.3
pF
DB5 (z)
1.1
pF
DB6 (z)
1.4
pF
DB7 (z)
1.1
pF
IORB(z)
0.7
pF
IOWB(z)
0.6
pF
MEMRB (z)
0.4
pF
MEMWB (z)
0.4
pF
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+ / -10%
NOTE: A.C. Characteristics are given to the edge of the SP8237 core. Additional delays will apply in
connecting SP8237 signals to package pins through selected I/O buffer cells.
DMA (MASTER) MODE
Symbol
parameter
Min.
Max.
Units
TAEl
AEN HIGH from ClK lOW
(SI) Delay Time
41.9
ns
TAET
AEN lOW from ClK HIGH
(SI) Delay Time
43.9
ns
TAFAB
Address Active to Float Delay from
ClK HIGH
58.4
ns
TAFC
10RB/MEMRB or 10WB/MEMWB
Float from ClK HIGH
55.6
ns
TAFDB
DB Active to Float Delay from
ClKHIGH
66.8
ns
TAHR
Address from 10RB/MEMRB HIGH
Hold Time
61.7
ns
TAHS
DB from ADSTB lOW Hold Time
15.6
ns
TAHW
Address from 10WB/MEMWB HIGH
Hold Time
74.0
ns
TAK
DACK Valid from ClK lOW
Delay Time (Note 2)
54.7
ns
EOPBOUT HIGH from ClK
HIGH Delay Time
41.5
ns
EOPBOUT lOW from ClK
HIGH Delay Time
45.5
ns
TASM
Address Stable from ClK HIGH
45.4
ns
TASS
DB to ADSTB lOW Setup Time
TCH
Clock HIGH Time (Transitions
~5
TCl
Clock lOW Time (Transitions
~5
TCY
ClK Cycle Time
58.7
ns
ns)
35.0
ns
ns)
35.0
ns,
80.0
ns
inter
SP8237
DMA (MASTER) MODE (Cont'd.)
Symbol
Max.
Units
ClK HIGH to IORB lOW Delay
27.2
ns
ClK HIGH to IOWB lOW Delay
31.5
ns
ClK HIGH to MEMRB lOW Delay
23.7
ns
ClK HIGH to MEMWB lOW Delay
30.6
ns
IORB HIGH from ClK HIGH
(S4) Delay Time
58.3
ns
MEMRB HIGH from ClK HIGH
(S4) Delay Time
57.9
ns
IOWB HIGH from ClK HIGH
(S4) Delay Time
45.6
ns
MEMWB HIGH from ClK HIGH
(S4) Delay Time
46.0
ns
TOO
HRO Valid from ClK HIGH
Delay Time
40.2
ns
TEPS
EOPBOUT lOW from ClK lOW
Setup Time
TEPW
EOPBIN Pulse Width
TFAAB
Address Float to Active Delay from
ClK HIGH
60.0
ns
TFAC
IORB/MEMRB or IOWB/MEMWB
Active from ClK HIGH
56.0
ns
TFADB
DB Float to Active Delay from
ClK HIGH
73.3
ns
THS
HlDA valid to ClK HIGH Setup Time
0
ns
TIDH
Input Data from MEMRB HIGH
Hold Time
3.0
ns
TIDS
Input Data to MEMRB HIGH
Setup Time
10.0
ns
TODH
Output Data from MEMWB HIGH
Hold Time
2.7
ns
TODV
Output Data Valid to MEMWB HIGH
60.2
ns
TDCl
TDCTR
TDCTW
Parameter
Min.
0
ns
20.0
ns
INTRODUCTION TO CELL-BASED DESIGN
DMA (MASTER) MODE (Cont'd.)
Symbol
Parameter
TQS
DREQ to ClK lOW (SI,S4)
Setup Time (Note 2)
TRH
Min.
Max.
Units
0
ns
ClK to READY lOW Hold Time
11.0
ns
TRS
READY to ClK lOW Setup Time
11.0
ns
TSTl
ADSTB HIGH from ClK HIGH
Delay Time
52.7
ns
TSTT
ADSTB lOW from ClK HIGH
Delay Time
50.3
ns
TDEl
DBCTl lOW from ClK HIGH
Delay Time
63.1
ns
TDEH
DSCTl HIGH from ClK HIGH
Delay Time
63.1
ns
TRWEl
RWACTl lOW from ClK HIGH
Delay Time,
49.8
ns
TRWEH
RWACTl HIGH from ClK HIGH
Delay Time
50.8
ns
TWR
End of IOWS/M EMWS to End of
IORB/MEMRS in DMA Transfer
ns
0
PERIPHERAL (SLAVE) MODE
Symbol
TAR
TAW
Parameter
Address Valid or CSS lOW to
laRS lOW
: Address Valid to lOWS HIGH
Setup Time
Min.
Max.
Units
0
ns
8.0
ns
TCW
CSS lOW to lOWS HIGH Setup Time
23.0
ns
TOW
Data Valid to lOWS HIGH Setup Time
8.0
ns
TRA
Address or CSS Hold from
laRS HIGH
0
ns
TRDE
Data Access from IORB lOW
79.5
ns
SP8237
PERIPHERAL (SLAVE) MODE (Cont'd.)
Symbol
Parameter
Min.
Max.
Units
7.2
29.2
ns
TRDF
DB Float Delay from IORB HIGH
TRSTD
Power Supply HIGH to RESET lOW
Setup Time
500.0
ns
TRSTS
RESET to First IORB or IOWB
2TCY
ns
TRSTW
RESET Pulse Width (Note 4)
160.0
ns
TRW
IORB Width
75.0
ns
TWA
Address from IOWB HIGH Hold Time
13.0
ns
TWC
CSB HIGH from IOWB HIGH
Hold Time
15.0
ns
TWO
Data from IOWB HIGH
Hold Time
43.0
ns
TWWS
IOWB Width
30.0
ns
TRDEl
DBCTl lOW from IORB HIGH
Delay Time
25.5
ns
TRDEH
DBCTl HIGH from IORB lOW
Delay Time
30.1
ns
TCDEl
DBCTl lOW from CSB HIGH
Delay Time
37.8
ns
NOTES:
1. DREQ should be held active until DACK is returned.
2. DREQ and DACK signals may be active high or active low. Timing diagrams assume the active high
mode.
3. Successive read and/or write operations by the external processor to program or examine the controller
must be timed to allow at least 160 ns for the SP8237 as recovery time between active read or write
pulses. The same recovery time is needed between an active read or write pulse followed by a DMA
.
transfer.
4. In order to properly reset the SP8237, the clock signal (ClK) should be driven low during reset or should
be allowed to run during reset and, at least one clock cycle after reset.
4-35
Intel
INTRODUCTION TO CELL-BASED DESIGN
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
AO-7
0.2
0.4
1.2
0.3
0.4
0.8
ns/pF
ADSTB
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
AEN
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
DACKO-3
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
OBO-7
0.2
0.4
1.2
0.3
0.4
0.8
ns/pF
OBCTL
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
EOPBOUT
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
HRQ
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
IORB
0.2
0.4
1.2
0.3
0.4
0.8
ns/pF
IOWB
0.2
0.4
1.2
0.3
0.4
0.8
ns/pF
MEMRB
0.2
0.4
1.2
0.3
0.4
0.8
ns/pF
MEMWB
0.2
0.4
1.2
0.3
0.4
0.8
ns/pF
RWACTL
0.3
0.7
2.0
0.5
0.7
1.2
ns/pF
Output Name
Units
inter
SP8237
TCW
CSB
1_
TWC
(NOTE 3)
TWWS
IOWB
-----TAW
AO-A3
INPUT VAllO
TWO
TOW
INPUT VAllO
OBO-OB7
Slave Mode Write Timing
G40208
~ d---:---ADDR-ESS
MUST BE VALID ~fr--IORB __t_T_AR_-J-.ltf_-------TRW --------?-l~TR~3D)F--I
_______~f-~==~~~~~_-_-___TRD_E~~~~~~~~~~~~1------~--~--------4
1
OO~
(
I
~~~
~
DBeTL_---=-_-_TRDEH--==jl.---------!--.:..~_TCDE~
~TRDEL
Slave Mode Read Timing
----rG40208
INTRODUCTION TO CELL-BA$ED DESIGN
ClK
j~rltlH~H:rlrlH~rlt~rL' ~lt · ~
-l
~
8'
LL/I
\ \ "l\"l\\ I\\\'
~- F
. ' ~-i~
TOSi--
OREO
I--
TOSI--
t--
!--TCY-
=
(NOTE 1)
THSHLDA
I
I
I--
///1
1\\' l\\\\\\\\\
TAEll-H
TAET
Vt
I
- -
TSTT
TSTL I - AOSTB
I
DBO-007
t-
I--
TEPS
1\
~
trQTASS
~ ~rs
TFAOB
I--
TFAAB
I-- t m T 1
i
I--
FOB
I
l -I-
-
t---TAFAB
TAHW
~
t--TAHW
ADDRESS VALID
i.
I--I- I-TAHR
~
I
TFAC
~
t-l..--
IORB, MEM RB
I
~
TOCTR -
H. 7
":R~TENO~O
I
TOCTW
WRITE I
i
TEPW
I
TeCTR
t-TAHR
"---
I--
-~
~
I-- f-
IOWB,MEMW B
EOPBOUT
TASM
ADDRESS VALID
~
DACK
~
I
-f-.
t-- TAFC
r""
TOCTW
'i
~
-::
I
~R
11-:"'"
~
~T\:;-J'
\' 1\\\\ 1\\\\\' l1//////;//m
EOPBIN
!-TOEH .... !-TDEl--
/' r\~
I
TRWEH_
!-TRWEl_
I-
/~
~~.
j
RWACTL
DMA Transfer Timing
4-38
G40208
inter
SP8237
ADSTB
AO-AT
DBO-DBT
MEMAB
-----+---4r
MEMWB
-----+---4r
EOPBOUT
-----+--+--4-----------1--+---+----+-"\.1
EOPBIN
---.--.-...-n
DBCTL
-----+-----'
TAWEL
TAWEH
AWACTL
-----I--J
Memory-to-Memory Transfer Timing
G40208
CLK
TDCTR
TDCL--+--I
IORB, MEMRB
I--+-I--TDCL
TDCL
IOWB, MEMWB
READY
TDCTW--
/'
~~\\Z"Z1J=- -IllT'"
Ready Timing
4-39
G40208
INTRODUCTION TO CELL-BASED DESIGN
ClK
AO-A7
TDCl-i--i-1
IORB, MEMRB
-TWR
IOWB,MEMWB
READY
TAK-
EOPBOUT
EOPBIN
--------------1.--""'1
to
n:!"'----Lt
------\r-I["""'~
Compressed Transfer Timing
G40208
--------L+l
--------,-----
II
Voo
1It---------rl----TRSTD
1
TRSTW
----
1
---~-;... ~
RESET _ _ _ _ _ _ _ _ _ _..J
.
~
lOR OR lOW
Reset Timing
4-40
G40208
SP8254
SP8254 -
PROGRAMMABLE INTERVAL TIMER
AOP
OOE
TAOP
07
AlP
06
TA1P
05
ROL
04
TROL
03
WRL
02
TWRL
01
CSL
00
TCSL
Functional Pin Diagram
G40208
•
Cell Version of the 82C54 Programmable Interval Timer; Functional Compatibility with
the Standard Product Assured.
•
•
12.5 MHz Operation.
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
•
Handles Inputs from DC to 12.5 MHz.
•
Three Independent 16 Bit Counters.
•
•
Six Programmable Counter Modes.
Binary or BCD Counting.
INTRODUCTION TO CELL-BASED DESIGN
SP8254 DESCRIPTION
The Intel SP8254 is a high performance, CHMOS cell version of the industry standard
82C54 Programmable Interval Timer designed to solve the timing control problems common
in microcomputer system design. It provides three independent 16-bit counters, each capable
of handling clock inputs up to 12.5 MHz. All modes are software programmable.
Six programmable timer modes allow the SP8254 to be used as an event counter, elapsed
time indicator, programmable one-shot, and in many other applications.
The SP8254 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library~
allowing the designer to implement a semi-custom integrated circuit that includes the SP8254
and design specific support logic.
For a complete functional description of the 82C54 architecture, refer to the "82C54
CHMOS Programmable Interval Timer" data sheet in the Intel Microprocessor and
Peripheral Handbook.
Pin Description
Pin Name
00-7
Pin Type
Function
I/O
DATA: Bidirectional 3-state data bus lines, connected to
system data bus through a transceiver.
CLKO
TCLKO
I
QUTO
0
GATEO
TGATEO
I
CLK1
TCLK1
I
QUT1
0
GATE1
TGATE1
I
CLK2
TCLK2
I
QUT2
0
GATE2
TGATE2
I
CLOCK 0: Clock input of Counter O.
OUTPUT 0: Output of Counter O.
GATE 0: Gate input of Counter O.
CLOCK 1: Clock input of Counter 1.
OUTPUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 2:
Cloc~
input of Counter 2.
OUTPUT 2: Output of Counter 2.
GATE 2: Gate input of Counter 2.
SP8254
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
AOP,A1P
TAOP,TA1P
I
ADDRESS: Used to select one of the three Counters or the
Control Word Register for read or write operations. Normally
connected to the system address bus.
A1P
AOP
0
0
1
1
0
1
0
1
Selects
Counter 0
Counter 1
Counter 2
Control Word Register
CSL
TCSL
I
CHIP SELECT: A low on this input enables the SP8254 to
respond to RDL and WRL signals. RDL and WRL are ignored
otherwise.
RDL
TRDL
I
READ CONTROL: This input is low during CPU read
operations.
WRL
TWRL
I
WRITE CONTROL: This input is low during CPU write
operations.
DOE
0
DATA DRIVE ENABLE: Used for data bus transceiver control.
When this signal is high, 00-7 are being driven by the SP8254.
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the SP8254 (see
table below). The SP8254 can operate in one of three modes:
user mode, active test mode, or inactive test mode.
TMODE
TSEL
Function
0
0
1
1
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal equivalents, but are not used during normal user
operation. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
4-43
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Max.
Units
AOP,A1P
0.3
pF
CLKO
0.3
pF
CLK1
0.3
pF
CLK2
0.3
pF
CSL
0.3
pF
00-7
0.6
pF
GATEO
0.3
pF
GATE1
0.3
pF
GATE2
0.3
pF
ROL
0.3
pF
TMOOE
0.3
pF
TSEL
. 0.3
pF
WRL
0.3
pF
Input Name
3-State Output Capacitance
Output Name
Max.
Units
00-7 (z)
0.6
pF
SP8254
A.C. Characteristics at 0-70°C, 5V+ / -10%
NOTE: A.C. Chracteristics are given to the edge of the SP8254 core. Additional delays will apply in connecting SP8254 signals to package pins through selected I/O buffer cells.
BUS PARAMETERS (NOTE 1)
READ CYCLE
Symbol
Min.
Parameter
tAR
Address Stable Before RDL
tSR
CSL Stable Before RDL
tRA
Address Hold Time After RDL t
tRR
RDL Pulse Width
tRD
Data Delay from RDL
tOF
RDL t to Data Floating
tRV
Command Recovery Time
tRE
DDE Active After RDL
tEE
DDE Pulse Width
.L-
.L-
Max.
Units
5.0
ns
0
ns
0
ns
22.0
ns
.L-
4.0
33.0
ns
19.0
ns
122.0
ns
17.0
.L-
22.0
ns
ns
WRITE CYCLE
Symbol
Min.
Parameter
tAW
Address Stable Before WRL
tSW
CSL Stable Before WRL
tWA
Max.
Units
0
ns
0
ns
Address Hold Time After WRL t
0
ns
tWW
WRL Pulse Width
63.0
ns
tOW
Data Setup Time Before WRL t
44.0
ns
tWD
Data Hold Time After WRL t
0
ns
tRV
Command Recovery Time
122.0
ns
.L-
.L-
Intel
INTRODUCTION TO CELL-BASED DESIGN
CLOCK AND GATE
Symbol
Parameter
Max.
Min.
Units
tClK
Clock Period
80.0
ns
tPWH
Clock High Pulse Width (Note 3)
26.0
ns
tPWl
Clock low Pulse Width (Note 3)
40.0
ns
tGW
Gate Width High
40.0
ns
tGl
Gate Width low
40.0
ns
tGS
Gate Setup Time to ClK t
8.0
ns
tGH
Gate Hold Time After ClK t (Note 2)
9.0
ns
tOO
Output Delay from ClK ,j,
31.0
ns
tODG
Output Delay from Gate "-
30.0
ns
tWC
ClK Delay for Loading
51.0
ns
tWG
Gate Delay for Sampling
17.0
ns
tWO
OUT Delay from Mode Write
73.0
ns
tCl
ClK Setup for Count latch
5.0
ns
0
1.0
-10.0
NOTES:
1. A.C. timings measured at Vth (crosspoint threshold voltage)
=
2.25V.
2. In modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 56 ns of the
rising clock edge may not be detected.
3. low-going glitches that violate tPWH, tPWl may cause errors requiring counter reprogramming.
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
00-7
0.2
0.3
0.9
0.2
0.3
0.5
ns/pF
DOE
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
aUTO
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
OUT1
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
OUT2
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
Output Name
Units
inter
SP8254
AOP, AlP
-I.w-
-
CSL
DATA BUS
VALID
low _ _ 1wo_
WRL
Write
G40208
.....- - I... A----+I
CSL
ROL
OATABUS - - -
DOE
Read
G40208
Recovery
G40208
ROL, WRL
4-47
INTRODUCTION TO CELL-BASED DESIGN
WRl
ClK
GATE
OUTO
• Last byte of count being written
Clock and Gate
G40208
SP8259
SP8259 -
PROGRAMMABLE INTERRUPT CONTROLLER
IRO
TIRO
IR1
TIR1
INT
IR2
OBCTL
TIR2
DO
IR3
01
TIR3
02
IR4
03
TIR4
04
IRS
05
TIRS
06
IR6
07
•
TIR6
IR
TIR7
Functional Pin Diagram
G4020B
•
Cell Version of the 82C59A Programmable Interrupt Controller; Functional Compatibility with the Standard Product Assured.
•
12.5 MHz Operation.
•
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1% AQL or Better.
•
Eight-Level Priority Interrupt Controller.
•
Expandable to 64 Levels.
•
Programmable Interrupt Modes.
•
Individual Request Mask Capability.
•
Fully Static Design.
INTRODUCTION TO CELL-BASED DESIGN
SP8259 DESCRIPTION
The Intel SP8259 is a high performance, CHMOS cell version of the industry standard
82C59A Programmable Interrupt Controller. The SP8259 is designed to relieve the system
CPU from the task of polling in a multi-level priority interrupt system.
The SP8259 can handle up to 8 vectored priority interrupts for the CPU and is cas cad able
to 64 without additional circuitry. It is designed to minimize the software and real time
overhead in handling multi-level priority interrupts. Two modes of operation make the SP8259
optimal for a variety of system requirements.
The SP8259 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes the SP8259
and design specific support logic.
For a complete functional description of the 82C59A architecture, refer to the "82C59A-2
CHMOS Programmable Interrupt Controller" data sheet in the Intel Microprocessor and
Peripheral Handbook.
Pin Description
Pin Name
Pin Type
Function
CS
TCS
I
CHIP SELECT: A low on this pin enables RD and WR
communication between the CPU and the SP8259. INTA
functions are independent of CS.
WR
TWR
I
WRITE: A low on this pin when CS is low enables the SP8259
to accept command words from the CPU.
RD
TRD
I
READ: A low on this pin when CS is low enables the SP8259
to release status onto the Data Bus for the CPU.
INTA
TINTA
I
INTERRUPT ACKNOWLEDGE: This pin is used to enable
SP8259 interrupt vector data onto the Data Bus by a
sequence of interrupt acknowledge pulses issued by the
CPU. INTA is active low.
AO
TAO
I
AO ADDRESS LINE: This pin acts in conjunction with the CS,
WR, and RD pins. It is used by the SP8259 to decipher
various Command Words the CPU writes and status the CPU
wishes to read. It is typically connected to the CPU AO
address line (A 1 for 80C86, 80C88).
IRQ-7
TIRO-7
I
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to high)
and holding it high until it is acknowledged (Edge Triggered
Mode), or just by holding a high level on the IR input (Level
Triggered Mode).
4-50
inter
SP8259
Pin Description (Cont'd.)
Pin Type
Function
INT
0
INTERRUPT: This pin goes high whenever a valid interrupt
request is asserted. It is used to interrupt the CPU, thus it is
connected to the CPU's interrupt pin.
00-7
I/O
DATA BUS: Bidirectional 3-state data bus lines, connected
to system data bus through a transceiver. Control, status and
interrupt vector information is transferred via this bus.
DBCTL
0
DATA BUS CONTROL: Used for data bus transceiver control.
When this signal is high, 00-7 are being driven by the SP8259.
CASO-2
I/O
CASCADE LINES: The CAS lines form a private bus to control
a multiple SP8259 structure. These pins are outputs for a
Master SP8259 and inputs for a Slave SP8259.
CASCTL
0
CASCADE CONTROL: Used for cascade lines transceiver
control. When this signal is high, CASO-2 are being driven by
the SP8259.
I/O
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function
pin. When in the Buffered Mode, it can be used as an output
to control buffer transceivers (EN). When not in the Buffered
Mode, it is used as an input to designate a Master (SP=1)
or a Slave (SP=O).
Pin Name
SPEN
SPCTL
o~
TMODE, TSEL
I
SPEN CONTROL: Used for SPEN transceiver control. When
this signal is high, SPEN is being driven by the SP8259.
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the SP8259 (see
table below). The SP8259 can operate in one of three modes:
user mode, active test mode, or inactive test mode.
TMODE
TSEL
Function
0
0
1
1
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal equivalents, but are not used during normal user
operation,. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
4-51
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
AO
0.3
pF
CASO-2
0.6
pF
CS
0.3
pF
00-7
0.6
pF
INTA
0.3
pF
IRO-7
0.3
pF
RD
0.3
pF
SPEN
0.6
pF
TMODE
0.3
pF
TSEL
0.3
pF
WR
0.3
pF
3-State Output Capacitance
Output Name
Max.
Units
DO-7 (z)
0.6
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
NOTE: A.C. Characteristics are given to the edge of the SP8259 core. Additional delays will apply in
connecting SP8259 signals to package pins through selected I/O buffer cells.
BUS PARAMETERS (NOTE 1)
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
TAHRL
AO/CS Setup to RD/INTA ..
0
ns
TRHAX
AO/CS Hold after RD/INTA t
0
ns'
TRLRH
RD/INTA Pulse Width
75.0
ns
TAHWL
AO/CS Setup to WR ..
0
ns
TWHAX
AO/CS Hold after WR t
0
ns
inter
SP8259
TIMING REQUIREMENTS (Cont'd.)
Symbol
Parameter
Min.
Max.
Units
TWLWH
WR Pulse Width
75.0
ns
TDVWH
Data Setup to WR t
40.0
ns
TWHDX
Data Hold after WR t
0
ns
TJLJH
Interrupt Request Width (Low)
15.0
ns
TCVIAL
Cascade Setup to Second or Third
INTA '" (Slave Only)
20.0
ns
TRHRL
End of RD to next RD, End of INTA
to next INTA within an INTA
sequence only
75.0
ns
TWHWL
End of WR to next WR
75.0
ns
TCHCL
End of Command to Next Command
(Not Same Command Type)
75.0
ns
TIMING RESPONSES
Symbol
Parameter
Min.
Max.
Units
75.0
ns
40.0
ns
TRLDV
Data Valid from RD/INTA '"
TRHDZ
Data Float after RD/INTA t
TJHIH
Interrupt Output Delay
40.0
ns
TIALCV
Cascade Valid from First INTA '"
(Master Only)
40.0
ns
TRLEL
Enable Active from RD/INTA
50.0
ns
TRHEH
Enable Inactive from RD/INTA t
30.0
ns
10.0
J,.
NOTES:
1. A.C. timings measured at Vth (crosspoint threshold voltage)
4-53
= 2.25V.
INTRODUCTION TO CELL-BASED DESIGN
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
CASO-2
0.2
0.3
0.9
0.2
0.3
0.5
ns/pF
CASCTL
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
00-7
0.2
0.3
0.9
0.2
0.3
0.5
ns/pF
OBCTL
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
INT
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
SPCTL
0.3
0.6
1.6
0.5
0.7
1.2
ns/pF
SPEN
0.2
0.3
0.9
0.2
0.3
0.5
ns/pF
Output Name
Units
SP8259
WR----------------------~
TAHWL
--
CS----------------~
ADDRESS BUS
AO----------------J
DATA BUS
Write
t-----
TRLRH
G40208
- - - - - I ,,.._ _ _ _ _ _ _ _ __
RD
INTA
TRLEL
EN
TRHAX
CS --------------"'"
ADDRESS BUS
AO _ _ _ _ _ _ _ _ _ _ _.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRH~
-t"--_________________1
TRCDV-t
DATA BUS -
Read/INTA
4-55
'
.. _ _ _ _ _ _
G40208
INTRODUCTION TO CELL-BASED DESIGN
RD
INTA
\
\
\
WR
RD
INTA
WR
J='"""'=+
jf=.wow,=t\
CT~'=)
RD
INTA
WR
I
I
I
Other Timing
G40208
IR
INT _ _ _ _ _ _- - J
INTA-----------,.
DATA
BUS -
-
-
-
-
-
-
-
-
-
-
--
-TCVIAL
--1_ _ _ _
CASO-2 _ _ _ _ _ _ _ _ _ _
~I_---L---..L......L..---------Io-
-TIALCV--
INTASequence
4-56
G40208
inter
SP8284 -
SP8284
8086/8088 CLOCK GENERATOR AND DRIVER
IRESB
IClK
IFCB
IPClK
IEFI
SP8284
IXTAl
ICSYNC
IOSC
IREADYB
IRESET
Functional Pin Diagram
G40208
•
Cell Version of the 82C84A 8086/8088 Clock Generator and Driver; Functional
Compatibility with the Standard Product Assured.
•
12.5 MHz Operation.
•
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
•
Generates the System Clock for the 8086 and 8088 Microprocessor Families.
•
Uses a Crystal or an External Frequency Source.
•
Provides Local READY Synchronization.
•
Generates System Reset Output.
•
Capable of Clock Synchronization with other SP8284 Cells.
INTRODUCTION TO CELL-BASED DESIGN
SP8284 DESCRIPTION
The Intel SP8284 is a high performance, CHMOS cell version of the industry standard
82C84A Clock Generator and Driver designed to service the requirements of the 80C86/88
and 8086/88. The chip contains a divide-by-three counter and complete READY synchronization and reset logic. A specially designed oscillator cell (POSC2) used in conjunction
with the SP8284 provides for operation from an external crystal. An external frequency
source may also be used.
The SP8284 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes the SP8284
and design specific support logic.
For a complete functional description of the 82C84A architecture, refer to the "82C84A/
82C84A-5 CHMOS Clock Generator and Driver for 80C86, 80C88 Processors" data sheet
in the Intel Microprocessor and Peripheral Handbook.
Pin Description
Pin Type
Function
IClK
0
PROCESSOR CLOCK: IClK is the clock output used by the
processor and all devices which directly connect to the
processor's local bus. IClK has an output frequency which
is one third of the IXTAl or IEFI input frequency and one third
duty cycle.
IFCB
I
FREQUENCY/CRYSTAL SELECT: When lOW, IFCB permits
the processor's clock to be generated from the IXTAl input.
When IFCB is HIGH, IClK is generated from the IEFI input.
IEFI
I
EXTERNAL FREQUENCY: When IFCB is high, IClK is generated from the frequency appearing on this pin. The input signal
is a square wave 3 times the frequency of the desired IClK
output.
IXTAl
I
EXTERNAL CRYSTAL IN: IXTAl is the pin to which the output
of the SP8284 oscillator companion cell POSC2 is attached.
The crystal frequency is 3 times the desired processor clock
frequency.
IPClK
0
PERIPHERAL CLOCK: IPClK is a peripheral clock signal
whose output frequency is one-half that of IClK and has a
50% duty cycle.
IOSC
0
OSCillATOR OUTPUT: IOSC is the oscillator output equal
in frequency to that of IXTAL.
Pin Name
inter
SP8284
Pin Description (Cont'd.)
Pin Type
Function
IAEN1B
IAEN2B
I
ADDRESS ENABLES: Active LOW signals which qualify their
respective Bus Ready Signals (IRDY1, IRDY2). Two IAEN
signals are useful in system configurations which permit the
processor to access two Multi-Master system busses. In non
Multi-Master configurations the IAEN signals are tied true
(low).
IRDY1
IRDY2
I
BUS READY (Transfer Complete): IRDY is an active HIGH
signal which is an indication from a device located on the
system data bus that the data has been received, or is available. IRDY1 and IRDY2 are qualified by IAEN1 and IAEN2
respectively.
IASYNCB
I
READY SYNCHRONIZATION SELECT: IASYNCB is an input
which defines the synchronization mode of the READY logic.
When IASYNCB is LOW, two stages of READY synchronization are provided. When IASYNCB is HIGH, a single stage of
ready synchronization is provided.
IREADYB
0
READY: IREADYB is an active LOW signal which is the
synchronized IRDY input signal. IREADYB is cleared after the
guaranteed hold time to the processor has been met.
ICSYNC
I
CLOCK SYNCHRONIZATION: ICSYNC is an active HIGH
signal which allows multiple SP8284s to be synchronized to
provide clocks that are in phase. When ICSYNC is HIGH the
internal counters are reset. When ICSYNC goes LOW the
internal counters are allowed to resume counting. ICSYNC
needs to be externally synchronized to IEF!. When using the
crystal oscillator ICSYNC should be connected to ground.
IRESB
I
RESET IN: IRESB is an active LOW signal which is used to
generate IRESET.
IRESET
0
RESET: IRESET is an active HIGH signal which is used to
reset the processor. Its timing characteristics are determined
by IRESB.
Pin Name
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
IAEN1B,
IAEN2B
0.05
pF
IASYNCB
0.05
pF
ICSYNC
0.19
pF
IEFI
0.05
pF
IFCB
0.10
pF
IRDY1,
IRDY2
0.10
pF
IRESB
0.06
pF
IXTAl
0.10
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
NOTE: A.C. Characteristics are given to the edge of the SP8284 core. Additional delays will apply in
connecting SP8284 signals to package pins through selected I/O buffer cells.
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
tEHEl
External Frequency HIGH Time
13.0
ns
tElEH
External Frequency lOW Time
13.0
ns
26.0
ns
12.0
ns
5.0
ns
- 6.0
ns
12.0
ns
6.0
ns
1.0
ns
6.0
ns
tElEl
. IEFI/IXTAl Period
tR1VCl
IRDY1/IRDY2 Active/Inactive
Setup to IClK
tR1VCH
IRDY1/IRDY2 Active Setup to IClK
tClR1X
IRDY1/IRDY2 Hold to IClK
tAYVCl
IASYNCB Setup to IClK
tClAYX
IASYNCB Hold to IClK
tA1VR1V
IAEN1 B/IAEN2B Setup to
IRDY1/IRDY2
tClA1X
IAEN1 B/IAEN2B Hold to IClK
-
-
SP8284
TIMING REQUIREMENTS (Cont'd.)
Symbol
Parameter
Max.
Min.
Units
tYHEH
ICSYNC Setup to IEFI
4.0
ns
tEHYl
ICSYNC Hold to IEFI
6.0
ns
tYHYl
ICSYNC Width
9.0
ns
tl1 HCl
IRESB Setup to IClK
4.0
ns
tCLl1 H
IRESB Hold to IClK
2.0
ns
TIMING RESPONSES
Parameter
Min.
tClCl
IClK Cycle Period
80.0
ns
tCHCl
JClK HIGH Time
(V3 tClCl) +5.8
ns
tClCH
IClK lOW Time
(2/:dClCl) -7.1
ns
tPHPl
IPClK HIGH Time
tClCl -0.1
ns
tPlPH
IPClK lOW Time
tClCl +0.1
ns
tRYlCl
IREADYB Inactive to IClK
3.5
ns
tRYHCH
IREADYB Active to IClK
(2/3 tClCl) -13.4
ns
tCLIl
IClK to IRESET Delay
tClPH
Symbol
Max.
Units
8.5
ns
IClK to IPClK HIGH Delay
12.7
ns
tClPl
IClK to IPClK lOW Delay
12.6
ns
tOlCH
IOSC to IClK HIGH Delay
-3.0
9.2
ns
tOlCl
IOSC to IClK lOW Delay
-8.8
16.3
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
IClK
0.25
0.57
1.53
0.45
0.67
1.19
ns/pF
IOSC
0.33
0.74
1.96
0.46
0.67
1.19
ns/pF
IPClK
0.33
0.73
1.96
0.46
0.67
1.19
ns/pF
IREADYB
0.08
0.16
0.42
0.13
0.20
0.38
ns/pF
IRESET
0.32
0.73
1.95
0.45
0.67
1.17
ns/pF
Output Name
4-61
Units
INTRODUCTION TO CELL-BASED DESIGN
NAIIE
IEFf
IOSC
IClK
0
IPClK
0
ICSYNC
I
IRESB
IRESET
0
____~/-------------~~t:
Clocks and Reset Signals
G40208
Ready Signals (for Asynchronous Devices)
G40208
IClK
IRDY1,2
IAEN1,2B
IASYNCB
IREADYB
4-62
SP8284
IClK
IRDY1.2
IAEN1.2B
IASYNCB
IREADYB
IRYlCL
Ready Signals (for Synchronous Devices)
4-63
G40208
INTRODUCTION TO CELL-BASED DESIGN
SP8288 -
8086/8088 BUS CONTROLLER
MRDC
MWTC
SOB
S1B
AMWC
S2B
10RC
10WC
SP8288
AIOWC
INTA
ClK
AENB
DTRB
CEN
DENB
PDENMCEB
lOB
AlEB
o
:!
~z ~
LU 15
c(
Functional Pin Diagram
G40208
•
Cell Version of the 82C88 8086/8088 Bus Controller; Functional Compatibility with
the Standard Product Assured.
•
•
•
•
•
12.5 ~Hz Operation.
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
Provides Support for 8086/88,80186/188 Microprocessor Families.
Provides Advanced Commands for Multi-Master Busses.
3-State Command Output Drivers.
•
Configurable for Use with an I/O Bus.
SP8288
SP8288 DESCRIPTION
The Intel SP8288 is a high performance, CHMOS cell version of the industry standard
82C88 Bus Controller. The SP8288 provides command and control timing generation for
8086/88, 80186/188 architecture systems. Specially designed SP8288 high drive output
buffer companion cells eliminate the need for additional bus drivers when used in conjunction with the SP8288.
The SP8288 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes the SP8288
and design specific support logic.
For a complete functional description of the 82C88 architecture, refer to the "82C88
CHMOS Bus Controller" data sheet in the Intel Microprocessor and Peripheral Handbook.
Pin Description
Pin Name
SOB
S1B
S2B
Pin Type
Function
I
STATUS INPUT PINS: These pins are the status input pins
from the processor. The SP8288 decodes these inputs to
generate command and control Signals at the appropriate
time. When these pins are not in use (passive) they are all
HIGH.
"
CLK
I
CLOCK: This is a clock signal from the SP8284 clock generator and serves to establish when command and control
signals are generated.
ALEB
0
ADDRESS LATCH ENABLE: This signal serves to strobe an
address into the address latches. This Signal is active LOW
and latching occurs on the rising (LOW to HIGH) transition.
DENB
0
DATA ENABLE: This Signal serves to enable data transceivers onto either the local or system data bus. This signal is
active LOW.
DTRB
0
DATA TRANSMIT/RECEIVE: This Signal establishes the
direction of data flow through the transceivers. A LOW on
this line indicates Transmit (write to I/O or memory) and a
HIGH indicates Receive (Read).
AENB
I
ADDRESS ENABLE: AENB enables command outputs of the
SP8288 at least 145 ns after it becomes active (LOW) via
the ENABIO and ENABMEM Signals. AENB going inactive
immediately 3-states the command output drivers via the
TRISTATEIO (I/O Bus Mode) and TRISTATEMEM signals.
4-65
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Type
Function
CEN
I
COMMAND ENABLE: When this signal is LOW all SP8288
command outputs and the DENB and PDENMCEB control
outputs are forced to their inactive state. When this signal
is HIGH, these same outputs are enabled. The command
outputs are controlled by the ENABIO and ENABMEM
signals.
lOB
TIOB
I
INPUT/OUTPUT BUS MODE: When lOB is HIGH the SP8288
functions in the I/O Bus mode. When LOW, the SP8288
functions in the System Bus mode.
AIOWC
0
ADVANCED I/O WRITE COMMAND: This command line
issues an I/O Write Command earlier in the machine cycle
to give I/O devices an early indication of a write instruction.
Its timing is the same as a read command signal. AIOWC is
active HIGH.
10WC
0
I/O WRITE COMMAND: This command line instructs an I/O
device to read the data on the data bus. 10WC is active HIGH.
10RC
0
I/O READ COMMAND: This command line instructs an I/O
device to drive its data onto the data bus. 10RC is active
HIGH.
AMWC
0
ADVANCED MEMORY WRITE COMMAND: This command
line issues a memory write command earlier in the machine
cycle to give memory devices an early indication of a write
instruction. Its timing is the same as a read command signal.
AMWC is active HIGH.
MWTC
0
MEMORY WRITE COMMAND: This command line instructs
the memory to record the data present on the data bus.
MWTC is active HIGH.
MRDC
0
MEMORY READ COMMAND: This command line instructs
the memory to drive its data onto the data bus. MRDC is
active HIGH.
INTA
0
INTERRUPT ACKNOWLEDGE: This signal tells an interrupting device that its interrupt has been acknowledged and
that it should drive the vectoring information onto the data
bus. INTA is active HIGH.
PDENMCEB
0
This is a dual function pin.
MCEB (lOB LOW): MASTER CASCADE ENABLE, occurs
during an interrupt sequence and serves to read a Cascade
Address from a master PIC (Priority Interrupt Controller) onto
the data bus. MCEB is active LOW.
I
Pin Name
PDEN (lOB HIGH): PERIPHERAL DATA ENABLE, enables
the data bus transceiver for the I/O bus that DENB performs
for the system bus. PDEN is active HIGH.
4-66
SP8288
Pin Description (Cont'd.)
Pin Type
Function
TRISTATEIO
0
3-STATE I/O: This signal is used as a 3-state control signal
for the I/O command signals (INTA, 10RC, AIOWC, 10WC).
TRISTATEIO is active HIGH.
TRISTATEMEM
0
3-STATE MEMORY: This signal is used as a 3-state control
signal for the memory command signals (MRDC, AMWC,
MWTC). TRISTATEMEM is active HIGH.
ENABIO
0
ENABLE I/O: This signal is used as an enable control signal
for the I/O command signals (INTA, IORC, AIOWC, 10WC).
ENABIO is active HIGH.
ENABMEM
0
ENABLE MEMORY: This signal is used as an enable control
signal for the memory command signals (MRDC, AMWC
MWTC). ENABMEM is active HIGH.
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the SP8288 (see
table below). The SP8288 can operate in one of three modes:
user mode, active test mode, or inactive test mode.
Pin Name
TMODE
TSEL
Function
0_
0
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
1
1
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal equivalents, but are not used during normal user
operation. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
Intel
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
AENB
0.41
pF
CEN
0.30
pF
ClK
2.41
pF
lOB
0.06
pF
SOB,S1B,S2B
0.33
pF
TMODE
0.19
pF
TSEl
0.08
pF
A.C. Characteristics at 0-70°C, 5V + / - 10%
NOTE: A.C. Characteristics are given to the edge of the SP8288 core. Additional delays will apply in
connecting SP8288 signals to package pins through selected I/O buffer cells.
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Units
12.5
MHz
fc
ClK Frequency
TClCl
ClK Cycle Period
80.0
ns
TClCH
ClK low Time
46.0
ns
TCHCl
ClK High Time
26.0
ns
TSVCH
Status Active Setup Time
7.2
TCHSV
Status Inactive Hold Time
0
0
ns
TSHCl
Status Inactive Setup Time
2.8
9.5
ns
TClSH
Status Active Hold Time
-8.8
-1.2
ns
4-68
14.8
ns
SP8288
TIMING RESPONSES
Symbol
TCVNV
TCVNX
Parameter
Min.
Max.
Units
Control Active Delay -
DENS Read
2.1
8.7
ns
Control Active Delay -
DENS Write
2.3
9.8
ns
Control Active Delay -
PDEN Read
1.6
6.6
ns
Control Active Delay -
PDEN Write
1.9
7.6
ns
Control Inactive Delay -
DENS Read
2.4
8.1
ns
Control Inactive Delay -
DENS Write
2.4
7.6
ns
Control Inactive Delay -
PDEN Read
2.4
9.2
ns
Control Inactive Delay -
PDEN Write
2.4
8.7
ns
Control Inactive Delay -
MCES
1.1
5.4
ns
TCLLH
ALES Active Delay (from CLK)
0.7
3.8
ns
TCLMCH
MCES Active Delay (from CLK)
1.3
5.5
ns
TSVLH
ALES Active Delay (from Status)
0.7
3.8
ns
TSVMCH
MCES Active Delay (from Status)
1.5
6.6
ns
TCHLL
ALES Inactive Delay
1.2
3.7
ns
TCLML
Command Active Delay
1.0
3.9
ns
TCLMH
Command Inactive Delay
1.4
5.7
ns
TCHDTL
Direction Control Active Delay
1.4
4.7
ns
TCHDTH
Direction Control Inactive Delay
0.9
3.3
ns
TAELCH
Command Enable Time (Memory)
0.5
1.5
ns
Command Enable Time (I/O)
0.8
3.5
ns
Command Disable Time (Memory)
0.6
1.3
ns
Command Disable Time (I/O)
0.9
2.5
ns
Enable Delay Time (Memory)
148.0
175.0
ns
Enable Delay Time (I/O)
148.0
176.0
ns
0.6
3.2
ns
TAEHCZ
TAELCV
TAEVNV
AENS to DENS
4-69
inter
INTRODUCTION TO CELL-BASED DESIGN
TIMING RESPONSES (Cont'd.)
Symbol
TCEVNV
TCELRH
TCELRL
Parameter
Min.
Max.
Units
CEN to DENB
1.1
4.2
ns
CEN to PDEN
0.7
2.6
ns
CEN to Command Enable Active
(Memory)
0.9
2.5
ns
CEN to Command Enable Active (I/O)
1.2
3.2
ns
CEN to Command Enable Inactive
(Memory)
0.8
3.5
ns
CEN to Command Enable Inactive
(I/O)
0.8
3.9
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
AIOWC
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
ALEB
0.32
0.78
2.03
0.65
0.82
1.54
ns/pF
AMWC
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
DENB
0.32
0.78
2.03
0.65
0.82
1.54
ns/pF
DTRB
0.32
0.78
2.03
0.65
0.82
1.54
ns/pF
ENABIO
0.08
0.19
0.51
0.14
0.22
0.38
ns/pF
ENABMEM
0.08
0.19
0.51
0.14
0.22
0.38
ns/pF
INTA
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
IORC
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
IOWC
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
MRDC
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
MWTC
0.37
0.82
2.20
0.42
0.72
1.38
ns/pF
PDENMCEB
0.75
1.64
4.41
0.84
1.44
2.76
ns/pF
TRISTATEIO
0.08
0.19
0.51
0.14
0.22
0.38
ns/pF
TRISTATEMEM
0.08
0.19
0.51
0.14
0.22
0.38
ns/pF
Output Name
Units
inter
SP8288
STATE
ClK
_T.
T1
In
TCHSV-
r\
I
-
I-
TSVCH ~
I
n
r\
ADDRESSIDATA
TCLLH-
r-
I
'\
ALEB
r
ADDR
VALID
~ 1\
- -ym~
TCHCL----
\
r\
T.-
T3
f--TCLCH-
\
\
SOB,SlB,S2B
T2
-TCLCLR
WRITE
DATA VALID
j
v--\
TSHCL I -
'/
CD
~'CH"
TSVLH
@
-
MRDC,IORC,
INTA,AMWC,AIOWC
-
I
V
I'--TCLMH
\
1\
-
-TCLML
I-TCLML
V
MWTC,IOWC
\
J
"1\
(READ )
DENB (INTI. )
1\
I-- TCVNV
~
~
I--
TCVNX-
V
(READ )
PDEN (INTI.)
j
v
\
1\
-
TCVNV-
\
DENB(WRITE )
I
\
PDEN'(WRITE )
I
-------
TCHDTH-
(READ)
DTRB (INTA )
I-{
MCEB
TCLMCH-
)
-
~-
\
1---
-
-TSVMCH
f--- TCVNX
\
\
~
v
@
~
/
V
\
r\
TCHDTL
V
TCHDTH-
I-
I - TCVNX
NOTES:
1, Address/Data Bus is shown only for reference purposes,
2, leading edge of AlEB and MCEB is determined by the falling edge of ClK or Status going active, whichever occurs last.
G4020B
4-71
INTRODUCTION TO CELL-BASED DESIGN
ADDRESS ENABLE (AENB) TIMING (3·STATE ENABLE/DISABLE).
AENB
TAELCH
TAEHCZ
TRISTATEIO/MEM
ENABIO/MEM
TCELRL
CEN
DENB, PDEN Qualification Timing
G40208
Address Enable (AENB) Timing (3-State Enable/Disable)
G40208
CEN
AENB
DENB
PDEN
4-72
SP82284
SP82284 -
80286 CLOCK GENERATOR AND READY
INTERFACE
IRESB_
leLK
IFeB
SP82284
IEFI
IPeLKB
IRESETB
IREADY
IXTAL
Dl
Dl
Dl
a:J
-
c:
~
-
a:
!!l
>- Z >- Z
ewe
w
a: >- a: >ct c Ul c
Functional Pin Diagram
G40208
•
Cell Version of the 82C284 80286 Clock Generator and Ready Interface; Functional
Compatibility with the Standard Product Assured.
•
12.5 MHz Operation.
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
Generates System Clock for 80286 Family Microprocessors.
Uses a Crystal or an External Frequency Source.
Provides Local READY Synchronization.
•
•
•
Generates System Reset Output.
INTRODUCTION TO CELL-BASED DESIGN
SP82284 DESCRIPTION
The Intel SP82284 is a high performance, CHMOS cell version of the industry standard
82C84 80286 Clock Generator and Ready Interface. The SP82284 is a clock generator /
driver which provides clock signals for 80286 family microprocessors and support components. It also contains logic to supply READY to the CPU from either asynchronous or
synchronous sources and synchronous RESET from an asynchronous input. A specially
designed oscillator cell (POSC2) used in conjunction with the SP82284 provides for operation from an external crystal. An external frequency source may also be used.
The SP82284 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes the
SP82284 and design specific support logic.
For a complete functional description of the 82C284 architecture, refer to the "82C284
Clock Generator and Ready Interface for 80286 Processors" data sheet in the Intel
Microprocessor and Peripheral Handbook.
Pin Description
Pin Type
Function
IClK
0
SYSTEM CLOCK: The clock signal used by the processor and
support devices which must be synchronous with the processor. The frequency of the IClK output is twice the desired
internal processor clock frequency.
IClKFB
I
INTERNAL CLOCK: IClKFB is the IClK signal used internal
to the SP82284. This signal is equivalent to the off-chip system
clock (IClK) and must be connected to the output of the IClK
SP82284 I/O buffer companion cell (PCN04). This signal is
filtered in the SP82284 to eliminate any noise or ringing which
may be present on the clock output.
IFCB
I
FREQUENCY/CRYSTAL SELECT: Selects the source for the
IClK output. When IFCB is low, the IXTAl input drives IClK.
When IFCB is HIGH, the EFI input drives the IClK output.
IEFI
I
EXTERNAL FREQUENCY IN: Drives IClK when IFCB is HIGH.
The EFI input frequency must be twice the desired internal
processor clock frequency.
IXTAl
I
EXTERNAL CRYSTAL IN: IXTAl is the pin to which the output
of the SP82284 oscillator companion cell POSC2 is attached.
The crystal frequency must be twice the desired internal
processor clock frequency.
IPClKB
0
PERIPHERAL CLOCK: An output which provides a 50% duty
cycle clock with one-half the frequency of IClKFB. IPClKB
will be in phase with the internal processor clock following the
first bus cycle after the processor has been reset.
Pin Name
SP82284
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
IARDYENB
I
ASYNCHRONOUS READY ENABLE: An active LOW input
which qualifies the IARDYB input. IARDYENB selects IARDYB
as the source of ready for the current bus cycle. Inputs to
IARDYENB may be applied asynchronously to ICLKFB. Setup
and hold times are given to assure a guaranteed response to
synchronous inputs.
IARDYB
I
ASYNCHRONOUS READY: An active LOW input used to
terminate the current bus cycle. The IARDYB input is qualified
by IARDYENB. Inputs to IARDYB may be applied asynchronously to ICLKFB. Setup and hold times are given to assure
a guaranteed response to synchronous inputs.
ISRDYENB
I
SYNCHRONOUS READY ENABLE: An active LOW input
which qualifies ISRDYB. ISRDYENB selects ISRDYB as the
source for IREADY to the CPU for the current bus cycle. Setup
and hold times must be satisfied for proper operation.
ISRDYB
I
SYNCHRONOUS READY: An active LOW input used to terminate the current bus cycle. The ISRDYB input is qualified by
the ISRDYENB input. Setup and hold times must be satisfied
for proper operation.
IREADY
0
READY: An active HIGH output which signals the current bus
cycle is to be completed. The ISRDY, ISRDYENB, IARDYB,
IARDYENB, ISOB, IS1 B, and IRESB inputs controiIREADY.
ISOB
IS1B
I
STATUS: Inputs which prepare the SP82284 for a subsequent bus cycle. ISOB and IS1 B synchronize IPCLK to the
internal processor clock and controllREADY. Setup and hold
times must be satisfied for proper operation.
IRESETB
0
RESET: An active LOW output which is derived from the
IRESB input. IRESETB is used to force the system into an
initial state. When IRESETB is active, IREADY will be active
(HIGH).
IRESB
I
RESET IN: An active LOW input which generates the system
reset signal, IRESETB. Signals to IRESB may be applied
asynchronously to ICLKFB. Setup and hold times are given
to assure a guaranteed response to synchronous inputs.
Intel
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
IARDYB
0.08
pF
IARDYENB
O.OB
pF
IClKFB
1.03
pF
IEFI
0.15
pF
IFCB
0.15
pF
IRESB
0.05
pF
ISOB,IS1B
0.06
pF
ISRDYB
O.OB
pF
ISRDYENB
O.OB
pF
IXTAl
0.12
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
NOTE: A.C. Characteristics are given to the edge of the SPB2284 core. Additional delays will apply in
connecting SP82284 signals to package pins through selected 1/0 buffer cells.
TIMING PARAMETERS
Symbol
Parameter
Min.
Max.
Units
1a
IEFI HIGH to IClK lOW
0.6
1.5
ns
1b
IEFI lOW to IClK HIGH
0.2
0.9
ns
1c
IXTAl HIGH to IClK lOW
4.4
B.3
ns
1d
IXTAl lOW to IClK HIGH
O.B
4.0
ns
4
IClKFB Period
31.0
ns
5
IClKFB lOW Time
10.0
ns
6
IClKFB HIGH Time
10.0
ns
9
Status Setup Time
6.0
ns
10
Status Hold Time
1.0
ns
4-76
inter
SP82284
TIMING PARAMETERS (Cont'd.)
Symbol
Parameter
Min.
11a
ISRDYB or ISRDYENB Active
Setup Time
11b
Max.
Units
7.0
ns
ISRDYB or ISRDYENB
Inactive Setup Time
10.0
ns
12
ISRDYB or ISRDYENB
Hold Time
1.0
ns
13
IARDYB or IARDYENB
Setup Time
1.0
ns
14
IARDYB or IARDYENB
Hold Time
11.0
ns
15
IRESB Setup Time
0
ns
16
IRESB Hold Time
7.0
ns
17
IREADY Inactive Delay
6.4
16.4
ns
18
IREADY Active Delay
2.6
10.0
ns
19a
IPClKB Delay lOW
2.3
7.8
ns
19b
IPClKB Delay HIGH
2.4
9.5
ns
20a
IRESETB Delay lOW
7.2
11.3
ns
20b
IRESETB Delay HIGH
7.6
11.5
ns
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
IClK
0.31
0.71
1.92
0.52
0.82
1.54
ns/pF
IPClKB
0.08
0.13
0.31
0.10
0.13
0.21
ns/pF
IREADY
0.08
0.16
0.42
0.10
0.11
0.19
ns/pF
IRESETB
0.09
0.15
0.39
0.12
0.16
0.26
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
ICLK as a Function of IEFI and IXTAL
G40208
ICLKFB
IRESB
IREADY
NOTE:
1. This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown.
IRESETB and IREADY Timing as a Function of IRESB with ISOB, IS 1B,
IARDYB + IARDYENB, and ISRDYB + ISRDYENB High
4-78
G40208
inter
SP82284
IPelKB
ISRDYB-r-r~~~~~rr~~~~~~~~--~~~~~r-~~~~~~~~
+
ISRDYENB :......'--':....L...J.-'--'--'-+..J-.......J-"'-+'--'(..J
IARDYB~~~~~r-~~~~~--;-~~~~~~~
+
IARDYENB -J....J....J.-'--'--'-..J-+.J-J-I
IREADY
NOTES:
1. This is an aSY:1chronous input. The setup and hold times shown are required to
guarantee the response shown.
2. If ISRDYB + ISRDYENB or IARDYB + IARDYENB are active before and/or during
the first bus cycle after IRESETB. IREADY may not be de asserted until after the
falling edge of 02 of Ts.
IREADY and IPCLKB Timing with IRESB High
4-79
G40208
INTRODUCTION TO CELL-BASED DESIGN
SP82288 -
80286 BUS CONTROLLER
SOBTEST
S1BTEST
TRISTATE
ENABLE
CMDlYTEST
NOTREADYTEST
INTA
IORC
IOWC
SOBPAD
S1BPAD
MIOBPAD
SP82288
ClK
MRDC
MWTC
DTRB
AENCENPAD
DENB
CENlPAD
AlEB
CMDlYPAD
MCEB
NOTREADYPAD
MBPAD
w ....
c w
o
Vl
::Iii ....
....
Functional Pin Diagram
G40208
•
Cell Version of the 82288 80286 Bus Controller; Functional Compatibility with the
Standard Product Assured.
•
12.5 MHz Operation.
•
Tested and Verified Against Standard Product Test Programs, Providing a Guaranteed
0.1 % AQL or Better.
•
Provides Support for 80286 Family Microprocessors.
•
Provides Commands and Control for Local and System Buses.
•
Offers Wide Flexibility in System Configurations.
•
Flexible Command Timing.
•
Optional MULTIBUS Compatible Timing.
inter
SP82288
SP82288 DESCRIPTION
The Intel SP82288 is a high performance, CHMOS cell version of the industry standard
82288 80286 Bus Controller designed for use in 80286 microsystems. The SP82288 provides
command and control outputs with flexible timing options. Separate command outputs are
used for memory and I/0 devices. The data bus is controlled with separate data enable and
direction control signals.
The SP82288 can be used in conjunction with the Intel 1.5 Micron CHMOS III Cell Library,
allowing the designer to implement a semi-custom integrated circuit that includes the
SP82288 and design specific support logic.
For a complete functional description of the 82288 architecture, refer to the "82288 Bus
Controller for 80286 Processors" data sheet in the Intel Microprocessor and Peripheral
Handbook.
Pin Description
Pin Name
Pin
Type
Function
ClK
I
SYSTEM CLOCK: This signal provides the basic timing control
for the SP82288 in an 80286 microsystem. Its frequency is twice
the internal processor clock frequency. The falling edge of this
input signal establishes when inputs are sampled and command
and control outputs change.
SOBPAD,
S1BPAD,
SOBTEST,
S1BTEST
I
BUS CYCLE STATUS: These signals start a bus cycle and, along
with MIOBPAD, defines the type of bus cycle. These inputs are
active lOW. A bus cycle is started when either SOBPAD or
S1 BPAD is sampled lOW at the falling edge ClK. Setup and hold
times must be met for proper operation.
80286 Bus Cycle Status Definition
MIOBPAD
MIOBTEST
I
MIOBPAD
S1BPAD
SOB PAD
Type of Bus Cycle
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Interrupt
Acknowledge
I/O Read
I/O Write
None; Idle
Halt or Shutdown
Memory Read
Memory Write
None; Idle
MEMORY OR I/O SELECT: This signal determines whether the
current bus cycle is in the memory or I/O space. When lOW, the
current bus cycle is in the I/O space. Setup and hold times must
be met for proper operation.
4-81
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Name
Pin
Type
Function
MBPAD
MULTIBUS MODE SELECT: This signal determines timing of the
command and control outputs. When HIGH, the bus controller
operates with MULTIBUS compatible timings. When LOW, the bus
controller optimizes the control and command output timing for
short bus cycles. The function of the AENCENPAD input is
selected by this signal.
CENLPAD
COMMAND ENABLED LATCHED: This is a bus controller select
signal which enables the bus controller to respond to the current
bus cycle being initiated. CENLPAD is an active HIGH input latched internally at the end of each TS cycle. CENLPAD is used to select
the appropriate bus controller for each bus cycle in a system where
the CPU has more than one bus it can use. This input may be tied
HIGH to select this SP82288 for all transfers. No control inputs
affect CENLPAD. Setup and hold times must be met for proper
operation.
CMDLYPAD,
CMDLYTEST
COMMAND DELAY: This signal allows delaying the start of a
command. CMDLYPAD is an active HIGH input. If sampled HIGH,
the command output is not activated and CMDLYPAD is again
sampled at the next clock cycle. When sampled LOW the selected
command is enabled. If NOTREADYPAD is detected LOW before
the command output is activated, the SP82288 will terminate the
bus cycle, even if no command was issued. Setup and hold times
must be satisfied for proper operation. This input may be tied LOW
if no delays are required before starting a command. This input
has no effect on SP82288 control outputs.
NOTREADYPAD
NOTREADYTEST
READY: Indicates the end of the current bus cycle.
NOTREADYPAD is an active LOW input. MULTIBUS mode
requires at least one wait state to allow the command outputs to
become active. NOTREADYPAD must be LOW during reset, to
force the SP82288 into the idle state. Setup and hold times must
be met for proper operation.
AENCENPAD
COMMAND ENABLE/ADDRESS ENABLE: This signal controls the
command and DENB outputs of the bus controller. AENCENPAD
inputs may be asynchronous to CLK. Setup and hold times are
given to assure a guaranteed response to synchronous inputs.
When MBPAD is HIGH this pin has the AENB function. AENB is
an active LOW input which indicates that the CPU has been
granted use of a shared bus and the bus controller command
outputs may exit 3-state OFF and become inactive. AENB HIGH
indicates that the CPU does not have control of the shared bus
and forces the command outputs into 3-state OFF and DENB
inactive (LOW). AENB would normally be controlled by an 82289
bus arbiter which activates AENB when that arbiter owns the bus
to which the bus controller is attached. When MBPAD is LOW this
pin has the CEN function. CEN is an unlatched active HIGH input
which allows the bus controller to activate its command and DENB
outputs. With MBPAD LOW, CEN LOW forces the command and
DENB outputs inactive.
4-82
SP82288
Pin Description (Cont'd.)
Pin Name
Pin
Type
Function
ALEB
0
ADDRESS LATCH ENABLE: This signal controls the address
latches used to hold an address stable during a bus cycle. This
output is active LOW. ALEB will not be issued for the halt bus
cycle and is not affected by any of the control inputs.
MCEB
0
MASTER CASCADE ENABLE: This signals that a cascade address
from a master SP8259 interrupt controller may be placed onto the
CPU address bus for latching by the address latches ALEB control.
The CPU's address bus may then be used to broadcast the
cascade address to slave interrupt controllers so only one of them
will respond to the interrupt acknowledge cycle. This control output
is active LOW. MCEB is only active during interrupt acknowledge
cycles and is not affected by any control input.
DENB
0
DATA ENABLE: This signal controls when data transceivers
connected to the local data bus should be enabled. DENB is an
active LOW control output. DENB is delayed for write cycles in
the MULTIBUS mode.
DTRB
0
DATA TRANSMIT/RECEIVE: This signal establishes the direction
of data flow to or from the local data bus. When LOW, this control
output indicates that a write bus cycle is being performed. A HIGH
indicates a read bus cycle. DENB is always inactive when DTRB
changes state. DTRB is not affected by any of the control inputs.
10WC
0
I/O WRITE COMMAND: This signal instructs an I/O device to read
the data on the data bus. 10WC is an active HIGH command output.
The MBPAD and CMDLYPAD inputs control when this output
becomes active. NOTREADYPAD controls when it becomes
inactive.
10RC
0
I/O READ COMMAND: This signal instructs an I/O device to place
data onto the data bus. 10RC is an active HIGH command output.
The MBPAD and CMDL YPAD inputs control when this output
becomes active. NOTREADYPAD controls when it becomes
inactive.
MWTC
0
MEMORY WRITE COMMAND: This signal instructs a memory
device to read the data on the data bus. MWTC is an active HIGH
command output. The MBPAD and CMDLYPAD inputs control
when this output becomes active. NOTREADYPAD controls when
it becomes inactive.
4-83
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Name
Pin
Type
Function
MRDC
a
MEMORY READ COMMAND: This signal instructs a memory
device to place data onto the data bus. MRDC is an active HIGH
command output. The MBPAD and CMDLYPAD inputs control
when this output becomes active. NOTREADYPAD controls when
it becomes inactive.
INTA
a
INTERRUPT ACKNOWLEDGE: This signal tells an interrupting
device that its interrupt request is being acknowledged. INTA is
an active HIGH command output. The MBPAD and CMDLYPAD
inputs control when this output becomes active. NOTREADYPAD
controls when it becomes inactive.
ENABLE
a
ENABLE: This signal is used to enable ·the command output
signals. ENABLE is active HIGH.
TRISTATE
a
TRISTATE: This signal is used to 3-state the command output
signals. TRISTATE is active HIGH (when active, command outputs
enter a 3-state OFF state).
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the SP82288 (see table
below). The SP82288 can operate in one of three modes: user
mode, active test mode, or inactive test mode.
TMODE
TSEL
a
a
a
1
a
1
1
1
Function
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
NOTE: All signals xxxTEST and Txxx are test related input signals. All test related signals except for TMODE
and TSEL have a user signal equivalent and are listed with their non-test counterpart. These test
signals have the identical functionality as their user signal equivalents, but are not used during normal
user operation. All test signals must be accessible through a package pin. This can be accomplished
by tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to
any other user input signal that is directly connected to a package pin. One package pin for TMODE
and TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
4-84
inter
SP82288
Input Capacitance
Input Name
Max.
Units
AENCENPAD
0.18
pF
CENlPAD
0.22
pF
ClK
2.42
pF
CMDlYPAD
0.11
pF
MBPAD
0.49
pF
MIOBPAD
0.11
pF
NOTREADYPAD
0.11
pF
SOBPAD,S1BPAD
0.11
pF
TMODE
0.14
pF
TSEL
0.08
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
NOTE: A.C. Characteristics are given to the edge of the SP82288 core. Additional delays will apply in
connecting SP82288 signals to package pins through selected 1/0 buffer cells.
Parameter
Symbol
Min.
Max.
Units
1
ClK Period
50.0
ns
2
ClK HIGH Time
16.0
ns
3
ClK lOW Time
12.0
ns
6
MIOBPAD and Status Setup Time
9.0
ns
7
MIOBPAD and Status Hold Time
0
ns
8
CENlPAD Setup Time
15.0
ns
9
CENlPAD Hold Time
1.0
ns
10
NOTREADYPAD Setup Time
15.0
ns
11
NOTREADYPAD Hold Time
0
ns
12
CMDlYPAD Setup Time
15.0
ns
13
CMDlYPAD Hold Time
0
ns
4-85
INTRODUCTION TO CELL-BASED DESIGN
A.C. Characteristics at 0-70°C, 5V+/-10% (Cont'd.)
Symbol
Parameter
Min.
Max.
Units
10.0
ns
1.0
ns
14
AENB Setup Time
15
AENB Hold Time
16
ALEB, MCEB Active
Delay from ClK
0.9
4.4
ns
17
AlEB, MCEB Inactive
Delay from ClK
0.6
3.7
ns
18
DENB (Write) Inactive
from CENlPAD
2.8
10.5
ns
19
DTRB lOW from ClK
1.8
8.1
ns
20
DENB (Read) Active Delay
from DTRB (Note 1)
1.0
6.2
ns
21
DENB (Read) Inactive
Delay from ClK
2.8
10.5
ns
22
DTRB HIGH from DENB
Inactive (Note 1)
1.5
6.6
ns
23
DENB (Write) Active
Delay from ClK
2.3
9.7
ns
24
DENB (Write) Inactive
Delay from ClK
2.8
10.5
ns
25
DENB Inactive from CEN
2.1
6.7
ns
26
DENB Active from CEN
1.7
7.3
ns
27
DTRB HIGH from ClK
(when CEN = lOW)
1.9
7.4
ns
28
DENB Active from AENB
2.1
6.7
ns
29
Command Output Active
Delay from ClK
0.6
3.7
ns
30
Command Output Inactive
Delay from ClK
0.9
4.4
ns
31
ENABLE lOW from CEN
0.8
3.7
ns
32
ENABLE HIGH from CEN
1.5
4.3
ns
33
TRISTATE lOW from AENB
0.8
4.1
ns
4-86
SP82288
A.C. Characteristics at 0-70°C, 5V+ / -10% (Cont'd.)
Symbol
Parameter
Min.
Max.
Units
1.7
4.7
ns
34
TRISTATE HIGH from AENB
35
MBPAD Setup Time
13.0
ns
36
MBPAD Hold Time
1.0
ns
37
TRISTATE LOW from MBPAD
,j..
0.8
4.1
ns
38
TRISTATE HIGH from MBPAD t
1.7
4.7
ns
39
DENB Inactive from MBPAD t
2.1
6.7
ns
40
DEN Active from MBPAD t
1.7
7.3
ns
NOTES:
1. This specification does not conform to the corresponding standard product specification for overlap
between DTRB and DENB. This may, depending on the system design, cause bus contention.
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
ALEB
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
DENB
0.32
0.78
2.03
0.65
0.82
1.54
ns/pF
DTRB
0.32
0.78
2.03
0.65
0.82
1.54
ns/pF
ENABLE
0.08
0.19
0.51
0.14
0.22
0.38
ns/pF
INTA
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
IORC
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
IOWC
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
MCEB
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
MRDC
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
MWTC
0.39
0.73
2.02
0.51
0.86
1.54
ns/pF
TRISTATE
0.08
0.19
0.51
0.14
0.22
0.38
ns/pF
Output Name
4-87
Units
INTRODUCTION TO CELL-BASED DESIGN
ClK
MIOBPAD
50BPAD
51BPAD
-----+--.
AlEB
MCEB
STATUS, ALEB, MCEB Characteristics
G40208
CENLPAD, CMDL VPAD, DENB Characteristics with MBPAD
and CEN = 1 during Write Cycle
Read Cycle Characteristics with MBPAD
4-88
=
0 and CEN
=
= 0
G40208
1
G40208
InIeI
SP82288
CLK
SOBPADe
S1BPAD
DENB
CMDlYPAD
S\\\\\\\\\\(
CMD
NOTREADYPAD
CENlPAD
\\\\\\\\\Wi
7000104
Write Cycle Characteristics with MBPAD
=
0 and CEN
=
1
G4020a
ClK
CEN
DENB
ENABLE
DTRB
\\\\\\\\\\\\\170777001777
~"E
T10
NOTREADYPAD
CEN Characteristics with MBPAD
=
0
G4020a
INTRODUCTION TO CEll-BASED DESIGN
AENB Characteristics with MBPAD
= 1
G40208
ClK Characteristics
T8
Tc
Tc
G40208
Tc
T8
ClK
SOBPADe
SlBPAD
MBPAD
CMD
TRISTATE
DENB
NOTREADYPAD
MBPAD Characteristics with AENCENPAD
4-90
=
1
G40208
Intel
SP82288
Ta
Te
Ta
Te
Ti
Te
elK
SOBPADe
SIBPAD
MBPAD
MWTC
TRISTATE
DENB
NOTREADYPAD
NOTES:
1. MPBAD is an asynchronous input. MBPAD setup and hold times specified to guarantee the response shown.
2. If the setup time, T35, is met two clock cycles will occur before CMD becomes active
after the falling edge of MBPAD.
MBPAD Characteristics with AENCENPAD
4-91
1 (Cont'd.)
G40208
INTRODUCTION TO CELL-BASED DESIGN
POSC2 -
OSCILLATOR
PAD1
OSCOUT
Logic Table
Inputs
PAD2
Outputs
PAD1
PAD2
OSCOUT
0
1
1
0
0
1
POSC2 Description
Oscillator, Frequency Range to 37.5 MHz. This cell is used to provide the clock input to the
SP8284 and the SP82284 clock generator cells (ICLK) from an external crystal. In test
mode, the external tester clock is connected directly to PAD 1, with P AD2 left unconnected.
POSC2 is designed to function over the full range of operating frequencies of the SP8284
and SP82284.
Pin Description
PAD1
PAD2
OSCOUT
Oscillator Input
Oscillator Feedback Output
Clock Output
Input Capacitance
Input Name
Max.
Units
PAD1
4.11
pF
A.C. Characteristics at 0-70°C, SV+ / -10%
Intrinsic Propagation Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
PAD1 to OSCOUT
1.2
1.8
3.4
1.4
1.9
3.5
ns
PAD1 to PAD2
0.6
0.8
1.3
0.9
1.1
1.5
ns
Signal Path
Units
MICROPROCESSOR SUPPORT PERIPHERAL COMPANION CELLS
Load Dependent Delay
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
OSCOUT
0.30
0.70
1.80
0.60
0.80
1.40
ns/pF
PAD2
0.06
0.10
0.20
0.08
0.10
0.20
ns/pF
Output Name
Units
INTRODUCTION TO CELL-BASED DESIGN
PCN04 -
NON-INVERTING CMOS OUTPUT BUFFER
1 - - - PVDD
Logic Table
IN - - - - t - - i
Inputs
Outputs
IN
PAD
0
1
0
1
1 - - - PAD
1 - - - - PVSS
PCN04 Description
Non-Inverting CMOS Output Buffer, 15 rnA. This cell is used in conjunction with the SP8284 and SP82284 clock generator cells as a clock output
driver /buffer. The output signal PAD is also used as a feedback to the
SP82284 to provide the internal clock signal ICLKFB.
Function:
Pin Description
Data Input
Output
IN
PAD
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
4.0
Typ.
Max.
0.4
VOL
Input Capacitance
Input Name
Max.
Units
IN
0.21
pF
Units
Test Conditions
V
IOH
=
V
IOL
=
-6.6 rnA
15.0 rnA
MICROPROCESSOR SUPPORT PERIPHERAL COMPANION CELLS
A.C. Characteristics at 0-70°C, 5V+ / -10%
Intrinsic Propag,ation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
2.5
3.5
6.1
2.2
3.2
6.0
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.03
0.04
0.07
0.03
0.03
0.05
Units
ns/pF
InTel
INTRODUCTION TO CELL-BASED DESIGN
PC02 -
INVERTING CMOS OUTPUT BUFFER
Logic Table
IN
PAD
Inputs
Outputs
IN
PAD
0
1
1
0
PC02 Description
Function:
Inverting CMOS Output Buffer, 16 rnA. This cell is used in conjunction
with the SP8288 and SP82288 bus controller cells as a high drive CMOS
output buffer.
Pin Description
I
Data Input
IN
~____________P_A_D______________~_____________
O_ut_p_ut______________~ .
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
4.0
Typ.
Max.
0.4
VOL
Input Capacitance
Input Name
Max.
Units
IN
0.22
pF
Units
Test Conditions
V
IOH
= -2.8 rnA
V
IOL
=
16.0 rnA
MICROPROCESSOR SUPPORT PERIPHERAL COMPANION CELLS
A.C. Characteristics at 0-70°C, 5V + / - 10%
Intrinsic Propagation Delay
Signal Path
IN to PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
2.5
3.4
6.5
3.3
4.7
7.8
Units
ns
Load Dependent Delay
Output Name
PAD
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.03
0.04
0.10
0.07
0.06
0.07
Units
ns/pF
Intel
INTRODUCTION TO CELL-BASED DESIGN
PCOT6 -
3-STATE INVERTING CMOS OUTPUT BUFFER
Logic Table
ENP
Inputs
IN
Outputs
PAD
ENT
IN
ENP
X
X
X
a
1
a
1
1
ENT
PAD
1
Z
a
a
a
1
1
a
peOT6 Description
Function:
3-State Inverting CMOS Output Buffer with Enable, 42 rnA. This cell is
used in conjunction with the SP8288 and SP82288 bus controller cells as a
command output driver/buffer.
Pin Description
IN
ENP
ENT
PAD
Data Input
Gate Enable Input
3-State Enable Input
Output
D.C. Characteristics at 0-70°C, 5V+ / -10%
Parameter
Min.
VOH
4.0
Typ.
VOL
Max.
0.4
Input Capacitance
Input Name
Max.
Units
IN
0.35
pF
ENP
0.13
pF
ENT
0.38
pF
Units
Test Conditions
V
IOH
=
V
IOL
=
-8.0 rnA
42.0 rnA
Intel
MICROPROCESSOR SUPPORT PERIPHERAL COMPANION CELLS
3-State Output Capacitance
Output Name
Max.
Units
PAD(z)
12.7
pF
A.C. Characteristics at 0-70°C, SV + / - 10%
Intrinsic Propagation Delay
Parameter
Signal Path
Min.
Typ.
Max.
Units
Tplh
IN to PAD
4.6
6.0
10.7
ns
Tphl
IN to PAD
6.3
7.5
11.7
ns
Tplh
ENP to PAD
5.3
7.6
14.6
ns
Tphl
ENP to PAD
6.7
8.5
14.5
ns
Tpzh
ENTto PAD
4.6
6.0
10.7
ns
Tpzl
ENTto PAD
6.3
7.5
11.7
ns
Tphz
ENTto PAD
6.3
7.5
11.7
ns
Tplz
ENTto PAD
4.6
6.0
10.7
ns
Load Dependent Delay
Parameter
Output Name
Min.
Typ.
Max.
Units
Tplh
PAD
0.01
0.02
0.04
ns/pF
Tphl
PAD
0.02
0.02
0.03
ns/pF
InIeI
RAM64 -
INTRODUCTION TO CELL-BASED DESIGN'
64 X 8 STATIC RANDOM ACCESS MEMORY
AO
DBO
Al
DBl
A2
DB2
A3
A4
DB4
AS-
DBS
DB6
DB7
RAM64
DBCTL
RAMWRL_
TRAMWRL
LBYTADD
RAMSELL
TLBYTADD
TRAMSELL
RAMRDL
TRAMRDL
TMODE_
RAM64 Description
Function:
TSEL-
64 X 8 Static Random Access Memory (SRAM).
Pin Description
Pin Name
Pin Type
Function
AO-5
I
AO-5 are address inputs to the RAM cell. AO-5 can be configured
as either latched or unlatched address inputs via the LBYTADD
input signal (see LBYTADD, LBYTDAT description). These lines
are not used when the RAM is configured with common, mUltiplexed address/data lines.
RAMWRL,
TRAMWRL
I
WRITE: RAMWRL is an active LOW write enable input. When the
RAM cell is selected (RAMS ELL LOW) and RAMRDL is HIGH, a
LOW on RAMWRL will enable the data inputs. The data present
on DBO-7 will be written into the addressed RAM location.
RAMRDL,
TRAMRDL
I
READ: RAMRDL is an active LOW read enable input. When the
RAM cell is selected (RAMS ELL LOW) and RAMWRL is HIGH, a
LOW on RAMRDL will enable the data outputs. The contents of
the addressed RAM location will be presented on DBO-7.
RAMSELL,
TRAMSELL
I
RAM SELECT: RAMSELL is an active LOW RAM cell select input.
RAMSELL must be active during all RAM operations. When
RAMSELL is HIGH, DBO-7 will be in a high impedance state.
I/O
DATA: DBO-7 are bidirectional, 3-state data lines. During a write
operation, DBO-7 are data inputs to the RAM. During a read
operation, DBO-7 are data outputs from the RAM.
DBO-7 outputs will remain in a high impedance state except during
a read operation (RAMS ELL, RAMRDL LOW). DBO-7 can also
serve as a multiplexed address/data bus. In this configuration,
the DBO-7 lines first present the valid address inputs to the RAM.
After the address is latched internally (see LBYTADD, LBYTDAT
description), DBO-7 acts as the RAM data bus operating as
described above.
DBO-7
4-100
FIXED CONFIGURATION RAM
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
LBYTADD,
LBYTDAT,
TLBYTADD,
TLBYTDAT
I
ADDRESS BUS CONTROL: LBYTADD and LBYTDAT are inputs
which together determine the source of RAM address inputs and
control the internal latching of the address lines (see table below).
AO-5 will drive the internal address lines if LBYTDAT is tied LOW.
In this configuration, the internal address lines will match AO-5
when LBYTADD is HIGH. Latching of the address inputs is
accomplished by toggling LBYTADD LOW. D80-5 will drive the
internal address lines if LBYTADD is tied LOW. In this configuration, the internal address lines will match DBO-5 when LBYTDAT
is HIGH. When LBYTDAT is taken LOW, the address inputs are
latched and valid data may be presented on D80-7.
LBYTADD
LBYTDAT
0
0
0
1
0
1
1
1
Internal Address Lines
Address Latched
Driven by DBO-5
Driven by AO-5
Invalid State
DBCTL
0
DATA BUS CONTROL: The Data Bus Control signal is used for
data bus transceiver control. When this signal is high, DBO-7 are
being driven by the RAM cell.
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the RAM cell (see table
below). The RAM cell can operate in one of three modes: user
mode, active test mode, or inactive test mode.
TMODE
0
0
TSEL
Function
0
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
1
0
1
1
1
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal equivalents, but are not used during normal user
operation. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
4-101
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
AO-5
0.15
pF
DBO-7
1.30
pF
LBYTADD
0.10
pF
LBYTDAT
0.10
pF
RAMRDL
0.15
pF
RAMSELL
0.15
pF
RAMWRL
0.15
pF
3-State Output Capacitance
Output Name
Max.
Units
DBO-7(z)
1.30
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
WRITE CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Write Cycle Time
20.0
33.0
72.0
ns
TELEH
RAMSELL Pulse Width
12.0
20.0
43.0
ns
TEHEL
RAMSELL HIGH Time
8.0
13.0
29.0
ns
TAVEL
Address Setup Time
0
0
0
ns
TELAX
Address Hold after RAMWRL HIGH
3.0
4.0
6.0
ns
TWLEL
RAMWRL LOW to Next RAMSELL LOW
20.0
33.0
72.0
ns
TWLWH
RAMWRL Pulse Width
12.0
20.0
43.0
ns
TDVWL
Data Setup to RAMWRL LOW
0
0
0
ns
TWLDX
Data Hold after RAMWRL HIGH
5.0
7.0
12.0
ns
TELWL
RAMS ELL LOW to RAMWRL LOW
0
0
0
ns
TWLEH
RAMWRL LOW to RAMSELL HIGH
12.0
20.0
43.0
ns
TWHEL
RAMWRL HIGH to Next RAMSELL LOW
8.0
13.0
29.0
ns
inter
FIXED CONFIGURATION RAM
READ CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Read Cycle Time
19.0
34.0
74.0
ns
TELQV
Access Time From RAMSELL
12.0
21.0
45.0
ns
TGLQV
Access Time From RAMRDL
12.0
21.0
45.0
ns
TELEH
RAMSELL Pulse Width
12.0
21.0
45.0
ns
TEHEL
RAMSELL HIGH Time
8.0
13.0
30.0
ns
TAVEL
Address Setup Time
5.0
6.0
10.0
ns
TELAX
Address Hold after RAMWRL HIGH
0
0
0
ns
TGLEL
RAMRDL LOW to Next RAMSELL LOW
19.0
34.0
74.0
ns
TGHEL
RAMRDL HIGH to Next RAMSELL LOW
8.0
13.0
29.0
ns
TGHQX
RAMRDLjRAMSELL HIGH to Data Float
5.0
8.0
15.0
ns
TELGL
RAMSELL LOW to RAMRDL LOW
0
0
0
ns
TGLEH
RAMRDL LOW to RAMSELL HIGH
12.0
21.0
45.0
ns
TSRLCH
RAMRDLjRAMSELL LOW to DBCTL HIGH
5.0
8.0
16.0
ns
TSRHCL
RAMRDLjRAMSELL HIGH to DBCTL LOW
5.0
8.0
16.0
ns
Load Dependent Delay
Output Name
DBO-7
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.75
1.50
3.20
0.75
0.90
1.50
Units
nsjpF
INTRODUCTION TO CELL-BASED DESIGN
t+---------TELEL--------~
t+-----TELEH----+-I
RAMSELL
RAMWRL
TAVEL
TDVWL
-lI
_DA_T_A______________
TWLDX
II-
TELA X l
~(r--------------~)~-------------------
Write Cycle
G40208
t+--------TELEL,-------~
Read Cycle
4-104
G40208
FIXED CONFIGURATION RAM
RAM 128 -
128 X 8 STATIC RANDOM ACCESS MEMORY
AO_
DBO
Al
OBI
A2
DB2
A3
DB3
A4
DB4
AS-
DBS
A6-
DB6
DB7
RAM128
RAMWRL_
DBCTL
LBYTDAT
TRAMWRL
LBYTADD
RAMSELL
TLBYTADD
TRAMSELL
RAMRDL
TRAMRDL
TMODE
RAM 128 Description
Function:
TSEL
128 X 8 Static Random Access Memory (SRAM).
Pin Description
Pin Name
Pin Type
Function
AO-6
I
ADDRESS: AO-6 are address inputs to the RAM cell. AO-6 can be
configured as either latched or unlatched address inputs via the
LBYTADD input signal (see LBYTADD, LBYTDAT description).
These lines are not used when the RAM is configured with
common, multiplexed address/data lines.
RAMWRL,
TRAMWRL
I
WRITE: RAMWRL is an active LOW write enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMRDL is HIGH, a
LOW on RAMWRL will enable the data inputs. The data present
on DBO-7 will be written into the addressed RAM location.
RAMRDL,
TRAMRDL
I
READ: RAMRDL is an active LOW read enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMWRL is HIGH, a
LOW on RAMRDL will enable the data outpu"ts. The contents of
the addressed RAM location will be presented on DBO-7.
RAMS ELL,
TRAMSELL
I
RAM SELECT: RAMSELL is an active LOW RAM cell select input.
RAMSELL must be active during all RAM operations. When
RAMSELL is HIGH, DBO-7 will be in a high impedance state.
I/O
DATA: DBO-7 are bidirectional, 3-state data lines. During a write
operation, DBO-7 are data inputs to the RAM. During a read
operation, DBO-7 are data outputs from the RAM.
DBO-7 will remain in a high impedance state except during a read
operation (RAMS ELL, RAMRDL LOW). DBO-7 can also serve as
a multiplexed address/data bus. In this configuration, the DBO-7
lines first present the valid address inputs to the RAM. After the
address is latched internally (see LBYTADD, LBYTDAT description), DBO-7 acts as the RAM data bus operating as described
above.
DBO-7
4-105
inter
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
LBYTADD,
LBYTDAT,
TLBYTADD,
TLBYTDAT
I
ADDRESS BUS CONTROL: LBYTADD and LBYTDAT are inputs
which together determine the source of RAM address inputs and
control the internal latching of the address lines (see table below).
AO-6 will drive the internal address lines if LBYTDAT is tied LOW.
In this configuration, the internal address lines will match AO-6
when LYTADD is HIGH. Latching of the address inputs is accomplished by toggling LBYTADD LOW. DBO-6 will drive the internal
address lines if LBYTADD is tied LOW. In this configuration, the
internal address lines will match DBO-6 when LBYTDAT is HIGH.
When LBYTDAT is taken LOW, the address inputs are latched
and valid data may be presented on DBO-7.
Cl
LBYTADD
LBYTDAT
0
0
1
1
0
1
0
1
Internal Address Lines
Address Latched
Driven by DBO-6
Driven by AO-6
Invalid State
DBCTL
0
DATA BUS CONTROL: The Data Bus Control signal is used for
data bus transceiver control. When this signal is high, DBO-7 are
being driven by the RAM cell.
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the RAM cell (see table
below). The RAM cell can operate in one of three modes: user
mode, active test mode, or inactive test mode.
TMODE
TSEL
Function
0
0
1
1
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have the
identical functionality as their user signal equivalents, but are not used during normal user operation. All
test signals must be accessible through a package pin. This can be accomplished by tying the test signal
to its user signal equivalent if it is directly connected to a package pin, or to any other user input signal that
is directly connected to a package pin. One package pin for TMODE and TSEL is required per device,
regardless of the number of cells implemented which require these inputs. Additional test logic will be
necessary for TSEL generation to multiple cells.
4-106
inter
FIXED CONFIGURATION RAM
Input Capacitance
Input Name
Max.
Units
AO-6
0.30
pF
DBO-7
1.40
pF
LBYTADD
0.10
pF
LBYTDAT
0.10
pF
RAMRDL
0.30
pF
RAMSELL
0.30
pF
RAMWRL
0.30
pF
3-State Output Capacitance
Output Name
Max.
Units
DBO-7(z)
1.40
pF
A.C. Characteristics at 0-70°C, SV+ / -10%
WRITE CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Write Cycle Time
20.0
33.0
73.0
ns
TELEH
RAMS ELL Pulse Width
12.0
20.0
43.0
ns
TEHEL
RAMSELL HIGH Time
8.0
13.0
30.0
ns
TAVEL
Address Setup Time
0
0
0
ns
TELAX
Address Hold after RAMWRL HIGH
3.0
4.0
6.0
ns
TWLEL
RAMWRL LOW to Next RAMS ELL LOW
20.0
33.0
73.0
ns
TWLWH
RAMWRL Pulse Width
12.0
20.0
43.0
ns
TDVWL
Data Setup to RAMWRL LOW
0
0
0
ns
TWLDX
Data Hold after RAMWRL HIGH
5.0
7.0
12.0
ns
TELWL
RAMSELL LOW to RAMWRL LOW
0
0
0
ns
TWLEH
RAMWRL LOW to RAMS ELL HIGH
12.0
20.0
43.0
ns
TWHEL
RAMWRL HIGH to Next RAMSELL LOW
8.0
13.0
30.0
ns
inter
INTRODUCTION TO CELL-BASED DESIGN
READ CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Read Cycle Time
20.0
35.0
76.0
ns
TELQV
Access Time From RAMS ELL
12.0
22.0
46.0
ns
TGLQV
Access Time From RAMRDL
12.0
22.0
46.0
ns
TELEH
RAMS ELL Pulse Width
12.0
22.0
46.0
ns
TEHEL
RAMSELL HIGH Time
8.0
13.0
30.0
ns
TAVEL
Address Setup Time
5.0
6.0
10.0
ns
TELAX
Address Hold after RAMWRL HIGH
0
0
0
ns
TGLEL
RAMRDL LOW to Next RAMS ELL LOW
20.0
35.0
76.0
ns
TGHEL
RAMRDL HIGH to Next RAMSELL LOW
8.0
13.0
30.0
ns
TGHQX
RAMRDL/RAMSELL HIGH to Data Float
5.0
8.0
15.0
ns
TELGL
RAMS ELL LOW to RAMRDL LOW
0
0
0
ns
TGLEH
RAMRDL LOW to RAMSELL HIGH
12.0
22.0
46.0
ns
TSRLCH
RAMRDL/RAMSELL LOW to DBCTL HIGH
5.0
8.0
16.0
ns
TSRHCL
RAMRDL/RAMSELL HIGH to DBCTL LOW
5.0 .
8.0
16.0
ns
Load Dependent Delay
Output Name
DBO-7
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.75
1.50
3.20
0.75
0.90
1.50
Units
ns/pF
FIXED CONFIGURATION RAM
I+---------TELEL-------~~
~----TELEH---~
RAMSELL
_
....--TWLEH
RAMWRL
TAVEL
TOVWL-l
TWLDX
_DA_T_A______________~(~--------------~~-------------------
Write Cycle
G40208
~-------TELEL-------__.j
Read Cycle
4-109
G40208
INTRODUCTION TO CELL-BASED DESIGN
RAM256 -
256 X 8 STATIC RANDOM ACCESS MEMORY
AO
OBO
Al
OBI
A2
OB2
A3
OB3
A4
OB4
OB5
OB6
OB7
A7
RAM256
OBCTL
LBYTOAT
TLBYTOAT
TRAMWRL
LBYTAOO
RAMSELL
TLBYTAOO
TRAMSELL
RAMROL
TRAMROL
TMOOE
RA~256
Description
Function:
TSEL
256 X 8 Static Random Access Memory (SRAM).
Pin Description
Pin Type
Function
AO-7
I
ADDRESS: AO-7 are address inputs to the RAM cell. AO-7 can be
configured as either latched or unlatched address inputs via the
LBYTADD input signal (see LBYTADD, LBYTDAT description).
These lines are not used when the RAM is configured with
common, multiplexed address/data lines.
RAMWRL,
TRAMWRL
I
WRITE: RAMWRL is an active LOW write enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMRDL is HIGH, a
LOW on RAMWRL will enable the data inputs. The data present
on DBO-7 will be written into the addressed RAM location.
RAMRDL,
TRAMRDL
I
READ: RAMRDL is an active LOW read enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMWRL is HIGH, a
LOW on RAMRDL will enable the data outputs. The contents of
the addressed RAM location will be presented on DBO-7.
RAMSELL,
TRAMSELL
I
RAM SELECT: RAMS ELL is an active LOW RAM cell select input.
RAMSELL must be active during all RAM operations. When
RAMSELL is HIGH, DBO-7 will be in a high impedance state.
I/O
DATA: DBO-7 are bidirectional, 3-state data lines. During a write
operation, DBO-7 are data inputs to the RAM. During a read
operation, DBO-7 are data outputs from the RAM.
DBO-7 will remain in a high impedance state except during a read
operation (RAMSELL, RAMRDL LOW). DBO-7 can also serve as
a multiplexed address/data bus. In this configuration, the. DBO-7
lines first present the valid address inputs to the RAM. After the
address is latched internally (see LBYTADD, LBYTDAT description), DBO-7 acts as the RAM data bus operating as described
above.
Pin Name
DBO-7
4-110
inter
FIXED CONFIGURATION RAM
Pin Description (Cont'd.)
Pin Name
Pin Type
Function
LBYTADD,
LBYTDAT
TLBYTADD,
TLBYTDAT
I
ADDRESS BUS CONTROL: LBYTADD and LBYTDAT are inputs
which together determine the source of RAM address inputs and
control the internal latching of the address lines (see table below).
AO-7 will drive the internal address lines if LBYTDAT is tied LOW.
In this configuration, the internal address lines will match AO-7
when LBYTADD is HIGH. Latching of the address inputs is
accompllished by toggling LBYTADD LOW. OBO-7 will drive the
internal address lines if LBYTADD is tied LOW. In this configuration, the internal address lines will match DBO-7 when LBYTDAT
is HIGH. When LBYTDAT is taken LOW, the address inputs are
latched and valild data may be presented on OBO-7.
LBYTADD
LBYTDAT
0
0
0
1
1
0
1
1
Internal Address Lines
Address Latched
Driven by OBO-7
Driven by AO-7
Invalid State
DBCTL
a
DATA BUS CONTROL: The Data Bus Control signal is used for
data bus transceiver control. When this signal is high, DBO-7 are
being driven by the RAM cell.
TMODE,
TSEL
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the RAM cell (see table
below). The RAM cell can operate in one of three modes: user
mode, active test mode, or inactive test mode.
TMODE
TSEL
Function
0
0
0
1
1
0
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
1
1
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal eqUivalents, but are not used during normal user
operation. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
4-111
INTRODUCTION TO CELL-BASED DESIGN
Input Capacitance
Input Name
Max.
Units
AO-7
0.45
pF
DBO-7
1.50
pF
LBYTADD
0.10
pF
LBYTDAT
0.10
pF
RAMRDL
0.45
pF
RAMSELL
0.45
pF
RAMWRL
0.45
pF
3-State Output Capacitance
Output Name
Max.
Units
DBO-7(z)
1.50
pF
A.C. Characteristics at 0-70°C, 5V+ / -10%
WRITE CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Write Cycle Time
21.0
35.0
77.0
ns
TELEH
RAMSELL Pulse Width
12.0
19.0
43.0
ns
TEHEL
RAMSELL HIGH Time
9.0
16.0
34.0
ns
TAVEL
Address Setup Time
0
0
0
ns
TELAX
Address Hold after RAMWRL HIGH
3.0
4.0
6.0
ns
TWLEL
RAMWRL LOW to Next RAMSELL LOW
21.0
35.0
77.0
ns
TWLWH
RAMWRL Pulse Width
12.0
19.0
43.0
ns
TDVWL
Data Setup to RAMWRL LOW
0
0
0
ns
TWLDX
Data Hold after RAMWRL HIGH
5.0
7.0
12.0
ns
TELWL
RAMS ELL LOW to RAMWRL LOW
0
0
0
ns
TWLEH
RAMWRL LOW to RAMSELL HIGH
12.0
19.0
43.0
ns
TWHEL
RAMWRL HIGH to Next RAMSELL LOW
9.0
16.0
34.0
ns
inter
FIXED CONFIGURATION RAM
READ CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Read Cycle Time
23.0
42.0
86.0
ns
TELOV
Access Time From RAMSELL
14.0
26.0
52.0
ns
TGLOV
Access Time From RAMRDL
14.0
26.0
52.0
ns
TELEH
RAMS ELL Pulse Width
14.0
. 26.0
52.0
ns
TEHEL
RAMSELL HIGH Time
9.0
16.0
34.0
ns
TAVEL
Address Setup Time
5.0
6.0
11.0
ns
TELAX
Address Hold after RAMWRL HIGH
0
0
0
ns
TGLEL
RAMRDL LOW to Next RAMSELL LOW
23.0
42.0
86.0
ns
TGHEL
RAMRDL HIGH to Next RAMSELL LOW
9.0
16.0
34.0
ns
TGHOX
RAMRDL/RAMSELL HIGH to Data Float
5.0
8.0
15.0
ns
TELGL
RAMSELL LOW to RAMRDL LOW
0
0
0
ns
TGLEH
RAMRDL LOW to RAMSELL HIGH
14.0
26.0
52.0
ns
TSRLCH
RAMRDL/RAMSELL LOW to DBCTL HIGH
5.0
8.0
16.0
ns
TSRHCL
RAMRDL/RAMSELL HIGH to DBCTL LOW
5.0
8.0
16.0
ns
Load Dependent Delay
Output Name
DBO-7
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.75
1.50
3.20
0.75
0.90
1.50
Units
ns/pF
inter
INTRODUCTION TO CELL-BASED DESIGN
TELEL
TELEH
. RAMSELL
TWLEH
RAMWRL
TAVEL
TDVWL-l
DATA
f-
TWLDX
~~Xl
)
<
Write Cycle
G40208
TELEL
Read Cycle
4-114
G40208
Intel
RAM512 -
FIXED CONFIGURATION RAM
512 X 8 STATIC RANDOM ACCESS MEMORY
AO
DBO
Al
OBI
A2
DB2
A3
DB3
A4
DB4
AS
DBS
A6
DB6
A7
DB7
AS
RAM512
DBCTL
LBYTDAT
TRAMWRL
TLBYTDAT
RAMSELL
LBYTADD
TLBYTADD
TRAMSELL
HBYTDAT
RAMRDL
TRAMRDL
THBYTDAT
TMODE
THBYTADD
HBYTADD
RAM512 Description
Function:
TSEL
512 X 8 Static Random Access Memory (SRAM).
Pin Description
Pin Type
Function
AO-8
I
ADDRESS: AO-8 are address inputs to the RAM cell. AO-8 can be
configured as either latched or unlatched address inputs via the
LBYTADD and HBYTADD input signals (see LBYTADD, LBYTDAT,
HBYTADD, HBYTDAT description). These lines are not used when
the RAM is configured with common, multiplexed address/data
lines.
RAMWRL,
TRAMWRL
I
WRITE: RAMWRL is an active LOW write enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMRDL is HIGH, a
LOW on RAMWRL will enable the data inputs. The data present
on DBO-7 will be written into the addressed RAM location.
RAMRDL,
TRAMRDL
I
READ: RAMRDL is an active LOW read enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMWRL is HIGH, a
LOW on RAMRDL will enable the data outputs. The contents of
the addressed RAM location will be presented on DBO-7.
RAMSELL,
TRAMSELL
I
RAM SELECT: RAMSELL is an active LOW RAM cell select input.
RAMS ELL must be active during all RAM operations. When
RAMSELL is HIGH, OBO-7 will be in a high impedance state.
Pin Name
4-115
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Name
OBO-7
Pin Type
Function
I/O
OATA: OBO-7 are bidirectional, 3-state data lines. During a write
operation, OBO-7 are data inputs to the RAM. During a read
operation, DBO-7 are data outputs from the RAM.
DBO-7 will remain in a high impedance state except during a read
operation (RAMSELL, RAMRDL LOW). OBO-7 can also serve as
a multiplexed address/data bus. In this configuration, the DBO-7
lines first present the valid address inputs to the RAM. After the
address is latched internally (see LBYTADD, LBYTOAT,
HBYTADD, HBYTDAT description), DBO-7 acts as the RAM data
bus operating as described above.
LBYTADO,
LBYTDAT,
HBYTAOD,
HBYTOAT,
TLBYTADD,
TLBYTDAT,
THBYTADD,
THBYTOAT
ADDRESS BUS CONTROL: LBYTADD, LBYTDAT, HBYTADD, and
HBYTDAT are inputs which together determine the source of RAM
address inputs and control the internal latching of the address
lines (see table below). AO-8 will drive the internal address lines if
LBYTDAT and HBYTDAT are tied LOW. In this configuration, the
internal address lines will match AO-8 when LBYTADO and
HBYTADD are HIGH. Latching of the address inputs is accomplished by toggling LBYTADD and HBYTADD LOW. DBO-7 will
drive the internal address lines if LBYTADD and HBYTADD are
tied LOW. In this configuration, the internal address lines AO-8 are
latched from OBO-7 in two stages. First, AO-7 is driven by OBO-7
when LBYTDAT is HIGH and HBYTDAT is LOW and is latched by
toggling LBYTDAT LOW. Next, HBYTDAT is taken high to allow
the data on DBO to appear on address bit A8. These address bits
are latched by toggling HBYTDAT LOW. When LBYTDAT and
HBYTDAT are LOW and the valid address has been latched in,
valid data may be presented on OBO-7.
LBYTADD
LBYTDAT
0
0
0
1
0
1
1
1
HBYTADD
HBYTDAT
0
0
0
1
0
1
1
DBCTL
a
1
Internal Address Lines
Address Latched
Driven by DBO-7 (AO-7)
Driven by AO-8
Invalid State
Internal Address Lines
Address Latched
Driven by DBO (A8)
Driven by AO-8
Invalid State
DATA BUS CONTROL: The Data Bus Control signal is used for
data bus transceiver control. When this signal is high, DBO-7 are
being driven by the RAM cell.
4-116
FIXED CONFIGURATION RAM
Pin Description (Cont'd.)
Pin Name
TMODE,
TSEL
Pin Type
Function
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the RAM cell (see table
below). The RAM cell can operate in one of three modes: user
mode, active test mode, or inactive test mode.
TMODE
TSEL
Function
0
0
1
1
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal equivalents, but are not used during normal user
operation. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
Input Capacitance
Input Name
Max.
Units
AO-8
0.60
pF
DBO-7
1.60
pF
HBYTADD
0.10
pF
HBYTDAT
0.10
pF
LBYTADD
0.10
pF
LBYTDAT
0.10
pF
RAMRDL
0.60
pF
RAMSELL
0.60
pF
RAMWRL
0.60
pF
4-117
inter
INTRODUCTION TO CELL-BASED DESIGN
3-State Output Capacitance
Output Name
Max.
Units
DBO·7(z)
1.60
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
WRITE CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Write Cycle Time
23.0
37.0
81.0
ns
TELEH
RAMS ELL Pulse Width
12.0
20.0
43.0
ns
TEHEL
RAMSELL HIGH Time
11.0
17.0
38.0
ns
TAVEL
Address Setup Time
0
0
0
ns
TELAX
Address Hold after RAMWRL HIGH
3.0
4.0
6.0
ns
TWLEL
RAMWRL LOW to Next RAMSELL LOW
23.0
37.0
81.0
ns
TWLWH
RAMWRL Pulse Width
12.0
20.0
43.0
ns
TDVWL
Data Setup to RAMWRL LOW
0
0
0
ns
TWLDX
Data Hold after RAMWRL HIGH
5.0
7.0
12.0
ns
TELWL
RAMS ELL LOW to RAMWRL LOW
0
0
0
ns
TWLEH
RAMWRL LOW to RAMSELL HIGH
12.0
20.0
43.0
ns
TWHEL
RAMWRL HIGH to Next RAMSELL LOW
11.0
17.0
38.0
ns
FIXED CONFIGURATION RAM
READ CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Read Cycle Time
26.0
47.0
95.0
ns
TELQV
Access Time From RAMSELL
15.0
30.0
57.0
ns
TGLQV
Access Time From RAMRDL
15.0
30.0
57.0
ns
TELEH
RAMSELL Pulse Width
15.0
30.0
57.0
ns
TEHEL
RAMSELL HIGH Time
11.0
17.0
38.0
ns
TAVEL
Address Setup Time
5.0
7.0
11.0
ns
TELAX
Address Hold after RAMWRL HIGH
0
0
0
ns
TGLEL
RAMRDL LOW to Next RAMSELL LOW
26.0
47.0
95.0
ns
TGHEL
RAMRDL HIGH to Next RAMSELL LOW
11.0
17.0
38.0
ns
TGHQX
RAMRDLjRAMSELL HIGH to Data Float
5.0
8.0
15.0
ns
TELGL
RAMSELL LOW to RAMRDL LOW
0
0
0
ns
TGLEH
RAMRDL LOW to RAMSELL HIGH
15.0
30.0
57.0
ns
TSRLCH
RAMRDLjRAMSELL LOW to DBCTL HIGH
5.0
8.0
16.0
ns
TSRHCL
RAMRDLjRAMSELL HIGH to DBCTL LOW
5.0
8.0
16.0
ns
Load Dependent Delay
Output Name
DBO-7
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.75
1.50
3.20
0.75
0.90
1.50
Units
nsjpF
INTRODUCTION TO CELL-BASED DESIGN
I.-----.,-----TELEL--------~
~-----TELEH----+-l
RAMSELL
_~--TWLEH
RAMWRL
TAVEL
TDVWL-l
TWLDX
_DA_T_A_____________~(~--------------~r-------------------
Write Cycle
G40208
..--------TELEL-------~
Read Cycle
4-120
G40208
InTel
RAM 1K -
FIXED CONFIGURATION RAM
1024 X 8 STATIC RANDOM ACCESS MEMORY
AO
DBO
Al
DBl
A2
DB2
A4
DB4
AS
DBS
A7
DB7
A9
RAM1K
RAMWRL
DBCTL
LBYTDAT
TRAMWRL
LBYTADD
RAMSELL
TLBYTADD
TRAMSELL
RAMRDL
HBYTDAT
TRAMRDL
THBYTDAT
TMODE
THBYTADD
HBYTADD
RAM 1K Description
Function:
TSEL
1024 X 8 Static Random Access Memory (SRAM).
Pin Description
Pin Type
Function
AO-9
I
ADDRESS: AO-9 are address inputs to the RAM cell. AO-9 can be
configured as either latched or unlatched address inputs via the
LBYTADD and HBYTADD input signals (see LBYTADD, LBYTDAT,
HBYTADD, HBYTDAT description). These lines are not used when
the RAM is configured with common, multiplexed address/data
lines.
RAMWRL,
TRAMWRL
I
WRITE: RAMWRL is an active LOW write enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMRDL is HIGH, a
LOW on RAMWRL will enable the data inputs. The data present
on DBO-7 will be written into the addressed RAM location.
RAMRDL,
TRAMRDL
I
READ: RAMRDL is an active LOW read enable input. When the
RAM cell is selected (RAMSELL LOW) and RAMWRL is HIGH, a
LOW on RAMRDL will enable the data outputs. The contents of
the addressed RAM location will be presented on DBO-7.
RAMSELL,
TRAMSELL
I
RAM SELECT: RAMSELL is an active LOW RAM cell select input.
RAMS ELL must be active during all RAM operations. When
RAMSELL is HIGH, DBO-7 will be in a high impedance state.
Pin Name
4-121
Intel
INTRODUCTION TO CELL-BASED DESIGN
Pin Description (Cont'd.)
Pin Name
DBO-7
LBYTADD,
LBYTDAT
HBYTADD,
HBYTDAT
TLBYTADD,
TLBYTDAT,
THBYTADD,
THBYTDAT
DBCTL
Pin Type
Function
I/O
DATA: DBO-7 are bidirectional, 3-state data lines. During a write
operation, DBO-7 are data inputs to the RAM. During a read
operation, DBO-7 are data outputs from the RAM. DBO-7 will
remain in a high impedance state except during a read operation
(RAMSELL, RAMRDL LOW). DBO-7 can also serve as a multiplexed address/data bus. In this configuration, the DBO-7 lines
first present the valid address inputs to the RAM. After the address
is latched internally (see LBYTADD, LBYTDAT, HBYTADD,
HBYTDAT description), DBO-7 acts as the RAM data bus operating as described above.
I
ADDRESS BUS CONTROL: LBYTADD, LBYTDAT, HBYTADD, and
HBYTDAT are inputs which together determine the source of RAM
address inputs and control the internal latching of the address
lines (see table below). AO-9 will drive the internal address lines if
LBYTDAT and HBYTDAT are tied LOW. In this configuration, the
internal address lines will match AO-9 when LBYTADD and
HBYTADD are HIGH. Latching of the address inputs is accomplished by toggling LBYTADD and HBYTADD LOW. DBO-7 will
drive the internal address lines if LBYTADD and HBYTADD are
tied LOW. In this configuration, the internal address lines AO-9 are
latched from DBO-7 in two stages. First, AO-7 is driven by DBO-7
when LBYTDAT is HIGH and HBYTDAT is LOW and is latched by
toggling LBYTDAT LOW. Next, HBYTDAT is taken high to allow
the data on DBO-1 to appear on address bits AS-9. These address
bits are latched by toggling HBYTDAT LOW. When LBYTDAT and
HBYTDAT are LOW and the valid address has been latched in,
valid data may be presented on DBO-7.
0
LBYTADD
LBYTDAT
0
0
0
1
1
1
0
1
HBYTADD
HBYTDAT
0
0
0
1
1
0
1
1
Internal Address Lines
Address Latched
Driven by DBO-7 (AO-7)
Driven by AO-9
Invalid State
Internal Address Lines
Address Latched
Driven by DBO-1 (AS-9)
Driven by AO-9
Invalid State
DATA BUS CONTROL: The Data Bus Control signal is used for
data bus transceiver control. When this signal is high, DBO-7 are
being driven by the RAM cell.
4-122
FIXED CONFIGURATION RAM
Pin Description (Cont'd.)
Pin Name
TMODE,
TSEL
Pin Type
Function
I
TEST CONTROL LINES: TMODE and TSEL are inputs which
together determine the operating mode of the RAM cell (see table
below). The RAM cell can operate in one of three modes: user
mode, active test mode, or inactive test mode.
TMODE
TSEL
Function
0
0
1
1
0
1
0
1
User Mode (Normal operation)
User Mode (Normal operation)
Inactive Test Mode
Active Test Mode
NOTE: All signals Txxx are test related input signals. All test related signals except for TMODE and TSEL
have a user signal equivalent and are listed with their non-test counterpart. These test signals have
the identical functionality as their user signal equivalents, but are not used during normal user
operation. All test signals must be accessible through a package pin. This can be accomplished by
tying the test signal to its user signal equivalent if it is directly connected to a package pin, or to any
other user input signal that is directly connected to a package pin. One package pin for TMODE and
TSEL is required per device, regardless of the number of cells implemented which require these
inputs. Additional test logic will be necessary for TSEL generation to multiple cells.
Input Capacitance
Input Name
Max.
Units
AO-9
0.90
pF
DBO-7
2.00
pF
HBYTADD
0.10
pF
HBYTDAT
0.10
pF
LBYTADD
0.10
pF
LBYTDAT
0.10
pF
RAMRDL
0.90
pF
RAMSELL
0.90
pF
RAMWRL
0.90
pF
4-123
INTRODUCTION TO CELL-BASED DESIGN
3-State Output Capacitance
Output Name
Max.
Units
DBO-7(z)
2.00
pF
A.C. Characteristics at 0-70°C, 5V + / -10%
WRITE CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Write Cycle Time
23.0
40.0
88.0
ns
TELEH
RAMSELL Pulse Width
12.0
20.0
43.0
ns
TEHEL
RAMSELL HIGH Time
11.0
20.0
45.0
ns
TAVEL
Address Setup Time
0
0
0
ns
TELAX
Address Hold after RAMWRL HIGH
2.0
3.0
6.0
ns
TWLEL
RAMWRL LOW to Next RAMSELL LOW
23.0
40.0
88.0
ns
TWLWH
RAMWRL Pulse Width
12.0
20.0
43.0
ns
TDVWL
Data Setup to RAMWRL LOW
0
0
0
ns
TWLDX
Data Hold after RAMWRL HIGH
5.0
7.0
12.0
ns
TELWL
RAMSELL LOW to RAMWRL LOW
0
0
0
ns
TWLEH
RAMWRL LOW to RAMSELL HIGH
12.0
20.0
43.0
ns
TWHEL
RAMWRL HIGH to Next RAMSELL LOW
11.0
20.0
45.0
ns
FIXED CONFIGURATION RAM
READ CYCLE
Symbol
Parameter
Min.
Typ.
Max.
Units
TELEL
Read Cycle Time
28.0
55.0
112.0
ns
TELQV
Access Time From RAMSELL
17.0
35.0
67.0
ns
TGLQV
Access Time From RAMRDL
17.0
35.0
67.0
ns
TELEH
RAMS ELL Pulse Width
17.0
35.0
67.0
ns
TEHEL
RAMSELL HIGH Time
11.0
20.0
45.0
ns
TAVEL
Address Setup Time
5.0
7.0
11.0
ns
TELAX
Address Hold after RAMWRL HIGH
0
0
0
ns
TGLEL
RAMRDL LOW to Next RAMSELL LOW
28.0
55.0
112.0
ns
TGHEL
RAMRDL HIGH to Next RAMSELL LOW
11.0
20.0
45.0
ns
TGHQX
RAMRDL/RAMSELL HIGH to Data Float
5.0
8.0
15.0
ns
TELGL
RAMS ELL LOW to RAMRDL LOW
0
0
0
ns
TGLEH
RAMRDL LOW to RAMSELL HIGH
17.0
35.0
67.0
ns
TSRLCH
RAMRDL/RAMSELL LOW to DBCTL HIGH
5.0
8.0
16.0
ns
TSRHCL
RAMRDL/RAMSELL HIGH to DBCTL LOW
5.0
8.0
16.0
ns
Load Dependent Delay
Output Name
DBO-7
Min.
Tplh
Typ.
Max.
Min.
Tphl
Typ.
Max.
0.75
1.50
3.20
0.75
0.90
1.50
Units
ns/pF
INTRODUCTION TO CELL-BASED DESIGN
!.---------TELEL--------~
!.-----TELEH---~
RAMSELL
-
.....--TWLEH
RAMWRL
TAVEL
TDVWL-l
TWLDX
_DA_T_A______________~(r--------------~~------------------
Write Cycle
G40208
~-------TELEL-------~
Read Cycle
4-126
G40208
Appendix
Packaging
A
APPENDIX A
PACKAGING
Intel offers a wide array of standard package types for use with cell-based ASICs. Refer to
Table A-I below for a chart of standard package types currently available. Additional package
types are available upon request.
Table A-I lists the available packages categorically by type and by lead count. In addition,
the pin spacing for each package type is given. Please consult with your Intel Sales Representative if you have any questions regarding a given package type.
Table A-1. Packages for Cell-Based ASICs
Lead Count
Pin Spacing
(Mils)
Plastic Dual-In-Line:
POIP
POIP
POIP
POIP
POIP
POIP
POIP
16
18
20
24
28
40
48
100
100
100
100
100
100
100
Ceramic Dual-In-Line:
COIP
COIP
COIP
COIP
COIP
20
24
28
40
48
100
100
100
100
100
Side Brazed Ceramic Dual-In-Line:
SIB DIP
SIB DIP
SIB DIP
28
40
48
100
100
100
Plastic Leaded Chip Carrier:
PLCC
PLCC
PLCC
PLCC
PLCC
PLCC
PLCC
20
28
32
44
52
68
84
50
50
50
50
50
50
50
Ceramic Leaded Chip Carrier:
CLCC
CLCC
CLCe
44
68
84
50
50
50
Package Type
A-1
INTRODUCTION TO CELL-BASED DESIGN
Table A-1. Packages for Cell-Based ASICs (Cont'd.)
Package Type
Lead Count
Pin Spacing
(Mils)
68
84
50
50
84
100
132
164
196
25
25
25
25
25
84
100
132
164
196
25
25
25
25
25
28
44
68
50
50
50
68
72
88
100
132
144
100
100
100
100
100
100
68
72
84
88
100
132
144
180
208
100
100
100
100
100
100
100
100
100
80
100
124
144
160
25.6
25.6
25.6
25.6
25.6
Ceramic Leadless Chip Carrier:
LCC
LCC
Plastic Quad Flat Pack:
PQFP
PQFP
PQFP
PQFP
PQFP
Ceramic Quad Flat Pack:
CQFP
CQFP
CQFP
CQFP
CQFP
Pressed Ceramic Quadpack:
CERQUAD
CERQUAD
CERQUAD
Plastic Pin Grid Array:
PPGA
PPGA
PPGA
PPGA
PPGA
PPGA
Ceramic Pin Grid Array:
CPGA
CPGA
CPGA
CPGA
CPGA
CPGA
CPGA
CPGA
CPGA
EIAJ Quad Flat Pack*:
EIAJQFP
EIAJQFP
EIAJQFP
EIAJQFP
EIAJQFP
*Contact your Intel Sales Representative
Appendix
Terms and Definitions
B
APPENDIX B
TERMS AND DEFINITIONS
The following terms and definitions are for cell specification parameters which appear in
the Intel 1.5 Micron CHMOS III Cell Library data sheets. These terms and definitions are
in accordance with current JEDEC standards.
I1H: High-Level Input Current
The current into* an input when a specified high-level voltage is applied to that input.
IlL: Low-Level Input Current
The current into* an input when a specified low-level voltage is applied to that input.
10H: High-Level Output Current
The current into* an output with input conditions applied that, according to the product
specification, will establish a high level at the output.
10L: Low-Level Output Current
The current into* an output with input conditions applied that, according to the product
specification, will establish a low level at the output.
Tphl: Propagation Delay Time, High-to-Low Level Output
The time interval between the specified reference points on the input and output voltage
waveforms with the specified output changing from the defined high level to the defined low
level.
Tphz: Disable Time from the High Level (of a three-state output)
The time interval between the specified reference points on the input and output voltage
waveforms with the specified output changing from the defined high level to a high-impedance
(off) state.
Tplh: Propagation Delay Time, Low-to-High Level Output
The time interval between the specified reference points on the input and output voltage
waveforms with the specified output changing from the defined low level to the defined high
level.
Tplz: Disable Time from the Low Level (of a three-state output)
The time interval between the specified reference points on the input and output voltage
waveforms with the specified output changing from the defined low level to a high-impedance
(off) state.
*Current out of a terminal is given as a negative quantity.
INTRODUCTION TO CELL-BASED DESIGN
Tpzh: Enable Time to the High Level (of a three-state output)
The time interval. between the specified reference points on the input and output voltage
waveforms with the specified output changing from a high-impedance (off) state to the
defined high level.
Tpzl: Enable Time to the Low Level (of a three-state output)
The time interval between the specified reference points on the input and output voltage
waveforms with the specified output changing from a high-impedance (off) state to the
defined low level.
Th: Hold time
The time interval during which a signal is retained at a specified input after an active transition occurs at another specified input.
Note: The hold time is the actual time between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which operation of the digital circuit is guaranteed.
Tsu: Setup Time
The time interval between the application of a signal at a specified input and a subsequent
active transition at another specified input.
Note: The setup time is the actual time between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the
shortest interval for which correct operation of the digital circuit is guaranteed.
Vhys: Hysteresis
The difference between the positive-going and negative-going input threshold voltages.
VIH (min): Minimum High-Level Input Voltage
The least positive (most negative) value of high-level input voltage for which operation of
the logic element within specification limits is guaranteed.
VIL (max): Maximum Low-Level Input Voltage
The most positive (least negative) value of low-level input voltage for which operation of the
logic element within specification limits is guaranteed.
VOH: High-Level Output Voltage
The voltage level at an output with input conditions applied that, according to the product
specification, will establish a high level at the output.
VOL: Low-Level Output Voltage
The voltage level at an output with input conditions applied that, according to the product
specification, will establish a low level at the output.
TERMS AND DEFINITIONS
VT +: Positive-Going Input Threshold Voltage
The input voltage level that, when crossed as the input voltage is rising, enables an output
to change its logic state.
VT-: Negative-Going Input Threshold Voltage
The input voltage level that, when crossed as the input voltage is falling, enables an output
to change its logic state.
Appendix
Cell Reference Guide
c
APPENDIX C
CELL REFERENCE GUIDE
Cell
ADDB
ADDC
ADDP
AND2
AND3
AND4
AND5
AND6
AND7
AND8
AOl22
AOR22
BUF
BUFH
BUFTD
BUFTE
BUF2
CMPB
CMPC
CMPP
CPR
CULB
CULC
CULP
CUPB
CUPC
CUPP
CUPP2
DMX2
DMX3
EXN2
EXR2
FFD
FFDE
FFDHI
FFDM2
FFJK
FFT
FFTE
FLOE
FLDET
Description
Grid Count
Page
Telescoping Adder Body
Telescoping Adder Control
Telescoping Adder Carry Out Driver
2 Input AND, Normal Drive
3 Input AND, Normal Drive
4 Input AND, Normal Drive
5 Input AND, Normal Drive
6 Input AND, Normal Drive
7 Input AND, Normal Drive
8 Input AND, Normal Drive
2 AND2 into NOR2, Normal Drive
2 AND2 into OR2, Normal Drive
Buffer, Normal Drive
Buffer, High Drive
3-State Buffer with Active High Output Enable,
Normal Drive
3-State Buffer with Active Low Output Enable,
Normal Drive
Buffer with Dual Output, Normal Drive
Telescoping Magnitude Comparator Body
Telescoping Magnitude Comparator Control
Telescoping Magnitude Comparator Equal/
Greater Than/Less Than Driver
8/9-bit Parity Checker/Generator
Telescoping Up Counter Body
Telescoping Up Counter Control
Telescoping Up Counter Carry Out Driver
Telescoping Up/Down Counter Body
Telescoping Up/Down Counter Control
Telescoping Up/Down Counter End Count Driver
Telescoping Up/Down Counter End Count/Carry/
Borrow Driver
2-Line to 4-Line Demultiplexer/Decoderwith
2 Enables
3-Line to a-Line Demultiplexer/Decoder
2 Input EXCLUSIVE NOR, Normal Drive
2 Input EXCLUSIVE OR, Normal Drive
o Flip-Flop with Master Reset
o Flip-Flop with Enable and Master Reset
Positive Edge Event Trigger with Master Reset
o Flip-Flop with 2 to 1 Data Multiplexer and
Master Reset
JK Flip-Flop with Master Reset
Toggle Flip-Flop with Master Reset
Toggle Flip-Flop with Enable and Master Reset
o Flip-Flop with Enable, Master Set, and Master
Reset
3-State 0 Flip-Flop with Enable, Master Set, and
Master Reset
169
13
39
52
65
78
104
130
169
182
78
78
39
52
65
3-161
3-160
3-163
3-39
3-40
3-41
3-42
3-43
3-44
3-45
3-54
3-53
3-18
3-18
3-23
65
3-21
52
182
26
104
3-30
3-168
3-167
3-170
429
338
169
39
429
195
26
143
3-100
3-138
3-136
3-141
3-151
3-148
3-154
3-156
299
3-96
559
65
78
208
273
195
260
3-98
3-56
3-55
3-68
3-70
3-81
3-77
247
195
247
260
3-61
3-57
3-59
3-72
260
3-74
C-1
INTRODUCTION TO CELL-BASED DESIGN
Cell
FLDM2
FLJK
FLJKT
INVN
INVNH
INVTD
INVTE
LAD
LANSR
LASR
LNSR
LSR
MUX21
MUX41
NAN2
NAN3
NAN4
NAN5
NAN6
NAN7
NAN8
NOR2
NOR3
NOR4
NOR5
NOR6
NOR7
NOR8
OR2
OR3
OR4
OR5
OR6
OR7
OR8
PADB
PCI
PCIH
PCIO
PCNO
PCN04
PCO
PCOT
PC02
PCOT6
PISH
PISRH
Description
Grid Count
Page
o Flip-Flop with 2 to 1 Data Multiplexer, Master
Set and Master Reset
JK Flip-Flop with Master Set and Master Reset
3-State JK Flip-Flop with Master Set and Master
Reset
Inverter, Normal Drive
Inverter, High Drive
3-State Inverter with Active High Output Enable,
Normal Drive
3-State Inverter with Active Low Output Enable,
Normal Drive
!r~nsparent 0 Latch with Master Reset
S-R Latch with Enable and Master Reset
S-R Latch with Enable and Master Reset
S-R Latch with Master Reset
S-R Latch with Master Reset
2-Line to 1-Line Multiplexer
4-Line to 1-Line Multiplexer
2 Input NAND, Normal Drive
3 Input NAND, Normal Drive
4 Input NANQ, Normal Drive
5 Input NAND, Normal Drive
6 Input NAND, Normal Drive
7 Input NAND, Normal Drive
8 Input NAND, Normal Drive
2 Input NOR, Normal Drive
3 Input NOR, Normal Drive
4 Input NOR, Normal Drive
5 Input NOR, Normal Drive
6 Input NOR, Normal Drive
7 Input NOR, Normal Drive
8 Input NOR, Normal Drive
2 Input OR, Normal Drive
3 Input OR, Normal Drive
4 Input OR, Normal Drive
5 Input OR, Normal Drive
6 Input OR, Normal Drive
7 Input OR, Normal Drive
8 Input OR, Normal Drive
Address/Data Bus I/O Buffer
Non-Inverting CMOS Input Buffer, Normal Drive
Non-Inverting CMOS Input Buffer, High Drive
CMOS I/O Buffer; Latched Non-Inverting Input,
3-State Inverting Output, 3.2 rnA
Non-Inverting CMOS Output Buffer, 3.2 rnA
Non-Inverting CMOS Output Buffer, 15 rnA
Inverting CMOS Output Buffer, 3.2 rnA
3-State Inverting CMOS Output Buffer, 3.2 rnA
Inverting CMOS Output Buffer, 16 rnA
3-State Inverting CMOS Output Buffer with
Enable, 42 rnA
Non-Inverting TTL Schmitt Trigger Input Buffer,
High Drive
Non-Inverting TTL Schmitt Trigger Input Buffer
with Pull-up Resistor, High Drive
260
3-79
260
247
3-63
3-65
26
39
52
3-12
3-12
3-16
52
3-14
143
182
182
104
104
104
182
39
65
78
104
117
169
182
52
78
104
130
143
169
182
52
78
91
143
156
182
195
3-83
3-91
3-87
3-89
3-85
3-93
3-94
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
3-46
3-47
3-48
3-49
3-50
3-51
3-52
4-18
3-172
3-172
3-201
C-2
3-183
4-94
3-182
3-184
4-96
4-98
3-178
3-180
inter
Cell
POSC
POSC2
PRESET
PRGPIN
PTI
PTIH
PTIO
PTI03
PTI05
PTIRH
PTND
PTND3
PTND5
PTNO
PTN03
PTN05
PTNQB
PTO
PTOT
PTOT3
PTOT5
RAM64
RAM128
RAM256
RAM512
RAM1K
REGB
REGBT
REGC
REGCT
SHLB
SHLC
SHRB
SHRC
SP82284
SP82288
SP8237
SP8254
SP8259
SP8284
SP8288
UC5100
UC5104
UC5108
UC5116
CELL REFERENCE GUIDE
Description
Oscillator, Frequency Range to 16 MHz
Oscillator, Frequency Range to 37.5 MHz
Reset Input Buffer
Programmable I/O Buffer
Non-Inverting TTL Input Buffer, Normal Drive
Non-Inverting TTL Input Buffer, High Drive
TTL I/O Buffer; Latched Non-Inverting Input,
3-State Inverting Output, 3.2 mA Sink
TTL I/O Buffer; Latched Non-Inverting Input,
3-State Inverting Output, 9.6 mA Sink
TTL I/O Buffer; Latched Non-Inverting Input,
3-State Inverting Output, 16 mA Sink
Non-Inverting TTL Input Buffer with Pull-up
Resistor, High Drive
Non-Inverting TTL Open-Drain Output Buffer,
3.2 mA Sink
Non-Inverting TTL Open-Drain Output Buffer,
9.6 mA Sink
Non-Inverting TTL Open-Drain Output Buffer,
16 mA Sink
Non-Inverting TTL Output Buffer, 3.2 mA Sink
Non-Inverting TTL Output Buffer, 9.6 mA Sink
Non-Inverting TTL Output Buffer, 16 mA Sink
Quasi-Bidirectional I/O Buffer
Inverting TTL Output Buffer, 3.2 mA Sink
3-State Inverting TTL Output Buffer, 3.2 mA Sink
3-State Inverting TTL Output Buffer, 9.6 mA Sink
3-State Inverting TTL Output Buffer, 16 mA Sink
64 X 8 Static Random Access Memory
128 X 8 Static Random Access Memory
256 X 8 Static Random Access Memory
512 X 8 Static Random Access Memory
1024 X 8 Static Random Access Memory
Telescoping Register Body
Telescoping 3-State Register Body
Telescoping Register Control
Telescoping 3-State Register Control
Telescoping Shift Register with Load, Body
Telescoping Shift Register with Load, Control
Telescoping Shift Register Body
Telescoping Shift Register Control
80286 Clock Generator and Ready Interface
80286 Bus Controller
Programmable DMA Controller
Programmable Interval Timer
Programmable Interrupt Controller
8086/8088 Clock Generator and Driver
8086/8088 Bus Controller
80C51 BH Microcontroller Core with No ROM
80C51 BH Microcontroller Core with 4K Bytes
ROM
80C51 BH Microcontroller Core with 8K Bytes
ROM
80C51 BH Microcontroller Core with 16K Bytes
ROM
C-3
Grid Count
Page
4-16
4-92
4-14
4-23
3-174
3-174
3-203
3-205
3-207
3-176
3-198
3-199
3-200
221
234
117
156
312
156
221
130
3-187
3-188
3-190
4-20
3-186
3-192
3-194
3-196
4-100
4-105
4-110
4-115
4-121
3-107
3-114
3-105
3-112
3-129
3-127
3-122
3-120
4-73
4-80
4-25
4-41
4-49
4-57
4-64
4-1
4-1
4-1
4-1
Introduction to Intel Cell-Based Design
231816-002
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Intel Corporation
Attn: CPO Product Marketing MIS WF1-61
6501 W. Chandler Blvd.
Chandler, AZ 85226
DOMESTIC SALES OFFICES
ALABAMA
GEORGIA
NEW MEXICO
TEXAS
tlntel Corp.
5015 Bradford Dr., #2
Huntsville 35805
Tel: (205) 830-4010
tlntel Corp.
3280 Pointe Parkway
Suite 200
Norcross 30092
Tel: (404) 449-0541
th')lgI~~~~1 Boulevard N.E.
!\njeJGf~g;'rson Lane
Suite 314
Austin 78752
Tel: (512) 454-3628
ARIZONA
m~~ ~or~8th
Dr.
Suite 0-214
Phoenix 85029
Tel: (602) 869-4980
NEW YORK
InteICo~.·
Intel Corp.
127 Main Streel
Binghamton 13905
~~~aN';mb~%n~gMoad, Suite 400
Tel: (312) 310-8031
INDIANA
Suite 301
Tucson 85715
Tel: (602) 299-6815
tlntel Corp.
8777 Purdue Road
Suite 125
Indianapolis 46268
Tel: (317) 875-0623
tlntel Corp.
21515 Vanowen Streel
Suile 116
~:c(gla8m~~8~00g
tlntel Corp.
2250 E. Imperial Highway
Suile 218
i~~(~~~)dg4~~t6~0
Intel Corp.
~~~~a~~~t~ V;Ui~uite 101
IOWA
Intel Corp.
193051. Andrews Drive N.E.
2nd Floor
Cedar Rapids 52402
Tal: (319) 393-5510
KANSAS
tlntel Corp.
8400 W. 11 Oth Street
SUite 170
Overland Park 66210
Tel: (913) 345-2727
Tel: (916) 920-8096
MARYLAND
tlnlel Corp.
4350 Executive Drive
Suite 105
San Diego 92121
Tel: (619) 452-5880
Intel Corp:
400 N. Tustin Avenue
Suite 450
Santa Ana 92705
Tel: (714) 835-9642
TWX: 910-595-1114
tlntel Corp:
San Tomas 4
2700 San Tomas Expressway
2nd Floor
Santa Clara, CA 95051
Tel: (408) 986-8086
TWX: 910-338-0255
COLORADO
Intel Corp.
4445 Northpark Drive
Suite 100
~~II:O{~~~ ~C4~6~~~0907
tlntel Corp:
g~~;er~~'i~ 51., Suite 915
Tel: (303) 321-8086
TWX: 910-931-2289
CONNECTICUT
tlntel Corp.
26 Mill Plain Road
2nd Floor
Danbury 06811
Tel: (203) 748-3130
TWX: 710-456-1199
FLORIDA
tlntel Corp.
~sc.~d'Z;d~tl~ ~~o:uite 100
Tel: (305) 771-0600
TWX: 510-956-9407
FAX: 305-772-8193
tlntel Corp.
5850 T.G. Lee Blvd.
Suite 340
Orlando 32822
~~~~~5m~g~~
tlntel Corp.
1I 300 4th Street North
Suite 170
51. Petersburg 33716
~~~:U&~~~;2~~JJt
ILLINOIS
\~t~\ ~or~i Dorado Place
CALIFORNIA
Suite B 295
Intel Corp:
7321 Parkway Drive South
SUiteC
Hanover 21076
Tel: (301) 796-7500
TWX: 710-862-1944
Intel Corp.
7833 Walker Drive
SUite 550
Greenb9lt 20770
Tel: (301) 441-1020
MASSACHUSETTS
tlntal Corp."
Westford Corp. Center
3 Carlisle Road
2nd Floor
Westford 01886
Tel: (617) 692-3222
TWX: 71 0-343-6333
MICHIGAN
tlntel Corp.
7071 Orchard Lake Road
Suite 100
West Bloomfield 48033
Tel: (313) 851-8096
MINNESOTA
Intel Corp.
3500 W. 80th St., Suite 360
Bloomington 55431
Tel: (612) 835-6722
TWX: 910-576-2867
MISSOURI
Intel Corp.
~~~~~~i-m:m~
tlntel Corp:
F;~~~s1SJ~~S Office Park
Tel: (716) 425-2750
TWX: 510-253-7391
UTAH
~:I~~m)g;3~ ~60
Intel Corp.
5201 Green Street
Suile 290
Murray 84123
Tel: (801) 263-8051
TWX: 510-227-6236
tlntel Corp.
15 Myers Corner Road
Suite 2B
Hollowbrook Park
~~P~~2i'~U~~sl ~ ~590
TWX: 510-248-0060
NORTH CAROLINA
Intel Corp.
5700 Executive Drive
Suite 213
Charlotte 28212
Tel: (704) 568-8966
tlntel Corp.
2700 Wycliff Road
Suite 102
~:llei3~9r7~~~8022
OHIO
Intel Corp:
3401 Park Center Drive
SUite 220
Dayton 45414
Tel: (513) 890-5350
TWX: 810-450-2528
Intel Corp.
155108th Avenue N.E.
SUite 386
Bellevue 98004
Tel: (206) 453-8086
TWX: 910-443-3002
Intel Corp.
408 N. Mullan Road
Suite 102
Spokane 99206
Tel: (509) 928-8086
WtSCONSIN
tlntel Corp.
330 S. Executive Dr.
Suite 102
Brookfield 53005
Tel: (414) 784-8087
FAX: (414) 796-2115
CANADA
BRITISH COLUMBIA
~J~\ crf.r~roadWay
Intel Semiconductor of Canada, Ltd.
Oklahoma City 73162
Tel: (405) 848-8086
~~~~a~~n~g~ ~W' Suite 202
Tel: (604) 298-0387
FAX: (604) 298-8234
OREGON
ONTARIO
tlntelCorp.
15254 N.W. Greenbrier Parkway, Bldg. B
Beaverton 97006
Tel: (503) 645-8051
TWX: 910-467-8741
tlntel Semiconductor of Canada, Ltd.
2650 Queensview Drive
Suite 250
Ottawa K2B 8H6
Tel: (613) 829-9714
TLX: 053-4115
Suite 115
PENNSYLVANIA
Intel Corp. ~
~knJe~c;;g;ate
WASHINGTON
OKLAHOMA
455 Pennsylvania Avenue
Suite 230
Fort Washington 19034
Tel: (215) 641-1000
TWX: 510-661-2077
Center
75 Uvingston Avenue
First Floor
Roseland 07068
Tel: (201) 740-0111
FAX: 201-740-0626
VIRGINIA
tlntel Corp.
1504 Santa Rosa Road
Suite 108
Richmond 23288
Tel: (804) 282-5668
Intel Corp:
25700 Science Park Dr., Suite 100
Beachwood 44122
Tel: (216) 464-2736
TWX: 810-427-9298
Suite 131
Earth City 63045
Tel: (314) 291-1990
tlntel Corp:
Parkway 109 Office Center
328 Newman Springs Road
Red Bank 07701
Tel: (201) 747-2233
~~~~~wm:~~g&
Intel Corp.-
7322 S.w. Freeway
Suite 1490
Houston 77074
Tel: (713) 988-8086
TWX: 910-881-2490
tlntel Corp:
300 Motor Parkway
4203 Earth City Expressway
NEW JERSEY
tlntel Corp.'
12000 Ford Road
Suite 400
Dallas 75234
Intel Corp:
400 Penn Center Blvd., Suite 610
~~~,.~~r~t81~~~70
PUERTO RICO
tlntel Semiconductor of Canada, Ltd.
190 Attwell Drive
Suite 500
Rexdale M9W 6H8
Tel: (416) 675-2105
TLX: 06983574
FAX: (416) 675-2438
QUEBEC
tlntel Semiconductor of Canada, Ltd.
62051. John Boule"ard
POinte Claire H9R 3K2
Tel: (514) 694-9130
TWX: 514-694-9134
Intel Micropr~essor Corp.
South Industnal Park
P.O. Box 910
Las Piedras 00671
Tel: (809) 733-8616
~~~~~11~_~~~~~6~
tSales and Service Office
"Field Application Location
CG-l/18/88
inter
DOMESTIC DISTRIBUTORS
ALABAMA
CALIFORNIA (Cont'd.)
FLORIDA
INDIANA (Cont'd.)
MICHIGAN (Cont'd.)
Arrow Electronics, Inc.
1015 Henderson Road
Huntsville 35816
Tel: (205) 837-6955
Kierulff Electronics. Inc.
10824 Hope Street
Cypress 90430
lArrow Electronics. Inc.
~6~~~~"ch:v~r~!eElectroniCS
~~k~Wi-~1t~~~
Pioneer ElectroniCs
4505 Bro.dmoor Ave. S.E.
Grand Rapids 49508
Tel: (616) 698-1800
FAX: 616-698-1831
tPioneer Electronics
6408 Castleplace Drive
Indianapolis 46250
rei: (317) 849-7300
TWX: 810-260-1794
13485 Stamford
Livonia 48150
Tel: (313) 525-1800
TWX: 810-242-3271
KANSAS
MINNESOTA
tHamilton/Avnet ElectronicS
9219 Quivera Road
Overland Park 66215
Tel: (913) 888-8900
FAX: 913-541-7951
tArrow Electronics. Inc.
5230 W. 73rd Street
Edina 55435
tHamilton/Avnet Electronics
4940 Research Drive
Huntsville 35805
Tel: (205) 837·7210
TWX: 810-726·2162
~~k~j',~_~~~:g~gg
50 Fairway Drive
Deerfield Beach 33441
Tel: (305) 429-8200
TWX: 510-955-9456
tKierulff Electronics, Inc.
1180 Murphy Avenue
San Jose 95131
Tel: (408) 971-2600
FAX: 408-947-3432
Arrow Electronics, Inc.
1001 NW. 62nd St., Ste. 108
Ft. Lauderdale 33309
Tel: (305) 475-4297
TWX: 510-955-9456
tKierulff Electronics, Inc.
14242 Chamber Rd.
Tustin 92680
tArrow Electronics, Inc.
1530 Bottlebrush N.E.
Palm Bay 32905
Tel: (305) 725-1480
Carmel 46032
tPioneer Electronics
Pioneer/Technologies Group Inc.
~~~~s~~I~e;~~r6Square
Tel: (205) 837-9300
TWX: 810-726-2197
~~Ik~jll~_~~~:~m
ARIZONA
tHamilton/Avnet Electronics
505 S. Madison Drive
Tempe 85281
Tel: (602) 968-1461
TWX: 910-950·0077
tHamillon/Avnet Electronics
tKierulff Electronics, Inc.
9800 Variel St.
Chaltsworth 91311
Tel: (213) 725-0325
FAX: 818-407-0803
Wyle Distribution Group
Kierulff Electronics, Inc.
4134 E. Wood Street
Phoenix 85040
Tel: (602) 437·0750
FAX: 602-252·9109
fifJU)~ti~~~~~~~~~~ Highway
Phoenix 85023
~~k~~~~-~~~:~~~~
CALIFORNIA
Arrow Electronics. Inc.
19748 Dearborn Street
Chatsworth 91311
Tel: (818) 701·7500
FAX: 818-772·8930
Arrow Electronics. Inc.
9511 Ridgehaven Court
~:~ (~it"~)o5~;~floo
~~~:~a~.::~f3J~
Rd.
Tel: (818) 880-9000
FAX: 816-880-5510
tWyle Distribution Group
17872 Cowan Avenue
Irvine 92714
m~jW~~~:gm
Wyle Distribution Gro.up
11151 Sun Center Drive
Rancho Cordova 95670
Tel: (916) 638-5282
FAX: 916-638-1491
tAvnet Electronics
350 McCormick Avenue
Costa Mesa 92626
~~lk~jWm:~gg~
Hamilton/Avnet ElectroniCs
1175 Bordeaux Drive
~~I~'iXo~M~~~joo
FAX: 408-745·6679
tHamilton/Avnet Electronics
4545 Viewridge Avenue
~:In (~\e~)o5~~~;~00
FAX: 619-277-6136
tHamilton/Avnet Electronics
9650 Desoto Ave.
Chatsworth 91311
Tel: (818) 700-1222, 6500
FAX: 818-700·6553
1~8f'~~~~~~r:k~I~I;~~~~cs
KENTUCKY
Hamilton/Avnet Electronics
805-A Newtown Circle
~:~T~J~) 2~09~n75
MISSOURI
Arrow Electronics. Inc.
8300 Guilford Road, Ste. H
Rivers Center
Columbia 21046
Tel: (301) 995-6002
TWX: 71 0-236-9005
FAX: 301-381-3854
tHamilton/Avnet Electronics
6822 Oak Hall Lane
Columbia 21045
Tel: (301) 995-3500
FAX: 301-995-3593
MASSACHUSETTS
m!jWg~J:~m
COLORADO
ILLINOIS
Arrow Electronics. Inc.
1390 S. Potomac Street
Suite 136
Aurora 80012
Tel: (303) 696-1111
tArrow ElectroniCS, Inc.
tHamilton/Avnet Electronics
8765 E. Orchard Road
Suite 708
Englewood 80111
Tel: (303) 740-1017
TWX: 910-935-0787
tWyle Distribution Group
451 E. 124th Avenue
Thornlon 80241
Tel: (303) 457-9953
TWX: 910-936-0770
tArrow Electronics. Inc.
12 Beaumont Road
3~7-3440
Tel: (312)
FAX: 312-397-3550
tHamiiton/Avnet Electronics
1130 Thorndale Avenue
Bensenville 60106
Tel: (312) 860-7780
TWX: 91 0-227-0060
Kierulff Electronics. Inc.
1140 W. Thorndale
Itasca 60143
Tel: (312) 250-0500
FAX: 312-250-0916
tPioneer Electronics
1551 Carmen Drive
TWX: 710-476-0162
~~: ~mi :3~~~~8~0007
Hamilton/Avnet Electronics
Commerce Industrial Park
Commerce Drive
TWX: 910-222-1834
~:I~~~O!Jmi-~800
FAX: 203-797-2866
FAX: 213-558-2248
tPioneer Northeast ElectroniCS
112 Main Street
Norwalk 06851
Tel: (203) 853-1515
TWX: 710-468-3373
jMICrocomputer System Technical Distributor Centers
tArrow Electronics. Inc.
1 Arrow Drive
Woburn 01801
Tel: (617) 933-8130
TWX: 710-393-6770
tHamilton/Avnet Electronics
10D Centennial Drive
~:~~g~t) ~~~~g701
INDIANA
tArrow Electronics, Inc.
2495 Directors Row, Suite H
Indianapolis 46241
Tel: (317) 243-9353
TWX: 810-341-3119
~~k~~W~~~:~~~
tHamilton/Avnet Electronics
13743 Shoreline Court East
Earth City 63045
m~~W~~tmg
Kierulff Electronics. Inc.
11804 Borman Dr.
St. Louis 63146
~~lk~~Wm:g~~g
NEW HAMPSHIRE
tArrow Electronics. Inc.
3 Perimeter Road
Manchester 031 03
Tel: (603) 668-6968
FAX: 603-668-3484
Hamilton/Avnet Electronics
444 E. Industrial Drive
Manchester 03103
m~~~~-~~1:~1gg
NEW JERSEY
~Arrow Electronics. Inc.
000 Lincoln Drive East
Marlton 08053
Tel: (609) 596-8000
FAX: 609-596-5632
TWX: 710-393-0382
tArrow Electronics, Inc.
6 Century Drive
Kierulff Electronics. Inc.
13 Fortune Dr.
Billerica 01821
Tel: (617) 667-8331
TWX: 710-390-1449
FAX: 617-663-1754
~:r:s!~8r)nSa~g~go
Pioneer Northeast Electronics
44 Hartwell Avenue
0
TWX: 710-940-0262
FAX: 609-751-8624
~:~i(~lt7)~62,~~~00
FAX: 617-863-1547
~~osW~;tm,."h~~~~~le
Itasca 60143
Tel: (312) 773-2300
tPioneer Electronics
10203 Bren Road East
Minnetonka 55343
Tel: (612) 935-5444
FAX: 612-935-1921
tArrow Electronics. Inc.
2380 Schuetz
St. Louis 63146
Pioneer Electronics
3100 F. Northwoods Place
Norcross 30071
Tel: (404) 448-1711
FAX: 404·446-8270
~~~~~m~~~n~~~ 7~treet
~~~g'Wh~~n~ta~~~"ci~fv~cs
Minnetonka 55343
Tel: (612) 932-0600
FAX: 612-932-0613
FAX: 606-252-3238
tPioneer Electronics
9100 Gaither Road
Gaithersburg 20877
Tel: (301) 921-0660
TWX: 710-828-0545
Wyle Systems
7382 Lampson Avenue
Garden Grove 92641
~~lk~~W~~g:mg
MARYLAND
Hamilton/Avnet Electronics
5825 D. Peachtree Corners East
Norcross 30092
Tel: (404) 447-7500
TWX: 810-766-0432
WyleMllitary
18910 Teller Avenue
Irvine 92715
Tel: (714) 851-9958
TWX: 310-371-9127
FAX: 714-851-8366
fe~~I~~%~r~6~~j?~ 1
~~k~j;~-~1j1~g
10551 Lackman Rd.
Lenexa 66215
Tel: (913) 492-0500
FAX: 913-492-7832
tMesa Technology Corp.
9720 Patuxent Woods Dr.
Columbia 21046
Tel: (301) 720-5020
TWX: 710-828-9702
tHamilton/Avnet Electronics
3002 G Street
Ontario 91311
tHamiiton Electro Sales
3170 Pullman Street
Costa Mesa 92626
Pioneer Electronics
tArrow Electronics. Inc.
3155 Northwoods Parkway
SUite A
Norcross 30071
Tel: (404) 449-8252
FAX: 404-242-6827
CONNECTICUT
t~~m;lre~~~~~i~~:~~tr~I~~s
~~II:V(;I~;'!ig_~~~8
TWX: 810-853-0284
GEORGIA
Sacramento 95834
Tel: (916) 920-3150
FAX: 916-925-3478
~~k~jW~~~:~m
~~~ ~8~)t~ff.983g 32701
~:~ (~;e~)o5~;~:l71
000 Bowers A venue
Santa Clara 95051
Tel: (408) 727-2500
FAX: 408-727-5896
~~k~jWm:~m
tPioneer Electronics
337 N. Lake Blvd., St •. 1000
TWX: 910-371-9592
FAX: 619-565-9171 ext. 274
tArrow Electronics. Inc.
521 Weddell Drive
Arrow Electronics. Inc.
2961 Dow Avenue
Tustin 92680
~~re~n~~~~2~9~oulevard
Tel: (385) 628-3888
FAX: 305·628-3888 ext. 40
Pioneer Electronics
674 S. Military Trail
Deerfield Beach 33442
Tel: (305) 428-8877
TWX: 510-955-9653
tWyle Distribution Group
9525 Chesapeake Drive
~Wyle Distribution Group
~~I~'imM~~~loo
Hamilton/Avnet Electronics
3245 Tech Drive North
St. Petersburg 33702
Tel: (813) 576-3930
TWX: 810-863-0374
Hamilton/Avnet Electronics
FAX: 619-279-0862
FAX: 408-743·4770
~~0~a~d~;d~~!h3~3a69
Tel: (305) 971·2900
TLX: 510-956-3097
MICHIGAN
Arrow Electronics. Inc.
755 Phoenix Drive
Ann Arbor 48108
~~lk~~II~_~~l:~~~g
tHamilton/Avnet Electronics
32487 Schoolcraft Road
livonia 48150
Tel: (313) 522-4700
TWX: 810-242-8775
FAX: 313-522-2624
FAX: 201-538-4962
tHamilton/Avnet ElectroniCS
1 Keystone Ave .. Bldg. 36
f~I~(~O~;I~g~?gll
tHamiiton/Avnet Electronics
10 Industrial
Fairfield 07006
Tel: (201) 575-3390
FAX: 201-575-5839
tPioneer Northeast Electronics
45 Route 46
Pine brook 07058
Tel: (201) 575-3510
FAX: 201-575-3454
tMTI Systems Sales
37 Kulick Rd.
Fairfield 07006
Tel: (201) 227-5552
FAX: 201-575-6336
Hamilton/Avnet Electronics
2215 29th Street S.E.
Space AS
Grand Rapids 49506
Tel: (616) 243-8805
TWX: 810-273-6921
FAX: 616-243-0028
CG-l/18/88
DOMESTIC DISTRIBUTORS
NORTH CAROLINA (Conl'd,)
PENNSYLVANIA (Conl'd.)
WASHINGTON
ONTARIO
Alliance Electronics Inc.
Pioneer Electronics
Pioneer Electronics
9801 A-Southern Pine Blvd.
Charlotte 28217
Tel: (704)527-8188
TWX: 810-621-0366
259 Kappa Drive
tArmac Electronics Corp.
14360 S.E. Eastgate Way
Bellevue 98007
Tel: (206) 643-9992
FAX: 206-643-9709
Arrow Electronics Inc.
11030 Cochiti S.E.
Albuquerque 87123
NEW MEXICO
m~~~~-m:rs3~
Hamilton/Avnet Electronics
2524 Baylor Drive S.E.
Albuquerque 87106
m~~~5J_m:15gg
NEW YORK
Arrow ElectroniCS, Inc.
25 Hub Drive
Melville 11747
Tel: (516) 694-6800
TWX: 510-224-6126
FAX: 516-391-1401
tArrow Electronics, Inc.
3375 Brighton-Henrietta Townline Rd.
Rochester 14623
~~~~~\~-m:g~gg
Arrow Electronics. Inc.
20 Oser Avenue
Hauppauge 11788
Tel: (516)231-1000
FAX: 516-231-1072
Hamilton/Avnet Electronics
2060 Townline Rd.
Rochester 14623
~~~~~11~_m:~m
t~3r;~i~n6~~~e6;!~ctronics
Syracuse 13206
Tel: (315)437-2641
FAX: 315-432-0740
tHamilton/Avnet Electronics
933 Motor Parkway
Hauppauge 11788
Tel: (516)231-9800
FAX: 516-434-7426
tMTI Systems Sales
38 Harbor Park Drive
P.O. Box 271
~~e (;";6)h62~~~20~ 050
FAX: 516-625-3039
tPioneer Northeast Electronics
68 Corporate Dr.
Binghamton 13904
Tel: (607) 722-9300
FAX: 607-722-9562
tPioneer Northeast Electronics
60 Crossway Park West
~~:0(~~~79il~~~J~land 11797
TWX: 510-221-2184
FAX: 516-921-2143
tPioneer Northeast Electronics
840 Fairport Park
Fairport 14450
Tel: (716) 381-7070
FAX: 716-381-5955
NORTH CAROLtNA
tArrow Electronics, Inc.
5240 Greens Dairy Road
~:11:"!2~9~~~~3132
FAX: 919-876-3132, exl. 200
tHamiiton/Avnet Electronics
~~1~ St~i9~0~orest Drive
Tel: (~19)878-0819
TWX: 51 0-928-1836
~~~:s~~r~)~~~~g~oo
TWX: 710-795-3122
FAX: 412-963-8255
OHIO
Arrow Electronics. Inc.
7620 McEwen Road
Centerville 45459
Tel: (513)435-5563
FAX: 513-435-2049
tPioneer ElectroniCS
261 Gibralter Road
Horsham 19044
Tel: (215)674-4000
TWX: 510-665-6778
FAX: 215·674·3107
fArrow ElectroniCs, Inc.
6238 Cochran Road
Solon 44139
Tel: (216)248-3990
FAX: 216-248-1106
tArrow Electronics. Inc.
3220 Commander Drive
Carrollton 75006
Hamilton/Avnet ElectroniCS
m~~W~~g:~~g:
~:s~:~~~s:gB~IBIVd.
~~~~~W~~~:~~gci
tHamilton/Avnet Electronics
954 Senate Drive
Dayton 45459
Tel: (513) 439-6700
FAX: 513-439·6711
tHamilton/Avnet Electronics
30325 Bainbridge Rd., Bldg. A
Solon 44139
Tel: (216)349·5100
FAX: 216-349-1894
t Pioneer Electronics
4433 Interpoint Blvd.
Dayton 45424
Tel: (513)236-9900
FAX: 513-236-8133
TEXAS
tArrow Electronics. Inc.
10899 Kinghurst Dr.
SUite 100
Houston 77099
Tel: (713)530-4700
FAX: 713·568·8518
tArrow Electronics. Inc.
2227 W. Braker Lane
Austin 78758
Tel: (512)835-4180
FAX: 512-832-9875
tHamilton/Avnet Electronics
1807 A W. Braker Lane
Austin 78758
Tel: (512) 837·89tl
FAX: 512-339·6232
tHamilton/Avnet ElectronicS
2111 W. Walnut Hill lane
~~:~M~~~~0-6111
tPioneer Electronics
4800 E. 131 st Street
Cleveland 44105
Tel: (216)587-3600
TWX: 810-422-2211
FAX: 216-587-3906
tHamllton/Avnet Electronics
~~,;Wol('~i~~moad, Ste. 190
FAX: 214-550-6172
Arrow Electronics. Inc.
14320 N.E. 21st Street
Bellevue 98007
Tel: (206)643-4800
FAX: 206-746-3740
Hamilton/Avnet Electronics
14212 N.E. 21st Street
Bellevue 98005
~~I~~~~~-~~~:~g~~
f;>;Jg ~3~t~ig~~~n, ~~~p
Bellevue 98005
Tel: (206)453-8300
FAX: 206-453-4071
1093 Meyerside Dr.
Umt2
Mississau~a LST 1M4
~~I~~~\6J_6~~:b~~~
Arrow Electronics Inc.
Nepean K2E 7W5
~~~~~11~_m:~~~~
tHamilton/Avnet Electronics
6845 Rexwood Road
Units 3-5
Mississau~a L4V 1R2
~~~~~11~_6~~:b~~~
Hamilton/Avnet Electronics
3688 Nashua Dr.
Units 9 and 10
~~nim)~;7:ciX8~M5
WISCONSIN
FAX: 416-677-0627
tArrow Electronics, Inc.
200 N. Patrick Blvd., Ste. 100
Brookfield 53005
Tel: (414)792-0150
FAX: 414-792-0156
tHamilton/Avnet ElectroniCs
190 Colonnade Road South
Nepean K2E 7J5
Tel: (613)226-1700
FAX: 613-226-1184
Hamilton/Avnet Electronics
2975 Moorland Road
New Berlin 53151
Tel: (414)784-4510
FAX: 414-784-9509
tZentronics
8Tilbury Court
Brampton L6T 3T4
Tel: (416)451-9600
FAX: 416-451-8320
Kierulff Electronics, Inc.
2238-E W. Bluemound Rd.
Waukesha 53186
tZentronics
155 Colonnade Road
Unit 17
Nepean K2E 7Kl
Tel: (613) 226-8840
FAX: 613-226-6350
~~~~~W~~tg!gg
CANADA
ALBERTA
Hamilton/Avnet Electronics
281621 st Street N.E:
SASKATCHEWAN
Zentronics
173-1222 Alberta Avenue
Saskatoon S7K 1R4
Tel: (306)955-2202, 2207
FAX: (306) 244-3731
OKLAHOMA
Tel: (713)240-7733
FAX: 713-240-0582
Arrow Electronics. Inc.
3158 5.108 East Ave., Ste. 210
Tulsa 74146
Tel: (918)665-7700
FAX: 918-665-7700
Kierulff Electronics. Inc.
2010 Merritt Dr.
Garland 75040
Tel: (214)840-0110
FAX: 214·278-0928
FAX: 403-250-1591
OUEBEC
Zentronics
6815 8th Street, N.E., Ste.l00
tArrow ElectroniCS Inc.
4050 Jean Talon Ouest
Montreal H4P lWI
OREGON
tPioneer Electronics
1826-0 Kramer lane
Austin 78758
Tel: (512)835-4000
FAX: 512-835-9829
BRITISH COLUMBIA
tAl mac Electronics Corp.
1885 N.w. 169th Place
Beaverton 97006
Tel: (503) 629-8090
FAX: 503-645-0611
tHamilton/Avnet Electronics
6024 S.w. Jean Road
Bldg. C, Suite 10
~~~(5~~m~_i~~~4
FAX: 503-636-1327
Wyle Distribution Group
5250 N.E. Elam Young Parkway
Suite 600
Hillsboro 97124
Tel: (503)640-6000
FAX: 503-640-5846
PENNSYLVANIA
Arrow Electronics. Inc.
650 Seco Road
Monroeville 15146
Tel: (412)856-7000
FAX: 412-856-5777
Hamilton/Avnet Electronics
~?g~b~~b~rtf5~~~"
Bldg. E
~~I~~~\~-~~l::~~g
tPioneer Electronics
13710 Omega Road
Dallas 75244
m~~w.~~g:~~~g
tPioneer Electronics
5853 POint West Drive
Houston 77036
Tel: (713)988-5555
FAX: 713-988-1732
UTAH
tHamilton/Avnet Electronics
1585 West 2100 South
9
i:n (~~~i ~7~-g~JJ
~:I?(~'3'3T~~;~~80
~:II?t;63ml-~:38
FAX: 403-295-8714
Hamilton/Avnet Electronics
2550 Boundary Rd .. Ste. 115
Burnaby V5M 3Z3
Tel: (604)437-6667
FAX: 604-437-4712
Zentronics
108-11400 Bridgeport Road
Richmond V6X 1T2
Tel: (604)273-5575
FAX: 604-273-2413
MANITOBA
Zentronics
60-1313 Border Street
Winnipeg R3H OX4
Tel: (204) 694-1957
FAX: 204-633-9255
m(~\~-m:~~~l
Arrow Electronics Inc.
909 Charest Blvd.
Quebec 61 N 269
Tel: (418)687-4231
FAX: 418-687-5348
Hamilton/Avnet Electronics
2795 Rue Halpern
51. Laurent H4S 1P8
~~I~~~11~j~~:~~g~
Zentronics
~;.\~~~~:r::r4iti N4
~~~~~w-m:mg
FAX: 801-974-9675
Kierulff Electronics, Inc.
1946 W. parkwal Blvd.
~::~ la"o~i ~m9g9
FAX: 801-972-0200
Wyle Distribution Group
1325 West 2200 South
Suite E
9
~::~ (~~~i ~~~-g~J~
FAX: 801-972-2524
tMicrocomputer System Technical Distributor Centers
CG-l/18/88
inter
EUROPEAN SALES OFFICES
DENMARK
WEST GERMANY
ISRAEL
Inlel
Glentevej '61, 3rd Floor
Inlel'
Seidlstrasse 27
8000 Muenchen 2
Inlel'
Atidlm Industrial Park· Neve Sharet
P.O. Box 43202
Tel·Aviv 61430
Tel: 03-498080
TLX: 371215
~!?:~0~)~~n~8~n NV
TLX: 19567
FINLAND
Inlol
Ruosllanlie 2
00390 Holsinki
Tel: +3580544644
TLX: 123332
FRANCE
Inlel
1, Rue Edison·BP 303
78054 SI Quenlin·en·Yvelines Cedex
Tel: (I) 30 57 70 00
TLX: 699016
Inlol
Immeuble BBC
4, Quai des Elroils
m:og?£mtO
SPAIN
Inlel
Hohenzollern Sirasse 5
3000 Hannover I
ITALY
i~:ogWm081
Inlel'
Milanofiorl Palazzo E
Inlel'
Tel: (02) 824 40 71
TLX: 341286
i~:0:.',~r,gg5.0
NETHERLANDS
~~?:°0~1~~~r7~g
TLX: 7254826
~~?:°l8 Lmo 89
~mRe~of~a
Tel: +468734 01 00
TLX: 12261
SWITZERLAND
Inlel'
Marten Measweg 93
3068 AV Rotterdam
m:(~1~~'0-421.23.77
Inlel'
Talackerslrasse 17
8065 Zurich
i~:OM~~~ 29 77
UNITED KINGDOM
Inlel'
Pipers Way
Swindon, Willshire SN3 I RJ
NORWAY
Inlel
TLX: 305153
28010 Madrid
Tel: 410 40 04
TLX: 46880
SWEDEN
~~~~Assago
Inlel
Abraham lincoln Sirasse 16-18
6200 Wiesbaden
Inlel
Zettachring lOA
Inlel
Zurbaran, 28
Hvamveien 4-P .0. Box 92
~~::~6~~:~~0
i~!~~~~4~~860 00
TLX: 78018
EUROPEAN DISTRIBUTORS / REPRESENTATIVES
AUSTRIA
WEST GERMANY
ITALY (Conl'd.)
UNITED KINGDOM
Bacher Eleclronics G.m.b.H.
Rolonmuehlgasse 26
1120Wien
Eleclronic 2000 Vertriebs·AG
lasi Elettronica S.p.a.
Viale Fulvio Tesli 126
20092 Clnisello Balsamo
Milano
t~~~~:~rt"h~s~e~~b~~~ 'f~~
~6~~t~~~~~~~ ';2
Accenl Eleclronic Componenls Lid.
i~:(~;W3~3 56 46-0
Tel: (089) 42 00 10
TLX: 522561
BELGIUM
In Mulilkomponeni GmbH
Bahnholslrasse 44
NETHERLANDS
Inelco Belgium SA
Av. des Croix de Guerre 94
1120 Bruxelles
~~~ ~0~~)~~ni:~9
Koning en Hartman
Bracknell
Energleweg 1
2627 AP Delft
Tel: (015) 60 99 06
TLX: 38250
Berks RG12 lRW
Tel: (0344) 48 22 II
TLX: 848215
?12~'l~~~~I:lenlaan. 94
i~:('ia'4~~6 01
60
DENMARK
In·Mullikomponenl
Naverland 29
TLX: 7264399
Jermyn GmbH
1m Oachsstueck 9
6250 limburg
Tel: (064) 31 5080
TLX: 415257-0
Melrologie GmbH
~0~~i~~;~~~:~e7~9
m!~~2~16 0012
TLX: 33 355
Tel: (089) 78 04 20
TLX: 5213189
Smedsvingen 4
1364 Hvalslad
Tel: (2) 84 6210
TLX: 77546
FINLAND
Proelectron Vertriebs GmbH
PORTUGAL
~~?'o4~\~i~ul'5 66 45
OY Flnlronic AB
Melkonkalu 24A
00210 Helsinki
Tel: (0) 6926022
TLX: 124224
FRANCE
Generim
Z.A. de Courtaboeuf
Av. de la Ballique·BP 88
91943 Les Ulis Cedex
Tel: (I) 69 07 78 78
TLX: 691700
~3:7~nr~';~es Solels
S,lie 585
f!~1i) ~~~6so~e:x
TLX: 260967
Metrologie
Tour d'Asnieres
4, avo Laurenl·Cely
92606 Asnieres Cedex
Tel: (I) 47 90 62 40
TLX: 611448
T ekelec-Airtronic
Ruo Carle Vernel • BP 2
92315 Sevres Cedex
Tel: (1) 45 34 75 35
TLX: 204552
'Field Applicalion Localion
Max Planck Strasse 1·3
6072 Dreieich
Tel: (061) 03 30 43 43
TLX: 417972
IRELAND
Micro Markelin~ Lid.
Glenageary Office Park
Glenageary
Co. Dublin
Tel: (01) 85 63 25
TLX: 31584
Bytech Comway Ltd.
Um! 2 The Western Cenlre
Weslern Road
Jermyn
Veslry ESlale
Olford Road
NORWAY
Nordisk Eleklronik
P.O. Box 122
AIS
Ditram
Av. M. Bombarda, 133-1 0
1000 Lisboa
Tel: (I) 54 53 13
TLX: 14182
SPAIN
A TO Eleclronica S.A.
Plaza Ciudad de Viena no. 6
28040 Madrid
Tel: (I) 234 40 00
TLX: 42477
ISRAEL
Easlronics Lid.
I I Rozanis Sireel
P.O. Box 39300
Tel·Aviv 61392
Tel: 03-475151
TLX: 33638
ITALY
Intesi Corporation Italia S.A.
Milanofiori Palazzo E/5
20090 Assago
Milano
Tel: (02) 82 47 01
TLX: 311351
Tel: (0462) 68 66 66
TLX: 626923
In·SESA
Calle Miguel Angel no. 21-3
28010 Madrid
Tel: (I) 419 09 S7
TLX: 27461
Sevenoaks
Kenl TN14 5EU
Tel: (0732) 45 01 44
TLX: 95142
Rapid Silicon
Rapid House
Denmark SI.
High Wycombe
Bucks HPI I 2ER
Tel: (0494) 44 22 66
TLX: 837931
Rapid Syslems
Rapid House
Denmark SI.
High Wycombe
Bucks HPI I 2ER
Tel: (0494) 45 02 44
TLX: 837931
YUGOSLAVIA
H.R. Microelectronics Corp.
2005 de la Cruz Blvd .. Ste. 223
Sanla Clara, CA 95050
U.S.A.
Tel: (408) 988-0286
TLX: 387452
SWEDEN
Nordisk Eleklronik A.B.
Huvudstagatan 1
P.O. Box 1409
17127 Solna
Tel: (8) 734 97 70
TLX: 10547
SWITZERLAND
Induslrade A.G.
Hertislrasse 3 I
8304 Wallisellen
Tel: (01) 8 30 50 40
TLX: 56788
CG·'/ 8/88
'
inter
INTERNATIONAL SALES OFFICES
AUSTRALIA
JAPAN
JAPAN (Cont'd)
KOREA
Intel Australia Ply. Ltd.'
sro'itrum Building
Intel Japan K.K.
5-6 Tokodai, Tsukuba-shi
Ibarakl, 300-26
Tel: 029747-8511
TLX: 3656-160
FAX: 029747-8450
~i~b~~e~~~'~isu91 Bldg.
Intel Technology ASia Ltd.
~!~:u~-~£~2~~~wwa 243
Seaul150
Tel: (2) 784-8186
TLX: 29312 INTELKO
FAX: (2) 784-8096
~rg::~~~t~~W~~O~56
i~:(~0~~~-2744
1-2-1 Asahl-machl
FAX: 0462-29-3781
FAX: (2) 923-2632
Intel Japan K.K.'
Daiichi Mitsugl Bldg.
1-8889 Fuchu-cho
BRAZIL
Intel Semicondulores do Brasil LTDA
Av. Paulista. 1159-CJS 404/405
01311 - Sao Paulo - S.P.
T 01: 55-11-287-5899
TLX: 1153146
FAX: 55-11-212-7631
~~~'ll'4~~~6);?tl71183
CHINA
~:I:a8i!.!'2~22~~kYO 154
Intel PRC Corporation
15/F. Office 1, Citic Bldg.
Jian Guo Men Wal Street
FAX: 03-427-7620
FAX: 0423-60-0315
Intel Japan K.K.'
Flower-HIli Shln-machi Bldg.
1-23-9 Shinmachl
Intel Japan K.K.'
Ryokuchi-Ekl Bldg.
2-4-1 Terauchi
T0r,0naka-shl, Osaka 560
m~~~g~:lgijl
Intel Japan K.K.
Shinmaru Bldg.
1·5·1 Marunouchi
Chiyoda-ku, Tokyo 100
Tel: 03-201-3621
FAX: 03-201-6850
Intel Japan K.K.
~:NT1~' to~~850
;~"t~~I~';iekl
Minami
Nakamura-ku, Nagoya-shl
Aichi 450
Tel: 052-561-5181
FAX: 052-561-5317
TLX: 22947 INTEL CN
FAX: (1) 500-2953
HONG KONG
~~~Y~~~O-~~~~~~~~~~'eUngpo-ku
SINGAPORE
\nriN;~~~aro~eR~~~~lm Ltd.
Goldhill Squar.
¥~~~~~:8~\30
TLX: 39921 INTEL
FAX: 250-9256
TAIWAN
Intel Technology (Far East) Ltd.
Taiwan Branch
10/F., No. 205, Tun Hua N. Road
Taipei, R.O.C.
Tel: 886-2-716-9660
TLX: 13159 INTELTWN
FAX: 886-2-717-2455
~1~~~~~:i~~i~~sashi-kOSU9i Bldg.
Intel Semiconductor Ltd.'
1701-3 Connaught Centre
1 Connaught Road
Tel: (5) 844-4555
TWX: 63869 ISLHK HX
FAX: (5) 294-589
915 Shinmaruko, Nakahara-ku
Kawasaki-shi, Kanagawa 211
Tel: 044-733-7011
FAX: 044-733-7010
INTERNATIONAL
DISTRIBUTORS / REPRESENTATIVES
ARGENTINA
CHINA (Cont'd)
JAPAN (Cont'd)
DAFSYSS.R.L.
Chacabuco, 90-4 PISO
106g-Buenos AireEt
Tel: 54-1-334-1871
54-1-34-7726
TLX: 25472
Schmidt & Co. Ltd.
18/F Great Eagle Cenlre
Dia Semicon Systems. Inc.
Wacore 84, 1-37-8 San~enjaya
23 Harbour Road
¥:la8~!.!'8~~ci;86kyo 15
Wanchai, Hong Kong
Tel: 852-5-833-0222
TWX: 74766 SCHMC HX
FAX: 852-5-891-8754
Reycom Electronica S.R.L.
Arcos 3631
1429-Buenos Aires
Tel: 54 (1) 701-4462/66
FAX: 54 (1) 11-1722
TLX: 22122
Micronic Devices
Arun Complex
No. 65 D.V.G. Road
Basavanagudi
~:I~~~I?;~2~~gO~~~
1
TLX: 0845-8332 MD BG IN
Total Electronics
P.M.B.250
9 Harker Street
Burwood, Victoria 3125
Tel: 61-3-288-4044
TLX: AA 31261
Total Electronics
P.O. Box 139
Artamon, N.SW. 2064
Tel: 61-02-438-1855
TLX: 26297
Micronic Devices
No. 515 5th Floor
Swastik Chambers
~~~b~~~~';!lROad
BRAZIL
Tel: 91-52-39-63
TLX: 9531 171447 MDEV IN
Elebra MicroelectroniCS
R. Geraldo Flausino Gomes, 78
9 Andar
04575 - Sao Paulo - S.P.
Tel: 55-11-534-9522
TLX: 1154591 or 1154593BR
FAX: 55-11-534-9637
JAPAN
Asahi Electronics Co. Ltd.
KMM Bldg. 2-14-1 Asano
KOkurakita-ku
Kitakyushu-shi 802
Tel: 093-511-8471
FAX: 093-551-7861
CHILE
DIN Instruments
Suecia 2323
Casilla 6055, Correa 22
Santiago
Tel: 56-2-225-8139
TLX: 440422 RUDY CZ
C. Itoh Techno-Science Co., Ltd.
C. Itoh Bldg., 2-5-1 Kita-Aoyama
~~~ari~:~~7~~~o" 107
FAX: 03-497-4969
CHINA
Auckland 1
Tel: 84-9-501-219, 501-801
TLX: 21570 THERMAL
~e'i~I~.'.l'_~3i_~~~8
Ryoyo Electro Corp.
Konwa Bldg.
1-12-22 Tsukiji
~~I~~t'tt~?Mfl104
FAX: 03-546-5044
Micronic Devices
403, Gagan Deep
12, Rajendra Place
New Deihl 110 008
Tel: 91-58-97-71
TLX: 03163235 MONO IN
Northrup Instruments & Systems Ltd.
~561~g:~~~~ rfeO:~arket
Northrup Inslruments & Systems Ltd.
P.O. Box 2406
INDIA
AUSTRALIA
~1~r~,p2g~~~~~f~;:;r~~~~I~;'"
FAX: 03-487-8088
NEW ZEALAND
KOREA
J-T ek Corporation
6th Floor, Government Pension Bldg.
~~:n~~~duO~~~;~u
Seoul 150
Tel: 82-2-782-8039
TLX: 25299 KODIGIT
FAX: 82-2-784-8391
Sam sung Semiconductor &
Telecommunications Co., ltd.
150, 2-KA, Tafpyung-ro, Chung-ku
Seoul 100
Tel: 82-2-751-3987
TLX: 27970 KORSST
FAX: 82-2-753-0967
MEXICO
Dicopel SA
Tochtli 368 Frace. Ind. San Antonio
Azcapotzalco
C.P. 02760-Mexico, D.F.
Tel: 52-5-561-3211
TLX: 1773790 DICOME
TLX: NZ3380
FAX: 64-4-857276
SINGAPORE
Francotone Electronics Pte ltd.
17 Harvey Road #04-01
Singapore 1336
Tel: 283-0888, 289-1618
TWX: 56541 FRELS
FAX: 2895327
SOUTH AFRICA
Electronic Building Elements, Ply. Ltd.
P.O. Box 4609
Pine Square, 18th Street
Hazelwood, Pretoria 0001
Tel: 27·12-469921
TLX: 3·227786 SA
TAIWAN
Mitac Corporation
~~i~?5R~i.~ Shen East Rd.
Tel: 886-2-501-8231
FAX: 886-2-501-4265
VENEZUELA
P. Benavides S.A.
Avilanes a Rio
Residencia Kamarata
Locales 4 AL 7
La Candelaria, Caracas
Tel: 58·2-571-0396
TLX: 28450
FAX: 58-2-572-3321
Ltd.
Phase 1, 26 Kwai Hei Street
N.T" Kowloon
~~~~5~~g?223-222
TWX: 39114 JINMI HX
FAX: 852-0-261-602
'Field Application Location
CG-l/18/88
intJ
DOMESTIC SERVICE OFFICES
ALABAMA
CONNECTICUT
MICHIGAN
PENNSYLVANIA
Intel Corp.
5015 Bradford Drive, #2
Huntsville 35605
Tel: (205) 630-4010
Intel Corp.
26 Mill Plain Road
Danbury 06611
Tel: (203) 746-3130
TWX: 710-456-1199
Intel Corp.
7071 Orchard Lake Aoad
Suite 100
West Bloomfield 46322
Tel: 1313) 651-6096
Intel Corp.
201 Penn Center Boulevard
Suite 301 W -
FLORIDA
MISSOURI
TEXAS
Intel Corp.
1500 N.W. 62, Suite 104
FI. Lauderdale 33309
Tel: 1305) 771-0600
TWX: 510-956-9407
Intel Corp.
4203 Earth City Expressway
Suile 143
Earth City 63045
Tel: (314) 291-2015
Intel Corp.
313 E. Anderson Lane
Suite 314
Austin 76752
Tel: (512) 454-3628
TWX: 910-674-1347
ARIZONA
Intel Corp.
11225 N. 26th Dr.
Suite D-214
Phoenix 65029
Tel: (602) 669-4960
Intel Corp.
~~~r~' Ji'ltaB~~d63~uite M-15
Tel: (602) 459-5010
ARKANSAS
Intel Corp.
P.O. Box 206
Ulm 72170
Tel: (501) 241-3264
CALIFORNIA
Intel Corp.
5650 T.G. Lee Blvd.
Suite 340
Orlando 32622
~~~~~~~-~!~~~
GEORGIA
Intel Corp.
3260 Pointe Parkway
Suite 200
Norcross 30092
Tel: (404) 449-0541
NEW JERSEY
Intel Corp.
365 Sylvan Avenue
Englewood Cliffs 07632
Tel: 1201) 567-0621
TWX: 710-991-6593
Inlel Corp.
Aaritan Plaza III
Raritan Center
Edison 06617
Tel: 1201) 225-3000
Intel Corp.
21515 Vanowen St.
Suite 116
ILLINOIS
NORTH CAROLINA
~:r,~f6j%~~6Vgg
Intel Corp.
300 N. Martingale Ad.
Suite 300
Intel Corp.
2250 E. Imperial Highway
Suite 216
~;~(~~2~3'po~gm
InlelCorp.
2306 W. Meadowview Aoad
Suite 206
Greensboro 27407
Tel: (919) 294-1541
~~~(~lu3)d~5~l6.io
Intel Corp.
~~Ps~~~i~t3~~~5~~'
INDIANA
Intel Corp.
6777 Purdue Rd., # 125
IndianapOlis 46266
Tel: 1317) 675-0623
KANSAS
Intel Corp.
San Tomas 4
2700 San Tomas Expressway
Santa Clara 95051
Tel: 1408) 966-6066
Intel Corp.
6400 W. 11 Oth Street
Suite 170
Overland Park 66210
Tel: (913) 345-2727
KENTUCKY
Intel Corp.
3525 Talescreek Aoad, #51
~:~i(~J~) 2j°i-~~45
MARYLAND
Suite 105
~:r, ~ile~04~~~tJ60
COLORADO
Intel Corp.
650 South Cherry 51.
Suite 915
Denver 60222
Tel: 1303) 321-8066
TWX: 910-931-2269
~:~~~;~1~:~~~~
Intel Corp.
8615 Dyer St" Suite 225
EI Paso 79904
Tel: (915)751-0166
Intel Corp.
5th Floor
7633 Walker Drive
Greenbelt 20770
Tel: (301) 441-1020
MASSACHUSETTS
Intel Corp.
1504 Santa Aosa Ad.
Suite 106
Aichmond 23286
Tel: (804) 262-5666
WASHINGTON
Inlel Corp.
2700 Wycliff Ad" Suite 102
~:II:e(~~9r7~~~6022
OHIO
Intel Corp.
110 IIOth Avenue N.E.
Suite 510
Bellevue 98004
Tel: 1-600-466-3546
TWX: 910-443-3002
Intel Corp.
~~i~~r3~:rainard Bldg.
WISCONSIN
f~~~~la~~a2lf2~oulevard
Intel Corp.
330 S. Executive Dr.
Suite 102
Brookfield 53005
Tel: 1414) 764-8087
Tel: 1216) 464-6915
TWX: 610-427-9296
Inlel Corp.
6500 Poe
Dayton 45414
Tel: 1513) 690-5350
CANADA
OREGON
Intel Semiconductor of Canada, Ltd.
190 Attwell Drive, Suite 500
Inlel Corp.
15254 N.w. Greenbrier Parkway, Bldg. B
Beaverton 97006
Tel: (503) 645-6051
TWX: 910-467-6741
Intel Semiconductor of Canada, Ltd.
620 51. John Blvd,'
~~~~~Ef.'
Canada H9A 3K2
Tel: (514) 694-9130
Intel Corp.
4350 Executive Drive
Intel Corp.
12000 Ford Aoad
Suite 400
Dalla. 75234
VIRGINIA
Tel: 1916) 351-6143
Intel Corp.
2000 E. 4th Street
Suite 110
Santa Ana 92705
Tel: 1714) 635-5769
TWX: 910-595-2475
~~:s~~r~M~~~~40
Elam Young Parkway
Hillsboro 97123
Tel: 1503) 661-6080
Intel Corp.
West10rd Corp. Center
3 Carlisle Road
Weslford 01866
Tel: 1617) 692-3222
Rexdale, Ontario
Canada M9W 6H8
Tel: (416) 675-2105
Pointe Claire, Quebec
Intel Semiconductor of Canada, Ltd.
2650 Queensview Drive
Suite 250
Ottawa, Ontario.
Canada K2B 6H6
Tel: (613) 829-9714
CUSTOMER TRAINING CENTERS
CALIFORNIA
ILLINOIS
MASSACHUSETTS
MARYLAND
2700 San Tomas Expressway
Santa Clara 95051
Tel: (406) 970-1700
~~~a~~~~n~3\~roO
3 Carlisle Aoad
Westford 01886
Tel: 1617) 692-1000
7833 Walker Dr., 4th Floor
Greenbelt 20770
Tel: 1301) 220-3380
Tel: (312) 310-5700
SYSTEMS ENGINEERING OFFICES
CALIFORNIA
ILLINOIS
NEW YORK
2700 San Tomas Expressway
Santa Clara 95051
Tel: (406) 986-6086
~~~~~~~7in~3\~l300
300 Motor Par1
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