Jetson TX2/TX2i OEM Product Design Guide TX2 TX2i 20180618
Nvidia_TX2_design_guide
User Manual:
Open the PDF directly: View PDF 
.
Page Count: 103
| Download | |
| Open PDF In Browser | View PDF |
OEM PRODUCT DESIGN GUIDE
NVIDIA Jetson TX2/TX2i
Abstract
This document contains recommendations and guidelines for Engineers to follow to create a product that is optimized
to achieve the best performance from the common interfaces supported by the NVIDIA ® Jetson™ TX2/TX2i Systemon-Module (SOM).
This document provides detailed information on the capabilities of the hardw are module, w hich may differ from
supported configurations by provided softw are. Refer to softw are release documentation for information on supported
capabilities.
Notes:
Jetson TX2 & Jetson TX2i modules utilize Tegra X2 which is a Parker series SoC.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
1
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Document Change History
Date
Description
MAY , 2017
Initial Release
SEP, 2017
Power
Added pull-up mention for CARRIER_PWR_ON and updated for RESET_OUT# & SLEEP# in Power &
-
Sy stem Pin Descriptions (Table 5 & Table 90 in Appendix)
Updated Power Block diagram to show pull-ups on CARRIER_PWR_ON, POWER_BTN# & SLEEP# and
added Auto-power-on block & pull-up for CHARGER_PRSNT#
Added Deep Sleep (SC7) sequence
USB 3.0
Added Electrical Spec section
Updated impedance
Added Trace Spacing f or TX/RX non-interleaving section
PCIe
Remov ed note under routing guidelines table related to max trace length as this was intended for chi-down
designs, not module based designs.
PCIe/SATA/HDMI
Remov ed min spacing between turn requirement from Serpentine section
DSI/CSI guidelines
Updated max frequency to include separate max speeds for DSI & CSI
Updated ref erence plane
Updated breakout impedance
Updated main impedance
Updated max trace delay to include different lengths for 1.0, 1.5 & 2.5 Gbps
HDMI
Added pre HDMI 1.4b max length/delay requirements
I2C
Updated notes under I2C signal Connections table to use E_IO_HV, not E_OD_HV.
UART
Updated UART Connections figure to add strapping information and added caution note below f igure
Debug
Remov ed external pull-up on JTAG_GP0 (JTAG_TRST_N)
Strapping
Updated f igure, table & notes to remove mention of RAM_CODE[3:2] straps.
Pads
Updated Schmitt Trigger Usage section to add caution when considering changing settings
Checklist
Corrected on-module termination for CHARGER_PRSNT# & added RESET_OUT#
Added check for using pins associated with Tegra straps
FEB, 2018
General
Updated to include Jetson TX2i where appropriate
Added SDIO pins which are supported by TX2i
Updated text/figures to indicate WLAN/BT available on TX2 only
Power
Added separate VDD_IN voltage range for TX2i
Added note under “Main Power Source/Supply Connections” figure that ground must make contact before
power when apply ing main power supply.
Updated power section to include differences for TX2i
Added separate Auto-Power-On support sections for TX2 & TX2i
USB/PCIe/SATA
Swapped order of lane mapping tables to have the "compatible" table first & modified text/notes to match
HDMI
Updated HDMI connection figure to have correct lane connections in connector block
Added notes/table entries indicating only a single CEC controller is available
Audio
Added DMIC guidelines
Strapping
Updated note #6 below strapping table
JUN, 2018
General
Remov ed Jetson TX1 mention in document except note in USB, PCIe & SATA section refering to the Jetson
TX1/TX2 Comparison & Migration AN for differences in lane mapping support.
Abstract
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
2
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Date
Description
-
Added paragraph related to potential differences between hardware capabilities and support in released
sof tware.
References
Added Jetson TX2/TX2i & Jetson TX1/TX2 Comparison & Migration App Notes.
Power
Updated to to add separate Power-Up sequence figures and timing tables for Power-button cases & Auto-
power-on cases & note on differences between TX2i in P2597_B04 v s C02.
Updated Auto-power-on section to remove alternate external solutions (kept mechanisms built-in to TX2 &
TX2i modules).
USB 3.0
Added USB 2.0/3.0 dual-rolw (host/device) connection example.
Updated Insertion Loss & max trace length guidelines to include device mode.
Updated minimum AC cap value.
Ethernet
Updated Magnetics connections figure to show individual caps to GND on CT inputs of magnetics device.
HDMI/DP
Updated eDP/DP connection example figure to show only Tegra & Module pin names in Tegra block .
Updated HDMI connection example figure to correctly align CLK/Data from Tegra to Connector & to show
only Tegra & Module pin names in Tegra block.
CSI
-
Updated intro paragraph to indicate 3 quad or 6 dual lane cameras possible & added reference to
conf iguration table
WLAN/BT
Updated Mating Antenna connector requirement to include both I -PEX & Hirose options.
Strapping
Updated Power-on Strapping Breakdown table to show pull-up on module for Tegra RAM_CODE pins may
be present or not installed.
Pads
Updated "Module Pins Pulled High on the Module Prior to CARRIER_PWR_ON Active" table to correct pullup on module f or RESET_OUT# pin.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
3
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table of Contents
1.0 INT RODUCTION.............................................................................................................................................................................6
1.1 References ...............................................................................................................................................................................6
1.2 Abbreviations and Definitions ..............................................................................................................................................6
2.0 JET SON TX2/TX2I ..........................................................................................................................................................................7
2.1 Overview...................................................................................................................................................................................7
3.0 POWER ...........................................................................................................................................................................................9
3.1 Supply Allocation ..................................................................................................................................................................10
3.2 Main Pow er Sources/Supplies ............................................................................................................................................11
3.3 Pow er Sequencing ................................................................................................................................................................11
3.4 Pow er Discharge ...................................................................................................................................................................15
3.5 Module Pow er-on Type Detection & Control ....................................................................................................................15
3.6 Pow er & Voltage Monitoring ...............................................................................................................................................17
3.7 Deep Sleep (SC7) ..................................................................................................................................................................18
3.8 Optional Auto-Power-On Support ......................................................................................................................................19
4.0 GENERAL ROUTING GUIDEL INES...........................................................................................................................................21
5.0 USB, PCIE & SATA ......................................................................................................................................................................23
5.1 USB .........................................................................................................................................................................................25
5.2 PCIe .........................................................................................................................................................................................30
5.3 SATA .......................................................................................................................................................................................33
6.0 GIGABIT ET HERNET ...................................................................................................................................................................36
7.0 DISPLAY .......................................................................................................................................................................................38
7.1 MIPI DSI ..................................................................................................................................................................................38
7.2 eDP / DP / HDMI .....................................................................................................................................................................41
8.0 MIPI CSI (VIDEO INPUT) .............................................................................................................................................................51
9.0 SDIO/SDCARD/EMMC.................................................................................................................................................................55
9.1 SD Card...................................................................................................................................................................................55
10.0 AUDIO .........................................................................................................................................................................................58
11.0 WLAN / BT (INT EGRAT ED) – JET SON TX2 ONL Y ...............................................................................................................61
12.0 MISCELLANEOUS I NT ERFACES............................................................................................................................................63
12.1 I2C .........................................................................................................................................................................................63
12.2 SPI .........................................................................................................................................................................................65
12.3 UART .....................................................................................................................................................................................67
12.4 Fan .........................................................................................................................................................................................69
12.5 CAN .......................................................................................................................................................................................69
12.6 Debug....................................................................................................................................................................................71
12.7 Strapping Pins .....................................................................................................................................................................72
13.0 PADS ...........................................................................................................................................................................................75
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
4
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
13.1 MPIO Pad Behavior w hen Associated Powe r Rail is Enabled .....................................................................................75
13.2 Internal Pull-ups for CZ Type Pins at Power-on.............................................................................................................75
13.3 Schm itt Trigger Usage .......................................................................................................................................................75
13.4 Pins Pulled/Driven High During Pow er -on......................................................................................................................75
13.5 Pad Drive Strength..............................................................................................................................................................76
14.0 UNUSED INT ERFAC E T ERMINATIONS .................................................................................................................................77
14.1 Unused MPIO Interfaces ....................................................................................................................................................77
14.2 Unused SFIO Interface Pins ..............................................................................................................................................77
15.0 DESIGN CHECKLIST ................................................................................................................................................................78
16.0 APPENDIX A: GENERAL LAYOUT GUIDELI NES ................................................................................................................86
16.1 Overview...............................................................................................................................................................................86
16.2 Via Guidelines .....................................................................................................................................................................86
16.3 Connecting Vias ..................................................................................................................................................................87
16.4 Trace Guidelines .................................................................................................................................................................87
17.0 APPENDIX B: STACK- UPS .....................................................................................................................................................89
17.1 Reference Design Stack -Ups ............................................................................................................................................89
18.0 APPENDIX C: T RA NSMISSION LINE PRIMER ......................................................................................................................90
18.1 Background .........................................................................................................................................................................90
18.2 Physical Transm ission Line Types ..................................................................................................................................90
18.3 Driver Characteristics ........................................................................................................................................................91
18.4 Receiver Characteristics....................................................................................................................................................91
18.5 Transm ission Lines & Reference Planes ........................................................................................................................91
19.0 APPENDIX D: DESIGN GUIDELINE GL OSSARY .................................................................................................................94
20.0 APPENDIX E: JETSON T X2/TX2I PIN DESCRI PTIONS .......................................................................................................95
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
5
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
1.0 INTRODUCTION
1.1 References
Refer to the documents or models listed in Table 1 for more information. Use the latest revision of all documents at all times.
Table 1. List of Related Documents
Document
Jetson TX2/TX2i Module Data Sheet
Park er Series SoC Technical Reference Manual
Jetson TX1/TX2 Dev eloper Kit Carrier Board Specification
Jetson TX2i Module Pinmux
Jetson TX2 and Jetson TX2i Comparison and Migration Application Note
Jetson TX1 and Jetson TX2 Comparison and Migration Application Note
Jetson TX2i Thermal Design Guide
Jetson TX2 Dev eloper Kit Carrier Board Design Files (P2597_B04)
Jetson TX2 Dev eloper Kit Carrier Board BOM (P2597_B04)
Jetson Dev eloper Kit Camera Module Design Files
Jetson TX1/TX2/TX2i Supported Component List
1.2 Abbreviations and Definitions
Table 2 lists abbreviations that may be used throughout this document and their definitions.
Table 2. Abbreviations and Definitions
Abbreviation
BT
CEC
CAN
DP
eDP
eMMC
GPS
HDMI
I2C
I2S
LCD
LDO
LPDDR4
PCIe (PEX)
PCM
PHY
PMC
PMIC
RF
RTC
SATA
SDIO
SPI
UART
USB
WLAN
Definition
Bluetooth
Consumer Electronic Control
Controller Area Network
Display Port
Embedded Display Port
Embedded MMC
Global Positioning System
High Definition Multimedia Interface
Inter IC
Inter IC Sound Interface
Liquid Crystal Display
Low Dropout (voltage regulator)
Low Power Double Data Rate DRAM, Fourth-generation
Peripheral Component Interconnect Express interface
Pulse Code Modulation
Physical Interface (i.e. USB PHY)
Power Management Controller
Power Management IC
Radio Frequency
Real Time Clock
Serial “AT” Attachment interface
Secure Digital I/O Interface
Serial Peripheral Interface
Universal Asynchronous Receiver-Transmitter
Universal Serial Bus
Wireless Local Area Network
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
6
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
2.0 JETSON TX2/TX2i
2.1 Overview
The Jetson TX2/TX2i module resides at the center of the embedded system solution and includes:
1.
3.
5.
7.
Power (PMIC/Regulators, etc.)
DRAM (LPDDR4)
eMMC
Connects to WLA N and Bluetooth enabled dev ices (TX2 only )
2.
4.
6.
Ethernet PHY
Power & Voltage Monitors
Thermal Sensor
In addition, a range of interfaces are available at the main connector for use on the carrier board as show n in the follow ing table.
Table 3. Jetson TX2/TX2i Interfaces
Catagory
Function
Catagory
Function
SATA
USB 2.0 (3x)
USB 3.0 (up to 3x) see note
Control [x3] (shared Wake)
PCIe (3 root ports - See note)
SATA & Device Sleep control
LAN
CAN
I2C
UART
SPI
Camera
CSI (6 x2 or 3 x4), Control, Clock
WLAN/BT/Modem
2x eDP/DP/HDMI
DSI (2 x4), Display/Backlight Control
I2S (4x), Control & Clock
Digital Mic & Speaker
SD Card or SDIO
SD Card or SDIO (Jetson TX2i only)
Touch
Sensor
Fan
Debug
System
Power
Gigabit Ethernet
2x
8x
5x
3x
PEX/UART/I2S, Control/handshake
(external only solution for TX2i)
Touch Clock, Interrupt & Reset
Control & Interrupt
FAN PWM & Tach Input
JTAG, UART
Power Control, Reset, Alerts
Main Input
USB
PCIe
Display
Audio
SD Card
SDIO
Note:
Some USB 3.0 or PCIe instances are shared. Refer to Chapter 5.0 USB, PCIe & SATA for details.
Table 4. Jetson TX2/TX2i Connector (8x50) Pin Out Matrix
B
C
VDD_IN
VDD_IN
VDD_IN
VDD_IN
GND
GND
GND
GND
RSVD
RSVD
I2C_PM_DAT
I2C_CAM_CLK
CARRIER_STBY#
BATLOW#
GPIO14_AP_WAKE_MDM VIN_PWR_BAD#
BATT_OC
GPIO15_AP2MDM_ GPIO17_MDM2AP_
9
WDT_TIME_OUT#
READY
READY
GPIO16_MDM_
GPIO18_MDM_COL
10
I2C_GP2_DAT
WAKE_AP
DBOOT
11 JTAG_GP1
JTAG_TCK
I2C_GP2_CLK
1
2
3
4
5
6
7
8
A
VDD_IN
VDD_IN
GND
GND
RSVD
I2C_PM_CLK
CHARGING#
D
E
FORCE_RECOV#
SLEEP#
SPI0_CLK
SPI0_MISO
UART7_RX
I2S3_SDIN
I2C_CAM_DAT
I2S3_CLK
GPIO5_CAM_FLASH_EN CAM2_MCLK
CAM_VSYNC
UART7_TX
F
AUDIO_MCLK
GPIO19_AUD_RST
SPI0_CS0#
SPI0_MOSI
I2S3_LRCLK
I2S3_SDOUT
CAM1_MCLK
H
I2S0_LRCLK
I2S0_SDOUT
GPIO20_AUD_INT
DSPK_OUT_DAT
I2S2_LRCLK
I2S2_SDOUT
GPIO4_CAM_STROBE GPIO3_CAM1_RST#
GPIO0_CAM0_PWR# GPIO2_CAM0_RST#
UART1_TX
UART1_RTS#
CAM0_MCLK
UART3_CTS#
UART3_RX
UART1_RX
UART1_CTS#
UART3_TX
RSVD
GND
RSVD
UART3_RTS#
RSVD
UART0_RTS#
UART0_CTS#
RSVD
RSVD
RSVD
RSVD
GPIO1_CAM1_PWR#
G
I2S0_SDIN
I2S0_CLK
GND
DSPK_OUT_CLK
I2S2_CLK
I2S2_SDIN
12 JTAG_TMS
13 JTAG_TDO
JTAG_TDI
JTAG_GP0
I2C_GP3_CLK
I2C_GP3_DAT
RSVD
I2S1_LRCLK
RSVD
RSVD
RSVD
SPI1_MOSI
UART0_RX
SPI1_CLK
UART0_TX
14 JTAG_RTCK
I2S1_SDIN
I2S1_SDOUT
SPI1_CS0#
SPI1_MISO
GPIO9_MOTION_INT
SPI2_CLK
15 UART2_CTS#
16 UART2_RTS#
GND
UART2_RX
UART2_TX
I2S1_CLK
FAN_PWM
I2C_GP0_DAT
I2C_GP0_CLK
AO_DMIC_IN_DAT AO_DMIC_IN_CLK
GND
SPI2_CS1#
SPI2_MOSI
SPI2_CS0#
SPI2_MISO
SDCARD_PWR_EN
17 USB0_EN_OC#
18 USB1_EN_OC#
FAN_TACH
RSVD
CAN1_STBY
CAN1_TX
CAN1_RX
CAN0_RX
RSVD
CAN0_ERR
SDCARD_CD#
SDCARD_D3
GND
SDCARD_CLK
SDCARD_D1
SDCARD_D0
19 RSVD
20 I2C_GP1_DAT
21 I2C_GP1_CLK
GPIO11_AP_WAKE_BT CAN1_ERR
CAN0_TX
GND
CSI5_D1-
SDCARD_D2
SDCARD_WP
SDCARD_CMD
GND
CSI4_D1-
CSI5_D1+
GND
GND
CSI4_CLK-
22 GPIO_EXP1_INT
23 GPIO_EXP0_INT
GPIO13_BT_WAKE_AP CSI5_D0-
GND
CSI3_D1-
CSI4_D0CSI4_D0+
CSI4_CLK+
GND
GPIO10_WIFI_WAKE_AP
CAN_WAKE
GPIO12_BT_EN
GND
GPIO7_TOUCH_RST CSI5_D0+
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
GND
CSI5_CLKCSI5_CLK+
GND
GPIO8_ALS_PROX_INT
CSI4_D1+
GND
CSI2_D1-
7
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A
LCD1_BKLT_PWM
LCD_TE
GSYNC_HSYNC
GSYNC_VSYNC
GND
SDIO_RST#
SDIO_D3
SDIO_D2
SDIO_D1
DP1_HPD
DP1_AUX_CHDP1_AUX_CH+
USB0_OTG_ID
GND
USB1_D+
USB1_D–
GND
PEX2_REFCLK+
PEX2_REFCLK–
GND
PEX0_REFCLK+
PEX0_REFCLK–
RESET_OUT#
RESET_IN#
CARRIER_PWR_ON
CHARGER_PRSNT#
VDD_RTC
Ground
Legend
Notes:
1.
2.
B
TOUCH_CLK
GPIO6_TOUCH_INT
LCD_VDD_EN
LCD0_BKLT_PWM
LCD_BKLT_EN
SDIO_CMD
SDIO_CLK
GND
SDIO_D0
HDMI_CEC
DP0_AUX_CHDP0_AUX_CH+
DP0_HPD
USB0_VBUS_DET
GND
USB0_D+
USB0_DGND
USB2_D+
USB2_DGND
PEX1_REFCLK+
PEX1_REFCLKGND
SYS_WAKE#
MOD_PWR_CFG_ID
POWER_BTN#
Power
C
GND
CSI3_D0CSI3_D0+
GND
CSI1_D0CSI1_D0+
GND
DSI3_D0+
DSI3_D0GND
DSI1_D0+
DSI1_D0GND
DP1_TX1DP1_TX1+
GND
PEX2_TX+
PEX2_TXGND
USB_SS0_TX+
USB_SS0_TXGND
PEX2_CLKREQ#
PEX1_CLKREQ#
PEX0_CLKREQ#
PEX0_RST#
RSVD
D
CSI3_CLKCSI3_CLK+
GND
CSI1_CLKCSI1_CLK+
GND
DSI3_CLK+
DSI3_CLK–
GND
DSI1_CLK+
DSI1_CLK–
GND
DP1_TX2DP1_TX2+
GND
PEX_RFU_TX+
PEX_RFU_TXGND
USB_SS1_TX+
USB_SS1_TXGND
SATA_TX+
SATA_TXSATA_DEV_SLP
PEX_WAKE#
PEX2_RST#
RSVD
E
CSI3_D1+
GND
CSI1_D1CSI1_D1+
GND
DSI3_D1+
DSI3_D1GND
DSI1_D1+
DSI1_D1GND
DP1_TX3DP1_TX3+
GND
DP1_TX0DP1_TX0+
GND
PEX1_TX+
PEX1_TXGND
PEX0_TX+
PEX0_TXGND
GBE_LINK_ACT#
GBE_MDI0+
GBE_MDI0PEX1_RST#
RSVD on Jetson TX2 (available on TX2i)
F
GND
CSI2_D0CSI2_D0+
GND
CSI0_D0CSI0_D0+
GND
DSI2_D0+
DSI2_D0GND
DSI0_D0+
DSI0_D0GND
DP0_TX1DP0_TX1+
GND
PEX2_RX+
PEX2_RXGND
USB_SS0_RX+
USB_SS0_RXGND
GBE_LINK1000#
GBE_MDI1+
GBE_MDI1GND
GBE_LINK100#
Reserved
G
CSI2_CLKCSI2_CLK+
GND
CSI0_CLKCSI0_CLK+
GND
DSI2_CLK+
DSI2_CLKGND
DSI0_CLK+
DSI0_CLKGND
DP0_TX2DP0_TX2+
GND
PEX_RFU_RX+
PEX_RFU_RXGND
USB_SS1_RX+
USB_SS1_RXGND
SATA_RX+
SATA_RXGND
GBE_MDI2+
GBE_MDI2GND
H
CSI2_D1+
GND
CSI0_D1CSI0_D1+
GND
DSI2_D1+
DSI2_D1GND
DSI0_D1+
DSI0_D1GND
DP0_TX3DP0_TX3+
GND
DP0_TX0DP0_TX0+
GND
PEX1_RX+
PEX1_RXGND
PEX0_RX+
PEX0_RXGND
GBE_MDI3+
GBE_MDI3GND
RSVD
Redefined for Jetson TX2i
RSVD (Reserv ed) pins must be left unconnected.
Signals starting with “GPIO_” are standard GPIOs that hav e been assigned recommended usage. If the assigned usage is
required in a design, it is recommended the matching GPIO be used. If the assigned usage is n ot required, the pins may be
used as GPIOs for other purposes.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
8
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
3.0 POWER
Caution
Jetson TX2/TX2i is not hot-pluggable. Before installing or removing the module, the main power
supply (to VDD_IN pins) must be disconnected and adequate time (recommended > 1 minute) must
be allowed for the various power rails to fully discharge.
Table 5. Jetson TX2/TX2i Power & System Pin Descriptions
Pin # Module Pin Name
A1
A2
B1
B2
C1
C2
C7
VDD_IN
VDD_IN
VDD_IN
VDD_IN
VDD_IN
VDD_IN
BATLOW#
A48
CARRIER_PWR_ON
B7
CARRIER_STBY#
A49
CHARGER_PRSNT#
A7
C16
B17
E1
CHARGING#
FAN_PWM
FAN_TACH
FORCE_RECOV#
B50
POWER_BTN#
A47
RESET_IN#
A46
RESET_OUT#
Tegra Signal
Usage/Description
Usage on the
Carrier Board
Direction
Pin Type
−
Main power – Supplies PMIC & external supplies
Main DC input
Input
5.5V-19.6V (TX2)
9.0V – 19.0V (TX2i)
(See note 1)
Input
CMOS – 1.8V
Output
Open-Collector – 3.3V
Output
CMOS – 1.8V
Input
MBATT level – 5.0V
(see note 2)
Input
Output
Input
Input
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Input
CMOS – 5.0V
(see note 2)
Bidir
Open Drain, 1.8V
Bidir
CMOS – 1.8V
Input
CMOS – 1.8V
(see note 2)
Input
CMOS – 5.0V
Input
CMOS – 1.8V
Bidir
1.65V-5.5V
Bidir
Input
CMOS – 1.8V
CMOS – 1.8V
Output
VDD_IN level
(PMIC_GPIO6)
Battery Low (PMIC GPIO)
Carrier Power On. Used as part of the power up sequence.
The module asserts this signal when it is safe for the carrier
−
board to power up. A 10kΩ pull-up to VDD_3V3_SYS is
present on the module.
Carrier Board Standby: The module drives this signal low
SOC_PWR_REQ
when it is in the standby power state.
System
Charger Present. Connected on module to PMIC ACOK
through FET & 4.7kΩ resistor. PMIC ACOK has 100kΩ pull-up
internally to MBATT (VDD_5V0_SYS). Can optionally be used
(PMIC ACOK)
to support auto-power-on where the module platform will
power-on when the main power source is connected instead
of waiting for a power button press.
(PMIC GPIO5)
Charger Interrupt
GPIO_SEN6
Fan PWM
Fan
UART5_TX
Fan Tachometer
GPIO_SW1
Force Recovery strap pin
Power Button. Used to initiate a system power-on.
Connected to PMIC EN0 which has internal 10KΩ Pull-up to
POWER_ON / (PMIC
VDD_5V0_SYS. Also connected to Tegra POWER_ON pin
EN0)
through Diode with 100kΩ pull-up to VDD_1V8_AP near
Tegra.
Reset In. System Reset driven from PMIC to carrier board for
devices requiring full system reset. Also driven from carrier
(PMIC NRST_IO)
board to initiate full system reset (i.e. RESET button). A pull- System
up is present on module.
Reset Out. Reset from PMIC (through diodes) to Tegra &
eMMC reset pins. Driven from carrier board to force reset of
Tegra & eMMC (not PMIC). An external 100kΩ pull-up to
SYS_RESET_N
1.8V near Tegra (module pin side) & external 10kΩ
pull-up to 1.8V on the other side of a diode (PMIC
E2
SLEEP#
GPIO_SW2
B8
VIN_PWR_BAD#
−
C9
WDT_TIME_OUT#
GPIO_SEN7
A50
VDD_RTC
(PMIC BBATT)
C8
B48
BATT_OC
SYS_WAKE#
BATT_OC
POWER_ON
B49
MOD_PWR_CFG_ID
−
side).
Sleep Request to the module from the carrier board. An
internal Tegra pull-up is present on the signal.
VDD_IN Power Bad. Carrier board indication to the module
that the VDD_IN power is not valid. Carrier board should deassert this (drive high) only when VDD_IN has reached its
required voltage level and is stable. This prevents Tegra from
powering up until the VDD_IN power is stable.
Watchdog Timeout
Real-Time-Clock. Optionally used to provide back-up power
for RTC. Connects to Lithium Cell or super capacitor on
Carrier Board. PMIC is supply when charging cap or coin cell.
Super cap or coin cell is source when system is disconnected
from power.
Battery Over-current (& Thermal) warning
Power button & SC7 wake interrupt
Module power configuration identification. Tied to GND on
Jetson TX2i. Floating on Jetson TX2. Determines the poweron mechanism used to support both Jetson TX2 & TX2i.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Sleep (VOL
DOWN) button
System
Battery Back-up
using Supercapacitor
Power/SC7 wake
Module power
configuration ID
9
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Note:
1.
2.
Power efficiency is higher when the input voltage is lower, such as 9V or 12V. At very low voltages (close to the 5.5V
minimum [TX2 only], the power supported by some of the supplies may be reduced ).
These pins are handled as Open-Drain on the carrier board.
Figure 1. Power Block Diagram
Jetson TX2/TX2i
PU
VIN_PWR_BAD#
B8
From Carrier Board main
power input & discharge circuit
CARRIER_PWR_ ON
A48
To Carrier Board power subsystem
RESET_IN#
A47
System Reset to/from Carrier Board
RESET_O UT#
A46
Tegra Force Reset from Carrier Board
PU
Power Subsystem
DC
Jack
A1
A2
B1
B2
C1
C2
Super Cap
or Li Cell
(Optional)
A50
PU
VDD_IN
5V/3.3V Pre-Regs
PMU Switchers/LDOs
CPU/GPU Regs
Ext. LDOs
Load Switches
PU
PU
VDD_RTC
Tegra
POWER
PU
POWE R_BTN#
Optional Power Button
B50
ACO K
SLEEP
PU
SLEEP #
PU
Memory/Peripherals
LPDDR4, eMMC,
Ethernet,
WiFi / BT (TX2 only)
CARRIER_STBY #
Auto-poweron Circuit
CHARGER_P RS NT#
Jets on TX 2
MOD_PWR_CFG _ID
Optional Sleep Button
E2
B7
To Carrier Board to disable devices/
rails to be off in sleep mode
A49
Optional signal from Carrier Board
to support Auto-Power-On
B49
To Carrier Board Power-on circuitry
(B49 on Jetson TX2 is RSVD – No Connect)
Jets on TX 2i
3.1 Supply Allocation
Table 6 Internal Power Subsystem Allocation
Power Rails
VDD_5V0_SYS
VDD_CPU
VDD_GPU & VDD_SRAM
VDD_SOC (CORE)
VDD_DDR_1V1_PMIC
AVDD_DSI_CSI_1V2
VDD_1V8
VDD_3V3_SYS
VDDIO_3V3_AOHV
VDDIO_SDMMC1_AP
VDD_RTC (See note)
VDDIO_SDMMC3_AP
VDD_HDMI_1V05
VDD_PEX_1V05
VDD_1V8_AP (&
VDD_1V8_AP_PLL)
Note:
Usage
Supplies various switchers & load switches that power
the various circuits & peripherals on the module
Tegra MCPU/BCPU
Tegra GPU & SRAM
Tegra Core
LPDDR4
Source for some DSI/CSI blocks
Tegra, eMMC, WLAN
Supplies various LDOs & load switches that in turn
power the various circuits & peripherals on the module
Tegra VDDIO_AO_HV rail
Tegra SD Card I/O rail
Tegra Real Time Clock/Always-on Rail
Tegra SDIO rail
Tegra HDMI / DP rail
Tegra PCIe / USB 3.0 / SATA rail
Main 1.8V Tegra rail
(V)
5.0
Power Supply
5V DC-DC
Source
VDD_IN
1.0 (Var)
1.0 (Var)
1.0 (Var)
1.125
1.2
1.8
3.3
OpenVREG (uP1666QQKF)
OpenVREG (uP1666QQKF)
OpenVREG (uP1666QQKF)
PMIC Switcher SD0
PMIC Switcher SD1
PMIC Switcher SD2
PMIC Switcher SD3
VDD_5V0_SYS
VDD_5V0_SYS
VDD_5V0_SYS
VDD_5V0_SYS
VDD_5V0_SYS
VDD_5V0_SYS
VDD_5V0_SYS
3.3
1.8/3.3
1.0 (Var)
1.8/3.3
1.0
1.0
1.8
PMIC LDO 2
PMIC LDO 3
PMIC LDO 4
PMIC LDO 5
PMIC LDO 7
PMIC LDO 8
Load Switch
VDD_5V0_SYS
VDD_5V0_SYS
VDD_1V8
VDD_5V0_SYS
AVDD_DSI_CSI_1V2
AVDD_DSI_CSI_1V2
VDD_1V8
This is the Tegra supply, and should not be confused with the module VDD_RTC pin which is the supply that connects to the
PMIC BBATT pin to keep the Real-Time Clock powered .
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
10
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
3.2 Main Power Sources/Supplies
The figure below show s the pow er connections used on the carrier board, including the DC Jack w hich connects to the AC/DC
adapter, and the main 5.0V, 3.3V and 1.8V supplies. Also show n are the pow er control signals that are used to enable these
supplies, or are used to communicate pow er sequence information to the module or other circuitry on the carrier board (i.e.
discharge circuits).
Figure 2. Main Power Source/Supply Connections
DC Jack
Blue – P2597_B04 Carrier Board
G
VDD_19V_IN (TX2: 5.5V-19.6V)
(TX2i: 9.0V-19.0V)
S
PWR
FET
D
G
S FET D
VIN_PWR_BAD#
VDD_MOD
From On/Off MOD_VIN_EN
Controller
Red – P2597_C02
(TX2/TX2i)
Carrier Board
5V
To Jetson TX2 VDD_IN
S
PWR
G
FET
D
G
S FET D
G
S FET D
To Jetson TX2 & Power
Discharge Circuitry
U31
G
S FET D
TPS53015
DC-DC
VIN
SW
EN
PG
VDD_5V0_IO_SYS
Main Carrier
Board 5V Supply
3V3_SYS_BUCK_EN
From CARRIER_PWR_ON
Jetson TX2
U16
TPS53015
DC-DC
VDD_3V3_SYS
VIN
SW
EN
PG
VDD_3V3_SYS_PG
Main Carrier Board
3.3V Supply
Main 3.3V Power Good –
Routed to Power LED on
Carrier board
1V8_IO_VREG_EN
U9
From Main VDD_5V0_IO_SYS
5V supply
VDD_1V8
APW8805
OpenVReg
VIN
VCC
EN/FS
SW
PGOOD
1V8_IO_PG
RESET_OUT#
Note
-
Main Carrier Board
1.8V Supply
Main 3.3V Power Good –
Routed to Power LED on
Carrier board
To Jetson TX2 (RESET_OUT#)
to keep Tegra in Reset until
1.8V rail Valid
The figure above is a high-level representation of the connections involved. Refer to the latest carrier board
reference design for details.
When connecting the main power, the ground must make connection before the main power rail.
3.3 Power Sequencing
In order to ensure reliable and consistent pow er up sequencing, the pins VIN_PWR_BAD#, CARRIER_PWR_ON, and
RESET_OUT# on the module connector should be connected and used as described below :
VIN_PWR_BA D# signal is generated by the Carrier Board and passed to the module to keep the Tegra processor pow ered off
until the VDD_IN supply is stable and it is possible to pow er up any standby circuits on the module. This signal prevents the
Tegra processor from pow ering up prematurely before the Carrier Board has charged up its decoupling capacitors and pow er to
the module is stable
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
11
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
CARRIER_PWR_ON signal is generated by the module and passed to the Carrier Board to indicate that the module is pow ered
up and that the pow er up sequence for the Carrier Board circuits can begin.
RESET_OUT# is de-asserted by the Carrier Board after a period sufficient to allow the Carrier Board circuits to pow er up.
Figure 3. Power Up Sequence – Power-Button Case (Jetson TX2i in P2597_C02)
1
2
3
4
5
6
7
8
VDD_IN
VIN_PWR_BAD#
POWER_BTN#
Jetson module System Power (Main 1.8V
rail most IF pins are associated with)
CARRIER_PWR_ON
Carrier Board VDD_1V8 (note 1)
RESET_OUT# (note 2)
Note:
1.
2.
3.
The 1.8V supply on the carrier board associated with MPIO pins common to the module must not be enabled unless the
module main 1.8V rail is on. In addition, the carrier board should keep RESET_OUT# lo w until this 1.8V supply is valid.
On the P2597, this is accomplished by connecting the VDD_1V8 supply PGOOD signal to RESET_OUT#.
Inactive when both PMIC Reset is inactive (high) & VDD_1V8 PGOOD is active (high)
During run time if any module I/O rail is switched OFF or ON, the following sequences should be performed. Violating
these sequences will result in extra in-rush current during the rail transition.
OFF Sequence: The associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register must be enabled before the
-
I/O Rail is powered OFF
ON Sequence. After an I/O Rail is powered ON, the associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0
register needs to be cleared to the “disable” state
Table 7. Power Up Sequence Timing Relationships
Timing
t1-2
t2-3
t3-4
t4-5
t4-6
t5-6
t6-7
t6-8
Note:
Parameter
VDD_IN On to POWER_BTN# Pull-up (PMIC) active
VDD_IN On to VIN_PWR_BAD# inactive
VIN_PWR_BAD# inactive to POWER_BTN# active
POWER_BTN# active time
POWER_BTN# active to CARRIER_PWR_ON active
Module System Power On to CARRIER_PWR_ON
CARRIER_PWR_ON active to Carrier Board System Power Enabled
CARRIER_PWR_ON to On-Module PMIC Reset Inactive
RESET_IN# active time
1.
2.
3.
4.
5.
6.
Min
0
50
0
50
Typ
8.8
54
See Notes
38.6
8
6.6
77.4
Max
Units
ms
ms
ms
ms
Notes
1
2
3
3
ms
ms
ms
ms
ms
4
5
6
Measured from VDD_IN ramp start to POWER_BTN# ramp start. Carrier board dependent.
Typical value using NVIDIA P2597, measured from VDD_IN ramp start to VIN_PWR_BAD# inactive start. Carrier board
dependent.
User Dependent if POWER_BTN# connected to button. Otherwise, carrier board dependent.
Typical value measured using NVIDIA P2597. Carrier board dependent
Typical value using P2597. Carrier board dependent.
User Dependent if RESET_IN# connected to button. Otherwise, carrier board dependent. Not shown in Power up
sequence figure.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
12
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 4. Power Up Sequence – Auto-Power-On Case (Jetson TX2i in P2597_B04)
1
2
3
4
5
6
7
8
VDD_IN
VIN_PWR_BAD#
Jetson module System Power (Main 1.8V
rail most IF pins are associated with)
CARRIER_PWR_ON
Carrier Board VDD_1V8 (note 1)
RESET_OUT# (note 2)
Note:
1.
2.
3.
4.
The 1.8V supply on the carrier board associated with MPIO pins common to the module must not be enabled unless the
module main 1.8V rail is on. In addition, the carrier board should keep RESET_OUT# low until this 1.8V supply is valid.
On the P2597, this is accomplished by connecting the VDD_1V8 supply PGOOD signal to RESET_OUT#.
Inactive when both PMIC Reset is inactive (high) & VDD_1V8 PGOOD is active (high)
POWER_BTN# not used for this power-up sequence, but if Jetson TX2i is used in P2597_B04 compatible motherboard,
system will power off if POWER_BTN# is asserted (power-button pressed or equivalent) and power-on sequence will
occur again once POWER_BTN# is de-asserted. This is due to the difference in the PMIC power on signal (edge triggered
on Jetson TX2 PMIC & level sensitive on Jetson TX2i. When Jetson TX2i is used in a P2597_C02 compatible carrier board,
logic on the carrier board simulates edge triggered power-on so the power button will function the same as for Jetson
TX2.
During run time if any module I/O rail is switched OFF or ON, the following sequences should be performed. Violating
these sequences will result in extra in-rush current during the rail transition.
OFF Sequence: The associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register must be enabled before the
-
I/O Rail is powered OFF
ON Sequence. After an I/O Rail is powered ON, the associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0
register needs to be cleared to the “disable” state
Table 8. Power Up Sequence Timing Relationships
Timing
t2-3
t3-4
t5-6
t6-7
t6-8
Note:
Parameter
VDD_IN On to VIN_PWR_BAD# inactive
VIN_PWR_BAD# inactive to CARRIER_PWR_ON active
Module System Power On to CARRIER_PWR_ON
CARRIER_PWR_ON active to Carrier Board System Power Enabled
CARRIER_PWR_ON to On-Module PMIC Reset Inactive
RESET_IN# active time
1.
2.
3.
4.
Min
Typ
54
38.6
8
0
6.6
77.4
50
Max
Units
ms
ms
ms
Notes
1
ms
ms
ms
2
3
4
Typical value using NVIDIA P2597, measured from VDD_IN ramp start to VIN_PWR_BAD# inactive start. Carrier board
dependent.
Typical value measured using NVIDIA P2597. Carrier board dependent
Typical value using P2597. Carrier board dependent.
User Dependent if RESET_IN# connected to button. Otherwise, carrier board dependent. Not shown in P ower up
sequence figure.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
13
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 5. Power Down Sequence (Controlled Case)
1
2
3
4
5
6
7
8
9
RESET_OUT#
CARRIER_PWR_ON
Carrier Board System Power (1.8V
used for pins shared w/Jetson module)
Jetson Module System Power (Main 1.8V
rail most IF pins are associated with)
VIN_PWR_BAD#
VDD_IN
Table 9. Power Down Sequence Timing Relationships (Controlled Case)
Timing
t1-2
t2-3
t2-4
Note:
Parameter
RESET_OUT# active to CARRIER_PWR_ON inactive
CARRIER_PWR_ON inactive to carrier board system power off
Min
Typ
3.76
0.46
CARRIER_PWR_ON inactive to the module System Power (main 1.8V rail) Off
1.
2.
3.
Max
1.24
Units
mS
ms
Notes
1
2
mS
3
Measured from RESET_OUT# active to CARRIER_PWR_ON to inactive ramp down start.
Typical value measured using NVIDIA P2597. Measured from CARRIER_PWR_ON to carrier board VDD_1V8 ramp down
start. Carrier board dependent.
Typical value measured using NVIDIA P2597. Meas ured from CARRIER_PWR_ON ramp down start to the module main
1.8V ramp down start.
Figure 6. Power Down Sequence (Uncontrolled Power Removal Case)
1
2
3
4
5
6
7
8
9
VDD_IN
VIN_PWR_BAD#
RESET_OUT#
CARRIER_PWR_ON
Carrier Board System Power
Jetson Module System Power
Table 10. Power Down Sequence Timing Relationships (Uncontrolled Power Removal Case)
Timing
t1
t2
Parameter
VDD_IN Removed in uncontrolled manner
VIN_PWR_BAD detection “sees” drop in VDD_IN & is
asserted to start uncontrolled power-down sequence.
RESET_OUT# & CARRIER_PWR_ON are driven low via
PMIC sequence soon after. Carrier board power & the
module power begin to ramp down.
Min
Typ
Max
Units
Notes
Carrier board power (mainly 1.8V rail
associated with interface pins connected to
the module) should ramp down faster so it is
off before the module main 1.8V rail is off.
Removal of the VDD_IN/VDD_MUX supply causes VIN_PWR_BAD# to go active w hich causes the module to initiate a
controlled shut dow n. The controlled shut dow n takes ~20ms to complete so the internal PMIC supply needs to stay above
~2.9v for >~20ms. The USB0_OTG_ID pin is a pin w hich can be monitored to see the state of the internal PMIC supply level.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
14
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 7. VIN_PWR_BAD# Detection Test Circuit for Uncontrolled Power -down Case
~20%
droop
VDD_IN
VIN_PWR_BAD#
Voltage measured at
USB0_OTG_ID pin
2.9V
>20ms
3.4 Power Discharge
In order to meet the Pow er Dow n requirements, discharge circuitry is required. In the figure below the DISCHARGE signal is
generated, based on a transition of the CARRIER_POWER_ON signal or the removal of the main supply (VDD_MUX/V DD_IN).
When DISCHARGE is asserted, VDD_5V0_IO_SYS, VDD_3V3_SYS, VDD_1V8 and VDD_3V3_SLP are forced to GND in a
controlled manner. Removal of the VDD_MUX supply also causes VIN_PWR_BAD# to go active w hich causes the module to
initiate a controlled shut dow n.
Figure 8. Power Discharge
VDD_5V0_IO_SYS
VIN_PWR_BAD#
(Jetson Module Pin B8)
100Ω
VDD_MUX
D
MMBT
4403
10kΩ
C
10uF
NTR4003
NT1G
G
VDD_3V3_SY S
47Ω
S
D
10MΩ
0Ω
E
B
0.05Ω Tol.
10kΩ
BAT54ALT1
10uF
D
NTR4001
NT1G
G
NTR4003
NT1G
G
S
D
DISCHARGE
VDD_MUX
NTR4003
NT1G
G
NTR4003
NT1G G
VDD_5V0_IO_SYS
VDD_3V3_SLP
47Ω
S
D
VDD_12V_SLP
D
470Ω
470Ω
S
S
D
75kΩ
CARRIER_PWR_ON
(Jetson Module pin A48)
NTR4003
NT1G
G
100kΩ,1%
1uF
47kΩ
100kΩ,1%
100kΩ,1%
BAT54CW
4.7uF
VDD_1V8
36Ω
S
BAT54CW
NTR4003
NT1G
G
VDD_5V0_IO_SLP
100Ω
S
FDV301N
D
VDD_3V3_SLP
G
S
Note
D
NTR4003
NT1G
G
S
The figure above is based on the carrier board reference design. Refer to the latest carrier board reference design
(P2597_B04 or later) for details.
3.5 Module Power-on Type Detection & Control
The follow ing describes w hat is required in a carrier board design to support Jetson TX2 and Jetson TX2i in a design that
requires a pow er button press to pow er the system on. If a design requires the system to pow er on immediately after the main
pow er supply is connected/enabled, see the “Optional Auto-Pow er-On Support” section.
Jetson TX2i uses a different PMIC (MAX20024) than Jetson TX2 (MAX77620). Due to the PMIC architecture differences, if the
platform requires a button press, the Pow er-on mechanism w ill need to change, from Edge to level triggered. This w ill require
the carrier boards to detect w hether a Jetson TX2 module or Jetson TX2i module is installed. A Reserved pin on the connector
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
15
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
w hich is floating on Jetson TX2 w ill be grounded on the Jetson TX2i as a means to differentiate betw een the tw o module types.
The module pow er configuration identification pin ( MOD_PWR_CFG_ID) resides on the Module Pin B49.
The updated carrier board, designed to support Jetson TX2i as w ell as Jetson TX2 w ill include logic that w ill use the state of the
MOD_PWR_CFG_ID pin to determine how the POWER_BTN# signal is handled. If the pin is pulled dow n due to a Jetson TX2i
module being installed, the POWER_BTN# pin w ill be driven to a steady high (ON) or low (OFF) state. If the pin is floating as
w ould be the case if a Jetson TX2 module is installed, a momentary pulse w ill be generated on the POWER_BTN# pin of the
module to initiate a pow er-on of the module. With either module type, if the system is already pow ered, a short press of the
pow er button w ill put the system in sleep mode (softw are dependent) if the system is “aw ake,” w ake the system if in sleep mod e,
or cause a force pow er-off if the Pow er-on button is held low for approximately 8 to 10 seconds.
Figure 9. Power-on Type Detection & Control
VDD_19V_IN
TPS7A1650
IN
EN
VDD_19V_IN
From Module MOD_PWR_CFG_ID
Strap (Pin B49)
From Power POWER_BTN
Button
FB_NC
TPAD
GND
D
G FET
S
D
G FET
S
5V0_AO
From Module CARRIER_PWR_ON
Pin (A48)
PG
DELAY
VDD_19V_IN
5V0_AO
5V0_AO
SRC0CS25D
D
G FET
S
D
G FET
S
5V0_AO
OUT
VCC
VCCLO*
PSHOLD
D
G FET
S
From Module
SYS_WAKE# (Pin WAKE_L
B48 – TX2i only)
ONOFF_CTLR_PBOUT
PBOUT
SR*
EN/EN*
PB*
RST*
CSRD
INT*
VREF
GND
MOD_PWR_ON_STATE_L
MOD_VIN_EN
5V0_AO
5V0_AO
74LVC1G74
SD
VCC
D
CP
RD
Q*
GND
Q
5V0_AO
MOD_PWR_CFG_ID_L
D
G FET
S
5V0_AO
POWER_ON
D
G FET
S
5V0_AO
5V0_AO
To main input
power FET enable
circuit (TX2i only).
To Module
POWER_BTN#
Pin (B50)
5V0_AO
5V0_AO
D
G FET
S
5V0_AO
5V0_AO
5V0_AO
D
G FET
S
Note
D
G FET
S
D
G FET
S
The figure above is a high-level representation of the connections involved. Details will be provided in a future carrier
board reference design.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
16
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
3.6 Power & Voltage Monitoring
3.6.1 Power Monitor
Pow er monitors are provided on the module. These monitor the main DC, CPU, GPU/SRAM, SOC (CORE) & DDR Supplies.
The monitors w ill toggle a WARN (w arning) output, or a CRIT (critical) output, depending on the pow er “seen” at the sense
resistors and the thresholds set for each supply.
Figure 10. Power Monitor (GPU/SRAM, SOC & WLAN)
INA3221AIRGVR
Power Monitor
VIN1P
VDD_3V3 _SYS
0.1uF
GEN1_ I2C
(PU to 3.3V)
VIN1N
SCL
SDA
AO
VIN2P
PV
TC
VPU
VIN2N
GND
PAD
VIN3P
10Ω
GPU_INA_ M
10Ω
SOC_INA_ P
SOC Supply Monitor
1uF
10Ω
SOC_INA_ M
10Ω
WIFI_INA_P
10Ω
Wi-Fi Supply Monitor
(Jet son TX 1/TX2 Only)
WIFI_INA_M
1uF
VIN3N
GPU_INA_ P
GPU Supply Monitor
1uF
VS
GEN1_ I2C_S CL
GEN1_ I2C_S DA
10Ω
Sense
Resistors
VDD_IN
0.01Ω, 1%
080 5
VDD_SYS _GPU_IN
(GP U supply input)
VDD_IN
0.01Ω, 1%
080 5
VDD_SYS _SOC_IN
(SO C supply input)
VDD_5V0 _SYS
0.01Ω, 1%
060 3
VDD_3V8 _WIFI_ SENSE
VDD_1V8
100 kΩ
WARN
INA_WIFI_THERM_ WARN_L
CRIT
Tegra GPIO_ MDM6
Figure 11. Power Monitor (VDD_IN, CPU & DDR)
INA3221AIRGVR
Power Monitor
VIN1P
VDD_3V3 _SYS
0.1uF
GEN1_ I2C_S CL
GEN1_ I2C_S DA
10Ω
VIN1N
SCL
SDA
10Ω
AO
VIN2P
PV
TC
VPU
VIN2N
GND
PAD
VIN3P
VDD_IN_P RE RE G_SENSE
10Ω
CPU_INA_M
10Ω
SRAM_ INA_P
10Ω
SRAM_ INA_M
DDR Supply Monitor
1uF
Sense
Resistors
VDD_IN_RS
0.02Ω, 1%
301 2
VDD_IN
CPU_INA_P
CPU S upply Monitor
1uF
VIN3N
VDD_IN_S ENSE
VDD_IN Supply Monitor
1uF
VS
GEN1_ I2C
(PU to 3.3V)
10Ω
VDD_IN
0.01Ω, 1%
080 5
VDD_SYS _CPU_ IN
(CPU s upply input)
VDD_5V0 _SYS
0.01Ω, 1%
060 3
VDD_5V0 _SD0
(DDR supply input)
VDD_1V8
WARN
CRIT
100 kΩ
INA_PREREG _THE RM_WARN_L
Tegra BATT_OC
3.6.2 Voltage Monitor
Jetson TX2i
A voltage monitor circuit is implemented on Jetson TX2i to indicate if the main DC input rail, VDD_IN, “droops” below an
acceptable level. The device used w ill react quickly and drive VIN_PWR_BAD# active (low ) w hich w ill force the pow er off . The
voltage monitor circuit is implemented w ith a fast voltage comparator supplied by VDD_IN w ith a 5V reference. This device has
an open drain active low output w hich is pulled low w hen the VDD_IN voltage drops below the selected threshold (8.04V).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
17
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 12. Voltage Monitor Connections
VDD_IN
RB5 21CS30L
TPS3808G01
100 kΩ,
1%
Note:
VCC
SENSE
TP
GND
RST*
MR*
CT
47.4kΩ,1%
47.5kΩ,
1%
VIN_PWR_BAD#
2.49kΩ,
1%
The threshold for VDD_IN, determined by the voltage divider components used in the circuit above is 8.04V.
Jetson TX2
A voltage monitor circuit is implemented on Jetson TX2 to indicate if the main DC input rail, VDD_IN, “droops” below an
acceptable level. The device used w ill react quickly and generate an alert to one of the Tegra SOC_THERM capable pins
(VCOMP_ALERT). The voltage monitor circuit is implemented w ith a fast voltage comparator supplied by V DD_IN w ith a 1.8V
(VDD_1V8) reference common w ith the Tegra IO domain that receives the output signal. This device has an open drain active
low output w hich is pulled low w hen the VDD_IN voltage drops below the selected threshold.
Figure 13. Voltage Monitor Connections
VDD_5V0_SYS
1.8V
100kΩ
VDD_IN
VDD_1V8
Note:
110kΩ,1%
IN_POS
49.9kΩ,
1%
IN_NEG
+
–
VCC
VOUT
COMP_SOC_THERM* (Tegra VCOMP_ALERT)
VEE
34kΩ,1%
The threshold for VDD_IN, determined by the voltage divider components used in the cir cuit above is 5.75V.
3.7 Deep Sleep (SC7)
Jetson TX2/TX2i supports a low pow er state called Deep Sleep or SC7. This can be entered under softw are control, and exited
using various mechanisms, including w ake capable pins that are listed in the table below .
Table 11. Signal Wake Events
Potential Wake Event (Reference Design Signal)
PCIe Wake Request (PEX_WAKE#)
Bluetooth Wake AP (BT2_WAKE_AP – Secondary)
WLAN Wake AP (WIFI_WAKE_AP - Secondary)
Thermal/Over-current Warning
Audio Codec Interrupt (AUD_INT_L)
DP 0 Hot Plug Detect (DP_AUX_CH0_HPD)
HDMI Consumer Electronic Control (HDMI_CEC)
DP 1 Hot Plug Detect (DP_AUX_CH1_HPD)
Camera Vertical Sync (CAM_VSYNC)
POWER_BTN#
Motion Interrupt (MOTION_INT)
CAN 1 Error (CAN1_ERR)
CAN Wake (CAN_WAKE)
CAN 0 Error (CAN0_ERR)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Module Pin Assigned
PEX_WAKE#
GPIO13_BT_WAKE_AP
GPIO10_WIFI_WAKE_AP
BATT_OC
GPIO20_AUD_INT
DP0_HPD
HDMI_CEC
DP1_HPD
CAM_VSYNC
POWER_BTN#
GPIO9_MOTION_INT
CAN1_ERR
CAN_WAKE
CAN0_ERR
Wake #
1
8
9
10
12
19
20
21
23
29
46
47
48
49
18
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Touch Interrupt (TOUCH_INT)
USB VBUS Detect (USB_VBUS_DET)
GPIO Expansion 0 Interrupt (GPIO_EXP0_INT)
Modem Wake AP (MDM_WAKE_AP)
Battery Low (BATLOW#)
GPIO Expansion 1 Interrupt (GPIO_EXP1_INT)
USB Vbus Enable 0 (USB_VBUS_EN0)
USB Vbus Enable 1 (USB_VBUS_EN1)
Ambient Light Proximity Interrupt (ALS_PROX_INT)
Modem Coldboot (MDM_COLDBOOT)
Force Recovery (FORCE_RECOV#)
Sleep (SLEEP_L)
GPIO6_TOUCH_INT
USB0_VBUS_DET
GPIO_EXP0_INT
GPIO16_MDM_WAKE_AP
BATLOW#
GPIO_EXP1_INT
USB_VBUS_EN0
USB_VBUS_EN1
GPIO8_ALS_PROX_INT
GPIO18_MDM_COLDBOOT
FORCE_RECOV#
SLEEP#
51
53
54
55
56
58
61
62
63
64
67
68
Figure 14. Deep Sleep (SC7) Entry/Exit Sequence
SC7 Entry
SC7 Exit
SC7 Entry/Exit Trigger
VDD_IN
VIN_PWR_BAD#
CARRIER_PWR_ON
Carrier Board VDD_1V8
RESET_OUT#
CARRIER_STBY#
(Tegra X2 SOC_PWR_REQ)
VDD_3V3_SLP
VDD_5V0_SLP
VDD_12V_SLP
VDD_5V0_HDMI_CON
3.8 Optional Auto-Power-On Support
Jetson TX2 and Jetson TX2i both optionally support Auto-Pow er-On. This allow s the platform to pow er on w hen VDD_IN is first
pow ered, instead of w aiting for a pow er button press. For Jetson TX2, to enable this feature, the CHARGER_PRSNT# pin
should be tied to GND. For Jetson TX2i, w hich uses a different PMIC, the POWER_BTN# pin needs to be held high. As there
is a pull-up on the module, the POWER_BTN# pin can be left floating on the carrier board. If a design w ill support both Jetson
TX2 and Jetson TX2i and needs to pow er on w ithout a button press (Auto-Pow er-On), the CHARGER_PRSNT# pin should be
tied to GND, and the POWER_BTN# pin should be left unconnected.
3.8.1 Jetson TX2 Auto-Power-On Details
This section provides guidance for modifying a carrier board design to pow er the platform on w hen VDD_IN is first pow ered,
instead of w aiting for a pow er button press. In order to pow er the system on w ithout a pow er button, a specific sequence is
required betw een the time the VDD_IN pow er is connected and the CHARGER_PRSNT# pin on the module is driven low . The
CHARGER_PRSNT# pin connects to the module PMIC and requires a minimum delay of 300ms from the point VDD_IN reaches
its minimum level (5.5V) before it can be driven low . Jetson TX2/TX2i includes circuitry on the module to support Auto-Pow erOn. In order to enable this feature, the CHARGER_PRSNT# pin should be tied to GND.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
19
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
3.8.2 Jetson TX2i Auto-Power-On Details
Jetson TX2i uses a different PMIC than Jetson TX2. The TX2i PMIC has a level sensitive on input, so in order to pow er
automatically w hen the main pow er is applied (Auto-Pow er-On), all that is required is for the POWER_BTN# pin to be pulled up.
Since this pin is pulled up on the module, it can be left unconnected for Auto-Pow er-On to be supported.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
20
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
4.0 GENERAL ROUTING GUIDELINES
Signal Nam e Conventions
The follow ing conventions are used in describing the signals for Jetson TX2/TX2i:
▪
▪
Signal names use a mnemonic to represent the function of the signal. For example, Secure Digital Interface #3
Command signal is represented as SDCARD_CMD, w ritten in bold to distinguish it from other text. All active low
signals are identified by a # or an underscore follow ed by capital N (_N) after the signal name. For example,
RESET_IN# indicates an active low signal. Active high signals do not have the underscore-N (_N) after the signal
names. For example, SDCARD_CMD indicates an active high signal. Differential signals are identified as a pair
w ith the same names that end w ith _P & _N, just P & N or + & - (for positive and negative, respectively). For
example, USB1_DP and USB1_DN indicate a differential signal pair.
I/O Type The signal I/O type is represented as a code to indicate the operational characteristics of the signal. The
table below lists the I/O codes used in the signal description tables.
Table 12. Signal Type Codes
Code
A
DIFF I/O
DIFF IN
DIFF OUT
I/O
I
O
OD
I/OD
P
Definition
Analog
Bidirectional Differential Input/Output
Differential Input
Differential Output
Bidirectional Input/Output
Input
Output
Open Drain Output
Bidirectional Input / Open Drain Output
Power
Routing Guideline Form at
The routing guidelines have the follow ing format to specify how a signal should be routed.
▪
▪
▪
Breakout traces are traces routed from a BGA or other pin array, either to a point beyond the array, or to another
layer w here full normal spacing guidelines can be met. Breakout trace delay limited to 500 mils unless otherw ise
specified.
After breakout, signal should be routed according to specified impedance f or differential, single-ended, or both (for
example: HDMI). Trace spacing to other signals also specified.
Follow max & min trace delays w here specified. Trace delays are typically show n in mm or in terms of signal delay
in pico-seconds (ps) or both.
For differential signals, trace spacing to other signals must be larger of specified × dielectric height or inter pair spacing
Spacing to other signals/pairs cannot be smaller than spacing betw een complementary signals (intra-pair).
Total trace delay depends on signal velocity w hich is different betw een outer (microstrip) & inner (stripline)
layers of a PCB.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
21
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Signal Routing Conventions
Throughout this document, the follow ing signal routing conventions are used:
SE Impedance (/ Diff Impedance) at x Dielectric Height Spacing
▪
Note:
Single-ended (SE) impedance of trace (along w ith differential impedance for diff pairs) is achieved by spacing
requirement. Spacing is multiple of dielectric height. Dielectric height is typically different for microstrip & stripline.
Note: 1 mil = 1/1000th of an inch.
Trace spacing requirement applies to SE traces or differential pairs to other SE traces or differential pairs. It does not a pply to
traces making up a differential pair. For this case, spacing/trace widths are chos en to meet differential impedance
requirement.
General Routing Guidelines
Pay close attention w hen routing high speed interfaces, such as HDMI/DP, USB 3.0, PCIe or DSI/CSI. Each of these interfaces
has strict routing rules for the trace impedance, w idth, spacing, total delay, and delay/flight time matching. The follow ing
guidelines provide an overview of the routing guidelines and notations used in this document.
▪
▪
▪
Controlled Im pedance
Each interface has different trace impedance requirements & spacing to other traces. It is up to designer to
calculate trace w idth & spacing required to achieve specified single-ended (SE) & differential (Diff) impedances.
Unless otherw ise noted, trace impedance values are ±15%.
Max Trace Lengths/Delays
Trace lengths/delays should include main PCB routing and any additional routing on a Flex/ secondary PCB
segment connected to main PCB. The max length/delay should be from the module to the actual connector (i.e.
USB, HDMI, SD Card, etc.) or device (i.e. onboard USB device, Display driver IC, camera imager IC, etc.)
Trace Delay/Flight Tim e Matching
Signal flight time is the time it takes for a signal to propagate from one end (driver) to other end (receiver). One
w ay to get same flight time for signal w ithin signal group is to match trace lengths w ithin specified delay in the
signal group.
Total trace delay = Carrier PCB trace delay only. Do not exceed maximum trace delay specified.
For six layers or more, it is recommended to match trace delays based on flight time of signals. For example,
outer-layer signal velocity could be 150psi (ps/inch) & inner-layer 180psi. If one signal is routed 10 inches on
outer layer & second signal is routed 10 inches in inner layer, difference in flight time betw een tw o signals w ill
be 300ps! That is a big difference if required matching is 15ps (trace delay matching). To fix this, inner trace
needs to be 1.7 inches shorter or outer trace needs to be 2 inches longer.
In this design guide, terms such as intra-pair & inter-pair are used w hen describing differential pair delay.
Intra-pair refers to matching traces w ithin differential pair (for example, true to complement trace matching).
Inter-pair matching refers to matching differential pairs average delays to other differential pairs average
delays.
General PCB Routing Guidelines
For GSSG stack-up to minimize crosstalk, signal should be routed in such a way that they are not on top of each
other in two routing layers (see diagram to right)
G
S
S
G
Do not route other signals or power traces/areas directly under or over critical high-speed interface signals.
Note:
The requiements detailed in the Interface Signal Routing Requirements tables must be met for all interfaces implemented or
proper operation cannot be guaranteed.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
22
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
5.0 USB, PCIE & SATA
Jetson TX2/TX2i allow s multiple USB 3.0 & PCIe interfaces, and a single SATA interface to be brought out on the module. In
some cases, these interfaces are multiplexed on some of the module pins.
Table 13. USB 2.0 Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
B40
B39
A17
A36
B37
A39
A38
A18
B43
B42
USB0_DN
USB0_DP
USB_VBUS_EN0
(PMIC GPIO0)
UART5_CTS
USB1_DN
USB1_DP
USB_VBUS_EN1
USB2_DN
USB2_DP
USB 2.0 Port 0 Data–
USB 2.0 Port 0 Data+
USB VBUS Enable/Overcurrent 0
USB 0 ID
USB 0 VBUS Detect
USB 2.0, Port 1 Data–
USB 2.0, Port 1 Data+
USB VBUS Enable/Overcurrent 1
USB 2.0, Port 2 Data–
USB 2.0, Port 2 Data+
USB0_D–
USB0_D+
USB0_EN_OC#
USB0_OTG_ID
USB0_VBUS_DET
USB1_D–
USB1_D+
USB1_EN_OC#
USB2_D–
USB2_D+
Usage on Carrier
Board
USB 2.0 Micro AB
Direction
Pin Type
Bidir
Bidir
Bidir
Input
Input
Bidir
Bidir
Bidir
Bidir
Bidir
USB PHY
USB 3.0 Type A
M.2 Key E
Open Drain – 3.3V
Analog
USB VBUS, 5V
USB PHY
Open Drain – 3.3V
USB PHY
Table 14. USB 3.0, PCIe & SATA Pin Descriptions
A44
Module Pin
Name
PEX0_REFCLK+
A45
PEX0_REFCLK–
PEX_CLK1N
C48
PEX0_CLKREQ#
PEX_L0_CLKREQ_N
C49
PEX0_RST#
PEX_L0_RST_N
H44
PEX0_RX+
PEX_RX4P
H45
PEX0_RX–
PEX_RX4N
E44
PEX0_TX+
PEX_TX4P
E45
PEX0_TX–
PEX_TX4N
G42
USB_SS1_RX+
PEX_RX2P
G43
USB_SS1_RX–
PEX_RX2N
D42
USB_SS1_TX+
PEX_TX2P
D43
USB_SS1_TX–
PEX_TX2N
F40
PEX2_RX+
PEX_RX3P
F41
PEX2_RX–
PEX_RX3N
C40
PEX2_TX+
PEX_TX3P
C41
PEX2_TX–
PEX_TX3N
G39
PEX_RFU_RX+
PEX_RX1P
G40
PEX_RFU_RX–
PEX_RX1N
D39
PEX_RFU_TX+
PEX_TX1P
D40
PEX_RFU_TX–
PEX_TX1N
D48
PEX_WAKE#
PEX_WAKE_N
B45
PEX1_REFCLK+
PEX_CLK3P
B46
PEX1_REFCLK–
PEX_CLK3N
C47
PEX1_CLKREQ#
PEX_L2_CLKREQ_N
E50
PEX1_RST#
PEX_L2_RST_N
H41
PEX1_RX+
PEX_RX0P
H42
PEX1_RX–
PEX_RX0N
E41
PEX1_TX+
PEX_TX0P
E42
PEX1_TX–
PEX_TX0N
A41
PEX2_REFCLK+
PEX_CLK2P
A42
PEX2_REFCLK–
PEX_CLK2N
Pin #
Tegra Signal
Usage/Description
PEX_CLK1P
PCIe 0 Reference Clock+ (PCIe IF #0)
PCIe 0 Reference Clock – (PCIe IF #0)
PCIe 0 Clock Request (PCIe IF #0)
PCIe 0 Reset (PCIe IF #0)
PCIe 0 Lane 0 Receive+ (PCIe IF #0)
PCIe 0 Lane 0 Receive– (PCIe IF #0)
PCIe 0 Lane 0 Transmit+ (PCIe IF #0)
PCIe 0 Lane 0 Transmit– (PCIe IF #0)
USB SS 1 Receive+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1)
Usage on the
Carrier Board
Output
Output
Bidir
Output
PCIe PHY
Open Drain 3.3V, Pullup on the module
Input
Output
Output
Input
M.2
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Pin Type
Input
USB SS 1 Receive– (USB 3.0 Port #2 or PCIe #0 Lane 1)
PCIe x4
USB SS 1 Transmit+ (USB 3.0 Port #2 or PCIe IF #0 Lane 1) Connector
USB SS 1 Transmit– (USB 3.0 Port #2 or PCIe #0 Lane 1)
PCIe 2 Receive+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe 2 Receive– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe 2 Transmit– (PCIe IF #0 Lane 2 or PCIe IF #1 Lane 0)
PCIe RFU Receive+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe RFU Receive– (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe RFU Transmit – (PCIe IF #0 Lane 3 or USB 3.0 Port #1)
PCIe Wake
PCIe x4 conn &
PCIe Reference Clock 1+ (PCIe IF #2)
PCIe Reference Clock 1– (PCIe IF #2)
PCIE 1 Clock Request (mux option - PCIe IF #2)
PCIe 1 Reset (PCIe IF #2)
PCIe 1 Receive+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 1 Receive– (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 1 Transmit+ (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 1 Transmit– (PCIe #2 Lane 0 muxed w/USB 3.0 Port
#0)
PCIe 2 Reference Clock+ (PCIe IF #1)
PCIe 2 Reference Clock– (PCIe IF #1)
Direction
Input
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Output
M.2 Key E
PCIe PHY, AC-Coupled
on carrier board
Output
Bidir
Output
Open Drain 3.3V, Pullup on the module
PCIe PHY
Open Drain 3.3V, Pullup on the module
Input
USB 3.0 Type A
(Default) or M.2
Key E
Input
Output
PCIe PHY, AC-Coupled
on carrier board
Output
Unassigned
Output
Output
PCIe PHY
23
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Module Pin
Name
Pin #
Usage/Description
PCIE 2 Clock Request (PCIe IF #1)
PCIe 2 Reset (PCIe IF #1)
USB SS 0 Receive+ (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
C46
PEX2_CLKREQ#
PEX_L1_CLKREQ_N
D49
PEX2_RST#
PEX_L1_RST_N
F43
USB_SS0_RX+
PEX_RX0P
F44
USB_SS0_RX–
Usage on the
Carrier Board
Tegra Signal
USB SS 0 Receive– (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
USB SS 0 Transmit+ (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
USB SS 0 Transmit– (USB 3.0 Port #0 muxed w/PCIe #2
Lane 0)
SATA Receive+
PEX_RX0N
C43
USB_SS0_TX+
PEX_TX0P
C44
USB_SS0_TX–
PEX_TX0N
G45
SATA_RX+
PEX_RX5P
G46
SATA_RX–
PEX_RX5N
D45
SATA_TX+
PEX_TX5P
D46
SATA_TX–
PEX_TX5N
D47
SATA_DEV_SLP
PEX_L2_CLKREQ_N
SATA Receive–
SATA Transmit+
SATA Transmit–
SATA Device Sleep or PEX1_CLKREQ# (PCIe IF #2)
depending on Mux setting
Direction
Pin Type
Bidir
Open Drain 3.3V, Pullup on the module
Output
Input
Input
USB SS PHY, ACCoupled (off the
module)
USB 3.0 Type A
Output
Output
USB SS PHY, ACCoupled on carrier
board
Input
Input
SATA Connector
Output
SATA PHY, AC-Coupled
on carrier board
Output
Input
Open Drain 3.3V, Pullup on the module
The table below show several w ays to bring out as many of the USB 3.0 or PCIe interf aces as possible to meet different design
requirements for a platform built for Jetson TX2/TX2i.
Note: Check the Jetson TX1 and Jetson TX2 Comparison and Migration Application Note which
provides the differences in USB 3.0, PCIe & SATA lane mapping between Jetson TX1 & Jetson
TX2/TX2i and provides a table of configurations supported by all three modules.
Table 15. USB 3.0, PCIe & SATA Lane Mapping Configurations
Module Pin Names
Configs
1
2 (CB
Default)
3
4
5
Tegra Lanes
Avail. Outputs from the
module
USB 3.0
PCIe
SATA
6
1.
2.
3.
4.
5.
PEX_RFU
PEX2
USB_SS1
PEX0
Lane 0
Lane 1
Lane 3
Lane 2
Lane 4
PCIe#0_3
PCIe#0_3
PCIe#0_2
PCIe#0_2
PCIe#0_1
PCIe#0_1
PCIe#0_0
PCIe#0_0
USB_SS#1
USB_SS#1
USB_SS#1
USB_SS#1
PCIe#1_0
USB_SS#2
PCIe#1_0
USB_SS#2
PCIe#1_0
PCIe#0_1
PCIe#1_0
PCIe#0_1
X4 PCIe Connector
PCIe#0_0
PCIe#0_0
PCIe#0_0
PCIe#0_0
0
1
1x1 + 1x4
1x4
1
1
PCIe#2_0
2
3
1
2
3x1
2x1
2x1 + 1x2
1x1 + 1x2
1
1
1
1
PCIe#2_0
Default Usage on CB (carrier board)
Note:
PEX1
PCIe#2_0
Unused
USB_SS0
(see note 1)
SATA
Lane 5
USB_SS#0
USB_SS#0
USB_SS#0
USB 3 Type A
SATA
SATA
SATA
SATA
SATA
SATA
SATA
PCIe interface #2 can be brought to the PEX1 pins, or USB 3.0 port #1 to the USB_SS0 pins on Jetson TX2/TX2i depending
on the setting of a multiplexor on the module. The selection is controlled by QSPI_IO2 configured as a GPIO.
Jetson TX2/TX2i has been designed to enable use cases listed in the table above. However, released Software may not
support all configurations, nor has every configura tion been validated.
o Configuration #1 & 2 represent the supported and validated Jetson TX2/TX2i Developer Kit configurations. These
configurations are supported by the released Software, and the PCIe, USB 3.0, and SATA interfaces have been
verified on the carrier board.
The cell colors highlight the different PCIe interfaces and USB 3.0 ports. Light and Medium green are used for PCIe
controllers #0 and #1. Four shades of blue are used for USB 3.0 controllers #[0:3]. SATA is highlighted in orange.
Any x4 configuration can be used as a single x2 using only lanes 0 & 1 or a single x1 using only lane 0. Any x2
configuration can be used as a single x1 using only lane 0.
In order to ease routing, the order of lanes for PCIe #0 can either be as shown above, or the reverse (I.e., PCIE#0_3 on
lane 4, PCIE#0_2 on lane 3, etc.).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
24
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 16. USB 3.0, PCIe & SATA Lane Mapping Configurations compatible with Jetson TX2 & Jetson TX2i only.
Module Pin Names
Configs
1
2 (CB
Default)
3
4
Tegra Lanes
Avail. Outputs from the
module
USB 3.0
PCIe
SATA
5
6
PEX_RFU
PEX2
USB_SS1
PEX0
Lane 0
Lane 1
Lane 3
Lane 2
Lane 4
PCIe#0_3
PCIe#0_3
PCIe#0_2
PCIe#0_2
PCIe#0_1
PCIe#0_1
PCIe#0_0
PCIe#0_0
USB_SS#1
USB_SS#1
USB_SS#1
USB_SS#1
PCIe#1_0
USB_SS#2
PCIe#1_0
USB_SS#2
PCIe#1_0
PCIe#0_1
PCIe#1_0
PCIe#0_1
X4 PCIe Connector
PCIe#0_0
PCIe#0_0
PCIe#0_0
PCIe#0_0
0
1
1x1 + 1x4
1x4
1
1
PCIe#2_0
2
3
1
2
3x1
2x1
2x1 + 1x2
1x1 + 1x2
1
1
1
1
PCIe#2_0
PCIe#2_0
Unused
Default Usage on CB (carrier board)
Note:
PEX1
USB_SS0
(see note 1)
SATA
Lane 5
SATA
SATA
USB_SS#0
SATA
SATA
SATA
SATA
SATA
USB_SS#0
USB_SS#0
USB 3 Type A
PCIe interface #2 can be brought to the PEX1 pins, or USB 3.0 port #1 to the USB_SS0 pins on Jetson TX2/TX2i depending
on the setting of a multiplexor on the module. The selection is controlled by QSPI_IO2 configured as a GPIO.
Jetson TX2/TX2i has been designed to enable use cases listed in the table above. However, released Software may not
support all configurations, nor has every configuration been validated.
o Configuration #1 & 2 represent the supported and validated Jetson TX2/TX2i Developer Kit configurations. These
configurations are supported by the released Software, and the PCIe, USB 3.0, and SATA interfaces have been
verified on the carrier board.
See notes under the Backward Compatible mapping table related to color coding, PCIe x2/x1 support & lane reversal.
6.
7.
8.
5.1 USB
Jetson TX2/TX2i
To PMIC G PIO0
(on Module)
Tegra
UARTCAM
UART5_CTS_N
Gate/LS
VDD_5V0_IO_SYS
USB0_OTG_ID
USB0_VBUS_DET
A36
USB_VBUS_EN0
Load Switch
IN
OUT
EN
OC
100kΩ
Figure 15 USB 2.0 OTG + USB 3.0 Host Connection Example
100Ω
B3 7
VBUS
VDD_3V3_SY S
USB2_EN_OC#
USB_VBUS_EN0
USB0_EN_OC#
USB_VBUS_EN1
USB 2.0
USB1_EN_OC#
USB0_DP
USB0_DN
USB0_D+
USB1_DP
USB1_DN
USB1_D+
USB2_DP
USB2_DN
USB2_D+
USB0_D–
USB1_D–
USB2_D–
USB_SS0_TX+
USB 3.0
& PEX
Default
USB_SS0_TX–
USB_SS0_RX+
PEX_TX0_P
PEX_TX0_N
PEX_RX0_P
PEX_RX0_N
USB_SS0_RX–
Mux
PEX1_TX+
PEX1_TX–
PEX1_RX+
PEX1_RX–
Note:
1.
2.
A19
A17
A18
B3 9
B4 0
D+
D–
Common
Mode Choke
VDD_5V0_IO_SYS
USB_VBUS_EN1
ID
Load Switch
IN
OUT
EN
OC
ESD
100Ω
A38
A39
B4 2
B4 3
VBUS
To M.2 Module
on Carrier Board
0.1uF
0.1uF
C43
C44
F43
F44
E41
E42
H41
H42
USB 2.0
Micro AB
PCIe#2 (x1)
Common
Mode Choke
D+
D–
Common
Mode Choke
TX+
TX–
Common
Mode Choke
RX+
RX–
USB 3.0
Type A
ESD
Common mode filters on USB[2:0]_DP/DN (USB 2.0 interfaces) are optional. Place only as needed if EMI is an issue.
Common mode filters on USB3_TX/RX_P/N signals are not recommended. If common mode devices are placed, they
must be selected to minimize the impact to signal quality, which must meet the USB spec. signal requirements. See the
Common Mode Choke requirements in the USB 3.0 Interface Signal Routing Requirements table .
If USB 3.0 is routed to a connector, only AC caps on the module TX lines are required. If routed directly to a peripheral,
AC caps are needed for both the module TX lines (connected to device RX) & Device TX lines (connected to the module
RX).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
25
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
3.
4.
USB0 must be available to use as USB Device for USB Recovery Mode.
Connector used must be USB-IF certified if USB 3.0 implemented.
Figure 16 USB 2.0/3.0 Dual-mode (host/device) Connection Example
Jetson TX2/TX2i
UARTCAM
UART5_CTS_N
Gate/LS
USB0_OTG_ID
USB0_VBUS_DET
100Ω
A36
VDD_5V0_IO_SYS
B3 7
VDD_3V3_SY S
USB_VBUS_EN0
USB0_EN_OC#
USB0_DP
USB0_DN
USB0_D+
A17
USB_VBUS_EN0
Load Switch
IN
OUT
EN
OC
100kΩ
To PMIC G PIO0
(on Module)
Tegra
USB 3.0
Micro AB
100Ω
VBUS
USB 2.0
USB0_D–
USB_SS0_TX+
USB 3.0
& PEX
Default
USB_SS0_TX–
USB_SS0_RX+
PEX_TX0_P
PEX_TX0_N
PEX_RX0_P
PEX_RX0_N
USB_SS0_RX–
Mux
PEX1_TX+
PEX1_TX–
PEX1_RX+
PEX1_RX–
Note:
1.
2.
B3 9
B4 0
0.1uF
0.1uF
C43
C44
F43
F44
E41
E42
H41
H42
Common
Mode Choke
D+
D–
ID
Common
Mode Choke
TX+
TX–
Common
Mode Choke
RX+
RX–
PCIe#2 (x1)
ESD
See notes under USB 2.0 OTG + USB 3.0 Host Connection Example figure.
USB 3.0 Port #0 is shown in the example above. Other supported USB 3.0 ports can be used instead. As noted, USB0
must be routed to a connector to support USB recovery mode. Since the connector above would be the only Device
capable connector in the system connected to Tegra, USB0 must be used.
USB 2.0 Design Guidelines
These requirements apply to the USB 2.0 controller PHY interfaces : USB[2:0]_D–/D+
Table 17. USB 2.0 Interface Signal Routing Requirements
Parameter
Max Frequency (High Speed)
Bit Rate/UI period/Frequency
Max Loading
High Speed / Full Speed / Low Speed
Reference plane
Trace Impedance
Diff pair / Single Ended
Via proximity (Signal to reference)
Max Trace Delay
With CMC or SW (Microstrip / Stripline)
Without CMC or SW (Microstrip / Stripline)
Requirement
480/2.083/240
10 / 150 / 600
GND
90 / 50
< 3.8 (24)
900/1050 (6)
1350/1575 (9)
Max Intra-Pair Skew between USBx_D+ & USBx_D–
7.5
Note:
1.
2.
3.
4.
Units
Mbps/ns/MHz
pF
Ω
mm (ps)
ps (in)
Notes
±15%
See Note 2
Prop delay assumption: 175ps/in.
for stripline, 150ps/in. for
microstrip). See Note 3
ps
If portion of route is over a flex cable this length should be included in the Max Trace Delay/Length calculation & 85 Ω
Differential pair trace impedance is recommended.
Up to 4 signal Vias can share a single GND return Via.
CMC = Common-Mode-Choke. SW = Analog Switch
Adjustments to the USB drive strength, slew rate, termination value settings should not be necessary, but if any are
made, they MUST be done as an offset to default values instead of overwriting those values.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
26
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
USB 3.0 Design Guidelines
The follow ing requirements apply to the USB 3.0 PHY interfaces
Table 18. USB 3.0 Interface Signal Routing Requirements
Parameter
Specification
Data Rate / UI period
Max Number of Loads
Termination
Reference plane
Electrical Specification
Insertion Loss (IL)
Host
Device
Type C
Type A
Micro AB
Resonance Dip Frequency
TDR dip
Near-end Crosstalk (NEXT) @ DC to 5GHz
IL/NEXT Plot
Trace Impedance
Trace Impedance
Diff pair / Single Ended
Reference plane
Trace Length/Skew
Trace loss characteristic @ 2.5GHz
Breakout Region
Max PCB Trace Length
Max trace length/delay
Host
Device
Requirement
Units
5.0 / 200
1
90 differential
GND
Gbps / ps
load
Ω
≤2
≤7
≤1
>8
On-die termination at TX & RX
>= 75
<=-45
Ω
dB
@ 2.5GHz
@ 2.5GHz
@ 2.5GHz
The resonance dip could be caused by a via stub for
layer transition or trace stub for co-layout.
Using TDR pulse with Tr (10%-90%) = 200ps
For each TX-RX NEXT
85-90 / 45-55
GND
Ω
±15%
< 0.7
dB
Notes
GHz
dB/in
11 (73)
mm (ps)
152.3 (1014)
50.8 (334)
mm (ps)
The following max length is derived based on this
characteristic. See Note 1.
Trace with minimum width and spacing
Max Within Pair (Intra-Pair) Skew
0.15 (1)
mm (ps)
Do trace length matching before hitting discontinuities
Differential pair uncoupled length
6.29 (41.9)
mm (ps)
Trace Spacing – for TX/RX non-interleaving
TX-RX Xtalk is very critical in PCB trace routing. The ideal solution is to route TX and RX on different layers.
If routing on the same layer, strongly recommend not interleaving TX and RX lanes
If it is necessary to have interleaved routing in breakout, all the inter-pair spacing should follow the rule of inter-SNEXT
The breakout trace width is suggested to be the minimum to increase inter-pair spacing
Do not perform serpentine routing for intra-pair skew compensation in the breakout region
Min Inter-S NEXT
(between TX/RX)
Main-route
Min Inter-S FEXT
(between TX/TX or RX/RX)
Breakout
Breakout
Main-route
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
4.85x
3x
1x
Dielectric
height
Intra-pair
spacing
-
This is the recommended dimension for meeting
NEXT requirement
This is the recommended dimension for meeting
NEXT requirement
1x
27
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Max length
Breakout
Main-route
Trace Spacing – for TX/RX interleaving
Trace Spacing
Pair-Pair (inter-pair)
Microstrip / Stripline
To plane & capacitor pad
Microstrip / Stripline
To unre lated high-speed signals
Microstrip / Stripline
Via
Topology
11
Max trace
length - LBRK
4x / 3x
4x / 3x
4x / 3x
-
GND via
-
-
Max # of Vias
Max Via Stub Length
Serpentine
Min bend angle
Dimension
PTH vias
Micro Vias
Min A Spacing
Min B, C Length
Min Jog Width
Added-on Components
Placement Order
AC Cap
Value
Min/Max
Location (max length to adjacent discontinuity)
Voiding
Inter-pair
spacing
mm
-
Stripline structure in a GSSG structure is assumed; it
holds in broadside-coupled stripline structure
All v alues are in terms of minimum dielectric height
dielectric
Y -pattern is
recommended
Keep sy mmetry
Y-pattern helps with
Xtalk suppression. It
can also reduce the
limit of pair-pair
distance. Need review
(NEXT/FEXT check) if
via placement is not Ypattern.
Place ground v ias as
sy mmetrically as
possible to data pair
v ias
up to 4 signal v ias (2
dif f pairs) can share a
single GND return v ia
GND via is used to maintain return path, while its Xtalk
suppression is limited
4
Not limited as long as total channel loss meets IL spec
0.4
mm
long via stub requires review (IL & resonance dip check)
135
4x
1.5x
3x
deg (α)
Trace
width
S1 must be taken care in order
to consider Xtalk to adjacent
pair
Chip ̶ AC capacitor (TX only) ̶ common mode choke ̶ ESD ̶ Connector
0.075 / 0.2
8
uF
mm
GND/PWR void under/above
cap is preferred
Only required for TX pair when routed to connector
Discontinuity is connector, via, or component pad
Voiding is required if AC cap size is 0603 or larger
ESD (the usage of ESD is optional. A design should include the footprint for ESD as a stuffing option)
Preferred device
e.g. SEMTECH RClamp0524p
Max Junction capacitance (IO to GND)
0.8
pF
Footprint
Pad should be on the net –
not trace stub
Location (max length to adjacent discontinuity)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
8 (53)
mm (ps)
Discontinuity is connector, via, or component pad
28
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Common-mode Choke (Only if needed. Place near connector.)
Common-mode impe dance @100MHz
Min/Max
Max Rdc
Differential TDR impedance @TR-200ps (10%-90%)
Min Sdd21 @ 2.5GHz
Max Scc21 @ 2.5GHz
Routing length reduction
65/90
0.3
90
2.22
19.2
<= 3
Ω
Ω
Ω
dB
dB
in
FPC (Additional length of Flexible Printed Circuit Board)
The FPC routing should be included for PCB trace calculations (max length, etc.)
Characteristic Impedance
Same as PCB
Loss characteristic
Strongly recommend being
the same as PCB or better
Connector
Connector used must be USB-IF certified
Note:
1.
2.
3.
TDK ACM2012D-900-2P
If worse than PCB, the PCB & FPC length must be reestimated
Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
max trace lengths will need to be reduced.
Recommend trace length matching to <1ps before Vias or any discontinuity to minimize common mode conversion.
Place GND Vias as symmetrically as possible to data pair Vias.
Com m on USB Routing Guidelines
Guideline
If routing to USB device or USB connector includes a flex or 2nd PCB, the total routing including all PCBs/flexes must be used for the max trace & skew
calculations.
Keep critical USB related traces away from other signal traces or unrelated power traces/areas or power supply components
Table 19. Module USB 2.0 Signal Connections
Module Ball Name
USB[2:0]_D+
USB[2:0]_D–
Type
DIFF
I/O
Termination
90Ω common-mode chokes close to
connector. ESD Protection between choke
& connector on each line to GND
Description
USB Differential Data Pair: Connect to USB connector, Mini-Card
Socket, Hub or other device on the PCB.
Table 20. Miscellaneous USB 2.0 Signal Connections
Module Pin Name
USB0_VBUS_DET
USB0_OTG_ID
Type
A
Termination
100kΩ resistor to GND. See reference
design for VBUS power filtering.
A
Description
USB0 VBus Detect: Connect to VBUS pin of USB connector receiving
USB0_+/– interface. Also connects to VBUS power supply if host mode
supported.
USB Identification: Connect to ID pin of USB OTG connector receiving
USB0_P/M interface.
Table 21. USB 3.0 Signal Connections
Module Pin Name
USB_SS0_TX+/–
PEX_RFU_TX+/–
USB_SS1_TX+/–
USB_SS0_RX+/–
PEX_RFU_RX+/–
USB_SS1_RX+/–
(USB 3.0 Port #0)
(USB 3.0 Port #1)
(USB 3.0 Port #2)
(USB 3.0 Port #0)
(USB 3.0 Port #1)
(USB 3.0 Port #2)
Type
DIFF
Out
Termination
Series 0.1uF caps. Common-mode chokes &
ESD protection if these are used.
DIFF
In
If routed directly to a peripheral on the board,
AC caps are needed for the peripheral TX lines.
Common-mode chokes & ESD protection, if
these are used.
Description
USB 3.0 Differential Transmit Data Pairs: Connect
to USB 3.0 connectors, hubs or other devices on the
PCB.
USB 3.0 Differential Receive Data Pairs: Connect
to USB 3.0 connectors, hubs or other devices on the
PCB.
Table 22. Recommended USB observation (test) points for initial boards
Test Points Recommended
One for each of the USB 2.0 data lines (D+/-)
One for each of the USB 3.0 output lines used (TXn_+/-)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Location
Near the module connector & USB device. USB connector pins can serve as test points.
Near USB device. USB connector pins can serve as test points
29
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
One for each of the USB 3.0 input lines (RX_+/-)
Near the module connector.
5.2 PCIe
Jetson TX2/TX2i contains a PCIe (PEX) controller that supports up to 5 lanes, and 3 Root-Port (RP) controllers.
Figure 17. PCIe Connection Example
Jetson TX2/TX2i
Tegra - PCIe
PEX
PEX1_REFCLK+
PEX_CLK3_P
PEX_CLK3_N
PEX1_REFCLK–
PEX1_TX+
PEX1_TX–
PEX1_RX+
PEX_TX0P
PEX_TX0N
PEX_RX0P
PEX_RX0N
PEX1_RX–
Mux
Tegra
QSPI_IO2 LS
SEL
USB_SS0_TX+
(Default)
USB_SS0_TX–
USB_SS0_RX+
USB_SS0_RX–
PEX_CLK1_P
PEX_CLK1_N
PEX0_REFCLK+
PEX_TX1P
PEX_TX1N
PEX_RX1P
PEX_RX1N
PEX_RFU_T X+
PEX0_REFCLK–
PEX_RFU_T X–
PEX_RFU_RX+
PEX_RFU_RX–
USB_SS1_TX+
PEX_TX2P
PEX_TX2N
PEX_RX2P
PEX_RX2N
USB_SS1_TX–
USB_SS1_RX+
USB_SS1_RX–
PEX2_TX+
PEX_TX3P
PEX_TX3N
PEX_RX3P
PEX_RX3N
PEX2_TX–
PEX2_RX+
PEX2_RX–
PEX0_TX+
PEX_TX4P
PEX_TX4N
PEX_RX4P
PEX_RX4N
PEX0_TX–
PEX0_RX+
PEX0_RX–
PEX2_REFCLK+
PEX_CLK2_P
PEX_CLK2_N
PEX2_REFCLK–
B4 5
B4 6
E41
E42
H41
H42
0.1uF
0.1uF
C43
C44
F43
USB 3.0 (Port #1)
F44
A44
A45
D39
D40
G39
G40
D42
D43
G42
G43
C40
C41
F40
0.1uF
0.1uF
PCIe IF #0 Lane 3
Default: PCIe x1
(only PEX2_TX/RX lane used)
0.1uF
0.1uF
PCIe IF #0 Lane 1 Alternate: PCIe x4
(Routed to PCIe Connector on
Carrier Board)
0.1uF
0.1uF
PCIe IF #0 Lane 2
F41
E44
E45
H44
H45
0.1uF
0.1uF
PCIe IF #0 Lane 0
Optionally used with PCIe
IF x1 on PEX2_TX/RX (PCIe
IF #1).
A41
A42
VDD_3V3_SYS
PEX
Control
PEX_L0_CLKREQ_N
PEX_L0_RST_N
PEX0_CLKREQ#
PEX_L1_CLKREQ_N
PEX_L1_RST_N
PEX2_CLKREQ#
PEX_L2_CLKREQ_N
PEX_L2_RST_N
PEX0_RST#
PEX2_RST#
Mux
PMIC
GPIO7
SEL
SATA_DEV_SLP
PEX1_CLKREQ#
PEX1_RST#
PEX_WAKE#
PEX_WAKE_N
PCIe – Single Lane (IF #2) or
(USB 3.0 Port #0). Used for M.2
Connector on Carrier Board
C48
C49
Control for PCIe
IF #0 Lanes
C46
Control for PCIe
IF #1 Lane
D49
D47
Control for PCIe
IF #2 Lane
C47
E50
Shared
D48
PCIE Design Guidelines
Table 23. PCIE Interface Signal Routing Requirements
Parameter
Specification
Data Rate / UI Period
Configuration / Device Organization
Topology
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Requirement
5.0 / 200
1
Point-point
Units
Gbps / ps
Load
Notes
2.5GHz, half-rate architecture
Unidirectional, differential
30
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Termination
Impedance
Trace Impedance
differential / Single Ended
Reference plane
Spacing
Trace Spacing (Stripline/Microstrip) Pair – Pair
To plane & capacitor pad
To unrelated high-speed signals
Length/Skew
Trace loss characteristic @ 2.5GHz
50
Ω
To GND Single Ended for P & N
85 / 50
GND
Ω
±15%. See note 1
3x / 4x
3x / 4x
3x / 4x
Dielectric
< 0.7
dB/in
Breakout region (Max Length)
41.9
ps
Max trace length
Max PCB via distance from the BGA
PCB within pair (intra-pair) skew
5.5 (880)
41.9
0.15 (0.5)
in (ps)
ps
mm (ps)
0.15 (0.5)
mm (ps)
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Via
Via placement
Max # of Vias
PTH Vias
Micro-Vias
Max Via stub length
Routing signals over antipads
AC Cap
Value
Min/Max
Location (max length to adjacent discontinuity)
Voiding
Serpentine
Min bend angle
Dimension
Min A Spacing
Min B, C Length
Min Jog Width
MIsc.
Routing signals over antipads
Routing over voids
Connector
Voiding
41.9
The following max length is derived based on this
characteristic. See note 3
Minimum width and spacing. 4x or wider
dielectric height spacing is preferred
Max distance from BGA ball to first PCB via.
Do trace length matching before hitting
discontinuities
ps
Place GND vias as symmetrically as possible to data pair vias. GND via distance should be placed
less than 1x the diff pair via pitch
2 for TX traces & 2 for RX trace
No requirement
0.4
mm
Longer via stubs would require review
Not allowed
0.075 / 0.2
uF
8
mm
Voiding the plane directly under the pad 3-4
mils larger than the pad size is
recommended.
Only required for TX pair when routed to connector
Discontinuity such as edge finger, component pad
135
4x
1.5x
3x
S1 must be taken care in
order to consider Xtalk to
adjacent pair
deg (a)
Trace width
Not allowed
When signal pair approaches Vias, the maximal trace length across the void on the plane is 50mil.
Voiding the plane directly under the pad 5.7
mils larger than the pad size is
recommended.
Keep critical PCIe traces such as PEX_TX/RX, TERMP etc. away from other signal traces or unrelated power traces/areas or powe r supply components
Note:
1.
2.
3.
4.
The PCIe spec. has 40-60Ω absolute min/max trace impedance, which can be used instead of the 50 Ω, ± 15%.
If routing in the same layer is necessary, route group TX & RX separately without mixing RX/TX routes & keep distance
between nearest TX/RX trace & RX to other signals 3x RX-RX separation.
Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
max trace lengths will need to be reduced.
Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
31
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 24. PCIE Signal Connections
Module Pin Name
Type
Termination
Description
PCIe Interface #0 (x1 default configuration – x4 optional.
PEX0_TX+/–
USB_SS1_TX+/–
PEX2_TX+/–
PEX_RFU_TX+/–
PEX0_RX_+/–
USB_SS1_RX+/–
PEX2_RX+/–
PEX_RFU_RX+/–
PEX0_REFCLK+/–
PEX0_CLKREQ#
PEX0_RST#
(Lane 0)
(Lane 1)
(Lane 2)
(Lane 3)
(Lane 0)
(Lane 1)
(Lane 2)
(Lane 3)
DIFF OUT
DIFF IN
Series 0.1uF Capacitor
Differential Transmit Data Pairs: Connect to TX_P/N pins of PCIe
connector or RX_P/N pin of PCIe device through AC cap according to
supported configuration. Default configuration (x1) uses only Lane 0.
Series 0.1uF capacitors if
device on main PCB.
Differential Receive Data Pairs: Connect to RX_P/N pins of PCIe
connector or TX_P/N pin of PCIe device through AC cap according to
supported configuration. Default configuration (x1) uses only Lane 0.
DIFF OUT
I/O
O
56KΩ pullup to
VDD_3V3_SYS on each line
(exists on the module)
Differential Reference Clock Output: Connect to REFCLK_P/N pins of
PCIe device/connector
PEX Clock Request for PEX0_REFCLK: Connect to CLKREQ pin on
device/connector.
PEX Reset: Connect to PERST pin on device/connector.
PCIe Interface #1 (x1) – (Shared with PCIe Interface #0 lane 2)
PEX2_TX+/–
DIFF OUT
PEX2_RX+/–
DIFF IN
PEX2_REFCLK+/–
PEX2_CLKREQ#
PEX2_RST#
Series 0.1uF Capacitor
Series 0.1uF capacitors if
device on main PCB.
DIFF OUT
I/O
O
56KΩ pullup to
VDD_3V3_SYS on each line
(exists on the module)
Differential Transmit Data Pairs: Connect to TX+/– pins of PCIe
connector or RX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Receive Data Pairs: Connect to RX_+/– pins of PCIe
connector or TX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Reference Clock Output: Connect to REFCLK_+/– pins of
PCIe device/connector.
PEX Clock Request for PEX2_REFCLK: Connect to CLKREQ pin on
device/connector(s)
PEX Reset: Connect to PERST pin on device/connector.
PCIe Interface #2 (x1) – Muxed with USB 3.0 Port #0 on USB_SS0
PEX1_TX+/–
DIFF OUT
PEX1_RX+/–
DIFF IN
PEX1_REFCLK+/–
PEX1_CLKREQ#
PEX1_RST#
PEX_WAKE#
Note:
Series 0.1uF Capacitor
Series 0.1uF capacitors if
device on main PCB.
DIFF OUT
I/O
O
I
56KΩ pullup to
VDD_3V3_SYS on each line
(exists on the module)
56KΩ pullup to
VDD_3V3_SYS (exists on the
module)
Differential Transmit Data Pairs: Connect to TX+/– pins of PCIe
connector or RX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Receive Data Pairs: Connect to RX_+/– pins of PCIe
connector or TX_+/– pin of PCIe device through AC cap according to
supported configuration.
Differential Reference Clock Output: Connect to REFCLK_+/– pins of
PCIe device/connector
PEX Clock Request for PEX1_REFCLK: Connect to CLKREQ pin on
device/connector(s)
PEX Reset: Connect to PERST pin on device/connector(s)
PEX Wake: Connect to WAKE pins on devices or connectors
Check “Supported USB 3.0, PEX & SATA Interface Mappings” tables earlier in this section for PCIE IF mapping options.
Table 25. Recommended PCIe observation (test) points for initial boards
Test Points Recommended
One for each of the PCIe TX_+/– output lines used.
One for each of the PCIe RX_+/– input lines used.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Location
Near PCIe device. Connector pins may serve as test points if accessible.
Near the module connector.
32
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
5.3 SATA
A Gen 2 SATA controller is implemented on Jetson TX2/TX2i. The interface is brought to the module connector as show n in the
figure below .
Figure 18. SATA Connection Example
Jetson TX2/TX2i
1
Tegra
2
SATA_TX+
PEX_TX5P
PEX_TX5N
PEX_RX5P
PEX_RX5N
PEX, USB
3.0 & SATA
SATA_TX–
SATA_RX+
SATA_RX–
PEXCTL
D45
D46
PEX_L2_CLKREQ_N
Mux
SEL
PMIC
SATA_DEV_SLP
4
0.01uF
0.01uF
G45
G46
5
6
7
VDD_1V8
PEX1_CLKREQ#
3
0.01uF
0.01uF
VDD_3V3_SLP
8
C47
D47
9
Level
Shifter
10
11
12
13
GPIO7
14
15
VDD_5V0_IO_SLP
16
17
18
19
VDD_12V_SLP
20
21
22
SATA Design Guidelines
Table 26. SATA Signal Routing Requirements
Parameter
Specification
Max Frequency
Bit Rate / UI
Topology
Configuration / Device Organization
Max Load (per pin)
Termination
Impedance
Reference plane
Trace Impedance
Differential Pair / Single Ended
Spacing
Trace Spacing
Pair-to-pair (inter-pair)
Stripline / Microstrip
To plane & capacitor pad
Stripline / Microstrip
To unre lated high-speed signals
Stripline / Microstrip
Length/Skew
Breakout region
Max Length
Spacing
Max Trace Length/Delay
Max PCB Via distance from pin
Max Within Pair (Intra-Pair) Skew
Intra-pair matching between subsequent discontinuities
Requirement
Units
Notes
3.0 / 333.3
Point to point
1
0.5
100
Gbps / ps
1.5GHz
Unidirectional, differential
Differential pair uncoupled length
AC Cap
AC Cap Value
typical (max)
AC Cap Location (max distance from adjacent discontinuities)
GND
95 / 45-55
load
pf
Ω
On die termination
Ω
±15%
3x / 4x
3x / 4x
3x / 4x
Dielectric
41.9
Min width/spacing
76.2 (480)
6.29 (41.9)
0.15 (0.5)
0.15 (0.5)
ps
6.29 (41.9)
mm (ps)
0.01 (0.012)
8 (53.22)
uF
mm (ps)
Mm (ps)
mm (ps)
mm (ps)
mm (ps)
4x or wider dielectric height spacing is
preferred
Do trace length matching before hitting
discontinuities
The AC cap location should be located as
close as possible to nearby
discontinuities.
Via
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
33
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Parameter
GND Via Placement
Requirement
Units
Notes
Place ground vias as symmetrically as possible to data pair vias
GND via distance should be placed less than 1x the diff pair via pitch
3
If all are through-hole
< 0.4
mm
Max # of vias
Via stub length
Voiding
AC cap pad voiding
Voiding the plane directly under the pad 3-4 mils larger than the pad size is
recommended
The size of voiding can be same as the size of pin pad
Connector voiding (Required)
ESD
ESD protection device (Optional)
Type: SEMTECH RClamp0524p. Place ESD component near connector.
A design may include the footprints for ESD as a stuffing option. The junction
capacitance in ESD may cause effect on signal integrity, so it’s important to choose
an ESD component with low capacitance and whose package design is optimized
for high speed links. The SEMTECH ESD Rclamp0524p has been well verified with
its 0.3pF capacitance.
8 (53)
mm (ps)
Max distance from ESD Device to Connector
Recommended ESD layout
Choke
Preferred device
Type: TDK ACM2012D-900-2P. Only if
needed. Place near connector. Refer to
Common Mode Choke Requirement
section.
Location - Max distance from to adjacent discontinuities – ex,
connector, AC cap)
Common-mode impe dance @ 100MHz
Min/Max
Max Rdc
Differential TDR impedance
8 (53)
mm (ps)
65/90
0.3
90
Ω
Ω
Ω @TR200ps
(10%-90%)
Min Sdd21 @ 2.5GHz
Max Scc21 @ 2.5GHz
2.22
19.2
dB
dB
135
4x
1.5x
3x
deg (a)
Serpentine
Min bend angle
Dimension
Min A Spacing
Min B, C Length
Min Jog Width
MIsc.
Routing over voids
Noise Coupling
Note:
Trace width
TDK ACM2012D-900-2P
S1 must be
taken care in
order to
consider Xtalk
to adjacent pair
Where signal pair approaches Vias, maximal trace length across void
on plane is 1.27mm
Keep critical SATA related traces such as SATA_TX/RX, SATA_TERM etc. away from
other signal traces or unrelated power traces/areas or power supply components
If routing to SATA device or SATA connector includes a flex or 2 nd PCB, the total routing including all PCBs/flexes must be used
for the max trace & skew calculations
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
34
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 27. SATA Signal Connections
Module Pin Name
SATA_TX+/–
SATA_RX+/–
SATA_DEV_SLP
Type
DIFF OUT
Termination
Series 0.01uF Capacitor
DIFF IN
Series 0.01uF Capacitor
O
1.8V to 3.3V level shifter
Description
Differential Transmit Data Pair: Connect to SATA+/– pins of SATA
device/connector through termination (capacitor)
Differential Receive Data Pair: Connect to SATA+/– pins of SATA
device/connector through termination (capacitor)
SATA Device Sleep: Connect through level shifter to matching pin
on device or connector (pin 10 of Connector show in example).
Table 28. Recommended SATA observation (test) points for initial boards
Test Points Recommended
One for each of the SATA_TX_+/– output lines.
One for each of the SATA_RX_+/– input lines.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Location
Near SATA device. Connector pins may serve as test points if accessible.
Near the module connector.
35
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
6.0 GIGABIT ETHERNET
Jetson TX2/TX2i integrates a BCM54610C1IMLG Ethernet PHY. The magnetics & RJ45 connector are implemented on the
Carrier board. Contact Broadcom for the Carrier board placement/routing guidelines.
Table 29. Gigabit Ethernet Pin Descriptions
Usage on Carrier
Board
Pin # Module Pin Name
Tegra Signal
Usage/Description
E47
F50
F46
E49
E48
F48
F47
G49
G48
H48
H47
−
−
−
−
−
−
−
−
−
−
−
GbE RJ45 connector Link ACT (LED0)
GbE RJ45 connector Link 100 (LED1)
GbE RJ45 connector Link 1000 (LED2)
GbE Transformer Data 0–
GbE Transformer Data 0+
GbE Transformer Data 1–
GbE Transformer Data 1+
GbE Transformer Data 2–
GbE Transformer Data 2+
GbE Transformer Data 3–
GbE Transformer Data 3+
GBE_LINK_ACT#
GBE_LINK100#
GBE_LINK1000#
GBE_MDI0–
GBE_MDI0+
GBE_MDI1–
GBE_MDI1+
GBE_MDI2–
GBE_MDI2+
GBE_MDI3–
GBE_MDI3+
Direction
Output
Output
Output
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
LAN
Pin Type
CMOS – 3.3V tolerant
MDI
Figure 19. Ethernet Connections
Jetson TX2/TX2i
Tegra
SDMMC2_HV
GbE
Tranceiver
EQOS_TXC
EQOS_TD0
EQOS_TD1
EQOS_TD2
EQOS_TD3
EQOS_TX_CTL
EQOS_RXC
EQOS_RD0
EQOS_RD1
EQOS_RD2
EQOS_RD3
EQOS_RX_CTL
EQOS_MDC
EQOS_MDIO
DMIC4_DAT
DMIC4_CLK
E48
GBE_MDI0–
E49
GBE_MDI1+
F47
F48
GBE_MDI1–
GBE_MDI2+
G48
G49
GBE_MDI2–
GBE_MDI3+
GBE_LINK_ACT
E47
F50
GBE_LINK_100
GBE_LINK_1000
VDD_3V3_SYS
ENETPHY_RST
To Magnetics /
RJ45 Connector
H47
H48
GBE_MDI3–
1.8V
AUDIO_HV
GBE_MDI0+
F46
H50
GBE_CTREF
3.3V
LS
ENETPHY_INT
VDD_1V8
Figure 20. Gigabit Ethernet Magnetics & RJ45 Connections
Magnetics
GBE_MDI0+
+
CT
–
+
CT
–
+
CT
–
+
CT
–
GBE_MDI0–
GBE_MDI1+
GBE_MDI1–
GBE_MDI2+
GBE_MDI2–
GBE_MDI3+
GBE_MDI3–
VDD_3V3_SLP
+
CT
–
+
CT
–
+
CT
–
+
CT
–
VDD_3V3_SLP
TDP
75Ω
0.1uF
TDN
RDP
RJ45
14
9
10
75Ω
1
RDN
TDP1
3
5
75Ω
7
TDN1
RDP1
11
4
6
8
12
13
75Ω
RDN1
ESD 10nF 10nF 10nF 10nF
2
100pF
1nF
0.1uF
GBE_LINK_ACT
GBE_LED0_SPICSB
GBE_LINK_100
GBE_LED1_SPISCK
681Ω,1%
0.1uF
681Ω,1%
Note:
The connections above match those used on the carrier board and are shown for reference.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
36
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 30. Ethernet MDI Interface Signal Routing Requirements
Parameter
Reference plane
Trace Impedance
Diff pair / Single Ended
Min Trace Spacing (Pair-Pair)
Max Trace Length
Max Within Pair (Intra-Pair) Skew
Number of Vias
Requirement
GND
100 / 50
0.763
109 (690)
0.15 (1)
minimum
Units
Notes
Ω
±15%. Differential impedance target is 100Ω. 90Ω can be used if 100Ω
is not achievable
mm
mm (ps)
mm (ps)
Ideally there should be no vias, but if required for breakout to Ethernet
controller or magnetics, keep very close to either device.
Table 31. Ethernet Signal Connections
Module Pin Name
GBE_MDI[3:0]+/–
GBE_LINK_ACT
GBE_LINK100
Type
DIFF
I/O
O
O
GBE_LINK1000
GBE_CTREF
O
na
Termination
ESD device to GND per signal
Description
Gigabit Ethernet MDI IF Pairs: Connect to Magnetics +/– pins
681Ω series resistor & 0.1uF capacitor to GND
681Ω series resistor & 0.1uF capacitor to GND.
10kΩ Pull-down to GND (exists on the module)
681Ω series resistor & 0.1uF capacitor to GND
Gigabit Ethernet ACT : Connect to LED1C on Ethernet connector.
Gigabit Ethernet Link 100 : Connect to LED2C on Ethernet connector.
Pulldown part of strapping to use 3.3V PHY mode.
Gigabit Ethernet Link 1000 : Connect to Link 1000 LED on conn.
Not used
Table 32. Recommended Gigabit Ethernet observation (test) points for initial boards
Test Points Recommended
One for each of the MDI[3:0]+/– lines.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Location
Near the module connector & Magnetics device.
37
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
7.0 DISPLAY
Jetson TX2/TX2i designs can select from several display options including MIPI DSI & eDP for embedded displays, and HDMI
or DP for external displays. Three display controllers are available, so the possible display combinations are:
▪
▪
▪
DP/HDMI + eDP + single/dual-link-DSI
DP/HDMI + single-link-DSI + single-link-DSI
DP/HDMI + DP/HDMI + single/dual-link-DSI
Table 33. Display General Pin Descriptions
Pin #
A26
A27
A25
B26
B28
B27
A24
Module Pin Name
GSYNC_HSYNC
GSYNC_VSYNC
LCD_TE
LCD_VDD_EN
LCD_BKLT_EN
LCD0_BKLT_PWM
LCD1_BKLT_PWM
Tegra Signal
GPIO_DIS4
GPIO_DIS2
GPIO_DIS1
GPIO_EDP0
GPIO_DIS3
GPIO_DIS0
GPIO_DIS5
Usage/Description
GSYNC Horizontal Sync
GSYNC Vertical Sync
Display Tearing Effect
Display VDD Enable
Display Backlight Enable
Display Backlight PWM 0
Display Backlight PWM 1
Usage on Carrier Board
Display Connector
Direction
Output
Output
Input
Output
Output
Output
Output
Pin Type
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
7.1 MIPI DSI
Jetson TX2/TX2i supports eight total MIPI DSI data lanes. Each data lane has a peak bandw idth up to 1.5Gbps. The lanes can
be configured in Dual Link & Split Link modes. The follow ing configurations are possible:
Dual Link Mode (Up to 8 PHY lanes):
▪
DSI-A (1x4) + DSI-C (1x4) to single display
▪
DSI-A (1x4) to one display, DSI-C (1x4) to a second display
Split Link Mode (Up to 8 PHY lanes):
▪
Two Links with 1-lane each: DSI-A(1x1) + DSI-B (1x1) or DSI-C (1x1) + DSI-D (1x1)
▪
Two Links with 2-lane each: DSI-A(1x2) + DSI-B (1x2) or DSI-C (1x2) + DSI-D (1x2)
▪
Four Links with 1-lane each: DSI-A(1x1) + DSI-B (1x1) + DSI-C (1x1) + DSI-D (1x1)
▪
Four Links with 2-lane each: DSI-A(1x2) + DSI-B (1x2) + DSI-C (1x2) + DSI-D (1x2)
Table 34. DSI Pin Descriptions
Pin #
G34
G33
F35
F34
H33
H32
D34
D33
C35
C34
E33
E32
G31
G30
F32
F31
H30
H29
D31
D30
C32
C31
E30
E29
Module Pin Name
DSI0_CLK–
DSI0_CLK+
DSI0_D0–
DSI0_D0+
DSI0_D1–
DSI0_D1+
DSI1_CLK–
DSI1_CLK+
DSI1_D0–
DSI1_D0+
DSI1_D1–
DSI1_D1+
DSI2_CLK–
DSI2_CLK+
DSI2_D0–
DSI2_D0+
DSI2_D1–
DSI2_D1+
DSI3_CLK–
DSI3_CLK+
DSI3_D0–
DSI3_D0+
DSI3_D1–
DSI3_D1+
Tegra Signal
DSI_A_CLK_N
DSI_A_CLK_P
DSI_A_D0_N
DSI_A_D0_P
DSI_A_D1_N
DSI_A_D1_P
DSI_B_CLK_N
DSI_B_CLK_P
DSI_B_D0_N
DSI_B_D0_P
DSI_B_D1_N
DSI_B_D1_P
DSI_C_CLK_N
DSI_C_CLK_P
DSI_C_D0_N
DSI_C_D0_P
DSI_C_D1_N
DSI_C_D1_P
DSI_D_CLK_N
DSI_D_CLK_P
DSI_D_D0_N
DSI_D_D0_P
DSI_D_D1_N
DSI_D_D1_P
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage/Description
Display, DSI 0 Clock–
Display, DSI 0 Clock+
Display, DSI 0 Data 0–
Display, DSI 0 Data 0+
Display, DSI 0 Data 1–
Display, DSI 0 Data 1+
Display DSI 1 Clock–
Display DSI 1 Clock+
Display, DSI 1 Data 0–
Display, DSI 1 Data 0+
Display, DSI 1 Data 1–
Display, DSI 1 Data 1+
Display DSI 2 Clock–
Display DSI 2 Clock+
Display, DSI 2 Data 0–
Display, DSI 2 Data 0+
Display, DSI 2 Data 1–
Display, DSI 2 Data 1+
Display DSI 3 Clock–
Display DSI 3 Clock+
Display, DSI 3 Data 0–
Display, DSI 3 Data 0+
Display, DSI 3 Data 1–
Display, DSI 3 Data 1+
Usage on Carrier Board
Display Connector
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pin Type
MIPI D-PHY
38
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 21: DSI Dual Link Connections
Jetson TX2/TX2i
Display
Connector (DSI)
Tegra
DSI/CSI
Note:
DSI_A_CLK_P
DSI_A_CLK_N
DSI_A_D0_P
DSI_A_D0_N
DSI_A_D1_P
DSI_A_D1_N
DSI0_CK+
DSI_B_CLK_P
DSI_B_CLK_N
DSI_B_D0_P
DSI_B_D0_N
DSI_B_D1_P
DSI_B_D1_N
DSI1_CK+
DSI_C_CLK_P
DSI_C_CLK_N
DSI_C_D0_P
DSI_C_D0_N
DSI_C_D1_P
DSI_C_D1_N
DSI2_CK+
DSI_D_CLK_P
DSI_D_CLK_N
DSI_D_D0_P
DSI_D_D0_N
DSI_D_D1_P
DSI_D_D1_N
DSI3_CK+
DSI0_CK–
DSI0_D0+
DSI0_D0–
DSI0_D1+
DSI0_D1–
DSI1_CK–
DSI1_D0+
DSI1_D0–
DSI1_D1+
DSI1_D1–
DSI2_CK–
DSI2_D0+
DSI2_D0–
DSI2_D1+
DSI2_D1–
DSI3_CK–
DSI3_D0+
DSI3_D0–
DSI3_D1+
DSI3_D1–
A_CLKP
A_CLKN
A_D0P
A_D0N
A_D1P
A_D1N
G33
G34
F34
F35
H32
H33
4-Lane
D33
D34
C34
C35
E32
E33
EMI/ESD
G30
G31
F31
F32
H29
H30
D30
D31
C31
C32
E29
E30
A_D2P
A_D2N
A_D3P
A_D3N
B_CLKP
B_CLKN
B_D0P
B_D0N
B_D1P
B_D1N
Each 4-lane
interface can go to
a separate display,
or both can go to a
single display.
4-Lane
B_D2P
B_D2N
B_D3P
B_D3N
If EMI/ESD devices are necessary, they must be tuned to minimize impact to signal quality, which must meet the DSI spec.
requirements for the frequencies supported by the design.
Figure 22: DSI Split Link Connections
Jetson TX2/TX2i
Display
Connector (DSI)
Tegra
DSI/CSI
DSI_A_CLK_P
DSI_A_CLK_N
DSI_A_D0_P
DSI_A_D0_N
DSI_A_D1_P
DSI_A_D1_N
DSI0_CK+
DSI_B_CLK_P
DSI_B_CLK_N
DSI_B_D0_P
DSI_B_D0_N
DSI_B_D1_P
DSI_B_D1_N
DSI1_CK+
DSI_C_CLK_P
DSI_C_CLK_N
DSI_C_D0_P
DSI_C_D0_N
DSI_C_D1_P
DSI_C_D1_N
DSI2_CK+
DSI_D_CLK_P
DSI_D_CLK_N
DSI_D_D0_P
DSI_D_D0_N
DSI_D_D1_P
DSI_D_D1_N
DSI3_CK+
DSI0_CK–
DSI0_D0+
DSI0_D0–
DSI0_D1+
DSI0_D1–
DSI1_CK–
DSI1_D0+
DSI1_D0–
DSI1_D1+
DSI1_D1–
DSI2_CK–
DSI2_D0+
DSI2_D0–
DSI2_D1+
DSI2_D1–
DSI3_CK–
DSI3_D0+
DSI3_D0–
DSI3_D1+
DSI3_D1–
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
CLK_P
CLK_N
D0_P
D0_N
D1_P
D1_N
1-2
Lanes
CLK_P
CLK_N
D0_P
D0_N
D1_P
D1_N
1-2
Lanes
G30
G31
F31
F32
H29
H30
CLK_P
CLK_N
D0_P
D0_N
D1_P
D1_N
1-2
Lanes
D30
D31
C31
C32
E29
E30
CLK_P
CLK_N
D0_P
D0_N
D1_P
D1_N
1-2
Lanes
G33
G34
F34
F35
H32
H33
D33
D34
C34
C35
E32
E33
EMI/ESD
39
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 23: Display Backlight/Control Connections
Jetson TX2/TX2i
Tegra
SYS
LCD_BKLT_EN
GPIO_DIS3
GPIO_DIS0
GPIO_DIS5
GPIO_DIS1
eDP
LCD0_BKLT_PWM
LCD1_BKLT_PWM
LCD_TE
LCD_VDD_EN
GPIO_EDP0
B2 8
B2 7
A24
A25
B2 6
Backlight
Control
Tearing Effect
Display
Power Enable
MIPI DSI / CSI Design Guidelines
Table 35. MIPI DSI & CSI Interface Signal Routing Requirements
Parameter
Max Frequency/Data Rate (per data lane)
HS (DSI)
HS (CSI)
LP
Requirement
0.75 / 1.5
1.25 / 2.5
10
1
10
GND
45-50
48
90-100 / 45-50
< 3.8 (24)
2x / 2x
1100
800
350
Units
GHz/Gbps
MHz
Number of Loads
Max Loading (per pin)
Reference plane
Breakout Region Impedance (Single Ended)
Max PCB breakout delay
Trace Impedance
Diff pair / Single Ended
Via proximity (Signal to reference)
Trace spacing
Microstrip / Stripline
Max Trace Delay
1 Gbps
1.5 Gbps
2.5 Gbps
Max Intra-pair Skew
1
Max Trace Delay Skew between DQ & CLK
5
Keep critical DSI/CSI related traces including DSI/CSI clock/data traces & RDN/RUP traces away from
traces/areas or power supply components
Note:
1.
2.
3.
Notes
load
pF
Ω
ps
Ω
mm (ps)
dielectric
mm (ps)
See Note 1
±15%
See Note 2
See Note 3
See Note 3
See Note 3
other signal traces or unrelated power
ps
ps
If PWR, 0.01uF decoupling cap required for return current
Up to 4 signal Vias can share a single GND return Via
If routing to device includes a flex or 2nd PCB, the max trace & skew calculations must include all the PCBs/flex routing
MIPI DSI / CSI Connection Guidelines
Table 36. MIPI DSI Signal Connections
Module Pin Name
DSI[3:0]_CK+/–
Type
DIFF OUT
DSI[3:0]_D[1:0]+/–
DIFF OUT
LCD_TE
LCD_BL_EN
LCD[1:0]_BKLT_PWM
I
O
O
LCD_VDD_EN
O
Termination
Description
DSI Differential Clocks: Connect to CLKn & CLKp pins of receiver. See
connection diagrams for Dual & Split Link Mode configurations.
DSI Differential Data Lanes: Connect to Dn & Dp pins of DSI display. See
connection diagrams for Dual & Split Link Mode configurations.
LCD Tearing Effect: Connect to LCD Tearing Effect pin if supported
LCD Backlight Enable: Connect to LCD backlight solution enable if supported
LCD Backlight Pulse Width Modulation: Connect to LCD backlight solution PWM
input if supported
LCD Power Enable: Connect as necessary to enable appropriate Display power
supply(ies).
Table 37. Recommended DSI observation (test) points for initial boards
Test Points Recommended
One for each signal line.
Note:
Location
Near display. Panel connector pins can be used if accessible.
Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
40
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
7.2 eDP / DP / HDMI
Jetson TX2/TX2i includes tw o interfaces (DP0 & DP1). Both support eDP / DP or HDMI. See Jetson TX2/TX2i Data Sheet for
the maximum resolution supported.
Table 38. HDMI / eDP / DP Pin Descriptions
Usage on the Carrier
Board
Pin # Module Pin Name
Tegra Signal
Usage/Description
Direction
Pin Type
B34
DP0_AUX_CH–
DP_AUX_CH0_N
Display Port 0 Aux– or HDMI DDC SDA
Bidir
B35
DP0_AUX_CH+
DP_AUX_CH0_P
Display Port 0 Aux+ or HDMI DDC SCL
Bidir
AC-Coupled on Carrier
Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C)
H38
H39
F37
F38
G36
G37
H35
H36
B36
A34
DP0_TX0–
DP0_TX0+
DP0_TX1–
DP0_TX1+
DP0_TX2–
DP0_TX2+
DP0_TX3–
DP0_TX3+
DP0_HPD
DP1_AUX_CH–
HDMI_DP0_TXDN2
HDMI_DP0_TXDP2
HDMI_DP0_TXDN1
HDMI_DP0_TXDP1
HDMI_DP0_TXDN0
HDMI_DP0_TXDP0
HDMI_DP0_TXDN3
HDMI_DP0_TXDP3
DP_AUX_CH0_HPD
DP_AUX_CH1_N
DisplayPort 0 Lane 0– or HDMI Lane 2–
DisplayPort 0 Lane 0+ or HDMI Lane 2+
DisplayPort 0 Lane 1– or HDMI Lane 1–
DisplayPort 0 Lane 1+or HDMI Lane 1+
DisplayPort 0 Lane 2– or HDMI Lane 0–
DisplayPort 0 Lane 2+ or HDMI Lane 0+
DisplayPort 0 Lane 3– or HDMI Clk Lane–
DisplayPort 0 Lane 3+ or HDMI Clk Lane+
Display Port 0 Hot Plug Detect
Display Port 1 Aux– or HDMI DDC SDA
A35
DP1_AUX_CH+
DP_AUX_CH1_P
Display Port 1 Aux+ or HDMI DDC SCL
E38
E39
C37
C38
D36
D37
E35
E36
A33
B33
DP1_TX0–
DP1_TX0+
DP1_TX1–
DP1_TX1+
DP1_TX2–
DP1_TX2+
DP1_TX3–
DP1_TX3+
DP1_HPD
HDMI_CEC
HDMI_DP1_TXDN2
HDMI_DP1_TXDP2
HDMI_DP1_TXDN1
HDMI_DP1_TXDP1
HDMI_DP1_TXDN0
HDMI_DP1_TXDP0
HDMI_DP1_TXDN3
HDMI_DP1_TXDP3
DP_AUX_CH1_HPD
HDMI_CEC
DisplayPort 1 Lane 0– or HDMI Lane 2–
DisplayPort 1 Lane 0+ or HDMI Lane 2+
DisplayPort 1 Lane 1– or HDMI Lane 1–
DisplayPort 1 Lane 1+ or HDMI Lane 1+
DisplayPort 1 Lane 2– or HDMI Lane 0–
DisplayPort 1 Lane 2+ or HDMI Lane 0+
DisplayPort 1 Lane 3– or HDMI Clk Lane–
DisplayPort 1 Lane 3+ or HDMI Clk Lane+
Display Port 1 Hot Plug Detect
HDMI CEC
Note:
Output
Output
Output
Output
Output
Output
Output
Output
Input
Bidir
Display Connector
Bidir
HDMI Type A Conn.
Output
Output
Output
Output
Output
Output
Output
Output
Input
Bidir
AC-Coupled on carrier
board
CMOS – 1.8V
AC-Coupled on Carrier
Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C)
AC-Coupled on carrier
board
CMOS – 1.8V
Open Drain, 3.3V
In the Connection figures & tables, the “x” in the signal/power rail names indicates that the interface can come from either
HDMI_DP0 or HDMI_DP1. The interface must include only signals from one or the other (not mixed).
Table 39. DP/HDMI Pin Mapping
Module Pin Name
Module Pin #s
Tegra Pin Name
Tegra Pin #s
HDMI
DP
H39
H38
F38
F37
G37
G36
H36
H35
HDMI_DP0_TXDP2
HDMI_DP0_TXDN2
HDMI_DP0_TXDP1
HDMI_DP0_TXDN1
HDMI_DP0_TXDP0
HDMI_DP0_TXDN0
HDMI_DP0_TXDP3
HDMI_DP0_TXDN3
E4
E5
C3
B3
A3
B4
C1
C2
TX2+
TX2–
TX1+
TX1–
TX0+
TX0–
TXC+
TXC–
TX0+
TX0–
TX1+
TX1–
TX2+
TX2–
TX3+
TX3–
E39
E38
C38
C37
D37
D36
E36
E35
HDMI_DP1_TXDP2
HDMI_DP1_TXDN2
HDMI_DP1_TXDP1
HDMI_DP1_TXDN1
HDMI_DP1_TXDP0
HDMI_DP1_TXDN0
HDMI_DP1_TXDP3
HDMI_DP1_TXDN3
A5
A6
C5
B5
D5
D6
C6
B6
TX2+
TX2–
TX1+
TX1–
TX0+
TX0–
TXC+
TXC–
TX0+
TX0–
TX1+
TX1–
TX2+
TX2–
TX3+
TX3–
DP0
DP0_TX0+
DP0_TX0–
DP0_TX1+
DP0_TX1–
DP0_TX2+
DP0_TX2–
DP0_TX3+
DP0_TX3–
DP1
DP1_TX0+
DP1_TX0–
DP1_TX1+
DP1_TX1–
DP1_TX2+
DP1_TX2–
DP1_TX3+
DP1_TX3–
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
41
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
7.2.1 EDP/DP
Figure 24: eDP / DP Connection Example
See Note 2
3.3V
Jetson TX2/TX2i
DP0/DP1
DPx_AUX_CH+
DP_AUX_CHx_P
DP_AUX_CHx_N
DPx_AUX_CH–
DPx_HPD
DP_AUX_CHx_HPD
DP[1:0]
Note:
1.
HDMI_DPx_TXDP0
HDMI_DPx_TXDN0
DPx_TX2
HDMI_DPx_TXDP1
HDMI_DPx_TXDN1
DPx_TX1
HDMI_DPx_TXDP2
HDMI_DPx_TXDN2
DPx_TX0
HDMI_DPx_TXDP3
HDMI_DPx_TXDN3
DPx_TX3
B3 5/A35
B3 4/A34
B3 6/A33
0.1uF
DPx_TX0
DPx_TX3
0.1uF 10uF
0.1uF
See Note 1
Level Shifter
100kΩ
1kΩ
EMI/
ESD
AUX+
AUX–
HPD
G37/D37
DPx_TX2
G36/D36
DPx_TX1
100kΩ
Tegra
EDP
eDP / DP Connector
+3.3V
F38/C3 8
0.1uF
0.1uF
LN2+
LN2–
0.1uF
LN1+
LN1–
0.1uF
F37/C3 7
0.1uF
0.1uF
H39/E3 9
H38/E3 8
EMI/ESD
0.1uF
H36/E3 6
2-lane
4-lane
LN3+
LN3–
0.1uF
H35/E3 5
LN0+
LN0–
A Lev el shifter is required on HPD to av oid the pin from being driv en when the module is off. The lev el shifter must be noninv erting (preserv e the polarity of the HPD signal from the display ).
Pull-up/down only required for DP – not for eDP.
If EMI dev ices are necessary , they must be tuned to minimize the impact to signal quality , which must meet the timing &
electrical requirements of the Display Port specification for the modes to be supported. Any ESD solution must also maintain
signal integrity & meet the Display Port requirements for the modes to be supported.
2.
3.
eDP Routing Guidelines
Figure 25: eDP / DP (Differential Main Link) Topology
Jetson TX2/TX2i
Common Mode
Chokes & ESD
Tegra
DP
Driver
P
eDP
Conn
Pkg
N
Table 40. eDP / DP Main Link Signal Routing Requirements (Including DP_AUX)
Parameter
Specification
Max Data Rate / Min UI
Requirement
HBR2
HBR
RBR
Number of Loads / Topology
Termination
Electrical Spec
Insertion Loss
E-HBR @ 0.675GHz
PBR 0.68GHz
HBR 1.35GHz
HBR2 @ 2.7GHz
Resonance dip frequency
TDR dip
FEXT
@ DC
@ 2.7GHz
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
5.4 / 185
2.7 / 370
1.62 / 617
1
100
<=0.7
<=0.7
<=1.2
<=2.4
>8
>85
<= -40dB
<= -30dB
Units
Gbps / ps
load
Ω
Notes
Per data lane
Point-Point, Differential, Unidirectional
On die at TX/RX
dB
dB
dB
dB
GHz
Ω
@ Tr-200ps (10%-90%)
IL/FEXT plot – up to HBR2
42
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Parameter
Impedance
Trace Impedance
Requirement
Diff pair
100
90
85
Units
Ω (±10%)
Notes
-
Reference Plane
Trace Length, Spacing & Skew
Trace loss characteristic @ 2.7GHz
GND
< 0.81
Max PCB Via dist. from module conn. RBR/HBR
HBR2
Max trace length from module to connector
RBR/HBR (Stripline / Microstrip)
HBR2 (Stripline)
HBR2 (Microstrip, 5x / 7x)
Trace spacing (Pair-Pair)
Stripline
Microstrip (HBR/RBR)
Microstrip (HBR2)
Trace spacing
Stripline/Microstrip
(Main Link to AUX)
Max Intra-pair (within pair) Skew
No requirement
7.63 (0.3)
dB/in
The following max length is derived based on this
characteristic. See note 2.
mm (in)
165 (1137.5)/(975)
101.6 (700)
89 (525) / 101.6 (600)
3x
4x
5x to 7x
3x / 5x
mm (ps)
dielectric
0.15 (1)
mm (ps)
175ps/inch assumption for Stripline, 150ps/inch
for Microstrip.
dielectric
-
Max Inter-pair (pair-pair) Skew
Via
Max GND transition Via distance
Via Structure
Impedance dip
Recommende d via dimens ion
for impedance control
100Ω is the spec. target. 95/85Ω are
implementation options (Zdiff does not
account f or trace coupling)
95Ω should be used to support DP-HDMI colay out as HDMI 2.0 requires 100Ω impedance
(see HDMI section for addition of series
resistor R S).
85Ω can be used if eDP/DP only & is
pref erable as it can provide better trace loss
characteristic performance. See Note 1.
Drill/Pad
Antipad
Via pitch
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Do not perform length matching within
breakout region
Do trace length matching before hitting
discontinuity (i.e. matching to <1ps
before the vias or any discontinuity to
minimize common mode conversion).
150
ps
< 1x
diff pair pitch
For signals switching reference layers, add
symmetrical GND stitching Via near signal Vias.
≥97
≥92
Ω @ 200ps
Ω @ 35ps
The via dimension must be required for the HDMIDP co-layout condition.
200/400
>840
≥880
um
um
um
43
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Parameter
Topology
Requirement
Units
Y -pattern is recommended
keep sy mmetry
Notes
Xtalk suppression is best using the Y-pattern.
It can also reduce the limit of pair-pair
distance.
For in-line via, the distance from a via of one
lane to the adjacent via from other lane >=
1.2mm center-center.
GND via
Max # of Vias
PTH vias
Micro Vias
Max Via Stub Length
Serpentine
Min bend angle
Dimension
AC Cap
Value
Max Dist. from A C cap
to connector
Voiding
Connector
Voiding
Min A Spacing
Min B, C Length
Min Jog Width
Place GND via as symmetrically as possible to
data pair vias. Up to 4 signal vias (2 diff
pairs) can share a single GND return via
4 if all vias are PTH via
Not limited as long as total channel loss
meets IL spec
0.4
mm
GND via is used to maintain return path, while its
Xtalk suppression is limited
135
4x
1.5x
3x
S1 must be taken care in
order to consider Xtalk to
adjacent pair
RBR/HBR
HBR2
RBR/HBR
HBR2
0.1
No requirement
0.5
No requirement
Voiding required
RBR/HBR
HBR2
No requirement
Voiding required
deg (a)
Trace width
uF
Discrete 0402
in
HBR2: Voiding the plane directly under the pad 34 mils larger than the pad size is recommended.
HBR2: Standard DP Connector: Voiding
requirement is stack-up dependent. For typical
stack-ups, voiding on the layer under the
connector pad is required to be 5.7mil larger than
the connector pad.
Keep critical eDP related traces including differential clock/data traces & RSET trace away from other signal traces or unrelated power traces/areas or
power supply components
Notes:
1.
2.
3.
4.
For eDP/DP, the spec puts a higher priority on the trace loss characteristic than on the impedance. However, b efore
selecting 85Ω for impedance, it is important to make sure the selected stack-up, material & trace dimension can achieve
the needed low loss characteristic.
Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
max trace lengths will need to be reduced.
The average of the differential signals is used for length matching.
Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before Vias
or any discontinuity to minimize common mode conversion
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
44
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 41. eDP Signal Connections
Module Pin Name
DPx_TX[3:0]+/–
Type
O
Termination
Series 0.1uF capacitors on all lines
DPx_AUX+/–
DPx_HPD
I/OD
I
Series 0.1uF capacitors
Description
eDP/DP Differential CLK/Data Lanes: Connect to matching pins on display
connector. See DP/HDMI Pin Mapping & connection diagram for details.
eDP/DP: Auxiliary Channels: Connect to AUX_CH+/– on display connector.
eDP/DP: Hot Plug Detect: Connect to HPD pin on display connector.
Table 42. Recommended eDP/DP observation (test) points for initial boards
Test Points Recommended
One for each signal line.
Note:
Location
Near display connector. Connector pins can be used if accessible.
Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces
7.2.2 HDMI
A standard DP 1.2a or HDMI V2.0 interface is supported. These share the same set of interface pins, so either Display Port or
HDMI can be supported natively. Dual-Mode DisplayPort(DP++ ) can be supported, in w hich the DisplayPort connector logically
outputs TMDS signaling to a DP-to-HDMI dongle.
7.2.3 HDMI
Figure 26: HDMI Connection Example
Jetson TX2/TX2i
VDD_1V8 VDD_3V3_SYS
HDMI Connector
VDD_5V0_HDMI
HDMI_DPx
DP_AUX_CH1_P
DP_AUX_CH1_N
DPx_AUX_CH+
HDMI_CEC
HDMI_CEC
10kΩ
10kΩ
DP0/DP1
B3 6/A33
See Note 1
Level Shifter
1.8kΩ
DPx_HPD
1.8kΩ
DP_AUX_CH1_HPD
0.1uF
10uF
100kΩ
HPD
EMI
DPx_AUX_CH–
HDMI_DPx_TXDP0
HDMI_DPx_TXDN0
TXD0_P
DPx_TX2
TXD0_N
DPx_TX2
HDMI_DPx_TXDP1
HDMI_DPx_TXDN1
TXD1_P
TXD1_N
DPx_TX1
DPx_TX1
HDMI_DPx_TXDP2
HDMI_DPx_TXDN2
TXD2_P
TXD2_N
DPx_TX0
HDMI_DPx_TXDP3
HDMI_DPx_TXDN3
TXC_P
TXC_N
DPx_TX3
DPx_TX
DPx_TX3
SCL
SDA
Level Shifter
B3 5/A35
B3 4/A34
B3 3
CEC Gating
Circuitry
100kΩ
eDP
10kΩ
+5V
Tegra - HDMI
CEC
See Note 2
ESD
RS
0.1uF
G37/D37
G36/D36
0.1uF
RS
F38/C3 8
0.1uF
0.1uF
RS
F37/C3 7
H39/E3 9
H38/E3 8
H36/E3 6
H35/E3 5
RS
CMC
0.1uF
0.1uF
RS
RS
RS
0.1uF
0.1uF
RS
See Note 3
See
Note 2
,
1%
ESD
See
Note 4
D0+
D0D1+
D1D2+
D2CK+
CK-
00
@100MHz
5V0_HDMI_EN
Note:
1.
2.
3.
4.
5.
Enable
FET
Level shifters required on DDC/HPD. Jetson TX2/TX2i pads are not 5V tolerant & cannot directly meet HDMI V IL/VIH
requirements. HPD level shifter can be non-inverting or inverting.
If EMI/ESD devices are necessary, they must be tuned to minimize the impact to signal quality, which must meet the
timing & electrical requirements of the HDMI specification for the modes to be supported. See requirements &
recommendations in the related sections of the HDMI Interface Signal Routing Requirements table.
The HDMI_DP_TXx pads are native DP pads & require series AC capacitors (AC CAP) & pull-downs (RPD) to be HDMI
compliant. The 499Ω, 1% pull-downs must be disabled when Tegra is off to meet the HDMI V OFF requirement. The
enable to the FET, enables the pull-downs when the HDMI interface is to be used. Chokes between pull-downs & FET are
required for Standard Technology designs and recommended for HDI designs.
Series resistors RS are required. See the R S section of the HDMI Interface Signal Routing Requirements table for details.
Tegra supports a single CEC controller that can be associated with one of the display output heads.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
45
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 27: HDMI Clk/Data Topology
Jetson TX2/TX2i
Tegra
Common Mode
Chokes & ESD
AC CAP
Main Route –
Seg A
95-100Ω
0.1uF
0.1uF
RS
(See note 4)
Seg B
100Ω
* Note 3
Seg D
100Ω
* Note 3
Seg E
100Ω
* Note 3
Seg F
100Ω
* Note 3
100Ω
100Ω
100Ω
100Ω
95-100Ω
Seg C
HDMI
Conn
See Note 1
PCB Vias
499Ω,
1%
RPD
499Ω,
1%
PCB Vias
3.3V
Note:
Choke or Trace
See Note 2
RPD pad must be on the main trace. R PD & ACCAP must be on same layer.
Chokes (600Ω@100MHz) or narrow traces (1uH@DC-100MHz) between pull-downs & FET are required for Standard
Technology (through-hole) designs and recommended for HDI designs.
The trace after the main-route via should be routed on the Top or Bottom layer of the PCB, and either with 100ohm
differential impedance, or as uncoupled 50ohm Single Ended traces.
RS series resistor is required. See the R S section of the HDMI Interface Signal Routing Requirements table for details.
1.
2.
3.
4.
Table 43. HDMI Interface Signal Routing Requirements
Parameter
Specification
Max Frequency / UI
Topology
Termination
Requirement
Units
5.94 / 168
Point to point
At Receiver 100
On-board 500
Gbps / ps
Ω
Electrical Specification
IL
TDR dip
<= 1.7
<= 2
<= 3
<6
resonance dip frequency > 12
>= 85
FEXT (PSFEXT)
dB @ 1GHz
dB @ 1.5GHz
dB @ 3GHz
dB @ 6GHz
GHz
Ω @ Tr=200ps
<= -50
<= -40
<= -40
dB at DC
dB at 3GHz
dB at 6GHz
IL/FEXT plot
Impedance
Trace Impedance
Reference plane
Trace spacing/Length/Skew
Trace loss characteristic:
Diff pair 100
Notes
Per lane – not total link bandwidth
Unidirectional, Differential
Differential To 3.3V at receiver
To GND near connector
10%-90%. If TDR dip is 75~85ohm that dip width
should < 250ps
PSNEXT is derived from an algebraic summation of the
individual NEXT effects on each pair by the other pairs
TDR plot
Ω
±10%. Target is 100Ω. 95Ω for the breakout & main
route is an implementation option.
dB/in. @ 3GHz
dB/in. @ 1.5GHz
The max length is derived based on this characteristic.
See note 1.
GND
< 0.8
< 0.4
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
46
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Parameter
Trace spacing (Pair-Pair)
Requirement
Stripline
Microstrip: pre 1.4b
Microstrip: 1.4b/2.0
Trace spacing
Stripline
(Main Link to DDC)
Microstrip
Max Total Delay (1.4b/2.0 - up to
5.94Gbps)
Stripline
Microstrip (5x spacing)
Microstrip (7x spacing)
Max Total Delay (Pre-1.4b)
(up to 165Mhz)
Microstrip
Stripline
Max Intra-Pair (within pair) Skew
Max Inter-Pair (pair to pair) Skew
Max GND transition Via distance
Via
Topology
3x
4x
5x to 7x
3x
5x
63.5/2.5 (437)
50.8/2.0 (300)
63.5/2.5 (375)
Recommende d Via Dime nsion
drill/pad
Antipad
Via pitch
GND via
Connector pin via
-
Max Via Stub Length
Serpentine
Min bend angle
PTH via
u-via
dielectric
Notes
For Stripline, this is 3x of the thinner of above and
below.
For Stripline, this is 3x of the thinner of above and
below.
Propagation delay: 175ps/in. for stripline, 150ps/in. for
microstrip).
mm/in (ps)
Mm (ps)
ps
Diff pair via pitch
Ω@200ps
Ω@35ps
200/400
uM
840
880
Place GND via as symmetrically as possible to data pair
vias. Up to 4 signal vias (2 diff pairs) can share a single
GND return via
The break-in trace to the connector pin via should
-
Max # of Vias
dielectric
mm/in (ps)
254/10 (1500)
225/8.5 (1500)
0.15 (1)
150
1x
8. Y-pattern is recommended
9. keep symmetry
97
92
Minimum Impedance Dip
Units
Propagation delay: 175ps/in. for stripline, 150ps/in. for
microstrip).
See Notes 2, 3 & 4
See Notes 2, 3 & 4
For signals switching reference layers, add one or two
ground stitching vias. It is recommended they be
symmetrical to signal vias.
Xtalk suppression is the
best by Y-pattern. Also it
can reduce the limit of
pair-pair distance. Need
review (NEXT/FEXT check)
if via placement is not Ypattern.
GND via is used to maintain return path, while its Xtalk
suppression is limited
be routed on the BOTTOM in order to av oid v ia stub
ef f ect
Equal spacing (0.8mm) between adjacent signal
v ias.
The x-axis distance between signal and GND via
should be > 0.6mm
4 if all vias are PTH via
Not limited as long as total channel loss meets IL spec.
No breakout: ≤ 3 vias
0.4
mm
135
deg (a)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
breakout on the same layer as main trunk: ≤ 4 vias
long via stub requires review (IL & resonance dip check)
47
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Parameter
Dimension
Min A Spacing
Min B, C Length
Min Jog Width
Requirement
4x
1.5x
3x
Units
Trace width
Topology
The main-route via dimensions should comply with the via structure rules (See Via section)
For the connector pin vias, follow the rules for the connector pin vias (See Via section)
The traces after main-route via should be routed as 100Ω differential or as uncoupled 50ohm
Single-ended traces on PCB Top or Bottom.
1
mm
Max distance from RPD to main
trace (seg B)
Max distance from AC cap to RPD
~0
mm
stubbing point (seg A)
Max distance between ESD and
3
mm
signal via
Add-on Components
Example of a case where space is
Top
limited for placing components.
AC Cap
Value
Max via distance from BGA
Location
0.1
uF
7.62 (52.5)
mm (ps)
must be placed before pull-down resistor
Notes
S1 must be taken care in order to
consider Xtalk to adjacent pair
See topology figure above table
Bottom
The distance between the AC cap and the HDMI
connector is not restricted.
Placement
PTH design Place cap on bottom layer if main-route above core
Place cap on top layer if main-route below core
Micro-Via design Not Restricted
Void
GND (or PWR) void under/above the cap is needed.
Void size = SMT area + 1x dielectric height keepout
distance
Pull-down Resistor (R PD), choke/FET
Value
500
Ω
Location.
Must be placed after AC cap
Layer of placement
Same layer as AC cap. The FET & choke can be placed
on the opposite layer thru a PTH via
Choke betwee n RPD & FET
Choke 600 or
Ω@100MHz
1
uH@DC-100MHz
Max Trace Rdc ≤20
mΩ
Max Trace length 4
mm
Void
GND/PWR void under/above cap is preferred
Common-Mode Choke (Stuffing option – not added unless EMI issue is seen)
Common-mode
Min 65
Ω
impedance @ 100MHz
Max 90
RDC
<=0.3ohm
Differential TDR impedance
90ohm +/-15% @
Tr=200ps (10%-90%)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Can be choke or Trace. Recommended option for
HDMI2.0 HF1-9 improvement.
TDK ACM2012D-900-2P
48
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Parameter
Min Sdd21 @ 2.5GHz
Max Scc21 @ 2.5GHz
Location
Requirement
Units
2.22
dB
19.2
dB
Close to any adjacent discontinuity (< 8mm) – such as
connector, via, etc.
Notes
ESD (On-chip protection diode is able to withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing option)
Max junction capacitance
0.35
pF
e.g. ON-semiconductor ESD8040
(IO to GND)
Footprint
Pad right on the net instead of trace stub
Location
Void
After pull-down resistor/CMC and before RS
GND/PWR void under/above the cap is needed. Void
size = 1mm x 2mm for 1 pair
Series Resistor (R S) – Series resistor on P/N path for HDMI 2.0 (Mandatory)
Value
≤6
Location
Void
± 10%. 0ohm is acceptable if the design passes the
HDMI2.0 HF1-9 test. Otherwise, adjust the RS value to
ensure the HDMI2.0 tests pass: Eye diagram, Vlow test
and HF1-9 TDR test
After all components and before HDMI connector
GND/PWR void under/above the RS device is needed.
Void size = SMT area + 1x dielectric height keepout
distance.
Trace at Component Region
Value
Location
Trace entering the SMT pad
Trace between components
HDMI Connector
Connector Voiding
General
Routing over Voids
Noise Coupling
Note:
Ω
1.
2.
3.
4.
100
At component region (Microstrip)
One 45°
Ω
± 10%
Uncoupled structure
Voiding the ground below the signal lanes
0.1448(5.7mil) larger than the pin itself
Routing over voids not allowed except void around device ball/pin the signal is routed to.
Keep critical HDMI related traces including differential clock/data traces & RSET trace away from other signal
traces or unrelated power traces/areas or power supply components
Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the
max trace lengths will need to be reduced.
The average of the differential signals is used for length matching.
Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or
any discontinuity to minimize common mode conversion
If routing includes a flex or 2 nd PCB, the max trace delay & skew calculations must include all the PCBs/flex routing.
Solutions with flex/2 nd PCB may not achieve maximum frequency operation.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
49
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 44. HDMI Signal Connections
Module Pin Name
DPx_TX3+/–
DPx_HPD
Type
DIFF
OUT
DIFF
OUT
I
HDMI_CEC
I/OD
DPx_AUX_CH+/–
I/OD
HDMI 5V Supply
P
DPx_TX[2:0] +/–
Note:
Termination (see note on ESD)
0.1uF series ACCAP → 500Ω RPD (controlled by FET) →
EMI/ESD (if required),.≤6Ω RS (series resistor)
Description
HDMI Differential Clock: Connect to C–/C+ & pins on
HDMI Connector
HDMI Differential Data: Connect to D[2:0]+/– pins. See
DP/HDMI Pin Mapping table and connection diagram.
HDMI Hot Plug Detect: Connect to HPD pin on HDMI
Connector
Module to Connector: 10kΩ PU to 1.8V → level shifter
→ 100kΩ series resistor. 100kΩ to GND on connector
side.
Gating circuitry, See connection figure or reference
schematics for details.
HDMI Consumer Electronics Control: Connect to CEC
on HDMI Connector through circuitry. Tegra supports a
single CEC controller that can be associated with one of
the display output heads.
HDMI: DDC Interface – Clock and Data: Connect
DP1_AUX_CH+ to SCL & DP1_AUX_CH– to SDA on
HDMI Connector
HDMI 5V supply to connector: Connect to +5V on
HDMI Connector.
From the module to Connector: 10kΩ PU to 3.3V →
level shifter → 1.8kΩ PU to 5V → connector pin
Adequate decoupling (0.1uF & 10uF recommended) on
supply near connector.
Any ESD and/or EMI solutions must support targeted modes (frequencies).
Table 45. Recommended HDMI / DP observation (test) points for in itial boards
Test Points Recommended
One for each signal line.
Note:
Location
Near display connector. Connector pins can be used if accessible.
Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & nea r signal traces
Figure 28: Optional Dual-Mode (DP/HDMI) Connections
5.0V
10kΩ
10kΩ
DP_MODE*
10kΩ
10nF
DP_AUX_CHx_P
DP_AUX
100kΩ 0.1uF
To Jetson
TX2/TX2i
CONFIG1
10kΩ
To DP Connector
Gated
100kΩ
3.3V
DP_MODE*
100kΩ
DP_AUX_CHx_N
DP_AUX*
100kΩ 0.1uF
DP Interface Signal Routing Requirem ents
See eDP/DP Signal Routing Requirements.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
50
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
8.0 MIPI CSI (VIDEO INPUT)
Jetson TX2/TX2i supports three MIPI CSI x4 bricks, allow ing a variety of device types and combinations to be supported. Up to
three quad lane cameras or six dual lane cameras are possible (see CSI Configurations table for details). Each data lane has a
peak bandw idth of up to 2.5Gbps.
Note:
Maximum data rate may be limited by use case / memory bandwidth.
Table 46. CSI Pin Descriptions
Usage on the Carrier
Board
Pin # Module Pin Name
Tegra Signal
Usage/Description
G27
G28
F28
F29
H26
H27
D27
D28
C28
C29
E26
E27
G24
G25
F25
F26
H23
H24
D24
D25
C25
C26
E23
E24
G21
G22
F22
F23
H20
H21
D21
D22
C22
C23
E20
E21
CSI_A_CLK_N
CSI_A_CLK_P
CSI_A_D0_N
CSI_A_D0_P
CSI_A_D1_N
CSI_A_D1_P
CSI_B_CLK_N
CSI_B_CLK_P
CSI_B_D0_N
CSI_B_D0_P
CSI_B_D1_N
CSI_B_D1_P
CSI_C_CLK_N
CSI_C_CLK_P
CSI_C_D0_N
CSI_C_D0_P
CSI_C_D1_N
CSI_C_D1_P
CSI_D_CLK_N
CSI_D_CLK_P
CSI_D_D0_N
CSI_D_D0_P
CSI_D_D1_N
CSI_D_D1_P
CSI_E_CLK_N
CSI_E_CLK_P
CSI_E_D0_N
CSI_E_D0_P
CSI_E_D1_N
CSI_E_D1_P
CSI_F_CLK_N
CSI_F_CLK_P
CSI_F_D0_N
CSI_F_D0_P
CSI_F_D1_N
CSI_F_D1_P
Camera, CSI 0 Clock–
Camera, CSI 0 Clock+
Camera, CSI 0 Data 0–
Camera, CSI 0 Data 0+
Camera, CSI 0 Data 1–
Camera, CSI 0 Data 1+
Camera, CSI 1 Clock–
Camera, CSI 1 Clock+
Camera, CSI 1 Data 0–
Camera, CSI 1 Data 0+
Camera, CSI 1 Data 1–
Camera, CSI 1 Data 1+
Camera, CSI 2 Clock–
Camera, CSI 2 Clock+
Camera, CSI 2 Data 0–
Camera, CSI 2 Data 0+
Camera, CSI 2 Data 1–
Camera, CSI 2 Data 1+
Camera, CSI 3 Clock–
Camera, CSI 3 Clock+
Camera, CSI 3 Data 0–
Camera, CSI 3 Data 0+
Camera, CSI 3 Data 1–
Camera, CSI 3 Data 1+
Camera, CSI 4 Clock–
Camera CSI 4 Clock+
Camera, CSI 4 Data 0–
Camera, CSI 4 Data 0+
Camera, CSI 4 Data 1–
Camera, CSI 4 Data 1+
Camera, CSI 5 Clock–
Camera, CSI 5 Clock+
Camera, CSI 5 Data 0–
Camera, CSI 5 Data 0+
Camera, CSI 5 Data 1–
Camera, CSI 5 Data 1+
Camera Connector
Usage on the Carrier
Board
CSI0_CLK–
CSI0_CLK+
CSI0_D0–
CSI0_D0+
CSI0_D1–
CSI0_D1+
CSI1_CLK–
CSI1_CLK+
CSI1_D0–
CSI1_D0+
CSI1_D1–
CSI1_D1+
CSI2_CLK–
CSI2_CLK+
CSI2_D0–
CSI2_D0+
CSI2_D1–
CSI2_D1+
CSI3_CLK–
CSI3_CLK+
CSI3_D0–
CSI3_D0+
CSI3_D1–
CSI3_D1+
CSI4_CLK–
CSI4_CLK+
CSI4_D0–
CSI4_D0+
CSI4_D1–
CSI4_D1+
CSI5_CLK–
CSI5_CLK+
CSI5_D0–
CSI5_D0+
CSI5_D1–
CSI5_D1+
Direction
Pin Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
MIPI D-PHY
Table 47. Camera Miscellaneous Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
F9
F8
E7
G8
F7
H8
H7
G7
D7
E8
EXTPERIPH1_CLK
EXTPERIPH2_CLK
GPIO_CAM2
QSPI_SCK
GPIO_CAM3
QSPI_CS_N
QSPI_IO0
GPIO_SEN5
UART5_RTS_N
QSPI_IO1
Camera 0 Reference Clock
Camera 1 Reference Clock
Camera 2 Master Clock
Camera 0 Powerdown or GPIO
Camera 1 Powerdown or GPIO
Camera 0 Reset or GPIO
Camera 1 Reset or GPIO
Camera Strobe or GPIO
Camera Flash Enable or GPIO
Camera Vertical Sync
CAM0_MCLK
CAM1_MCLK
CAM2_MCLK
GPIO0_CAM0_PWR#
GPIO1_CAM1_PWR#
GPIO2_CAM0_RST#
GPIO3_CAM1_RST#
GPIO4_CAM_STROBE
GPIO5_CAM_FLASH_EN
CAM_VSYNC
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Camera Connector
Direction
Pin Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
51
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 48. CSI Configurations
Camera #
CSI Lanes
CSI_0_CLK
CSI_0_D[1:0]
CSI_1_CLK
CSI_1_D[1:0]
CSI_2_CLK
CSI_2_D[1:0]
CSI_3_CLK
CSI_3_D[1:0]
CSI_4_CLK
CSI_4_D[1:0]
CSI_5_CLK
CSI_5_D[1:0]
Note:
1.
2.
#1
2-Lane Configurations
#3
#4
#2
#5
#6
√
√
#1
4-Lane Configurations
#2
#3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Each 2-lane options shown abov e can also be used for one single lane camera as well
Combinations of 1, 2 & 4-lane cameras are supported, as long as any 4-lane cameras match one of the three configurations
abov e
Figure 29: Camera Control Connections
Jetson TX2/TX2i
Tegra
1kΩ
VDD_1V8
1kΩ
UART/CAM
I2C_CAM_CLK
CAM_I2C_SCL
CAM_I2C_SDA
EXTPERIPH1_CLK
EXTPERIPH2_CLK
GPIO_CAM2
GPIO_CAM3
UART5_RTS
I2C_CAM_DAT
120Ω
CAM0_MCLK
120Ω
GPIO0_CAM0_PWR#
120Ω
GPIO2_CAM0_RST#
CAM1_MCLK
GPIO1_CAM1_PWR#
GPIO3_CAM1_RST#
QSPI_SCK
QSPI_CS
QSPI_IO1
QSPI_IO0
SPI
CAM2_MCLK
CAM_VSYNC
GPIO4_CAM_STROBE
GPIO5_CAM_FLASH_EN
AO
Note:
Camera
I2C
C6
D6
F9
G8
H8
F8
F7
CAM_AF_EN
H7
Camera 0
Clock/Control
EMI
&
ESD
Camera 1
Clock/Control
E7
Camera 2 Clock
E8
Misc.
Camera
Strobe/Flash
G7
D7
GPIO_SEN5
1.
2.
If the module is providing flash control (as shown), GPIO5_CAM_FLASH_EN & GPIO4_CAM_STROBE must be used.
Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing & Vil/Vih requirements at
the receiver & maintain signal quality and meet requirements for the frequencies supported by the design .
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
52
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 30: Camera CSI Connections
Jetson TX2/TX2i
Tegra
DSI/CSI
Note:
CSI_A_CLK_P
CSI_A_CLK_N
CSI_A_D0_P
CSI_A_D0_N
CSI_A_D1_P
CSI_A_D1_N
CSI0_CK+
CSI_B_CLK_P
CSI_B_CLK_N
CSI_B_D0_P
CSI_B_D0_N
CSI_B_D1_P
CSI_B_D1_N
CSI1_CK+
CSI_C_CLK_P
CSI_C_CLK_N
CSI_C_D0_P
CSI_C_D0_N
CSI_C_D1_P
CSI_C_D1_N
CSI2_CK+
CSI_D_CLK_P
CSI_D_CLK_N
CSI_D_D0_P
CSI_D_D0_N
CSI_D_D1_P
CSI_D_D1_N
CSI3_CK+
CSI_E_CLK_P
CSI_E_CLK_N
CSI_E_D0_P
CSI_E_D0_N
CSI_E_D1_P
CSI_E_D1_N
CSI4_CK+
CSI_F_CLK_P
CSI_F_CLK_N
CSI_F_D0_P
CSI_F_D0_N
CSI_F_D1_P
CSI_F_D1_N
CSI5_CK+
CSI0_CK–
CSI0_D0+
CSI0_D0–
CSI0_D1+
CSI0_D1–
CSI1_CK–
CSI1_D0+
CSI1_D0–
CSI1_D1+
CSI1_D1–
CSI2_CK–
CSI2_D0+
CSI2_D0–
CSI2_D1+
CSI2_D1–
CSI3_CK–
CSI3_D0+
CSI3_D0–
CSI3_D1+
CSI3_D1–
CSI4_CK–
CSI4_D0+
CSI4_D0–
CSI4_D1+
CSI4_D1–
CSI5_CK–
CSI5_D0+
CSI5_D0–
CSI5_D1+
CSI5_D1–
G28
G27
F29
F28
H27
H26
2-Lane
4-Lane
(B_CLK not
used)
D28
D27
C29
C28
E27
E26
2-Lane
G25
G24
F26
F25
EMI
H24
H23
&
D25
D24
C26
C25
E24
E23
2-Lane
4-Lane
(D_CLK not
used)
ESD
2-Lane
G22
G21
F23
F22
H21
H20
2-Lane
4-Lane
(F_CLK not
used)
D22
D21
C23
C22
E21
E20
2-Lane
Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing & Vil/Vih requirements at the
receiver & maintain signal quality and meet requirements for the frequencies supported by the design .
CSI Design Guidelines
CSI & DSI use the MIPI D-PHY for the physical interface. The routing & connection requirements are found in the DSI section.
Table 49. MIPI CSI Signal Connections
Module Pin Name
CSI[5:0]_CLK+/–
Type
I
CSI[5:0]_D[1:0]+/–
I/O
Note:
Termination
See note
See note
Description
CSI Differential Clocks: Connect to clock pins of camera. See the CSI Configurations tables for
details
CSI Differential Data Lanes: Connect to data pins of camera. See the CSI Configurations tables for
details
Depending on the mechanical design of the platform and camera modules, ESD protection may be necessary. In addition,
EMI control may be needed. Both are shown in the Camera Connection Example diagram. Any EMI/ESD solution must be
compatible with the frequency required by the design.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
53
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 50. Miscellaneous Camera Connections
Module Pin Name
I2C_CAM_CLK
I2C_CAM_DAT
CAM[2:0]_MCLK
GPIO1_CAM1_PWR#
GPIO0_CAM0_PWR#
GPIO4_CAM_STROBE
Type
O
I/O
O
Termination
1kΩ Pull-ups VDD_1V8 (on the module).
See note related to EMI/ESD under MIPI
CSI Signal Connections tables.
120Ω Bead in series (on the module) See
note related to EMI/ESD under MIPI CSI
Signal Connections tables.
I/O
GPIO5_CAM_FLASH_EN
GPIO3_CAM1_RST#
GPIO2_CAM0_RST#
O
O
CAM_VSYNC
O
See note related to ESD under MIPI CSI
Signal Connections tables.
Description
Camera I2C Interface: Connect to I2C SCL & SDA pins of imager
Camera Master Clocks: Connect to Camera reference clock
inputs.
Camera Power Control signals (or GPIOs [1:0]): Connect to
powerdown pins on camera(s).
Camera Strobe Enable (or GPIO 4): Connect to camera strobe
circuit unless strobe control comes from camera module.
Camera Flash Enable: Connect to enable of flash circuit
Camera Resets (or GPIO [3:2]): Connect to reset pin on any
cameras with this function. If AutoFocus Enable is required,
connect GPIO3_CAM1_RST# to AF_EN pin on camera module &
use GPIO2_CAM0_RST# as common reset line.
Camera Vertical Sync
Table 51. Recommended CSI observation (test) points for initial boards
Test Points Recommended
One per signal line.
Note:
Location
Near the module pins
Test points must be done carefully to minimize signal integrity impact. Avoid stubs & keep pads small & near signal traces
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
54
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
9.0 SDIO/SDCARD/EMMC
Jetson TX2/TX2i has four SD/MMC interfaces. The mapping of these interfaces for each module is show n in the SDIO / SD
Card / eMMC Interface Mapping table.
Table 52. SDMMC Pin Descriptions
Usage on the Carrier
Board
Pin # Module Pin Name
Tegra Signal
Usage/Description
G18
G19
H18
H17
F19
F18
F17
H16
F20
B30
B29
B32
A32
A31
A30
A29
SDMMC1_CLK
SDMMC1_CMD
SDMMC1_DAT0
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3
GPIO_EDP2
GPIO_EDP3
GPIO_EDP1
SDMMC3_CLK
SDMMC3_CMD
SDMMC3_DAT0
SDMMC3_DAT1
SDMMC3_DAT2
SDMMC3_DAT3
NFC_EN
SD Card (or SDIO) Clock
SD Card (or SDIO) Command
SD Card (or SDIO) Data 0
SD Card (or SDIO) Data 1
SD Card (or SDIO) Data 2
SD Card (or SDIO) Data 3
SD Card Card Detect
SD Card power switch Enable
SD Card Write Protect
SDIO Clock
SDIO Command
SDIO Data 0
SDIO Data 1
SDIO Data 2
SDIO Data 3
SDIO Reset
Note:
SDCARD_CLK
SDCARD_CMD
SDCARD_D0
SDCARD_D1
SDCARD_D2
SDCARD_D3
SDCARD_CD#
SDCARD_PWR_EN
SDCARD_WP
SDIO_CLK
SDIO_CMD
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_RST#
SD Card
SDIO
Direction
Pin Type
Output
Bidir
Bidir
Bidir
Bidir
Bidir
Input
Output
Input
Output
Bidir
Bidir
Bidir
Bidir
Bidir
Output
CMOS – 3.3/1.8V
CMOS – 3.3/1.8V
CMOS – 3.3V/1.8V
CMOS – 3.3V/1.8V
CMOS – 3.3/1.8V
CMOS – 3.3/1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
The SDIO Signals highlighted in Cyan are available only on the Jetson TX2i module pins (not on Jetson TX2).
Table 53. SDIO / SD Card / eMMC Interface Mapping
Module Pins
SDCARD
Tegra Interface
SDMMC1
Width
4-bit
N/A
SDIO (TX2i only)
SDMMC2
SDMMC3
4-bit
4-bit
N/A
SDMMC4
8-bit
Usage
SD (Primary SD Card). Can be used instead for SDIO
interface.
Pins used for EQOS for Ethernet on the module
Jetson TX2: Used for WLAN/BT
Jetson TX2i: Available for SDIO at module pins
Used on the module - eMMC
9.1 SD Card
The Figure show s a standard SD socket. Internal pull-up resistors are used for SDCARD Data/CMD lines, so external pull-ups
are not required.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
55
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 31. SD Card Socket Connection Example
VDD_3V3_SYS
Load Switch
VIN
VOUT
4.7kΩ
ON
D
Jetson TX2/TX2i
G
S
Tegra
SDMMC1
SDCARD_CLK
120Ω@100MHz
SDCARD_CMD
SDMMC1_CLK
SDMMC1_CMD
SDCARD_D0
SDMMC1_DAT0
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3
EDP
SDCARD_D1
SDCARD_D2
SDCARD_D3
SDCARD_PWR_EN
GPIO_EDP3
SDCARD_CD#
GPIO_EDP2
G18
10Ω
DATA2
10Ω
DATA3
10Ω
CMD
GND
G19
VDD
H18
H17
F19
F18
H16
F17
CLK
0Ω
GND
SDMMC_VDD_EN
10Ω
DATA0
10Ω
DATA1
SDMMC1_ CD*
C_DETECT
COMMON
C_WR_PROTECT
ESD
SDCARD_WP
GPIO_EDP1
Notes:
1.
2.
F20
SDMMC1_ WP
If EMI and/or ESD devices are necessary, they must be tuned to minimize the impact to signal quality, which must meet
the timing & Vil/Vih requirements at the receiver & maintain signal quality and meet requirements for the frequencies
supported by the design.
Supply (load switch, etc) used to provide power to the SD Card must be current limited if the supply is shorted to GND.
Table 54. SDCARD / SDIO Interface Signal Routing Requirements
Parameter
Max Frequency
3.3V Signaling
DS
HS
SDR12
SDR25
SDR50
SDR104
DDR50
1.8V Signaling
Topology
Reference plane
Trace Impedance
Max Via Count
Via proximity (Signal to reference)
Trace spacing
Trace length
SDR50 / SDR25 / SDR12 / HS / DS
PTH
HDI
Microstrip / Stripline
Min
Max
Min
Max
SDR104 / DDR50
Requirement
25 (12.5)
50 (25)
25 (12.5)
50 (25)
100 (50)
208 (104)
50 (50)
Point to point
GND or PWR
50
4
10
< 3.8 (24)
4x / 3x
Units
MHz (MB/s)
Ω
mm (ps)
dielectric
16 (100)
139 (876)
16 (100)
83 (521)
Notes
See Note 1
See Note 2
±15%. 45Ω optional depending on stack-up
Independand of stackup layers
Depends on stackup layers
Up to 4 signal Vias can share 1 GND return Via
mm (ps)
Max Trace Delay Skew in/between CLK & CMD/DAT
See Note 3
Mm (ps)
SDR50 / SDR25 / SDR12 / HS / DS 14 (87.5)
SDR104 / DDR50 2 (12.5)
Keep CLK, CMD & DATA traces away from other signal traces or unrelated power traces/areas or power supply components
Note:
1.
2.
3.
Actual frequencies may be lower due to clock source/divider limitations.
If PWR, 0.01uF decoupling cap required for return current.
If routing to SD Card socket includes a flex or 2nd PCB, max trace & skew calculations must include PCB & flex routing.
Table 55. SD Card Loading vs Drive Type
General SD Card Compliance
CCARD (CDIE+CPKG)
Parameter
Min
Max
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Value
5
10
Units
pF
pF
Notes
Spec best case value
Spec worst case value
56
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Drive Type
A
B
C
D
SDR104
DDR50
SDR50
SDR25
SDR12
HS
DS
Drive Type = A
Drive Type = B
Drive Type = C
Drive Type = D
Drive Type = A
Drive Type = B
Drive Type = C
Drive Type = D
F MAX (CLK base frequency)
CLOAD (CCARD+CEQ)
(CLK freq = 208MHz)
CLOAD (CCARD+CEQ)
(CLK freq = 100/50/25MHz)
33
50
66
100
208
50
100
50
25
50
25
21
15
11
22
43
30
23
22
Ω
Ω
Ω
Ω
MHz
MHz
MHz
MHz
MHz
MHz
MHz
pF
pF
pF
pF
pF
pF
pF
pF
UHS50 Card = optional, UHS104 Card = mandatory
UHS50 Card = mandatory, UHS104 Card = mandatory
UHS50 Card = optional, UHS104 Card = mandatory
UHS50 Card = optional, UHS104 Card = mandatory
Single data rate up to 104MB/sec
Double data rate up to 50MB/sec
Single data rate up to 50MB/sec
Single data rate up to 25MB/sec
Single data rate up to 12.5MB/sec
Single data rate up to 25MB/sec
Single data rate up to 12.5MB/sec
Total load capacitance supported
Total load capacitance supported
Total load capacitance supported
Possibly 22pF+ depending on host system
Total load capacitance supported
Total load capacitance supported
Total load capacitance supported
Possibly 22pF+ depending on host system
Table 56. SDCARD Signal Connections
Function Signal Name
SDCARD_CLK
SDCARD_CMD
SDCARD_D[3:0]
Type
O
I/O
I/O
SDCARD_CD#
SDCARD_WP
I
I
SDIO_RST#
SDCARD_PWR_EN
O
O
Note:
Termination
120 Ω bead on module
for SDCARD_CLK. 0Ω
series resistor on carrier
board as placeholder.
See note for EMI/ESD
10Ω series resistors for
SDCARD CMD/D[3:0].
See note for EMI/ESD
Description
SDIO/SD Card Clock: Connect to CLK pin of device or socket
SDIO/SD Card Command: Connect to CMD pin of device/socket
SDIO/SD Card Data: Connect to Data pins of device or socket
SD Card Card Detect: Connect to CD/C_DETECT pin on socket if required.
SD Card Write Protect: Connect to WP/WR_PROTECT pin on socket if
required.
SDIO Reset: Connect to reset line on SDIO peripheral/connector.
SD Card Supply/Load Switch Enable: Connect to enable of supply/load switch
supplying VDD on SD Card socket.
EMI/ESD may be required for SDIO when used as the SD Card socket interface. Any EMI/ESD device used must be able to meet signal
timing/quality requirements. The Carrier Board implements 10Ω series resistors on the SDCARD data lines and a 0Ω series resistor on the
clock line (for possible tuning if required).
Table 57. SDIO Signal Connections (Jetson TX2i only)
Function Signal Name
SDIO_CLK
SDIO_CMD
SDIO_D[3:0]
SDIO_RST#
Type
O
I/O
I/O
O
Termination
120 Ω bead on module
for SDCARD_CLK. See
note for EMI/ESD
See note for EMI/ESD
Description
SDIO/SD Card Clock: Connect to CLK pin of device or socket
SDIO/SDMMC Command: Connect to CMD pin of device/socket
SDIO/SDMMC Data: Connect to Data pins of device or socket
SDIO Reset: Connect to reset line on SDIO peripheral/connector.
Table 58. Recommended SDCARD/SDIO observation (test) points for initial boards
Test Points Recommended
One for SDCARD/SDIO_CLK line.
One SDCARD/SDIO_DATx line & one for
SDCARD/SDIO_CMD.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Location
Near Device/Connector pin. SD connector pin can be used for device end if accessible.
Near the module & Device pins. SD connector pin can be used for device end if accessible.
57
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
10.0 AUDIO
Jetson TX2/TX2i brings four PCM/I2S audio interfaces to the module pins & includes a flexible audio-port sw itching architecture.
In addition, digital microphone & speaker interfaces are provided.
Table 59. Audio Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
F1
G2
H1
G1
H2
C15
D13
C14
D14
G5
H5
G6
H6
E6
F5
E5
F6
E16
D16
G4
H4
F2
H3
AUD_MCLK
DAP1_SCLK
DAP1_FS
DAP1_DIN
DAP1_DOUT
DAP2_SCLK
DAP2_FS
DAP2_DIN
DAP2_DOUT
DMIC2_DAT
DMIC1_CLK
DMIC1_DAT
DMIC2_CLK
DAP4_SCLK
DAP4_FS
DAP4_DIN
DAP4_DOUT
CAN_GPIO1
CAN_GPIO0
GPIO_AUD3
GPIO_AUD2
GPIO_AUD1
GPIO_AUD0
Audio Codec Master Clock
I2S Audio Port 0 Clock
I2S Audio Port 0 Left/Right Clock
I2S Audio Port 0 Data In
I2S Audio Port 0 Data Out
I2S Audio Port 1 Clock
I2S Audio Port 1 Left/Right Clock
I2S Audio Port 1 Data In
I2S Audio Port 1 Data Out
I2S Audio Port 2 Clock
I2S Audio Port 2 Left/Right Clock
I2S Audio Port 2 Data In
I2S Audio Port 2 Data Out
I2S Audio Port 3 Clock
I2S Audio Port 3 Left/Right Clock
I2S Audio Port 3 Data In
I2S Audio Port 3 Data Out
Digital Mic Input Clock
Digital Mic Input Data
Digital Speaker Output Clock
Digital Speaker Output Data
Audio Codec Reset or GPIO
Audio Codec Interrupt or GPIO
AUDIO_MCLK
I2S0_CLK
I2S0_LRCLK
I2S0_SDIN
I2S0_SDOUT
I2S1_CLK
I2S1_LRCLK
I2S1_SDIN
I2S1_SDOUT
I2S2_CLK
I2S2_LRCLK
I2S2_SDIN
I2S2_SDOUT
I2S3_CLK
I2S3_LRCLK
I2S3_SDIN
I2S3_SDOUT
AO_DMIC_IN_CLK
AO_DMIC_IN_DAT
DSPK_OUT_CLK
DSPK_OUT_DAT
GPIO19_AUD_RST
GPIO20_AUD_INT
Usage on the Carrier
Board
Expansion Header
GPIO Expansion
Header
M.2 Key E
Camera Connector
Expansion Header
GPIO Expansion
Header
Expansion Header
Direction
Pin Type
Output
Bidir
Bidir
Input
Bidir
Bidir
Bidir
Input
Bidir
Bidir
Bidir
Input
Bidir
Bidir
Bidir
Input
Bidir
Output
Input
Output
Output
Output
Input
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
When possible, the follow ing assignments should be used for the I2Sx interfaces.
Table 60. I2S Interface Mapping
Module Pins (Tegra Functions)
I2S0 (I2S1)
I2S1 (I2S2)
I2S2 (I2S3)
I2S3 (I2S4)
NA (I2S6)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
I/O Block
AUDIO
CONN
AUDIO_HV
AUDIO_HV
DMIC_HV
Typical Usage
Available (Codec)
Available (Misc)
Available (WLAN / BT, Modem)
Available (Misc)
Jetson TX2: Used for on-module WLAN / BT
Jetson TX2i: Unused – not brought to module pins.
58
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 32. I2S & Codec Clock/Control Connections
Jetson TX2/TX2i
Tegra
AUDIO
AUD_MCLK
GPIO_AUD1
DAP1_SCLK
DAP1_FS
DAP1_DOUT
DAP1_DIN
AUDIO_HV
GPIO_AUD0
DMIC2_DAT
DMIC1_CLK
DMIC2_CLK
DMIC1_DAT
DMIC_HV
CONN
Note:
-
Nvidia
Carrier Board
Net Name
Tegra
Function
75Ω
AUDIO_MCLK
F1
F2
G2
H1
H2
G1
GPIO19_AUD_RST
I2S1_CLK
75Ω
I2S0_CLK
I2S1_LRCK
I2S0_LRCK
I2S1_SDOUT
I2S0_SDOUT
I2S1_SDIN
I2S0_SDIN
GPIO20_AUD_INT
I2S3_CLK
75Ω
I2S3_LRCK
GPIO_PQ0
GPIO_PQ3
GPIO_PQ1
GPIO_PQ2
I2S6_CLK
DAP2_SCLK
DAP2_FS
DAP2_DOUT
DAP2_DIN
I2S2_CLK
H5
I2S2_SDOUT
I2S3_SDIN
DAP4_SCLK
DAP4_FS
DAP4_DOUT
DAP4_DIN
G5
I2S2_LRCK
I2S3_SDOUT
I2S4_CLK
H3
I2S2_CLK
H6
I2S2_SDIN
120Ω@
G6
I2S3_CLK
I2S4_LRCK
E6
I2S3_LRCK
I2S4_SDOUT
F5
I2S3_SDOUT
I2S4_SDIN
F6
I2S3_SDIN
E5
AUDIO_I2S_MCLK
GPIO_X1_AUD
Audio
Codec
DAP1_SCLK_AP
DAP1_F S_AP
DAP1_DOUT_AP
DAP1_DIN_AP
AUD_INT
DAP3_SCLK_AP
DAP3_FS_AP
DAP3_DOUT_AP
2nd WiFi/BT,
Modem
DAP3_DIN_AP
DAP4_SCLK_AP
DAP4_FS_AP
Misc
DAP4_DOUT_AP
DAP4_DIN_AP
120Ω@
Primary
WiFi/BT
(TX2 only)
I2S6_LRCK
I2S6_SDOUT
I2S6_SDIN
I2S1_CLK
I2S2_LRCK
I2S2_SDOUT
I2S1_LRCK
I2S1_SDOUT
I2S2_SDIN
I2S1_SDIN
C15
D13
D14
C14
DAP2_SCLK_AP
DAP2_FS_AP
Misc
DAP2_DOUT_AP
DAP2_DIN_AP
The I2S interfaces can be used in either Master or Slave mode.
A capacitor from DAPn_FS to GND is recommended if Tegra an I2S slave & the edge_cntrl configuration = 1 (SDATA
driven on positive edge of SCLK). The value of the capacitor should be chosen to provide a minimum of 2ns hold time for
the DAPn_FS edge after the rising edge of DAPn_SCLK.
I2S Design Guidelines
Table 61. I2S Interface Signal Routing Requirements
Parameter
Configuration / Device Organization
Max Loading
Reference plane
Breakout Region Impedance
Trace Impedance
Via proximity (Signal to reference)
Trace spacing
Microstrip or Stripline
Max Trace Delay
Max Trace Delay Skew between SCLK & SDATA_OUT/IN
Note:
Requirement
1
8
GND
Min width/spacing
50
< 3.8 (24)
2x
3600 (~22)
250 (~1.6”)
Units
load
pF
Ω
mm (ps)
dielectric
Notes
±20%
See Note 1
ps (in)
ps (in)
Up to 4 signal Vias can share a single GND return Via
Table 62. I2S & Codec Clock/Control Signal Connections
Module Pin Name
I2S[3:0]_SCLK
I2S[3:0]_LRCK
I2S[3:0]_SDATA_OUT
I2S[3:0]_SDATA_IN
AUD_MCLK
GPIO19_AUD_RST
GPIO20_AUD_INT
Type
I/O
Termination
I2S[2,0]_CLK have 75Ω beads & I2S3_CLK
has a 120Ω Bead in series (on the module).
I/O
I/O
I
O
O
I
75Ω Beads in series (on the module).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Description
I2S Serial Clock: Connect to I2S/PCM CLK pin of audio device.
I2S Left/Right Clock: Connect to Left/Right Clock pin of audio device.
I2S Data Output: Connect to Data Input pin of audio device.
I2S Data Input: Connect to Data Output pin of audio device.
Audio Codec Master Clock: Connect to clock pin of Audio Codec.
Audio Reset: Connect to reset pin of Audio Codec.
Audio Interrupt: Connect to interrupt pin of Audio Codec.
59
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
DMIC Design Guidelines
Table 63. DMIC Interface Signal Routing Requirements
Parameter
Clock Frequency/Period
Data Bit-rate/Period (DDR24)
Configuration / Device Organization
Topology
Reference plane
Trace Impedance
Via proximity (Signal via to GND return via)
Trace spacing
Microstrip / Stripline
Max Trace Delay
Max Trace Delay Skew between CLK & DAT
Notes:
Requirement
12/83.33
24/41.66
1
Point to Point
GND
45-50
< 3.8 (24)
2x / 2x
1280
150
Units
MHz/ns
Mbps/ns
load
Notes
Ω
mm (ps)
dielectric
±20%
See Note
ps
ps
Up to 4 signal Vias can share a single GND return Via
Table 64. DMIC Signal Connections
Function Name
AO_DMIC_IN_CLK
AO_DMIC_IN_DAT
Type
O
I
Termination
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Description
Digital Microphone Clock: Connect to clock pin of DMIC device
Digital Microphone Data: Connect to data pin of DMIC device
60
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
11.0 WLAN / BT (INTEGRATED) – JETSON TX2 ONLY
Jetson TX2 integrates a Broadcom BCM4354 WLAN / BT solution. Tw o Dual-band antenna connectors are located on the
module. The requirements are in the Antenna Requirements table below . The UART interface is multiplexed and either route
these to the WLAN/BT device or to the connector pins for use on the carrier board. The default selection for the multiplexers is
to the WLAN/BT device.
Figure 33. Integrated WLAN / BT (Jetson TX2 only)
Jetson TX2
Tegra
SDMMC3
SDMMC3_CLK
SDMMC3_CMD
SDMMC3_DAT0
SDMMC3_DAT1
SDMMC3_DAT2
SDMMC3_DAT3
SPI
CAM
SYS
UART
QSPI_IO3
GPIO_CAM1
WIFI_WAKE_AP
GPIO_SW4
BT2_WAKE_AP
GPIO_MDM5
Load
Switch
WIFI_EN
GPIO_SW3
MCPU_PWR_REQ
VDD_3V3_SYS
MUX_SEL
RF
VDD_1V8
Antenna
Connector #1
RF
Antenna
Connector #2
WiFi / BT
BT_EN
AP2_WAKE_BT
UART 3_TX
UART 3_RX
CONN
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
GPIO_PQ0
GPIO_PQ1
GPIO_PQ2
GPIO_PQ3
DMIC_HV
SEL
UART 3_RTS#
UART 3_CTS#
Mux
H10
H9
G10
G9
(Default)
DAP6_SCLK
DAP6_DOUT
DAP6_DIN
DAP6_FS
Figure 34. Jetson TX2i connections related to the pins & interfaces used on Jetson TX2 for WLAN / BT
Jetson TX2i
Tegra
SDMMC3
SPI
CAM
SYS
UART
CONN
DMIC_HV
SDIO_CLK
SDMMC3_CLK
SDMMC3_CMD
SDMMC3_DAT0
SDMMC3_DAT1
SDMMC3_DAT2
SDMMC3_DAT3
SDIO_CMD
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
B3 0
B2 9
B3 2
A32
A31
A30
QSPI_IO3
GPIO_CAM1
TEGRA_GPIO_SHUTDOWN
GPIO_SW3
RDC_IN
GPIO_SW4
BT2_WAKE_AP
4.7kΩ
To ON/OFF & Wake Circuitry
Tegra Package Daisy Chain Test
1.8V
MCPU_PWR_REQ
GPIO_MDM5
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
UART 3_TX
UART 3_RX
UART3_RTS#
UART3_CTS#
H10
H9
G10
G9
GPIO_PQ0
GPIO_PQ1
GPIO_PQ2
GPIO_PQ3
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
61
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 65. Antenna Requirements
Parameter
Type
Frequency Band(s)
Impedance
Mating Connector
Note:
1.
2.
3.
Requirement
Dual-Band (x2) Dipole
2.4 & 5.0
50
Matching I-PEX MHF or Hirose U.FL
Female
Units
Notes
GHz
Ω
See note 1
Receptacles on Jetson TX2 are from Hirose Electric (U.S.A). Part # is U.FL-R-SMT-1(10).
Antenna Manufacturer: Pulse, Part Number: W1043
Cable manufacturer: Pulse, part number: W9009
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
62
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
12.0 MISCELLANEOUS INTERFACES
12.1 I2C
Tegra has nine I2C controllers. Jetson TX2/TX2i brings eight of the I2C interfaces out, w hich are show n in the tables below .
The assignments in Table 67 should be used for the I2C interfaces:
Table 66. I2C Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
C6
D6
E15
D15
A21
A20
C11
C10
C12
C13
A6
B6
A34
A35
B34
B35
CAM_I2C_SCL
CAM_I2C_SDA
GPIO_SEN8
GPIO_SEN9
GEN1_I2C_SCL
GEN1_I2C_SDA
GEN7_I2C_SCL
GEN7_I2C_SDA
GEN9_I2C_SCL
GEN9_I2C_SDA
GEN8_I2C_SCL
GEN8_I2C_SDA
DP_AUX_CH1_N
DP_AUX_CH1_P
DP_AUX_CH0_N
DP_AUX_CH0_P
Camera I2C Clock
Camera I2C Data
General I2C 0 Clock
General I2C 0 Data
General I2C 1 Clock
General I2C 1 Data
General I2C 2 Clock
General I2C 2 Data
General I2C 3 Clock
General I2C 3 Data
PM I2C Clock
PM I2C Data
Display Port 1 Aux– or HDMI DDC SDA
Display Port 1 Aux+ or HDMI DDC SCL
Display Port 0 Aux– or HDMI DDC SDA
Display Port 0 Aux+ or HDMI DDC SCL
I2C_CAM_CLK
I2C_CAM_DAT
I2C_GP0_CLK
I2C_GP0_DAT
I2C_GP1_CLK
I2C_GP1_DAT
I2C_GP2_CLK
I2C_GP2_DAT
I2C_GP3_CLK
I2C_GP3_DAT
I2C_PM_CLK
I2C_PM_DAT
DP1_AUX_CH–
DP1_AUX_CH+
DP0_AUX_CH–
DP0_AUX_CH+
Usage on the Carrier
Board
Camera Connector
I2C (General)
HDMI Type A Conn.
Display Connector
Direction
Pin Type
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 3.3V
Open Drain – 3.3V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
AC-Coupled on Carrier
Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C)
Table 67. I2C Interface Mapping
Ctrlr
Module Pins Names
I2C1
I2C2
I2C3
I2C4
I2C_GP1_CLK/DAT
I2C_GP0_CLK/DAT
I2C_CAM_CLK/DAT
DP1_AUX_CH_P/N
I2C5
I2C6
na
DP0_AUX_CH_P/N
I2C7
I2C8
I2C9
I2C_GP2_CLK/DAT
I2C_PM_CLK/DAT
I2C_GP3_CLK/DAT
Usage on Jetson
TX2/TX2i
Power monitors
Typcial usage on Carrier board
On-module Pull-up/voltage
General I2C bus usage. 3.3V devices supported
Audio Codec, general I2C. 1.8V devices supported
Cameras & related functions. 1.8V devices supported
HDMI / DP / I2C. 1.8V / 3.3V devices supported.
Power control
On-module use only
HDMI / DP / I2C. 1.8V / 3.3V devices supported.
1KΩ on the module to 3.3V
1KΩ on the module to 1.8V
1KΩ on the module to 1.8V
None on the module. I/F supports
pull-up to 1.8V or 3.3V (3.3V in
Open-drain mode only)
1KΩ on the module to 1.8V
None on the module. I/F supports
pull-up to 1.8V or 3.3V (3.3V in
Open-drain mode only)
1KΩ on the module to 1.8V
1KΩ on the module to 1.8V
1KΩ on the module to 1.8V
Thermal Sensor
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
General I2C bus. 1.8V devices supported
General I2C bus. Only 1.8V devices supported
General I2C bus. Only 1.8V devices supported
63
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 35. I2C Connections
Jetson TX2/TX2i
1kΩ
Tegra – I2C
SYS
I2C5
VDD_1V8
1kΩ
PWR_I2C_SCL
PWR_I2C_SDA
On-Module
Usage Only
1kΩ
VDD_3V3_SYS
1kΩ
I2C1
I2C_GP1_CLK
GEN1_I2C_SCL
GEN1_I2C_SDA
I2C_GP1_DAT
1kΩ
A21
A20
Used on-module for power monitors, & typically offmodule for GPIO expansion or other misc 3.3V I2C usage
VDD_1V8
1kΩ
CAM
I2C3
I2C_CAM_CLK
CAM_I2C_SCL
CAM_I2C_SDA
I2C_CAM_DAT
1kΩ
UART
C6
D6
Used as camera module
control interface
VDD_1V8
1kΩ
I2C7
I2C_GP2_CLK
GEN7_I2C_SCL
GEN7_I2C_SDA
I2C_GP2_DAT
1kΩ
C11
C10
Available for misc.
1.8V I2C devices
C12
C13
Available for misc.
1.8V I2C devices
E15
D15
Available for misc.
1.8V I2C devices
A6
Available for misc.
1.8V I2C devices
VDD_1V8
1kΩ
I2C9
I2C_GP3_CLK
GEN9_I2C_SCL
GEN9_I2C_SDA
I2C_GP3_DAT
1kΩ
VDD_1V8
1kΩ
AO
I2C2
I2C_GP0_CLK
GPIO_SEN8
GPIO_SEN9
I2C_GP0_DAT
1kΩ
VDD_1V8
1kΩ
DP
GEN8_I2C_SCL
GEN8_I2C_SDA
I2C_PM_CLK
I2C8
DP_AUX_CH0_P
DP_AUX_CH0_N
DP0_AUX_CH+
I2C6
DP_AUX_CH1_P
DP_AUX_CH1_N
DP1_AUX_CH+
I2C4
I2C_PM_DAT
DP0_AUX_CH–
DP1_AUX_CH–
B6
B3 5
B3 4
A35
A34
Typically used for eDP. Otherwise
available for Misc 1.8V/3.3V I2C usage.
Typically used for HDMI or DP. Otherwise
available for Misc 1.8V/3.3V I2C usage.
I2C Design Guideline s
Care must be taken to ensure I2C peripherals on same I2C bus connected to the module do not have duplicate addresses.
Addresses can be in tw o forms: 7-bit, w ith the Read/Write bit removed or 8-bit including the Read/Write bit. Be sure to compare
I2C device addresses using the same form (all 7-bit or all 8-bit format).
Table 68. I2C Interface Signal Routing Requirements
Parameter
Max Frequency
Topology
Max Loading
Reference plane
Trace Impedance
Trace Spacing
Max Trace Delay
Note:
1.
2.
3.
Standard-mode / Fm / Fm+
Standard-mode / Fm / Fm+
Standard Mode
Fm & Fm+
Requirement
Units
Notes
100 / 400 / 1000
kHz
See Note 1
Single ended, bi-directional, multiple masters/slaves
400
pF
Total of all loads
GND or PWR
50 – 60
Ω
±15%
1x
dielectric
3400 (~20)
ps (in)
1700 (~10)
Fm = Fast-mode, Fm+ = Fast-mode Plus
Avoid routing I2C signals near noisy traces, supplies or components such as a switching power regulator.
No requirement for decoupling caps for PWR reference
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
64
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 69. I2C Signal Connections
Module Pin Name
I2C_GP0_CLK/DAT
I2C_GP1_CLK/DAT
Type
I/OD
I/OD
I2C_GP2_CLK/DAT
I2C_GP3_CLK/DAT
I2C_PM_CLK/DAT
I/OD
I/OD
I/OD
I2C_CAM_CLK/DAT
DP0_AUX_CH+/–
I/OD
I/OD
DP1_AUX_CH+/–
I/OD
Note:
1.
2.
Termination
1kΩ pull-ups
1kΩ pull-ups
module
1kΩ pull-ups
1kΩ pull-ups
1kΩ pull-ups
to VDD_1V8 on the module
to VDD_3V3_SYS on the
to VDD_1V8 on the module
to VDD_1V8 on the module
to VDD_1V8 on the module
1kΩ pull-ups to VDD_1V8 on the module
See eDP/HDMI/DP sections for correct
termination
See eDP/HDMI/DP sections for correct
termination
Description
General I2C 0 Clock\Data. Connect to CLK/Data pins of 1.8V devices
General I2C 1 Clock\Data. Connect to CLK/Data pins of 3.3V devices.
General I2C 2 Clock\Data. Connect to CLK/Data pins of 1.8V devices
General I2C 3 Clock\Data. Connect to CLK/Data pins of 1.8V devices.
Power Mon. I2C Clock\Data. Connect to CLK/Data pins of 1.8V
devices
Camera I2C Clock\Data. Connect to CLK/Data pins of any 1.8V devices
DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI).
Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI)
DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI).
Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI)
If some devices require a different voltage level than others connected to the same I2C bus, level shifters are required.
For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are
pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers.
De-bounce
The tables below contain the allow able De-bounce settings for the various I2C Modes.
Table 70. De-bounce Settings (Fast Mode Plus, Fast Mode & Standard Mode)
I2C Mode
Clock Source
Source Clock Freq
I2C Source Divisor
Sm/Fm Divisor
Fm+
PLLP_OUT0
408MHz
5 (0x04)
10 (0x9)
Fm
PLLP_OUT0
408MHz
5 (0x4)
Sm
PLLP_OUT0
408MHz
20 (0x13)
Note:
De-bounce Value
0
5:1
7:6
I2C SCL Freq
1016KHz
905.8KHz
816KHz
26 (0x19)
7:0
392KHz
26 (0x19)
7:0
98KHz
Sm = Standard Mode.
12.2 SPI
Jetson TX2/TX2i brings out three of the Tegra SPI interfaces.
Table 71. SPI Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
E3
F3
E4
F4
G13
E14
F14
F13
H14
G16
F16
H15
G15
GPIO_SEN1
GPIO_SEN4
GPIO_SEN2
GPIO_SEN3
GPIO_CAM4
GPIO_CAM7
GPIO_CAM5
GPIO_CAM6
GPIO_WAN5
GPIO_WAN8
GPIO_MDM4
GPIO_WAN6
GPIO_WAN7
SPI 0 Clock
SPI 0 Chip Select 0
SPI 0 Master In / Slave Out
SPI 0 Master Out / Slave In
SPI 1 Clock
SPI 1 Chip Select 0
SPI 1 Master In / Slave Out
SPI 1 Master Out / Slave In
SPI 2 Clock
SPI 2 Chip Select 0
SPI 2 Chip Select 1
SPI 2 Master In / Slave Out
SPI 2 Master Out / Slave In
SPI0_CLK
SPI0_CS0#
SPI0_MISO
SPI0_MOSI
SPI1_CLK
SPI1_CS0#
SPI1_MISO
SPI1_MOSI
SPI2_CLK
SPI2_CS0#
SPI2_CS1#
SPI2_MISO
SPI2_MOSI
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage on the Carrier
Board
Display Connector
Expansion Header
Display/Camera Conns.
Direction
Pin Type
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
Bidir
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
65
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 36. SPI Connections
Jetson TX2/TX2i
Tegra – SPI
AO
120Ω@100MHz
GPIO_SEN1
GPIO_SEN2
GPIO_SEN3
GPIO_SEN4
CAM
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_CS0#
SPI1_CLK
GPIO_CAM4
GPIO_CAM5
GPIO_CAM6
GPIO_CAM7
SPI1_MISO
SPI1_MOSI
SPI1_CS0#
SPI1_CS1#
UART
SPI2_CLK
GPIO_WAN5
GPIO_WAN6
GPIO_WAN7
GPIO_WAN8
GPIO_MDM4
SPI2_MISO
SPI2_MOSI
SPI2_CS0#
SPI2_CS1#
E3
E4
F4
F3
G13
F14
F13
Touch
Expansion
E14
E13
H14
H15
G15
G16
F16
Display (CS0)
Camera (CS1)
The figure below show s the basic connections used.
Figure 37. Basic SPI Master/Slave Connections
Jetson TX2/TX2i
SPIn_CSx#
Master
SPI Slave Device
CS (Chip Select)
SPIn_SCK
CLK (Clock)
Jetson TX2/TX2i
SPIn_CSx#
Master
SPIn_SCK
SPI Master Device
CS (Chip Select)
CLK (Clock)
SPIn_MOSI
MOSI (Master out, Slave in)
SPIn_MOSI
MOSI (Master out, Slave in)
SPIn_MISO
MISO (Master in, Slave out)
SPIn_MISO
MISO (Master in, Slave out)
SPI Design Guidelines
Figure 38. SPI Point-Point Topology
Jetson TX2/
TX2i
Die
PKG
Main trunk
SPI
Device
Figure 39. SPI Star Topologies
Jetson TX2/
TX2i
Die
Branch-A
SPI
Device #1
Branch-B
SPI
Device #2
PKG
Main trunk
Figure 40. SPI Daisy Topologies
Branch-A
Jetson TX2/
TX2i
Die
SPI
Device #1
PKG
Main trunk
Branch-B
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
SPI
Device #2
66
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Table 72. SPI Interface Signal Routing Requirements
Parameter
Max Frequency
Configuration / Device Organization
Max Loading (total of all loads)
Reference plane
Breakout Region Impedance
Max PCB breakout delay
Trace Impedance
Via proximity (Signal to reference)
Trace spacing
Microstrip / Stripline
Max Trace Length/De lay (PCB Main Trunk)
Point-Point
For MOSI, MISO, SCK & CS
2x-Load Star/Daisy
Max Trace Length/De lay (Branch-A)
2x-Load Star/Daisy
for MOSI, MISO, SCK & CS
Max Trace Length/De lay (Branch-B)
2x-Load Star/Daisy
for MOSI, MISO, SCK & CS
Max Trace Length/Delay Skew from MOSI, MISO & CS to SCK
Note:
Requirement
65
3
15
GND
Minimum width & spacing
75
50 – 60
< 3.8 (24)
4x / 3x
195 (1228)
120 (756)
75 (472)
Units
MHz
load
pF
ps
Ω
mm (ps)
dielectric
Notes
±15%
See Note 1
mm (ps)
mm (ps)
75 (472)
mm (ps)
16 (100)
mm (ps)
At any point
Up to 4 signal Vias can share a single GND return Via
Table 73. SPI Signal Connections
Module Pin Names
SPI[2:0]_CLK
SPI[2:0]_MOSI
SPI[2:0]_MISO
SPI2_CS[1:0]#
SPI[1:0]_CS0#
Type
I/O
Termination
SPI0_CLK has 120Ω Bead in series
(on the module).
I/O
I/O
I/O
Description
SPI Clock.: Connect to Peripheral CLK pin(s)
SPI Data Output: Connect to Slave Peripheral MOSI pin(s)
SPI Data Input: Connect to Slave Peripheral MISO pin(s)
SPI Chip Selects.: Connect one CS_N pin per SPI IF to each Slave
Peripheral CS pin on the interface
Table 74. Recommended SPI observation (test) points for initial boards
Test Points Recommended
One for each SPI signal line used
Location
Near the module & Device pins.
12.3 UART
Jetson TX2/TX2i brings five UARTs out to the main connector. One of the UARTs is used for the WLAN/BT on Jetson TX2 or
as UART3 at the connector depending on the setting of a multiplexor. See Table 76 for typical assignments of the UARTs.
Table 75. UART Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
H11
G11
G12
H12
E10
E9
D10
D9
A15
A16
B15
B16
G9
G10
H9
H10
D5
UART1_CTS
UART1_RTS
UART1_RX
UART1_TX
UART3_CTS
UART3_RTS
UART3_RX
UART3_TX
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
UART4_CTS_N
UART4_RTS_N
UART4_RX
UART4_TX
UART7_RX
UART 0 Clear to Send
UART 0 Request to Send
UART 0 Receive
UART 0 Transmit
UART 1 Clear to Send
UART 1 Request to Send
UART 1 Receive
UART 1 Transmit
UART 2 Clear to Send
UART 2 Request to Send
UART 2 Receive
UART 2 Transmit
UART 3 Clear to Send (muxed on TX2)
UART 3 Request to Send (muxed on TX2)
UART 3 Receive (muxed on TX2)
UART 3 Transmit (muxed on TX2)
UART 7 Receive
UART0_CTS#
UART0_RTS#
UART0_RX
UART0_TX
UART1_CTS#
UART1_RTS#
UART1_RX
UART1_TX
UART2_CTS#
UART2_RTS#
UART2_RX
UART2_TX
UART3_CTS#
UART3_RTS#
UART3_RX
UART3_TX
UART7_RX
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage on the Carrier
Board
Debug Header
Serial Port Header
M.2 Key E
Not assigned
Optional source of
UART on Exp. Header
Not Assigned
Direction
Pin Type
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
67
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
D8
UART7_TX
UART 7 Transmit
UART7_TX
Usage on the Carrier
Board
Direction
Pin Type
Output
CMOS – 1.8V
Table 76. UART Interface Mapping
Module Pins (Tegra Functions)
UART0 (UART1)
UART1 (UART3)
UART2 (UART2)
UART3 (UART4)
I/O Block
DEBUG
AO
UART
CONN
Typical Usage
Debug
Serial Port
M.2 socket for external WLAN / BT
Jetson TX2
Misc. Available if not used for on-module WLAN
/ BT (selected by on-module multiplexor)
UART7 (UART7)
Jetson TX2i
Misc (no mux inv olved)
2nd Debug/Misc.
AO
Figure 41. UART Connections
Jetson TX2/TX2i
Tegra – UART
AO
UART3_TX
UART3_RX
UART3_RTS_N
UART3_CTS_N
(RAM_CODE1 Strap) UART 1_TX
UART7_TX
UART7_RX
(RAM_CODE1 Strap) RSVD
UART 1_CTS#
RSVD
UART3_TX
CONN
Jet son TX2
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
Jetson TX2i
DEBUG
UART 3_RX
UART 3_RTS#
Mux
UART 3_CTS#
D9
D10
E9
E10
Serial Port,
etc.
UART 7_TX_AP
D8
UART 7_RX_AP
D5
Misc.
H10
H9
G10
G9
Misc.
H10
H9
G10
G9
Misc.
WiFi / BT on
Jetson TX2
UART 3_TX
UART4_TX
UART4_RX
UART4_RTS_N
UART4_CTS_N
UART1_TX
UART1_RX
UART1_RTS_N
UART1_CTS_N
UART 3_RX
UART 3_RTS#
UART3_CTS#
UART0_TX
UART0_RX
(RAM_CODE0 Strap) UART 0_RTS#
UART 0_CTS#
UART 2_TX
UART2_TX
UART2_RX
UART2_RTS_N
UART2_CTS_N
UART
Note:
UART 1_RX
UART 1_RTS#
UART 2_RX
UART2_RTS#
UART2_CTS#
H12
G12
G11
H11
B1 6
B1 5
A16
A15
Used for
Debug, etc.
M.2 Conn.
(2nd WiFi/Bt)
Care should be taken when using UART pins that are associated with Tegra straps. See Strapping Pins section for details.
Table 77. UART Signal Connections
Ball Name
UART[7,3:0]_TX
UART[7,3:0]_RX
UART[3:0]_CTS#
UART[3:0]_RTS#
Type
O
I
I
O
Termination
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Description
UART Transmit: Connect to Peripheral RXD pin of device
UART Receive: Connect to Peripheral TXD pin of device
UART Clear to Send: Connect to Peripheral RTS_N pin of device
UART Request to Send: Connect to Peripheral CTS pin of device
68
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
12.4 Fan
Jetson TX2/TX2i provides PWM and Tachometer functionality for controlling a fan as part of the thermal solution. Information on
the PWM and Tachometer pins/functions can be found in the follow ing locations:
Module Pin Mux:
▪
This is used to configure the FAN_PWM & FAN_TACH pins. The FAN_PWM pin is configured as GP_PWM4.
The FAN_TACH pin is configured as NV_THERM_FA N_TACH.
Tegra X2 Technical Reference Manual:
▪
Functional descriptions and related registers can be found in the TRM for the FAN_PWM (PWM chapter) &
FAN_TACH (Tachometer chapter) functions.
Jetson Developer Kit Carrier Board Specification:
▪
The document contains the maximum current capability of the VDD_5V0_IO_SYS supply in the Interface Pow er
chapter (VDDIO_5V0_IO_SLP comes from that supply). The fan is pow ered by this supply on the module
Developer Kit carrier board.
Table 78. Fan Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
C16
B17
GPIO_SEN6
UART5_TX
Fan PWM
Fan Tach
FAN_PWM
FAN_TACH
Usage on the Carrier
Board
Fan
Direction
Pin Type
Output
Input
CMOS – 1.8V
CMOS – 1.8V
Figure 42. Fan Connection Example
VDD_1V8
VDD_5V0_IO_SLP
AO
GPIO_SEN6
FAN_PWM
UART5_TX
FAN_TACH
UART
D
100Ω
10kΩ
Tegra – Fan
100kΩ
4. 7kΩ
Jetson TX2/TX2i
10uF
0.1uF
G
C16
Fan
Header
4
S
3
2
B1 7
VDD_5V0_IO_SYS
100kΩ
D
10pF
G
PS_VDD_FAN_DISABLE
(G PIO Expander P04)
1
10pF
S
Table 79. Fan Signal Connections
Module Name
FAN_PWM
FAN_TACH
Type
O
I
Termination
ESD diode to GND
Description
Fan Pulse Width Modulation: Connect through FET as shown in the Fan
Connections figure.
Fan Tachometer: Connect to TACH pin on fan connector.
12.5 CAN
Jetson TX2/TX2i brings tw o CAN (Controller Area Netw ork) interfaces out to the main connector.
Table 80. CAN Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
C20
E18
D18
D19
C19
D17
CAN_GPIO4
CAN_GPIO5
CAN0_DIN
CAN0_DOUT
CAN_GPIO3
CAN1_DIN
CAN Wake
CAN #0 Error
CAN #0 Receive
CAN #0 Transmit
CAN #1 Error
CAN #1 Receive
CAN_WAKE
CAN0_ERR
CAN0_RX
CAN0_TX
CAN1_ERR
CAN1_RX
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage on the Carrier
Board
GPIO Expansion
Header
Direction
Pin Type
Input
Input
Input
Output
Input
Input
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
69
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
C17
C18
CAN_GPIO6
CAN1_DOUT
CAN #1 Standby
CAN #1 Transmit
CAN1_STBY
CAN1_TX
Usage on the Carrier
Board
Direction
Pin Type
Output
Output
CMOS 3.3V
CMOS 3.3V
Figure 43. CAN Connections
Jetson TX2/TX2i
Tegra - CAN
AO_HV
CAN #1
CAN1_TX
CAN1_DOUT
CAN1_DIN
CAN1_RX
CAN0_DOUT
CAN0_DIN
CAN0_RX
CAN0_TX
CAN1_ERR
CAN_GPIO3
CAN_GPIO4
CAN_GPIO5
CAN_GPIO6
CAN_WAKE
CAN0_ERR
CAN1_STBY
C18
D17
D19
D18
CAN #0
C19
C20
E18
CAN Wake
C17
Table 81. CAN Interface Signal Routing Requirements
Parameter
Max Data Rate / Frequency
Configuration / Device Organization
Reference plane
Trace Impedance
Via proximity (Signal via to GND return via)
Trace spacing
Max Trace Length (for RX & TX only)
Max Trace Length/Delay Skew from RX to TX
Microstrip / Stripline
Requirement
1
1
GND
50
< 3.8 (24)
4x / 3x
223 (1360)
8 (50)
Units
Mbps / MHz
load
Notes
Ω
mm (ps)
dielectric
±15%
See Note 1
mm (ps)
mm (ps)
See Note 2
See Note 2
Table 82. CAN Signal Connections
Ball Name
CAN[1:0]_TX
CAN[1:0]_RX
CAN[1:0]_ERR
CAN1_STBY
CAN_WAKE
Type
O
I
I
O
I
Termination
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Description
CAN Transmit: Connect to matching pin of device
CAN Receive: Connect to Peripheral pin of device
CAN Error: Connect to matching pin of device
CAN Standby: Connect to matching pin of device
CAN Wake: Connect to matching pin of device
70
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
12.6 Debug
Figure 44. Debug Connections
Jetson TX2/TX2i
JTAG_T MS
JTAG_T DI
JTAG_TCK
JTAG_TDO
JTAG_GP0
100kΩ
100kΩ
100kΩ
JTAG_GP1
0.1uF
To PMIC
RESET_IN
A13
B1 3
A11
A47
0Ω
See Note 1
VDD_1V8
UART0_TX
UART1_TXD
UART1_RXD
UART1_RTS_N
UART1_CTS_N
A14
A12
B1 2
B1 1
UART 0_RX
UART 0_RTS#
UART0_CTS#
VDD_3V3_SYS
H12
G12
G11
100kΩ
JTAG_RTCK
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_TRST_N
NVJTAG_SEL
100kΩ
Tegra
DEBUG
Optional JTAG
connections
RTCK
TMS
TDI
TCLK
TDO
TRST_N
RST
VDD_1V8
Level
Shifter
For Debug Use
H11
See Note 2
DP
RSVD
UART7_TX
UART7_RX
Notes:
1.
2.
3.
RSVD
D8
D5
JTAG_GP1 (Tegra NVJTAG_SEL) is left unconnected (pulled down on module) for normal operation and pulled to 1.8V for
Boundary Scan Mode.
If level shifter is implemented, pull-ups are required the RX & CTS lines on the non-Tegra side of the level shifter. This is
required to keep the inputs from floating and toggling when no device is connected to the debug UART.
Check preferred JTAG debugger documentation for JTAG PU/PD reco mmendations.
12.6.1 JTAG
JTAG is not required, but may be useful for new design bring-up or for Boundary Scan.
Table 83. JTAG Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
B13
JTAG_TRST_N
JTAG Test Reset
JTAG_GP0
A11
JTAG_GP1
NVJTAG_SEL
A14
B11
B12
A13
A12
JTAG_RTCK
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
−
JTAG_TCK
JTAG_TDI
JTAG_TD0
JTAG_TMS
JTAG General Purpose 1. Pulled low on
module for normal operation & pulled
high by test device for Boundary Scan
test mode.
JTAG Return Clock
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Usage on the Carrier
Board
JTAG Header & Debug
Connector
JTAG
JTAG Header & Debug
Connector
Direction
Pin Type
Input
CMOS – 1.8V
Input
CMOS – 1.8V
Input
Input
Input
Output
Input
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Table 84. JTAG Signal Connections
Module Pin
(function) Name
JTAG_TMS
JTAG_TCK
JTAG_TDO
JTAG_TDI
JTAG_RTCK
Type
I
I
O
I
I
Termination
100kΩ to GND (on the module)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Description
JTAG Mode Select: Connect to TMS pin of connector
JTAG Clock: Connect to TCK pin of connector
JTAG Data Out: Connect to TDO pin of connector
JTAG Data In: Connect to TDI pin of connector
JTAG Return Clock: Connect to RTCK pin of connector
71
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JTAG_GP0#
(JTAG_TRST_N)
JTAG_GP1
I
100kΩ to GND &
0.1uF to GND (on the module)
100kΩ to GND (on the module)
JTAG General Purpose Pin #0: Connect to TRST pin of connector
JTAG General Purpose Pin #1: Used as select
Normal operation: Leave series resistor from NVJTAG_SEL not stuffed.
Scan test mode: Connect NVJTAG_SEL to VDD_1V8 (install 0Ω resistor as
shown).
12.6.2 Debug UART
Jetson TX2/TX2i provides UART0 for debug purposes. The connections are show n in Figure 44 and described in the table
below .
Table 85. Debug UART Connections
Module Pin Name
UART0_TXD
UART0_RXD
Type
O
I
UART0_RTS#
O
UART0_CTS#
I
Termination
If level shifter implemented, 100kΩ to supply
on the non-the module side of the device.
4.7kΩ to GND or VDD_1V8 on the module for
RAM Code strapping
If level shifter implemented, 100kΩ to supply
on the non-the module side of the device.
Description
UART #0 Transmit: Connect to RX pin of serial device
UART #0 Receive: Connect to TX pin of serial device
UART #0 Request to Send: Connect to CTS pin of serial device
UART #0 Clear to Send: Connect to RTS pin of serial device
12.6.3 Boundary Scan Test Mode
To support Boundary Scan Test mode, the Tegra NVJTAG_SEL pin must be pulled high and Tegra must be held in reset
w ithout resetting the PMIC. The figure below illustrates this. Other requirements related to supporting Boundary Scan Test
mode are described in the “Tegra X2 Boundary Scan Requirements & Usage” document.
Figure 45. Boundary Scan Connections
Jetson TX2/TX2i
Tegra
NVJTAG_SEL
JTAG_GP0
100kΩ
100kΩ
JTAG_GP1
VDD_1V8
SYS_RESET_N
eMMC
RESET_OUT#
RESET*
PMIC
RST I/O
RESET_IN#
10kΩ
B1 3
A11
100kΩ
JTAG_TRST_N
A46
A47
TRST on JTAG Connector
R1 - 0 Ω
VDD_1V8
Leave Resistors R1 & R2 uninstalled
for normal operation. Install both
for boundary scan test mode.
R2 - 0Ω
Devices requiring system reset
& System Reset Sources
1.8V
12.7 Strapping Pins
Jetson TX2/TX2i has one strap (FORCE_RECOV#) that is intended to be used on the carrier board. That strap is used to enter
Force Recovery mode. The other straps mentioned in this section are for use on the module by Nvidia only. They are included
here as their state at pow er-on must be kept at the level selected on the module.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
72
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 46. Strap Connections
Tegra
Jetson TX2/TX2i
~100kΩ
1.8V
~100kΩ
~100kΩ
RECOVERY
SYS
GPIO_SW1
GPIO_SW2
GPIO_SW4
RCM0 Strap
FORCE_RECOV#
RCM1 Strap
SLEEP#
BT Wake AP
(On-Module
Bt/Wi-Fi – TX2 only)
RCM2 Strap
1.8V
DEBUG
E1
E2
VOL DN / SLEEP
(See Note)
RAM_CODE1 Strap
UART3_TX
UART7_TX
BOOT_SELECT2 Strap
4.7kΩ
AO
4.7kΩ
RAM_CODE0 Strap
UART1_RTS_N
UART 0_RTS
G11
~100kΩ
UART 1_TX
~100kΩ
D9
~100kΩ
UART7_TX
UART4_TX
UART4_RTS_N
UART3_TX
SPI
~100kΩ
UART3_RTS
Mux
4.7kΩ
BOOT_SELECT0 Strap
4.7kΩ
~100kΩ
BOOT_SELECT1 Strap
4.7kΩ
CONN
SEL
D8
H10
G10
UART
(On-Module
Bt/Wi-Fi – TX2 only)
QSPI_IO2
Table 86. Power-on Strapping Breakdown
Module Pin
Name
Tegra Ball Name
Strap Options
Module
PU/PD
RCM0
RCM1
Tegra
Internal
PU/PD
~100kΩ PU
~100kΩ PU
FORCE_RECOV#
SLEEP#
GPIO_SW1
GPIO_SW2
UART1_TX
UART3_TX
RAM_CODE1
~100kΩ PD
4.7KΩ PU
or none
UART0_RTS
UART1_RTS_N
RAM_CODE0
~100kΩ PD
RSVD-D8
NA (see note 5)
NA (see note 5)
UART7_TX
UART4_TX
UART4_RTS_N
BOOT_SELECT2
BOOT_SELECT1
BOOT_SELECT0
~100kΩ PD
~100kΩ PD
~100kΩ PD
4.7KΩ PU
or none
4.7kΩ PD
4.7kΩ PD
4.7kΩ PD
Note:
1.
2.
3.
4.
Description
Recovery Mode [1:0]
x1: Normal boot from secondary device
10: Forced Recovery Mode
00: Reserved
See critical warning in note 1
[3:2] Selects secondary boot device configuration set
within the BCT. For Nvidia use only.
[1:0] Selects DRAM configuration set within the BCT. For
Nvidia use only.
See critical warning in Note 2.
Software reads value and determines Boot device to be
configured and used
000 = eMMC x8 BootModeOFF, 512-byte page. Maps to
SDMMC w/config=0x0001 size. 26MHz
001 – 111 Reserved
See Note 3 & 5. See critical warning in Note 4.
If the SLEEP# pin is used in a design, it must not be drive n or pulled low during power-on at the same time as
FORCE_RECOV# is pulled low for Recovery Mode as this would change the strapping and select a reserved mode.
Violating this requirement will prevent the system from entering Recovery Mode.
If UART1_TX or UART0_RTS are used in a design, they must not be driven or pulled high or low during power-on.
Violating this requirement can change the RAM_CODE strapping & result in functional failures.
The above BOOT_SELECT option is only in effect in "regular boot" conditions i.e. coldboot. If "Forced Recovery" mode is
detected (FORCE_RECOV# low at boot), that mode take precedence over the eMMC boot device choice.
If UART7_TX (on RSVD pin) is used in a design, it must not be driven or pulled high during power-on as this would affect
the BOOT_SELECT strapping. Violating this requirement will likely prevent the system from booting.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
73
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
5.
eMMC boot does not use either the normal boot mode or alternate boot mode supported by the eMMC spec. The Tegra
BootROM uses the Card Identification mode for booting from eMMC.
6.
Tegra UART4_TX & UART4_RTS_N are routed to a mux on Jetson TX2 and directed to either UART3_TX/RTS or On-module WLAN/BT.
Since these pins are outputs, and the mux is in the path, Jetson TX2 UART3 pins will not affect the Boot Select [1:0] strapping. On Jetson
TX2i, the Tegra UART4 pins are routed directly to the UART3 pins on the module. If these pins are used in a design, they must not
be driven or pulled high during power-on as this would affect the BOOT_SELECT strapping. Violating this requirement
will likely prevent the system from booting.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
74
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
13.0 PADS
13.1 MPIO Pad Behavior when Associated Power Rail is Enabled
Jetson TX2/TX2i CZ (see note) type MPIOs pins may glitch w hen the associated pow er rail is enabled or disabled. Designers
should take this into account. MPIOs of this type that must maintain a low state even w hile the pow er rail is being ramped up or
dow n may require special handling. The CZ type pins are used on the follow ing module pins:
-
I2S[3:2]_x
SDCARD_x
CANx
Note:
-
AO_DMIC_IN_x
GPIO[18,17,11,9,8,6]/x
SDIO_x (TX2i only )
The Pin Descriptions section of the Jetson TX2/TX2i Data Sheet includes the pin type information.
13.2 Internal Pull-ups for CZ Type Pins at Power-on
The MPIO pads of type CZ (see note) are on blocks that can be pow ered at 1.8V or 3.3V. If the associated block is pow ered at
1.8V, the internal pull-up at initial pow er-on is not effective. The signal may only be pulled up a fraction of the 1.8V rail. Once
the system boots, softw are can configure the pins for 1.8V operation and the internal pull-ups w ill w ork correctly. Signals that
need the pull-ups during pow er-on should have external pull-up resistors added. If the associated block is pow ered at 3.3V by
default, the pull-ups w ork correctly. The affected pins listed below . These are the module CZ Type Pins on blocks pow ered at
1.8V w ith Pow er-on-Reset Default of Internal Pull-up Enabled. The SD_CARD & SDIO (TX2i only) pins are CZ type, but the
associated pow er rails are not enabled at pow er-on – softw are enables these at a later time. As long as the sof tw are configures
the pins appropriately for the voltage, the issue w ill not affect the SD_CARD & SDIO (TX2i only) pins.
-
CAN1_DOUT
CAN1_DIN
CAN0_DOUT
CAN0_DIN
Note:
The Pin Descriptions section of Jetson TX2/TX2i Data Sheet includes the pin type information.
13.3 Schmitt Trigger Usage
The MPIO pins have an option to enable or disable Schmitt Trigger mode on a per -pin basis. This mode is recommended for
pins used for edge-sensitive functions such as input clocks, or other functions w here each edge detected w ill affect the
operation of a device. Schmitt Trigger mode provides better noise immunity, and can help avoid extra edges from being “seen”
by the Tegra inputs. Input clocks include the I2S & SPI clocks (I2Sx_SCLK & SPIx_SCK) w hen Tegra is in slave mode . The
FAN_TACH pin is another input that could be affected by noise on the signal edges. The SD_CARD pin (Tegra SDMMC1_CLK
function), w hile used to output the SD clock, also samples the clock at the input to help w ith read timing. Therefore, the
SD_CARD_CLK pin may benefit from enabling Schmitt Trigger mode. Care should be taken if the Schmitt Trigger mode setting
is changed from the default initialization mode as this can have an effect on interface timing.
13.4 Pins Pulled/Driven High During Power-on
Jetson TX2/TX2i is pow ered up before the carrier board (See Pow er Sequencing section). The table below lists the pins on the
module that default to being pulled or driven high. Care must be taken on the carrier board design to ensure that any of these
pins that connect to devices on the carrier board (or devices connected to the carrier board) do not cause damage or excessive
leakage to those devices. The SD_CARD & SDIO (TX2i only) pins are not included because the associated pow er rails are not
enabled at pow er-on – softw are enables these at a later time. Some of the w ays to avoid issues w ith sensitive devices are:
▪
External pull-dow ns on the carrier board that are strong enough to keep the signals low are one solution, given that
this does not affect the function of the pin. This w ill not w ork w ith RESET_IN# w hich is actively driven high.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
75
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
▪
Buffers or level shifters can be used to separate the signals from devices that may be affected. The buffer/shifter
should be disabled until the device pow er is enabled.
Table 87. Module Pins Pulled/Driven High by Tegra Prior to CARRIER_PWR_ON Active
Module Pin
DSPK_OUT_CLK
SPI1_CS0#
RESET_IN#
FORCE_RECOV#
SLEEP#
GPIO7_TOUCH_RST
CARRIER_STBY#
GPIO5/CAM_FLASH_EN
USB0_VBUS_DET
SPI2_CS1#
SPI2_CS0#
UART0_TX
UART0_RX
WDT_TIME_OUT#
Power-on Reset
Default
Internal Pull-up
Internal Pull-up
Driven High
Internal Pull-up
Internal Pull-up
Driven High
Driven High
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Driven High
Pull-up Strength
(kΩ)
~100
~100
na
~100
~100
na
na
~100
~100
~100
~100
~100
~100
na
Module Pin
JTAG_TMS
JTAG_TDI
UART1_RX
SPI0_MISO
SPI0_MOSI
CAN1_TX
CAN1_RX
CAN0_TX
CAN0_RX
GPIO6_TOUCH_INT
GPIO3_CAM1_RST#
CAM_VSYNC
GPIO2_CAM0_RST#
Power-on Reset
Default
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Internal Pull-up
Driven High
Internal Pull-up
Internal Pull-up
Internal Pull-up
Pull-up Strength
(kΩ)
~100
~100
~100
~100
~100
~20
~20
~20
~20
na
~18
~18
~18
Table 88. Module Pins Pulled High on the Module Prior to CARRIER_PWR_ON Active
Module Pin
VIN_PWR_BAD#
RESET_OUT#
I2C_GP0_CLK/DAT
I2C_GP1_CLK/DAT
I2C_GP2_CLK/DAT
I2C_GP3_CLK/DAT
I2C_PM_CLK/DAT
I2C_CAM_CLK/DAT
Pull-up Supply
Voltage (V)
5.0
1.8
1.8
3.3
1.8
1.8
1.8
1.8
External
Pull-up (kΩ)
10
100
1.0
1.0
1.0
1.0
1.0
1.0
Module Pin
USB0_EN_OC#
USB1_EN_OC#
PEX0_CLKREQ#
PEX0_RST#
PEX1_CLKREQ#
PEX1_RST#
PEX2_CLKREQ#
PEX2_RST#
PEX_WAKE#
Pull-up Supply
Voltage (V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
External
Pull-up (kΩ)
100
100
56
56
56
56
56
56
56
13.5 Pad Drive Strength
The table below provides the maximum MPIO pad output drive current w hen the pad is configured for the maximum
DRVUP/DRVDN values (11111b). The MPIO pad types include the ST, DD, CZ and LV_CZ type pads. The pad types can be
found in the Jetson TX2/TX2i Module Data Sheet.
Table 89. MPIO Maximum Output Drive Current
IOL/IOH
+/- 1mA
+/- 1mA
+/- 1mA
+/- 1mA
+/- 1mA
Pad Type
ST
DD
CZ (1.8V mode)
CZ (3.3V mode)
LV_CZ
VOL
0.15*VDD
0.15*VDD
0.15*VDD
0.15*VDD
0.15*VDD
VOH
0.825*VDD
0.8*VDD
0.85*VDD
0.85*VDD
0.85*VDD
+/- 2mA
+/- 2mA
+/- 2mA
+/- 2mA
+/- 2mA
ST
DD
CZ (1.8V mode)
CZ (3.3V mode)
LV_CZ
0.15*VDD
0.175*VDD
0.25*VDD
0.15*VDD
0.25*VDD
0.7*VDD
0.7*VDD
0.75*VDD
0.75*VDD
0.75*VDD
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
76
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
14.0 UNUSED INTERFACE TERMINATIONS
14.1 Unused MPIO Interfaces
The follow ing Jetson TX2/TX2i pins (& groups of pins) are MPIO (Multi-purpose Standard CMOS Pad) pins that support either
special function IOs (SFIO) and/or GPIO capabilities. Any unused pins or portions of pin groups listed below that are not used
can be left unconnected.
Table 90. Unused MPIO pins / Pin Groups
Module Pins / Pin Groups
SLEEP#
BATLOW#
FORCE_RECOV#
RESET_OUT#
WDT_TIME_OUT#
CARRIER_STBY#
CHARGER_PRSNT#
CHARGING#
USBx_EN_OC#
PEXx_REFCLK/RST/CLKREQ/WAKE
LCD0_BKLT_PWM, FAN_PWM
CAN
LCD_x
DP0_HPD, DP1_HPD, HDMI_CEC
CAM Control, Clock
Module Pins / Pin Groups
SD_CARD, SDIO (TX2i only)
AUDIO_x
I2S
DMIC
DSPK
UART
I2C
SPI
TOUCH_x
WIFI_WAKE_x
MODEM_x, MDM2AP_x, AP2MDM_x
GPIO_EXP[1:0]_INT
ALS_PROX_INT, MOTION_INT
JTAG
14.2 Unused SFIO Interface Pins
See the Unused SFIO (Special Function I/O) interface pins section in the Checklist at the end of this document.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
77
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
15.0 DESIGN CHECKLIST
The checklist below is intended to help ensure that the correct connections have been made in a design. The check items
describe connections for the various interfaces and the “Same/Diff/NA” column is intended to be used to indicate w hether the
design matches the check item description, is different, or is not applicable to the design.
Table 91. Checklist
Same/Diff/NA
Check Item Description
Module Signal Terminations (Present on the module - shown for reference only)
Note: Internal refers to Tegra internal Pull-up/down resistors. External refers to resistors added on the module.
Parallel Termination
Series Termination
USB0_EN_OC#
USB1_EN_OC#
USB0_VBUS_DET
External 100KΩ pull-up to 3.3V
External 100KΩ pull-up to 3.3V
PEX0_CLKREQ#
PEX0_RST#
PEX1_CLKREQ#
PEX1_RST#
PEX2_CLKREQ#
PEX2_RST#
PEX_WAKE#
External
External
External
External
External
External
External
–
–
Level shifter between Tegra & the module
USB0_VBUS_DET pin
–
–
–
–
–
–
–
USB/PCIe
56KΩ pull-up
56KΩ pull-up
56KΩ pull-up
56KΩ pull-up
56KΩ pull-up
56KΩ pull-up
56KΩ pull-up
to 3.3V
to 3.3V
to 3.3V
to 3.3V
to 3.3V
to 3.3V
to 3.3V
HDMI/DP/eDP
DP0_HPD
DP1_HPD
Internal pull-down
Internal pull-down
–
–
External
External
External
External
External
External
–
–
–
–
–
–
I2C
I2C_GP0_CLK/DAT
I2C_GP1_CLK/DAT
I2C_GP2_CLK/DAT
I2C_GP3_CLK/DAT
I2C_PM_CLK/DAT
I2C_CAM_CLK/DAT
1KΩ pull-up to 1.8V
1KΩ pull-up to 3.3V
1KΩ pull-up to 1.8V
1KΩ pull-up to 1.8V
1KΩ pull-up to 1.8V
1KΩ Pull Up to 1.8V
SPI
SPI0_MOSI
SPI0_MISO
SPI0_CLK
SPI0_CS0#
SPI1_MOSI
SPI1_MISO
SPI1_CLK
SPI1_CS0#
SPI2_MOSI
SPI2_MISO
SPI2_CLK
SPI2_CS0#
SPI2_CS1#
Internal pull-down
Internal pull-down
Internal pull-down
Internal pull-up to 1.8V
Internal pull-down
Internal pull-down
Internal pull-down
Internal pull-up to 1.8V
Internal Pull Down
Internal Pull Down
Internal Pull Down
Internal pull-up to 1.8V
Internal pull-up to 1.8V
–
–
–
–
–
–
–
–
–
–
–
–
–
Internal pull-up
Internal pull-up
Internal pull-up
Internal pull-up
–
–
–
–
SD Card
SDCARD_CMD
SDCARD_D[3:0]
SDCARD_CD#
SDCARD_WP
to 1.8V/3.3V
to 1.8V/3.3V
to 1.8V
to 1.8V
SD Card
SDIO_CMD
SDIO_D[3:0]
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Embedded Display
LCD_TE
Internal pull-down
–
GPIO
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
78
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
GPIO0_CAM0_PWR
GPIO1_CAM1_PWR
GPIO2_CAM0_RST
GPIO3_CAM1_RST
GPIO4_CAM_STROBE
GPIO5_CAM_FLASH_EN
GPIO6/TOUCH_INT
GPIO7/TOUCH_RST
GPIO8/ALS_PROX_INT
GPIO9/MOTION_INT
GPIO10/WIFI_WAKE_AP
GPIO11_AP_WAKE_BT
GPIO12_BT_EN
GPIO13/BT_WAKE_AP
GPIO14_AP_WAKE_MDM
GPIO15_AP2MDM_READY
GPIO16/MDM_WAKE_AP
GPIO17/MDM2AP_READY
GPIO18/MDM_COLDBOOT
GPIO19/AUD_RST
GPIO20/AUD_INT
GPIO_EXP0_INT
GPIO_EXP1_INT
Internal pull-down to GND
Internal pull-down to GND
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-down to GND
Internal pull-up to 1.8V
Internal pull-up to 1.8V
(Driven high)
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-down to GND
Internal pull-down to GND
Internal pull-up to 1.8V
(Driven low)
(Driven low)
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
External 10kΩ pull-up to 3.8V
External 10kΩ pull-up to 3.3V
Internal pull-up to 1.8V
Internal pull-up to 1.8V
Internal Pull Up to 1.8V near Tegra & PMIC
internal Pull-up to 5.0V on other side of
diodes (module pin side)
External 10kΩ pull-up to 1.8V
External 100kΩ pull-up to 1.8V near Tegra
(module pin side) & external 10kΩ pull-up
to 1.8V on the other side of a diode
External 10kΩ pull-up to 1.8V
Internal pull-up to 1.8V
–
System Control
VIN_PWR_BAD#
CARRIER_PWR_ON
FORCE_RECOV#
SLEEP#
POWER_BTN#
RESET_IN#
RESET_OUT#
SYS_WAKE# (TX2i only)
FAN_TACH
–
–
BAT54CW Schottky barrier diodes
–
Charging
CHARGER_PRSNT#
CHARGING#
BATLOW#
External 4.7kΩ pull-up to 5V & Internal
–
PMIC pull-up to 5.0V once FET is enabled
by VDD_IN on & VIN_PWR_BAD# inactive.
Internal pull-up to 1.8V
–
Internal pull-up to 1.8V
–
JTAG
JTAG_TCK
JTAG_GP0
JTAG_GP1
External 100KΩ pull-down to GND
–
External 100KΩ pull-down to GND & 0.1uF –
capacitor to GND
External 100KΩ pull-down to GND
Carrier Board Signal Terminations
(To be implemented on the carrier board for interfaces that are used)
Parallel Termination
Series Termination
–
–
–
–
–
–
–
–
–
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors if directly connected
0.1uF capacitors directly connected
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors if directly connected
USB/PCIe/SATA
USB_SS0_TX+/USB_SS1_TX+/USB_SS0_RX+/USB_SS1_RX+/PEX0_TX+/PEX1_TX+/PEX2_TX+/PEX_RFU_TX+/PEX0_RX+/-
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
79
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
PEX1_RX+/PEX2_RX+/PEX_RFU_RX+/SATA_TX+/SATA_RX+/SATA_DEV_SLP
–
–
–
–
–
–
0.1uF capacitors if directly connected
0.1uF capacitors if directly connected
0.1uF capacitors
0.01uF capacitors
0.01uF capacitors
1.8V to 3.3V Level Shifter
–
–
–
–
–
–
–
Magnetics near RJ45 connector
Magnetics near RJ45 connector
Magnetics near RJ45 connector
Magnetics near RJ45 connector
LED and pull-up Current Limiting Circuit
LED and pull-up Current Limiting Circuit
LED and pull-up Current Limiting Circuit
–
–
–
–
100kΩ Pull-down to GND near connector
(DP only)
100kΩ Pull-up to 3.3V near connector (DP
only)
10kΩ Pull-up to 1.8V near main conn. &
100kΩ Pull-down to GND on DP side of
level shifter.
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors
0.1uF capacitor
499Ω, 1% resistor to 600Ω bead to GND
499Ω, 1% resistor to 600Ω bead to GND
499Ω, 1% resistor to 600Ω bead to GND
499Ω, 1% resistor to 600Ω bead to GND
10kΩ Pull-up to 3.3V near main conn. &
1.8kΩ Pull-up to 5V near HDMI conn.
10kΩ Pull-up to 1.8V near main conn. &
100kΩ Pull-down to GND near HDMI conn.
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors
0.1uF capacitors
Bidirectional level shifter between Pull-ups in
Parallel Termination column
Level shifter (w/output toward main connector)
between Pull-up & Pull-down in Parallel
Termination column. Level shifter can be
inverting or non-inverting. 100kΩ series
resistor between pull-down & HDMI connector.
Ethernet
GBE_MDI0+/GBE_MDI1+/GBE_MDI2+/GBE_MDI3+/GBE_LINK100#
GBE_LINK1000#
GBE_LINK_ACT#
DP[1:0] for eDP/DP
DPx_TX3+/DPx_TX2+/DPx_TX1+/DPx_TX0+/DPx_AUX_CH+
DPx_AUX_CHDPx_HPD
0.1uF capacitor
Level Shifter (w/output toward main
connector) near main connector & 100kΩ
resistor to DP connector. Level shifter must be
non-inverting.
DP[1:0] for HDMI
DPx_TX3+/DPx_TX2+/DPx_TX1+/DPx_TX0+/DPx_AUX_CH+/DPx_HPD
Power
Module Power Supplies
Supply (Carrier Board)
VDD_IN
Usage
Main Supply from Adapter
VDD_RTC
Real-time clock supply
(V)
Supply Type
TX2: 5.5- Adapter
19.6
TX2i:
9.0-19.0
1.65-5.5 PMIC is supply
when charging
cap or coin cell
Source
na
Enable
na
Super cap or coin
cell is source when
system power
removed
na
FETs
DC Adapter
DC/DC
DC/DC
DC/DC
VDD_MUX
VDD_MUX
VDD_5V0_IO_SYS
FETs/Load
Switch
VDD_3V3_SYS
Carrier Board Supplies
VDD_MUX
Main power input from DC
Adapter
VDD_5V0_IO_SYS
VDD_3V3_SYS
VDD_1V8
Main 5V supply
Main 3.3V supply
Main 1.8V supply
TX2: 5.519.6
TX2i:
9.0-19.0
5.0
3.3
1.8
VDD_3V3_SLP
3.3V rail, off in Sleep (various)
3.3
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
CARRIER_PWR_ON
3V3_SYS_BUCK_EN
1V8_IO_VREG_EN
(VDD_3V3_SYS_PG)
SOC_PWR_REQ
80
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
VDD_5V0_IO_SLP
5V rail, off in Sleep (SATA/FAN) 5
VDD_12V_SLP
VDD_VBUS_CON
USB_VBUS
SD_CARD_SW_PWR
VDD_5V0_HDMI_CON
VDD_TS_1V8
AVDD_TS_DIS
PCIe & SATA connectors
VBUS (USB 2.0 Type AB conn)
VBUS (USB 3.0 Type A conn)
SD Card power rail
5V rail for HDMI connector
1.8V rail for touch screen
High voltage rail for touch
screen
1.8V rail for panel
High voltage rail for panel
Generic 1.2V display rail
1.8V rail for camera I/O
High voltage rail for cameras
1.2V rail for camera Core
VDD_LCD_1V8_DIS
VDD_DIS_3V3_LCD
VDD_1V2
DVDD_CAM_IO_1V8
AVDD_CAM
DVDD_CAM_IO_1V2
VDD_5V0_IO_SYS
VDD_3V3_SLP
12
5.0
5.0
3.3
5.0
1.8
3.3
FETs/Load
Switch
Boost
Load Switch
Load Switch
Load Switch
Load Switch
Load Switch
Load Switch
VDD_5V0_IO_SYS
VDD_5V0_IO_SYS
VDD_5V0_IO_SYS
VDD_3V3_SYS
VDD_5V0_IO_SYS
VDD_1V8
VDD_3V3_SLP
VDD_3V3_SLP
USB_VBUS_EN0
USB_VBUS_EN1
SDCARD_VDD_EN
GPIO Expander U29, P14
GPIO Expander U29, P01
1.8
3.3
1.2
1.8
2.8
1.2
Load Switch
Load Switch
LDO
Load Switch
Load Switch
LDO
VDD_1V8
VDD_3V3_SYS
VDD_1V8
VDD_1V8
VDD_3V3_SLP
VDD_1V8
GPIO Expander U29,
GPIO Expander U29,
GPIO Expander U29,
GPIO Expander U28,
GPIO Expander U29,
GPIO Expander U28,
GPIO Expander U29, P02
P11
P03
P12
P11
P15
P12
Power Control
VIN_PWR_BAD# connects to Carrier Board main power input & discharge circuit. Inactive when main supply is stable
CARRIER_PWR_ON used as enable for Carrier Board main 5V supply & discharge circuit
RESET_IN# to/from carrier board connects to devices requiring full system reset, and to system reset sources (reset button, etc.)
RESET_OUT# to the module from Carrier Board when a force reset is required (as for Boundary Scan test mode)
POWER_BTN# connects to button or similar to pull POWER_BTN# to GND when pressed/asserted to power system ON/OFF
SLEEP# connects to button or similar to pull SLEEP# to GND when pressed/asserted to put system in sleep mode
CARRIER_STBY# connects to enable of supplies that should be off in Sleep mode such as VDD_3V3_SLP
Power Discharge
VIN_PWR_BAD# connects to Carrier Board main power input & discharge circuit. Inactive when main supply is stable
VDD_5V0_IO_SYS Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 100Ω to VDD_5V0_IO_SYS
VDD_3V3_SYS Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 47Ω to VDD_3V3_SYS
VDD_1V8 Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 36Ω to VDD_1V8
VDD_3V3_SLP Discharge implemented: FET enabled by DISCHARGE w/Source GND'd & 47Ω to VDD_3V3_SLP
VDD_12V_SLP Discharge implemented: FET enabled by DISCHARGE & VDD_3V3_SLP w/Source GND'd & 2x470Ω to VDD_12V_SLP
VDD_5V0_IO_SLP Discharge implemented: FET enabled by DISCHARGE & VDD_3V3_SLP w/Source GND'd & 100Ω to VDD_5V0_IO_SLP
Wake Event Pins
If Audio Interrupt required, GPIO20_AUD_INT pin is used
If External BT Wake Request to AP required, GPIO13_BT_WAKE_AP pin is used
If External WLAN Wake Request to AP required, GPIO10_WIFI_WAKE_AP pin is used
If Modem to AP Ready required, GPIO17_MDM2AP_READY pin is used
If Modem Coldboot Alert required, GPIO18_MDM_COLDBOOT pin is used
If HDMI CEC required, HDMI_CEC pin is used
If GPIO Exapander 0 Interrupt required, GPIO_EXP0_INT pin is used
If Power Button On required, POWER_BTN# pin is used
If Charging Interrupt required, CHARGING# pin is used
If Sleep Request from Carrier Board required, SLEEP# pin is used
If Ambient/Proximity Interrupt required, GPIO8_ALS_PROX_INT pin is used
If HDMI Hot Plug Detect required, DP1_HPD pin is used
If Battery Low Warning required, BATLOW# pin is used
If Primary Modem Wake Request to AP required, GPIO16_MDM_WAKE_AP pin is used
If Touch Controller Interrupt required, GPIO6_TOUCH_INT pin is used
If Motion Sensor Interrupt required, GPIO9_MOTION_INT pin is used
USB/PEX/SATA Connections
USB 2.0
USB0 available to be used as device for USB recovery at a minimum
USB ID from connector, if used, connects to the module USB0_OTG_ID pin
VBUS from connector connects to load switch (if host supported) and USB0_VBUS_DET pin on the module (100kΩ resistor to GND
required)
USB[2:0]_DP/DN connected to D+/D- pins on USB 2.0 connector/device.
Any EMI/ESD devices used are suitable for USB High-speed
USB 3.0
USB_SS0_RX+/– connected to RX+/- pins on USB 3.0 connector, Device, Hub, etc. (muxed w/PCIe #2 on module)
USB_SS0_TX+/– connected to TX+/- pins on USB 3.0 conn., Device, Hub, etc. (muxed w/PCIe #2 on module - See Signal Terminations)
Additional USB 3.0 interfaces taken from USB_SS1 or PEX_RFU (See Signal Terminations)
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
81
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
See USB 3.0 section for Common Mode Choke requirements if this is required. TDK ACM2012D-900-2P device is recommended
See USB 3.0 section for ESD requirements. SEMTECH ESD Rclamp0524p device is recommended
PCIe
PCIe Controller #0 (x1 by default – supports up to x4. Lanes [2:1] of x4 configuration shared w/USB_SS#[2:1]
PEX0 used for 3.3V single-lane device/connector (lane 0 of PCIe x1 connector on reference Carrier Board)
PEX0 & USB_SS1 used for 3.3V 2-lane device/connector
PEX0, USB_SS1, PEX2 & PEX_RFU used for 3.3V 4-lane device/connector
TX+/– connected to corresponding pins on connector, or RX+/– on device on the carrier board (See Signal Terminations)
RX+/– connected to corresponding pins on connector, or TX+/– on device on the carrier board
AC caps are provided for device TX pins (those connected to the module RX+/–) if device is on the carrier board (See Signal
Terminations)
Reference clock used for PCIe Controller #0 (Up to x4 lane PCIe interface) is PEX0_REFCLK+/–
Clock Request & Reset for PCIe Controller #0 are PEX0_CLKREQ# & PEX0_RST#
PCIe Controller #1 (x1 – Shared with PCIe Controller #0 lane 2)
PEX2 used for 3.3V single-lane device/connector
TX+/– connected to corresponding pins on connector, or RX+/– on device on the carrier board (See Signal Terminations)
RX+/– connected to corresponding pins on connector, or TX+/– on device on the carrier board
AC caps are provided for device TX pins (those connected to the module RX+/–) if device is on the carrier board (See Signal
Terminations)
Reference clock used for PCIe Controller #1 (single-lane PCIe interface) is PEX2_REFCLK+/–
Clock Request & Reset for PCIe Controller #1 are PEX2_CLKREQ# & PEX2_RST# (See Signal Terminations)
PCIe Controller #2 (x1)
PEX1 used for 3.3V single-lane device/connector (M.2 connector on Jetson carrier board) or USB_SS#0 (controlled by on module mux)
TX+/– connected to corresponding pins on connector, or RX+/– on device on the carrier board (See Signal Terminations)
RX+/– connected to corresponding pins on connector, or TX+/– on device on the carrier board
AC caps are provided for device TX pins (those connected to the module RX+/–) if device is on the carrier board (See Signal
Terminations)
Reference clock used for PCIe Controller #2 (single-lane PCIe interface) is PEX1_REFCLK+/–
Clock Request & Reset for PCIe Controller #1 are PEX1_CLKREQ# & PEX1_RST# (PEX1_CLKREQ# muxed with SATA_DEV_SLP on module See Signal Terminations)
Common
PEX_WAKE# connected to WAKE pins on devices/connectors (See Signal Terminations)
SATA
SATA_TX+/– connected to TX_P/N pins of SATA connector (or RX+/– pins of onboard device) (See Signal Terminations)
SATA_RX+/– connected to RX_P/N pins of SATA connector (or TX+/– pins of onboard device) (See Signal Terminations)
See SATA section for Common Mode Choke requirements if they are required. TDK ACM2012D-900-2P device is recommended
See SATA section for ESD requirements. SEMTECH ESD Rclamp0524p device is recommended
SATA_DEV_SLP connected to matching pin on device or connector (pin 10 on conn. shown in SATA section – See Signal Terminations)
Ethernet
GBE_MDI[3:0]+/ – connected to equivalent pins on magnetics device (See Signal Terminations)
GBE_LINK_ACT, GBE_LINK100 & GBE_LINK1000 connected to LED pins on connector (See Signal Terminations)
GBE_CTVREF – Not used. Leave NC.
SDMMC Connections
SD Card
SDCARD_CLK connected to CLK pin of socket/device
SDCARD_CMD connected to CMD pin of socket/device. (See Signal Terminations)
SDCARD_D[3:0] connected to DATA[3:0] pins of socket/device. (See Signal Terminations)
SDCARD_CD connected to the SD Card Detect pin on socket
SDCARD_WP connected to the SD Card Write Protect pin on socket (if supported)
SDCARD_PWR_EN connected to SD Card VDD supply/load switch enable pin
Adequate bypass caps provided on SD Card VDD rail
Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended).
SD Card
SDIO_CLK connected to CLK pin of device
SDIO_CMD connected to CMD pin of device. (See Signal Terminations)
SDIO_D[3:0] connected to DATA[3:0] pins of device. (See Signal Terminations)
Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended).
Display Connections
DSI
DSI Dual Link Configurations
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
82
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
DSI0_CK+/– connected to CLKp/n pins of the lower x4 DSI interface of display
DSI0_D[1:0] +/– connected to lower 2 data lanes of the lower x4 DSI interface of display
DSI1_D[1:0] +/– connected to upper 2 data lanes of the lower x4 DSI interface of display
DSI2_CK+/– connected to CLKp/n pins of the upper x4 DSI interface of display or a x4 DSI interface of secondary display
DSI2_D[1:0] +/– connected to lower 2 data lanes of the upper x4 DSI interface of display or lower 2 lanes of secondary display
DSI3_D[1:0] +/– connected to upper 2 data lanes of the upper x4 DSI interface of display or upper 2 lanes of secondary display
Any EMI/ESD devices used on DSI signals are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
DSI Split Link Configurations
DSI0_CK+/– connected to CLKp/n pins of the 1st x2 DSI interface of split link display
DSI0_D[1:0] +/– connected to up to 2 data lanes of the 1st x1/x2 DSI interface of split link display
DSI1_CK+/– connected to CLKp/n pins of the 2nd x2 DSI interface of split link display
DSI1_D[1:0] +/– connected to up to 2 data lanes of the 2nd x1/x2 DSI interface of split link display
DSI2_CK+/– connected to CLKp/n pins of the 3rd x2 DSI interface of split link display
DSI2_D[1:0] +/– connected to up to 2 data lanes of the 3rd x1/x2 DSI interface of split link display
DSI3_CK+/– connected to CLKp/n pins of the 4th x2 DSI interface of split link display
DSI3_D[1:0] +/– connected to up to 2 data lanes of the 4th x1/x2 DSI interface of split link display
Any EMI/ESD devices used on DSI signals are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
Display Control Connections
LCD_TE (used for Tearing Effect signal from display) connected to matching pin on display connector if supported
LCD_VDD_EN connected to enable of embedded display related power supply/load switch
LCD_BKLT_EN connected to enable of backlight solution(s)
LCD[1:0]_BKLT_PWM connected to PWM input(s) of backlight solution(s)
eDP / DP
DPx_TX[3:0]+/– connected to D[3:0]+/– pins on eDP/DP connector (See DP/HDMI Pin Mapping table & Signal Terminations)
DPx_AUX_CH+/– connected to Aux Lane of panel/connector (See Signal Terminations)
DPx_HPD connected to HPD pin of panel/connector
Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
HDMI
DPx_TX3+/– connected to C–/C+ & pins on HDMI Connector (See Signal Terminations)
DPx_TX[2:0]+/– connected to D[0:2]+/– pins (See DP/HDMI Pin Mapping table) (See Signal Terminations)
DPx_HPD connected to HPD pin on HDMI Connector (See Signal Terminations)
HDMI_CEC connected to CEC on HDMI Connector through gating circuitry.
DPx_AUX_CH+ connected to SCL & DPx_AUX_CH– to SDA on HDMI Connector (See Signal Terminations)
HDMI 5V Supply connected to +5V on HDMI Connector.
See HDMI section for Common Mode Choke requirements if this is required (not recommended unless EMI issues seen)
See HDMI section for ESD requirements. ON-Semiconductor ESD8040 device is recommended
Video Input
Camera (CSI)
CSI[5:0]_CLK+/– connected to clock pins of camera. See CSI D-PHY Configurations table for details
CSI[5:0]_D[1:0]+/– connected to data pins of camera. See CSI D-PHY Configurations table for details
Any EMI/ESD devices used are suitable for highest frequencies supported (low capacitive load: <1pf recommended)
Control
I2C_CAM_CK/DAT connected to I2C SCL & SDA pins of imager (See Signal Terminations).
CAM[1:0]_MCLK connected to Camera reference clock inputs.
GPIO1_CAM1_PWR# / GPIO0_CAM0_PWR# connected to powerdown pins on camera(s).
GPIO4_CAM_STROBE connected to camera strobe circuit unless strobe control comes from camera module.
CAM_FLASH_EN connected to enable of flash circuit
If a module GPIO is used for flash control, CAM_FLASH_EN and/or CAMR_STROBE pins are used
GPIO3_CAM1_RST# / GPIO2_CAM0_RST# connected to reset pin on any cameras with this function.
If AutoFocus Enable is required, GPIO3_CAM1_RST# connected to AF_EN pin on camera module & GPIO2_CAM0_RST# used as
common reset line.
Audio
Codec/I2S/DMIC/DSPK
I2S0 used for Audio Codec if present in design
I2S2 used for BT if present in design
I2S[3:0]_SCLK Connect to I2S/PCM CLK pin of audio device.
I2S[3:0]_LRCK Connect to Left/Right Clock pin of audio device.
I2S[3:0]_SDATA_OUT Connect to Data Input pin of audio device.
I2S[3:0]_SDATA_IN Connect to Data Output pin of audio device.
AUD_MCLK Connect to clock pin of Audio Codec.
GPIO8_AUD_RST Connect to reset pin of Audio Codec.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
83
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
GPIO9_AUD_INT Connect to interrupt pin of Audio Codec.
AO_DMIC_IN_CLK/DAT connect to CLK/DAT pins of digital mic
DSPK_OUT_CLK/DAT connect to CLK/DAT pins of digital speaker driver
I2C/SPI/UART
I2C
I2C devices on same I2C interface do not have address conflicts (comparisons are done 7-bit to 7-bit format or 8-bit to 8-bit format)
I2C_CAM, I2C_GP0, I2C_GP2, I2C_GP3 & I2C_PM (See Signal Terminations). Additional external pull-ups are not added unless stronger
pull-up than on module required. Devices on bus are 1.8V or level shifter is used.
I2C_GP1 (See Signal Terminations). Additional external pull-ups are not added unless stronger pull-up than on module required &
devices on bus are 3.3V or level shifter is used.
Pull-up resistors are provided on the non-module side of any level shifters.
Pull-up resistor values based on frequency/load (check I2C Spec)
I2C_CAM_CK/DAT, I2C_GP[3:0]_CK/DAT & I2C_PM_CK/DAT connect to SCL/SDA pins of devices
SPI
SPI[2:0]_CLK connected to Peripheral CLK pin(s)
SPI[2:0]_MOSI connected to Slave Peripheral MOSI pin(s)
SPI[2:0]_MISO connected to Slave Peripheral MISO pin(s)
SPI2_CS[1:0]# / SPI[1:0]_CS0# connected one CS# pin per SPI IF to each Slave Peripheral CS pin on the interface
CAN
CAN[1:0]_TX connected to input data (RX) pins of respective CAN device
CAN[1:0]_RX connected to output data (TX) pin of respective CAN device
CAN1_STBY connected to Standby pin of respective CAN device
CAN[1:0]_ERR connected to Error pin of respective CAN device
CAN_WAKE connected to Wake pin of CAN devices
UART
UARTx_TX connects to Peripheral RX pin of device
UARTx_RX connects to Peripheral TX pin of device
UARTx_CTS# connects to Peripheral RTS# pin of device
UARTx_RTS# connects to Peripheral CTS# pin of device
Miscellaneous
JTAG
JTAG_TMS Connect to TMS pin of connector
JTAG_TCK Connect to TCK pin of connector (See Signal Terminations).
JTAG_TDO Connect to TDO pin of connector
JTAG_TDI Connect to TDI pin of connector
JTAG_RTCLK Connect to RTCK pin of connector
JTAG_GP0 (JTAG_TRST#): Connect to TRST pin of connector
JTAG_GP1 (NVJTAG_SEL): For Boundary Scan test mode, NVJTAG_SEL is connected to VDD_1V8. (See Signal Terminations).
JTAG_GP1 (NVJTAG_SEL): For normal operation, NVJTAG_SEL is pullled down. (See Signal Terminations).
Strapping
FORCE_RECOV#: To enter Forced Recovery mode, pin is connected to GND when system is powered on.
All other module pins associated with strapping on Tegra X2: Ensure any devices connected to module pins associated with Tegra X2
straps do not affect the level of the straps at power-on. Module pins affected are: SLEEP#, UART1_TX, UART0_RTS, RSVD-D8
(UART7_TX)
Pin Selection
Pinmux completed including GPIO usage (direction, initial state, Ext. PU/PD resistors, Deep Sleep state).
SFIO usage matches reference platform where possible.
Each SFIO function assigned to only one pin, even if function selected in Pinmux registers is not used or pin used as GPIO
GPIO usage matches reference platform where possible.
Unused SFIO (Special Function I/O) Interface Pins
Ball Name
USB 2.0
Termination
USB[2:1]+/–
Leave NC any unused pins
*USB 3.0 / PCIe
PEX_[2:0]_TX+/–, USB_SS[1:0]_TX+/–,
PEX_RFU_TX+/–
PEX_[2:0]_RX+/–, USB_SS[1:0]_RX+/–,
PEX_RFU_RX+/–
Leave NC any unused TX lines
Connect to GND any unused RX lines
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
84
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
PEX_[2:0]_REFCLK+/–
Leave NC if not used
SATA
SATA_TX+/–
SATA_RX+/–
Leave NC if not used.
Connect to GND if SATA IF not used
DSI
DSI[3:0]_CK+/–
DSI[3:0]_D[1:0]+/–
Leave NC any Clock lane not used.
Leave NC any unused DSI Data lanes
CSI
CSI[5:0]_CK+/–
CSI[5:0]_D[1:0] +/–
Leave NC any unused CSI Clock lanes
Leave NC any unused CSI Data lanes
eDP/DP
DPx_TX[3:0] +/–
DPx_AUX_CH+/–
DPx_HPD
Leave NC any unused lanes
Leave NC if not used
Leave NC if not used
HDMI
DPx_TX[3:0] +/–
DPx_AUX_CH+/–
DPx_HPD
HDMI_CEC
Leave NC if lanes not used for HDMI or DP
Leave NC if not used
Leave NC if not used
Leave NC if not used
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
85
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
16.0 APPENDIX A: GENERAL LAYOUT GUIDELINES
16.1 Overview
Trace and via characteristics play an important role in signal integrity and pow er distribution on the module. Vias can have a
strong impact on pow er distribution and signal noise, so careful planning must take place to ensure designs meet NVIDIA’s via
requirements. Trace length and impedance determine signal propagation time and reflections, both of w hich can greatly improve
or reduce the performance of the module. Trace and via requirements for each signal type can be found in the corresponding
chapter; this appendix provides general guidelines for via and trace placement.
16.2 Via Guidelines
The number of vias in the path of a given signal, pow er supply line, or ground line can greatly affect the performance of the
trace. Via placement can make differences in current carrying capability, signal integrity (due to reflections and attenuatio n), and
noise generation, all of w hich can impact the overall performance of the trace. The follow ing guidelines provide basic advice for
proper use of vias.
16.2.1 Via Count and Trace Width
As a general rule, each ampere of current requires at least tw o micro-vias.
16.2.2 Via Placement
If vias are not placed carefully, they can severely degrade the robustness of a board’s pow er plane. In standard deigns that don’t
use blind or buried vias, construction of a via entails drilling a hole that cuts into the pow er and ground planes. Thus, inc orrect
via placement affects the amount of copper available to carry current to the pow er balls of the IC.
16.2.3 Via Placement and Power/Ground Corridors
Vias should be placed so that sufficiently w ide pow er corridors are created for good pow er distribution, as show in Figure 47.
Figure 47. Via Placement for Good Power Distribution
Care should also be taken to avoid use of “thermal spokes” (also referred to as “thermal relief”) on pow er and ground vias.
Thermal spokes are not necessary for surface-mount components, and the narrow spoke w idths contribute to increased
inductance. The metal on the inner layers betw een vias may not be flooded w ith copper if sufficient spacing is not provided. The
diminished spacing creates a blockage and forces the current to find another path due to lack of copper, as show n in Figure 48
and Figure 49. This leads to pow er delivery issues and impedance discontinuities w hen traces are routed over these p lane
voids.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
86
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 48. Good Current Flow Resulting from Correct Via Placement
Current Flow
Current Flow
With sufficient via spacing
Correct via implementation
Figure 49. Poor Current Flow Resulting from Incorrect via Placement
Current Flow
Current Flow
With insufficient via spacing
Incorrect via implementation
In general, a dense via population should be avoided and good PCB design principles and analysis should be applied.
16.3 Connecting Vias
To be effective, vias must be connected properly to the signal and pow er planes. Poor via connections make the capacitor and
pow er planes less effective, leading to increased cost due to the need for additional capacitors to achieve equivalent
performance. This not only impacts the BOM (Bill of Material) cost of the design, but it can greatly impact quality and relia bility of
the design.
16.4 Trace Guidelines
Trace length and impedance play a critical role in signal integrity betw een the driver and the receiver on the module. Signal
trace requirements are determined by the driver characteristics, source characteristics, and signal fr equency of the propagating
signal.
16.4.1 Layer Stack-Up
The number of layers required is determined by the number of memory signal layers needed to achieve the desired
performance, and the number of pow er rails required to achieve the optimum pow er delivery/noise floor. For example, highperformance boards require four memory signal routing layers, w ith at least tw o GND planes for reference. This comes to six
layers; add another tw o for pow er, w hich gives eight layers minimum. Reduction from eight to six layers starts the trade-off of
cost versus performance.
Pow er and GND planes usually serve tw o purposes in PCB design: pow er distribution and providing a signal reference for highspeed signals.
Either the pow er or the ground planes can be used for high-speed signal reference; this is particularly common for low -cost
designs w ith a low layer count. When both pow er and GND are used for signal reference, make sure you minimize the reference
plane transition for all high-speed signals. Decoupling caps or transition vias should be added close to the reference plane
transitions.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
87
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
16.4.2 Trace Length
The maximum trace length for a given signal is determined by the maximum allow able propagation delay and impedance for the
signal. Higher frequency signals must be treated as transmission lines (see “Appendix C – Transmission Line Primer”) to
determine proper trace characteristics for a signal.
All signals on the graphics card maintain different trace guidelines; please refer to the corresponding signal chapter in the
Design Guide to determine the guidelines for the signal.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
88
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
17.0 APPENDIX B: STACK-UPS
17.1 Reference Design Stack-Ups
17.1.1 Importance of Stack-Up Definition
Stack-ups define the number and order of Board layers. Stack-up definition is critical to the follow ing design:
▪
▪
▪
Circuit routability
Signal quality
Cost
17.1.2 Impact of Stack-Up Definition on Design
Stack-Up Im pact on Circuit Routability
If there are insufficient layers to maintain proper signal spacing, prevent discontinuities in reference planes, obstruct flo w of
sufficient current, or avoid extra vias, circuit routing can become unnecessarily complex. Layer count must be minimally
appropriate for the circuit.
Stack-Up Im pact on Signal Quality
Both layer count and layer order impact signal integrity. Proper inter-signal spacing must be achievable. Via count for critical
signals must be minimized. Current commensurate w ith the performance of the board must be carried. Critical signals must be
adjacent to major and minor reference planes, and adhere to proximity constraints w ith respect to those planes. The
recommended NVIDIA stack-ups achieve these requirements for the signal speeds supported by the board.
Stack-Up Im pact on Cost
While defining extra layers can facilitate excellent signal integrity, current handling capability and routability, extra layers can
impede the goal of hitting cost targets. The art of stack-up definition is achieving all technical and reliability circuit requirements
in a cost efficient manner. The recommended NVIDIA stack-ups achieve these requirements w ith efficient use of board layers.
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
89
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
18.0 APPENDIX C: TRANSMISSION LINE PRIMER
18.1 Background
NVIDIA maintains strict guidelines for high-frequency PCB transmission lines to ensure optimal signal integrity for data
transmission. This section provides a brief primer into basic board-level transmission line theory.
Characteristics
The most important PCB transmission line characteristics are listed in the follow ing bullets:
▪
Trace w idth/height, PCB height and dielectric constant, and layer stack-up affect the characteristic trace
impedance of a transmission line.
Z0 =˜
▪
L
1/2
C
Signal rise time is proportional to the transmission line impedance and load capacitance.
RiseTime =
˜
▪
Z0 * RTerm
Z0 + RTerm
* CLoad
Real transmission lines (Figure 50) have non-zero resistances that lead to attenuation and distortion, creating
signal integrity issues.
Figure 50. Typical Transmission Line Circuit
Source
ZS
Transmission Line
Z0
Load
ZL
Transmission lines are used to “transmit” the source signal to the load or destination w ith as little signal degradation or reflection
as possible. For this reason it is important to design the high-speed signal transmission line to fall w ithin characteristic guidelines
based on the signal speed and type.
18.2 Physical Transmission Line Types
The tw o primary transmission line types often used for module board designs are:
▪
▪
Microstrip transmission line (Figure 51)
Stripline transmission line (Figure 52)
The follow ing sections describe each type of transmission.
Microstrip Transmission Line
Figure 51. Microstrip Transmission Line
W
H
Dielectric
▪
▪
▪
▪
▪
T
Z0 =
87
Er + 1.414
ln
5.98H
0.8W + T
Z0: Impedance
W: Trace w idth (inches)
T: Trace thickness (inches)
Er: Dielectric constant of substrate
H: Distance betw een signal and reference plane
Stripline Transm ission Line
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
90
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 52. Stripline Transmission Line
W
T
B
H
▪
▪
▪
▪
▪
Z0 =
60
Er
4H
ln
0.67πW 0.8 +
T
W
Z0: Impedance
W: Trace w idth (inches)
T: Trace thickness (inches)
Er: Dielectric constant of substrate
H: Distance betw een signal and reference plane
18.3 Driver Characteristics
Driver characteristics are important to the integrity and maximum speed of the signal. The follow ing points identify key driv er
equations and concepts used to improve signal integrity and transmission speed.
▪
The driver (source) has resistive output impedance Z S, w hich causes only a fraction of the signal voltage to
propagate dow n the transmission line to the receiver (load).
• Transfer function at source:
T1 =
▪
Z0
ZS+ Z0
• Driver strength is inversely proportional to the source impedance, Z S.
ZS also acts as the source termination, w hich helps dampen reflection.
Source reflection coefficient:
R1 =
(ZS– Z0)
(ZS+ Z0)
18.4 Receiver Characteristics
Receiver characteristics are important to the integrity and detectability of the signal. The follow ing points identify key receiver
concepts and equations for optimum signal integrity at the final destination.
▪
▪
The receiver acts as a capacitive load and often has a high load impedance, Z L.
Unterminated transmission lines cause overshoot and reflection at the receiver, w hich can cause data corruption.
Output transfer function at load:
T2 =
-
▪
2 * ZL
ZL + Z0
Load reflection coefficient:
(Z – Z )
R2 = L 0
(ZL + Z0)
Load impedance can be low ered w ith a termination resistor (RTerm) placed at the end of the transmission line.
Reflection is minimized w hen Z L matches Z 0
18.5 Transmission Lines & Reference Planes
Defining an appropriate reference plane is vital to transmission line performance due to crosstalk and EMI issues. The follow ing
points explore appropriate reference plane identification and characteristics for optimal signal integrity:
▪
Transmission line return current (Figure 53)
High-speed return current follow s the path of least inductance.
The low est inductance path for a transmission line is right underneath the transmission line; i(D) is
proportional to:
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
91
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 53. Transmission Line Height
▪
Transmission line return current:
High-speed return current follow s the path of least inductance.
The low est inductance path for a transmission line is the portion of the line closest to the dielectric surface;
i(D) is proportional to
1
D
(1 +
▪
2
H
)
Crosstalk on solid reference plane (Figure 54):
Crosstalk is caused by the mutual inductance of tw o parallel traces.
Crosstalk at the second trace is proportional to
1
(1 +
-
D
H
2
)
The signals need to be properly spaced to minimize crosstalk.
Figure 54. Crosstalk on Reference Plane
▪
▪
Reference plane selection
Solid ground is preferred as reference plane.
Solid pow er can be used as reference plane w ith decoupling capacitors near driver and receiver.
Reference plane cuts and layer changes need to be avoided.
Pow er plane cut example (Figure 55)
Pow er plane cuts w ill cause EMI issues.
Pow er plane cuts also induce crosstalk to adjacent signals.
Figure 55. Example of Power Plane Cuts
▪
When cut is unavoidable:
• Place decoupling capacitors near transition.
• Place transition near source or receiver w hen decoupling capacitors are abundant ( Figure 56).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
92
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Figure 56. Another Example of Power Plane Cuts
▪
When signal changes plane:
Try not to change the reference plane, if possible.
When a reference plane sw itches to different pow er rail, a stitching capacitor is required ( Figure 57).
Figure 57. Switching Reference Planes
-
When the same ground/pow er reference plane changes to a different layer, a stitching via is required ( Figure
58).
Figure 58. Reference Plane Switch Using VIA
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
93
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
19.0 APPENDIX D: DESIGN GUIDELINE GLOSSARY
The Design Guidelines include various terms. The descriptions in the table below are intended to show w hat these terms mean
and how they should be applied to a design.
Table 92 Layout Guideline Tutorial
Trace Delays
Max Breakout Delay
Routing on Component layer: Maximum Trace Delay from module connector pin to point beyond pin array where normal trace spacing/impedance can be met.
Routing passes to layer other than Component layer: Beyond this, normal trace spacing/impedance must be met.
Max Total Trace Delay
Trace from module connector pin to Device pin. This must include routing on the main PCB & any other Flex or secondary PCB. Delay is from Module connector to the
final connector/device.
Intra/Inter Pair Skews
Intra Pair Skew (within pair)
Difference in delay between two traces in differential pair: Shorter routes may require indirect path to equalize delays
Inter Pair Skew (pair to pair)
Difference between two (or possibly more) differential pairs
Impedance/Spacing
Microstrip vs Stripline
Microstrip: Traces next to single ref. plane. Stripline: Traces between two ref planes
Trace Impedance
Impedance of trace determined by width & height of trace, distance from ref. plane & dielectric constant of PCB material. For differential traces, space between pair
of traces is also a factor
Board trace spacing / Spacing to other nets
Minimum distance between two traces. Usually specified in terms of dielectric height which is distance from trace to reference layers.
Pair to pair spacing
Spacing between differential traces
Breakout spacing
Possible exception to board trace spacing where different spacing rules are allowed under module connector pin in order to escape from the pin array. Outside device
boundary, normal spacing rules apply
Reference Return
Ground Reference Return Via & Via proximity (signal to reference)
Signals changing layers & reference GND planes need similar return current path
Accomplished by adding via, tying both GND layers together
Via proximity (sig to ref) is distance between signal & reference return vias
GND reference via for Differential Pair
Where a differential pair changes GND reference layers, return via should be placed close to & between signal vi as (example to right)
Signal to return via ratio
Number of Ground Return vias per Signal vias. For critical IFs, ratio is usually 1:1. For less critical IFs, several trace vias can share fewer return vias (i.e. 3:2 – 3 trace
vias & 2 return vias).
Slots in Ground Reference Layer
When traces cross slots in adjacent power or ground plane
Return current has longer path around slot
Longer slots result in larger loop areas
Avoid slots in GND planes or do not route across them
Routing over Split Power Layer Reference Layers
When traces cross different power areas on power plane
-
-
Return current must find longer path - usually a distant bypass cap
-
Placing one cap across two PWR areas near where traces cross area boundaries provides high -frequency path for return current
If possible, route traces w/solid plane (GND or PWR) or keep routes across single area
If traces must cross two or more power areas, use stitching capacitors
Cap value typically 0.1uF & should ideally be within 0.1" of crossing
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
94
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
20.0 APPENDIX E: JETSON TX2/TX2I PIN DESCRIPTIONS
Table 93. Jetson TX2/TX2i Connector (8x50) Pin Descriptions
Pin # Module Pin Name
Tegra Signal
Usage/Description
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VDD_IN
VDD_IN
GND
GND
RSVD
I2C_PM_CLK
CHARGING#
GPIO14_AP_WAKE_MDM
GPIO15_AP2MDM_READY
GPIO16_MDM_WAKE_AP
−
−
−
GEN8_I2C_SCL
(PMIC GPIO5)
UFS0_RST
UFS0_REF_CLK
GPIO_MDM2
A11
JTAG_GP1
NVJTAG_SEL
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
JTAG_TMS
JTAG_TDO
JTAG_RTCK
UART2_CTS#
UART2_RTS#
USB0_EN_OC#
USB1_EN_OC#
RSVD
I2C_GP1_DAT
I2C_GP1_CLK
GPIO_EXP1_INT
GPIO_EXP0_INT
LCD1_BKLT_PWM
LCD_TE
GSYNC_HSYNC
GSYNC_VSYNC
GND
SDIO_RST#
JTAG_TMS
JTAG_TD0
−
UART2_CTS
UART2_RTS
USB_VBUS_EN0
USB_VBUS_EN1
−
GEN1_I2C_SDA
GEN1_I2C_SCL
GPIO_MDM7
GPIO_MDM1
GPIO_DIS5
GPIO_DIS1
GPIO_DIS4
GPIO_DIS2
−
GPIO_WAN3
Main power – Supplies PMIC & external
supplies
GND
GND
Not used
PM I2C Clock
Charger Interrupt
AP (Tegra) Wake Modem or GPIO
AP (Tegra) to Modem Ready or GPIO
Modem Wake AP (Tegra) or GPIO
JTAG General Purpose 1. Pulled low on
module for normal operation & pulled
high by test device for Boundary Scan
test mode.
JTAG Test Mode Select
JTAG Test Data Out
JTAG Return Clock
UART 2 Clear to Send
UART 2 Request to Send
USB VBUS Enable/Overcurrent 0
USB VBUS Enable/Overcurrent 1
Not used
General I2C 1 Data
General I2C 1 Clock
GPIO Expander 1 Interrupt or GPIO
GPIO expander 0 Interrupt or GPIO
Display Backlight PWM 1
Display Tearing Effect
GSYNC Horizontal Sync
GSYNC Vertical Sync
GND
Secondary WLAN Enable
A32
SDIO_D3
SDIO_D2
SDIO_D1
SDMMC3_DAT3
SDMMC3_DAT2
SDMMC3_DAT1
SDIO Data 3
SDIO Data 2
SDIO Data 1
A33
A34
DP1_HPD
DP1_AUX_CH–
DP_AUX_CH1_HPD
DP_AUX_CH1_N
Display Port 1 Hot Plug Detect
Display Port 1 Aux– or HDMI DDC SDA
A35
DP1_AUX_CH+
DP_AUX_CH1_P
Display Port 1 Aux+ or HDMI DDC SCL
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
USB0_OTG_ID
GND
USB1_D+
USB1_D–
GND
PEX2_REFCLK+
PEX2_REFCLK–
GND
PEX0_REFCLK+
PEX0_REFCLK–
(PMIC GPIO0)
−
USB1_DP
USB1_DN
−
PEX_CLK2P
PEX_CLK2N
−
PEX_CLK1P
PEX_CLK1N
A46
RESET_OUT#
SYS_RESET_N
USB 0 ID / VBUS EN
GND
USB 2.0, Port 1 Data+
USB 2.0, Port 1 Data–
GND
PCIe 2 Reference Clock+ (PCIe IF #1)
PCIe 2 Reference Clock– (PCIe IF #1)
GND
PCIe 0 Reference Clock+ (PCIe IF #0)
PCIe 0 Reference Clock – (PCIe IF #0)
Reset Out. Reset from PMIC (through
diodes) to Tegra & eMMC reset pins.
Driven from carrier board to force reset
of Tegra & eMMC (not PMIC). An
external 100kΩ pull-up to 1.8V near
A31
−
Usage on the Carrier
Board
Main DC input
GND
GND
−
I2C (General)
System
M.2 Key E
JTAG
JTAG Header & Debug
Connector
M.2 Key E
USB 2.0 Micro AB
USB 3.0 Type A
−
I2C (General)
GPIO Expander
Display Connector
GND
M.2 Key E
SDIO
Direction
−
−
−
Bidir
Input
Output
Output
Input
5.5V-19.6V (TX2)
9.0V-19.0V (TX2i)
GND
GND
−
Open Drain – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Input
CMOS – 1.8V
Input
Output
Input
Input
Output
Bidir
Bidir
−
Bidir
Bidir
Input
Input
Output
Input
Output
Output
−
Output
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Open Drain – 3.3V
Open Drain – 3.3V
−
Open Drain – 3.3V
Open Drain – 3.3V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
GND
CMOS – 1.8V
Bidir
Bidir
Bidir
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Input
Bidir
CMOS – 1.8V
AC-Coupled on Carrier
Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C)
Analog
GND
Input
HDMI Type A Conn.
Bidir
USB 2.0 Micro AB
GND
USB 3.0 Type A
GND
Unassigned
GND
PCIe x4 Connector
System
Pin Type
Input
−
Bidir
Bidir
−
Output
Output
−
Output
Output
Bidir
USB PHY
GND
PCIe PHY
GND
PCIe PHY
CMOS – 1.8V
Tegra (module pin side) & external
10kΩ pull-up to 1.8V on the other
side of a diode (PMIC side).
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
95
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
A47
RESET_IN#
A48
CARRIER_PWR_ON
A49
CHARGER_PRSNT#
(PMIC ACOK)
A50
VDD_RTC
(PMIC BBATT)
B1
B2
B3
B4
B5
B6
VDD_IN
VDD_IN
GND
GND
RSVD
I2C_PM_DAT
−
−
−
GEN8_I2C_SDA
B7
CARRIER_STBY#
SOC_PWR_REQ
B8
VIN_PWR_BAD#
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
GPIO17_MDM2AP_READY
GPIO18_MDM_COLDBOOT
JTAG_TCK
JTAG_TDI
JTAG_GP0
GND
UART2_RX
UART2_TX
FAN_TACH
RSVD
GPIO11_AP_WAKE_BT
GPIO10_WIFI_WAKE_AP
GPIO12_BT_EN
GPIO13_BT_WAKE_AP
GPIO7_TOUCH_RST
TOUCH_CLK
GPIO6_TOUCH_INT
LCD_VDD_EN
LCD0_BKLT_PWM
LCD_BKLT_EN
SDIO_CMD
SDIO_CLK
GND
(PMIC NRST_IO)
−
−
−
GPIO_PQ7
GPIO_PQ6
JTAG_TCK
JTAG_TDI
JTAG_TRST_N
−
UART2_RX
UART2_TX
UART5_TX
−
GPIO_PQ5
GPIO_WAN4
MCU_PWR_REQ
GPIO_WAN2
SAFE_STATE
TOUCH_CLK
CAN_GPIO7
GPIO_EDP0
GPIO_DIS0
GPIO_DIS3
SDMMC3_CMD
SDMMC3_CLK
−
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
Bidir
Open Drain, 1.8V
Output
Open-Collector – 3.3V
Input
MBATT level – 5.0V (see
note 3)
Bidir
1.65V-5.5V
Main DC input
Input
5.5V-19.6V (TX2)
9.0V-19.0V (TX2i)
GND
GND
−
−
−
Bidir
GND
GND
−
Open Drain – 1.8V
Output
CMOS – 1.8V
Input
CMOS – 5.0V
Input
Input
Input
Input
Input
−
Input
Output
Input
−
Output
Input
Output
Input
Output
Output
Input
Output
Output
Output
Bidir
Output
−
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
GND
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
−
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
GND
Reset In. System Reset driven from
PMIC to carrier board for devices
requiring full system reset. Also driven
from carrier board to initiate full system
reset (i.e. RESET button). A pull-up is
present on module.
Carrier Power On. Used as part of the
power up sequence. The module asserts
this signal when it is safe for the carrier
board to power up. A 10kΩ pull-up to
VDD_3V3_SYS is present on the module.
Charger Present. Connected on module
to PMIC ACOK through FET & 4.7kΩ
resistor. PMIC ACOK has 100kΩ pull-up
internally to MBATT (VDD_5V0_SYS).
Can optionally be used to support autopower-on where the module platform
will power-on when the main power
source is connected instead of waiting
for a power button press.
Real-Time-Clock. Optionally used to
provide back-up power for RTC.
Connects to Lithium Cell or super
Battery Back-up using
capacitor on Carrier Board. PMIC is
Super-capacitor
supply when charging cap or coin cell.
Super cap or coin cell is source when
system is disconnected from power.
Main power – Supplies PMIC & external
supplies
GND
GND
Not used
PM I2C Data
Carrier Board Standby: The module
drives this signal low when it is in the
standby power state.
VDD_IN Power Bad. Carrier board
indication to the module that the
VDD_IN power is not valid. Carrier board
should de-assert this (drive high) only
when VDD_IN has reached its required
voltage level and is stable. This prevents
Tegra from powering up until the
VDD_IN power is stable.
Modem to AP (Tegra) Ready or GPIO
Modem Coldboot or GPIO
JTAG Test Clock
JTAG Test Data In
JTAG General Purpose 0 (Test Reset)
GND
UART 2 Receive
UART 2 Transmit
Fan Tachometer
Not used
AP (Tegra) Wake Bluetooth or GPIO
WLAN 2 Wake AP (Tegra) or GPIO
BT 2 Enable or GPIO
BT 2 Wake AP (Tegra) or GPIO
Touch Reset or GPIO
Touch Clock
Touch Interrupt or GPIO
Display VDD Enable
Display Backlight PWM 0
Display Backlight Enable
SDIO Command
SDIO Clock
GND
−
I2C (General)
System
M.2 Key E
JTAG Header & Debug
Connector
GND
M.2 Key E
Fan
−
Display Connector
M.2 Key E
Display Connector
SDIO
GND
96
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
B32
B33
B34
SDIO_D0
HDMI_CEC
DP0_AUX_CH–
SDMMC3_DAT0
HDMI_CEC
DP_AUX_CH0_N
SDIO Data 0
HDMI CEC
Display Port 0 Aux– or HDMI DDC SDA
B35
DP0_AUX_CH+
DP_AUX_CH0_P
Display Port 0 Aux+ or HDMI DDC SCL
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
DP0_HPD
USB0_VBUS_DET
GND
USB0_D+
USB0_D–
GND
USB2_D+
USB2_D–
GND
PEX1_REFCLK+
PEX1_REFCLK–
GND
SYS_WAKE#
DP_AUX_CH0_HPD
UART5_CTS
−
USB0_DP
USB0_DN
−
USB2_DP
USB2_DN
−
PEX_CLK3P
PEX_CLK3N
−
POWER_ON
B49
MOD_PWR_CFG_ID
B50
POWER_BTN#
Display Port 0 Hot Plug Detect
USB 0 VBUS Detect
GND
USB 2.0 Port 0 Data+
USB 2.0 Port 0 Data–
GND
USB 2.0, Port 2 Data+
USB 2.0, Port 2 Data–
GND
PCIe 1 Reference Clock+ (PCIe IF #2)
PCIe 1 Reference Clock– (PCIe IF #2)
GND
Power button & SC7 wake interrupt
Module power configuration
identification. Tied to GND on Jetson
TX2i. Floating on Jetson TX2.
Determines the power-on mechanism
used to support both Jetson TX2 & TX2i.
Power Button. Used to initiate a system
power-on. Connected to PMIC EN0
which has internal 10KΩ Pull-up to
VDD_5V0_SYS. Also connected to Tegra
POWER_ON pin through Diode with
100kΩ pull-up to VDD_1V8_AP near
Tegra.
C1
C2
C3
C4
C5
C6
C7
VDD_IN
VDD_IN
GND
GND
RSVD
I2C_CAM_CLK
BATLOW#
−
−
−
CAM_I2C_SCL
(PMIC_GPIO6)
C8
BATT_OC
BATT_OC
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
WDT_TIME_OUT#
I2C_GP2_DAT
I2C_GP2_CLK
I2C_GP3_CLK
I2C_GP3_DAT
I2S1_SDIN
I2S1_CLK
FAN_PWM
CAN1_STBY
CAN1_TX
CAN1_ERR
CAN_WAKE
GND
CSI5_D0–
CSI5_D0+
GND
CSI3_D0–
CSI3_D0+
GND
CSI1_D0–
CSI1_D0+
GND
DSI3_D0+
DSI3_D0–
GPIO_SEN7
GEN7_I2C_SDA
GEN7_I2C_SCL
GEN9_I2C_SCL
GEN9_I2C_SDA
DAP2_DIN
DAP2_SCLK
GPIO_SEN6
CAN_GPIO6
CAN1_DOUT
CAN_GPIO3
CAN_GPIO4
−
CSI_F_D0_N
CSI_F_D0_P
−
CSI_D_D0_N
CSI_D_D0_P
−
CSI_B_D0_N
CSI_B_D0_P
−
DSI_D_D0_P
DSI_D_D0_N
−
POWER_ON / (PMIC
EN0)
−
−
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Main power – Supplies PMIC & external
supplies
GND
GND
Not used
Camera I2C Clock
Battery Low (PMIC GPIO)
Battery Over-current (& Thermal)
warning
Watchdog Timeout
General I2C 2 Data
General I2C 2 Clock
General I2C 3 Clock
General I2C 3 Data
I2S Audio Port 1 Data In
I2S Audio Port 1 Clock
Fan PWM
CAN 1 Standby
CAN 1 Transmit
CAN 1 Error
CAN Wake
GND
Camera, CSI 5 Data 0–
Camera, CSI 5 Data 0+
GND
Camera, CSI 3 Data 0–
Camera, CSI 3 Data 0+
GND
Camera, CSI 1 Data 0–
Camera, CSI 1 Data 0+
GND
Display, DSI 3 Data 0+
Display, DSI 3 Data 0–
Usage on the Carrier
Board
SDIO
HDMI Type A Conn.
Display Connector
USB 2.0 Micro AB
GND
USB 2.0 Micro AB
GND
M.2 Key E
GND
M.2 Key E
GND
Power/SC7 wake
Module power
configuration ID
Direction
Pin Type
Bidir
Bidir
Bidir
CMOS – 1.8V
Open Drain, 3.3V
AC-Coupled on Carrier
Board (eDP/DP) or OpenDrain, 1.8V (3.3V tolerant DDC/I2C)
CMOS – 1.8V
USB VBUS, 5V
GND
Bidir
Input
Input
−
Bidir
Bidir
−
Bidir
Bidir
−
Output
Output
−
Input
USB PHY
GND
USB PHY
GND
PCIe PHY
GND
CMOS – 1.8V
Output
VDD_IN level
System
Input
CMOS – 5.0V (see note 3)
Main DC input
Input
5.5V-19.6V (TX2)
9.0V-19.0V (TX2i)
GND
GND
−
−
−
Bidir
Input
GND
GND
−
Open Drain – 1.8V
CMOS – 1.8V
Bidir
CMOS – 1.8V
Input
Bidir
Bidir
Bidir
Bidir
Input
Bidir
Output
Output
Output
Input
Input
−
Input
Input
−
Input
Input
−
Input
Input
−
Output
Output
CMOS – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
Open Drain – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
GND
−
Camera Connector
System
I2C (General)
GPIO Expansion
Header
Fan
GPIO Expansion
Header
GND
Camera Connector
GND
Camera Connector
GND
Camera Connector
GND
Display Connector
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
97
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
C33
C34
C35
C36
C37
C38
C39
GND
DSI1_D0+
DSI1_D0–
GND
DP1_TX1–
DP1_TX1+
GND
−
DSI_B_D0_P
DSI_B_D0_N
−
HDMI_DP1_TXDN1
HDMI_DP1_TXDP1
−
C40
PEX2_TX+
PEX_TX3P
GND
Display, DSI 1 Data 0+
Display, DSI 1 Data 0–
GND
DisplayPort 1 Lane 1– or HDMI Lane 1–
DisplayPort 1 Lane 1+ or HDMI Lane 1+
GND
PCIe 2 Transmit+ (PCIe IF #0 Lane 2 or
PCIe IF #1 Lane 0)
PCIe 2 Transmit– (PCIe IF #0 Lane 2 or
PCIe IF #1 Lane 0)
GND
USB SS 0 Transmit+ (USB 3.0 Port #0
muxed w/PCIe #2 Lane 0)
USB SS 0 Transmit– (USB 3.0 Port #0
muxed w/PCIe #2 Lane 0)
GND
PCIE 2 Clock Request (PCIe IF #1)
PCIE 1 Clock Request (mux option - PCIe
IF #2)
PCIE 0 Clock Request (PCIe IF #0)
PCIe 0 Reset (PCIe IF #0)
Not used
Not used
Not used
Not used
Not used
UART 7 Receive
Camera I2C Data
Camera Flash Enable or GPIO
UART 7 Transmit
UART 1 Transmit
UART 1 Receive
Not used
Not used
I2S Audio Port 1 Left/Right Clock
I2S Audio Port 1 Data Out
General I2C 0 Data
Digital Mic Input Data
CAN 1 Receive
CAN 0 Receive
CAN 0 Transmit
GND
Camera, CSI 5 Clock–
Camera, CSI 5 Clock+
GND
Camera, CSI 3 Clock–
Camera, CSI 3 Clock+
GND
Camera, CSI 1 Clock–
Camera, CSI 1 Clock+
GND
Display DSI 3 Clock+
Display DSI 3 Clock–
GND
Display DSI 1 Clock+
Display DSI 1 Clock–
GND
DisplayPort 1 Lane 2– or HDMI Lane 0–
DisplayPort 1 Lane 2+ or HDMI Lane 0+
GND
PCIe RFU Transmit+ (PCIe IF #0 Lane 3 or
USB 3.0 Port #1)
C41
PEX2_TX–
C42
GND
C43
USB_SS0_TX+
PEX_TX3N
−
PEX_TX0P
C44
USB_SS0_TX–
PEX_TX0N
C45
C46
GND
PEX2_CLKREQ#
−
PEX_L1_CLKREQ_N
C47
PEX1_CLKREQ#
PEX_L2_CLKREQ_N
C48
C49
C50
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
PEX0_CLKREQ#
PEX0_RST#
RSVD
RSVD
RSVD
RSVD
RSVD
UART7_RX
I2C_CAM_DAT
GPIO5_CAM_FLASH_EN
UART7_TX
UART1_TX
UART1_RX
RSVD
RSVD
I2S1_LRCLK
I2S1_SDOUT
I2C_GP0_DAT
AO_DMIC_IN_DAT
CAN1_RX
CAN0_RX
CAN0_TX
GND
CSI5_CLK–
CSI5_CLK+
GND
CSI3_CLK–
CSI3_CLK+
GND
CSI1_CLK–
CSI1_CLK+
GND
DSI3_CLK+
DSI3_CLK–
GND
DSI1_CLK+
DSI1_CLK–
GND
DP1_TX2–
DP1_TX2+
GND
PEX_L0_CLKREQ_N
PEX_L0_RST_N
−
−
−
−
−
UART7_RX
CAM_I2C_SDA
UART5_RTS_N
UART7_TX
UART3_TX
UART3_RX
−
−
DAP2_FS
DAP2_DOUT
GPIO_SEN9
CAN_GPIO0
CAN1_DIN
CAN0_DIN
CAN0_DOUT
−
CSI_F_CLK_N
CSI_F_CLK_P
−
CSI_D_CLK_N
CSI_D_CLK_P
−
CSI_B_CLK_N
CSI_B_CLK_P
−
DSI_D_CLK_P
DSI_D_CLK_N
−
DSI_B_CLK_P
DSI_B_CLK_N
−
HDMI_DP1_TXDN0
HDMI_DP1_TXDP0
−
D39
PEX_RFU_TX+
PEX_TX1P
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage on the Carrier
Board
GND
Display Connector
GND
HDMI Type A Conn.
GND
Direction
Pin Type
−
Output
Output
−
Output
Output
−
GND
Output
PCIe x4 Connector
Output
GND
−
Output
USB 3.0 Type A
Output
MIPI D-PHY
GND
AC-Coupled on carrier
board
GND
PCIe PHY, AC-Coupled on
carrier board
GND
USB SS PHY, AC-Coupled on
carrier board
GND
Unassigned
−
Bidir
GND
M.2 Key E
Bidir
Open Drain 3.3V, Pull-up on
the module
GND
Bidir
Output
−
−
−
−
−
Input
Bidir
Output
Output
Output
Input
−
−
Bidir
Bidir
Bidir
Input
Input
Input
Output
−
Input
Input
−
Input
Input
−
Input
Input
−
Output
Output
−
Output
Output
−
Output
Output
−
PCIe x4 Connector
Output
PCIe x4 Connector
−
−
−
−
−
Not Assigned
Camera Connector
Not Assigned
Serial Port Header
−
−
GPIO Expansion
Header
I2C (General)
GPIO Expansion
Header
GND
Camera Connector
GND
Camera Connector
GND
Camera Connector
GND
Display Connector
GND
Display Connector
GND
HDMI Type A Conn.
−
−
−
−
−
CMOS – 1.8V
Open Drain – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
−
−
CMOS – 1.8V
CMOS – 1.8V
Open Drain – 1.8V
CMOS – 1.8V
CMOS 3.3V
CMOS 3.3V
CMOS 3.3V
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
AC-Coupled on carrier
board
GND
PCIe PHY, AC-Coupled on
carrier board
98
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
D43
USB_SS1_TX–
PEX_TX2N
D44
D45
D46
GND
SATA_TX+
SATA_TX–
PEX_TX5P
PEX_TX5N
D47
SATA_DEV_SLP
PEX_L2_CLKREQ_N
D48
D49
D50
E1
PEX_WAKE#
PEX2_RST#
RSVD
FORCE_RECOV#
PEX_WAKE_N
PEX_L1_RST_N
−
GPIO_SW1
E2
SLEEP#
GPIO_SW2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
SPI0_CLK
SPI0_MISO
I2S3_SDIN
I2S3_CLK
CAM2_MCLK
CAM_VSYNC
UART1_RTS#
UART1_CTS#
RSVD
RSVD
RSVD
SPI1_CS0#
I2C_GP0_CLK
AO_DMIC_IN_CLK
RSVD
GPIO_SEN1
GPIO_SEN2
DAP4_DIN
DAP4_SCLK
GPIO_CAM2
QSPI_IO1
UART3_RTS
UART3_CTS
−
−
−
GPIO_CAM7
GPIO_SEN8
CAN_GPIO1
−
PCIe RFU Transmit – (PCIe IF #0 Lane 3
or USB 3.0 Port #1)
GND
USB SS 1 Transmit+ (USB 3.0 Port #2 or
PCIe IF #0 Lane 1)
USB SS 1 Transmit– (USB 3.0 Port #2 or
PCIe #0 Lane 1)
GND
SATA Transmit+
SATA Transmit–
SATA Device Sleep or PEX1_CLKREQ#
(PCIe IF #2) depending on Mux setting
PCIe Wake
PCIe 2 Reset (PCIe IF #1)
Not used
Force Recovery strap pin
Sleep Request to the module from the
carrier board. An internal Tegra pull-up
is present on the signal.
SPI 0 Clock
SPI 0 Master In / Slave Out
I2S Audio Port 3 Data In
I2S Audio Port 3 Clock
Camera 2 Master Clock
Camera Vertical Sync
UART 1 Request to Send
UART 1 Clear to Send
Not used
Not used
Not used
SPI 1 Chip Select 0
General I2C 0 Clock
Digital Mic Input Clock
Not used
E18
CAN0_ERR
CAN_GPIO5
CAN 0 Error
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
GND
CSI5_D1–
CSI5_D1+
GND
CSI3_D1–
CSI3_D1+
GND
CSI1_D1–
CSI1_D1+
GND
DSI3_D1+
DSI3_D1–
GND
DSI1_D1+
DSI1_D1–
GND
DP1_TX3–
DP1_TX3+
GND
DP1_TX0–
DP1_TX0+
GND
−
CSI_F_D1_N
CSI_F_D1_P
−
CSI_D_D1_N
CSI_D_D1_P
−
CSI_B_D1_N
CSI_B_D1_P
−
DSI_D_D1_P
DSI_D_D1_N
−
DSI_B_D1_P
DSI_B_D1_N
−
HDMI_DP1_TXDN3
HDMI_DP1_TXDP3
−
HDMI_DP1_TXDN2
HDMI_DP1_TXDP2
−
E41
PEX1_TX+
PEX_TX0P
E42
PEX1_TX–
PEX_TX0N
E43
GND
GND
Camera, CSI 5 Data 1–
Camera, CSI 5 Data 1+
GND
Camera, CSI 3 Data 1–
Camera, CSI 3 Data 1+
GND
Camera, CSI 1 Data 1–
Camera, CSI 1 Data 1+
GND
Display, DSI 3 Data 1+
Display, DSI 3 Data 1–
GND
Display, DSI 1 Data 1+
Display, DSI 1 Data 1–
GND
DisplayPort 1 Lane 3– or HDMI Clk Lane–
DisplayPort 1 Lane 3+ or HDMI Clk Lane+
GND
DisplayPort 1 Lane 0– or HDMI Lane 2–
DisplayPort 1 Lane 0+ or HDMI Lane 2+
GND
PCIe 1 Transmit+ (PCIe #2 Lane 0 muxed
w/USB 3.0 Port #0)
PCIe 1 Transmit– (PCIe #2 Lane 0 muxed
w/USB 3.0 Port #0)
GND
D40
PEX_RFU_TX–
D41
GND
D42
USB_SS1_TX+
PEX_TX1N
−
PEX_TX2P
−
−
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Usage on the Carrier
Board
Direction
Pin Type
Output
GND
−
Output
PCIe x4 Connector
Output
GND
SATA Connector
−
Output
Output
GND
USB SS PHY, AC-Coupled on
carrier board
GND
SATA PHY, AC-Coupled on
carrier board
Input
Open Drain 3.3V, Pull-up on
the module
PCIe x4 conn & M.2
Unassigned
−
System
Input
Output
−
Input
Open Drain 3.3V, Pull-up on
the module
−
CMOS – 1.8V
Sleep (VOL DOWN)
button
Input
CMOS – 1.8V (see note 3)
Bidir
Bidir
Input
Bidir
Output
Output
Output
Input
−
−
−
Bidir
Bidir
Output
−
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
−
−
−
CMOS – 1.8V
Open Drain – 1.8V
CMOS – 1.8V
−
Input
CMOS 3.3V
−
Input
Input
−
Input
Input
−
Input
Input
−
Output
Output
−
Output
Output
−
Output
Output
−
Output
Output
−
GND
Display Connector
Camera Connector
Serial Port Header
−
−
−
Expansion Header
I2C (General)
Expansion Header
−
GPIO Expansion
Header
GND
Camera Connector
GND
Camera Connector
GND
Camera Connector
GND
Display Connector
GND
Display Connector
GND
HDMI Type A Conn.
GND
HDMI Type A Conn.
GND
USB 3.0 Type A
(Default) or M.2 Key E
GND
Output
Output
−
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
AC-Coupled on carrier
board
GND
AC-Coupled on carrier
board
GND
PCIe PHY, AC-Coupled on
carrier board
GND
99
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
E44
E45
E46
E47
E48
E49
PEX_TX4P
PEX_TX4N
PCIe 0 Transmit+ (PCIe IF #0 Lane 0)
PCIe 0 Transmit– (PCIe IF #0 Lane 0)
GND
GbE RJ45 connector Link ACT (LED0)
GbE Transformer Data 0+
GbE Transformer Data 0–
PEX0_TX+
PEX0_TX–
GND
GBE_LINK_ACT#
GBE_MDI0+
GBE_MDI0–
−
−
−
−
Usage on the Carrier
Board
PCIe x4 Connector
GND
LAN
Direction
Pin Type
Output
Output
−
Output
Bidir
Bidir
PCIe PHY, AC-Coupled on
carrier board
E50
PEX1_RST#
PEX_L2_RST_N
PCIe 1 Reset (PCIe IF #2)
M.2 Key E
Output
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
AUDIO_MCLK
GPIO19_AUD_RST
SPI0_CS0#
SPI0_MOSI
I2S3_LRCLK
I2S3_SDOUT
GPIO1_CAM1_PWR#
CAM1_MCLK
CAM0_MCLK
GND
RSVD
RSVD
SPI1_MOSI
SPI1_MISO
GND
SPI2_CS1#
SDCARD_CD#
SDCARD_D3
SDCARD_D2
SDCARD_WP
GND
CSI4_D0–
CSI4_D0+
GND
CSI2_D0–
CSI2_D0+
GND
CSI0_D0–
CSI0_D0+
GND
DSI2_D0+
DSI2_D0–
GND
DSI0_D0+
DSI0_D0–
GND
DP0_TX1–
DP0_TX1+
GND
AUD_MCLK
GPIO_AUD1
GPIO_SEN4
GPIO_SEN3
DAP4_FS
DAP4_DOUT
GPIO_CAM3
EXTPERIPH2_CLK
EXTPERIPH1_CLK
−
−
−
GPIO_CAM6
GPIO_CAM5
−
GPIO_MDM4
GPIO_EDP2
SDMMC1_DAT3
SDMMC1_DAT2
GPIO_EDP1
−
CSI_E_D0_N
CSI_E_D0_P
−
CSI_C_D0_N
CSI_C_D0_P
−
CSI_A_D0_N
CSI_A_D0_P
−
DSI_C_D0_P
DSI_C_D0_N
−
DSI_A_D0_P
DSI_A_D0_N
−
HDMI_DP0_TXDN1
HDMI_DP0_TXDP1
−
Expansion Header
Output
Output
Bidir
Bidir
Bidir
Bidir
Output
Output
Output
−
−
−
Bidir
Bidir
−
Bidir
Input
Bidir
Bidir
Input
−
Input
Input
−
Input
Input
−
Input
Input
−
Output
Output
−
Output
Output
−
Output
Output
−
F40
PEX2_RX+
PEX_RX3P
Audio Codec Master Clock
Audio Codec Reset or GPIO
SPI 0 Chip Select 0
SPI 0 Master Out / Slave In
I2S Audio Port 3 Left/Right Clock
I2S Audio Port 3 Data Out
Camera 1 Powerdown or GPIO
Camera 1 Reference Clock
Camera 0 Reference Clock
GND
Not used
Not used
SPI 1 Master Out / Slave In
SPI 1 Master In / Slave Out
GND
SPI 2 Chip Select 1
SD Card Card Detect
SD Card (or SDIO) Data 3
SD Card (or SDIO) Data 2
SD Card Write Protect
GND
Camera, CSI 4 Data 0–
Camera, CSI 4 Data 0+
GND
Camera, CSI 2 Data 0–
Camera, CSI 2 Data 0+
GND
Camera, CSI 0 Data 0–
Camera, CSI 0 Data 0+
GND
Display, DSI 2 Data 0+
Display, DSI 2 Data 0–
GND
Display, DSI 0 Data 0+
Display, DSI 0 Data 0–
GND
DisplayPort 0 Lane 1– or HDMI Lane 1–
DisplayPort 0 Lane 1+or HDMI Lane 1+
GND
PCIe 2 Receive+ (PCIe IF #0 Lane 2 or
PCIe IF #1 Lane 0)
PCIe 2 Receive– (PCIe IF #0 Lane 2 or
PCIe IF #1 Lane 0)
GND
USB SS 0 Receive+ (USB 3.0 Port #0
muxed w/PCIe #2 Lane 0)
USB SS 0 Receive– (USB 3.0 Port #0
muxed w/PCIe #2 Lane 0)
GND
GbE RJ45 connector Link 1000 (LED2)
GbE Transformer Data 1+
GbE Transformer Data 1–
GND
GbE RJ45 connector Link 100 (LED1)
I2S Audio Port 0 Data In
F41
PEX2_RX–
F42
GND
F43
USB_SS0_RX+
F44
USB_SS0_RX–
F45
F46
F47
F48
F49
F50
G1
GND
GBE_LINK1000#
GBE_MDI1+
GBE_MDI1–
GND
GBE_LINK100#
I2S0_SDIN
PEX_RX3N
−
PEX_RX0P
PEX_RX0N
−
−
−
−
−
−
DAP1_DIN
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
Display Connector
Camera Connector
GND
−
−
Expansion Header
GND
Display/Camera Conns.
SD Card
GND
Camera Connector
GND
Camera Connector
GND
Camera Connector
GND
Display Connector
GND
Display Connector
GND
Display Connector
GND
Input
PCIe x4 Connector
Input
GND
−
Input
USB 3.0 Type A
Input
GND
LAN
GND
LAN
Expansion Header
−
Output
Bidir
Bidir
−
Output
Input
GND
CMOS – 3.3V tolerant
MDI
Open Drain 3.3V, Pull-up on
the module
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
GND
−
−
CMOS – 1.8V
CMOS – 1.8V
GND
CMOS – 1.8V
CMOS – 1.8V
CMOS – 3.3/1.8V
CMOS – 3.3/1.8V
CMOS – 1.8V
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
AC-Coupled on carrier
board
GND
PCIe PHY, AC-Coupled on
carrier board
GND
USB SS PHY, AC-Coupled
(off the module)
GND
CMOS – 3.3V Tolerant
MDI
GND
CMOS – 3.3V Tolerant
CMOS – 1.8V
100
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Pin # Module Pin Name
Tegra Signal
Usage/Description
G2
G3
I2S0_CLK
GND
DAP1_SCLK
−
I2S Audio Port 0 Clock
GND
G4
DSPK_OUT_CLK
GPIO_AUD3
Digital Speaker Output Clock
G5
G6
G7
G8
I2S2_CLK
I2S2_SDIN
GPIO4_CAM_STROBE
GPIO0_CAM0_PWR#
I2S Audio Port 2 Clock
I2S Audio Port 2 Data In
Camera Strobe or GPIO
Camera 0 Powerdown or GPIO
G9
UART3_CTS#
Direction
Pin Type
Bidir
−
CMOS – 1.8V
GND
Output
CMOS – 1.8V
Bidir
Input
Output
Output
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Input
CMOS – 1.8V
UART 3 Request to Send
Output
CMOS – 1.8V
UART 0 Request to Send
UART 0 Receive
SPI 1 Clock
Output
Input
Bidir
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
Input
CMOS – 1.8V
Bidir
Bidir
−
Output
Bidir
−
Input
Input
−
Input
Input
−
Input
Input
−
Output
Output
−
Output
Output
−
Output
Output
−
CMOS – 1.8V
CMOS – 1.8V
GND
CMOS – 3.3/1.8V
CMOS – 3.3/1.8V
GND
G10
UART3_RTS#
G11
G12
G13
UART0_RTS#
UART0_RX
SPI1_CLK
DMIC2_DAT
DMIC1_DAT
GPIO_SEN5
QSPI_SCK
UART4_CTS_N (via
mux)
UART4_RTS_N (via
mux)
UART1_RTS
UART1_RX
GPIO_CAM4
G14
GPIO9_MOTION_INT
CAN_GPIO2
Motion Interrupt or GPIO
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
SPI2_MOSI
SPI2_CS0#
GND
SDCARD_CLK
SDCARD_CMD
GND
CSI4_CLK–
CSI4_CLK+
GND
CSI2_CLK–
CSI2_CLK+
GND
CSI0_CLK–
CSI0_CLK+
GND
DSI2_CLK+
DSI2_CLK–
GND
DSI0_CLK+
DSI0_CLK–
GND
DP0_TX2–
DP0_TX2+
GND
GPIO_WAN7
GPIO_WAN8
−
SDMMC1_CLK
SDMMC1_CMD
−
CSI_E_CLK_N
CSI_E_CLK_P
−
CSI_C_CLK_N
CSI_C_CLK_P
−
CSI_A_CLK_N
CSI_A_CLK_P
−
DSI_C_CLK_P
DSI_C_CLK_N
−
DSI_A_CLK_P
DSI_A_CLK_N
−
HDMI_DP0_TXDN0
HDMI_DP0_TXDP0
−
G39
PEX_RFU_RX+
PEX_RX1P
DAP1_FS
DAP1_DOUT
GPIO_AUD0
SPI 2 Master Out / Slave In
SPI 2 Chip Select 0
GND
SD Card (or SDIO) Clock
SD Card (or SDIO) Command
GND
Camera, CSI 4 Clock–
Camera CSI 4 Clock+
GND
Camera, CSI 2 Clock–
Camera, CSI 2 Clock+
GND
Camera, CSI 0 Clock–
Camera, CSI 0 Clock+
GND
Display DSI 2 Clock+
Display DSI 2 Clock–
GND
Display, DSI 0 Clock+
Display, DSI 0 Clock–
GND
DisplayPort 0 Lane 2– or HDMI Lane 0–
DisplayPort 0 Lane 2+ or HDMI Lane 0+
GND
PCIe RFU Receive+ (PCIe IF #0 Lane 3 or
USB 3.0 Port #1)
PCIe RFU Receive– (PCIe IF #0 Lane 3 or
USB 3.0 Port #1)
GND
USB SS 1 Receive+ (USB 3.0 Port #2 or
PCIe IF #0 Lane 1)
USB SS 1 Receive– (USB 3.0 Port #2 or
PCIe #0 Lane 1)
GND
SATA Receive+
SATA Receive–
GND
GbE Transformer Data 2+
GbE Transformer Data 2–
GND
I2S Audio Port 0 Left/Right Clock
I2S Audio Port 0 Data Out
Audio Codec Interrupt or GPIO
G40
PEX_RFU_RX–
G41
GND
G42
USB_SS1_RX+
PEX_RX1N
−
PEX_RX2P
PEX_RX2N
G44
G45
G46
G47
G48
G49
G50
H1
H2
H3
GND
SATA_RX+
SATA_RX–
GND
GBE_MDI2+
GBE_MDI2–
GND
I2S0_LRCLK
I2S0_SDOUT
GPIO20_AUD_INT
H4
DSPK_OUT_DAT
GPIO_AUD2
Digital Speaker Output Data
H5
I2S2_LRCLK
DMIC1_CLK
I2S Audio Port 2 Left/Right Clock
−
−
−
−
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
M.2 Key E
Camera Connector
Not assigned
USB_SS1_RX–
−
GND
GPIO Expansion
Header
UART 3 Clear to Send
G43
PEX_RX5P
PEX_RX5N
Usage on the Carrier
Board
Debug Header
Expansion Header
Camera Conn & Exp.
Hdr.
Display/Camera Conns.
GND
SD Card
GND
Camera Connector
GND
Camera Connector
GND
Camera Connector
GND
Display Connector
GND
Display Connector
GND
Display Connector
GND
Input
PCIe x4 Connector
Input
GND
−
Input
PCIe x4 Connector
Input
GND
SATA Connector
GND
LAN
GND
Expansion Header
GPIO Expansion
Header
M.2 Key E
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
AC-Coupled on carrier
board
GND
PCIe PHY, AC-Coupled on
carrier board
GND
USB SS PHY, AC-Coupled
(off the module)
−
Input
Input
−
Bidir
Bidir
−
Bidir
Bidir
Input
GND
SATA PHY, AC-Coupled on
carrier board
GND
Output
CMOS – 1.8V
Bidir
CMOS – 1.8V
MDI
GND
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
101
NVIDIA Jetson TX2/TX2i OEM Product Design Guide
Usage on the Carrier
Board
Pin # Module Pin Name
Tegra Signal
Usage/Description
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
I2S2_SDOUT
GPIO3_CAM1_RST#
GPIO2_CAM0_RST#
UART3_RX
UART3_TX
UART0_CTS#
UART0_TX
GPIO8_ALS_PROX_INT
SPI2_CLK
SPI2_MISO
SDCARD_PWR_EN
SDCARD_D1
SDCARD_D0
GND
CSI4_D1–
CSI4_D1+
GND
CSI2_D1–
CSI2_D1+
GND
CSI0_D1–
CSI0_D1+
GND
DSI2_D1+
DSI2_D1–
GND
DSI0_D1+
DSI0_D1–
GND
DP0_TX3–
DP0_TX3+
GND
DP0_TX0–
DP0_TX0+
GND
DMIC2_CLK
QSPI_IO0
QSPI_CS_N
UART4_RX (via mux)
UART4_TX (via mux)
UART1_CTS
UART1_TX
GPIO_PQ4
GPIO_WAN5
GPIO_WAN6
GPIO_EDP3
SDMMC1_DAT1
SDMMC1_DAT0
−
CSI_E_D1_N
CSI_E_D1_P
−
CSI_C_D1_N
CSI_C_D1_P
−
CSI_A_D1_N
CSI_A_D1_P
−
DSI_C_D1_P
DSI_C_D1_N
−
DSI_A_D1_P
DSI_A_D1_N
−
HDMI_DP0_TXDN3
HDMI_DP0_TXDP3
−
HDMI_DP0_TXDN2
HDMI_DP0_TXDP2
−
H41
PEX1_RX+
PEX_RX0P
H42
PEX1_RX–
PEX_RX0N
H43
H44
H45
H46
H47
H48
H49
H50
GND
PEX0_RX+
PEX0_RX–
GND
GBE_MDI3+
GBE_MDI3–
GND
RSVD
I2S Audio Port 2 Data Out
Camera 1 Reset or GPIO
Camera 0 Reset or GPIO
UART 3 Receive
UART 3 Transmit
UART 0 Clear to Send
UART 0 Transmit
Proximity sensor Interrupt or GPIO
SPI 2 Clock
SPI 2 Master In / Slave Out
SD Card power switch Enable
SD Card (or SDIO) Data 1
SD Card (or SDIO) Data 0
GND
Camera, CSI 4 Data 1–
Camera, CSI 4 Data 1+
GND
Camera, CSI 2 Data 1–
Camera, CSI 2 Data 1+
GND
Camera, CSI 0 Data 1–
Camera, CSI 0 Data 1+
GND
Display, DSI 2 Data 1+
Display, DSI 2 Data 1–
GND
Display, DSI 0 Data 1+
Display, DSI 0 Data 1–
GND
DisplayPort 0 Lane 3– or HDMI Clk Lane–
DisplayPort 0 Lane 3+ or HDMI Clk Lane+
GND
DisplayPort 0 Lane 0– or HDMI Lane 2–
DisplayPort 0 Lane 0+ or HDMI Lane 2+
GND
PCIe 1 Receive+ (PCIe #2 Lane 0 muxed
w/USB 3.0 Port #0)
PCIe 1 Receive– (PCIe #2 Lane 0 muxed
w/USB 3.0 Port #0)
GND
PCIe 0 Receive+ (PCIe IF #0 Lane 0)
PCIe 0 Receive– (PCIe IF #0 Lane 0)
GND
GbE Transformer Data 3+
GbE Transformer Data 3–
GND
Not used
Ground
Legend
Notes:
1.
2.
3.
−
PEX_RX4P
PEX_RX4N
−
−
−
−
−
Power
RSVD on Jetson TX2 (available on TX2i)
Camera Connector
Optional source of
UART on Exp. Header
Debug Header
Sensor
Display/Camera Conns.
SD Card
GND
Camera Connector
GND
Camera Connector
GND
Camera Connector
GND
Display Connector
GND
Display Connector
GND
Display Connector
GND
Display Connector
GND
USB 3.0 Type A
(Default) or M.2 Key E
GND
PCIe x4 Connector
GND
LAN
GND
Reserved
−
Direction
Pin Type
Bidir
Output
Output
Input
Output
Input
Output
Input
Bidir
Bidir
Output
Bidir
Bidir
−
Input
Input
−
Input
Input
−
Input
Input
−
Output
Output
−
Output
Output
−
Output
Output
−
Output
Output
−
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 1.8V
CMOS – 3.3V/1.8V
CMOS – 3.3V/1.8V
GND
Input
Input
−
Input
Input
−
Bidir
Bidir
−
−
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
MIPI D-PHY
GND
AC-Coupled on carrier
board
GND
AC-Coupled on carrier
board
GND
PCIe PHY, AC-Coupled on
carrier board
GND
PCIe PHY, AC-Coupled on
carrier board
GND
MDI
GND
−
Redefined for Jetson TX2i
The Usage/Description column uses the module port/lane/interface references.
In the Type/Dir column, Output is from the module. Input is to the module. Bidir is for Bidirectional signals.
These pins are handled as Open-Drain on the carrier board
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618
102
Notice
T he information provided in this specification is believed to be accurate and reliable as of the date provided. However, NVIDIA Corporation
("NVIDIA") does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information.
NVIDIA shall have no liability for the consequences or use of such information or for any infringement of patents or other rights of third
parties that may result from its use. T his publication supersedes and replaces all other specifications for the product that may have been
previously supplied.
NVIDIA reserves the right to make corrections, modifications, enhancements, improvements, and other changes to this specification, at any
time and/or to discontinue any product or service without notice. Customer should obtain the latest relevant specification before placing
orders and should verify that such information is current and complete.
NVIDIA products are sold subject to the NVIDIA standard terms and conditions of sale supplied at the time of order acknowledgment, unless
otherwise agreed in an individual sales agreement signed by authorized representatives of NVIDIA and customer. NVIDIA hereby expressly
objects to applying any customer general terms and conditions with regard to the purchase of the NVIDIA product referenced in this
specification.
NVIDIA products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life suppo rt
equipment, nor in applications where failure or malfunction of the NVIDIA product can reasonably be expected to result in per sonal injury,
death or property or environmental damage. NVIDIA accepts no liability for inclusion and/or use of NVIDIA products in such equipment or
applications and therefore such inclusion and/or use is at customer's own risk.
NVIDIA makes no representation or warranty that products based on these specifications will be suitable for any specified use without
further testing or modification. T esting of all parameters of each product is not necessarily performed by NVIDIA. It is c ustomer's sole
responsibility to ensure the product is suitable and fit for the application planned by customer and to do the necessary test ing for the
application in order to avoid a default of the application or the product. Weaknesses in customer's product designs may affect the quality and
reliability of the NVIDIA product and may result in additional or different conditions and/or requirements beyond those conta ined in this
specification. NVIDIA does not accept any liability related to any default, dam age, costs or problem which may be based on or attributable
to: (i) the use of the NVIDIA product in any manner that is contrary to this specification, or (ii) customer product designs.
No license, either expressed or implied, is granted under any NVIDIA p atent right, copyright, or other NVIDIA intellectual property right
under this specification. Information published by NVIDIA regarding third-party products or services does not constitute a license from
NVIDIA to use such products or services or a warrant y or endorsement thereof. Use of such information may require a license from a third
party under the patents or other intellectual property rights of the third party, or a license from NVIDIA under the patents or other intellectual
property rights of NVIDIA. Reproduction of information in this specification is permissible only if reproduction is approved by NVIDIA in
writing, is reproduced without alteration, and is accompanied by all associated conditions, limitations, and notices.
ALL NVIDIA DESIGN SPECIFICAT IONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOST ICS, LIST S, AND OT HER
DOCUMENT S (T OGET HER AND SEPARAT ELY, "MAT ERIALS") ARE BEING PROVIDED "AS IS." NVIDIA MAKES NO
WARRANT IES, EXPRESSED, IMPLIED, ST AT UT ORY, OR OT HERWISE WIT H RESPECT T O T HE MAT ERIALS, A ND
EXPRESSLY DISCLAIMS ALL IMPLIED WARRANT IES OF NONINFRINGEMENT , MERCHANT ABILIT Y, AND FIT NESS FOR A
PART ICULAR PURPOSE. Notwithstanding any damages that customer might incur for any reason whatsoever, NVIDIA's aggregate and
cumulative liability towards customer for the products described herein shall be limited in accordance with the NVIDIA terms and conditions
of sale for the product.
VESA DisplayPort
DisplayPort and DisplayPort Compliance Logo, DisplayPort Compliance Logo for Dual-mode Sources, and DisplayPort Compliance Logo
for Active Cables are trademarks owned by the Video Electronics Standards Association in the United States and other countrie s.
HDMI
HDMI, the HDMI logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC.
Trademarks
NVIDIA, the NVIDIA logo, T egra and Jetson are trademarks and/or registered trademarks of NVIDIA Corporation in the U.S. and o ther
countries. Other company and product names may be trademarks of the respective companie s with which they are associated.
Copyright
© 2014, 2015, 2016, 2017 NVIDIA Corporation. All rights reserved.
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.7 Linearized : No Page Count : 103 Language : en-US Tagged PDF : Yes XMP Toolkit : 3.1-701 Producer : Microsoft® Word 2016 Title : Jetson TX2/TX2i OEM Product Design Guide Creator : Nvidia Description : Jetson TX2 OEM Product Design Guide Creator Tool : Microsoft® Word 2016 Create Date : 2018:06:18 11:11:35-07:00 Modify Date : 2018:06:18 11:11:35-07:00 Document ID : uuid:97CA4BD5-582D-4B63-B04E-2CDDC1F79F56 Instance ID : uuid:97CA4BD5-582D-4B63-B04E-2CDDC1F79F56 Author : Nvidia Subject : Jetson TX2 OEM Product Design GuideEXIF Metadata provided by EXIF.tools