K23 051 7863 A

User Manual:

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1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

(.csa)

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Contents
Table of Contents

N/A

TABLE_TABLEOFCONTENTS_HEAD

09/02/2009

TABLE_TABLEOFCONTENTS_ITEM

09/02/2009

TABLE_TABLEOFCONTENTS_ITEM

MASTER

2

System Block Diagram

K22

Power Block Diagram

K22

3
4

BOM Configuration

N/A

TABLE_TABLEOFCONTENTS_ITEM

N/A

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N/A

TABLE_TABLEOFCONTENTS_ITEM

09/02/2009

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N/A

TABLE_TABLEOFCONTENTS_ITEM

MASTER

6

Power Conn / Alias

MASTER

7

Holes

MASTER

8

UNUSED SIGNAL ALIAS

K22

Signal Aliases

MASTER

9
10

CPU FSB

09/02/2009

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09/02/2009

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09/02/2009

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K22

11

CPU TEST & MISC.

K22

12

CPU POWER, GND, DECAPS

K22

13

eXtended Debug Port (XDP)

K22

14

MCP CPU Interface

K22

15

MCP Memory Interface

K22

MCP MEMORY CNTRL & MISC

K22

16
17

MCP PCIe Interfaces

09/02/2009

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09/02/2009

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K22

18

MCP Ethernet & Graphics

K22

19

MCP PCI & LPC

K22

20

MCP SATA & USB

K22

21

MCP HDA & MISC

K22

22

MCP Power & Ground

K22

MCP Standard Decoupling

K22

25
26

MCP Graphics Support

09/02/2009

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09/02/2009

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09/02/2009

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N/A

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07/06/2009

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09/02/2009

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N/A

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K22

28

SB Misc

K22

29

FSB/DDR3 Vref Margining

K22

30

MEMORY CAPS

MASTER

31

DDR3 SO-DIMMs 0 & 2

K22

32

DDR3 SO-DIMM CONNECTOR B

K22

DDR3 SUPPORT AND BITSWAPS

MASTER

33
34

PCI-E Wireless Connector

05/28/2009

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09/02/2009

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09/02/2009

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N/A

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03/12/2009

TABLE_TABLEOFCONTENTS_ITEM

03/12/2009

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K22

37

Ethernet PHY (RTL8211CL)

K22

38

Ethernet Support

K22

39

ETHERNET CONNECTOR

MASTER

41

FireWire LLC/PHY (XIO2213B)

K22

42

FW: 1394B MISC

K22

FIREWIRE CONNECTOR

K22

43
45

SATA Connectors

K22

46

EXTERNAL USB CONNECTORS

K22

47

Internal USB Connections

K22

49

SMC

MARKVIDEO

SMC Support

MARKVIDEO

50
51

09/02/2009

LPC+SPI Debug Connector

K22

SMBus Connections

MASTER

CPU/MXM CURRENT AND VOLTAGE SENSE

K22

MCP CURRENT AND VOLTAGE SENSE

K22

52

1

REV

ECN

DESCRIPTION OF REVISION

A

0000774489

CK
APPD
DATE

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2

PRODUCTION RELEASED

2009-08-20

D

LAST_MODIFIED=Wed Sep 2 16:45:56 2009
Page
Contents
Sync

Date

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K23

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84
85
86

Date

55

09/02/2009

Thermal Sensors

K22

HD AND OD FAN

K22

CPU FAN

K22

SPI ROM

K22

AUDIO: CODEC/REGULATOR

K22

AUDIO: FILTER/BUFFER

SKIPAUDIO

AUDIO: Tweeter Amp 1

SKIPAUDIO

AUDIO: Woofer Amp

SKIPAUDIO

Audio: MLB to I/O Conn.

K22

AUDIO: Detects/Grounding

SKIPAUDIO

AUDIO: Mikey

K22

POWER SEQUENCING BLOCK DIAGRAM

K22

PGOOD and Power Sequencing

K22

VREG: PPVCORE_S0_CPU

K22

VREG: PPVCORE_S0_CPU

K22

5V_S3 REGULATOR

K22

MCP CORE REGULATOR

K22

1.5V DDR SUPPLY

K22

FSB VTT/3.3V S5 SUPPLIES

K22

S3 & S0 FETs

K22

1V1 S5 POWER SUPPLY

K22

MXM PCIe, DP & Power

K22

MXM I/O

K22

MXM PCIE CAPS

K22

Display: Aliases

MARKVIDEO

Display: Int DP Connector

MARKVIDEO

Display: BiDiVi Mux1

MARKVIDEO

BIDIVI DP MUX2

MASTER

Display: Ext DP Connector

MARKVIDEO

Display: BiDiVi Support

MARKVIDEO

CPU/FSB Constraints

K22

Memory Constraints

K22

MCP Constraints 1

K22

MCP Constraints 2

K22

56

09/02/2009

57

09/02/2009

61

09/02/2009

62

09/02/2009

63

04/20/2009

64

04/20/2009

65

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67

04/20/2009

68

09/02/2009

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70

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C

09/02/2009

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76

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78

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79

09/02/2009

84

09/02/2009

85

09/02/2009

86

09/02/2009

87

03/12/2009

90

03/12/2009

91

03/12/2009

92

N/A

94

03/12/2009

95

03/12/2009

100

09/02/2009

101

09/02/2009

102

09/02/2009

103

B

09/02/2009

104

09/02/2009

Ethernet Constraints

K22

FireWire Constraints

K22

SMC Constraints

K22

Graphics Constraints

MASTER

K22/K23 SPECIFIC CONSTRAINTS

K22

K22/K23 RULE DEFINITIONS

K22

K22/K23 ICT/FCT

K22

105

09/02/2009

106

09/02/2009

107

N/A

108

09/02/2009

109

09/02/2009

110

09/02/2009

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09/02/2009

54

09/02/2009

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A

A
DRAWING TITLE

SCH,K23,MLB
DRAWING NUMBER

Apple Inc.

051-7863
REVISION

R

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
DRAWING
IV ALL RIGHTS RESERVED

DRAWING
TITLE=K22
ABBREV=DRAWING
LAST_MODIFIED=Wed Sep

2 16:45:56 2009

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U1000

INTEL CPU
3.X GHZ

POWER SUPPLY

PG 10-12

LGA775 - WOLFDALE

U1300

PG 10

TEMP, CURRENT SENSE

XDP CONN
PG 13

FSB

D
PG 13

J3100, J3200

MAIN
MEMORY

FSB INTERFACE

GPIOs

4 SO-DIMMs
DDR3-1067MHZ

D

TEMP SENSORS
MXM - GPU DIE
CPU HEATSINK
GPU HEATSINK
AMBIENT INTAKE
CPU DIE
HARD DRIVE
OPTICAL DRIVE
MCP DIE
MCP HEATSINK
LCD TEMP

64-Bit
1333 MHZ

DIMM

PG 15
PG 31,32

PG 55

Misc
CLK
PG 24
U6100

SYNTH

J4510

SPI
1.05V/3GHZ.
PG 45

SATA-A0

SATA
Conn
HD

SATA-A1

C

PG 45

FAN CONN AND CONTROL

PG 61

PG 56,57

NVIDIA
1.05V/3GHZ.

J5600, J5601, J5700

PG 21

J4520

SATA
Conn
ODD

POWER PGSENSE
53

SPI
Boot ROM

U4900

B,0

MCP7A

SATA

BSB

SMC
LPC

PG 20

ADC Fan Ser
Prt

PG 49

PWR
CTRL

LVDS OUT

J4720

DVI OUT

J4700

J4780

Bluetooth

IR

PG 47

PG 47

J47xx

CAMERA

J4610,4620,4630,4640

SD CARD

J9410

PG 18

USB

X16 PCI-E

PG 20

MXM CONNECTOR
PG 84

B

PCI-E

UP TO 20 LANES3
PG 17

PG 90

(UP TO 12 DEVICES)

HDMI OUT
J8400

PG 47

0 1 2 3 4 5 6 7 8 9 10 11

DP OUT

INTERNAL
DISP

EXTERNAL
USB
Connectors

RGB OUT

J9002

C

PG 51

TMDS OUT

PG 94

LPC+SPI CONN
Port80,serial

PG 19

U1400

DISPLAY
PORT
CONN

J5100

PG 47

PG 47

WHICH PORT?

B
DIMM’s

SMB
PG 21

RGMII

PCI

(UP TO FOUR PORTS)

MIKEY

HDA

PG 18
PG 19

PG 21

U6806

U4100

U6201

FW643

Audio
Codec

U3700

GB
E-NET

PG 41

Mikey

RTL8211CLGR
PG 37

U6400, U6500
T3900

A

Speaker
Amps

MAGNETICS

SYNC_MASTER=K22

Headphones
Int/Ext Mics
Line In

SYNC_DATE=09/02/2009

System Block Diagram

PG 39

J4300

DRAWING NUMBER

Apple Inc.

J3400
U3900

FireWire
Conn

Mini PCI-E
AirPort

PG 43

PG 34

NOTICE OF PROPRIETARY PROPERTY:

J6600,J6601,J6602,J6603

Audio
Conns

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PG 39

SIZE

051-7863

D

REVISION

A.0.0

R

E-NET
Conn

A

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D
AC/DC POWER SUPPLY

SMBUS
TEMP SENSOR
CONTROL
DCM/FCM

12V_S5

PM_SLP_S3_OD

PAGE 6

PP12V_S0_HDD
PP12V_S0_INV
PP12V_S5

PP12V_S0
24" PANEL
20" PANEL
HARD DRIVE
FANS
MXM
20" INVERTER
AUDIO

FIREWIRE PORTS

C

PPVCORE_CPU

DDR3 MAIN MEMORY
PP5V_S3_REG

USB
CAMERA
IR

MAIN MEMORY

PPDDR_S3_REG

PAGE 74

PPVTT_S0_FSB

PAGE 75

C

MCP, CPU FSB (VTT)

PAGE 76
PM_SLP_S3

P5VS0_EN

PP5V_S0

AUDIO
20" PANEL
OPTICAL
MXM
HDD

PAGE 78

PP1V5_S0

PP1V8_S0_REG

CPU_AVDD
AP PCIE
MCP79 MEM

PAGE 78

PAGE 80

PP0V75_S0
PP3V3_S5_REG

CPU_CORE

PAGE 71-72

BOOT ROM
MCP
SMC

MEM_VTT

PAGE 75

PAGE 76

P3V3S3_EN
PP1V2_S3
PP3V3_S3
PAGE 76

ETHERNET
BT
AP
FW

PP1V_S5

FW

ENET

PAGE 38

PAGE 42

B

B
P3V3S0_EN

PP3V3_S0
PAGE 78

PP1V1_S5

AUDIO
MXM
CLOCK
MCP

MCP_ENET
MCP_VDD_AUXC

PAGE 79

PPMCPCORE_S0_REG MCP_CORE
CPU_VCCP
MCP_PLL
PAGE 74

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Power Block Diagram
DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

051-7863
BRANCH

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COMMON

BOM Variants

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

338S0731

1

IC,GMCP,MCP7A-JA,B03,35X35MM,BGA1437,DT

U1400

CRITICAL

IG

338S0732

1

IC,MCP,MCP7A-DA,B03,35X35MM,BGA1437,DT

U1400

CRITICAL

MXM

TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

TABLE_5_ITEM

BOM OPTIONS
TABLE_BOMGROUP_ITEM

630-9879

PCBA,MLB,BETTER,K23

K23,2P80GHZ_CPU,BASIC,MXM,K23_MXM

639-0394

PCBA,MLB,2.80 GHZ-2M,K23

K23,2P80GHZ_2M_CPU,BASIC,MXM,K23_MXM

341T0170

1

IC,EFI BOOTROM,K22/K23

U6100

CRITICAL

338S0765

1

IC,XIO2211ZAY,1394B,167BGA

U4100

CRITICAL

338S0694

1

IC,RTL8251CA,GIGE TRANSCEIVER, 48P TQFP

U3700

CRITICAL

825-7122

1

MLB LABEL,48.0X4.8

X14

CRITICAL

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

D

639-0185

PCBA,MLB,2.93 GHZ,K23

TABLE_5_ITEM

K23,2P93GHZ_CPU,BASIC,MXM,K23_MXM
TABLE_BOMGROUP_ITEM

PCBA,MLB,BEST,K23

630-9983

MCP -J SKU HAS INTEGRATED GPU
MCP -D SKU DOES NOT

TABLE_5_ITEM

D

TABLE_5_ITEM

K23,3P0GHZ_CPU,BASIC,MXM,K23_MXM
TABLE_BOMGROUP_ITEM

639-0509

PCBA,MLB,3.06 GHZ,K23

K23,3P06GHZ_CPU,BASIC,MXM,K23_MXM

639-0109

PCBA,MLB,3.16 GHZ,K23(INVESTIGATION)

K23,3P16GHZ_CPU,BASIC,MXM,K23_MXM

630-9880

PCBA,MLB,ULTIMATE,K23

K23,3P33GHZ_CPU,BASIC,MXM,K23_MXM

607-4427

PCBA,MLB,DEV,K23

DEVELOPMENT,DEV_GROUP

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CPUS
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

TABLE_5_ITEM

337S3745

1

WLF,QXXX,QS,2.80G,65W,1066,R0,3M,LGA

CPU

CRITICAL

2P80GHZ_CPU

337S3742

1

WLF,SLB9J,PRQ,2.83G,65W,1333,E0,6M,LGA

CPU

CRITICAL

2P83GHZ_CPU

337S3726

1

WLF,SLB9J,PRQ,3.0G,65W,1333,E0,6M,LGA

CPU

CRITICAL

3P0GHZ_CPU

337S3715

1

WLF,SLB9K,PRQ,3.16G,65W,1333,E0,6M,LGA

CPU

CRITICAL

3P16GHZ_CPU

337S3727

1

WLF,SLB9L,PRQ,3.33G,65W,1333,E0,6M,LGA

CPU

CRITICAL

3P33GHZ_CPU

337S3807

1

WLF,SLB9L,PRQ,2.93G,65W,1333,E0,6M,LGA

CPU

CRITICAL

2P93GHZ_CPU

337S3766

1

WLF,SLB9L,PRQ,3.06G,65W,1333,E0,6M,LGA

CPU

CRITICAL

3P06GHZ_CPU

337S3804

1

WLF,SLGU9,PRQ,2.80G,65W,1066,R0,2M,LGA

CPU

CRITICAL

2P80GHZ_2M_CPU

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

C

C
BOM GROUPS
TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

BASIC

COMMON,ALTERNATE,MCP7A,XDP,BETTER,MCP_ISL9563A,PRODUCTION

MCP7A

BOOT_MODE_USER,MEMRESET_HW,MEMRESET_MCP

DEV_GROUP

XDP_CONN,LPCPLUS,VREFMRGN,MCP_PWR_SENSE,MCP_CPU_TDIODE,PECI_SMB,MOJOMUX

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

K23 PARTS
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

051-7863

1

SCH,K23,MLB

SCH1

820-2507

1

PCBF,K23,MLB

(338S0489 - BLNK) 341T0169

1

IC,SMC,K23

CRITICAL

BOM OPTION
TABLE_5_ITEM

K23
TABLE_5_ITEM

MLB1

K23
TABLE_5_ITEM

U4900

CRITICAL

K23

BOARD STACK-UP
B

TOP
2
3
4
5
6
7
BOTTOM

B

ALTERNATES

SIGNAL
GROUND
SIGNAL
POWER
POWER
SIGNAL
GROUND
SIGNAL

A

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE

BOM Configuration
DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

051-7863
BRANCH

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D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/05/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

051-7863
BRANCH

PAGE

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6

EMC: C600,C626,C627,C628,C629,C630,C631
PLACE AT J600.

5

518-0352
CRITICAL

4

3

"S0" RAILS

J600

1
"S5" RAILS

"S3" RAILS
ON IN RUN AND SLEEP

ONLY ON IN RUN

76833-0100

2

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

M-RT-TH

52
45 6
6

90

=SMB_ACDC_SCL
=PP5V_S0_SATA
PP12V_S5
LCD_PWM

D

1

8

2

9

3

10

4

11

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12

6

13

7

14

=SMB_ACDC_SDA
PP12V_S0

52
75

PPVTT_S0_DDR_LDO
MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

70 6

LCD_BKL_ON 90
72 71

PPVCORE_S0_CPU

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP

=PPVCORE_S0_CPU

75

MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PPDDR_MEM
MAX_NECK_LENGTH=3 MM

78

12

MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

C623

1

10UF

C631
0.001UF

20%
2 10V
X5R
805

10%
2 50V
X7R
402

1

C627

1

0.001UF

C626

1

0.001UF

10%
2 50V
X7R
402

C630
0.001UF

10%
2 50V
X7R
402

10%
2 50V
X7R
402

1

C624
10UF

54 74

PPMCPCORE_S0_REG
MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

10%
2 16V
X5R-CERM
1210

PM_ACDC_PS_ON

3

0.001UF
10%
50V
X7R
402

2N7002

70 50 49 9

1

PM_SLPS3_BUF2_L

IN

G

SOT23-HF1

S

2

76

PPVTT_S3_DDR_BUF

=PPVTT_S3_DDR_BUF

108 30 31
79

=PPVCORE_S0_MCP
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_HDMI_VDD_R

110 6 78

PP3V3_S3
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

22 25

25
25 28
25
28 20
26

PP1V1_S5_REG

78

MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

110 73

54

PP1V5_S0
MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

C

=PPVTT_S0_CPU
=PPVTT_S0_FSB_CPU
=PPVTT_S0_XDP
=PP1V05_S0_MCP_FSB

=PP1V5_S0_CPU_VCCPLL
=PP1V8R1V5_S0_MCP_MEM
=PP1V5_S0_AUD_DIG
=PP1V5_FWRS0_FWXIO

11 12
13
14 22 25

=PP5V_S3_DDRREG
=PP5V_S3_USB
=PP5V_S3_VTTCLAMP
=PP5V_S3_PWRCTL
=PP5V_S3_S0FET
=PP5V_S3_MCPREG
=PP5V_S3_CAMERA
=PP5V_S3_IR
=PP5V_S3_1V8

=PP3V3_S5_MCP
=PP3V3_S5_MCP_GPIO
=PP3V3_S5_SMC
=PP3V3_S5_ROM
=PP3V3_S5_RTC_D
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMBUS_SMC_BSA

MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
34
47
29

21
50
52
74

75

78
76

47

PP5V_S5_LDO

47

PP12V_S5

R600
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

ITS_ALIVE

=PP3V3R1V8_S0_MCP_IFP_VDD_R
=PP1V8_S0_PGCMP

51

=PP3V3_S5_SMCUSBMUX
=PP3V3_S5_MEMRESET
=PP3V3_S5_P1V1S5
=PP3V3_S5_PWRCTL
=PP3V3_S5_S3FET
=PP3V3_S5_S0FET
=PP3V3_S5_ENET_FET

70

=PP5V_S5_AVREF

50

46
33
79

78
78
38

=PP12V_S5_FW
=PPVIN_S5_DDRREG
=PPVIN_S5_P3V3S5
=PPVIN_S5_P5VS3
=PP12V_S5_REG
=PP12V_S5_PWRCTL

1

PP1V8_S0_REG

28

52

MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

74

DEVELOPMENT

5%
1/16W
MF-LF
2 402

51 61

70

PP3V3_S3

1K

49 50

78

MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

41

18 20

46

6

62

22 25

47

12
16 25 30

38

D
PP3V3_S5_REG

PP5V_S3_REG
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

10 50 55 71

22 25

70

29
6 76

=PP3V3_S3_MINI
=PP3V3_S3_BT
=PP3V3_S3_VREFMRGN
=PP3V3_S3_SDCARD
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_SMC
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_MCPREG

=PP1V05_S5_MCP_VDD_AUXC
=PP1V1_S5_ENET_FET

MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

108 30 32
33

MAKE_BASE=TRUE
VOLTAGE=0.75V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 mm

PPVTT_S0_FSB_REG

2

110 6 78

75

=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET
=PPDDR_S3_S0FET
=PPDDR_S3_PGCMP

C600

1

Q610

D

PPDDR_S3_REG

31
32

43
75

C

76
73
76
38 70 78

26
70

1 DEVELOPMENT

LED605
2

GND RAILS

GREEN-3.6MCD
2.0X1.25MM-SM

GND
110 6 78

1

R602

6 78

5%
1/16W
MF-LF
2 402

PP3V3_S5_REG
1

R601

PP3V3_S0
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1K

6 76

CORE_VOLTAGES_ON_R

1K

=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
=PP3V3_S0_VRD
=PP3V3_S0_AUDIO
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_SMBUS
=PP3V3_S0_SMC_LS
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_SMBUS_SMC_MGMT
=PP3V3_S0_DPCONN
=PP3V3_S0_TSENS
=PP3V3_S0_MXM
=PP3V3_S0_XDP
=PP3V3_S0_ODD
=PP3V3_S0_SATALED
=PP3V3_S0_SMC
=PP3V3_S0_PWRCTL
=PP3V3_S0_MCPTHMSNS
=PP3V3_S0_VIDEO
=PP3V3_FW_FWPHY
=PP3V3_FWRS0_FWXIO
=PP3V3_S0_DP

LED602

ITS_PLUGGED_IN

GREEN-3.6MCD
2.0X1.25MM-SM

2

SILKSCREEN:2
CORE_VOLTAGES_ON

1

6

LED601
D

GREEN-3.6MCD
2.0X1.25MM-SM

2

SILKSCREEN:1

2N7002DW-X-G

G

ALL_SYS_PWRGD_R

SOT-363

1 S

IN

2

Q602
70

6 78

PP3V3_S0

6 78

PP3V3_S0

1

R604

1

1K

R603

5%
1/16W
MF-LF
2 402

1K
5%
1/16W
MF-LF
2 402

GPU_PRESENT_R

PP5V_S0
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

LED604
GREEN-3.6MCD
2.0X1.25MM-SM

LED603

SILKSCREEN:3
GPU_PRESENT_DRAIN

A

110 78

LCD_SHOULD_ON

1

2

=PP3V3_S0_FAN
=PP3V3_S0_MCP
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_MCP_PLL_UF

MAKE_BASE=TRUE
MAX_NECK_LENGTH=4.1 MM

56 57
21 22 25
26
18 19 21
25

1

5%
1/16W
MF-LF
2 402

B

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=0V
NET_SPACING_TYPE=AUDIO

PP3V3_S3

2

GREEN-3.6MCD
2.0X1.25MM-SM

SILKSCREEN:4

=PP5V_S0_LPCPLUS
=PP5V_S0_AUDIO
=PP5V_S0_SATA
=PP5V_S0_MXM
=PP5V_S0_VRD
=PP5V_S0_DP_AUX_MUX
=PP5V_S0_ISENSE
=PP5V_S0_PWRCTL

31
32
71
62 64 65 66 67 68
21 25

B

52
50 55
52
52
52
94
55
85 84
13
45
45
50 53 54
70
55
90
41 42 43
41
95 87 90 91 92

51
62 68
6 45
84
71

53

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

D

3

PAGE TITLE
90

MXM_GOOD

4 S

IN

G

9

5

Q602

IN

Power Conn / Alias

VIDEO_ON_L
6 70

sourced from buffer on csa 90

PP12V_S0
MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

2N7002DW-X-G
SOT-363

=PP12V_S0_FAN
=PP12V_S0_AUDIO_SPKRAMP
=PP12V_S0_VRD
=PPV_S0_MXM_PWR
=PPVIN_S0_PPVTT_FSB
=PP12V_S0_LCD
=PPVIN_S0_MCPCORE

DRAWING NUMBER

56 57
67

Apple Inc.

70 71

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

90
74

D

REVISION

A.0.0

R

53
76

SIZE

051-7863
BRANCH

PAGE

6 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

CPU Heatsink

1

Nuts (805-9582)

OMIT

OMIT

OMIT

OMIT

ZH0700

ZH0701

ZH0702

ZH0703

1

2

DIMM CONNECTOR NUTS

4mm Plated Holes (998-0850)

4P75R4

3

4P75R4

4P75R4

1

CRITICAL

1

CRITICAL

CRITICAL

CRITICAL

NUT0750

NUT0751

NUT0752

NUT0753

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-4.25OD1.4H-1.40-3.25-TH

4P75R4

1

D

1

1

1

D

1

MCP Heatsink
EMC Springs (870-1125)
CRITICAL

1

CRITICAL

SC0700

1

EMI-SPRING

SC0701
EMI-SPRING

CLIP-SM1

CLIP-SM1

C

C
Rear Cover
Standoffs (860-1255)
CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

SDF0714

SDF0715

SDF0717

SDF0718

SDF0719

STDOFF-6.8OD15.0H-1.56-TH

STDOFF-6.8OD15.0H-1.56-TH

STDOFF-6.8OD15.0H-1.56-TH

STDOFF-6.8OD15.0H-1.56-TH

STDOFF-6.8OD15.0H-1.56-TH

1

B

CRITICAL

SDF0713
STDOFF-6.8OD15.0H-1.56-TH

1

1

1

1

1

Backer Plate

B

Nuts (835-0269)
CRITICAL

CRITICAL

CRITICAL

CRITICAL

NUT0700

NUT0701

NUT0702

NUT0703

NUT-6.5OD1.4H-1.56-3.8-TH

NUT-6.5OD1.4H-1.56-3.8-TH

NUT-6.5OD1.4H-1.56-3.8-TH

NUT-6.5OD1.4H-1.56-3.8-TH

1

1

1

1

A

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE

Holes
DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

051-7863
BRANCH

PAGE

7 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

17

TP_PCIE_PE4_R2D_CP

NC_PCIE_PE4_R2D_CP

17

TP_PCIE_PE4_R2D_CN

NC_PCIE_PE4_R2D_CN

17

TP_PCIE_PE4_D2RP

NC_PCIE_PE4_D2RP

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

NC ON UNUSED ALIASES

D

18

MCP_TV_DAC_RSET

18

MCP_TV_DAC_VREF

18

MCP_CLK27M_XTALIN

18

MCP_CLK27M_XTALOUT

18

CRT_IG_R_C_PR

18

CRT_IG_G_Y_Y

NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_TV_DAC_VREF
MAKE_BASE=TRUE

TP_ENET_INTR_L

18

TP_ENET_PWRDWN_L

21

TP_MCP_KBDRSTIN_L

NC_MCP_KBDRSTIN_L

TP_MCP_GPIO_18

NC_MCP_GPIO_18

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN
MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_R_C_PR
MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE
21

TP_MLB_RAM_SIZE

19

TP_PCI_C_BE_L<3>

17

PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N

17

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE
18

CRT_IG_B_COMP_PB

18

CRT_IG_HSYNC

NO_TEST=TRUE

NC_CRT_IG_B_COMP_PB
MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE
18

CRT_IG_VSYNC

NC_CRT_IG_VSYNC

TP_MCP_RGB_HSYNC

NC_MCP_RGB_HSYNC

18

TP_MCP_RGB_VSYNC

NC_MCP_RGB_VSYNC
MAKE_BASE=TRUE

TP_PCI_IRDY_L

NC_PCI_AD<31..15>
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_IRDY_L
MAKE_BASE=TRUE

C

TP_PCI_C_BE_L<1..0>

NC_PCI_C_BE_L<1..0>

19

TP_PCI_SERR_L

NC_PCI_SERR_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

19

TP_PCI_DEVSEL_L

NC_PCI_DEVSEL_L
NO_TEST=TRUE

NC_PCI_PERR_L
MAKE_BASE=TRUE

19

21

TP_LPC_DRQ0_L

19

TP_PCI_GNT1_L

NC_PCI_GNT1_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE

TP_PCI_INTW_L

MAKE_BASE=TRUE

19

TP_PCI_INTX_L

19

TP_PCI_INTY_L

NC_PCI_INTY_L

19

TP_PCI_INTZ_L

NC_PCI_INTZ_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE

19

TP_PCI_PAR

NC_LPC_DRQ0_L
NO_TEST=TRUE

NC_MCP_BUF_SIO_CLK
MAKE_BASE=TRUE

19

TP_PCI_STOP_L
TP_PCI_TRDY_L
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

15

TP_MEM_A_CLK2P

NC_MEM_A_CLK2P

NO_TEST=TRUE

15

TP_MEM_A_CLK2N

NC_MEM_A_CLK2N

17

TP_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6P

17

TP_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE6N

17

PCIE_EXCARD_PRSNT_L

NC_PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

TP_USB_10P

NC_USB_10P

20

USB_MINI_N

NC_USB_MINI_N

MAKE_BASE=TRUE
MAKE_BASE=TRUE

20

USB_MINI_P

NC_USB_MINI_P

20

USB_EXCARD_N

NC_USB_EXCARD_N

MAKE_BASE=TRUE
MAKE_BASE=TRUE

21

17

17

PCIE_CLK100M_EXCARD_N

17

EXCARD_CLKREQ_L

19

TP_PCI_AD<12..10>

19

TP_PCI_AD<8>

15

NC_MEM_B_CLK2P

NO_TEST=TRUE

15

TP_MEM_B_CLK2N

NC_MEM_B_CLK2N

MAKE_BASE=TRUE
MAKE_BASE=TRUE

16

TP_MEM_B_CLK5P

NC_MEM_B_CLK5P

16

TP_MEM_B_CLK5N

NC_MEM_B_CLK5N

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

B

UNUSED GMUX JTAG FROM MCP

NO_TEST=TRUE
17

GMUX_JTAG_TCK_L

17

GMUX_JTAG_TDO

NC_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE
NO_TEST=TRUE
19

GMUX_JTAG_TDI

NC_GMUX_JTAG_TDI

19

GMUX_JTAG_TMS

NC_GMUX_JTAG_TMS

MAKE_BASE=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NC_GMUX_JTAG_TDO

MAKE_BASE=TRUE

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_EXCARD_N
MAKE_BASE=TRUE

A

NO_TEST=TRUE

TP_MEM_B_CLK2P

NC_ODD_PWR_EN_L
MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXCARD_P
MAKE_BASE=TRUE

ODD_PWR_EN_L

NC_MEM_A_CLK5N

NC_USB_10N

20

USB_EXCARD_P

TP_MEM_A_CLK5N

NC_SB_A20GATE
MAKE_BASE=TRUE

20

NO_TEST=TRUE

NC_PE4_PRSNT_L
MAKE_BASE=TRUE

TP_USB_10N

NO_TEST=TRUE

NC_PE4_CLKREQ_L
MAKE_BASE=TRUE

20

16

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5P

TP_SB_A20GATE

NC_MEM_A_CLK5P

NO_TEST=TRUE

NC_PCIE_CLK100M_PE5N

21

C

NO_TEST=TRUE

TP_PCIE_CLK100M_PE5P

TP_PE4_PRSNT_L

TP_MEM_A_CLK5P

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE5N

17

16

NO_TEST=TRUE

17

TP_PE4_CLKREQ_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE

NO_TEST=TRUE

17

17

UNUSED MEMORY SIGNALS

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4P
MAKE_BASE=TRUE

B

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4N
MAKE_BASE=TRUE

17

NO_TEST=TRUE

NC_PCI_TRDY_L
MAKE_BASE=TRUE

17

NO_TEST=TRUE

NC_PCI_STOP_L
MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCI_RESET1_L
MAKE_BASE=TRUE

19

MAKE_BASE=TRUE
MCP HAS INTERNAL 15K PULL-DOWNS

NO_TEST=TRUE

NC_PCI_PAR
MAKE_BASE=TRUE

TP_PCI_RESET1_L

NO_TEST=TRUE

NC_USB_TPAD_P

NC_PCI_INTX_L
MAKE_BASE=TRUE

19

USB_TPAD_P

NC_PCI_INTW_L
MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_MCP_BUF_SIO_CLK

NC_MCP_PCI_GNT0_L

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCI_PERR_L

TP_PCI_GNT0_L

NO_TEST=TRUE

19

19

19

19

NO_TEST=TRUE

NC_USB_TPAD_N

NC_PCI_FRAME_L
MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCI_CLK1
MAKE_BASE=TRUE

TP_PCI_FRAME_L

NO_TEST=TRUE

NC_PCI_CLK0
MAKE_BASE=TRUE

19

NO_TEST=TRUE

MAKE_BASE=TRUE

19

TP_PCI_CLK1

NO_TEST=TRUE

18

TP_PCI_AD<31..15>

TP_PCI_CLK0

19

NO_TEST=TRUE

MAKE_BASE=TRUE

19

19

USB_TPAD_N

NO_TEST=TRUE

D

NO_TEST=TRUE

NC_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

NC_PCI_C_BE_L<3>
MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

20

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_N
MAKE_BASE=TRUE

17

NO_TEST=TRUE

NC_PCIE_EXCARD_D2R_P

NO_TEST=TRUE

20

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

17

NO_TEST=TRUE

NC_PCIE_PE4_D2RN

NO_TEST=TRUE

NC_MLB_RAM_SIZE
MAKE_BASE=TRUE

TP_PCIE_PE4_D2RN

MAKE_BASE=TRUE

NC_ENET_PWDWN_L
MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT
MAKE_BASE=TRUE

NC_ENET_INTR_L

18

17

1

NO_TEST=TRUE

NC_EXCARD_CLKREQ_L
MAKE_BASE=TRUE

NO_TEST=TRUE

SYNC_MASTER=K22

NC_PCI_AD<12..10>
MAKE_BASE=TRUE

A

UNUSED SIGNAL ALIAS

NC_PCI_AD<8>
MAKE_BASE=TRUE

SYNC_DATE=09/02/2009

PAGE TITLE

NO_TEST=TRUE
NO_TEST=TRUE

DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

051-7863
BRANCH

PAGE

8 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

SIGNAL ALIAS

2

1

Platform Reset Connections
LPC Reset (Unbuffered)

21

MXM_GOOD

TP_MLB_RAM_VENDOR

6

MAKE_BASE=TRUE

R981

D

103 19

R910
102 21

PM_SLP_S3_L

1

15

PM_SLPS3_BUF2_L

2

PLACEMENT_NOTE=Place close to U1400

LPC_RESET_L

33

1

2

5%
1/16W
MF-LF
402

6 49 50 70

MAKE_BASE=TRUE

5%
1/16W
MF-LF
402

IN

15
5%
1/16W
MF-LF
402

PLACEMENT_NOTE=Place close to U1400

PM_SLPS3_BUF1_L

2

OUT

51

SMC_LRESET_L

OUT

49

FW_RESET_L

OUT

41

MINI_RESET_L

OUT

34

PEG_RESET_L

OUT

87

PCA9557D_RESET_L

OUT

29

CARDREADER_PLT_RST_L

OUT

47

R983
33

1

(P50 HAS A 100K TO GROUND)

R911
1

D

DEBUG_RESET_L

2

5%
1/16W
MF-LF
402

73 94

MAKE_BASE=TRUE
1

R912
100K
5%
1/16W
MF-LF

PCIE Reset (Unbuffered)

2 402

R992
17

IN

PCIE_RESET_L

PEG Slot Support

C

PEG_CLK100M_P

IN

MAKE_BASE=TRUE

17

IN

PEG_CLK100M_N

17

IN

=PEG_R2D_C_P<0..15>

17

IN

=PEG_R2D_C_N<0..15>

17

OUT

=PEG_D2R_P<0..15>

OUT

=PEG_D2R_N<0..15>

IN

PEG_PRSNT_L

17

17

GPU_CLK100M_PCIE_P
GPU_CLK100M_PCIE_N
MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE

PEG_D2R_P<0..15>
MAKE_BASE=TRUE

PEG_D2R_N<0..15>
MAKE_BASE=TRUE

MXM_DETECT_L

OUT

87 102

0

OUT

87 102

OUT

102 86

OUT

102 86

IN

86 102

IN

86 102

OUT

MAKE_BASE=TRUE

2

5%
1/16W
MF-LF
402

R990
0

1

0

2

5%
1/16W
MF-LF
402

85

2

5%
1/16W
MF-LF
402

R971
1

2

5%
1/16W
MF-LF
402

R991
1

17

0

1

C

R993
0

1

2

5%
1/16W
MF-LF
402

R972
19

20 46

46

MEM_VTT_EN_R

IN

33

1

DDRVTT_EN

2

75 78

OUT

5%
1/16W
MF-LF
402

USB_EXTC_OC_L
MAKE_BASE=TRUE
USB_EXTD_OC_L

K22/K23 Use one GPIO for both ports 2&3 OC

NO STUFF
1

USB PORT 2 AND 3 (C AND D) SHARE OVER-CURRENT WITH PORT 2
PREVIOUSLY, PORT 3 HAD IT’S OWN BUT EFI MAPS THAT TO EXPRESSCARD
SEE RDAR://6250424

C973
0.47UF

2

10%
6.3V
CERM-X5R
402

R900

B

18

=DVI_HPD_GMUX_INT

HPLUG_DET2

1

MAKE_BASE=TRUE

20K

R925

2

5%
1/16W
MF-LF
402

103 19

IN

LPC_CLK33M_SMC_R

PLACEMENT_NOTE=Place close to U1400

1

33

2

5%
1/16W
MF-LF
402

B

LPC_CLK33M_SMC

OUT

103 49

LPC_CLK33M_LPCPLUS

OUT

103 51

PM_CLK32K_SUSCLK

OUT

103 49

R926
1

PLACEMENT_NOTE=Place close to U1400

33

2

5%
1/16W
MF-LF
402

R929

PCIE_FW_PRSNT_L
PCIE_MINI_PRSNT_L

103 21

OUT

17

OUT

17

IN

PM_CLK32K_SUSCLK_R

1
PLACEMENT_NOTE=Place close to U1400

22

2

5%
1/16W
MF-LF
402

MCP_CPUVDD_EN WILL ASSERT AFTER MCP_PS_PWRGD IS UP
R930
21

IN

MCP_CPUVDD_EN

1
PLACEMENT_NOTE=Place close to U1400

A

18

=MCP_MII_RXER

18

=MCP_MII_COL

18

=MCP_MII_CRS

22

2

MCP_CPU_VLD

OUT

21

5%
1/16W
MF-LF
402

MCP_MII_NU
MAKE_BASE=TRUE

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE
1

Signal Aliases

R955
47K

5%
1/16W
MF-LF
2 402

DRAWING NUMBER

Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

051-7863
BRANCH

PAGE

9 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

CRITICAL

4

PPCPU_VTT_OUT_LEFT

3

CRITICAL

J1000

WOLFDALE-SKT-1
=PPVTT_S0_CPU

BGA-NOHSK

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14
100 14
100 14

C

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

100 14

BI

BI
BI
BI

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

REQ_0*
REQ_1*
REQ_2*
REQ_3*
REQ_4*

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>

K4
J5
M6
K6
J6

ADDR GROUP0
CONTROL

BI

100 14

A_3*
A_4*
A_5*
A_6*
A_7*
A_8*
A_9*
A_10*
A_11*
A_12*
A_13*
A_14*
A_15*
A_16*
ADSTB_0*

AB6 A_17*
W6 A_18*
Y6 A_19*
Y4 A_20*
AA4 A_21*
AD6 A_22*
AA5 A_23*
AB5 A_24*
AC5 A_25*
AB4 A_26*
AF5 A_27*
AF4 A_28*
AG6 A_29*

ADS*
BNR*
BPRI*

D2
C2
G8

FSB_ADS_L
FSB_BNR_L
FSB_BPRI_L

DEFER*
DRDY*
DBSY*

G7
C1
B2

FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L

BR_0*

F3

FSB_BREQ0_L

IERR*
INIT*

AB2
P3

LOCK*
RESET*
RS_0*
RS_1*
RS_2*
TRDY*

C3
G23
B3
F5
A3
E3

BI
BI

14 100

IN

14 100

IN

14 100

BI

14 100

BI

14 100

1

R1003
62

1

PPCPU_VTT_OUT_RIGHT

R1004

1

R1000
62

5%
1/16W
MF-LF
2 402

14 100

PLACE W/ A TESTPOINT W/ A GND NEARBY
IN

FSB_LOCK_L

BI

FSB_HIT_L
FSB_HITM_L

HIT*
HITM*

D4
E4

A20M*
FERR_PBE*
IGNNE*

K3
R3
N2

CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L

STPCLK*
LINT0
LINT1
SMI*

M3
K1
L1
P2

CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L

BCLK_0
BCLK_1

F28
G28

FSB_CLK_CPU_P
FSB_CLK_CPU_N

10 11 12

200

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

BI

CPU_INIT_L

14 100

14 100

IN
IN
IN

13 14 100

14 100
14 100

IN

14 100

IN

14 100

BI

14 100

BI

14 100

IN

14 100

PPCPU_VTT_OUT_RIGHT

10 11 12

R1001
62

14 100

IN

14 100

IN

14 100

IN

14 100

IN

14 100

IN

14 100

IN

14 100

100 14

BI

100 14

BI

100 14

BI

5%
1/16W
MF-LF
2 402
OUT

IN

FSB_D_L<0>
FSB_D_L<1>
100 14 BI
FSB_D_L<2>
100 14 BI
FSB_D_L<3>
100 14 BI
FSB_D_L<4>
100 14 BI
FSB_D_L<5>
100 14 BI
FSB_D_L<6>
100 14 BI
FSB_D_L<7>
100 14 BI
FSB_D_L<8>
100 14 BI
FSB_D_L<9>
100 14 BI
FSB_D_L<10>
100 14 BI
FSB_D_L<11>
100 14 BI
FSB_D_L<12>
100 14 BI
FSB_D_L<13>
100 14 BI
FSB_D_L<14>
100 14 BI
FSB_D_L<15>
100 14 BI
FSB_DINV_L<0>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>

B4
C5
A4
C6
A5
B6
B7
A7
A10
A11
B10
C11
D8
B12
C12
D11
A8
C8
B9

BGA-NOHSK
CPU
D_0* (2 OF 7) D_32*
D_33*
D_1*
D_34*
D_2*
D_35*
D_3*
D_36*
D_4*
D_37*
D_5*
D_38*
D_6*
D_39*
D_7*
D_40*
D_8*
D_41*
D_9*
D_42*
D_10*
D_43*
D_11*
D_44*
D_12*
D_45*
D_13*
D_14*
D_46*
D_15*
D_47*
DBI_0*
DBI_2*
DSTBN_0*
DSTBN_2*
DSTBP_0
DSTBP_2

G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G20
G19

FSB_D_L<32> BI 14 100
FSB_D_L<33> BI 14 100
FSB_D_L<34> BI 14 100
FSB_D_L<35> BI 14 100
FSB_D_L<36> BI 14 100
FSB_D_L<37> BI 14 100
FSB_D_L<38> BI 14 100
FSB_D_L<39> BI 14 100
FSB_D_L<40> BI 14 100
FSB_D_L<41> BI 14 100
FSB_D_L<42> BI 14 100
FSB_D_L<43> BI 14 100
FSB_D_L<44> BI 14 100
FSB_D_L<45> BI 14 100
FSB_D_L<46> BI 14 100
FSB_D_L<47> BI 14 100
FSB_DINV_L<2>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>

FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
100 14 BI
FSB_D_L<20>
100 14 BI
FSB_D_L<21>
100 14 BI
FSB_D_L<22>
100 14 BI
FSB_D_L<23>
100 14 BI
FSB_D_L<24>
100 14 BI
FSB_D_L<25>
100 14 BI
FSB_D_L<26>
100 14 BI
FSB_D_L<27>
100 14 BI
FSB_D_L<28>
100 14 BI
FSB_D_L<29>
100 14 BI
FSB_D_L<30>
100 14 BI
FSB_D_L<31>
100 14 BI
FSB_DINV_L<1>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>

G9
F8
F9
E9
D7
E10
D10
F11
F12
D13
E13
G13
F14
G14
F15
G15
G11
G12
E12

D_16*
D_17*
D_18*
D_19*
D_20*
D_21*
D_22*
D_23*
D_24*
D_25*
D_26*
D_27*
D_28*
D_29*
D_30*
D_31*
DBI_1*
DSTBN_1*
DSTBP_1

D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17

FSB_D_L<48> BI 14 100
FSB_D_L<49> BI 14 100
FSB_D_L<50> BI 14 100
FSB_D_L<51> BI 14 100
FSB_D_L<52> BI 14 100
FSB_D_L<53> BI 14 100
FSB_D_L<54> BI 14 100
FSB_D_L<55> BI 14 100
FSB_D_L<56> BI 14 100
FSB_D_L<57> BI 14 100
FSB_D_L<58> BI 14 100
FSB_D_L<59> BI 14 100
FSB_D_L<60> BI 14 100
FSB_D_L<61> BI 14 100
FSB_D_L<62> BI 14 100
FSB_D_L<63> BI 14 100
FSB_DINV_L<3>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>

100 14

100 CPU_IERR_L

FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L

WOLFDALE-SKT-1
6 50 55 71

14 100

1

SB

100 14

L5
FSB_A_L<3>
P6
FSB_A_L<4>
M5
FSB_A_L<5>
L4
FSB_A_L<6>
M4
FSB_A_L<7>
R4
FSB_A_L<8>
T5
FSB_A_L<9>
U6
FSB_A_L<10>
T4
FSB_A_L<11>
U5
FSB_A_L<12>
U4
FSB_A_L<13>
V5
FSB_A_L<14>
V4
FSB_A_L<15>
W5
FSB_A_L<16>
FSB_ADSTB_L<0> R6

CLK

BI

ADDR GROUP1

D

100 14

1

10 11 12

J1000
CPU
(1 OF 7)

2

14 100

AG4 A_30*
AG5 A_31*
AH4 A_32*
AH5 A_33*
AJ5 A_34*

100 14

BI

100 14

BI

100 14

BI

BI

100 14

BI

100 14

BI

100 14

BI

D_48*
D_49*
D_50*
D_51*
D_52*
D_53*
D_54*
D_55*
D_56*
D_57*
D_58*
D_59*
D_60*
D_61*
D_62*
D_63*
DBI_3*
DSTBN_3*
DSTBP_3

D

BI

14 100

BI

14 100

BI

14 100

C

BI

14 100

BI

14 100

BI

14 100

AJ6 A_35*
AD5 ADSTB_1*

CPU GTLREF
12 11 10

PPCPU_VTT_OUT_LEFT
GTLREF VOLTAGE SHOULD BE 0.635 * VTT
(63.5% OF 1.2V) = 0.762V

1

R1040
57.6

1%
1/16W
MF-LF
2 402

B

1

R1041
100

1%
1/16W
MF-LF
2 402

1

10

2

1%
1/16W
MF-LF
402

1

12 11 10

B

R1042
CPU_GTLREF_DIV0

C1040

CPU_GTLREF0

11 29 100

CPU_GTLREF1

11 29 100

NOSTUFF
1

1UF

C1041
220PF

10%
6.3V
2 CERM
402

10%
50V
2 X7R-CERM
402

PPCPU_VTT_OUT_LEFT
1

R1043
57.6

1%
1/16W
MF-LF
2 402

R1045
CPU_GTLREF_DIV1

1

R1044
100

1%
1/16W
MF-LF
2 402

1

C1042
1UF

1

10

1%
1/16W
MF-LF
402

2

NOSTUFF
1

C1043
220PF

10%
50V
2 X7R-CERM
402

10%
2 6.3V
CERM
402

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

CPU FSB
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

10 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

7

6

5

4

3

2

PPCPU_VTT_OUT_RIGHT

R1100
(TMS)
12 11 10

D

12 6

1

PPCPU_VTT_OUT_RIGHT

=PPVTT_S0_FSB_CPU

R11291

R11301

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

51

51

5%
1/16W
MF-LF
402 2

51

51

5%
1/16W
MF-LF
402 2

R1102

5%
1/16W
MF-LF
402 2

(TCK) 1

51

2

5%
1/16W
MF-LF
402

CRITICAL

CPU_PROCHOT_L
100 50 14

PM_THRMTRIP_L

OUT

AL1
AK1
G5

THERMDA
THERMDC
PECI

AL2
M2

PROCHOT*
THERMTRIP*

H2
H1
F2
G10

GTLREF1
GTLREF0
FC5/GTLREF2
FC38/GTLREF3

A13
T1
G2
R1
B13
F6

COMP_0
COMP_1
COMP_2
COMP_3
COMP_8
IMPSEL

J1000
WOLFDALE-SKT-1

PWRGOOD
DPRSTP*
DPSLP*
SLP*
PSI*
VRDSEL

N1
T2
P1
L2
Y3
AL3 NC

CPU_PWRGD
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_CPUSLP_L
CPU_PSI_L

G29
H30
G30

CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>

IN

13 14 100

OUT

14 100

OUT

14 100

OUT

14 100

OUT

71

OUT

14 100

OUT

14 100

OUT

14 100

100 13
100 13
100 13
100 13
100 13

100 29 10
100 29 10

100 11

C

100 11
100 11
100 11
100 11

CPU_GTLREF1
CPU_GTLREF0

CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_COMP<8>
CPU_PD_IMPSEL

BSEL_0
BSEL_1
BSEL_2
SKTOCC*
MSID_1
MSID_0
BOOTSELECT

IPU

AE8 NC
V1 NC
W1 NC
Y1

CPU_XDP_TCK
IN CPU_XDP_TDI
OUT CPU_XDP_TDO
IN CPU_XDP_TMS
IN CPU_XDP_TRST_L

AE1
AD1
AF1
AC1
AG1

IN

CPU_TESTHI_M

CPU_TESTHI_0
CPU_TESTHI_1
CPU_TESTHI_2_7
CPU_BOOT
1

R1109
51

5%
1/16W
MF-LF
2 402

1

R1151

CPU_TESTHI_10

51
5%
1/16W
MF-LF
2 402

U1
W2

FROM 975X PDG: IMPSEL
0 - 51 PD TO GND
(SELECTS 50 OHM SYSTEM IMPEDANCE)

100 13 11

BI

100 13 11

BI

100 13 11

BI

100 13 11

BI

100 13 11

BI

100 13 11

BI

CPU_XDP_BPM_L<0>
CPU_XDP_BPM_L<1>
CPU_XDP_BPM_L<2>
CPU_XDP_BPM_L<3>
CPU_XDP_BPM_L<4>
CPU_XDP_BPM_L<5>
100 13 11

BI

100 13 11

BI

100 13 11

BI

100 13 11

BI

28 13

IN

CPU_XDP_BPMB<0>
CPU_XDP_BPMB<1>
CPU_XDP_BPMB<2>
CPU_XDP_BPMB<3>

XDP_DBRESET_L

12 11 10

CPU BPM TERM

PPCPU_VTT_OUT_RIGHT

B
1

R1190 1R1191 1R1192 1R1193 1R1194 1R1195
51

51

5%
1/16W
MF-LF
2 402

100 13 11
100 13 11
100 13 11
100 13 11
100 13 11
100 13 11

100 11
100 11
100 11
100 11
100 11

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

51

5%
1/16W
MF-LF
2 402

51

5%
1/16W
MF-LF
2 402

(ALSO WRITTEN AS BPM2)

R1120
49.9

1%
1/16W
MF-LF
2 402

1

R1121 1R1122
49.9

1%
1/16W
MF-LF
2 402

49.9

1%
1/16W
MF-LF
2 402

1

R1123
49.9

1%
1/16W
MF-LF
2 402

1

R1128
24.9

KENTSFIELD CPU SUPPORT

1%
1/16W
MF-LF
2 402

G6
N4
P5
AC4
AE4
F29
AH2
V2
N5
E7
AE6
D16
A20
E23
F23
D14
E6
E5
J3
D1

TESTHI_0
TESTHI_1
TESTHI_2
TESTHI_3
TESTHI_4
TESTHI_5
TESTHI_6
TESTHI_7
TESTHI_10

AJ2
AJ1
AD2
AG2
AF2
AG3

BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*

G1
C9
G4
G3

AK3
AJ3

C

PM_PGOOD_PVCORE_CPU

IN

70 71

B

5%
1/16W
MF-LF
2 402

CPU_XDP_BPM_L<0>
CPU_XDP_BPM_L<1>
CPU_XDP_BPM_L<2>
CPU_XDP_BPM_L<3>
CPU_XDP_BPM_L<4>
CPU_XDP_BPM_L<5>

CPU BPMB TERM
1

RSVD_G6
RSVD_N4
RSVD_P5
RSVD_AC4
RSVD_AE4
RSVD_F29
RSVD_AH2
FC27/BPMB0*
FC41/BPMB1*
RSVD_V2
TESTHI_9/BPMB2*
RSVD_N5
RSVD_E7
TESTHI_8/BPMB3*
RSVD_AE6
DBR*
RSVD_D16
ITPCLK_0
RSVD_A20
ITPCLK_1
RSVD_E23
RSVD_F23
RSVD_D14
RSVD_E6
RSVD_E5
RSVD_J3
RSVD_D1

FC28/TDO_M
TESTHI_12/TDI_M

51

PPCPU_VTT_OUT_LEFT

CPU_COMP<8>
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>

A

51

J2
AK6
E24
H29
AE3
A24
E29
U2
U3
J16
H15
H16
J17
H4
AD3
AB3
AA2
AM6

F26
W3
F25
G25
G27
G26
G24
F24
H5

AC2
NC

BGA-NOHSK
CPU
(4 OF 7)

FC3
FC8
FC10
FC15
FC18
FC23
FC26
FC29
FC30
FC31
FC32
FC33
FC34
FC35
FC36
FC37
FC39
FC40

TCK
TDI
TDO
TMS
TRST*

JTAG

108 55

CPU_THERMD_P
OUT CPU_THERMD_N
CPU_PECI_L
OUT
IN

BGA-NOHSK
CPU
(3 OF 7)

PWR MGMT

108 55

108 55

OUT

5%
1/16W
MF-LF
402

R11331 R11321 R11351

WOLFDALE-SKT-1

130

PLACE TMS/TMI/TCK TERMINATION
WITHIN 38MM (1.5IN) OF THE CPU

2

J1000

NOSTUFF

R1150

1%
1/16W
MF-LF
2 402

51

XDP/ITP

PPCPU_VTT_OUT_RIGHT

1

100 50 14

1

CRITICAL

THERMAL

12 11 10

D

R1101

PPCPU_VTT_OUT_LEFT

51

10 11 12

2

5%
1/16W
MF-LF
402

(TDI)
12 11 10

51

1

TEST
RESERVED

8

100 13 11

BI

100 13 11

BI

100 13 11

BI

100 13 11

BI

10 11 12

1

R1180 1R1181 1R1182 1R1183
51

5%
1/16W
MF-LF
2 402

51
5%
1/16W
MF-LF
2 402

51
5%
1/16W
MF-LF
2 402

51
5%
1/16W
MF-LF
2 402

CPU_XDP_BPMB<3>
CPU_XDP_BPMB<2>
CPU_XDP_BPMB<1>
CPU_XDP_BPMB<0>

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

CPU TEST & MISC.
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

11 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

THIS IS FOR OLDER CPU SUPPORT
WILL PLACE FILTER BUT NOT CONNECT FOR WOLFDALE

6

CONROE
~125MA CURRENT

=PPVCORE_S0_CPU
12 11 6

L1210

=PPVTT_S0_FSB_CPU
1

0

1

2

12 6

VID PULLUPS WITH VREG
100 71
OUT CPU_VID<0>
100 71
OUT CPU_VID<1>
100 71
OUT CPU_VID<2>
100 71
OUT CPU_VID<3>
100 71
OUT CPU_VID<4>
100 71
OUT CPU_VID<5>
100 71
OUT CPU_VID<6>
100 71
OUT CPU_VID<7>
12 CPU_VCCA
12 CPU_VSSA
=PP1V5_S0_CPU_VCCPLL
12 CPU_VCCIOPLL

108 53

OUT

100 71

OUT

CPU_VCC_SENSE
CPU_VCC_PKG_SENSE_P
12

100 71

12 11 6

OUT

CPU_VID_SELECT

11 10
12

11 10
12

AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
A23
B23
C23
D23

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
VID_7
VCCA
VSSA
VCCIOPLL
VCCPLL

AN3
AN5

VCC_SENSE
VCC_MB_REGULATION

AN7

VID_SELECT

PPCPU_VTT_OUT_RIGHT
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

J19
J20
J21
J22
J23
J24

CRITICAL

WOLFDALE-SKT-1
BGA-NOHSK
CPU
(7 OF 7)

VSS_SENSE
VSS_MB_REGULATION

A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30

VTT_A25
VTT_A26
VTT_A27
VTT_A28
VTT_A29
VTT_A30
VTT_B25
VTT_B26
VTT_B27
VTT_B28
VTT_B29
VTT_B30
VTT_C25
VTT_C26
VTT_C27
VTT_C28
VTT_C29
VTT_C30
VTT_D25
VTT_D26
VTT_D27
VTT_D28
VTT_D29
VTT_D30

AA1
J1
F27

VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL

POWER

VCCP

PPCPU_VTT_OUT_LEFT
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

TP_VTT_SEL

B
AC8
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD8
AE11
AE12
AE14
AE15
AE18
AE19
AE21
AE22
AE23
AE9
AF11
AF12
AF14
AF15
AF18
AF19

A

CPU_VCCIOPLL

VCCP

J25
J26
J27
J28
J29
J30
J8
J9
K23
K24
K25
K26
K27
K28
K29
K30
K8
L8
M23
M24
M25
M26
M27
M28
M29
M30
M8
N23
N24
N25
N26
N27
N28
N29
N30
N8
P8
R8
T23
T24
T25
T26
T27
T28
T29
T30
T8
U23
U24
U25
U26
U27
U28
U29
U30
U8
V8
W23
W24
W25
W26
W27
W28
Y27
Y26
Y25
Y24
Y23
W8
W30
Y8
Y30
Y29
Y28
W29
AL15
AL8
AL11
AL12
AL14

0

1

CPU_VCCA 12

2

5%
1/10W
MF-LF
603

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

NOSTUFF

C1211

1

1UF
1

C1210

1

22UF

C1213

NOSTUFF

10%
6.3V
CERM 2
402

C1212

1

1UF

10%
2 6.3V
CERM
402

10uF

20%
2 6.3V
X5R
603

20%
6.3V
2 CERM-X5R
805-3

CPU_VSSA 12
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

VCC PLL DECOUPLING
12 6

=PP1V5_S0_CPU_VCCPLL

1

C1280

12 11 10

C1281

1

10UF

0.01UF

10%
2 16V
CERM
402

20%
2 6.3V
X5R
603

PPCPU_VTT_OUT_LEFT

PPCPU_VTT_OUT_RIGHT

1

C1200

1

0.1UF

10 11 12

C1201
0.1UF

20%
2 10V
CERM
402

20%
10V
2 CERM
402

FSB VTT DECOUPLING
12 11 6

=PPVTT_S0_FSB_CPU

1

C1226 1 C1234 1 C1235
0.1UF

0.1UF

20%
10V
2 CERM
402

1

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

C1236 1 C1237 1 C1238
0.1UF

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

J1000

J1000
WOLFDALE-SKT-1

A12
A15
A18
A2
A21
A6
A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE5
AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF3
AF30
AF6
AF7
AG10
AG13
AG16
AL7

BGA-NOHSK
CPU
(5 OF 7)

GND

GND

GND

AG17
AG20
AG23
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AM24
AM27
AM28
AM4
AN1
AN10
AN13
AN16
AN17
AH7
AJ7

BGA-NOHSK
CPU
(6 OF 7)

AN2
AN20
AN23
AN24
AN27
AN28
B1
B11
B14
B17
B20
B24
B5
B8
C10
C13
C16
C19
C22
C24
C4
C7
D12
D15
D18
D21
D24
D3
D5
D6
D9
E11
E14
E17
E2
E20
E25
E26
E27
E28
E8
F10
F13
F16
F19
F22
F4
F7
H10
H11
H12
H13
H14
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3

GND

GNDGND

D

H6
H7
H8
H9
J4
J7
K2
K5
K7
L23
L24
L25
L26
L27
L28
L29
L3
L30
L6
L7
M1
M7
N3
N6
N7
P23
P24
P25
P26
P27
P28
P29
P30
P4
P7
R2
R23
R24
R25
R26
R27
R28
R29
R30
R5
R7
T3
T6
T7
U7
V23
V24
V25
V26
V27
V28
V29
V3
V30
V6
V7
W4
W7
Y2
Y5
Y7

C

B

VCCP CORE DECOUPLING
(SEE VREG PAGE)

SYNC_MASTER=K22
12 11 10

SYNC_DATE=09/02/2009

CPU POWER, GND, DECAPS
DRAWING NUMBER

1

R1200

Apple Inc.

680

5%
1/16W
MF-LF
2 402
12

A

PAGE TITLE

PPCPU_VTT_OUT_RIGHT

AF21
AF22
AF8
AF9
AG11
AG12
AG14
AG15
AG18
AG19
AG21
AG22
AG25
AG26
AG27
AG28
AG29
AG30
AG8
AG9
AH11
AH12
AH14
AH15
AH18
AH19
AH21
AH22
AH25
AH26
AH27
AH28
AH29
AH30
AH8
AH9
AJ8
AJ9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AK8
AK9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26

VCCP

CPU_VCCA_FLT

CRITICAL

WOLFDALE-SKT-1

12

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

R1211

J1000

=PPVTT_S0_FSB_CPU

2

5%
1/10W
MF-LF
603

VCCP

TP_CPU_VSS_SENSE AN4
CPU_VCC_PKG_SENSE_N
AN6

C

AN29
AN30
AN8
AN9
J10
J11
J12
J13
J14
J15
J18

AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
AN25
AN26

0603

D

CRITICAL

R1210

FERR-120-OHM-0.2A

CPU_VID_SELECT

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

12 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

MCP79-specific pinout
6
6

=PP3V3_S0_XDP
=PPVTT_S0_XDP

100 11
100 11

100 11
100 11

BI
BI

BI
IN

100 11

IN

100 11

IN

C
IN

100 11

IN

100 11

IN

100 11

IN

XDP

R1399
100 14 11

IN

CPU_PWRGD

1K
1

J1300
F-ST-SM

CPU_XDP_BPM_L<5>
CPU_XDP_BPM_L<4>

OBSFN_A0
OBSFN_A1

CPU_XDP_BPM_L<3>
CPU_XDP_BPM_L<2>

OBSDATA_A0
OBSDATA_A1

CPU_XDP_BPM_L<1>
CPU_XDP_BPM_L<0>

OBSDATA_A2
OBSDATA_A3
OBSFN_B0
OBSFN_B1

CPU_XDP_BPMB<3>
CPU_XDP_BPMB<2>

OBSDATA_B0
OBSDATA_B1

CPU_XDP_BPMB<1>
CPU_XDP_BPMB<0>

OBSDATA_B2
OBSDATA_B3

XDP_OBS20

5%
1/16W
MF-LF
402
19

IN

21

OUT

106 52 21

BI

106 52 21

BI

100 11

OUT

PM_LATRIGGER_L
JTAG_MCP_TCK

5%
1/16W
MF-LF
402 2

LTH-030-01-G-D-A-TR

XDP_PWRGD

2

1

62

2

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1
100 11

R1316

CRITICAL

54.9
1%
1/16W
MF-LF
402

XDP

XDP_CONN

XDP

R1315 1

PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3

SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK

SDA
SCL
TCK1
TCK0

CPU_XDP_TCK

NC

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

1

1

0.1uF
10%
16V
X5R
402

JTAG_MCP_TDO
JTAG_MCP_TRST_L

OBSDATA_C0
OBSDATA_C1

MCP_DEBUG<0>
MCP_DEBUG<1>

BI

19

BI

19

OBSDATA_C2
OBSDATA_C3

MCP_DEBUG<2>
MCP_DEBUG<3>

BI

19

OBSFN_D0
OBSFN_D1

JTAG_MCP_TDI
JTAG_MCP_TMS

OUT

21

OUT

21

OBSDATA_D0
OBSDATA_D1

MCP_DEBUG<4>
MCP_DEBUG<5>

BI

19

BI

19

OBSDATA_D2
OBSDATA_D3

MCP_DEBUG<6>
MCP_DEBUG<7>

BI

19

C1301
0.1uF

2

2

10%
16V
X5R
402

IN

21

OUT

21

BI

BI

FSB_CLK_ITP_P
ITPCLK/HOOK4
FSB_CLK_ITP_N
ITPCLK#/HOOK5
VCC_OBS_CD
100 XDP_CPURST_L
RESET#/HOOK6
XDP_DBRESET_L
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
CPU_XDP_TDO
TDO
CPU_XDP_TRST_L
TRSTn
CPU_XDP_TDI
TDI
CPU_XDP_TMS
TMS
XDP_PRESENT#
XDP
XDP

XDP

C1300

OBSFN_C0
OBSFN_C1

R1301

19

C

19

IN

14 100

IN

14 100

XDP

R1303
1K
1

OUT

11 28

IN

11 100

OUT

11 100

OUT

11 100

OUT

11 100

2
5%
1/16W
MF-LF
402

FSB_CPURST_L

IN

10 14 100

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1

51
5%
1/16W
MF-LF
402 2

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

eXtended Debug Port (XDP)
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

13 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP7A
BGA
(1 OF 11)
BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

C

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

25 22 14 6

=PP1V05_S0_MCP_FSB

R1410

1

1

62

B

100 50 11

IN

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

100 10

BI

R1416

5%
1/16W
MF-LF
2 402

100 11

IN

100 11

IN

100 11

IN

R1421

R1422

470

470

470

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

2

OUT

100 10

2

AE36
AK35

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

100 50 11

100 10

R1420

CPU_DSTBP3*
CPU_DSTBN3*
CPU_DBI3*

OUT

100 10

100 10

1

M39
M41
J41

108 55

100 10

1

FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>

100 10

100 10

100 10

1

CPU_DSTBP2*
CPU_DSTBN2*
CPU_DBI2*

FSB_ADSTB_L<0>
FSB_ADSTB_L<1>

CPU_PECI_MCP
CPU_PROCHOT_L
CPU_FERR_L

IN

CPU_BSEL<2>
CPU_BSEL<1>
CPU_BSEL<0>

CPU_A3*
CPU_A4*
CPU_A5*
CPU_A6*
CPU_A7*
CPU_A8*
CPU_A9*
CPU_A10*
CPU_A11*
CPU_A12*
CPU_A13*
CPU_A14*
CPU_A15*
CPU_A16*
CPU_A17*
CPU_A18*
CPU_A19*
CPU_A20*
CPU_A21*
CPU_A22*
CPU_A23*
CPU_A24*
CPU_A25*
CPU_A26*
CPU_A27*
CPU_A28*
CPU_A29*
CPU_A30*
CPU_A31*
CPU_A32*
CPU_A33*
CPU_A34*
CPU_A35*
CPU_ADSTB0*
CPU_ADSTB1*

AC38
AA33
AE38
AC37
AC39

CPU_REQ0*
CPU_REQ1*
CPU_REQ2*
CPU_REQ3*
CPU_REQ4*

AD42
AD43
AE40
AL32
AD39
AD41
AB42
AD40
AC43
AE41

CPU_ADS*
CPU_BNR*
CPU_BR0*
CPU_BR1*
CPU_DBSY*
CPU_DRDY*
CPU_HIT*
CPU_HITM*
CPU_LOCK*
CPU_TRDY*

E41
AJ41
AG43
AH40

CPU_PECI
CPU_PROCHOT*
CPU_THERMTRIP*
CPU_FERR*

F42
D42
F41

Y41
Y43
Y40
W42
Y42
Y39
V42
W41
T41
T43
T42
T39
U41
R41
P42
R42
AA38
AA35
AA36
AA37
AA34
W33
W34
W35
W38
U33
U34
U35
U36
U37
R33
U38
R35
R34
P35
N34
R38
R37
N33
R39
N36
N38
L37
L38
L39
J37
J38
J39
H40
L42
P41
M40
N40
N41
K42
M42
M43
L41
H42
H41
J40
K41
H43
H39

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

CPU_BPRI*
CPU_DEFER*

AA41
AA40

FSB_BPRI_L
FSB_DEFER_L

OUT

10 100

OUT

10 100

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

G42
G41

FSB_CLK_CPU_P
FSB_CLK_CPU_N

OUT

10 100

OUT

10 100

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

AL43
AL42

FSB_CLK_ITP_P
FSB_CLK_ITP_N

OUT

13 100

OUT

13 100

BCLK_OUT_NB_P
BCLK_OUT_NB_N

AL41
AK42

100 FSB_CLK_MCP_P

BCLK_IN_N
BCLK_IN_P

AK41
AJ40

CPU_A20M*
CPU_IGNNE*
CPU_INIT*
CPU_INTR
CPU_NMI
CPU_SMI*

AF41
AH39
AH42
AF42
AG41
AH41

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L

CPU_PWRGD
CPU_RESET*

AH43
H38

CPU_PWRGD
FSB_CPURST_L

AM33
AN33
AM32 NC
AG42
AN32

CPU_DSTBP1*
CPU_DSTBN1*
CPU_DBI1*

N37
L36
N35

AB35
AE37
AC33
AC35
AC34
AE35
AE34
AG39
AE33
AG38
AG37
AF35
AG35
AG34
AJ34
AG33
AJ38
AJ37
AJ35
AL37
AJ36
AL39
AL38
AJ33
AL35
AL34
AN37
AL33
AN38
AN35
AN36
AR39
AN34

CPU_D0*
CPU_D1*
CPU_D2*
CPU_D3*
CPU_D4*
CPU_D5*
CPU_D6*
CPU_D7*
CPU_D8*
CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D16*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D20*
CPU_D21*
CPU_D22*
CPU_D23*
CPU_D24*
CPU_D25*
CPU_D26*
CPU_D27*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*
CPU_D40*
CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D54*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
CPU_D60*
CPU_D61*
CPU_D62*
CPU_D63*

CPU_DSTBP0*
CPU_DSTBN0*
CPU_DBI0*

FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>

FSB_ADS_L
FSB_BNR_L
BI
FSB_BREQ0_L
BI
100 FSB_BREQ1_L
FSB_DBSY_L
BI
FSB_DRDY_L
BI
FSB_HIT_L
BI
FSB_HITM_L
BI
FSB_LOCK_L
IN
FSB_TRDY_L
OUT

100 10

PM_THRMTRIP_L

BI

100 10

62

5%
1/16W
MF-LF
402 2

BI

100 10

W39
W37
V35

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<10>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>

BI

100 10

T40
U40
V41

FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>

BI

100 10

100 10

FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>

FSB

D

100 10

CPU_BSEL2
CPU_BSEL1
CPU_BSEL0

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

10 100

BI

D

C

B

10 100

100 FSB_CLK_MCP_N

Loop-back clock for delay matching.

R1430

1

1

R1435

49.9

49.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

2

2

100 10

OUT

100 10

OUT

100 10

OUT

FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>

25

206
20
29
15

mA
mA
mA
mA

100 MCP_BCLK_VML_COMP_VDD

100 MCP_CPU_COMP_VCC

R1431

1

R1436
49.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

2

2

V1P1_DLLDLCELL_AVDD
V1P1_PLL_MCLK
V1P1_PLL_FSB
V1P1_PLL_CPU

AM43
AM42

100 MCP_CPU_COMP_GND

49.9

AG27
AH27
AG28
AH28
AM39
AM40

100 MCP_BCLK_VML_COMP_GND

1

CPU_RS0*
CPU_RS1*
CPU_RS2*

PP1V05_S0_MCP_PLL_FSB

270 mA (A01)

A

AC41
AB41
AC42

BCLK_VML_COMP_VDD
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_COMP_GND

CPU_SLP*
CPU_DPSLP*
CPU_DPWR*
CPU_STPCLK*
CPU_DPRSTP*

OUT

10 100

OUT

10 100

=PP1V05_S0_MCP_FSB

OUT

10 100

OUT

10 100

OUT

10 100

OUT

10 100

OUT

10 13 100

FSB_CPUSLP_L
CPU_DPSLP_L

OUT

11 100

OUT

11 100

CPU_STPCLK_L
CPU_DPRSTP_L

OUT

10 100

OUT

11 100

7

R1440
150

2

5%
1/16W
MF-LF
402

SYNC_MASTER=K22
OUT

11 13 100

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP CPU Interface
DRAWING NUMBER

Apple Inc.

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

BRANCH

PAGE

14 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

6 14 22 25

NO STUFF
1

6

5

4

3

2

1

7

6

5

4

3

2

OMIT

OMIT

U1400

U1400

MCP7A

C

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33
101 33
101 33

BI
BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33
101 33

B

BI

BI
BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

OUT

101 33

OUT

101 33

OUT

101 33

OUT

101 33

OUT

101 33

OUT

101 33

OUT

101 33

OUT

MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5
AN10
AR5
AU6
AV5
AU7
AU8
AW9
AP11
AW6
AY5
AU9
AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

AN5
AU5
AR10
AN13
AN27
AW29
AV35
AR34

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

MEMORY PARTITION 0

D

101 33

BGA
(2 OF 11)
MDQ0_63
MDQS0_7_P
MDQ0_62
MDQS0_7_N
MDQS0_6_P
MDQ0_61
MDQS0_6_N
MDQ0_60
MDQ0_59
MDQS0_5_P
MDQ0_58
MDQS0_5_N
MDQS0_4_P
MDQ0_57
MDQ0_56
MDQS0_4_N
MDQ0_55
MDQS0_3_P
MDQS0_3_N
MDQ0_54
MDQS0_2_P
MDQ0_53
MDQS0_2_N
MDQ0_52
MDQ0_51
MDQS0_1_P
MDQ0_50
MDQS0_1_N
MDQS0_0_P
MDQ0_49
MDQS0_0_N
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MRAS0*
MDQ0_42
MCAS0*
MDQ0_41
MWE0*
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MBA0_2
MDQ0_34
MBA0_1
MDQ0_33
MBA0_0
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MA0_14
MDQ0_26
MA0_13
MDQ0_25
MA0_12
MDQ0_24
MA0_11
MDQ0_23
MA0_10
MDQ0_22
MA0_9
MDQ0_21
MA0_8
MDQ0_20
MA0_7
MDQ0_19
MA0_6
MDQ0_18
MA0_5
MDQ0_17
MA0_4
MDQ0_16
MA0_3
MDQ0_15
MA0_2
MDQ0_14
MA0_1
MDQ0_13
MA0_0
MDQ0_12
MDQ0_11
MDQ0_10
MEMORY
MDQ0_9
CONTROL
MDQ0_8
0A
MDQ0_7
MCLK0A_2_P
MDQ0_6
MCLK0A_2_N
MDQ0_5
MCLK0A_1_P
MDQ0_4
MDQ0_3
MCLK0A_1_N
MDQ0_2
MCLK0A_0_P
MDQ0_1
MCLK0A_0_N
MDQ0_0

1

MCP7A
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

AV17
AP17
AR17

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

AP23
AP19
AW17

MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19

TP_MEM_A_CLK2P
TP_MEM_A_CLK2N

AW33
AV33

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

BI

33 101

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

OUT

31 101

101 33

BI

OUT

31 101

101 33

BI

OUT

31 101

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

OUT

31 101

101 33

BI

OUT

31 101

101 33

BI

OUT

31 101

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

101 33

BI

101 33

BI

101 33

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

OUT

31 101

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

101 33

BI

8
8

BA24
AY24

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

OUT

33 101

101 33

BI

OUT

33 101

101 33

BI

BB20
BC20

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

101 33
33 101

BI

OUT
OUT

33 101

MCS0A_1*
MCS0A_0*

AT15
AR18

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MODT0A_1
MODT0A_0

AP15
AV15

MCKE0A_1
MCKE0A_0

AU23
AT23

101 33

BI

101 33

BI

OUT

31 101

101 33

OUT

OUT

31 101

101 33

OUT

101 33

OUT

MEM_A_ODT<1>
MEM_A_ODT<0>

OUT

31 101

101 33

OUT

OUT

31 101

101 33

OUT

101 33

OUT

MEM_A_CKE<1>
MEM_A_CKE<0>

OUT

31 101

101 33

OUT

OUT

31 101

101 33

OUT

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8
BA9
BB10
BB12
AW12
BB8
BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42

BGA
(3 OF 11)
MDQ1_63
MDQS1_7_P
MDQ1_62
MDQS1_7_N
MDQ1_61
MDQS1_6_P
MDQ1_60
MDQS1_6_N
MDQ1_59
MDQS1_5_P
MDQ1_58
MDQS1_5_N
MDQ1_57
MDQS1_4_P
MDQ1_56
MDQS1_4_N
MDQ1_55
MDQS1_3_P
MDQ1_54
MDQS1_3_N
MDQ1_53
MDQS1_2_P
MDQS1_2_N
MDQ1_52
MDQ1_51
MDQS1_1_P
MDQ1_50
MDQS1_1_N
MDQ1_49
MDQS1_0_P
MDQ1_48
MDQS1_0_N
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MRAS1*
MDQ1_41
MCAS1*
MDQ1_40
MWE1*
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MBA1_2
MDQ1_34
MBA1_1
MDQ1_33
MBA1_0
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MA1_14
MDQ1_26
MA1_13
MDQ1_25
MA1_12
MDQ1_24
MA1_11
MDQ1_23
MA1_10
MDQ1_22
MA1_9
MDQ1_21
MA1_8
MDQ1_20
MA1_7
MDQ1_19
MA1_6
MDQ1_18
MA1_5
MDQ1_17
MA1_4
MDQ1_16
MA1_3
MDQ1_15
MA1_2
MDQ1_14
MA1_1
MDQ1_13
MA1_0
MDQ1_12
MDQ1_11
MDQ1_10
MEMORY
MDQ1_9
CONTROL
MDQ1_8
1A
MDQ1_7
MCLK1A_2_P
MDQ1_6
MCLK1A_2_N
MDQ1_5
MCLK1A_1_P
MDQ1_4
MCLK1A_1_N
MDQ1_3
MDQ1_2
MCLK1A_0_P
MDQ1_1
MCLK1A_0_N
MDQ1_0

MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>

AT5
BA2
AY7
BA11
BB34
BB38
AY43
AR42

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

A

MEMORY PARTITION 1

8

AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

AW16
BA15
BA16

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

BB29
BB18
BB17

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18

MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

BA42
BB42

TP_MEM_B_CLK2P
TP_MEM_B_CLK2N

BB22
BA22

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

BI

33 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

OUT

32 101

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

OUT

33 101

OUT

33 101

BA19
AY19

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

OUT

33 101

OUT

33 101

MCS1A_1*
MCS1A_0*

BB14
BB16

MEM_B_CS_L<1>
MEM_B_CS_L<0>

OUT

32 101

OUT

32 101

MODT1A_1
MODT1A_0

BB13
AY15

MEM_B_ODT<1>
MEM_B_ODT<0>

OUT

32 101

OUT

32 101

MCKE1A_1
MCKE1A_0

AY31
BB30

MEM_B_CKE<1>
MEM_B_CKE<0>

OUT

32 101

OUT

32 101

D

C

8

B

8

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP Memory Interface
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

15 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP7A

8

101 33
101 33

101 33
101 33

101 31
101 31

101 31
101 31

101 31
101 31

30 25 16 6

25

=PP1V8R1V5_S0_MCP_MEM

TP_MEM_A_CLK5P
TP_MEM_A_CLK5N

AU33
AU34

MCLK0B_2_P
MCLK0B_2_N

MEM_A_CLK_P<4>
MEM_A_CLK_N<4>

BB24
BC24

MCLK0B_1_P
MCLK0B_1_N

MEM_A_CLK_P<3>
MEM_A_CLK_N<3>

BA21
BB21

MCLK0B_0_P
MCLK0B_0_N

MEM_A_CS_L<2>
MEM_A_CS_L<3>

AU17
AR15

MCS0B_0*
MCS0B_1*

MEM_A_ODT<2>
MEM_A_ODT<3>

AN17
AN15

MODT0B_0
MODT0B_1

MEM_A_CKE<2>
MEM_A_CKE<3>

AV23
AN25

MCKE0B_0
MCKE0B_1

1

40.2
1%
1/16W
MF-LF
402

17
12
19
39

mA
mA
mA
mA

T28
U28
U27
T27

AM41
AN41

101 MCP_MEM_COMP_VDD

R1611 1

AA22
AP12
G30
P10
T10
T6
V10
V34
W5
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AT25
AP30
AR36
AU10
F28
BC21
AY9
BC9
D34
F24
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T18
T20
AK11
T24
T26

40.2
1%
1/16W
MF-LF
402

BA41
BB41

TP_MEM_B_CLK5P
TP_MEM_B_CLK5N

MCLK1B_1_P
MCLK1B_1_N

AY23
BA23

MEM_B_CLK_P<4>
MEM_B_CLK_N<4>

MCLK1B_0_P
MCLK1B_0_N

BA20
AY20

MEM_B_CLK_P<3>
MEM_B_CLK_N<3>

MCS1B_0*
MCS1B_1*

BC16
BA13

MEM_B_CS_L<2>
MEM_B_CS_L<3>

MODT1B_0
MODT1B_1

AY16
BC13

MEM_B_ODT<2>
MEM_B_ODT<3>

MCKE1B_0
MCKE1B_1

BA30
BA31

MEM_B_CKE<2>
MEM_B_CKE<3>

MRESET0*

AY32

8

D

8

33 101
33 101

33 101
33 101

32 101
32 101

32 101
32 101

32 101
32 101

V1P1_PLL_V
V1P1_PLL_DP
V1P1_PLL_CORE
V1P1_PLL_XREF_XS

MCP_MEM_RESET_L

OUT

33

TP or NC for DDR2.

2
101 MCP_MEM_COMP_GND

C

MCLK1B_2_P
MCLK1B_2_N

PP1V05_S0_MCP_PLL_CORE

87 mA (A01)

R1610

MEMORY CONTROL 1B

8

D

MEMORY CONTROL 0B

BGA
(4 OF 11)

2

B

A

MEM_COMP_GND
MEM_COMP_1P8V

GND

=PP1V8R1V5_S0_MCP_MEM

V1P8_MEM_VDDP

GND

AM17
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AM19
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AM21
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AM23
AY26
AW19
AW24
BC25
AL30
AM31
AM25
AM27
AM29
AN16
BC29

6 16 25 30

4771 mA (A01, DDR3)

C

B

T33
T34
T35
T37
T38
T7
T9
U18
U20
U22

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP MEMORY CNTRL & MISC
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

A.0.0

7

BRANCH

PAGE

16 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

D

REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP7A

D

C

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

=PEG_D2R_P<0>
=PEG_D2R_N<0>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
=PEG_D2R_P<2>
=PEG_D2R_N<2>
=PEG_D2R_P<3>
=PEG_D2R_N<3>
=PEG_D2R_P<4>
=PEG_D2R_N<4>
=PEG_D2R_P<5>
=PEG_D2R_N<5>
=PEG_D2R_P<6>
=PEG_D2R_N<6>
=PEG_D2R_P<7>
=PEG_D2R_N<7>
=PEG_D2R_P<8>
=PEG_D2R_N<8>
=PEG_D2R_P<9>
=PEG_D2R_N<9>
=PEG_D2R_P<10>
=PEG_D2R_N<10>
=PEG_D2R_P<11>
=PEG_D2R_N<11>
=PEG_D2R_P<12>
=PEG_D2R_N<12>
=PEG_D2R_P<13>
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_N<14>
=PEG_D2R_P<15>
=PEG_D2R_N<15>

IN

9

IN

42

IN

9

IN

8

IN

8

IN

8

67

B

IN

8

OUT

47

OUT

PE0_TX0_P
PE0_TX0_N
PE0_TX1_P
PE0_TX1_N
PE0_TX2_P
PE0_TX2_N
PE0_TX3_P
PE0_TX3_N
PE0_TX4_P
PE0_TX4_N
PE0_TX5_P
PE0_TX5_N
PE0_TX6_P
PE0_TX6_N
PE0_TX7_P
PE0_TX7_N
PE0_TX8_P
PE0_TX8_N
PE0_TX9_P
PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

E11
D11

9
9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

PEG_CLK100M_P
PEG_CLK100M_N

OUT

9

OUT

9

G11
F11

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

OUT

34 102

OUT

34 102

PE2_REFCLK_P
PE2_REFCLK_N

J11
J10

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

OUT

41 102

OUT

41 102

PE3_REFCLK_P
PE3_REFCLK_N

G13
F13

PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

OUT

8

OUT

8

PE4_REFCLK_P
PE4_REFCLK_N

J13
H13

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

PE5_REFCLK_P
PE5_REFCLK_N

L14
K14

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

PE6_REFCLK_P
PE6_REFCLK_N

N14
M14

TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N

PEX_RST0*

K11

PCIE_RESET_L

D5
D9

Int PU
PEB_CLKREQ*/GPIO_49
PEB_PRSNT* Int PU

PE1_REFCLK_P
PE1_REFCLK_N

FW_CLKREQ_L
PCIE_FW_PRSNT_L

E8
C10

Int PU
PEC_CLKREQ*/GPIO_50
PEC_PRSNT* Int PU

EXCARD_CLKREQ_L
PCIE_EXCARD_PRSNT_L

M15
B10

Int PU
PED_CLKREQ*/GPIO_51
PED_PRSNT* Int PU

TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L

L16
L18

AUD_IP_PERIPHERAL_DET
GMUX_JTAG_TCK_L

M16
M18
M17
M19
F17

PEF_PRSNT*/GPIO_47
Int PU
Int PU
PEG_CLKREQ*/GPIO_18
PEG_PRSNT*/GPIO_48
Int PU
PE_WAKE* Int PU (S5)

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>

OUT

Int PU
PE0_PRSNT_16*

Int PU
PEE_CLKREQ*/GPIO_16
PEE_PRSNT*/GPIO_46
Int PU
Int PU
PEF_CLKREQ*/GPIO_17

C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1

OUT

C9

MINI_CLKREQ_L
PCIE_MINI_PRSNT_L

8

PE0_RX0_P
PE0_RX0_N
PE0_RX1_P
PE0_RX1_N
PE0_RX2_P
PE0_RX2_N
PE0_RX3_P
PE0_RX3_N
PE0_RX4_P
PE0_RX4_N
PE0_RX5_P
PE0_RX5_N
PE0_RX6_P
PE0_RX6_N
PE0_RX7_P
PE0_RX7_N
PE0_RX8_P
PE0_RX8_N
PE0_RX9_P
PE0_RX9_N
PE0_RX10_P
PE0_RX10_N
PE0_RX11_P
PE0_RX11_N
PE0_RX12_P
PE0_RX12_N
PE0_RX13_P
PE0_RX13_N
PE0_RX14_P
PE0_RX14_N
PE0_RX15_P
PE0_RX15_N

PE0_REFCLK_P
PE0_REFCLK_N

PEG_PRSNT_L

IN

34

F7
E7
D7
C7
E6
F6
E5
F5
E4
E3
C3
D3
G5
H5
J7
J6
J5
J4
L11
L10
L9
L8
L7
L6
N11
N10
N9
P9
N7
N6
N5
N4

PCI EXPRESS

BGA
(5 OF 11)

D

C

8
8

8
8

8

IN

CARDREADER_RESET
GMUX_JTAG_TDO

34

IN

PCIE_WAKE_L

OUT

9

102 34

IN

PE1_RX0_P
PE1_RX0_N

PE1_TX0_P
PE1_TX0_N

D8
C8

PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N

OUT

IN

K9
J9

34 102

102 34

PCIE_MINI_D2R_P
PCIE_MINI_D2R_N

OUT

34 102

PCIE_FW_D2R_P
PCIE_FW_D2R_N

H9
G9

PE1_RX1_P
PE1_RX1_N

PE1_TX1_P
PE1_TX1_N

B8
A8

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

OUT

41 102

OUT

41 102

PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N

F9
E9

PE1_RX2_P
PE1_RX2_N

PE1_TX2_P
PE1_TX2_N

A7
B7

PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N

OUT

8

OUT

8

TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN

H7
G7

PE1_RX3_P
PE1_RX3_N

PE1_TX3_P
PE1_TX3_N

B6
C6

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

102 41

IN

102 41

IN

8

IN

8

IN
8
8

=PP1V05_S0_MCP_PEX_DVDD0

28 25

=PP1V05_S0_MCP_PEX_AVDD0

57 mA (A01, DVDD0 & 1)
Minimum 1.025V for Gen2 support

T17
W19
U17
V19
W16
W17
W18
U16

V1P1_PEX_DVDD0

T19
U19

V1P1_PEX_DVDD1

V1P1_PEX_AVDD0

Y12
AC12
AD12
V12
W12
AA12
AB12
M12
P12
R12
N12
T12
U12

V1P1_PEX_AVDD1

M13
N13
P13

=PP1V05_S0_MCP_PEX_DVDD1

28

PP1V05_S0_MCP_PLL_PEX

25

T16

102 MCP_PEX_CLK_COMP

A11

PEX_CLK_COMP

8

B

8
8

25 28

206 mA (A01, AVDD0 & 1)
Minimum 1.025V for Gen2 support

=PP1V05_S0_MCP_PEX_AVDD1

V1P1_PLL_PEX

84 mA (A01)

8

28

NO STUFF

A

1

R1710

2

SYNC_MASTER=K22

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

2.37K
1%
1/16W
MF-LF
402

SYNC_DATE=09/02/2009

MCP PCIe Interfaces
DRAWING NUMBER

PLACEMENT_NOTE=Place within 12.7mm of U1400

Apple Inc.

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

A.0.0
BRANCH

PAGE

17 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

7

SIZE

REVISION

R

8

A

PAGE TITLE

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP7A
BGA
(6 OF 11)

=PP3V3_ENET_MCP_RMGT

D

J24
K24

V1P0_DUAL_RMGT_0
V1P0_DUAL_RMGT_1

U23
V23

MII_VREF

E28

MCP_MII_VREF

MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3

B24
C24
C25
D25

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

MII_TXCLK
MII_TXEN

D24
C26

MII_MDC
MII_MDIO

18 25 38

83 mA (A01)
=PP1V05_ENET_MCP_RMGT

38 25 18

=PP3V3_ENET_MCP_RMGT

R1810

IN

104 37

IN

104 37

IN

104 37

IN

104 37

IN

104 37

IN

9

IN

9

IN

9

IN

1

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>

8

1%
1/16W
MF-LF
402

C23
B23
E24
A24

MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3

ENET_CLK125M_RXCLK
ENET_RX_CTRL

A23
C22

MII_RXCLK
MII_RXDV

=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS

F23
B26
B22

MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK

TP_ENET_INTR_L

J22

MII_INTR/GPIO_35

PP1V05_ENET_MCP_PLL_MAC

25

5 mA (A01)

T23

V1P1_DUAL_MACPLL

104 MCP_MII_COMP_GND

C27
B27

MII_COMP_VDD
MII_COMP_GND

37 104
37 104

OUT

37 104

OUT

37 104

ENET_CLK125M_TXCLK
ENET_TX_CTRL

OUT

37 104

OUT

37 104

D21
C21

ENET_MDC
ENET_MDIO

OUT

37 104

MII_PWRDWN/GPIO_37

G23

TP_ENET_PWRDWN_L

49.9

RGB_DAC_RSET
RGB_DAC_VREF

1

47K

51

OUT

8

OUT

8

IN

8

OUT

MCP Signal

TMDS/HDMI

=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N

TMDS_IG_TXC_P/N
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N

DisplayPort
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.
LVDS:
Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

V3P3_RGBDAC_VDD
V3P3_TVDAC_VDD

J32
K32

MCP_TV_DAC_RSET
MCP_TV_DAC_VREF

E36
A35

TV_DAC_RSET
TV_DAC_VREF

MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT

C38
D38

XTALIN_TV
XTALOUT_TV

TV
C
Y
Comp

103 mA
103 mA
MCP_DDC_CLK0
MCP_DDC_DATA0

RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE

B39
A39
B40

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC
Component
Pr
TV_DAC_RED
Y
TV_DAC_GREEN
Pb
TV_DAC_BLUE

A40
A41

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

A36
B36
C36

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

D36
C37

CRT_IG_HSYNC
CRT_IG_VSYNC

IFPA_TXC_P
IFPA_TXC_N

B35
C35

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

B32
A32
D32
C32
D33
C33
B34
C34

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

IFPB_TXC_P
IFPB_TXC_N

L31
K31

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

J29
H29
L29
K29
L30
K30
N30
M30

LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24

C30
B30

/
/
/
/

BI

37 104

38 104

OUT

37

1

MII

0

=PP3V3_S0_MCP_GPIO

R1860 1

26

1

100K

206 mA (A01)

ENET_TXD<0>

RGMII

NOTE: All Apple products set strap to
MII, RGMII products will enable
feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.

8

OUT

Interface

5%
1/16W
MF-LF
402

6 19 21

R1861
100K

2

2

5%
1/16W
MF-LF
402

C

RGB DAC Disable:
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
8
8

TV DAC Disable:
OUT

8

OUT

8

OUT

8

OUT

8

OUT

8

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

OUT

89 107

LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

OUT

89

DDC_CLK3
DDC_DATA3

D31
E31

=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

OUT

IFPAB_RSET
IFPAB_VPROBE

E32
G31

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

OUT

26 102

OUT

26 102

Okay to float all TV_DAC signals.
Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.

2

LPCPLUS_GPIO
DP_IG_CA_DET

BI
93

Interface Mode

ENET_RESET_L

B31
A31

IN

89

OUT

89

OUT

89

LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

107 93

OUT

107 93

OUT

9

IN

9

IN

E16
B15
(See below)

D35
E35

HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N

=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>

G35
F35
F33
G33
J33
H33

HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD2_N/ML0_LANE0_N

DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

D43
C43

DP_AUX_CH0_P
DP_AUX_CH0_N

C31
F31

HPLUG_DET2/GPIO_22
HPLUG_DET3

(See below)

=PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V)
PP3V3_S0_MCP_VPLL

26

16 mA (A01)

26

107 26

LCD_BKL_CTL/GPIO_57
LCD_BKL_ON/GPIO_59
LCD_PANEL_PWR/GPIO_58

=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N

=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD

26

107 26

G39
E37
F40

GPIO_6/FERR*/IGPU_GPIO6
GPIO_7/NFERR*/IGPU_GPIO7

=PP1V05_S0_MCP_HDMI_VDD

95 mA (A01)
MCP_HDMI_RSET
OUT
MCP_HDMI_VPROBE
OUT

8 mA
8 mA

M27
M26

V1P8_IFPA_VDD
V1P8_IFPB_VDD

M28
M29

V3P3_PLL_IFPAB
V3P3_PLL_HDMI

T25

V1P1_HDMI_VDD

J31
J30

HDMI_RSET
HDMI_VPROBE

FLAT PANEL

5%
1/16W
MF-LF
402

MCP_CLK25M_BUF0_R

J23

RGB ONLY

8

=PP3V3_S5_MCP_GPIO

R1820

E23

DDC_CLK0
DDC_DATA0

DACS

2

C39
B38

C

20 6

BUF_25MHZ
MII_RESET*

PP3V3_S0_MCP_DAC

TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF

25

OUT

R1811 1
1%
1/16W
MF-LF
402

IN
OUT

2
104 MCP_MII_COMP_VDD

D

25 38

131 mA (A01)

Network Interface Select

LAN

104 37

49.9

B

V3P3_DUAL_RMGT0
V3P3_DUAL_RMGT1

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

1

BI

BI

B

89

9
9

R1850
10K

GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.

A

2

5%
1/16W
MF-LF
402

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP Ethernet & Graphics

=DVI_HPD_GMUX_INT:

DRAWING NUMBER

Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

7

SIZE

D

REVISION

A.0.0

R

BRANCH

PAGE

18 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

051-7863

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400

21 18 6

=PP3V3_S0_MCP_GPIO

MCP7A
BGA
(7 OF 11)

19

D

OUT

68

OUT

19

IN

13

BI

13

BI

13

BI

13

BI

13

BI

13

BI

13

BI

13

BI
8

8
8
8

8
8
8
8
8
8
8
8
8
8
8

C

8
8
8
8
8
8

8
8
8
8

8

51 49

42

IN
8

51 49

BI

MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>

AC3
AE10
AC4
AE11
AB3
AC6
AB2
AC7
AC8
AA2
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
T5
U7

TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L

P2
N3
N2
N1

TP_PCI_TRDY_L
PM_CLKRUN_L

IN

T2
V9
T3
U9
T4

Y3
AD11

FW_PME_L
TP_LPC_DRQ0_L
LPC_SERIRQ

AE2
AE1
AE6

PCI_REQ0*
PCI_REQ1*/FANRPM2
PCI_REQ2*/GPIO_40/RS232_DSR*
PCI_REQ3*/GPIO_38/RS232_CTS*
PCI_REQ4*/GPIO_52/RS232_SIN*
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CLKRUN*/GPIO_42
LPC_DRQ1*/GPIO_19 Int PU
LPC_DRQ0*
Int PU
LPC_SERIRQ Int PU

TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L

PCI_CBE0*
PCI_CBE1*
PCI_CBE2*
PCI_CBE3*

AA3
AA6
AA11
W10

TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>

PCI_DEVSEL*
PCI_FRAME*
PCI_IRDY*
PCI_PAR
PCI_PERR*/GPIO_43/RS232_DCD*
PCI_SERR*
PCI_STOP*

AA9
Y4
AA10
Y1
AB9
AA7
Y2

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L

T1

PM_LATRIGGER_L

R10
R11

MEM_VTT_EN_R
TP_PCI_RESET1_L

PCI_PME*/GPIO_30
Int PU (S5)

PCI_RESET0*
PCI_RESET1*

PCI_CLK0
PCI_CLK1
PCI_CLK2

TP_PCI_CLK0
TP_PCI_CLK1
103 PCI_CLK33M_MCP_R

R6
R7
R8

A

8
103 19

OUT

8

OUT

8

OUT

19

19
19

MCP_RS232_SOUT_L

R1989

8.2K

1

2

PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
MCP_RS232_SIN_L

R1990
R1991
R1992
R1994

8.2K
8.2K
8.2K
8.2K

1

2

1

2

1

2

1

2

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

D
8
8

8

8
8
8
8
8
8
8

OUT

13

OUT

9

8

8
8

R1910

C

22

PCI_CLKIN

LPC_FRAME*
LPC_PWRDWN*/GPIO_54/EXT_NMI*

R9

103 PCI_CLK33M_MCP

AD4
AE12

103 LPC_FRAME_R_L

LPC_RESET0*

AE5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

AD3
AD2
AD1
AD5

5%
1/16W
MF-LF
402

PLACEMENT_NOTE=Place close to pin R8

R1960

22

1

LPC_FRAME_L

2
5%

LPC_PWRDWN_L

LPC_CLK0

GND

GND

1/16W

MF-LF

OUT

402

LPC_RESET_L
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

103
103
103
103

R1950
R1951
R1952
R1953

22
22
22
22

1

2

1

2

1

2

1

2

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%
5%

GND

B

103 19

2

1/16W
1/16W

MF-LF
MF-LF

402

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>

402

Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34

49 51 103

OUT

49 51

OUT

9 103

BI

49 51 103

BI

49 51 103

BI

49 51 103

BI

LPC_CLK33M_SMC_R

AE9
1

U24
U26
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25

8

1

PCI_INTW*
PCI_INTX*
PCI_INTY*
PCI_INTZ*
PCI_TRDY*

19

R3
U10
R4
U11
P3

PCI_GNT0*
PCI_GNT1*/FANCTL2
PCI_GNT2*/GPIO_41/RS232_DTR*
PCI_GNT3*/GPIO_39/RS232_RTS*
PCI_GNT4*/GPIO_53/RS232_SOUT*

PCI

103 19

PCI_REQ0_L
PCI_REQ1_L
CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L

LPC

103 19

OUT

49 51 103

9 103

R1961
10K

5%
1/16W
MF-LF
2 402

Strap for Boot ROM Selection (See HDA_SDOUT)

B

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP PCI & LPC
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

19 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400
MCP7A
BGA
(8 OF 11)
102 45

OUT

102 45

OUT

102 45

IN

102 45

IN

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N

AJ7
AJ6

SATA_A0_TX_P
SATA_A0_TX_N

USB0_P
USB0_N

C29
D29

External A
USB_EXTA_P
USB_EXTA_N

BI

46 103

BI

46 103

SATA_HDD_D2R_N
SATA_HDD_D2R_P

AJ5
AJ4

SATA_A0_RX_N
SATA_A0_RX_P

USB1_P
USB1_N

C28
D28

AirPort (PCIe Mini-Card)
USB_MINI_P
USB_MINI_N

BI

8

BI

8

USB2_P
USB2_N

A28
B28

External D
USB_EXTD_P
USB_EXTD_N

BI

46 103

BI

46 103

USB3_P
USB3_N

F29
G29

USB_CAMERA_P
USB_CAMERA_N

BI

47 103

BI

47 103

USB4_P
USB4_N

K27
L27

USB_IR_P
USB_IR_N

BI

47 103

BI

47 103

BI

8

BI

8

BI

47 103

BI

47 103

BI

46 103

BI

46 103

BI

8

BI

8

BI

46 103

BI

46 103

D
OUT

102 45

IN

102 45

IN

SATA_ODD_D2R_N
SATA_ODD_D2R_P

TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_SATA_C_D2RN
TP_SATA_C_D2RP

SATA_A1_TX_P
SATA_A1_TX_N

AJ9
AK9

SATA_A1_RX_N
SATA_A1_RX_P

AK2
AJ3
AJ2
AJ1

SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P

IR

USB6_P
USB6_N

Geyser Trackpad/Keyboard
USB_TPAD_P
J26
USB_TPAD_N
J27
Bluetooth
USB_BT_P
F27
USB_BT_N
G27

USB7_P
USB7_N

External B
USB_EXTB_P
D27
USB_EXTB_N
E27

USB5_P
USB5_N

AM4
AL3

SATA_B1_TX_P
SATA_B1_TX_N

USB8_P
USB8_N

TP_SATA_D_D2RN
TP_SATA_D_D2RP

AL4
AK3

SATA_B1_RX_N
SATA_B1_RX_P

USB9_P
USB9_N

TP_SATA_E_D2RN
TP_SATA_E_D2RP

AN1
AM1
AM2
AM3

SATA_C0_TX_P
SATA_C0_TX_N

ExpressCard
USB_EXCARD_P
K25
USB_EXCARD_N
L25
External C
USB_EXTC_P
H25
USB_EXTC_N
J25

USB10_P
USB10_N

F25
G25

TP_USB_10P
TP_USB_10N

USB11_P
USB11_N

K23
L23

USB_SDCARD_P
USB_SDCARD_N

USB_OC0*/GPIO_25
USB_OC1*/GPIO_26
USB_OC2*/GPIO_27/MGPIO
USB_OC3*/GPIO_28/MGPIO

L21
K21
J21
H21

AP3
AP2

SATA_C1_TX_P
SATA_C1_TX_N

TP_SATA_F_D2RN
TP_SATA_F_D2RP

AN3
AN2

SATA_C1_RX_N
SATA_C1_RX_P

V3P3_PLL_USB

L28

PP1V05_S0_MCP_PLL_SATA

25

28 6

E12

AE16

SATA_LED*

V1P1_PLL_SATA

84 mA (A01)
=PP1V05_S0_MCP_SATA_DVDD0
43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

AF19
AG16
AG17
AG19

V1P1_SATA_DVDD0

AH17
AH19

V1P1_SATA_DVDD1

=PP1V05_S0_MCP_SATA_DVDD1

28

B
=PP1V05_S0_MCP_SATA_AVDD0

28

127 mA (A01, AVDD0 & 1)
Minimum 1.025V for Gen2 support

AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13

V1P1_SATA_AVDD0

AN14
AL14
AM13
AM14

V1P1_SATA_AVDD1

GND

=PP1V05_S0_MCP_SATA_AVDD1

28

102 MCP_SATA_TERMP

1

AE3

1

R2051
8.2K

2

R2053
8.2K

5%
1/16W
MF-LF
402

2

5%
1/16W
MF-LF
402

8

BI

47 103

BI

47 103

R2050 1

8.2K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

C

R2052 1

8.2K

2

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L

IN

46

IN

46

IN

9 46

EXCARD_OC_L

PP3V3_S0_MCP_PLL_USB

25

A27

103 MCP_USB_RBIAS_GND

R2060
TP_MCP_SATALED_L

1

6 18

19 mA (A01)
USB_RBIAS_GND

45

=PP3V3_S5_MCP_GPIO

8

SATA_C0_RX_N
SATA_C0_RX_P

TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN

D

Camera

TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN

TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN

C

AJ11
AJ10

USB

OUT

102 45

SATA

102 45

SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N

SATA_TERMP

AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24

1

806
1%
1/16W
MF-LF
402

2

B

R2010
2.49K

2

1%
1/16W
MF-LF
402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP SATA & USB
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

A.0.0

7

BRANCH

PAGE

20 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

D

REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

6

5

4

3

2

1

8

7

6

5

4

3

2

1

OMIT

U1400

=PP3V3R1V5_S0_MCP_HDA

MCP7A

6 21 25

7 mA (A01)

BGA
(9 OF 11)

HDA

V3P3_DUAL_HDA_0
V3P3_DUAL_HDA_1

D
103 62

HDA_SDIN0

IN

8

9

=PP3V3R1V5_S0_MCP_HDA

25 21 6

G15

TP_MLB_RAM_SIZE

HDA_SDATA_IN0
Int PD

J14

TP_MLB_RAM_VENDOR

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

51
50 49

49.9K

C

1%
1/16W
MF-LF
402

OUT
IN

R2121

8

49.9K

2

2

22

1

103 21

K15

103 21

L15

103 21

2

1

22
2

HDA_RST_L

OUT

8

1%
1/16W
MF-LF
402

49

IN

49

IN

22

HDA_SYNC

2

OUT

A15

HDA_PULLDN_COMP

AE18
AE17

20 mA
17 mA

GPIO_4/HDA_DOCK_EN*/PS2_MS_CLK
GPIO_5/HDA_DOCK_RST*/PS2_MS_DATA

K17
L17

SLP_S3*
SLP_RMGT*
SLP_S5*

G17
J17
H17

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

=SPI_CS1_R_L_USE_MLB
SMC_ADAPTER_EN

L24
L26

THERM_DIODE_P
THERM_DIODE_N

B11
C11

MCP_THMDIODE_P
MCP_THMDIODE_N

V1P1_PLL_NV_H
V1P1_PLL_SP_SPREF

GPIO_1/PWRDN_OK/SPI_CS1
GPIO_12/SUS_STAT*/ACCLMTR_EXT_TRIG

TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
SMC_RUNTIME_SCI_L

K13
L13
C19
C18

Int PU
A20GATE
KBRDRSTIN* Int PU
SIO_PME*
Int PU (S5)
EXT_SMI*/GPIO_32 Int PU (S5)

SM_INTRUDER_L

B20

INTRUDER*

IN

TP_MCP_LID_L
PM_BATLOW_L

M25
M24

49

IN

28

IN

PM_PWRBTN_L
PM_SYSRST_DEBOUNCE_L
RTC_RST_L

49

B

70

GPIO_13/MCP_VID0
GPIO_14/MCP_VID1
GPIO_15/MCP_VID2

L20
M20
M21

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

SPKR

C13

MCP_SPKR

IN

21 68

SMB_CLK0
SMB_DATA0
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT*/GPIO_64

L19
K19
G21
F21
M23

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

PWRBTN* Int PU (S5)
RSTBTN* Int PU
RTC_RST*

(MGPIO2)
(MGPIO3)

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62

B12
A12
D12
C12

MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT

CPUVDD_EN

D17

MCP_CPUVDD_EN

IN

PWRGD_SB
PS_PWRGD

MCP_CPU_VLD

C17

CPU_VLD

JTAG_MCP_TDI
JTAG_MCP_TDO
JTAG_MCP_TMS
JTAG_MCP_TRST_L
JTAG_MCP_TCK

E19
F19
J19
J18
G19

JTAG_TDI Int PU
JTAG_TDO
JTAG_TMS Int PU
JTAG_TRST*
JTAG_TCK

GPIO_10/SPI_CS0
GPIO_11/SPI_CLK
GPIO_8/SPI_DI
GPIO_9/SPI_DO

C14
D13
C15
B14

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT

A16
B16

XTALIN
XTALOUT

SUS_CLK/GPIO_34
BUF_SIO_CLK

B18
AE7

PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK

RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT

A19
B19

XTALIN_RTC
XTALOUT_RTC

TEST_MODE_EN
PKG_TEST

K22
L22

9

IN

IN

13

OUT

13

IN

13

IN

13

IN

103 28

IN

103 28

OUT

103 28

IN

103 28

OUT

10K
5%
1/16W
MF-LF
402 2

1

OUT

9 102

OUT

70

OUT

70 102

OUT

55 108

OUT

55 108

OUT

21 74

OUT

21 74

OUT

21 74

OUT
BI
OUT
BI
OUT

IN
OUT

100K
5%
1/16W
MF-LF
2 402

2

IN

OUT

=PP3V3_S0_MCP_GPIO

C2170

C2172

1

10PF
5%
50V
CERM
402

21 103

R2140

R2141

1

1

R2142

5%
50V
CERM
402

1

2

C2171

=PP3V3_S0_MCP
1

NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.

6 22 25

R2180
5%
1/16W
MF-LF
402

13 52 106

Frequency
50

10K

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

21 103

MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L

21 103
21 103

ARB_DETECT

R2181
10K

13 52 106
52
2

52
21

5%
1/16W
MF-LF
402

1

C2173
10PF

5%
50V
CERM
402

5%
50V
CERM
402

2

2

HDA_SYNC

24 MHz

1

14.31818 MHz

0

USER mode: Normal
SAFE mode: For ROMSIP
recovery

SPI Frequency Select

Connects to SMC for
automatic recovery.

Frequency

SPI_DO

SPI_CLK

31 MHz

0

0

42 MHz

0

1

25 MHz

1

0

1 MHz

1

1

21 31 32 49 55
8
21 50

9

51 103

OUT

51 61 103

NOTE: Straps not provided on this page.

IN

51 61 103

OUT

51 61 103

OUT

9 103

R2190
1K

2

1%
1/16W
MF-LF
402

6 18 19

1

6

R2154
100K

5%
1/16W
MF-LF
2 402

AP_PWR_EN

21

21

21 68
21 31 32 49 55

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

21 50

21

21 74
21 74
21 74

SYNC_MASTER=K22

1

R2147

R2155

1

R2156

1

22K

22K

22K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

2

2

DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

PAGE

21 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

7

A

MCP HDA & MISC

R2157

100K

SYNC_DATE=09/02/2009

PAGE TITLE

2

1

C

BUF_SIO_CLK Frequency

10K

OUT

1

5%
1/16W
MF-LF
402

1

10PF

8

1

B

R2163

R2143

10K

10PF
2

1

NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

=PP3V3_S3_MCP_GPIO

For EMI Reduction on HDA interface

SPI1

8

HDA Output Caps
1

0

21

10K

R2151

1

1

MCP_TEST_MODE_EN
1

R2150 1

1

SPI0

BOOT_MODE_USER

D20
E20

13

0

R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.

OUT

PM_RSMRST_L
MCP_PS_PWRGD

IN

0

PCI

21

1

CPU_DPRSLPVR

C20

LPC_FRAME#

0

BOOT_MODE_SAFE

LID* Int PU (S5)
LLB* Int PU (S5)

C16
D16

HDA_SDOUT

LPC

62 103

PP1V05_S0_MCP_PLL_NV

NC M22

A

62 103

I/F

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

MCP_GPIO_4
AUD_I2C_INT_L

MISC

49

HDA_RST_R_L
HDA_SYNC_R

62 103

5%
1/16W
MF-LF
402

2

HDA_SDOUT_R
HDA_BIT_CLK_R

OUT

R2172
1

1

62 103

BIOS Boot Select
HDA_BIT_CLK

2

HDA_RST_R_L

HDA_SYNC_R

OUT

5%
1/16W
MF-LF
402

22

HDA_BIT_CLK_R

HDA_SDOUT

5%
1/16W
MF-LF
402

PP3V3_G3_RTC

R2120

E15

D

R2170
HDA_SDOUT_R

1%
1/16W
MF-LF
402

37 mA (A01)

1

103 21

R2110

25

1

F15

R2173

103 MCP_HDA_PULLDN_COMP

28 22

8.2K

5%
1/16W
MF-LF
402

49.9

2

R2160

R2171

GPIO_3/HDA_SDATA_IN2/PS2_KB_DATA
Int PD

(MXM_OK for MXM systems)
1

1

5%
1/16W
MF-LF
2 402

GPIO_2/HDA_SDATA_IN1/PS2_KB_CLK
Int PD

J15

J16
K16

6

5

4

3

2

1

8

7

6

5

4

OMIT

MCP7A

C

B

A

GND

1

U1400
MCP7A

BGA
(11 OF 11)

D

2

OMIT

U1400
AH26
AH33
AH34
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41

3

GND

25 6

AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22

BGA
(10 OF 11)

=PPVCORE_S0_MCP
AA25
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC23
AC24
AC25
AC26
AC27
AC28
AD21
AD23
W27
V25
AA18
U25
AE19
AE21
AE23
AE25
AE26
AE27
AE28
AF10
AF11
AA19
AH12
AF2
AF21
AF23
AF25
AF3
AF4
AF7
AH23
AF9
AA20
AG10
AG11
AG12
AG21
AG23
AG25
AG3
AG4
AA21
AG6
AG7
AG5
AG8
AG9
AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
Y21
AH21
AH3
AH4
AH5
AH6
AH7
AH9
AA24
W21
W23
Y23
W25
AF12
AA16

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

28 21

=PP1V05_S0_MCP_FSB

V1P2_CPU_VTT

V1P0_CORE_VDD

V1P2_CPUCLK_VTT

A20

1139 mA

AG32

43 mA

V3P3

C

AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9

6 21 25

450 mA (A01)

B

=PP3V3_S5_MCP
16 mA

V3P3_DUAL

G18
H19
J20
K20
G26
H27
J28
K28

250 mA

V3P3_DUAL_USB

V1P0_VDD_AUXC

T21
U21
V21

=PP1V05_S5_MCP_VDD_AUXC

V3P3_VBAT

6 14 25

1182 mA (A01)

D

=PP3V3_S0_MCP

PP3V3_G3_RTC
10 uA (G3)
80 uA (S0)

R32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
AC32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
E40
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
J36
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
N32
P32
Y32
AA32
T32
U32
V32
W32

6 25

266 mA (A01)

6 25

105 mA (A01)

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

MCP Power & Ground
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

A.0.0
BRANCH

PAGE

22 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

7

SIZE

REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

8

A

PAGE TITLE

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

23 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

24 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

MCP Core Power
22 6

6

5

4

3

2

1

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
APPLE: 4X 4.7UF 0402, 4X 1UF 0402, 6X 0.1UF 0402 (23.4 UF)

=PPVCORE_S0_MCP

TABLE_5_HEAD

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
(No IG vs. EG data)

PART#

28 6

MCP PCIE (DVDD) Power
DIFFERENT THAN ON T18
=PP1V05_S0_MCP_PEX_DVDD

1

C2501

4.7UF

1

C2502

4.7UF
20%
4V
X5R
402

2

1

C2503

4.7UF

1

1

20%
4V
X5R
402

2

1UF
2

10%
10V
X5R
402-1

2

MXM

1

C2515

C2516
1UF

2

1

1

2.2UF
20%
6.3V
CERM
402-LF

10%
10V
X5R
402-1

MXM

1

C2517
1UF

2

2

1

C2505
1UF

2

NV: 1X 4.7UF 0402, 2X 1UF 0402, 2X 0.1UF 0402 (6.9UF)
K50: 2X 2.2UF 0402, 2X 1UF 0402, (6.4 UF)
28 17 =PP1V05_S0_MCP_PEX_DVDD0

PEX_DVDD RAIL SPLIT BASED
ON IG VS. EG. 8 OUT OF 10
BALLS FOR DVDD0 SO 80% OF
CAPACITANCE ON DVDD0

1

C2504

4.7UF

20%
4V
X5R
402

2

57 mA (A01)

1UF

10%
10V
X5R
402-1

2

2

1

C2507
1UF

10%
10V
X5R
402-1

2

1

C2508
1UF

10%
10V
X5R
402-1

2

C2509

1

1UF

10%
10V
X5R
402-1

2

10%
10V
X5R
402-1

1

C2510
1UF

2

1

C2511
1UF

10%
10V
X5R
402-1

2

C2512

1

1UF

10%
10V
X5R
402-1

2

10%
10V
X5R
402-1

C2513

REFERENCE DESIGNATOR(S)

116S0004

2

6

43 mA (A01)

MXM

RES,0,5%,0402

C2574,C2518

1

C2520

1

1

4.7UF
20%
4V
X5R
402

2

2

1

C2521

C2570

0.1uF

2.2UF

20%
10V
CERM
402

20%
6.3V
CERM
402-LF

2

MCP 1.05V RMGT Power

1

131 mA (A01)

1

C2525

C2526

0.1uF
2

MCP FSB (VTT) Power

C2528

0.1uF

20%
10V
CERM
402

1

2

2

4.7uF
20%
4V
X5R
402

20%
10V
CERM
402

2

1

2

C2529
0.1uF

2

1

2

C2531

1

C2532

1

C2533

1

C2534

1

C2535

1

C2536

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

2.2UF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

2

2

2

2

2

2

20%
4V
X5R
402

1

1

2

2

2.2UF

20%
6.3V
CERM
402-LF

2

20%
6.3V
CERM
402-LF

PEX_AVDD RAIL SPLIT BASED
ON IG VS. EG. 12 OUT OF 15
BALLS FOR AVDD0 SO 80% OF
CAPACITANCE ON AVDD0

127 mA (A01)

2

C2576
20%
6.3V
CERM
402-LF

14

270 mA (A01)

C

C2581
20%
4V
X5R
402

L2582
1

PP1V05_S0_MCP_PLL_PEX

C2540

1

1

4.7UF
20%
4V
X5R
402

2

2

1

C2541

1

C2542

1

C2543

1

C2544

1

C2545

1

C2546

1

C2547

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

2

2

2

2

2

2

2

2

450 mA (A01)

1

19 mA (A01)

2
0402

1

C2550

1

C2551

C2552

1

1

C2553

2.2UF

2.2UF

2.2UF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

2

2

20%
4V
X5R
402

2

1

2

2

84 mA (A01)

C2583
4.7UF
20%
4V
X5R
402

L2584
30-OHM-1.7A
1

PP1V05_S0_MCP_PLL_SATA

0402

C2584

1

1

2

2

4.7UF
20%
4V
X5R
402

20

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2

19 mA (A01)

C2555

2.2UF

20%
6.3V
CERM
402-LF

1

4.7UF

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

2.2UF
2

C2582

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
PP3V3_S0_MCP_PLL_USB
20

L2555
30-OHM-1.7A

=PP3V3_S0_MCP_PLL_UF

6

2

C2549

0.1UF

20%
10V
CERM
402

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)

1

1

C2548

0.1UF

17

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2
0402

=PP3V3_S0_MCP

2

17 28

C2574

4.7UF

30-OHM-1.7A

=PP1V8R1V5_S0_MCP_MEM

MCP 3.3V Power

1

2.2UF

20%
6.3V
CERM
402-LF

4.7UF

4771 mA (A01, DDR3)

22 21 6

MXM

C2573
2.2UF

20%
6.3V
CERM
402-LF

PP1V05_S0_MCP_PLL_FSB

C2580

MCP Memory Power
30 16 6

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2
0402

1

C2575

30-OHM-1.7A

=PP1V05_S0_MCP_PLL_UF
562 mA (A01)

C2530

1

2.2UF

206 mA (A01)

=PP1V05_S0_MCP_PEX_AVDD0

L2580
6

1

1

2.2UF

20%
10V
CERM
402

1182 mA (A01)

C

20%
6.3V
CERM
402-LF

MXM

C2572

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2

1

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)

=PP1V05_S0_MCP_FSB

1

2.2UF

0603

1

MXM

C2571

MXM

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
PP1V05_S0_MCP_SATA_AVDD
28

L2575
30-OHM-5A

=PP1V05_ENET_MCP_RMGT

D
28

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2
0603

38 18

1

IG

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
PP1V05_S0_MCP_PEX_AVDD

30-OHM-5A

=PP1V05_S0_MCP_AVDD_UF
333 mA (A01)

20%
6.3V
CERM
402-LF

=PP1V05_S5_MCP_VDD_AUXC

2

10%
10V
X5R
402-1

C2518

105 mA (A01)

22 14 6

BOM OPTION

1UF

L2570

=PP1V05_S0_MCP_SATA_DVDD

2.2UF

10%
10V
X5R
402-1

1

C2506

MCP SATA (DVDD) Power
28

MCP 1.05V AUX Power
22 6

DESCRIPTION

TABLE_5_ITEM

C2500
20%
4V
X5R
402

D

QTY

84 mA (A01)

C2585
4.7UF
20%
4V
X5R
402

B

B
MCP 3.3V AUX/USB Power
22 6

=PP3V3_S5_MCP

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V Ethernet Power
38 25 18

266 mA (A01)

2

MCP 3.3V/1.5V HDA Power
=PP3V3R1V5_S0_MCP_HDA

L2586
30-OHM-1.7A
1

PP1V05_S0_MCP_PLL_CORE

1

C2560

C2564

2.2UF

2.2UF

20%
6.3V
CERM
402-LF

20%
6.3V
CERM
402-LF

2

C2586

1

C2597

4.7UF

4.7UF

20%
4V
X5R
402

20%
4V
X5R
402

2

1

1

2

2

C2587
4.7UF
20%
4V
X5R
402

30-OHM-1.7A
1

PP1V05_S0_MCP_PLL_NV

0402

C2562

C2588

2.2UF

38 25 18

1

1

4.7UF

MCP79 Ethernet VRef

20%
6.3V
CERM
402-LF

20%
4V
X5R
402

21

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2

7 mA (A01)

2

87 mA (A01)

L2588

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

16

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2
0402

83 mA (A01)
1

21 6

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

=PP3V3_ENET_MCP_RMGT

C2589

1

4.7UF
2

2

20%
4V
X5R
402

37 mA (A01)

C2590
2.2UF

2

20%
4V
X5R
402

=PP3V3_ENET_MCP_RMGT

R2591 1
1.47K

A

1%
1/16W
MF-LF
402 2

L2595
38

5 mA (A01)

1

SYNC_MASTER=K22

PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2
0402

C2595

1

1

4.7UF
20%
4V
X5R
402

MCP_MII_VREF

18

7

A

2

MCP Standard Decoupling

18

5 mA (A01)

R2590 1

C2596

DRAWING NUMBER
1

1.47K
1%
1/16W
MF-LF
402 2

4.7UF
2

OUT

20%
4V
X5R
402

C2591

Apple Inc.

0.1UF
2

20%
10V
CERM
402

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

BRANCH

PAGE

25 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

SYNC_DATE=09/02/2009

PAGE TITLE

30-OHM-1.7A

=PP1V05_ENET_MCP_PLL_MAC

6

5

4

3

2

1

8

7

6

5

4

3

2

1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

IG

R2680
6

=PP3V3R1V8_S0_MCP_IFP_VDD_R 1

0

PP3V3R1V8_S0_MCP_IFP_VDD

2

5%
1/16W
MF-LF
402

=PP3V3R1V8_S0_MCP_IFP_VDD

18

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

IG
1

C2610

190 mA (A01, 1.8V)
TABLE_5_HEAD

2.2UF
2

D

PART#

20%
6.3V
CERM
402-LF

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

116S0004

1

RES,0,5%,402

C2610

MXM

D

IG

R2690
6

=PP1V05_S0_MCP_HDMI_VDD_R

1

0

TABLE_5_HEAD

PP1V05_S0_MCP_HDMI_VDD

2

5%
1/16W
MF-LF
402

IG

C2615

IG
1

1

2

2

4.7UF
20%
4V
X5R
402

C2616

=PP1V05_S0_MCP_HDMI_VDD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

18

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

TABLE_5_ITEM

116S0004

1

RES,0,5%,402

C2616

MXM

0.1UF
20%
10V
CERM
402

95 mA (A01)

R2650
18

PP3V3_S0_MCP_DAC

POWER_MCP_DAC
MAKE_BASE=TRUE

107 18
107 18

MCP_HDMI_RSET
MCP_HDMI_VPROBE

C

102 18
102 18

NO STUFF

C2620

1

1

6

2

C2630

2

1%
1/16W
MF-LF
402

0

2

5%
1/16W
MF-LF
402

NO STUFF

NO STUFF

R2620
1K

0.1UF
20%
10V
CERM
402

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

1

1

1

20%
10V
CERM
402

2

C

R2630
1K

0.1UF
2

1%
1/16W
MF-LF
402

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
IG
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640
Apple: ???
30-OHM-1.7A
PP3V3_S0_MCP_VPLL
18

=PP3V3_S0_MCP_VPLL_UF

1

16 mA (A01)

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

2
0402

IG

VOLTAGE=3.3V

16 mA (A01)

IG

C2640

1

1

2

2

4.7UF
20%
6.3V
X5R-CERM
402

C2641
0.1uF
20%
10V
CERM
402

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

116S0004

1

RES,0,5%,402

C2641

MXM

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP Graphics Support
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

A.0.0

7

BRANCH

PAGE

26 OF 110
SHEET

 OF 

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

D

REVISION

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

27 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

RTC Power Sources
PEG POWER ALIAS/OPTION TO GND UNUSED POWER PIN

D2800
BAT54DW-X-G
SOT-363
6

IMAC
Coin-Cell Holder

1K
2

PPVBATT_G3_RTC_R

1

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V

5%
1/16W
MF-LF
402

CRITICAL
1

PP3V3_G3_RTC

NC

6

4

3

C2800
1UF

0.1UF

0.1UF

5

2

10%
6.3V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

NC

NC

21 22

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

R2800

PPVBATT_G3_RTC

D

=PP3V3_S5_RTC_D

NC

J2800

1

2

1

2

1

C2801

2

C2802

25

PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_AVDD1

MXM

R2880

BB10201-C1403-7H
2

0

1

SM

PLACE AT LEAST 1 CAP NEAR MCP PIN A20

511S0054

D

17

2

NOTE: R2800 and D2800 form the doublefault protection for RTC battery.

PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_AVDD0

17 25

MAKE_BASE=TRUE
VOLTAGE=1.05V

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm

UNPOWER PEG INTERFACE WHEN IG IS USED

RTC Crystal
25 6

R2810
RTC_CLK32K_XTALOUT

10M

CRITICAL

5%
50V
CERM
402

Y2810
32.768K-12.5PF
SM-HF

2

17

R2882

2
1

5%
1/16W
MF-LF
402

OUT

=PP1V05_S0_MCP_PEX_DVDD1
MXM

12pF
1

RTC_CLK32K_XTALOUT_R

2

5%
1/16W
MF-LF
402

R28111

103 21

0

1

4

IN

1

103 21

=PP1V05_S0_MCP_PEX_DVDD

C2810

0
5%
1/16W
MF-LF
402

2

PP1V05_S0_MCP_PEX_DVDD0

=PP1V05_S0_MCP_PEX_DVDD0

17 25

MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm

UNPOWER PEG INTERFACE WHEN IG IS USED

C2811
12pF
1

RTC_CLK32K_XTALIN

2
5%
50V
CERM
402

MCP 25MHz Crystal

C

C2815

R2815
103 21

IN

MCP_CLK25M_XTALOUT

0

1

NO STUFF
1

R2816

20PF

5%
1/16W
MF-LF
402

CRITICAL

Y2815

2

1

5%
50V
CERM
402

2

C2816

25.0000M

5%
1/16W
MF-LF
402 2

OUT

1

MCP_CLK25M_XTALOUT_R

2

10M

103 21

C

SATA ALIAS/GROUNDING UNUSED DVDD1 AND AVDD1

SM-3-LF

AVDD IS FILTERED ON P25

20PF
1

MCP_CLK25M_XTALIN

2
5%
50V
CERM
402

25

PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE

=PP1V05_S0_MCP_SATA_AVDD0

20

25

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_SATA_DVDD0

6 20

DVDD DOES NOT NEED FILTER

20

=PP1V05_S0_MCP_SATA_DVDD1

20

=PP1V05_S0_MCP_SATA_AVDD1

Reset Button
49

IN

PM_SYSRST_L
XDP

R2896
13 11

IN

XDP_DBRESET_L

1

0

R2899
33

2

1

5%
1/16W
MF-LF
402

B

10K pull-up to 3.3V S0 inside MCP
PM_SYSRST_DEBOUNCE_L

2
5%
1/16W
MF-LF
402

1

0

21

B

C2899
1UF

NO STUFF

R2898

OUT

NO STUFF
1

2

10%
10V
X5R
402

5%
1/10W
MF-LF
603 2

SILK_PART=RESET_BTN

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

SB Misc
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

28 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Page Notes
MEM A VREF DQ

Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
- =PPVTT_S3_DDR_BUF

DAC channel
Min DAC code
Max DAC code
Max sink I
Max source I
Nominal Vref
Min Vref
Max Vref
Vref Stepping
(per DAC LSB)

Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA

D

BOM options provided by this page:
VREFMRGN
PRODUCTION

MEM A VREF CA

A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV

MEM B VREF DQ

B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV

MEM B VREF CA

A
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV

B
0x00
0x87
-3.75 mA
5 mA
0.75 V
0.375 V
1.250 V
6.5 mV

CPU FSB VREF
C
0x00
0x55
-0.91 mA
0.52 mA
0.70 V
0.091 V
1.044 V
11.2 mV

SO-DIMM A and SO-DIMM B Vref settings should be margined separately
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
=PPVTT_S3_DDR_BUF
6

D

10mA max load

R2903
1

B1
A2

C2903

V+

0.1UF

20%
2 10V
CERM
402

=PP3V3_S3_VREFMRGN
6

U2902

V-

29

B4

VREFMRGN

R2901

C2901
0.1UF

20%
2 6.3V
CERM
402-LF

20%
2 10V
CERM
402
B1
C2

V+

=I2C_VREFDACS_SCL

BI

=I2C_VREFDACS_SDA

6 SCL
7 SDA
9 A0

ADDR=0x98(WR)/0x99(RD)

C

10 A1

V-

VOUTB 2

VREFMRGN_CA_SODIMM

VOUTC 4

VREFMRGN_CPUFSB0

VOUTD 5

VREFMRGN_CPUFSB1

100K
5%
1/16W
MF-LF
402
B1

1

A2

C2904

V+

0.1UF

V-

B1
C2

52

IN
BI

1

=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA

2

SCL
SDA
THRM

B

B4

RESET*

9
10
11
12
13

15

1

R2908
100K

29

5%
1/16W
MF-LF
402

VREFMRGN

29

1

VOLTAGE=0.75V

2

Place close to J3100.126

200

OMIT

2

PP0V75_S3_MEM_VREFCA_B

1

100

32

1%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

VREFMRGN

VOLTAGE=0.75V

2

Place close to J3200.126

VREFMRGN

C2905
0.1UF

29

20%
10V
2 CERM
402

TP_PCA9557_P6
TP_PCA9557_P7

14

31

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

VREFMRGN

1%
1/16W
MF-LF
402

VREFMRGN_CA_SODIMMB_EN

29
29

100

C

PP0V75_S3_MEM_VREFCA_A

R2912

29

OMIT

2

1

VREFMRGN_CPUFSB_EN0
VREFMRGN_CPUFSB_EN1
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_DQ_SODIMMB_EN

7

PCA9557D_RESET_L
IN

9

GND

17

PAD

6

VREFMRGN

VREFMRGN_CA_SODIMMB_BUF

29

PCA9557

5

52

U2903

200

R2911
1

5%
1/16W
MF-LF
402

MAX4253

V-

U2901

A2

V+

R2914

MAX4253

UCSP
A1
VREFMRGN
A3

B

U2904

B1

8

ADDR=0x30(WR)/0x31(RD)

Place close to J3200.1

1%
1/16W
MF-LF
402

VREFMRGN_CA_SODIMMA_EN

C4

C3

P0
P1
P2
P3
P4
P5
P6
P7

2

1

VREFMRGN_CPUFSB_BUF0

29

B4

VREFMRGN_CPUFSB_EN0

R2913

FSB_VREFMRGN

CPU_GTLREF0

2

1%
1/16W
MF-LF
402

A4

V-

100

OUT

10 11 100

OUT

10 11 100

PLACE CLOSE TO U1000

2

16

VREFMRGN

1

VREFMRGN_CA_SODIMMA_BUF

29

UCSP
C1
VREFMRGN

VCC

QFN

VOLTAGE=0.75V

2

VREFMRGN

V+

4

100

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

VREFMRGN

1%
1/16W
MF-LF
402

A4

A3

100K

A0
A1
A2

32

R2910

R2907

3

1

MAX4253

B4

0.1UF

PP0V75_S3_MEM_VREFDQ_B

R2909
VREFMRGN

U2903

UCSP
A1
VREFMRGN

20%
10V
2 CERM
402

C2902

OMIT

2

1%
1/16W
MF-LF
402

VREFMRGN_DQ_SODIMMB_EN

R2902

GND
3

20%
2 10V
CERM
402

Place close to J3100.1

VREFMRGN_DQ_SODIMM

VREFMRGN

1

1

VREFMRGN_DQ_SODIMMB_BUF

29

B4

2

R2906

C4

C3

200

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

1%
1/16W
MF-LF
402

1

52

IN

DAC5574

52

5%
1/16W
MF-LF
402

VREFMRGN

MAX4253

UCSP
C1
VREFMRGN

VREFMRGN
8 U2900
VDD
MSOP VOUTA 1

U2902

31

R2905
1

100K
1

1

2.2UF

VREFMRGN_DQ_SODIMMA_EN

2

C2900

100

VREFMRGN

1%
1/16W
MF-LF
402

2

VREFMRGN
1

1

VREFMRGN_DQ_SODIMMA_BUF

A4

A3

PP0V75_S3_MEM_VREFDQ_A

R2904

MAX4253

UCSP
A1
VREFMRGN

OMIT

2

1%
1/16W
MF-LF
402

2

VREFMRGN
1

200

100K

VREFMRGN

1

5%
1/16W
MF-LF
402

U2904

B1
C2

V+

VREFMRGN

29

VREFMRGN_CPUFSB_EN1

R2915

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

114S0149

1

RES,MTL FILM,200,1%,0402,SM,LF

R2903

CRITICAL

VREFMRGN

116S0004

1

RES,MTL FILM,0,5%,0402,SM,LF

R2903

CRITICAL

PRODUCTION

114S0149

1

RES,MTL FILM,200,1%,0402,SM,LF

R2905

CRITICAL

VREFMRGN

116S0004

1

RES,MTL FILM,0,5%,0402,SM,LF

R2905

CRITICAL

PRODUCTION

114S0149

1

RES,MTL FILM,200,1%,0402,SM,LF

R2909

CRITICAL

VREFMRGN

116S0004

1

RES,MTL FILM,0,5%,0402,SM,LF

R2909

CRITICAL

PRODUCTION

114S0149

1

RES,MTL FILM,200,1%,0402,SM,LF

R2911

CRITICAL

VREFMRGN

116S0004

1

RES,MTL FILM,0,5%,0402,SM,LF

R2911

CRITICAL

PRODUCTION

100K

BOM OPTION

100

1%
1/16W
MF-LF
402

FSB_VREFMRGN

CPU_GTLREF1

2

PLACE CLOSE TO U1000

5%
1/16W
MF-LF
402

VREFMRGN

1

PART NUMBER

1

VREFMRGN_CPUFSB_BUF1

C4

VB4

Required zero ohm resistors when no VREF margining circuit stuffed

A

UCSP
C1

2

C3

R2916

MAX4253

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

FSB/DDR3 Vref Margining
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

29 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

DIMM A (FURTHER FROM MCP)
30 25 16 6

5

CAPS TO COUPLE MCP 1V5_S0_MEM
30 25 16 6

=PP1V8R1V5_S0_MCP_MEM

C3016
0.1UF

20%
10V
2 CERM
402

1

C3017
0.1UF

20%
10V
2 CERM
402

1

C3018
0.1UF

20%
2 10V
CERM
402

1

C3019
0.1UF

20%
2 10V
CERM
402

1

3

2

1

DIMM B (CLOSER TO MCP)

=PP1V8R1V5_S0_MCP_MEM

1
1

4

C3010
0.1UF

C3025
0.1UF
20%

10V
2 CERM
402

20%
2 10V
CERM
402

1

C3026

1

0.1UF

20%
10V
2 CERM
402

C3027
0.1UF
20%

10V
2 CERM
402

1

C3028
0.1UF
20%

10V
2 CERM
402

1

1

C3029
0.1UF

20%
10V
2 CERM
402

C3020
0.1UF

20%
10V
2 CERM
402

1

C3021
0.1UF

20%
10V
2 CERM
402

1

C3022
0.1UF
20%

10V
2 CERM
402

1

C3023
0.1UF

20%
10V
2 CERM
402

1

C3014
0.1UF

20%
10V
2 CERM
402

1

C3030
0.1UF

20%
10V
2 CERM
402

1

C3031
0.1UF

20%
10V
2 CERM
402

1

C3032
0.1UF

20%
10V
2 CERM
402

1

C3033
0.1UF

20%
10V
2 CERM
402

1

1

C3034
0.1UF
20%

C3035
0.1UF

20%
10V
2 CERM
402

10V
2 CERM
402

D

D
EXTRA DECOUPLING CAPS FOR MCP MEM RAIL
30 25 16 6

=PP1V8R1V5_S0_MCP_MEM
4771 mA (A01, DDR3)
1
1

1

C3042

1

C3044

C3046

0.1UF

0.1UF

0.1UF

0.1UF

20%
10V
CERM
402

2

20%
10V
CERM
402

2

20%
10V
CERM
402

20%
10V
CERM
402

1

C30A1

1

C30A2

2

16 6
30 25

1

C3041

2

C3040

1

1UF

C3043

1

1UF

10%
6.3V
2 CERM
402

C3045

1

1UF

10%
2 6.3V
CERM
402

C3047

1

1UF

10%
2 6.3V
CERM
402

C3048

1

1UF

10%
2 6.3V
CERM
402

C3049

1

1UF

10%
2 6.3V
CERM
402

C3090

1

1UF

10%
2 6.3V
CERM
402

C3091

1

1UF

10%
2 6.3V
CERM
402

C3092

1

1UF

10%
2 6.3V
CERM
402

C3093

1

1UF

10%
2 6.3V
CERM
402

C3094

1

1UF

10%
2 6.3V
CERM
402

C3095

1

1UF

10%
2 6.3V
CERM
402

C3096

1

C3097

1

1UF

1UF

10%
2 6.3V
CERM
402

C3098
1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

1

C3099

1

1UF

C3000

1

1UF

10%
6.3V
2 CERM
402

C3001

1

C3002
1UF

1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

1

1

=PP1V8R1V5_S0_MCP_MEM
4771 mA (A01, DDR3)
1

C30A0
1UF

1

1UF

1UF

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

1

C30A3
1UF

10%
2 6.3V
CERM
402

1

C30A4
1UF

10%
2 6.3V
CERM
402

1

C30A5
1UF

1

C30A6

1

C30A7
1UF

1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

1

C30A8
1UF

10%
2 6.3V
CERM
402

1

C30A9
1UF

10%
6.3V
2 CERM
402

1

C30AA

1

C30AB
1UF

1UF

10%
2 6.3V
CERM
402

1

C30AC
1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

1

C30AD
1UF

10%
2 6.3V
CERM
402

1

C30AE
1UF

10%
2 6.3V
CERM
402

C30AF

1

10%
2 6.3V
CERM
402

C30B0
1UF

1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

1

C30B1
1UF

10%
2 6.3V
CERM
402

1

C30B2
1UF

10%
2 6.3V
CERM
402

1

C30B3

1

C30B4

1UF

1UF

10%
2 6.3V
CERM
402

C30B5
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C30B6
1UF

10%
2 6.3V
CERM
402

1

C30B7
1UF

10%
2 6.3V
CERM
402

C

C
25 16 6 =PP1V8R1V5_S0_MCP_MEM
30 4771 mA (A01, DDR3)

1

1

C30B8
1UF

1

C30B9
1UF

1

C30BA
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

1

C30BB
1UF

10%
6.3V
2 CERM
402

1

C30BC

C30BD
1UF

1UF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

B

B

DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR
31 108 6

=PP1V5_S3_MEM_A

1

C3050

1

10UF
2

1

C3051

2

1

C3052
1UF

10UF

20%
6.3V
X5R
603

1

C3053

1

C3054
1UF

1UF

10%
6.3V
2 CERM
402

20%
6.3V
X5R
603

10%
6.3V
2 CERM
402

1

C3055
1UF

10%
6.3V
2 CERM
402

1

C3056
1UF

10%
6.3V
2 CERM
402

1

C3057
1UF

10%
6.3V
2 CERM
402

1

C3058
1UF

10%
6.3V
2 CERM
402

1

C3059
1UF

10%
6.3V
2 CERM
402

1

C3060
1UF

10%
6.3V
2 CERM
402

1

C3061
1UF

10%
6.3V
2 CERM
402

1

C3062
1UF

10%
6.3V
2 CERM
402

1

C3063
1UF

10%
6.3V
2 CERM
402

1

C3064
1UF

10%
6.3V
2 CERM
402

C3065
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

A

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE
32 108 6

MEMORY CAPS

=PP1V5_S3_MEM_B

DRAWING NUMBER
1

C3070

1

10UF
2

20%
6.3V
X5R
603

1

C3071

2

C3072
1UF

10UF

10%
6.3V
2 CERM
402

20%
6.3V
X5R
603

1

C3073
1UF

10%
6.3V
2 CERM
402

1

C3074
1UF

10%
6.3V
2 CERM
402

1

C3075
1UF

10%
6.3V
2 CERM
402

1

C3076
1UF

10%
6.3V
2 CERM
402

1

C3077
1UF

10%
6.3V
2 CERM
402

1

C3078
1UF

10%
6.3V
2 CERM
402

1

C3079
1UF

10%
6.3V
2 CERM
402

1

C3080
1UF

10%
6.3V
2 CERM
402

1

C3081
1UF

10%
6.3V
2 CERM
402

1

C3082
1UF

1

C3083
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

1

C3084
1UF

10%
6.3V
2 CERM
402

1

Apple Inc.

C3085

051-7863

10%
6.3V
2 CERM
402

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

1UF

SIZE

BRANCH

PAGE

30 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

=MEM_A_DM<0>

33 31

33 31
33 31

D
33 31
33 31

33 31
33 31

33 31
33 31

33 31
33 31

33 31
33 31

=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<24>
=MEM_A_DQ<25>

33 31

=MEM_A_DM<3>

33 31
33 31

101 15
108 31 30 6

101 31 15

101 31 15
101 31 15

101 31 15
101 31 15

101 31 15
101 31 15

33
33

101 31 15
101 31 15

101 31 15
101 31 15

101 31 15
101 15

33 31
33 31

33 31
33 31

33 31
33 31

33 31
33 31

33 31

33 31
33 31

33 31
33 31

33 31
33 31

33 31
33 31

A

=MEM_A_DQ<8>
=MEM_A_DQ<9>

33 31

33 31

B

=MEM_A_DQ<2>
=MEM_A_DQ<3>

33 31
33 31

33 31

33 31
33 31

31
31 6
31
31 6

=MEM_A_DQ<26>
=MEM_A_DQ<27>

MEM_A_CKE<0>
=PP1V5_S3_MEM_A
MEM_A_BA<2>
MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
=MEM_A_CLK_P<0>
=MEM_A_CLK_N<0>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<1>

=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<40>
=MEM_A_DQ<41>
=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DQ<50>
=MEM_A_DQ<51>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_DIMM0_SA<0>
=PPSPD_S0_MEM_A
MEM_DIMM0_SA<1>
=PP0V75_S0_MEM_VTT_A

73A
75A
77A
79A
81A
83A
85A
87A
89A
91A
93A
95A
97A
99A
101A
103A
105A
107A
109A
111A
113A
115A
117A
119A
121A
123A
125A
127A
129A
131A
133A
135A
137A
139A
141A
143A
145A
147A
149A
151A
153A
155A
157A
159A
161A
163A
165A
167A
169A
171A
173A
175A
177A
179A
181A
183A
185A
187A
189A
191A
193A
195A
197A
199A
201A
203A
409

8

J3100

MTG PIN

MTG PIN

7

2A
4A
6A
8A
10A
12A
14A
16A
18A
20A
22A
24A
26A
28A
30A
32A
34A
36A
38A
40A
42A
44A
46A
48A
50A
52A
54A
56A
58A
60A
62A
64A
66A
68A
70A
72A
74A
76A
78A
80A
82A
84A
86A
88A
90A
92A
94A
96A
98A
100A
102A
104A
106A
108A
110A
112A
114A
116A
118A
120A
122A
124A
126A
128A
130A
132A
134A
136A
138A
140A
142A
144A
146A
148A
150A
152A
154A
156A
158A
160A
162A
164A
166A
168A
170A
172A
174A
176A
178A
180A
182A
184A
186A
188A
190A
192A
194A
196A
198A
200A
202A
204A

5
31 29

=MEM_A_DQ<4>
=MEM_A_DQ<5>

PP0V75_S3_MEM_VREFDQ_A

31 33

33 31

=MEM_A_DQ<0>
=MEM_A_DQ<1>

31 33

33 31

=MEM_A_DM<0>

31 33

33 31

31 33

33 31

31 33

=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>

33 31

31 33

=MEM_A_DQ<6>
=MEM_A_DQ<7>
=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DM<1>
MEM_RESET_L
=MEM_A_DQ<14>
=MEM_A_DQ<15>
=MEM_A_DQ<20>
=MEM_A_DQ<21>
=MEM_A_DM<2>

31 33

33 31

31 33

33 31

31 33

33 31

31 32 33

33 31

31 33

33 31

31 33

33 31

31 33

33 31

31 33

33 31

31 33

33 31
33 31

=MEM_A_DQ<22>
=MEM_A_DQ<23>

=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DQ<10>
=MEM_A_DQ<11>
=MEM_A_DQ<16>
=MEM_A_DQ<17>
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>

31 33
31 33

33 31
33 31

=MEM_A_DQ<28>
=MEM_A_DQ<29>

=MEM_A_DQ<18>
=MEM_A_DQ<19>

31 33
31 33

=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>

33 31

=MEM_A_DQ<24>
=MEM_A_DQ<25>

33 31

=MEM_A_DM<3>

33 31

31 33
31 33

=MEM_A_DQ<30>
=MEM_A_DQ<31>

MEM_A_CKE<1>
=PP1V5_S3_MEM_A
MEM_A_A<15>
MEM_A_A<14>

31 33

33 31

31 33

33 31

15 101
6 30 31 108

101 16
108 31 30 6

=MEM_A_DQ<26>
=MEM_A_DQ<27>

MEM_A_CKE<2>
=PP1V5_S3_MEM_A

31 33
15 31 101

MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>
MEM_A_A<2>
MEM_A_A<0>

15 31 101

101 31 15

15 31 101

101 31 15

15 31 101

101 31 15

15 31 101

101 31 15

15 31 101

101 31 15

15 31 101

=MEM_A_CLK_P<1>
=MEM_A_CLK_N<1>
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_ODT<1>

101 31 15

101 31 15

33

33

33

33

15 31 101

101 31 15

15 31 101

101 31 15

15 101

101 31 15

15 101

101 31 15

15 101

101 31 15
101 16

PP0V75_S3_MEM_VREFCA_A
=MEM_A_DQ<36>
=MEM_A_DQ<37>
=MEM_A_DM<4>

MEM_A_A<12>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<1>
=MEM_A_CLK_P<2>
=MEM_A_CLK_N<2>
MEM_A_A<10>
MEM_A_BA<0>
MEM_A_WE_L
MEM_A_CAS_L
MEM_A_A<13>
MEM_A_CS_L<3>

29 31

31 33

33 31

31 33

33 31

31 33

33 31
33 31

=MEM_A_DQ<38>
=MEM_A_DQ<39>

MEM_A_BA<2>

=MEM_A_DQ<32>
=MEM_A_DQ<33>
=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>

31 33
31 33

33 31
33 31

=MEM_A_DQ<44>
=MEM_A_DQ<45>

=MEM_A_DQ<34>
=MEM_A_DQ<35>

31 33
31 33

33 31
33 31

=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>

=MEM_A_DQ<40>
=MEM_A_DQ<41>

31 33

=MEM_A_DQ<46>
=MEM_A_DQ<47>
=MEM_A_DQ<52>
=MEM_A_DQ<53>
=MEM_A_DM<6>

31 33

33 31

31 33

33 31

31 33

33 31

31 33

33 31

31 33

33 31

31 33

33 31
33 31

=MEM_A_DQ<54>
=MEM_A_DQ<55>

=MEM_A_DM<5>
=MEM_A_DQ<42>
=MEM_A_DQ<43>
=MEM_A_DQ<48>
=MEM_A_DQ<49>
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>

31 33
31 33

33 31
33 31

=MEM_A_DQ<60>
=MEM_A_DQ<61>

=MEM_A_DQ<50>
=MEM_A_DQ<51>

31 33
31 33

33 31
33 31

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

31 33

=MEM_A_DQ<62>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=PP0V75_S0_MEM_VTT_A

31 33

33 31

31 33

33 31

31 33

33 31

21 31 32 49 55
31 52
31 52
6 31

31
31 6
31
31 6

=MEM_A_DM<7>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_DIMM2_SA<0>
=PPSPD_S0_MEM_A
MEM_DIMM2_SA<1>
=PP0V75_S0_MEM_VTT_A

4
1B
3B
5B
7B
9B
11B
13B
15B
17B
19B
21B
23B
25B
27B
29B
31B
33B
35B
37B
39B
41B
43B
45B
47B
49B
51B
53B
55B
57B
59B
61B
63B
65B
67B
69B
71B
73B
75B
77B
79B
81B
83B
85B
87B
89B
91B
93B
95B
97B
99B
101B
103B
105B
107B
109B
111B
113B
115B
117B
119B
121B
123B
125B
127B
129B
131B
133B
135B
137B
139B
141B
143B
145B
147B
149B
151B
153B
155B
157B
159B
161B
163B
165B
167B
169B
171B
173B
175B
177B
179B
181B
183B
185B
187B
189B
191B
193B
195B
197B
199B
201B
203B

VSS_0
VREFDQ
VSS_1
DQ4
DQ0
DQ5
F-RT-TH
VSS_2
DQ1
(2 OF 2)
VSS_3
DQS0*
CRITICAL
DM0
DQS0
VSS_4
VSS_5
DQ2
DQ6
DQ3
DQ7
VSS_6
VSS_7
DQ12
DQ8
DQ9
DQ13
VSS_8
VSS_9
DM1
DQS1*
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ15
DQ11
VSS_13
VSS_12
DQ20
DQ16
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
VSS_16
DQS2
DQ22
VSS_17
DQ23
DQ18
VSS_18
DQ19
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DM3
DQS3
VSS_22
VSS_23
DQ30
DQ26
DQ27
DQ31
VSS_24
VSS_25
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A7
A9
VDD_4
VDD_5
A6
A8
A5
A4
VDD_7
VDD_6
A3
A2
A1
A0
VDD_9
VDD_8
CK0
CK1
CK1*
CK0*
VDD_10
VDD_11
A10_AP
BA1
RAS*
BA0
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
ODT1
A13
S1*
NC_1
VDD_16
VDD_17
VREFCA
TEST
VSS_26
VSS_27
DQ32
DQ36
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
VSS_30
DQS4
DQ38
VSS_31
DQ39
DQ34
DQ35
VSS_32
DQ44
VSS_33
DQ40
DQ45
VSS_34
DQ41
VSS_35
DQS5*
DM5
DQS5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ52
DQ48
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
VSS_42
DQS6
DQ54
VSS_43
DQ55
DQ50
VSS_44
DQ51
DQ60
VSS_45
DQ61
DQ56
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ63
DQ59
VSS_50
VSS_51
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT_0
VTT_1

J3100
DDR3-SODIMM-DUAL

33 31

VREFDQ
VSS_0
VSS_1CRITICAL DQ4
DQ0
DQ5
F-RT-TH
VSS_2
DQ1
(1 OF 2)
VSS_3
DQS0*
DQS0
DM0
VSS_4
VSS_5
DQ2
DQ6
DQ3
DQ7
VSS_7
VSS_6
DQ8
DQ12
DQ9
DQ13
VSS_8
VSS_9
DQS1*
DM1
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ11
DQ15
VSS_12
VSS_13
DQ16
DQ20
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
DQS2
VSS_16
VSS_17
DQ22
DQ18
DQ23
DQ19
VSS_18
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DQS3
DM3
VSS_22
VSS_23
DQ30
DQ26
DQ31
DQ27
VSS_25
VSS_24
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A9
A7
VDD_4
VDD_5
A6
A8
A5
A4
VDD_7
VDD_6
A2
A3
A0
A1
VDD_8
VDD_9
CK0
CK1
CK0*
CK1*
VDD_10
VDD_11
A10_AP
BA1
BA0
RAS*
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
A13
ODT1
S1*
NC_1
VDD_17
VDD_16
VREFCA
TEST
VSS_27
VSS_26
DQ36
DQ32
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
VSS_30
DQS4
DQ38
VSS_31
DQ39
DQ34
DQ35
VSS_32
VSS_33
DQ44
DQ40
DQ45
DQ41
VSS_34
VSS_35
DQS5*
DQS5
DM5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ48
DQ52
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
DQS6
VSS_42
VSS_43
DQ54
DQ50
DQ55
DQ51
VSS_44
VSS_45
DQ60
DQ56
DQ61
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ63
DQ59
VSS_50
VSS_51
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT_0
VTT_1

DDR3-SODIMM-DUAL

33 31

33 31

C

PP0V75_S3_MEM_VREFDQ_A
=MEM_A_DQ<0>
=MEM_A_DQ<1>

33 31

6

DIMM 0

31 29

7
1A
3A
5A
7A
9A
11A
13A
15A
17A
19A
21A
23A
25A
27A
29A
31A
33A
35A
37A
39A
41A
43A
45A
47A
49A
51A
53A
55A
57A
59A
61A
63A
65A
67A
69A
71A

DIMM 2

8

2B
4B
6B
8B
10B
12B
14B
16B
18B
20B
22B
24B
26B
28B
30B
32B
34B
36B
38B
40B
42B
44B
46B
48B
50B
52B
54B
56B
58B
60B
62B
64B
66B
68B
70B
72B

3
=MEM_A_DQ<4>
=MEM_A_DQ<5>
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>

2

31 33

DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD)

=MEM_A_DQ<12>
=MEM_A_DQ<13>
=MEM_A_DM<1>
MEM_RESET_L

31

MEM_DIMM0_SA<1>

31

MEM_DIMM0_SA<0>

31 33

31 6

=PPSPD_S0_MEM_A

31 33

1

31 33
31 33

31 33

1

R3140

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

2

31

MEM_DIMM2_SA<1>

31

MEM_DIMM2_SA<0>

D

31 33
31 32 33

31 33

31 33

=PPSPD_S0_MEM_A

31 33
1

=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>

MEM_A_CKE<3>
=PP1V5_S3_MEM_A
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<11>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4>

C3140
2.2UF

31 33
31 33

20%
6.3V
CERM
402-LF

2

31 33
31 33

31 33
31 33
31 29

=MEM_A_DQ<30>
=MEM_A_DQ<31>

PP0V75_S3_MEM_VREFCA_A

31 33
31 33

C3135

1

C3136

2.2UF

16 101
6 30 31 108

0.1UF

20%
6.3V
CERM
402-LF

2

31 33

20%
10V
CERM
402

2

15 31 101
31 29

15 31 101

PP0V75_S3_MEM_VREFDQ_A

15 31 101
15 31 101

1

15 31 101
2
15 31 101

=MEM_A_CLK_P<3>
=MEM_A_CLK_N<3>

33

MEM_A_BA<1>
MEM_A_RAS_L

15 31 101

MEM_A_CS_L<2>
MEM_A_ODT<2>

C3130

1

C3131
20%
10V
CERM
402

2

31 6

=PP0V75_S0_MEM_VTT_A

15 31 101

1

16 101

16 101

29 31

=MEM_A_DQ<36>
=MEM_A_DQ<37>

31 33

=MEM_A_DM<4>

31 33

=MEM_A_DQ<38>
=MEM_A_DQ<39>

31 33

C3150

1

2.2UF

16 101

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<44>
=MEM_A_DQ<45>

0.1UF

20%
6.3V
CERM
402-LF

33

2

MEM_A_ODT<3>

C

15 31 101

2.2UF

MEM_A_A<2>
MEM_A_A<0>

5%
1/16W
MF-LF
402

31 33

31 6

=MEM_A_DM<2>

R3143
10K

31 33

2

=MEM_A_DQ<20>
=MEM_A_DQ<21>

5%
1/16W
MF-LF
402

31 33

1

=MEM_A_DQ<14>
=MEM_A_DQ<15>

R3142
10K

R3141

10K

1

74B
76B
78B
80B
82B
84B
86B
88B
90B
92B
94B
96B
98B
100B
102B
104B
106B
108B
110B
112B
114B
116B
118B
120B
122B
124B
126B
128B
130B
132B
134B
136B
138B
140B
142B
144B
146B
148B
150B
152B
154B
156B
158B
160B
162B
164B
166B
168B
170B
172B
174B
176B
178B
180B
182B
184B
186B
188B
190B
192B
194B
196B
198B
200B
202B
204B

DIMM2 SPD ADDR=0XA4(WR)/0XA5(RD)

31 33

1

=MEM_A_DQ<6>
=MEM_A_DQ<7>

1

C3151
2.2UF

20%
6.3V
CERM
402-LF

2

20%
6.3V
CERM
402-LF

B

31 33

31 33

Page Notes

31 33

Power aliases required by this page:

31 33

- =PP1V5_S0_MEM_A

=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>

31 33

- =PP1V5_S3_MEM_A

31 33

- =PP0V75_S0_MEM_VTT_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)

=MEM_A_DQ<46>
=MEM_A_DQ<47>

31 33

Signal aliases required by this page:
31 33

- =I2C_SODIMMA_SCL

=MEM_A_DQ<52>
=MEM_A_DQ<53>

- ALL DQ, DQS, DM SIGNALS;
TO FACILITATE BITSWAPS WITH ALIASES

- =I2C_SODIMMA_SDA
31 33

BOM options provided by this page:

31 33

(NONE)

=MEM_A_DM<6>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<60>
=MEM_A_DQ<61>

31 33

31 33
31 33

31 33
31 33

SYNC_MASTER=K22

SYNC_DATE=07/06/2009

A

PAGE TITLE

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>

DDR3 SO-DIMMs 0 & 2

31 33
31 33

DRAWING NUMBER

=MEM_A_DQ<62>
=MEM_A_DQ<63>
MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=PP0V75_S0_MEM_VTT_A

Apple Inc.

31 33
31 33

051-7863

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

21 31 32 49 55

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

31 52
31 52
6 31

PAGE

31 OF 110
SHEET

 OF 

410

6

5

4

3

2

1

33 32

33 32
33 32

33 32
33 32

D
33 32
33 32

33 32
33 32

33 32
33 32

33 32
33 32

33 32
33 32

33 32
33 32

33 32

33 32
33 32

101 15

C

108 32 30 6

101 32 15

101 32 15
101 32 15

101 32 15
101 32 15

101 32 15
101 32 15

33
33

101 32 15
101 32 15

101 32 15
101 32 15

101 32 15
101 15

B

33 32
33 32

33 32
33 32

33 32
33 32

33 32
33 32

33 32

33 32
33 32

33 32
33 32

33 32
33 32

33 32
33 32

A

33 32
33 32

33 32

33 32
33 32

32
32 6
32
32 6

=MEM_B_DQ<0>
=MEM_B_DQ<1>
=MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DQ<18>
=MEM_B_DQ<19>
=MEM_B_DQ<24>
=MEM_B_DQ<25>
=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<27>

MEM_B_CKE<0>
=PP1V5_S3_MEM_B
MEM_B_BA<2>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
=MEM_B_CLK_P<0>
=MEM_B_CLK_N<0>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<1>

=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DM<5>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<56>
=MEM_B_DQ<57>
=MEM_B_DM<7>
=MEM_B_DQ<58>
=MEM_B_DQ<59>
MEM_DIMM1_SA<0>
=PPSPD_S0_MEM_B
MEM_DIMM1_SA<1>
=PP0V75_S0_MEM_VTT_B

73A
75A
77A
79A
81A
83A
85A
87A
89A
91A
93A
95A
97A
99A
101A
103A
105A
107A
109A
111A
113A
115A
117A
119A
121A
123A
125A
127A
129A
131A
133A
135A
137A
139A
141A
143A
145A
147A
149A
151A
153A
155A
157A
159A
161A
163A
165A
167A
169A
171A
173A
175A
177A
179A
181A
183A
185A
187A
189A
191A
193A
195A
197A
199A
201A
203A
409

8

VREFDQ
VSS_0
VSS_1CRITICAL DQ4
DQ0
DQ5
F-RT-TH
VSS_2
DQ1
(1 OF 2)
VSS_3
DQS0*
DQS0
DM0
VSS_4
VSS_5
DQ2
DQ6
DQ3
DQ7
VSS_7
VSS_6
DQ8
DQ12
DQ9
DQ13
VSS_8
VSS_9
DQS1*
DM1
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ11
DQ15
VSS_12
VSS_13
DQ16
DQ20
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
DQS2
VSS_16
VSS_17
DQ22
DQ18
DQ23
DQ19
VSS_18
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DQS3
DM3
VSS_22
VSS_23
DQ30
DQ26
DQ31
DQ27
VSS_25
VSS_24
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A9
A7
VDD_4
VDD_5
A6
A8
A5
A4
VDD_7
VDD_6
A2
A3
A0
A1
VDD_8
VDD_9
CK0
CK1
CK0*
CK1*
VDD_10
VDD_11
A10_AP
BA1
BA0
RAS*
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
A13
ODT1
S1*
NC_1
VDD_17
VDD_16
VREFCA
TEST
VSS_27
VSS_26
DQ36
DQ32
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
VSS_30
DQS4
DQ38
VSS_31
DQ39
DQ34
DQ35
VSS_32
VSS_33
DQ44
DQ40
DQ45
DQ41
VSS_34
VSS_35
DQS5*
DQS5
DM5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ48
DQ52
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
DQS6
VSS_42
VSS_43
DQ54
DQ50
DQ55
DQ51
VSS_44
VSS_45
DQ60
DQ56
DQ61
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ63
DQ59
VSS_50
VSS_51
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT_0
VTT_1

J3200

MTG PIN

MTG PIN

7

2A
4A
6A
8A
10A
12A
14A
16A
18A
20A
22A
24A
26A
28A
30A
32A
34A
36A
38A
40A
42A
44A
46A
48A
50A
52A
54A
56A
58A
60A
62A
64A
66A
68A
70A
72A
74A
76A
78A
80A
82A
84A
86A
88A
90A
92A
94A
96A
98A
100A
102A
104A
106A
108A
110A
112A
114A
116A
118A
120A
122A
124A
126A
128A
130A
132A
134A
136A
138A
140A
142A
144A
146A
148A
150A
152A
154A
156A
158A
160A
162A
164A
166A
168A
170A
172A
174A
176A
178A
180A
182A
184A
186A
188A
190A
192A
194A
196A
198A
200A
202A
204A

5
32 29

=MEM_B_DQ<4>
=MEM_B_DQ<5>

PP0V75_S3_MEM_VREFDQ_B

32 33
32 33

33 32
33 32

=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>

=MEM_B_DQ<0>
=MEM_B_DQ<1>

32 33
32 33

=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DM<2>

33 32

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32

31 32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32
33 32

=MEM_B_DQ<22>
=MEM_B_DQ<23>

=MEM_B_DM<0>
=MEM_B_DQ<2>
=MEM_B_DQ<3>
=MEM_B_DQ<8>
=MEM_B_DQ<9>
=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>

32 33
32 33

33 32
33 32

=MEM_B_DQ<28>
=MEM_B_DQ<29>

=MEM_B_DQ<18>
=MEM_B_DQ<19>

32 33
32 33

33 32
33 32

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>

=MEM_B_DQ<24>
=MEM_B_DQ<25>

32 33
32 33

=MEM_B_DQ<30>
=MEM_B_DQ<31>

MEM_B_CKE<1>
=PP1V5_S3_MEM_B
MEM_B_A<15>
MEM_B_A<14>

33 32

32 33

33 32

32 33

33 32

15 101
6 30 32 108

101 16
108 32 30 6

=MEM_B_DM<3>
=MEM_B_DQ<26>
=MEM_B_DQ<27>

MEM_B_CKE<2>
=PP1V5_S3_MEM_B

32 33
15 32 101

MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
=MEM_B_CLK_P<1>
=MEM_B_CLK_N<1>
MEM_B_BA<1>
MEM_B_RAS_L

15 32 101

101 32 15

15 32 101

101 32 15

15 32 101

101 32 15

15 32 101

101 32 15

15 32 101

101 32 15

15 32 101

101 32 15

33

33

33

33

15 32 101

MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_ODT<1>

101 32 15

101 32 15

15 32 101

101 32 15

15 101

101 32 15

15 101

101 32 15

15 101

101 32 15
101 16

PP0V75_S3_MEM_VREFCA_B
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DM<4>

MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
=MEM_B_CLK_P<2>
=MEM_B_CLK_N<2>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<13>
MEM_B_CS_L<3>

29 32

32 33

33 32

32 33

33 32

32 33

33 32
33 32

=MEM_B_DQ<38>
=MEM_B_DQ<39>

MEM_B_BA<2>

=MEM_B_DQ<32>
=MEM_B_DQ<33>
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>

32 33
32 33

33 32
33 32

=MEM_B_DQ<44>
=MEM_B_DQ<45>

=MEM_B_DQ<34>
=MEM_B_DQ<35>

32 33
32 33

33 32
33 32

=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

32 33

=MEM_B_DQ<46>
=MEM_B_DQ<47>
=MEM_B_DQ<52>
=MEM_B_DQ<53>
=MEM_B_DM<6>

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32

32 33

33 32
33 32

=MEM_B_DQ<54>
=MEM_B_DQ<55>

=MEM_B_DM<5>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<48>
=MEM_B_DQ<49>
=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>

32 33
32 33

33 32
33 32

=MEM_B_DQ<60>
=MEM_B_DQ<61>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

32 33
32 33

33 32
33 32

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>

=MEM_B_DQ<56>
=MEM_B_DQ<57>

32 33

=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=PP0V75_S0_MEM_VTT_B

32 33

33 32

32 33

33 32

32 33

33 32

21 31 32 49 55
32 52
32 52
6 32

32
32 6
32
32 6

=MEM_B_DM<7>
=MEM_B_DQ<58>
=MEM_B_DQ<59>
MEM_DIMM3_SA<0>
=PPSPD_S0_MEM_B
MEM_DIMM3_SA<1>
=PP0V75_S0_MEM_VTT_B

4
1B
3B
5B
7B
9B
11B
13B
15B
17B
19B
21B
23B
25B
27B
29B
31B
33B
35B
37B
39B
41B
43B
45B
47B
49B
51B
53B
55B
57B
59B
61B
63B
65B
67B
69B
71B
73B
75B
77B
79B
81B
83B
85B
87B
89B
91B
93B
95B
97B
99B
101B
103B
105B
107B
109B
111B
113B
115B
117B
119B
121B
123B
125B
127B
129B
131B
133B
135B
137B
139B
141B
143B
145B
147B
149B
151B
153B
155B
157B
159B
161B
163B
165B
167B
169B
171B
173B
175B
177B
179B
181B
183B
185B
187B
189B
191B
193B
195B
197B
199B
201B
203B

VSS_0
VREFDQ
VSS_1CRITICAL DQ4
DQ0
DQ5
F-RT-TH
VSS_2
DQ1
(2 OF 2)
VSS_3
DQS0*
DM0
DQS0
VSS_4
VSS_5
DQ2
DQ6
DQ3
DQ7
VSS_6
VSS_7
DQ12
DQ8
DQ9
DQ13
VSS_8
VSS_9
DM1
DQS1*
DQS1
RESET*
VSS_10
VSS_11
DQ10
DQ14
DQ15
DQ11
VSS_13
VSS_12
DQ20
DQ16
DQ17
DQ21
VSS_14
VSS_15
DQS2*
DM2
VSS_16
DQS2
DQ22
VSS_17
DQ23
DQ18
VSS_18
DQ19
VSS_19
DQ28
DQ24
DQ29
DQ25
VSS_20
VSS_21
DQS3*
DM3
DQS3
VSS_22
VSS_23
DQ30
DQ26
DQ27
DQ31
VSS_24
VSS_25
KEY
CKE0
CKE1
VDD_0
VDD_1
NC_0
A15
BA2
A14
VDD_2
VDD_3
A12/BC*
A11
A7
A9
VDD_4
VDD_5
A6
A8
A5
A4
VDD_7
VDD_6
A3
A2
A1
A0
VDD_9
VDD_8
CK0
CK1
CK1*
CK0*
VDD_10
VDD_11
A10_AP
BA1
RAS*
BA0
VDD_12
VDD_13
WE*
S0*
CAS*
ODT0
VDD_14
VDD_15
ODT1
A13
S1*
NC_1
VDD_16
VDD_17
VREFCA
TEST
VSS_26
VSS_27
DQ32
DQ36
DQ33
DQ37
VSS_28
VSS_29
DQS4*
DM4
VSS_30
DQS4
DQ38
VSS_31
DQ39
DQ34
DQ35
VSS_32
DQ44
VSS_33
DQ40
DQ45
VSS_34
DQ41
VSS_35
DQS5*
DM5
DQS5
VSS_36
VSS_37
DQ42
DQ46
DQ43
DQ47
VSS_38
VSS_39
DQ52
DQ48
DQ49
DQ53
VSS_40
VSS_41
DQS6*
DM6
VSS_42
DQS6
DQ54
VSS_43
DQ55
DQ50
VSS_44
DQ51
DQ60
VSS_45
DQ61
DQ56
DQ57
VSS_46
VSS_47
DQS7*
DM7
DQS7
VSS_48
VSS_49
DQ58
DQ62
DQ63
DQ59
VSS_50
VSS_51
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT_0
VTT_1

J3200
DDR3-SODIMM-DUAL

33 32

PP0V75_S3_MEM_VREFDQ_B

DDR3-SODIMM-DUAL

33 32

6

DIMM 1

32 29

7
1A
3A
5A
7A
9A
11A
13A
15A
17A
19A
21A
23A
25A
27A
29A
31A
33A
35A
37A
39A
41A
43A
45A
47A
49A
51A
53A
55A
57A
59A
61A
63A
65A
67A
69A
71A

DIMM 3

8

2B
4B
6B
8B
10B
12B
14B
16B
18B
20B
22B
24B
26B
28B
30B
32B
34B
36B
38B
40B
42B
44B
46B
48B
50B
52B
54B
56B
58B
60B
62B
64B
66B
68B
70B
72B
74B
76B
78B
80B
82B
84B
86B
88B
90B
92B
94B
96B
98B
100B
102B
104B
106B
108B
110B
112B
114B
116B
118B
120B
122B
124B
126B
128B
130B
132B
134B
136B
138B
140B
142B
144B
146B
148B
150B
152B
154B
156B
158B
160B
162B
164B
166B
168B
170B
172B
174B
176B
178B
180B
182B
184B
186B
188B
190B
192B
194B
196B
198B
200B
202B
204B

3
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>

2

32 33
32 33

DIMM1 SPD ADDR=0XA2(WR)/0XA3(RD)

32 33
32 33
32 6

=MEM_B_DQ<6>
=MEM_B_DQ<7>
=MEM_B_DQ<12>
=MEM_B_DQ<13>
=MEM_B_DM<1>
MEM_RESET_L
=MEM_B_DQ<14>
=MEM_B_DQ<15>

1

DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

=PPSPD_S0_MEM_B

32 6

=PPSPD_S0_MEM_B

32 33
1

32 33

32 33
32 33

2

32 33

1

R3240

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

32

MEM_DIMM1_SA<1>

32

MEM_DIMM3_SA<1>

32

MEM_DIMM1_SA<0>

32

MEM_DIMM3_SA<0>

31 32 33

R3242

10K

1

R3243
10K

2

5%
1/16W
MF-LF
402

D

32 33
1

32 33

R3241
10K

=MEM_B_DQ<20>
=MEM_B_DQ<21>
=MEM_B_DM<2>
=MEM_B_DQ<22>
=MEM_B_DQ<23>
=MEM_B_DQ<28>
=MEM_B_DQ<29>

5%
1/16W
MF-LF
2 402

32 33
32 33

32 33

32 6

32 33

=PPSPD_S0_MEM_B

32 33

1

32 33

2

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DQ<30>
=MEM_B_DQ<31>

MEM_B_CKE<3>
=PP1V5_S3_MEM_B
MEM_B_A<15>
MEM_B_A<14>

32 33

MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<2>
MEM_B_A<0>
=MEM_B_CLK_P<3>
=MEM_B_CLK_N<3>
MEM_B_BA<1>
MEM_B_RAS_L
MEM_B_CS_L<2>
MEM_B_ODT<2>

32 33
32 33

32 29

16 101

PP0V75_S3_MEM_VREFCA_B

6 30 32 108

C

32 33
15 32 101

C3235

=MEM_B_DM<4>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
=MEM_B_DQ<44>
=MEM_B_DQ<45>

20%
10V
CERM
402

2

15 32 101
15 32 101

32 29

15 32 101

PP0V75_S3_MEM_VREFDQ_B

15 32 101

33

1

33

C3230

1

C3231

2.2UF
2

15 32 101

0.1UF

20%
6.3V
CERM
402-LF

20%
10V
CERM
402

2

15 32 101

16 101
16 101

=PP0V75_S0_MEM_VTT_B

16 101

C3250

1

2.2UF

29 32
2

=MEM_B_DQ<36>
=MEM_B_DQ<37>

C3236
0.1UF

20%
6.3V
CERM
402-LF

2

15 32 101

1

PP0V75_S3_MEM_VREFCA_B

1

2.2UF

15 32 101

32 6

MEM_B_ODT<3>

20%
6.3V
CERM
402-LF

32 33

1

MEM_B_A<11>
MEM_B_A<7>

C3240
2.2UF

32 33

32 33

C3251
2.2UF

20%
6.3V
CERM
402-LF

2

20%
6.3V
CERM
402-LF

B

32 33

32 33

32 33
32 33

Page Notes

32 33

Power aliases required by this page:

32 33

- =PP1V5_S0_MEM_B

=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>

32 33

- =PP1V5_S3_MEM_B

32 33

- =PP0V75_S0_MEM_VTT_B
- =PPSPD_S0_MEM_B (2.5 - 3.3V)

=MEM_B_DQ<46>
=MEM_B_DQ<47>

32 33

Signal aliases required by this page:
32 33

- =I2C_SODIMMB_SCL

=MEM_B_DQ<52>
=MEM_B_DQ<53>

- ALL DQ, DQS, DM SIGNALS;
TO FACILITATE BITSWAPS WITH ALIASES

- =I2C_SODIMMB_SDA
32 33

BOM options provided by this page:

32 33

(NONE)

=MEM_B_DM<6>
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<60>
=MEM_B_DQ<61>

32 33

32 33
32 33

32 33
32 33

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>

DDR3 SO-DIMM CONNECTOR B

32 33
32 33

DRAWING NUMBER

=MEM_B_DQ<62>
=MEM_B_DQ<63>
MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
=PP0V75_S0_MEM_VTT_B

Apple Inc.

32 33
32 33

051-7863

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

21 31 32 49 55

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

32 52
32 52
6 32

PAGE

32 OF 110
SHEET

 OF 

410

6

5

4

3

2

1

8

7

6

MCP CHANNEL A DQS 0 -> DIMM A DQS 0
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

D

101 15
101 15

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DM<0>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DM<1>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

C

101 15

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DM<2>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DM<3>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

B

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DM<4>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DM<5>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
=MEM_A_DM<4>
=MEM_A_DQ<39>
=MEM_A_DQ<38>
=MEM_A_DQ<37>
=MEM_A_DQ<36>
=MEM_A_DQ<35>
=MEM_A_DQ<34>
=MEM_A_DQ<33>
=MEM_A_DQ<32>

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DM<6>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15
101 15

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DM<7>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>
=MEM_B_DM<0>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<5>
=MEM_B_DQ<4>

32

DDR3 RESET Support

32
32

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
32
6

32

=PP1V5_S3_MEMRESET

32
32

1

32

32
6

32

=PP3V3_S5_MEMRESET

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>
MEM_B_DM<1>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>
MEM_B_DM<2>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

R3310
1K

3.3V input must be stable before
before 1.5V starts to rise to
avoid glitch on MEM_RESET_L.

32

5%
1/16W
MF-LF
2 402

D
MEM_RESET_L

MEMRESET_HW
1

=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
=MEM_B_DM<1>
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<13>
=MEM_B_DQ<12>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<9>
=MEM_B_DQ<8>

32

20K

MEMRESET_HW

32

R3300

=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
=MEM_B_DM<2>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DQ<21>
=MEM_B_DQ<20>
=MEM_B_DQ<19>
=MEM_B_DQ<18>
=MEM_B_DQ<17>
=MEM_B_DQ<16>

2

1

5%
1/16W
MF-LF
402

32
32

MEM_RESET_RC_L
MEMRESET_HW

1
1

20K
5%
1/16W
MF-LF
402

32

G

MEMRESET_MCP
1

2N7002

R3309

SOT23-HF1

0

S
2

2

5%
1/16W
MF-LF
402

MMBT3904G
SOT23

MEMRESET_HW
32

1

Q3306

Q3305

1

32

R3301

MEMRESET_HW

D

3 MEMRESET_HW

2

32

32

3

5%
1/16W
MF-LF
402

MEM_RESET

10K

32

31 32

R3305

32
32

OUT

2

C3300
0.1UF

2
2

20%
10V
CERM
402

32
32
32
32
16

32

IN

MCP_MEM_RESET_L

32
32
32
32
32

MEM_B_DQS_N<3>
MEM_B_DQS_P<3>
MEM_B_DM<3>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
=MEM_B_DM<3>
=MEM_B_DQ<31>
=MEM_B_DQ<30>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<27>
=MEM_B_DQ<26>
=MEM_B_DQ<25>
=MEM_B_DQ<24>

C

32
32
32
32
32
32
32
32
32
32
32

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>
MEM_B_DM<4>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MCP MEMORY CLOCK ALIASING
=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
=MEM_B_DM<4>
=MEM_B_DQ<39>
=MEM_B_DQ<38>
=MEM_B_DQ<37>
=MEM_B_DQ<36>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<33>
=MEM_B_DQ<32>

32
32
101 15
32
101 15
32
101 15
32
101 15
32
101 16
32
101 16
32
101 16
32
101 16

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CLK_P<3>
MEM_A_CLK_N<3>
MEM_A_CLK_P<4>
MEM_A_CLK_N<4>

32

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_A_CLK_P<0>
=MEM_A_CLK_N<0>
=MEM_A_CLK_P<1>
=MEM_A_CLK_N<1>
=MEM_A_CLK_P<2>
=MEM_A_CLK_N<2>
=MEM_A_CLK_P<3>
=MEM_A_CLK_N<3>

31

=MEM_B_CLK_P<0>
=MEM_B_CLK_N<0>
=MEM_B_CLK_P<1>
=MEM_B_CLK_N<1>
=MEM_B_CLK_P<2>
=MEM_B_CLK_N<2>
=MEM_B_CLK_P<3>
=MEM_B_CLK_N<3>

32

31
31
31
31
31
31
31

32

MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DM<5>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
=MEM_B_DM<5>
=MEM_B_DQ<47>
=MEM_B_DQ<46>
=MEM_B_DQ<45>
=MEM_B_DQ<44>
=MEM_B_DQ<43>
=MEM_B_DQ<42>
=MEM_B_DQ<41>
=MEM_B_DQ<40>

32
101 15
32
101 15
32
101 15
32
101 15
32
101 16
32
101 16
32
101 16
32
101 16

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CLK_P<3>
MEM_B_CLK_N<3>
MEM_B_CLK_P<4>
MEM_B_CLK_N<4>

32

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

B

32
32
32
32
32
32
32

32
32

MCP CHANNEL B DQS 6 -> DIMM B DQS 6
=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
=MEM_A_DM<6>
=MEM_A_DQ<55>
=MEM_A_DQ<54>
=MEM_A_DQ<53>
=MEM_A_DQ<52>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<49>
=MEM_A_DQ<48>

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

MCP CHANNEL A DQS 7 -> DIMM A DQS 7

A

1

MCP CHANNEL B DQS 5 -> DIMM B DQS 5
=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
=MEM_A_DM<5>
=MEM_A_DQ<47>
=MEM_A_DQ<46>
=MEM_A_DQ<45>
=MEM_A_DQ<44>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<41>
=MEM_A_DQ<40>

MCP CHANNEL A DQS 6 -> DIMM A DQS 6
101 15

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MCP CHANNEL B DQS 4 -> DIMM B DQS 4

MCP CHANNEL A DQS 5 -> DIMM A DQS 5
101 15

2

MCP CHANNEL B DQS 3 -> DIMM B DQS 3
=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
=MEM_A_DM<3>
=MEM_A_DQ<31>
=MEM_A_DQ<30>
=MEM_A_DQ<29>
=MEM_A_DQ<28>
=MEM_A_DQ<27>
=MEM_A_DQ<26>
=MEM_A_DQ<25>
=MEM_A_DQ<24>

MCP CHANNEL A DQS 4 -> DIMM A DQS 4
101 15

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DM<0>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

MCP CHANNEL B DQS 2 -> DIMM B DQS 2
=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
=MEM_A_DM<2>
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<19>
=MEM_A_DQ<18>
=MEM_A_DQ<17>
=MEM_A_DQ<16>

MCP CHANNEL A DQS 3 -> DIMM A DQS 3
101 15

3

MCP CHANNEL B DQS 1 -> DIMM B DQS 1
=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
=MEM_A_DM<1>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<12>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<9>
=MEM_A_DQ<8>

MCP CHANNEL A DQS 2 -> DIMM A DQS 2
101 15

4

MCP CHANNEL B DQS 0 -> DIMM B DQS 0
=MEM_A_DQS_N<0>
=MEM_A_DQS_P<0>
=MEM_A_DM<0>
=MEM_A_DQ<7>
=MEM_A_DQ<6>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<3>
=MEM_A_DQ<2>
=MEM_A_DQ<1>
=MEM_A_DQ<0>

MCP CHANNEL A DQS 1 -> DIMM A DQS 1
101 15

5

MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DM<6>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
=MEM_B_DM<6>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
=MEM_B_DQ<53>
=MEM_B_DQ<52>
=MEM_B_DQ<51>
=MEM_B_DQ<50>
=MEM_B_DQ<49>
=MEM_B_DQ<48>

32

MCP MEMORY TEST POINT ALIASING

32
32
32

TP_MEM_A_A<15>
TP_MEM_B_A<15>

32
32

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_A<15>
MEM_B_A<15>

31
32

32
32
32
32
32

MCP CHANNEL B DQS 7 -> DIMM B DQS 7
=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
=MEM_A_DM<7>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=MEM_A_DQ<57>
=MEM_A_DQ<56>
=MEM_A_DQ<59>
=MEM_A_DQ<58>
=MEM_A_DQ<61>
=MEM_A_DQ<60>

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

31

101 15

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DM<7>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
=MEM_B_DM<7>
=MEM_B_DQ<63>
=MEM_B_DQ<62>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<56>

32

SYNC_MASTER=MASTER

32

SYNC_DATE=N/A

A

PAGE TITLE

32

DDR3 SUPPORT AND BITSWAPS

32

DRAWING NUMBER

32
32

Apple Inc.

32

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

32
32

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REVISION

A.0.0

R

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SIZE

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 OF 

8

7

6

5

4

3

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1

8

7

6

5

4

3

2

1

D

D

L3400

PP3V3_MINI
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

FERR-120-OHM-1.5A
1

=PP3V3_S3_MINI

6

2
0402-LF

C3400 1

C3401 1 C3402 1

0.1uF

L3430

CRITICAL

C

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

10uF

20%
6.3V 2
X5R
603

C

90-OHM-100MA
DLP11S

J3400

20247-916E-01F

SYM_VER-1

F-ST-SM
17

1

4

3

PCIE_CLK100M_MINI_P

IN

17 102

1

2

PCIE_CLK100M_MINI_N

IN

17 102

2

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

3

MINI_CLKREQ_L
PCIE_WAKE_L
MINI_RESET_L

4
5
6

OUT
OUT
IN

17
17
9

7

PCIE_CLK100M_MINI_CON_N
PCIE_CLK100M_MINI_CON_P

8
9
10

PCIE_MINI_R2D_N
PCIE_MINI_R2D_P

11
12
13

PCIE_MINI_D2R_N
PCIE_MINI_D2R_P

14
15

OUT

102 17

OUT

102 17

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

C3431

16

0.1uF
1

L3440
12-OHM-100MA

18
4

518S0731

3

B

TCM1210-4SM
SYM_VER-2

1

2

PCIE_MINI_R2D_C_N

2

IN

17 102

IN

17 102

10%
16V
X5R
402

PCIE_MINI_R2D_L_N
PCIE_MINI_R2D_L_P

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

B

C3430

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

0.1uF
1

2

PCIE_MINI_R2D_C_P

10%
16V
X5R
402

A

SYNC_MASTER=K22

SYNC_DATE=05/28/2009

A

PAGE TITLE

PCI-E Wireless Connector
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

34 OF 110
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8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

35 OF 110
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D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

36 OF 110
SHEET

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8

7

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5

4

3

2

=PP1V05_ENET_PHY

D

C3710

1

C3711

0.1UF
38

10%
16V
X5R
402

=PP3V3_ENET_PHY

(43mA typ - 1000base-T)
(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek

1

1

0.1UF
10%
16V
X5R
402

2

1

38

(221mA typ - 1000base-T)
( 7mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek

D

CRITICAL

L3715

2

FERR-120-OHM-1.5A
0402-LF

1

1

1

C3700
0.1UF

CRITICAL

L3705
FERR-120-OHM-1.5A

C3701

1

0.1UF

10%
16V
X5R
402

2

2

C3702

2

0.1UF

10%
16V
X5R
402

2

10%
16V
X5R
402

PP1V05_ENET_PHYAVDD
1

C3714

0402-LF

C3715

1

C3716

0.1UF

0.1UF

0.1UF

10%
16V
X5R
402

10%
16V
X5R
402

10%
16V
X5R
402

2

2

2

1

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

2

PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

1

C3705
0.1UF

2

C3706
0.1UF

10%
16V
X5R
402

2

10%
16V
X5R
402

=PP3V3_ENET_PHY_VDDREG

38

If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

38

40

10

5%
1/16W
MF-LF
402 2

AVDD12

28

3

45

44

37

21

15

36

DVDD12

5%
1/16W
MF-LF

1

4.7K

R3752 1

R3751
4.7K

5%
1/16W
MF-LF
402
2

4.7K

=RTL8211_REGOUT

5%
1/16W
MF-LF
402 2

If internal switcher is used, must place inductor within 5mm
of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

38

C

If internal switcher is not used, VDDREG and REGOUT can float.

2 402

39

=RTL8211_ENSWREG

IN

4.7K

FB12

5%
1/16W
MF-LF
402 2

Alias to =PP3V3_ENET_PHY for internal switcher.
Alias to GND for external 1.05V supply.

R3725

VDDREG

10K

C

NOSTUFF

1

AVDD33

R3720 1

DVDD33

6

41

R3750 1

U3700
ENSWREG

RTL8211CLGR

REGOUT

48

RXC

19

TQFP

R3780

ENET_CLK125M_TXCLK

104 18

IN

104 18

IN

104 18

IN

WF: Verify that ENET_RESET_L does not assert when WOL is active.
If true, RC and 0-ohm resistor should be removed.
If false, ENET_RESET_L should be removed.

IN

1/16W

MF-LF

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

ENET_TX_CTRL

104 18

IN

104 18

BI

ENET_MDC
ENET_MDIO

22

TXC

23
24
25
26

27

30
31

TXD[0]
TXD[1]
TXD[2]
TXD[3]

RGMII/MII

RXD[0]
RXD[1]/TXDLY
RXD[2]/AN0
RXD[3]/AN1

TXCTL

MDC
MDIO

RXCTL

100

RTL8211_PHYRST_L

2

5%
1/16W
MF-LF
402

29

PHYRSTB*

1

C3725
0.1UF

2

RTL8211_RSET

20%
10V
CERM
402

B

TP_RTL8211_CLK125

R3730

22

1

32

RSET

REFERENCE

104

17

104

18

104

13

MDI+[1]
MDI-[1]

4

MDI+[2]
MDI-[2]

8

MDI+[3]
MDI-[3]

11

LED0/PHYAD0
LED1/PHYAD1
LED2/RXDLY

34

104

2

5

9

12

R3791
R3792
R3793
R3794

ENET_RXD_R<0>
ENET_RXD_R<1>
ENET_RXD_R<2>
ENET_RXD_R<3>

R3795

ENET_RXCTL_R

ENET_MDI_P<0>
ENET_MDI_N<0>

BI

39 104

BI

39 104

ENET_MDI_P<1>
ENET_MDI_N<1>

BI

39 104

BI

39 104

ENET_MDI_P<2>
ENET_MDI_N<2>

BI

39 104

BI

39 104

ENET_MDI_P<3>
ENET_MDI_N<3>

BI

39 104

BI

39 104

22
22
22
22

22

1

2

1

2

1

2

1

2

1

ENET_CLK125M_RXCLK

2
5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>

ENET_RX_CTRL

2

OUT

18 104

OUT

18 104

OUT

18 104

OUT

18 104

OUT

18 104

OUT

18 104

B

CLK125

1

CLOCK

2.49K
104 38

IN

RTL8211_CLK25M_CKXTAL1
TP_RTL8211_CKXTAL2

42
43

CKXTAL1
CKXTAL2

LED

2

GND
7

1%
1/16W
MF-LF
402

46

104

16

1

RESET MEDIA DEPENDENT

NOSTUFF

14

MDI+[0]
MDI-[0]

MANAGEMENT

R3724
1

R3790

104 ENET_CLK125M_RXCLK_R

402

RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY

35
38

NO STUFF

C3790

47

ENET_RESET_L

ENET_CLK125M_TXCLK_R

2

IN

104 18

IN

1

5%

104 18

18

22

33

IN

20

104 18

OMIT
CRITICAL

1

10PF
5%
50V
CERM
402

2

R3755 1

R3756 1

4.7K

4.7K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

1

R3757
4.7K

2

5%
1/16W
MF-LF
402

Reserved for EMI
per RealTek request.

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Ethernet PHY (RTL8211CL)
DRAWING NUMBER

Apple Inc.

051-7863

PHYAD
AN[1:0]
RXDLY
TXDLY

=
=
=
=

01
11
0
0

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

(PHY Address 00001)
(Full auto-negotiation)
(RXCLK transitions with data)
(No TXCLK Delay)

8

D

REVISION

A.0.0

R

Configuration Settings:

SIZE

BRANCH

PAGE

37 OF 110
SHEET

 OF 

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

1.1V ENET FET
78 70 38 6

ENET ALIASES

=PP12V_S5_PWRCTL
1

C3800
0.1UF

10%
16V
2 X5R
402

CRITICAL

Q3800
S 2

=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_PHY

18 25
25
37

38

VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.1 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

SOT23

38

PP3V3_RMGT

=PP3V3_ENET_MCP_RMGT
=PP3V3_ENET_PHY

MAKE_BASE=TRUE

18 25
37

P1V1_ENET_EN

1

1
G

D 3

6

PP1V1_RMGT
MAKE_BASE=TRUE

PP1V1_RMGT

IRLML2502GPBF

=PP1V1_S5_ENET_FET

38

VCC

=RTL8211_ENSWREG
MAKE_BASE=TRUE

U3800
TDFN

5D
7G

ON 2

CRITICAL

S6
NC_RTL8211_REGOUT

THRM
PAD

GND
4

NC 3

9

8 PG

=RTL8211_REGOUT

37

=PP3V3_ENET_PHY_VDDREG

37

MAKE_BASE=TRUE
NO_TEST=TRUE

NC_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
NO_TEST=TRUE

C
70 38

37

NOTE: NOT USING THE BUILT-IN 1.05V REGULATOR OF THE PHY

SLG5AP001

C

ENET_EN

IN

3.3V ENET FET
78 70 38 6

=PP12V_S5_PWRCTL
1

C3850
0.1UF

10%
2 16V
X5R
402

CRITICAL

Q3850

PP3V3_RMGT

38

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR

IRLML2502GPBF

=PP3V3_S5_ENET_FET

S 2

SOT23

1
G

D 3

6

B
P3V3_ENET_EN

1

B
VCC

U3850
SLG5AP001
TDFN

5D
7G

CRITICAL

S6

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

GND
4

NC 3
THRM
PAD
9

8 PG

RTL8211 25MHz Clock

ON 2

R3895
104 18

IN

MCP_CLK25M_BUF0_R

22
1

2

RTL8211_CLK25M_CKXTAL1

OUT

37 104

5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
70 38

IN

ENET_EN

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Ethernet Support
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

38 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

CRITICAL

T3900

LFE9287APF
SOI

C

1 TCT1

MCT1 24

ENET_MCT0

104 37

ENET_MDI_P<0>

2 TD1+ 1CT:1CT

MX1+ 23

ENET_MDI_T_P<0>

104 39

104 37

ENET_MDI_N<0>

3 TD1-

MX1- 22

ENET_MDI_T_N<0>

104 39

4 TCT2

MCT2 21

104 37

ENET_MDI_P<1>

5 TD2+ 1CT:1CT

MX2+ 20

ENET_MDI_T_P<1>

104 39

C
CRITICAL

J3900
RJ45-10/100TX-K22

ENET_MCT1

F-ANG-TH
104 39
104 39

104 37

ENET_MDI_N<1>

6 TD2-

MX2- 19

7 TCT3

MCT3 18 ENET_MCT2

8 TD3+ 1CT:1CT

MX3+ 17

ENET_MDI_T_N<1>

104 39

104 39
104 39

104 37

ENET_MDI_P<2>

104 39

ENET_MDI_T_P<2>

104 39
104 39
104 39

104 37

MX3- 16

9 TD3-

ENET_MDI_N<2>

ENET_MDI_T_N<2>

104 39

ENET_MDI_T_P<0>
ENET_MDI_T_N<0>
ENET_MDI_T_P<1>
ENET_MDI_T_P<2>
ENET_MDI_T_N<2>
ENET_MDI_T_N<1>
ENET_MDI_T_P<3>
ENET_MDI_T_N<3>

1

ENET_MDI
TRAN_P0
TRAN_N0
TRAN_P1
TRAN_P2
TRAN_N2
TRAN_N1
TRAN_P3
TRAN_N3

2
3
4
5
6
7
8

104 39

9

10 TCT4

MCT4 15 ENET_MCT3

10

104 37

ENET_MDI_P<3>

11 TD4+ 1CT:1CT

MX4+ 14

ENET_MDI_T_P<3>

104 39

104 37

ENET_MDI_N<3>

12 TD4-

MX4- 13

ENET_MDI_T_N<3>

104 39

SHIELD
PINS

514-0654

B

B
1

R3900
75

ENET_TCT
1

C3901
0.1UF

20%
10V
2 CERM
402

1

C3902
0.1UF

20%
10V
2 CERM
402

1

C3903
0.1UF

20%
10V
2 CERM
402

1

C3904

1

R3901
75

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

1

R3902
75

5%
1/16W
MF-LF
2 402

1

R3903
75

5%
1/16W
MF-LF
2 402

0.1UF

20%
10V
2 CERM
402

ENET_MCT_BS
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm

NOSTUFF
1

C3900
1000PF

PLACE ONE CAP PER TCT PIN

10%
2KV
2 CERM
1206

NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.

NOTE: BOB SMITH TERMINATION FOR EMC.

A

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE

ETHERNET CONNECTOR
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

39 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

40 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8
6
43 42 41 6

7

6

5

4

3

2

1
=PP1V5_FWRS0_FWXIO

=PP3V3_FWRS0_FWXIO
=PP3V3_FW_FWPHY

C4100

C4101

1

1

C4102

C4103

1

1

C4104

1

C4105

1UF

1UF

1UF

1UF

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

2

2

2

2

2

C4124

1

2

C4123

1

C4122

1

1

C4121

C4120

1

1UF

1UF

1UF

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

2

2

2

2

1

6

R4125 1
1
5%
1/16W
MF-LF
402

2

2

PP1V5_FW_VDDA

1

D
2

C4106
R4110

1UF

1

10%
6.3V
CERM
402

5%
1/16W
MF-LF
402

1

C4107

1

1UF
10%
6.3V
CERM
402

2

C4108

C4128

1

1UF
2

10%
6.3V
CERM
402

C4127

1

1UF
10%
6.3V
CERM
402

2

1

C4126

1UF
10%
6.3V
CERM
402

2

C4125

1

1UF
10%
6.3V
CERM
402

2

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

1

1UF
10%
6.3V
CERM
402

2

D

2

PP3V3_FW_AVDD
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1

R4119

1
2

1
5%
1/16W
MF-LF
402

C4110

C4111

1

1

C4112

C4113

1

1

C4114

1

C4115

R4117

1UF

1UF

1UF

1UF

1UF

1UF

1

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

5%
1/16W
MF-LF
402

2

2

2

2

2

PP1V95_FW_FWPHY 42

1

2

C4132

PP3V3_FW_VDDA
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

2

C4131

1

C4130

1

1UF

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

2

2

1

1

1UF

1%
1/16W
MF-LF
402

14.3K
1%
1/16W
MF-LF
402

VDDA_15

DVDD_CORE

OMIT
CRITICAL

U4100
XIO2213B

2

1

2

10%
6.3V
CERM
402

PP1V96_FW_XTAL
4

C4137

1

1

C4138

C4139

1

1UF

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

2

2

2

102 PCIE_FW_D2R_C_N

OUT

=FW_CLKREQ_L

102 17

IN

102 17

IN

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

42

PLACEMENT_NOTE=Place C4145 close to UA200
PLACEMENT_NOTE=Place C4146 next to C4145

H13

REFCLK_SEL

FWXIO_SCL
FWXIO_SDA

J13

SCL
SDA

H12

NC
NC
NC
NC
NC
NC
NC
NC

220
5%
1/16W
MF-LF
2 402

B
42

OUT

=FW_PME_L
FWXIO_CYCLEOUT

NO STUFF
1

N6

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

P8

OHCI_PME*

N2
P2
N3

2

N4
P5
P6

N8

TP_FWXIO_GRST_L

C13

2

1

2

TP_FWXIO_JTAG_TMS
TP_FWXIO_JTAG_TDO
TP_FWXIO_JTAG_TDI

E12
F12
F13

R4160

G12

5%
1/16W
MF-LF
402

NC
NC
NC
FWXIO_SNOOP_EN
(Snoop Enable, for FireBug)

R4180 1
1K
5%
1/16W
MF-LF
402

2

K12
L12
L13
M8

NC
NC
NC
NC
NC
NC
NC
NC
NC

M11
M12
M13
N10
N11
N12
N13
P10
P11
D12

R4181 1

1

1K
5%
1/16W
MF-LF
402

R4182

D13

1K

2

2

5%
1/16W
MF-LF
402

FWPHY_BMODE
FWPHY_TESTM
FWPHY_TESTW

A5
B2
A6
P13

NO STUFF1

P14

R4189

G1

PINT_L
PINT_P

D2

LPS_L
LPS_P

C1

LREQ_L
LREQ_P

F2

CTL0
CTL1

H1

D0
D1
D2
D3
D4
D5
D6
D7

J2

R0
R1

N1

PD

B3

CNA
CPS

A2
P12

TP_FWPHY_CNA
FWPHY_CPS

PHY_RESET*

B4

FWPHY_RESET_L

TPBIAS0
TPBIAS1
TPBIAS2

K13

FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS

TPA0_P
TPA0_N
TPA1_P
TPA1_N
TPA2_P
TPA2_N

K14

TPB0_P
TPB0_N
TPB1_P
TPB1_N
TPB2_P
TPB2_N

M14

(IPU)

RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18

(JTAG_TDO)
(JTAG_TDI)
(JTAG_TCK)

(IPU)

IN

42

TP/NC TPBIASx
TP/NC TPAx_P/TPAx_N
Ground TPBx_P/TPBx_N

(JTAG_TRST)

BMODE
TESTM
TESTW_VREG_PD
SE
SM
GND
H5

G9

G8

G7

G6

G5

F9

F8

F7

F6

E7

N5

PLLGND

VSS

2

VSSA

TRI-ST/NC

NC

GND

IN

42

IN

42

=PP3V3_FW_FWPHY
=FWPHY_DS0
=FWPHY_DS1
FWOHCI_LINKON_L
FWPHY_LKON_DS2

P9
E1
D1

R4170
1K
1

2

FWOHCI_CLK98M_LCLK

1

C

6 41 42 43

R4171
470
5%
1/16W
MF-LF

5%
1/16W
MF-LF
402

DS2 hard-strapped to 1,
page assumes no more than
2 FW800 connectors

2 402

H2

FWPHY_CLK98M_PCLK

Strap DSx high on unused ports.

F1

FWPHY_PINT

D3

FWOHCI_LPS

C2

FWOHCI_LREQ

J1

K2
K1
L1
L2
L3
M2
M3

M1

R4175
10K

E2

5%
1/16W
MF-LF
2 402

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

B
1

R4185
6.34K

1%
1/16W
MF-LF
2 402

FWPHY_R0
FWPHY_R1

=PPVP_FW_PHY_CPS
1

42

R4186
390K

5%
1/16W
MF-LF
2 402

1

Unused Ports:

OUT

2

A11

(JTAG_TMS)

1K
5%
1/16W
MF-LF
402

PCLK_L
PCLK_P

1394B OHCI & PHY

1K

A

GRST*

R4153
5%
1/16W
MF-LF
402

LCLK_L
LCLK_P

G2

CYCLEOUT

47K

=PP3V3_FW_FWPHY

N9

(IPU)

CLK98M_FW_XI_R

1

2

1

E6

43 42 41 6

P1

DS0
DS1
LINKON_L
LKON_DS2_P

REFCLK_P
REFCLK_M

FWXIO_REFCLK_SEL

R4152

220

B1

=FWPHY_PC0

CLKREQ*

SM

E8

G13
E13

L14
F14
G14
B14
C14

N14

FW_P0_TPA_P
FW_P0_TPA_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P2_TPA_P
FW_P2_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N

H14

BI

42

BI

42

BI

42

BI

42

BI

42

BI

42

BI

42

BI

42

BI

42

BI

42

BI

42

C4189
0.22UF

2

10%
6.3V
CERM-X5R
402

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

FireWire LLC/PHY (XIO2213B)
DRAWING NUMBER

Apple Inc.

D14
E14

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

VSSA_PCIE

A

PAGE TITLE

J14

C7

2

1

5%
1/16W
MF-LF
402 2

1K
5%
1/16W
MF-LF
402

1

A1

PC0
PC1
PC2

E9

C6

R4151

J12

C5

1

A8

C4

402

B6

X5R

Alias =FWPHY_PC0
as appropriate

PCI EXPRESS

TXP
TXN

C10

402

16V

CLK98M_FW_XI
TP_FWOHCI_XO

Multiple-ports:
PC[0:2] = ’100’

RXP
RXN

F5

X5R

2
10%

R4150

A9

PERST*

A7

16V

1

0.1uF

102 PCIE_FW_D2R_C_P

402

2
10%

0.1uF

102 PCIE_FW_R2D_N

A3

A14

C4146

A4

K8

PCIE_FW_D2R_N

X5R

1

FW_RESET_L
102 PCIE_FW_R2D_P

K7

OUT

16V

IN

K6

102 17

0.1uF

402

K5

C4145

X5R

J8

PCIE_FW_D2R_P

9

16V

J7

OUT

2
10%

J6

102 17

1

0.1uF

J5

C4141

P3

10%
6.3V
CERM-X5R
402

3

5%
1/16W
MF-LF
402

1

0.22UF

98P3040MHZ

R4191
1

P4

C4190

VCC

Y4190
22

XI
RSVD_19

Single-port:
PC[0:2] = ’000’

H9

C4140

PCIE_FW_R2D_C_N

REF0_PCIE
REF1_PCIE

H8

PCIE_FW_R2D_C_P

IN

B13

A12

H7

IN

102 17

A13

H6

102 17

FWXIO_REF0_PCIE
FWXIO_REF1_PCIE

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.96V

2

BGA
PLACEMENT_NOTE=Place C4140 close to U1400
PLACEMENT_NOTE=Place C4141 next to C4140

R4190
4.7

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.96V

1UF

C11

B11

C12

M9

F3

C9

B5

B7

B9

B10

P7

B8

M6

K10

H3

G3

M10

K9

J9

F10

A10

E10

C3

K3

J3

B12

C8

M5

M4

VDD_15

VDD_33_COM_IO

2

R4140 1

AVDD_3_3

VDD_33_COMB

232

DVDD_3_3 VDDA_33

VDD_15_COMB

R4141

VDD_33

(VDD_33_AUX)

1

PLLVDD_CORE

FWXIO_REF_PCIE

For single-port systems, all FW power should
be tied together and powered by S0 or by the
5K pull-down device detect circuit.

C4135

2

J10

10%
6.3V
CERM
402

2

H10

10%
6.3V
CERM
402

PLLVDD_3_3

FWRS0_FWXIO nets are OHCI/PCIe power, and
can be S0.

1UF
2

G10

10%
6.3V
CERM
402

FWXIO_VDD15COMB
FWXIO_VDD33COMB
FWXIO_VDD33COMIO

1

E3

1UF

C4119

1

M7

C4118

1

N7

C4117

FW_FWPHY nets are PHY power, and for
multi-port systems must come from bus power.

2
10%

2

PP1V96_FW_PLLVDD

Power Aliases:

1

5%
1/16W
MF-LF
402

2

PP3V3_FW_PLLVDD
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

C

R4135 1

1

BRANCH

PAGE

41 OF 110
SHEET

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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Termination
Place close to FireWire PHY
41

FW_P0_TPBIAS
VOLTAGE=1.86V
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.08MM

1

1394 PHY 1.95V SUPPLY

D

C4250

10%
6.3V
2 CERM
402

CRITICAL

L4250

U4200
43 42 41 6

PP1V95_FW_FWPHY

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.95V

SON

OUT 1
NR 2

6 IN
4 EN

41

MAKE_BASE=TRUE

TPS799195

=PP3V3_FW_FWPHY

5 NC

1

P1V95_FW_NR

1UF

GND

10%
6.3V
CERM 2
402

3

THRML

C4201

PAD

18NH-250MA

1

1

2

2

0402

0402

Peak Current: 100mA

1

1

0.01UF

7

L4251

18NH-250MA
TI PHY "Peaking Inductors" To improve Data Eye.

105

C4200

D

1UF

TI PHY requires 1UF, not 0.33uF spec value.

FW_P0_TPA_L_P

105

VOLTAGE=1.86V
NO_TEST=TRUE

C4202

FW_P0_TPA_L_N
VOLTAGE=1.86V
NO_TEST=TRUE

2.2UF

20%
4V
2 X5R
402

10%
16V
CERM 2
402

1

1

R4250

R4251

56.2

56.2

1%
1/16W
MF-LF
402 2

41
41
41
41

1%
1/16W
MF-LF
2 402

FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

FW_PORT0_TPA_P
FW_PORT0_TPA_N
FW_PORT0_TPB_P
FW_PORT0_TPB_N

43 105
43 105
43 105
43 105

MAKE_BASE=TRUE

R42521

C

41

=FW_CLKREQ_L

FW_CLKREQ_L

1

R4253

56.2

FireWire Aliases For Connectivity
17

C

56.2

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

MAKE_BASE=TRUE
105
41

=FW_PME_L

FW_PME_L

FW_P0_TPB_L_N

105

VOLTAGE=0V
NO_TEST=TRUE

19

MAKE_BASE=TRUE

VOLTAGE=0V
NO_TEST=TRUE

L4252

41

=PPVP_FW_PHY_CPS

PPVP_FW_PHY_CPS

43

MAKE_BASE=TRUE

FW_P0_TPB_L_P

L4253

18NH-250MA

18NH-250MA

1

1

2
0402

2
0402

FW_P0_TPA_C

1

C4254
220PF

5%
25V
CERM 2
402

1394 PHY STRAPPING OPTIONS

B

43 42 41 6

1

R4254
4.99K

1%
1/16W
MF-LF
2 402

B

=PP3V3_FW_FWPHY

NOSTUFF

2ND & 3RD TPA/TPB PAIR UNUSED

1

R4255 1R4256

41

=FWPHY_DS0

FW_PHY_DS0

41

=FWPHY_DS1

FW_PHY_DS1

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

41

FW_P1_TPBIAS

NC_FW_PORT1_TPBIAS

41

FW_P1_TPA_P

NC_FW_PORT1_TPA_P

41

FW_P1_TPA_N

NC_FW_PORT1_TPA_N

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT
IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.

MAKE_BASE=TRUE

NO_TEST=TRUE

1

R4258
10K

5%
1/16W
MF-LF
2 402

41

FW_P2_TPBIAS

NC_FW_PORT2_TPBIAS

41

FW_P2_TPA_P

NC_FW_PORT2_TPA_P

41

FW_P2_TPA_N

NC_FW_PORT2_TPA_N

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE
MAKE_BASE=TRUE

NO_TEST=TRUE

A

41

=FWPHY_PC0

FW_PHY_PC0

SYNC_MASTER=K22

MAKE_BASE=TRUE

SYNC_DATE=09/02/2009

A

PAGE TITLE

iMacs are now one port only and have Power Code "000"

FW: 1394B MISC

1

R4257
10K

DRAWING NUMBER

5%
1/16W
MF-LF
2 402

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

42 OF 110
SHEET

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8

7

6

5

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3

2

1

8

7

6

5

4

3

2

1

CRITICAL
INRUSH RESETABLE PTC

F4301
0.3AMP-60V
1

2
PLACEMENT_NOTE=PLACE CLOSE TO F4300

XW4300

SMD030F-SM

R4300
0.33 2
1

=PP12V_S5_FW

5%
1W
MF
2512

FAST NON-RESETABLE FUSE
THIS FUSE WILL NOT BLOW
IT IS HERE FOR SAFETY ONLY
CRITICAL

P12V_S5_FW_CL

SSOT6

MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V

1

2

CRS08-1.5A-30V

CRITICAL

L4300

F4300

P12V_S5_FW_D

1

MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V

D

FERR-250-OHM

3AMP-32V
FW_PORT0_VP_F

2

1

MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V

603

FW_PORT0_VP

2

MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V

SM

4

5

12 VOLTS
7 WATTS MAX PER PORT

42

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

D4300
SM

FDC610PZ

MIN_LINE_WIDTH=1.7MM
MIN_NECK_WIDTH=0.5MM
VOLTAGE=12V

PPVP_FW_PHY_CPS
VOLTAGE=12V

Q4300

P12V_S5_FW_R

2

SM

CRITICAL

6

D

43 6

1

CRITICAL
POUR COPPER TO SINK HEAT

2

1

1

0.01UF

3

5.1V

3

SHOULD BE DONE AS A POWER STRIP(SUBPLANE)

D4301

MMBT2907AXG
60V-600MA

MMBZ5231BXG

SOT23

1

1

Q4301

C4300

10%
50V
2 X7R
603-1

SOT23

3

2

R4352
51.1K2
1

FW_CURRENT_LIMIT

43

1%
1/16W
MF-LF
402

1

R4301
10K

FW_TURN_ON_V

5%
1/16W
MF-LF
2 402

3

Q4302

1

15K

20K

5%
1/10W
MF-LF
2 603

5%
1/16W
MF-LF
2 402

& "Late VG" Protection
CRITICAL

DP4310

CRITICAL

DP4310

BAV99DW-X-G
SOT-363
5

BAV99DW-X-G

C4310

1

0.01UF

SOT-363
2

10%
50V 2
X7R
402

FW_FET_LINEAR_LIMIT_OUT 43
FW_FET_LINEAR_LIMIT_IN 43

SOT23
2

PP3V3_FW_ESD "Snapback"

R4302 1R4303

FW_CURRENT_LIMIT_Q

MMBT2222A7F

43

1

C4311

1

0.01UF
6

3

10%
50V 2
X7R
402

4

PORT 0
1394B

1

PLACE CLOSE TO COMPARITOR
1
1

C4302
0.01UF

C

2

R4307
20K

5%
1/16W
MF-LF
2 402

20%
16V
CERM
402

105 42

C

CRITICAL

FW_PORT0_TPB_N

J4300

1394B-K22
105 42

F-ANG-TH

FW_PORT0_TPB_P

1

TPB-

TPB(R)

9
2

105 42

FW_PORT0_TPA_P

1

FW_FET_LINEAR_LIMIT_FB

3

7

3

FW_PORT0_TPA_R

SOT23

43

PP3V3_FW_ESD

1

C4304
0.1UF

8

10%
16V
X7R-CERM
402

2

V+

C4312

LM393

R4305
43

FW_CURRENT_LIMIT

1

100K 2

FW_CURRENT_LIMIT_R

5%
1/16W
MF-LF
402

B

5.1V

6
5

3

SOI-HF

1
43

FW_CURRENT_LIMIT_RD
FW_FET_LINEAR_LIMIT_IN

DP4311

BAV99DW-X-G

BAV99DW-X-G

10%
50V 2
X7R
402

NC

1

C4313
0.01UF

1

FW_FET_LINEAR_LIMIT_OUT

TPA+

VG

TPA(R)

C4332

SHIELD
PINS

11
1

514-0656

0.001UF

10%
50V
CERM 2
402

3
1
4

10%
50V
X7R 2
402

R43351

2
3

SC/NC
TPA-

10

NOSTUFF

SOT-363
5
6

1

0.01UF

7

CRITICAL

DP4311
SOT-363
2

U4300

D4303
SOT23

VP

5
4

CRITICAL

=PP12V_S5_FW

TPB+

8

6

BAS40XG

5%
1/16W
MF-LF
402
43 6

FW_PORT0_TPA_N

D4302

R4304
100K 2
1

105 42

43

1

1M

GND

C4335
0.1UF

1%
1/16W
MF-LF
402 2

MMBZ5231BXG

10%
2 50V
X7R
603-1

B

4
1

PLACE CLOSE TO COMPARATOR

C4305

1

2.2UF

10%
16V 2
X5R
603

R4306
200K

5%
1/16W
MF-LF
2 402

ESD Rail
R4390
42 41 6

=PP3V3_FW_FWPHY

1

332

PP3V3_FW_ESD

2

43

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

D4390
SOT23
1

[ LATE VG NOTES ]
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP

3

1%
1/16W
MF-LF
402

MMBZ5227BLT1H

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

FIREWIRE CONNECTOR
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

43 OF 110
SHEET

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8

7

6

5

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3

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8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

44 OF 110
SHEET

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8

7

D

6

5

4

3

2

1

D

SATA PORT A0 FOR HDD
CRITICAL

J4510
EP00-081-91

C4510

M-ST-SM
1

1

2

1

2

10%

0.01UF
110
102
110
102

2
3

C4511

SATA_HDD_R2D_P
SATA_HDD_R2D_N

10%

0.01UF

16V

CERM

402

16V

CERM

402

SATA_HDD_R2D_C_P

IN

20 102

SATA_HDD_R2D_C_N

IN

20 102

SATA_HDD_D2R_N

OUT

20 102

SATA_HDD_D2R_P

OUT

20 102

SATA Activity LED

4
5

110
102

6

110
102

SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P

C4515

7

1

2

1

2

10%

0.01UF

C4516

10%

0.01UF

518S0251

16V

16V

CERM

CERM

402
6

402

=PP3V3_S0_SATALED
DEVELOPMENT

R4599

1

330
5%
1/10W
MF-LF
603

2

MCP_SATALED_R_L
1

DEVELOPMENT

DS4599

518-0361

GREEN-3.6MCD

SATA PORT A1 FOR SLIMLINE ODD

2.0X1.25MM-SM
2

J4520

20

1735574
M-ST-TH

C

50 49

C4517

S3

S5
S6

1

110 102 SATA_ODD_R2D_N

16V

CERM

402

16V

CERM

402

16V

CERM

402

2
10%

0.01UF

C4519

110 102 SATA_ODD_D2R_C_N
110 102 SATA_ODD_D2R_C_P

KEY

2

2

10%

0.01UF

P1
P2

1

1

0.01UF

C4520

S7

GND

MD
GND
GND

10%

0.01UF

C4518

110 102 SATA_ODD_R2D_P

2

SATA_ODD_R2D_C_P

IN

20 102

SATA_ODD_R2D_C_N

IN

20 102

SATA_ODD_D2R_N

OUT

20 102

SATA_ODD_D2R_P

OUT

20 102

C

SMC_EXCARD_OC_L

S4

BB+

DP
+5V
+5V

1

S1
S2

MCP_SATALED_L
MAKE_BASE=TRUE

14

GND
A+
AGND

TP_MCP_SATALED_L

SILK_PART=SATA ACTIVE

=PP5V_S0_SATA

10%

16V

CERM

402

6

P3

=PP3V3_S0_ODD

P4

C4530 C4531
1

P5

0.1UF

10%
2 25V
X5R
402

P6

6

1

1

R4530

0.1UF

10%
25V
2 X5R
402

33K
5%
1/10W
MF-LF
603

15

2

SMC_ODD_DETECT

49 110

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

SATA Connectors
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

45 OF 110
SHEET

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8

7

6

5

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7

6

5

4

3

2

1

CRITICAL

U4601
TPS2060

2

46 6

20 9

USB_EXTC_OC_L

9

USB_EXTD_OC_L

IN

CRITICAL

7

L4630

FERR-250-OHM

OC1*

3

OUT2

EN1*

5

6

OC2*

4

R4600
10K

1

9

6

1

OMIT
CRITICAL

0.1UF

20%
10V
2 CERM
402

1

0.01uF
20%
16V
CERM
402

2

C4631
0.1UF

1

20%
10V
2 CERM
402

C4650
0.1UF

20%
10V
2 CERM
402

C4606

CRITICAL

J4630
USB-K22

CRITICAL

150UF

CRITICAL

9

C4605

1

0.1UF

20%
10V
2 CERM
402

USB_PWR_ENA_L

1

C4621

PP5V_USB2_PORT3_F
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

C4630

(PUT CAP ON CONNECTOR SIDE)

=PP3V3_S5_SMCUSBMUX

2
SM

1

GND TPAD

5%
1/16W
MF-LF
2 402

1

PP5V_USB2_PORT3
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

USB/SMC DEBUG MUX

EN2*

1

D

OUT1

MSOP

8

20%
2 6.3V
POLY-TANT
CASE-D2-SM

5 M+
4 M-

SMC_RX_L
SMC_TX_L

51 50 49
51 50 49

MOJOMUX

U4650

F-ANG-TH
5

L4631

VCC

120-OHM-90MA
DLP0NS

Y+ 1
Y- 2

VDD
DD+
GND

SYM_VER-1

4

103 USB_D_MUXED_N

3

103 USB_PORT3_N

PI3USB102ZLE
TQFN
1

103 USB_D_MUXED_P

USB_DEBUGPRT_EN_L
SEL=0: CHOOSE SMC
SEL=1: CHOOSE USB

SEL 10

8 OE*

2

103 USB_PORT3_P

3

2N7002

6 VBUS

R4651

G

4

514-0659

1 GND

PRODUCTION
1

PM_EN_USB_PWR

3

SOT23-HF1

D

70

VBUS
DATADATA+
GND

2

2 5 3 4

GND

Q4600

1

D

6

49 50

NC
IO
NC
IO

7 D+
6 D-

USB_EXTD_P
USB_EXTD_N

103 20
103 20

3

PORT 3

=PP5V_S3_USB

0

S
1

PRODUCTION

2

R4652
1

0

2

2

D4630

5%
1/16W
MF-LF
402

RCLAMP0502N
SLP1210N6
CRITICAL

5%
1/16W
MF-LF
402

CRITICAL

L4620

FERR-250-OHM

TPS2060
2

USB_EXTA_OC_L

8
3

20

CRITICAL

OUT1 7

IN

5 OC2*
4
EN2*

USB_EXTB_OC_L

1

PP5V_USB2_PORT1
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

0.1UF

OMIT
CRITICAL

0.1UF

20%
2 10V
CERM
402

1

C4603

330UF

20%
16V
CERM
402

2

C4611
0.1UF

20%
2 10V
CERM
402

C4602

1

CRITICAL

(PUT CAP ON CONNECTOR SIDE)

20%
2 10V
CERM
402

CRITICAL

20%
2 6.3V
POLY-TANT
CASE-D3L-SM1

J4610
USB-K22
CRITICAL

F-ANG-TH1
5

L4611

120-OHM-90MA
DLP0NS

103 20

4

USB_EXTB_N

3

1

USB_EXTB_P

103 USB_PORT1_N

2

1

VDD
DD+
GND

SYM_VER-1

103 20

20%
16V
CERM
402

J4620

0.01uF

9
1

C4601

2

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

SM

GND TPAD

1

2

C4620

C4610

1
1

PP5V_USB2_PORT1_F

C

PP5V_USB2_PORT2_F
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

0.01uF

(PUT CAP ON CONNECTOR SIDE)

FERR-250-OHM

OUT2 6

EN1*

1

L4610

MSOP
OC1*

103 USB_PORT1_P

PORT 1

20

=PP5V_S3_USB

2
SM

PORT 2

U4600
46 6

1

PP5V_USB2_PORT2
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

CRITICAL

USB-K22
CRITICAL

3
4

VDD
DD+
GND

SYM_VER-1

103 20

103 20

4

USB_EXTC_N

1

USB_EXTC_P

3

2

103 USB_PORT2_N

103 USB_PORT2_P

1
2
3
4

VBUS
DATADATA+
GND

6

514-0659

VBUS
DATADATA+
GND

2

F-ANG-TH
5

L4621

120-OHM-90MA
DLP0NS

2 5 3 4
6 VBUS

NC
IO
NC
IO

C

1 GND
6

NC
IO
NC
IO

2 5 3 4

B

6 VBUS

B

D4620
RCLAMP0502N

514-0672

1 GND

SLP1210N6
CRITICAL

D4610
RCLAMP0502N
SLP1210N6
CRITICAL

CRITICAL

L4600

FERR-250-OHM
1

2
SM

1

PP5V_USB2_PORT0_F
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

C4600
0.01uF

2

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

20%
16V
CERM
402

(PUT CAP ON CONNECTOR SIDE)

TABLE_5_ITEM

128S0238

1

330UF, TANT-POLY BULK CAP

C4602

CRITICAL

K23

128S0225

1

150UF, TANY-POLY BULK CAP

C4606

CRITICAL

K22

TABLE_5_ITEM

CRITICAL

J4600
USB-K22
CRITICAL

F-ANG-TH1
5

L4601

120-OHM-90MA
DLP0NS

A

VDD
DD+
GND

SYM_VER-1

103 20

103 20

4

USB_EXTA_N

1

USB_EXTA_P

3

2

103 USB_PORT0_N

103 USB_PORT0_P

2
3
4

VBUS
DATADATA+
GND

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

EXTERNAL USB CONNECTORS

NC
IO
NC
IO

6

Apple Inc.

051-7863

514-0672

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D4600
RCLAMP0502N
SLP1210N6

7

6

5

D

A.0.0
BRANCH

PAGE

46 OF 110
SHEET

 OF 

CRITICAL

8

SIZE

REVISION

R

1 GND

A

PAGE TITLE

DRAWING NUMBER

2 5 3 4
6 VBUS

1

PORT 0

PP5V_USB2_PORT0
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

4

3

2

1

8

7

6

5

4

3

2

1

CAMERA CONNECTOR & FILTER
CRITICAL

L4701

K37L (BLUETOOTH) CONNECTOR

120-OHM-90MA
DLP0NS
SYM_VER-1

D

103 20

4

USB_CAMERA_P

110 103 USB_CAMERA_L_P

103 20

1

USB_CAMERA_N

2

CRITICAL

CRITICAL

110 103 USB_CAMERA_L_N

J4720

L4720

53261-8605

120-OHM-90MA
DLP0NS

CRITICAL

J4700

M-RT-SM

6

SYM_VER-1

103 20

USB_BT_N

4

3

103 20

USB_BT_P

1

2

53780-8605

110 103

M-RT-SM

6
1
2
3

CRITICAL
6

D

3

L4700

=PP5V_S3_CAMERA

FERR-250-OHM
1
1

C4700

SM

10UF

4
5

CRITICAL

L4721

FERR-250-OHM
7
6

=PP3V3_S3_BT

1

2
SM

PP3V3_S3_BT
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

1

7

C4701

20%
6.3V
2 CERM
805-1

4
5

PP5V_S3_CAMERA
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

2

1

0.1UF

C4720
10UF

20%
6.3V
2 CERM
805-1

518S0668

20%
10V
CERM 2
402

1
2
3

USB_BT_L_N

110 103 USB_BT_L_P

1

C4721
0.1UF

518S0688

20%
10V
2 CERM
402

LAYOUT NOTE:
PLACE C4700, C4701 & L4700
NEAR J4700 PINS 4 AND 5 IN THE
ORDER LISTED, AND NOT ON
BOTH SIDES OF THE PIN.

C

C

IR RECEIVER CONNECTOR

SD Card Reader Board Connector
CRITICAL
CRITICAL
CRITICAL

CRITICAL

4
103 20

6

L4751

=PP3V3_S3_SDCARD

103 20

USB_SDCARD_N
USB_SDCARD_P

1

2
SM

M-RT-SM
5

SYM_VER-1

M-RT-SM
7

103 20

USB_IR_N

4

3

103 20

USB_IR_P

1

2

3

1

2

110 103 USB_SDCARD_L_N

1

110 103 USB_SDCARD_L_P

2

C4750

1

1UF
10%
6.3V
CERM
402

1

110 103 USB_IR_L_P

2

PP5V_S3_IR
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

L4703

4

PP3V3_S3_SDCARD
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM

110 103 USB_IR_L_N

CRITICAL

3

FERR-250-OHM

B

53261-8604

120-OHM-90MA
DLP0NS

53261-8606

SYM_VER-1

CRITICAL

L4702

J4750

L4750

120-OHM-90MA
DLP0NS

J4780

FERR-250-OHM

5
6

6

=PP5V_S3_IR

1

3
4

B

6

2
SM

2

1

8

C4781
1UF

518S0690
2

10%
6.3V
CERM
402

CARDREADER_RESET_L

Q4700

D

3

S

4

SSM6N15FEAPE
SOT563

5
17

G

CARDREADER_RESET

CARDREADER_PLT_RST

Q4700

D

6

S

1

SSM6N15FEAPE
SOT563

2
9

G

CARDREADER_PLT_RST_L

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Internal USB Connections
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

47 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

48 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

50
50 6

PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC

D

D
C4902

1

1

2

2

22UF

IN

NC
21

OUT

71

OUT

21

OUT

50

OUT

95

IN

95

IN

95

IN

95

IN

95

OUT

91 95

OUT

PM_RSMRST_L
PM_EN_PVCORE_CPU
PM_PWRBTN_L
ESTARLDO_EN
SMC_VIDEO_ON
AUXCH_P_STATE
AUXCH_N_STATE

NC

C

103 51 19

BI

103 51 19

BI

103 51 19

BI

103 51 19

BI

51 103 19

IN

9

IN

103 9
51 19

IN
BI

SMC_DP_HPD
BIDIVI_AUDIO_MUX_SEL
DPMUX_VIDEO_IN_SEL
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ

NC
BI

SMC_P41
SMB_MGMT_DATA
SMS_ONOFF_L

50

OUT

(OC)

NC
NC
50

OUT

51 50 49 46

OUT

SMC_GFX_THROTTLE_L

NC
50 49 51 46
52

(DEBUG_SW_1)
(DEBUG_SW_2)

SMC_PA0
SMC_PA1
PM_SYSRST_L
OUT
USB_DEBUGPRT_EN_L
OUT
MEM_EVENT_L
BI
SMC_PA5
50
SYS_ONEWIRE
BI
PM_BATLOW_L
OUT

(OC)

55 32 31 21

50
21

OUT
IN

55

IN

50 45

IN

136
137
138
2
3
4
5
6

P40
P41
P42
P43
P44
P45
P46
P47

16
15
14

P50
P51
P52

41
40
39
38
37
35
34
33

(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

50

IN

SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
NC_SMC_PB3
SMC_EXCARD_CP

NC

56

OUT

56

OUT

57

OUT

50

OUT

56

IN

56

IN

57

IN

50

IN

50

IN

50

IN

50

IN

50

IN

50

IN

50

IN

50

IN

50

IN

SMC_EXCARD_OC_L
SMC_GFX_OVERTEMP_L

TQFP
(1 OF 3)
OMIT

P60
P61
P62
P63
P64
P65
P66
P67

78
79
80
81
82
83
84
85

P70
P71
P72
P73
P74
P75
P76
P77

68
69
70
71
72
73
74
75

P80
P81
P82
P83
P84
P85
P86

129
130
131
132
133
134
135

P90
P91
P92
P93
P94
P95
P96
P97

24
23
22
21
20
19
18
17

120
119
118
117
116
115
114
113

SMC_FAN_0_CTL
SMC_FAN_1_CTL
SMC_FAN_2_CTL
SMC_FAN_3_CTL
SMC_FAN_0_TACH
SMC_FAN_1_TACH
SMC_FAN_2_TACH
SMC_FAN_3_TACH

94
93
92
91
90
89
88
87

SMS_X_AXIS
SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE
SMC_NB_DDR_ISENSE
ALS_LEFT
ALS_RIGHT

66
65
64
63
62
61
60
59

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

HS82117
TQFP
(2 OF 3)
OMIT

PE0
PE1*
PE2*
PE3*
PE4*
PF0

32
31
30
29
28
50

PF1
PF2
PF3
PF4
PF5
PF6
PF7

49
48
47
46
45
44
43

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

58
57
56
55
54
53
52
51

PH0
PH1
PH2
PH3
PH4
PH5

10
12
26
140
141
142

C4906
0.1UF

20%
10V
CERM
402

2

20%
10V
CERM
402

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

SMC_PM_G2_EN

OUT

50

NC
NC
NC

SMC_VCL

R4999
1

SMC_ADAPTER_EN

OUT

SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L
SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE
SMC_WAKE_SCI_L

IN

50

IN

50

IN

53 108

IN

53 108

IN

53 108

IN

108 53

IN

50

IN

50

IN

50

IN

50

OUT

21

4.7

2

5%
1/16W
MF-LF
402

21 50

NC

PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

C4907

C4920

1

10%
6.3V
CERM-X5R
402

0.1UF
20%
10V
CERM
402

AVCC

2

VCC

VCL AVREF

2

R4909

U4900

NC

HS82117

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

1

0.47UF

TQFP
(3 OF 3)
OMIT

51 50

IN
50
50

SMC_RESET_L
SMC_XTAL
SMC_EXTAL

8
143
144

RES*
XTAL
EXTAL

MD1
MD2

9
25

NMI

11

ETRST*

27

AVSS

67

1

1

R4901

10K

10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

SMC_MD1

IN

51

SMC_NMI

IN

51

SMC_TRST_L

IN

51

SMC_KBC_MDE

NC

(OC)

PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK

(OC)

SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLPS3_BUF2_L
PM_SLP_S4_SMC_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA

U4900

NC
21
110 45

HS82117

P30
P31
P32
P33
P34
P35
P36
P37

50

50 46

A

P20
P21
P22
P23
P24
P25
P26
P27

50

28

B

IN
BI

SMC_TX_L
SMC_RX_L
SMB_0_S0_CLK

103
102
101
100
99
98
97
96
121
122
123
124
125
126
127
128

50
52

P10
P11
P12
P13
P14
P15
P16
P17

C4905
0.1UF

2

77

IN

70

112
110
109
108
107
106
105
104

20%
10V
CERM
402

2

13

70

SMC_EXCARD_PWR_EN
SMC_RSTGATE_L
ALL_SYS_PWRGD_SMC
RSMRST_PWRGD

C4904
0.1UF

20%
10V
CERM
402

1
36
86

OUT

0.1UF

1

76

OUT

50

U4900

C4903

1

OUT

51 19

IN

19 51

OUT

46 49 50 51

IN

46 51 49 50

BI
IN
IN

50

IN

6 9 50 70

IN

70 50

IN

50

IN

9 103

XW4900
SM
2

50

IN

BI

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS

52

50

NOTE: P94 and P95 are shorted, P95 could be spare.

C

NO STUFF
1

VSS
7
42
95
111
139

50

20%
6.3V
CERM-X5R
805-3

1

1

R4902

R4998

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

1

R4903
0

5%
1/16W
MF-LF
2 402

1

GND_SMC_AVSS

50 53 54

52

IN

50

IN

51 50

IN

51 50

OUT

51 50

IN

51 50

B

NC
SMC_SYS_LED
SMC_LID
BIDIVI_AUX_TERM_EN
BIDIVI_PNL_PWR_EN
SMC_MCP_SAFE_MODE
BIDIVI_BKL_ON
BIDIVI_BKL_PWM

(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

SMC_PNL_BL_PWM
=SMC_SMS_INT
SMB_BSA_DATA
SMB_BSA_CLK
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
SMB_B_S0_CLK
SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN

OUT

50

OUT

50

OUT

95

OUT

95

OUT

50

OUT

95

OUT

95

IN
IN

50 95
50

BI

52

BI

52

BI

52

BI

52

BI

52

BI

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

52

OUT

50

OUT

50

OUT

50

50

NC
NC

SYNC_MASTER=MARKVIDEO

SYNC_DATE=03/12/2009

A

PAGE TITLE

SMC
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

49 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4
49

SMS_Z_AXIS

49

ALS_LEFT

NO_TEST=TRUE

49

1

CRITICAL

0.1uF
20%
10V
CERM
402

DEVELOPMENT

S5000

2

SOT23-5-HF

NTC020-CC1J-B260T
1 SM 2
SMC_MANUAL_RST_L

D

5

NC

C5001

4

CD
NC
GND

1

10%
16V
CERM
402

4

R5000

49

NO_TEST=TRUE
NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
NO_TEST=TRUE

SMC_ANALOG_ID

1

51 49 46
49 51 46
49
49

SMC_RESET_L

OUT

UNUSED TP/NC ALIASES

51 49

49 51
51 49

2
49

ALS_GAIN

49

SMC_PM_G2_EN

49 51

NC_ALS_GAIN
NO_TEST=TRUE
TP_SMC_PM_G2_EN

MAKE_BASE=TRUE

3

0.01UF
3

OUT
IN

49

NC_ALS_RIGHT

5%
1/16W
MF-LF
2 402

NCP303LSN

95 49

NO_TEST=TRUE

MAKE_BASE=TRUE

1K

U5000

ALS_RIGHT

SMC_ONOFF_L
SMC_PNL_BL_PWM
SMC_PH2
SMC_TX_L
SMC_RX_L
SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_EXCARD_OC_L
SMC_PA0
SMC_PA1
SMC_BIL_BUTTON_L
SMC_FAN_3_CTL
SMC_FAN_3_TACH
SMC_BC_ACOK
SMC_ADAPTER_EN
USB_DEBUGPRT_EN_L

49 50

NC_ALS_LEFT
MAKE_BASE=TRUE

1

49 51
49 45

MAKE_BASE=TRUE
2

49
49
49

SILK_PART=SMC RESET

SMC_EXCARD_PWR_EN

TP_SMC_EXCARD_PWR_EN

49

MAKE_BASE=TRUE
49

SMS_ONOFF_L

49

TP_SMS_ONOFF_L
MAKE_BASE=TRUE

49

SMC_RSTGATE_L

49

TP_SMC_RSTGATE_L

49

MAKE_BASE=TRUE

POWER BUTTON

49

49

J5010

Y5020

1

SM-4

1

POWER_BUTTON_L

49

10K
10K

1

2

1

2

1

2

1

SMC_CPU_INPUT_ISENSE

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

49

SMC_PBUS_VSENSE

49

SMS_X_AXIS

SMC_CPU_INPUT_VSENSE

49

R5010
1

DEVELOPMENT

1K
5%
1/16W
MF-LF
402

S5010

SMC_ONOFF_L OUT

2

1

49 50

49

50 49

SMC_1V5_S0_VSENSE

1

2

1

2

1

2

1

2

1

2

1

2

SMC_PA5

R5093

10K

1

2

SMC_GFX_OVERTEMP_L

R5099

10K

1

2

SMS_Y_AXIS

SMC_MCP_CORE_VSENSE

49

SMC_NB_DDR_ISENSE

0.1UF

49

SMC_NB_CORE_ISENSE

20%
10V
CERM
402

49

SMC_1V5_S0_ISENSE

108 54

70 49 9 6

54 108

R5046
R5094

SMC_CASE_OPEN
PM_SLPS3_BUF2_L

49

SMC_MCP_CORE_ISENSE

SMC_BATT_ISENSE

1

SMC_NB_MISC_ISENSE

R5050

49

10K
100K

SMC_GFX_OVERTEMP_L

R5089

MAKE_BASE=TRUE

2

C5065

SMC_GFX_THROTTLE_L

0.47UF

10uF

10%
6.3V
CERM-X5R
402

20%
6.3V
X5R
603

71 55 10 6

85

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

D

=PP3V3_S0_SMC

402

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

TO SMC
SMC_PROCHOT_3_3_L

OUT

2

100K

1

C

2

=PP3V3_S0_SMC_LS

=PPVTT_S0_CPU

51

1

2

1

SMC_IG_THROTTLE_L

C5067

2

R5070

5%
1/16W
MF-LF
2 402

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

1

0

TABLE_ALT_ITEM

353S1381

353S1278

ALL

CPU_PROCHOT_BUF

R5019

Intersil ISL60002-33

49

SMC_MCP_SAFE_MODE

1

FOR 
2

2

49

3

Q5077

TABLE_ALT_HEAD

PART NUMBER

5%
1/16W
MF-LF
402

3.3K

21

MAKE_BASE=TRUE

5%
1/16W
MF-LF
402

R5078
470

R5020

49

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

GND_SMC_AVSS

5

MMDT3904-X-G
SOT-363-LF

MCP_SPKR

4

21

TO CPU

5%
1/16W
MF-LF
402

100 14 11

R5071
1

CPU_PROCHOT_L

BI

3.3K

2

6

CPU_PROCHOT_L_R

49 53 54

Q5077

2

MMDT3904-X-G
SOT-363-LF

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

B

1/16W

85

MXM_PWR_LEVEL

0.01UF

C5066

402

5%

PLACEMENT_NOT=PLACE CLOSE TO U4900(SMC)

55 50 6

MXM_ALERT_L

GND

1

402

MF-LF

MAKE_BASE=TRUE

PP3V3_S5_AVREF_SMC

10%
16V
CERM
402

MF-LF

1/16W

MF-LF

2

1

2

1/16W

5%

1/16W

1

MAKE_BASE=TRUE

3

402

5%

1/16W

1

IG

1

MF-LF

SMC PROCHOT 3.3V LEVEL SHIFTING

MISC. SIGNAL ALIASES
50 49

PM_SLP_S4_SMC_L
PM_SLP_S5_L

49 70

5%
1/16W
MF-LF
2 402

4

49

2

1/16W

SMC_UNUSED_ADC_PORT7

VR5065
OUT

402

5%

MAKE_BASE=TRUE

CRITICAL

IN

402

MF-LF

5%

MAKE_BASE=TRUE

SMC AVREF Supply
1

MF-LF

1/16W

108 54

MAKE_BASE=TRUE

C5010

SILK_PART=SYS POWER

SOT23-3

1/16W

5%

5%

108 54

10K

REF3133

402

5%

MAKE_BASE=TRUE

49

=PP5V_S5_AVREF

402

MF-LF

MAKE_BASE=TRUE

NTC020-CC1J-B260T
1 SM 2

3

MF-LF

1/16W

2

53

MAKE_BASE=TRUE

CRITICAL

2

1/16W

5%

53

MAKE_BASE=TRUE

2

6

2

=PP3V3_S5_SMC

5%

54 53 6

SMC_DCIN_ISENSE

4

5%
50V
CERM
402

C

MAKE_BASE=TRUE

R5091
R5087

2

ANALOG SENSORS

518S0665

22PF
1

SMC_EXTAL

SMC_SMS_INT

1

2

C5021

2

=SMC_SMS_INT
SMC_LID

49
49

49

20.000M

TP_ESTARLDO_EN
MAKE_BASE=TRUE

10K
100K
10K
10K
100K
2.0K
100K
10K
10K
10K
10K
10K
10K
10K
10K
100K
100K
10K
10K
10K

2
5%
50V
CERM
402

CRITICAL

ESTARLDO_EN

49 46

NO STUFF

R5032
R5033
R5034
R5035
R5036
R5037
R5038
R5039
R5040
R5041
R5042
R5043
R5096
R5090
R5092
R5095
R5097
R5047
R5049
R5098

M-RT-SM
3

22PF
1

SMC_XTAL

21 49

TP_SMC_P41

53261-8602

C5020
49

SMC_P41

MAKE_BASE=TRUE

SILK_PART=PWR BTN

SMC Crystal Circuit

1
50 49 6

NC_SMS_Z_AXIS
MAKE_BASE=TRUE

=PP3V3_S5_SMC

C5000

2

UNUSED TP/NC ALIASES - PORT D - INTERNAL PULLUPS

SMC Reset Button / Brownout Detect
50 49 6

3

1

B

3

D

FROM SMC

Q5095
2N7002DW-X-G

49

5

SMC_PROCHOT

IN

G

SOT-363

S

SIL: FOR DEVELOPMENT USE ONLY
4

6

SMC & MXM THERMTRIP LEVEL SHIFTING

=PP3V3_S3_SMC
DEVELOPMENT
55 50 6

1

R5075

=PP3V3_S0_SMC_LS
MXM

1K

MXM

5%
1/16W
MF-LF
2 402

SYS_LED_AN
1

1

R5068

R5069

10K

DEVELOPMENT

MXM_THRMTRIP_L

5%
1/16W
MF-LF
2 402

3

D

LED5075
2

MXM_THRMTRIP
6

D

3
D

Q5075

85

2N7002
SMC_SYS_LED

1

G

SOT23-HF1

S

IN

MXM_OVERT_L

G

MXM

6

D

Q5096
49

IN

SMC_THRMTRIP

11 100 14

2N7002DW-X-G
2

4

MXM

OUT

PULL-UP ON PAGE 14

Q5095

FROM SMC

SOT-363

S

PM_THRMTRIP_L

2

G

SOT-363

S
1

Q5096

FROM MXM

DEVELOPMENT

5

0

5%
1/16W
MF-LF
402

2N7002DW-X-G

GREEN-3.6MCD
2.0X1.25MM-SM

SYS_LED_CATH

49

1

3.3K

5%
1/16W
MF-LF
2 402

SILK_PART=SIL

R5018

MXM

1

2N7002DW-X-G
2

G

SOT-363

S
1

2

A

SYNC_MASTER=MARKVIDEO

SYNC_DATE=03/12/2009

A

PAGE TITLE

SMC Support
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

50 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

LPC+SPI Connector
FRANK CONNECTOR

CRITICAL
LPCPLUS

J5100

55909-0374

D

6

103 49 19

BI

103 49 19

BI

51

IN

51

OUT

103 49 19
49 19
50 49
9
50 49

IN
OUT
OUT
IN
OUT

49

IN

49

OUT

50 49 46

M-ST-SM
31
32

=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS

51 6

IN

LPC_AD<0>
LPC_AD<1>
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

33

34

D
LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>

IN
BI
BI

SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

9 103
19 49 103
19 49 103

OUT

51

IN

51

IN

51

BI

19 49

IN

19 49

OUT

49 50

OUT

49 50

OUT

49 50

OUT

49

OUT

46 49 50

OUT

18

516S0573

C

C

Alternate SPI ROM Support
51 6
61 6

=PP3V3_S5_LPCPLUS
=PP3V3_S5_ROM
1

20K

OUT

SPI_MLB_CS_L

51 6

=PP3V3_S5_LPCPLUS

20%
2 10V
CERM
402

LPCPLUS

5%
1/16W
MF-LF
402 2
61

C5144
0.1UF

R51441

R5140

1

100K
5%
1/16W
MF-LF
402 2

U5100
NC7SB3157P6XG
PATH=I96
SC70
1 B1
SEL 6

51

SPIROM_USE_MLB

=SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

BI

21

1

2 GND

VCC 5

LPCPLUS

R5145

0
51

OUT

SPI_ALT_CS_L

3

4
B0

Pull-up on debug card

A

VER 1

CRITICAL

103

SPI_CS0_L

1

0

2
SPI_CS0_R_L IN 21 103
5% PLACEMENT_NOTE=Place near U1400
1/16W
MF-LF
402

PRODUCTION

R5146

B

0

1

5%
1/16W
MF-LF
402

B

2
PLACEMENT_NOTE=PLACE NEXT TO U5100

SPI Bus Series Resistance Option
LPCPLUS
R5156
51

OUT

SPI_ALT_CLK

1

51

OUT

0

2

SPI_ALT_MOSI

1

LPCPLUS
R5158
51

IN

SPI_ALT_MISO

1

PLACEMENT_NOTE=Place next to R6105

A

0

SPI_CLK_R

IN

21 61 103

SPI_MOSI_R

IN

21 61 103

OUT

21 61 103

LPCPLUS
R5157

5%
1/16W
MF-LF
402

PLACEMENT_NOTE=Place next to R6150

2

0
5%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place next to R6152

SPI_MISO

5%
1/16W
MF-LF
402

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

LPC+SPI Debug Connector
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

51 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

MCP79 SMBUS "0" CONNECTIONS

4

3

2

SMC "0" SMBus Connections

1

SMC "A" SMBus Connections
NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE

52 6

=PP3V3_S0_SMBUS

R5200 1

MCP79

106 21 13

106 21 13

1

4.7K

U1400
(MASTER)

D

6

R5201
4.7K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE

SO-DIMM "A"

SMC

J3100
(Write: 0xA0 Read: 0xA1)

U4900
(MASTER)

=PP3V3_S0_SMBUS_SMC_0_S0

6

R5250 1

=I2C_SODIMMA_SCL

31

49

SMB_0_S0_CLK

106

=I2C_SODIMMA_SDA

31

49

SMB_0_S0_DATA

106

1

4.7K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
2 402

2

MXM TEMP

R5251

4.7K

R52701

SMC

GPU ON CARD - J8400
NV INSIDE (WRITE: 0X9E READ: 0X9F)
MXM CARD (WRITE: 0X98 READ: 0X99)

SMBUS_SMC_0_S0_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

1

R5271

100K

U4900
(MASTER)

100K

5%
1/16W
MF-LF
402 2

=SMB_MXM_THRM_SCL

85

49

SMB_A_S3_CLK

106

=SMB_MXM_THRM_SDA

85

49

SMB_A_S3_DATA

106

MAKE_BASE=TRUE

5%
1/16W
MF-LF
2 402

D

SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE

Also reserve 0x56 and 0x32 per spec
SMBUS 0 ALSO GOES TO THE XDP CONNECTOR

SO-DIMM "B"

DIE TEMPS

J3200
(WRITE: 0XA2 READ: 0XA3)
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA

POTENTIAL SMC SLAVE SMBUS CONNECTIONS

EMC1403-2: U5535
(WRITE: 0X9A READ: 0X9B)

32

=SMB_MCP_CPU_THRM_SCL

55

=SMB_MCP_CPU_THRM_SDA

55

6

=PP3V3_S5_SMBUS_SMC_BSA

32

DIODE1: MCP

DIODE2: CPU

R52801

SMC
U4900
(MASTER)

CPU - PECI DTS
MAX6618 - U5570
(WRITE: 0X54 READ: 0X55)

49

SMB_BSA_CLK

106

1

R5281

100K

100K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

2

SMBUS_SMC_BSA_SCL

DISPLAY TCON
DP RX MASTER FOR MCCS
SMC SLAVE ADDRESS TBD

=SMB_DP_TCON_SCL

90

=SMB_DP_TCON_SDA

90

MAKE_BASE=TRUE
49

SMB_BSA_DATA

106

SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE

=SMB_CPU_PECI_SCL

55

=SMB_CPU_PECI_SDA

55

MCP79 SMBUS "1" CONNECTIONS
C

SMC "MANAGEMENT" SMBUS CONNECTIONS

C
52 6

=PP3V3_S0_SMBUS
6

MCP79
U1400
(MASTER)
21

21

R5202

1

2.2K
5%
1/16W
MF-LF
402 2

SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE

1

R5203
2.2K

5%
1/16W
MF-LF
2 402

=PP3V3_S0_SMBUS_SMC_MGMT

MIKEY
J9800
(WRITE: 0X72 READ: 0X73)
=I2C_AUDIO_SCL

68

=I2C_AUDIO_SDA

68

1

R5291

4.7K

U4900
(MASTER)

SMC "B" SMBus Connections

1

R5290

SMC

49

SMB_MGMT_CLK

106

49

SMB_MGMT_DATA

106

VREF DAC

4.7K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

SMBUS_SMC_MGMT_SCL

U2900
(Write: 0x98 Read: 0x99)
=I2C_VREFDACS_SCL

29

=I2C_VREFDACS_SDA

29

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE

6

=PP3V3_S0_SMBUS_SMC_B_S0

R5260 1

SMC
U4900
(MASTER)
49

SMB_B_S0_CLK

106

1

R5261

2.2K

2.2K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

2

2

MARGINGING CONTROL

REMOTE TEMPS

U2901
(WRITE: 0X30 READ: 0X31)

EMC1047-2, U5500, SEE TABLE
(WRITE: 0X90 READ: 0X91)

SMBUS_SMC_B_S0_SCL

=SMB_REMOTE_TEMP_SCL

55

=SMB_REMOTE_TEMP_SDA

55

MAKE_BASE=TRUE
49

SMB_B_S0_DATA

106

SMBUS_SMC_B_S0_SDA

=I2C_PCA9557D_SCL

29

=I2C_PCA9557D_SDA

29

MAKE_BASE=TRUE

DP RX EQ CONTROL

B

EMC1047-2 HEX DIODE SENSOR
DIODE
FUNCTION
1
2
3
4
5
6

ODD TEMP
LCD TEMP
AMBIENT TEMP
CPU HEATSINK
MXM HEATSINK
MCP HEATSINK

B

U9200
(WRITE: 0X92 READ: 0X93)

AC/DC PS TEMPS
EMC1403-[1,2]: ACDC THRU J600
(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)

=I2C_DP_EQLZ_SCL

92

=I2C_DP_EQLZ_SDA

92

3 SENSE POINTS - PRIMARY, SECONDARY, AMB

=SMB_ACDC_SCL

6

=SMB_ACDC_SDA

6

DP TX EQ CONTROL
U9100
(WRITE: 0X9C READ: 0X9D)

AC/DC PS POWER
INA219: ACDC THRU J600
(WRITE: 0X80, READ: 0X81))

=I2C_DP_DRV_SCL

91

=I2C_DP_DRV_SDA

91

OUTPUT VOLTAGE, CURRENT, POWER

A

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE

SMBus Connections
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

52 OF 110
SHEET

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8

7

6

5

4

3

2

1

8

7

6

5

4
53

3

2

1

MXM PWRSRC VOLTAGE SENSE

PPV_S0_MXM_PWRSRC
MXM

(SCALING 12V INPUT VOLTAGE TO SMC)

1

R5353
18.2K

SCALE

CPU Voltage Sense / Filter

4 V/V

PCB: PLACE C5359 WITHIN 1" OF SMC (U4900)

1%
1/16W
MF-LF
2 402

COUNT
.0129 V/COUNT

ADC IS 10BIT 0 TO 1023
0 TO 3.3V

SMC_GPU_VSENSE 49

R5309
108 12

IN

CPU_VCC_SENSE

1

1

OUT

R5354

49 108

GND_SMC_AVSS

D

20%
2 6.3V
X5R
402

1%
1/16W
MF-LF
2 402

20%
6.3V
X5R
402

C5359
0.22UF

6.04K

C5309
0.22UF

2

1

1

SMC_CPU_VSENSE

2
1%
1/16W
MF-LF
402

D

108

MXM

4.53K

GND_SMC_AVSS

49 50 53 54

49 50 53 54

OMIT

Place RC close to SMC

MXM PWRSRC (GPU CORE & MEM) CURRENT SENSE

R5380
0.025
1%
1W
MF
2512-1

54 53 50 6

=PP3V3_S0_SMC

6

1
3

=PPV_S0_MXM_PWR

CRITICAL
MXM
1

C5380
0.22UF

20%
2 6.3V
X5R
402

CPU CURRENT SENSE AMP & FILTER
R5363
21K

3

VCC
MAX4073TAXK+G65
SC70
RS_P 4
RS_M 5

1

1%
1/16W
MF-LF
402

84
TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

107S0063

1

25 MILLIOHM

R5380

CRITICAL

K22_MXM

107S0111

1

18 MILLIOHM

R5380

CRITICAL

K23_MXM

132S0242

1

CAP,0.082UF,402

C5381

MXM

116S0090

1

RES,10KOHM,5%,402

C5381

IG

TABLE_5_ITEM

108 MXM_PWRSRC_SENSOR_N

1

TABLE_5_ITEM

SMC_GPU_ISENSE

49 108

OMIT
1

TABLE_5_ITEM

C5381

1

10%
16V
CERM-X7R
402

2

353S2291
GAIN = 20

C5360

0.01UF

=PP5V_S0_ISENSE

10K

=PPV_S0_MXM_PWRSRC

COUNT
.0087518 A/COUNT

ADC IS 10BIT 0 TO 1023
0 TO 3.3V

TABLE_5_ITEM

R5360
VR_CPU_IOUT

SCALE
2.778 A/V

ADC IS 10BIT 0 TO 1023
0 TO 3.3V

0.082UF

C
IN

K51 SET FOR APPROX 1.98V AT 5.5A ON PWRSRC

COUNT
.0064453 A/COUNT

2 A/V

108 MXM_PWRSRC_SENSOR_P

2

GND_SMC_AVSS

2

20%
16V
CERM
402

108 71

OUT

SCALE

53

MAKE_BASE=TRUE
VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

U5380

2

1%
1/16W
MF-LF
402
6

PPV_S0_MXM_PWRSRC

MXM

GND
1

K50 SET FOR APPROX 2V AT 4A ON PWRSRC
2
4

49 50 53 54

C

PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)

U5360

2 108 VR_ISNS_CPU_P

VR_ISNS_CPU_N

1

5

OPA348
SC70-5
4
SNS_PS_CPU_ISNS

3
2

R5364
1

5.1K 2
5%
1/16W
MF-LF
402

SMC_CPU_ISENSE

R5361
10K

1%
1/16W
MF-LF
2 402

49 108

C5362

0.22UF

10%
2 6.3V
CERM-X5R
402

1

OUT

AMPLIFIED AND FILTERED ISNS TO SMC
1

CPU CORE INPUT SIDE CURRENT & VOLTAGE SENSE
GND_SMC_AVSS

49 50 53 54

CRITICAL

54 53 50 6

=PP3V3_S0_SMC

DEVELOPMENT
C5320 1
0.1UF

3

20%
10V
CERM
402

DEVELOPMENT

2

V+

U5320
71

CPU_INPUT_ISENSE_N

5 IN-

DEVELOPMENT
R5321

INA210
SC70

OUT

6 SMC_CPU_INPUT_IOUT

4.53K
1

CRITICAL
71

CPU_INPUT_ISENSE_P

4 IN+

SMC_CPU_INPUT_ISENSE

2
1%
1/16W
MF-LF
402

REF 1

C5321
0.22UF

GND

2

2

B

50

OMIT
1

20%
6.3V
X5R
402

GND_SMC_AVSS

B
49 50 53 54

PLACE RC CLOSE TO SMC

TABLE_5_HEAD

PART#
72 71

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

PP12V_S0_CPU_FLTRD

TABLE_5_ITEM

132S0080

1

CAP, 0.22UF, 0402

C5321

DEVELOPMENT

116S0004

1

RES, 0-Ohm, 0402

C5321

PRODUCTION

TABLE_5_ITEM

1

R5330
18.2K

1%
1/16W
MF-LF
2 402

SMC_CPU_INPUT_VSENSE
1

1

R5331

50

C5330
0.22UF

6.04K

20%
6.3V
2 X5R
402

1%
1/16W
MF-LF
2 402

GND_SMC_AVSS

A

49 50 53 54

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

CPU/MXM CURRENT AND VOLTAGE SENSE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

53 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

53 50 6

4

3

2

1

=PP3V3_S0_SMC
MCP_PWR_SENSE

OMIT

1

R5400
PP1V5_S0_FET

D

1
3

1.5V S0 CURRENT SENSE

2
4

PP1V5_S0

3

20%
2 6.3V
X5R
402

1%
1/4W
MF-LF
1206
78

C5400
0.22UF

0.002

MCP_PWR_SENSE

V+

6 54

108 SENSE_1V5_S0_N

5 IN-

108 SENSE_1V5_S0_P

4 IN+

R5401

INA210
SC70

D

MCP_PWR_SENSE

U5400

OUT

4.53K2

6 108 SMC_1V5_S0_ISENSE_R

1

SMC_1V5_S0_ISENSE

1%
1/16W
MF-LF
402

REF 1

OMIT
1

C5401
0.22UF

GND

20%
6.3V
2 X5R
402

2

353S2073
GAIN = 200V/V
TRANSFER RATIO = 0.4V/A

50 108

GND_SMC_AVSS

49 50 53 54

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

132S0080

1

CAP, 0.22UF, 0402

C5401

MCP_PWR_SENSE

116S0004

1

RES, 0 OHM, 0402

C5401

PRODUCTION

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

TABLE_5_ITEM

TABLE_5_ITEM

104S0018

1

RES,2 MILLIOHM,1206

R5400

CRITICAL

MCP_PWR_SENSE

101S0414

1

RES,0 OHM,1206,20MILLIOHM MAX

R5400

CRITICAL

PRODUCTION

1.5V S0 VOLTAGE SENSE

TABLE_5_ITEM

R5402
4.53K2

1

PP1V5_S0

54 6

SMC_1V5_S0_VSENSE

1%
1/16W
MF-LF
402

1

50 108

C5402
0.22UF

20%
6.3V
2 X5R
402

C

C
GND_SMC_AVSS

49 50 53 54

MCP CORE CURRENT SENSE
R5404
108 74

IN

MCPCORES0_IMON

4.53K
1

SMC_MCP_CORE_ISENSE

2

OUT

50 108

NOSTUFF

1%
1/16W
MF-LF
402

1

R5405

1

C5404
0.22UF

4.53K
1%
1/16W
MF-LF
402 2

2

20%
6.3V
X5R
402

GND_SMC_AVSS

49 50 53 54

Place RC close to SMC

SCALE IS 0.116 V/A

B

B
MCP CORE VOLTAGE SENSE
R5403
74 6

PPMCPCORE_S0_REG

4.53K2

1

1%
1/16W
MF-LF
402

SMC_MCP_CORE_VSENSE

1

50 108

C5403
0.22UF

20%
6.3V
2 X5R
402

GND_SMC_AVSS

49 50 53 54

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP CURRENT AND VOLTAGE SENSE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

54 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

REMOTE THERMAL SENSORS

3

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
MCP_CPU_TDIODE
6

R5535

=PP3V3_S0_MCPTHMSNS

22

1

SENSOR CH1

FERR-220-OHM
108 55

SNS_T_DP1_DN6

1

2

108 55

SNS_T_DN1_DP6

1

1

110

2

L5554

SNS_ODD_P
108 SNS_ODD_N

L5536

108 55

SNS_T_DN1_DP6

1

2

108 55

4

SNS_T_DP1_DN6

1

SNS_MCP_P

1

108 SNS_MCP_N

2

108

FERR-220-OHM

FERR-220-OHM

C5536

1

TSSOP

10%
50V
CERM
402
108 21

2

1

R5536
100K
5%
1/16W
MF-LF
402

10%
10V
X5R
402-1

MCP_CPU_TDIODE

R5537
10K

2

2

5%
1/16W
MF-LF
402

2

DP1

THERM*

7

MCPTHMSNS_THERM_L

3

DN1

ALERT*

8

MCPTHMSNS_ALERT_L

4

DP2/DN3

SMDATA

9

=SMB_MCP_CPU_THRM_SDA

BI

52

5

DN2/DP3

SMCLK

10

=SMB_MCP_CPU_THRM_SCL

BI

52

MCP_THMDIODE_N

BI

D

R5538
0

1

2

MEM_EVENT_L

21 31 32 49

5%
1/16W
MF-LF
402

2

GND

4

0402

108 11

CRITICAL

MCP_CPU_TDIODE
1

C5535
1UF

EMC1403-2-AIZL

2
0402

1

0.0022UF

0402
110 108

MCP_CPU_TDIODE

CRITICAL

U5535

SIGNAL_MODEL=EMPTY
MCP_CPU_TDIODE

M-ST-SM
3

2

0402

MCP_THMDIODE_P

BI

53398-8602

FERR-220-OHM

M-RT-SM
3

1

MCP_CPU_TDIODE
108 21

J5535

L5535

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

VDD

SILK_PART=MCP HSK

J5551
53780-8602

PP3V3_S0_MCPTHMSNS_R

2

5%
1/16W
MF-LF
402

SENSOR CH6

SILK_PART=ODD TEMP

L5553

1

MCP & CPU T-Diode Thermal Sensor

HEATSINKS, AMBIENT, PANEL AND ODD
D

2

CRITICAL

6

CPU_THERMD_P

OUT

353S2224

SIGNAL_MODEL=EMPTY
MCP_CPU_TDIODE

C5580

518S0698

1

0.0022UF
10%
50V
CERM
402

518S0678
108 11

SENSOR CH2

1

2

108 55

SNS_T_DN2_DP3

1

2

0402

C

SNS_LCD_P

110 108 SNS_LCD_N

2

110 108

L5521

1

SNS_T_DN2_DP3

108 14

CPU_PECI_MCP

BI

0402
1

SNS_AMB_P

1

110 108 SNS_AMB_N

2

110 108

L5523

FERR-220-OHM
108 55

M-RT-SM
4

FERR-220-OHM

2

4

108 55

SNS_T_DP2_DN3

1

C

3
55 6

2

0402

0402

=PP3V3_S0_TSENS

=PPVTT_S0_CPU

6 10 50 71

5

CRITICAL
518S0698

PECI_SMB

CRITICAL
518S0677

PECI_MCP

R5570

PECI_SMB

C5570

1

1

0.1UF

C5571

20%
10V
CERM
402

2

VCC

2

VREF

20%
10V
CERM
402

J5510

L5510

SNS_T_DP4_DN5

1

2

108 55

1

SNS_T_DN4_DP5

0402

L5511

108 55

2

MXM

SNS_MXM_P
108 SNS_MXM_N

108

L5513

2

FERR-220-OHM
1

M-ST-SM
3

0402
1

SNS_CPU_H_P
108 SNS_CPU_H_N

108

SNS_T_DN4_DP5

53398-8602

FERR-220-OHM

M-ST-SM
3

108

1

GND

11 108

2

5%
1/16W
MF-LF
402

PECI_SMB

AGND

20

1

SMB_PECI_L

8 AD2
9 AD1
3 AD0

J5511

MXM

L5512

53398-8602

FERR-220-OHM
108 55

SILK_PART=MXM HSK

7

SILK_PART=CPU HSK

52

PECI 1

2

SENSOR CH4

4 SDA
5 SCL

=SMB_CPU_PECI_SDA
=SMB_CPU_PECI_SCL

BI

R5571

USOP-HF
52

CPU_PECI_L

PECI_SMB

MAX6618
SENSOR CH5

2

5%
1/16W
MF-LF
402

U5570

PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU

20

1

0.1UF
10

SNS_T_DP2_DN3

53780-8603

FERR-220-OHM

M-RT-SM
3

CPU PECI DTS OPTIONS

J5521

L5522

53780-8602

6

108 55

SILK_PART=AMBIENT TEMP

J5520

L5520

PLACEMENT NOTE: PLACE U5535 NEAR MCP, TOP SIDE UNDER HEATSINK

SENSOR CH3

SILK_PART=LCD TEMP
FERR-220-OHM

2

CPU_THERMD_N

OUT

2

FERR-220-OHM

2

4

0402

108 55

SNS_T_DP4_DN5

1

2

4

0402

CRITICAL
518S0678

CRITICAL
MXM

Consider 3rd option - direct to SMC

518S0678

B

B

REMOTE THERMAL SENSORS (HEATSINKS AND ODD)

HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING
50 6

55 6

=PP3V3_S0_TSENS
1

22

1
1

PP3V3_S0_TSENS_R

2

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

5%
1/16W
MF-LF
402

108 55

C5501
1UF
10%
10V
X5R
402-1

SNS_T_DN1_DP6

J5550
53780-8602

2

1

108 55

SNS_T_DP1_DN6
SNS_T_DP2_DN3

1
2

3 DN1/DP6
2 DP1/DN6

SIGNAL_MODEL=EMPTY

1

4 DP2/DN3
5 DN2/DP3

0.0022UF
10%
50V
CERM 2
402
108 55
108 55

SNS_T_DN2_DP3
SNS_T_DP4_DN5

8 DP4/DN5
7 DN4/DP5

SMDATA 9
SMCLK 10

SIGNAL_MODEL=EMPTY

C5504

2

HDD_OOB_TEMP

108

R5553
200K
5%
1/16W
MF-LF
402

CRITICAL
518S0698

52
52

1

108 55

HDD_OOB_TEMP_R

3

R5551
1K

5%
1/16W
MF-LF
2 402

LM393
SOI-HF
108 SMC_HDD_OOB_TEMP

TO SMC
SMC_EXCARD_CP 49

MAKE_BASE=TRUE

GND
4

2

GND

Cannot pull low because some drives use this bit to
determine 1.5 Gbps vs. 3.0 Gbps SATA
Must pull high to 2.5V for compatibility with all drives

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

Thermal Sensors
DRAWING NUMBER

Apple Inc.

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SNS_T_DN4_DP5
DIFFERENTIAL_PAIR=SNS_T3

SIZE

D

REVISION

A.0.0

R

2

A

PAGE TITLE

1

0.0022UF
10%
50V
CERM
402

2

5%
1/16W
MF-LF
402

Drive active = valid signal protocol
Drive asleep = HDD drives HDD_OOB_TEMP low
Drive disconnected = pulled high

DIFFERENTIAL_PAIR=SNS_T2
DIFFERENTIAL_PAIR=SNS_T3

1

3.3K

U7030
1

R5550

0402

4

=SMB_REMOTE_TEMP_SDA
=SMB_REMOTE_TEMP_SCL

2

V+

1

U5500
TSSOP

DIFFERENTIAL_PAIR=SNS_T2

A

108 HDD_OOB_TEMP_FILT

2

VDD

DIFFERENTIAL_PAIR=SNS_T1

C5503

CRITICAL

12VS5_1V60_REF

L5552

1

EMC10472AIZL

10%
50V
CERM
402

8
70

M-RT-SM
3

6

C5502

5%
1/16W
MF-LF
2 402

FERR-220-OHM

0.0022UF

power/gnd and ref for this dual part
is on csa 70 with power sequencing
CRITICAL

R5554
62K

FROM DRIVE:
LOW: -0.3V TO 0.5V
HIGH: 2.0V TO 3.6V

SILK_PART=HDD TEMP

1

DIFFERENTIAL_PAIR=SNS_T1
SIGNAL_MODEL=EMPTY

108 55

=PP3V3_S0_SMC_LS

R5500

BRANCH

PAGE

55 OF 110
SHEET

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8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

FAN 0
CRITICAL
57 56 6

L5610

=PP12V_S0_FAN

220-OHM-1.4A
1

2

110 PP12V_S0_FAN0_L

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V

0603

=PP3V3_S0_FAN
1

R5602

1

R5606

R5603

1.5K

1.5K

5%
1/8W
MF-LF
805 2

5%
1/4W
MF-LF
2 1206

10K

5%
1/16W
MF-LF
2 402

MIN_NECK_WIDTH=0.25MM

1

3.9K2

F0_GATESLOWDN

Q5600

4

C5601

CRITICAL

J5600

2 16V
X7R
805

3

=PP3V3_S0_FAN

47K

NOTE:

2

CRITICAL

4

MMBD914XG

20%
2 16V
ELEC
6.3X5.5-SM1-HF

CRITICAL

L5600

1

FAN_TACH0

FAN_0_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1

R5620
0

FERR-220-OHM

5%
1/10W
MF-LF
2 603
518S0592
PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

2
0402

C

ADDED TO PROTECT SMC

FAN 1
57 56 6

57 56 6

CRITICAL

L5630

=PP12V_S0_FAN

220-OHM-1.4A
1

=PP3V3_S0_FAN

2

1

10K

1

R5610

5%
1/16W
MF-LF
2 402

R56071

1.5K

1.5K

5%
1/4W
MF-LF
2 1206

F1_VOLTAGE8R5
MIN_LINE_WIDTH=0.5MM

1

5%
1/8W
MF-LF
805 2

R5609
3.9K
1

2

B

F1_GATESLOWDN

G

C5609
0.01UF

20%
2 16V
CERM
402

HD FAN

1206A-03-HF

CRITICAL

L5640

220-OHM-1.4A

1
2
3

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

1

FAN_1_PWR

SOT23-HF1

S

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

M-RT-SM
5

2
0603

110 FAN_1_PWR_L

1

110 FAN_TACH1_L

2
3

57 56 6

2

=PP3V3_S0_FAN

3

CRITICAL

D5601

1

MMBD914XG

R5601
10K

1

1

4

C5605
100UF

SOT23

110

SMC_FAN_1_TACH

1

47K

R5630
0

5%
1/10W
MF-LF
2 603
518S0592
PLACEMENT_NOTE=PLACE R5630 CLOSE TO J5601 Pin3

FERR-220-OHM
1

FAN_TACH1

2

2
0402

5%
1/16W
MF-LF
402

A

FAN_1_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
1

CRITICAL

L5601

R5698

MOTOR CONTROL
TACH
GND
12V DC

6

20%
2 16V
ELEC
6.3X5.5-SM1-HF

5%
1/16W
MF-LF
2 402

49

B

J5601
53780-8604

CRITICAL

2N7002

1

1

C5603

10%
2 16V
X7R
805

Q5605

2.2UF

Q5603

4

0.47UF

D

C5628

10%
2 16V
X5R
603

NTHS5443T1H
1

3

1

2.2UF

5%
1/8W
MF-LF
805

MIN_NECK_WIDTH=0.25MM

SMC_FAN_1_CTL

C5608

10%
2 16V
X5R
603

CRITICAL
5

6
7
8

R5611

110 PP12V_S0_FAN1_L

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V

0603

49

MOTOR CONTROL
TACH
GND
12V DC

6
110

5%
1/16W
MF-LF
402

C

1

110 FAN_TACH0_L

100UF

5%
1/16W
MF-LF
2 402

2

110 FAN_0_PWR_L

C5602

1

SOT23

1

M-RT-SM
5

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

3

D5600

R5600
10K

R5699

2
0603

1

SMC_FAN_0_TACH

1

FAN_0_PWR

SOT23-HF1

1

49

L5620

220-OHM-1.4A

MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM

2

53780-8604

CRITICAL

2N7002

57 56 6

D
ODD FAN

0.47UF
10%

Q5602

S

0.01UF

1206A-03-HF

3

G

C5607

20%
2 16V
CERM
402

NTHS5443T1H

1

1

1

4.7UF

5%
1/8W
MF-LF
805

SMC_FAN_0_CTL
D

C5606

20%
2 16V
CERM
1206-1

R5605
F0_VOLTAGE8R5
MIN_LINE_WIDTH=0.5MM

49

1
CRITICAL
5

6
7
8

D

1

1
2
3

57 56 6

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

HD AND OD FAN
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

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4

3

2

1

FAN 2
CRITICAL
56 6

L5710

=PP12V_S0_FAN

220-OHM-1.4A
1

D

D

2
0603

57 56 6

=PP3V3_S0_FAN
1

R5705

1

1.5K

5%
1/16W
MF-LF
2 402
49

R57011

R5704

10K

1

1.5K

5%
1/4W
MF-LF
2 1206

5%
1/8W
MF-LF
805 2

SMC_FAN_2_CTL

C5708

1

4.7UF
20%

CRITICAL
5

C5709
0.01UF

20%
16V
2 CERM
402

2 16V
CERM
1206-1

R5703
F2_VOLTAGE8R5
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

1

3.9K 2
5%
1/8W
MF-LF
805

F2_GATESLOWDN

CPU FAN
1206A-03-HF

4

NTHS5443T1H

Q5700
1

CRITICAL

C5701

J5700

0.47UF

Q5702

L5720

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

2N7002

1

G

2
0603

=PP3V3_S0_FAN

1

1

FAN_2_PWR_L

110

MMBD914XG
SOT23

1

3

C5702

4

110 PP12V_S0_FAN2_L
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

100UF

20%
2 16V
ELEC
6.3X5.5-SM1-HF

VOLTAGE=12V

6
110

1

R5700
10K

CRITICAL

5%
1/16W
MF-LF
2 402

C

L5701

1

FAN_2_GND
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

R5720
0

1

FERR-220-OHM

FAN_TACH2

MOTOR CONTROL
TACH
GND
12V DC

2

110 FAN_TACH2_L

CRITICAL

3

D5700
57 56 6

1

FAN_2_PWR

SOT23-HF1

M-RT-SM
5

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

220-OHM-1.4A

S
2

53780-8604

CRITICAL

6
7
8

3
D

1
2
3

10%
16V
2 X7R
805

C

5%
1/10W
MF-LF
2 603
518S0592

2
0402

PLACEMENT_NOTE=PLACE R5720 CLOSE TO J5700 Pin3

R5797
49

SMC_FAN_2_TACH

1

47K

2

5%
1/16W
MF-LF
402

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

CPU FAN
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

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BRANCH

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1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

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D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

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D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

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BRANCH

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1

D

D

C

C
51 6

=PP3V3_S5_ROM

1

1

R6100

R6101

3.3K

R6150
103 51 21

IN

SPI_CLK_R

PLACEMENT_NOTE=PLACE CLOSE TO U6100
51

IN

SPI_MLB_CS_L

8

1

20%
10V
CERM
402

CRITICAL

1

R6191

VDD
U6100

0.1UF

5%
1/16W
MF-LF
2 402

2

10K
5%
1/16W
MF-LF
2 402

16MBIT

R6152

SOI

0
1

C6100

3.3K

5%
1/16W
MF-LF
402 2

2

103

6

SPI_CLK

5%
1/16W
MF-LF
402

SI

SCK

5

103

0

SPI_MOSI

1

SST25VF016B
1

1

R6190

SPI_WP_L
SPI_HOLD_L

3
7

10K

CE*
WP*
HOLD*

R6105

OMIT

SO

103 SPI_MISO_R

0
1

SPI_MOSI_R

SPI_MISO

2

IN

21 51 103

PLACEMENT_NOTE=PLACE CLOSE TO U6100

OUT

21 51 103

5%
1/16W
MF-LF
402

VSS

5%
1/16W
MF-LF
402 2

2

2
5%
1/16W
MF-LF
402

4

MCP79 SPI Frequency Select
Frequency

B

SPI_MOSI

SPI_CLK

31 MHz

0

0

42 MHz

0

1

25 MHz

1

0

1 MHz

1

1

B

NOTE: MCP79 only issues ’READ’ (0x03) commands
not ’READ_FAST’ (0x0B). Limits SPI bus
frequency and part selection.
SST25VF016B max speed for READ command is 25MHz.

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

SPI ROM
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

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2

1

AUDIO CODEC
APPLE P/N 353S2592
=PP5V_S0_AUDIO
6

C6203

1

=PP3V3_S0_AUDIO IN

C6258

1

4.7UF

0.47UF

20%
4V
X5R
402

PP4V5_AUDIO_ANALOG

10%
10V
2 X5R
402

2

C6259
C6260

D

C6261

1%
1/16W
MF-LF
2 402

OUT

68 65 64

OUT
IN

AUD_SENSE_A

IN

67

10UF

VBIAS_DAC

20%
2 6.3V
X5R
603

1

20%
6.3V
CERM
402-LF

2

2

2.2UF

2.2UF
20%
6.3V
CERM
402-LF

CS4206_FLYN

C

103 21

IN

HDA_BIT_CLK

103 21

IN

HDA_SYNC

103 21

OUT

HDA_SDIN0

IN

103 21

IN

9

IN

HDA_SDOUT
HDA_RST_L
AUD_SPDIF_IN_CODEC

22

2

AUD_SDI_R

5%
1/16W
MF-LF
402

103

OUT

AUD_SPDIF_OUT

1

2

13

SENSE_A

LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-

31
30
32
33

AUD_LO2_P_L
TP_AUD_LO2_N_L
AUD_LO2_P_R
TP_AUD_LO2_N_R

NC

MICBIAS

16

VCOM

28

LINEIN_L+
LINEIN_CLINEIN_R+

21
22

MICIN_L+
MICIN_LMICIN_R+
MICIN_R-

18
17
19
20

VREF+_ADC

27

3

VL_HD

1

VL_IF

BITCLK

RESET*

SPDIF_IN
SPDIF_OUT

1%
1/16W
MF-LF
402 2

=PP3V3_S0_AUDIO

MAKE_BASE=TRUE

1

CS4206_VREF_ADC

OUT

67

IN

63

AUD_LI_COM
AUD_LI_P_R IN

63

TP_AUD_DMIC_CLK

CRITICAL

63

IN

C

IN

68

IN

68

IN

67

IN

67

63

IN

NC

CRITICAL

C6211 1

1

10%
20V 2
TANT
CASE-P3-HF

20%
2 16V
POLY-TANT
CASE-B2-SM

C6263

NOSTUFF

10UF

1

R6267
100K

5%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

HP OUT ZOBEL NETWORK

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

GND_AUDIO_HP_AMP_L

2

62 63 66

R6299

B

63 62

IN

AUD_HP_PORT_L

63 62

IN

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

100K

C6298

C6297

1

0.1UF

AUD_GPIO_1

62

OUT

R6298
10K

5%
1/16W
MF-LF
2 402

L6201

VR6201
TPS71745

FERR-220-OHM
=PP5V_S0_AUDIO

1

R6201
2.21K2

=PP3V3_S0_AUDIO 1

2

4V5_REG_IN

6 IN

0402

SON

OUT

10%
16V
X7R-CERM 2
402

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

AUD_Z_R
AUD_Z_L

R62961

R62971

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

39

APPLE P/N 353S2456
4.5V POWER SUPPLY FOR CODEC
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V

1

0.1UF

10%
16V
X7R-CERM 2
402

DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

1

IN

65

NC

1

68 67 66 65 64 62 6

OUT

65

NC

AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R

VOLTAGE=0V

A

OUT

DGND THRM_PAD AGND

XW6201
SM

IN

64

AUD_LI_P_L

4

DMIC_SCL

62 63

NC

GND_AUDIO_CODEC

B

68 62 6

64

OUT

62 63

OUT

CS4206_VCOM

5%
1/16W
MF-LF
2 402

EDUCATION

OUT

OUT

100K

0

5%
1/16W
MF-LF
2 402

66

AUD_LI_N_R

SDI
SDO

R6263

BETTER

IN

SYNC

NOSTUFF

IN

AUD_HP_PORT_REF

23

1

68 67 66 65 64 62 6

AUD_HP_PORT_L
AUD_HP_PORT_R

AUD_CODEC_MICBIAS

1UF

68 67 65 64 63 62

65 67 68

AUD_LI_N_L

R62951

5%
1/16W
MF-LF
402

25

NC

14
15

47
48

AUD_SPDIF_CHIP

GND_AUDIO_HP_AMP_L 62 63 66
GND_AUDIO_CODEC 62 63 64

AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
TP_AUD_LO1_N_R

11

22

D

35
34
36
37

FLYP
FLYC
FLYN

6 62 64 65 66 67 68

62

20%
6.3V
2 X5R
603

LINEOUT_L1+
LINEOUT_L1LINEOUT_R1+
LINEOUT_R1-

8
5

R6257
103 66

6 62 68

10UF

10%
10V
X5R 2
402

GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
/SPDIF_OUT2
GPIO2
GPIO3

10
103

IN

MIN_NECK_WIDTH=0.1MM

U6201

7

103 21

1

VOLTAGE=4.5V
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.2MM

6

R6254

0.47UF

C6213

39

45
43
42

C6208

10%
10V 2
X5R
402

20%
2 16V
POLY-TANT
CASE-B2-SM

1

MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

2

1

2

10UF

1

MIN_LINE_WIDTH=0.30MM
MIN_LINE_WIDTH=0.30MM

44
41

CS4206_FLYP
CS4206_FLYC

10V
C6262 X5R
402-1

CRITICAL

C6265

38
40

12

C6206

1

1

VD VA_REF VA_HP VA
VBIAS_DAC
CRITICAL HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206ACNZC HPREF
QFN

29

CS4206_FP
CS4206_FN

46

C6205

26

68 64

AUD_MUX_CNTRL
AUD_GPIO_1
AUD_GPIO_2
AUD_GPIO_3

9
62

1

20%
6.3V 2
X5R
603

2.67K

K22 = NC
K23 LOW = S/PDIF IN, HIGH = DP SPDIF

1

10UF

R6255

24

C6204
1

49

IN

10%
10V 2
X5R
402

C6264
0.47UF

10%

1

0.47UF
9

66 63 62

20%
16V 2
POLY-TANT
CASE-B2-SM

GND_AUDIO_HP_AMP_L
PP4V5_AUDIO_ANALOG

1

1UF

1

10UF

62

IN

=PP1V5_S0_AUD_DIG

39

NC
NC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

GND_AUDIO_HP_AMP_L

62 63 66

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V
1

PP4V5_AUDIO_ANALOG

OUT

62

CRITICAL

4V5_REG_EN

4 EN

1%
1/16W
MF-LF
402

NR/FB 3

2

C6201
1UF

10%
2 10V
X5R
402-1

1

C6202

SYNC_MASTER=K22

C6266

1
1

0.1UF

1UF

10%
16V
X7R-CERM 2
402

10%
2 10V
X5R
402-1

SYNC_DATE=09/02/2009

A

PAGE TITLE

NC 5

GND
1

4V5_NR

AUDIO: CODEC/REGULATOR

C6207

DRAWING NUMBER

1UF

10%
10V
2 X5R
402-1

Apple Inc.

051-7863

NOTICE OF PROPRIETARY PROPERTY:

62 63 64 65 67 68

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

GND_AUDIO_CODEC

SIZE

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1

1ST ORDER DAC FILTER PLACEHOLDER
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

R6324

D

62

IN

AUD_HP_PORT_L

1

0

AUD_HP_L

2

5%
1/10W
MF-LF
603

OUT

D

66

NOSTUFF
CRITICAL

C6320

1

2200PF
5%
50V
C0G-CERM
603

66 62

IN

2

GND_AUDIO_HP_AMP_L
NOSTUFF
CRITICAL

C6321

1

2200PF
5%
50V
C0G-CERM
603

2

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

R6325
62

IN

AUD_HP_PORT_R

1

0

AUD_HP_R

2

OUT

66

5%
1/10W
MF-LF
603

C

C

CODEC Nom SE RIN = 20K OHMS
FC = 5 HZ Max
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
NET RIN = 18K OHMS
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
66

3.3UF

7.87K2

AUD_LI_L

IN

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

CRITICAL

C6300

R6300
AUD_LI_LF

1

1

1%
1/16W
MF-LF
402

AUD_LI_P_L

2

OUT

62

10%
10V
CERM-X5R
805-1

R63011

NOSTUFF
1

21.5K

1%
1/16W
MF-LF
402 2

C6301
820PF

10%
50V
2 CERM
402

CRITICAL

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

C6302
3.3UF

63 66

AUD_LI_GND

IN

1

AUD_LI_N_L

2

OUT

62

10%
10V
CERM-X5R
805-1

1

R6303
10

1%
1/16W
MF-LF
2 402

B
68 65 64 67 62

IN

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
66

IN

B

AUD_LI_R

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

CRITICAL

C6303

R6306

3.3UF

7.87K2

AUD_LI_RF

1

1

1%
1/16W
MF-LF
402

AUD_LI_P_R

2

R63051
21.5K
1%
1/16W
MF-LF
402 2

OUT

62

C6304
820PF

10%
50V
2 CERM
402

CRITICAL

IN

62

NOSTUFF
1

MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM

C6305

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
63 66

OUT

10%
10V
CERM-X5R
805-1

3.3UF

AUD_LI_GND

1

AUD_LI_N_R

2

10%
10V
CERM-X5R
805-1

A

SYNC_MASTER=SKIPAUDIO

SYNC_DATE=04/20/2009

A

PAGE TITLE

AUDIO: FILTER/BUFFER
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

63 OF 110
SHEET

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2

1

TWEETER SPEAKER AMPLIFIER
MAX9736B APN:353S2042
GAIN = -4.8(20K/17.4K)
CODEC OUT = 1.335VRMS
AMP VOUT = 7.355VRMS

TURN ON TIME: 110MS
TURN ON DELAY: 150MS
RIN = 17.4 OHMS
FC = 19.5 HZ
POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

D

D

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=12V
65 67

IN

PP12V_AUD_SPKRAMP_PLANE

C6499 1

C6401

220UF

65 64 67

IN

1

0.1UF

20%
16V 2
ELEC
SM-CASE-C1-HF

20%
16V
CERM 2
603

GND_AUDIO_SPKRAMP_PLANE
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

MAX9736_INT_1REG

C6402

1

1UF

10%
10V 2
X5R
402-1

NOSTUFF

C6403

C6412

0.47UF

AUD_LO1_P_L

1

L01_P_L

2

AUD_LO1_P_R

VS

1

1

17.4K2

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

L01_P_R

2

R6403

1

1

17.4K2

1%
1/16W
MF-LF
402

B

IN

=PP3V3_S0_AUDIO

68 67 66 65 64 62 6

IN

=PP3V3_S0_AUDIO

1

68 62

65 64 67

IN

IN

IN

68 65 63 67 62

AUD_GPIO_3

0

1

AUD_GPIO_2

GND_AUDIO_SPKRAMP_PLANE

1

TQFN
CRITICAL

BOOT

MOD
MONO
SHDN*
MUTE*
REGEN

22
21
3

AUDSAMPCPN1

AUD_BOOT1

OUTL1+
OUTL1-

31
1

OUTL2+
OUTL2-

32
2

OUTR1+
OUTR1-

25
23

OUTR2+
OUTR2-

26
24

NC1
NC2
NC3

7
8
17

C6405

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

CRITICAL

L6400

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

180-OHM-1.5A
1

CRITICAL

2

L6401

AUD_L_N1

1

0.5MM
0.2MM

2

1

1

5%
1/16W
MF-LF
2 402

0

5%
1/16W
MF-LF
402

2

R6406
100K

1

66

AUD_SPKR_OUTLO1L_NOUT

OUT

66

AUD_SPKR_OUTLO1R_POUT

OUT

66

AUD_SPKR_OUTLO1R_NOUT

OUT

66

180-OHM-1.5A

0.5MM
0.2MM CRITICAL 1

AUD_R_P1

2
0603-LF

CRITICAL

L6403

180-OHM-1.5A
AUD_R_N1

1

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

2
0603-LF

C6406
1

C6410

C6408

1UF

10%
2 25V
X7R
805

1

B

1000PF

1

5%
25V
NP0-C0G 2
402

1000PF

5%
25V
NP0-C0G 2
402

1

C6409
1000PF

1

C6407
1000PF

R6407

OUT

L6402

0603-LF

5%
25V
2 NP0-C0G
402

5%
2 25V
NP0-C0G
402

AUD_SPKRAMP_1MUTE_L
NOSTUFF

AUD_SPKR_OUTLO1L_POUT

0603-LF

180-OHM-1.5A

THM
AGND PGND PAD
13
14

10%
2 50V
X7R
603-1

AUD_L_P1

1UF

10%
2 10V
X5R
402-1

C6411
0.1UF

C1P
C1N

NOSTUFF

AUD_SPKRAMP_1SHDN_L

2

5%
1/16W
MF-LF
402

AUD_MAX9736_1INR
AUD_MAX9736_1FBR

18 INR
19 FBR

2

5%
1/16W
MF-LF
402

R6405
65 68 62

2

12 COM

20
4
10
9
11

1

0

AUD_MAX9736_1COM

0.001UF

R6404
1

5 FBL
6 INL

C6413
10%
50V
X7R
402

68 67 66 65 64 62 6

AUD_MAX9736_1FBL
AUD_MAX9736_1INL

20.0K2

1%
1/16W
MF-LF
402

10%
10V
X5R
402

AUDSAMPCPP1

MAX9736BETJ+
AUD_MAX9736_1VREG 15 REG

1%
1/16W
MF-LF
402

R6402

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

PVDD

U6400

20.0K2

1%
1/16W
MF-LF
402

0.47UF

IN

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

R6400

C6495
62

2

R6401

10%
10V
X5R
402

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1
10%
50V
X7R
402

C6496
IN

1UF

10%
10V
X5R 2
402-1

0.001UF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

33

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

62

C

GND_AUDIO_SPKRAMP_PLANE

27
30

IN

16

65 64 67

28
29

C

C6404
100PF

5%
50V
2 CERM
402

VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM

GND_AUDIO_CODEC

A

SYNC_MASTER=SKIPAUDIO

SYNC_DATE=04/20/2009

A

PAGE TITLE

AUDIO: Tweeter Amp 1
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

64 OF 110
SHEET

 OF 

8

7

6

5

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3

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1

8

7

6

5

4

3

2

1

WOOFER SPEAKER AMPLIFIER
MAX9736B APN:353S2042
TURN ON TIME: 110MS
GAIN = -4.8(20K/17.4K)
TURN ON DELAY: 150MS
CODEC OUT = 1.335VRMS
RIN = 17.4 OHMS
AMP VOUT = 7.355VRMS
FC = 19.5 HZ
POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

D

D

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=12V
64 67

IN

PP12V_AUD_SPKRAMP_PLANE

C6599 1

C6501

20%
16V
CERM 2
603

20%
16V 2
ELEC
SM-CASE-C1-HF

65 64 67

IN

1

0.1UF

220UF

GND_AUDIO_SPKRAMP_PLANE
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

C

C

MAX9736_INT_REG

C6502

1

1UF

10%
10V 2
X5R
402-1

GND_AUDIO_SPKRAMP_PLANE
NO STUFF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

0.47UF

AUD_LO2_P_L

1

2

L02_P_L

1

1

17.4K2

IN

AUD_LO2_P_R

AUD_MAX9736_VREG

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

2

R6503

1

1

17.4K2

L02_P_R

1%
1/16W
MF-LF
402

IN

AUD_MAX9736_COM

12 COM

AUD_MAX9736_INR
AUD_MAX9736_FBR

18 INR
19 FBR
20
4
10
9
11

0.001UF
2
10%
50V
X7R
402

68 67 66 65 64 62 6

5 FBL
6 INL

C6513
1

15 REG

AUD_MAX9736_FBL
AUD_MAX9736_INL

20.0K2

1%
1/16W
MF-LF
402

10%
10V
X5R
402

AUDSAMPCPP
1

TQFN

C1P
C1N

CRITICAL

BOOT

MOD
MONO
SHDN*
MUTE*
REGEN

NO STUFF

=PP3V3_S0_AUDIO

1

22
21
3

AUDSAMPCPN

31
1

OUTL2+
OUTL2-

32
2

OUTR1+
OUTR1-

25
23

OUTR2+
OUTR2-

26
24

NC1
NC2
NC3

7
8
17

1

2

AUD_SPKRAMP_SHDN_L

5%
1/16W
MF-LF
402
64 68 62

IN

1

R6506
100K

5%
1/16W
MF-LF
2 402
IN

68 64 63 67 62

CRITICAL

L6500

180-OHM-1.5A
1

CRITICAL

2

L6501

0

5%
1/16W
MF-LF
402

2

AUD_L_NOUT

1

0.5MM
0.2MM

2

OUT

66

AUD_SPKR_OUTLO2L_NOUT

OUT

66

AUD_SPKR_OUTLO2R_POUT

OUT

66

AUD_SPKR_OUTLO2R_NOUT

OUT

66

L6502

0603-LF

180-OHM-1.5A

0.5MM

AUD_R_POUT 0.2MM CRITICAL

1

2

B

0603-LF

CRITICAL

L6503

180-OHM-1.5A
AUD_R_NOUT

1

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

2
0603-LF

C6506
1

C6510

C6508

1

1UF

10%
25V
2 X7R
805

1

1000PF

1000PF

5%
25V
NP0-C0G 2
402

5%
25V
NP0-C0G 2
402
1

C6507
1000PF

1

C6509
1000PF

5%
25V
2 NP0-C0G
402

5%
25V
2 NP0-C0G
402

AUD_SPKRAMP_MUTE_L
1

AUD_SPKR_OUTLO2L_POUT

0603-LF

180-OHM-1.5A

R6505

AUD_GPIO_3
1

65 64 67

33

=PP3V3_S0_AUDIO

28
29

IN

13
14

68 67 66 65 64 62 6

0

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

AUD_L_POUT

1UF

THM
AGND PGND PAD

10%
2 50V
X7R
603-1

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

AUD_BOOT

OUTL1+
OUTL1-

C6505

10%
2 10V
X5R
402-1

R6504

C6511
0.1UF

MAX9736BETJ+

1%
1/16W
MF-LF
402

R6502

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

PVDD

U6500

20.0K2

1%
1/16W
MF-LF
402

0.47UF
62

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

VS

R6500

C6595

B

2

R6501

10%
10V
X5R
402

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

10%
10V
X5R 2
402-1

10%
50V
X7R
402

C6596
IN

1

1UF

0.001UF
1

62

C6503

C6512

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

27
30

IN

16

65 64 67

C6504
100PF

5%
50V
2 CERM
402

VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM

GND_AUDIO_SPKRAMP_PLANE

GND_AUDIO_CODEC

A

SYNC_MASTER=SKIPAUDIO

SYNC_DATE=04/20/2009

A

PAGE TITLE

AUDIO: Woofer Amp
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

65 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3
APPLE P/N 518S0748
APPLE P/N 518S0656

APPLE P/N 518S0677
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

L6600

67

OUT

AUD_MIC1_IN_N

1

2

1

AUD_MIC_IN1_N_EMI

2
0402

OUT

AUD_MIC1_IN_P

1

1

AUD_MIC_IN1_P_EMI

2

65

WOOFER (PRIMARY)

3

TWEETER (SECONDARY)

IN

64

IN

64
110 AUD_MIC_IN1_P_CONN

IN

65

IN

J6603

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

J6602

78048-0573
M-RT-SM

78048-0473
M-RT-SM

1

FERR-1000-OHM

2
0402

CRITICAL

CRITICAL

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

M-RT-SM
4

2

L6603

FERR-1000-OHM
67

110 AUD_MIC_IN1_N_CONN
VOLTAGE=0V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

GND_AUDIO_MIC1_CONN
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

L6602

PROPERTIES FOR ALL SPKR NETS

53780-8603

FERR-1000-OHM

0402

D

J6601

L6601

FERR-1000-OHM

PROPERTIES FOR ALL SPKR NETS

CRITICAL

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

1

SPEAKER CABLE CONNECTORS

INTERNAL MIC CON
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

2

AUD_SPKR_OUTLO2R_POUT
AUD_SPKR_OUTLO2R_NOUT
AUD_SPKR_OUTLO1R_POUT
AUD_SPKR_OUTLO1R_NOUT

65

WOOFER (PRIMARY)

1

65

2

NO_TEST

3

64

TWEETER (SECONDARY)

4

64

IN
IN

NC
IN
IN

AUD_SPKR_OUTLO2L_POUT
AUD_SPKR_OUTLO2L_NOUT
NC_J6702_3
AUD_SPKR_OUTLO1L_POUT
AUD_SPKR_OUTLO1L_NOUT

1
2

D

3
4
5

5

0402

CRITICAL

2

DZ6600

CRITICAL

2

DZ6601

6.8V-100PF

1

R6600

6.8V-100PF

402

0

402
1

5%
1/16W
MF-LF
2 402

1

R6601
103 9

OUT

AUD_SPDIF_IN

1

L6604
FERR-1000-OHM
68 67 65 64 62 6

IN

=PP3V3_S0_AUDIO

1

2
0402

22

2

5%
1/16W
MF-LF
402

REMOTE I/O CONNECTOR

L6605
FERR-1000-OHM

C

67

OUT

AUD_LI_TIP_DET

1

C

0402

R6610

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
63

OUT

AUD_LI_GND

63

OUT

OUT

AUD_LI_R

OUT

1

HS_MIC_HI

OUT

AUD_HP_PORT_REF

63 62

OUT

L6609

0402

FERR-1000-OHM
2

L6606

0402

FERR-1000-OHM
1

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

2
0402

XW6617
1

2

SM

R6617

GND_AUDIO_HP_AMP_L

1

0

IN

AUD_HP_L

63

IN

1

2

OUT

AUD_HP_R

1

2

L6614

AUD_HP_TYPE

67

OUT

AUD_HP_TIP_DET

B

0402

1

23
24

2

L6615
FERR-1000-OHM

AUD_IP_PERPH_DET
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM

FERR-1000-OHM
0402

OUT

VOLTAGE=3.3V

220-OHM-0.7A-0.28-OHM

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
67

MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM

L6618

0402

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
67

MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.2MM

L6616

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM

2

5%
1/10W
MF-LF
220-OHM-0.7A-0.28-OHM 603

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
63

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

AUD_SPDIFIN_JACK
PP3V3_AUDIO_SPDIF_JACK
AUD_LI_DET_JACK
AUD_LI_GND_JACK
AUD_LI_R_JACK
AUD_LI_GND_JACK
AUD_LI_L_JACK
HS_MIC_LO_JACK
HS_MIC_HI_JACK
AUD_HP_GND_JACK
AUD_HP_L_JACK
AUD_HP_GND_JACK
AUD_HP_R_JACK
AUD_HP_TYPEDET_JACK
AUD_IP_PERPH_JACK
AUD_HP_TIPDET_JACK
PP3V3_AUDIO_SPDIF_JACK
AUD_SPDIF_OUT_JACK

2

1

OUT

F-RT-SM
21

2

L6608

HS_MIC_LO

62

20143-020E-20F

0402

1

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
68

J6600

L6607
FERR-1000-OHM

FERR-1000-OHM

AUD_LI_L
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=0V

68

CRITICAL

2

5%
1/10W
MF-LF
603

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
63

0

1

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

B

APPLE P/N 518S0723

2

1

L6612

22

2
0402

FERR-1000-OHM
1

2

L6613

0402

FERR-1000-OHM
103 62

IN

AUD_SPDIF_OUT

1

2
2
0402

CRITICAL

2

DZ6603
402

DZ6604

2

CRITICAL
1

DZ6606

6.8V-100PF

6.8V-100PF

402

402

CRITICAL

2

DZ6607
6.8V-100PF

1

DZ6608

2

1

1UF

10%
10V 2
X5R
402-1

1

1

C6601

CRITICAL

2

DZ6611
6.8V-100PF

DZ6610

2 1

2

6.8V-100PF

6.8V-100PF

402

402

402

2 1

CRITICAL

DZ6615
6.8V-100PF

402

CRITICAL

DZ6612

6.8V-100PF

1

CRITICAL

DZ6613
6.8V-100PF

402

CRITICAL
1

1

C6600

2

402

CRITICAL
2

CRITICAL

DZ6609
6.8V-100PF

402

402

CRITICAL
1

2

CRITICAL

DZ6605
6.8V-100PF

6.8V-100PF

402

CRITICAL

DZ6614

2 1

6.8V-100PF
402
1

1

1

0.47UF

10%
2 10V
X5R
402

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Audio: MLB to I/O Conn.
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

66 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

Internal Microphone Impedance Matching
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

5%
1/16W
MF-LF
402

CRITICAL
1

R6793 C6751 1

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

C6795
0.1UF

66

IN

AUD_MIC1_IN_P

1

C6750

1
1

0.0082UF

10%
25V
X7R 2
402
66

IN

100K

5%
1/16W
MF-LF
2 402

1

62

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

6

IN

L6739

=PP12V_S0_AUDIO_SPKRAMP

1

1

R6792

OMIT

1

OUT

GND_AUDIO_CODEC

1

62 67 63 64 65 68

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

2

D

2

5%
1/16W
MF-LF
402

NOSTUFF
OUT

XW6704
SM

62

OMIT

1

GND_AUDIO_SPKRAMP_PLANE

OUT

R6748

64 65

2

0

1

2

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

AUD_MIC_INN_R

2

0

1

OMIT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

OUT

R6747

2

XW6703
SM

62 67 63 64 65 68

GND_AUDIO_CODEC

2

NOSTUFF

64 65

SM-1

AUD_MIC_INP_R

0.1UF

PP12V_AUD_SPKRAMP_PLANE

FERR-250-OHM
1

XW6705
SM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=12V

2
SM-1

2

C6796

AUD_MIC1_IN_N
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

IN

10%
16V
X5R
402

R6791

Audio Ground Returns

FERR-250-OHM

AUD_CODEC_MICBIAS

20%
6.3V 2
TANT
603-HF

1%
1/16W
MF-LF
2 402

1

L6738

4.7UF

3.40K

D

2.2K 2

2

Place Across Ground Split

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

R6743

AUD_INTMICBIAS

3

OUT

NOSTUFF

62

R6749

10%
16V
X5R
402

0

1

3.40K

1%
1/16W
MF-LF
2 402

XW6702
SM

AUD_MIC1_IN_G

1

2

2

5%
1/16W
MF-LF
402

GND_AUDIO_CODEC

62 67 63 64 65 68

IPHS HS Detect Debounce CKT
68 67 66 65 64 62 6

=PP3V3_S0_AUDIO
1

100K

100K

100K

5%
1/16W
MF-LF
2 402

C

R67681

R67981

R6797

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

R6799
AUD_IP_PERPH_DET_DB

1

0

2

AUD_IP_PERIPHERAL_DET

OUT

C

17

5%
1/16W
MF-LF
402

6

D

R6796
AUD_IP_PERPH_DET_INV

0

1

2

Q6701
AUD_IP_PERPH_DET_R

2

G

3

S

D

1

R6700
66

IN

Q6701

17.4K2

AUD_IP_PERPH_DET

AUD_IP_PER_DEB

1

1%
1/16W
MF-LF
402

5

G

C6740

67 62

68 67 66 65 64 62 6

IN

0.1UF

IN

67 62

=PP3V3_S0_AUDIO

CRITICAL
1

R6794

1

67 66 65 64 62 6
68

IN

=PP3V3_S0_AUDIO

5%
1/16W
MF-LF
2 402

IN

AUD_HP_TYPE

2

AUD_SENSE_A

68 67 66 65 64 62 6

IN

=PP3V3_S0_AUDIO

39.2K

NC

1

R6701

100K
AUD_Q6701_D6

10K

5%
1/16W
MF-LF
402 2

NC

1%
1/16W
MF-LF
2 402

6

3

NOSTUFF

D

D

R6732

G

Q6702

NTZD3154NT1H AUD_HP_TYPE_INV

B

R67301

1%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402 2

Q6700
66

IN

R6744

100K
AUD_Q6702_D3

67 62

1

R67951

0.1%
1/16W
MF
2 402

100K

LI Insert Detect

AUD_SENSE_A

IN

20K

R6790

4

Headphone Out

AUD_SENSE_A

0.1UF

GND_AUDIO_CODEC

Digital Out

B

C6797

10%
2 16V
X5R
402

S

10%
2 16V
X5R
402
68 65 64 63 67 62

NOSTUFF

1

NTZD3154NT1H
SOT-563-HF

1

NTZD3154NT1H
SOT-563-HF

5%
1/16W
MF-LF
402

5

G

66

IN

AUD_LI_TIP_DET

1

NTZD3154NT1H

SOT-563-HF

SOT-563-HF

S

S

1

4

0

2

AUD_LI_TIP_D

5%
1/16W
MF-LF
402

1

R6731
0

5%
1/16W
MF-LF
2 402

AUD_LI_TIP_DET_INV
68 67 66 65 64 62 6

IN

=PP3V3_S0_AUDIO
6

D

AUD_HP_TIP_DET_INV

Q6703

1

R6762

2

100K

A

5%
1/16W
MF-LF
2 402

IN

AUD_HP_TIP_DET

NTZD3154NT1H
SOT-563-HF

3

6

D

D

Q6700
66

G

5

G

DP Audio Enable

Q6702

NTZD3154NT1H

2

G

NTZD3154NT1H

SOT-563-HF

95

SOT-563-HF

S

S

4

1

IN

SYNC_MASTER=SKIPAUDIO

S

3

1

D
5

G

4

68 65 64 63 67 62

DRAWING NUMBER

NTZD3154NT1H

Apple Inc.

SOT-563-HF

GND_AUDIO_CODEC

051-7863

NOTICE OF PROPRIETARY PROPERTY:

SIZE

D

REVISION

A.0.0

R

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

GND_AUDIO_CODEC

A

AUDIO: Detects/Grounding
Q6703

MUX_CNTRL

S

68 65 64 63 67 62

SYNC_DATE=04/20/2009

PAGE TITLE

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PAGE

67 OF 110
SHEET

 OF 

8

7

6

5

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3

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8

7

FUNCTION

D

6

4

ENABLE/
CONVERTER VOLUME CNTRL TYPE

PIN

0X04
0X03
0X02
0X05
0X06
0X06
N/A
N/A
N/A

0X04
0X03
0X02
0X05
0X06
0X06
0X08
0X07
N/A

0X0B
0X0A
0X09
0X0C
0X0D(13,B,RIGHT)
0X0D (13,V22,B,LEFT)
0X10
0X0F
N/A

PRIMARY
SECONDARY
HEADPHONES
LINE INPUT
BUILT-IN MICROPHONE
HEADSET MICROPHONE
SPDIF OUT
SPDIF IN
MIKEY

5

3

2

1

DETECT/INTERRUPT

GPIO 3
GPIO 3
N/A
N/A
MICBIAS 80%
MIKEY
N/A
N/A
MCP GPIO_38

N/A
N/A
0X09 (A)
LINE IN
N/A
MIKEY
0X0C (B)
N/A
MCP GPIO_5

D

=PP5V_S0_AUDIO

1

IN

6 62

C6857
1UF

10%
2 10V
X5R
402-1

C

C

MIKEY RECEIVER CKT
WRITE: 0X72

READ: 0X73

67 66 65 64 62 6

IN

1

1

SOD-323-HF

1

R6806

2

10UF

47K

20%
2 6.3V
X5R
603

5%
1/16W
MF-LF
2 402

1

0

2

R6804
21

OUT

AUD_I2C_INT_L

0

IN

AUD_IPHS_SWITCH_EN1

0

6

HS_SDA

5
7

HS_RST

8
1

R6807
100K

R6805
19

HS_SCL

HS_INT_L

2

5%
1/16W
MF-LF
402

B

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

DRC

5%
1/16W
MF-LF
402

1

CRITICAL

AVDD

U6806
CD3275
MICBIAS

1

SDA

DETECT

2

INT*

BYPASS

10

SCL

HS_MIC_BIAS
HS_SW_DET
CRITICAL
1

HS_RX_BP

ENABLE
GND

1

THM

10%
25V
2 X7R
402

1

R6852
1K

5%
1/16W
MF-LF
402

68 67 65 64 63 62

C6854

20%
2 6.3V
TANT
603-HF

C6899
0.01UF

5%
1/16W
MF-LF
2 402

2

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

4.7UF

4

BI

=I2C_AUDIO_SDA

OUT

C6852

R6803
52

IN

AUD_GPIO_3

CRITICAL

NOSTUFF
1

5%
1/16W
MF-LF
402

D6800
1N4148WS-X-G

65 64 62

3

=I2C_AUDIO_SCL

NOSTUFF

2

11

IN

OUT

PP3V3_S0_HS_F

2

9

52

0

AUD_GPIO_2
1

0402

R6802

IN

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V

L6840

FERR-1000-OHM
=PP3V3_S0_AUDIO

64 62

APN 353S2256

5%
1/16W
MF-LF
2 402

B
GND_AUDIO_CODEC

1

R6809

62 63 64 65 67 68

2.2K

5%
1/16W
MF-LF
2 402

GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
66

IN

R6810

HS_MIC_HI

1

5%
1/16W
MF-LF
402

1

R6808
100K

IN

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

AUD_MIC_INF
1

C6801
0.1UF
1

C6853

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

10%
25V
2 X7R
402

HS_MIC_LO

2

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

AUD_MIC_INP_L

OUT

62

10%
16V
X5R
402

0.0082UF

5%
1/16W
MF-LF
2 402
66

2.2K 2

C6802
0.1UF
1

2

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

AUD_MIC_INN_L

OUT

62

10%
16V
X5R
402

FLP = 8.82 KHZ
FHP = 80 HZ

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

AUDIO: Mikey
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

68 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

S5 POWER RAIL SEQUENCING
12V_S5 SUPPLIED BY AC/DC MAX RAMP TIME < 50MS MAX RAMP RATE 10V/MS
12V_S5

STARTUP (BOOT OR WAKE) TIMING
3V3_S5 SWITCHER LOGIC POWERED BY INTERAL LDO, SOURCED FROM 12V_S5

BOOT UP

3V3_S5
1V05_S5 SWITCHER SOURCED FROM 3V3_S5 AND ENABLED FROM 3V3_S5_PGOOD
1V05_S5

D

D

SB: PM_SLP_S3_L
SB: PM_SLP_S4_L
VREGS: ALL_SYS_PWRGD
99 MS
SMC: IMVP_VR_ON

RMGT POWER RAIL SEQUENCING
IMVP: VR_PWRGOOD_DELAY
PM_SLP_RMGT_L FOLLOWS PM_SLP_S4_L TIMING CLOSELY
MCP: PM_SLP_RMGT_L
3V3_RMGT FET SOURCED FROM 3V3_S5, ENABLED BY PM_SLP_RMGT_L

AND GATE: MCP_PS_PGOOD
ALL_SYS_PWRGD * VR_PWRGOOD_DELAY

3V3_RMGT

1V05_RMGT

SMC STARTS
COUNT

1V05_RMGT FET SOURCED FROM 1V05_S5, ENABLED BY PM_SLP_RMGT_L

State

S3 POWER RAIL SEQUENCING

C

5V_S3 SWITCHER LOGIC POWERED BY INTERNAL LDO (EN BY SLP_S4_L)
OUTPUT SOURCED FROM 12V_S5 AND ENABLED BY PM_SLP_S4_L + LDO OUTPUT GOOD

5V3_S3

Manageability

SMC_PM_G2_ENABLE

PM_S4_STATE_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_M_L

N/A

1

1

1

1

1

Sleep (S3/M1)

On

1

1

0

1

1

Soft-Off (S5/M1)

On

1

0

0

1

1

Sleep (S3/M-Off)

Off

1

1

0

1

0

Soft-Off (S5/M-Off)

Off

1

0

0

0

0

Battery Off (G3Hot)

N/A

0

0

0

0

0

Run (S0/M0)

MCP: PM_SLP_S4_L

IMVP6 ON

C

3V3_S3 FET GATED BY PM_SLP_S4_L
3V3_S3

SHUT DOWN (SHUTDOWN OR SLEEP) TIMING

1V5_S3 SWITCHER LOGIC POWERED BY 5V_S3 SO ENABLED BY PGOOD_5V_S3
SOURCED BY 12V_S5; MUST RAMP IN < 2MS

1V5_S3

POWER RAILS ON DURING THIS TIME

SB SAYS
SUSPEND SOON

SLEEP OR SHUTDOWN

SB: PM_SUS_STAT#

NOTE: NO SEQUENCING REQUIREMENTS FOR THESE 3 RAILS

SB: PM_SLP_S3_L
SB: PM_SLP_S4_L

S0 POWER RAIL SEQUENCING
POWER RAILS SHUT DOWN
CPU VTT_PWRGD LOW

VREGS: ALL_SYS_PWR_GD

B

B

SB: PM_SLP_S3_L
12V_S0 SUPPLIED BY AC/DC, GATED BY PM_SLP_S3_L

SMC SAYS SHUTDOWN CPU
VREG IN RESPONSE TO
OS COMMANDS

12V_S0
5V_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT

SMC: IMVP_VR_ON

5V_S0
3V3_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT; SLOWER THAN 5V_S0
3V3_S0
1V8_S0 LDO SOURCED FROM 5V_S0, ENABLED BY 5V_S0 WITH RC DELAY

IMVP6: VR_PWRGOOD_DELAY

1V8_S0
1V5_S0 FET SOURCED FROM 1V5_S3, GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY
1V5_S0

MCP_VCORE

1V05_S0

MCP_VCORE REGULATOR INTERNAL LOGIC POWERED FROM 5V_S3, SOURCED FROM 12V_S5,
ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

MCP: CPUPWRGD

1V05_S0 REGULATOR SHARES INTERNAL LOGIC POWER WITH 3V3_S5 REG, SOURCED FROM 12V_S0
ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY
AND GATE: MCP_PS_PGOOD

CPU_VCORE

VTT_S0_DDR_LDO

CLK GEN DISABLED
CPU VCORE OFF
CPU_PWRGD DISABLED
SB PWROK DISABLE

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

POWER SEQUENCING BLOCK DIAGRAM
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

69 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

Power Control Signals

1

State

SMC_PM_G2_ENABLE (PORTABLES)

PM_SLP_S4_L

PM_SLP_S3_L

Run (S0)

1

1

1

Sleep (S3)

1

1

0

Soft-Off (S5)

1

0

0

Battery Off (G3Hot)

0

0

0

3.3V,5V S3 enable

R7050
21

PM_SLP_RMGT_L

IN

OUT

38

1

R7072
100K
5%
1/16W
MF-LF

R7051
(PM_S4_STATE_L)

PM_SLP_S4_L

IN

=PP5V_S3_PWRCTL

6

ENET_EN

2

NOSTUFF

FROM MCP (6)
102 21

0

1

33

1

2

2 402

PLACEMENT_NOTE=Place close to U1400

PGOOD_5V_S3

70

=DDRREG_EN OUT

MAKE_BASE=TRUE

D

75

Enable regulator

D

R7052

33

1

P3V3S3_EN

2

OUT

78

Enable FET

PLACEMENT_NOTE=Place close to U1400

70

IN

PGOOD_5V_S3

PM_EN_USB_PWR OUT

46

USB Port Switch

R7053

33

1

MXM POWER SEQUENCE

ENABLE REGULATOR

5VREG_EN

2

OUT

73

OUT

49 50

PLACEMENT_NOTE=Place close to U1400
85

R7054

33

1

IN

ALL_SYS_PWRGD_R

=PM_MXM_PGOOD_PULLUP

6 70

MAKE_BASE=TRUE

To SMC

PM_SLP_S4_SMC_L

2

PM_MXM_EN

OUT

85

PLACEMENT_NOTE=Place close to U1400

MXM CARD INPUT POWER ARE 12V_S0, 3V3_S0, 5V_S0
ALL_SYS_PWRGD ENABLES MXM REGULATORS
PM_MXM_PGOOD IS OPEN DRAIN SIGNAL, IT’S PULLED UP TO ALL_SYS_PWRGD

C7058

=PP3V3_S5_PWRCTL

70 6

0.1UF

2

1

1

R7040
10K

5 TC7SZ08AFEAPE

U7059
PM_SLPS3_BUF2_L

(PM_SLP_S3_L)

1

4

PM_SLP_S3_L_AND_S0_RDY

(PM_SLP_S3_L_BUF)

33

1

2

=P5VS0_EN

P5VS0_EN

3

From SMC (6)

R7080

2

39K

5%
1/16W
MF-LF
402
1

R7081

2

5%
1/16W
MF-LF
402

R7082

2

1

5%
1/16W
MF-LF
402
1

Enable FET

78

=PP3V3_S5_PWRCTL

5%
1/16W
MF-LF
402

1

R7031
1K

CPUVTTS0_EN

OUT

78

Enable FET

=MCPDDR_EN

OUT

78

Enable FET DELAY OF ~15MS FROM PM_SLP_S3_L

=PVTT_S0_EN

OUT

76

Enable regulator DELAY OF ~18MS FROM PM_SLP_S3_L

OUT

74

Enable regulator DELAY OF ~16MS FROM PM_SLP_S3_L

MAKE_BASE=TRUE

MCPCORES0_EN

=MCPCORES0_EN

MAKE_BASE=TRUE

1.5V_S3 NEED TO BE ON BEFORE S0 FET ON
12V_S0 NEED TO BE ON BEFORE MCP REG AND 1.05_S0 REG EN

79

C7080

C7081

1

0.47UF

10%
6.3V
CERM-X5R

2

10%
6.3V
CERM-X5R

1

C7082
0.47UF

2

RSMRST_PWRGD

1V05V_S0 DERIVES FROM 3.3V_S5

2

10%
2 16V
X5R
402

10%
6.3V
CERM-X5R

70 6

=PP3V3_S5_PWRCTL

S0 RAILS PGOOD

PGOOD Comparators

1

R7033
10K

1

1%
1/16W
MF-LF
402

R7018
84.5K
1%
1/16W
MF-LF
402

2

1%
1/16W
MF-LF

C7010

2

=PP3V3_S5_PWRCTL

20%
16V
CERM
603

70

IN

PGOOD_1V8_S0

78

IN

PGOOD_1V5_S0

1

78

R7014 1

1

10K

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

2

6

2

1

1%
1/16W
MF-LF
402

12VS5_9V00_REF
12VS0_COMP_REF

6

SOI-HF

2

2

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

7

PGOOD_12V_S0

5

OUT

6

=PPDDR_S3_PGCMP 1

2

1V5S3_PG_CMP

OMIT
SM
USING COMPARTOR INSTEAD OF REGULATOR
PGOOD OUTPUT BECAUSE IF 5V_S3 DOES
NOT COME UP, PPDDR REGULATOR HAS
NO INTERNAL POWER TO PULL PGOOD
LOW

12VS5_1V27_REF
1V5S3_COMP_REF

1.21K2
1

1

PGOOD_1V5_S3

3

1

1

4 ALL_SYS_PWRGD

B

70
76

49

OUT

33

2

ALL_SYS_PWRGD_R

OUT

6 70

5%
1/16W
MF-LF
402

MAKE_BASE=TRUE

4

I

(PULLUPS ARE NEAR LOADS)

0.1uF
1

MXM 1

R7022
100K
5%
1/16W
MF-LF
402

A

2

1

R7020
R7006

1%
1/16W
MF-LF
2 402

49.9K

CRITICAL
8

(1.67V/1.53V; 132MV HYSTERESIS)
55

12VS5_1V60_REF

6

IG

V+

1

2
SM

OMIT

1V8S0_PG_CMP

1

2.0K 2
1%
1/16W
MF-LF
402

2

1V8S0_COMP_REF

5

Rds(on)
7mOHM
18mOHM
35mOHM
70mOHM
65mOHM
115mOHM

13A
9.6A
8.8A
5.8A
3.7A
1.6A

Vgs +/8V
20V
25V
20V
12V
8V

20%
16V
CERM
603
5
85

LM393

IN

PM_MXM_PGOOD

1

IN

PM_PGOOD_PVCORE_CPU

2

MC74VHC1G08
SOT23-5-HF

U7056

SOI-HF
7

R7002
XW7002

U7030

2

1%
1/16W
MF-LF
402

2

20%
10V
CERM
402

C7025
0.1UF

1

64.9K

IRF7410
IRF7413
FDS4435
IRF7406
IRF6402
SI2302

C7056

=PP3V3_S5_PWRCTL

=PP12V_S0_VRD

=PP1V8_S0_PGCMP

ALL_SYS_PWRGD_SMC

R7099
1

PGOOD_1V05_S0

IN

2

3

2

S0_PWR_REG_PGOOD
OUT

33

5%
1/16W
MF-LF
402

GND

1

6

U7020 Y

PGOOD_MCPCORE_S0

IN

70 6
71 6

TC7SZ08AFEAPE
SOT665

A

MAKE_BASE=TRUE

2

1%
1/16W
MF-LF
402

2

B

R7098

70

(1.30V/1.22V; 80MV HYSTERESIS)

R7001

S0_PWR_CMP_PGOOD

1

10K

49.9K

74

XW7001

PLACE RESISTORS CLOSE TO U7020
R7030

R7008

49.9K

LM393
(9.91V/9.58V; 330MV HYSTERESIS)

1

R7007

U7010

1%
1/16W
MF-LF
402

20%
10V
CERM
402

=PP3V3_S0_PWRCTL
5

8

V+

4.99K2
12VS0_PG_CMP1

SM

PGOOD_5V_S0

2

R7000

OMIT

IN

R70191

100K

CRITICAL

XW7000

C7020
0.1UF

2

2

PLACE SHORTS CLOSE TO PLANE CUTS

6 70

2 402

0.1UF

1

33.2K

PP12V_S0

FROM THIS SMC GENERATES PM_RSMRST_L
WHICH GOES INTO PGOOD_SB OF MCP
DELAY IS ABOUT 200MS

402

=PP12V_S5_PWRCTL

R7013

6

To SMC (2)

C7083

1

B

49

OUT

C7031
0.1UF

0.47UF

10%
6.3V
CERM-X5R
402

402

402

HYSTERESIS NUMBERS CALCULATED BASED ON OUPTPUT PULL UP OF 3.3V

C

2

PGOOD_1V1_S5

1
1

0.47UF
2

5%
1/16W
MF-LF
402

=P3V3S0_EN

MAKE_BASE=TRUE

MCPDDR_EN
MAKE_BASE=TRUE

1

6 70

R7083

P3V3S0_EN

C

78 38 6

OUT

MAKE_BASE=TRUE

PLACEMENT_NOTE=Place close to U7059

B

2

IN

Y

2.2K

50 49 9 6

R7085

SOT665

A

1

2

MAKE_BASE=TRUE

10K

2

S0_RDY

20%
10V
CERM
402

5%
1/16W
MF-LF
402

43K

FROM COMPARATOR
70 PGOOD_1V5_S3
FROM COMPARATOR
70 PGOOD_12V_S0

PGOOD_1V8_S0

71 11

OUT

70

4

MCP_PS_PWRGD

SYNC_MASTER=K22
OUT

21

SYNC_DATE=09/02/2009

PGOOD and Power Sequencing

3

GND

DRAWING NUMBER

ALL_SYS_PWRGD IS ALSO AN INPUT TO THIS
AND GATE BY THE FACT THAT
PM_MXM_PGOOD IS PULLED UP TO IT

4
1

Apple Inc.

R7021

051-7863

NOTICE OF PROPRIETARY PROPERTY:

1%
1/16W
MF-LF

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2 402

SIZE

D

REVISION

A.0.0

R

10K

A

PAGE TITLE

BRANCH

PAGE

70 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

XW7120

R7127

SM

1

1K

2 VR_CPU_VSNS_VCC 1
VOLTAGE=1.1V

C7104

2

VR_CPU_FB_R

5%
1/16W
MF-LF
402

1

2

VR_CPU_COMP_R

2

=PP5V_S0_VRD

CPU_VCC_PKG_SENSE_P 1

VR_CPU_VSNS_R_P

2

10

1

5%
1/16W
MF-LF
402

D

R7101

R7134
2

NOSTUFF

1

R7129
IN

0.0022UF

SM

2

R7135

2 VR_CPU_VSNS_R_N

5%
1/16W
MF-LF
402

XW7130
1

0

1

1K

1

0.0022UF

1

C7103

1

0.0022UF

71

1.5K 2

0

20.0K

1%
1/16W
MF-LF
402 2

NOSTUFF

NOSTUFF

0

0

5%
1/16W
MF-LF
402

NOSTUFF

2

1

R7146

R7103

VR_CPU_VDIFF_R1

150

1

1M

2

R7145
VR_CPU_VDIFF_R2

1

0

1

RT7101
6.8K

R7106

C7130

0603

R7107

5%
1/16W
MF-LF
2 402

47.5 2

0.0022UF

100K

1

1%
1/16W
MF-LF
2 402

2

2

R7110
1

1K

2

1%
1/16W
MF-LF
402

AGND_CPU

PM_EN_PVCORE_CPU

IN

1

10K

C7110

6

CRITICAL

14 FB

U7100ISEN1+

70 11

OUT

VR_CPU_FS

34 FS

VR_CPU_SS

35 SS

VR_CPU_ISNS1_P

IN

72
108

VR_CPU_ISNS1_N

IN

72
108

10%
16V
2 X5R
402

VR_CPU_PWM2

OUT

VR_CPU_ISNS2_P

IN

72
108

VR_CPU_ISNS2_N

IN

72
108

VR_CPU_PWM3

OUT

72

1%
1/16W
MF-LF
2 402

PWM2 20

VR_CPU_PWM2_R

0

2

PWM3 31
29
108
ISEN3+
108 30
ISEN3-

2

1

NOSTUFF
1

0

383

1 VR_CPU_ISNS3_RR_P

1%
1/16W
MF-LF 402

C7152
15PF

2

R7143

R7123

5%
1/16W
MF-LF
402

VR_CPU_PWM3_R

0

2
1VR_CPU_ISNS2_RR_P 2
1
1%
5%
R7122
1/16W
1/16W 4.75K
MF-LF 402
MF-LF2
1
402
1%
1 C7116
1 C7117
1 C7118
1/16W
68PF
0.1UF
0.1UF MF-LF
402
5%
20%
10%
2 50V
2 16V
2 10V
X5R
CERM
CERM
402-1
402
402
SIGNAL_MODEL=EMPTY
AGND_CPU

R7166

1%

402

1

C7119
68PF

5%
2 50V
CERM
402-1

1

7
6
5
4
3
2
1
40

1

R7115
49.9K

1%
1/16W
MF-LF
2 402

D

1

C7120
0.1UF

10%
2 16V
X5R
402

0

2

1

VR_CPU_ISNS3_P

5%
1/16W R7124
MF-LF 4.75K
1
402 2
1%
1 C7121
1/16W
0.1UF MF-LF
402
20%
2 10V
CERM
402
SIGNAL_MODEL=EMPTY

VR_CPU_ISNS3_N

72

IN

72
108

IN

72
108

AGND_CPU

5%
1/16W
MF-LF
402

VR_CPU_ISNS3_R_P
VR_CPU_ISNS3_R_N

C
PWM4 25

VR_CPU_PWM4

ISEN4+ 23
ISEN4- 24

33 EN_VTT

PP5V_S0_CPU_VCORE_VCC

49.9K

402

72

R7139

12 REF

2.0K

R7114

1%

2 50V
C0G

39 TM

R7112

1

15PF

2 50V
C0G

28 VR_CPU_ISNS1_R_P
108
27 VR_CPU_ISNS1_R_N
108
ISEN1-

R7165

11 DAC

VR_CPU_DAC

1

PM_PGOOD_PVCORE_CPU

C7151

9 OFS

0.01UF

71

0.1UF

383

0

5%
1/16W
MF-LF
402 2

22 VR_CPU_ISNS2_R_P
108
ISEN2+
21 VR_CPU_ISNS2_R_N
108
ISEN2-

18 TCOMP

36 VR_RDY

5%
1/16W
MF-LF
402 2

0

5%
1/16W
MF-LF
402 2

26
SYM_VER_2 PWM1

15 VDIFF
17 VSEN
16 RGND

=PP3V3_S0_VRD

10%
2 16V
CERM
402

C7114

5%
1/16W R7120
MF-LF 4.75K
1
402 2
1%
1 C7115
1/16W
0.1UF MF-LF
402
20%
2 10V
CERM
402

R7121

NOSTUFF

13 COMP

VR_CPU_EN_VTT
1

0

VR_CPU_FB

VR_CPU_TM

2

5%
1/16W
MF-LF
402

OUT

SIGNAL_MODEL=EMPTY

5%
1/16W
MF-LF
402 2

VR_CPU_COMP

VR_CPU_REF

R7111
49

1

1

NOSTUFF

1

VR_CPU_VDIFF

10%
50V
CERM
402

LAYOUT: PLACE RT7101 NEAR HOT SPOT.

C

5%
50V
2 CERM
402-1

402

R71601 R71611 R71621

QFN

1%
1/16W
MF-LF
402

C7109

R7109

5%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

1%

C7113
68PF

2 50V
C0G

VCC

VR_CPU_TCOMP

1

75K

22.1K

1%
1/16W
MF-LF
2 402

20%
10V
2 CERM
402

R7108

1

100K

0.1UF

1

1

5%
1/8W
MF-LF
805

10%
2 10V
X5R
402
AGND_CPU

VR_CPU_OFS
1

1

15PF

NOSTUFF

5%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
402

1%
5%
5%
1/16W
1/16W
1/16W
MF-LF
MF-LF
MF-LF
402 2
402 2
2 402
VR_HOT goes HIGH when VTM/VCC < 28%
and LOW when VTM/VCC > 33%.

1

C7150

0

2

AGND_CPU

10%
50V
CERM
402

R71301 R71641

R7105

2

MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V

R7104 1 C7107
1UF

C7106
1

1

PP5V_S0_CPU_VCORE_VCC

2.2

1

2

470PF

1.02K

1

R7118

2

10%
50V
CERM
402

1%
1/16W
MF-LF
402

10%
2 50V
CERM
402

AGND_CPU

R71001

1

R7163
1

R7102

C7102

10%
2 50V
CERM
402

2

5%
1/16W
MF-LF
402
PP5V_S0_CPU_VCORE_VCC

NET_PHYSICAL_TYPE=POWER

71

10%
2 50V
CERM
402

VR_CPU_VSNS_MI

2

5%
1/16W
MF-LF
402

R7133

VR_CPU_VSNS_GND
VOLTAGE=0V

10

1

C7101

NOSTUFF

560PF

1VR_CPU_ISNS1_RR_P

1%
1/16W
MF-LF 402

6

C7105

VR_CPU_COMP_RC

1%
1/16W
MF-LF
402

SIGNAL_MODEL=EMPTY

5%
1/16W
MF-LF
402

1.25 mOhm loadline
CPU_VCC_PKG_SENSE_N 1

10.7K2

1

VR_CPU_VSNS_PL

19

IN

0

ISL6334

R7128

5%
50V
CERM
402

383

VR_CPU_PWM1

R7167

R7119

47PF

NET_PHYSICAL_TYPE=POWER

100 12

1

PPVCORE_S0_CPU

72 6

100 12

2

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

INPUT SENSE & FILTER
CRITICAL

CRITICAL

R7169
0.002

L7160

70 6

=PP12V_S0_VRD

1%
1/4W
MF
1206

1UH-20A-4.5MOHM
1

2
TH-VERT-HF

1
PP12V_S0_CPU_FLTRD_R
NET_PHYSICAL_TYPE=POWER 3

2
4

VOLTAGE=12V

PP12V_S0_CPU_FLTRD
NET_PHYSICAL_TYPE=POWER
1CRITICAL

8 PSI*

53

CPU_INPUT_ISENSE_P

53

CPU_INPUT_ISENSE_N

53 71 72

VOLTAGE=12V

C7160
270UF

20%
2 16V
ELEC
8X12-TH-HF

1

CRITICAL

C7161
270UF

20%
2 16V
ELEC
8X12-TH-HF

R7140
108 53

OUT

VR_CPU_IOUT

0

1

VR_CPU_IMON

2

5%
1/16W
MF-LF
402

VR_CPU_FAN
VR_CPU_VRDHOT

10 IMON
37 VR_FAN
38 VR_HOT

EN_PWR 32

VR_CPU_EN_PWR

THRM_PAD
1

R7117

VR_CPU_IOUT_PD

20.0K

XW7101

1%
1/16W
MF-LF
2 402

SM

1
1

AGND_CPU
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0V

10%
2 25V
CERM
402

R7116

1
1

R7132
1K

C7112
33NF

1

2

R7131

41

B

5%
1/16W
MF-LF
402 2

C7131 1

0.001UF

10K

PP12V_S0_CPU_FLTRD

53 71 72

B

2

5%
1/16W
MF-LF
402

10%
50V
CERM 2
402

0

5%
1/16W
MF-LF

2 402

55 50 10 6

=PPVTT_S0_CPU

CPU CORE

8

7

6

5

8

7

6

5

RP7190

RP7191

5%
1/16W
SM-LF

5%
1/16W
SM-LF

680

1
100 12

IN

CPU_VID<7..0>

2

3

4

K22/K23 65W
75A PEAK
70A AVE

680

1

2

3

4

7
6

A

5

SYNC_MASTER=K22

4

PAGE TITLE

SYNC_DATE=09/02/2009

2

DRAWING NUMBER

1

Apple Inc.

0

051-7863

IN

CPU_PSI_L

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

11

A

VREG: PPVCORE_S0_CPU

3

BRANCH

PAGE

71 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7
72 71 53

6

5

4

3

2

PP12V_S0_CPU_FLTRD

PP12V_S0_CPU_FLTRD
DIDT=TRUE

CRITICAL

5%
1/10W
MF-LF
603 2

5%
1/10W
MF-LF
2 603

5%
1/10W
MF-LF
603 2

VR_CPU_DRV1_VCC

10%
16V
603

NET_PHYSICAL_TYPE=POWER

R7206
2.2

5%
1/8W
MF-LF
2 805

5

R7207
0

5%
1/10W
MF-LF
2 603

CRITICAL

VR_CPU_DRV1_BOOT

BOOT 2

4 PWM

VR_CPU_DRV1_UGATE

1

UGATE
CRITICAL

1

WPAK

0.001UF

R7221

PHASE 2

10

5%
1/10W
MF-LF
2 603

0

5%
1/10W
MF-LF
603 2

C7221
10%
16V
603

5%
1/10W
MF-LF
2 603

C7223

1

R7226
2.2

5

5%
1/8W
MF-LF
2 805

CRITICAL

VR_CPU_DRV2_BOOT

Q7223

4

VR_CPU_PH2_SNUB

RJK0348DPA

402

PPVCORE_S0_CPU

6 71 72

2

0.001UF

CRITICAL

2

2

XW7221

XW7222

SM

SM

1
SIGNAL_MODEL=EMPTY

NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
1 C7228

WPAK

1
SIGNAL_MODEL=EMPTY

VR_CPU_ISNS2_P

OUT

71 108

VR_CPU_ISNS2_N

OUT

71 108

10%
50V
2 CERM
402

1 2 3

PAD

TABLE_5_HEAD

11

5

20%

2 16V
CERM

4

0.22UF

10%
2 16V
X7R
603

5

1

0

3

R7224

THRML

GND

VR_CPU_PWM2

0.01UF

20%
2 16V
CERM
402

MMD10EE-SM

2

1

5%
1/10W
MF-LF
603 2

BOOT 2

C7231

1

0.01UF

L7221

DIDT=TRUE
OMIT
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
VR_CPU_DRV2_UGATE
UGATE 1
CRITICAL
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
PHASE 10 108 VR_CPU_SW2
NET_PHYSICAL_TYPE=POWER
4 PWM
VR_CPU_DRV2_LGATE DIDT=TRUE
LGATE 6
NET_PHYSICAL_TYPE=POWER
3 GDSEL

0

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

353S1733

2

IC,ISL6612,SYNC,FETDRV,DFN10,LF

U7221,U7241

CRITICAL

PP12V_S0_CPU_FLTRD

PP12V_S0_CPU_FLTRD

CRITICAL
1

5 CRITICAL

R72421

R7241

R72451

10

5%
1/10W
MF-LF
603 2

5%
1/10W
MF-LF
2 603

0

5%
1/10W
MF-LF
603 2

VR_CPU_DRV3_VCC

C7247
1UF

NET_PHYSICAL_TYPE=POWER
NOSTUFF

C7241
10%
16V
603

C7243
2.2

5%
1/8W
MF-LF
2 805

5

CRITICAL

DIDT=TRUE
OMIT
NET_PHYSICAL_TYPE=POWER
VR_CPU_DRV3_UGATE DIDT=TRUE
UGATE 1
CRITICAL
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
PHASE 10 108 VR_CPU_SW3
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
4 PWM
6
VR_CPU_DRV3_LGATE
LGATE
NET_PHYSICAL_TYPE=POWER

1

R7247
0

5%
1/10W
MF-LF
2 603

VR_CPU_DRV3_BOOT

VR_CPU_PH3_SNUB

Q7243

4

2

WPAK

0.001UF

CRITICAL

6 71 72

2

XW7241

XW7242

1

1

SM

NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
1 C7248

RJK0348DPA

SM

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

VR_CPU_ISNS3_P

OUT

71 108

VR_CPU_ISNS3_N

OUT

71 108

10%
2 50V
CERM
402

THRML

5

GND

VR_CPU_PWM3

PPVCORE_S0_CPU
2

1 2 3

PAD
11

NOSTUFF

20%
16V
402

4

R7246

5

1

3

0.22UF

10%
16V
2 X7R
603

DFN
BOOT 2

0.01UF

MMD10EE-SM

2

0

5%
1/10W
MF-LF
603 2

1

TLM833

8

R72441

ISL6622
3 GDSEL

B

C7251

2 CERM

0.36UH

1 2 3
1

U7241

VR_CPU_DRV3_GDSEL

20%
16V
2 CERM
402

L7241

NET_PHYSICAL_TYPE=POWER

VCC UVCC LVCC

603

1

0.01UF

VR_CPU_BOOT3_RC

D7240

10%

7

C7240

16V
2 X5R

C7250

RJK0353DPA

2 X5R

1UF

1

THESE TWO CAPS ARE FOR EMC
1

1UF
9

1

1

10%
10%
16V
2 16V
X5R-CERM2 X5R
0805
603

WPAK

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV3_UVCC

1UF

Q7241

4

C7249
10UF

10%
2 16V
X5R-CERM
0805

53 71 72

CRITICAL
1

C7246
10UF

20%
2 16V
ELEC
8X12-TH-HF

VR_CPU_DRV3_PVCC

NET_PHYSICAL_TYPE=POWER
1

1

270UF

PHASE 3

10

CRITICAL

C7245

1

NOSTUFF

CTLSH3-30M833

B

1

72 71 53

IN

C7230

1

0.36UH

DFN

R7227

71

1UF

1

1

U7221

1

10%
16V 2
X5R
603

C7227

1 2 3

TLM833

VCC UVCC LVCC

NOSTUFF

C7242

1

10%
10%
16V
2 16V
X5R-CERM 2 X5R
603
0805

C

D7220

10%

603

VR_CPU_DRV2_GDSEL

IN

C7229
10UF

10%
2 16V
X5R-CERM
0805

CTLSH3-30M833

7

9

8

1UF

53 71 72

RJK0353DPA

NET_PHYSICAL_TYPE=POWER

ISL6622

71

20%
2 16V
ELEC
8X12-TH-HF

Q7221

4

10UF

VR_CPU_BOOT2_RC

1UF

2 X5R

16V
2 X5R

71 108

THESE TWO CAPS ARE FOR EMC
1

C7220

OUT

CRITICAL
1

C7226

NET_PHYSICAL_TYPE=POWER

NET_PHYSICAL_TYPE=POWER
NOSTUFF
1

VR_CPU_ISNS1_N

WPAK

VR_CPU_DRV2_UVCC

1

10%
16V 2
X5R
603

1

VR_CPU_DRV2_PVCC

NET_PHYSICAL_TYPE=POWER

1UF

CRITICAL

C7225
270UF

1

R72251

VR_CPU_DRV2_VCC

71 108

11

5

CRITICAL
1

5 CRITICAL

5%
1/10W
MF-LF
603 2

OUT

PP12V_S0_CPU_FLTRD

NOSTUFF

10

VR_CPU_ISNS1_P

1 2 3

PP12V_S0_CPU_FLTRD

R72221

C7222

XW7202

SM
SIGNAL_MODEL=EMPTY
1

10%
2 50V
CERM
402

PAD

VR_CPU_PWM1

C

2

XW7201

SM
SIGNAL_MODEL=EMPTY
1

NET_PHYSICAL_TYPE=VR_CTL_PHY
DIDT=TRUE
1 C7208

RJK0348DPA

THRML

GND

VR_CPU_PH1_SNUB

Q7203

4

CRITICAL

2
5

1

DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
PHASE 10 108 VR_CPU_SW1
NET_PHYSICAL_TYPE=POWER
DIDT=TRUE
VR_CPU_DRV1_LGATE
LGATE 6
NET_PHYSICAL_TYPE=POWER

3 GDSEL

NOSTUFF

72 71 53

0.22UF

DFN

VR_CPU_DRV1_GDSEL

IN

C7203

10%
2 16V
X7R
603

4

ISL6622

71

1

0

5%
1/10W
MF-LF
603 2

3

R7204

A

1

critical

C7295
22UF

OUTPUT CAPS

PPVCORE_S0_CPU

20%
2 6.3V
CERM-X5R
805-3

6 71 72

1

critical

C7296
22UF

1

critical

C7297
22UF

20%
20%
6.3V
2 6.3V
CERM-X5R 2 CERM-X5R
805-3
805-3

1

critical

C7298
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7299
22UF

20%
2 6.3V
CERM-X5R
805-3

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

C7260

1

330UF

critical

C7261

1

330UF

critical

C7262

1

330UF

critical

C7263

1

VREG: PPVCORE_S0_CPU
DRAWING NUMBER

330UF

critical

C7264

1

330UF

critical

C7265

1

330UF

20%
2.5V 2
POLY-TANT

20%
2.5V 2
POLY-TANT

20%
2.5V 2
POLY-TANT

20%
2.5V 2
POLY-TANT

20%
2.5V 2
POLY-TANT

20%
2.5V 2
POLY-TANT

CASE-D2E-SM

CASE-D2E-SM

CASE-D2E-SM

CASE-D2E-SM

CASE-D2E-SM

CASE-D2E-SM

1

critical

C7280
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7281
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7282
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7283
22UF

20%
2 6.3V
CERM-X5R
805-3

critical
1 C7284

22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7285
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7286
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7287
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7288
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7289
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7290
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7291
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7292
22UF

20%
2 6.3V
CERM-X5R
805-3

1

critical

C7293
22UF

1

critical

051-7863

22UF

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

C7294

20%
20%
6.3V
2 6.3V
CERM-X5R 2 CERM-X5R
805-3
805-3

A

PAGE TITLE

Apple Inc.
critical

D

6 71 72

2
MMD10EE-SM

2

U7201

1

TLM833

VCC UVCC LVCC

603

20%
16V
402

2 CERM

PPVCORE_S0_CPU

1

1

10%

0.01UF

20%
16V
2 CERM
402

0.36UH

1 2 3

D7200

7

9

1UF

C7211

1

0.01UF

L7201

VR_CPU_BOOT1_RC

1UF

2 16V
X5R

C7210

RJK0353DPA

2 X5R

C7200

1

10%
2 16V
X5R
603

THESE TWO CAPS ARE FOR EMC

C7201

1

8

1

C7207
1UF

10%
2 16V
X5R-CERM
0805

WPAK

NET_PHYSICAL_TYPE=POWER

10%
16V 2
X5R
603

1

C7215
10UF

10%
2 16V
X5R-CERM
0805

CTLSH3-30M833

1UF

Q7201

4

10UF

20%
2 16V
ELEC
8X12-TH-HF

53 71 72

CRITICAL
1

C7206

NET_PHYSICAL_TYPE=POWER

VR_CPU_DRV1_UVCC

1

1

VR_CPU_DRV1_PVCC

NET_PHYSICAL_TYPE=POWER

D

PHASE 1

10

0

CRITICAL

C7205
270UF

R7201

R72051

10

1

5 CRITICAL

1 NOSTUFF

R72021

C7202

1

BRANCH

PAGE

72 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

=PPVIN_S5_P5VS3
DIDT=TRUE

5V S3 REGULATOR

2

1

6 73

CRITICAL
1

C7342 C7300
270UF

1

C7332

10UF

10%
16V
ELEC
2
8X12-TH-HF X5R-CERM
0805

D

1

C7335

10UF

20%

1

10UF

10%
16V
X5R-CERM 2
0805

2 16V

10%
16V
X5R-CERM
0805

2

D

=PPVIN_S5_P5VS3
6 73

C7345

EMC: C7353,C7354
PLACE AT Q7330

1

2.2UF
10%
16V
X5R 2
603

C7354

1

C7353

0.1UF

1

0.1UF

10%
25V
X5R
402

10%
25V
X5R
402

2

1

2

1

B0530WXG
11

4

5VS3_TG
CRITICAL

1

100K

0.1UF
10%
16V
X5R 2
402

C

R7301
5%
1/16W
MF-LF
402

C7316

1

0.001UF
2

C7303
10%
16V
CERM
402

TK/SS

3

5VS3_ITH

IN

ITH

SENSE+ 6
SENSE- 5

LTCMODE 15 MODE/PLLIN

C7315

10%
50V
2 CERM
402

2

SWITCHNODE

MIN_LINE_WIDTH=0.25MM

PLACE XW CLOSE 1
TO L7320 OMIT
1

1

5%
50V
CERM
402

4
2

5VS3_SENSEN

R7304
0 1
2

C7307
100PF

S

Q7335

5%
1/16W
MF-LF
402

D7300

CTLSH3-30M833

1 2 3

MLP5X6-LFPAK-Q5A

R7362
1

5%
1/10W
MF-LF
2 603

5%
50V
2 CERM
402

2

R7336

3
2
4

C7302

(5VS3_VOUT)

1%
1/16W
MF-LF
402 2

20%
6.3V 2
POLY-TANT
CASE-D3L-SM

C7301
10UF

1

43.2K

1

330UF

1

RA

R7305

5

1.5K
1%
1/16W
MF-LF
402

CRITICAL

1
1

5V_SNUBBER
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.4MM
1

C

OMIT

5VS3_SENSE

DIDT=TRUE

CSD58856Q5A

6 110

XW7301
SM

TLM833

1

CRITICAL

PP5V_S3_REG
PLACE XW CLOSE
TO L7320 2

CRITICAL

XW7300

C7363
1000PF

5%
50V
2 C0G-CERM
603

G

1
SM

5

100PF

17

8
5VS3_ITH_R

C7306
0.001UF

L7320

1

D

FB 4

1

1 5V_BOOT1_R 2

PEAK=3.31A
AVE=3.19A

10%
25V 2
X5R
402

2.2UH-10A-11.6M-OHM

0.1UF

5% MIN_NECK_WIDTH=0.2 MM
10%
1/10W
25V
MF-LF
X5R
603
402

DIDT=TRUE
5VS3_SENSEP

THRM
GND PAD

1

2

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

2
73

5V_BOOT1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

1

1

0.1UF

10%
25V
X5R 2
402

CRITICAL

C7326

R7324

BG 9 5VS3_BG

1

0.01UF

10%
50V
CERM 2
402

2

1 2 3

DIDT=TRUE

C7304

1

0.1UF

SM

1

C7331

ILIM
FREQ/PLLFLTR
RUN

C7356

5VS3_SW
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

TG 13
SW 14
BOOST 12

5V_S3
K22/K23
POWER BUDGET

MLP5X6-LFPAK-Q5A

S
108

QFN

OSCILLATED AT APPR. 330KHZ

EMC: C7304,C7356
PLACE AT L7320.1

CSD58856Q5A

DIDT=TRUE

U7300
LTC3851EUD
7
16
1

Q7330

G

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

INTVCC VIN

LTCINTVCC
73
5VS3_FREQ
5VREG_EN
5VS3_TK_SS
SOFT START TIME 8MS

CRITICAL

D

2

SOD-123-HF

2

10

10%
35V
X5R-CERM
0805

5

D7301

4.7UF

2

C7334

C7309

20%

1

2 6.3V
CERM

100PF

1

C7322
10UF
20%

2 6.3V
CERM

CRITICAL

805-1

5%
50V
CERM 2
402

1

805-1

C7305
330UF

20%
2 6.3V
POLY-TANT
CASE-D3L-SM

1

RB

R7302
24.9K

R73061

1%
1/16W
MF-LF
2 402

8.06K

C7317

1

R73071
1.24K

2

1%
1/16W
MF-LF
402 2

0.22UF
10%
10V
CERM
402

5VS3_FB
1

1%
1/16W
MF-LF
402

2

C7325
20PF

5%
2 50V
CERM
402

5VS3_SENSEN_R

(5VS3_FB)

B

B

LTCINTVCC

73

1

R7311
100K

5%
1/16W
MF-LF
2 402

STATE

PM_SLP3_BUF1_L 5VREG_PS_L

LTCMODE

Mode

5VREG_PS_L

Q7303
SI2301BDS

2

SM-HF

CRITICAL
1

S

S0

1

0

1

CONT MODE

S3

0

1

0

BURST MODE

D

R7310
94 9

PM_SLPS3_BUF1_L

2

10K

1

3

PM_SLPS3_BUF1_R_L

R7312

5%
1/16W
MF-LF
2 402

3

Q7360

1

MMBT3904G
SOT23

5%
1/16W
MF-LF
402

A

1

100K

G

2

SYNC_MASTER=K22
LTCMODE

SYNC_DATE=09/02/2009

A

PAGE TITLE

73

5V_S3 REGULATOR
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

73 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

MCP CORE

D

D

=PPVIN_S0_MCPCORE

6

DIDT=TRUE

=PP5V_S3_MCPREG

6

=PP3V3_S3_MCPREG

MCP_ISL9563A
R7490
21

21

IN

IN

IN

R7461

5%
1/16W
MF-LF
2 402

MCP_VID<0>

1

2

MCP_VID<1>

R7491
1

MCP_VID<2>

1

VDD

PVCC

2 SOFT

2
5%
1/16W
MF-LF
402

2

108 54

70

5%
1/16W
MF-LF
402

31
24
25
26
27
23

OUT PGOOD_MCPCORE_S0

MCP_VID0_R
MCP_VID1_R
MCP_VID2_R
MCP_VID3
MCP_ISL6263D_OFFSET0
=MCPCORES0_EN
70
IN
MCPCORES0_FDE

1MCP_ISL6263D

R7484
20.0K

1%
1/16W
MF-LF
2 402

C

28 IMON

MCPCORES0_IMON

29
30
32
8
9

MCPCORES0_VSEN
MCPCORES0_RTN

1

R7483
20.0K

1%
1/16W
MF-LF
402 2

PGOOD
VID0
VID1
VID2
VID3

2

402

VIN 14

R7474
0 2

UGATE 18 MCPCORES0_UGATE

1

PHASE 19
108

0.2 MM
0.25 MM

0.25 MM
0.2 MM

MCPCORES0_PHASE

2

PLACE XW NEAR THE MCP,
CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
OF MCP

2

MCPCORES0_RSEN_H

1

LGATE 21 MCPCORES0_LGATE

OMIT

XW7463
SM
1

2

MCPCORES0_RSEN_L

1

2

1%
1/16W
MF-LF
402

OMIT

1

0.1UF
10%
25V
402

DIDT=TRUE

CRITICAL
C7466
10UF

1

20%
4V
X5R
603

R7462
0.499

1%
1/10W
MF
2 603

1

CASE-D2E-SM

SM

MCPCORES0_SNUBBER
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.4MM
1

DIDT=TRUE

C7468
330UF

20%
2 2.5V
POLY-TANT

2 X5R

XW7460

MLP5X6-LFPAK-Q5

S

OCSET 3

1

1

2

20%
2 2.5V
POLY-TANT

C7484 1
10UF

C7465
330UF

20%
4V
X5R 2
603

CASE-D2E-SM

C7483 1
10UF
20%
4V
X5R
603

2

C7469
0.0027UF
10%
50V
CERM
402

C

2

MCPCORES0_ISP_R
(=PPMCPCORE_S0_REG)

R7464
11.3K

ISP 13 MCPCORES0_ISP
ISN 11 MCPCORES0_ISN

1

1

10%
16V
X7R-CERM 2
402

(MCPCORES0_VSEN)

15

(MCPCORES0_VO)

1

1%
1/16W
MF-LF
2 402

R7472
150K

R7470
10K

C7473
0.12UF

1%
1/16W
MF-LF
2 402

10%
2 10.0V
CERM-X5R
402

R7473
10K

XW7461
2

(MCPCORES0_ISP)
(MCPCORES0_ISN)

GND_MCPCORES0_AGND
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM

10%
2 50V
X7R
402

2 MCPCORES0_ISN_R

R7467
1K

10KOHM-5%

1%
1/16W
MF-LF
2 402

CRITICAL

1

1%
1/16W
MF-LF
2 402

1

C7470
0.001UF

XW7402
SM
1

1

R7469
10K

THRM_PAD
33

VSS

OMIT

1
1

PGND

2

1%
R7465
1/16W 0603-LF
MF-LF
2 402

MCPCORES0_OCSET

OMIT

1%
1/16W
MF-LF
2 402

1

1

C7477
0.1UF

10%
2 25V
X5R
402

C7478
0.1UF

10%
2 25V
X5R
402

1

R7475
59.0K

(MCPCORES0_RTN)

1%
1/16W
MF-LF
2 402

1

R7471
100

B

CRITICAL
1 C7467

C7463
0.0022UF 2OMIT

10%
50V
2 CERM
402

1 2 3

1

C7476
0.1UF

1%
1/16W
MF-LF
2 402

1

R7468
20

F = 200-300 KHZ

2
MMD12EZ-SM

CSD58857Q5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

402

L7460

Q7465

G

MAX CURRENT: 20A

2 X5R

CRITICAL

CRITICAL

D
(MCPCORES0_LGATE) 4

SM

1%
1/16W
MF-LF
402

6 54 74

Vout = See below

1.0UH-29A-2.5MOHM

1

OMIT

20

PPMCPCORE_S0_REG

R7463
100

1

PPMCPCORE_S0_REG

10%
25V

(MCPCORES0_PHASE)
SWITCHNODE
5

CRITICAL

7 VDIFF

1

PPMCPCORE_S0_REG

10%
25V
X5R
805

0.1UF
1 2 3

X7R
16V
603
10%

DIDT=TRUE

DIDT=TRUE

VR_ON
AF_EN
FDE
VSEN
RTN

S

C7464

ICOMP 10 MCPCORES0_ICOMP

74 54 6

C7475
10UF

1 C7457

0.22UF
1

MCPCORES0_BOOT_R

5%
1/10W
MF-LF
603

BOOT 17 MCPCORES0_BOOT

6 FB

MCPCORES0_FB

R7466
20
1
2

2

DIDT=TRUE

5 COMP

MCPCORES0_VDIFF

SM

10%
25V
X5R
805

1

MCPCORES0_COMP

XW7462

C7474
10UF

EMC: C7467,C7457
PLACE AT L7460

CSD58856Q5A

VO 12 MCPCORES0_VO

74 54 6

805

Q7460

G

4 VW

MCPCORES0_VW

2

MLP5X6-LFPAK-Q5A

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE

NC

10%
25V

CRITICAL

D
4

(MCPCORES0_UGATE)

C7460

2 X5R

1

5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

QFN

1 RBIAS

MCPCORES0_SOFT

0

0

C7462
1UF

10%
25V
X5R
402

10%
16V
2 X5R
402

U7401
MCPCORES0_RBIAS

5%
1/16W
MF-LF
402

0.1UF

2 X5R

1

10UF

20%
16V 2
ELEC
8X12-TH-HF

1 C7472

0.1UF
1

1K

0

R7492
21

1

1%
1/16W
MF-LF
2 402

1

10%
16V
X5R 2
402

ISL9563A

R7485
20.0K

1 C7455
10%
25V

22

C7461
1UF

1MCP_ISL6263D

EMC:
PLACE AT Q7460

VOLTAGE=5V
0.6 mm
0.2 MM

1

1

C7471
270UF

2 5V_S3_MCPREG_VIN

5%
1/10W
MF-LF
603

16

6

1

CRITICAL

R7460
2.2

B

(MCPCORES0_ICOMP)

1%
1/16W
MF-LF
2 402

(MCPCORES0_VW)

C7479

1

1

10%
50V 2
X7R
402

2

5%
50V
CERM
402-1

R7477
133K

2

1

R7476
6.98K

1%
1/16W
MF-LF
2 402

C7481
560PF

MCPCORES0_COMP_C

1

10%
50V
CERM
402

1

1%
1/16W
MF-LF
402

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION
TABLE_5_ITEM

353S2497

1

INTERSIL ISL9563A

U7401

CRITICAL

MCP_ISL9563A

353S2303

1

INTERSIL ISL6263D

U7401

CRITICAL

MCP_ISL6263D

VID<2:0>

Voltage

TABLE_5_ITEM

(MCPCORES0_FB)

000

+1.100V

C7482

R7478

100

1.1V DEFAULT, OTHER VALUES TBD
TABLE_5_HEAD

PART#

2

(MCPCORES0_COMP)

1%
1/16W
MF-LF
402

560PF
2

MCPCORES0_VDIF_C

R7479

2.21K2

1

1%
1/16W
MF-LF
402

A

1

0.001UF

C7480
68PF

1

2

10%
50V
CERM
402

(MCPCORES0_VDIFF)

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP CORE REGULATOR
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

74 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

1.5 V DDR SUPPLY
D

D
PPDDR_S3_REG
VOUT
PEAK
AVG

1

= 1.5V
= 11.28A
= 6.72A

C7555
10UF

2

30 6

20%
6.3V
X5R
603

6

=PPVIN_S5_DDRREG
CRITICAL

R7505

=PP5V_S3_DDRREG

4.7
1

EMC CAPS
PLACE CLOSE TO FET

DIDT=TRUE

C7530

PP5V_S3_DDRREG_V5FILT

2

5%
1/16W
MF-LF
402

CRITICAL
1

270UF

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

20%
16V
ELEC
8X12-TH-HF

C7531

1
1

1

C7532

2

20%
16V
ELEC
8X12-TH-HF

10%
16V
X5R-CERM
0805

2

2

C7510

1

0.1UF

10UF

270UF

2

20%
16V
CERM
603

C7511
0.1UF
20%

2 16V
CERM
603

EMC CAPS
PLACE CLOSE TO L7530

5

4.7UF
20%
6.3V
CERM
603

D

1

1UF
10%
10V
X5R
402-1

2

DDRREG_VDDQSNS

23

C7505

14

1

15

C7500

V5FILT

VLDOIN

6 COMP

C
70

IN
IN

DDRVTT_EN
=DDRREG_EN
TP_PGOOD_DDRREG_S3

6

PPVTT_S3_DDR_BUF

6

PPVTT_S0_DDR_LDO

10 S3
11 S5
13 PGOOD

XW7560

DDRREG_VBST

VBST 22

U7500

VDDQ PGOOD

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

DRVH 21

QFN

5 VTTREF

LL 20

24 VTT

Vout = VTTREF

DRVL 19

20%
6.3V
CERM-X5R

C7561
22UF

2

805-3

2

20%
6.3V
CERM-X5R
805-3

VDDQSET 9
THRM_PAD GND

PGND

1

20%

2 16V
CERM
603

603

S

C7525

R7525
1

0

5%
1/10W
MF-LF
603

2

DDRREG_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

1

2

1.5UH-22A-4MOHM
1

SWITCHNODE

PPDDR_S3_REG

2

MSQ12111R5LF-TH
20%
25V
CERM
603

5

4

(DDRREG_DRVL)

G

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

CRITICAL

Q7535
CSD58857Q5

5%
25V
2 NP0-C0G
402

MLP5X6-LFPAK-Q5

C7563
1000PF

1V5_SNUBBER
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.4MM
DIDT=TRUE

1

20%
2 2V
POLY
CASE-D2-HF1

CRITICAL
1

1

20%
2V 2
POLY
CASE-D2-HF1

2

C7541
330UF-0.009OHM

C7545
10UF

2

20%
6.3V
X5R
603

XW7545
SM

PLACEMENT_NOTE=PLACE NEXT TO L7530

R7562
0.499

CS_GND

1

1%
1/10W
MF
2 603

XW7535
SM
1

NOSTUFF
1

1 2 3
PLACEMENT_NOTE=Place next to Q7335

C7540
330UF-0.009OHM

D

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

2

NO STUFF

NOSTUFF

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

C7520

1
1

5%
50V
CERM
402

C7550

STATE
S0
S3
S5

B

S3
HI
LO
LO

S5 VDDQ VTTREF
HI
ON
ON
ON
HI
ON
LO
OFF
OFF

VTT
ON
OFF
OFF

2

XW7501

1

SM

0.033UF
10%
16V
X5R
402

(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

2

1%
1/16W
MF-LF
2 402



(DDRREG_FB)

2

Vout = 0.75V * (1 + Ra / Rb)

1

XW7500

2

R7520
15.0K

100PF
DDRREG_PGND
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

6

VOUT = 1.50V
14.75A MAX OUTPUT
(Q7335 limit)
f = 400 kHz

CRITICAL
1

(DDRREG_LL)

(DDRREG_CSGND)

C

CRITICAL

L7530

1 2 3

0.1UF

C7513
0.1UF

20%

2 16V
CERM

MLP5X6-LFPAK-Q5A

DDRREG_FB

DDRREG_CSGND

C7512
0.1UF

CSD58856Q5A

S

VTTGND

1

Q7530

G

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DDRREG_CS

17

22UF

NC
NC

CS 16

7 NC0
12 NC1

18

1

2 VTTSNS

3

1

DDRREG_VTTSNS
NO_TEST=TRUE
FEEDBACK THROUGH SHORT
SHOULD NOT NEED TP

1

C7560

2

CRITICAL

DDRREG_DRVL
GATE_NODE=TRUE
DIDT=TRUE

25

CRITICAL

DDRREG_LL
SWITCH_NODE=TRUE
DIDT=TRUE

SM
1

DDRREG_DRVH
GATE_NODE=TRUE
DIDT=TRUE

SYM (2 OF 2)

Vout = VDDQSNS/2

1%
1/16W
MF-LF
402 2

MODE 4

VDDQ/VTTREF Enable

1

5.90K

VTT Enable

TPS51116
10mA max load

R7510

VDDQSNS 8
CRITICAL

78 9

4

(DDRREG_DRVH)
V5IN

2

CRITICAL

1

SM

R7521
15.0K

1%
1/16W
MF-LF
2 402

1

B



GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

1.5V DDR SUPPLY
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

75 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

FSB VTT AND 3.3V S5 RAILS
D

D
INPUT POWER OF 12V_S5
6

=PP12V_S5_REG

6

EMC CAPS
PLACE CLOSE TO FET

=PPVIN_S5_P3V3S5
DIDT=TRUE
CRITICAL

C7681

C7680

1

1

2.2

VOLTAGE=12V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.20 MM

DIDT=TRUE

1

1

C7611
0.1UF

10%
16V
X5R-CERM 2
0805

C7622
0.1UF

CRITICAL

Q7610
RJK0384DPA

20%

20%

2 16V
CERM

16V
2 CERM

D1

603

603

1

C7608

10UF

10UF

10%
16V
X5R-CERM
0805

10%
16V
X5R-CERM
0805

2

10%
16V
X5R
1206

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

PP5V_S5_LDO
2

C7670

G2
2

10%
16V
X5R
603

(PVTTS0_LGATE)

6

1
1

1UF

1

2

PPVTT_S0_FSB_REG

1

OMIT
CRITICAL

C7614

L7610
2

1.5UH-12A

(R7614 LIMIT)

1

2

PLACEMENT_NOTE=Place next to C7516

PVTTS0_BOOT
PVTTS0_UGATE

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.25MM

(PVTTS0_PHASE)

SWITCHNODE

MMD06EZ-SM

f = 200 kHz

5%
1/10W
MF-LF
603

6
17
15
16
18
10
14
9
11
12
29
4

108 PVTTS0_PHASE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

DIDT=TRUE
DIDT=TRUE
DIDT=TRUE

PVTTS0_LGATE DIDT=TRUE

2

(=PVTTS0_EN)

CRITICAL

C7615

1

C7617

10UF

1

10UF

10%
16V
X5R-CERM 2
0805

C7621

1
1

330UF

10%
16V
X5R-CERM
0805

2

20%
2.5V 2
POLY-TANT

C7623

1

0.1UF
20%
2 16V
CERM
603

2

XW7616

EN LDO ASAP

1%
1/10W
MF
2 603

EMC CAPS
PLACE CLOSE
TO L

NOSTUFF

76

1

R7620
7.32K

C7620
5%
50V
CERM
402

1

NC
NC

3

108 3V3S5_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.20 MM

SWITCHNODE
CRITICAL

7
8
24
26
25
23
30
27

D1

WPAK

PEAK=0.69A
AVE=0.46A

G1

1

CRITICAL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.20 MM

S1/D2

R7666
1

3V3_BOOT2
DIDT=TRUE

0.25MM
0.2MM

0

DIDT=TRUE

23V3_BOOT2_R

DIDT=TRUE

EN REG ASAP
AFTER LDO OUT

1

76

S2

R7675

1

1

NOSTUFF

3V3_SNUBBER
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.4MM
DIDT=TRUE
1

C7675

R7662
0.499

10%
16V
X5R
603

PGOOD_1V05_S0

OUT

PGOOD_3V3_S5

PGND

CRITICAL

70

C7691 1
0.1UF

20%
16V
CERM 2
603

2

OMIT

XW7651
SM

1%
1/10W
MF
2 603

1

1

1

C7694
10UF
20%

2 6.3V
CERM

805-1

C7626
0.1UF

C7693 1
330UF

20%
6.3V 2
POLY-TANT
CASE-D3L-SM
1

C7692
10UF

20%

20%
6.3V

2 16V
CERM

NOSTUFF

3V3S5_OUT

C7685

1

R7614

0.1UF

110K

0.5%
1/16W
MF
2 402

6

2 CERM

805-1

THRM_PAD GND

R7621

PP3V3_S5_REG

C7663
1000PF

5%
2 25V
NP0-C0G
402

1UF

2

(3.3V NOMINAL)

2
MMD06EZ-SM

10%
25V
2 X5R
402

5%
1/16W
MF-LF
2 402

3V3S5_REF

1

0.1UF

200K

3V3S5_ILIM

L7660

G2

6

C7666
3V3S5_BG

1

7

2.2UH-10A-13.6MOHM

0.25MM

5%
0.2MM
1/10W
MF-LF
603

DIDT=TRUE

REFIN2 32
ILIM2 31
REF 1
POK1 13
POK2 28

SEL A3V3 S5
K22/K23
POWER BUDGET

5
20 NC

2

10.0K

PEAK=5.28A
AVE=2.88A

C

20%
6.3V
CERM
603

603
1

100PF

1%
1/16W
MF-LF
2 402

C7689

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.20 MM

2 TON

3V3REG_TON

NO STUFF


VTT_FSB_S0
K22/K23
POWER BUDGET

U7600

PVTTS0_VSNS

1

R7663
0.499

PVTTS0_FB
PVTTS0_ILIM

OMIT

PVTT_SNUBBER
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.4MM
DIDT=TRUE

20%
16V
CERM
603

CASE-D2E-SM

B

SM

5%
2 25V
NP0-C0G
402

C7616
0.1UF

NOSTUFF

C7662
1000PF

6

3V3S5_TG

LDO
LDOREFIN
CRITICAL BOOT2
UGATE2
PHASE2
QFN
LGATE2
OUT2
EN2

33

1

VIN
BOOT1
UGATE1
PHASE1
LGATE1
OUT1
EN1
BYP
FB1
ILIM1
SKIP*
EN_LDO

21

6.7A MAX OUTPUT

10%
16V
X5R-CERM 2
0805

Q7660
RJK0384DPA

PVCC VCC

0.1UF
10%
50V
X7R
603-1

1

10UF

VOLTAGE=5V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.1 MM

ISL6237

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.25MM

2

1

6

0

19

3

4

5

R7610
1

C7678

10%
16V
X5R-CERM 2
0805

3V3REG_VCC

76

PVTTS0_BOOT_R

1

10UF

4.7UF
2

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

S2

Vout = 1.212V for Wolfdale

603

1

10UF

(P1V05S0_UGATE)

1

S1/D2

7

C7609

C7601

WPAK
G1

C

20%

5

1

10UF

0.1UF

2

C7610

2

C7625

2 16V
CERM

4

1

20%
16V
CERM
603

3

10%
16V
X5R-CERM
0805

2

C7679

22

C7612
10UF

10%
16V
X5R-CERM
0805

2

1

10UF

0.1UF

10%
16V
X5R-CERM
0805

2

1

C7624

10UF

PPVIN_S5_3V3_VTT_R

EMC CAPS
PLACE CLOSE TO FET
=PPVIN_S0_PPVTT_FSB

C7613

2

1

C7683

5%
1/8W
MF-LF
2 805

INPUT POWER OF 12V_S0

6

1

10%
16V
X5R-CERM 2
0805

20%
16V 2
POLY
6.3X9-TH

R7650

1

10UF

100UF

1

10%
16V
X7R-CERM 2
402

1%
1/16W
MF-LF
2 402

B

EMC CAPS
PLACE CLOSE
TO L
1

R7667
110K

1%
1/16W
MF-LF
2 402


Vout = 0.7V * (1 + Ra / Rb)
70

IN

GND_PP3VREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

=PVTT_S0_EN

OMIT
1

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

2

XW7650
SM

TABLE_5_HEAD

BOM OPTION
TABLE_5_ITEM

152S1078

1

IND,PWR,1.5UH,20%,9A,12mOHM

L7610

CRITICAL

SELECTS SWITCHING FREQUENCY
76

3V3REG_VCC
1 NOSTUFF

R7643

EN_LDO TIED TO 12V_S5 TO EN LDO FIRST & REGULATOR INTERNAL LOGIC GETS POWER
EN2 (3V3_S5) IS TIED TO VCC, TIED INTERNALLY TO PVCC
TIED EXTERNALLY TO LDO OUT. SO REGULATOR IS ENABLED
3V3REG_TON
AS SOON AS LDO OUTPUT IS GOOD

5%
1/16W
MF-LF
2 402

EN1 (PPVTT_S0) CONTROLLED SEPARATELY

1

0

76

A

2
76

R7622
0

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

5%
1/16W
MF-LF
402

FSB VTT/3.3V S5 SUPPLIES
DRAWING NUMBER

Apple Inc.

3V3S5_REF

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

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D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

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A.0.0

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8

7

6

5

4

3

2

1

D

D
5V S0 FET

3.3V S0 FET
78 70 38 6

C7800

=PP12V_S5_PWRCTL

0.1UF

1

10%
2 16V
X5R
402

CRITICAL

78 70 38 6

C7853

1

10%
16V
2 X5R
402

CRITICAL

Q7800

Q7853

0.1UF

POWER33

6 110

3

Q7850

2

=PP3V3_S5_S0FET

PP3V3_S0

IRFH7914PBF

6

1

D

S

6

1

G

4

6 110

=PP3V3_S5_S3FET
5

G

G
4

PP3V3_S3

PQFN

S

S

1

D

6

5

D

PP5V_S0

PQFN

=PP5V_S3_S0FET

C7850

10%
16V
2 X5R
402

CRITICAL

FDMC8296

IRFH7914PBF
5

=PP12V_S5_PWRCTL

0.1UF

1

1

6

3.3V S3 FET

=PP12V_S5_PWRCTL

78 70 38 6

70

IN

4

1

TDFN

5D
7G

ON 2

CRITICAL

S6
NC 3

SLG5AP001
5D

TDFN

7G

CRITICAL

ON 2

8 PG

THRM
PAD

GND
4

GND
4

8 PG

THRM
PAD
9

C

S6
NC 3

U7850
S6

C

NC 3
THRM
PAD

GND
4

CRITICAL

8 PG

VCC

U7853
SLG5AP001

9

7G

ON 2

9

TDFN

P3V3_S3_EN

SLG5AP001
5D

PGOOD_5V_S0

OUT

VCC
P3V3_S0_EN

P5V_S0_EN
70

1

VCC

U7800

=P5VS0_EN
70

IN

=P3V3S0_EN
70

IN

P3V3S3_EN

1.5V S0 FET
78 70 38 6

MCP79 DDRVTT FET

=PP12V_S5_PWRCTL
1

C7825

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
LOW THROUGH VTT TERMINATION RESISTORS.

0.1UF

10%
16V
2 X5R
402

CRITICAL

B

Q7825
IRFH7914PBF
PP1V5_S0_FET

PQFN
1

S

B

1

4

G

D

=PPDDR_S3_S0FET
5

6

54

MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

P1V5_S0_EN

VCC

TDFN

CRITICAL

8 PG

PGOOD_1V5_S0

R7875

ON 2
6

7G

=PPVTT_S0_VTTCLAMP

2

S6

6

GND

10

1

VTTCLAMP_L

60mA max load @ 0.75V
45mW max power

5%
1/10W
MF-LF
603

NC 3
THRM
PAD

4

OUT

SLG5AP001
5D

9

70

U7825

=PP5V_S3_VTTCLAMP

Q7875
R7876

D

6

S

1

SSM6N15FEAPE

1

SOT563

100K
5%
1/16W
MF-LF
402

70

IN

2

2

=MCPDDR_EN

G

VTTCLAMP_EN

A

Q7875

D

3

NO STUFF

C7876

SSM6N15FEAPE

20%
50V
CERM
402
5

75 9

IN

G

1

SYNC_MASTER=K22

0.001UF

SOT563

S

SYNC_DATE=09/02/2009

A

PAGE TITLE

S3 & S0 FETs

2

DRAWING NUMBER

4

Apple Inc.

DDRVTT_EN

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

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D

D

MCP 1.1V_S5 AUXC SUPPLY
=PP3V3_S5_P1V1S5

1
1

R7923
23.2K
1%
1/16W
MF-LF
402

2

2

R7922
1

1

5%
1/16W
MF-LF
402

2

C7920
22UF

C

20%
6.3V
CERM-X5R
805-3

CRITICAL
L7920

1V1S5_AVIN
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

10

(ENABLED AT 2,8V MINIMUM)

C

9

6

2.2UH-3.25A
IHLP1616BZ-SM

AVINPVIN

CRITICAL SW

6 EN

P1V1_S5_EN

1 1V1S5_SW

1

2

PP1V1_S5_REG

SWITCHNODE
MIN_NECK_WIDTH=0.1MM

5 OVT

10%
2 16V
X5R
402

1

C7981
0.1UF
10%

2 16V
X5R

MIN_LINE_WIDTH=0.3MM

1

C7982
22PF

2 50V
CERM

8

402

2

1V1S5_FB

1%
1/16W
MF-LF
402


1

PGOOD_1V1_S5


R7980

R7981

6

Vout = 1.1V

51.1K

5%

AGND PGND THRM_PAD

402

1

DIDT=TRUE

11

C7901
0.1UF

PG

BQA

3

1

U7950

TPS62510

7 MODE

2

NOSTUFF

FB 4

MAX Current = 0.55A
1

C7983

2

20%
6.3V
CERM-X5R
805-3

FREQ = 1Mhz

22UF

60.4K
70

2

1%
1/16W
MF-LF
402

VOUT = 0.6V * (1 + Ra / Rb)

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

1V1 S5 POWER SUPPLY
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

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SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

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A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

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A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

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SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

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Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM
- =PP5V_S0_MXM
- =PPV_S0_MXM_PWRSRC
Signal aliases required by this page:
(NONE)

D

BOM options provided by this page:
- MXM

=PP3V3_S0_MXM

MXM
CRITICAL

MXM

MXM_CLKREQ_L

87

87

MXM_RESET_L

156

102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86

102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86
102 86

A

19
155
153

102 86

B

MXM_PCIE_STD_SWING_L
CLK_100M_MXM_P
CLK_100M_MXM_N

87

C

154

102 86
102 86
102 86
102 86
102 86
102 86

MXM_PCIE_D2R_N<0>
MXM_PCIE_D2R_P<0>
MXM_PCIE_D2R_N<1>
MXM_PCIE_D2R_P<1>
MXM_PCIE_D2R_N<2>
MXM_PCIE_D2R_P<2>
MXM_PCIE_D2R_N<3>
MXM_PCIE_D2R_P<3>
MXM_PCIE_D2R_N<4>
MXM_PCIE_D2R_P<4>
MXM_PCIE_D2R_N<5>
MXM_PCIE_D2R_P<5>
MXM_PCIE_D2R_N<6>
MXM_PCIE_D2R_P<6>
MXM_PCIE_D2R_N<7>
MXM_PCIE_D2R_P<7>
MXM_PCIE_D2R_N<8>
MXM_PCIE_D2R_P<8>
MXM_PCIE_D2R_N<9>
MXM_PCIE_D2R_P<9>
MXM_PCIE_D2R_N<10>
MXM_PCIE_D2R_P<10>
MXM_PCIE_D2R_N<11>
MXM_PCIE_D2R_P<11>
MXM_PCIE_D2R_N<12>
MXM_PCIE_D2R_P<12>
MXM_PCIE_D2R_N<13>
MXM_PCIE_D2R_P<13>
MXM_PCIE_D2R_N<14>
MXM_PCIE_D2R_P<14>
MXM_PCIE_D2R_N<15>
MXM_PCIE_D2R_P<15>

147
149
141
143
135
137
121
123
115
117
109
111
103
105
97
99
91
93
85
87
79
81
73
75
67
69
61
63
55
57
49
51

MXM_PCIE_R2D_N<0>
MXM_PCIE_R2D_P<0>
MXM_PCIE_R2D_N<1>
MXM_PCIE_R2D_P<1>
MXM_PCIE_R2D_N<2>
MXM_PCIE_R2D_P<2>
MXM_PCIE_R2D_N<3>
MXM_PCIE_R2D_P<3>
MXM_PCIE_R2D_N<4>
MXM_PCIE_R2D_P<4>
MXM_PCIE_R2D_N<5>
MXM_PCIE_R2D_P<5>
MXM_PCIE_R2D_N<6>
MXM_PCIE_R2D_P<6>
MXM_PCIE_R2D_N<7>
MXM_PCIE_R2D_P<7>
MXM_PCIE_R2D_N<8>
MXM_PCIE_R2D_P<8>
MXM_PCIE_R2D_N<9>
MXM_PCIE_R2D_P<9>
MXM_PCIE_R2D_N<10>
MXM_PCIE_R2D_P<10>
MXM_PCIE_R2D_N<11>
MXM_PCIE_R2D_P<11>
MXM_PCIE_R2D_N<12>
MXM_PCIE_R2D_P<12>
MXM_PCIE_R2D_N<13>
MXM_PCIE_R2D_P<13>
MXM_PCIE_R2D_N<14>
MXM_PCIE_R2D_P<14>
MXM_PCIE_R2D_N<15>
MXM_PCIE_R2D_P<15>

148
150
142
144
136
138
120
122
114
116
108
110
102
104
96
98
90
92
84
86
78
80
72
74
66
68
60
62
54
56
48
50

F-RT-SM
(2 OF 4)
APPLE P/N: 516S0699
CLK_REQ*
DP_A_AUX*
DP_A_AUX
PEX_STD_SW*
DP_A_HPD
PEX_REFCLK
PEX_REFCLK*
DP_A_L0*
DP_A_L0
PEX_RST*
DP_A_L1*
PEX_RX0*
DP_A_L1
PEX_RX0
DP_A_L2*
PEX_RX1*
DP_A_L2
PEX_RX1
DP_A_L3*
PEX_RX2*
DP_A_L3
PEX_RX2
DP_B_AUX*
PEX_RX3*
DP_B_AUX
PEX_RX3
PEX_RX4*
DP_B_HPD
PEX_RX4
DP_B_L0*
PEX_RX5*
DP_B_L0
PEX_RX5
DP_B_L1*
PEX_RX6*
DP_B_L1
PEX_RX6
DP_B_L2*
PEX_RX7*
DP_B_L2
PEX_RX7
DP_B_L3*
PEX_RX8*
DP_B_L3
PEX_RX8
PEX_RX9*
DP_C_AUX*
PEX_RX9
DP_C_AUX
PEX_RX10*
DP_C_HPD
PEX_RX10
PEX_RX11*
DP_C_L0*
PEX_RX11
DP_C_L0
PEX_RX12*
DP_C_L1*
PEX_RX12
DP_C_L1
PEX_RX13*
DP_C_L2*
PEX_RX13
DP_C_L2
PEX_RX14*
DP_C_L3*
PEX_RX14
DP_C_L3
PEX_RX15*
DP_D_AUX*
PEX_RX15
DP_D_AUX
PEX_TX0*
DP_D_HPD
PEX_TX0
PEX_TX1*
DP_D_L0*
PEX_TX1
DP_D_L0
PEX_TX2*
DP_D_L1*
PEX_TX2
DP_D_L1
PEX_TX3*
DP_D_L2*
PEX_TX3
DP_D_L2
PEX_TX4*
DP_D_L3*
PEX_TX4
DP_D_L3
PEX_TX5*
PEX_TX5
PEX_TX6*
PEX_TX6
PEX_TX7*
PEX_TX7
PEX_TX8*
PEX_TX8
PEX_TX9*
PEX_TX9
PEX_TX10*
PEX_TX10
PEX_TX11*
PEX_TX11
PEX_TX12*
PEX_TX12
PEX_TX13*
PEX_TX13
PEX_TX14*
PEX_TX14
PEX_TX15*
PEX_TX15

6 84 85

MXM

B35P101-0121

5%
1/16W
MF-LF
402 2

85

=PP3V3_S0_MXM

J8400

R84001
100K

DP

85 84 6

PCI-E

D

6

277
279

MXM_DP_A_AUX_N
MXM_DP_A_AUX_P

276

MXM_DP_A_HPD

J8400

=PP5V_S0_MXM

MXM_DP_A_ML_N<0>
MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<2>
MXM_DP_A_ML_N<3>
MXM_DP_A_ML_P<3>

93 107

MXM

91

270
272

MXM_DP_B_AUX_N
MXM_DP_B_AUX_P

274

MXM_DP_B_HPD

246
248
252
254
258
260
264
266

MXM_DP_B_ML_N<0>
MXM_DP_B_ML_P<0>
MXM_DP_B_ML_N<1>
MXM_DP_B_ML_P<1>
MXM_DP_B_ML_N<2>
MXM_DP_B_ML_P<2>
MXM_DP_B_ML_N<3>
MXM_DP_B_ML_P<3>

223
225

MXM_DP_C_AUX_N
MXM_DP_C_AUX_P

234

MXM_DP_C_HPD

199
201
205
207
211
213
217
219

MXM_DP_C_ML_N<0>
MXM_DP_C_ML_P<0>
MXM_DP_C_ML_N<1>
MXM_DP_C_ML_P<1>
MXM_DP_C_ML_N<2>
MXM_DP_C_ML_P<2>
MXM_DP_C_ML_N<3>
MXM_DP_C_ML_P<3>

230
232

MXM_DP_D_AUX_N
MXM_DP_D_AUX_P

236

MXM_DP_D_HPD

206
208
212
214
218
220
224
226

MXM_DP_D_ML_N<0>
MXM_DP_D_ML_P<0>
MXM_DP_D_ML_N<1>
MXM_DP_D_ML_P<1>
MXM_DP_D_ML_N<2>
MXM_DP_D_ML_P<2>
MXM_DP_D_ML_N<3>
MXM_DP_D_ML_P<3>

91 107
91 107
91 107

1

F-RT-SM
(4 OF 4)

93 107

1

253
255
259
261
265
267
271
273

MXM

B35P101-0121

C8410
0.001UF

10%
2 50V
X7R
402

MXM
1

C8401
22UF

20%
2 6.3V
CERM-X5R
805-3

1
3
5
7
9

C8415

MXM
1

0.001UF

3V3

278
280

10%
50V
2 X7R
402

C8416
22UF

20%
6.3V
2 CERM-X5R
805-3

5V
=PPV_S0_MXM_PWRSRC
PWR_SRC

53

E2
E1

91 107
91 107

MXM
91 107

1

91 107

C8400
22UF

91 107

MXM SPEC POWER REQUIREMENTS
87

20%
2 35V
ELEC
6.3X5.5-SM1

MXM
1

MXM

MXM

C8412

1

0.001UF

C8413

0.001UF

10%
50V
2 X7R
402

10%
50V
2 X7R
402

1

C8414

0.001UF

10%
50V
2 X7R
402

(NOT NECESSARILY THE SAME FOR EVERY MODULE)
VOLTAGE
CURRENT
POWER

87

87

3V3
5V
PWR (7-20V)

87
87

1.0 A
2.5 A
UP TO 10 A

C

3.3 W
12.5 W
PLATFORM DEPENDENT

87
87
87
87
87
87

87
87

87

87
87
87
87
87
87
87
87

87
87

B

87

87
87
87
87
87
87
87
87

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MXM PCIe, DP & Power
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

84 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Page Notes
Power aliases required by this page:
- =PP3V3_S0_MXM

Signal aliases required by this page:
- =SMB_MXM_THRM_DATA
- =PM_MXM_PGOOD_PULLUP
- =SMB_MXM_THRM_CLK

D

PULLUPS & PULLDOWNS AT MXM CONNECTOR

D

BOM options provided by this page:

MXM

MXM

J8400

J8400

B35P101-0121

89

89
89

89
89

89
89

89
89

C

89
89

89
89

89
89

89
89

89
89

70
85 70
50

52
52

50
50

B

176
178

LVDS_LCLK*
LVDS_LCLK

MXM_LVDS_A_DATA_N<0>
MXM_LVDS_A_DATA_P<0>

200
202

LVDS_LTX0*
LVDS_LTX0

MXM_LVDS_A_DATA_N<1>
MXM_LVDS_A_DATA_P<1>

194
196

LVDS_LTX1*
LVDS_LTX1

MXM_LVDS_A_DATA_N<2>
MXM_LVDS_A_DATA_P<2>

188
190

LVDS_LTX2*
LVDS_LTX2

MXM_LVDS_A_DATA_N<3>
MXM_LVDS_A_DATA_P<3>

182
184

LVDS_LTX3*
LVDS_LTX3

MXM_LVDS_B_CLK_N
MXM_LVDS_B_CLK_P

169
171

LVDS_UCLK*
LVDS_UCLK

193
195

LVDS_UTX0*
LVDS_UTX0

MXM_LVDS_B_DATA_N<1>
MXM_LVDS_B_DATA_P<1>

187
189

LVDS_UTX1*
LVDS_UTX1

MXM_LVDS_B_DATA_N<2>
MXM_LVDS_B_DATA_P<2>

181
183

LVDS_UTX2*
LVDS_UTX2

MXM_LVDS_B_DATA_N<3>
MXM_LVDS_B_DATA_P<3>

175
177

LVDS_UTX3*
LVDS_UTX3

PM_MXM_EN
PM_MXM_PGOOD
MXM_PWR_LEVEL

8
6
18

PWR_EN
PWRGOOD
PWR_LEVEL

=SMB_MXM_THRM_SCL
=SMB_MXM_THRM_SDA

34
32

SMB_CLK
SMB_DAT

MXM_ALERT_L
MXM_OVERT_L
TP_MXM_TH_PWM

22
20
24

TH_ALERT*
TH_OVERT*
TH_PWM

TP_MXM_VGA_DDC_CLK
TP_MXM_VGA_DDC_DAT

160
158

VGA_DDC_CLK
VGA_DDC_DAT

TP_MXM_VGA_BLUE
TP_MXM_VGA_GREEN
TP_MXM_VGA_HSYNC
TP_MXM_VGA_RED
TP_MXM_VGA_VSYNC

172
170
164
168
162

VGA_BLUE
VGA_GREEN
VGA_HSYNC
VGA_RED
VGA_VSYNC

MXM_VGA_DISABLE_L

21

GPIO0
GPIO1
GPIO2

26
28
30

TP_MXM_GPIO0
TP_MXM_GPIO1
TP_MXM_GPIO2

HDMI_CEC

29

TP_MXM_HDMI_CEC

DVI_HPD

MXM_LVDS_A_CLK_N
MXM_LVDS_A_CLK_P

MXM_LVDS_B_DATA_N<0>
MXM_LVDS_B_DATA_P<0>

F-RT-SM
(3 OF 4)
VGA_DISABLE*

85

OEM0
OEM1
OEM2
OEM3
OEM4
OEM5
OEM6
OEM7

38
39
40
41
42
43
44
45

PNL_BL_EN

25

MXM_PNL_BL_EN

89

PNL_BL_PWM

27

MXM_PNL_BL_PWM

89

LVDS

89

31

B35P101-0121

F-RT-SM
(1 OF 4)

PNL_PWR_EN

SYSTEM MANAGEMENT

TP_MXM_DVI_HPD

LVDS_DDC_CLK
LVDS_DDC_DAT

MANAGEMENT
POWER/THERMAL

89 85

35
33

ANALOG DISPLAY

89 85

MXM_LVDS_DDC_CLK
MXM_LVDS_DDC_DAT

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
PRSNT_L*
PRSNT_R*
WAKE*

MXM_PNL_PWR_EN

23
10
159
12
161
163
165
167
227
229
231
233
235
237
238
239
240
241
242
243
245
247
249
14
16
281
2

89

11
13
15
17
36
37
46
47
52
53
58
59
64
65
70
71
76
77
82
83
88
89
94
95
100
101
106
107
112
113
118
119
124
125
133
134
139
140

GND

FLOAT = NORMAL VGA MODE
GND = SECONDARY DISPLAY CARD

GND

145
146
151
152
157
166
173
174
179
180
185
186
191
192
197
198
203
204
209
210
215
216
221
222
228
244
E3
250
251
256
257
262
263
268
269
275
282
283
E4

85

NOSTUFF

R8510
2

MXM_VGA_DISABLE_L

MF-LF

0

1

5% 1/16W
402

MXM

R8504

FLOAT = LOW SWING
GND = HIGH SWING
84

MXM_PCIE_STD_SWING_L

2
MF-LF

0

1

5% 1/16W
402

C

=PP3V3_S0_MXM

R8500
85 9

MXM_DETECT_L

1

100K 2

MF-LF 5% 1/16W
402

PULLED TO GROUND ON MXM
WE DON’T USE CARD DETECT

R8501
85

MXM_DETECT_R

1

100K 2

MF-LF 5% 1/16W
402

=PM_MXM_PGOOD_PULLUP
MXM_DETECT_L
MXM_DETECT_R

6 84 85

B

70

SYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,
OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIOR

9 85
85

TP_MXM_WAKE_L

4

R8503
85 70

PM_MXM_PGOOD

2
MF-LF

10K

1

5% 1/16W
402

MXM SYSTEM INFORMATION ROM
PLACE CLOSE TO J7800
=PP3V3_S0_MXM

6 84 85

MXM
1

C8570
0.1UF

STUFF FOR WRITE PROTECT
NOSTUFF

R85701

I2C ADDRESS: AC 8
VCC
3 E2/NC2 MXM
5
2 E1/NC1 CRITICALSDA
1 E0/NC0
SCL 6

0

5%
1/16W
MF-LF
402 2

A

MXM_ROM_WP

20%
10V
2 CERM
402

MXM_LVDS_DDC_DAT

85 89

MXM_LVDS_DDC_CLK

85 89

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

7 WC* U8570
M24C02-WMN6TPHF
SO8
VSS
4

MXM I/O
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

85 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

MXM TX CAPS
102 9

102 9

D

B

IN

102 9

IN

102 9

IN

102 9

IN

102 9

IN

102 9

IN

102 9

102 9

102 9

C

IN

PEG_R2D_C_N<0>

MXM

PEG_R2D_C_P<0>

MXM

PEG_R2D_C_P<1>

MXM

PEG_R2D_C_N<1>

MXM

PEG_R2D_C_N<2>

MXM

PEG_R2D_C_P<2>

MXM

PEG_R2D_C_N<3>

MXM
MXM

IN

PEG_R2D_C_P<3>
PEG_R2D_C_N<4>

MXM

IN

PEG_R2D_C_P<4>

MXM

IN

102 9

IN

102 9

IN

102 9

IN

102 9

IN

102 9

IN

102 9

IN

PEG_R2D_C_N<5>
PEG_R2D_C_P<5>
PEG_R2D_C_N<6>
PEG_R2D_C_P<6>

IN

PEG_R2D_C_P<8>

102 9

IN

102 9

IN

PEG_R2D_C_N<9>
PEG_R2D_C_P<9>

102 9

IN

PEG_R2D_C_N<10>

102 9

IN

PEG_R2D_C_P<10>

102 9

IN

102 9

IN

102 9

IN

102 9

IN

PEG_R2D_C_P<11>
PEG_R2D_C_N<11>

PEG_R2D_C_N<12>
PEG_R2D_C_P<12>

102 9

IN

PEG_R2D_C_N<13>

102 9

IN

PEG_R2D_C_P<13>

102 9

102 9

IN
IN

102 9

IN

102 9

IN

C8616 0.1UF 1
MXM C8617 0.1UF 1
C8618 0.1UF 1
MXM C8619 0.1UF 1

MXM

C8620 0.1UF 1
MXM C8621 0.1UF 1

MXM

C8622 0.1UF 1
MXM C8623 0.1UF 1
MXM

C8624 0.1UF 1
MXM C8625 0.1UF 1

MXM

C8626 0.1UF 1
MXM C8627 0.1UF 1

MXM

MXM

PEG_R2D_C_P<14>

MXM

PEG_R2D_C_P<15>

C8614 0.1UF 1
C8615 0.1UF 1

MXM

PEG_R2D_C_N<14>

PEG_R2D_C_N<15>

C8608 0.1UF 1
C8609 0.1UF 1

C8612 0.1UF 1
MXM C8613 0.1UF 1

MXM

IN

C8606 0.1UF 1
C8607 0.1UF 1

MXM

MXM

102 9

C8604 0.1UF 1
C8605 0.1UF 1

C8610 0.1UF 1
MXM C8611 0.1UF 1

PEG_R2D_C_P<7>

102 9

C8602 0.1UF 1
C8603 0.1UF 1

MXM

PEG_R2D_C_N<7>

PEG_R2D_C_N<8>

C8600 0.1UF 1
C8601 0.1UF 1

C8628 0.1UF 1
C8629 0.1UF 1

C8630 0.1UF 1
MXM C8631 0.1UF 1
MXM

3

2

1

MXM RX CAPS
2 10% 16V X5R 402

MXM_PCIE_R2D_P<15>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<15>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<14>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<14>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<13>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<13>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<12>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<12>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<11>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<11>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<10>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<10>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<9>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<9>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<8>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<8>

OUT

84 102

OUT

84 102

84 102

102 84

IN

84 102

102 84

IN

OUT

84 102

102 84

IN

OUT

84 102

102 84

IN

OUT

84 102

102 84

IN

OUT

84 102

102 84

IN

OUT

84 102
102 84

IN

OUT

84 102

OUT

84 102

OUT

84 102

OUT

84 102

OUT

84 102

OUT

84 102

OUT

84 102

OUT

84 102

2 10% 16V X5R 402

MXM_PCIE_R2D_N<7>

OUT

84 102

2 10% 16V X5R 402

MXM_PCIE_R2D_N<6>

OUT

84 102

OUT

84 102

2 10% 16V X5R 402

MXM_PCIE_R2D_P<5>

OUT

84 102

2 10% 16V X5R 402

MXM_PCIE_R2D_N<5>

OUT

84 102

2 10% 16V X5R 402

MXM_PCIE_R2D_P<4>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<4>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<3>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<3>

OUT

84 102

OUT

84 102

84 102

OUT

84 102

MXM_PCIE_R2D_P<2>

OUT

84 102

2 10% 16V X5R 402

MXM_PCIE_R2D_N<2>

OUT

84 102

MXM_PCIE_R2D_P<1>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<1>

2 10% 16V X5R 402

MXM_PCIE_R2D_P<0>

2 10% 16V X5R 402

MXM_PCIE_R2D_N<0>

2 10% 16V X5R 402

PEG_D2R_N<0>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<0>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<1>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<1>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<2>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<2>

OUT

9 102

C8638 0.1UF 1
C8639 0.1UF 1

2 10% 16V X5R 402

PEG_D2R_P<3>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<3>

OUT

9 102

C8640 0.1UF 1
C8641 0.1UF 1

2 10% 16V X5R 402

PEG_D2R_N<4>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<4>

OUT

9 102

C8642 0.1UF 1
C8643 0.1UF 1

2 10% 16V X5R 402

PEG_D2R_N<5>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<5>

OUT

9 102

C8644 0.1UF 1
C8645 0.1UF 1

2 10% 16V X5R 402

PEG_D2R_P<6>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<6>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<7>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<7>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<8>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<8>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<9>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<9>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<10>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<10>

OUT

9 102

C8654 0.1UF 1
C8655 0.1UF 1

2 10% 16V X5R 402

PEG_D2R_N<11>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<11>

OUT

9 102

C8656 0.1UF 1
MXM C8657 0.1UF 1

2 10% 16V X5R 402

PEG_D2R_N<12>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<12>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<13>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<13>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<14>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<14>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_N<15>

OUT

9 102

2 10% 16V X5R 402

PEG_D2R_P<15>

OUT

9 102

MXM_PCIE_D2R_P<14>

MXM

MXM_PCIE_D2R_N<14>

MXM

MXM_PCIE_D2R_P<13>

MXM

MXM_PCIE_D2R_N<13>

MXM

MXM_PCIE_D2R_P<12>

MXM

MXM_PCIE_D2R_N<12>

MXM

MXM_PCIE_D2R_P<11>

MXM

MXM_PCIE_D2R_N<11>

MXM

102 84

IN

IN

MXM_PCIE_D2R_P<10>

MXM

102 84

IN

MXM_PCIE_D2R_N<10>

MXM

102 84

IN

MXM_PCIE_D2R_P<9>

MXM

102 84

IN

MXM_PCIE_D2R_N<9>

MXM

102 84

IN

MXM_PCIE_D2R_P<8>

MXM

102 84

MXM_PCIE_D2R_N<8>

MXM

102 84

IN

102 84

IN

102 84

IN

102 84

IN

102 84

IN

102 84

IN

102 84

IN

102 84

C8632 0.1UF 1
C8633 0.1UF 1

MXM_PCIE_D2R_P<7>

MXM

MXM_PCIE_D2R_N<7>

MXM

MXM_PCIE_D2R_P<6>

MXM

MXM_PCIE_D2R_N<6>

MXM

MXM_PCIE_D2R_P<5>

MXM

MXM_PCIE_D2R_N<5>

MXM

MXM_PCIE_D2R_P<4>

MXM

IN
IN

MXM_PCIE_D2R_N<4>

MXM

102 84

IN

MXM_PCIE_D2R_P<3>

MXM

102 84

102 84

IN

MXM_PCIE_D2R_N<3>

IN

MXM_PCIE_D2R_P<2>

MXM

102 84

IN

MXM_PCIE_D2R_N<2>

MXM

102 84

IN

MXM_PCIE_D2R_P<1>

MXM

102 84

IN

MXM_PCIE_D2R_N<1>

MXM

102 84

IN

MXM_PCIE_D2R_P<0>

MXM

102 84

MXM_PCIE_D2R_N<0>

MXM

C8634 0.1UF 1
C8635 0.1UF 1
C8636 0.1UF 1
C8637 0.1UF 1

C8646 0.1UF 1
C8647 0.1UF 1
C8648 0.1UF 1
C8649 0.1UF 1
C8650 0.1UF 1
C8651 0.1UF 1
C8652 0.1UF 1
C8653 0.1UF 1

D

C

B
OUT

2 10% 16V X5R 402

2 10% 16V X5R 402

IN

OUT

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_P<6>

MXM

102 84

MXM_PCIE_D2R_N<15>

OUT

2 10% 16V X5R 402

2 10% 16V X5R 402

MXM_PCIE_D2R_P<15>

MXM

IN

102 84

OUT

84 102

OUT

84 102

OUT

84 102

OUT

84 102
102 84

IN

C8658 0.1UF 1
C8659 0.1UF 1
C8662 0.1UF 1
C8663 0.1UF 1
C8660 0.1UF 1
C8661 0.1UF 1

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MXM PCIE CAPS
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

86 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Page Notes
Power aliases required by this page:
- =PP3V3_S0_DP

Signal aliases required by this page:
(NONE)

D

Unused LVDS Interfaces

BOM options provided by this page:
(NONE)

MCP Connections
84

CLK_100M_MXM_P

84

CLK_100M_MXM_N

84

MXM_RESET_L

GPU_CLK100M_PCIE_P
MAKE_BASE=TRUE
GPU_CLK100M_PCIE_N
MAKE_BASE=TRUE
PEG_RESET_L
MAKE_BASE=TRUE

18

LVDS_IG_A_CLK_P

18

LVDS_IG_A_CLK_N

18

LVDS_IG_A_DATA_P<0>

18

LVDS_IG_A_DATA_N<0>

18

LVDS_IG_A_DATA_P<1>

18

LVDS_IG_A_DATA_N<1>

18

LVDS_IG_A_DATA_P<2>

18

LVDS_IG_A_DATA_N<2>

18

LVDS_IG_A_DATA_P<3>

18

LVDS_IG_A_DATA_N<3>

18

LVDS_IG_B_CLK_P

18

LVDS_IG_B_CLK_N

18

LVDS_IG_B_DATA_P<0>

18

LVDS_IG_B_DATA_N<0>

18

LVDS_IG_B_DATA_P<1>

18

LVDS_IG_B_DATA_N<1>

18

LVDS_IG_B_DATA_P<2>

18

LVDS_IG_B_DATA_N<2>

18

LVDS_IG_B_DATA_P<3>

18

LVDS_IG_B_DATA_N<3>

18

LVDS_IG_DDC_CLK

18

LVDS_IG_DDC_DATA

9 102

9 102

9

C

Unused MXM DP Interfaces

NC_LVDS_IG_A_CLK_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_CLK_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_P<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_N<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_P<1>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_N<1>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_P<2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_N<2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_P<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_N<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_CLK_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_CLK_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_P<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_N<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_P<1>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_N<1>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_P<2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_N<2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_P<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_N<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_DDC_CLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_DDC_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE

84

MXM_DP_B_ML_P<0..3>

84

MXM_DP_B_ML_N<0..3>

84

MXM_DP_B_AUX_P

84

MXM_DP_B_AUX_N

84

MXM_DP_B_HPD

84

MXM_DP_D_ML_P<0..3>

84

MXM_DP_D_ML_N<0..3>

84

MXM_DP_D_AUX_P

84

MXM_DP_D_AUX_N

84

MXM_DP_D_HPD

D

NC_MXM_DP_B_ML_P<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_ML_N<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_AUX_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_DP_B_AUX_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_B_HPD
MAKE_BASE=TRUE
NO_TEST=TRUE

NC_MXM_DP_D_ML_P<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_ML_N<0..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_AUX_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_DP_D_AUX_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_DP_D_HPD
MAKE_BASE=TRUE
NO_TEST=TRUE

Unused MCP Interfaces
18

LVDS_IG_BKL_ON

18

LVDS_IG_BKL_PWM

NC_LVDS_IG_BKL_ON
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_PANEL_PWR
MAKE_BASE=TRUE
NO_TEST=TRUE

18

LVDS_IG_PANEL_PWR

18

=MCP_HDMI_TXD_P<0..2>

18

=MCP_HDMI_TXD_N<0..2>

18

=MCP_HDMI_TXC_P

18

=MCP_HDMI_TXC_N

C

NC_MCP_HDMI_TXD_P<0..2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_HDMI_TXD_N<0..2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_HDMI_TXC_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_HDMI_TXC_N
MAKE_BASE=TRUE
NO_TEST=TRUE

Unused MXM Interfaces

B

85

MXM_LVDS_A_CLK_N

85

MXM_LVDS_A_CLK_P

85

MXM_LVDS_A_DATA_N<0>

85

MXM_LVDS_A_DATA_P<0>

85

MXM_LVDS_A_DATA_N<1>

85

MXM_LVDS_A_DATA_P<1>

85

MXM_LVDS_A_DATA_N<2>

85

MXM_LVDS_A_DATA_P<2>

85

MXM_LVDS_A_DATA_N<3>

85

MXM_LVDS_A_DATA_P<3>

85

MXM_LVDS_B_CLK_N

85

MXM_LVDS_B_CLK_P

85

MXM_LVDS_B_DATA_N<0>

85

MXM_LVDS_B_DATA_P<0>

85

MXM_LVDS_B_DATA_N<1>

85

MXM_LVDS_B_DATA_P<1>

85

MXM_LVDS_B_DATA_N<2>

85

MXM_LVDS_B_DATA_P<2>

85

MXM_LVDS_B_DATA_N<3>

85

MXM_LVDS_B_DATA_P<3>

NC_MXM_LVDS_A_CLK_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_CLK_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_N<1>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MXM_LVDS_A_DATA_P<1>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_N<2>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_P<2>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_N<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_A_DATA_P<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_CLK_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_CLK_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_N<0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_N<1>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<1>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_N<2>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<2>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_N<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MXM_LVDS_B_DATA_P<3>
NO_TEST=TRUE
MAKE_BASE=TRUE

92 91 90 95 6

=PP3V3_S0_DP

1

R8700

1

R8701

2.7K

18

=MCP_HDMI_DDC_CLK

18

=MCP_HDMI_DDC_DATA

18

=MCP_HDMI_HPD

MAKE_BASE=TRUE
DP_IG_DDC_CLK
MAKE_BASE=TRUE
DP_IG_DDC_DATA
MAKE_BASE=TRUE
DP_IG_HPD

5%
1/16W
MF-LF
2 402

2.7K
5%
1/16W
MF-LF
2 402

1

R8710
22K

B

5%
1/16W
MF-LF
2 402

18

DP_IG_AUX_CH_P

18

DP_IG_AUX_CH_N

18

DP_IG_CA_DET

NC_DP_IG_AUX_CH_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_AUX_CH_N
MAKE_BASE=TRUE
NO_TEST=TRUE

1

R8711
1M

5%
1/16W
MF-LF
2 402

A

SYNC_MASTER=MARKVIDEO

SYNC_DATE=03/12/2009

A

PAGE TITLE

Display: Aliases
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

87 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K23_DAVE

SYNC_DATE=01/05/2009

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

88 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

89 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Page Notes
Power aliases required by this page:
- =PP12V_S0_LCD
- =PP3V3_S0_VIDEO

INTERNAL DP INTERFACE

Signal aliases required by this page:
(NONE)

CRITICAL

D

BOM options provided by this page:
IG, MXM, MLB_PNL_PWR, LCD_PNL_PWR

J9002

NOSTUFF

=SMB_DP_TCON_SCL

52

1

NOSTUFF

R9051
0
1

=SMB_DP_TCON_SDA

52

F-RT-SM
33
518S0685

2

5%
1/16W
MF-LF
402

1

I2C MASTER ON TCON
I2C_TCON_SCL
I2C_TCON_SDA

2

D

20389-Y30E-01

R9050
0

5%
1/16W
MF-LF
402

GND

2
3
4

107 92
107 92

DP_INT_AUXCH_N
DP_INT_AUXCH_P

5
6
7

107 92

IN

107 92

IN

C9040
10% 16V
C9041
10% 16V

DP_INT_LINK_P<0>
DP_INT_LINK_N<0>

1

0.1uF

2

X5R
1

107 DP_INT_LINK_CONN_P<0>

402

0.1uF

2

X5R

IN

DP_INT_LINK_P<1>

107 92

IN

DP_INT_LINK_N<1>

IN

DP_INT_LINK_P<2>

C9042
10% 16V
C9043
10% 16V

1

2

1

2

C9044
10% 16V
C9045
10% 16V

1

C9046
10% 16V
C9047
10% 16V

1

0.1uF
X5R

107 DP_INT_LINK_CONN_N<1>

107 92

IN

DP_INT_LINK_N<2>

14

NO_TEST
NO_TEST

15

0.1uF

2

X5R
1

12
13

107 DP_INT_LINK_CONN_P<2>

402

107 DP_INT_LINK_CONN_N<2>
107 92

11

NO_TEST
NO_TEST

402

0.1uF
X5R

9
10

402
107 DP_INT_LINK_CONN_P<1>

107 92

8

NO_TEST
NO_TEST

107 DP_INT_LINK_CONN_N<0>

16

402

107 DP_INT_LINK_CONN_P<3>

0.1uF

2

X5R

DP_INT_LINK_CONN_N<3>

107

402

17

NO_TEST
NO_TEST

18
19

107 92

107 92

IN

DP_INT_LINK_P<3>

IN

DP_INT_LINK_N<3>

0.1uF

2

X5R
1

95

402
95 90

0.1uF

2

X5R

402

92

20

SPDIF_DP_AUDIO_OUT
VIDEO_ON
DP_HPD_INT

21
22
23

C

C

24

PANEL POWER CONTROL

25
6

=PP12V_S0_LCD

PP12V_LCD_CONN

26

VOLTAGE=12V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

27
28

R9000

1

29

CRITICAL

100K

R9001

LCD_PANEL_PWR_L_DIV

1

R9002

1

100K
5%
1/16W
MF-LF
402 2

30

Q9000

5%
1/16W
MF-LF
402 2

29.4K

FDC638P_G

L9000

SM

FERR-250-OHM

C9000

6

PP12V_LCD

0.1UF

5

VOLTAGE=12V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

1

2

4

2

2

1%
1/16W
MF-LF
402

6

1

32

20%
50V
CERM
402

C9020

1

C9001

10UF
10%
16V
X5R-CERM
0805

1

GND

1
34

0.001uF

SM

3

31

C9010

2

1

10%
50V
X7R
603-1

=PP3V3_S0_VIDEO

2

0.001uF
20%
50V
CERM 2
402

2

LCD_PANEL_PWR_L_RC

PLACE NEAR J9002
NOSTUFF

LCD_PANEL_PWR_L

R9071
95

LCD_PANEL_PWR

1

0

3
2

LCD_PANEL_PWR_G
D

5%
1/10W
MF-LF
603

B

R9072
95 90

VIDEO_ON

1

0
5%
1/10W
MF-LF
603

Q9001
2N7002

1

2

G

SOT23-HF1

S
2

B

=PP3V3_S0_DP

92 91 90 87 95 6

1

NOSTUFF

R9070
100K

1

5%
1/16W
MF-LF
402

2 10V
CERM

C9011
0.1UF
20%

2

402

CRITICAL

NOSTUFF

5 TC7SZ08AFEAPE
95 90

95

2

VIDEO_ON
LCD_BKL_ON_MUX

BACKLIGHT CONTROL SUPPORT

1

R9012

SOT665

A

U9050Y

L9050

R9081

NOSTUFF

4

1

LCD_BKL_MLB_EN

1K

95

3

1

47

2

LCD_PWM_FILT

1

2

LCD_PWM

6

SM

5%
1/16W
MF-LF
402

2

5%
1/16W
MF-LF
402

B

BACKLIGHT_PWM

FERR-250-OHM

guarantee backlight is
only on when Panel has valid video
Options for GPU or MLB HW controlled backlight enable are included

92 91 90 87 95 6

6

=PP3V3_S0_DP

VIDEO_ON_L

OUT

1

A

92 91 90 87 95 6

2

=PP3V3_S0_DP

U9500
14
95 90

VIDEO_ON

3

20%
6.3V
CERM
805

5

D9000
SOT23

74LVC14
4

1

3

14
7

C9005
22UF

used by diag LED

SYNC_MASTER=MARKVIDEO

U9520

74AUP2G14GM
VIDEO_ON_L_DLY

3

4

LCD_BKL_ON_DLY

BAT54XG
2

R9009

1

1K

2

LCD_BKL_ON OUT

A

Display: Int DP Connector

6

DRAWING NUMBER

5%
1/16W
MF-LF
402

TSSOP-HF

SYNC_DATE=03/12/2009

PAGE TITLE

R9011

SOT886

Apple Inc.

051-7863

19.1K2

NOTICE OF PROPRIETARY PROPERTY:

1%
1/16W
MF-LF
402

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

buffers are multiple parts, other parts are on csa 95

D

REVISION

A.0.0

R

1

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PAGE

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8

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1

EQ & Re-Driver for DP source

1

107 84

IN

107 84

IN

107 84

IN

107 84

IN

107 84

IN

107 84

IN

107 84

IN

MXM_DP_A_ML_P<0>
MXM_DP_A_ML_N<0>
MXM_DP_A_ML_P<1>
MXM_DP_A_ML_N<1>
MXM_DP_A_ML_P<2>
MXM_DP_A_ML_N<2>
MXM_DP_A_ML_P<3>
MXM_DP_A_ML_N<3>

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

1

C9123
10% 16V

1

X5R

20%
10V
CERM
402

2

2

1

2

C9126
10% 16V

1

2

0.1uF

2

84

OUT

C9104

1

0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

2

2

D

C9105

0.1UF

20%
10V
CERM
402

Common mode bias for Tx EQ AUX interception

1

402

0.1uF
402

0.1uF

2

16V

107

0.1uF
X5R

X5R

=PP3V3_S0_DP

NOSTUFF

5%

402
1
MF-LF

499
1%

=PP3V3_S0_DP

38
39
41
42
44
45
47
48

R91501
107 MXM_DP_A_ML_EQ_P<0>

23
22
20
19
17
16
14
13

OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N

IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N

107 MXM_DP_A_ML_EQ_N<0>
107 MXM_DP_A_ML_EQ_P<1>
107 MXM_DP_A_ML_EQ_N<1>
107 MXM_DP_A_ML_EQ_P<2>
107 MXM_DP_A_ML_EQ_N<2>
107 MXM_DP_A_ML_EQ_P<3>
107 MXM_DP_A_ML_EQ_N<3>

1

R9151

100K

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

100K

5%
1/16W
MF-LF
402 2

107 91

MXM_DP_A_AUX_C_P
NO_TEST

C9150
10% 16V

1

2

107 91

MXM_DP_A_AUX_C_N
NO_TEST

C9151

1

2

10%

5%
1/16W
MF-LF
2 402

0.1uF
X5R

402

0.1uF

16V

X5R

402

DP_TX_EQ_AUXCH_P
NO_TEST

91 107

DP_TX_EQ_AUXCH_N
NO_TEST

91 107

402

R91002
10K

92 91 90 87 95 6

QFN
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

1/16W

NOSTUFF

5%

R91022
1/16W

10K

10K
5%

PS8121_PC0
3
PS8121_PC1
4
PS8121_I2C_EN_L26

402
1
MF-LF

PC0/I2C_ADDR0 INT_PD
PC1/I2C_ADDR1 INT_PD
I2C_CTL_EN* INT_PD

25

402
1
MF-LF

PS8121_REXT

402
1

OE*

6

402

92 91 90 87 95 6

BI
IN

52
52

4.7UF

10 PS8121_CEXT 6.3V
1

CEXT

CA_DET

7

107 91

C9106

MF-LF

DP_CA_DET
MXM_DP_A_HPD

107 91

=I2C_DP_DRV_SDA
=I2C_DP_DRV_SCL

34
35

SDA_CTL
SCL_CTL

INT_PD

DP_TX_EQ_AUXCH_P
DP_TX_EQ_AUXCH_N

8
9

AUX+
AUX-

REXT

27

C

1

0.1UF

PS8121ED
MXM_DP_A_ML_C_P<0>
MXM_DP_A_ML_C_N<0>
107 MXM_DP_A_ML_C_P<1>
107 MXM_DP_A_ML_C_N<1>
107 MXM_DP_A_ML_C_P<2>
107 MXM_DP_A_ML_C_N<2>
107 MXM_DP_A_ML_C_P<3>
107 MXM_DP_A_ML_C_N<3>

402

X5R

1/16W
IN

2

C9103

U9100

402

X5R

R91032
91 94

1

402

X5R

C9125
10% 16V

1/16W

0.1UF

0.1uF

2

1

R91012

C9102

20%
10V
CERM
402

0.1uF

2

C9124
10% 16V

NOSTUFF

1

0.1UF

402

107

C9127

C9101

20%
10V
CERM
402

VCC

C9122
10% 16V

10%

92 91 90 87 95 6

X5R

1

0.1UF
2

0.1uF

2

C9100

HPD

2

20%

C

X5R-CERM

30

HPD_SINK

=PP3V3_S0_DP

=PP3V3_S0_DP
NC

36
2
32

MODE
CFGX
CFGY

1
NC
28
NC
29
NC

NC
GND

THRM_PAD
49

5
12
18
24
31
37
43

A4
B5
A5
B6
A6
A8
A9

107 84

BI
BI

MXM_DP_A_AUX_P
NO_TEST
MXM_DP_A_AUX_N
NO_TEST

C9138
10% 16V
C9139
10%

16V

1

2

0.1uF
X5R

1

2

0.1uF
X5R

91
107 MXM_DP_A_AUX_C_P

NO_TEST

91
107 MXM_DP_A_AUX_C_N

NO_TEST

H9

402

J9

402

H8
J8

B

=PP3V3_S0_DP

From external source
to internal display via EQ

J2

92 91 90 87 95 6

92 107

OUT

92 107

OUT

92 107

OUT

92 107

OUT

92 107

OUT

92 107

OUT

92 107

OUT

92 107

OUT

107 92

BI

107 92

BI

DP_MUX_N<3>
DP_MUX_P<3>

NO_TEST
NO_TEST

B8

DP_MUX_N<2>
DP_MUX_P<2>

NO_TEST
NO_TEST

D8

DP_MUX_N<1>
DP_MUX_P<1>

NO_TEST
NO_TEST

E8

DP_MUX_N<0>
DP_MUX_P<0>

NO_TEST
NO_TEST

F8

DP_MUX_AUXCH_P
DP_MUX_AUXCH_N

10K

5%
1/16W
MF-LF
402 2

D9

E9

F9
H6

NO_TEST
NO_TEST

J6
H5
J5

DIN1_0+
DIN1_0-

VDD
2

C9322

1

20%
10V
CERM
402

2

CBTL06141EE
BGA

DIN1_2+
DIN1_2-

CRITICAL

DIN1_3+
DIN1_3-

107
DOUT_0+
107
DOUT_0-

B2
B1

NO_TEST
DP_EXT_LINK_C_P<0>
DP_EXT_LINK_C_N<0>
NO_TEST

107
DOUT_1+
107
DOUT_1-

DDC_CLK1
DDC_DAT1

1

2

C9131

1

2

D2
D1

NO_TEST
DP_EXT_LINK_C_P<1>
DP_EXT_LINK_C_N<1>
NO_TEST

107
DOUT_2+
107
DOUT_2-

E2
E1

DIN2_0+
DIN2_0-

NO_TEST
DP_EXT_LINK_C_P<2>
DP_EXT_LINK_C_N<2>
NO_TEST

107
DOUT_3+
107
DOUT_3-

DIN2_1+
DIN2_1DIN2_2+
DIN2_2DIN2_3+
DIN2_3-

F2
F1

AUX+
AUX-

H2

HPDIN

J1

H1

NO_TEST
DP_EXT_LINK_C_P<3>
DP_EXT_LINK_C_N<3>
NO_TEST

16V
1

2

1

2

C9134
10% 16V

1

2

C9135

1

2

C9136
10% 16V

1

2

C9137
10% 16V

1

2

402

0.1uF
X5R

402

0.1uF
X5R

402

NO_TEST
NO_TEST

DAUX2+
DAUX2-

107 94

BI

107 94

BI

107 94

BI

107 94

BI

107 94

BI

107 94

BI

107 94

BI

107 94

DP_EXT_AUXCH_P
DP_EXT_AUXCH_N

BI

94 107 95

BI

94 107 95

DP_HPD_EXT

BI

94 95

DP_CA_DET

IN

NO_TEST
DP_EXT_LINK_P<1>
DP_EXT_LINK_N<1>
NO_TEST
NO_TEST
DP_EXT_LINK_P<2>
DP_EXT_LINK_N<2>
NO_TEST

402

0.1uF
X5R

BI

402

0.1uF
X5R

16V

402

0.1uF
X5R

NO_TEST
DP_EXT_LINK_P<0>
DP_EXT_LINK_N<0>
NO_TEST

402

0.1uF
X5R

16V

402

0.1uF
X5R

C9133

10%

0.1uF
X5R

C9132
10% 16V
10%

HPD_1

NO_TEST
DP_EXT_LINK_P<3>
DP_EXT_LINK_N<3>
NO_TEST

B

R9309

DDC_CLK2
DDC_DAT2

IN

DP_MUX_HPD

H3

HPD_2

95 49

IN

DPMUX_VIDEO_IN_SEL

A1

GPU_SEL

B7

XSD*

DP_HPD_EXT_R

1

1K

2

1%
1/16W
MF-LF
402
LO=AUX_CH
HI=DDC

LO=PORT1
HI=PORT2

DDC_AUX_SEL

C2

TST0

G2

GND

DisplayPort Mux 1
Analog mux at External Connector

A

C9130
10% 16V
10%

DAUX1+
DAUX1-

92

DPMUX1_ENABLE

C9323
0.1UF

20%
10V
CERM
402

U9120

DIN1_1+
DIN1_1-

B3

IN

B9

NC
NC

NOSTUFF

R91301

95

1

0.1UF
B4

107 84

6 95 87 90 91 92

MXM_DP_A_HPD_EQ

J4

IN

1

402

94 91

H7

107 84

X5R

A2

From iMac GPU

C9121
10% 16V

0.1uF

2

To External connector

1

16V

H4

10%

G8

C9120

C8

D

=PP3V3_S0_DP

11
15
21
33
40
46

92 91 90 87 95 6

SYNC_MASTER=MARKVIDEO

SYNC_DATE=03/12/2009

A

PAGE TITLE

Display: BiDiVi Mux1
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

91 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D
=PP3V3_S0_DP

1

IN

MXM_DP_C_ML_P<0>
NO_TEST

C9240
10%

1

2

2

2

16V

107 84

IN

MXM_DP_C_ML_N<0>
NO_TEST

C9241
10% 16V

107 84

IN

MXM_DP_C_ML_P<1>
NO_TEST

C9242
10% 16V

1

107 84

IN

MXM_DP_C_ML_N<1>
NO_TEST

C9243
10% 16V

1

2

107 84

IN

MXM_DP_C_ML_P<2>
NO_TEST

C9244
10% 16V

1

2

107 84

IN

MXM_DP_C_ML_N<2>
NO_TEST

C9245
10% 16V

1

2

107 84

IN

MXM_DP_C_ML_P<3>
NO_TEST

C9246
10% 16V

1

2

107 84

IN

MXM_DP_C_ML_N<3>
NO_TEST

C9247
10%

0.1uF
X5R

1

0.1uF
X5R

NO_TEST

107 MXM_DP_C_ML_C_P<1>

NO_TEST

107 MXM_DP_C_ML_C_N<1>

NO_TEST

107 MXM_DP_C_ML_C_P<2>

NO_TEST

107 MXM_DP_C_ML_C_N<2>

NO_TEST

107 MXM_DP_C_ML_C_P<3>

NO_TEST

402

0.1uF
X5R

92 91 90 87 95 6

=PP3V3_S0_DP

R92211 R92151 R92201
1K

1K
5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

1K

2

1

C9202
0.1UF

20%
2 10V
CERM
402

2

402

0.1uF
X5R

0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

2

107 MXM_DP_C_ML_C_N<3>

107 91

IN

107 91

IN

107 91

IN

107 91

IN

107 91

IN

107 91

IN

107 91

IN

107 91

IN

=I2C_DP_EQLZ_SDA

2
3
5
6
8
9
11
12
68

=I2C_DP_EQLZ_SCL

14
15
17
18
20
21
23
24
67

NO_TEST
IN

DP_MUX_P<0>
DP_MUX_N<0>
DP_MUX_P<1>
DP_MUX_N<1>
DP_MUX_P<2>
DP_MUX_N<2>
DP_MUX_P<3>
DP_MUX_N<3>
52

IN

MODE[2..0] = 111 SELECTS I2C CONTROL MODE

R9222 14.99K2
1%

92 91 90 87 95 6

1/16W

From external input
via MUX 1

MXM_DP_C_AUX_P

BI

MXM_DP_C_AUX_N

107 91

BI

107 91

BI

DP_MUX_AUXCH_P
DP_MUX_AUXCH_N

107 84

NO_TEST
NO_TEST

NC
NC

NOSTUFF

C9248
10% 16V
C9249
10% 16V

1

X5R
1

1/16W

0.1uF

2

0.1uF

2

X5R

402

0

2 DP_EQLZ_ADDR
MF-LF 402

61
60
58
57
55
54
52
51

NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST
NO_TEST

TMDS_CH0P
TMDS_CH0N
TMDS_CH1P
TMDS_CH1N
TMDS_CH2P
TMDS_CH2N

43
42
46
45
49
48

NC
NC
NC
NC
NC
NC

TMDS_CLKN 39
TMDS_CLKP 40

NC
NC

DP_INT_LINK_P<0>
DP_INT_LINK_N<0>
DP_INT_LINK_P<1>
DP_INT_LINK_N<1>
DP_INT_LINK_P<2>
DP_INT_LINK_N<2>
DP_INT_LINK_P<3>
DP_INT_LINK_N<3>

OUT

107 90

OUT

107 90

OUT

107 90

OUT

107 90

OUT

107 90

OUT

107 90

OUT

107 90

OUT

107 90

C

92

see below
NO_TEST DP_EQLZ_AUXCH_P
NO_TEST DP_EQLZ_AUXCH_N

BI
BI

92
107
92 107

2

20%
6.3V
X5R-CERM
402

To Internal display
DP_AUXP_SCL 32
DP_AUXN_SDA 33

DP_INT_AUXCH_P
DP_INT_AUXCH_N

NO_TEST
NO_TEST

BI

92 107 90

BI

92 107 90

25 IN2_AUXP_SCL
26 IN2_AUXN_SDA

5%
IN

1

DP_EQLZ_EXTC

DP_AC_AUXP 30
DP_AC_AUXN 31

34 TMDS_SCL
35 TMDS_SDA

28 IN1_AUXP_SCL
29 IN1_AUXN_SDA

NO_TEST
107 MXM_DP_C_AUX_C_N
NO_TEST

NO_TEST
NO_TEST

90

C9212
CEXT 1

INT_PD
66 SW/I2C_ADDR

92 107 MXM_DP_C_AUX_C_P

402

R9281 1
From Internal display

IN2_D0P
IN2_D0N
IN2_D1P
IN2_D1N
IN2_D2P
IN2_D2N
IN2_D3P
IN2_D3N
IN2_PEQ/SCL_CTL

DP_D0P
DP_D0N
DP_D1P
DP_D1N
DP_D2P
DP_D2N
DP_D3P
DP_D3N

4.7UF

=PP3V3_S0_DP
5%

From iMac GPU

PS8325
QFN
IN1_D0P
IN1_D0N
IN1_D1P
IN1_D1N
CRITICAL
IN1_D2P
IN1_D2N
IN1_D3P
IN1_D3N
IN1_PEQ/SDA_CTL

70 REXT

DP_EQLZ_EXTR

MF-LF 402

R9280 1
BI

Note: INT_PD = Internal Pulldown
on this pin of >=100 kOhms

64 MODE0
65 MODE1
69 MODE2

DP_EQLZ_MODE0
DP_EQLZ_MODE1
DP_EQLZ_MODE2

107 84

DisplayPort
Equalizer & MUX 2

C9204

0.1UF

VDD

402

5%
1/16W
MF-LF
402 2

B

1

C9203

U9200

52

C

20%
10V
CERM
402

402

0.1uF
X5R

From external input
via MUX 1

0.1UF

402

0.1uF
X5R

16V

107 MXM_DP_C_ML_C_N<0>

402

0.1uF
X5R

2

NO_TEST

1

C9201

20%
10V
CERM
402

402

0.1uF
X5R

1

2

107 MXM_DP_C_ML_C_P<0>

402

1

0.1UF

4
22
38
47
62

From iMac GPU

107 84

C9200

To Internal display

92 91 90 87 95 6

1/16W

1M

2

DP_EQLZ_CADET

MF-LF 402

INT_PDIN1_CADET 7
INT_PDIN2_CADET 16

56 DP_CADET
53 DP_HPD INT_PD

DP_HPD_INT

NC 41 TMDS_HPD INT_PD

NC
NC

IN1_HPDX 10

MXM_DP_C_HPD

OUT

84

TO IMAC GPU

IN2_HPDX 19

DP_MUX_HPD

OUT

91

TO EXTERNAL SOURCE VIA MUX1

B

NC 37 TMDS_PC0
NC 44 TMDS_PC1

=PP3V3_S0_DP

13
27
36
50
63
72

Pulls for AUX_CH
from DisplayPort Mux #2

THRM_PAD
73

NC 71 PIO INT_PD
NC 59 PDINT_PD GND

6 95 87 90 91 92

R92121
100K
1%
1/16W
MF-LF
402 2

AC caps for EQ AUX interception
MXM_DP_C_AUX_C_N

92 107

MXM_DP_C_AUX_C_P

92 107

107 92

BI

DP_EQLZ_AUXCH_P

NO_TEST

90 107 92

BI

DP_INT_AUXCH_P

NO_TEST

107 92

BI

DP_EQLZ_AUXCH_N

NO_TEST

90 107 92

BI

DP_INT_AUXCH_N

NO_TEST

C9290
10%

1

2

16V

0.1uF
X5R

402

R92131

A

100K

1%
1/16W
MF-LF
402 2

SYNC_MASTER=MASTER

C9291
10% 16V

1

2

X5R

SYNC_DATE=N/A

A

PAGE TITLE

0.1uF

BIDIVI DP MUX2

402

DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

92 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

93 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

94 6

6

5

4

3

2

1

=PP3V3_S0_DPCONN

L9400

CRITICAL

400-OHM-EMI

C9480

1

1

10UF

20%
2 6.3V
X5R
603

D

U9400

C9481
0.1UF

20%
2 10V
CERM
402

PP3V3_S0_DPFUSE

5 IN

TPS2051B
SOT23
OUT 1

4 EN

OC* 3

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

73 9

IN

PP3V3_S0_DPPWR

2

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

SM-1

94 6

TP_DP_OC

GND
2

CRITICAL

1

=PP3V3_S0_DPCONN

D

CRITICAL
1

C9485

1

10UF

1

20%
2 6.3V
X5R
603

0.1UF

C9400

8
CRITICAL
VCC

20%
2 10V
CERM
402

0.01UF
20%
50V
CERM
603

2

PM_SLPS3_BUF1_L

C9450
U9450

D9410
RCLAMP0524P
95

SLP2510P8

IN

1
7

DP_SRC_AUX_TERM_EN

5
3
IO
NC

20

1

4
IN

107 91

IN

12-OHM-100MA
TCM1210-4SM
SYM_VER-2

3

1%
1/16W
MF-LF
402

C
IO
NC

IO
NC

1

J9400

10

MDP-K22

3

R9421
100K

2

2

R9406
1
2

1%
1/16W
MF-LF
402

0

C

FL9403
12-OHM-100MA
TCM1210-4SM
4

1

SYM_VER-2

F-ANG-TH1

GND

9

1

100K

APPLE PART NO 514-0686
2

MIN_LINE_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.10 MM
VOLTAGE=0V

R9420 1

0

SLP2510P8

R9402
1
2

CRITICAL

0

3
1

NOSTUFF

NO_TEST
NO_TEST

FL9401
12-OHM-100MA

3

107 DP_ML_CONN_P<0>

5

107 DP_ML_CONN_N<0>

7

TCM1210-4SM
IN

6

2

R9401
1
2

RCLAMP0524P

107 91

2Z

1

NOSTUFF

D9410

IN

2

4

MIN_LINE_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.10 MM
VOLTAGE=3.3V

DP_EXT_LINK_P<0>
DP_EXT_LINK_N<0>
CRITICAL

107 91

2Y
2E

1Z

GND_DPAUX

R9400

NOSTUFF

FL9400
107 91

SOT996-2

GND

7

GND
3

NX3L2G66GD

4

PP3V3_S0_DPAUX

IO
6 NC
5

1Y
1E

4

DP_EXT_LINK_P<1>
DP_EXT_LINK_N<1>

1

SYM_VER-2

9

NO_TEST107 DP_ML_CONN_P<1>
NO_TEST 107 DP_ML_CONN_N<1>
3

11

2

13

NOSTUFF

NO_TEST
NO_TEST

R9403
1
2

107 DP_ML_CONN_P<2>

15

107 DP_ML_CONN_N<2>

17

0

19

GND
ML_LANE0P
ML_LANE0N
GND
ML_LANE1P
ML_LANE1N
GND
ML_LANE2P
ML_LANE2N
RETURN

HPD
CONFIG1
CONFIG2
GND
ML_LANE3P

2

10

107 DP_ML_CONN_P<3>

ML_LANE3N

12

107 DP_ML_CONN_N<3>

GND
AUX_CHP
AUX_CHN
DP_PWR

2

NOSTUFF

4
6

HDMI_CEC

R9407

8

1

20

DP_EXT_LINK_P<3> IN
DP_EXT_LINK_N<3> IN

NO_TEST
NO_TEST

16

DP_EXT_AUXCH_P
DP_EXT_AUXCH_N

18

91 107 95

20

CRITICAL

22

21

1

FL9402
12-OHM-100MA
4
IN

107 91

IN

RCLAMP0524P

2

SLP2510P8

5%
1/16W
MF-LF
402

5
6

1

DP_EXT_LINK_P<2>
DP_EXT_LINK_N<2>

IO
NC

IO
NC

4
7

GND

107 91

SYM_VER-2

D9411

R9425
1M

0

TCM1210-4SM

91 107

91 107 95

SHIELD PINS

R9404
1
2

91 107

14

B

3

2

NOSTUFF

RCLAMP0504F

0

D9411

SC70-6-1

RCLAMP0524P

6

SLP2510P8

91

OUT

DP_CA_DET

1

2
2

IO
NC

IO
NC

3

DP_HPD_EXT

IN

91 95

5

1

R94221

10

1M

GND

9

B

NOSTUFF

D9400

R9405
1
2

CRITICAL

3

CRITICAL

5%
1/16W
MF-LF
402

NOSTUFF

4
3

2

A

SYNC_MASTER=MARKVIDEO

SYNC_DATE=03/12/2009

A

PAGE TITLE

Display: Ext DP Connector
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

94 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

4
3
2
External AUX Channel and HPD Buffers & filters

PANEL/BACKLIGHT CONTROL MUX
95 92 91 90 87 6

92 91 90 87 95 6

=PP3V3_S0_DP

=PP3V3_S0_DP
CRITICAL
6

C9550

1

VCC

0.1UF
14
1

BIDIVI_AUX_TERM_EN

IN

7

D
91 95 49

74LVC14
2

14

U9540

20%
10V
CERM 2
402

U9500
95 49

NX3L1G66
SOT886

BIDIVI_AUX_TERM_EN_L
95

5 TC7SZ08AFEAPE

TSSOP-HF

2

DP_SINK_AUX_TERM_EN

SOT665

A

U9550Y

1

DPMUX_VIDEO_IN_SEL

IN

BIDIVI_BKL_MUX_SEL 95

4

4

E

2

Z

1

C9500
0.1UF

92 91 90 87 95 6

20%
10V
2 CERM
402

1

Y

1

NC

5

GND
3

U9510

5

16

PP3V3_S0_DPAUXP_SINK
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.10 MM

U9522

NOSTUFF

R9523
0 2

95

1%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

95 49

IN

95 85

IN

95 49

IN

85

IN

95 49

IN

85

IN

107 94 91

DP_EXT_AUXCH_P

74LVC157A

1 S
15 E*

BIDIVI_BKL_MUX_SEL

3
2
6
5
10
11
13
14

BIDIVI_BKL_PWM
MXM_PNL_BL_PWM
BIDIVI_BKL_ON
MXM_PNL_BL_EN
BIDIVI_PNL_PWR_EN
MXM_PNL_PWR_EN

6

1K

1

5%
1/16W
MF-LF
402

2

1Y
2Y
3Y
4Y

4
7
9
12

BACKLIGHT_PWM
LCD_BKL_ON_MUX
LCD_PANEL_PWR

OUT

90

OUT

90

OUT

90

92 91 90 87 95 6

92 91 90 87 95 6

3

17

8

U9510

3

DP_EXT_AUXCH_N

U9500

R9505

4

1

DP_AUXN_L

1K

2

7

C9503

1%
1/16W
MF
402 2

3.3K 2

AUXCH_N_STATE

49 95

C

5%
1/16W
MF-LF
402

1

PLACE NEAR U6201

92 91 90 87 95 6
MUX
OUTPUT

S

GND

2

SELECTOR

6

1 I1
3 I0

Y 4

1

D9503
SOT23

SOT886

5

0

1

TSSOP-HF

10%
6.3V
CERM 2
402

AUD_SPDIF_IN_CODEC

OUT

1

=PP3V3_S0_DP

C9562

92 91 90 87 95 6

20%
2 10V
CERM
402

PP3V3_S0_DP_D
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.10 MM

BAT54XG

3

U9520

1

DP_HPD_EXT

6

DP_HPD_EXT_L

2

1M
MUX_CNTRL

1

9

DP_HPD_PULS_EAT_L

8

C9504

R9509
1

14
7

TSSOP-HF

1

3.3K 2

SMC_DP_HPD

49 95

5%
1/16W
MF-LF
402

1UF

5%
1/16W
MF-LF
402 2

67

74LVC14

14

4.7K 2
5%
1/16W
MF-LF
402

1

R9507

U9500

R9508

SOT886

2

1

BAT54XG
5

94 91

=PP3V3_S0_DP

D9502
SOT23

0.1UF

3

62

R9542
0 2
1

1

10 AUXCH_N_R

14

1UF

NOSTUFFR9541
AUD_MUX_CNTRL

11

DP_AUXN_DLY_L

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

IN

49 95

R9506

74LVC14

14

2

74AUP2G14GM

62

AUXCH_P_STATE

5%
1/16W
MF-LF
402

=PP3V3_S0_DP

SPDIF_DP_AUDIO_OUT
AUD_SPDIF_IN

BIDIVI_AUDIO_MUX_SEL

3.3K 2

1

SOT886

VCC

IN

1

TSSOP-HF

=PP3V3_S0_DP

BAT54XG

74AUP2G14GM
107 94 91

U9524
74LVC1G157

95 49

12 AUXCH_P_R

D9501
SOT23
5

DisplayPort
AUDIO MUX

IN

7

R9503

74LVC14

=PP3V3_S0_DP

4.75M

IN

14

1%
1/16W
MF
402 2

R95211

90

13

DP_AUXP_DLY_L

4.75M

1I1
1I0
2I1
2I0
3I1
3I0
4I1
4I0

C

103 66

U9500
14

2

R95201

DHVQFN

THM
GND PAD

92 91 90 87 95 6

10%
6.3V 2
CERM
402

R9502

DP_AUXP_L

499K 2
1

VCC

1

1

D

1

1UF

BAT54XG

74AUP2G14GM

R9543

C9501

3

SOT886

=PP3V3_S0_DP

=PP3V3_S0_DP

D9500
SOT23

B

3

92 91 90 87 95 6

1

10%
6.3V
CERM 2
402

HPD_FILT

OUT

95

5%
1/16W
MF-LF
402

B

B

BiDiVi MUX Enable
92 91 90 87 95 6

=PP3V3_S0_DP

92 91 90 87 95 6

8
91 95 49

DPMUX_VIDEO_IN_SEL 7

IN

U9501
74LVC2G32

92 91 90 87 95 6

SOT902
1
DPMUX1_OROUT_L

A

Y

95

IN

AUX Bias Enable

6

HPD_FILT

R9511
0 2
1

4

1

C9560
0.1UF

DPMUX1_ENABLE

OUT

20%
10V
2 CERM
402

91

U9500

5%
1/16W
MF-LF
402

B

=PP3V3_S0_DP

=PP3V3_S0_DP

14
91 95 49

IN

5

DPMUX_VIDEO_IN_SEL

74LVC14
6

14
7

8 74LVC2G08

DPMUX_VIDEO_IN_SEL_L

3

SOT902

A

U9502Y 5
2

TSSOP-HF

B

08

DP_SRC_AUX_TERM_EN OUT

94

enables 100k dp aux source termination

4
92 91 90 87 95 6

=PP3V3_S0_DP

*Some inputs listed below come up as outputs driven low under the SMC flasher
Series R should prevent any issues on the inputs
Ouptuts are OK as low by default

1

0.1UF

20%
10V
2 CERM
402

SMC Signals for BiDiVi
8

Inputs

A

90

VIDEO_ON

IN

1

3.3K
5%
1/16W
MF-LF
402

SMC_VIDEO_ON

2

Outputs

SMC

R9510
49

95

Default Values
S5/S3

C9561

IN

3

HPD_FILT

U9501
74LVC2G32
SOT902
5

A

Y

S0
95 49

P21*

P27

DPMUX_VIDEO_IN_SEL

0

0

OUT

IN

2

BIDIVI_AUX_TERM_EN

49 91 95

95 49

IN

AUXCH_P_STATE

P22*

PF3

BIDIVI_AUX_TERM_EN

0

0

OUT

49 95

95 49

IN

AUXCH_N_STATE

P23*

PF4

BIDIVI_PNL_PWR_EN

0

0

OUT

49 95

AUX_TERM_OR_OUT

B

4

SYNC_MASTER=MARKVIDEO
=PP3V3_S0_DP

95 49

SMC_DP_HPD

IN

P25*

PF6

BIDIVI_BKL_ON

X

X

OUT

49 95

PF7

BIDIVI_BKL_PWM

X

X

OUT

49 95

IN

MXM_PNL_BL_PWM

R9540
3.3K 2

1

P26

BIDIVI_AUDIO_MUX_SEL

0

0

OUT

49 95

8 74LVC2G08
7

NOSTUFF
95 85

SYNC_DATE=03/12/2009

A

PAGE TITLE

SMC_PNL_BL_PWM

49 50

PG0

IN

Apple Inc.

SOT902

6

DPMUX_VIDEO_IN_SEL

DRAWING NUMBER

enables weak sink-like aux termination
so that one bi-directional system can find the other

B

051-7863

DP_SINK_AUX_TERM_EN

OUT

08

95

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

4

SIZE

D

REVISION

A.0.0

R

A

U9502Y 1
91 95 49

5%
1/16W
MF-LF
402

Display: BiDiVi Support

6 95 87 90 91 92

BRANCH

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8

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D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

96 OF 110
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8

7

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5

4

3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

97 OF 110
SHEET

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7

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5

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3

2

1

D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

98 OF 110
SHEET

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D

D

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=12/02/2008

A

PAGE TITLE

BLANK PAGE
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

99 OF 110
SHEET

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8

7

6

5

4

FSB (Front-Side Bus) Constraints

3

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

1

CPU / FSB Net Properties
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

2

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

NET_TYPE

DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

FSB_50S

*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

Group 0
TABLE_PHYSICAL_RULE_ITEM

FSB_42S

*

=42_OHM_SE

=42_OHM_SE

=42_OHM_SE

=42_OHM_SE

=STANDARD

=STANDARD

FSB_DSTB_42S

*

=42_OHM_SE

=42_OHM_SE

=42_OHM_SE

=42_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

FSB_DATA

FSB_42S

FSB_DATA

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB

FSB_42S

FSB_DATA

FSB_42S

FSB_DATA

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB

FSB_42S

FSB_DATA

FSB_42S

FSB_DATA

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB

FSB_42S

FSB_DATA

FSB_42S

FSB_DATA

FSB_DSTB_42S

FSB_DSTB

FSB_DSTB_42S

FSB_DSTB

FSB_50S

FSB_ADDR

FSB_50S

FSB_ADDR

FSB_50S

FSB_ADSTB

FSB_50S

FSB_ADDR

FSB_50S

FSB_ADSTB

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

FSB_50S

FSB_1X

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_8MIL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_8MIL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

MCP_50S

MCP_FSB_COMP

MCP_50S

MCP_FSB_COMP

MCP_50S

MCP_FSB_COMP

MCP_50S

MCP_FSB_COMP

CLK_FSB_100D

CLK_FSB

CLK_FSB_100D

CLK_FSB

CLK_FSB_100D

CLK_FSB

CLK_FSB_100D

CLK_FSB

CLK_FSB_100D

CLK_FSB

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_P
FSB_CLK_MCP_N

CPU_50S

CPU_AGTL

CPU_IERR_L

CPU_50S

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_GTLREF0
CPU_GTLREF1

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

TABLE_PHYSICAL_RULE_ITEM

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

D

FSB_DATA

*

=2x_DIELECTRIC

?

FSB_DSTB

*

=3x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

FSB_DATA

TOP,BOTTOM

=4x_DIELECTRIC

?

FSB_DSTB

TOP,BOTTOM

=5x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

FSB_ADDR

*

=STANDARD

?

FSB_ADSTB

*

=2x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

FSB_ADDR

TOP,BOTTOM

=3x_DIELECTRIC

?

FSB_ADSTB

TOP,BOTTOM

=4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

FSB_1X

*

=STANDARD

FSB 4X Signal Groups

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

FSB_1X

TOP,BOTTOM

=3x_DIELECTRIC

?

All 2x/1x/Async FSB signals with impedance requirements are 50-ohm single-ended.
All 4x FSB signals with impedance requirements are 42-ohm single-ended.

Group 1

Group 2

Group 3

FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

Group 0

FSB 2X
Signals

FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 90 ps. (Tighther than MCP79)
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

Group 1

Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.

FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>

FSB_42S

FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>

FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>

FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>

FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>
FSB_A_L<35..17>
FSB_ADSTB_L<1>

10 14
10 14
10 14
10 14

10 14
10 14

D

10 14
10 14

10 14
10 14
10 14
10 14

10 14
10 14
10 14
10 14

10 14
10 14
10 14

10 14
10 14

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

FSB 1X Signals

C

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

CPU_50S

*

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

*

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

0.175 MM

0.175 MM

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

CPU_AGTL

*

=STANDARD

?

CPU_8MIL

*

0.2 MM

?

TABLE_SPACING_RULE_ITEM

CPU_AGTL

TOP,BOTTOM

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

*

0.6 MM

?
TABLE_SPACING_RULE_ITEM

CPU_GTLREF

*

0.6 MM

SR DG recommends at least 25 mils, >50 mils preferred

?
TABLE_SPACING_RULE_ITEM

CPU_ITP

*

=2:1_SPACING

?
TABLE_SPACING_RULE_ITEM

CPU_VCCSENSE

*

0.6 MM

?

MOST CPU SIGNALS WITH IMPEDANCE REQUIREMENTS ARE 50-OHM SINGLE-ENDED.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

B

10 14
10 14

C

14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 14
10 13 14
10 14
10 14

?

TABLE_SPACING_RULE_ITEM

CPU_COMP

FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L

MCP FSB COMP Signal Constraints

CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L

10 14
11 14
10 14
10 14
10 14
10 14
10 14
11 14 50
11 13 14
10 14
10 14
11 14 50
11 14
11 14

B

11 14

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

MCP_50S

*

SPACING_RULE_SET

LAYER

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

14
14
14
14

TABLE_SPACING_RULE_ITEM

MCP_FSB_COMP

*

0.2 MM

?

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

FSB Clock Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

10 14
10 14
13 14
13 14
14
14

TABLE_PHYSICAL_RULE_ITEM

CLK_FSB_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=3x_DIELECTRIC

?

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=4x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

CLK_FSB

*

10

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

CLK_FSB

TOP,BOTTOM

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

A

CPU_27P4S

CPU_COMP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

CPU_50S

CPU_8MIL

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_COMP<8>
CPU_COMP<3>
CPU_COMP<2>
CPU_COMP<1>
CPU_COMP<0>
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TCK
CPU_XDP_TRST_L
CPU_XDP_BPM_L<5..0>
CPU_XDP_BPMB<3..0>
XDP_CPURST_L
CPU_VID<7..0>
CPU_VCC_PKG_SENSE_P
CPU_VCC_PKG_SENSE_N
VR_CPU_VSNS_R_P
VR_CPU_VSNS_R_N

10 11 29
10 11 29

11
11
11
11
11
11 13
11 13
11 13
11 13

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

CPU/FSB Constraints

11 13

DRAWING NUMBER
11 13

Apple Inc.

13
12 71
12 71

A

PAGE TITLE

11 13

051-7863

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

12 71
71
71

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PAGE

100 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

Memory Bus Constraints

4

LAYER

ALLOW ROUTE
ON LAYER?

2

1

Memory Net Properties
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

3

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

NET_TYPE

DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

MEM_40S

*

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD
MEM_70D_VDD

MEM_CLK

MEM_70D_VDD

MEM_CLK

MEM_70D_VDD

MEM_CLK

MEM_70D_VDD

MEM_CLK

MEM_A_CLK_P<1..0>
MEM_A_CLK_N<1..0>
MEM_A_CLK_P<4..3>
MEM_A_CLK_N<4..3>

TABLE_PHYSICAL_RULE_ITEM

MEM_40S_VDD

=40_OHM_SE

*

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD
TABLE_PHYSICAL_RULE_ITEM

MEM_70D

*

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

15 33
15 33
16 33
16 33

TABLE_PHYSICAL_RULE_ITEM

MEM_70D_VDD

*

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF
MEM_40S_VDD

MEM_CTRL

MEM_40S_VDD

MEM_CTRL

MEM_40S_VDD

MEM_CTRL

MEM_40S_VDD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

D

LAYER

LINE-TO-LINE SPACING

WEIGHT

15 16 31
15 16 31
15 16 31

D

TABLE_SPACING_RULE_ITEM

MEM_CLK2MEM

*

=4:1_SPACING

?

MEM_CTRL2CTRL

*

=2:1_SPACING

?

MEM_CTRL2MEM

*

=2.5:1_SPACING

?

TABLE_SPACING_RULE_ITEM

MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

TABLE_SPACING_RULE_ITEM

MEM_CMD2CMD

*

=1.5:1_SPACING

?

MEM_CMD2MEM

*

=3:1_SPACING

?

MEM_40S_VDD

MEM_CMD

TABLE_SPACING_RULE_ITEM

MEM_40S_VDD

MEM_CMD

TABLE_SPACING_RULE_ITEM

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_70D

MEM_DQS

MEM_A_DQ<7..0>
MEM_A_DM<0>

15 31
15 31
15 31
15 31
15 31

15 33
15 33

TABLE_SPACING_RULE_ITEM

MEM_DATA2DATA

*

=1.5:1_SPACING

?

MEM_A_DQ<15..8>
MEM_A_DM<1>

TABLE_SPACING_RULE_ITEM

MEM_DATA2MEM

*

=3:1_SPACING

?

MEM_DQS2MEM

*

=3:1_SPACING

?

MEM_2OTHER

*

=3:1_SPACING

?

15 33
15 33

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

MEM_CLK

*

MEM_CLK2MEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CMD

MEM_CLK

*

MEM_CMD2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

*

MEM_CLK2MEM

MEM_CLK

MEM_CMD

*

MEM_CLK2MEM

MEM_CLK

MEM_DATA

*

MEM_CLK2MEM

MEM_CMD

MEM_CTRL

*

MEM_CMD2MEM

MEM_CMD

MEM_CMD

*

MEM_CMD2CMD

MEM_CMD

MEM_DATA

*

MEM_CMD2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

*

MEM_CLK2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_DQS

*

MEM_CMD2MEM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DATA

MEM_CLK

*

MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_HEAD

C

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CTRL

MEM_CLK

*

MEM_CTRL2MEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

*

MEM_CTRL2CTRL

MEM_CTRL

MEM_CMD

*

MEM_CTRL2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

MEM_CTRL

*

MEM_DATA2MEM

MEM_DATA

MEM_CMD

*

MEM_DATA2MEM

MEM_DQS
MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS
MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D_VDD

MEM_CLK

MEM_70D_VDD

MEM_CLK

MEM_70D_VDD

MEM_CLK

DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

MEM_70D_VDD

MEM_CLK

MEM_40S_VDD

MEM_CTRL

DDR3:

MEM_DATA

*

MEM_CTRL2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

*

MEM_DATA

MEM_DQS

*

MEM_CTRL2MEM

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DQS

*

MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_CLK

*

MEM_DQS2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_CTRL

*

MEM_DQS2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_CMD

*

MEM_DQS2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_DATA

*

MEM_DQS2MEM

*

MEM_DQS

MEM_DATA

MEM_DQS2MEM

15 33

15 33
15 33

15 33
15 33

15 33
15 33

15 33
15 33

15 33

C

15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33

TABLE_SPACING_ASSIGNMENT_ITEM

*

*

MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

MEM_A_DQ<63..56>
MEM_A_DM<7>

MEM_DATA2DATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_A_DQ<55..48>
MEM_A_DM<6>

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Memory Net Properties

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

*

*

MEM_2OTHER

Need to support MEM_*-style wildcards!

DDR2:

B

MEM_70D
MEM_70D

MEM_70D

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

MEM_A_DQ<47..40>
MEM_A_DM<5>

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

15 33

15 33

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_A_DQ<39..32>
MEM_A_DM<4>

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

MEM_A_DQ<31..24>
MEM_A_DM<3>

15 33

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

MEM_A_DQ<23..16>
MEM_A_DM<2>

MEM_40S_VDD

DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

MCP MEM COMP Signal Constraints

MEM_B_CLK_P<1..0>
MEM_B_CLK_N<1..0>
MEM_B_CLK_P<4..3>
MEM_B_CLK_N<4..3>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>

MEM_CTRL

MEM_40S_VDD

MEM_CTRL

MEM_40S_VDD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_40S_VDD

MEM_CMD

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_40S

MEM_DATA

MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ<7..0>
MEM_B_DM<0>
MEM_B_DQ<15..8>
MEM_B_DM<1>
MEM_B_DQ<23..16>
MEM_B_DM<2>
MEM_B_DQ<31..24>
MEM_B_DM<3>

15 33

NET_TYPE
15 33

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

16 33
16 33

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

15 16 32
15 16 32
15 16 32

MEM_70D

MEM_DQS

15 32

MEM_70D

MEM_DQS

15 32

MEM_70D

MEM_DQS

15 32

MEM_70D

MEM_DQS

15 32

MEM_70D

MEM_DQS

MEM_70D

15 32

MEM_DQS

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

15 33
15 33

MEM_70D

MEM_DQS

15 33

MEM_70D

MEM_DQS

15 33

MEM_70D

MEM_DQS

MEM_70D

MEM_DQS

MCP_MEM_COMP

MCP_MEM_COMP

MCP_MEM_COMP

MCP_MEM_COMP

15 33
15 33
15 33
15 33
15 33
15 33

B

15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33
15 33

15 33
15 33

MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND

16
16

15 33
15 33

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MCP_MEM_COMP

*

Y

0.175 MM

0.175 MM

=STANDARD

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

*

0.2 MM

MEM_B_DQ<47..40>
MEM_B_DM<5>

15 33
15 33

15 33
15 33

WEIGHT
TABLE_SPACING_RULE_ITEM

MCP_MEM_COMP

MEM_B_DQ<39..32>
MEM_B_DM<4>

MEM_B_DQ<55..48>
MEM_B_DM<6>

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MEM_B_DQ<63..56>
MEM_B_DM<7>

15 33
15 33

15 33
15 33

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Memory Constraints
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

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7

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PCI-Express
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCIE_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=3X_DIELECTRIC

?

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=4X_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

PCIE

*

PCIE GRAPHICS

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

D

*

0.5 MM

?

MCP_PEX_COMP

*

0.2 MM

?

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

PCIE_90D

PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

SATA_100D

SATA

MCP_50S

SATA_TERMP

TABLE_SPACING_RULE_ITEM

PCIE

TOP,BOTTOM

TABLE_SPACING_RULE_ITEM

CLK_PCIE

PCIE_90D

TABLE_SPACING_RULE_ITEM

SATA Interface Constraints
LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SATA_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

SATA

*

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

SATA

TOP,BOTTOM

=3x_DIELECTRIC

?

TABLE_SPACING_RULE_ITEM

SATA_TERMP

*

0.2 MM

9 86
9 86
9 86
9 86
84 86
84 86

D

84 86
84 86

PCIE I/O
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

SPACING_RULE_SET

PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
MXM_PCIE_R2D_P<15..0>
MXM_PCIE_R2D_N<15..0>
MXM_PCIE_D2R_P<15..0>
MXM_PCIE_D2R_N<15..0>

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_L_P
PCIE_MINI_R2D_L_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N

34
34
17 34
17 34
34
34
17 34
17 34
41
41
17 41
17 41
17 41
17 41
41
41

PCIE REF CLOCKS

C

GPU_CLK100M_PCIE_P
GPU_CLK100M_PCIE_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_MINI_CON_P
PCIE_CLK100M_MINI_CON_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

9 87
9 87

C

17 34
17 34
34
34
17 41
17 41

SATA
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
MCP_SATA_TERMP

20 45
20 45
45 110
45 110
20 45
20 45
45 110
45 110
20 45
20 45
45 110
45 110
20 45
20 45
45 110
45 110
20

B

B
MISC

MCP_50S

MCP_PEX_COMP

MCP_DV_COMP

MCP_PEX_COMP

MCP_50S

MCP_PEX_COMP

MCP_PEX_CLK_COMP
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
PM_SLP_S3_L
PM_SLP_S4_L

A

17
18 26
18 26

9 21
21 70

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP Constraints 1
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

102 OF 110
SHEET

 OF 

8

7

6

5

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3

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8

7

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5

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PCI Bus Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCI_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

CLK_PCI_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

SPACING_RULE_SET

LAYER

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL

SPACING

PCI_55S

PCI

PCI_55S

PCI

CLK_PCI_55S

CLK_PCI

CLK_PCI_55S

CLK_PCI

LPC_55S

LPC

LPC_55S

LPC

LPC_55S

LPC

LPC_55S

LPC

LPC_55S

LPC

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

PCI

*

=STANDARD

?

CLK_PCI

*

0.2 MM

?

PCI_REQ0_L
PCI_REQ1_L
PCI_CLK33M_MCP_R
PCI_CLK33M_MCP

19
19
19
19

TABLE_SPACING_RULE_ITEM

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

LPC Bus Constraints

LPC_AD<3..0>
LPC_AD_R<3..0>
LPC_FRAME_L
LPC_FRAME_R_L

19 49 51

D

19
19 49 51
19

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

LPC_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

CLK_LPC_55S

CLK_LPC

CLK_LPC_55S

CLK_LPC

CLK_LPC_55S

CLK_LPC

CLK_LPC_55S

CLK_LPC

CLK_LPC_55S

CLK_LPC

TABLE_PHYSICAL_RULE_ITEM

CLK_LPC_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
MCP_USB_RBIAS
TABLE_SPACING_RULE_ITEM

LPC

*

0.15 MM

?
TABLE_SPACING_RULE_ITEM

CLK_LPC

*

0.2 MM

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

USB_90D

USB

MCP_50S

SPI

MCP_50S

SPI

MCP_50S

SPI

MCP_50S

SPI

MCP_50S

SPI

MCP_50S

SPI

MCP_50S

SPI

MCP_50S

SPI

HDA_55S

HDA

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

C

USB_90D

USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MCP_USB_RBIAS

*

=STANDARD

0.2 MM

0.2 MM

=STANDARD

=STANDARD

=STANDARD

USB_90D

*

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

USB

*

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

?

USB

TOP,BOTTOM

=4x_DIELECTRIC

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

SMBus Interface Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

SMB_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

LPC_RESET_L
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
MCP_USB_RBIAS_GND
USB_EXTA_P
USB_EXTA_N
USB_PORT0_P
USB_PORT0_N
USB_EXTB_P
USB_EXTB_N
USB_PORT1_P
USB_PORT1_N
USB_EXTC_P
USB_EXTC_N
USB_PORT2_P
USB_PORT2_N
USB_EXTD_P
USB_EXTD_N
USB_D_MUXED_P
USB_D_MUXED_N
USB_PORT3_P
USB_PORT3_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_L_P
USB_CAMERA_L_N
USB_BT_P
USB_BT_N
USB_BT_L_P
USB_BT_L_N
USB_IR_P
USB_IR_N
USB_IR_L_P
USB_IR_L_N
USB_SDCARD_P
USB_SDCARD_N
USB_SDCARD_L_P
USB_SDCARD_L_N

9 19
9 19
9 49
9 51
9 21
9 49
20
20 46
20 46
46
46
20 46
20 46
46
46
20 46
20 46
46
46
20 46
20 46
46
46

C

46
46
20 47
20 47
47 110
47 110
20 47
20 47
47 110
47 110
20 47
20 47
47 110
47 110
20 47
20 47
47 110
47 110

TABLE_SPACING_RULE_ITEM

SMB

*

=2x_DIELECTRIC

?

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

HD Audio Interface Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

B

HDA_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

HDA

*

=2x_DIELECTRIC

?

MCP_HDA_COMP

*

0.2 MM

?

TABLE_SPACING_RULE_ITEM

MCP_HDA_COMP

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

HDA_55S

HDA

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

SPI_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

HDA
HDA

TABLE_SPACING_RULE_ITEM

SPI

*

0.2 MM

?
HDA

SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
HDA_BIT_CLK
MCP_HDA_PULLDN_COMP
HDA_BIT_CLK_R
HDA_RST_L
HDA_RST_R_L
HDA_SDOUT
HDA_SDOUT_R
HDA_SYNC
HDA_SYNC_R
HDA_SDIN0
AUD_SDI_R
AUD_SPDIF_IN
AUD_SPDIF_OUT
AUD_SPDIF_CHIP

21 51 61
61
21 51 61

B

61
21 51 61
61
21 51
51
21 62
21
21
21 62
21
21 62
21
21 62
21
21 62
62
9 66
62 66
62

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

A

CLK_MCP_XTAL

XTAL

CLK_MCP_XTAL

XTAL

CLK_MCP_XTAL

XTAL

CLK_MCP_XTAL

XTAL

MCP_CLK25M_XTALOUT
MCP_CLK25M_XTALIN
RTC_CLK32K_XTALOUT
RTC_CLK32K_XTALIN

XTAL Constraints

21 28
21 28
21 28
21 28

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

MCP Constraints 2

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

CLK_MCP_XTAL

*

=100_OHM_DIFF

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

DRAWING NUMBER

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

*

=4X_DIELECTRIC

?

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D

REVISION

A.0.0

R

TABLE_SPACING_RULE_ITEM

XTAL

051-7863
BRANCH

PAGE

103 OF 110
SHEET

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8

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6

5

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6

5

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MCP RGMII (Ethernet) Constraints
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MCP_MII_COMP

*

=STANDARD

0.2 MM

0.2 MM

=STANDARD

=STANDARD

=STANDARD

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

MCP_MII_COMP_VDD
MCP_MII_COMP_GND

MCP_MII_COMP
TABLE_PHYSICAL_RULE_ITEM

ENET_MII_55S

*

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

MCP_MII_COMP
ENET_MII_55S

MCP_BUF0_CLK

ENET_MII_55S

MCP_BUF0_CLK

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MII_55S

ENET_MII

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

ENET_MDI_100D

ENET_MDI

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1

18
18

18 38
37 38

TABLE_SPACING_RULE_ITEM

MCP_BUF0_CLK

*

=3:1_SPACING

?

ENET_MII

*

0.3 MM

?

TABLE_SPACING_RULE_ITEM

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

RTL8211CLGR (ETHERNET PHY) CONSTRAINTS
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

ENET_MDI_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

ENET_MDI

*

0.6 MM

?

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

ENET_MDIO
ENET_MDC
ENET_CLK125M_RXCLK
ENET_CLK125M_RXCLK_R
ENET_RXD<0>
ENET_RXD_R<0>
ENET_RXD<3..1>
ENET_RXD_R<3..1>
ENET_RX_CTRL
ENET_RXCTL_R
ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL
ENET_MDI_P<3..0>
ENET_MDI_N<3..0>
ENET_MDI_T_P<3..0>
ENET_MDI_T_N<3..0>

18 37
18 37

D

18 37
37
18 37
37
18 37
37
18 37
37
18 37
18 37
18 37
18 37
37 39
37 39
39
39

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

Ethernet Constraints
DRAWING NUMBER

Apple Inc.

051-7863

SIZE

D

REVISION

R

A.0.0

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

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6

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FIT;

1

8

7

6

5

FireWire Interface Constraints

4

3

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

1

FireWire Net Properties
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

2

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

NET_TYPE

DIFFPAIR NECK GAP
PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

TABLE_PHYSICAL_RULE_ITEM

FW_110D

*

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF
FW_110D

FW_TP

FW_110D

FW_TP

FW_110D

FW_TP

FW_110D

FW_TP

FW_110D

FW_TP

FW_110D

FW_TP

FW_110D

FW_TP

FW_110D

FW_TP

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

FW_TP

*

=3:1_SPACING

FW_PORT0_TPA_P
FW_PORT0_TPA_N
FW_PORT0_TPB_P
FW_PORT0_TPB_N

42 43
42 43
42 43
42 43

?

PORT 1 & 2 NOT USED

D

FW_P0_TPA_L_P
FW_P0_TPA_L_N
FW_P0_TPB_L_P
FW_P0_TPB_L_N

D

42
42
42
42

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

FireWire Constraints
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

105 OF 110
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8

7

6

5

4

3

2

1

SMC SMBus Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

SMBus Interface Constraints

SPACING

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

SMB_55S

SMB

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

SMB_55S

*

=55_OHM_SE

=55_OHM_SE

D

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

SMB

*

=2x_DIELECTRIC

?

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA

52
52
52
52
52
52
52
52

D

52 106
52 106
52 106
52 106
13 21 52
13 21 52

C

C

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

SMC Constraints
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

106 OF 110
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5

Digital Video Signal Constraints

4

3

2

1

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

ASSINGED IN CONT. MGR.

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

DP_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

0.08MM

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

MCP_DV_COMP

*

Y

0.5 MM

0.5 MM

=STANDARD

=STANDARD

=STANDARD

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

DISPLAYPORT

*

=3x_DIELECTRIC

?

D

TABLE_SPACING_RULE_ITEM

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MXM_DP_A_ML_P<3..0>
MXM_DP_A_ML_N<3..0>
MXM_DP_A_ML_C_P<3..0>
MXM_DP_A_ML_C_N<3..0>
MXM_DP_A_ML_EQ_P<3..0>
MXM_DP_A_ML_EQ_N<3..0>
MXM_DP_A_AUX_P
MXM_DP_A_AUX_N
MXM_DP_A_AUX_C_P
MXM_DP_A_AUX_C_N

84 91
84 91
91
91
91
91
84 91

D

84 91
91
91

TABLE_SPACING_ASSIGNMENT_ITEM

DISPLAYPORT

*

*

3:1_SPACING

DISPLAYPORT

POWER

*

PWR_P2MM

DISPLAYPORT

GND

*

GND_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

C

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

DP_100D

DISPLAYPORT

MCP_DV_COMP
MCP_DV_COMP

DP_EXT_LINK_P<3..0>
DP_EXT_LINK_N<3..0>
DP_EXT_LINK_C_P<3..0>
DP_EXT_LINK_C_N<3..0>
DP_EXT_AUXCH_P
DP_EXT_AUXCH_N
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>
MXM_DP_C_ML_P<3..0>
MXM_DP_C_ML_N<3..0>
MXM_DP_C_ML_C_P<3..0>
MXM_DP_C_ML_C_N<3..0>
MXM_DP_C_AUX_P
MXM_DP_C_AUX_N
MXM_DP_C_AUX_C_P
MXM_DP_C_AUX_C_N
DP_INT_LINK_P<3..0>
DP_INT_LINK_N<3..0>
DP_INT_LINK_CONN_P<3..0>
DP_INT_LINK_CONN_N<3..0>
DP_INT_AUXCH_P
DP_INT_AUXCH_N
DP_MUX_P<3..0>
DP_MUX_N<3..0>
DP_MUX_AUXCH_P
DP_MUX_AUXCH_N
DP_MUX_AUXCH_P
DP_MUX_AUXCH_N
DP_TX_EQ_AUXCH_P
DP_TX_EQ_AUXCH_N
DP_EQLZ_AUXCH_P
DP_EQLZ_AUXCH_N
MCP_HDMI_RSET
MCP_HDMI_VPROBE

91 94
91 94
91
91
91 94 95
91 94 95
94
94

84 92
84 92
92
92
84 92
84 92
92
92

92 90
92 90
90
90
92 90

C

92 90

91 92
91 92
91 92 107
91 92 107
91 92 107
91 92 107
91
91
92
92

18 26
18 26

B

B

A

SYNC_MASTER=MASTER

SYNC_DATE=N/A

A

PAGE TITLE

Graphics Constraints
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

107 OF 110
SHEET

 OF 

8

7

6

5

4

3

2

1

8

7

6

5

LAYER

LINE-TO-LINE SPACING

WEIGHT

=STANDARD

?

3

2

1

K50/K51 SPECIFIC NET PROPERTIES

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

4

NET_TYPE
TABLE_SPACING_RULE_ITEM

GND

*

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_SPACING_RULE_ITEM

PPDDR_MEM

*

=STANDARD

?

SWITCHNODE

=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
VR_CPU_SW1
VR_CPU_SW2
VR_CPU_SW3
1V8_SW
1V1S5_SW
PVTTS0_PHASE

SWITCHNODE

3V3S5_SW

PPDDR_MEM
PPDDR_MEM
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

SWITCHNODE

TABLE_SPACING_RULE_ITEM

GND_P2MM

*

0.20 MM

SWITCHNODE

1000
SWITCHNODE
TABLE_SPACING_RULE_ITEM

PWR_P2MM

*

0.20 MM

1000

SWITCHNODE

D

SWITCHNODE
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

GND

*

GND_P2MM

6 30 31
6 30 32
72
72
72
80

D

79
76
76

TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

GND

*

GND_P2MM

MEM_CTRL

GND

*

GND_P2MM

SWITCHNODE
THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

THERM_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

SNS_DIFF

THERMAL

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

GND

*

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

GND

*

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

PPDDR_MEM

*

PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

PPDDR_MEM

*

PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

PPDDR_MEM

*

PWR_P2MM

5VS3_SW
MCPCORES0_PHASE
SNS_T_DP1_DN6
SNS_T_DN1_DP6
SNS_T_DP2_DN3
SNS_T_DN2_DP3
CPU_THERMD_P
CPU_THERMD_N
SNS_T_DP4_DN5
SNS_T_DN4_DP5
MCP_THMDIODE_P
MCP_THMDIODE_N

73
74
55
55
55
55
11 55
11 55
55
55
21 55
21 55

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

PPDDR_MEM

*

PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

PPDDR_MEM

*

PWR_P2MM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MXM_PWRSRC_SENSOR_P
MXM_PWRSRC_SENSOR_N

53
53

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_FSB

TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE

*

GND

GND

*

GND_P2MM

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE

GND

*

GND_P2MM

SATA

GND

*

GND_P2MM

CPU_COMP

GND

*

GND_P2MM

CPU_GTLREF

GND

*

GND_P2MM

CPU_VCCSENSE

GND

*

GND_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

USB

GND

*

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

FSB_DSTB

C

GND

*

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

CLK_PCIE

PWR

*

PWR_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

THERMAL

*

*

4:1_SPACING
TABLE_SPACING_ASSIGNMENT_ITEM

SWITCHNODE

*

*

SWITCHNODE
TABLE_SPACING_ASSIGNMENT_ITEM

THERMAL

PWR

*

PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

B

THERMAL

GND

*

GND_P2MM

AUDIO

*

*

AUDIO

I210

THERMAL

I211

THERMAL

I212

THERMAL

I213

THERMAL

I214

THERMAL

I215

THERMAL

I216

THERMAL

I217

THERMAL

I218

THERMAL

I219

THERMAL

I220

THERMAL

I221

THERMAL

I222

THERMAL

I223

THERMAL

I230

THERMAL

I224

THERMAL

I225

THERMAL

I226

THERMAL

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

SENSE_1V5_S0_P
SENSE_1V5_S0_N
SNS_LCD_P
SNS_LCD_N
SNS_ODD_P
SNS_ODD_N
SNS_CPU_H_P
SNS_CPU_H_N
SNS_MCP_P
SNS_MCP_N
SNS_AMB_P
SNS_AMB_N
SNS_MXM_P
SNS_MXM_N

VR_CPU_ISNS1_P
VR_CPU_ISNS1_N
VR_CPU_ISNS1_R_P
VR_CPU_ISNS1_R_N
VR_CPU_ISNS2_P
VR_CPU_ISNS2_N
VR_CPU_ISNS2_R_P
VR_CPU_ISNS2_R_N
VR_CPU_ISNS3_P
VR_CPU_ISNS3_N
VR_CPU_ISNS3_R_P
VR_CPU_ISNS3_R_N
SMC_CPU_ISENSE
VR_CPU_IOUT
VR_ISNS_CPU_P
VR_ISNS_CPU_N
SNS_PS_CPU_ISNS

54
54
55 110

C

55 110
55 110
55 110
55
55
55
55

55 110
55 110
55
55

71 72
71 72
71
71
71 72
71 72
71
71
71 72
71 72
71
71

B

49 53
53 71
53
53
53

TABLE_PHYSICAL_ASSIGNMENT_ITEM

THERM_DIFF

*

1:1_DIFFPAIR
TABLE_PHYSICAL_ASSIGNMENT_ITEM

SNS_DIFF

*

1:1_DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

MEM_40S

TOP

OVERRIDE

OVERRIDE

OVERRIDE

0.1 MM

600 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MEM_40S_VDD

TOP

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.1 MM

600 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MEM_70D

TOP

OVERRIDE

OVERRIDE

0.1 MM

OVERRIDE

OVERRIDE

OVERRIDE

600 MIL

OVERRIDE

OVERRIDE

SMC_GPU_VSENSE
SMC_GPU_ISENSE

49 53
12 53

49 53
49 53

DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

OVERRIDE

SMC_CPU_VSENSE
CPU_VCC_SENSE

OVERRIDE

SMC_1V5_S0_ISENSE
SMC_1V5_S0_ISENSE_R
SMC_1V5_S0_VSENSE
SMC_MCP_CORE_ISENSE
SMC_MCP_CORE_VSENSE
MCPCORES0_IMON

50 54
54
50 54
50 54
50 54
54 74

TABLE_PHYSICAL_RULE_ITEM

PCIE_90D

TOP

OVERRIDE

OVERRIDE

USB_90D

TOP

OVERRIDE

OVERRIDE

MCP_DV_COMP

TOP

OVERRIDE

OVERRIDE

500 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

500 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.1 MM

500 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

THERMAL

OVERRIDE

I227

THERMAL

I228

THERMAL

I229

THERMAL

TABLE_PHYSICAL_RULE_ITEM

MCP_MEM_COMP

TOP

OVERRIDE

A

OVERRIDE

0.1 MM

OVERRIDE

OVERRIDE

OVERRIDE

500 MIL

OVERRIDE

OVERRIDE

11 55
55
14 55

OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

OVERRIDE

CPU_PECI_L
SMB_PECI_L
CPU_PECI_MCP

OVERRIDE

HDD_OOB_TEMP_FILT
HDD_OOB_TEMP
HDD_OOB_TEMP_R
SMC_HDD_OOB_TEMP

55
55
55
55

TABLE_PHYSICAL_RULE_ITEM

MCP_MII_COMP

TOP

OVERRIDE

OVERRIDE

MCP_USB_RBIAS

TOP

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.1 MM

500 MIL

OVERRIDE

OVERRIDE

0.1 MM

500 MIL

OVERRIDE

OVERRIDE

SYNC_MASTER=K22

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE
0.25 MM

250 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

SYNC_DATE=09/02/2009

K22/K23 SPECIFIC CONSTRAINTS
DRAWING NUMBER

TABLE_PHYSICAL_RULE_ITEM

MCP_DV_COMP

*

OVERRIDE

OVERRIDE

Apple Inc.

TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

BOTTOM

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.23 MM

100 MIL

OVERRIDE

OVERRIDE

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

A.0.0

OVERRIDE

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION

R

OVERRIDE

A

PAGE TITLE

TABLE_PHYSICAL_RULE_ITEM

BRANCH

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K50/K51 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO

BOARD LAYERS

BOARD AREAS

BOARD UNITS
(MIL or MM)

ALLEGRO
VERSION

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM

NO_TYPE,BGA_P1MM

MM

15.5.1

PHYSICAL CONSTRAINTS

SPACING RULE SET
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DEFAULT

*

Y

=50_OHM_SE

=50_OHM_SE

100 MM

0 MM

0 MM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

0.1 MM

?

TABLE_PHYSICAL_RULE_ITEM

*

TABLE_PHYSICAL_RULE_ITEM

STANDARD

*

Y

=DEFAULT

=DEFAULT

12.7 MM

=DEFAULT

=DEFAULT

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

27P4_OHM_SE

TOP,BOTTOM

Y

0.300 MM

0.085 MM

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LINE-TO-LINE SPACING

WEIGHT

2X_DIELECTRIC

LAYER
*

0.150 MM

?

2X_DIELECTRIC

TOP,BOTTOM

0.160 MM

?

3X_DIELECTRIC

*

0.220 MM

?

TABLE_SPACING_RULE_ITEM

DEFAULT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

STANDARD

*

=DEFAULT

?

D

TABLE_SPACING_RULE_ITEM

D

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

0.15 MM

?

TABLE_SPACING_RULE_ITEM

3X_DIELECTRIC

TOP,BOTTOM

0.240 MM

?

4X_DIELECTRIC

*

0.300 MM

?

4X_DIELECTRIC

TOP,BOTTOM

0.320 MM

?

5X_DIELECTRIC

*

0.380 MM

?

5X_DIELECTRIC

TOP,BOTTOM

0.400 MM

?

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

1.5:1_SPACING

*

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

27P4_OHM_SE

*

Y

0.275 MM

0.085 MM

=STANDARD

=STANDARD

=STANDARD

TABLE_SPACING_RULE_ITEM

2:1_SPACING

*

?

0.2 MM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

TOP,BOTTOM

*

0.25 MM

?

3:1_SPACING

*

0.3 MM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

2.5:1_SPACING

DIFFPAIR NECK GAP

Y

0.165 MM

0.085 MM

TABLE_SPACING_RULE_ITEM

=STANDARD
TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

*

Y

0.15 MM

0.085 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

4:1_SPACING

*

0.4 MM

?
TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

TABLE_PHYSICAL_RULE_ITEM

CLK_SPACING_0.5MM

*

0.5 MM

?

TABLE_PHYSICAL_RULE_ITEM

CLK_SPACING_0.6MM

*

0.6 MM

?

GND_P2MM

*

0.2 MM

1000

PWR_P2MM

*

0.2 MM

1000

SWITCHNODE

*

0.6 MM

1000

TABLE_PHYSICAL_RULE_HEAD

42_OHM_SE

TOP,BOTTOM

SPACING_RULE_SET

LAYER

TABLE_SPACING_RULE_ITEM

Y

0.151 MM

0.085 MM

=STANDARD
TABLE_SPACING_RULE_ITEM

42_OHM_SE

*

Y

0.136 MM

0.085 MM

=STANDARD

=STANDARD

=STANDARD
TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

50_OHM_SE

TOP,BOTTOM

Y

0.1 MM

0.085 MM

15 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE

*

Y

0.1 MM

0.085 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

55_OHM_SE

TOP,BOTTOM

Y

0.085 MM

0.085 MM

=STANDARD

55_OHM_SE

*

Y

0.076 MM

0.075 MM

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

CONSTRAINTS FOR BGA AREA

TABLE_PHYSICAL_RULE_ITEM

C

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LINE-TO-LINE SPACING

WEIGHT

BGA_P1MM

LAYER
*

=DEFAULT

?

BGA_P2MM

*

0.2 MM

?

BGA_P3MM

*

0.3 MM

?

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

=STANDARD

C

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

70_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

70_OHM_DIFF

ISL3,ISL6

Y

0.155 MM

0.085 MM

=STANDARD

0.135 MM

0.1 MM

70_OHM_DIFF

TOP,BOTTOM

Y

0.165 MM

0.085 MM

=STANDARD

0.130 MM

0.1 MM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

*

*

BGA_P1MM

BGA_P1MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

*

BGA_P1MM

BGA_P2MM

TABLE_PHYSICAL_RULE_ITEM

CLK_FSB

*

BGA_P1MM

BGA_P2MM

TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE

*

BGA_P1MM

BGA_P1MM

TABLE_PHYSICAL_RULE_ITEM

FSB_DSTB

FSB_DSTB

BGA_P1MM

BGA_P1MM

CLK_LPC

*

BGA_P1MM

BGA_P1MM

CLK_PCI

*

BGA_P1MM

BGA_P1MM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MCP_FSB_COMP

*

BGA_P1MM

BGA_P2MM

MCP_MEM_COMP

*

BGA_P1MM

BGA_P2MM

MCP_PEX_COMP

*

BGA_P1MM

BGA_P2MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP
TABLE_SPACING_ASSIGNMENT_ITEM

90_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

90_OHM_DIFF

ISL3,ISL6

Y

0.099 MM

0.085 MM

12 MM

0.200 MM

0.1 MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

90_OHM_DIFF

TOP,BOTTOM

Y

0.110 MM

0.085 MM

=STANDARD

0.200 MM

0.1 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF

*

N

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

100_OHM_DIFF

ISL3,ISL6

Y

0.081 MM

0.085 MM

=STANDARD

0.25 MM

0.1 MM

100_OHM_DIFF

TOP,BOTTOM

Y

0.091 MM

0.085 MM

=STANDARD

0.25 MM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

110_OHM_DIFF

*

N

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

B

TABLE_SPACING_ASSIGNMENT_ITEM

B

TABLE_PHYSICAL_RULE_ITEM

110_OHM_DIFF

TOP,BOTTOM

Y

0.075 MM

0.085 MM

=STANDARD

0.320 MM

0.15 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

1:1_DIFFPAIR

*

Y

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.085 MM

POWER_WIDTH

*

Y

0.600 MM

0.200 MM

3.0 MM

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

POWER

*

POWER_WIDTH

VR_CTL_PHY

*

POWER_WIDTH

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

K22/K23 RULE DEFINITIONS
DRAWING NUMBER

Apple Inc.

051-7863

NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

CONSTRAINTS ARE BASED ON MCP79 DESIGN GUIDE DG-03328-001_V06
PCI,LPC,SMB,HDA,SPI,RGMII,SMBUS ARE ROUTED AS 55 OHM SE SIGNALS

SIZE

BRANCH

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FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

J4700 USB CAMERA
103 47

IN

103 47

IN

D

USB_CAMERA_L_P
USB_CAMERA_L_N

J5520 ANALOG LCD TEMP SENSOR

FUNC_TEST=TRUE

108 55

IN

FUNC_TEST=TRUE

108 55

IN

SNS_LCD_P
SNS_LCD_N

66

IN

FUNC_TEST=TRUE

66

IN

66

IN

1 PP5V_S3_REG Testpoint near J4700
2 Ground Testpoints near J4700

IN

103 47

IN

USB_SDCARD_L_P
USB_SDCARD_L_N

J5521 AMBIENT TEMP SENSOR

FUNC_TEST=TRUE

108 55

IN

FUNC_TEST=TRUE

108 55

IN

SNS_AMB_P
SNS_AMB_N

IN

FUNC_TEST=TRUE

IN
IN
IN

J4720 USB BLUETOOTH

103 47

IN
IN

USB_BT_L_P
USB_BT_L_N

J5551 ODD TEMP SENSOR

FUNC_TEST=TRUE
108 55

IN

108 55

IN

FUNC_TEST=TRUE

1 PP3V3_S3 Testpoint near J4720
2 Ground Testpoints near J4720

SNS_ODD_P
SNS_ODD_N

AUD_SPKR_OUTLO2R_P
AUD_SPKR_OUTLO2R_N
AUD_SPKR_OUTLO1R_P
AUD_SPKR_OUTLO1R_N

GND

16 TP’S

FUNC_TEST=TRUE

FUNC_TEST=TRUE
MIN_ALLOWED_TPS=16

FUNC_TEST=TRUE
FUNC_TEST=TRUE
78 6

IN

PP3V3_S3

2 TP’S

73 6

IN

PP5V_S3_REG

2 TP’S

78 6

IN

PP5V_S0

J6602 AUDIO RIGHT SPEAKER

FUNC_TEST=TRUE

1 PP3V3_S3 Testpoint near J4750
2 Ground Testpoints near J4750

103 47

AUD_MIC_IN1_N_CONN
GND_AUDIO_MIC1_CONN
AUD_MIC_IN1_P_CONN

1 Ground Testpoint near J6601

J4750 USB CARD READER
103 47

J6601 AUDIO MICROPHONE

FUNC_TEST=TRUE

D

FUNC_TEST=TRUE
MIN_ALLOWED_TPS=2

FUNC_TEST=TRUE
MIN_ALLOWED_TPS=2

FUNC_TEST=TRUE
FUNC_TEST=TRUE

FUNC_TEST=TRUE
MIN_ALLOWED_TPS=1

FUNC_TEST=TRUE
FUNC_TEST=TRUE

J6603 AUDIO LEFT SPEAKER

FUNC_TEST=TRUE

IN

FUNC_TEST=TRUE

IN
IN
IN

AUD_SPKR_OUTLO2L_P
AUD_SPKR_OUTLO2L_N
AUD_SPKR_OUTLO1L_P
AUD_SPKR_OUTLO1L_N

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

J4780 IR BOARD
103 47

IN

103 47

IN

USB_IR_L_P
USB_IR_L_N

FUNC_TEST=TRUE

J5600 ODD FAN

FUNC_TEST=TRUE

1 PP5V_S3_REG Testpoint near J4780
2 Ground Testpoints near J4780

56

IN

56

IN

56

IN

56

IN

FAN_0_PWR_L
FAN_TACH0_L
PP12V_S0_FAN0_L
FAN_0_GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

C

C
J5700 CPU FAN
J4520 SATA ODD (HIGH SPEED)
102 45

IN

102 45

IN

102 45

IN

102 45

IN

49 45

IN

SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P
SMC_ODD_DETECT

57

IN

57

IN

57

IN

57

IN

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

FAN_2_PWR_L
FAN_TACH2_L
PP12V_S0_FAN2_L
FAN_2_GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

J5601 HD FAN

FUNC_TEST=TRUE

1 PP5V_S0 Testpoint near J4520
5 Ground Testpoints near J4520

56

IN

56

IN

56

IN

56

IN

FAN_1_PWR_L
FAN_TACH1_L
PP12V_S0_FAN1_L
FAN_1_GND

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

J4510 SATA HDD (HIGH SPEED)
102 45

IN

102 45

IN

102 45

IN

102 45

IN

SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE

3 Ground Testpoints near J4510

B

B

A

SYNC_MASTER=K22

SYNC_DATE=09/02/2009

A

PAGE TITLE

K22/K23 ICT/FCT
DRAWING NUMBER

Apple Inc.

051-7863

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

REVISION

A.0.0

R

NOTICE OF PROPRIETARY PROPERTY:

SIZE

BRANCH

PAGE

110 OF 110
SHEET

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8

7

6

5

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---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
Page Count                      : 110
Producer                        : AFPL Ghostscript 8.0
Create Date                     : 2009:09:02 21:51:44
Modify Date                     : 2009:09:02 21:51:44
Creator                         : Cadence Design Systems

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