KA K1170 MG 003_1170_Maintenance_Service_Guide_Apr88 003 1170 Maintenance Service Guide Apr88
KA-K1170-MG-003_1170_Maintenance_Service_Guide_Apr88 KA-K1170-MG-003_1170_Maintenance_Service_Guide_Apr88
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KA-K1170-MG-003
1170 MAINTENANCE
SERVICE GUIDE
PREPARED BY: BERNIE LEDUC
: ED SMITH
CANADIAN PRODUCT SUPPORT
REPRINT: APRIL 1988
dlgnal equipment of canada ltd. kanata, onta~o, canada
The PDP1170 Maintenance Service Guide version 3 is now available for
ordering for USA and CANADA Field Service. We are unable to provide this
guide for outside of North America due to customs and licensing
requirements.
For those who have never seen version 1, the 1170 Maintenance Service Guide
is a made in Canada, 7'h" by 10" binder sized troubleshooting guide that no
1170 engineer should be without. It contains information on Diagnostics,
Bootstraps, Togglein's, Adjustments, Switches, Jumpers, Indicators, and
Cabling diagrams. It also has block diagrams, registers and troubleshooting
info on the CPU, Cache, Memory Management, Unibus Map, RH70, MJ11,
MK11 and KY11 R.
Anyone who would like to get on my distribution list for future updates and
corrections to this guide can send me VaxMail at ENET node:
CGFSV1 ::SMITH
Also if you have any questions, suggestions or corrections to Version 3 please
send them to me.
You can order your copy, complete with binder for $40.00 per guide, by
sending:
DECMail
ENET
PAT DAVIES @KAO
KAFSV1 ::DAVIES
Please include the following information:
PART NUMBER:
KA-K1170-MG-003
DESCRIPTION:
1170 Maintenance Service Guide
REQUESTERS NAME:
COST CENTER:
(to be charged to)
COST CENTER MANAGER:
(approving purchase)
INTERNAL MAIL STOP:
COMPLETE MAILING ADDRESS:
DOCUMENTATIONS
DIAGNOSTICS
BOOTSTRAPS
TOGGLE-INS
TECH-TIPS/FCRS
ADJUSTMENTS
SWITCHES, JUMPERS, INDICATORS
CACHE
MEMORY MANAGEMENT
UNIBUS MAP
RH70
MJ11
MK11
KY11-R
PM'S
CABLES
I
TROUBLESHOOTING AIDS
'~1I1(Q) MA~~'1IE~A~CIE tGillJ~[Q)1E
CO~'1IE~'1$
DOCUMENTATIONS ........................ .
DIAGNOSTICS .............................. .
BOOTSTRAPS .............................. .
TOGGLE-INS .. ............................. .
TECH-TIPS/FCRS ........................... .
ADJUSTMENTS ............................. .
SWITCHES, JUMPERS, INDiCATORS ..... ... .
CPU ........................................ .
CACHE ..................................... .
MEMORY MANAGEMENT .... ............... .
UNIBUS MAP ............................... .
RH70 ....................................... .
MJ11 ....................................... .
MK11 ....................................... .
KY11-R ..................................... .
PM'S ....................................... .
CABLES .............. ...................... .
TROUBLESHOOTING AIDS ................. .
CHAPTER
PAGES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1-2
3-8F
9-14
15-18
19-24
25-28
29-42C
43-68
69-82
83-90
91-96
97-100
101-110
111-118
119-124B
125-130
131-138
139-UNIX-4
•
C~JA~u~~
·u
[i)«::DCUM~U\juAu~«::DU'J
CONTENT
PAGE
DOCUMENTATION LIST AND AVAILABILITY
2
A) DOCUMENTATION LIST AND AVAILABILITY
A) MANUALS
DESCRIPTION
-KB11B
-KB11C
-PDP-11170
-KY11-R
-FP11-C
-RWPOS/06
-M9301
-M9312
-MJ11
-MK11
PROC MANUAL
PROC MANUAL
MAINT & INST MANUAL
TECH MANUAL
MAINT MANUAL
MAINT MANUAL
TECH MANUAL
TECH MANUAL
MEM SYS MAINT MANUAL
MOS MEM TECH MANUAL
PART NUMBER
EP-KB11-B-PM-A
EK-KB11-C-TM-A
EK-11070-MM-A
EK-KY11 R-TM-002
EK-FP11 C-MM-001
EK-RWPS6-MM-A 1
EK-M9301-TM-001
EK-M9312-TM-003
EK-OMJ11-MM-A
EK-OMK11-TM-001
MAINT
MAINT
MAINT
MAINT
MAINT
MAINT
MAINT
PART NUMBER
M P-00823-00
MP-00822-00
M P-00348-00
MP-00038-00
MP-ORH70-00
MP-OMJ11-00
M P-OOS23-00
B) PRINTS
DESCRIPTION
-PDP-1170
-PDP-1170
-KY11-R
-FP11-C
-RH70
-MJ11
-MK11
PRINTS (KB11B)
PRINTS (KB11C)
PRINTS
PRINTS
PRINTS
PRINTS
PRINTS
C) MAINTENANCE CARDS
DESCRIPTION
-MK11
-PDP 11170
-PDP 11170
MEM MAINT CARD
ELECT CONSOL COMMANDS
MAINT CARD
PART NUMBER
EK-OM K11-MC-001
EK-E1170-MC-001
(THROUGH ED.
SERVICES)
D) PREVENTIVE MAINT WORKSHEETS
DESCRIPTION
-1170
-RH70
-FP11-B
PM WORKSHEET
PM WORKSHEET
PM WORKSHEET
PART NUMBER
EK-11070-WS
EK-ORH70-WS
EK-FP11 B-WS
PROC IPB
MEM SYS MAINT GUIDE
PART NUMBER
EK-01170-1 P
EK-11070-HP-001
E) OTHERS
DESCRIPTION
-1170
-PDP-1170
2
•
C~~AiP'ulE~
2
[j)~A«3~(Q)~u~(C$
CONTENT
PAGE
DIAG LIST/SWITCHES
DIAG PATCHES AND SPECIAL MODIFICATIONS
4,5,6,7,8
3
8A,8B,8C,8D,8E,8F
All of the PDP1170 diagnostics rely on the previous diagnostics verifying
sections of the hardware. They should be run in the following order:
Latest Rev.
Name
EKBADO
EKBBFO
EKBCD1
EKBDEO
EKBEE1
EKBFD1
EKBGCO
EQKCE1
EMJADO
EMKABO
ERHAE1
EFPAAO
EFPBA1
CPU TEST PART 1
CPU TEST PART 2
CACHE TEST PART 1
CACHE TEST PART 2
MEMORY MANAGEMENT TEST
UNIBUS MAP TEST
PDP1170 POWER FAIL TEST
PDP1170 INSTRUCTION EXERCISER
MJ11 MEMORY TEST
MK11/MJ11 MEMORY TEST
RH70 TEST
FP11-C TEST PART 1
FP11-C TEST PART 2
The following is a summary of the diagnostic setups and commands:
Et(BA
Starting Address(s): 200
Switch Register: None
Notes:
*Halts on Error.
* * First pass runs with cache disabled.
Et~J3B
Starting Address(s): 200
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Inhibit T-bit trapping
11 Inhibit iterations
10 Ring bell on error
09 Loop on error
08 Loop on test in <7:0>
07 No action
06 Skip BR6 tests
05 Skip BR5 tests
04 Skip BR4 tests
00 Skip operator intervention tests
Notes:
*First pass runs with Cache disabled.
**This diagnostic wi/l also write on any write enabled disk drives. You must
spin down or write protect any diagnostic pack or customer software pack to
prevent a disaster. If you wish to use this feature Simply mount a SCRA TCH
pack on any drive and write enable it.
* * * This diagnostic looks for an RH70 to do BR5 tests. If there are none in the
system it wi/l print "NO BR5 DEVICES". This is not an error message.
4
Im8C/D
Starting Address(s): 200
Switch Register:
B IT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 No action
11 I nhibit iterations
10 Ring bell on error
09 Loop on error
08 Loop on test in <6:0>
07 Skip MM tests
<6:0> Test # to loop on
Notes:
*Use • C to restore monitor.
**The EKBD diagnostic will also write on any write enabled disk drives. You
must spin down or write protect any diagnostic pack or customer software
pack to prevent a disaster. If you wish to use this feature simply mount a
SCRA TCH pack on any drive and write enable it.
***There is also a problem when trying to chain the EKBD diagnostic or
typing' C to exit to the monitor. It doesn't chain or exit properly because the
monitor doesn't get fully restored. The following patch will correct the
problem.
EKBDDO
location 05162/27343000
54546/2734 3000
EKBDEO
location 05324/2734 3000
56110/27343000
Et{8E/rStarting Address(s):
200 Normal, run all tests
204 Test R/W bits in MMR's
210 Test PAR's/PDR's
214 Relocation and Adder test
220 MM aborts and trap logic tests
224 D space tests
230 A + W bit logic and dual mapping
234 MFP/MTP tests
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Inhibit trace trap every other pass
11 Inhibit iterations
10 Ring bell on error
09 Loop on error
08 Loop on test in <6:0>
07 Inhibit multiple error typeouts
<6:0> Test # to loop on
Notes:
*To run with cache disabled halt the program and load a 14 into 17777746,
then load the starting address into 17777707 and hit continue.
5
E[CBG
Starting Address(s):
200 Normal
220 Restart
Switch Register:
B IT15 Halt on error
14 Loop on test (section 1 only)
08 Enable system powerfail test 25
07 Disable section 1 tests (multi only)
06 Multiprocessor mode
05 UBE selected
Notes:
*See listing for multiprocessor mode.
EMJA
Starting Address(s): 200
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Inhibit using MM
11 Inhibit iterations
10 Ring bell on error
09 Display error count in DR
08 Halt program unrelocated
06 Use 18 bit mapping only
Notes:
*Program must not be relocated when restarting.
EIVl[CA
Starting Address(s): 200
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Inhibit program relocation
11 Inhibit iterations
10 Bellon error
09 Loop on error
08 Halt program and flush DBE's
07 Detailed error report
06 Print configuration map
05 Limit max errors per bank
04 132 column terminal
<3:1> Pattern (see listing)
00 Detect single bit errors
Notes:
* There must be no unibus devices addressed from 752100 to 752136./fthere is
remove them prior to running the diagnostic.
**The lower 16K must have no DBE's.
Special Functions:
•C
Flush DBE's and boot DKO:
o
Enter modified ODT
6
Exit ODT
Tell me whats happening
Field service mode
E
T
F
o
Exit field service mode
1 Read MK11 CSR
2 Load MK11 CSR
3 Examine memory
4 Modify memory
5 Select BANK, MARGIN,PATTERN
6 Type configuration map
7 Battery backup test
8 SOB-A-Long test
9 Super tight scope loop
10 Error summary
11 Refresh test
12 Set fill count
13 Enter KAM I KAZE mode
14 Exit KAMIKAZE mode
15 Turn off cache
16 Turn on cache
17 Run only multi-port tests
18 Resume single and multi tests
19 Test only selected banks
20 Resume testing all banks
Display register:
15 Relocated
<14:8> Bank #
<7:5> Margin
<4:1> Pattern
o Not used
Margin:
MJ11
MK11
o
Normal
Force addrs par
Early strobe
Late strobe
Low current
High current
Same
Same
Early MDR load
Late refresh
Reserved
Reserved
1
2
3
4
5
EOt(C
Starting Address(s):
200 Normal
210 Display register test (see listing)
214 Micro-break reg test (see listing)
230 CPU ID register jumper cutting aid
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Inhibit UBE
11 Inhibit iterations
10 Ring bell on error
09 Loop on error
08 Relocate on disk
7
•
07
06
05
04
03
<2:0>
Inhibit system size typeout
I nh ibit relocation
Inhibit round robin
Inhibit random disk address
Inhibit MBT
Specific device code
Device code:
o
1
2
3
4
5
6
7
RP11/RP03
RK05
Not used
Not used
RH70/RP04
RH70/RS03/RS04
Not used
Not used
Notes:
* The diagnostic will use the VBE, MB Tand FP11-B or FP11-C if installed. See
listing for details.
**To use with RM0315's set SWR bit 4 (inhibit random disk relocation) and
select it as an RP04.
Er-PA/B
Starting Address(s): 200
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Skip MM tests
11 Inhibit iterations
10 Bell on error
09 Loop on error
08 = 1 Loop on test in <7:0>
08 = 0 Load uBreak register from <7:0>
<7:0> Test #1 uBreak register value
Notes:
*See listing for more details.
* * If you have FP11-B use the CFP??? series of diagnostics.
ERHA
Starting Address(s):
200 Standard RH70, PGM drives inhibited
210 Non-standard, PGM drives not inhibited
220 Standard RH70, no inhibits
Switch Register:
BIT15 Halt on error
14 Loop on test
13 Inhibit error typeouts
12 Not used
11 Inhibit iterations
10 Bell on error
09 Loop on error
08 Loop on test in <7:0>
<7:0> Test # to loop on
Notes:
*Must have a tape loaded at BOT and/or a scratch pack mounted with heads at
cylinder zero. Be careful of programmable drives!
8
EKBA**
CPU Part 1
EKBADO
No Patches
EKBB**
CPU Part 2
EKBBFO
No Patches
EKBC**
CACHE Part 1
EKBDC1
Memory size problem with 1920K or more of memory
Location
31420
31422
From
23712
172356
To
22712
170000
EKBD**
CACHE Part 2
EKBDDO/EO
See page 5 for Monitor reload problem patch
EKBE**
Memory Management Test
EKBEE1
Memory size problem with 1920K or more of memory
Location
30756
30760
From
23712
172356
To
22712
170000
EKBF**
Unibus Map Test
EKBFDO/D1
Fails test 34, parity errors from Group 0 of CACHE
Rev
DO
D1
Location
17722
17734
From
40010
140000
8A
To
40100
140010
EMKA**
MK11/MJ11 Memory Diagnostic
EMKAAO/BO
You can disable Cache in EMKA with the following patch
instead of using Field Service command 15.
Rev
AO
BO
Location
2132
2700
From
1
1
To
15
15
Note 1. Cache is not disabled until initialization is completed
Note 2. Halt EMKA by setting SWR bit 8 to a 1 (swr =400).
This cleans up memory by clearing any errors the diagnostic may
have forced into memory data locations, or the CSR's. It will also
reenable ECC providing that ECC is not turned off by the switch on
the memory control panel.
Note 3. Typing a • C cleans up memory and tries to boot RK05 drive #0. If
unsuccessful, drive #1. After • C is typed and system halts, normal
Memory System Error Register ($44) will contain 4200. The Cache
Control Register ($46) will contain any of the following;14,15,1 .. All
are legal diagnostic residue.
EMKAAO/BO
Peripheral Address Problem
When EMKAAO is run on a 1170 with a peripheral at address 166000, the
diagnostic will hang in a loop after printing the diagnostic header "CEMKAAO
1170 MAIN MEMORY DIAGNOSTIC" due to the address of liST
(Interprocessor Interrupt and Sanity Timer at address 166000). EMKABO was
patched to solve this problem. The solution was to change liST address to
777500. Therefore, with EMKABO, if there is a device at address 177500, the
same problem symptom as EMKAAO will be evident. If you run into this
problem, You can modify those two (2) locations to equal a non-existant 110
page address.
Rev
AO
BO
Location
2162
2164
2736
2740
From
166000
166002
177500
177502
8B
To
Non-existant
Non-existant
Non-existant
Non-existant
I/O
110
110
110
address
address
address
address
EQKC**
1170 I nstruction Exerciser
There is a common problem with all revisions of EQKC, the 1170 CPU
Exerciser. This diagnostic supports the Massbus tester used in production.
The addresses specified for the MBT in EQKC are 160100 thru 160176. Since
these addresses are commonly used for communications gear (OZ11's), this
may create a problem. The problem seems to be that if EQKC is halted in a
disorderly manner, it may think that the system has a Massbus tester attached.
If a device responds to address of 160100 a trap thru loc. 4 will result and the
program must be reloaded. This has caused some techs to go on a wild goose
chase. It is recommended that EQKC be halted by typing a C on the console
terminal.
A
EQKCBO/CO/OO/EO Non-Standard I/O Addresses
If you want to allow EQKC to relocate to a device at a non-standard address
you will need to patch several locations.
BO/CO
2142
2144
2146
2150
2152
2154
2156
2160
2162
2164
2166
2170
2172
2174
2176
2200
DO
EO
2252
2254
2256
2260
2262
2264
2266
2270
2272
2274
2276
2300
2302
2304
2306
2310
2202
2204
2206
2210
2212
2214
2216
2220
2222
2224
2226
2230
2232
2234
2236
2240
Contents
176700
176702
176704
176750
176706
176710
176752
176712
176714
176734
176740
176742
176736
176732
000254
000256
Note: Change above locations to reflect the new addresses and vector and
note that they are not in order.
EQKCE1
Memory size problem with 1920K or more of memory
Location
62102
62104
From
23712
172356
8C
To
22712
170000
liJiAGWOSTiC PATCHES AWD SPECIAL MODir-ICATIOWS (cont)
ERHA**
RH70 Diagnostic
-ERHADO/EO
In order to test unit numbers other than 0 with ERHA, the
diagnostic must be patched as follows:
Rev
DO
EO
ERHAE1
Location
5376
5364
7040
7022
From
0
0
0
0
To
Unit #
Slave # (for Tapes)
Unit #
Slave # (for Tapes)
Fails T26 when going to TE16
Location
24046
24146
From
177772
2300
8D
To
177766
2200
ID~AGil'JOSii~C PAiiC~H:S
DEG}(11
AND SPECiAL
I\IJOID!F!CAii~OiI'JS
(cont)
EGG Enable Patch
DECX will disable EGC on an 1144 as it does on an 1170.
The following is a list of patches for the 1144:
XMONB
Loc 45120
Loc 45122
Loc 45134
XMONG
45362
45364
45376
XMOND
46122
46124
46136
Was
52731
3
42731
Should be
12731
1
12731
The following is a list of patches for the 1170:
XMONB
Loc 32214
Loc 32216
Loc 3222
XMONG
32436
32440
32444
XMOND
33024
33026
33032
Was
52731
3
42731
Should be
12731
1
12731
Keep in mind that these patches will not reset ECG if it is disabled but it will
simply prevent DECX from disabling it. So if you load and run DEGX before
putting in the patch you will have to manually reset ECC by the GSR's then
reload DEGX and patch it.
DEG}(11
EGG/Parity Messages Modification
When running DECX11 on an 1144/1170system with MS11/MK11 memory, we
all know that paches are needed to correct DECX. Here is the way to leave
DECX11 alone but cause it to print the full message as the authors intended:
Monitor
XMONBO
XMONCO
GMONDO
****
Location
44706
45150
45704
From
42400
42400
42400
FOR THE 'E' MONITOR ONLY
8E
To
42401
42401
42401
****
DECX11
Memory Margins Patch
See Page 140 for procedure on using DECX with MJ11/MK11 memory
margins.
DECX11
DECX11 as a Memory Test
This is a proven method to use DECX11 as an excellent memory exerciser
when no other diagnostic seems to fail.
Preferred Method:
1.
Run DXCL and build a DECX11 exerciser to include only the modules
CPAG and CPBJ using monitor "E". Link it with a name of "FASTX.BIN"
for ease of future reference. Now go ahead and run it. At the CMD<
prompt, do the following:
CMD
8WR <07:03>
8WR <15:12>
UNIT #
DEVICE CODE
32K MEMORY BANK
The following jumpers and switch settings apply for the M9301-YC on the
PDP1170:
JUMPERS
SETTING
W1-6
IN
SWITCHES
NORMAL SETTING
81-1
81-2
81-3:7
81-10:7,5
81-8:10
81-6,2,1
ON for
On for
Device
Device
Unit #
Unit #
(etch
(etch
(etch
(etch
F)
E)
F)
E)
DEVICE SELECT CODE
low ROM enable
powerup boot
select
select
ETCH E S1-10
ETCH F S1-3
S1-9
S1-4
S1-8
S1-5
S1-7
S1-6
S1-5
S1-7
TM11/TU10
TC11/TU56
RK11/RK05
RP11/RP03
RE8ERVED
RH70/TU16
RH70/RP04
RX11/RX01
01
02
03
04
05
06
07
11
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
UNIT #
ETCH E
ETCH F
S1-3
S1-4
S1-10 S1-9
S1-6
S1-8
ON
ON
ON
ON
OFF
OFF
OFF
,OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
0
1
2
3
4
5
6
7
ON
ON
OFF
OFF
ON
ON
OFF
OFF
If an- error is detected during the diagnostics the CPU halts and the halt
address indicates what the failure was (see table 1).
If boot halts at
17773654
17773746
17773764
Press continue to force misses in CACHE.
10
To boot with cache off first deposit a 14 in 17777746, then deposit 173000 into
17777707, setup your 8WR and hit continue.
rul9301-na
This bootstrap is used for both the PDP1160 and the PDP1170. It runs the same
tests as the M9301-YC except for checking the kernal PDR's and PAR's. It also
doesn't turn on memory management and the unibus map. To start the bootstrap you load address 17773000 and set the 8WR. Diagnostics are run or
bypassed depending on your switch settings. The 8WR must be set in the
following format:
8WR <02:00>
8WR <06:03>
UNIT #
DEVICE CODE
The following jumpers and switch settings apply for the M9301-YH on the
PDP1170:
JUMPERS
SETTING
W1-6
IN
SWITCHES
NORMAL SETTING
81-1
81-2
81-3
81-4:7
81-8
81-9
81-10
ON for low ROM enable
ON for powerup boot
Diagnostic select
Device select
OFF for device code from 8WR, ON use 81-4:7
Diagnostic select
OFF for PDP1170
DIAGNOSTIC SELECT
S1-9
S1-3
No diagnostics
No diagnostics
Run tests 1-24
Run tests 1-20
OFF
OFF
ON
ON
OFF
ON
OFF
ON
DEVICE SELECT
CODE
S1-4
S1-5
S1-6
S1-7
TM11/TU10
TC11/TU56
RK11/RK05
RP11/RP03
RK611/RK06
RH70/TU16
RH70/RP04
RX11/RX01
PC11
01
02
03
04
05
06
07
11
12
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
ON
If an error is detected during the diagnostics the CPU halts and the halt
address indicates what the failure was (see table 1).
If boot halts at
17765614
17765732
17765752
Press continue to force misses in CACHE.
To boot with cache off first set switches 81-9 and 81-3 to the OFF position.
Then deposit a 14 into 17777746, deposit a 173000 into 17777707, setup your
8WR and hit continue.
11
M9312
This is a multipurpose PDP11 bootstrap. To use it on a PDP1170 you must have
the PDP1160/1170 diagnostic ROM (part # 23-233F1) installed in E20 and the
appropriate boot ROMs installed for the devices you have. To boot the
PDP1170 you load add ress 17765744 and set the SWR as follows:
SWR
= OOUXMM
Where:
U = Device unit # 0 - 7
X = 0 for ROM 1
2 for ROM 2
4 for ROM 3
6 for ROM 4
MM = 42 for low speed reader and TU55/56
56 for RP04/5/6 and RM02/3/5
12 for all other devices
All alternate boot procedure is to start at the device ROMs starting address as
follows:
STARTING ADDRESS
Where:
X =0
2
4
6
N =5
3
for
for
for
for
for
for
o for
Y = 4 for
6 for
o for
2 for
ROM
ROM
ROM
ROM
= 17773XNY
1
2
3
4
RP04/5/6 and RM02/3/5
low speed reader and TU55/56
all other devices
no diagnostics if N = 0 or 3
diagnostics if N = 0 or 3
no diagnostics if N = 5
diagnostics if N = 5
The following jumpers and switch settings apply for the M9312 on the
PDP1170:
JUMPERS
SETTING
W1-7
W8
W9,10
W11,12
IN
OUT
IN
OUT
SWITCHES
NORMAL SETTING
81-1
81-2
81-3,4
S1-5:9
81-10
OFF
ON for powerup boot
ROM socket select
Device select
ON for diagnostics
ROM SOCKET
S1-3
S1-4
1
2
3
4
OFF
OFF
ON
ON
OFF
ON
OFF
ON
(E35)
(E33)
(E34)
(E32)
12
PART #
DEVICE SELECT
S1-5
S1-6
S1-7
S1-8
S1-9
23-751A9
23-752A9
23-753A9
*23-811A9
23-755A9
RL01/2
RK06/7
RX01
RX02
RP02/3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
RP04/5/6,RM02/3
23-756A9
23-757A9
23-758A9
23-759A9
23-760A9
23-761A9
23-762A9
23-763A9
23-764A9
23-765A9
23-767A9
23-E38A9
RK03/5 (unit 0)
RK03/5 (unit 2)
TU55/56
TU 16/TE16/TU45ITU77
TU 10/TE1 0/TS03
RS03/4
PC05
DL 11A/W
TU60
RS11
RS64
CR11
TS11/TU80/TS05
TU58
RA60/80/81/RC25
TK50/TU81
If an error is detected during the diagnostics the CPU halts and the halt
address indicates what the failure was (see table 1).
If boot halts at
17765554
17765676
17765716
Press continue to force misses in CACHE.
To boot with cache off first deposit a 14 into 17777746, then deposit a 173XN4
or 173XNO if N =5 (X and N refer to your boot device, see section above on the
M9312) into 17777707 and hit continue. If the diagnostics detect an error the
CPU halts and the halt address indicates the failure (see table 1).
*RX02 boot ROMS with date codes 7921 thru 7931 are bad
console boot ROM part # is 23-248F1
***The 1160, 1170 boot ROM 23-233F1 is replaced by 23-616F1
* * 11 04134
13
TABLE 1
HALT ADDAESS DISPLAYED
M9301
YC
M9301
YH
M9312*
165004
165020
165036
165052
165066
165076
165134
165146
165166
165204
165214
165222
165236
165260
165004
165020
165036
165052
165066
165076
165126
165136
165154
165172
165202
165210
165224
165246
165052
165070
165104
165116
165270
165312
165346
165360
165374
165450
165474
165510
165520
165530
165542
165550
NO HLT
165742
165760
166000
173644
173654
173736
173746
173764
165256
165300
165334
165352
165376
165406
165416
165430
165436
165520
165540
165604
165614
165720
165732
165752
INSTRUCTIONS TESTED
BR
CLR, BMI, BVS, BHI, BLOS, (BL T)
DEC, BPL, BEQ, BGE, [BGT], BLE
ROR, BVC, BHIS, [BHI], BNE
SEZ, BHI, SEN, BL T, BLOS
CLZ, BLE, BGT
MOV, REG DATA PATH, SUB, BLT, BEQ
ROL, BCC, BL T
165174 ADD, INC, COM, BSC, BLE, (BL T)
165214 ROR, BIS, ADD, INC, BLO, [BGE], (DEC)
DEC, BLOS, BLT
165220 COM, BLOS
165234 BIC, ADD, BGT, [BGE], BLE
165256 [ADC], (SWAB),CMP,BNE,BIT,BGT,COM,
[SUB],[BEQ]
165266 MOVB, BPL
165310 SOB, CLR, INC, TST, BNE, BEQ
ASR,ASL
ASH
ASH, SWAB
KERNAL PARS
KERNAL PDRS
165322 JSR
165332 WRONG VALUE PUSHED ON STACK
165342 RTS
165354 RTI
165362 JMP
LOAD AND TURN ON MM AND UBM
165460 MAIN MEMORY 1000-28K, CACHE OFF
165500 DATA NOT COMPLEMENT, CACHE OFF
PARITY ERROR HALT
165544 CACHE DATA ERROR
165554**NO CACHE HIT
165664 DATA COMPAIR, CACHE ON
165676**NO CACHE HIT, RO = ADDRESS+2
165716**CACHE ERROR/PARITY ERROR
Note:
(????) = M9312 ONLY
[????] = M9301 ONL Y
*For M9312 boot ROM part # 23-233F1
**To boot with cache off, hit continue
14
C~:JAL0ulE~
<0
u(D~~llEg~~~
CONTENT
PAGE
MEM MAN CHECKOUT
US MAP CHECKOUT
CACHE CHECKOUT
MEM CLEAR ROUTINE
16
16
16
17
15
There are several useful toggle-ins that are probably not very well known.
They are as follows:
PJlemory Management Cl1ecr~oL!i
Use the following toggle-in to verify the correct operation of Memory
Management Relocation.
2001012737
202/000400
204/177572
206/012737
2101070707
212/000200
214/000000
MOV #400,@#177572 (load maint. bit in MMRO)
3001000300
Preset loc 300 to 300
MOV #070707,@#200 (move 070707 to virtual 200)
HLT
Set Kernal I PDR 0 to R/W 4K page
Set Kernall PAR 0 to (Base address 100)
177723001077406
177723401000001
Load Address 200
Start
Load Address 300
Exam
Display = 000216 (Halt@214)
Display = 070707 ... Relocation works
Unibus Map Ci1eclwui
Use the followi ng console operati ng procedu re to verify the correct operation
of the Unibus Map.
Load address
Deposit
500
125252
Load address
Examine
17000500
125252
Data path ok
Load address
Deposit
17000700
070707
Known data
Load address
Deposit
17770202
000000
Map register 0 Hi
Relocation constant
Load address
Deposit
17770200
000200
Map register 0 Lo
Relocation constant
Load address
Deposit
17772516
000040
MMR3
Enable map
Load address
Examine
17000500
070707
Relocates to 700
... Relocated ok
Known data
Caci1e Chec!wut
Perform the following check-out procedure to determine if Cache correctly
detects Hits and Misses.
Power-up
Load address
Examine
17777752
000000
Load address
Examine ...
********
Load address
Examine
17777752
000025
000200
HitlMiss register
Power-up cleared register ok
Examine locations 200 thru 212
Contents don't matter
Hit/Miss register
50% hit rate
16
Load address
Examine ...
000200
********
Examine locations 200 thru 212
Contents don't matter
Load address
Examine
17777752
000077
Hit/Miss register
100% hit rate
Load address
Deposit
17777746
14
Cache control register
Disable cache
Load address
Examine
000200
********
Examine locations 200 thru 212
Contents don't matter
Load address
Examine
17777752
000000
HitlMiss register
No hits in Cache
Memory Clear Program
Use this toggle-in to clear all of memory from location 0 to system size.
LOCATION
CONTENTS
INSTRUCTIONS & NOTES
17772300
17772316
17772340
17772356
17777700
17777701
17777702
17777703
17777704
17777705
17777706
17777776
17772240
17772242
17772244
17772246
17772250
17772252
17772254
17772256
17772260
17772262
17772264
17772266
17772270
17772272
17772274
077406
077406
000000
177600
000000
172340
177572
177760
172516
Pattern
177676
000000
012714
000020
005212
010520 1$:
020027
017776
003774
062711
000200
021311
003402
005000
000776
005312 2$
000000
KIPDR 0
KIPDR 7 = 1/0 page for program
KIPAR 0; Load 200 if using trap catchers.
KIPAR 7 = 1/0 page for program
RO = Start Virtual Address
R1 = KIPAR 0 Address
R2 = MMRO Address
R3 = System size register Address
R4 = MMR3 Address
R5 = Desired pattern or "0"
R6 = Stack pointer
PSW= 0
MOV #20, (R4); Enable 22-bit Mapping
Load address
Start
172240
INC (R2); Enable Memory Management
MOV R5, (RO)+; Data to memory
CMP RO, #17776; Top of Page O?
BLE1$
ADD #200, (R1); Step Page
CMP (R3), (R1); Top of Memory?
BLE2$
CLR RO; Start at Virtual Address 0
BR1$
DEC (R2); Disable Relocation
HLT
The program should halt when all of memory is cleared. If it doesn't halt
examine the CPU error, Memory system error and HIILO error address registers to determine the cause. Trap catchers can be used by depositing 200 in
KIPAR 0 (17772340) instead of zero, and setting up vector locations with their
address + 2 and the Vector+ 2 with a 0 (halt). Note: When loading the program
you must be in console physical.
If you just want to clear bad parity in 0 to 28K memory you can do so by
depositing 14747 into 157776 and then loading address 157776 and start.
17
C~~A~l'Er.:l
5
l'lECH-l'~~S/fCrJ SECl'~OW
CONTENT
PAGE
1170 FCR
1170 TT
MK11 TT
MJ11 TT
MISC
20
21
22
22
23
19
r-CO'§/"fECH- "f~P§
PDP1170 FIELD CHANGE ORDERS INDEX
DESCRIPTION
FCO #
FICHE
POP1170
-
R1
Green
Replace 7009540 with 7011051 power harness.
POP1170
-
S12
Green
+-15v not available for ROC panel, modify
7011051 power harness.
5411294
-S2
Blue
CPU halts when address switch turned,
update revision of ETCH B to CS C.
7010329
-R2
Blue
Poor power distribution, this FCD included in
POP1170 - R1.
7010329
-H5
Blue
Changes for KB11-B to KB11-C, update
revision to WL 0, WT H.
7010329
-R6
Blue
Intermittant massbus errors, update revision
to WL E, WT J.
7010329
-
Blue
Changes for OL 11-W use, update revision to
WL L, WT R.
G235
-S9
Blue
Memory is marginal due to high current drive,
update revision of ETCH 0 to CS N.
M8132
-R2
Blue
For FP11-C use, update revision of ETCH A
to CS B.
M8136
-S2'
Blue
Unibus devices vector to wrong location on
loaded systems, update revision of ETCH 0
to CS C.
M8136
-S4
Blue
Push button boot and down line load feature
needed, update revision of ETCH B,C to CS
C1, E respectively.
M8136
-S5
Blue
M9301 will not boot on MJ11 power fail,
update revision of ETCH B,C to CS C1,F
respectively.
M8138
-
R6
Blue
Memory management aborts may go undetected, update revision of ETCH A,B to CS
C2,F respectively.
M8139
-
R3
Blue
Cache and main memory data errors, update
revision of ETCH B to CS O.
M8140
-R2
Blue
Incorrect data from PAR's, POR's and
memory management registers, update
revision of ETCH A to CS B.
M8142
-S3
Blue
Main memory timeouts, update revision of
ETCH B to CS C.
M8142
-S4
Blue
Main memory parity errors when MAP
transfers timeout and Cache address errors
due to incorrect setup of E42, update revision
of ETCH B to CS O.
M8148
-S3
Blue
Main memory parity errors, update revision of
ETCH A to CS C.
R10
20
M8148
-S4
Blue
Poor main memory bus termination, update
revision of ETCH A to CS A1.
M8151
-S1
Blue
MXF errors occuring with WCE errors, update
revision of ETCH A to CS A.
M8160
-R4
Blue
Circuit breaker on H775D trips during power
fail, update revision of ETCH C,D to CS F.
M9301
-
R1
Blue
M9301-YC diagnostic fails after power up,
update revision of ETCH E to CS E.
PDP1HO 7IECH71P IWDE}{
TT #
FICHE
DESCRIPTION
Green
1170 system serial #.
2
Green
1170 power su pplies.
3
Green
M8143 wire damage.
4
Green
1170 bootstraps.
5
Green
KW11-L noise problem, cross to KW11-TT-10.
6
Green
Timeout problems with Fairchild 74123's.
7
Green
Array boards in MaS ECC memory, cross to MF11-TT-10.
8
Green
Disabling Cache on the 1170.
9
Green
PRS01 useage on KY11-R equipped 1170's, cross to
KY11 R-TT -3.
10
Green
1170 backplane replacement.
11
Green
BC06R cable testing, cross to BC06R-TT-1.
12
Green
Tripping circuit breakers, cross to H775-TT-4.
13
Green
Mixed MaS/CORE on 1170's.
14
Green
RL 11 and RM03 configured on an 1170, cross to
RL 11-TT-4.
15
Green
MK11 initialization cable, cross to MK11-TT-4.
16
Green
Cabling for MK11 boxes, cross to MK11-TT-5.
17
Green
RH11's on 1170's, cross to RH11-TT-7.
18
Green
PDP1170/PDP11 software problem.
19
Green
Guidelines for optimized system cooling, cross to
Cabinets-TT -10.
20
Green
DMC11 basic W/R and Microprocessor diagnostic failures, cross to DMC11-TT -11.
21
Green
MK11 upgrade, cross to MK11-TT-7.
22
Green
MK11 add-on installation, cross to M K11- TT-8.
23
Green
MJ11 troubleshooting flowchart, cross to MJ11-TT-12.
24
Green
1170 troubleshooting, RH70/Cache jumpers.
25
Green
Massbus ribbon cable orientation.
26
Green
10 resister setup.
27
SB274
MK11 voltage regulator 70-14251.
28
SB288
1170 power harness in corporate cabinets.
21
29
SB383
Troubleshooting 1170 MK11 write parity errors.
30
SB384
PDP1170 Bootstrap halt addresses.
31
SB441
1170 Pause Hang Troubleshooting
32
SB476
MK11 CSR's verses 1170 $40, $42, cross to MK11-TT-14
33
SB476
1170 Maintenance Service Guide
34
SB476
1170 Memory System Error Register
Mt{11 TECHTIP INDE}{
TT #
FICHE
DESCRIPTION
1
Green
Array boards in MaS ECC memory, cross to MF11-TT-10.
2
Green
Troubleshooting MK11 systems.
3
Green
Mixed MaS over CORE, cross to 1170-TT-13.
4
Green
MK11 ECC initialization cycle.
5
Green
Cabling MK11 boxes.
6
Green
Tripping circuit breakers during battery backup, cross to
H775-TT-4.
7
Green
MK11 upgrade.
8
Green
Bottom cover shorting to backplane.
9
Green
Enable boot on power-up cable.
10
Green
MK11 fatal SBE's and undetected DBE's
11
SB274
MK11 memory voltage regulator, 70-14251.
12
SB292
Adjustment of memory voltage regulators.
13
SB383
Troubleshooting 1170 MK11 write parity errors, cross to
1170-TT-29
14
SB476
MK11 CSR's verses 1170 $40, $42, cross to 1170-TT-32
I\J1Ji i TECHTiP H\lDEj{
TT #
FICHE
DESCRIPTION
Green
MJ11 B configuration.
2
Green
MM11-U/UP memorys failing high current margins, cross
to MM11-TT-15.
3
Green
Intermittant data parity errors.
4
Green
Memory bus cabling.
5
Green
Core memory upgrade.
6
Green
Core parity errors.
7
Green
BC06R cable testing, cross to BC06R-TT -1.
8
Green
Mixed MaS over CORE on 1170's, cross to 1170-TT-13.
9
Green
MJ11 memory maintenance philosophy.
10
Green
MJ11 cabling procedure.
11
Green
Memory cables.
22
12
Green
MJ11 memory troubleshooting flowchart.
13
Green
H224 cables on MJ11 B.
14
Green
Bottom cover shorting to backplane, cross to
MK11-TT-14.
15
Green
MJ11 strobe timing adjustment.
16
Green
Backplane contact interference from foam and tags.
SHOULD'VE BEEN FCO'S
M8136
Problem:
SACK timeouts, TRAP O's and Unibus timeouts due to improper
clearing of FAIRCHILD, AMD and SIGNETICS 74123's in timeout
logic.
Solution:
Replace E15 and E25with TEXAS INSTRUMENTS 74123's (DEC#
19-10436) if one of the above vendors chips present.
G116
Problem:
Solution:
NATIONAL SEMICONDUCTOR NS7520 sense amps occasionally
generate transient spikes that will effect only other stacks on the
same side (ODD/EVEN) of the box. They do not effect the stack
they are in. This results in transient data parity errors in other
stacks.
Replace G116's that have NS7520's if problem symptom evident.
There are 20 sense amps along the bottom row towards the fingers.
H224
Problem:
Over the top cables get destroyed from adjacent module insertion,
removal and unreliable crimp connections result after several
removals of the cables.
Solution:
Replace any H224's or tape and recrimp damaged cables which
have the above problems.
M8149
Problem:
Mixed mos over core memory configurations require 3 etch cuts to
the M8149 to prevent the unused data bit (byte 1, bit 9) from
rebooting the system th rough the M K11 boot enable. This also
prevents noise problems from the unused data bit (byte 3, bit 9)
and unused data-cable BOCC.
Solution:
Reference PDP1170-TT-13.
M7984
Problem:
Green bypass capacitors burn up causing intermittant data parity
errors.
Solution:
Replace any M7984's with burnt bypass capacitors. This is a good
area to check if you are having intermittant data parity error
problems.
23
CH6\~u[~J\1 (@
A[l)Jl9SuM~~u§
CONTENT
PAGE
CPU REG ADJ
MK11 REG ADJ
MJ11 REG ADJ
TIG ADJ
26
27
27
28
25
11/70 CPU VOL l"AGES, TOLERANCES, AND TEST POINTS
OUTPUT
SLOTS
CPU BACKPLANE PIN V.D.C.
MAX RIPPLE
H744+5V
Regulator A
2-5
F02A2
+5V±0.1
0.2V p-p
H744+5V
Regulator 8
1,6-9
F09A2
+5V±0.1
0.2V p-p
H744 +5V
Regulator C
10-15
F15A2
+5V±0.1
0.2V p-p
H744+5V
Regulator D
36-44
F44A2
+5V±0.1
0.2V p-p
H744+5V
Regulator H
20-22
F22A2
+5V±0.1
0.2V p-p
H744+5V
Regulator J
16-18
F18A2
+5V±0.1
0.2V p-p
H744+5V
Regulator K
24-28
F28A2
+5V±0.1
0.2V p-p
H744+5V
Regulator L
29-35
F35A2
+5V±0.1
0.2V p-p
Upper H7420 1
5411086
80181
+8V±1.2
0.24V p-p
Upper H7420 40-44
5411086
E13A1
+15V±1.5 0.45V p-p
Lower H7420 2,17,25,
27,29-31
5411086
33-35,
37-44
E1382
-15V ±1.5 0.45V p-p
All measurements should be made with a DVM. Ripple must be measured with an
oscilloscope. A YOM is useful for making continuity and resistance checks in the
power supplies.
I
h7420
REGUlATOR
,
I
UPPER POWER SUPPLY
REGULATOR
0
REGULATOR
C
...,
...,
'''''
PROCESSOR
'''''.
CENTRAL
a.MEMQRY
MANAGEMENT
,
REGULATOR
""'"
,,""'-,
'"''
REGU~ATOR
'"
'"
PROCESSOR
""''''
ctNTRAL
FLOATING
LOWER POWER SUPPLY
H7420
h7420
+1.5VTO
"""'"
"""""'"
.
REGULATOR
REGULATOR
'"
"'"
~'"
e
I-
'"
BULK
SUPPLY
,
REGULATOR
...,
CACHE
CONSOLE
REGULATOR
"
,
REGULATOR
~~~SSOR
~HE
"""
"""
'd.
l-
'0.
",,0
l+15VTO
CENTRAL
'"
CACHE
I-
USED
+8VTO
MAINTSLOT
,ow,
+5VTO
36.37,38,39,40
.'.42.43,,,",
+5VTO
ROWS
,OWS
+5VTO
+5VTO
10,11,12,13,14,15
1.6.7.8.9
2,3,4,5
,OWS
~
~
I-
5~TO
26
+5VTO
,OWS
+5VTO
,OW,
+5VTO
ROWS
29,30,31.32
33,3"-35
2425.26.2728
16.17.18
+5vro
~O2~2
M&~11
VOL 'TAGle ADJUSTMIeNTS, TOLERANCES AND TEST POINTS
OUTPUT
SLOTS TEST POINT V.D.C.
MAX RIPPLE
H7441 +5V
10-17
J21-7
4.9_5.3V
200MV pp
6-13
J18-4
J18-5
J18-7
200MV pp
4.9 - 5.3V
250MV pp
11 -13V
-10.5 _ -13.5V 250MV pp
15-21
J21-5
J21-4
J21-2
200MV pp
4.9 -5.3V
250MV pp
11 -13V
-10.5 _ -13.5V 250MV pp
22-25
2-5
J21-6
J21-3
J21-1
200MV pp
4.9-5.3V
11 _13V
250MV pp
-10.5 - -13.5V 250MV pp
REGULATOR "A
70-14251 +5VB
+12VB
-12VB
REGULATOR B
70-14251 +5VB
+12VB
-12VB
REGULATOR C
70-14251 +5VB
+12VB
-12VB
LAYOUT
REG
C
REG
B
AC
INPUT
BOX
#7441
REG
A
MJ11 VOL TAGlE ADJUSTMIENTS, TOLIERANCES AND TEST POINTS
OUTPUT
M8149 (TP7 GND)
SLOTS TEST POINT
REGULATOR #1
H754 +20V
-5V
VDC
MAX RIPPLE
TP4
TP6
+20
-5
± 1.0V 1.0 V pp
± .25V 250MV pp
TP2
+5
± .25V 200MV pp
REGULATOR #3
H754 +20V
-5V
TP3
TP5
+20
-5
± 1.0V 1.0V pp
± .25V 250MV pp
REGULATOR #4
H744 +5V
TP1
+5
± .25V 200MV pp
REGULATOR #2
H744 +5V
LAYOUT
REG
#4
REG
#3
AC
INPUT
BOX
27
REG
#2
REG
#1
•
11170 TIG BOARD (M8139) ADJUSTMENTS
Procedure for adjusting 11170 TIG Boards.
1. Install M8139/09 on Extender.
2. Monitor E32-8 with an oscilloscope (be sureto use a ground lead on probe).
3. Adjust L 1 tank circuit in XTAL oscillator for oscillation by turning tuning
slug all the way in (don't over-tweak, it is a ferrite core and will break) then
turning counter clockwise until oscillation just starts then continue one and
one-half turns more.
Note: refer to figure 1 for the following symmetry adjustments. (Oscillator
Symmetry.)
4. While monitoring E32-8 adjust R130 (R211 if M8109) for a symmetrical
15 ns for each half cycle.
5. Phase Splitter Symmetry
a. Monitorsignal T1G C TF L (backpanel pin ER2 oremitter lead of 057 or
058.) Adjust R129 (R21 0 for M81 09) for a symmetrical 15 ns for each half
cycle.
b. Monitor signal TIG C TF H (backpanel pin DM2 or emitter lead of 051
or 052) Adjust R128 (R209 for M8109) for a symmetrical 15 ns for each
half cycle.
c. Recheck steps A & B, as they may interact, and readjust if necessary.
6. Reinstall TIG Board in machine and monitor backpanel pins in steps5A and
5B to insure extender board did not cause a gross loading/mismatch problem.
FIGURE 1 REPRESENTATIVE WAVE FORM
Frequency
= 33.333
Rise time
Fall time
2 NS
2 NS
MHZ (period
= 30
NS ± 0)
Rise and fall times are measured between .8V & 2V
Symmetry measurements are easiest made when ground reference is set at
1.5 V below center line and centerline is used as reference during adjustment.
1.5 V REF
-----f_---------+--------~f_-
¢V REF
1-1
TR
I-
TF
15 NS
I-
-1
30NS
28
·1
C~JA~VE~
~WruCHE§, Jl!lM~E~S
"7
AND
~ND~CAVO~S
CONTENT
PAGE
CPU
MK11
MJ11
RH70
KY11-R
FP11-C
1170 BACKPLANE
PDP11 WIRE COLOR CHART
1170 DC POWER USE CHART
30,30A,31
32
35
38
39
42A
42B
42C
42C
29
•
M8i30 START VECTOR JUMPERS
JUMPER
W1
W2
W3
W4
W5
W6
W7
W8
W9
FUNCTION WHEN IN
'START VECTOR BIT 2
START VECTOR BIT 3
START VECTOR BIT 4
START VECTOR BIT 5
START VECTOR BIT 6
START VECTOR BIT 7
"START VECTOR = 173000 + XXX
PUSH BUDON BOOT 173000 + XXX
IW7 MUST BE OUT)
PUSH BUDON BOOT 173200 + XXX
IW7 MUST BE OUT + W8 IN)
'START VECTOR BITS 0.1 ALWAYS = 0
"XXX = OFFSET FROM W1 THRU W6.
STANDARD SETUPS: 1
JUMPER
W1
W2
W3
W4
W5
W6
W7
W8
W9
= JUMPER INSTALLED
M9301/M9312
(NO BOOT SW)
M9301
(BOOT SW)
M9312
(BOOT SW)
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
M8i36 SACI( TIME OUT LED
IF NO RESPONSE (SACK) IS
RECEIVED FROM THE UNIBUS 10
MICROSECONDS AFTER A UNIBUS
GRANT (NPG OR BG) IS ISSUED THE
SACK TIMEOUT LED IS LIT. IT'S
RESET BY INIT.
•
SACK TIMEOUT
M8136
30
M8"132 FLOATING POINT SELECTION JUMPER
W1 in
W1 out
=
FP11-B
= FP11-C
M8137 PLFE JUMPERS (PDR /SiT 15)
II
Wl W2
W1 in, W2 out
*W1 out, W2 in
=
=
Normal
Reserved
*This Reserved Jumper configuration connects the extra bit in the PDR registers to bit 15. This
bit is not used or supported by any operating system and should be left grounded by having
W1 in and W2 out.
30A
MB140 SYSTEM SIZE AND ID flEGISTEfl SWITCHES
ALL SWITCHES ON
=
0 OFF = 1
SYSTEM ID REGISTER
M8140
NORMALLY NOT USED, HOWEVER
IT'S CONTENTS CAN BE CHANGED
BY SETTING SWITCHES IN THE
HIGH/LOW BYTE SYSTEM ID SWITCH
PACKS.
31T 6
4
7
1
5
0
3
SYSTEM SIZE REGISTER
2
THIS REGISTER MUST BE SET TO
REFLECT BITS 21 THRU 14 OF THE
LAST PHYSICAL MEMORY ADDRESS.
BITS 13 THRU 1 ARE ALWAYS 1's.
SYSTEM ID (LOW BYTE)
BIT 12
8
11
15
13
14
10
9
EG: 1024 K WORDS MEMORY
LAST ADDRESS = 07777776
BITS 21-14 = 01111111111
SWITCH SETTING LEFT TO RIGHT IS
SYSTEM ID (HIGH BYTE)
BIT 17
21
20
16
18
14
19
15
OFF, ON, OFF, OFF, OFF, OFF, OFF,
OFF
NOTE: EMKABO WILL INFORM YOU IF
THE SWITCHES ARE SET WRONG
AND GIVE YOU THE CORRECT
SETTINGS.
SYSTEM SIZE REGISTER
M8141 MAP LIMIT JUMPERS
M8141
W3
W4
W5
W6
W7
W8
W10
W9
W2
W1
ADDRESS BIT
13
14
15
16
17
LOW LIMIT
W2
W10
W9
WB
W7
HIGH LIMIT
W1
W6
W5
W4
W3
31
THE STANDARD SETUP FOR THE
MAP JUMPERS IS W1, W3 THRU W6
OUT AND W2, W7 THRU W10 IN. THIS
GIVES A MAPPING RANGE OF
ADDRESSES FROM 0 TO 757776. THE
JUMPERS ALLOW YOU TO CHANGE
THE UPPER OR LOWER LIMIT IN 4K
INCREMENTS. TO SET UP THE
JUMPERS SELECT THE UPPER AND
LOWER ADDRESS LIMIT YOU WANT
THE MAP TO USE FROM THE RANGE
OF 0 TO 760000 (0 to 124K). THEN
USING BITS 17 THRU 13 SET UP THE
JUMPERS USING THE FOLLOWING
TABLE.
NOTE: JUMPER REMOVED = 1
JUMPER INSTALLED = 0
MG145 MASSGUS PRIORITY JUMPERS
MBC SELECTION PRIORITIES IM8145)
JUMPER CONFIGURATION
W1
OUT
OUT
OUT
OUT
IN
IN
IN
IN
M8145
W3
W2
W1
W2
OUT
OUT
IN
IN
OUT
OUT
IN
IN
PRIORITY STRUCTURE'
W3
OUT
IN
OUT
IN
OUT
IN
OUT
IN
(A-S)-(C-D)
(A-SHC-D)
(A-SHC-D)
(A-SHC-D)
(A-S)-(C-D)
(A-SHC-D)
(A-SHC-D)
(A-S)-(C-D)
* A-B indicates the expression on the
left has a higher priority than that on
the right (A over B).
B-C indicates the selection alternates between the expressions on
either side of the symbol.
NOTE: TO AVOID PROBLEMS JUMPERS W1 THRU
W3 SHOULD ALL BE "IN", GIVING SEQUENTIAL
PRIORITY FROM RH70 "A" TO RH70 "D".
(A-B)-(C-D) indicates group A-B
is over group C-D and A is over B. A
has the highest priority and D the
lowest.
Mt(11 SWITCHES, INDICATORS AND JUMPERS
CorJTROL PAtJEL SETUP, ItJIlICATORS
SOXCONTROLLER
o
0
BATTERY STATUS
LEO'S
lIfUMBWHE[l
SWITCHES
1.
2.
3.
4.
~~~lEl~~~l
FUNCTION
FAST CHARGE
SLOW CHARGE
DISCHARGE
BATTERY OFF
SLOW FLASH
ON
FAST FLASH
OFF
INTERLEAVE
f>I10GCONTROL
o NO EXT INTERL
1 NOT USED
2 (2) WAY EXT INTERL BOX 0
3 (2) WAY EXT INTERL BOX 1
4 (4) WAY EXT INTERLBOXO
5 (4) WAY EXT INTERL BOX 1
6 (4) WAY EXT INTERL BOX 2
7 (4) WAY EXT INTERL BOX 3
INDICATES
SI AOO~ & INT
,.,
BtiNGIAKEN
THUMBWflEEL
SWITCHES
STARTING ADDRESS
PAN~ K
MA1326
INTERLEAVE SWITCH SETTINGS ON FRONT
CONTROL PANEL
A03 A02
=0
=1
Sox 0 = 2 X
Sox 1 = 3 X
Sox 0 =4 a
Sox 1 = 5 a
Sox 2 =6 I
Sox 3 =7 I
Not interleaved
Invalid
.2-Way:
.4-Way:
a
I
2-Way
a
I
a
SET
WORDS
000
001
002
003
004
005
006
007
010
011
012
013
014
015
016
017
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
4-Way
I
32
a
PAN~Yw
K
PAN~Yw,
K
SET WORDS
SET WORDS
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037
512
544
576
60B
640
672
704
736
768
800
B32
864
896
928
960
992
040
041
042
043
044
045
046
047
050
051
052
053
054
055
056
057
1024
1056
10B8
1120
1152
11B4
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
PANVw,K
SET WORDS
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077
1536
156B
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
Starting Address
• Box 0 starting address = 0
• Box 1starting address = amount of
32K memory contained in Box 0 in
octal
MKll CONFIGURATION RULES
• Local/Remote switch on 861 bulk
power supply must be in local.
• All core must be closest to CPU
(physically).
• MOS Memory closest to controller
in the following order:
32K modules (4K chips)
32K modules (16K chips par
populated)
128K modules (16K chips fully
populated)
• No empty slots between arrays.
• SW1-8 on M8158 to Off (open) for
test (allows one to access CSR
directly). This switch is On
(closed) for PDP-11/70.
• Terminators must be screwed in
tight as the screws supply power
and ground to terminator.
Conditions for External Interleaving
• Number of boxes must be even.
• Boxes must have same capacity.
• Boxes must have same starting
address.
Conditions for Internal Interleaving
• Number of array cards within a
box must be even.
• Each pair of array cards must be
identical.
r.18159/f,10164 SWITCHES, ItJDlCATOR
ALL 11/70's WITH MK11 SHOULD
HAVE A CONTROL PANEL. IF FOR
SOME REASON YOU NEED TO RUN
WITHOUT THE PANEL, YOU CAN SET
IT UP USING THE SWITCHES.
M8159/64
E46SW
FUNCTION
E55SW
ADRS BITO
1
2
3
4
5
6
7
ALL SWITCHES MUST BE OFF
TO USE THE MK11 CONTROL PANEL
FUNCTION
ADRS BIT 8
INTERLEAVE BIT 1
INTERLEAVE BIT 0
INTERLEAVE BIT 2
FORCE PANEL ADRS.
ECC DISABLE
DOUBLE ERROR = MEMORY HAS AT LEAST ONE DBE
LOCATION
r-18HiB SWITCHES, JUmPERS, ItJDlCATORS
ADDRESS
PARITY
ERROR
•
•
CONFIG.
ERROR
CSR SWITCHES
'1
BOX NO.
M8158
8
51
W1 W2
W3 W4
%% %%
33
CSR ADDRESS
17772100
17772104
17772110
17772114
SI SWITCH POSITION
81-3
81·2
SI·1
ON
ON
ON
ON
OFF
ON
OFF
ON
ON
OFF
ON
OFF
SWI-4 THROUGH SW 1·7 NOT USED.
SWI-8 MUST BE "ON" FOR THE 1170.
•
POWER FAIL JUMPERS
LAST MEMORY ON BUS
ALL OTHER MEMORY BOXES
WI
W2
W3
OUT
IN
OUT
W4
IN
IN
OUT
IN
OUT
CONFIGURATION ERROR
" SPACE IN MEMORY ORDER
" MOS MEMORY IN WRONG ORDER.
ADDRESS PARITY ERROR
" INCOMING ADDRESS HAD BAD PARITY.
rJlB160 IrJDICATOR
BUSY LED - MEMORY IS BUSY.
M8160
•
BUSY
rJl79B4 JUMPERS,
I~JDlCATOR
JUMPERS W1-W10 SELECT MEMORY
SIZE AND CHIP TYPE. THEY ARE
FACTORY SET AND SHOULD NOT BE
ALTERED.
M7984
10
9 B
II
17
6
I ::: i
1 ......... 2
4
..... 1
LED (GREEN) INDICATES MODULE IS
RECEIVING +5V.
MB72B JUMPERS, ItJDlCATOR
LED
THERE ARE 23 JUMPER LOCATIONS
(W1-W23) ON THE MODULE WHICH
ARE FACTORY SET FOR MEMORY
CHIPS AND SHOULD NOT BE
ALTERED.
M8728
LED (GREEN) INDICATES MODULE IS
RECEIVING +5V.
34
MJ1'l SWITCHES, INDICATORS AND JUMPERS
IVlS'147/8 ADDRESS/INTERLEAVE SWITCHES AND INDICATORS.
M8147/8
1. Hi and La stacks must be same
size.
• MISMATCH ERROR
• CONFIGURATION ERROR
• ADDRESS PARITY ERROR
52
BUSY.*
2. All 16K stacks must occupy
addresses lower than 32K stacks
(within same box).
3. Starting address switches:
• Not Interleaved
a. Count the multiples of 32K
below this box.
b. Insert that binary number
in the starting address
switches .
• Interleaved
a. Same as above, but both
boxes must have same starting address and amount of
memory.
b. Set the Interleave switch for
INTLV on both boxes.
c. Set the ODD/EVEN switch to
EVEN on the first box and to
ODD on the second box.
ON=O
OfF=t
S2·3 Off = INTERLEAVE ON; 52·3 ON = INTERLEAVE OFF
S2·4 OFF = ODD BOX; S2·4 ON = EVEN BOX
BIT 16
17
18
19
20
21
22"
16K MODULES
1M MAX
'BUSY LED IS BELOW ADDRESS PARITY ERROR LED ON M8147
"BIT 22, 23, 24 NOT USED
M8148
M8149
Gl14
G235
H217C
7010497
ADRS/CONTRL
DATA XCVR
SENSE/INH
DRIVE
STACK
BACKPLANE
32K MODULES
2M MAX
M8147* ADRS/CNTRL
M8149 DATAXCVR
Gl16
G236
H224C
7010497 with ECO • 04
'M8147 will work with 16K and/or32K
stacks.
'Insure screws are installed tightly in
terminators as they connect power
and ground to the terminator.
LED'S
MISMATCH ERROR
- HI AND LOW STACK PAIR NOT THE SAME SIZE.
CONFIGURATION ERROR -16K STACKS NOT BEFORE 32K STACKS.
ADDRESS ERROR
- PARITY ERROR DETECTED ON INCOMING ADDRESS.
BUSY LED
- MEMORY IS BUSY.
35
•
G23S/G236 BIAS CURRENT, STROBE JUMPERS AND FUSES
REFER TO ADJUSTMENT PROCEDURE
BEFORE ALTERING JUMPERS.
(IN = 1: OUT = 0.)
BIAS JUMPERS:
W7
G235
3 2 1
I II I
W6
W5
0
1
0
0
0
0
0
1
1
1
1
5 6 7
III
....•......... G236 MODULE
HIGHEST CURRENT
LOWEST CURRENT
STROBE JUMPERS:
W4
WI
4321
10 9
G236
II
W2
W3
0
0
0
0
I
11
7 6 5
III
Fl
W3
W4
0
a
0
a
W8-Wl1 MUST BE INSTALLED
W8 = IN = X READ CURRENT SOURCE
W9 = IN = Y READ CURRENT SOURCE
Wl0 = IN = X WRITE CURRENT SOURCE
Wll = IN = Y WRITE CURRENT SOURCE
(IN = 1: OUT =0.)
WI
W2
0
1
0
1
0
0
1
1
0
1
0
1
0
a
1
1
0
1
a
1
0
0
1
1
a
1
a
1
.......•..•....•. G236
.....•.•..•....•. G235
LA TEST STROBE
0
0
0
0
EARLIEST STROBE
Fl = 3/4 AMP PIca FOR +20 VOLT
G114/G116 FUSES
ALL FUSES 3/4 AMP PICD
............
500'5
300'5
400'5
-- .........
200'5
100'5
G114
G114 FUSES
36
G114
G116
FUSE FUSE
101
102
103
104
201
202
203
204
301
302
303
la
9
12
11
2
1
4
3
6
5
8
INTERNAL BUS
DATA BIT
PDP 1170
BYTE· BIT
19
18
17
16
15
14
13
12
11
10
09
I-PARITY, 3-PARITY
NOT USED
NOT USED
a-PARITY, 2-PARITY
1-6,3-6
1-5,3-5
1-4,3-4
1-3,3-3
1-2,3-2
1-1,3-1
1-0,3-0
FUSE LAYOUT EXAMPLE:
F104
304
401
402
403
404
501
502
503
504
F103
F102
F101
7
14
13
16
15
18
17
20
19
08
07
06
05
04
03
02
01
00
1-7,3-7
0-7,2-7
0-6,2-6
0-5,2-5
0-4,2-4
0-3,2-3
0-2,2-2
0-1,2-1
0-0,2-0
G116
64
58
51
45
39
'EI
21
E14
EB
EI
G116 FUSES
H217 JUrllPERS
H217
--WI
W1
+ W2 = TEST PURPOSES ONLY
00 NOT ALTER
W2
H224
H224 JUMPERS
.......
W3
W1. W2. W4NOT
VISABLE
W1 THRU W4 = TEST PURPOSES ONLY
DO NOT ALTER
37
r.lC-J70 JW\IlPEr.lS AND
INDICATO~S
ADDRESS SelECTION
f.10153 JUf.1PEIIS JWD IfJDlCIlTDIIS
Q._-
0:
---0
000
!
!I\
SSYN
8BSY SACK BGIN
JUMPER
ADDRESS BIT
W14
W10
W9
W8
W11
W13
W15
W12
12
11
10
9
8
7
6
TRA
M8153
W4 ••. -~---13
Wl • •
5
W5 • •
WI • •
JUMPER IN = 0
JUMPER OUT = 1
IW • •
W3 ••
WI • •
# OF REGISTERS SelECTION
JUMPER
SET THE JUMPERS (E41) TO SELECT >20 OR <20
REGISTERS AND FOR THE NUMBER OF REGISTERS
MINUS 2 BY THE BINARY WEIGHT.
JUMPER
>20 REGISTERS
<20 REGISTERS
1-16
2-15
3-14
4-13
OUT
OUT
IN
IN
IN
IN
OUT
OUT
JUMPER
BINARY WEIGHT
5-12
6-11
7-10
8-9
2
4
8
VECTOR SELECTION
ADDRESS BIT
W7
W3
W6
W2
W5
W1
W4
2
3
4
5
6
7
8
JUMPER IN = 1
JUMPER OUT = 0
lED'S
JUMPER OUT =
BINARY WEIGHT
16
EG. RWP04 HAS 22 REGISTERS, SO JUMPERS AT
E41 (FROM TOP TO BOTTOM) WOULD BE OUT,
OUT, IN, IN, IN, OUT, IN, OUT
TU/TE16ITU45ITU77 HAS 16 REGISTERS, SO
JUMPERS AT E41 (FROM TOP TO BOTTOM)
WOULD BE IN, IN, OUT, OUT, OUT, OUT, OUT, IN.
THE FOLLOWING STATUS LED's ARE
PROVIDED FOR TROUBLE-SHOOTING
-
TRANSFER (TRA)
BUS GRANT IN (BG IN)
SELECTION ACKNOWLEDGE
(SACK)
BUS BUSY (BBSY)
SLAVE SYNC (SSYN)
r.18150 JUr.1PERS
M8150
W3 W1
II II
W4
W2
38
JUMPERS W1 THRU W4 ARE USED
TO ISOLATE PROBLEMS IN THE
WRITE CHECK ERROR CIRCUIT.
REFER TO PRINT SET PAGE MDPE.
I{Yl1-A JUMPIEFlS AND SWITCHES
M8255 Jumper Descripiion and Configuraiion
Jumper
Jumpers Installed
At Factory For
ROM Configuration
1Kx8
2Kx8
Description
IN/OUT State
W1
W2
Factory use only
Steal Grant L
W3
KW11-L option
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
IN
OUT
IN
OUT
IN
Always IN
OUT on CS Rev F and
earlier to disable
I N on CS Rev H to enable
IN to disable KW11-L
equivalent logic
OUT to enable KW11-L
equivalent logic
OUT
IN
OUT
IN
OUT
OUT
IN
IN
OUT
There is no W10
OUT
IN
IN
OUT
OUT
IN
M8255 ROM/PROM Configuraiion
M8255
Variant
Microcode
Version
ROM or
PROM
-00
V01
1Kx8
UV EPROM
(with windows)
00787
00887
00987
01087
-00
V01
2Kx8
Masked ROM
(without windows)
013E2
-
014E2
-
-00
V02
2Kx8
UV EPROM or
Masked ROM
175E2
176E2
177E2
178E2
-01
V02
2Kx8
UV EPROM
(with windows)
075E2
077E2
076E2
121E2
E52
39
In ROM Location
E46
E38
E31
C
J1
8255A
1
~
W2
R11
D
8647
or
DC013
W1
W11
~W12
W9 W8
W7 W6
@]
W13
W14
~
~
8080A
NOTE
J2 FOR FACTORY
USE ONLY
~
W3
J2
R20
~
W5
W4
NOTES: - KY11-R IS A DMA DEVICE, THEREFORE YOU MUST REMOVE BACKPLANE
JUMPER CA1-CB1
- KY11-R CAN ASSERT AC LOW ON THE UNIBUS.
40
THIS 20K OHM RESISTOR (R26)
MUST BE REMOVED FROM
ALL-01 VARIANT BOARDS
I
01
r
J1
1r
J3
1
C
J2
1r
J4
JC
0
~
20KOOO1K
J5
J
J8
JC
0
~ ~ ~
~~ ~ 0
~
1 ern
J6
0
UART-E6
rnLJ
UART-E5
E12CJ
54-12781
MULTIPLEXER
I
I
c::JE4
,----., J
W1-W12r::::=J c::JE3
o
: E16 :
I..---~
o
I
rrrrrrrriirr
N ~ 0
...-..- ......
O'lCCr--.c,olO
"'2"MN...-
;;:;;:;;: ;;:;;:;;:;;:;;:;;:;;:;;:;;:
11ll111l1111
54-12781 JUrnPER CmJFIGURATlDrJ ArlO LAYOUT
System Terminal Fill Character Selection
54-12781 DIP Switch E19
Switch
Setting
Function
S1
N/A
Unused_
S2
N/A
Unused_
S3
OFF
Four fills after LF (VT05)_
ON
No fills after LF_
S4
OFF
Eight fills after CR.
ON
No fills after CR.
S5
OFF
Gate electronic console status bits into transmitter control and status register_
ON
Suppress electronic console status bits_
OFF
Reserved for future use_
S6,7,8
Usual switch settings for LA34, LA36, LA38, LA 120:
S3 = ON, S4 = ON, S5 = ON_
41
0
•
Console Terminal 20 mA Loop Option Selection
54-12781 DIP Switch E28
Mode
Transmitter Switches
S1
S2
S3
S4
Active*
ON
Passive
OFF ON
OFF
ON
S5
OFF ON
OFF ON
Receiver Switches
S7
S8
S9
S6
S10
OFF ON
ON
ON
OFF
OFF
OFF ON
OFF ON
OFF
* Standard LA36 switch setting, active mode
Baud Rate Selection
54-12781 DIP Switch E3
Baud
Rate
110
300*
600
1200
1800
2000t
2400
3600t
4800
7200
9600
INVALID
Transmit:
Receive:
S1
S2
S4
S3
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
*Standard switch settings for LA36 (300 Baud)
tNot compatible with LA 120
42
S6
S5
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S7
S8
ON
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
L=P1-i-C JlH\JlPI2RS
Ma"l2a FLOATING POINT START/ATTEN DELAY JUMPERS
-W1
-W2
W1 in, W2 out = Normal
*W1 out, W2 in = Reserved
*This Reserved Jumper configuration adds 5ns to 7ns delay onto the FP START and FP ATTEN
signals from the CPU (reference FRMC)_ This is not used and the Jumpers should always be
set normal, W1 in and W2 out.
42A
•
GENERAL 11/70 JUMPERS
The following is a list of backplane jumpers useful in troubleshooting 1170
problems.
Bec!tp!ane:
To disable Cache Data Memories
Group 0 C17L 1 To ground
Group 1 C17J1 To ground
To remove KW11 L
Jumper D1R2 to D1V2
To remove any NPR device in CPU backplane
G7273 in C and D row of affected slot or
G727 in D row and jumper C4XA1 to C4XB1
To run off RC clock on M8139 TIG module in place of crystal clock
F13J1 to ground
To clear MJ11 memory box address error LED without powering off
TP2 to ground
42B
WIRE COLORS r-OR PDP"I"I VOLTAGES
Voltage
Color
+8
+5
-15
+15
-5
AClO
DClO
+20
LTC
GND
white
red
blue
grey
brown
yellow
violet
orange
brown
black
1170 MODULES DC POWER USAGE
Voltage
Modules + Circuit Usage
Pin
+5
All
All TTL Chips
AnyA2
+15
M8139
SPC's
Clock Circuits
Unique to Device
E13A1
CxxU1
BxxN2
-15
M8139
M8142
M5904
M8126
Clock Circuits
SYNC Clock
Transceivers
FP Clocks on FRHM
E13B2
E17B2
AxxB2
E02B2
+8
FP11-B
KB11-8/C
Maintenance card
Maintenance card
A01B1
80181
42C
CHAf=DVE~ ~
C~l!J
CONTENT
PAGE
MODULE LAYOUT
11170 REVISIONS
MODULE DESCRIPTION
DATA PATH BLOCK
ADD PATH BLOCK
PARITY NETWORK
CPU BLOCK
ROM TIMING, BIT USAGE
ABORTS, TRAPS, AND INTERRUPTS
CPU REGISTERS
CHART OF MEMORY SIZE
CPU ERRORS
PAUSE CONDITIONS
DATA XFER TIMING
AC LOW/DC LOW CONNECTIONS
44
44A
45-48
43
49
50
51,51A
52,53
54,55
56,56A,57
58
58A,58B
59
60-64
65
67
o
"
o
N
,."
~.,
:;!
'"
"::i
it
W//,///h
KW11
M9301 - YC
2~
FAH M8126
;;
FAL M8127
to
\
"
"
~
! -
FRM
"
I
M8128
FXP M8129
FPMAINT
~
C,
OAP M8130
1
~ '""
~ "''""
{'""
{"
I
CPMAINT
GRA
M8131
IRC M8132
lln
i~
RAG M8123·
b
PDR M8134
<5
k;
TMC M8135
USC
co
M813(i
~[
TIG M8139
SAP
}~~
M813?
~~
SSA M8138-YA'
b
f//// //////1/1IIIIm 7771l7T1777TTn71l
I
b"
T
I
T
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------------- ----- - -- - - -- - --T
&i[ tJ
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MBSS M5904
BCT
MBse M5904
~
"'"
<:l
"i
"l
'"
ill
~
"
MalS1
MBSA M5004
AWA
M81S2
MBSS
BCT
M8153
MBse M5904
0
~
~
CST
MalS!
MBSA M5004
AWA
M81S2
MBSS MSOO4
BCT
M8153
MBse M5904
tJ
MBSA M5004
~
CST
M81S1
0
AWA
M8152
MBSS M5004
BCT
M8153
M8se
I '"
il<[
T
MOP M8150
<3
b
M5904
-r
MOP M8150
M5004
M7800-YA (OUI-AI
OPTIONAL SPC
f$
OPTIONAL SPC
t:;
OPTIONAL SPC
to
OPTIONAL SPC
~z
M9302 (SEE NOTE 1)
iI ~:~-:~~;:~=:,;;::a: l ~o ~
:;
9
o~o=o~o~o~o~o~o~o~
0
z
z
o~o~o~o~o~o~o~o~o~
I O~O~O~O~ONO~O~O~O~
I~: ~
m~
~
I ~I ~
L __________ J-
i
1);
~
T
CST
kl
'"
"'
M8153
MOP M8150
"i
! '"
Ie
M8SA M5004
MB1S!
AWA M81S2
ill
ill
o~
~~
--~
M8141
----- -
MOP M8150
~
~~
~n
COP M8145
[:l
t;;
:-i~
t;
iii
FIGURE 8-1
44
11170 REV. LEVELS
Module
Etch
CS Rev.
M8126
M8127
M8128
M8129
C
C
C
C
C
B
B
B
FRH
FRL
FRM
FXP
M8130
M8131
M8132
M8123
M8134
M8135
M8136
M8139
A
C
B
C
C
A
C
B
D
D
D
B
E
F
D
DAP
GRA
IRC
RAC
PDR
TMC
UBC
TIG
M8137
M8138VA
M8140
B
A
SAP
B
A
F
B
SSR
SCC
M8142
M8143
M8144
M8145
B
B
A
B
F
B
C
ADM
DTM
CDP
M8141
A
A
MAP
70-10329
WL>M
WT>S
BACKPLANE
44A
•
DAP (M8130) DATA PATHS
A
B
C
o
E
F
H
J
"BR" Register
"A", "B", "BA" MUX
"A", "B", "BA" MUX
"A", "B", "BA" MUX
"KI" MUX, TRAP and START Vectors
SHFR (0-5) PCA and PCB (0-5) ALU (0-7)
SHFR (8-14) PCA and PCB (6-15) ALU (8-15)
SHFR 7&15
GRA (M8131) GENERAL REG AND ALU CONTROL
A
B
C
o
E
F
H
J
K
ALU Shr. Cont. and ALU sub ROM, swap byte in SHFR
SHFT = zero detector
Gen. Purpose Reg. Address
GS, GO, "SR" MUX, "DR" MUX, "DR" (0-3) SR (0-5)
GS, GO, "SR" MUX, "DR" MUX, "DR" (4-7)
GS, GO, "SR" MUX, "DR" MUX, "DR" (8-11) SR (6-11)
GS, GO, "SR" MUX, "DR" MUX, "DR" (12-15)
Shifter Counter
ALU Control ROM Chart
IRC (M8132) "IR" DECODE AND COND CODES
A
B
C
o
E
F
H
J
"IR" Register (0-15)
"B" Fork, IR Decode
"C" FORK, IR Decode, Source Const.
Instr. Traps, Destination Const.
Condition Codes "V" Bit
Condition Codes "C", "N", "Z"
Condition Code Bits
Inst. Decode ROM Maps
KNL CONSOLE BOARD
A,B,C,D
PDR (M8134) PROC DATA AND UNIBUS REGISTER
A
B
C
o
E
F
H
J
"BR" MUX
"BRA" Register, Light Register
Program Brake Register, Stack Limit
Prog. Interrupt, Proc. Status Register
"0" MUX Register to Unibus
Data Display MUX
HI and LO Parity Bit, J1 Cable Conn.
Bus Buffer Register
RAC (M8123) ROM and ROM CONTROL
A
B
C
o
E
F
H
J
ROM Bits 48-63 (zap 200 generated)
ROM Bits 32-47
ROM Bits 16-31
ROM Bits 00-15
"A" Fork Logic
"A" Fork Logic
"A" Fork Logic
Instruction Reg. ("A" Fork)
45
K
l
Branch Conditions (ROM, ADD, MOD) (BEN +20, +40)
ROM Address Selection
TIG (M8139) TIMING GENERATOR
TMC (M8135) Traps and Misc. Control
A
B
C
o
E
F
Priority ARB. (Order of Sequence Chart)
Priority ARB Trap Vectors (BOR True)
Add Error, Odd Address Error, etc.
CPU Reg. (Bits 2-7) Internal Stack Limit
MSC, BCT, BSC, Decode
"BR" MUX Selection FP Read
UBC (M8136) UNIBUS AND CONSOLE CONTROL
A
B
C
o
E
F
H
*
*
MSYN, BBSY, Timeout, CP BSY
Parity and Timirlg Cont. (Parity, Error, PE Abort, TIG Restart)
Restart Canst. (BUS SYNC INTRF, RESET INTR)
BUS ARB. (External BRO, No Sack, Proc BR4-BR7)
PWRF Control (BUS, OClO, Int. BUS, Start Init)
Console Cont. (Console ACK, Stop, Start, Continue)
Console YAOR (Reg. Exam and Step, Clear, Conf)
Timing Diagram
Flow Chart for Unibus Hand Shaking
ADM (M8143) ADDRESS MEMORY BOARD (CACHE)
A
B
C
o
E
F
H
J
K
l
*
TAGO (add. for TAGO Bits 14-21)
TAGO (add. for TAGO Bits 13-10) and TAGO Valid, and Par A, Par B)
TAG1 (add. for TAG1 Bits 14-21)
TAG1 (add. for TAG1 Bits 13-10) TAG1 valid and Par A, Par B)
Address MUX (0-11)
Address MUX (12-21)
MBC Add. Buffer (MBC AOO-A21) (CO-C1)
Byte Mask, Pup Sequencer
Equals Check, Parity Check (Group 0+1 hit, group 0+1 match)
Main. Memory Add. Drivers (AORS 2-21) and Memory Signals
TAGO and TAG1 Block Diagram
CCB (M8142) CACHE CONTROL
A
B
C
o
E
F
H
J
K
l
M
*
Initialize and Clock logic
Request Arbitration
Oatip and End Cycle Control (Mem Sync, Done, UB ACKN)
Main Mem. Control (Start, Timeout, Slow Cycle, Start Slow)
Timing and Main Mem. Restart (Disable Req. Mem Sync Slow)
Reg. Data Path (Reg 000-015)
Error ADS Reg. and Decode (ERR Add. 00-21, CO+C1)
Cache Error Reg. (Bits 10-15)
Cache Error Reg. (Bits 0-9)
Cache Maint. and Hit Reg. (Hit Reg 0-5) Maint. Mode
Valid and Write Select logic (Valid Input, Write Sel.)
Register Bit Breakdown Chart
COP (M8145) CACHE DATA PATH
A
B
BO Register (BOOO-B031)
Data MUX (Even MUX 000-015) (Odd MUX 016-031)
46
C
D
E
F
H
J
K
*
Main. Memory Even Word (Main Data Byte 0 [0-7] and Main Data Byte 1
[0-7]
Main. Memory Odd Word (Main Data Byte 2 [0-7] and Main Data Byte 3
[0-7]
Write MUX (Write MUX 00-15)
Memory Parity Control (Main Hi Parity OK, Main LO Par OK, MUX
Byte 0-3)
MBC Request (Areg, Breg, Creg, Dreg, Block A-D)
MBC Arbitrator (Req, Clk, Init A, Sel Data Ctrl A.B,C,D)
MBC Data Control (Read "B", RDY CLK' Data RDY, RIP, Data RDY CNTRL
A-D)
Cache Data Path Flow Chart
DTM (M8144) DATA MEMORY
A
B
C
D
E
F
H
J
K
L
M
N
P
*
*
*
*
*
*
Address Drivers (WRD 0-3 A02H and WRDO-3 A03H and WRDO-3 A04H)
Write Pulse Drivers and Chip Select Dri. (CSO-3 and Write Hand A01 L)
Word 0 Hi Byte (Even MUX D08-D15 and Group 0 Hi Par H)
Word 0 Lo Byte (GRPO D07-DOO and Group 0 Lo Par H)
Word 1 Hi Byte (GRP08-15 and GRPO Hi Par H)
Word 1 Lo Byte (GRPO D07-DOO and GRPO Lo Par H)
Word 2 Hi Byte (GRP1 D08-D15 and GRP1 Hi Par H)
Word 2 Lo Byte (GRP1 D07-DOO and GRP1 Lo Par H)
Word 3 Hi Byte (GRP1 D08-D15 and GRP1 Hi Par H)
Word 3 Lo Byte (GRP1 D07-DOO and GRP1 Lo Par H)
Data Output MUX (CDMX DOO-D15 and Bad Parity H)
Fast Memory Parity Checkers (Data Par 0 OKL and Data Par 1 OKL)
Main Memory Data Inverters (Even MUX 00-15 and Odd MUX 15-31)
Memory Management Block Diagram 1.
Memory Management Block Diagram 2.
Memory Management Registers
Cache Address Timing
INternal REgisters Cycle Timing
Mem. MGMT Trap Timing
SAP (M8137) SYSTEM ADDRESS PATH
A Kernal Page Address Registers (PAF06-PAF21)
B Supervisor Page Add. Reg. (PAF06-PAF21)
C User Page Add. Reg. (PAF06-PAF21)
D Kernal Page Description Reg. (APR ADDRO-3 and WRTN Data)
E Supervisor Page Desc. Reg. (User Super, Kernal CSL)
F User Page Desc. Reg. (PLF6-0 and Addr 0-3)
H Address Buffers (VA15-01 and Ex Mem Flag H)
J Relocation Logic (16, 18, 22 Bit Map and Reloc. ALU and PA21-PA6)
K Register Select and Control (1 SPace A+B BROO-BR11)
LAbor and Trap Decode (Mem MGMT and Read Only FAult and Abort
Cond.)
M PDR/PAR Read Multiplexers (APR Bit OO-APR Bit 15)
N Valid Address Check (18 Bit Overflow and not Cache Adrs)
SCC (M8140) SYSTEM DESC/CNSL CABLES
A
B
C
D
Address Buffers (VA15-VAOO and PA06-PA15)
Reg. Address Decoder (User Par Adrs. and MMR Adrs and Super PDR)
Reg Address Decoder (SW Reg. Land Int. Reg. A+B and Int. Reg H)
Reg. Add Decode (APR Reg, into Reg, Int CLR BL)
47
E
F
H
J
K
L
M
N
System Reg. add Decode (PS, SL, PIR, PB-Adrs's)
General Register Decode (Gen. Reg. (1) H, Console Light Driver)
Internal Bus Drivers (Int D15-lnt DOO)
SCC/CNSL Cables (J1, J2)
Console Add Display (Disp Adrs 21-06)
Unibus Add. Drivers and MMR3 (Bus AOOL-A17L)
System Reg. Bits 00-07 (internal "D" Bus)
System Reg. Bits 08-15 (internal "D" Bus and Memory Size)
SSR (M8138-YA) SYSTEM STATUS REGISTERS
A
B
C
D
E
F
H
J
K
L
M
MMU ROM + ROM Decode
Address space (K, S, U + I/D) Control Logic
MMRO Bits <15:13> Abort Flags
MMRO Bits<12,9> Trap Flags
MMRO Bits <8:0> Mode Status Bits
MMR1 Bits <15:0> Auto INC/DEC Information
MMR2 Bits <15:0> 16 Bit Virtual Address
Internal Data Bus MUX
Console Address Select Switch, Timing Logic, Init Logic
MMU ROM Map for M8138-YA
MMU ROM Map for M8138
48
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I
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CCBH.J.K.L
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FIGURE 8.5
52
::0
oII:
FIGURE 8.6
53
•
I
T2
I
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T3
T4
T5
T6
T1
I
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T2 H
T3 H
I
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BITS
BITS
46:63
15:40
BITS 41:45
r
T2
T3
T4
I
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n
T1~
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SECOND ROM CYCLE _
I
FIRST ROM CYCLE
T6
T1
n
n
I
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I
I
I
I
I
I
I
I
I
I
I
ROM ACCESS TIME
I
t
I
~
ROM OUTPUT
CLOCKED IN"FO
BUFFER (RBR)
RAR
CLOCKED
~
ROM OUTPUT
CLOCKED INTO
BUFFER (RBR)
[?JOM
"f~M~~G
1
ROM
ADDRESS
LOGIC
8
MEMORY
MANAGEMENT
•
ROM
UAD
8
I
156
J
DATA
PATHS
T
IL
1
INTERFACE
CONSOLE
1
1
FIGURE 8.7
54
TIMING
1
RAR
CLOCKED
Microprogram Bii Usage
Bit Positions
Contents
Clocked At
RACA
67
66
65-64
63
62
61-60
59-58
57
56-55
54-52
51
50-49
48-47
46
FP start (UFPS)
clear sync (UClS)
Floating Point Control (UFPC)
bus register clock (UBRK)
bus register multiplexer (UBRX)
source register MUX (USRX)
destination register MUX (UDRX)
source register clock (USRK)
destination register clock (UDRK)
condition-code load (UCCl)
program counter A ClK (UPCA)
program counter B ClK (UPCB)
shifter control (USHF)
instruction register ClK (UIRK)
45-44
43-41
40-39
38-37
36-35
pad write-enable (UPWE)
scratch pad address (UPAD)
bus delay (UBSD)
bus address multiplexer (UBAX)
internal bus (UIBS)
34-33
32-30
29-27
26-24
23-22
21-20
19-18
17-15
shift counter (USHC)
bus control (UBCT)
miscellaneous control (UMSC)
bus conditions (UBSC)
A multiplexer (UAMX)
B multiplexer (UBMX)
constant multiplexers (UKMX)
arithmetic logic unit cont (UAlU)
14
13
12
11-08
07-00
fork C enable (UCFEN)
fork B enable (UBFEN)
fork A enable (UAFEN)
branch-enable (UBEF)
microprogram address (UADR)
T1
T1
T1
T2
T2
T2
T2
T2
T2
T2
T2
T2
T2
T2
RACB
T1 +15 ns
T1+15ns
T1
T1
T1
RACC
T1
T1
T1
T1
T1
T1
T1
T1
RACD
not
not
not
not
not
buffered
buffered
buffered
buffered
buffered
SPECIAL uADDRESSES (as seen in the lights)
FP11
3
76
377
CPU
FP11 C idle loop
FP11 B idle loop
No FP11
170
200
244
352
275
374
377
Console halt loop
Abort entry ZAP 200
WAIT instr INTR PAUSE
Any other INTR PAUSE
WAIT loop (11,264)*
RESET loop
AFORK entry
*On KY11-R consoles you will see 1 of the 2 uAddresses as the KY11-R takes a snapshot
of the RAR register. On the old console the lights are blurred together to make
uAddress 275.
55
A~ORTS,TRAPS,
AND INTERRUPTS
A) GENERAL
ABORT
=
TRAP
=
INTERRUPT
=
THE NON-COMPLETION OR INTERRUPTION OF A DATA CYCLE DUE TO AN
ERROR. SERVICED IMMEDIATELY, PRIOR TO THE COMPLETION OF THE
INSTRUCTION BEING EXECUTED.
AN INTERRUPTION OFTHE NORMAL PROGRAM FLOW BY INTERNAL MACHINE
CONDITIONS. SERVICED AFTER COMPLETION OF THE INSTRUCTION BEING
PROCESSED.
CAUSED BY CONDITIONS EXTERNAL TO THE MACHINE.
B) VECTORS
- ALL ABORTS, TRAPS, AND INTERRUPTS OBTAIN A VECTOR.
- FOR AN EXTERNAL INTERRUPT, THE VECTOR IS PROVIDED BY THE DEVICE CAUSING THE
INTERRUPT.
- FOR ABORTS AND TRAPS, THE VECTOR IS READ FROM THE TRAP VECTOR LOGIC.
-THE VECTOR LOGIC IS CONTROLLED BY FUNCTIONS ON THE "TMC" MODULE AND BY
FUNCTIONS ON THE "IRC" MODULE.
-IRC FUNCTIONS ARE TRAP INSTRUCTIONS WHICH DO NOTHING BUT GENERATE AN
INTERRUPT (lOT, BPT, EMT, TRAP).
- VECTORS ARE GENERATED BY THE TRAP VECTOR LOGIC ON THE "DAP" MODULE
- THE INTERNAL VECTORS ARE:
4
=
10
14
20
24
30
34
114
240
244
250
=
=
=
=
(DEFAULT)
RED ZONE, UB TIMEOUT
ODD ADD, ILLEGAL HALT
RESERVED INSTRUCTION
BPT
lOT
POWER FAIL
EMT
TRAP
PARITYERROR
PIRQ
FPTRAP
KTTRAP
- ALL ABORTS GO TO MICRO-CODE ADDRESS 200 (ZAP)
- ALL TRAPS AND INTERRUPTS GO TO ADDRESS 240 (BRQ)
- THE FOLLOWING WILL CAUSE AN ABORT:
-
NXM
UBTIMEOUT
RED ZONE
KT ABORT
ODD ADORESS
PARITY ABORT
1) MAIN MEMORY PAR ERR ON WORD REQUESTED BY THE
CPU.
2) MAIN MEMORY TIMEOUT ON CPU CYCLES
3) ADDRESS PAR ERR ON CP CYCLES
- SEE DIAGRAM THAT FOLLOWS. REMEMBER THAT WITH AN RDC CONSOLE, THE "IND ADRS
ERR" AND "IND PAR ERR" ARE THE LOWER TWO BITS OF THE "T" COMMAND.
56
ABORTS/TRAPS/INTERRUPTS
TRAPS
ABORTS
MEM (114)
Unibus
TOUT * CP
APE * CP
MPE * CP REO
WD
APE * UB
MPE
MPE
TPE
FPE
*
*
*
*
UB
CP -REO WD
CP/UB
CP/UB
INTERRUPTS
TOUT * UB/MBC (Dev V)
APE * UB/MBC (Dev V)
MPE * MBC
(DevV)
(These actually cause
an interrupt at BRx)
CP->UB * PB (114)
BR4->7
MMU (250)
(DevV)
MMU NON-RES
MMU PLE
MMU RO * ACF=O,1
MMU ACF = 1 * RD
MMU ACF = 4 * R/W
MMU ACF = 5 * WRT
PWR (24)
POWER UP
CPU (4)
RED ZONE
POWER FAIL
YELLOW ZONE
UNIBUS TIMEOUT
NXM
ODD ADRS ERROR
I LLEGAL HALT
(240)
PIRO 1->7
TBIT PS<14> (14)
CNSL FLG (No Vect)
Instrn's
TRAP
EMT
BPT
lOT
RSVD
(34)
(30)
(14)
(20)
(10)
FP (244)
FP EXCEPTION
Note 1: RESET and SPL instructions execute NOP's if in USER or SUPER mode.
TERMS
TOUT
CP
APE
MPE
REQWD
TPE
FPE
UB
MBC
PB
MMU
ACF
NON-RES
PLE
RO
Main Memory Timeout
CPU Cycle
Main Memory Address Parity Error
Main Memory Data Parity Error
Requested Word
Cache TAG Address Parity Error
Cache Fast Data Memory Parity Error
Unibus Cycle
Massbus (RH70) Cycle
Unibus PB bit (Unibus Parity Error)
Memory Management
Access Control Field
Non-Resident Abort
Page Length Abort
Read Only Abort
56A
•
~~'?@ ~V~u~M
ABORT II
uIXlA~s) A[~[j)
A0J©I?tu©
ABORT CLR l
!!
[TMec)
JTMCC)
C)
c:
IND.
:2J
m
co
Co
/-_ _ _... IIlD ADRS ERR II
ADDRS
UNI ADD l
ERROR
KT ABORT FLQl
FRONT PANEl
LIGHTS
PAUSESl
[TMCF]
IUD PAR ERR II
'PE ABORT L
VAUDCPCVCLE~
t11
UBMEMl~
-..j
TIMEOUT
MAIN HI PAR OK
MAIN lD PAR OK
PART L
{CCBJ)
PAUSES
L
eLK
BUSPA
DIS mAPS l
MUX
PARITY fRR L
BUSPB
[CCBJ)
(CCBK]
IUBCS)
eLK
MAIN MEM HI PAR OK L
'PE ADORTL
MUX
MAIN MEM LO PAR OK l
MSVN(OIH
DATA PAROOKl
[UBCB]
DATA PAR 1 OK l
CACHE PERF L
• nMEour - MAIN MEMORY TIMEOUT
ICCBJj
liliGROUP1DAIA
L
I
H
I
GROUP 0 DATA
H
L
MAlNEVENWOfID
H
H
MAIN ODD WORD
OR
ADD PAR ERROR WITH TIMEOUT
eLK
[PORH]
Processor Status Word 17 777 776
CURRENT MODE *
PREVIOUS MODE *
GENERAL REGISTER
SET (0.1)
* MODE: 00 = KERNEL
01
11
=
=
SUPERVISOR
USER
Program Interrupt Request (PIR) 17 777 772
15
9 8
5
7
I
4
3
AhiAp
!
Yt;,@
1
,
0
I,AWA
"
~
CPU Error Register 17 777 766
~7 615 4 3 1 2 1 0
~I_IIJ~
7c~~=======~'=1~1 111
ODO ADDRESS ERROR
ILLEGAL
HALT MEMORY (CACHE)
NON EXISTENT
_
UNIBUS TIME OUT
YELLOW ZONE STACK LIMIT
RED ZONE STACK LIMIT _ _ _ _ _ _ _ _ _ _ _ _ _ _.-J
SL REGISTER 17 777 774
8
15
I
7
0
I
JlBG Register 17 777 770
8 7
15
System ID 17 777 764
15
I
I
SYSTEM SIZE HI 17 777 762
LO 17 777 760
8
15
ALL Os
SWITCHES
=
=
I
LO
HI
HI
SWITCHES
7
ALL ls
I
RESERVED FOR FUTURE
MAXIMUM AVAILABLE MEMORY AND REPRESENTS ADDRESS BITS 21:14
FIGURE 8.10
58
11-4552
CHART OF MEMORV SIZE,
$60 REGISTER CONTENTS AND SWITCH SETTlbljGS
Kwords
Last Adrs
$60
M8140 SW's
32K
64K
96K
128K
160K
192K
224K
256K
288K
320K
352K
384K
416K
448K
480K
512K
544K
576K
608K
640K
672K
704K
736K
768K
800K
832K
864K
896K
928K
960K
992K
1024K
00177776
00377776
00577776
00777776
01177776
01377776
01577776
01777776
02177776
02377776
02577776
02777776
03177776
03377776
03577776
03777776
04177776
04377776
04577776
04777776
05177776
05377776
05577776
05777776
06177776
06377776
06577776
06777776
07177776
07377776
07577776
07777776
001777
003777
005777
007777
011777
013777
015777
017777
021777
023777
025777
027777
031777
033777
035777
037777
041777
043777
045777
047777
051777
053777
055777
057777
061777
063777
065777
067777
071777
073777
075777
077777
00000101
00010101
10000101
10010101
00001101
00011101
10001101
10011101
00000111
00010111
10000111
10010111
00001111
00011111
10001111
10011111
00100101
00110101
10100101
10110101
00101101
00111101
10101101
10111101
00100111
00110111
10100111
10110111
00101111
00111111
10101111
10111111
58A
CHART Or- MEMORY SIZE,
$GO REGISTER CONTENTS AND SWITCH SETTINGS
Kwords
Last Adrs
$60
M8140 SW's
1056K
1088K
1120K
1152K
1184K
1216K
1284K
1280K
1312K
1344K
1376K
1408K
1440K
1472K
1504K
1536K
1568K
1600K
1632K
1664K
1696K
1728K
1760K
1792K
1824K
1856K
1888K
1920K
1952K
1984K
2016K
2048K
10177776
10377776
10577776
10777776
11177776
11377776
11577776
11777776
12177776
12377776
12577776
12777776
13177776
13377776
13577776
13777776
14177776
14377776
14577776
14777776
15177776
15377776
15577776
15777776
16177776
16377776
16577776
16777776
17177776
17377776
17577776
17777776
101777
103777
105777
107777
111777
113777
115777
117777
121777
123777
125777
127777
131777
133777
135777
137777
141777
143777
145777
147777
151777
153777
155777
157777
161777
163777
165777
167777
171777
173777
175777
177777
01000101
01010101
11000101
11010101
01001101
01011101
11001101
11011101
01000111
01010111
11000111
11010111
01001111
01011111
11001111
11011111
01100101
01110101
11100101
11110101
01101101
01111101
11101101
11111101
01100111
01110111
11100111
11110111
01101111
01111111
11101111
11111111
58B
1/0 Page
~
CPU
ER~OA
REGISTER
BIT
DESCRIPTION
02
"RED ZONE STACK LIMIT"
03
-
RED ZONE IS DETECTED BY THE CPU AND OCCURS WHEN IN KERNAL MODE, AND R6
IS BEING USED, AND THE R6 ADDRESS IS IN RED ZONE (000-336).
-
RED ZONE ABORTS THE DATA CYCLE AND TRAPS TO 4.
-
THE FOLLOWING OCCURS:
1) SET STACK POINTER TO 4.
2) PUT OLD PC & PSW IN LOCATION 0 & 2.
3) TAKE NEW PC & PSW FROM LOC 4 & 6.
-
MOST PROBABLE CAUSE:
1) A BURST OF INTERRUPTS FROM AN EXTERNAL DEVICE.
2) STACK LOGIC: M8135, M8134, M8140.
3) A BURST OF ERRORS
"YELLOW ZONE"
-
04
05
06
YELLOW ZONE ERROR TRAPS TO 4 (NO ABORT) IF IN KERNEL MODE, AND USING R6,
AND THE R6 ADDRESS = 340-376.
"UNIBUS TIMEOUT"
-
DETECTED BY THE UNIBUS CONTROL LOGIC (UBC MODULE) AFTER A UNIBUS
CYCLE HAS BEEN STARTED AND THERE WAS NO RESPONSE TO MSYN WITHIN 10
MICRO-SECONDS.
-
UB TIMEOUT ABORTS AND TRAPS TO 4.
-
MOST PROBABLE CAUSE:
1) BAD DEVICE ON UNIBUS.
2) BAD UNIBUS.
3) M8136.
4) MMU LOGIC RELOCATED WRONG
"NON-EXISTENT MEMORY"
-
NXM IS DETECTED IN THE MEMORY MANAGEMENT LOGIC, AFTER THE VIRTUAL
ADDRESS IS FORMED INTO A PHYSICAL ADDRESS, AND THE PHYSICAL ADDRESS
IS NOT DECODED AS A UNIBUS ADDRESS (1/0 PAGE) OR AS A MEMORY ADDRESS
(BELOW SYSTEM SIZE REG). NO DATA TRANSFER IS STARTED AND AN ABORT
OCCURS FOLLOWED BY A TRAP TO 4.
-
MOST PROBABLE CAUSE:
1) SYSTEM SIZE REGISTER IS WRONG.
2) MEMORY MANAGEMENT LOGIC.
"ODD ADDRESS ERROR"
-
AN ODD ADDRESS IS ONLY ALLOWED IN A BYTE INSTRUCTION. AN ODD ADDRESS
IS DETECTED IN THE CPU BEFORE THE VIRTUAL ADDRESS IS SENT TO MEMORY
MANAGEMENT. AN ABORT OCCURS, FOLLOWED BY A TRAP TO 4.
-
MOST PROBABLE CAUSE:
1) MEMORY IS CORRUPTED.
2) ODD ADDRESS LOGIC: M8135, M8132.
3) SOFTWARE.
59
07
"ILLEGAL HALT"
- A USER WAS TRYING TO EXECUTE A HALT INSTRUCTION.
- A TRAP TO 4 OCCURS.
1170 PAUSE CYCLES
A) GENERAL
DATA TRANSFER PAUSES:
ALL CPU DATA TRANSFERS REQUIRE TWO ROM CYCLES FOR PROPER OPERATION: A "BUST"
ROM CYCLE AND A "PAUSE" ROM CYCLE. IN THE "BUST" CYCLE, THE VIRTUAL ADDRESS IS
SENT TO MEMORY MANAGEMENT SO IT CAN BE CONVERTED TO A PHYSICAL ADDRESS. THE
"BUST" CYCLE IS ALSO USED TO INITIALIZE CACHE. THE "PAUSE" CYCLE DOES THE ACTUAL
DATA TRANSFER. IN THIS CYCLE THE CPU RING COUNTER STOPS AND IS RESTARTED WHEN
THE DATA TRANSFER IS COMPLETED. "ROM 40 (UBSD01)" ENABLES A DATA TRANSFER
PAUSE CYCLE. THE DECODE OF THE PHYSICAL ADDRESS BY MEMORY MANAGEMENT (DONE
IN THE "BUST" CYCLE), WILL DETERMINE WHAT TYPE OF DATA PAUSE WILL TAKE PLACE.
THE TYPES ARE: CACHE, UNIBUS, AND INTERNAL DATA PATH.
EXTERNAL INTERRUPT PAUSE:
AN EXTERNAL INTERRUPT PAUSE IS ENABLED BY "ROM 39 (UBSDOO)" AND ONLY OCCURS IN
MICRO-CODE LOCATIONS 352 AND 244. SINCE NO ADDRESS IS NEEDED, THERE IS NO "BUST"
CYCLE PRECEEDING IT. IN THIS CYCLE, THE CPU RING COUNTER IS STOPPED AND IS RESTARTED WHEN THE DEVICE VECTOR IS AVAILABLE TO THE CPU.
B) PAUSE DESCAIPTlDfJ
CACHE PAUSE:
SEE FIGURE 8.11.
M8139: DURING THE "BUST" CYCLE, MEMORY MANAGEMENT DECODED A CACHE ADDRESS
("CACHE ADD H"). THE NEXT ROM CYCLE IS A PAUSE CYCLE AND "ROM 40" IS
ASSERTED. THE ASSERTION OF THE ABOVE TWO SIGNALS STOPS THE RING COUNTER ATT5.
M8135: WITH "ROM 40" ASSERTED (UBSD01 H), AND "CACHE ADD H" ASSERTED, "CONTROL
OK H" IS SENT TO CACHE.
M8142: IN THE "BUST" CYCLE, CACHE RECEIVED "BUST H" FROM THE M8123 AND STARTED
IT'S TIMING. WHEN CACHE NEXT RECEIVES "CONTROL OK", IT PERFORMS A DATA
CYCLE.IFTHE DATA CYCLE WAS COMPLETED WITHOUT ERROR, CACHE GENERATES
"MEM SYNC H".
M8139: "MEM SYNC H" WILL ENABLE THE RING COUNTER TO CONTINUE.
UNIBUS PAUSE:
SEE FIGURE 8.12.
M8139: DURING THE "BUST" CYCLE MEMORY MANAGEMENT DECODED A UNIBUS ADDRESS
WHICH WAS NOT AN INTERNAL REGISTER ADDRESS. IN THE "PAUSE" CYCLE, "ROM
40" IS ASSERTED AND STOPS THE RING COUNTER AT T2.
M8136: WITH "UNIBUS ADD H" ASSERTED, THE UBC MODULE STARTS A UNIBUS DATA
TRANSFER BY ASSERTING "MSYN L" ON THE UNIBUS. THE DEVICE RESPONDS WITH
"SSYN L" AND "TIG RESTART H" IS ASSERTED.
60
M8139: "TIG RESTART H" WILL ENABLE THE RING COUNTER TO CONTINUE.
INTERRUPT PAUSE CYCLE:
SEE FIGURE 8.13.
M8135: IN BETWEEN INSTRUCTIONS, THE CPU WILL DO A BRQ STROBE TO SEE IF ANY
INTERRUPTS ARE PENDING. IF A BR4,5,6 OR 71S ASSERTED WHEN THE BRQ STROBE
OCCURS, THEN HONOR BR4,5,6, OR 7 WILL BE ASSERTED OUT OF THE ARBATRATOR
AND THE CPU WILL GO TO THE BREAK REQUEST MICRO·CODE SERVICE ROUTINE. AT
MICRO·CODE LOCATIONS 352 OR 244, "ROM 39 (UBSDOO)" WILL BE ASSERTED AND
WILL ASSERT "INTR PAUSE H".
M8136: WITH "INTR PAUSE H" AND "HONOR BR4,5,6, OR 7" ASSERTED, "BG4,5,6, OR 7': WILL
BE GENERATED ON THE UNIBUS. ATTHE SAME TIME, THE RING COUNTER WILL STOP
ATT2SINCE "ROM 40" IS NEGATED, "ROM 39 (UBSDOO)" IS ASSERTED, AND "EXT BRQ
H" IS ASSERTED. WHEN THE INTERRUPT DIALOGUE ONTHE UNIBUS IS COMPLETED,
THE DEVICE WILL ASSERT "INTR L" WHICH WILL ASSERT "TlG RESTART H".
M8139: "TIG RESTART H" WILL ENABLE THE RING COUNTER TO CONTINUE.
FOR MORE DETAILS, SEE THE TROUBLESHOOTING CHAPTER.
INTERNAL DATA PAUSE:
WHEN MEMORY MANAGEMENT DECODES AN INTERNAL REGISTER ADDRESS, THE RING
COUNTER IS NOT STOPPED, BUT ONLY DELAYED FOR 90 NANO·SEC BETWEEN T2 AND T3. THIS
PROVIDES ENOUGH TIME FOR THE INTERNAL REGISTERS TO PUT THERE DATA ON THE
INTERNAL DATA BUS.
WHICH PAUSE WAS IT?
Interrupt PAUSE
Unibus PAUSE
Cache PAUSE
-
uAddress
uAddress
uAddress
~
~
~
352 or 244
PAUSE ROM STATE uADDRESS
1 uADDRESS past the PAUSE ROM STATE
uADDRESS.
Note: This will occur because the ROM address registers are clocked on the rising edge of T3
clock pulse. Therefore if the clock hangs in T2, the uAddress lightslregister will
indicate the current ROM state (the PAUSE ROM state) since it was not updated. If the
clock hangs in T5, the uAddress lights/register will indicate the ROM state following
the PAUSE ROM state since it was updated at T3.
FOR MORE DETAILS ON PAUSE CYCLES, SEE THE TROUBLESHOOTING CHAPTER.
61
F.18139 TIG
STOPS TIMER AT T5
ROM40L
STOPTlL
(i)
T1H
CACHE ADD H
T1
F/F
ABORTH
[TiGAr
o
MEM SYNC (0) H
MEM SYNCH
AESTARTSIIMER
ERROR OCCURRED
{ IN PAUSE CYCLE.
RESTART TIMER.
VIRTUAL ADD.
DECODED
DURlNG~BUST"
ROMCVClE.
VIRTUAL
ADDRESS
DECDDE
{RACBI
~
Q
0
P-I+----tol-- NOT CACHE ADD H
"
ROM
[SAPN[
[TMCE]
"BUSTH"
IRACBl
[RACH]
F.18135 mc
r.18123 nAC
MUST BE RECEIVED
BY CACHE PRIOR
TO "CONTROL OK"
OR CACHE Will
HANG.
r.18137 SAP
(Fm.10RY r.1AFlAGEF.1EFlTI
CONTROL OK H
~
BUSTH
o
MEM SYNC H
o
MAIN
MEMORY
OATACVCLE
COMPlETED
WITHOUT ERROR
SEE MEMORY SECTION
FOR MAIN MEMORY
DIALOG.
r.1B142 cca
(CACHEI
FIGURE 8.11
62
[,]3139 TIG
STOPS TIMER AT T2
ROM 40 L
STOPTJ L
UNIBUS ADO H
T3 H
T3
[TIGAI
=-- RESTARTS
TIMER
-::;;:J
TIG RESTART H
SSVNl
U
N
I
B
U
MSVNL
r,18136 uoe
[,18123 RAe
UNIBUSADOl
VIRTUAL
NOT AN
ADDRESS
DECODE
INTERNAL
REGISTER
INTO REG (1) l
[.18140 see
1.18137 SAP
1[,1Er.10RY r.1AIlAGEr.1EIHI
FIGURE 8.12
63
VIRTUAL ADDRESS
IS DECODED
DURING THE
"BUST"ROM
CYCLE
S
•
r,18139 TIG
0
0
HDLDS TIMER AT 12
ROM 40 L
STOPlJL
UBSOOOH
T3H
T3
0
EXT8RDH
[T1GAI
TIG RESTART H
0
TlG RESTART H
INTRl
MUX
UBSOOOH
G).-I-~~-I
(RACB)
007
006
005
'G4
r,18123 nAC
r,1S136 UBC
U'SDOIl H
-'---+---1
HONORBR7l
[TMCE)
HONORBR6l
INTR PAUSE H
HONOR BRS l
HDNORBR4l
BUS BR4 L
BUSBRSG
BUSBR6l
BUSBR7L
F.18135 mc
FIGURE 8.13
64
0
U
N
I
B
U
S
::!!
C)
Cl9J1lJ UO
M~MO~V W'~~ulE
c:
:zJ
m
CD
:...
""
TIME
CPU
T1
BUST
MEM MAN
CACHE
MEMORY
VIRTUAL ADD -----.~~ADDRESSDECODE
~
PHYSICAL ADD
T3
START CP CYCLE
~
T2
...
0)
PAUSE
ADDRESS
01
T3
CONTROL OK
+
DATA'
T5
•••
••
••
T1
..
ADDRESS
..
+
CONTROL
HOLD ClK
..
MAIN START
MAIN OCC
..
+
DATA
RESTART . .
ClK
••
MEM ...........- - - - - MAIN ACK
SYNC
::!!
C~QJ
c:
TirJlE
CPU
m
!»
en
T1
BUST
C)
%I
...
1'10
~~EMIO~V ~EAlQ)
ME~l
VIRTUAL ADD
~
MAi\J
CAC~-JE
~JlEMORY
ADDRESS DECODE
~
PHYSICAL ADD
T3
START CP CYCLE
..
T2
PAUSE
ADDRESS
T3
CONTROL OK
..
•
.-
ADDRESS
+
0)
0)
CONTROL
T5
••
••
••
••
T1
HOLD ClK
If
MAIN ACK
..
MAIN OCC
If
RESTART
TIMER
ClK BR
•
MAIN START
If
MEM ..
SYNC
••
DATA
MAIN DATA
READY
!!
c:
...
i P6
MJ11 BACKPLANE
I
P/J19
DC LOW
MAIN
MEMORY
BUS CABLE
J3
J4
NOTE
2
IT
MJ11 MEMORY
POWER SUPPLY
(UP TO 8)
aClOW
TT
AC lOW
AR I
(POWER CONTROL
AC LOW
I
I
I AR
~[!)~-~.U'?~
CARD5411086
MEMORY
I
r---------
I
MAIN DC LOW l
MAIN AC lOW l
PROTECTION
I
CIRCUITS ....J
L____
II
[)lClO
M8143
TT
i
RR
•
CACHE POWER
UP CIRCUIT
L ___ J
I
-.J
Al3E1
AlBC1
AIBOl
C18Rl
MAIN DClO l
ADML MAIN
OClO H
C12F2
AOMl MAIN
AClO H
UBeE AClO l
E12l1
- -, frM;---'
I I
I
'CS REV F
M8135
PROCESSOR BACKPLANE
P3
......
PROCESSOR
POWER SUPPLY
I
BUS ACLO L
F01Fl
I I
01252
~-: II
~
OC LO 1
(5411086 IN
UPPER 7420)
1!..
BUS OClO L
;;r-
ICl
P22
.....,
B44F2
BUS
!-_~J
I
I
I
_ _ _ _ _ _ .JI
ACLO L
P7
PROCESSOR
POWER SUPPLY
(5411086IN
10
AC lO3
LOWER 7420)
AC L02
BUS ACLO l
DC LO 2
MAiNiiCl'OL
B44F1
:rP4
12
I
I
I
I
r-----,I
I
I
J2
PROCESSOR
HARNESS 7011051
Pl5
COu~~ECu~O~~
AD~---l
ADML
L _ _ _ _ _ .J
""-J
Au~[)l
I
I
I
L_
OR 541H!86YM
O'l
AClO
I M8143
MCTH M8148
HARNESS
7010581
:tI
m
!XI'
en
r
- - - - -,
I
MEMORY CONTROL
G)
DC LO X
I
,J: I
I 'L~J I
I
I
I
I
IL _ _ _ JI
NOTES
1 Processor Power-down/power-up circuit. Refer to
KB11-B Processor Manual Seclion II. Chapler 6.
F12E2
8US DeLD l
2. Contractor J4 connects Main Memory Bus cable to
J3 on M8148 of next memory frame
3. AC LOW L Yellow wire
DC LOW L Purple wire
0
SPC SLOTS
- CV1·
' - - - - - - - SPC SLOTS
- eN1
M5904's MBse - BV2
11-4000
0
'SPC oplions 1ha1 can se1 ACLO - KY11-R. DMC11. DRM11. DEUNA. e1c.
C~~~AlDu~~ ~
CAC~H::
CONTENT
PAGE #
CACHE BLOCK
CABLE LAYOUT
REGISTERS
MEMORY SYSTEM ERRORS CHART
ERROR CIRCUITS
70
71
72, 73, 74, 75
75A
76-81
69
(ADMF,J)
(ADMH)
,_.-- ••. _.
•
ADRS PARITY
CACHE
ADDRESS
MUX
ADDRESS.
CNTl&
BYTe
(AOMe)
MASK TO
AMX<21:10>
MAIN
MEMORY
ADME,f,J
so
"eJ
{Q
"eJ
PRIORITY"
rOMAP
3
t tSl
~ T:_~_
MAIN A <21:2>
MAINe <1:0>
MAIN eYTe MASK <3:0>
100
DO
CPU
PWR·UP
MBC
UNIBUS
.cl
=1>
~
e
--..
o
oj9
o
TAG 0<21:10>
I
''"5_.... ' ' i~:~~C:~I~'PAR8
:z:
m
5
m
5
rg
;EJ
~
CACHE DATA
<15:00>
TO
PROCESSOR
UNIBUS MAP
(OTMM)
!!
C>
c:
IVlJ11/1Vl1(11
~
M8148/47, M8158
M8149, M8159/64
MGT
MXR
ABS
D8B
::tJ
m
!"
.....
ADD.lCOrJTROL
DATA
J3
J3
J1
Jl
IT=? t;==T
- - - - - - - - - - - - - - - - - - 1 - ..,- + - + - - - - - - - -
..
aDee
CO,C1
BM30
--J
ACK
CABLES
PAR ERR
START
ACl
DCl
~l
~,
'>
MEMORY
BUS
CABLES
0<1631>
PAR
D~~~5>
...
I I I
t-+-i-------1170
M8142
M8143
CCB
ADM
~c:':::::::::!
J2
M8145
CDP
J2
J1
CACHE
~
MEMORY}
ERROR
REG
CACIIE
COIJTROL
ADD.lCOIJTROL
DATA
Jl
Control Register 17 777 746
15
6
4
3
2
'---If 1
FORCE REPLACEMENT GROUP 1 _ _ _ _ _ _ _ _ _ _ _ _
FORCE REPLACEMENT GROUP 0
FORCE MISS GROUP 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...1
1
I1
FORCE MISS GROUP 0
DISABLE UNIBUS TRAP - - - - - - - - - - - - - - - - - - - '
DISABLE T R A P S - - - - - - - - - - - - - - - - - - - - - - '
Memory System Error Register 17 777 744
15
14
13
12
11
10
9
8
I I I II I I I I
~
CPU ABORT
CPU ABORT AFTER ERROR
UNIBUS PARITY ERROR
UNIBUS MULT IPLE PARITY ERROR
CPU ERROR
UNIBUS ERRO R
CPU UNIBUS ABORT
ERROR IN MAl NTENANCE
DATA MEMOR Y GROUP 1
DATA MEMOR Y GROUP 0
,ADDRESS MEM ORY GROUP 1
iADDRESS MEM ORY GROUP 0
MAIN MEMOR YODDWORD
MAIN MEMOR Y EVEN WORD
MAIN MEMORY ADDRESS PARITY ERROR
MAIN MEMORY TIMEOUT
7
6
I
5
4
0
DATA ERRORS
I
I
I
I I
I
J J
High Error Address Register 17 777 742
15
14
6
13
5
HIGH ADDRESS
I
DATI
DATIP
DATO
DATOB
0
1
0
1
Low Error Address Register 17 777 740
15
LOW ADDRESS (16 BITS)
I
I
I
,
HIVMlss Register 17 777 752
6
15
5
Maintenance Register 17 777 750
15
12
11
8
7
4
1
0
~~~~~
-----1
1
r
I
MAIN MEMORY PARITY
FAST ADDRESS PARITY - - - - - - -.....FAST DATA PARITY
MEMORY MARGINS
FIGURE 9.2
11-4551
72
MEMORY SYSTEM ERr-lOA r-lEGISTEfl
Bit
Function
Name
15
CPU Abort
Set if an error occurs which causes the Cache to abort a processor cycle.
14
CPU Abort After Error
Set if an abort occurs with the Error Address Register locked by
a previous error.
13
Unibus Parity Error
Set if an error occurs which results in the Unibus Map asserting
the parity error signal on the Unibus.
12
Unibus Multiple
Parity Error
Set if an error occurs which causes the parity error signal to be
asserted on the Unibus with the Error Address Register locked
by a previous error.
11
CPU Error
Set if any memory error occurs during a Cache cycle from the
processor.
10
Unibus Error
Set if any memory error occurs during a Cache cycle from the
Unibus.
9
CPU Unibus Abort
Set if the processor traps to vector 114 because of a Unibus
parity error on a DATI or DATIP cycle by the processor on the
Unibus.
B
Error in Maintenance
Set if an error occurs when any bit in the Maintenance Register
is set. The Maintenance Register will then be cleared.
7-6
Data Memory
These bits are set if a parity error is detected in the Fast Data
Memory in the Cache. Bit 7 is set if there is an error in Group 1", bit
6 for Group O.
5-4
Address Memory
These bits are set if a parity error is detected in the Address
Memory in the Cache. Bit 5 is set if there is an error in Group 1, bit
4 for Group O.
3-2
Main Memory
These bits are set if a parity error is detected on data from Main
Memory. Bit 3 is set if there is an error in either byte of the odd
word, bit2 forthe even word. An abort occurs if the erroris in the
word needed by a CPU reference. A trap occurs if the error is in
the other word, or if it is a Unibus reference.
Main Address Parity Error
Set if there is a parity error detected on the address and control
lines on the Main Memory Bus.
Main Memory Time-out
Set if there is no response from Main Memory. For CPU cycles,
this error causes an abort. When a Unibus device requests a
non-existent location, this bit will not set.
0
CACHE REGISTERS
A) HIGH ArlO LOW ERROR ADDRESS REGISTERS
THESE TWO REGISTERS ARE LOCKED IN WHEN ANY ERROR IS SET IN THE MEMORY ERROR
REGISTER WHILE DOING A CPU OR A UNIBUS MAP MEMORY REFERENCE. THESE TWO REGISTERS CONTAIN THE 22 BIT PHYSICAL ADDRESS THAT CAUSED THE ERROR. THE REGISTERS
73
WILL STAY LOCKED IN UNTIL THE MEMORY ERROR REGISTER IS CLEARED. IF AN ERROR IS
SET WHILE REFERENCING AN MJ11, THE LOW BITS OF THE ERROR ADDRESS REGISTER WILL
POINT TO THE CORRECT SIDE (LOW OR HI) ONLY IF "CPU ABORT" IS SET IN THE MEMORY
ERROR REGISTER. IF "CPU ABORT" IS NOT SET, THEN THE ERROR IS IN THE OPPOSITE WORD
THEN POINTED OUT BY THE LOW BITS OF THE ERROR ADDRESS REGISTER. THE ERROR
ADDRESS REGISTER ALWAYS POINTS TO THE CORRECT SIDE WHEN AN MK11 IS INVOLVED,
SINCE "CPU ABORT" WILL ALWAYS BE SET FOR ANY ERROR CAUSED BY AN MK11.
B) mr,lOnY SYSTE[,1 ERnOR nEGISTEn
BIT
DESCRIPTION
00
MAIN MEMORY TIMEOUT:
MJ11-THE MEMORY CONTROLLER (M8147/48) DID NOT RESPOND WITH "ADD
ACK" 4 MICRO-SECONDS AFTER CACHE SENT "MAIN START". - SEE
FIGURE 9-3.
PROBABLE CAUSES:
1) MEMORY STARTING ADDRESS IS WRONG.
2) SYSTEM SIZE REGISTER IS TOO HIGH.
3) M8147/48.
4) CABLES BETWEEN M8143 AND M8147/48.
5) M8143 AND M8142.
6) MEMORY BUS TERMINATORS ON M8147/48.
7) CPU BACKPLANE.
MK11-MEMORY CONTROLLER 0 OR 1 (M8160) DID NOT RESPOND WITH "ADD
AKN" 4 MICRO SECONDS AFTER "MAIN START" FROM CACHE WAS
SENT. WHEN THE ADDRESS BUFFER MODULE (M8158) IN THE MK11
RECEIVES "MAIN START" FROM CACHE, IT SENDS "GO" TO THE
SELECTED CONTROLLER. THE SELECTED CONTROLLER, AFTER RECEIVING THE "GO" SIGNAL, STARTS IT'S ARRAY TIMING. AFTER THE TIMING
HAS STARTED, THE SELECTED CONTROLLER SENDS "ADD AKN" TO THE
ADDRESS BUFFER MODULE (M8158), WHICH IN TURN SENDS IT TO
CACHE. - SEE FIGURE 9-4.
PROBABLE CAUSES:
1) MEMORY START ADDRESS WRONG.
2) SYSTEM SIZE REGISTER TOO HIGH.
3) M8160 IN BOTH CONTROLLERS.
4) M8158.
5) CABLES BETWEEN M8158 AND M8143.
6) MEMORY BUS TERMINATORS ON M8158.
7) M8143 AND M8142.
8) CPU BACKPLANE/MK11 BACKPLANE.
01
ADDRESS PARITY ERROR:
ALL MEMORY CONTROLLERS CHECK FOR PARITY ON THE ADDRESS AND CONTROL LINES SENT BY CACHE. ALL THE CONTROLLERS THAT HAVE DETECTED
THE BAD PARITY WILL TURN THE PARITY ERROR ON. - SEE FIGURE 9-5.
PROBABLE CAUSES:
1) M8147/48 (MJ11), M8158 (MK11).
2) CABLES.
3) MEMORY BUS TERMINATORS.
4) M8143 AND M8142.
74
02/03
MAIN MEMORY EVEN/ODD WORD PARITY ERROR:
MJ11-THE MJ11 CONTROLLER WILL READ TWO WORDS FROM TWO DIFFERENT STACKS (ODD AND EVEN). THEREFORE ONLY ONE OF THESE BITS
WILL MOST LIKELY BE SET AT ANY ONE TIME. FIND OUT WHICH SIDE,
ODD OR EVEN, HAS CAUSED THE ERROR. SEE HI AND LO ERROR
ADDRESS REGISTER DESCRIPTION ON PREVIOUS PAGE. - SEE FIGURE
9-6 AND 9-7 FOR MOST PROBABLE CAUSES.
MK11-THE MK11 WILL PULL OUT TWO WORDS FROM ONE ARRAY. THEREFORE,
IF AN ARRAY IS BAD, BOTH THESE BITS WILL BE SET. TO FIND OUT
WHICH SIDE IS BAD, SEE BIT #9 OF THE MK11 CSR WORD #2. IF ONLY
ONE OF THESE BITS ARE SET, THEN THE ARRAYS ARE NOT AT FAULT.SEE FIGURE 9-8.
04/05
ADDRESS MEMORY GROUP 0/1 PARITY ERROR:
THE ADDRESS MEMORY ON THE M8143 MODULE DETECTED A PARITY ERROR.
THE ADDRESS MEMORY AND THE PARITY GENERATING AND CHECKING CIRCUITS ARE ALL ON THE M8143.
PROBABLE CAUSES:
1) M8143.
2) M8142.
3) CPU BACKPLANE.
06/07
DATA MEMORY GROUP 0/1 PARITY ERROR:
THE DATA MEMORY ON THE M8144 HAS DETECTED A PARITY ERROR.
PROBABLE CAUSES:
1) M8144.
2) M8142.
3) CPU BACKPLANE.
NOTE: ABLE DH/DM's below rev H7 can cause FDM,TAG and/or MAIN MEMORY DATA
PARITY errors.
75
•
MEMORV SYSTEM ERRORS
MSER BIT
CP CYCLE
UB CYCLE
MBC CYCLE
....... 0........
Memory timeout
(No ACK in 4us)
Sets 15,11,0.
Aborts.
No bits set.
TOUT prevent SSYN
on MAP result is
Dev NXM, interupt.
No bits set.
Set RH70 CSR2<11 >
NXM + interrupt.
....... 1........
Memory APE.
(Mem sends APE +
no ACK so TOUT) .
Sets 15,11,1.
Aborts cause of
resulting TOUT.
(no set bit 0).
Sets 10,1 .
Traps, Dev NXM +
interrupts.
No bits set.
Set RH70 CSR3<15>
APE + interrupt.
...... 2,3 .......
Main Memory PE
wanted word.
Sets 15,11,2 or 3.
Aborts.
Sets 13,10,2 or 3.
Unibus PB + Trap.
No bits set.
Set RH
CSR3<14,13>
MPE + interrupts .
...... 2,3 .......
Main Memory PE
unwanted word.
Sets 11,2 or 3.
Traps.
Sets 10,2 or 3.
Traps
No bits set.
Set RH
CSR3<14,13>
MPE + interrupts.
.... ..4,5 .......
TAG Parity error.
Sets 11,4 or 5 .
Force miss, Trap.
Sets 10,4 or 5.
Force miss, Trap.
No bits set.
Doesn't check TAG
parity, use match to
invalidate TAG.
...... 6,7 .......
FDM Parity error.
Sets 11,6 or 7 .
Force slowcycle +
Trap.
Sets 10,6 or 7.
Force slowcycle +
Trap.
No bits set.
FDM not used on
MBC cycles.
....... 8 ........
Error in Maint.
Set if any bit in
MSER<7:0> and any
CMR<15:1> set.
Set if any bit in
MSER<7:1> and any
CMR<15:1> set.
Never set.
....... 9 ........
CPU -> UB Abort
Never set.
* See Note 1.
Never set.
....... 10 ......
Unibus Error.
Never set.
Set if any bit in
MSER<7:1> set.
Never set.
....... 11 .......
CPU error.
Set if any bit in
MSER<7:0> set.
Never set.
Never set.
....... 12 .......
Multiple UB PE.
Never set.
Set if UB PE and any
MSER<7:0> set, HI
LEAR was locked.
Never set.
....... 13.......
U B Parity error.
Never set.
Set if bits 2 or 3
wanted word set.
Never set.
....... 14 .......
CP Abort after error.
Set if PE Abort + any
MSER<7:0> set, HI
LEAR was locked .
Never set.
Never set.
....... 15 .......
CP Abort.
Set if bits 2 or 3
wanted word set or
bits 0 or 1 set.
Never set.
Never set.
Note 1: UB Parity Error, bit 9 sets if the PB bit is set on the Unibus on a CPU to Unibus transfer
then Aborts. (ie: accessing MK11 CSR's)
75A
•
:!!
G)
C
P,~J11
~
M8148/47
M8149
MCT
MXR
:D
m
co
W
ADDRESS
RANGE
CHECK
J3
-...j
CJ)
~
[,lAm [,1Ei,1OnV TI[,lEOUT
CP
CYCLE
START
1170
MEMORY
BUS
CABLES
M8143
M8145
ADM
COP
"
----7'>
J2
CACHE
~
ADD.ACK
MEMORY}
ERROR
REG.
-:+?~~~~___J
TI1.1EOUT"~
I,IAIIlMEt.t
J1
"'1'1
CONTROL Al
is
c:
::a
~
M8160
m
•
CD
~
CDNT.
SEl.
D
ACK
ADDRESS BUFFER
M8158
......
......
¢
r.1AIU rm.lORY TJr.1EOUT
1170
MEMORY
ERROR
REG.
BUS
CABLES
M8143
M8145
ADM
COP
'-
----.."7>
J2
CACHE
~
MEMORY
l
Jl
:!!
Q
c:
::D
r,~J11/pm[11
M8148/47. M8158
~
MCT
M8149. M8159/64
PAR. LIGHT
ABS
m
MXR
OBB
PAR. ERR.
CD
en
--------- ------------
¢
ex>
1170
CACHE
M8142
M8143
M8145
ADM
cOP
MAIN ADD PAR. ERR.
CO,Cl
PAR
BM()103
MEM.ORY
ERROR
~
REG
PAR.
GEN.
ADD}
PAR.
ERR
MEMORY
BUS
CABLES
CCB
jCCBK]
~
Jl
J2
Jl
----+~
,\DDRESS PARITY ERROR
-.J
J3
A
'-
--7-7'>
CORE
II
!!
G')
c:
::D
MJ11
~
M8148/47
M8149
MCT
MXR
l}
LOW
EVEN
0<0015>
+2 PAR. BITS
m
co
en
J3
'i=i'
cr==
J3
J1
-----------H~+----
<=
[,lAHJ m[,lOnV EVErJ \'IOnD
-.j
to
- - , -j-
MEMORY
'-
BUS
CABLES
-------7'7
1170
M8143
CCB
ADM
M8145
o:!::::::!:r c!:=
J2
Jl
1+'-
>
- - - - - - - - - - - - ----------\-++-1-- - - - - - - M8142
•
r==? 'i"i"?
+--1-1';-'.!::::!. r:!::
COP
J2
J1
I Jl
CACHE
V'
[CDPF]
MEMOAYJ~
ERROR
REG .
..,""..,EM.
EVEl'WORD
MAIN lOOK
r---
!
_=V;E~3
~ '~i'~l'~?_--+-~
J
•
PARITY
CHECK
1-
CORE
!!
C)
C
:lJ
:C1,Ji 1
~
M8148/47
M8149
MGT
MXR
HIGH
000
m
CD
:.....
D<16:31>
+2 PAR_ BITS
J3
- - - - -- - - - - - - - - - - -
---
<=
i,lAII! mi,lORY 000 \"ORO
MEMORY
BUS
CABLES
---- ---J2
MEM."V}
ERROR
R '
J1
!!
G)
rm(11
:D
~
c::
m
I
t
CONT
SEL
CD
00
1////////
CONTROL 81
(M8161)
•
I
ADDRESS
DECODE
t
(Xl
.....
- -
- - -- -
-
- -
1170
~
¢
MAINMEM EVEN WI
l-
e- -
~
1~
)1 ' 1 1 ' 1
~2~'
1
OK
ICDPfI
I
-
EVEI
JO="
M8145
~
1
h
- - - - - - - - - - f..i- -I+. -
PARITY
CHECK
0
d'
>
MEMORY
BUS
CABLES
MAIN HI
2
MAtrlMEM OODW'
- - -- - -- - -
1681TS
2PAA
< ;'<
J1
~
MEMORY
ERROR
REG
- -
"
,---L16BlTS
2 PAR
- - - - - - - - - I- - - - - - - - - - - - - D O O · L
M8143
M8142
////////, '////////1/,fl/I/II
=:j.=
f,lAIll fm,lORY PARITY ERROR
--
J
3281T5
4 PAR BITS
DATA BUFFER
I
J3
CONTROL 80
(M8161)
M8159
CONTROLLER
SELECT
A<02>
-- -- --
CONT
SEL
4PARBITS
INTERNAL INTERFACE BUS
ADDRESS BUFFER
-
I
!~Blffi
M8158
-
I
1
iC~A~uE~ 'u@
MEMO~V
MAWAGEMEWu
CONTENT
PAGE
BLOCKS
REGISTERS
RELOCATION
87
84, 85, 86
88, 89, 90
•
83
!!
SAP' M8l37
SSR· M8l38-YA
sec· M8l40
C)
c:
-
INCOMING VA
;u
UNlEiUS
• ADRS
m
II
o
:~O~;~:S
BUS A<17:00>
:...
;==========::::::::>(JX'C~l~~:SJ
SAPJ
5
m
::y
QISP A<21:00>
=
0
4J
~
c::'
=
00
"""
J9
G
:9
ROM CUT <16:01>
PS<15:12>
MFP+MTP
IR15
~
ADRS
SPACE
,CONTROll
SSRB
KERNEL SPACE
SUPER SPACE
JJ
SElECT APR SET
(MMU REGISTERS)
INTERNAL REG ADDRESSES
USER SPACE
I SPACE A,B
ABORT CONDiTIONS
m
(CPU REGISTERS)
CPU REG ADDRESSES
f
UNIBUS AORS
I SSRC
~ I SSRE
(>17000000)
r
TRAP CONDITIONS
c::'
=
m
P-
PAF <21:6> + VA <12:6>
SYS SIZE <21:14>
~gMRO
~ SGRD
NOT CACHE ADRS
(>SYSSIlEj
MODE/OPERATE/CONTROL ~
G
=J
G
F
©
SR <05:04,02:00>
CNSlOVERFlOW
(>SYSSIZE)
SWR<15j)Q>
~
(\1J
M
SYS 10 <15:00>
QJ
:9
~
4J
:9
::y
=
INTERNAL DATA BUS
BUS INTD <15:00>
ERROR CONDITIONS
SYSSIZE<21:14>
.THIS SIGNAL ONLY EXISTS ON KBIt·eM (11/74)
XM
"D
db
!!
G)
moc
c:
<: :D
!!5iJ
(\I)
.....
J9
~
F
ENAB
22 BIT
KY PH
MEMAC
0
0
0
m
0
KY PH MEM AC
FUNCT.
{
16 BIT
RELOC
1B BIT
22 BIT
CONS.
~
~
SWR21:16
~
EXT MEM FLG
!!5iJ
AORS 21:16
m
C?!i~
PA 17:14
(\I)
CONS. PHY
..
16 BIT MODE
PA21:16
22BrT MODE
18 BIT UPAOA
SAPJ
AORS 17, 16
SAPH
} 18 BIT MOOE
BAMX 15:00
T
!!5iJ
U1
AORS 15
AORS 17
VA 15:13
QJ
~
1
SAPJ PA MUX
lQl
lQl
ex>
ENAB 22 BIT MAPPING
9
:2:3
6
AORS
BFA
VA 15:13
BAMX
AORS 15:13
15:13
(\I)
~
=~
QJ
"'"~~.~~
SAPB
PA 15:13
tBBrTOR
22 BIT MOOE
PA 12:06
SAPA
~
16 BIT MODE
OR CONS PHY
PAF21:06
SAPC
PAR
BAMX 05.00
rmTES:
r~~
121
I
21
VA
06IA~U
PAF
ADRS
06J A;U
'I
13 : 12
PA
06
ALU
OUT
AlU FUNCTIONS
F" A
IF-RElOC
F " A+B
IF RELOC
MMRO <0>
1 Enables Relocation in 18 or 22 SI'
Mode.
MMRO <0>" 1 . Enables Relocation for the Dest.
Adrsonly-in 18or22 Bit Mode
KY PH MEM AC Console PhYSical Memory Access.
True when Adrs Select Switch is in
CONS PHYand an EXAM or DEPOSIT
is in progress. NEGATES RElDe.
5 ::!!
G)
Uuil
c:='
c:
=
m
© ...
~
~
c:='
=
:D
Q
W
8R14:7
~
oI0
~ ~
BR3
~
8R2:0
~
-----
PAOGRAM WRITE
} TO PORAORS.
NOTES:
PDR
PAGE LENGTH
Program writes to a PAR will also write zeros to the
A & W bits of the PAR's associated POA.
The A & Wcontrol logic is on sheet SAPO.
MMRO <15:13> when set cause the logic to FREEZE
the contents of MMRO <7:1>. MMRI. & MMR2.
MMRO <12> when set disables FUTURE MEM MGMT
traps.
J9
G
J9
Wl
MMRO <15:12> are cleared by a program wrile of
zeros to those bits.
LENGTH FAULT: ED", 0 • VA 12:5 > PlF
EO-1.YAI2:6
SSRO
MEMMGMT
TRAP
!
TO TMCA BREAK
REQUEST ARBITRATOR.
CPU INTERRUPTTRAP
VIA VECTOR 250
SSRO
MEMMGMT
DET(ll
:ill
J9
~
w
SSRC
KTF~~:~RT
f:;J
J9
w
©
VA 12:6
I
TO TMCC CPU ABORT
lOGIC. CPU ZAP &
TRAP VIA VECT 250
dQJ
=J
(!ffI)
SSRA OST (11
MMRO
NON RESIDENT
SSRC {PAGE LENGTH ERROR
ABORT
flAGS
READ ONLY VIOLATION
TRAP MEMORY MANAGEMENT
MEMOAV MANAGEMENT AEGISTEr-lS
15
I,
I
I
PA'
,
,
!
Page Addnss Register
CONTENTS USED FOR 18 OR 22 BIT
ADDRESS RELOCATION
1514
,
,
ACF
,
,
Page Desr:ripiiOA Register
r,'EArmIG
4
5
6
7
NON RESIDENT, ABORT ALL ACCESSES
READ IWLY, ABORT ON WRITl TRAP ON READ
READ IWLY, ABORT ON WRITE
NDT USE~ ABORT AlL ACCESSES
READ/WRITE, NO ABIIITS, TRAP ON READ/WRITE
REAOIWRITE, NO ABIIITS, TRAP ON WRITE
REAOIWRITE, NO ABIIITS, NO TRAPS
UNUSED, ABORT ALL ACCESSES
ED
MEANING
0
UPWARD EXPANDABLE PAGE
DOWNWARD EXPANDABLE PAGE
0
1
2
formal IIf Memory Managemenl RegistuNO IMMIII) 11 m512
151413121110
9
8
:U
7
6
5
---
4
3
2'
1
3
IIlliIW.IAiPllllIlllll
WABrd
'ABORrlDlR
'ABORT-PAG
UNGTHERRO
'ABORT-PiADillY}
~
""""1lA
IIW'-II
M:tMIlAGEMENT
HOI USED
IIIIIU5EO
EllABLfMEMIJI y MANAGEMUT TRAP
IIWITENMC [MODE
IIISIRUCTbJl OOMPLETED
PAGE MODE
PAGEAOORESS SPACE 110
PAGE.UMBER
EIlABlEREl.II'.AnON
1
Format 01 Memory Management RegisteJ Nl (MMRI) 17 mS74
15
11
B
10
,
1
!
AMJUNTCHANGEO
Q'sCOMPlEMENTj
REGISTER
lUMBER
,
2
I
'
I
!
I'tsOOMPWllIn
;W._.
,
!
ACTIVE PAGE
PLF
nmsnR
AM(JUIITIlLUIilD
PAGE LENGTH FIELD
·SETS ADDRESS ERROR LITE ON FRONT PANEl.
NIIMBER
15
I
PAGE WAS WRITTEIIINTO
A
!
,
fllmalof tilllllry Management Register f2 IMIIII2I11 Tn516
I, ,
W
I
I
,
NOTE: MMRO BITS 15 AND 14 WILL BOTH BE SET IF
AN ILLEGAL CPU MODE IS USED, IE:
PS<15:14> = 10
lS-BITVIAlUAlMNlRESS
Formal 01 MelllOlY"anagement Re!listerf3 !MMIL1j 11772i16
15
@
6
5
4
EIIABlElIIIlBIlSMAP
EIIAilE 228fT MAPflIIG
flABlI }KERla
I
:~VISOR
oSPACE
3
; . I II
2'
1
0
,"001,
I
III
ACTIVE PAGE REGISTERS
15
14
PruCtsSOl Status WI)fd
I SPACE
oSPACE
I
KERNa~
APRIl
1
APRD
Imm;
11772316
117723:11
11112332
11112334
11112336
177ll37Il
11712312
17712374
1=
PAR
PDR
PAR
PDR
PAR
USER 1111
APRO
,=
1=.
177l23OO
177l23Il2
11112114
171l23OO
11772310
11772312
11712314
17712316
SUPERVISOR «Ill
I111Z14D
1111l2OO
1771Z!42
lrom
I111Z144
11112204
17m246
1111m
17772210
1=
ITm252
17772212
1i712254
17T12214
17712216
17772216
11117&40
17111642
11111&4<
11111S4O
1111165
MMR3<4>
ADRS MODE
CLEARED
X
16 BIT
SET
CLEARED
18 BIT
SET
SET
22 BIT
NOTE: MMRO and MMR3 are cleared by Power Up, Console START, and the
RESET Instruction.
UNIBUS ADDRESS H
~
I I I
15114113112 11
I 21
~
I
[
~
I
I
I
....."
•
-
I
VIRT. ADRS
1
-
20 I 19 I 18 I 17 I 161 15 14 13 12 11
[
10 9 8 7 6 5 4 3 2 1 0
..--.....
10 987 6 5 4 3 2 1
BITS <21:16> = 1'5 IF UNIBUS ADDRESS
BITS <21:16> = 0'5 IF NOT UNIBUS ADDRESS
88
0]
PHYS.ADRS
1~1~~
APF
VIRT. ADRS
DISPLACEMENT
IN BLOCK
BLOCK #
r------iPAR SELECT ~
PAR
~ 21
20 19 18 17 16 15 14 13 12 11 10 9 8 7
61
I
I
I
I
I
ADDER
I
12..8~B~'T~U~B~A~D~R~s~I.:::~::=::;-____1____- __ ,
I
I
I
I
I
I
12 11 10 9 876 5 4 321 0
14 13 12 11
----~
10 9 876 5 4 3 2 1
BITS <21:18> : I's IF UNIBUS ADDRESS
BITS <21:18> : O's IF NOT UNIBUS ADDRESS
89
oI
18 BIT PHYS.
ADRS
22 BIT PHYS.
ADRS
VIRT. ADRS
h5 14 13
"---v--"j
APF j
DISPLACEMENT
IN BLOCK
BLOCK #
I
I
.-------1 PAR SELECT 1"-
G
I
PAR 421 20 19 18 17 16 15 14 13 12 11
1
10 9 8 7
--
6J
I
ADDER
I 21
!
20 19 18 17 16 15 14 13 12 11
10 9 8 7 6
UNIBUS ADDRESS IF BITS <21:18> = 1
22-Srii" ADDRI::SSING
90
4 3 2 1 0
22 BIT PHYS.
ADRS
1C~=dA~ufE~ ~ ~
l!l~j~[Sll!l~ MA~
CONTENT
PAGE
BLOCKS
RELOCATION
REGISTERS
92-94
95
96
91
-
R
MSYN
=D--
UPPER & LOWER
LIMIT JUMPERS
MAPB
11
I
<17:13>
I
CCBC UB ACKN l
I
LIMIT
COMPARATOR
MAPF
MAPF UB REQUEST I11L
FF
MA~
NOT PERIPHERAL
PAGE
I
MAPD ENAB MAP
SCCL ENAB MAP H
r----"R
----0
MAPA DATA <15:00>H
UB
OATA
0<15:01>
0<05:00>
MAPA
'---
A<17:13>
A<00:02>
--
1
"
I
MAP REGS.
JMX
MAPH
....
RA <21,01>
r---'ji"
r-AOOER
I
MAPl
MAPC, MAPO D
MAPE CA <21:01> H
R RA<17:01>
MAPE
UB
AOORS
MAPA
-
MAPA CAOOH
r---
-
I--
~=
.
MAPB CACHE REG L
CACHE REG L
C1.CO
MAPB
MAPA ADRS <03:01> H
MAP REG OP
~
-QD-
.....
MAPB C1H. CO H
----0
Il=r---> ~
-..../
CCBO UB TIMEOUT L
CCBC UB OONE H
V
<15:01>
<05:00>
r--'-OTML CDMX 0 <15:00> H
-"
'!Y
CCBF REG 0 <15:00> H
BUFFER
REG
MAPH
BUS SSYN
j -----0
BUSO
3'>
~
'---
.
.
MAPB PB OATA H
r-'--
I
OTML BAO PARITY H
FF
MAPH
'--NOTE:
o- UNIBUS OAIVER, R - UNIBUS RECEIVER
FIGURE 11.1
92
D
BUS PB
11·4018
UNIBUS
MSYN
CACHE
UNIBUS MAP
{
MAPF US REQUEST (1) L
CCBB PRE UBUS F/F
CCBC UB ACKN L
CO
MAPB CO H
ADMJ CO H
C1
MAPB C1 H
ADMJ READ L
{"'' -"
}
MAPE CA <21 :01> H
A <17:00>
MAPA ADRS <03:01> H
} CCBH, CCBJ (REG, LOGIC)
MAPB CACHE REG L
"<',~ {
ADME AMX <21:00> H
COPE WRITE MUX <15:00> H
MAPJ DATA <15:00> H
DTML CDMX 0<15:00> H
(MAPJ) BUS 0 <15:00> L
CCBF REG 0<15:00> H
PB
DTML BAD PARITY
(MAPB) BUS PB L
MAPB PB DATA H
CCBJ (REG. LOGIC)
CCBC UB DONE H
SSYN
(MAPS) BUS SSYN L
CCBD UB TIMEOUT L
SCCL ENAS MAP H
MAPD ENAB MAP L
11-4052
FIGURE 11.2
93
6
G
0
!!
LIMIT JUMPERS _ ,
G')
I
C
:II
6
m
=
W
.....
!W .....
2::::,
UNIBUS
ADRS
RECURS
V:>
";('J
MAP
LIMIT
COMPAIR
A <00>
A <17:13>
A <17:00>
BUS A <17:00>
0
t
A <17:13>
F
(Q
•
CACHE ADRS <21:00>
(\J
M
IidJ
V:>
MAPPING
REGISTERS
W
to
.j:o
RA <21:01>
r-
'"dB
~
V:>
~
BUS D<15:00>
CACHE D<15:00>
~I
UNIBUS
DATA
RECURS
•
•
CACHE
DATA
CATCH
REG D<15:00>
RA <21:16>
I
RA <15:01>
DATA <15:00>
:
CACHEDATA<15:00>
UNIBUS
DATA
DRIVERS
BUS D<15:00>
.--------1
BUS A <17:13> SELECT
ONE OF 32 MAPPING
REGISTERS, 00-37
21
001
1<
37
01
MAPl
,
I,,:
MAPH
I
\\
--v-
I
01
21
00
CACHE ADORESS
MAPE CA <21 :01> H, MAPA CAOO H
Single Mapping Register 11 of 31) 17770200 - 17770372
15
6 5
0
15
1 0
16 HIGH ORDER BITsLtl ~:::~~;~1~6ElO~W~0~R~DE~R~B~IT~S~~~~~----r--;~1I
ALWAYS ZERO J
DOUBLE WORD
17
UB ADDR
SELECTS ONE
13 12
0
1!--'_::--,J--_'--_ _ _ _ _ _-t-r"J
~I
G=_'it;._.3~1_~R~E~~I:~T:~R~:~_~_~-~-~-~-~"~A~+~B~EN~A~Bl~E~D~BY~M~M~3~~~1:1,5r,
I
I
I
,
~21
~--------------------~~
RESULT OF ADDING UB 12:1 & MAP REG 211
21
CA ADDR L1...l..1_ _ _ _ _ _ _--,,-_ _ _ _ _ _-'--'-'
t
TO CACHE
ADDX MUS
FIGURE 11.4
95
ACCESS TO UNIBUS MAP REGISTERS
Unibus Address
Read or Write
Register No.
Unibus Address for
Memory Reference
MAPL
MAPH
0
1
2
3
17770200,
17770204,
17770210,
17770214,
02
06
12
16
17000000 17020000 17040000 17 060 000 -
17 017 777
17 037 777
17057777
17 077 777
4
5
6
7
17770220,
17770224,
17770230,
17770234,
22
26
32
36
17 100 000 17120000 17140000 17 160 000 -
17
17
17
17
10
11
12
13
17770240,
17770244,
17770250,
17770254,
42
46
52
56
17200000 17220000 17240000 17260000 -
17217777
17 237 777
17257777
17277 777
14
15
16
17
17770260,
17770264,
17770270,
17770274,
62
66
72
76
17300000 17320000 17340000 17360000 -
17 317 777
17337777
17357777
17 377 777
20
21
22
23
17770300,
17770304,
17770310,
17770314,
02
06
12
16
17400000 17420000 17440000 17460000 -
17 417 777
17 437 777
17457777
17477 777
24
25
26
27
17770320,
17770324,
17770330,
17770334,
22
26
32
36
17500000 17520000 17540000 17560000 -
17
17
17
17
30
31
32
33
17770340,
17770344,
17770350,
17770354,
42
46
52
56
17600000 17620000 17640000 17600000 -
17 617 777
17637777
17 657 777
17 677 777
34
35
36
*37
17770360,
17770364,
17770370,
17770374,
62
66
72
76
17700000 17720000 17740000 17760000 -
17
17
17
17
* Note: Can be read or written into, but not used for mapping.
96
117 777
137777
157777
177 777
517
537
557
577
717
737
757
777
777
777
777
777
777
777
777
777
CHi~~U~~
'u2
~H7q]
CONTENT
PAGE #
BLOCKS
UNIQUE REGISTERS
98,99
100
•
97
...
!!
\
Q
I
c
....
N
:... ~
~
~
V
f-....
BUS
D<17:00>
_
.A
,
MASS 0 <17:00 & OPA>
I
... I
RECEIVERS I
DRIVERS
....
.... I
....
~
I
I
C
M I ...-L
oK
=
~ ~~~lB~;
H
E
8
~
AWRB
I
I
DRIVERS
I
I
I
~
I
I
I
~
F
A
C
E
BUS AD DR
A <15:01>
~
U
MBC BUS
D<31:00>
PA <3:0>
AWRC
,
/\
"
.A
DRIVERS
MOPH
READ
l-
....
AWRO.E
I-
BUFFER
CONTROL
MOPA.O
j\
...
..
1\
t, ~
MEMORY
CYCLE
CONTROL
CSTC
I-
WORD
COUNT
OVERFLOW
........
./
-....
I
AWRE
WORD
COUNT
MASS SClK
t<-
J
I
MASSBUS
CONTROL
~
EBl
RUN
I
DRIVER
MBSA
J
I
RECEIVER
MBSB
J
DRIVER
1
CSTB
1
MASS WClK
1
1
I
I
MBSA
MASS ElB
M
A
S
S
MASS RUN
I
B
U
S
START
COUNTER
AWRO.E
CSTE
r
'--
MASS 0<17:00& OPA>
I
WRITE OR WRITE CHECK
I
C DRIVE WORD
COUNT
1
8 WORD
FIRST IN-FIRST OUT
DATA BUFFER
AND
PARITY CKTS
BA <21:01>
I
I-.
n
I-
AWRE
MOPB.C.F.H
I,
I
'""
DRIVE COUNT
OVERFLOW
AWRA.B
MEM
'
0<31:00>
BYTE <3:0> PAR I
I--I---
_
,
.....,.
U
S
)
"'-----'1
RECEIVER
MBSA 1
I
EXT
BUS AOOR
A <21:16>
WRITE
UlISClKI
I
r-
1
CLOCK
MAINTENANCE WRITE
I
DRIVERS
MBSA.B.C
WRITE
0 <17:00>
I
RI
Y
MAINTENANCE REAO
L.._ _B:;;:C:;;;T0:..l
~
~
.....
K
~
., ....
"
MOPE
I.A
B
co
~
WRITE CHECK
I
~
(Xl
WRITE CHECK
ERROR
XOR
I
U
I;>-
I
WRITE CHECK
I
:D
m
RH70
REAO OR WRITE CHECK
J
RECEIVERS
,I-------J
MBSA.B.C I
J
:!!
C)
c:
::D
...m
I\)
N
WC OUT ~
(FROM
DECODER I
DB OUT
(FROM
DECODER I
CLOCK
BA
CLOCK
CS1
CLOCK
CS2
I IE
CNTRlOUT
(FROM
DECODER I
CLOCK
DB
MASS
C<15.00>
co
co
I
MC~~S
Q
I
CNTRL DUll
WC IN L. WC OUT L
AS IN l. AS OUT l
MASS OS <2:0>
DEMAND
f-----+i'l
LOCAL
RSEL <04:00>
PJH?«JJ
•
MASS CTOD
CTOD
-~
PJE«]~~TEPJ
DRIVERS
I
MBSA.B.C
CONTPJOl PATH
A
I~
MASS TRA
CS11N L, CS1 OUT l
CS2 IN L CS2 OUT l
BCTA
1M
S
5
B
UNIT
SELECT
CS3 IN L. CS3 OUT L
DB IN L. DB OUT L
BA IN L. BAOUT L
BAE IN L. BAE OUT L
I
MASS RS <4:0>
MASS OEM
ADDITIONAL r.r::GISTI::RS r-OP. P.H70
The RH70 has the same registers as the RH11 plus two more, the Bus Address
Extension Register and Control and Status Register 3
15
14
13
12
11
10
9
7
8
6
5
4
3
I I I I I I I I I I I'" I,w I,
0
0
0
0
0
0
0
0
0
19
0
2
o
1, 18 1A171 A161
Gus Address i::J:tension Register
BITS <5:0> - USED FOR 22 BIT ADDRESSING ON THE 1170
15
14
13
APE
DPE
OW
DPE
EW
12
11
WCE WCE
OW EW
10
9
8
7
6
5
4
DBL
0
0
0
IE
0
0
Contro! and
S~a~w:;
Regisier 3
BIT
MEANING WHEN SET
15
14
13
12
11
10
6
3
2
1
ADDRESS PARITY ERROR DETECTED IN MEMORY.
DATA PARITY ERROR ODD WORD FROM MEMORY.
DATA PARITY ERROR EVEN WORD FROM MEMORY.
WRITE CHECK ERROR ON ODD WORD.
WRITE CHECK ERROR ON EVEN WORD.
DOUBLE WORD WAS THE LAST TRANSFER.
INTERRUPT ENABLE (SAME AS BIT 6 OF CS1).
INVERSE PARITY CHECK (DIAGNOSTIC PURPOSES)
o
100
3
2
o
IPCK IPCK IPCK IPCK
0
1
3
2
C~~~APuE~
·u3
MJ·u·u
CONTENT
PAGE #
MDL
BLOCKS
STACK CONVERSION
102, 103
104, 105
106, 107, 108,
109
101
MINIMUM CONFIGURATION 64K WORDS
,------------16K
16K
\
MAIN
MEMORY
BUS
26 25 24 23 2221 2019 18 17 1615 1413 12 11 1098
-.--
~.-.,-
--..-
STACK
STACK
STACK
STACK
0123
---------- ----------
7 6 5 4
--..- -..-..--
3 2
~
(EVEN) LOW WORD
(ODD) HIGH WORD
addresses XX XXX XXO
XX XXX XX4
add resses XX XXX XX2
XX XXX XX6
EVEN
ODD
FIGURE 13.1
~v~JIJ U ~(j~~L0~(j)P.lV
102
1
-..-.'
STACK
STACK
STACK STACK
3210
ADDRESSES
XX XXX XXO
XX XXX XX4
ADDRESSES
XX XXX XX2
XX XXX XX6
MJll-A BACKPLANE
ROW
~
~ ~
~ ~ ~
1 ~ 1 ~ J- 1 J- J- 1 J- 1
A
B
G
H
G
G
G
G
H
G
G
H
G
M
M
G
G
G
G
G
H
G
G
2
I
I
2
2
2
2
I
I
8
8
2
2
I
2
2
2
I
2
2
I
I
I
I
2
5
4
5
I
4
I
4
I
I
4
, , , ,
H
2
,
H
I
I
,
H
2
,
H
_2
4
5
7
C
4
5
4
5
,
o
5
-
I
7
C
I
7
C
,
I
7
C
,
I
7
C
5
4
9
8
I
7
C
7
C
4
5
I
G
I
I
7
4
C
0
R
M
B
E
I
4
--:':--:
--::':---::026 25 24 23
I T TI
.-
~
22 21
~
20 19 18
~
LOW WORD
STAet< 0
lOW WORD
SlACK 1
LOW WOAD
STACt< ;:
ROW
,1
17 16
15
~
I
14
7
13
'---'
T I"
12 11
10
~
LOW wORD
MEMORY
HIGH WORD
STACK 3 CONTROLLER STACK:3
1
,1- ,1 ,1-
1 1
'II '1 '1
'11 '1 1
:3
9
8
7
,~
6
5
4
~
'-----'
HIGH WORD
STACK 2
HIGH WORD
STACK 1
HIGH WORD
STACt( 0
1 ,1-
,1 1
2
1
SLOT
1 1
A
B
G
H
G
-2
2
2
I
I
,
4
6
6
,
o
6
-
C
G
H
G
2
2
2
I
I
,
4
6
6
C
M
G
H
G
G
2
I
I
2
2
G
I
2
,
H
2
I
, 8,
4
2
6
6
6
4
4
9
7
14
13
C
4
C
M
8
G
H
G
G
G
G
G
G
G
2
2
2
I
2
2
2
I
I
2
I
2
I
,
H
I
2
,
H
2
,
H
2
I
I
4
6
6
4
6
6
4
6
6
4
,
6
C
C
C
2
C
6
E
-
~
--:::-.:::-.~
26 25 24 23 22 21
..
'-----'
~
STACK 0
STACK 1
LOW
WORD
LOW WORD
I I
20
19
18
,~
LOW WORD
STACK 2
T 'I
17
16
15
1.............---.....-----' "--.....,---J
LOW WORD
MEMORY
I I II I I 1 I
12
~
9
B
7
'---...,---J
HIGH WORD
HIGH wORD
STACK:3
STACK 2
STACK 3 CONTROLLER
"
10
6
5
4
T1 1
:3
2
1
SLOT
'-----'
'-----'
HIGH WORD
HIGH wORD
SlACK 1
STACK 0
MJll-B BACKPLANE
NOTE:
1. This figure illustrates a view as seen from the pin
side (in a maintenance position with the power
supply below the modules).
2. Stack 0 consists of two 16K word stacks (MJ11-A)
or two 32K word stock (MJ11-8). Likewise for
stack 1, stack 2, & stack 3.
I
+-______ IOdd Frame
L -_ _ _ _ _ _
~
IL-________
~--------~
Cache _ - - - - - - - '
MJll Interleaving
FIGURE 13.2
103
IEven Frame
;=::0
•••
•
•
~
~
d9
1!0
1!0
3
Uuil
ffi;
ffi;
........
::D
...pm
M8147/8
Co)
to
\
·••
G235/6
STACK SEL
"---
,
=~
STACK
A <15:01>
r---
"-
to
F
-I'>-
~
000
PARITY
CHECKER
A <21:16...>
:2J
0
ADDRESS
r--~PARITY
ERROR
MAIN A <21:02>
BYTE MASK <3:0>
MAIN C <10>
MAIN ADRS PARITY
~
&
•••
•
••
"TI
=
i5
Go"
c:
r-
\\'J
d9
XDRIVE
STACK SELECT
Dlff
CONTROL
I--
YDRIVE
~
SA <21:16>
I
N
T
E
R
N
A
L
.--
=J
~
'--
16 BLK
ADDRESS
SA
SWITCH
'---
.---
A <15:02>
ADRS
LATCH
STACK
A<15:D1>
G114/6
B
U
S
~
MAIN C<0:1>
BYTE MASK <03>
MAIN START
CONTROL
SIGNAL
GENERATOR
CONTROL
CONTROL LINES
•
-
H2171H224
C?
=
."
"= i5
c
.d,
.d,
:II
IQ)
.....
p
=J
m
---II
~
01>0
HIGH
P
u
P
DATA
M8149
=J
DR~~~RS
INTERNAL
~
II
I"
H217/H224
SENSEIINH18IT
..
"
HIGH
OATA
..
I
..
I
J3
ODD WORD DATA
BUS
DRIVERS
INTERNAL
BUS
RECEIVERS
o
0"1
I
INTERNALI
BUS
ORiVERS
I
C
LOW
~
H217/H224
G114/6
DATA
J1
~
EVEN WORD DATA
DATA
SENSE/INHIBIT
BUS
DRIVERS
...
INTERNAlI....c:·
BUS
,RECEIVER
w
it
MJ11-A 161(W STACI(S
BOX MAX = 1281
17777 740
...
m
-
LOW ADDRESS (?????????)
----
.......... ,-
Ol
Low Error Address Register
~
~
~
ffl
15
=~
P
17777742
(1
=
14
I CY~LE
13
6
W##$$~
5
. HIGHADDRE~S
0
I
•
",,,"
ffl
High Error Address Register
0
~
16
15
21~-
121 1 20 119118117116115
----..
II I
1
L
L-
•
1
I
1
I II
1
I
-0
1
I
0
I
22 BIT
ADDRESS
-..-
~~----~~
I
1
~
STACK # ,0-3
BOX#,0-7
L
EVEN~OOR4
ODD
~
2 OR 6
MJ11-B 321
c:
0
LOW ADDRESS (?????????)
---
::0
...
m
~
---
-..............
Q)
~
Low Error Address Register
c,:i
"~
M
rm
15 14 13
=~
6 5
I CY~LE W/I;f;01~
:b
0
0
HIGH
ADDRE~S
I
,
M
rm
High Error Address Register
0
<0
16 15
121 120119118117116115 1 1 1
21~-
,./"0.."
111 111
I 111 1
0
1
22ADDRESS
BIT
-...-
~~
L-----I.~
-0
STACK
BOX
#
#
,0-3
,0-7
L
EVEN
~
0 OR 4
ODD
~
2 OR 6
CONTENT
PAGE
MDL
BLOCKS
REGISTERS
MAXIMUM MEMORY NOTES
112, 113
114, 115
116, 117
118
111
NOT USED
STORAGE ARRAY #14
2
STORAGE ARRAY #12
3
STORAGE ARRAY #10
4
STORAGE ARRAY #8
5
STORAGE ARRAY #6
6
STORAGE ARRAY #4
7
STORAGE ARRAY #2
8
STORAGE ARRAY #0
9
CONTROL B #0 M8161 (CBB)
10
CONTROL A #0 M8160 (CBA)
11
NOT USED
12
ADDRESS BUFFER M8158 (ABB)
13
NOT USED
14
DATA BUFFER M8159/64 (DBB)
15
CONTROL A #1 M8160 (CBA)
16
CONTROL B #1 M8161 (CBB)
17
STORAGE ARRAY #1
18
STORAGE ARRAY #3
19
STORAGE ARRAY #5
20
STORAGE ARRAY #7
21
STORAGE ARRAY #9
22
STORAGE ARRAY #11
23
STORAGE ARRAY #13
24
STORAGE ARRAY #15
25
NOT USED
26
~
FRONT
(TOP VIEW)
FIGURE 14.1
GlA-
I
,
36 BITS
"
,
'\.
/
CSR5l
I
N
T
E
R
F
A
C
E
DOUBLE ERR
INDICATOR
t
DATA
RECEIVERS &
TRANSMITTERS
MAIN
DATA
36 BITS
B
U
S
32 DATA BITS
4 PARITY BITS
DATA BUFFER
(M8159/64)
I
I
U
-- ------------ ---- r-
r::l
SlIlGLE/OOUBLE
ERROR
~~~g~E
"
/
.
ERROR
DETECTION
&
CORRECTION
LOGIC
I f-[
.--L,"
I+7
r;-
t
32
SINGLE
BIT CORR. &
PARITY
3l-GEN.
DIR
-
I .or' I
7 CHECK BITS
J
7
~
M
0
32
R
PARITY
CHECK
'----
B
U
S
CONTROL BO
(M8161)
l
WRITE
PARITY'
ERROR
L.J
A
R
R
A
Y
;+-
l4
4
I
N
T
E
R
N
A
L
.
0
-
I AR~AY I
"T'I
-
M~~~~
C5
C
JJ
P;'[j)[j)~~§S ~AuH
.....
P;'[j)[j)~ES§ [j)~Cg[J)E
m
.--
'~r::l
~
r--
•••
•
B
U
S
0l:Io
W
1
CONTROL Al
•
-
CONT SEL
A <02>
A <17.02>
I
,
A <17:02>
(J"I
I
I
I
ARRAY SEL <0-2>
I
I
I
N
T
E
R
N
A
L
E
MAIN
A <21:02>
I
I
;
A <16:21>
NA
.--
-
ROW/COL A <0-5>
DECODE
ROW SEL <0-1>
'---MEM SEL <0-7>
DECODE
I
START
ADO.
FROM
CO NT
PANEL
AnnRFC::C:: RIIFFFR
(M8158)
•
L
B
U
S
CONFIG
CIRCUIT
B-8
•
I
N
T
E
R
N
A
A
R
R
A
Y
B
U
S
RA
SA
SCAN
, OF 16K ARRAY
0
, OF 16K x 32 BLKS
1
---------- -------------- ----
I
N
T
E
R
F
A
C
• 1 '":"
COUNTERS
FINGER PRINTS
J1. J2
BOX CAP.
'---
L-
CONTROL A 0
(M816D)
•
I::l
LJ
•
•
•
•
•
1--8
ACCESSING
,------------,
I
C'UASSEMBlY
I
I
I
I
I
I
I
• Halt all NPR activity in system
I
CPU.
MEM MGT
esP-'s
UNIBUS
• Turn off cache
17777746 -- 14
• Set up map 0
17770200' -- 170000
17770202
77
• Turn on Unibus map
17772516 -- 40
• Turn display switch to console physical
L_
• Examine/deposit
17002100 through 17002136"
'Sets up map to contain relocation constant.
"Unibus address from switch register to Unibus map which will be
added to 17,770,000. This will produce 1/0 page address of CSR
(17,772,100).
MA 1330
M({11 eSA'S
1ST WORO
y
OBE
• CHECK
• SYNOROME
• CAPACITY
BAD
ARRAY
SBE
DlAG.
CHECK
PROTECTION
POINTER
ENA
PAR
TRAP
ECC
DIS
2ND WORD
~------~y--------~}
'---y-------'
BAD
CONTROL
STARTING ADDRESS
'NOTE: DBE DOESN'T NECESSARILY MEAN
YOU HAVE A BAD ARRAY. MK11 DOESN'T
TELL YOU WHEN IT RECEIVES BAD
PARITY AND FORCES BAD ECC TO BE
WRITTEN INTO A LOCATION. THIS
RESULTS IN A DBE ON A SUBSEQUENT
READ OF THAT LOCATION. BE CAREFUL
CHANGING ARRAYS FOR INTERMITTANT
DBE'S WHICH MAY HAVE BEEN CAUSED
BY A PROBLEM IN THE DATA PATH TO
THE MK11.
INTERLEAVE
DBE
INTERLEAVE
ST. ADDR./LOAD
-NORMALLY A '.,.. ON POWER UP
--NORMALLY A "I" ON POWER UP WITH AN EVEN. OF CARDS
First Word
Second Word
Bit O' (Ena. Par. Trap) gets set on power up
Bits <8:0>* (Starting Address on Box Controller Thumbwheel Switches)
• When set:
Asserts bad parity on OBE
Asserts bad parity on SSE with ECC DIS
Bit 9** (Control Select)
• Identifies array group error was found in
0= on right
1 = on left
• When cleared:
Keeps processor from aborting on
SBE/DSE
Bit 10* (Starting Address Controller)
Bit l' (ECC Disable)
• 0 = Source of starting address and ex!. in!.
is box controller/sw. on data buffer mod.
• Allows SBE to be detected as uncorrectable.
116
Bit 2* (In diagnostic mode when
=
1)
• 1 = Program control is initiated which
allows a write to:
<14:12> ext. interleaving
<8:0> starting address
<11> internal interleaving
• On a read check bits of addressed
OW _ CSR <14:8>
• On a write <14:8> of CSR - CK bits of
addressed OW.
Bit 11** (Internal Interleaving)
Bit 3* (Protection Pointer Overrides Bits 1and 2)
• Set on power up when number of array
cards = even
• 0 protects first 16K bank of memory
• 1 protects second 16K bank of memory
• To uninterleave internally
Set bit 10
must be in force panel mode
Clear bit 11
Bit 4* (Single Bit Error Indication)
Bits <7:5>** (Bad Array)
• If number of array cards are odd cannot be
set
• When bit 9 of second word = 0 bad array on
right
• When bit 9 of second word = 1 bad array on
left
Bits <14:12> (External Interleaving)
•
•
•
•
Bit 12 = two-way
Bit 13 = four-way
Bit 14 = ext. A02
When bit 10 is 0 source of interleaving is
control panel
• When bit 10 is 1 source of interleaving is
under program control
Bits <14:8>' (Check/Syndrome/Box Capacity)
• Bits <3:1> equal 010 = stores check bits
• Bits <3:1> equal 100 = box capacity is
stored
• Bits <3:1> equalOOO = syndrome bit
storage
Bit 15* (Double Bit Error)
Bit 15* (Double Bit Error)
*Can read or write this bit(s)
**Can only read this bit(s)
*Can read or write this bit(s)
**Can only read this bit(s)
117
I\/m:11 MA)(IMUM MEMORY NOTES
Due to the I/O space taking up the top 128KW of the 2MEG total address space
on the 1170 memory bus, you can not have more than 1920KW of physical
memory in any number of MJ11/MK11 boxes that may exist on the bus. The
reason is that any address in the 1920K to 2048K range will conflict with the
addresses of the MK11 CSR's. Problems have arisen when attempts have been
madeto install a full set of 16, 128K arrays in a MK11 box. Adding the 16th array
brings you to 2048K causing dual adressing between the last array and the
MK11 CSR's in that box.
In these cases you must reduce memory size one of three (3) ways.
1. Pull one array going to a total of 15 arrays. This will kill the internal
interleaving and give the max memory size of 1920KW.
2. Pull two (2) arrays (down to 14 total) reducing size to 1792K and allowing
internal interleaving.
3. The best if possible. Go with two (2) 32KW arrays in arrays 0 and 1. Arrays
2-15 should be 128KW arrays. This give you 1856KW of total memory and
again keeps internal interleaving in place.
You can see that you can have the maximum of 1920KW but to do that you
sacrifice the added speed of internal interleaving. By using STEP #3 above you
only loose 64KW of memory but gain the speed of interleaving. If the customer
must have the maximum allowed go to STEP #1.
118
PAGE #
CONTENTS
THIS SECTION CONTAINS A COpy OF THE
ELECTRONIC CONSOLE COMMANDS POCKET GUIDE.
KY11-R TROUBLE SHOOTING
119
119-123
124-124B
PDP-11170
ELECTROfJIC COfJSOLE COr,1r.1ArJDS
INDICATES CONSOLE HAS PWR
B
SW
RUN1
HAL r
RUN 0
DISABLE
LOCAL
LDCAL:@REMDTE LIGHT
DISABLE
DISABLE
OFF
REMOTE
tr
WILL ALLOW CPU TO
PWR UP RUNNING WITH
sw
REG IN IT TO ALL Os
DISABLES PWR FAIL RESTART
SW REG INIT TO ALL 1"
TK1311
KEYSWITCH POSITION DESCRIPTION
• 20 seconds have elapsed without using console, and
• Program is running, and
• Character Ready bit is set, and
• Key switch in LOCAL.
Turns CPU and electronic
console off.
LOCAL DISABLE
II P recognition disabled,
disables all console functions.
LOCAL
liP recognition enabled, enables
all console functions at local
terminal.
REMOTE DISABLE liP recognition disabled,
disables all console functions,
forces local copy.
REMOTE
II P recognition enabled, enables
all console functions at remote
terminal.
OFF
LEGEND:
All RED symbols typed by human. All other
symbols typed by CPU.
II P
S
THREE SEPARATE STATES
Program liD
State
Console
State
Talk State
[n]
Command Z Allows
communication
with program.
Command II P Console
communicates
with CPU interface
(accepts
commands)
Command ilL Allows two-way
communication
between local site
and DOC (Digital
Diagnostic Center)
operator
m
Means typing the control key and
the letter P at the same time to
perform the command.
Means typing $ to perform the
command.
Is used to indicate that a numeric
variable is REQUIRED.
Is used to indicate that a numeric
variable is OPTIONAL.
Is content of console switch register.
Means that a and were
generated by the CPU.
CONSOLE CONTROL COMMANDS
liE
liP
NOTE
Console (V02-00 or greater)
reverts to program liD state when
the following conditions occur:
[n] R
120
Prints ASCII text that identifies CPU
and console code revision;
Example: 11/70 V01-00.
Sets talk state; ignores all
characters except P.
Sets console state; puts address
display multiplexer to console
physical; puts data display
multiplexer to data paths.
Will load and read control register;
if data precedes Rit will load it; if
no data precedes Rit will read it.
CONTROL REGISTER
'SUPRESSES
REMOTE
TYPEOUT
SPECIAL
MODE
SUPPRESSES
• SYNTAX
ERRORS
• RUNNING
ERRORS
EXPANO
PRINTOUT
'TALK
ECHO
'LOCAL
CONTROL
'LOCAL
COPY
ADDS AN "M"
COMMAND
AFTER EACH
"N"COM
ENABLES
LOCAL COPY
IN TALK
MODE
ENABLES
LOCAL
CONTROL IN
REMOTE MODE
OUTPUTS
LOCAL COPY
IN REMOTE
MODE
TK-1224
'THESE BITS CAN NOT BE SET FROM LOCAL TERMINAL.
AU
Clears the data typed in the
temporary data register.
Sets a flag to indicate a register
versus a memory location;
Example: $n/xxxxxx
will examine contents of general
register n.
Data separator before a start or go
command;
Example: 30,17765000G.
Verifies console logic; will print
V000377 if no fault is detected.
Sets serial line multiplexer to
program 110 state.
Rub out; deletes the rightmost octal
character from the temporary
register. DEL KEY causes "rubout"
action to occur.
Example: 1234\4\3\2\1\0\0
(For V01-00 consoles)
1234\4321\
(For V02-00 consoles),
$
v
z
nl
[n]@
B
[m], nG
p
n\
• On V02-00 the backslash only occurs on the
first and last character being deleted from the
buffer.
Performs load address and
examine; effectively opens word
location n.
Reserved for future expansion.
Deposits any data typed and uses
contents of currently open location
as address of location to open next.
Reserved for future expansion.
Go command begins at address n
with switch register set to m; places
console in program 110.
Example: 30,17765000G
Proceed command places console in
program 110. It continues program
from address in program counter.
Performs load address and
examine; effectively opens byte
location n.
Example:'
Ap
CON = O/XXXXXX 123456
CON = 0\056
CON = 1\247
CON =
• Command is available on consoles with an 10
of V02-00 or greater.
CPU CONTROL OOT,11 COMMANDS
CONSOLE MESSAGES
nAD
[n]
[n]
II
Dumps successive memory
locations continuously, until a
character is typed, starting at
address n.
Deposits any data typed and opens
the next sequential location.
Deposits any data typed and closes
the location to further modification.
Changes to hex data format from
octal; data is displayed in hex while
address display does not change.'
Changes tooctal data format from
hex:
Example: A P
CON = 0/123456"
00000000 I" A72 E'
00000000/123456
,,?
SYN ER"
"? RUN ER"
"? ERITXXXXX"
Fault Indicator
121
Syntax error;
command is given out
of sequence or with
missing character.
Illegal when CPU
running; certain
commands are illegal
with CPU running.
Example: Start, load
address, and initialize.
Memory reference
error; addressldata
parity error detected
during a memory
reference.
Console logic fault;
"+"
console logic has
detected an error
within itself.
Serial line error;
identifies framing or
overrun errors with a
[n] 0
"+".
H
Continues program from address
stored in program counter.
Deposit; sequential deposits are
possible (location must be open).
Examine; sequential examines are
possible.
Halt; address counter and CPU
status will be printed.
Initialize CPU.
Set single bus cycle.
Reset single bus cycle.
Load address n.
Prints data registers:
n ~ 0 Bus Register
n ~ 1 Data Paths (shifter)
n ~ 2 Display Register
n ~ 3 CPU I'ADRS
C
CPU response time
out; # is printed if CPU
did not respond to a
console command.
'''HXXXXXXXX/TXXXXX'' Programmed halt;
console will print "halt
notification" and HALT
ADDR/ status.
,,? CAR ER"
Carrier lost.
"#"
I
J
K
nL
[n] M
CPU CONTROL BASIC COMMANDS
NOTE
[n)
A
Prints address display in octal as
received from one of eight inputs to
address multiplexer.
n ~ 0 Program Physical
n ~ 1 Kernel Data
n ~ 2 Kernellnst.
n ~ 3 Console Physical
n ~ 4 Supervisor Data
n ~ 5 Supervisor Inst.
n ~ 6 User Data
n ~ 7 User Inst.
Position 1 is set by /\ P. E or
"Power on." To change data
path's position, type new
position n first then type M
N
R
[m.] nS
Execute next instruction/bus cycle.
Read switch reg ister.
Start the CPU at the address n with
switch register set to m.
Read CPU status.
Read UNIBUS status.
Write n into switch register.
T
U
nW
NOTE
/\ P or "Power On" set position 3; if
octal # precedes A, new position
is set.
CPU STATUS
1 1 1 1 14> 1
1 1
'"~\~~! ~!!I--I____'__ I I I II II
...JI
CP STOP
L_='--==
L._ _ _
.
•
r~~i!:!1~"
SINGLE CYCLE SWITCH
UNIBUS STATUS
14>1 1 1 1 1 14>1 1 1 1 1 14>1 1 1 1 1 1 1 1 1 I 1 1
NPR
BR?
BR6
BR5
BR4
L-.-
II
IIII
IIII
NPG~~~
BG?
BG6
BG5
BG4 _ _ _ _ _ _ _ _ _ _ _---J
122
DC LOW
AC LOW
INITIALIZE
BBSY
SSYNC
MSYN
SACK
PB
INTFRRUPT
CI
CO
STATUS OF
UNIBUS
CONTROL
LINES
EXAMPLES
BASIC COMMANDS
OPEN BYTE LOCATION AND DEPOSIT
I\P
CON = O\XXX
0000000I\XXX
00000002\XXX 24
00000003\XXX
WITH DOT
START PROGRAM
I\P
I\P
CON = 200S
CON = 200G
CON =Z
CONTINUE PROGRAM
I\P
I\P
CON = CZ
CON = P
READ ROM STATE
I\P
CON = 3MXXXXXXXX
DISPLAY ADRS IN CON PHY
I\P
CON = AXXXXXXXX
TO EXAMINE
1\ P
1\ P
CON = 4L E051531
CON = 4/051531
TO DEPOSIT
1\ P
I\P
CON = 4L E051531 770
CON = 4/051531 77
TO HALT
I\P
CON = H 017312401T14410
TO CK FOR RUNNING CPU
I\P
CON = T XXOXX CPU IS RUNNING
OPEN BYTE LOCATION IN A REGISTER
I\P
CON = $O\XXX
177777700H\XXX
177777701 L\XXX
TO BOOT THE SYSTEM
Bootstrap Example with initial switch value for
an RP04 (M9301-YC)
1Jl
1. Switch register value
2. Data separator
HEXADECI MAL DISPLAY
I\P
CON = "OL E"XXXX
CON = E"XXXX'
CON = EXXXXXX
I JJI
~
.
M9301-YC BOOTSTRAP (Type PH before
attempting to boot.)
10,17765000G
20, 17765000G
30, 17765000G
40, 17765000G
50, 17765000G
60, 17765000G
70, 17765000G
100,17765000G
110,17765000G
This program
will print the
letter A
TMll
TCll
RK05
RP03/RP05/RP06
RK06/RK07
TU16
RP04
RS04
RXOI
Bootstrap Example with an initial switch value
for an RP (M9312)
Using Basic Commands
Conditions
HEXADECIMAL DEPOSIT
ONLY POSSIBLE
UNDER ODT
!!.
4. Start processor/enable program I/O
fmeans program moved
character to terminal print buffer not a human
BASIC COMMANDS
17765000
3. Set the starting address
An example of how to single step a program
using the electronic console is shown below.
I\P
CON = 1000/XXXXXX 12737
0OOOI002/XXXXXX
101
0OOOI004/XXXXXX
177566
00001006/XXXXXX
O
CON = 1000L I NOO001006 A
.l.
WITH DOT
1. • Diagnostic ROM in E20
• RP06 ROM in E35
socket (ROM 1)
• Unit 0 (Drive 0)
I\P
CON = O/XXXXXX"
OOOOOOO/"XXXX 2AF1
0000002/"XXXX 2AF2
2. Same as in #1 except for
RP06 ROM in E34 socket
(ROM 3)
I\P
CON = O/XXXXXX"
00000000/ "XXXX
0OO00002/"XXXX
3.
123
liT
456,17765744G
~~~~ ~~/i~:~~''''¢f''
UNIT 2
ROM3
RP06
BOOT ADDRESS
HEXADECIMAL CONTINUOUS EXAMINES
I\P
CON = " 0 1\ D
OOOOOOOO/"XXXX XXXX ....
OPEN BYTE LOCATION IN HEX
I\P
CON = O\XXX"
OOOOOOOO\"XX
00000002\ "XX
56,17765744G
I{V11R Troubleshooting Procedure (Local)
Symptom:
Causes:
Remedy:
Turn key off to Local or Local Disable, All lights except Carrier
come on and stay on
M8255 console board, cable from J1 of M8255 to J4 of 5412781
Replace M8255, Replace 54-12781 MUX board, Check cable
hookup and connector seating
Symptom:
Causes:
Remedy:
Fault lite stays on after power up and all other lites go out
M8255 console board, Console cables
Replace M8255, Replace MUX, Check cable in connector J4
Symptom:
Causes:
Remedy:
Console prints nothing, Fault lite is not on
Console cable at J5
Check cables from J5 of MUX to the terminal, Check baud rate
switches on Mux
Symptom:
Causes:
Remedy:
Console prints V, but then prints con error
M8255 board, Cables
Replace M8255, Check J1 of M8255 board to J4 of MUX
Symptom:
Causes:
Remedy:
Console prints V000377 but still gives a Fault
LTC on M8255, No LTC slot
Replace M8255, Check for LTC from H7420
Symptom:
Causes:
Remedy:
Console prints out to many characters (i.e. V0000003777)
M8255
Replace M8255
Symptom:
Causes:
Remedy:
Console prints out wrong characters (i.e. V000375 or V001377),
Fault lite is not on
Consoie board, M8255
Replace 54-12781 (MUX), M8255
Symptom:
Causes:
Remedy:
Console prints strings of V000377
M8255
Replace M8255
Symptom:
Characters print out on terminal correctly, but there is not
activity from keyboard
MUX board
Replace MUX (54-12781)
Causes:
Remedy:
Symptom:
Causes:
Remedy:
Console will not accept some or any console commands,
although they echo back properly
M8255, +5 Volts
Replace M8255, +5 Volts on M8255
124
Symptom:
Causes:
Remedy:
A "#" symbom printed on console when executing any
command to PCU (i.e. 200G#, H#, 1000L#)
Cable loose or pins broken
Check J1, J2, J3 on MUX and CPU boards (M8140, M8134),
Replace M8140, Replace M8134
Symptom:
Causes:
Remedy:
Fault lite comes on after a few minutes of operation
MUX board
MUX board
Symptom:
Causes:
Remedy:
Garbled character printed on console when typing on
keyboard, Receives characters correctly
MUX, +15 Volts, -15 Volts
Replace MUX
Symptom:
Causes:
Remedy:
Fails Run 1-Halt-Run 0 power up
MUX board, M8255
Replace MUX, Replace M8255
Symptom:
Causes:
Remedy:
Prints H after typing N for single-step operation
CPU, MUX board
Replace M8140, Replace MUX, Replace M8255
Symptom:
Occasional *H printed on console terminal, CPU in hung, no
address printed after H
Static eliminator, Grounding, M8255
Bad or no static filter, Check for equipment (rack to rack) and
earth grounds, Replace M8255
Causes:
Remedy:
124A
[{Vii r-: Troubleshooting Procedure (Remote)
Symptom:
Causes:
Remedy:
DAA does not answer when dialed in test mode
+12, -12 Volts, to DAA
Replace MUX, Check +15m -15 Volts, Check DAA connections,
Bad DAA
Symptom:
Causes:
Remedy:
DAA busy in test mode
Called once, DAA, Phone line
Turn switch to Local and to Test, Have DAA checked, Have
phone line checked
Symptom:
Causes:
Remedy:
DAA answers to test, but not online
Keyswitch, Modem cable, Phone line
Put keyswitch in Remote or Remote Disable, Check and reseat
cables, Replace modem (54-12498)
Symptom:
Causes:
Remedy:
DAA answers in test mode, but goes busy when online
Wrong DAA cables to DAA, Modem cable, LA36 modem
Check for 1001 d label, Check connections to DAA, Check
cable seating, Replace modem (54-12498)
Symptom:
Causes:
Remedy:
DAA answers online, but no carrier
LA36 modem, Modem cable
Replace modem, Check modem cable
Symoptom: DAA unable to connect, Carrier not received from remote
console
Causes:
DAA, MUX, Modem, Voltages
Remedy:
Check if in test mode DA, Replace MUX, Replace modem,
Check +-12v
Symptom:
Causes:
Remedy:
Symptom:
Causes:
Remedy:
Symptom:
DOC connects but unable to establish protocol, Console has
Carrier lite on for a short time
LA36 modem, Cable, M8255
Replace modem, Check seating of J6, Replace M8255
DCC connects but unable to establish protocol, Console does
have the Carrier lite on
LA36 modem, Cable
Replace modem, Check J6 seating
Causes:
Remedy:
No local control of console, Talk between DOC and remote
terminal does not function
Console Uart, Console E17
Replace MUX
Symptom:
Causes:
Remedy:
Unable to down-line load any program to remote console
M8255, CPU
Check M8255, NPR circuitry
124B
rcHAl?uE~
r>ruJ
r>~(j)rc~[jJl\J~E~
CONTENTS
-
-m
PAGE
ANNUAL PM
126, 127, 128, 129, 130
125
t
A
Page 1 of 5
PDP 1170 CPU and Memory Subsystem
DEVICE:
OPERATION
1. Check CPU Regulators
- Regulator A
TEST POINT
NOMINAL
F02A2
+5V±0.1
200 MV PP
-
Regulator B
F09A2
Same
-
Regulator C
F15A2
Same
-
Regulator 0
F44A2
Same
-
Regulator H
F22A2
Same
-
Regulator J
F18A2
Same
-
Regulator K
F28A2
Same
-
Regulator L
F35A2
Same
-
Upper H7420
B01B1
+ 8V ± 1.2
240 MV PP
I\J
0>
----
Page 2 of 5
PDP 1170 CPU and Memory Subsystem
DEVICE:
t
OPERATION
TEST POINT
NOMINAL
- Upper H7420
E13A1
+15V ± 1.5
450 MV PP
-
Lower H7420
E13B2
-15 ± 1.5
450 MV PP
2. Check MK11 Regulators
- Regulator A
J18-4
J18-5
+ 5 VBB
4.9 to 5.3
+ 12 VBB
11 to 13
I\)
-..j
-
-
Regulator B
Regulator C
J18-7
- 12 VBB
-10.5 to -13.5
J21-5
+ 5 VBB
4.9 to 5.3
J21-4
+ 12 VBB
11 to 13
J21-2
- 12 VBB
-10.5 to -13.5
J21-6
+5 VBB
4.9 to 5.3
t
OPERATION
TEST POINT
NOMINAL
J21-3
+ 12V BB
11 to 13
J21-1
- 12 VBB
-10.5 to -13.5
J21-7
+5V
4.9 to 5.3
M8149-TP1
+ 5V ± .25
200 MV PP
Regulator #2
-TP2
+ 5V ± .25
200 MV PP
Regulator #3
-TP3
+ 20V ± 1.0
Regulator #1
-TP4
+ 20V ± 1.0
Regulator #3
-TP5
- 5V ± .25
Regulator #1
-TP6
- 5V ± .25
H7441 Regulator
i'U
Page 3 of 5
PDP 1170 CPU and Memory Subsystem
DEVICE:
3. Check MJ11 Regulators
Regulator #
ex>
.-
-
.-
- - _ . _ ..
_-
t
OPERATION
A
4. Check All Fans
A
5. Check MK11 Battery
Backup units for
proper operation.
6. Perform 1170 timing
margin check;
a) Connect Jumper
I\)
Page 4 of 5
PDP 1170 CPU and Memory Subsystem
DEVICE:
b) Set R162 on M8139
for slow margin
TEST POINT
NOMINAL
F13J1 to E21T1
D13T2
250 ns
prompt utilize the MOD command to implement the
changes.
3. Then use the MOD command to set the maintenance register.
CMD> MOD 177750
177750/000000 XXXXXX
Where XXXXXX is:
MK11
MJ11
o = Normal
4 = Early strobe
6 = Late strobe
Normal
Early MDR load
Late refresh
Normal
Normal
10 = Low current
12 = High current
140
4. At this point you can now run DECX11 with the memory margins you
desire.
5. If you suspect a particular bank of memory, utilize the RUNL command
to lock DECX11 into that area.
WlJ'l1 CORE WlEMOAV TUNING PROCEDURE
A)
The option consists of the following modules:
MJ11-B
MJ11-A
G236 ................ X-V Driver . ................ . G235
G116 ................ Sense/Inhibit ............. .. G114
H224-C .............. Core Stack ................ . H217-C
B)
There are two adjustable components present in the memory.
1)
~
Bias current supply controls the amplitude of the read and write
currents. Variation of the currents affects the 0 switching noise level,
the 1 switch voltage amplitude, and the time relationship between
read current start time and the core output voltage peak.
NOISE _ _
L~S=
___
x-v CURRENT
J_CORESWITCHE
Bias current is controlled by jumper changes on the G236 module.
There are three such jumpers and each has a varying effect on the
stack currents. JUMPER EFFECT:
Maximum effect to least effect: W5,W7,W6.
2)
a)
All jumpers in = minimum stack current.
All jumpers out = maximum stack current.
b)
Least significant change (W6)
c)
Bias reference voltage is measured on the G236 between AK2
and AA2. It is important that AA2 reference be on the same
module.
d)
The bias reference voltage is nominally set for 340 mV at 25
degrees Centigrade. (7r F). (365 mV for the G235)
e)
If the memory box is hotter, make the bias voltage lower by 1 mV
per degree C. (1 0 C. equals approximately 1.8 0 F.)
f)
The stack should be idle when checking bias voltage levels.
g)
Higher bias currents and higher tem peratures cause the coresto
switch faster. (Affects Strobe Timing.)
= 14 mA = 7 mV.
Strobe timing affects the lead time occurance of the strobe window.
(End time is fixed.) Output of the memory core during the window
will be interpreted as a "1" if it meets threshold requirements.
Strobe timing is controlled by jumper changes on the G236 module.
There are four such jumpers that affect the strobe timing.
JUMPER EFFECT:
Maximum effect to least effect: W1, W4, W3, W2.
(G235 = W2, W1, W4, W3.)
141
a)
All jumpers in = earliest strobe.
All jumpers out = latest strobe.
b)
The least significant change = 3 nSec.
c)
Range = 300 to 350 nSec. MJ11-B. (225 to 275 nSec. MJ11-A)
DRVA SSO L - - - - " - - - - - - '
G235/6 CN2
(Values measured
from Read Early.)
C13J1
C)
The core output voltage is an analog voltage; to digitize the output it is
compared to a treshold standard voltage. This voltage is normally
constant.
Threshold margining theory maintains that the quality of the parameters
affected by the adjustable components can be monitored and optimized
by varying the threshold and modifying the bias and strobe jumpers to
expand failure limits.
Normally, the threshold inputto the sense amps is a constant 1.7 mV level
produced on the G116 module. For margining purposes, we can manipulate this voltage by connecting a test potentiometer as follows:
Backplane pin A2 (+ 5V)
1Kohm
FR10fG116
200 mV of noise is OK.
Ground
D)
The diagnostic used to check the failure limits is EMKA in the Field
Service Mode:
1)
2)
3)
4)
Control F
Command 5
Bank = Address/16K (100000)
Margin variations:
SWR = 4000 = No margins
SWR = 0 = All Margins
Note: When a test failure occurs, the test must be restarted since the
memory control register 17777750 gets zeroed. Margin control occurs in bits 1 thru 3 of this register.
142
E)
Procedure for accomplishing memory tuning.
1)
Adjust the +5V, -5V, and +20V to 5% of spec.
2)
Adjust the bias voltage for 340 mV nominal. (365 mV for G235.)
3)
Connect the Vth potentiometer and adjust to 1.7V.
4)
Start the diagnostic with margin
o.
5)
Margin Vth toward 1.0v, until it fails and record the voltage.
6)
Restart the diagnostic (margin 0), and margin the Vth toward 2.5v,
until it fails and record the voltage.
7)
Analyze the failure limits and modify the diagnostic selection to
improve the failure limits.
FAILED LOW VTH
Strobe too early
G116 Bad
Bias too high
FAILED HIGH VTH
Strobe too late
Bad G116
Bias too low
FAILED BOTH VTH DIRECTIONS
Bias too high
Bad G116
8)
Modify jumpers dependent on the results of running the affect strobe
requirements.
9)
Return to steps 4, 5, and 6; retest to final criteria. If unsuccessful,
reperform steps 7, 8, and 9.
FINAL CRITERIA:
Margin = 0, Vth from 1.0v to 2.5v
= all, Vth from 1.3v to 2.3v
Note: If the margins are tightened further, ie .. 8v to 2.6v, a large trade
off of G116 modules will occur. (50% D.O.A.)
BIAS JUMPERS:
(In = 1; Out = 0.)
W7
W6
W5
o
o
o
o
o
o
o
1
1
o
o
1
1
1
o
1
o
1
o
1
1
1
1
1
STROBE JUMPERS:
...... G236 Module and G235 Module
Highest current
Lowest current
(In = 1; Out = 0.)
143
W4
W1
W3
W4
W2
W3
W1
W2
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
....... G236 Module
....... G235 Module
Latest Strobe
Earliest Strobe
Note: When ever you remove a module to change a jumper, be sure
to allow 5 minutes warm-up before proceeding with tests.
11170 CPU TIMING MARGINS PROCEDURE
Perform the timing margin procedure as follows:
a)
Connect a jumper from F13J1 to GND (E21T1), or install the PDP-11/70
CPU maintenance card and switch to RC clock.
b)
Set up oscilloscope as follows:
1 V/cm, 0.1JLSec time base
Sync: Channel 1, Internal
c)
Halt the processor, and, while monitoring pin D13T2 with Channel 1,
adjust R162 on the M8139 module (Slot 13) so that a slow margin of 250 nS
from leading edge to leading edge is set.
d)
Run one pass of the PDP-11/70 Instruction Exerciser
(MAINDEC-11-DEQKC).
1)
2)
3)
Start at address 200; select applicable devices.
Run one pass.
If errors occur, correct the malfunction and rerun the test.
e)
Halt the processor, and, while monitoring pin D13T2 with Channel 1,
adjust potentiometer R162 on the M8139 module (Slot 13) so that a fast
margin of 140 nS from leading edge to leading edge is set.
f)
Repeat step d) from above.
g)
Halt the processor, and, while monitoring pin D13T2 with Channel 1,
adjust R162 on the M8139 module (Slot 13) for normal timing of 150 nS
from leading edge to leading edge.
h)
Disconnect the jumper from F13J1 and E21T1 (GND).
Proceed with normal acceptance testing.
144
CPU VOL TAGlE MARGINS
All CPU and RH70 logic should run errorfree when the 5V power regulator is in
the 4. 75V to 5.25V range. Sometimes intermittent problems can be made solid
when setting the +5 regulator to it's hi and low extremes.
Procedure
1)
2)
3)
4)
Set all +5V regulators (CPU and used RH70) to 4.75V. Use chart on
page 26.
Run EQKC for half an hour. Then DECX for half an hour (exercise all
RH70's).
If errors occur, readjust regulators one at a time until problem disappears.
By using chart on page 26, find bad module.
If no errors, repeat above procedure, but adjust to 5.25 in step 1.
Good Luck!!
DATA PATH
CHEC~(
1)
Assure memory location 0 is good.
Deposit all ones
Examine all ones
Deposit all zeros
Examine all zeros
2)
Deposit known pattern in location O.
Load address 000000
Deposit 070707
3)
Read location 0 via Unibus Map.
Load address 17000000
Examine
You should read 070707
If data differs, one of the data or address paths is bad. See diagram below.
4)
Reverse the procedure, i.e. deposit known pattern in location 17000000
and examine location 000000. Again the data should be the same.
145
MEMORY MANAGEMENT
CPU
UNIBUS
AMX
I
I
I
I
BR
I
I
I
__
•
~
1 .
I
_____ J
I
,
I
UNIBUS
MAP
I
I
- --- ___ .I
I
CACHE
I
I
I
I
ADDRESS 000000
DATA PATH =_. _. _. (RED)
ADDRESS PATH =-. -. - . (BLK)
ADDRESS 17000000
DATA PATH =---- (RED)
ADDRESS PATH = ---- (BLK)
MEMORY
CUSTOMER CRASH/HALT SHEET
STANDARD FRONT PANEL
If your system halts please collect the following information prior to restarting
your system.
1.
Without touching anything please record which lights are on using the
attached sheet.
2.
Press the halt key down.
3.
Set the switches for the ADDRESS (see table) then press LOAD AD DRS.
The contents of the switches will now be in the address lights. Now press
EXAM and record the condition of the data lights in the table. If you
encounter any problems with this procedure please contact your local
Field Service for assistance.
146
SWITCHES SET
All up except 0,3
ADDRESS/PROCEDURE
DATA LIGHTS
17777766/LOAD ADDRS
Press EXAM
Press EXAM again
Press EXAM again
Press EXAM again
Press EXAM again
All up except 0,2,7
17777572/LOAD ADDRS
Press EXAM
Press EXAM again
Press EXAM again
All up except 0,4,5,7,9,11
17772516/LOAD ADDRS
All up except 0,1,2,3,4
17777740/LOAD AD DRS
Press EXAM
Press EXAM
Press EXAM again
Press EXAM agai n
Press EXAM again
Press EXAM again
Press EXAM again
All up except 0,1,2,3,4,5,9
17776700/LOAD ADDRS
Press EXAM
If your system has MK11 memory (MOS) please do the following as before.
SWITCHES SET
ADDRESS/PROCEDURE
All up except 0,3,4
1777746/LOAD ADDRS
All down except 2,3
14IDEP
All up except 0,1,2,3,4,6,
8,9,10,11
17770200/LOAD ADDRS
All down except 12,13,14,15
170000/DEP
All down except 0,1,2,3,4,5
77/DEP
All up except 0,4,5,7,9,11
17772516/LOAD ADDRS
All down except 5
40/DEP
All down except 6,10,18,19,
20,21
17002100/LOAD ADDRS
Press EXAM
Press EXAM again
147
DATA LIGHTS
PAR
DDDDcIDDODDDD
PDP-11/70
0.
X
ADDRESSING
ADDRS
X
X
X
X
D
DUSERD
DSUPERD
D
USER 1
DSUPER1~
OKERNELD
DKERNEL1W
D
CONSPHY
D
PROGPHY
D
DATA
PATHS
D
FPPI A D R S @
U
CPU
ADDRESS
DDDDDDDDDDDDDDDDDDDDDD
--'
.j:>.
CP
a
x
x
x
x==>
0
(g
DO DODDDDDDODDODDDO
DCK
POWER
OFF
PARITY
HIGH LOW
DATA
D
BUS
REGISTER
DISPLAY
DREGISTER
REMOTE CONSOLE r-PIONY PANEL
If you r system halts please collect the following information priorto restarting
it. Please type in the following in response to the "CON==" prompt. The system
will type out the information we need to help isolate the cause. The following
only shows what you should type in and not what the system responds with.
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
CONS==
I\P
T U OM 1 M 2M 3M
OA 1A 2A 3A 4A
5A 6A 7 AI\P
$601 ---':LF>
$5721
$25161
$401
177767001\0
177724401\0
-------->
$46/14
$0200/170000 77
>
$2516/40
>
-------->
170021001
II\E
V
Only if
You have
MK11 mos
memory.
You may now attempt a system restart. If you encounter any problems with this
procedure, please contact the local Field Service office for assistance.
$
NOTE: V01 consoles allow the use of the $ sign with a maximum of 2 trailing
digits and the V02 consoles allow any number of trailing digits. If you
have a V01 console (I\E at the CONS= prompt will print the version)
you must make the following changes to the above procedure:
V02
V01
$5721
$2516
$02001
177775721
17772516/
177702001
149
INTRODUCTION
Intermittent DBE's in MK11 memory can sometimes be very difficult to isolate.
There are two causes for DBE's of which the most common is a failing array
module. The other cause is bad data being written into an array. When this
problem occurs we get no indication until a subsequent read of that location.
We usually waste many hours and parts before resolving the problem. But
there is hope!!!
M K11 doesn't store parity bits but stores ECC check bits. Because of this it
must check the incoming data and parity for correct parity. If it detects a parity
error it inverts four of the check bits and then writes the data and bad check
bits into the array. This will cause a DBE when the location is read.
With a Logic Analyzer we can trigger when it is writing the inverted check bits
and use this to determine where the bad data was coming from. The following
setup is for the K100D logic analyzer.
SIGNAL NAME
PIN
PRINTS
ANALYZER CHANNEL
A11 M1
A11N2
*
CBA5
CBA5
CBB5
F
E
D
D17L 1
D17K1
D17N1
F21 K1
F21K2
F21E2
F21C1
CCBB
CCBB
CCBC
CDPH
CDPH
CDPH
CDPH
6
5
IN MK11:
CAS TIM L
WR TIM L
WRITE PAR ERR H
IN 1170:
AMX SO H
AMXS1H
DONE(1) H
CTRLA REO
CTRLB REO
CTRLC REO
CTRLD REO
L
L
L
L
4
3
2
1
0
* CBB5 WRITE PAR ERR H doesn't come to a backplane pin so you can either
hook up to the chip (E92-12 on M8161 right hand) or run a wire to spare pin
D10V1 and use it. This wire must be removed when you resolve the problem
because if someone replaces that board and returns it for repair the branch
will not get credit for the module!
TRIGGER
Set up the trigger to combinational on channels F,E,D. ie:
Trigger (C) (T) FED
o
0
1
C
x
B
x
A
x
9
x
8
x
7
x
654
x x x
320
x x x x
WHAT TO LOOle FOP, U= IT TP,IGGEP,S
1)
The logic analyzer is set up to trigger when CAS TI M Land WR TI M L both
go low at the same time WRITE PAR ERR H is high. This is the point we are
writing the inverted check bits into the memory chips. In other words a
WRITE PARITY ERROR has occurred which will result in a DBE when we
read that location.
150
2)
Channels C and B are set up to identify who was using cache at the time.
Use the following table to determine the source of the bad data.
AMX SO H (e)
AMX S1 H (8)
o
o
o
eAeHEPORT
CPU
RH70
PWR UP
MAP (UNIBUS)
1
1
o
1
1
3)
Channel A indicates completion of cache cycles whether it was a Hit in
Cache or a main memory cycle.
4)
Channels 9,8,7 and 6 will indicate which RH70 (A thru D) was accessing
Cache if AMX 0+1 show the RH70 port into cache was selected.
5)
Now you need a couple of Write Parity Errors triggers on the analyzer to
determine where to start looking for the cause of the bad data. The logic
analyzer is set up to trigger only if a Write Parity Error occurs on Control 0
side (addresses ending in 0 or 2).lf you get a DBE in Control 1 (addresses
ending in 4 or 6) the analyzer will not trigger. If the problem is a Write
Parity Error, the chances of it happening in both sides are high. If your
DBE's only occur on one side and it's not an Array, you should suspect the
M8161 on the failing side or the MK11 backplane.
6)
Use the following tables to determine where to start with in isolating the
source of the bad data.
POSSIBLE CAUSES IF MORE THAN ONE PORT:
1.
2.
3.
4.
5.
M8145 Cache data path
Main Memory Bus data cables
M8159 Data Buffer
M8161 Control BO/1
MK11 Backplane
POSSIBLE CAUSES IF ONLY RH70 PORT:
1.
2.
3.
M8150 in selected RH70
M8145 Cache Data Path
CPU Backplane
POSSIBLE CAUSES IF ONLY MAP PORT:
1.
2.
3.
4.
5.
M8141 Unibus Map
M8145 Cache Data Path
Any DMA Unibus Device
Unibus
CPU Backplane
POSSIBLE CAUSES IF ONLY CPU PORT:
**
1.
Follow steps in ANY PORT first
2.
3.
4.
M8134 Processor Data Path
M8145 Cache Data Path
CPU Backplane
** Since the CPU port uses Cache much much morethan the MAPorthe
RH70, two Analyzer triggers are not conclusive enough to rule out it
happening on ANY PORT. The problem is more likely to be between
Cache and Main Memory, so start looking there first.
151
INTRODUCTION
1170 systems that hang in the pause state can become real headaches for
everyone, especially when the obvious logic has been swapped out, because
the problem could be almost anywhere in the system. If a logic analyzer could
be triggered at the time of the pause, the signal that put the system in the pause
state could be seen, and as a result, we could target in on a specific area within
the system. Since all system activities prior to the pause hang is quite normal, it
is almost impossible to trigger most logic analyzersat the time of the hang. For
this reason, I have put a 10 micro-second one-shot circuit on the M8142 to
provide a trigger for the logic analyzer if any pause exceeds the 10 microsecond time frame (no normal pause will). The circuit is as follows:
The input to the one-shot is brought from the TMC module pin 11AJ1 (I NO
PAUSE H) via a backplane jumper to the M8142 unused pin 17EB1. The output
of the one-shot, which I have called "Pause Timeout L", is brought to another
M8142 unused pin 17EA 1 for analyzer hook-up. The signal at pin 17EA 1 will go
high if any pause exceeds 10 micro-seconds. The following pages state the
logic analyzer setup forthe various pause cycles (the analyzer in this case is a
K01 00). The analyzer is set up as events happen, starting with Channel F. A
detailed description of the events that happen on the analyzer then follows.
When the analyzer triggers, by following the description, along with what you
see on the analyzer, you should be able to find the signal that put the system in
the pause hang.
Trigger: Trigger on "Pause Ti meout H" on pi n 17EA 1.
* Warning: The modification of the M8142 should be done only on a module
owned by field service and used only when troubleshooting pause
hangs!!
Note: The above circuit could be built in a test box external to the CPU.
A)
CACHt:: PAUSE 75
1)
Set Logic Analyzer as follows:
152
2)
SIG NAME
PIN
BUSTH
CACHE ADRS H
PAUSE B H
CONTROL OK H
HIT EITHER l
START H
ADRS ACKN H
RDY ClK l
MEM SYNC H
MEM SYNC H
DONE H
PAUSE TIMEOUT H
Sequence of events:
17ET2
11CM1
14DK1
17DV2
17Fl2
18BE1
17DM2
17DF1
17FE2
13CJ2
17DN1
17EA1
PRINTS
CCBC
TMCF
SAPC
CCBC
CCBC
ADMl
CCBE
CCBE
CCBC
TIGA
CCBC
****
ANAL CHANNEL
F
E
D
C
B
A
9
8
7
*
6
5
1)
A data transfer is completed in two Rom cycles; a Bus Start
Cycle, which is used to initialize memory management and
cache (in case of a cache address), and a Pause Cycle, which will
do the actual data transfer.
During the Bus Start Rom Cycle, "Bust H" will be asserted and
will be sent to memory management to start relocation and
address decoding, and also to cache to start cache timing (in
case of cache address). In this example, memory management
will decode a cache address and "Cache Adrs H"will be asserted.
2)
When the CPU leaves the bus start cycle and enters the pause
cycle, "Bust H" will be negated and "Pause B H" will be asserted.
3)
With both "Pause B H" and "Cache Address H" asserted "Control
Ok H" will be asserted (TMCE) and will be sentto cache to start a
data transfer.
4)
If dOing a read and a hit is detected, then "Hit Either l" is asserted
and no main memory cycle is required. "Mem Sync H" will be
generated with both "Control Ok H" and "Hit Either l" asserted.
"Mem Sync H" will be sent to the CPU to restart the timing and
clock the data into the CPU BR register.
4A) If a write operation is specified when "Control Ok H" is
received in cache, "S,tart H" is asserted and sent down the
main memory bus to start an MJ11 or an MK11 data cycle.
Once the MJ or the MK has completed the cycle, it sends
"Adrs Ackn H" to cache. When cache receives "Adrs Ackn
H", it generates "Mem Sync H" and sends it to the CPU to
restart the timing.
4B) If a main memory read cycle (Read Miss) is specified when
cache receives "Control Ok H", "Start H" will be asserted
and an MJ or an MK read cycle will be started. Once the MJ
or MK has started it's timing, it will assert "Adrs Ackn H"
which is sent to cache. When the read cycle is completed,
the MJ or the MK will generate "Data Rdy H". With both
"Adrs Ackn H" and "Data Rdy H" asserted in cache, "Mem
Sync H" is generated and sent to the CPU to restart the
timing and clock the data in the CPU BR register.
5)
"Done H" will then be asserted in cache to place cache in it's idle
mode.
The data transfer is now over and the CPU moves to it's next Rom
cycle.
153
•
3)
Analyzer Trigger:
Trigger on "Pause Timeout H" on pin 17EA1. The analyzer will trigger
if a cache pause is longer than 10 micro-seconds.
Set time to 10-50 nSec.
13)
UNIBUS ADDRESS PAUSE T2
1)
Set Logic Analyzer as follows:
SIG NAME
PIN
PRINTS
BUSTH
17ET2
CCBC
PAUSE B H
14DK1
SAPC
UNIBUS ADRS H
12AM2
UBCA
PSEUDO T3 H
TIGA
13FC1
BUS NPR L
12DR1
UBCD
PROC NPG H
12FD2
UBCD
BUS SACK L
12DJ1
UBCD
BUS SSYN L
12ER2
UBCB
BUS BBSY L
12FK2
UBCA
CPBSY B H
12FL1
UBCA
BUS MSYN L
12FL2
UBCA
**Waiting for SSYN, see Channel 8.
TIG RESTART H
12AM1
UBCB
TIG RESTART H
13CD1
TIGA
PAUSE TIMEOUT H
17EA1
****
2)
3)
ANAL CHANNEL
F
E
D
C
B
A
9
8
7
6
5
4
*
3
Sequence of events:
1)
As mentioned previously, during the Bus Start Rom Cycle, "Bust
H" is sent to memory management to start relocation and
address decode. In this example, a unibus address will be
decoded from memory management and "Unibus Adrs H" will be
asserted and sent to the Unibus Control Module "UBC".
2)
When the processor leaves the bus start rom cycle and enter the
pause cycle, "Bust H" will be negated and "Pause B H" will be
asserted.
3)
When "Pause B H" is asserted "Pseudo T3" will be generated.
Pseudo T3 is only generated in a Pause Rom Cycle.
4)
"Pseudo T3" will be sent to the Unibus Control Module "UBC"
and if "Unibus Adrs H" is asserted, and the following conditions
are not true; NPR-NPG-SACK-SSYN-BBSY; "CPBSY B H" will
be asserted.
5)
"CPBSY B H" will generate "BUS MSYN L".
6)
When the unibus control module receives "SSYN L" from the
unibus, "TIG Restart H" will be generated and sent to the TIG
module to restart the CPU timing and clock the data into the CPU
BR register (if dati).
The data transfer is over and the CPU moves on to it's next rom
cycle.
Analyzer Trigger:
Once again trigger on "Pause Timeout H" on pin 17EA1. The analyzer will trigger if a unibus address pause at T2 is longer than 10
micro-seconds. Set time to 10-50 nanoSec.
154
C) IN7R PAUSE 72
1)
Set Logic Analyzer as follows:
SIG NAME
PIN
PRINTS
,
EXT BRQ H
UBCD
12DD1
INTR PAUSE H
12DD2
UBCD
TIGE TS2 L
12ES1
UBCD
PROC NPG H
12FD2
UBCD
BUS NPR L
12DR1
UBCD
BUS SACK L
12DJ1
UBCD
PROC BG4 H
12ET2
UBCD
PROC BG5 H
12EM2
UBCD
PROC BG6 H
12EP2
UBCD
PROC BG7 H
12ES2
UBCD
**Waiting for SACK, see Channel A.
BUS BBSY L
12FK2
UBCA
BUS INTR L
12DT2
UBCC
TIG RESTART H
13CD1
TIGA
TIGE TS3 L
12DP2
UBCB
BUS SSYN L
12ER2
UBCB
PAUSE TIMEOUT H
17EA1
****
2)
ANAL CHANNEL
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Sequence of events:
1)
In between instruction execution, the CPU will do a BR Strobe
to see if any bus request are present. If a request is present, the
CPU will not fetch the next instruction but will go to an interrupt
micro-code routine to get a vector address on the unibus. At the
time of the BR Strobe, if any BR are present, then "EXT BRQ H"
will be asserted.
2)
The CPU will go in an INTR Pause. "INTR Pause H" will be
asserted and the timing will stop at T2.
3)
When "TIGE TS2 L" is generated during the pause cycle, and
with both "EXT BRQ H" and "Intr Pause H" asserted, and the
following conditions not true; NPG-NPR-SACK; the USC
module will assert "PROC BG* H" on the unibus (*=4,5,6, or?).
4)
The interrupting device will assert "Bus Sack L" on the unibus.
When the UBC module receives "Bus Sack L", it will negate
"PROC BG* H" and disable the sack timeout circuit.
5)
When the unibus becomes available (BBSY negated) the interrupting device will take the bus by asserting "BUS BBSY L" and
negating "BUS SACK L".
6)
The interrupting device will then put it's vector on the unibus
data lines and assert "BUS INTR L".
7)
When the Unibus Control Module (UBC) receives "BUS INTR
L", it will generate "TIG Restart H", which will be sentto the TIG
module to restart the timing and clock the vector into the CPU
BR register.
8)
When the CPU timing restarts, "TIGE TS3 L" will be generated.
9)
When the UBC module receives "TIGE TS3 L", it will generate
"BUS SSYN L" out on the unibus.
155
10)
3)
The device will then negate "BUS INTR L", "BUS BBSY L", and
also remove it's vector from the unibus data lines. The transaction is over and the CPU now fetches the next instruction.
Analyzer Trigger:
Again trigger on "Pause Timeout H" on pin 17EA1. The analyzer will
trigger if an I NTR Pause is longer than 10 micro-seconds.
Set time to 10-50 nano-Sec.
TROUBLESHOOTING RED ZONE ABORT,S
A)
In between program instructions (Le. before fetching the next instruction) the micro-code will do a "BRQ Strobe" to see if there are any
pending internal or external break requests. If a request exists, the microcode will branch away from the instruction fetch rom cycle and go into a
break request rom cycle, in order to obtain a vector that will be used as a
new PC (software subroutine to handle the request).
Internal Requests Are:
1)
2)
I nternal Traps.
Memory Management traps or parity traps for example.
Program Interrupt Requests (PIRQ) which are software controlled.
External Requests Are:
1)
Unibus Requests.
BR4 for example.
Vectors forthe internal requests are obtained internally. That is, the CPU
itself provides the vector (see DAPE). The CPU must go out onto the
unibus to obtain a vector when an external request exists (device vectors), and therefore must go into an INTR Pause Cycle.
As stated previously, before fetching a new instruction with the updated
PC, a BRQ Strobe is done, and if a request exists, the instruction is not
fetched and the updated PC is pushed into the stack so that we can return
to it after the request has been serviced. If a request exists while in the
request subroutine (there is a BRQ Strobe in between all instructions in
the subroutine) then that PC is pushed on the stack. If we cannot get out
of the subroutine because of continuous requests, then we will continuously push onto the stack, and decrement it to the red zone.
B)
Here is a list of the internal and external requests, their priority and their
vector assignment:
156
1
2
3
4
5
6
--
CONSOLE FLAG
PARITY TRAP
SEG MEM MANAGEMENT TRAP
STACK LIMIT YELLOW
POWER FAIL
FP EXEPTION TRAP
-
CP LEVEL 4
13 PIRQ 4 (PIR 12)
14 BUS REQUEST 4
114
250
4
24
244
16 PIRQ 2 (PIR 10)
240
INTR
C)
240
I
240
I
240
CP LEVEL 1
17 PIRQ 1 (PIR 09)
240
INTR
CP LEVEL 0
18 T BIT (PS 04) AND NOT RRT & Rn NOT
LOCKED OUT BY PRGC STATUS LEVELS
BUT SERVICED LAST
CP LEVEL 5
11 PIRQ 5 (PIR 13)
12 BUS REQUEST 5
I
CP LEVEL 2
CP LEVEL 6
9 PIRQ 6 (pIR 14)
10 BUS REQUEST 6
240
INTR
CP LEVEL 3
15 PIRQ3(PIR11)
CP LEVEL 7
7 PIRQ 7 (PIR 15)
8 BUS REQUEST 7
I
240
INTR
I
14
By triggering the logic analyzer with "TMCD Yellow Trap H" we should
see which one of the above listed request was continuously asserted and
caused the red zone.
Analyzer Setup:
Analyzer Setup Yellow/Red Zone Violations:
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
TRIGGER
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
11AD2
11 ER1
11ED1
11 EE2
11EL1
11EU1
11DJ1
11EN1
11FA1
11DC1
11AN1
11 DF2
11CR2
11CL2
11EF1
YELLOW TRAP H
HONOR BR 7 L
HONOR BR 6 L
HONOR BR 5 L
HONORBR4L
PARITYTRAPH
MEMMNGTTRAPL
PWRFAIL(1)H
FPTRAPL
UNIBUS TIMEOUT B L
ODD AD DR ERR L
KT ABORT FLG L
PEABORTL
NOT CACHE ADDR H
UNIBUSADDRL
NEXM L
Set timing to 1 mSec.
Trigger Setup:
Trigger (C) (T) FED C
B A 9 8
7 6 5 4
3 2
x x x
x x x x
x x x x
x x x
Analyzer -
GNDS
CLK
Input Mode
Threshold
Delay
Any pin with a black wire on it
10ns for ali except UB TOUT + BR
Latch
TTL
500 Clks
157
= 10ms
AEDZONETESTP~OGAAMS
The following programs can be used to verify the logic analyzer setup for a
particular RED ZONE. Use a analyzer clock of 1Ons for all except the "BR" and
"UB TIMEOUT" RED ZONES which use a clock of 10ms.
1. Memory Management Abort Red Zone Program
The program executes from PARO while trying to access location thru
PAR1 (physical memory address 20000) which has been setup to abort all
access.
1000/12737/0/772340
1006/12737/77406/772300
1014/12737/200/772342
1022/12737/77400/772302
1030/12737/1/777572
1036/137/20000
MOV #0, PARO
MOV #77406, PDRO
MOV #200, PAR1
MOV #77400, PDR1
MOV#1, MMRO
JMP@20000
250/1036
17777706/600
4/1036
MMU vector service routine
Stack pointer
Restart after yellow zone
200001777
BR (Should not set here)
Result is MMRO = 100003, CPER = 14
2. Odd Address Error Red Zone Program
The following program will try and access an odd address then try
again and again until Red Zone.
1000/0127371100/2001
1006/137/1000
MOV #100, 2001
JMP 1000
17777706/600
Set stack pointer = 600
4/1006
6/0
Odd adrs error service
PSW
Result is CPER
= 114
158
RED ZONE TEST PROGRAMS (continued)
3. BR6 Red Zone Program
The following program will turn on interrupts from the KW11 and never
service them which will result in a Red Zone.
1000/777
1002/012737/1001777546
1010137/1000
BR
MOV #100,777546
JMP 1000
17777706/600
Set stack pointer
100/1000
102/0
KWW11 Vector service
PSW
4/1000
6/0
Restart after yellow zone
PSW
Result is CPER
(KW11 IE)
= 600
= 14
4. Unibus Timeout Red Zone Program
The following program will try and access a non-existant device on the
unibus again and again until Red Zone.
10001013737/777400/2000
1006/137/1000
MOV 777400, 2000
JMP 1000
17777706/600
Set stack pointer
4/1006
6/0
UB Timeout Service
PSW
Result is CPER
= 34
159
(RKDS->2000)
= 600
RED ZONE TEST PROGRAMS (concluded)
5. NXM Red Zone Program
The following program causes NXM aborts which never get serviced
resulting in a Red Zone.
1000/12737/0/772340
1006/12737177 406/772300
1014/12737/60000/772342
1022/12737/77406/772302
1030/12737/20/772516
1036/12737/11777572
1044/12737/4/20000
1052/774
MOV #0, PARO
MOV #77406, PDRO
MOV #60000, PAR1
MOV #77406, PDR1
MOV #20, MMR3
MOV #1, MMRO
MOV #4, 20000
BR Back
17777706/600
Set SP
4/1044
6/0
NXM Service
PSW
Result is CPER = 54
160
=600
UNIBUS CAUSED ~ED ZONES AND UNIBUS
TIMEOLlJT T~OUBLESHOOTING
When a RED ZONE occurs as a result of a multiple BRs or UNIBUS TIMEOUTs
it can be difficult to isolate to a device without knowing what was happening
on the unibus. If we could see the vector in the case of a BR or the address in
the case of a UNIBUS TIMEOUT the solution would be simple. The Unibus
Trace Analyzer (UTA) can be used to help get this information. Also if you are
troubleshooting an intermittant UNIBUS TIMEOUT problem this technique
will be very useful.
In order to catch the state of the unibus prior to the RED ZONE or UNIBUS
TIMEOUT we need to add a couple of wires to the UTA to provide it with a
latching external input. The circuit below will stop the UTA from recording any
further Unibus activity once the external input goes high (or low). It will keep
the UTA locked with the first occurrence of the trigger even if the external
input toggles again.
E24·11 (+3V)
EXTL
10
PRE
~1
12 0
EXTH
1 E17
0
2
BA1
E26
7474
10
~
Q 9
E6
'P
Q8
11 C
E27-2
CLR
13
E26-1
CHANGE LIST
1.
2.
3.
4.
5.
6.
7.
8.
9.
Add
Add
Add
Add
Add
Add
Add
Add
Add
wire E26-8
wi re E26-8
wi re E26-10
wire E26-11
wire E26-12
wire E26-13
wire E6 -10
wire E17-1
wire E17-2
to
to
to
to
to
to
to
to
to
E27-2
E6 -9
E24-11
E6 -8
E26-10
E26-1
E17-2
module pin BA1
module pin BB1
161
•
UNi8US CAI!JSED PlED ZONES AND I!JNI8US
uu\'~EtOl!Ju TP'OU8lES~'JOOTING
*** With this addition if you are using the module in any of it's other recording
modes the EXT H should be connected to a ground on the backplane to
prevent false triggering.
1. Catching Unibus caused RED ZONES on the PDP1170
Install the modified UTA in the first Unibus SPC slot so all devices on the
Unibus are covered. Run the diagnostic (G5445C.BI N) with the Enable SW
in the down position. If all checks out ok hookup the EXT H input to pin
A 11 D2, YELLOW TRAP H. Then set the Enable SW down and load the CSR
address (17776570) and deposit 100000 (inits the module). Atthis point it is
a good idea to verify every thing is working with the following program. If
everything works, init the module again and boot the customer's software.
TEST PROGRAM:
The following program will turn on interrupts from the KW11 L and never
service them which will result in a RED ZONE.
10001777
1002/012737/1001777546
1010/137/1000
BR
MOV #100,777546
JMP 1000
17777706/600
SP = 600
100/1000
102/0
KW11 Vector Service
PSW
4/1000
6/0
Restart after a RED ZONE
PSW
(KW11 IE)
The result when you halt the system is CPU ERROR REGISTER = 14.
If you then run BUSDMP.BIN to examine the UTA memory you will
see it recorded a BR6 and a VECTOR = 100 prior to stopping the
recording. Bingo, we know 'who done it'.
162
Here is an example of what the BUSDMP looks like for the test program.
You will notice that 33 decimal interrupts occured at vector 100. This would
result in 66 decimal (102 octal) pushes onto the Kernal stack (PC and PSW
are pushed). The 102 octal pushes converts to 204 octal word addresses.
Since our Kernal stack started at 600, we went into yellow zone (600204 = 374) and stopped the UTA from recording .
.R BUSDMP
BUSDMP.BIN
UNIBUS CRASH DUMP ANALYZER PROGRAM
IS THE MODULE SET FOR THE STANDARD ADDRESS? YIN Y
RESTART ADDRESS IS 2000
THE MODULE STORES 2048 (10) UNIBUS SAMPLES.
THE LAST SAMPLE WAS STORED AT LOCATION 00033(10)
TYPE HLP FOR COMMAND SUMMARY
>DMP
FM>O
TO>33
SAMPLE
ADDRESS
DATA
MISC
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
777546
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000100
000100
000100
000100
000100
000100
000100
000100
000100
000100
000100
C1 MSYN INIT BBSY
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
INTR BR6 SACK BG6
BBSY
BBSY
BBSY
BBSY
BBSY
BBSY
BBSY
BBSY
BBSY
BBSY
00030
00031
00032
00033
000000
000000
000000
000000
000100
000100
000100
000100
INTR
INTR
INTR
INTR
BBSY
BBSY
BBSY
BBSY
162A
BR6
BR6
BR6
BR6
SACK
SACK
SACK
SACK
BG6
BG6
BG6
BG6
UNIBUS CAUSED RED ZONES AND UNIBUS
TIMEOUT TROUGLESHOOTING
2. Catching UNIBUS TIMEOUTS on the PDP1170
Install the modified UTA in the first Unibus SPC slot so all devices on the
Unibus are covered. Run the diagnostic (G5445C.BIN) with the Enable SW
in the down position. If all checks out ok hookup the EXT H input to pin
B11A1, UNIBUS TIMEOUT H. Then set the Enable SW down and load the
CSR address (17776570) and deposit 100000 (inits the module). At this
point it is a good idea to verify everything is working with the following
program. If everything works, bring up the customer's software and then
use online ODT or halt the system and init the module again (continue the
system if you halted it). You have to do it in that order because most
operating systems size the Unibus for devices on startup and will set a
UNIBUS TIMEOUT.
TEST PROGRAM:
The following program will try and access an RK05's CSR which will result
in a UNIBUS TIMEOUT. If your system has an RK05, pick an address of
some device you do not have and substitute it in location 1004.
1000/012737/5/777404
1006/0
MOV #5, RKCS
HLT
4/6
6/0
UB TIMEOUT Trap Catcher
HLT
The result when the system halts is the CPU ERROR REGISTER =
20. If you then run BUSDMP.BIN to examine the UTA memory you
will see it recorded a ADDRESS = 777404 (or the one you selected)
prior to stopping the recording. Bingo, we know 'who done it' .
••• Remember to INIT the module after the customer's system is up or
the UTA will trigger on system startup.
163
Here is what the BUSDMP printout will look like for the test program. You
will notice there is only 1 entry since the address sent ot the Unibus caused
a timeout and the UTA stopped recording.
NOTE: Since the UTA clocks the memory with MSYN on a DATO and
SSYN on a DATI if the Unibus Timeout occurs on a DATI the
address causing the Timeout will not be stored (no SSYN). This
means you have a 50/50 chance of getting the bad address .
.R BUSDMP
BUSDMP.BIN
UNIBUS CRASH DUMP ANALYZER PROGRAM
IS THE MODULE SET FOR THE STANDARD ADDRESS? YIN Y
RESTART ADDRESS IS 2000
THE MODULE STORES 2048 (10) UNIBUS SAMPLES.
THE LAST SAMPLE WAS STORED AT LOCATION 00000(10)
TYPE HLP FOR COMMAND SUMMARY
>DMP
FM>O
TO>O
SAMPLE
ADDRESS
DATA
MISC
00000
777404
000005
MSYN INIT BBSY
163A
Tr-lOlJI3LESt-~OOTING
MAIN MEMORV lilMEOUTS
Main Memory Timeouts are a result of a loss of communications between the
Main Memory and Cache. At the start of a memory cycle Cache sends the
ADDRESS and MAIN START to Memory and starts a 4us timer. Memory
decodes the address and responds with a MAIN ACK. If a signal is lost along
the way the Cache will timeout with the 4us one shot setting the Main Memory
Timeout if Cache was doing a CPU cycle (MSER bit 0 set), set the RH70
Timeout if Cache was doing an MBA cycle (RH70 CSR2 bit 11 set) or cause the
requesting Unibus Device to set it's NXM bit if cache was doing a MAP cycle.
The following analyzer setup can be used to isolate which signal was lost and
where for a Main Memory Timeout. To test this setup run a BR SELF
instruction with Cache off and ground CPU backplane pin A 18A1. This should
trigger the analyzer showing MAl N ACK was never received from memory but
memory sent it out.
Logic Analyzer Setup:
Module
Signal Name
Prints
Pin
Channel
M8142
CCBD CP TIMEOUT L
CCBD MBC TIMEOUT H
CCBD UB TIMEOUT L
CCBD
CCBD
CCBD
D17H2
C17V2
D17A1
F
E
D
M8143
CCBD START H
ADML ADRS ACK H
ADML
ADML
B18E1
A18A1
C
B
M8158
ABB9GO H
DBB21ACK L
ABB9
ABB3
D13U1
D13T2
1
0
M8147/8
MCTASTART H
MCTF lACK L
MeTA
MCTF
E87-3
E39-8
1
0
Trigger setup:
* Trigger (e) (F) FED
1 0 1 x
Analyzer
-
GNDS
-
CLK
Input Mode
Threshold
Delay
o
x
= MK11 = any T1
= CPU
or e2 pin
=any pin with black
wire on it
= 10ns
Latch
TTL
= 100clks
* Note: Trigger is setup for FALSE (F) so that anyone of the timeout signals
setting (Going LOW) will trigger the analyzer.
164
RSTS ERROR LOGGER
To run the RSTS Error Logger proceed as follows after logging in and answer
the questions presented. All of these questions may not appear depending on
what options are selected. The defaults are in <> and are accepted by typing a
'
$ RUN $ERRDIS
ERRDIS V9.1-05 RSTS V9.2-10 SYSTEM 1170
Input File ?
Output to ?
He[lp], Ba[d Blocks[. Su[mmary] of Fu[lI] Report ?
Specific Error Type ?
Starting Date ?
Starting Time ?
Ending Date ?
Ending Time ?
List Bad Blocks (Yes/No) ?
Zero Error File upon completion (Yes/No) ?
; note 1
;note 2
;note 3
;note 4
Notes:
1. This is the default account (may vary in different RSTS versions) and error
log file. You can also select ERRCRS.FIL which if it exists will contain the
error log buffer at the time of the system crash.
2. This can be any file specification, eg: LPO: for output to printer,
ERROR.RPT for a file, etc.
3. Specify ALL (default) or device mnemonic. Request a He[lp] report fora list
of mnemonics. You can also specify ALL/NOTAPE for everything but
magtape errors.
4. Date format
= dd-mm-yy and Time format = hh:mm (24 hour format).
RSTS-1
•
PoSTS
CrlAS~'l
DUMP ANALSVS
When RSTS is having a serious problem and it doesn't expect to recover it will
attempt to create [0, 1]CRASH.SYS on the system disk. If it is able to create this
file it will reboot to "OPTION". What it does from here depends on the state of
SWR bit O. If bit a is clear it will stay at "OPTION". If bit a is set or the SWR is
disabled it will attempt to come all the way up using the crash procedure in a
command file. This should run ANALYS on the crash and generate a report. If
the command procedure is not setup this way or the system didn't restart, you
can run ANALYS at any time on the last [0,1]CRASH.SYS file. This file is
overwritten on each crash.
To run ANALYS proceed as follows after logging in and answer the questions
presented. The defaults are in <> and are accepted by typing a '
$ RUN $ANALYS
ANALYS V9.0 RSTS V9.2-10 SYSTEM 1170
INPUT <[0,1]CRASH.SYS>?
OUTPUT ?
Crash error log filename<[0,3]ERRCRS.FIL>?
;note 1
;note 2
;note 3
Notes:
1. ANAL YS uses the currently installed monitor SIL for symbol references.
If the CRASH.SYS being analyzed is for a different monitor use the
/SIL:sil_ name switch on the input file.
2. The following switches apply to the output file spec:
/NARROW
/NOSTB
/NODUMP
Create an 80 column report
Omit the Symbol table printout
Omit the memory dump
3. If you enter /DET here it will cause ANAL YS to detach.
RSTS-2
FISTS CRASH DUMP ANALSVS
FISTS CRASH ERFIOR CODES
Code
Description
177777
Power Fail
177776
Trap 0 (Jump to 0)
177775
Continue from 52
177774
Software forced Crash
000041
Trap 4 (CPU error)
000042
Trap 10 (Illegal Instruction)
000043
Trap 250 (MMU abort)
000044
Red Zone, Kernal stack overflow
000046
Trap 114 (Memory system error)
o or other
Forced Dump
CRASH DUMP ENABLED?
To find out if crash dump is enabled RUN $UTI LlTY and type SNAP (for V9.x
type $DUMP/SYSTEM at the DCl prompt). This will attempt to create a
[0, 1]CRASH.SYS file of the current system state. If the function works, then
crash dump is enabled. If the function returns a "Can't find file or account"
error, then crash dump was NOT enabled at system startup or through
DEFAULT. In V9.x crash dump is always enabled unless there isn't enough
room on the disk for CRASH.SYS in which case RSTS prints an error message.
To re-enable crash dump, do the following:
1. Get to the OPTION: prompt of INIT.SYS by shutting down timesharing.
2. Execute the REFRESH option to create the CRASH.SYSfile (if it does NOT
already exist).
3. Finally, execute the DEFAULT option and answer YES to the crash dump
enabled question.
RSTS-3
P.STS
CP.lAS~·~
DUMP ANAlSVS
r-Or-lCiNG A CRASH DUMP
At times it is useful to force a crash dump to gather information on a RSTS/E
system. This can be used to get a dump when a system hangs. These all
require the system to be put into console mode. In order to do this, halt the
processor, either by the switch on the front panel or typing /\P H on the
console. After the commands are typed, you will need to proceed, which refers
to either switching the front panel switch back to the RUN position and
pressing the CONTINUE switch or typing the P console command.
1. Poke the clock. Load add ress 100 (which is the clock vector) and deposit a 1
into this location, then proceed.
2. Force a trap to 4. Examine the contents at location 4 and 6. Load the
contents from location 4 into the PC (address 17777707), and load the
contents of location 6 into the PSW (address 17777776), then proceed.
3. Force an odd address trap. Examine the contents of the PC (address
17777707) and deposit back into the PC it contents plus 1, then proceed.
RSTS will now do a crash dump and initiate a system reload/auto-restart if
crash dump is enabled and switch register bit 0 = 1 (Auto Restart bit). After
time-sharing is resumed, the standard diagnostic tools such as ANAL YS and
ERRDIS can be used to analyse the crash dump. When analyzing these
dumps, however, one should rememberthatthe reported error code (41) is no
longer valid since the dump was taken by forcing a trap through 4.
RSTS-4
ANAL VZING AS7S HAL 7S
When RSTS has a serious problem it attempts to create a crash file on the disk.
If it is unable to create or fully complete [O,1]CRASH.SYS or restart RSTS it
will halt at 1 of 6 locations. To identify which halt you are at you will need to
look at the memory locations around the halt. BECAREFUL, the halt address
the KY11 R gives you is VIRTUAL. You must insure you are examining the
correct memory locations. This can be done by relocating the virtual address
using KIPARx manually or on the KY11R by typing the following on the
console IMMEDIATELY following the halt, eg:
*H00033054/T4441 0
CONS= OA00377054AP
CONS=
;type a
;type a OA then AP, 377054 is the
; physical relocation of virtual 33054
If after examining the memory locations, the halt is not one listed here, you
may have just been transferred into hyperspace (incorrect relocation, memory
cleared or corrupted, etc.). Your best approach in this case is to find out where
you are and if the code you examined is what is supposed to be there. Another
CAUTION is always verify R7 matches the halt address. The KY11 R doesn't
always display the virtual PC on a halt but R7 is always correct.
Here are the 6 halts. Following this summary is a listing of the memory
locations around each halt. Once the halt is identified there is a detailed
description of each halt and how to troubleshoot it.
1. *H00000056/T44410
HLT54, Double PWR FAILS orT114's
2. *Hxxxxxxxx/T44410
C.HL T1, Unable to map Crash phase
3. * Hxxxxxxxx/T 44410
C.HL T2, Crashed while Crashing
4. *Hxxxxxxxx/T44410
REBOOT+72 Halt, Disk read error
5. *Hxxxxxxxx/T44410
WRILOW+106 Halt, Disk write error
6. * HOOOOOxxx/T 44410
TRAP CATCH ER Halt, Restart error
RSTS-5
ANALYZING RlSTS I-'JAL"fS
IDl::NTH::VING Tt-dl:: HALT
1. HLT54
This address is fixed and is the same on all RSTS systems. The pattern in
in memory is as follows:
00000052/000434
00000054/000000
00000056/000770
BR DODUMP
HALT
BR 10$
;do a crash dump
;halt
;do a system reload
2/3. C.HL T1, C.HL T2
The C.HL T1 and C.HL T2 addresses may vary from system to system and
to be sure thats where you actually halted examine your halt address +-6
locations and look for the following pattern:
xxxxxxx/OOOOOO
xxxxxxx/000776
xxxxxxx/OOOOOO
xxxxxxx/000776
C.HL T2: HALT
BR C. HLT2
C.HL T1 : HALT
BR C.HL T1
;double error halt
;no continue allowed
;crash not mapped halt
;no continue allowed
4. REBOOT+72
The REBOOT +72 halt add ress may vary from system to system and to be
sure thats where you actually halted examine your halt address +-6
locations and look for the following pattern:
xxxxxxxx/022737
xxxxxxxx/000240
xxxxxxxx/OOOOOO
xxxxxxxx/001402
xxxxxxxx/OOOOOO
xxxxxxxx/000741
CMP #NOP,@#O
;boot read in ok?
BEQ 10$
HALT
BR REBOOT
;yes, jump to boot
;no, halt REBOOT+72
;retry after halt
5. WRILOW+106
The WRILOW+106 halt addresses may vary from system to system and to
be sure thats where you actually halted examine your halt address +-6
locations and look for the following pattern:
xxxxxxxx/004767
xxxxxxxx/?
xxxxxxxx/103001
xxxxxxxx/OOOOOO
xxxxxxxx/000207
50$
JSR PC,B.READ
;go to dump writer
BCC 50$
HALT
RTS PC
;write error?
;yes, halt WRILOW+1 06
;no; return or continue
RSTS-6
ANALYZING RSTS HALTS
IDENTIFYING THE HALT (cont.)
6. TRAP CATCHER
The halt addresses for TRAP CATCHER halts are always the address of the
vector that caused the trap, interrupt or abort + 4. For example if the system
halted at 10 memory would look as follows:
00000004/000006
00000006/000000
00000010/000012
HALT
;TRAP 4 catcher, new PC
;TRAP 4 halt
;TRAP 10 catcher, new
PC
ANALYZING THE HALT
1. HLT54
If you halted at 56 you have either had a powerfail while servicing a
powerfail or a parity error while servicing a parity error. To determine which
it was look at the following physical memory locations:
00034/000054
00114/000054
You had a double powerfail!
You had a double parity error!
In the case of double parity errors the $40,$42,$44 and the MK11 CSR's will
still contain the failure information. A double powerful problem should be
troubleshot as any normal powerfail.
2. C.HLT1
If you halted at C.HL T1 this means RSTS was having problems mapping the
Crash phase and gave up. Before giving up it did however write the ERROR
CODE into a location called CRASAV+776. For RSTS VS.x and 9.x,
CRASAV is physical 24000. In this location will be the reason RSTS
attempted to crash (see table of ERROR CODES in RSTS CRASH DUMP
ANALSYS section).
Also be sure to look at the CPU error register ($66), MMRO ($572), Memory
error registers ($40, $42, $44) and the MK11 CSR's which may also contain
information about the crash.
RSTS-7
ANAL VZING PoSTS HALTS
ANAL VZING THE HALT (cont)
3. C.HLT2
A halt at C.HL T2 indicates we were in the process of crashing when another
fatal error occured. Unfortunately when this happens it usually always
means the error registers have been cleared. This happens because RSTS
issues a RESET instruction before it attempts to reboot. In any case it has
assembled all or part of the CRASH file in memory starting at location
CRASAV for 776 locations. Use an old Crash dump to get this address and
the addresses for LOWAD, HGHAD and MEMERR (for RSTS V8.x and 9.x,
CRASAV is physical 24000, but the locations were the memory registers are
saved vary from system to system). These locations will reflect the 1st crash
and the current registers ($40, $42, $44, $66, $572) should contain the
information on the second crash. Refer to the table on the layout of the
CRASAV, LOWAD, HGHAD and MEMERR area in memory.
4. REBOOT +72
A halt here indicates the system was in the process of doing a software
BOOT and an disk error occured. It tries to load the primary bootstrap off of
block a of the system disk and then checks physical memory location a to
insure it contains a NOP (240) instruction. If it doesn't, the system halts. If
you halted here you should check the SYSTEM DISK's REGISTERS for the
source of the problem. It is also useful to check the CRASAV, LOWAD,
HGHAD and MEMERR area of memory incase this boot was a reboot of
RSTS following a crash.
5. WRILOW+6
RSTS will halt here if a disk error occurs while trying to write the file
[0, 1]CRASH.SYS. If you halted here you should check the SYSTEM DISK's
REGISTERS for the source of the problem. It it also important to check the
CRASAV, LOWAD, HGHAD, MEMERR area of memory to find out why we
were crashing in the first place.
6. TRAP CATCHER
During the initial loading or reloading of RSTS the vector area of memory is
loaded up with trapcatchers. This prevents unexpected ABORTS, TRAPS
or INTERRUPTS from affecting the startup/restart. If you halt at a TRAP
CATCHER location the vector that caused the trap will tell you what to look
at. For example if I halted at 120, this would mean I had a TRAP 114. It would
then make sense to look at the memory system error registers for the cause
of the problem. It is also useful to check the CRASAV, LOWAD, HGHAD,
and MEMERR area of memory incase this boot was a reboot of RSTS
following a crash.
RSTS-8
ANAL VZING f-ISTS HALTS
RSTS V8.lC CRASH DUMP AREA IN MEMORV
Location
Contents
CRASAV + 0
2
4 .. 12
14 .. 22
24
26
30
32 .. 54
KISAR5
KDSAR5
Instruction Space -6(PC) to (PC)
Instruction Space 2(PC) to 8(PC)
CPU ID register
CPU error resister
PDP 11/60 MED data length
PDP 11/60 MED data (reserved for 10. words)
The following area is unassigned and must be at least 10. words long for stack
space.
56 .. 260
UNASSIGNED
These next two words may be at higher addresses depending on exclusion of
other conditional data below.
262
264
Complement of size of dumped monitor image
Size of dumped monitor/image
The following data is only present if the system has Unibus Mapping
Registers. If I and D space is not present this data will occupy slots 332 thru
524.
226
306
326
346
366
406
426
446
..
..
..
..
..
..
..
..
304
324
344
364
404
424
444
460
UMR's
UMR's
UMR's
UMR's
UMR's
UMR's
UMR's
UMR's
0-3
4-7
8-11
12-15
16-19
20-23
24-27
28-30
The following data is only present if the CPU's has I and D space.
462
466
472
476
502
506
512
516
..
..
..
..
..
..
..
..
464
470
474
500
504
510
514
520
KDSARO
KDSAR1
KDSAR2
KDSAR3
KDSAR4
KDSAR5
KDSAR6
KDSAR7
KDSDRO
KDSDR1
KDSDR2
KDSDR3
KDSDR4
KDSDR5
KDSDR6
KDSDR7
RSTS-9
•
ANALYZING PoSTS HALuS
Location
Contents
CRASAV + 522
524
526
530
MMR3
MMR1
MMR2
MMRO
532
542
552
562
572
602
612
622
..
..
..
..
..
..
..
..
540
550
560
570
600
610
620
630
UISARO
UISAR1
UISAR2
UISAR3
UISAR4
UISAR5
UISAR6
UISAR7
UISDRO
UISDR1
UISDR2
UISDR3
UISDR4
UISDR5
UISDR6
UISDR7
KISARO
KISAR1
KISAR2
KISAR3
KISAR4
KISAR5
KISAR6
KISAR7
KISDRO
KISDR1
KISDR2
KISDR3
KISDR4
KISDR5
KISDR6
KISDR7
646 .. 632
706 .. 650
710
User XRB (in reverse order)
User FIRQB (in reverse order)
User keyword
712 .. 720
722 .. 730
732
16(USP) 14(USP) 12(USP) 10(USP)
6(USP) 4(USP) 2(USP)
(USP)
User stack pointer, USP
734 .. 742
744 .. 752
754
756
760 .. 772
774
CRASAV + 776
16(KSP) 14(KSP) 12(KSP) 10(KSP)
6(KSP) 4(KSP) 2(KSP)
(KSP)
Processor status word, PSW
Virtual PC
RO R1 R2 R3 R4 R5
Kernal stack pointer, KSP
ERROR CODE
LOWAD
HGHAD
MEMERR
$40, Low order address of error
$42, High order address of error and cycle type
$44, Memory System Error register
'NOTE 1 The CRASAV area is normally filled with all 1's (177777). This is
helpful in determining what is valid data and how far the crash got.
'NOTE 2 CRASAV =24000 physical for RSTS VS.x and V9.x. The LOWAD,
HGHAD and MEMERR vary per system. Look at an old CRASH
DUMP for the following:
Memory parity/ECC log
LOWADD
HI ADD
MEMERR .. .
067554/ 040122
000001
144014 .. .
Therefore
LOWAD =067554,
MEMERR = 067560 virtual.
RSTS-10
HGHAD = 067556
and
ANAL VZING RSTS HAL 7S
flSTS V9.lt CRASH DUMP AREA IN MEMORV
Below are listed the locations that differ from V8.x
Location
Contents
The following area is unassigned and must be at least 10. words long for stack
space.
CRASAV
56 .. 220
UNASSIGNED
These next two words may be at higher addresses depending on exclusion of
other conditional data below.
Complement of size of dumped monitor image
Size of sumped monitor image
222
224
The following data is only present if the system has Unibus Mapping
Registers. If I and D space is not present this data will occupy slots 332 thru 524
226 .. 244
UMR's 0-3
246 .. 264
UMR's 4-7
UMR's 8-11
266 .. 304
306 .. 324
UMR's 12-15
UMR's 16-19
326 .. 344
UMR's 20-23
346 .. 364
366 .. 404
UMR's 24-27
406 .. 420
UMR's 28-30
The following data is only present if the CPU's has I and D space.
422
432
442
452
462
472
502
512
..
..
..
..
..
..
..
..
430
440
450
460
470
480
510
520
UDSARO
UDSAR1
UDSAR2
UDSAR3
UDSAR4
UDSAR5
UDSAR6
UDSAR7
UDSDRO
UDSDR1
UDSDR2
UDSDR3
UDSDR4
UDSDR5
UDSDR6
UDSDR7
RSTS-11
KDSARO
KDSAR1
KDSAR2
KDSAR3
KDSAR4
KDSAR5
KDSAR6
KDSAR7
KDSDRO
KDSDR1
KDSDR2
KDSDR3
KDSDR4
KDSDR5
KDSDR6
KDSDR7
Asm1M V3.2 ERROA LOGGER
To run the RSX11 M V3.2 Error Logger proceed as follows after logging in:
>RUN $PSE
PSE>[outpuUile]=[inpuLdev:]
(default=SYO:[1,6]ERROR.SYS=SYO:)
PSE>/\Z
>RUN $SYE
SYE>[reporUile] [/sw's]=inpuUile
Example of a full error report:
RUN $PSE
PSE>SYO: [1,6] ERROR.SYS=SYO:
PSE>/\Z
>RUN $SYE
SYE> SYO:ERRLOG.LST/RP=SYO:[1 ,6] ERROR.SYS
SYE>/\Z
>PIP TI:=ERRLOG.LST
Switches:
/RP[:class]
HDW[:type]
:MEM (all cache/memory errors)
:DSK (disk errors)
:MAG (tape errors)
null (all types of hardware errors)
TMO[:type]
:DSK (interrupt timeout errors)
:MAG (interrupt timeout errors)
SYS[:type]
:PSE (all entries from PSE operations)
:STA (errlog startups)
null (all types of system entries)
/SU
(create Summary)
/OU
(create short summary)
/-RP
(not include individual error reports)
/DV:DEV[n]
:CMM
:UDI
:PWR
(DB1: ,DR1: etc)
(comm devices)
(unidentified Interrupts)
(power fail)
/BEG:time
/END:time
(dd-mmm-yy:hh:mm:ss)
(dd-mmm-yy:hh:mm:ss)
RSX-1
r.SJ~11
M Vi!·,;:/r-ISX11 M+
~p.P.Op. LOGG~P'
To run the RSX11 M V4.x/RSX11 M+ Error Logger proceed as follows after
logging in:
>RUN $RPT
RPT> [reporUile] [/sw's]=[inpuUile] [/sw's]
Example of a full error report
RPT> [1 ,6]ERRLOG.LST=[1 ,6]LOG.RPT/F:F/T:A/W:N/DE:A
Switches:
/T:A
:c
:E
:M
PE
:PR
:S
/DA:P
:R
:T
:Y
/F:B
:F
:N
:R
/W:N
:W
[II]
[ontrl]
[rrors]
[emory]
[ripherals]
[ocessor]
[ystemJ nfo]
[revious]:ndays
[ange]:startend (DD-MMM-YY HH:MM:SS)
[oday]
[esterday]
[rief]
[ull]
[one]
register]
[arrow]
[ide]
/DE:A
[II]
:(device mnemonic)
/PA:bbbb.xxx(:bbbb.xxx) [b=block #, x=record #]
/R:D
M
W
S
/SE:D
:P
lay]
[onth]
leek]
[ystem]
[rive]:number and/or
[ack]:number
IV:volumeJabel
/SU:parameter
(one of - ALL,ERROR,GEOMETRY,HISTORY) (M+ only)
RSX-2
rlS!(
CrlAS~·J
DUMP ANAL VZER (CDA)
When RSX crashes it will either go into XDT, if it was gen'd into the system, or
transfer control to the EXECUTIVE CRASH DUMP ROUTINE. From XDT you
can transfer control by typing an X to the XDT> prompt. You can also transfer
control manually by restarting the processor at location 40. This can be used
in the case of system halts or hangs. After control has been transferred, the
following message will appear on the console terminal:
CRASH-CONT WITH SCRATCH MEDIA ON (device mnemonic):
The CPU then halts waiting for you to put the scratch media online and hit the
CONTINUE switch on the processor console. When the dump is complete the
CPU halts again and you may now reboot the system. Once the system is up
you can run the CRASH DUMP ANALYZER program (CDA) to analyze the
dump. The procedure is as follows:
>MOUNT ddu:/FOR (crash dump media on device ddu:)
>RUN$CDA
CDA>[lisUile/sw'sj,[binary_file/swj=[symboUile/STBj,crashJnput[/sw'sj
CDA>/\Z
>
Example, crash dump on MMO:
>MOUNT MMO:/FOR
>RUN$CDA
CDA>CRASH/-SP,CRASH/MEMSIZ:256.=[1,54jRSX11 M.STB/STB,MMO:I
All/DUMP:0:1000000
CDA>/\Z
>PIP TI:=CRASH.lST
Crash-'nput Analysis Switches
IACT or IATl
I ADV
IAll
ICLI or ICPB
IClQ
ICTl
IDEVor ISCB
IDUMP:a:b
IHDR
IKDS:a:b
IKIS:a:b
IPCB or IPAR
IPOOl[:a:bj
= Control Blocks for Active Tasks
= Control Blocks for all Devices
= All Switches Except IDUMP IKDS IKIS I
TASK ITDS ITIS
= Command Line Interpreter Parser
Blocks
= Clock Queue
= Device Control Tables and Request
Blocks
= Control Blocks for all Active Devices
= Physical Memory Dump from
Address a to b
= Headers for Memory Resident Tasks
= Kernel Dspace Virtual Dump from
Address a to b (M+)
= Kernel Ispace Virtual Dump from
Address a to b (M+)
= Partition Control Blocks
= System Pool Dump
RSX-3
P,Sj~
CPlASH
DU~_qp
ANALVZER (CDA)
CrashJnput Analysis Switches (cont.)
/SECPOOL[:a:bj
/STD or /TCB
/-SYS
/TASK:name:a:b
/TDS:name[:a:bj
/TIS:name[:a:bj
= Secondary Pool Dump (M+)
= Control Blocks for the System Task Directory
= Suppress the System Information (first 5 pages)
= Task "name"'s Virtual Space from address a to b
= Task "name"'s Virtual Dspace from Address a to b
(M+)
= Task "name"'s Virtual Ispace form Address a to b
(M+)
CrashJnput Function Switches
/BL:n
/DENS:n
= Starting Octal Block of CrashJnput Device
= MagTape Density, n = 800,1600, low, high,
/KMR
= Forces assignment of KAPR's for crash <-KMR>
LisCFile Function Switches
*/EXIT:n
*/LlMIT:n
*/LlNES:n
/-SP
= Terminate after n analysis errors <-->
= Limits LisCFile to n Pages
= Limits Page length to n Lines
= Don't print the LisCFile
Binary_File Function Switch
*/MEMSIZ:n
= Save nK of Memory from
Crash
Note: n can be specified in decimal by putting a "." after the number, for
example 256 decimal is specified in the command line as "256."
RSX-4
RSX has several halts in the code but are almost always preceded by an
ERROR message describing the problem. The halts are located in the CRASH
code, PARITY code, POWER code and the I NITL code (at least the only ones I
could find!). The most common halt is in the CRASH code as RSX always halts
on a system crash after asking you to specify the crash dump device and put it
online.
With all halts there is one very important rule to follow and that is to always
dump the registers (see pages 146-149). The halts can occur in 1 of 4 RSX
modules (look these up on RSX uFiche for more detail). I have indicated if they
apply to M and/or M+.
-I_ CRASH module
a) DOCRSH (M+)
This is where RSX11 M+ halts after printing the "CRASH-CaNT WITH
SCRATCH .. " message on the console. Remember to examine all
registers before taking a dump as they may help in determining why we
crashed. The halt can be identified by examining the data around the
halt address (remember the console halt address is virtual and must be
relocated, see RSTS-5 for details) for the following pattern:
xxxxxxxx/OOOOOO
xxxxxxxx/000167
xxxxxxxx/000076
HALT
JMP DUMP
;hit continue for dump
;do a crash dump
b) CRSHL T (M,M+)
This halt is where RSX11 M/M+ goes after completing a dump or getting
an error on the I/O on the crash device (exam registers). RSX11 M also
uses it as the location to halt at after printing the "CRASH-CaNT WITH
SCRATCH .. " message on the console. When you halt here after taking·a
dump you can either reboot the system or hit continue to take another
dump. The pattern in memory around this halt is?
For RSX11 M:
xxxxxxxx/000773
xxxxxxxx/000207
xxxxxxxx/OOOOOO
xxxxxxxx/000413
BR 10$
RTS
$CRSHLT: HALT
BR DUMP
RSX-5
;branch
;return
;crash halt, hit cont
;to do a crash dump
•
ANAL VZING liS}( HALTS
b) CRSHL T (M,M+) (cont.)
For RSX11 M+:
xxxxxxxx/OOOOOO
xxxxxxxx/000167
xxxxxxxx/176700
$CRSHLT: HALT
JMP $CRALT
;dump complete, hit
;continue for another
;crash dump
c) CKSUM+16 (M/M+)
This halt will occur after starting a crash dump ifthe crash has corrupted
the crash device's address table. A checksum is done on the address. No
error message is printed. Since a dump can't be taken your only hope is
the register dump you took earlier. The pattern in memory will be as
follows:
xxxxxxxx/001402
xxxxxxxx/OOOOOO
xxxxxxxx/000767
xxxxxxxx/000207
BEQ 10$
HALT
BR CKSUM
RTS
;checksum ok?
;no, halt system
;try checksum again
;return
d) HALT 40 (M,M+)
If no crash dump support was included in the system it will halt at
location 40 in memory. Look at the registers to find the cause of the
crash. In this case memory will look like:
00000040/000000
00000043/000776
HALT
BR 40
RSX-6
;no crash support
;no cont possible
ANALYZING RS:' HAIL7S
2. PARITY module
a) RSX will halt here if it gets a parity error in the EXECUTIVE or if it gets
anofher parity error while se.rvicing the first. The registers will give the
error information on the most recent parity error and an area in memory
called $MSTAT will contain info on the first parity error in the case of
double error halts. The halt pattern in memory looks like:
xxxxxxxx/000771
xxxxxxxx/012600
xxxxxxxx/OOOOOO
xxxxxxxx/000776
50$:
60$:
BR 30$
MOV (SP)+,RO
HALT
SR 60$
;branch
;pop stack to RO
;fatal parity error
;no cont possible
To find $MSTAT's address for the first error's information you need to
EXAM location 114 to get the address of the service routine ($PARER).
Remember this is a virtual address! Then EXAM $PARER for about 30
locations and look for this pattern where "aaaaaa" is the virtual address
of $MSTAT.
xxxxxxxx/012700
xxxxxxxx/?
xxxxxxxx/012701
xxxxxxxx/aaaaaa
MOV #$MPCSR,RO
MOV #$MSTAT,R1
;move CSR address
;table to RO
;move save status
;area to R1
If you now EXAM aaaaaa ($MSTAT) the following registers were saved:
MSTAT: +0
+2
+4
+6
+10
+12
$40
$42
$44
$46
$50
$52
Low error address register
High error address register
Memory system error register
Cache control register
Cache mai ntenance register
Cache hit/miss register
RSX-7
ANAL VZING P.Sie HALTS
3. POWER module
a) PWRFAIL (M/M+)
This halt occurs when RSX is finished it's power down code and is
waiting for a powerup. The pattern in memory will look as follows:
xxxxxxxx/OOOOOO
xxxxxxxx/016706
xxxxxxxx/?
xxxxxxxx/052767
xxxxxxxx/030000
xxxxxxxx/177776
HALT
MOV $POWSP,SP
BIS #PMODE,PS
;wait for powerup
;restore SP
;index to $POWSP
;setup PSW mode
;PM=user
;PSW
b) PWRUP (M+)
This halt occurs is power is restored but a powerfail was not indicated.
This can happen if the system is halted, powered off and then back on
again or possibly on double powerfails. The area in memory will be as
follows:
xxxxxxxx/OOOOOO
xxxxxxxx/000776
xxxxxxxx/005067
xxxxxxxx/?
xxxxxxxx/OO5301
$5:
10$:
HALT
BR 5$
CLR $PWKAO(R2)
DEC R1
;pwrup + no pwrdwn
;no cant possible
;reference only
;reference only
;reference only
I"!. IWITL module
There are various halts in the RSX initialization code. They are all preceded
by an ASCII message on the console describing the problem. Examine the
registers to determine the cause of the halt.
RSX-8
Pall1ic Traps
An unexpected system fault occured. On PDP11 the message goes:
KA6=#
APS=#
PC=#, PS=#
Trap type #
KA6 APS PC PS -
is the contents of the segmentation register for the area in which
the system stack is kept.
is the location where the hardware stored the PSW during the trap.
is the contents of the program counter.
is the contents of the processor status word.
Trap type is one of the following:
o
1
2
3
4
Bus error
Illegal instruction
BPT/trace
lOT
Power fail
5
EMT
6
7
8 or 10
9 or 11
Recursive system call (trap instruction)
1170 Cache parity or programmed interrupt
Floating point trap
Segmentation violation (almost always software)
Note: In some versions of UNIX, Panic trap types get echoed in octal. Thus
panic 8 will be type 10 and 9 will be type 11.
Oiher Panics:
Panic:parity
1# 2# 3# 4#
A parity error has occured in main memory. If this occurs in user mode, then
the users process is simply terminated and no panic occurs. The four registers
printed out in order are:
LEAR
17777740
HEAR
MSER
17777742
17777744
UNIX-1
CCR
17777746
UNm ERROR IlGESSAGES (cont)
Panic:buffers
Insufficient memory space was found when the system was allocating the
non-addressable buffer pool space. SOFTWARE! Either decrease these
system parameters or the main memory size should be increased.
Panic:IO err in swap
An unrecoverable error has occurred during a system swap operation. Could
be a hardware problem in the disk drive or controller. Could also be a bad spot
on the pack.
Panic:no clock
A KW11 L or KW11 P was not found at the standard address during system
startup. UNIX requires a PDP11 to have a clock.
Panic:double
You occasionally may see a "DOUBLE PANIC" message. This simply means
that the system was processing one panic trap when a second occured.
Some Diller Possible Messages
Bad block on "device name" drive #,[cntrl #], [slice #]
A block number not in the valid range of available free blocks on a file system
has been detected. Device type may be any of those listed in the device error
message description. SOFTWARE PROBLEM. (File system must be
unmounted and checked).
Bad free count on "device name" drive #,[cntrl #],[slice #]
Corrupted free list block on file system was detected. Same device types as
above. SOFTWARE PROBLEM. Same fix as above.
UNIX-2
LINDe ERROR MESSAGES (cont)
Stray interrupt at # (#=interrupt vector)
A device has interrupted through an unexpected vector on the unibus. The
vector number printed is usually the correct value for a device. Could possibly
be caused by a device specified at an incorrect vector in the system descriptor
file. If this is not the case, then hardware is suspect.
**Death
Red zone stack violation always
Device Error Messages
Device error messages indicate that a hardware error has occured on a block
type device. The error will appear as follows:
Device error on "device type", drive #,[cntrl #], [slice #]
bn=#,er=#,#
"device type":
RM02/3/S,RM80,RP04/S/6,RP07,RP03,RKOS,RL01/2,
RF11 ,RS03/4,TU16,TU78,ML 11 (TU16 for TU16,TE16,
TRU4S,TU77)
[contrl #]:
0 will appear if more than one controller is gen'd into your
system (RHO,RH1,TMO,TM1).
bn=#:
is the logical block number in error, followed by the
contents of two of the device registers:
Device
RL01/2
RF11
RKOS
RMOS
RM80
RP03
RP04/S/6 (HP.C)
(GD.C)
RP07
RS03/4
TU16
(HT.C)
Error Register
RLCS
RFCS
RKDS
RMER1
RMER1
RPER
RPER1
RPER1
RPER1
RPCS2
MTER
MTER
All register contents are printed in octal.
UNIX-3
Control Register
RLDA
RFDAE
RKER
RMDS
RMDS
RPDS
RPCS2
MBA Status reg
RPDS
MTCS2
MBA Status reg
UNDC ERROR MESSAGES (cont.)
If after a crash, a tape dump is initiated and a tape error occurs the following
message will appear:
ERR #,#
The first number is the address of the block being transmitted at the time of the
error. The second number is MTER in the case of a TU16 and TUDTE in the
case of a TU78.
In the case of a hard error on a disk the message will appear as follows:
Hard error on "drive type",drive #, [cntrl #],[slice #],
DS=#,ER=#,#,#
This message pertains only to RP04/S/6, RMOS,RM80,RP07,ML 11. In the case
of the RP's the registers are RPDS followed by RPER1 ,RPER2,RPER3. In the
case of the RM's they are RMDS followed by RMER1,RMMR2,RMER2 ..
To initiate a crash dump
1. Take a Hardware Register Dump first
2. Load address 44
or deposit 44 into R7
3. Press start
or
press proceed/continue
UNIX-4
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