LA5941PR10_ LA 5941P

User Manual:

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1

1

Compal Confidential
NIMUA/UB
2

Schematics Document
Arrandale
with Intel IBEX PEAK-M core logic

2

3

3

REV:0.3

4

4

Issued Date

Compal Electronics,Ltd.

Compal Secret Data

Security Classification

2010/01/13

Deciphered Date

2011/01/13

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Cover Sheet
Size Document Number
Custom

Rev
0.3

LA-5941P

Date: Thursday, April 08, 2010

Sheet
E

1

of

50

http://hobi-elektronika.net

A

B

Compal confidential
File Name :

C

D

Thermal-sensor
EMC1403

ZZZ

VRAM 64*16
DDR3*4

14.1W_PCB_LA5941P
1

DAZ0D500102

Intel
Arrandale
(UMA/SG)

PCI-E X16

page20

E

CR BD:
LS-5944P

POWER BD:
LS-5941P
POWER BT
SW BD:
LS-5942P
NOVO BT

page38

Clock Generator
SLG8LV597VTR

Body-Detect BD:
LS-5947P

1

page12

Socket-rPGA989
37.5mm*37.5mm

NVidia N11M-LP1
page19~23

DDR3-SO-DIMM X2
BANK 0, 1, 2, 3

page5~9

level shift IC
ASM1442

HDMI
CONN

100MHz
2.7GT/s

page25

page24

Finger Print BD:
LS-5943P
U-pek TCS5D

Dual Channel
DDR3-800(1.5V)
DDR3-1067(1.5V)

DMI *4

FDI *8

page 10,11

UP TO 8G
2Channel Speaker
page33

CRT Connector

SW1

Intel Ibex Peak M

page26
2

LVDS
Connector

page27

AZALIA

2

page33

ALC259

FCBGA 951

PCI Express
Mini card Slot 2

DMIC_Int

Audio Codec

SW2

Audio Jack CONN.

page33

page37

25mm*25mm

6*PCI-E BUS

CMOS Camera

14*USB2.0

page28

page27

USB(WLAN)

SPI

BlueTooth CONN

6*SATA serial

page 13~18

page37

PCI Express
Mini card Slot 3

SPI ROM
BIOS+ME

page28

USB1 CONN.

page37

USB2 CONN

page37

LPC BUS

page13

3

EC

Atheros 8131/32
SIM Card
page28

10/100/1G LAN
USB(WWAN)

ENE KB926E0

Touch Pad

page30

AD

4

page28

SPI ROM
EC

page38

page38

ESATA AND USB CONN
page37

page36

SATA HDD CONN
page32
4

SSD

page28

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Mini card Slot 1
2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Card Reader
CONN

page35

page35

USB/JACK BD:
LS-5945P
USB PORT1,2,3
HP JACK
MIC JACK
KILL SW

WWAN/3G
Int.KBD

G-sensor
CAP SENSOR BD:
LS-5946P
USER/SG
MUTE
Power Saving
BUTTON & LED

page37

page34

page29

RJ45 CONN

USB3 CONN

3

B

C

D

Title

Compal Electronics, Inc.
MB Block Diagram

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P

Thursday, April 08, 2010

Sheet
E

2

of

50

http://hobi-elektronika.net

A

B

DDR3 Voltage Rails

C

D

E

SMBUS Control Table

+5VS

+3VS

SOURCE RAM
M2

+1.5VS
power
plane

+VCCP
+CPU_CORE
+VGA_CORE

1

+5VALW

+1.5V
+1.8VS

+B

+0.75VS
+3VALW
+1.05VS

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK

State

For SG

SML0DATA

+3VS_DELAY

SML1CLK

+1.8VS_VGA

SML1DATA

KB926
+3VALW
KB926
+3VALW
PCH
+3VALW
PCH
+3VALW
PCH
+3VALW

X

KB926

SODIMM

V

X

X

X

X

V

X

X

X

+3VALW

X

X

V

X

X

X

X

X

X

+3VALW

WLAN
CLK CHIP WWAN

BATT

+3VALW

N11x
Thermal
Sensor

EMC1403

Cap sensor
board

X

X

X

+3VS

+3VS

V

X

V

ALS

PCH

X

X

V

V

+3VS

+3VALW

+3VS

+3VS

V

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

V

X

X

X

X

X

X

X

X

V

1

+1.5VS_VGA

2

S0

O

O

O

O

S3

O

O

O

X

S5 S4/AC

O

O

X

X

S5 S4/ Battery only

O

X

X

X

S5 S4/AC & Battery
don't exist

X

X

X

X

PCH, I2C / SMBUS ADDRESSING

EC, I2C / SMBUS ADDRESSING

DEVICE

HEX

ADDRESS

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

PCH

96/98,R/W

1001011X

DDR SO-DIMM 1

A4

10100100

EMC1403 Thermal sensor

9A

1001101X

CLOCK GENERATOR (EXT.)

D2

11010010

N-vidia Thermal sensor

9E

1001111X

ALS

70/72,R/W

0111000X

@ FUNCTION

3

PVT
(45 BOM)
10/100 LAN
GIGA LAN
FOR UMA HDMI components
FOR HDMI components
3G(WWAN) function
(X76 BOM)
ESATA function
Camera function
SSD w/ miniPCIE socket
FOR 10M CHIP
FOR 11M CHIP
UMA only (Arranddale)
DIS only (Arranddale)
FOR NVIDIA PART
FOR SWITCHABLE

45@
100@
GIGA@
UMA_HDMI@
HDMI@
3G@
X76@
ESATA@
CMOS@
SSD@
10M@
11M@
UMA@
DIS@
VGA@
HYBRID@
HU@
HD@

PCIE PORT LIST

NON-USE

PORT
1
2
3
4
5
6
7
8

SKU
Arrandale(dGPU)
4

DIS@ / 100@

DEVICE

PORT

DEVICE

NEW CARD
WLAN
LAN
3G

0
1
2
3
4
5
6
7
8
9
10
11
12
13

USB 1
USB/ESATA
CMOS
USB 2

DEVICE

0
HDD
1
SSD
2,3 HM55 disabled
4
E-SATA
5

SWITCHABLE or UMA only
SWITCHABLE or DIS only

2

0111001X

USB PORT LIST

SATA PORT LIST
PORT

1001100X

3

CARD READER
X HM55 disabled
X HM55 disabled
WIRELESS
USB 3
FigerPrinter
BT
3G

for EVT
4

DIS only

Arrandale(iGPU)

UMA@ / 100@

for EVT

UMA only

Arrandale(iGPU+dGPU) HYBRID@

Compal Secret Data

Security Classification

SWITCHABLE

2010/01/13

Issued Date

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
MB Notes List

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
E

3

of

50

A

http://hobi-elektronika.net
B

VGA and DDR3 Voltage Rails

C

D

E

(N11M GPIO)

GPIO

I/O

ACTIVE

Function Description

GPIO0

N/A

N/A

GPIO1

IN

-

HDMI_DETECT_VGA

GPIO2

OUT

H

NV_INVTPWM

GPIO3

OUT

H

VGA_ENVDD_R

GPIO4

OUT

H

VGA_ENABLT

GPIO5

OUT

-

GPU VID0

GPIO6

OUT

-

GPU VID1

GPIO7

OUT

-

GPIO8

I/O

L

GPIO9

OUT

L

GPIO10

OUT

GPIO11

I/O

L

GPIO12

IN

-

GPIO13

OUT

-

GPIO14

OUT

-

GPIO15

IN

-

GPIO16

OUT

-

GPIO17

IN

-

GPIO18

IN

-

GPIO19

IN

-

GPIO20

IN

-

GPIO21

IN

-

GPIO22

IN

-

GPIO23

I/O

1

1

Power Sequence

The ramp time for any rail must be more than 40us

(+3VS) VDD33
PEX_VDD can ramp up any time

2

(1.05VS)PEX_VDD
tNVVDD

(+VGA_CORE) NVVDD
tNV-IFPAB_IOVDD

(1.8VS)IFPAB_IOVDD

2

tNV-FBVDDQ

(1.5VS) FBVDDQ

3

3

N11M-LP1
(40nm)

GPIO5

GPIO6

Device ID

GPU_VID0

GPU_VID1
0

0.8V

Deep P12

0x0A6E

0
0

1
1

0.85V

P8

0.86V

P0

1

VGA_CORE

P-State

4

4

Compal Secret Data

Security Classification
2010/01/13

Issued Date

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, Inc.
VGA Notes List

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
E

4

of

50

http://hobi-elektronika.net

5

4

3

2

1

DDR3 Compensation Signals

SM_RCOMP0

1
R567
1
R566
1
R565

SM_RCOMP1
SM_RCOMP2

Κ

D

2
100_0402_1%
2
24.9_0402_1%
2
130_0402_1%

Layout Note:Please these
resistors near Processor

Layout rule 10mil width trace
length < 0.5", spacing 20mil

D

JCPU1B
AT23

COMP3

2COMP2

AT24

COMP2

49.9_0402_1%

1 R548

2COMP1

G16

COMP1

49.9_0402_1%

1 R557

2COMP0

AT26

COMP0

TP_SKTOCC#

16

H_PECI

R564
1

0_0402_5%
2 H_PECI_ISO

2 R569

+VCCP

H_CATERR#

1
R163

49.9_0402_1%

AK14

AT15

SKTOCC#
CATERR#

THERMAL

2

+VCCP

AH24

PECI

1 68_0402_5%
H_PROCHOT#

34,48 H_PROCHOT#

H_THERMTRIP#

16 H_THERMTRIP#

AN26

AK15

PROCHOT#

THERMTRIP#

A16
B16

CLK_CPU_BCLK
CLK_CPU_BCLK#

BCLK_ITP
BCLK_ITP#

AR30
AT30

CLK_CPU_ITP
CLK_CPU_ITP#

PEG_CLK
PEG_CLK#

E16
D16

CLK_EXP
CLK_EXP#

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A18
A17

BCLK
BCLK#

CLOCKS

2COMP3

1 R558

F6

SM_DRAMRST#

AL1
AM1
AN1

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXT_TS#[0]
PM_EXT_TS#[1]

AN15
AP15

PM_EXTTS#0
PM_EXTTS#1

PRDY#
PREQ#

AT28
AP27

XDP_PRDY#
XDP_PREQ#

TCK
TMS
TRST#

AN28
AP28
AT27

XDP_TCK
XDP_TMS
XDP_TRST#

TDI
TDO
TDI_M
TDO_M

AT29
AR27
AR29
AP29

XDP_TDI
XDP_TDO
R555 2

DBR#

AN25

XDP_DBRESET#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

DDR3
MISC

1 R560

20_0402_1%

MISC

20_0402_1%

C

SVT

68_0402_5%
1 R187

16 H_CPUPWRGD
15 PM_DRAM_PWRGD

RESET_OBS#

AL15

PM_SYNC
VCCPWRGOOD_1

1 R190

2 VCCPWRGOOD_1
0_0402_5%

AN14

1 R139

2 VCCPWRGOOD_0
0_0402_5%

AN27

VCCPWRGOOD_0

1 R191

2 VDDPWRGOOD_R
0_0402_5%

AK13

SM_DRAMPWROK

VTT_POK

R183
560_0402_5%

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

R185
1

BUF_PLT_RST#

1

16,28,29

PLT_RST#_R

2

1.5K_0402_5%

+VCCP
PM_EXTTS#0

PAD
PAD

1
R561
1
R562

PM_EXTTS#1
CLK_EXP 14
CLK_EXP# 14

3

only for Arrandale
without EDP

1
R563

2
0_0402_5%

T19

PM_EXTTS#1_R 10,11

PAD

2
10K_0402_5%
2
10K_0402_5%

XDP_PREQ# R136 1

@

2 51_0402_1%

XDP_TMS

R138 1

@

2 51_0402_1%

XDP_TDI

R556 1

@

2 51_0402_1%

XDP_TDO

R134 1

XDP_TCK

R57

XDP_TRST#

R133 1

XDP_DBRESET#

1

R137
1

2 51_0402_5%
@

2 51_0402_1%
2 51_0402_5%

@

2 1K_0402_5%

C

+3VS

CHECK INTEL DOCUMENT #385422
Debug Port Design Guide Rev1.3
1 0_0402_5%

1

2
1
R184
1K_0402_1%

VCCP_POK

AP26

2 H_PM_SYNC_R
0_0402_5%

2

IC,AUB_CFD_rPGA,R1P0
ME@

2

R186
750_0402_1%
B

For Intel S3 Power Reduction.
+1.5V

1

2

2
VDDPWRGOOD_R

2

1.5K_0402_1%
NC7SZ08P5X_NL_SC70-5
R194

DDR3 CONNECTER

2

2

DRAMRST#

10,11 DRAMRST#

R192
3K_0402_1%

750_0402_1%

2
R300

1

Q27
2N7002_SOT23

@

PCH GPIO CONTROL
16 DRAMRST_CNTRL_PCH

1
R281

2

1

R416
10K_0402_5%

SM_DRAMRST#

3

2
R283

1
100K_0402_5%

2 DRAMRST_CNTRL_R
0_0402_5%

+5VALW

A

3

@
1
0_0402_5%

S

DRAM_PWRGD

R301
1K_0402_1%

D

4

G

Y
3

For Intel S3 Power Reduction.

2
G

A

R195

1

1

VCCP_POK

U8

P

B

R193
1.1K_0402_1%
@

1

5

+3VALW

2

+1.5V

1

5

B

1

46

FROM POWER VTT
POWER GOOD SIGNAL

1 H_CPURST#_R
R135

PWR MANAGEMENT

2

+VCCP

15 H_PM_SYNC

JTAG & BPM

@

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16
T17
T18

2

A

1

6

SVT
C338
0.047U_0402_16V7K

1

S3_0.75V_EN

44

D
Q61
2N7002_SOT23

2
G
3

VCCP_POK

Compal Secret Data

Security Classification

S

Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Arrandale(1/5)-Thermal/XDP

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

5

of

50

http://hobi-elektronika.net

5

Κ

4

3

2

1

Layout rule trace
length < 0.5"

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

15
15
15
15

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B24
D23
B23
A22

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

15
15
15
15

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

D24
G24
F23
H23

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

15
15
15
15

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

D25
F24
E23
G23

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

E22
D21
D19
D18
G21
E19
F21
G18

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

D22
C21
D20
C18
G22
E20
F20
G19

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

15 FDI_FSYNC0
15 FDI_FSYNC1

FDI_FSYNC0
FDI_FSYNC1

F17
E17

FDI_FSYNC[0]
FDI_FSYNC[1]

15 FDI_INT

FDI_INT

C17

FDI_INT

15 FDI_LSYNC0
15 FDI_LSYNC1

FDI_LSYNC0
FDI_LSYNC1

F18
D17

JCPU1E

FDI_LSYNC[0]
FDI_LSYNC[1]

PCI EXPRESS -- GRAPHICS

C

15
15
15
15
15
15
15
15

A24
C23
B22
A21

Intel(R) FDI

15
15
15
15
15
15
15
15

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI

D

15
15
15
15

EXP_ICOMPI

1 R544

2 49.9_0402_1%

EXP_RBIAS

1 R545

2 750_0402_1%
PCIE_CRX_GTX_N[0..15]

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

B26
A26
B27
A25

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P0

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PCIE_CTX_GRX_C_N15
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N0

C527
C540
C529
C542
C531
C544
C533
C546
C535
C562
C564
C555
C557
C561
C548
C559

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K

PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N0

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P0

C528
C541
C530
C543
C532
C545
C534
C547
C536
C563
C565
C556
C558
C560
C549
C550

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K

PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P0

PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P[0..15]

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

19

19

CFG0
CFG3
CFG4

PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal

@ R59

PCIE_CTX_GRX_N[0..15]

R547
0_0402_5%
@
1
2
@
1
2

PCIE_CTX_GRX_P[0..15]

19

CFG Straps for PROCESSOR

R536 1

HYBRID@
2 1K_0402_5%

FDI_INT

R534 1

HYBRID@
2 1K_0402_5%

FDI_LSYNC0

R533 1

HYBRID@
2 1K_0402_5%

FDI_LSYNC1

R535 1

HYBRID@
2 1K_0402_5%

H_RSVD17_R
H_RSVD18_R

1
R58

@
2
3.01K_0402_1%

CFG3

RSVD15
RSVD16

A20
B20

RSVD17
RSVD18

U9
T9

RSVD19
RSVD20

AC9
AB9

RSVD21
RSVD22

RSVD32
RSVD33

AJ13
AJ12

RSVD34
RSVD35

AH25
AK26

RSVD36
RSVD_NCTF_37

AL26
AR2

RSVD38
RSVD39

AJ26
AJ27

RSVD_NCTF_40
RSVD_NCTF_41

AP1
AT2

RSVD_NCTF_42
RSVD_NCTF_43

AT3
AR1

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65

E15
F15
A2
D15
C15
AJ15
AH15

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

RSVD_NCTF_23
RSVD_NCTF_24

J29
J28

RSVD26
RSVD27

A34
A33

RSVD_NCTF_28
RSVD_NCTF_29

C35
B35

RSVD_NCTF_30
RSVD_NCTF_31

VSS

11=1*16 PEG
10=2*8 PEG

1
R61

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

B19
A19

PCI-Express Configuration Select
1: Single PEG
CFG0
0: Bifurcation enabled
Not applicable for Clarksfield Processor
CFG[1:0]

FDI_FSYNC1

R546
0_0402_5%

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

C1
A3

IC,AUB_CFD_rPGA,R1P0
ME@

HYBRID@
2 1K_0402_5%

CFG7

19

CFG0

R532 1

1
2
3.01K_0402_1%

FOR ES1 SAMPLE ONLY

HYBRID@

B

FDI_FSYNC0

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

RESERVED

JCPU1A

D

C

R189
0_0402_5%
RSVD64_R 2
@
@
RSVD65_R 2
R188
0_0402_5%

1
1

B

AP34

IC,AUB_CFD_rPGA,R1P0
ME@

2
3.01K_0402_1%

CFG3-PCI Express Static Lane Reversal
1: Normal Operation
CFG3
0: Lane Numbers Reversed
15 -> 0, 14 ->1, .....

CFG4

1
R60

@
2
3.01K_0402_1%

CFG4-Display Port Presence
1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
Display Port
A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Arrandale(2/5)-DMI/PEG/FDI

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

6

of

50

http://hobi-elektronika.net

5

4

3

2

1

JCPU1D
JCPU1C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

C

B

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

10 DDR_A_BS0
10 DDR_A_BS1
10 DDR_A_BS2

AC3
AB2
U7

SA_BS[0]
SA_BS[1]
SA_BS[2]

10 DDR_A_CAS#
10 DDR_A_RAS#
10 DDR_A_WE#

AE1
AB3
AE9

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

10 DDR_A_D[0..63]

11 DDR_B_D[0..63]

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

AA6
AA7
P7

M_CLK_DDR0 10
M_CLK_DDR#0 10
DDR_CKE0_DIMMA

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

Y6
Y5
P6

M_CLK_DDR1 10
M_CLK_DDR#1 10
DDR_CKE1_DIMMA

10

SA_CS#[0]
SA_CS#[1]

AE2
AE8

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

10
10

SA_ODT[0]
SA_ODT[1]

AD8
AF9

M_ODT0 10
M_ODT1 10

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

B9
D7
H7
M7
AG6
AM7
AN10
AN13

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C9
F8
J9
N9
AH7
AK9
AP11
AT13

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

C8
F9
H9
M9
AH8
AK10
AN11
AR13

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DM[0..7]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

10

10

10

10

10

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

11 DDR_B_BS0
11 DDR_B_BS1
11 DDR_B_BS2

AB1
W5
R7

SB_BS[0]
SB_BS[1]
SB_BS[2]

11 DDR_B_CAS#
11 DDR_B_RAS#
11 DDR_B_WE#

AC5
Y7
AC6

SB_CAS#
SB_RAS#
SB_WE#

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

W8
W9
M3

M_CLK_DDR2 11
M_CLK_DDR#2 11
DDR_CKE2_DIMMB

11

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

V7
V6
M2

M_CLK_DDR3 11
M_CLK_DDR#3 11
DDR_CKE3_DIMMB

11

SB_CS#[0]
SB_CS#[1]

AB8
AD6

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

11
11

SB_ODT[0]
SB_ODT[1]

AC7
AD1

M_ODT2 11
M_ODT3 11

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

D4
E1
H3
K1
AH1
AL2
AR4
AT8

DDR_B_DM[0..7]

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

D

11

C

DDR SYSTEM MEMORY - B

D

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D5
F4
J4
L4
AH2
AL4
AR5
AR8

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#[0..7]

11

DDR_B_DQS[0..7]

11

DDR_B_MA[0..15]

11

B

IC,AUB_CFD_rPGA,R1P0
ME@
IC,AUB_CFD_rPGA,R1P0
ME@

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Arrandale(3/5)-DDR III

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

7

of

50

3

2

1

R132

AS NO CONNECT

GFX_IMON_R

+CPU_CORE

+GFX_CORE

JCPU1F

1 1K_0402_5%

2

BUT A SMALL AMOUNT OF POWER

HYBRID@

(~15MW) MAYBE WASTED

DGPU_SELECT

2

2

1

2

2

1
3

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

1.8V

1

0.6A

+1.5V_DDR3

J3
2

1

2

1

2

1

2

C

1

VCCPLL1
VCCPLL2
VCCPLL3

1

2

+VCCP

2

L26
L27
M26

1

2

+1.8VS

2

1

2

1

2

1

2

1

2

B

For Intel S3 Power Reduction.

1

@

2

47

C170
4.7U_0603_6.3V6K

+1.5V

VTT_SELECT 46

1

C169
10U_0805_6.3V6M

1

G15 VTT_SELECT

1

1

IC,AUB_CFD_rPGA,R1P0
ME@

48

47

+VCCP

1

PROC_DPRSLPVR

2

2

1

2

GFXVR_EN

C213
10U_0805_6.3V6M

POWER

2

1

1

C168
2.2U_0603_6.3V6K

CPU VIDS

J22
J20
J18
H21
H20
H19

+

2

C149
1U_0603_10V6K

1
R56

H_VID0 48
H_VID1 48
H_VID2 48
H_VID3 48
H_VID4 48
H_VID5 48
H_VID6 48
2
0_0402_5%

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

1

1

C218
10U_0805_6.3V6M

1

H_PSI#_R
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR_R

P10
N10
L10
K10

2

C167
1U_0603_10V6K

VTT_SELECT

2

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

PEG & DMI

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

1

C240
10U_0805_6.3V6M

2

C272
10U_0805_6.3V6M

1

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR

VTT0_59
VTT0_60
VTT0_61
VTT0_62

1

2

C215
10U_0805_6.3V6M

Q51
MMST3904-7-F_SOT323-3
@

C214
10U_0805_6.3V6M

E

Lenovo Request

AN33

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

2
2
B

@

PSI#

VTT1_45
VTT1_46
VTT1_47

3A

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

B

2

10K_0402_5%

0_0402_5%
@

C257
1U_0603_10V6K

E

1 R182

PSI_ON#

GFX_VR_EN

GFXVR_IMON

+VCCP

C

34

2

R140
330_0402_5%
1
2

C212
10U_0805_6.3V6M

2

PAD T16

C255
1U_0603_10V6K

1

2 R141

1

C273
10U_0805_6.3V6M

C

3
Q18
MMBT3906_SOT23-3

1

AR25 GFX_VR_EN
AT25
AM24 GFX_IMON_R

47
47
47
47
47
47
47

C258
10U_0805_6.3V6M

1

48

R550
1K_0402_1%
@

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

C253
1U_0603_10V6K

PSI#

@

D

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

C252
10U_0805_6.3V6M

H_PSI#_R

R551
1K_0402_1%

J24
J23
H25

FDI

SVT
STRIP PIN

0_0402_5%
1

C211
10U_0805_6.3V6M

2

R282
2

C210
10U_0805_6.3V6M

2

1

C209
10U_0805_6.3V6M

1

C208
10U_0805_6.3V6M

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AM22
AP22
AN22
AP23
AM23
AP24
AN24

47
47

+1.5V_DDR3

+VCCP
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

VCC_AXG_SENSE
VSS_AXG_SENSE

C256
1U_0603_10V6K

2

AR22
AT22

C268
220U_B2_2.5VM_R35

2

1

C207
10U_0805_6.3V6M

2

1

C274
10U_0805_6.3V6M

1

C217
10U_0805_6.3V6M

2

C219
10U_0805_6.3V6M

1

VAXG_SENSE
VSSAXG_SENSE

C254
1U_0603_10V6K

+VCCP

SENSE
LINES

2

15A

GRAPHICS VIDs

2

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

- 1.5V RAILS

2

2

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

1

C592

22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M

C554
330U_D2E_2.5VM_LESR9M

1

2

C591

DDR3

2

1

+
2

2

C159

HYBRID@
Q58
S 2N7002_SOT23

10U_0805_6.3V6M

1

1.1V

1

2

2

C189

1

GRAPHICS

2

@

1

2

C190
@

1

C200
10U_0805_6.3V6M

1

2

2

C191
@

1

2

1

C182
10U_0805_6.3V6M

@

1

C216
10U_0805_6.3V6M

2

2

C270
10U_0805_6.3V6M

1

1

C673
330U_D2E_2.5VM_LESR9M

C181
10U_0805_6.3V6M

2

C198
10U_0805_6.3V6M

1

C199
10U_0805_6.3V6M

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

C271
10U_0805_6.3V6M

AN35

IMVP_IMON

48

1
1

2

VTT_SENSE 46
@ PAD T15

SUSP

2

2

1

2

1

2

2

SUSP

R233
220_0402_5%

D

S

Q19
2N7002_SOT23

2
G

PVT

1

D

2
G

+1.5V_DDR3

0_0402_5%
11.5V_DDR3_GATE

Q23
2N7002_SOT23
3

39,44,45

1.5_SUS-

R267
2

1

C286
0.1U_0402_10V6K

B15
A15

1

SI4800BDY-T1-E3_SO8
R268
47K_0402_1%

SVT,timing
VTT_SENSE
VSS_SENSE_VTT

@

1
2
3
4

C287
0.1U_0402_10V6K

VCCSENSE 48
VSSSENSE 48

S
S
S
G

C288
0.1U_0402_10V6K

VCCSENSE
VSSSENSE

D
D
D
D

C289
0.1U_0402_10V6K

VCC_SENSE
VSS_SENSE

AJ34
AJ35

1

U11
8
7
6
5

+5VALW

C269
0.1U_0402_10V6K

ISENSE

1

JUMP_43X118

+1.5V_DDR3

2

+1.5V

@

H_VTTVID1 = High, 1.05V FOR Auburndale

1 2

H_VTTVID1 = Low, 1.1V FOR Clarksfiel

3

JUMP_43X118
J2
2 2
1 1

CPU

A

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

C160
@

1

+VCCP

CPU CORE SUPPLY

B

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

C161
@

+
C201
10U_0805_6.3V6M

C

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

SENSE LINES

D

+VCCP

18A

1.1V RAIL POWER

48A

1

POWER

22U_0805_6.3V6M
22U_0805_6.3V6M

22U_0805_6.3V6M
1

D

2
G

DESIGN GUIDE REV1.1

JCPU1G

1

1

4

3

http://hobi-elektronika.net

5

S

2

A

C325
0.1U_0603_25V7K

For Intel S3 Power Reduction.

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IC,AUB_CFD_rPGA,R1P0
ME@

5

4

3

2

Title

Compal Electronics, Inc.
Arrandale(4/5)-PWR

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

8

of

50

http://hobi-elektronika.net

5

4

3

2

CPU CORE

+CPU_CORE

2

1

2

1

2

C571
22U_0805_6.3V6M

2

1

C572
22U_0805_6.3V6M

2

1

C577
22U_0805_6.3V6M

2

1

C583
22U_0805_6.3V6M

2

1

C578
22U_0805_6.3V6M

2

1

C584
22U_0805_6.3V6M

2

1

C573
22U_0805_6.3V6M

2

1

C574
22U_0805_6.3V6M

2

1

C579
22U_0805_6.3V6M

2

1

Inside cavity

D

1

2

+
2

1
+
2

1

2

1

2

1

2

1

2

C129
22U_0805_6.3V6M

2

1

C87
22U_0805_6.3V6M

+

C90
22U_0805_6.3V6M

2

1

C91
22U_0805_6.3V6M

+

C164
330U_D2E_2.5VM_LESR9M

1

between Inductor and socket

C92
330U_D2E_2.5VM_LESR9M

2

2

C76
330U_D2E_2.5VM_LESR9M

1

1

C75
330U_D2E_2.5VM_LESR9M

2

2

C194
10U_0805_6.3V6M

1

1

C165
10U_0805_6.3V6M

2

2

C197
10U_0805_6.3V6M

1

1

C148
10U_0805_6.3V6M

2

2

C89
10U_0805_6.3V6M

1

1

C166
10U_0805_6.3V6M

2

2

C180
10U_0805_6.3V6M

1

1

C193
10U_0805_6.3V6M

2

2

C196
10U_0805_6.3V6M

1

1

C88
10U_0805_6.3V6M

2

2

C192
10U_0805_6.3V6M

1

1

C179
10U_0805_6.3V6M

2

C162
10U_0805_6.3V6M

1

C163
10U_0805_6.3V6M

IC,AUB_CFD_rPGA,R1P0
ME@

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

C580
22U_0805_6.3V6M

1
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

C585
22U_0805_6.3V6M

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

C195
10U_0805_6.3V6M

B

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

C147
10U_0805_6.3V6M

C

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

C568
22U_0805_6.3V6M

D

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

JCPU1I

Under cavity

VSS

NCTF

JCPU1H

1

PVT, change from 470uF 4.5mohm
to 330uF 6mohm and 2nd 470uF 7mohm by power;
'10 1/8 update main to 330uF 9m ohm

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

C

VSS_NCTF1_R
VSS_NCTF2_R
VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R
VSS_NCTF6_R
VSS_NCTF7_R

B

IC,AUB_CFD_rPGA,R1P0
ME@

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Arrandale(5/5)-GND/Bypass

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

9

of

50

5

http://hobi-elektronika.net
4

3

4BA2/6W

2

DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

C

7 DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

7 DDR_A_BS2

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

7 M_CLK_DDR0
7 M_CLK_DDR#0

M_CLK_DDR0
M_CLK_DDR#0

7 DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

7 DDR_A_WE#
7 DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

7 DDR_CS1_DIMMA#

DDR_A_MA13
DDR_CS1_DIMMA#

B

DDR_A_D34
DDR_A_D35

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA

7

C

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#

M_CLK_DDR1 7
M_CLK_DDR#1 7
DDR_A_BS1 7
DDR_A_RAS# 7

DDR_CS0_DIMMA#
M_ODT0
M_ODT1

DDR_CS0_DIMMA#
M_ODT0 7

7

M_ODT1 7

DDR_A_D36
DDR_A_D37

1

DDR_A_DM4
2

DDR_A_D38
DDR_A_D39

+VREF_DQ_DIMMA

1

2

Layout Note:
Place near DIMM

B

+1.5V

2

2

2

2

1

2

1

2

1

2

1
+

C569
220U_B2_2.5VM_R35

2

6*0603 10uf (PER CONNECTOR)

DDR_A_DM6

VTT(0.75V) =

DDR_A_D54
DDR_A_D55

3*0805 10uf

4*0402 1uf

VREF =

DDR_A_D60
DDR_A_D61

1*0402 0.1uf

DDR_A_DQS#7
DDR_A_DQS7

2

1

2

1

2

1

2

10U_0603_6.3V6M

2

1

C301

PM_EXTTS#1_R 5,11
SMB_DATA_S3 11,12,14,28
SMB_CLK_S3 11,12,14,28

1

1U_0603_10V6K

PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

1*0402 2.2uf

1U_0603_10V6K

1*0402 0.1uf

DDR_A_D62
DDR_A_D63

+0.75VS

1*0402 2.2uf

VDDSPD (3.3V)=

A

+0.75VS

1/76BA1/86W

FOX_AS0A626-U4SN-7F
ME@

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1

C316
0.1U_0402_10V6K

2

1

C317
0.1U_0402_10V6K

2

1

C315
0.1U_0402_10V6K

2

1

C314
0.1U_0402_10V6K

2

1

C308

@

1

10U_0603_6.3V6M

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)

DDR_A_D52
DDR_A_D53

2

1

10U_0603_6.3V6M

@

1

C570

VDDQ(1.5V) =

DDR_A_D46
DDR_A_D47

1

C309

DDR_A_DQS#5
DDR_A_DQS5

10U_0603_6.3V6M

DDR_A_D44
DDR_A_D45

C300

1

DDR_A_D30
DDR_A_D31

10U_0603_6.3V6M

2

DDR_A_DQS#3
DDR_A_DQS3

C606

206

DDR_A_D28
DDR_A_D29

C310

G2

DDR_A_D22
DDR_A_D23

1U_0603_10V6K

G1

DDR_A_DM2

C607

205

For Arranale only +VREF_DQ_DIMMA
supply from a external 1.5V voltage divide
circuit.
07/17/2009

DDR_A_D20
DDR_A_D21

1U_0603_10V6K

2

R571
10K_0402_5%

2

1

C617
0.1U_0402_10V6K

1

C608
2.2U_0603_6.3V6K

+3VS
A

5,11

C605

DDR_A_D58
DDR_A_D59
1 R570
2
10K_0402_5%

DRAMRST#

DDR_A_D14
DDR_A_D15

10U_0603_6.3V6M

DDR_A_DM7

DDR_A_DM1
DRAMRST#

C581

DDR_A_D56
DDR_A_D57

D

R305
1K_0402_1%

DDR_A_D12
DDR_A_D13

C586

DDR_A_D50
DDR_A_D51

DDR_A_D6
DDR_A_D7

10U_0603_6.3V6M

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_DQS#0
DDR_A_DQS0

C588

DDR_A_D48
DDR_A_D49

+VREF_DQ_DIMMA

7 DDR_A_MA[0..15]

10U_0603_6.3V6M

DDR_A_D42
DDR_A_D43

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

R297
1K_0402_1%

7 DDR_A_DQS#[0..7]

C589

DDR_A_DM5

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

7 DDR_A_DQS[0..7]

DDR_A_D4
DDR_A_D5

10U_0603_6.3V6M

DDR_A_D40
DDR_A_D41

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C355
2.2U_0603_6.3V6K

DDR_A_DQS#4
DDR_A_DQS4

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C346
0.1U_0402_10V6K

DDR_A_D32
DDR_A_D33

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

1

C347
2.2U_0603_6.3V6K

2
D

C303
0.1U_0402_10V6K

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+1.5V

7 DDR_A_DM[0..7]

2

JDIMM1
DDR_A_D0
DDR_A_D1

1

7 DDR_A_D[0..63]

DDR3 SO-DIMM A
+VREF_DQ_DIMMA

2

+1.5V

1

+1.5V

2

+VREF_DQ_DIMMA

4

3

2

Title

Compal Electronics, Inc.
DDRIII-SODIMM SLOT1

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

10

of

50

http://hobi-elektronika.net

5

4

+VREF_DQ_DIMMB

+1.5V

4BA2/6W

3

+1.5V

2

1

7 DDR_B_DQS#[0..7]
7 DDR_B_D[0..63]

2

DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27

C

7 DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

7 DDR_B_BS2

DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

7 M_CLK_DDR2
7 M_CLK_DDR#2

M_CLK_DDR2
M_CLK_DDR#2

7 DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

7 DDR_B_WE#
7 DDR_B_CAS#

DDR_B_WE#
DDR_B_CAS#

7 DDR_CS3_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#

1

7

C

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 7
M_CLK_DDR#3 7

DDR_B_BS1
DDR_B_RAS#

Layout Note:
Place near DIMM

DDR_B_BS1 7
DDR_B_RAS# 7

DDR_CS2_DIMMB#
M_ODT2
M_ODT3

DDR_CS2_DIMMB#
M_ODT2 7

7

M_ODT3 7

+VREF_DQ_DIMMB
+1.5V

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

C306
0.1U_0402_10V6K

DDR_B_DQS#5
DDR_B_DQS5

2

@

C305
0.1U_0402_10V6K

DDR_B_D44
DDR_B_D45

1

C304
0.1U_0402_10V6K

@

C312

2

C575

2

DDR_B_D38
DDR_B_D39

1

C307
0.1U_0402_10V6K

1

DDR_B_DM4

10U_0603_6.3V6M

DDR_B_D36
DDR_B_D37

10U_0603_6.3V6M

206

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

C590

G2

DDR_CKE3_DIMMB

10U_0603_6.3V6M

G1

DDR_B_D30
DDR_B_D31

B

VDDQ(1.5V) =

DDR_B_D46
DDR_B_D47

3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)

DDR_B_D52
DDR_B_D53

Layout Note:
Place near DIMM

VTT(0.75V) =

DDR_B_DM6

3*0805 10uf

DDR_B_D54
DDR_B_D55

4*0402 1uf
+0.75VS

DDR_B_D60
DDR_B_D61

1*0402 0.1uf

1*0402 2.2uf

VDDSPD (3.3V)=

DDR_B_DQS#7
DDR_B_DQS7

1*0402 0.1uf

1*0402 2.2uf
1

DDR_B_D62
DDR_B_D63
PM_EXTTS#1_R
SMB_DATA_S3
SMB_CLK_S3

1/76BA1/86W

2
PM_EXTTS#1_R 5,10
SMB_DATA_S3 10,12,14,28
SMB_CLK_S3 10,12,14,28
+0.75VS

1

2

1

2

1

2

C598
1U_0603_10V6K

2

205

DDR_B_DQS#3
DDR_B_DQS3

C313

2

1

1 R572
2
10K_0402_5%
1
2
R573 10K_0402_5%

DDR_B_D28
DDR_B_D29

C299
1U_0603_10V6K

1

C616
0.1U_0402_10V6K

+3VS

C618
2.2U_0603_6.3V6K

A

DDR_B_D22
DDR_B_D23

C595
1U_0603_10V6K

DDR_B_D58
DDR_B_D59

For Arranale only +VREF_DQ_DIMMB
supply from a external 1.5V voltage divide
circuit.
07/17/2009

DDR_B_DM2

C596
1U_0603_10V6K

DDR_B_DM7

DDR_B_D20
DDR_B_D21

10U_0603_6.3V6M

DDR_B_D56
DDR_B_D57

5,10

10U_0603_6.3V6M

DDR_B_D50
DDR_B_D51

DRAMRST#

DDR_B_D14
DDR_B_D15

C311

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_DM1
DRAMRST#

C576

DDR_B_D48
DDR_B_D49

R340
1K_0402_1%

10U_0603_6.3V6M

DDR_B_D42
DDR_B_D43

+VREF_DQ_DIMMB

D

DDR_B_D12
DDR_B_D13

C587

DDR_B_DM5

DDR_B_D6
DDR_B_D7

10U_0603_6.3V6M

DDR_B_D40
DDR_B_D41

R341
1K_0402_1%

7 DDR_B_MA[0..15]

DDR_B_DQS#0
DDR_B_DQS0

C582

DDR_B_D34
DDR_B_D35

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D4
DDR_B_D5

10U_0603_6.3V6M

B

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

7 DDR_B_DQS[0..7]

C383
2.2U_0603_6.3V6K

DDR_B_DQS#4
DDR_B_DQS4

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C385
0.1U_0402_10V6K

DDR_B_D32
DDR_B_D33

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

C384

C382

2

DDR_B_D0
DDR_B_D1

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

0.1U_0402_10V6K

2.2U_0603_6.3V6K

D

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

+VREF_DQ_DIMMB

+1.5V

7 DDR_B_DM[0..7]

JDIMM2

A

FOX_AS0A626-U4RN-7F
ME@

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
DDRIII-SODIMM SLOT2

Size

Document Number

Rev
0.3

LA-5941P
Date:

Sheet

Thursday, April 08, 2010
1

11

of

50

http://hobi-elektronika.net

5

4

3

2

1

Reserve for Low Power CLK GEN.
RTM890N-632
SLG8LV597VTR
+3VS_CK505

VDD_3V3_1V5

1
0_0603_5%

2
R278

@

+1.5VS

1 PCS CAP(0.1u) BY 1 INPUT PIN

D

1
0_0603_5%

1. 27M_CLK_SS

+3VS_CK505

1

2

+1.05VS_CK505

1

2

C330
0.1U_0402_10V6K

1. 27M_CLK

2. CLK_BUF_BCLK

2

C334
0.1U_0402_10V6K

CLK GEN TO VGA

1. CLK_DMI

1

C366
0.1U_0402_10V6K

2

C336
10U_0805_6.3V6M

1

CLK GEN TO PCH

D

VDD_3V3_1V5

2
R269

+3VS_CK505

+1.05VS_CK505

U14

3. CLK_BUF_CKSSCD
VDD_3V3_1V5

4. CLK_BUF_DOT96
5. CLK_14M_PCH

CLK_BUF_DOT96
CLK_BUF_DOT96#

14 CLK_BUF_DOT96
14 CLK_BUF_DOT96#

R318
1
1
R319

0_0402_5%
L_CLK_BUF_DOT96
L_CLK_BUF_DOT96#

2
2
0_0402_5%

CLK_48M_CR_R

1
2
3
4
5
6
7
8

VDD_USB_48
VSS_48M
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
USB_48

9
10
11
12
13
14
15
16

VSS_27M
SATA
SATA#
VSS_SRC
SRC_1
SRC_1#
VDD_SRC_IO
CPU_STOP#

33

TGND

CLOSE U27
14 CLK_BUF_CKSSCD
14 CLK_BUF_CKSSCD#

C

14
14

CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#

R324
R308

1
1

CLK_DMI
CLK_DMI#

R307
R306

1
1

R299

1

CLK_DMI
CLK_DMI#

+3VS_CK505

CLK_BUF_CKSSCD_R
2 0_0402_5%
CLK_BUF_CKSSCD#_R
2
0_0402_5%
2 0_0402_5% L_CLK_DMI
L_CLK_DMI#
2
0_0402_5%
CPU_STOP#
2
10K_0402_5%

SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#

32
31
30
29
28
27
26
25

SMB_CLK_S3
SMB_DATA_S3
REF_0/CPU_SEL

VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC

24
23
22
21
20
19
18
17

VDD_3V3_1V5
R275
R_CLK_BUF_BCLK
1
R_CLK_BUF_BCLK#
1
R276

2

1 R315 CLK_14M_PCH
33_0402_1%

SMB_CLK_S3 10,11,14,28
SMB_DATA_S3 10,11,14,28
CLK_14M_PCH 14

CLK_XTAL_IN
CLK_XTAL_OUT
CK_PWRGD
0_0402_5%
2 CLK_BUF_BCLK
2 CLK_BUF_BCLK#
0_0402_5%

CLK_BUF_BCLK 14
CLK_BUF_BCLK# 14

C

VDD_3V3_1V5

RTM890N-631-VB-GRT_QFN32_5X5
CK_PWRGD

2
R277
1

2

1

2

1

2

C335
0.1U_0402_10V6K

2

C343
0.1U_0402_10V6K

1

C332
0.1U_0402_10V6K

2

C331
10U_0805_6.3V6M

C333
10U_0805_6.3V6M

1

2

+3VS_CK505

1

SA00003HQ10 S IC RTM890N-631-VB-GRT QFN 32P CLK GEN
(SA00003HR00)S IC ICS9LVS3199AKLFT MLF 32P CLK GEN
S IC SLG8SP587VTR QFN 32P CLK GEN (SA00002XY00)

1 PCS CAP(0.1u) BY 1 INPUT PIN
1
0_0603_5%

R298 1

10K_0402_5%

+1.05VS_CK505

D

2
G

CLK_EN#

48

Q25 S
2N7002_SOT23-3

3

+1.05VS

1

2

C1212
47P_0402_50V8J

CLK_48M_CR_R

2
0_0402_5%

1
R323
@

PIN8 IS GND FOR ICS3197
PIN8 IS 48MHz FOR ICS3199

RF 10/22

B

B

+3VS

+3VS_CK505
C364 2

1 PCS CAP(0.1u) BY 1 INPUT PIN
1
0_0603_5%

CLK_14M_PCH
1
@ 10P_0402_50V8J
CLK_XTAL_OUT

2
R279

2

1

2

C367
0.1U_0402_10V6K

2

1

C350
0.1U_0402_10V6K

1

C342
0.1U_0402_10V6K

2

C344
10U_0805_6.3V6M

1

CLK_XTAL_IN
1

2

C1213
47P_0402_50V8J

C365

2

1 REF_0/CPU_SEL
10P_0402_50V8J

EMI Capacitor

Y1
14.318MHZ_20PF_7A14300003
2
1

SVT RF

RF 10/22

C348
27P_0402_50V8J

1

1

2

2

C349
27P_0402_50V8J

+1.05VS

PIN 30

CPU_0

CPU_1

0 (Default)

133MHz

133MHz

1

100MHz

100MHz

PVT, resize 5032, CL27pF
1
R317

2
@ 10K_0402_5%

1
R316

2
10K_0402_5%

REF_0/CPU_SEL

A

A

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
CLOCK GENERATOR

Size

Document Number

Rev
0.3

LA-5941P
Date:

Sheet

Thursday, April 08, 2010
1

12

of

50

http://hobi-elektronika.net

5

4

3

2

1

PCH_RTCX1

1
R154

1

4

2

3

X1
32.768KHZ_12.5P_MC-146

D

C183
15P_0402_50V8J

*

0.1U_0402_16V4Z

H
L

Κ
VRM enable
ΚIntegrated
Integrated VRM disable

+3VS

RF 1103 add

@

33 HDA_BITCLK_CODEC

PCH_SPKR
2
1K_0402_5%

33

CLRP2
SHORT PADS

C

2

2

BITCLK

A30

2 33_0402_5%

HDA_SYNC

D29

PCH_SPKR

P1

HDA_RST#

C30

HDA_RST#

HDA_SDIN0

G30

HDA_SDIN0

HDA_SDIN1_R

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

R169 1

2 33_0402_5%
0_0402_5%
@
1
2
0_0402_5%
1
2

R677
33

C1222
12P_0402_50V8J
@

HDA_SDIN1

HDA_SDIN1

SVT

33 HDA_SDOUT_CODEC
34

flash ME core of strap pin pull down

R166 1

2 33_0402_5%
R409 1
R425 1

ME_FLASH
R424 1

+3VALW

C34

LDRQ0#
LDRQ1# / GPIO23

A34
F34

GPIO23

SERIRQ

AB9

SERIRQ

LPC_FRAME#
T7

2
2

1K_0402_5%
0_0402_5%
GPIO13

SPKR

28,34

PAD

+3VS

GPIO23 = NATIVE,3.3V,CORE
SERIRQ

34

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AK7
AK6
AK11
AK9

SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AH6
AH5
AH9
AH8

SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF11
AF9
AF7
AF6

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AH3
AH1
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AD9
AD8
AD6
AD5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AD3
AD1
AB3
AB1

1
R479

0.01U_0402_16V7K
0.01U_0402_16V7K

1 C140
1 C141

2
2

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_DTX_C_IRX_N0 32
SATA_DTX_C_IRX_P0 32
SATA_ITX_DRX_N0 32
SATA_ITX_DRX_P0 32

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1

SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1

SATA_DTX_C_IRX_N4
SATA_DTX_C_IRX_P4
SATA_ITX_C_DRX_N4
SATA_ITX_C_DRX_P4

0.01U_0402_16V7K
0.01U_0402_16V7K

2
2

M3

JTAG_TCK

PCH_JTAG_TMS

K3

JTAG_TMS

PCH_JTAG_TDI

K1

JTAG_TDI

PCH_JTAG_TDO

J2

JTAG_TDO

PCH_JTAG_RST#

J4

TRST#

SPI_CLK_PCH_R

BA2

SPI_CLK

SPI_SB_CS0#

AV3

SPI_CS0#

AY3

SPI_CS1#

SATALED#

T3

SPI_SI

AY1

SPI_MOSI

SATA0GP / GPIO21

Y9

GPIO21

GPIO21

SPI_SO_R

AV1

SATA1GP / GPIO19

V1

GPIO19

GPIO19

AF16

SATAICOMPI

AF15

SSD

R500
SATAICOMP 1
2
37.4_0402_1%

SATA_DTX_C_IRX_N4 37
SATA_DTX_C_IRX_P4 37
SATA_ITX_DRX_N4_CONN
SATA_ITX_DRX_P4_CONN

C142 SATA_ITX_DRX_N4_CONN
C143 SATA_ITX_DRX_P4_CONN

1
1

PCH_JTAG_TCK

SATAICOMPO

28
28
28
28

HDD

C

SPI_CLK_PCH

1

2
0_0402_5%

PCH_JTAG_RST#

1
R453

2
10K_0402_5%

+3VS

R447
10K_0402_5%

HDD_LED#

R482
10K_0402_5%

38

@
R118
10K_0402_5%

B

GPIO21 = GPI,3.3V,CORE
SPI_MISO

GPIO19 = GPI,3.3V,CORE

1

SPI_CLK_PCH

SA00003N7A0 (MP)

PCH Pin

RefDes

ES1

PCH_JTAG_TDO

ES2

*

PCH_JTAG_TCK

R114 1

2 51_0402_5%

(2009,05,04)
R62

MP

R591

No Install

200ohm

No Install

R590

No Install

100ohm

No Install

1

2 SPI_WP#
3.3K_0402_5%

R102 1

2SPI_HOLD#
3.3K_0402_5%

FOR INTEL DPDG REV1.6 (MAY 2009)

+3VS

200ohm

R584

200ohm

No Install

R583

100ohm

100ohm

No Install

R587

200ohm

200ohm

No Install

PCH_JTAG_TDI

R586

100ohm

100ohm

No Install

PCH_JTAG_TCK

R580

PCH_JTAG_TMS

SPI_SB_CS0#
SPI_SO_R

U3
1 SPI_SO_L
R101
SPI_WP#
15_0402_5%

2

A

PCH_JTAG_RST#

51ohm

51ohm

20Kohm

20Kohm

No Install

R594

10Kohm

10Kohm

No Install

5

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

2

2
0.1U_0402_16V4Z

SPI_HOLD#
SPI_CLK_PCH
SPI_SI
A

MX25L3205DM2I-12G_SO8

51ohm

R595

1
2
3
4

C138
22P_0402_50V8J
@

C460
1

R103
15_0402_5%
1
2

R100
33_0402_5%
@

4M SPI ROM FOR HM55
(ME code & BIOS code)
SA000021A00 MXIC
SA00003K800 Winbond
SA00003IN00 E-ON

+3VS

PCH JTAG
Production

E-SATA

R99

@
R75
20K_0402_5%

IBEXPEAK-M_FCBGA1071

PCH JTAG
Pre-Production

37
37

+3VS

+1.05VS

1

2
1
1

1

HDA_SDOUT

HDA_SYNC

2

@
R116
100_0402_1%

2

@
R115
100_0402_1%

PCH_JTAG_TDI

FWH4 / LFRAME#

HDA_BCLK

GPIO13 = GPI,3.3V,SUS

+3VALW

@
R73
200_0402_5%

2

PCH_JTAG_TMS

1

1
2
1

@
R117
100_0402_1%

@
R72
200_0402_5%

2

1
2
1

PCH_JTAG_TDO

2

B

@
R74
200_0402_5%

+3VALW

@

2 10K_0402_5%
@

(2009,07,07)
+3VALW

INTVRMEN

2 33_0402_5%

GPIO33 = GPO , internal pull-up,should not be pulled low

+3VALW

A14

R167 1

R676
HDA_SDOUT_CODEC
1
C1221
12P_0402_50V8J
@

PCH_INTVRMEN

R168 1

PCH_SPKR

33 HDA_RST_CODEC#

HDA_BITCLK_CODEC

1

INTRUDER#

2
10K_0402_5%

33 HDA_SYNC_CODEC
1
R452

2

A16

28,34
28,34
28,34
28,34

2

C441

C202
1U_0603_10V6K

PCH_INTVRMEN

SRTCRST#

SM_INTRUDER#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1

1

R420 1

2

100_0603_1%

RTCRST#

D17

D33
B33
C32
A32

2

R144
1
2

SM_INTRUDER#

C14

PCH_SRTCRST#

IHDA

2
1M_0402_5%
2
330K_0402_5%

PCH_RTCRST#

LAD0
LAD1
LAD2
LAD3

FWH0 /
FWH1 /
FWH2 /
FWH3 /

SATA

R421 1

1

RTCX1
RTCX2

LPC

+RTCVCC

B13
D13

JTAG

+RTCBATT

2

PCH_RTCX1
PCH_RTCX2

CLRP3
SHORT PADS

SPI

+RTCVCC

1

C184
1U_0603_10V6K
1
2
R419 20K_0402_1%
1
2
R422 20K_0402_1%

RTC

+RTCVCC

PVT

1

U7A

2

2 EPSON Q13MC1461005000 2
6.9x1.4x1.3mm

1

C171
15P_0402_50V8J

1

2

1
D

PCH_RTCX2

2
10M_0402_5%

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

Compal Electronics, Inc.
IBEX-M(1/6)-HDA/JTAG/SATA

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

13

of

50

http://hobi-elektronika.net

5

4

DEVICE
NEW CARD
WLAN
LAN
3G
X
X
X
X

EC_LID_OUT#

PCIE_PRX_DTX_N2 AW30
PCIE_PRX_DTX_P2 BA30
PCIE_PTX_DRX_N2 BC30
PCIE_PTX_DRX_P2 BD30

PERN2
PERP2
PETN2
PETP2

WLAN

PERN3
PERP3
PETN3
PETP3

LAN

2 0.1U_0402_10V6K
2 0.1U_0402_10V6K
3G@
3G@

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

AU30
AT30
AU32
AV32

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

BA32
BB32
BD32
BE32

PERN4
PERP4
PETN4
PETP4

BF33
BH33
BG32
BJ32

PERN5
PERP5
PETN5
PETP5

BA34
AW34
BC34
BD34

PERN6
PERP6
PETN6
PETP6

AT34
AU34
AU36
AV36
BG34
BJ34
BG36
BJ36

10/6 Remove Express card CLK
R431 1

2 10K_0402_5%

SMBDATA

AK48
AK47
GPIO73

P9

R220 1
R221 1

2 0_0402_5%
2 0_0402_5%

R113 1

2 10K_0402_5%

R223 1 3G@
R222 1 3G@

2 0_0402_5% CLK_PCIE_CARD_PCH#_R
2 0_0402_5% CLK_PCIE_CARD_PCH_R

AM47
AM48
N4

+3VALW

R120 1

+3VALW

R435 1

AH42
AH41

2 10K_0402_5%

2 10K_0402_5%

GPIO26

M9

GPIO26 = NATIVE,3.3V,SUS
AJ50
AJ52
R434 1

2 10K_0402_5%

GPIO44

H6

GPIO44 = NATIVE,3.3V,SUS
AK53
AK51

+3VALW

SML0CLK

SML0CLK

SML0DATA

G8

SML0DATA

CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

SMB_DATA_S3

10,11,12,28

2N7002DW-T/R7_SOT363-6
Q8B

SML1ALERT# / GPIO74

M14

GPIO74

SML1CLK / GPIO58

E10

SML1CLK

R79

0_0402_5%

EC_SMB_CK2

EC_SMB_CK2

31,34

SML1DATA / GPIO75

G12

SML1DATA

R80

0_0402_5%

EC_SMB_DA2

EC_SMB_DA2

31,34

SMBCLK

1

R122
0_0402_5%
@ 2

SMBDATA

1

@ 2

SMB_CLK_S3
SMB_DATA_S3

0_0402_5%
R119

EC_THERMAL

DTS , read from EC
CL_CLK1

T13

CL_DATA1

T11

CL_RST1#

T9

PEG_A_CLKRQ# / GPIO47

H1

C

PEG_CLKREQ#
10K_0402_5%
PEG_CLKREQ#
1

R412
2

19

@

GPIO47 = 10Kohm PULL DOWN

PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

DDR3*2 AND CLK GEN
SMB_DATA_S3

4

GPIO74 = NATIVE,3.3V,SUS

MINI1

10,11,12,28

AD43
AD45

CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R

R524 1
R525 1

2 0_0402_5%
2 0_0402_5%

CLKOUT_DMI_N
CLKOUT_DMI_P

AN4
AN2

CLK_EXP#_R
CLK_EXP_R

R105 1
R106 1

2 0_0402_5%
2 0_0402_5%

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AT1
AT3

CLKOUT_DP_N
CLKOUT_DP_P

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLK_PCIE_VGA#
CLK_PCIE_VGA

19
19

CLK_EXP# 5
CLK_EXP 5
+3VS_DELAY

T24 PAD
T25 PAD

Nvidia Thermal sensor

+3VS_DELAY

AW24
BA24

CLK_DMI# 12
CLK_DMI 12

CLKIN_BCLK_N
CLKIN_BCLK_P

AP3
AP1

CLK_BUF_BCLK# 12
CLK_BUF_BCLK 12

CLKIN_DOT_96N
CLKIN_DOT_96P

F18
E18

CLK_BUF_DOT96# 12
CLK_BUF_DOT96 12

AH13
AH12

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLKIN_DMI_N
CLKIN_DMI_P

HYBRID@
Q7A
6

EC_SMB_DA2

EC_SMB_CK2
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

PCIECLKRQ2# / GPIO20

CLK_PCIE_VGA#
CLK_PCIE_VGA

R124
2.2K_0402_5%
HYBRID@

12
12

HYBRID@
Q7B
3

R82
2.2K_0402_5%
HYBRID@
SMB_EC_DA2_R

1

SMB_EC_DA2_R

19

SMB_EC_CK2_R

19

2N7002DW-T/R7_SOT363-6
SMB_EC_CK2_R

4

B

2N7002DW-T/R7_SOT363-6

CLKOUT_PCIE3N
CLKOUT_PCIE3P
PCIECLKRQ3# / GPIO25

REFCLK14IN

P41

CLK_14M_PCH

CLKIN_PCILOOPBACK

J42

CLK_PCI_FB

XTAL25_IN
XTAL25_OUT

AH51
AH53

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

AF38

R491

CLK_14M_PCH
CLK_PCI_FB

12
16

GPIO25 = NATIVE,3.3V,SUS
AM51
AM53

+3VALW

D

GPIO20 = NATIVE,3.3V,CORE

A8

28 PCIECLKREQ3#

GPIO60

C6

SMB_CLK_S3

R457 1

2 10K_0402_5%

GPIO56

P13

CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56

GPIO56 = NATIVE,3.3V,SUS

CLKOUTFLEX0 / GPIO64

T45

CLKOUTFLEX1 / GPIO65

P43

1

2 90.9_0402_1%

+1.05VS

R198
1

XTAL25_OUT
2 22_0402_5%
@

CLKOUTFLEX2 / GPIO66

T42

CLKOUTFLEX3 / GPIO67

N50

XTAL25_IN

EMI REQUEST 0303
CLK_PCI_DB_R

CLK_PCI_DB

28

CLK_PCI_FB

GPIO67

T9

IBEXPEAK-M_FCBGA1071

2

1

A

2
1M_0402_5%
Y4

R209
22_0402_5%
@

PAD

For CR 48M CLK

1
R598

CLK_14M_PCH
1

2

28 CLK_PCIE_CARD_PCH#
28 CLK_PCIE_CARD_PCH

3

SMB_CLK_S3

1

2N7002DW-T/R7_SOT363-6
Q8A

R413
22_0402_5%

2
C263
10P_0402_50V8J
@

1

2

25MHZ_20PF_7A25000012

SVT
RF

1

+3VS

SMBDATA

J14

SML0ALERT# / GPIO60

GPIO18 = NATIVE,3.3V,CORE
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

C8

6

GPIO11 = NATIVE,3.3V,SUS

2

29 CLK_PCIE_LAN#
29 CLK_PCIE_LAN
29 CLKREQ_LAN#

3G

2 10K_0402_5%

SMBCLK

1

+3VS

LAN

R454 1

AM43
AM45
U4

28 WLAN_CLKREQ1#

B

2 0_0402_5% CLK_PCIE_WLAN1#_R
2 0_0402_5% CLK_PCIE_WLAN1_R

LID_OUT#

GPIO60 = NATIVE,3.3V,SUS

GPIO73 = NATIVE,3.3V,SUS
R196 1
R197 1

B9
H14

2

C231 1
C232 1

2 0.1U_0402_10V6K
2 0.1U_0402_10V6K

SMBCLK

5

C223 1
C222 1

SMBALERT# / GPIO11

NEW CARD

SMBus

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

2 0.1U_0402_10V6K
2 0.1U_0402_10V6K

C

WLAN

+3VALW

2

PERN1
PERP1
PETN1
PETP1

Link

29
29
29
29

28 CLK_PCIE_WLAN1#
28 CLK_PCIE_WLAN1

GPIO74
LID_OUT#

5

BG30
BJ30
BF29
BH29

Controller

C230 1
C229 1

+3VALW

SML0DATA

2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

R407
0_0402_5%

PEG

3G

SML0CLK

34

U7B

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

SMBDATA

GPIO60

28
28
28
28

28
28
28
28

1
R123
1
R78
1
R148
1
R147
1
R404
1
R403
1
R399
1
R145
1
R400

SML1DATA

PCI-E*

LAN

SMBCLK

+3VS

+3VS

10/6 Remove Express card

WLAN

1

2
10K_0402_5%
2
10K_0402_5%

SML1CLK

From CLK BUFFER

D

1
R121
1
R406

SMB_DATA_S3

Clock Flex

1
2
3
4
5
6
7
8

2

SMB_CLK_S3

PCIE PORT LIST
PORT

3

1

C439
10P_0402_50V8J

2

C630
27P_0402_50V8J
C631
27P_0402_50V8J

1

2
A

18->27pF, PVT
Y4 resize 5032

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
IBEX-M(2/6)-PCI-E/SMBUS/CLK

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

14

of

50

http://hobi-elektronika.net

5

4

3

2

1

D

D

BH25
DMI_IRCOMP
2
49.9_0402_1%

1
R520

BF25

DMI_ZCOMP

FDI_INT
FDI_FSYNC0
FDI_FSYNC1

DMI_IRCOMP
FDI_LSYNC0

4mil width and place
within 500mil of the PCH

Κ

6
6
6
6
6
6
6
6

FDI_LSYNC1

BJ14

FDI_INT

BF13

FDI_FSYNC0

FDI_INT

BH13

FDI_FSYNC1

BJ12

FDI_LSYNC0

BG14

FDI_LSYNC1

6
6

FDI_LSYNC0

6

FDI_LSYNC1

6

2

0.01U_0402_16V7K
1

2

1

1K_0402_5%
2

SYS_RST#

T6

@

2 0_0402_5%

SYS_PWROK M6

SYS_RESET#

WAKE#

SYS_PWROK

CLKRUN# / GPIO32

R397 1

@

2 0_0402_5%

2

ICH_POK

B17
R455
0_0402_5%

1

(2009,05,04)
R146

2 10K_0402_5%A10

1

PM_DRAM_PWRGD D9

5 PM_DRAM_PWRGD

C16

2 10K_0402_5% SUS_PWR_DN_ACK_R M1
2
0_0402_5%
PBTN_OUT#P5

R437 1

1
R599

34 SUS_PWR_DN_ACK
+3VALW

J12

PCIE_WAKE#

34 PBTN_OUT#

1
2
34 AC_PRESENT

BB47
BA52
AY48
AV47

27 LVDS_A0
27 LVDS_A1
27 LVDS_A2

BB48
BA50
AY49
AV48

PWROK
MEPWROK

C1214
12P_0402_50V8J
@

LAN_RST#
DRAMPWROK
RSMRST#

10K_0402_5%

1
R451

2 AC_PRESENT_R
0_0402_5%

P7

ACPRESENT / GPIO31

CLKRUN#

34

PVT

1

2

2

C1215
12P_0402_50V8J
@

SUSCLK / GPIO62

F3

SUSCLK

SLP_S5# / GPIO63

E4

PM_SLP_S5# 34

SLP_S4#

H7

PM_SLP_S4# 34

1

SLP_S3#
SLP_M#
TP23

2

8.2K_0402_1%

GPIO72

A6

BATLOW# / GPIO72

PMSYNCH

GPIO30 = GPI,3.3V,SUS
R165

1

2

10K_0402_5%

F14

P12
K8

SUSCLK 34

DAC_BLU
DAC_GRN
DAC_RED

26 DAC_BLU
26 DAC_GRN
26 DAC_RED

PM_SLP_S3# 34

26 CRT_HSYNC
26 CRT_VSYNC

R688 UMA@ 33_0402_1%
HSYNC
2
1
VSYNC
2
1
R687 UMA@ 33_0402_1%
SVT

R688

N2

RI#

SLP_LAN# / GPIO29

BJ10

R687

3
G

2

Y
B

5

V51
V53
Y53
Y51

CRT_IREF AD48
AB51

4

SDVO_STALLN
SDVO_STALLP

BJ48
BG48

SDVO_INTN
SDVO_INTP

BF45
BH45

SDVO_CTRLCLK
SDVO_CTRLDATA

LVDSA_CLK#
LVDSA_CLK

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA

BG44
BJ44
AU38
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

R510
2

100K_0402_5%
1
+3VS

R504
2.2K_0402_5%
UMA@

R503
2.2K_0402_5%
UMA@

Y49
AB49

HDMICLK_NB
HDMIDAT_NB

HDMICLK_NB
HDMIDAT_NB

25
25
C

DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA

BE44
BD44
AV40

TMDS_B_HPD 25

BE40 TMDS_B_DATA2#_PCH
BD40 TMDS_B_DATA2_PCH
BF41 TMDS_B_DATA1#_PCH
BH41 TMDS_B_DATA1_PCH
BD38 TMDS_B_DATA0#_PCH
BC38 TMDS_B_DATA0_PCH
BB36 TMDS_B_CLK#_PCH
BA36 TMDS_B_CLK_PCH

C638
C639
C640
C641
C642
C643
C644
C645

2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K
2UMA@ 0.1U_0402_10V6K

1
1
1
1
1
1
1
1

TMDS_B_DATA2# 25
TMDS_B_DATA2 25
TMDS_B_DATA1# 25
TMDS_B_DATA1 25
TMDS_B_DATA0# 25
TMDS_B_DATA0 25
TMDS_B_CLK# 25
TMDS_B_CLK 25

U50
U52

HDMI
SVT

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

CRT_DDC_CLK
CRT_DDC_DATA

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

T51
T53

BC46
BD46
AT38

R675
2

100K_0402_5%
1

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

IBEXPEAK-M_FCBGA1071

If CRT DAC is not used then
a 5% resistor can be used.
(checklist 1.6)

22_0402_5% 22_0402_5%
HYBRID@
HYBRID@
SD028220A80 SD028220A80

B

CRT OUT

SYS_PWROK

RSMRST circuit

U28

@ R402
0_0402_5%
2

1

DAC_BLU

R493

1

2 150_0402_1%

DAC_GRN

R495

1

2 150_0402_1%

DAC_RED

R494

1

2 150_0402_1%

+3VS
E

BAV99DW-7_SOT363

1 2

2

4

B

5

+3VS

PM_RSMRST#
1
Q14
MMBT3906_SOT23-3
1
2
+3VALW
R176
4.7K_0402_5%

C

3

34 EC_RSMRST#

Reserved
(2009,09,08)

SDVO_TVCLKINN
SDVO_TVCLKINP

LVD_VREFH
LVD_VREFL

NC7SZ08P5X_NL_SC70-5

P

ICH_POK

A

5

1

H_PM_SYNC

GPIO29 = GPO,3.3V,SUS
If not using integrated
LAN,signal may be left as NC.

F6

AA52
AB53
AD53

CRT_DDC_CLK
CRT_DDC_DATA

26 CRT_DDC_CLK
26 CRT_DDC_DATA

Can be left NC when IAMT is
not support on the platfrom

IBEXPEAK-M_FCBGA1071

VGATE

LVD_IBG
LVD_VBG

GPIO62 = NATIVE,3.3V,SUS

2

R77

+3VALW

AY51
AT48
AU50
AT51

GPIO61 = NATIVE,3.3V,SUS

GPIO31 = GPI,3.3V,SUS
B

AY53
AT49
AU52
AT53

1

RF 10/22

GPIO61

SUS_PWR_DN_ACK / GPIO30
PWRBTN#

+3VS

P8

SUS_STAT# / GPIO61

AP48
AP47

LVDS_ACLK#
LVDS_ACLK

PCIE_WAKE# 28

SVT
1
2
R108 10K_0402_5% @
1
2
R180 0_0402_5%

Y1

AV53
AV51

R492
1K_0402_0.5%

R450

PM_RSMRST#

R401 2
1
10K_0402_5%

+3VALW

K5

System Power Management

R398 1

L_CTRL_CLK
L_CTRL_DATA

27 LVDS_A0#
27 LVDS_A1#
27 LVDS_A2#

+3VALW

GPIO32 = GPO,3.3V,CORE
34

LVDS_ACLK#
LVDS_ACLK

R436

VGATE

34,48

AB46
V48

AT43
AT42

1

MP

1

R396

R448
10K_0402_5%

L_DDC_CLK
L_DDC_DATA

PAD

27 LVDS_ACLK#
27 LVDS_ACLK

FDI_FSYNC1

AB48
Y45

AP39
AP41
T10
R502
2.37K_0402_1%

6

FDI_FSYNC0

2
2 10K_0402_5%
10K_0402_5%

+3VS

Checklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable

C

1 R497
1
R496

+3VS

L_BKLTCTL

1

+1.05VS

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

EDID_CLK
EDID_DATA

27 PCH_EDID_CLK
27 PCH_EDID_DATA

L_BKLTEN
L_VDD_EN

Y48

1

BD22
BH21
BC20
BD18

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

PCH_PWM

2

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

6
6
6
6

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

27

BJ46
BG46

2

BE22
BF21
BD20
BE18

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

27 PCH_ENBKL
27 PCH_ENVDD

Digital Display Interface

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

6 DMI_CRX_PTX_N0
6 DMI_CRX_PTX_N1
6 DMI_CRX_PTX_N2
6 DMI_CRX_PTX_N3

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

6
6
6
6
6
6
6
6

T48
T47

CRT

BD24
BG22
BA20
BG20

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

PCH_ENBKL
PCH_ENVDD

1

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

2

6
6
6
6

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI

DMI_CTX_PRX_N0 BC24
DMI_CTX_PRX_N1 BJ22
DMI_CTX_PRX_N2 AW20
DMI_CTX_PRX_N3 BJ20

DMI

6 DMI_CTX_PRX_N0
6 DMI_CTX_PRX_N1
6 DMI_CTX_PRX_N2
6 DMI_CTX_PRX_N3

U7D

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

LVDS

U7C

LVDS EDID
EDID_CLK

D8B

R458

2.2K_0402_5%

EDID_DATA R498

2.2K_0402_5%

1

3

R175

A

6

D8A
BAV99DW-7_SOT363
A

2

4.7K_0402_5%
PVT, Common design

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
IBEX-M(3/6)-DMI/LVDS/DP/PM

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P

Thursday, April 08, 2010

Sheet
1

15

of

50

http://hobi-elektronika.net

5

4

PCI_REQ0#
PCI_REQ1#
26,27 DGPU_SELECT#

PCI_REQ3#
PCI_GNT0#
PCI_GNT1#

C

27 DGPU_PWMSEL#

GPIO2
GPIO3
GPIO4
GPIO5
28,34

=
=
=
=

PCI_GNT3#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

GPI,5V,CORE
GPI,5V,CORE
GPI,5V,CORE
GPI,5V,CORE

F51
A46
B45
M53

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

F48
K45
F36
H53

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

R408 2

1 100K_0402_1%

PCI_SERR#
PCI_PERR#

PCIRST#

E44
E50

SERR#
PERR#

GNT2
PCI_IRDY#

Default-Internal pull up

*

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)

INTERNAL pull -H

PCI_DEVSEL#
PCI_FRAME#

A42
H44
F46
C46

IRDY#
PAR
DEVSEL#
FRAME#

PCI_LOCK#

D49

PLOCK#

PCI_STOP#
PCI_TRDY#

T26
PAD
PLT_RST#

R199
34
14

1
1

CLK_PCI_LPC
CLK_PCI_FB

R211

B

22_0402_5%
CLK_PCI_LPC_R
2
CLK_PCI_FB_R
2

D41
C48

STOP#
TRDY#

M7

PME#

D5

PLTRST#

N52
P53
P46
P51
P48

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

AU2
AV7

NV_WR#0_RE#
NV_WR#1_RE#

AY8
AY5

NV_WE#_CK0
NV_WE#_CK1

AV11
BF5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USBRBIAS#

B25

USBRBIAS

USBRBIAS

D25
N16
J16
F16
L16
E14
G16
F12
T15

RP3
1
2
3
4

8.2K_0804_8P4R_5%

USB20_N8
USB20_P8
USB20_N9
USB20_P9

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

USB20_N11
USB20_P11
USB20_N13
USB20_P13

1
R164

CARD READER

8.2K_0804_8P4R_5%

DGPU_PWR_EN

DGPU_HOLD_RST#

Bluetooth

1
2
3
4

2
22.6_0402_1%

@ 2 1K_0402_5%

PCI_GNT1#

R210 1

@ 2 1K_0402_5%

USB_OC#5

GPIO36

R627
1

@
0_0402_5%
2

GPIO0

R613
1

HYBRID@
0_0402_5%
2

R628
1

@
0_0402_5%
2

R609
1

24 DGPU_HPD_INT#

HYBRID@
0_0402_5%
2
@
0_0402_5%
2

R611
1

37
37

37

EDIDSEL#

HYBRID@
0_0402_5%
2

R612
1

0

1

1

0

PCI

8.2K_0804_8P4R_5%

1

1

SPI

8
7
6
5

GPIO16

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

2

GPIO37 AB13

2

GPIO38

2
2

SCLOCK / GPIO22
GPIO24

NV_ALE

@ R515 1

2 1K_0402_5%

@ R98

1

+3VS

2 1K_0402_5%

H_THERMTRIP#_L 1 R518
2
56_0402_5%
56 5%-->checklist 1.6
R519
54.9 1%-->CRB 1.0
56_0402_5%

SATA2GP / GPIO36

TP1

BA22

SATA3GP / GPIO37

TP2

AW22

SATACLKREQ# / GPIO35

SLOAD / GPIO38

TP3

P3

SDATAOUT0 / GPIO39

TP4

AY45

PCIECLKRQ6# / GPIO45

TP5

AY46

GPIO46

F1

PCIECLKRQ7# / GPIO46

TP6

AV43

GPIO48

AB6

SDATAOUT1 / GPIO48

TP7

AV45

AA4

SATA5GP / GPIO49

TP8

AF13

GPIO57

TP9

M18

TP10

N18

TP11

AJ24

TP12

AK41

TP13

AK42

TP14

M32

TP15

N32

TP16

M30

TP17

N30

TP18

H12

GPIO35

GPIO6

GPIO15

3
G
P

4

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

4

D

AA23

NC_1

AB45

NC_2

AB38

NC_3

AB42

NC_4

AB41

KB_RST#
5

H_THERMTRIP#

5

+VCCP

2

+3VALW

1
R405

DRAMRST_CNTRL_PCH
10K_0402_5%

C

T39

NC_5

P6

INIT3_3V#

INT3_3V#

USB PORT LIST

C10 TP24

TP24

GPIO1

R111
10K_0402_5%

1
2
3
4

DGPU_PWROK
2
10K_0402_5%

PORT

DEVICE

0
1
2
3
4
5
6
7
8
9
10
11
12
13

USB1
USB/ESATA
CMOS
USB2

B

1
R429
PVT, timing
1
2
R485
1K_0402_1%

8
7
6
5

1
R484

PCH_TEMP_ALERT#
2
10K_0402_5%

2
R107

1
10K_0402_5%

GPIO16

+3VS

@
1
R426

2
10K_0402_5%

EC_SCI#

+3VALW

@
1
R414

2
10K_0402_5%

EC_SMI#

+3VS

RP2
USB_OC#4
USB_OC#5_R
USB_OC#6
USB_OC#7

1
2
3
4

GPIO36

8
7
6
5

NV_ALE
Enable Intel Anti-Theft
Technology 8.2K PU to +3VS

Κ
Κ

Disable Intel Anti-Theft
Technology floating(internal PD)

CARD READER
X
X
WIRELESS
USB3
FingerPrint
BT
3G

0_0402_5%

1 R580

2

DGPU_PWROK

A

1

2

5

2

A

1

Compal Secret Data

Security Classification

DGPU_HOLD_RST#

Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

HYBRID@
NC7SZ08P5X_NL_SC70-5
R173
100K_0402_5%
HYBRID@

TP19

0.1U_0402_16V4Z
C687
@

B

Y

1

19 PLTRST_VGA#

34

BD10

STP_PCI# / GPIO34

H3

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

5

KB_RST#

THRMTRIP#

GPIO28

GPIO45

F8

H_PECI

H_CPUPWRGD

+3VS
U15

KB_RST#

BE10

45 VGA_PWROK

+3VS

H_PECI

GPIO39

GPIO16

+3VS

5
5

PVT

P

2

BG10
T1

DMI termination voltage.
weak internal PU, don't PD

PLT_RST#

G

U5
R155
100K_0402_5%
@

2

1

2

PECI

Title

3

2

Compal Electronics, Inc.
IBEX-M(4/6)-PCI/USB/GPIO

3

0.1U_0402_16V4Z
C646

Low=A16 swap
override/Top-Block
PCI_GNT3# Swap Override enabled
High=Default *

1

B

CLK_CPU_BCLK

8.2K_0804_8P4R_5%

Weak internal
PU,Do not pull low

A

AM1

DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW

*

22_0402_5%

Y

CLK_CPU_BCLK#

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

BB22

5

4

BUF_PLT_RST#
1

5,28,29

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

34

PROCPWRGD

NV_CLE
NC7SZ08P5X_NL_SC70-5

GATEA20

AM3

RCIN#

GPIO27

8.2K_0804_8P4R_5%

2

2 1K_0402_5%

U2

V3

+1.8VS

NV_CLE

5

A20GATE

GPIO15

*

8.2K_0804_8P4R_5%

A

LAN_PHY_PWR_CTRL / GPIO12

T7

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3_R

Intel Anti-Theft Techonlogy

@

A16 swap overide Strap/Top-Block
Swap Override jumper

K9

R110
10K_0402_5%

+3VALW

Reserved(NAND)

1

AF48
AF47

+3VS

IBEXPEAK-M_FCBGA1071

High=Enabled
NV_ALE
Low=Disable(floating)

8
7
6
5

AH45
AH46

GPIO15

RP1

Boot BIOS Strap

R149

@ R200 1

GPIO8

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

HDMI HPD FOR PCH

2
0_0402_5%
2
0_0402_5%

R212 1

RP4

PCI_GNT3#

TACH3 / GPIO7

3G CARD

USB_OC#0
USB_OC#1
1
R625
1
R626

J32
F10

2 GPIO57
10K_0402_5%

R614
1

FP

28
28

TACH2 / GPIO6

1
2
R480
PCH_TEMP_ALERT#

HYBRID@
0_0402_5%
2

WLAN
USB3

T20
PAD
2

1
R433

1
R415

+3VALW

Within 500 mils minimum spacing to other
signal is 15mil
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3_R
USB_OC#4
USB_OC#5_R
USB_OC#6
USB_OC#7

10K_0402_5%
34 PCH_TEMP_ALERT#

USB2

28
28
37
37
38
38
37
37

USB20_N13
USB20_P13

+3VALW

LEFT USB (COMBO)

22,39,45

D37

EC_SMI#

1
R481
1
10K_0402_5%
R109
1
10K_0402_5%
R112
1
10K_0402_5%
R76
DRAMRST_CNTRL_PCH

5 DRAMRST_CNTRL_PCH

USB Camera

GPIO6

10K_0402_5%

6

USB1

PCI_GNT0# PCI_GNT1# Boot BIOS
Location
0
0
LPC

RP6
PCI_DEVSEL#
PCI_LOCK#
PCI_SERR#
PCI_PERR#

8
7
6
5

1
2
3
4

37
37
37
37
27
27
37
37

USB20_N5 37
USB20_P5 37

PCI_GNT0#

8
7
6
5
8.2K_0804_8P4R_5%

RP7

PCI_STOP#
PCI_IRDY#
PCI_PIRQD#
DGPU_SELECT#

GPIO1 = GPI,3.3V,CORE
GPIO6 = GPI,3.3V,CORE
GPIO7 = GPI,3.3V,CORE
GPIO8 = GPO,3.3V,SUS
GPIO12 = GPI,3.3V,SUS

TACH1 / GPIO1

BMBUSY# / GPIO0

Default-Internal pull up
+3VS

PCI_PIRQG#
PCI_PIRQC#
PCI_PIRQA#
PCI_PIRQE#

8
7
6
5

1
2
3
4

High Enables the internal VccVRM
to have a clean supply for analog
rails. no need to use on board
filter circuit.

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N5
USB20_P5

ΚDo not connect(floating)

26,27 DGPU_EDIDSEL#

RP5

PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
PCI_PIRQH#

Κ

2

@

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

IBEXPEAK-M_FCBGA1071

1
2
3
4

NV_RCOMP 1 R104
32.4_0402_1%

C38

Y7
1
2 GPIO22
10K_0402_5%
R449
H10
GPIO27 if pull down to turn off 1.8V VR
@
AB12
2
1
10K_0402_5%
R507
V13
1
2 GPIO28
+3VALW
10K_0402_5%
R446
M11
2
1 GPIO34
10K_0402_5%
R432
V6
2
1 GPIO35
10K_0402_5%
R456
GPIO36
AB7

it have weak internal PU 20K

NV_RB#

1K_0402_5%

Y3

GPIO1

DGPU_PWROK

Κ

GPIO27
Default

EC_SMI#

+3VALW

H Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

22_0402_5%
+3VS

PCI_REQ0#
PCI_PIRQB#
PCI_PIRQF#
PCI_REQ3#

*Κ

NV_ALE
NV_CLE

EC_SCI#

34

GPIO15
L Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

within 500mil

NV_RCOMP

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

10K_0402_5%
34

GPIO0

1

BD3
AY6

Check list Rev0.8 section1.23.2
If not implemented, the
Braidwood
interface signals can be
left as No Connect (NC).

1
2
R483
1
2
R428
1
2
R427
EC_SCI#

2

NV_ALE
NV_CLE

10K_0402_5%

1

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

10K_0402_5%

2

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

GPIO0 = GPI,3.3V,CORE

+3VS

2

AV9
BG8

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

K6

PCI_RST#

NV_DQS0
NV_DQS1

GPIO8
Weak internal PU, don't PD

1

PIRQA#
PIRQB#
PIRQC#
PIRQD#

AY9
BD1
AP15
BD8

MISC

G38
H51
B37
A44

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

CPU

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B41
K53
A36
A48

1

GPIO

J50
G42
H47
G34

NVRAM

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

NCTF

GPIO18 = NATIVE,5V,CORE
GPIO52 = NATIVE,5V,CORE
GPIO54 = NATIVE,5V,CORE

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

USB

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

2

U7F

PCI

D

3

RSVD

U7E

Size
Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

16

of

50

http://hobi-elektronika.net

Y22

+3VALW

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

DCPSUS

AH22

VCCVRM[4]

AT20

VCCIO[10]

AH19

VCCIO[11]

AD20

VCCIO[12]

AF22

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

AD19
AF20
AF19
AH20

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

AB19
AB20
AB22
AD22

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

AA34
Y34
Y35
AA35

AN35

VCC3_3[1]

AT22

VCCVRM[1]

0.035A

BJ18

VCCFDIPLL

6mA

AM23

VCCIO[1]

1
AD35

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

V_CPU_IO[1]

AU18

V_CPU_IO[2]

1

2

+1.05VS

IBEXPEAK-M_FCBGA1071

HDA

RTC

VCCRTC

2mA

6mA

VCCSUSHDA

R528
0_0402_5%
@

2

10U_0603_6.3V6M 10U_0603_6.3V6M
1
C456

2
0.1U_0402_16V4Z

check

+1.8VS

C

R509
VCCVRM[2]

AT24

VCCDMI[1]

AT16

VCCDMI[2]

AU16

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AM8
AM9
AP11
AP9

0.061A

0.156A

2 0_0402_5%

1
+VCCP

R514 1

1
C491

1

2

@

+1.5VS

2 0_0402_5%

2
1U_0402_6.3V6K

R508

1

2 0_0402_5%

+1.8VS

R501

1

2 0_0402_5%

+3VS

@

+3VS

0.085A

1

B

+VCCADPLLA

10uH inductor, 120mA
L26
1
2
10UH_LB2012T100MR_20%

+1.05VS
+PCH_VCC1_1_20
+PCH_VCC1_1_21
+PCH_VCC1_1_22
+PCH_VCC1_1_23

1
1
1
1

R488
R487
R489
R490

2
2
2
2

+5VALW +3VALW
1

C507 +
220U_B2_2.5VM_R35

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

1
C494
1U_0402_6.3V4Z
2

L30
1

2

R410

1

R411

1
@

R521
0_0402_5%
@

R423
10_0402_1%

2

2 0_0402_5%

+3VALW

2 0_0402_5%

+1.5V

D6

+5VS

+3VS

R438
10_0402_1%

D9

CH751H-40PT_SOD323-2
+VCCADPLLB

CH751H-40PT_SOD323-2

PCH_V5REF_SUS

10uH inductor, 120mA

PCH_V5REF_RUN

20 mils

L25
1
2
10UH_LB2012T100MR_20%

1
1

C506 +
220U_B2_2.5VM_R35

1

C447
1U_0603_10V6K

20 mils
1

SVT

2

C493
1U_0402_6.3V4Z
2

2

C448
1U_0603_10V6K
A

2

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C492

2

+3VS

IBEXPEAK-M_FCBGA1071

2

>1mA

CPU

AT18

+1.05VS

SVT

C505
2

1

LVDS

VCC3_3[4]

C486
2

L28
2
1
0.1UH_MLF1608DR10KT_10%_1608

1

2

VCCIO[54]
VCCIO[55]

VCC3_3[3]

AB35

2

VCCSUS3_3[31]

U22

A12

CRT

2
+1.05VS

AN30
AN31

0.01U_0402_16V7K
AB34

1

+PCH_VRM

+PCH_VRM

C435

2

+3VS

1U_0402_6.3V6K

C440

2

1

VCCIO[9]

0.1U_0402_16V4Z

C442

1

A

0.1U_0402_16V4Z

3nBA4/4W

2

0.1U_0402_16V4Z

2

C489
0.1U_0402_16V4Z

C500

+RTCVCC

C501
4.7U_0603_6.3V6K

2

1

AK3
AK1

C483

1/5BA4/4W

1

2
0.1U_0402_16V4Z

1U_0402_6.3V6K

U20

+VCCP

1

2

VCC3_3[2]

2

+3VS

1/2BA2/2W

1
C457

2

1

+VCCTX_LVDS 0.01U_0402_16V7K
C485 1
1

1

1/3BA4/4W
2
0.1U_0402_16V4Z
C454

1

2
0.1U_0402_16V4Z
C139

2

+3VS

1

+PCH_VRM

1

1

VCCSATAPLL[1]
VCCSATAPLL[2]

1

2

0.1uH inductor, 200mA +1.8VS

2

+V1.1A_INT_VCCSUS
2
0.1U_0402_16V4Z
C463

0.032A

AH39
AP43
AP45
AT46
AT45

1

DCPSST

B

AD13

VCC CORE

2

V12

1

VCC3_3[14]

VSSA_LVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

C467

VCCIO[4]

+VCCSST
2
0.1U_0402_16V4Z
C453

2

VCC3_3[13]

U35

C476
0.1U_0402_16V4Z

2

1

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

2 0.022_0805_1%

1

0.1U_0402_16V4Z

VCCIO[3]

AF32

2

P36

3.208A

AH34

2

VCC3_3[12]

2

+3VS

1

R213

D

+3VS

2

VCCIO[2]

VCC3_3[11]

N36

2

0.1U_0402_16V4Z

AF34

M36

1

@

R214
0_0402_5%
@

C468

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCC3_3[9]
VCC3_3[10]

1

C514

AH23
AJ35
AH35

0.357A

L38

PCH_V5REF_RUN

C474

VCCADPLLB[1]
VCCADPLLB[2]

K49
J38

+1.05VS

10U_0603_6.3V6M

0.073A

BD51
BD53

V5REF

VCC3_3[8]

2

1_0603_5%

1

VCCADPLLA[1]
VCCADPLLA[2]

>1mA

AH38

2

1

2

0.072A

VCCALVDS

2

1

1

0.035A
VCCVRM[3]

2

1U_0402_6.3V6K

1

PCH_V5REF_SUS

C473

1

1U_0402_6.3V6K

C484
1U_0402_6.3V6K

C472

C465
1U_0402_6.3V6K

1

F24

1U_0402_6.3V6K

+1.05VS

V5REF_SUS

>1mA

VCCAPLLEXP0.042A

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

1

+VCCADPLLB

DCPRTC

1

C462

BB51
BB53

+1.05VS

+3VALW

1U_0402_6.3V6K

lsolate AF32,AF34,AH34
from AH35,AJ35
for Intel request
09.09.08

V23

VCCIO[24]

BJ24

C464

+VCCADPLLA

VCCIO[56]

AK24

1U_0402_6.3V6K

V9

VCCSUS3_3[28]

AF51

HVCMOS

VCCME[12]

0.059A

DMI

VCCME[11]

Y42

U23

VSSA_DAC[2]

1

+VCCA_LVDS

PCI E*

VCCME[10]

Y41

AU24

+PCH_VRM

USB

VCCME[9]

Y39

Clock and Miscellaneous

V42

+1.05VS

C455

C452
+VCCRTCEXT
1
2
0.1U_0402_16V4Z

C

VCCME[8]

SATA

2

VCCME[7]

V41

PCI/GPIO/LPC

1

V39

1.998A

PCI/GPIO/LPC

VCCME[6]

VSSA_DAC[1]

0.030A

NAND / SPI

1

AF42

2

AE52
AF53

C490

VCCME[5]

VCCADAC[2]

2

0.01U_0402_16V7K

AF41

1

0.1U_0402_16V4Z

2

C475

2

1

VCCME[4]

1U_0402_6.3V6K

1

10U_0603_6.3V6M

2

C504
10U_0603_6.3V6M

1

C515
10U_0603_6.3V6M

2

C503
10U_0603_6.3V6M

C516

1

VCCME[3]

AF43

VCCADAC[1]

0.069A

C478

UPDATE 0210

VCCME[2]

AD41

C224

2

AD39

+3VALW

0.1U_0402_16V4Z

C471

1U_0402_6.3V6K

1

VCCME[1]

2

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4] 1.524A
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

+3VS

PVT
R208
1

0.1U_0402_16V4Z

+1.05VS

DCPSUSBYP

2

1

C262

AD38

VCCLAN[2]

1

10U_0805_6.3V6M

2

T8
Y20
2
0.1U_0402_16V4Z

2

AE50
C477

PAD
1
C461

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

0.01U_0402_16V7K

@ C469
1U_0402_6.3V4Z

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
0.163AVCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

POWER

U7G

C502

R486
0_0402_5%

AF24

0.344A

1

10U_0603_6.3V6M

1

V24
V26
Y24
Y26

C470

VCCLAN[1]

+3VS_DAC
+1.05VS

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

0.052A

1U_0402_6.3V6K

VCCACLK[2]

AF23

1

+1.05VS

C466

@

0_0402_5%
2

VCCACLK[1]

AP53

2

1U_0402_6.3V6K

R527
1

AP51

3

POWER

U7J

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

+1.05VS

D

4

FDI

5

4

3

2

Title

Compal Electronics, Inc.
IBEX-M(5/6)-PWR

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

17

of

50

http://hobi-elektronika.net

5

4

3

2

1

U7I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

D

C

B

A

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

U7H

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

AB16

VSS[0]

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

D

C

B

IBEXPEAK-M_FCBGA1071

A

IBEXPEAK-M_FCBGA1071

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
IBEX-M(6/6)-GND

Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

18

of

50

http://hobi-elektronika.net

5

4

3

2

U22A

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N15

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

CLK_PCIE_VGA
CLK_PCIE_VGA#

14 CLK_PCIE_VGA
14 CLK_PCIE_VGA#

AB10
AC10

PEX_RST_N

0

0.8V

Deep P12

0x0A7D

1
1

0.85V

P8

0.9V

P0

DACA_VREF
DACA_RSET

T5
R4
T4

DACB_VREF
DACB_RSET

R6
V6

I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA

AD25

R1
T3
R2
R3

+3VS_DELAY

1

D

1

2

GPIO

I2CB_SCL
I2CB_SDA

AF3
AG4
AE4
AF4
AG3

P-State

R505
10K_0402_5%
@

2

AF1
AE1

DACB_RED
DACB_BLUE
DACB_GREEN

VGA_CORE

VGA_HSYNC 26
VGA_VSYNC 26

DACA_VREF
DACA_RSET
DACB_HSYNC
DACB_VSYNC

N11M-GE1/LP1
(40nm)

R513
10K_0402_5%
@

VGA_CRT_R 26
VGA_CRT_B 26
VGA_CRT_G 26

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

CRT OUT

R537
R538
R530

1 HYBRID@
2
1 HYBRID@
2
1 HYBRID@
2

150_0402_1%
150_0402_1%
150_0402_1%

2
C81

1
0.1U_0402_16V4Z
HYBRID@

R48 HYBRID@ 124_0402_1%

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

PAD
PAD
PAD
PAD

T14
T13
T12
T11

C

1
2
R539 HYBRID@ 10K_0402_5%
TESTMODE
1
2
R24 HYBRID@ 10K_0402_5%
1
2
10K_0402_5% @ R25
+3VS_DELAY
VGA_DDCCLK_C
VGA_DDCDATA_C
I2CB_SCL
I2CB_SDA

R517 1 HYBRID@
2
R516 1
2
HYBRID@

A2
B1

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

A3
A4

HDCP_SMB_CK1
HDCP_SMB_DAI
SMB_EC_CK2_R
SMB_EC_DA2_R

T1
T2

+3VS_DELAY
+3VS_DELAY

2.2K_0402_5%
2.2K_0402_5%

R499
2.2K_0402_5%
HYBRID@

+3VS_DELAY

R478
2.2K_0402_5%
HYBRID@
VGA_LVDS_SCL_C

R64

2 HYBRID@
1 2.2K_0402_5%

VGA_LVDS_SDA_C

R63

2 HYBRID@
1 2.2K_0402_5%

I2CS is VDD33 power plane
same as EC +3.3VS.

SMB_EC_CK2_R 14
SMB_EC_DA2_R 14

I2CS is internal thermal sensor.
XTAL_SSIN
XTAL_OUTBUFF
XTAL_OUT
XTAL_IN

Removed external HDCP.
07/17/2009

D11
E9
E10

XTALOUT

D10

XTALIN

R42
10K_0402_5%
HYBRID@

N11M-LP1_BGA533
HYBRID@

HYBRID@
2 10K_0402_5%
R542

1

+3VS_DELAY

2

PEX_CLKREQ_N

GPU_VID1

0
0
1

2

R46
10K_0402_5%
@

GPIO6

GPU_VID0

VGA_GPIO11
VGA_GPIO14

AD2
AD1

U6
U4

GPU_VID0 45
GPU_VID1 45

VGA_GPIO14

DACA_RED
DACA_BLUE
DACA_GREEN

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

VGA_ENVDD_R 27
VGA_ENABLT 27
GPU_VID0
2
GPU_VID1
2 0_0402_5% HYBRID@
0_0402_5% HYBRID@
2
2 0_0402_5% HYBRID@
0_0402_5% HYBRID@

1
R511 1
R512
1
R577 1
R579
VGA_GPIO11

VGA_CRT_R
VGA_CRT_B
VGA_CRT_G

I2CA_SCL
I2CA_SDA

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_TERMP

GPIO5

NV_INVTPWM 27

AE2
AD3
AE3

TESTMODE

PEX_REFCLK
PEX_REFCLK_N

1

AE9

B

DACA

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

AF10
AE10
1
2
R540 200_0402_5% @
1
2
AG10
R541 2.49K_0402_1% HYBRID@
AD9

PLTRST_VGA#

16 PLTRST_VGA#

AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26

HDMI_DETECT_VGA 24

1

HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1
HYBRID@
1

DACA_HSYNC
DACA_VSYNC

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

R34
10K_0402_5%
HYBRID@

B

2

C120
C119
C118
C117
C80
C79
C78
C77
C116
C115
C114
C113
C112
C111
C109
C110
C108
C107
C105
C106
C104
C103
C102
C101
C100
C99
C98
C97
C96
C95
C94
C93

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

1

C

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

DACB

HYBRID@

PCI EXPRESS

D

TEST

PCIE_CRX_GTX_P[0..15]

6 PCIE_CRX_GTX_P[0..15]

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

I2C

PCIE_CRX_GTX_N[0..15]

6 PCIE_CRX_GTX_N[0..15]

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27

Device ID

10/01 Add

Part 1 of 5

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P[0..15]

6 PCIE_CTX_GRX_P[0..15]

CLK

PCIE_CTX_GRX_N[0..15]

6 PCIE_CTX_GRX_N[0..15]

1

+3VS
2

PVT, org SM010010710 121T03
L17
R543
Q50
10K_0402_5%
2N7002_SOT23

Y2
4

GND

OUT

1

S

3

1

2
G

D

1

IN

GND

3

C69
20P_0402_50V8
HYBRID@2

+3VS_DELAY

VGA_LVDS_SCL_C
VGA_LVDS_SDA_C

2

27MHZ_16PF_X7S027000BG1H-U
HYBRID@

HYBRID@ 0_0603_5%
2
2
HYBRID@ 0_0603_5%
HYBRID@ 0_0603_5%
L8 1
2
1
2
L7
HYBRID@ 0_0603_5%
1
1

VGA_DDCCLK 26
VGA_DDCDATA 26

L18

1

PEG_CLKREQ#

14 PEG_CLKREQ#

VGA_DDCCLK_C
VGA_DDCDATA_C

VGA_LVDS_SCL 27
VGA_LVDS_SDA 27

1

2

C56
20P_0402_50V8
HYBRID@

C450
@

1

2

C451
@

1

2

C86
@

1

2

C85
@

1

2

12P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J
A

A

Compal Secret Data

Security Classification
2010/01/13

Issued Date

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N10M-GE1 PCIE,GPIO,CLK

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
1

19

of

50

http://hobi-elektronika.net

5

4

23

FBAA[0..13]

23

FBBA[2..5]

FBAA[0..13]
FBBA[2..5]
FBADQM[0..7]

23 FBADQM[0..7]

3

2

VGA_LVDS_ACLK#
VGA_LVDS_ACLK

FBADQS[0..7]

23 FBADQS[0..7]

C1216
12P_0402_50V8J
@

FBADQS#[0..7]

23 FBADQS#[0..7]

FBA_D[0..63]

23 FBAD[0..63]

1

1

1

2

2

C1217
12P_0402_50V8J
@

RF 10/22
U22B
D

FB_VREF
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_DEBUG

N24
N23

R18
10K_0402_5%
HYBRID@

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

+1.5VS_VGA
1

F7
G6
D6
C6
A6
A7
B6
B7
E6
E7

R30
1.3K_0402_1%
@

1.27V~0.9V

10mil

FBACLK0 23
FBACLK0# 23

1

FBACLK1 23
FBACLK1# 23

2

R26 2
M22
1
10K_0402_5%HYBRID@

NC
RFU

STRAP0

B9

STRAP1

STRAP2

A9

STRAP2

BUFRST_N

N5

THERMDN

D8

PAD

T2

THERMDP

D9

PAD

T3

C43
0.01U_0402_16V7K
@

STRAP0

22

STRAP1

22

STRAP2

22

C

CEC
SPDIF

R445
10K_0402_5%
HYBRID@
+3VS_DELAY

N2
F9

SPDIF_IN
1 HYBRID@
2
R32 36K_0402_5%

R468
10K_0402_5%
HYBRID@
2

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

C7

STRAP1

+3VS_DELAY

ROM_CS_N

SERIAL

D3
D4
F5
F4
E4
D5
C3
C4
B3
B4

STRAP0

1

R15
10K_0402_5%
HYBRID@

G4
G5
P4
N4
M5
M4
L4
K4
H4
J4

T6
W6
Y6
AA6
N3

1

FBAACS0# 23
FBAAODT0 23

RFU_1
RFU_2
RFU_3
RFU_4
RFU_5

C15
D15
J5

2

HDMI
24 VGA_HDMI_SCL
24 VGA_HDMI_SDA
24 VGA_HDMI_TX2+
24 VGA_HDMI_TX224 VGA_HDMI_TX1+
24 VGA_HDMI_TX124 VGA_HDMI_TX0+
24 VGA_HDMI_TX024 VGA_HDMI_CLK+
24 VGA_HDMI_CLK-

FBA_BA2 23
FBBAODT0 23

NC
NC
NC

STRAP

1

R526
4.7K_0402_5%
HYBRID@

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

LVDS / TMDS

1
R23
10K_0402_5%
HYBRID@

AB3
AB2
W1
V1
W3
W2
R531
AA2
4.7K_0402_5% AA3
HYBRID@
AB1
AA1

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

GENERAL

1
2
1

F24
F23

FBAA_CKE 23

2

FBAA0
FBAA9
FBAA6
FBAA2
FBAA8
FBAA3
FBAA1
FBAA13
FBA_BA2
FBBAODT0
FBAACS0#
FBAAODT0

+3VS_DELAY

FBA_RST 23
R16
10K_0402_5%
HYBRID@

2

FB_VREF1

FBAA_CKE

2

A16

23

1

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

FBACAS# 23
FBAWE# 23
FBA_BA0 23
FBAA12

FBBA_CKE 23
R22
10K_0402_5%
HYBRID@

2

C25
A19
E19
A24
T22
AA24
AA26
T27

FBBACS0# 23

1

FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3
FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7

FBBA_CKE
FBBACS0#
FBAA11
FBACAS#
FBAWE#
FBA_BA0
FBBA5
FBAA12
FBA_RST
FBAA7
FBAA10

VGA_LVDS_ACLK AC4
VGA_LVDS_ACLK# AD4
VGA_LVDS_A0
V5
VGA_LVDS_A0#
V4
VGA_LVDS_A1
AA5
VGA_LVDS_A1#
AA4
VGA_LVDS_A2
W4
VGA_LVDS_A2#
Y4
AB4
AB5

VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A0
VGA_LVDS_A0#
VGA_LVDS_A1
VGA_LVDS_A1#
VGA_LVDS_A2
VGA_LVDS_A2#

2

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

D25
A18
E18
B24
R22
Y24
AA27
R27

Part 3 of 5
27
27
27
27
27
27
27
27

FBA_BA1 23

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

ROM_SCLK
ROM_SI
ROM_SO

IFPAB_RSET
IFPC_RSET
IFPD_RSET
IFPE_RSET

B10
C9

ROM_SCLK

A10

ROM_SI

C10

ROM_SO

AB6

ROM_SCLK 22
ROM_SI 22
ROM_SO 22

1
R44

2

1K_0402_1%
2
HYBRID@ 1K_0402_1%
1
2
R40
@
1K_0402_1%
1
2
R477
@
1K_0402_1%

R5

@

1

R39
M6
F8

1

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

U22C

FBARAS# 23

2

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

C26
B19
D19
D23
T24
AA23
AB27
T26

LVDS

1

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBAA4
FBARAS#
FBAA5
FBA_BA1
FBBA2
FBBA4
FBBA3

2

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
J22
L22

B

N11M-LP1_BGA533
HYBRID@

R29
1.3K_0402_1%
@
2

B

D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21
F21
D20
F20
D17
F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24
T23
R23
P24
P22
AC24
AB23
AB24
W24
AA22
W23
W22
V22
AA25
W27
W26
W25
AB25
AB26
AD26
AD27
V25
R25
V26
V27
R26
T25
N25
N26

MEMORY INTERFACE

C

D

Part 2 of 5
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

+1.5VS_VGA

N11M-LP1_BGA533
HYBRID@

A

A

Compal Secret Data

Security Classification
2010/01/13

Issued Date

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N10M-GE1 LVDS,Memory Bus

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
1

20

of

50

http://hobi-elektronika.net

5

4

3

2

PLACE UNDER GPU

NEAR
BGA
+VGA_CORE

U22D

1

D

C26
HYBRID@

2

1
C50
HYBRID@

2

0.01U_0402_16V7K

1
C38
HYBRID@

2

J9
J10
J12
J13
L9
M9
M11
M17
N9
N11
N12
N13
N14
N15
N16
N17
N19
P11
P12
P13
P14
P15
P16
P17
R9
R11
R12
R13
R14
R15
R16
R17
T9
T11
T17
U9
U19
W9
W 10
W 12
W 13
W 18
W 19

1
C39
HYBRID@

2

C40
HYBRID@

2
0.1U_0402_10V7K

0.01U_0402_16V7K
0.047U_0402_16V7K

N10M-GS: 15.8A
N11M-GE1:16.7A

1

2

0.01U_0402_16V7K

1
C41
HYBRID@

2

1
C37
HYBRID@

2

C29
HYBRID@

0.01U_0402_16V7K
0.047U_0402_16V7K

1

2

0.01U_0402_16V7K

1
C36
HYBRID@

2

1
C52
HYBRID@

2

C51
HYBRID@

0.01U_0402_16V7K

NEAR BGA

+3VS_DELAY

NEAR BALL

C

1U_0402_6.3V6K

1

120mA

2

C84
HYBRID@

2

1
C459
HYBRID@

4.7U 6.3V K X5R 0603

+1.8VS_VGA
1

0.1U_0402_10V7K

1

300mA

C44
HYBRID@

2

1
C55
HYBRID@

0.1U_0402_10V7K

NEAR BGA

L27
MBK1608121YZF_0603
2
HYBRID@
1

2

1

2

C54
HYBRID@

A12
B12
C12
D12
E12
F12

0.1U_0402_10V7K

+PEX_SVDD_3V3

NEAR BALL

AG9

1

2
4.7U 6.3V K X5R 0603

2

C499
HYBRID@

1

0.1U_0402_10V7K
1

2

C510
C511
HYBRID@ HYBRID@
2

+IFPA_IOVDD

2

0.1U_0402_10V7K
1

1

C498
HYBRID@

C497
HYBRID@
2

2

1

1

1

1

2

C53
HYBRID@
2

C28
HYBRID@
2

C27
HYBRID@
2

C42
HYBRID@
2

C32
HYBRID@
2

H6
AD5

2
0_0402_5%
HYBRID@

1U_0402_6.3V6K

C68
HYBRID@

1

C67
HYBRID@
2

2

2

+1.05VS_VGA

NEAR BALL

MBK1608121YZF_0603
1

2

1
C73
HYBRID@

4.7U 6.3V K X5R 0603

2

1

1

1

2

C46
HYBRID@
2

1U_0402_6.3V6K

4.7U 6.3V K X5R 0603

1
C58
HYBRID@

2

0.1U_0402_10V7K

1
C83
HYBRID@

1

1

10U_0805_6.3V6M

1U_0402_6.3V6K

1

1

2

C47
HYBRID@
2

C60
HYBRID@
2

C59
HYBRID@

2

0.1U_0402_10V7K

+1.05VS_VGA

4.7U 6.3V K X5R 0603

1

1

1

C49
C48
HYBRID@ HYBRID@
2

2

1
C551
HYBRID@

1U_0402_6.3V6K

C553
HYBRID@

2

10U_0805_6.3V6M

+1.05VS_VGA

120mA

NEAR BGA

L3
1
2
MBK1608121YZF_0603

1U_0402_6.3V6K

1

2

C

1
C45
HYBRID@

2

C57
HYBRID@

HYBRID@

+PEX_PLLVDD

NEAR BALL
0.1U_0402_10V7K

FB_PLLAVDD

R19

FB_PLLAVDD

AC19

FB_DLLAVDD

T19

MBK1608121YZF_0603
2
1
L21
1
1
HYBRID@
C65
C482
HYBRID@ HYBRID@
2
2

1U_0402_6.3V6K

+1.05VS_PLL

12~16mil

1

1

C480
C481
HYBRID@ HYBRID@
2
2
0.1U_0402_10V7K

DACA_VDD

AG2

DACB_VDD

W5

+DACB_VDD

4.7U 6.3V K X5R 0603

+1.05VS_VGA
1
R45

2
HYBRID@ 10K_0402_5%
+SP_PLLVDD

P6

IFPC_PLLVDD

FB_CAL_PD_VDDQ

IFPD_PLLVDD

VDD_SENSE

W 15

D7

IFPE_PLLVDD

VDD_SENSE

E15

VID_PLLVDD=45mA
SP_PLLVDD=45mA
PLLVDD=60mA

+FB_PLLAVDD
+DACA_VDD

N6

+1.05VS_VGA

NEAR BGA

+SP_PLLVDD

B15
R465

L24
1
2
MBK1608121YZF_0603
HYBRID@

1U_0402_6.3V6K

+1.5VS_VGA

HYBRID@
40.2_0402_1%

1

The power is base on VRAM type.
+VGASENSE

+VGASENSE 45

2

1
C64
HYBRID@

B

C488
HYBRID@

2
4.7U 6.3V K X5R 0603

+1.05VS_VGA

+3VS_DELAY

L30

MBK1608121YZF_0603
2
1
HYBRID@
1
C458
HYBRID@

NEAR BGA
+FB_PLLAVDD

1U_0402_6.3V6K

120mA

1

2

1
C30
HYBRID@

+IFPC_PLLVDD

2

L1

1
2
MBK1608121YZF_0603
HYBRID@

L29

NEAR BALL
+DACA_VDD

1U_0402_6.3V6K

0.1U_0402_10V7K

1U_0402_6.3V6K

2

2

2

1
HYBRID@

1
C82
HYBRID@

+3VS_DELAY

NEAR BGAMBK1608121YZF_0603

4700P_0402_25V7K

+IFPAB_PLLVDD

1

FB_PLLVDD=100mA
FB_DLLVDD=100mA

C23
HYBRID@

4.7U 6.3V K X5R 0603

1
C71
HYBRID@

2

4.7U 6.3V K X5R 0603

1
C523
HYBRID@

470P_0402_50V7K

2

C522
HYBRID@

1

1

2

C520
HYBRID@
2

0.1U_0402_10V7K

1

1

C513
C521
HYBRID@HYBRID@
2

2

120mA

1
C519
HYBRID@

0.1U_0402_10V7K

2

C524
HYBRID@
A

4.7U 6.3V K X5R 0603

1

C72
HYBRID@

C62
C63
C61
HYBRID@ HYBRID@ HYBRID@
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K

Issued Date

4

3

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1

NEAR BGA

0.1U_0402_10V7K

1

0.1U_0402_10V7K

22U_0805_6.3V6M

C35
C537
C538
C552
HYBRID@ HYBRID@ HYBRID@ HYBRID@
2
2
2
2

1U_0402_6.3V6K

NEAR BALL

NEAR BGA

MBK1608121YZF_0603

0.1U_0402_10V7K

1

2A

NEAR BGA

0.1U_0402_10V7K

NEAR BALL

HYBRID@
2

220mA

+3VS_DELAY

1U_0402_6.3V6K

NEAR BALL

0.1U_0402_10V7K

1

220mA

PLLVDD

K5

C66
HYBRID@

0.1U_0402_10V7K

A

D

2

NEAR BGA
HYBRID@
2

L6

1
C74
HYBRID@

0.047U_0402_16V7K

+1.05VS_VGA

IFPAB_PLLVDD

1 @
R47
1 HYBRID@
R43

2
10K_0402_5%
2
10K_0402_5%

L5

L6

K6

SP_PLLVDD

0.1U_0402_10V7K

1

2
0.01U_0402_16V7K

IFPC_IOVDD
IFPDE_IOVDD

N11M-GE1:2.55A

1
C24
HYBRID@

C31
HYBRID@

4.7U 6.3V K X5R 0603

VID_PLLVDD

+PEX_SVDD_3V3

4.7U 6.3V K X5R 0603

1

AF9

NEAR BALL

1

2

1
R49

PEX_PLLVDD

4.7U 6.3V K X5R 0603

N11M-LP1_BGA533
HYBRID@

NEAR BGA

L4
MBK1608121YZF_0603

2
HYBRID@

IFPB_IOVDD

C496
HYBRID@

0.1U_0402_10V7K

1

V2
J6

+IFPC_PLLVDD
1U_0402_6.3V6K
1

B

IFPA_IOVDD

+IFPC_IOVDD

2
1
10K_0402_5%
R41
HYBRID@
+IFPAB_PLLVDD

0.1U_0402_10V7K

285mA

PEX_SVDD_3V3

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

AG7
AF7
AE7
AD8
AD7
AC9

0.047U_0402_16V7K

1

0.01U_0402_16V7K

AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

V3

A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

1U_0402_6.3V6K

C512
HYBRID@

+1.05VS_VGA

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

POWER

0.047U_0402_16V7K

0.047U_0402_16V7K

1

Part 4 of 5
4.7U 6.3V K X5R 0603

1

CLOSE TO GPU

0.01U_0402_16V7K

NEAR BALL

1

+1.5VS_VGA

2

Title

N10M-GE1 PWR
Size Document Number
Custom
Date:

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

21

of

50

http://hobi-elektronika.net

5

4

3

2

1

A total of 8 signals are required for GB1 strapping this includes
2 reference signals

6 physical strapping pins
4 logical strapping bits

U22E

FB_CAL_PU_GND
FB_CAL_TERM_GND

W16
E14

GND_SENSE MULTI_STRAP_REF1_GND
GND_SENSE MULTI_STRAP_REF0_GND

+3VS

FBVDDQ

R28

1 HYBRID@
2 40.2_0402_1%

R27

1

1

2

2K_0402_5%

1

2

2K_0402_5%

1
R470
X76@

R466

2

2

20K_0402_1%

R50

2

R467
@

10K_0402_5%
HYBRID@

1
1

2

4.99K_0402_1%

R469
@

15K_0402_1%
HYBRID@

1
2

45.3K_0402_1%
HYBRID@

1
2

R476
@
10K_0402_5%

2

34.8K_0402_1%

R51
@

1

2 60.4_0402_1%
HYBRID@

STRAP1 use for 3GIO_PADCFG to set 35K pull up.
(PUN-04335-001_V10 HW9 update)

F11
F10

R463
40.2K_0402_1%
HYBRID@
2

40.2 ohm

24.9K_0402_1%

2

A15
B16

FB_CAL_PU_GND FBCAL_PD_VDDQ

+1.5VS

R471
@

R473

C

R464
40.2K_0402_1%
HYBRID@

FB Memory (DDR3)

GPU

N11M-GE1
LP1
(0x0A7D)
40nm

DDR3

1

1
R475
@

Place Components Close to BGA

Memory/PKG

R472

1

STRAP2
STRAP1
STRAP0
ROM_SCLK
ROM_SI
ROM_SO

20 STRAP2
20 STRAP1
20 STRAP0
20 ROM_SCLK
20 ROM_SI
20 ROM_SO

N11M-LP1_BGA533
HYBRID@

N11M-GE1
LP1

2

2

R474
PVT
34.8K_0402_1%
DeviceID 0A6E HYBRID@

34.8K_0402_1%
HYBRID@

1

D

1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2

C

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

U2
U5
U11
U12
U13
U14
U15
U16
U17
U23
U26
V9
V19
W11
W14
W17
Y2
Y5
Y23
Y26
AC2
AC5
AC6
AC8
AC11
AC14
AC17
AC20
AC23
AC26
AF2
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
T16
T15
T14
F6

1

D

A total of 24 logical strapping bits are available

Part 5 of 5

GND

B2
B5
B8
B11
B14
B17
B20
B23
B26
E2
E5
E8
E11
E17
E20
E23
E26
H2
H5
J11
J14
J17
K9
K19
L2
L5
L11
L12
L13
L14
L15
L16
L17
M12
M13
M14
M15
M16
P2
P5
P9
P19
P23
P26
T12
T13

40.2 ohm

Samsung
800MHz
(defaul)

K4W1G1646E-HC12

Hynix
800MHz

H5TQ1G63BFR-12C

64Mx16

64Mx16

FBCAL_TERM_GND

ROM_SO

ROM_SCLK

ROM_SI

STRAP2

STRAP1

STRAP0

PD 10K

PD 15K

PD 20K

PU 30K

PU 35K

PU 45K

PD 10K

PD 15K

PD 15K

PU 30K

PU 35K

PU 45K

X76

40.2/60.4 ohm

B

B

Must be used 1% resister for driver calibration

DG-04642-001-V01(May 22, 2009)
HYBRID@ 1021 add

C597 @
4.7U_0805_10V4Z

2

G

2

R959
100K_0402_1%
HYBRID@

5

Q36A
2N7002DW-T/R7_SOT363-6
HYBRID@

3
2

1

+1.8VS_VGA
R762

6

+3VS_DELAY
DGPU_PWR_EN

Q75 HYBRID@
SI2301BDS-T1-E3_SOT23-3

C1209 HYBRID@
2 0.1U_0402_16V4Z

Q73 HYBRID@
SI2301BDS-T1-E3_SOT23-3

C1208 HYBRID@
2 0.1U_0402_16V4Z
1

16,39,45 DGPU_PWR_EN
A

1

HYBRID@
2

C628 @
4.7U_0805_10V4Z

2

Q59A
2N7002DW-T/R7_SOT363-6
HYBRID@

2

R761
+3VS_DELAY_R 2
1
0_0603_5%
PVT,chg AO3413 main

+1.8VS_DELAY_R2
1
0_0603_5%
PVT,chg AO3413 main
HYBRID@

1

4

6

1

D

R958
33K_0402_1%

1

PVT,timing
1
2

4

DGPU_PWR_RC_EN# 2

Q59B
2N7002DW-T/R7_SOT363-6
HYBRID@

W=60mils
R156
0_0402_5%
@

1

S

PVT,timing
1
2

3

2

3

1

3VDELAY-

VGA1.8EN-

3

R910 HYBRID@
100K_0402_5%

+1.8VS

1

W=60mils

R911
100K_0402_5%
HYBRID@

2

+3VS
1

R17 @
150_0603_1%

5

DGPU_PWR_RC_EN#

1
R86 @
150_0603_1%

+5VALW

Q36B
2N7002DW-T/R7_SOT363-6
HYBRID@

+5VALW

D

+3VS_DELAY

G

HYBRID@

S

+1.8VS_VGA

A

HYBRID@

Compal Secret Data

Security Classification
2010/01/13

Issued Date

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
N10M-GE1 GND & STRAP

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
1

22

of

50

http://hobi-elektronika.net

5

4

+VRAM_VREFB

K2
L3
J4
K4
L4

FBADQS1
FBADQS3

F4
C8

FBADQM1
FBADQM3

E8
D4

FBADQS#1
FBADQS#3

G4
B8

FBA_RST

T3

DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J2
L2
J10
L10

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

R12
240_0402_1%
HYBRID@

J8
K8
K10

A2
A9
C2
C10
D3
E10
F2
H3
H10

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

K2
L3
J4
K4
L4

FBADQS2
FBADQS0

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

FBADQM2
FBADQM0

E8
D4

FBADQS#2
FBADQS#0

G4
B8

FBA_RST

T3
L9

BA0
BA1
BA2

A1
A11
T1
T11

NC
NC
NC
NC

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R21
240_0402_1%
HYBRID@

A1
A11
T1
T11

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0

FBACLK1

2

M3
N9
M4

+1.5VS_VGA

A2
A9
C2
C10
D3
E10
F2
H3
H10

20
20

FBACLK1
FBACLK1#

FBACLK1
FBACLK1#

20

FBBA_CKE

20
20

FBBAODT0
FBBACS0#

J8
K8
K10

FBBA_CKE
FBBAODT0
FBBACS0#
FBARAS#
FBACAS#
FBAWE#

K2
L3
J4
K4
L4

FBADQS4
FBADQS7

F4
C8

FBADQM4
FBADQM7

E8
D4

FBADQS#4
FBADQS#7

G4
B8

FBA_RST

T3

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

L9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

1

C21
HYBRID@

2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R7
240_0402_1%
HYBRID@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

100-BALL
SDRAM DDR3

R14
243_0402_1%
HYBRID@

E4
F8
F3
F9
H4
H9
G3
H8

FBAD37
FBAD36
FBAD35
FBAD32
FBAD39
FBAD34
FBAD38
FBAD33

D8
C4
C9
C3
A8
A3
B9
A4

FBAD61
FBAD57
FBAD56
FBAD62
FBAD58
FBAD63
FBAD59
FBAD60

1

C518
HYBRID@

C444
HYBRID@
2
10U_0603_6.3V6M

2

C3
HYBRID@

10U_0603_6.3V6M
1

1

2

C6
HYBRID@

1

C7
2

2

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

FBADQM5
FBADQM6

E8
D4

FBADQS#5
FBADQS#6

G4
B8

T3
L9

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R523
240_0402_1%
HYBRID@

A1
A11
T1
T11

CK
CK
CKE/CKE0
ODT/ODT0
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R11
1.33K_0402_1%
HYBRID@

+VRAM_VREFA

1
2

2

1

HYBRID@

1

2

B

HYBRID@

1
R529
1.33K_0402_1%
HYBRID@
2

2

+VRAM_VREFD

12MIL
1

2

R522
1.33K_0402_1%
HYBRID@

HYBRID@

Compal Secret Data
2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

2

1

2

HYBRID@
A

Compal Electronics, Inc.
VRAM DDR3

Size
C
Date:

3

B2
B10
D2
D9
E3
E9
F10
G2
G10

0.1U_0402_10V6K

1U_0402_6.3V6K

Issued Date

4

C

+1.5VS_VGA

0.1U_0402_10V6K

R8
1.33K_0402_1%
HYBRID@

Security Classification

5

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

+VRAM_VREFB

R10
1.33K_0402_1%
HYBRID@

1
1

HYBRID@
HYBRID@
2
2
1U_0402_6.3V6K

1

1
HYBRID@
2

C8

1
HYBRID@
2

+1.5VS_VGA

A2
A9
C2
C10
D3
E10
F2
H3
H10

12MIL
1

+VRAM_VREFC

2

1

HYBRID@
2
2
1U_0402_6.3V6K

6
+1.5VS_VGA

B3
D10
G8
K3
K9
N2
N10
R2
R10

0.1U_0402_10V6K

1

HYBRID@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

12MIL
C19

2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D

+1.5VS_VGA

R9
1.33K_0402_1%
HYBRID@

C16

1U_0402_6.3V6K

1

C11

HYBRID@

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

FBAD50
FBAD52
FBAD49
FBAD53
FBAD48
FBAD54
FBAD51
FBAD55

X76@

+1.5VS_VGA

1U_0402_6.3V6K
C12

2

C17

1

HYBRID@

C18

2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

D8
C4
C9
C3
A8
A3
B9
A4

5

K4B1G1646D-HCF8_FBGA100

0.1U_0402_10V6K

1

1U_0402_6.3V6K

1U_0402_6.3V6K

C9

1

C10

HYBRID@
2
1U_0402_6.3V6K

F4
C8

BA0
BA1
BA2

FBAD42
FBAD46
FBAD40
FBAD45
FBAD41
FBAD47
FBAD44
FBAD43

HYBRID@
HYBRID@
2
2
1U_0402_6.3V6K

HYBRID@
2

1U_0402_6.3V6K

C438

1

FBADQS5
FBADQS6

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4
F8
F3
F9
H4
H9
G3
H8

C525

2

1

C446

HYBRID@
2

1

C445

HYBRID@
HYBRID@ HYBRID@
HYBRID@
2
2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

HYBRID@

1U_0402_6.3V6K

HYBRID@

K2
L3
J4
K4
L4

FBA_RST

1U_0402_6.3V6K
1

C437

1

C479

1

C487

C20

C5

C128

1

1U_0402_6.3V6K

HYBRID@

A

2

1

+1.5VS_VGA

C526

2

J8
K8
K10

FBBAODT0
FBBACS0#
FBARAS#
FBACAS#
FBAWE#

A2
A9
C2
C10
D3
E10
F2
H3
H10

1U_0402_6.3V6K
1U_0402_6.3V6K

1

C509

C517

+

C436
220U_B2_2.5VM_R35

1

FBACLK1
FBACLK1#
FBBA_CKE

+1.5VS_VGA

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

12MIL

1U_0402_6.3V6K

+1.5VS_VGA

M3
N9
M4

VREFCA
VREFDQ

100-BALL
SDRAM DDR3

R19
1.33K_0402_1%
HYBRID@

1

2
1U_0402_6.3V6K

FBA_BA0
FBA_BA1
FBA_BA2

+1.5VS_VGA
B3
D10
G8
K3
K9
N2
N10
R2
R10

R20
1.33K_0402_1%
HYBRID@

10U_0603_6.3V6M
HYBRID@

1U_0402_6.3V6K

HYBRID@

7

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

+1.5VS_VGA
10U_0603_6.3V6M
1

+1.5VS_VGA

HYBRID@

4

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

100-BALL
SDRAM DDR3

10U_0603_6.3V6M

1

M9
H2

K4B1G1646D-HCF8_FBGA100
X76@

2

FBACLK1#

FBA_BA0
FBA_BA1
FBA_BA2

+1.5VS_VGA
B3
D10
G8
K3
K9
N2
N10
R2
R10

K4B1G1646D-HCF8_FBGA100
X76@

10U_0603_6.3V6M
1

1

B

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

+1.5VS_VGA

HYBRID@
243_0402_1%
R442
FBACLK0#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

100-BALL
SDRAM DDR3
K4B1G1646D-HCF8_FBGA100
X76@

FBACLK0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

0

1

ZQ/ZQ0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

M3
N9
M4

FBACLK0
FBACLK0#
FBAA_CKE

+1.5VS_VGA

1

L9

ODT/ODT0
CS
RAS
CAS
WE

FBA_BA0
FBA_BA1
FBA_BA2

+1.5VS_VGA
B3
D10
G8
K3
K9
N2
N10
R2
R10

FBAD4
FBAD1
FBAD7
FBAD0
FBAD5
FBAD2
FBAD6
FBAD3

FBAA0
FBAA1
FBBA2
FBBA3
FBBA4
FBBA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

C4

FBA_RST

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

D8
C4
C9
C3
A8
A3
B9
A4

2

U23

VREFCA
VREFDQ

C495

C

J8
K8
K10

BA0
BA1
BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M9
H2

1

FBAA_CKE

FBAAODT0
FBAACS0#
FBARAS#
FBACAS#
FBAWE#

20

M3
N9
M4

3

FBAD21
FBAD17
FBAD20
FBAD16
FBAD22
FBAD18
FBAD23
FBAD19

2

20
20
20
20
20

FBACLK0
FBACLK0#
FBAA_CKE

FBA_BA0
FBA_BA1
FBA_BA2

FBAD26
FBAD29
FBAD24
FBAD25
FBAD28
FBAD31
FBAD27
FBAD30

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E4
F8
F3
F9
H4
H9
G3
H8

1

20
20
20

FBA_BA0
FBA_BA1
FBA_BA2

D8
C4
C9
C3
A8
A3
B9
A4

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

20
20
20

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

VREFCA
VREFDQ

1

FBAD[0..63]

1

M9
H2

2

FBADQS#[0..7]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

FBAD9
FBAD14
FBAD8
FBAD12
FBAD10
FBAD13
FBAD11
FBAD15

1

20 FBAD[0..63]

FBADQS[0..7]

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

E4
F8
F3
F9
H4
H9
G3
H8

1

20 FBADQS#[0..7]
D

FBADQM[0..7]

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12
FBAA13

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

20 FBADQS[0..7]

FBBA[2..5]

VREFCA
VREFDQ

C22

20 FBADQM[0..7]

M9
H2

U1

1

FBBA[2..5]

FBAA[0..13]

U2

2

20

+VRAM_VREFC

+VRAM_VREFA

2

FBAA[0..13]

1

+VRAM_VREFD

+VRAM_VREFC

+VRAM_VREFA
U21

20

2

+VRAM_VREFD

2

N10x 40nm DDR3 MAPPING
NVIDIA COCUMENT FOR DA-3978-001

3

+VRAM_VREFB

Document Number

Rev
0.3

LA-5941P
Sheet

Thursday, April 08, 2010
1

23

of

50

http://hobi-elektronika.net
4

From VGA

D

20
20
20
20
20
20
20
20

C284
C283
C282
C281
C601
C600
C614
C599

VGA_HDMI_CLK+
VGA_HDMI_CLKVGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX2+
VGA_HDMI_TX2-

1
1
1
1
1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

2
2
2
2
2
2
2
2

HYBRID@
HYBRID@
HYBRID@
HYBRID@
HYBRID@
HYBRID@
HYBRID@
HYBRID@

3

2

HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

+3VS_DELAY

Near L33,L34,L35,L36

D

4

1

20 VGA_HDMI_SCL

HDMIDAT_R

3
Q84B HYBRID@
2N7002DW -T/R7_SOT363-6

2

20 VGA_HDMI_SDA

From Level Shiftter

HDMICLK_R

6
Q84A
HYBRID@
2N7002DW -T/R7_SOT363-6

25
25
25
25
25
25
25
25

HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

1

5

5

C611

1

1
C603

HYBRID@
2
12P_0402_50V8J

HYBRID@
2
12P_0402_50V8J

+3VS

2

25 HP_DET#

1

R615
10K_0402_1%
UMA@
C

DGPU_HPD_INT#

R618 1

2

0_0402_5%

HP_DET#

C

1

16 DGPU_HPD_INT#

D

HYBRID@

HP_DET

3

HDMI_TX0+_CONN

1
R589

HDMI_TX0-_CONN

1
R587

HDMI_TX1+_CONN

1
R593

HDMI_TX1-_CONN

1
R591

HDMI_TX2+_CONN

1
R597

HDMI_TX2-_CONN

1
R595

B

19 HDMI_DETECT_VGA

499_0402_1%

HDMI_DETECT_VGA

1

499_0402_1%

1

R583

R616
100K_0402_5%

2

1

2

Q53
2N7002W -T/R7_SOT323-3

D

499_0402_1%

W=40mils

2
G

499_0402_1%

R581

HYBRID@S
Q52
2N7002W -T/R7_SOT323-3

3

2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@
2
HYBRID@

1

499_0402_1%

1

1
R585

HDMI_CLK-_CONN

1 C678
0.1U_0402_16V4Z

S

R617
10K_0402_1%
HYBRID@

D

499_0402_1%
499_0402_1%

S

3

HDMI_CLK+_CONN

2

2
G
+3VS_DELAY

499_0402_1%

+5VS

D28

F2

1+5VS_HDMI_R

2
2
+3VS
G
HYBRID@
Q41
2N7002W -T/R7_SOT323-3

0_0805_5%

@

2

PMEG2010ET SOT23

1
1.1A_6V_SMD1812P110TF

R603

0_0805_5%

@

NEAR CONNECT

B

+5VS_HDMI

4

4

2

HDMI_CLK+_CONN

3

3

HDMI_CLK-_CONN

R249
2.2K_0402_5%

1

W CM-2012-900T_4P

1 C627
0.1U_0402_16V4Z

2

1

HDMI_CLK-_CK

2

2

R257
2.2K_0402_5%

1

1

2

L33 @
HDMI_CLK+_CK

L34 @
HDMI_TX0+_CK

1

HDMI_TX0-_CK

4

1
4

2

HDMI_TX0+_CONN

3

3

HDMI_TX0-_CONN

HP_DET

25 HP_DET
25
25

W CM-2012-900T_4P

HDMI_TX1-_CK

1
4

HDMI_CLK-_CONN

1

2

2

4

3

3

HDMI_TX1+_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX1-_CONN
+5VS

W CM-2012-900T_4P
L36 @
HDMI_TX2+_CK
A

1

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMIDAT_R
HDMICLK_R

HDMIDAT_R
HDMICLK_R

L35 @
HDMI_TX1+_CK

3

1

2

2

4

3

3

HDMI_TX0+_CONN
HDMI_TX1-_CONN

+5VS

HDMI_TX1+_CONN
HDMI_TX2-_CONN

3

HDMI_TX2+_CONN

1

HDMIDAT_R

1

HDMICLK_R
HDMI_TX2+_CONN

HDMI_TX2-_CK

4

HDMI_TX2-_CONN

@
D24
BAT54S-7-F_SOT23-3

2

W CM-2012-900T_4P
HDMI_CLK+_CK
HDMI_CLK-_CK
HDMI_TX0+_CK
HDMI_TX0-_CK
HDMI_TX1+_CK
HDMI_TX1-_CK
HDMI_TX2+_CK
HDMI_TX2-_CK

R584
R582
R588
R586
R592
R590
R596
R594

5

1
1
1
1
1
1
1
1

PVT
DIP type

JHDMI1

2

2
2
2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2

@
D25
BAT54S-7-F_SOT23-3

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND1
CK_shield GND2
CK+
D0D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21

A

FOX_QJ1119L-NVBT-7H
ME@

HDMI_CLK+_CONN
HDMI_CLK-_CONN
HDMI_TX0+_CONN
HDMI_TX0-_CONN
HDMI_TX1+_CONN
HDMI_TX1-_CONN
HDMI_TX2+_CONN
HDMI_TX2-_CONN

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

2

Title

HDMI CONN
Size
Document Number
Custom

Rev
0.3

LA-5941P

Date: Thursday, April 08, 2010

Sheet
1

24

of

50

http://hobi-elektronika.net

5

4

3

2

1

P/N:SA00003GT00 (ASM1442)

R428 STUFF
RESERVE THE R668 PULL UP TO 3VS
RESERVE THE R670 PULL DOWN TO GND
CHANGE R245 FROM 499 TO 3.4K OHM
1

U12

2

HDMICLK_R

HDMICLK_R

28

SCL_SINK

24

HDMIDAT_R

HDMIDAT_R

29

output
SDA_SINK

24

HP_DET

30

HPD_SINK

32

DDC_EN

24

1
1

2

R242
4.7K_0402_5%
UMA@

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

1442_VCC

R254 1
R255 1

4.7K_0402_5%
2 @
2 @
4.7K_0402_5%

34
35

R256
4.7K_0402_5%
@

1

C

CFG0
CFG1
internal pull down

internal pull down

input

1

R244
4.7K_0402_5%
@

48
47

15 TMDS_B_DATA0
15 TMDS_B_DATA0#

45
44

15 TMDS_B_DATA1
15 TMDS_B_DATA1#

42
41

15 TMDS_B_DATA2
15 TMDS_B_DATA2#

39
38

R246 1
R248 1

7

SDA

8

HDMIDAT_NB 15

SCL

9

HDMICLK_NB

10

TMDS_B_HPD

R232 1

OUT_D3+
OUT_D3-

16
17

HDMI_TX0+_CK
HDMI_TX0-_CK

IN_D2+
IN_D2-

OUT_D2+
OUT_D2-

19
20

HDMI_TX1+_CK
HDMI_TX1-_CK

IN_D1+
IN_D1-

OUT_D1+
OUT_D1-

22
23

HDMI_TX2+_CK
HDMI_TX2-_CK

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PAD

1
5
12
18
24
27
31
36
37
43
49

1

TMDS_B_HPD 15

@

2 4.7K_0402_5%

TMDS_B_HPD

R674
2

100K_0402_5%
1
C

SVT
HYBRID@
CLOSE ASM1442

15

1442_VCC

HDMI_CLK+_CK 24
HDMI_CLK-_CK 24
HDMI_TX0+_CK 24
HDMI_TX0-_CK 24
HDMI_TX1+_CK 24
HDMI_TX1-_CK 24
HDMI_TX2+_CK 24
HDMI_TX2-_CK 24

B

R280
R331
0_0402_5% 0_0402_5%

R261
0_0402_5%

2

2

2 UMA@ 3.4K_0402_1%

6

13
14

IN_D3+
IN_D3-

1442_VCC

2 UMA@ 4.7K_0402_5%
4.7K_0402_5%
2 @

HPD#

OUT_D4+
OUT_D4-

IN_D4+
IN_D4-

R670
2.2K_0402_5%
UMA@
SVT

R245 1

2 0_0805_5%

1442_VCC

4.7K_0402_5%
R247 1
@
2
4.7K_0402_5%
R334 1
@
2

HDMI_CLK+_CK
HDMI_CLK-_CK

TMDS_B_CLK#

B

0_0402_5%
1
0_0402_5%
1

REXT

RT_EN#
15 TMDS_B_CLK
15 TMDS_B_CLK#

2R332
2R333

PC1 4
3
PC0 internal
pull down

2

2

2

@
R243
0_0402_5%

2
11
15
21
26
33
40
46

2

1442_VCC
1 R559
1
1
UMA@
UMA@
C604
C285
0.1U_0402_16V4Z
10U_0805_10V4Z
2
2

UMA@
C602
0.1U_0402_16V4Z

ASM1442_QFN48_7X7

2

OE#

1

FOR PS8171

1

25

HP_DET#

1442_VCC

UMA@
C280
0.1U_0402_16V4Z

2

HP_DET#

24

D

+3VS
1442_VCC

1

D

1

FOR asmedia

UMA@

Pin1
Pin3
Pin4
Pin6
Pin11
Pin12

R331 NC
R248,R334 NC
R246,R247 NC
R245 499ohm
R332 NC
R280 NC

Pin27 R261 NC
Pin33 R333 NC
Pin34 R254 4.7K ohm
A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Level Shiftter_ASM1442
Size
Document Number
Custom
Date: Thursday, April 08, 2010

Rev
0.3

LA-5941P
Sheet
1

25

of

50

http://hobi-elektronika.net

A

B

C

D

+5VS

3

2
@
D27
BAT54S-7-F_SOT23-3

1
R129
CRT_VSYNC
1
R130
CRT_DDC_DATA 1
R322
CRT_DDC_CLK 1
R328

CRT_G
CRT_B

1

R93
CRT_HSYNC
SVT

1
R153
150_0402_1%

2

PVT

R131
150_0402_1%

R90
150_0402_1%

CLOSE TO CONN
+3VS

U38

@
D26
BAT54S-7-F_SOT23-3

1

FCM1608CF-121T03 0603
1
2
L11
FCM1608CF-121T03 0603
1
2
L10
FCM1608CF-121T03 0603
1
2
L9

CRT_R

1
C158

1
C146

2

2

1

1

R91
DAC_BLU

CRT_R
2
UMA@ 0_0402_5%
CRT_G
2
UMA@ 0_0402_5%
CRT_B
2
UMA@ 0_0402_5%
HSYNC_G
2
UMA@ 33_0402_1%
VSYNC_G
2
UMA@ 33_0402_1%
CRT_DAT
2
UMA@ 0_0402_5%
CRT_CLK
2
UMA@ 0_0402_5%

2

1

1

1
R92

DAC_GRN

JVGA_VS

1
2

UMA ONLY BYPASS
DAC_RED

3

JVGA_HS

1

1

E

+5VS

2

2

C137
10P_0402_50V8J

R_L

R682 0_0603_5%
1
2

RED

G_L

R683 0_0603_5%
1
2

GREEN

B_L

R684 0_0603_5%
1
2

1

1

1

2

2

2

1

C809@
22P_0402_50V8J
C808@
C810 @
22P_0402_50V8J22P_0402_50V8J

HYBRID@

1

C136
10P_0402_50V8J
C145
10P_0402_50V8J
C157
2 10P_0402_50V8J
2
2

SVT

10P_0402_50V8J 10P_0402_50V8J

BLUE

1

+5VS

+CRT_VCC

D21

2

2

19
VGA_CRT_R
19
VGA_CRT_G
19
VGA_CRT_B
19 VGA_HSYNC
19 VGA_VSYNC
19 VGA_DDCDATA
19 VGA_DDCCLK

VGA_DDCDATA
VGA_DDCCLK

27
25
22
20
18
12
14

0B1
1B1
2B1
3B1
4B1
5B1
6B1

A0
A1
A2
A3
A4

1
2
5
6
7

CRT_R
CRT_G
CRT_B
HSYNC_G
VSYNC_G

SEL1

8

DGPU_SELECT#

A5
A6

9
10

CRT_DAT
CRT_CLK

SEL2

30

PMEG2010ET SOT23

Trace length <3.6' from switch to conn.

2

VDD
VDD
VDD
VDD
VDD

L: A -> B1(VGA)
H: A -> B2(PCH)

+3VS

2

1

+CRT_VCC

DGPU_DDC_SEL#

3
11
28
31
33

4

R158
2.2K_0402_5%
CRT_DDC_DAT_CONN

3

JCRT1
+CRT_VCC_F

Q99B
2N7002DW -T/R7_SOT363-6

1
2
3
4
5
6
7
8
9
10
11
12
13
14

RED

PI3V712-AZLEX_TQFN32_6X3~D

From PCH

C629
0.1U_0402_16V4Z

1

R157
2.2K_0402_5%

2

GND
GND
GND
GND
GPAD

2

0B2
1B2
2B2
3B2
4B2
5B2
6B2

2

26
24
21
19
17
13
15

5

DAC_RED
DAC_GRN
DAC_BLU
CRT_HSYNC
CRT_VSYNC
CRT_DDC_DATA
CRT_DDC_CLK

1

2
15 DAC_RED
15 DAC_GRN
15
DAC_BLU
15 CRT_HSYNC
15 CRT_VSYNC
15 CRT_DDC_DATA
15 CRT_DDC_CLK

F1
1.1A_6V_SMD1812P110TF

W=40mils
DGPU_SELECT# 16,27

1

From VGA

4
16
23
29
32

1

GREEN

1

CRT_DDC_CLK_CONN

6

BLUE
Q99A
2N7002DW -T/R7_SOT363-6

@
C178
100P_0402_50V8J

2

JVGA_HS
CRT_DDC_DAT_CONN
CRT_DDC_CLK_CONN
+CRT_VCC

E&T_3703-E12N-03R
ME@

1

DGPU_DDC_SEL#

C619
0.1U_0402_16V4Z

16,27

CRT Connector

2

HSYNC_G

2

A

R162
2.2K_0402_5%
HYBRID@

JVGA_HS

1

2

R956
1K_0402_5%

1

1

P
VSYNC_G

A
3

G

2

1

5

2
OE#

C620
0.1U_0402_16V4Z

CRT_VSYNC_1
4
1
2
L31
FCM1608CF-121T03 0603
U25
SN74AHCT1G125DCKR_SC70-5

JVGA_VS

Y

1

4

2

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

@
C626
10P_0402_50V8J

2

+CRT_VCC

2

2

R159
2.2K_0402_5%
HYBRID@
VGA_DDCDATA
VGA_DDCCLK

CRT_HSYNC_1
4
1
2
L32
FCM1608CF-121T03 0603
U26
SN74AHCT1G125DCKR_SC70-5

Y

1

1

3

G

+3VS_DELAY

3

1

0_0402_5%
DGPU_SELECT#
1
2
@
R443
0_0402_5%
1
2
DGPU_EDIDSEL#

5

R441

P

PVT

OE#

CRT_DDC_DATA
CRT_DDC_CLK

2

JVGA_VS

@
C177
68P_0402_50V8K

R610
2.2K_0402_5%

2

R381
2.2K_0402_5%

2

3

1

1

1

+3VS

1

1
2
3
4
5
6
7
8
9
10
11
12
G1
G2

B

C

D

Title

@ C625
10P_0402_50V8J

4

Compal Electronics, Inc.
CRT Connector

Size
Document Number
Custom
Date:

Rev
0.3

LA-5941P

Thursday, April 08, 2010

Sheet
E

26

of

50

http://hobi-elektronika.net

2

3

220K_0402_5%
ENVDD#_R

3

DCR_EN

PVT,chg AO3413 main

+LCDVDD

1

1

R392
2.2K_0402_5%

2

1

2

R395
2.2K_0402_5%

CONN_LVDS_A1
CONN_LVDS_A1#
CONN_LVDS_A0
CONN_LVDS_A0#

+LCDVDD_CONN
CONN_LVDS_SDA
CONN_LVDS_SCL

2
C33

4.7U_0805_10V4Z

3

R65
@
100K_0402_5%

CONN_LVDS_A2
CONN_LVDS_A2#

+LCDVDD_CONN

FBMA-L11-201209-221LMA30T_0805

OUT
1

IN

GND

2

19 VGA_ENVDD_R

L2

DISPOFF#
INVPWM
2 680_0402_5% LCD_COLOR_1
CONN_LVDS_ACLK
CONN_LVDS_ACLK#

1

680P_0402_50V7K
C14
@

W=60mils

R370 1

34 LCD_COLOR_EN

+3VS

0.1U_0402_16V4Z

Q95
DTC124EKAT146_SC59-3

2

R37
@
100K_0402_5%

1

1
OUT
3

1

IN

GND

2

PCH_ENVDD

2

C34

Q4
SI2301BDS-T1-E3_SOT23-3

D

D

15

34

SVT

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ACES_88341-3000B001

C539
4.7U_0805_10V4Z

+3VS

1

2

W=60mils
C25
0.1U_0402_16V4Z

+3VS

DMIC

Q12
DTC124EKAT146_SC59-3

33 INT_MIC_DATA
33 INT_MIC_CLK
16
16

CMOS

JLVDS1

2

2

2

B+

1 R549

USB20_P2
USB20_N2

USB20_P2
USB20_N2

2

+CMOS_PW

C567
680P_0402_50V7K
@

1

1

2

2

2 0_0805_5%

C566
4.7U_0805_25V6-K

INVPWM
DCR_EN
C15
1 @

2

1 @
C13
2

D

DISPOFF#

1 @
C296
2

For EMI

+3VS

1

1

G

R38
ENVDD#

2
G

S

1

2

1

LCD_COLOR_1

1 @
C370

R250
4.7K_0402_5%

D12
34

2

W=60mils

D36 CH751H-40PT_SOD323-2
2
1

1

+LEDVDD

470P_0402_50V7K

R31
1K_0402_1%

D
Q3
2N7002_SOT23 S

2

470P_0402_50V7K

1

+3VS

SVT

R13
150_0603_1%

3

LCD POWER CIRCUIT

+5VALW

470P_0402_50V7K

4

+LCDVDD

470P_0402_50V7K

5

BKOFF#

BKOFF#

1

DISPOFF#

2

CH751H-40PT_SOD323-2

ME@

DGPU_EDID_SEL#

54

SEL2

52
5
51

NC
NC
NC

B

57

Thermal_GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1
2

CONN_LVDS_SDA

2
G

DGPU_PWMSEL#

R260
1

Q46A @
2N7002DW-T/R7_SOT363-6

R259
1

19 NV_INVTPWM

DGPU_EDID_SEL#

34

L: B1 -> A (VGA)
H: B2 -> A (PCH)
PCH_EDID_CLK

4

PCH_EDID_DATA

0_0402_5%
2

R207 0_0402_5%
1
2
HYBRID@

INVT_PWM

DGPU_PWMSEL#

+3VS

@

2

A

3

CONN_LVDS_SCL

+3VS

Q47B @
2N7002DW-T/R7_SOT363-6

1

0_0402_5%
2
@

5

TO LVDS Connector

16

1

6

P

DGPU_SELECT#

1

OE#

17

VGA_LVDS_SDA

D
Q43
2N7002_SOT23 S

G

CONN_LVDS_A0#
CONN_LVDS_A0
CONN_LVDS_ACLK
CONN_LVDS_ACLK#
CONN_LVDS_A2
CONN_LVDS_A2#
CONN_LVDS_A1#
CONN_LVDS_A1
CONN_LVDS_SCL
CONN_LVDS_SDA

CONN_LVDS_SCL

3

2
3
7
8
11
12
14
15
19
20

1
6
9
13
16
21
24
28
33
39
44
49
53
55

3

Q46B @
2N7002DW-T/R7_SOT363-6

5

SEL

4

15

CONN_LVDS_SDA

6

2

PCH_PWM

A

Q47A @
2N7002DW-T/R7_SOT363-6

1

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2

VGA_LVDS_SCL

P

46
45
41
40
35
34
30
29
25
26

DGPU_PWMSEL

C899
4.7U_0805_10V4Z

2

C

4
Y
U17
74AHC1G125GW_SOT353
HYBRID@
SVT LOW COST
3V Vcc 1G125 BUFFER
DGPU_PWMSEL
OE# A
Y
L
L
L
L
H
H
H
X
Z
4
Y
U6
74AHC1G125GW_SOT353
HYBRID@

OE#

LVDS_A0#
LVDS_A0
LVDS_ACLK
LVDS_ACLK#
LVDS_A2
LVDS_A2#
LVDS_A1#
LVDS_A1
PCH_EDID_CLK
PCH_EDID_DATA

15
LVDS_A0#
15
LVDS_A0
15 LVDS_ACLK
15 LVDS_ACLK#
15
LVDS_A2
15
LVDS_A2#
15
LVDS_A1#
15
LVDS_A1
15 PCH_EDID_CLK
15 PCH_EDID_DATA

C898
0.1U_0402_16V4Z

HYBRID@

G

FROM PCH LVDS

HYBRID@ 1

3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

4
10
18
27
38
50
56

5

VCC
VCC
VCC
VCC
VCC
VCC
VCC

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1

PVT

1

48
47
43
42
37
36
32
31
22
23

2

VGA_LVDS_A0#
VGA_LVDS_A0
VGA_LVDS_ACLK
VGA_LVDS_ACLK#
VGA_LVDS_A2
VGA_LVDS_A2#
VGA_LVDS_A1#
VGA_LVDS_A1
VGA_LVDS_SCL
VGA_LVDS_SDA

20 VGA_LVDS_A0#
20 VGA_LVDS_A0
20 VGA_LVDS_ACLK
20 VGA_LVDS_ACLK#
20 VGA_LVDS_A2
20 VGA_LVDS_A2#
20 VGA_LVDS_A1#
20 VGA_LVDS_A1
19 VGA_LVDS_SCL
19 VGA_LVDS_SDA

PWMSEL#
R35
1K_0402_1%

L: VGA
H: PCH

5

FROM VGA LVDS

2

C

+3VS

DGPU_EDID_SEL

EDIDSEL#

+3VS

PVT, change TI to ST main
U42

3

LVDS switch1

R161 0_0402_5%
1
2
UMA@

B

INVPWM

ST3DV520EQTR_QFN_56P_11X5
HYBRID@
DGPU_SELECT#

CMOS Camera

LVDS_A0
LVDS_A0#

0_0402_5%
0_0402_5%

2 UMA@ 1 R383
2 UMA@ 1 R382

CONN_LVDS_A0
CONN_LVDS_A0#

LVDS_A1
LVDS_A1#

0_0402_5%
0_0402_5%

2 UMA@ 1 R389
2 UMA@ 1 R388

CONN_LVDS_A1
CONN_LVDS_A1#

LVDS_A2
LVDS_A2#

0_0402_5%
0_0402_5%

2 UMA@ 1 R386
2 UMA@ 1 R387

CONN_LVDS_A2
CONN_LVDS_A2#

LVDS_ACLK
LVDS_ACLK#

0_0402_5%
0_0402_5%

2 UMA@ 1 R384
2 UMA@ 1 R385

CONN_LVDS_ACLK
CONN_LVDS_ACLK#

5

3

2
1

Q64
2N7002W-T/R7_SOT323-3
HYBRID@

DGPU_BKL_SEL

IN

R69 @
100K_0402_5%

3

A

3

CMOS@

Q74 CMOS@
SI2301BDS-T1-E3_SOT23-3

+CMOS_PW

0.1U_0402_16V4Z

+CMOS_PW_R
Q21 CMOS@
DTC124EKAT146_SC59-3

1

2

PVT,chg AO3413 main R304 CMOS@
0_0603_5%

2010/01/13

1

2

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C326

2

Compal Secret Data

Security Classification
Issued Date

CMOS_EN_RC#

1

2

+3VS

2

R54
CMOS@
220K_0402_5%

2

2

CMOS_EN

1

2
G

CONN_LVDS_SCL
CONN_LVDS_SDA

R440 1K_0402_1%
1
2
1
HYBRID@

1

C609 @
4.7U_0805_10V4Z

2

1

3
2 UMA@ 1 R393
2 UMA@ 1 R394

ENBKL

S

PCH_EDID_CLK 0_0402_5%
PCH_EDID_DATA 0_0402_5%

2 UMA@ 1 R575

34

DGPU_SELECT#

D

0_0402_5%

2CAM_ENG

Q38 @
2N7002_SOT23 S

4

U19
74AHC1G125GW_SOT353
HYBRID@

UMA SW BYPASS
PCH_ENBKL

Y

1

A

OUT

2

GND

PCH_ENBKL

1

3

15

W=40mils

R270 CMOS@
100K_0402_5%

D

3

+3VS

R66 @
150_0603_1%

1

3

DGPU_EDID_SEL

Replace FET inverter Q42

+3VS

34

2

G
4

5

Y

Y

+5VALW

1

ENBKL
4
ENBKL
U18
74AHC1G125GW_SOT353
HYBRID@
R970
100K_0402_1%
DGPU_BKL_SEL

A

G

3

1

5
P
A
3

S

2

+CMOS_PW

1

1

VGA_ENABLT

U16 @
NC7SZ14P5X_NL_SC70-5

P

R371

2 DGPU_EDID_SEL#
G

19

NC

D

@ C260
0.1U_0402_16V4Z
0_0402_5%
2
2
DGPU_SELECT# 16,26
@
0_0402_5%
DGPU_EDID_SEL# 2
2
DGPU_EDIDSEL# 16,26

G

2

1

@ Q42
2N7002W-T/R7_SOT323-3

P

1
R372

OE#

PVT

1

DGPU_EDID_SEL

+3VS

D

R33
@
1K_0402_1%

OE#

1

1

5

+3VS

G

SVT

S

+3VS

2

Title

C337 CMOS@
10U_0805_10V4Z

A

Compal Electronics, Inc.
LVDS/CAMERA

Size
Document Number
Custom
Date:

Rev
0.3

LA-5941P

Thursday, April 08, 2010

Sheet
1

27

of

50

http://hobi-elektronika.net

A

B

C

Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card(WLAN/WiMAX)

+3VALW

R68
2
1
0_0603_5%

1

JPCIE3

1
3
5
7
9
11
13
15

WLAN_CLKREQ1#

14 WLAN_CLKREQ1#

14 CLK_PCIE_WLAN1#
14 CLK_PCIE_WLAN1

1

PCI_RST#_R
CLK_PCI_DB

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
54

14 PCIE_PRX_DTX_N2
14 PCIE_PRX_DTX_P2
14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2
+JPCIE3_3.3

34,35 EC_TX_P80_DATA
34,35 EC_RX_P80_CLK

EC_TX_P80_DATA 1
EC_RX_P80_CLK 1

PVT

100_0402_1%
R274
2
2
R273
100_0402_1%

R336
100K_0402_5%
1
2

E

+1.5VS

R352
2
1
0_0603_5%

JPCIE3_1.5

PCIE_WAKE#

15 PCIE_WAKE#

D

+3VS

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
G2

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G3
G4

+JPCIE3_3.3

2
4
6
8
10
12
14
16

2

1

C421
0.1U_0402_16V4Z

2

+JPCIE3_3.3

1

C423
0.1U_0402_16V4Z

2

1

C422 @
0.1U_0402_16V4Z

Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

D31
WLAN_LED_R1#

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
55
56

R377 1

2

C425
10U_0805_10V4Z

2

2 @ 0_0402_5%
0_0402_5%
2

R374 1
R373 1

2 @ 0_0402_5%
2 @ 0_0402_5%

2

WLAN_LED#

WLAN_LED#

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

34,38

CH751H-40PT_SOD323-2

0_0402_5%

R376 1
R375 1

1

WL_OFF# 34
BUF_PLT_RST#

@

5,16,29

+3VALW
+3VS
SMB_CLK_S3 10,11,12,14
SMB_DATA_S3 10,11,12,14

R284
R285
R286
R287
R288
R290

@
@
@
@
@
@

1
1
1
1
1
1

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PCI_RST#

LPC_FRAME# 13,34
LPC_AD3 13,34
LPC_AD2 13,34
LPC_AD1 13,34
LPC_AD0 13,34
PCI_RST# 16,34
CLK_PCI_DB 14

1

D32
WIMAX_LED1#

1

USB20_N8 16
USB20_P8 16

2

WLAN_LED#

CH751H-40PT_SOD323-2
@

WIMAX_LED1#
WLAN_LED_R1#
MINIBT_LED1#

SVT

SVT
R672
1

D33
MINIBT_LED1#

1

BELLW_80052-1021

2

37

WLAN_LED#

BT_LED#

2

WLAN_LED#

0_0402_5%
@

CH751H-40PT_SOD323-2
@

ME@

H=1.7mm, P/N : DC040006S00
+3VS

Mini-Express Card(WWAN 3G)

R353 3G@
2
1
0_0603_5%

JPCIE2

PCIECLKREQ3#

14 PCIECLKREQ3#

14 CLK_PCIE_CARD_PCH#
14 CLK_PCIE_CARD_PCH

1
3
5
7
9
11
13
15

14 PCIE_PTX_C_DRX_N4
14 PCIE_PTX_C_DRX_P4
+JPCIE2_3.3

@

+JPCIE2_3.3

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53
54

JPCIE2_1.5
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R368 1 3G@

R366 1
R365 1

13 SATA_DTX_C_IRX_P1
13 SATA_DTX_C_IRX_N1

0.01U_0402_16V7K
0.01U_0402_16V7K

13 SATA_ITX_C_DRX_N1
13 SATA_ITX_C_DRX_P1

34

SSD_DET#

2
2

1

C417
0.1U_0402_16V4Z
2 3G@

C419
0.1U_0402_16V4Z
2 3G@

1

WLAN_LED_R2#

1

2

Vn

0_0402_5%

3G_OFF#

WLAN_LED#
3

CH2

6

CH3

+3VS

JSIM1

34
D35
WIMAX_WWAN_LED2#

1

2

WLAN_LED#

CH751H-40PT_SOD323-2
USB20_N13
USB20_P13

16
16

4
5
6
7

UIM_VPP
UIM_DATA

SVT

SMB_CLK_S3
SMB_DATA_S3

2 @ 0_0402_5%
2 @ 0_0402_5%

@
3G@

GND
VPP
I/O
DET

VCC
RST
CLK

@
1

GND
GND

DAN217T146_SC59-3
3
1
2

40mil

+UIM_PWR
UIM_RST
UIM_CLK

1
2
3

8
9

2

D5

1

2

C176
0.1U_0402_16V4Z

3G@

TAITW_PMPAT6-06GLBS7N14N0
ME@

1

2

C418 3G@
10U_0805_10V4Z

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
54

1
3
5
7
9
11
13
15

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

3

+3VS

JPCIE1
1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+1.5VS

R128 SSD@
+JPCIE1_3.3 2
1
0_0603_5%
JPCIE1_1.5
1

1

C386
0.1U_0402_16V4Z
2 SSD@

R177 SSD@
2
1
0_0603_5%

C431
0.1U_0402_16V4Z
2 SSD@

SSD Pin Table
R380 1 SSD@
DA/DSS

2

0_0402_5%

Pin Number

+3VS

SATA Assignment

11

T27

+JPCIE1_3.3

13
17

1

2

1

C388
0.1U_0402_16V4Z

SSD@

2

1

C387
0.1U_0402_16V4Z

SSD@

2

C372
0.1U_0402_16V4Z

19
+B (port 1)

23

-B (port 1)

25

SSD@

GND
GND

30

45

DA/DSS

47

SSD_DET#

32

ME@

DA/DSS (NEW)
-A (port 1)

31

P-TWO_A54402-A0G16-N

4

33

SSD_DET# (NEW)
+A (port 1)

4

STD H=4.0mm, P/N : SP01000KQ00

Compal Secret Data

Security Classification

Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

B

C

D

Compal Electronics, Inc.
Mini-Card/Nwe Card/SIM

Size

Document Number

Rev
0.3

LA-5941P
Date:

A

2

5

Vp

3G@

GND1
GND2

SSD_DET#

1 +UIM_PWR
R152

2

+UIM_PWR

EVT 0324 SSD Pin Define
please pull high by EC internal

2

2

D34

+JPCIE2_3.3

1B+
2 0.01U_0402_16V7K
1B#
2 0.01U_0402_16V7K
SSD@
SSD@
SATA_ITX_DRX_N1
1 C427
SATA_ITX_DRX_P1
1 C428
SSD@
+JPCIE1_3.3
SSD@

R578 1 @
100K_0402_5%

UIM_DATA

4

CH4

10K_0402_5%

WIMAX_WWAN_LED2#
WLAN_LED_R2#

T28
R506 SSD@
0_0402_5%
DA/DSS_NEW
SSD_DET#_NEW
2
1
EC_TX_P80_DATA 1
2 SSD_P80_DAT
EC_RX_P80_CLK 1 SSD@ 2 SSD_P80_CLK
R339 0_0402_5%
SSD@
R343 0_0402_5%
PVT

+3VS

CH1

+3VS

BUF_PLT_RST#
0_0402_5% +3VALW
2 @
2 @ 0_0402_5%
+3VS

USB20_N13
USB20_P13

Mini-Express Card( Only for SSD)

C426 1
C424 1

2

R367 1
R369 1

H=4.0mm, P/N : DC020910200

SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1

1

@

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

BELLW_80053-1021
ME@

3

R88
3G@
2
1
0_0603_5%

CH751H-40PT_SOD323-2

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

14 PCIE_PRX_DTX_N4
14 PCIE_PRX_DTX_P4

D4
@
CM1293-04SO_SOT23-6

+1.5VS
2
4
6
8
10
12
14
16

C188
4.7U_0805_10V4Z

2

1
3
5
7
9
11
13
15

R151
10K_0402_5%
2
1

PCIE_WAKE#

Sheet

Thursday, April 08, 2010
E

28

of

50

http://hobi-elektronika.net

A

B

C

+3V_LAN

+5VALW

1

+3VALW

@

R972
150_0603_1%

W=60mils

R973
100K_0402_5%

LAN_EN-

1

WOL_EN_RC#

2

2

1

SI2301BDS-T1-E3_SOT23-3

1

2

Q97

C1211

+3V_LAN
3VLANOUT

0.1U_0402_16V4Z

W=60mils

1 R726

2 0_0805_5%

PVT,chg AO3413 main

Q5
DTC124EKAT146_SC59-3

C748

L48
1

1

1

C750

C751

1

1

2

C1218
47P_0402_50V8J

Place Close to Pin 2

2

2

S INDUC_ 4.7UH +-20% SIA4012-4R7M
+1.8_VDD/LX
2

close to pin1

C594
10U_0805_10V4Z

+3V_LAN

U30

1

1

1

TW SI_DATA
TW SI_CLK
LED_LINK10_100n
LED_ACTn

30
29
48
47

SPI_CS/LED_DUPLEXn/LED_DUPLEXn
VDD3V/VDDHO/VDDHO

27

SPI_DI/NC/LED_Link1000n

26

1000_LINK_LED

REFCLKN
REFCLKP

40
41

REFCLKN
REFCLKP

TXN0/TXN0/TRXN0
TXP0/TXP0/TRXP0
RXN1/RXN1/TRXN1
RXP1/RXP1/TRXP1
NC/NC/TRXN2
NC/NC/TRXP2
NC/NC/TRXN3
NC/NC/TRXP3

14
13
18
17
21
20
24
23

VDDHO/VDD18O/VDD18O

2

2

close to pin6
2
C667

+AVDD_CEN

1
0.1U_0402_16V4Z

1
C656

6

CTR12

2
0.1U_0402_16V4Z

5

close to pin5
3

5,16,28 BUF_PLT_RST#

1 R656

+3V_LAN

7

2

4.7K_0402_5%

LAN_WAKE#

C246 1
C247 1

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

PCIE_IRX_C_PTX_N3
PCIE_IRX_C_PTX_P3
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

XTALO
LAN_XTALI

3

1

2 2.37K_0402_1%

VDDLO/CTR12/CTR12
PERSTn
VAUX_AVL/VBG1P18/VBG1P18

4
37
38
44
43

W AKEn
TX_N
TX_P
RX_N
RX_P

9
10

XTLO
XTLI

34
35

TESTMODE
NC

31
33

SMCLK
SMDATA

49
R67

VDD3V

SVT
R654
4.7K_0402_5%
@

10/100_LINK_LED
ACTIVITY# 30

10/100_LINK_LED

D30
1

1000_LINK_LED

1

12

㪘㫋㪿㪼㫉㫆㫊

2
0_0402_5%

MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

C663
0.1U_0402_16V4Z
2
2
C664 0.1U_0402_16V4Z
MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

42
39
36
22
16
11
8

+AVDDVCO2
+1.2_AVDDL

DVDDL0
AVDDL/DVDDL/DVDDL
DVDDL1
SPI_CLK/DVDDL/DVDDL

46
45
32
28

+1.2_DVDDL

SPI_DO/AVDDH/AVDDH
AVDDH0
AVDDH1

25
19
15

GND

2

CH751H-40PT_SOD323-2

CLKREQ_LAN# 14

1
1

AVDDL0
AVDDL1
AVDDL2
DVDDL/AVDDL/AVDDL
AVDDL3
AVDDL4
AVDDL5

PVT
LAN_SK# 30

2

30
30
30
30
30
30
30
30

Place Close to LAN chip

CLK_PCIE_LAN# 14
CLK_PCIE_LAN 14

close to pin40,41

R150
1
R94
1
R84
1
R36
1
R171
1
R85
1
R170
1
R172
1

MDI0+
MDI0MDI1+
MDI1MDI2+

AR8121/8131

RBIAS

1
R601

CH751H-40PT_SOD323-2
2

D29

2

+3V_LAN

14
14
14
14

1

close to L48

C676
0.1U_0402_16V4Z

34

C749

RF 10/22

LAN Power Circuit & Soft start
+AVDD_CEN

1

10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
2
2
10U_0805_10V4Z
1000P_0402_50V7K

2

R975
@
100K_0402_5%

IN

3

2

WOL_EN

GND

OUT

1

1

1

3

220K_0402_5%
D

34

C1210 @
4.7U_0805_10V4Z

2

G

2
G

Q96 @
2N7002_SOT23 S

3

R974

S

1

2

1
D
1

D

MDI2MDI3+

+AVDDVCO1
+1.2_AVDDL

MDI3-

49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2
49.9_0402_1%
2

1

2 C245 0.1U_0402_16V4Z

1

2 C243 0.1U_0402_16V4Z

1

2 C658 0.1U_0402_16V4Z

1

2 C238 0.1U_0402_16V4Z

close to pin19
3

C654
0.1U_0402_16V4Z

+1.2_AVDDL

CTR12
C674
1U_0402_6.3V4Z

close to pin15

1

1

1

2

2

2

C650
0.1U_0402_16V4Z

close to pin11

AR8131L-AL1E_QFN48_6X6 GIGA@

PVT

SA000038N00 S IC AR8131L-AL1E QFN 48P E-LAN CTRL

close to pin25
1

SA000031Z00

R602
1
@

2

R390
0_0603_5%

0_0603_5%
2

C655
1000P_0402_50V7K

close to pin36
close to pin16

2

XTALO

R391
0_0402_5%

NBLG0_DVT

+1.2_DVDDL
1
C251
1U_0402_6.3V4Z

C248
C244
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
1

2

2

2

2

1
1

2

C652
0.1U_0402_16V4Z

1

1

1

25MHZ_20PF_7A25000012

1

1

2
2
C661
0.1U_0402_16V4Z

2
2
C662
0.1U_0402_16V4Z

2

C647
0.1U_0402_16V4Z

L37

2

+AVDDVCO2

2
0_0603_5%

1

2

C660
0.1U_0402_16V4Z

close to pin8
If overclocking, R602 , L37 stuffed and R390 removed.

4

close to pin46
If not overclocking, R390 , L37 suffed and R602 removed.
AR8131:L37=0ohm (more power saving mode)

close to pin22
1

2

C649
27P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2

C653
1U_0402_6.3V4Z

1
1

2

2 LAN_XTALO

C665
27P_0402_50V8J

1

close to pin28

4

Y3

GIGA@
C659
1U_0402_6.3V4Z

1

C648
C657
0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.2_AVDDL
LAN_XTALI

+AVDDVCO1

1

B

C

Title

AR8131/ AR8132
Size Document Number
Custom
Date:

Rev
0.3

Thursday, April 08, 2010
D

Sheet

29

of

50

5

http://hobi-elektronika.net
4

+AVDD_CEN

3

2

1

C666

1

2
1U_0402_6.3V4Z

1

2

R430
0_0603_5%

Close to T20
D

D

T22

GIGA@
C669 2
1 0.01U_0402_16V7K

GIGA@
C671 2
1 0.01U_0402_16V7K

C672 2

29

MDI3+

29

MDI3-

29

MDI2+

29

MDI2-

29

MDI1+

29

MDI1-

TD1+

MDI3-

3

TD1-

MDI0+

1:1

MCT1

24

MCT3

MX1+

23

MDO3+

MX1-

22

MDO3-

MCT2

21

MCT2

MX2+

20

MDO2+

MDO2-

4

TCT2

MDI2+

5

TD2+

MDI2-

6

TD2-

MX2-

19

7

TCT3

MCT3

18

MCT1

8

TD3+

MX3+

17

MDO1+

MDI1+

MDI1-

1 0.01U_0402_16V7K
29

TCT1

2

1 0.01U_0402_16V7K

C

C668 2

1
MDI3+

MDI0+

1:1

1:1

9

TD3-

MX3-

16

MDO1-

10

TCT4

MCT4

15

MCT0

11

TD4+

MX4+

14

MDO0+

1:1

R97

2 GIGA@ 1 75_0402_5%

R126

2 GIGA@ 1 75_0402_5%

R95

1 75_0402_5%

2

C

R96

2

1 75_0402_5%

40mil
C670

Place close to TCT pin

1000P_1206_2KV7K
29

MDI0-

MDI0-

12

TD4-

MX4-

13

MDO0-

1

2

350uH_NS892406
GIGA@

T22

RJ45 Conn.
SANTA_130452-D
29

ACTIVITY#

ACTIVITY#

R179

2

1 300_0402_5%

1
1

NS892404
100@

R125
5.1K_0402_5%

2

2

B

C249
@ 68P_0402_50V8K

close to LED

LAN_SK#

LAN_SK#

R600

2

Yellow LED-

8

PR4-

G1

13

MDO3+

7

PR4+

G2

14

MDO1-

6

PR2-

MDO2-

5

PR3-

MDO2+

4

PR3+

MDO1+

3

PR2+

MDO0-

2

PR1-

MDO0+

1

PR1+

10

1 300_0402_5%

9

B

Green LED+
Green LEDJRJ45
ME@

1

2

Yellow LED+

11
MDO3-

+3V_LAN
29

12

C613
68P_0402_50V8K
@

DC020910220

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LAN Magnetic & RJ45
Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
1

30

of

50

http://hobi-elektronika.net
4

3

+3VS +3VS

1

1

VDD

SMCLK

10

EC_SMB_CK2 14,34

2

DP1

SMDATA

9

EC_SMB_DA2 14,34

REMOTE1-

3

DN1

ALERT#

8

4

DP2

THERM#

7

REMOTE2-

5

DN2

GND

6

Close U20

1

Q39
MMST3904-7-F_SOT323-3

2
B
2

D

3

E

REMOTE1-

REMOTE1+

REMOTE2+

C

Under WWAN

REMOTE2+
@
C324
100P_0402_50V8J

1

1

C443
0.1U_0402_16V4Z

R461
10K_0402_5%
@

1

C
Q22
MMST3904-7-F_SOT323-3

2
B
2

E

3

2

2

U20

@
C508
100P_0402_50V8J

2

+3VS

1

Close to DDR

REMOTE1+
R460
10K_0402_5%
@

D

2

1

SMSC thermal sensor
placed near by VRAM

1

5

REMOTE2REMOTE1+
EMC1403-2-AIZL-TR_MSOP10

1
C449
2200P_0402_50V7K

2

REMOTE1-

REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

Address 1001_101xb
P/N SA000029210

REMOTE2+

1

C

C651
2200P_0402_50V7K

2

C

REMOTE2-

FAN1 Conn
+5VS
JFAN1
34
EC_TACH
34 EC_FAN_PW M

C714
10U_0805_10V4Z

2

2

1

1

1
2
3
4
5
6

EC_TACH
EC_FAN_PW M

C593
10U_0805_10V4Z

1
2
3
4
G1
G2
ACES_85204-04001
ME@

B

B

SP02000CW00

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

EMC1403_Thermal sensor/FAN
Size
Document Number
Custom
Date: Thursday, April 08, 2010

Rev
0.3

LA-5941P
Sheet
1

31

of

50

A

B

http://hobi-elektronika.net
C

D

E

F

G

H

SATA HDD Conn.
JHDD1

13 SATA_ITX_DRX_P0
13 SATA_ITX_DRX_N0
13 SATA_DTX_C_IRX_N0
13 SATA_DTX_C_IRX_P0

1

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

C434 1
C433 1

1
2
3
4
5
6
7

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

+3VS

SATA_DTX_IRX_N0
SATA_DTX_IRX_P0

1 R574

2

+3VS_HDD

0_0805_5%

+5VS_HDD
+5VS
+3VS
1 R576

+5VS_HDD

2 0_0805_5%
1

2

1
C125
1000P_0402_50V7K

2

1
C126
0.1U_0402_16V4Z

2

1
C124
1U_0603_10V6K

2

1
C123
10U_0805_10V4Z

2

1
C122
10U_0805_10V4Z

2

@
C121
0.1U_0402_16V4Z

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
RX+
RXGND
TXTX+
GND

1

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

GND

23

GND

24

SUYIN_127043FB022G272ZR
ME@

2

2

3

3

4

4

Issued Date

2010/01/13

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

E

F

Title

HDD/ODD Connector
Size
B

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Date:
G

Sheet

32
H

of

50

http://hobi-elektronika.net

5

4

3

2

CA57

1

1

2
1

@

1

CA1

2

1
@

37

HDA_RST_CODEC#

External MIC 37

2
CA13
100P_0402_50V8J
@

CA21
1
1

4.7U_0805_10V4Z

CA22

2

27 INT_MIC_CLK
PVT

34

EC_MUTE#
1
CH751H-40PT_SOD323-2
PVT,realtek AP note.
@

EC_MUTE#

EMI
CA18
100P_0402_50V8J

1
CA12

2
RA10

PLUG_IN

RA21

B

RA23

2
1
0_0402_5%

1
2
CA15
2.2U_0603_6.3V6K

259PD#

39.2K

PORT-I (PIN 32, 33)

Headphone out

20K

PORT-B (PIN 21, 22)

Ext. MIC

10K

PORT-C (PIN 23, 24)

CA47 1

2 0.1U_0603_50V7K

CA50 1

2 0.1U_0603_50V7K

25

38
AVDD2

10

BCLK

6

SDATA_OUT

5

SPDIFO
PCBEEP

35
31

MIC2_VREFO
MIC1_VREFO_R
LDO_CAP

CBP

HP_OUT_L
HP_OUT_R

Internal SPEAKER

RA4
RA5

75_0402_1%
75_0402_1%

DGND

CBN

VREF

MIC1_VREFO_L

JDREF

PVSS2
PVSS1
DVSS2
DVSS1
ALC259-GR_QFN48_7X7

CPVEE
AVSS1
AVSS2

8

AZ_SDIN0_HD_R

2
RA6

1
33_0402_5%

RA22 2

HDA_SDOUT_CODEC

13

HDA_SDIN1

0_0402_5%

1

13
C

EAPD

13

C1219
22PF_0402_50V9
@

2

Near PIN

34

RF 1022

48
20
29
30
28

LDO_CAP

27

AC_VREF2.5V

19

AC_JDREF 2 RA9

34

A_RVO
1
CA14

CA23 10U_0805_10V4Z
1
2

+MIC1_VREFO_R

1 20K_0402_1%
1

2
2.2U_0603_6.3V6K

26
37

1

CA17

2
2
0.1U_0402_16V4Z

CA16
10U_0805_10V4Z

AGND

2
0_0603_5%

2

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

EMI 1030

BEEP#

2

2
B

560_0402_5%

E

2
R335
2.4K_0402_1%

@

1

2

@

1

2

@

1

2

1
2
3
4

5
6

G1
G2

ACES_88266-04001
ME@

SP02000K200

@

A

1

1U_0603_10V6K

Q30
2SC2411KT146_SOT23-3

2

1

1 1

1

2
C352

2

PCH_SPKR

1 1

1U_0603_10V6K

EMI 1030

R311

SE074102K80

2
1

C345
@ 0.1U_0402_16V4Z

C

R310

3

C351
2

1
2
3
4

C635
1000PF_0402_25V7

FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603

C634
1000PF_0402_25V7

1U_0603_10V6K
PC_BEEP
1

2
2
2
2

C633
1000PF_0402_25V7

1

2

C374
2

1
1
1
1

C632
1000PF_0402_25V7

1

2

1

JSPK1
L19
L20
L22
L23

1

EC Beep

560_0402_5%

D15 @
RB751V_SOD323

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

2011/01/13

Deciphered Date

2

ICH Beep

13
HDA_BITCLK_CODEC

47

SVT change to SA00003QR10

SPK_R1SPK_R2+
SPK_L1SPK_L2+

R309

PC_BEEP1

13

HDA_SYNC_CODEC

wide 20MIL
R326
20K_0402_5%

10K_0402_5%

D16
RB751V_SOD323
@

A

Headphone

+5VS
+3VS

34

HP_OUTL 37
HP_OUTR 37

1

EAPD

SENSE B

36

place close to chip

B

1
RA18

PC Beep

SYNC

RESET#

SENSE A

1

CA6

place close to chip

(PIN 48)

5.1K

32
33

SDATA_IN

18

43
42
49
7

Function

HP_OUT_L
HP_OUT_R

PD#

13

1

CA5

SPK_R2+
SPK_R1-

MONO_OUT

39.2K_0402_1%

Codec Signals

46

39
PVDD1

1

PVT

1

CA4

2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z

SPK_OUT_R+
SPK_OUT_R-

GPIO1/DMIC_CLK

12

1

SPK_L2+
SPK_L1-

3
4

CA3

40
41

GPIO0/DMIC_DATA

11

U43

D

0.1U_0402_16V4Z
+5VS
1
1
CA59
@
@
CA58

2
2
10U_0805_10V4Z
RA3
0.1U_0402_16V4Z 2
1
+5VS
0_0603_5%

45
44

2

259PD#

+MIC1_VREFO_L

SENSE A

MIC2_L
MIC2_R

SENSE_A

1
20K_0402_1%

EC_MUTE#

Impedance

MIC1_L
MIC1_R

16
17

D7

SENSE_A
SVT,add

Sense Pin

21
22

HDA_RST_CODEC#

PC_BEEP
2
100P_0402_50V8J

place close to chip
MIC_JD

37

LINE2_L
LINE2_R

RA24

2

2
10U_0805_10V4Z

2
10U_0805_10V4Z

SPK_OUT_L+
SPK_OUT_L-

LINE1_L
LINE1_R

14
15

SVT

2

37

1

0_0402_5%

INT_MIC_CLK

1

MIC1_L
MIC1_R

27 INT_MIC_DATA

Internal MIC

C

9

DVDD

EXT_MIC_L
EXT_MIC_R

4.7U_0805_10V4Z
2
2

DVDD_IO

2

2

23
24

1

1

RA8
4.7K_0402_5%

1

2
RA7
4.7K_0402_5%
@

2

RA11
2
1
0_0603_5%
@
CA60

10U_0805_10V4Z

AVDD1

2

0.1U_0402_16V4Z
2
+AVDD

place close to chip
1103 add
RA12
4.7K_0402_5%

1

1

CA7
10U_0805_10V4Z
2

+MIC1_VREFO_R

+3VS

13 HDA_RST_CODEC#

1

PVDD2

ESD 1102
near pin

+5VS

1

place close to chip

+PVDD2
1
CA61

0.1U_0402_16V4Z

+MIC1_VREFO_L

1

CA43

2
10U_0805_10V4Z

+3VS_DVDD

10U_0805_10V4Z
2

CA8

CA44

1

CA2
D

2

2

JA1
JUMP_43X39

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CA56

1

RA1
2
1
0_0603_5%

+3VS

RA2
2
1
0_0603_5%

0.1U_0402_16V4Z

+PVDD1

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

ALC259 Codec

Size Document Number
Custom

Rev
0.3

LA-5941P

Date: Thursday, April 08, 2010

Sheet
1

33

of

50

http://hobi-elektronika.net

10_0402_5%

16 CLK_PCI_LPC
16,28 PCI_RST#

2
47K_0402_5%

16

2
C323
0.1U_0402_16V4Z

PCI_RST#
EC_RST#
EC_SCI#

EC_SCI#

1

1

2 CLKRUN#
SVT
R671
10K_0402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
EC_RF_LED#
G_SELFTEST

35

KSO[0..15]

35

KSI[0..7]

+3VALW
2 47K_0402_5% KSO1
2 47K_0402_5% KSO2

ENE UPDATE 08/10/21
1

28,38 WLAN_LED#
SVT

12
13
37
20
38

R685

2
38 G_SELFTEST

0_0402_5%

41
41
14,31
14,31

+3VS

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

R236 1

2 4.7K_0402_5%

EC_TACH

GEN_EN
BEEP#
EC_FAN_PWM
ACOFF

67

9
22
33
96
111
125

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

BATT_TEMP

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

DCR_EN

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
EC_USB_ON#
NOVO#
BT_EN
TP_CLK
TP_DATA

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

926C-STRAP
WOL_EN
ME_FLASH
LID_SW#

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

FRD#SPI_SI
FWR#SPI_SO
SPI_CLK
FSEL#SPICS#

PS2 Interface

GEN_EN 38
BEEP# 33
EC_FAN_PWM 31
ACOFF 40,42

KILL_SW#

SPI Flash ROM

GPIO

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

+3VALW
FRD#SPI_SI

2

FSEL#SPICS#

2

1
R262 @
100K_0402_1%
1
R271 @
100K_0402_1%

EC_SMB_CK1
R240
2.2K_0402_5%
EC_SMB_DA1

DCR_EN 27
PSI_ON# 8
IREF
42
CHGVADJ 42

IREF
CHGVADJ

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

FAN control by EC 09.09.08

BATT_TEMP 41
SSD_DET# 28
ADP_I 42
VOUTX 38
VOUTY 38
KILL_SW# 37

ADP_I

EC_MUTE# 33
NOVO# 38
BT_EN 37
TP_CLK 35
TP_DATA 35

R239
2.2K_0402_5%
2
R237
10K_0402_5%

EC_USB_ON#

1

LID_SW#

2

1
R325
100K_0402_1%

EC_MUTE#

1

2
R238 @
10K_0402_5%

T21 PAD
WOL_EN 29
ME_FLASH 13
LID_SW# 38

SPI Device Interface

SM Bus

BATT_TEMP

10/20 add

AVCC

21
23
26
27

PWM Output
AD

1
C297
1
C298
1
C328

ACIN

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

Touch Pad lock LED

U13

2 4.7K_0402_5%

SC500005I00

2

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

TP_CLK

+5VS

TP_DATA R235 1

DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

R357 560_0402_5%
1
2

2

LTW-C193TS5 0603 WHITE

VCC
VCC
VCC
VCC
VCC
VCC

2

1

1

CLKRUN#

KSI[0..7]

R263 1

1
2
3
4
5
7
8
10

T23 PAD
15

KSO[0..15]

R265 1

2

1

C327
1000P_0402_50V7K

1
R266

2

1

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

16
GATEA20
16
KB_RST#
13
SERIRQ
13,28 LPC_FRAME#
13,28
LPC_AD3
13,28
LPC_AD2
13,28
LPC_AD1
13,28
LPC_AD0

2
1
2
1
@ C340 22P_0402_50V8J @ R289
+3VALW

2

1

C341
1000P_0402_50V7K

2 1 ECAGND 2
FBM-11-160808-601-T_0603

1
L13

2

1

C329
0.1U_0402_16V4Z

C294
1000P_0402_50V7K

1

C339
0.1U_0402_16V4Z

+EC_AVCC

1

C319
0.1U_0402_16V4Z

2

C293
0.1U_0402_16V4Z

C290
0.1U_0402_16V4Z

L14 1
2
FBM-11-160808-601-T_0603

TP_LOCK#

PVT, for EC ROM fail
R978 0_0402_5%
1
2

FRD#SPI_SI 36
FWR#SPI_SO 36
FSEL#SPICS# 36

73
74
89
90
91
92
93
95
121
127

BATT_SEL_EC
CAP_INT
FSTCHG
BATT_CHG_LED#
TP_LOCK#
BATT_LOW_LED#
PWR_LED#
SYSON
VR_ON
ACIN

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
EC_ON
CMOS_EN
ICH_POK_EC
BKOFF#
WL_OFF#
AC_PRESENT
CAP_RST#

+3VS
SPI_CLK_R 36

1

ESB_CLK
2 R291
4.7K_0402_5%

1

ESB_DAT
2 R294
4.7K_0402_5%

1

CAP_INT
2 R241
10K_0402_5%

1

BATT_SEL_EC 42
CAP_INT 38
FSTCHG 42
BATT_CHG_LED# 38
BATT_LOW_LED# 38
PWR_LED# 38
SYSON 39,44
VR_ON 48
ACIN
40

2

RF 1103

C1220
22P_0402_50V8J
@

ESB Bus for ENE cap. sensor only,
not compatible with SMB bus

add

PVT

2

@
C292
100P_0402_50V8J

3G_OFF#
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
SUSP_LED#
LCD_COLOR_EN

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

GPI

2

122
123

XCLK1
XCLK0

2

C322

15P_0402_50V8J

KB926QFA1_LQFP128
XCLKO

1

XCLKI

PM_SLP_S4#
ENBKL
EAPD
EC_PROCHOT
SUSP#
PBTN_OUT#
EC_PME#

ICH_POK

1
2
R258 0_0402_5%

1
2
R251 100K_0402_1%
@

37

PM_SLP_S4# 15
ENBKL 27
EAPD
33
+3V_LAN

SUSP# 39,42,46
PBTN_OUT# 15
SUSP#

124
1

2

1

C320
4.7U_0603_6.3V6K

2

R292
10K_0402_5%
@

@
C318
1000P_0402_50V7K
place it nearby Lan
29

H_PROCHOT#

change to LCD_COLOR_EN

EC_PROCHOT

EC_SMB_CK2
EC_SMB_DA2

10/17 add

EC_PME#
2
0_0402_5%

1
R293

LAN_WAKE#

H_PROCHOT# 5,48

change to TP_LOCK#

11/09 change EC pin
2
20_0402_5%
0_0402_5%

+3VALW

ENE926E0 SA00001J5A0
PIN36

1
R3291
R330

EC_USB_ON#

3

15P_0402_50V8J

PIN91

ALS_CLK
ALS_DATA

1

USB_ON#

2

C321

38
38

Q63
2N7002W-T/R7_SOT323-3

ICH_POK 15

ECAGND

4

R264
10M_0402_5%
2

3

EPSON Q13MC1461005000
6.9x1.4x1.3mm
X2
32.768KHZ_12.5P_MC-146

1

1

EC_TACH

PVT

V18R
AGND

1

XCLKI
XCLKO

69

SUSCLK

@
2
0_0402_5%

GND
GND
GND
GND
GND

15

R345
10K_0402_5%

PVT, EC AP note
1
R327

11
24
35
94
113

PVT, Fan FB pull-up

2

1

+3VS

110
112
114
115
116
117
118

BKOFF# 27
WL_OFF# 28
AC_PRESENT 15
CAP_RST# 38

R344
+5VALW
10K_0402_5%
1
2

2

1

EC_RSMRST# 15
EC_LID_OUT# 14
EC_ON 38
CMOS_EN 27

1

2

@
C291
100P_0402_50V8J

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

D

EC_SMB_CK2
EC_SMB_DA2
1

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

2
G

@

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

VR_ON

2010/01/13

D
Q17
S 2N7002_SOT23

2
G

PVT, pull cpu_core nearby
VGATE 15,48

Compal Secret Data

Security Classification
Issued Date

R459
@
10K_0402_5%
1
2

1

@

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
PCH_TEMP_ALERT#
ESB_CLK
ESB_DAT
SUS_PWR_DN_ACK
INVT_PWM

15 PM_SLP_S3#
15 PM_SLP_S5#
16 EC_SMI#
16 PCH_TEMP_ALERT#
38
ESB_CLK
38
ESB_DAT
15 SUS_PWR_DN_ACK
27 INVT_PWM
31
EC_TACH
28
3G_OFF#
28,35 EC_TX_P80_DATA
28,35 EC_RX_P80_CLK
38
ON/OFF#
38 SUSP_LED#
27 LCD_COLOR_EN

R227
2.2K_0402_5%

3

R226
2.2K_0402_5%

S

+EC_AVCC

+3VALW

+5VS

LED1

+3VALW

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
BIOS & EC I/O Port

Size Document Number
Custom
Date:

Thursday, April 08, 2010

Rev
0.3

LA-5941P
Sheet

34

of

50

http://hobi-elektronika.net

5

4

3

2

1

KB Matrix 10/30
JKB1

INT_KBD Conn.
KSI[0..7]
D

KSI[0..7]

KSO[0..15]

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

34

KSO[0..15] 34

KSO2

C203 1

2 @ 100P_0402_50V8J

KSO1

C205 1

2 @ 100P_0402_50V8J

KSO15

C153 1

2 @ 100P_0402_50V8J

KSO7

C186 1

2 @ 100P_0402_50V8J

KSO6

C175 1

2 @ 100P_0402_50V8J

KSI2

C226 1

2 @ 100P_0402_50V8J

KSO8

C185 1

2 @ 100P_0402_50V8J

KSO5

C206 1

2 @ 100P_0402_50V8J

KSO13

C172 1

2 @ 100P_0402_50V8J

KSI3

C225 1

2 @ 100P_0402_50V8J

KSO12

C173 1

2 @ 100P_0402_50V8J

KSO14

C156 1

2 @ 100P_0402_50V8J

KSO11

C155 1

2 @ 100P_0402_50V8J

KSI7

C236 1

2 @ 100P_0402_50V8J

KSO10

C154 1

2 @ 100P_0402_50V8J

KSI6

C235 1

2 @ 100P_0402_50V8J

KSO3

C174 1

2 @ 100P_0402_50V8J

KSI5

C228 1

2 @ 100P_0402_50V8J

KSO4

C187 1

2 @ 100P_0402_50V8J

KSI4

C233 1

2 @ 100P_0402_50V8J

KSI0

C204 1

2 @ 100P_0402_50V8J

KSO9

C234 1

2 @ 100P_0402_50V8J

KSO0

C227 1

2 @ 100P_0402_50V8J

KSI1

C241 1

2 @ 100P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

EC DEBUG PORT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND2
GND1

D

JP11
+3VALW
28,34 EC_TX_P80_DATA
28,34 EC_RX_P80_CLK

EC_TX_P80_DATA
EC_RX_P80_CLK

1
2
3
4

1
2
3
4

ACES_85205-0400
ME@

26
25

E-T_6905-E24N-01R
ME@

C

C

To TP/B Conn.
+5VS

C150

ME@

0.1U_0402_16V4Z

34
34

TP_CLK
TP_DATA

ACES_85201-04051
4 4 GND 6
3 3 GND 5
2 2
1 1

TP_CLK
TP_DATA

1

2

@
C151
100P_0402_50V8J

1

2

@
C152
100P_0402_50V8J

JTP1

2

3

SP01000KC00
B

B

1

D22
PACDN042Y3R_SOT23-3
@

SCA00000G00
ESD 1104 CHANGE

A

A

Compal Secret Data

Security Classification
2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
KB /SW /LPC Debug Conn.

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet
1

35

of

50

http://hobi-elektronika.net
FOR EC 256KB SPI ROM
(150mil PACKAGE)
20mils
1

+3VALW

1
C265
0.1U_0402_16V4Z

R217
10K_0402_5%
2

U9

Changed to BEAD for EMI.
Close to EC after C1220
R215

SPI_SO_EC
1
R201

2 15_0402_5%

FWR#SPI_SO

R216
0_0402_5%
@

FWR#SPI_SO 34

Colse to EC

W25X20BVSNIG_SO8

1

1

C266
10P_0402_50V8J
2

SA00003GM10

C264
12P_0402_50V8J
@

EMI

FD1
1

2

3G

FD4

FD2

1

FD3

1

1

H6
HOLEA

H7
HOLEA

A:H_2P8
H1
HOLEA

H2
HOLEA

H3
HOLEA

H4
HOLEA

H5
HOLEA

H8
HOLEA

H10
HOLEA

H11
HOLEA

H12
HOLEA

1

5

SPI_CLK_L
SPI_CLK_R 34

1

SI

FBMA-10-100505-101T 0402
2

1

GND

1

2

4

SPI_CLK_L

1

6

1

SCLK

G:H_3P2 X6
H13
HOLEA

H14
HOLEA

H15
HOLEA

H16
HOLEA

H17
HOLEA

1

WP#

1

3

1

HOLD#

1

HOLD#

8
7

1

SO

VCC

1

CS#

1

2

1

1030 change to H_3P8
for thermal

H_4P5X3P0N

I:H_3P0 X1
H18
HOLEA

H19
HOLEA

H20
HOLEA
1

SPI_SI_R

Compal Secret Data

Security Classification
Issued Date

1

2 15_0402_5%

1

R218 1

1

FRD#SPI_SI

1

1

34 FRD#SPI_SI

FSEL#SPICS#

1

34 FSEL#SPICS#

1

2

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.
EC SPI ROM

Size
B
Date:

Document Number

Rev
0.3

LA-5941P
Thursday, April 08, 2010

Sheet

36

of

50

http://hobi-elektronika.net
B

C

1

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JUSB1

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

USB POWER

4
L_USB20_N0
L_USB20_P0

4

2
3

2

1

3

2

2

@

1

+

C615
150U_B2_6.3VM_R35M

2

USB20_N3 16
USB20_P3 16

1

EMI request
+USB_VCCC

2
USB20_N9
USB20_P9

EMI request
MIC_JD 33
PLUG_IN 33

EXT_MIC_L 33
EXT_MIC_R 33

2

C622
470P_0402_50V7K

JESAT1

@

SATA_DTX_C_IRX_N4
SATA_DTX_C_IRX_P4

13 SATA_DTX_C_IRX_N4
13 SATA_DTX_C_IRX_P4

SATA_ITX_DRX_P4_CONN
SATA_ITX_DRX_N4_CONN

0.01U_0402_16V7K 2
2
0.01U_0402_16V7K

1 C624
1 C623

1

2

@

1

2

+USB_VCCA

E-SATA COMBO
LEFT USB PORT

U27

@

1
2
3
4

C621 0.1U_0402_16V4Z
2
1

Audio Jet

GND
IN
IN
EN

OUT
OUT
OUT
OC#

8
7
6
5

34

1

C610
@ 1000P_0402_50V7K
16
16

KILL_SW# 34

OFF
ON

+3VS_BT

+USB_VCCB

USB_OC#0 16

1
3

2

C636
@ 1000P_0402_50V7K

D

BTEN-

2
G

Q54 @
2N7002_SOT23 S
U31

OUT
OUT
OUT
OC#

8
7
6
5

34
USB_OC#5

1

APL3510BKI_SO8

Low Active

2

BT_EN

1

USB_OC#5 16

2
IN

C675
@ 1000P_0402_50V7K

3

GND
IN
IN
EN

1

USB_ON#

1
2
3
4

BT_EN_RC#

2

R55
BT@
220K_0402_5%

OUT

+USB_VCCC

C677 0.1U_0402_16V4Z
2
1

1

1

3

3

+5VALW

3

2

2

1

2

R71 @
100K_0402_5%

C353

2

BT@

+3VS_BT_R

1

1

PVT

C354 BT@
2 0.1U_0402_16V4Z

OUT

1

JBT1

GND

BT_PRESENCE

10K_0402_5%
@

JCR1
4

1
2
3 GND
4 GND

16
16

IN

USB20_P11
USB20_N11

2

1
2
3
4
5
6

USB20_P11
USB20_N11
BTON_LED
BT_PRESENCE

Q29
DTC124EKAT146_SC59-3
@

1
2
3
4
5 G1
6 G2

7
8

ACES_87213-0600G
ME@

4

5
6

2010/01/13

Issued Date

ME@

SP01000KC00

Compal Electronics, Inc.

Compal Secret Data

Security Classification

ACES_85201-04051

A

2

3

1

3

2

PVT,chg AO3413 main R321 BT@
0_0603_5%

BT_LED#

R234

+3VALW

USB20_N5
USB20_P5

@

+3VS_BT

+3VS

CARD READER CONN

16
16

2

Blue Tooth Moudle

0.1U_0402_16V4Z

Q31 BT@
DTC124EKAT146_SC59-3

28

1
2
3
4

1

Q32 BT@
SI2301BDS-T1-E3_SOT23-3

2

2

USB20_N5
USB20_P5

@

C612 @
4.7U_0805_10V4Z

2

1

2

GND

Low Active

1

3

R979 BT@
100K_0402_5%

1

1

APL3510BKI_SO8

4

2

W=40mils

1
USB_OC#0

R70 @
150_0603_1%

D

USB_ON#

B- = TXN
B+ = TXP

+5VALW
+3VS

8
7
6
5

OUT
OUT
OUT
OC#

G

C637 0.1U_0402_16V4Z
2
1

GND
IN
IN
EN

GNDS1
GNDS2
GNDS3
GNDS4

L38

U29

1
2
3
4

12
13
14
15

SVT
EMI request
@
R678 1
2 0_0402_5% L_USB20_N1
R679 1
2 0_0402_5% L_USB20_P1
@
WCM-2012-900T_4P

1

S

+5VALW

USB_ON#

USB_ON#

USB20_N1
USB20_P1

USB20_N1
USB20_P1

4

STATUS
1,2(LOW)
2,3(HI)

GND1
A+
ESATA
AGND2
BB+
GND3

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

1

TAIWI_EU091-117CRL-T
ME@

Kill

2 R295
1
100K_0402_5%

5
6
7
8
9
10
11

USB
A+ = RXP
A- = RXN

USB_OC#1 16

Low Active

2

+3VALW

USB

VBUS
DD+
GND0

APL3510BKI_SO8

GNDA

2

KILL_SW#

SATA_DTX_IRX_N4
SATA_DTX_IRX_P4

+5VALW

ME@

SP010804150

1
2
3
4

L_USB20_N1
L_USB20_P1

2

13 SATA_ITX_DRX_P4_CONN
13 SATA_ITX_DRX_N4_CONN

USB20_N9
USB20_P9

USB20_N9 16
USB20_P9 16

HP_OUTR 33
HP_OUTL 33

@

1

W=80mils

+USB_VCCA
1

WCM-2012-900T_4P
USB20_N3
USB20_P3

USB20_N3
USB20_P3

KILL_SW#

@

1

ESATA and USB Conn.

+USB_VCCA

C801
1P_0402

G2
G1

E

C800
1P_0402

32
31

2 0_0402_5% L_USB20_N0
2 0_0402_5% L_USB20_P0

C805
1P_0402

P-TWO_196054-30041

@
R680 1
R681 1
@
L39
1 1

C807
1P_0402

+USB_VCCB

USB20_N0
USB20_P0

USB20_N0
USB20_P0

C803
1P_0402

16
16

C804
1P_0402

TO USB BOARD/Audio Jet CONN

D

EMI request

C802
1P_0402

SVT

C806
1P_0402

A

C

D

Title

USB ports/BT/E-SATA
Size Document Number
Custom
Date:

Rev
0.3

LA-5941P

Thursday, April 08, 2010

Sheet
E

37

of

50

http://hobi-elektronika.net

ON/OFF switch FOR DEBUG

Power Bottom Board Conn.4pin

Power Button

3

2

4

JPW 1

6
5

SMT1-05_4P

TOP Side

34

+3VALW

PW R_LED#

1
2
3
4

ON/OFFBTN#

2

@

ON/OFFBTN#

1
2

ON/OFF#

3

51_ON#

ON/OFF# 34

+3VALW

1

Q28
2N7002_SOT23-3

R302
10K_0402_5%

3

2

EC_ON

34
34
34

D

2
G

1
2
3
4
5
6
7
8

ALS_CLK
ALS_DATA
LID_SW #

S

1

34
34

1
2
3
4
5
6
GND
GND

ESB_DAT
ESB_CLK

1

1

1

3

2
1

GEN_EN_RC# 2

2

RG8 GEN@
220K_0402_5%

+3VS
JFP1

OUT

2
IN

GND

2

GEN_EN

3

1

34

RG3 @
10K_0402_5%

2

UG1
ST

ST

14
15

Vs
Vs

GEN@

Xout
Yout

12
10

2

RG6 GEN@
100K_0402_5%

NC
NC
NC
NC
NC
NC
NC

1
4
8
9
11
13
16

3
5
6
7

COM
COM
COM
COM

CG4

SP01000KC00

CG9 @
4.7U_0805_10V4Z

GEN@

+3VS_GEN_R

34 SUSP_LED#
34 BATT_LOW _LED#
34 BATT_CHG_LED#
28,34 W LAN_LED#

Amber
Blue

PVT,chg AO3413 main

QG3 GEN@
DTC124EKAT146_SC59-3

+3VS

+3VS

1

JLED

QG1 GEN@
SI2301BDS-T1-E3_SOT23-3

X
Y

1
1

RG4 GEN@
56K_0402_5%
2
2
RG5 GEN@
56K_0402_5%

1
2
3
4
5
6
7
8
9
10

W LAN_LED#

+3VS

1

VOUTX
VOUTY

34
34

PVT

1
CG7 GEN@
0.1U_0402_16V4Z

+1.5VS_VGA

1

1
2
3
4
5
6
7
8
GND
GND

SP01000H200
VOUTX
VOUTY

2

1

2

+1.5VS_VGA

C728
0.1U_0402_16V4Z

Issued Date

2

+3VS

2010/01/13

Deciphered Date

+3VS

1

1

1

C723
0.1U_0402_16V4Z
2
+5VALW

C724
0.1U_0402_16V4Z
2
+5VALW

C725
0.1U_0402_16V4Z
2
+3VALW

C729
0.1U_0402_16V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

C722
C726
C727
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
+5VS
+VGA_CORE
+VGA_CORE

+3VS

1

CG8 GEN@
0.1U_0402_16V4Z
+5VALW

C721
0.1U_0402_16V4Z
2
+1.05VS

LED CONN 8 pin

+3VALW
+5VALW

0.1U_0402_16V4Z

S IC LIS244ALTR LGA 16P G-SENSOR

1

5
6

ACES_85201-0805N
ME@

1

2

1
2
3 GND
4 GND

ACES_85201-04051

2

1

RG9 @
100K_0402_5%

C720
0.1U_0402_16V4Z
2
+5VS

1
2
3
4

USB20_N10
USB20_P10

USB20_N10
USB20_P10

+5VS

1

1

1

1

3

GENEN-

+3VS_GEN_R

CG3
10U_0805_10V4Z
GEN@

34 G_SELFTEST

2

SP01000H200

PIN adjust

2

D

RG1 GEN@
1
2
47_0402_5%

+5VS

ACES_85201-0805N
ME@

RG2 GEN@
100K_0402_5%

G

2
G

QG2 @
2N7002_SOT23 S

+3VS

@
C2
33P_0402_50V8J

W=20mils

S

+3VS_GEN

1

1

FP Board Conn 4 pin

1

+3VS

1

ME@

D

CG2 GEN@
1U_0603_10V6K

2

APS G-Sensor

+5VALW

RG7 @
150_0603_1%

2

2

EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00

+3VS

2

2 0_0402_5%
2 0_0402_5%

D20
PJSOT24C 3P C/A SOT-23
@

1
NOVO_BTN#

3

+3VS_GEN

2

2 0_0402_5% I2C_INT_R

1
1

@
C1
33P_0402_50V8J

16
16

1

1

R2
R1

1
2
3
4
5
6
7
8
GND
GND

2

BAV70W _SOT323-3

1

R3

JCAP1

1
2
3
4
5
6
7
8
9
10

D13

1

1

+3VS_CAP

2

3

2

3
2

D19
PJSOT24C 3P C/A SOT-23
@

51_ON#

CG1 GEN@
0.1U_0402_16V4Z

+5VS_CAP

ON/OFFBTN#

R296
100K_0402_5% PVT
NOVO#

13 HDD_LED#
34
CAP_RST#
34
CAP_INT

SP01000B000

+3VALW

NOVO#

2
0_0402_5%
2
0_0402_5%

ACES_85201-06051
ME@

NOVO_BTN#

34

+5VS

JFB1
NOVO_BTN#

51_ON# 40

BAV70W _SOT323-3
PVT

1
R349
1
R351

+3VS

SP01000KC00

NOVOBottom/ALS Board Conn.6pin

1

EC_ON

5
6

ME@

R272
100K_0402_5%
D14

1
2
3 GND
4 GND

ACES_85201-04051

Bottom Side

34

Cap Sensor Board Conn. 8pin
ENE SB3534

+5VALW

SW 1

1

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Audio Jack & SW connector
Size
Document Number
Custom
Date: Thursday, April 08, 2010

Rev
0.3

LA-5941P
Sheet

38

of

50

http://hobi-elektronika.net
B

D

+3VALW TO +3VS

+1.5V to +1.5VS

+1.5VS

2

C135
1U_0603_10V6K

B+

10K_0402_5%
Q20
2N7002_SOT23

2

SUSP

D

S

SUSP#

2

IN

3

1
Q9
2N7002_SOT23

2
G

2

R_1.5VS_EN-

C144
0.1U_0603_25V7K

C389 @
4.7U_0805_10V4Z

2

2

1

SI2301BDS-T1-E3_SOT23-3

R312
15K_0402_1%

1

2

Q33

C361

0.1U_0402_16V4Z

Q13
DTC124EKAT146_SC59-3
R181
100K_0402_5%

PVT,chg AO3413 main

C362
C363
10U_0805_10V4Z 1U_0603_10V6K
2

2

IN

SVT,discharge

1

1
2

SUSP

34,42,46

2

SUSP#

IN

2

3

3

For Intel S3 Power Reduction.

Q1
DTC124EKAT146_SC59-3

1

OUT

SUSP

2

2

8,44,45

MP
R5
100K_0402_5%

OUT

SVT,add

SYSON

SYSON

R4
100K_0402_5%

GND

34,44

+5VALW

@

1

SYSON#
Q2
DTC124EKAT146_SC59-3
@

2 SUSP
G
Q11
2N7002_SOT23
@

S

RTCVREF

1
@
R6
100K_0402_5%

D

2 SUSP
G
Q40
2N7002_SOT23

3

S

R143
470_0603_5%
@

GND

1 2

1 2

D

2 SUSP
G
Q15
2N7002_SOT23
@

S

1

2

+5VALW

SYSON
1
2
R673
SVT
10K_0402_5%
MUST CLOSE PR501,1.5V_EN

1

1

1
D

2 SYSON#
G
Q35
2N7002_SOT23
@

1

+1.05VS

R568
22_0603_5%

3

S

3

3

2

D

2 SUSP
G
Q10
2N7002_SOT23

+0.75VS

R174
470_0603_5%
@

3

D

R342
470_0603_5%
@

1 2

1 2

1 2

R142
470_0603_5%

S

+VCCP

1

+1.5V

1

+1.8VS

+1.5VS

W=60mils

2

S

C278
0.1U_0603_25V7K

SVT,discharge

3VS_GATE

1.5VS_EN-

3

1

Q34
2N7002_SOT23 S

2 SUSP
G
Q6
2N7002_SOT23

1

PVT,timing
1
2

1

1
2

SVT,discharge

15VS_GATE_R

2
G

1

D

2
G
3

SUSP

S
R89
47K_0402_5%

1

1

5VS_GATE 2 R228

D

D

2 SUSP
G
Q16
2N7002_SOT23

3

3

S

SVT,discharge

OUT

D

R229
20K_0402_5%

R87
470_0603_5%

R178
100K_0402_5%

3

C134
10U_0805_10V4Z

W=60mils

1

1
2

R337
470_0603_5%

2

2

+1.5V

1

1

1 2

B+

1

C127
10U_0805_10V4Z

R202
470_0603_5%

1

GND

C276
1U_0603_10V6K

2

SI4800BDY-T1-E3_SO8
1
2
3

1 2

C277
10U_0805_10V4Z

U4
8
7
6
5

1

1

1

3

2

4

2

1

+5VALW

+3VS

1 2

C279
10U_0805_10V4Z

SI4800BDY-T1-E3_SO8
1
2
3

1

U10
8
7
6
5

1

+3VALW

4

+5VS

D

+5VALW

E

G

+5VALW TO +5VS

C

S

A

+1.05VS to +1.05VS_VGA Transfer

+1.5V to +1.5VS_VGA Transfer
+1.5V

+1.5VS_VGA
1

+1.05VS_VGA
SVT

2
HYBRID@
U33
AO4430L_SO8

2

1

1

C680
HYBRID@
10U_0805_10V4Z
2

2

C679
0.1U_0402_16V4Z
HYBRID@

R621
470_0603_5%
HYBRID@

1

1

2

2

C705
10U_0805_10V4Z
HYBRID@

2

C686
10U_0805_10V4Z
HYBRID@

250mil(6A)
1
2
3
1

4

100mil(1.5A)
2

1

2

1

C681
10U_0805_10V4Z
HYBRID@

HYBRID@
SI4800BDY-T1-E3_SO8
1
2
3

4

3

U34
8
7
6
5

8
7
6
5

C706
10U_0805_10V4Z
HYBRID@

C685
10U_0805_10V4Z
HYBRID@

1

2

C684
0.1U_0402_16V4Z
HYBRID@

R624
470_0603_5%
HYBRID@

3

1

+VGA_1.05VS

B+

DGPU_PWR_EN#

1

DGPU_PWR_EN#

5

2

DGPU_PWR_EN#

HYBRID@

4

4

HYBRID@

C683
0.1U_0603_25V7K
HYBRID@
Q57B
2
2N7002DW-T/R7_SOT363-6

Q57A
2N7002DW-T/R7_SOT363-6
HYBRID@

1

2

1.5VSDGPU_GATE

R623
200K_0402_1%
HYBRID@

3

C682
0.1U_0603_25V7K
HYBRID@
Q24B
2
2N7002DW-T/R7_SOT363-6

Q24A
2N7002DW-T/R7_SOT363-6
HYBRID@

1

3

1

DGPU_PWR_EN# 5

PVT,timing
1
2

6

HYBRID@
1.05VSDGPU_GATE
1
2
R622
510K_0402_1%

6

B+

1

+5VALW

2

R52
100K_0402_5%
HYBRID@
DGPU_PWR_EN#

16,22,45 DGPU_PWR_EN

1

4

R127
0_0402_5%
2
1

D

3

4

S

2
G

Q56
2N7002W-T/R7_SOT323-3
HYBRID@

1

HYBRID@

2
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
R53
100K_0402_5%
HYBRID@

2010/01/13

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

DC Interface
Size
Document Number
Custom
Date:

Rev
0.3

LA-5941P

Thursday, April 08, 2010

Sheet
E

39

of

50

http://hobi-elektronika.net
B

C

ACIN

1

PR102
1K_1206_5%
1
2
PR103
1K_1206_5%
1
2

1

1

1

Max.
18.384V
17.728V

VIN

VS

34,42

2

ACOFF

PQ103

3

3
PR113
2.2M_0402_5%
2
1

-

6

PU102B
LM393DG_SO8

PRG-

2

51ON-1
1

1

PD105
LL4148_LL34-2
2
1

1

BATT+

2

PACIN

1

+5VALW

2

3
JRTC1

PQ106
DTC115EUA_SC70-3

+

PR128
560_0603_5%
1+RTCBATT-1 1
2

+RTCBATT

1

PD106
@ MAXEL_ML1220T10

1

PR127
200_0603_5%

2

+CHGRTC

RB751V-40_SOD323-2

APL5156-33DI-TRL_SOT89-3

4

2

RTC Battery

PC116
10U_0603_6.3V6M

1

1

VIN
GND

2CHGRTCIN
PC117
1U_0805_25V6K

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

VOUT

1

3

2

PR123
47K_0402_5%
1

VS

Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2

PC115
0.1U_0603_25V7K

-

PU101

+CHGRTC

3.3V

2
G
3

1

51ON-3

RTCVREF
PR129
560_0603_5%
RTCVREF-1
1
2

PQ105
2N7002KW _SOT323-3

2

1

3

2

4

2

RTCVREF

D

2

2

1

PC114
0.22U_0603_25V7K

51ON-2

2

PR126
22K_0402_1%
1
2

51_ON#

PR122
10K_0402_5%
2
1

3

S

PR125
100K_0402_1%

38

PR121
68_1206_5%
2

PR120
68_1206_5%
PQ101
TP0610K-T1-E3_SOT23-3
PR124
200_0603_5%
CHGRTCP 1
2

1

PD104
LL4148_LL34-2

PC113
0.1U_0603_25V7K

3

PRG+

1

5

2
1
PR119
499K_0402_1%

+

O

1

7

1

1
2
8
PRG-1

PC111
1000P_0402_50V7K

ACON

2

42

P

VIN

PD103
RB715F_SOT323-3
2
1
3

G

41,43 MAINPWON

PC110
0.01U_0402_25V7K

VS

3.3V

2

VL

PC112
0.01U_0402_25V7K

42

2
1
PR116
499K_0402_1%

PACIN

2
1
PR117
100K_0402_1%

2
RTCVREF

34

2

PD101
LLZ4V3B_LL34-2
PR115
10K_0402_5%
2
1

2

B+
PQ104

1
PR118
205K_0402_1%

1
PR109
10K_0805_5%

PACIN

1

O

PU102A
LM393DG_SO8

DTC115EUA_SC70-3
2
DTC115EUA_SC70-3

ACIN

1
PR114
10K_0402_5%

-

1

+

2

PR110
10K_0402_1%
1
2

4

8
3

4

1
2

PC109
0.1U_0402_16V7K

2

PR112
20K_0402_1%

1

VINDE-3

P

VINDE-1

G

2

PR111
22K_0402_1%
1
2

2

2

PR108
84.5K_0402_1%

PC108
0.068U_0603_16V7K
2
1

PC107
0.01U_0402_25V7K

1

1

2

PRG++ 2

VINDE-2
VIN

1

PR101
1M_0402_1%
1
2

1 2

1

Vin Detector
Min.
typ.
L-->H 17.430V 17.901V
H-->L 16.976V 17.262V

3

PR104
1K_1206_5%
1
2
PR105
100K_0402_1%
2
1

PD102
RLS4148_LL34-2

2

2

VIN

PQ102
TP0610K-T1-E3_SOT23-3

PR106
100K_0402_1%
2
1

1
2

PC106
1000P_0402_50V7K

1
2

PC105
100P_0402_50V8J

1
2

ACES_87302-0401-003

1

6

2

5

GND

PC104
@ 0.1U_0603_25V7K

GND

1

4

2

3

4

PL101
SMB3025500YA_2P
1
2

PC103
100P_0402_50V8J

2

3

PF101
7A_24VDC_429007.W RML
1
2 APDIN1

1

2
1

APDIN

2

1

PC102
1000P_0402_50V7K

1

PC101
@ 0.1U_0603_25V7K

JDCIN1

BATT ONLY
Precharge detector
Min.
typ.
Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V

Precharge detector
Min.
typ.
Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V

VIN

D

PR107
100K_0402_1%

A

B

C

Title

DCIN & DETECTOR
Size Document Number
Custom
Date:

Rev
0.3

Thursday, April 08, 2010
D

Sheet

40

of

50

http://hobi-elektronika.net

A

B

C

D

1

1

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C
VMB

3

OT1 TMSNS2

6

OT2 RHYST2

5

G718TM1U_SOT23-8
EC_SMB_CK1 34

2

1

1

G718_TMSNS1
G718_RHYST1

2

7

PR206
9.76K_0402_1%
1

8

GND RHYST1

1

VCC TMSNS1

2

2

PR205
@ 100K_0402_1%

2

PU201
1

4

PR204
21.5K_0402_1%

1

PR203
10K_0402_1%

1
2G718_TMSNS2
PR207
@ 47K_0402_1%

2

PC202
0.01U_0402_25V7K

2

PC203
0.1U_0603_25V7K

1

1
2

PC201
1000P_0402_50V7K

G718_RHYST2

@ SUYIN_200082MR007G100ZR

VL

BATT+
1

EC_SMCA
EC_SMDA
TS
2
1
PR202
100_0402_1%

1
2
3
4
5
6
7
8
9

2
1
PR201
100_0402_1%

2

1
2
3
4
5
6
7
GND
GND

VL
PL201
SMB3025500YA_2P
1
2

PH201
100K_0402_1%_TSM0B104F4251RZ
2

PF201
12A_65V_451012MRL
1
2

2

VMB2
JBATT

MAINPW ON 40,43
1

EC_SMB_DA1 34
PH202
@ 100K_0402_1%_TSM0B104F4251RZ

+3VALW

2

1
2
PR208
6.49K_0402_1%

1
2
PR209
10K_0402_5%

BATT_TEMP 34

A/D

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

BATTERY CONN / OTP
Size
Date:

Document Number

Rev
0.3

Thursday, April 08, 2010

Sheet
D

41

of

50

http://hobi-elektronika.net

5

4

3

P3

P2

CHG_B+
PJ301

PQ303
FDS6675BZ_SO8
8
7
6
5

DISCHG_G

D

4

1
2
3

PC306
2200P_0402_50V7K

CSIN
CSIP

PR304
47K_0402_1%
1
2

VIN

1DISCHG_G-1
1

CSOP

21

5

ICOMP

CSIN

20

6

VCOMP

CSIP

19

7

ICM

PHASE

18

CHG 1

4

2

3

C

BATT+

12

16

ACLIM

VDDP

15

VADJ

LGATE

14

GND

PGND

13

PR320
2.2_0402_5%
BST_CHG 1
2

PC317
0.1U_0603_25V7K
BST_CHGA 2
1
4
PD303
RB751V-40TE17_SOD323-2

6251_VDDP
DL_CHG

26251_VDD

1

PR323
4.7_0402_5%
PC323
4.7U_0805_6.3V6K

PC320
10U_1206_25V6M
2
1

BOOT

PC319
10U_1206_25V6M
2
1

CHLIM

1

DH_CHG

PC318
10U_1206_25V6M
2
1

10

6251_VADJ
11

17

2

34 CHGVADJ

PACIN

PQ309
2N7002KW _SOT323-3

PR317
0.02_1206_1%

PR318
4.7_1206_5%

9

PR324
2K_0402_1%

UGATE

16251_SN
2

VREF

ISL6251AHAZ-T_QSOP24

Connect to EC A/D Pin.

2

2
G
S

5
8

2

1
2

3

PR322
100K_0402_1%

PL301
10U_LF919AS-100M-P3_4.5A_20%

D

PC322
680P_0603_50V7K

IREF

1
2
PC316
6251_CHLIM
0.1U_0402_16V7K
PR321
16.9K_0402_1%
6251_VREF 1
6251_ACLIM
2

VIN

2

1
PQ312
SI7716ADN-T1-GE3 _PAK1212-8

1

34

PR319
154K_0402_1%
2
1

1
26251_ICM
PR316
100_0402_1%
6251_VREF

4

3
2
1

6251_ICOMP

CSOP

PR307
200K_0402_1%
1
2

1

CELLS

PD302
RB715F_SOT323-3

PC311
0.1U_0603_25V7K
2
1

4

CSON

ACOFF

2

3

CELLS

6251_CSON
PC310
0.047U_0402_16V7K
6251_CSOP 1
2
PR311
20_0402_5%
6251_CSIN
2
1
PC314
PR312
20_0402_5%
0.1U_0402_16V7K
6251_CSIP
1
2
PR315
2.2_0402_5%
LX_CHG

PQ308
SIS412DN-T1-GE3 _PAK1212-8

22

5

CSON

3
2
1

EN

3
1

PQ306
DTC115EUA_SC70-3

PR310
20_0402_5%
1
2

1

1

23

3

6.81K_0402_1%
6251_VCOMP
2

1
2
PC315
@ 100P_0402_50V8J

ADP_I

ACOFF 2

ACOFF

ACSET ACPRN

1

0.01U_0402_25V7K

34

34,40

2

S

ACON
PQ311
DTC115EUA_SC70-3

24

2

1

PC313
PR314
1
26251_VCOMP-1
1

2
G

PC321
0.01U_0402_25V7K
2
1

40

6800P_0402_25V7K
2

DCIN

1

PACIN

PC312
1

PQ310
D 2N7002KW _SOT323-3

VDD

6251_EN

1

PACIN

3

40

PR313
3K_0402_1%
1
2

1

2

P2-2 2

3

S

C

PR308
2

1

PQ307
D 2N7002KW _SOT323-3

2
PC308
0.1U_0402_16V7K
PR309
150K_0402_1%

1

1

PC309
0.1U_0603_25V7K
6251_DCIN2
1

2

FSTCHG

PU301

2

3

34

PR306
10K_0402_1%
2
1

FSTCHG

100K_0402_1%

PQ305
DTC115EUA_SC70-3

1

2

PC307
2.2U_0603_6.3V6K
2
1

1

P2-1

2
G

PR305
10K_0402_1%

PD301
RB751V-40TE17_SOD323-2
6251_VDD
1
2

3

1

2

PC303
4.7U_0805_25V6-K
1
2

@ JUMP_43X118

PC305
4.7U_0805_25V6-K
1
2

1

1

1
2

2

PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%

3

PQ304

1

PC304
4.7U_0805_25V6-K
1
2

3

2

1

2

2

2

4

PC324
0.1U_0603_25V7K
2

1

2

1
PR301
47K_0402_5%

PR302
0.02_1206_1%

8
7
6
5
4

1
2
3

DTA144EUA_SC70-3

2

D

1
2
3

4

8
7
6
5

1

VIN

1

PQ302
FDS6675BZ_SO8

PC302
@ 470P_0603_50V8J

PQ301
FDS6675BZ_SO8

2

B+

PR325
15.4K_0402_1%
1
2

2

PR330
@ 0_0402_5%

IREF=1.016*Icharge

2

5
4

1

2

IREF=0.254V~3.048V

B

PR327
PR328
100K_0402_1% @ 100K_0402_1%

CELLS

CC=0.25A~3A

6251_VDD

1

3.2935V

4cell : PR327
3cell : PR330

3

1.882V

4.35V

6251_VDD

PR326
31.6K_0402_1%

1

4.2V

DIS/UMA CP mode (55W)
Vaclim=2.39*(2K/(2K+16.9K))=0.253V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.253V, Iinput=2.76A

2

0V

1

4V

6

CHGVADJ

Vcell

2

B

1

CHGVADJ=(Vcell-4)/0.10627

VCHLIM need over 95mV

2

1
PR331
@ 0_0402_5%

34 BATT_SEL_EC
PQ314 TP0610K-T1-E3_SOT23-3
3

1

P3-2

PQ313A
@ 2N7002KDW -2N_SOT363-6

6251_DCIN

PQ313B
@ 2N7002KDW -2N_SOT363-6

PR337

2

PR335
100K_0402_1%
2
1

P3

PR333
10_0603_5%
P3-1 1
2

2

1

P3-3

100K_0402_1%
A

1

A

PQ315
DTC115EUA_SC70-3

3

2P3-41

5

2

FSTCHG

3

SUSP#

SUSP# 34,39,46

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/01/13

Issued Date

PD304
RB715F_SOT323-3

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2

Title

CHARGER
Size
Date:

Document Number

Rev
0.3
Sheet

Thursday, April 08, 2010
1

42

of

50

http://hobi-elektronika.net

5

4

3

3
2
1
HG5

17

BST5A2
PR406
2.2_0603_5%

25

LG3

23

LGATE2

30

OUT2

32

FB2

VL

@

PHASE1

16

SW 5

LGATE1

18

LG5

PGND

22

OUT1

10

FB1

11

BYP

9

SKIP

29

SECFB

POK2

28

EN_LDO

POK1

13

EN1

ILIM1

12

ILM1

31

ILIM2

PHASE2

2VREF_ISL6237
1

2

1

REF

8

NC

PC418
0.22U_0603_25V7K
PD401
2

PC414
0.1U_0603_25V7K

4

3/5V_EN1

14
27

EN2

ILIM2

1
2

2

21

2

PC407
0.1U_0402_25V6
2
1

PC415
150U_B2_6.3VM_R45M

5V_SKIP

2
1
PR410
@ 0_0402_5%
1
2
PR411
0_0402_5%
2
1
PR413
@ 0_0402_5%

RT8206BGQW _QFN32_5X5

VL

2VREF_ISL6237

2
1
PR415
301K_0402_1%
2
1
PR416
301K_0402_1%

B

13/5V_TON

PR417
0_0402_5%

PC406
2200P_0402_50V7K
2
1

FB5

PR421
0_0402_5%

PJ402

+3VALWP

2

2

1

1

+3VALW

@ JUMP_43X118
2VREF_ISL6237

1

0_0402_5%

1

PR420
@ 47K_0402_1%

PC420
1U_0603_10V6K
2
13/5V_NC

1

2VREF_ISL6237

40,41 MAINPW ON

1

PR419
2

PC422
0.047U_0402_16V7K
2
1

RB751V-40_SOD323-2

PC421
0.047U_0402_16V7K

2
2

PR418

1

806K_0603_1%

VL
PD403

+
2

C

2

B

5

2

3/5V_EN2

GND

PC419
0.22U_0603_25V7K

EN_LDO

TON

2

LLZ5V1B_LL34-2

1

2

PR414
200K_0402_1%
1
2

1

EN_LDO-1

NC

20
PR412
100K_0402_1%
1
2

PD402

PC416
680P_0603_50V7K

PQ404
SI7716ADN-T1-GE3_PAK1212-8

RB751V-40_SOD323-2

VS

1

2

SW 3

4
1

PC413
0.1U_0603_25V7K

PR405
4.7_1206_5%

1BST5A-1

PR407
@ 61.9K_0402_1%
1
2

15

BOOT1

1

UGATE1

15V_SNB
2

19

5

4.7U_0805_6.3V6K

PC410
2
1
7

PC411
1U_0603_10V6K
1
2

PVCC

+5VALWP

PL402
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
2
1

3
2
1

BOOT2

PQ402
SIS412DN-T1-GE3_PAK1212-8

2

VCC

UGATE2

24

LDO

3

6

2
1

VIN

26

FB3

1

PC405
10U_1206_25V6M
2
1

1U_0603_10V6K

3/5V_VIN

2
1

UG3
BST3A

5

2
1
PR403
2.2_0603_5%

4

D

PR409
0_0402_5%
1
2

2

TP

PQ403
SI7716ADN-T1-GE3_PAK1212-8

PR408
10K_0402_1%

1

C

33

1
2
3

PC417
680P_0603_50V7K

4

2

2

BST3A-1

13V_SNB
2

+

PR404
0_0402_5%

2

1

PU401

PR402
4.7_1206_5%

1

PC412
150U_B2_6.3VM_R45M

VL

1
2
3

PL401
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2

1

PC408
0.1U_0603_25V7K

PQ401
4 SIS412DN-T1-GE3_PAK1212-8

PC409
3/5V_VCC
1
2

5

5

PC404
2200P_0402_50V7K
2
1

PC403
10U_1206_25V6M
2
1

PR401
0_0402_5%
1
2

PC402
0.1U_0402_25V6
2
1

PC401
330P_0402_50V7K
2
1

PJ401
@ JUMP_43X118
2 2
1 1

+3VALWP

1

ISL6237_B+

ISL6237_B+

B+

D

2

@

PJ403

+5VALWP

2

2

1

1

+5VALW

@ JUMP_43X118

A

A

2010/01/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

3VALW/5VALW

Size Document Number
Custom
Date:

Rev
0.3

Thursday, April 08, 2010

Sheet
1

43

of

50

http://hobi-elektronika.net

5

4

3

2

1

PJ501
1.5V_IN

10

LGATE

9

LG_1.5V

4

2

RT8209BGQW _W QFN14_3P5X3P5

PC512
4.7U_0805_6.3V6K

2
1
PC505
2200P_0402_50V7K

2
1
PC504
0.1U_0402_25V6

PR504
4.7_1206_5%

1
+
2

1

11

+5VALW

2

CS
VDDP

1.5V_TRIP
1
2
PR506
7.15K_0402_1%

1

PGND
8

GND

1

SW _1.5V

ΚΚ
Κ

+1.5VP

Imax 13A
Ipeak 16.2A
OCP 30A

PC508
10U_0603_6.3V6M

PGOOD

PC510
@ 47P_0402_50V8J
1
2

7

2

PC509
4.7U_0603_6.3V6K

D

PC507
220U_B2_2.5VM_R15M

6

12

1.5V_SNB 2

FB

PHASE

1

VDD

5

UG_1.5V

B+

PC513
680P_0603_50V7K

2

NC

1

4

1.5V_FB

13

1

PQ501
SI4172DY-T1-GE3_SO8

PQ502
TPCA8028-H_SOP-ADVANCE8-5

VOUT

2
1
PC503
10U_1206_25V6M

2
1
PC502
10U_1206_25V6M

5
6
7
8
3
1.5V_V5FILT

UGATE

1

+5VALW

TON

1

PL501
1.0UH_PCMC104T-1R0MN_20A_20%
1
2

5

PR505
100_0603_1%
1
2

2

15

PU501

EN/DEM

2

PC501
@0.1U_0402_16V7K

2BST_1.5V-1
1
2
PC506
0.1U_0603_25V7K

3
2
1

BST_1.5V 1
PR503
2.2_0603_5%
14

1.5V_EN

BOOT

SYSON

1

34,39

4

3
2
1

1.5V_TON
PR501
0_0402_5%
1
2

2

@ JUMP_43X79

D

PR502
240K_0402_1%
1
2

2

PR508
31.6K_0402_1%
1
2

C

1

C

2

PR509
30.1K_0402_1%

PJ504
2

+1.5VP

2

1

1

+1.5V

@ JUMP_43X118

PJ506
2

+0.75VSP

+1.5V

2

1

1

+0.75VS

@ JUMP_43X79
B

PJ503
@ JUMP_43X79

2

1

1

B

6

NC

5

3

VREF

NC

7

4

VOUT

NC

8

TP

9

+3VALW

2
2

PC526
1U_0402_6.3V6K

1

+0.75VSP

S PQ505
SSM3K7002FU_SC70-3

PC530
10U_0603_6.3V6M

PC527
0.1U_0402_16V7K

1

PR522
1K_0402_1%

2

3
2

PC528
@ 0.1U_0402_16V7K

D

PC529
10U_0603_6.3V6M
2
1

0.75V_EN 2
G

1

PR521
@ 0_0402_5%
1
2

VCNTL

GND

G2992F1U_SO8

2

SUSP

0.75V_REF

1

8,39,45

PR523
0_0402_5%
1
2

2

S3_0.75V_EN

1

5

VIN

2
1

1

PR519
1K_0402_1%

2

PC525
4.7U_0805_6.3V6K

1

1

2

PU503
0.75V_IN

A

A

2010/01/13

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

1.5V/0.75VS
Size
Date:

Document Number

Rev
0.3

Thursday, April 08, 2010

Sheet
1

44

of

50

http://hobi-elektronika.net

5

4

3

2

VGA_IN

1

PJ601

2

2

1

1

B+

1
2

2
1
PC604
2200P_0402_50V7K

ΚΚ
Κ

RT8209BGQW _W QFN14_3P5X3P5

PC614
4.7U_0805_6.3V6K

1
2

1
2

PC611
10U_0603_6.3V6M

PC613
680P_0603_50V7K

2

PC610
10U_0603_6.3V6M

PR608
100_0402_5%

1

+

PQ602
SI4634DY-T1-E3_SO8

4
1

PGND
8

GND
7

PGOOD

LG_VGA

PR607
4.7_1206_5%

2

LGATE

9

1

+5VALW

2

PC615
@ 47P_0402_50V8J
2
1

1
2
PR609
0_0402_5%

2

PC612
4.7U_0603_6.3V6K

6

SW _VGA
VGA_TRIP
1
2
PR606
7.68K_0402_1%

PC609
10U_0603_6.3V6M

15

14
VDDP

10

1

FB

11

PC607
330U_D2_2.5VY_R9M

5

12

CS

1

VGA_FB

PHASE

2

VDD

1

VOUT

4

+VGA_COREP

UG_VGA

1VGA_SNB
2

3

VGA_V5FILT

13

2

VGA_VOUT

UGATE

5
6
7
8

TON

D

Imax 8.89A
Ipeak 9.88A
OCP 12.19~15.21A

PL601
0.82UH_PCMC063T-R82MN_13A_20%
1
2

3
2
1

PR605
100_0603_1%
1
2

2

BOOT

PR604
@ 0_0402_5%
+VGA_COREP 1
2

NC

PU601

1

2

3
2
1

PC606
0.1U_0402_16V7K

+5VALW

PQ601
AO4466_SO8

4

2
1
PC603
0.1U_0402_25V6

PR603
PC605
2.2_0402_5%
0.1U_0603_25V7K
1
2 BST_VGA-1 1
2
BST_VGA

VGA_EN

2

EN/DEM

1
PR602
33K_0402_1%

16,22,39 DGPU_PW R_EN

1

D

PC602
10U_1206_25V6M

1
2

5
6
7
8

VGA_TON

PC601
10U_1206_25V6M

@ JUMP_43X79
PR601
205K_0402_1%
1
2

Rds=5.5~6.7mȍ
PR610
6.81K_0402_1%
2
1

C

GVID1-2 1

PR612
84.5K_0402_1%
2

VGA_PW ROK 16
VGA_FB1

1

PR611
0_0402_5%
2

C

+VGASENSE 21

PR613
84.5K_0402_1%
1
2

1

6

VFB=0.75V

PR615
@ 100K_0402_1%
PQ603A
2N7002KDW -2N_SOT363-6
2

PC616
0.01UF_0402_25V7K

2
1GVID0-1
PR617
@ 10K_0402_1%

1

+VGA_CORE

PJ603
1

+1.8VSP

1

2

2

+1.8VS

@ JUMP_43X39

4

1

PR618
@ 10K_0402_5%

+3VS

PC617
@0.01UF_0402_25V7K

B

2

1

VIN

VCNTL

6

2

GND

NC

5

3

VREF

NC

7

4

VOUT

NC

8

TP

9

2

2

PR619
1K_0402_1%

LDO_1.8V_REF

+1.8VSP

PQ604
SSM3K7002FU_SC70-3

2

2

3

S

PC623
10U_0603_6.3V6M

1

PC620
0.1U_0402_16V7K

PC621
10U_0603_6.3V6M
2
1

1

PR621
1.24K_0402_1%

A

2010/01/13

Compal Electronics, Inc.
2011/01/13

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

A

Compal Secret Data

Security Classification
Issued Date

G2992F1U_SO8

2

D

2

PC622
0.1U_0402_16V7K

PC619
1U_0402_6.3V6K

1
1

PR620
33K_0402_1%
1
2LDO_1.8V_EN
2
G

SUSP

1

8,39,44

+5VS

1

PC618
4.7U_0805_6.3V6K

1

GPU_VID0 GPU_VID1 VGA_CORE
0.8V
0
0
0
1
0.86V
1
1
0.86V

2

N11M-GE1/LP1

PU602
LDO_1.8V_IN

2

GPIO5 GPIO6

1

PJ604
@ JUMP_43X39

1

1

2

2

B

1

PQ603B
2N7002KDW -2N_SOT363-6

5

1

19 GPU_VID0

2

@ JUMP_43X118

3

2

2

PR616
10K_0402_5%

PJ602
2

+VGA_COREP

GVID0-2

1

2
1GVID1-1 2
PR614
10K_0402_1%
1

1

19 GPU_VID1

2

Title

VGA_CORE/1.8VS/1.1VS
Size
Date:

Document Number

Rev
0.3

Thursday, April 08, 2010

Sheet
1

45

of

50

http://hobi-elektronika.net

5

4

3

2

1

PJ701
B+

2

2

1

VTT_B+

1

5

PGND

12

ISEN

11

3
2
1

1
1 2
2

VO
10

4

PQ703
TPCA8028-H_SOP-ADVANCE8-5

5
4
PR709
2.21K_0402_1%

VFB=0.6V

+1.1V_VCCPP

PR707
4.7_1206_5%

1
+

VTT_SNB
2

PC711
1000P_0603_50V7K

C

2

1

PR712
10_0402_5%

PC712
@0.01U_0402_25V7K
1

9

7

2

Rds=1.15~1.6mȍ
2

1
1

VTT_COMP-1
2

VTT_ISEN 1

5

PL701
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

PC709
330U_D2E_2VM_R6M

13

ΚΚ
Κ

Imax 20A
Ipeak 22A
OCP 30A

2

3
2
1

1
15

1

16
UG

BOOT
LG

PC706
2.2U_0603_6.3V6K
LG_VTT

316KHz

1

2
PR714
1.58K_0402_1%

VTT_FB-1

2

PR715
0_0402_5%
1

VTT_SENSE 8

PR716
1.96K_0402_1%

H_VTTVID1= Low, 1.1V
H_VTTVID1= High, 1.05V

B

PJ702

2

B

VTT_PVCC
1

PQ701
TPCA8030-H_SOP-ADV8-5

4

2

PC714
@ 6800P_0402_25V7K

1
2

@ 22P_0402_50V8J

PC713
2
PR713
35.7K_0402_1%

FB

NC
6

2

PC710
0.1U_0402_16V7K

FSET

EN

2
1 VTT_FSET
PR711
42.2K_0402_1%

5

PR710
@ 22.1K_0402_1%
VTT_FB

VTT_EN-1

1

PR705
4.7_0603_5%
1
2 VTT_VCC

APW 7138NITRL_SSOP16
PC707
2.2U_0603_6.3V6K

VTT_COMP

8 VTT_SELECT

PR704
0_0603_5%

2

1
2

PR706
47K_0402_1%
1
2

34,39,42 SUSP#

2

PC705
0.1U_0603_25V7K

14

PVCC

VCC

1

C

4

VIN

1

PQ702
TPCA8028-H_SOP-ADVANCE8-5

VTT_VCC
PD701
@ RB751V-40_SOD323-2
1
2

PR702
2.2_0603_5%
2 VTT_BOOT-1
+5VALW

PHASE

3

PGOOD

GND

PU701

8

VCCP_POK

VTT_BOOT1

3
2
1

UG_VTT

PR703
0_0402_5%
1
2

2

5

+5VS

1

2
1
PC704
2200P_0402_50V7K

PC702
10U_1206_25V6M
2
1
PC703
0.1U_0402_25V6

D

SW _VTT

PR701
1K_0402_5%
1
2
1.1VS_PGOOD

2

1

D

PC701
10U_1206_25V6M
2
1

@ JUMP_43X118

2

+1.1V_VCCPP

2

1

1

+VCCP

@ JUMP_43X118
PJ703
2

2

1

1

@ JUMP_43X118

PJ705
2

2

1

1

+VGA_1.05VS

@ JUMP_43X118

PJ704
2
1
+
2

A

2010/01/13

Issued Date

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

1

1

+1.05VS

@ JUMP_43X118

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PC708
330U_D2E_2VM_R6M

+VCCP

2

Title

+1.1VS_VTT
Size Document Number
Custom
Date:

Rev
0.3
Sheet

Thursday, April 08, 2010
1

46

of

50

http://hobi-elektronika.net
3

1

+GFX_B+
2

PR810

GFX_SW

2

1
2

PC803
10U_1206_25V6M

1
2

PC802
10U_1206_25V6M

2
1

2

3
2
1
5

PC808
2.2U_0603_10V6K

18

4

17
33

16

C

0.36UH_PCMC104T-R36MN1R17_30A_20%

+
2

PC812
680P_0603_50V7K

LL=7m ohm
OCP=26A
VID:0.3~1.25V
Io(max)=22A

PH801
1

2

GFX_CSCOMP-1

15

14
GFX_CSREF

GFX_CSFB

13

GFX_CSCOMP

12
GFX_RAMP

GFX_CSCOMP

+GFX_COREP

3
1

PR816
4.7_1206_5%

1

PC811
330U_D2_2.5VY_R9M

GFX_DRVL

2

2
1

4

1
AGND

19

+5VS

1GFX_SNB2

AGND

20

1

Place RTH1 close to inductor
on the same layer

1
1

1

PC814
560P_0402_50V7K

PC813
1000P_0402_50V7K

PR827
165K_0402_1%
2

2

2

1

1
1

2
GFX_RAMP-1

1

GFX_CSFB-1

PR828
39K_0603_1%

PR830
100_0402_1%
1
2

2

PC816
1000P_0402_50V7K

8

8
+GFX_CORE

VSS_AXG_SENSE

VCC_AXG_SENSE

PC815
1000P_0402_50V7K

1

B

Connect to input caps

2

PR831
100_0402_1%
2

B

+GFX_B+

B+

PL802
1

PR826
71.5K_0402_1%
2
1

PR825
422K_0402_1%

11

10

GFX_RT
PR822
340K_0402_1%
1
2

9

PR824
0_0402_5%

PR829
1K_0402_1%
2
1

2

220K_0402_5%_ERTJ0EV224J~D

2

PR823
0_0402_5%

PR821
237K_0402_1%
1
2 GFX_RPM

2
GFX_CSCOMP 1

2

2

Avoid high dV/dt

PR820
80.6K_0402_1%
GFX_IREF
1
2

GFX_FB-1

PR819
10.7K_0402_1%

PC818
2200P_0402_50V7K

1

GFX_DRVH

21

PQ801
SI4172DY-T1-GE3_SO8

5
6
7
8
1
2

22

3
2
1

IREF

PR818
20K_0402_1%

CSCOMP

GPU
ILIM

4

PR815
PC805
2.2_0603_5%
0.22U_0603_25V7K
2GFX_BOOST-1
1
2
23 GFX_BOOST 1

24

PC819
0.1U_0603_25V7K

1
GFX_VCC

1

PR809
1

25 GFX_VID6
VID6

VID5

26 GFX_VID5

PR808
1
VID4

27 GFX_VID4

PR807

PR806

VID3

1

PR805
1

28 GFX_VID3

VID2

VID1

29 GFX_VID2

PR804
1

PGND

GFX_VCC 7
GFX_ILIM 8

PC810
470P_0402_50V8J

DRVL

COMP

2

PC804
1U_0603_16V6K

PQ802
TPCA8028_PSO8

6

PVCC

PU801

CSFB

GFX_COMP

ADP3211AMNR2G_QFN32_5X5

FB

CSREF

2GFX_COMP-1
1

1

PC809
47P_0402_50V8J
1

PR817
1K_0402_1%

1

SW
FBRTN

LLINE

5

CLKEN#

RAMP

GFX_FB

2

PC807
220P_0402_50V7K
2

30 GFX_VID1

DRVH

RT

4

VID0

BST
IMON

3

2

1

31 GFX_VID0

PR803
PWRGD

2

GFX_FBRTN

1
PR811
10_0603_1%

VCC

1
GFX_IMON

C

1

1
EN

PR813
6.98K_0402_1%

RPM

2

GFX_IMON

2

1

PC801
0.056U_0402_16V7K

1
2

PC806
1000P_0402_50V7K

1 2

GFXVR_IMON

32

PR812
@ 300K_0402_1%
8

PL801
FBMA-L11-201209-121LMA50T_0805

2

1

+VCCP

GFX_EN

GFXVR_PWRGD

8

8

8

GFXVR_VID_68

GFXVR_VID_58

GFXVR_VID_48

GFXVR_VID_3

GFXVR_VID_2

8

+5VS

PR801
10K_0402_1%
PR802
0_0402_5%
2
1GFX_PWRGD

1

D

1
@ PR814
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

+3VS

GFXVR_VID_1

GFXVR_VID_0

2
0_0402_5%

D

2

8

4

GFXVR_EN

5

Shortest the
net trace
PJ801
+GFX_COREP

2

2

1

1

+GFX_CORE

@ JUMP_43X118
PJ802
2

2

1

1

@ JUMP_43X118

(15A,600mils ,Via NO.= 30)

A

A

Compal Secret Data

Security Classification

Issued Date

2010/01/13

Deciphered Date

2011/01/13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

GFX_CORE
Size
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

Rev
0.3
Sheet

Thursday, April 08, 2010
1

47

of

50

8

http://hobi-elektronika.net

7

6

8 PROC_DPRSLPVR

H_VID6

8

H_VID5

8

H_VID4

8

H_VID3

8

H_VID2

8

H_VID1

8

H_VID0

2

1

Icc_TDC

Icc_Dyn

Auburndale 45W

0.85

HFM_Icc
50

1.9m

37

35

Auburndale 35W

0.85

38

1.9m

29

27

Clarksfield SV

0.95

52

1.9m

38

39

Clarksfield XE

0.95

65

TBD

48

TBD

HFM_VID

PSI#

8

3

LL

H

PH0

PH1

# of PH

+5VS

PR902
10_0603_5%

0

0

1

0

1

2

1

1

3

+CPU_B+
PL901
FBMA-L18-453215-900LMA90T_1812

2

H

4

1

8

5

PC904
2200P_0402_50V7K
2
1

3212_BST1

36

3
2
1

1

5

5

PR917
PC908
2.2_0603_5%
0.1U_0603_25V7K
2
13212_BST1-1
2
1
PQ903

IMON

SW1

3212_DRVH1

TPCA8028-H_SOP-ADVANCE8-5
3212_DRVL1
4

3212_DRVL1

TPCA8028-H_SOP-ADVANCE8-5

4

3212_SW1

34

FBRTN

PVCC

5
6

FB

DRVL1

$'3015*B4)1B;

1

12P_0402_50V8J
3212_FB PC913

PR923
7
COMP
39.2K_0402_1%
23212_COMP-1
1
23212_COMP
2
13212_TRDET#
8
PR924
5.11K_0402_1% TRDET

32

PGND

TPCA8028-H_SOP-ADVANCE8-5

PC907
68U_25V_M_R0.36

1
1
2

D

PR932
10_0402_5%

2

3
2
1

4

3
2
1

3212_DRVL2

2

TPCA8028-H_SOP-ADVANCE8-5
3212_DRVL2
4

3CSREF-2

2

1

SWFB3

PWM3

PQ908

Layout note:
Boost Parts close

24

OD3

23

22

ILIM

5

CSCOMP

PQ907

3212_ILIM

21

2.2_0603_5%

PR938
1.91K_0402_1%
2

2

2
PR945
100_0402_1%
2
1

+CPU_CORE

VCCSENSE
VSSSENSE

VCCSENSE

8

VSSSENSE

8

2

PR941
71.5K_0402_1%
2
1

LL=1.9m ohm
OCP=60A
VID:0.8~0.85V
Io(max)=48A

1

220K_0402_5%_ERTJ0EV224J~D

C

3212_CSCOMP-1
+VCCP

PR943 137K_0603_1%
2
1

3212_CS_PH1

2

3212_CS_PH2

PR944

B

PR942
165K_0402_1%
1
2

PH902

1

PC925
1U_0603_16V6K

@ PH901
100K +-1% NCP15WF104F03RC 0402

PC924
1200P_0402_50V7K
1
2

PC923
390P_0402_50V7K
2
1

2

1TTSENSE-12

PC922
1000P_0402_50V7K

Layout note:
Close Phase 1 MOS

Layout note:
Close to PHASE 1
inductor on the same layer

1

1

2 PR939

1K_0402_1%

CSREF

2

3212_BST2 2

25

1

20
3212_CSCOMP

CSREF

CSSUM
19

18

RAMP

LLINE
17

PR936
649K_0402_1%

2

1

1

+CPU_B+

PC921
@ 0.01U_0402_50V7K

PR940
@ 0_0402_5%

BST2

DCR=1.1mȍ ±7%
PL903
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

Connect to input caps
TTSENSE

C

3212_CSSUM

3212_VRTT

3212_CSCOMP

1

2
G

S

2

PR937
7.32K_0402_1%

2
13212_IREF13
PR933
80.6K_0402_1%
2
13212_RPM14
PR934
69.8K_0402_1%
2
13212_RT 15
PR935
162K_0402_1%
3212_RAMP-1 2
1 3212_RAMP
16

1

+5VS

D

3

@ PQ909

2N7002W-T/R7_SOT323-3

1

3212_VRTT-1

2

RT

AGND

RPM

GND

2

49

IREF

12

3212_SW2

CSREF

1

PR929
@ PR928
499_0402_1%

1

PQ906
TPCA8030-H_SOP-ADV8-5
PC919
0.1U_0603_25V7K
13212_BST2-2
2
1

3
2
1

DRVH2

5

TTSNS

PC915
10U_1206_25VAK

4

2

2
3212_DRVH2

3212_DRVH2

26

3212_CS_PH2

SW2

3212_CS_PH2
3212_SW2

27

1

VRTT

3212_SWFB2
1
2
100_0402_1%

28

PR931
4.7_1206_5%

11

SWFB2

1CPU_SNB2
2

TTSENSE

VARFR

PC920
680P_0603_50V8J

10

PC917
2200P_0402_50V7K
2
1

3212_VRTT
+3VS

5,34 H_PROCHOT#

1

3212_DRVL2

@ PC916
0.1U_0603_25V7K

9

1

1

2

30
29

PR925

+5VS

PR930
@ 0_0402_5%

Avoid high dV/dt

+CPU_B+

Close IC

PC911
4.7U_0603_6.3V6M

E

DRVL2

PC914
150P_0402_50V8J

PR927
0_0402_5%

D

3
2
1

+5VS
3212_DRVL1

31

5

VCCSENSE-1

1

2

2
PR926
0_0402_5%

3212_CS_PH1

2

F

PR919
10_0402_5%

2

PR922
1.65K_0402_1%
1
2

E

3212_SWFB1
1 PR921

33

2

SWFB1

1

PC912 150P_0402_50V8J
1
2

CLKEN

100_0402_1%

3212_FBRTN

1

PC910
1000P_0402_50V7K

4

2

1
2

3212_CLK_EN#

PC901
0.082U_0402_16V7K

2

PR920
4.99K_0402_1%

3
2
1

1

3

DRVH1

2

IMVP_IMON

PWRGD

35

+CPU_CORE

3CSREF-1

2

1

BST1

PL902
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
4

CSREF

EN

3212_SW1

1CPU_SNB1
2

2
IMVP_IMON

2

8

2

PC906
10U_1206_25VAK

1
2

5

PC905
10U_1206_25VAK

PC903
0.1U_0603_25V7K
2
1

1
2
3212_VCC
37

38

VCC

PH1

39

3212_PSI#
PSI

40

41

3212_VID5

3212_VID6
VID6

42

43
VID5

3212_VID3

3212_VID4
44
VID4

3212_VID2

VID3

45

3212_VID1

46

DCR=1.1mȍ ±7%
Layout note:
Boost Parts close

PC909
680P_0603_50V8J

3212_PWRGD

PR916
0_0402_5%

2

G

PQ902
TPCA8030-H_SOP-ADV8-5

4

PQ904
@

B+
+

3212_CS_PH1

1

VID2

48
VID0

47

1

1
PR912
3K_0402_5%

3212_EN

3212_DRVH1

@

1
1

PR918
4.7_1206_5%

F

PC902
1U_0603_16V6K

PC918
10U_1206_25VAK

VGATE

1

15,34

2

2

+VCCP

PU901

PR913
0_0402_5%

CLK_EN#

3212_CLK_EN#
PR915
0_0402_5%
2
1

2

12

PR914
0_0402_5%
2
1

VID1

1

3212_VID0

+3VS

PH0

+3VS

PR901
3K_0402_5%

2

PR911
499_0402_1%
3212_DPRSLP 2
1

VR_ON

DPRSLP

34
G

Shortest the
net trace

1

H_VID0

2

1PR947 @ 1K_0402_5%

H_VID0

2

1PR955

1K_0402_5%

H_VID1

2

1PR948 @ 1K_0402_5%

H_VID1

2

1PR956

1K_0402_5%

H_VID2

2

1PR949

1K_0402_5%

H_VID2

2

1PR957 @ 1K_0402_5%

H_VID3

2

1PR950 @ 1K_0402_5%

H_VID3

2

1PR958

1K_0402_5%

H_VID4

2

1PR951 @ 1K_0402_5%

H_VID4

2

1PR959

1K_0402_5%

H_VID5

2

1PR952

1K_0402_5%

H_VID5

2

1PR960 @ 1K_0402_5%

H_VID6

2

1PR953 @ 1K_0402_5%

H_VID6

2

1PR961

PROC_DPRSLPVR

2

1PR954

PROC_DPRSLPVR

2

1PR962 @ 1K_0402_5%

137K_0603_1%

0603 package
at least

Auburndale SV:
ULV:

1

10K_0402_5%

B

1K_0402_5%

VID(0-5):001001
VID(0-5):001010

PR946
100_0402_1%
A

A

Compal Secret Data

Security Classification

2010/01/13

Issued Date

Layout note:
Close CPU pin

Deciphered Date

2011/01/13

Title

CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
Date:

8

7

6

5

4

3

Compal Electronics, Inc.

2

Document Number
Thursday, April 08, 2010

Rev
0.3
Sheet

48
1

of

50

5

http://hobi-elektronika.net
4

3

2

9HUVLRQFKDQJHOLVW 3,5/LVW
,WHP
D

5HDVRQIRUFKDQJH

3*

0RGLI\/LVW

1

3DJHRI
IRU3:5

'DWH

3KDVH



Add S3_0.75V_EN for 0.75 enable singal

44

Add PR523 and reserve PR521

11/09

Before A



Modify VGA GPIO table for NVIDIA SPEC.

45

Reserve PR615, PR617, PR618 and PC617
PR612, PR613 change to 84.5K from 100K

11/09

Before A

D





C

C








B

B








A



20081022

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2009/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

A

2

Title

PIR (PWR)
Size Document Number
Custom

Rev
0.3



Date:

Sheet

Thursday, April 08, 2010
1

49

of

50

5

D

http://hobi-elektronika.net
4

OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!QVSQPTF
........................................................................
WFS/!S1`2141
41
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2
46
LC!Nbusjy!dibohf
3
42
FND2514.2!dibohf!up!FND2514.3
4
51-53
QPXFS!npejgz!QR424-QV213
5
dibohf!VTC!qpsu!!!!!!!!GQ!!;!qpsu21
6
!!!!!!!!!!!!!!!!!!!!!!VTC4!;!qpsu!:
7
dibohf!VTC!qpxfs!!!!
8
2213E!NPEJGZ

9
:
21
22
23
24
25
26
27
28
29
2:
31
32
33
34
35

C

44
46
49
47
38
24
2215ENPEJGZ
27
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39
37
3:
36
26
25
9
25
221:ENPEJGZ

36
37
38
39

25
27
38
45

3:

37
6

B

1

OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!QVSQPTF
..................................................................................
2

QWU

35

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EGC!sfrvftu

3

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39

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CPN!fssps

4

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49

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dptu!epxo

5

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49

SH5-SH6!dibhof!67l!pin

SD!gjmufs!gps!H.tfotps!pvuqvu-!FD!sfrvftu/

6

QWU

48

KCU2!dibohf!up!7!qjo

Gps!7!qjo!CU!npevmf

7

QWU

45

TVTDML!dpoofdu!up!dmpdl!pvu

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S:89!56!up!1!pin

Gps!FDSPN!dbo(u!gmbti

D

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45

Bee!R74!3O8113-!S455!21L

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:

QWU

45

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sftfswf!gps!qpxfs!tbwjoh

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DIBOHF!OFU!OBNF
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EFM!DMSQ2

21

QWU

45

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22

QWU

24

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dptu!epxo

23

QWU

44

JOU`NJD`DML!bee!DB29!211qG!dbq/

FNJ!sfrvftu

24

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44

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25

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39

Bee!R56!3O8113

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26

QWU

38

dibohf!V53!up!TU

dptu!epxo

27

QWU

38

Bee!R75-R48-S551

dptu!epxo-!fobcmf!clm!djsdvju

Bee!!V26-S284-S288-S289-S738-S739

28

QWU

37

Bee!S433-S439!1!pin

Gps!#opo.QoQ!efwjdf#!cvh

29

QWU

33

Bee!S585!45/9L!pin

O.wjejb!O22N.MQ2!efwjdf!JE

Bee!!R55-R56-R5:-R66-R71-R73-S447
Bee!!R72-R74
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Bee!U35!QBE-U36!QBE
Bee!S393
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2:

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gps!FEJE!dbo(u!efufdu!tpnfujnf-!dptu!epxo

31

QWU

28

S319!dibohf!up!2!pin

DSU!hbscfhf!jo!vnb!npef

32

QWU

27

S691!bee!1!pin

gps!cvh-!vnb!txjudi!up!ejt!xjmm!iboh!vq

33

QWU

26

S286!3/3l!up!5/8l!pin

dpnnpo!eftjho!vqebuf

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dpnnpo!eftjho
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35

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1:

D86-D87-D:3-D275!dibohf!up!444vG!7n!pin

36

QWU

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R5-RH2-R43-R44-R84-R85-R86-R:8!dibohf!up!BP4524 dptu!epxo

37

QWU

45

Bee!S456!21Lpin

C

FD`UBDI!qvmm!vq

OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!QVSQPTF
..................................................................................

OP!EBUF!!!QBHF!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!QVSQPTF
..................................................................................
A

2

9

Efm!S92-S94
Bee!U37!QBE-D798
Bee!S482-S483
Efm!R37-S414!U32QBE
Bee!S341-R28
Efm!R72-R74!!Bee!R::B-R::C
Bee!R72-S527
KGJS!DPOO!dibohf!KMFE!DPOO
bee!UQ3:-S431-S439-S341

45

3

2

TWU

4:

Bee!S679-!R51

,1/86WT!ejtdibshf

3

TWU

4:

Bee!S784!21L

,2/6W!FO!qjo!qvmm!epxo

4

TWU

4:

Dibohf!V44!up!Mpx!Set.po!uzqf

WSBN!wpmubhf!espq

5

TWU

48

Bee!FNJ!dpnnpo!dipdl!po!VTC!q2-q1
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.5
Linearized                      : No
Encryption                      : Standard V5.5 (256-bit)
Warning                         : Incomplete Encrypt specification

EXIF Metadata provided by EXIF.tools