LA6911P P7YE0/P7YH0/P7YS0 R0.3 LA 6911P

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A

B

Compal Confidential
1

C

D

E

Model Name : P7YE0/P7YH0/P7YS0
File Name : LA-6911P
BOM P/N:43

1

Compal Confidential
2

2

P7YE0/P7YH0/P7YS0 M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
ATI Seymour/Whistler/Granville

2010-11-01

3

3

REV:0.3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

1

of

60

http://hobi-elektronika.net

A

B

C

D

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Fan Control

page 40

204pin DDRIII-SO-DIMM X2

1

Channel A
PEG(DIS)

100MHz

PCI-E 2.0x16 5GT/s PER LANE

ATI Seymour/
Whistler/
Granville

Intel
Sandy Bridge

133MHz

BANK 0, 1, 2, 3

1

page 11

Memory BUS(DDRIII)
Two Dimm Per Channel
1.5V DDRIII 1066/1333/

Processor

204pin DDRIII-SO-DIMM X2

page22`29

BANK 0, 1, 2, 3

Channel B

rPGA988B

page 12

page 4~10

HDMI(DIS)

CRT(DIS)

HDMI Conn.

LVDS(DIS) EDP(DIS)

CRT Conn.

page 32

FDI x8

LVDS Conn. USBx1(3D)

page 31

page 30

USB port 4

2

100MHz

100MHz

2.7GT/s

1GB/s x4

LVDS(UMA)
CRT(UMA)
TMDS(UMA)

HDMI(UMA)

DMI x4

Intel
Cougar Point-M

USB 2.0 conn x2
USB port 0,1 on USB/B

Bluetooth
Conn

CMOS Camera

Card Reader
RTS5138

USB port 13

USB port 10

USB port 11

page 36

page 36

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

page 36

page 30

2

PCH
port 3

port 2

USB 2.0 conn x1

MINI Card x2
WLAN, WWAN
USB port 8,9 page 35

page 42

port 1

HDA Codec

100MHz

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)

page 13~21

AR8151/8152

SPI ROM x1

page 34

RJ45

3

page 34

SATA HDD
Conn. x2
page

33

USB/B 2Port
USB Port0,1
page 13

Int. Speaker

page 13

port 2

SATA CDROM
Conn. page 33

Combo Jack x 1
MIC Jack x1

page 39

page 39

LPC BUS

3

33MHz

ENE KB930

Sub-board
LS-6911P

page 37

CPU XDP

page 35

Int.KBD

Touch Pad
page 38

LS-6912P
Power On/Off CKT.

page 39

SPI

LAN(GbE)

port 0,1

RTC CKT.

ALC271X/277X

989pin BGA

100MHz

page 6

page 38

LAN/B

page 38

page 37

BIOS ROM
DC/DC Interface CKT.
page 41

4

LS-6914P

LS-6913P
PWR/B

page 38

LID/B

4

page 34

Power Circuit DC/DC
page 43~

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

2

of

60

A

Voltage Rails
Power Plane

1

2

http://hobi-elektronika.net

Description

B

C

S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

BATT+

Battery power supply (12.6V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+VGA_CORE

Core voltage for GPU

ON

OFF

OFF

D

SIGNAL

STATE
Full ON

SLP_S1# SLP_S3# SLP_S4# SLP_S5#
HIGH

HIGH

HIGH

E

+VALW

+V

+VS

HIGH

ON

ON

ON

Clock
ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

+VGFX_CORE

Core voltage for UMA graphic

ON

OFF

OFF

+0.75VS

+0.75VP to +0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VSDGPU

+1.0VSDGPU switched power rail for GPU

ON

OFF

OFF

+1.05VS_VTT

+1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU

ON

OFF

OFF

+1.05VS_PCH

+1.05VS_VTT to +1.05VS_PCH power for PCH

ON

OFF

OFF

+1.5V

+1.5VP to +1.5V power rail for DDRIII

ON

ON

OFF

+1.5VS

+1.5V to +1.5VS switched power rail

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.5VSDGPU

+1.5V to +1.5VSDGPU switched power rail for GPU

ON

OFF

OFF

Board ID

+1.8VS

(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON

OFF

OFF

+3VALW

+3VALW always on power rail

ON

ON

ON*

+3VALW_PCH

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

ON

ON

ON*

+3VS

+3VALW to +3VS power rail

ON

OFF

OFF

+5VALW

+5VALWP to +5VALW power rail

ON

ON

ON*

+5VALW_PCH

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

ON

ON

ON*

+5VS

+5VALW to +5VS switched power rail

ON

OFF

OFF

+VSB

+VSBP to +VSB always on power rail for sequence control

ON

ON

ON*

0
1
2
3
4
5
6
7

+RTCVCC

RTC power

ON

ON

ON

1

Board ID / SKU ID Table for AD channel
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

BOARD ID Table

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

2

BTO Option Table

BTO Item
BOM Structure
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID
PCB Revision
UMA Only
UMAO@
0
0.1
Muxless/UMA
UMA@
EC SM Bus1 address
EC SM Bus2 address
1
0.2
P9,P19,P23,P30-32,P59
DIS Only
DISO@
2
0.3
P4,P14
Device
Address
Device
Address
Muxless/DIS
DIS@
3
1.0
P.22-28
Smart Battery
0001 011X b
Muxless/DIS
VGA@
4
BACO mode
BACO@
P.26 ,P.29
PCH SM Bus address
5
nonBACO mode
NOBACO@
VRAM P/N
6
P.27,28
Device
Address
VRAM
X76@
SAM 64*16 900M SA00004GS10(S IC D3 64M16 K4W1G1646G-BC11 FBGA ABO!)
7
P.27
ChannelA
DIMM0
JDIMM1
1010 000X
A0
SAM 64*16 800M SA000035720(S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
128bit
VRAM
128@
SAM 128*16 800M SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!)
P.23,P.59
DIMM1
JDIMM3
1010 001X
A2
HYN 64*16 900M SA000041S40(S IC D3 64MX16 H5TQ1G63DFR-11C FBGA ABO!)
Granville GPU
GRAN@
HYN 64*16 800M SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!)
P.59
ChannelB
DIMM0
JDIMM2
1010 010X
A4
HYN 128*16 800M SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!)
Whistler
GPU
WHIS@
3
SA0000324G0(S
IC
D3
64M16
H5TQ1G63DFR-12C
FBGA
ABO!)
HYN 64*16 800M
P.22-26
DIMM1
JDIMM4
1010 011X
A6
Seymour
GPU
SEYM@
USB Port Table
P.23,P.25
non Granville GPU NOGRAN@
BT Config
GPU config
BACO config
3 External
P.35
Blue Tooth
BT@
USB 2.0 USB 1.1 Port
USB
Port
BT@
WHIS@
BACO@
BACO:
BT SKU:
Whistler:
Connector
CONN@
SEYM@
NOBACO@
4DIMM config
Seymour:
nonBACO:
0
USB/B(Right side 2.0 option)
UHCI0
Unpop
@
4DIMM@ Granville:
GRAN@
4 DIMM:
Muxless config
1
USB/B(Right side 2.0 option)
MUXL@
Muxless:
2
Granville config
LVDS/eDP config
USB port(left side 2.0)
P.30,59
UHCI1
DIS eDP
DEDP@
GRAN@ (VDDCI)
3
UMA LVDS: ULVDS@ Granville:
nonMuxless: NOMUXL@ (DISO,UMAO)
USB/B(Right side 3.0 option)
P.30
EHCI1
UMA LVDS
ULVDS@
4
DIS LVDS: DLVDS@ nonGranville: NOGRAN@ (VGA_CORE)
UHCI2
VRAM BOM Config
DIS LVDS
DLVDS@
DEDP@
5
DIS eDP:
GPU Frame config
P.18,P.32
X76264BOL01: 64Mx16x4 Seymour
512M HYN NEW
Muxless
MUXL@
128@ (WHIS,GRAN)
6
128bit:
P.18
X76264BOL02: 64Mx16x4 Seymour
512M HYN OLD
UHCI3
non Muxless
NOMUXL@
7
P.41
X76264BOL03: 64Mx16x8 Whistler/Granville 1G HYN NEW
USB2.0 Conn
USB2@
8
Mini Card(WLAN)
P.41
X76264BOL04: 64Mx16x8 Whistler/Granville 1G HYN OLD
UHCI4
USB3.0 Conn
USB3@
9
Mini Card
P.11-12
X76264BOL05: 128Mx16x8 Whistler/Granville 2G HYN
4 Dimm
4DIMM@
10
Camera
X76264BOL06: 128Mx16x8 Whistler/Granville 2G SAM
EHCI2
UHCI5
11
Card Reader
X76264BOL07: 128Mx16x4 Seymour
1G SAM
4
12
X76264BOL08: 128Mx16x4 Seymour
1G HYN
UHCI6
13
Blue Tooth
BOM Config
BT@/UMAO@/UMA@/ULVDS@/NOMUXL@
+DIMM,USB option
* UMA Only LVDS Panel:
BT@/DIS@/VGA@/DISO@/DLVDS@/NOMUXL@
+DIMM,USB option Security Classification
+X76+GPU
* DIS Only LVDS Panel:
Compal Secret Data
Compal Electronics, Inc.
Title
2010/07/12
2012/07/12
+DIMM,USB option
BT@/DIS@/VGA@/DISO@/DEDP@/NOMUXL@
+X76+GPU
Issued Date
DIS Only EDP Panel:
Deciphered Date
SCHEMATIC,MB A6911
BT@/UMA@/DIS@/VGA@/ULVDS@/BACO@/MUXL@
+X76+GPU(S,W) +DIMM,USB option THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
* Muxless BACO LVDS Panel:
Size Document Number
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
+DIMM,USB option DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Muxless nonBACO LVDS Panel: BT@/UMA@/DIS@/VGA@/ULVDS@/NOBACO@/MUXL@ +X76+GPU(G)
4019A9
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

A

B

C

D

Tuesday, November 09, 2010

Sheet

E

3

of

60

3

4

http://hobi-elektronika.net
B

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms

C

D

+1.05VS_VTT

R532
24.9_0402_1%

15
15
15
15

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

15
15
15
15

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

15
15
15
15

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

DMI

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

15
15
15
15
15
15
15
15

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

15 FDI_FSYNC0
15 FDI_FSYNC1

J18
J17

FDI0_FSYNC
FDI1_FSYNC

15 FDI_INT

H20

FDI_INT

15 FDI_LSYNC0
15 FDI_LSYNC1

J19
H17

FDI0_LSYNC
FDI1_LSYNC

A18
A17
B16

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

C15
D15

eDP_AUX
eDP_AUX#

C17
F16
C16
G15

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

C18
E16
D16
F15

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

1

+1.05VS_VTT

R118
24.9_0402_1%

EDP_COMP
3

eDP

2

eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
should not be left floating
,even if disable eDP function...

B27
B25
A25
B24

PCI EXPRESS* - GRAPHICS

2

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

Intel(R) FDI

PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

15
15
15
15

2

JCPU1A
1

PEG_GTX_HRX_N[0..15] 22
PEG_GTX_HRX_P[0..15] 22

E

1

A

PEG_COMP

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

J22
J21
H22

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

C320
C316
C313
C308
C300
C297
C287
C275
C262
C249
C244
C233
C224
C207
C206
C194

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_GTX_HRX_N15
PEG_GTX_HRX_N14
PEG_GTX_HRX_N13
PEG_GTX_HRX_N12
PEG_GTX_HRX_N11
PEG_GTX_HRX_N10
PEG_GTX_HRX_N9
PEG_GTX_HRX_N8
PEG_GTX_HRX_N7
PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
PEG_GTX_HRX_N4
PEG_GTX_HRX_N3
PEG_GTX_HRX_N2
PEG_GTX_HRX_N1
PEG_GTX_HRX_N0

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

C318
C314
C309
C303
C298
C288
C278
C265
C255
C246
C235
C225
C214
C210
C196
C190

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_GTX_HRX_P15
PEG_GTX_HRX_P14
PEG_GTX_HRX_P13
PEG_GTX_HRX_P12
PEG_GTX_HRX_P11
PEG_GTX_HRX_P10
PEG_GTX_HRX_P9
PEG_GTX_HRX_P8
PEG_GTX_HRX_P7
PEG_GTX_HRX_P6
PEG_GTX_HRX_P5
PEG_GTX_HRX_P4
PEG_GTX_HRX_P3
PEG_GTX_HRX_P2
PEG_GTX_HRX_P1
PEG_GTX_HRX_P0

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

C685
C683
C680
C676
C673
C671
C667
C663
C661
C659
C654
C648
C644
C640
C637
C631

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

C684
C681
C677
C674
C670
C668
C664
C662
C658
C657
C650
C645
C641
C636
C635
C626

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

1

2

3

Sandy Bridge_rPGA_Rev0p61
CONN@

Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Issued Date

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

4

of

60

http://hobi-elektronika.net

A

B

C

D

+1.05VS_VTT

R418
4.7K_0402_5%
1
2
@

2

+3VS

6

14,34 PCH_SMBDATA

XDP_PREQ#
XDP_PRDY#

+3VS

Q26A @
R407
DMN66D0LDW-7_SOT363-6
+3VS
4.7K_0402_5%
1
2
@

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

5

+3VS

1

3

14,34 PCH_SMBCLK

SMB_CLK_S3

4

+1.05VS_VTT

JXDP1

SMB_DATA_S3

1

E

XDP_BPM#4
XDP_BPM#5

Q26B @
DMN66D0LDW-7_SOT363-6

XDP_BPM#6
XDP_BPM#7

Connect to CPU,PCH XDP
H_CPUPWRGD

R605 1
R603 1

@
@

2 1K_0402_5%
2 0_0402_5%

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

CFG0
SYS_PWROK

R602 1
R600 1

@
@

2 1K_0402_5%
2 0_0402_5%

XDP_HOOK2
SYS_PWROK_XDP

15,36 PBTN_OUT#
7

CFG0

SMB_DATA_S3
SMB_CLK_S3
XDP_TCK

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

1

CLK_CPU_ITP
CLK_CPU_ITP#
XDP_RST#_R R601 2
XDP_DBRESET#

CLK_CPU_ITP 14
CLK_CPU_ITP# 14
@

1 1K_0402_5%

PLT_RST# 17,34,35,36,41

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
+1.05VS_VTT

SAMTE_BSH-030-01-L-D-A
CONN@

Debug port DG 0.65~
Note: 1. These signals are optional, can be left as OPEN/No-Connect if debug by Intel will not be needed

PROC_SELECT#
Future platforms,PH VCPLL and connect to PCH DF_TVS

18,36

R220 2

+1.05VS_VTT

1 10K_0402_5% H_CPUPWRGD

H_CATERR#

AL33

CATERR#

1 62_0402_5%
H_PROCHOT#

36,45 H_PROCHOT#

H_PECI

H_PECI

AN33

PECI

R216
56_0402_5%
1
2

AL32

PROCHOT#

H_PROCHOT#_R

AN32

18 H_THRMTRIP#

1

CLOCKS

XDP_TDI
XDP_TDO

DBR#

AL35

XDP_DBRESET#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

2

5
P

BUFO_CPU_RST#

18 H_CPUPWRGD

R227
43_0402_1%
1
2 BUF_CPU_RST#

H_CPUPWRGD

PM_SYNC

AP33

UNCOREPWRGOOD

UNCOREPWRGOOD:ॺCORE؆ऱሽOK
PM_DRAM_PWRGD_R

V8

SM_DRAMPWROK

1

SM_DRAMPWROK:DRAM power ok
BUF_CPU_RST#

R225
1K_0402_1%
@

+3VALW

AR33

RESET#

SM_DRAMRST# 6

2
2
2

1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%

+1.05VS_VTT

XDP_TMS

R202 2

@

1 51_0402_5%

XDP_TDI

R210 2

@

1 51_0402_5%

XDP_TDO

R200 2

@

1 51_0402_5%

XDP_TCK

R209 2

@

1 51_0402_5%

XDP_TRST#

R205 2

@

1 51_0402_5%

+3VS
XDP_DBRESET# R569 2

1 1K_0402_5%
3

CRB1.0 PH 1K +3VS
Check list 1.0 PH 5K +3VS
Check list 1.2 PH 10K +3VS
Debug port DG1.1-1.2 50~5K ohm
XDP_DBRESET# 15

Sandy Bridge_rPGA_Rev0p61
CONN@

1

1

Use open drain MOS:
+1.5V_CPU_VDDQ PH pop 200ohm
series resister pop 130ohm

1 1K_0402_5%

CLK_CPU_DPLL 14
CLK_CPU_DPLL# 14

DDR3 Compensation Signals

AR28
AP26

+1.5V_CPU_VDDQ

R88
200_0402_5%
5

4

PM_SYS_PWRGD_BUF

2
130_0402_5%

4

PM_DRAM_PWRGD_R
R104
1.3K_0402_1%
@

MC74VHC1G09DFT2G SC70 5P

2

3

1
R97

1

Y
A

G

1

15 PM_DRAM_PWRGD

P

U5
2 B

15 SYS_PWROK

2

2

4

SM_RCOMP0 R149
SM_RCOMP1 R486
SM_RCOMP2 R484

TDI
TDO

AM34

RESET#:ຟok৵ᓮCPU೚reset

C101
0.1U_0402_16V4Z

AK1
A5
A4

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

+1.05VS_VTT

15 H_PM_SYNC

R117 2

PU/PD for JTAG signals

XDP_TCK
XDP_TMS
XDP_TRST#

SN74LVC1G07DCKR SC-70 5P

Follow DG 1.2 & CRB1.0

SM_DRAMRST#

TCK
TMS
TRST#

2

A

R8

SM_DRAMRST#

XDP_PRDY#
XDP_PREQ#

G

1
2 1
@ R249
0_0402_5%

3

PLT_RST#

CLK_CPU_DPLL
CLK_CPU_DPLL#

AR26
AR27
AP30

R226
75_0402_5%

4

Y

A16
A15

AP29
AP27

C396
0.1U_0402_16V4Z

CLK_CPU_DPLL

CLK_CPU_DMI 14
CLK_CPU_DMI# 14

PRDY#
PREQ#

2
U15
2 B

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

JTAG & BPM

3

A28
A27

Use open drain MOS:
+1.05VS_VTT PH pop 75ohm
series resister pop 43ohm

PWR MANAGEMENT

+3VS

BCLK
BCLK#

THERMTRIP#

1

Follow DG 1.2 & CRB1.0
Buffered reset to CPU

SKTOCC#

THERMAL

Follow DG 1.2 & CRB1.0
2

PAD

AN34

@

Processor Pullups follow CRB1.0
R223

T2

XBOX Կદ‫פ‬౨

SNB_IVB#

DDR3
MISC

ೠྒྷCPU‫ڜྤڶ‬ᇘ

PCH->CPU
UNCOREPWRGOOD:ॺCORE؆ऱሽOK
SM_DRAMPWROK:DRAM power ok
RESET#:ຟok৵ᓮCPU೚reset

1 1K_0402_5%

2

C26

MISC

17 H_SNB_IVB#

R116 2

Checklist1.0 P.58 Graphis Disable Guide
DIS only SKU eDP disable
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT

JCPU1B
2

CLK_CPU_DPLL#

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

5

of

60

http://hobi-elektronika.net

A

B

2

11 DDR_A_BS0
11 DDR_A_BS1
11 DDR_A_BS2

3

11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_WE#

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AE10
AF10
V6

SA_BS[0]
SA_BS[1]
SA_BS[2]

AE8
AD9
AF9

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

1

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

AB6
AA6
V9

SA_CLK_DDR0 11
12 DDR_B_D[0..63]
SA_CLK_DDR#0 11
DDRA_CKE0_DIMMA 11

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

SA_CLK_DDR1 11
SA_CLK_DDR#1 11
DDRA_CKE1_DIMMA 11

SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]

AB4
AA4
W9

SA_CLK_DDR2 11
SA_CLK_DDR#2 11
DDRA_CKE2_DIMMA 11

SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]

AB3
AA3
W10

SA_CLK_DDR3 11
SA_CLK_DDR#3 11
DDRA_CKE3_DIMMA 11

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

AK3
AL3
AG1
AH1

DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#
DDRA_CS2_DIMMA#
DDRA_CS3_DIMMA#

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

AH3
AG3
AG2
AH2

SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C4
G6
J3
M6
AL6
AM8
AR12
AM15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

11
11
11
11

11
11
11
11

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

11

11

11

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

12 DDR_B_BS0
12 DDR_B_BS1
12 DDR_B_BS2

12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_WE#

Sandy Bridge_rPGA_Rev0p61 CONN@

2
SM_DRAMRST#

DIMM_DRAMRST#_R
1
Q6
BSS138_NL_SOT23-3

2

3

1

2

G

R79
4.99K_0402_1%
4

11,12,14 RST_GATE
1

2

AA9
AA7
R6

SB_BS[0]
SB_BS[1]
SB_BS[2]

AA10
AB8
AB9

SB_CAS#
SB_RAS#
SB_WE#

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

AE2
AD2
R9

SB_CLK_DDR0 12
SB_CLK_DDR#0 12
DDRB_CKE0_DIMMB 12

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

SB_CLK_DDR1 12
SB_CLK_DDR#1 12
DDRB_CKE1_DIMMB 12

SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]

AB2
AA2
T9

SB_CLK_DDR2 12
SB_CLK_DDR#2 12
DDRB_CKE2_DIMMB 12

SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]

AA1
AB1
T10

SB_CLK_DDR3 12
SB_CLK_DDR#3 12
DDRB_CKE3_DIMMB 12

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

AD3
AE3
AD6
AE6

DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#
DDRB_CS2_DIMMB#
DDRB_CS3_DIMMB#

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

AE4
AD4
AD5
AE5

SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

12
12
12
12

12
12
12
12

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

12

2

12

12

3

Sandy Bridge_rPGA_Rev0p61
CONN@

C78
0.047U_0402_16V7K

1

R63
1K_0402_5%
2

DIMM_DRAMRST# 11,12

S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

1

R66
1K_0402_5%

D

S

5 SM_DRAMRST#

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

1

@ R78
0_0402_5%
1
2

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

+1.5V

Follow CRB1.0

CPUຏवDIMM೚reset

E

JCPU1D

11 DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

D

DDR SYSTEM MEMORY B

JCPU1C

C

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

6

of

60

http://hobi-elektronika.net

A

B

C

D

E

CFG Straps for Processor
1

CFG2

2

R234
1K_0402_1%

1

1

PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane # definition matches
socket pin map definition

CFG2
JCPU1E

CFG2
CFG4
CFG5
CFG6
CFG7

2

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32

L7
AG7
AE7
AK2
W8

RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

RSVD37
RSVD38
RSVD39
RSVD40

T8
J16
H16
G16

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AR35
AT34
AT33
AP35
AR34

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

B34
A33
A34
B35
C35

RSVD51
RSVD52

AJ32
AK32

RSVD53

AH27

RSVD54
RSVD55

AN35
AM35

RSVD56
RSVD57
RSVD58

AT2
AT1
AR1

CFG4

UMA,Muxless eDPඔ೯
DISO eDPᣂຨ

1

CFG0

CFG0

2

5

0:Lane Reversed

*

R204
1K_0402_1%
@

eDP enable
CFG4

1:Disable

*

2

0:Enable
CFG6

RSVD1
RSVD2
RSVD3
RSVD4

AJ26

RSVD5

B4
D1

RSVD6
RSVD7

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

J20
B18
A19

RSVD24
RSVD25
RSVD26

J15

RSVD27

CFG5
R230
1K_0402_1% @

1

AJ31
AH31
AJ33
AH33

@

2

R69
1K_0402_1%

3

1

VCCIO_SEL

2

VCCIO_SEL

VCCIO_SEL For 2012 CPU support
A19

*

CFG[6:5]

(Default) 1x16 PCI Express
*11:
10: 2x8 PCI Express
01: Reserved

PAD

3

00: 1x8,2x4 PCI Express

T1

@
CFG7
R224
1K_0402_1%

@

2

R520
10K_0402_5%

@

PCIE Port Bifurcation Straps

1

1
2

R68
1K_0402_1%

RESERVED

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

11 SA_DIMM_VREFDQ
12 SB_DIMM_VREFDQ

1

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
For Future CPU M3 support,
Sandey bridge not supportM3,
Check list1.0&CRB say can NC

R228
1K_0402_1%

2

PAD @
PAD @
PAD @
PAD @

1

T4
T6
T5
T3

2

VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VALSENSE

PEG DEFER TRAINING

1/NC : (Default) +1.05VS_VTT

KEY

B1

CFG7

0: +1.0VS_VTT

CRB1.0 P.12

1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training

Sandy Bridge_rPGA_Rev0p61
CONN@
4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Issued Date

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

7

of

60

POWER
http://hobi-elektronika.net

A

B

C

D

E

JCPU1F

SV type CPU

5x TOP in,7x BOT in

QC 94A
DC 53A

PEG AND DDR

1

1

2

1

2

1

2

1

2

1

1

+ C594
2

+

C601
330U_6.3V_R15M

2
330U_6.3V_R15M

INTEL Recommend
2*330uF,12*22uF
from PDDG 1.0
2

1

1

+1.05VS_VTT

R580
75_0402_5%
2

2

SVID

CORE SUPPLY

AJ29
AJ30
AJ28

2

change to SF000002080
OS-CON 330U 6.3V ESR 15mohm H6

R574
130_0402_5%

VIDALERT#
VIDSCLK
VIDSOUT

1

Place TOP
IN Conn

+1.05VS_VTT

R576
43_0402_1%
1
2
R577 1
2 0_0402_5%
R578 1
2 0_0402_5%

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

VR_SVID_ALRT# 52
VR_SVID_CLK 52
VR_SVID_DAT 52

Place the PU
resistors close to VR

3

Place the PU
resistors close to CPU

1

+CPU_CORE

AJ35 VCCSENSE_R
AJ34 VSSSENSE_R

R579 1
R581 1

2
2

0_0402_5%
0_0402_5%

VCCSENSE 52
VSSSENSE 52
1

VCC_SENSE
VSS_SENSE

2

R588
100_0402_1%

B10
A10

R589
100_0402_1%

VCCIO_SENSE 48

VSSIO_SENSE
1

VCCIO_SENSE
VSSIO_SENSE

R105
10_0402_5%
2

SENSE LINES

Place BOT
Out Socket

2

2

C165
22U_0805_6.3V6M

Place BOT
Out Socket

1

1

C624
22U_0805_6.3V6M

SGA00001Q80 S POLY C 330U
2V M X LESR6M SX H1.9
change footprint to 2 pin
(C_X)

2

2

C151
22U_0805_6.3V6M

SGA00004V00
change footprint to
2 pin
(C_X)

1

1
@

C652
22U_0805_6.3V6M

2

2

2

C192
22U_0805_6.3V6M

+

1

1

C180
22U_0805_6.3V6M

2

C678
1

J23

2

2

C625
22U_0805_6.3V6M

2

+

VCCIO40

1

@

C109
22U_0805_6.3V6M

@

C354
1

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

2

C632
22U_0805_6.3V6M

+

330U_X_2VM_R6M

2

C332
1

330U_X_2VM_R6M

+

330U_X_2VM_R6M

2

C653
1
470U 2V M D2 LESR4M

+

470U 2V M D2 LESR4M

C242
1

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

+1.05VS_VTT
1
1

Place BOT IN Conn
C248
22U_0805_6.3V6M

2

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

C639
22U_0805_6.3V6M

1

C282
22U_0805_6.3V6M

2

C247
22U_0805_6.3V6M

1

2

C256
22U_0805_6.3V6M

2

1

Place TOP
Out Socket

+CPU_CORE

3

1

C333
22U_0805_6.3V6M

2

C259
22U_0805_6.3V6M

1

C335
22U_0805_6.3V6M

2

2

C312
22U_0805_6.3V6M

1

1

C342
22U_0805_6.3V6M

2

2

C305
22U_0805_6.3V6M

1

1

C346
22U_0805_6.3V6M

2

2

C283
22U_0805_6.3V6M

1

1

C272
22U_0805_6.3V6M

INTEL Recommend
4*470uF,16*22uF and 10*10uF
from PDDG 1.0

2

2

C232
22U_0805_6.3V6M

2

1

C245
22U_0805_6.3V6M

1
2

2

1

C296
22U_0805_6.3V6M

2

1

C325
22U_0805_6.3V6M

1

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

C106
22U_0805_6.3V6M

Place TOP
IN Socket

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

+1.05VS_VTT

Place TOP IN Conn

C642
22U_0805_6.3V6M

+CPU_CORE

8.5A

C619
22U_0805_6.3V6M

2

Place BOT
IN Socket

C649
10U_0805_6.3V6M

2

1

C669
10U_0805_6.3V6M

2

2

C660
10U_0805_6.3V6M

2

1

C666
10U_0805_6.3V6M

1

2

1

C293
10U_0805_6.3V6M

2

C634
10U_0805_6.3V6M

2

1

C638
10U_0805_6.3V6M

1

2

1

C656
10U_0805_6.3V6M

1

1

C627
10U_0805_6.3V6M

2

1

C277
10U_0805_6.3V6M

1

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

2

+CPU_CORE

Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.

4

4

CONN@
Sandy Bridge_rPGA_Rev0p61

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

8

of

60

http://hobi-elektronika.net
B

2

1 UMA@

2

SGA00001Q80 S POLY C 330U
2V M X LESR6M SX H1.9

Θ Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
Θ VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

SENSE
LINES

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

10A

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

H23

FC_C22
VCCSA_VID1

1
2

J6
@

1

2

1

2

1

2

1

2

1

2

INTEL Recommend
1*330uF,3*10uF
from PDDG 1.0
Place BOT
IN Conn

6A
M27
M26
L26
J26
J25
J24
H26
H25

+1.5V

Place BOT OUT Conn

Place BOT
OUT Conn

1

2

1

2

JUMP_43X118

1
+

C599
330U_D2_2V_Y

+1.5VS
2

J7

2

@

1

2

JUMP_43X118

Short for +1.5VS to +1.5V_CPU_VDDQ
change to SF000002000
OS-CON 330U 6.3V ESR 15mohm H6

INTEL Recommend
1*330uF,6*10uF
from PDDG 1.0

+VCCSA

+VCCSA
@

1

2

1

2

1

2

2

R1281

2 0_0402_5%

R1341

2 0_0402_5%

VCCSA_SENSE

VSSSA_SENSE 47

3

VCCSA_SENSE 47

CPU EDS1.3 P.93
VCCSA_VID0 Must PD
C22 VCCSA_VID0
C24

1

VCCSA_VID1

VCCSA_VID1 47

1

2

MISC

VCCPLL1
VCCPLL2
VCCPLL3

1

+1.5V_CPU_VDDQ

1.8V RAIL

2

B6
A6
A2

SGA20331E10 S POLY C 330U
2V 9mohm H1.9

C222
10U_0603_6.3V6M

2

1

C584
1U_0402_6.3V6K

change to SF000002080
OS-CON 330U 6.3V ESR 15mohm H6

2

1

C583
1U_0402_6.3V6K

2

C578
10U_0805_6.3V6M

+

1

R540
1K_0402_5%

C643
10U_0805_6.3V6M

+1.8VS_VCCPLL

1
C582
330U_6.3V_R15M

1.2A

Place BOT OUT Conn

1

C131
10U_0805_6.3V6M

R477
0_0805_5%
2

C647
0.1U_0402_16V4Z

C208
10U_0805_6.3V6M

1

+V_SM_VREF

AL1

2

3

+1.8VS

SM_VREF

R534
1K_0402_5%

C107
10U_0805_6.3V6M

Vaxg

+V_SM_VREF should
have 20 mil trace width

C112
10U_0805_6.3V6M

Place TOP OUT Conn

1

+1.5V_CPU_VDDQ

C149
10U_0805_6.3V6M

C693
330U_X_2VM_R6M
UMA@

VCC_AXG_SENSE 52
VSS_AXG_SENSE 52

C162
10U_0805_6.3V6M

2

AK35
AK34

C172
10U_0805_6.3V6M

+
2

VAXG_SENSE
VSSAXG_SENSE

C116
10U_0805_6.3V6M

1

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

2

2

1 UMA@
C334
22U_0805_6.3V6M

2

C694
22U_0805_6.3V6M

C343
22U_0805_6.3V6M

2

1 UMA@

2

C331
22U_0805_6.3V6M

1 UMA@

1 UMA@

C338
22U_0805_6.3V6M

1 UMA@
C665
22U_0805_6.3V6M

Place TOP OUT Conn

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

1 UMA@

VREF

2

JCPU1G

DDR3 -1.5V RAILS

1 UMA@
C266
22U_0805_6.3V6M

2

C280
22U_0805_6.3V6M

2

1 UMA@

Place TOP
IN Conn

2

DISO@

2

C696
22U_0805_6.3V6M

2

R184
0_0402_5%

2

1 UMA@

1 UMA@

E

POWER

QC 33A
DC 26A
C672
22U_0805_6.3V6M

1 UMA@

C699
22U_0805_6.3V6M

Place BOT OUT Conn

C708
22U_0805_6.3V6M

INTEL Recommend
2*470uF,12*22uF
from PDDG 1.0

1

1

Place BOT
IN Conn

D

SA RAIL

+VGFX_CORE

C

GRAPHICS

A

R119
10K_0402_5%

Sandy Bridge_rPGA_Rev0p61
CONN@

VCCSA

1

INTEL Recommend
1*330uF,1*10uF and 2*1uF(0402)
from PDDG 1.0

R129
0_0402_5%
@

2

VID0 VID1 Vout

2011CPU 2012CPU

0

0

0.9V

V

V

VCCSA_VID0

0

1

0.8V

V

V

For 2012 future CPU
VCCSA voltage select

1

0

0.725V

X

V

1

1

0.675V

X

V

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Issued Date

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Tuesday, November 09, 2010

Rev
B

4019A9
Sheet
E

9

of

60

A

http://hobi-elektronika.net
B

C

D

JCPU1H
1

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

2

3

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

E

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

1

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

Sandy Bridge_rPGA_Rev0p61
CONN@

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

2

3

Sandy Bridge_rPGA_Rev0p61
CONN@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

10

of

60

http://hobi-elektronika.net

A

B

+1.5V

C

+1.5V

1

DDR_A_D10
DDR_A_D11

6

DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]

6

DDR_A_D[0..63]

6

DDR_A_MA[0..15]

6

DDR_A_D16
DDR_A_D17

All VREF traces should
have 10 mil trace width

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25

Layout Note:
Place near JDIMM1

2

DDRA_CKE0_DIMMA

6 DDRA_CKE0_DIMMA

DDR_A_BS2

6 DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
+1.5V

+1.5V

DDR_A_WE#
DDR_A_CAS#

6 DDRA_CS1_DIMMA#

DDR_A_MA13
DDRA_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

2

DDR_A_DQS#4
DDR_A_DQS4

C14
330U_D2_2V_Y

DDR_A_D34
DDR_A_D35

SGA20331E10
330U 2V H1.9
9mohm POLY

DDR_A_D40
DDR_A_D41
DDR_A0_DM5
DDR_A_D42
DDR_A_D43

+0.75VS

DDR_A_D48
DDR_A_D49

DDR_A0_DM7
DDR_A_D58
DDR_A_D59

Layout Note:
Place near JDIMM1.203,204

R47

2 10K_0402_5%

1

+3VS

G1

G2

206

DDRA_CKE1_DIMMA

DDRA_CKE1_DIMMA 6

DDRA_CKE2_DIMMA

6 DDRA_CKE2_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_BS2

DDR_A_MA11
DDR_A_MA7

DDR_A_MA12
DDR_A_MA9

DDR_A_MA6
DDR_A_MA4

DDR_A_MA8
DDR_A_MA5

DDR_A_MA2
DDR_A_MA0

DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR1
SA_CLK_DDR#1

SA_CLK_DDR1 6
SA_CLK_DDR#1 6

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 6
DDR_A_RAS# 6

DDRA_CS0_DIMMA#
SA_ODT0

DDRA_CS0_DIMMA# 6
SA_ODT0 6

SA_ODT1

SA_CLK_DDR2
SA_CLK_DDR#2

6 SA_CLK_DDR2
6 SA_CLK_DDR#2

+1.5V

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#

R61
1K_0402_1%

DDR_A_MA13
DDRA_CS3_DIMMA#

SA_ODT1 6
6 DDRA_CS3_DIMMA#

+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A0_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

1

2

1

2

DDR_A_D32
DDR_A_D33
R62
1K_0402_1%

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A1_DM5

DDR_A_D46
DDR_A_D47

DDR_A_D42
DDR_A_D43

DDR_A_D52
DDR_A_D53

DDR_A_D48
DDR_A_D49

DDR_A0_DM6

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D55

DDR_A_D50
DDR_A_D51

DDR_A_D60
DDR_A_D61

DDR_A_D56
DDR_A_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_A1_DM7

DDR_A_D62
DDR_A_D63

DDR_A_D58
DDR_A_D59

D_CK_SDATA
D_CK_SCLK

R42

+3VS

2 4DIMM@1 10K_0402_5%

+3VS

D_CK_SDATA 12,14
D_CK_SCLK 12,14

+0.75VS

+0.75VS

FOX_AS0A626-U8SN-7F
CONN@

R41
10K_0402_5%
4DIMM@



1

2

DIMM_1 Reserve H:8mm

4DIMM@

1

2

4DIMM@
C15
2.2U_0603_6.3V6K

1

205

DDR_A_D26
DDR_A_D27

C21
0.1U_0402_16V4Z

2

R54
10K_0402_5%

2

1

C36
2.2U_0603_6.3V6K

1

2

+0.75VS
C44
0.1U_0402_16V4Z

DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM2
DDR_A0_DM3
DDR_A0_DM4
DDR_A0_DM5
DDR_A0_DM6
DDR_A0_DM7

DDR_A1_DM3

DDR_A_D30
DDR_A_D31

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

205

G1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

+1.5V

DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

4DIMM@
1

DDR_A_D30
DDR_A_D31

2

DDRA_CKE3_DIMMA

4DIMM@
1

2

4DIMM@
1

2

4DIMM@
1

2

DDRA_CKE3_DIMMA 6

DDR_A_MA15
DDR_A_MA14

Layout Note:
Place near JDIMM3

DDR_A_MA11
DDR_A_MA7
+1.5V

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR3
SA_CLK_DDR#3

1
SA_CLK_DDR3 6
SA_CLK_DDR#3 6
2

DDR_A_BS1
DDR_A_RAS#
DDRA_CS2_DIMMA#
SA_ODT2

DDRA_CS2_DIMMA#
SA_ODT2 6

SA_ODT3

SA_ODT3 6

1

2

1

2

1

2

2

6
4DIMM@ 4DIMM@ 4DIMM@ 4DIMM@
+1.5V

+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A1_DM4

1

DDR_A_D38
DDR_A_D39

2

DDR_A_D44
DDR_A_D45

1

2

@
1

2

DDR_A_DQS#5
DDR_A_DQS5
4DIMM@ 4DIMM@
DDR_A_D46
DDR_A_D47

+0.75VS

DDR_A_D52
DDR_A_D53
4DIMM@
DDR_A1_DM6

1

DDR_A_D54
DDR_A_D55

2

DDR_A_D60
DDR_A_D61

4DIMM@
1

2

4DIMM@
1

2

4DIMM@
1

2

C19
1U_0402_6.3V6K

DDR_A_D56
DDR_A_D57

DDR_A_D24
DDR_A_D25

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D22
DDR_A_D23

C32
1U_0402_6.3V6K

DDR_A_D50
DDR_A_D51

DDR_A_D28
DDR_A_D29

DDR_A1_DM2

C20
1U_0402_6.3V6K

2

DDR_A_D18
DDR_A_D19

C31
1U_0402_6.3V6K

2

1

C576
1U_0402_6.3V6K

2

1

C39
1U_0402_6.3V6K

2

1

C40
1U_0402_6.3V6K

3

C577
1U_0402_6.3V6K

1

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D22
DDR_A_D23

DDR_A_D20
DDR_A_D21

C27
10U_0603_6.3V6M

+

DDR_A_DQS#2
DDR_A_DQS2

1

DDR_A_D14
DDR_A_D15

C29
10U_0603_6.3V6M

1

DDR_A_D16
DDR_A_D17

DDR_A1_DM1
DIMM_DRAMRST#

C25
10U_0603_6.3V6M

2

6 DDR_A_WE#
6 DDR_A_CAS#

DDR_A_D10
DDR_A_D11

DDR_A0_DM2

C74
0.1U_0402_16V4Z

@

6 DDR_A_BS0

DDR_A_MA10
DDR_A_BS0

All VREF traces should
have 10 mil trace width

DDR_A_D20
DDR_A_D21

C77
2.2U_0603_6.3V6K

2

1

C76
10U_0603_6.3V6M

1

C71
10U_0603_6.3V6M

2

C72
10U_0603_6.3V6M

1

SA_CLK_DDR0
SA_CLK_DDR#0

6 SA_CLK_DDR0
6 SA_CLK_DDR#0

DIMM_DRAMRST# 6,12

DDR_A_D14
DDR_A_D15

DDR_A_D12
DDR_A_D13

C22
10U_0603_6.3V6M

2

DDR_A_DQS#1
DDR_A_DQS1

C18
10U_0603_6.3V6M

1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_A0_DM1
DIMM_DRAMRST#

DDR_A_D6
DDR_A_D7

C13
10U_0603_6.3V6M

2

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_D8
DDR_A_D9

DDR_A_DQS#0
DDR_A_DQS0

C23
10U_0603_6.3V6M

1

DDR_A_MA3
DDR_A_MA1

C41
10U_0603_6.3V6M

2

C42
10U_0603_6.3V6M

1

C35
10U_0603_6.3V6M

2

C43
10U_0603_6.3V6M

1
2

DDR_A_MA8
DDR_A_MA5

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_D12
DDR_A_D13

DDR_A_D4
DDR_A_D5

C16
1U_0402_6.3V6K

2

1

C34
1U_0402_6.3V6K

2

1

C75
1U_0402_6.3V6K

1

C73
1U_0402_6.3V6K

2

C38
1U_0402_6.3V6K

1

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C17
1U_0402_6.3V6K

DDR_A_D26
DDR_A_D27

DDR_A1_DM0

DDR_A_D6
DDR_A_D7

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C30
1U_0402_6.3V6K

DDR_A0_DM3

DDR_A_DQS#0
DDR_A_DQS0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C26
1U_0402_6.3V6K

+1.5V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D0
DDR_A_D1

1

DDR_A_DQS#1
DDR_A_DQS1

+V_DDR_REFA

DDR_A_D4
DDR_A_D5

2

DDR_A_D8
DDR_A_D9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

2

G

6,12,14 RST_GATE

2

DDR_A_D2
DDR_A_D3

E

+1.5V

JDIMM3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

2

2

BSS138_NL_SOT23-3

R53
1K_0402_1%

C33
0.1U_0402_16V4Z

1
Q4
@

C37
2.2U_0603_6.3V6K

D

S

3

1

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

2

DDR_A0_DM0
1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

1
7 SA_DIMM_VREFDQ

DDR_A_D0
DDR_A_D1

1

R55
0_0402_5%
1
2
@

+1.5V

JDIMM1

+V_DDR_REFA
R57
1K_0402_1%

M3 support

D

+1.5V

3

DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

Layout Note:
Place near JDIMM3.203,204

D_CK_SDATA
D_CK_SCLK
+0.75VS

DDR_A1_DM0
DDR_A1_DM1
DDR_A1_DM2
DDR_A1_DM3
DDR_A1_DM4
DDR_A1_DM5
DDR_A1_DM6
DDR_A1_DM7

FOX_AS0A626-U4RN-7F
CONN@



DIMM_3 Reverse type H:4mm

Channel A
4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

11

of

60

A

+V_DDR_REFB

DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19

All VREF traces should
have 10 mil trace width

Layout Note:
Place near JDIMM2

DDR_B_D24
DDR_B_D25

2

DDRB_CKE0_DIMMB

6 DDRB_CKE0_DIMMB

DDR_B_BS2

6 DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
+1.5V

DDR_B_DQS#4
DDR_B_DQS4

SGA20331E10
330U 2V H1.9
9mohm POLY

DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B0_DM5
DDR_B_D42
DDR_B_D43

+0.75VS

DDR_B_D48
DDR_B_D49

1

DDR_B0_DM7

R218
10K_0402_5%
2

Layout Note:
Place near JDIMM2.203,204

DDR_B_D58
DDR_B_D59

+3VS

1

2

R221
10K_0402_5%

2

1

C362
2.2U_0603_6.3V6K

1

2

+0.75VS
C363
0.1U_0402_16V4Z

DDR_B0_DM0
DDR_B0_DM1
DDR_B0_DM2
DDR_B0_DM3
DDR_B0_DM4
DDR_B0_DM5
DDR_B0_DM6
DDR_B0_DM7

205

G1

G2

206

DDR_B_D26
DDR_B_D27

DDRB_CKE1_DIMMB

DDRB_CKE1_DIMMB 6

DDRB_CKE2_DIMMB

6 DDRB_CKE2_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_BS2

DDR_B_MA11
DDR_B_MA7

DDR_B_MA12
DDR_B_MA9

DDR_B_MA6
DDR_B_MA4

DDR_B_MA8
DDR_B_MA5

DDR_B_MA2
DDR_B_MA0

DDR_B_MA3
DDR_B_MA1

SB_CLK_DDR1
SB_CLK_DDR#1

SB_CLK_DDR1 6
SB_CLK_DDR#1 6

DDR_B_BS1
DDR_B_RAS#

DDR_B_BS1 6
DDR_B_RAS# 6

DDRB_CS0_DIMMB#
SB_ODT0

DDRB_CS0_DIMMB#
SB_ODT0 6

SB_ODT1

SB_CLK_DDR2
SB_CLK_DDR#2

6 SB_CLK_DDR2
6 SB_CLK_DDR#2

+1.5V

DDR_B_MA10
DDR_B_BS0
6

DDR_B_WE#
DDR_B_CAS#

R176
1K_0402_1%

DDR_B_MA13
DDRB_CS3_DIMMB#

SB_ODT1 6
6 DDRB_CS3_DIMMB#

+VREF_CB
DDR_B_D36
DDR_B_D37
DDR_B0_DM4
DDR_B_D38
DDR_B_D39

1

2

1

2

DDR_B_D44
DDR_B_D45

DDR_B_D32
DDR_B_D33
R178
1K_0402_1%

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B1_DM5

DDR_B_D46
DDR_B_D47

DDR_B_D42
DDR_B_D43

DDR_B_D52
DDR_B_D53

DDR_B_D48
DDR_B_D49

DDR_B0_DM6

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D55

+3VS

+3VS

DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7

R217
10K_0402_5%
4DIMM@

DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK

R214
10K_0402_5%
4DIMM@

DDR_B1_DM7
DDR_B_D58
DDR_B_D59

+3VS

D_CK_SDATA 11,14
D_CK_SCLK 11,14

+0.75VS

+0.75VS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205

FOX_AS0A626-U8SN-7F
CONN@

C361
0.1U_0402_16V4Z
4DIMM@

1

1

2

2

C360
2.2U_0603_6.3V6K
4DIMM@



CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

G1

6

+1.5V

DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

4DIMM@
1

DDR_B_D30
DDR_B_D31

2

DDRB_CKE3_DIMMB

4DIMM@
1

2

4DIMM@
1

2

4DIMM@
1

2

DDRB_CKE3_DIMMB 6

DDR_B_MA15
DDR_B_MA14

Layout Note:
Place near JDIMM4

DDR_B_MA11
DDR_B_MA7
+1.5V

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

4DIMM@ 4DIMM@ 4DIMM@ 4DIMM@

SB_CLK_DDR3
SB_CLK_DDR#3

1
SB_CLK_DDR3 6
SB_CLK_DDR#3 6
2

DDR_B_BS1
DDR_B_RAS#
DDRB_CS2_DIMMB#
SB_ODT2

DDRB_CS2_DIMMB#
SB_ODT2 6

SB_ODT3

SB_ODT3 6

1

2

1

2

1

2

2

6

+1.5V

+VREF_CB
DDR_B_D36
DDR_B_D37

4DIMM@ 4DIMM@

DDR_B1_DM4

1

DDR_B_D38
DDR_B_D39

2

DDR_B_D44
DDR_B_D45

1

2

@
1

2

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47

+0.75VS

DDR_B_D52
DDR_B_D53
4DIMM@
DDR_B1_DM6

1

DDR_B_D54
DDR_B_D55

2

DDR_B_D60
DDR_B_D61

4DIMM@
1

2

4DIMM@
1

2

4DIMM@
1

2

C371
1U_0402_6.3V6K

DDR_B_D56
DDR_B_D57

DDR_B1_DM3

DDR_B_D30
DDR_B_D31

6
6

DDR_B_MA[0..15]

DDR_B_D22
DDR_B_D23

C366
1U_0402_6.3V6K

DDR_B_D50
DDR_B_D51

+3VS

DDR_B_D24
DDR_B_D25

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_DQS[0..7]
DDR_B_D[0..63]

DDR_B1_DM2

C375
1U_0402_6.3V6K

2

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D18
DDR_B_D19

DDR_B_D28
DDR_B_D29

DDR_B_D20
DDR_B_D21

C369
1U_0402_6.3V6K

2

1

C365
1U_0402_6.3V6K

2

1

C374
1U_0402_6.3V6K

2

1

C370
1U_0402_6.3V6K

3

C367
1U_0402_6.3V6K

1

DDR_B_D22
DDR_B_D23

6

DDR_B_DQS#[0..7]

C157
10U_0603_6.3V6M

2

C264
330U_D2_2V_Y

DDR_B_DQS#2
DDR_B_DQS2

1

DDR_B_D14
DDR_B_D15

C189
10U_0603_6.3V6M

+

DDR_B_D16
DDR_B_D17

DDR_B0_DM2

DDR_B1_DM1
DIMM_DRAMRST#

C216
10U_0603_6.3V6M

2

1

DDR_B_D10
DDR_B_D11

DDR_B_D20
DDR_B_D21

C317
0.1U_0402_16V4Z

@

DDR_B_D32
DDR_B_D33

All VREF traces should
have 10 mil trace width

DDR_B_D12
DDR_B_D13

C181
10U_0603_6.3V6M

DDR_B_MA13
DDRB_CS1_DIMMB#

DIMM_DRAMRST# 6,11

DDR_B_D14
DDR_B_D15

DDR_B_D6
DDR_B_D7

C209
10U_0603_6.3V6M

DDR_B_WE#
DDR_B_CAS#

DDR_B_DQS#1
DDR_B_DQS1

C311
2.2U_0603_6.3V6K

2

1

C223
10U_0603_6.3V6M

C200
10U_0603_6.3V6M

1

C174
10U_0603_6.3V6M

2

6 DDR_B_WE#
6 DDR_B_CAS#
6 DDRB_CS1_DIMMB#

+1.5V

1

6 DDR_B_BS0

DDR_B_MA10
DDR_B_BS0

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDR_B0_DM1
DIMM_DRAMRST#

DDR_B_DQS#0
DDR_B_DQS0

C228
10U_0603_6.3V6M

2

SB_CLK_DDR0
SB_CLK_DDR#0

6 SB_CLK_DDR0
6 SB_CLK_DDR#0

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D8
DDR_B_D9

DDR_B_D4
DDR_B_D5

C276
10U_0603_6.3V6M

2

1

DDR_B_MA3
DDR_B_MA1

C156
10U_0603_6.3V6M

2

1

C257
10U_0603_6.3V6M

1

C279
10U_0603_6.3V6M

2

C153
10U_0603_6.3V6M

1
2

DDR_B_MA8
DDR_B_MA5

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_B_D12
DDR_B_D13

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C243
1U_0402_6.3V6K

2

1

C191
1U_0402_6.3V6K

2

1

C238
1U_0402_6.3V6K

1

C231
1U_0402_6.3V6K

2

C183
1U_0402_6.3V6K

1

DDR_B_D2
DDR_B_D3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C197
1U_0402_6.3V6K

DDR_B_D26
DDR_B_D27

DDR_B1_DM0

DDR_B_D6
DDR_B_D7

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C199
1U_0402_6.3V6K

DDR_B0_DM3

DDR_B_DQS#0
DDR_B_DQS0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C171
1U_0402_6.3V6K

+1.5V

DDR_B_D0
DDR_B_D1

2

DDR_B_D10
DDR_B_D11

+V_DDR_REFB

DDR_B_D4
DDR_B_D5

1

1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

1

DDR_B_DQS#1
DDR_B_DQS1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2

DDR_B_D8
DDR_B_D9

E

+1.5V

JDIMM4

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1

2

G

6,11,14 RST_GATE

2

DDR_B_D2
DDR_B_D3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2

2

2

1

C85
0.1U_0402_16V4Z

BSS138_NL_SOT23-3

R87
1K_0402_1%

C89
2.2U_0603_6.3V6K

D

S

1
Q10
@

+1.5V

1

DDR_B0_DM0
1

3

+V_DDR_REFB

2

1

DDR_B_D0
DDR_B_D1

1

7 SB_DIMM_VREFDQ

D

+1.5V

JDIMM2

+V_DDR_REFB

2

R106
0_0402_5%
@
1
2

C

+1.5V

R84
1K_0402_1%

M3 support

http://hobi-elektronika.net
B

+1.5V

3

DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

Layout Note:
Place near JDIMM4.203,204

D_CK_SDATA
D_CK_SCLK
+0.75VS

DDR_B1_DM0
DDR_B1_DM1
DDR_B1_DM2
DDR_B1_DM3
DDR_B1_DM4
DDR_B1_DM5
DDR_B1_DM6
DDR_B1_DM7

FOX_AS0A626-U4RN-7F
CONN@



DIMM_2 Reserve H:8mm

DIMM_4 Reverse type H:4mm

Channel B
4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

12

of

60

http://hobi-elektronika.net

A

B

RTCRST close RAM door J1

C

D

E

+RTCCONN

2

PCH_RTCRST#

3 1

PCH_SRTCRST#

D30
DAN202UT106_SC70-3

R561
0_0603_5%
@

1

+RTCVCC

1

20mil

1

SRTCRST close RAM door J2

2

2

2

2

JBATT1

+RTCCONN_R

1
1

1

C502
1U_0603_10V6K

20mil
2

1
2
R338 20K_0402_5%
1
2
R337 20K_0402_5%

+

R644
1K_0402_5%

-

2
2

+RTCVCC
C516
1U_0603_10V6K

+CHGRTC

R568
0_0603_5%
@

1

1

+RTCCONN

1

C761

SUYIN_060003HA002G202ZL
CONN@

0.1U_0402_16V4Z

+RTCVCC
R353 1

2 1M_0402_5%

SM_INTRUDER#

R347 1

2 330K_0402_5%

PCH_INTVRMEN

+3VS

INTVRMEN

*

HΚIntegrated VRM enable

SERIRQ

R403

2

1 10K_0402_5%

PCH_SATALED#

R662

2

1 10K_0402_5%

LΚIntegrated VRM disable
(INTVRMEN should always be pull high.)

U37A

HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature
LOW= Disable (Default internal PD)

*

PCH_RTCRST#

D20

RTCRST#

PCH_SRTCRST#

G22

+3VALW_PCH
2

36

HDA_SDO

HDA_SDOUT_PCH

੡۶൷۟EC

HDA_SDO

*

@ R322
1K_0402_5%
2
1
R320
0_0402_5%
2
1

SRTCRST#

SM_INTRUDER#

K22

INTRUDER#

PCH_INTVRMEN

C17

INTVRMEN

HDA_BITCLK_PCH

N34

HDA_BCLK

HDA_SYNC_PCH

L34

ME debug mode,this signal has a weak internal PD
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]

HDA_SYNC

PCH_SPKR

T10

38

PCH_SPKR

SPKR

HDA_RST_PCH#

K34

HDA_RST#

HDA_SDIN0

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

C38
A38
B37
C37

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4 / LFRAME#

D36

LPC_FRAME#

LDRQ0#
LDRQ1# / GPIO23

E36
K36

SERIRQ

1.5V when smapled high

Prevent back drive issue.

*

HDA_SDOUT_PCH

1.8V when sampled low
Needs to be pulled High for Huron River platfrom

R670
100_0402_1%

1

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

PCH_JTAG_TMS

H7

JTAG_TMS

PCH_JTAG_TDI

K5

JTAG_TDI

PCH_JTAG_TDO

H1

JTAG_TDO

PCH_SPI_CLK_1
1
R697
PCH_SPI_CS0#_1 1
R696

2 PCH_SPI_CLK
0_0402_5%
2 PCH_SPI_CS0#
0_0402_5%

PCH_SPI_MOSI_1 1
R678
PCH_SPI_MISO_1 1
R689

2 PCH_SPI_MOSI
0_0402_5%
2 PCH_SPI_MISO
0_0402_5%

2

2

2

HDA_DOCK_EN# / GPIO33

N32

PCH_JTAG_TCK

PCH_JTAG_TDI
R669
100_0402_1%

R671
100_0402_1%

2

C36

R468
1M_0402_5%

2

1
2

R658
200_0402_5%

1

PCH_JTAG_TMS

1

PCH_JTAG_TDO

2

R659
200_0402_5%

1

2

R660
200_0402_5%

R672
51_0402_5%
2
1

R302 @
0_0402_5%

+3VALW_PCH

1

1

+3VALW_PCH

1

Q20
BSS138_NL_SOT23-3
1HDA_SYNC_PCH
D

38 HDA_RST_AUDIO#
38 HDA_SDOUT_AUDIO

3
S

38 HDA_SYNC_AUDIO

+3VALW_PCH

2

1

38 HDA_BITCLK_AUDIO
3

G

R677
33_0402_5%
2 HDA_BITCLK_PCH
R676
33_0402_5%
1
2 HDA_SYNC_PCH_R
R673
33_0402_5%
1
2 HDA_RST_PCH#
R665
33_0402_5%
1
2 HDA_SDOUT_PCH

+3VS

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

36
36
36
36

LPC_FRAME# 36

2

SERIRQ

V5

SERIRQ

36

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AM3
AM1
AP7
AP5

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

33
33
33
33

HDD1

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10
AM8
AP11
AP10

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

33
33
33
33

HDD2

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

33
33
33
33

ODD

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7
Y5
AD3
AD1

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

Y3
Y1
AB3
AB1

SATAICOMPO

Y11

SATAICOMPI

Y10

+3VS

R687
10K_0402_5%
PCH_GPIO21
R688 @
10K_0402_5%
+1.05VS_PCH

SATA_COMP

R389
37.4_0402_1%
1
2
R388
49.9_0402_1%
1
2

+1.05VS_PCH

SATA3_COMP

SATA3RCOMPO

AB12

SATA3COMPI

AB13

SATA3RBIAS

AH1

RBIAS_SATA3

P3

PCH_SATALED#

R650

1

R674
4.7K_0402_5%

SATALED#

V4

SPI_MOSI

SATA0GP / GPIO21

V14

PCH_GPIO21

U3

SPI_MISO

SATA1GP / GPIO19

P1

PCH_GPIO19

PCH_SPI_CS0#_1
SPI_WP1#
SPI_HOLD1#

1
3
7
4

PCH_GPIO19

No use PH 10K +3VS

1
R638

2
10M_0402_5%

OSC

4
OSC
NC

1
2

NC

C756

3

18P_0402_50V8J

1

2

Y4

32.768KHZ_12.5PF_Q13MC14610002

4

+3VS

R699 1
R700 1

2 3.3K_0402_5%
2 3.3K_0402_5%

Boot BIOS Strap

+3VS

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

Boot BIOS
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1

MX25L3206EM2I-12G SOP 8P
SA000041P00

SPI ROM FOR ME (4MB)
Footprint 200mil
1

C757
18P_0402_50V8J

Issued Date

*

2010/07/12

GPIO51
0
0
1
1

LPC
Reserved
SPI

2012/07/12

Deciphered Date

SCHEMATIC,MB A6911

Date:

B

C

4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

GPIO19
0
1
0
1

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2

@

Debug Port DG 1.2 PH 4.7K +3VS

GPIO19 has internal Pull up

8
6
5
2

3

+3VS

U40

PCH_RTCX2

GPIO21
0
1

Switchable
* Non SG

2
750_0402_1%

PCH_SATALED# 37

COUGARPOINT_FCBGA989~D

PCH_RTCX1

Switchable Graph
2

On Die PLL VR Select is supplied by

SATA

This signal has a weak internal pull-down

JTAG

1 1K_0402_5% HDA_SYNC_PCH

2

HDA_SDIN0

SPI

R328

38

IHDA

+3VALW_PCH

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1

RTCX2

2

C20

1

RTCX1

PCH_RTCX2

2

PCH_SPKR

2 1K_0402_5%

1

R405 1

LPC

A20

SATA 6G

PCH_RTCX1
@

RTC

+3VS

D

Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

13

of

60

http://hobi-elektronika.net

A

B

C

D

E

+3VALW_PCH

U37B

PERN4
PERP4
PETN4
PETP4

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5
PCIE_PTX_DRX_P5

BG37
BH37
AY36
BB36

PERN5
PERP5
PETN5
PETP5

BJ38
BG38
AU36
AV36

PERN6
PERP6
PETN6
PETP6

BG40
BJ40
AY40
BB40

PERN7
PERP7
PETN7
PETP7

BE38
BC38
AW38
AY38

PERN8
PERP8
PETN8
PETP8

C438
C444

1
1

Y40
Y39
2

PCH_GPIO73

No use PH 10K +3VALW

MINI1_CLKREQ#

34 MINI1_CLKREQ#

No use PH 10K +3VS

No use PH 10K +3VS

USB30_CLKREQ#

35 USB30_CLKREQ#

34 CLK_PCIE_LAN#
34 CLK_PCIE_LAN

PCIE LAN
No use PH 10K +3VALW

LAN_CLKREQ#

34 LAN_CLKREQ#

No use PH 10K +3VALW
USB3.0 On Board
No use PH 10K +3VALW

MINI2_CLKREQ#

34 MINI2_CLKREQ#

41 CLK_PCIE_USB30_L#
41 CLK_PCIE_USB30_L
USB30_CLKREQ#_L

41 USB30_CLKREQ#_L

CLKOUT_PCIE3N
CLKOUT_PCIE3P

A8

PEG_CLKREQ#

PCH_GPIO45

No use PH 10K +3VALW

PCH_GPIO46

No use PH 10K +3VALW
5 CLK_CPU_ITP#
5 CLK_CPU_ITP

CLK_CPU_ITP# R667
CLK_CPU_ITP R666

2
2

@
@

1 0_0402_5%
1 0_0402_5%

CLK_BCLK_ITP#
CLK_BCLK_ITP

CLKOUT_PCIE5N
CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

CL_DATA1

T11

CL_RST1#

P10

PCIECLKRQ6# / GPIO45

2.2K_0402_5%

2

2.2K_0402_5%

RST_GATE

R648

1

2

1K_0402_5%

PCH_GPIO74

R647

1

2

10K_0402_5%

PCH_SML1CLK

R375

1

2

2.2K_0402_5%

PCH_SML1DATA

R369

1

2

2.2K_0402_5%

PCH_GPIO47

R683

1

2

10K_0402_5%

PCH_SMBDATA

For DDR
R427
4.7K_0402_5%
1
2

6

+3VS

D_CK_SDATA

1

Q27A
DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

D_CK_SDATA 11,12

R415
4.7K_0402_5%
1
2 +3VS

3

D_CK_SCLK

4

D_CK_SCLK 11,12

Q27B
DMN66D0LDW-7_SOT363-6

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

M10

PCH_GPIO47

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AM12
AM13

CLK_CPU_DPLL#
CLK_CPU_DPLL

CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

+3VS

No use PH 10K +3VALW

AB37
AB38

CLKOUT_DMI_N
CLKOUT_DMI_P

PCH_SML1DATA 6
CLK_CPU_DMI# 5
CLK_CPU_DMI 5

Pull up at EC side.
For VGA,EC
2

CLK_CPU_DPLL# 5
CLK_CPU_DPLL 5

1

Q22A
DMN66D0LDW-7_SOT363-6
PCH_SML1CLK

120MHz for eDP.

CLKIN_DMI_N
CLKIN_DMI_P

BF18
BE18

CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI

R357 1
R358 1

2 10K_0402_5%
2 10K_0402_5%

CLKIN_DMI2_N
CLKIN_DMI2_P

BJ30
BG30

CLKIN_GND1#
CLKIN_GND1

R330 1
R331 1

2 10K_0402_5%
2 10K_0402_5%

G24
E24

CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M

R346 1
R345 1

2 10K_0402_5%
2 10K_0402_5%

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

AK7
AK5

CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA

R387 1
R393 1

2 10K_0402_5%
2 10K_0402_5%

REFCLK14IN

K45

CLK_BUF_ICH_14M

R292 1

2 10K_0402_5%

CLKIN_PCILOOPBACK

H45

CLK_PCI_LPBACK

XTAL25_IN
XTAL25_OUT

V47
V49

XTAL25_IN
XTAL25_OUT

EC_SMB_DA2

EC_SMB_DA2 23,36

3

4

EC_SMB_CK2

EC_SMB_CK2 23,36

Q22B
DMN66D0LDW-7_SOT363-6

+3VS

Pull down 10K ohm
for using internal Clock

UMAO@
DGPU_PRSNT#

DIS@

XCLK_RCOMP

T13

2

1

+3VS

M7

2
1
R293
33_0402_5%

Y47

R610
10K_0402_5%

C421

1

2
22P_0402_50V8J

CLK_PCI_LPBACK

R609
10K_0402_5%

17

3

Reserve for EMI please close to PCH
R289
90.9_0402_1%
1
2

PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P

K12

CL_CLK1

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

V40
V42

AK14
AK13

PH 2.2K +3VALW

CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26

V38
V37

M16

CLKIN_DOT_96N
CLKIN_DOT_96P

L12

E6

EC-PCH SMBUS

PCH_SML1DATA

SML1DATA / GPIO75

1

R664

1

No use PH 10K +3VALW

PCH_SML1CLK

PCIECLKRQ3# / GPIO25

V45
V46

S3 reduse

E14

CLKOUT_PCIE2N
CLKOUT_PCIE2P

Y37
Y36

PCH_GPIO74

R668

PCH_SMBDATA

No use PH 10K +3VALW

G12

SML1CLK / GPIO58

PCIECLKRQ1# / GPIO18

PCIECLKRQ2# / GPIO20

AB42
AB40

22 CLK_PEG_VGA#
22 CLK_PEG_VGA

CLKOUT_PCIE1N
CLKOUT_PCIE1P

RST_GATE 6,11,12

S3 reduse

C13

PEG_A_CLKRQ# / GPIO47

PCIECLKRQ0# / GPIO73

RST_GATE

C8

SML1ALERT# / PCHHOT# / GPIO74

CLKOUT_PCIE0N
CLKOUT_PCIE0P

V10

Y43
Y45

34 CLK_PCIE_MINI2#
34 CLK_PCIE_MINI2

Mini Card 2

M1
AA48
AA47

35 CLK_PCIE_USB30#
35 CLK_PCIE_USB30

USB3.0/B

3

AB49
AB47

34 CLK_PCIE_MINI1#
34 CLK_PCIE_MINI1

Mini Card 1

J2

SML0DATA

A12

DDR,WLAN,XDPSMBUS
PH 2.2K +3VALW

PCH_SMBDATA 5,34

1

BF36
BE36
AY34
BB34

1
1

SML0CLK

PCH_SMBCLK

EC LID SW OUT

EC_LID_OUT# 36

PCH_SMBCLK 5,34

2

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

SML0ALERT# / GPIO60

10K_0402_5%

2

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCH_SMBDATA

2

1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

C9

1

5

1
1

PCH_SMBCLK

R383

5

C451
C469

H14

EC_LID_OUT#

2

PERN3
PERP3
PETN3
PETP3

2 .1U_0402_16V7K
2 .1U_0402_16V7K

E12

SMBCLK
SMBDATA

SMBUS

BG36
BJ36
AV34
AU34

1
1

SMBALERT# / GPIO11

EC_LID_OUT#

2

USB3.0 Left

PERN2
PERP2
PETN2
PETP2

C573
C572

C464
C472

41 PCIE_PRX_DTX_N5
41 PCIE_PRX_DTX_P5
41 PCIE_PTX_C_DRX_N5
41 PCIE_PTX_C_DRX_P5

BE34
BF34
BB32
AY32

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

Link

35 PCIE_PRX_DTX_N4
35 PCIE_PRX_DTX_P4
35 PCIE_PTX_C_DRX_N4
35 PCIE_PTX_C_DRX_P4

USB3.0 Right

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PERN1
PERP1
PETN1
PETP1

Controller

34 PCIE_PRX_DTX_N3
34 PCIE_PRX_DTX_P3
34 PCIE_PTX_C_DRX_N3
34 PCIE_PTX_C_DRX_P3

Mini Card 2

1
1

BG34
BJ34
AV32
AU32

XCLK_RCOMP

+1.05VS_VTT

GPIO67
DGPU_PRSNT#

FLEX CLOCKS

34 PCIE_PRX_DTX_N2
34 PCIE_PRX_DTX_P2
34 PCIE_PTX_C_DRX_N2
34 PCIE_PTX_C_DRX_P2

Mini Card 1

1

C11
C12

No use PH 10K +3VALW

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

CLOCKS

PCIE LAN

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

PCI-E*

34
34
34
34

CLKOUTFLEX0 / GPIO64

K43

VGA_CLK_27M 23

CLKOUTFLEX1 / GPIO65

F47

CLK_SD_48M 35

CLKOUTFLEX2 / GPIO66

H47

CLK_FLEX2

CLKOUTFLEX3 / GPIO67

K49

DGPU_PRSNT#

@

T21

For Granville GPU need 27Mhz 3.3V nonSSC
change to 14Mhz

DIS,Muxless
UMA

For Cardreader 48Mhz

0
1

PAD

XTAL25_IN

COUGARPOINT_FCBGA989~D
XTAL25_OUT

+3VALW_PCH

1
R611

+3VS

2
1M_0402_5%

1

Y3
R401
10K_0402_5%

UMAO@

PEG_CLKREQ#

1

23 PEG_CLKREQ#

2

4

2

1 10K_0402_5%

MINI1_CLKREQ#

R686

2

1 10K_0402_5%

USB30_CLKREQ#

R652

2

1 10K_0402_5%

PCH_GPIO73

R399

2

1 10K_0402_5%

LAN_CLKREQ#

R684

2

1 10K_0402_5%

MINI2_CLKREQ#

R410

2

1 10K_0402_5%

USB30_CLKREQ#_L

R400

2

1 10K_0402_5%

PCH_GPIO45

R414

2

1 10K_0402_5%

PCH_GPIO46

2

+3VALW_PCH

DIS@
2

R396
10K_0402_5%

R424

C744
27P_0402_50V8J

Issued Date

2010/07/12

2012/07/12

Deciphered Date

B

2

2

4

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

C745
27P_0402_50V8J

Title

Date:

A

25MHZ_20PF_7A25000012 1

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

1

D

Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

14

of

60

http://hobi-elektronika.net

A

B

C

D

E

U37C

R378

2

1 10K_0402_5%

SUS_PWR_DN_ACK

R341

2

1 200K_0402_5%

PCH_ACIN

R402

2

1 10K_0402_5%

PCH_GPIO72

R649

2

1 10K_0402_5%

RI#

2

1 200_0402_5%

PM_DRAM_PWRGD

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BC24
BE20
BG18
BG20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

4
4
4
4

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

4
4
4
4

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

4
4
4
4

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

FDI_FSYNC1

+1.05VS_PCH

+3VS
R373
R634

2

1 10K_0402_5%

DMI_IRCOMP
2
49.9_0402_1%
DMI2RBIAS
2
750_0402_1%

1
R625
1
R632

BH21

FDI

1

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

+3VALW_PCH

4
4
4
4

DMI2RBIAS

PCH_RSMRST#

not support Deep S4,S5 mux
with SUS_PWR_DN_ACK

SUS_PWR_DN_ACK
R372
5 XDP_DBRESET#

R661

1

2 SUSACK#_R
0_0402_5%

1

2 XDP_DBRESET#_R
0_0402_5%
SYS_PWROK

not support AMT APWROK can mux
with PWROK (check list1.0 P.40)

PCH_PWROK

2 PCH_PWROK_R
0_0402_5%

1
R382

C12
K3
P12
L22

System Power Management

4mil width and place
within 500mil of the PCH

SUSACK#
SYS_RESET#
SYS_PWROK
PWROK

2

5 PM_DRAM_PWRGD
36 PCH_RSMRST#

36 SUS_PWR_DN_ACK

APWROK

PM_DRAM_PWRGD

B13

DRAMPWROK

PCH_RSMRST#

C21

RSMRST#

SUS_PWR_DN_ACK

K16
E20

PWRBTN#

PBTN_OUT#

5,36 PBTN_OUT#
36,40,43

L10

ACIN

D19

1

PCH_ACIN
2
RB751V-40_SOD323-2

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

4
4
4
4
4
4
4
4

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

4
4
4
4
4
4
4
4

FDI_INT

AW16

FDI_INT

FDI_FSYNC0

AV12

FDI_FSYNC0

BC10

FDI_FSYNC1

FDI_LSYNC0

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

DSWVRMEN

A18

DSWODVREN

DPWROK

E22

PCH_RSMRST#

B9

PCH_PCIE_WAKE#

N3

PCH_GPIO32

WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62

G8

SUS_STAT#
SUSCLK

D10

PM_SLP_S5#

SLP_S4#

H4

PM_SLP_S4#

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

F4

PM_SLP_S3#

SLP_A#

G10

SLP_A#

SLP_S5# / GPIO63

H20

ACPRESENT / GPIO31

SLP_SUS#

G16

BATLOW# / GPIO72

PMSYNCH

AP14

H_PM_SYNC

K14

PCH_GPIO29

No use PH 10K +3VALW

PCH_GPIO72

E10

Ring Indicator CRB1.0 PH 10K +3VALW

RI#

A10

RI#

SLP_LAN# / GPIO29

+RTCVCC

FDI_INT 4

FDI_LSYNC1

N14

1

FDI_FSYNC0

4

FDI_FSYNC1

4

FDI_LSYNC0

4

FDI_LSYNC1

4

DSWODVREN

*

R361

2

R360

2

1 330K_0402_5%
@

1 330K_0402_5%

DSWODVREN - On Die DSW VR Enable
HΚEnable internal DSW +1.05VS
LΚDisable
Must always PH at +RTCVCC

not support Deep S4,S5 DPWROK mux with PWROK
check list1.0 P.42
PCH_PCIE_WAKE# 34,35,41
+3VALW_PCH

No use PH 10K +3VS
T15
@

PCH_PCIE_WAKE#
R656

1

2 10K_0402_5%

PCH_GPIO29

1

2 10K_0402_5%

PAD
R395

SUSCLK 36
PCH_GPIO32

PM_SLP_S5# 36
PM_SLP_S4# 36
PM_SLP_S3# 36
T51
@

PAD

2

+3VS
R653

1

2 8.2K_0402_5%

Can be left NC
when IAMT is not
support on the
platfrom
not support
Deep S4,S5 can NC
PCH EDS1.2 P.74

H_PM_SYNC 5

No use PH 10K +3VALW

COUGARPOINT_FCBGA989~D

+3VS

1

5
Y

A

SYS_PWROK

SYS_PWROK 5

3

MC74VHC1G08DFT2G_SC70-5

R681
10K_0402_5%

2

R680
10K_0402_5%

4

1

VGATE

1

36,52

3

ALL power OK

2

36 PCH_PWROK

P

U38
2 B

G

tell PCH all power ok
but cpu core

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

15

of

60

A

UMA Panel Backlight ON/OFF
ENBKL

R612

2

1 0_0402_5%
UMA@

IGPU_BKLT_EN

U37D

+3VS

IGPU_BKLT_EN

UMA LVDS DDC
R259

1

R260

1

UMA@
UMA@

2 2.2K_0402_5%

CTRL_CLK

2 2.2K_0402_5%

CTRL_DATA

R269

1
1

UMA@
UMA@

2 2.2K_0402_5%

PCH_CRT_CLK

2 2.2K_0402_5%

PCH_CRT_DATA

1

R607

1

R608

2

1

UMA@
UMA@
UMA@

2 150_0402_1%

PCH_CRT_B

2 150_0402_1%

PCH_CRT_G

2 150_0402_1%

PCH_CRT_R

J47
M45

L_BKLTEN
L_VDD_EN

30

DPST_PWM

P45

L_BKLTCTL

30 PCH_LCD_CLK
30 PCH_LCD_DATA

T40
K47

L_DDC_CLK
L_DDC_DATA

CTRL_CLK
CTRL_DATA

R285

2.37K_0402_1%
2
1
UMA@

R286

0_0402_5%
2
1
UMA@

30 PCH_TXCLK30 PCH_TXCLK+

UMA CRT RGB
R606

PCH_ENVDD

DIS only can NC

UMA CRT DDC
R268

30

30 PCH_TXOUT030 PCH_TXOUT130 PCH_TXOUT230 PCH_TXOUT0+
30 PCH_TXOUT1+
30 PCH_TXOUT2+

Check list1.0 P.55 disable Graphics
ALL Can NC
but DAC_IREF still need PD

30 PCH_TZCLK30 PCH_TZCLK+
30 PCH_TZOUT030 PCH_TZOUT130 PCH_TZOUT2-

LVDS disable:
DATA/Clock/Control an NC
VCC_TX_LVDS,VCCA_LVDS PD to GND

30 PCH_TZOUT0+
30 PCH_TZOUT1+
30 PCH_TZOUT2+

CRT disable:
DATA/Clock/Control an NC
VCCADAC connect to +3VS

31 PCH_CRT_B
31 PCH_CRT_G
31 PCH_CRT_R
31 PCH_CRT_CLK
31 PCH_CRT_DATA
31 PCH_CRT_HSYNC
31 PCH_CRT_VSYNC

T45
P39
AF37
AF36

LVD_IBG
LVD_VBG

LVD_VREF

AE48
AE47

LVD_VREFH
LVD_VREFL

PCH_TXCLKPCH_TXCLK+

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

PCH_TZCLKPCH_TZCLK+

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

PCH_TZOUT0PCH_TZOUT1PCH_TZOUT2-

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

PCH_TZOUT0+
PCH_TZOUT1+
PCH_TZOUT2+

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

PCH_CRT_CLK
PCH_CRT_DATA

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

M47
M49

CRT_HSYNC
CRT_VSYNC

T43
T42

DAC_IREF
CRT_IRTN

CRT_IREF

SDVO_STALLN
SDVO_STALLP

AM42
AM40

SDVO_INTN
SDVO_INTP

AP39
AP40

1

SDVO_CTRLDATA strap pull high
at level shift page

P38
M39

SDVO_SCLK
SDVO_SDATA

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

AT49
AT47
AT40

PCH_DPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

SDVO_SCLK 32
SDVO_SDATA 32

PCH_DPB_HPD 32
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

32
32
32
32
32
32
32
32

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

P46
P42

DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD

AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

2

M43
M36

DDPD_CTRLCLK
DDPD_CTRLDATA

1
UMA@
R307
1K_0402_0.5%

AP43
AP45

SDVO_CTRLCLK
SDVO_CTRLDATA

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

3

SDVO_TVCLKINN
SDVO_TVCLKINP

L_CTRL_CLK
L_CTRL_DATA

LVDS_IBG

Digital Display Interface

+3VS

E

Pull high at LVDS conn side.

PD 100K
at EC side

1

D

LVDS

ENBKL

C

CRT

23,36

http://hobi-elektronika.net
B

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

3

2

COUGARPOINT_FCBGA989~D

DIS only sku can use 1K_0402_5% to GND

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

16

of

60

http://hobi-elektronika.net

A

B

C

‫אױ‬լ‫ش‬PH,‫ڕ‬೚GPIOࠌ‫ش‬PH+3VS

PCH_GPIO55
PCH_GPIO53
PCH_GPIO52
PCH_GPIO5

1
2
3
4

8.2K_1206_8P4R_5%
R256
PCH_GPIO51
PCH_GPIO2
ODD_DA#
PCH_GPIO4

1
2
3
4

B21
M20
AY16
BG46

TP21
TP22
TP23
TP24

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

8.2K_1206_8P4R_5%
1
R267

@

DGPU_PWR_EN
2
10K_0402_5%

DGPU_HOLD_RST#
2
8.2K_0402_5%

1
R310

2

Boot BIOS Strap
GPIO19 GPIO51 Boot BIOS
Bit11 Bit10 Destination
0

1
0

PCI

1

1

SPI

0

0

LPC

*

PCI Interrupt Requests

‫ໍ׽‬GPIOऱ‫פ‬౨޲‫ڶ‬strap function
լ೚GPIO૞PH +3VS,‫ڕ‬೚GPIO PH +3VS
Only GPIO
function

23,29,40,50,51 DGPU_PWR_EN

‫ໍ׽‬GPIOऱ‫פ‬౨޲‫ڶ‬strap function
ྤႊPH(Internal PH),‫ڕ‬೚GPIO PH +3VS

33

K40
K38
H38
G38

PIRQA#
PIRQB#
PIRQC#
PIRQD#

DGPU_HOLD_RST#
PCH_GPIO52
DGPU_PWR_EN

C46
C44
E40

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

PCH_GPIO51
PCH_GPIO53
PCH_GPIO55

D47
E42
F46

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5

ODD_DA#

PAD

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

T13 @

3

5,34,35,36,41 PLT_RST#
CLK_PCI_LPBACK
CLK_PCI_LPC

14 CLK_PCI_LPBACK
36 CLK_PCI_LPC

R604
R316

2
1

PLT_RST#

1 22_0402_5%
2 22_0402_5%
T20 @
T7 @
T8 @

PAD
PAD
PAD

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

G42
G40
C42
D44

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

K10

PME#

C6
H49
H43
J48
K42
H40

NV_DQS0
NV_DQS1

AT10
BC8

NV_ALE
NV_CLE
NV_RCOMP

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AY1

NV_RB#

AT8
AY5
BA2

NV_WE#_CK0
NV_WE#_CK1

1

DF_TVS

DMI,FDI Termination Voltage

AV10

NV_RE#_WRB0
NV_RE#_WRB1

Set to Vcc when HIGH

DF_TVS

Set to Vss when LOW

DG1.2 CRB1.0 PH 2.2K series 1K
For 2012 support

AT12
BF3

+1.8VS
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4

USBRBIAS#

C33

USBRBIAS

USBRBIAS

B33

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

A14
K20
B17
C16
L16
A16
D14
C14

Reserved

1

AY7
AV7
AU3
BG4

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

USB

8
7
6
5

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4

35
35
41
41
35
35
35
35
30
30

USB2/B (Right side)
1

R276
8
7
6
5

PCI

1

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

USB2/B (Right side)

2

R651
2.2K_0402_5%

USB Port (Left side)
USB3/B (right side)

2

8.2K_1206_8P4R_5%

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

NVRAM

PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#

1
2
3
4

RSVD

R262
8
7
6
5

Internal
PH

E

U37E

+3VS

GNT1#/
GPIO51

D

DF_TVS

EHCI 1

3D Panel

R654

2

1
1K_0402_5%

H_SNB_IVB# 5

CLOSE TO THE BRANCHING POINT

Some PCH config not support USB port 6 & 7.
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11

USB20_N8 34
USB20_P8 34
USB20_N9 34
USB20_P9 34
USB20_N10 30
USB20_P10 30
USB20_N11 35
USB20_P11 35

Mini Card (WLAN)
+3VALW_PCH

Mini Card (WWAN)
CMOS Camera (LVDS)

USB20_N13 35
USB20_P13 35

2
R384

1
10K_0402_5%

USB_OC7#

2
R374
2
R379

1
10K_0402_5%
1
10K_0402_5%

EHCI 2

Card Reader
Mini Card (SIM card)

USB20_N13
USB20_P13

USB_OC0#

USB_OC5#

Bluetooth

+3VALW_PCH

Within 500 mils
1
R620

2
22.6_0402_1%

R386
USB_OC1#
USB_OC4#
USB_OC3#
USB_OC6#

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

4
3
2
1

5
6
7
8

3

10K_1206_8P4R_5%
USB_OC2# 41

COUGARPOINT_FCBGA989~D

R371
0_0402_5%
2
1
@

P
Y

4

PLT_RST_BUF# 34
1

A

R376
100K_0402_5%

PLTRST_VGA# 22

R365
100K_0402_5%
DIS@

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MC74VHC1G08DFT2G_SC70-5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1

G

A

4

3

1
DIS@

Y

4

R364
100_0402_5%
1
2
DIS@

P

U24
2 B
DGPU_HOLD_RST#

5

MC74VHC1G08DFT2G_SC70-5
+3VS

4

2

3

1

G

PLT_RST#

5

+3VS

U26
2 B

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

17

of

60

http://hobi-elektronika.net
D

Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
No use PD to GND Check list1.0 P.70

2

1

2 10K_0402_5%

R413

2

1 200K_0402_5% ODD_DETECT#

R370

2

1 200K_0402_5% WWAN_OFF#

+3VS

1

TACH4 / GPIO68

C40

ODD_EN#

A42

TACH1 / GPIO1

TACH5 / GPIO69

B41

PCH_GPIO69

DGPU_HPD_INT#

H36

TACH2 / GPIO6

TACH6 / GPIO70

C41

PCH_GPIO70

+3VS

EC_SCI#

E38

TACH3 / GPIO7

TACH7 / GPIO71

A40

PCH_GPIO71

2

36

EC_SMI#

EC_SMI#

C10

GPIO8

2 0_0402_5%

1

C4

LAN_PHY_PWR_CTRL / GPIO12

SMIB

G2

GPIO15

DGPU_PWROK

U2
D40

A20GATE

SATA4GP / GPIO16
TACH0 / GPIO17

No use PH 10K +3VS

PCH_GPIO22

T5

SCLOCK / GPIO22

CRB1.0 PH 10K +3VALW

PCH_GPIO24

E8

GPIO24 / MEM_LED

No use PD 10K to GND

PCH_GPIO27

E16

GPIO27

No use PH 10K +3VALW

PCH_GPIO28

P8

GPIO28

No use PH 10K +3VS BT ON/OFF

BT_ON#

K1

STP_PCI# / GPIO34

PCH_GPIO35

K4

GPIO35

34,35
PAD

No use can NC

BT_ON#
T16 @

Can't PH

33 ODD_DETECT#

ODD_DETECT#

V8

SATA2GP / GPIO36

Can't PH

34 WWAN_OFF#

WWAN_OFF#

M5

SATA3GP / GPIO37

PECI
RCIN#

P4

GATEA20 36

AU16

PCH_PECI_R

P5

EC_KBRST#

PROCPWRGD

AY11

THRMTRIP#

AY10

INIT3_3V#

T14

NC_1

AH8

NC_2

AK11

NC_3

AH10

NC_4

AK10

NC_5

P37

@
1
2
0_0402_5% R248

PCH_THRMTRIP#_R 1
R385

SLOAD / GPIO38
SDATAOUT0 / GPIO39

No use PH 10K +3VS

PCH_GPIO48

V13

SDATAOUT1 / GPIO48

VSS_NCTF_15

BG2

@T38
@
T38

PAD

34
WL_OFF#
SATA5GP&TEMP_ALERT# CRB PH 10K +3VS

WL_OFF#

V3

SATA5GP / GPIO49

VSS_NCTF_16

BG48

@T24
@
T24

PAD

No use PH +3VALW or PD to GND

PCH_GPIO57

D6

GPIO57

VSS_NCTF_17

BH3

@T37
@
T37

PAD

VSS_NCTF_18

BH47

@T19
@
T19

PAD
PAD

PAD

T47 @

A4

VSS_NCTF_1

VSS_NCTF_19

BJ4

@T36
@
T36

PAD

T30 @

A44

VSS_NCTF_2

VSS_NCTF_20

BJ44

T31
@T31
@

PAD

PAD

T28 @

A45

VSS_NCTF_3

VSS_NCTF_21

BJ45

@T29
@
T29

PAD

PAD

T27 @

A46

VSS_NCTF_4

VSS_NCTF_22

BJ46

@T25
@
T25

PAD

PAD

T49 @

A5

VSS_NCTF_5

VSS_NCTF_23

BJ5

@T35
@
T35

PAD

PAD

T46 @

A6

VSS_NCTF_6

VSS_NCTF_24

BJ6

@T34
@
T34

PAD

@T39
@
T39

PAD

R406

1

2 10K_0402_5%

PCH_GPIO0

R614

1

2 10K_0402_5%

WL_EN#

R326

1

2 10K_0402_5%

DGPU_HPD_INT#

R663

1

2 10K_0402_5%

PCH_GPIO16

PAD

T50 @

B3

VSS_NCTF_7

VSS_NCTF_25

C2

R305

1

2 10K_0402_5%

DGPU_PWROK

PAD

T26 @

B47

VSS_NCTF_8

VSS_NCTF_26

C48

R412

1

2 10K_0402_5%

PCH_GPIO22

GPIO38

PAD

T43 @

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

@T40
@
T40

PAD

OPTIMUS_EN#

PAD

T17 @

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

@T22
@
T22

PAD

PAD

T44 @

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

@T41
@
T41

PAD

PAD

T23 @

BE49

VSS_NCTF_12

VSS_NCTF_30

E49

PAD

T45 @

BF1

VSS_NCTF_13

VSS_NCTF_31

F1

@T42
@
T42

PAD

PAD

T18 @

BF49

VSS_NCTF_14

VSS_NCTF_32

F49

R428

1

2 10K_0402_5%

PCH_GPIO39

R675

1

2 10K_0402_5%

BT_ON#

R679

1

2 10K_0402_5%

PCH_GPIO48

R404

1

2 10K_0402_5%

WL_OFF#

R430

*

1

2 10K_0402_5%

Muxless
nonMuxless

0
1

+3VS

EC_KBRST#

N2

OPTIMUS_EN#

130c shut sown

Checklist1.0 P.59

2 10K_0402_5%

1

3

COUGARPOINT_FCBGA989~D

+3VALW_PCH
R398

1

2 10K_0402_5%

PCH_GPIO24

R657

1

2 10K_0402_5%

PCH_GPIO12

R391

1

2 1K_0402_5%

SMIB

R397

1

2 10K_0402_5%

PCH_GPIO57

GPIO24 Unmultiplexed
NOTE: GPIO24 configuration
register bits are not cleared by
CF9h reset event.
CRB1.0 PH10K to +3VALW
4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

R420

2

TS_VSS1~4
PD to GND

M3

MUXL@

non CPU power ok
H_THRMTRIP# 5

This signal has weak internal
PU, can't pull low,leave NC

PCH_GPIO39

NOMUXL@
2 10K_0402_5%

CTRL+ALT+DEL
5

H_THRMTRIP#
2
390_0402_5%

INIT3_3V

No use PH 10K +3VS

1

PECI CPU-EC

5,36

H_CPUPWRGD

No use PH 10K +3VS Optimus(L)/ non optimus(H)

R429

H_PECI

EC_KBRST# 36

OPTIMUS_EN#

+3VS

1

R419
10K_0402_5%

PCH_GPIO12

PCH_GPIO16
R304

ODD_EN# 33

EC_SCI#

35,41 SMIB

29,49 VGA_PWROK

PCH_GPIO27

BMBUSY# / GPIO0

WL_EN#

36

32 DGPU_HPD_INT#

USB3.0 System management
Interrupt signal “SMI#”.
No use PH +3VS

SATA2GP/GPIO36 & SATA3GP/GPIO37
Sampled at Rising edge of PWROK.
Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled

4

No use PH 10K +3VS

WL_EN#

No use PH +3VALW

+3VS

3

R621
10K_0402_5%

GPIO69 GPIO70 GPIO71
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
1
1
1

1

Debug Port DG 1.2 PH 4.7K +3VALW_PCH

35

CPU/MISC

1

No use PH 10K +3VS

T7

GPIO

2
R417
1K_0402_5%

R362

R619
10K_0402_5%

U37F
PCH_GPIO0

No use PH 10K +3VS

NCTF

2

PCH_GPIO28

@

R618
10K_0402_5%

Fan Tachometer Inputs
TACH1~7 only on server
can insted to GPIO

R422
4.7K_0402_5%

@

PCH_GPIO70

1

1

1

@ R617
10K_0402_5%

2

PCH_GPIO69

Project ID
* P7YE0
x
x
x
x
x
x
x
x
x
x
x

2

@ R616
10K_0402_5%

2

PCH_GPIO71

+3VS

1

+3VS

1

ODD_EN#

+3VALW_PCH

@ R615
10K_0402_5%
2

HΚOn-Die PLL voltage regulator enable
LΚOn-Die PLL Voltage Regulator disable

2

R324
10K_0402_5%

This signal has a weak internal pull up

*

+3VS

1

On-Die PLL Voltage Regulator

1

+3VS

GPIO28

E

1

C

2

B

2

A

HDA_SYNC PH(PLL =+1.5VS)

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

18

of

60

http://hobi-elektronika.net

A

B

D

E

Thermal Senser share with VCCADAC power rail
so can't remove this power

PAD-OPEN 4x4m

POWER

U37G

+3VS

1300mA

Place Near AA23

VCCADAC
VSSADAC

U47

1

C419

VCCALVDS

AK36

VSSALVDS

AK37

VCCTX_LVDS[1]

AM37

VCCTX_LVDS[2]

AM38

VCCTX_LVDS[3]

AP36

VCCTX_LVDS[4]

AP37

1mA

60mA

+1.05VS_PCH
2

2

1

2

C492
1U_0402_6.3V6K

Place Near AN16,AN21,AN33
+3VS

VCCIO[16]
VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29
1

Place Near
BH29

2925mA

AN21

1

+VCCAFDI_VRM
@
PAD T14

+1.05VS_VCCAPLL_FDI

AP16
BG6

AU20
C491
1U_0402_6.3V6K

3

2

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

1

C425
0.01U_0402_16V7K
2 UMA@

C412
22U_0805_6.3V6M
2 UMA@

VCC3_3[7]

V34

+1.8VS
L20
0.1UH_MLF1608DR10KT_10%_1608
2
1
UMA@
R280
0_0402_5%
DISO@

0.1uH inductor, 200mA

Place Near V33

1

I/O Buffer Voltage

C449
.1U_0402_16V7K

2

AT16

+VCCAFDI_VRM

Internal PLL and VRM(+1.5VS)

+1.05VS_PCH
VCCDMI[1]

20mA
VCCIO[1]

AT20
1
AB36

DMI buffer logic

C477
1U_0402_6.3V6K

2

place
near AT20

Core Well I/O Buffer

190mA

VCC3_3[3]

VCCVRM[2]
VCCFDIPLL

VCCPNAND[1]

AG16

VCCPNAND[2]

AG17

+1.8VS

1

VCCPNAND[3]

AJ16

VCCPNAND[4]

AJ17

2

VccDFTERM should PH +1.8VS or +3VS
C523
.1U_0402_16V7K

place
near AG16

+3VS

1

HΚOn-Die PLL voltage regulator enable

1

0.01U_0402_16V7K
V33

+1.05VS_PCH
AP17

On-Die PLL Voltage Regulator

+VCCTX_LVDS

PCH Power Rail Table

C749
.1U_0402_16V7K

2

C462
UMA@

+3VS

VCC3_3[6]

VCCVRM[3]

VCCIO[27]

FDI

2

1

C474
1U_0402_6.3V6K

2

1

C486
1U_0402_6.3V6K

1

C496
1U_0402_6.3V6K

2

C543
10U_0805_6.3V6M

1

AN17

1

1 UMA@ 2
R272
0_0805_5%

Place Near AM37

266mA
HVCMOS

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

VCCIO[15]

DMI

HΚOn-Die PLL voltage regulator enable

VCCAPLLEXP

AN16

NAND / SPI

On-Die PLL Voltage Regulator

BJ22

C418
10U_0805_6.3V6M

2

R270
0_0402_5%
DISO@

VCCIO[28]

VCCIO

+VCCAPLLEXP

T33 @

1

C420

+VCCA_LVDS

2
PAD

1

0.01U_0402_16V7K .1U_0402_16V7K
2
2

+3VS

+1.05VS_PCH
AN19

1mA

L23
MBK1608221YZF_2P
2
1

Place Near U48

+VCCADAC

1

2

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

U48

2

2

1

C505
1U_0402_6.3V6K

2

1

C517
1U_0402_6.3V6K

1

C519
1U_0402_6.3V6K

2

1

C754
10U_0805_6.3V6M

PAD-OPEN 4x4m 1

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

CRT

+1.05VS_PCH

1

LVDS

2

VCC CORE

J3 @

1

1

2

J4 @
2
+1.05VS_VTT

C

VCCDMI[2]

20mA

VCCSPI

COUGARPOINT_FCBGA989~D

For SPI control logi

V1
1

2

Near
AU20

Trace 20mil

C770
1U_0402_6.3V6K

Voltage Rail

Voltage

S0 Iccmax
Current(A)

V_PROC_IO

1.05

0.001

Processor I/F

V5REF

5

0.001

PCH Core Well Reference Voltage

V5REF_Sus

5

0.001

Suspend Well Reference Voltag

Vcc3_3

3.3

0.266

I/O Buffer Voltage

VccADAC

3.3

0.001

Display DAC Analog Power. This power is
supplied by the core well.

VccADPLLA

1.05

0.08

Display PLL A power

VccADPLLB

1.05

0.08

Display PLL B power

VccCore

1.05

1.3

Internal Logic Voltage

2

VccDMI

1.05

0.042

DMI Buffer Voltage

VccIO

1.05

2.925

Core Well I/O buffers

VccASW

1.05

1.01

1.05 V Supply for Intel R Management
Engine and Integrated LAN

VccSPI

3.3

0.02

3.3 V Supply for SPI Controller Logic

VccDSW

3.3

0.003

3.3v supply for Deep S4/S5 well

VccpNAND

1.8

0.19

1.8V power supply for DF_TVS

VccRTC

3.3

6 uA

Battery Voltage

VccSus3_3

3.3

0.266

Suspend Well I/O Buffer Voltage

3

+VCCAFDI_VRM
+1.5VS
R394

2

1

0_0603_5%

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec
಻HDA_SYNC PH(PLL =+1.5VS)

4

3.3 / 1.5

0.01

VccVRM

1.8 / 1.5

0.16

High Definition Audio Controller Suspend
Voltage
1.8 V Internal PLL and VRMs (1.8 V for
Desktop)

VccCLKDMI

1.05

0.02

DMI Clock Buffer Voltage

VccSSC

1.05

0.095

Spread Modulators Power Supply

VccDIFFCLKN

1.05

0.055

Differential Clock Buffers Power Supply

VccALVDS

3.3

0.001

VccTX_LVDS

1.8

0.06

Analog power supply for LVDS (Mobile
Only)
Analog power supply for LVDS (Mobile
Only)

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

VccSusHDA

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

19

of

60

http://hobi-elektronika.net
T38

VCC3_3[5]

PAD

T9

@

+VCCSUS1

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

C513
1U_0402_6.3V6K

2

C426
1U_0402_6.3V6K

Near BD47

+1.05VS_VCCA_B_DPL

1

1
+

C750
220U_6.3V_M

2

SGA00001700
220U 2.5V M B2
ESR 35mohm@100Khz

1

2

C429
1U_0402_6.3V6K

2
L49
10UH_LB2012T100MR_20%

3

2

2
C521

+1.05VS_VCCA_A_DPL

2

suppied by internal
1.05V VR Must NC

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

AF17
AF33
AF34
AG34
AG33

Place
near AF33,
AF34,AG34

Near V16

2
C526
PAD

+VCCSST
1
.1U_0402_16V7K

V16

+1.05VM_VCCSUS T17
V19

T10
@

+1.05VS_PCH

BJ8

2

1

2

VCCSUS3_3[8]

T24

VCCSUS3_3[9]

V23

VCCSUS3_3[10]

V24

VCCSUS3_3[6]

P24

VCCIO[34]

T26

Near T24

2

1

2

C495
.1U_0402_16V7K

1

C494
.1U_0402_16V7K

1

+3VALW_PCH

+5VALW

+1.05VS_PCH

+PCH_V5REF_SUS

DCPSUS[4]

+VCCA_USBSUS

VCCSUS3_3[1]

AN24

V5REF

P34

VCCSUS3_3[2]

N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

suppied by internal
1.05V VR Must NC

+3VALW_PCH

+PCH_V5REF_RUN

1

C771
.1U_0402_16V7K

VCC3_3[4]

Place near
AJ2

VCCIO[5]
VCCIO[12]

AH13

VCCIO[13]

AH14

VCCIO[6]

2

+3VS

1

2

AF11

+VCCAFDI_VRM

Place near
AA16,W16

AC17
AD17

2

C471
.1U_0402_16V7K

Place near
T34

Near AH13,AH14,AF13
C533
1U_0402_6.3V6K

@ T48

3

On-Die PLL Voltage Regulator

PAD

HΚOn-Die PLL voltage regulator enable

+VCCAFDI_VRM

VCCIO[4]

1

C522
.1U_0402_16V7K

GPIO28
+VCCSATAPLL

AC16

2

Near P34

AF14
AK1

VCCIO[3]

2

+1.05VS_PCH

1

VCCIO[2]

R321
100_0402_5%

1

Near N20

T34

AJ2

D14
RB751V-40_SOD323-2

C501
1U_0402_6.3V6K

W16

AF13

+5VS

C470
1U_0603_10V6K

AA16

2

+3VS

+3VALW_PCH

2

1

2

0.1U_0603_25V7K
@

VCC3_3[8]

VCCAPLLSATA

95mA

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

+1.05VS_PCH

Near AC16
1

C482
1U_0402_6.3V6K

+1.05VS_PCH

2

DCPSUS[1]
DCPSUS[2]

1mA

T11
PAD

VCC3_3[1]

VCC3_3[2]

80mA
80mA

1

C484

1mA

R334
100_0402_5%

RB751V-40_SOD323-2

Near M26

DCPSST

V_PROC_IO

C497
.1U_0402_16V7K

2

VCCASW[22]

T21

+VCCME_22

R416

2

1 0_0603_5%

VCCASW[23]

V21

+VCCME_23

R421

2

1 0_0603_5%

VCCASW[21]

T19

+VCCME_21

R426

2

1 0_0603_5%

10mAVCCSUSHDA

P32

+VCCSUSHDA

R327

2

1 0_0603_5%

+3VALW_PCH
A22

2

Place
near BJ8

Near T23

2

M26

55mA

VCCIO[10]

1

C490
.1U_0402_16V7K

AN23

VCCVRM[1]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]

1

V5REF_SUS

1mA

VCCVRM[4]

VCCADPLLB

+3VALW_PCH

D16

DCPRTC

VCCADPLLA

Near N26

+RTCVCC

C493
1U_0402_6.3V6K

C541
.1U_0402_16V7K

1

C537
.1U_0402_16V7K

isolation between SSC (AG33)
and DIFFCLKN(AF33,AF34,AG34)
18mil width(DIFFCLKN)
10mil (SSC)

2

C544
4.7U_0603_6.3V6K

1

4

T23

+1.05VS_PCH

1 C467
1U_0402_6.3V6K
2

VCCSUS3_3[7]

1010mA

VCCASW[5]

AA29

BF47

+1.05VS_PCH

Place
near AG33

VCCASW[4]

BD47

1 C476
1U_0402_6.3V6K

Place
2
near AF17

VCCASW[3]

AA26

Y49

+1.05VS_VCCA_B_DPL

1 C524
1U_0402_6.3V6K

AA24

N16

+VCCAFDI_VRM

SF000001580
220U 6.3V H6 OS-CON
ESR 15mohm@100Khz

+1.05VS_PCH

+VCCRTCEXT

1
.1U_0402_16V7K

VCCASW[1]
VCCASW[2]

Near M6

Near BF47

119mA

DCPSUS[3]

AA21

AA27

Near AA19

+1.05VS_VCCA_A_DPL

2

1

C478
1U_0402_6.3V6K

2

1

C518
1U_0402_6.3V6K

1

2

C552
22U_0805_6.3V6M

2

2

1

C547
22U_0805_6.3V6M

1

2

T29

1

+VCCAPLL_CPY_PCH

AA19

1

VCCIO[33]

1

1

+3VS_VCC_CLKF33

C468
1U_0402_6.3V6K

2

2

DCPSUSBYP

1

2

V12

+1.05VS_PCH

+

VCCIO[32]

T27

3mA

+PCH_VCCDSW

+1.05VS_PCH

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
,VCCAPLLSATA

1

P28

1

T32 @

HΚOn-Die PLL voltage regulator enable

C746
220U_6.3V_M

P26

VCCIO[31]

2

T12 @

VCCDMI = 42mA detal waiting for newest spec

2

PAD

On-Die PLL Voltage Regulator

L48
10UH_LB2012T100MR_20%
1
2

VCCIO[30]
VCCDSW3_3

USB

PAD

suppied by internal
1.05V VR must NC

T16

GPIO28

+1.05VS_PCH

N26

2

Near T16

VCC3_3 = 266mA detal waiting for newest spec

+1.05VS_PCH
VCCIO[29]

VCCACLK

PCI/GPIO/LPC

Near T38

AD49

SATA

2

C520
.1U_0402_16V7K

MISC

2
1

POWER

U37J

1

Not support Deep S4,S5
connect to +3VALW

+VCCACLK

E

1

R273
0_0603_5%
2
1
@
+3VALW_PCH

VCCRTC

HDA

+3VS_VCC_CLKF33
1

C440
1U_0402_6.3V6K

1

C465
10U_0805_10V4Z

D

+1.05VS_PCH

+1.05V analog
internal clock PLL
Can NC

CPU

R329
0_0805_5%
2
@
L26
10UH_LB2012T100MR_20%
1
2
1

C

RTC

+3VS

B

Clock and Miscellaneous

A

1

COUGARPOINT_FCBGA989~D

Need +3VALW and 0.1U close PCH

C473
0.1U_0402_16V4Z

4

2

Near P32

Near A22
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

20

of

60

http://hobi-elektronika.net

A

B

C

D

E

U37I

1

U37H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

2

3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

COUGARPOINT_FCBGA989~D

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

1

2

3

4

4

COUGARPOINT_FCBGA989~D

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

21

of

60

http://hobi-elektronika.net

A

4 PEG_GTX_HRX_N[0..15]
4 PEG_GTX_HRX_P[0..15]

B

C

D

GFX PCIE LANE REVERSAL

U30G

U30A

4 PEG_HTX_C_GRX_N[0..15]
4 PEG_HTX_C_GRX_P[0..15]

1

AA38
Y37

PCIE_TX0P
PCIE_TX0N

PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

Y35
W36

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W33
W32

PEG_GTX_HRX_P1
PEG_GTX_HRX_N1

PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2

W38
V37

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33
U32

PEG_GTX_HRX_P2
PEG_GTX_HRX_N2

PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3

V35
U36

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30
U29

PEG_GTX_HRX_P3
PEG_GTX_HRX_N3

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

T33
T32

PEG_GTX_HRX_P4
PEG_GTX_HRX_N4

PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

T30
T29

PEG_GTX_HRX_P5
PEG_GTX_HRX_N5

PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6

R38
P37

PCIE_TX6P
PCIE_TX6N

P33
P32

PEG_GTX_HRX_P6
PEG_GTX_HRX_N6

PCIE_RX6P
PCIE_RX6N

PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7

P35
N36

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

P30
P29

PEG_GTX_HRX_P7
PEG_GTX_HRX_N7

PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_N8

N38
M37

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

N33
N32

PEG_GTX_HRX_P8
PEG_GTX_HRX_N8

PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_N9

M35
L36

PCIE_TX9P
PCIE_TX9N

N30
N29

PEG_GTX_HRX_P9
PEG_GTX_HRX_N9

PCIE_RX9P
PCIE_RX9N

PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10

L38
K37

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

L33
L32

PEG_GTX_HRX_P10
PEG_GTX_HRX_N10

PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11

K35
J36

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

L30
L29

PEG_GTX_HRX_P11
PEG_GTX_HRX_N11

PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12

J38
H37

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

K33
K32

PEG_GTX_HRX_P12
PEG_GTX_HRX_N12

PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13

H35
G36

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

J33
J32

PEG_GTX_HRX_P13
PEG_GTX_HRX_N13

PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14

G38
F37

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

K30
K29

PEG_GTX_HRX_P14
PEG_GTX_HRX_N14

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33
H32

PEG_GTX_HRX_P15
PEG_GTX_HRX_N15

PCI EXPRESS INTERFACE

PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4

2

3

PCIE_RX0P
PCIE_RX0N

VARY_BL
DIGON

AK27
AJ27

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0

Y33
Y32

LCD PWM (pulse width modulated)
output to adjust LCD brightness
Active High ,external PD need

R133
10K_0402_5%
1
2
VGA@
LVDS CONTROL

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0

E

R127
1 VGA@ 2
10K_0402_5%

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AK35
AL36

VGA_TZCLK+
VGA_TZCLK-

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AJ38
AK37

VGA_TZOUT0+
VGA_TZOUT0-

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

VGA_TZOUT1+
VGA_TZOUT1-

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AG38
AH37

VGA_TZOUT2+
VGA_TZOUT2-

TXOUT_U3P
TXOUT_U3N

AF35
AG36

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

VGA_TXCLK+
VGA_TXCLK-

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

VGA_TXOUT0+
VGA_TXOUT0-

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

VGA_TXOUT1+
VGA_TXOUT1-

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

VGA_TXOUT2+
VGA_TXOUT2-

TXOUT_L3P
TXOUT_L3N

AN36
AP37

VGA_PNL_PWM 30
ENVDD
30

Controls panel digital power on/off.
Active High ,external PD need

1

VGA_TZCLK+ 30
VGA_TZCLK- 30
VGA_TZOUT0+ 30
VGA_TZOUT0- 30

Display Port F config

VGA_TZOUT1+ 30
VGA_TZOUT1- 30
VGA_TZOUT2+ 30
VGA_TZOUT2- 30

LVTMDP

eDP
VGA_TXCLK+ 30
VGA_TXCLK- 30
VGA_TXOUT0+ 30
VGA_TXOUT0- 30
VGA_TXOUT1+ 30
VGA_TXOUT1- 30
VGA_TXOUT2+ 30
VGA_TXOUT2- 30

DP3
DP2

Display Port E config

DP1
DP0

2

2160809000A11SEYMOU_FCBGA962
SEYM@

3

CLOCK
AB35
AA36

14 CLK_PEG_VGA
14 CLK_PEG_VGA#

PCIE_REFCLKP
PCIE_REFCLKN

For M96, AH16 is NC
For Boardway,Madison,Park, AH16 must connect to GND
2
1
R141 VGA@ 10K_0402_5%
17 PLTRST_VGA#

AH16
AA30

PWRGOOD

CALIBRATION
PCIE_CALRP

Y30

R153 1 VGA@

2

1.27K_0402_1%

PCIE_CALRN

Y29

R156 1 VGA@

2

2K_0402_1%

+1.0VSDGPU

PERSTB
2160809000A11SEYMOU_FCBGA962
SEYM@

Park XT P/N : SA00003M570 (S IC 216-0774009 A11 PARK XT S3 631P C38)
Madision Pro P/N : SA00003M360 ( S IC 216-0772000 MADISON PRO FCBGA 0FA)
Seymour XT P/N: SA000047H00 (S IC 216-0809000 A11 SEYMOUR XT M2 0FH)
4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Issued Date

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

22

of

60

http://hobi-elektronika.net

A

B

C

D

E

U30B

VSYNC

BIF_GEN2_EN GPIO2
H2SYNC
GPIO8

0
11
0

Internal use only. THIS PAD HAS AN INTERNAL
pad may be left unconnected

NC on Park,
Robson and Seymour

DNI

GPIO21
+3VSDGPU
R122
R94
R501
R95
R96

1 VGA@
1 VGA@
@
1
@
1
@
1

R91
R92
R93
R90

2
2
2
2
2

1 VGA@
@
1
@
1
@
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
2 3K_0402_5%

PD 100K at EC side

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
GPIO_22_ROMCSB

DISO@
DGPU_BKL_EN
1
2
R500
0_0402_5% DISCRETE

ENBKL

ID3-0 Vender

ONLY

SAM

Freq

64*16 800M
128*16 800M
64*16 900M
64*16 900M

GPU_VID0
VDDCI_VID
THM_ALERT#
VGA_EDP_DET

GPU_VID0
VDDCI_VID

30 VGA_EDP_DET
49

GPU_VID1

GPU_VID1

GPIO_22_ROMCSB

External BIOS device
SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!)
X762 ON(1)/OFF(0) inter PD
SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!)
X768
SA0000324G0(S IC D3 64M16 H5TQ1G63DFR-12C FBGA ABO!)X761 Internal Debug
no use can floating
ON(1)/OFF(0)
Stereo Sync
Whistler/Granville(PRO)
no use can NC
P/N
Description
For ATI Cross fire
SA000035720(S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
X7612 no use can NC
SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!)
X766
SA00004GS10(S IC D3 64M16 K4W1G1646G-BC11 FBGA ABO!)
X7614
SA000041S40(S IC D3 64MX16 H5TQ1G63DFR-11C FBGA ABO!)
X7613

AU14
AV13

TX0P_DPC2P
TX0M_DPC2N

AT15
AR14

TX1P_DPC1P
TX1M_DPC1N

AU16
AV15

DPC

DPD

I2C

Reserved

14 PEG_CLKREQ#

JTAG_TRSTB
JTAG_TDI
VGA_CLK_27M_R
JTAG_TMS
JTAG_TDO

PAD T52 @
PAD T53 @

HPD

Park NC pins
VGA_HDMI_DET

32 VGA_HDMI_DET

HPD

AT17
AR16

NC_TXCDP_DPD3P
NC_TXCDM_DPD3N

AU20
AT19

NC_TX3P_DPD2P
NC_TX3M_DPD2N

AT21
AR20

NC_TX4P_DPD1P
NC_TX4M_DPD1N

AU22
AV21

NC_TX5P_DPD0P
NC_TX5M_DPD0N

AT23
AR22

R
RB

AD39
AD37

VGA_CRT_R 31

AE36
AD35

VGA_CRT_G 31

AF37
AE38

VGA_CRT_B 31

GPIO_0
GPIO_1
G
GPIO_2
GB
GPIO_3_SMBDATA
GPIO_4_SMBCLK
B
GPIO_5_AC_BATT
BB
DAC1
GPIO_6
GPIO_7_BLON
HSYNC
GPIO_8_ROMSO
VSYNC
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
RSET
GPIO_12
70mA AVDD
GPIO_13
GPIO_14_HPD2
AVSSQ
GPIO_15_PWRCNTL_0
100mA
GPIO_16
VDD1DI
GPIO_17_THERMAL_INT
VSS1DI
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
R2/NC
GPIO_21_BB_EN
R2B/NC
GPIO_22_ROMCSB
GPIO_23_CLKREQB
G2/NC
JTAG_TRSTB
G2B/NC
JTAG_TDI
JTAG_TCK
B2/NC
JTAG_TMS
B2B/NC
JTAG_TDO
GENERICA
GENERICB
C/NC
GENERICC
Y/NC
GENERICD
COMP/NC
GENERICE_HPD4
DAC2
NC_GENERICF_HPD5
NC_GENERICG_HPD6
H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

AK24

HPD1

+1.8VSDGPU

R495 1 VGA@

2 499_0402_1%

R496 1 VGA@

2 249_0402_1%

1

1

1

1
2
1

JTAG_TRSTB
1 GRAN@ 2
R120
10K_0402_5%
+3VSDGPU

JTAG_TMS
1 GRAN@ 2
R139
10K_0402_5%

+3VSDGPU

1 GRAN@ 2
R143
10K_0402_5%

C163
12P_0402_50V8J

18P_0402_50V8J

AL31

TS_A/NC

AJ32
AJ33

TSVDD
TSVSS

THERMAL

20mA

2

VGA@

1

2

R485
470_0603_5%
GRAN@

5

DGPU_PWR_EN#

40,51

GRAN@

VGA@

1

2

1 VGA@ 1 VGA@ 1
VGA@

AF30
AF31

2

AC32
AD32
AF32

Reserved

10mil
10mil

R2SET/NC

AA29

AM26
AN26

AUX1P
AUX1N

AM27
AL27

DDC2CLK
DDC2DATA

AM19
AL19

AUX2P
AUX2N

AN20
AM20

DDCCLK_AUX3P
DDCDATA_AUX3N

AL30
AM30

NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N

AL29
AM29

DDCCLK_AUX5P
DDCDATA_AUX5N

AN21
AM21

DDC6CLK
DDC6DATA

AJ30
AJ31

NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

AK30
AK29

AUD Strap

AMD ref:120ohm/0.3A

C166
22U_0805_6.3V6M

CRT,HDMI
DDC

1
+1.8VSDGPU
VGA@
BLM18AG121SN1D_0603

2

VGA_CRT_VSYNC
VGA_CRT_HSYNC

R531 1 DISO@ 2 10K_0402_5%
R530 1 DISO@ 2 10K_0402_5%

VGA_HDMI_SDATA
VGA_HDMI_SCLK

R99 1 VGA@
R100 1 VGA@

2 10K_0402_5%
2 10K_0402_5%

VGA_DDC_CLK
VGA_DDC_DATA

R82
R81

1 VGA@
1 VGA@

2 10K_0402_5%
2 10K_0402_5%

R528 1 VGA@
R525 1 VGA@
R522 1 VGA@

2 150_0402_1%
2 150_0402_1%
2 150_0402_1%

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

NC on Whistler

SM010030010
and Seymour
200ma 120ohm@100mhz DCR 0.2

AMD ref:120ohm/0.3A

Granville can NC when no use

Back compatibility(Manhattan)
+VDD2DI
VSS2DI

R146 1 GRAN@ 2 0_0402_5%
R147 1 GRAN@ 2 0_0402_5%

+A2VDD

R521 1 GRAN@ 2 0_0402_5%

+3VSDGPU

+A2VDDQ

R132 1 GRAN@ 2 0_0402_5%
1 GRAN@1 GRAN@1 GRAN@

+1.8VSDGPU

2

1 VGA@ 2
R152
715_0402_1%

DDC1CLK
DDC1DATA

2

In Whistler and Seymour, change to
GENLK_CLK, GENLK_VSYNC for
Global Swap Lock on multiple GPUs

AD29
AC29

AG33

2

1

L9

2
AD30
AD31

2
VGA@

2

HSYN:VSYNC
11: Audio for both DisplayPort and HDMI

VGA_HDMI_SCLK
VGA_HDMI_SDATA

VGA_HDMI_SCLK 32
VGA_HDMI_SDATA 32

+VDD1DI

2

2

Whistler and Seymour
Except A2VSSQ change to TSVSSQ,
others are NC

GPIO8 Serial-ROM output from ROM.
GPIO9 Serial-ROM input to ROM.
GPIO10 Serial-ROM clock to ROM.
GPIO22 erternal BIOS-ROM enable

HDMI

+3VSDGPU
4.7K_0402_5%
4.7K_0402_5%

2 DLVDS@1
2 DLVDS@1

GPIO8,GPIO9,GPIO10 no use can NC
GPIO22
Enable need 3K PH ,no use must NC

R497
R498

VGA_LCD_CLK
VGA_LCD_DATA

GPIO_9_ROMSI

5

GPIO_10_ROMSCK 6
GPIO_22_ROMCSB 1

VGA_DDC_CLK 31
VGA_DDC_DATA 31

3

U2

VGA_LCD_CLK 30
VGA_LCD_DATA 30

NC on Park,
Robson and Seymour
VGA_DDC_CLK
VGA_DDC_DATA

if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
if GPIO22 Low ,GPIO 11-13->CFG[0:2]
Config Primary memory-aperture size
CFG[3:0]
128MB 000
256MB 001 *
64MB 010

CRT

+3VSDGPU

2
R75
2
R74

NC on Park,
Robson and Seymour

@
@

1
0_0402_5%
1
0_0402_5% 2
@

D

Q

2

GPIO_8_ROMSO

C

FLASH ROM

S

7

HOLD

3

W

8

VCC

TYPE 1

VSS

4

M25P10-AVMN6P@
C79
0.1U_0402_16V4Z

2160809000A11SEYMOU_FCBGA962
SEYM@

VGA@
C160
0.1U_0402_16V4Z

C592

10mil

+TSVDD

1

C120
1U_0402_6.3V6K

120ohm/0.3A

27MCLK

C119
10U_0603_6.3V6M

2

L8
BLM18AG121SN1D_0603
2
1
VGA@
1
VGA@

Y2

2

TS_FDO

R491
2
1
2
0_0402_5%
1
GRAN@
C580
GRAN@
0.1U_0402_16V4Z
2

1

2

4

AK32

0_0402_5%

Future ASIC call MLPS
OLD ASIC is Fan PWM

24
+1.8VSDGPU

External 27MHZ 3.3V CLK

2 VGA@ 1
R505
1M_0402_5%

DPLUS
DMINUS

@

EC_SMB_DA2 14,36

+3VSDGPU

GRAN@
1
1
C581
GRAN@
.1U_0402_16V7K
10U_0805_6.3V6M
2
2
R479
GRAN@
1
2
24K_0402_1%
Q35B
GRAN@ DMN66D0LDW-7_SOT363-6
Q35A
DMN66D0LDW-7_SOT363-6
GRAN@
C579

VGA_CLK_27M_R

1
@

XTALOUT

AF29
AG29

1

75mA

R499
@

GPU_THERM_D+
GPU_THERM_D-

TESTEN

1 GRAN@ 2
R135 0_0402_5%

14 VGA_CLK_27M

XO_IN2

VGA@

10mil

AC30
AC31

A2VDD/NC

XO_IN

EC_SMB_DA2

+3VSDGPU

10mil

2

A2VSSQ/TSVSSQ

XTALIN
XTALOUT

AW35

+VDD1DI

AD33

125mA

XO_IN2

AC33
AC34

AF33

PLL/CLOCK
DPLL_VDDC

AW34

+AVDD

A2VDDQ/NC

DDC/AUX

AN31

27MCLK
AV33
XTALOUT AU34

XO_IN

R503

0_0402_5%

2

2

2
1
2

1
2

2
1

1
2

2

C132
1U_0402_6.3V6K

2

C133
0.1U_0402_16V4Z

2

C99
10U_0603_6.3V6M

AMD ref:470ohm/1A

20mil

DGPU_PWR_EN

L11
BLM18AG121SN1D_0603
1
+1.8VSDGPU
VGA@

C141
10U_0603_6.3V6M

2

DPLL_PVDD
DPLL_PVSS

VGA@
3

31
31

499_0402_1%

2

C140
0.1U_0402_16V4Z

2

L4
BLM18AG121SN1D_0603
+DPLL_VDDC
2
1
VGA@
1 VGA@ 1 VGA@ 1 VGA@

C103
1U_0402_6.3V6K

C147
0.1U_0402_16V4Z

+1.0VSDGPU

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
X76@

AM32
AN32

1 VGA@

AD34
AE34

AG31
AG32

20mil
+DPLL_PVDD
1 VGA@ 1 VGA@

AMD ref:470ohm/1A

R489
10K_0402_5%

R490
10K_0402_5%

X76@

L2
BLM18AG121SN1D_0603
2
1
VGA@
1
C95
10U_0603_6.3V6M
SM010030010
VGA@
2
200ma 120ohm@100mhz DCR 0.2

X76@
R482
10K_0402_5%

R488
10K_0402_5%

X76@

X76@
R483
10K_0402_5%

R487
10K_0402_5%

X76@

X76@
R481
10K_0402_5%

R480
10K_0402_5%

3

X76@

2mA

17,29,40,50,51

VGA_CRT_HSYNC
VGA_CRT_VSYNC
R154

AB34

VDD2DI/NC
VSS2DI/NC

VREFG

VGA@

+1.8VSDGPU

+1.8VSDGPU

100mA

+VGA_VREF AH13

AC36
AC38

10mil

20mil

2 0.1U_0402_16V4Z

1

EC_SMB_CK2 14,36

NOGRAN@
R492
0_0603_5%

R478
100K_0402_5%
GRAN@

C145
1U_0402_6.3V6K

C596

EC_SMB_CK2

Q42A DMN66D0LDW-7_SOT363-6

AO3419L_SOT23-3
Q36
100mA
3
1

NC on Park,
Robson and Seymour

Not share via for other GND

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

6

4

+3VS

+3VSDGPU

SCL
SDA

2

64*16 800M SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!)
X764
128*16 800M SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!)
X765
64*16 800M SA0000324G0(S IC D3 64M16 H5TQ1G63DFR-12C FBGA ABO!)X763

1

VGA@

1

Q42B DMN66D0LDW-7_SOT363-6

TX2P_DPC0P
TX2M_DPC0N

100mA
HYN
HYN
HYN

VGA@
R526
4.7K_0402_5%

VGA_SMB_DA2

C122
10U_0603_6.3V6M

Size

HPD
49
50

TXCCP_DPC3P
TXCCM_DPC3N

VGA_SMB_CK2

C195
0.1U_0402_16V4Z

0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

SAM
SAM
SAM
HYN

64*16 800M
128*16 800M
64*16 800M

ROM

if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD

Reserved

HYN
HYN
HYN

DGPU_BKL_EN
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

2 VGA@ 1
R504 10K_0402_5%

GPIO7 Controls backlight on/off.
Active High ,need external PD

GPIO6,15,16,20
64*16 900M SA00004GS10(S IC D3 64M16 K4W1G1646G-BC11 FBGA ABO!)
X7611 Voltage control signal
64*16 900M SA000041S40(S IC D3 64MX16 H5TQ1G63DFR-11C FBGA ABO!)
X7610 GPIO6,15 no use can NC
128*16 800M SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!)
X767 Thermal monitor interrupt

SWAPLOCKA
SWAPLOCKB

TX5P_DPB0P
TX5M_DPB0N

AT33
AU32

GENERAL PURPOSE I/O
VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4

GPIO6 voltage control signal ,No use can NC

Critical temperature fault

ID3-0 Vender

* 0000
0001
0010
* 0011
* 0100

800M SA000035720(S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)X769

64*16

AR32
AT31

+3VSDGPU

+3VSDGPU

C158
0.1U_0402_16V4Z

SAM
HYN

Description

TX4P_DPB1P
TX4M_DPB1N

DPB

2
4.7K_0402_5%

+3VSDGPU

VGA@
R523
4.7K_0402_5%

C187
1U_0402_6.3V6K

0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

SAM

P/N

AV31
AU30

C159
1U_0402_6.3V6K

* 0000
0001
* 0010
0011
* 0100

Freq

Size

2

2

AJ26

GPIO5 fast-power reduction:
HW control will casue display disturb
should use SW method control

Seymour XT

AJ21
AK21

Move to
DDCCLK_AUX3P,DDCDATA_AUX3N, AK26

GPIO0 Power-state indicator.
GPIO1 PCIE transmitter deemphasis enable.
GPIO2 Advertises the PCIe 0:2.5G 1:5G
GPIO3,4 SMBus data/CLK

1

16,36

Global Swap Lock on
Multiple GPUs

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4

AR30
AT29

TX3P_DPB2P
TX3M_DPB2N

1 VGA@
R130

ADM1032ARMZ-2REEL_MSOP8

2

001

(GENLK_CLK) PULL-DOWN AND MUST BE 0 V AT RESET. The

RESERVED

TXCBP_DPB3P
TXCBM_DPB3N

5

2

AUD(0)

00: No audio function;
10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software

VGA_HDMI_TXD2+ 32
VGA_HDMI_TXD2- 32

THM_ALERT#

GND

3 1

HSYNC

AT27
AR26

VGA_SMB_DA2

ALERT#

4

Enable external BIOS ROM device (Internal PD)
0: Diable, 1: Enable

AUD[1]

TX2P_DPA0P
TX2M_DPA0N

THERM#

5

BIOS_ROM_EN GPIO22

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
NC_DVPCNTL_0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
NC_DVPDATA_17
NC_DVPDATA_18
NC_DVPDATA_19
NC_DVPDATA_20
NC_DVPDATA_21
NC_DVPDATA_22
NC_DVPDATA_23

D-

4

D

GPIO11

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

VGA_SMB_CK2

7
6

G

GPIO12

CONFIG[0]

NC on Park,
Robson and Seymour
NC on Park, Robson

2

8

SDATA

SCLK

3

2

CONFIG[1]

1

GPIO13,12,11 (config 2,1,0) : (Internal PD)
memory apertures
a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0]
the ROM type.
128 MB 000
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 *
64 MB 010
the primary memory aperture size.

VGA_HDMI_TXD1+ 32
VGA_HDMI_TXD1- 32

D+

2

GPIO13

AU26
AV25

VDD

2

S

CONFIG[2]

PCI Express Transmitter De-emphasis Enable (Internal PD)
0: Tx de-emphasis diabled
1: Tx de-emphasis enabled

TX1P_DPA1P
TX1M_DPA1N

DPA

1

2

GPIO1

VGA_HDMI_TXD0+ 32
VGA_HDMI_TXD0- 32

U9 VGA@

GPU_THERM_D+
2200P_0402_50V7K
1
2 VGA@
C161
GPU_THERM_D-

1

TX_DEEMPH_EN

1

AT25
AR24

1

VGA@

2

GPIO0

Transmitter Power Saving Enable (Internal PD)
0: 50% Tx output swing
1: full Tx output swing

VGA_HDMI_TXC+ 32
VGA_HDMI_TXC- 32

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

0

AU24
AV23

1

GPIO9

TX_PWRS_ENB

1

VGA Disable determines (Internal PD)
0: VGA Controller capacity enabled
1: The device will not be recognized as the system’s VGA controller

TXCAP_DPA3P
TXCAM_DPA3N

6

VGA_DIS

Don't have this strap on
Whistler and Seymour

0

C150
0.1U_0402_16V4Z

VIP Device Strap Enable indicates to the software driver (Internal PD)
V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device

VIP_DEVICE_EN

External VGA Thermal Sensor

+3VSDGPU

1

Setting

Pin Straps description 

1

Strap Name

1

27MHZ_16PF_X5H027000FG1H
VGA@
VGA@
C593
VGA@

4

18P_0402_50V8J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

23

of

60

http://hobi-elektronika.net

R177
R168
R148
R172
R166
R138

1 VGA@
1 VGA@
1 VGA@
1 VGA@
1 VGA@
1 VGA@

L27
2
2 243_0402_1% N12
2 243_0402_1% AG12
243_0402_1%
M12
2
2 243_0402_1% M27
2 243_0402_1% AH12
243_0402_1%

CLKA0
CLKA0#

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

1
2
QSA#[0..7]

M13
K16

CSA1#_0

NC_CKEA0
NC_CKEA1

K21
J20

CKEA0
CKEA1

NC_MEM_CALRN0
MEM_CALRN1
NC_MEM_CALRN2

NC_WEA0B
NC_WEA1B

K26
L15

WEA0#
WEA1#

MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2

NC_MAA0_8
NC_MAA1_8

H23
J19

NC_MVREFDA
NC_MVREFSA

R158
VGA@
100_0402_1%

1

2

QSA#[0..7] 27
+1.5VSDGPU

2009/09/18
change R64 PD change
to +3VSDGPU

R155
VGA@
40.2_0402_1%
ODTA0
ODTA1

27
27

CLKA0
CLKA0#

27
27

CLKA1
CLKA1#

27
27

20mil
MVREFSB

RASA0#
RASA1#

27
27

CASA0#
CASA1#

27
27

CSA0#_0

27

CSA1#_0

27

CKEA0
CKEA1

27
27

WEA0#
WEA1#

27
27

MAA13

27

1

R151
VGA@
100_0402_1%

2

2160809000A11SEYMOU_FCBGA962
SEYM@

MVREFDB Y12
MVREFSB AA12
23

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

MVREFDB
MVREFSB

2

C154
0.1U_0402_16V4Z
VGA@

1

R136
51.1_0402_1%
VGA@

2

1

AD28

TESTEN

AK10
AL10

CLKTESTA
CLKTESTB

CLKB0
CLKB0#

CLKB1
CLKB1B

AD8
AD7

CLKB1
CLKB1#

RASB0B
RASB1B

T10
Y10

RASB0#
RASB1#

CASB0B
CASB1B

W10
AA10

CASB0#
CASB1#

CSB0B_0
CSB0B_1

P10
L10

CSB0#_0

CSB1B_0
CSB1B_1

AD10
AC10

CSB1#_0

CKEB0
CKEB1

U10
AA11

CKEB0
CKEB1

WEB0B
WEB1B

N10
AB11

WEB0#
WEB1#

MAB0_8
MAB1_8

T8
W8

DQMB#[0..7] 28

QSB[0..7]

28

QSB#[0..7] 28

ODTB0
ODTB1

28
28

CLKB0
CLKB0#

28
28

CLKB1
CLKB1#

28
28

RASB0#
RASB1#

28
28

CASB0#
CASB1#

28
28

CSB0#_0

28

CSB1#_0

28

CKEB0
CKEB1

28
28

WEB0#
WEB1#

28
28

MAB13

28

R144 10_0402_5%
1
2
1 VGA@
R150
VGA@

AH11

C142
0.1U_0402_16V4Z
VGA@

2

2
51_0402_5%

VRAM_RST# 27,28

3

R140
VGA@
5.11K_0402_1%

2160809000A11SEYMOU_FCBGA962
SEYM@
R125
51.1_0402_1%
VGA@

M96 use 4.7K to
PD directly.

B_BA[0..2] 28

QSB#[0..7]

ODTB0
ODTB1

DRAM_RST

1

B_BA[0..2]

QSB[0..7]

T7
W7

CLKB0
CLKB0B

MAB[0..12] 28

DQMB#[0..7]

L9
L8

ADBIB0/ODTB0
ADBIB1/ODTB1

TESTEN
R145
5.11K_0402_1%
TESTEN
2
1
VGA@
TEST_MCLK
TEST_YCLK

AG28: VDDCI_SEN feedback path to regulator
no use can NC
AF28:VDDC_SEN feedback path to regulator
no use can NC

In M97, Medison and Park, AF28 is
FB_VDDC, AG28 is FB_VDDCI, AH29 is
FB_GND. GCORE_SEN and FB_GND
should route as differential pair Same
as VDDCI_SEN and FB_GND

C203
VGA@
0.1U_0402_16V4Z

If use M96 upper resistor will
change to 100ohm for
MVREFDA/B and MVREFSA/B

AL31 Manhatann/Vancouver NC
Boardway ADC input(0-1V)
use measure regulator current
or temperature

3

C234
VGA@
0.1U_0402_16V4Z

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

MEMORY INTERFACE B

H27
G27

20mil
MVREFDB

1

L18
L20

ODTA0
ODTA1

27

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

2

+1.5VSDGPU

MVREFDA
MVREFSA

J21
G19

QSA[0..7]

MAB[0..12]

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

1

2

2

C291
0.1U_0402_16V4Z

R171
VGA@
100_0402_1%

MVREFSA

1 VGA@

QSA[0..7]

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

E

DDR2
GDDR5/GDDR3
DDR3

GDDR5

1

2

20mil

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

R157
VGA@
40.2_0402_1%

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

1

2

R175
VGA@
40.2_0402_1%

A34
E30
E26
C20
C16
C12
J11
F8

DQMA#[0..7] 27

2

1

+1.5VSDGPU

C34
D29
D25
E20
E16
E12
J10
D7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

+1.5VSDGPU
DQMA#[0..7]

1

VGA@

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

A_BA[0..2] 27

2

2

2

C295
0.1U_0402_16V4Z

1

A32
C32
D23
E22
C14
A14
E10
D9

A_BA[0..2]

U30D
DDR2
GDDR3/GDDR5
DDR3

MDB[0..63]

MDB[0..63]

2

1

2

20mil
MVREFDA

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

28

1

VGA@
40.2_0402_1%

NC_DQA0_0/DQA_0
NC_MAA0_0/MAA_0
NC_DQA0_1/DQA_1
NC_MAA0_1/MAA_1
NC_DQA0_2/DQA_2
NC_MAA0_2/MAA_2
NC_DQA0_3/DQA_3
NC_MAA0_3/MAA_3
NC_DQA0_4/DQA_4
NC_MAA0_4/MAA_4
NC_DQA0_5/DQA_5
NC_MAA0_5/MAA_5
NC_DQA0_6/DQA_6
NC_MAA0_6/MAA_6
NC_DQA0_7/DQA_7
NC_MAA0_7/MAA_7
NC_DQA0_8/DQA_8
NC_MAA1_0/MAA_8
NC_DQA0_9/DQA_9
NC_MAA1_1/MAA_9
NC_DQA0_10/DQA_10
NC_MAA1_2/MAA_10
NC_DQA0_11/DQA_11
NC_MAA1_3/MAA_11
NC_DQA0_12/DQA_12
NC_MAA1_4/MAA_12
NC_DQA0_13/DQA_13
NC_MAA1_5/MAA_13_BA2
NC_DQA0_14/DQA_14
NC_MAA1_6/MAA_14_BA0
NC_DQA0_15/DQA_15
NC_MAA1_7/MAA_A15_BA1
NC_DQA0_16/DQA_16
NC_DQA0_17/DQA_17
NC_WCKA0_0/DQMA_0
NC_DQA0_18/DQA_18
NC_WCKA0B_0/DQMA_1
NC_DQA0_19/DQA_19
NC_WCKA0_1/DQMA_2
NC_DQA0_20/DQA_20
NC_WCKA0B_1/DQMA_3
NC_DQA0_21/DQA_21
NC_WCKA1_0/DQMA_4
NC_DQA0_22/DQA_22
NC_WCKA1B_0/DQMA_5
NC_DQA0_23/DQA_23
NC_WCKA1_1/DQMA_6
NC_DQA0_24/DQA_24
NC_WCKA1B_1/DQMA_7
NC_DQA0_25/DQA_25
GDDR5/DDR2/GDDR3
NC_DQA0_26/DQA_26 NC_EDCA0_0/QSA_0/RDQSA_0
NC_DQA0_27/DQA_27 NC_EDCA0_1/QSA_1/RDQSA_1
NC_DQA0_28/DQA_28 NC_EDCA0_2/QSA_2/RDQSA_2
NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3
NC_DQA0_30/DQA_30 NC_EDCA1_0/QSA_4/RDQSA_4
NC_DQA0_31/DQA_31 NC_EDCA1_1/QSA_5/RDQSA_5
NC_DQA1_0/DQA_32
NC_EDCA1_2/QSA_6/RDQSA_6
NC_DQA1_1/DQA_33
NC_EDCA1_3/QSA_7/RDQSA_7
NC_DQA1_2/DQA_34
NC_DQA1_3/DQA_35 NC_DDBIA0_0/QSA_0B/WDQSA_0
NC_DQA1_4/DQA_36 NC_DDBIA0_1/QSA_1B/WDQSA_1
NC_DQA1_5/DQA_37 NC_DDBIA0_2/QSA_2B/WDQSA_2
NC_DQA1_6/DQA_38 NC_DDBIA0_3/QSA_3B/WDQSA_3
NC_DQA1_7/DQA_39 NC_DDBIA1_0/QSA_4B/WDQSA_4
NC_DQA1_8/DQA_40 NC_DDBIA1_1/QSA_5B/WDQSA_5
NC_DQA1_9/DQA_41 NC_DDBIA1_2/QSA_6B/WDQSA_6
NC_DQA1_10/DQA_42NC_DDBIA1_3/QSA_7B/WDQSA_7
NC_DQA1_11/DQA_43
NC_DQA1_12/DQA_44
NC_ADBIA0/ODTA0
NC_DQA1_13/DQA_45
NC_ADBIA1/ODTA1
NC_DQA1_14/DQA_46
NC_DQA1_15/DQA_47
NC_CLKA0
NC_DQA1_16/DQA_48
NC_CLKA0B
NC_DQA1_17/DQA_49
NC_DQA1_18/DQA_50
NC_CLKA1
NC_DQA1_19/DQA_51
NC_CLKA1B
NC_DQA1_20/DQA_52
NC_DQA1_21/DQA_53
NC_RASA0B
NC_DQA1_22/DQA_54
NC_RASA1B
NC_DQA1_23/DQA_55
NC_DQA1_24/DQA_56
NC_CASA0B
NC_DQA1_25/DQA_57
NC_CASA1B
NC_DQA1_26/DQA_58
NC_DQA1_27/DQA_59
NC_CSA0B_0
NC_DQA1_28/DQA_60
NC_CSA0B_1
NC_DQA1_29/DQA_61
NC_DQA1_30/DQA_62
NC_CSA1B_0
NC_DQA1_31/DQA_63
NC_CSA1B_1

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

MAA[0..12] 27

2

R170

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

MAA[0..12]

D

1

1

+1.5VSDGPU

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

C

DDR2
GDDR5/GDDR3
DDR3

GDDR5

1

R169
VGA@
100_0402_1%

U30C
DDR2
GDDR3/GDDR5
DDR3

MDA[0..63]

MDA[0..63]

MEMORY INTERFACE A

27

B

2

A

1

2

C186
VGA@
120P_0402_50V8

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2

Seymour is single channel for
memory (channel B only)

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

24

of

60

http://hobi-elektronika.net

A

B

C

D

Seymour/WhistlerΚ
PCIE_VDDR,PCIE_PVDD can combian to PCIE_VDDR

U30E

+1.5VSDGPU

MEM I/O

+BIF_VDDC

+BIF_VDDC

1
+

C604
330U_D2_2V_Y
NOGRAN@

2

2

C591
330U_D2_2V_Y
NOGRAN@

Granville option
SGA00004200
S POLY C 470U 2V M D2
LESR4.5M SX H1.9

2010/04/27
non-BACO design,N27,T27
connect BIF_VDDC to VDDC
For BACO design

BOM option at page59

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
3

(GDDR3/DDR3 1.12V@4A VDDCI)
(GDDR5 1.12V@16A VDDCI)

+VDDCI

SM01000BY00 5000ma 120ohm@100mhz DCR 0.02

160mil

2
1
NOGRAN@
L45
FBMA-L11-201209-121LMA50T_0805
2
1
NOGRAN@
L46
FBMA-L11-201209-121LMA50T_0805

2

2

2

2

2

2

2

VGA@

2

VGA@

1

2

2

+VGA_CORE

Seymour/Whistler

VGA@

1

2

1

C703
10U_0805_6.3V6M

2

VGA@

1

2

C711
10U_0805_6.3V6M

1

2

C213
1U_0402_6.3V6K

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
C227
1U_0402_6.3V6K

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

+VDDCI

Granville GPU short
Jumper at power side

C697
10U_0805_6.3V6M

1

2

Granville PRO VDDC:47A
Madison PRO VDDC+VDDCI=31.3A
Whistler PRO VDDC+VDDCI=24A
SeymourXT VDDC+VDDCI=14.2A
RobsonXT VDDC+VDDCI=12.9A

SGA20331E10 S POLY C 330U
2V 9mohm H1.9

BIF_VDDC
Park/Madison:Connect to VDDC
Seymour/Whistler:
dGPU operating:VDDC
BACO mode:+1.0V

C241
1U_0402_6.3V6K

2

1

VGA@

2

C168
1U_0402_6.3V6K

2

2

VGA@

+VGA_CORE

C198
1U_0402_6.3V6K

+

1

VGA@

2

1

C169
1U_0402_6.3V6K

2

VGA@

C218
1U_0402_6.3V6K

VGA@

2

1

C236
1U_0402_6.3V6K

1

VGA@

C220
1U_0402_6.3V6K

2

1

C80
10U_0805_6.3V6M

FB_GND

1

VGA@

2

1

C250
1U_0402_6.3V6K

FB_VDDCI

AH29

2

1

VGA@

2

C217
1U_0402_6.3V6K

R142
0_0402_5% @

FB_VDDC

1

VGA@

2

VGA@

C251
0.1U_0402_16V4Z

FB_GND

AF28
AG28

2

1

VGA@

2

C252
1U_0402_6.3V6K

VDDCI_SEN

10mil

C682
10U_0805_6.3V6M

GCORE_SEN

1

VGA@

2

VGA@

C182
1U_0402_6.3V6K

VDDCI_SEN

VOLTAGE
SENESE

2

1

VGA@

2

1

Seymour/Whistler option

Granville VDDCI:4.6A
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
5A VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

1

VGA@

2

VGA@

C260
1U_0402_6.3V6K

120mA

SPVSS

2

1

VGA@

2

1

C261
1U_0402_6.3V6K

SPV10

2

VGA@

1

C263
1U_0402_6.3V6K

AN9
AN10

VGA@

2

GCORE_SEN

50

75mA

2

2

C258
1U_0402_6.3V6K

49

SPV18

2

1

VGA@

C284
1U_0402_6.3V6K

2

1

150mA

AM10

VGA@

1

VGA@

2

C274
1U_0402_6.3V6K

2

+SPV10

VGA@

1

C130
0.1U_0402_16V4Z

470ohm/1A

SM010030010
200ma 120ohm@100mhz DCR 0.2

+SPV_18

MPV18#1
MPV18#2

1
VGA@

1

VGA@

2

VGA@

2

1

C81
10U_0805_6.3V6M

20mil
VGA@

1

C124
1U_0402_6.3V6K

L32
2
1
VGA@
BLM18AG121SN1D_0603

C585
10U_0603_6.3V6M

2

C595
0.1U_0402_16V4Z

2

VGA@ VGA@
1
+1.0VSDGPU
C589
1U_0402_6.3V6K

C587
10U_0603_6.3V6M

2

1

H7
H8

1
VGA@

1

VGA@

2

1

C185
1U_0402_6.3V6K

VGA@

+MPV_18

VGA@

1

C221
1U_0402_6.3V6K

20mil

C299
1U_0402_6.3V6K

PLL

2

C82
10U_0805_6.3V6M

2

10mil
1

NC_VDDRHB
NC_VSSRHB

2

C193
1U_0402_6.3V6K

2

C700
0.1U_0402_16V4Z

2

C695
1U_0402_6.3V6K

2

C705
0.1U_0402_16V4Z

C698
1U_0402_6.3V6K

L34
2
1
BLM18AG121SN1D_0603
VGA@

C710
10U_0603_6.3V6M

SM010030010
200ma 120ohm@100mhz DCR 0.2
+1.8VSDGPU

V12
U12

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

2

3

NC_VDDRHA
NC_VSSRHA

1

+1.0VSDGPU

C219
1U_0402_6.3V6K

L44
2
1
BLM18AG121SN1D_0603
VGA@

M20
M21

220ohm/2A

C290
1U_0402_6.3V6K

+1.8VSDGPU

For M92/M96 only,
Manhattan are NC pin

C633
10U_0805_6.3V6M

SM010030010
200ma 120ohm@100mhz DCR 0.2

1

C83
10U_0805_6.3V6M

470ohm/1A

2

C205
1U_0402_6.3V6K

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

2

C239
1U_0402_6.3V6K

AD12
AF11
AF12
AG11

170mA

C302
1U_0402_6.3V6K

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

C629
1U_0402_6.3V6K

AF13
AF15
AG13
AG15

20mil
+VDDR4_5

60mA

1
+1.8VSDGPU
L40 VGA@
FBMA-L11-201209-221LMA30T_0805

Granville VDDC:47A

C84
10U_0805_6.3V6M

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

2

C204
1U_0402_6.3V6K

AF23
AF24
AG23
AG24

2

C240
1U_0402_6.3V6K

+VDDR3

10mil

2

C271
1U_0402_6.3V6K

2

C177
0.1U_0402_16V4Z

2

C178
1U_0402_6.3V6K

2

C586
10U_0603_6.3V6M

1 VGA@ 1 VGA@ 1 VGA@

C230
1U_0402_6.3V6K

I/O

2

C229
1U_0402_6.3V6K

219mA

2

C86
10U_0805_6.3V6M

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

2

C201
1U_0402_6.3V6K

AF26
AF27
AG26
AG27

2

C237
1U_0402_6.3V6K

20mil
+VDD_CT

2

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C87
10U_0805_6.3V6M

LEVEL
TRANSLATION

POWER

2

VGA@

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

2

C202
1U_0402_6.3V6K

1

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
47A VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
55mA VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

2

C184
1U_0402_6.3V6K

2

VGA@

C173
0.1U_0402_16V4Z

1
L33 VGA@
120ohm/0.3ABLM18AG121SN1D_0603

1

C179
0.1U_0402_16V4Z

2

+1.8VSDGPU

2

VGA@
C164
1U_0402_6.3V6K

2

1

VGA@
C102
10U_0603_6.3V6M

2

2

VGA@
C176
1U_0402_6.3V6K

1

VGA@
C620
10U_0603_6.3V6M

Ref137-12~ remove Bead
+3VSDGPU

1

2

C281
1U_0402_6.3V6K

1

3400mA 2A

+PCIE_VDDR

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C254
1U_0402_6.3V6K

C125
1U_0402_6.3V6K

2

2

2

SM010030010
300ma 120ohm@100mhz DCR 0.3

2

C286
1U_0402_6.3V6K

1
L41 VGA@
BLM18AG121SN1D_0603

2

C350
1U_0402_6.3V6K

2

C307
1U_0402_6.3V6K

2

C339
10U_0805_6.3V6M

120ohm/0.3A

2

C351
10U_0805_6.3V6M

+1.8VSDGPU

2

C355
10U_0805_6.3V6M

C358
10U_0805_6.3V6M

C345
10U_0805_6.3V6M

SM010030010
300ma 120ohm@100mhz DCR 0.3

2

VGA@

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

SM010014520 3000ma 220ohm@100mhz DCR 0.04

40mil

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

C630
1U_0402_6.3V6K

VGA@

2

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

2

C167
1U_0402_6.3V6K

2

C292
1U_0402_6.3V6K

2

C148
1U_0402_6.3V6K

2

C289
1U_0402_6.3V6K

2

C301
1U_0402_6.3V6K

2

C304
1U_0402_6.3V6K

SF000002M00 330U 2.5V ESR 16mohm

2

C211
1U_0402_6.3V6K

2

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
440mA PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

C212
0.1U_0402_16V4Z

2

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

C226
0.1U_0402_16V4Z

2

C175
1U_0402_6.3V6K

2

C188
1U_0402_6.3V6K

2

C353
1U_0402_6.3V6K

2

PCIE

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

VGA@

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1
C273
1U_0402_6.3V6K

1

2

C215
1U_0402_6.3V6K

SF000002080
330U 6.3V H5.9
15mohm

2

C285
1U_0402_6.3V6K

2

C134
1U_0402_6.3V6K

2

C270
1U_0402_6.3V6K

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

+ C718
VGA@

C306
1U_0402_6.3V6K

1
330U_6.3V_R15M

E

VGA@

2

2160809000A11SEYMOU_FCBGA962
SEYM@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

25

of

60

http://hobi-elektronika.net

A

B

U30F

20mil
+DPABCD_VDD18

AN17
AP16
AP17
AW14
AW16

20mil
+DPABCD_VDD18

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

AN24
AP24

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

AP31
AP32

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

AN27
AP27
AP28
AW24
AW26

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

20mil
+DPABCD_VDD18

20mil
+DPABCD_VDD10

1

2

VGA@

2

VGA@

1

2

+1.8VSDGPU

VGA@

*SM01000AX00
550ma 220ohm@100mhz DCR 0.3

AP22
AP23

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

AP25
AP26

+DPABCD_VDD18

AP14
AP15

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AN33
AP33

+DPABCD_VDD10

20mil

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
L5
MBK1608221YZF_2P
2
1
VGA@

220mA

+1.0VSDGPU
2

L37
MBK1608221YZF_2P
2
1
VGA@

1

29
2

2

2

C615
0.1U_0402_16V4Z

PX_EN

PX_EN:
R126
5.11K_0402_1% SBIOS will control VGA power on/off.
BACO@
High :BACO mode enable
LOWLBACO disable

AW18

DPCD_CALR

DPAB_CALR

AW28

AH34
AJ34

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

AU28
AV27

AL33
AM33

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

AV29
AR28

AN34
AP39
AR39
AU37

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

AU18
AV17

DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

AV19
AR18

DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

AM37
AN38

20mil
DP mode:220mA
LVDS mode:240mA

L7
MBK1608221YZF_2P
2
1
VGA@

DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

AL38
AM35

AF34
AG34

C146
0.1U_0402_16V4Z

2

+DPABCD_VDD18

+DPABCD_VDD18

AK33
AK34

AF39
AH39
AK39
AL34
AM34

+DPABCD_VDD18

20mA
+DPABCD_VDD18

+DPEF_VDD18

20mA

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

2

2

10mil

10mil

10mil

10mil
3

20mA

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

1 VGA@ 1 VGA@ 1 VGA@

2

R502
150_0402_1%
2
VGA@

20mA

20mil
+DPEF_VDD10

2

1

20mA

+DPEF_VDD18

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

2

20mA

20mil
+DPEF_VDD10

* SM01000AX00
550ma 220ohm@100mhz DCR 0.3

+1.0VSDGPU

AN29
AP29
AP30
AW30
AW32

20mil
+DPEF_VDD18
1 VGA@ 1 VGA@ 1 VGA@

PX_EN

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

C100
10U_0603_6.3V6M

+1.8VSDGPU

R494
150_0402_1%
2
1
VGA@

DP mode:300mA
LVDS mode:440mA

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

C126
1U_0402_6.3V6K

* SM01000AX00
550ma 220ohm@100mhz DCR 0.3

AN19
AP18
AP19
AW20
AW22

C127
0.1U_0402_16V4Z

1 VGA@ 1 VGA@ 1 VGA@

+DPEF_VDD18

10mil

10mil

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

R508
2

Park/Madison :AL21left NC

1 AM39
VGA@
150_0402_1%

A39
AW1
AW39

DPEF_CALR
2160809000A11SEYMOU_FCBGA962
SEYM@

Seymour/Whistler:
AL21:PX_EN
use to control discreate GPU regulators
for power express BACO mode
Support BACO:
output High3.3V:turn off regulators (BACO mode on)
output Low0V:turn on regulators (BACO mode off)
need PD resistor
No support BACO:
left NC

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2160809000A11SEYMOU_FCBGA962
SEYM@

REF137-13 update

Date:

A

1

20mil

20mil
+DPABCD_VDD10

Manhatann:220mA
Seymour:110mA

L3
MBK1608221YZF_2P
2
1
VGA@

300mA

C97
1U_0402_6.3V6K

AP13
AT13

DP A/B POWER

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

C104
0.1U_0402_16V4Z

20mil
+DPABCD_VDD10

AP20
AP21

1

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

DP C/D POWER

Manhatann:300mA
Seymour:150mA

C113
1U_0402_6.3V6K

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

* SM01000AX00
550ma 220ohm@100mhz DCR 0.3

U30H

C616
1U_0402_6.3V6K

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

E

DPx-VSSR,DPx_PVSS can combian to DP_VSSR
(Manhatann should have individual GND)
where x is A,B,C,D,E,F

C114
10U_0603_6.3V6M

4

GND

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

C607
10U_0603_6.3V6M

3

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

D

Seymour/WhistlerΚ
DPA_VDD10,DPB_VDD10
can combian to DPAB_VDD10
DPC_VDD10,DPD_VDD10
can combian to DPCD_VDD10
DPE_VDD10,DPD_VDD10
can combian to DPEF_VDD10

C92
10U_0603_6.3V6M

2

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

2

1

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

C

DPA_VDD18,DPA_PVDD,DPB_VDD18,DPB_PVDD
can combian to DPAB_VDD18
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD
can combian to DPCD_VDD18
(DPD_VDD18,DPD_PVDD not applicable on Robson/Park)
DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD
can combian to DPEF_VDD18

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

26

of

60

http://hobi-elektronika.net

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA2
QSA0

F3
C7

DQSL
DQSU

DQMA#2
DQMA#0

E7
D3

DML
DMU

QSA#2
QSA#0

G3
B7

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

CLKA0
CLKA0#
CKEA0

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA0_1
CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA3
QSA1

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#3
DQMA#1

E7
D3

DML
DMU

QSA#3
QSA#1

G3
B7

DQSL
DQSU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSDGPU 24

BA0
BA1
BA2

CLKA1
CLKA1#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA4
QSA5

F3
C7

DQSL
DQSU

DQMA#4
DQMA#5

E7
D3

DML
DMU

QSA#4
QSA#5

G3
B7

DQSL
DQSU

ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#

VRAM_RST# T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VREFCA_A4
VREFDA_Q4

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

A_BA0
A_BA1
A_BA2

M2
N8
M3

BA0
BA1
BA2

CLKA1
CLKA1#
CKEA1

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA6
QSA7

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

DML
DMU

QSA#6
QSA#7

G3
B7

DQSL
DQSU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

+1.5VSDGPU

R199
243_0402_1%
128@

+1.5VSDGPU

R563
4.99K_0402_1% 128@

R565
4.99K_0402_1% 128@

VRAM_RST# T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R587
243_0402_1% 128@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

+1.5VSDGPU

+1.5VSDGPU

2

1

R582
4.99K_0402_1% 128@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

R194
4.99K_0402_1% 128@

R235
4.99K_0402_1% 128@

+1.5VSDGPU

R592
4.99K_0402_1% 128@

R559
4.99K_0402_1% 128@
3

+1.5VSDGPU

128@

1

2

C720
128@

1

2

+1.5VSDGPU

C348
128@

1

2

2

2

VREFDA_Q3
R232
C389
4.99K_0402_1%
128@
128@

1

VREFCA_A4

2

R591
4.99K_0402_1%
128@

VREFDA_Q4
1

VREFCA_A3
R193
4.99K_0402_1%
128@

1

VREFDA_Q2

R590
4.99K_0402_1%
128@

15mil

1

C727
128@

2

R558
C707
4.99K_0402_1%
128@
128@

1

2

2

2

C702

1

VREFCA_A2
R560
4.99K_0402_1%
128@

2

C706
128@

2

2

1

15mil

0.1U_0402_16V4Z

2

R557
4.99K_0402_1%
128@

15mil

0.1U_0402_16V4Z

128@

1

15mil

0.1U_0402_16V4Z

C384

15mil

1

1

VREFDA_Q1

1

VREFCA_A1
R236
4.99K_0402_1%
128@

15mil

2

15mil

2

2

2

15mil

0.1U_0402_16V4Z

ODTA1_1

M2
N8
M3

0.1U_0402_16V4Z

R203
56_0402_1%
128@ 2

A_BA0
A_BA1
A_BA2

2

2

R237
4.99K_0402_1% 128@

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CKEA1

24
24
24
24

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

0.1U_0402_16V4Z

R198
0_0402_5%
ODTA1 2 128@ 1
1

B2
D9
G7
K2
K8
N1
N9
R1
R9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

0.1U_0402_16V4Z

ODTA1

R196
56_0402_1%
128@ 2

0.1U_0402_16V4Z

24

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSDGPU

1

ODTA0_1

ODTA0 2 128@ 1
1
0_0402_5%
R197

J1
L1
J9
L9

1

Pull high for Madison and Park...

ODTA0

ZQ/ZQ0

R564
243_0402_1% 128@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

+1.5VSDGPU

24

RESET

L8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

M8
H1

1

1
2

R231
243_0402_1% 128@

3

VRAM_RST# T2

MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8

1

VRAM_RST#

24,28 VRAM_RST#

D7
C3
C8
C2
A7
A2
B8
A3

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

1

QSA#[7..0]

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A3
VREFDA_Q3

2

2

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

+1.5VSDGPU

2

QSA[7..0]

+1.5VSDGPU

E3
F7
F2
F8
H3
H8
G2
H7

1

CSA0#_0
RASA0#
CASA0#
WEA0#

DQMA#[7..0]

24

B2
D9
G7
K2
K8
N1
N9
R1
R9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

ODTA0_1

MAA[13..0]

24

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREFCA
VREFDQ

2

CLKA0
CLKA0#

24
24
24
24
24

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

M8
H1

1

CKEA0

D7
C3
C8
C2
A7
A2
B8
A3

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MDA[0..63]

MDA[0..63]

24

24

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A2
VREFDA_Q2

1

M2
N8
M3

MDA22
MDA19
MDA21
MDA18
MDA23
MDA16
MDA20
MDA17

2

24

A_BA0
A_BA1
A_BA2

E3
F7
F2
F8
H3
H8
G2
H7

1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E

U32

2

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

24
24
24

VREFCA
VREFDQ

2

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

D

U13

1

VREFCA_A1 M8
VREFDA_Q1 H1

C

U33

1

B

U12

1

A

+1.5VSDGPU
+1.5VSDGPU

2

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

2

C726
1U_0402_6.3V6K

2

C736
1U_0402_6.3V6K

2

C730
1U_0402_6.3V6K

2

C731
1U_0402_6.3V6K

1 128@ 1 128@ 1 128@ 1 128@ 1 128@

C390
10U_0603_6.3V6M

2

2

C391
10U_0603_6.3V6M

C729
0.01U_0402_16V7K

2

2

C735
10U_0603_6.3V6M

1
128@

2

2

C734
10U_0603_6.3V6M

2

C728
10U_0603_6.3V6M

1 128@ 2
R586
56_0402_1%

C733
10U_0603_6.3V6M

CLKA1#

C392
10U_0603_6.3V6M

24

C385
10U_0603_6.3V6M

1 128@ 2
R585
56_0402_1%

2

1 128@ 1 128@ 1 128@ 1 128@

1 128@ 1 128@ 1 128@ 1 128@
CLKA1

2

C732
1U_0402_6.3V6K

+1.5VSDGPU

2

+1.5VSDGPU
C737
0.01U_0402_16V7K

4

24

2

C383
1U_0402_6.3V6K

2

C382
1U_0402_6.3V6K

2

C388
1U_0402_6.3V6K

2

C387
1U_0402_6.3V6K

2

2

C386
1U_0402_6.3V6K

1
128@

2

C723
1U_0402_6.3V6K

1 128@ 2
R584
56_0402_1%

2

C724
1U_0402_6.3V6K

2

2

C725
1U_0402_6.3V6K

2

2

C721
1U_0402_6.3V6K

2

C722
1U_0402_6.3V6K

1 128@ 1 128@ 1 128@ 1 128@ 1 128@

C381
1U_0402_6.3V6K

1 128@ 1 128@ 1 128@ 1 128@ 1 128@

C380
1U_0402_6.3V6K

1 128@ 1 128@ 1 128@ 1 128@ 1 128@
C379
1U_0402_6.3V6K

CLKA0#

1 128@ 2
R583
56_0402_1%

C378
1U_0402_6.3V6K

24

CLKA0

C377
1U_0402_6.3V6K

24

C

D

Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

27

of

60

http://hobi-elektronika.net

A

B

U31
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

B_BA0
B_BA1
B_BA2

24

CKEB0

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

BA0
BA1
BA2

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB3
QSB1

F3
C7

DQSL
DQSU

DQMB#3
DQMB#1

E7
D3

DML
DMU

QSB#3
QSB#1

G3
B7

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

CLKB0
CLKB0#

MAB[13..0]

24

ODTB0_1
24
24
24
24

DQMB#[7..0]

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CSB0#_0
RASB0#
CASB0#
WEB0#

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCB_A2 M8
VREFDB_Q2 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB2
QSB0

F3
C7

DQSL
DQSU

DQMB#2
DQMB#0

E7
D3

DML
DMU

QSB#2
QSB#0

G3
B7

DQSL
DQSU

+1.5VSDGPU

VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB4
QSB5

F3
C7

DQSL
DQSU

DQMB#4
DQMB#5

E7
D3

DML
DMU

QSB#4
QSB#5

G3
B7

DQSL
DQSU

VRAM_RST#

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

+1.5VSDGPU

24

+1.5VSDGPU

CKEB1
ODTB1_1

24
24
24
24

CSB1#_0
RASB1#
CASB1#
WEB1#

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VREFCA
VREFDQ

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKB1
CLKB1#
CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

QSB6
QSB7

F3
C7

DQSL
DQSU

DQMB#6
DQMB#7

E7
D3

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB#6
QSB#7

G3
B7

DQSL
DQSU

VRAM_RST#

T2

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

1

+1.5VSDGPU

+1.5VSDGPU

R517
243_0402_1%
VGA@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

+1.5VSDGPU

R542
4.99K_0402_1%

R159
4.99K_0402_1%

VGA@
2

2

VREFDB_Q2

VREFCB_A3

VGA@

2

R518
4.99K_0402_1%
VGA@

VREFDB_Q3

C606

1

VGA@ 2

R538
4.99K_0402_1%
VGA@

C646
VGA@

1

2

R163
4.99K_0402_1%
VGA@

1

2

C

2

VGA@
C618
10U_0603_6.3V6M

2

VGA@

4

Compal Electronics, Inc.
2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

Date:

B

C139
0.1U_0402_16V4Z
VGA@

C138
1U_0402_6.3V6K

1

C621
10U_0603_6.3V6M

C155
10U_0603_6.3V6M

C170
10U_0603_6.3V6M

2

VGA@

2

C137
1U_0402_6.3V6K

1

2

C136
1U_0402_6.3V6K

VGA@

2

C135
1U_0402_6.3V6K

+1.5VSDGPU

C143
1U_0402_6.3V6K

2

C608
1U_0402_6.3V6K

2

C611
1U_0402_6.3V6K

C609
1U_0402_6.3V6K

C612
1U_0402_6.3V6K

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2

2

2

Compal Secret Data
2010/07/12

2

1

2

2

Security Classification

VREFDB_Q4

R124
4.99K_0402_1%
VGA@

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

1

Issued Date

VGA@

1

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
C613
1U_0402_6.3V6K

2

2

C326
1U_0402_6.3V6K

2

2

2

C319
1U_0402_6.3V6K

2

2

C321
1U_0402_6.3V6K

C610
0.01U_0402_16V7K

1 VGA@

2

C253

+1.5VSDGPU

C315
10U_0603_6.3V6M

2

1 VGA@ 1 VGA@ 1 VGA@
C310
10U_0603_6.3V6M

VGA@

+1.5VSDGPU

C675
10U_0603_6.3V6M

1

2

C679
10U_0603_6.3V6M

R516
56_0402_1%
1
2
VGA@
R515
56_0402_1%
1
2
VGA@

2

C330
1U_0402_6.3V6K

2

2

C324
1U_0402_6.3V6K

2

2

3

VGA@

VREFCB_A4

1

1

2

C651

2

2

R535
4.99K_0402_1%
VGA@
2

1

1

1

1
2

VGA@

C687
1U_0402_6.3V6K

2

C686
0.01U_0402_16V7K

R121
4.99K_0402_1%

VGA@

2

VGA@

1

1

1

1

1
2

2
1
2

2

2

C327

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

C688
1U_0402_6.3V6K

VGA@

CLKB1#

VREFCB_A2
R187
4.99K_0402_1%
VGA@

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@

1

CLKB1

VGA@

1

R513
4.99K_0402_1%

+1.5VSDGPU

56_0402_1%
2

C689
1U_0402_6.3V6K

VGA@

C692

VGA@

+1.5VSDGPU

C690
1U_0402_6.3V6K

1

2

VGA@

VREFDB_Q1

R555
4.99K_0402_1%
VGA@

+1.5VSDGPU

C691
1U_0402_6.3V6K

CLKB0#

VGA@

1

+1.5VSDGPU

0.1U_0402_16V4Z

R553 56_0402_1%
2
VGA@
R554

C655

+1.5VSDGPU

0.1U_0402_16V4Z

R539
4.99K_0402_1%
VGA@

+1.5VSDGPU

0.1U_0402_16V4Z

1

1

1

VREFCB_A1
R162
56_0402_1%
2
VGA@

ODTB1_1

CLKB0

VGA@

0.1U_0402_16V4Z

1

VGA@

R541
4.99K_0402_1%

0.1U_0402_16V4Z

ODTB1 R161
VGA@
0_0402_5%

R164
56_0402_1%
2
VGA@

R190
4.99K_0402_1%

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

ODTB1

ODTB0 R165
VGA@
0_0402_5%

1

ODTB0

R556
4.99K_0402_1%

2

3

R536
4.99K_0402_1%

2

+1.5VSDGPU

R160
243_0402_1%
VGA@

1

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

J1
L1
J9
L9

2

1

ZQ/ZQ0

+1.5VSDGPU
ODTB0_1

24

M2
N8
M3

ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

2

RESET

L8

2

2
+1.5VSDGPU

4

B_BA0
B_BA1
B_BA2

+1.5VSDGPU

E3
F7
F2
F8
H3
H8
G2
H7

1

1

VRAM_RST# T2

R186
243_0402_1%
VGA@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSDGPU

Pull high for Madison and Park...

24

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

2

VRAM_RST#

R543
243_0402_1%
VGA@

24

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSDGPU

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

1

QSB#[7..0]

24,27 VRAM_RST#

24

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

2

24

24

VREFCB_A4 M8
VREFDB_Q4 H1

QSB[7..0]

2

24

E

U10

1

24

MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29

2

24

E3
F7
F2
F8
H3
H8
G2
H7

MDB[0..63]

MDB[0..63]

D

U29

1

24

24
24
24

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

C

U11

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

28

of

60

http://hobi-elektronika.net
B

BACO@

2 10K_0402_5%

PX_EN needs to be isolated
during a scan dump

6

1

5
Y

1

A

BACO@

1.5_VDDC_PWREN

49

40,49 1.5_VDDC_PWREN#

MC74VHC1G08DFT2G_SC70-5
1.5_VDDC_PWREN

1 BACO@ 2
R80
0_0402_5%

2

R71
100K_0402_5%
BACO@

DMN66D0LDW-7_SOT363-6
DIS@

1

PX_EN

2

PD 5.11K at VGA side
PX_EN = 1, For BACO Mode
PX_EN = 0, For Normal Mode
PX_EN:
Connect to PWR to shudown
VDDC/VDDCI/VDDR1
(VGA_CORE,+1.5VSDGPU)
High in BACO mode

BACO_EN#=0 (Normal mode)

1

1

6

3

5
P

BACO_EN=1 (Normal mode)

Q38A

5

BACO@

2
1

4

DMN66D0LDW-7_SOT363-6

3

BACO@

BACO_EN#

BACO_EN=0 (BACO mode)

PX_MODE

4

BACO_EN#=1 (BACO mode)
BACO_EN

Q38B
BACO@
Y

A

1K_0402_5%
BACO@

G

1

18,49 VGA_PWROK

R493

1K_0402_5%
BACO@

BACO@
1.5_VDDC_PWREN

1: Normal mode->BACO_EN# High->
BIF_VDDC=+VGA_CORE(N-MOS),VGA_CORE(N-MOS)

2

R509

U28
2 B

BACO_EN/BACO_EN#:
0: BACO Mode->BACO_EN High->
BIF_VDDC=+1.0VSDGPU(N-MOS),VGA_CORE(P-MOS)

+5VS

2

+5VS

+3VS
C588
.1U_0402_16V7K
1
2

2

1

Q8B
DMN66D0LDW-7_SOT363-6
DIS@

5

1

Q8A
26

DIS@

3

1

1.5_VDDC_PWREN#

4

R85

1.5_VDDC_PWREN

G

+3VS

R72
100K_0402_5%

BACO@

4

E

+5VALW

3

17,23,40,50,51 DGPU_PWR_EN

1
2 0_0402_5%
NOBACO@
C88
.1U_0402_16V7K
1
2

P

U3
2 B

D

2

R70
+3VS

C

1

A

DMN66D0LDW-7_SOT363-6

MC74VHC1G08DFT2G_SC70-5

Check Power VGA_CORE off page

Q39
AO3416L_SOT23-3

+1.0VSDGPU_BACO

+BIF_VDDC

1

3
BACO@

BACO@

1

2
G

G

2

+VGA_CORE
NOBACO@
1
2
R506
0_0805_5%

S

1

D

D

S

3
3

Q41
AO3416L_SOT23-3

2

BACO_EN

C597
22U_0805_6.3V6M
BACO@

BACO mode
1
0
0
1
ON
ON
ON
OFF
OFF
+1.0VSDGPU

2

VGA Power Enable Signal Mapping table
Graville
Whistler and Seymour
+3VSDGPU
DGPU_PWR_EN
SUSP#
+1.8VSDGPU
DGPU_PWR_EN
DGPU_PWR_EN
DGPU_PWR_EN
+1.0VSDGPU
DGPU_PWR_EN
+VDDCI
Combine with +VGA_CORE
DGPU_PWR_EN
1.5_VDDC_PWREN
DGPU_PWR_EN
+VGA_CORE
1.5_VDDC_PWREN
DGPU_PWR_EN
+1.5VSDGPU

rdson<140mohm

+1.0VSDGPU

VGA Status Mapping table
Normal mode
0
PX_EN
1.5_VDDC_PWREN
1
BACO_EN#
1
BACO_EN
0
+3VSDGPU
ON
+1.8VSDGPU
ON
+1.0VSDGPU
ON
+VGA_CORE
ON
+1.5VSDGPU
ON
+BIF_VDDC
+VGA_CORE

3

If no support BACO,
need pop R191

Power Sequence of Granville

Power Sequence of Whistler and Seymour
SUSP#

DGPU_PWR_EN

Q37
AO3416L_SOT23-3

+3VSDGPU

1.5_VDDC_PWREN

(BOM option form +3VS)

BACO@
3

1

+3VSDGPU

S

+VGA_CORE_BACO

D

S

+VGA_CORE

BACO@
1

D

3

2
G

G

2

BACO_EN#

DGPU_PWR_EN

Q40
AO3416L_SOT23-3

1.5_VDDC_PWREN

+VGA_CORE

rdson<21mohm
PX_EN = 1, For BACO Mode

+VGA_CORE
+VDDCI

+VDDCI

BACO_EN=0
BACO_EN#=1(5V)==> BIF_VDDC=+1.0VSDGPU
PX_EN = 0, For Normal Mode

+1.5VSDGPU

+1.5VSDGPU

BACO_EN=1(5V) ==> BIF_VDDC=VGA_CORE
BACO_EN#=0
4

+1.0VSDGPU

+1.0VSDGPU

4

For the MOSFETs on the path of delivering
PCIE_VDDC(+1.0VSDGPU) to
BIF_VDDC Rdson of 140 mOhms or less is required.
For the MOSFETs on the path of delivering VGA_CORE to
BIF_VDDC, Rdson of 21 mOhms or less is required.

+1.8VSDGPU

2010/07/12

20ms

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

+1.8VSDGPU

20ms

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

29

of

60

http://hobi-elektronika.net

A

B

100505 change to +3VALW
101029 add +5VALW

D

+3VS

+3VALW

+5VS

1

W=60mils

R14

W=60mils

1

D

3

PCH_ENVDD

PCH_ENVDD

Q31
UMA@
S 2N7002H_SOT23-3

2
G

G
@

5

1

P
+LCDVDD

UMA@
4

Y

DPST_PWM_1

INVTPWM
2
0_0402_5%

1
R6

U1
74AHCT1G125GW_SOT353-5
UMA@
DISO@

W=60mils

36

1
R2

INVT_PWM

2
0_0402_5%
@

1

1

4.7U_0603_6.3V6K
2

2

1
R1

22 VGA_PNL_PWM

C565

2
0_0402_5%

0.1U_0402_16V4Z

R4
10K_0402_5%

TXOUT0+
TXOUT0-

PCH_TXOUT1+
PCH_TXOUT1-

EDP_TXP1
EDP_TXN1

VGA_TXOUT1+
VGA_TXOUT1-

DP1P
DP1N

TXOUT1+
TXOUT1-

PCH_TXOUT2+
PCH_TXOUT2-

EDP_TXP0
EDP_TXN0

VGA_TXOUT2+
VGA_TXOUT2-

DP0P
DP0N

TXOUT2+
TXOUT2-

PCH_TXCLK+
PCH_TXCLK-

VGA_TXCLK+
VGA_TXCLK-

TXCLK+
TXCLK-

PCH_TZOUT0+
PCH_TZOUT0-

VGA_TZOUT0+
VGA_TZOUT0-

TZOUT0+
TZOUT0-

PCH_TZOUT1+
PCH_TZOUT1-

VGA_TZOUT1+
VGA_TZOUT1-

TZOUT1+
TZOUT1-

PCH_TZOUT2+
PCH_TZOUT2-

VGA_TZOUT2+
VGA_TZOUT2-

TZOUT2+
TZOUT2-

VGA_TZCLK+
VGA_TZCLK-

PCH_TZCLK+
PCH_TZCLK-

1
ENVDD

D

2
G

Pull Low at GPU side

3

22

ENVDD

PCH_TZCLK+
PCH_TZCLK-

S

1

TZCLK+
TZCLK-

2

2

R439
100K_0402_5%
UMA@

VBIOS PWM SETTING
CHANGE TO NORMAL

D

0.047U_0402_16V7K
2
C566

A
G

Q53
AO3419L_SOT23-3

3

D

2

DPST_PWM

OE#

3

16

S

ENVDD_R 2

G

1

2

C590
@
4.7U_0805_10V4Z

1

3

C564

1

16

S

S

2

1

2N7002H_SOT23-3

4.7U_0603_6.3V6K

1

R446
1K_0402_5%
2
1 ENVDD_R

2
G

2

3

2

Q33
AO3419L_SOT23-3

1

C563

Panel
Conn.

VGA_TXOUT0+
VGA_TXOUT0-

PCH_TXOUT0+
PCH_TXOUT0-

1

1

Q30

1

R443
10K_0402_5%

1

2

2

R448
10K_0402_5%
@

D
1

100K_0402_5%
1

2

+3VS
R442
300_0603_5%

UMA@

E

UMA/DIS LVDS/eDP Mapping table
UMA
DIS
LVDS
eDP
LVDS
eDP

LCD POWER CIRCUIT

+LCDVDD
+5VALW

C

AUXP
AUXN

EDP_AUXP VGA_LCD_CLK
EDP_AUXN VGA_LCD_DATA

I2CC_SCL
I2CC_SDA

Q32
2N7002H_SOT23-3
DISO@

SM010014520 3000ma 220ohm@100mhz DCR 0.04
SM01000BY00 5000ma 120ohm@100mhz DCR 0.02

UMA ONLY/Muxless
16 PCH_TXOUT0+
16 PCH_TXOUT016 PCH_TXOUT1+
16 PCH_TXOUT116 PCH_TXOUT2+
16 PCH_TXOUT216 PCH_TXCLK+
16 PCH_TXCLK16 PCH_TZOUT0+
16 PCH_TZOUT016 PCH_TZOUT1+
16 PCH_TZOUT116 PCH_TZOUT2+
16 PCH_TZOUT2-

R452 1 ULVDS@2 0_0402_5%
R450 1 ULVDS@2 0_0402_5%

TXOUT0+
TXOUT0-

PCH_TXOUT1+
PCH_TXOUT1-

R455 1 ULVDS@2 0_0402_5%
R453 1 ULVDS@2 0_0402_5%

TXOUT1+
TXOUT1-

1

PCH_TXOUT2+
PCH_TXOUT2-

R456 1 ULVDS@2 0_0402_5%
R454 1 ULVDS@2 0_0402_5%

TXOUT2+
TXOUT2-

PCH_TXCLK+
PCH_TXCLK-

R458 1 ULVDS@2 0_0402_5%
R457 1 ULVDS@2 0_0402_5%

TXCLK+
TXCLK-

PCH_TZOUT0+
PCH_TZOUT0-

R460 1 ULVDS@2 0_0402_5%
R459 1 ULVDS@2 0_0402_5%

TZOUT0+
TZOUT0-

PCH_TZOUT1+
PCH_TZOUT1-

R462 1 ULVDS@2 0_0402_5%
R461 1 ULVDS@2 0_0402_5%

TZOUT1+
TZOUT1-

PCH_TZOUT2+
PCH_TZOUT2-

R465 1 ULVDS@2 0_0402_5%
R463 1 ULVDS@2 0_0402_5%

TZOUT2+
TZOUT2-

PCH_TZCLK+
PCH_TZCLK-

16 PCH_TZCLK+
16 PCH_TZCLK16 PCH_LCD_CLK
16 PCH_LCD_DATA

2

0.1U_0402_16V4Z

2

1

C8
10U_0603_6.3V6M

2

C5

TZCLK+
TZCLK-

PCH_LCD_CLK
R444 1 ULVDS@2 0_0402_5%
PCH_LCD_DATA R445 1 ULVDS@2 0_0402_5%

I2CC_SCL
I2CC_SDA

R440 1 ULVDS@2 4.7K_0402_5%

PCH_LCD_CLK

R441 1 ULVDS@2 4.7K_0402_5%

PCH_LCD_DATA

C2
68P_0402_50V8J

BKOFF#
C6

1

2

1

2

220P_0402_50V7K
+3VS

220P_0402_50V7K

BKOFF#

BKOFF#
10K_0402_5% 2

22 VGA_TXOUT2+
22 VGA_TXOUT222 VGA_TXCLK+
22 VGA_TXCLK-

R39 1

LOCAL_DIM

@

+3VSDGPU

1

C

VGA_TXOUT1+
VGA_TXOUT1-

R23
R17

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

TXOUT1+
TXOUT1-

VGA_TXOUT2+
VGA_TXOUT2-

R24
R22

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

TXOUT2+
TXOUT2-

VGA_TXCLK+
VGA_TXCLK-

R26
R25

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

TXCLK+
TXCLK-

Q34
MMBT3904_G_SOT23-3
DEDP@
23 VGA_EDP_DET

R38 1

36 COLOR_ENG_EN
R449
10K_0402_5%
DEDP@

@

2 0_0402_5%

DEDP@
EDP_HPD

0_0402_5% 1

2 R238

TXOUT1+
TXOUT1-

VGA_TZOUT1+
VGA_TZOUT1-

R30
R29

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

TZOUT1+
TZOUT1-

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

TZOUT2+
TZOUT2-

VGA_TZOUT2+
VGA_TZOUT2-

22 VGA_TZOUT2+
22 VGA_TZOUT222 VGA_TZCLK+
22 VGA_TZCLK-

AUX P 23 VGA_LCD_CLK
N 23 VGA_LCD_DATA

R32
R31

VGA_TZCLK+
VGA_TZCLK-

R34
R33

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

TZCLK+
TZCLK-

VGA_LCD_CLK
VGA_LCD_DATA

R9
R7

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

I2CC_SCL
I2CC_SDA

TXOUT0+
TXOUT0I2CC_SDA
I2CC_SCL

2

TZOUT0+
TZOUT0-

R8
100K_0402_5%

+3VS

DEDP@
1

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

I2CC_SDA
I2CC_SCL

+LCDVDD

17
17

USB20_N4
USB20_P4

0_0402_5% 1
0_0402_5% 1

17
17

USB20_P10
USB20_N10

0_0402_5% 1
0_0402_5% 1

2

22 VGA_TZOUT1+
22 VGA_TZOUT1-

R28
R27

TZOUT0+
TZOUT0COLOR_ENG_EN_R
TXCLK+
TXCLKTXOUT2+
TXOUT2-

R10
100K_0402_5%

DEDP@

2 R250
2 R352
2 R3
2 R5

+5VS
+3VS

USB20_3D_N4
USB20_3D_P4
USB20_CMOS_P10
USB20_CMOS_N10

2

2

6

I/O4

5

REF2 REF1

2

4

I/O3

3

1

I/O1

I/O2

USB20_CMOS_N10

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

G1
G2
G3
G4
G5
G6

41
42
43
44
45
46

Issued Date

4

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

A

C7
680P_0402_50V7K

IPEX_20143-040E-20F
CONN@

1

22 VGA_TZOUT0+
22 VGA_TZOUT0-

VGA_TZOUT0+
VGA_TZOUT0-

LOCAL_DIM_R
BKOFF#
INVTPWM
TZCLK+
TZCLKTZOUT2+
TZOUT2TZOUT1+
TZOUT1-

DEDP@
EDP_HPD
1
2
R447
150K_0402_5%

2
B
E

1

TXOUT0+
TXOUT0-

+3VS

4

36

2 0_0402_5%

2

22 VGA_TXOUT1+
22 VGA_TXOUT1-

36

BOM option for Discrete eDP

1 DLVDS@2 0_0402_5%
1 DLVDS@2 0_0402_5%

1

1 R15

LED PANEL Conn.

R13
R12

1

PJUSB208H_SOT23-6
@

+INVPWR_B+

VGA_TXOUT0+
VGA_TXOUT0-

2

0.1U_0402_16V4Z

USB20_CMOS_P10

R467 1 ULVDS@2 0_0402_5%
R466 1 ULVDS@2 0_0402_5%

W=60mils

C4

D1
INVTPWM

Discrete ONLY
DP0P
N

1

C3

L1
1
2 +INVPWR_B+_R
1
2
B+
1.2UH_1127AS-1R2N_2.4A_30%
FBMA-L11-201209-121LMA50T_0805

W=60mils

22 VGA_TXOUT0+
22 VGA_TXOUT0-

DP1P
N

+INVPWR_B+
L52

Place closed to JLVDS1

5/4 PCH_LCD_CLK& PCH_LCD_DATA
Pull high 2.2K change to 4.7K

+3VS

3

PCH_TXOUT0+
PCH_TXOUT0-

3

2

+LCDVDD
+3VS

C

D

Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

30

of

60

http://hobi-elektronika.net
B

C

D

CRT Connector

+5VS

E

W=40mils
+R_CRT_VCC

D4

1

1

D26
D25
D24
BAV99_SOT23-3 BAV99_SOT23-3 BAV99_SOT23-3
1

A

2

1

1

RB491D_SOT23-3

2

C121
0.1U_0402_16V4Z

3

2

3

2

3

2

SM01000GA00 300mA 47ohm@100Mhz DCR 0.55

W=40mils

1.1A_6V_SMD1812P110TF
1

CRB1.0 use 47ohm@100Mhz Bead
1

+CRT_VCC

F1

+3VS

1

2

Change to 0 ohm for Discrete
UMA@
CRT_R

L42

1

CRT_G

L38

1

CRT_B

L35

1

CRT_R_1
2
BLM18BA470SN1D_2P

L43

1

2
BLM18BA470SN1D_2P

CRT_R_2

CRT_G_1
2
BLM18BA470SN1D_2P

L39

1

2
BLM18BA470SN1D_2P

CRT_G_2

CRT_B_1
2
BLM18BA470SN1D_2P

L36

1

2
BLM18BA470SN1D_2P

CRT_B_2

JCRT1
PAD

T54 @

CRT_11

PAD
C111

T55 @

CRT_5

UMA@

R524

1

1

1

UMA@

R512

C605

1

C598

1

C628

UMA@
UMA@
UMA@
2
2
2
10P_0402_50V8J
10P_0402_50V8J

2

150_0402_1%
2

2

1
C622

R507

150_0402_1%

150_0402_1%

UMA@

1

UMA@

C602

1

1

UMA@

2
2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J

10P_0402_50V8J

2

1

C617

Change to 15pf for Discrete

C623
10P_0402_50V8J

1
UMA@
C614
10P_0402_50V8J
2

UMA@

2

2 0.1U_0402_16V4Z

2

UMA@
C600
10P_0402_50V8J

R111 2

1 10K_0402_5%

1
L10

2
MBC1608121YZF_0603

CRT_HSYNC_2

1
L6

2
MBC1608121YZF_0603

CRT_VSYNC_2
1
1

1

5
P

OE#

A

C128
10P_0402_50V8J

U8
Y

DSUB_12

2

2

2

C115
10P_0402_50V8J

DSUB_15

C144 2
68P_0402_50V8J 1

2

74AHCT1G125GW_SOT353-5
+CRT_VCC

C108
68P_0402_50V8J

P

5

1

2 0.1U_0402_16V4Z

2

A

U6
Y

4

+CRT_VCC

CRT_VSYNC_1

1

+3VS

74AHCT1G125GW_SOT353-5

1

3

G

CRT_VSYNC

OE#

3
C117 1

16
17

1

CRT_HSYNC_1

4

G
G

SUYIN_070546HR015M21MZR
CONN@

100P_0402_50V8J

G

2

2

SM010012010 300ma 120ohm@100mhz DCR 0.4

2

CRT_HSYNC

1

Change to 12pf for Discrete

+CRT_VCC
C152 1

1

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRT_DDC_DATA

16 PCH_CRT_G
3

16 PCH_CRT_B
16 PCH_CRT_HSYNC
16 PCH_CRT_VSYNC
16 PCH_CRT_CLK
16 PCH_CRT_DATA

R529 2 UMA@ 1 0_0402_5%

CRT_R

PCH_CRT_G

R519 2 UMA@ 1 0_0402_5%

CRT_G

PCH_CRT_B

R511 2 UMA@ 1 0_0402_5%

CRT_B

CRT_DDC_CLK

PCH_CRT_HSYNC

R137 2 UMA@ 1 33_0402_5%

CRT_HSYNC

PCH_CRT_VSYNC

R110 2 UMA@ 1 33_0402_5%

CRT_VSYNC

PCH_CRT_CLK

R102 2 UMA@ 1 0_0402_5% CRT_DDC_CLK

PCH_CRT_DATA

R89

1
5

PCH_CRT_R

4

R103
4.7K_0402_5%
2

2

UMA only/Muxless
16 PCH_CRT_R

2

R101
4.7K_0402_5%

DSUB_12

6
Q9A
DMN66D0LDW-7_SOT363-6

DSUB_15

3

3

Q9B
DMN66D0LDW-7_SOT363-6

2 UMA@ 1 0_0402_5% CRT_DDC_DATA

PCH DDC PU 2.2K on Page 17

Discrete only
23 VGA_CRT_R
23 VGA_CRT_G
23 VGA_CRT_B
23 VGA_CRT_HSYNC
23 VGA_CRT_VSYNC
4

23 VGA_DDC_CLK
23 VGA_DDC_DATA

VGA_CRT_R

R527 2 DISO@ 1 0_0402_5%

CRT_R

VGA_CRT_G

R514 2 DISO@ 1 0_0402_5%

CRT_G

VGA_CRT_B

R510 2 DISO@ 1 0_0402_5%

CRT_B

VGA_CRT_HSYNC

R131 2 DISO@ 1 0_0402_5% CRT_HSYNC

VGA_CRT_VSYNC

R107 2 DISO@ 1 0_0402_5% CRT_VSYNC

VGA_DDC_CLK

R98

VGA_DDC_DATA R86

2 DISO@ 1 0_0402_5% CRT_DDC_DATA

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

4

2 DISO@ 1 0_0402_5% CRT_DDC_CLK

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

31

of

60

http://hobi-elektronika.net

A

B

C

D

R173
0_0603_5%
1
2

E

W=40mils
+HDMI_5V_OUT

D5
+5VS

2

F2
1

+HDMI_5V

1

@
RB491D_SOT23-3

2

1.1A_6V_SMD1812P110TF

1

2

1

C344
0.1U_0402_16V4Z
1

HDMI connector
JHDMI1
HDMI_HPD

+3VS

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

1

HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-

R182
1M_0402_5%

UMA@

2

G

2

HDMI_R_CK+
HDMI_R_D01
D

Q15
2N7002H_SOT23-3

HDMI_HPD
1

3
S

16 PCH_DPB_HPD

R191
UMA@
100K_0402_5%

2

C337

HDMI_R_D1+
HDMI_R_D2-

220P_0402_50V7K
HDMI_R_D2+

2

UMA@

HDMI_R_D0+
HDMI_R_D11

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

ACON_HMR2E-AK120D
CONN@

2

2

SM070001310 400ma 90ohm@100mhz DCR 0.3
HDMI_CLK+

R211 1

1
L13
@
WCM2012F2S-900T04_0805
4

4

3

HDMI_CLK-

R207 1

2

HDMI_TX0+

R201 1

2

2
3
0_0402_5%

HDMI_R_CK-

0_0402_5%

HDMI_R_D0+

C364 UMA@ 2
C368 UMA@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX2HDMI_TX2+

16 PCH_DPB_N1
16 PCH_DPB_P1

C357 UMA@ 2
C359 UMA@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX1HDMI_TX1+

16 PCH_DPB_N2
16 PCH_DPB_P2

C347 UMA@ 2
C349 UMA@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX0HDMI_TX0+

HDMI_TX0-

R195 1

2

0_0402_5%

HDMI_R_D0-

16 PCH_DPB_N3
16 PCH_DPB_P3

C352 UMA@ 2
C356 UMA@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_CLKHDMI_CLK+

HDMI_TX1+

R213 1

2

0_0402_5%

HDMI_R_D1+

23 VGA_HDMI_TXD223 VGA_HDMI_TXD2+

C716 DISO@ 2
C717 DISO@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX2HDMI_TX2+

23 VGA_HDMI_TXD123 VGA_HDMI_TXD1+

C714 DISO@ 2
C715 DISO@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX1HDMI_TX1+

23 VGA_HDMI_TXD023 VGA_HDMI_TXD0+

C704 DISO@ 2
C709 DISO@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_TX0HDMI_TX0+

23 VGA_HDMI_TXC23 VGA_HDMI_TXC+

C712 DISO@ 2
C713 DISO@ 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_CLKHDMI_CLK+

1
L12
@
WCM2012F2S-900T04_0805
4

1
L14
@
WCM2012F2S-900T04_0805
4

+3VSDGPU

DISO@ Q43
MMBT3904_G_SOT23-3
3

2
B

1
R544

E

HDMI_HPD
2
150K_0402_5%

DISO@

1

2

4

3

1

2

4

3

2
3

2
3

HDMI_TX1-

R212

1

2

0_0402_5%

HDMI_R_D1-

HDMI_TX2+

R219

1

2

0_0402_5%

HDMI_R_D2+

1
L15
@
WCM2012F2S-900T04_0805
4

C

HDMI_TX2-

2
G

DIS Only
3

2

16 PCH_DPB_N0
16 PCH_DPB_P0

1

UMA/Muxless

2

1

HDMI_R_CK+

0_0402_5%

1

2

4

R215 1

3

3
2

2
3
0_0402_5%

HDMI_R_D2-

3

Q44
2N7002H_SOT23-3
MUXL@

2

R537
10K_0402_5%
DISO@

1

S

1

18 DGPU_HPD_INT#

D

23 VGA_HDMI_DET

+HDMI_5V_OUT

SDVO_SDATA

+3VS

Q47

UMA only/Muxless need confirm

1 UMA@ 2 0_0402_5%
1 DISO@ 2 0_0402_5%

HDMI_SDATA_R

3

1

Q45
2N7002H_SOT23-3
1
D

S

Place closed to JHDMI1

HDMI_SDATA

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

4

HDMI_SCLK

Issued Date

Q46
2N7002H_SOT23-3

S

2N7002H_SOT23-3

1

1
G

R551
R550

16 SDVO_SDATA
23 VGA_HDMI_SDATA

3

D

HDMI_SCLK_R

S

1 UMA@ 2 0_0402_5%
1 DISO@ 2 0_0402_5%

D

2
G

+3VS
R548
2.2K_0402_5%

G

R547
R546

16 SDVO_SCLK
23 VGA_HDMI_SCLK

2 680_0402_5%
2 680_0402_5%
HDMI_GND

2

GPU Pull high at VGA side

2 680_0402_5%
2 680_0402_5%

HDMI_CLK- R567 1
HDMI_CLK+ R570 1
D27
RB751V-40_SOD323-2

R552
2.2K_0402_5%

2

4

HDMI_TX0- R562 1
HDMI_TX0+ R566 1

2 1

2 1

D28
RB751V-40_SOD323-2

2 680_0402_5%
2 680_0402_5%

1

R549 1 UMA@ 2 2.2K_0402_5%

2 680_0402_5%
2 680_0402_5%

HDMI_TX1- R571 1
HDMI_TX1+ R572 1

3

SDVO_SCLK
2

R545 1 UMA@ 2 2.2K_0402_5%

2

+3VS

HDMI_TX2- R573 1
HDMI_TX2+ R575 1

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

32

of

60

http://hobi-elektronika.net

A

B

C

D

E

SATA HDD1 Conn.
CL 2.9 mm

JHDD1
13 SATA_PTX_DRX_P0
13 SATA_PTX_DRX_N0
13 SATA_PRX_DTX_N0
13 SATA_PRX_DTX_P0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

C507 1
C514 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C508 1
C515 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

+3VS

1
2
3
4
5
6
7

GND
RX+
RXGND
TXTX+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
GND
GND

1

1

1

C488
0.1U_0402_16V4Z

+5VS

+3VS

2

J8 @
1

1

2

+5VS_HDD1

2

JUMP_43X118

100mils

2

1

2

C536
1000P_0402_50V7K

2

1

C534
0.1U_0402_16V4Z

1

C532
1U_0402_6.3V6K

2

C525
10U_0805_10V4Z

1

OCTEK_SAT-22DD1G
CONN@

SATA HDD2 Conn.
CL 4.4 mm
JHDD2

2

13 SATA_PTX_DRX_P1
13 SATA_PTX_DRX_N1
13 SATA_PRX_DTX_N1
13 SATA_PRX_DTX_P1

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

C433 1
C435 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

C446 1
C463 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

+3VS

C512
0.1U_0402_16V4Z

+5VS
J9
1

1

1

+3VS

2

@
2

+5VS_HDD2

2

JUMP_43X118

100mils

2

1

2

C538
1000P_0402_50V7K

2

1

C540
0.1U_0402_16V4Z

1

C539
1U_0402_6.3V6K

2

C546
10U_0805_10V4Z

1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

2

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

24
23

GND
GND

ALLTO_C16634-122A4-L
CONN@

3

3

SATA ODD Conn.
JODD1

SB564020020(S TR AO6402A 1N TSOP-6 W/D)
+5VS_ODD

+5VS
+VSB

GND
A+
AGND
BB+
GND

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

S
G
2

1

SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2

2

18 ODD_DETECT#

+5VS_ODD

2

17

ODD_DA#

R174 1

@

2 0_0402_5%

ODD_DETECT#_R

R167 1

@

2 0_0402_5%

ODD_DA#_R

1

S 2N7002H_SOT23-3

1
@

2

1

2

1

2

1

2

1

2

C269
1000P_0402_50V7K

3

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

C268
0.1U_0402_16V4Z

@

C329 1
C323 1

C267
1U_0402_6.3V6K

@

4

1

80mils

D
Q14

2
G

13 SATA_PRX_DTX_N2
13 SATA_PRX_DTX_P2

JUMP_43X118

C328
0.1U_0402_25V6K

ODD_EN#

1

Q13
AO6402A 1N TSOP6

R188
1.5M_0402_5%

18

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

J10 @

4
@

C294
10U_0805_10V4Z

ODD_EN

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

+5VS

D
1

2

6
5
2
1

C341 1
C336 1

3

2

@

C322
1U_0402_6.3V6K

1

R185
470K_0402_5% @

13 SATA_PTX_DRX_P2
13 SATA_PTX_DRX_N2

1
2
3
4
5
6
7

17
16
15
14

GND
GND
GND
GND

OCTEK_SLS-13SB1G_RV
CONN@

4

Place Cap near ODD Conn.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9
Sheet

Tuesday, November 09, 2010
E

33

of

60

http://hobi-elektronika.net

A

B

For Wireless LAN

+3VS_WLAN

1
+3VS

+3VS_WLAN
J11 @
2

2

1

1

60mil

+1.5VS

1

C28
4.7U_0805_10V4Z

2

C9
0.1U_0402_16V4Z

2

1

C

D

E

+3VS_WLAN

C574
4.7U_0805_10V4Z

2

1

C24
0.1U_0402_16V4Z

2

1

1

C10
0.1U_0402_16V4Z

2

C575
0.1U_0402_16V4Z

2

JUMP_43X118
1

1

+3VS_WLAN
JMINI1

14 MINI1_CLKREQ#
14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1

14 PCIE_PRX_DTX_N2
14 PCIE_PRX_DTX_P2

14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2
R473
1

36,40,47,48 SUSP#

18,35

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

BT_CTRL
D

S

Primary Power (mA)

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

WL_OFF#
PLT_RST_BUF#

Normal

WL_OFF# 18
PLT_RST_BUF# 17
+3VS_WLAN

MINI_SMBCLK
MINI_SMBDATA

R469 1
R470 1

@
@

2 0_0402_5%
2 0_0402_5%

PCH_SMBCLK 5,14
PCH_SMBDATA 5,14
USB20_N8 17
USB20_P8 17
MINI1_LED# 36

(9~16mA)
R472
100K_0402_5%

2

G1
G2
G3
G3
53
54
55
56

ACES_88914-5204

8 mm High

+3VS_WLAN

WLAN&BT Combo module circuits

CONN@
Q51

2
G

Power

1

D31
RB751V-40_SOD323-2
1
2
@

BT_ON#

E51TXD_P80DATA1_R
E51RXD_P80CLK_R

2
4
6
8
10
12
14
16

R476
1K_0402_5%

1

2

36 E51TXD_P80DATA
36 E51RXD_P80CLK

1
3
5
7
9
11
13
15

2

R474
0_0402_5%
1
2
1
2
R475
0_0402_5%

100K_0402_5%

3

2

1
3
5
7
9
11
13
15

1

(WLAN_BT_DATA)
(WLAN_BT_CLK)

2

15,35,41 PCH_PCIE_WAKE#

Mini Card Power Rating

+1.5VS +3VS_WLAN

R464
0_0402_5%
1
2
@

BT on module

2N7002H_SOT23-3

Enable

Disable

BT_CTRL

H

L

BT_ON#

L

H

+3VS_WWAN

+1.5VS

+3VS_WWAN

J12 @
2

+3VS

2

1

1

1

+3VS_WWAN

JUMP_43X118

C753
4.7U_0805_10V4Z

2

1

C741
0.1U_0402_16V4Z

2

1

C743
4.7U_0805_10V4Z

2

1

C747
0.1U_0402_16V4Z

2

1

C752
0.1U_0402_16V4Z

2

1

C742
0.1U_0402_16V4Z

2

JMINI2

3

R597 1

@

2 0_0402_5%

14 MINI2_CLKREQ#
14 CLK_PCIE_MINI2#
14 CLK_PCIE_MINI2

14 PCIE_PRX_DTX_N3
14 PCIE_PRX_DTX_P3

14 PCIE_PTX_C_DRX_N3
14 PCIE_PTX_C_DRX_P3
+3VS_WWAN

R599 1
R598 1

@
@

2 0_0402_5%
2 0_0402_5%

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

LAN CONN. LS-6912P

+3VS_WWAN
+1.5VS

3

JLAN1

WWAN_OFF#
PLT_RST_BUF#

18
17

WWAN_OFF# 18

+3VS_WWAN
MINI_SMBCLK
MINI_SMBDATA
USB20_N9
USB20_P9

USB20_N9 17
USB20_P9 17

G2
G1

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+3VALW

LAN_CLKREQ# 14
EC_PME# 36
PLT_RST# 5,17,35,36,41
PCIE_PTX_C_DRX_N1 14
PCIE_PTX_C_DRX_P1 14
CLK_PCIE_LAN 14
CLK_PCIE_LAN# 14
PCIE_PRX_DTX_P1 14
PCIE_PRX_DTX_N1 14

ACES_88460-1601
CONN@

MINI2_LED# 36

(9~16mA)
R623
100K_0402_5%

CONN@

53
54
55
56

ACES_88914-5204

2

G1
G2
G3
G3

E51TXD_P80DATA
E51RXD_P80CLK

1
3
5
7
9
11
13
15

1

PCH_PCIE_WAKE#

+3VS_WWAN
4

4

8 mm High

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

34

of

60

http://hobi-elektronika.net

A

B

JREAD1
11
18
39

SD_VCC
MS_VCC
XD_VCC

XDD0_SDCLK_MSD2
XDD2_SDCMD
XDWE#_SDCD#
XDDRY_SDWP_MSCLK
XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1

8
16
1
2
4
3
21
19

SD_CLK
SD_CMD
SD_CD
SD_WP
SD/MMC_DAT0
SD/MMC_DAT1
SD/MMC_DAT2
SD/MMC_DAT3

XDD1_MSD0
XDD4_SDD3_MSD1
XDD0_SDCLK_MSD2
XDALE_MSD3
XDDRY_SDWP_MSCLK
XDRE#_MSINS#
XDD6_MSBS

10
9
12
15
17
14
7

MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS

+CARDPWR

1

C

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

31
32
33
34
35
36
37
38

XDD0_SDCLK_MSD2
XDD1_MSD0
XDD2_SDCMD
XDD3
XDD4_SDD3_MSD1
XDD5_SDD2_MS_D5
XDD6_MSBS
XD_D7

XD_CD
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP-IN

22
23
24
25
26
27
28
29

XD_CD#
XDDRY_SDWP_MSCLK
XDRE#_MSINS#
XDCE#_SDD1
XDCLE_SDD0
XDALE_MSD3
XDWE#_SDCD#
XDWP#

SD_GND
SD_GND
MS_GND
MS_GND
XD_GND
XD_GND
GND
GND

6
13
5
20
30
40
41
42

D

1

LS-6911P
USB/B Conn. (USB2.0 SKU)

TAITW_R013-P17-HM_NR
CONN@

W=100mils

(Port 0,1)
17
17

USB20_N0
USB20_P0

17
17

USB20_N2
USB20_P2

JUSB1
1
2
3
4
5
6
7
8
9
10
11
12

USB20_N0
USB20_P0
USB20_N2
USB20_P2
SYSON#

40,41 SYSON#

+5VALW
+CARDPWR

+CARDPWR

30mil

close to connector
1

2

13
14
2

C509
0.1U_0402_16V4Z

1
R344
100K_0402_5%
@

2

C511
0.1U_0402_16V4Z

USB/B USB3.0 Conn.(USB3.0 SKU)

1

2

GND
GND

ACES_85201-1205N
CONN@

1
C510

0.1U_0402_16V4Z

1
2
3
4
5
6
7
8
9
10
11
12

2

2

E

(Port 3)
+3VS_CR

30mil

RTS5138

JUMP_43X39
C4272

1 100P_0402_50V8J

1
R287
17
17

2
6.2K_0603_1%
USB20_N11
USB20_P11

30mil
1

2

10mil

REFE

2
3

DM
DP

+3VS_CR
+CARDPWR
VREG

4
5
6

3V3_IN
CARD_3V3
V18

XD_CD#

7

XD_CD#

C430
2

1U_0402_6.3V6K

C423
1

0.1U_0402_16V4Z

4.7U_0805_10V4Z

C424
2

1

U18
1

XDDRY_SDWP_MSCLK_L 8
XDRE#_MSINS#
9
XDCE#_SDD1
10
XDCLE_SDD0
11
XDALE_MSD3
12

SP1
SP2
SP3
SP4
SP5

25

3

10mil
RREF

30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

R333
10K_0402_5%
2

2

2

EPAD

1

1

J14 @
1

5IN1_LED#

GPIO0

17

CLK_IN

24

XD_D7

23

R314 1
XD_D7

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

XDD6_MSBS
XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1
XDD3
XDD2_SDCMD
XDD1_MSD0
XDD0_SDCLK_MSD2_L
XDWP#
XDWE#_SDCD#

5IN1_LED# 37
CLK_SD_48M 14
@

18,41
SMIB
15,34,41 PCH_PCIE_WAKE#
36,40,41,46 SYSON

SYSON
+1.5V

2
1
2
10_0402_5%C442
10P_0402_50V8J

+5VALW

@

30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

GND
GND
GND
GND
GND
GND

+3VS

36
35
34
33
32
31

+3VS

29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

+3VALW

2

1

XDD0_SDCLK_MSD2
1
22_0402_5%
1
C483
4.7P_0402_50V8J

SD

BT_ON#

C559

2

G
D

2

SD_CD#

1
C561
BT@
4.7U_0805_10V4Z

MS_D2
MS_D0

1

2

MS_D1
MS_BS

R438
BT@
300_0603_5%

D

2
G
3

Share Pin

BT Conn.

S

17
17

USB20_P13
USB20_N13

18

WL_EN#

(WLAN_BT_DATA)
(WLAN_BT_CLK)
WL_EN#

Q28
2N7002H_SOT23-3
BT@

8
7
6
5
4
3
2
1

2010/07/12

(Port 13)

8 GND
7
6
5
4
3
2
1 GND

10

4

9

ACES_87213-0800G
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

+BT_VCC

JBT1

C558
BT@
0.1U_0402_16V4Z

SD_CMD
SD_D3
SD_D2

BT Wire Cable Note:
Pin 3, Pin 4 NC
+BT_VCC

2

0930 EMI request

1U_0603_10V6K

Q29
BT@
AO3419L_SOT23-3

W=40mils

BT@
0.1U_0402_16V4Z
MS_D3

SD_CLK

3

1 BT@
2
R431
10K_0402_5%

MS_CLK
MS_INS#

SD_D1
SD_D0

2

S

1

SD_WP

MS

BT_ON#

1

1

XD
XD_CD#
XD_RDY
XD_RE#
XD_CE#
XD_CLE
XD_ALE
XD_WE#
XD_WP
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

18,34

C562

BT@

2

XDD0_SDCLK_MSD2_L 2
R332
4

3

1

2

Pull high @ USB3.0/B side

+3VS

BT@

SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14

PLT_RST# 5,17,34,36,41
USB30_CLKREQ# 14

+3VALW
+5VALW

RTS5138-GR_QFN24_4X4
C560

1 XDDRY_SDWP_MSCLK
22_0402_5%
1
C448
4.7P_0402_50V8J

PCIE_PTX_C_DRX_P4 14
PCIE_PTX_C_DRX_N4 14
PCIE_PRX_DTX_P4 14
PCIE_PRX_DTX_N4 14
CLK_PCIE_USB30 14
CLK_PCIE_USB30# 14
USB20_N3 17
USB20_P3 17

JUSB3
ACES_50050-03071-001
CONN@

0.1U_0402_16V4Z

XDDRY_SDWP_MSCLK_L 2
R318

29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

35

of

60

http://hobi-elektronika.net

A

B

C

D

E

+3VALW
EC_MUTE#

R317

2

65W/90W#

R350

2

1 100K_0402_5%

3S/4S#

R349

2

1 100K_0402_5%

TP_CLK

R319

1

2

4.7K_0402_5%

TP_DATA

R323

1

2

4.7K_0402_5%

@

1 10K_0402_5%

+5VS

18
GATEA20
18 EC_KBRST#
13
SERIRQ
13 LPC_FRAME#
13
LPC_AD3
13
LPC_AD2
13
LPC_AD1
13
LPC_AD0

0.1U_0402_16V4Z

1

+3VALW

10/1 ENE Recommand
1

2 47K_0402_5%

KSO1

R252

1

2 47K_0402_5%

KSO2

R300

1

2 1K_0402_5%

EC_SMI#

1

2 2.2K_0402_5%

EC_SMB_DA1

1

2 2.2K_0402_5%

EC_SMB_CK1

R253

17 CLK_PCI_LPC
5,17,34,35,41 PLT_RST#
18

R297
R290

EC_SCI#

2

R299

2 100K_0402_5%

1

EC_PME#

+3VS
2 2.2K_0402_5% EC_SMB_CK2

1

R309

1

2 2.2K_0402_5% EC_SMB_DA2

R296

1

2 10K_0402_5% EC_SCI#

R308 1

2 100K_0402_5%

EC_XCLK1

@

OSC

OSC
NC

3

NC

2

45
45
14,23
14,23

C504

@
2

15P_0402_50V8J

SUSWARN#
PM_SLP_SUS#

2

Board ID

PCH_PWR_EN

Analog Board ID definition,
Please see page 3.

SUSACK#

R257
100K_0402_5%
AD_BID0

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

1

R355

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

C411
0.1U_0402_16V4Z

2

2

BATT_TEMP

68
70
71
72

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
GFX_CORE_PWRGD

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

LOCAL_DIM
65W/90W#
HDA_SDO
LID_SW#

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

COLOR_ENG_EN
EC_PECI
FSTCHG
BATT_GRN_LED#

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PCH_RSMRST#
EC_LID_OUT#
EC_ON
3S/4S#
PCH_PWROK
BKOFF#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

PM_SLP_S4#
ENBKL
EAPD
VGATE
SUSP#
PBTN_OUT#

V18R

124

+V18R

PCH_DPWROK

2 10K_0402_5%

ADP_I
AD_BID0

ADP_I

IMON_R

R281 2

1 0_0402_5%

EC_ACIN

1
RB751V-40_SOD323-2

VR_HOT#

VR_HOT#

EN_DFAN1 39
IREF
43
CALIBRATE# 43

R258
0_0402_5%
2
1

H_PROCHOT#_EC

EC_MUTE# 38
GFX_CORE_PWRGD 52

WWAN_LED#

15,40,43

H_PROCHOT# 5,45
D

S

Q48
2N7002H_SOT23-3

2
G

2

Latest design guide suggest change to
74LVC1G06.

DRAMRST_CNTRL_EC

TP_CLK 37
TP_DATA 37

ACIN

1 100P_0402_50V8J

2

43,45

52

H_PROCHOT#_EC
TP_CLK
TP_DATA

2

C481

IMVP_IMON 52

DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#

1 200K_0402_5%

2

D17

42,43

1 100P_0402_50V8J ECAGND
BATT_TEMP 45

LOCAL_DIM 30
65W/90W# 43,45
HDA_SDO 13
LID_SW# 37

SPI Device Interface
SPI Flash ROM

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
EC_PME#
MINI1_LED#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

122
123

@

1

+3VALW

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

EC_XCLK1
EC_XCLK0
2
0_0402_5%

ACOFF
C398 2

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

PS2 Interface

77
78
79
80

E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED#
WLAN_LED#

1

AD

MINI2_LED# 34
BEEP#
38

ACOFF

63
64
65
66
75
76

R340

CPU1.5V_S3_GATE

MINI2_LED#
BEEP#

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

21
23
26
27

PWM Output

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

FAN_SPEED1

34 E51TXD_P80DATA
34 E51RXD_P80CLK
37
ON/OFF
37 PWR_SUSP_LED#
37 WLAN_LED#

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

GPIO
SM Bus

GPI

XCLK1
XCLK0

11
24
35
94
113

R263
8.2K_0402_5%

Rb

12
13
37
20
38

SUS_PWR_DN_ACK

15 SUS_PWR_DN_ACK
30
INVT_PWM
39 FAN_SPEED1

15 SUSCLK

1

1

Ra

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

15 PM_SLP_S3#
15 PM_SLP_S5#
18
EC_SMI#
34
EC_PME#
34 MINI1_LED#

X1
32.768KHZ_12.5PF_Q13MC14610002

+3VALW

KSI[0..7]
KSO[0..17]

PLT_RST#

3

15P_0402_50V8J

4

1
1

1
@

KSI[0..7]
KSO[0..17]

CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#

EC_XCLK0

2

C499

37
37

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

GND
GND
GND
GND
GND

R301

1
2
3
4
5
7
8
10

R342

+3VALW

CPU1.5V_S3_GATE

GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

COLOR_ENG_EN 30
FSTCHG 43
BATT_GRN_LED# 37

R351

1 100K_0402_5%

2

R277 1

2 43_0402_1%

H_PECI

5,18

3G_LED#

BATT_AMB_LED# 37
PWR_LED 37
SYSON
35,40,41,46
VR_ON
52

PCH_RSMRST# 15
EC_LID_OUT# 14
EC_ON
37,44
3S/4S# 43
PCH_PWROK 15
BKOFF# 30

3

PCH_APWROK

SA_PGOOD

1

2

KB930QF A1 LQFP 128P

LID_SW#

EC_SI_SPI_SO 37
EC_SO_SPI_SI 37
EC_SPICLK 37
EC_SPICS#/FSEL# 37

BATT_AMB_LED#
PWR_LED
SYSON
VR_ON
EC_ACIN

AGND

C399 2

1

BKOFF#

EC_RST#

1 47K_0402_5%

69

R251 2

+3VALW

+3VS

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U21

2

1

1

C414
0.1U_0402_16V4Z

SA_PGOOD 47

PM_SLP_S4# 15
ENBKL
EAPD
38
VGATE
15,52
SUSP#
34,40,47,48
PBTN_OUT# 5,15

16,23

2

1

1

R354
100K_0402_5%
1

2

2

C400
1000P_0402_50V7K

2

2

C422
1000P_0402_50V7K

CLK_PCI_LPC

2

1

C475
0.1U_0402_16V4Z

2

R315
33_0402_5%
2
1

1

C498
0.1U_0402_16V4Z

C443
22P_0402_50V8J
2
1

1

C447
0.1U_0402_16V4Z

1

C506
0.1U_0402_16V4Z

1

ECAGND

2

JUMP_43X39

9
22
33
96
111
125

1

+3VALW_EC

2

3

J15 @
1

67

+3VALW

L21
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

C748
4.7U_0805_10V4Z

20mil

For EC Tools

L22
ECAGND 2
1
FBMA-L11-160808-800LMT_0603

+3VALW

Place on RAM door

JP1
1
2
3
4

4

1
2
3
4

E51RXD_P80CLK
E51TXD_P80DATA

E51RXD_P80CLK 34
E51TXD_P80DATA 34

ACES_85205-0400
@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

36

of

60

4

http://hobi-elektronika.net
B

C

C755 1

TP/B P7YE0/P7YH0

2 0.1U_0402_16V4Z

20mil

150mils

8
7

VDD
SCK
SI
SO

8
6
5
2

EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R

R629 1
R624 1
R631 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

MX25L1005AMC-12G_SOP8
EC_SPICLK_R
1

KSI[0..7]

KSO[0..17]

LED/B P7YE0/P7YH0

7
8

1
@

1

2

100P_0402_50V8J

C66

1

2

100P_0402_50V8J

KSO15

C64

1

2

100P_0402_50V8J

KSO7

C56

1

2

100P_0402_50V8J

KSO14

C63

1

2

100P_0402_50V8J

KSO6

C55

1

2

100P_0402_50V8J

KSO13

C62

1

2

100P_0402_50V8J

KSO5

C69

1

2

100P_0402_50V8J

KSO12

C61

1

2

100P_0402_50V8J

KSO4

C70

1

2

100P_0402_50V8J

KSI0

C47

1

2

100P_0402_50V8J

KSO3

C68

1

2

100P_0402_50V8J

KSO11

C60

1

2

100P_0402_50V8J

KSI4

C51

1

2

100P_0402_50V8J

KSO10

C59

1

2

100P_0402_50V8J

KSO2

C46

1

2

100P_0402_50V8J

KSI1

C48

1

2

100P_0402_50V8J

KSO1

C45

1

2

100P_0402_50V8J

KSI2

C49

1

2

100P_0402_50V8J

KSO0

C67

1

2

100P_0402_50V8J

EMI ADD at 10/29

ON

Battery
Full

C52

1

2

6
5
4
3
2
1

+5VS

+3VALW
LID_SW# 36

LID_SW#

1

PWR_LED#
ON/OFFBTN#

Charge

3G/WLAN
3G

LEFT_BTN#
RIGHT_BTN#

D7
PJDLC05C_SOT23-3

D6
PJDLC05C_SOT23-3

C340
0.1U_0402_16V4Z

2

2

BlueTooth

ACIN
LEFT_BTN#

WLAN

3

SW2
EVQPLDA15_4P
1

4

NEW70/80/90 Blue Amber Blue

TP_CLK
TP_DATA

RIGHT_BTN#

2

3

SW3
EVQPLDA15_4P
1

4

2

Blue Amber

PWR_LED#
LED6

+3VALW

100P_0402_50V8J

1

1

A

D

C50

1

2

100P_0402_50V8J

KSI6

C53

1

2

100P_0402_50V8J

KSO8

C57

1

2

100P_0402_50V8J

KSI7

C54

1

2

100P_0402_50V8J

Q19
2N7002H_SOT23-3

PWR_SUSP_LED# 36

2
G

PWR_LED 36

S
LED5

KSI3

PWR_SUSP_LED#
1
820_0402_5%

2
HT-191UD5_AMBER R432

2

PWR_LED#
1
499_0402_1%

2
R433

B

R288
100K_0402_5%

3

1
1

KSI5

C405

2
2
100P_0402_50V8J 100P_0402_50V8J

ACES_85201-0605N
CONN@

SUS

@

3

100P_0402_50V8J

GND
GND
6
5
4
3
2
1

PWR_LED#
ON/OFFBTN#

Power/SUS

LED Status

EMI ADD at 10/29

1
C404

2

+3VALW

LID_SW#

2

3

TP_CLK 36
TP_DATA 36

JLED2
8
7

ACES_85201-0605N
CONN@

C65

2

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

LS-6913P

JLED1

ACES_88747-2601
CONN@

1

1
2
3
4
5
6

LED/B P7YS0

LS-6913P

KSO17

C58

1
2
3
4
5
6
GND
GND

ACES_85201-0605N
CONN@

KSO16

KSO9

+5VS

7
8

1
2
3
4
5
6
GND
GND

1

C372

2
2
100P_0402_50V8J 100P_0402_50V8J

JTP2

KSO[0..17] 36

1
2
3
4
5
6

1
C373

TP/B P7YS0

R626
@
0_0402_5%
C751
@
33P_0402_50V8K

36

1

1

(Right)

KSI[0..7]

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

5
6

2

INT_KBD Conn.

28
27

KSO0
G2
KSO1
G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

6
5
4
3
2
1

ACES_85201-0605N
CONN@

2
JKB1

(Left)
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

+5VS

GND
GND
6
5
4
3
2
1

EC_SPICLK 36
EC_SO_SPI_SI 36
EC_SI_SPI_SO 36

3

CE#
WP#
HOLD#
VSS

2

1
3
7
4

1

+3VALW

2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#

2

R628 1
R633 1

To TP/B Conn.

JTP1

U35
36 EC_SPICS#/FSEL#

E

5
6

+3VALW

D

3

A

HT-191NB5_BLUE

2

ON/OFF switch

2
R436

1
499_0402_1%

R381

TOP Side
1

51ON#

4

R380

Test Only

36

51ON#

42

2

S

Q23
2N7002H_SOT23-3

2
G

A

U22
2

B
A

Y

5IN1_LED# 35

1

PCH_SATALED# 13

MC74VHC1G08DFT2G_SC70-5

1

2
HT-191UD5_AMBER R435
LED7
2

2
R434

B

BATT_AMB_LED#
1
820_0402_5%

BATT_AMB_LED# 36

BATT_GRN_LED#
1
499_0402_1%

BATT_GRN_LED# 36

LED10

(Amber)

1
+3VS

2
R437

1
820_0402_5%

2

A

WLAN_LED#

1

WLAN_LED# 36

HT-191NB5_BLUE
HT-191UD5_AMBER

10K_0402_5%

SW5
EVQPLDA15_4P
1
3
2

4

1

Bottom Side

4
@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

6
5

4

1
EC_ON

D

3

EC_ON

2

36,44

ON/OFF

+3VALW

DAN202UT106_SC70-3

6
5

@

4

LED8

2
3

2

MEDIA_LED#

1

HT-191NB5_BLUE

1
ON/OFFBTN#

(Blue)
B

100K_0402_5%

D21

SW4
EVQPLDA15_4P
1
3

2

P
+3VS

G

LED9

+3VALW

3

Power Button

5

+3VS

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

37

of

60

http://hobi-elektronika.net

A

B

C

D

E

+VDDA

2
1

2

13

C480 1

PCH_SPKR

2

1

R336

3

1
2
3
4

1
2
3
4

1
R368
E

Q21
MMBT3904_G_SOT23-3

D2
PJDLC05C_SOT23-3

D3
PJDLC05C_SOT23-3

Singatron 2SJ2326
DC021007151

2

1

Place near Pin46
C550

SM010014520 3000ma 220ohm@100mhz DCR 0.04

HD Audio Codec

2

C777 1
C778 1
1

2

Combo MIC

3

C767
2.2U_0402_6.3VM

+MIC2_VREFO

Internal MIC

MIC1_R

35

CBN

36

CBP

29

31

10mil

SPK_OUT_L+

40

SPKL+

SPK_OUT_L-

41

SPKL-

SPK_OUT_R+

45

SPKR+

SPK_OUT_R-

44

SPKR-

HPOUT_L

32

HP_LEFT

HPOUT_R

33

HP_RIGHT

SDATA_IN

8

SDATA_OUT

5

2 10U_0805_10V4Z

28

MIC2_VREFO

SYNC

10

RESET#

11

MIC1_VREFO_R

1
20K_0402_1%

19

2

D13

BCLK

HDA_SYNC_AUDIO

HDA_SDIN0 13

MIC1_L
R282

13

MIC1_R
R312

13

1
+MIC1_VREFOR

+MIC1_VREFOL

HDA_BITCLK_AUDIO

1
1

2 MIC1_L_1
1K_0603_5%
2 MIC1_R_1
1K_0603_5%

MIC JACK

R271
4.7K_0402_5%

L24 1
2
FBMA-L11-160808-800LMT_0603
L25 1
2
FBMA-L11-160808-800LMT_0603

JMIC1

MIC1_L_R

1
2

MIC1_R_R

3

SM010015410 300ma 80ohm@100mhz DCR 0.3 C432

13

@
@
1
2
1
2 C769
22P_0402_50V8J
R645 0_0402_5%

LDD_CAP

220P_0402_50V7K

For EMI

1

2

MIC_PLUG#

1

C416
220P_0402_50V7K

2
D12
PJDLC05C_SOT23-3

2

GPIO1/DMIC_CLK

3

PD#

4

JDREF

3

4

SM010004010 300ma 70ohm@100mhz DCR 0.3

HDA_RST_AUDIO# 13

6

D11
RB751V-40_SOD323-2

R298
4.7K_0402_5%

HDA_SDOUT_AUDIO

2
D15
PJDLC05C_SOT23-3

R702
22K_0402_5%

0927 Vender suggest add 22K PD

HDA_SDIN0_AUDIO 1 R646
2
33_0402_5%

MIC1_VREFO_L

GPIO0/DMIC_DATA
R693
2

10U_0805_10V4Z

1

HP_PLUG#
+MIC1_VREFO

RB751V-40_SOD323-2

+INTMIC_VREFO

C772 1

C557

22K_0402_5%

2

35mA

MIC_PLUG#

COM_MIC

2

3

1

1

46

9

Q25
BSS138_NL_SOT23-3S

MIC1_L

22

2
G

1

LINE1_R

R411
1

1

LINE1_L

10mil

39

MIC2_R

24
21

38

68mA 600mA

23

10mil
+MIC1_VREFO

R409
2.2K_0402_5%

3

MIC2_L

17

30

External MIC

MIC2JD

1

MIC1_R

MIC1_C_L
4.7U_0603_6.3V6K
MIC1_C_R
2
4.7U_0603_6.3V6K
2

16

DVDD

2

LINE2_R

2

FootPrint

2

External MIC

2

C776 1

LINE2_L

15

CONN@

1

MIC1_L

C775 1

14

SINGA_2SJ2326-001111

+MIC2_VREFO

D
DVDD_IO

1 COM_MIC_R
1K_0402_5%

2

PVDD2

2
R692

2

C774 1

PVDD1

INT_MIC
1
1K_0402_5%

5

SM010015410 300ma 80ohm@100mhz DCR 0.3

+3VS

1
C545

2

COM_MIC

2
R691

2
4

SM010004010 300ma 70ohm@100mhz DCR 0.3

2

Combo MIC

INT_MIC_R

MIC2_C_L
4.7U_0603_6.3V6K
MIC2_C_R
4.7U_0603_6.3V6K
LINE2_C_L
4.7U_0603_6.3V6K
LINE2_C_R
4.7U_0603_6.3V6K

1

HPOUT_R_2
HP_PLUG#

Place near Pin1, 9
U36

HPOUT_L_2

3

2
0.1U_0402_16V4Z

Place near Pin25, 38

Internal MIC

L29 2
1
BLM18AG121SN1D_0603

L30 1
2
FBMA-L11-160808-800LMT_0603
L27 1
2
FBMA-L11-160808-800LMT_0603

3
6

2

C766

C773 1

10U_0603_6.3V6M
1
C548

0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

25

2

2 75_0603_5% HPOUT_R_1

1

1

1

C762
2

1
C542

AVDD2

C758
10U_0805_10V4Z

+3VS_DVDD

+AVDD_HDA

40mil

0.1U_0402_16V4Z
1
1

AVDD1

+VDDA

2 75_0603_5% HPOUT_L_1

HP_RIGHT R363 1

SM010030010 200ma 120ohm@100mhz DCR 0.2

10mil

SM010030010 200ma 120ohm@100mhz DCR 0.2
L50 2
1
BLM18AG121SN1D_0603

HP_LEFT R408 1

COM_MIC

2

40mil

Place near Pin39

2

Headphone Out

C487

1

2

+PVDD1_HDA

2

C760
10U_0805_10V4Z

2

330P_0402_50V7K
1

1

0.1U_0402_16V4Z
1
1
C765

2

JHP1
330P_0402_50V7K

L28 2
1
FBMA-L11-201209-221LMA30T_0805

5

6
SINGA_2SJ-A960-C01
CONN@

SM010004010 300ma 70ohm@100mhz DCR 0.3

EC_MUTE# 36

SM010015410 300ma 80ohm@100mhz DCR 0.3

4

GND

EAPD

1
R6951
R643

J16
@ JUMP_43X39
1 1
2 2

J17
@ JUMP_43X39
1 1
2 2

J18
@ JUMP_43X39
1 1
2 2

J19
@ JUMP_43X39
1 1
2 2

J20
@ JUMP_43X39
1 1
2 2

J21
@ JUMP_43X39
1 1
2 2

GNDA

GND

SENSE A
SENSE B
EAPD

PCBEEP

12

MONO_OUT
AVSS2

20
37

VREF

27

AVSS1
PVSS2
PVSS1

26
43
42

SPDIFO

7

DVSS

49

GND

CODEC_VREF C549 1
C553 1
10mil
@

2 0.1U_0402_16V4Z
2 10U_0805_10V4Z

D23

PJDLC05C_SOT23-3

AGND

1
2

1
2

G1
G2

3
4

15mil

INT_MIC_L
L31

1

2 INT_MIC_R
FBMA-L11-160808-800LMT_0603

1

2

C571
220P_0402_50V7K

ACES_88266-02001
CONN@
4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

GNDA

2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

R694
10K_0402_5%

15mil

JMIC2

Place next pin27

0927 Vender suggest remove 10U(EMI)

For EMI

Int. MIC

INT_MIC_L

ALC271X-GR_QFN48_7X7

DGND

+INTMIC_VREFO

MONO_IN

1

CPVEE

2

36

CPVEE
34
2
C768
2.2U_0402_6.3VM 10mil
SENSE_A
13
SENSE_B
18
2
47
2 20K_0402_1%
0_0402_5%
48
1

3

1
R682
39.2K_0402_1%
MIC_PLUG#
2
1
R690
20K_0402_1% MIC2JD

2

2

1

HP_PLUG#

1

2
2.4K_0402_1%

D18
RB751V-40_SOD323-2

R630
0_0603_5%

+VDDA

5
6

G1
G2

ACES_88266-04001
CONN@

MONO_IN

2

2

560_0402_5%

1U_0402_6.3V4Z

2

C527
1
1U_0402_6.3V4Z

2
B

560_0402_5%

2

20mil

SPK_L+
SPK_LSPK_R+
SPK_R-

1

40mil

R335

2

C759
10U_0805_10V4Z

0.1U_0402_16V4Z
1
1
C763
@

MCK1608301YZF_2P~N
MCK1608301YZF_2P~N
MCK1608301YZF_2P~N
MCK1608301YZF_2P~N

2
2
2
2

1

BEEP#

1U_0402_6.3V4Z

@
L51 2
1
FBMA-L11-201209-221LMA30T_0805

1
1
1
1

C

3

36

1

L53
L54
L55
L56

1

+PVDD_HDA

2

SPKL+
SPKLSPKR+
SPKR-

R367
10K_0402_5%

10K_0402_5%

C479 1

JSPK1

2
1U_0402_6.3V4Z

2

R356

1

3

D20
RB751V-40_SOD323-2

C530

2

@
4.75V
1
2
SHDN
BYP
C485
G9191-475T1U_SOT23-5 0.01U_0402_16V7K
@
4

SM010014520 3000ma 220ohm@100mhz DCR 0.04
+VDDA

Int. Speaker Conn.

2

GND

(output = 300 mA)

1

R366
10K_0402_5%

+3VS

+VDDA

2

2

5

OUT

1

2
3

40mil

1

C489
0.1U_0402_16V4Z

1

U23
IN

2

60mil 1

1

2
0_0805_5%

1

1
R348

+5VS

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

38

of

60

http://hobi-elektronika.net

A

B

C

D

E

1

1

@
1

H13
H_3P0

@
1

H3
H_3P0

@
1

H2
H_3P0

@
1

H1
H_3P0

GNDA

@

@

@

@

@

@

@

@

@

@

@

H20
H_4P2

H21
H_4P2

H22
H_4P2

@

@

@

@

@

@

@

@
1

H19
H_4P2

1

H18
H_4P0

1

H17
H_4P0

1

H16
H_3P8

1

8
7
6
5

2

H15
H_3P8

1

GND
GND
GND
GND

1

@

1

@

1

@

1

@

1

H29
H_3P3

1

H28
H_3P3

1

H24
H_3P3

APL5607KI-TRG_SO8
C569
10U_0805_10V4Z
1
2

@

@

H14
H_5P0X1P0

@

@

1

@

C567
1000P_0402_50V7K
1
2

1

H30
H_3P0N

1

+3VS

H25
H26
H27
H_6P0X3P0N H_6P0X3P0N H_6P0X3P0N

1

C568
0.1U_0402_16V4Z

1

1

2

H23
H_3P3

1

EN_DFAN1

EN
VIN
VOUT
VSET

H12
H_3P0

1

36

1
2
3
4

+VCC_FAN1
1
300_0402_5%

H11
H_3P0

10U_0805_10V4Z
2

U27

2
R451

H10
H_3P0

1

C570
1

H9
H_3P0

1

+5VS
2

H8
H_3P0

1

FAN1 Conn

1

H32
H_3P3

1

H31
H_3P3

1

H7
H_3P0

1

H6
H_3P0

1

H5
H_3P0

1

H4
H_3P0

R11
10K_0402_5%
2

40mil
36

+VCC_FAN1

FAN_SPEED1
1

C1
1000P_0402_50V7K

JFAN1
1
2
3
ACES_85205-03001
CONN@
FD1

2

1

FD4

1

FD3

1

FD2

1

3

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

@

@

@

3

@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

39

of

60

http://hobi-elektronika.net

A

B

2

JUMP_43X79

20mil
C555

+5VS_R

10U_0805_10V4Z

2
2

3

1

1

1

5VS_GATE

6
Q52A

2

+5VALW
2

+1.8VS to +1.8VSDGPU for GPU

4

+1.5VS_R

C96

DIS@

1

1
3

2

4

1

2
1
1
1

2N7002H_SOT23-3
DIS@

3

+1.5VSDGPU_R

DIS@
C118

2

1.5_VDDC_PWREN#

R114
0.1U_0603_25V7K
2 DIS@

510K_0402_5%

S 2N7002H_SOT23-3

Q11

2
R36
470_0603_5%

@
1

1

R390
470_0603_5%

+1.05VS_VTT_R

D

2
G

+1.5V

2

2

+1.8VS

R37
470_0603_5%
1

R123
470_0603_5%
DIS@

DMN66D0LDW-7_SOT363-6

+1.05VS_VTT

1

1

Q12B
DIS@

5

@

+0.75VS_R

1

Q16

6
1.5_VDDC_PWREN#

ACIN

R35
22_0603_5%

C129

Q12A
DMN66D0LDW-7_SOT363-6

1.5VSDGPU_GATE

1

R113
100K_0402_1%
DIS@

Q5
@

2

@

S 2N7002H_SOT23-3

1

10U_0603_6.3V6M
2
DIS@ 2 1U_0603_10V6K
DIS@

10mil

1

+VSB

0.1U_0603_25V7K

D

C123

SUSP

2

29,49 1.5_VDDC_PWREN#
2
G

1
2
3

10U_0603_6.3V6M
2
DIS@

20mil
C110

3

ACIN

ACIN

2

8
7
6
5

1

S

2
G

17,23,29,50,51 DGPU_PWR_EN
R233
100K_0402_5%
DIS@

D

3

R76
470_0603_5%

4

2

5

DGPU_PWR_EN#

4

SUSP

Q7B
DMN66D0LDW-7_SOT363-6

1

+1.5VSDGPU
U7
AO4430L_SO8
2

C94

1

Q7A
DMN66D0LDW-7_SOT363-6

510K_0402_5%

R65
@

2

1

4

6

R229
100K_0402_5%
DIS@

+1.5V to +1.5VSDGPU for GPU

1

10U_0603_6.3V6M
2
2
1U_0603_10V6K

1.5VS_GATE

3

R67
750K_0402_5%

10mil

1

1

2

+0.75VS

1

2N7002H_SOT23-3

+1.5V

2

15,36,43

S

23,51 DGPU_PWR_EN#
+1.5VS

0.1U_0402_16V4Z

+VSB

+5VALW
Q18

+1.5V to +1.5VS

3

20mil

SF000002M00 330U 2.5V ESR 16mohm

2

2

2

D

2
G
@

6

2

1

ACIN

0.1U_0402_16V4Z
2
10U_0603_6.3V6M

DGPU_PWR_EN#

0.1U_0603_25V7K
DIS@

510K_0402_5%

1

1

2

1

C93

2

@

5

4

1

C91

C394

1

1

R635
10K_0402_5%

2

C105

DGPU_PWR_EN#

DMN66D0LDW-7_SOT363-6
DIS@

C90

Q50B
DMN66D0LDW-7_SOT363-6

5

34,36,47,48 SUSP#

R240
Q17B

Q49A
DMN66D0LDW-7_SOT363-6

SUSP

SUSP

+1.8VSDGPU_R

Q17A
DMN66D0LDW-7_SOT363-6
DIS@
1

1

1

R241
470_0603_5%
DIS@

10U_0603_6.3V6M 1U_0603_10V6K
DIS@ 2
DIS@ 2

1.8VSDGPU_GATE

DIS@

0.1U_0603_25V7K

+1.5V
U4
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

10U_0603_6.3V6M

2
1
R239
510K_0402_5%

2

1211 EMI ADD 0.1U close PJ5

C764

+VSB

4

DMN66D0LDW-7_SOT363-6

C98

2

5

+

C701

330U_6.3V_R15M
2
DIS@

10mil

4

Q49B
SUSP

20mil

SUSP

2
1

C393

1

R640
470_0603_5%

2
1U_0603_10V6K +3VS_R

3VS_GATE

3

2
1
R641
200K_0402_5%

+VSB

10mil

C376

1

2

1

SF000002080 330U 6.3V H5.9 15mohm
47,48

1

1

C529

2

DIS@

R642
100K_0402_5%

+1.8VSDGPU

2

1

2

20mil

10U_0603_6.3V6M
2
DIS@

2
C528

10U_0603_6.3V6M

+1.8VS
U14
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
1

1

10U_0603_6.3V6M
2

2

C395

1

C531

+3VS

6 1

10U_0603_6.3V6M

+3VALW
U25
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
1
4

1

2

DMN66D0LDW-7_SOT363-6

+3VALW TO +3VS

C535

DMN66D0LDW-7_SOT363-6

R639
100K_0402_5%

0.1U_0603_25V7K

3

DMN66D0LDW-7_SOT363-6

C780

1

2

1

2

3

SUSP

Q50A
SYSON

35,36,41,46 SYSON

SUSP

5
1

2

SYSON#

35,41 SYSON#

2

10mil

1

R698
100K_0402_5%

3

2

+VSB

4

20mil

Q52B

1

1

R701
470_0603_5%

6

C781

1U_0603_10V6K
2

R637
100K_0402_5%

40mil

2

2

1

2

@ J5
1 1

1

+5VALW

+3VALW_PCH

3

2

1

1

10U_0805_10V4Z
2

C779

10U_0805_10V4Z

4

C782

+3VALW

C556
1U_0603_10V6K

1

E

+3VALW TO +3VALW(PCH AUX Power)

+5VS

C554
10U_0805_10V4Z

C783
10U_0805_10V4Z

D

1

+5VALW TO +5VS
+5VALW
U39
DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5
1

C

+1.8VS_R

+1.5V_R

2
G

Q3

2
G

SUSP

S
2N7002H_SOT23-3

3

3

S
2N7002H_SOT23-3

SUSP

1

D
Q24

D
2
G

S

2N7002H_SOT23-3

SUSP

Q2

2
G

SYSON#

@S

3

Q1

D

3

D

1

1

4

1

4

2N7002H_SOT23-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/08/14
CP_S3PowerReduction
WhitePaper_Rev0.9
0.75VS speed up discharge

2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

40

of

60

http://hobi-elektronika.net
B

A1
A2
A3
A4
A5
A7
A9
A11
A13
A14
B3
B4
B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11

Pin compare table for support USB remote wakeup or not

pull high
10k to VDD33

Not support USB Tied to GND
remote wakeup
A

P13

D7

2 U3TXDN2
0_0402_5%

U3RXDP2_L

@
1
R246

2 U3RXDP2
0_0402_5%

U3RXDN2_L

@
1
R247

2 U3RXDN2
0_0402_5%

U2DN2_L

@
1
R244

2 U2DN2
0_0402_5%

U2DP2_L

@
1
R245

2 U2DP2
0_0402_5%

3

4

4

U3RXDN2

SUPERWORLD OCE2012120YZF_0805
USB3@
L17
U2DN2
2 2
1 1
3

3

4

4

U2DP2

+USB3_VCCA

U2DP2
U3RXDP2

P8
B8

U3RXDN2

A8

U3RXDN2_L

U3TX_C_DP2

6

I/O4

I/O1

1

5

REF2 REF1

2

4

I/O3

3

Must use 24MHz crystal: mount
Y5,R816,C879,C880

pull high
to VDD33

Can use either 48MHz or 24MHz When
use 48MHz clock: mount R22,R25

I/O2

U2DP2

PJUSB208H_SOT23-6

1

For USB3.0 ESD diode
D32

+3V_USB3.0

R311
G14 USB_OC2#_R 1 USB3@ 2 10K_0402_5%
H13 OCI1B R303 1 USB3@ 2 10K_0402_5%

U3TXDP2

1

10

U3TXDP2

U3TXDN2

2

9

U3TXDN2

U3RXDP2

4

7

U3RXDP2

U3RXDN2

5

6

U3RXDN2

2

3
PPON2
PPON1

PCI Express/ExpressCard select signal
1:others
0:Express Card or Mini card

GND
GND
GND

H14
J14

8
RCLAMP0524P.TCT~D
USB3@

SPISCK
SPISCB
SPISI
SPISO

B10

U3TXDN1
U2DM1

A10
N10

U2DP1
U3RXDP1

P10
B12

U3RXDN1

A12

As short as possible

RREF
GND

GND

P12 USB3_REF
N12

GND

N11

GND

D6

+3VALW
+USB3_VCCA
+5VALW

R261
1.6K_0402_1%
1
2
USB3@

C738
.1U_0402_16V7K
1
2
35,40

SYSON#

SYSON#

W=100mils

U34
1
2
3
4

GND
VIN
VIN
EN

R594
100K_0402_5% USB2@

8
7
6
5

VOUT
VOUT
VOUT
FLG

USB_OC2#_R

AP2301MPG-13_MSOP8

XT1
XT2

R595 1

CSEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

CLK

Tied to GND

1

D29
U2DN2

@

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6

17
17

USB20_N1
USB20_P1

USB20_N1

1

USB20_P1

4

1

2 0_0402_5%

4

USB3@

UPD720200AF1-DAP-A_FBGA176

3

USB2@
3

1

C740

@
U2DP2

2

0.1U_0402_16V4Z

Resister overlap with L70

USB2.0 Conn SKU
+USB3_VCCA
+USB3_VCCA

SF000002Y00 220U
6.3V 17mohm H4.5

W=100mils
1
+
2

1

2

U2DN2
U2DP2

JUSB2
1
2
3
4

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4
SUYIN_020173GB004M25MZL
CONN@

USB2.0 Conn

Compal Electronics, Inc.

Compal Secret Data
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

B

C

4

P/N: SA000048H10 (S IC UPD720200AF1-DAP-SSA-A FBGA USB3.0)

Security Classification
Issued Date

2

3

USB_OC2# 17

USB2@

U2DN2

2

2
R593
0_0402_5%

WCM2012F2SF-670T04_0805
1
2
R596
@
0_0402_5%

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

24MHZ_12PF_X5H024000DC1H
USB3@
1
1
C417
C428
12P_0402_50V8J
12P_0402_50V8J
USB3@
USB3@
2
2

Support USB
remote wakeup

@
1
R243

9

2

Place as close as
possibile to
U41.N14 and U41.M14

AUXDET(Pin J2) CSEL(Pin P6)

U3TXDN2_L

For USB2.0 ESD diode

A6
N8

C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

4

U3TXDN2

C739
470P_0402_50V7K

1

+3V_USB3.0
R291
100_0402_5%
USB3@

2

4

220U_6.3V_M
C719

USB3_XT1
USB3_XT2

1

U2AVDD10

U3AVDO33

H11
K11
K12
L8
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10

H3
H4
L5

E11
E12
VDD10
VDD10

E3
E4
VDD10
VDD10

C8
C9
D8
D9
VDD10
VDD10
VDD10
VDD10

C4
C5
C6
C7
D5
VDD10
VDD10
VDD10
VDD10
VDD10

N4
N5
N6
P3
VDD33
VDD33
VDD33
VDD33

L13
L14
VDD33
VDD33

L9
L10
VDD33
VDD33

F3
G3
G4
VDD33
VDD33
VDD33

D10
F13
F14
VDD33
VDD33
VDD33
2
1

2
1

MX25L5121EMC-20G
USB3@

Y1

4

L47
SPI_CS_USB#
USB_SI_SPI_SO

R255
0_0402_5%

1
2
3
4

3

1
P6

R254
0_0402_5%

CS#
SO
WP#
GND

U3TXDN2_L 3

WCM2012F2S-900T04_0805
USB3@

U3TXDN2
U2DM2

USB3@ USB3@

VCC
HOLD#
SCK
SI

2 U3TXDP2
0_0402_5%

1

1
2

USB3@
R266
47K_0402_5%

U17

8
7
SPI_CLK_USB
6
USB_SO_SPI_SI 5

@
1
R242

2

GND
1

USB3@
R264
10K_0402_5%

U3TXDP2_L

1

2

C415
.1U_0402_16V7K
USB3@

1

2
1

R265
10K_0402_5%

1

USB3_XT1 N14
USB3_XT2 M14

2

2

+3V_USB3.0

USB3@

.1U_0402_16V7K

3

U3TXDP2

U2DP2_L

C459.1U_0402_16V7K
2 U3TXDP2_L
USB3@
U3TX_C_DN2 1
2 U3TXDN2_L
U2DN2_L
USB3@
C458.1U_0402_16V7K
U2DP2_L
U3RXDP2_L

+3V_USB3.0
+3V_USB3.0

.1U_0402_16V7K

C14

C450

K13
K14
J13

.1U_0402_16V7K

C413
1U_0603_10V6K
USB3@ 2

C466

PONRSTB

.1U_0402_16V7K

SPI_CLK_USB
M2
SPI_CS_USB#
N2
USB_SO_SPI_SI N1
USB_SI_SPI_SO M1

1

+3V_USB3.0
+3VA_USB3.0
L19
BLM18AG601SN1D_2P
1
2
USB3@
1
C397
10U_0805_6.3V6M
USB3@
2

B6

OCI2B
OCI1B

1

U2DN2_L

U3TXDP2

Can be attach to EC, either.

2

U3RXDN2_L 3

+3VA_USB3.0

U3TXDP1

1
2
D10 1 2
USB3@
1SS355TE-17_SOD323-2 1

C407

+3V_USB3.0

P5

.1U_0402_16V7K

R275 1 USB3@ 2 10K_0402_5%

AUXDET
PSEL
SMI
SMIB

C460

SMIB

R283 1
R294 1

USB3@ 2 10K_0402_1%
@
2 100_0402_1% J2
USB3@ 2 10K_0402_5% J1
0_0402_5%
SMI_R
H1
0_0402_5%
SMIB_R
P4

.1U_0402_16V7K

+3V_USB3.0
18,35

+1.05VR

U3TXDP2_L 2

SUPERWORLD OCE2012120YZF_0805
USB3@
L18
U3RXDP2_L 2
U3RXDP2
2
1 1

7K for customer request, can use other kind
of capacitor, like Y5V.

R325
0_0805_5%
1
2
USB3@

SPEC Max:+3V---200mA;+1.05V---800mA
Idle mode:0.489W:
+3V---43mA;+1.05V---328mA
D3 mode:0.066W:
+3V---5.4mA;+1.05V---45mA

PERSTB
PEWAKEB
PECREQB

C461

+3V_USB3.0

R278 1
R279 1
R284 1
USB3@
2
USB3@
2

H2
K1
K2

.1U_0402_16V7K

R295 1 USB3@ 2 0_0402_5%
R274 1 USB3@ 2 0_0402_5%

C454

PERXP
PERXN

.1U_0402_16V7K

F2
F1

C452

5,17,34,35,36 PLT_RST#
15,34,35 PCH_PCIE_WAKE#
14 USB30_CLKREQ#_L

.1U_0402_16V7K

PETXP
PETXN

PECLKP
PECLKN

C406

B2
B1
PCIE_PRX_C_DTX_P5 D2
PCIE_PRX_C_DTX_N5 D1

14 PCIE_PTX_C_DRX_P5
14 PCIE_PTX_C_DRX_N5

2

C453

14 CLK_PCIE_USB30_L
14 CLK_PCIE_USB30_L#
2 USB3@.1U_0402_16V7K
2 USB3@.1U_0402_16V7K

1
1
1
1
1
1
1
1
1
USB3@ USB3@ USB3@ USB3@

.1U_0402_16V7K

C441 1
C436 1

For EMI request

USB3@ USB3@ USB3@ USB3@ USB3@
2
2
2
2
2
2
2
2
2

U19

1
5

RT9701-PB_SOT23-5
USB3@

14 PCIE_PRX_DTX_P5
14 PCIE_PRX_DTX_N5

.1U_0402_16V7K

GND

C439

2

.1U_0402_16V7K

VIN
VOUT
VIN/CE VOUT

2

C434

3
4

+1.05V_USB3.0

2

1
USB3@

USB3@ USB3@
2
2
2
2
2
.1U_0402_16V7K

SYSON

35,36,40,46 SYSON

+3V_USB3.0
+3V_USB3.0

U16

2

C408

+3VALW

2

1
1
1
1
USB3@ USB3@

USB3@
2

.1U_0402_16V7K

+3VALW to +3V Transfer

2

1

USB3@ USB3@ USB3@
1
1

C445

2

2

1

.1U_0402_16V7K

Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05 ~ 1.1025

1 USB3@

R306
32.4K_0402_1%
USB3@

USB3@ USB3@ USB3@
1
1

C431

2

APL5930KAI-TRG_SO8
USB3@

1

R313 USB3@
1
2
10K_0402_1%

C410
8P_0402_50V8D

FB

3
4

C403
0.01U_0402_16V7K

EN
POK

VOUT
VOUT

C437
10U_0603_6.3V6M

SYSON
8
7
2
1
R343 5.1K_0402_1%
USB3@

C402
.1U_0402_16V7K

VCNTL
VIN
VIN

E

L16

+3VA_USB3.0

C456
8P_0402_50V8D

+5VALW

+3VA_USB3.0

C457
0.01U_0402_16V7K

6
5
9

+1.05VR

Close to U41.P13

C409

+1.5V

Close to U41.D7

+1.05V_USB3.0

U20

C455
.1U_0402_16V7K

2

C500
10U_0603_6.3V6M

1

C503
1U_0603_10V6K

2

+5VALW

D

+3V_USB3.0

+1.5V to +1.05V Transfer
+5VALW
+1.5V
USB3@
USB3@
1
1

C

EPAD

A

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

41

of

60

http://hobi-elektronika.net

A

B

@PJP1
@
PJP1
ACES_50305-00441-001

C

VIN

PL1
SMB3025500YA_2P
1
2

1
2
3
4
GND
GND

D

E

@PJ3
@
PJ3

+3VALWP

2

2

1

1

+3VALW

+0.75VSP

PJ7
JUMP_43X39@
2 2
1 1

+0.75VS

2

PC2
100P_0402_50V8J

1
PC3
100P_0402_50V8J

PC4
1000P_0402_50V7K

2

1

1

2

PC1
1000P_0402_50V7K

2

1

JUMP_43X118

@PJ6
@
PJ6
+5VALWP

3

2

1

2

@ PJ4
1

1

+5VALW

+VCCSAP

2

JUMP_43X118

PJ31
@JUMP_43X39
1 1
2 2

PD11 @
PJSOT24CH_SOT23-3

2

2

1

+VCCSA

1

1

JUMP_43X118

1

@ PJ14
2

2

1

1

JUMP_43X118
VIN

@PJ13
@
PJ13

2

+1.8VSP

2

1
2

37

1

51ON#

2

1

2

1

1

1

+VGA_CORE

2

1

1

JUMP_43X118

1

@PJ12
@
PJ12

VS

+1.5VP

2

2

2

2

JUMP_43X118

2

1

@ PJ8
+1.5V

1

+VSBP

1

JUMP_43X118

1

2

2

+VSB

JUMP_43X39

1
@ PJ21
PC6
0.1U_0603_25V7K

2

2

1

1

2

JUMP_43X118

2

1

3

2

JUMP_43X118
PR2
68_1206_5%

@PJ9
@
PJ9

2

1
PR3
100K_0402_5%

2

PC5
0.22U_0603_25V7K
2
1

N1

+VGA_COREP

@ PJ22

PR1
68_1206_5%
PQ1
TP0610K-T1-E3_SOT23-3

@ PJ15
+1.8VS

1

@PJ10
@
PJ10
2

1

BATT+

1

JUMP_43X118

PD1
LL4148_LL34-2
PD2
LL4148_LL34-2
2
1

2

2

2

2

1

@ PJ19

1
+VGFX_COREP

JUMP_43X118

PR4
22K_0402_5%

2

2

1

1

+VGFX_CORE

JUMP_43X118
@PJ11
@
PJ11
+1.05VS_VTTP

2

2

1

+1.05VS_VTT

1

JUMP_43X118

@PJ30
@
PJ30
+VDDCIP

2

2

1

+VDDCI

1

JUMP_43X118

PreCHG

@ PD3
LL4148_LL34-2

@

3

1

@ PR15
1K_1206_5%
1
2

12

@ PR16
100K_0402_5%
1

+5VALWP

2

2

3

44

@ PD10
BAS40CW_SOT323-3
2
1
3

ACOFF

+CHGRTC

+CHGRTC

PR6
0_0603_5%
1

2

@ PQ3
@PQ3
PDTC115EU_SOT323-3

@ PQ4
PDTC115EU_SOT323-3
3

36,43

B+

1

2

PR13
1

@

2

@ PR14
1K_1206_5%
1
2

100K_0402_5%

3

PR12
1

@ PR10
1K_1206_5%
1
2

3

@ PQ2
TP0610K-T1-E3_SOT23-3

1

2

2

100K_0402_5%

@ PR8
1K_1206_5%
1
2

VIN

+3VLP

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

42

of

60

http://hobi-elektronika.net
B

C

D

PC1097
10U_1206_25V6M
1
2

ADP_I = 19.9*Iadapter*Rsense

1 2
2
G
65W90W@ PQ20
2N7002W-T/R7_SOT323-3

36 CALIBRATE#

CP mode, for Acer spec, CP=0.85*Iadapter.

7

ICM

PHASE

18

D

1
2
PR51
15.4K_0402_1%

CHLIM

BOOT

16

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

12

GND

PGND

13

4
2ACOFF

2

PR49
4.7_0603_5%
PC33
4.7U_0603_6.3V6M

1

1
3

PC26
2200P_0402_50V7K
2
1

1
3

PC21
0.1U_0603_25V7K
2
1

1

1

2

3

6251VDD

1

1

PR55
10K_0402_1%
1
2

2

ACIN

15,36,40

PACIN

1

1

2

PR54
10K_0402_1%

12.60V

2

ACPRN

2
PQ21
PDTC115EU_SOT323-3

3

CC=0.6~4.48A

PR56
14.3K_0402_1%

IREF=0.43V~3.24V

Kv
Rinternal ic=514K Rec=3K R1=PR379=15.4K
R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
A=Vref*(R/(R+514K))=0.052
Kv=9.451

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

BATT+

4 PR41
0.02_1206_1%
3

ISL6251AHAZ-T_QSOP24
120W@ PR50 51.1K_0402_1%

1

CV mode

IREF=0.7224*Icharge

Ki
Vchlim=Iref*(PR46/(PR44+PR46))
=Iref*(100K/(80.6K+100K))
=Iref*0.5537
Ichanrge=(165mV/PR22)*(Vchlim/3.3V)
=(165m/20m)*(1/3.3V)*Iref*0.5537
=1.3842*Iref
Iref=0.7224*Ichanrge =>Ki=0.7224

4

26251VDD

1

2

DL_CHG

PQ18
AO4466L_SO8

PD9
RB751V-40_SOD323-2

PR53
47K_0402_5%

Charging Voltage
(0x15)

4

PR102
100K_0402_5%
2 V1

1
PC28
0.1U_0603_25V7K
BST_CHGA 2
1

6251VDDP

For 120W
Iinput=(1/0.01)(0.05*Vaclm/2.39+0.05)
Vaclm=2.344V, Iinput=5.403

12600mV

PC15
2200P_0402_25V7K
2
1

3

PR45
2.2_0603_5%
BST_CHG 1
2

2

9

DH_CHG

1

17

1

PR52
31.6K_0402_1%

For 65W, 65W/90W#=High
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=0.376, Iinput=2.89A.

Normal 3S LI-ON Cells

PC14
0.1U_0603_25V7K
2
1

1
2
1
2

5
6
7
8
UGATE

1

VREF

<40,41>

TCR=50ppm / C
PL2
10UH_PCMB104T-100MS_6A_20%
CHG
1
2

S

For 90W, 65W/90W#=Low, Vref=2.39V
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.489V, Iinput=4.05A

BATT Type

2

4

2

6251aclim

8

S

PC32
10U_1206_25V6M
2
1

19

PQ13
2N7002W-T/R7_SOT323-3
2 PACIN
G

PC31
10U_1206_25V6M
2
1

CSIP

@

D

PQ16
AO4466L_SO8

1

VCOMP

2

65W90W@ PR48
2.55K_0402_1%

36,45 65W/90W#

65W/ Iadapter=3.42A
90W/ Iadapter=4.74A
120W/ Iadapter=6.32A

20

CSOP

3
2
1

65W90W@ PR47 12.1K_0402_1%
6251VREF 1
2
120W@ PR47 1K_0402_1%

3

PQ19
PDTC115EU_SOT323-3

CSIN

1

2

2

ACOFF

ADP_I

3

ACOFF

2

PC22
0.047U_0402_16V7K
1
2
PR36
20_0402_5%
2
1
PR37
20_0402_5%
PC24
0.1U_0603_25V7K
1
2
PR39
2_0402_5%
LX_CHG

1

PR46
100K_0402_1%

PC29
0.01U_0402_25V7K
2
1

1

1

PR44
80.6K_0402_1%
2
1

ICOMP

6

PR38
1

S

PR42
4.7_1206_5%

PC23 6800P_0402_25V7K
5
1
2

D

PD8
1SS355_SOD323-2
2

PC30
680P_0402_50V7K

21

1

@ PQ27
2N7002W-T/R7_SOT323-3

3
2
1

CSOP

PD5
1SS355_SOD323-2

ACPRN
2
G

ACPRN 44

CSON

PR28
200K_0402_1%

2

PQ11
PDTC115EU_SOT323-3

PR35
20_0402_5%
1
2

1

VIN

5
6
7
8

CSON

CELLS

0.01U_0402_25V7K
10K_0402_1%
1
2
PR40 100_0402_1%
1
2
6251VREF
PC27 .1U_0402_16V7K

36,45

@

PC20
DCIN 2
1

2

1
PR34

EN

4

PR23
47K_0402_1%
1
2

2

S

1
2
6251_EN 3

2
1
65W90W@ PR50
20K_0402_1%

6
1

G

IREF

23
22

PC25
1
2

PR43
47K_0402_5%
PACIN 1
2

36

3

PQ14A
DMN66D0LDW-7_SOT363-6

D

ACSET ACPRN

VDD

2

3S/4S#

PQ14B
DMN66D0LDW-7_SOT363-6

DCIN

24

PR30
14.3K_0402_1%

0.1U_0603_25V7K
ACSETIN 2

S

2

3

1

PR27
10K_0402_1%
1
2

ACSETIN

1

36

@ PR26
PR704 191K_0402_1%
191K_0402_1%

PD6
RB751V-40_SOD323-2

PU2

2

1

PQ15
PDTC115EU_SOT323-3

2

36,42

FSTCHG

2

PQ12
PDTC115EU_SOT323-3

PR31
0_0402_5%
2
1

PR33 47K_0402_5%
1
2

6251VDD
PR32
150K_0402_1%

3

3
G
4

5

0.01_2512_1%
6251VDD

100K_0402_1%

1

1

V1

1

36
PQ10
PDTA144EU_SOT323-3

2
D

VIN PreCHG

120W@ PR22

47K

CHG_B+

8
7
6
5

CSIN
CSIP

PC18
1000P_0402_50V7K 2
2
1

2

3

PR29
10_1206_5%
2
1 1

47K

PR25
200K_0402_1%

2

PL29
MCK3225201YZF_2P
1
2

1
2
3

2

1
3

2

2

PR24
200K_0402_1%

4

1

4
PC16
0.1U_0603_25V7K
2
1

1

1

B+

1

PC13
10U_1206_25V6M
2
1

8
7
6
5
PC11
5600P_0402_25V7K
1
2

1
2
3

65W90W@ PR22
0.02_2512_1%

P3

PQ8
AO4407A_SO8

1
2
3

4

8
7
6
5

PC17
2.2U_0603_6.3V6K
2
1

P2

PQ7
AO4407A_SO8

VIN

E

PQ9
AO4407A_SO8

PC1098
10U_1206_25V6M
1
2
PL30
1.2UH_1127AS-1R2N_2.4A_30%
1
2

PC12
10U_1206_25V6M
2
1

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

43

of

60

http://hobi-elektronika.net

A

B

C

D

E

45

5
6
7
8

PC42
2200P_0402_50V7K
2
1

SPOK

PC43
0.1U_0603_25V7K
2
1

PC41
4.7U_0805_25V6-K
2
1

ENTRIP1
1

3

2
FB1

REF

4

6

5

PR62
154K_0402_1%
2

ENTRIP1

P PAD

TONSEL

25

1

FB2

PU3

2

PQ22
AO4466L_SO8

PR61
110K_0402_1%
1
2

RT8205_B+

PC40
4.7U_0805_25V6-K
2
1

PR60
20K_0402_1%
1
2

ENTRIP2

PR59
20K_0402_1%
1
2

1

PC44
4.7U_0805_10V6K

8
7
6
5

PQ23
AO4466L_SO8

4

4

22

UGATE2

UGATE1

21

UG_5V

11

PHASE2

PHASE1

20

LX_5V

LG_3V

12

LGATE2

LGATE1

19

LG_5V

1

1
5
6
7
8
2
1
3
2
1

PC52
4.7U_0805_10V6K

1
2

1
2

@ PR66
4.7_1206_5%

NC
18

VIN

VREG5
17

16

GND

EN

SKIPSEL
14

13

15

2
1
PC53
0.1U_0603_25V7K

4

+
2

3

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

1
2

+3.3VALWP
Ipeak=4.64A ; 1.2Ipeak=5.57A=Iocpmin; Imax=3.25A
f=375KHz, L=4.7UH
Rdson=15 18m ohm
1/2Delta I = 1/2 *(19-3.3)*(3.3/19)/(375KHz*4.7UH)=0.773A
Vlimit=(10uA*110Kohm)/10=0.11V
Ilimitmin=0.11/(18m*1.2)=5.09A
Ilimitmax=0.11/(15m*1.2)=6.11A
Iocp=5.863A 6.883A

+5VALWP
Ibudget=8.4A =>7AIpeak=7A 1.2Ipeak=8.4A; Imax=4.9A
f=300KHz, L=4.7UH,Rentrip=221K ohm
Rdson=15 18m ohm
1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A
Vlimitmin=(10uA*154Kohm)/10=0.154V
limitmin=0.154V/(18m*1.2)=7.12A
Ilimitmax=0.221/(15m*1.2)=8.55A
Iocp=8.44A 9.86A

3

3

PC54
2.2U_0603_6.3V6K

2

1

2
2
1
PR72
40.2K_0402_1%

1
3

220U_6.3VM_R15

~

1

RT8205_B+

1
PC48

~

1

PR71
100K_0402_1%

PQ45
PDTC115EU_SOT323-3

2

S

PQ28
PDTC115EU_SOT323-3

VS

2VREF_8205

PQ26A
DMN66D0LDW-7_SOT363-6

VL

Typ: 175mA

~

EC_ON

S

4

~

36,37

D

RT8205EGQW_WQFN24_4X4

+5VALWP

PR70
100K_0402_1%
2
1

VL

ACPRN

D

G

PR637
0_0402_5%
2
1

2N7002W-T/R7_SOT323-3
PQ34
PR640
200K_0402_5%
2
1
2
G

PL5
4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A
1
2

AO4712_SO8
PQ25
PC51
1U_0603_10V6K
2
1

ENTRIP2

5

PR68
100K_0402_1%

ENTRIP1

2

MAINPWON

VFB=2.0V

2

1
2
3

PR67
499K_0402_1%
1
2

S

45

BOOT2

B+

G

3

9

4

6

3

D
PQ26B
DMN66D0LDW-7_SOT363-6

VREG3

PR636 @
0_0402_5%
2
1

MAINPWON

+
2

43

PQ24
AO4712_SO8

@ PC49
680P_0402_50V7K
2
1

PC47
220U_6.3VM_R15

BOOT1

2

10

1
2
3
1

PGOOD

23

1
2 1
2
2.2_0603_5%
UG_3V
PC45
0.1U_0603_25V7K
LX_3V

BST_3V

8
7
6
5

@ PR65
4.7_1206_5%
2
1

+3VALWP

24

PR64
PC46
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

PR63

PL4
4.7UH +-20% FDSD0630-H-4R7M=P3 5.5A
1
2

VO1

VO2

8

3
2
1

7

2

@ PC50
680P_0402_50V7K

PC39
2200P_0402_50V7K
2
1

PC38
4.7U_0805_25V6-K
2
1

@

PR58
30K_0402_1%
1
2

Typ: 175mA +3VLP
PC37
4.7U_0805_25V6-K
2
1

PC35
680P_0402_50V7K
2
1

B+

PC36
0.1U_0603_25V7K
2
1

PL12
HCB4532KF-800T90_1812
1
2

PR57
13K_0402_1%
1
2

ENTRIP2

RT8205_B+

1

2

1

1

PC34
1U_0603_10V6K

2VREF_8205

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

44

of

60

http://hobi-elektronika.net

A

B

C

D

E

@ PJP2
SUYIN_200275GR008G13GZR
1

10
9
8
7
6
5
4
3
2
1

2

EC_SMDA
EC_SMCA
TH
PI

PR73
100_0402_1%

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 72 degree C

2

GND
GND
8
7
6
5
4
3
2
1

1

1

PR74
100_0402_1%

EC_SMB_DA1 36

VL

1

1

<40,41>
VMB
<40,41>
BATT+

PC55
0.1U_0603_25V7K

PR77
21K_0402_1%

1

2

1

PU4

@ PR79
100K_0402_1%

1

VCC TMSNS1

8

2

GND RHYST1

7

2

3

OT1 TMSNS2

6

PR81
9.53K_0402_1%

OT2 RHYST2

5

1

PR80
1K_0402_1%

4
BATT_TEMP 36

2

2

1

@ PR82
47K_0402_1%
1

G718TM1U_SOT23-8

1

1

44 MAINPWON

2

2

1

PR76
10K_0402_1%

VL

+3VALWP
2

PC57
0.01U_0402_25V7K

2

1
PR78
6.49K_0402_1%
2
1

1
PC56
1000P_0402_50V7K

2

2

1

2

EC_SMB_CK1 36
PR75
1K_0402_5%

2

PL6
SMB3025500YA_2P
1
2

PH2 @

PH1

2

100K_0402_1%_NCP15WF104F03RC
2

100K_0402_1%_NCP15WF104F03RC
PQ29
TP0610K-T1-E3_SOT23-3

3

1
2

Change 5VALW to 3VALW on DVT

PC59
0.1U_0603_25V7K

65W@ PR695
3.92K_0402_1%

2

+3VALWP
PR692
0_0402_5%
1
2

5,36 H_PROCHOT#

90W@ PR695
9.09K_0402_1%

D

@ PQ128
2N7002W-T/R7_SOT323-3
2
G

65W/90W# 36,43

S

3

PU1003
G718TM1U_SOT23-8

2

1

1
PR694
10K_0402_1%

2

PR696
100K_0402_1%

@PC1095
@
PC1095
0.1U_0603_25V7K

2

+3VS

1

@ PR703
100K_0402_1%
2
1

3

@PR693
@PR693
7.15K_0402_1%

1

PQ30
2N7002W-T/R7_SOT323-3

2

1

S

2
G

ADP_I 36,43

120W@ PR695
15.4K_0402_1%

1

VCC TMSNS1

8

2

GND RHYST1

7

1

3

OT1 TMSNS2

6

90W@ PR697
16.2K_0402_1%

4

OT2 RHYST2

5

D
PQ129
2N7002W-T/R7_SOT323-3

2
G

65W@ PR697
10.5K_0402_1%

PR698
10K_0402_1%
2

3

S

2

1

1

2

2

D

3

SPOK

1

44

PR86
1K_0402_5%
1
2

PC60
1U_0402_6.3V6K

1

3

1

PR85
100K_0402_1%

1

1
2

+VSBP

2

VL

1

PC58
0.22U_0603_25V7K

PR84
22K_0402_1%
1
2

2
1
PR83
100K_0402_1%

B+

120W@ PR697
17.4K_0402_1%

For 65W adapter==>action 70W , Recovery 54W
4

4

For 90W adapter==>action 97W , Recovery 75W
For 120W adapter==>action 135W , Recovery 100W
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

45

of

60

http://hobi-elektronika.net
C

D

PC76
4.7U_0805_25V6-K
2
1

PL18
HCB4532KF-800T90_1812
1
2

B+
PC73
680P_0402_50V7K

3
2
1

PQ33
AO4406AL_SO8

9

1

LGATE

PR100
4.7_1206_5%

PQ39
AO4456_SO8
2

15

14

10

+5VALW
DL_1.5V

1
+

PC71
330U_6.3V_R15M

2

4

RT8209MGQW_WQFN14_3P5X3P5

1

PGOOD

VDDP

+1.5VP

PC69
4.7U_0805_10V6K

PC74
680P_0402_50V7K

2

6

11

5
6
7
8

FB

LX_1.5V

CS

VFB=0.75V

3
2
1

5

DH_1.5V

12

PL9
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1
2

1

VDD

13

PHASE

2

4

UGATE

1

PR99
PC83
2.2_0603_5%
0.1U_0603_25V7K
1
2BST_1.5V-1 1
2

1

VOUT

BST_1.5V

BOOT

NC

1

TON

3

7
1

+5VALW

PR97
100_0603_5%
1
2

2

PGND

@

8

PC84 @
.1U_0402_16V7K

EN/DEM

PU6

GND

2

1

2
1

35,36,40,41 SYSON

PR98
47K_0402_5%

1

PR109
2.2_0603_5%
1
2 4

PR110
267K_0402_1%
1
2

PR108
0_0402_5%
1
2

PC75
4.7U_0805_25V6-K
2
1

5
6
7
8

1.5_51117_B+

E

1

B

2

A

2

PR112
16.5K_0402_1%

2

PC72
4.7U_0603_10V6K

PR111

1

1

2
10K_0402_1%

PR101
9.53K_0402_1%

2

2

2

+1.5VP
Ipeak=21.56A;1.2Ipeak=25.87A ;Imax=15.09A
Rton=267K, Fsw=298KHz ,Rdson=4.5~5.6mohm
Rtrip=16.5K
Iocp=25.97A~42.41A

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

46

of

60

http://hobi-elektronika.net
B

C

1
PR106
9.76K_0402_1%

1
2

1.8VSP
Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A
Vout=0.6*(1+(20K/10K))=1.8V
-DVT-

1

2

1
2

1
2

PC78
680P_0603_50V7K

PC79
.1U_0402_16V7K

2
3

S

PR103
1M_0402_5%
@

1

1

D

SY8033BDBC_DFN10_3X3

PC81
22U_0805_6.3VAM

2

FB_1.8V

1

NC

FB=0.6Volt

1

11

PR105
20K_0402_1%

PC80
22U_0805_6.3VAM

6

E

+1.8VSP

PC77
68P_0402_50V8J
2
1

FB

1

3

2

LX

D

PL11
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

LX_1.8V

1

2

2

EN

LX

PR107
4.7_1206_5%

SVIN

5

PG

8

2

PQ131
2N7002W-T/R7_SOT323-3
2
G

40,48 SUSP

PVIN

EN_1.8V

1
PR104
510K_0402_5%

34,36,40,48 SUSP#

9
PC82
22U_0805_6.3VAM

2
1

PVIN

NC

JUMP_43X118

10

TP

1

1

1

@

2

4

PU7

PJ20

2

+5VALW

7

A

B+

PR159
267K_0402_1%
1
2

PHASE

12

LX_VCCSAP

CS

11

0_0402_5%
PR117
1

LG_VCCSAP

SA_PGOOD 36

PC109
4.7U_0805_10V6K

+

1

2

PC105
330U_6.3V_R15M

2

2
PR125
0_0402_5%

@ PC113
470P_0603_50V8J

PR147
1
0_0402_5%

1

RT8209MGQW_WQFN14_3P5X3P5

1

10
9

2

VDDP
LGATE

1

PGOOD

PQ47
IRFH3707TRPBF_PQFN8-3
4
PR153
12.1K_0402_1%

2

2

1
@ PR151
4.7_1206_5%

+5VALW

2

FB

6

PGND

5

7

1
2
PR137
10K_0402_5%

PC106
4.7U_0603_6.3V6K

2

1

Layout Note:
Place near V5FILT Pin

+3VS

8

PR149
100_0603_1%
1
2

+5VALW

VDD

GND

4

+VCCSAP

1

UG_VCCSAP

1

NC

1

15

14

13

2

VOUT

UGATE

2

PL10
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1
2

5

3

BOOT

1
2

TON

PR156
PC111
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_VCCSAP-1
1
2

2

PC112
@.1U_0402_16V7K

2

EN/DEM

PU12

@ PR135
47K_0402_5%

1

3
2
1

BST_VCCSAP

1

48 VCCPPWRGOOD

1

4

EN_VCCSAP
PR164
0_0402_5%
1
2

2

2

VSSSA_SENSE 9

3
2
1

2

JUMP_43X118

PC110
4.7U_0805_25V6-K

PQ46
SIS412DN-T1-GE3_POWERPAK8-5

2

PC107
4.7U_0805_25V6-K

2

5

1

@PJ24
@
PJ24
51117_VCCSAP_B+

PR160
2K_0402_1%
1
2

PR162

1

2

VFB=0.75V

VCCSA_SENSE 9

10_0402_5%
3

+VCCSAP
Ipeak=6A , Imax=4.2A, 1.2Ipeak=7.2A
DCR= 9 m(typ)~10 m(max)
Rlimit=12.1K,Rdson=14.5~17.9mohm
Iocp=7.24A~12.59A

3

1

1

+3VS

PR283
15K_0402_1%

2

PQ65
PMBT2222A_SOT23-3

2

1
0_0402_5%

VCCSA_VID1 9
@ PR580
@PR580
10K_0402_5%

2

3

2
PR585

1

@ PR280
@PR280
100K_0402_5%

1

@ PC179
4700P_0402_25V7K

2

2

2

3

S

1

D

PR282
10K_0402_5%
2
1

1

PR150
30K_0402_1%

1

1

2

PR281
10K_0402_5%

PQ64
2N7002W-T/R7_SOT323-3
2
G

4

VID[0]
0
0
1
1

VID[1]
0
1
1
1

VCCSA Vout
0.9 V
0.8 V
0.75V
0.65V

Require on 2011/ 2012 Required
Yes/Yes
Yes/Yes
No/Yes
No/Yes

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

47

of

60

http://hobi-elektronika.net

A

B

C

D

E

1

1

PU8
VIN

VCNTL

6

2

GND

NC

5

3

VREF

NC

7

NC

8

TP

9

+3VALW
PC91
1U_0603_10V6K

2

PR126
1K_0402_1%

4

VOUT

2

1

PC90
4.7U_0805_6.3V6K

1

1

2

+1.5V

@ PJ18
JUMP_43X118
1
2 2

1

1

2

PQ35
2N7002W-T/R7_SOT323-3

+0.75VSP
1

S

PR128
1K_0402_1%

PC94
10U_0603_6.3V6M

2

D

2
G

PC92
.1U_0402_16V7K
2
1

1

SUSP

1

PQ36
2N7002W-T/R7_SOT323-3

S

3

1

D

2
G

2

PC93
.1U_0402_16V7K

1

PR127
267K_0402_1%
1
2

40,47 SUSP

3

G2992F1U SO 8P

For shortage changed

2

5
6
7
8
PR130
680K_0402_5%
1
2

@ PC97
@PC97
680P_0402_50V7K

9

4

+

PC101
680P_0402_50V7K

RT8209MGQW_WQFN14_3P5X3P5
PR136
10.7K_0402_1%

PC103
4.7U_0805_10V6K

Change PR133 from 10 to
0ohm
Change PR144 from
0 to 10ohm

2

2

PC102
4.7U_0603_10V6K

3

PC100
330U_6.3V_R15M

2

PR133
0_0402_5%

2
1

8

7

3
2
1

DL_1.05VS_VCCP

1
2

LGATE

+5VALW

PR132
4.7_1206_5%

PQ40
AO4456_SO8

1

NC

14

10

1

PGOOD

VDDP

VFB=0.75V

+1.05VS_VTTP

1

1 2

6

LX_1.05VS_VCCP

11

5
6
7
8

FB

12

CS

2

3
2
1

5

PHASE

PL19
1UH_FDUE1040D-1R0M-P3_21.3A_20%

1

VDD

13

DH_1.05VS_VCCP

2

VOUT

4

BOOT

3

PR131
PC98
2.2_0603_5% 0.1U_0603_25V7K
BST_1.05VS_VCCP 1
2
1
2

UGATE

PGND

PR134
100_0603_5%
1
2

1

TON

1

+5VALW

2

S

3

EN/DEM

PU9

GND

PC99
.1U_0402_16V7K

15

1

1
@ PR702
47K_0402_5%

2

D

PQ37
AO4406AL_SO8
4

2
3

PQ130
2N7002W-T/R7_SOT323-3
SUSP
2
G

1

34,36,40,47 SUSP#

PR129
267K_0402_1%
1
2

B+
PL16
HCB4532KF-800T90_1812
1
2
1

1.05VS_51117_B+

2

PC95
4.7U_0805_25V6-K
2
1
PC96
4.7U_0805_25V6-K
2
1

2

PR141
4.02K_0402_1%
1
2
PR144
10_0402_5%
2
1

1

VCCPPWRGOOD

PR145
1

2

VCCIO_SENSE 8

+3VALW

10K_0402_1%
2

2

47
PR142
10K_0402_1%

1

PR146 @
10K_0402_1%

4

4

+1.05VS_VTTP:
Ipeak=14.05A;Imax=9.84A;1.2Ipeak=16.86A
Rdson=4.5~5.6m ohm ; Freq=298KHz
Rtrip=10.7Kohm,Vtrip<200mV
Iocp=16.99A~27.73A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

48

of

60

http://hobi-elektronika.net

A

B

C

D

E

5
10

VGA@ PR660
2.2_0603_5%
BST_VGA 1
2

DRVH

9

UG_VGA

SW

8

SW_VGA

V5IN

7

V5IN_VGA

DRVL

6

LG_VGA

5

RF

TP

11
2

TPS51218DSCR_SON10_3X3

VGA@ PQ124
TPCA8057-H 1N PPAK56-8
PC1086
1U_0603_6.3V6M
4

1
2

3
2
1

2
G
3

VGA@ PC1082
10U_0805_25V6K
2
1

VGA@ PC1083
10U_0805_25V6K
2
1

VGA@ PR667
0_0402_5%
1
2
GCORE_SEN

5.9K_0402_1%
SEY@ PR669

VGA@ PC1094
470U_V_2.5VM

+

1
VGA@ PC1093
470U_V_2.5VM

2

+
2

25

2

GRA@ PR669
5.9K_0402_1%

@

8057H 2.6 mohm(typ) 3.2 mohm(max)

S

1

VGA@ PR665
10_0402_1%

GW@ PQ123
TPCA8057-H 1N PPAK56-8

4

3
2
1

D

WHI@ PR669

@

2

VGA@ PR666
200K_0402_1%

+VGA_COREP

1

RF_VGA

+5VALW

2

VFB

1

4

5.9K_0402_1%

2

FB_VGA

VGA@ PL27
.36UH +-20% MMD-12CE-R36M-M1L 34A
1
2

1

EN

PR663
4.7_1206_5%

TRIP

3

2

2

EN_VGA

PC1089
680P_0603_50V8J

TRIP_VGA

VGA@ PC1084
0.1U_0603_25V7K
1
2

5

VBST

5

PGOOD

1

1

1

1

VGA@ PC1085
0.1U_0402_10V7K

2
1

3
2
1

4

2

4

2
VGA@ PR662
10K_0402_5%
1
2

29,40 1.5_VDDC_PWREN#

1

VGA_PWROK 18,29

GRA@ PR661
64.9K_0402_1%
1
2

VGA@ PQ127
2N7002W-T/R7_SOT323-3

B+

GRA@ PQ122
TPCA8065-H 1N PPAK56-8

3
2
1

1

VGA@ PR659
10K_0402_5%

1

SEY@ PR661
40.2K_0402_1%

VGA@ PQ121
TPCA8065-H 1N PPAK56-8

PU1002 VGA@

2

2
PL31
HCB4532KF-800T90_1812

+3VS

@ PR657
10K_0402_5%

29 1.5_VDDC_PWREN

VGA@ PC1081
0.1U_0603_25V7K
2
1

WHI@ PR661
36.5K_0402_1%
+3VS

1

5

1

VGA@ PC1080
2200P_0402_25V7K
2
1

+VGA_COREP_B+

FB=0.7V

4

GPIO 15

GPIO 20

Whistler

Seymour

GPU_VID0

GPU_VID1

Core Voltage Level

Core Voltage Level

Core Voltage Level

1

1

0.85V

0.85V(0.855V)

0.90V

0

1

0.9V

0.9V(0.930V)

0.95V

1

0

1.00V

1.00V(1.025V)

1.00V

0

0

1.1V(1.100V)

1.05V

For Granville
1/2Delta I=4.05A
Vtrip=Rtrip*Itrip=64.9K*10uA=0.649V
Iocpmin=(Vtrip/8*Rdson)+1/2Delta
=(0.649V/(8*1.6m ohm))+4.502A
=50.7A+4.05A=54.75A

2

1

+3VSDGPU

VGA@ PR685
10K_0402_5%
1
2

3

2

D

@ PR686
10K_0402_5%

3

GPU_VID1 23
VGA@ PR690
10K_0402_5%

S

VGA@ PQ126B
DMN66D0LDW-7_SOT363-6
2

VGA@ PC1092
4700P_0402_16V7K
2
1

@

G

VGA@ PR688
10K_0402_5%
5 2
1

4

S

PR689
10K_0402_5%
2
1

G

1

D
VGA@ PQ126A
DMN66D0LDW-7_SOT363-6

1

S
6

1

+3VSDGPU

VGA@ PR682
10K_0402_5%

2

VGA@ PQ125A
DMN66D0LDW-7_SOT363-6

G

27.4K_0402_1% 26.7K_0402_1%

1

D

GRA@ PR673
20.5K_0402_1%
WHI@ PR673 SEY@ PR673

2

6

GRA@ PR677
35.7K_0402_1%
54.9K_0402_1% 24.3K_0402_1%

1

1
2

@

2

VGA@ PC1091
4700P_0402_16V7K

2
1

VGA@ PC1090
820P_0402_50V7K

2

Switch freq. (RF pin setting)
47K ==>450KHz
100K ==>390KHz
200K ==>350KHz (Currently setting)
470K ==>300KHz

G

VGA@ PQ125B S
DMN66D0LDW-7_SOT363-6

VGA@ PR681
10K_0402_5%
2
1
PR684
10K_0402_5%

VGA@ PR687
10K_0402_5%

D

2

GPU_VID0
1

23

VGA@ PR683
10K_0402_5%
1
2 5

4

2

@ PR680
10K_0402_5%

3

1
3

Ipeak
Granville(35W) 47A
Whistler(25W) 27A(VDDC+VDDCI)
Seymour(15W) 14.2A(VDDC+VDDCI)

2

1
VGA@ PR676
10K_0402_5%

+3VSDGPU

1

82.5K_0402_1% 26.1K_0402_1%
SEY@ PR672 SEY@ PR677

2

GRA@ PR672
82.5K_0402_1%

2

+3VSDGPU

1

WHI@ PR677

1

WHI@ PR672

Granville

For Whistler
1/2Delta I=4.05A
Vtrip=36.5K*10uA=0.365V
Iocpmin=0.365V/(8*1.6m)+1/2Delta I=28.51A+4.05A
=32.56A
4

For Seymour
1/2Delta I=4.31A
Vtrip=40.2K*10uA=0.402V
Iocp=0.402V/(8*3.2m)+1/2Delta I
=15.70A+4.31A=20.01A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

49

of

60

http://hobi-elektronika.net

A

B

C

D

E

2

1

JUMP_43X118

GRA@ PC1071
4.7U_0805_25V6-K

1
2

5
GRA@ PQ117
SIS412DN-T1-GE3_POWERPAK8-5

1

2

GRA@ PC1070
4.7U_0805_25V6-K

@ PJ29

51117_VDDCI_B+

2

1

1

B+

1

VDDCI_SEN
GRA@ PR642
267K_0402_1%
1
2

1
RT8209MGQW_WQFN14_3P5X3P5

2

3
2
1

1

LG_VDDCI

GRA@ PR649
9.76K_0402_1%

2
@ PC1075
470P_0603_50V8J

VFB=0.75V
Vo=VFB*(1+PR650/PR653)=1.01V
Ton=19E-12*Ron*(((2/3)*Vo+150mV)/Vin)+50ns=2.4E-7
Freq=282KHz

2

GRA@ PC1076
4.7U_0805_10V6K

GRA@ PC1074
330U_6.3V_R15M

2

1

9

GRA@ PQ118
IRFH3707TRPBF_PQFN8-3
4

2

10

+

@ PR647
4.7_1206_5%

+5VALW

1

VDDP
LGATE

LX_VDDCI

5

11

3
2
1

NC

BOOT

12

CS

+VDDCIP
1

2

PGOOD

PHASE

2

GRA@ PC1077
4.7U_0603_6.3V6K

15

1

FB

6

1

Layout Note:
Place near V5FILT Pin

5

7

GRA@ PR648
100_0603_1%
1
2

+5VALW

GRA@

GRA@ PR643
10_0402_5%

GRA@ PL25
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2

UG_VDDCI

13

1

VDD

PGND

VOUT

4

2

3

GRA@ PR646
GRA@ PC1073
2.2_0603_5%
0.1U_0603_25V7K
1
2 BST_VDDCI-11
2

UGATE

8

TON

EN/DEM

2

GRA@ PC1072
.1U_0402_16V7K

2

@ PR645
47K_0402_5%

1

1

PU1001

GND

GRA@ PR644
10K_0402_1%
1
2

BST_VDDCI
14

EN_VDDCI

7,23,29,40,51 DGPU_PWR_EN

VDDCI_SEN 25

4

Cesr=15m ohm
Ipeak=4.60A Imax=2.70A 1.2Ipeak=5.52A
Delta I=((19.5-1.0)*(1.0/19.5))/(L*Freq)=1.48A
Rdson=14.5m~17.9m ohm
Iocp=5.76A~10.19A

2

GRA@ PR650
2.05K_0402_1%
1
2

1

VFB=0.75V

2

+3VALW
1

2

GRA@ PR651
2.87K_0402_1%

GPIO 6

Broadway PRO

2

VDDCI_VID

VDDCI_VID

VDDCI_VID 23

PQ119
2N7002W-T/R7_SOT323-3
GRA@

GRA@ PR655
10K_0402_5%
2

2

GRA@ PR654
10K_0402_5%
2
1

VDDCI Voltage Level

Comment

1

2

1

1

G

GRA@ PR653
5.9K_0402_1%

PR652
10K_0402_5%
@

D

S

3

0

1.00 V

1

0.90 V

Default

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

50

of

60

http://hobi-elektronika.net

A

B

C

D

E

1

1

+3VALW

VGA@ PC1079
1U_0402_6.3V6K

VGA@ PU17
G971ADJF11U SO 8P

EN
POK

3
4

FB

2

+1.0VSDGPU
2

VGA@ PR267
1.54K_0402_1%

VGA@ PC180
0.022U_0402_25V7K

VGA@ PC182
22U_0805_6.3V6M

1

1

2

GND

FB=0.8V

2

VGA@ PC181
4.7U_0603_6.3V6K

VOUT
VOUT

1

1

8
7

2

VCNTL
VIN
VIN

1

2

6
5
9

1

@ PJ28
JUMP_43X79

2

1

1

2

1

+1.5V

2

2

2

VGA@ PR268
6.04K_0402_1%

1

VGA@ PR269
15K_0402_1%
1
2
PR270
22K_0402_5%
@

1

23,40 DGPU_PWR_EN#

D

3

2

2

VGA@ PC183
1U_0402_6.3V6K

1

17,23,29,40,50 DGPU_PWR_EN

S

Ien=10uA, Vth=0.3V, notice
the res. and pull high
voltage from HW

VGA@ PQ120
2N7002W-T/R7_SOT323-3

2
G

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

51

of

60

http://hobi-elektronika.net

LGATE

4

PGND

9

3

GND

27

PHASE1

UG1

26

UGATE1

BOOT1

25

BOOT1

GFX@ PC1003
10U_1206_25V6M
2
1

GFX@ PC1002
10U_1206_25V6M
2
1

2

PC1016
680P_0402_50V7K

1 2

1

1

PR567
4.7_1206_5%
2
1
PR568
GFX@
10K_0402_1%

GFX@ PQ104
TPCA8057-H 1N PPAK56-8

3
2
1

2

3
2
1
5

@ PQ103
TPCA8057-H 1N PPAK56-8

3
2
1
3
2
1
3
2
1

PC1028
2.2U_0603_10V6K
2
1

5

PC1066 @
0.01U_0402_16V7K
+5VS

1

+CPU_CORE
QC@ PR155
2 10K_0402_1%
2
1ISEN1

2

QC@ PR158
10K_0402_1%
2
1ISEN2

QC@ PR161
1_0402_5%
2
1

VSUM-

2
1

3

PR699
10K_0402_1%

2
1

PR607
10K_0402_1%

2

PR612
1_0402_5%
1
2

PR608
3.65K_0402_1%

VSUM+ 2

ISEN2

1

3

PR606
10K_0402_1%
2
1

PR605
4.7_1206_5%

5

1
1 2

PC1045
680P_0402_50V7K

3
2
1

2.61K_0402_1%

PC1056
10U_1206_25V6M
2
1

PQ113
TPCA8065-H 1N PPAK56-8
VSUM-

4

PL24
.36UH 20% PCMC104T-R36MN1R105 30A
4
1
+CPU_CORE

Ri is PR618

2010/07/12

Deciphered Date

D

2
1

4

Compal Electronics, Inc.
2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

PR701
10K_0402_1%

2

PR624
10K_0402_1%

PR627
1_0402_5%
1
2

PR625
3.65K_0402_1%

1
VSUM+ 2

PR623
10K_0402_1%
2
1

PR622
4.7_1206_5%

1
1 2

PC1063
680P_0402_50V7K

3
2
1

Issued Date

2

Compal Secret Data

Security Classification

Rdroop is PR615

4

3

ISEN3

Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A
Rdson=3.6~4.5m ohm
DCR=1.1m ohm
HW output cap:
(1)22U_0805_6.3V *12
(2)470U_D2_2V
*2(ESR=4.5m ohm)

@

2

PC1062
0.22U_0603_10V7K
4

PQ116
TPCA8057-H 1N PPAK56-8

1

5

5

PR621
2.2_0603_5%
2
1 2

3
2
1

2

PHASE1

1

3
2
1

.1U_0402_16V7K

UGATE1

ISEN1

PH6
10KB_0603_5%_ERTJ1VR103J

PC1053
10U_1206_25V6M
2
1

CPU_B+

5

PR613

1 2

PR616
2
1
11K_0402_1%

QC@ PC1052
2
1

0.068U_0402_16V7K

0.33U_0603_10V7K

@ PR619
100_0402_1%

@

4

2

4

PQ112
TPCA8057-H 1N PPAK56-8

PC1040
0.22U_0603_10V7K

1

PC1035
10U_1206_25V6M
2
1

3
2
1
1

LGATE2

LGATE1

B

100_0402_1%
@ PR577
2

GFX@ PR581
590_0402_1%

MUX@ PR639
0_0402_5%
2
1ISNG

Date:

A

1

PL23
.36UH 20% PCMC104T-R36MN1R105 30A
4
1
+CPU_CORE

3
2
1

PC1044
0.22U_0603_25V7K

5

PR603
2.2_0603_5%
2
1 2

PQ111
TPCA8057-H 1N PPAK56-8

BOOT2

1
2

PC1034
10U_1206_25V6M
2
1

5

1
2
+5VS

+VGFX_COREP

*OCP setting value=40A

PC1017GFX@
.1U_0402_16V7K
1
2

ISEN2

*Dual Core OCP setting value=70A
*Qual Core OCP setting value=120A

.1U_0402_16V7K
GFX@ PC1013
1
2

2

QC@ PR157
3.65K_0402_1%
VSUM+2
1

PHASE2

PQ115
TPCA8057-H 1N PPAK56-8

1

(Ipeak=56A)

2

1

CPU_B+

1

@ PC1060
330P_0402_50V7K

4

DC@ PR601
4.32K_0402_1%

PC1061
2
1

1

4

PQ109
TPCA8065-H 1N PPAK56-8

VSUM+

DC@ PR618
1.47K_0402_1%
2
1

2

1

CPU_B+
QC@
PR601
590_0402_1%

PU1000

QC@ PR618
1.24K_0402_1%

330P_0402_50V7K

2
1
PC1059
1000P_0402_50V7K

GFX@ 11K_0402_1%
1 PR575 2

VSUM-

Icc-max=53A
Rdson=3.6~4.5m ohm
DCR=1.1m ohm
HW output cap:
(1)10U_0805_4V
*10
(2)22U_0805_6.3V *15
(3)470U_D2_2V
*4(ESR=4.5m ohm)

2

4
LGATE1

2

1
2

PC1048
2
1
0.22U_0402_6.3V6K
PC1049
2
1
0.22U_0402_6.3V6K

PH4 GFX@
7.5K_0402_1%
10K_0402_5%_TSM0A103J4302RE
PR571
1 GFX@ 21
2

QC@ PL17
.36UH 20% PCMC104T-R36MN1R105 30A
4
QC@ PR154
10K_0402_1%
3
ISEN3
2
1

PC178
PR138
2
1 2
1
680P_0402_50V7K 4.7_1206_5%

28

PH1

PR592
0_0402_5%
1
2

QC@ PQ44
TPCA8057-H 1N PPAK56-8

VSSP1

1

1
PC1068 +
PR569 GFX@ GFX@
1_0402_5% 330U_X_2VM_R6M
2

2

+5VS

3
2
1

29

PROG1

DC@ PR638
0_0402_5%
1
2

BOOT1

+CPU_CORE

QC@ PQ41
TPCA8065-H 1N PPAK56-8

4

@ PQ43
TPCA8057-H 1N PPAK56-8

30

LG1

2

CPU_B+

5

PWM3

3

+VGFX_COREP

2

7

1

ISPG

8

PHASE

PC1037
10U_1206_25V6M
2
1

UGATE

PWM

PC1036
10U_1206_25V6M
2
1

FCCM

2

5

6

QC@ PC122
0.22U_0603_10V7K

4

4

ISEN1

QC@
PR615
3.83K_0402_1%

PC1043
1U_0603_10V6K

VSUM-

PC1054
2
1

ISEN1

1

PC1055
2
1
330P_0402_50V7K

PR620

5

5

3
2
1
QC@ PU10
ISL6208ACRZ-T_QFN8_3X3
5 VCC
BOOT 1

1

37
LGG

UGG

38

39

40

41
PROG2

BOOTG

42

43
ISNG

NTCG

44
ISPG

46

45
RTNG

PHG

31

PR604
1_0603_5%
2
1

PR617
10_0402_1%
2
1

8 VSSSENSE

5
4

QC@PR148
2.2_0603_5%
2
1

GFX@ PL21
.36UH 20% PCMC104T-R36MN1R105 30A

1

1
2

QC@ PR140
0_0402_5%
2
1

LGATEG

PHASEG

UGATEG

2
1

BOOTG

LGATEG

B+

PL20
HCB4532KF-800T90_1812

VSUM-

DC@ PR615
3.32K_0402_1%
2
1

*Iccmax in Turbo Mode for SV (35W) is 53A
4

0.22U_0603_10V7K

UGATE2

PC1047
470P_0402_50V7K
2
1

8 VCCSENSE

2

2.2_0603_5%

LGATE2

PR600
0_0603_5%
1
2

2
1
10_0402_1%
PC1096
470P_0402_50V8J

VDDP

PC1051
2
1

PR611
499_0402_1%
2
1

+CPU_CORE

GFX@ PC1008
1
2
1

2

2

150P_0402_50V8J

PR700
2K_0402_1%

32

DC@ PC1041
22P_0402_50V8J

PR614
PC1050 412K_0402_1%
2
1 2
1

499K_0402_1%

VIN

VW

23

NTC

12

PC1058
2
1

PC1039
2
1

1

4

2

ISEN3

2

33

LG2

24

11

VDD

VR_HOT#

ISUMP

IMON

22

9

VSSP2

ISL95831CRZ-T_TQFN48_6X6

21

PGOOD

10

QC@ 0.22U_0402_6.3V6K
PC1046
33P_0402_50V8J
PR610
2

ISNG
NTCG

VR_ON

8

ISUMN

7

RTN

SCLK

19

6

3

@
1

330P_0402_50V7K

PC1011 GFX@
2
1
ISPG

ALERT#

VSEN

SDA

5

ISEN1

4

PH5
470K_0402_5%_TSM0B474J4702RE
PR5991
2
27.4K_0402_1%

1000P_0402_50V7K

2

PR602

1

change from 43P to 47P
for shortage problem
2010-03-15

8.06K_0402_1%

PC1032
47P_0402_50V8J

47

PHASE2

ISEN2

1

3.83K_0402_1%

FBG

34

17

470P_0402_50V7K
2
1

VSENG

GND

PH2

13

PR598

COMPG

UG2

PGOODG

@ PC1033
@PC1033
2
1

1

PR597
1
2
499_0402_1%
+1.05VS_VTTP @

IMONG

UGATE2

ISEN2

2

For shortage changed

VR_HOT#

PHASEG
GFX@ PR565
BOOTG 2

QC@ PR152
0_0402_5%
BOOT2

ISEN3

1
2

PC1027
0.047U_0603_16V7K

2
1
PR596
19.1K_0402_1%

1 PR593

VR_ON

0_0402_5%

2

36

36

PR579 @
16.5K_0402_1%

35

ISEN3/ FB2

15,36

VSSSENSE

4

+5VS

36

16

1.91K_0402_1%
2

IMVP_IMON

3

48

49

GFX_CORE_PWRGD

2

VGATE

PC1007GFX@
1
2

BOOT2

VWG

15

36

PR594

1

2

FB

8 VR_SVID_CLK

1

COMP

8 VR_SVID_ALRT#

UGATEG

+VGFX_COREP
GFX@ PR564
2
1
10_0402_1%

+3VS

14

8 VR_SVID_DAT

+3VS

2

GFX@ PQ102
TPCA8065-H 1N PPAK56-8

@ PQ101
TPCA8065-H 1N PPAK56-8

VCC_AXG_SENSE 9
330P_0402_50V7K
PC1012
VSS_AXG_SENSE 9
2
1
GFX@
1000P_0402_50V7K GFX@ PR574
2
1
10_0402_1%

PR583
54.9_0402_1%

1
2

For shortage changed

PR584 GFX@
2
1
1.91K_0402_1%

2
1

2
1
130_0402_1%
PR582

2

1

GFX@ PC1018
0.047U_0603_16V7K

GFX@
PR578
18.2K_0402_1%
2
1

+1.05VS_VTTP
PC1020@
.1U_0402_16V7K

18

2
VSS_AXG_SENSE

Parallel and tune length

+

2

2
1
GFX@ PR573
2.55K_0402_1%

GFXVR_IMON

DEL off page

1

GFX@ PR563
27.4K_0402_1%

PC1010 GFX@
680P_0402_50V7K
2
1

1

CPU_B+

QC@ PC117
1U_0603_10V6K

1

GFX@ PR570
2
1
422_0402_1%

PC1014 GFX@
150P_0402_50V8J
2
1
2
1
PR572 GFX@
475K_0402_1%

NTCG

20

2

1

PC1006 GFX@
1000P_0402_50V7K

PR562 GFX@
8.06K_0402_1%
2
1

1

PC1009 GFX@
39P_0402_50V7K
2
1

PR566 @
499K_0402_1%

E

CPU_B+

GFX@ PR561 470P_0402_50V7K
3.83K_0402_1%
2
1
2
1
GFX@ PH3
470KB_0402_5%_ERTJ0EV474J

1

D

2
1
@
PC1019
470P_0402_50V7K

C

PC999 @
2
1

1

B

PC1069
220U_25V_M

A

Alert# PU resister need close CPU,
so the PU resister in HW schematic.
but DAT and CLK need close PWM-IC,
so the PU resister in POWER schematic.

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

52

of

60

5

http://hobi-elektronika.net
4

3

2

Version change list (P.I.R. List)
Item
D

C

Page 1 of 1 for PWR

Fixed Issue

Reason for change

Rev. PG#

1

HW increase 1.8V voltage.

2

VGA Granville OVP issue.

Because VGA has happened OVP issue in Granville SKU, that is caused by outptut capacitor
too small. change PC1094 to SGA00004200 to solve it. PC1088 must remove.

3

1.8V Power sequence adjust.

HW adjust 1.8V power sequence.

4

0.75V Power sequence adjust.

5

HW need to increase 1.8V voltage.

Modify List

Date

Phase

0.1

47

Change PR106 from SD034100280 to SD034976180.

2010/09/23

DVT

0.1

49

Add PC1094 to SGA00004200 and delete PC1088 SF000002O00.

2010/09/23

DVT

0.1

47

2010/09/23

DVT

HW adjust 0.75V power sequence.

0.1

48

Change PR127 from SD028150380 to SD034267380.

2010/09/23

DVT

adjust +1.05VS_VTT power sequence

HW adjust +1.05VS_VTT power sequence

0.1

48

Change PC99 from SE107475K80 to SE076104K80.

2010/09/23

DVT

6

adjust +VDDCI power sequence

HW adjust +VDDCI power sequence

0.1

50

Change PR644 from SD034301380 to SD034100280.

2010/09/23

DVT

7

HW request to delete PR103.

HW request to delete PR103.

0.2

47

Delete PR103 SD028100480.

2010/09/28

DVT

8

PR104 BOM error.

PR104 BOM error for power sequence.

0.2

47

Change PR104 from SD034150380 to SD034510380.

2010/09/28

DVT

9

PR669 BOM error for Seymour only.

PR669 BOM error for Seymour only.

0.2

49

Chnage PR669 from SD034681180 to SD034590180.

2010/09/28

DVT

10

To same as P5WE0 VCCSAP choke.

To same as P5WE0 VCCSAP choke.

0.2

47

Change PL10 from SH000009Q00 to SH00000M700.

2010/09/28

DVT

0.3

47
48

Add PQ130 and PQ131 SB000006800.

2010/10/05

DVT

0.3

42

Delete PR691 SD013000080
CHange PR6 from SD013560080 to SD013000080.

2010/10/05

DVT

11

HW request to add PQ130 and PQ131 to speed HW request to add PQ130 and PQ131 to speed
up to ࣋ሽ.
up to ࣋ሽ.
We reserve chargeable RTC battery to prevent over heat issue, Thermal team result is pass,
so remove chargeable RTC battery.

change PR104 from SD028100380 to SD028150380.

12

Remove chargable RTC battery.

13
14

Chnage PL4 and PL5 to TOKO new part.

Chnage PL4 and PL5 to TOKO new part.

0.3

44

Change PL4 and PL5 from SH000006J80 to SH00000MB00

2010/10/05

DVT

for ISN issue.

for ISN issue.

0.3

43

Add PL30 SH000009Q00.
Delete PL28 SM010018210

2010/10/05

DVT

47

Change PL10 and PL11 from SH000009Q00 to SH00000F800

2010/10/05

DVT

Delete PQ20 SB000006800.

2010/10/05

15
B

1

to same as P5WE0 choke.

to same as P5WE0 choke.

0.3

16

for QC+25WGPU and QC+35W GPU
change CP point.

Becasue Acer deine QC with 25W/35W GPU to be 120W SKU, change CP point to meet
Acer request.

0.3

17

for QC+25WGPU and QC+35W GPU
change CP point.

Becasue Acer deine QC with 25W/35W GPU to be 120W SKU, change CP point to meet
Acer request.

0.3

43

18

Modify adapter throttling at turbo mode
setting point.

Modify adapter throttling at turbo mode
setting point.

0.3

45

CPU Transient responds issue.

Change CPU transient reponds RC time constant.

0.4

52

Add PC1052 SE000003J80. Add PC1096 SE071471J80. Add PR700 SD034200180.

for ISN issue.

0.4

43

Make BOM same as P5WE0.

0.4

19
20
21

for ISN issue.
Make BOM same as P5WE0.

43

Delete PR48 SD034255180

Change PR22 from SD000001F00 to SD021100D80.

D

C

DVT
B

Change PR47 from SD034121280 to SD034100180

2010/10/05

DVT

2010/10/05

DVT

2010/10/07

DVT

Change PL30 from SH000009Q00 to SH00000M700.

2010/10/07

DVT

52

Change PL21,PL23,PL24 from SH000005680 to SH00000HK00.

2010/10/07

DVT

Change PR50 from SD034200280 to SD034511280
Add PR695 SD034154280
Add PR697 SD034174280

22

BOM loss.

Because BOM Config loss 65@ and 90W@, so miss PR695 and PR697.

0.5

45

2010/10/26

PVT

23

Add PR695 SD034909180 9.09K_0402_1%
ADD PR697 SD034162280 16.2K_0402_1%

Modify CPU OCP.

Becuase original design is for 3 phase DC, now change to 2 phase DC, so modify OCP.

0.5

52

Chnage PR618 from SD034698080 to SD000009480

2010/10/26

PVT

24

Modify DC LL.

Because DC OCP was modified, must also update LL of DC.

0.5

52

Chnage PR615 from SD034215180 to SD034332180

2010/10/26

PVT

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

SCHEMATIC,MB A6911
Rev
B

4019BE

Tuesday, November 09, 2010

Sheet
1

53

of

60

http://hobi-elektronika.net

A

BATTERY
12.6V

BATT+

AC ADAPTOR
19V 90W

B

PU2
CHARGER
SL6251AHAZ-T

PU1000
ISL95831CRZ-T

C

D

VIN

PU9
RT8209BGQW

1

Intel Sandy Bridge

+CPU_CORE

+CPU_CORE

1.1V

VCC CORE 94A

+VGFX_CORE

+VGFX_CORE

0.8~1.5V

VAXG 33A

+VCCSA

0.9V
1.5V

VCCSA 6A

+1.05VS_VTT

1.05V

VCCIO 8.5A

+1.8VS

1.8V

VCCPLL 1.2A

B+
PU12
G5603RU1U

E

+1.5V

+VCCSA

VDDQ 10A

+1.05VS_VTTP
1

RAM DDRIII SODIMMX4
PU6
RT8209BGQW

+1.5V

PU998
APW7138NITRL

+VGA_CORE

1.5V

VDD_MEM 14A

0.75V

VTT_MEM 2A

+0.75VS

PU8
UP7711U8

Seymour / Whistler / Granville
+VGA_CORE

0.85~1.1V

47A

+VDDCI

1V

2.775A

1.5V

34A

3.3V

0.19A

VRAM 512M or 1GB
64Mx16 (K4B1G1646E)
1.5V

2.4 A

+1.5VSDGPU

U38
AO4430L

+1.8VS

4.6A (Granville only)

+1.0VSDGPU

PU17
G971-120ADJF11U

PU7
SY8033BDBC

1V

+3VSDGPU

Q9
AO3413L

2

+1.8VSDGPU

U36
DMN3030LSS-13

1.8V

U37
DMN3030LSS-13

2

2.174A

Intel Cougar Point-M PCH
V_PROC_IO 1mA
VccCore 1.3A
VccDMI 42mA
+1.05VS_VCCP

U35
+3VS
DMN3030LSS-13

1.05V

+3VALW
+INVPWR_B+

3

PU3
RT8205EGQW

+LCDVDD

LCD panel
17.3"

+1.5VS

+5VALW

U33
DMN3030LSS-13

Q19
AO3413L

B+ 25mA
+3VS 515mA

1.5V

VccVRM 160mA

+1.8VS

1.8V

VccpNAND 190mA
VccTX_LVDS 60mA

+3VS

3.3V

+5VS
+5VALW_PCH

RTC
Bettary

Vcc3_3 266mA
VccADAC 1mA
VccALVDS 1mA

3

VccSPI 20mA
VccDSW 3mA
VccSus3_3 119mA
VccSusHDA 10mA

+3VALW_PCH

FAN Control
APL5607

VccADPLLA 80mA
VccADPLLB 80mA
VccIO 2.925A
VccASW 1.01A
VccDIFFCLKN 55mA

5V
RTCVCC

V5REF 1mA
V5REF_Sus 1mA
VCCRTC

+5VS 250mA

4

USB3.0X1

USB2.0 X2

+5VALW 3A

+5VALW
2A

+1.05V_USB3.0
500mA

SATA

Audio Codec
ALC271X

+5VS 3A

+5VS 668mA

+3VS

+3VS 35mA

Realtek
RTS5138

LAN
AR8151
+3VALW 217mA

+3VS 217mA

EC
ENE KB930

4

Bluetooth

+3.3VALW 30mA
+3VS 3mA

+3VS 61mA

Mini Card 1

Mini Card 2

+1.5VS 500mA
+3VS 1A
+3VALW 330mA

+1.5VS 500mA
+3VS 1A
+3VALW 330mA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

Title

SCHEMATIC,MB A6911

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Rev
B

4019A9

Tuesday, November 09, 2010
E

Sheet

54

of

60

http://hobi-elektronika.net

A

B

C

D

1.5_VDDC_PWREN#

(PU17)
G971-120ADJF11U

E

+1.0VSDGPU

Page 51

SYSON
VR_ON

(PU1000)
ISL95831CRZ-T

+CPU_CORE

(U39)
APL5930KAI

+1.05V_USB3.0
Page 42

1

1

Page 55
1.5_VDDC_PWREN#

(PU998)
APW7138NITRL

+VGA_CORE

(U37)
DMN3030LSS-13

SUSP

+1.5VS

Page 40

Page 49

ADAPTER
SYSON

(PU6)
RT8209BGQW

(PU8)
UP7711U8

+1.5V

+0.75VS

SUSP

B+
BATTERY

Page 48

Page 46

VCCPPWRGOOD

(PU12)
G5603RU1U
Page 47

VS_ON
2

(U38)
AO4430L

+VCCSA

+1.5VSDGPU
Page 40

DGPU_PWR_EN#

(PU9)
RT8209BGQW

+1.05VS_VTT

+1.05VS_PCH
2

(SUSP#)

Page 48

CHARGER

(PU3)
RT8205EGQW
Page 44

+5VALW

SUSP

SYSON#

(U33)
DMN3030LSS-13
Page 40

+3VALW

SYSON#

(U46)
AP2301MPG-13

SUSP#

(U42)
AP2301MPG-13

Page 36

SUSP

(PU7)
SY8033BDBC

Page 41

+3VALW_PCH

JLAN1

(U35)
DMN3030LSS-13

+3VALW_EC

Page 47

SYSON

(U40)
RT9701-PB

Page 40

Page 41

3

3

+5VS

+USB_VCCB

+USB_VCCA

+1.8VS

+3VS

+3V_USB3.0

DGPU_PWR_EN#

(U36)
DMN3030LSS-13

+CRT_VCC

Page 40

BT_ON#

ENVDD

(Q31)
AO3413L

+3VS_WWAN
Page 35

+HDMI_5V_OUT

DGPU_PWR_EN

(Q19)
AO3413L

(Q9)
AO3413L
Page 30

+1.8VSDGPU

+3VS_WLAN

+BT_VCC

+LCDVDD

Page 23

+3VSDGPU

+5VS_HDD1

+5VS_HDD2
4

4

+5VS_ODD

+VDDA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

55

of

60

http://hobi-elektronika.net

A

B

C

D

E

1

1

2.2K
4.7K

+3VALW_PCH

2.2K

4.7K
H14

PCH_SMBCLK

C9

PCH_SMBDATA

2N7002

+3VS

D_CK_SCLK

200

D_CK_SDATA

202

DIMM1, 2

2N7002

PCH

200
202

0 @
0 @

2

MINI_SMBCLK
MINI_SMBDATA

DIMM3, 4
2

WLAN

4.7K

+3VS

4.7K
SMB_CLK_S3

53

SMB_DATA_S3

51

2N7002
CPU XDP

2N7002
53

2.2K
2.2K
E14

PCH_SML1CLK

M16

PCH_SML1DATA

51

4.7K

PCH XDP

+3VALW_PCH

4.7K
EC_SMB_CK2

53

EC_SMB_DA2

51

2N7002

VGA
Thermal
Sensor

2N7002

2N7002

+3VSDGPU

VGA_SMB_CK2
VGA_SMB_DA2

2N7002

2.2K
2.2K

3

79

EC_SMB_CK2

80

EC_SMB_DA2

+3VALW
3

SCL2
SDA2

2.2K

+3VALW

KBC

2.2K
77

EC_SMB_CK1

78

EC_SMB_DA1

SCL1
SDA1

100 ohm
100 ohm

7

BATTERY

6

CONN

KB930QF A0
PCH SM Bus address
Device
ChannelA

4

ChannelB

A0

1010 000X

DIMM1

A2

1010 001X

DIMM0

A4

1010 010X

DIMM1

A6

1010 011X

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

Address
DIMM0

2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

56

of

60

A

http://hobi-elektronika.net
B

C

D

DIMMA*2

DDR_A_CLK[1..2]
1

CLK_CPU_DMI

BCLK

120MHZ (For eDP)

DDR_B_CLK[1..2]

DPLL_REF_SCLK

FDI

CLK_CPU_DPLL

1

DIMMB*2

CLK_CPU_DPLL

CPU
Sandy Bridge
SOCKET

E

100MHZ DMI

100MHZ

CLKOUT_PCIE1

CLK_OUT_DP

CLK_PCIE_MINI1

Mini Card 1

100MHZ

2

2

CLK_CPU_DMI
100MHZ

CLK_BUF_ICH_14M
14.318MHZ
CLK_BUF_PCIE_SATA
100MHZ
CLK_BUF_CPU_DMI
100MHZ
CLK_BUF_DREF_96M
96MHZ
CLKIN_GND1
100MHZ

CLK_OUT_DMI

CLKOUT_PCIE2

REFCLK14IN
CLKOUT_PCIE3

24M Hz

CLK_PCIE_USB30

USB3.0

100MHZ

Y5

25M Hz

CLK_PCIE_LAN#

AR8151

100MHZ

CLKIN_SATA

CLKIN_DMI

INTEL
PCH
Cougar Point

CLKOUT_PCIE4

CLK_PCIE_MINI2

Mini Card 2

100MHZ

CLKOUT_PCIE5
CLKIN_DOT_96

CLKOUT_PCIE6
CLKOUT_PCIE7

CLKIN_DMI2

CLKOUT_PEG_A

3

3

CLK_BCLK_ITP

CPU XDP

100MHZ

CLK_PCI_LPBACK

CLKOUT_PEG_B
CLKOUT_BCLK0

Seymour/
Whistler/
Granville

CLK_PEG_VGA
100MHZ

CLK_PCI_LPC
CLKIN_PCILOOPBACK

27MHz Y3

EC KB930 A0

32.768K Hz
X1

33MHZ

CLK_SD_48M

RTC

SATA

32.768K Hz
Y1

25M Hz

RTS5138
48MHZ

Y2

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

57

of

60

http://hobi-elektronika.net

A

B

C

D

E

1

1

2

V

+5VALW

+5VALW

V

B4

V

SYS_PWROK

13

B7

5

PBTN_OUT#

EC_ON

B6

PLT_RST#

V

14

15

CPU
2

VGA_PWROK

6

V
9

V

+1.5VSDGPU
U38

U35
+3VS

V

V
PU9
+1.05VS_VTT

V

V

V

V

3

U33
+5VS

+1.8VSDGPU
U36

+1.0VSDGPU
PU17
+VGA_CORE
PU998

1.5_VDDC_PWREN#

PU8
+0.75V

VCCPPWRGOOD

VGA

11
VGATE

U37
+1.5VS

V

8

V

DGPU_PWR_EN#

V

8a (DIS)

SUSP#,SUSP

VR_ON

+1.5V
PU6

V

DGPU_PWR_EN

SYSON#

V

7

+3VSDGPU
Q9

V

SYSON

V

8b (DIS)

V

ON/OFF

V

A4

V

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#

2

H_CPUPWRGD

V

A5

PM_DRAM_PWRGD

PCH

V V

PCH_RSMRST#

V

V V

B3

12

4

EC
PQ1

51ON#

+3VALW_PCH

3

2

V

B2

B+

2

10
3

PCH_PWROK

PU12
+VCCSA

V

B1

B7

V

BATT

A5

V

+3VALW

V

PU3

VV

B+

+5VALW

+5VALW

B5

V

PU2

A3

V

V V

A2

VV

BATT
MODE

+3VALW_PCH J5

+3VALW

VIN

V

AC
MODE

A1

PU1000
+CPU_CORE

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

58

of

60

http://hobi-elektronika.net

A

B

C

D

E

1

1

PCB
ZZZ

LA-6911P MB Rev0: DA80000LC00
LA-6911P MB Rev1: DA80000LC10
LA-6911P MB with Small Board Rev1: DAZ

LA-69111P REV0 M/B

VGA

CRT Option Components

Granville VGA_CORE CAP Option

DIS EDP Option Components

C622

C605

C591 GRAN@
C604 GRAN@

C598
1

DISO@
DISO@
DISO@
2
2
2
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J

216-0769024 A12

R23
R17

.1U_0402_16V7K
.1U_0402_16V7K

2 2

1 1

.1U_0402_16V7K
.1U_0402_16V7K

R24
R22

DEDP@
DEDP@

R9
R7

DEDP@
DEDP@

SGA00003N00
S POLY C 470U 2V Y X
LESR9M S H1.9

TXOUT_1P = DP1P
TXOUT_1N = DP1N

1

EC susclk/crystal
Option Components

I2CC_SCL = AUXP
I2CC_SDA = AUXN

X761@

Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
X76264BOL01

L38

X76264BOL02 VRAM 512M HYN P7YE0

X762@

DISO@
1
0_0805_5%
DISO@
2
1
0_0805_5%
DISO@
2
1
0_0805_5%
2

L42

64Mx16x4 Seymour

X76264BOL02

2

2
1
C504
100K_0402_5%

X76264BOL01

X76264BOL01 VRAM 512M SAM P7YE0

470U_X_2VY_R9M
470U_X_2VY_R9M

C600
1

15P_0402_50V8J: SE071150J80
12P_0402_50V8J: SE071120J80

X76

ZZZ

C614
1

TXOUT_2P = DP0P
TXOUT_2N = DP0N

DISO@
DISO@
DISO@
2
2
2
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J

216-0810005 A11
2

ZZZ

C623

1 1

WHISTLER PRO M2 A11:
SA00004C720(S IC 216-0810005 A11 WHISTLER PRO FCBGA 962P ABO !)

WHIS@

.1U_0402_16V7K
.1U_0402_16V7K

2 2

U30

DEDP@
DEDP@

1 1

1

2 2

1

1 1

Granville PRO M2 A12:
SA00004C820(S IC 216-0769024 A12 GRANVILLE PRO ABO!)

GRAN@

2 2

U30

L35

Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!)
X76264BOL02
ZZZ

0_0805_5%: SD002000080

64Mx16x4 Seymour

X76264BOL03
2

X76264BOL03 VRAM 1G SAM P7YE0

X763@

R307

Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
X76264BOL03
ZZZ
3

64Mx16x8 Whistler/Granville

DISO@
1
1K_0402_5%

DIS only PCH DAC_IREF
can use 1K_0402_5% PD to GND

X76264BOL04

X76264BOL04 VRAM 1G HYN P7YE0

X764@

3

Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!)
X76264BOL04
ZZZ

64Mx16x8 Whistler/Granville

X76264BOL05

X76264BOL05 VRAM 2G HYN P7YE0

X765@

Hynix : SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!)
X76264BOL05
ZZZ

128Mx16x8 Whistler/Granville

X76264BOL06

X76264BOL06 VRAM 2G SAM P7YE0

X766@

Samsung : SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!)
X76264BOL06
ZZZ

128Mx16x8 Whistler/Granville

X76264BOL07

X76264BOL07 VRAM 1G SAM P7YE0

X767@

Samsung : SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!)
X76264BOL07
ZZZ
4

128Mx16x4 Seymour

X76264BOL08

X76264BOL08 VRAM 1G HYN P7YE0

X768@

4

Hynix : SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!)
X76264BOL08

128Mx16x4 Seymour

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

60

of

60

A

http://hobi-elektronika.net
B

0923:
rework
ADD Q8 DMN66D0LDW-7(SB00000DH00) & change BOM structure to DIS@(DIS@ Granville can't power on issue)
R72 100K_0402_5%(SD028100380)change BOM structure to DIS@(DIS@ Granville can't power on issue)
R674 4.7K PH change BOM structure to @(+3VS GPIO19 leakage)
D31 change BOM structure to @(EC debug CLK leakage)
R531,R530 change BOM structure to DISO@(HSYN:VSYNC 11: Audio for both DisplayPort and HDMI)
ADD C591 C604 BOM option
(Seymour/Whistler option NOGRAN@ SGA20331E10 S POLY C 330U 2V 9mohm H1.9)
(Granville option GRAN@ SGA00004200 S POLY C 470U 2V M D2 LESR4.5M SX H1.9)
C746,C750 change from SF000001500 to SF000001580

1

Power sequence:
1. BOT (adjust +5VS power sequence)
R698 change from 200K to 100K_0402_5% (SD028100380)
2. BOT (adjust +1.8VS power sequence)
PR104 change from 100K to 510K_0402_5%(SD028510380)
remove PR103 1M_0402_5%
3. TOP (adjust +1.5VS power sequence)
R67
change from 510K_0402_5% to 750K_0402_5%(SD028750380)
4. TOP (adjust +0.75VS power sequence)
PR127 change from 150K_0402_5% to 267K_0402_1%(SD034267380)
5. TOP (adjust +1.05VS_VTT power sequence)
PC99 change from 4.7U to .1U_0402_16V7K (SE076104K80)
6. TOP (adjust +1.5VSDGPU power sequence)
R113 510K change to 100K_0402_1% (SD034100380)
7. BOT (adjust +VDDCI power sequence)
PR644 301K change to 10K_0402_1% (SD034100280)

E

0930:
R534,R540 change from 100_0402_1% to 1K_0402_5%(SD028100180)(DG1.5 change save cost)
C744,C745 change from 18P_0402_50V8J to 27P_0402_50V8J(SE071270J80)(25Mhz Crystal modify)
R357,R358,R330,R331,R345,R346,R387,R393,R292 change BOM structure to @ (10K_0402_5%)PD to GND(DG1.5 unuse CLK NC)
R666,R667 change BOM structure to @(XDP unuse)
R573,R575,R571,R572,R562,R566,R567,R570 DEL option 499_0402_1% leave 680_0402_5%
R318,R332 change from 0ohm to 22_0402_5%(SD028220A80)
C448,C483 change to 4.7P_0402_50V8J(SE07147AC80)
L47 change to 67ohm common mode choke CHENG HANN WCM2012F2SF-670T04(SM070000S80)
------------------------------------------------------------------

1025:
R370,R413 change from SD028100380(100K_0402_5%) to SD028200380(200K_0402_5%)
PCH_GPIO1 change net to WL_EN#
LVDS
Add +5VS (Pin34) & USB20_N4/P4 (Pin35, 36)
change EDP_HPD to Pin18
PCH side add USB20_N4/P4 (Pin35, 36)
For eDP interface AUX channel, please request Layout routing as differential signal to follow eDP Layout Guide.
(VGA_LCD_CLK & VGA_LCD_DATA / I2CC_SCL & I2CC_SDA)
DEL DDR DM
R50,R58,R59,R48,R56,R51,R60,R49 DIMMA
R39,R52,R44,R43,R46,R38,R45,R40 DIMMA
R77,R73,R109,R112,R180,R181,R192,R206 DIMMB
R64,R83,R108,R115,R179,R183,R189,R208 DIMMB
1026:
C604,C591 change from SGA00004200(470 4.5mohm)to SGA00003N00(470 9mohm)
Pop R257(SD028100380 100K_0402_5%),R622(SD028820180 8.2K_0402_5%) Board ID
R443 change from 100K_0402_5% to 10K_0402_5% (SD028100280)
remove R471,R622(JMINI1,JMINI2 Pin42 0ohm series resister)
J1,J2 change location to J6,J7
remove R222 0ohm_0402 (H_CPUPWRGD_R)
remove R423,0ohm_0402 (MINI1_CLKREQ#_R)
remove R392 0ohm_0402 (LAN_CLKREQ#_R)
remove R685 0ohm_0402 (MINI2_CLKREQ#_R)
remove R655 0ohm_0402 (WAKE#)
remove R636 0ohm_0402 (PCH_RSMRST#)
remove R377 0ohm_0402 (SUS_PWR_DN_ACK)
remove R339 0ohm_0402 (PBTN_OUT#)
remove R359 0ohm_0402 (DGPU_HOLD_RST#)
remove R16 0ohm_0402 (BKOFF#)
remove R448 0ohm_0402 (VGA_EDP_DET)
remove R533 0ohm_0402 (VGA_HDMI_DET)
remove R627 0ohm_0603 (+SPI_VCC)

0924:
Q37,Q39,Q40,Q41, change from SB00000FG00 to SB00000FG10
U7 change from SB000007O00 to SB000007O10
USB3.0 schmetic change to unpop
XDP change to unpop
U19 A10,N10,P10,B12 connect to GND
0925:
R249 change from U15.2 to U15.1(footprint issue)
R105 change form 10K to 10_0402_5%(SD028100A80)
R422 change BOM structure to @(crystal issue debug port1.2)
R422 change +3VS to +3VALW_PCH (GPIO28)
R674 change BOM structure to @(leakage issue debug port1.2)
R674 change +3VALW_PCH to +3VS (GPIO19)
ADD LED11 pop WLAN_LED#(SC500007700),LED12 @ MEDIA_LED#(SC591NB5A30)
LED10 WLAN_LED#(SC500007700) change BOM structure to @
DEL D9,D10 USB3.0 old ESD diode
ADD D32 new USB3.0 ESD diode (SC300001D00)
DEL R238,R250,C401 USB3.0 conn PD resister & CAP
EMI request:
R595,R596 change to @ L47 change to POP(USB2.0 common mode choke)

3

D

1

Power:
PR101 change from 10K to 9.53K (adjust +1.5V power)
PR106 change from 10K to 9.76K (adjust +1.8VS power)
Layout:
D21 channge to SC600000B00 (for sourcer 2nd source)
DEL C590,C603 (DEL colay Cap)
L24,25,27,30,31 change from SM010004010 to SM010015410
BATT Blue light place at front side
H1 change H3P0 to H4P6
DEL LED1,LED2,LED3,LED4

2

C

0929:
DEL Rechargerable RTC schematic D21,R425,C551

2

ADD R39 0ohm_0402 LOCAL_DIM
ADD R38 0ohm_0402 COLOR_ENG_EN
C242,C653,C332,C354,C678 change footprint to C_X(2pin)

0927:
Audio vender suggest:
C913 change BOM structure to @
ADD C702 22K_0402_5%(SD028220280)
change USB conn to USB2.0(SUYIN_020133GB004M25MZL_4P-T)
modify Debug port note(GPIO19 PH +3VS GPIO28 PH +3VALW_PCH)
R667,R666 change BOM structure to @(XDP CLK source)
change SW4,SW5 BOM structure to @ (debug PWRBTN)
change R432,R435,R437 from 1K_0402_5% to 300_0402_5%(orange LED resister)
change USB3.0 schmetic BOM structure back to USB3@
C746,C750 change from SF000001500 to SF000001580
D4,D5 change from SCSH491D010(S SCH DIO CH491DPT SOT-23) to SCS00002000(S SCH DIO RB491D SOT-23 PANJIT)
Q29,Q33,Q36 change from SB934130020(S TR AO3413L 1P SOT23-3) to SB000006R10(S TR AO3419L 1P SOT23-3)

3

0928:
DEL R468
JMINI1.24 change power source from +3VS to +3VS_WLAN
DEL R613
JMINI2.24change power source from +3VS to +3VS_WWAN
DEL R352
change power source from +XDPWR_SDPWR_MSPWR to +CARDPWR
Q21 change from SB324110080(2SC2411K) to SB039040020(MMBT3904)
Change JUSB2 footprint to "SUYIN_020173GB004M25MZL_4P"
ADD R613 1M PD to GND(HDA_SYNC_PCH_R)
ADD SLP_A#
at U37.G10 test point(for DFT request)
ADD JTAG_TDI at U30.AN23 test point(for DFT request)
ADD JTAG_TDO at U30.AM24 test point(for DFT request)
JREAD1 change conn from TAITW_R013-P12-HM_44P_NR to TAITW_R013-P17-HM_40P_NR

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

SCHEMATIC,MB A6911
Rev
B

4019A9

Tuesday, November 09, 2010

Sheet
E

59

of

60



---

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File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.5
Linearized                      : No
Encryption                      : Standard V5.5 (256-bit)
Warning                         : Incomplete Encrypt specification

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