UM10398 LPC111x/LPC11Cxx User Manual LPC11C Reference
User Manual:
Open the PDF directly: View PDF
Page Count: 548 [warning: Documents this large are best viewed by clicking the View PDF Link!]
- Chapter 1: LPC111x/LPC11Cxx Introductory information
- Chapter 2: LPC111x/LPC11Cxx Memory mapping
- Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
- 3.1 How to read this chapter
- DEVICE_ID register
- C_CAN controller
- Entering Deep power-down mode
- Enabling sequence for UART clock
- NMI source selection register
- 3.2 General description
- 3.3 Pin description
- 3.4 Clock generation
- 3.5 Register description
- 3.5.1 System memory remap register
- 3.5.2 Peripheral reset control register
- 3.5.3 System PLL control register
- 3.5.4 System PLL status register
- 3.5.5 System oscillator control register
- 3.5.6 Watchdog oscillator control register
- 3.5.7 Internal resonant crystal control register
- 3.5.8 System reset status register
- 3.5.9 System PLL clock source select register
- 3.5.10 System PLL clock source update enable register
- 3.5.11 Main clock source select register
- 3.5.12 Main clock source update enable register
- 3.5.13 System AHB clock divider register
- 3.5.14 System AHB clock control register
- 3.5.15 SPI0 clock divider register
- 3.5.16 UART clock divider register
- 3.5.17 SPI1 clock divider register
- 3.5.18 WDT clock source select register
- 3.5.19 WDT clock source update enable register
- 3.5.20 WDT clock divider register
- 3.5.21 CLKOUT clock source select register
- 3.5.22 CLKOUT clock source update enable register
- 3.5.23 CLKOUT clock divider register
- 3.5.24 POR captured PIO status register 0
- 3.5.25 POR captured PIO status register 1
- 3.5.26 BOD control register
- 3.5.27 System tick counter calibration register
- 3.5.28 IRQ latency register
- 3.5.29 NMI source selection register
- 3.5.30 Start logic edge control register 0
- 3.5.31 Start logic signal enable register 0
- 3.5.32 Start logic reset register 0
- 3.5.33 Start logic status register 0
- 3.5.34 Deep-sleep mode configuration register
- 3.5.35 Wake-up configuration register
- 3.5.36 Power-down configuration register
- 3.5.37 Device ID register
- 3.6 Reset
- 3.7 Start-up behavior
- 3.8 Brown-out detection
- 3.9 Power management
- 3.10 Deep-sleep mode details
- 3.11 System PLL functional description
- Post divider
- Feedback divider
- Changing the divider values
- 3.12 Flash memory access
- Chapter 4: LPC111x/LPC11Cxx Power Monitor Unit (PMU)
- Chapter 5: LPC111x/LPC11Cxx Power profiles
- 5.1 How to read this chapter
- 5.2 Basic configuration
- 5.3 Features
- 5.4 Description
- 5.5 Definitions
- 5.6 Clocking routine
- 5.6.1 set_pll
- 5.6.1.1 Param0: system PLL input frequency and Param1: expected system clock
- 5.6.1.2 Param2: mode
- 5.6.1.3 Param3: system PLL lock time-out
- 5.6.1.4 Code examples
- 5.6.1.4.1 Invalid frequency (device maximum clock rate exceeded)
- 5.6.1.4.2 Invalid frequency selection (system clock divider restrictions)
- 5.6.1.4.3 Exact solution cannot be found (PLL)
- 5.6.1.4.4 System clock less than or equal to the expected value
- 5.6.1.4.5 System clock greater than or equal to the expected value
- 5.6.1.4.6 System clock approximately equal to the expected value
- 5.6.1 set_pll
- 5.7 Power routine
- Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt Controller (NVIC)
- Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration (IOCONFIG)
- 7.1 How to read this chapter
- Pin configuration
- C_CAN pins
- Pseudo open-drain function
- Pull-up level
- 7.2 Features
- 7.3 General description
- 7.4 Register description
- 7.4.1 IOCON_PIO2_6
- 7.4.2 IOCON_PIO2_0
- 7.4.3 IOCON_PIO_RESET_PIO0_0
- 7.4.4 IOCON_PIO0_1
- 7.4.5 IOCON_PIO1_8
- 7.4.6 IOCON_PIO0_2
- 7.4.7 IOCON_PIO2_7
- 7.4.8 IOCON_PIO2_8
- 7.4.9 IOCON_PIO2_1
- 7.4.10 IOCON_PIO0_3
- 7.4.11 IOCON_PIO0_4
- 7.4.12 IOCON_PIO0_5
- 7.4.13 IOCON_PIO1_9
- 7.4.14 IOCON_PIO3_4
- 7.4.15 IOCON_PIO2_4
- 7.4.16 IOCON_PIO2_5
- 7.4.17 IOCON_PIO3_5
- 7.4.18 IOCON_PIO0_6
- 7.4.19 IOCON_PIO0_7
- 7.4.20 IOCON_PIO2_9
- 7.4.21 IOCON_PIO2_10
- 7.4.22 IOCON_PIO2_2
- 7.4.23 IOCON_PIO0_8
- 7.4.24 IOCON_PIO0_9
- 7.4.25 IOCON_SWCLK_PIO0_10
- 7.4.26 IOCON_PIO1_10
- 7.4.27 IOCON_PIO2_11
- 7.4.28 IOCON_R_PIO0_11
- 7.4.29 IOCON_R_PIO1_0
- 7.4.30 IOCON_R_PIO1_1
- 7.4.31 IOCON_R_PIO1_2
- 7.4.32 IOCON_PIO3_0
- 7.4.33 IOCON_PIO3_1
- 7.4.34 IOCON_PIO2_3
- 7.4.35 IOCON_SWDIO_PIO1_3
- 7.4.36 IOCON_PIO1_4
- 7.4.37 IOCON_PIO1_11
- 7.4.38 IOCON_PIO3_2
- 7.4.39 IOCON_PIO1_5
- 7.4.40 IOCON_PIO1_6
- 7.4.41 IOCON_PIO1_7
- 7.4.42 IOCON_PIO3_3
- 7.4.43 IOCON_SCK_LOC
- 7.4.44 IOCON_DSR_LOC
- 7.4.45 IOCON_DCD_LOC
- 7.4.46 IOCON_RI_LOC
- Chapter 8: LPC1100XL series: I/O configuration (IOCONFIG)
- 8.1 How to read this chapter
- 8.2 Features
- 8.3 General description
- 8.4 Register description
- 8.4.1 IOCON_PIO2_6
- 8.4.2 IOCON_PIO2_0
- 8.4.3 IOCON_PIO_RESET_PIO0_0
- 8.4.4 IOCON_PIO0_1
- 8.4.5 IOCON_PIO1_8
- 8.4.6 IOCON_PIO0_2
- 8.4.7 IOCON_PIO2_7
- 8.4.8 IOCON_PIO2_8
- 8.4.9 IOCON_PIO2_1
- 8.4.10 IOCON_PIO0_3
- 8.4.11 IOCON_PIO0_4
- 8.4.12 IOCON_PIO0_5
- 8.4.13 IOCON_PIO1_9
- 8.4.14 IOCON_PIO3_4
- 8.4.15 IOCON_PIO2_4
- 8.4.16 IOCON_PIO2_5
- 8.4.17 IOCON_PIO3_5
- 8.4.18 IOCON_PIO0_6
- 8.4.19 IOCON_PIO0_7
- 8.4.20 IOCON_PIO2_9
- 8.4.21 IOCON_PIO2_10
- 8.4.22 IOCON_PIO2_2
- 8.4.23 IOCON_PIO0_8
- 8.4.24 IOCON_PIO0_9
- 8.4.25 IOCON_SWCLK_PIO0_10
- 8.4.26 IOCON_PIO1_10
- 8.4.27 IOCON_PIO2_11
- 8.4.28 IOCON_R_PIO0_11
- 8.4.29 IOCON_R_PIO1_0
- 8.4.30 IOCON_R_PIO1_1
- 8.4.31 IOCON_R_PIO1_2
- 8.4.32 IOCON_PIO3_0
- 8.4.33 IOCON_PIO3_1
- 8.4.34 IOCON_PIO2_3
- 8.4.35 IOCON_SWDIO_PIO1_3
- 8.4.36 IOCON_PIO1_4
- 8.4.37 IOCON_PIO1_11
- 8.4.38 IOCON_PIO3_2
- 8.4.39 IOCON_PIO1_5
- 8.4.40 IOCON_PIO1_6
- 8.4.41 IOCON_PIO1_7
- 8.4.42 IOCON_PIO3_3
- 8.4.43 IOCON_SCK0_LOC
- 8.4.44 IOCON_DSR_LOC
- 8.4.45 IOCON_DCD_LOC
- 8.4.46 IOCON_RI_LOC
- 8.4.47 IOCON_SSEL1_LOC
- 8.4.48 IOCON_CT16B0_CAP0_LOC
- 8.4.49 IOCON_SCK1_LOC
- 8.4.50 IOCON_MISO1_LOC
- 8.4.51 IOCON_MOSI1_LOC
- 8.4.52 IOCON_CT32B0_CAP0_LOC
- 8.4.53 IOCON_RXD_LOC
- Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C, and LPC1100L series, HVQFN/LQFP packages)
- Chapter 10: LPC111x Pin configuration (LPC1100L series, TSSOP, DIP, SO packages)
- Chapter 11: LPC111x Pin configuration (LPC1100XL series, HVQFN/LQFP/TFBGA48 packages)
- Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
- 12.1 How to read this chapter
- 12.2 Introduction
- 12.3 Register description
- 12.3.1 GPIO data register
- 12.3.2 GPIO data direction register
- 12.3.3 GPIO interrupt sense register
- 12.3.4 GPIO interrupt both edges sense register
- 12.3.5 GPIO interrupt event register
- 12.3.6 GPIO interrupt mask register
- 12.3.7 GPIO raw interrupt status register
- 12.3.8 GPIO masked interrupt status register
- 12.3.9 GPIO interrupt clear register
- 12.4 Functional description
- Write operation
- Read operation
- Chapter 13: LPC111x/LPC11Cxx UART
- 13.1 How to read this chapter
- 13.2 Basic configuration
- 13.3 Features
- 13.4 Pin description
- 13.5 Register description
- 13.5.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0, Read Only)
- 13.5.2 UART Transmitter Holding Register (U0THR - 0x4000 8000 when DLAB = 0, Write Only)
- 13.5.3 UART Divisor Latch LSB and MSB Registers (U0DLL - 0x4000 8000 and U0DLM - 0x4000 8004, when DLAB = 1)
- 13.5.4 UART Interrupt Enable Register (U0IER - 0x4000 8004, when DLAB = 0)
- 13.5.5 UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only)
- 13.5.6 UART FIFO Control Register (U0FCR - 0x4000 8008, Write Only)
- 13.5.7 UART Line Control Register (U0LCR - 0x4000 800C)
- 13.5.8 UART Modem Control Register
- 13.5.9 UART Line Status Register (U0LSR - 0x4000 8014, Read Only)
- 13.5.10 UART Modem Status Register
- 13.5.11 UART Scratch Pad Register (U0SCR - 0x4000 801C)
- 13.5.12 UART Auto-baud Control Register (U0ACR - 0x4000 8020)
- 13.5.13 Auto-baud
- 13.5.14 Auto-baud modes
- 13.5.15 UART Fractional Divider Register (U0FDR - 0x4000 8028)
- 13.5.16 UART Transmit Enable Register (U0TER - 0x4000 8030)
- 13.5.17 UART RS485 Control register (U0RS485CTRL - 0x4000 804C)
- 13.5.18 UART RS485 Address Match register (U0RS485ADRMATCH - 0x4000 8050)
- 13.5.19 UART1 RS485 Delay value register (U0RS485DLY - 0x4000 8054)
- 13.5.20 RS-485/EIA-485 modes of operation
- RS-485/EIA-485 Normal Multidrop Mode (NMM)
- RS-485/EIA-485 Auto Address Detection (AAD) mode
- RS-485/EIA-485 Auto Direction Control
- RS485/EIA-485 driver delay time
- RS485/EIA-485 output inversion
- 13.6 Architecture
- Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
- 14.1 How to read this chapter
- 14.2 Basic configuration
- 14.3 Features
- 14.4 General description
- 14.5 Pin description
- 14.6 Register description
- 14.6.1 SPI/SSP Control Register 0
- 14.6.2 SPI/SSP0 Control Register 1
- 14.6.3 SPI/SSP Data Register
- 14.6.4 SPI/SSP Status Register
- 14.6.5 SPI/SSP Clock Prescale Register
- 14.6.6 SPI/SSP Interrupt Mask Set/Clear Register
- 14.6.7 SPI/SSP Raw Interrupt Status Register
- 14.6.8 SPI/SSP Masked Interrupt Status Register
- 14.6.9 SPI/SSP Interrupt Clear Register
- 14.7 Functional description
- Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
- 15.1 How to read this chapter
- 15.2 Basic configuration
- 15.3 Features
- 15.4 Applications
- 15.5 General description
- 15.6 Pin description
- 15.7 Register description
- 15.7.1 I2C Control Set register (I2C0CONSET - 0x4000 0000)
- 15.7.2 I2C Status register (I2C0STAT - 0x4000 0004)
- 15.7.3 I2C Data register (I2C0DAT - 0x4000 0008)
- 15.7.4 I2C Slave Address register 0 (I2C0ADR0- 0x4000 000C)
- 15.7.5 I2C SCL HIGH and LOW duty cycle registers (I2C0SCLH - 0x4000 0010 and I2C0SCLL- 0x4000 0014)
- 15.7.6 I2C Control Clear register (I2C0CONCLR - 0x4000 0018)
- 15.7.7 I2C Monitor mode control register (I2C0MMCTRL - 0x4000 001C)
- 15.7.8 I2C Slave Address registers (I2C0ADR[1, 2, 3] - 0x4000 00[20, 24, 28])
- 15.7.9 I2C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C)
- 15.7.10 I2C Mask registers (I2C0MASK[0, 1, 2, 3] - 0x4000 00[30, 34, 38, 3C])
- 15.8 I2C operating modes
- 15.9 I2C implementation and operation
- 15.9.1 Input filters and output stages
- 15.9.2 Address Registers, ADDR0 to ADDR3
- 15.9.3 Address mask registers, MASK0 to MASK3
- 15.9.4 Comparator
- 15.9.5 Shift register, DAT
- 15.9.6 Arbitration and synchronization logic
- 15.9.7 Serial clock generator
- 15.9.8 Timing and control
- 15.9.9 Control register, CONSET and CONCLR
- 15.9.10 Status decoder and status register
- 15.10 Details of I2C operating modes
- 15.10.1 Master Transmitter mode
- 15.10.2 Master Receiver mode
- 15.10.3 Slave Receiver mode
- 15.10.4 Slave Transmitter mode
- 15.10.5 Miscellaneous states
- 15.10.6 Some special cases
- 15.10.7 I2C state service routines
- 15.10.8 Initialization
- 15.10.9 I2C interrupt service
- 15.10.10 The state service routines
- 15.10.11 Adapting state services to an application
- 15.11 Software example
- Chapter 16: LPC111x/LPC11Cxx C_CAN controller
- 16.1 How to read this chapter
- 16.2 Basic configuration
- 16.3 Features
- 16.4 General description
- 16.5 Pin description
- 16.6 Register description
- Baud rate prescaler
- Time segments 1 and 2
- Synchronization jump width
- 16.6.1.5 CAN interrupt register
- 16.6.1.6 CAN test register
- 16.6.1.7 CAN baud rate prescaler extension register
- 16.6.2 Message interface registers
- 16.6.2.1 Message objects
- 16.6.2.2 CAN message interface command request registers
- 16.6.2.3 CAN message interface command mask registers
- 16.6.2.4 IF1 and IF2 message buffer registers
- 16.6.2.4.1 CAN message interface mask 1 registers
- 16.6.2.4.2 CAN message interface mask 2 registers
- 16.6.2.4.3 CAN message interface c arbitration 1 registers
- 16.6.2.4.4 CAN message interface arbitration 2 registers
- 16.6.2.4.5 CAN message interface message control registers
- 16.6.2.4.6 CAN message interface data A1 registers
- 16.6.2.4.7 CAN message interface data A2 registers
- 16.6.2.4.8 CAN message interface data B1 registers
- 16.6.2.4.9 CAN message interface data B2 registers
- 16.6.3 Message handler registers
- 16.6.3.1 CAN transmission request 1 register
- 16.6.3.2 CAN transmission request 2 register
- 16.6.3.3 CAN new data 1 register
- 16.6.3.4 CAN new data 2 register
- 16.6.3.5 CAN interrupt pending 1 register
- 16.6.3.6 CAN interrupt pending 2 register
- 16.6.3.7 CAN message valid 1 register
- 16.6.3.8 CAN message valid 2 register
- 16.6.4 CAN timing register
- 16.7 Functional description
- 16.7.1 C_CAN controller state after reset
- 16.7.2 C_CAN operating modes
- 16.7.3 CAN message handler
- 16.7.3.1 Management of message objects
- 16.7.3.2 Data Transfer between IFx Registers and the Message RAM
- 16.7.3.3 Transmission of messages between the shift registers in the CAN core and the Message buffer
- 16.7.3.4 Acceptance filtering of received messages
- 16.7.3.5 Receive/transmit priority
- 16.7.3.6 Configuration of a transmit object
- 16.7.3.7 Updating a transmit object
- 16.7.3.8 Configuration of a receive object
- 16.7.3.9 Handling of received messages
- 16.7.3.10 Configuration of a FIFO buffer
- 16.7.4 Interrupt handling
- 16.7.5 Bit timing
- Chapter 17: LPC11Cxx C_CAN on-chip drivers
- 17.1 How to read this chapter
- 17.2 Features
- 17.3 General description
- 17.4 API description
- 17.4.1 Calling the C_CAN API
- 17.4.2 CAN initialization
- 17.4.3 CAN interrupt handler
- 17.4.4 CAN Rx message object configuration
- 17.4.5 CAN receive
- 17.4.6 CAN transmit
- 17.4.7 CANopen configuration
- 17.4.8 CANopen handler
- 17.4.9 CAN/CANopen callback functions
- 17.4.10 CAN message received callback
- 17.4.11 CAN message transmit callback
- 17.4.12 CAN error callback
- 17.4.13 CANopen SDO expedited read callback
- 17.4.14 CANopen SDO expedited write callback
- 17.4.15 CANopen SDO segmented read callback
- 17.4.16 CANopen SDO segmented write callback
- 17.4.17 CANopen fall-back SDO handler callback
- Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer CT16B0/1
- 18.1 How to read this chapter
- Pin-out variations
- 18.2 Basic configuration
- 18.3 Features
- 18.4 Applications
- 18.5 Description
- 18.6 Pin description
- 18.7 Register description
- 18.7.1 Interrupt Register (TMR16B0IR and TMR16B1IR)
- 18.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
- 18.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and TMR16B1TC - address 0x4001 0008)
- 18.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and TMR16B1PR - address 0x4001 000C)
- 18.7.5 Prescale Counter register (TMR16B0PC - address 0x4000 C010 and TMR16B1PC - address 0x4001 0010)
- 18.7.6 Match Control Register (TMR16B0MCR and TMR16B1MCR)
- 18.7.7 Match Registers (TMR16B0MR0/1/2/3 - addresses 0x4000 C018/1C/20/24 and TMR16B1MR0/1/2/3 - addresses 0x4001 0018/1C/20/24)
- 18.7.8 Capture Control Register (TMR16B0CCR and TMR16B1CCR)
- 18.7.9 Capture Register (CT16B0CR0 - address 0x4000 C02C and CT16B1CR0 - address 0x4001 002C)
- 18.7.10 External Match Register (TMR16B0EMR and TMR16B1EMR)
- 18.7.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
- 18.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
- 18.7.13 Rules for single edge controlled PWM outputs
- 18.8 Example timer operation
- 18.9 Architecture
- Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
- 19.1 How to read this chapter
- 19.2 Basic configuration
- 19.3 Features
- 19.4 Applications
- 19.5 Description
- 19.6 Pin description
- 19.7 Register description
- 19.7.1 Interrupt Register (TMR16B0IR and TMR16B1IR)
- 19.7.2 Timer Control Register (TMR16B0TCR and TMR16B1TCR)
- 19.7.3 Timer Counter (TMR16B0TC - address 0x4000 C008 and TMR16B1TC - address 0x4001 0008)
- 19.7.4 Prescale Register (TMR16B0PR - address 0x4000 C00C and TMR16B1PR - address 0x4001 000C)
- 19.7.5 Prescale Counter register (TMR16B0PC - address 0x4000 C010 and TMR16B1PC - address 0x4001 0010)
- 19.7.6 Match Control Register (TMR16B0MCR and TMR16B1MCR)
- 19.7.7 Match Registers (TMR16B0MR0/1/2/3 - addresses 0x4000 C018/1C/20/24 and TMR16B1MR0/1/2/3 - addresses 0x4001 0018/1C/20/24)
- 19.7.8 Capture Control Register (TMR16B0CCR and TMR16B1CCR)
- 19.7.9 Capture Register (CT16B0CR0/1 - address 0x4000 C02C/30 and CT16B1CR0/1 - address 0x4001 002C/30)
- 19.7.10 External Match Register (TMR16B0EMR and TMR16B1EMR)
- 19.7.11 Count Control Register (TMR16B0CTCR and TMR16B1CTCR)
- 19.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
- 19.7.13 Rules for single edge controlled PWM outputs
- 19.8 Example timer operation
- 19.9 Architecture
- Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer CT32B0/1
- 20.1 How to read this chapter
- 20.2 Basic configuration
- 20.3 Features
- 20.4 Applications
- 20.5 Description
- 20.6 Pin description
- 20.7 Register description
- 20.7.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
- 20.7.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR)
- 20.7.3 Timer Counter (TMR32B0TC - address 0x4001 4008 and TMR32B1TC - address 0x4001 8008)
- 20.7.4 Prescale Register (TMR32B0PR - address 0x4001 400C and TMR32B1PR - address 0x4001 800C)
- 20.7.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and TMR32B1PC - address 0x4001 8010)
- 20.7.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
- 20.7.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001 4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001 8018/1C/20/24)
- 20.7.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR)
- 20.7.9 Capture Register (TMR32B0CR0 - address 0x4001 402C and TMR32B1CR0 - address 0x4001 802C)
- 20.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
- 20.7.11 Count Control Register (TMR32B0CTCR and TMR32B1TCR)
- 20.7.12 PWM Control Register (TMR32B0PWMC and TMR32B1PWMC)
- 20.7.13 Rules for single edge controlled PWM outputs
- 20.8 Example timer operation
- 20.9 Architecture
- Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
- 21.1 How to read this chapter
- 21.2 Basic configuration
- 21.3 Features
- 21.4 Applications
- 21.5 Description
- 21.6 Pin description
- 21.7 Register description
- 21.7.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
- 21.7.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR)
- 21.7.3 Timer Counter (TMR32B0TC - address 0x4001 4008 and TMR32B1TC - address 0x4001 8008)
- 21.7.4 Prescale Register (TMR32B0PR - address 0x4001 400C and TMR32B1PR - address 0x4001 800C)
- 21.7.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and TMR32B1PC - address 0x4001 8010)
- 21.7.6 Match Control Register (TMR32B0MCR and TMR32B1MCR)
- 21.7.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001 4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001 8018/1C/20/24)
- 21.7.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR)
- 21.7.9 Capture Register (TMR32B0CR0/1 - address 0x4001 402C/30 and TMR32B1CR0/1 - address 0x4001 802C/30)
- 21.7.10 External Match Register (TMR32B0EMR and TMR32B1EMR)
- 21.7.11 Count Control Register (TMR32B0CTCR and TMR32B1TCR)
- 21.7.12 PWM Control Register (TMR32B0PWMC and TMR32B1PWMC)
- 21.8 Functional description
- 21.9 Architecture
- Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
- Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
- Chapter 24: LPC111x/LPC11Cxx System tick timer (SysTick)
- Chapter 25: LPC111x/LPC11Cxx ADC
- Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
- 26.1 How to read this chapter
- 26.2 Features
- 26.3 General description
- 26.3.1 Bootloader
- 26.3.2 Memory map after any reset
- 26.3.3 Criterion for Valid User Code
- 26.3.4 Boot process flowchart
- 26.3.5 Flash configuration for LPC1100, LPC1100C, LPC1100L series
- 26.3.6 Flash configuration for LPC1100XL series
- 26.3.7 Flash content protection mechanism
- 26.3.8 Code Read Protection (CRP)
- 26.4 UART Communication protocol
- 26.4.1 UART ISP command format
- 26.4.2 UART ISP response format
- 26.4.3 UART ISP data format
- 26.4.4 UART ISP flow control
- 26.4.5 UART ISP command abort
- 26.4.6 Interrupts during UART ISP
- 26.4.7 Interrupts during IAP
- 26.4.8 RAM used by ISP command handler (for LPC11Cxx parts)
- 26.4.9 RAM used by ISP command handler (for LPC111x parts)
- 26.4.10 RAM used by IAP command handler
- 26.5 UART ISP commands
- 26.5.1 Unlock <Unlock code> (UART ISP)
- 26.5.2 Set Baud Rate <Baud Rate> <stop bit> (UART ISP)
- 26.5.3 Echo <setting> (UART ISP)
- 26.5.4 Write to RAM <start address> <number of bytes> (UART ISP)
- 26.5.5 Read Memory <address> <no. of bytes> (UART ISP)
- 26.5.6 Prepare sector(s) for write operation <start sector number> <end sector number> (UART ISP)
- 26.5.7 Copy RAM to flash <Flash address> <RAM address> <no of bytes> (UART ISP)
- 26.5.8 Go <address> <mode> (UART ISP)
- 26.5.9 Erase sector(s) <start sector number> <end sector number> (UART ISP)
- 26.5.10 Blank check sector(s) <sector number> <end sector number> (UART ISP)
- 26.5.11 Read Part Identification number (UART ISP)
- 26.5.12 Read Boot code version number (UART ISP)
- 26.5.13 Compare <address1> <address2> <no of bytes> (UART ISP)
- 26.5.14 ReadUID (UART ISP)
- 26.5.15 UART ISP Return Codes
- 26.6 C_CAN communication protocol
- 26.6.1 C_CAN ISP SDO communication
- 26.6.2 C_CAN ISP object directory
- 26.6.3 Unlock (C_CAN ISP)
- 26.6.4 Write to RAM (C_CAN ISP)
- 26.6.5 Read memory (C_CAN ISP)
- 26.6.6 Prepare sectors for write operation (C_CAN ISP)
- 26.6.7 Copy RAM to flash (C_CAN ISP)
- 26.6.8 Go (C_CAN ISP)
- 26.6.9 Erase sectors (C_CAN ISP)
- 26.6.10 Blank check sectors (C_CAN ISP)
- 26.6.11 Read PartID (C_CAN ISP)
- 26.6.12 Read boot code version (C_CAN ISP)
- 26.6.13 Read serial number (C_CAN ISP)
- 26.6.14 Compare (C_CAN ISP)
- 26.6.15 C_CAN ISP SDO abort codes
- 26.6.16 Differences to fully-compliant CANopen
- 26.7 IAP commands
- 26.7.1 Prepare sector(s) for write operation (IAP)
- 26.7.2 Copy RAM to flash (IAP)
- 26.7.3 Erase Sector(s) (IAP)
- 26.7.4 Blank check sector(s) (IAP)
- 26.7.5 Read Part Identification number (IAP)
- 26.7.6 Read Boot code version number (IAP)
- 26.7.7 Compare <address1> <address2> <no of bytes> (IAP)
- 26.7.8 Reinvoke ISP (IAP)
- 26.7.9 ReadUID (IAP)
- 26.7.10 Erase page
- 26.7.11 IAP Status Codes
- 26.8 Debug notes
- 26.9 Flash memory access
- 26.10 Flash signature generation
- Signature generation
- Content verification
- Chapter 27: LPC111x/LPC11Cxx Serial Wire Debug (SWD)
- Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
- 28.1 How to read this chapter
- 28.2 Introduction
- 28.3 About the Cortex-M0 processor and core peripherals
- 28.4 Processor
- 28.5 Instruction set
- 28.5.1 Instruction set summary
- 28.5.2 Intrinsic functions
- 28.5.3 About the instruction descriptions
- 28.5.4 Memory access instructions
- 28.5.5 General data processing instructions
- 28.5.6 Branch and control instructions
- 28.5.7 Miscellaneous instructions
- 28.6 Peripherals
- 28.6.1 About the ARM Cortex-M0
- 28.6.2 Nested Vectored Interrupt Controller
- 28.6.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
- 28.6.2.2 Interrupt Set-enable Register
- 28.6.2.3 Interrupt Clear-enable Register
- 28.6.2.4 Interrupt Set-pending Register
- 28.6.2.5 Interrupt Clear-pending Register
- 28.6.2.6 Interrupt Priority Registers
- 28.6.2.7 Level-sensitive and pulse interrupts
- 28.6.2.8 NVIC usage hints and tips
- 28.6.3 System Control Block
- 28.6.3.1 The CMSIS mapping of the Cortex-M0 SCB registers
- 28.6.3.2 CPUID Register
- 28.6.3.3 Interrupt Control and State Register
- 28.6.3.4 Application Interrupt and Reset Control Register
- 28.6.3.5 System Control Register
- 28.6.3.6 Configuration and Control Register
- 28.6.3.7 System Handler Priority Registers
- 28.6.3.8 SCB usage hints and tips
- 28.6.4 System timer, SysTick
- 28.7 Cortex-M0 instruction summary
- Chapter 29: Supplementary information