UM10139 LPC214x User Manual LPC2148
User Manual:
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- Chapter 1: Introductory information
- Chapter 2: LPC214x Memory mapping
- Chapter 3: LPC214x Memory accelerator module
- Chapter 4: LPC214x System control
- 4.1 Summary of system control block functions
- 4.2 Pin description
- 4.3 Register description
- 4.4 Crystal oscillator
- 4.5 External interrupt inputs
- 4.5.1 Register description
- 4.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)
- 4.5.3 Interrupt Wakeup register (INTWAKE - 0xE01F C144)
- 4.5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)
- 4.5.5 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
- 4.5.6 Multiple external interrupt pins
- 4.6 Other system controls
- 4.7 Memory mapping control
- 4.8 Phase Locked Loop (PLL)
- 4.8.1 Register description
- 4.8.2 PLL Control register (PLL0CON - 0xE01F C080, PLL1CON - 0xE01F C0A0)
- 4.8.3 PLL Configuration register (PLL0CFG - 0xE01F C084, PLL1CFG - 0xE01F C0A4)
- 4.8.4 PLL Status register (PLL0STAT - 0xE01F C088, PLL1STAT - 0xE01F C0A8)
- 4.8.5 PLL Interrupt
- 4.8.6 PLL Modes
- 4.8.7 PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED - 0xE01F C0AC)
- 4.8.8 PLL and Power-down mode
- 4.8.9 PLL frequency calculation
- 4.8.10 Procedure for determining PLL settings
- 4.8.11 PLL0 and PLL1 configuring examples
- 4.9 Power control
- 4.10 Reset
- 4.11 APB divider
- 4.12 Wakeup timer
- 4.13 Brown-out detection
- 4.14 Code security vs. debugging
- Chapter 5: LPC214x Pin configuration
- Chapter 6: LPC214x Pin connect block
- Chapter 7: LPC214x VIC
- 7.1 Features
- 7.2 Description
- 7.3 Register description
- 7.4 VIC registers
- 7.4.1 Software Interrupt register (VICSoftInt - 0xFFFF F018)
- 7.4.2 Software Interrupt Clear register (VICSoftIntClear - 0xFFFF F01C)
- 7.4.3 Raw Interrupt status register (VICRawIntr - 0xFFFF F008)
- 7.4.4 Interrupt Enable register (VICIntEnable - 0xFFFF F010)
- 7.4.5 Interrupt Enable Clear register (VICIntEnClear - 0xFFFF F014)
- 7.4.6 Interrupt Select register (VICIntSelect - 0xFFFF F00C)
- 7.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)
- 7.4.8 FIQ Status register (VICFIQStatus - 0xFFFF F004)
- 7.4.9 Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C)
- 7.4.10 Vector Address registers 0-15 (VICVectAddr0-15 - 0xFFFF F100-13C)
- 7.4.11 Default Vector Address register (VICDefVectAddr - 0xFFFF F034)
- 7.4.12 Vector Address register (VICVectAddr - 0xFFFF F030)
- 7.4.13 Protection Enable register (VICProtection - 0xFFFF F020)
- 7.5 Interrupt sources
- 7.6 Spurious interrupts
- 7.7 VIC usage notes
- Chapter 8: LPC214x GPIO
- 8.1 Features
- 8.2 Applications
- 8.3 Pin description
- 8.4 Register description
- 8.4.1 GPIO port Direction register (IODIR, Port 0: IO0DIR - 0xE002 8008 and Port 1: IO1DIR - 0xE002 8018; FIODIR, Port 0: FIO0DIR - 0x3FFF C000 and Port 1:FIO1DIR - 0x3FFF C020)
- 8.4.2 Fast GPIO port Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK - 0x3FFF C030)
- 8.4.3 GPIO port Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000 and Port 1: IO1PIN - 0xE002 8010; FIOPIN, Port 0: FIO0PIN - 0x3FFF C014 and Port 1: FIO1PIN - 0x3FFF C034)
- 8.4.4 GPIO port output Set register (IOSET, Port 0: IO0SET - 0xE002 8004 and Port 1: IO1SET - 0xE002 8014; FIOSET, Port 0: FIO0SET - 0x3FFF C018 and Port 1: FIO1SET - 0x3FFF C038)
- 8.4.5 GPIO port output Clear register (IOCLR, Port 0: IO0CLR - 0xE002 800C and Port 1: IO1CLR - 0xE002 801C; FIOCLR, Port 0: FIO0CLR - 0x3FFF C01C and Port 1: FIO1CLR - 0x3FFF C03C)
- 8.5 GPIO usage notes
- Chapter 9: LPC214x USB Device
- 9.1 Introduction
- 9.2 Features
- 9.3 Fixed endpoint configuration
- 9.4 Architecture
- 9.5 Data flow
- 9.6 Interfaces
- Soft connect
- Good link
- 9.7 USB device register definitions
- 9.7.1 USB Interrupt Status register (USBIntSt - 0xE01F C1C0)
- 9.7.2 USB Device Interrupt Status register (USBDevIntSt - 0xE009 0000)
- 9.7.3 USB Device Interrupt Enable register (USBDevIntEn - 0xE009 0004)
- 9.7.4 USB Device Interrupt Clear register (USBDevIntClr - 0xE009 0008)
- 9.7.5 USB Device Interrupt Set register (USBDevIntSet - 0xE009 000C)
- 9.7.6 USB Device Interrupt Priority register (USBDevIntPri - 0xE009 002C)
- 9.7.7 USB Endpoint Interrupt Status register (USBEpIntSt - 0xE009 0030)
- 9.7.8 USB Endpoint Interrupt Enable register (USBEpIntEn - 0xE009 0034)
- 9.7.9 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xE009 0038)
- 9.7.10 USB Endpoint Interrupt Set register (USBEpIntSet - 0xE009 003C)
- 9.7.11 USB Endpoint Interrupt Priority register (USBEpIntPri - 0xE009 0040)
- 9.7.12 USB Realize Endpoint register (USBReEp - 0xE009 0044)
- 9.8 EP_RAM requirements
- 9.8.1 USB Endpoint Index register (USBEpIn - 0xE009 0048)
- 9.8.2 USB MaxPacketSize register (USBMaxPSize - 0xE009 004C)
- 9.8.3 USB Receive Data register (USBRxData - 0xE009 0018)
- 9.8.4 USB Receive Packet Length register (USBRxPLen - 0xE009 0020)
- 9.8.5 USB Transmit Data register (USBTxData - 0xE009 001C)
- 9.8.6 USB Transmit Packet Length register (USBTxPLen - 0xE009 0024)
- 9.8.7 USB Control register (USBCtrl - 0xE009 0028)
- 9.8.8 Slave mode data transfer
- 9.8.9 USB Command Code register (USBCmdCode - 0xE009 0010)
- 9.8.10 USB Command Data register (USBCmdData - 0xE009 0014)
- 9.8.11 USB DMA Request Status register (USBDMARSt - 0xE009 0050)
- 9.8.12 USB DMA Request Clear register (USBDMARClr - 0xE009 0054)
- 9.8.13 USB DMA Request Set register (USBDMARSet - 0xE009 0058)
- 9.8.14 USB UDCA Head register (USBUDCAH - 0xE009 0080)
- 9.8.15 USB EP DMA Status register (USBEpDMASt - 0xE009 0084)
- 9.8.16 USB EP DMA Enable register (USBEpDMAEn - 0xE009 0088)
- 9.8.17 USB EP DMA Disable register (USBEpDMADis - 0xE009 008C)
- 9.8.18 USB DMA Interrupt Status register (USBDMAIntSt - 0xE009 0090)
- 9.8.19 USB DMA Interrupt Enable register (USBDMAIntEn - 0xE009 0094)
- 9.8.20 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xE009 00A0)
- 9.8.21 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0xE009 00A4)
- 9.8.22 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0xE009 00A8)
- 9.8.23 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0xE009 00AC)
- 9.8.24 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xE009 00B0)
- 9.8.25 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0xE009 00B4)
- 9.8.26 USB System Error Interrupt Status register (USBSysErrIntSt - 0xE009 00B8)
- 9.8.27 USB System Error Interrupt Clear register (USBSysErrIntClr - 0xE009 00BC)
- 9.8.28 USB System Error Interrupt Set register (USBSysErrIntSet - 0xE009 00C0)
- 9.9 Protocol engine command description
- 9.9.1 Set Address (Command: 0xD0, Data: write 1 byte)
- 9.9.2 Configure Device (Command: 0xD8, Data: write 1 byte)
- 9.9.3 Set Mode (Command: 0xF3, Data: write 1 byte)
- 9.9.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes)
- 9.9.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
- 9.9.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
- 9.9.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
- 9.9.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
- 9.9.9 Read Error Status (Command: 0xFB, Data: read 1 byte)
- 9.9.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
- 9.9.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte)
- 9.9.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional))
- 9.9.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
- 9.9.14 Validate Buffer (Command: 0xFA, Data: none)
- 9.10 USB device controller initialization
- 9.11 DMA descriptor
- 9.11.1 Next_DD_pointer
- 9.11.2 DMA_mode
- 9.11.3 Next_DD_valid
- 9.11.4 Isochronous_endpoint
- 9.11.5 Max_packet_size
- 9.11.6 DMA_buffer_length
- 9.11.7 DMA_buffer_start_addr
- 9.11.8 DD_retired
- 9.11.9 DD_status
- 9.11.10 Packet_valid
- 9.11.11 LS_byte_extracted
- 9.11.12 MS_byte_extracted
- 9.11.13 Present_DMA_count
- 9.11.14 Message_length_position
- 9.11.15 Isochronous_packetsize_memory_address
- 9.12 DMA operation
- 9.13 Non isochronous endpoints - Normal mode operation
- 9.14 Concatenated transfer (ATLE) mode operation
- 9.15 Isochronous endpoint operation
- Chapter 10: LPC214x UART0
- 10.1 Features
- 10.2 Pin description
- 10.3 Register description
- 10.3.1 UART0 Receiver Buffer Register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only)
- 10.3.2 UART0 Transmit Holding Register (U0THR - 0xE000 C000, when DLAB = 0, Write Only)
- 10.3.3 UART0 Divisor Latch Registers (U0DLL - 0xE000 C000 and U0DLM - 0xE000 C004, when DLAB = 1)
- 10.3.4 UART0 Fractional Divider Register (U0FDR - 0xE000 C028)
- 10.3.5 UART0 baudrate calculation
- 10.3.6 UART0 Interrupt Enable Register (U0IER - 0xE000 C004, when DLAB = 0)
- 10.3.7 UART0 Interrupt Identification Register (U0IIR - 0xE000 C008, Read Only)
- 10.3.8 UART0 FIFO Control Register (U0FCR - 0xE000 C008)
- 10.3.9 UART0 Line Control Register (U0LCR - 0xE000 C00C)
- 10.3.10 UART0 Line Status Register (U0LSR - 0xE000 C014, Read Only)
- 10.3.11 UART0 Scratch pad register (U0SCR - 0xE000 C01C)
- 10.3.12 UART0 Auto-baud Control Register (U0ACR - 0xE000 C020)
- 10.3.13 Auto-baud
- 10.3.14 UART0 Transmit Enable Register (U0TER - 0xE000 C030)
- 10.4 Architecture
- Chapter 11: LPC214x UART1
- 11.1 Features
- 11.2 Pin description
- 11.3 Register description
- 11.3.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only)
- 11.3.2 UART1 Transmitter Holding Register (U1THR - 0xE001 0000, when DLAB = 0 Write Only)
- 11.3.3 UART1 Divisor Latch Registers 0 and 1 (U1DLL - 0xE001 0000 and U1DLM - 0xE001 0004, when DLAB = 1)
- 11.3.4 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)
- 11.3.5 UART1 baudrate calculation
- 11.3.6 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when DLAB = 0)
- 11.3.7 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)
- 11.3.8 UART1 FIFO Control Register (U1FCR - 0xE001 0008)
- 11.3.9 UART1 Line Control Register (U1LCR - 0xE001 000C)
- 11.3.10 UART1 Modem Control Register (U1MCR - 0xE001 0010)
- 11.3.11 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)
- 11.3.12 UART1 Modem Status Register (U1MSR - 0xE001 0018)
- 11.3.13 UART1 Scratch pad register (U1SCR - 0xE001 001C)
- 11.3.14 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020)
- 11.3.15 Auto-baud
- 11.3.16 Auto-baud Modes
- 11.3.17 UART1 Transmit Enable Register (U1TER - 0xE001 0030)
- 11.4 Architecture
- Chapter 12: LPC214x SPI
- Chapter 13: LPC214x SPI1/SSP
- 13.1 Features
- 13.2 Description
- 13.3 Bus description
- 13.3.1 Texas Instruments Synchronous Serial (SSI) frame format
- 13.3.2 SPI frame format
- 13.3.3 Clock Polarity (CPOL) and Clock Phase (CPHA) control
- 13.3.4 SPI format with CPOL=0,CPHA=0
- 13.3.5 SPI format with CPOL=0,CPHA=1
- 13.3.6 SPI format with CPOL = 1,CPHA = 0
- 13.3.7 SPI format with CPOL = 1,CPHA = 1
- 13.3.8 Semiconductor Microwire frame format
- 13.3.9 Setup and hold time requirements on CS with respect to SK in Microwire mode
- 13.4 Register description
- 13.4.1 SSP Control Register 0 (SSPCR0 - 0xE006 8000)
- 13.4.2 SSP Control Register 1 (SSPCR1 - 0xE006 8004)
- 13.4.3 SSP Data Register (SSPDR - 0xE006 8008)
- 13.4.4 SSP Status Register (SSPSR - 0xE006 800C)
- 13.4.5 SSP Clock Prescale Register (SSPCPSR - 0xE006 8010)
- 13.4.6 SSP Interrupt Mask Set/Clear register (SSPIMSC - 0xE006 8014)
- 13.4.7 SSP Raw Interrupt Status register (SSPRIS - 0xE006 8018)
- 13.4.8 SSP Masked Interrupt register (SSPMIS - 0xE006 801C)
- 13.4.9 SSP Interrupt Clear Register (SSPICR - 0xE006 8020)
- Chapter 14: LPC214x I2C-bus interface I2C0/1
- 14.1 Features
- 14.2 Applications
- 14.3 Description
- 14.4 Pin description
- 14.5 I2C operating modes
- 14.6 I2C implementation and operation
- 14.7 Register description
- 14.7.1 I2C Control Set Register (I2C[0/1]CONSET: 0xE001 C000, 0xE005 C000)
- 14.7.2 I2C Control Clear Register (I2C[0/1]CONCLR: 0xE001 C018, 0xE005 C018)
- 14.7.3 I2C Status Register (I2C[0/1]STAT - 0xE001 C004, 0xE005 C004)
- 14.7.4 I2C Data Register (I2C[0/1]DAT - 0xE001 C008, 0xE005 C008)
- 14.7.5 I2C Slave Address Register (I2C[0/1]ADR - 0xE001 C00C, 0xE005 C00C)
- 14.7.6 I2C SCL High Duty Cycle Register (I2C[0/1]SCLH - 0xE001 C010, 0xE005 C010)
- 14.7.7 I2C SCL Low Duty Cycle Register (I2C[0/1]SCLL - 0xE001 C014, 0xE005 C014)
- 14.7.8 Selecting the appropriate I2C data rate and duty cycle
- 14.8 Details of I2C operating modes
- 14.8.1 Master Transmitter mode
- 14.8.2 Master Receiver mode
- 14.8.3 Slave Receiver mode
- 14.8.4 Slave Transmitter mode
- 14.8.5 Miscellaneous states
- 14.8.6 Some special cases
- 14.8.7 Simultaneous repeated START conditions from two masters
- 14.8.8 Data transfer after loss of arbitration
- 14.8.9 Forced access to the I2C bus
- 14.8.10 I2C Bus obstructed by a Low level on SCL or SDA
- 14.8.11 Bus error
- 14.8.12 I2C State service routines
- 14.9 Software example
- 14.9.1 Initialization routine
- 14.9.2 Start master transmit function
- 14.9.3 Start master receive function
- 14.9.4 I2C interrupt routine
- 14.9.5 Non mode specific states
- 14.9.6 Master states
- 14.9.7 Master Transmitter states
- 14.9.8 Master Receive states
- 14.9.9 Slave Receiver states
- 14.9.10 Slave Transmitter States
- Chapter 15: LPC214x Timer
- 15.1 Features
- 15.2 Applications
- 15.3 Description
- 15.4 Pin description
- 15.5 Register description
- 15.5.1 Interrupt Register (IR, TIMER0: T0IR - 0xE000 4000 and TIMER1: T1IR - 0xE000 8000)
- 15.5.2 Timer Control Register (TCR, TIMER0: T0TCR - 0xE000 4004 and TIMER1: T1TCR - 0xE000 8004)
- 15.5.3 Count Control Register (CTCR, TIMER0: T0CTCR - 0xE000 4070 and TIMER1: T1CTCR - 0xE000 8070)
- 15.5.4 Timer Counter (TC, TIMER0: T0TC - 0xE000 4008 and TIMER1: T1TC - 0xE000 8008)
- 15.5.5 Prescale Register (PR, TIMER0: T0PR - 0xE000 400C and TIMER1: T1PR - 0xE000 800C)
- 15.5.6 Prescale Counter Register (PC, TIMER0: T0PC - 0xE000 4010 and TIMER1: T1PC - 0xE000 8010)
- 15.5.7 Match Registers (MR0 - MR3)
- 15.5.8 Match Control Register (MCR, TIMER0: T0MCR - 0xE000 4014 and TIMER1: T1MCR - 0xE000 8014)
- 15.5.9 Capture Registers (CR0 - CR3)
- 15.5.10 Capture Control Register (CCR, TIMER0: T0CCR - 0xE000 4028 and TIMER1: T1CCR - 0xE000 8028)
- 15.5.11 External Match Register (EMR, TIMER0: T0EMR - 0xE000 403C; and TIMER1: T1EMR - 0xE000 803C)
- 15.6 Example timer operation
- 15.7 Architecture
- Chapter 16: LPC214x PWM
- 16.1 Features
- 16.2 Description
- 16.3 Pin description
- 16.4 Register description
- 16.4.1 PWM Interrupt Register (PWMIR - 0xE001 4000)
- 16.4.2 PWM Timer Control Register (PWMTCR - 0xE001 4004)
- 16.4.3 PWM Timer Counter (PWMTC - 0xE001 4008)
- 16.4.4 PWM Prescale Register (PWMPR - 0xE001 400C)
- 16.4.5 PWM Prescale Counter register (PWMPC - 0xE001 4010)
- 16.4.6 PWM Match Registers (PWMMR0 - PWMMR6)
- 16.4.7 PWM Match Control Register (PWMMCR - 0xE001 4014)
- 16.4.8 PWM Control Register (PWMPCR - 0xE001 404C)
- 16.4.9 PWM Latch Enable Register (PWMLER - 0xE001 4050)
- Chapter 17: LPC214x WDT
- Chapter 18: LPC214x RTC
- 18.1 Features
- 18.2 Description
- 18.3 Architecture
- 18.4 Register description
- 18.4.1 RTC interrupts
- 18.4.2 Miscellaneous register group
- 18.4.3 Interrupt Location Register (ILR - 0xE002 4000)
- 18.4.4 Clock Tick Counter Register (CTCR - 0xE002 4004)
- 18.4.5 Clock Control Register (CCR - 0xE002 4008)
- 18.4.6 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
- 18.4.7 Alarm Mask Register (AMR - 0xE002 4010)
- 18.4.8 Consolidated time registers
- 18.4.9 Consolidated Time register 0 (CTIME0 - 0xE002 4014)
- 18.4.10 Consolidated Time register 1 (CTIME1 - 0xE002 4018)
- 18.4.11 Consolidated Time register 2 (CTIME2 - 0xE002 401C)
- 18.4.12 Time counter group
- 18.4.13 Leap year calculation
- 18.4.14 Alarm register group
- 18.5 RTC usage notes
- 18.6 Reference clock divider (prescaler)
- 18.7 RTC external 32 kHz oscillator component selection
- Chapter 19: LPC214x ADC
- 19.1 Features
- 19.2 Description
- 19.3 Pin description
- 19.4 Register description
- 19.4.1 A/D Control Register (AD0CR - 0xE003 4000 and AD1CR - 0xE006 0000)
- 19.4.2 A/D Global Data Register (AD0GDR - 0xE003 4004 and AD1GDR - 0xE006 0004)
- 19.4.3 A/D Global Start Register (ADGSR - 0xE003 4008)
- 19.4.4 A/D Status Register (ADSTAT, ADC0: AD0CR - 0xE003 4030 and ADC1: AD1CR - 0xE006 0030)
- 19.4.5 A/D Interrupt Enable Register (ADINTEN, ADC0: AD0INTEN - 0xE003 400C and ADC1: AD1INTEN - 0xE006 000C)
- 19.4.6 A/D Data Registers (ADDR0 to ADDR7, ADC0: AD0DR0 to AD0DR7 - 0xE003 4010 to 0xE003 402C and ADC1: AD1DR0 to AD1DR7- 0xE006 0010 to 0xE006 402C)
- 19.5 Operation
- Chapter 20: LPC214x DAC
- Chapter 21: LPC214x Flash memory
- 21.1 Flash boot loader
- 21.2 Features
- 21.3 Applications
- 21.4 Description
- 21.4.1 Memory map after any reset
- 21.4.2 Criterion for valid user code
- 21.4.3 Communication protocol
- 21.4.4 ISP command format
- 21.4.5 ISP response format
- 21.4.6 ISP data format
- 21.4.7 ISP flow control
- 21.4.8 ISP command sbort
- 21.4.9 Interrupts during ISP
- 21.4.10 Interrupts during IAP
- 21.4.11 RAM used by ISP command handler
- 21.4.12 RAM used by IAP command handler
- 21.4.13 RAM used by RealMonitor
- 21.4.14 Boot process flowchart
- 21.5 Sector numbers
- 21.6 Flash content protection mechanism
- 21.7 Code Read Protection (CRP)
- 21.8 ISP commands
- 21.8.1 Unlock <unlock code>
- 21.8.2 Set Baud Rate <baud rate> <stop bit>
- 21.8.3 Echo <setting>
- 21.8.4 Write to RAM <start address> <number of bytes>
- 21.8.5 Read memory <address> <no. of bytes>
- 21.8.6 Prepare sector(s) for write operation <start sector number> <end sector number>
- 21.8.7 Copy RAM to Flash <Flash address> <RAM address> <no of bytes>
- 21.8.8 Go <address> <mode>
- 21.8.9 Erase sector(s) <start sector number> <end sector number>
- 21.8.10 Blank check sector(s) <sector number> <end sector number>
- 21.8.11 Read Part Identification number
- 21.8.12 Read Boot code version number
- 21.8.13 Compare <address1> <address2> <no of bytes>
- 21.8.14 ISP Return codes
- 21.9 IAP Commands
- 21.10 JTAG flash programming interface
- Chapter 22: LPC214x Embedded ICE
- Chapter 23: LPC214x Embedded Trace
- Chapter 24: LPC214x RealMonitor
- Chapter 25: Supplementary information