LA 3803P Latitude E6400 Discrete
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A
B
C
D
E
COMPAL CONFIDENTIAL
1
MODEL NAME : JBL01
PCB NO : LA-3803P ( DAA00000O1L)
BOM P/N : 43152231L01
1
M09 Roush DIS
uFCPGA Mobile Penryn
Intel Cantiga PM + ICH9M
2
2
2008-06-12
REV : 1.0(A00)
@ : Nopop Component
1@ : Use PCMCIA card only
2@ : Use Express card only
4@ : Use CHINA TPM only
5@ : Use Broadcom TPM only
6@ : All TPM Disabled for CCC - Depop D70, Pop R483
3
3
4
4
MB PCB
Part Number
DELL CONFIDENTIAL/PROPRIETARY
Description
DAA00000O0L
PCB 03J LA-3803P REV0 M/B DIS
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
A
B
C
D
Title
Cover Sheet
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
E
1
of
71
A
B
Block Diagram
Compal confidential
Model : JBL01
FAN
C
Pentium-M
Penryn -4MB (Socket P)
+1.5V_RUN
uFCPGA CPU
Thermal
GUARDIAN III
EMC4002
+FAN1_VOUT
page 18
+3.3V_SUS
E
Clock Generator
CK505
SLG8LP554
CPU ITP Port
+1.05V_VCCP
page 18
+VCC_CORE
1
D
+1.05V_VCCP
+3.3V_M
page 7
page6
page 7,8,9
478pin
CRT CONN
+5V_RUN
1
page 20
Video Switch
TS3DV520
VGA/SVID
+3.3V_RUN page 20
H_A#(3..35)
VGA
SVID
NV G98
LVDS CONN
+3.3V_RUN
PCIE-E 16X
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
page 16,17
INTEL
+1.1V_GFX_PCIE
+1.5V_RUN
on M/B Board
+PWR_SRC
page 51,52,53,54,55,56
D PC
+1.8V_MEM
+1.8V_MEM 667/800 MHz
1329pin BGA
+1.8V_MEM
page 19
+0.9V_DDR_VTT
Memory BUS (DDR2)
Cantiga
+GPU_CORE
+5V_ALW
DDRII-DIMM X2
FSB 1066 MHz
+FBVDDQ
+3.3V_RUN
LVDS
H_D#(0..63)
System Bus
+1.05V_VCCP
Trough LVDS Cable
USB Port
Camera
USB[11]
+3.3V_RUN
+1.05V_M
DP Switch
TS2DP512
+5V_RUN
DMI
page 21
PCI BUS
+3VRUN 33MHz
IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)
CardBus
R5C847
page 21
+1.8V_LAN_M page 35
+3.3V_RUN
DAI
+5V_RUN
+RTC_CELL
page 31,32
SD CONN
IEEE1394
page 42
+3.3V_RUN
page 31
SATA5
USB[7]
USB[0,1] RIGHT SIDE
On IO/B
676pin BGA
+3.3V_ALW_ICH
Intel Boaz
82567LF
S-ATA(4)
PCIE2
Mini Card 3
WPAN/BT/Robson
3
DC IN
+3.3V_RUN
+2.5V_RUN
+1.2V_RUN
+RTC_CELL
page 43
+5V_HDD
Azalia Codec
92HD71B
page 26
+3.3V_RUN
+VDDA
page 27
TPM 1.2 USB[10]
page 43
Dig. MIC
page 19
DAI
S SM2602
page 38
ME & LED
1.8V/1.25V/0.9V
4
SNIFFER
USBH
M DC
page 36
+3V_SUS
SMBus
For China
+3.3V_RUN
Smart Card
page 29
On IO/B
+VDDA
32M 4K sector
MEC5035
+RTC_CELL
+3.3V_ALW
page 36
3
page 28
+3.3V_LANpage 24
SMSC KBC
TPM 1.2
SSX35BCB
+3.3V_RUN
page 36
page 41
+5V_RUN
RJ45
Trough LVDS Cable
73S8009CN
BATT IN
AMP & INT.
Speaker
W25X32VSSIG
USH I/F
BCM5880
page 36
Power Sequence
page 29
S-HDD
+3.3V_RUN
SPI
LPC BUS
USB[5]
RFID
page 40
E-Module
+5V_MOD
page 26
+3V_RUN
33MHz
+3.3V_RUN
+1.5V_RUN page 34
USB[4]
DC/DC Interface
LPC BUS
Mini Card 1
WWAN
+3.3V_WLAN
+1.5V_RUN page 34
USB[6]
+1V_LAN_M
SATA0
PCIE1
Mini Card 2
WLAN
+3.3V_RUN
+1.5V_RUN page 34
+3.3V_ALW
page 30
+1.8V_LAN_M
page 22,23,24,25
SATA1
PCIE3
LAN Switch
P13L500
+3.3V_ALW
+1.05V_VCCP
PCI Express BUS
USB Ports X2
Azalia I/F
+3.3V_RUN
2
+5V_ALW
GLCI/LCI
+1.5V_RUN
Trough Cable
USB[8,9]
48MHz
INTEL
ICH9-M
+5V_ALW
SATA4
Charger USB Port X1
+5V_ALW
page 33
DP CONN
+5V_RUN
+PWR_SRC
E-SATA
USB Port1 X1
USB[2,3] LEFT SIDE
+1.5V_RUN
100MHz
2
DOCKING
PORT
page 19
page 10,11,12,13,14,15
DPB
+3.3V_RUN page 27
DOCKING
HeadPhone &
MIC Jack
+3.3V_RUN
BC
On IO/B
Option
page 42
page 46
VCORE (IMVP-6)
1.5V/1.05V
page 45
page 47
CHARGER
4
Biometric
+3.3V_RUN page 33
3V/5V
page 44
page 48
A
Trough Cable
B
ECE1077
+3.3V_ALW
page 39
Int.KBD &
Stick page
RJ11
Touch Pad
page 39
39
BC BUS
SMSC SIO
ECE5028
DELL CONFIDENTIAL/PROPRIETARY
DOCK LPC BUS
Block Diagram
Size
http://hobi-elektronika.net
C
Compal Electronics, Inc.
Title
+3.3V_ALW
page 37
Stick
Trough Cable
Document Number
Rev
0.8
LA-3803P
Date:
D
Thursday, June 12, 2008
Sheet
E
2
of
71
5
4
3
2
POWER STATES
USB PORT#
Signal
State
D
C
1
S0 (Full ON) / M0
SLP
S3#
SLP
S4#
SLP
S5#
S4
STATE#
SLP
M#
ALWAYS
PLANE
HIGH
HIGH
HIGH
HIGH
HIGH
ON
M
PLANE
SUS
PLANE
RUN
PLANE
ON
ON
ON
CLOCKS
DESTINATION
0
JUSB1 (Ext Right Side Top)
ON
1
JUSB1 (Ext Right Side Bottom)
JESA1 (Ext Left Side Top)
S3 (Suspend to RAM) / M1
LOW
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
OFF
ON
2
S4 (Suspend to DISK) / M1
LOW
HIGH
HIGH
LOW
HIGH
ON
ON
ON
OFF
ON
3
JESA1 (Ext Left Side Bottom)
S5 (SOFT OFF) / M1
LOW
HIGH
LOW
LOW
HIGH
ON
ON
ON
OFF
ON
4
WLAN
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
5
WWAN
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
LOW
ON
OFF
OFF
OFF
OFF
6
WPAN
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
7
Card Bus/Express card
8
DOCKING
9
DOCKING
10
USH->BIO
11
Camera
ICH9-M
PM TABLE
power
plane
+15V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+5V_ALW
+1.8V_MEM
+3.3V_RUN
+1.05V_M +1.05V_M
+3.3V_ALW_ICH
+1.8V_RUN
+3.3V_RTC_LDO
+1.5V_RUN
+3.3V_M
(M-OFF)
D
C
+0.9V_DDR_VTT
+GPU_CORE
+VCC_CORE
State
B
PCI EXPRESS
+1.05V_VCCP
+FBVDDQ
DESTINATION
Lane 1
MINI CARD-1 WWAN
S0
ON
ON
ON
ON
ON
Lane 2
MINI CARD-2 WLAN
S3
ON
ON
OFF
ON
OFF
Lane 3
MINI CARD-3 BT/UWB
S5 S4/AC
ON
OFF
OFF
ON
OFF
Lane 4
EXPRESS CARD
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
Lane 5
None
Lane 6
10/100/1G LAN
B
PCI TABLE
PCI DEVICE
IDSEL
REQ#/GNT#
PIRQ
R5C847
AD17
REQ#1 / GNT#1
PIRQ[B..D]
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Index and Config.
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
3
of
71
5
4
3
2
1
D
Refer to add-on
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
Power Rail
Size
Rev
0.8
LA-3803P
Date:
2
Document Number
Thursday, June 12, 2008
Sheet
1
4
of
71
5
4
3
2
1
D
D
C
C
Refer to add-on
B
B
A
A
Compal Electronics, Inc.
Title
SMBUS TOPOLOGY
Size
http://hobi-elektronika.net
5
4
3
Document Number
Rev
0.8
LA-3803P
Date:
2
Thursday, June 12, 2008
Sheet
1
5
of
71
5
4
3
+3.3V_M
2
266
100
33.3
0
0
1
133
100
33.3
0
1
0
200
100
33.3
1
0
1
166
100
2
1
1
2
2
0
1
@
2
1
R10
1
2
SATA_CLKREQ#
MINI3CLK_REQ#
EXPCLK_REQ#
1
2
X1
14.31818MHz_20P_1BX14318CC1A~D
2
1
C16
33P_0402_50V8J~D
33.3
1
R12
1
R14
2 +CK_VDD_REF
0_0603_5%~D
2 +CK_VDD_48
0_0603_5%~D
1
49
54
65
VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC
30
36
VDD_PCI
VDD_PCI
12
VDD_CPU
18
VDD_REF
40
0
333
100
33.3
1
0
1
100
100
33.3
1
1
0
400
100
33.3
CLK_XTAL_IN
Place crystal within
500 mils of CK505
C17
33P_0402_50V8J~D
2
1
5.2
VDD_A
7
SLG8LP554VTR VSS_A
8
CLK_XTAL_OUT
19
XTAL_OUT
<24> CLK_ICH_48M
<8,10> CPU_MCH_BSEL0
<8,10> CPU_MCH_BSEL1
FSA
41
USB_48MHz/FSLA
FSB
45
FSL_B/TEST_MODE
<8,10> CPU_MCH_BSEL2
CPU_MCH_BSEL2
2 10K_0402_5%~D
FSC
1
<37> CLK_PCI_5028
<31> CLK_PCI_PCM
<36> CLK_PCI_TPM
<29> CLK_PCI_TPM_CHA
<35> CLK_PCI_DOCK
@ R51
10K_0402_5%~D
<24> CLK_ICH_14M
<37> CLK_SIO_14M
@ R55
10K_0402_5%~D
<50> CLK_NV_27M
2
<50> CLK_NVSS_27M
<22> CLK_PCI_ICH
B
1
CLK_PCI_5028
R26
CLK_PCI_PCM
R30
CLK_PCI_TPM
R29
CLK_PCI_TPM_CHA R854
CLK_PCI_DOCK
R27
2
2
1
1
1
PCI_SIO
34
PCICLK4/FCT_SEL
33
PCICLK3
CLK_PCI_5035
R32
2
1 43_0402_5%~D
PCI_DOCKING
32
PCICLK2/TME
PCI_EC
27
PCICLK1
CLK_ICH_14M
CLK_SIO_14M
R33
R35
1
1
2 22_0402_5%~D
2 22_0402_5%~D
CLKREF
22
CLK_NV_27M
R37
REF_1
2
1 33_0402_5%~D
CLK_NV
43
DOT_96/27M
CLK_NVSS_27M
CLK_PCI_ICH
R38
1
2 33_0402_5%~D
CLK_NVSS
44
DOT_96#/27M_SS
R41
2
1 33_0402_5%~D
PCI_ICH
37
1
1
2
2
2
39
*
PIN 32
0
overclocking enabled
1
overclocling disabled
CLK_SCLK
+3.3V_RUN
16
CLK_SDATA
R46
10K_0402_5%~D
ITP_EN
PCI_ICH
*
Pin 5/6 as SRC_10
1
Pin 5/6 as CPU_ITP
2
1
1
R54
10K_0402_5%~D
2
R50
10K_0402_5%~D
FCTSEL1
@
*
PIN43
PIN44
PIN47
PIN48
0=UMA
DOT96T
DOT96C
96/100M_T
96/100M_C
1=DIS
27M_out
27M SSout
SRCT0
SRCC0
H_STP_CPU#
CPU_1
11
MCH_BCLK
CPU_1#
10
MCH_BCLK#
CPU_0
14
CPU_BCLK
CPU_0#
13
CPU_BCLK#
CPU_ITP/SRC_10
6
CPU_ITP
CPU_ITP#/SRC_10#
5
CPU_ITP#
SRC_9
3
PCIE_MINI1
SRC_9#
2
PCIE_MINI1#
CLKREQ_9#
72
MINI1CLK_REQ#
SRC_8
70
PCIE_MINI2
SRC_8#
69
PCIE_MINI2#
CLKREQ_8#
71
MINI2CLK_REQ#
SRC_7
66
PCIE_ICH
PCIE_ICH#
SRC_7#
67
CLKREQ_7#
38
SRC_6
63
PCIE_MINI3
SRC_6#
64
PCIE_MINI3#
CLKREQ_6#
62
MINI3CLK_REQ#
SRC_5
60
PCIE_VGA
PCIE_VGA#
PCICLK_F0/ITP_EN
CKPWRGD/PD#
SRC_5#
61
CLKREQ_5#
29
NC
SRC_4
58
PCIE_EXP
SRC_4#
59
PCIE_EXP#
CLKREQ_4#
57
SRC_3
55
56
SMBCLK
SMBDAT
4
VSS_SRC
SRC_3#
15
VSS_CPU
CLKREQ_3#
28
21
VSS_REF
SRC_2
52
31
VSS_PCI
SRC_2#
53
35
VSS_PCI
CLKREQ_2#
26
42
VSS_48
68
VSS_SRC
73
THRM_PAD
PIN 37
0
+3.3V_RUN
PCI_SIO
17
H_STP_PCI#
24
REF_0/FSL_C/TEST_SEL
PCI_TPM
5@
4@
43_0402_5%~D
22_0402_5%~D
43_0402_5%~D
22_0402_5%~D
33_0402_5%~D
23
9
TME
PCI_DOCKING
2
1
0_0402_5%~D
CLK_PWRGD
<24> CLK_PWRGD
R43
10K_0402_5%~D
2
+3.3V_RUN
1
2
FSA
1
2
<38> CLK_PCI_5035
R24
1
25
XTAL_IN
1 43_0402_5%~D
2 2.2K_0402_5%~D
2 0_0402_5%~D
R17
PCI_STP#
CPU_STP#
VDD_48
CLK_ICH_48M
R19 2
CPU_MCH_BSEL0 R22 1
CPU_MCH_BSEL1 R1044 1
+3.3V_M
A
20
1
R4
1
R5
1
R6
1
R7
1
R8
1
R356
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
D
+CK_VDD_A
2
2.2_0603_5%~D
2
0
MINI1CLK_REQ#
CLK_3GPLLREQ#
C
1
+3.3V_RUN
U1
1
5
0
2
CLK_CPU_BCLK
2
33_0402_5%~D
CLK_CPU_BCLK#
2
33_0402_5%~D
1
@ R18
1
@ R21
CLK_MCH_BCLK# <10>
C
CLK_CPU_BCLK <7>
CLK_CPU_BCLK# <7>
CLK_CPU_ITP
2
33_0402_5%~D
CLK_CPU_ITP#
2
33_0402_5%~D
CLK_CPU_ITP <7>
CLK_CPU_ITP# <7>
1
R23
1
R25
CLK_PCIE_MINI1
2
33_0402_5%~D
CLK_PCIE_MINI1#
2
33_0402_5%~D
1
R28
1
R31
CLK_PCIE_MINI2
2
33_0402_5%~D
CLK_PCIE_MINI2#
2
33_0402_5%~D
1
R34
1
R36
CLK_PCIE_ICH
2
33_0402_5%~D
CLK_PCIE_ICH#
2
33_0402_5%~D
1
R39
1
R40
CLK_PCIE_MINI3
2
33_0402_5%~D
CLK_PCIE_MINI3#
2
33_0402_5%~D
1
R42
1
R44
CLK_PCIE_VGA
2
33_0402_5%~D
CLK_PCIE_VGA#
2
33_0402_5%~D
1
R408
1
R415
CLK_PCIE_EXP
2
33_0402_5%~D
CLK_PCIE_EXP#
2
33_0402_5%~D
CLK_PCIE_MINI1 <34>
CLK_PCIE_MINI1# <34>
MINI1CLK_REQ# <34>
CLK_PCIE_MINI2 <34>
CLK_PCIE_MINI2# <34>
MINI2CLK_REQ# <34>
CLK_PCIE_ICH <24>
CLK_PCIE_ICH# <24>
CLK_PCIE_MINI3 <34>
CLK_PCIE_MINI3# <34>
B
MINI3CLK_REQ# <34>
CLK_PCIE_VGA <50>
CLK_PCIE_VGA# <50>
CLK_PCIE_EXP <32>
CLK_PCIE_EXP# <32>
CLK_PCIE_SATA
2
33_0402_5%~D
CLK_PCIE_SATA#
2
33_0402_5%~D
2
475_0402_1%~D
CLK_PCIE_SATA# <23>
PCIE_SATA#
LCD_CLK#/SRC_0#
1
R15
1
R16
CLK_MCH_BCLK <10>
CLK_MCH_3GPLL# <10>
PCIE_SATA
48
CLK_MCH_BCLK
2
33_0402_5%~D
CLK_MCH_BCLK#
2
33_0402_5%~D
EXPCLK_REQ# <32>
51
47
1
R11
1
R13
CLK_MCH_3GPLL
2
33_0402_5%~D
CLK_MCH_3GPLL#
2
33_0402_5%~D
CLK_3GPLLREQ#
2
475_0402_1%~D
50
46
<24>
H_STP_CPU# <24>
1
R45
MCH_3GPLL#
1
R47
CLK_3GPLLREQ#_R 1
R48
SRC_1/SATA
CLKREQ_1#
2
H_STP_PCI#
MCH_3GPLL
SRC_1#/SATA#
LCD_CLK/SRC_0
1
C15
0.047U_0402_16V4Z~D
0
1
C14
4.7U_0603_6.3V4Z~D
PCI
MHz
2
C7
0.1U_0402_16V4Z~D
SRC
MHz
1
C6
0.1U_0402_16V4Z~D
*
CPU
MHz
2
C5
0.1U_0402_16V4Z~D
FSA
CLKSEL0
2
1
C10
0.1U_0402_16V4Z~D
FSB
CLKSEL1
1
2
C4
0.1U_0402_16V4Z~D
FSC
CLKSEL2
2
2
C13
0.047U_0402_16V7K~D
2
1
@
1
+CK_VDD_REF
C12
0.047U_0402_16V4Z~D
1
C11
4.7U_0603_6.3V4Z~D
1
2
@ R9
0_0402_5%~D
1
C9
0.1U_0402_16V4Z~D
+CK_VDD_48
C3
0.1U_0402_16V4Z~D
<27,38,48> CKG_SMBCLK
CLK_SCLK
2
C8
10U_0805_10V4Z~D
3
Q1B
2N7002DW-T/R7_SOT363-6~D
4
1
MINI2CLK_REQ#
1
2
@ L2
BLM21PG600SN1D_0805~D
+3.3V_M
D
+CK_VDD_MAIN2
2
C2
10U_0805_10V4Z~D
CLK_SDATA
Q1A
2N7002DW-T/R7_SOT363-6~D
1
R851
0_0805_5%~D
1
2
1
+CK_VDD_MAIN
1
2
L1
BK2125HS601-T 0805~D
C1
0.1U_0402_16V4Z~D
6
<27,38,48> CKG_SMBDAT
R2
2.2K_0402_5%~D
1
2
@ R3
0_0402_5%~D
R1
2.2K_0402_5%~D
1
+3.3V_M
1
2
+CK_VDD_MAIN
1
R49
1
R52
SATA_CLKREQ#_R 1
R53
CLK_MCH_3GPLL <10>
CLK_3GPLLREQ# <10>
CLK_PCIE_SATA <23>
SATA_CLKREQ# <24>
A
DELL CONFIDENTIAL/PROPRIETARY
SLG8LP554VTR_QFN72_10X10~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0=UMA
1=Disc. GRFX down
http://hobi-elektronika.net
5
4
3
Title
Clock Generator
Size
Rev
0.8
LA-3803P
Date:
2
Document Number
Thursday, June 12, 2008
Sheet
1
6
of
71
5
4
C
<10> H_ADSTB#1
A6
A5
C4
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
A20M#
FERR#
IGNNE#
IERR#
INIT#
H_IERR#
H_INIT#
LOCK#
H4
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
ITP_BPM#0
R1104
ITP_BPM#1
R1105
ITP_BPM#2
R1106
ITP_BPM#3
R1107
ITP_BPM#4
R1108
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
CONTROL
XDP/ITP SIGNALS
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
H_BR0# <10>
2
H_INIT#
R56
56_0402_5%~D
1
+1.05V_VCCP
<23>
H_LOCK#
<10>
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
<10>
<10>
<10>
<10>
<10>
<6> CLK_CPU_ITP
<6> CLK_CPU_ITP#
H_HIT#
<10>
H_HITM# <10>
1
1
1
1
1
2
2
2
2
2
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
@ R1103
1
2 0_0402_5%~D
ITP_DBRESET#R
@ R780
1
2 0_0402_5%~D
ITP_BPM#0R
@ R781
1
2 0_0402_5%~D
ITP_BPM#1R
@ R782
1
2 0_0402_5%~D
ITP_BPM#2R
@ R783
1
2 0_0402_5%~D
ITP_BPM#3R
@ R784
1
2 0_0402_5%~D
ITP_BPM#4R
@ R785
R57
@ R1111
1
1
1
2 0_0402_5%~D ITP_BPM#5R
2 124_0402_1%~D H_RESET#R
2 0_0402_5%~D ITP_TCK_R
CLK_CPU_ITP
CLK_CPU_ITP#
R58
1
2 22.6_0402_1%~DITP_TDO_R
ITP_TCK_R
@ R1109
@ R1112
@ R1113
+1.05V_VCCP
1
1
1
2 0_0402_5%~D
2 0_0402_5%~D
2 0_0402_5%~D
ITP_TRST#R
ITP_TMS_R
ITP_TDI_R
29
VTT1
VTT0
VTAP
DBR#
DBA#
BPM0#
GND5
BPM1#
GND4
BPM2#
GND3
BPM3#
GND2
BPM4#
GND1
BPM5#
RESET#
FBO
GND0
BCLKP
BCLKN
TDO
NC2
TCK
NC1
TRST#
TMS
TDI
JCPU1D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
MOLEX_52435-2891_28P~D
R59
56_0402_5%~D
ITP_DBRESET# <24>
EC_CPU_PROCHOT#
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D21
A24
B25
C7
H_THERMDA
2
H_THERMDC
H_THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_THERMDA <18>
+1.05V_VCCP
@ C18
100P_0402_50V8K~D
1
H_THERMDC <18>
H_THERMTRIP# <18>
CLK_CPU_BCLK <6>
CLK_CPU_BCLK# <6>
1
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
2
C20
0.1U_0402_16V4Z~D
H_A20M#
H_FERR#
H_IGNNE#
H_BR0#
D20
B3
H_DEFER# <10>
H_DRDY# <10>
H_DBSY# <10>
C19
0.1U_0402_16V4Z~D
H_STPCLK#
H_INTR
H_NMI
H_SMI#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
ICH
<23> H_A20M#
<23> H_FERR#
<23> H_IGNNE#
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
F1
BR0#
ADDR GROUP_1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_DEFER#
H_DRD Y#
H_DBSY#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND6
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H5
F21
E1
DEFER#
DRDY#
DBSY#
H_ADS# <10>
H_BNR# <10>
H_BPRI# <10>
30
K3
H2
K2
J3
L1
H_ADS#
H_BNR#
H_BPRI#
1
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H1
E2
G5
ADS#
BNR#
BPRI#
2
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
1
2
Place near JITP
RESERVED
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP_0
<10> H_ADSTB#0
JITP1
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
1
GND7
JCPU1A
D
<23>
<23>
<23>
<23>
2
+1.05V_VCCP
<10> H_A#[3..35]
<10>
<10>
<10>
<10>
<10>
3
+1.05V_VCCP
1
R61
TYCO_1-1674770-2_Penryn~D
+3.3V_ALW_ICH
2 H_THERMTRIP#
56_0402_5%~D
+1.05V_VCCP
+1.05V_VCCP
B
1
@ R912
ITP_DBRESET#
2
150_0402_5%~D
1
R60
ITP_BPM#5
2
51_0402_5%~D
Place close to CPU within 200 mil
1
R62
1
@ R63
1
R64
ITP_TDO
2
56_0402_5%~D
H_RESET#
2
51_0402_5%~D
ITP_TMS
2
39_0402_5%~D
This shall place near CPU
1
R67
ITP_TCK
2
27_0402_5%
Place close to JITP within 200ps = 1000 mil
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
D
C
B
TYCO_1-1674770-2_Penryn~D
+1.05V_VCCP
A
1
R65
ITP_TDI
2
150_0402_5%~D
1
R66
ITP_TRST#
2
649_0402_1%~D
A
Place close to CPU within 200ps = 1000 mil
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Penryn Processor(1/2)
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
7
of
71
5
4
3
2
1
+VCC_CORE
+VCC_CORE
JCPU1C
D
<10> H_D#[0..63]
JCPU1B
TYCO_1-1674770-2_Penryn~D
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
+1.05V_VCCP
1
+
2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE
C
CRB was 270uF
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
<47>
<47>
<47>
<47>
<47>
<47>
<47>
VCCSENSE
<47>
VSSSENSE
<47>
1
2
1
2
+1.5V_RUN
Length match within 25 mils, Z0=27.4 ohm
B
Place R75 and R76 near CPU
+VCC_CORE
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
BCLK
BSEL2
BSEL1
BSEL0
533
133
0
0
1
667
166
0
1
1
VCCSENSE=18 mils
1
R75
VCCSENSE
2
100_0402_1%~D
1
@ R833
1
R76
VSSSENSE
2
100_0402_1%~D
Reserve for testing
only
2
27.4_0402_1%~D
+1.05V_VCCP
Route VCCSENSE and VSSSENSE trace at
27.4 ohms, 7 mils spacing and R75 & R76
keep to pad max 1 inch
R77
1K_0402_1%~D
+V_CPU_GTLREF
800
200
0
1
0
1067
266
0
0
0
1
2
FSB
1
2
1
R73
1K_0402_5%~D
R72
1K_0402_5%~D
2
VCCA[01]
VCCA[02]
TEST3
TEST5
@ PAD~D T2
@ PAD~D T3
1
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.
TEST1
TEST2
@
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
D
TYCO_1-1674770-2_Penryn~D
B
@
1
<10,23,47>
<23>
<10>
<23>
<10>
<47>
2
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
1
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PW RGOOD
H_CPUSLP#
H_PSI#
2
E5
B5
D24
D6
D7
AE6
1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
2
COMP0
COMP1
COMP2
COMP3
1
DATA GRP 2
R26
U26
AA1
Y1
R71
27.4_0402_1%~D
COMP[0]
COMP[1]
COMP[2]
COMP[3]
MISC
R70
54.9_0402_1%~D
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
H_DSTBN#3 <10>
H_DSTBP#3 <10>
H_DINV#3 <10>
R69
27.4_0402_1%~D
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
R68
54.9_0402_1%~D
TEST1
TEST2
TEST3
TEST4
@ PAD~D T1
TEST5
TEST6
@ PAD~D T138
TEST7
@ PAD~D T4
CPU_MCH_BSEL0 1
2
<6,10> CPU_MCH_BSEL0
R1041 0_0402_5%~D
CPU_MCH_BSEL1 1
2
<6,10> CPU_MCH_BSEL1
R1042 0_0402_5%~D
CPU_MCH_BSEL2 1
2
<6,10> CPU_MCH_BSEL2
R1043 0_0402_5%~D
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_DSTBN#2 <10>
H_DSTBP#2 <10>
H_DINV#2 <10>
2
+V_CPU_GTLREF
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DATA GRP 3
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
C23
10U_0805_10V4Z~D
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
C22
0.01U_0402_16V7K~D
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
C21
220U_D2_4VY_R15M~D
<10> H_DSTBN#1
<10> H_DSTBP#1
<10> H_DINV#1
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 1
C
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 0
<10> H_DSTBN#0
<10> H_DSTBP#0
<10> H_DINV#0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A
A
2
R78
2K_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Penryn Processor(2/2)
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
8
of
71
5
4
3
2
1
+VCC_CORE
D
Place these inside 1
socket cavity on L8
(North side
Secondary)
2
1
C24
10U_0805_4VAM~D
2
1
C25
10U_0805_4VAM~D
2
1
C26
10U_0805_4VAM~D
2
1
C27
10U_0805_4VAM~D
C28
10U_0805_4VAM~D
2
1
1
2
C29
10U_0805_4VAM~D
2
1
C30
10U_0805_4VAM~D
2
1
C31
10U_0805_4VAM~D
2
1
C32
10U_0805_4VAM~D
2
C33
10U_0805_4VAM~D
D
+VCC_CORE
Place these inside 1
socket cavity on L8
(Sorth side
Secondary)
2
1
C34
10U_0805_4VAM~D
2
1
C35
10U_0805_4VAM~D
2
1
C36
10U_0805_4VAM~D
2
1
C37
10U_0805_4VAM~D
C38
10U_0805_4VAM~D
2
1
1
2
C39
10U_0805_4VAM~D
2
1
C40
10U_0805_4VAM~D
2
1
C41
10U_0805_4VAM~D
2
1
C42
10U_0805_4VAM~D
2
C43
10U_0805_4VAM~D
+VCC_CORE
Place these inside 1
socket cavity on L8
(North side
Primary)
2
1
C44
10U_0805_4VAM~D
2
1
C45
10U_0805_4VAM~D
2
1
C46
10U_0805_4VAM~D
2
1
C47
10U_0805_4VAM~D
1
C48
10U_0805_4VAM~D
2
2
C49
10U_0805_4VAM~D
+VCC_CORE
C
Place these inside 1
socket cavity on L8
(Sorth side
Primary)
2
1
C50
10U_0805_4VAM~D
2
1
C51
10U_0805_4VAM~D
2
1
C52
10U_0805_4VAM~D
2
1
C53
10U_0805_4VAM~D
10uF 0805 X6S -> 85 degree C
1
C54
10U_0805_4VAM~D
2
2
C55
10U_0805_4VAM~D
C
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE
+
2
1
+
2
@
1
+
2
1
+
@
2
C61
270U_X_2VM_R4.5M~D
2
1
C60
270U_X_2VM_R4.5M~D
+
C59
270U_X_2VM_R4.5M~D
2
1
C58
270U_X_2VM_R4.5M~D
+
C57
270U_X_2VM_R4.5M~D
1
C56
270U_X_2VM_R4.5M~D
South Side Secondary
North Side Secondary
@
ESR <= 1.5m ohm
Capacitor > 1320uF
B
B
+1.05V_VCCP
1
2
1
C62
0.1U_0402_10V7K~D
2
1
C63
0.1U_0402_10V7K~D
2
1
C64
0.1U_0402_10V7K~D
2
1
C65
0.1U_0402_10V7K~D
1
C66
0.1U_0402_10V7K~D
2
2
C67
0.1U_0402_10V7K~D
Place these inside
socket cavity on L8
(North side
Secondary)
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
CPU Bypass
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
9
of
71
5
4
3
2
1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<8>
<8>
<8>
<8>
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<8>
<8>
<8>
<8>
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
C12
E11
H_CPURST#
H_CPUSLP#
+H_VREF
H_ADS#
<7>
H_ADSTB#0
<7>
H_ADSTB#1
<7>
H_BNR#
<7>
H_BPRI#
<7>
H_BR0#
<7>
H_DEFER#
<7>
H_DBSY#
<7>
CLK_MCH_BCLK <6>
CLK_MCH_BCLK# <6>
H_DPWR#
<8>
H_DRDY#
<7>
H_HIT#
<7>
H_HITM# <7>
H_LOCK# <7>
H_TRDY#
<7>
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_RS#0
H_RS#1
H_RS#2
1
<7>
<7>
<7>
1
1
2
1
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
M_ODT0
M_ODT1
M_ODT2
M_ODT3
BD17
AY17
BF15
AY13
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SMRCOMP
SMRCOMP#
BG22
BH21
SM_RCOMP
SM_RCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
+V_DDR_MCH_REF AV42
SM_PWROK
AR36
499_0402_1%~D
BF17
TP_SM_DRAMRST#
BC36
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
B38
A38
E41
F41
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
F43
E43
PEG_CLK
PEG_CLK#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
AE41
AE37
AE47
AH39
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
AE40
AE38
AE48
AH40
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
AE35
AE43
AE46
AH42
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
AD35
AE44
AF46
AH43
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
T25
T26
T27
T28
T29
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
B33
B32
G33
F33
E33
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_ON
C34
GFX_VR_EN
2
<24> CL_CLK0
<24> CL_DATA0
<24,38> ICH_CL_PWROK
<24> CL_RST0#
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
+CL_VREF
@ PAD~D T31
<12> DDPC_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
<6> CLK_3GPLLREQ#
<24> MCH_ICH_SYNC#
AH37
AH36
AN36
AJ35
AH34
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CLK_3GPLLREQ#
MCH_ICH_SYNC#
N28
M28
G36
E36
K36
H36
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MCH_TSATN#
B12
TSATN#
ICH_AZ_MCH_BITCLK
ICH_AZ_MCH_RST#
ICH_AZ_MCH_SDIN2
ICH_AZ_MCH_SDOUT
ICH_AZ_MCH_SYNC
B28
B30
B29
C29
A28
2
C
3
1
1 2
R101
54.9_0402_1%~D
1
2
1
2 2
B
R104
E
330_0402_5%~D
Q4
MMST3904-7-F_SOT323-3~D
4
T32
T33
T34
T35
T36
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
TP_MCH_RSVD1
M36
TP_MCH_RSVD2
N36
TP_MCH_RSVD3
R33
TP_MCH_RSVD4
T33
TP_MCH_RSVD5
AH9
TP_MCH_RSVD6
AH10
TP_MCH_RSVD7
AH12
TP_MCH_RSVD8
AH13
TP_MCH_RSVD9
K12
ME_JTAG_TCK @ R804 1
AL34
ME_JTAG_TDI @ R805 1
AK34
ME_JTAG_TDO @ R806 1
AN35
ME_JTAG_TMS @ R807 1
AM35
TP_MCH_RSVD14
@ R1088 1
T24
RSVD15
RSVD16
RSVD17
B31
B2
M1
TP_MCH_RSVD15
TP_MCH_RSVD16
TP_MCH_RSVD17
T6
T7
T8
PAD~D@
PAD~D@
PAD~D@
RSVD20
AY21
TP_MCH_RSVD20
T9
PAD~D@
RSVD22
RSVD23
RSVD24
RSVD25
BG23
BF23
BH18
BF18
TP_MCH_RSVD22
TP_MCH_RSVD23
TP_MCH_RSVD24
TP_MCH_RSVD25
T10 PAD~D@
T11 PAD~D@
T12 PAD~D@
T159PAD~D@
T150PAD~D@
T151PAD~D@
T152PAD~D@
T153PAD~D@
T154PAD~D@
T155PAD~D@
T156PAD~D@
T157PAD~D@
2
2
2
2
2
PAD~D@
T5
100_0402_5%~D
T123 PAD~D@
100_0402_5%~D
T124 PAD~D@
100_0402_5%~D
T125 PAD~D@
100_0402_5%~D
51K_0402_1%~D +1.05V_VCCP
D
Reserve 100ohm
and Test point
for ME JTAG
debug
C
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
R29
B7
N33
P32
AT40
AT11
T20
R32
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
CPU_MCH_BSEL0 <6,8>
CPU_MCH_BSEL1 <6,8>
CPU_MCH_BSEL2 <6,8>
T14 PAD~D@
T15 PAD~D
@ <12>
CFG5
CFG6
<12>
CFG7
<12>
T16 PAD~D@
CFG9
<12>
T17 PAD~D@
T18 PAD~D@
T19 PAD~D@
T20 PAD~D@
T21 PAD~D@
T22 PAD~D@
CFG16
<12>
T23 PAD~D@
T24 PAD~D@
CFG19
<12>
CFG20
<12>
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_SYNC#
H_DPRSTP#
PM_EXTTS#
PM_SYNC#
H_DPRSTP#
PM_EXTTS#
I CH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
<24>
<8,23,47>
<18>
ICH_PWRGD <24,41>
B
THERMTRIP_MCH# <18>
DPRSLPVR
<24,47>
+3.3V_RUN
PM_EXTTS#
2
R84
1
10K_0402_5%~D
SM_PWROK
2
R86
1
0_0402_5%~D
Use for DDR3 signls,
if support DDR2 need
connect to GND
CANTIGA ES_FCBGA1329~D
A
PLTRST1#_R
2
R100
1
100_0402_5%~D
PLTRST1#
<22,32,50>
MCH_TSATN_EC <37>
C
THERMTRIP_MCH#
2
B
1
R102
2
56_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
+1.05V_VCCP
E
Compal Electronics, Inc.
3
1
2
+1.05V_VCCP
1
2
1
2
1
2
1
2
1
MCH_TSATN# 2
1
R103
0_0402_5%~D
5
<24>
<24>
<24>
<24>
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
+3.3V_RUN
R98
1K_0402_5%~D
1
R97
1K_0402_1%~D
2
1
2
1
2
C76
2.2U_0603_6.3V6K~D
2
1
SMRCOMP_VOL
C75
0.01U_0402_16V7K~D
2
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
BA17
AY16
AV16
AR13
NC
1
<24>
<24>
<24>
<24>
@ PAD~D
@ PAD~D
@ PAD~D
@ PAD~D
@ PAD~D
R99
1K_0402_5%~D
@
C74
0.1U_0402_16V7K~D
2
R95
100_0402_1%~D
A
C73
0.1U_0402_16V7K~D
R94
2K_0402_1%~D
2
C72
2.2U_0603_6.3V6K~D
H_SWNG
1
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SMRCOMP_VOH
C71
0.01U_0402_16V7K~D
+H_VREF
<24>
<24>
<24>
<24>
@ PAD~D T30
1
R87
499_0402_1%~D
1
R93
3.01K_0402_1%~D
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
+1.05V_M
<7>
<7>
<7>
<7>
<7>
R88
1K_0402_1%~D
R91
221_0402_1%~D
<24>
<24>
<24>
<24>
@ PAD~D
@ PAD~D
@ PAD~D
@ PAD~D
@ PAD~D
H_AVREF
H_DVREF
+1.05V_VCCP
1
2
@ PAD~D T13
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
<8>
<8>
<8>
<8>
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
+1.8V_MEM
R90
1K_0402_1%~D
2
R81
<6> CLK_MCH_3GPLL
<6> CLK_MCH_3GPLL#
CANTIGA ES_FCBGA1329~D
+1.05V_VCCP
1
C70
0.1U_0402_16V4Z~D
A11
B11
2
2
H_RESET#
H_CPUSLP#
H_RESET#
H_CPUSLP#
1
2
<7>
<8>
+V_DDR_MCH_REF
R83
1K_0402_1%~D
B
SMRCOMP
1
80.6_0402_1%~D
SMRCOMP#
1
80.6_0402_1%~D
2
R79
2
R80
M_ODT0
M_ODT1
M_ODT2
M_ODT3
BC28
AY28
AY36
BB36
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
CLK
J8
L3
Y13
Y1
<16>
<16>
<17>
<17>
+1.8V_MEM
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DMI
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
GRAPHICS VID
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPW R#
H_D RDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
<16>
<16>
<17>
<17>
AR24
AR21
AU24
AV20
ME
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
MISC
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
<16>
<16>
<17>
<17>
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
HDA
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
AP24
AT21
AV24
AU20
PM
H_SWING
H_RCOMP
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
<16>
<16>
<17>
<17>
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
CFG
C5
E3
<7>
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
RSVD
2
24.9_0402_1%~D
H_SWNG
+H_RCOMP
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
C69
0.1U_0402_16V4Z~D
C
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C68
0.1U_0402_16V4Z~D
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1
R82
H_A#[3..35]
U2A
H_D#[0..63]
HOST
<8>
D
<16>
<16>
<17>
<17>
DDR CLK/ CONTROL/COMPENSATION
U2B
Q3
MMST3904-7-F_SOT323-3~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
3
2
Title
Cantiga(1 of 6)
Size
Document Number
Date:
Thursday, June 12, 2008
Re v
0.8
LA-3803P
Sheet
1
10
of
71
5
4
3
2
1
D
D
DDR_A_D[0..63] <16>
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
BB20
BD20
AY20
SA_RAS#
SA_CAS#
SA_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
<16> DDR_A_MA[0..14]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
MEMORY
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SYSTEM
<16> DDR_A_DQS#[0..7]
DDR_A_DQS0
AJ44
DDR_A_DQS1
AT44
DDR_A_DQS2
BA43
DDR_A_DQS3
BC37
DDR_A_DQS4
AW12
DDR_A_DQS5
BC8
DDR_A_DQS6
AU8
DDR_A_DQS7
AM7
DDR_A_DQS#0 AJ43
DDR_A_DQS#1 AT43
DDR_A_DQS#2 BA44
DDR_A_DQS#3 BD37
DDR_A_DQS#4 AY12
DDR_A_DQS#5
BD8
DDR_A_DQS#6
AU9
DDR_A_DQS#7
AM8
DDR
<16> DDR_A_DQS[0..7]
C
A
<16> DDR_A_DM[0..7]
B
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D[0..63] <17>
U2E
<17> DDR_B_BS0
<17> DDR_B_BS1
<17> DDR_B_BS2
<17> DDR_B_RAS#
<17> DDR_B_CAS#
<17> DDR_B_WE#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
BC16
BB17
BB33
SB_BS_0
SB_BS_1
SB_BS_2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
AU17
BG16
BF14
SB_RAS#
SB_CAS#
SB_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
<17> DDR_B_DM[0..7]
<17> DDR_B_DQS[0..7]
<17> DDR_B_DQS#[0..7]
<17> DDR_B_MA[0..14]
CANTIGA ES_FCBGA1329~D
B
SA_BS_0
SA_BS_1
SA_BS_2
MEMORY
BD21
BG18
AT25
SYSTEM
<16> DDR_A_RAS#
<16> DDR_A_CAS#
<16> DDR_A_WE#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR
U2D
<16> DDR_A_BS0
<16> DDR_A_BS1
<16> DDR_A_BS2
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C
B
CANTIGA ES_FCBGA1329~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
Cantiga(2 of 6)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
11
of
71
5
4
3
2
Strap Pin Table
2
+VCC_PEG
Low = DMI x 2
CFG5
DMI X2 Select
CFG6
iTPM Host
Interface
Low = iTPM enable
CFG7
Management
Engine Crypto
Strap
Low = TLS cipher suite with no confidentiality
CFG9
PCI Express
Graphic Lane
CFG16
FSB Dynamic
ODT
Low=Dynamic ODT Disable
DMI Lane
Reversal
Low=Normal (default)
High = DMI x 4 (Default)
U2C
1
R105
49.9_0402_1%~D
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
M29
C44
B43
E37
E38
C41
C40
B37
A37
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
E28
G28
G29
H32
J32
J29
E29
L29
B
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
VGA
J28
TV
F25
H25
K25
LVDS
C
M33
K33
J33
PEG_COMPI
PEG_COMPO
GRAPHICS
D
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
PCI-EXPRESS
L32
G32
M32
T37
T36
PEGCOMP
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
1
PEG_MRX_GTX_N[0..15] <50>
CFG19
PEG_MRX_GTX_P[0..15] <50>
CFG20
High = iTPM disable(Defult)
High = Normal Operation(Default)
High=Dynamic ODT Enable(default)
High=Lane Reversed
Low=Only digital display port (SDVO/DP/iHDMI) or
PCIe is operational (default)
High = Digital display port (SDVO/DP/iHDMI) and
PCIe are operating simultaneously via the PEG
port
Digital Display
Port
Concurrent
Operation
SDVO_CRTL_DATA
Low=No SDVO Device Present
(default)
High=SDVO Device Present
Low=DisplayPort disabled (default)
DDPC_CTRLDATA
PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]
D
High = TLS cipher suite with
confidentiality(Default)
Low = Reverse Lane
High=DisplayPort device present
C
PEG_MTX_GRX_P[0..15] <50>
PEG_MTX_GRX_N[0..15] <50>
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
C77
2
1 0.1U_0402_10V7K~D
C78 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
C79
2
1 0.1U_0402_10V7K~D
C80 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_N2
C81
2
1 0.1U_0402_10V7K~D
C82 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
C83
2
1 0.1U_0402_10V7K~D
C84 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_N4
C85
2
1 0.1U_0402_10V7K~D
C86 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
C87
2
1 0.1U_0402_10V7K~D
C88 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
C89
2
1 0.1U_0402_10V7K~D
C90 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
C91
2
1 0.1U_0402_10V7K~D
C92 2
1 0.1U_0402_10V7K~D
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
C93
1
2 0.1U_0402_10V7K~D
C94 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
C95
1
2 0.1U_0402_10V7K~D
C96 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10
C97
1
2 0.1U_0402_10V7K~D
C98 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11
C99
1
2 0.1U_0402_10V7K~D
C100 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12
C101 1
2 0.1U_0402_10V7K~D
C102 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13
C103 1
2 0.1U_0402_10V7K~D
C104 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14
C105 1
2 0.1U_0402_10V7K~D
C106 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15
C107 1
2 0.1U_0402_10V7K~D
C108 1
2 0.1U_0402_10V7K~D
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
CANTIGA ES_FCBGA1329~D
<10>
CFG5
@ R106 1
2 2.21K_0402_1%~D
<10>
CFG6
@ R107 1
2 2.21K_0402_1%~D
<10>
CFG7
@ R108 1
2 2.21K_0402_1%~D
<10>
CFG9
@ R109 1
2 2.21K_0402_1%~D
<10>
CFG16
@ R110 1
2 2.21K_0402_1%~D
B
CFG[5:16] have internal pullup
+3.3V_RUN
<10>
CFG19
@ R111 1
2 4.02K_0402_1%~D
<10>
CFG20
@ R112 1
2 4.02K_0402_1%~D
<10> DDPC_CTRLDATA
@ R113 1
2 4.02K_0402_1%~D
CFG[19:20] have internal pulldown
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
Cantiga(3 of 6)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
12
of
71
5
4
3
2
1
+1.05V_VCCP
U2H
VSSA_LVDS
J47
AA48
VCCA_PEG_PLL
+1.05V_M_PEGPLL
1
2
2
2
SM CK
A CK
AXF
TV
VCCD_TVDAC
M25
VCCD_QDAC
L28
2
1
2
1
2
24mA Max.
1
2
+1.05V_M
L4
2
1
BLM18AG121SN1D_0603~D
1
2
+1.05V_M_MPLL
139.2mA Max.
1
2
+1.05V_M
2
1
L5
LQH32CNR15M33L_1210~D
R120
0_0603_5%~D
1
2
C133
22U_0805_6.3VAM~D
1
2
C998
0.1U_0402_16V4Z~D
B
+1.5V_RUN_QDAC
AF1
VCCD_HPLL
+1.05V_M
AA47
1
M38
L37
VCCD_LVDS_1
VCCD_LVDS_2
+1.5V_RUN
L49
BLM18PG181SN1_0603~D
2
1
1
R1077
2
0_0402_5%~D
+1.05V_M_PEGPLL
CANTIGA ES_FCBGA1329~D
1
2
+1.8V_MEM
+1.05V_M_HPLL
@
+1.5V_RUN
VCCD_PEG_PLL
LVDS
DMI
D TV/CRT
HDA
HV
PEG
VTTLF
A32
1
C132
0.1U_0402_16V4Z~D
VCC_HDA
C
2
0_1210_5%~D
1
2
C140
0.1U_0402_16V4Z~D
VTTLF1
VTTLF2
VTTLF3
B24
A24
2
2
1
2
C139
0.1U_0402_16V4Z~D
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VCCA_TV_DAC_1
VCCA_TV_DAC_2
1
1_0402_5%~D
+1.05V_M
1
R119
C141
0.1U_0402_16V4Z~D
2
+
@
C138
0.01U_0402_25V7K~D
AH48
AF48
AH47
AG47
C144
0.47U_0402_10V4Z~D
C143
0.47U_0402_10V4Z~D
C142
0.47U_0402_10V4Z~D
2
1
2
1
D
C131
4.7U_0603_6.3V6M~D
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
GMCH_VTTLF1 A8
GMCH_VTTLF2 L1
GMCH_VTTLF3AB2
1
2
1
1
C118
10U_0805_4VAM~D
2
1
R117
C130
0.1U_0402_16V4Z~D
+VCC_DMI
C137
0.1U_0402_16V4Z~D
C136
0.1U_0402_16V4Z~D
VCC_HV_1
VCC_HV_2
VCC_HV_3
V48
U48
V47
U47
U46
+VCC_PEG
2
1
2
C124
22U_0805_6.3V6M~D
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
R116
0_0805_5%~D
+1.05V_VCCP
Follow ERB,CRB option
to select +1.05V_M or
+1.05V_VCCP
+1.05V_M_PEGPLL
L3
BLM21PG221SN1D_0805~D
1
2
+1.05V_M
+1.05V_M_A_SM 1
2
+1.5V_RUN
+3.3V_RUN
+1.05V_M
C117
0.1U_0402_16V4Z~D
2
1
@ R115
0_1210_5%~D
C119
0.1U_0402_16V4Z~D
2
VCC_TX_LVDS
C35
B35
A35
2
0_0603_5%~D
1
2
2 0_0402_5%~D
0_0402_5%~D
C129
2.2U_0603_6.3V6K~D
1
R1076
1
R778 1
@ R779
1
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
A SM
+VCCA_PEG_BG
AD48
VCCA_PEG_BG
2
1
+1.05V_M
2
VCCA_LVDS
1
1
2
R114
0_1210_5%~D
1
CRT
PLL
A LVDS
+1.05V_M_MPLL
J48
C123
22U_0805_6.3V6M~D
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
K47
+VCC_DMI
2
1
1
+VCC_PEG
PJP1
PAD-OPEN1x1m
1
+1.05V_M
2 @
@ L6
LBC2518T91NM_1210~D
+
@ C145
220U_D2_4VY_R15M~D
2
+1.8V_SM_CK
C147
10U_0805_4VAM~D
2
1
R121
1_0603_5%~D
L7
LQM21FN1R0N00 _0805~D
Rdc=0.1~0.2,rated
current=220mA(MAX)
1
1
2
2
1
2
C146
0.1U_0402_16V4Z~D
A
+1.05V_M_HPLL
C128
22U_0805_6.3V6M~D
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
+3.3V_RUN
2
AD1
AE1
C127
0.1U_0402_16V4Z~D
2
B22
B21
A21
BF21
BH20
BG20
BF20
1
VCCA_HPLL
VCCA_MPLL
+1.05V_M_SM_CK
+1.8V_SM_CK
B
2
C122
4.7U_0603_6.3V6M~D
1
@
C126
1U_0603_10V4Z~D
C125
10U_0805_4VAM~D
1
2
2
L48
+
+VCC_AXF
2
1
R118
0_1210_5%~D
1
F47
VCCA_DPLLB
1
C121
1U_0603_10V4Z~D
+1.05V_M
VCCA_DPLLA
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
POWER
C
VCCA_DAC_BG
VSSA_DAC_BG
A25
B25
C120
100U_D2E_6.3VM_R15M~D
A PEG
2
B27
A26
C113
22U_0805_6.3V6M~D
2
1
C116
2.2U_0603_10V7K~D
1
C115
4.7U_0603_6.3V6M~D
2
C114
4.7U_0603_6.3V6M~D
1
+VCC_PEG
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
C112
4.7U_0603_6.3V6M~D
D
2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
C111
220U_D2_4VY_R15M~D
2
1
C110
0.47U_0402_10V4Z~D
+
C109
220U_D2_4VY_R15M~D
1
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
VTT
CRB 270uF
A
+1.05V_VCCP
2
1
@ D1
RB751V_SOD323-2~D
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_RUN
VCC_HV
1
2
@ R122
10_0603_5%~D
Follow CRB to
VCC_HV(C35,B35,A35)
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
Cantiga(4 of 6)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
13
of
71
4
3
2
2
VCC_35
+1.05V_M
VCC NCTF
1
2
Layout Note:
Inside GMCH cavity.R123
0_0402_5%~D
B
Layout Note:
Place on the edge
Layout Note:
Place close to GMCH
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
T37
T38
VCC_AXG_SENSE
VSS_AXG_SENSE
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
2
A
CANTIGA ES_FCBGA1329~D
1
2
1
2
1
2
1
2
1
2
1
2
C163
1U_0402_6.3V4Z~D
@ PAD~D
@ PAD~D
AV44
BA37
AM40
AV21
AY5
AM10
BB13
C162
1U_0402_6.3V4Z~D
VCC_AXG_SENSE
VSS_AXG_SENSE
CANTIGA ES_FCBGA1329~D
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
C161
0.47U_0402_10V4Z~D
AJ14
AH14
B
C160
0.22U_0402_10V4Z~D
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
C
C159
0.22U_0402_10V4Z~D
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
D
C158
0.1U_0402_10V7K~D
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
C157
0.1U_0402_10V7K~D
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC SM LF
2
1
C156
0.1U_0402_10V7K~D
1
C155
0.22U_0402_10V4Z~D
C
2
POWER
T32
Layout Note:
Place close to GMCH
2
1
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC GFX NCTF
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
2
1
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
VCC SM
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
+
VCC CORE
2
1
POWER
2
1
C154
0.22U_0402_10V4Z~D
2
1
C153
22U_0805_6.3VAM~D
+
C152
220U_D2_4VY_R15M~D
1
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
1
C151
22U_0805_6.3V6M~D
CRB 270uF
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
C150
22U_0805_6.3V6M~D
2
D
C148
330U_D2_2.5VY_R15M
U2F
C149
0.1U_0402_10V7K~D
+1.05V_M
1
U2G
+1.8V_MEM
VCC GFX
5
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
Cantiga(5 of 6)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
14
of
71
A
5
4
3
2
1
U2I
B
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
CANTIGA ES_FCBGA1329~D
U2J
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
BA16
VSS_235
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS
VSS NCTF
C
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS SCB
D
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
NC
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS_351
VSS_352
VSS_353
VSS_354
U24
U28
U25
U29
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
BH48
BH1
A48
C1
A3
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
D
C
B
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
CANTIGA ES_FCBGA1329~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
Cantiga(6 of 6)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
15
of
71
5
4
3
2
1
+1.8V_MEM
+1.8V_MEM
<11> DDR_A_DQS#[0..7]
<11> DDR_A_MA[0..14]
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
D
DDR_A_D8
DDR_A_D9
+1.8V_MEM
DDR_A_DQS#1
DDR_A_DQS1
2
1
DDR_A_D10
DDR_A_D11
C170
C169
1
2.2U_0603_6.3V6K~D
2
2.2U_0603_6.3V6K~D
2
1
C168
C167
1
2.2U_0603_6.3V6K~D
C166
2
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
DDR_A_D16
DDR_A_D17
2
1
DDR_A_D18
DDR_A_D19
C174
0.1U_0402_16V4Z~D
1
C173
C172
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C171
0.1U_0402_16V4Z~D
2
1
DDR_A_D24
DDR_A_D25
2
DDR_A_DM3
DDR_A_D26
DDR_A_D27
C
<10> DDR_CKE0_DIMMA
<11> DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<11> DDR_A_BS0
<11> DDR_A_WE#
<11> DDR_A_CAS#
<10> DDR_CS1_DIMMA#
+0.9V_DDR_VTT
<10>
M_ODT1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D32
DDR_A_D33
2
1
2
DDR_A_DQS#4
DDR_A_DQS4
1
DDR_A_D34
DDR_A_D35
2
C188
C187
C186
C185
C184
C183
C182
C181
C180
C179
C178
C177
C176
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C175
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B
2
1
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
+0.9V_DDR_VTT
RN1
DDR_A_MA3
1
DDR_A_MA1
2
56_0404_4P2R_5%~D
RN4
4
3
RN6
4
3
4
3
4
3
4
3
DDR_A_DM7
1 DDR_A_MA5
2 DDR_A_MA9
56_0404_4P2R_5%~D
DDR_A_D58
DDR_A_D59
1 DDR_A_MA2
2 DDR_A_MA4
56_0404_4P2R_5%~D
<17,24> MEM_SDATA
<17,24> MEM_SCLK
+3.3V_M
DDR_CKE1_DIMMA 2
1
R130
56_0402_5%~D
4
3
RN11
RN13
RN12
DDR_CKE0_DIMMA 2
DDR_A_BS2
1
56_0404_4P2R_5%~D
1 DDR_A_MA13
2 M_ODT0
56_0404_4P2R_5%~D
3
4
4
3
1 DDR_A_MA11
2 DDR_A_MA14
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1.3"
1
2
1
2
C190
2.2U_0603_6.3V6K~D
4
3
1 DDR_A_BS1
2 DDR_A_MA0
56_0404_4P2R_5%~D
C189
4
3
MEM_SDATA
MEM_SCLK
0.1U_0402_16V4Z~D
A
DDR_A_D56
DDR_A_D57
RN10
RN9
DDR_CS1_DIMMA# 1
M_ODT1
2
56_0404_4P2R_5%~D
DDR_A_D50
DDR_A_D51
Layout Note:
Place these resistor
closely DIMMA,all
trace length<750 mil
RN8
RN7
DDR_A_CAS#
1
DDR_A_WE#
2
56_0404_4P2R_5%~D
1 DDR_A_MA6
2 DDR_A_MA7
56_0404_4P2R_5%~D
4
3
RN5
DDR_CS0_DIMMA# 1
DDR_A_RAS#
2
56_0404_4P2R_5%~D
1 DDR_A_MA12
2 DDR_A_MA8
56_0404_4P2R_5%~D
4
3
RN3
DDR_A_BS0
1
DDR_A_MA10
2
56_0404_4P2R_5%~D
DDR_A_DQS#6
DDR_A_DQS6
RN2
4
3
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND1
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND2
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
1
2
1
2
D
DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_A_D14
DDR_A_D15
4
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
C
DDR_CKE1_DIMMA <10>
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS1 <11>
DDR_A_RAS# <11>
DDR_CS0_DIMMA# <10>
M_ODT0
<10>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R128 1
R129 1
2 10K_0402_5%~D
2 10K_0402_5%~D
A
TYCO_1-1734074-1~D
DIMMA
REVERSE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
DDR_A_DQS#2
DDR_A_DQS2
1
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C165
DDR_A_D0
DDR_A_D1
Layout Note:
Place near JDIMMA
C164
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
0.1U_0402_16V4Z~D
JDIMMA
<11> DDR_A_DQS[0..7]
1
2.2U_0603_6.3V6K~D
<11> DDR_A_D[0..63]
<11> DDR_A_DM[0..7]
1
+V_DDR_MCH_REF
+V_DDR_MCH_REF
3
2
Title
DDRII-SODIMM SLOT1
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
16
of
71
5
4
3
2
+1.8V_MEM
<11> DDR_B_DQS#[0..7]
+1.8V_MEM
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
2
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
2
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
<10> DDR_CKE2_DIMMB
C
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
DDR_B_BS2
<11> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
<11> DDR_B_BS0
<11> DDR_B_WE#
+0.9V_DDR_VTT
DDR_B_CAS#
DDR_CS3_DIMMB#
<11> DDR_B_CAS#
<10> DDR_CS3_DIMMB#
2
1
2
M_ODT3
M_ODT3
1
DDR_B_D32
DDR_B_D33
2
DDR_B_DQS#4
DDR_B_DQS4
C214
C213
C212
C211
C210
C209
C208
C207
C206
C205
C204
C203
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
2
1
0.1U_0402_16V4Z~D
1
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C202
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
<10>
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
B
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
+0.9V_DDR_VTT
DDR_B_MA3
1
DDR_B_MA1
2
56_0404_4P2R_5%~D
4
3
4
3
RN19
4
3
4
3
4
3
4
3
DDR_CKE3_DIMMB 2
1
R133
56_0402_5%~D
4
3
DDR_B_MA5
1
DDR_B_MA8
2
56_0404_4P2R_5%~D
DDR_B_D56
DDR_B_D57
Layout Note:
Place these resistor
closely DIMMB,all
trace length<750 mil
DDR_B_DM7
DDR_B_D58
DDR_B_D59
RN21
RN20
DDR_B_MA7
1
DDR_B_MA6
2
56_0404_4P2R_5%~D
RN26
RN25
DDR_CS3_DIMMB# 2
M_ODT3
1
3
4
56_0404_4P2R_5%~D
M_ODT2
1
DDR_B_MA13
2
56_0404_4P2R_5%~D
4
3
DDR_B_MA9
1
DDR_CKE2_DIMMB
2
56_0404_4P2R_5%~D
Layout Note:
Place these resistor
closely DIMMB,all
trace length
Max=1.3"
1
2
1
C216
RN24
C215
DDR_B_MA4
1
DDR_B_MA2
2
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
A
0.1U_0402_16V4Z~D
RN23
RN22
MEM_SDATA
MEM_SCLK
<16,24> MEM_SDATA
<16,24> MEM_SCLK
+3.3V_M
2
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND2
DDR_B_D6
DDR_B_D7
4
2
1
2
DDR_B_D12
DDR_B_D13
D
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 <10>
M_CLK_DDR#2 <10>
DDR_B_D14
DDR_B_D15
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB <10>
C
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS1 <11>
DDR_B_RAS# <11>
DDR_CS2_DIMMB# <10>
M_ODT2
DDR_B_MA13
M_ODT2
<10>
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
B
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 <10>
M_CLK_DDR#3 <10>
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
TYCO_2-1734072-2~D
DIMMB
REVERSE
+3.3V_M
2
1
R131
10K_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
1
R132
4
3
DDR_B_WE#
1
DDR_B_CAS#
2
56_0404_4P2R_5%~D
DDR_B_MA14
1
DDR_B_MA11
2
56_0404_4P2R_5%~D
4
3
4
3
DDR_B_RAS#
1
DDR_CS2_DIMMB# 2
56_0404_4P2R_5%~D
DDR_B_D50
DDR_B_D51
RN17
RN18
DDR_B_MA0
1
DDR_B_BS1
2
56_0404_4P2R_5%~D
DDR_B_MA12
1
DDR_B_BS2
2
56_0404_4P2R_5%~D
4
3
RN16
DDR_B_BS0
1
DDR_B_MA10
2
56_0404_4P2R_5%~D
DDR_B_DQS#6
DDR_B_DQS6
RN15
RN14
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND1
DDR_B_DM0
10K_0402_5%~D
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
DDR_B_D16
DDR_B_D17
C201
1
1
C197
C200
2
2.2U_0603_6.3V6K~D
2
0.1U_0402_16V4Z~D
C199
2
1
1
C196
2.2U_0603_6.3V6K~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
1
1
C195
2
C198
0.1U_0402_16V4Z~D
1
C194
2
1
2.2U_0603_6.3V6K~D
C193
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
DDR_B_D4
DDR_B_D5
1
DDR_B_D2
DDR_B_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
DDR_B_DQS#0
DDR_B_DQS0
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C192
<11> DDR_B_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
C191
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DDR_B_D0
DDR_B_D1
0.1U_0402_16V4Z~D
Layout Note:
Place near JDIMMB
<11> DDR_B_DM[0..7]
1
2.2U_0603_6.3V6K~D
JDIMMB
<11> DDR_B_DQS[0..7]
1
+V_DDR_MCH_REF
+V_DDR_MCH_REF
<11> DDR_B_D[0..63]
D
1
+1.8V_MEM
3
2
Title
DDRII-SODIMM SLOT2
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
17
of
71
5
4
3
2
1
+3.3V_M
1
Discrete
VGA_THERMDP
VGA_THERMDP <50>
1
THERMATRIP1#
C217
470P_0402_50V7K~D
1
1
C218
0.1U_0402_16V4Z~D
<7> H_THERMTRIP#
<22> FAN1_DET#
C219
R137
8.2K_0402_5%~D
1
2
2
THERMATRIP2#
5
6
PWR_MON
3
<47>
Diode circuit at DP4/DN4 is used for skin
temp sensor (placed optimally between CPU,
MEM).
MCH and
Place C221 close to the
Guardian pins as possible.
@ R997
270K_0402_1%
1
1
<38> BC_DAT_EMC4002
C
1
2
C220
0.1U_0402_16V4Z~D
2
T137PAD~D@
PWR_MON_GFX
MOLEX_53398-0471~D
1
+1.05V_VCCP
R138
C
2.2K_0402_5%~D
1
2
2
B
E
Q6
MMST3904-7-F_SOT323-3~D
1
2
3 G1
4 G2
<10> THERMTRIP_MCH#
1
Q7
MMBT3904WT1G_SC70-3~D
2
B
C221
E
<38> BC_CLK_EMC4002
2
2200P_0402_50V7K~D
2
1
U3
EMC4002
Place C223 close to the Q8 as possible
Place C224,C225 close to the Guardian pins as possible
10
11
<7> H_THERMDA
1
C
@ C227
100P_0402_50V8K~D
1
+3.3V_M
E
1
C228
2200P_0402_50V7K~D
2
B
Q9
MMBT3904WT1G_SC70-3~D
REM_DIODE3_P
REM_DIODE3_N
DP4/DN8
DN4/DP8
DP2
DN2
DP5/DN9
DN5/DP9
47
46
41
40
DP3/DN7
DN3/DP7
2
+RTC_CELL
1 R887
2 0_0603_5%~D
1
C229
0.1U_0402_16V4Z~D
2
C230
1U_0603_10V4Z~D
1
<38,41> 3.3V_M_PWRGD
<41> ICH_PWRGD#
R140
10KB_0603_1%_TSM1A103F34D3R~D
C226
0.1U_0402_16V4Z~D
1
2
1
2
1
4
+RTC_CELL_R
21
2 1K_0402_5%~D 18
2 1K_0402_5%~D 17
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
22
23
24
VSET
R150
42
1 4.7K_0402_5%~D 3
2
2
R141
VCC
ATF_INT#/BC-LINK_IRQ#
POWER_SW#
ACAVAIL_CLR
THERMTRIP_SIO/PWM1/GPIO5
SYS_SHDN#
VCC_PWRGD
3V_PWROK#
RTC_PWR3V
THERMTRIP1#
THERMTRIP2#
THERMTRIP3#
12
26
27
20
25
LDO_SHDN#
19
VSET
LDO_POK
34
ADDR_MODE/XEN
LDO_SET
33
1
10K_0402_5%~D
+3.3V_M
BC_INT#_EMC4002 <38>
POWER_SW#
ACAV_IN
2
R149
1
10K_0402_5%~D
2
@ R211
1
10K_0402_5%~D
<38,48>
2
R145
1
@ R147
1
2
+3.3V_M
10K_0402_5%~DTHERM_STP#
+RTC_CELL
47K_0402_1%~D
<44>
+3.3V_SUS
At maximum load current of 600mA,the the
voltage drop across the should be keep
in the range of 0.5V to 1V
2.5V_RUN_PWRGD <37,41>
B
LDO_SET
+3.3V_RUN
FAN1_TACH_FB
VDD_3V
7
8
FAN_OUT
FAN_OUT
15
14
TACH1/GPIO3
CLK_IN/GPIO2
VDDL/VDD_3V2
LDO_OUT/FAN_OUT2
LDO_OUT/FAN_OUT2
29
30
TACH2/GPIO4
PWM2/GPIO1
16
13
+3V_LDOIN
1
2
EC_32KHZ_OUT
R926
0_0402_5%~D
2
1
49
<38> EC_32KHZ_OUT
1
+1.8V_RUN
1
2
2
PM_EXTTS#
1
2
C233
0.1U_0402_16V4Z~D
2
+FAN1_VOUT
32
31
28
C239
0.1U_0402_16V4Z~D
2
1
VDDH/VDD_5V2
VDDH/VDD_5V2
C238
10U_0805_10V6K~D
2
1
C237
10U_0805_10V4Z~D
1
VDD_5V
VDD_5V
9
C232
10U_0805_10V4Z~D
6
5
+3.3V_RUN
C236
0.1U_0402_16V4Z~D
2
C235
10U_0805_10V4Z~D
1
Rset=953,Tp=88degree
C234
0.1U_0402_16V4Z~D
2
2
C231
0.1U_0402_16V4Z~D
+3VSUS_THRM
+5V_RUN
R151
953_0402_1%~D
+3VSUS_THRM
R146 1
R148 1
B
1
DP6/VREF_T2
DN6/VIN2
2
2
2
R142
0_0603_5%~D
VGA_THERMDP
VGA_THERMDN
DP1/VREF_T
DN1/THERM
38
37
1
2
1
R152
0.82_1210_1%~D
+1.8V_RUN
1
2
1
1
REM_DIODE4_P
REM_DIODE4_N
44
43
VSS
Place C227 close
to Q9
39
48
45
36
35
Place C228 close to the Guardian pins as possible
3
Q9 Place near DIMM
2
VIN1
VCP1
VCP2
C
1
2
R139
1.2K_0402_1%~D
2
<7> H_THERMDC
REM_DIODE1_P
REM_DIODE1_N
SMDATA/BC-LINK_DATA
SMBCLK/BC-LINK_CLK
THERMISTOR OPTION:
Single-ended routing to thermistor is permissible
(ground return). Place R139 and C226 near EMC4002
LDO_SET
<10>
1
C225
470P_0402_50V7K~D
ISL88731_ICM
1
E
<48> ISL88731_ICM
C224
2200P_0402_50V7K~D
2
1
C
2
2
B
Q8
MMBT3904WT1G_SC70-3~D
4.7K_0402_5%~D
R998
1
C
2
3
@ C223
100P_0402_50V8K~D
@C222
100P_0402_50V8K~D
Place C222 close to Q7 as
possible.
Place under CPU
+3.3V_M
C
THERM_B3 2
B
Q11
MMST3904-7-F_SOT323-3~D
10K
1
E
3
2
C240
0.1U_0402_16V4Z~D
2N3904
2F(r/w)
2N3904
2E(r/w)
18K
Thermistor
2F(r/w)
>= 33K
Thermistor
2E(r/w)
1
2
IN2
2
2
O
G
<= 4.7K +/- 5%
4
3
2
*
THERMATRIP3#
IN1
P
U68
74AHC1G08GW_SOT353-5~D
POWER_SW#
1
R157
2.2K_0402_5%~D
2
1
R156
8.2K_0402_5%~D
2
1
A
Pull-up Resistor For Remote1 SMBUS
on ADDR_MODE/XEN mode
Address
R155
8.2K_0402_5%~D
@ R1014
@ R1015
1
1
R143
0_0402_5%~D
1
1
R144
0_0402_5%~D
2
0_0402_5%~D
2
0_0402_5%~D
2
C1050
0.1U_0402_16V4Z~D
1
2
5
+RTC_CELL
1
+3.3V_RUN
DOCK_PWR_SW# <38>
POWER_SW_IN# <38>
R153
3.16K_0402_1%~D
2
19.2
1
2
3
4
1
1
1
D2
RB751S40T1_SOD523-2~D
+FAN1_VOUT
FAN1_TACH_FB
22U_0805_6.3VAM~D
+3.3V_M
D
VGA_THERMDN <50>
Place Capacitor close to Guardian Chip
JFAN1
Ra
R154
5.1K_0402_1%~D
2
VGA_THERMDN 2
R136
10K_0402_5%~D
2
3
D
3
+1.05V_VCCP
R135
C
2.2K_0402_5%~D
1
2
2
B
E
Q5
MMST3904-7-F_SOT323-3~D
+3.3V_M
1
2
R134
8.2K_0402_5%~D
Rb
Voltage margining circuit
for LDO output. Adjustable
from 1.2 to 2.5V.
Ra=((LDO_OUT/1.12)-1)*Rb.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
<50> THERMTRIP_VGA#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
FAN & Thermal Sensor
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
18
of
71
A
5
4
3
2
JLVDS1
1
4
2
1
I
BAT54CW_SOT323~D
1
2
@ R164
0_0402_5%~D
DMIC_CLK
+3.3V_RUN
DMIC0
DMIC0
1
@
1
2
2
C241
0.1U_0402_16V4Z~D
D
Q15
DDTC124EUA-7-F_SOT323-3~D
3
LDDC_DATA_GPU <50>
LDDC_CLK_GPU <50>
LVDS_CBL_DET# <22>
+3.3V_RUN
CAM_MIC_CBL_DET# <22>
G
2
<50> ENVDD_GPU
Q12
1
SI3456DV-T1-E3_TSOP6~D
2
3
1
2
O
3
<37> LCD_VCC_TEST_EN
LCD_A0+_GPU <50>
LCD_A0-_GPU <50>
<27>
<27>
LCD_SMBCLK <38>
LCD_SMBDAT <38>+3.3V_RUN
+INV_PWR_SRC
@
1
1
2
C246
0.1U_0603_50V4Z~D
@
C
2
R165
10K_0402_5%~D
@
D48
SD05.TCT_SOD323-2~D
2
1
LCD_SMBCLK
LCD_SMBDAT
D56
SD05.TCT_SOD323-2~D
2
1
USBP11_DUSBP11_D+
D47
SD05.TCT_SOD323-2~D
2
1
+CAMERA_VDD
1
@ R166
2
0_0402_5%~D
BIA_PWM_GPU <50>
+5V_ALW
1
1
2
1
+PWR_SRC
Q17
SI3457DV-T1_TSOP6~D
Close to JLVD1.6,7,8
4
2
6
5
2
1
40mil
40mil
+INV_PWR_SRC
8
7
6
5
1
2
3
C248
1000P_0402_50V7K~D
+INV_PWR_SRC
1
R167
100K_0402_5%~D
2
+3.3V_RUN
2
Q18
2N7002W-7-F_SOT323-3~D
3
+5V_RUN
S
2
1
100K_0402_5%~D
PWR_SRC_ON
<28,37,40,41,56> RUN_ON
SI3457DV : P CHANNAL
1
2
D
1
R168
B
2
G
R995
0_0603_5%~D
2
1
C247
0.1U_0603_50V4Z~D
PWR_SRC_ON
3
+CMOS_VDD
G
C250
10U_1206_16V4Z~D
C249
0.1U_0402_16V4Z~D
2
1
Close to JLVD1.9
+LCDVDD
4
+3.3V_RUN
@ Q16
FDS4435_NL_SO8~D
+PWR_SRC
Overlap on Q16 for pop option
C244
0.1U_0402_16V4Z~D
D
S
3
1
@ R170
0_0603_5%~D
2
1
Dual layout for Q17
C243
0.1U_0402_16V4Z~D
Q132
PMV45EN_SOT23-3~D
C245
0.1U_0402_16V4Z~D
1
2
2
PNL_BKLT_CBL_DET# <22>
BREATH_BLUE_LED <42>
BATT_YELLOW_LED <42>
BATT_BLUE_LED <42>
D
BREATH_BLUE_LED
BATT_YELLOW_LED
BATT_BLUE_LED
<37>
S
LCD_TST
+LCDVDD
G
LCD_TST
For Webcam
2
1
D3
LCD_A1+_GPU <50>
LCD_A1-_GPU <50>
2
B
5
1
LCD_A2+_GPU <50>
LCD_A2-_GPU <50>
2
2
Q13A
2N7002DW-T/R7_SOT363-6~D
1
1
6 2
Place near to JLVDS1
LCD_ACLK+_GPU <50>
LCD_ACLK-_GPU <50>
R158
100K_0402_5%~D
R163
100K_0402_5%~D
LCD_B0+_GPU <50>
LCD_B0-_GPU <50>
LDDC_CLK_GPU
2
2.2K_0402_5%~D
LDDC_DATA_GPU
2
2.2K_0402_5%~D
C242
0.1U_0402_25V4Z~D
1
R159
1
R160
JAE_FI-DP58SB-VF88L
+CAMERA_VDD
+3.3V_RUN
6
5
2
1
4
G
1
+3.3V_RUN
LCD_B1+_GPU <50>
LCD_B1-_GPU <50>
CAM_MIC_CBL_DET#
DMIC_CLK
+15V_ALW
3
+LCDVDD
LCD_B2+_GPU <50>
LCD_B2-_GPU <50>
LDDC_DATA_GPU
LDDC_CLK_GPU
LVDS_CBL_DET#
+LCDVDD
D
+15V_ALW
S
C
LCD_BCLK+_GPU <50>
LCD_BCLK-_GPU <50>
Q13B
2N7002DW-T/R7_SOT363-6~D
Even_ClkIN+
Even_ClkINVSS
Even_Rin2+
Even_Rin2VSS
Even_Rin1+
Even_Rin1VSS
Even_Rin0+
Even_Rin0VSS
Odd_ClkIN+
Odd_ClkINVSS
Odd_Rin2+
Odd_Rin2VSS
Odd_Rin1+
Odd_Rin1VSS
Odd_Rin0+
Odd_Rin0VSS
DATA EEDID
CLK EEDID
VSS
VEEDID
Diag_Loop_CAM
MIC_CLK
3.3V
MIC_SIG
5V
USBUSB+
GND
CONNTST
SMB_CLK
SMB_DATA
INV_SRC
INV_SRC
INV_SRC
INV_SRC
VBLVBLVBLVBLINV_PWM
+5V_ALW
TEST
VDD
VDD
VDD
CONNTST
PWR_LED
BATT2_LED
BATT1_LED
VSS
R162
100K_0402_5%~D
D
LCD Power
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MGND1
MGND2
MGND3
MGND4
MGND5
MGND6
MGND7
MGND8
MGND9
MGND10
MGND11
MGND12
MGND13
MGND14
R161
470_0402_5%~D
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
FDS4435: P CHANNAL
C1043
0.1U_0402_16V4Z~D
1
+15V_ALW
R169
100K_0402_5%~D
<24>
CCD_OFF
D
S
Q133
CCD_OFF
2
G
2N7002W-7-F_SOT323-3~D
<37>
1
2
<24>
3
Webcam PWR CTRL
USBP11USBP11+
USBP11USBP11+
1
4
@ L59
DLW21SN121SQ2L_4P~D
1
2 2
4
3
USBP11_DUSBP11_D+
3
1
R457
2
0_0402_5%~D
1
R513
2
0_0402_5%~D
1
2
C1044
0.1U_0402_25V4K~D
@ U50
USBP11_D-
1
GND IO2
3
2
IO1
4
VIN
USBP11_D+
+CAMERA_VDD
PRTR5V0U2X_SOT143-4~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
LVDS Conn
Size
Rev
0.8
LA-3803P
Date:
2
Document Number
Thursday, June 12, 2008
Sheet
1
19
of
71
1
2
2
+3.3V_RUN
1
2
2
+5V_RUN_CRT1
3
2
1
2
2
1
1
3
2
2
1
1
@
1
R174
150_0402_1%~D
2
1
R173
150_0402_1%~D
2
1
R172
150_0402_1%~D
2
1
@
R
1
1
2
2
1
2
2
R176
1K_0402_5%~D
R175
1K_0402_5%~D
52
5
54
51
R793
2.2K_0402_5%~D
NC
NC
NC
NC
HSYNC_CRT 1
R177
To Dock Conn.
VSYNC_CRT 1
R178
B
16
17
SUYIN_070546FR015S558ZR
L11
BLM11A121S_0603~D
2 HSYNC_L2 1
2
0_0402_5%~D
C258
2
0.1U_0402_16V4Z~D
2 VSYNC_L2 1
2
0_0402_5%~D
L12
BLM11A121S_0603~D
+3.3V_RUN
2
1
2
1
2
1
2
1
2
1
2
1
2
1
@
2
C268
22P_0402_50V8J~D
2
1
C267
22P_0402_50V8J~D
2
1
C266
0.1U_0402_16V4Z~D
1
TS3DV520ERHUR_QFN56_11X5~D
C265
0.1U_0402_16V4Z~D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
@
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
DAT_DDC2_DOCK <35>
CLK_DDC2_DOCK <35>
VSYNC_DOCK <35>
HSYNC_DOCK <35>
RED_DOCK <35>
GREEN_DOCK <35>
BLUE_DOCK <35>
C264
0.1U_0402_16V4Z~D
1
6
9
13
16
21
24
28
33
39
44
49
53
55
DAT_DDC2_DOCK
CLK_DDC2_DOCK
VSYNC_DOCK
H SYNC_DOCK
RED_DOCK
GREEN_DOCK
BLUE_DOCK
C263
0.1U_0402_16V4Z~D
SEL
46
45
41
40
35
34
30
29
25
26
@
JVGA_HS
B
+CRT_VCC
JVGA_VS
M_ID2#
DAT_DDC2_CRT
CLK_DDC2_CRT
C262
0.1U_0402_16V4Z~D
17
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
To MB CRT Conn.
C261
0.1U_0402_16V4Z~D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
DAT_DDC2_CRT
CLK_DDC2_CRT
VSYNC_BUF
HSYNC_BUF
RED_CRT
GREEN_CRT
BLUE_CRT
C260
0.1U_0402_16V4Z~D
TV
LIO
NA
2
3
7
8
11
12
14
15
19
20
G
48
47
43
42
37
36
32
31
22
23
C259
10U_0805_10V4Z~D
SEL CRT
0
MB
1
APR/SPR
CRT_SWITCH
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R794
2.2K_0402_5%~D
<37> CRT_SWITCH
4
10
18
27
38
50
56
1
U4
GPU_DAT_DDC
GPU_CLK_DDC
2
+5V_RUN_SYNC
B
<50> GPU_DAT_DDC
<50> GPU_CLK_DDC
<50> CRT_VSYNC_GPU
<50> CRT_HSYNC_GPU
<50> CRT_RED_GPU
<50> CRT_GRN_GPU
<50> CRT_BLU_GPU
1
C254
0.01U_0402_16V7K~D
2
@
+CRT_VCC
R171
0_1206_5%~D
@
C253
10P_0402_50V8J~D
2
1
C252
10P_0402_50V8J~D
@
1
C251
10P_0402_50V8J~D
1
C996
22P_0402_50V8J~D
2
BLUE_CRT_L
C518
22P_0402_50V8J~D
@
GREEN_CRT_L
C390
22P_0402_50V8J~D
2
1
C257
10P_0402_50V8J~D
@
C256
10P_0402_50V8J~D
C255
10P_0402_50V8J~D
2
1
1
2
L61
BLM18BB470SN1D_0603~D
1
2
L62
BLM18BB470SN1D_0603~D
1
2
L63
BLM18BB470SN1D_0603~D
F2
5A_125V_R451005.MRL~D
BLUE_CRT
3
2
GREEN_CRT
1
RED_CRT_L
1
2
R1095
0_0402_5%~D
1
2
R1096
0_0402_5%~D
1
2
R1097
0_0402_5%~D
@
D8
SDM10U45-7_SOD523-2~D
RED_CRT
@
+5V_RUN
D7
DA204U_SOT323-3~D
@
+3.3V_RUN
D6
DA204U_SOT323-3~D
D5
DA204U_SOT323-3~D
1
2
@
2
+5V_RUN
1
D9
SDM10U45-7_SOD523-2~D
+5V_RUN_SYNC
P
2
A
3
G
HSYNC_BUF
A
Y
4
HSYNC_CRT
U5
SN74AHCT1G125GW_SC70-5~D
A
2
A
3
G
1
C270
0.1U_0402_16V4Z~D
VSYNC_BUF
5
2
P
1
2
1K_0402_5%~D
1
5
1
R179
OE#
2
OE#
1
C269
0.1U_0402_16V4Z~D
Y
4
VSYNC_CRT
U6
SN74AHCT1G125GW_SC70-5~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
CRT/Video switch
http://hobi-elektronika.net
2
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
1
Sheet
20
of
71
2
+5V_RUN
+3.3V_RUN
2
1
2
C1030
0.1U_0402_10V7K~D
2
1
C1029
0.001U_0402_25V7K~D
2
1
C1028
0.01U_0402_16V7K~D
1
C1027
0.1U_0402_10V7K~D
2
C1026
0.1U_0402_10V7K~D
C1025
1U_0603_10V4Z~D
2
1
R186
@ R187
R188
@ R1022
@ R1023
2 DPB_CA_DET
2
1
2
1
2
1
2
1
2
1
2
1
2
DPC_CA_DET
1M_0402_5%~D
DPB_MB_CA_DET
1M_0402_5%~D
DPB_MB_HPD
100K_0402_5%~D
DPB_DOCK_CA_DET
1M_0402_5%~D
DPB_DOCK_HPD
100K_0402_5%~D
DPB_AUX_SW
100K_0402_5%~D
DPB_AUX#SW
100K_0402_5%~D
@ R1026
@ R1027
1
2
1
2
DPC_DOCK_AUX_SW
100K_0402_5%~D
DPC_DOCK_AUX#_SW
100K_0402_5%~D
2
@ D10
B0540WS-7_SOD323-2~D
4
Y
2
A
DPC_CA_DET
@
1
5
+3.3V_RUN
2
+5V_RUN_R
1
2
2
1
1
F1
1206L150PR~D
1
2
C276
0.1U_0402_16V4Z~D
U7
NC7SZ04P5X_NL_SC70-5~D
1
1
2
1
2
1
+5V_RUN
C1074
0.1U_0402_16V4Z~D
1
2
P
NC
P
5
<50> DVI_C_DAT_DDC
G
R996
@ R185
1
1
1
+3.3V_RUN
A
+3.3V_RUN
3
Y
SN74CBTD3306CPWR_TSSOP8~D
R1086
2.2K_0402_5%~D
1
2
R92
U78
33_0402_5%~D
1
2 DVI_C_CLK_R 2 1A
VCC 8
DVI_C_DAT_R 5
2A
1B 3
R764
1 1OE#
2B 6
33_0402_5%~D
7 2OE# GND 4
1
2
SN74CBTD3306CPWR_TSSOP8~D
R1087
DPC_CA_DET#
2.2K_0402_5%~D
1
2
+3.3V_RUN
<50> DVI_C_CLK_DDC
DPC_DOCK_AUX_SW <35>
DPC_DOCK_AUX#_SW <35>
1
DPC_CA_DET <35,50>
2
<50> DPB_LANE_P0_C
<50> DPB_LANE_N0_C
ML_IN 0(p)
ML_IN 0(n)
ML_A 0(p)
ML_A 0(n)
56
55
DPB_MB_LANE0
DPB_MB_LANE0#
C278
C279
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE0_C
DPB_MB_LANE0#_C
<50> DPB_LANE_P1_C
<50> DPB_LANE_N1_C
6
7
ML_IN 1(p)
ML_IN 1(n)
ML_A 1(p)
ML_A 1(n)
53
52
DPB_MB_LANE1
DPB_MB_LANE1#
C280
C281
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE1_C
DPB_MB_LANE1#_C
<50> DPB_LANE_P2_C
<50> DPB_LANE_N2_C
9
10
ML_IN 2(p)
ML_IN 2(n)
ML_A 2(p)
ML_A 2(n)
50
49
DPB_MB_LANE2
DPB_MB_LANE2#
C282
C283
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE2_C
DPB_MB_LANE2#_C
ML_A 3(p)
ML_A 3(n)
47
46
DPB_MB_LANE3
DPB_MB_LANE3#
C284
C285
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_MB_LANE3_C
DPB_MB_LANE3#_C
AUX_A (p)
AUX_A (n)
45
43
DPB_MB_AUX
DPB_MB_AUX#
ML_B 0(p)
ML_B 0(n)
25
24
DPB_DOCK_LANE0 C286
DPB_DOCK_LANE0# C287
ML_B 1(p)
ML_B 1(n)
22
21
ML_B 2(p)
ML_B 2(n)
12
13
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
DPB_MB_AUX
2
100K_0402_5%~D
2
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
DPB_MB_HPD
DPB_MB_AUX#
<50> DPB_MB_P14
DPB_MB_AUX
DPB_MB_P14
DPB_MB_CA_DET
DPB_MB_LANE3#_C
DPB_MB_LANE3_C
DPB_MB_LANE2#_C
40
32
DPB_MB_CA_DET
41
DPB_DOCK_CA_DET 33
30
2
1
R190
100K_0402_5%~D
29
1
19
18
DPB_DOCK_LANE2 C290
DPB_DOCK_LANE2# C291
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_DOCK_LANE2_C <35>
DPB_DOCK_LANE2#_C <35>
ML_B 3(p)
ML_B 3(n)
16
15
DPB_DOCK_LANE3 C292
DPB_DOCK_LANE3# C293
2
2
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
DPB_DOCK_LANE3_C <35>
DPB_DOCK_LANE3#_C <35>
AUX_B (p)
AUX_B (n)
28
26
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_HPD
39
DPB_CA_DET
RCLAMP0524P.TCT~D
@ D12
DPB_MB_LANE2_C
<50>
DPB_CA_DET <50>
5
11
20
27
31
42
44
51
Thermal GND
57
9
DPB_MB_LANE2#_C
DPB_MB_LANE3_C
4
7
DPB_MB_LANE3_C
DPB_MB_LANE3#_C 5
6
DPB_MB_LANE3#_C
8
A
RCLAMP0524P.TCT~D
+3.3V_RUN
@
@ D13
1
<35,37> DOCK_DET#
<37> DP_MB_EN
@ R9181
2
0_0402_5%~D
R9191
2
0_0402_5%~D
DPB_MB_HPD
10 DPB_MB_LANE2_C
1
DPB_MB_LANE2#_C 2
3
1
IN1
2
IN2
2
C1041 0.1U_0402_16V4Z~D
O
3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
21
22
23
24
8
DPB_DOCK_AUX <35>
DPB_DOCK_AUX# <35>
2
2
8
14
17
23
34
48
54
DPB_MB_LANE1#_C
3
R1098
1M_0402_5%~D
+5V_RUN
DPB_MB_LANE1_C
6
DPB_DOCK_LANE1_C <35>
DPB_DOCK_LANE1#_C <35>
DPVadj
VDD*1
7
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
CAD
38
DPB_MB_LANE0#_C
4
2
2
+3.3V_RUN
+3.3V_RUN
9
DPB_MB_LANE1_C
DPB_DOCK_LANE1 C288
DPB_DOCK_LANE1# C289
DPB_HPD
GND
GND
GND
GND
10 DPB_MB_LANE0_C
1
DPB_MB_LANE1#_C 5
37
DP_PWR
RTN
HP_DET
AUX_CHGND
AUX_CH+
GND
CA_DET
LANE3LANE3_shield
LANE3+
LANE2LANE2_shield
LANE2+
LANE1LANE1_shield
LANE1+
LANE0LANE0_shield
LANE0+
DPB_MB_LANE0#_C 2
DPB_DOCK_LANE0_C <35>
DPB_DOCK_LANE0#_C <35>
Priority
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
@ D11
DPB_MB_LANE0_C
Pads for interoperability,
remove in X01 if not needed.
R191
100K_0402_5%~D
R193
5.11K_0402_1%~D
2
DPB_MB_LANE0_C
2
2
HPD
1
A
DPB_MB_LANE1_C
DPB_MB_LANE0#_C
1 0.1U_0402_10V7K~D
1 0.1U_0402_10V7K~D
LP
B
MOLEX_105019-0001
5
DP_PRIORITY
<37> DP_PRIORITY
CAD_A
CAD_B
DPB_MB_LANE2_C
DPB_MB_LANE1#_C
P
<35> DPB_DOCK_CA_DET
HPD_A
HPD_B
1
R1024
DPB_MB_AUX#
1
@ R1025
DPB_DOCK_AUX 2
@ R1028
DPB_DOCK_AUX# 2
@ R1029
4
DPB_MB_AUX
1
10 DPB_MB_AUX
DPB_MB_AUX#
2
9
DPB_MB_HPD
4
7
DPB_MB_HPD
DPB_MB_CA_DET
5
6
DPB_MB_CA_DET
DP_MB_HPD_EN
G
<35> DPB_DOCK_HPD
2
JDP1
2
@ R209
DPB_MB_AUX#
2
R278
DPB_DOCK_AUX 2
@ R336
DPB_DOCK_AUX# 2
@ R337
DPC_DOCK_AUX 2
@ R419
DPC_DOCK_AUX# 2
@ R647
R917
0_0402_5%~D
1
2
DP_MB_HPD_EN
DPB_DOCK_HPD
AUX (p)
AUX (n)
1
2
R189
100K_0402_5%~D
1
+3.3V_RUN
36
35
1
DPB_AUX_SW
DPB_AUX#SW
ML_IN 3(p)
ML_IN 3(n)
2
<50> DPB_LANE_P3_C
<50> DPB_LANE_N3_C
1
+3.3V_RUN
DPB_MB_AUX
U9
3
4
+VDISPLAY_VCC
C1075
10U_0805_10V6K~D
4
U8
NC7SZ04P5X_NL_SC70-5~D
DPC_DOCK_AUX_SW
DPC_DOCK_AUX#_SW
NC
2
1
1
8
3
6
4
G
C277
0.1U_0402_16V4Z~D
C274
0.1U_0402_10V7K~D
1A
VCC
2A
1B
1OE#
2B
2OE# GND
C275
0.01U_0402_16V7K~D
B
2
+5V_RUN
C1073
0.1U_0402_16V4Z~D
1
2
U77
2
5
1
7
DPC_AUX#_C
3
R1084
2.2K_0402_5%~D
1
2
+3.3V_RUN
1
+3.3V_RUN
@
R184
0_1206_5%~D
<50> DVI_B_DAT_DDC
<50> DPC_DOCK_AUX#
2
SN74CBTD3306CPWR_TSSOP8~D
R74
U76
33_0402_5%~D
2 1A
1
2 DVI_B_CLK_R
VCC 8
DVI_B_DAT_R
5 2A
1B 3
R89
1 1OE#
2B 6
33_0402_5%~D
7 2OE# GND 4
1
2
SN74CBTD3306CPWR_TSSOP8~D
R1085
DPB_CA_DET#
2.2K_0402_5%~D
1
2
+3.3V_RUN
<50> DVI_B_CLK_DDC
1
2
1
DPB_AUX_SW
DPB_AUX#SW
2
2
C273
0.1U_0402_10V7K~D
1A
VCC
2A
1B
1OE#
2B
2OE# GND
C272
0.1U_0402_10V7K~D
2
1 DPC_AUX_C
R1102
1K_0402_1%~D
2
2
DPB_AUX#_C
<50> DPC_DOCK_AUX
@ R1101
1K_0402_1%~D
R1100
1K_0402_1%~D
@ R1099
1K_0402_1%~D
1
1
<50> DPB_AUX#
1
8
3
6
4
@
R210
0_1206_5%~D
2
U75
2
5
1
7
+5V_RUN
C1065
0.1U_0402_16V4Z~D
1
2
@
R183
100K_0402_5%~D
C271
0.1U_0402_10V7K~D
2
1 DPB_AUX_C
DPB_AUX
@
R182
100K_0402_5%~D
C1064
0.1U_0402_16V4Z~D
1
2
Display port Connector
+3.3V_RUN
SW for eDOCK side
R181
100K_0402_5%~D
+5V_RUN
R180
100K_0402_5%~D
SW for MB side
<50>
1
+3.3V_RUN
U62
74AHC1G08GW_SOT353-5~D
DPB_MB_AUX#
3
8
TS2DP512_QFN56_8X8~D
RCLAMP0524P.TCT~D
Place close to JDP1 connector
Pin30 Level
LP
State
Description
Hi
Normal Mode
Standard operational mode for device
Low
Low power Mode
Device is forced into a low power mode
causing the output s to go to a high-Z
state, all other inputs are ignore
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Display port
http://hobi-elektronika.net
2
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
1
Sheet
21
of
71
5
4
3
2
1
+3.3V_RUN
<31> PCI_AD[0..31]
<31> PCI_PIRQB#
<31> PCI_PIRQC#
<31> PCI_PIRQD#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
J5
E1
J6
C4
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C14
D4
R2
PCI_PLTRST#
CLK_PCI_ICH
ICH_PME#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
+3.3V_ALW_ICH
C294
0.1U_0402_16V4Z~D
<31>
<31>
<31>
<31>
14
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#
ICH_GPIO55
PCI_PCIRST#
PCI_IRDY# <31>
PCI_PAR <31>
1
IN1
2
IN2
PCI_DEVSEL# <31>
PCI_PERR# <31>
P
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D8
B4
D6
A5
PCI_REQ1#
<31>
PCI_GNT1# <31>
PCIE_MCARD2_DET# <34>
T160PAD~D@
PCIE_MCARD3_DET# <34>
GNT2#/GPIO53
OUT
PCI_SERR# <31>
PCI_STOP# <31>
PCI_TRDY# <31>
PCI_FRAME# <31>
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
H4
K6
F2
G2
PCI_RST#
3
PCI_RST#
<29,31>
G
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
U11A
74VHC08MTCX_NL_TSSOP14~D
7
F1
G4
B6
A7
F13
F12
E6
F6
+3.3V_ALW_ICH
14
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
CLK_PCI_ICH <6>
ICH_PME#
<37>
PCI_PLTRST#
4
IN1
5
IN2
P
PCI
OUT
LVDS_CBL_DET#
PNL_BKLT_CBL_DET#
CAM_MIC_CBL_DET#
FAN1_DET#
LVDS_CBL_DET# <19>
PNL_BKLT_CBL_DET# <19>
CAM_MIC_CBL_DET# <19>
FAN1_DET#
<18>
PLTRST1#
6
PLTRST1#
<10,32,50>
G
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C
U11B
74VHC08MTCX_NL_TSSOP14~D
+3.3V_ALW_ICH
ICH9M REV 1.0
10
IN1
9
IN2
OUT
PLTRST2#
8
PLTRST2#
<37,38>
U11C
74VHC08MTCX_NL_TSSOP14~D
7
C
PCI_PIRQA#
2
8.2K_0402_5%~D
PCI_PIRQB#
2
8.2K_0402_5%~D
PCI_PIRQC#
2
8.2K_0402_5%~D
PCI_PIRQD#
2
8.2K_0402_5%~D
PCI_REQ0#
2
8.2K_0402_5%~D
PCI_REQ1#
2
8.2K_0402_5%~D
FAN1_DET#
2
100K_0402_5%~D
LVDS_CBL_DET#
2
100K_0402_5%~D
CAM_MIC_CBL_DET#
2
100K_0402_5%~D
PNL_BKLT_CBL_DET#
2
100K_0402_5%~D
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
7
+3.3V_RUN
1
R202
1
R203
1
R204
1
R205
1
R207
1
R208
1
R702
1
R755
1
R212
1
R817
D
U10B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
14
PCI_DEVSEL#
2
8.2K_0402_5%~D
PCI_STOP#
2
8.2K_0402_5%~D
PCI_TRDY#
2
8.2K_0402_5%~D
PCI_FRAME#
2
8.2K_0402_5%~D
PCI_PLOCK#
2
8.2K_0402_5%~D
PCI _IRDY#
2
8.2K_0402_5%~D
PCI_SERR#
2
8.2K_0402_5%~D
PCI_PERR#
2
8.2K_0402_5%~D
P
1
R194
1
R195
1
R196
1
R197
1
R198
1
R199
1
R200
1
R201
G
D
14
+3.3V_ALW_ICH
IN1
12
IN2
P
13
7
PCI_GNT0#
<24> ICH_SPI_CS1#
PLTRST3#
<34,36>
U11D
74VHC08MTCX_NL_TSSOP14~D
1
ICH_SPI_CS1#
1
ICH_GPIO55
B
1
B
11 PLTRST3#
G
OUT
@ R214
1K_0402_5%~D
2
2
R213
1K_0402_5%~D
2
@ R215
1K_0402_5%~D
Place closely pin U10.D4
2
CLK_PCI_ICH
Boot BIOS Strap
A16 away override strap.
PCI_GNT0#
*
SPI_CS1#
Boot BIOS Location
0
1
SPI
1
0
PCI
1
1
LPC
CLK_ICH_TERM 1
PCI_GNT3#/(MDC_RST_DIS#)
@ R216
10_0402_5%~D
Low = A16 swap override enabled.
High = Default.
1
2
@ C295
8.2P_0402_50V8J~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
ICH9-M(1/4)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
22
of
71
3
2
1
+RTC_CELL
+RTC_CELL
1
4
1
5
R218
332K_0402_1%~D
2
2
R217
332K_0402_1%~D
@ R220
0_0402_5%~D
ICH9M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
1
2
2
<29>
ICH_INTVRMEN
LAN100_SLP
B22
A22
INTVRMEN
LAN100_SLP
E25
LAN_CLK
@ ME1
1
C298
@SHORT PADS~D
2
1U_0603_10V4Z~D
@ CMOS1 @SHORT PADS~D
1
2
C299
1U_0603_10V4Z~D
Close to U55
1
R234
1
R235
1
R239
1
R241
<27> ICH_AZ_CODEC_SDOUT
<27> ICH_AZ_CODEC_SYNC
<27> ICH_AZ_CODEC_RST#
<27> ICH_AZ_CODEC_BITCLK
1
C302
27P_0402_50V8J~D
2 ICH_AZ_SDOUT
33_0402_5%~D
2 I CH_AZ_SYNC
33_0402_5%~D
2 ICH_AZ_RST#
33_0402_5%~D
2 ICH_AZ_BITCLK
33_0402_5%~D
<33> ICH_AZ_MDC_BITCLK
<33> ICH_AZ_MDC_SYNC
<33> ICH_AZ_MDC_RST#
<27> ICH_AZ_CODEC_SDIN0
<33> ICH_AZ_MDC_SDIN1
<29>
<29>
<29>
LAN_RX0
LAN_RX1
LAN_RX2
<29>
<29>
<29>
LAN_TX0
LAN_TX1
LAN_TX2
C13
LAN_RSTSYNC
F14
G13
D14
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TX0
LAN_TX1
LAN_TX2
D13
D12
E13
LAN_TXD0
LAN_TXD1
LAN_TXD2
GLAN_DOCK#
B10
GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
1
2
+1.5V_RUN_PCIE_ICH
R232
2
1
C300
R236 33_0402_5%~D
24.9_0402_1%~D
ICH_AZ_BITCLK
27P_0402_50V8J~D
1
2
I CH_AZ_SYNC
1
2
R238
33_0402_5%~D
ICH_AZ_RST#
1
2
R240
33_0402_5%~D
ICH_AZ_CODEC_SDIN0
ICH_AZ_MDC_SDIN1
2
1
R242
<33> ICH_AZ_MDC_SDOUT
<37>
ME_FWP
ICH_AZ_SDOUT
2
33_0402_5%~D
ME_FWP
RTC_BAT_DET#
SATA_ACT#_R
<42> SATA_ACT#_R
<26> PSATA_IRX_DTX_N0_C
<26> PSATA_IRX_DTX_P0_C
<26> PSATA_ITX_DRX_N0
<26> PSATA_ITX_DRX_P0
B
<26> SATA_ODD_IRX_DTX_N1_C
<26> SATA_ODD_IRX_DTX_P1_C
<26> SATA_ODD_ITX_DRX_N1
<26> SATA_ODD_ITX_DRX_P1
2
C307 2
C308
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
2
C310 2
C311
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
AE7
HDA_RST#
AF4
AG4
AH3
AE5
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AH13
AJ13
SATA_ODD_ITX_DRX_N1_C AG14
SATA_ODD_ITX_DRX_P1_C AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
K3
LPC_LFRAME#
LDRQ0#
LDRQ1#/GPIO23
J3
J1
LPC_LDRQ0#
LPC_LDRQ1#
A20GATE
A20M#
N7
AJ27
SIO_A20GATE
H_A20M#
DPRSTP#
DPSLP#
AJ25
AE23
FERR#
AJ26
H_DPRSTP#
H_DPSLP#
R229
2
1
56_0402_5%~D
H_PW RGOOD
GLAN_CLK
LAN_RX0
LAN_RX1
LAN_RX2
<29> LAN_RSTSYNC
C
FWH4/LFRAME#
CPUPWRGD
AD22
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT#
H_INTR
SIO_RCIN#
NMI
SMI#
AF23
AF24
H_NMI
H_SMI#
STPCLK#
AH27
H_STPCLK#
+3.3V_RUN
<29,36,37,38>
<29,36,37,38>
<29,36,37,38>
<29,36,37,38>
SIO_RCIN#
LPC_LFRAME# <29,36,37,38>
LPC_LDRQ0# <37>
LPC_LDRQ1# <37>
SIO_A20GATE <38>
H_A20M#
<7>
SIO_A20GATE
+1.05V_VCCP
@
1
RTCRST#
SRTCRST#
INTRUDER#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
1
10K_0402_5%~D
1
10K_0402_5%~D
2
R233
1
56_0402_5%~D
+1.05V_VCCP
H_FERR#
H_DPRSTP#
H_DPSLP#
H_FERR#
2
R230
2
R231
@
2
1
A25
F20
C22
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
<8,10,47>
<8>
C
<7>
H_PWRGOOD <8>
H_IGNNE#
<7>
H_INIT#
H_INTR
SIO_RCIN#
<7>
<7>
<38>
H_NMI
H_SMI#
<7>
<7>
H_STPCLK#
<7>
+1.05V_VCCP
1
2
ICH_RTCRST#
SRTCRST#
INTRUDER#
K5
K4
L6
K2
R228
56_0402_1%~D
2
2
2 20K_0402_5%~D
2 20K_0402_5%~D
1M_0402_5%~D
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
R227
56_0402_1%~D
1
1
R224 1
R225 1
R226
RTCX1
RTCX2
THRMTRIP#
AG26
THRMTRIP_ICH#
TP12
AG27
ICH_TP12
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
R237
56_0402_5%~D
2
+RTC_CELL
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
LPC_LAD[0..3] <29,36,37,38>
U10A
C23
C24
ICH_RTCX2
1
Keep ME RTC Registers
1
R223
0_0402_5%~D
1
1
2
12P_0402_50V8J~D
2
C297
2
Open
1
2
Clear ME RTC Registers
RTC
LPC
Shunt
ICH_LAN100_SLP
Low = Internal VR Disabled
High = Internal VR Enabled(Default)
LAN / GLAN
CPU
Keep CMOS
ME_CLR1 TPM setting
ICH_INTVRMEN
R222
10M_0402_5%~D
IHDA
Open
Y1
32.768KHZ_12.5PF_9H03200584~D
ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)
ICH_RTCX1
2
1
C296
15P_0402_50V8J~D
Clear CMOS
SATA
CMOS setting
2
Shunt
1
CMOS_CLR1
D
Package
9.6X4.06 mm
1 GLAN_DOCK#
10K_0402_5%~D
2
R221
1
1
+3.3V_ALW_ICH
D
LAN100_SLP
2
2
ICH_INTVRMEN
@ R219
0_0402_5%~D
1
2
C301
0.1U_0402_16V4Z~D
@ T41PAD~D
ESATA_ITX_DRX_N4_C
2
ESATA_ITX_DRX_P4_C C303 2
C304
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
AH9
AJ9
AE10
AF10
SATA_ITX_DRX_N3_C
SATA_ITX_DRX_P3_C
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
SATA_CLKN
SATA_CLKP
AH18
AJ18
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS#
SATARBIAS
AJ7
AH7
2
R247
2
C305 2
C306
ESATA_IRX_DTX_N4_C <33>
ESATA_IRX_DTX_P4_C <33>
ESATA_ITX_DRX_N4 <33>
ESATA_ITX_DRX_P4 <33>
SATA_SBRX_DTX_N3_C
SATA_SBRX_DTX_P3_C
SATA_SBTX_C_DRX_N3
SATA_SBTX_C_DRX_P3
<35>
<35>
<35>
<35>
B
CLK_PCIE_SATA# <6>
CLK_PCIE_SATA <6>
1
24.9_0402_1%~D
Within 500 mils
ICH9M REV 1.0
Description
1
R905
100K_0402_5%~D
@ R249
1K_0402_5%~D
RTC_BAT_DET#
1
1
Set PCIE port config bit 1
<43> RTC_BAT_DET_R#
@ R907
0_0402_5%~D
RTC_BAT_DET_R# 1
2
2
1M_0402_5%~D
1
3
2N7002W-7-F_SOT323-3~D
Q96
1
Normal Operation (Default)
1
Enter XOR Chain
0
2
1
1
1
2
ICH_RSVD_TP3 <24>
0
+COINCELL
R906
ICH_AZ_SDOUT
RSVD
2
G
0
S
0
D
HDA SDOUT
+3.3V_RUN
@ R248
1K_0402_5%~D
2
ICH RSVD_TP3
1
+3.3V_RUN
XOR Chain Entrance Strap
R908
1K_0402_5%~D
A
2
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
ICH9-M(2/4)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
23
of
71
5
4
10/100/1G LAN --->
SIO_SLP_M#
CL_CLK0
CL_CLK1
F24
B19
CL_CLK0 <10>
ICH_CL_CLK1 <34>
CL_DATA0
CL_DATA1
F22
C19
CL_DATA0 <10>
ICH_CL_DATA1 <34>
CL_VREF0
CL_VREF1
C25
A19
+CL_VREF0_ICH
+CL_VREF1_ICH
CL_RST0#
CL_RST1#
F21
D18
CL_RST0#
ICH_CL_RST1#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
A16
C18
C11
C20
ME_SUS_PWR_ACK
AC_PRESENT
ME_WOL_EN
CLK_ICH_14M
ICH_LAN_RST#
CL_RST0#
<10>
ICH_CL_RST1# <34>
PERN2
PERP2
PETN2
PETP2
C322 1
C323 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_IRX_MCARDTX_N3
PCIE_IRX_MCARDTX_P3
PCIE_ITX_MCARDRX_N3
PCIE_ITX_MCARDRX_P3
J29
J28
K27
K26
PERN3
PERP3
PETN3
PETP3
C1008 1
C1009 1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4
PCIE_ITX_EXPRX_P4
G29
G28
H27
H26
PERN4
PERP4
PETN4
PETP4
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6
PCIE_ITX_GLANRX_P6
C29
C28
D27
D26
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
ICH_EC_SPI_CLK
ICH_SPI_CS0#_R
ICH_SPI_CS1#_R
D23
D24
F23
ICH_EC_SPI_DO
ICH_EC_SPI_DIN
D25
E23
USB_OC0_1#
USB_OC1#
USB_OC2#
ESATA_USB_OC#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC8#
USB_OC9#
USB_OC10#
USB_OC11#
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
PCIE_IRX_EXPTX_N4
PCIE_IRX_EXPTX_P4
PCIE_ITX_EXPRX_N4_C
PCIE_ITX_EXPRX_P4_C
<29>
<29>
<29>
<29>
PCIE_IRX_GLANTX_N6
PCIE_IRX_GLANTX_P6
PCIE_ITX_GLANRX_N6_C
PCIE_ITX_GLANRX_P6_C
<22> ICH_SPI_CS1#
C328
1
2
1
8
7
6
5
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
R294
33_0402_5%~D
ICH_SPI_CS0#
1
2
ICH_SPI_CS1#
1
2
R377
33_0402_5%~D
0.1U_0402_16V4Z~D
R299
3.3K_0402_5%~D
R1045
0_0402_5%~D
<33> USB_OC0_1#
1
2
<33> USB_OC2#
<33> ESATA_USB_OC#
R301
33_0402_5%~D
SPI_CLK_R1 1
2 ICH_EC_SPI_CLK
SPI_DO_R1 1
2 ICH_EC_SPI_DO
R302
33_0402_5%~D
2
VCC
HOLD#
SCLK
SI
C326 1
C327 1
1
1
2
1
R303
22.6_0402_1%~D
0.1U_0402_16V4Z~D
@ R380
3.3K_0402_5%~D
8
7
6
5
W25X16-VSSIG_SO8~D
@ R308
33_0402_5%~D
SPI_CLK_R2 1
2
SPI_DO_R2
1
2
@ R309
33_0402_5%~D
AG2
AG1
PCIE_MCARD1_DET# <34>
ME_SUS_PWR_ACK <38>
AC_PRESENT <38>
ME_WOL_EN <38>
ICH_EC_SPI_DIN1
R385
ICH_EC_SPI_CLK
ICH_EC_SPI_DO
4
2 ICH_SPI_DIN_R
0_0402_5%~D
Follow Daisy Chain and Star
Topology. Place close to U10
pinE23 within 500mils
1
1
2
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V27
V26
U29
U28
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
USB
AF29
AF28
DMI_IRCOMP
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2
<10>
<10>
<10>
<10>
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3
<10>
<10>
<10>
<10>
CLK_PCIE_ICH# <6>
CLK_PCIE_ICH <6>
1
Straped high ROW TPM
TPM_ID
Straped low China_TPM
@ R285
10_0402_5%~D
2
5@
1
2
+3.3V_WLAN
1
2
24.9_0402_1%~D
+1.5V_RUN_PCIE_ICH
----->Right Side Top
----->Right Side Bottom
----->Left Side Top
----->Left Side Bottom
----->WLAN
----->WWAN
ICH_SMBDATA 6
----->WPAN
----->Card Bus
+3.3V_M
----->DOCK
----->DOCK
ICH_SMBCLK 3
----->BIO
----->Camera
@ C318
4.7P_0402_50V8C~D
6@
+CL_VREF1_ICH
1
R292
C
CLK_ICH_48M
Within 500 mils
USBP0- <33>
USBP0+ <33>
USBP1- <33>
USBP1+ <33>
USBP2- <33>
USBP2+ <33>
USBP3- <33>
USBP3+ <33>
USBP4- <34>
USBP4+ <34>
USBP5- <34>
USBP5+ <34>
USBP6- <34>
USBP6+ <34>
USBP7- <31>
USBP7+ <31>
USBP8- <35>
USBP8+ <35>
USBP9- <35>
USBP9+ <35>
USBP10- <36>
USBP10+ <36>
USBP11- <19>
USBP11+ <19>
@ C312
4.7P_0402_50V8C~D
Place closely pin U10.AF3
+3.3V_ALW_ICH
2
+3.3V_M
1
+3.3V_M
+CL_VREF0_ICH
1
2
B
MEM_SDATA
MEM_SDATA
<16,17>
MEM_SCLK
<16,17>
Q27A
2N7002DW-T/R7_SOT363-6~D
MEM_SCLK
4
Q27B
2N7002DW-T/R7_SOT363-6~D
A
DELL CONFIDENTIAL/PROPRIETARY
ICH9M REV 1.0
Within 500 mils
2
VCC
HOLD#
SCLK
SI
USBRBIAS
@ R279
10_0402_5%~D
1
L29
L28
M27
M26
PCIE_IRX_MCARDTX_N3
PCIE_IRX_MCARDTX_P3
PCIE_ITX_MCARDRX_N3_C
PCIE_ITX_MCARDRX_P3_C
@
2
1
2
@ R284
10K_0402_5%~D
Place closely pin U10.H1
+3.3V_ALW_ICH
SIO_SLP_M# <38>
2
SATA
GPIO
Clocks
B16
R287
3.24K_0402_1%~D
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2
1
2
SLP_M#
CLK_PWRGD <6>
ICH_CL_PWROK <10,38>
1
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
@ R304
3.3K_0402_5%~D
2
ICH_CL_PWROK
2
C320 1
C321 1
@ C395
1
2
5
R6
1
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
Flash ROM
@ U13
1 CS#
2 SO
3 WP#
4 GND
CLPWROK
ICH_RSMRST# <38>
2
<34>
<34>
<34>
<34>
W25X32VSSIG_SO8~D
2SPI_DIN_R2
33_0402_5%~D
2
0_0402_5%~D
CLK_PWRGD
1
PERN1
PERP1
PETN1
PETP1
+3.3V_LAN
ICH_SPI_CS1#
ICH_SPI_DIN_R 1
@ R384
SPI_WP#_SEL
1
@ R1060
R5
2
N29
N28
P27
P26
U12
SPI_WP#_SEL <37>
SMB
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1
PCIE_ITX_WANRX_P1
R298
3.3K_0402_5%~D
A
CK_PWRGD
ICH_LAN_RST# <38>
R297
2.2K_0402_5%~D
2 0.1U_0402_10V7K~D
2 0.1U_0402_10V7K~D
200 MIL SO8
2SPI_DIN_R1
33_0402_5%~D
2
0_0402_5%~D
ICH_RSMRST#
R296
2.2K_0402_5%~D
C317 1
C319 1
Express card--->
CS#
SO
WP#
GND
ICH_LAN_RST#
D22
+3.3V_RUN
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
<32>
<32>
<32>
<32>
1
2
3
4
D20
RSMRST#
1
+3.3V_ALW_ICH
8.2K_0402_5%~D
SIO_PWRBTN# <38>
ICH9M REV 1.0
<34>
<34>
<34>
<34>
<34>
<34>
<34>
<34>
10K_1206_8P4R_5%~D
USB_OC9#
1
2
R288
10K_0402_5%~D
USB_OC10#
1
2
R291
10K_0402_5%~D
USB_OC8#
1
2
R293
10K_0402_5%~D
ICH_SPI_CS0#
ICH_EC_SPI_DIN1
R300
SPI_WP#_SEL
1
R386
LAN_RST#
2
R275
D
R290
453_0402_1%~D
10K_1206_8P4R_5%~D
RP2
USB_OC5#
5
4
USB_OC6#
6
3
USB_OC7#
7
2
USB_OC11#
8
1
For iAMT
SIO_PWRBTN#
1
BT/UWB--->
+3.3V_LAN
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
ICH_BATLOW#
C325
0.1U_0402_16V4Z~D
B
M7
AJ24
B21
AH20
AJ20
AJ21
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
2
100K_0402_5%~D
2
100K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
100K_0402_5%~D
R922
100K_0402_5%~D
MiniWLAN (Mini Card 2)--->
4
3
2
1
TP11
B13
R3
1
+3.3V_ALW_ICH
5
6
7
8
VRMPWRGD
A20
BATLOW#
PWRBTN#
U10D
MiniWWAN (Mini Card 1)--->
USB_OC0_1#
USB_OC2#
ESATA_USB_OC#
USB_OC4#
D21
<10,47>
R273
100K_0402_5%~D
Option to " Disable " clkrun.
Pulling it down will keep the
clks
running.
RP1
2 ITP_DBRESET#
100K_0402_5%~D
2 DMI_TERM_SEL
1K_0402_5%~D
1
@ R811
1
@ R789
WAKE#
SERIRQ
THRM#
DPRSLPVR
2
2
@ R283
10_0402_5%~D
SPKR
MCH_ICH_SYNC#
ICH_RSVD_TP3
ICH_TP8
ICH_TP9
ICH_TP10
DPRSLPVR
ICH_CL_PWROK 1
R250
DPRSLPVR
1
@ R253
ICH_PWRGD
1
R257
ICH_RSMRST# 1
R260
ME_WOL_EN
1
R263
2
<27>
SPKR
<10> MCH_ICH_SYNC#
<23> ICH_RSVD_TP3
PAD~D T50
@ PAD~D T51
@ PAD~D T52
@
M2
DPRSLPVR/GPIO16
ICH_PWRGD <10,41>
R286
3.24K_0402_1%~D
2
@
@ PAD~D T133
<33>
IO_LOOP
<6> SATA_CLKREQ#
<26,38> ODD_DET#
PAD~D T48
@
<26> HDD_DET#
CLKRUN#
T130 PAD~D
@
1
1
2
1
1
2
@
@ PAD~D T132
ICH_PWRGD
R276
10K_0402_5%~D
CLKRUN#
1
C316
4700P_0402_25V7K~D
2
@
C315
47P_0402_50V8J~D
1
R282
8.2K_0402_5%~D
C313
47P_0402_50V8J~D
C
2
0_0402_5%~D
2
0_0402_5%~D
ICH_GPIO26
G20
HDD_DET#
SIO_SLP_S3# <37>
SIO_SLP_S4# <38>
SIO_SLP_S5# <38>
2
<34> USB_MCARD2_DET#
C10
PWROK
2
100K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
R289
453_0402_1%~D
1
R280
1
R281
<34> USB_MCARD1_DET#
S4_STATE#/GPIO26
T44 PAD~D
@
2
High = No Reboot
+3.3V_RUN
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S5#
1
R836
2
R760
1
R759
ODD_DET#
1
Low = Default
SPKR
STP_PCI#
STP_CPU#
AG19
AH21
AG21
SIO_EXT_SMI#
A21
LAN_DISABLE#
C12
CONTACTLESS_DET#
C21
AE18
K1
ICH_GPIO20
AF8
AJ22
ICH_GPIO27
A9
IO_LOOP
D19
SATA_CLKREQ#
L1
ODD_DET#
AE19
WPAN_RADIO_DIS_MINI# AG22
HDD_DET#
AF21
DMI_TERM_SEL
AH24
A8
C16
E16
G17
1394_DET#
CLK_ICH_14M <6>
CLK_ICH_48M <6>
R271
10K_0402_5%~D
<38> SIO_EXT_SMI#
<29> LAN_DISABLE#
<36> CONTACTLESS_DET#
@ PAD~D T90
SMBALERT#/GPIO11
SIO_EXT_SCI#
TPM_ID
P1
SLP_S3#
SLP_S4#
SLP_S5#
PMSYNC#/GPIO0
A14
E19
E20
M5
AJ23
ICH_TP11
SUS_STAT#/LPCPD#
SYS_RESET#
A17
L4
SUSCLK
ICH_SUSCLK
2
2
0_0402_5%~D
M6
CLK_ICH_14M
CLK_ICH_48M
+3.3V_RUN
2
1
R277
<37> SIO_EXT_WAKE#
No Reboot Strap
R4
G19
H1
AF3
CLK14
CLK48
SPEAKER_DET# <28>
USB_MCARD3_DET# <34>
1394_DET#
<31>
1
<38> SIO_EXT_SCI#
RI#
SPEAKER_DET#
USB_MCARD3_DET#
1394_DET#
2
Stuff = Enable
F19
AH23
AF19
AE21
AD20
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
1
@ PAD~D T45
No stuff = Disable
R270
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
C324
0.1U_0402_16V4Z~D
iTPM
2 CONTACTLESS_DET#
100K_0402_5%~D
1
R822
G16
A13
E17
C17
B18
2
8.2K_0402_5%~D
5
2 ICH_EC_SPI_DO
1K_0402_5%~D
1
R256
U10C
SYS GPIO
Power MGT
1
@ R270
+3.3V_ALW_ICH
2 ICH_SMBCLK
2.2K_0402_5%~D
ICH_SMBCLK
2 ICH_SMBDATA
2.2K_0402_5%~D
ICH_SMBDATA
ICH_GPIO60
2 ICH_CL_RST1#
10K_0402_5%~D
AMT_SMBCLK
<38> AMT_SMBCLK
AMT_SMBDAT
2 AMT_SMBCLK
<38> AMT_SMBDAT
10K_0402_5%~D
I CH_RI#
2 AMT_SMBDAT
10K_0402_5%~D
@ PAD~DT173
SUS_STAT#/LPCPD#
2 I CH_RI#
10K_0402_5%~D
ITP_DBRESET#
<7> ITP_DBRESET#
2 ICH_PCIE_WAKE#
10K_0402_5%~D
PM_SYNC#
<10> PM_SYNC#
1 ME_SUS_PWR_ACK
10K_0402_5%~D
SMB_ALERT#
IO_LOOP
2
H_STP_PCI#
100K_0402_5%~D
<6>
H_STP_PCI#
H_STP_CPU#
2 SIO_EXT_SMI#
<6> H_STP_CPU#
10K_0402_5%~D
CLKRUN#
2 ICH_GPIO60
<29,31,37,38> CLKRUN#
10K_0402_5%~D
ICH_PCIE_WAKE#
2 SMB_ALERT#
<37> ICH_PCIE_WAKE#
10K_0402_5%~D
IRQ_SERIRQ1
2 IRQ_SERIRQ_ICH
<29,31,36,37,38> IRQ_SERIRQ
RSV_THRM#
R1126
2 LAN_DISABLE#
33_0402_5%~D
10K_0402_5%~D
IMVP_PWRGD
function
<37,41,47> IMVP_PWRGD
MISC
GPIO
Controller Link
+3.3V_LAN
1
+3.3V_RUN
1
R252
1
R255
1
@ R259
1
R262
1
R265
1
R267
1
R268
2
R269
1
R835
1
R274
1
R787
1
R192
1
@ R295
PCI-Express
D
+3.3V_ALW_ICH
2 IMVP_PWRGD
2.2K_0402_5%~D
2 MCH_ICH_SYNC#
10K_0402_5%~D
2 RSV_THRM#
8.2K_0402_5%~D
1 IRQ_SERIRQ
10K_0402_5%~D
2 SPKR
1K_0402_5%~D
2 SPEAKER_DET#
100K_0402_5%~D
2 SIO_EXT_SCI#
10K_0402_5%~D
Direct Media Interface
1
@ R251
1
@ R254
1
R258
2
R261
1
@ R264
1
R834
1
R272
2
SPI
+3.3V_RUN
3
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
3
Title
ICH9-M(3/4)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
24
of
71
5
4
3
2
1
+RTC_CELL
ICH_V5REF_SUS
2
1
2
AC12
AC13
AC14
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
AJ5
VCCUSBPLL
AA7
AB6
AB7
AC6
AC7
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
A10
A11
VCCLAN1_05[1]
VCCLAN1_05[2]
A12
B12
VCCLAN3_3[1]
VCCLAN3_3[2]
A27
VCCGLANPLL
D28
D29
E26
E27
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
A26
VCC3_3[2]
AJ6
VCC3_3[7]
AC10
+3.3V_RUN
1
VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
AD19
AF20
AG24
AC20
C349
0.1U_0402_16V4Z~D
1
2
2
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
B9
F9
G3
G6
J2
J7
K7
CORE
VCCHDA
AJ4
VCCSUSHDA
AJ3
VCCSUS1_05[1]
VCCSUS1_05[2]
AC8
F17
VCCSUS1_5[1]
AD8
VCCSUS1_5[2]
F18
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
A18
D16
D17
E22
VCCSUS3_3[5]
AF1
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
VCCCL1_05
G22
VCCCL1_5
G23
VCCCL3_3[1]
VCCCL3_3[2]
A24
B24
2
+3.3V_RUN
1
2
+3.3V/1.5V_RUN_HDA
+3.3V_RUN
1
2
1
2
1
2
2
2
C352
0.1U_0402_16V4Z~D
+3.3V_ALW_ICH
TP_VCCSUS1.05_INT_ICH1
T53
PAD~D@
TP_VCCSUS1.05_INT_ICH2
VCCSUS1_5_ICH_1
T91 PAD~D@
VCCSUS1_5_ICH_2
T122
PAD~D@
2
1
C357
0.1U_0402_16V4Z~D
+3.3V_ALW_ICH
VCCSUS1_5_ICH_2
1
+3.3V_ALW_ICH
2
1
2
VCCCL1_05_ICH 1
C366
VCCCL1_5
1
2
1
2
C360
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
+3.3V_LAN
1
2
1
2
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
VSS_NCTF[1]
VSS_NCTF[2]
VSS_NCTF[3]
VSS_NCTF[4]
VSS_NCTF[5]
VSS_NCTF[6]
VSS_NCTF[7]
VSS_NCTF[8]
VSS_NCTF[9]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
D
C
B
ICH9M REV 1.0
A
VCCGLAN3_3
ICH9M REV 1.0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
http://hobi-elektronika.net
4
2
2
1
+3.3V_RUN
R314
0_0603_5%~D
2
1
+1.5V_RUN
@ R315
0_0603_5%~D
Choice to support GMCH
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
1
+3.3V/1.5V_RUN_HDA
+3.3V_RUN
1
1
C369
0.1U_0402_16V4Z~D
2
+3.3V_RUN
VCC1_5_A[21]
VCC1_5_A[22]
VCC3_3[1]
AG29
C355
0.1U_0402_16V4Z~D
2
1
C373
4.7U_0603_6.3V6M~D
2
1
C372
2.2U_0603_6.3V6K~D
1
C371
10U_0805_4VAM~D
A
VCC1_5_A[20]
G10
G9
AB23
AC23
1
+1.05V_VCCP
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
GLAN POWER
+1.5V_RUN
VCC1_5_A[18]
VCC1_5_A[19]
AC21
V_CPU_IO[1]
V_CPU_IO[2]
2
C368
1U_0603_10V4Z~D
+VCCGLANPLL
+VCCGLANPLL_L1
2
L17
1UH_20%_0805~D
VCC1_5_A[17]
+VCC_DMI_ICH
5ohm@100MHz
1
2
+1.05V_VCCP
L15
BLM18PG181SN1_0603~D
C354
0.1U_0402_16V4Z~D
+1.5V_RUN
AC9
AC18
AC19
+VCCDMIPLL
W23
Y23
+1.5V_RUN
L14
BLM18PG181SN1_0603~D
1
2
2
1
R312
1_0603_1%~D
C363
0.1U_0402_16V4Z~D
VCCLAN1.05_INT_ICH
1
2
C370
0.1U_0402_16V4Z~D
VCC1_5_A[9]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
USB CORE
2
C367
0.1U_0402_16V4Z~D
1
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
R29
VCC_DMI[1]
VCC_DMI[2]
C362
0.022U_0402_16V7K~D
2
+3.3V_LAN
C365
0.1U_0402_16V4Z~D
1
2
C364
0.1U_0402_16V4Z~D
1
VCC1_5_A[1]
VCC1_5_A[2]
VCC1_5_A[3]
VCC1_5_A[4]
VCC1_5_A[5]
VCC1_5_A[6]
VCC1_5_A[7]
VCC1_5_A[8]
VCCDMIPLL
C361
0.022U_0402_16V7K~D
B
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
ATX
2
C359
1U_0603_10V4Z~D
1
VCCSATAPLL
ARX
2
C358
1U_0603_10V4Z~D
1
AJ19
2
C353
0.1U_0402_16V4Z~D
C351
1U_0603_10V4Z~D
C350
10U_0805_4VAM~D
1
1
1
MMBD4148-7-F_SOT23-3~D
C347
0.1U_0402_16V4Z~D
C
2
2
C348
0.1U_0402_16V4Z~D
+1.5V_RUN_SATAPLL
L16
10UH_LB2012T100MR_20%_0805~D
+VCCSATAPLLR 1
2
VCCA3GP
+1.5V_RUN
1
1
C346
0.1U_0402_16V4Z~D
C342
1U_0603_10V6K~D
2
2
10_0805_5%~D
C345
0.1U_0402_16V4Z~D
2
1
+1.05V_VCCP_D 1
3
C344
4.7U_0603_6.3V6M~D
1
VCC1_5_B[1]
VCC1_5_B[2]
VCC1_5_B[3]
VCC1_5_B[4]
VCC1_5_B[5]
VCC1_5_B[6]
VCC1_5_B[7]
VCC1_5_B[8]
VCC1_5_B[9]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
C343
4.7U_0603_6.3V6M~D
1
D16
RB751S40T1_SOD523-2~D
2
R313
100_0402_5%~D
V5REF_SUS
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
VCCP_CORE
2
V5REF
PCI
2
2
1
2
1
VCC1_05[1]
VCC1_05[2]
VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
VCC1_05[8]
VCC1_05[9]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
C341
10U_0805_4VAM~D
+3.3V_ALW_ICH
1
AE1
VCCRTC
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C340
0.01U_0402_16V7K~D
2
+5V_ALW
1
A6
ICH_V5REF_SUS
C339
2.2U_0603_6.3V6K~D
+
I CH_V5REF_RUN
C338
22U_0805_6.3V6M~D
1
C337
22U_0805_6.3V6M~D
C335
1U_0603_10V6K~D
+1.5V_RUN_PCIE_ICH
L13
+1.5V_RUN_PCIE_ICH
1
2
BLM21PG600SN1D_0805~D
+1.5V_RUN
C336
220U_D2_4VY_R15M~D
2
R310
1
VCCPSUS
1
2
D
+1.05V_VCCP
U10F
A23
C334
0.1U_0402_16V4Z~D
1
2
+1.5V_RUN
2
C333
0.1U_0402_16V4Z~D
I CH_V5REF_RUN
2
U10E
+1.05V_VCCP
D14
VCCPUSB
2
1
2
D15
RB751S40T1_SOD523-2~D
1
C332
0.1U_0402_16V4Z~D
R311
100_0402_5%~D
1
C331
0.1U_0402_16V4Z~D
+5V_RUN +3.3V_RUN
C330
1U_0603_10V4Z~D
1
3
2
Title
ICH8(4/4)
Size
Document Number
Date:
Thursday, June 12, 2008
Re v
0.8
LA-3803P
Sheet
1
25
of
71
5
4
3
2
1
D
D
+5VMOD Source
+15V_ALW
GND1
GND2
14
15
2
<37> MODC_EN
1
TYCO_2-1759838-8
R319
100K_0402_5%~D
Pleace near ODD CONN
Main SATA +5V Default
2
2
Main SATA +5V Default
Pleace near HDD CONN
4
1
2
5
6
4
1
2
1
2
5
6
2
1
3
4
1
2
2
1
R323
100K_0402_5%~D
TYCO_1775707-3_RV
1
+5V_RUN
PJP3
1
R322
100K_0402_5%~D
2
<37> HDDC_EN
+5V_HDD
2
@
23
24
S
C383
10U_0805_10V4Z~D
GND1
GND2
3
C382
0.1U_0603_50V4Z~D
2
5
D Q32
SI3456BDV-T1-E3_TSOP6~D
G
HDD_EN_5V
Q34B
2N7002DW-T/R7_SOT363-6
2
1
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
Q34A
2N7002DW-T/R7_SOT363-6
1
HDD_DET#
+5V_HDD
@ C388
0.1U_0402_10V7K~D
2
<24> HDD_DET#
@ C387
0.1U_0402_16V4Z~D
2
1
@ C386
10U_0805_10V4Z~D
2
1
C385
0.1U_0402_16V4Z~D
1
C384
1000P_0402_50V7K~D
B
+3.3V_RUN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
R320
100K_0402_5%~D
R321
100K_0402_5%~D
2
close SATA connector
+5V_HDD
+3.3V_RUN
+3.3V_ALW2
6
PSATA_IRX_DTX_N0
1
1 0.01U_0402_16V7K~D PSATA_IRX_DTX_P0
0.01U_0402_16V7K~D
PAD-OPEN 4x4m
+5V_ALW
GND
RX+
RXGND
TXTX+
GND
1
2
C380 2
C381
2
2
+15V_ALW
1
<23> PSATA_IRX_DTX_N0_C
<23> PSATA_IRX_DTX_P0_C
1
2
3
4
5
6
7
1
+5V_RUN
PJP2
1
HDD PWR
JSATA2
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
+5V_MOD
C
For HDD
<23> PSATA_ITX_DRX_P0
<23> PSATA_ITX_DRX_N0
2
4
C
1
1
2
3
2
6
5
S
@
R318
100K_0402_5%~D
DP
+5V
+5V
MD
GND
GND
Q31A
2N7002DW-T/R7_SOT363-6
8
9
10
11
12
13
3
C379
10U_0805_10V4Z~D
close SATA connector
D Q29
SI3456BDV-T1-E3_TSOP6~D
G
2 MOD_EN
1
<23> SATA_ODD_IRX_DTX_P1_C
1 SATA_ODD_IRX_DTX_N1
0.01U_0402_16V7K~D
1 SATA_ODD_IRX_DTX_P1
0.01U_0402_16V7K~D
ODD_DET#
<24,38> ODD_DET#
+5V_MOD
2
C374
2
C375
R316
100K_0402_5%~D
R317
100K_0402_5%~D
C378
0.1U_0603_50V4Z~D
2
<23> SATA_ODD_IRX_DTX_N1_C
GND
RX+
RXGND
TXTX+
GND
Q31B
2N7002DW-T/R7_SOT363-6
1
C377
0.1U_0402_16V4Z~D
2
C376
1000P_0402_50V7K~D
1
1
2
3
4
5
6
7
1
JSATA1
SATA_ODD_ITX_DRX_P1
SATA_ODD_ITX_DRX_N1
<23> SATA_ODD_ITX_DRX_P1
<23> SATA_ODD_ITX_DRX_N1
2
+3.3V_ALW2
+5V_MOD
+5V_ALW
1
For ODD
PAD-OPEN 4x4m
Open
B
+5V_HDD Source
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
ODD/HDD CONNECTOR
Size
Document Number
Date:
Thursday, June 12, 2008
R ev
0.8
LA-3803P
Sheet
1
26
of
71
2
1
+3.3V_RUN
L18
BLM18EG601SN1D_2P~D
1
2
+3.3V_RUN_I2S_VDD
7
I2S_BCLK
DACDAT
ADCDAT
8
10
I2S_DI#
I2S_DO
DACLRC
ADCLRC
9
11
I2S_LRCLK
NC_ADCLRC
Thermal Pad
29
PORT_B_L
PORT_B_R
VREFOUT_B
21
22
28
PORT_C_L
PORT_C_R
VREFOUT_C
23
24
29
AUD_EXT_MIC_L <33>
AUD_EXT_MIC_R <33>
+VREFOUT
C1068
1000P_0402_50V7K~D
1
2
PORT_D_L
PORT_D_R
35
36
+3.3V_RUN
R331
10K_0402_5%~D
1
2
@ R330
10K_0402_5%~D
SPDIF_OUT_0_1/EAPD/GPIO0
48
SPDIF_OUT_0
NC
NC
NC
18
19
20
@ C412
10P_0402_50V8J~D
2
1
AUD_DOCK_HP_OUT_L
AUD_DOCK_HP_OUT_R
33
27
2
1
1
2
92HD71B7X5NLGXB3X8_QFN48_7x7~D
@ R344
47_0402_5%~D
1
2
1U_0603_10V6K~D
26
42
AVSS
AVSS
Thermal PAD GND
C414
49
ICH_AZ_CODEC_SDOUT
DVSS
10U_0805_10V6K~D
C415
7
CAP2
VREFFILT
1
+3.3V_RUN
@
U17
16
1A
1Y#
3
DAI_BCLK#
<35>
4
2A
2Y#
5
DAI_LRCK#
<35>
6
3A
3Y#
7
DAI_DO#
<35>
DAI_12MHZ# <35>
2
2
1
R345
1K_0402_5%~D
10
4A
4Y#
9
12
5A
5Y#
11
14
6A
6Y#
13
1
15
OE1#
OE2#
GND
8
R354
100K_0402_5%~D
2
1
4
5
1
4
2
Q40A
2N7002DW-T/R7_SOT363-6~D
Y
A
2
1
2
4
1
R762
DOCK_MIC_DET <37>
Q40B
2N7002DW-T/R7_SOT363-6~D
A
D20
DA204U_SOT323-3~D
@
G
@ U18
74LVC1G14GV_SOT753-5
AUD_MIC_SWITCH <33>
<37> DOCK_HP_DET
@
1
5
1
1
@
2
2
+3.3V_RUN
3
2
2
1
2
2
4
1
6
1
1
1
2
2
6
3
1
1
2
5
Q38B
2N7002DW-T/R7_SOT363-6~D
+3.3V_RUN
+3.3V_RUN
C419
0.1U_0402_16V7K~D
2
Q38A
2N7002DW-T/R7_SOT363-6~D
1
C420
1000P_0402_50V7K~D
<28,33,37> AUD_HP_NB_SENSE
R352
39.2K_0402_1%~D
R355
100K_0402_5%~D
R353
100K_0402_5%~D
2
+3.3V_RUN
R351
20K_0402_1%~D
1
C417
1000P_0402_50V7K~D
R349
20K_0402_1%~D
R348
39.2K_0402_1%~D
R350
100K_0402_5%~D
AUD_SENSE_B
+3.3V_RUN
+3.3V_RUN
C418
0.1U_0402_16V7K~D
AUD_SENSE_A
+3.3V_RUN
+VDDA_AVDD
R347
5.11K_0402_1%~D
2
1
NC
P
Place closely to Pin 34
R346
5.11K_0402_1%~D
2
1
Place closely to Pin 13.
I2S_DI#
CD74HC366M96_SO16~D
+VDDA_AVDD
A
@
I2S_LRCLK
@C416
0.1U_0402_10V7K~D
<37> EN_I2S_NB_CODEC
@
2
I2S_DO
2
VCC
@
I2S_BCLK
I2S_12MHZ
1
CKG_SMBDAT <6,38,48>
D55
DA204U_SOT323-3~D
Close to U16 pin5
GPIO5
GPIO6
SPDIF_OUT_1/GPIO7
3
D19
DA204U_SOT323-3~D
CAP2
VREFFILT
+3.3V_RUN
CKG_SMBCLK <6,38,48>
Q36B
2N7002DW-T/R7_SOT363-6~D
D18
DA204U_SOT323-3~D
MONO_OUT
AUD_PC_BEEP
6
Q36A
2N7002DW-T/R7_SOT363-6~D
4
D17
DA204U_SOT323-3~D
12
32
1
DAI_SMBDATA
C413
0.1U_0402_16V7K~D
PC_BEEP
+3.3V_RUN
For next version I2S.
will disconnect SMBUS
and PU.
Need check the PU
value.
Place close to U16
43
44
45
2
DAI_SMBCLK
200_0402_5%~D
2 AUD_DOCK_HP_L_R
2 AUD_DOCK_HP_R_R
200_0402_5%~D
1
47
<50> SPDIF_OUT
16
17
30
200_0402_5%~D
2AUD_DOCK_MIC_IN_L_C
2AUD_DOCK_MIC_IN_R_C
200_0402_5%~D
T61PAD~D@
SSM2602_LFCSP28_5X5~D
C406
10U_0805_10V6K~D
1
AUD_LINE_OUT_L <28>
AUD_LINE_OUT_R <28>
2
<28> AUD_EAPD
PORT_F_L
PORT_F_R
GPIO3
VMID
5
DMIC1/VOL_DN/GPIO2
CSB
20
+3.3V_RUN
C408 1U_0805_16V7K~D
R1091
2
1 DOCK_MIC_IN_L_C 1
2
1 DOCK_MIC_IN_R_C 1
R1092
C409 1U_0805_16V7K~D
C410 0.22U_0805_16V7K~D
R340
AUD_DOCK_HP_L_C
1
2
1
1
2 AUD_DOCK_HP_R_C 1
R342
C411 0.22U_0805_16V7K~D
AUD_DOCK_MIC_IN_L
AUD_DOCK_MIC_IN_R
14
15
31
PORT_E_L
PORT_E_R
GPIO4/VREFOUT_E
Select I2C & SPI
interface
26
B
2
DMIC0/VOL_UP/GPIO1
4
MODE
2
C1069
1000P_0402_50V7K~D
DMIC_CLK
2
25
1
DMIC0
MICIN
MICBIAS
3
46
1
MCLK/XTI
XTO/ POR
2
AUD_HP_OUT_L <28>
AUD_HP_OUT_R <28>
R1090
10M_0402_5%~D
1
6
BCLK
1
2
22
21
T56 PAD~D@
2
39
41
37
1
2
CLKOUT
I2S_12MHZ
1
PORT_A_L
PORT_A_R
NC
R1089
10M_0402_5%~D
@ R343
10_0402_5%~D
C676
150P_0402_50V8J~D
2
NC_LHPOUT
2
92HD71B
L78
BLM18BB221SN1D_0603~D
DMIC_CLK_R
1
2
ICH_AZ_CODEC_BITCLK
13
14
2
HDA_RST#
Close to U16 pin6
LHPOUT
RHPOUT
3
HDA_SYNC
11
<19>
SCLK
SDIN
R335
2.2K_0402_5%~D
13
34
2
10
<23> ICH_AZ_CODEC_RST#
1
28
27
XTALI_12MHZ
XTALO_12MHZ
R334
2.2K_0402_5%~D
C407
0.1U_0402_10V7K~D
<23> ICH_AZ_CODEC_SYNC
Close to U16 pin3
DAI_SMBCLK
DAI_SMBDATA
3
AUD_SENSE_A
AUD_SENSE_B
SENSE_A
SENSE_B
1
<23> ICH_AZ_CODEC_SDOUT
<19> DMIC_CLK
2
2
HDA_SDO
AUD_DOCK_MIC_IN_L_C
AUD_DOCK_MIC_IN_R_C
1
5
HDA_SDI_CODEC
5
16
17
Y
NC
P
8
LOUT
ROUT
RLINEIN
A
2
DAI_DI
<35>
G
ICH_AC_SDIN0_R
2
33_0402_5%~D
ICH_AZ_CODEC_SDOUT
LLINEIN
23
1
@ R329
10K_0402_5%~D
2
1
R332
<23> ICH_AZ_CODEC_SDIN0
+3.3V_RUN
24
AUD_DOCK_HP_R_R
3
HDA_BITCLK
AUD_DOCK_HP_L_R
2
2
1
2
6
4
19
15
3
2
DVSS
AVSS
HPVSS
R333
10K_0402_5%~D
ICH_AZ_CODEC_BITCLK
<23> ICH_AZ_CODEC_BITCLK
2
2
+3.3V_RUN
1
Close to U16 pin1 & pin9
1
25
38
AVDD
AVDD
1
1
2
DVDD_CORE
DVDD_CORE
NC/OTP
DVDD_IO
@
DCVDD
AVDD
HPVDD
DBVDD
2
1
9
40
3
1
1
C1067
1000P_0402_50V7K~D
U16
C401
0.1U_0402_10V7K~D
2
1
+3.3V_RUN
C400
10U_0805_10V6K~D
2
1
C399
0.1U_0402_10V7K~D
1
@
C405
0.1U_0402_10V7K~D
2
C404
1U_0603_10V6K~D
B
1
C403
10U_0805_10V6K~D
2
C402
1000P_0402_50V7K~D
1
L77
BLM18EG601SN1D_2P~D
1
2
+VDDA_AVDD
SSM2602
3
18
12
5
+3.3V_RUN_I2S_AVDD
C1066
1000P_0402_50V7K~D
+3.3V_RUN
U15
1
+VDDA
1
1
3
2
1
1
1
2
2
2
2
1
2
2
1
2
2
1+3.3V_RUN_I2S_AVDD_HPVDD
L70
47UH_LBMF1608T470M_20%~D
1
2
3
1
TRACE>15 mil
@ R328
10K_0402_5%~D
XTALI_12MHZ
2
12MHZ_18PF_1Y712000CE1J~D
1
1
AUD_PC_BEEP
C393
0.1U_0402_16V7K~D
2
499K_0402_1%~D
2
499K_0402_1%~D
C398
0.1U_0402_16V7K~D
BEEP
1
R327
1
R828
C397
4.7U_0603_6.3V4Z~D
<38>
2
0.1U_0402_16V4Z~D
2
0.1U_0402_16V4Z~D
C994
27P_0402_50V8J~D
1
C389
1
C394
SPKR
C995
27P_0402_50V8J~D
<24>
1
C392
0.1U_0402_16V7K~D
Y5
C391
4.7U_0603_6.3V4Z~D
XTALO_12MHZ
2
100_0402_5%~D
1
R786
@ U19
74LVC1G14GV_SOT753-5
2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Azalia (HD) Codec
http://hobi-elektronika.net
2
Size
Document Number
Date:
Thursday, June 12, 2008
Re v
0.8
LA-3803P
1
Sheet
27
of
71
5
4
3
2
1
+5V_SPK_AMP
B
3
A
U20 0.1U_0402_10V7K~D
1
2
Y 4
R357
0_0402_5%~D
74AHCT1G08GW_SOT353-5~D
@
2
AUD_HP_NB_SENSE 1
G
AUD_NB_MUTE
<27,33,37> AUD_HP_NB_SENSE
P
5
C421
1
2
Speaker Connector
JSPK1
15 mils trace
INT_SPK_R1
INT_SPK_R2
INT_SPK_L1
INT_SPK_L2
D
<24> SPEAKER_DET#
Place Close to Audio Chip
8
18
SPVDD
SPVDD
30
VDD
LOUT-
7
INT_SPK_L2
ROUT+
20
INT_SPK_R1
ROUT-
19
INT_SPK_R2
HP_OUTL
16
HP_SPK_L1
HP_OUTR
15
HP_SPK_R1
GAIN0
31
AUD_GAIN1
GAIN1
32
AUD_GAIN2
HP_INL_C
27
HP_INR_C
26
HP_INR
24
BYPASS
HP_INL
2
2
+5V_SPK_AMP
CPVDD
C1N
12
C1N
11
REG_OUT
29
CPGND
SPKR_RIN-
1
1
1
SET
1
TPA6040A4RHBR_QFN32_5X5~D
1
2
For MAX9789A, depop C443,pop R362
R362 0_0402_5%~D
1
2
1
2
C443
0.033U_0402_16V7K~D
+CPVSS
8mil
C450
1U_0603_10V6K~D
2
2
AUD_AMP_MUTE#
2
0_0402_5%~D
4
2
SGND
SPGND
SPGND
TP
C1P
28
5
21
33
1
10
HPVSS
CPVSS
2
C1P
SPKR_LIN-
2
1
RUN_ON
<19,37,40,41,56>
2
HPVDD
9
14
13
R363
1M_0402_1%~D
2
1
1
17
2
1
+VDDA
Minimum 150 mA
GAIN1
1
3
GAIN2
AV(inv)
INPUT
IMPEDANCE
B
*
For
MAX9789A
depop
C449,pop
R366
Q42A
2N7002DW-T/R7_SOT363-6~D
1
AUD_GAIN2
R361
100K_0402_5%~D
1
AUD_GAIN1
REG_EN
@ R360
100K_0402_5%~D
2
25
HP_SPK_R1 <33>
1
HP_EN
2
1
22
<33>
2
/SPKR_EN
AUD_HP_EN
HP_SPK_L1
C449
0.033U_0402_16V7K~D
2
23
R367
100K_0402_5%~D
For TPA6040A,pop
R368,depop R367
1
R368
AUD_SPK_ENABLE#
C448
1U_0603_10V6K~D
1
2
1U_0603_10V6K~D
2
<27> AUD_EAPD
2
Gain Setting
C447
1U_0603_10V6K~D
2
SPKR_RIN+
@ R366
0_0402_5%~D
1
2
@
6
INT_SPK_L1
AUD_AMP_MUTE#
+5V_SPK_AMP
RUN_ON
6
@
AUD_SPK_ENABLE#
LOUT+
C446
1U_0603_10V6K~D
+5V_SPK_AMP
R365
100K_0402_5%~D
SPKR_LIN+
C445
1U_0603_10V6K~D
2
1
C438
C444
10U_0805_10V6K~D
1
R364
100K_0402_5%~D
3
SPKR_INR_C
2
2
1
GND
GND
@ R359
100K_0402_5%~D
2
+5V_SPK_AMP
B
SPKR_INL_C
1
1
1
R358
100K_0402_5%~D
2
1
@ C442
47P_0402_50V8J~D
1
@ C441
47P_0402_50V8J~D
2
2
2
1
7
8
D
C
@ C440
47P_0402_50V8J~D
@ C439
47P_0402_50V8J~D
2
1
U22
1
C433
10U_0805_10V6K~D
<27> AUD_HP_OUT_R
2
2
C432
1U_0603_10V6K~D
C
1
1
C431
10U_0805_10V6K~D
<27> AUD_HP_OUT_L
1
W=40mils
C430
1U_0603_10V6K~D
<27> AUD_LINE_OUT_R
2
1
C434
0 .033U_0805_50V7K~D
2
1
C435
0 .033U_0805_50V7K~D
1
2
1
2
C436
R818
1K_0402_1%~D
10U_1206_25VAK~D
1
2
1
2
C437
R827
1K_0402_1%~D
10U_1206_25VAK~D
1
1
2
C429
0.1U_0402_10V7K~D
1
C428
1U_0603_10V6K~D
2
<27> AUD_LINE_OUT_L
+5V_SPK_AMP
Place Close to Audio Chip
+5V_SPK_AMP
74AHCT1G08GW_SOT353-5~D
C427
1U_0603_10V6K~D
3
B
AUD_HP_EN
4
G
Y
1
2
3
4
5
6
MOLEX_53780-0670~D
2
5
U21 0.1U_0402_10V7K~D
P
A
@ C426
100P_0402_50V8J~D
1
@ C425
100P_0402_50V8J~D
2
@ C424
100P_0402_50V8J~D
AUD_EAPD
<27> AUD_EAPD
L19
BLM21PG600SN1D_0805~D
1
2
+5V_RUN
@ C423
100P_0402_50V8J~D
+5V_SPK_AMP
C422
1
2
1
2
3
4
5
6
0
0
6dB
82K ohm
0
1
10dB
66K ohm
1
0
15.6dB
45K ohm
1
1
21.6dB
26K ohm
5
<37> AUD_NB_MUTE
4
Q42B
2N7002DW-T/R7_SOT363-6~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
AMP and PHONE JACK
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
28
of
71
5
4
3
2
1
Layout Notice : Place as close
chip as possible.
+3.3V_ALW
1
2
4
1
1
2
1
2
DOCKED
4
3
TPS73601
1
1
5
ADJ
R1017
4.64K_0402_1%
Q146
2
R1020
10K_0402_5%~D
2
MMBT3906WT1G_SC70-3~D
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
R1018
39.2K_0402_1%~D
2
<30,37> DOCKED
VOUT
C
+1V_LAN_M
C645
0.1U_0402_16V4Z~D
200_0402_5%~D
2
200_0402_5%~D
2
200_0402_5%~D
2
2
VIN
GND
EN
2
C603
0.1U_0402_16V4Z~D
1
T146 PAD~D@
T147 PAD~D@
T148 PAD~D@
1
2
3
1
35
40
39
7
6
1
+LOM_VCT
Q50
1
Follow 82567 schematic
chiplist that VCC_1.0 for
external use 10uF XR5 *2 and
0.1uF *2
for internal use 4.7uF X5R *2
and 0.1uF *1
2
R1019
36.5K_0402_1%~D
+3.3V_RUN
4@
1
2
C480
0.1U_0402_16V4Z~D
LOW:Power Down Mode
High:Working Mode
1
2
C479
0.1U_0402_16V4Z~D
@ R890
1
@ R916
JTAG_TCK_LAN 1
@ R915
JTAG_TMS_LAN 1
JTAG_TDI_LAN
Need to ensure
crystal at least
300uW max power
drive-level
1
2
C478
4.7U_0805_10V4Z~D
+3.3V_LAN
2
2
C477
4.7U_0805_10V4Z~D
1
VOUT = 1.204 (1+R1/R2),
where R1 = R1017 + R1018, R2 = R1019
+3.3V_LAN
82567LM_QFN56~D
C481
0.1U_0402_16V4Z~D
C476
12P_0402_50V8J~D
2
1
Q45
BCP69_SOT223~D
C483
4.7U_0603_6.3V4Z~D
1
C475
12P_0402_50V8J~D
2
1
+1.8V_LAN_M
JTAG_TDI_LAN
JTAG_TMS_LAN
JTAG_TCK_LAN
JTAG_TRST_LAN
@ R891
1K_0402_5%~D
1
2
XTALI
Y2
25MHZ_12PF1HX25000CE1G~D 2
2
57
JTAG_TDO_LAN
@ R889
0_0402_5%~D
1
2
XTALO
2
GND_PAD
1
1
REGCTL_PNP18
C482
4.7U_0603_6.3V4Z~D
1
RESERVED_NC
51
Trace=12mil
REGCTL_PNP18
1
XTAL2
XTAL1
<37> LAN_DISABLE#_R
2
100_0402_5%~D
29
31
2
1
Trace=12mil
R374
5.1K_0402_5%~D
2
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
TEST_EN
C
1
R379
CTRL18
CTRL10
+1.8V_LAN_M
+3.3V_LAN_R
C473
470P_0402_50V7K~D
1
1U_0402_6.3V6K~D
LAN_DISABLE_N
D
C472
470P_0402_50V7K~D
37
LAN_DISABLE#_R
R378
36
1
2
10K_0402_5%~D
XTALO
9
XTALI
10
2
4.3K_0402_5%~D
1
RB751S40T1_SOD523-2~D
1
C471
4.7U_0603_6.3V4Z~D
DIS_REG10
1
2
C470
0.1U_0402_16V4Z~D
IEEE_TEST_P
IEEE_TEST_N
34
+1.8V_LAN_M
1
C474
10U_0805_10V4Z~D
2
@ C677
1 1K_0402_5%~D
1 1K_0402_5%~D
12
13
11
14
19
18
24
25
41
54
32
30
1
2
1
2
C469
0.1U_0402_16V4Z~D
1
@ R1008
2
@ D38
@ R375 2
R376 2
LAN_TEST_P
LAN_TEST_N
AVDD_18_11
AVDD_18_14
AVDD_18_19
AVDD_18_18
AVDD_18_24
AVDD_18_25
AVDD_18_41
AVDD_18_54
AVDD_18_32
AVDD_18_30
2
1
2
C468
0.1U_0402_16V4Z~D
+3.3V_LAN
2
0_0402_5%~D
+1V_LAN_M
2
C467
10U_0805_10V4Z~D
1
@ R373
RSET
5
8
33
38
2
+3.3V_LAN
C466
10U_0805_10V4Z~D
15
1
4.99K_0402_1%~D
2
R372
LED_0
LED_1
LED_2
DVDD_10_5
DVDD_10_8
DVDD_10_33
DVDD_10_38
+3.3V_LAN
C465
0.1U_0402_16V4Z~D
4
2
1
VDDO_33_3
VDDO_33_46
AVDD_33_28
1
<40> ENAB_3VLAN
R371
2_1210_5%~D
JRXD_0
JRXD_1
JRXD_2
<30>
<30>
2
47
48
49
3
46
28
LAN_TX3LAN_TX3+
1
+3.3V_LAN
Q44
STS11NF30L_SO8~D
1
2
3
3
LAN_RX0
LAN_RX1
LAN_RX2
LAN_TX3LAN_TX3+
1
8
7
6
5
1
<23>
<23>
<23>
16
17
<30>
<30>
2
R370
JTXD_0
JTXD_1
JTXD_2
MDI_N_3
MDI_P_3
LAN_TX2LAN_TX2+
2
2_1210_5%~D
42
43
44
LAN_TX2LAN_TX2+
<30>
<30>
C464
4.7U_0603_6.3V4Z~D
LAN_TX0
LAN_TX1
LAN_TX2
20
21
<30>
<30>
LAN_TX1LAN_TX1+
C463
0.1U_0402_16V4Z~D
<23>
<23>
<23>
<30> LOM_ACTLED_YEL#
<30> LOM_SPD100LED_ORG#
<30> LOM_SPD10LED_GRN#
For internal 1.0V
regulator strap
R376 and unstuff
R375,R377 and Q46
<24> LAN_DISABLE#
R369
MDI_N_2
MDI_P_2
LAN_TX0LAN_TX0+
C459
0.1U_0402_16V4Z~D
D
MDI_N_1
MDI_P_1
LAN_TX1LAN_TX1+
C458
0.1U_0402_16V4Z~D
JKCLK
JRSTSYNC
1
LAN_TX0LAN_TX0+
22
23
C457
4.7U_0603_6.3V4Z~D
<23>
LAN_CLK
<23> LAN_RSTSYNC
26
27
C456
4.7U_0603_6.3V4Z~D
GLAN_RXP
GLAN_RXN
2 LAN_CLK_R 45
33_0402_5%~D 50
MDI_N_0
MDI_P_0
C455
10U_0805_10V4Z~D
55
56
2
GLAN_TXP
GLAN_TXN
<24> PCIE_ITX_GLANRX_P6_C
<24> PCIE_ITX_GLANRX_N6_C
4
U23
52
53
B
1 PCIE_IRX_GLANTX_N6_C
0.1U_0402_10V7K~D
E
2
C452
C
<24> PCIE_IRX_GLANTX_N6
C454
0.1U_0402_16V4Z~D
1 PCIE_IRX_GLANTX_P6_C
0.1U_0402_10V7K~D
C453
4.7U_0603_6.3V4Z~D
<24> PCIE_IRX_GLANTX_P6
2
C451
China TPM
B
1
@ R382
4.7K_0402_5%~D
GND_11
GND_18
GND_25
GND_4
11
18
25
4
NC_3
NC_5
NC_12
NC_13
NC_14
3
5
12
13
14
1
4@ 2
1
4@ 2
C_TPM_LPC_EN
4@ R383
100_0402_1%~D
1
A
2
1
4@ 1
2
4@
USH pin R6 LPCEN
R841
POP
@
POP
@
Pull-down on LPC_EN_R
USH pin R6 LPCEN
R483
@
POP
@
POP
@
5@ R464
@
POP
@
Series from EC to LPD#
EC to USH Pin P7 LPCPD_N
R466
@
@
@
@
Pull-up on LPD#
USH pin P7 LPCPD_N
R474
POP
POP
POP
POP
Pull-up on EC
SIO pin 105 OUT65
R788
@
@
@
@
Pull-down on China TPM
To China TPM U24 pin 28
4@ R892
@
@
POP
POP
POP
Series from EC to LPC_EN_R EC to USH Pin R6 LPCEN
4@ R892
4.7K_0402_5%~D
SSX35BCB_TSSOP28~D
ROUSH USH and China TPM BOM Option
Ref Des A0 USH B0 USH A0 w/CHINA B0 w/CHINA
PART/PIN
DESCRIPTION
Pull-up on LPC_EN_R
Series from EC to China PD# SIO to China Pin 28 LPCPD#
4@ R893
Broadcom USH
U32 USH
U32
China TPM
U24 China TPM
4@ U24
@
@
POP
POP
POP
POP
POP
@
@
POP
POP
LPCBus Series Resistors
R705,R723,R724,R732,R733
5@
POP
POP
@
@
TPM_ID(Strap Low)
ICH9M GPIO6 Pin AH21
4@ R922
@
@
POP
POP
TPM_ID (Strap High)
ICH9M GPIO6 Pin AH21
5@ R273
POP
POP
@
@
A
2
@ R884
4.7K_0402_5%~D
1
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
TESTBI/BADD
TESTI
2
2
TESTI
21
22
16
27
15
7
9
8
LPCPD#
LAD0
LAD1
LAD2
LAD3
10
19
24
1
<6> CLK_PCI_TPM_CHA
<23,36,37,38> LPC_LFRAME#
<22,31> PCI_RST#
<24,31,36,37,38> IRQ_SERIRQ
<24,31,37,38> CLKRUN#
2
28
26
23
20
17
VDD_0
VDD_1
VDD_2
C487
10U_0603_6.3V6M~D
4@ R893 0_0402_5%~D
C_TPM_LPC_EN
1
2
<23,36,37,38> LPC_LAD0
<23,36,37,38> LPC_LAD1
<23,36,37,38> LPC_LAD2
<23,36,37,38> LPC_LAD3
GPIO1
GPIO2
GPIO_EXPRESS_00
C486
0.1U_0402_16V4Z~D
2
4@ U24
1
2
6
C485
0.1U_0402_16V4Z~D
+3.3V_RUN
X02
build
+3.3V_RUN
C484
0.1U_0402_16V4Z~D
<36,37> SP_TPM_LPC_EN
R381
51K_0402_1%~D
1
B
4@ is for China TPM only
5@ is for Broadcom TPM only
Address select, no stuff for
4E4F and stuff for 2E2F.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
LAN-82567LM
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
29
of
71
5
4
3
2
1
D
D
+3.3V_LAN
LAN ANALOG
SWITCH
56
50
38
27
18
10
4
1
U25
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
1
2
C462
0.1U_0402_16V4Z~D
2
C461
0.1U_0402_16V4Z~D
1
C460
0.1U_0402_16V4Z~D
2
<29>
<29>
<29>
C
LAN_TX0+
LAN_TX0-
LAN_TX1+
<29>
LAN_TX1-
<29>
LAN_TX2+
<29>
LAN_TX2-
<29>
LAN_TX3+
<29>
LAN_TX3-
<29,37> DOCKED
LAN_TX0+ 1
LAN_TX0+R
2
L20
22NH_0603CS-220EJTS_5%_0603~D
LAN_TX0LAN_TX0-R
1
2
L21
22NH_0603CS-220EJTS_5%_0603~D
2
3
0B1
1B1
48
47
SW_LAN_TX0+
SW_LAN_TX0-
A1
2B1
3B1
43
42
SW_LAN_TX1+
SW_LAN_TX1-
A2
4B1
5B1
37
36
SW_LAN_TX2+
SW_LAN_TX2SW_LAN_TX3+
SW_LAN_TX3-
A0
SW_LAN_TX0+ <33>
SW_LAN_TX0- <33>
SW_LAN_TX1+ <33>
SW_LAN_TX1- <33>
SW_LAN_TX2+ <33>
SW_LAN_TX2- <33>
LAN_TX1+ 1
LAN_TX1+R
2
L22
22NH_0603CS-220EJTS_5%_0603~D
LAN_TX1LAN_TX1-R
1
2
L23
22NH_0603CS-220EJTS_5%_0603~D
7
8
A3
6B1
7B1
32
31
LAN_TX2+ 1
LAN_TX2+R
2
L24
22NH_0603CS-220EJTS_5%_0603~D
LAN_TX2LAN_TX2-R
1
2
L25
22NH_0603CS-220EJTS_5%_0603~D
11
A4
12
A5
0LED1
1LED1
2LED1
22
23
52
LAN_LEDACT#
LINK_LED10#
LINK_LED100#
LAN_TX3+ 1
LAN_TX3+R
2
L26
22NH_0603CS-220EJTS_5%_0603~D
LAN_TX3LAN_TX3-R
1
2
L27
22NH_0603CS-220EJTS_5%_0603~D
14
A6
0B2
1B2
46
45
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
15
A7
2B2
3B2
41
40
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
DOCKED
17
SEL
4B2
5B2
35
34
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
19
20
54
LED0
LED1
LED2
6B2
7B2
30
29
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
0LED2
1LED2
2LED2
25
26
51
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#
Layout Notice : Place bead as
close PI3L500 as possible
<29> LOM_ACTLED_YEL#
<29> LOM_SPD10LED_GRN#
<29> LOM_SPD100LED_ORG#
5
NC
C
DOCK_LOM_TRD0+ <35>
DOCK_LOM_TRD0- <35>
DOCK_LOM_TRD1+ <35>
DOCK_LOM_TRD1- <35>
DOCK_LOM_TRD2+ <35>
DOCK_LOM_TRD2- <35>
DOCK_LOM_TRD3+ <35>
DOCK_LOM_TRD3- <35>
DOCK_LOM_ACTLED_YEL# <35>
DOCK_LOM_SPD10LED_GRN# <35>
DOCK_LOM_SPD100LED_ORG# <35>
PAD_GND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
57
SW_LAN_TX3+ <33>
SW_LAN_TX3- <33>
PI3L500-AZFEX_TQFN56~D
FROM NIC
DOCKED
TO
DOCK
1
6
9
13
16
21
24
28
33
39
44
49
53
55
1: TO DOCK
0: TO RJ45
+3.3V_LAN
1
@
2
2
2
@
R394
10K_0402_5%~D
@
R393
10K_0402_5%~D
R392
10K_0402_5%~D
1
B
1
B
LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
LAN_LEDACT#
LINK_LED10#
LINK_LED100#
1
R395
1
R396
1
R397
LAN_ACTLED_YEL_R#
2
150_0402_5%~D
LED_10_GRN_R#
2
110_0402_5%~D
LED_100_ORG_R#
2
200_0402_5%~D
LAN_ACTLED_YEL_R# <33>
LED_10_GRN_R# <33>
LED_100_ORG_R# <33>
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
LAN TRANSFOMER
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
30
of
71
5
4
3
2
1
U26A
2
SDCD#/MMCCD#
MDIO1
T165 PAD~D@
MDIO2
T166 PAD~D@
SDWP#
CARD_PWR
MDIO5
T167PAD~D@
MDIO6
T168PAD~D@
MDIO07
2
1
SDCMD/MMCCMD R414
0_0402_5%~D
SDCLK/MMCCLK
1
2 SDCLK/MMC_CLK_R
SDDAT0/MMCDAT0 R416
0_0402_5%~D
SDDAT1/MMCDAT1
close to
SDDAT2/MMCDAT2
SDDAT3/MMCDAT3
MMCDAT4
MMCDAT5
MMCDAT6
For MMC PLUS
MMCDAT7
MDIO18
T170PAD~D
MDIO19
T171PAD~D@
@
2
2
2
2
1
CBS_CCLK
<32>
CBS_CRST#
<32>
@ R1117
10M_0402_5%~D
2
R5C847XO
1
0_0402_5%~D
1
2
1
2
1@
VCC5IN
VCC5IN
VPPEN0
VPPEN1
3
4
EN0
EN1
VCC3EN#
VCC5EN#
2
1
VCC3_EN
VCC5_EN
2
2 100K_0402_5%~D
100K_0402_5%~D
VCCOUT
VCCOUT
VCCOUT
9
14
12
VPPOUT
8
1
2
+CBS_VPP
1
2
FLG
GND
NC
NC
NC
7
6
10
1@ 2
1
1@ 1
2
@
C
@
+3.3V_RUN
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
270P_0402_50V7K~D
270P_0402_50V7K~D
+3.3V_RUN_CARD
U28
5
CARD_PWR
4
1
2
IN
EN#
OUT
GND
OC#
1
2
3
TPS2051BDBVR_SOT23-5~D
2
1
1
2
Close to JP5 pin5
2
1
1
1
1
1
1
1
1
1
1
B
Close to JP5 pin5
JSD1
+3.3V_RUN_CARD
2
1
2
SDDAT0/MMCDAT0
SDDAT1/MMCDAT1
SDDAT2/MMCDAT2
14
12
10
9
8
6
4
3
15
DAT3/SD1
CMD/SD2
VSS1/SD3
VCC/SD4
CLK/SD5
GND/VSSS2/SD6
DAT7/SD7
DAT1/SD8
DAT2/SD9
MMCDAT4
MMCDAT5
MMCDAT6
MMCDAT7
13
11
7
5
DAT4/MMC10
DAT5/MMC11
DAT6/MMC12
DAT7/MMC13
16
17
CD_WP_SW/GRD
CD_WP_SW/GRD
19
20
2
1
CD_SW/SD
WP_SW/SD
CD_SW_TAISOL/SD
WP/SW_TAISOL/SD
SDCLK/MMC_CLK_R
SDCD#/MMCCD#
SDWP#
SDCD#/MMCCD#
SDWP#
18
Place close
to JSD1.9
GND_SW
A
FOX_2WX131A1-31DD-7F
Close to Pin A16,B16
only for MMC/SD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
13
15
+5V_RUN
1@
SDDAT3/MMCDAT3
SDCMD/MMCCMD
R5C847
1
1
2
1
1
2
1
PCI_CBS_TERM 2
2
R421
VCC3IN
1
1
R411 1
@ R412
SDDAT0/MMCDAT0
2
SDDAT1/MMCDAT1
C502 2
SDDAT2/MMCDAT2
C503 2
SDDAT3/MMCDAT3
C504 2
MMCDAT4
C507 2
MMCDAT5
C508 2
MMCDAT6
C510 2
MMCDAT7
C511 2
CBS_CCD1#
C512 2
CBS_CCD2#
C1036 2
C1037
C767
0.1U_0402_16V4Z~D
@
C516
1U_0603_10V4Z~D
1
2
1
C515
22P_0402_50V8J~D
+CBS_VCC
1@ U27
11
R5531V002-E2-FA_SSOP16~D
VPPEN0
SDCLK/MMCCLK
R5C847XI
X3
24.576MHz_16P_1BG24576CKIA~D
Close to U26
5
16
CBS_DATA14 <32>
CBS_DATA2 <32>
CBS_DATA18 <32>
CBUS_GRST#
C517
4.7P_0402_50V8C~D
2
R418
10_0402_5%~D
A
R420
100K_0402_5%~D
@
R407
5.1K_0402_1%~D
1
1
2
+3.3V_RUN_CARD
+3.3V_RUN
MOLEX_53780-0670~D
1
2
@ C501
0.01U_0402_16V7K~D
<32>
<32>
<32>
<32>
@ C622
0.01U_0402_16V7K~D
CLK_PCI_PCM
1
1
1
2
1
FIL0
2
1
C514
27P_0402_50V8J~D
D
Z3008
+3.3V_RUN
R5C847-CSP208Q_CSP208~D
1
2
1
16 bit PC card I/F
B1
A2
A3
B3
B4
A5
B5
D5
A6
B6
D6
E6
A7
B7
D7
E7
A8
B8
D8
E8
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
GND
GND
R413
150K_0402_5%~D
1
CBS_DATA14
CBS_DATA2
CBS_DATA18
VPPEN0
VPPEN1
VCC5EN#
VCC3EN#
7
8
C497
10U_0805_10V4Z~D
W18
C19
N16
V13
W13
R13
T13
CBS_CCD1#
CBS_CCD2#
CBS_CVS1
CBS_CVS2
1
2
3
4
5
6
C506
1U_0603_10V4Z~D
TEST1
TEST2
CDATA14
CDATA2
CADR18
VPPEN0
VPPEN1
VCC5EN#
VCC3EN#
CBS_CAUDIO <32>
<24> 1394_DET#
1
2
3
4
5
6
C496
0.1U_0402_16V4Z~D
F4
R7
CBS_CCD1#
CBS_CCD2#
CBS_CVS1
CBS_CVS2
J1394
R401
56.2_0402_1%~D
2
C494
270P_0402_50V7K~D
2
1@ R410
22_0402_5%~D
<32>
2
C505
0.01U_0402_16V7K~D
1@ R803
0_0402_5%~D
T14
D15
R16
H16
CBS_CINT#
1
C500
0.01U_0402_16V7K~D
USBDM
USBDP
CD1#/CCD1#
CD2#/CCD2#
VS1#/CVS1
VS2#/CVS2
CBS_CC/BE3# <32>
CBS_CC/BE2# <32>
CBS_CC/BE1# <32>
CBS_CC/BE0# <32>
CBS_CPAR <32>
CBS_CFRAME# <32>
CBS_CTRDY# <32>
CBS_CIRDY# <32>
CBS_CSTOP# <32>
CBS_CDEVSEL# <32>
CBS_CBLOCK# <32>
CBS_CPERR# <32>
CBS_CSERR# <32>
CBS_CREQ# <32>
CBS_CGNT# <32>
CBS_CSTSCHNG <32>
CBS_CCLKRUN# <32>
2
C499
0.1U_0402_16V4Z~D
W14
V14
CBS_CC/BE3#
CBS_CC/BE2#
CBS_CC/BE1#
CBS_CC/BE0#
CBS_CPAR
CBS_CFRAME#
CBS_CTRDY#
C BS_CIRDY#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CBLOCK#
CBS_CPERR#
CBS_CSERR#
CBS_CREQ#
CBS_CGNT#
CBS_CSTSCHNG
CBS_CCLKRUN#
CBS_CCLK_R
CBS_CINT#
CBS_CRST#
CBS_CAUDIO
1
C509
0.1U_0402_16V4Z~D
2@ R671
0_0402_5%~D
2
1
2
1
2@ R739
0_0402_5%~D
USBP7-_R1
USBP7+_R1
TPAP0
TPAN0
TPBP0
TPBN0
TPBIAS0
CPS
VREF
REXT
XI
XO
FIL0
F16
K18
P15
V19
N15
K16
L16
K15
M16
L18
N19
N18
G16
G19
M15
E18
A18
L19
M18
H19
F19
R403
56.2_0402_1%~D
C491
10P_0402_50V8J~D
<32> USBP7-_EXP
<32> USBP7+_EXP
USBP7USBP7+
PAD~DT169
R802
1@ 0_0402_5%~D
2
1
2
1
B12
A12
B13
A13
D12
D11
D13
B14
A16
B16
A14
INTA#
INTB#
INTC#
UDIO0/SRIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
RI_OUT#/PME#
SPKROUT#
USB TEST
R417
10K_0402_1%~D
C513
0.01U_0402_16V7K~D
<24>
<24>
GBRST#
PCIRST#
PCICLK
CLKRUN#
HWSPND#
1394 I/F
TPAP0
TPAN0
TPBP0
TPBN0
TPBIAS0
CPS
CBVREF
CBREXT
R5C847XI
R5C847XO
FIL0
B
1
G2
L4
K1
L5
F2
CBS_CAD13/USBP7+
REG#/CCBE3#
CADR12/CCBE2#
CADR8/CCBE1#
CE1#/CCBE0#
CADR13/CPAR
CADR23/CFRAME#
CADR22/CTRDY#
CADR15/CIRDY#
CADR20/CSTOP#
CADR21/CDEVSEL#
CADR19
CADR14/CPERR#
WAIT#/CSERR#
INPACK#/CREQ#
WE#/CGNT#
BVD1/CSTSCHG
WP/CCLKRUN#
CADR16/CCLK
READY/CINT#
RESET/CRST#
BVD2/CAUDIO
INT &
AUDIO
PAD~DT163
@ PAD~DT164
@
@
REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
J2
K4
K2
J4
UDIO1
H1
UDIO2
H2
UDIO3
H4
UDIO4
H5
UDIO5
G1
RI_OUT#/PME# G4
CBS_SPK
F1
<22> PCI_PIRQD#
<22> PCI_PIRQB#
<22> PCI_PIRQC#
<24,29,36,37,38> IRQ_SERIRQ
PAD~DT161
@ PAD~DT162
@
2
M4
M5
V3
V4
W4
T5
V5
W5
T6
RST&
CLK
CBUS_GRST#
PCI_RST#
CLK_PCI_PCM
CLKRUN#
CB_HWSPND#
<22,29> PCI_RST#
<6> CLK_PCI_PCM
<24,29,37,38> CLKRUN#
<37> CB_HWSPND#
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IDSEL
CBS_CAD15/USB7-
TPAP0
TPAN0
TPBP0
TPBN0
C498
1U_0402_6.3V6K~D
C
V6
T9
W6
W2
P2
P1
CBS_CAD31 <32>
CBS_CAD30 <32>
CBS_CAD29 <32>
CBS_CAD28 <32>
CBS_CAD27 <32>
CBS_CAD26 <32>
CBS_CAD25 <32>
CBS_CAD24 <32>
CBS_CAD23 <32>
CBS_CAD22 <32>
CBS_CAD21 <32>
CBS_CAD20 <32>
CBS_CAD19 <32>
CBS_CAD18 <32>
CBS_CAD17 <32>
CBS_CAD16 <32>
CBS_CAD15/USBP7- <32>
CBS_CAD14 <32>
CBS_CAD13/USBP7+ <32>
CBS_CAD12 <32>
CBS_CAD11 <32>
CBS_CAD10 <32>
CBS_CAD9 <32>
CBS_CAD8 <32>
CBS_CAD7 <32>
CBS_CAD6 <32>
CBS_CAD5 <32>
CBS_CAD4 <32>
CBS_CAD3 <32>
CBS_CAD2 <32>
CBS_CAD1 <32>
CBS_CAD0 <32>
C495
1U_0402_6.3V6K~D
PCI_AD17
PCI_PAR
<22> PCI_PAR
PCI_C_BE0#
<22> PCI_C_BE0#
PCI_C_BE1#
<22> PCI_C_BE1#
PCI_C_BE2#
<22> PCI_C_BE2#
PCI_C_BE3#
<22> PCI_C_BE3#
CBS_IDSEL
1
2
R409
100_0402_5%~D
PCI_REQ1#
<22> PCI_REQ1#
PCI_GNT1#
<22> PCI_GNT1#
PCI_FRAME#
<22> PCI_FRAME#
PCI _IRDY#
<22> PCI_IRDY#
PCI_TRDY#
<22> PCI_TRDY#
PCI_DEVSEL#
<22> PCI_DEVSEL#
PCI_STOP#
<22> PCI_STOP#
PCI_PERR#
<22> PCI_PERR#
PCI_SERR#
<22> PCI_SERR#
Media Card I/F
CPS
2
0_0402_5%~D
UDIO4
2
10K_0402_5%~D
CBS_SPK
2
100K_0402_5%~D
1
R404
1
R406
1
@ R1037
TPBIAS0
B19
C18
D19
D18
E19
E16
F18
F15
G18
G15
H18
H15
J18
J16
J15
P16
P19
R19
P18
R18
T19
T18
U19
U18
W17
V17
W16
V16
W15
V15
T15
R14
C493
0.33U_0603_10V7K~D
+3.3V_RUN_PHY
CDATA10/CAD31
CDATA9/CAD30
CDATA1/CAD29
CDATA8/CAD28
CDATA0/CAD27
CADR0/CAD26
CADR1/CAD25
CADR2/CAD24
CADR3/CAD23
CADR4/CAD22
CADR5/CAD21
CADR6/CAD20
CADR25/CAD19
CADR7/CAD18
CADR24/CAD17
CADR17/CAD16
IOWR#/CAD15
CADR9/CAD14
IORD#/CAD13
CADR11/CAD12
OE#/CAD11
CE2#/CAD10
CADR10/CAD9
CDATA15/CAD8
CDATA7/CAD7
CDATA13/CAD6
CDATA6/CAD5
CDATA12/CAD4
CDATA5/CAD3
CDATA11/CAD2
CDATA4/CAD1
CDATA3/CAD0
R399
56.2_0402_1%~D
CB_HWSPND#
2
10K_0402_5%~D
CBS_SPK
2
100K_0402_5%~D
UDIO3
2
10K_0402_5%~D
1
R400
1
R402
1
R405
D
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
R398
56.2_0402_1%~D
+3.3V_RUN
W12
V12
T12
W11
V11
T11
W9
V9
R9
W8
V8
T8
R8
W7
V7
T7
V1
U1
U2
T1
T2
R1
R2
R4
P4
P5
N1
N2
N4
N5
M1
M2
PCI I/F
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
C492
0.01U_0402_16V7K~D
R5C847-CSP208Q
<22> PCI_AD[0..31]
4
3
Title
CardBus Controller(R5C847)
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
31
of
71
5
4
3
2
1
+3.3V_RUN
C528
1000P_0402_50V7K~D
C527
1000P_0402_50V7K~D
2
+1.5V_CARD
D
+1.5V_RUN
DIGITAL
GND
3.3Vout
3.3Vout
2
100K_0402_5%~D
2
0_0402_5%~D
2
100K_0402_5%~D
2
100K_0402_5%~D
6
AUX_OUT
SYSRST#
OC#
20
SHDN#
PERST#
EXPRCRD_STBY_R#
1
STBY#
NC
EXPRCRD_PWREN#
10
CPPE#
GND
CPUSB#
9
18
<37> EXPRCRD_PWREN#
CBS_CTRDY# 1
@ R800
AUX_IN
1
3
5
2
15
+3.3V_CARDAUX
19
8
1
16
2
7
CPUSB#
1
2
2@ 1
2
2@ 1
2
2@
RCLKEN
CARD_RESET#
R5538_QFN20~D
2
0_0402_5%~D
2
2@ C1016
10U_0805_6.3V6M~D
ANALOG
GND
3.3Vin
3.3Vin
2
C1003
10U_0805_6.3V6M~D
2
4
11
13
C1002
0.1U_0402_16V4Z~D
1.5Vout
1.5Vout
+3.3V_CARD
C1001
0.1U_0402_16V4Z~D
1.5Vin
1.5Vin
1
2@ C1012
10U_0805_6.3V6M~D
1
@ R657
1
2@ R683
1
@ R684
1
@ R790
<37> EXPRCRD_STDBY#
PLTRST1#
<10,22,50> PLTRST1#
2
2@ U52
12
14
1
2@ C1006
0.1U_0402_16V4Z~D
+3.3V_SUS
A10
A11
B10
B11
C1
D1
E12
NC
NC
NC
NC
NC
NC
NC
NC
2
2@ C1000
0.1U_0402_16V4Z~D
NC
NC
NC
NC
NC
NC
NC
2
2@
1
17
A9
B9
D9
D14
A15
B15
AGND
AGND
AGND
AGND
AGND
AGND
1
2@
2@ C999
0.1U_0402_16V4Z~D
D10
E1
C2
D2
E2
L2
E4
C
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
2
2@
C997
0.1U_0402_16V4Z~D
E10
E11
A17
B17
1
J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C135
0.1U_0402_16V4Z~D
+3.3V_RUN_PHY
VCC_3V
VCC_3V
VCC_3V
VCC_3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_RIN
VCC_RIN
VCC_ROUT
VCC_ROUT
VCC_MD3V
C134
0.1U_0402_16V4Z~D
R5C847-CSP208Q
F5
G5
J19
K19
W3
R11
R12
R6
E13
L1
E14
A4
ANALOG
POWER
2
2
1
1
DIGITAL
POWER
2
1
2
1
+3.3V_SUS +3.3V_RUN
C540
0.01U_0402_16V7K~D
2
1
C539
0.47U_0402_16V4Z~D
2
1
C538
0.01U_0402_16V7K~D
2
1
C537
0.47U_0402_16V4Z~D
2
1
C536
0.1U_0402_10V7K~D
1
C535
0.01U_0402_16V7K~D
2
C534
0.01U_0402_16V7K~D
C533
10U_0805_10V4Z~D
2
1
2
1
U26B
+3.3V_RUN
1
1
C526
0.1U_0402_16V4Z~D
2
+3.3V_RUN_PHY
C525
0.1U_0402_16V4Z~D
2
1
C524
10U_0805_10V4Z~D
1
2
C776
0.01U_0402_16V7K~D
2
2
1
C530
0.01U_0402_16V7K~D
1
1
C523
0.01U_0402_16V7K~D
2
2
C529
0.01U_0402_16V7K~D
2
1
C532
0.01U_0402_16V7K~D
1
C531
10U_0805_10V4Z~D
+3.3V_RUN
2
1
C522
0.01U_0402_16V7K~D
2
D
1
C521
0.01U_0402_16V7K~D
1
C520
0.01U_0402_16V7K~D
2
C519
10U_0805_10V4Z~D
1
+3.3V_RUN L28
BLM21A601SPT_0805~D
1
2
C
1
@ R799
2 CBS_DATA2
0_0402_5%~D
R5C847-CSP208Q_CSP208~D
Express Card
+1.5V_CARD: Max. 650mA, Average 500mA
+3.3V_CARD: Max. 1300mA, Average 1000mA
JCBUS1
<31> USBP7-_EXP
Close to JCBUS1 Pin18/52
2
2
1
+3.3V_SUS
6
1
2@
1
2
2@
PCIE_WAKE#
CARD_RESET#
+3.3V_CARD
2@
<6> EXPCLK_REQ#
1
2
EXP_SMBDATA
2@
EXPRCRD_PWREN#
<6> CLK_PCIE_EXP#
<6> CLK_PCIE_EXP
<24> PCIE_IRX_EXPTX_N4
<24> PCIE_IRX_EXPTX_P4
<24> PCIE_ITX_EXPRX_N4_C
<24> PCIE_ITX_EXPRX_P4_C
2@ Q112A
2N7002DW-T/R7_SOT363-6
5
<34,38> CARD_SMBCLK
3
4
2@
JEXP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND1
USB_DUSB_D+
CPUSB#
RESERVED
RESERVED
SMB_CLK
SMB_DAT
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PER_N0
PER_P0
GND
PET_N0
PET_P0
GND
27
28
29
30
GND
GND
GND
GND
B
MOLEX_48326-0001_RT
2@ Q112B
2N7002DW-T/R7_SOT363-6
A
EXP_SMBCLK
1
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
4
CPUSB#
2@
1@
Close to JCBUS1 pin23,63
5
USBP7_D+
2
<34,37> PCIE_WAKE#
+3.3V_CARDAUX
2
2
1@
1
1
2
USBP7_D-
+3.3V_SUS
C543
10U_0805_10V4Z~D
1
C542
0.01U_0402_16V7K~D
C541
0.01U_0402_16V7K~D
2
1@
2
0_0402_5%~D
3 3
EXP_SMBCLK
EXP_SMBDATA
+CBS_VCC
C769
0.1U_0402_10V7K~D
1
1
@ R792
4 4
1
2@ L64
DLW21SN900SQ2_0805~D
<34,38> CARD_SMBDAT
+CBS_VPP
A
2
0_0402_5%~D
1
<31> USBP7+_EXP
2
MOLEX_48315-0013_RT
1@
1
R791
@
1
71
72
CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19
CBS_CVS2
CBS_CRST#
CBS_CSERR#
CBS_CREQ#
CBS_CC/BE3#
CBS_CAUDIO
CBS_CSTSCHNG
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CCD2#
+1.5V_CARD
C1005
0.1U_0402_16V4Z~D
GND7
GND8
CBS_CCD1# <31>
CBS_CAD2 <31>
CBS_CAD4 <31>
CBS_CAD6 <31>
CBS_DATA14 <31>
CBS_CAD8 <31>
CBS_CAD10 <31>
CBS_CVS1
<31>
CBS_CAD13/USBP7+ <31>
CBS_CAD15/USBP7- <31>
CBS_CAD16 <31>
CBS_DATA18 <31>
CBS_CBLOCK# <31>
CBS_CSTOP# <31>
CBS_CDEVSEL# <31>
+CBS_VCC
+CBS_VPP
CBS_CTRDY# <31>
CBS_CFRAME# <31>
CBS_CAD17 <31>
CBS_CAD19 <31>
CBS_CVS2
<31>
CBS_CRST# <31>
CBS_CSERR# <31>
CBS_CREQ# <31>
CBS_CC/BE3# <31>
CBS_CAUDIO <31>
CBS_CSTSCHNG <31>
CBS_CAD28 <31>
CBS_CAD30 <31>
CBS_CAD31 <31>
CBS_CCD2# <31>
R127
2.2K_0402_5%~D
GND5
GND6
CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_DATA14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13/USBP7+
CBS_CAD15/USBP7CBS_CAD16
CBS_DATA18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#
R126
2.2K_0402_5%~D
69
70
GND3
CCD1#
CAD2
CAD4
CAD6
CB_D14
CAD8
CAD10
CVS1
CAD13
CAD15
CAD16
CB_D18
CBLOCK#
CSTOP#
CDEVSEL#
VCC
VPP2
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CCBE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
GND4
C1004
0.1U_0402_16V4Z~D
CBS_CCLK
C BS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_DATA2
CBS_CCLKRUN#
GND1
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
VCC
VPP1
CCLK
CIRDY#
CCBE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
CB_D2
CCLKRUN#
GND2
2
CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
C1007
0.1U_0402_16V4Z~D
B
<31> CBS_CAD0
<31> CBS_CAD1
<31> CBS_CAD3
<31> CBS_CAD5
<31> CBS_CAD7
<31> CBS_CC/BE0#
<31> CBS_CAD9
<31> CBS_CAD11
<31> CBS_CAD12
<31> CBS_CAD14
<31> CBS_CC/BE1#
<31> CBS_CPAR
<31> CBS_CPERR#
<31> CBS_CGNT#
<31> CBS_CINT#
+CBS_VCC
+CBS_VPP
<31> CBS_CCLK
<31> CBS_CIRDY#
<31> CBS_CC/BE2#
<31> CBS_CAD18
<31> CBS_CAD20
<31> CBS_CAD21
<31> CBS_CAD22
<31> CBS_CAD23
<31> CBS_CAD24
<31> CBS_CAD25
<31> CBS_CAD26
<31> CBS_CAD27
<31> CBS_CAD29
<31> CBS_DATA2
<31> CBS_CCLKRUN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
3
Title
CardBus/SD card Socket
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
32
of
71
5
4
3
2
1
+5V_ESATA
2
2
JESA1
TPS2062ADR_SO8~D
USBP3_DUSBP3_D+
1
2
3
4
USBP2_D-_SW
USBP2_D+_SW
5
6
7
8
+5V_CHGUSB
+
USB_OC2#
8
7
6
5
USB_OC2#
<24>
2
TPS2062ADR_SO8~D
1
2
1
C1042
2
@ R928
2
<38> EN_CELL_CHARGER_DET#
<37> CELL_CHARGER_DET#
SATA_ITX_DRX_P4_C
SATA_ITX_DRX_N4_C
SATA_IRX_DTX_N4_C 2
C549
SATA_IRX_DTX_P4_C 2
C550
2
1U_0402_6.3V6K~D
1
0_0402_5%~D
1
D69
RB751S40T1_SOD523-2~D
1SATA_IRX_DTX_N4
4700P_0402_25V7K~D
1SATA_IRX_DTX_P4
4700P_0402_25V7K~D
R1040
100K_0402_5%~D
1
2
+3.3V_ALW2
+1.8V_RUN
9
10
11
12
13
14
15
GND
A+
ESATA
AGND
BB+
GND
16
17
DET1
DET2
18
19
20
21
G1
G2
G3
G4
1.2x
1
-3.5dB
4
4
1
R424
USBP3+
USBP3USBP3+
4
4
3
3
1
R427
2
0_0402_5%~D
1
1
@ R1050
@ R1051
1
1
2 0_0402_5%~D
2 0_0402_5%~D
33
14
SEL1_A
SEL1_B
R1052
R1053
1
1
2 0_0402_5%~D
2 0_0402_5%~D
32
15
SEL2_A
SEL2_B
R1054
R1055
1
1
2 0_0402_5%~D
2 0_0402_5%~D
31
16
SEL3_A
SEL3_B
USBP3_D+1.8V_RUN
USBP3_D+
R306
R307
1
1
2 5.1K_0402_1%~D
2 5.1K_0402_1%~D
30
29
@ R305
1
2 470_0402_5%~D
19
R1056
R1057
2 0_0402_5%~D
2 0_0402_5%~D
1
1
11
12
<30> SW_LAN_TX1+
<30> SW_LAN_TX1<30> SW_LAN_TX0<30> SW_LAN_TX0+
+3.3V_LAN
<24>
<24>
USBP0+
USBP0-
<24>
<24>
USBP1+
USBP1-
1
2
A
+3.3V_LAN
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AO+
AO-
27
26
SATA_ITX_DRX_P4
SATA_ITX_DRX_N4
BIBI+
21
22
SATA_IRX_DTX_N4_C
SATA_IRX_DTX_P4_C
OUT+
OUT-
17
18
@ R1066 1
@ R1067 1
2 0_0402_5%~D
2 0_0402_5%~D
SD_A
SD_B
36
35
@ R1069 1
@ R1070 1
2 0_0402_5%~D
2 0_0402_5%~D
GND
GND
GND
GND
AGND
25
20
9
4
24
PAD
37
SEL0_A
SEL0_B
EN_A
EN_B
IREF
ICH_AZ_MDC_RST1#
CLKIN+
CLKIN-
4
WLAN
5
WWAN
6
WPAN
7
Card Bus/Express card
8
DOCKING
9
DOCKING
10
USH->BIO
11
Camera
<36>
FP_USBD+
1
<36>
FP_USBD-
4
4
*
= 2.5V when undocked.
<28>
<28>
Compliance Channel
0
0
no equalization
0
1
[0:2.5dB] @ 1.6 GHz
1
1
0
[2.5:4.5dB] @ 1.6 GHz
1
[4.5:6.5dB] @ 1.6 GHz
1
2
3
4
5
6
GND
GND
7
8
+3.3V_RUN
FP_USB_DFP_USB_D+
Place close
to JIO1.13
Place close
to JIO1.30
5
2
Place close
to JIO1.35
2
<36>
2
1
2
@
B
+3.3V_RUN Place close to
JBIO1.1
TYCO_1734242-6
<24>
USBP2+
USBP2-
R1082
1
2 0_0402_5%~D
USBP2+
R1083
1
2 0_0402_5%~D
FP_USB_D-
2
1
USBP3_D+
1
GND IO2
3
2
IO1
4
@ U54
8 VCC
1
2
NC
7
6
HSD-
D-
5
USBP2_D-
2
HSD+
D+
3
USBP2_D+
1
OE#
GND
4
1
@ R324
1
<23> ICH_AZ_MDC_RST#
TS3USB31RSER_QFN8_1P5X1P5~D
+5V_ALW
GND IO2
3
IO1
4
VIN
USBP2_D-_SW
Place Switch as close to
ICH9M as possible
+5V_CHGUSB
2
GND IO2
3
IO1
4
VIN
VIN
FP_USB_D+
+3.3V_RUN
PRTR5V0U2X_SOT143-4~D
@ U55
+LOM_VCT
1
1
FP_RESET#
+5V_RUN
1
2
@ R873
0_0402_5%~D
@ U30
C712
0.1U_0402_16V4Z~D
2
1
+5V_RUN Place close to
JBIO1.6
Fingerprint CONN.
+3.3V_RUN+5V_RUN
1
2
3
4
5
6
+3.3V_SUS
1
C711
0.1U_0402_16V4Z~D
1
FP_USB_D-
3
3
U51
USBP2-
ICH_AZ_MDC_SDOUT <23>
ICH_AZ_MDC_SYNC <23>
ICH_AZ_MDC_SDIN1 <23>
AUD_HP_NB_SENSE <27,28,37>
+3.3V_SUS
FP_USB_D+
2
0_0402_5%~D
2
0_0402_5%~D
PRTR5V0U2X_SOT143-4~D
+VREFOUT
D
C
@ L29
DLW21SN121SQ2L_4P~D
1
2 2
1
R422
1
R423
SEL0_ [A:B] SEL1_ [A:B]
<24>
ICH_AZ_MDC_BITCLK <23>
HP_SPK_L1
HP_SPK_R1
C488
4700P_0402_25V7K~D
2
1 SATA_ITX_DRX_N4_C
Equalizer Selection
AUD_EXT_MIC_L <27>
AUD_EXT_MIC_R <27>
+VREFOUT
AUD_MIC_SWITCH <27>
LAN_ACTLED_YEL_R# <30>
LED_10_GRN_R# <30>
LED_100_ORG_R# <30>
+3.3V_SUS
+LOM_VCT
+LOM_VCT
USB_SIDE_EN# <37>
USB_OC0_1# <24>
2
JESA1 (Ext Left Side Bottom)
JBIO1
DETECT_GND
USBP2_D+_SW
C634
0.1U_0402_16V4Z~D
2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TYCO_1759898-1
C768
0.1U_0402_16V4Z~D
1
C623
0.1U_0402_16V4Z~D
<24>
+5V_ALW
IO_LOOP
1
6
10
23
28
5
C1045
0.1U_0402_16V4Z~D
<30> SW_LAN_TX2<30> SW_LAN_TX2+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BO+
BO-
2
C1052
4700P_0402_25V7K~D
2
1 SATA_ITX_DRX_P4_C
VDD
VDD
VDD
VDD
VDD
AVDD
PI2EQX3201BZFE_TQFN36_6X5~D
JIO1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
<30> SW_LAN_TX3+
<30> SW_LAN_TX3-
AI+
AI-
+1.8V_RUN
Left side USB Port
B
1
C1062
1
C1063
2
1
3
C1035
0.1U_0402_16V4Z~D
2
0_0402_5%~D
2
1
JESA1 (Ext Left Side Top)
C770
0.1U_0402_16V4Z~D
1
R426
2
1
2
2
<24>
USBP3-
2
0_0402_5%~D
@ L31
DLW21SN121SQ2L_4P~D
1 1
2 2
R1047
R1049
2
3
2IRX_DTX_P4
0.01U_0402_16V7K~D 7
8
2IRX_DTX_N4
0.01U_0402_16V7K~D
34
2 0_0402_5%~D
0_0402_5%~D
13
2
<23> ESATA_ITX_DRX_P4
<23> ESATA_ITX_DRX_N4
<23> ESATA_IRX_DTX_P4_C
<23> ESATA_IRX_DTX_N4_C
2
0_0402_5%~D
1
R425
<24>
USBP2_D-_SW
3
3
2
1
U72
1
USBP2_D-
USBP2_D+_SW
2
USBP2_D+
*
1
C1057
0.1U_0402_16V4Z~D
1
1
C1056
0.1U_0402_16V4Z~D
0dB
C1055
0.1U_0402_16V4Z~D
0
C489
0.1U_0402_16V4Z~D
SEL3_ [A:B]
1x
C490
0.1U_0402_16V4Z~D
Swing
0
R1058
470_0402_5%~D
@ L30
DLW21SN121SQ2L_4P~D
1 1
2 2
De-emphasis
SEL2_ [A:B]
*
C
Output De-emphasis Adjustment
C1054
10U_1206_16V4Z~D
TYCO_1759562-1
Output Swing Control
JUSB1 (Ext Right Side Bottom)
USBP3_D-
2
0_0402_5%~D
ICH_AZ_MDC_RST1#
3
Q35
2N7002W-7-F_SOT323-3~D
1
<37> USB_POWERSHARE_PWR_EN#
OC1#
OUT1
OUT2
OC2#
1
2
+5V_ALW_FUSE
GND
IN
EN1#
EN2#
B_VCC
B_DB_D+
B_GND
USB
JUSB1 (Ext Right Side Top)
R325
100K_0402_5%~D
1
2
3
4
C548
0.1U_0402_16V4Z~D
1
+5V_CHGUSB
U53
A_VCC
A_DA_D+
A_GND
0
S
OC1#
OUT1
OUT2
OC2#
1
D
GND
IN
EN1#
EN2#
ESATA_USB_OC# <24>
2
G
+5V_ALW_FUSE
<37> ESATA_USB_PWR_EN#
ESATA_USB_OC#
8
7
6
5
1
1
2
3
4
C588
150U_D_6.3VM_R15M~D
2
+
U29
DESTINATION
R326
10K_0402_5%~D
1
C547
10U_1206_16V4Z~D
2
C546
0.1U_0402_16V4Z~D
1
D
PJP4
PAD-OPEN 4x4m
2
1
C545
0.1U_0402_16V4Z~D
1
+5V_ESATA
+5V_ALW
USB PORT#
C544
150U_D_6.3VM_R15M~D
@ FUSE1
L0603
1
2
A
<37> MDC_RST_DIS#
+5V_ESATA
DELL CONFIDENTIAL/PROPRIETARY
PRTR5V0U2X_SOT143-4~D
Compal Electronics, Inc.
Place ESD diodes as close as USB connector
Title
Place close
to JIO1.36
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
3
USB 2.0 PORT
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
33
of
71
5
4
3
2
1
+3.3V_WLAN
R437
100K_0402_5%~D
MINI1CLK_REQ#
<6> MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
<6> CLK_PCIE_MINI1#
<6> CLK_PCIE_MINI1
PCIE_IRX_WANTX_N1
PCIE_IRX_WANTX_P1
<24> PCIE_IRX_WANTX_N1
<24> PCIE_IRX_WANTX_P1
PCIE_ITX_WANRX_N1_C
PCIE_ITX_WANRX_P1_C
<24> PCIE_ITX_WANRX_N1_C
<24> PCIE_ITX_WANRX_P1_C
PCIE_MCARD2_DET#
<22> PCIE_MCARD2_DET#
C
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
USBP5_DUSBP5_D+
USB_MCARD2_DET#
LED_WWAN_OUT#
1
1
USB_MCARD2_DET# <24>
LED_WWAN_OUT# <42>
For WIMAX LED debug
@ C552
33P_0402_50V8J~D
2
+1.5V_RUN
2
1
2
1
2
1
@
2
1
2
2
5
2
1
2
+
2
UIM_VPP
UIM_DATA
UIM_CLK
2
3
1
2
SRV05-4.TCT_SOT23-6~D
2
1
2
COEX2_WLAN_ACTIVE R454 1
COEX1_BT_ACTIVE
R455 1
<6> MINI3CLK_REQ#
1
R458
1
R266
+1.5V_RUN
HOST_DEBUG_RX
MSCLK
PCIE_IRX_MCARDTX_N3
PCIE_IRX_MCARDTX_P3
PCIE_ITX_MCARDRX_N3_C
PCIE_ITX_MCARDRX_P3_C
PCIE_MCARD3_DET#
+-5%
500
375
2
1
2
1
2
C585
4.7U_0603_6.3V4Z~D
+1.5V
2
1
C584
0.1U_0402_16V4Z~D
250
2
1
C583
0.1U_0402_16V4Z~D
330
2
1
C582
0.047U_0402_16V4Z~D
+-9%
2
1
C581
0.047U_0402_16V4Z~D
+3.3Vaux
1
C580
0.1U_0402_16V4Z~D
750
2
2
100K_0402_5%~D
2 USB_MCARD3_DET#
100K_0402_5%~D
+3.3V_RUN
C579
0.047U_0402_16V4Z~D
1000
1
Normal
C578
0.047U_0402_16V4Z~D
+-9%
Aux Power
PCIE_WAKE#
2 0_0402_5%~D
2 0_0402_5%~D
MINI3CLK_REQ#
CLK_PCIE_MINI3#
CLK_PCIE_MINI3
<6> CLK_PCIE_MINI3#
<6> CLK_PCIE_MINI3
+3.3V_RUN
+3.3V
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
2
100K_0402_5%~D
GND2
54
+3.3V_ALW_ICH
1
R443
1
USB_MCARD1_DET#
1
@ R741
2PCIE_MCARD1_DET#
0_0402_5%~D
WLAN_RADIO_DIS#_R
2
1 PLTRST3#
0_0402_5%~D
R444
WLAN_SMBCLK
WLAN_SMBDATA
USBP4_DUSBP4_D+
USB_MCARD1_DET#
WIMAX LED
LED_WLAN_OUT#
1
2 LED_WPAN_OUT#
@ R446
0_0402_5%~D
USB_MCARD1_DET# <24>
C
LED_WLAN_OUT# <42>
LED_WPAN_OUT# <42>
WWAN Noise
USB_MCARD1_DET#
1
2
C553
4700P_0402_25V7K~D
@
<24>
@ L33
DLW21SN121SQ2L_4P~D
4 4
3 3
USBP4-
<24>
1
USBP4+
1
2
USBP4_DUSBP4_D+
2
2
0_0402_5%~D
2
0_0402_5%~D
USB_MCARD3_DET# 1
@ R742
2 PCIE_MCARD3_DET#
0_0402_5%~D
WPAN Noise
USB_MCARD3_DET#
+3.3V_RUN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
B
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
TYCO_1775861-1~D
+1.5V_RUN
2
1
C572
4700P_0402_25V7K~D
2
C571 4700P_0402_25V7K~D
HOST_DEBUG_TX
2
R456
HOST_DEBUG_TX <38>
1 PLTRST3#
0_0402_5%~D
WPAN_RADIO_DIS# <37>
MINI_SMBCLK
MINI_SMBDATA
USBP6_DUSBP6_D+
USB_MCARD3_DET#
MSDATA
1
R459
USB_MCARD3_DET# <24>
MSDATA
<38>
LED_WPAN_OUT#
2
0_0402_5%~D
<24>
USBP6-
<24>
USBP6+
1
4
@ L34
DLW21SN121SQ2L_4P~D
1
2 2
4
1
R460
1
R461
3
USBP6_DUSBP6_D+
3
A
2
0_0402_5%~D
2
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
250 (Wake enable)
5 (Not wake enable)
Compal Electronics, Inc.
PROPRIETARY@NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
NA
http://hobi-elektronika.net
5
PCIE_MCARD1_DET#
+1.5V_RUN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
JMINI3
1
<24> PCIE_IRX_MCARDTX_N3
<24> PCIE_IRX_MCARDTX_P3
Normal
2
100K_0402_5%~D
2
100K_0402_5%~D
UIM_DATA
4
C577
33P_0402_50V8J~D
1
Peak
GND1
1
R438
PCIE_MCARD1_DET# 1
@ R439
TYCO_1775861-1~D
+3.3V_RUN
Primary Power
53
WPAN Card
+SIM_PWR
<38> HOST_DEBUG_RX
<38> MSCLK
Voltage
Tolerance
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
4
D
+3.3V_RUN
UIM_VPP
<22> PCIE_MCARD3_DET#
PWR
Rail
1
C562
4.7U_0603_6.3V4Z~D
6
C576
33P_0402_50V8J~D
C573
1U_0603_10V4Z~D
GND
VPP
I/O
NC
GND
GND
MOLEX_475531001
1
USBP5_D+
CARD_SMBDAT <32,38>
USB_MCARD1_DET#
1
R452
1
R453
1
C575
33P_0402_50V8J~D
VCC
RST
CLK
NC
3
2
0_0402_5%~D
2
0_0402_5%~D
USBP5_D-
C561
0.1U_0402_16V4Z~D
UIM_RESET
UIM_CLK
5
6
7
8
9
10
5
2
0_0402_5%~D
1
CARD_SMBCLK <32,38>
CARD_SMBDAT
3
U31
C574
33P_0402_50V8J~D
1
2
3
4
4
1
R450
1
R451
3
C560
0.1U_0402_16V4Z~D
USBP5+
4
C559
0.047U_0402_16V4Z~D
<24>
USBP5-
@ L32
DLW21SN121SQ2L_4P~D
1 1
2 2
C558
0.047U_0402_16V4Z~D
2
<24>
2
1
D
S
G
3
1
1
R448
+3.3V_WLAN
<24> PCIE_ITX_MCARDRX_N3_C
<24> PCIE_ITX_MCARDRX_P3_C
A
PCIE_MCARD1_DET#
<24> ICH_CL_CLK1
<24> ICH_CL_DATA1
<24> ICH_CL_RST1#
+3.3V_RUN
1
100K_0402_5%~D
2
100K_0402_5%~D
PCIE_ITX_WLANRX_N2_C
PCIE_ITX_WLANRX_P2_C
<24> PCIE_MCARD1_DET#
C557
0.1U_0402_16V4Z~D
+
4
+3.3V_WLAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C554
330U_D2E_6.3VM_R25~D
USB_MCARD2_DET# 2
R447
PCIE_MCARD2_DET# 1
R449
JSIM1
2
PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
<24> PCIE_ITX_WLANRX_N2_C
<24> PCIE_ITX_WLANRX_P2_C
COEX2_WLAN_ACTIVE
WIMAX LED
2
0_0402_5%~D
1
R840
+SIM_PWR
1
6
MINI_SMBCLK
MINI_SMBDATA
UIM_RESET
B
PCIE_WAKE#
1
2 0_0402_5%~D
1
2 0_0402_5%~D
WWAN_RADIO_DIS# <37>
PLTRST3#
<22,36>
<24> PCIE_IRX_WLANTX_N2
<24> PCIE_IRX_WLANTX_P2
CARD_SMBCLK
6
Q49A
2N7002DW-T/R7_SOT363-6~D
Mini WLAN
<6> CLK_PCIE_MINI2#
<6> CLK_PCIE_MINI2
WWAN_RADIO_DIS#
1
2 PLTRST3#
R442
0_0402_5%~D
1
Q49B
2N7002DW-T/R7_SOT363-6~D
<6> MINI2CLK_REQ#
C556
0.047U_0402_16V4Z~D
2
1
WLAN_SMBDATA
+3.3V_WLAN
COEX2_WLAN_ACTIVE R440
COEX1_BT_ACTIVE
R441
+1.5V_RUN
+SIM_PWR
C555
0.047U_0402_16V4Z~D
2
1
C563
330U_D2E_6.3VM_R25~D
2
1
C568
33P_0402_50V8J~D
2
1
C567
22U_0805_6.3VAM~D
1
C566
33P_0402_50V8J~D
2
C565
0.047U_0402_16V4Z~D
1
C564
0.047U_0402_16V4Z~D
2
C570
0.047U_0402_16V4Z~D
1
2
JMINI2
2
53
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
@
+3.3V_RUN
C569
33P_0402_50V8J~D
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
TYCO_1775861-1~D
+1.5V_RUN
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
+3.3V_RUN
JMINI1
PCIE_WAKE#
<32,37> PCIE_WAKE#
2
<38> AUX_EN_WOWL
2 PCIE_MCARD2_DET#
0_0402_5%~D
1
+3.3V_RUN
USB_MCARD2_DET# 1
@ R740
1
Mini WWAN
@
4
5
Q48B
2N7002DW-T/R7_SOT363-6~D
2
1
2
3
2
1
2
1
2
2
Q53A
2N7002DW-T/R7_SOT363-6~D
1
C551
4700P_0402_25V7K~D
5
CARD_SMBDAT
3
WLAN_SMBCLK
R435
470K_0402_5%~D
4
R436
200K_0402_5%~D
MINI_SMBDATA
Q53B
2N7002DW-T/R7_SOT363-6~D
D
4
Q47
SI3456BDV-T1-E3_TSOP6~D
R434
2.2K_0402_5%~D
CARD_SMBCLK
6
Q48A
2N7002DW-T/R7_SOT363-6~D
+3.3V_WLAN
6
5
2
1
R433
2.2K_0402_5%~D
D21
RB751S40T1_SOD523-2~D
1
+3.3V_ALW
WLAN_RADIO_DIS#_R
2
R432
100K_0402_5%~D
<37> WLAN_RADIO_DIS#
+15V_ALW
2
0_0402_5%~D
1
R431
100K_0402_5%~D
R430
2.2K_0402_5%~D
R429
2.2K_0402_5%~D
MINI_SMBCLK
1
@ R428
1
+3.3V_RUN
3
2
Title
Mini Card
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
34
of
71
2
1
@ D23
JDOCK1
DPB_DOCK_LANE1_C
6
DPB_DOCK_LANE1#_C
3
DPB_DOCK_LANE0_C
DPB_DOCK_LANE0#_C
<21> DPB_DOCK_LANE0_C
<21> DPB_DOCK_LANE0#_C
DPB_DOCK_LANE1_C
DPB_DOCK_LANE1#_C
<21> DPB_DOCK_LANE1_C
<21> DPB_DOCK_LANE1#_C
8
@ D25
10 DPB_DOCK_LANE2_C
DPB_DOCK_LANE2#_C 2
9
DPB_DOCK_LANE3_C 4
DPB_DOCK_LANE3#_C 5
<21> DPB_DOCK_LANE3_C
<21> DPB_DOCK_LANE3#_C
DPB_DOCK_LANE3_C
6
DPB_DOCK_LANE3#_C
DPB_DOCK_AUX
DPB_DOCK_AUX#
<21> DPB_DOCK_AUX
<21> DPB_DOCK_AUX#
DPB_DOCK_LANE2#_C
7
DPB_DOCK_LANE3_C
DPB_DOCK_LANE3#_C
DPB_DOCK_HPD
<21> DPB_DOCK_HPD
+NBDOCK_DC_IN_SS
2
0_0603_5%~D
BLUE_DOCK
<20> BLUE_DOCK
3
1
R387
8
DPB_DOCK_AUX
1
10 DPB_DOCK_AUX
DPB_DOCK_AUX#
2
9
DPB_DOCK_AUX#
7
DPB_DOCK_HPD
DPB_DOCK_CA_DET
4
5
6
<20> HSYNC_DOCK
<20> VSYNC_DOCK
<38>
DPB_DOCK_CA_DET
<38> CLK_MSE
DAT_MSE
<27> DAI_BCLK#
<27> DAI_LRCK#
3
8
<27>
<27>
RCLAMP0524P.TCT~D
DPB_DOCK_HPD
1
<37>
<37>
D_LAD0
D_LAD1
<37>
<37>
D_LAD2
D_LAD3
<37> D_LFRAME#
<37> D_CLKRUN#
C672
0.1U_0402_16V7K~D
2
DAI_DI
DAI_DO#
<27> DAI_12MHZ#
GND_CLK_DAI
Place close to JP1 connector
GND_VGA
GREEN_DOCK
<20> GREEN_DOCK
GND_VGA
@ D27
DPB_DOCK_HPD
RED_DOCK
<20> RED_DOCK
RCLAMP0524P.TCT~D
<37> D_SERIRQ
<37> D_DLDRQ1#
@
<6> CLK_PCI_DOCK
GND_CLK_PCI
<38> DOCK_SMB_CLK
<38> DOCK_SMB_DAT
GND_CLK_DAI
<38,43> DOCK_SMB_ALERT#
<43> DOCK_PSID
<38> DOCK_PWR_BTN#
<37,43,49> SLICE_BAT_PRES#
GND_CLK_PCI
2
D64
SM24.TCT_SOT23-3~D
2
1
GND_PWR_SENSE
C1034
0.1U_0603_50V4Z~D
1
145
146
147
148
GND1
PWR1
PWR1
PWR1
153
154
155
156
157
158
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
PWR2
PWR2
PWR2
GND2
149
150
151
152
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
159
160
161
162
163
164
DOCK_AC_OFF
DPC_CA_DET
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
DPC_DOCK_AUX_SW
DPC_DOCK_AUX#_SW
DOCK_AC_OFF <37,49>
DOCK_LOM_SPD100LED_ORG# <30>
DPC_CA_DET <21,50>
DPC_LANE_P0_C <50>
DPC_LANE_N0_C <50>
1
10 DPC_LANE_P0_C
DPC_LANE_N0_C
2
9
DPC_LANE_N0_C
DPC_LANE_P1_C
4
7
DPC_LANE_P1_C
DPC_LANE_N1_C
5
6
DPC_LANE_N1_C
3
8
DPC_LANE_P2_C <50>
DPC_LANE_N2_C <50>
DPC_DOCK_HPD
RCLAMP0524P.TCT~D
DPC_LANE_P3_C <50>
DPC_LANE_N3_C <50>
DPC_DOCK_AUX_SW <21>
DPC_DOCK_AUX#_SW <21>
2 DPC_DOCK_HPD
DPC_DOCK_HPD <50>
0_0603_5%~D
ACAV_DOCK_SRC# <49>
1
R821
DPC_LANE_P0_C
DPC_LANE_P1_C <50>
DPC_LANE_N1_C <50>
@ D24
DAT_DDC2_DOCK <20>
CLK_DDC2_DOCK <20>
SATA_SBRX_DTX_P3
2
SATA_SBRX_DTX_N3 C586 2
C587
DPC_LANE_P2_C
1
10 DPC_LANE_P2_C
DPC_LANE_N2_C
2
9
DPC_LANE_N2_C
DPC_LANE_P3_C
4
7
DPC_LANE_P3_C
DPC_LANE_N3_C
5
6
DPC_LANE_N3_C
B
3
1
1 0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
8
SATA_SBRX_DTX_P3_C <23>
SATA_SBRX_DTX_N3_C <23>
RCLAMP0524P.TCT~D
SATA_SBTX_C_DRX_P3 <23>
SATA_SBTX_C_DRX_N3 <23>
@ D26
DPC_DOCK_AUX_SW
USBP8+ <24>
USBP8- <24>
USBP9+ <24>
USBP9- <24>
CLK_KBD <38>
DAT_KBD <38>
10 DPC_DOCK_AUX_SW
1
DPC_DOCK_AUX#_SW 2
9
DPC_DOCK_AUX#_SW
DPC_DOCK_HPD
4
7
DPC_DOCK_HPD
DPC_CA_DET
5
6
DPC_CA_DET
3
8
RCLAMP0524P.TCT~D
Place close to JDOCK1 connector
BREATH_LED# <38,42>
DOCK_LOM_ACTLED_YEL# <30>
DOCK_LOM_TRD0+ <30>
DOCK_LOM_TRD0- <30>
+3.3V_ALW
R1038
100K_0402_5%~D
1
2
DOCK_LOM_TRD1+ <30>
DOCK_LOM_TRD1- <30>
TR0/1CT
TR2/3CT
+LOM_VCT
2.65V when docked.
DOCK_LOM_TRD2+ <30>
DOCK_LOM_TRD2- <30>
DOCK_DET#
DOCK_LOM_TRD3+ <30>
DOCK_LOM_TRD3- <30>
+RTC_CELL
@ R124
100K_0402_5%~D
2
1
DOCK_DCIN_IS+ <48>
DOCK_DCIN_IS- <48>
D71
RB751S40T1_SOD523-2~D
1
2
DOCK_POR_RST# <38>
DOCK_DET_R#
DOCK_DET#
<21,37>
CLK_PCI_DOCK
+DOCK_PWR_BAR
1
2
C1033
0.1U_0603_50V4Z~D
3
+DOCK_PWR_BAR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
R796
100K_0402_5%~D
DPB_DOCK_LANE2_C 1
DPB_DOCK_LANE2_C
DPB_DOCK_LANE2#_C
<21> DPB_DOCK_LANE2_C
<21> DPB_DOCK_LANE2#_C
RCLAMP0524P.TCT~D
B
DPB_DOCK_CA_DET
1
DPB_DOCK_LANE1#_C 5
7
@ D22
<30> DOCK_LOM_SPD10LED_GRN#
<21> DPB_DOCK_CA_DET
@ R462
10_0402_5%~D
R1068
@ 910K_0402_5%~D
2
DPB_DOCK_LANE1_C 4
DPB_DOCK_LANE0#_C
2
9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
1
DPB_DOCK_LANE0#_C 2
DOCK_DET_1
1
10 DPB_DOCK_LANE0_C
1
2
DPB_DOCK_LANE0_C 1
2
@C590
4.7P_0402_50V8C~D
JAE_WD2F144WB1
A
A
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DOCKING CONN
http://hobi-elektronika.net
2
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
1
Sheet
35
of
71
2
1
+1.2V_VDDC_5880
RDIF
CLK
JTAG
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
1
2
2
1
2
1
1
2
1
2
2
1
2
1
2
1
1
2
+1.2V_RUN_AVDD
+3.3V_RUN
3
1
1
2
@ D28
DA204U_SOT323-3~D
2
2
1
1
2
2
1
2
1
A
RFTAG_VRXN
RFTAG_VRXP
2
1
2
JCS1
2
L72
100NH_LLQ1608-FR10G_2%~D
RFREADER_TXP1
2
1
2
1U_0603_10V6K~D
1
1
placement close to U32 pins: RFREADER_TXN1 &
RFREADER_TXP1, and ESD diodes should be placed
between Pi filter and connector.
1
2
+3.3V_RUN
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD3P3
L38
L71
100NH_LLQ1608-FR10G_2%~D
2 RFREADER_TXN1
1
2
1U_0603_10V6K~D
1
1
2
2
1
2
C1021
4.7U_0603_6.3V6M~D
2
C602
1U_0402_6.3V6K~D
1
1
C607
1U_0402_6.3V6K~D
PCI_TPM_TERM 2
1
2
C601
1U_0402_6.3V6K~D
1
B
C606
1U_0402_6.3V6K~D
2
2
C605
1U_0402_6.3V6K~D
1
1
2
C632
0.1U_0402_16V4Z~D
2
1
1
C619
1U_0402_6.3V6K~D
1
2
C631
1U_0402_6.3V6K~D
1
1
C1018
4.7U_0603_6.3V6M~D
1
SPI
SPI
BootStrap
2
C618
1U_0402_6.3V6K~D
1
2
C1017
4.7U_0603_6.3V6M~D
1
1
2
C617
1U_0402_6.3V6K~D
2
2
100K_0402_5%~D
2
4.7K_0402_5%~D
1
2
C875
1U_0402_6.3V6K~D
BCM5880_GPIO15
R498
3K_0402_1%~D
1
2
1
C643
2
C630
3.3U_0603_10V4Z~D
1
R914
BCM5880_GPIO15 1
R341
1
C1071
68P_0402_50V8J~D
SPI_RXD
M45PE16-VMP6TP_SO8~D
SC_DET
R494
3K_0402_1%~D
1
2
1
C639
+1.2V_RUN_AVDD
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD1P2
L37
C1070
68P_0402_50V8J~D
8
7
6
5
48MHz
C629
0.1U_0402_16V4Z~D
Q
VSS
VCC
W#
RVD
C647
150P_0402_50V8J~D
D
C
RESET#
S#
4.7P_0402_50V8C~D
C589
1
2
3
4
CLK_PCI_TPM
R744
10_0402_5%~D
TYCO_1-1775784-1
U34
SPI_TXD
SPI_CLK
SPI_RST
SPI_CS
2
Pull-downs for 5880
Rev A0, and pull-ups
for Rev B0
2
RFREADER_RXP
4@ R1016
100K_0402_5%~D
10
9
8
7
6
5
4
3
2
1
2
@
1
R913
300_0402_5%~D
10
9
8
7
6
5
4
3
2
1
24MHZ 27.12MHz
POR_EXTR
+3.3V_RUN
@
SC_IO
SC_C8
SC_DET
2
GND
GND
SPI
RVD
R488
3.3M_0402_5%~D
1
12
11
SMC
AD[16:15]
1
RFREADER_RXN
JSC1
SC_RST
SC_CLK
SC_C4
+3.3V_RUN
1
AD[18:17]
REF CLK
2
R476
5.1M_0402_5%~D
C644
1U_0603_10V4Z~D
1
2
When using the 73S8009C,no-stuff R768,R769,R490
When using the 73S8009CN,stuff R768,R769,R490
C646
0.47U_0402_6.3V6K~D
@ C1031
10U_0805_10V4Z~D
2
1
2
+3.3V_RUN
SC_DET
SC_IO
SC_C4
SC_C8
SC_CLK
SC_RST
USB
Boot SRC
+2.5V_RUN_AVDD
BLM18BB100SN1D_0603~D
2
1 +RFID_AVDD2P5
L36
1
1
10UH_LQH32CN100K53L_10%~D
1
1
2
+3.3V_RUN
1
11
C641
150P_0402_50V8J~D
2
C621
4.7U_0603_6.3V6K~D
2
1
100K_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
10
C628
1U_0402_6.3V6K~D
17
28
31
2
L69
TER_USBH_N1
TER_USBH_P1
R773 2
1
R491 1
2
R493 1
2
R492 1
2
R772 1
2
01
C627
1U_0603_10V4Z~D
GND
GND
GND
+LIN
00
JTCE_USH
R898
4.7K_0402_5%~D
2
1
2
+2.5V_RUN_AVDD
SSMC
C626
0.1U_0402_16V4Z~D
23
25
14
22
21
20
16
18
73S8009CN-32IMR/F_QFN32_5X5~D
2
Function
C625
1U_0402_6.3V6K~D
DM
DP
PRES
I/O
AUX1
AUX2
CLK
RST
+SC_VCC
+SC_VCC
1
JTAG_RST#_USH
R897
0_0402_5%~D
1
2
C624
1U_0402_6.3V6K~D
19
26
29
15
27
C1015
27P_0402_50V8J~D
VCC
VPC
VDD
VP
LIN
C633
27P_0402_50V8J~D
A
ON/OFF
CLKIN
RDY
OFF_ACK
OFF_REQ
CS
SC_USB#
CMDVCC5#
CMDVCC3#
RSTIN
OFF#
TEST1
TEST2
I/OUC
AUX1UC
AUX2UC
JTAG_TMS_USH
@
@@@
24
7
2
1K_0402_5%~D
8
9
11
47K_0402_1%~D
12
13
2 SC_USB#
2 47K_0402_1%~D 4
2 47K_0402_1%~D 5
1 10K_0402_5%~D 6
32
10
30
BCM5880_IO
1
AUX1UC
2
AUX2UC
3
JTAG_TDO_USH
R896
0_0402_5%~D
1
2
2 BBCLK
1K_0402_5%~D
2 LPC_EN_R
4.7K_0402_5%~D
2 JTAG_RST#_USH
1K_0402_5%~D
2 SMC_ADD15
4.7K_0402_5%~D
SMC_ADD18
SMC_ADD17
USBH_OC0#
USBH_OC1#
1
R473
1
6@ R483
1
R737
1
R478
R485
4.7K_0402_5%~D
U33
GPIO14_TER_ON/OFF
BCM5880_SCCLK
1
R771
PAD~D T139
PAD~D T63
PAD~D T64
GPIO16_TER_TRIS@ R490 1
5880_GPIO26
R766 1
5880_GPIO25
R767 1
BCM5880_SCRST R770 2
BCM5880_SCDET
JTAG_TDI_USH
SBOOT
1
2
+3.3V_RUN
2 LPD#
4.7K_0402_5%~D
2 OVSTB
4.7K_0402_5%~D
2 TAMPER_N
4.7K_0402_5%~D
2 RST_N
4.7K_0402_5%~D
2 SMC_ADD16
4.7K_0402_5%~D
1 SC_USB#
10K_0402_5%~D
2 FP_RESET#
4.7K_0402_5%~D
C638
1U_0402_6.3V6K~D
2
VDDO_33
VDDO_33
VDDO_33
C637
1U_0402_6.3V6K~D
1
1
VESD
C636
1U_0402_6.3V6K~D
2 8009_VDDMON
47K_0402_1%~D
2
C706
10U_0805_10V6M~D
@
GPIO2_TER_VDDMON 1
R20
1
C620
0.1U_0402_16V4Z~D
1
2
C1014
0.1U_0402_16V4Z~D
2
C609
15P_0402_50V8J~D
+3.3V_RUN
VDD_BB
VDD_BB
C635
1U_0402_6.3V6K~D
+3.3V_RUN
C1013
0.1U_0402_16V4Z~D
2 GND GND 4
1
27.12MHZ_12PF_1N227120CC0B~D
C608
12P_0402_50V8J~D
2
2
1
V3P3_TAMPER_N
@ R847
4.7K_0402_5%~D
OUT
XO
BCM5880KFBG_FBGA225~D
R705 1
2 0_0402_5%~D LPC_LFRAME#_R
R723 1
2 0_0402_5%~D LPC_LAD0_R
R724 1
2 0_0402_5%~D LPC_LAD1_R
R732 1
2 0_0402_5%~D LPC_LAD2_R
R733 1
2 0_0402_5%~D LPC_LAD3_R
<23,29,37,38> LPC_LFRAME#
<23,29,37,38> LPC_LAD0
<23,29,37,38> LPC_LAD1
<23,29,37,38> LPC_LAD2
<23,29,37,38> LPC_LAD3
V3P3_PWRGOOD
2
BCM5880KFBG_FBGA225~D
1
R474
1
R484
1
R736
1
R810
1
R479
2
R850
1
R1034
@ R846
4.7K_0402_5%~D
IN
3
1
L8
L9
L10
L11
@ R482
4.7K_0402_5%~D
R487
0_0402_5%~D
Y3
1
V3P3_BBLCLK
C14
G11
G6
G7
G8
H10
H11
H6
H7
H8
H9
J10
J12
J6
J7
J8
J9
K10
K12
L12
M13
F8
C616
1U_0402_6.3V6K~D
REF_XIN
1
2
R339
4.7K_0402_5%~D
H14
+3.3V_RUN
BCM5880KFBG_FBGA225~D
JTAG_CLK_USH
R895
0_0402_5%~D
1
2
VDDO_33SC
VDDO_33SC
VDDO_SC
H12
J13
+3.3V_RUN
+3.3V_RUN
L13
M14
K13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C615
1U_0402_6.3V6K~D
2
R899
0_0402_5%~D
1
2
VDDO_33CORE
VDDO_33CORE
VDDO_33CORE
H15
1
0_0402_5%~D
TAMPER_N H13
2
R471
+3.3V_RUN
R820
4.7K_0402_5%~D
1
1
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTN
JTCE
BBCLK
@
XI
2
10M_0402_5%~D
2
C1023
1U_0402_6.3V6K~D
@
1
R486
2
C1022
1U_0402_6.3V6K~D
2 REF_XOUT
0_0402_5%~D
1
R481
C8
D7
A5
E9
G10
F10
A10
A9
B8
E8
RST_N
RSTOUT_N
P10
R11
N10
R12
P11
M9
@
+SC_PWR
Smard Card
T142
HF_RFIDTAG_AVSS
HF_RFIDTAG_AVSS
HF_RFIDTAG_DVSS
HF_RX_ADC_AVSS1
HF_RX_ADC_AVSS2
HF_RX_AVSS
HF_RX_AVSS
HF_TX_AVSS
HF_TX_AVSS
HF_TX_AVSS
VDDO_LPC
VDDO_LPC
K5
L5
L6
C1019
4.7U_0603_6.3V6M~D
PAD~D
CLKOUT
CLKOUT_EN
N8
R8
K8
L7
AVSS_LDO12
AVSS_ldo25
AVSS_ldo25
AVSS_AUX
AVSS_REF
AVSS_PLL
C614
1U_0402_6.3V6K~D
K2
J1
K1
J3
M1
K3
P12
J2
L1
A1
2 BBCLK_R
2 4.7K_0402_1%~DB2
PLTRST3# 1
2 RST_N
SPI_RST
@ R1071
0_0402_5%~D
JTAG_CLK_USH
JTAG_TDI_USH
JTAG_TDO_USH
JTAG_TMS_USH
JTAG_RST#_USH
JTCE_USH
VDDO_SMC
VDDO_SMC
VDDO_SMC
C613
1U_0402_6.3V6K~D
SMC_ADV_N
SMC_BLS_N_0
SMC_BLS_N_1
SMC_CRE
SMC_CS_N_0
SMC_CS_N_1
SMC_IO_3V
SMC_OE_N
SMC_WE_N
AUXCLK_XTALIN
AUXCLK_XTALOUT
VDDO_VAR
VDDO_VAR
Place
close
to
pinA14
C599
1U_0402_6.3V6K~D
@
BCM5880_SCCLK_R
BCM5880_SCVCC
BCM5880_SCRST
BCM5880_IO
AUX1UC
AUX2UC
BCM5880_SCDET
D15
E14
E6
F6
G5
H5
J5
1
2
@ C591
680P_0402_50V7K
R4
M5
1
2
R463 1
D10
2 2.2K_0402_5%~D
R465
4.7K_0402_5%~D
A14
G12
+2.5V_RUN_AVDD
B13
A13
1
+3.3V_RUN
B12
E11
+1.2V_RUN_AVDD
E13
2
F13
+1.2V_RUN_PLL
D14
P15 +OTP_PWR 2
1
+3.3V_RUN
@ R467
0_0603_5%~D
F11
2
1
+SC_PWR
R829
0_0603_5%~D
C12
D11
C15
+1.2V_VDDC_5880
E15
C1020
4.7U_0603_6.3V6M~D
5880_GPIO25
5880_GPIO26
2
10_0402_5%~D
22_0402_5%~D
BBCLK R555 1
R848 1
RFREADER_RXN
RFREADER_RXP
RFREADER_TXN1
RFREADER_TXP1
CORE_CINRUSH
CORE_PWRDN
ALDO_PWRDN
AVDD33_LDO25
AVDD_2P5I
AVDD_2P5O
AVDD25_ldo12
AVDD25_ldo12
AVDD_1P2O
AVDD_1P2I_AUX
AVDD_1P2I_REF
AVDD25_PLL
OTP_PWR
C598
1U_0402_6.3V6K~D
1
R472
BCM5880
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
C612
1U_0402_6.3V6K~D
GPIO_25/SC_SEL5V
GPIO_26/SC_SEL18V
SC_CINRUSH
SC_CLK
SC_VCC
SC_RST
SC_IO
SC_FCB
SC_FCB_ENB
SC_DET
SC_PWR
SC_PWR
@
BCM5880_SCCLK
<33>
REFCLK_XTALIN
REFCLK_XTALOUT
+RFID_AVDD3P3
1
2
C595
0.01U_0402_25V7K~D
RFTAG_VRXN
RFTAG_VRXP
R845
4.7K_0402_5%~D
P8
R7
N15
L14
L15
K15
K14
J14
J15
M10
M15
N14
C600
680P_0402_50V7K
1
2
FP_RESET#
REF_XIN
F15
REF_XOUT F14
+3.3V_RUN
R844
4.7K_0402_5%~D
USBH_DN1
USBH_UP1
USBH_OC_1
SBOOT
SWV
OVSTB/ZEROB
SCANACCMODE
SECURE_BOOT
SWV/ERROR,OSC1,OSC2,SPL
TESTMODE/TST_SEC_BOOT
IDDQ_EN/CM3_MODE
B6
A6
C7
B7
E7
B10
C10
A11
A12
C11
B11
C9
B9
+RFID_AVDD1P2
R819
4.7K_0402_5%~D
N13
P13
R15
N9
M8
P9
M12
R9
R10
HF_RFIDTAG_AVSS
HF_RFIDTAG_VREF
HF_RFIDTAG_VRX_N
HF_RFIDTAG_VRX_P
HF_RFIDTAG_VTX
HF_RX_TEST0
HF_RX_TEST1
HF_RX_TEST2
HF_RX_TEST3
HF_RX_N
HF_RX_P
HF_TX_N
HF_TX_P
C13
E5
F5
J11
K11
K6
K7
K9
N4
P4
+RFID_AVDD2P5
@ R475
4.7K_0402_5%~D
2 22_0402_5%~D USBH_N1
2 22_0402_5%~D USBH_P1
USBH_OC1#
SMC_ADD15
SMC_ADD16
SMC_ADD17
SMC_ADD18
PLL_VDD_1P2I
PLL_AVDD_1P2O
PLL_VSS
PLL_VDD_1P2I
PLL_VSS
NC
A7
F7
C6
E10
F9
G9
D8
A8
D9
C877
1U_0402_6.3V6K~D
R768 1
R769 1
OVSTB
@
USBH_DN0
USBH_UP0
USBH_OC_0
B14
B15
D12
D13
E12
A15
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_AVDD2P5
HF_RFIDTAG_DVDD1P2
HF_RX_ADC_AVDD1P2
HF_RX_AVDD1P2
HF_RX_AVDD2P5
HF_TX_AVDD1P2
HF_TX_AVDD2P5
HF_TX_AVDD3P3
@
N11
N12
M11
2
POR_AVSS
POR_EXTR
POR_INT12
POR_MONITOR
C597
1U_0402_6.3V6K~D
TER_USBH_N1
TER_USBH_P1
FP_USBDFP_USBD+
USBH_OC0#
FP_USBDFP_USBD+
2
1
BCM5880
F12
POR_EXTR G13
G15
G14
C873
1U_0402_6.3V6K~D
<33>
<33>
SMC_DATA_0
SMC_DATA_1
SMC_DATA_2
SMC_DATA_3
SMC_DATA_4
SMC_DATA_5
SMC_DATA_6
SMC_DATA_7
SMC_DATA_8
SMC_DATA_9
SMC_DATA_10
SMC_DATA_11
SMC_DATA_12
SMC_DATA_13
SMC_DATA_14
SMC_DATA_15
USBD_DN
USBD_UP
GPIO_27/USBD_ATATCH
1
C593
1U_0603_10V4Z~D
USBP10USBP10+
R2
P3
R1
P2
R3
M4
N2
N3
P1
M3
M2
L4
N1
L3
L2
K4
+1.2V_RUN_PLL
@
<24>
<24>
H1
J4
H2
H3
G1
H4
F2
G4
G2
G3
E2
F4
F1
F3
D2
E3
D1
E1
C2
D3
C1
E4
B1
C3
@
@
B
GPIO_14
GPIO_15
GPIO_16
SMC_ADD_0
SMC_ADD_1
SMC_ADD_2
SMC_ADD_3
SMC_ADD_4
SMC_ADD_5
SMC_ADD_6
SMC_ADD_7
SMC_ADD_8
SMC_ADD_9
SMC_ADD_10
SMC_ADD_11
SMC_ADD_12
SMC_ADD_13
SMC_ADD_14
SMC_ADD_15/REFCLK_FREQ_0
SMC_ADD_16/REFCLK_FREQ_1
SMC_ADD_17/BOOT_SRC_0
SMC_ADD_18/BOOT_SR_1
SMC_ADD_19
SMC_ADD_20
SMC_ADD_21
SMC_ADD_22
SMC_ADD_23
C592
1U_0603_10V4Z~D
@
@
2 PLTRST3#_USH
10K_0402_5%~D
GPIO14_TER_ON/OFF C4
BCM5880_GPIO15
A2
2 LPC_EN_R
47K_0402_1%~D
GPIO16_TER_TRIS
D4
2 IRQ_SERIRQ_R
47K_0402_1%~D
R468 1
R13
2 0_0402_5%~D USBP10-_R
R469 1
R14
2 0_0402_5%~D USBP10+_R
R470 1
P14
2 1.5K_0402_5%~D
UART LPC
BCM5880
1
@ R1059
1
5@ R841
1
R843
U32C
U32B
C596
1U_0402_6.3V6K~D
5@ D70
U32A
RB751S40T1_SOD523-2~D
1
2
@ R464
CLK_PCI_TPM
0_0402_5%~D
R1048
M7 LCLK
R6 LPCEN
1
2 0_0402_5%~D LPC_EN_R
<29,37> SP_TPM_LPC_EN
PLTRST3#
N5 GPIO_17/LRESET_N
1
2 PLTRST3#_USH
<22,34> PLTRST3#
LPC_LFRAME#_R
P5 GPIO_18/LFRAME_N
IRQ_SERIRQ_R
M6 GPIO_19/LSERIRQ
1
2
<24,29,31,37,38> IRQ_SERIRQ
LPC_LAD0_R
R842
0_0402_5%~D
R5 GPIO_20/LAD[0]
LPC_LAD1_R
N6 GPIO_21/LAD[1]
LPC_LAD2_R
N7 GPIO_22/LAD[2]
LPC_LAD3_R
P6 GPIO_23/LAD[3]
LPD#
P7 GPIO_24/LPCPD_N
1
2
<29,37> SP_TPM_LPC_EN
R466
0_0402_5%~D
UART_RX/GPIO0
B5 GPIO_0/UART_RX
UART_RX/GPIO0
UART_TX/GPIO1
B4
GPIO2_TER_VDDMON D6 GPIO_1/UART_TX
R894
GPIO_2/UART_CTS
SC_DET
SC_DET_R
0_0402_5%~D
A4 GPIO_3/UART_RTS
2
1
R849
1.5K_0402_1%~D
1
2
SPI_CLK
C5 GPIO_6/SSP_CLK
UART_TX/GPIO1
SPI_CS
B3 GPIO_7/SSP_FSS
SPI_RXD
D5 GPIO_8/SSP_RXD
+3.3V_RUN
SPI_TXD
A3 GPIO_9/SSP_TXD
<6> CLK_PCI_TPM
1
R496
1
R497
2
4.12K_0402_1%~D
2
4.12K_0402_1%~D
1
C640
1
C642
2
1U_1206_100V4Z~D
2
1U_1206_100V4Z~D
RFREADER_TXN1_PI
ANT_RFTAG_VRXN_R
ANT_RFTAG_VRXP_R
RFREADER_TXP1_PI
<24> CONTACTLESS_DET#
1
2
3
4
5
6
1
2
3
4
5 G1
6 G2
7
8
TYCO_1-1775784-0
+3.3V_RUN
3
1
2
@ D29
DA204U_SOT323-3~D
Hardware enable for USH TPM:Populate D70 & R841,
No Stuff R483.
Hardware disable for USH TPM:No Stuff D70 &
R841, Populate R483
DELL CONFIDENTIAL/PROPRIETARY
1
2
SWV
@ C594
680P_0402_50V7K
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
http://hobi-elektronika.net
USH I/F
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
36
of
71
5
4
3
2
1
+3.3V_ALW
PCIE_WAKE#
2
10K_0402_5%~D
SLICE_BAT_PRES#
2
4.7K_0402_5%~D
DCIN_CBL_DET#
2
100K_0402_5%~D
CELL_CHARGER_DET#
1
100K_0402_5%~D
PWR_BTN_BD_DET#
2
100K_0402_5%~D
1
R501
1
R503
1
R862
2
R877
1
R754
+3.3V_ALW
1
2
1
C1072
10U_0805_10V4Z~D
2
1
C648
0.1U_0402_16V4Z~D
1
2
C652
0.1U_0402_16V4Z~D
2
1
C649
0.1U_0402_10V7K~D
2
1
C650
0.1U_0402_16V4Z~D
2
C651
0.1U_0402_16V4Z~D
D
<56> GFX_CORE_ON
<26> HDDC_EN
<26> MODC_EN
<35,43,49> SLICE_BAT_PRES#
<42> PWR_BTN_BD_DET#
<29> LAN_DISABLE#_R
<42> CAP_LED#
<42> SYS_LED_MASK#
<50> GFX_OPEN_GL_EN
<24> SIO_EXT_WAKE#
<22> ICH_PME#
<24> ICH_PCIE_WAKE#
<34> WLAN_RADIO_DIS#
B
<34> WWAN_RADIO_DIS#
@ D66
RB751S40T1_SOD523-2~D
<38,42> INSTANT_ON_SW#
INSTANT_ON_SW#
1
2
INSTANT_ON_SW_D#
1
2
R1036
0_0402_5%~D
GFX_CORE_ON
INSTANT_ON_SW_D#
HD DC_EN
MODC_EN
63
28
29
30
31
GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N
SLICE_BAT_PRES#
PWR_BTN_BD_DET#
32
33
GPIOH[6]
GPIOH[7]
LAN_DISABLE#_R
88
89
90
91
92
93
94
95
WWAN_RADIO_DIS#
VGA_IDENTIFY
CHIPSET_ID1
R528
10K_0402_5%~D
2
1
CHIPSET_ID0
BID2
BID1
BID0
2
2
1
@ R534
1
@ R535
1
@ R536
1
R537
1
R538
BID1
BID2
CHIPSET_ID0
CHIPSET_ID1
5
GPIOI[7](ATEST)
126
DOCK_AC_OFF_EC
GPIOI[4](XTAL1/CLKIN)
GPIOI[3](XTAL2)
123
122
3.3V_RUN_ON
54
52
49
47
42
41
56
37
46
44
39
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST2#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLKI (14.318 MHz)
64
CLK_SIO_14M
VSS
96
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLK_RUN#
DLDRQ1#
DSER_IRQ
55
53
50
48
43
38
45
40
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
DLPC
109
110
111
112
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
ACAV_IN_NB
2
1
R514
1K_0402_5%~D
<38,48>
1
ACAV_IN_NB
1
IN1
2
IN2
SIO_SLP_S3# <24>
3.3V_RUN_ON <40>
2
R515
2
R516
1.05V_RUN_ON
2
R518
3.3V_RUN_ON
2
R519
0.9V_DDR_VTT_ON 2
R520
PBATT_OFF
2
R521
GFX_CORE_ON
1
R523
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
RUN_ON
@ R1081
2 0_0402_5%~D
1.5V_RUN_ON
2
1
O 4
D65
RB751S40T1_SOD523-2~D
U69
74AHC1G08GW_SOT353-5~D
LPC_LAD[0..3] <23,29,36,38>
DOCK_AC_OFF <35,49>
R1078
33K_0402_5%~D
C
+3.3V_RUN
LPC_LFRAME# <23,29,36,38>
PLTRST2# <22,38>
CLK_PCI_5028 <6>
CLKRUN# <24,29,31,38>
LPC_LDRQ0# <23>
LPC_LDRQ1# <23>
IRQ_SERIRQ <24,29,31,36,38>
CLK_PCI_5028
R648
10K_0402_5%~D
ME_FWP
CLK_SIO_14M
R527
10_0402_5%~D
@R506
10_0402_5%~D
CLK_SIO_14M <6>
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
@ R649
10K_0402_5%~D
D_LAD0 <35>
D_LAD1 <35>
D_LAD2 <35>
D_LAD3 <35>
D_LFRAME# <35>
D_CLKRUN# <35>
D_DLDRQ1# <35>
D_SERIRQ <35>
1
C656
4.7P_0402_50V8C~D
2
1
@C654
4.7P_0402_50V8C~D
2
B
+3.3V_ALW
R524
1M_0402_5%~D
PWRGD
RUNPWROK
7
OUT65
105
GPIOJ[4](VSS)
VSS
GPIOK[7](VSS)
VSS
VSS
VSS
VSS
VSS
GPIOJ[1](VSS)
11
17
23
36
51
72
87
121
128
RUNPWROK
<38,41,47>
SP_TPM_LPC_EN <29,36>
LID_CL_SIO#
R525
10_0402_5%~D
2
1
LID_CL#
LID_CL#
<42>
1
IRTX
IRRX
GPIOF[3]/IRMODE/IRRX3B
GPIOF[2]/IRTX2
GPIOF[1]/IRRX2
GPIOF[0]/IRMODE/IRRX3A
GPIO_PSID_SELECT <43>
SPI_WP#_SEL <24>
1
2
2
C655
0.047U_0402_16V4Z~D
C657
4.7U_0603_6.3V4Z~D
TP_DET#
ECE5028-NU_VTQFP128_14X14~D
TP_DET#
<39>
BID2 BID1 BID0 REV
@
1
1
2
1
2
1
2
1
R533
10K_0402_5%~D
R532
10K_0402_5%~D
BID0
R531
10K_0402_5%~D
R530
10K_0402_5%~D
R529
10K_0402_5%~D
A
CLK
GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]
SYSOPT1/GPIOH[2]
SYSOPT0/GPIOH[3]
115
116
117
118
TEST
LPC
106
107
113
114
GPIO
TEST_PIN
35
C1051
0.1U_0402_16V4Z~D
2
1
GPIOD[1]
GPIOD[2]
+3.3V_ALW
@
GPIOB[0]/INIT#
GPIOB[1]/SLCTIN#
GPIOC[2]/SCLT
GPIOC[3]/PE
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIOC[6]/ERROR#
GPIOC[7]/ALF#
GPIOD[0]/STROBE#
GPIOC[1]/PD7
GPIOC[0]/PD6
GPIOB[7]/PD5
GPIOB[6]/PD4
GPIOB[5]/PD3
GPIOB[4]/PD2
GPIOB[3]/PD1
GPIOB[2]/PD0
61
62
R526 1
2 0_0402_5%~D
ICH_PME#
ICH_PCIE_WAKE#
WLAN_RADIO_DIS#
DP_MB_EN
D_DLDRQ1#
1
LID_CL_SIO#
1.05V_RUN_ON
SYS_LED_MASK#
+CAP_LDO 8mil
D_SERIRQ
2
<40> 1.05V_RUN_ON
Option for select PC Card &
Express Card
For PC Card stuff R882
For Experss card stuff R883
IMVP_VR_ON <47>
IMVP_PWRGD <24,41,47>
0.9V_DDR_VTT_ON <46>
+3.3V_ALW
DP_MB_EN
<21>
+3.3V_RUN
1
1
2@ R883
100K_0402_5%~D
2
0_0402_5%~D
0.9V_DDR_VTT_ON
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2
2
DET_PCCRD_EXPSCRD#
LCD_TST
PSID_DISABLE#
PANEL_BKEN_GPU
DOCKED
DOCK_DET#
AUD_NB_MUTE
CELL_CHARGER_DET#
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
1
R509
2
R510
2
R511
2
R512
2
1
<19> LCD_TST
<43> PSID_DISABLE#
<50> PANEL_BKEN_GPU
<29,30> DOCKED
<21,35> DOCK_DET#
<28> AUD_NB_MUTE
<33> CELL_CHARGER_DET#
<19> LCD_VCC_TEST_EN
<19> CCD_OFF
<27,28,33> AUD_HP_NB_SENSE
<33> ESATA_USB_PWR_EN#
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
125
124
120
86
127
D_CLKRUN#
1
1@ R882
100K_0402_5%~D
USB_SIDE_EN#
EN_I2S_NB_CODEC
CB_HWSPND#
EN_DOCK_PWR_BAR
ADAPT_OC
GPIOI[6](VDDA33PLL)
GPIOI[5](VDDA18PLL)
GPIOI[2](VDD18)
CAP_LDO
GPIOJ[0](RBIAS)
RUN_ON
1.5V_RUN_ON
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
1
100K_0402_5%~D
2
100K_0402_5%~D
2
2
<33> USB_SIDE_EN#
<27> EN_I2S_NB_CODEC
<31> CB_HWSPND#
<49> EN_DOCK_PWR_BAR
<48> ADAPT_OC
BIOS_RECOVERY
GPIOE[0]/RXD
GPIOE[1]/TXD
GPIOE[2]/RTS#
GPIOE[3]/DSR#
GPIOE[4]/CTS#
GPIOE[5]/DTR#
GPIOE[6]/RI#
GPIOE[7]/DCD#
1
T81 PAD~D
SNIFFER_BLUE# <42>
2
SNIFFER_YELLOW# <42>
DOCK_HP_DET <27>
CRT_SWITCH <20>
ME_FWP
<23>
NB_AC_OFF <43,48,49>
DP_PRIORITY <21>
2.5V_RUN_PWRGD <18,41>
RUN_ON
<19,28,40,41,56>
1.5V_RUN_ON <45>
1
PAD~D T149
USB
9
10
13
12
15
16
19
18
21
22
2
@ R507
SNIFFER_YELLOW# 2
@ R508
TP_DET#
2
R756
VGA_IDENTIFY
2
R522
INSTANT_ON_SW_D# 1
@ R1035
1
+3.3V_RUN
GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0)
GPIOJ[6](USBDP1)
GPIOJ[5](USBDN1)
GPIOK[0](USBDP2)
GPIOK[1](USBDN2)
GPIOK[3](USBDP3)
GPIOK[2](USBDN3)
GPIOK[5](USBDP4)
GPIOK[6](USBDN4)
DOCK_MIC_DET <27>
MCH_TSATN_EC <10>
1.8V_RUN_ON
@
SNIFFER_BLUE#
SNIFFER_YELLOW#
DOCK_HP_DET
CRT_SWITCH
ME_FWP
NB_AC_OFF
119
2
@
C
GPIOI[1](VCC1)
DOCK_MIC_DET
1
DET_PCCRD_EXPSCRD#
1
2
3
4
5
84
83
6
GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
BC_INT#
BC_DAT
BC_CLK
ECE5028-NU
(ECE5018)
+3.3V_ALW
SNIFFER_BLUE#
8
14
20
2
24
25
26
27
58
59
60
+3.3V_ALW
VCC1(VDDA33)
GPIOJ[7](VDDA33)
GPIOK[4](VDDA33)
5
LCD_TST
2
100K_0402_5%~D
PANEL_BKEN_GPU
1
100K_0402_5%~D
SYS_LED_MASK#
2
10K_0402_5%~D
1
R816
2
R505
1
R658
WIRELESS_ON#/OFF
WPAN_RADIO_DIS#
EXPRCRD_PWREN#
EXPRCRD_STDBY#
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]
P
<42> WIRELESS_ON#/OFF
<34> WPAN_RADIO_DIS#
<32> EXPRCRD_PWREN#
<32> EXPRCRD_STDBY#
<38> BC_INT#_ECE5028
<38> BC_DAT_ECE5028
<38> BC_CLK_ECE5028
WIRELESS_ON#/OFF
2
100K_0402_5%~D
SP_TPM_LPC_EN
2
10K_0402_5%~D
1
R874
1
@ R788
97
98
99
DCIN_CBL_DET#
100
PBATT_OFF
101
MDC_RST_DIS#
102
PCIE_WAKE#
103
USB_POWERSHARE_PWR_EN# 104
G
+3.3V_RUN
PBAT_PRES#
C653
0.1U_0402_16V4Z~D
<43> PBAT_PRES#
<42> SCRL_LED#
<42> NUM_LED#
<43> DCIN_CBL_DET#
<49> PBATT_OFF
<33> MDC_RST_DIS#
<32,34> PCIE_WAKE#
<33> USB_POWERSHARE_PWR_EN#
USB_SIDE_EN#
2
10K_0402_5%~D
ESATA_USB_PWR_EN#
2
100K_0402_5%~D
USB_POWERSHARE_PWR_EN#
1
100K_0402_5%~D
1
R502
1
R923
2
R929
VCC1
VCC1
VCC1
VCC1
U35
3
+3.3V_ALW2
34
57
85
108
D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
2
10K_0402_5%~D
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
X00
X01
X02
X03
X04
X05
X06
X07
CHIPSET_ID0
0
0
CHIPSET_ID1
Note
A
0
0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
3
2
Title
ECE5028
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
37
of
71
5
4
3
2
1
1
+RTC_CELL
R539
100K_0402_5%~D
1
1
R554
DOCK_PWR_BTN# <35>
+RTC_CELL
+3.3V_ALW
2
R578
10K_0402_5%~D
SNIFFER/INSTANT_SW# 2
@ R900
2
INSTANT_ON_SW#
DOCK_SMB_CLK
CLK_KBD
+3.3V_ALW
CARD_SMBDAT
CARD_SMBCLK
CLK_MSE
R85
1K_0402_5%~D
1
100K_0402_5%~D
1
2.2K_0402_5%~D
1
2.2K_0402_5%~D
+5V_RUN
2
R569
2
R570
2
R571
2
R572
1
R573
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
1
4.7K_0402_5%~D
2
10K_0402_5%~D
@
1
2
1
JTAG_RST#
@ JTAG1
@SHORT PADS~D
+RTC_CELL
@ C1011
1
2
5
IN1
1
INSTANT_ON_SW#
IN2
2
SNIFFER_PWR_SW#
O
2
R445
1=JTAG interface Reset disabled
0=Reset JTAG interface
B
0.1U_0402_16V4Z~D
P
SNIFFER/INSTANT_SW#
4
ALWON
ALWON
<44>
EN_CELL_CHARGER_DET#
EN_CELL_CHARGER_DET# <33>
POWER_SW_IN#
ACAV_IN
ACAV_IN
<18,48>
DOCK_PWR_SW#
C
+3.3V_ALW
1
CARD_SMBDAT <32,34>
CARD_SMBCLK <32,34>
2
R589
2
R565
2
R567
1
1
DOCK_SMB_DAT <35>
DOCK_SMB_CLK <35>
LCD_SMBDAT <19>
LCD_SMBCLK <19>
CKG_SMBDAT <6,27,48>
CKG_SMBCLK <6,27,48>
AMT_SMBDAT <24>
AMT_SMBCLK <24>
ACAV_IN_NB <37,48>
AC_PRESENT
1
RC _ID
DAT_MSE
2
ACAV_IN_NB
DAT_KBD
2
DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK
DOCK_SMB_DAT
1
5
6
7
8
12
13
93
94
95
96
97
98
99
100
M_ON
ICH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
@ R586
10K_0402_5%~D
SIO_SLP_M#
<24>
DOCK_SMB_ALERT# <35,43>
ME_WOL_EN <24>
ME_SUS_PWR_ACK <24>
1.8V_SUS_PWRGD <46>
ICH_CL_PWROK <10,24>
3.3V_LAN_PWRGD <41>
1.05V_M_PWRGD <45>
ALW_PWRGD_3V_5V <44,46>
SUSPWROK
<41>
SIO_SLP_S5# <24>
BEEP
<27>
AUX_ON
<40>
ODD_DET#
<24,26>
3.3V_M_PWRGD <18,41>
AUX_EN_WOWL <34>
SIO_SLP_S4# <24>
M_ON
<40,45>
ICH_RSMRST# <24>
AC_PRESENT <24>
SIO_PWRBTN# <24>
2
SIO_SLP_M#
DOCK_SMB_ALERT#
ME_WOL_EN
ME_SUS_PWR_ACK
1.8V_SUS_PWRGD
ICH_CL_PWROK
3.3V_LAN_PWRGD
1.05V_M_PWRGD
ALW_PWRGD_3V_5V
SUSPWROK
SIO_SLP_S5#
BEEP
AUX_ON
ODD_DET#
1
100K_0402_5%~D
+3.3V_ALW
FWP#
2
= Amber LED
= Blue LED
1
100K_0402_5%~D
2
100K_0402_5%~D
2
200K_0402_5%~D
1
RB751S40T1_SOD523-2~D
2
HOST_DEBUG_TX <34>
HOST_DEBUG_RX <34>
RESET_OUT# <41>
MSDATA
<34>
MSCLK
<34>
SIO_A20GATE <23>
PS_ID
<43>
BAT1_LED#
<42> Bat2
BAT2_LED#
<42> Bat1
2
@ R560
SNIFFER_PWR_SW#
1
R562
EN_CELL_CHARGER_DET# 1
R504
2
D68
1
2
3
14
15
16
17
18
28
29
30
31
32
33
34
73
84
89
90
91
108
109
118
119
120
126
127
128
1
2
1K_0402_5%~D
C670
1U_0603_10V4Z~D
1
HOST_DEBUG_TX
HOST_DEBUG_RX
RESET_OUT#
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#
G
BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#
2
@ C669
1U_0402_6.3V6K~D
2
thermal GND
VR_CAP[1]
VSS_RO
129
15mil
+5035_VSS 101
22
8mil
+VR_CAP
2
1
INSTANT_ON_SW#
3
121
21
44
65
83
116
104
4
52
VBAT
AGND
26
51
74
88
113
20
53
125
2
2
15mil
1+5035_AGND
2
C673
4.7P_0402_50V8C~D
1
C671
4.7U_0603_6.3V4Z~D
2
1
1
2
L39
BLM18AG121SN1D_0603~D
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[7]
VSS[8]
1
2
1
1
2
2
1
1
1
1
2
2
1
C675
27P_0402_50V8J~D
2
A
2
C674
22P_0402_50V8J~D
3
1
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
MASTER CLOCK
XTAL1
XTAL2
GPIO160/32KHZ_OUT
1
2
DELL PWR SW INF
<18> EC_32KHZ_OUT
R588
10_0402_5%~D
Y4
32.768K_12.5P_1TJS125DJ4A420P~D
MEC5035_XTAL2
4
1
1
2
GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
GPIO011/nSMI
GPIO061/LPCPD#
LDRQ#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/nEC_SCI
CLK_PCI_5035
DOCK_PWR_SW#
DDR_ON
<46>
RUNPWROK <37,41,47>
ICH_LAN_RST# <24>
20mA drive pins
SMBUS INTERFACE
HOST INTERFACE
Place closely pin 58
R550
100K_0402_5%~D
C1040
0.1U_0402_16V4Z~D
2
BC-LINK
122
124
117
D
R585
100_0402_5%~D
32 KHz
Clock
Same as Laguna
GPIO001
GPIO002
GPIO014/GPTP-IN7
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO020
GPIO26/GPTP-IN1
GPIO27/GPTP-OUT1
GPIO30/GPTP-IN2
GPIO31/GPTP-OUT2
GPIO032/GPTP-IN3
GPIO040/GPTP-OUT3
GPIO041
GPIO107
GPIO120
GPIO124/GPTP-OUT5
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
RC _ID
DDR_ON
RUNPWROK
POWER_SW#_MB <39,42>
+RTC_CELL
<18> DOCK_PWR_SW#
19
27
49
50
67
68
69
70
71
72
81
82
92
110
114
115
123
GENERAL PURPOSE I/O
FAN PWM & TACH
ACES_85204-06001~D
MEC5035_XTAL1
GPIO021/RC_ID
GPIO025/UART_CLK
VCC_PRWGD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO102/ECGP_SOUT
GPIO103/ECGP_SIN
GPIO104/UART_TX
GPIO105/UART_RX
GPIO106/nRESET_OUT
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
nFWP
JTAG INTERFACE
11
54
55
56
57
58
59
60
61
62
63
64
66
2
2
1K_0402_5%~D
C659
1U_0603_10V4Z~D
R579
10K_0402_5%~D
2
GPIO145/I2C1K_DATA/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#
GPIO022/BCM_B_CLK/V_CLK
GPIO023/BCM_B_DAT/V_DATA
GPIO024/BCM_B_INT#/V_FRAME
GPIO042/BCM_C_INT#
GPIO043/BCM_C_DAT
GPIO044/BCM_C_CLK
GPIO045/LSBCM_D_INT#
GPIO046/LSBCM_D_DAT
GPIO047/LSBCM_D_CLK
GPIO121/BCM_A_INT#
GPIO122/BCM_A_DAT
GPIO123/BCM_A_CLK
2
1
C918
4700P_0402_25V7K~D
MEC5035_XTAL1
1
0_0402_5%~D
102
103
105
106
107
23
24
25
35
36
37
38
39
40
85
86
87
2
1
C668
0.1U_0402_16V4Z~D
MEC5035_XTAL2
2
R587
SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC5035
IRQ_SERIRQ
PLTRST2#
CLK_PCI_5035
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
GPIO007/I2C1D_DATA/PS2_CLK0B
GPIO010/I2C1D_CLK/PS2_DAT0B
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO155/I2C1C_CLK/PS2_DAT1B
GPIO050/FAN_TACH1
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PWM0
GPIO054/PWM1
GPIO055/PWM2
GPIO056/PWM3
2
1
C667
0.1U_0402_16V4Z~D
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
BC_INT#_ECE1077
BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028
9
10
75
76
77
78
79
80
111
112
41
42
43
45
46
47
48
2
1
C666
0.1U_0402_16V4Z~D
R583
10K_0402_5%~D
1
2
3
4
5
6
R584
10K_0402_5%~D
R582
10K_0402_5%~D
R581
10K_0402_5%~D
G1
G2
1
2
3
4
5
6
R580
49.9_0402_1%~D
@ JP2
7
8
<24,29,31,36,37> IRQ_SERIRQ
<22,37> PLTRST2#
<6> CLK_PCI_5035
<23,29,36,37> LPC_LFRAME#
<23,29,36,37> LPC_LAD0
<23,29,36,37> LPC_LAD1
<23,29,36,37> LPC_LAD2
<23,29,36,37> LPC_LAD3
<24,29,31,37> CLKRUN#
<24> SIO_EXT_SCI#
BC_CLK_EMC4002
BC_DAT_EMC4002
BC_INT#_EMC4002
2
1
C665
0.1U_0402_16V4Z~D
+3.3V_ALW
<24> SIO_EXT_SMI#
<23> SIO_RCIN#
BREATH_LED#
ICH_ALW
KYBRD_BKLT_PWM
1
C664
0.1U_0402_16V4Z~D
HOST_DEBUG_RX
2
0_0402_5%~D
DOCK_POR_RST#
SUS_ON
C663
10U_0805_10V4Z~D
<39> BC_INT#_ECE1077
<39> BC_DAT_ECE1077
<39> BC_CLK_ECE1077
<37> BC_INT#_ECE5028
<37> BC_DAT_ECE5028
<37> BC_CLK_ECE5028
Molex_53261
B
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
2
C662
0.1U_0402_16V4Z~D
<35,42> BREATH_LED#
<40> ICH_ALW
<39> KYBRD_BKLT_PWM
R576
10K_0402_5%~D
R575
10K_0402_5%~D
MSDATA
MSCLK
1
R577
<39> CLK_TP_SIO
<39> DAT_TP_SIO
<35> CLK_KBD
<35> DAT_KBD
<35> CLK_MSE
<35> DAT_MSE
<43> PBAT_SMBDAT
<43> PBAT_SMBCLK
1
MISC INTERFACE
PS/2 INTERFACE
<18> BC_CLK_EMC4002
<18> BC_DAT_EMC4002
<18> BC_INT#_EMC4002
R574
100K_0402_5%~D
@ JDEG1
5 5
4 4
3 3
2 2
1 1
1
2
U36
<35> DOCK_POR_RST#
<40,41> SUS_ON
+3.3V_ALW
C660
0.1U_0402_16V4Z~D
C661
0.1U_0402_16V4Z~D
C
2
+RTC_CELL_VBAT
1
2
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
C1053
0.1U_0402_16V4Z~D
1
2
M_ON
1
1M_0402_5%~D
AUX_ON
2
2.7K_0402_5%~D
DDR_ON
2
100K_0402_5%~D
SUS_ON
2
100K_0402_5%~D
ICH_ALW
2
100K_0402_5%~D
DOCK_POR_RST#
2
1M_0402_5%~D
2
R561
1
R563
1
R564
1
R566
1
R568
1
R1046
1
2
R544
0_0402_5%~D
1
R541
1
+3.3V_ALW
+RTC_CELL
2
@ C658
1U_0402_6.3V6K~D
POWER_SW_IN#
<18> POWER_SW_IN#
2 CKG_SMBDAT
2.2K_0402_5%~D
2 CKG_SMBCLK
2.2K_0402_5%~D
2 BC_DAT_ECE5028
100K_0402_5%~D
1 BC_DAT_EMC4002
100K_0402_5%~D
1 BC_DAT_ECE1077
100K_0402_5%~D
1 DOCK_SMB_ALERT#
10K_0402_5%~D
2 LCD_SMBCLK
2.2K_0402_5%~D
2 LCD_SMBDAT
2.2K_0402_5%~D
2 PBAT_SMBDAT
2.2K_0402_5%~D
2 PBAT_SMBCLK
2.2K_0402_5%~D
1 LPC_LDRQ#_MEC5035
100K_0402_5%~D
2 CARD_SMBDAT
2.2K_0402_5%~D
2 CARD_SMBCLK
2.2K_0402_5%~D
1 HOST_DEBUG_TX
10K_0402_5%~D
1
R540
1
R542
1
R543
2
R545
2
R546
2
R547
1
R548
1
R549
1
R551
1
R552
2
@ R837
1
R838
1
R839
2
R911
D
1
2
+3.3V_ALW
INSTANT_ON_SW# <37,42>
SNIFFER_PWR_SW# <42>
@ U57
74AHC1G08GW_SOT353-5~D
1
0_0402_5%~D
MEC5035_XVTQFP128_14X14~D
1
2
L40
BLM18AG121SN1D_0603~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
EMC5035
Size
Document Number
Date:
Thursday, June 12, 2008
R ev
0.8
LA-3803P
Sheet
1
38
of
71
3
2
1
1
2
1
2
2
@
DAT_TP_SIO
1
2
1
2
D
DAT_TP_SIO <38>
CLK_TP_SIO
CLK_TP_SIO <38>
C683
10P_0402_50V8J~D
2
R595
4.7K_0402_5%~D
2
1
@
C682
10P_0402_50V8J~D
1
+5V_RUN
R594
4.7K_0402_5%~D
TP_CLK
C681
10P_0402_50V8J~D
2
L41
1
2
BLM18AG601SN1D_0603~D
1
2
L42
BLM18AG601SN1D_0603~D
TP_DATA
C680
10P_0402_50V8J~D
2
1
C679
0.1U_0402_16V4Z~D
1
C678
0.1U_0402_16V4Z~D
D
+3.3V_ALW
R1094
4.7K_0402_5%~D
+5V_RUN
R1093
4.7K_0402_5%~D
1
+5V_ALW
1
4
2
5
C
C
Power Switch for debug
JTP1
<38> BC_DAT_ECE1077
<38> BC_CLK_ECE1077
<38> BC_INT#_ECE1077
+3.3V_ALW
+3.3V_ALW
B
2
C771
0.1U_0402_16V4Z~D
1
TP_CLK
TP_DATA
+5V_RUN
+5V_ALW
+3.3V_RUN
<38> KYBRD_BKLT_PWM
<37> TP_DET#
Place close to
JTP1.5,6
KYBRD_BKLT_PWM
TP_DET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
G1
G2
<38,42> POWER_SW#_MB
POWER_SW#_MB
1
1
2
2
1
@ C684
100P_0402_50V8J~D
2
PWRSW1
@SHORT PADS~D
@ Place
1
1
2
B
on Top
2
PWRSW2
@SHORT PADS~D
TYCO_1-1775737-6
Place
on Bottom
@
2
1
@
2
@
A
D54
SD05.TCT_SOD323-2~D
D53
SD05.TCT_SOD323-2~D
1
TP_CLK
TP_DATA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place close to JTP1 connector
Title
Touch PAD/Int KB/LID
Size
4
3
http://hobi-elektronika.net
Rev
0.8
LA-3803P
Date:
5
Document Number
2
Thursday, June 12, 2008
Sheet
1
39
of
71
A
5
4
3
2
1
+5VRUN Source
4
2
2
<19,28,37,41,56> RUN_ON
2
3
RUN_ON_3V#
5
4
C692
4700P_0402_25V7K~D
R607
20K_0402_5%~D
1
C693
470P_0402_50V7K~D
C
1
1
+1.05V_VCCP Source
3
1
S
+15V_ALW
S
3
R614
20K_0402_5%~D
1
2
1
4
C697
470P_0402_50V7K~D
B
2
<37> 1.05V_RUN_ON
2
1
1
2
1
1
1
2
S
D
3
S
D
RUN_ON_3V# 2
G
3
1
2
1
1
1
2
S
D
2
G
3
S
D
2
G
3
1
2
1
D
2
G
3
1
2
1
1
2
1
3
S
RUN_ON_5V#
Q79
2N7002W-7-F_SOT323-3~D
3
1
2
3
4
+1.05V_VCCP
S
RUN_ON_1.05V# 2
G
@ Q80
@ R626
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
1
+3.3V_RUN
R625
39_0402_5%~D
2
+0.9V_DDR_VTT
@ Q78
@ R624
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
S
D
ALW_ON_3.3V# 2
G
@ Q77
@ R623
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
D
SUS_ON_3.3V# 2
G
+1.5V_RUN
@ Q76
@ R622
2N7002W-7-F_SOT323-3~D
1K_0402_5%~D
2
R621
470K_0402_5%~D
@ Q82
2N7002W-7-F_SOT323-3~D
@ R628
1K_0402_5%~D
6
2
2
+3.3V_ALW_ICH
@ Q81
2N7002W-7-F_SOT323-3~D
@ R627
1K_0402_5%~D
1
1
Q70B
2N7002DW-T/R7_SOT363-6~D
1
Q70A
2N7002DW-T/R7_SOT363-6~D
+5V_RUN
+3.3V_SUS
@
1
C698
4700P_0402_25V7K~D
Q74A
2N7002DW-T/R7_SOT363-6~D
@ R629
200K_0402_5%~D
5
Q74B
2N7002DW-T/R7_SOT363-6~D
N21917830
AUX_ON 2
5
+1.05V_VCCP
Discharg Circuit
ENAB_3VLAN <29>
2
R620
100K_0402_5%~D
AUX_ON
2
1
RUN_ON_1.05V#
R619
100K_0402_5%~D
<38>
1
2
D31
RB751V_SOD323-2~D
1
2
R618
0_0402_5%~D
2
1
2
D
2
G
Q67
NTMS4107NR2G_SO8~D
1
2
3
1
+3.3V_ALW2
1
1
D
2
G
R617
100K_0402_5%~D
4
2
Q68A
2N7002DW-7-F_SOT363-6~D
M_ON_3.3V#
C696
4700P_0402_25V7K~D
R613
100K_0402_5%~D
6
4
6
1
+3.3V_M
3
1
2
1
+1.05V_M
8
7
6
5
@
3
2
2
3
G
1
+1.05V_M
1
D
S
4
M_ENABLE
+15V_ALW
Discharg Circuit
@ Q71
2N7002W-7-F_SOT323-3~D
@ R615
75_0603_5%~D
2
1
+3.3V_ALW2
@ Q72
2N7002W-7-F_SOT323-3~D
@ R616
1K_0402_5%~D
6
5
2
1
Q68B
2N7002DW-7-F_SOT363-6~D
M_ON_3.3V# 5
+3.3V_M
R612
20K_0402_5%~D
2
Q66
SI3456BDV-T1-E3_TSOP6~D
C694
10U_0805_10V4Z~D
R611
100K_0402_5%~D
+3.3V_ALW
R610
100K_0402_5%~D
1
+15V_ALW
C695
10U_0805_10V4Z~D
+3.3VM Source
A
2
2
<37> 3.3V_RUN_ON
2
2
1
Q64A
2N7002DW-T/R7_SOT363-6~D
2
+3.3V_ALW2
M_ON
1
Q64B
2N7002DW-T/R7_SOT363-6~D
+3.3V_RUN
2
4
1
2
D30
RB751V_SOD323-2~D
1
2
R609
0_0402_5%~D
2
1
1
2
1
R608
100K_0402_5%~D
6
4
3
Q62A
2N7002DW-T/R7_SOT363-6~D
4
6
1
2
1
2
1
2
5
2
R606
100K_0402_5%~D
@
Q62B
2N7002DW-T/R7_SOT363-6~D
SUS_ON_3.3V#
C
1
R605
20K_0402_5%~D
SUS_ENABLE
Q61
NTMS4107NR2G_SO8~D
8
1
7
2
6
3
5
+3.3V_ALW
+3.3V_SUS
C690
10U_0805_10V4Z~D
R604
100K_0402_5%~D
+15V_ALW
C691
10U_0805_10V4Z~D
+3.3V_ALW2
Q60
STS11NF30L_SO8~D
8
1
7
2
6
3
5
R603
100K_0402_5%~D
+3.3V_ALW2
<38,45>
1
1
1
+3.3V_ALW
B
D
+3.3V_RUN Source
+3.3V_SUS Source
+15V_ALW
<38,41> SUS_ON
R600
20K_0402_5%~D
2
3
2
4
2
1
1
4
2
6
2
Q57A
2N7002DW-T/R7_SOT363-6~D
5
Q56A
2N7002DW-T/R7_SOT363-6~D
2
ICH_ALW
2
Q56B
2N7002DW-T/R7_SOT363-6~D
RUN_ON_5V#
C688
3300P_0402_50V7K~D
+5V_RUN
1
RUN_ENABLE
R601
20K_0402_5%~D
2
Q55
STS11NF30L_SO8~D
1
2
3
6
1
5
1
2
ALW_ENABLE
3
2
3
G
C687
10U_0805_10V4Z~D
1
4
Q57B
2N7002DW-T/R7_SOT363-6~D
ALW_ON_3.3V#
R599
100K_0402_5%~D
S
1
6
5
2
1
R597
100K_0402_5%~D
8
7
6
5
C689
2200P_0402_50V7K~D
R602
100K_0402_5%~D
<38>
1
Q54
+3.3V_ALW_ICH
SI3456BDV-T1-E3_TSOP6~D
R598
100K_0402_5%~D
+5V_ALW
C686
10U_0805_10V4Z~D
+3.3V_ALW2
+15V_ALW
1
+3.3V_ALW
D
+15V_ALW
D
+3.3V_ALW2
+3.3V_ALW_ICH Source
DC/DC Interface
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
POWER CONTROL
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
40
of
71
3
2
1
C
Q84
MMST3904-7-F_SOT323-3~D
1
A
8
P
P
8
+3.3V_ALW
Y
7
6
A
U39A
74LVC3G14DC_VSSOP8~D
+3.3V_ALW
2
Y
U39B
74LVC3G14DC_VSSOP8~D
1
C700
0.1U_0402_16V4Z~D
2
14
D
1
1
2
R636
0_0402_5%~D
<19,28,37,40,56> RUN_ON
2
14
3
E
U40A
74VHC08MTCX_NL_TSSOP14~D
IN1
OUT 3
IN2
+3.3V_ALW
P
2
R635
4.7K_0402_5%~D
1
2
2
B
C703
2200P_0402_50V7K~D
C699
0.1U_0402_16V4Z~D
2
G
2
1
1
7
3
2
1
1
1
2
B
2
R634
200K_0402_5%~D
C702
0.1U_0402_16V4Z~D
E
1
D32
RB751V_SOD323-2~D
1
Q83
MMBT3906WT1G_SC70-3~D
C
2
D
R633
10K_0402_5%~D
1
2
1
G
+5V_RUN
+3.3V_ALW
4
<56> 1.1V_GFX_PWRGD
2
+5V_ALW
1
0_0402_5%~D
1
0_0402_5%~D
1
0_0402_5%~D
1
0_0402_5%~D
R632
C701
100K_0402_5%~D 0.1U_0402_16V4Z~D
<45> 1.5V_RUN_PWRGD
<52,56> GFX_CORE_PWRGD
2
@ R630
2
R631
2
R808
2
@ R809
1
+3.3V_SUS
<18,37> 2.5V_RUN_PWRGD
G
4
4
5
E
R639
4.7K_0402_5%~D
1
2
2
B
1
C705
2200P_0402_50V7K~D
U40B
74VHC08MTCX_NL_TSSOP14~D
RUNPWROK
6
RUNPWROK <37,38,47>
G
IN2
C
+3.3V_ALW
Q86
MMST3904-7-F_SOT323-3~D
14
2
2
1
E
3
IN1
IN2
+3.3V_ALW
P
10
3.3V_5V_SUS_PWRGD 9
OUT
G
<38,40> SUS_ON
+3.3V_ALW
8
SUSPWROK <38>
U40C
74VHC08MTCX_NL_TSSOP14~D
7
1
2
R638
200K_0402_5%~D
C704
0.1U_0402_16V4Z~D
2
1
2
R637
1 10K_0402_5%~D
5
Q85
MMBT3906WT1G_SC70-3~D
B
1
OUT
C
2
D33
RB751V_SOD323-2~D
1
IN1
7
3
+3.3V_RUN
P
4
+3.3V_ALW
8
+3.3V_M
P
Y
G
A
5
1
3
4
U39C
74LVC3G14DC_VSSOP8~D
R640
100K_0402_5%~D
2
+3.3V_ALW
ICH_PWRGD#
ICH_PWRGD# <18>
12
IN2
1
IN1
RESET_OUT#
3
14
13
11
OUT
ICH_PWRGD
S
Q87
2N7002W-7-F_SOT323-3~D
2
G
U40D
74VHC08MTCX_NL_TSSOP14~D
7
<38> RESET_OUT#
IMVP_PWRGD
D
P
<24,37,47> IMVP_PWRGD
G
1
2
2
1
1
B
1
C
2
E
C
Q88
MMBT3906WT1G_SC70-3~D
D35
RB751V_SOD323-2~D
2
1
R643
200K_0402_5%~D
2
C707
0.1U_0402_16V4Z~D
R641
10K_0402_5%~D
1
2
2
C708
2200P_0402_50V7K~D
1
R642
200K_0402_5%~D
D34
RB751V_SOD323-2~D
2
1
3
+3.3V_SUS
C
ICH_PWRGD <10,24>
+3.3V_ALW
+3.3V_ALW
+3.3V_M
3
B
8
P
2
1
1
A
Y
G
2
D37
RB751V_SOD323-2~D
4
2
1
1
1
1
E
2
B
Q89
MMBT3906WT1G_SC70-3~D
R646
200K_0402_5%~D
2
C709
0.1U_0402_16V4Z~D
R644
10K_0402_5%~D
1
2
2
C710
2200P_0402_50V7K~D
1
R645
200K_0402_5%~D
D36
RB751V_SOD323-2~D
2
1
C
B
+3.3V_ALW
3
8
P
1
2
A
1
6
A
Y
G
2
D41
RB751V_SOD323-2~D
4
1
1
B
2
C
2
E
1
C713
0.1U_0402_16V4Z~D
1
2
Q91
MMBT3906WT1G_SC70-3~D
R653
200K_0402_5%~D
C714
0.1U_0402_16V4Z~D
C715
2200P_0402_50V7K~D
2
R652
200K_0402_5%~D
1
R651
10K_0402_5%~D
1
2
2
3.3V_M_PWRGD <18,38>
+3.3V_ALW
+3.3V_LAN
D40
RB751V_SOD323-2~D
2
1
7
U41A
74LVC3G14DC_VSSOP8~D
2
3.3V_LAN_PWRGD <38>
U41B
74LVC3G14DC_VSSOP8~D
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Power Good
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
41
of
71
2
<37> PWR_BTN_BD_DET#
1
1
@
1
D42
LTST-C191TBKT-5A BLU_0603~D
1
1
2
R_CAP_LED#
2
1K_0402_5%~D
1
2
WLAN LED solution for Blue LED
2
R_SCRL_LED#
2
1K_0402_5%~D
1
R655
2
2
+3.3V_ALW
1
1
U64
3
1
2
2
1
5
D43
LTST-C191TBKT-5A BLU_0603~D
4
Q145B
2N7002DW-7-F_SOT363-6~D
1
<37> SYS_LED_MASK#
1
1
C1060
1
Y
4
1
BREATH_LED#_R
0.1U_0402_16V4Z~D
2
O
3
Q102
DDTA114EUA-7-F_SOT323-3~D
1
1
+1.05V_M
2
0.1U_0402_16V4Z~D
1
+1.5V_RUN
2
0.1U_0402_25V4K~D
1
+PWR_SRC
2
0.1U_0402_25V4K~D
1
2
0.1U_0402_25V4K~D
1
1
D
+DOCK_PWR_BAR
2
0.1U_0402_25V4K~D
1
S
+PWR_SRC
2
0.1U_0402_25V4K~D
1
2
0.1U_0402_25V4K~D
1
2
0.1U_0402_25V4K~D
1
2
0.1U_0402_25V4K~D
1
2
0.1U_0402_25V4K~D
1
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
2
0.1U_0402_16V4Z~D
1
+3.3V_LAN
2
0.1U_0402_16V4Z~D
1
+GPU_CORE
2
0.1U_0402_16V4Z~D
1
+1.8V_RUN_GPU
2
0.1U_0402_16V4Z~D
1
+1.8V_MEM
2
0.1U_0402_16V4Z~D
1
+1.05V_M
2
0.1U_0402_16V4Z~D
1
+DOCK_PWR_BAR
C924
+3.3V_ALW
C925
C926
C927
C930
+1.05V_VCCP
C
+3.3V_RUN
R1002
1K_0402_5%~D
1
2
C935
BATT_BLUE_LED <19>
C936
+3.3V_RUN
C939
R1003
150_0402_5%~D
1
2
C940
BATT_YELLOW_LED <19>
MASK_BASE_LEDS#
74AHC1G08GW_SOT353-5~D
C950
+1.8V_MEM
+5V_ALW
C978
+PWR_SRC
B
Q134B
2N7002DW-7-F_SOT363-6~D
4
3 2
DDTA114EUA-7-F_SOT323-3~D
Q136
1
<37> SYS_LED_MASK#
+5V_ALW
R664
BREATH_BLUE_LED
2
1K_0402_5%~D
BREATH_BLUE_LED <19>
Q135B
2N7002DW-7-F_SOT363-6~D
4
3 2
DDTA114EUA-7-F_SOT323-3~D
Q137
MASK_BASE_LEDS#
1
A
R1001
BREATH_BLUE_LED_SNIFF
2
100_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
1
<37> SNIFFER_BLUE#
4
IN2
3
LID_CL#
IN1
1
SYS_LED_MASK# 1
2
G
<37> SYS_LED_MASK#
+5V_ALW
U65
P
5
A
0.1U_0402_16V4Z~D
1
C919
C923
MASK_BASE_LEDS# 2
G
+3.3V_ALW
2
NC
A
6
2
2
U42
NC7SZ04P5X_NL_SC70-5~D
1
5
P
<35,38> BREATH_LED#
C1061
1
2
0.1U_0402_16V4Z~D
+3.3V_ALW
Q100
DDTA114EUA-7-F_SOT323-3~D
2
G
2
1
3
3
<37> SNIFFER_YELLOW#
YEL
LTST-C155TBJSKT_Blue/YEL~D
5
+3.3V_ALW
X
0
1
1
6
LID_CL#
0
1
1
Q135A
2N7002DW-7-F_SOT363-6~D
SYS_LED_MASK#
Q134A
2N7002DW-7-F_SOT363-6~D
2
LED Circuit Control Table
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened)
2
C871
+3.3V_ALW
WPAN LED solution for Blue LED
+3.3V_ALW
0.1U_0402_16V4Z~D
1
3
NC7SZ04P5X_NL_SC70-5~D
1
G
1
R661
WPAN_LED 2
2
1K_0402_5%~D
S
1
3
Q142
2N7002W-7-F_SOT323-3~D
D
2
4
S
G
MASK_BASE_LEDS#
Y
2
3
A
2
BAT1_LED# 2
G
<38> BAT1_LED#
0.1U_0402_16V4Z~D
1
C933
Q140
2
2
C870
+3.3V_RUN
+3.3V_ALW
R1005
100K_0402_5%~D
BAT1_LED
5
P
D
S
1
NC
1
Q94
DDTA114EUA-7-F_SOT323-3~D
3
1
3
0.1U_0402_16V4Z~D
D
R666
150_0402_5%~D
1
2
2
0.1U_0402_16V4Z~D
1
C929
3
2
R660
10K_0402_5%~D
+3.3V_ALW
2
2
C922
R999
100K_0402_5%~D
C1059
1
1
+3.3V_ALW
+5V_RUN
0.1U_0402_16V4Z~D
1
C928
3
+3.3V_RUN
3
R1000
100K_0402_5%~D
Q145A
2N7002DW-7-F_SOT363-6~D
6
2
DDTA114EUA-7-F_SOT323-3~D
WWAN LED solution for Blue LED
R1007
100K_0402_5%~D
1
2
Q101
DDTA114EUA-7-F_SOT323-3~D
1
+3.3V_ALW
1
3
2
1
BATT_YELLOW4
5
2
2
G
G
2 W AN_LED
1K_0402_5%~D
D61
LTST-C191TBKT-5A BLU_0603~D
Q95
2N7002W-7-F_SOT323-3~D
1
<37> SYS_LED_MASK#
1
<34> LED_WPAN_OUT#
3
3
5
Q144B
2N7002DW-7-F_SOT363-6~D
2 BATT_BLUE 2
1K_0402_5%~D
Q139
DDTA114EUA-7-F_SOT323-3~D
2
3
2N7002W-7-F_SOT323-3~D
2
C921
3
1
1
Q115
PDTA114EU_SC70-3~D
R125
1
MASK_BASE_LEDS# 2
G
Q150
2N7002W-7-F_SOT323-3~D
6
1
Q143
U63
NC7SZ04P5X_NL_SC70-5~D
4
5
1
P
3
4
Y
G
3
A
2
MASK_BASE_LEDS#
B
1
R665
+5V_ALW
R1004
100K_0402_5%~D
BAT2_LED
0.1U_0402_16V4Z~D
1
C851
D46
BLUE
D
1
0.1U_0402_16V4Z~D
S
D
S
3
<34> LED_WWAN_OUT#
<38> BAT2_LED#
BAT2_LED# 2
NC
1
2
+5V_RUN
R206
100K_0402_5%~D
Q116
2N7002W-7-F_SOT323-3~D
2
2
C803
D59
LTST-C191TBKT-5A BLU_0603~D
+5V_ALW
2
0.1U_0402_16V4Z~D
1
C611
1
Q99
DDTA114EUA-7-F_SOT323-3~D
2
C610
Battery LED
C1058
1
C356
+5V_ALW
1
2
Q144A
2N7002DW-7-F_SOT363-6~D
+3.3V_RUN
@ FD6
1
FIDUCIAL MARK~D
1
1
R1006
100K_0402_5%~D
1
2
+5V_ALW
C
@
D58
LTST-C191TBKT-5A BLU_0603~D
+5V_ALW
1
D45
LTST-C191TBKT-5A BLU_0603~D
+3.3V_ALW
@
D57
LTST-C191TBKT-5A BLU_0603~D
R_NUM_LED#
2
1K_0402_5%~D
1
R596
1
G
2
@ FD5
1
Keyboard Status LED
Q122
DDTA114EUA-7-F_SOT323-3~D
2 WLAN_LED
1K_0402_5%~D
1
R663
@
1
<37> SCRL_LED#
Q97
PDTA114EU_SC70-3~D
D
FIDUCIAL MARK~D
@ R1039
0_0402_5%~D
2
MASK_BASE_LEDS#
H18
H19
@H_2P5N @H_3P0N
3
2
@ FD4
1
@
H16
@H_2P6
@
3
1
D67
SDM10U45-7_SOD523-2~D
2
1
R556
Q121
DDTA114EUA-7-F_SOT323-3~D
3
3
1
2
D
S
1
@
FIDUCIAL MARK~D
3
3
2
<37> NUM_LED#
3
@
Q120
DDTA114EUA-7-F_SOT323-3~D
+5V_RUN
Q98
2N7002W-7-F_SOT323-3~D
@
@ FD3
1
1
2
CAP_LED#
+3.3V_WLAN
<34> LED_WLAN_OUT#
FIDUCIAL MARK~D
CLIP2
EMI_CLIP
FIDUCIAL MARK~D
@
<37>
R662
100K_0402_5%~D
1
@
H13
H14
H15
@H_2P5 @H_3P1X2P1 @H_5P2
+5V_ALW
HDD LED solution for Blue LED
H12
@H_4P2
2
2
1
GND
@
H11
@H_2P5
Q141
2N7002W-7-F_SOT323-3~D
R659
2 SATA_LED
1K_0402_5%~D
@
H10
@H_3P8
FIDUCIAL MARK~D
@ FD2
1
1
1
@
H9
@H_3P0
GND
TYCO_1-1734820-2
MASK_BASE_LEDS#
@
@ FD1
1
CLIP1
EMI_CLIP
1
2
G
D
WIRELESS_ON#/OFF
S NIFFER_PWR_SW#
SN IFFER_YELLOW
SNIFFER_BLUE
PWR_BTN_BD_DET#
<37> WIRELESS_ON#/OFF
<38> SNIFFER_PWR_SW#
@
H7
@H_3P0
Fiducial Mark
EMI CLIP
1
D
S
Q93
2N7002W-7-F_SOT323-3~D
1
@
H6
@H_3P0
1
Q92
DDTA114EUA-7-F_SOT323-3~D
1SATA_ACT# 2
3
<23> SATA_ACT#_R
<38,39> POWER_SW#_MB
<37,38> INSTANT_ON_SW#
1
3
2
H5
@H_3P0
1
LID_CL#
C685
0.1U_0402_16V4Z~D
2
<37>
LID_CL#
BREATH_BLUE_LED_SNIFF
12
11
10
9
8
7
6
5
4
3
2
1
H4
@H_3P0
1
+3.3V_ALW
R654
10K_0402_5%~D
GND
GND
12
11
10
9
8
7
6
5
4
3
2
1
H3
@H_3P0
1
1
+5V_RUN
1
H2
@H_3P0
1
+3.3V_RUN
H1
@H_3P0
1
JSNIF1
14
13
1
3
1
4
1
5
1
R667
1
R668
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
SN IFFER_YELLOW
2
220_0402_5%~D
http://hobi-elektronika.net
SNIFFER_BLUE
2
1K_0402_5%~D
4
3
2
Title
PAD and Standoff
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
42
of
71
5
4
3
2
1
+COINCELL
1
COIN RTC Battery
PR215
1K_0402_5%~D
2
Z4012
1
PR7
100_0402_5%~D
1
2
Z4304
Z4305
Z4306
PR8
100_0402_5%~D
1
2
PR9
100_0402_5%~D
1
2
PBAT_SMBCLK <38>
PBAT_SMBDAT <38>
PR10 @
100_0402_5%~D
1
2
PBAT_ALARM#
2
PBATT+
PAD-OPEN 4x4m
3
BAT54CW_SOT323~D
PBAT_PRES#
PC201
1U_0603_10V6K~D
<37>
PQ61
FDN338P_NL_SOT23-3~D
1
2
1
3
DOCK_SMB_ALERT# <35,38>
2
2
PD32
RB751V-40_SOD323~D
C
3
PBATT1
1
PC4
2200P_0402_50V7K~D
2
1
11
10
9
8
7
6
5
4
3
2
1
PC3
0.1U_0603_25V7K~D
2
1
SUYIN_200275MR009G50PZR
GND
GND
9
8
7
6
5
4
3
2
1
PD24
PJP12
1
PD8
DA204U_SOT323~D
2
DA204U_SOT323~D @
+3.3V_ALW
PR6
10K_0402_1%~D
2
1
1
PD6
PD7
DA204U_SOT323~D
@
1
@
1
1
PD5
DA204U_SOT323~D
D
4
5
+RTC_CELL
PL2
FBMA-L18-453215-900LMA90T_1812~D
1
2
@
1
2 G1
3 G2
MOLEX_53398-0371~D
2
3
2
3
2
3
2
3
2
ESD Diodes
Primary Battery Connector
JRTC1
1
2
3
+COINCELL
<23> RTC_BAT_DET_R#
+3.3V_RTC_LDO
+3.3V_ALW
1
D
C
DCIN_CBL_DET# <37>
PR11
2.2K_0402_5%~D
1
2
2
3
1
1
NC
6
V+
5
+5V_ALW
COM
4
PS_ID
GPIO_PSID_SELECT <37>
<38>
2
@
B
1
2
3
3
PD11
DA204U_SOT323~D
1
2
G
+5V_ALW
PR17
1
@
2
PSID_DISABLE# <37>
10K_0402_5%~D
2
1
2
PC9
10U_1206_25V6M~D
PR19
4.7K_0805_5%~D
2
1
PC8
0.1U_0603_25V7K~D
2
1
PR22
22K_0402_5%~D
2
1
1
PR21
PC7
0.1U_0603_25V7K~D
2
1
PC6
0.1U_0603_25V7K~D
2
1
4
1
PR16
1M_0402_5%~D
2
+DC_IN_SS
A
PR283
100K_0402_5%~D
1
2
D
S
1
2
G
DELL CONFIDENTIAL/PROPRIETARY
NB_AC_OFF <37,48,49>
Compal Electronics, Inc.
Title
PC11
0.1U_0603_25V7K~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
5
1
PQ4A
IMD2AT-108_SC74-6~D
<49> NB_AC_OFF_BJT
3
PQ5
RHU002N06_SOT323
1
@
http://hobi-elektronika.net
5
3
GND
IN
TS5A63157DCKR_SC70-6~D
E
DC_IN+ Source
4
1M_0402_5%~D
3
2
@
PL5
FBMJ4516HS720NT_1806~D
1
2
PC65
0.1U_0603_25V7K~D
2
1
PQ4B
IMD2AT-108_SC74-6~D
6
MOLEX_87437-0763
A
NB_PSID_TS5A63157
NO
8
7
6
5
+D C_IN
@
2
PC5
0.022U_0603_50V7K
1
2
1
2
3
2
1
PR20
0_0402_5%~D
+ DCIN_JACK
1
PD12
VZ0603M260APT_0603
PC10
0.1U_0603_25V7K~D
2
1
-D CIN_JACK
PC66
0.1U_0603_25V7K~D
2
1
1
2
3
4
5
6
7
PQ2
FDS6679AZ_SO8~D
+DC_IN
PL4
FBMJ4516HS720NT_1806~D
1
2
1
2
3
4
5
6
7
2
1
@
PJPDC1
1
2
PC254
0.47U_0402_6.3V6K
1
2
0_0402_5%~D
PU1
<35> DOCK_PSID
+5V_ALW
PQ3
MMST3904-7-F_SOT323~D
2
B
PR18
15K_0402_1%~D
1
2
1
PR67
PQ1
FDV301N_SOT23~D
C
@
PD10
SM24_SOT23
@
3
1
3
2
1
2
3
PD13
DA204U_SOT323~D
PR14
100K_0402_1%~D
1
2
1
+3.3V_ALW
PR13
33_0402_5%~D
1
2
+3.3V_ALW
PR15
10K_0402_1%~D
D
PL3
BLM18BD102SN1D_0603~D
2
1
NB_PSID
B
PR12
1
2
0_0402_5%~D
S
@
PD9
DA204U_SOT323~D
+5V_ALW
2
PC266
1500P_0402_50V7K~D
<35,37,49> SLICE_BAT_PRES#
4
3
2
+DCIN
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3801P
Sheet
1
43
of
71
5
4
3
2
1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D
D
PJP14
1
+PWR_SRC
2
PC64
10U_1206_25V6M~D
2
1
PC15
10U_1206_25V6M~D
2
1
PC14
10U_1206_25V6M~D
2
1
PC13
0.1U_0805_50V7K
2
1
PC12
2200P_0402_50V7K~D
2
1
5
6
7
8
D
D
D
D
2
1
2
4
1
PQ9
FDS6676AS_NL_SO8~D
PC251
1000P_0603_50V7K
PR276
2.2_1206_1%
2
+3.3V_ALW_LGATE
PC30
330U_D3L_6.3VM_R25~D
1
GNDA_3V5V
+3.3V_ALWP
3.0UH_HMP1362-3R0-R_17A_20%~D
PC32
0.1U_0402_10V7K~D
2
1
3
2
1
PL7
PR39
0_0402_5%~D
2
1
2
PC28
0.1U_0603_25V7K~D
1
NC
S
S
S
GNDA_3V5V
C
G
5
6
7
8
8
7
6
5
4
3
2
1
LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF
PR37
2.2_0603_1%~D
+3.3V_ALW_BOOT1
2
+5V_ALW_LGATE
2
4
PQ7
FDS8880_NL_SO8~D
3
2
1
1
2
3
PR277
2.2_1206_1%
GNDA_3V5V
PR36
1_0603_5%~D
1
2 +5V_ALW_BOOT
1
2 PR33 0_0402_5%~D
1
POK2
EN_3V_5V
+3.3V_ALW_UGATE
+3.3V_ALW_PHASE
2
2
1
4
32
31
30
29
28
27
26
25
PR31
237K_0402_1%
1
2
BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2
FDS6676AS_NL_SO8~D
1000P_0603_50V7K
@
PAD
1
PQ8
33
PC27
0.1U_0603_25V7K~D
2
1
8
7
6
5
2
@ PR30
0_0603_5%~D@
17
18
19
20
21
22
23
24
S
S
S
3.0UH_HMP1362-3R0-R_17A_20%~D
PR28
@ PR29
0_0603_5%~D
BYP
REFIN2
OUT1
ILIM2
FB1
OUT2
PU2
ILIM1 ISL6236IRZA_QFN32~D SKIP#
POK1
POK2
EN1
EN2
UGATE1
UGATE2
PHASE1
PHASE2
3.3 Volt +/-5%
Thermal Design Current: 7.20A
Peak current: 10.29A
OCP min: 13A
0_0402_5%~D
2
9
10
11
12
13
14
15
16
EN_3V_5V
+5V_ALW_UGATE
+5V_ALW_PHASE
GNDA_3V5V
2
PR35
0_0402_5%~D
2
1
PC24
0.1U_0603_25V7K~D
1
2
PC25
0.1U_0402_10V7K~D
2
1
EN_3V_5V
PR27
0_0402_5%~D
1
2
1
PC20
4.7U_0805_6.3V6K
2
1
PR26
@ 0_0402_5%~D
1
2
+5V_ALWP
PR32
187K_0402_1%~D
1
2
POK1
GNDA_3V5V
PC23
1U_0603_10V6K~D
2
1
PC22
0.1U_0603_25V7K~D
2
1
PC21
0.1U_0603_25V7K~D
2
1
+3.3V_ALW2
GNDA_3V5V
1
2
3
NC
PR34
0_0603_5%~D
1
2
PL6
PC245
PR38
0_0603_5%~D
1
2
PC31
0.1U_0402_10V7K~D
2
1
PC29
330U_D3L_6.3VM_R25~D
PR25
10_0603_5%~D
2
1
PAD-OPEN1x1m
@
4
+5V_ALWP
2
@
@
PC26
0.1U_0402_10V7K~D
2
1
8
7
6
5
D
D
D
D
PQ6
FDS8880_NL_SO8~D
G
+
+5V_VCC1
2
1
C
1
PJP15
1
+5V_ALW2
GNDA_3V5V
5 Volt +/-5%
Thermal Design Current:6.59A
Peck current: 9.41A
OCP min: 11.3A
1
PR24
0_0805_5%
1
2
PR23
0_0805_5%
1
2
PC63
10U_1206_25V6M~D
2
1
PC19
10U_1206_25V6M~D
2
1
PC18
10U_1206_25V6M~D
2
1
PC16
2200P_0402_50V7K~D
2
1
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 4.7U_HMU1356-4R7-R_10A(DELTA)
PC17
0.1U_0805_50V7K
2
1
PAD-OPEN 4x4m
VOUT1=5V
L=4.7uF
Fsw=400KHz
D=0.265
Output Ripple Current=1.97A
Output Ripple Voltage=1.97A*25mOhm=49.37mV)
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
1
+
2
@
GNDA_3V5V
PC36
0.1U_0603_25V7K~D
1 1
2
2
2
+3.3V_ALW
PAD-OPEN1x1m
GNDA_3V5V @
PD16
BAT54CW_SOT323~D
3
1
+15V_ALWP
(100mA,20mils ,Via NO.=1)
@
PJP18
+5V_ALW
ALW_PWRGD_3V_5V <38,46>
PR46
200K_0402_1%~D
2
1
PC37
0.1U_0603_25V7K~D
2
1
2
PAD-OPEN1x1m
2
2
POK1
PJP17
1
Component select
Input CAP 10uF_1206_25V *2
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
Inductor 3.0U_HMP1362-3R0-R_17A(DELTA)
PR43
0_0402_5%~D
2
1
PR45
0_0402_5%~D
2
1
+15V_ALW
+5V_ALWP
3
BAT54SW-7-F_SOT323-3~D
B
PR47
39.2K_0402_1%~D
1
2
<18> THERM_STP#
@
POK2
PD15
PR44
200K_0402_5%
1
2
<38> ALWON
PR42
2K_0402_5%~D
2
1
VOUT2=3.3V
L=3.0uF
Fsw=500KHz
D=0.176
Output Ripple Current=1.84A
Output Ripple Voltage=1.84A*25mOhm=46.05mV
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
+3.3V_ALW
PR41
100K_0402_1%~D
1
2
PD14
BAT54SW-7-F_SOT323-3~D
PJP16
1
PR40
100K_0402_1%~D
1
2
3
GNDA_3V5V
PC34
1U_0603_10V6K~D
2
1
B
PC33
0.1U_0603_25V7K~D
1 1
2
2
1
PC35
0.1U_0603_25V7K~D
2
1
+5V_ALWP
+5V_ALW2
GNDA_3V5V
PAD-OPEN 4x4m
A
A
GNDA_3V5V
PJP19
+3.3V_ALWP
1
2
+3.3V_ALW
PAD-OPEN 4x4m
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://hobi-elektronika.net
5
4
3
2
DC/DC +3V/ +5V
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
44
of
71
5
4
3
2
1
+1.5V_RUN / +1.05V_M/ +3.3V_RTC_LDO
+DC2_PWR_SRC
PJP20
1
+PWR_SRC
2
1
+1.05V_MP
3
2
3
2
1
+
2
1
+
2
PC53
0.1U_0402_10V7K~D
1
2
1
PC52
10U_1206_6.3V7K
2
1
PR279
2.2_1206_1%
PC51
330U_D2E_2.5VM_R9
1
2
1
1000P_0603_50V7K
GNDA_1P5V_1P05V
1.05V_LGATE
+5V_ALW
@
Component select
Input CAP 10uF_1206_25V
Output Cap 220U_D2_4VM_R15(NEC_PSLV0G227M)
H_MOSFET SI4800BDY
L_MOSFET SI4810BDY(16/20mOhm@4.5V, 6A)
Inductor 3.3U_MPL73-3R3_6A(DELTA)
PC60
1U_0603_10V6K~D
2
1
PR66
100K_0402_1%~D
1
2
PR65
100K_0402_1%~D
2
1
+3.3V_SUS +3.3V_ALW
@ PR63
10_0603_5%~D
2
1
Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2.5VM_R9*2(Sanyo2R5TPE330M9)
H_MOSFET SI4682DY
L_MOSFET SI4362DY(4.2/5.5mOhm@4.5V, 15A)
Inductor 0.88U_MPC1040LR88_17A(NEC_TOKIN)
GNDA_1P5V_1P05V
POK2
1.05V_M_PWRGD <38>
POK1
1.5V_RUN_PWRGD <41>
PJP21
1
EN1
PJP24
2
+1.5V_RUN
B
VOUT2=1.05V
L=0.88uF
Fsw=300KHz
D=0.057
Output Ripple Current=3.88A
Output Ripple Voltage=3.88A*4.5mOhm=17.44mV
Input Ripple Current=TDC*(D*(1-D))^0.5=2.53A
+5V_VCC2
PC59
1U_0603_10V6K~D
2
1
VOUT1=1.5V
L=3.3uF
Fsw=200KHz
D=0.081
Output Ripple Current=2.15A
Output Ripple Voltage=2.15A*15mOhm=32.27mV
Input Ripple Current=TDC*(D*(1-D))^0.5=0.97A
1
PC50
330U_D2E_2.5VM_R9
4
PC247
2
5
6
7
8
PL8
1.4UH_HMU1350-1R4PF_15A_20%~D
B
+1.5V_RUN_P
C
PR62
2.2_0603_1%~D
1
2
GNDA_1P5V_1P05V
A
PC44
2200P_0402_50V7K~D
2
1
PC43
0.1U_0603_25V7K~D
2
1
1
PC42
10U_1206_25V6M~D
2
1
2
SI4682DY-T1-E3_SO8~D
PQ10
5
6
7
8
D
D
D
D
4
3
2
1
1.05 Volt +/-5%
Thermal Design Current: 7.32A
Peack current: 10.45A
OCP min: 13.8A
1
REFIN2_1_05
@
1
2
PR56 187K_0402_1%~D
GNDA_1P5V_1P05V
PR58 2 0_0402_5%~D
1
GNDA_1P5V_1P05V
POK2
EN2
1.05V_UGATE
1.05V_PHASE
SI4362DY-T1-E3_SO8~D
PQ12
1
PC49
0.1U_0402_10V7K~D
1
2
LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF
1.5V_LGATE
GNDA_1P5V_1P05V
PC58
0.1U_0603_25V7K~D
1
2
2
S
S
S
GNDA_1P5V_1P05V
PR61
1_0603_5%~D
1
2
@
1
@ PR52
0_0603_5%~D
G
S
S
S
2
PR51
0_0402_5%~D
2
8
7
6
5
4
3
2
1
4
32
31
30
29
28
27
26
25
BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2
GNDA_1P5V_1P05V
BYP
REFIN2
OUT1
ILIM2
FB1
OUT2
ILIM1
SKIP#
PU3
POK1 ISL6236IRZA_QFN32~DPOK2
EN1
EN2
UGATE1
UGATE2
PHASE1
PHASE2
PAD
9
10
11
12
POK1
13
EN1
14
1.5V_UGATE 15
1.5V_PHASE 16
GNDA_1P5V_1P05V
17
18
19
20
21
22
23
24
8
7
6
5
D
D
D
D
PC47
0.01U_0402_25V7K~D
2
1
PR54
0_0402_5%~D
1
2
@
PR57
187K_0402_1%~D
1
2
1
2
3
2
G
PR53
@ 0_0402_5%~D
1
2
2
1
PR55
@ 0_0603_5%~D
33
1
GNDA_1P5V_1P05V
1
2
3
PR278
2.2_1206_1%
@
PQ13
SI4812BDY-T1-E3_SO8~D
1
1
1000P_0603_50V7K
2
PR59
0_0603_5%~D
1
2
PC246
PR60
0_0603_5%~D
1
2
+
2
PC56
0.1U_0402_10V7K~D
1
2
1
PC55
10U_1206_6.3V7K
2
1
PC54
330U_D2E_2.5VM_R9
PL9
3.3UH_MPLC0730L3R3_6.5A_20%~D
2
1
4
+3.3V_RTC_LDO
PR50
0_0402_5%~D
PC46
0.1U_0603_25V7K~D
REF 1
2
GNDA_1P5V_1P05V
PC57
0.1U_0603_25V7K~D
+1.5V_RUN_P
PC48
0.1U_0402_10V7K~D
C
2
PQ11
SI4800BDY-T1_SO8~D
1.5 Volt +/-5%
Thermal Design Current: 2.18A
Peak current: 3.12A
OCP min: 4.3A
8
7
6
5
1
2
+5V_VCC2
PC41
10U_1206_25V6M~D
PC45
PR49
0.1U_0603_25V7K~D0_0805_5%~D
1
2
1
2
PR48
0_0805_5%~D
1
2
PC40
2200P_0402_50V7K~D
2
1
PAD-OPEN 4x4m
PC39
0.1U_0603_25V7K~D
2
1
D
PC38
10U_1206_25V6M~D
2
1
D
+3.3V_ALW
@ PR244
100K_0402_1%~D
2
1
PAD-OPEN 4x4m
EN2
1.5V_RUN_ON <37>
2
PJP23
1
1
+1.05V_MP
PR64
0_0402_5%~D
1
2
PAD-OPEN1x1m
M_ON
GNDA_1P5V_1P05V
<38,40>
2
PAD-OPEN 4x4m
PJP22
2
+1.05V_M
A
PAD-OPEN 4x4m
@
DELL CONFIDENTIAL/PROPRIETARY
OK to Short if CAD
System can Support
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://hobi-elektronika.net
4
3
2
+1.5V_RUN / +1.05V_VCCP
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
45
of
71
5
4
3
2
1
+1.8VSUSP/ +0.9V_DDR_VTT
D
D
DDR2 Termination
+DDR_PWR_SRC
GNDA_DDR
18
DH
19
LX
26
2
22
28
AVDD
17
C
5
POK2
6
SHDN
27
STBY
7
VTTI
13
REFIN
14
PGND2
11
+1.8VSUSP_L
2
VIN
POK1
1.8V_SUS_PWRGD <38>
DDR_ON
<38>
23
PGND1
16
VOUT
4
ISL88550A_TQFN28~D
1
PC232
10U_0805_6.3V6M~D
2
2
SS
GNDA_DDR
12
VTTS
9
VTTR
10
+0.9V_DDR_VTTP
1
2
1
2
1
2
Design current 0.7A for +0.9V_DDR_VTTP
Peak current 1A for +0.9V_DDR_VTTP
@
+V_DDR_MCH_REF
PC239
1000P_0402_50V7K~D
@
B
GNDA_DDR
2
1
VOUT=1.8V
L=1.4uF
Fsw=300KHz
D=0.097
Output Ripple Current=3.96A
Output Ripple Voltage=3.96A*7.5mOhm=29.7mV
Input Ripple Current=TDC*(D*(1-D))^0.5=2.52A
1
1
2
PR259
59K_0402_1%~D
B
8
ILIM
4
ISL88550_ILIM
+1.8V_SUSP
PC234
0.1U_0402_10V7K~D
1
PC238
0.22U_0402_6.3V 5K~D
REF
2
ISL88550_AVDD
PR255
100K_0402_1%~D
1
2
1
@
PR257
0_0402_5%~D
1
2
2
PR256
17.4K_0402_1%~D
VTT
TON
2
1
ISL88550_REF 3
FB
GND
1
24
15
SKIP
ISL88550_FB
PR254
@ 0_0402_5%~D
2
1
25
@
PR258
0_0402_5%~D
1
2
1
2
3
PR280
2.2_1206_1%
0.9V_DDR_VTT_ON <37>
+1.8V_SUSP
PR253
20_0603_1%~D
ISL88550_REFIN
2
1
PC235
10U_0805_6.3V6M~D
FDS6676AS_NL_SO8~D
1
2
PQ53
1000P_0603_50V7K
PR251
0_0402_5%~D
2
1
DL
GND
21
29
1
ISL88550_LX
2
2
PC233
1000P_0402_50V7K~D
2
1
1
+
PC248
PR252
27.4K_0402_1%
1
2
2
1
2
+
PC231
0.1U_0402_10V7K~D
1
PC230
330U_D2E_2.5VM_R15~D
PC229
330U_D2E_2.5VM_R15~D
8
7
6
5
1
BST
PC237
10U_0805_6.3V6M~D
1
2
3
ISL88550_DH
20
PC236
10U_0805_6.3V6M~D
3
S
S
S
1.4UH_HMU1350-1R4PF_15A_20%~D
PC228
0.22U_0603_10V7K~D PR250
1
2
2
1
1_0603_5%~D
4
TP0
G
VDD
PU16
PL20
OVP/ UVP
PQ52
FDS8880_NL_SO8~D
D
D
D
D
8
7
6
5
PR248
100K_0402_1%~D
1
2
1
2
PC227
ISL88550_AVDD
2
PR249
0_0402_5%~D
1
2
1U_0603_10V6K~D
PC226
4.7U_0805_6.3V6K
2
1
@
PR246 @
0_0402_5%~D
GNDA_DDR
C
+1.8V_SUSP
+3.3V_ALW
ALW_PWRGD_3V_5V
PR247
20K_0402_5%~D
1
2
1.8 Volt +/-5%
Thermal Design Current:6.10A
Peck current: 8.72A
OCP min: 9.85A
<38,44>
1
1
2
2
+5V_ALW
@ PR245
2
1
10_1206_5%~D
PD26
RB751V-40_SOD323~D
2
1
PC225
2200P_0402_50V7K~D
2
1
1
PC224
0.1U_0603_25V7K~D
2
1
PC222
10U_1206_25V6M~D
PC223
10U_1206_25V6M~D
@ PJP41
PAD-OPEN 4x4m
1
2
+PWR_SRC
PC240
1U_0603_10V6K~D
GNDA_DDR
PJP42
GNDA_DDR
GNDA_DDR
2
1
PAD-OPEN1x1m
GNDA_DDR
Component select
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2.5VM_R15*2(Sanyo_2R5TPE330MF)
H_MOSFET FDS8880
L_MOSFET FDS6676AS(4.2/5.5mOhm@4.5V, 15A)
Inductor 1.4U_HMU1350-1R4PF_15A(DELTA)
@
PJP43
PAD-OPEN 4x4m
1
2
+1.8V_SUSP
@
PJP44
PAD-OPEN 4x4m
1
2
+1.8V_MEM
@
A
A
PJP45
+0.9V_DDR_VTTP
2
1
DELL CONFIDENTIAL/PROPRIETARY
+0.9V_DDR_VTT
PAD-OPEN 2x2m~D
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
+1.8VSUSP/ +0.9V_DDR_VT
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
46
of
71
5
4
3
2
1
GND
4
2
1
@
7
PC87
100U_25V_M~D
PC88
100U_25V_M~D
PC89
100U_25V_M~D
2
1
PC94
10U_1206_25V6M~D
2
1
PC93
10U_1206_25V6M~D
PC92
2200P_0402_50V7K~D
2
1
2
PR271
PC91
2.4_0805_1%~D
0.1U_0603_25V7K~D
2
1
5
6
7
8
PC98
0.22U_0603_10V7K~D
2
1
PR88
10_0402_1%~D
1
2
PR90
10K_0402_1%~D
1
2
1
PR269
PC99
1500P_0603_25V7K~D
2
1
1
2
2.4_0805_1%~D
2
PQ18
1
PR92
0_0402_5%~D
VSUM
1 @
8
PWM PHASE
7
3
GND
4
@
@
2
1
PC104
10U_1206_25V6M~D
PC103
2200P_0402_50V7K~D
2
1
PC105
10U_1206_25V6M~D
2
1
PC109
0.22U_0603_10V7K~D
2
1
PR106
10_0402_1%~D
D
2
PR111
7.68K_0805_1%~D
PR112
0_0402_5%~D
2
VSUM
VO
PC114
10U_1206_25V6M~D
2
1
PC113
10U_1206_25V6M~D
2
1
@
C
PL15
0.45UH_ETQP4LR45XFC_25A_20%~D
<18>
3
+VCC_CORE
2
4
2
PR128
10_0402_1%~D
PC125
0.22U_0603_10V7K~D
2
1
B
1
PR133
10K_0402_1%~D
1
2
PR134
7.68K_0805_1%~D
1
@
1
1
PR270
2
PHASE3
PR135
0_0402_5%~D
VSUM
VO
DELL CONFIDENTIAL/PROPRIETARY
A
Compal Electronics, Inc.
Title
GNDA_VCORE
+VCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://hobi-elektronika.net
6
+VCC_CORE
2
2
2
G
@
2
1
3
PR109
10K_0402_1%~D
1
2
2.4_0805_1%~D
2
PC126
1500P_0603_25V7K~D
2
1
1
LGATE3
PQ22
@
1
4
@
ISL6208CRZ-T_QFN8~D
PWR_MON
2.4_0805_1%~D
2
PR268
2
5
6
7
8
D
D
D
D
3
2
1
UGATE3
FDMS8670AS_MLP-8~D
LGATE
PC178
1000P_0603_25V7K~D
2
1
1
FCCM UGATE
2
G
S
S
S
PR121
PC119
2.2_0603_1%~D 0.22U_0603_10V7K~D
1 2
1
1
2
3
6
BOOT
E
+CPU_PWR_SRC
D
2
SI4386DY-T1-E3_SO8~D
PQ21
VCC
@
1
1
2
PU9
PR272
2.4_0805_1%~D
PC102
0.1U_0603_25V7K~D
2
1
2
G
PC110
1500P_0603_25V7K~D
2
1
1
2
4
VO
PL14
0.45UH_ETQP4LR45XFC_25A_20%~D
PHASE2
PR273
2.4_0805_1%~D
LGATE2
5
@
F
2
FDMS8670AS_MLP-8~D
+VCC_CORE
PR91
7.68K_0805_1%~D
PQ20
FDMS8670AS_MLP-8~D
33K_0402_5%~D
ISL6208CRZ-T_QFN8~D
S
2
GNDA_VCORE
8
2
2
PC132
4700P_0402_25V7K~D
1
@
2
PC134
0.01U_0402_16V7K~D
PC129
1
4700P_0402_25V7K~D
1
1
UGATE2
1
1
2
PR132
1K_0402_1%~D
2
1
@
PC118
1U_0603_10V6K~D
1
1
330P_0402_50V7K~D
PC131
2
PR136
6.34K_0402_1%~D
2
2
PC128
1
PR137
1K_0402_1%~D
1
2
2
0_0402_5%~D
PR131
9.76K_0402_1%
2
1
1
1000P_0402_50V7K~D
2
GNDA_VCORE
PR129
82.5K_0402_1%~D
PC127
220P_0402_50V8J~D
1
2
GNDA_VCORE
PR367
2
VO
2
2
2
1
VO
16
14
1
VSUM
PR122
4.53K_0402_1%~D
2
1
PC122
0.33U_0603_10V7K
GND
PC121
PR126
0_0603_5%~D
680P_0402_50V7K~D 2
1
1.69K_0402_1%~D
2
PC124
1500P_0402_50V7K~D
7
OCSET
PR120
2
1
0_0402_5%~D
1
1
3
@
LGATE
@
1
3
2
H
PC116
2200P_0402_50V7K~D
2
1
PWM PHASE
7
30K_0402_5%~D
VSUM 17
VW
ISL6260CCRZ_QFN40~D
1
PR127
0_0402_5%~D
4
PC115
0.1U_0603_25V7K~D
2
1
1
8
+5V_ALW
GNDA_VCORE
PR368
33K_0402_5%~D
2
1
8
B
@
PC177
1000P_0603_25V7K~D
2
1
1
BOOT
FCCM UGATE
2
PR98
PC108
2.2_0603_1%~D 0.22U_0603_10V7K~D
2
1
1
2
PR117
12.7K_0402_1%~D
2
1
FB
PC117 1000P_0402_50V7K~D
2
1
2
@ PR116
226K_0402_1%~D
2
1
1
21
PR139
ISEN3
2
VDIFF
COMP
2
3
2
1
S
S
S
VCC
6
G
@
PC130
0.1U_0402_16V7K~D
RTN
11
25
PR125
0_0402_5%~D
2
1
13
PWM3
1
VSEN
2
VR_ON
12
PR130
15K_0402_1%~D
35
PR124
1
3
S
5
PAD-OPEN 4x4m
+PWR_SRC
G
5
6
7
8
PQ19
PU8
+
2
PL13
0.45UH_ETQP4LR45XFC_25A_20%~D
D
D
D
D
39
40
4
24
FCCM
PR119
2.43K_0402_1%~D
2
1
CLK_EN#
41
1
2
1
PMON
9
GNDA_VCORE
2
+CPU_PWR_SRC
@
PC112 1000P_0402_50V7K~D
2
1
VSSSENSE
G
S
PSI#
2
38
10
PR123
2
1
332_0402_1%~D
1
1
PH3
0_0402_5%~D
1
1
PR118
2
1
4.99K_0402_1%
2
S
S
S
DPRSLPVR
22
ISEN2
DFB
2
@ PH2
10KB_0603_1%_ERTJ1VG103FA~D
PR138
LGATE1
3
2
1
DPRSTP#
36
C
A
ISL6208CRZ-T_QFN8~D
3
37
PWM2
26
6.8KB_0603_5%_ERTJ1VR682J~D
PR114
2
VCCSENSE
2
+
PJP32
1
1
Iccmax=44A
I_TDC=35A
OCP=65A, Intel spec=50A
PHASE1
D
VID0
VID1
VID2
VID3
VID4
VID5
VID6
23
PC123
0.01U_0402_16V7K~D
@ PR115 0_0402_5%~D
2
<8> 1
CLK_ENABLE#
@
T55
<37> IMVP_VR_ON
@
4
LGATE
SI4386DY-T1-E3_SO8~D
28
29
30
31
32
33
34
ISEN1
15
2
1
@ PR113
PAD~D
0_0402_5%~D
2
1
<37,38,41> RUNPWROK
<8>
7
GND
D
1
SOFT
1
NTC
6
27
PC120
0.033U_0402_16V7K~D
1
2
PR107
2
1
499_0402_1%~D
PR110
2
1
10K_0402_5%~D
GNDA_VCORE
@
PWM PHASE
3
+
1
@
UGATE1
2
5
PWM1
PC133
0.1U_0402_16V7K~D
PR108
2
1
0_0402_5%~D
H_PSI#
PC111
1U_0603_10V6K~D
18
RBIAS
DROOP
<10,24> DPRSLPVR
D
2
PU7
2 PR99
1
0_0402_5%~D
2 PR100 1
0_0402_5%~D 2 PR101 1
0_0402_5%~D
2 PR102 1
0_0402_5%~D 2 PR103 1
0_0402_5%~D
2 PR104 1
0_0402_5%~D 2 PR105 1
0_0402_5%~D
VID0
VID1
VID2
VID3
VID4
VID5
VID6
<18> PWR_MON
8
1
1
470KB_0402_5%_NCP15WM474J03RB~D
<8,10,23> H_DPRSTP#
<8>
VIN
VR_TT#
3
3V3
19
20
4
PH1
GNDA_VCORE
<8>
<8>
<8>
<8>
<8>
<8>
<8>
FCCM UGATE
PC106
1U_0603_10V6K~D
@
2
PC107
0.015U_0402_16V7K~D
2
1
6
1
@
@
PGOOD
IMVP6_PROCHOT#
VDD
@
T92
1
@
2
E
PAD~D
BOOT
+5V_ALW
@
2
2
GNDA_VCORE
@ PC101
2200P_0402_50V7K~D
2
1
VCC
PL12
FBMJ4516HS720NT_1806~D
1
2
IMVP_PWRGD <24,37,41>
VSS
@ PR96
0_0402_5%~D
2
1
PR97
13K_0402_5%~D
PR94
147K_0402_1%~D
2
1
+3.3V_RUN
5
PR93
1.91K_0603_1%~D
1
F
PR95
0_0603_5%~D
1
PC100
PR89
1U_0603_10V6K~D 10_0603_5%~D
2
1
1
2
+5V_ALW
GNDA_VCORE
G
PR87
PC96
2.2_0603_1%~D 0.22U_0603_10V7K~D
2
1
1
2
PU6
PR366
33K_0402_5%~D
1
0.01U_0402_25V7K~D
PC97
2
1
PR86
10_0603_5%~D
G
4
PC95
1U_0603_10V6K~D
2
1
2
+5V_ALW
PC176
1000P_0603_25V7K~D
2
1
1
+CPU_PWR_SRC
D
D
D
D
PQ17
SI4386DY-T1-E3_SO8~D
H
PC90
0.1U_0603_25V7K~D
2
1
+CPU_PWR_SRC
PC265
470P_0402_50V7K~D
2
1
6
PC264
680P_0402_50V7-K~D
2
1
7
1
8
5
4
3
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3801P
2
47
Sheet
1
of
71
5
4
3
2
PD30 B540C~D
2
1
+SDC_IN
PQ62B
NTGD4161PT1G_TSOP6~D
2
3
PC137
0.1U_0603_25V7K~D
2
1
ISL88731_TQFN28~D
@
@ PJP34
1
PC152
10U_1206_25V6M~D
2
1
PC151
10U_1206_25V6M~D
2
1
@ PC139
0.1U_0603_25V7K~D
1
2
2
PAD-OPEN1x1m
GNDA_CHG
@ PC261
0.1U_0603_25V7K~D
2
1
PC166
1
2
1
PC150
0.1U_0603_25V7K~D
2
1
PC149
2200P_0402_50V7K~D
2
1
5
6
7
8
1000P_0603_50V7K
PR264
1.8K_1206_5%~D
G
@
2
4
@
1
+VCHGR
100_0402_5%~D
D
S
PQ36
RHU002N06_SOT323
16
3
PC249
PC179
2200P_0402_50V7K~D
2
1
NC
2
PC162
10U_1206_25V6M~D
2
1
VFB
1 PR161
1
PC161
10U_1206_25V6M~D
2
1
GND
15
4
5.6U_HMU1356-5R6_8.8A_20%~D 2
PC160
10U_1206_25V6M~D
2
1
GND
29
CSON
17
S
S
S
12
19
18
+VCHGR
PR160
0.01_1206_1%~D
2+VCHGR_L1
PR355
10_0402_1%~D
2
1
PC159
0.1U_0603_25V7K~D
2
1
NC
PGND
CSOP
3
2
1
@
VREF
PL16
+VCHGR_B
D
D
D
D
7
1
PR339
100K_0402_5%~D
PC154
220P_0402_50V7K~D
CHG_LGATE
PQ31
SI4800BDY-T1_SO8~D
20
2
3
@ PR263
1
2
0_0402_5%~D
PC163
0.1U_0402_10V7K~D
2
1
@
1
2
28
CSSP
27
LGATE
3
B
ISL88731_VREF
PC158
1U_0603_10V6K~D
2
1
@
1
1
2
@ PC243
@ PR262
2000P_0402_10V7K~D 7.5K_0402_5%~D
@ PC241
130P_0402_10V7K~D @
1
2
PC165
0.01U_0402_25V7K~D
2
1
@
PC164
0.1U_0402_10V7K~D
2
1
PR162
16.2K_0402_1%~D
2
1
<18> ISL88731_ICM
2
PC157
PC242
0.01U_0402_25V7K~D130P_0402_10V7K~D
2
1
1
2
<6,27,38> CKG_SMBDAT
PC156
0.01U_0402_25V7K~D
2
1
PR159
2.2K_0402_5%~D
2
1
GNDA_CHG
<6,27,38> CKG_SMBCLK
4
PR163
10_0402_1%~D
2
1
ICOMP
PHASE
4
CHG_UGATE
2 PR158 1
0_0603_1%~D
C
3
2
1
4
24
23
1
NC
UGATE
PC148
1U_0603_10V6K~D
1
2
1 2
VCOMP
5
21 ISL88731_VDDP
2
6
@
PR153
33_0603_1%~D
2
ICM
VDDP
PR155
2.2_0603_1%~D
2
1
PR281
4.7_1206_5%
8
25
PQ30
SI4800BDY-T1_SO8~D
NC
<49>
SI4812BDY-T1-E3_SO8~D
PQ32
SDA
BOOT
5
6
7
8
9
14
26
PC155
3300PF_0402_50V7K~D
2
1
5
3
6
2
7
1
8
SCL
DOCK_DCIN_IS- <35>
1
VDDSMB
10
6
PR338
100K_0402_5%~D
SW_GND
2
1
PC144
1U_0603_10V6K~D
1
2
GNDA_CHG
PD17
RB751V_SOD323~D
2
1
ACOK
11
VCC
PC147
0.1U_0603_25V7K~D
2
1
13
CSSN
ACIN
NC
DCIN
2
ISL88731_ICM
1
PU10
22
D
DOCK_DCIN_IS+ <35>
5
2
2
1
@
PQ62A
NTGD4161PT1G_TSOP6~D
PR340
100K_0402_5%~D
2
PC143
0.1U_0402_10V7K~D
1
2
2
1
1
1
PR149
10_0402_1%~D
PR354
10_0402_1%~D
2
1
2
PR177
10K_0402_5%~D
1
GNDA_CHG
1
2
0_0402_5%~D
1
2
@ PR176
200K_0402_5%~D
4
PC136
2200P_0402_50V7K~D
2
1
PQ25
NTR4502PT1G_SOT23-3~D
1
3
1
PQ26
NTR4502PT1G_SOT23-3~D
PQ27
RHU002N06_SOT323
1
3
@
@ PC260
GNDA_CHG
0.1U_0603_25V7K~D
GNDA_CHG
PC153
0.1U_0402_10V7K~D
3
1
PR157
15.8K_0402_1%~D
2
1
+3.3V_ALW
3
1
2
PC135
TBD_0603_25V7K~D
PR141
33K_0402_5%~D
2
1
PR146
10K_0402_5%~D
2
1
1
2
PC142
0.047U_0603_25V7K~D
1
PR143
160K_0402_1%~D
2
1
2
PR173
0_0402_5%~D
1
@ PC138
0.1U_0603_25V7K~D
1
2
PC145
1U_0805_25V6K~D
2
1
2
PR152
10K_0402_1%~D
2
1
2
1
PR145
215K_0402_1%
S
2
G
PR150
33K_0402_5%~D
3
0.01U_0402_25V7K~D
GNDA_CHG
D
1
2
2
2
D
<18,38> ACAV_IN
PAD-OPEN 4x4m
2
2
PR156
1
CHAGER_SRC
G
PC146
2
3
1
3
S
@
PR154
49.9K_0402_1%~D
1
2
C
ISL88731_VREF
1
4
2
D
S
2
G
+SDC_IN
ISL88731_VDDP
PL21
FBMJ4516HS720NT_1806~D
1
2
1
G
D
@
S
S
S
3
+DC_IN_SS
PQ44
RHU002N06_SOT323
PR284
200K_0402_1%~D <49> ACAV_DOCK_SRC
2
1
1
D
2
G
PQ35
RHU002N06_SOT323
3
1
NB_AC_OFF# 2
G
0_0402_5%~D
PD33
BAT54CW_SOT323~D
1
2
+DOCK_PWR_BAR
@ PR356
PQ56
RHU002N06_SOT323
D
PR175
24K_0402_1%~D
2
1
3
1
D
+DC_IN
1
PR174
10K_0402_5%~D
2
1
NB_AC_OFF <37,43,49>
+PWR_SRC
PR140
0.01_1206_1%~D
PJP33
2
+DC_IN_SS
4
PQ34
SI4835BDY-T1-E3_SO8~D
8
1
7
2
6
3
5
1
2
G
@
0.1U_0402_10V7K~D
GNDA_CHG
ACAV_IN
GNDA_CHG
B
GNDA_CHG
ISL88731_VREF
+5V_ALW
+3.3V_ALW
GNDA_CHG
GNDA_CHG
GNDA_CHG
GNDA_CHG
GNDA_CHG
@
PD35
NB_AC_OFF# 2
1
@
@
GNDA_CHG
@
1
2
G
S
PQ33
RHU002N06_SOT323
@
GNDA_CHG
1K_0402_5%~D
@
PR170
1
ADAPT_OC <37>
D
3
G
P
8
@
+5V_ALW
PR168
100K_0402_1%~D
2
1
4
@
GNDA_CHG GNDA_CHG
GNDA_CHG
RB751S40T1_SOD523-2~D
A
GNDA_CHG
GNDA_CHG
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
GNDA_CHG
Title
@
GNDA_CHG GNDA_CHG
5
@
@
2
<37,38>
IN+
@
PC167
10P_0402_50V8J~D
2
1
ACAV_IN_NB
PU11B
LM393DR_SO8~D
3
PC173
0.01U_0402_25V7K~D
2
1
PR335
1
2
0_0402_5%~D
7
IN-
GNDA_CHG
PU11A
LM393DR_SO8~D
O 1
PC172
100P_0402_50V8J
2
1
G
O
2
PC171
100P_0402_50V8J
2
1
IN-
P
IN+
6
4
PR332
42.2K_0402_1%~D
2
1
5
PC170
100P_0402_50V8J
2
1
PAD~D
T174
PC168
0.1U_0402_25V7K~D
2
1
1
PR362
100K_0402_5%~D
@
PR169
33.2K_0402_1%~D
1
2
@
8
2
+5V_ALW
2
1
@
PR166
51.1K_0402_1%~D
2
1
@ PR167
1
2
8.45K_0402_5%~D
PR171
17.8K_0402_1%
2
1
PC169
0.01U_0402_25V7K~D
2
1
ISL88731_ICM
PR172
348_0402_1%~D
2
1
ISL88731_VREF
+3.3V_ALW
PR334
1M_0402_5%~D
1
2
PR341
100K_0402_5%~D
PR333
47K_0402_1%~D
2
1
PC255
100P_0402_50V8J
2
1
PR336
21.5K_0402_1%
1
2
A
PC256
100P_0402_50V8J
2
1
PR331
232K_0402_1%~D
2
1
+DC_IN ISL88731_VREF
PR165
100K_0402_5%~D
2
1
Maximum charging current is 6.24A
@ PR164
1M_0402_1%~D
1
2
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://hobi-elektronika.net
3
2
Charger
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3801P
Sheet
1
48
of
71
5
4
3
2
2
1
PD27
B540C~D
1
FDS6679AZ_SO8~D
PQ23
1
PR144
22K_0402_5%~D
2
1
1
2
4
1
6
2
G
EN_DOCK_PWR_BAR <37>
S
3
2
3
1
PQ28
RHU002N06_SOT323
D
2
1
PR181
22K_0402_5%~D
2
2
<48>
6
C
NB_AC_OFF_BJT <43>
1
D
PQ39
RHU002N06_SOT323
2
G
PQ63A
2N7002DW-T/R7_SOT363-6~D
3
4
PQ63B
2N7002DW-T/R7_SOT363-6~D
1
1
3
PQ24A
IMD2AT-108_SC74-6~D
1
PR360
0_0402_5%~D
2 2
1
5
D
PQ57
RHU002N06_SOT323
EN_DOCK_PWR_BAR#
5
PR151
22K_0402_5%~D
SW_GND
ACAV_DOCK_SRC <48>
2
G
D
+5V_ALW
3
1
2
C
3
1
3
S
PR275
100K_0402_5%~D
+3.3V_ALW2
S
2
PQ37
RHU002N06_SOT323
PR179
22K_0402_5%~D
1
D
2
G
<35> ACAV_DOCK_SRC#
S
2
G
PQ29
RHU002N06_SOT323
1
2
1
PQ38
RHU002N06_SOT323
2
G
D
<37,43,48>
D
PR148
47K_0402_1%~D
1
PR180
100K_0402_5%~D
2
1
2
2
PR357
330K_0402_5%~D
NB_AC_OFF
PR274
100K_0402_5%~D
2
1
+3.3V_ALW2
PR178
100K_0402_5%~D
1
PR147
100K_0402_5%~D
1
D
PQ24B
IMD2AT-108_SC74-6~D
PR142
240K_0402_5%~D
3
+3.3V_ALW
4
+3.3V_ALW
1
2
3
PC141
0.47U_0805_25V7K~D
2
1
8
7
6
5
+DOCK_PWR_BAR
S
S
SLICE_BAT_PRES
PD31
PDS5100H-13_POWERDI5-3
2
PR361
330K_0402_5%~D
1
5
6
1
1
1
4
5
1
1
4
D
PQ43
RHU002N06_SOT323
2
G
2
EN_DOCK_PWR_BAR#
1
PR358
0_0402_5%~D
2
1
S
3
3
S
RHU002N06_SOT323
<37> PBATT_OFF
A
ACAV_DOCK_SRC
2
@ PR359
0_0402_5%~D
PD34
RB751S40T1_SOD523-2~D
DELL CONFIDENTIAL/PROPRIETARY
1
Compal Electronics, Inc.
<35,37> DOCK_AC_OFF
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
PC175
0.1U_0603_25V7K~D
2
1
PQ66
D
2
G
A
PC174
2200P_0402_50V7K~D
2
1
1
RB751V-40_SOD323~D
2
PQ40B
2N7002DW-T/R7_SOT363-6~D
<35,37,43> SLICE_BAT_PRES#
PD20
2
PR186
33K_0402_5%~D
1
2
PR326
240K_0402_5%~D
1
2
2
2
1
+DOCK_PWR_BAR
3
RB751S40T1_SOD523-2~D
4
B
PQ59A
NTGD4161PT1G_TSOP6~D
2
1
5
PC262
PR363
1U_0603_25V6-K~D 1K_1206_5%
3
2
6 1
1
SLICE_BAT_PRES
1
RB715F_SC70-3~D
PQ40A
2N7002DW-T/R7_SOT363-6~D
PD36
2
3
+PWR_SRC
PR328
47K_0402_5%~D
3
4
2
PR329
100K_0402_5%~D
1
2
PC263
1U_0603_25V6-K~D
6
3
1
1
PQ55B
2N7002DW-T/R7_SOT363-6~D
5
1
4
PR327
47K_0402_5%~D
4
1
2
PR325
240K_0402_5%~D
1
2
PR260
620K_0402_5%~D
2
PR365
PR364
390K_0402_5%~D 390K_0402_5%~D
2
1
2
1
1
2
PR352
47K_0402_1%~D
6
1
+3.3V_ALW2
PD18
D
2
1
1
2
3
2
+DC_IN_SS
G
PR353
100K_0402_5%~D
33_0402_5%~D
2N7002DW-T/R7_SOT363-6~D
PQ55A
2
PQ64B
2N7002DW-T/R7_SOT363-6~D
<37> PBATT_OFF
2
1
+NBDOCK_DC_IN_SS
S
<37> PBATT_OFF
PQ59B
NTGD4161PT1G_TSOP6~D
PD19
RB751V-40_SOD323~D
PQ64A
2N7002DW-T/R7_SOT363-6~D
2
8
7
6
5
+DC_IN_SS
2
2
D
+3.3V_ALW
PR261
1
1
3
FDS6679AZ_SO8~D
PQ42
8
7
6
5
G
B
1
2
3
S
2
4
+VCHGR
PBATT+
PR351
240K_0402_5%~D
PQ65
SI4835BDY-T1-E3_SO8~D
8
1
7
2
6
3
5
FDS6679AZ_SO8~D
PQ41
4
3
2
Selector
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
49
of
71
4
2
C743
1 C742 PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_P13
0.1U_0402_10V7K~D
PEG_MRX_GTX_N130.1U_0402_10V7K~D
2
1
2
C746
1 C745 PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_P14
0.1U_0402_10V7K~D
PEG_MRX_GTX_N140.1U_0402_10V7K~D
2
1
2
C749
1 C747 PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_P15
0.1U_0402_10V7K~D
PEG_MRX_GTX_N150.1U_0402_10V7K~D
2
1
2
C754
1 C752 PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
<6> CLK_PCIE_VGA
<6> CLK_PCIE_VGA#
<10,22,32> PLTRST1#
R681 1
CLK_PCIE_VGA
CLK_PCIE_VGA#
AB10
AC10
PEX_REFCLK
PEX_REFCLK_N
AD9
AG10
PEX_RST_N
PEX_TERMP
2 0_0402_5%~D
PEX_TERMP
E9
<6> CLK_NVSS_27M
B
R686
1
2
XTALSSIN_R
0_0402_5%~D
XTALOUTBUFF
D11
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CD_SCL
I2CD_SDA
I2CE_SCL
I2CE_SDA
I2CH_SCL
I2CH_SDA
I2CS_SCL
I2CS_SDA
XTALSSIN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
TESTMODE
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
XTALIN
CLK
XTALOUT
PEX_TERMP
2
2.49K_0402_1%~D
CRT_CLK_DDC
2
6
GPU_CLK_DDC
GPU_CLK_DDC <20>
5
CRT_DAT_DDC
4
1
@ R861
0_0402_5%~D
Q123B
2N7002DW-T/R7_SOT363-6~D
GPU_DAT_DDC
3
HDCP_WP
GPU_DAT_DDC <20>
I2CE_SCL_PU
I2CE_SDA_PU
2
U56
8
7
6
5
1
2
3
4
1
2
R752
0_0402_5%~D
1
2
R753
0_0402_5%~D
190-00007-0000-T00 AT24C16BN-SHBY-B_SO8~D
VCC
WP
SCL
SDA
A0
A1
A2
GND
2
R758
1
R96
2
@ R1012
2
@ R1013
1
2.2K_0402_5%~D
2
10K_0402_5%~D
1
10K_0402_5%~D
1
10K_0402_5%~D
+3.3V_RUN
2
2
2
2
2
2
2
2
2
1
R691
CRT_GRN_GPU
1
R692
CRT_BLU_GPU
1
R693
STRAP_CAL_PU_GND0
1
R727
STRAP_CAL_PU_GND1
1
R731
JTAG_RST#_GPU
1
@ R853
4
@
STRAP0
STRAP1
STRAP2
ROM_SCLK_GPU
ROM_SI_GPU
ROM_SO_GPU
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
<21>
<21>
<21>
<21>
<21>
<21>
<21>
<21>
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
@
Each strap pin represents a 4 bit value
Pullup or Pulldown configures the MSB
Resistor Value determines the 3 LSBs
Resistor range is R*n
where n is 0-9 and R is 5K ohm.
For NVG98 NS part stuff R719, no-stuff R716
For NVG98 GLM part stuff R716, no-stuff R719
For Samsung 32Mx16 DDR2 part stuff R725=30K
For Qimonda 32Mx16 DDR2 part stuff R725=35K
For Hynix 32Mx16 DDR2 part stuff R725=45K
2 LCD_A0-_GPU
3.3P_0402_50V8C~D
2 LCD_A1-_GPU
3.3P_0402_50V8C~D
2 LCD_A2-_GPU
3.3P_0402_50V8C~D
2 LCD_B0-_GPU
3.3P_0402_50V8C~D
2 LCD_B1-_GPU
3.3P_0402_50V8C~D
2 LCD_B2-_GPU
3.3P_0402_50V8C~D
2 LCD_ACLK-_GPU
3.3P_0402_50V8C
2 LCD_BCLK+_GPU
3.3P_0402_50V8C~D
ROM_SCLK_GPU
2
150_0402_5%~D
2
150_0402_5%~D
2
150_0402_5%~D
2
40.2K_0402_1%
2
40.2K_0402_1%
2
1K_0402_5%~D
@ C744
100P_0402_50V8K~D
C
VGA_THERMDN <18>
1
R825
@
Resistor
@
@
@
@
Multilevel
Tied to VCC
5 Kohms
Y
1000
Tied to Ground
0000
10 Kohms
Y
1001
0001
15 Kohms
Y
1010
0010
20 Kohms
Y
1011
0011
25 Kohms
Y
1100
0100
30 Kohms
Y
1101
0101
35 Kohms
Y
1110
0110
40 Kohms
Y
1111
0111
45 Kohms*
N
1xxx
0xxx
Value
2
15K_0402_1%~D
B
GFX_OPEN_GL_EN <37>
+3.3V_RUN
<27> SPDIF_OUT
1
2
C1032
0.01U_0402_16V7K~D
CLOSE TO GPU
2
@ R801
10K_0402_5%~D
@
@ D63
DA204U_SOT323-3~D
SPDIF_OUT_GPU
A
DELL CONFIDENTIAL/PROPRIETARY
Stuff R824 for
standard I2C ROM.
Stuff R801 for
crypto ROM
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
NVG98 PCIE,GPIO,CLK,LVDS
Size
3
http://hobi-elektronika.net
2
Document Number
Re v
0.8
LA-3803P
Date:
5
VGA_THERMDP <18>
1
+3.3V_RUN
1
CRT_RED_GPU
THERMDP
THERMDN
2
@ R797
100K_0402_5%~D
DPB_MB_P14 <21>
SPDIF_OUT_GPU
D9
D8
Strap pin define
R824
2.2K_0402_5%~D
HDCP_CLK
2
10K_0402_5%~D
1
1
@ R832
F9
N5
2
A
DPB_GPU_P14
SPDIF
BUFRST_N
ENVDD_GPU
LCD_A0+_GPU 1
@ C790
LCD_A1+_GPU 1
@ C794
LCD_A2+_GPU 1
@ C801
LCD_B0+_GPU 1
@ C772
LCD_B1+_GPU 1
@ C773
LCD_B2+_GPU 1
@ C774
LCD_ACLK+_GPU1
@ C789
LCD_BCLK-_GPU1
@ C802
+3.3V_RUN
HDCP_DAT
NC0
NC1
NC2
NC3
Keep stub for caps as small as possible
Q123A
2N7002DW-T/R7_SOT363-6~D
+3.3V_RUN
HDMI
AA6
AC19
E15
T6
R856
R857
4.99K_0402_1%~D 36K_0402_5%~D
1
HDCP_WP
HDCP_CLK
HDCP_DAT
1
DPC_LANE_P0
DPC_LANE_N0 C759
DPC_LANE_P1 C760
DPC_LANE_N1 C761
DPC_LANE_P2 C762
DPC_LANE_N2 C763
DPC_LANE_P3 C764
DPC_LANE_N3 C765
C766
E10
2
C788
0.1U_0402_10V7K~D
R695
2.2K_0402_5%~D
1
2
@ R860
0_0402_5%~D
0
CRT_CLK_DDC
<---CRT
CRT_DAT_DDC
DVI_C_CLK_DDC
DVI_C_CLK_DDC <21> <---DVI C
DVI_C_DAT_DDC
DVI_C_DAT_DDC <21>
LDDC_CLK_GPU
<---LVDS
LDDC_CLK_GPU <19>
LDDC_DATA_GPU
LDDC_DATA_GPU <19>
DVI_B_CLK_DDC
<---DVI B
DVI_B_CLK_DDC <21>
DVI_B_DAT_DDC
DVI_B_DAT_DDC <21>
I2CE_SCL_PU
I2CE_SDA_PU
HDCP_CLK
HDCP_DAT
1
2
+3.3V_RUN
@ R1079 1
2 10K_0402_5%~D
@ R1080
10K_0402_5%~D
JTAG_TCK_GPU
AF3
T83 PAD~D@
JTAG_TDI_GPU
AG4
T84 PAD~D@
JTAG_TDO_GPU
AE4
T85 PAD~D@
JTAG_TMS_GPU
AF4
T86 PAD~D@
JTAG_RST#_GPU
DPB_LANE_P0
AG3
2
DPB_LANE_N0 C748 2
AD25
2
1
R680
10K_0402_5%~D
DPB_LANE_P1 C750 2
DPB_LANE_N1 C751 2
AF10
DPB_LANE_P2 C753 2
AE10
1
2
R696
200_0402_1%~D
DPB_LANE_N2 C755 2
DPB_LANE_P3 C756 2
DPB_LANE_N3 C757 2
C758
D10
CLK_NV_27M <6>
1
1
1
2
2
R694
2.2K_0402_5%~D
DVI
R1
T3
R2
R3
A2
B1
N2
N3
Y6
W6
A3
A4
T1
T2
+3.3V_RUN
1
0
2
+3.3V_RUN
0
NB9M-GS_BGA533~D
NB9M-GS_BGA533~D
1
R687
DP Conn.
GPIO17 function
X
DP
R718
4.99K_0402_1%~D
2
1
PEG_MRX_GTX_P12
0.1U_0402_10V7K~D
PEG_MRX_GTX_N120.1U_0402_10V7K~D
2
1
1
R726
4.99K_0402_1%~D
2
1
1 C740 PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
GPIO16
R717
4.99K_0402_1%~D
2
1
2
C741
U6
U4
T5
R4
T4
V6
R6
STRAP0
STRAP1
STRAP2
STRAP_CAL_PU_GND0
STRAP_CAL_PU_GND1
R244
10K_0402_5%~D
PEG_MRX_GTX_P11
0.1U_0402_10V7K~D
PEG_MRX_GTX_N110.1U_0402_10V7K~D
2
1
DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_BLUE
DACC_GREEN
DACC_RSET
DACC_VREF
C7
B9
A9
F10
F11
STRAP0
STRAP1
STRAP2
STRAP_CAL_PD_3V3(NC)
STRAP_CAL_PD_MIOB(NC)
GENERAL
R725
34.8K_0402_1%~D
2
1
1 C738 PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
1
2
R721
1K_0402_1%~D
C9 ROM_SCLK_GPU
ROM_SI_GPU
A10
C10 ROM_SO_GPU
B10
R716
15K_0402_1%
2
1
2
C739
AD10
AD11
AD12
AC12
AB11
AB12
AD13
AD14
AD15
AC15
AB14
AB15
AC16
AD16
AD17
AD18
AC18
AB18
AB19
AB20
AD19
AD20
AD21
AC21
AB21
AB22
AC22
AD22
AD23
AD24
AE25
AE26
D
DPC_DOCK_AUX <21>
DPC_DOCK_AUX# <21>
R719
15K_0402_1%
2
1
PEG_MRX_GTX_P10
0.1U_0402_10V7K~D
PEG_MRX_GTX_N100.1U_0402_10V7K~D
2
1
PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
PEG_MRX_GTX_C_P10
PEG_MRX_GTX_C_N10
PEG_MRX_GTX_C_P11
PEG_MRX_GTX_C_N11
PEG_MRX_GTX_C_P12
PEG_MRX_GTX_C_N12
PEG_MRX_GTX_C_P13
PEG_MRX_GTX_C_N13
PEG_MRX_GTX_C_P14
PEG_MRX_GTX_C_N14
PEG_MRX_GTX_C_P15
PEG_MRX_GTX_C_N15
RFU0(NC)
RFU1(NC)
RFU2(NC)
RFU3(NC)
RFU4(NC)
RFU5(NC)
RFU6(NC)
RFU7(NC)
M6
R715
20K_0402_1%~D
2
1
1 C735 PEG_MRX_GTX_C_P9
PEG_MRX_GTX_C_N9
C15
D15
J5
F6
J22
L22
AG9
AE9
IFPE_RSET
ROM_SCLK
ROM_SI
ROM_SO
ROMCS_N
R730
4.99K_0402_1%~D
2
1
2
C736
F7
E6
E7
F8
D6
G6
HDA_BCLK
HDA_SYNC
HDA_SDI
HDA_SDO
HDA_RST_N
R714
4.99K_0402_1%~D
2
1
PEG_MRX_GTX_P9
0.1U_0402_10V7K~D
PEG_MRX_GTX_N9 0.1U_0402_10V7K~D
2
1
DACB_RED
DACB_BLUE
DACB_GREEN
DACB_RSET
DACB_CSYNC
DACB_VREF
IFPAB_RSET
2
1K_0402_1%~D
DPC_LANE_P0
DPC_LANE_N0
DPC_LANE_P1
DPC_LANE_N1
DPC_LANE_P2
DPC_LANE_N2
DPC_LANE_P3
DPC_LANE_N3
R729
10K_0402_1%~D
2
1
1 C733 PEG_MRX_GTX_C_P8
PEG_MRX_GTX_C_N8
HDA_RST#
A7
B7
A6
B6
C6
1
R720
R713
45.3K_0402_1%~D
2
1
2
C734
CRT_HSYNC_GPU <20>
CRT_VSYNC_GPU <20>
CRT_RED_GPU <20>
CRT_BLU_GPU <20>
CRT_GRN_GPU <20>
2
124_0402_1%~D1
2
C732
0.1U_0402_10V7K~D
D3
D4
F5
F4
E4
D5
C3
C4
B3
B4
R728
4.99K_0402_1%~D
2
1
PEG_MRX_GTX_P8
0.1U_0402_10V7K~D
PEG_MRX_GTX_N8 0.1U_0402_10V7K~D
2
1
CRT_HSYNC_GPU
CRT_VSYNC_GPU
CRT_RED_GPU
CRT_BLU_GPU
CRT_GRN_GPU
DACA_RSET 1
DACA_VREF R677
R5
<21>
<21>
2
2
C731
1 C730 PEG_MRX_GTX_C_P7
PEG_MRX_GTX_C_N7
AD2
AD1
AE2
AD3
AE3
AE1
AF1
IFPC_RSET
IFPE_AUX
IFPE_AUX_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
DPB_AUX
DPB_AUX#
DPB_LANE_P0
DPB_LANE_N0
DPB_LANE_P1
DPB_LANE_N1
DPB_LANE_P2
DPB_LANE_N2
DPB_LANE_P3
DPB_LANE_N3
3
PEG_MRX_GTX_P7
0.1U_0402_10V7K~D
PEG_MRX_GTX_N7 0.1U_0402_10V7K~D
2
1
DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN
DACA_RSET
DACA_VREF
G4
G5
P4
N4
M5
M4
L4
K4
H4
J4
1
1 C728 PEG_MRX_GTX_C_P6
PEG_MRX_GTX_C_N6
IFPC_AUX
IFPC_AUX_N
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
1
1 C726 PEG_MRX_GTX_C_P5
PEG_MRX_GTX_C_N5
2
C729
DPC_DOCK_HPD <35>
1 R1009 2 DPB_CA_DET
0_0402_5%~D
1 R1010 2 DPC_CA_DET
0_0402_5%~D T119PAD~D
@
Part 3 of 5
2
2
C727
PEG_MRX_GTX_P6
0.1U_0402_10V7K~D
PEG_MRX_GTX_N6 0.1U_0402_10V7K~D
2
1
DPC_DOCK_HPD
DPB_CA_DET_R
DPB_GPU_P14
DPC_CA_DET_R
HDMI_DET1
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
1
PEG_MRX_GTX_P5
0.1U_0402_10V7K~D
PEG_MRX_GTX_N5 0.1U_0402_10V7K~D
2
1
THERMTRIP_VGA# <18>
LCD_ACLK+_GPU
LCD_ACLK-_GPU
LCD_A0+_GPU
LCD_A0-_GPU
LCD_A1+_GPU
LCD_A1-_GPU
LCD_A2+_GPU
LCD_A2-_GPU
MXM/DVI/DP
1 C724 PEG_MRX_GTX_C_P4
PEG_MRX_GTX_C_N4
2
0_0402_5%~D
@ C1076
0.1U_0402_10V7K~D
1
2
LCD_ACLK+_GPU
LCD_ACLK-_GPU
LCD_A0+_GPU
LCD_A0-_GPU
LCD_A1+_GPU
LCD_A1-_GPU
LCD_A2+_GPU
LCD_A2-_GPU
AC4
AD4
V5
V4
AA5
AA4
W4
Y4
AB4
AB5
LCD_BCLK+_GPU AB3
<19> LCD_BCLK+_GPU
LCD_BCLK-_GPU AB2
<19> LCD_BCLK-_GPU
LCD_B0+_GPU
W1
<19> LCD_B0+_GPU
LCD_B0-_GPU
V1
<19> LCD_B0-_GPU
LCD_B1+_GPU
W3
<19> LCD_B1+_GPU
LCD_B1-_GPU
W2
<19> LCD_B1-_GPU
LCD_B2+_GPU
AA2
<19> LCD_B2+_GPU
LCD_B2-_GPU
AA3
DPB_CA_DET <21> <19> LCD_B2-_GPU
AB1
@ R672
AA1
DPC_CA_DET <21,35>
1K_0402_5%~D
AB6
2
1
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>
LVDS
1 C722 PEG_MRX_GTX_C_P3
PEG_MRX_GTX_C_N3
2
C725
DPB_HPD
<21>
BIA_PWM_GPU <19>
ENVDD_GPU <19>
PANEL_BKEN_GPU <37>
GPU_VID_0
<56>
GPU_VID_1
<56>
HDA
2
C723
PEG_MRX_GTX_P4
0.1U_0402_10V7K~D
PEG_MRX_GTX_N4 0.1U_0402_10V7K~D
2
1
1
R670
1
U44C
DPB_HPD
BIA_PWM_GPU
ENVDD_GPU
PANEL_BKEN_GPU
GPU_VID_0
GPU_VID_1
2
PEG_MRX_GTX_P3
0.1U_0402_10V7K~D
PEG_MRX_GTX_N3 0.1U_0402_10V7K~D
2
1
N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2
1
2
C721
1 C720 PEG_MRX_GTX_C_P2
PEG_MRX_GTX_C_N2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
DVO / GPIO
1 C718 PEG_MRX_GTX_C_P1
PEG_MRX_GTX_C_N1
PEG_MRX_GTX_P2
0.1U_0402_10V7K~D
PEG_MRX_GTX_N2 0.1U_0402_10V7K~D
2
1
DACs
2
C719
Part 1 of 5
I2C
1 C716 PEG_MRX_GTX_C_P0
PEG_MRX_GTX_C_N0
PEG_MRX_GTX_P1
0.1U_0402_10V7K~D
PEG_MRX_GTX_N1 0.1U_0402_10V7K~D
2
1
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
R243
10K_0402_5%~D
2
C717
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22
AF22
AE22
AE24
AF24
AG24
AF25
AG25
AG26
AF27
AE27
TEST
PEG_MRX_GTX_N[0..15]
<12> PEG_MRX_GTX_N[0..15]
PEG_MRX_GTX_P0
0.1U_0402_10V7K~D
PEG_MRX_GTX_N0 0.1U_0402_10V7K~D
2
1
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_P4
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
PCI EXPRESS
PEG_MRX_GTX_P[0..15]
<12> PEG_MRX_GTX_P[0..15]
C
@ C1077
0.1U_0402_10V7K~D
1
2
U44A
PEG_MTX_GRX_N[0..15]
<12> PEG_MTX_GRX_N[0..15]
2
2
<12> PEG_MTX_GRX_P[0..15]
D
3
PEG_MTX_GRX_P[0..15]
1
5
Thursday, June 12, 2008
Sheet
1
50
of
71
5
4
3
FBAD[0:63]
2
FBAD[0:63] <54,55>
DQMA#[0:7]
DQMA#[0:7]
D
DQSA_WP[0:7]
<54,55>
D
DQSA_WP[0:7] <54,55>
DQSA_RN[0:7]
GPU CMD Maping VRAM table
DQSA_RN[0:7] <54,55>
FBA_CMD[0..27]
CMD_Address
FBA_CMD[0..27] <54,55>
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
U44B
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
SNN_FBA_CMD28
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
D23
C26
D19
B19
T24
T26
AA23
AB27
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
B24
D25
E18
A18
R22
R27
Y24
AA27
DQSA_RN0
DQSA_RN1
DQSA_RN2
DQSA_RN3
DQSA_RN4
DQSA_RN5
DQSA_RN6
DQSA_RN7
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
A24
C25
E19
A19
T22
T27
AA24
AA26
DQSA_WP0
DQSA_WP1
DQSA_WP2
DQSA_WP3
DQSA_WP4
DQSA_WP5
DQSA_WP6
DQSA_WP7
FB_VREF
A16
FBA_VREF
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_DEBUG
F24
F23
N24
N23
M22
CLKA0
CLKA0#
CLKA1
CLKA1#
T113PAD~D@
T114PAD~D@
T115PAD~D@
FBA_CMD11
FBA_CMD12
1
R697
1
R698
2
10K_0402_5%~D
2
10K_0402_5%~D
Pull-down for initialization
CKE & RESET/ODT
2
1
+1.8V_RUN_GPU
R699
1K_0402_1%~D
@
VRAM
Location
A3
A0
A2
A1
A3
A4
A5
U46,U47
U46..U49
U46,U47
U46..U49
U48,U49
U48,U49
U48,U49
CS#
WE#
BA0
CKE
ODT
A2
A12
RAS#
A11
A10
BA1
A8
A9
A6
A5
A7
A4
CAS#
U46..U49
U46..U49
U46..U49
U46..U49
U46..U49
U48,U49
U46..U49
U46..U49
U46..U49
U46..U49
U46..U49
U46..U49
U46..U49
U46..U49
U46,U47
U46..U49
U46,U47
U46..U49
NC#L1
U46..U49
C
B
10mil
2
1
R701
10K_0402_5%~D
CLKA0
<54>
CLKA0#
<54>
CLKA1
<55>
CLKA1#
<55>
T88 PAD~D@
+1.8V_RUN_GPU
1
2
@
R700
1K_0402_1%~D
NB9M-GS_BGA533~D
F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
1
Part 2 of 5
2
B
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
MEMORY
INTERFACE
C
D21
C22
B22
A22
C24
B25
A25
A26
D22
E22
E24
D24
D26
D27
C27
B27
D16
E16
D17
F18
D20
F20
E21
F21
C16
B18
C18
D18
C19
C21
B21
A21
P22
P24
R23
R24
T23
U24
V23
V24
N25
N26
R25
R26
T25
V26
V25
V27
V22
W22
W23
W24
AA22
AB23
AB24
AC24
W25
W26
W27
AA25
AB25
AB26
AD26
AD27
C775
0.1U_0402_10V7K~D
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
1
@
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
NVG98 Memory Interface
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
51
of
71
5
4
+15V_ALW
+1.8V_MEM
3
2
1
+1.8V_RUN Source
Place near GPU
1
2
1
2
W15
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22
IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPE_IOVDD
V3
V2
J6
H6
+IFPAB_IOVDD
AD5
P6
N6
+IFPAB_PLLVDD
+IFPC_PLLVDD
+IFPE_PLLVDD
K5
K6
L6
+GPU_PLLVDD
+PEX_PLLVDD
1
R852
2
0_0402_5%~D
GPU_VDD_SENSE <56>
+1.8V_RUN_GPU
C
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
C820
4.7U_0603_6.3V4Z~D
1
1
2
1
3
POWER
3
4
2
4
2
1
2
6
1
2
+1.8V_RUN_GPU
2
1
2
1
2
+IFPX_IOVDD= 385mA
1
2
1
2
1
2
1
2
C842
0.1U_0402_10V7K~D
2
1
C841
0.1U_0402_10V7K~D
2
1
C840
0.1U_0402_10V7K~D
2
1
C839
0.1U_0402_10V7K~D
2
1
C838
0.022U_0402_16V7K~D
2
1
C837
0.022U_0402_16V7K~D
2
1
C836
0.022U_0402_16V7K~D
1
+1.1V_GFX_PCIE
GPU_PLLVDD = 140 mA
+IFPC_IOVDD
+IFPE_IOVDD
+GPU_PLLVDD
2
1
2
2
L45
BLM18AG121SN1D_0603~D
C850
1U_0402_6.3V6K~D
2
1
C849
1U_0402_6.3V6K~D
2
1
C848
0.1U_0402_10V7K~D
1
C847
4700P_0402_25V7K~D
+IFPX_PLLVDD= 160mA
1
B
NB9M-GS_BGA533~D
2
1
2
1
2
1
2
C859
4.7U_0603_6.3V6M~D
2
1
C858
1U_0402_6.3V6K~D
2
1
L47 +1.8V_RUN_GPU
BLM18AG121SN1D_0603~D
1
2
C857
4.7U_0603_6.3V6M~D
2
1
C856
4700P_0402_25V7K~D
2
1
+IFPAB_PLLVDD
C855
470P_0402_50V7K~D
2
1
IFPAB_PLLVDD = 100 mA
C864
4.7U_0603_6.3V6M~D
2
1
C861
4700P_0402_25V7K~D
1
C329
4700P_0402_25V7K~D
2
+IFPAB_IOVDD
C860
470P_0402_50V7K~D
2
1
C897
4.7U_0603_6.3V6M~D
2
1
C889
4700P_0402_25V7K~D
L76
BLM18PG600SN1_0603~D
1
2
+IFPE_IOVDD
1
2
+1.8V_RUN_GPU
L48
BLM18AG121SN1D_0603~D
1
2
IFPAB_IOVDD = 100mA
C309
470P_0402_50V7K~D
2
1
C866
4.7U_0603_6.3V6M~D
2
1
C879
4700P_0402_25V7K~D
2
1
C888
470P_0402_50V7K~D
2
1
C917
4.7U_0603_6.3V6M~D
1
C898
4700P_0402_25V7K~D
2
C878
470P_0402_50V7K~D
1
2
L75
BLM18AG121SN1D_0603~D
1
2
+IFPE_PLLVDD
A
1
+1.1V_GFX_PCIE
L67
BLM18PG600SN1_0603~D
1
2
+IFPC_IOVDD
C880
470P_0402_50V7K~D
2
C863
4700P_0402_25V7K~D
C865
470P_0402_50V7K~D
2
1
C862
4.7U_0603_6.3V6M~D
+1.8V_RUN_GPU
L66
BLM18AG121SN1D_0603~D
1
2
+IFPC_PLLVDD
1
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
D
C787
4.7U_0603_6.3V4Z~D
C786
4.7U_0603_6.3V4Z~D
C785
0.01U_0402_16V7K~D
VDD_SENSE
PLLVDD
VID_PLLVDD
SP_PLLVDD
C784
0.1U_0402_10V7K~D
AF9
FBCAL_PD_VDDQ
2
C819
4.7U_0603_6.3V4Z~D
B15
1
C835
0.022U_0402_16V7K~D
2 FB_CAL_PD_VDDQ
30.1_0402_1%
2
C818
1U_0402_6.3V6K~D
2
2
R1011
2
R722
2
1
C800
10U_0805_10V4Z~D
2
1
C854
470P_0402_50V7K~D
1
C853
4700P_0402_25V7K~D
2
C852
4.7U_0603_6.3V6M~D
1
1
R706
+DACB_VDD
1
10K_0402_5%~D
+DACC_VDD
1
10K_0402_5%~D
+1.8V_RUN_GPU
+DACA_VDD
2
1
Place near Balls
PEX_PLLVDD
IFPAB_PLLVDD
IFPC_PLLVDD
IFPE_PLLVDD
C604
10U_0805_10V4Z~D
FB_PLLAVDD
FB_DLLAVDD
1
C834
4700P_0402_25V7K~D
R19
T19
DACA VDD= 120mA
+3.3V_RUN
L46
BLM18AG121SN1D_0603~D
1
2
2
C817
1U_0402_6.3V6K~D
DACA_VDD
DACB_VDD
DACC_VDD
1
C799
1U_0402_6.3V6K~D
+FB_PLLVDD
AG2
D7
W5
2
C833
4700P_0402_25V7K~D
B
+DACB_VDD
+DACC_VDD
1
C816
0.1U_0402_10V7K~D
+DACA_VDD
2
1
+1.1V_GFX_PCIE
C798
1U_0402_6.3V6K~D
2
2
1
Place near Balls
C832
4700P_0402_25V7K~D
1
2
1
2
1
L65
10UH +-10% LQH2MCN100K02L_0805~D
Place near GPU
C815
0.1U_0402_10V7K~D
2
VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
2
1
PEX_IOVDDQ = 1600mA
C831
4700P_0402_25V7K~D
1
C846
0.1U_0402_10V7K~D
2
C845
0.1U_0402_10V7K~D
1
C844
1U_0402_6.3V6K~D
2
C843
4.7U_0603_6.3V6M~D
1
A12
B12
C12
D12
E12
F12
1
10 mil
Place near Balls
C830
4700P_0402_25V7K~D
+3.3V_RUN
2
C814
0.022U_0402_16V7K~D
2
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
C813
0.022U_0402_16V7K~D
2
1
C826
0.1U_0402_10V7K~D
2
1
C825
0.1U_0402_10V7K~D
2
1
C824
0.1U_0402_10V7K~D
2
1
C823
0.1U_0402_10V7K~D
2
1
Part 4 of 5
2
1
C797
1U_0402_6.3V6K~D
2
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
AC9
AD7
AD8
AE7
AF7
AG7
AB13
AB16
AB17
AB7
AB8
AB9
AC13
AC7
AD6
AE6
AF6
AG6
1
C796
0.1U_0402_10V7K~D
2
1
C811
0.47U_0402_6.3V4Z~D
2
1
C810
0.47U_0402_6.3V4Z~D
1
C809
0.47U_0402_6.3V4Z~D
2
C808
0.47U_0402_6.3V4Z~D
1
J10
J12
J13
J9
L9
M11
M17
M9
N11
N12
N13
N14
N15
N16
N17
N19
N9
P11
P12
P13
P14
P15
P16
P17
R11
R12
R13
R14
R15
R16
R17
R9
T11
T17
T9
U19
U9
W10
W12
W13
W18
W19
W9
C795
0.1U_0402_10V7K~D
2
C1024
10U_0805_10V4Z~D
2
C822
0.1U_0402_10V7K~D
2
1
C821
0.1U_0402_10V7K~D
2
1
C812
0.1U_0402_10V7K~D
2
1
C829
0.1U_0402_10V7K~D
1
1
1
+FB_PLLVDD
C828
1U_0402_6.3V6K~D
2
C827
4.7U_0603_6.3V6M~D
1
= 40 mA
2
2
C807
0.47U_0402_6.3V4Z~D
+1.1V_GFX_PCIE
FB_PLLVDD
L44
BLM18AG121SN1D_0603~D
1
2
1
1
C793
4.7U_0603_6.3V6M~D
C
2
C806
0.47U_0402_6.3V4Z~D
2
C805
0.47U_0402_6.3V4Z~D
1
1
2
U44D
Place near Balls
C792
4.7U_0603_6.3V6M~D
2
C791
4.7U_0603_6.3V6M~D
1
+PEX_PLLVDD
1
+1.1V_GFX_PCIE
PEX_PLLVDD = 100mA
C782
4.7U_0603_6.3V4Z~D
+GPU_CORE
+1.1V_GFX_PCIE
PEX_IOVDD = 500mA
C781
1U_0402_6.3V6K~D
Q119A
2N7002DW-T/R7_SOT363-6
S
C780
1U_0402_6.3V6K~D
2
<41,56> GFX_CORE_PWRGD
D
GFX_CORE_PWRGD_1.8V# 2
G
C779
0.1U_0402_10V7K~D
2
2
C778
0.1U_0402_10V7K~D
GFX_CORE_PWRGD_1.8V# 5
1
R814
20K_0402_5%~D
D
1
Q119B
2N7002DW-T/R7_SOT363-6
+1.8V_RUN_GPU
C1010
10U_0805_10V4Z~D
1.8V_RUN_ENABLE
C314
4700P_0402_25V7K~D
R815
100K_0402_5%~D
Q117
STS11NF30L_SO8~D
1
2
3
@ Q118
2N7002W-7-F_SOT323-3~D
@ R813
1K_0402_5%~D
+3.3V_ALW2
R812
100K_0402_5%~D
1
+1.8V_RUN_GPU
8
7
6
5
4
3
Title
NVG98 POWER
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
52
of
71
5
4
3
2
1
D
D
U44E
C
B
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
Part 5 of 5
GND
AC11
AC14
AC17
AC2
AC20
AC23
AC26
AC5
AC8
AF11
AF14
AF17
AF2
AF20
AF23
AF26
AF5
AF8
B11
B14
B17
B2
B20
B23
B26
B5
B8
E11
E14
E17
E2
E20
E23
E26
E5
E8
H2
H5
J11
J14
J17
K19
K9
L11
L12
L13
L14
L15
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
L16
L17
L2
L5
M12
M13
M14
M15
M16
P19
P2
P23
P26
P5
P9
T12
T13
T14
T15
T16
U11
U12
U13
U14
U15
U16
U17
U2
U23
U26
U5
V19
V9
W11
W14
W17
Y2
Y23
Y26
Y5
C
B
RFU_GND
AC6
GND_SENSE
W16
GND_SENSE
FBCAL_PU_GND
FBCAL_TERM_GND
A15
B16
FB_CAL_PU_GND
R707
R703
1
2
1
2
0_0402_5%~D
30.1_0402_1%
NB9M-GS_BGA533~D
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
NVG98 GND
Size
4
3
http://hobi-elektronika.net
Rev
0.8
LA-3803P
Date:
5
Document Number
2
Thursday, June 12, 2008
Sheet
1
53
of
71
5
4
3
2
1
FBAD[0:63]
FBAD[0:63] <51,55>
U46
U47
FBA_CMD10
FBA_CMD18
+1.8V_RUN_GPU
1
2
1
FBA_VREF_A
1
2
C872
0.047U_0402_16V4Z~D
R738
1K_0402_1%~D
2
R734
1K_0402_1%~D
D
<51>
<51>
CLKA0#
CLKA0
<51,55> FBA_CMD11
+1.8V_RUN_GPU
L2
L3
BA0
BA1
FBA_CMD14
FBA_CMD16
FBA_CMD17
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD21
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
FBA_CMD3
FBA_CMD1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CLKA0#
CLKA0
K8
J8
CK
CK
FBA_CMD11
K2
CKE
FBA_CMD8
L8
CS
FBA_CMD9
K3
WE
FBA_CMD15
K7
RAS
FBA_CMD25
L7
CAS
DQMA#1
DQMA#0
F3
B3
LDM
UDM
FBA_CMD12
K9
ODT
DQSA_WP1
DQSA_RN1
F7
E8
LDQS
LDQS
1
2
R749
60.4_0402_1%~D
DQSA_WP0
DQSA_RN0
B7
A8
UDQS
UDQS
R750
475_0402_1%~D
FBA_VREF_A
J2
VREF
UDQ7
UDQ6
UDQ5
UDQ4
UDQ3
UDQ2
UDQ1
UDQ0
LDQ7
LDQ6
LDQ5
LDQ4
LDQ3
LDQ2
LDQ1
LDQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
FBAD7
FBAD3
FBAD4
FBAD0
FBAD2
FBAD6
FBAD1
FBAD5
FBAD10
FBAD15
FBAD8
FBAD13
FBAD12
FBAD9
FBAD14
FBAD11
+1.8V_RUN_GPU
@
2
C
2
FBA_CMD27
@
@
1
C876
0.01U_0402_16V7K~D
1
2
R751
60.4_0402_1%~D
2
D2 32M16/400 HYB18T512161B2F-25_ FBGA84~D
+1.8V_RUN_GPU
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CLKA0#
CLKA0
K8
J8
CK
CK
FBA_CMD11
K2
CKE
FBA_CMD8
L8
CS
FBA_CMD9
K3
WE
FBA_CMD15
K7
RAS
FBA_CMD25
L7
CAS
DQMA#2
DQMA#3
F3
B3
LDM
UDM
FBA_CMD12
K9
ODT
DQSA_WP2
DQSA_RN2
F7
E8
LDQS
LDQS
DQSA_WP3
DQSA_RN3
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
UDQ7
UDQ6
UDQ5
UDQ4
UDQ3
UDQ2
UDQ1
UDQ0
LDQ7
LDQ6
LDQ5
LDQ4
LDQ3
LDQ2
LDQ1
LDQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
BA0
BA1
DQMA#[0:7]
FBAD26
FBAD29
FBAD24
FBAD31
FBAD28
FBAD27
FBAD30
FBAD25
FBAD17
FBAD23
FBAD19
FBAD21
FBAD22
FBAD18
FBAD20
FBAD16
DQMA#[0:7]
DQSA_WP[0:7]
<51,55>
DQSA_WP[0:7] <51,55>
DQSA_RN[0:7]
DQSA_RN[0:7] <51,55>
FBA_CMD[0..27]
FBA_CMD[0..27] <51,55>
D
+1.8V_RUN_GPU
C
D2 32M16/400 HYB18T512161B2F-25_ FBGA84~D
1
2
2
C903
0.1U_0402_10V7K~D
2
2
1
B
C907
0.01U_0402_16V7K~D
1
1
C902
0.1U_0402_10V7K~D
2
2
C906
0.01U_0402_16V7K~D
2
1
1
C901
0.1U_0402_10V7K~D
1
2
C905
0.01U_0402_16V7K~D
2
2
1
C884
0.1U_0402_10V7K~D
1
1
C904
0.01U_0402_16V7K~D
2
2
C887
0.01U_0402_16V7K~D
1
C886
0.01U_0402_16V7K~D
2
C885
0.01U_0402_16V7K~D
1
2
1
C883
0.1U_0402_10V7K~D
2
1
C882
0.1U_0402_10V7K~D
2
1
C881
4.7U_0603_6.3V6M~D
1
Place below decoupling caps close U46
C900
4.7U_0603_6.3V6M~D
2
FBA_CMD27
C899
4.7U_0603_6.3V6M~D
1
2
C912
0.1U_0402_10V7K~D
2
2
1
C916
0.01U_0402_16V7K~D
1
1
C893
0.1U_0402_10V7K~D
2
C915
0.01U_0402_16V7K~D
2
1
C892
0.1U_0402_10V7K~D
2
1
C914
0.01U_0402_16V7K~D
1
2
C891
0.1U_0402_10V7K~D
2
2
1
C913
0.01U_0402_16V7K~D
1
1
C911
0.1U_0402_10V7K~D
2
2
C896
0.01U_0402_16V7K~D
1
C895
0.01U_0402_16V7K~D
2
C894
0.01U_0402_16V7K~D
1
2
1
C910
0.1U_0402_10V7K~D
2
1
C890
4.7U_0603_6.3V6M~D
2
1
FBA_CMD14
FBA_CMD16
FBA_CMD17
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD21
FBA_CMD22
FBA_CMD24
FBA_CMD0
FBA_CMD2
FBA_CMD3
FBA_CMD1
+1.8V_RUN_GPU
Place below decoupling caps close U47
C909
4.7U_0603_6.3V6M~D
1
C908
4.7U_0603_6.3V6M~D
B
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
L2
L3
FBA_VREF_A
1
C874
0.047U_0402_16V4Z~D
CLKA0#
A2
E2
L1
R3
R7
R8
1
2
CLKA0
@
1
R748
0_0402_5%~D
FBA_CMD10
FBA_CMD18
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
NVG98 External GDDR2-A
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
54
of
71
5
4
3
2
1
FBAD[0:63]
FBAD[0:63] <51,54>
U48
2
FBA_VREF_B
1
2
C934
0.047U_0402_16V4Z~D
R765
1K_0402_1%~D
1
2
D
R761
1K_0402_1%~D
1
+1.8V_RUN_GPU
<51>
<51>
CLKA1#
CLKA1
<51,54> FBA_CMD11
FBA_CMD10
FBA_CMD18
L2
L3
FBA_CMD14
FBA_CMD16
FBA_CMD17
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD21
FBA_CMD6
FBA_CMD5
FBA_CMD4
FBA_CMD13
FBA_CMD3
FBA_CMD1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CLKA1#
CLKA1
K8
J8
CK
CK
FBA_CMD11
K2
CKE
BA0
BA1
FBA_CMD8
L8
CS
FBA_CMD9
K3
WE
FBA_CMD15
K7
RAS
FBA_CMD25
L7
CAS
DQMA#4
DQMA#5
F3
B3
FBA_CMD12
K9
LDM
UDM
UDQ7
UDQ6
UDQ5
UDQ4
UDQ3
UDQ2
UDQ1
UDQ0
LDQ7
LDQ6
LDQ5
LDQ4
LDQ3
LDQ2
LDQ1
LDQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
FBAD43
FBAD46
FBAD41
FBAD44
FBAD45
FBAD40
FBAD47
FBAD42
FBAD36
FBAD39
FBAD35
FBAD34
FBAD33
FBAD32
FBAD37
FBAD38
+1.8V_RUN_GPU
ODT
+1.8V_RUN_GPU
C
2
DQSA_WP4
DQSA_RN4
F7
E8
1
2
1
2
@ R775
60.4_0402_1%~D
B7
A8
UDQS
UDQS
FBA_VREF_B
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
1
CLKA1#
FBA_CMD27
1
2
C937
0.01U_0402_16V7K~D
1
2
@ R777
60.4_0402_1%~D
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
L2
L3
BA0
BA1
FBA_CMD14
FBA_CMD16
FBA_CMD17
FBA_CMD20
FBA_CMD19
FBA_CMD23
FBA_CMD21
FBA_CMD6
FBA_CMD5
FBA_CMD4
FBA_CMD13
FBA_CMD3
FBA_CMD1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CLKA1#
CLKA1
K8
J8
CK
CK
FBA_CMD11
K2
CKE
FBA_CMD8
L8
CS
FBA_CMD9
K3
WE
FBA_CMD15
K7
RAS
FBA_CMD25
L7
CAS
DQMA#7
DQMA#6
F3
B3
LDM
UDM
FBA_CMD12
K9
ODT
DQSA_WP7
DQSA_RN7
F7
E8
LDQS
LDQS
DQSA_WP6
DQSA_RN6
B7
A8
UDQS
UDQS
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
FBA_VREF_B
1
2
@
D2 32M16/400 HYB18T512161B2F-25_ FBGA84~D
C958
0.047U_0402_16V4Z~D
DQSA_WP5
DQSA_RN5
R776
475_0402_1%~D
FBA_CMD10
FBA_CMD18
UDQ7
UDQ6
UDQ5
UDQ4
UDQ3
UDQ2
UDQ1
UDQ0
LDQ7
LDQ6
LDQ5
LDQ4
LDQ3
LDQ2
LDQ1
LDQ0
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
J1
J7
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
FBAD52
FBAD49
FBAD55
FBAD48
FBAD51
FBAD53
FBAD50
FBAD54
FBAD61
FBAD58
FBAD62
FBAD57
FBAD59
FBAD60
FBAD56
FBAD63
DQMA#[0:7]
DQSA_WP[0:7]
<51,54>
DQSA_WP[0:7] <51,54>
DQSA_RN[0:7]
DQSA_RN[0:7] <51,54>
FBA_CMD[0..27]
FBA_CMD[0..27] <51,54>
D
+1.8V_RUN_GPU
C
LDQS
LDQS
@ R774
0_0402_5%~D
CLKA1
DQMA#[0:7]
U49
FBA_CMD27
D2 32M16/400 HYB18T512161B2F-25_ FBGA84~D
+1.8V_RUN_GPU
+1.8V_RUN_GPU
Place below decoupling caps close U48
1
2
2
C973
0.1U_0402_10V7K~D
2
2
1
B
C977
0.01U_0402_16V7K~D
1
1
C954
0.1U_0402_10V7K~D
2
2
C976
0.01U_0402_16V7K~D
1
1
C972
0.1U_0402_10V7K~D
2
2
C975
0.01U_0402_16V7K~D
1
1
C971
0.1U_0402_10V7K~D
2
2
C974
0.01U_0402_16V7K~D
1
1
C953
0.1U_0402_10V7K~D
2
2
C957
0.01U_0402_16V7K~D
1
C956
0.01U_0402_16V7K~D
2
C955
0.01U_0402_16V7K~D
1
2
1
C952
0.1U_0402_10V7K~D
2
1
C951
4.7U_0603_6.3V6M~D
2
1
C970
4.7U_0603_6.3V6M~D
2
2
1
C969
4.7U_0603_6.3V6M~D
1
1
C964
0.1U_0402_10V7K~D
2
2
Place below decoupling caps close U49
C968
0.01U_0402_16V7K~D
1
1
C963
0.1U_0402_10V7K~D
2
2
C967
0.01U_0402_16V7K~D
1
1
C962
0.1U_0402_10V7K~D
2
2
C966
0.01U_0402_16V7K~D
1
1
C945
0.1U_0402_10V7K~D
2
2
C965
0.01U_0402_16V7K~D
1
1
C944
0.1U_0402_10V7K~D
2
2
C948
0.01U_0402_16V7K~D
1
C947
0.01U_0402_16V7K~D
2
C946
0.01U_0402_16V7K~D
1
2
1
C943
0.1U_0402_10V7K~D
2
1
C942
4.7U_0603_6.3V6M~D
2
1
C961
4.7U_0603_6.3V6M~D
1
C960
4.7U_0603_6.3V6M~D
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Title
NVG98 External GDDR2-B
Size
Date:
2
Document Number
Rev
0.8
LA-3803P
Thursday, June 12, 2008
Sheet
1
55
of
71
3
2
1
PL17
FBMJ4516HS720NT_1806~D
1
2
16
FB
15
1
PC183
2200P_0402_50V7K~D
2
1
2
PR288
162K_0402_1%~D
2
2
2
2
+3.3V_RUN
PC253
330P_0402_50V7K
GNDA_GPU_CORE
2
1
PR286
10K_0402_5%~D
GNDA_GPU_CORE
1
2
1
2
D
3
<50> GPU_VID_1
@ PJP35
+GPU_CORE
2
PR285
10K_0402_5%~D
1
PQ49
BSS138W-7-F_SOT323~D
PC252
0.01U_0402_16V7K~D
2
S
2
G
1
1
D
2
1.17V
1
1
PR214
100K_0402_5%~D
0.9V 1.09V
0
1
0
0
1
1
PC199
0.01U_0402_16V7K~D
1
2
2
PR213
10K_0402_5%~D
GPU_VID_0
GPU_VID_1
PAD-OPEN 43X118
2
PR289
68.1K_0402_1%~D
GNDA_GPU_CORE
PR212
10K_0402_5%~D
GNDA_GPU_CORE
2
1
B
1
1
+3.3V_RUN
PC197
820P_0402_50V7K~D
1
PR209
46.4K_0402_1%
1
2
GNDA_GPU_CORE
2
2
1
PR211
4.87K_0402_1%~D
@ PJP11
+VCC_GFX_CORE
2
PR207
75K_0402_1%~D
PR210
487_0402_1%~D
1
2
GNDA_GPU_CORE
1
PR203
90.9K_0402_1%~D
1
PR205
49.9K_0402_1%~D
GNDA_GPU_CORE
2
1
@ PR206
0_0402_5%~D
<50> GPU_VID_0
GNDA_GPU_CORE
GPU_VDD_SENSE <52>
PR201
26.1K_0402_1%
2
GNDA_GPU_CORE
1
1
ILIM
4
PR204
100K_0402_1%~D 2
2
PAD-OPEN1x1m
PC198
0.01U_0402_16V7K~D
2
2
C
@
GNDA_GPU_CORE
1
@
1 2
5
6
7
8
3
2
1
2
1
@ PR202
0_0402_5%~D
GFX_REF
3
1
1
SS
2
1
1
GNDA_GPU_CORE
PJP36
1
8
1
PR208
100K_0402_5%~D
2
REF
SKIP
VTTR
25
10
GND
VTTS
2
@
PC194
0.22U_0402_6.3V6K~D
TON
9
PC195
1U_0603_10V6K~D
2
1
+3.3V_RUN
B
VTT
GND
PC193
22U_0805_6.3VAM~D
2
PGND2
12
29
2
2
PC192
22U_0805_6.3VAM~D
+1.1VRUNP
11
+
1
VOUT
REFIN
PC196
0.047U_0402_10V7K~D
24
1
14
PC191
10U_0805_6.3V6M~D
1
+
2
2
23
MAX8632ETI+_TQFN28~D
VTTI
PR282
2.2_1206_1%
2
+VCC_GFX_CORE
1
1
PGND1
4
1
1
2
21
1000P_0603_50V7K
PC257
PC190
1000P_0402_50V7K~D 1000P_0402_50V7K~D
DL
PC250
2
STBY
13
1
1
PL18
0.88UH_MPC1040LR88C_17A_20%~D
1
2
PQ48
FDS6676AS_NL_SO8~D
7
+1.8V_RUN_GPU
1
2
5
6
7
8
PC186
0.22U_0603_10V7K~D
1
2
PC200
2200P_0402_50V7K~D
2
1
2
D
D
D
D
S
S
S
G
PC188
330U_D2E_2.5VM_R9~D
19
GPU_CORE
Thermal Design Current:7.7A
Peak current: 11A
OCP min: 12A
1
LX
D
2
3
2
1
2
28
22
VDD
DH
1
PAD-OPEN 43X118
PC187
330U_D2E_2.5VM_R9~D
SHDN
18
PR198
2.2_0603_1%~D
1
2
4
1
C
POK2
27
POK1
20
1
+PWR_SRC
@ PJP10
PQ47
FDS8880_NL_SO8~D
3
<37> GFX_CORE_ON
1
0_0402_5%~D
1
0_0402_5%~D
6
OVP/ UVP
2
2
@ PR199
2
PR200
5
1.1V_GFX_PWRGD
GFX_REF
<41> 1.1V_GFX_PWRGD
<19,28,37,40,41> RUN_ON
GFX_CORE_PWRGD
BST
2
2
PR267
10_0402_5%~D
<41,52> GFX_CORE_PWRGD
VIN
TP0
PU14
17
AVDD
@ PR197
61.9K_0402_1%~D
26
GNDA_GPU_CORE
RB751V-40_SOD323~D
1
1
2
2
PD23
1
1
PC184
1U_0603_10V6K~D
PC185
2.2U_0603_6.3V6K~D
GFX_+5V_RUN
2
+5V_RUN
PR196
10_0805_5%~D
1
2
1
PC182
0.1U_0603_25V7K~D
D
PC181
10U_1206_25V6M~D
1
PC180
10U_1206_25V6M~D
+GPU_PWR_SRC
PC189
0.1U_0402_10V7K~D
4
PR287
100K_0402_5%~D
5
S
PQ60
BSS138W-7-F_SOT323~D
2
G
PAD-OPEN 43X118
A
A
GNDA_GPU_CORE
@ PJP37
+1.1VRUNP
1
2
output voltage adjustable network
+1.1V_GFX_PCIE
PAD-OPEN 43X79
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
NVG72M VDD_CORE
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
56
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
1
2
3
Date
Request
Owner
HW
HW
08/14/2007
08/14/2007
Compal
Compal
Change P/N to 8009CN
For vender request
HW
08/14/2007
Compal
Part Number issue
Title
36
36
29,10~15
4
36
HW
08/14/2007
Compal
For vender request
5
6
36
41
HW
HW
08/14/2007
08/16/2007
Compal
Compal
For vender request
Fix power sequence issue.
7
21
HW
08/16/2007
DELL
Follow DELL suggection.
8
52,53,
54,55
HW
08/16/2007
Compal
Follow Nvidia suggection.
9
38
HW
08/16/2007
DELL
10
37
HW
08/16/2007
DELL
11
21
HW
08/16/2007
DELL
12
13
14
38
6,50
46
HW
HW
HW
08/16/2007
08/16/2007
08/16/2007
Compal
Compal
Compal
15
28
HW
08/16/2007
Compal
16
17
18
31
24
42
HW
HW
HW
08/20/2007
08/20/2007
08/20/2007
Compal
Compal
Compal
C
19
33
HW
08/28/2007
Compal
20
38
HW
08/28/2007
Compal
21
29
HW
08/28/2007
Compal
22
18
HW
08/30/2007
Compal
23
29, 36
HW
08/30/2007
Compal
24
25
26
31
38
36
HW
HW
HW
08/30/2007
08/30/2007
08/30/2007
Compal
Compal
Compal
27
29
HW
08/30/2007
Compal
28
29
HW
08/30/2007
Compal
29
31
HW
08/30/2007
Compal
30
31
32
10
37
35
HW
HW
HW
08/30/2007
08/30/2007
08/31/2007
HW
09/01/2007
B
A
Issue Description
33
22,24
Solution Description
Rev.
X01
X01
Change U33
Change R799 from 5 to 0ohm
1. Change U23 from 82567LF to 82567LM
2. Change U2 from Teenah to Cantiga
1. Change R476 from 2.2K to 510Kohm
2. Change R488 from 1K to 330Kohm
Add L77
Depop R630, R809
Add C1036, C1037, C1038, C1039. Change pop C271~274 from 0.1u cap to
0 ohm resistor.
1. Change R706, R703 from 40.2ohm to 30ohm.
2. Change R750, R776 from 121ohm to 240ohm.
Need to add a 100k pull up to RTC_CELL on
CELL_CHARGER_DET# at the 5035.
Follow New GPIO MAPand add
DET_PCCRD_EXPSCRD# for Expresscard/Cardbus
detection
Follow DELL request to remove common mode
chokes and 0ohm resistor.
U57, U59 power and GND reverse
CLK_NVSS_27M not link to GPU
DDR reference voltage no soure
BOM option error for use TPA6040 audio
amplifier
For vender request
For vender request
For vender request
Follow SMSC request to modify JTAG_RST#
control schematic.
Follow USB Switch Specification and change
the supply volatge from +5V to +3.3V.
LPC address conflict DOCK side SIO
LPC47N237
Avoid +RTC_CELL drop to 2.5V and +3.3V_SUS
have leakage issue
X01
X01
X01
X01
X01
X01
Add a 100k pull up to +RTC_CELL
X01
Add a pull-up and pull-down resistor option(R882, R883) to GPIOE[4] for
Expresscard/Cardbus pop option.
X01
Remove L70~L74, R863~R872
X01
U57,U59 pin3 contact to GND and pin5 contact to +RTC_CELL
Stuff R38,R686
Change V_DDR_MCH_REF to +V_DDR_MCH_REF
X01
X01
X01
Stuff C443,C449 and no-stuff R362,R366
X01
Change R802 & R803 to 1@,R671 & R739 to 2@
Change RP2 from 100K to 10K
X01
X01
X01
C
Change Q98 & Q116 from BSS138W to 2N7002, Q120-Q122
pin 3 pull up from +5V_ALW to +5V_RUN
Add C1040 and change R579 from 100Kohm to 10Kohm, R585 from
1Kohm to 100ohm and no-stuff.
X02
Change U54 pin 8 from +5V_CHGUSB to +3.3V_SUS
X02
Reserve 4.7K pull-down of R884 on U24 pin9 for select LPC
address of 4E/4F or 2E/2F.
U3 pin 21 add R887 0 ohm, U3 pin 22-24 reserved pull up R885, R886 &
R888 to +RTC_CELL
X02
B
X02
U32 pin B5, B4 add @R894, pin P10, R11, N10, R12, P11 & M9 add
@R895-@R897, pin M9 add R899 0ohm pull down resistor
X02
Schematic issue
Follow SMSC request
For JTAG debug purpose
VCC3EN# connect to U27 pin2, VCC5EN# connect to U27 pin 1
Add R900 100K ohm pull high to +RTC_CELL
SBOOT reserved R898 pull down to GND
X02
X02
X02
U24 pin 28 C_TPM_LPC_EN add R892 pull down 4.7K ohm to
GND, and add @R893 to EC & USH
Change signal name from AUD_EAPD# to AUD_EAPD
Change R417 from 10K_5% to 10K_1%
Compal
Compal
Compal
Add pop options for China TPM for request
from DELL issue item SCH161931
AUD_EAPD is high event not low event.
REXT of R5C847 pinB14 pull-down not
follow spec
Add test point for test
Change Board ID to X02
Change E-Dock connector location
Compal
Follow DELL issue item SCH162009
Use JTAG to debug USH request
D
X02
X02
X02
Add test point in U2 RSVD1-RSVD25.
Pop R530, R534, de-pop R529, R535
Change from JP1 to JDOCK1
Change R817, R212 from 8.2K ohm to 100K ohm,
R823 from 10K ohm to 100K ohm
X02
X02
X02
A
X02
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Changed-List History 1
Size
Document Number
Custom
2
Rev
0.8
LA-3803P
Date:
Thursday, June 12, 2008
Sheet
1
57
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
34
Title
36
HW
Date
09/01/2007
Request
Owner
Compal
D
Issue Description
Solution Description
Follow DELL issue item SCH162011 Remove Contactless
Smart Cart resistors and traces to the Touch Pad
Connector
35
36
HW
09/01/2007
Compal
For vender request
36
37
38
36
27
24
HW
HW
HW
09/01/2007
09/01/2007
09/01/2007
Compal
Compal
Compal
For vender request
For vender request
For vender request
39
23
HW
09/01/2007
DELL
Follow EE WORK ITEM SCH162092
HW
09/01/2007
DELL
Follow DELL issue item TASK162008
40
36,39
correct RTC PAID
41
21
HW
09/01/2007
DELL
Follow DELL issue item SCH162035
42
38
HW
09/01/2007
DELL
Follow DELL issue item SCH162105 Fix ACAV_IN_DOCK# for
battery discharge issue
C
B
A
43
7
HW
09/01/2007
Intel
Follow Debug port design guide for Santa Rosa and
Montevina Platforms_Rev0.95 for ITP700Flex debug port
44
35
HW
09/01/2007
DELL
Follow DELL issue item SCH161983 Fix Slice detect circuit
45
46
38
42
HW
HW
09/01/2007
09/01/2007
DELL
Compal
For DELL request
Correct net name for sniffer blue led.
47
37
HW
09/01/2007
Compal
Correct VGA_IDENTIFY
48
49
42
35
HW
HW
09/03/2007
09/03/2007
Compal
Compal
For vender request
For vender request
50
36
HW
09/04/2007
Compal
Change net name
51
52
22,24
29
HW
HW
09/04/2007
09/04/2007
Compal
Compal
Add test point
BOM control add 4@ for China TPM
53
31,36
HW
09/04/2007
Compal
Add test point
54
18
HW
09/05/2007
Compal
Solved +3.3V_SUS backdrive issue.
55
31
HW
09/05/2007
Compal
Fix 1394 can't detec issue
56
29
HW
09/05/2007
Compal
Follow CRB to reserved pull up and pull down reisitor for
JTAG
57
27
HW
09/05/2007
Compal
Correct net name
58
21
HW
09/06/2007
Compal
Follow DELL issue item SCH161967 System DP off circuit.
59
60
42
26
HW
HW
09/06/2007
09/06/2007
Compal
Compal
For vender request
Schematic issue.
Rev.
Remove R858, R875, R876, R859
X02
D
Remove R735
De-pop R555, R848, R20 and add @R831, R855 0 ohm
Remove L77
De-pop R334, R335
R293 change to 10k ohm
Add R905,906,907,908,Q96 and cheage the pull up power
rail from +3.3V_RUN to +3.3V_ALW_ICH for RTC_BAT_DET#
Remove "CONTACTLESS_DET" from JTP1 pin 20 and connect to
JCS1 pin6 ,add pull-up resistor R910 100Kohm to
+3.3V_ALW.
1. Stuff C271,C272 C273,C274 with .1 uF.
2. Change C1036, C1037, C1038, and C1039 to 0 ohm
of R901~904
1.Change DOCK_DET# pull-up from +3.3V_ALW to +RTC_CELL
2.Change ACAV_IN_DOCK# pull-up from +DC_IN to +3.3V_ALW2
Change ITP_TDO,ITP_TMS,ITP_TDI,ITP_TRST#,ITP_TCK of
R62,R64,R65,R66,R67 pull-up from 56 to 51ohm and add
ITP_BPM#5 of R912 pull-up 51ohm to +1.05V_VCCP. Change
H_RESET# serial resistor to 1K ohm
a). Short jdock1 pin 141 to pin 143.
b). Keep the net name SLICE_BAT_PRES#
c). Remove the connection to EC5028 pin 28.
HOST_DEBUG_TX Add R911 100K ohm pull up to +3.3V_ALW
Correct net name from SNIFFER_GREEN# to SNIFFER_BLUE#
Correct VGA_IDENTIFY from pull low for UMA to Pull
high to +3.3V_ALW for DIS.
Change D43 pin2 net name from R_WPAN_LED to WPAN_LED
C1033 & C1034 change to 0603 25V
Change net name from SC_DET# to SC_DET
JSC1 pin1 add R913 4.7K ohm
GNT2#/GPIO53, SUS_STAT#/LPCPD#,
Change C484-C486, R381, R383, R893, U24, R892 to 4@
UDIO1, UDIO2, UDIO5, RI_OUT#/PME#, FIL0, MDIO1,MDIO2,
MDIO5,MDIO6, MDIO18, MDIO19, SC_FCB_ENB
Reserved R914 0ohm 0603 resister and connect to +3.3_ALW
Change J1394 from 5 pin to 6 pin and connect pin 1 to
GND
Reserved R890,R916,R915 200ohm to +3.3V_LAN, R891
1Kohm to GND and R889 0ohm to GND
Correct net name from DAI_BCLK, DAI_LRCK, DAI_DO,
DAI_12MHZ, I2S_DI to DAI_BCLK#, DAI_LRCK#, DAI_DO#,
DAI_12MHZ#, I2S_DI# and update U17 symbol.
Add U62, @R917, @R918,R919,C0141, and change R189 from
pull down to pull up +3.3V_RUN, connect DP_MUX_PD# from
U9 pin30 to U62 pin 1 and change DP_MUX_PD# net name to
DP_MB_EN, connect DP_MB_HPD from U9 pin 40 to U62 pin2,
connect U62 pin 4 to U9 pin 40
change R57 from 22.6ohm to 1Kohm.
change C380 and C381 from 3900pF to 0.01UF.
X02
X02
X02
X02
X02
X02
X02
X02
C
X02
X02
X02
X02
X02
X02
X02
X02
X02
X02
B
X02
X02
X02
X02
X02
X02
A
X02
X02
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
58
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
61
62
63
37
18
28
HW
HW
HW
09/06/2007
09/06/2007
09/06/2007
DELL
Compal
Compal
For customer request
Add net name
Schematic issue
64
29
HW
09/06/2007
DELL
Disable USH TPM & enable China TPM
65
36,37
HW
09/06/2007
Compal
For vender request
65
24,33
37,38
39,40
41
HW
09/08/2007
DELL
Follow M09 GPIO Map_0907
Change @R788 pull up from +3.3V_ALW to +3.3V_RUN
Add net name for +RTC_CELL U3 pin21
Stuff R368 and no-stuff R367
Stuff R841,R474,R892,R893 and no-stuff
r483,R464,R466,R788,R750,R723,R724,R732,R733
Change @R464, @R466, R705, R723, R724, R732, R733 to 5@,
SP_TPM_LPC_EN add pull down R920 10K ohm, pop R841
67
68
69
70
27,37
50
24
33,37,38
24
HW
09/08/2007
Compal
Rename net name
HW
HW
HW
09/10/2007
09/10/2007
09/11/2007
Compal
Compal
DELL
For DELL EE work item: SCH162359
Change SPI ROM P/N
ESATA USB charger control signal issue
HW
09/11/2007
DELL
Follow DELL request
72
10,16
17,18
23,24
HW
09/11/2007
DELL
Follow DELL request for PM_EXTTS#
HW
09/11/2007
Compal
Aviod leakage issue
73
37
HW
09/11/2007
Compal
74
36
HW
09/11/2007
Broadcom
Add pull-up resistor for DELL_ESATA_PWR_EN#
initial
Follow vendor request for use smard card
controller of 73S8009CN
X02
X02
C
1. Rename DOCK_MIC_DET# to DOCK_MIC_DET
2. Rename DOCK_HP_DET# to DOCK_HP_DET
Change R825 from 45.3K_1% to 15K_1%
Change U12,U13 to SA00001OZ0L
X02
X02
X02
1. Add serial resitor of R928 for CELL_CHARGER_DET# and R927,C1042
for EN_CELL_CHARGER_DET# and wire-and contact to JESA1 pin16.
2. Change U29 pin3,4 from ESATA_USB_PWR_EN# to DELL_ESATA_PWR_EN#
3. Change U53 pin3,4 from N_CELL_CHARGER_DET# to ESATA_USB_PWR_EN#
X02
X02
A
B
X02
X02
Add pull-up resistor of R929 to pull-up +3.3V_ALW
1.
2.
3.
4.
5.
D
X02
Remove SIO_EXT_SCI# on ICH9M pinC12(GPIO12) and U36
pin43(GPIO052) and contact from ICH9M pinAG19(GPIO1) to U36
pin66(GPIO100)
Add serial resistor of R926 from U3 pin13 contact to U2
pinN33,P32 and remove trace of PM_EXTTS#[0,1] contact to DIMM
1. Change SIO_EXT_SCI# pull-up from +3.3V_ALW_ICH to +3.3V_RUN
2. Change TPM_ID pull-up from +3.3V_ALW_ICH to +3.3V_RUN
3. Change SNIFFER_DET# pull-up from +3.3V_ALW_ICH to +3.3V_RUN
4. Change IO_LOOP from +3.3V_RUN to +3.3V_ALW_ICH
5. Change RTC_BAT_DET# from +3.3V_ALW_ICH to +3.3V_RUN
B
71
X02
X02
X02
1. Change MEC5035 pin43(GPIO52) from SIO_EC_SCI2# to SIO_EXT_SCI#
and contact to ICH9M pinC12(GPIO12) and pinAG19(GPIO1)
2. Remove MEC5035 pin66(GPIO100/nEC_SCI) off-page
3. Change ICH9M pinAH21(GPIO6) form SIO_EC_SCI2# to TPM_ID and
add pull-down of R922 for China TPM(4@), stuff R273 for USH
TPM(5@) and change to 100K
4. Change ICH9M pinC21(GPIO13) from ENERGY_DET# to
CONTACTLESS_DET# and change R822 from 20K to 100K.Remove ECE1088
pin10 and R910.
5. Change CELL_CHARGER_DET# from MEC5035 pin126(VCI_IN1#) to
ECE5028 pin78(GPIOB6)
6. Rename MEC5035 pin126(VCI_IN1#) from CELL_CHARGER_DET# to
EN_CELL_CHARGER_DET# and contact to U53 pin3,4
7. Rename USB_CHARGER_PWR_EN# to ESATA_USB_PWR_EN# and contact to
U29 pin3,4 and add pull-up 100K of R923 to +3.3V_ALW
8. Remove ECE5028 pin82 off-page for DELL_ESATA_PWR_EN#
9. Change MEC5035 pin42(GPIO051) from 3.3V_SUS_ON to SUS_ON and
remove pin34(GPIO041) from SUS_ON to NC
10. Remove MEC5035 pin118(BGPO0) to NC
C
66
Rev.
X02
Contact of GPIO14_TER_ON/OFF from U33 pin24 to U32 pinC4
Contact AUX1UC from U33 pin2 to U32 pinJ14
Contact AUX2UC from U33 pin3 to U32 pinJ15
Stuff R768,R769,R490
Change netname from GPIO1_TER_ON/OFF to UART_TX/GPIO1
X02
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
59
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
75
39
HW
09/11/2007
Compal
ECE1088 & JCS1 de-pop option
De-pop U38, C676, C677, R650, R826, JCS1
X02
76
18
HW
09/11/2007
Compal
Change EMC4002 part number
From SA00001PYL for rev.B to SA00001PY1L for rev.C
change @R685 from 33 ohm to 0 ohm, R85 de-pop, @R330
from 0 ohm to 10K ohm
Un stuff R912.
R574 change from 1Mohm to 100Kohm.
Change ITP_TDO,ITP_TMS,ITP_TDI,ITP_TRST#,ITP_TCK of
R62,R64,R65,R66,R67 pull-up from 51 to 56ohm.
Correct C242 power rating from 16V to 25V.
Populate R276, No Pop R271
Chane the text in the table to show that it
R892 is connect to pin China TPM pin 28
Follow the new GPIO map to implement China TPM ID strap
Depop R466
Depop U37, C672, R589, R590, R591, R592, R593
Changed the value of R908 to 1 k ohm
SOT353 and SC70 footprint are the same package
X02
X03
X03
X03
X03
X03
Removed U58. Added R1008.
X03
No pop R740, R741, and R742
X03
Removed R85 and changed netname from PM_EXTTS#0/#1 to PM_EXTTS#
X03
Removed D4 and Added C1043, C1044, Q132, Q133, R995.
Use GPIOB4 on the 5028 for CCD_OFF .
X03
77
10,27
HW
09/11/2007
Compal
For vender request
78
79
7
38
HW
HW
09/13/2007
09/13/2007
Compal
Compal
For vender request
For vender request
80
7
HW
09/13/2007
Compal
For vender request
81
82
19
24
HW
ICH9M
09/13/2007
09/14/2007
Compal
Dell
Fix schematic Issue.
SCH162577: Populate pull-down on ICH_LAN_RST#
83
29
ICH9M
09/14/2007
Dell
SCH161941: USH and China TPM Pop Options
84
85
86
87
88
29
36
38
23
21, 38
ICH9M
USH
EC
ICH
ICH
Dell
Dell
Dell
Dell
Dell
89
24,29,37
09/14/2007
09/14/2007
09/19/2007
09/19/2007
09/19/2007
10/09/2007
Updated
SCH162277: GPIO for China TPM vs. USH TPM
Follow TPM Option Table on page 29.
SCH162762: No Stuff U37 - Flash ROM on the EC
SCH162766: Need to change the value of R908
SCH162800: Check U57 and U62 for packages
SCH162826: Connect the ICH9 GPIO12 to the
Intel LOM LAN_DISABLE_N
SCH162827: No pop the 0 Ohm resistors that
connect the USB and PCIE mini-card detects
SCH162822: Remove one of the two pull-ups on
PM_EXTTS#
C
ICH/LOM
Dell
90
34
MiniCard
09/19/2007
Dell
91
10
MCH
09/19/2007
Dell
92
19,37
93
21
LVDS/5028 09/27/2007
DP
09/27/2007
X02
X03
X03
X03
X03
X03
X03
C
Dell
SCH162824: Add load switch for the camera power
Dell
SCH162926: Need to add 100k pull down to DPC_CA_DE Added R996
X03
Compal
SCH163185: Add ESD discharge parts for the Dock
Power pins
Added D64, D65 (Nostuff)
X03
94
35
Docking
95
28
Amplifier 09/29/2007
Dell
SCH162939: C434 and C435 can be reduced to 0805
Changed C434, C435 size to 0805
X03
96
18
10/09/2007
Updated
Dell
SCH162823: Connect PWR_MON_GFX to VIN1 on
the EMC4002 - Depop the UL circuit
Added R997(@), R998 on page 18. PR170 stuff.
X03
97
37
SIO
10/01/2007
Dell
Change BID to X00 (011)
Changed R529 stuff. R534 nostuff.
X03
98
36
USH
10/02/2007
Dell
Changed R479 pull-up and R478 pull-down.
X03
Guardian
09/29/2007
D
B
B
SCH163294: USH strapping option
resitor missing in Roush
SCH163380: Populate the PCIE MCARD Detect 100k
pull-ups, and move R266 to page 34
99
24,34
Minicard
10/03/2007
Dell
100
37,42
LED
10/09/2007
Updated
Dell
SCH161770: LED Circuit Changes
SCH163409: Populate D64 and D65
(ESD Diodes on +DOCK_PWR_BAR)
Populate:R439, R449 (Change from 8.2k to 100k), R458.
Move R266 from page 24 to page 34
Added:R999~R1006. Q136, Q137. Q139~Q145, U65.
Removed: D44, D60, D62.
X03
X03
101
35
Docking
10/04/2007
Compal
D64, D65 changed to stuff.
X03
102
6
Clock
10/04/2007
Dell
SCH163426: Wrong series termination on CLK_NV_27M
R37 needs to change to 33 ohm
X03
Change R565 and R567 from +5V_ALW to +3.3V_ALW
X03
103
5,38
EC
10/05/2007
Dell
SCH163535: DOCK_SMB_CLK and DOCK_SMB_DAT
pulled up resistor to +3.3V_ALW
104
20
Video
10/05/2007
Compal
SCH163503: Nostuff ESD Diodes
Nostuff ESD Diodes D5, D6, D7
X03
SCH163465: Change Netname following 1003 GPIO Map
Rename GPIOB2 pin 82 from DELL_ESATA_PWR_EN# to
USB_CHARGER_PWR_EN# for clarification
X03
A
105
33, 37
EC
10/05/2007
Dell
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
60
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Rev.
52,53,54
GFX
10/05/2007
Dell
SCH163430: NVidia Feedback: Change FBCAL
resistors and CLK Shunt Resistor
R703, R706 set to 30.1 Ohm 1% . R750 set
107
24,37
ICH,SIO
10/09/2007
Dell
SCH163524: Need to change SNIFFER_DET# connection
Disconnect SNIFFER_DET# from ICH pin AE18 and connect it to
EC5028 pin 33. Rename, SNIFFER_DET# to PWR_BTN_BD_DET#
X03
108
36
USH
10/11/2007
Compal
L69 change to use 10uH with maximun 400mA rated current.
X03
109
33
USB
10/26/2007
Updated
Compal
110
38
EC
10/17/2007
Compal
111
50
GFX
10/25/2007
Dell
112
23, 29,
36, 38
C
113
A
Solution Description
106
D
B
Issue Description
ICH, LOM,
USH,EC
38
114
37
115
28
116
20,50,52
117
18,41
EC
SIO
10/30/2007
10/30/2007
Compal
Dell
SCH163437: Teridian Feedback: Make sure Inductor
has max rated current 400mA on pin 27
SCH163706: Charge USB Circuit Update
SCH163795: Follow M09 GPIO_100307 MAP to modify
scheamtic
SCH163765: Need to add two series zero ohm pop
options for CA_DET
SCH164316: Crystal CL Capacitor Changes
(Discrete Only)
SCH163795: Follow M09 GPIO_100307 MAP to modify
scheamtic
Dell
SCH164408: GPIO Map Update (1025)
Amplifier
11/01/2007
Dell
GFX
11/01/2007
Dell
SCH164416: Line out and Line In THD+N Failures
reqire cap changes
SCH164532: Remove options for TV on Discrete
Thremal
11/01/2007
Dell
50
GFX
11/05/2007
NV
119
33
USB
11/06/2007
Compal
120
23,50
ICH9M,GFX 11/06/2007
121
37
122
50
123
SIO
Dell
11/07/2007
Dell
GFX
11/07/2007
Dell
18
Thremal
11/07/2007
Dell
124
35
Docking
11/08/2007
Dell
125
42
LED
11/08/2007
Dell
X03
D
10/31/2007
118
to 475 Ohm 1% .
SCH162207: Issue to track the power rail for the
EMC4002
SCH163991: Reserve 10K pull-down on NV9M
I2CE SMbus from Nvidia FAE request
SCH164452: USB Switch Footprint Changed for
Multiple Sources Support
TASK162887: Add level shifter from 3.3V to 1.5V
for MCH HDA
SCH164730: MDC_RST Connection Changed per GPIO
Map (1105)
SCH164740: Roush/Heelys: discrete graphics 3
voltages setting
TASK162399: Need to contact SMSC about Guardian
errata
SCH164795: Docking Pin Out Change to Support
Battery Slice
SCH164770: Change CAP/NUM/SCRL LEDs to +5V_ALW
1. JESA1 pin1 change to +5V_ESATA and pin5 change to +5V_CHGUSB
2. JESA1 pin2,3 change to USBP3_D-,USBP3_D+ and pin6,7 change
to USBP2_D-_SW, USBP2_D+_SW
1.Add R85,C918 for RC_ID
2.Remove DEBUG_ENABLE# and connect HOST_DEBUG_RX from U36
pin71 to R577 pin2
3.Remove ADAPT_TRIP_SET on U35 pin70 and PR169 Pin1
X03
X03
Added R1009, R1010 nostuff.
X03
1. C297, C475, C476, C608 changed to 12pF
2. C609 changed to 15pF
3. C515 changed to 22pF
4. C514, C675 changed to 27pF
1. Changed MEC5035 pin30 to SUSPWROK ( Host RX is used) R553 del
2. Changed MEC5035 pin19 from SUSPWROK to RC_ID
3. RSVD Pin 70 GPIOC5 / ACK# ADAPT_TRIP_SEL
4. RSVD Pin 71 GPIOC6 / ERROR# ITP_DBRESET#(RSVD) / LCD_TST
1. Added MDC_RST_DIS# to GPIOE5/DTR# (Del R489, R830)
2. Changed pin 82 from USB_CHARGER_PWR_EN# to ESATA_USB_PWR_EN#
3. Change pin 104 from ESATA_USB_PWR_EN# to USB_POWERSHARE_PWR_EN#
Changes need to be made to the Line Out series
Capacitors C436 & C437 from 1uF 1206 to 2.2uF 1206
1. Removed R669, R762, R763.Make pins 7B1, 8B1, 9B1, 7B2, 8B2,
and 9B2 NC at U4
2. Disconneced DAC port B as NC at U44(Pin F7, E6, E7, F8, D6,
G6) Removed C869, C868, C867, L49, R679, C737,R688,R689,R690.
3. Pull down DACB_VDD (pin D7) thru 10K ohm. Added R1011.
Follow Maybach circuit.
Added R1012, R1013.
X03
C
X03
X03
X03
X03
B
X03
X03
Added C1045. Changed U54 footprint.
X03
Stuff R673, R674, R675, R6767, R678 and R243~R246. R673,R674,R676,
R678 cnahged value from 33 ohm to 0 ohm because R243~R246 stuff .
ECE5028
Moved MDC_RST from pin 84 GPIOE5/DTR# to Pin 102 GPIOA5
GPIO6 is connected to GPU_VID_0, and GPIO5 is connected to
GPU_VID_1.
Changed R142 from 22 to 0 Ohm.
X03
X03
Assign Pin 41 of the docking connector for NBDOCK_DC_IN_SS
X03
Change the 3x LED power rail to +5V_ALW instead of +5V_RUN
X03
X03
X03
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
61
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Issue Description
126
30
LAN
11/09/2007
Compal
127
12,13
GMCH
11/09/2007
Dell
128
129
130
18
38
6,36
4002
11/12/2007
EC
11/12/2007
CLOCK,USH 11/12/2007
Dell
Dell
Dell
SCH164877:
SCH164893:
SCH164896:
China TPM
50
GFX
11/12/2007
29,33,35 LOM,Docking 11/12/2007
Dell
Dell
SCH164899:
SCH164888:
Dell
SCH164892:
D
131
132
133
21
DP
11/12/2007
Solution Description
SCH164581: Remove termination resistor and
capacitor for LAN_TX[0..3]+/SCH164856: Remove options for TV form Cantiga
C
30
LAN SW
11/12/2007
Dell
SCH164889: Change L20-L27 from 36nH to 22nH
135
33
USB
11/12/2007
Compal
136
21
DP
11/13/2007
Compal
LAY164667: USB Switch Layout Changes following
Vendor's recommendation
TASK163764: Input derating data before PT gerber
137
38
EC
11/13/2007
Dell
SCH164928: Change Netnames Following Power
Circuit Changes
138
21,50
DP,GFX
11/13/2007
Dell
SCH164956: More DP clean up on discrete
B
139
37
SIO
11/13/2007
Dell
DF174483: [SSI2]The LCD/LED will keep had power
with USB device when unplug AC & Battery.
140
18
4002
11/14/2007
Dell
SCH162823: Connect PWR_MON_GFX to VIN1 on the
EMC4002 - Depop the UL circuit
141
142
37
39
SIO
1088
11/14/2007
11/14/2007
Dell
Dell
143
36
USH
SCH165017: Change PU to PD on SYS_LED_MASK#
SCH165024: Remove nostuff parts from Roush
schematic
SCH165076: Remove unnecessary Contactless
SmartCard components
11/15/2007
Dell
Removed MDI termination R384~R391,C488~C491
X03
D
1.VCCD_TVDAC --> connect to GND
2.VCCD_QDAC --> connect to 1.5V with filter
3.TV_DCONSEL_0, TV_DCONSEL_1 --> left as NC
EMC4002 POWER_SW# Input - Add AND Gate Added U68, R1014, R1015, C1050
Remove U37 (SPI ROM on EC)
Removed U37, R558, R589~R593, C672
PCI Clock BOM Options for ROW vs.
Change R29
from 22 Ohm to 33 Ohm 5@ (ROW TPM PCI Clock)
Change R854 from 22 Ohm to 33 Ohm 4@ (China TPM PCI Clock)
Add R1016 (100k) pull-down 4@ on U32 pin M7
Roush Discrete Pop Options
Populate R825. No Pop R719
Add Intel LOM LDO for 2.65V/2.5V
1. Add Q50, Q146, R1017~R1020
2. Remove R377, R380, Q46
Discrete Graphics changes for DP
1. No pop 100Kohm pull ups R180
2. Add 100Kohm PD on DPB_AUX_SW and DPB_AUX#SW.R1022, R1023(@).
3. Add 100kohm PD on DPB_MB_AUX and DPB_MB_AUX#.R1024(@),R1025(@).
4. Remove Q10, R798. Connect U9 pin 37 directly to U44 pin G1
5. Change R720 and R721 (DPRSet) to 800Ohms
6. No pop 100Kohm pull ups R182
7. Add 100Kohm PD on the DPC_AUX_SW and DPC_AUX#SW. R1026,R1027(@).
8. Remove Q114 ,R795. Connect JDOCK1 pin 40 directly to U44 pin F3.
134
A
Rev.
Change MDI bus value at L20~ L27 from 36nH to 22nH.
These changes will help improving the IEEE Return Loss margins
Change Common mode choke connection to between switch and
connector.
1. Applying voltage on ceramic capacitors: C921~C929, C1044
2. Applying current on inductor: L65, L67, L76
3. Applying current on diode: D10
From "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
From "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#"
From "ACAV_IN_MB/DOCK" to"ACAV_IN"
Remove U59, C1012. Add U69, C1051.
1. De-pop R181, De-pop R183
2. Populate R1024 (pull-down on DPB_MB_AUX)
3. Populate R278 (pull-up on DPB_MB_AUX#)
4. Add pull-down pads for DPB_DOCK_AUX and DPB_DOCK_AUX#
5. De-pop R1026
6. Change R193 to 3.48 kohm
7. Change DPB_HPD# to DPB_HPD and DPC_DOCK_HPD# to DPC_DOCK_HPD
1) Add 100k no pop pull-ups to +3.3V_ALW2 on:
- USB_SIDE_EN#
- ESATA_USB_PWR_EN#
- USB_POWERSHARE_PWR_EN#
2) No stuff R502, R923, R929.
- Connect PWR_MON_GFX to VIN1 on the EMC4002
- Add a pull-down resistor on the pin on the guardian
- Remove PWR_MON_GFX from VCP2
change R658 from a no stuff pull-up to a populated pull-down
Remove U38 (ECE1088), C677, C676, R747, R650, R826, R557
X03
X03
X03
X03
X03
X03
X03
C
X03
X03
X03
X03
X03
B
X03
X03
X03
X03
A
R495, R799, C777, R499, and C783 can be replaced with a
short, and R800 can be replaced with an open
X03
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
62
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
144
Title
50
GFX
Date
Request
Owner
11/15/2007
Dell
DP
USH,BIO,
ICH
11/15/2007
11/15/2007
Dell
Dell
D
145
146
147
37
SIO
11/15/2007
Dell
148
27,38
CODEC,EC
11/15/2007
Dell
CODEC,USH
NB,SB,USH,
CODEC,LOM
SIO
Mini-Card
SPI
DP
11/19/2007
11/21/2007
Compal
Compal
11/20/2007
11/20/2007
11/22/2007
11/22/2007
Dell
Dell
Dell
Dell
149
150
C
B
A
21
24,33,36
151
152
153
154
27,36
10,22,27,
29,36,50
37
34
24
21,50
155
35
Docking
11/26/2007
Compal
156
157
24
34
SPI
Mini-Card
11/28/2007
11/28/2007
Dell
Compal
158
38
EC
11/29/2007
Compal
159
30
11/29/2007
DELL
160
161
13
7
MCH
CPU
11/29/2007
11/30/2007
Compal
Compal
162
21
DP
11/30/2007
Compal
163
36
USH
12/3/2007
Broadcom
158
28
Amplifier
12/5/2007
159
37,42
Wireless
12/5/2007
LAN Switch
Issue Description
Solution Description
SCH165071: Need to depop R832 and R797 to pass
HDMI spec
SCH165069: Depop R1022 for discrete
SCH165067: FP_RESET# signal from USH to
Fingerprint reader
SCH165765: Audio Feedback: Change 2 resistor
values, Add two resistors on IO board
DELL
SCH165763: Change Wireless net name (on is
toward the user)
Broadcom SCH165731: Follow Broadcom request to modify
Maybach schematic for USH
36
USH
12/5/2007
161
162
166
167
18
42
37
29
EMC4002
LED
ECE5028
LAN
12/7/2007
12/7/2007
12/8/2007
12/8/2007
SMSC
Compal
Compal
Intel
168
29
LAN
12/8/2007
Compal
Depop R832, R797.
X03
D
Depop R1022
X03
1) Connect USH SMC_ADD_23 (Pin C3) to Fingerprint reader connector X03
JBIO1 pin5 with a 4.7K pull-up to +3.3V_RUN. R1034 added.
2) Remove BIO_DET# conncetion to the ICH9M pin A8
SCH165068: Add FET buffer on signal INSTANT_ON_SW# Add D66, R1035, R1036
X03
to 5028 pin 28
DF179111: SMBus EA some item measure fail
1.LCD_SMBCLK/LCD_SMBDAT change PU resistor of R548,R549 to 2.2K
X03
2.DAI_SMBCLK/DAI_SMBDAT stuff R334,R335 to 2.2K
3.DOCK_SMB_CLK/DOCK_SMB_DAT change PU to +3.3V_ALW (R565, R567)
Some Crystal is not PSL parts.
Y3, Y5 change to use KDS's crystal replace non-PSL part.
X03
Change U2,U10,U16,U23,U32,U44 P/N
X03
Change chips new revision P/N for PT1
Nostuff R717. Change R725 to 34.8K.
Chnage VRAM Strapping setteing for Qimonda
Change BID to X04 (100)
Change R531, R534, R535 stuff. R529, R530, R536 nostuff.
X04
SIM card Footprint change per ME request
JSIM1 footprint change
X04
X04
Unstuff 2nd SPI ROM for ICH
Depop U13,R304,R305,R306,R308,R309,R295,C329
SCH165325: For PT1 SMT: Build PT1 Discrete with
1.Pop R336,R337,R1028,R1029,R182,R183,R1026,R1027
X04
R720 and R721 = 1k Ohm
2.Change R720,R721 to 1K
SCH165517: DP stuffing options for Roush PT1
SCH165307: Docking Conn ESD Concern - Dock
Remove D65 & change D64 fooptint from SOD323-2 to SOT23-3
X04
Power pins
SCH165504: Remove 2nd SPI ROM for ICH
Remove U13,R304,R305,R306,R307,R308,R309,R295,C329
X04
SCH165319: PCIE_MCARD1_DET# pull-up to wrong
No-stuff R439 and add 100K of R443 to pull-up +3.3V_ALW_ICH
X04
power rail
SCH165505: X04: Add pop options to change
Add 0ohm of R445,100K of R589. No-stuff R560,C1011,U57,D66, Pop
X04
INSTANT_ON_SW# from RTC to +3.3V_ALW Rail
R1036
LAY165172: LOM Feedback for X04 - Improve routing Swap LAN_TX[0..3]+/LAN_TX[0..3]-,SW_LAN_TX[0..3]+
X04
on the MDI signals
/SW_LAN_TX[0..3]-,DOCK_LOM_TRD[0..3]+/DOCK_LOM_TRD[0..3]SCH165564: Remove D1,R122 from Intel request
No-stuff D1,R122 from Intel request
X04
SCH165378: No-stuff H_RESET# pull-up resistor
No-stuff R63
X04
of R63
D10 PCB Footprint can't stuff 0805 or 1210 resistor
SCH165621: X04: Populate D10 with a 0 Ohm resistor
X04
directly, so add 1210 0ohm of R210 and no-stuff D10.
SCH165660: SC_DET issue from Broadcom highlight
Add R914 pull-down contact to SC_DET on JSC1 pin2 and no-stuff
X04
DELL
160
Rev.
SCH165882: Disable EMC4002 LDO
SCH165913: +5V_RUN backdrive issue on S3 mode
INSTANT_ON_SW double pull-up
Intel request if didn't use ICH GPIO12 to
control LAN_DISABLE need connected to 3.3V
SCH165838: De-pop R1008 for control LAN PHY
enable form BIOS setting
Change R818,R827 to 1K_0402_1%
X04
Change net name from WIRELESS_ON/OFF# to WIRELESS_ON#/OFF
X04
1.Depop R490,C591
2.Pop R829 and depop R467
3.Depop R849
4.Change R476 to 5.1M ohm and R488 to 3.3M ohm
5.No-stuff C594
6.Change R473,R771 to 1K
7.Change C621,C706,C646 to X5R
Add R211 and no-stuff R149
Add D67 between Q97 and Q98
No-stuff R1035
Add pull-up resistor of R295 to +3.3V_ALW_ICH and no-stuff
X04
De-pop R1008
X04
C
B
X04
X04
X04
X04
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
63
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Solution Description
169
27
Auido Codec
12/10/2007
IDT
170
31
Cardbus
12/10/2007
Ricoh
TTL
12/13/2007
Compal
SCH166138: About 74AHCT1G08GW AND Gate issue
5035
Docking
LED
USB,5035
12/14/2007
12/14/2007
12/17/2007
12/18/2007
Updated
12/17/2007
Dell
Dell
Dell
Dell
TASK166116: Updated GPIO Map
SCH166112: Add a pull-up on DOCK_DET# to +3.3V_ALW
SCH166225: Add mask signal on NUM/SCRL/CAPS LEDs
SCH166229: Update Cell charger detect circuit
Dell
SCH165838: De-pop R1008 for control LAN
PHY enable form BIOS setting
SCH166180: Intel NOA test point compliance
D
171
172
173
174
175
176
C
Issue Description
18,21,
37,38,42
38
35
42
33, 38
29
PHY
177 6,8,10,24 CLOCK,CPU,
MCH, ICH
33
USB
178
12/17/2007
Dell
12/17/2007
Dell
179
180
ICH,GPU
RICOH
12/18/2007
12/18/2007
Dell
Dell
5035,
Docking
4002,eSATA
12/18/2007
Dell
12/19/2007
Updated
Dell
23,50
31
181
35,38
182
18,33
SCH165972: Follow IDT request to change C408~C411
to 2.2uF
SCH165973: Follow Ricoh request to modify schematic
SCH166140: Add SATA repeater for ICH to ESATA
trace over 5inch issue
SCH166293: Roush X04 Discrete: Remove HDA resistors
SCH165973: Follow Ricoh request to modify schematic
SCH166292: Add Dock changes for GPIO50 pin 41 of
the 5035
TASK166288: ESATA Redriver Questions
B
A
183
184
50
36
GPU
USH
12/19/2007
12/19/2007
Dell
Dell
185
186
187
36
42
36
USH
LED
USH
12/19/2007
12/20/2007
12/20/2007
Dell
Compal
Compal
188
189
190
35
13
51
Docking
MCH
GPU
12/20/2007
12/21/2007
12/27/2007
Dell
Compal
NVIDIA
191
192
193
37
33
36
SIO
ESATA
Broadcom
12/27/2007
12/27/2007
12/27/2007
DELL
DELL
DELL
Rev.
Change C408~C411 to 2.2U_10V_0805 X5R
X04
Add C622,C1012,C1016,C1036,C1037,R1037,R799,R800
No-stuff R684,R790,R657
Change U68, U62, U69, U57, and U65 from 74AHCT1G08GW to
74AHC1G08GW
The signal ACAV_DOCK_SRC# can be removed from the 5035
Add R1038. R124 nostuff.
Add Q150. R1039 nostuff.
Add D68, D69, R1040. Del R927. C1042 change value to 1uF.
X04
X04
X04
X04
X04
Pop R1008 because new BIOS fixed this softstrap issue
X04
Add R1041~R1045.
X04
Add U72, C488~C490, C1052, R305~R307.
X04
Del R673~R676, R678, R243~R246, C309. U10.AH3 as NC.
1.Connect totally 10uF bulk capacitor(s) to 1.5VOUT pins.
2. Connect totally 10uF bulk capacitor(s) to AUXOUT pins.
3. Remove pull-up resistor from CPPE# signal.
4. Remove pull-up resistor from CPUSB# signal.
5. SHDN#, apply NC/open
6. Remove pull-up resistor from SHDN#
7. Apply pull-down resistor to SPKROUT pin.
8. Add capacitors for CCD[2:1]#
9. Connect CADR22 to CPUSB# pin of ExpressCard Connector
10. Connect CDATA2 to PERST# pin of ExpressCard Connector
11. Add capacitor for FIL0, 0.01uF
X04
X04
Add R1046, C1053. 5035 GPIO50 connected to Docking pin 140.
X04
1. Using the Guardian LDO set to +1.8V for the VDD
2. Changed power rail to +1.8V_RUN
3. Connected the enable to a pull-up to the same rail as VDD
4. Use PI2EQX3201B.
5. No any 2nd source for this part
Populate R1009 and R1011
Add R1048
X04
D
X04
C
B
SCH166329: NVidia feedback to pop R1009 and R1010
SCH166328: Add a series resistor on PLTRST3# for
the USH RESET_N
SCH166327:Add a no stuff diode in parallel w/ R464 Add D70
SCH166355: Add Bypass Capacitor for TTL gate
Add C1058~C1061
SCH166388:Change USH Circuit per Broadcom Feedback 1.Change R476 to 5.1M ohms and R488 to 3.3M ohms to lower
2.Pop D70, C641, C647,C1020,C1021,R474,R829. Depop R464,R466,R467
SCH166399:Roush + Docking AC protect issue(crowbar) Add D71, R1068.
Debug +3.3V_RUN backdrive issue on S3 mode
Add R1076
SCH166484: Follow NV feedback to update DIS
No stuff R699,R700,C775/ Stuff R852. Change C855 to 470P.C857
schmatic
to 4.7u. Add C309,C329,R1079,R1080
For Power change Media Slice issue
Add D65,R1078 and reserve R1081
SCH166445: ESATA feedback on 3201 pin 11 and pin 12 Reserve R1056,R1057,R1066,R1067,R1069,R1070
SCH166428: Add a No Stuff series resistor between
Reserve R1071
PLTRST3# and RST_N
X04
X04
X04
X04
X04
X04
X04
X05
X05
X05
X05
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
64
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
194
All
All
01/23/2008
Compal
Update changes following PT2 MEMO
Update changes following PT2 latest MEMO Rev.0.6
X05
195
196
197
198
37
7
36
33
SIO
CPU
USH
USB
01/23/2008
01/23/2008
01/23/2008
01/23/2008
Dell
Dell
Dell
Dell
No Stuff R1081
R67->27 ohm,R64->39 ohm,R66->649 ohm,R65->150 ohm, R57->124 ohm
Change R468 and R469 to 0 Ohms
Add R1082, R1083
X05
X05
X05
X05
199
200
42
36
LED
USH
01/28/2008
01/28/2008
Compal
Dell
SCH166607: UMA X04 - No Stuff R1081
SCH166740: X05 - Change ITP resistor values
SCH166962: Roush X05 - EA issue with USB to 5880
SCH167262: X05 - Add 0 Ohm bypass resistors
on U54 for USB port 2
DF192207: Power LED current over spec
SCH167383: ROW TPM Disable Pop Options
X05
X05
201
18
EMC4002
01/29/2008
Dell
202
6
Clock
Dell
Change L1 to BK2125HS601-T
X05
203
204
205
206
207
208
209
210
36
35
21
33
10
27
21
21
USH
Docking
DP
eSATA
MCH
CODEC
DP
DP
02/12/2008
Update
01/30/2008
01/31/2008
02/12/2008
02/12/2008
02/12/2008
02/13/2008
02/19/2008
02/19/2008
SCH167478: Change R152 from 0 Ohm to 0.82 Ohm for
EMC4002 LDO Input
SCH167489: L1 Part Derating Problem
Change R1001 to 82 ohm
Make D70, and R841 = 5@ (pop for USH TPM)
Make R483 = 4@ (for China config)
Change R152 from 0 Ohm to 0.82 Ohm
Compal
Compal
Dell
Dell
Dell
Compal
Dell
Dell
SCH167486:
SCH167590:
SCH167949:
SCH167851:
SCH167660:
SCH168055:
SCH168269:
SCH168268:
211
27,28
CODEC
02/19/2008
Dell
212
213
214
07
36
27
ITP
USH
CODEC
02/19/2008
02/21/2008
02/26/2008
Update
Dell
Dell
Dell
215
216
39
27
TP
Audio
02/27/2008
02/27/2008
Dell
ADI
217
34
SIM
02/27/2008
Compal
D
C
B
D
218 18,37,38
219
220
37
20
4002,5028,
5035
5028
CRT
221
222
223
224
225
21
35
34
33
55
DP
Docking
Mini-Card
USB
GFX
226
21
03/04/2008
SMSC
03/04/2008
03/04/2008
COmpal
Compal
03/04/2008
03/07/2008
03/07/2008
03/07/2008
03/07/2008
Dell
Dell
Dell
Dell
Dell
03/10/2008
Dell
A
DP
X05
Smartcard Circuit Update
Docking Detection Circuit Update
Add pass gate FETs to Roush Discrete
X05 - Pop R1058 for ESATA EA
BOM option for Intel debug
PC BEEP Circuit Update
Correction to meet DP spec
More DP changes for discrete
R849 must be pop-ed to support USH low power
No stuff R1068.
Add U73, U74, C1064, C1065, R1084~R1087, Q151, Q152
Stuff R1058
Add R1088 (no stuff)
Nostuff R328. Change R327 and R828 to 499K
Change R996 to 1 M ohm
Change R1084, R1085, R1086, R1087 to 10k.
Change R336, R337, R1028, R1029, R1026, R1027 to no pop.
Change R193 to 5.11k
SCH168158: SSM2602 Circuit Update
Add R1089, R1090 resistors around C410 and C411.
Change C406 to 10uF cap to pin 20 of U15 2602
Change C436 and C437 from 2.2uF 1206 to 10uF 1206 (DF194434)
SCH168093: Populate JITP1 and Supporting Components Populate JITP1
Broadcom feedback: Pi filter
Add L71, L72, C1070, C1071
SCH168407: SSM2602 Circuit Review Feedback
Remove:C395
Add:L70, L71, C1066, C1067, C1068, C1069, R1091, R1092.
Value change:C391,C406,C397,C401,C408,C409,C410,C411,R340,R342.
Connection change:R1089, R1090, C396, C397, C398, R346, R347.
SCH168492: Touchpad Changes to fix backdrive
Add R1093, R1094. No stuff R594, R595.
SCH168407: SSM2602 Circuit Review Feedback
Add:L70, C1066, C1067, C1068, C1069
Value change:C391,C406,C397,C401,C408,C409,C410,C411,R340,R342.
Connection change:R1089, R1090, C396, C397, C398
SCH168596: Change SIM Card Connector Back
Changed JSIM1 to push-push type
to Push-Push Button Type
SCH168546: SMSC ST Feedback for 4002/5028/5035
R153 change to 3.16K.
Add C1072. No stuff R900.
BID Chnage
Stuff R529. No stuff R534.
SCH167856: X05 - RGB Filter Change
R1095~R1097(0 ohm) replace L8,L9,L10.
No stuff C255,C256 C257,C390,C518,C996.
SCH168809: Add pull down to prevent floating input Add R1098. No stuff R185, R187
D26 pin 4 and 7 should be connected to DPC_DOCK_HPD
LAY169084: Fix D26 routing for discrete
SCH169083: Pop R840 for WIMAX LED support post RTS Populate R840.
SCH169019: Pop R1082 & R1083 to bypass USB buffer Populate R1082 & R1083. No stuff U54.
SCH169006: NVidia Feedback for X05 Discrete
Change R776 from 243 Ohm to 475 Ohm
SPDIF: Make R856 and R857 no stuff
SCH168766: Add 1k ohm pop option for nVidia
Add R1099, R1100, R1101, R1102
silicon concern
X05
X05
X05
X05
X05
X05
X05
X05
C
X05
X05
X05
X05
X05
X05
B
X05
X05
X05
X05
X05
X05
X05
X05
X05
A
X05
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
65
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
227
228
36
20
USH
CRT
03/10/2008
03/10/2008
Dell
Compal
229
21
DP
03/10/2008
Dell
03/10/2008
03/11/2008
03/11/2008
Dell
Dell
Compal
03/11/2008
03/12/2008
Compal
Compal
230
231
232
233
234
7
ITP
50
GPU
6,23,24, RC
27,29,37, Termination
38
34,42
MiniCard
23
Crystal
Solution Description
Change R849=1.5k, and R913=300 Ohm
1. Removed C390, C518, C996, C255, C256, C257, C267 and C268.
2. Short L8, L9 and L10 (Replaced by R1095~R1097).
SCH168711:Modify circuit to comply to DP 1.1a spec 1. Depop R336, R337, R1028, R1029, R182, R183, R1026, R1027.
2. Add SN74CBTD3306CPWR switches (U75~U78) to DDC lines.
3. Change R996 to 1 M ohm
4. Add a 1 M (R1098) pull down on U9 pin 39. Depop R185 and R187.
5. Change R193 to 5.11k.
6. Replace F1 with GEC 1206L150-C PTC.
7. Add a 10 uF cap (C1075) from +VDISPLAY_VCC to ground
SCH168709: Issue to track ITP
Add R1103~R1113
SCH169189: Add pads for a .1uF cap on HPD signals Add C1076, C1077 and no-stuff
SCH169206: WWAN Noise Solution
- Add R527, R744, R588, R285, C656, C673, C318, C302, C300
- Value Change R786, R379, R26, R29, R32, R19
235
26,32
ME
03/12/2008
236
31
SD card
03/12/2008
237
36
RFID
03/12/2008
238
36
DAI
03/13/2008
239
35
Docking
03/13/2008
Compal
240
241
27
24,37
Auido
SPI ROM
03/13/2008
03/14/2008
Compal
DELL
242
243
244
245
36
31
21
6
SPI ROM
CARDBUS
DP
Clock
03/14/2008
03/17/2008
03/17/2008
03/18/2008
Compal
Compal
Compal
Dell
246
27
DAI
04/01/2008
Compal
247
248
36
37
RFID
SIO
04/01/2008
04/03/2008
Compal
DELL
249
35
Docking
04/03/2008
DELL
250
36
USH
04/23/2008
Compal
A
Rev.
SCH169129: Smart Card Insertion
SCH167856: X05 - RGB Filter Change
SCH169218: Remove Screw Hole and MiniCard Latchs
ME add new z-high limit cause 32.768Khz material
interfere.
Compal
ME update ODD,PCMCIA connector footprint
Remove Hole & Mini card latch from ME request
Ricoh
SCH169273: Resolve SD_CLK under shoot issue
below from Ricoh request
Broadcom SCH169256: Need to make changes to RFID schematic
connections
ADI
Follow DELL request to modify
C
B
Issue Description
DF193241: Enhance ESD: Air discharge to
jack screw cause system hang-up
EMI team find had noise at 2MHz
SCH169380: GPIO for Write Protect (WP#) for
SPI Flash
U34 component z-high interfere ME define
SCH169447: 24.576MHz (X3) Crystal Circuit Update
SCH169464: DVI Pull Ups Changes per NV suggestion
CLK_PCI_DOCK is shared with CLK_PCI_PCM. It
does not follow the Roush PIG, and causes risk
for docking scenarios. (Roush gating list)
SCH169971: Add 0ohm between double inverter for
DAI function
Change ESD Diode package
SCH170088: ICH LOM errata update
SCH170091: Add series 0603 zero ohm on
DPB_DOCK_HPD and DPC_DOCK_HPD_R.
Add 3.3V_RUN discharge circuit for backdrive
X05
X05
D
X05
X05
X05
X05
Remove H8, JLAT2, JLAT3
Change Y1 Footprint from Y_1TJS125DJ4A420P_4P to Y_1TJE125DP1_2P
X05
X05
Change JSATA1 Footprint to TYCO_2-1759838-8_13P_RV-T, JCBUS1
to MOLEX_48315-0012_68P_RT-T.Delete H8,JLAT2,JLAT3
Add C491 close to JSD1 pin8
X05
X05
Follow Broadcom comment to modify circuit
X05
1. U15 pin12 to GND and remove C396
2. Change C1066, C1067, C1068 and C1069 to 1nF
3. Change C408 and C409 to 1uf.
4. Change C410 and C411 to 0.22uF
5. Change R340 and R342, R1091 and R1092 to 200 Ohm
6. Change R1089 and R1090 to 10M.
Add C672 close to JDOCK1 pin39, stuff C1076
X05
C
X05
Reserve C676 on DMIC_CLK signal
1.Add 2nd SPI ROM schematic
2.Add serial resistor and contact SPI_WP#_SEL signal from
U35.23 to U12.3,U13.3
Change package from SO8 to VFQFPN8
Add R1117 no stuff
R1084~R1087 change value from 10K to 2.2K
CLK_PCI_PCM change net from pin32 to pin33 of U1
X05
X05
X05
X05
Add R762
X06
Change from BAS40-04_SOT23-3 to DA204U_SOT323-3
1.PBAT_PRES# contact to U35 pin 97
2.LAN_DISABLE#_R contact to U35 pin88.
3.Add D38,C677 and no-stuff.R1008 change to 4.3K and no-stuff.
Add R387
X06
X06
Stuff R625, Q79.
X07
X05
B
X05
X06
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
66
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
C
Title
Date
Request
Owner
Issue Description
Solution Description
251
252
37
24
SIO
ICH
04/23/2008
04/23/2008
Compal
Dell
BID change to X07
SCH170773: No Stuff 2nd SPI ROM (U13)
253
254
36
40
05/02/2008
05/02/2008
Dell
Dell
255
256
35
33
USH
Power
Control
Docking
TP
05/12/2008
05/15/2008
Compal
Compal
257
27
AUDIO
Compal
258
259
260
261
32
40
6
36
Express
Power
Clock
USH
Compal
Compal
Dell
Compal
262
263
264
265
266
267
24
42
38
37
27
27
ICH
LED
EC
SIO
AUDIO
Nvidia
05/23/2008
Update
05/15/2008
05/23/2008
05/29/2008
06/04/2008
Update
06/02/2008
06/02/2008
06/03/2008
06/03/2008
06/03/2008
06/09/2008
SCH170926: Broadcom Feedback
SCH170717: Power Sequence Check with Discharge
Circuit
DOCK_DET# need not have pull down
DF216972: Contact +/-6kv to FP cause system
lock-up
SCH171755/DF216224: DMIC EMI failed
Compal
Compal
Dell
Dell
Compal
Nvidia
Rev.
Depop R535, Populate R530
Depop U13, R304, R380, C395, R308, R309, R384, R1060,
Populate R298
Populate R705, R723, R724, R732, R733
Change R625 from 10 ohm to 39 ohm
X07
X07
X07
X07
Depop R1068
Pop U51
X07
X07
Remove R338. Add L78. Pop C676.
X07
DF216223: EMI radiation failed for express card
SCH171795: Power Step on +3.3V_ALW_ICH rail
SCH172103: No Stuff ITP clock resistors for X07
SCH172075: RFID Implementation
Depop R791, R792. Pop L64.
C688 change value to 3300pF
No stuff R18, R21.
C639 and C643 have to use X5R. L71, L72 change to 2%.
X07
X07
X07
X07
SCH170341: Sawtooth waveform on SERIRQ Issue
SCH172191: Breath Power LED Resistor Change
SCH172185: Connect ODD_DET# to GPIO41 5035.34
SCH170391 (SLICE_BAT_PRES#)
TASK169849: Regress Audio HP and Microphone test
Add pull-down resistor on HDA_RST#(U44.C6) &
GPIO3(U44.M2)
Add R1126
Change value from 82 to 100 ohm (R1001)
Connect ODD_DET# to GPIO41 5035.34, ICH9.AE19, JSATA1.8
R504 change to 4.7K. Add PC266 (1500pF)
L70 change value to 47UH_LBMF1608T470M_20%
Add pull-down resistor on HDA_RST#(U44.C6) &
GPIO3(U44.M2)
X07
X07
X07
X07
X07
X07
D
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
67
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
1
48
Title
Date
Request
Owner
Charger
08/31
Saha
ACAV_IN_NB will pull high
when DOCK adapter insert.
Change PR145, PIN2 connection from +SDC_IN to +DC_IN
X02
Issue Description
Solution Description
2
48/49
Charger
Selector
08/31
Saha
ACAV_IN_DOCK# won't pull high
when battery only mode.
Change ACAV_IN_DOCK# pull high to +3.3V_ALW2
Add inverter for ACAV_IN_DOCK
PQ27 enable change to ACAV_IN_DOCK
Confirm HW delete U58 and R124 pull up to +RTC_CELL
X02
3
48
Charger
09/28
DELL
Doug
EE work item
SCH162823
Connect ISL88731_ICM to VCP2 with a series resistor
Depop the UL circuit (bottom of page 48)
X03
4
43
Charger
09/28
Saha
DFX team suggest change
GND to PIN1 and PIN2
PJPDC1 PIN1/PIN2 is -DCIN_JACK, PIN3 is DCIN_CBL_DET#
PIN4 NB_PSID, PIN5/PIN6 is +DCIN_JACK
X03
5
PWR
Snubber
10/22
DELL request add a snubber circuit
on every regulator
Add below location of regulator switching node
+3.3V_ALW: PR276, PR251
+5V_ALW: PR277, PC245
+1.5V_RUN:PR278, PC246
+1.05V_M:PR279, PC246
+1.8V_SUS:PR280, PC249
+VCHGR:PR281, PC249
VGA_CORE:PR282, PC250
X03
Guangyong
DELL
C
43
+DC_IN
10/22
Guangyong
DELL
Add a resistor around AC power
soft-start fet
Add PR251 0_0402_5% before NB_AC_OFF for delay switch
X03
7
43
+DC_IN
11/2
Compal
DCIN_CBL_DET# damage ECE5028
Add ESD diedo PD13 DA204U_SOT323 at DCIN_CBL_DET#
Series PR67 1K_0402_5% between PJPDC1, PIN1 and DCIN_CBL_DET#
Parallel 0.47uF_0402_6.3V on DCIN_CBL_DET#
X03
8
48
Charger
11/2
Compal
NB DC blocking MOSFET won't turn off
when Dock AC insert.
Add PQ44 RHU002N06 control NB DC blocking MOSFET.
Control singal is NB_AC_OFF
Series PR284 200K_0402_1% between PQ44, PIN1 and NB_AC_OFF
Add PD30 B540C parallel PQ34
X03
9
49
Selector
11/2
Compal
PBATT DC blocking MOSFET won't turn off
when Docking AC insert.
It will cause Battery or adapter protect.
Add PD18 RB715F_SOT323, PD20 and PD19 RB751V_SOD323, PR329 100K_0402_5%
PR328 and PR327 47K_0402_5%, PR326 and PR325 240K_0402_5%
PQ40 2N7002DW-7-F_SOT363-6, PQ59 NTG6161PT1G_TSOP6
Extra net name add +NBDOCK_DC_IN_SS from Docking connector
X03
10
43
+DC_IN
11/2
Merle
DELL
Roush component and rework changes
for Dcoking test
PC5 change form 0.47uF_0805_25V to 0.1uF_0805_25V
PR16 change form 240K_0402_5% to 1M_0402_5%
PR21 change form 47K_0402_1% to 220K_0402_5%
PR22 change form 47K_0402_1% to 22K_0402_5%
PR283 change form 0_0402_1% to 100K_0402_5%
X03
11
62
MAX8632_VGA
11/7
nVidia
NB9x's GPU CORE Voltage
Change PR203 to 90.9K_0402_1%, PR205 to 93.1K_0402_1%, PR209 to 68.1K
Add PR288 221k_0402_1% , PC253 100P_0402_50V, PR289 63.4K_0402_1%
PQ60 BSS138W, PC252 0.01u_0402_16V
PR287 100K_0402_5%, PR286 and PR285 10K
X03
12
43
11/8
Compal
Battery slice need detect
NB battery is insert or not.
Add PQ61 NTR4502PT1G, and PD32 RB751_SOD323
Connect to DOCK_SMB_ALERT# and SLICE_BAT_PRES#
X03
+DC_IN
D
C
6
B
A
Rev.
B
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Changed-List History 1
Size
Document Number
Custom
2
Rev
0.8
LA-3803P
Date:
Thursday, June 12, 2008
Sheet
1
68
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
D
C
D
13
49
Selector
11/8
Compal
NB_AC_OFF_BJT can't turn off
when Dock adapter exist
Change PQ39 to PQ61A/B (2N7002DW-7-F),
NB_AC_OFF_BJT control by NB_AC_OFF
X03
14
48
Charger
11/8
Compal
Charger of ISL88731 will turn off
When ACIN is no power
Add LM393 to replace ISL88731 ACOK function(PU11B)
X03
15
48
Charger
11/09
Merle
Dell
+PWR_SRC exist on Docking connector
through the DOCK_DCIN_IS+ and -
Add PQ62 NTGD4161PT1G series DOCK_DCIN_IS+ and Add PQ63 RHU002N06 to control PQ62 on/off
X03
16
43
+DC_IN
11/09
Kyle
DELL
No pop PD13, PR67 and PC254.
Reduce mass build risk
No pop PD13, PR67 and PC254.
X03
17
48
49
Charger
Selector
11/12
Merle
DELL
A global signal name change
for all notebooks
From "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"
From "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#"
X03
18
48
Charger
11/12
Merle
DELL
Add pull up resistor at PU11.7.to +3.3V_ALW Remove PR337, Change PR145 from +DC_IN to +SDC_IN.
Change signal name at Node PR157.1
Pop PR145 and PR156, change PR157 net name from ACAV_IN_NB to ACAV_IN.
from "ACAV_IN_NB" to "ACAV_IN"
Add PR341 100K_0402 pull up +3.3V_ALW at PU11B output.
Show PR156 as a stuff.
X03
19
43
+DC_IN
11/22
Merle
DELL
NB and Dock adapter swap issue
PR21 change to 1M_0402_5%
PC5 change to 0.022uF_0805_50V
X03
20
56
VGA_PM
11/22
Compal
DELL
GFX_CORE support 0.9V/1.09V/1.17V
PC197, PC253
PR201 change
PR205 change
PR288 change
X03
21
48
Charger
11/30
Greg
DELL
Comparator Circuit for E-Dock
PC256 change from 100pF to 0.1uF
X04
22
49
Selector
11/30
Merle
DELL
PBATT back drive to Battery Slice
vias charger high side MOSFET
Add PQ65 between PBATT+ and +VCHGR
Use PBATT_OFF control PQ64 to switch PQ65
X04
B
change to 330pF_0402
to 26.1K_0402_1% PR289 change to 68.1K_0402_1%
to 49.9K_0402_1% PR209 change to 46.4K_0402_1%
to 162K_0402_1%
C
B
20
56
VGA_PM
11/30
Guangyong
DELL
GFX_CORE support 0.9V/1.09V/1.17V
Un-pop PC190
X04
21
57
VGA_PM
11/31
Guangyong
DELL
To fix dynamic MAX8632 PGOOD drop issue.
Reserve PC257 between MAX8632 FB to GND
X04
22
43
+DC_IN
12/05
Greg
DELL
PJPDC1 change to 7pin connector
PJPDC1 change to MOLEX_87437-0763_7P-T
Change PC67 to 0_0402_5% and populate
X04
+DC_IN
12/07
AJ
Compal
P-MOS Vgs too high
PQ61 change to FDN338P_NL
X04
Charger
12/10
Guangyong
DELL
Modify Charger schematic
Follow Intersil suggestion
Add PD33 BAT54CW_SOT323, +DOCK_PWR_BAR/+DC_IN_SS
Reserve PR356 0_0402_5% form +SDC_IN to PU10 PIN22
Add PR354 10_0402_1% to CSSP, PR355 10_0402_1% to CSON
Add PC260 0.1U_0603_25V to CSSN, PC261 0.1U_0603_25V to CSOP
PC143 and PC166 change to 0.1U_0402_10V
PR161 change to 100_040_5%
23
25
43
48
A
X04
A
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Changed-List History 2
Size
Document Number
Custom
2
Rev
0.8
LA-3803P
Date:
Thursday, June 12, 2008
Sheet
1
69
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
26
50
Selector
12/10
AJ
Compal
PBATT_OFF connect to DOCK_AC_OFF
Add PD34 RB751V-40
X04
27
57
VGA_PM
12/17
Guangyong
DELL
To fix dynamic MAX8632 PGOOD drop issue.
Change PC197 form 330pF to 820pF
X04
28
47
+VCORE
12/19
Saha
Compal
INTEL CPA line need adjust
PR131 change to 9.76K_0402_1%
X04
29
50
Selector
12/20
Merle
DELL
Hot dock issue, adapter crowber
Add PR357 330K_0402 form +DOCK_PWR_BAR to GND.
X04
Add PQ66 RHU002N06 parallel PQ43, series PR358 0_0402 to EN_DOCK_PWR_BAR#
30
48
Charger
12/21
Merle
DELL
Charger Isense MOSFET timing change
PC142 change to 0.047u_0603_25V
X04
31
47
+VCORE
1/25
Guangyong
DELL
Change VCORE OCSET
Change PR117 form 11.5K to 12.7K_0402_1%
X05
32
48
Charger
1/25
Guangyong
DELL
Change ACAV_IN_NB pull high voltage
Add PR362 100K_0402_5% form PU11B out pull high to ISL88731_VREF
De-pop PR341
X05
33
49
Selector
1/25
AJ
Compal
Charger for Battery Slice
Change PQ63 to 2N7002DW
Add PR360 0_0402_5% between PQ63 and SLICE_BAT_PRES
X05
34
50
Selector
2/12
Merle
DELL
Fix BITS CR196131 and CR196130
Add PR363 1K_1206 and PC262 1U_0603_25V from +NBDOCK_DC_IN_SS to ground
Add PD35 RB751S40T1_SOD523-2 from NB_AC_OFF# to ACAV_IN_NB
X05
35
48
Charger
2/25
Power
Compal
Change Charger sunbber resistor size
form 0805 to 1206.
Change PR281 from 4.7_0805 to 4.7_1206
X05
36
47/48
CPU_CORE
Charger
3/6
EMI
Compal
To solve CPU_CORE and Charger BB noise
Add Bead PL21 on PJP33, Pop PL12
X05
All power
3/6
WWAN
Compal
Change all power rail snubber resistor
form 0805 to 1206 size.
Change all power rail snubber resistor
form 0805 to 1206 size.
X05
Fix Battery slice discharge issue
Change PR260 from 240K to 620K, PR261 from 47K to 33
PQ55 from IMD2AT to 2N7002DW
Add PR364 390K, PR365 390K, PD36 RB751S40T1, PC263 1U_0603.
X05
Add PC264 680p_0402 and PC265 470p_0402 at PL12 +PWR_SRC
X05
D
C
C
PWR
B
37
38
39
Seletor
50
CPU_CORE
47
40
PWR
All PWR
35
48
Charger
3/6
3/7
3/17
Power
Compal
EMI
Compal
EMI
Compal
To solve CPU_CORE and Charger BB noise
Plastic palmrest logic up BB noise solution
Pop +3.3V, +5V, +1.05V, +1.5V, +1.8V, VGA_CORE snubber
R=2.2_1206 C=1000pF_0603
Pop VGH snubber
R=4.7_1206 C=1000pF_0603
Change +3.3V, +1.05V, VGH, VGA_CORE and VCORE boot resistor
PR37=2.2_0603 PR62=2.2_0603 PR155=2.2_0603 PR198=2.2_0603
PR87, PR98, PR121 change to 2.2_0603
Pop PC155=3300pF and PC154=220pF
B
X05
A
A
5/9
Elick
Compal
populate ADAPT_OC function(90W setting)
Pop PR167,PR166,PR171,PR172,PC168,PC169,PC170,PC171,PC172,PR164,PR168
,PC167,PR165,PQ33
un-pop PR170
X07
DELL CONFIDENTIAL/PROPRIETARY
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
Changed-List History 2
Size
Document Number
Custom
2
Rev
0.8
LA-3803P
Date:
Thursday, June 12, 2008
Sheet
1
70
of
71
5
4
3
2
1
Version Change List ( P. I. R. List )
Item Page#
D
Title
Date
Request
Owner
Issue Description
Solution Description
Rev.
42
48
Charger
5/21
Merle
DELL
Reduce delay time between NB adapter removal
and ACAV_IN_NB de-assert from 1.6mS to~400uS.
change PC256 from .1uF to 100pF.
change PR175 from 100K to 24K.
X07
47
V-CORE
5/21
Elick
Compal
Add 33K as a reservation on pin2 of 8791 (CPU
driver all 3 phases) for Maxim V_CORE solution.
Add un-pop PR366(33K 0402) between pin2 of PU6 and GND.
Add un-pop PR367(33K 0402) between pin2 of PU8 and GND.
Add un-pop PR368(33K 0402) between pin2 of PU9 and GND.
X07
43
44
43
DC-IN
6/3
Elick
Compal
45
49
Selector
6/5
Elick
Compal
Glitch issue on SLICE_BAT_PRES#
Reserve a pull high resistor between +3.3V_ALW2
and SLICE_BAT_PRES#
Add PC266:SE074152K8L(S CER CAP 1500P 50V +-10% X7R 0402)
between pin2 of PQ61 and GND.
X07
Add un-pop PR369:SD02847018L(S RES 1/16W 4.7K +-5% 0402)
between +3.3V_ALW2 and PQ40B.5.
X07
D
C
C
46
48
Charger
6/5
47
48
Charger
6/5
Elick
Compal
un-pop
Elick
Compal
un-Pop PR167,PR166,PR171,PR172,PC168,PC169,PC170,PC171,
PC172,PR164,PR168,PC167,PR165,PQ33
populate PR170:SD02810018L(S RES 1/16W 1K +-5% 0402)
ADAPT_OC function.
Reserve a 0402 size capcitor between NB_AC_OFF#
to GND
X07
Add un-pop PC267 0402 size between PQ35.2 to GND.
X07
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
http://hobi-elektronika.net
5
4
3
2
Title
Changed-List History
Size
Document Number
Date:
Thursday, June 12, 2008
Rev
0.8
LA-3803P
Sheet
1
71
of
71
5
4
3
+3.3V_ALW_ICH
2.2K
G16
ICH_SMBCLK
A13
ICH_SMBDATA
2
1
2.2K
2.2K
2N7002
+3.3V_M
2.2K
MEM_SCLK
197
MEM_SDATA
195
DIMMA
SMBUS Address [TBD]
DIMMB
SMBUS Address [TBD]
2N7002
10K
ICH9-M
197
D
+3.3V_ALW_ICH
10K
C17
AMT_SMBCLK
B18
AMT_SMBDAT
195
D
2.2K
93
2A
94
+3.3V_ALW
2.2K
2A
1A
1A
6
DOCK_SMB_CLK
5
DOCK_SMB_DAT
6
5
1B
1B
SMBUS Address [TBD]
+3.3V_ALW
2.2K
C
DOCKING
2.2K
8
LCD_SMBCLK
6
7
LCD_SMDATA
5
INVERTER
(JLVDS)
C
SMBUS Address [TBD]
2.2K
+3.3V_ALW
2.2K
SIO
1C
112
PBAT_SMBCLK
100 ohm
3
1C
111
PBAT_SMBDAT
100 ohm
4
BATTERY
CONN
SMBUS Address [TBD]
2.2K
1D
1D
2.2K
10
9
2N7002
2.2K
1E
1E
7
EXP_SMBDATA
8
2.2K
+3.3V_ALW
99
2.2K
2.2K
B
98
CARD_SMBCLK
1F
97
CARD_SMBDAT
2N7002
30
WLAN_SMBDATA
32
2N7002
2.2K
2.2K
1H
96
2N7002
95
2N7002
32
2.2K
2.2K
1H
1H
CKG_SMBDAT
13
CKG_SMBCLK
1J
1J
106
105
2.2K
2N7002
2N7002
9
A
+3.3V_ALW
10
Charger
17
CLK_SCLK
16 CLK GEN
1K
5
102
Dedicated JTAG
BT/UWB
SMBUS Address [TBD]
SMBUS Address [TBD]
SMBUS Address [TBD]
2N7002
2.2K
SMBUS Address [TBD]
+3.3V_RUN
3
Compal Electronics, Inc.
Title
SMBUS TOPOLOGY
Size
http://hobi-elektronika.net
4
32
30
A
DAI
SMBUS Address [TBD]
103
30
MINI_SMBDATA
USH
2.2K
1K
SMBUS Address [TBD]
+3.3V_M
CLK_SDATA
2N7002
Dedicated JTAG SMBUS Address [TBD]
B
WLAN
+3.3V_RUN
MINI_SMBCLK
WWAN
2.2K
12
SMBUS Address [TBD]
+3.3V_WLAN
WLAN_SMBCLK
MEC 5035
1G
Express card
2N7002
100
1F
+3.3V_SUS
EXP_SMBCLK
Document Number
Rev
0.8
LA-3803P
Date:
2
Thursday, June 12, 2008
Sheet
1
5
of
71
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