Liberty User Guides And Reference Manual Suite Version 2017.06
Liberty_User_Guide_2017_06
User Manual:
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- Liberty_cover.pdf
- Liberty_2017.06_relnotes
- lug1
- Sample Library Description
- Building a Technology Library
- Creating Library Groups
- Using General Library Attributes
- Delay and Slew Attributes
- input_threshold_pct_fall Simple Attribute
- input_threshold_pct_rise Simple Attribute
- output_threshold_pct_fall Simple Attribute
- output_threshold_pct_rise Simple Attribute
- slew_derate_from_library Simple Attribute
- slew_lower_threshold_pct_fall Simple Attribute
- slew_lower_threshold_pct_rise Simple Attribute
- slew_upper_threshold_pct_fall Simple Attribute
- slew_upper_threshold_pct_rise Simple Attribute
- Defining Units
- Building Environments
- Library-Level Default Attributes
- Defining Operating Conditions
- Defining Power Supply Cells
- Defining Wire Load Groups
- Specifying Delay Scaling Attributes
- Defining Core Cells
- Defining cell Groups
- Defining pin Groups
- pin Group
- General pin Group Attributes
- capacitance Attribute
- clock_gate_clock_pin Attribute
- clock_gate_enable_pin Attribute
- clock_gate_obs_pin Attribute
- clock_gate_out_pin Attribute
- clock_gate_test_pin Attribute
- complementary_pin Simple Attribute
- connection_class Simple Attribute
- direction Attribute
- driver_type Attribute
- fall_capacitance Attribute
- fault_model Simple Attribute
- inverted_output Attribute
- is_analog Attribute
- pin_func_type Attribute
- rise_capacitance Attribute
- steady_state_resistance Attributes
- test_output_only Attribute
- Describing Design Rule Checks
- Describing Clocks
- Defining Bused Pins
- Defining Signal Bundles
- Defining Layout-Related Multibit Attributes
- Defining Multiplexers
- Defining Decoupling Capacitor Cells, Filler Cells, and Tap Cells
- Defining Sequential Cells
- Using Sequential Cell Syntax
- Describing a Flip-Flop
- Using the function Attribute
- Describing a Multibit Flip-Flop
- Describing a Latch
- Describing a Multibit Latch
- Describing Sequential Cells With the Statetable Format
- Flip-Flop and Latch Examples
- Cell Description Examples
- Defining Test Cells
- Timing Arcs
- Understanding Timing Arcs
- Modeling Method Alternatives
- Defining the timing Group
- Naming Timing Arcs Using the timing Group
- Timing Arc Between a Single Pin and a Single Related Pin
- Timing Arcs Between a Pin and Multiple Related Pins
- Timing Arcs Between a Bundle and a Single Related Pin
- Timing Arcs Between a Bundle and Multiple Related Pins
- Timing Arcs Between a Bus and a Single Related Pin
- Timing Arcs Between a Bus and Multiple Related Pins
- Timing Arcs Between a Bus and a Related Bus Equivalent
- Delay Model
- timing Group Attributes
- Naming Timing Arcs Using the timing Group
- Describing Three-State Timing Arcs
- Describing Edge-Sensitive Timing Arcs
- Describing Clock Insertion Delay
- Describing Intrinsic Delay
- Describing Transition Delay
- Modeling Load Dependency
- Describing Slope Sensitivity
- Describing State-Dependent Delays
- Setting Setup and Hold Constraints
- Setting Nonsequential Timing Constraints
- Setting Recovery and Removal Timing Constraints
- Setting No-Change Timing Constraints
- Setting Skew Constraints
- Setting Conditional Timing Constraints
- when and sdf_cond Simple Attributes
- when_start Simple Attribute
- sdf_cond_start Simple Attribute
- when_end Simple Attribute
- sdf_cond_end Simple Attribute
- sdf_edges Simple Attribute
- min_pulse_width Group
- minimum_period Group
- min_pulse_width and minimum_period Example
- Using Conditional Attributes With No-Change Constraints
- Impossible Transitions
- Examples of NLDM Libraries
- Describing a Transparent Latch Clock Model
- Driver Waveform Support
- Sensitization Support
- Phase-Locked Loop Support
- Modeling Power and Electromigration
- Modeling Power Terminology
- Switching Activity
- Modeling for Leakage Power
- Representing Leakage Power Information
- Threshold Voltage Modeling
- Modeling for Internal and Switching Power
- Representing Internal Power Information
- Defining Internal Power Groups
- Naming Power Relationships, Using the internal_power Group
- Power Relationship Between a Single Pin and a Single Related Pin
- Power Relationships Between a Single Pin and Multiple Related Pins
- Power Relationships Between a Bundle and a Single Related Pin
- Power Relationships Between a Bundle and Multiple Related Pins
- Power Relationships Between a Bus and a Single Related Pin
- Power Relationships Between a Bus and Multiple Related Pins
- Power Relationships Between a Bus and Related Bus Pins
- internal_power Group
- equal_or_opposite_output Simple Attribute
- falling_together_group Simple Attribute
- power_level Simple Attribute
- related_pin Simple Attribute
- rising_together_group Simple Attribute
- switching_interval Simple Attribute
- switching_together_group Simple Attribute
- when Simple Attribute
- mode Complex Attribute
- fall_power Group
- power Group
- rise_power Group
- Internal Power Examples
- Naming Power Relationships, Using the internal_power Group
- Modeling Libraries With Integrated Clock-Gating Cells
- Modeling Electromigration
- Advanced Low-Power Modeling
- Power and Ground (PG) Pins
- PG Pin Power Mode Modeling
- Feedthrough Signal Pin Modeling
- Silicon-on-Insulator (SOI) Cell Modeling
- Level-Shifter Cells in a Multivoltage Design
- Operating Voltages
- Level Shifter Functionality
- Basic Level-Shifter Syntax
- Cell-Level Attributes
- Pin-Level Attributes
- std_cell_main_rail Attribute
- level_shifter_data_pin Attribute
- level_shifter_enable_pin Attribute
- input_voltage_range and output_voltage_range Attributes
- ground_input_voltage_range Attribute
- ground_output_voltage_range Attribute
- input_signal_level Attribute
- power_down_function Attribute
- alive_during_power_up Attribute
- Enable Level-Shifter Cell
- Clamping Enable Level-Shifter Cell Outputs
- Level Shifter Modeling Examples
- Isolation Cell Modeling
- Switch Cell Modeling
- Retention Cell Modeling
- Always-On Cell Modeling
- Macro Cell Modeling
- Modeling Antenna Diodes
- Composite Current Source Modeling
- Modeling Cells With Composite Current Source Information
- Representing Composite Current Source Driver Information
- Representing Composite Current Source Receiver Information
- Comparison Between Two-Segment and Multisegment Receiver Models
- Two-Segment Receiver Capacitance Model
- Multisegment Receiver Capacitance Model
- CCS Retain Arc Support
- Composite Current Source Driver and Receiver Model Example
- Advanced Composite Current Source Modeling
- Modeling Cells With Advanced Composite Current Source Information
- Compact CCS Timing Model
- Variation-Aware Timing Modeling Support
- Nonlinear Signal Integrity Modeling
- Modeling Noise Terminology
- Modeling Cells for Noise
- Representing Noise Calculation Information
- I-V Characteristics Lookup Table Model
- Defining the Lookup Table Steady-State Current Groups
- I-V Characteristics Curve Polynomial Model
- Defining Polynomial Steady-State Current Groups
- Using Steady-State Resistance Simple Attributes
- Using I-V Curves and Steady-State Resistance for tied_off Cells
- Defining tied_off Attribute Usage
- Representing Noise Immunity Information
- Representing Propagated Noise Information
- Examples of Modeling Noise
- Composite Current Source Signal Integrity Modeling
- CCS Signal Integrity Modeling Overview
- CCS Signal Integrity Modeling Syntax
- Library-Level Groups and Attributes
- Pin-Level Groups and Attributes
- ccsn_first_stage and ccsn_last_stage Groups
- is_needed Attribute
- is_inverting Attribute
- stage_type Attribute
- miller_cap_rise and miller_cap_fall Attributes
- output_signal_level and input_signal_level Attributes
- dc_current Group
- output_voltage_rise and output_voltage_fall Groups
- propagated_noise_high and propagated_noise_low Groups
- when Attribute
- CCS Noise Library Example
- Conditional Data Modeling in CCS Noise Models
- CCS Noise Modeling for Unbuffered Cells With a Pass Gate
- CCS Noise Modeling for Multivoltage Designs
- Referenced CCS Noise Modeling
- CCS Signal Integrity Modeling Overview
- Composite Current Source Power Modeling
- On-Chip Variation (OCV) Modeling
- Defining I/O Pads
- Library Characterization Configuration
- The char_config Group
- Common Characterization Attributes
- driver_waveform Attribute
- driver_waveform_rise and driver_waveform_fall Attributes
- input_stimulus_transition Attribute
- input_stimulus_interval Attribute
- unrelated_output_net_capacitance Attribute
- default_value_selection_method Attribute
- default_value_selection_method_rise and default_value_selection_method_fall Attributes
- merge_tolerance_abs and merge_tolerance_rel Attributes
- merge_selection Attribute
- CCS Timing Characterization Attributes
- Input-Capacitance Characterization Attributes
- lug2
- Physical Library Group Description and Syntax
- Attributes and Groups
- phys_library Group
- bus_naming_style Simple Attribute
- capacitance_conversion_factor Simple Attribute
- capacitance_unit Simple Attribute
- comment Simple Attribute
- current_conversion_factor Simple Attribute
- current_unit Simple Attribute
- date Simple Attribute
- dist_conversion_factor Simple Attribute
- distance_unit Simple Attribute
- frequency_conversion_factor Simple Attribute
- frequency_unit Simple Attribute
- has_wire_extension Simple Attribute
- inductance_conversion_factor Simple Attribute
- inductance_unit Simple Attribute
- is_incremental_library Simple Attribute
- manufacturing_grid Simple Attribute
- power_conversion_factor Simple Attribute
- power_unit Simple Attribute
- resistance_conversion_factor Simple Attribute
- resistance_unit Simple Attribute
- revision Simple Attribute
- SiO2_dielectric_constant Simple Attribute
- time_conversion_factor Simple Attribute
- time_unit Simple Attribute
- voltage_conversion_factor Simple Attribute
- voltage_unit Simple Attribute
- antenna_lut_template Group
- resistance_lut_template Group
- shrinkage_lut_template Group
- spacing_lut_template Group
- wire_lut_template Group
- phys_library Group
- Attributes and Groups
- Specifying Attributes in the resource Group
- Specifying Groups in the resource Group
- Syntax for Groups in the resource Group
- array Group
- cont_layer Group
- implant_layer Group
- ndiff_layer Group
- pdiff_layer Group
- poly_layer Group
- avg_lateral_oxide_permittivity Simple Attribute
- avg_lateral_oxide_thickness Simple Attribute
- height Simple Attribute
- oxide_permittivity Simple Attribute
- oxide_thickness Simple Attribute
- res_per_sq Simple Attribute
- shrinkage Simple Attribute
- thickness Simple Attribute
- conformal_lateral_oxide Complex Attribute
- lateral_oxide Complex Attribute
- max_current_ac_absavg Group
- max_current_ac_avg Group
- max_current_ac_peak Group
- max_current_ac_rms Group
- max_current_dc_avg Group
- routing_layer Group
- avg_lateral_oxide_permittivity Simple Attribute
- avg_lateral_oxide_thickness Simple Attribute
- baseline_temperature Simple Attribute
- cap_multiplier Simple Attribute
- cap_per_sq Simple Attribute
- coupling_cap Simple Attribute
- default_routing_width Simple Attribute
- edgecapacitance Simple Attribute
- field_oxide_permittivity Simple Attribute
- field_oxide_thickness Simple Attribute
- fill_active_spacing Simple Attribute
- fringe_cap Simple Attribute
- height Simple Attribute
- inductance_per_dist Simple Attribute
- max_current_density Simple Attribute
- max_length Simple Attribute
- max_observed_spacing_ratio_for_lpe Simple Attribute
- max_width Simple Attribute
- min_area Simple Attribute
- min_enclosed_area Simple Attribute
- min_enclosed_width Simple Attribute
- min_fat_wire_width Simple Attribute
- min_fat_via_width Simple Attribute
- min_length Simple Attribute
- min_width Simple Attribute
- min_wire_split_width Simple Attribute
- offset Simple Attribute
- oxide_permittivity Simple Attribute
- oxide_thickness Simple Attribute
- pitch Simple Attribute
- process_scale_factor Simple Attribute
- res_per_sq Simple Attribute
- res_temperature_coefficient Simple Attribute
- routing_direction Simple Attribute
- same_net_min_spacing Simple Attribute
- shrinkage Simple Attribute
- spacing Simple Attribute
- thickness Simple Attribute
- u_shaped_wire_spacing Simple Attribute
- wire_extension Simple Attribute
- wire_extension_range_check_connect_only Simple Attribute
- wire_extension_range_check_corner Simple Attribute
- conformal_lateral_oxide Complex Attribute
- lateral_oxide Complex Attribute
- min_extension_width Complex Attribute
- min_shape_edge Complex Attribute
- plate_cap Complex Attribute
- ranged_spacing Complex Attribute
- spacing_check_style Complex Attribute
- stub_spacing Complex Attribute
- end_of_line_spacing_rule Group
- extension_via_rule Group
- max_current_ac_absavg Group
- max_current_ac_avg Group
- max_current_ac_peak Group
- max_current_ac_rms Group
- max_current_dc_avg Group
- min_edge_rule Group
- min_enclosed_area_table Group
- notch_rule Group
- resistance_table Group
- shrinkage_table Group
- spacing_table Group
- wire_extension_range_table Group
- routing_wire_model Group
- site Group
- tile Group
- via Group
- via_array_rule Group
- Syntax for Groups in the resource Group
- Specifying Attributes in the topological_design_rules Group
- Syntax for Attributes in the topological_design_rules Group
- topological_design_rules Group
- antenna_inout_threshold Simple Attribute
- antenna_input_threshold Simple Attribute
- antenna_output_threshold Simple Attribute
- min_enclosed_area_table_surrounding_metal Simple Attribute
- contact_min_spacing Complex Attribute
- corner_min_spacing Complex Attribute
- end_of_line_enclosure Complex Attribute
- min_enclosure Complex Attribute
- diff_net_min_spacing Complex Attribute
- min_generated_via_size Complex Attribute
- min_overhang Complex Attribute
- same_net_min_spacing Complex Attribute
- topological_design_rules Group
- Syntax for Attributes in the topological_design_rules Group
- Specifying Groups in the topological_design_rules Group
- Syntax for Groups in the topological_design_rules Group
- antenna_rule Group
- adjusted_gate_area_calculation_method Simple Attribute
- adjusted_metal_area_calculation_method Simple Attribute
- antenna_accumulation_calculation_method Simple Attribute
- antenna_ratio_calculation_method Simple Attribute
- apply_to Simple Attribute
- geometry_calculation_method Simple Attribute
- metal_area_scaling_factor_calculation_method Simple Attribute
- pin_calculation_method Simple Attribute
- routing_layer_calculation_method Simple Attribute
- layer_antenna_factor Complex Attribute
- adjusted_gate_area Group
- adjusted_metal_area Group
- antenna_ratio Group
- metal_area_scaling_factor Group
- default_via_generate Group
- density_rule Group
- extension_wire_spacing_rule Group
- stack_via_max_current Group
- via_rule Group
- via_rule_generate Group
- wire_rule Group
- wire_slotting_rule Group
- max_metal_density Simple Attribute
- min_length Simple Attribute
- min_width Simple Attribute
- slot_length_range Complex Attribute
- slot_length_side_clearance Complex Attribute
- slot_length_wise_spacing Complex Attribute
- slot_width_range Complex Attribute
- slot_width_side_clearance Complex Attribute
- slot_width_wise_spacing Complex Attribute
- antenna_rule Group
- Syntax for Groups in the topological_design_rules Group
- Specifying Attributes and Groups in the process_resource Group
- Syntax for Attributes in the process_resource Group
- Syntax for Groups in the process_resource Group
- process_cont_layer Group
- process_routing_layer Group
- cap_multiplier Simple Attribute
- cap_per_sq Simple Attribute
- coupling_cap Simple Attribute
- edgecapacitance Simple Attribute
- fringe_cap Simple Attribute
- height Simple Attribute
- inductance_per_dist Simple Attribute
- lateral_oxide_thickness Simple Attribute
- oxide_thickness Simple Attribute
- res_per_sq Simple Attribute
- shrinkage Simple Attribute
- thickness Simple Attribute
- conformal_lateral_oxide Complex Attribute
- lateral_oxide Complex Attribute
- resistance_table Group
- shrinkage_table Group
- process_via Group
- process_via_rule_generate Group
- process_wire_rule Group
- Specifying Attributes and Groups in the macro Group
- macro Group
- cell_type Simple Attribute
- create_full_pin_geometry Simple Attribute
- eq_cell Simple Attribute
- extract_via_region_within_pin_area Simple Attribute
- in_site Simple Attribute
- in_tile Simple Attribute
- leq_cell Simple Attribute
- source Simple Attribute
- symmetry Simple Attribute
- extract_via_region_from_cont_layer Complex Attribute
- obs_clip_box Complex Attribute
- origin Complex Attribute
- size Complex Attribute
- foreign Group
- obs Group
- site_array Group
- macro Group
- Specifying Attributes and Groups in the pin Group
- pin Group
- capacitance Simple Attribute
- direction Simple Attribute
- eq_pin Simple Attribute
- must_join Simple Attribute
- pin_shape Simple Attribute
- pin_type Simple Attribute
- antenna_contact_accum_area Complex Attribute
- antenna_contact_accum_side_area Complex Attribute
- antenna_contact_area Complex Attribute
- antenna_contact_area_partial_ratio Complex Attribute
- antenna_contact_side_area Complex Attribute
- antenna_contact_side_area_partial_ratio Complex Attribute
- antenna_diffusion_area Complex Attribute
- antenna_gate_area Complex Attribute
- antenna_metal_accum_area Complex Attribute
- antenna_metal_accum_side_area Complex Attribute
- antenna_metal_area Complex Attribute
- antenna_metal_area_partial_ratio Complex Attribute
- antenna_metal_side_area Complex Attribute
- antenna_metal_side_area_partial_ratio Complex Attribute
- foreign Group
- port Group
- pin Group
- Developing a Physical Library
- Defining the Process and Design Parameters
- Defining the Design Rules
- Parasitic RC Estimation in the Physical Library
- Physical Library Group Description and Syntax
- lrm
- Technology Library Group Description and Syntax
- Library-Level Attributes and Values
- General Syntax
- library Group Name
- library Group Example
- Simple Attributes
- bus_naming_style Simple Attribute
- comment Simple Attribute
- current_unit Simple Attribute
- date Simple Attribute
- default_fpga_isd Simple Attribute
- default_threshold_voltage_group Simple Attribute
- delay_model Simple Attribute
- distance_unit and dist_conversion_factor Attributes
- critical_area_lut_template Group
- device_layer, poly_layer, routing_layer, and cont_layer Groups
- em_temp_degradation_factor Simple Attribute
- input_threshold_pct_fall Simple Attribute
- input_threshold_pct_rise Simple Attribute
- is_soi Simple Attribute
- leakage_power_unit Simple Attribute
- nom_process Simple Attribute
- nom_temperature Simple Attribute
- nom_voltage Simple Attribute
- output_threshold_pct_fall Simple Attribute
- output_threshold_pct_rise Simple Attribute
- power_model Simple Attribute
- pulling_resistance_unit Simple Attribute
- revision Simple Attribute
- slew_derate_from_library Simple Attribute
- slew_lower_threshold_pct_fall Simple Attribute
- slew_lower_threshold_pct_rise Simple Attribute
- slew_upper_threshold_pct_fall Simple Attribute
- slew_upper_threshold_pct_rise Simple Attribute
- time_unit Simple Attribute
- voltage_unit Simple Attribute
- Defining Default Attribute Values in a CMOS Technology Library
- Complex Attributes
- capacitive_load_unit Complex Attribute
- default_part Complex Attribute
- define Complex Attribute
- define_cell_area Complex Attribute
- define_group Complex Attribute
- receiver_capacitance_fall_threshold_pct Complex Attribute
- receiver_capacitance_rise_threshold_pct Complex Attribute
- technology Complex Attribute
- voltage_map Complex Attribute
- Group Statements
- base_curves Group
- base_curve_type Complex Attribute
- curve_x Complex Attribute
- curve_y Complex Attribute
- compact_lut_template Group
- base_curves_group Simple Attribute
- variable_1 and variable_2 Simple Attributes
- variable_3 Simple Attribute
- index_1 and index_2 Complex Attributes
- index_3 Complex Attribute
- char_config Group
- internal_power_calculation Simple Attribute
- three_state_disable_measurement_method Simple Attribute
- three_state_disable_current_threshold_abs Simple Attribute
- three_state_disable_current_threshold_rel Simple Attribute
- three_state_disable_monitor_node Simple Attribute
- three_state_cap_add_to_load_index Simple Attribute
- ccs_timing_segment_voltage_tolerance_rel Simple Attribute
- ccs_timing_delay_tolerance_rel Simple Attribute
- ccs_timing_voltage_margin_tolerance_rel Simple Attribute
- CCS Receiver Capacitance Simple Attributes
- Input-Capacitance Measurement Simple Attributes
- driver_waveform Complex Attribute
- driver_waveform_rise Complex Attribute
- driver_waveform_fall Complex Attribute
- input_stimulus_transition Complex Attribute
- input_stimulus_interval Complex Attribute
- unrelated_output_net_capacitance Complex Attribute
- default_value_selection_method Complex Attribute
- default_value_selection_method_rise Complex Attribute
- default_value_selection_method_fall Complex Attribute
- merge_tolerance_abs Complex Attribute
- merge_tolerance_rel Complex Attribute
- merge_selection Complex Attribute
- dc_current_template Group
- em_lut_template Group
- fall_net_delay Group
- fall_transition_degradation Group
- input_voltage Group
- fpga_isd Group
- lu_table_template Group
- maxcap_lut_template Group
- maxtrans_lut_template Group
- normalized_driver_waveform Group
- operating_conditions Group
- output_current_template Group
- output_voltage Group
- part Group
- pg_current_template Group
- power_lut_template Group
- rise_net_delay Group
- rise_transition_degradation Group
- sensitization Group
- pin_names Complex Attribute
- vector Complex Attribute
- timing Group
- type Group
- user_parameters Group
- voltage_state_range_list Group
- wire_load Group
- wire_load_selection Group
- wire_load_table Group
- cell and model Group Description and Syntax
- cell Group
- Attributes and Values
- Simple Attributes
- always_on Simple Attribute
- antenna_diode_type Simple Attribute
- area Simple Attribute
- auxiliary_pad_cell Simple Attribute
- base_name Simple Attribute
- bus_naming_style Simple Attribute
- cell_footprint Simple Attribute
- cell_leakage_power Simple Attribute
- clock_gating_integrated_cell Simple Attribute
- contention_condition Simple Attribute
- dont_fault Simple Attribute
- dont_touch Simple Attribute
- dont_use Simple Attribute
- driver_type Simple Attribute
- driver_waveform Simple Attribute
- driver_waveform_rise and driver_waveform_fall Simple Attributes
- em_temp_degradation_factor Simple Attribute
- fpga_cell_type Simple Attribute
- fpga_isd Simple Attribute
- interface_timing Simple Attribute
- io_type Simple Attribute
- is_pad Simple Attribute
- is_pll_cell Simple Attribute
- is_clock_gating_cell Simple Attribute
- is_clock_isolation_cell Simple Attribute
- is_isolation_cell Simple Attribute
- is_level_shifter Simple Attribute
- is_macro_cell Simple Attribute
- is_soi Simple Attribute
- level_shifter_type Simple Attribute
- map_only Simple Attribute
- pad_cell Simple Attribute
- pad_type Simple Attribute
- power_cell_type Simple Attribute
- power_gating_cell Simple Attribute
- preferred Simple Attribute
- retention_cell Simple Attribute
- sensitization_master Simple Attribute
- single_bit_degenerate Simple Attribute
- slew_type Simple Attribute
- switch_cell_type Simple Attribute
- threshold_voltage_group Simple Attribute
- timing_model_type Simple Attribute
- use_for_size_only Simple Attribute
- Complex Attributes
- Group Statements
- cell Group Example
- critical_area_table Group
- bundle Group
- bus Group
- char_config Group
- clear_condition Group
- clock_condition Group
- dynamic_current Group
- ff, latch, ff_bank, and latch_bank Groups
- related_inputs Simple Attribute
- related_outputs Simple Attribute
- typical_capacitances Simple Attribute
- when Simple Attribute
- switching_group Group
- input_switching_condition Simple Attribute
- output_switching_condition Simple Attribute
- min_input_switching_count Simple Attribute
- max_input_switching_count Attribute
- pg_current Group
- compact_ccs_power Group
- values Attribute
- vector Group
- index_1, index_, index_3, and index_4 Simple Attributes
- index_output Simple Attribute
- reference_time Simple Attribute
- values Simple Attribute
- ff Group
- ff_bank Group
- fpga_condition Group
- generated_clock Group
- intrinsic_parasitic Group
- total_capacitance Group
- latch Group
- latch_bank Group
- leakage_current Group
- gate_leakage Group
- input_low_value Simple Attribute
- input_high_value Simple Attribute
- leakage_power Group
- lut Group
- mode_definition Group
- pg_setting_definition Group
- pg_pin Group
- preset_condition Group
- retention_condition Group
- statetable Group
- test_cell Group
- type Group
- model Group
- pin Group Description and Syntax
- Syntax of a pin Group in a cell or bus Group
- Simple Attributes
- alive_during_power_up Simple Attribute
- always_on Simple Attribute
- antenna_diode_related_ground_pins Simple Attribute
- antenna_diode_related_power_pins Simple Attribute
- antenna_diode_type Simple Attribute
- bit_width Simple Attribute
- capacitance Simple Attribute
- clamp_0_function Simple Attribute
- clamp_1_function Simple Attribute
- clamp_z_function Simple Attribute
- clamp_latch_function Simple Attribute
- clock Simple Attribute
- clock_gate_clock_pin Simple Attribute
- clock_gate_enable_pin Simple Attribute
- clock_gate_test_pin Simple Attribute
- clock_gate_obs_pin Simple Attribute
- clock_gate_out_pin Simple Attribute
- clock_isolation_cell_clock_pin Simple Attribute
- complementary_pin Simple Attribute
- connection_class Simple Attribute
- data_in_type Simple Attribute
- direction Simple Attribute
- dont_fault Simple Attribute
- drive_current Simple Attribute
- driver_type Simple Attribute
- driver_waveform Simple Attribute
- driver_waveform_rise and driver_waveform_fall Simple Attributes
- fall_capacitance Simple Attribute
- fall_current_slope_after_threshold Simple Attribute
- fall_current_slope_before_threshold Simple Attribute
- fall_time_after_threshold Simple Attribute
- fall_time_before_threshold Simple Attribute
- fanout_load Simple Attribute
- fault_model Simple Attribute
- function Simple Attribute
- has_builtin_pad Simple Attribute
- has_pass_gate Simple Attribute
- hysteresis Simple Attribute
- illegal_clamp_condition Simple Attribute
- input_map Simple Attribute
- input_signal_level Simple Attribute
- input_threshold_pct_fall Simple Attribute
- input_threshold_pct_rise Simple Attribute
- input_voltage Simple Attribute
- internal_node Simple Attribute
- inverted_output Simple Attribute
- is_analog Attribute
- is_pad Simple Attribute
- is_pll_reference_pin Attribute
- is_pll_feedback_pin Attribute
- is_pll_output_pin Attribute
- is_unbuffered Simple Attribute
- isolation_cell_enable_pin Simple Attribute
- isolation_cell_data_pin Simple Attribute
- permit_power_down Simple Attribute
- alive_during_partial_power_down Simple Attribute
- is_isolated Simple Attribute
- isolation_enable_condition Simple Attribute
- level_shifter_data_pin Simple Attribute
- level_shifter_enable_pin Simple Attribute
- map_to_logic Simple Attribute
- max_capacitance Simple Attribute
- max_fanout Simple Attribute
- max_transition Simple Attribute
- min_capacitance Simple Attribute
- min_fanout Simple Attribute
- min_period Simple Attribute
- min_pulse_width_high Simple Attribute
- min_pulse_width_low Simple Attribute
- multicell_pad_pin Simple Attribute
- nextstate_type Simple Attribute
- output_signal_level Simple Attribute
- output_signal_level_high Simple Attribute
- output_signal_level_low Simple Attribute
- output_voltage Simple Attribute
- pg_function Simple Attribute
- pin_func_type Simple Attribute
- power_down_function Simple Attribute
- prefer_tied Simple Attribute
- primary_output Simple Attribute
- pulling_current Simple Attribute
- pulling_resistance Simple Attribute
- pulse_clock Simple Attribute
- related_ground_pin Simple Attribute
- related_power_pin Simple Attribute
- restore_action Simple Attribute
- restore_condition Simple Attribute
- restore_edge_type Simple Attribute
- rise_capacitance Simple Attribute
- rise_current_slope_after_threshold Simple Attribute
- rise_current_slope_before_threshold Simple Attribute
- rise_time_after_threshold Simple Attribute
- rise_time_before_threshold Simple Attribute
- save_action Simple Attribute
- save_condition Simple Attribute
- signal_type Simple Attribute
- slew_control Simple Attribute
- slew_lower_threshold_pct_fall Simple Attribute
- slew_lower_threshold_pct_rise Simple Attribute
- slew_upper_threshold_pct_fall Simple Attribute
- slew_upper_threshold_pct_rise Simple Attribute
- state_function Simple Attribute
- std_cell_main_rail Simple Attribute
- switch_function Simple Attribute
- switch_pin Simple Attribute
- test_output_only Simple Attribute
- three_state Simple Attribute
- x_function Simple Attribute
- Complex Attributes
- Simple Attributes
- Group Statements
- ccsn_first_stage Group
- Syntax
- Simple Attributes
- Complex Attribute
- Group Statements
- is_inverting Simple Attribute
- is_needed Simple Attribute
- is_pass_gate Simple Attribute
- miller_cap_fall Simple Attribute
- miller_cap_rise Simple Attribute
- mode Attribute
- stage_type Simple Attribute
- when Simple Attribute
- mode Complex Attribute
- dc_current Group
- output_voltage_fall Group
- output_voltage_rise Group
- propagated_noise_high Group
- propagated_noise_low Group
- ccsn_last_stage Group
- char_config Group
- electromigration Group
- input_ccb Group
- output_ccb Group
- internal_power Group
- Simple Attributes
- Complex Attribute
- Group Statements
- Syntax for One-Dimensional, Two-Dimensional, and Three-Dimensional Tables
- equal_or_opposite_output Simple Attribute
- falling_together_group Simple Attribute
- power_level Simple Attribute
- related_pin Simple Attribute
- related_pg_pin Simple Attribute
- rising_together_group Simple Attribute
- switching_interval Simple Attribute
- switching_together_group Simple Attribute
- when Simple Attribute
- mode Complex Attribute
- fall_power Group
- power Group
- rise_power Group
- max_cap Group
- max_trans Group
- min_pulse_width Group
- minimum_period Group
- receiver_capacitance Group
- timing Group in a pin Group
- Simple Attributes
- Complex Attributes
- Group Statements
- clock_gating_flag Simple Attribute
- default_timing Simple Attribute
- fpga_arc_condition Simple Attribute
- interdependence_id Simple Attribute
- output_signal_level_high Simple Attribute
- output_signal_level_low Simple Attribute
- related_output_pin Simple Attribute
- related_pin Simple Attribute
- sdf_cond Simple Attribute
- sdf_cond_end Simple Attribute
- sdf_cond_start Simple Attribute
- sdf_edges Simple Attribute
- sensitization_master Simple Attribute
- timing_sense Simple Attribute
- timing_type Simple Attribute
- wave_rise_sampling_index and wave_fall_sampling_index Attributes
- when Simple Attribute
- when_end Simple Attribute
- when_start Simple Attribute
- active_input_ccb Complex Attribute
- active_output_ccb Complex Attribute
- function Complex Attribute
- propagating_ccb Complex Attribute
- reference_input Complex Attribute
- mode Complex Attribute
- pin_name_map Complex Attribute
- wave_rise and wave_fall Complex Attributes
- wave_rise_time_interval and wave_fall_time_interval Complex Attributes
- ccs_retain_rise and ccs_retain_fall Groups
- cell_degradation Group
- cell_fall Group
- cell_rise Group
- char_config Group
- compact_ccs_retain_rise and compact_ccs_retain_fall Groups
- compact_ccs_rise and compact_ccs_fall Groups
- base_curves_group Simple Attribute
- values Complex Attribute
- fall_constraint Group
- fall_propagation Group
- fall_transition Group
- ocv_sigma_cell_fall Group
- ocv_sigma_cell_rise Group
- ocv_sigma_fall_constraint Group
- ocv_sigma_fall_transition Group
- ocv_sigma_rise_constraint Group
- ocv_sigma_rise_transition Group
- ocv_sigma_retaining_fall Group
- ocv_sigma_retaining_rise Group
- ocv_sigma_retain_fall_slew Group
- ocv_sigma_retain_rise_slew Group
- ocv_mean_shift_* Groups
- ocv_skewness_* Groups
- ocv_std_dev_* Groups
- output_current_fall Group
- output_current_rise Group
- receiver_capacitance_fall Group
- receiver_capacitance_rise Group
- receiver_capacitance1_fall Group
- receiver_capacitance1_rise Group
- receiver_capacitance2_fall Group
- receiver_capacitance2_rise Group
- retaining_fall Group
- retaining_rise Group
- retain_fall_slew Group
- retain_rise_slew Group
- rise_constraint Group
- rise_propagation Group
- rise_transition Group
- tlatch Group
- ccsn_first_stage Group
- Syntax of a pin Group in a cell or bus Group
- Technology Library Group Description and Syntax