M37640E8 XXXFP_Specification_V1.02_Aug97 XXXFP Specification V1.02 Aug97

User Manual: M37640E8-XXXFP_Specification_V1.02_Aug97

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Preliminary

Ver 1.02

MITSUBISm SEMICONDUCTOR
' . . . . AMERICA, INC.

Mitsubishi

M37640MX·XXXFP Preliminary Specification

This publication, or any parts Ihcn>of, may not be reproduced in any form without the prior written
pennission of Mitsubishi Semiconductor America, Inc:. (MSAI).

Rev. 1.0 Internal Release
Rev. 1.01 Design Spec Updates
Rev. 1.02 Design Spec Updates

April 2, 1997

July 1, 1997
August 28, 1997

The pmduct(s) described in 1hia publication are not designed. intended, or authorized for use as
components in systemS intended for surgic:al implant into the body, or other applications intended to
support or sustsin life, or for any other application in which failure of the product could cn:atc a
situation whele pcnonaI injury ordesth may occur. Should Buyer purdIase or use 1hia product forany
such lUlintendcd or ID1authorizcd application, Buyer shall indemnify and hold MSAI and its officers,
employees. subsidiaries, affiliates, and distributers hannIess against an claims, costs, damages, and
Cltpcnses, and reasonable attorney fees arising out of, clircctly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use. even if such claim a1lcges that
MSAI was negligent rcguding the design and manufacture of the pan.

Information supplied by MSAI is belicvcd to be accurate and reliable. MSAI assumes no
responsibility for any errors tItst may appear in 1hia publication. MSAI reserves the right, without
notice, to make changes in device design or specificstions. Product is subject to availability.

C 1997 Mitsubishi Semiconductor America, Inc.

Mitsubishi

M37640E8-XXXF Preliminary Specification

J....

Contents
1 Product Description
1.1 MCU Features ........................................................ 4
1.2 Pin Description and Layout... ................................. 6

2 Functional Description
2.1 Central Processing Unit... ..................................... 11
2.1.1 Register Structure ........................................... 11
2.1.2 Accumulator (A) ............................................. ll
2.1.3 Index Registers X and Y ................................. 12
2.1.4 Stack Pointer ................................................... 12
2.1.5 Program Counter ............................................ 13
2.1.6 Processor Status Register ............................... 13
2.2 CPU Mode Registers ............................................ 14
2.3 Memory Map ........................................................ 16
2.3.1 Zero page ........................................................ 17
2.3.2 Special Page .................................................... 17
2.3.3 Special Function Registers ............................. 17
2.4 Processor Modes ................................................... 19
2.4.1 Single Chip ..................................................... 19
2.4.2 Memory Expansion ........................................ 20
2.4.3 Microprocessor ............................................... 20
2.4.4 EPROM .......................................................... 20
2.4.5 Slow Memory Wait ........................................ 20
2.4.6 Hold Function ................................................. 23
2.4.7 Expanded Data Memory Access .................... 24
2.5 Peripheral Interface .............................................. 25
2.5.1 Chip Bus Timing ............................................ 25
2.5.2 Peripheral Interface and Access Timing ......... 26
2.6 Input and Output Ports ......................................... 28
2.6.1 Ports ................................................................ 28
2.6.1.1 110 Ports .................................................... 29
2.6.1.2 Power and Ground Pins ........................... .31
2.6.1.3 CNVss Pin ................................................. 31
2.6.1.4 Xin and Xout Pins ..................................... 31
2.6.1.5 Xcin and XCout Pins ................................ 31
2.6.1.6 RESET Pin ................................................ 31
2.6.1.7 RDY Pin ................................................... 31
2.6.1.8 DMAoutPin ............................................. 31
2.6.1.9 F out Pin...................................................... 32
2.6.1.10 SYNCoutPinC ........................................ 32
2.6.1.11 RD and WR Pins ..................................... 32
2.6.1.12 LPF Pin ................................................... 32
2.6.2 Port Control Register ...................................... 32
2.6.3 Port P2 Pull-up Control Register .................... 33
2.7 Interrupt Control Unit.. ......................................... 33
2.7.1 Interrupt Control ............................................. 34
2.7.2 Interrupt Sequence and Timing ...................... 36
2.8 Direct Memory Access Controller ...................... .38
2.8.1 Operation ........................................................ 40
2.8.1.1 Source, Destination, and Transfer Count Register Operation ...................................................... 40
2.8.1.2 DMAC Transfer Request Sources ........... .41

-i

2.8.1.3 Transfer Features for USB and Master CPU
Bus Interface ......................................................... 42
2.8.1.4 DMAC Transfer Mode ............................ .43
2.8.1.5 DMAC Transfer Timing .......................... .43
2.9 Timers ................................................................... 48
2.9.1 Timer X ........................................................... 48
2.9.1.1 Read and Write Method ............................ 48
2.9.1.2 Count Stop Control... ................................ 49
2.9.1.3 Timer Mode ....... :...................................... 49
2.9.1.4 Pulse Output Mode .................................. .49
2.9.1.5 Event Counter Mode ................................. 50
2.9.1.6 Pulse Width Measurement Mode .............. 50
2.9.2 Timer Y ........................................................... 50
2.9.2.1 Read and Write Method ............................ 51
2.9.2.2 Count Stop Control ................................... 51
2.9.2.3 Timer Mode .............................................. 51
2.9.2.4 Pulse Period Measurement Mode ............. 52
2.9.2.5 Event Counter Mode ................................. 52
2.9.2.6 HL Pulse-width Measurement Mode ........ 52
2.9.3 Timer 1 ........................................................... 53
2.9.3.1 Timer Mode .............................................. 53
2.9.3.2 Pulse Output Mode ................................... 53
2.9.4 Timer 2 ........................................................... 53
2.9.4.1 Timer Mode .............................................. 54
2.9.4.2 Pulse Output Mode ................................... 54
2.9.5 Timer 3 ........................................................... 54
2.9.5.1 Timer Mode .............................................. 54
2.10 Universal Serial Bus ........................................... 56
2.10.1 USB Function Control Unit... ....................... 57
2.10.1.1 Serial Interface Engine ........................... 57
2.10.1.2 Generic Function Interface ..................... 57
2.10.1.3 Serial Engine Interface Unit ................... 57
2.10.1.4 Microcontroller Interface Unit.. ..... ;........ 57
2.10.1.5 USB Transceiver..................................... 57
2.10.2 USB Interrupts .............................................. 58
2.10.2.1 USB Function Interrupt .......................... 58
2.10.2.2 USB SOF Interrupt ................................. 59
2.10.3 USB Endpoint FIFOs .................................... 59
2.10.3.1 TransmitFIFOs ....................................... 59
2.10.3.2 Receive FIFOs ........................................ 60
2.10.4 USB Special Function Registers................... 60
2.11 Master CPU Bus Interface .................................. 68
2.11.1 Data Bus Buffer Status Registers (DBBSO,
DBBS1) ................................................................... 71
2.11.2 Input Data Bus Buffer Registers (DBBINO,
DBBIN1) ................................................................. 71
2.11.3 Output Data Bus Buffer Registers (DBBOUTO,
DBBOUT1) ............................................................. 71
2.12 UART ................................................................. 72
2.12.1 Baud Rate Selection...................................... 73
2.12.2 UART Mode Register ................................... 74
2.12.3 UART Baud Rate Register ........................... 74

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

Contents
2.12.4 UART Control Register ................................75
2.12.5 UART Status Register .................................. 75
2.12.6 Transinit/~eceive Fonnat .............................78
2.12.7 Interrupts .................................... :.................78
2.12.8 Clear-to Send (CTS) and Request-ta-Send
(RTS) Signals ..........................................................79
2.12.9 UART Address Mode ................................... 80
2.13 Serial I/O ............................................................ 81
2.13.1 SIO Control Register .................................... 81
2.13.2 SIO Operation ............................................... 81
2.14 Special Count Source Generator ........................ 84
2.14.1 SCSG Operation ........................................... 84
2.14.2 SCSG Description ......................................... 85
2.14.2.1 SCSG1 .................................................... 85
2.14.2.2 SCSG2 .................................................... 85
2.15 Oscillator Circuit ................................................ 86
2.15.1 Description.................................................... 86
2.15.2 Frequency Synthesizer Circuit............. ~ ........ 89
2.16 Low Power Modes .....•........................................91
2.16.1 Stop Mode .....................................................91
2.16.2 Wait Mode ....................................................92
2.17 Reset ...................................................................93
2.18 Key-On Wake-Up ...............................................94

3 Electrical Characteristics
3.1 Absolute Maximum Rating ..................................97
3.2 Recommended Operating conditions ...................97
3.3 Electrical Characteristics ......................................99
4 Application Notes
4.1 DMAC ................................................................ 105 .
4.1.1 Programming ................................................ 105
4.1.2 Application ................................................... 105
4.2 UART ................................................................. 106
4.2.1 Application ~ .................................................. 106
4.3 Timer .................................................................. 106
4.3.1 Usage ............................................................ 106
4.4 Frequency Synthesizer Interface ........................ 107

-ii

~ MITSUBISm SEMICONDUCTOR
. . . AMERICA, INC.

CHAPTER 1
PRODUCT
DESCRIPTION

1 Overview ................... 3
1.1 MCU Features ............. 4
1.2 Pin Description and Layout. . . 6

M37640E8-XXXF Preliminary Specification

Mitsubishi

J,..

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

1 Overview
The 7600 series, an enhanced family of CMOS 8-bit microcontrollers, offers high-speed operation at
low voltage, large internal-memory options, and a wide variety of standard peripherals. The series is
code compatible with the M38000, M37200, M37400, and the M37500 series, and provides many
performance enhancements to the instruction set.
This device is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB)
Version 1.0 specification. This device provides data exchange between a USB-equipped host computer
and PC peripherals such as telephones, audio systems and digital cameras.
The USB function control unit can support all four data transfer types listed in the USB specification:
Control, Isochronous, Interrupt, and Bulk. Each transfer type is used for controlling a different set of
PC peripherals. Isochronous transfers provide guaranteed bus access, a constant data rate, and error
tolerance for devices such as computer-telephone integration (CTI) and audio systems. Interrupt transfers
are designed to support human input devices (HID) that communicate small amounts of data
infrequently. Bulk transfers are necessary for devices such as digital cameras and scanners that
communicate large amounts of data to the PC as bus bandwidth becomes free. Finally, control transfers
are supported and are useful for bursty, host-initiated type communication where bus management is the
primary concern.

24 MHz

1
1
DQ(7:0'
1
1
1
Ao
1 So,Sl
I
I
I

1
1

I'
1
1
1
1

frequency 48 MHz
sYnthesizer

I
I

IBFo
OBFo
IBFl
OBFl

....

UARTX21

]

f%I

]
§
U

r10~

~
~

'":s
f%I
u

1;
(i)
1:;

'"
~

TUners

RAM(1K)

:§

ROM(32K)

1
u
5

7600 CPU

III

DMAx2

...

u
.2= ,

D+

D-

FIFOs

(Normal MeU or DMA Transfer)

110 Ports (PO - P8)

Figure 1·1. Application System Diagram

·3

Mitsubishi

M37640E8-XXXF Preliminary Specification

J...

Table 1-1. Device Feature List

Function Description

Parameter
Number of basic instruction
Instruction execution time
Clock frequency (maximum)

83ns at f(Xin) - 24 MHz
Xin = 24 MHz. XCm - 5 MHz (digital input). 4>- 12 MHz

ROM

External clock Xin and XCm can be selectively divided and multiplied by X to create
system internal clock ell
321{ bytes

RAM

lK bytes

Clock multiplier option
Memory size

PO-P3. P5. P6.
110 8-bit X 7 (8 bits have Key-on Wake-up)
P8
Input/Output ports

P4
P7

USB Function Control

110 5-bit
110 5-bit
FIFO:
Endpoint 0:
Endpoint 1:
Endpoint 2:
Endpoint 3:
Endpoint 4:

IN 16-byte OUT 16-byte
IN 512-byteOUT 8oo-byte·
IN 32-byte OUT 32-byte
IN 16-byte OUT 16-byte
IN 16-byte OUT 16-byte

Master CPU bus interface

DQ(7:0). R(E). W(RfW). So' St, Ao. mFo. OBFo• mFt • OBF t ; total of 17 signals interface
with master CPU (Intel 8042-like interface)

Special Count Source Generator(SCSG)

Baud rate synthesizer

ers, RTS available
ers. RTS available

UARTI

7/8/9-bit character length, with

UART2

7/8/9-bit character length. with

Serial 110
TImers

8-bit X 1 clock synchronous serial 110. supports both master and slave modes
8-bit X 3. 16-bit X 2

DMA
Software slew rate control

PortsPO-PS

Interrupts
Supply voltage

2 channels, 16 address lines. support single byte or burst transfer modes
4 external, 19 internal. 1 software, 1 system interrupts

External memory expansion

Vcc - 45 - 5.5V
Memory Expansion and Microprocessor mode

External Data Memory Access (EDMA)

Allows> 64 Kbyte data access for instruction LOA (indY) and STA (indY)

Device structure
Package

CMOS
80P6N

Operating temperature range

-20 to 85°C

1.1

MCU Features
• 7600 8-bit CPU core, CMOS process
• Instruction Execution Time of 83ns (I-cycle instruction @ - 12 MHz)
• Efficient Software Support (C and/or Assembly)
• ROM: 32 KB On-chip
• RAM: 1 KB On-chip

MCU Features-4

MCU Features

Mitsubishi

M37640E8-XXXF Preliminary Specification

• Built-in Microprocessor or Memory-expansion modes
• Three Slow Memory Wait modes: Software Wait, RDY Wait, and Extended RDY Wait
• Nine I/O Ports, Total 66 Programmable I/O Pins available
• Programmable Direction Control on every I/O pin
• Software Slew Rate Control on every I/O pin
• Master CPU Bus Interface:
• MCU can be operated in Slave mode by control signals from the Host CPU
• 8 Data lines (DQ7-DQO) and R(E), W(RlW), Ao, So' Slo IBFo, OBFo, IBF 1, OBF 1 Signals
Available
• Master CPU Sends and Receives Data, Command and Status by means of DQ7-DQO
• USB Function Control Unit
• USB Transceiver (conforms to USB V1.0 Specification)
• DMA
•
•
•
•
•

Controller:
Two DMA channels available
16 Address Lines for 64K byte Address Space
Single Byte or Burst Transfer modes
Transfer Request by external pins, Software Triggers or Built-in Peripherals
Maximum 6M byte/sec transfer Speed (in Burst mode)

• Timers: Three 8-bit Timers, Two 16-bit Timer available On-chip
• Two Full Duplex UARTs available
• One Master/Slave Clock Synchronous I/O (SIO), Internal or External Clock Selectable
• Built-in Special Count Source Generator (SCSG): can be a clock source for Timer X, UARTs,
and SIO
• Power-saving Wait (IDLE) and Stop (powerdown) modes.

MCU Features

MCU Features-5

M37640E8-XXXF Preliminary Specification

1.2

Mitsubishi

J....

Pin Description and Layout
6'

III

~
Iii 0~ iiI
o 0
0
t:::'

~ N
Q.

t:z;;~

~ ~

i8
0

~
Q.

III

!a
0

III

Iii ~

'1;: '0 ~
0
0
~ Q. Q.
:$.

:$.

iiI
<

in'

III

;:::'
III

~d' ~
!( Q. Q.

0
Q.

10
III

:$. :$. :$. :$. :$.
oud
P3s'ISYNCoud

USBD-

P3s/[WRI

XCVR Power/Ext. Cap

P37/[RiJ]

[ ]Indicates function in memory expansion and microprocessor modes

Vas

P8dUTXD2ISRDY
P81/IURXD2ISCLK

Vex;
PSr/DQ7

PEli~RXD

P6&'DQ6

P8~STXD

P6s'D05

P841'UTXDl

P641'DQ4

P8sfURXDl

P63"OO3

PEliD02

'S .e
aE >= Iw cJO
~ (g ~~Ii III
>' ~J >8 "(~
en
z
w
~'o-~ ~ ~
0
a: ~~
~
lflfl{~

g§

t::>Q.

.n
Q.

u.
Q.
-l

0
=
a: zt=
~ lz Iz

~
~

$
Q.

P8~

P871RfS1

~ ~ 'b

Figure 1·2. Pin Layout
Table 1·2. Pin Description
Name
fOty'ABO
-P1 7/AB15

P2oIDBO
-~IDB7

110

110
110

P3lfRDY

110

P3 1

110
110

P3i(VRFY)
P33"DMAout
IPGM

110

Description
CMOS 110 port (address bus). When the MCV is in memory expansion or microprocessor mode, these pins
function as the address bus.
CMOS 110 port (data bus). When the MCV is in memory expansion or microprocessor mode, these pins function
as the data bus. These pins may also be used to implement the Key-on Wake up function.
CMOS 110 port (Ready). When the MCV is in memory expansion or microprocessor mode, this pin functions as
RDY (hardware wait cycle control).
CMOS 110 port.
CMOS 110 port. When the MCV is in EPROM program mode, the pin is used as VRFY (EPROM memory verify)
CMOS 110 port (DMAout). When the MCU is in memory expansion or microprocessor mode, this pin goes high
during a DMA transfer. When the MCU is in EPROM program mode, the pin is used as PGM (EPROM memory
program).

Pin Description and Layout-6

Pin Description and Layout

J...

Mitsubishi

M37640E8-XXXF Preliminary Specification
Table 1-2. Pin Description

Name

I/O

Description

P34"out

I/O CMOS 110 port (<1». When the MCU is in memory expansion or microprocessor mode, this pin becomes out pin.

P3s/SYNCout

110

CMOS 110 port (SYNC output). When the MCU is in memory expansion or microprocessor mode, this pin
becomes the SYNCout pin.

P3&'WR1(CE)

I/O

CMOS 110 port. (WR output). When the MCU is in memory expansion or microprocessor mode, this pin becomes
WR. When the MCU is in EPROM program mode, the pin is used as CE (EPROM memory chip enable).

P3 7/RD/(OE)

I/O

CMOS 110 port. (RD output). When the MCU is in memory expansion or microprocessor mode, this pin becomes
RD. When the MCU is in EPROM program mode, the pin is used as OE (EPROM memory output enable).

P4tYEDMA

110

CMOS 110 port (EDMA: expanded Data Memory Access). When the MCU is in memory expansion or
microprocessor mode, this pin can become the EDMA pin.

P4 l /INTO
-P4z!INTI

110

CMOS 110 port or external interrupt ports INTO and INTI. These external interrupts can be configured active high
or low.

P<\:3/CNTRO

CMOS 110 port or Tuner X input pin for pulse width measurement mode and event counter mode or Tuner X
I/O output pin for pulse output mode. This pin can also be used as an external interrupt when Tuner X is not in output
mode and the polarity is selected in the Tuner X mode register.

P44"CNTRI

CMOS I/O port or Tuner Y input pin for pulse period measurement mode, pulse H-L measurement mode and event
I/O counter mode or Tuner Y output pin for pulse output mode. This pin can also be used as an external interrupt when
Tuner Y is not in output mode and the polarity is selected in the Tuner Y mode register.

PSdXCin

I/O CMOS 110 port or XCin •

PSlffout
XCout
PS2/OBFo

I/O CMOS I/O port or timer I pulse output pin (can be configured initially high or initially low), or XCout '
I/O CMOS I/O port or OBFo output to master CPU for data bus buffer O.

PS3IIBFO

I/O CMOS I/O port or IBFo output to master CPU for data bus buffer O.

PS4"So

I/O CMOS 110 port or So input from master CPU for data bus buffer O.

PSs/Ao

I/O CMOS 110 port or Ao input from master CPU.

PStIR(E)

I/O CMOS 110 port or R(E) input from master CPU.

PS 7!W(RIW)

I/O CMOS 110 port or W(RIW) input from master CPU.

P60fDQ0
-P671DQ7

I/O CMOS 110 port or master CPU data bus.

USBD-

I/O USB minus voltage line interface, a series resistor of IS-20 ohms should be connected to this pin.

USBIY

110 USB plus voltage line interface, a series resistor of IS-20 ohms should be connected to this pin.

P7cfSOF

I/O CMOS 110 port or USB start of frame pulse output, an 80 ns pulse outputs on this pin for every USB frame.

P7 l /HOLD

I/O CMOS 110 port or HOLD pin.

P7z1S1

I/O CMOS 110 port or SI input from master CPU for data bus buffer 1.

P7~Fl/

HLDA

I/O

CMOS 110 port or IBFl output to master CPU for data bus buffer I, or HLDA pin. IBFI and HLDA are mutually
exclusive. IBFl has priority over HLDA.

P74"OBF l

I/O CMOS 110 port or OBF l output to master CPU for data bus buffer 1.

P8cfUTXD2I
SRDY

I/O

CMOS I/O port or UARTI pin UTXD2 or SIO pin SRDY. UARTI and SIO are mutually exclusive, UARTI has
priority over SIO.

P8 llURXD2I
SCLK

I/O

CMOS 110 port or UARTI pin URXD2 or SIO pin SCLK. UARTI and SIO are mutually exclusive, UARTI has
priority over SIO.

I/O

CMOS 110 port or UARTI pin CTS2 or SIO pin SRXD. UARTI and SIO are mutually exclusive, UARTI has
priority over SIO.

P8iRTS2I
STXD

I/O

CMOS 110 port or UARTI pin RTS2 or SIO pin STXD. UARTI and SIO are mutually exclusive, UARTI has
priority over SIO.

P8JUTXDI

I/O CMOS 110 port or UARTI pin UTXDI.

P8 slURXDi

I/O CMOS 110 port or UARTl pin URXD 1.

P8 61CTSI

I/O CMOS 110 port or UARTl pin CTS 1.

P8z1CTS2I
SRXD

Pin Description and Layout

Pin Description and Layout-7

M37640ES-XXXF Preliminary Specification

Mitsubishi

J....

Thble 1-2. Pin Description
Name
P8iRTSI
AVcc.AVss
CNVss ,

I/O
Description
I/O CMOS I/O portor UARTl pin RTSI.
I Power supply inputs for ~alog circuitry.
I Controls the processor mode of the chip. Normally connected to Vss or Vcc' '

Vcc.Vss

RESET

XCin
XCout

Xin
Xout

I
0

LPF

XCVRPower.
Ext Cap

Power supply inputs: Vcc - 4.5- 5.5Y, Vss - OV.
To enter the reset state. this pin must be kept L for more that 2J1S (20 cycles under normal Vcc conditions). If the
crystal or ceramic resonator requires more time to stabilize. extend this L level time appropriately.
An external ceramic or quartz crystal oscillator is connected between the XCin and XCout pins. If an external clock
source is used. connect the clock source to the XCin pin and leave the XCout pin open.
Input and output signals to and from the internal clock generation circuit Connect a ceramic resonator or quartz
crystal between Xin and Xout pins to set the oscillation frequency. If an external clock is used. connect the clock
source to the Xin pin and leave the Xout pin open.
Low pass filter for the frequency synthesizer.
1) A 3.3V line driver power supply (default after reset) pin
2) An external capacitor (Ext Cap) pin. If Vdd (AVdd) -5V is used for the entire chip. (no separate 3.3V power
supply). a 1¢ or larger capacitor should connect between this pin and Vss to ensure proper operation of the USB
line driver. This option is enabled by setting bit 4 of the USB control register (00 131~ High.

D+ID- Line driver notes: In order to match the USB cable impedance. a series resistor of 15-200
should be connected to each USB line; i.e. on D+ (pin 70) and on D- (pin 71). If the USB line is
improperly terminated or not matched, signal fidelity will suffer, resulting in excessive overshoot or
undershoot. This will potentially introduce bit errors.

Pin Description and Layout-8

Pin Description and Layout

iii"&.

MITSUBISm SEMICONDUCTOR
AMERICA, INC.

Chapter 2
Functional
Description

2.1 Central Processing Unit ....... 11
2.2 CPU Mode Registers ......... 14
2.3 Memory Map ................ 16
2.4 Processor Modes ............ 19
2.5 Peripheral Interface ........... 25
2.6 Input and Output Ports ....... 28
2.7 Interrupt Control Unit ......... 33
2.8 Direct Memory Access Controller. 38
2.9 Timers ..................... 48

2.10 Universal Serial Bus ......... 56
2.11 Master CPU Bus Interface.... 68
2.12 UART ..................... 72
2.13 Serial 1/0 . ................. 81

2.14 Special Count Source Generator 84
2.15 Oscillator Circuit ............ 86
2.16 Low Power Modes .......... 91
2.17 Reset ...................... 93

2.18 Key-On Wake-Up ........... 94

M37640ES-XXXF Preliminary Specification

Mitsubishi

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M37640E8-XXXF Preliminary Specification

Mitsubishi

2 Functional Description
2.1

Central Processing Unit
The central processing unit (CPU) has six registers:
• Accumulator (A)
• Index Register X (X)
• Index Register Y (Y)
• Stack Pointer (S)
• Processor Status Register (PS)
• Program Counter (PC)

2.1.1

71
71
71
7

PCH

Accumulator
Index Register X
Index Register Y
Stack Pointer

PCl

1°
1°
1°
1°
1°Program Counter

71Nlvl TI BI 0111 z ICI O

I L...:::

Carry Flag (bit 0)

Zero Flag (bit l)
Interrupt Disable Flag (bit 2)
Decimal Mode Flag (bit 3)
Break Flag (bit 4)
Index X Mode Flag (bit 5)
Overflow Flag (bit 6)
Negative Flag (bit 7)

Figure 2-1. Register Structure

Five of the CPU registers are 8-bit registers, Accumulator (A), Index register X (X), Index register Y
(y), Stack pointer (S), and the Processor Status register (PS).
The PC is a 16-bit register consisting of two 8-bit registers (PeR and PCL) (see Figure 2-3.).
Mter a hardware reset, bit 2 (the I flag) of the PS is set High and the values at the addresses FFFAl6
and FFFB 16 are stored in the PC, but the values of the other bits of the PS and the other registers are
undefined. Initialization of undefmed registers may be necessary for some programs.

2.1.2

Accumulator (A)

The accumulator is the main register of the microcomputer. Data operations such as data transfer, input!
output, and so forth, are executed mainly through the accumulator.

Central Processing Unit

Central Processing Unit-ll

Mitsubishi

M37640E8-XXXF Preliminary Specification

2.1.3

Index Registers X and Y

Both index registers X and Y are 8-bit registers. In the absolute addressing modes, the contents of
these. ~~gisters are added to. the value of the OPERAND to spec~fy the real address ..
. In the indirect X addressing mode, the value of the OPERAND is added to the contents of register X
to specify the zero page basic address. The data at the basic address specifies the real address.
In the indirect Y addressing mode, the value of the operand specifies a zero page address. The data at
this address is added to the contents of register Y to produce the real address: 'These addressing modes
are useful for referencing subroutine tables and memory tables.
When the T flag in the processor status register is set High, the value contained in index register X points
to a zero page memory location that replaces the accumulator for most accumulator based instructions.

2.1.4

Stack Pointer

Main Routine

I ...... · I
Inte~ R!l9u~s!
Ole I)

...

·1
I ...... · I

L M(S)..--

(PCb)

. . - - (S-I)

Return Address Storea
on Stack (Note 2)
1 M(S)..-- (PCI)

1 (S)

. . - - (S-I)J

I
ExecuteJSR
~

I .... · .. I

1 M(S)..-1
1 (S) . . - -

(PCb)

(S-1)

1 M(S)..-1
1 (S)
1
1 M(S)..--

(PCJ)

(S-1)

(PS)

1Processor Status

(S-1)

II Flag set Higb

..--

·1

Contents of

..--

(S)

Return Address stored
on Stack (Note 2)

Jump Vector Fetched

I-

Subroutine

-I

Interrupt Routine

ExecuteRTS

ExecuteRTI

(S)

. . - - (8+1)

1 (S)

. . - - (S I) Ifontentsof
+
Processor Status
Register Restored
1

1(pcJ)

. . - - M(S)

1(PS)

. . - - M(S)

Return Address
Restored

I-

(S)

. . - - (S+I)

1 (S)

. . - - (8+1)

1
1

1
1(PCb)..-I

M(S)

(PC)..-- (pc+1)1

1(PCI)..-1
I (S) . . - 1

L(PCb)..--

M(S)

(S+I)

Return Address
Restored

M(S).I

Figure 2·2. Register Push and Pop when Servicing Interrupts and Calling Subroutines

Note 1. The condition to enable an interrupt Interrupt enable bit is High and Interrupt inhibit flag
(I flag) is Low.
Note 2. When an interrupt occurs, the address of the next instruction to be executed is stored on the
stack. When a subroutine is called, the address of (next instruction -1) to be executed is stored
on the stack.

Central Processing Unit·12

Central Processing Unit

Mitsubishi

M37640E8-XXXF Preliminary Specification

The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to
store the current address data and processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the contents of the stack pointer. The
upper eight bits of the stack address are determined by the Stack Page Select Bit, bit 2 of the CPU
Mode Register A. If the Stack Page Select bit is ''0'', then the RAM in the zero page (addresses
0070 16 to OOFF I6 ) is used as the stack area. If the stack page select bit is High (the default value),
then the RAM in one page (addresses 0100 16 to 01FF 16) is used as the stack area. The base of the
stack must be set in software, and stack grows towards lower addresses from that point. The operations
of pushing register contents onto the stack- and popping them from the stack are shown in Figure 2-4.

2.1.5

Program Counter

The program counter (PC) is a 16-bit register consisting of two 8-bit sub-registers PCH and PCL. It
is used to indicate the address of the next instruction to be executed.

2.1.6

Processor Status Register

The processor status (PS) register is an 8-bit register consisting of flags that indicate the status of the
processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C),
Zero (Z), Overflow (V), or the Negative (N) flags.
After reset, the I flag is set High, but all other flags are undefined. Because the T and D flags directly
affect arithmetic operations, they should be initialized in the beginning of a program.

Carry Flag (C)
The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately
after an arithmetic operation. It is also affected by shift and rotate instructions. The C flag can be
set directly by the set carry (SEC) instruction and cleared by the clear carry (CLC) instruction.
Zero Flag (Z)
The Z flag is set if the result of an arithmetic operation or a data transfer is "0", and cleared if the
result is anything other than "0".
Interrupt Disable Flag (I)
The I flag disables all interrupts except for the interrupt generated by the BRK instruction and any
non-maskable interrupts, if available. Interrupts are disabled when the I flag is High. When an
interrupt occurs, this flag is automatically set High to prevent other interrupts from interfering until
the current interrupt service routine is completed. The I flag can be set by the set interrupt disable
(SEI) instruction and cleared by the clear interrupt disable (CLI) instruction.
Decimal Mode Flag (D)
The D flag determines whether additions and subtractions are executed in binary or decimal. Binary
arithmetic is executed when this flag is Low; decimal arithmetic is executed when it is High.
Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used
for decimal arithmetic. The D flag can be set by the set decimal mode (SED) instruction and cleared
by the clear decimal mode (CLD) instruction.
Break Flag (B)
The B flag is used to indicate whether the current interrupt was generated by the BRK instruction.
The BRK flag in the processor status register is nominally Low. When the BRK instruction is used
to generate an interrupt, the processor status register is pushed onto the stack with the break flag set
High. The saved processor status is the only place where the break flag is ever set.

Central Processing Unit

Central Processing Unit-13

Mitsubishi

M37640E8-XXXF Preliminary Specification

Index X Mode Flag (T)
When the T flag is ''0'', arithmetic operations are performed between accumulator and memory,
the results are stored in the accumulator. When the T flag is High, direct arithmetic operations
direct data transfers are enabled between memory and memory, as well as between I/O and I/O.
result .of an arithmetic ()peration performed on data in memory location 1 and memory location
stored in memory location 1.
.
.

and
and
The
2 is

The address of memory location 1 is specified by index register X, and the address of memory
location 2 is specified ..by normal ..addressing modes. The T flag can be set by the set T flag (SET)
instruction and cleared by the clear T flag (CLT) instruction. Because the T flag directly affects
calculations, it should be initialized after a reset.
Overflow Flag (V)
The V flag is used during the addition or subtraction of one byte of signed data. It is set if the
result exceeds the range from +127 to -128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored in the overflow flag. The V flag can
be cleared by the CLV instruction, but there is no set instruction. In decimal mode, the V flag is
invalid.
Negative Flag (N)
The N flag is set if the result of an arithmetic operation or data transfer is negative, that is (bit 7
is High). When the BIT instruction is executed, bit 7 of the memory location operated by the BIT
instruction is stored in the negative flag. There are no instructions for directly setting or clearing the
N flag.

2.2

CPU Mode Registers
Address

Description

Code

000016

CPU mode register A

CPUMA-OC

0001 16

CPU mode register B

CPUMB-83

This device has two CPU mode registers: CPU Mode Register A (CPUMA) and CPU Mode Register
B (CPUMB) that control the processor mode, clock, slow memory wait and other CPU functions. The
bit representation of each register is described in Figure 2-3 and Figure 2-4:

CPU Mode Registers-14

CPU Mode Registers

J...

Mitsubishi

t;tSB

M37640E8-XXXF Preliminary Specification

CPMA7

CPMA6

CPMAS

CPMA4

CPMA3

CPMA2

CPMAI

CPMAO

Address: 0000 16
Access: RIW

CPMAO, I

Processor Mode Bits (bits 0,1)
Bit I Bit 0
00: Single,Chip Mode
o I: Memory Expansion Mode
I 0: Microprocessor Mode
II: Not used
CPMA2
Stack Page Selection Bit (bit 2)
0: In page 0 area
I: In page I area
CPMA3
Xcout Drive Capacity Selection Bit (bit 3)
0: Low
l:High
CPMA4
Oock XCin,XC out Stop Bit (bit 4)
0: Stop
I:Oscillator
CPMA5
Clock Xin-Xout Stop Bit (bit 5)
O:Oscillator
I:Stop
Internal Clock Selection Bit (bit 6)
CPMA6
O:Externai Clock
I:fsyn
CPMA 7
External Clock Selection Bit (bit 7)
O:Xin,Xout
I:XCin,XCout

Reset:

OC 16

Figure 2-3. CPU Mode Register A

t;tSB

CPMB7

Reserved

CPMB5

CPMB4

CPMB3

CPMB2

CPMBI

CPMBO,I

CPMBO

Slow Memory Wait Bits (bit 1,0)
Bit I Bit 0
00: No wait
oI: One time wait
I 0: Two time wait
II: Three time wait
Stack Page Selection Bit (bit 2)
CPMB2,3
Bit 3 Bit 2
00: Software wait
oI: Not used
10: Fixed wait by RDY pin L
I I: Extended RDY wait
CPMB4
Expanded Data Memory Access Bit (bit 4)
O:EDMA output disabled (64 Kbyte data access area)
I:~ output enabled (greater than 64 Kbytes data access area)
CPMB5
HOLD Function Enable Bit (bit 5)
O:HOLD Function Disabled
I:HOLD Function Enabled
CPMB6
Reserved
CPMB7
Xout Drive Capacity Selection Bit (bit 7)
O:Low
I:High (default state after reset and after STOP mode)

Address: 0001 16
Access: RIW
Reset:

83 16

Figure 2-4. CPU Mode Register B

CPU Mode Registers

CPU Mode Registers-IS

Mitsubishi

M37640E8-XXXF Preliminary Specification

2.3

J..

Memory Map
0000 16
SFR Area
006F 16

Zero Page

0070 16

OOFF I6
0100 16
046F16
0470 16

Not Used

7FFF I6

8000 16

Reserved Area

Special page for
subroutine calls

Reserved Area
'--_ _ _ _ _-'FFFF I6

Figure 2-5. Memory Map

The first 112 bytes of memory from 0000 16 to 006F 16 are the special function register (SFR) area and
contain the CPU mode registers, interrupt registers, and other registers to control peripheral functions
(see Figure 2-7.).
The general purpose RAM resides from 0070 16 to 046F I6• When the MCU is in memory expansion
or microprocessor mode and external memory is overlaid on the internal RAM, the CPU reads data
from the internal RAM. However, the CPU writes data in both the internal and external memory. The
area from 0470 16 to 7FFF I6 is not used in single-chip mode, but can be mapped for an external
memory device when the MCU is in memory expansion or microprocessor mode.
The area from 8000 16 to 807F 16 and from FFFC I6 to FFFFI6 are factory reserved areas. Mitsubishi
uses it for test and evaluation purposes. The user can not use this area in single-chip or memory
expansion modes.
The user 32K byte ROM resides from 8080 16 to FFFB 16. When the MCU is in microprocessor mode,
the CPU accesses an external area rather than accessing the internal ROM.
Zero page and special page area can be accessed by 2-byte commands by using special addressing
modes.
Memory Map-16

Memory Map

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

2.3.1

Zero page

The 256 bytes zero page area is where the SFR and part of the internal RAM are allocated. The zero
page addressing modes can be used to specify memory and register addresses in this area (see
Figure 2-6.). These dedicated addressing modes enable access to this area with fewer instruction cycles.

j,,- - - --+ ----Addressing Modes for

=1~:

Zero
Zero
Zero
-Zero
Zero
Zero

__ _

Addressing modes in which zero

Page
Page
Page
Page
Page
Page

(2 byte instruction)
Indirect (2 byte instruction)
X (2 byte instruction)
Y (2 -byte instruGtion)
Bit (2 byte instruction)
Bit Relative (3 byte instruction)

Absolute (3 byte instruction)
Absolute X (3 byte instruction)
Absolute Y (3 byte instruction)
Relative (2 byte instruction)
Indirect (3 byte instruction)
Indirect X (2 byte instruction)
Indirect Y (2 byte instruction)

--------t
Addressing modes m which
special page access is possible

-=l~'~~ _ _ _-----------------------,
Special Page (2 byte instruction)

Addressing mode
for special page only

----y----,~
Figure 2-6. Zero Page and Special Page Addressing Modes

2.3.2

Special Page

The 256 bytes from address FFOO 16 to FFFF16 are called the special page area. In this area special
page addressing can be used to specify memory addresses (see Figure 2-6.). This dedicated special page
addressing mode enables access to this area with fewer instruction cycles. Frequently used subroutines
are normally stored in this area.

2.3.3

Special Function Registers

The special function registers (SFR) are used for controlling the functional blocks, such as 110 ports,
Timers, DART, and so forth (see Table 2-3.). The reserved addresses should not be read or written to.

Memory Map

Memory Map-I7

Mitsubisbi

M37640E8-XXXF Preliminary Specification

J...

Table 2-3. SFR Addresses

Memory Map-IS

Memory Map

J...

Mitsubishi

2.4

M37640E8-XXXF Preliminary Specification

Processor Modes
The operation modes are described below. The memory maps for the first three modes are shown in
Figure 2-7.
Single chip mode is normally entered after reset. However, if the MCU has a CNV ss pin, holding this
pin High will cause microprocessor mode to be entered after reset. After the reset sequence has
completed, the mode can be changed with software by modifying the value of bits 0 and 1 of
CPUMA. However, while CNVss is High, bit 1 of CPUMA is High and cannot be changed.
Single Chip Mode
0000

0007
0008

Memory Expansion Mode

CPMA. CPUMB.&
Int Registers

Microprocessor Mode

0000

0007
0008

SFR

OOOF
0010

006F
0070

OOFF
0100

046F
0470

7FFF
8000
807F
8080

Reserved Area

7FFF
8000

Reserved Area

807F
8080
ROM

ROM
FFC9

Interrupt
Vectors

Interrupt
Vectors
FFFB
FFFC

FFFF

Reserved Area

FFFB
FFFC
FFFF

Reserved Area

FFFF

Figure 2-7. Operation Modes Memory Maps

2.4.1

Single Chip

In this mode, all ports take on their primary function and all internal memory is accessible. Those
areas that are not in internal memory are not accessible. Also, slow memory wait and EDMA are
disabled in this mode.

Processor Modes

Processor Modes-19

M37640E8-XXXF Preliminary Specification

2.4.2

Mitsubishi

J...

Memory Expansion

In this mode, Ports 0 and 1 output the address bus (ABO-AB1S)' port 2 acts as the data bus input and

output, and port 3 bits 7 to 3 output RD, WR, SYNCout, -~-~DBo
D

Internal

~
Port P3z - P30

110XPort

PortP3

Same as
Microprocessor Mode

Port~-P2o

Port 34

~
Port 3z

\!!V'Output

Same as
Microprocessor Mode

Port 36
\iilOulpUt

. YNCou
~
---1 Port 3
DMAout Ou2!t
3

Figure 2-8. Function of Ports P O-P3 in each Processor Mode

DBin/out:

RD:~
,

WR:

'~ ~,-_.'6Iii_'__",'>-:
, ,
f--T--1~--Ir:

ADoUl :
DBin/oUl :
-RD-:

WR:

:11--r--.-.,....,.-.-....-4

RDY'

Figure 2-9. Software Wait Timing Diagram

Processor Modes

Processor Modes-21

Mitsubisbi

M37640E8-XXXF Preliminary Specification

DBin/out •

RD:
WR .

.
:l--f:
:~

~
~

~.......-.,.....,.~

•

~ ~
~
I

___
,. ••
_....._I_n_..J>+

J....

~,,_.....;;00Il;;;..._-'>-;

~
I
I
I
I
I

ROY'

ADout :
DBiniout •

RD'

...._ _ _ _....

WR .
ROY.

I!la Ihtem'al 'Signals'
Figure 2·10. RDY Wait Tuning Diagram

Processor Modes·22

Processor Modes

J....

M37640E8-XXXF Preliminary Specification

Mitsubishi

II~

,r 'wI ",

WR: :

•

,-.t~

:,:
,

,'sui

, ,

~tsul

r
'41_ '

............

' ..... 1'4"r

RDY:~
I

, ,

DBin/out: , , , ,
RD: :

, , ,

, .'

J: :

It~

~~_:

Itsd

.....

:~1+7 :~~~~
!

III~

I~~

:1.._'_....._.......................:......r:
i

Itlll

: ,n:-+tt:--±
, ,

,~:

::::

, ,

,
ADout :

DBin/out " , •

I
Ii.
I

....,..

>+- :--;<

Out
I
I

I
I

lit...,
I

ILl

Itsu'

I .......

t_~_

i,i I
I

In
I
I

I
I

.tsd

•

I
Iii

I
I

ILl-....!...

I
I

tsb

I
I

WR:

•

.........

~ :~:

;

l'1il:3 RDY ~o~~ ~t~~ ~~~ait:
Internal"
Signals' '. . .

CPUMB

.. OE·16'.

....

I
•

I
I

•
I

t_!_

,"'11

=!t J:!r

........

..............................

,tSu.
~

,tiu

Ii: I:
I

•

ii,

su.

, ,

Three Time ElItended ROY. WBit I

• . .CPUMB .. OF I6

! I I itsul t I
~t. ' .......... '

: • • • ,

I
I

>+-:

Out

Iii

RD', ' ~'-""""
' ,"'11t!=t
......... - . . ..... ' ........... ,""?I""- , , ,
~
~ -pt
4iJII ...
.=!t14T .-..e....-r ....... t+r
.tSu,
• lin
1m
lku
1m
I

r:>+- ~

Figure 2-11. Extended RDY Wait Timing Diagram

2.4.6

Hold Function

The hold function is used when the MCU is put in a system where more than one device will need
control of the external address and data buses. Two signals are used to implement this function, HOLD
and HLDA. HOLD is an input to the MCU and is brought Low when an external device wants the
MCU to relinquish the address and data buses. HLDA is an output from the MCU that signals when
the MCU has relinquished the buses. When this is the case, the MCU tri-state ports 0 and 1 (address
bus) and port 2 (data bus), and holds port P37 (RD) and port P36 (WR) High. Ports P37 and P36 are
held High to prevent any external device that is enabled by RD or WR from being falsely activated.
The clocks to the CPU are stopped, but the peripheral clocks and port P34 (Wout) continue to oscillate.
HOLD is brought High to allow the MCU to regain the address and data buses. When this occurs,
HLDA will go High and ports PI' P 2, P3 7 and P36 will begin to drive the external buses again. The
timing for the hold function is shown in Figure 2-12. The hold function is only valid for memory
expansion and microprocessor modes. Bit 5 of CPUMB is used to enable the hold function.

Processor Modes

Processor Modes-23

Mitsubishi

M37640E8-XXXF Preliminary Specification

J....

XIN
PI '
P2
PIPER'
P2PER

SYNCoot~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~

Address
Data
EDMA:~-------------~

Figure 2-14. LDA Y Instruction Sequences with EDMA Enabled

2.5

Peripheral Interface

2.5.1

Chip Bus Timing

The internal bus timing is described below for the CPU (or DMAC) writing to and reading from a
peripheral (see Figure 2-15.)
• The address (AB[15:0]) is output from the CPU on P2.
• The data bus (DB[7:0]) is driven by the CPU during a write, or by
on PI.

a peripheral

during a read,

• The RIW signal is High for a read and Low for a write, and changes on P2.
• The EB signal is High when a read or write is not valid, and is Low for a valid read or write.
It changes on P2.
• A PDnB signal (peripheral decode) is assigned to each peripheral and is Low when reading from
or writing to the peripheral. Each PDnB signal is clocked on P2 timing.
The address, RJW, EB, and PDnB signals are latched at the peripheral block on PI, so they must all
be valid before this time. The data bus is latched by the CPU during a read, or by a peripheral during
a write, on P2; so the value on the data bus must be valid before this time.

Peripheral Interface

Peripheral Interface-25

Mitsubishi

M37640E8-XXXF Preliminary Specification

2*cI>--1

PI__~____~__-J(~-~~~

____ __

P2~

AB[I5:0], RIW,

EB,~;;::::==========~

1...

L
L

-J

'lN8Ii

PDnB [P2~

\II6Iil1!liUll~'---_-:-_-:-_

AB[I5:0], RIW, EB,
'/:\
PDnB laochoo@--~----~-----J,
~--~----~----~'I
,
peripheral [pI]
AB[2:0], RIW, EB,--.........--"----""""\\&t
PDnB peripheral [PI]
~

DB[7:0] [PI]
DB[7:0] iaochoo [P2]

~
,

',,-----...

---{

~~----~----~----~;

:\1-----.;.-----;.--

Figure 2-15. 7600 Series Internal Bus Timing

2.5.2

Peripheral Interface and Access Timing

The 7600 series offers a wide variety of peripherals. These include RAM, ROM, EPROM, UARTs,
SIOs, 8-bit and 16-bit timers, AID converters, D/A converters, various 110 ports, OpAmps, and clock
generators, to name a few.
The interface between the CPU, the peripheral decode block, and peripheral blocks is shown in
Figure 2-16. Signals DB7 to DBO, AB2 to ABO, RIW, EB, and at least one peripheral decode (PDnB)
are routed to each peripheral. The address signals and peripheral decode signal are used in the
peripheral block to create decode signals for each register. Because three address bits are available at
the peripheral, a maximum of eight decode signals can be created for each peripheral decode signal.
If the peripheral contains more than eight registers, additional peripheral decode signals are routed to
the peripheral.
The bus timing for reading from and writing to a peripheral is shown in Figure 2-17.
• When P2goes High, the address, RIW, and EB are output from the CPU. All address signals are
routed to the peripheral decode block where a peripheral decode signal is generated
asynchronously.· Also, data read from a peripheral in the previous half cycle is latched in the
CPU, and data written to a peripheral in the previous half cycle is latched in the desired register
of the peripheral at this time.
• When PI goes High, address AB[2:0], RIW, EB, and PDnB are latched at the peripherals. From
these signals, the determination of which peripheral and register inside of that peripheral is to be
written or read is made. Also, if the CPU is writing to a peripheral, it begins to drive the data
bus at this time with the data to be written to the peripheral. If the CPU is reading from a
peripheral, the peripheral begins to drive the data bus as soon as the decode is finished and the
data is available from the register.
This timing does not apply for the RAM and ROM/EPROM.

Peripheral Interface-26

Peripheral Interface

J..

M37640E8-XXXF Preliminary Specification

Mitsubishi

[Pjl

OB[7:01

perOB[7:0]

......... t-

cpu..§J
P

..-[P2)

t-- r--

.,..,

RlW

I - r--

AB[2:0). R/W. EB

AB[15:0)
PI

Peripheral PDIB
P02B
Decode

II::~
AS

IPrl.

r - ....
Dl
D

f)-WRre g

! - - - re

:IE.!

;)

-'"

···
··
·

E
RDreg
~l

! - - - i-tI

t-- r-

PONJ

Peripheral N

Figure 2-16. Internal Peripheral Interface

L
,

,
PI ________

CPU: AB, RfW, EB
Active Peripheral Decode (pDnB)
AB, RfW, EB, PDnB
lalChed@peripheral

____- J'/

=~~~~~~~=[=====:2~~~~~r=~==~F=

AB, RfW, EB. PDnB peripheral _......:..__________....J

~'--

_ _ _ _ _ _ _ _ _ __ _ J

~'------

REAb from peripheral

RDbuf
ROreg
perDB
DB

:;111 :

>tOlIIII/Ili

*:-_-:-__

====:;=. ==== =====;-7;*~---':"'.-.....,;,...-~------X"--===:a:::::=
='"=.

=±;:;,

X,-r-"=::::t==

=:;::::=:o::::=~~

-----?r

CPU read of DB [P2] ---.;------.;-----.....;------....
'

WRITE to perip~eral
WRreg[P2] _____________________

--Jt

----.......,r----....J~
DB
--------:-----'>tOlIIII/Ili
,
,

perDB -

.......

~'--.....;---...;.--

~I...-------

*===~==

*'----:--

Figure 2-17. 7600 Series Peripheral Bus Timing

Peripheral Interface

Peripheral Interface-27

Mitsubisbi

M37640ES-XXXF Preliminary Specification

2.6

J....

Input and Output Ports
Address
OOOS16

000916
OOOA 16
OOOB 16
OOOC 16
OOOD 16
OOOE16
OOOF16
001416
001S16

Description

Acronym and
Value at Reset

. po=oo

Port PO
Port PO direction register

POD-OO

Port PI

PI-O

Port PS direction register

PSD=OO

00lS16 PortP6
0019 16 Port P6 direction register
00lA16 PortP7
OOlB 16 Port P7 direction register

P6-00
P6D=OO

00lC 16 PortPS
OOlD16 Port PS direction register

PS-O
P7D=OO

is multiplexed with EDMA
are multiplexed with external interrupts INTO, INTI
is multiplexed with TImer X CN1RO pin
is multiplexed with TImer Y CN1RI pin
is multiplexed with xqn
is multiplexed with TImer I pulse output pin or XCout
is multiplexed with OBFo output to master CPU
is multiplexed with IBFo output to master CPU
is multiplexed with So input to master CPU
is multiplexed with Ao input to master CPU
is multiplexed with R (E) input to master CPU
is multiplexed with W (RfW) input to master CPU

Bits60~ are multiplexed

Bit 70
Bit 71
Bit 72
Bit 73
Bit 74
Bits SO-S3

with Master CPU Bus IIF DQO-DQ7 pins
is multiplexed with SOP
is multiplexed with HOLD
is multiplexed with SI
is multiplexed with IBf't or HLDA
is multiplexed with OBF1
are multiplexed with the first alternate function UARTI pins or 2nd alternate function with

SIOpins

Bits S4-S7 are multiplexed with the UARTI pins

2.6.1

Ports

This device has 66 programmable I/O pins arranged as ports POo to PS7• Each port bit can be
configured as input or output. To set the I/O port bit direction, write a "1" to the corresponding
direction register bit to select output mode, or write a "0" to the direction register bit to select input
mode.

Input and Output Ports-28

Input and Output Ports

M37640E8-XXXF Preliminary Specification

Mitsubishi

At reset, all of the direction registers are initialized to 00 16, setting all of the I/O ports to input mode.
If data is written to a pin and then read from that pin while it is in output mode, the data read is the

value of the port latch rather than the value of the pin itself. Therefore, if an external load changes the
value of an output pin, the intended output value will still be read correctly. Pins set to input mode
are floating (provided that the pull up resistors are not being used) to ensure that the value input to
such a pin can be read accurately. In the case when data is written to a pin configured as an input,
the data is written only to the port latch; the pin itself remains floating.
Most of the I/O Ports are multiplexed with secondary functions. When a GPIO is multiplexed with a
second function, the control signal from the peripheral overrides the direction register. The
multiplexing is briefly described below. The second function signals to and from the I/O ports are
described in detail in their respective block's description.

2.6.1.1

YO Ports

Ports 0 and 1
Ports 0 and 1 act as the address bus (ABo-ABJs) in Microprocessor and Memory Expansion modes.

Direction Register

Port Latch

Data Bus

Figure 2-18. Port PO, PI, P3, and P6 6 Block Diagram

Port 2
Port 2 acts as the data bus during microprocessor and memory expansion modes and also contains
key-on wake up circuitry (see Figure 2-19.).

Pull-up C....on_tr_o_l~--I

Direction Register

Data ..............._ ..

Port Latch

Key-on Wake-up Input

Figure 2-19. Port P2 Block Diagram

Input and Output Ports

Input and Output Ports-29

Mitsubishi

M37640E8-XXXF Preliminary Specification

J...

Port 3
Port 3 outputs the signals described in the pin description (Figure 1-2. Pin Description).
Port 4
See Figure 2-20., Figure 2-21., and Figure 2-22.
CPMB4
Direction Register

Data'LW~_~

Port Latch

EDMA Signal ) - - - - i

Figure 2-20. Port P40 Block Diagram

Direction Register

Data Bus

---+---.t

Port Latch

futerruptfuput~-<~

_ _ _ _ _~

Figure 2-21. Port P4 1 and P42 Block Diagram
Timer Counter fuput Enable
Pulse Output Mode Enable ')-_ _ _ _...,
Direction Register

Data B;;..u;;.;:s~_~

Port Latch

Timer X, Y Output

Counter fuput or ....--<::!t-_ _ _ _ _---'
Interru t Input

Figure 2-22. Port P43 and P44 Block Diagram

Input and Output Ports-30

Input and Output Ports

J...

Mitsubishi

M37640E8-XXXF Preliminary Specification

Tout Enable

Bit

Direction Register

Data Bus

~'-~

Port Latch

Timer \

Output
Figure 2-23. Port P4S Block Diagram

2.6.1.2

Power and Ground Pins

There are two Vss and two Vdd pins that supply power to the MCU. There are also one analog Vdd
(AVec) and one analog Vss (AVss) pins for the analog circuits.
2.6.1.3

CNVssPin

The level of the signal input to the CNVss pin at reset detennines whether the chip enters single chip
or microprocessor mode. With CNVss connected to Vdd, the MCU enters microprocessor mode after a
reset. After the reset sequence has been completed, the mode can be changed by modifying the value
of bits 0 and 1 of CPUMA. However, while CNVss is connected Vdd, bit 1 of CPUMA can not be
overwritten. With CNVss connected to Vss' the MCU enters single chip mode after a reset.
2.6.1.4

Xin and Xout Pins

The Xin and Xout pins are clock input and output pins. This device has a built-in clock generation
circuit whose oscillation frequency is set by a ceramic or a quartz oscillator. Also, an external clock
source can be used by connecting the Xin pin to a clock generator and leaving the Xout pin floating.
2.6.1.5

XCin and XCout Pins

The P5dXcin and P5\ffou!XCout pins are clock input and output pins. This device has a built-in clock
generation circuit whose oscillation frequency is set by a ceramic or quartz oscillator. An external clock
may also be used by connecting the XCin pin to a clock generator and leaving the XCout pin floating.
2.6.1.6

RESET Pin

The MCU is reset by holding RESET Low for at least 2JlS before returning to High.
2.6.1.7

RDYPin

For a detailed description of the P3dRDY pin see "2.4.5 Slow Memory Wait".
2.6.1.8

DMAoutPin

When the chip is in microprocessor or memory expansion mode, the DMAout (p3 3/DMAout) pin goes
High during a DMA access.

Input and Output Ports

Input and Output Ports-31

Mitsubishi

M37640E8-XXXF Preliminary Specification

2.6.1.9

J...

ct>out Pin

When the MCU is in microprocessor or memory expansion mode, pin P3 4 outputs the internal system
.clock ct>out~ When the STP or WIT instructions are executed, the output· of the ct>out pin stops at a
High level.
2.6.1.10

SYNCout PinC

When the MCn is in microprocessor or JIlemory expansion mode, the SYNCout .pin outputs a signal
that is High for one-half cycle of ct>out every time an OpCode is fetched.
2.6.1.11

RD and WR Pins

A read control signal is output from the RD pin and write control signal is output from the WR pin
(P36"WR and P3 71RD). A Low output from the RD pin indicates that the CPU is reading and a Low
output from the WR pin indicates that the CPU is writing.
2.6.1.12

LPF Pin

When the Frequency Synthesizer is active, the XouPF pin is the loop filter for the Frequency
Synthesizer.

2.6.2

Port Control Register

This device is equipped with a port control register to control multiplexing of several pins and to turn
on and off the slew rate control (SRC) (see Figure 2-24.).

~BI

Pre7

PTCO

Prel
PTC2

Pre3
Pre4
PreS

Pre6
PI'C7

Pre6

PI'C5

Pre4

Pre3

PTC2

Prel

Slew Rate Control Ports 0-3
O:Disabled
l:EnabIed
Slew Rate Control Port 4
O:Disabled
l:Enabled
Slew Rate Control Port S
O:Disabled
l:Enabled
Slew Rate Control Port 6
O:Disabled
l:Enabled
Slew Rate Control Port 7
O:Disabled
l:EnabIed
Slew Rate Control Port 8
O:Disabled
l:Enabled
Port 2 Input Level Select
o:rn.. level input
l:CMOS level input
Master Bus Input Level Select
O:CMOS level input
l:rn.. level input

Address: 0010 16

Access: RIW
Reset:

00 16

Figure 2·24. Port Control Register

Input and Output Ports·32

Input and Output Ports

J....

M37640E8-XXXF Preliminary Specification

Mitsubishi

2.6.3

Port P2 Pull-up Control Register

This device is equipped with internal pull-ups on Port P2 that can be enabled by software. Each bit of
that pull-up control register controls a corresponding pin of Port P2. The pull-up control register pulls
up the port when the port is in input mode. The value of the pull-up control register has no effect
when the port is in output mode.

PUP20

PUP21

PUP22

PUP23

PUP24

PUP2S
PUP26
PUP27

Pull-up Control
O:Disabled
l:Enabled
Pull-up Control
O:Disabled
l:Enabled
PulI-up Control
0: Disabled
l:Enabled
Pull-up Control
O:Disabled
l:Enabled
Pull-up Control
O:Disabled
l:Enabled
Pull-up Control
O:Disabled
l:Enabled
Pull-up Control
O:Disabled
l:Enabled
Pull-up Control
O:Disabled
l:Enabled

I~B

Address: 0012 16
Access: RIW

for Port 2. Bit 0

Reset:

0016

for Port 2. Bit 1

for Port 2, Bit 2

for Port 2, Bit 3

for Port 2. Bit 4

for Port 2. Bit 5
for Port 2, Bit 6
for Port 2, Bit 7

Figure 2-25. Pull-up Control Register

2.7

Interrupt Control Unit
Address

Description

Code

000216
0003 16

Interrupt request register A IREQA-OO
Interrupt request register B IREQB-OO

000416

Interrupt request register C IREQC-OO
Interrupt control register A ICONA-OO

0005 16

Address
000616

0007 16
0037 16

Code

Description
Interrupt control register B
Interrupt control register C

ICONB=OO
ICONC=-OO

Interrupt polarity selection register

IPOL=OO

The interrupt control unit (ICU), a specialized peripheral, is described in detail in this section.
This series supports a maximum of 23 maskable interrupts, one software interrupt, and one reset
vector that is treated as a non-maskable interrupt
See Table 2-4 for the interrupt sources, jump destination addresses, and interrupt priorities. For
example, User Reset has a jump destination storage address of FFFA and FFFB and a priority of 3.

Interrupt Control Unit

Interrupt Control Unit-33

Mitsubishi

M37640E8-XXXF Preliminary Specification

2.7.1

J...

Interrupt Control

Each maskable interrupt has associated with it an interrupt request bit and an interrupt enable bit.
These bits, along with the I flag, determine· whether interrupt events can cause an interrupt service
request to be generated. An interrupt request bit is set High when its corresponding interrupt event is
activated. The bit is cleared to a "0" when the interrupt is serviced or when a "0" is written to the
bit. The bit can not be set High by writing "I" to it.
Each interrupt enable bit determines whether the interrupt request bit it is paired with is seen when the
interrupts are polled. When the interrupt enable bit is Low, the interrupt request bit is not seen; and
when the enable bit is High, the interrupt request is seen.
The interrupt request register configurations for the 23 maskable interrupts are shown in Figure 2-26.,
Figure 2-27., and Figure 2-28. The interrupt control register configurations for the 23 maskable
interrupts are shown in Figure 2-29., Figure 2-30., and Figure 2-31. The configuration of the polarity
register for the external interrupts is shown in Figure 2-32.

¥SB

IRA6

IRA7

I
IRAO
IRA I
IRA2
IRA3
IRA4
IRA5

IRA6
IRA7

IRA I
IRA2
I
I
I
USB Function Interrupt Request Bit 0
USB SOF Interrupt Request· Bit I
Extemal Interrupt 0 Request Bit 2
Extemal Interrupt I Request Bit 3
DMAC channel 0 Interrupt Request Bit 4
DMAC channel I Interrupt Request Bit 5
UARTI Receive Buffer Full· Interrupt Request Bit 6
UARTI Transmit Interrupt Request Bit 7
No interrupt request issued
0:
I:
Interrupt request issued

IRA5

IRA4

IRA3

IRAO

I~SB

Address: 0002 16
Access: R/W
Reset: 0016

Figure 2-26. IREQA Configuration

~BI

IRB7

IRB6
IRBO
IRBI
IRB2
IRB3
IRB4
IRBS
IRB6
IRB7

IRB5

IRB4

IRB3

IRB2

IRBI

IRBO

I~B

UARTI Error Sum Interrupt Request Bit 0
UART2 Receive Buffer Full Interrupt Request Bit I
UART2 Transmit Interrupt Request Bit 2
UART2 Error Sum Interrupt Request Bit 3
TImer X Interrupt Request Bit 4
TImer Y Transmit Interrupt Request Bit 5
Tuner I Interrupt Request Bit 6
Tuner 2 Interrupt Request Bit 7
No interrupt request issued
0:
I:
Interrupt request issued

Address: 0003 16
Access: R/W
Reset: 00 16

Figure 2-27. IREQB Configuration

LSB
0

Bit 7

Tuner 3 Interrupt Request Bit ·0
External CNTRO Interrupt Request Bit I
External CNTRI Interrupt Request Bit 2
SIO Interrupt Request Bit 3
Input Buffer Full Interrupt Request Bit 4
Output Buffer Empty Request Bit 5
Key·on Wake-up Interrupt Request Bit 6
No interrupt request issued
0:
I:
Interrupt request issued
BRK Instruction - Reserved (0 when read)

Address: 000416
Access: R/W
Reset: 0016

Figure 2-28. IREQC Configuration

Interrupt Control Unit-34

Interrupt Control Unit

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

~SB I

ICA6

ICA7

ICAO
ICAI
ICA2
ICA3
ICA4
ICA5
ICA6
ICA7

ICA5

ICA4

ICA3

ICA2

ICAI

ICAO

I~B

USB Function Interrupt Request Bit 0
USB SOF Interrupt Request Bit I
External Interrupt 0 Enable Bit 2
External Interrupt I Enable Bit 3
DMAC channel 0 Interrupt Enable Bit 4
DMAC channel I Interrupt Enable Bit 5
UART! Receive Buffer Full Interrupt Enable Bit 6
UARTI Transmit Interrupt Enable Bit 7
0:
Interrupt Disable
I:
Interrupt Enable

Address: 0005 16
Access: RIW
Reset:
00 16

Figure 2-29. ICONA Configuration

~SBI

ICB7

ICB6
ICCO
ICCI
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7

ICB5

ICB4

ICB3

ICB2

ICBI

ICBO

I~B

UART! Error Sum Interrupt Enable Bit 0
UARTI Receive Buffer Full Interrupt Enable Bit I
UARTI Transmit Interrupt Enable Bit 2
UARTI Error Sum Interrupt Enable Bit 3
Tuner X Interrupt Enable Bit 4
TImer Y Interrupt Enable Bit 5
Tuner I Interrupt Enable Bit 6
TImer 2 Interrupt Enable Bit 7
0:
Interrupt Disable
I:
Interrupt Enable

Address: 0006 16
Access: RIW
Reset:
00 16

Figure 2-30. ICONB Configuration

~SB li{~~zl

ICC6

ICCO
ICC I
ICC2
ICC3
ICC4
ICC5
ICC6

Bit 7

ICC5

ICC4

ICC3

ICC2

ICC I

Address: 0007 16

ICCO

Access: RIW
Tuner 3 Interrupt Enable Bit 0
External CNTRO Interrupt Enable Bit 2
External CNTRI Interrupt Enable Bit 3
SIO Interrupt Enable Bit 4
Input Buffer Full Enable Bit 5
Output Buffer Empty Interrupt Enable Bit 6
Key-on Wake-up Interrupt Enable Bit 6
0:
Interrupt disabled
I:
Interrupt enabled
Reserved (Always write 0)

Reset:

00 16

Figure 2-31. ICONC Configuration

MSB
7

LSB
~~~~____~____~O

INTOPol

INTI Pol

Bits 2-7

INTO Interrupt Edge Selection Bit
0:
FaIling edge selected.
I:
Rising edge selected.
INTI Interrupt Edge Selection Bit
0:
FaIling edge selected.
I:
Rising edge selected.
Reserved (0 when read)

Address: 0011 16
Access: RIW
Reset:
00 16

Figure 2-32. IPOL Configuration

Interrupt Control Unit

Interrupt Control Unit-35

Mitsubisbi

M37640E8-XXXF Preliminary Specification

J....

Table 2-4 Interrupt Vector Table

2.7.2

Jump Destination Storage
Address (Vector Address)

Remarks

Priority

Interrupt

RSRVI

FFFF

FFFE

RSRV2

FFFD

FFFC

Reserved for factory use
.- User·Reset (Non-Maskable)

Higb-order
Byte

Low-order
.Byte

Reset

FFFB

FFFA

USB

FFF9

FFF8

Reserved for factory use

USB Function Interrupt

LSB

SOF

FFF7

FFF6

USB SOF Interrupt

INTO

FFF5

FFF4

External Interrupt 0

INTl

FFF3

FFF2

External Interrupt 1

DMAI

FFFI

FFFO

DMAC Channel 0 Interrupt

DMA2

FFEF

FFEE

DMAC Channel lInterrupt

UlRBF

FFED

FFEC

UARTl Receiver Buffer Full

UlTX

FFEB

FFEA

UARTl Transmit Interrupt

MSB

UIES

FFE9

FFE8

UARTl Error Sum Interrupt

LSB

U2RBF

FFE7

FFE6

UART2 Receiver Buffer Full

U2TX

FFE5

FFE4

UART2 Transmit Interrupt

U2ES

FFE3

FFE2

UART2 Error Sum Interrupt

FFEI

FFEO

TlIDerX

tIl

I:)

[

(")

(")
0

'"g

(JQ

tIl

I:)

::d

c§.
'"ff
...

6- >
'"

I»

FFDF

FFDE

TImerY

FFDD

FFDC

TlIDer I

(")

0
Z

FFDB

FFDA

Timer 2

MSB

FFD9

FFD8

TlIDer3

LSB

CNTRO

FFD7

FFD6

External CNTRO Interrupt

CNTRI

FFD5

FFD4

External CNTRI Interrupt

SID

FFD3

FFD2

SID Interrupt

IBF

FFDI

FFDO

Input Buffer Full Interrupt

OBE

FFDF

FFCE

Output Buffer Empty Interrupt

KEY

FFCD

FFCC

.Key-on Wake Up

BRK

FFCB

FFCA

BRK Instruction (Non-Maskable)

(")

0
Z

(")

MSB

Interrupt Sequence and Timing

The interrupts are polled prior to the beginning of each instruction. An interrupt service request is
generated when an interrupt event has its interrupt request bit set High, its interrupt enable bit is set
High, and the interrupt inhibit flag I is set Low. The I flag is used to disable all maskable interrupts.
When this bit is set High, only a BRK instruction or a user Reset can cause an interrupt service
request to be generated. Figure 2-33. is a simplified version of the logic that controls whether an
interrupt service request is generated.

Interrupt Control Unit-36

Interrupt Control Unit

J..

M37640E8-XXXF Preliminary Specification

Mitsubishi

Interrupt Request Bit
Interrupt Enable Bit

Interrupt Inhibit Flat I

Figure 2-33. Interrupt Service Request Control Logic

The time elapsed from the occurrence of an interrupt event until execution of its service routine varies
from 7 cycles to 23 cycles, depending on what instruction is executing when the interrupt event occurs
(see Figure 2-34.)
Interrupt R~uest
23 to 7 Cycles (2.3 ~ to 0.7 ~, when f(ll» - 10 MHz)

ICurrent

Instruc~c::::>tL..-_ _""

Maximum 16 cycles •
Minimum 0 cycles

2 cycles,
dummy cycles
for pipeline
postprocessing

5 cycles,
stack push
and
vector fetch

• For ON Instruction

Figure 2-34. Execution Time Prior to Interrupt Service Routine

When an interrupt service request occurs, the current instruction stream is temporarily halted and the
appropriate interrupt service routine is executed. Mter the interrupt service routine ends, the current
instruction stream is resumed with the next instruction.
The interrupt service request causes the MCU to automatically push the high-order byte of the program
counter, the low-order byte of the program counter, and the contents of the processor status register
onto the stack. A push consists of storing data at the stack address and decrements the stack pointer
by one. The I flag is set High to prevent other interrupts from being serviced during the interrupt
service routine, and the request bit corresponding to the interrupting event is automatically cleared to
"0". The program counter is set to the address specified in the vector table for the interrupt being
serviced. This address contains the address for the fIrst instruction of the interrupt service routine. The
timing for the pushing of data onto the stack, and fetching the starting address of the interrupt routine
is illustrated in Figure 2-35.

SYNCom:~

__________________________________________

~r-l

Address
Data

Figure 2-35. Interrupt Cycle Tuning

Interrupt Control Unit

Interrupt Control Unit-37

M37640E8-XXXF Preliminary Specification

Mitsubishi

See Figure 2-36. for the stack and program counter modifications that occur when an interrupt request
is serviced.

Program Counter
PCL

Program Counter (L)

PCH

Program Counter (H)

Stock (m 'Zrffo/Ooo Page) I

( Interrupt Enable )

(8;

Stack Pointer

(S)

Program Counter
PCL
PCH
S

Loaded values of the vector
address corresponding to
the accepted interrupt.

( Interrupt Disable)
(S)

Stack Pointer
(S) - 3

Figure 2-36. Stack Pointer and Program Counter Modifications During Interrupt Service Sequence

Returning from an interrupt is accomplished by executing an RTI instruction. This causes the MCU to
pop the contents of the process status register and the low-order and high-order bytes of the program
counter from the stack. The I flag, is cleared to "0" when the process status value is restored ftom the
stack.

2.8

Direct Memory Access Controller
Address
003F16
004016

0041 16
0042 16
0043 16
004416
0045 16
0046 16
0047 16

Description
DMAC index and status register
DMAC channel x mode register 1
DMAC channel x mode register 2
DMAC channel x source register Low
DMAC channel x source register High
DMAC channel x destination register Low
DMAC channel x destination register High
DMAC channel x transfer count register Low
DMAC channel x transfer count register High

Acronym
and Value
DMAIS==OO
DMAxMl=OO
DMAyM2=OO
DMAxSL-OO
DMAxSH-<>O
DMAxDL-OO
DMAxDH- channell)
• Two cycles of cI> required per byte transferred
Each channel of the DMAC is made up of the following:
• 16-bit source and destination registers
• A 16-bit transfer count register
• Two mode registers
• Status flags contained in a status register shared by the two channels
• Control and timing logic
The 16-bit source and destination registers allow accesses to any two locations in the 64K byte
memory area. The 16-bit transfer count register decrements by one for each transfer performed and
causes an interrupt and flag to be set when it underflows. The mode registers control the configuration
and operation of the DMAC channel associated with the registers. A block diagram of the DMAC is
shown in Figure 2-37.
The SFR addresses for the two mode, source, destination, and transfer count registers of a channel are
the same for each channel. Which channel's registers are accessible is determined by the value of the
DMAC Channel Index Bit (DCI) (bit 7 of the DMAC Index and Status Register (DMAIS)). When
this bit is a "0", channel 0 registers are accessible, and when this bit is a one, channel 1 registers are
accessible. The configuration of DMAIS and the mode registers are shown in Figure 2-38., Figure 239., Figure 2-40., and Figure 2-41.

Direct Memory Access Controller

Direct Memory Access Controller-39

Mitsubishi

M37640ES-XXXF Preliminary Specification

J....

DMAC Channel 0

DMAC Channel I

Figure 2-37. DMAC Block Diagram

2.S.1

Operation

Each channel of the DMAC transfers byte data from a source address to a destination address when a
selected event occurs. If single-byte transfer mode is enabled, one byte of data is transferred per
request. If burst transfer mode is enabled, several bytes can be transferred per request, one byte at a
time. A temporary register internal to the DMAC stores the data read from the source address until it
is written to the destination address on the next cycle. The transfer of one byte takes two cycles of . Writing a "1" to the DMAC Channel x Transfer Initiation Source Capture Register
Reset bit (DxCRR) causes the initiating source sample latch of the associated DMAC channel to be
reset. The sample latch is reset automatically one cycle of PHI after a transfer request is detected. New
transfer requests for a channel that occur during a DMAC transfer by that same channel are latched
as long as they occur after the sample latch is reset. However, if multiple transfer requests occur
during a transfer, only one transfer request will be registered.
If an interrupt is chosen as the initiating source for DMAC transfers, its interrupt control bit located in
one of the three interrupt control registers of the ICU should be cleared to "0" if the user does not
wish to have the interrupt serviced by the CPU.

Direct Memory Access Controller

Direct Memory Access Controller-41

Mitsubisbi

M37640E8-XXXF Preliminary Specification

2.8.1.3

J,..

Transfer Features for USB and Master CPU Bus Interface

In order to make the transfer of data between the USB endpoint FIFOs and the input and output
buffers of the Master CPU Bus Interface more efficient, special features have been included in the
transfer requestlogic of each DMACchannel. ~e.se features are enabled for a channel when one of
the USB endpoint signals is selected as the hardware transfer request source and the DMAC Channel x
USB" and Master CPU Bus Interface Enable Bit (DxUMIE) is set High. These features are only
intended to be used with single-byte transfer mode.
USB OUT FIFO to Master CPU Bus Interface Output Buffer Transfers
When a USB endpoint packet received signal is selected as the hardware transfer request source for
a .DMAC channel and the DxUMIE bit of the same channel is set High, a transfer request is
generated for that DMAC channel when the packet received signal for the chosen USB endpoint is
active and output buffer x (where x is "0" for DMAC channel 0 and "1" for DMAC channell) of
the Master CPU Bus Interface is empty. The packet received signal remains active until all bytes of
the packet have been read from the FIFO corresponding to that endpoint. Thus, the first transfer
request is generated when the packet received signal goes active and subsequent transfer requests are
generated each time output buffer x becomes empty. Once the fmal byte of the received packet has
been' read, the packet received signal automatically goes inactive (if this option is enabled in the
USB block). This in turn causes the source,' destination, and transfer count registers of the involved
DMAC channel to be reloaded (unless the DRLDD bit is set High) and the DMAC interrupt for the
involved channel to be set. In addition, if the DxDAUE bit associated with the channel is "I", the
channel's DxCEN bit is automatically cleared to "0", disabling the channel.
This feature allows a channel of the DMAC in single-byte transfer mode to automatically transfer a
received packet of an endpoint from the endpoint's FIFO to the master CPU (via the Master CPU
Bus Interface) without any intervention by the on-chip CPU. Also, because the source, destination,
and transfer count registers are automatically reloaded once the current packet has been completely
transferred, on-chip CPU intervention is not needed to set up the DMAC channel for transfer of
subsequently received packets, even in the case of reception of a short packet.
A second method for generating DMAC transfer requests based on a signal from USB endpoint 1
and the status of output buffer x of the Master CPU Bus Interface is supported. This method
facilitates byte-by-byte transfers; whereas, the method described above facilitates packet-by-packet
transfers. This method is enabled when the USB endpoint 1 OUT FIFO not empty signal is chosen
as the hardware transfer request source for a DMAC channel and the DxUMIE bit of the same
channel is set High. A transfer request is generated for the DMAC channel if the endpoint 1 FIFO
is not empty and output buffer x of the Master CPU Bus Interface is empty. As is the case when
the packet-by-packet method is used, the packet received signal goes active once a complete packet
has been received. It remains active until all bytes of the packet have been read from the FIFO.
When the fmal byte has been read from the FIFO, the packet received signal goes inactive (if this
option is enabled in the USB block), which causes the source, destination, and transfer count
registers of the involved DMAC channel to be reloaded (unless the DRLDD bit is set High) and the
DMAC interrupt corresponding to the involved channel to be set. Also, if the DxDAUE bit
associated with the channel is "I", the channel's DxCEN bit is automatically cleared to "0",
disabling the channel. If the last byte of the packet has been read from the FIFO before the
end_oCpacket signal is received by the USB block, the packet received signal will still go to its
active state and then go inactive a short period of time later (if this option is enabled in the USB
block).

Direct Memory Access ControUer42

Direct Memory Access Controller

Mitsubishi

M37640E8-XXXF Preliminary Specification

Master CPU Bus Interface Input Buffer to USB IN FIFO Transfers
When a USB endpoint packet sent signal is selected as the hardware transfer request source for a
DMAC channel and the DxUMIE bit of the same channel is set High, a transfer request is generated
when the FIFO associated with the endpoint is not full (with respect to the programmed packet size)
and input buffer x of the Master CPU Bus Interface contains data. The transfer request is not
generated if input buffer x contains a command. The FIFO not full signal of the endpoint remains
active until a full packet has been written to the FIFO. Thus, the first transfer request is generated
when the FIFO not full signal goes active and subsequent transfer requests are generated when data
is written to input buffer x by an external device. Once the full packet has been written to the
FIFO, the FIFO not full signal goes inactive and the in_packeCready signal of the endpoint is
automatically set (if this option is enabled in the USB block). In this case, the .source, destination,
and transfer count registers are not automatically reloaded. Instead, the packet size for the endpoint
should be written to the transfer count register at initialization time so that it underflows and reloads
once the last byte of the data is transferred from input buffer x to the endpoint's FIFO.
The feature described above allows a channel of the DMAC in single-byte transfer mode to
automatically transfer data received from the master CPU (via the Master CPU Bus Interface) to the
endpoint's FIFO without any intervention by the on-chip CPU. Additionally, since the
in_packecready signal associated with the endpoint is automatically set (if this option is enabled in
the USB block), multiple packets can be transferred by a channel of the DMAC without on-chip
CPU intervention. Note however that short packets are not handled automatically and instead require
intervention by the on-chip CPU.
2.8.1.4

DMAC Transfer Mode

Each channel of the DMAC can be operated in single-byte transfer mode or burst transfer mode. The
choice is made by the setting of the Channel x DMAC Transfer Mode Selection Bit (DxTMS). When
single-byte transfer mode is selected, one byte of data is transferred per transfer request. When burst
transfer mode is selected, the value in the transfer count register determines how many single byte
transfers occur per transfer request. For example, if the value in the transfer count register is 0014 16,
21 transfers will occur before control of the address bus and data bus is given back to the CPU.
2.8.1.5

DMAC Transfer Timing

A DMAC transfer can occur at any point during the execution of an instruction by the CPU. However, at
least one cycle of OU!
SYNCOU!:

RD.
WR.

Address
Data

DMAC Transfer:
Signal (Port3 3)

.r-------------------------'

Transfer Request:
Source (active low).
Transfer Request
Source Sampling.
Transfer Request:

,.....------------.,

SourceSample.~------------------------------------~

Latch Reset·

Figure 2-43. DMAC Transfer - Software Trigger Initiated

_______________

~r-l~

.
.

____________________________________________________________

'
RD'

WR •

LOA $zz
STA $zz
OMAC Transfer
STA $zz (second 4cle)
r -______~~,______~~(~fm~~~~c1-e)~r------~~~-------~--~

Address'
Data

'---"

DMAC
Transfer'
Signal (Port3 ) .'_ _ _ _ _ _ _ _ _ _ _ _ _ _- '
3

Transfer Request
Source (active low)
Transfer Request
Source Sampling
Transfer Request
Source Sample
Latch Reset

:
•
•
:
....-----------------------'
Figure 2-44. DMAC Transfer - Burst Transfer Mode

Direct Memory Access Controller

Direct Memory Access Controller-47

Mitsubishi

M37640ES-XXXF Preliminary Specification

2.9

J...

Timers
Address

Acronym and
Value at Reset

Description

Address

Description

Acronym and
Value at Reset

0025 16

Tuner 2

T2-o1

TimerXH

TXL=FF
- TXH-FF

·00261'6'

Tuner 3

TunerYL

TYL-FF

002716

Tuner X mode register

T3-FF
TXM-DO

TunerYH

TYH-FF

0028 16

Tuner Y mode register

TYM-DO

Tuner 1

Tl-FF

0029 16

Tuner 123 mode register T123M-OO

0020 16

Tuner XL

0021 16
0022 16
0023 16
002416

This device has five built-in timers: Timer X, Timer Y, Timer 1, Timer 2, and Timer 3.
The contents of the timer latch, corresponding to each timer, determine the divide ratio. The timers can
be read or written at any time. However, the read and write operations on the high and low-order
bytes of the 16-bit timers (Timer X and Y) must be performed in a specific order.
The timers are all down count timers; when the count of a timer reaches 00 16 (0000 16 for Timer X
and Y), an underflow occurs at the next count pulse and the contents of the corresponding timer reload
latch are reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to
that timer is set High.
The divide ratio of a timer is given by l/(n + 1), where n is the value written to the timer. When the
STP instruction is executed, 01 16 is loaded into Timer 2 and the Timer 2 reload latch, and FF 16 is
loaded into Timer 1 and the Timer 1 reload latch.
Figure 2-48. is a block diagram of the five timers.

Timer X

2.9.1

Timer X is a 16-bit timer that has a 16-bit reload latch, and can be placed in one of four modes by
setting bits TXM4 and TXM5 (bits 4 and 5 of the Mode Register, TXM). The bit assignment of the
TXM is shown in Figure 2-45 ..

2.9.1.1

BitS-TXM5

Bit4-TXM4

Timer X Mode
Tuner mode

Pulse output mode

Event counter mode

Pulse width measurement mode

Read and Write Method

Read and write operations on the high and low-order bytes of Timer X must be performed in a
specific order.

Write Method
When writing to the timer, the lower order byte is written first. This data is placed in a temporary register
that is assigned the same address as Timer XL. Next, the higher order byte is written. When this is done,
the data is placed in the Timer XH reload la~h and the low-order byte is transferred from its temporary
register to the Timer XL reload latch. At this point, if the Timer X Data Write Control Bit (TXMO) (bit 0)
is "0", the value in the Timer X reload latch is also loaded in Timer X. If TXMO is "1", the data in the
Timer X reload latch is loaded in Timer X after Timer X underflows.

Timers-48

Timers

J..

M37640E8-XXXF Preliminary Specification

Mitsubishi

~SB

TXM7

TXM6

TXM5

TXMO

TXM2,1

TXM3

TXM5,4

TXM6

TXM7

TXM4

TXM3

TXM2

TXMI

TXMO

Tuner X Data Write Control Bit • Bit 0
O:Write data in latch and timer
I:Write data in latch only
Tuner X Frequency Division Ratio Bits • Bits 2 and 1
00:«11 divided by 8
01:«11 divided by 16
10:«11 divided by 32
11:«11 divided by 64
TJlller X Internal Clock Select Bit Bit 3
O:CIICII/n
I:SCSGCLK (from chip special count source generator)
Tuner X Mode Bits • Bit 5 and 4
OO:Tuner Mode
OI:Pulse output mode
lO:Event counter mode
Il:Pulse width measurement mode
CNTRO Polarity Select Bit • Bit 6
O:For event counter mode, clocked by rising edge
For pulse output mode, start from High level output
For CNTRO interrupt request, falling edge active
For pulse width measurement mode, measure High period
1:For event counter mode, clocked on falling edge
For pulse output mode, start from Low level output
For CNTRO interrupt request, rising edge active
For pulse width measurement mode, measure Low period
Tuner X Stop Bit • Bit 7
O:Count start
l:Count stop

I~B

Address: 0027 16
Access: RIW
Reset:
00 16

Figure 2-45. TXM Register

Read Method
When reading Timer X, the high-order byte is read fIrst. Reading the high-order byte causes the values of
Timer XH and Timer XL to be placed in temporary registers assigned the same addresses as Timer XH and
Timer XL. The low-order byte of Timer X is then read from its temporary register. This operation assures
the correct reading of Timer X while it is counting.
2.9.1.2

Count Stop Control
-\

If the Timer X Count Stop Bit (TXM7) (bit 7 of the TXM) is set High, Timer X stops counting in all
four modes.

2.9.1.3

Timer Mode

Count Source:

4>ln (where n is 8, 16, 32, or 64) or SCSGCLK

In this mode, each time the timer underflows, the corresponding timer interrupt request bit is set High,
the contents of the timer latch are loaded into the timer, and the count down sequence begins again.

2.9.1.4

Pulse Output Mode

Count Source:

4>ln (where n is 8, 16, 32, or 64) or SCSGCLK

Each time the timer X underflows, the output of the CNTRO pin is inverted, and the corresponding
Timer X interrupt request bit is set High. The repeated inversion of the CNTRO pin output produces a
rectangular waveform with a duty ratio of 50 percent. The initial level of the output is determined by
the CNTRO polarity select bit (bit 6). When this bit is Low, the output starts from a High level. When
this bit is High, the output starts from a Low level.

Timers

Timers49

M37640E8-XXXF Preliminary Specification

2.9.1.5

Mitsubishi

J...

Event Counter Mode

Count Source:

CNTRO

Timer countdown is triggered by inputs to the CNTRO pin. Each time. a timer underflows, the
corresponding timer interrupt request bit is set High,the contents of the timer reload latch. are loaded
into the timer, and the countdown sequence begins again ..
The edge used to clock Timer X is determined by the CNTRO polarity select bit (bit 6).

2.9.1.6

Pulse Width Measurement Mode

Count Source:

4>ln (where n is 8, 16, 32, or 64) or SCSGCLK

This mode measures either the high or low-pulse width of the signal on the CNTRO pin. The pulse
width measured is determined by the CNTRO polarity select bit (bit 6). When this bit is "0", the High
pulse is measured. When this bit is "1 ", the Low pulse is measured.
The timer counts down while the level on the CNTRO pin is the polarity selected by the CNTRO
polarity select bit. When the timer underflows, the Timer X interrupt request bit is set High, the
contents of the timer reload latch are reloaded into the timer, and the timer continues counting down.
Each time the signal polarity. switches to the inactive state, a. CNTRO interrupt occurs indicating that
the pulse width has been measured. The width of the measured pulse can be found by reading Timer
X during the CNTRO interrupt service routine.

2.9.2

Timer Y

Timer Y is a 16-bit timer that has a 16-bit reload latch, and can be placed in any of four modes by
setting TYM4 and TYMS (bits 4 and 5) (see Figure 2-46.). The desired mode is selected by modifying
the values of TYM4 and TYM5.

Timers-SO

BitS-TYMS

Bit4-TYM4

0
0
1
1

0
1
0
1

TImerYMode
TImer mode
Pulse period measurement mode
Event counter mode
In. Pulse width measurement mode

Timers

J....

M37640E8-XXXF Preliminary Specification

Mitsubishi

MSB
7

TYM7

TYM6
TYMO

TYMI

TYM3.2

TYM5.4

TYM6

TYM7

TYM5

TYM4

TYM3

TYM2

TYMI

TYMO

I~B

Address: 0028 16
Access: RIW

Tnner Y Data Write Control Bit - Bit 0
Reset:
00 16
O:Write data in latch and timer
I:Write data in latch only
Tnner Y Output Control Bit - Bit I
O:TYOUT output disable
I:TYOUT output enable
Tnner Y Frequency Division Ratio Bits - Bit 3 and 2
00:<11 divided by 8
01:<11 divided by 16
10:<11 divided by 32
ll: divided by 8
I:XCin divided by 2
Timer 2 Count Source Select Bit - Bit 3
0: TIMer I underflow signal
1:4>
TIMer 3 Count Source Select Bit - Bit 4
O:Tuner I underflow signal
1:4> divided by 8
TOUT Output Active Edge Selection Bit - Bit 5
0: Start on High output
I: Start on Low output
TOUT Output Control Bit - Bit 6
O:TOUT output disabled
I:TOUT output enabled
Tuner I and 2 Data Write Control Bit - Bit 7
O:Write data in latch and timer
I:Write data in latch only

Address: 0029 16
Access: R!W
Reset:

00 16

Figure 2-47. T123M Register

Timer 1 is an 8-bit timer with an 8-bit reload latch and has a pulse output option.
T123M7 of TimerI23 mode register (TI23M) is the Timer 1 and 2 Data Write Control Bit If T123M7
is "1 ", data written to Timer 1 is placed only in the Timer 1 reload latch. The latch value is loaded
into Timer 1 after Timer 1 underflows. If T123M7 is "0", the value written to Timer 1 is placed in
Timer 1 and the Timer 1 reload latch. At reset, T123M7 is set Low.
The output signal TOUT is controlled by T123M5 and T123M6. TI23M5 controls the polarity of
TOUT. Setting the bit T123M5 to "1" causes TOUT to start at a Low level, and clearing this bit to
"0" causes TOUT to start at a High level. Settfug T123M6 to "1" enables TOUT, and clearing
TI23M6 to "0" disables TOUT.
2.9.3.1

Timer Mode

Count Source:

<1>18 or XCin/2

In Tuner mode, each time the timer underflows, the corresponding timer interrupt request bit is set High,
the contents of the timer latch are loaded into the timer, and the count down sequence begins again.

2.9.3.2

Pulse Output Mode

Count Source:

<1>18 or XCin/2

Timer 1 Pulse Output mode is enabled by setting T123M6 to "1" and TI23MO to a "0". Each time the
Timer 1 underflows, the output of the TOUT pin is inverted, and the corresponding Timer 1 interrupt
request bit is set High_ The repeated inversion of the TOUT pin output produces a rectangular
waveform with a duty ratio of 50 percent The initial level of the output is determined by the TOUT
polarity select bit (TI23M5). When this bit is Low, the output starts from a High level. When this bit
is High, the output starts from a Low leveL

2.9.4

Timer 2

Timer 2 is an 8-bit timer with an 8-bit reload latch_

Timers

Timers-53

Mitsubisbi

M37640E8-XXXF Preliminary Specification

T123M7 (bit 7 of T123M) is the Timer 1 and 2 Data Write Control Bit. If T123M7 is "I", data
written to Timer 2 is placed only in the Timer 2 reload latch (see Figure 2-50). The latch value is
loaded into Timer 2 after Timer 2 underflows. If the T123M7 is ''0'', the value written to Timer 2 is
placed in Ti~er 2 and the Timer 2 reload latch. At reset, T123M2 is set Low.
The Timer 2 reload latch value is ·not affected by a change of the count source. However, because
changing the count source may cause an inadvertent countdown or' the timer, the timer should be
rewritten when the count source is changed.

2.9.4.1

Timer Mode

Count Source:

If T123M3 is "0", the Timer 2 count source is the Timer 1 underflow output.
If T123M3 is

1 It, the Timer 2 count source is 4>.

In Timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set High,
the contents of the timer latch are loaded into the timer, and the count down sequence begins again.

2.9.4.2

Pulse Output Mode

Count Source:

If T123M3 is "0", the Timer 2 count source is the Timer 1 underflow output.
If T123M3 is "I", the Timer 2 cOunt source is 4>.

Timer 2 Pulse Output mode is enabled by setting TI23M6 to a "1" and T123MO to a "1". Each time
the Timer 2 underflows, the output of the TOUT pin is inverted, and the corresponding Timer 2
interrupt request bit is set High. The repeated inversion of. the TOUT pin output produces a rectangular
waveform with a duty ratio of 50 percent. The initial level of the output is determined by the TOUT
polarity select bit (TI23M5). When this bit is ''0'', the output starts from a High level. When this bit
is "1", the output starts from a Low level.

2.9.5

Timer 3

Timer 3 is an 8-bit timer with an 8-bit reload latch. The Timer 3 reload latch value is not affected by
a change of the count source. Because changing the count source may cause an inadvertent countdown
of the timer, the timer should be rewritten whenever the count source is changed.

2.9.5.1

Timer Mode

Count Source:

If TI23M4 is

''0'', the Timer 3 count source

is the Timer 1 underflow output.

If T123M4 is "I", the count source is 4>18 .
In Timer mode, each time the timer underflows. the corresponding timer interrupt request bit is set
High, the contents of the timer latch are loaded into the timer, and the count down sequence begins

again.
Data written to Timer 3 is always placed in Timer 3 and the Timer 3 reload latch.

Timers-54

Timers

J..

M37640E8-XXXF Preliminary Specification

Mitsubishi

SCSGCLK

O~------,

TXMO

TImer X Interrupt Request

CNTRO

CNTRO Interrupt Request

TXM5,4-01
TXM6

TXM5,4-01

TYMO
TYMS,4
00

TYM7 r;:;::-::-v;--:-::=~=::>:m;c-::::=~

Tuner Y Interrupt Request
11

TYMl- one and TYM5,4 - ero

TYM5,4
00

CNTR 1 Interrupt Request

TYM- one & TYMS, 4 - 00
Tl23M7
Tuner 2
Interrupt Request

XCmf2

Tuner 1
Interrupt Request

Tuner 3
Interrupt Request

Tl23M6-on

Figure 2-48. Block Diagram of Timers X, Y, 1, 2, and 3

Timers

Timers-55

Mitsubisbi

M37640E8-XXXF Preliminary Specification

J...

2.10 Universal Serial Bus
Address

Acronym and
Value

Description

005016
0051 16

USB Address Register

USBA=OO
USB Power Management Register· USBPM=OO

005B 16
005C I6

0052 16

USB Interrupt Status Register 1

USBIS1=OO

005D16

0053 16

USB Interrupt Status Register 2

USBIS2- half of the FIFO size), the IN_PKT_RDY is cleared upon successful transmission of the
data packet. In the case where the FIFO is configured to hold two data sets (MAXP <= half of the
FIFO size), every time there is one or two data sets available, the IN_PKT_RDY is cleared. In the
later case, in order to determine if a data packet has been transmitted out, a read only bit,
TX_NOT_EMPTY is available. The status of a TX FIFO status could be obtained by:
IN PKT RDY

TX NOT EMPTY

No data packet in TX FIFO

One data packet in TX FIFO

Invalid

Two data packets in TX FIFO

TX FIFO Status

For isochronous data transfer, an additional bit, named ISO_UPDATE is provided. The function of this
bit is described below:
If ISO_UPDATE = "0", whenever the IN_PKT_RDY is set, it is sent to the Serial Interface Engine
(SIE) immediately, available for the next IN_TOKEN from the host; if ISO_UPDATE = "I" and ISO
bit of the corresponding endpoint's IN CSR is set, then the IN_PKT_RDY bit is delayed until the
next SOF before being sent to the SIE. In this way the IN_PKT_RDY is synchronized with the SOF.
The ISO_UPDATE bit is a global bit for endpoints 1 to 4, and works with isochronous pipe only.
Endpoints 2 to 4 (IN direction) can be used for interrupt transfer. This is done by setting the INTPT
bit in the IN CSR register of the corresponding endpoint. The CPU sets this bit to initialize that
endpoint as a status change endpoint, meaning that whenever the USB GFI receives an IN token
addressed to that endpoint, the GFI will unconditionally transmit out the most recent updated data
packet in the TX FIFO which the size is equal to the MAXP set for that endpoint. In order to avoid
transmitting some unwanted data to the host while the CPU is in initialization stage, the following
setup sequence is recommended:

Universal Serial Bus

Universal Serial Bus-59

M37640E8-XXXF Preliminary Specification

Mitsubishi

J...

1. SetMAXP;
2. Load interrupt status information with the number of bytes equal to MAXP to that endpoint's FIFO;
3. Set IN_PKT_RDY and INTPT bits of the IN CSR;
4. Load the FIFO wi.th the number of bytes equal to MAXP for all· the subsequent interrupt status updates.
Because all endpoints start up default to be bulk transfer, before Step 3 listed above is done,
the OF! will send NAK to every IN token the host addresses to this endpoint, therefore
unwanted data will not be transmitted out to the host.
The USB function control unit handles all the bad transmission retry and data set management tasks.

2.10.3.2

Receive FIFOs

The USB OF! writes data to the endpoint's receive FIFO location specified by the write pointer, which
automatically increments by one after a write. When a good reception is complete, the OF! sets the
OUT_PKT_RDY bit in the corresponding Endpoint OUT Control and Status Register (OUT CSR),
signaling the CPU that it has successfully received a data packet. This bit is cleared upon unloading
the packet from the FIFO. Clearing the OUT_PKT_RDY bit can be done in two ways. If bit 7 of the
OUT_CSR is a "0", OUT_PKT_RDY is cleared by the CPU writing a ''0'' to that bit. If bit 7 of the
. OUT_CSR is a "1", OUT_PKT_RDY is automatically cleared by the OF! when the number of bytes of
data equal to the value of the Write_Count register (WRT_CNT) is unloaded from the FIFO. In the
case where the FIFO is configured to hold two data sets, every time there is one or two data sets
available, the OUT_PKT_RDY bit is set.
The USB function control unit handles all the write pointer reversal for a bad reception and data set
management tasks.
For endpoint I, when transferring ISO data, the receive FIFO can be unloaded as soon as there is
some data in the FIFO, which is indicated by DATA_NOT_EMPTY signal. The completion of
unloading a packet of data is signified by OUT_PKT_RDY - one, and DATA_SET_NOT_EMPTYzero. This feature is available only in DMA transfer mode, and is tightly coupled with the DMA
controller, see the DMA section for detail.

2.10.4 USB Special Function Registers
This device controls the USB operation through the use of special function registers (SFR). This
section describes in detail each USB related SFR. Certain USB SFRs are endpoint-indexed. Those are
the Control & Status Registers (IN CSR and OUT CSR), the Maximum Packet Size Registers (IN
MAXP and OUT MAXP) and the Write Count Registers (OUT WRT_CNT). To access each of the
endpoint-indexed SFR, the target endpoint number should be written to the Endpoint Index Register
first. The lower 3 bits (EPINDEX2:0) of the Endpoint Index Register are used for endpoint selection.

Note:

Each endpoint's FIFO Register is NOT endpoint-indexed.

Universal Serial Bus-60

Universal Serial Bus

Mitsubishi

M37640E8-XXXF Preliminary Specification

~B Address: 0013 16

MSB
7

Reset:
Bit

Name

3:0

Description

00 16

CPU
R

Reserved, write "0" to these bits.

USBC4

USB Line Driver Supply Select
0: Pin tn2 is the USB line driver power supply pin. This should connect
to a 3.3V supply.
I: Pin tn2 is the USB line driver external capacitor pin. This should
connect to a I pi or larger capacitor between pin #12 and V 55 for 5V
only power supply applications.

USBCS

USB Clock Enable
0: 48 MHz clock to the USB block is disabled.
I: 48 MHz clock to the USB block is enabled.

W/R

USBC6

USB SOF Port Select
0: USB SOF output is disabled. P70 is used as GPIO pin.
I: USB SOF output is enabled.

W/R

USBC7

USB Enable
0: USB block is disabled, all USB internal registers are held at their
default values.
1: USB block is enabled

W/R

Figure 2-50. USB Control Register

Address: 0050 16

LSB

MSB
7

_ _ _ _ _ _ _ _~_ _ _ _ _ _~_ _ _ _ _ _ _ _~_ _ _ _ _ __ L_ _ _ _ _ _~~_ _ _ _ _ _~_ _ _ _ _ _~O

BIt

Name

6:0

FUN_ADDR6:0

DescrIption

00 16

CPU

7-bit programmable Function Address

Reset:

W/R

Reserved, write a "0" to this bit

Figure 2-51. Function Address Register

The ·Function Address register maintains the USB address assigned by the host. The function control
unit uses this register value to decode USB token packet address. At reset, the device is not yet
configured, the value is 00 16,
Address: 0051 16
MSB
7

ijSB Reset:
Bit

Name

SUSPEND

R..RESUME

Description

CPU

When the functioo control unit receives suspend signaling, it sets this bit and suspends its clocks. This
also generates an interrupt. Upoo seeing this bit set, the CPU can save its internal register and then
enter suspend mode, independent of the ftmction control unit The CPU clears this bit when any of the
resume bit is set

W/R

When the function control unit is in suspend mode and receives resume signaling, its clocks are
enabled. and this bit is set, An interrupt is also generated when this bit is set. Upoo seeing this bit set,
the CPU can start its wake up sequence. The CPU should clear this bit after the wake up sequence is

00 16

W/R

done.
2

S_RESUME

7:3

When the CPU is waken up (by peripheral or timer), it starts its wake up sequence and set this bit
While this bit is set, and the function control unit was in suspend mode, it will generate resume signal
to the host. The CPU should keep this bit set for a minimum of lOms and a maximum of ISms.

Reserved, write "0" to these bits

W/R

Figure 2-52. Power Management Register

The Power Management register is used for power management in the function control unit.

Universal Serial Bus

Universal Serial Bus-61

Mitsubishi

M37640E8-XXXF Preliminary Specification

MS~IEP3_0UT_INTI EP3_IN_INT 1EP2_0UT_~ EP2_IN_INT Fl_OUT_~ EPl_IN_INT _ENDPTO_INT
Bit

ENDPTO_INT

Address: 0052 16
Reset:

00 16

CPU

DescripdoD

Name

J..

GFI sets this bit upon:
1. Setting OUT_PKT_RDY bit of the ENDPOINT 0 IN CSR register
2. Clearing IN_PKT_RDY bit of the ENDPOINT 0 IN CSR register
3. Setting SElUP_END bit of the ENDPOINT 0 IN CSR register
4. Clearing DATA_END bit of the ENDPOINT 0 IN CSR register
5. Setting FORCE_STALL bit of the ENDPOINT 0 IN CSR register

RIW

Reserved

RIW

EPl_IN_INT

GFI sets this bit upon clearing IN_PKT_RDY bit of the ENDPOINT 1 IN CSR register

RIW

EPl_OUT_INT

GFI sets this bit upon setting OUT]KT_RDY bit of the ENDPOINT lOUT CSR register

RIW

EP2_IN_INT

GFI sets this bit upon clearing IN_PKT_RDY bit of the ENDPOINT 2 IN CSR register

RIW

EP2_0UT_INT

GFI sets this bit upon setting OUT]KT_RDY bit of the ENDPOINT 2 OUT CSR register

RIW

EP3_IN_INT

GFI sets this bit upon clearing IN_PKT_RDY bit of the ENDPOINT 3 IN CSR register

RIW

EP3_0UT_INT

GFI sets this bit upon setting OUT_PKT_RDY bit of the ENDPOINT 3 OUT CSR register

RIW

Figure 2·53. Interrupt Status Register 1

The Interrupt Status Register 1 is used to indicate what condition caused an interrupt to the CPU. The
CPU writes a "1" to clear the corresponding interrupt status bit.
______

______

LSB

Address: 0053 16

Reset:
Bit

Name

Descripdon

CPU

EP4_IN_INT

GFI sets this bit upon clearing IN_PKT_RDY bit of the ENDPOINT 0 IN CSR register

RIW

EP4_0UT_INT

GFI sets bit upon setting OUT_PKT_RDY bit of the ENDPOINT 0 OUT CSR register

RIW

Reserved

RIW

OVERIUNDER

GFI sets this bit if an overrun or underrun condition occurred in any of the isochronous endpoints

RIW

USB_RST_INT

GIF sets this bit upon receiving a reset signal from the host. All USB intemal registers will be reset to their default
values except this bit. This bit is cleared by the CPU writing a ''0'' to it. An interrupt will also generate if the
corresponding enable bit is set.

RIW

RESUME_INT

GFI sets this bit upon receiving resume signaling from the host.

RIW

SUSPEND_INT

GFI sets this bit upon receiving suspend signaling from the host.

RIW

3:2
4
5

Figure 2·54. Interrupt Status Register 2

The Interrupt Status Register 2 register is used to indicate what condition caused an interrupt to the
CPU. The CPU writes a "1" to clear the corresponding interrupt status bit.

~S~ E_EP3_0_INT! E_EP3_CINT !EYP2_0_INT! E_EP2_CINT !EJlPCO_INT! E_EPUJNT
Bit

Name

E_EPO_CINT

DescripdoD
Endpoint 0 IN interrupt is enabled when this bit is set High
Reserved

Reset:

FFI6

CPU

WfR
R

E~CUNT

Endpoint 1 IN interrupt is enabled when this bit is set High

E_EPCO_INT

Endpoint 1 OUT interrupt is enabled when this bit is set High

E_EP2_CINT

Endpoint 2 IN interrupt is enabled when this bit is set High

E_EP2_0_INT

Endpoint 2 OUT interrupt is enabled when this bit is set High

E_EP3_CINT

Endpoint 3 IN interrupt is enabled when this bit is set High

E_EP3_0_INT

Endpoint 3 OUT interrupt is enabled when this bit is set High

Address: 005416
E_EPO_CINT 0

WfR
WfR
WfR
WfR
WfR
WfR

Figure 2·55. Interrupt Enable Register 1

Universal Serial Bus-62

Universal Serial Bus

Mitsubishi

M37640E8-XXXF Preliminary Specification

The Interrupt Enable Register I register is an interrupt enable register, if the corresponding bit is "0",
the respective interrupt is disabled. Upon reset, all the interrupts are' disabled.
.
MSB
7

E- sus- INT

l'iyi'''<,,,;1
.< ,',;, ,<

l,j;~Hr~'%~lrli'r;'!~~.l~~;;IE
F';;""
,"'.if//'F';;?l}'·"'"
- EPO- - INTI E- EP4- I- INT I

E_RST_INT I E_OU_INT

Name

E_EP4_I_INT

Endpoint 4 IN interrup1 is enabled when this bit is set High

W/R

E_EP4_0_INT

Endpoint 4 OUT interrupt is enabled when this bit is set High

WIR

E_OU_INT

E_RST_INT

E_SUS_INT

Address: 0055 16
Reset:

33 16

CPU

Bit

3:2

~SB

Description

Reserved

OverrunlUnderrun interrupt is enabled when this bit is set High

WIR

USB Reset interrupt is enabled when this bit is set High

W/R

Reserved

Suspend and Resume interrupts are enabled when this bit is set High

WIR

Figure 2-56. Interrupt Enable Register 2

The Interrupt Mask Register 2 is an interrupt enable register, if the corresponding bit is "0", the
respective interrupt is disabled. Upon reset, all the interrupts are enabled except bit 7 - suspend and
resume interrupt is disabled.

~sd

FN7

FN6

FN5

FN4

I....____~____'_____-'-____

FN3

FN2

FNl

I~SB

FNO

.L__ _ __ J ._ _ _ _..J__ _ __ _ ' ' _ __ _ _.....I.

Bit
7:0

Name
RN7:0

Description

Lower 8 bits of the II-bit frame number issued with a SOF token

Address: 0056 16
Reset:
00 16

CPU
R

Figure 2-57. Frame Number Register Low

The frame number low register contains the lower 8 bits of the II-bit time stamp received from the host. '
LSB Address: 005716

Name

Bit
2:0

FNIO:8

7:3

Description

Reset:

CPU

Upper 3 bits of the II-bit frame number issued with a SOF token

Reserved

Figure 2-58. Frame Number Register High

The frame number high register contains the upper 3 bits of the II-bit time stamp received from the host.

Universal Serial Bus

Universal Serial Bus-63

Mitsubisbi

M37640E8-XXXF Preliminary Specification

MSB
7

J...

LSB Address: 0058 16
0

~=::;;::=~:::==~====~===~==================~_~R~eset: 00 16
Bit

2:0

EPINDEX2:0

6:3

CPU

Description

Name
Endpoint Index:
000 Function Endpoint 0
001 Function Endpoint I
010 Function Endpoint 2
011 Function Endpoint 3
100 Function Endpoint 4
Others: Undefined

WIR

Reserved
HlSO_UPDATE - zero, whenever the IN]KT_RDY bit is set, it is send to the Serial Interface
Engine (SlE) immediately, available for the next IN_TOKEN from the host; if lOS_UPDATE - one
and ISO bit of the corresponding endpoint's IN CSR is set, the in IN]KT_RDY bit is delayed until
the next SOF before being sent to the SlE.1n this way, the IN_PKT_RDY is synchronized with the
SOF. The ISO_UP_DATE bit is a global bit for endpoints I to 4, and wolks with isochronous pipe
only.

WIR

Figure 2-59. Endpoint Index Register

The Endpoint Index Register identifies the endpoint pair. Its contents select the transmit and receive
FIFO pair and serve as an index to endpoint-specific IN_CSR, OUT_CSR, IN_MAXP, OUTMAXP and
OUT_WRT_CNT registers. This register also contains a global bit, ISO_UPDATE, for endpoints 1-4, to
specify the way IN_PKT_RDY is sent by the SIE.
MS
7

SERVICED
SETUP_END

1OUT_PKT_RDY
SERVICED ·1

SETUP_END

1 SENT_STAlL 1

DATA_END

1FORCE_STALL 1 IN]KT_RDY

IOUT_PKT_RDY

LSB

Address: 0059 16
Reset:
Bit

Name

DescrIption

00 16
CPU

OUT_PKT_RDY

GFI sets this bit upon receiving a valid SETUP/OUT token from the host. CPU clears this bit after
unloading the FIFO, by way of writing a "I" to bit 6 of this register.

IN_PKT_RDY

CPU sets this bit upon writing a packet of data to endpoint 0 FIFO. GFI clean this bit upon successful
transmission of IN packet.

WIR

SEND_STALL

CPU writes a "I" to this bit if it decodes an invalid SETUP token. GFI clean this bit upon sending a
STALL handshake.

WIR

DATA_END

CPU sets this bit when it writes (IN data phase) or reads (OUT data phase) the last packet of data from/to
the FIFO. This bit indicates to the GFI that the specific amount of data in the setup phase is transferred.
The GFI will advance to status phase once this bit is set. When the status phase completes, the GFI clean
this bil

WIR

FORCE_STALL

GFI sets this bit if it detects a protocol violation, sends a STALL handshake, and also causes an interrupt.
The CPU writes a "0" to clear this bit.

WIR

SETUP..END

GFI sets this bit if a control transfer has ended before the specific length of data is transferred during the
data phase (for instance, if it gets a new setup phase or a status phase before data end is set). CPU clean
this bit, after returning to idle state by way of writing a "I" to bit 7 of this register. Once the CPU sees
SETUP_END bit set, it will stop access the FIFO to service the previous setup transaction. H
OUT_PKT_RDY is set at the same time SETUPJlND is set, it indicates the previous setup transaction
ended, and new SETUP token is in the FIFO.

SERVICED_OUT]KT_RDY

CPU writes a "I" to this bit to clear OUT_PKT_RDY bit (bit 0).

SERVICED_SETUP_END

CPU writes a "I" to this bit to clear SETUP_END bit (bit 5).

W
W

Figure 2-60. Endpoint 0 IN CSR

The Endpoint 0 IN register contains the control and status infonnation of the respective endpoint.
(Endpoint 0 uses this register for all control and status Infonnation).

Universal Serial Bus-64

Universal Serial Bus

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

MSB
LSB Address: 0059'6
L-_ _ _ _...l.._ _ _ _....1..._ _ _ _-L._ _ _ _-L._ _ _ _-..L_ _ _ _ _L -_ _ _ _L -_ _ _--1 0
Reset:
00'6
7
Bit

Name

Description

CPU

WfR

IN_PKT_RDY

This bit is set when a packet of data is written to the FIFO. If bit 7 (AUTO_SEl) is a ''0''. the IN]KT_RDY bit is set by
the CPU after a packet of data is loaded into the FIFO; If AUTO_SET bit is a "1 ", the IN]KT_RDY is set automatically
by the GFI after the numher of bytes of data equal to the maximum packet size (MAXP) is written into the FIFO. This bit
is cleared by the GFI. (see 'Transmit F1F0s' description for detail)

UNDER_RUN

This bit is used in ISO mode only to indicate to the CPU that FIFO underrun occurred. GFI sets this bit at the heginning
ofa IN token ifIN]KT_RDY bit is not set. Upon setting this bit, the OVER_UNDER bit of the Interrupt Status Register
2 will be set. This bit is cleared by the CPU writing a "0" to this bit.

WfR

SEND_STALL

CPU writes a "1" to this bit when it encounters a STALL condition The GFI sends a STALL handshake when this bit is
set. the CPU writes a ''0'' to clear this bit after the STALL condition is removed.

WfR

ISO

CPU sets this bit to initialize the respective endpoint as an Isochronous endpoint for IN transaction.

W/R

INTPT

CPU sets this bit to initialize this endpoint as a status change endpoint for IN transaction. This bit should be set if the
corresponding endpoint is to be used as an interrupt endpoint. (see 'Transmit F1FOs' description for detail)

WfR

TICNOT_EPT

Transmit FIFO not empty, the GFI sets this when there is data in tbe TX FIFO. This bit in conjunction with
IN_PKT_RDY bit will ptovide the transmit FIFO status information (see 'Transmit F1FOs' description for detail)

FLUSH

CPU sets this bit to flush the FIFO

AUTO_SET

If this bit is a "1", the IN]KT_RDY is set automatically by tbe GFI after the number of bytes of data equal to the
maximum packet size (MAXP) is written into the FIFO.

WfR

Figure 2-61. Endpoints 1, 2, 3, 4 IN CSR

This register contains the control and status information of the respective IN endpoint. (For Endpoints
1, 2, 3, 4)
MSB
7

LSB

Bit

Name

7:0

Address: 005A'6
Reset:

00 16

CPU

Description

Reserved

Figure 2-62. Endpoint 0 OUT CSR

For Endpoint 0, all bits in this register are reserved (all the control and status information is in
Endpoint 0 IN CSR)
MSB
7

AUTO_CLR I
Bit

FLUSH

DATA_ERR I SENT_STALLI

ISO

IFORCE_STA~

OVER_RUN

IOUT]KT_RD~

bSB Address: 005A 16
Reset:

Name

Description

CPU

WfR

OUT]KT_RDY

GFI sets this bit after it has written a packet of data to the FIFO. This bit is cleared when a packet of data is
unloaded from the FIFO. If bit 7 (AUTO_CLR) is a "0", the OUT]KT_RDY bit is cleared by the CPU
after a packet of data is unloaded from the FIFO; If AUTO_CLR bit is a "1", the OUT]KT_RDY is
cleared automatically by the GFI after the packet of data in unloaded from the FIFO.

OVER_RUN

This bit is used in ISO mode only to indicate to the CPU that FIFO overrun occurred. If the GFI receives a
OUT ISO token while OUT_PKT_RDY bit is not cleared, then it discards the data from the host. and sets
this bit. This bit is cleared by the CPU writing a ''0'' to this bit.

WfR

SEND_STALL

CPU sets this bit when it encounters a STALL condition. CPU writes a ''0'' to clear this bit after the STALL
condition is removed.

WfR

ISO

CPU sets this bit to initialize the respective endpoint as an Isochronous endpoint for OUT transaction

WfR

FORCE_STALL

GFI sets this bit if it detects a protocol violation, and sends a STALL handshake. CPU writes a ''()'' to clear
this bit after the STALL condition is removed

DATA_ERR

GFI sets this bit to indicate a CRC error or bit stuffing error received in an ISO packet The CPU writes a
''0'' to clear this bit.

FLUSH

CPU sets this bit to flush the FIFO

AUTO_CLR

If this bit is a "1", the OUT]KT_RDY is cleared automatically by the GFI after the packet of data in
unloaded from the FIFO.

00 16

WfR
W
WfR

Figure 2-63. Endpoint 1, 2, 3,4 OUT CSR

This register contains the control and status information of the respective endpoint. (For Endpoints 1, 2, 3, 4)

Universal Serial Bus

Universal Serial Bus-65

M37640E8-XXXF Preliminary Specification

Mitsubishi

J...

Address: 005B 16

Reset:

Name

Bit

00 16

Description

CPU

MAXP - n * 8 for endpoint 1
Where n is the value written to this register. For endpoints that support smaller FIFO size, unused bits
are not implemented (always·write ''0'' to those bits)

WfR

MAXI' - n for endpoints 0, 2, 3, 4

MAXP7:0

7:0

Figure 2-64. Endpoint x IN MAXP

This register indicates the maximum packet size (MAXP) of Endpoint x IN packet. The default value
for endpoint 0 is 8-byte, the default values for endpoints 1-4 are O-byte. The CPU can change this
value, as negotiated with the host controller through the SET_DESCRIPTOR command.

MS~

MAXP5

Name

Bit
7:0

MAXP6

MAXP7

MAXP4

Address: 005C 16

MAXP3

Reset:

00 16

Description

CPU

MAXP - n for endpoints 2, 3, 4
MAXP - n * 8 for endpoint 1
where n is the value written to this register. For endpoints that support smaller FIFO size, unused bits
are not implemented (always write ''0'' to those bits)

MAXP7:0

WfR

Figure 2·65. Endpoint x OUT MAXP

This register indicates the maximum packet size (MAXP) of Endpoint x OUT packet. The default
values for endpoints 1-4 are O-byte. The CPU can cbange this value, as negotiated with the host
controller through the SET_DESCRIPTOR command.
For endpoint 0, all bits in this register are reserved; endpoint 0 uses IN MAXP register for both IN
and OUT transfers.
Address: 005D 16

MSB
7

Reset:

00 16

Byte Count. This regist!'1" contains the lower 8 bits of the byte count register.

Figure 2-66. Endpoint 0, 1,2,3,4 OUT Write Count Register Low

LSB

MSB
7

' - -_ _--'-_ _---1

Bit

1:0

Description

Name

WRT_CNT9:8

7:2

Address: 005E 16

Reset:

00 16

CPU

Byte Count. This register contains the upper 2 bits of the byte count register. The GFI
sets the value in these two Write Count Registers after received end-of-packet (EOP)
signal from the host. The CPU reads these two registers to determine the number of
bytes to be read from the FIFO. The CPU should read Count Register Low first then
Register High.

Reserved.

Figure 2-67. Endpoint 0,1,2,3,4 OUT Write Count Register High

These two registers contains the number of bytes in Endpoint x OUT FIFO.

Universal Serial Bus-66

Universal Serial Bus

J,..

Mitsubishi

M37640E8-XXXF Preliminary Specification

Address: 0060 16

Reset:

Bit

Name

00 16

Description

IEndpoint 0 IN/our FIFO register

WIR

Figure 2-68. Endpoint 0 FIFO Register

This register is the USB transmit (IN) and receive (OUT) FIFO data register. The CPU writes data to this
register for Endpoint 0 IN FIFO. The CPU reads data from this register for Endpoint 0 OUT FIFO.
Address: 0061 16

Reset:

Bit

Name

I
Description
1Endpoint 1 IN/OUT FIFO register

I
I

CPU

WIR

00 16

I
J

Figure 2-69. Endpoint 1 FIFO Register

This register is the USB transmit (IN) and receive (OUT) FIFO data register. The CPU writes data to this
register for Endpoint 1 IN FIFO. The CPU reads data from this register for Endpoint 1 OUT FIFO.
Address: 0062 16

MSB

Reset:

0016

Figure 2-70. Endpoint 2 FIFO Register

This register is the USB transmit (IN) and receive (OUT) FIFO data register. The CPU writes data to this
register for Endpoint 2 IN FIFO. The CPU reads data from this register for Endpoint 2 OUT FIFO.
MSB

Address:

0063 16

Reset:

00 16

Description
Endpoint 3 IN/our FIFO register

Figure 2-71. Endpoint 3 FIFO Register

This register is the USB transmit (IN) and receive (OUT) FIFO data register. The CPU writes data to this
register for Endpoint 3 IN FIFO. The CPU reads data from this register for Endpoint 3 OUT FIFO.
Address: 006416

Reset:

Bit

Name

I
DescrIption
IEndpoint 4 IN/our FIFO register

CPU

WIR

00 16

Figure 2·72. Endpoint 4 FIFO Register

This register is the USB transmit (IN) and receive (OUT) FIFO data register. The CPU writes data to this
register for Endpoint 4 IN FIFO. The CPU reads data from this register for Endpoint 4 OUT FIFO.

Universal Serial Bus

Universal Serial Bus-67

Mitsubishi

M37640E8-XXXF Preliminary Specification

J...

2.11 Master CPU Bus Interface
Address

Description

Code

Data bus buffer register 0

0048 16

DBBO=OO

- Data bus buffer status register 0

0049 16

DBBSO=OO

004C 16

Data bus buffer control register 0 DBBCO=OO
Data bus buffer register 1
DBBl==OO

004D 16

Data bus buffer status register 1

004A 16

004E16

DBBSl==OO
Data bus buffer control register 1 DBBCl=OO

Description

P601P67 are multiplexed with DQO-DQ7
P51 is multiplexed with OBFo
P52 is multiplexed with ffiFo
P53 is multiplexed with So
P54 is multiplexed with Ao

Description

P55
P56
P72

is multiplexed with R or E
is multiplexed with W or RJW

P73
P77

is multiplexed with IBFl
is multiplexed with OBF1

is multiplexed with SI -

This device has a 2-bit internal bus interface function that can be operated in slave mode by control
signals from the master CPU (see Figure 2-73. Bus Interface Circuit). The bus interface can be
connected directly to either a RlW type of CPU or a CPU with RD and WR separate signals. Slave
mode is selected with the bit 7 of the data buffer control register O. The single data bus buffer mode
and the double data bus buffer mode are selected with the bit 7 of the data bus buffer control register
1. When selecting the double data bus buffer mode. Port P72 becomes 8 1 input.
OBFO 1BFo Ao So R:

...
B

.~
~-

y y6 or y4 yl y2 yl yO

r7f

...L

r- -

~ roo-

r+ ~

~I-

S1;"

~r-

,...
..

~
II
Q

}

~
1
i

. _..L."
!.?.

Ilf

Rn
WR

~D1iiiS;

I 1

T I

~., mF 08F,

~l1i

•

Rn
WR

1.1,

BF.

).J
i

!!I

DOP,

u
~..
.
0

r" ~

:system Bus

--.

1'1

-~:

=u• •

-Us

!!.
~
FI

:! r-~

til

-'"=
til
- =

b;
--~

g
[

E
~.

Data Bus

Figure 2-73. Bus Interface Circuit

When data is written to the MCU from the master CPU, an input buffer full interrupt request occurs.
Similarly, when data is read from the master CPU, an output buffer empty interrupt request occurs.

Master CPU Bus Interface-68

Master CPU Bus Interface

Mitsubishi

M37640E8-XXXF Preliminary Specification

When the bus interface is operating, DQo-D07 become a 3-state data bus that sends and receives data,
command, and status to and from the master Cpu. At the same time, W, R, So' Sl' and Ao become
host CPU control signal input pins.
Two input buffer full interrupt requests and two output buffer full requests are used as shown in
Figure 2-74..
The bus interface can be operated under normal MCU control or under on-chip DMA control for fast
data transfer. If a master CPU has a large amount of data to be transferred, use of the on-chip DMA
controller is highly recommended.
The bus interface signal input level can be programmed as CMOS level (default) or as TTL level.
Bit 7 of the Port Control Register (PTC7) is used for the input level selection.
Input buffer full flag 0
IBFO - - - I

Ri5in, Edll" .
detecboncm:w'

Input buffer full flag 1
IBFl - - - - I

=.:rn:ui,

Input Buffer full intenupt
request signal IBF

Output buffer full flag 0
OBFO
Output buffer full flag 1
OBFl

Output Buffer Empty intenupt
request signal OBE

IBFO _ _---.I
IBF1 _ _ _ _ _ _ _ _

----..Wf--!!:::::::=::::::;.LL
~Set intenupt request at this rising

IBF

OBFO
( O B E O ) - - - - -....
OBFl
(OBE1)

------------1

---------------'W---'======R.

OBE

--=Set intenupt request at this rising

Figure 2-74. Data Bus ButTer Interrupt Request Circuit

~SB

DBBS07

DBBS06

DBBSOO

DBBSOI

DBBSOO
DBBS03
DBBS04
DBBSOS
DBBS06
DBBS07

DBBOS

DBBS04

DBBS03

DBBSOO

DBBSOl

DBBSoo

Output Buffer Full (OBFO> Flag
oOutput buffer empty.
1Output buffer full.
Input Buffer Full (IBFO> Flag
oInput buffer empty.
1 Input buffer full.
User Definable (U2) Flag

Ao (Aoo>

I~B

Address: 0049 16
Access: RIW

Reset:

00 16

Flag

Indicates the Ao status when IBF flag is set
User Definable (U4) Flag
User Definable (US) Flag
User Definable (U6) Flag
User Definable (U7) Flag

Figure 2-75. Data Bus ButTer Status Register 0

Master CPU Bus Interface

Master CPU Bus Interface-69

Mitsubishi

M37640E8-XXXF Preliminary Specification

MSB

LSB

______~____~____~____~____~O

?
DBBCoo

DBBCOI

DBBC02

DBBC03
DBBC04
DBBCOS
DBBC06

DBBCO?

.J...

Address: 004A16

Access: RJW
OBF Output Selection Bit
.Reset:
00 16
is operated as normal 110 pin
I PS2 pin is operated as OBFo output pin
mP Output Selection Bit
.
oPS3 pin is operated as normal 110 pin
I PS3 pin is operated as IBFo output pin
IBFo Interrupt Selection Bit
OIBFo interrupt is generated by both write-data (Ao - zero) and write-command (Ao - one)
I IBFo interrupt is generated by write-command (Ao - one) only
Output buffer 0 empty interrupt disable
Input buffer 0 full interrupt disable
Reserved
Master CPU Bus Interface Enable Bit
OP60-P6? PS4-PS? are GPIO pins
I P60-P6? PS4-PS? are bus interface signals DQO-DQ? ~()o Ao. It W respectively.
Bus Interface 'JYpe Selection Bit
oRD. WR separate type bus
I RJW type bus.

oPS2 pin

Figure 2·76. Data Bus ButTer Control Register 0

~SB 1 DBBSI? 1 DBBSI6 I'
DBBSIO

DBBSll

DBBSI2
DBBS13
DBBSI4
DBBSIS
DBBSI6
DBBSI?

DBBIS

1 DBBSI4 1 DBBSI3

DBBSI2

DBBSll

1 DBBSIO 1~B

Output Buffer Full (OBF I) Flag
OOutput buffer empty.
I Output buffer full.
Input Buffer Full (lBF I) Flag
oInput buffer empty.
I Input buffer full
User Definable (U2) Flag
Ao (AoI) Flag
Indicates the Ao status when IBF flag is set
User Definable (U4) Flag
User Definable (US) Flag
User Definable (U6) Flag
User Definable (U7) Flag

Address: 004D16
Access: RJW

Reset:

00 16

Figure 2-77. Data Bus ButTer Status Register 1

______

DBBCll

DBBCI2

DBBCI3

DBBCI4
DBBCIS
DBBCI6
DBBCI?

LSB

Address: 004E 16

Access: RIW
~~--~----~----~~--~O
OBF I Output Selection .
Reset:
00)6
0: P74 pin is operated as normal ·110 pin
I: P74 pin is operated as OBF I output pin if DBBCI? - one
IBF) Output Selection Bit
0: P73 pin is operated as normal 110 pin
I: P73 pin is operated as mPl output pin if DBBCI? - one
IBF) Interrupt Se1ection Bit
0: IBF) interrupt is generated by both write-data (Ao - zero) and write-command (Ao - one)
1: IBFI interrupt is generated by write-command (Ao - one) only
Output Buffer I Empty interrupt disable
I: Disable
0: Enable (default)
Input Buffer I Full interrupt disable
Reserved
Reserved
Data Bus Buffer Function Selection bit
0: Single data bus buffer - P72 is used as GPIO
I: Double data bus buffer - P72 is used as ~1 input

Figure 2·78. Data Bus ButTer Control Register 1

Master CPU Bus Interface-70

Master CPU Bus Interface

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

2.11.1 Data Bus ButTer Status Registers (DBBSO, DBBS1)
The data bus buffer status register is an 8-bit register that indicates the data bus status, with bits 0, 1, and
3 being dedicated read-only bits. Bits 2, 4, 5, 6, and 7 are user definable flags set by software, and can
be read and write. When the Ao pin is High, the master CPU can read the contents of this register.
Output Buffer Full Flag (OBFo, OBF1)
The OBFo and the OBF 1 flags are set High when data is written to the output data bus buffer by the
slave CPU and is cleared to "0" when data is read by the master CPU.
Input Buffer Full Flag (IBF~ IBF I)
The IBFo and the IBF 1 flags are set High when data is written to the input data bus buffer by the
master CPU and is cleared to "0" when data is read by the slave CPU.

Flag (Ao~

The level of the
bus buffer.

AoI)

pin is latched when data has been written from the host CPU to the input data

2.11.2 Input Data Bus ButTer Registers (DBBINo, DBBIN1)
The data on the data bus is latched into DBBINo or DBBINl by a write request from the master CPU.
The data in DBBINo or DBBIN 1 can be read from the data bus buffer register in the SFR area.

2.11.3 Output Data Bus ButTer Registers (DBBOUT0' DBBOUT1)
Data is set in DBBOUTo or DBBOUT 1 by writing to the data bus buffer register in the SFR area.
When the Ao pin is Low, the data of this register is output by a read request from the host CPU.

Master CPU Bus Interface

Master CPU Bus Interface-71

Mitsubisbi

M37640E8-XXXF Preliminary Specification

J...

2.12 UART
Address

UARTt Description

Acronym and
Value at Reset

Address

UART2 Description

Acronym and
Value at Reset

003016

UARTl mode register

UlMOD=OO

0038 16

UARTl mode register

U2MOD=OO

0031 16

UARTI baud rate generator

UlBRG=XX

0039 16

UARTl baud rate generator

U2BRG-XX

0032 16

UARTl status register

UlSTS=03

003A16

UARTl status register

U2STS=03

0033 16

UARTl control register

UlCON=OO

003B 16

UARTl control register

U2CON=OO

003416

UARTltransmitlreceiver buffer I

UlTURBI-XX

003C16

UARTltransmitlreceiver buffer I

U2TRBl=XX

0035 16

UARTl transmitlreceiver buffer 2

UlTURB2=XX

003D 16

UARTltransmitlreceiver buffer 2

U2TRB2-XX

0036 16

UARTl RTS control register

UlRTSC=OO

003E16

UARTl RTS control register

U2RTSC=OO

Description

UIXDI

UARTl transmit pin is multiplexed with
P84.

UTXD2

UARTl transmit pin is multiplexed with
PSO.

URXDI

UARTI receive pin is multiplexed with
PS5.

URXD2

UARTl receive pin is multiplexed with
PSI.

CTSI

UARTl CTS I pin is multiplexed with
P86

CTS2

UARTI CTS2 pin is multiplexed with
P82

RTSI

UARTl RTS 1 pin is multiplexed with
P87

RTS2

UARTl RTS2 pin is multiplexed with
P83

This chip contains two identical UARTs. Each UART has the following main features:
•
•
•
•
•
•
•
•
•
•

cl» or SCSGCLK
xl/x8/x321x256 divisions (both cl» and SCSGCLK)
9.5 bits/second - 625 Kbyteslsecond (at cl» - lOMHz)
parity/framingloverrunlerror sum
odd/evenlnone
1 or 2
7, 8, or 9 bits
2 stages (double buffering)
Tx Buffer Empty or Transmit Complete, RX Buffer full and
Receive error sum.
Address mode for multi-receiver environment

Clock selection:
Prescaler selection:
Baud rate:
Error detection:
Parity:
Stop bits:
Character length:
Transmit/receive buffer:
Interrupt generation conditions:

The following descriptions apply to both UARTs.
The UART receives parallel data from the core, or DMA converts it into serial data, and transmits the
results to the send data output terminal UTXDx. The UART receives serial data from an external
source through the receive data input, URXDx, converts it into parallel data and makes it available to
the core or DMA. The UART can detect parity, overrun, and framing errors in the input stream and
report the appropriate status information. A double buffering configuration is used for the UART's
transmit and receive operations. This double buffering is accomplished by the use of a Transmit Buffer
and Transmit Shift Register on the transmit side and the Receive Buffer and Receive Shift Register
on the receive side.
The UART generates the Transmit interrupt when either the TranSmit Buffer Empty (TBE) flag or the
Transmit Complete (TCM) flag are set, depending on the state of the Transmit Interrupt Source
Selection (bit 4 of the UxCON). The UART generates the Rx Buffer full interrupt when receiving and

UART·72

UART

M37640E8-XXXF Preliminary Specification

Mitsubisbi

the Rx Buffer Full flag goes High. The Receive Error interrupt is generated instead of a Rx Buffer full
interrupt if the UART detects an error when receiving (see Figure 2~79.). Enabling a transmit or
receive operation by setting the TEN or the REN (bits 0 and 1 of UxCON) automatically forces the
corresponding the UART port pins in the appropriate direction.
The UART supports an address mode for use in a multi-receiver environment where an address is sent
before each message to designate which UART or UARTs are to wake-up and receive the message.

Tx Enable

UART

Intemil Data

Receive line from URXD

Receive Buffer Full Interrupt
UTRBI
UTRB2

Receive Error

errupt
Data Bus

Figure 2-79. UART Block Diagram

2.12.1 Baud Rate Selection
Either an internal clock /1

Baud Rate

625,000.0

312,500.0

208,333.3

156,250.0

125,000.0

104,166.7

89,285.7

78,125.0

69,444.4

62,500.0

<1>18

Baud Rate

<1>1256

<1>132

Baud Rate

78,125.0

39,062,5

26,041.7

19,531.3

19,531.8

9,765.6

15,625.0

6,510.4

13,020.8

4,882.8

11,160.7

3,906.3

3,255.2

2,790.2

2,441.4

2,170.1

1,220.7

255

441.4

J...

255

305.2

255

76.3

8l3.8

610.3

488.3

406.9

348.7

255

9.54

Figure 2-80. Prescale Value and Baud Rate Thble

2.12.2 UART Mode Register
UxMOD defines data formats and selects the clock to be used (see Figure 2-82.)

2.12.3 UART Baud Rate Register
In the UART Baud Rate Register (UxBRG), any value can be specified to obtain the desired baud
rate. This register remains in effect whether the UART is send-enabled, receive-enabled, transmit-inprogress, or receive-in-progress. The contents of this register can be modified only when the UART is
not in any of these four states.

UART-74

UART

Mitsubishi

M37640E8-XXXF Preliminary Specification

2.12.4 UART Control Register
The DxCON specifies the initialization and enabling of a transmit/receive process (see Figure 2-81.)
Information can be read from and written to the Control Register. Bits 5 and 6 are always Low during
read; writing to these bits is ignored.

2.12.5 UART Status Register
The DART Status Register (DxSTS) reflects -both the transmit and receive status -(see Figure 2-83.).
The status register is read only. The MSB is always "0" during a read operation. Writing to this
register has no effect. Status flags are set and reset under the conditions indicated below. The setting
and resetting of the transmit and receive status are not affected by transmit and receive enable flags.
The setting and resetting of the receive error flags and receive buffer full flag differs when DART
address mode is enabled. These differences are described in "2.12.9 DART Address Mode".

Receive Error Sum Flag
The Receive Error Sum Flag (SER) is set when an overrun, framing, or parity error occurs after
completion of a receive operation.
It is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized

by setting the Receive Initialization Bit (RIN). If a receive operation is completed when the status
register is being read, the status information is updated upon completion of the status register read.

Receive Overrun Flag
The Receive Overrun Flag (OER) is set if the previous lower byte data is not read before the current
receive operation is completed. It is also set if a receive error occurred for the previous data and the
status register is not read before the current receive operation is completed. This flag is reset when the
status register is read. This flag is also reset when the hardware reset is asserted or the receiver is
initialized by RIN. If a receive operation is completed when the status register is being read, the status
information is updated upon completion of the status register read.

Receive Framing Error Flag
The Receive Framing Error Flag (FER) is set when the stop bit of the received data is "0". If the
Stop Bit Selection Bit (STB, bit 3) is set, the flag is set if either of the two stop bits is low. This
flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized
by RIN. If a receive operation is completed when the status register is being read, the status
information is updated upon completion of the status register read.

Receive Parity Error Flag
The Receive Parity Error Flag (PER) is set when the parity of received data and the Parity Selection
Bit (PMD, bit 4) are different. It is enabled only if the Parity Enable Bit (PEN, bit 5) is set.
This flag is reset when the status register is read, the hardware reset is asserted, or the receiver is
initialized by RIN. If a receive operation is completed when the status register is being read, the status
information is updated upon completion of the status register read.

Receive ButTer Full Flag
The Receive Buffer Full flag (RBF) is set when the last stop bit of the data is received. It is not set
when a receive error occurs. This flag is reset when the lower byte of the receive buffer is read, the
hardware reset is asserted, or the receive process is initialized by RIN. If a receive operation is
completed when the status register is being read, the status information is updated upon completion of
the status register read.

UART

UART-7S

Mitsubishi

M37640E8-XXXF Preliminary Specification

J....

Transmission Complete Flag
In the case where no data is contained in the transmit buffer, the Transmission Complete Flag (TCM)
is set when the last bit in the transmit shift register is transmitted. In the case of disabling
transmission when the transmission when the transmit buffer still contains data, the TCM flag is set
. when the last bit in the transmit shift register is transmitted. The TCM flag is also set when the
hardware reset is asserted or when the transmitter is initialized by setting the Transmit Initialization Bit
(TIN) (bit 2). It is reset when a transmission operation begins.

Transmission Buffer Empty Flag
The Transmission Buffer Empty Flag (TBE) is set when the contents of the transmit buffer are loaded
into the transmit shift register. The TBE flag is also set when the hardware reset is asserted or when
the transmitter is initialized by TIN. It is reset when a write operation is performed on the lower byte
of the transmit buffer.

~BI

AME

TEN

REN

TIN

RIN

TIS

AME

I RTS_SEL I CTS_SEL I

TIS

RIN

TIN

REN

TEN

LSO B Address: 0033 16,003B 16

Access: R/W

Transmission Enable Bit
00 16
Reset:
O:Disable the transmit process
l:Enables the transmit process. If the transmit process is disabled (TEN cleared) during transmission,
the transmit will not stop until completed.
Receive Enable Bit
O:Disable the receive process
l:Enables the receive process. If the receive process is disabled (REN cleared) during reception, the
receive will not stop until completed.
1ransmission Initialization Bit
O:No action.
l:Resets the UART transmit status register bits as well as stopping the transmission operation. 1be
TEN bit must be set and the transmit buffer reloaded in order to transmit again. 1be TIN is
automatically reset one cycle after TIN is set.
Receive Initialization Bit
O:No action.
l:Clears the receive status flags for the UARTand the REN bit. If RIN is set during receive in
progress, receive operation is aborted. 1be RIN bit is automatically reset one cycle after RIN is set.
1ransmit Interrupt Source Selection Bit
O:Transmit interrupt occurs when the Transmit Buffer Empty flag is set.
l:Transmit interrupt occurs when the Transmit Complete flag is set.
Clear To Send (CTS) Selection Bit
O:CTS function is disabled, P86 (or P82) is used as GPIO pin.
l:CTS function is enabled, P86 (or P82) is used as CTS input.
Request To Send (RTS) Selection Bit
O:RTS function is disabled, P87 (or P83) is used as GPIO pin.
l:RTS function is enabled, P83 (or P83) is used as RTS output.
UART Address Mode Enable Bit
O:Address Mode disabled.
l:Address Mode enabled.

Figure 2-81. UxCON Register

UART-76

UART

M37640E8-XXXF Preliminary Specification

Mitsubishi

~SB

LEI
LEO
PEN
PMD
STB
PSI
PSO
CLK.
'----L.C-L-K-----L--U-A-R-T----ICL.I-oc-k-Se-I-ect..Ji'""on-B-it-----I-------I-----L-----I

0:«1>

LOSB

003016• 0038 16
Address: R1W
Access:
Reset:
00 16

I:SCSGCLK
Internal Clock Prescaling Selection Bits
OO:Division by I
OI:Division by 8
10:Division by 32
l1:Division by 256
Stop Bits Selection Bit
0:1
1:2
Parity Selection Bit
O:Even
I:Odd
Parity Enable Bit
O:Off
I:On
Uart Character Length Selection Bits
00:7 bits/character
01: 8 bits/character
10:9 bits/character
l1:Reserved

PSO-I

STB

PMD

PEN

LEO.I

Figure 2-82. UxMOD Register

LSB Address: 0032 16• 003A 16

MSB
7

~~--~~---L~--~~----~----~-TBE

RBF

PER

FER

OER

SER

Bit 7

__~----~O

Transmit-Cornplete (Transmission Register Empty) Flag
0: Data in the transmission register.
I: No data in the transmission register.
TX Buffer Empty Flag
0: Data in the TX Buffer.
I: No data in the TX Buffer.
RX Buffer Full Flag
0: No data in the RX Buffer.
I:Data in the RX Buffer.
Receive Parity Error Flag
0: No receive parity error.
I: Receive parity error.
Receive Framing Error Flag
O:No receive framing error.
I :Receive framing error.
Receive Overrun Flag
O:No receive overrun.
I:Receive overrun.
Receive Error Sum Flag
O:No receive error.
I:Receive error.
Reserved (Read as zero)

Access: R only
Reset:

03 16

Figure 2-83. UxSTS Register

LSB Address: 0036 16• 003E 16

MSB
7

o
RTS3:0

RTS Assertion Delay Count 3:0
0000: No delay. ~ asserts immediately upon receive operation completed.
0001: R'i'S" asserts 8 bit-time upon receive operation completed.
0010: ~ asserts 16 bit-time upon receive operation completed.
0011: R'i'S" asserts 24 bit-time upon receive operation completed.

Access: RIW
Reset:

80 16

III 0: ~ asserts 112 bit-time upon receive operation completed.
asserts 120 bit-time upon receive operation completed.
1111:
Reserved

Bit 3:0

Figure 2-84. UxRTSC Register

UART

UART-77

M37640E8-XXXF Preliminary Specification

Mitsubishi

2.12.6 TransmitIReceive Format
Transmit Method
Setup
• Set the baud rate by writing a value from 0-255 into the UxBRG.
• Set the TIN to one, bit 2 of UxCON. This will reset the transmit status to a value of 03 16.
• Select the interrupt source to either the TBE or the TCM by clearing or setting the TIS bit, bit 4.
• Set the data format and clock selection by writing the appropriate value to UxMOD.
• Set the TEN to one, bit 0 in the UxCON.
Operation
• If no data is being shifted out of the Transmit Shift Register, the TCM Flag in UxSTS goes

High and the data written to the Transmit Buffer Register is transferred to the Transmit Shift
Register. The TBE flag is set High and TCM is signalling that the next byte of data can be written to the transmit buffer.
• Data from the Transmit Shift Register is transmitted one bit at a time beginning with the start bit
and ending with the stop bit. Note that the LSB is transmitted first.
• If the TEN bit is cleared while data is still being transmitted, the transmitter will continue until
the last bit is sent.
• When the last bit is transmitted, the TCM bit is set High. The transmitter is now ready for the
next byte.
Receive Method
Set up
• Set the baud rate by writing a value from 0-255 into UxBGR.
• Set the RIN, bit 3 in the UxCON, to "I".
• Set the data format and the clock selection by using writing the appropriate value to UxMOD.
• Set the REN, bit 1 in the UxCON, to "I".
Operation
• Input data received through the URXDx pin is read one bit at a time, LSB first, into the Receive
Shift Register when the start bit is detected and the receiver is enabled.
• When the number of bits specified by the data format has been received and the stop bit is
detected, the contents of the Receive Shift Register are transferred to the Receive Buffer Register
and the Rx Buffer Full Flag is set High in the UxSTS, if a receive error has not occurred. The
receive interrupt request is also generated at this time if a receive interrupt has not occurred.
Also, at this time the error flags are checked and the receive interrupt request is generated.
• When the Receive Buffer Register is read, the Rx Buffer Full Flag is cleared, and the Receive
Buffer Register is now ready for the next byte.

2.12.7 Interrupts
The transmit and receive interrupts are generated under the conditions described below. The generation
of the receive interrupts differs when UART Address mode is enabled. The differences are described in
"2.12.9 UART Address Mode".

UART-7S

UART

Mitsubishi

M37640E8-XXXF Preliminary Specification

Transmit interrupts
The UART generates a Transmit Interrupt to the CPU core. The source of the Transmit Interrupt is
selectable by setting TIS.
• If TIS = "0", the Transmit interrupt is generated when the transmit buffer register becomes empty
(that is, when TBE flag set).
• If TIS

= "1", The Transmit interrupt is generated after the last bit is sent out of the transmit
shift register and no data has been written to the transmit buffer (that is, when TCM flag set).

Receive Interrupts
The UART generates the Receive Buffer Full (RBF) and Receive Error interrupts to the CPU core
when receiving.
• The RBF interrupt is generated when a receive operation completes and a receive error is not
generated.
• The Receive Error (SER) interrupt is generated when a receive error sum, overrun, framing or
parity error occurs.

2.12.8 Clear-to Send (CTS) and Request-to-Send (RTS) Signals
The UART, as a transmitter, recognizes the Clear-to-Send (CTS) input as a handshaking signal. As a
receiver, the UART will generate the Request-to-Send (RTS) handshaking signal.
Clear-to-Send (CTS) Input
When TEN is set and Tx buffer is loaded, the UART begins the transmission process when a CTS is
asserted Oow input). After beginning a send operation, the UART does not stop sending until the
transmission is completed, even if the CTS is negated (high input). If TEN is cleared, the UART will
not stop transmitting and the port pins will remain under the control of the UART until the end of the
transmission.
Request-to-Send (RTS) Output
The UART controls the RTS output under the following conditions:
Assertion conditions (active low):
• Receive-enable (REN in Control Register) is set.
• Receive operation has completed during receiver being enabled.
The timing of the RTS assertion from the last frame's stop bit is programmable.(see 'RST control
register' for detail)
Non-assertion conditions (inactive high):
• Falling edge of the start bit is detected during Receive-enable.
• Receive-enable (REN in Control Register) is cleared before receive operation is in progress.
• Hardware reset.
• Receiver of the UART is initialized (RIN is set).

UART

UART-79

Mitsubishi

M37640E8-XXXF Preliminary Specification

CTS (input)

TXD (output)

/
start

stop

RXD (input)

DATA

J...

DATA

programmable

\1/

start

DATA

RTS (output)

In both examples, the Transmit and Receive have already heen enabled

Figure 2-85. CTS and RTS TIming Example

2.12.9 UART Address Mode
The UART address mode is intended for use in a multi-receiver environment where an address is sent
before each message to designate which UART or UARTs are to wake-up and receive the message. An
address is identified by the MSB of the incoming data byte being a "1". The bit is ''0'' for non-address
data. UART address mode can be used in either 8-bit or 9-bit character length mode. The character
length is chosen by writing the appropriate values to the UART Character Length Selection Bits
(LEO,l).
UART address mode is enabled by setting the UART Address Mode Enable Bit (AME) to "1". When
UART address mode is enabled, the MSB of a newly received byte of data (that is either 8 or 9 bits
in length) is examined if a valid stop bit is detected and a parity error has not occurred (if parity is
enabled). If the MSB is "1", then the receive buffer full interrupt and flag are set and AME is
automatically cleared, disabling UART address mode. If the MSB is "0", then the receive buffer full
interrupt is not set. However, the RBF flag is still set for this case. If a valid stop bit is not detected
or a parity error has occurred, neither the receive buffer full flag nor interrupt is set and the MSB of
the data is not examined. Instead, either the framing error or parity error flag is set, the error sum flag
is set, and the error sum interrupt is set.
While in UART address mode, the generation of overrun errors is disabled after the first byte of data
is received. Therefore, when non-address data is received without errors while in the UART address
mode, it is not necessary to read the UART receive buffer prior to the reception of the next byte of
data. Also, if a framing or parity error occurs while in UART address mode, it is not necessary to
read the UxSTS prior to the reception of the next byte of data. However, an overrun error will occur
if an address byte is received and the UART receive buffer is not read before a new byte of data is
received. This is the case because the UART address mode was automatically disabled when the
address byte was received. Also, an overrun error will occur for the first byte received after UART
address mode is enabled if the preceding byte received did not generate an error and the UART
receive buffer was not read, or the preceding byte did generate an error and UxST~ was not read.

UART-SO

UART

J...

Mitsubishi

M37640E8-XXXF Preliminary Specification

When the MSB is "1" and the UART address mode is automatically disabled, the UART reverts back
to normal reception mode. In normal reception mode, the value of the MSB of each byte of received
data has no effect on the setting of the receive buffer full interrupt or the determination of overrun
errors.

2.13 Serial 110
Address

Acronym and
Value at Reset

Description

002A 16

SIO shift register

SIOSHT=XX

002B 16

SIO control register I

SIOCON I =00

002C 16

SIO control register 2

SIOCON2=OO

Name

SRDY

is multiplexed with P80

SCLK

is multiplexed with P81

SRXD

is multiplexed with P82

STXD

is multiplexed with P83

The SID uses the clock synchronous method (see Figure 2-86.).
• Transfer method: Half Duplex data transfer is available.
• Synchronous Clock
• Internal Clock (when serial I/O synchronous clock select bit is "I", internal clock source divided by
2, 4, 8, 16, 32, 64, 128, 256 can be selected). If bit 1 of SID Control Register2 is "0", internal
clock source == 4>; if bit 1 of SID Control Register2 is "I", internal clock source = SCS-GCLK
• External Clock (when SID synchronous clock select bit is "I", an external clock input from the
SCLK pin is selected).

2.13.1 SIO Control Register
The Serial I/O Control Register controls the various SID functions (see Figure 2-87.). All of this
register's bits can be read from and written to by software. At reset, this register is cleared to 00 16•
The SID Control Register determines whether the device's pins are used as ordinary I/O ports or as
SID function pins. This register also determines the transfer direction and transfer clock for serial data.

2.13.2 SIO Operation
An internal clock or an external clock can be selected as the synchronous clock. When the internal
clock is chosen, dividers are built in to provide eight different clock selections. If an internal clock is
selected, start of transfer is done by a write signal to the serial I/O register. After an 8-bit transfer is
completed, the TxD pin enters a high-impedance state. If an external clock is selected, the contents of
the serial I/O register continue to be shifted while the send/receive clock is being input. Therefore, the
clock needs to be controlled by the external source. Also there is no TxD high impedance function
after data is transferred.

Serial 110

Serial 110-81

Mitsubishi

M37640E8-XXXF Preliminary Specification

Regardless of an internal or external clock, after an 8-bit transfer, the interrupt request bit is set.
Figure 2-89. shows the timing for the serial I/O with the LSB-first option selected.
SIO can be operated in slave mode. In slave mode the SRDY pin becomes an input from a master. If
SRDY is held High, the shift clock is inhibited, STXD is tri-stated, and shift count is reset. If SRDY
is held Low, then the. normal shift operation is performed.
SRXD

STXD
~

"0
til

(I>

-1
)

SCLK

•

.P8I Latch

SRDY

•

SCSGCLK

+--

SRDY

P80Latch

)

) (

)

Data Bus
SIO Interrupt Request
Figure 2-86. Clock Synchronous SIO Block Diagram

Serial 110-82

Serial 110

J....

M37640E8-XXXF Preliminary Specification

Mitsubishi

~SB

OCHCont

SCSel

ISCSel0-2

TDSeI

RDYSel

PSel

ISCSe12

ISCSell

ISCSelO

I~SB

RDYSel

RDSel

SCSeI

OCHCont

Access: R/W
Reset:

Internal Synchronization Oock Select Bit
000: Internal Clock divided by 2.
001: Internal Clock divided by 4.
010: Internal Clock divided by 8.
011: Internal Clock divided by 16
100: Internal Clock divided by 32.
101: Internal Clock divided by 64
110: Internal Clock divided by 128.
111: Internal Clock divided by 256
SIO Port Selection Bit
0: 110 Port
I: TxD output, SCLK function
SRDY Output Select Bit
0: 110 Port.
I: SRDY signal
Transfer Direction Select Bit
0: LSB first.
I: MSB first.
Synchronization Clock Select Bit
0: External Clock.
I: Internal Clock.
TxD Output Channel Control Bit
0: CMOS output.
I: N-Channel open drain output.

PSel

Address: 002B 16
00 16

Figure 2-87. SIO Control Register 1

MSB
7

LSB

SLAVE

CLKSEL

RXDSeI

Address: 002C 16

Access: R/W
----~----~----~
Slave Mode Selection
Reset:
00 16
0: Normal mode
1: Slave mode (to enter Slave mode, bit 4 of SIO Control register 1 also needs to
set)
SIO Internal Oock Selection Bit
0:<1>
1: SCSGCLK
SRXD Input Selection Bit
0: SRXD input disabled

Figure 2-88. SIO Control Register 2
Synchronous Clock
Transfer Clock
SIO Re~ister
Write Signal
Receive Enable
Signal SRDY
SIOOutput
SIOInput

Note:

~..,;_ __
Interrupt Request Bit Set
When the internal clock is selected, the TxD pin goes into highimpedance after the data is, transferred.

Figure 2·89. Normal Mode SIO Function TIming (with LSB·First selected)

Serial 110

Serial 110·83

Mitsubishi

M37640E8-XXXF Preliminary Specification

J..

2.14 Special Count Source Generator
Description

Address
002D 16

Code

Special Count Source Generatorl

SCSGl=FF

002E 16

Special Count Source Generator2

SCSG2=FF

002F16

Special Count Source mode register

SCSM-OO

This device has a built-in special count source generator. It consists of two 8-bit timers: SCSGl, and
SCSG2 (see Figure 2-90.) The contents of the timer latch, corresponding to each timer, determine the
divide ratio. The timers can be written to at any time. The output of the special count source generator
can be a clock source for Timer X, SID and the two UARTs.
SCSGMO

SCSGMl
SCSGM3
SCSG 1 Reload Latch (8)
SCSGl (8)

SCSGM3

r -______________--.SCSGM2

SCSG2 Reload Latch (8)
SCSG2 (8)
SCSGM3
SCSGCLK

(To UARTs, TlDler X and SIO)
Figure 2-90. SCSG Block Diagram

2.14.1 SCSG Operation
The SCSGI and SCSG2 are both down count timers. When the count of a timer reaches 00 16, an
underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are
loaded into the timer. For the count operation for SCSGI with the Data Write Mode set to write to
the latch only see (Figure 2-91.).
A memory map and the initial values after reset of the timers and timer reload latches are detailed
above. The divide ratio of each timer is given by 1/(n + 1), where n is the value written to the timer.
The output of the frrst timer (SCSGl) is effectively ANDed with the original clock (~) to provide a
count source for the second timer (SCSG2). This results in a count source of nI(n + 1) being fed to
SCSG2.
The output of the SCSG is a clock, SCSGCLK. The frequency is calculated as follows:
SCSGI
1
SCSGCLK = <1>. SCSGI + 1 • SCSG2 + 1 where SCSGI is the value written to SCSGI and SCSG2 is

the value written to SCSG2.

Special Count Source Generator-84

. Special Count Source Generator

M37640E8-XXXF Preliminary Specification

Mitsubisbi

Count Source

SCSG 1 Contents
SCSG 1 Underflow
m

SCSG I Latch Contents

SCSG I reload latch contents loaded into SCSG I
Figure 2-91. Timer Count Operation for SCSG1

2.14.2 SCSG Description
2.14.2.1

SCSGI

SCSG I is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer.

Write Method
When writing to the timer, the data is placed in the SCSGI reload latch. At this point, if the SCSGI
Data Write Control Bit (SCSGMO) is "0", the value in the SCSGI reload latch is also loaded in
SCSGI. If SCSGMO is "I", the data in the SCSGI reload latch is loaded in SCSGI after SCSGI
underflows.

SCSG1 Count Stop Control
If the SCSGI Count Stop Bit (SCSGMl) (bit 1 of the SCSGM Register) is set High, SCSGI stops
counting. This allows to bypass SCSG 1 and act as the clock source for SCSG2. If the SCSGCLK
Output Control Bit (SCSGM3) is cleared to "0", SCSGCLK is disabled and SCSGI stops counting (see
Figure 2-92.).

2.14.2.2

SCSG2

SCSG2 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer.

Write Method
When writing to the timer, the data is placed in the SCSG2 reload latch. At this point, if the SCSG2
Data Write Control Bit (SCSGM2) is Low, the value in the SCSG2 reload latch is also loaded in
SCSG2. If SCSGM2 is High, the data in the SCSG2 reload latch is loaded in SCSG2 after SCSG2
underflows.
MSB

LSB

______~____~____~____~O

7
SCSGMO

SCSGMI

SCSGM2

SCSGM3

SCSGM7-4

SCSGl Data Write Control Bit (Bit 0)
0: Write data in latch and timer
I: Write data in latch only
SCSGl Count Stop Bit (Bit I)
0: Count start
I: Count stop
SCSG2 Data Write Control Bit (Bit 2)
0: Write data in latch and timer
I: Write data in latch only
SCSGCLK Output Control Bit (Bit 3)
0: S.CSGCLK output disabled (SCSGI and SCSG2 off)
I: SCSGCLK output enabled.
Not used (zero when read)

Address: 002F 16
Access: RIW
Reset:
00 16

Figure 2-92. SCSGM Register

Special Count Source Generator

Special Count Source Generator-85

M37640E8-XXXF Preliminary Specification

Mitsubisbi

SCSG2 Count Stop Control

If the SCSGCLK Output Control Bit (SCSGM3) is cleared to "0", SCSGCLK is disabled and SCSG2
stops counting.
SCSG2 Output (SCSGCLK)
The output signal SCSGCLK (output to the UART and Timer blocks) is controlled by SCSGM3. When,
the SCSGCLK Output Control Bit (SCSGM3) is cleared to "0", SCSGCLK is disabled.

2.15 Oscillator Circuit
2.15.1 Description
An on-chip oscillator provides the system and peripheral clocks as well as the USB clock necessary for
operation. This oscillator circuit is comprised of amplifiers that provide the gain necessary for '
oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. A block
diagram of the oscillator circuit is shown in Figure 2-94. The following external clock inputs are
supported:
• A Ceramic resonator or quartz crystal oscillator of up to 48 MHz, connected to the
pins.

and Xout

• An external clock signal of up to 48 MHz, connected to the Xin pin.
• A Ceramic resonator or quartz crystal oscillator of 32.768 kHz, connected to the XCin and XC out
pins.
• An external clock signal of up to 5.12 MHz, connected to the XCin pin.
The frequency synthesizer can be used to generate a 48MHz clock signal (fUSB ) needed by the USB
block and clock fSYN' which can be chosen as the source for the system and peripheral clocks. Both
fUSB and fSYN are phase-locked frequency multiples of the frequency synthesizer input The inputs to
the frequency synthesizer can be either Xin or XCin•
One of three clock signals can be chosen as the source for the system and peripheral clocks; fXINI2,
fXIN ' fXCIN ' or fSYN ' The selection is based on the values of bits CPMA6, CPMA7 and CCR7. The
default source after reset is f x1N/2.
The default source for the system and peripheral clocks is fXJN/2. If fXIN - 24MHz, then the CPU will
be running at = 6MHz Oow frequency mode.) For the CPU to run in high frequency mode, i.e.,
source of clock - fxlN , write a "1 ", to bit 7 of the clock control register.

Oscillator Circuit-86

Oscillator Circuit

J...

Mitsubishi

M37640E8-XXXF Preliminary Specification

MSB

LSB

Address: 00lF I6

7
CCR7:

CCR6:

CCR5:

CCR4:

Access: RIW
Reset:
00 16
X IN Divider Select
0: fXJN/2 is used for the system clock source when CMPA7:6-00
I: fXIN is used for the system clock source when CMPA7:6-00
"our Oscillation Drive Disable bit
0: Xour oscillation drive is enabled (when Xin oscillation is enabled).
I: XOtIT oscillation drive is disabled.
Xcour Oscillation Drive Disable Bit
0: Xcour oscillation drive is enabled (when XCin oscillation is enabled).
I: XCOtIT -oscillation drive is disabled.
frequency synthesizer Bypass
0: 48MHz USB clock is from the Frequency Synthesizer.
I: 48MHz USB clock is from the Xu/Xout pins.

Figure 2·93. Clock Control Register

The drive strength of the Xout and XCout inverting amplifier can be controlled by bits CPMB7 and
CPMA3, respectively. High drive is the default at reset or after executing a STP instruction and must
be chosen whenever restarting Xin or XCin oscillation if a ceramic or crystal oscillator is used. When
oscillation has been established, low drive can be selected to reduce power consumption. If an external
clock signal is input to Xin or XCin, the inverting amplifiers can be disabled by means of the CCR6
and CCR7 bits, respectively, in order to reduce power consumption.
There is an option to bypass the frequency synthesizer and use a 48MHz crystal on Xin - Xout to
provide f USB ' This can be done by writing "1" to CCR4. Note that, in this mode, CCR7 must be set
Low.

OsciUator Circuit

Oscillator Circuit·87

Mitsubishi

M37640E8-XXXF Preliminary Specification

1...

RESETB

P2T

P2 Peripheral_-=--:-;t-:-"""""'-"-'---'
P I Peripheral

Peripheral

r---------~R

I Peripheral

Interrupt Request
I Flag

WIT S

OSCSTP

CPMA4
XCOOSCSTP

P2+ T

CPMA5
XOOSCSTP

Out nout
lOut

PIN2

PINI, P1N2

r.;:::::====::::;---'

g~B~

Slow Memory Wait

PI+,P2+

CPMB2

CPMB3~--~--------'

RDY

fEXT

USB 48MHz clock

Figure 2-94. Clock Block Diagram

Oscillator Circuit-88

Oscillator Circuit

Mitsubisbi

M37640E8-XXXF Preliminary Specification

2.15.2 Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz clock needed by the USB block and a clock
fSYN that are both a multiple of the external input reference clock fIN' A block diagram of the circuit
is shown in Figure 2-95 ..
Frequency
Multiplier

Frequency

fveo

fSYN

Divider

Figure 2-95. Frequency Synthesizer Circuit

The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider
macro, and four registers, namely FSMI, FSM2, FSC and FSO. Two multiply registers (FSMI, FSM2)
control the frequency multiply amount. Clock fIN is prescaled using FSM2 to generate fpIN . fpIN is
multiplied using FSMI to generate an fvco clock that is then divided using FSO to produce the clock
fSYN ' The fvco clock is optimized for 48 MHz operation and is buffered and sent out of the
frequency synthesizer block as signal f USB ' This signal is used by the USB block.
Clock fPIN is a divided down version of clock fIN, which can be either· fXIN or fXCIN ' The default
clock after reset is f XIN ' The relationship between fPIN and the clock input to the prescaler (fIN) is as
follows:
• fPIN - fIN I 2(n+l) where n is a decimal number between 0 and 254 (TBO). Setting FSM2 to
255 disables the prescaler and fPIN = fIN'

~S'

Bit 7

Bit 6

BitS

Bit 4

Bit 3

Bit 2

Bit 1

Dec(n)

Access: WIR

Reset:

FSM2
fPIN

Address: 006E 16

Hex(n)

FF16

fIN

24 MHz

255

24.00 MHz

1 MHz

24.00 MHz

2 MHz

24.00 MHz

3 MHz

24.00 MHz

6 MHz

24.00 MHz

12 MHz

24.00 MHz

tIN{.l(n+l) - fPIN

Figure 2-96. Frequency Synthesizer Multiply Control Register FSMl

Oscillator Circuit

Oscillator Circuit-89

Mitsubishi

M37640E8-XXXF Preliminary Specification

SBI

Bit 7

Bit 2

Bit 6

Bit 5

fPIN

Decimal (n)

320kHz

48.00 MHz

2 MHz

48.00 MHz

4 MHz

48.00 MHz

6 MHz

48.00 MHz

12 MHz

48.00 MHz

24 MHz

48.00 MHz

Bit 4

Bit 3

Bit I

Bit 0

Address: OO6D I6
lJSB Access: WIR
Reset:

Hex

FF 16

fyeo

FSMI

FSM2

J....

lyed~(n+l) - lplN

Figure 2-97. Frequency Synthesizer Multiply Control register FSMI

~SBI

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

fveo

FSD(m)

DeclmaI

fsyu

48.00 MHz

24.00 MHz

127

187.50 kHz

48.00 MHz

7F
Yed2(m+l) -

Bit 0

LSB Address: 006F 16
Access: WIR
Reset:

FFI6

SYN

Figure 2·98. Frequency Synthesizer Divide Register

The relationship between fPIN' fyeo, and fSYN is as follows:
• fyeo
Note:

fPIN x 2(n+l) where n is the decimal equivalent of the value loaded in FSM2,FSMl.

n must be chosen such that fyeo equals 48 MHz.

• fSYN - fyeo / 2(m+l) where m is the decimal equivalent of the value loaded in FSD
Note:

Setting m ... 255 disables the divider and negates fSYN'

The FSCO bit in the FSC Control Register enables the frequency synthesizer block. When disabled
(FSCO ... zero), fyeo is held at either a high or low state. When the frequency synthesizer control bit
is active (FSCO - one), a lock status (LS == one) indicates that fSYN and fyeo are the correct frequency. The LS and FSCO control bits in the FSC Control register are shown in Figure 2-99.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.

Oscillator Circuit·90

Oscillator Circuit

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

Bit 6

BitS
FSCO

VCOI,O

Bit 3

Bit 4>
Bits 6,5>

F_l:1

Bit 3

I VCOI

VCOO

FSCO

Frequency Synthesizer Enable Bit
0: Disabled
I: Enabled
Frequency Gain Control Bits
00: TBD
01: TBD
10: TBD
11: TBD
Frequency Synthesizer input selector
0: Xin
I: XCin
Not used (Always write 0)
LPF Gain Control Bits
00: 00 NOT USE
01: Valid in-lock stale
10: Valid in-lock stale
1J: During lock-in state
Lock StalUS Bit
0: Unlocked
I: Locked

I~SB

Address: 006C 16
Access: WfR
Reset: 60 16

Figure 2-99. Frequency Synthesizer Control Register

2.16 Low Power Modes
This device has two low-power dissipation modes:
• Stop
• Wait.

2.16.1 Stop Mode
Use of the stop mode allows the microcomputer to be placed in a state where no internal excitation of
the circuitry is taking place, thus resulting in extremely low power dissipation. The microcomputer
enters the stop mode when the STP instruction is executed. The internal state of the microcomputer
after execution of the STP instruction is as follows:
• All internal oscillation stops with P2 and P2PER held High and PI and PIPER held Low.
• Timer 1 and Timer 2 are loaded with FF16 and 01 16 respectively.
• The count source for Timer 1 is set to Cl>/8 and the count source for Timer 2 is set to Timer 1
underflow.
Oscillation is restarted (for example, all clocks other than PI and P2 begin to oscillate) when a reset
or an external interrupt is received. The interrupt control bit of the interrupt used to release the stop
mode must be set High and the I flag set Low prior to the execution of the STP instruction. To allow
the oscillation source time to stabilize, the oscillation source is connected as the clock source for the
wake-up timer (Timer 1 and Timer 2 cascaded). When Timer 2 underflows, the system clocks PI and
P2 are restarted and the microcomputer services the interrupt that caused the return from the stop state.
It then services any other enabled interrupts that occurred, in the order of their respective priorities, and
returns to its state prior to the execution of the STP instruction. The timing for the STP instruction is
shown in Figure 2-100.

Low Power Modes

Low Power Modes-91

Mitsubishi

M37640E8-XXXF Preliminary Specification

J...

PIPER :
P2PER '

IN1REQ:
•,
STPSIG·

CPUOSC:

SYNCout :

_.
RD

'
WR·

Address

PC+I

Invalid

,+-+1
Sleep Period

Start of Interrupt Service
Timer Countdown
Routine
(Oscillator stabilization) Tuner 2 underflow

Note: Return from a STP Instruction is caused by an interrupt, followed by the countdown and underflow of Tuner 2

Figure 2-100. STP Cycle Timing Diagram

2.16.2 Wait Mode
Use of the wait mode allows the microcomputer to be placed in a state where excitation of the CPU
is stopped, but the clocks to the peripherals continue to oscillate. This mode provides lower power
dissipation during the idle periods and quick wake-up time. The microcomputer enters the wait mode
when the WIT instruction is executed. After the instruction execution, P2 is held High and PI is held
Low.
Returning from wait mode is accomplished just as it is when· returning from stop mode, with the
exception that you need not provide time for the oscillator to stabilize, because the oscillation never
stopped. Because PIPER and P2PER continue to oscillate in the wait mode, any peripheral interrupt
can be used to bring the microcomputer out of the wait mode. The timing for the WIT instruction is
shown in Figure 2-101.

Low Power Modes-92

Low Power Modes

J...

Mitsubishi

M37640E8-XXXF Preliminary Specification

,
PIPER,
P2PER
~EQ

S1PSIG
SYNCout

,
'~j_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~--~~

,
'~j_ _ _ _ _ _ _ _ _ _ _ _ _ _- - - '

~~----------------~----------------------------~

RD~

WR:'------------------~--~------------~L_J

BC+ I

Address ,
Data '

Invalid

Note: Return ~m a WIT instruction is caused by an interrupt.

,....-..

Sleep Period

Start of Interrupt

Figure 2-101. WIT Cycle Timing Diagram

2.17 Reset
This device is reset if the RESET pin is held Low for a minimum of 2J.1.S while the supply voltage is
between 4.5 and 5.5Volts. When the RESET pin returns High, the reset sequence commences (see
Figure 2-102.) To allow the oscillation source the time to stabilize a delay is generated by the
countdown of Timer 1 and Timer 2 cascaded with FF 16 loaded in Timer 1 and 01 16 loaded in Timer
2. After the reset sequence completes, program execution begins at the address whose high-order byte
is the contents of address FFFA 16 and whose low-order byte is the contents of address FFFB 16•

PI
P2
Reset
SYNCout
Address

..J
---~---~~~~~==~~~~==~~~~

Data
Timer countdown from 0 IFF l6

Figure 2-102. Internal Processing Sequence after RESET

Reset

Reset-93

M37640E8-XXXF Preliminary Specification

Mitsubishi

2.18 Key-On Wake-Up
This device contains a key-on wake-up interrupt function. The key-on wake-up interrupt function is one
way of returning from a power-down state caused by the STP or WIT instructions. This interrupt is
generated by applying Low level to any pin of Port 2. If a key matrix is connected as shown in
Figure 2-103., the microcomputer can be returned to a normal state by pressing anyone of the keys.
Port PXX

L level output from arbitrary port Xx
Key-on
wake up
Interrupt

Request

,
~output

~output:

P2s output:

,
-LP20inp~t
Off Chip

, On Chip

Figure 2-103. Port 2 with Key-ON Wake-Up Function

Key-On Wake-Up-94

Key-On Wake-Up

~ MITSUBISm SEMICONDUCTOR
. . . AMERICA, INC.

Chapter 3
Electrical
Characteristics

3.1 Absolute Maximum Rating ..... 97
3.2 Recommended Operating
conditions .................. 97
3.3 Electrical Characteristics ...... 99

M37640E8-XXXF Preliminary Specification

Mitsubishi

J...

J....

M3764OE8-XXXF Preliminary Specification

Mitsubisbi

3 Electrical Characteristics
3.1

Absolute Maximum Rating
Table 3-1. Absolute Maximum Rating

Symbol

Conditions

Parameter

Unit

Limits

Vee

Power Supply

-0.3 to 7.0

Input Voltage PO, PI, P2, P3, P4, P5, P6, P7, P8

-0.3 to Vcc + 0.3

Input Voltage RESET, Xm, XCin

Input Voltage CNVSS

Values are with respect to -0.3 to Vcc + 0.3
V8S' output transistors are in -0.3 to 13
off state.
-0.3 to Vcc + 0.3

Output Voltage PO, PI, P2, P3, P4, P5, P6, P7, P8, Xout'
XCout
Power Dissipation

Topr

Operating Temperature

Tstg

3.2

V
SV
mW

750

Ta-25°C

°c

-20to+85°C

-40 to +125°C

Storage Temperature

°c

Recommended Operating conditions
Thble 3-2. Recommended Operating Conditions (Vc:c Symbol

4.5 to s.sv, Vss - OV, Ta - -20 to SSOC, unless otherwise noted)

Limits

Parameter

Vee
Vss
Vih

Supply voltage
Supply voltage
H input voltage

Vih

H input voltage

Vii

L input voltage

Vii

L input voltage

101 (peak)

L peak output current Note 1

101 (avg)

L average output current Note 2

lob (peak)

H peak output current Note 1

lob (avg)

H average output current Note 2

Absolute Maximum Rating

Min. Typ. Max.
4.5

5.5

Vee

0.2Vcc

rnA

-10

rnA

-5

rnA

RESET, Xin' XCin, CNVSS
PO,PI,P2,P3,P4,P5,P6,P7,
0.8Vcc
P8
PO, PI, P2, P3,P 4, P5, P6, P7,
0
P8
RESET, Xin, XCin, CNVSS
0
0.8Vcc

PO,PI, P2, P3, P4, P5, P6, P7,
P8
PO~ PI, P2, P3, P4, P5, P6, P7,
P8
PO, PI, P2, P3, P4, P5, P6, P7,
P8
PO, PI, P2, P3, P4, P5, P6, P7,
P8

Unit

Absolute Maximum Rating-97

M37640E8-XXXF Preliminary Specification

Mitsubishi

Table 3·2. Recommended Operating Conditions (Va: Dol (peak

L total peak OUtput current

Note 3

L total average output current

Dol (avg) Note 4
Doh

(peak)

PO,P I, P2, P3, P4, P5, P6, P7,
P8

PO, PI, P2, P3, P4, P5, P6, P7,
P8

H total peak output current Note 3

Symbol

4.5 to S.5V, Vss - OV, 1'8 - -20 to 85°C, unless otherwise noted)

PO, PI, P2, P3, P4, P5, P6, P7,
P8

H total average output current

PO, PI, P2, P3, P4, P5, P6, P7,
P8

f(CNTRO TnnerX - input frequency ",ote ;>
f(CNTRI TnnerY - input frequency Note ~
Clock frequency ",ote ;>
f(Xin)
f(XC in)

rnA

-80

rnA

Limits
Min. Typ. Max.

Parameter

Doh (avg) Note 4

80 .

Oock frequency Note ~

Unit

-40

rnA

2.6

MHz

2.6

MHz

TBD

MHz

Note 1. The peak output current is the peak current flowing through any pin of the listed ports.
Note 2. The average output current is an average current value measured over lOOms.
Note 3. The total peak output current is the peak current flowing through all pins of the listed ports.
Note 4. The total average output current is an average value measured over lOOms.
Note 5. The oscillation frequency has a 50% duty

Recommended Operating conditions·98

cycle~

Recommended Operating conditions

J...

M37640E8-XXXF Preliminary Specification

Mitsubishi

3.3

Electrical Characteristics
Table 3-3. Electrical Characteristics (Vec - 4.5 to 5.5Y, VIS - OV, Ta - ·20 to 8S°C, unless otherwise noted)

Symbol
Voh

Houtput
current

PO, PI, P2,P3, P4,PS, P6, P7, P8

Ioh ... -IOmA

Vol

Loutput
current

PO,PI,P2,P3,P~PS,P6,P7,P8

Iol--IOmA

Vt+
-Vt-

Iih

Hysteresis

H input current

Limits

Test Conditions

Parameter

Min Typ. Max Unit
Va;-

2.0

CN1RO, CN1RI, INTO, INTI
URXDl, URXD2 (SCLK), CTS2 (SRXD),
SRDY, CTSI, CN1RO, CN1RI, INTO,
INTI
RESET
PO, PI, P2, P3, P4, PS, P6, P7, P8
V i-Vee
CNVSS, RESET

P2
IiI

Vram

L input current

RESET, CNVSS
Xin
XCin

RAM
retention
voltage

0.5

V
V

5
4
4

Vi-V ss
Vi ... Vss (Pullups oft)

-5
-5

Vcc - 5V, Vi = Vss (PuIlups on)

-70

Vi-Vss

-4

-5
-4

with stopped clock

Normal Mode

XCin

0.5

Xm
PO,PI,P3,P~PS,P6,P7,P8

2.0

5.5

IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
IJA
V

«I>-12MHz, Vcc .. SV, USB
operating,
frequency synthesizer on

150

«I> - 12MHz, Vcc = 5V, USB
suspend,
frequency synthesizer on

TBO

«I> - 12MHz, WIT mode, Vcc'" 5V,
USB operating, frequency
synthesizer on

TBO

«I> ... 12MHz, WIT mode, Vcc - 5V,
USB suspend, frequency
synthesizer on

TBO

«I>-12MHz, WIT mode, Vcc ·5V,
USB suspend, frequency
synthesizer off

TBO

«1> ... 12MHz, Vcc'" 5V, USB

Icc

suspend,
frequency synthesizer off

Supply current
(Output
transistors are
in off state)
Wait Mode

Stop Mode

Electrical Characteristics

Ta ... 25°C, Vcc - 5V
Ta'" 85°C, Vcc ... 5V

0.1

IJA
IJA

Electrical Characteristics-99

Mitsubishi

M37640E8-XXXF Preliminary Specification

J..

Table 3-4. Master CPU Bus Interface Tuning (R and W Separation Type Mode)

Limits
Symbol

Parameter

Unit
Min.

Typ.

Max.

1su(S-R)

S Set-up TIme

Isu(s-W)

S Set-up Tune

th(R-S)

SHoldTune

!J.(W-S)

SHoldTune

!su(A-R)

AO Set-up Tune

Isu(A-W)

AO Set-up Tune

th(R-A)

AOHoldTune

th(W-A)

AOHoldTune

1w(R)

Read Pulse Width

1w(W)

Write Pulse Width

1su(D-W)

Dale Input Set-up Tune before Write

!J.(W-O)

Dale Input Hold TIme after Write

Ia(R-O)

Data Output Enable TIme after Read

"40

!,,(R-O)

Data Output Disable Tune after Read

IpIh(R-OBF)

OBP Output Transmission Tune after Read

IpIh(W-mF)

mF Output Transmission Tune after Write

Table 3·5. Master CPU Bus Interface TIming (RIW Type Mode)
Symbol

Limits

Parameter

Unit
Min.

Max.

Isu(s-E)

S Set-up TlDle

!J.(E-S)

SHoldTlDle

Isu(A-E)

AO Set-up TlDle

!J.(E-A)

AO Hold TlDle

RiW Set-up TlDle
" RIW Hold TIlDe

1su(Rw-E)

1w(E)

Enable pulse width

1w(E-E)

Enable pulse interval

1su(D-E)

Dale Input Set-up TlDle before Write

!J.(E.O)

Date Input Hold TlDle after Write

Ia(E..O)

Data Output Enable TlDle after Read

Iv(E-O)

Data Output Disable TlDle after Read

IpIh(E-OBF)

OBP Output Transmission Tune after I!
inactive

!J.(E.RW)

lpJh(E-mF)

Note:

Typ.

mF Output Transmission Tune after B
inactive

The timing information listed above is Nor derived from the device characterization, it is
for reference only.

Electrical Characteristics·tOO

Electrical Characteristics

J...

Mitsubishi

M37640E8-XXXF Preliminary Specification

Read

lsu(A R)
1t.(R-A}

1t.(R-S}

lsu(S-R}

r-+

lw(R)

.......

A
'I..

ta(R-D)

lv(R-D)

++I

lplh(R-OBF)

OBF

Write

1t.(W-A}

lsu(A-W)

D<
Is~

1t.(W-S}

~
"I

lw(W)

w
lsu(D-W)

1t.(W-D}
lI.
I

...

lplh(W-IBF) .1

Figure 3-104. Master CPU Bus Interface RD and WR Separation Type

Electrical Characteristics

Electrical Characteristics-10l

Mitsubishi

M37640E8-XXXF Preliminary Specification

J...

lw(E)

E
tsu(A-E)

\i;u(A-E)

RIW
\i;u(S-E)

Read

la(E..D)

Write

__________________________________________

lplh(E_OBF)
~lplh(E-IBF)

OBF,IBF

Figure 3-105. Master CPU Bus Interface RIW Type

Electrical Characteristics~102

Electrical Characteristics

~ MITSUBISm SEMICONDUCTOR
. . . . AMERICA, INC.

Chapter 4
Application Notes

4.1 DMAC .. . . . . . . . . . . . .. 105
4.2 UART. . . . . . . . . . . . . . .. 106
4.3 Timer . . . . . . . . . . . . . . .. 106
4.4 Frequency Synthesizer
Interface ............. 107

M37640E8-XXXF Preliminary Specification

Mitsubishi

J....

Mitsubishi

M37640E8-XXXF Preliminary Specification

4 Application Notes
4.1

DMAC

4.1.1

Programming

The following Programming notes should be adhered to for correct DMA operation:
• When using the software trigger to initiate a transfer request and the hardware requests are
enabled (for example, RSD is zero), the user should follow the sequence given below:
• Disable the hardware requests by setting RSD to one.
• Trigger the software request and re-enable the hardware requests at the same time (for example,
using the same assembly instruction) by writing a zero to RSD and a one to DSWT.

4.1.2

Application

The following is an example of how to set up the DMAC for interfacing with a peripheral block. In
this case data is being transferred by the DMAC from the UART receive buffer to user RAM.
• Write 08 16 to DMAMI so that after each transfer the destination register will be decrements by
one and the source register will remain unchanged.
• Write 00 16 to the low-order byte of the destination register (DMADL) and 03 16 to the high-order
byte of the destination register (DMADH) so that the data received by the UART is placed in
page three of the user RAM starting from address 0300 16,
• Write 3C 16 to the low-order byte of the source register (DMASL) and 00 16 to the high-order byte
of the source register (DMASH) so that the DMA reads from address OO3C 16, which is the loworder byte of the UART receive buffer.
• Write to the transfer count register (DMAC) with an 8-bit value that corresponds to the number
of transfers to occur before flag CRUF and the DMA interrupt are set.
• Set the DMA transfer initiating source to the UART receive interrupt by writing 00 16 to DMAM2.
• Place the UART in the desired configuration for data reception by writing to the UART control
(UCON), UART mode (UMOD), and UART baud rate (UBRO) registers.
• Disable the UART receive interrupt from being serviced by the CPU by clearing to a. zero bit 4
of interrupt control register A (ICONA).
• Enable the DMA interrupt by setting bit 3 of ICONA to one.
• Enable the DMA controller and reset the initiating source sample latch by writing C8 16 to DMAMI.
The DMA controller will transfer one byte of data from the UART receive buffer to third page user
RAM each time that the UART receive interrupt is set. Because the destination register is incremented
by one after each transfer, third page user RAM is contiguously filled with received data.
The transfer count register is decrements by one after each transfer. When it underflows, flag CRUF
and the DMA interrupt are set. In the DMA service routine, the user can either write new values to
the source, destination, and transfer count registers, or leave these registers untouched. If they are left

DMAC

DMAC-I05

Mitsubishi

M37640E8-XXXF Preliminary Specification

J...

untouched, then they contain the previously written values that were reloaded when the transfer count
register underflowed. This would result in the previously transferred UART data in third page user
RAM being overwritten with newly received UART data.

4.2
4.2.1

UART
Application
• 7 bit operation:
When 7 bit data fonnat is used, bit 7 of the transmit buffer register 1 is ignored. The transmit buffer register 2 does not affect the 7 or 8 bit fonnat.
• 9 bit operation:
The upper transmit/receive buffer register is a single bit register (bit 0). Writing to the upper bits in these
registers has no affect When reading the register the upper 7 bits are zero.
Note:

4.3
4.3.1

The value in UBRG is not affected by a reset

Timer
Usage
• For Timer X, if CNTRO is read while Pulse Output mode is being used, the value returned is the
pulse output signal fed from the timer to the port
• For Timer Y, if CNTRI is read while Pulse Output mode is being used, the value returned is the
pulse output signal fed from the timer to the port.
• For TlDler 1, if Tout is read while Pulse Output mode is being used, the value returned is the
pulse output signal fed from the timer to the port

Thble4-1.
Selection Bit

Timer

TlDlerY CNlR 1 Polarity Select Bit (fXM6)

0: LogicH
1: LogicL

TlDlerX CNlRO Polarity Select Bit (fXM6)

0: Logic H
1: LogicL

TImer 1

UART-I06

Initial Output Value

Tout Output Active Edge Selection Bit
(T123M5)

0: LogicH
1: LogicL

UART

J....
4.4

M37640E8-XXXF Preliminary Specification

Mitsubishi

Frequency Synthesizer Interface
All passive components should be in close proximity to pin 86 n 1hat may

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appear in this pub1ic:ation. Mitsubishi Semiconductor America, Inc reserves the right. without
notice. to make changes in device design or spedf1C8lions. Product subject to availability.

GDI997 Mitsubishi Semiconductors Inc.
Mitsubishi Semiconductor America is a wholly owned subsidialy ofMitsubishi Electric
Infonnation supplied by Mitsubishi Semiconductor America Inc. is believed 10 be acauate and

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