M68000_Family_Reference_1988 M68000 Family Reference 1988

User Manual: M68000_Family_Reference_1988

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FR68KID

M68000

FAMILY
REFERENCE

MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
any liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola and ® are registered trademarks of Motorola, Inc. Motorola, Inc.
is an Equal Employment Opportunity/Affirmative Action Employer.
Motorola, Inc. general policy does not recommend the use of its components in
life support applications wherein in failure or malfunction of the component may
directly threaten life or injury. Per Motorola Terms and Conditions of Sale, the user
of Motorola components in life support applications assumes all risks of such use
and indemnifies Motorola against all damages.

Printed in U.S.A.

MOTOROLA'S M68000 .FAMILY

SELECTOR· GUIDE
PROCESSORS
COPROCESSORS
DMA CONTROLLERS
DATA COMMUNICATION DEVICES
NETWORK DEVICES
GENERAL-PURPOSE PERIPHERAL DEVICES

MECHANICAL DATA

lEI

1m
DEVELOPMENT SYSTEMS ID
TECHNICAL SUPPORT

MOTOROLA'S M68000 FAMILY
SELECTOR GUIDE
PROCESSORS
COPROCESSORS
DMA CONTROLLERS
DATA COMMUNICATION DEVICES
NETWORK DEVICES
GENERAL-PURPOSE PERIPHERAL DEVICES
MECHANICAL DATA
•

TECHNICAL SUPPORT

III DEVELOPMENT SYSTEMS

TABLE OF CONTENTS
Page

Number
SECTION 1 -

MOTOROLA'S M68000 FAMILV

SECTION 2 -

SELECTOR GUIDE

SECTION 3 -

MICROPROCESSOR

MC68000 MC68HCOOO
MC68008 MC68010 MC68020 MC68030 SECTION 4 -

16-/32-Bit Microprocessor ................................ ".............................
- Low Power HCMOS 16-/32-Bit Microprocessor ....... ;......................
16-Bit Microprocessor with 8~Bit Data Bus.......................................
16-/32-Bit Virtual Memory Microprocessor.......................................
32-Bit Virtual Memory Microprocessor............................................
Second Generation 32-Bit Enhanced Microprocessor..........................
COPROCESSORS

MC68851 MC68881 MC68882 SECTION 5 -

32-Bit Paged Memory Management Unit ..... '.................... ...... ..........
HCMOS Floating-Point Coprocessor................................................
HCMOS Enhanced Floating-Point Coprocessor..................................

MC68153
MC68230
MC68452
MC68901

Bus Interrupter Module................................................................
Parallel Interface/Timer ................................................................
Bus Arbitration Module................................................................
Multi-Function Peripheral.............................................................

8-1
8-17
8-33
8-40

MECHANICAL DATA

M68000 FAMILY

REFERENCE

7-1
7-27
7-29
7-35
7-61
7-76
7-78
7-105

GENERAL-PURPOSE PERIPHERAL DEVICES

SECTION 9 -

6-1
6-27
6-53

NETWORK DEVICES

MC68184 - Broadband Interface Controller......................................................
MC68185 - Twisted-Pair Modem ...................................................................
MC68194 - Carrierband Modem....................................................................
MC68605 - X.25 Protocol Controller...............................................................
MC68606 - Multi-Link LAPD Protocol Controller................................................
MC68606ESP - Evaluation and Support Package for the MC68606........................
MC68824 - Token-Passing Bus Controller.. ........................................ ........ ......
MC68KTBFA - Token Bus Frame Analyzer Software..........................................
SECTION 8 -

5-1
5-30

DATA COMMUNICATION DEVICES

MC2681 - Dual Asynchronous Receiver/Transmitter..........................................
MC68652/MC2652 - Multi-Protocol Communications Controller............................
MC68681 - Dual Asynchronous Receiver/Transmitter................................ .........
SECTION 7 -

4-1
4-33
4-61

DMA CONTROLLERS

MC68440/MC68442 - Dual-Channel Direct Memory Access Controllers.. ................
MC68450 - Direct Memory Access Controller...................................................
SECTION 6 -

3-1
3-20
3-38
3-62
3-86
3-108

MOTOROLA

iii

TABLE OF CONTENTS (Continued)
Page
Number
SECTION 10 -

TECHNICAL SUPPORT

10.1 Literature.................... ....... .............. ...... ... ............ .... ..... ... ...... .... ......... 10-1
10.2 Technical Training ................................................................................ 10-3
10.3 Motorola Sales Offices .......................................................................... 10-8
SECTION 11 -

11-2

DEVELOPMENT SYSTEMS

11.1 Host Systems ..................................................................................... .
11.1.1 M68DVLP Host Computer System ....................... .' .............. ~ ............
11.1.2 VAX Host System ........................................................................
11.1.3 Macintosh Host System ........................................... , .....................
11.1.4 SUN-3 Host System ........................................................... ~.~., .....
11.2 HDS-300 Control Station ........................................................................
11.2.1 Real-Time Bus Analysis ................................................................
11.2.1.1 Bus State Monitor ..................................................................
11.2.1.2 System Performance Analyzer ..................................................
11.2.2 User Interface..........................................................................
11.2.3 HDS-300 asa Test Tool ...................................... ~ .......................
11.3 In-Circuit Emulation ..............................................................................
. 11.3.1 16-Bit Emulators: MC68000, MC68HCOOO, MC68008, MC68010 ..............
11.3.2 32-BitEmulator: MC68020 ................................................. : ..............
11.3.3 32-Bit Emulator: MC68030 .............................................................
11.4 Development·Software ..........................................................................
11.4.1 Source-Level Debug.....................................................................
11.4.2 Cross-Support Software ............................................................ ~ ..
11.5 Part Numbers ................................ ·.......... ·.............................................

MOTOROLA

11-2
11-3
11-3
11-3
11-3
11-4
11-4
11-5
11-5
11-5
11-6
11-6
11~7

11 ~7
11-9
11-9
11-10
11-10

M68000 FAMILY

REFERENCE

MOTOROLA'S M68000 FAMILY

SECTION 1
MOTOROLA'S M68000 FAMILY
In this manual, descriptions of the devices in the M68000 Family are grouped in six. categories.
The processor group includes 8-, 16-, and 32-bit microprocessors, all using 32-bit internal architecture with 17 general-purpose data and address registers. The coprocessor group includes
memory management and floating-point coprocessors. The direct memory access (DMA) controller group, the data communication device group, the network device group, and the generalpurpose peripheral device group complete the M68000 Family.
The MC68000 is the original microprocessor unit (MPU) of the M68000 Family. It has a 16-bit data
bus and many flexible addressing modes. With a 24-bit address bus, it provides a 16 megabyte
linear address space.
The MC68HCOOO is the HCMOS version of the MC68000, with all its functions and performance.
The maximum power dissipation of the 12.5-MHz MC68HCOOO is just 0.175 watt, one-tenth of the
MC68000's power requirement.
The MC68008 has an 8-bit data bus for designs that need to conserve PC board space. The 48pin DIP version has a 20-bit address bus providing a one megabyte address space. A 52-pin quadpack version uses a 22-bit address bus to support four megabytes of linear address space.
The MC68010 uses a 16-bit data bus with the 32-bit internal architecture common to the M68000
Family. Multiple addressing modes provide flexible addressing. The MC68010 uses instruction
continuation to permit pre-emption for page swapping in virtual memory systems. Its loop-mode
operation" allows faster execution of tight software loops. The 24-bit address bus provides 16
megabytes of linear address space.
The MC68020 uses a 32-bit data bus and supports a coprocessor interface for as many as eight
coprocessors. It contains a 256-byte, on-chip instruction cache and offers additional addressing
modes. The MC68020's 32-bit address bus provides four gigabytes of linear address space.
The newest and most powerful member of the processor group, the MC68030, has on-chip,
demand-paged memory management. The increased parallelism of the MC68030 results from
two, independent, 32-bit address buses and two, independent, 32-bit data buses, which allow the
central processor unit (CPU), data cache, instruction cache, memory management unit (MMU),
and bus controller to operate in parallel. While the MMU provides address translation for a variety
of page sizes, it also supports transparently addressed windows in memory where direct access
is required without address translation. Separate on-chip data and instruction caches, 256 bytes
each, provide increased performance. The burst fill mode for these caches further enhances
throughput. Also, the asynchronous bus of the M68000 Family is supplemented by synchronous
"
bus capabilities to provide a two-clock physical bus cycle.
The MC68040 microprocessor is previewed in this manual. In addition to significantly improving
on the features and capabilities of the MC68030, the MC68040 provides floating-point arithmetic,
using a subset of the floating-point instructions supported by the MC68881 floating-point coprocessor.

M68000 FAMILY

REFERENCE

MOTOROLA
1-1

The coprocessor group includes the MC68851 paged memory managment unit (pMMU), the
MC68881 floating-point coprocessor and the MC68882 enhanced floating-point coprocessor. The
MC68851 PMMU provides full support for a demand-paged virtual memory environment. It sup,ports a four-gigabyte address space and programmable page sizes from 256 to 32K bytes. An onchip address translation cache minimizes translation delays. Both the MC68881 and the MC68882
coprocessors conform to a full implementation of the IEEE Standard for Binary Floating-Point
Arithmetic. They perform more than 40 types of transcendental and nontranscendental functions
in addition to basic add, subtract, multiply, and divide operations. The functions include root
values, trigonometric functions, exponentials, hyperbolics, and logarithms. All functions are calculated to 80 bits of precision in hardware. The enhanced MC68882 has dual-ported registers and
an advanced pipeline that allows execution of mUltiple instructions in 'parallel (more than twice
the floating-point performance of the MC68881). Although the MC68881 and MC68882 are intended
primarily as coprocessors for the MC68020 and MC68030, they can be used as peripherals with
all MPUs of the M68000 Family as well as other MPUs.
The DMA controller group consists of the MC68440 and MC68442 dual DMA controllers and the
MC68450 DMA controller. The MC68440 dual DMA controller performs memory-ta-memory, peripheral-to-memory, and memory-ta-peripheral transfers through each of two, completely independent DMA channels with minimum intervention from the MPU. The MC68442 is an expanded
version that supports a four-gigabyte addressing range. The MC68450 DMA controller has four,
completely independent DMA channels 'that use sequential and linked-array chained addressing.
The MC68450 maintains hardware and software compatibility with the MC68440.
The data communication group includes the MC2681 dual universal asynchronous Jeceiver/trans~
mitter (DUART), the MC68652/MC2652 multiprotocol communication controller (MPCC), and the
MC68681 DUART. The MC2681 DUART contains two, completely independent full-duplex asynchronous receiver/transmitter channels that interface to non-Motorola buses. Receiver data registers are quadruple buffered, and transmission data registers are double buffered; each channel
has an independently selectablebaud rate. The maximum transfer rate is 1 Megabyte per second.
The MC68652/MC2652 MPCC is a single-channel serial data device that recognizes byte-control
and bit-oriented protocois. It transfers data of 8- or 16-bit widths at a maximum two Mbit/second
(Mbps) rate with cyclical redundancy check (CRC) error detection. The MC68681 DUART has all
the capabilities and features of the MC2681 and interfaces with the M68000 Family processors.
The network device group consists of the MC68184 broadband interface controller (BIC), the
MC68194 carrierband modem (CBM), the MC68605 X.25 protocol controller (XPC), the MC68606
multilink access procedure (MLAPD) protocol controller, and the MC68824 token bus controller
(TBC). The MC68184 BIC implements the IEEE 802.4 broadband physical layer of the International
Standards Organization/Open Systems Interface (lSO/OSI) communication model for standardized
multivendor data communications networking. It supports high-speed data rates to 10 Mbps. With
the MC68824 TBC, the BIC implements layers one and two of the OSI communication modeL 1he
MC68194 CBM is an advanced bipolar LSI ,device that implements the IEEE 8024 Phase Coherent
Physical Layer. It modulates the information from' the serial interface and transmits this signal
onto the network cable. The CBMaiso receives signals from the network, demodulates th'€! information, and passes it to the TBC over the serial interface.The MC68605 XPC implements the
1984 CCITT X.25 Recommendation Data Link Procedure (level two) LAPD. It indepe'ndently performs higher level communications functions such as frame sequencing, retransmission, flow
control, retries limit, and timeout conditions for data rates as high as 10 Mbp's in addition to th'e
lower-level functions: HDLC framing, CRC generation/checking, and zero insertion/deletion. As a
bus 'master, the XPC uses on-chip DMA capability and two, 22~bit, first in-first out queues (FIFOs)
fortransferring frames to and from memory. The MC68606MLAPD protocol controller implements
the LAPD protocol for use at the link layer (OSI Layer 2) for both signaling and data transfer

MOTOROLA
1-2

M68000 FAMILY

REFERENCE

applications in integrated services digital network (ISDN) configurations. An on-chip DMA controller transfers data packets to and from a buffer memory. The MC68824 TBC implements the
IEEE 8024 media access control sublayer of the OSI data link layer as specified by General Motors'
Manufacturing Automation Protocol (MAP). It supports serial data rates of 1, 5, and 10 Mbps and
relieves the host processor of the frame-formatting and token-management functions.
The general-purpose peripheral device group consists of the MC68153 bus interrupter module
(BIM), the MC68230 parallel interface/timer (PlfT), the MC68452 bus arbitration module (BAM),
and the MC68901 multifunction peripheral. The MC68153 BIM is an interface between the M68000
microcomputer system bus and slave devices that require interrupt capability. It routes four,
independent sources of interrupt requests to any of the seven M68000 interrupt levels, and is
VMEbus compatible. The MC68230 PlfT provides double-buffered, 8- or 16-bit parallel interfaces
and a 24-bit, system-oriented timer with a 5-bit prescaler. The MC68452 BAM arbitrates control
of the M68000 bus between as many as eight bus masters. The MC68901 multifunction peripheral
provides a full-function, single-channel USART, an eight-source interrupt controller, four eightbit timers, and eight parallel I/O lines.

VERSAbus is a trademark of Motorola Inc.

M68000 FAMILY

REFERENCE

MOTOROLA
1-3

MOTOROLA
1-4

M68000 FAMILY

REFERENCE

SELECTOR GUIDE

SECTION 2
SELECTOR GUIDE

To guide the designer in selecting the components for a system, Table 2-1 lists the processors,
coprocessors, and other devices of the M68000 Family, with a brief description of each. Columns
in Table 2-1 indicate available package types and operating frequencies. The devices are listed in
numeric order.
Table 2-1. Selector Guide (Sheet 1 of 2)
Device No.
MC68000 MPU

Description
16-Bit Data Bus. 16M-Byte Address
Space

M68HCOOO MPU HCMOS Version of MC68000
MC68008 MPU

8·Bit Data Bus. 1M-Byte Address
Space

MC68010 MPU

16-Bit Data Bus. Supports Virtual
Memory. 16M-Byte Address Space

MC68020 MPU

32-Bit Data Bus. Instruction Cache.
Coprocessor Interface.
4G-Byte Address Space

MC68030 MPU

32-Bit Data Bus. Data and Instruction
Caches. Memory Management
Unit. Coprocessor Interface.
4G-Byte Address Space

MC68153 BIM

Four Interrupt Sources. Eight
Programmable ReadlWrite Registers

MC68184 BIC

IEEE 802.4 Broadband Physical Layer
Station Management. 20 Lines. 13
User-Defined Outputs. Up to 10 Mbps

MC68194 CBM

IEEE 802.4 Single-Channel PhaseCoherent FSK Physical Layer.
1 to 10 Mbps

MC68230 PIfT

Bit 1/0. Unidirectional and
Bidirectional 8- and 16-Bit
Modes. 24-Bit Timer

MC68440 DMA
Controller

Dual Channel. Up to 5M-Bytesl
Second Transfer Rate. 16M-Byte
Address Range

MC68442 DMA
Controller

Same Features as MC68440 but
with 4G-Byte Address Range

MC68450 DMA
Controller

Four Channel. Up to 5M-Bytes/Second
Transfer Rate. 16M-Byte Address
Range

MC68452 BAM

Arbitrates for 8 Bus Users. 52 ns .•
Maximum Aribtration Time

MC68605 XPC

CCITI X.25 Recommendation LAPB
Procedure. 16- and 32-Bit CRC.
8- and 16-Bit Data Bus. Up to
10 Mbps Synchronous Serial
Data Rate. DMA Transfers

M68000 FAMIL V
REFERENCE

Operating Frequency

Package Designation
L

X
X

MOTOROLA
2-1

Table 2-1. Selector Guide (Sheet 2 of 2)
Device No.

Description

MC68606
MLAPD
Controller

CCITI 0.920/0.921 LAPD, Up to
8192 Logical Links, Serial Bit
Stream Aggregate in Excess of
2.048 Mbps

MC686521

BOP or BCP, 8- or 16-Bit
Data Bus, Up to 2 Mbps Data
Rate, CRC-16 or VRC

MC2652
MPCC

Operating Frequency

Package Designation

MC68681
DUART

Programmable Data Format, 6-Bit
Input Port, 8-Bit Output Port

MC68824 TBC

IEEE 802.4 MAC, 32-Bit'Address Bus,
DMA Transfers, 8- or 16-Bit Transfers

MC68851
PMMU

32-Bit Logical and Physical
Addresses, Coprocessor Interface

MC68881 FPCP

IEEE 754 Standard, 67-Bit Arithmetic
Unit, 8-,16-, or 32-Bit Data Bus

MC68882 EFCP

All Features of the MC68881 with
Enhanced Performance

MC68901 MFP

Eight Programmable 1/0 Pins,
16-Source Interrupt Controller,
Four Timers

MOTOROLA

MC2681 DUART Selectable Baud Rate, Non-Motorola
Interface

2-2

M68000 FAMILY

REFERENCE

PROCESSORS

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68000

Technical Summary

16-/32-Bit Microprocessor
This document contains both a summary of the MC68000 as well as a detailed set of parametrics. The
purpose is twofold - to provide an introduction to the MC68000 and support for the sophisticated user.
For detailed information on the MC68000, refer to the MC68000 16-/32-Bit Microprossor Advance Information Data Sheet.
The MC68000 is the first implementation of the M68000 16/32 microprocessor architecture. The
MC68000 has a 16-bit data bus and 24-bit address bus while the full architecture provides for 32-bit address and data buses. It is completely code-compatible with the MC68008 8-bit data bus implementation
of the M68000 and is upward code compatible to the MC68010/MC68012 virtual extensions and the
MC68020 32-bit implementation of the architecture. Any user-mode programs written using the MC68000
instruction set will run unchanged on the MC68008, MC68010, MC68020. This is possible because the
user programming model is identical for all five processors and the instruction sets are proper sub-sets
of the complete architecture. Resources available to the MC68000 user consists of the following:
• . 17 32-Bit Data and Address Registers·
•

16 Megabyte Direct Addressing Range

•

56 Powerful Instruction Types

•

Operations on Five Main Data Types

•

Memory Mapped 110

•

14 Addressing Modes
31

16 15
DO .
01
02
03
04

EIGHT
DATA
REGISTERS

05
06
07
31

16 15

I
I

0
_ AD
Al

I
I

A3
A4
A5

·A7

I iUSPJ
31

SEVEN
ADDRESS
REGISTERS

USER STACK
POINTER

I PC

PROGRAM
COUNTER

....JI CCR

STATUS
REGISTER

I
L -_ _

Figure 1. User Programming Model

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA M68000 FAMILY

REFERENCE

MOTOROLA
3-1

MC68000

INTRODUCTION
As shown in the user programming model (Figure 1),
the MC68000 offers 16 32-bit registers and a 32-bit program counter. The first eight registers (00-07) are used
as data registers for byte (8-bit), word (16-bit), and long
word (32-bit) operations. The second set of seven registers \AO-A6) and the user stack pointer (USP) may be
used as software stack pointers and base address registers. In addition, the registers may be used for word
and long word operations. All of the 16 registers may be
used as index registers.
In supervisor mode, the upper byte of the status register and the supervisor stack pointer (SSP) are also available to the programmer. These registers are shown in
Figure 2.
SUPERVISOR STACK
POINTER
31

1615

STATUS REGISTER

8 7

CCR

I ~~PI
a
I SR

Figure 2. Supervisor Programming Model Supplement
The status register (Figure 3) contains the interrupt mask
(eight levels available) as well as the condition codes:
extend (X), negative (N), zero (Z), overflow (V). and carry
(C). Additional status bits indicate that the processor is
in a trace (T) mode and in a supervisor (S) or user state.

SYSTEM BYTE

USER BYTE
ICONTROl CODE REGISTER I

• Program Counter Relative
• Immediate
• Implied
Included in the register indirect addressing modes is a
capability to do postincrementing, predecrementing, offsetting, and indexing. The program counter relative mode
can also be modified via indexing and offsetting.

Table 1. Addressing Modes
Addressing Modes

Syntax

On
An

Absolute Data Addressing
Absolute Short
Absolute Long

xxx.W
xxx.L

Program Counter Relative Addressing
Relative with Offset
Relative with Index Offset

d I6 (PCI
da(PC,Xnl

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

(Ani
(Ani i
~ (Ani
d l6 (Anl
da(An,Xnl

Immediate Data Addressing
Immediate·
Quick Immediate
Implied Addressing
Implied Register

#xxx
#1~#a

SR USP SP PC

NOTES:
On
An =
Xn =
SR =
PC =
SP =
USP =

Figure 3. Status Register

0 16
#xxx

Data Register
Address Register
Address of Data Register used as Index Register
Status Register
Program Counter
Stack Pointer
User Stack Pointer
= Effective Address
= a-Bit Offset (Displacementl
16-Bit Offset (Displacement)
= Immediate Data

DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types
are:

INSTRUCTION SET OVERVIEW

• Bits
• BCD Digits (4-Bits)
• Bytes (8 Bits)
• Words (16 Bits)
• Long Words (32 Bits)
In addition, operations on other data types such as memory addresses, status word data, etc. are provided in the
instruction set.
The 14 addressing modes, shown in Table 1, include
six basic types:
• Register Direct
• Register Indirect
• Absolute

The MC68000 instruction set is shown in Table 2. Some
additional instructions are variations, or sub-sets, of these
and they appear in Table 3. Special emphasis has been
given to the instruction set's support of structured highlevel languages to facilitate ease of programming. Each
instruction, with few exceptions, operates on bytes, words,
and long words and most instructions can use any of the
14 addressing modes. Combining instruction types, data
types, and addressing modes, over 1000 useful instructions are provided. These instructions include signed and
unsigned, multiply and divide, "quick" arithmetic operations, BCD arithmetic, and expanded operations (through
traps).

MOTOROLA
3-2

M68000 FAMILY
REFERENCE

MC68000

Table 2. Instruction Set Summary
Mnemonic

Description

ABCD
ADD
AND
ASL
ASR

Add Decimal With Extend
Add
Logical AND
Arithmetic Shift Left
Arithmetic Shift Right

Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test

CHK
CLR
CMP

Check Register Against Bounds
Clear Operand
Compare

DBcc
DIVS
DIVU

Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide

EOR
EXG
EXT

Exclusive OR
Exchange Registers
Sign Extend

JMP
JSR

Jump
Jump to Subroutine

LEA
LINK
LSL
LSR

Lead Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

MOVE
MULS
MULU

Move
Signed Multiply
Unsigned Multiply

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

Logical OR

PEA

Push Effective Address

RESET.
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS

Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine

SBCD
Scc
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on Overflow
Test

UNLK

Unlink

M68000 FAMILY

REFERENCE

Table 3. Variations of Instruction Types
Instruction
Type
ADD

AND

Description

Variation
ADD
ADDA
ADDQ
ADDI
ADDX

Add
Add
Add
Add
Add

AND
ANDI
ANDI to CCR

Logical AND
AND Immediate
AND Immediate to
Condition Codes
AND Immediate to
Status Register

ANDI to SR

Address
Quick
Immediate
with Extend

CMP

CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR

EOR
EORI
EORI to CCR

Exclusive OR
Exclusive OR Immediate
Exclusive OR Immediate to
Condition Codes
Exclusive OR Immediate to
Status Register

EORI to SR

MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Move
Move
Move
Move
Move
Move
Move
Move
Move

NEG

NEG
NEGX

Negate
Negate with Extend

OR
ORI
ORI to CCR

Logical OR .
OR Immediate
OR Immediate to
Condition Codes
OR Immediate to
Status Register

MOVE

ORI to SR

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

Address
Multiple Registers
Peripheral Data
Quick
from Status Register
to Status Register
to Condition Codes
User Stack Pointer

Subtract
Subtract
Subtract
Subtract
Subtract

Address
Immediate
Quick
with Extend

MOTOROLA
3-3

MC68000

SIGNAL. DESCRIPTION

Data Transfer Acknowledge (DTACK)

The input and output signals are illustrated functionally
in Figure 4 and are described in the following paragraphs.
VCC(2)
GND(2)
CLK

ADDRESS
BUS

A1-A23
DO-D15

AS
FCO
FC1
FC2

PRDCESSOR {
STATUS

E
VMA

M6800 {
PERIPHERAL
CONTRDl
SYSTEM
CDNTROl

a::
Cl
en
en

Cl
ClUJ
ClU
ClC)Cl

a::
uo..

::'5

RIVi
UDS
lDS

ifi'lCK

ASYNCHRONOUS
BUS
CONTROL
'

BR
lffi

' } BUS ARBITRATION
lffiACi(
CONTROL

{--,,=:::-

ms:

SO S1

S2 S3 S4

S5 S6 S7 SO

eLK

A1·A23

R/Vi

VPA

VMA

DATA DUT

DATAIN----------------------------------------------------------------------------------------~

NOTE: This· timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly attainable

:s:
o
o

-i
::xJ

wo
.:...
--...J»

Figure 11. MC68000 to M6800 Peripheral Timing Diagram (Worst Case)

en
00
o
o
o

MC68000

AC ELECTRICAL SPECIFICATIONS -

Num.

BUS ARBITRATION (VCC=5.0 Vdc±5%; GND=O Vdc; TA=h to TH; see Figure 12)

Characteristic

Symbol

8 MHz*

10 MHz* 12.5 MHz*

16.67 MHz
'12F'
Unit

Min Max Min Max Min Max Min Max
7

Clock High to Address, Data Bus High Impedance
(Maximum)

r---16
Clock High to Control Bus High Impedance

tCHADZ

tCHCZ

Clock High to BG Asserted

tCHGL

Clock High to BG Negated

tCHGH

BR Asserted to BG Asserted

tBRLGL

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

36'

BR Negated to BG Negated

tBRHGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

BGACK Asserted to BG Negated

tGALGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

37A2

BGACK Asserted to BR Negated

tGALBRH

1.5
Clks

BG Asserted to Control, Address, Data Bus High
Impedance (AS Negated)

tGLZ

BG Width Negated

tGH

1.5

Clks

BGACK Width Low

tGAL

1.5

Clks

Asynchronous Input Setup Time

tASI

BGACK Negated to AS, DS, RIW Driven

tGASD

1.5

Clks

57A

BGACK Negated to FC, VMA Driven

tGAFD

Clks

58'

BR Negated to AS, DS, RIW Driven

tRHSD

1.5

Clks

BR Negated to FC, VMA Driven

tRHFD

Clks

58A'

*These specifications represent an improvement over previously published specifications for the 8-, 10-, and 12.5-MHz MC68000 and
are valid only for product bearing date codes of 8827 and later.
NOTES:
1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK.
2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be re-asserted.

These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications.
They are not intended as a functional description of the input and output signals. Refer to other functional descriptions
and their related diagrams for device operation.

STROBES
ANO R/W

BR
liGACK

BG
eLK

NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, IPLO-IPL2, and VPA guarantees their
recognition at the next falling edge of the clock.

Figure 12. MC68000 Bus Arbitration Timing Diagram

MOTOROLA
3-18

M68000 FAMILY
REFERENCE

MC68000

PIN ASSIGNMENTS

64·PIN DUAL·IN·LlNE PACKAGE
04
03

02
01
00

68·TERMINAL PIN GRID ARRAY

07
08
09

010
011
012
R/iii
OTACK

014

iiG

11
12
13
14

015
GNO
A23
A22

A21

GNO

HID

17
18

VCC
A20
A19

BGACK

lffi
VCC
CLK

RESET

19
20
21

A18

BERR

22
23

A15

iPU

0 0

FCO

BERR

iPi:O

0
0

0 0
iPLi
0

FCI

0A4 0 0

0 0

N C

HAL T

AID

N C

All

A14

A12

A16

VPA

A15

A17

0 0
0 0
vcc
0 0

0
0
Q vcc
o 0

A13

BOTTOM
VIEW

A18

GND

CLK

0 0 0
0 0

RESET

0 0
0 0

0 0

IPL2

A19

A20

,/
,/

GND

A21

(5
0 0 0
BG /
0
0
0
0
o /d
0
0 0 0

BGACK

VMA
E
VPA

fP[T

0 0

FC2

VMA

013

0 0

DTACK
A

LDS

R/W

UDS

0 0
AS

0 0

D13

A23

Dll

D14

D15

0 0 0

DID

D12

A17
A16

A14
A13

IPLO
FC2

24
25
26

FCl
FCO

A12
All
Al0

A2
A3

30
31

A7
A6

68·LEAD QUAD PACK

!~~=g~~8g~~~~~~~~
I

I I I

I I

I I I

I I

068
1

llTACR -

BG-

61
60

BGACK -

lffiVCC CLK GNOGNON.C. HALT RESETVMA-

E-

VPA-

llEIfRIPL244
43

fP[T-

35
I

I I I

I I

I I I

I I

013
014
015
GNO
GNO
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13

~~~~~<~~~~~~~~~~~

M68000 FAMILY
REFERENCE

MOTOROLA
3-19

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68HCOOO
Technical Summary

Low Power HCMOS
16-132-Bit Microprocessor
This document contains both a summary of the MC68HCOOO as well as a detailed set of parametrics.
The purpose is twofold - to provide an introduction to the MC68HCOOO and support for the sophisticated.
user. For detailed information on the MC68HCOOO, refer to the MC68000 16-8it Micorprocessor User's
Manual.'
The primary benefit of the MC68HCOOO is its reduced power consumption. The device dissipates an
order of magnitude less power than the HMOS MC68000.
The MC68HCOOO is an implementation of the M68000 16/32 microprocessor architectur.e. The
MC68HCOOO has a 16-bit data bus implementation of the M68000 and is upward code compatible to the
MC68010 virtual extension and the MC68020 32-bit implementation of the architecture. Any user-mode
programs written using the MC68HCOOO instruction set will run unchanged on the MC68000, MC68008,
MC68010, and MC68020. This is possible because the user programming model is identical for all five
processors and the instruction sets are proper sub-sets of the complete architecture. Resources available
to the MC68HCOOO user consist of the following:
• 17 32-Bit Data and Address Registers
• 16 Megabyte Direct Addressing Range
• 56 Powerful Instruction Types
• Operations on Five Main Data Types
• Memory Mapped I/O
• 14 Addressing Modes
31

16 15

8 7
DO
Dl
D2
D3
D4

' EIGHT
DATA
REGISTERS

D5
D6
D7
31

16 15
AO
Al
A2
A3

SEVEN
ADDRESS
REGISTERS

A5
A6
A7

I (USP)
31

I PC

I CCR

USER STACK
POINTER
PROGRAM
COUNTER
STATUS
REGISTER

Figure 1. User Programming Model

This document contains information on a new product. Specifications and information herein are subject to change without notice,

MOTOROLA·_
MOTOROLA
3-20

M68000 FAMILY
REFERENCE

MC68HCOOO

INTRODUCTION

Table 1. Addressing Modes

As shown in the user programming model (Figure 1l.
the MC68HCOOO offers 16 32-bit registers and a 32-bit
program counter. The first eight registers (00-07) are
used as data registers for byte (8-bit), word (16-bit), and
long word (32-bit) operations. The second set of seven
registers (AO-A6) and the user stack pointer (USP) may
be used as software stack pointers and base address registers. In addition, the registers may be used for word
and long word operations. All of the 16 registers may be
used as index registers.
In supervisor mode, the upper byte of the status register and the supervisor stack pointer (SSP) are also available to the programmer. These registers are shown in
Figure 2.
The status register (Figure 3) contains the interrupt mask
(eight levels available) as well as the condition codes:
extend (Xl. negative (Nl. zero (Zl. overflow (Vl. and carry
(C). Additional status bits indicate that the processor is
in a trace (T) mode and in a supervisor (S) or user state.
SYSTEM BYTE

USER BYTE
ICONTROL COOE REGISTER I

DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types
are:
• Bits
• BCD Digits (4 Bits)
• Bytes (8 Bits)
• Words (16 Bits)
• Long Words (32 Bits)
In addition, operations on other data types such as memory addresses, status word data, etc. are provided in the
instruction set.
The 14 addressing modes, shown in Table 1, include
six basic types:
• Register Direct
• Register Indirect
• Absolute
• Program Counter Relative
• Immediate
• Implied
Included in the register indirect addressing modes is the
capability to do postincrementing, predecrementing, off31

Dn
An

Absolute Data Addressing
Absolute Short
Absolute Long

xxx.W
xxx.L

Program Counter Relative Addressing
Relative with Offset
Relative with Index Offset

d16 1PCI
dalPC,Xnl

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

IAn I
IAnl+
-IAnl
d16 1Ani
dslAn,Xn)

Immediate Data Addressirig
Immediate
Quick Immediate

#xxx
#l-#S

Implied Addressing
Implied Register

SR/USP/SP/PC

Data Register

= Address Register
= Address of Data Register
= Status Register

used as Index Register

Program Counter
Stack Pointer
= User Stack Pointer
= Effective Address
= S-Bit Offset !Displacement)
d16
= 16-Bit Offset IDisplacementl
#xxx = Immediate Data
=

setting, and indexing. The program counter relative mode
can also be modified via indexing and offsetting.

iNSTRUCTION SET OVERVIEW
The MC68HCOOO instruction set is shown in Table 2.
Some additional instructions are variations, or sub-sets,
of these and they appear in Table 3. Special emphasis
has been given to the instruction set's support of structured high-Ievellangugages to facilitate ease of programming. Each instruction, with few exceptions, operates on
bytes, words, and long words and most instructions can
use any of the 14 addressing modes. Combining instruction types, data types, and addressing modes, over 1000
useful instructions are provided. These instructions include signed and unsigned, multiply and divide, "quick"
arithmetic operations, BCD arithmetic, and expanded operations (\hrough traps).
0

16 15

I ~~PI

L ._ _ _ _ _ _ _ _~_ _ _ _ _ _ _- - - '

15
~T ATUS

Syntax

NOTES:
Dn
An
Xn
SR
PC
SP
USP
I )
dS

Figure 3. Status Register

SUPERVISOR STACK
POINTER

Addressing Modes

8 7

CCR

Figure 2. Supervisor Programming Model Supplement

M68000 FAMILY
REFERENCE

MOTOROLA
3-21

MC68HCOOO

Table 2. Instruction Set Summary
Mnemonic

Description

ABCD
ADD
AND
ASl
ASR

Add Decimal With Extend
Add
Logical AND
Arithmetic Shift Left
Arithmetic Shift Right

Bce
BCHG
BClR
BRA
BSET
BSR
BT5T

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test

CHK
CLR
CMP

Check Register Against Bounds
Clear Operand
Compare

DBcc
DIVS
DIVU

Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide

EOR
EXG
EXT

Exclusive OR
Exchange Registers
Sign Extend

JMP
JSR

Jump
Jump to Subroutine

LEA
LINK
LSl
LSR

Lead Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

Mnemonic

Description'

MOVE
MULS
MULU

Move
Signed Multiply
Unsigned Multiply

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

Logical OR

PEA

Push Effective Address

RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS

Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine

SBCD
Scc
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on Overflow
Test

UNLK

Unlink

Table 3. Variations of Instruction Types
Instruction
Type
ADD

AND

Description

Variation
ADD
ADDA
ADDQ
ADDI
ADDX

Add
Add
Add
Add
Add

AND
ANDI
ANDI to CCR

Logical AND
And Immediate
And Immediate to
Condition Codes
And Immed i 3te to Status
Register

ANDI to SR
CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR

EOR
EORI
EORI to CCR

Exclusive OR
Exclusive OR Immediate
Exclusive OR Immediate to
Condition Codes
Exclusive OR Immediate to
Status Register

MOTOROLA
3-22

Variation

Description

MOVE

MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Move
Move Address
Move Multiple Registers
Move Peripheral Data
Move Quick
Move from Status Register
Move to Status Register
Move to Condition Codes
Move User Stack Pointer

NEG

NEG
NEGX

Negate
Negate w~th Extend

Address
Quick
Immediate
with Extend

CMP

EORI to SR

Instruction
Type

OR
ORI
. ORI to CCR
ORI to SR

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

Logical OR
OR Immediate
OR Immediate to
Condition Codes
OR Immediate to Status
Register
Subtract
Subtract
Subtract
Subtract
Subtract

Address
Immediate
Quick
with Extend

M68000 FAMILY

REFERENCE

MC68HCOOO

SIGNAL DESCRIPTION

Table 4. Data Strobe Control of Data Bus

The input and output signals are illustrated functionally in
Figure 4 and are described in the following paragraphs.

.--------,AOORESS
BUS

0l)S

R/W

08-015

00-07

High

No Valid Data

Low

High

Valid Data Bits

8-15

0-7

A1·A23

High

Low

High

No Valid Data

Valid Data Bits

00015

Low

High

Valid Data Bits

No Valid Data

0-7

8-15
Low

FCO
PROCESSOR {
STATUS

o °
en
°oU U
en
....
:x: °

Low

VMA
VPA

SYSTEM {
CONTROL

0-7
Valid Data Bits

Low

Valid Data Bits

0-7*

0-7

Low

High

Low

Valid Data Bits

8-15

8-15*

Valid Data Bits

8-15
Low

<0"'-

::;;;~

Valid Data Bits

High

coO::

M6800 {
PERIPHERAL
CONTROL

Low

*These conditions are a result of current implementation and may
not appear on future devices.

}

INTERRUPT
CONTROL

Data Transfer Acknowledge (DTACK)
Figure 4. Input and Output Signals

ADDRESS BUS (A1 THROUGH A23)
This 24-bit, unidirectional, three-state bus is capable of addressing 16 megabytes of data. It provides the address for bus
operation during all cycles except interrupt cycles. During interrupt cycles, address lines A 1, A2, and A3 provide information about what level interr'Jpt is being serviced while
addr~ss lines A4 through A23 are set to a logic high.
DATA BUS (DO THROUGH 015)
This 16-bit, bidirectional, three-state bus is the general purpose data path. It can transfer and accept data in either word
or byte length. During an interrupt acknowledge cycle, the
external device supplies the vector number on data lines 00- .

07.
ASYNCHRONOUS BUS CONTROL
Asynchronous data transfers are handled using the following
control signals: address strobe, read/write, upper and lower
data strobes, and data transfer acknowledge. These signals
are explained in the following paragraphs.
Address Strobe (AS)
This signal indicates that there is a valid address on the
address bus.
Read/Write (R/W)
This signal defines the data bus transfer as a read or wr.ite
cycle. The R/W signal also works in conjunction with the data
strobe~ as explaindd in the fo!lowing paragraph.

This input indicates that the data transfer is completed.
When the processor recognizes DTACK during a read cycle,
data is latched and the bus cycle terminated. When DT ACK
is recognized during a write cycle, the bus cycle is terminated.
BUS ARBITRATION CONTROL
The three signals, bus request, bus grant, and bus grant
acknowledge, form a bus arbitration circuit to determine which
device will be the bus master device.
Bus Request (BR)
This input is wire ORed with all other devices that could be
bus masters. This input indicates to the processor that some
other device desires to becomE' the bus master.
Bus Grant (BG)
This output indicates to all other potential bus master devices
that the processor will release bus control at the end of the
current bus cycle.
Bus Grant Acknowledge (BGACK)
This input indicates that some other device has become the
bus master. This signal should not be asserted until the following four conditions are met:
1. a bus grant has been received,
2. address strobe is inactive which indicates that the microprocessor is not using the bus,
3. data transfer acknowledge is inactive which indicates that
neither memory nor peripherals are using the bus, and
4. bus grant acknowledge is inactive which indicates that
no other device is still claiming bus mastership.
INTERRUPT CONTROL (JPLO, IPL1, IPL2)

Upper and Lower Data Strobe (UDS, LOS)
These signals control the flow of data on the data bus, as
shown in Table 4. When the R/W line is high, the processor
will read from the data bus as indicated. When the R/W line
is low, the processor will write to the data bus as shown.

M68000 FAMILY
REFERENCE

These input pins indicate the encoded priority level of the
device requesting an interrupt. Level seven is the highest priority while level zero indicates that no interrupts are requested.
Level seven cannot be masked. The least significant bit is given
in IPLO and the most significant bit is contained in IPL2. These

MOTOROLA
3-23

MC68HCOOO

lines must remain stable until the processor signals interrupt
acknowledge (FCO-FC2 are all high) to insure that the interrupt
is recognized.

synchronized with the enable (E) signal. This input also indicates that the processor should use automatic vectoring for
an interrupt during an lACK cycle.

SYSTEM CONTROL

Valid Memory Address (VMA)

The system control inputs are used to either reset or halt
the processor and to indicate to the processor that bus errors
have occurred. The three system control inputs are explained
in the following paragraphs.

This output is used to indicate to M68000 peripheral devices
that there is a valid address on the address bus and the processor is synchronized to enable. This signal only responds to
a valid peripheral address (VPA) input which indicates that the
peripheral is an M68000 Family device.

Bus Error (BERR)
This input informs the processor that there is a problem with
the cycle currently being executed. Problems may be a result
of:
1. nonresponding devices,
2. interrupt vector number acquisition failure,
3. illegal access request as determined by a memory management unit, or
4. other application dependent errors.
The bus error signal interacts with the halt signal to determine
if the current bus cycle should be re-executed or if exception
processing should be performed.
Reset (RESET)
This bidirectional signal line acts to reset (start a system
initialization sequence) the processor in response to an external
reset signal. An internally generated reset (result of a RESET
instruction) causes all external devices to be reset and the
internal state of the processor is not affected. A total system
reset (processor and external devices) is the result of external
HALT and RESET signals applied at the same time.
Halt (HALT)
When this bidirectional line is driven by an external device,
it will cause the processor to stop at the completion of the
current bus cycle. When the processor has been halted using
this input, all control signals are inactive and all three-state
lines are put in their high-impedance state.
When the processor has stopped executing instructions,
such as in a double bus fault condition, the HALT line is driven
by the processor to indicate to external devices that the processor has stopped.
M6800 PERIPHERAL CONTROL
These control signals are used to allow the interfacing of
synchronous M6800 peripheral devices with the asynchronous
MC68HCOOO. These signals are explained in the following
paragraphs.
Enable (E)
This signal is the standard enable signal common to all
M6800 type peripheral devices. The period for this output is
ten MC68HCOOO clock periods (six clocks low, four clocks
high). Enable is generated by an internal ring counter which
may come up in any state (i.e., at power on, it is impossible
to guarantee phase relationship of E to ClK). E is a free-running
clock and runs regardless of the state of the bus on the MPU.
Valid Peripheral Address (VPA)
This input indicates that the device or region addressed is
an M68000 Family device and that data transfer should be

MOTOROLA
3-24

PROCESSOR STATUS (FCD, FC1, FC2)
These function code .outputs indicate the state (user or supervisor) and the cycle type currently being executed, as
shown in Table 5. The information indicated by the function
code outputs is valid whenever address strobe (AS) is active.
Table 5. Function Code Outputs
Function Code Output
FC2

FC1

FCD

Cycle Time

Low
Low
Low
Low
High
High
High
High

Low
Low
High
High
Low
Low
High
High

Low
High
Low
High
Low
High
Low
High

(Undefined, Reserved)
User Data
User Program
(Undefined, Reserved)
(Undefined, Reserved)
Supervisor Data
Supervisor Program
Interrupt Acknowledge'

CLOCK (ClK)
The clock input is a TTL-compatible signal that is internally
buffered for development of the internal clocks needed by the
processor. The clock input should not be gated off at any time
and the clock signal must conform t6 minimum and maximum
pulse width times. The clock is a constant frequency square
wave with no stretching or shaping techniques required.

DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following
leads:
1. address bus A 1 through A23,
2. data bus DO through D15, and
3. control signals.
The address and data buses are separate parallel buses used
to transfer data using an asynchronous bus structure. In all
cycles, the bus master assumes responsibility for deskewing
all signals it issues at both the start and end of a cycle. In
addition, the bus master is responsible for deskewing theacknowledge and data signals from the slave device.
The following paragraphs explain the read, write, and readmodify-write cycles. The indivisible read-modify-write cycle is
the method used by the MC68HCOOO for interlocked multiprocessor communications.
READ CYCLE
During a read cycle, the processor 'receives data from the
memory of a peripheral device. The processor reads bytes of
data in all cases. If the instruction specifies a word (or double
word) operation, the processor reads both upper and lower
bytes simultaneously by asserting both upper and lower data

M68000 FAMILY
REFERENCE

MC68HCOOO

strobes. When the instruction specifies byte operation, the
processor uses an internal AO bit to determine which byte to
read and then issues the data strobe required for that byte.
For byte operations, when the AO bit equals zero, the upper
data strobe is issued. When the AO bit equals one, the lower
data strobe is issued. When the data is received, the processor
correctly positions it internally.

WRITE CYCLE
During a write cycle, the processor sends data to either the
memory or a peripheral device. The processor writes bytes of
data in all cases. If the instruction specifies a word operation,
the processor writes both bytes. When the instruction specifies
a byte operation, the processor uses an internal AO bit to
determine which byte to write and then issues the data strobe
required for that byte. For byte operations, when the AO bit
equals zero, the upper data strobe is issued. When the AO bit
equals one, the lower data strobe is issued.

READ-MODIFY-WRITE CYCLE
The read-modify-write cycle performs a read, modifies the
data in the arithmetic-logic unit, and writes the data back to
the same address. In the MC68HCOOO, this cycle is indivisible
in that the address strobe is asserted throughout the entire
cycle. The test and set (TAS) instruction uses this cycle to
provide meaningful communication between processors in a
multiple processor environment. This instruction is the only
instruction that uses the read-modify-write cycles and since
the test and set instruction only operates on bytes, all readmodify-write cycles are byte op~rations.

PROCESSING STATES
The MC68HCOOO is always in one of three processing states:
normal, exception, or halted.

NORMAL PROCESSING
The normal processing state is that associated with instruction execution; the memory references are to fetch instructions
and operands, and to store results. A special case of normal

M68000 FAMILY
REFERENCE

state is the stopped state which the processor enters when a
stop instruction is executed. In this state, no further references
are made.

EXCEPTION PROCESSING
The exception processing state is associated with interrupts,
trap instructions, tracing, and other exception conditions. The
, exception may be internally generated by an instruction or by
an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by
an interrupt, by a bus error, or by a reset. Exception processing
is designed to provide an efficient context switch so that the
processor may handle unusual conditions.

HALTED PROCESSING
The halted processing state is an indication of catastrophic
hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor'
assumes that the system is unusable and halts. Only an external
reset can restart a halted processor. Note that a processor in
the stopped state is not in the halted state, nor vice versa.

INTERFACE WITH M6800 PERIPHERALS
Motorola's extensive line of M6800 peripherals are directly
compatible with the MC68HCOOO. Some of these devices that
are particularly useful are:
MC6821
MC6840
MC6843
MC6845
MC6850

Peripheral Interface Adapter
Programmable Timer Module
Floppy Disk Controller
CRT Controller
Asynchronous Communications Interface
Adapter
MC6854 Advanced Data Link Controller

To interface the synchronous M6800 peripherals with the asynchronous MC68HCOOO, the processor modifies its bus cycle'
to meet' the M6800 cycle requirements whenever an M6800
device address is detected. This is possible since' both the
processors us~ memory mapped I/O.

MOTOROLA
3-25

MC68HCOOO

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

VCC

-'-0.3 to +6.5

Input Voltage

Vin

-0.3 to +6.5

Operating Temperature Range
MC68HCOOO

TL to TH
o to 70

°c

Tstg

-55.to +150

°c

Storage Temperature

This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields;
however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum. rated voltages to this high-impedance
circuit. Reliability of operation .is enhanced if unused inputs are tied to the
.appropriate logic voltage level (e.g.,
either GND or Vccl. .

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance (Still Air)
Ceramic, Type ULC
Ceramic; Type R/RC
Plastic, Type P
Plastic, Type FN

Symbol

Value

Symbol

Value

{lJC

{lJA
30
33
30
45

Rating
°CIW

15*
15
15*
25*

*Estimated

CMOS CONSIDERATIONS
The MC68HCOOO, with its significantly lower power
consumption, has other considerations. The CMOS cell
is basically composed of two complementary transistors
(a P channel and an N channel), and only one transistor
is turned on while the cell is in the steady state. The active
P-channel transistor sources current when the output is
a logic high and presents a. high impedance when the
output is a logic low. Thus, the overall result is extremely
low power consumption because no power is lost through
the active P-channel transistor. Also, since only one transistor is turned on during the steady state, power consumption is determined by leakage currents.
Because the basic CMOS cell is composed of two complementary transistors, a virtual semiconductor controlled rectifier (SCR) may be formed when an input
exceeds the supply voltage. The SCR that is formed by
this high input causes the device to become latched in a

MOTOROLA
3-26

mode that may result in excessive current drain and eventual destruction of the device. Although the MC68HCOOO
is implemented with input protection diodes, care should
be exercised to ensure that the maximum input voltage
specification is not exceeded. Some systems may require
that the CMOS circuitry be isolated from voltage transients; others may require no additional circuitry.
The MC68HCOOO, implemented in CMOS; is applicable
to designs to which the following considerations are relevant:
1. The MC68HCOOO completely satisfies the input/output drive requirements of CMOS logic devices.
2. The HCMOS MC68HCOOO provides an order of magnitude reduction in power dissipation when compared to the HMOS MC68000. However, the
MC68HCOOO does not offer a "power down" mode.
The minimum operating frequency of the
MC68HCOOO is 4 MHz.

M68000 FAMILY
REFERENCE

MC68HCOOO

DC ELECTRICAL CHARACTERISTICS

(VCC = 5.0 Vdc ± 5%; GND = 0 Vdc; TA = TL to THI
Symbol

Min

Max

Unit

Input High Voltage

VIH

2.0

Input Low Voltage

VIL

GND-O.3

VCC
0.8
2.5
20

iJ.A

iJ. A

Characteristic

Input Leakage Current
(u 5.25 V

BERR, BGACK, BR, DTACK, CLK, IPLO-IPL2, VPA
HALT, RESET

lin

Three-State (Off State I Input Current
((I 2.4 V/0.4 V

~ A 1.:£>.2]LJ~.o:.Q.Th
FCO-FC2, LDS, RIW, UDS, VMA

ITSI

Output High Voltage
(lOH = - 400 iJ.AI

E, AS,..A!::A2~B~.LQO:.Q.Th
FCO-FC2, LDS, R/W, UDS, VMA

VOH

Output Low Voltage
(lQL=1.6 mAl
(lOL =3.2 mAl
(lOL=5.0 mAl
(lOL =5.3 mAl

VOL

f=8
f= 10
f= 12.5
f= 16.67

MHz
MHz
MHz
MHz

Power Dissipation

f=8
f=10
f= 12.5
f= 16.67

MHz
MHz
MHz
MHz

Capacitance (Vin = 0 V, TA = 25°C, Frequency = 1 MHzl**
HALT
All Others

V
V

0.5
0.5
0.5
0.5

.'
I

Cin

Load Capacitance

VCC- 0.75

HALT
A l-A23, BG, FCO-FC2
RESET
E, AS, DO-D15, LDS, R/W, UDS, VMA

Current Dissipation*

25
30
35
50

rnA

0.13
0.16
0.19
0.26

20.0

70
130

*Currents listed are with no loading.
**Capacitance is periodically sampled rather than 100% tested.

AC ELECTRICAL SPECIFICATIONS -

Num.

CLOCK TIMING (See Figure 5)

Symbol

Characteristic
Frequency of Operation

f
t cvc

2,3

Clock Pulse Width (Measured from 1.5 V to 1.5 V for 12Fl

tCL
tCH

4,5

Clock Rise and Fall Times

tCr
tCf

10 MHz* 12.5 MHz*

8.0

4.0

10.0 4.0

125 250

100

250

125

125
125

45
45

125
125

35
35

125
125

27
27

62.5
62.5

5
5

4.0

Cycle Time

16.67 MHz
'12F'
Unit
Min Max Min Max Min Max Min Max
8 MHz*

55
55

10
10

12.5 8.0

5
5

16.7 MHz

*These specifications represent an improvement over previously published specifications for the 8-, 10-, and 12.5-MHz MC68HCOOO
and are valid only for product bearing date codes of 8827 and later.

J . - - - - - - teye

-----+-i

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volt and high a voltage of 2.0 volts, unless otherwise noted. The
voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt
and 2.0 volts.

Figure 5. Clock Input Timing

M68000 FAMILY

REFERENCE

MOTOROLA
3-27

MC68HCOOO

AC ELECTRICAL SPECIFICATION DEFINITIONS
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times.
All signals are specified relative to an appropriate edge
of the clock and possibly to one or more other signals.
The measurement of the AC specifications is defined
by the waveforms shown in Figure 6. In order to test the
parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in that figure. Outputs
are specified with minimum and/or maximum limits( as
DRIVE
TO 2.4 V

appropriate, and are measured as shown in Figure
Inputs are specified with minimum setup and hold times,
and are measured as shown. Finally, the measurement
for signal-to-signal specifications is also shown.

NOTE
The testing levels used to verify conformance to the
AC specifications does not affect the guaranteed DC'
operation of the device as specified in the DC electrical characteristics.

elK

OUTPUTS(l) elK

VALID
OUTPUT n

OUTPUTS(2) elK

INPUTS(3) elK

VALID
OUTPUT n+ 1

2.0 V

VALID

0.8 V OUTPUT n + 1

DRIVE-.
TO 2.4 V
DRIVE-.
TO 0.5 V

+---- DRIVE
TO 2.4 V

INPUT(4) elK

+--

DRIVE
TO 0.5 V

All SIGNAlS(5)

2.0 V
0.8 V

NOTES:
1. This
This
This
This
This

2.
3.
4.
5.

output timing is applicable to all parameters specified relative to the rising edge of the clock.
output timing is applicable to all parameters specified relative to the falling edge of the clock.
input timing is applicable to all parameters specified relative to the rising edge of the clock.
input timing is applicable to all parameters specified relative to the falling edge of the clock.
timing is applicable to all parameters specified relative to the assertion/negation of another signal.

lEGEND:

A.
B.
C.
D.
E.
F.

Maximum output delay specification.
Minimum output hold time.
Minimum input setup time specification.
Minimum input hold time specification.
Signal valid to signal valid specification (maximum or minimum).
Signal valid to signal invalid specification (maximum or minimum).

Figure 6. Drive Levels and Test Points for AC Specifications

MOTOROLA
3-28

M68000 FAMILY

REFERENCE

MC68HCOOO

AC ELECTRICAL SPECIFICATIONS - READ AND WRITE CYCLES (VCC=5.0 Vdc:t5%; GND=O Vdc; TA=lL to TH;
see Figures 7 and 8)

Num.

Characteristic

Symbol

8 MHz* 10 MHz* 12.5 MHz* 16'~172F~HZ
f-------r--t----.-+-,---t-----r--i

Unit

Min Max Min Max Min Max Min Max
6

Clock Low to Address Valid

tCLAV

Clock High to FC Valid

tCHFCV

Clock High to Address, Data Bus High Impedance
(Maximum)

tCHADZ

Clock High to Address, FC Invalid (Minimum)

tCHAFI

Clock High to AS, DS Asserted

tCHSL

112

Address Valid to AS, DS Asserted (Read)/AS
Asserted (Write)

tAVSL

30
90

llA2

FC Valid to AS, DS Asserted (Read)/AS Asserted (Write)

tFCVSL

121

Clock Low to AS, DS Negated

tCLSH

13 2

AS, DS Negated to Address, FC Invalid

tSHAFI

o
60

AS (and DS Read) Width Asserted

tSL

270

195

DS Width Asserted (Write)

tDSL

140

152

AS, DS Width Negated

tSH

150

105

Clock High to Control Bus High Impedance

tCHCZ

AS, DS Negated to RIW Invalid

tSHRH

18 1

Clock High to RIW High (Read)

tCHRH

20 1

Clock High to RIW Low (Write)

tCHRL

20A2,6 AS Asserted to RiW Valid (Write)
212
21A2

30
31 2,5

o
o

55
55

o
o

tAVRL

FC Valid to RIW Low (Write)

tFCVRL

RIW Low to DS Asserted (Write)

tRLSL

Clock Low to Data-Out Valid (Write)

tCLDO

AS, DS Negated to Data-Out Invalid (Write)
Data-Out Valid to DS Asserted (Write)
Data-In Valid to Clock Low (Setup Time on Read)

160

ns
40

120

ns
ns

10
-

50
10

20
45

o
o

ns
ns

tASRV

Address Valid to RiW Low (Write)

tSHDOI

tDOSL

tDICL

tSHDAH

AS, DS Negated to Data-In Invalid (Hold Time on Read)

tSHDIl

AS, DS Negated to Data-In High Impedance

tSHDZ

AS, DS Negated to DTACK Negated
(Asynchronous Hold)

29A

30
40

3
15

60
50

142

14A

172

AS, DS Negated to BERR Negated

tSHBEH

DTACK A~serted to Data-In Valid (Setup Time)

tDALDI

240

190

120

o
187

ns
ns

o
65

110

o
150

o
90

ns
150

HALT and RESET Input Transition Time

tRHr,f

200

150

Clock High to BG Asserted

tCHGL

Clock High to BG Negated

tCHGH

BR Asserted to BG Asserted

tBRLGL

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

BR Negated to BG Negated

tBRHGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

BGACK Asserted to BG Negated

tGALGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

37AB

BGACK Asserted to BR Negated

tGALBRH

1.5
Clks

BG Asserted to Control, Address, Data Bus High
Impedance (AS Negated)

M68000 FAMILY

REFERENCE

tGLZ

200

MOTOROLA
3-29

MC68HCOOO

AC ELECTRICAL SPECIFICATIONS -

Num.

READ AND WRITE CYCLES (Continued)

Characteristic

BG Width Negated

Clock Low to VMA Asserted

Clock Low to E Transition

E Output Rise and Fall Time

VMA Asserted to E High

AS, OS Negated to VPA Negated

E Low to Control, Address Bus Invalid
(Address Hold Time)

Symbol

16.67 MHz
'12F'
Unit
Min Max Min Max Min Max Min Max
8 MHz*

1.5

tCLVML

tCLET

tEr,f

tvMLEH

200

150

tSHVPH

120

tELCAI

1.5

Clks

1.5

ns
ns

tGH

BGACK Width Low

tGAL

1.5

47 5

Asynchronous Input Setup Time

tASI

tBELDAL

48 2,3
49 9

BERR Asserted to DTACK Asserted

Clks

tSHEL

-70

-55

-45

-35

E Width High

tEH

450

350

280

220

E Width Low

tEL

700

550

440

340

Data-Out Hold from Clock High

tCHDOI

R/W Asserted to Data Bus Impedance Change

tRLDBD

56 4

HALT/RESET Pulse Width

tHRPW

tELDOI

E Low to Data-Out Invalid

BGACK Negated to AS, OS, RIW Driven

tGASD

1.5

Clks

BGACK Negated to FC, VMA Driven

tGAFD

tRHSD

1.5

tRHFD

Clks

BR Negated to AS, OS, Riw Driven

BR Negated to FC, VMA Driven

Clks

57A
58 7
58A7

AS, OS, Negated to E Low

10 MHz* 12.5 MHz*

ns
ns
elks

Clks

*These specifications represent an improvement over previously published specifications for the 8-,10-, and 12.5-MHz MC68HCOOO
and are valid only for product bearing date codes of 8827 and later.
NOTES:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the maximum
columns.
2. Actual value depends on clock period.
3. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input
using the asynchronous input setup time (#47).
4. For power-up, the MC68000 must be held in the reset state for 100 milliseconds to allow stabilization of on-chip circuitry. After
the system is powered up, #56 refers to the minimum pulse width required to reset the processor.
5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK-asserted to data setup time (#31)
requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle.
6. When AS and R/W are equally loaded (±20%), subtract 5 nanoseconds from the values given in these columns.
7. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK.
8. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be re-asserted.
9. The falling edge of S6 triggers both the negation of the strobes (AS and xDS) and the falling edge of E. Either of these events
can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will
occur between the rising edge of the strobes and the falling edge of the E clock.

MOTOROLA
3-30

M68000 FAMILY
REFERENCE

MC68HCOOO

ClK

FCO·FC2

Al·A23

DATA IN - - - - - - - - - - + - - - - + - + - - - - ( 1

BERRIBR
INOTE 21

ASYNCHRONOUS - - - - - - - - - - - INPUTS
INOTE 1 1 - - - - - - - - - - - - -

NOTES:
1. Setup time for the asynchronous inputs IPLO-IPL2 and VPA (#47) guarantees their recognition at the next falling edge of the
clock.
.
2. BR need fall at this time only in order to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise
noted .. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear
between 0.8 volt and 2.0 volts.

Figure 7. MC68HCOOO Read-Cycle Timing Diagram

M68000 FAMILY

REFERENCE

MOTOROLA
3-31

MC68HCOOO

DATA OUT

BERRIBR
INOTE 2)

ASYNCHRONOUS - - - - - - - - - - - INPUTS
INOTE 1) - - - - - - - - - - - -

NOTES:
1. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise
noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear
between 0.8 volt and 2.0 volts.
2. Because of loading variations, R/IN may be valid after AS even though both are initiated by the rising edge of S2 (specification
#20A).

Figure 8. MC68HCOOO Write-Cycle Timing Diagram

M68000 FAMILY

REFERENCE

MC68HCOOO

AC ELECTRICAL SPECIFICATIONS - MC68HCOOO TO M6800 PERIPHERAL CYCLES (VCC=5.0 Vdc::!:5%; GND=O Vdc;
TA=TL to TH; see Figures 9 and 10)
Num.

Characteristic

Symbol

16.67 MHz
'12F'
Unit
Min Max Min Max Min Max Min Max
8 MHz*

10 MHz* 12.5 MHz*

121

Clock Low to AS, DS Negated

tCLSH

181

Clock High to RIW High (Read)

tCHRH

20 1

Clock High to RIW Low (Write)

tCHRL

Clock Low to Data-Out Valid (Write)

tCLDO

Data-In Valid to Cloc'k Low (Setup Time of Read)

tDICL

tSHDIl

AS, DS Negated to Data-In Invalid (Hold Time on Read)

Clock Low to VMA Asserted

tCLVML

tCLET

E Output Rise and Fall Time

tEr f

Clock Low to E Transition

VMA Asserted to E High

tVMLEH

200

150

AS, DS Negated to VPA Negated"

tSHVPH

120

E Low to Control, Address Bus Invalid
(Address Hold Time)

tELCAI

Asynchronous Input Setup Time

49 2

AS, DS, Negated to E Low

tASI

tSHEL

-70

-55

-45

-35

350

280

220

440

340

E Width High

tEH

450

E Width Low

tEL

700

E Low to Data-Out Invalid

tELDOI

550
20

*These specifications represent an improvement over previously published specifications for the 8-,10-, and 12.5-MHz MC68HCOOO
and are valid 'only for product bearing date codes of 8827 and later.
NOTES:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the maximum
columns.
2. The falling edge of S6 trigger both the negation of the strobes (AS and xDS) and the falling edge of E: Either of these events
can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will
occur between the rising edge of the strobes and the falling edge of the E clock.

M68000 FAMILY

REFERENCE

MOTOROLA
3-33

MC68HCOOO

S3· S4

wwwwwwwwww

Al·A23

RfW

DATA
OUT

DATA IN

NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the best case
possibly attainable.

Figure 9. MC68HCOOO to M6800 Peripheral Timing Diagram (Best Case)

MOTOROLA
3-34

M68000 FAMILY

REFERENCE

::Cs

mOl
-nO)

mo
mo

::Co

2"T1

OJ>

-<
SO SI S2 S3 S4 w

w w w w w w w w w w w w

w w w w

w w

w www·w S5 S6 S7 SO

elK

Al·A23

AS
R/Vi

VPA

VMA

DATA OUT

II =\

f
~

DATA IN

NOTE: This timing diagram is included for these who wish to design their own circuit to generate VMA. It shows the worst case
possibly attainable.

a
-i
a

::0

'fa
w'
01»

Figure 10. MC68HCOOO to M6800 Peripheral Timing Diagram (Worst Case)

n
0')

:I:

n
o
o
o

MC68HCOOO

AC ELECTRICAL SPECIFICATIONS - BUS ARBITRATION (VCC=5.0 Vdc:!:5%; GND=O Vdc; TA=lL to TH; see Figure 11)

Num.

Characteristic

Clock High to Address, Data Bus High Impedance
(Maximum)

16.67 MHz
'12F'
Unit
Min Max Min Max Min Max Min Max
8 MHz*

10 MHz* 12.5 MHz*

tCHADZ

tCHCZ

ns
ns

62 '

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

Symbol

Clock High to Control Bus High Impedance

Clock High to BG Asserted

tCHGL

Clock High to BG Negated

tCHGH

BR Asserted to

BG Asserted

tBRLGL

1.5

36'

BR Negated to BG Negated

tBRHGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

BGACK Asserted to BG Negated

tGALGH

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

37A2

BGACK Asserted to BR Negated

tGALBRH

1.5
Clks

tGLZ

1.5

Clks

1.5

Clks

1.5

Clks

1.5
1

Clks

BG Asserted t~ontrol, Address, Data Bus High
Impedance (AS Negated)

BG Width Negated

tGH

1.5

BGACK Width Low

tGAL

1.5

Asynchronous Input Setup Time

tASI

BGACK Negated to AS, DS, RfW Driven

tGASD

1.5

57A

BGACK Negated to FC, VMA Driven

tGAFD

58'

BR Negated to AS, DS, R/W Driven

tRHSD

1.5

tRHFD

1.5

BR Negated to FC, VMA Driven

58A'

Clks

*These specifications represent an improvement over previously published specifications for the 8-, 10-, and 12.5-MHz MC68HCOOO
and are valid only for product bearing date codes of 8827 and later.
NOTES:
1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK.
2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be re-asserted.

eLK

NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, IPLO-IPL2 and VPA guarantees their
recognition at the next falling edge of the clock.

Figure 11. MC68HCOOO Bus Arbitration Timing Diagram

MOTOROLA
3-36

M68000 FAMILY
REFERENCE

MC68HCOOO

PIN ASSIGNMENTS

68-TERMINAL PIN GRID ARRAY .

64-PIN DUAL-IN-LiNE PACKAGE

05
06
07
DB

09
010
UOS
LOS

011
012

R/Vi

013
014

BGACK

IPL2

0
VPA

VCC
A20

N.C.

A12

A13

BOTTOM
VIEW

A18

0
0

GNO

A23

013

UOS

011

N.C.

A14

A16

A17

A19

VCC
/
/

BG / 'R/Vi

All

A15

VCC

OTACK LOS

AID

iPi:T

o ,0

cOOO
BGACK

N.C.

0
0

A21

HALT RESET
GNO

A17
A16

014

A20

A21

A22

015

DID

012

A15

BERR
IPL2

iPi:T

FCI

VMA

FCO

0 0

A18

VPA

IPLO

CLK

A19

RESET
VMA

FC2

GNO
A22

HALT

BERR

015
A23
15

N.C.

A14
24

A13

25
26

A12

FCI

All
AID
A9
A8

Al
30

68-LEAD QUAD PACK

1~lgl§l~g c~8g ~ ~ 8~~~~~
I

I I

OTACK - .l:""'OL9_ _ _ _~~::.!.6~8---~~ - 013
1
BG - 014
BGACK - 015
BR - GNO
VCC - GNO
CLK - A23
GNO - A22
GNO - A21
N.C. 18
- VCC
HALT - A20
RESET - A19
VMA - A18
E- A17
VPA - A16
BERR - A15
IPL2-A14
lPIT - 26
35
- A13
27
I

I I

~~~~~~~~:~~~~~~~~

M68000 FAMILY
REFERENCE

MOTOROLA
3-37

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68008
Technical Summary

16-Bit Microprocessor With
8-Bit Data Bus
This document contains both a summary of the MC68008 as well as a detailed set of parametrics.
The purpose is twofold - to provide an introduction to the MC68008 and support for the sophisticated user. For detailed information on the MC68008 refer to the MC68008 Advance Information

Data Sheet.
The·MC68008 is a member of the M68000 Family of advanced microprocessors. This device allows the design of cost effective systems using 8-bit data buses while providing the benefits of a
32-bit microprocessor architecture. The performance of the MC68008 is greater than any 8-bit microprocessor and superior to several 16-bit microprocessors. Resources available to the MC68008
lIser consist of the following:
•
•
•
•
•
•

17 32-Bit Data and Address Registers
56 Basic Instruction Types
Extensive Exception Processing
Memory Mapped I 0
14 Addressing Modes
Complete Code Compatibility with the MC68000

16 15

I
I

- DO

01
02
- 03
04
- 05
- 06

I
I
I
I

1615

--'-I________

L._ _ _ _ _ _ _

c ---

USER STACKprnNTIR- -

~ : ~ ~s
1:

-1

_ _ _ ~U~R~SO~ S.!..AC~ P~N~R _ _ _ _ J AT

I
I

15
B7
0
SYSTEM BYTE USER BYTE

EIGHT
DATA
REGISTERS

REGISTERS

TWO STACK
POINTERS
PROGRAM
COUNTER
STATUS
REGISTER

Figure 1. Programming Model

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA·_
MOTOROLA
3-38

M68000 FAMILY

REFERENCE

MC68008

INTRODUCTION
The MC68008 allows the design of cost effective systems using 8-bit data buses while providing the benefits
of a 32-bit microprocessor architecture. The performance
of the MC68008 is greater than any 8-bit microprocessor
and superior to several 16-bit microprocessors.
A system implementation based on an 8-bit data bus
reduces system cost in comparison to 16-bit systems due
to a more effective use of components and the fact that
byte-wide memories and peripherals can be used much
more effectively. In addition, the non-multiplexed address and data buses eliminate the need for external demultiplexers, thus further simplifying the system.
The MC68008 has full code compatibility (source and
object) with the MC68000 which allows programs to be
run on either MPU, depending on performance requirements and cost objectives.
The MC68008 is available as a 48-pin dual-in-line package (in plastic or ceramic) and 52-pin quad plastic package. Among the four additional pins of the 52-pin package,
two additional address lines are included beyond the 20
address lines of the 48-pin package. The address reach
of the MC68008 is 1 of 4 megabytes with the 48- or 52pin package, respectively.
The large non-segmented linear address space of the
MC68008 allows large modular programs to be developed and executed efficiently. A large linear address space,
allows program segment sizes to be determined by ,the
application rather than forcing the designer to adopt an
arbitrary segment size without regard to the applicaton's
individual requirements.
The programmer's model is identical to that of the
MC68000, as shown in Figure 1, with seventeen 32-bit
registers, a 32-bit program counter, and a 16-bit status
register. The first eight registers (00-07) are used as data
registers for byte (8-bit), word (16-bit). and long word (32bit) operations. The second set of seven registers (AOA6). the user stack pointer (A7), and the system stack
pointer (AT) may be used as software stack pointers and
base address registers. In addition, the registers may be
used for some simple word and long word data operations. All of the 17 registers may be used as index registers.
The system stack is used by many instructions. The 14
addressing modes allow the creation of user stacks and
queues. While all of the address registers can be used to
create stacks and queues, the A7 register by convention
is used as the system stack pointer. Supplementing this
convention is another address register, AT; also referred
to as the system stack pointer. This powerful concept
allows the supervisor mode and user mode of the
MC68008 to each have their own system stack pointer
(consistently reffered to as SP) without needing to mqve
pointers for each context of use when the mode is
switched.
The system stack pointer (SP) is either the supervisor
stack pointer (A7'=SSP) or the user stack pointer
(A7=USP), depending on the state of the S bit in the
status register. If the S bit is set, indication that the processor is in the supervisor state, then the SSP is the active
system stack pointer and the USP is not used. If the S bit
is clear, indicating that the processor is in the user state,

M68000 FAMILY
REFERENCE

then the USP is the active system stack pointer and the
SSP is protected from user modification.
The status register, shown in Figure 2, may be considered as two bytes, the user byte and the system byte.
The user byte contains five bits defining the overflow (V),
zero (Z). negative (N), carry (C), and extended (X) condition codes. The system byte contains five defined bits.
Three bits are used to define the current interrupt priority;
and any interrupt level higher than the current mask level
will be recognized. (Note that level 7 interrupts are nonmaskable - that is, level 7 interrupts are always processed.) Two additional bits indicate whether the processor is in the trace (T) mode and/or in the supevisor (S)
state.

STATE

INTERRUPT
MASK

ZERO
OVERFLOW
CARRY

Figure 2. Status Register

DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types
are:
•
•
•
•
•

Bits
BCD Digits (4 bits)
Bytes (8 bits)
Words (16 bits)
Long Words (32 bits)
In addition, operations on other data types such as
memory addresses, status word data, etc. are provided
in the instruction set.
Most instructions can use any 'of the 14 addressing
modes which are listed in Table 1. These addressing
modes consist of six basic types.
• Register Direct
• Register Indirect
• Absoulte
• Program Counter Relative
• Immediate
• Implied
The register indirect addressing modes also have the
capability to perform postincrementing, predecrementing, offsetting, and indexing. The program counter relative mode may be used in combination with indexing
and offsetting for writing relocatable programs.

INSTRUCTION SET OVERVIEW
The MC68008 is completely code compatible with the
MC68000. This means that the programs developed for
the MC68000 will run on the Me68008 and visa versa.
This applies equally to either source code or object code.

MOTOROLA
3-39

MC68008

Table 2. Instruction Set Summary

Table 1. Addressing Modes
Syntax

Addressing Modes
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long

xxx.W
xxx.L

Program Counter Relative Addressing
Relative with Offset
Relative with Index Offset

d16(PC)
da(PC,Xn)

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

(An)
(An)+
-(An)
d16(An)
da(An,Xn)

Immediate Data Addressing
Immediate
Quick Immediate

#xxx
#l-#a

Implied Addressing
Implied Register

SR/USP/SP/PC

On
An

NOTES:
On = Data Register
An = Address Register
Xn = Address or Data Register used as Index Register
SR = Status Register
PC = Program Counter
SP = Stack Pointer
USP = User Stack Pointer
( ) = Contents of
da = a-Bit Offset (Displacement)
d16 = 16-Bit Offset (Displacement)
#xxx = Immediate Data

This instruction set was designed to minimize the number of mnemonics remembered by the programmer. To
further reduce the programmer's burden, the addressing
modes are orthogonal.
The instruction set, shown in Table 2, forms a set of
programming tools that include all processor functions
to perform data movement, integer arithmetic, logical
operations, shift and rotate operations, bit manipulation,
BCD opertions, and both program and system control.
Some additional instructions are variations or subsets of
these and appear in Table 3.

SIGNAL DESCRIPTION
The MC68008 is available in two package sizes (48-pin
and 52-pin). The additional four pins of the 52-pin quad
package allow for additional signals: A20, A21, BGACK,
and IPL2.
Throughout this document, references to the address
bus pins (AO-A 19) and the interrupt priority level pins
(lPLO/IPL2,IPL 1) refer to AO-A21, and IPLO, IPL 1, and IPL2
for the 52-pin version of the MC68008.
The input and output signals can be functionally organized into the groups shown in Figure3(a) for. the 48pin version and in Figure 3(b) for the 52-pin version. The
following paragraphs provide a brief description of the

MOTOROLA
3-40

Description

Mnemonic
ABCD
ADD
AND
ASL
ASR

Add Decimal With Extend
Add
Logical AND
Arithmetic Shift Left
Arithmetic Shift Right

Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST

Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test

CHK
CLR
CMP

Check Register Against Bounds
Clear Operand
Compare

DBcc
DIVS
DIVU

Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide

EOR
EXG
EXT

Exclusive OR
Exchange Registers
Sign Extend

JMP
JSR

Jump
Jump to Subroutine

LEA
LINK
LSL
LSR

Lead Effective Address
Link Stack
Logical Shift Left
Logical Shift Right

MOVE
MULS
MULU

Move
Signed Multiply
Unsigned Multiply

NBCD
NEG
NOP
NOT

Negate Decimal with Extend
Negate
No Operation
One's Complement

Logical OR

PEA

Push Effective Address

RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS

Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine

SBCD
Scc
STOP
SUB
SWAP

Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves

TAS
TRAP
TRAPV
TST

Test and Set Operand
Trap
Trap on Overflow
Test

UNLK

Unlink

M68000 FAMILY
REFERENCE

MC68008

Table 3. Variations of Instruction Types
Instruction
Type
ADD

AND

Variation

Description

ADD
ADDA
ADDQ
ADDI
ADDX

Add
Add
Add
Add
Add

AND
ANDI
ANDI to CCR

logical AND
AND Immediate
AND Immediate to
Condition Codes
AND Immediate to
Status Register

ANDI to SR

Address
Quick
Immediate
with Extend

DATA BUS (DO through 07)
This 8-bit, bidirectional, three-state bus is the general
purpose data path. During an interrupt acknowledge cycle,
the external device supplies the vector number on data
lines DO-D7.
ASYNCHROUNOUSBUSCONTROL
Asynchrounous data transfers are handled using the
following control signals: address strobe, read/write, data
strobe, and data transfer acknowledge. These signals are
explained in the following paragraphs.
Address Strobe (AS)
This three-state signal indicates that there is a valid
address on the address bus. It is also used to "lock" the
bus during the read-modify-write cycle used by the test
and set (TAS) instruction.

CMP

CMP
CMPA
CMPM
CMPI

Compare
Compare Address
Compare Memory
Compare Immediate

EOR

EOR
EORI
EORI to CCR

Exclusive OR
Exclusive OR Immediate
Exclusive OR Immediate to
Condition Codes
Exclusive OR Immediate to
Status Register

This three-state signal defines the data bus transfer as
a read or write cycle. The R/IN signal also works in conjunction with the data strobe as explained in the following
paragraph.

MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP

Move
Move
Move
Move
Move
Move
Move
Move
Move

This three-state signal control the flow of data on the
data bus as shown in Table 4. When the R/IN line is high,
the processor will read from the data bus as indicated.
When the RIW is low, the processor will write to the data
bus as shown.

NEG
NEGX

Negate
Negate with Extend

OR
ORI
ORI to CCR

Logical OR
OR Immediate
OR Immediate to
Condition Codes
OR Immediate to
, Status Register

Data Transfer Acknowledge (DTACK)

Subtract
Subtract
Subtract
Subtract
Subtract

This input indicates that the data transfer is completed.
Then the processor recognizes DTACK during a read cycle,
data is latched and the bus cycle is terminated. When
DTACK is recognized during a write cycle, the bus cycle
is terminated.

EORI to SR
MOVE

Address
Multiple Registers
Peripheral Data
Quick
fr.om Status Register
to Status Register
to Condition Codes
User Stack Pointer

Read/Write (RtW)

Data Strobe (OS)

Table 4. Data Strobe Control of Data Bus
OS

NEG

ORI to SR

SUB

SUB
SUBA
SUBI
SUBQ
SUBX

Address
Immediate
Quick
with Extend

R/IN

00-07
No Valid Data

Valid Data Bits 0-7 (Read Cycle)

Valid Data Bits 0-7 (Write Cycle)

BUS ARBITRATION CONTROL
signals and a reference (if applicable) to other paragraphs
that contain more information about the function being
performed.
ADDRESS BUS (48-Pin: AO through A19.
52-Pin: AO through A21)
This unidirectional three-state bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles. During interrupt acknowledge cycles,
address lines A1, A2, and A3 provide information about
what level interrupt is being serviced while .address lines
AO and A4 through A19 (A21) are all driven high.

M68000 FAMILY

REFERENCE

The 48-pin MC68008 contains a simple two,wire arbitration circuit and the 52-pin MC68008 contains a full
three-wire MC68000 bus arbitration control. Both versions are designed to work with the daisy-chained networks, priority encoded networks, or a combination of
these techniques. This circuit is used in determining which
device will be the bus master device:
Bus Request (BR)
This input is wire-ORed with all other devices that could
be bus masters. This device indicates to the' processor
that some other device desires to become the bus master.

MOTOROLA
3-41

MC68008

(a) 48-PIN VERSION

VCC
ADDRESS BUS

GNo {21
CLK

PROCESSOR
STATUS

M6BOO
PERIPHERAL
CONTROL

{

SYSTEM
CONTROL

AO-A 19

~ ~TABUS

FCO
FC1

FC2

RIW

MC6BOOB
MICROPROCESSOR

}

olACK

VPA

iiR

BIT

BERR
RESET

IPLOl2

HALT

iPIT

00-07

ASYNCHRONOUS
BUS
CONTROL

}

BUS
ARBITRATION
CONTROL

}

INTERRUPT
CONTROL

(b) 52-PIN VERSION
Vec
ADDRESS BUS

GNo 121
CLK

PROCESSOR
STATUS

M6BOO
PERIPHERAL
CONTROL

SYSTEM
CONTROL

{

~AS

FCO

DATA BUS

FC1

R!W

FC2

MC6BOOB
MICROPROCESSOR

E
VPA

BERR
RESET
HALT

.
.
...

..
..

...

AoA21

•
•

DTACK

iiR
BIT
BGACK

•

0007

}

ASYNCHRONOUS
BUS
CONTROL

}

BUS
ARBITRATION
CONTROL

}

INTERRUPT
CONTROL

IPLO

iPIT
IP1.2

Figure 3_ Input and Output Signals
Bus requests may be issued at any time in cycle or even
if no cycle is being performed.

2. address strobe is inactive which indicates that the
microprocessor is not using the bus,

Bus Grant (BG)

3. data transfer acknowledge is inactive which indicates that neither memory nor peripherals are using
the bus, and

This output indicates to all other potential bus master
devices that the processor will release bus control at the
end of the current bus cycle.
Bus Grant Acknowledge (BGACK)
This input, available on the 52-pin version only, indicates that some other device has become the bus master_
This signal should not be asserted until the following four
conditions are met:
1. a bus grant has been recieved,

MOTOROLA
3-42

4. bus grant acknowledge is inactive which indicates
that no other device is still claiming bus mastership.
NOTES
1) There is a two-clock interval straddling the
transition of AS from the inactive state to
the active state during which BG can not
be issued.
2) If an existing MC68000 system is retrofitted
to use the MC68008; 48-pin version (using

M68000 FAMILY

REFERENCE

MC68008

BR and BG only). the existing BR and
BGACK signals should be ANDed and the
resultant signal connected to the
MC68008's BR.
INTERRUPT CONTROL (48-Pin: IPLO/lPL2, IPL 1
52-Pin: IPLO, IPL1, IPL2)
These input pins indicate the encoded priority level of
the device requesting an interrupt. The MC68000 and the
52-pin MC68008 MPU's use three pins to encode a range
of 0-7 but, for the 48-pin MC68008 only two pins are
available. By connecting the IPLO/IPL2 pin to both the IPLO
and IPL2 inputs internally, the 48-pin encodes values of
0,2,5, and 7. Level zero is used to indicate that there are
no interrupts pending and level seven is a non-maskable
edge-triggered interrupt. Except for level seven, the requesting level must be greater than the interrupt mask
level contained in the processor status register before the
processor will acknowledge the request.
The level presented to these inputs is continually monitored to allow for the case of a requesting level that is
less than or equal to the processor status register level
to be followed by a request that is greater than the processor status register level. A satisfactory interrupt condition must exist for two successive clocks before
triggering an internal interrupt request. An interrupt acknowledge sequence is indicated by the function codes.

SYSTEM CONTROL
The system control inputs are used to either reset or
halt the processor and to indicate to the processor that
bus errors have occurred. The three system control signals are explained in the following paragraphs.
~us

Error (BERR)

This input informs the processor that there is a problem
with the cycle currently being executed. Problems may
be a result of:
1) nonresponting devices,

external RESET signal. An internally generated reset (result of a reset instruction) causes all external devices to
be reset and the internal state of the processor is not
affected. A total system reset (processor and external
devices) is the result of external HALT and RESET signals
applied at the same time.
Halt (HALT)
When this bidirectional line is driven by an external
device, it will cause the processor to stop at the completion of the current bus cycle. When the processor has
been halted using this input, all control signals are inactive and all three-state lines are put in their high-impedence state.
When the processor has stopped executing instructions, such as in a double-bus fault condition, the halt
line is driven by the processor to indicate to external
devices that the processor has stopped.

M6800 PERIPHERAL CONTROL
These control signals are used to allow the interfacing
of synchronous M6800 peripheral devices with the asynchronous MC68008. These signals are explained in the
following paragraphs.
The MC68008 does not supply a valid memory address
(VMA) signal like that of the MC68000. The VMA signal
indicates to the M6800 peripheral devices that there is a
valid addess on the address bus and that the processor
is synchronized to the enable clock. This signal can be
produced by a TTL circuit (see a sample circuit in Figure
4). The VMA signal, in this circuit only responds to a valid
peripheral address (VPA) input which indicates that the
peripheral is an M68000 Family device.
The VPA decode shown in Figure 4 is an active high
decode indicating that address strobe (AS) has been asserted and the address bus is addressing an M6800 peripheral. The VPA output of the circuit is used to indicate
to the MC68008 that the data transfer should be synchronized with the enable (E) signal.

2) interrupt vector number acquisition failure,

Enable (E)

3) illegal access request as determined by a memory
management unit, or

This signal is the standard enable signal common to
all M6800 type peripheral devices. The period for this
output is ten MC68008 clock periods (six clocks low, four
clocks high).

4) various other application dependent errors.
The bus error signal interacts with the halt signal to
determine if the current bus cycles should be re-executed
or if exception processing should be performed. A summarization of the interaction is as follows:
BERR

HALT

High
High
Low
Low

High
Low
High
Low

Resulting Operation
Normal Operation
Single Bus Cycle Operation
Bus Error - Exception Processing
Bus Error Re-Run Current Cycle

Reset (RESET)
This bidirectional signal line acts to reset (start a system
initialization sequence) the processor in response to an

M68000 FAMILY
REFERENCE

Valid Peripheral Address (VPA)
This input indicates that the device or region addressed
is an M6800 Family device and that data transfer should
be synchronized with the enable (E) signal. This input
also indicates that the processor should use automatic
vectoring for an interrupt.

PROCESSOR STATES (FCO, FC1, and FC2)
These function code outputs indicate the state (user or
supervisor) and the cycle type currently being executed,
as shown in Table 5. The information indicated by the
function code output is valid whenever address strobe
(AS) is active.

MOTOROLA
3-43

MC68008

VPA DECDDE (ADDRESS
DE CD DE • STRDBE) -

SN74lS73
A

SN74lS73

......- - 1 J ,

VMA (TD MC6S00
DEVICES)

ClK _ _ _ _ _ _- . J

L....------l~

VPA (TO MC6S00S)

Figure 4. External VMA Generation

Table 5. Function Code Outputs
Function Code Output
Cycle Type
FC2

FC1

FCO

Low

High

User Data

Low

High

Low

User Program

(Undefined, Reserved)

Low

High

(Undefined, Reserved)

High

Low

(Undefined, Reserved)

High

Low

High

Supervisor Data

High

Low

Supervisor Program

High'

High

Interrupt Acknowledge

CLOCK (ClK)
The clock input is a TTL-compatible signal that is iriternally buffered for development of the internal clocks
needed by the processor. The clock input shall be a const",nt frequency.

VCC AND GND
Power is supplied to the processor using these two
signals. VCC is power and GND is th~ ground connection.

The address and data buses are separated non-multiplexed parallel buses. Data transfer is accomplished with
an asynchrounous bus structure that uses handshaes to
ensure the corect movement of data. In all cycles, the
bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. 'In
addition, the bus master is responsible for deskewing the
acknowledge and data signals from the slave device.
The following paragraphs explain the read, write, and
read-modify-write cycles. The indivisible read-modifywrite cycle is the method used by the MC680D8 for interlocked multiprocessor communications.

READ CYCLE
During a read cycle, the processor receives data from
the memory or a pripheral device. The processor reads
bytes of data in all cases. If the instruction specifies a
word (or double word) operation, the processor reads
both bytes. When the instruction specifies byte operation,
the processor uses AD to determine which byte to read
and then issues data strobe.

SIGNAL SUMMARY
Table 6 is a summary of all the signals discussed in
the previous paragraphs.

DATA TRANSFER OPERATIONS
Transfer of data between devices involves the follo~ing leads:
1) address bus AO through A21,
2) data bus DO through 07, and
3) control signals.

MOTOROLA
3-44

READ-MODIFY-WRITE CYCLE
The read-modify-write cycle performs a byte read,
modifies the data in the arithmetic-logic unit, and writes
the data back to the same address. In the MC68DD8, this
cycle is indivisible in that the address strobe is asserted
throughout the entire cycle. The test and set (TAS) instruction Uses the cycle to provide meaningful communication between processors in a multiple processor
environment. This instruction is the only instruction that
uses the read-modify-write cycle and since the test and
set instruction only operates on bytes, all read-modifywrite cycles are byte operations.

M68000 FAMILY
REFERENCE

MC68008

Table 6. Signal Summary
Hi-Z
Signal Name

Input/Output

Active State

AO-A19 (A21)

Output

00-07

Input/Output

Address Strobe

ReadlWrite

Data Strobe

Address Bus

Mnemonic

Data Bus

Data Transfer Acknowledge

on HALT

on BGACK

High

Yes

High

Yes

Output

Low

Yes

RiW

Output

Read - High
Write - Low

No
No

Yes
Yes

Output

Low

Yes
No

DTACK

Input

Low

Bus Request

Input

Low

Bus Grant

Output

Low

BGACK

Input

Low

Interrupt Priority Level

IPLx

Input

Low

Bus Error

BERR

Input

Low

Reset

RESET

Input/Output

Low

No*

Halt

HALT

Input/Output

Low

No*

Output

High

Bus Grant Acknowledge**

Enable

-VPA

Input

Low

FCO, FC1, FC2

Output

High

Yes

High

Valid Peripheral Address
Function Code Output

CLK

Input

Power Input

VCC

Input

Ground

GND

Input

Clock

*Open Drain
**52-Pin Version Only

PROCESSING STATES
The MC68008 is always in one of three processing
states: normal, exception, or halted.
NORMAL PROCESSING
The normal processing state is that associated with
instruction execution; the memory references are to fetch
instructions and operands, and to store results. A special
case of the normal state is the stopped state which the
processor enters when a STOP instruction is executed.
In this state, no further memory references are made.

processing can be forced by an interrupt, by a bus error,
or by a reset. Exception processing is designed to provide
an efficient context switch so that the processor may
handle unusual conditions.
HALTED PROCESSING
The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs,
the processor assumes that the system is unusable and
halts. Only an external reset can restart a halted processor. Note that a processor in the stopped state is not in
the halted state, nor vise versa.

EXCEPTION PROCESSING
The exception processing state is associated with interupts, trap instructions, tracing, and other exceptional
conditions,. The exception may be internally generated
by an instruction or by an unusual condidion arising during the execution of an instruction. Externally, exception

M68000 FAMILY
REFERENCE

INTERFACE WITH M6800 PERIPHERALS
Motorola's extensive line of M6800 peripherals are
compatible with the MC68008. Some of these devices
which are particularly useful are:

MOTOROLA
3-45

MC68008

MC6821
MC6840
MC6845
MC6850
MC6852

Peripheral Interface Adapter
Programmable Timer Module
CRT Controller
Asynchronous Communications Interface
Adapter
Synchronous Serial Data Adapter

MC6854 Advanced Data Link Controller
To interface the synchronous M6800 peripherals with the
asynchronous MC68008, the processor modifies its bus
cycle to meet the M6800 cycle requirements whenever
an M6800 device address is detected. This is possible
since both processors use memory mapped 1/0.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
. Value

Symbol

Rating

Unit

VCC

-0.3 to +7.0

Input Voltage

Vin

-0.3 to + 7.0

Operating Temperature Range
MC68008
MC68008C

TL to TH
o to 70
-40 to 85

°c

T stg

- 55 to 150

°C

Supply Voltage

Storage Temperature

The device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, normal precautions should be taken to avoid application
of voltages higher than maximum-rated voltages to these high-impedance circuits. Tying
unused inputs to the appropriate logic voltage level (e.g., either GNO or Vecl enhances
reliability of operation.

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance (Still Airl
Ceramic, Type LC
Plastic, Type P
Plastic, Type FN

Symbol

Value

Symbol

Value

40
40
50

Rating
°C/W

!lJC

HJA

15*
20*
30*

*Estimated

DC ELECTRICAL CHARACTERISTICS (VCC=5.0 Vdc±5%; GNO=OVdc; TA=TL to TH; see Figures 5, 6, and 7l
Symbol

Min

Max

Unit

Input High Voltage

VIH

2.0

VCC

Input Low Voltage

VIL

GNO -0.3

0.8

liN

f.1A

2.5
20

ITSI.

f.1A

Characteristic

Input Leakage Current ((/ 5.25 V

BERR, BGACK, BR, OTACK, CLK, IPLO/IPL2, VPA
HALT, RESET

Three-State (Off Statellnput Current ((/ 2.4 V/O.4 V

AS, AO-A18, A20, A21,
00-07, FCO-FC2, OS, R/W, VMA

Output High Voltage (lOH = -400 f.1Al
E*
E, AS, AO-A19, A20, A21, BG, 00-07, FCO-FC2, OS, R/W, VMA
(lOH = - 400 f.1Al

VOH

Output Low Voltage
(lQL = 1.6 mAl
(lQL =3.2 mAl
(lQL =5.0 mAl
(lQL =5.3 mAl

VOL

Capacitance (Vin = 0 V, TA = 25°C, Frequency = 1 MHzl**
Load Capacitance

HALT
All Others

2.4
V

HALT
AO-A19, A20, A21, FCO-FC2
RESET
E, AS, 00-07, OS, R/W, VMA

Power Oissipation (see POWER CONSIDERATIONSl

VCC-0.75
2.4

0.5
0.5
0.5
0.5

PO***

Cin

20.0

70
130

*With external pullup resistor of 1.1 n.
**Capacitance is periodically sampled rather than 100% tested.
***Ouring normal operation instantaneous Vec current requirements may be as high as 1.5 A.

MOTOROLA
3·46

M68000 FAMILY
REFERENCE

MC68008

case to the outside ambient air (!lCA). These terms are
related by the equation:
UJA = 0JC + 0CA
(4)
0JC is device related and cannot be influenced by the
user. However, OCA is user dependent and can be minimized by such thermal management techniques as heat
sinks, ambient air cooling, and thermal convection. Thus,
good therlTlal management on the part of the user can
significantly reduce (lCA so that 0JA approximately equals
(lJC. Substitution of (lJC for (lJA in equation 1 results in
a lower semiconductor junction temperature.
Table 7 summarizes maximum power dissipation and
average junction temperature for the curve drawn in Figure 5, using the minimum and maximum values of ambient temperature for different packages and substituting
(lJC for (lJA (assuming good thermal management). Table 8 provides the maximum power dissipation and average junction temperature for the MC68000 assuming
that no thermal management is applied (i.e., still air).

POWER CONSIDERATIONS
The average die-junction temperature, TJ' in °c can be
obtained from:
(1)

where:
TA
0JA

= Ambient Temperature, °c
= Package Thermal Resistance, Junction-toAmbient, °CIW
Po
= PINT+ PliO
PINT = ICC x VCC' Watts - Chip Internal Power
PliO = Power Oissipation on Input and Output Pins
- User Oetermined
For most applications PI/O-f

(")

::c

CIO

C)
C)

These waveforms should only be referenced to the edge-to-edge measurement of the timing specifications. They are
not intended as a functional description of the input and output signals. Refer to other functional descriptions and their
related diagrams for device operation.

5I 52 53 54

w, w

W w

w' 'w ,w

w, w

w" w

CIO

55 56 57 50

eLK

AI·A23

R/W

m
VMA

DATA OUT

DATA IN

l
\-

NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly attainable

s:
en

::a~

.,,0

m."
:XJl>

ms:
~r=
m<

Figure 11. MC68008 to M6800 Peripheral Timing Diagram (Worst Case)

MC68008

ACELECTRICAL SPECIFICATIONS - BUS ARBITRATION (VCC=5.0 Vdc±5%;GND=0 Vdc; TA=TL to TH;
see Figures 12, 13, and 14)

Characteristic

Num

Symbol

8 MHz·

10 MHz·

Unit

Min

Max

Min

Max

70
70

62.

Clock High to Address, Data Bus High Impedance (Maximum)

Clock High to Control Bus High Impedance

tCHCZ

Clock High to BG Asserted

tCHGL

Clock High to BG Negated

tCHGH

BR Asserted to BG Asserted

tBRLGL

1.5

3.5

1.5

3.5

Clks

36'

BR Negated to BG Negated

tBRHGH

1.5

3.5

1.5

3.5

Clks

BGACK Asserted to BG Negated

tGALGH

1.5

3.5

1.5

3.5

Clks

37A2

BGACK Asserted to BR Negated

tGALBRH

1.5
Clks

tGLZ

ns
Clks

BGAsserted to Control, Address, Data Bus High Impedance
(AS Negated)

tCHADZ

BG Width Negated

tGH

1.5

BGACK Width Low

tGAL

1.5

Asynchronous Input Setup Time

tASI

BGACK Negated to AS, DS, RfW Driven

tGASD

1.5

Clks

1
1.5

Clks

57A

BGACK Negated to FC, VMA Driven

tGAFD

58'

BR Negated to AS, DS, RfW Driven

tRHSD

1.5

BR Negated to FC, VMA Driven

tRHFD

58A'

Clks

Clks
Clks

*These specifications represent an improvement over previously published specifications for the 8-, 10-; and 12.5-MHz MC68008 and
are valid only for product bearing date codes of 8827 and later.

NOTES:'
1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK.
2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded. BG may be reasserted.

M68000 FAMILY

REFERENCE

MOTOROLA
3-57

MC68008

These waveforms should only be referenced to the edge-to-edge measurement of the timing specifications.
They are not intended as a functional description of the input and output signals. Refer to other functional
descriptions and their related diagrams for device operation.

NOTE:
1. 52-Pin Version of MC68008 Only

Figure 12. MC68008 Bus Arbitration Timing - Idle Bus Case
(52-pin Version Only)

MOTOROLA
3-58

M68000 FAMILY

REFERENCE

MC68008

CLK

R/W

FCo·FC2

AO·A19

00·07

-t-------:..----,-

...------

ms:
~r=

Figure 11. MC68010 to M6800 Peripheral Timing Diagram (Worst Case)

MC68010

AC ELECTRICAL SPECIFICATIONS - BUS ARBITRATION (VCC=5.0 Vdc::':5%; GND=O Vdc; TA=lL to TH;
see Figures 12,13, and 14)

Characteristic

Symbol

Clock High to Address, Data Bus High
Impedance (Maximum)

Num.

8 MHz·

10 MHz·

12.5 MHz·

Min

Max

Unit

Min

Max

Min

Max

tCHADZ

Clock High to Control Bus High Impedance

tCHCZ

Clock High to BG Asserted

tCHGL

33
34

Clock High to BG Negated

tCHGH

BR Asserted to BG Asserted

tBRLGL

1.5

3.5.

1.5

3.5

1.5

3.5

Clks

36'

BR Negated to BG Negated

tBRHGH

1.5

3.5

1.5

3.5

1.5

3.5

Clks

BGACK Asserted to BG Negated

tGALGH

1.5

3.5.

1.5

3.5

1.5

3.5

Clks

37A2

BGACK Asserted to BR Negated

tGALBRH

1.5
Clks

_tGLZ

1.5

Clks

1.5

Clks

10
1.5

BG Asserted to Control, Address, Data Bus
High Impedance (AS Negated)

BG Width Negated

tGH

1.5

BGACK Width Low

tGAL

1.5

Asynchronous Input Setup Time

tASI

BGACK Negated to AS, DS, RIW Driven

tGASD

1.5

57A

BGACK Negated to FC, VMA Driven

tGAFD

58'

BR Negated to AS, DS, Rm Driven

tRHSD

1.5

tRHFD

58A'

BR Negated to FC, VMA Driven

ns
Clks
Clks
Clks
Clks

*These specifications represent an improvement over previously published specifications for the 8-,10-, and 12.5-MHz MC68010 and
are valid only for product bearing date codes of 8827 and later.
NOTES:
1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK.
2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.

M68000 FAMILV
REFERENCE

MOTOROLA
3-81

MC68010

NOTE:
1. 52-Pin Version of MC68008 Only

Figure 12. MC68010 Bus Arbitration Timing -

MOTOROLA
3-82

Idle Bus Case

M68000 FAMILY

REFERENCE

MC68010

CLK

R/W

FCO-FC2

AO-A19

00-07
NOTE:
1. 52-Pin Version of MC68008 Only

Figure 13. MC68010 Bus Arbitration Timing -

M68000 FAMILY

REFERENCE

Active Bus Case

MOTOROLA
3-83

MC68010

These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications.
They are not intended as a functional description of the input and output signals. Refer to other functional des'criptions
and their related diagrams for device operation.

NOTE:
1. 52-Pin Version of MC68008 Only

Figure 14. MC68010 Bus Arbitration Timing -

MOTOROLA
3-84

Multiple Bus Requests

M68000 FAMILY
REFERENCE

MC68010

PIN ASSIGNMENTS

68-Pin Quad Pack

64-Pin Dual-In-Line Package

~1~1~I~O-NM.~w~rom~=~
~~~~ooooooooooooo

11111111111111111

03
07
01

08
09

AS
UOS
lOS

011
012
013

R/W
OTACK

014
015
GNO

BG
BGACK

A23
A22

VCC
ClK
GNO

A21

OTACK- h~_ _ _ _--,-l-",68",--_ _ _~~ -013

BG-

-014
-015
-GNO
-GNO
-A23
-A22
-A21
-Vec
-A20
-A19
-A18
-A17
-A16
-A15
-A14
-A13

BGACK-

EfR-

VCCCLKGNOGNDN.C.HALTRESETVMAEVPABERRIPL2-

TOP VIEW

iPLi- 2~7

VCC
A20

HALT
RESET

Al9

VMA
E
VPA

Al8
Al7
Al6

BERR
IPl2

Al5
Al4

iPD

A13
A12
All
Al0

IPlO
FC2
FCl

A9
A8

FCO
Al
A2

A3
A4

Top View

68-Pin Grid Array

0000000000

N.C

FC2

FCO

N C

0000000000
BEAA

IPlO

FCl

N.C

000
E
iPL2 iPLi
o 0

HALT

ClK

AlB

o
o

GND

LOS

VCC

GND

A/W

UDS

A12

BOTTOM
VIEW

BG /

All

A15

AESET

VCC

DTACK

A13

oBR 0
o 0 ~CJ
o /d 0
o 00

BGACK

AlO

A14

000
o 0

0
DO

All

0
0
0

A19

A20

A21

000
0 0 0 0 0 0
D3

0 0
D2

A16

D13

A23

A22

Dll

D14

D15

0 0 0 0 0
D5

DlO

D12
lO

M68000 FAMILY
REFERENCE

MOTOROLA
3-85

MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC68020

Technical Summary

32-Bit Virtual Memory
Microprocessor
The MC68020 is the first full 32-bit implementation of the M68000 Family of microprocessors
from Motorola. Using Motorola's advanced HCMOS technology, the MC68020 is implemented with
32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing
modes.
The main features of the MC68020 are:
• Object Code Compatible with Earlier M68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High Level Languages
• New Bit Field Data Type Accelerates Bit-Oriented Applications, i.e., Video Graphics
• Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth
• Coprocessor Interface to Companion 32-Bit Peripherals - the MC68881 and MC68882 Floating
Point Coprocessors and the MC68851 Paged Memory Management Unit
• Pipelined Architecture with High Degree of Internal Parallalism Allowing Multiple Instructions to
be Executed Concurrently
• High Performance Asynchronous Bus is Non-Multiplexed and Full 32-Bits
• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peirpherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and 5 Special Purpose Control Registers
• 18 Addressing Modes and 7 Data Types
• 4-Gigabyte Direct Addressing Range
• Selection of Processor Speeds: 12.5,16.67,20,25, and 33.33 MHz

Figure 1. MC68020 Block Diagram

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA _
MOTOROLA
3-86

M68000 FAMILY

REFERENCE

MC68020

INTRODUCTION
The MC68020 is a high-performance 32-bit microprocessor. It is the first microprocessor to have evolved from
a 16-bit machine to a full 32-bit machine that provides
32-bit address and data buses as well as 32-bit internal
structures. Many techniques were utilized to improve performance and at the same time maintain compatibility
with other processors of the M68000 Family. Among the
improvements are new addressing modes which better
support high-level language structures, an expanded instruction set which provides 32-bit operations for the limited cases not supported by the MC68000 and the
MC68010, and several new instructions which support
new data types. For special-purpose applications when
a general-purpose processor alone is not adequate, a
coprocessor interface is provided.
The MC68020 is a high-performance microprocessor
implemented in HCMOS, Motorola's low power, small
geometry process. This process allows CMOS and HMOS
(high density NMOS) gates to be combined on the same
device. CMOS structures are used where speed and low
power is required, and HMOS structures are used where
minimum silicon area is desired. This technology enables
the MC68020 to be very fast while consuming less power
(less than 1.5 watts), and still have a reasonably small
die size.

Figure 1 is a block diagram of the MC68020. The processor can be divided into two main sections: the bus
controller and the micromachine. This division reflects
the autonomy with which the sections operate.
The bus controller consists of the address and data
pads and multiplexers required to supportdynamic bus
sizing, a macro bus controller which schedules the bus
cycles on the basis of priority with two state machines
(one to control the bus cycles for operand accesses and
the other to control the bus cycles for instruction accesses), and the instruction cache with its associated con-

trol.
The micromachine consists of an execution unit, nanorom and microrom storage, an instruction decoder, an
instruction pipe, and associated control sections. The execution unit consists of an address section, an operand
address section, and a data section. Microcode control is
provided by a modified two-level store of microrom and
nanorom. Programmed logical arrays (PLAs) are used to
provide instruction decode and sequencing information.
The instruction pipe and other individual control sections
provide the secondary decode of instructions and generate the actual control signals that result in the decoding
and interpretation of nanorom and microrom information.
As shown in the programming models (Figures 2 and
3) the MC68020 has sixteen 32-bit general-purposed registers, a 32-bit program counter, two 32-bit supervisor

B 7
DO
01

03
04

DATA REGISTERS

05
06

07
. 31

15
AO

Al
A2
A3

ADDRESS REGISTERS

A4
A5
A6

A7IUSP)

USER STACK POINTER

PROGRAM COUNTER

CCR

CONDITION CODE REGISTER

__________________________________________~I
15

____________~

C~ ~ ~ ~ jJ~ ~ ~ ~ _L.I_ _ _ _ _

----J

Figure 2. User Programming Model

M68000 FAMILY

REFERENCE

MOTOROLA
3-87

MC68020

I A7' (lSP!
16

INTERRUPT STACK POINTER

I A7" (MSP!
15

8 7

MASTER STACK POINTER

0
(CCR!

I SR

STATUS REGISTER

31
VBR

VECTOR BASE REGISTER

SFC

ALTERNATE FUNCTION
CODE REGISTERS

DFC
31
~

____________________________________________~I CACR

CACHE CONTROL REGISTER

CAAR

CACHE ADDRESS REGISTER

~------------------------------------------------------~

Figure -3, Supervisor Programming Model Supplement

stack pointers, a 16-bit status register, a 32-bit vector base
register, two 3-bit alternate function code registers, and
two 32-bit cache handling (address and control) registers.
Registers DO-D7 are used as data registers for bit and bit
field (1 to 32 bit), byte (8 bit), word (16 bit), long word
(32 bit), and quad word (64 bit) operations. Registers AOA6 and the user, interrupt, and master stack pointers are
address registers that may be used as software stack
pointers or base address registers.' In addition, the address registers may be used for word and long word
operations. All of the 16 (DO-D7, AO-A7) registers may be
used as index registers.
The status register (Figure 4) contains the interrupt
priority mask (three bits) as well as the condition codes:
extend (X). negate (N), zero (Z), overflow (V), and carry
(C). Additional control bits indicate that the processor is
in the trace mode (T1 or TO). supervisor/user state (5).
and master/interrupt state (M).
All microprocessors of the M68000 Family support instruction tracing (via the TO status bit in the MC68020)
where each instruction executed is followed by a trap to

a user-defined trace routine. The MC68020 adds the capability to trace only the change of flow instructions
(branch, jump, subroutine call and return, etc.) using the
T1 status bit. These features are important for software
program development and debug.
The vector base register is used to determine the runtime location of. the exception vector table in memory,
hence it supports multiple vector tables so each process
or task can properly manage exceptions independent of
each other.
The M68000 Family processors distinguish address
spaces as supervisor/user and program/data. These four
combinations are specified by the function code pins (FCO/
FClIFC2) during bus cycles, indicating the particular address space. Using the function codes, the memory subsystem can distinguish between authorized access (supervisor mode is privileged access) and unauthorized access (user mode may not have access to supervisor
program or data areas). To support the full privileges of
the supervisor, the alternate function code registers allow
the supervisor to specify an access to user program or
'USER BYTE
(CONDITION CODE REGISTER!

SYSTEM BYTE

MASTERIINTERRUPT STATE
SUPERVISOR/USER STATE
TRACE ENABLE
TO - TRACE ON CHANGE OF FLOW (BRA, JUMP, ETC.!
Tl - TRACE ALL INSTRUCTIONS

ZERO
OVERFLOW
CARRY

Figure 4. Status Register

MOTOROLA
3-88

M68000 FAMILY

REFERENCE

MC68020

data areas by preloading the SFC/DFC registers appropriately.
The cache registers (control- CACR, address- CAAR)
allow software manipulation of the on-chip instruction
cache. Control and status accesses to the instruction cache
are provided by the cache control register (CACR), while
the cache address register (CAAR) holds the address for
those cache control functions that require an address.

DATA TYPES AND ADDRESSING MODES
Seven basic types are supported. These data types are:
• Bits
• Bit Fields (String of consecutive bits, 1-32 bits long)
• BCD Digits (Packed: 2 digits/byte,
Unpacked: 1 digit/byte)
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long Word Integers (32 bits)
• Quad Word Integers (64 bits)
In addition, operations on other data types, such as memory addresses, status word data, etc., are provided in the
instruction set. The coprocessor mechanism allows direct
support of floating-point data types with the MC68881
floating-point coprocessor, as well as specialized userdefined data types and functions.
The 18 addressing modes, shown in Table 1, include
nine basic types:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Memory.lndirect
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Program Counter Memory Indirect
• Absolute
• Immediate
The register indirect addressing modes support
postincrement, predecrement, offset, and indexing.
Programmers find these capabilities particularly useful
for handling advanced data structures common to sophisticated applications and high level languages. The
program counter relative mode also has index and offset
capabilities; programmers find that this addressing mode
is required to support position-independent software. In
addition to these addressing modes, the MC68020 provides data operand sizing and scaling; these features provide performance enhancements to the programmer.

INSTRUCTION SET OVERVIEW
The MC68020 instruction set is shown in Table 2. Special emphasis has been given to the instruction set's support of structured high-level languages and sophisticated

M68000 FAMILY
REFERENCE

operating systems. Each instruction, with few exceptions,
operates on bytes, words, and long words and most instructions can use any of the 18 addressing modes. Many
instruction extensions have been made on the MC68020
to take advantage of the full 32-bit operation where, on
the earlier M68000 Family members, only 8- and 16-bit
values were used. The MC68020 is upward source- and
object-level code compatible with the family because it
supports all of the instructions that previous family members offer. Additional instructions are now provided by
the MC68020 in support of its advanced features.
BIT FIELD OPERATIONS

The MC68020 supports variable length bit field operations up to 32 bits. A bit field may start in any bit position
and span any address boundary for the full length of the
bit field, up to the 32 bit maximum. The bit field insert
(BFINS) inserts a value into a field. Bit field extract unsigned (BFEXTU) and bit field extract signed (BFEXTS)
extract a unsigned or signed value from the field. BFFFO
finds the first bit in a bit field that is set. To complement
the M68000 bit manipulation instruction, there are bit
field change, clear, set, and test instructions (BFCHG,
BFCLR, BFSET, BFTST). Using the on-chip barrel shifter,
the bit and bit field instructions are very fast and particularly useful in applications using packed bits and bit
fields, such as graphics and communications.

BINARY CODED DECIMAL (BCD) SUPPORT

The M68000 Family supports BCD operations including
add, subtract, and negation. The MC68020 adds the PACK
and UNPACK operations for BCD conversions to and from
binary form as well as other conversions, e.g., ASCII and
EBCDIC. The PACK instruction reduces two bytes of data
into a single byte while UNPACK reverses the operation.
BOUNDS CHECKING

Previous M68000 Family members offer variable bounds
checking only on the upper limit of the bound. The underlying assumption is that the lower bound is zero. This
is expanded on the MC68020 by providing two new instructions, CHK2 and CMP2. These instructions allow
checking and comparing of both the upper and lower
bounds. These instructions may be either signed or unsigned. The CMP2 instruction sets the condition codes
upon completion while the CHK2 instruction, in addition
to setting the condition codes, will take a system trap if
either boundary condition is exceeded.
SYSTEM TRAPS

Three additions have been made to the system trap
capabilities of the MC68020. The current TRAPV (trap on
overflow) instruction has been expanded to a TRAPcc
format where any condition code is allowed to be the
trapping condition. And, the TRAPcc instruction is expanded to optionally provide one or two additional words
following the trap instruction so user-specified information may be presented to the trap handler. These additional words can be used when needed to provide simple
error codes or debug information for interactive runtime
debugging or post-mortem program dumps. Compilers

MOTOROLA
3-89

MC68020

Table 1. MC68020 Addressing Modes
Addressing Modes

Syntax

Dn
An

(An)
(An)+
-(An)
(d 16,An)

Indirect
Indirect with Post Increment
Indirect with Predecrement
Indirect with Displacement

Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)

(d 8,An,Xn)
(bd,An,Xn)

Memory Indirect
Memory Indirect Post-Indexed
Memory Indrect Pre-Indexed

([bd,An).Xn,od)
([bd,An,Xn).od)

Program Counter Indirect with Displacement

(d 16 ,PC)

Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)

(d 8 ,PC,Xn)
(bd,PC,Xn)

Program Counter Memory Indirect
PC Memory Indirect Post-Indexed
PC Memory Indirect Pre-Indexed

([bd,PC).Xn,od)
([bd,PC,Xn).od)

Absolute
Absolute Short
Absolute Long

xxx.W
xxx.L

Immediate

#(data)

NOTES:
Dn = Data Register, DO-D7
An = Address Register, AO-A7
d 8, d 16 = A twos-complement, or sign-extended displacement; added as part of the
effective address calculation; size is 8 (d 8 ) or 16 (d 16 ) bits; when omitted,
assemblers use a value of zero.
Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE,
where SIZE is.W or.L (indicates index register size) and SCALE is 1, 2,4, or
8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional.
bd = A twos-complement base displacement; when present, size can be 16 or 32
bits.
od = Outer displacement, added as part of effective address calculation after any
memory.indirection; use is optional with a size of 16 or 32 bits.
PC = Program Counter
(data) = Immediate value of 8, 16, or 32 bits
( ) = Effective Address
[1 = Use as indirect address to long word address.

may provide direction to run-time execution routines towards handling of specific conditions.
The breakpoint instruction, BKPT, is used to support
the program breakpoint function for debug monitors and
real-time in-circuit or hardware emulators, and the operation will be dependent on the actual system implementation. Execution of this instruction causes the
MC68020 to run a breakpoint acknowledge bus cycle,
with a 3-bit breakpoint identifier placed on address lines
A2, A3, and A4. This 3-bit identifier permits up to eight
breakpoints to be easily differentiated. The normal response to the MC68020 is an operation word (typically
an instruction, originally replaced by the debugger with

MOTOROLA
3-90

the breakpoint instruction) placed on the data lines by
external debugger hardware and the breakpoint acknowledge cycle properly terminated. The MC68020 then executes this operation word in place of the breakpoint
instruction. The debugger hardware can count the number of executions of each breakpoint and halt execution
after a pre-determined number of cycles.

MULTI-PROCESSING
To further support multi-processing with the MC68020,
a compare and swap instruction, CAS, has been added.
This instruction makes use of the read-modify-write cycle
to compare two operands and swap a third operand

M68000 FAMILY

REFERENCE

MC68020

Table 2. Instruction Set
Mnemonic

Description

Mnemonic

ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR

Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left and Right

Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST

Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit

CALLM
CAS
CAS2
CHK
CHK2

Call Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and
Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and
Lower Bounds

CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS, DIVSL
DIVU, DIVUL

Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide

EOR
EORI
EXG
EXT,EXTB

Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend

ILLEGAL

Take Illegal Instruction Trap

JMP
JSR

Jump
Jump to Subroutine

cpBCC
cpDBcc

Branch Conditionally
Test Coprocessor Condition,
Decrement and Branch
Coprocessor General Instruction

Description

LEA
LINK
LSL,LSR

Load Effective Address
Link and Allocate
Logical Shift Left and Right

MOVE
MOVEA
MOVE CCR
MOVE SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEO
MOVES
MULS
MULU

Move
Move Address
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Ouck
Move Alternate Address Sapce
Signed Multiply
Unsigned Multiply

NBCD
NEG
NEGX
NOP
NOT

Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement

OR
ORI

Logical Inclusive OR
Logical Inclusive OR Immediate

PACK
PEA

Pack BCD
Push Effective Address

RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
RTS

Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore Codes
Return from Subroutine

SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBO
SUBX
SWAP

Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words

TAS
TRAP
TRAPcc
TRAPV
TST

Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand

UNLK
UNPK

Unlink
Unpack BCD

COPROCESSOR INSTRUCTIONS

cpGEN

M68000 FAMILY

REFERENCE

cpRESTORE
cpSAVE
cpScc
cpTRAPcc

Restore Internal State of Coprocessor
Save Internal State of Coprocessor
Set Conditionally
Trap Conditionally

MOTOROLA
3-91

MC68020

pending the results of the compare. A varient of this instruction, CAS2, performs similarly comparing dual operand pairs, and updating two operands.
These multi-processing operations are useful when using common memory to share or pass data between multiple processing elements. The read-modify-write cycle
is an indivisible operand that allows reading and updating a "lock" operand used to control access to the common memory elements. The CAS2 instruction is more
powerful since dual operands allow the "lock" to be
checked and two values (i.e., both pointers in a doublylinked list) to be updated according to the lock's status,
all in a single operation.
MODULE SUPPORT
The MC68020 includes support for modules with the
call module (CALLM) and return from module (RTM) instructions. The CALLM instruction· references a module
descriptor. This descriptor contains control information
for entry into the associated module. The CALLM instruction creates a module stack frame and stores the module
state in that frame. The RTMinstruction recovers the
previous module state from the stack frame and returns
to the calling module.
The module interface also provides a mechanism for
finer resolution of access control by external hardware.
Although the MC68020 does not interpret the access control information, it does communicate with external hardware when the access control is to be changed, and relies
on the external hardware to verify that the changes are
legal.
..
.
CALLM and RTM, when used as subroutine calls and
returns with proper descriptor formats, cause the MC68020
to perform the necessary actions to verify legitimate access to modules.

VIRTUAL MEMORY/MACHINE CONCEPTS
The full addressing range ofthe MC68020 is 4 gigabytes
(4,294,967,296). However, most MC68020 systems implement a smaller physical memory. Nonetheless, by using
virtual memory techniques, the system can be made to
appear to have a full 4 gigabytes of physical memory
available to each user program. These techniques have
been used for many years in large mainframe computers
and minicomputers. With the MC68020 (as with the
MC68010 and MC68012). virtual memory can be fully supported in microprocessor-based systems.
In a virtual memory system, a user program can be
written as though it has a large amount of memory available to it when actually only a smaller amount of memory
is physically present in the system. In a similar fashion,
a system provides user programs access to other devices
that are not physically present in the system such as tape
drives, disk drives, printers, or terminals. With proper
software emulation, a physical system can be made to
appear to a user program as any other M68000 computer
system and the program may be given full access to all
of the resources of that emulated system. Such an emulated system is called a virtual machine.

MOTOROLA
3-92

VIRTUAL MEMORY
The basic mechanism for supporting virtual memory
is to provide a limited amount of high-speed physical
memory that can be accessed directly by the processor
while maintaining an image of a much larger "virtual"
memory on secondary storage devices such as large capacity disk drives. When the processor attempts to access
a location in the virtual memory map that is not resident
in physical memory (referred to as a page fault), the access to that location is temporarily suspended while the
necessary data is fetched from secondary storage and
placed in physiCal memory; the suspended access is then
either restarted or continued.
The MC68020 uses instruction continuation to support
virtual memory. In orderfor the MC68020 to use instruction continuation, it stores its internal state on the supervisor stack when a bus cycle is terminated with a bus
error signal. It then loads the program counter with the
address of the virtual memory bus error handler from
the exception vector table (entry number two) and resumes program execution atthat new address. When the
bus error exception handler routine has completed execution, an RTE instruction is executed which reloads the
MC68020 with the internal state stored on the stack, reruns the faulted bus cycle (when required), and continues
the suspended instruction.
Instruction continuation is crucial to the support of virtual I/O devices in memory-mapped input/output systems. Since the registers of a virtual device may. be
simulated in the memory map, an access to such a register will cause a fault and the function of the register can
be emulated by software.
VIRTUAL MACHINE
A typical use for a virtual machine system is the development of software, such as.an operating system, for
a new machine also under development and not yet available for programming use. In such a system, a governing
operating system emulates the hardware ofthe prototype
system and allows the new operating system to be executed and debugged as though it were running on the
new hardware. Since the new operating system is controlled by the governing operating system, it is executed
at a lower privilege level than the. governing operating
system. Thus, any attempts by the new operating system
to use virtual resources that are not physically present
(and should be emulated) are trapped to the governing
operating system and handled by its software .. In the
MC68020, a virtual machine is fully supported by running
the new operating system in the user mode. The governing operating system executes in the supervisor mode
and any attempt by the new operating system to access
supervisor resources or execute privileged instructions
will cause a trap to the governing operating system.

OPERAND TRANSFER MECHANISM

Though the MC68020 has full 32-bit data bus, it offers
the ability to automatically and dynamically downsize its
bus to 8 or 16 bits if peripheral devices are unable to
accommodate the entire 32 bits. This feature allows the

M68000 FAMILY
REFERENCE

MC68020

programmer the ability to write code that is not bus-width
specific. For example, long word (32 bit) accesses to peripherals may be used in the code, yet the MC68020 will
transfer only the amount of data that the peripheral can
manage. This feature allows the peripheral to define its
port size as 8, 16, or 32 bits wide and the MC68020 will
dynamically size the data transfer accordingly, using multiple bus cycles when necessary. Hence, programmers
are not required to program for each device port size or
know the specific port size before coding; hardware designers have flexibility to choose implementations independent of software prejudices.
This is accomplished through the use of the DSACK
pins and occurs on a cycle-by-cycle basis. For example,
if the processor is executing an instruction that requires
the reading of a long word operand, it will attempt to
read 32 bits during the first bus cycle to a long word
address boundary. If the port responds that it is 32 bits
wide, the MC68020 latches all 32 bits of data and continues. If the port responds that it is 16 bits wide, the MC68020
latches the 16 valid bits of data and runs another cycle
to obtain the other 16 bits of data. An 8-bit port is handled
similarly but with four bus read cycles. Each port is fixed
in assignment to particular sections of the data bus.
Justification of data on the bus is handled automati~
cally by dynamic bus sizing~ When reading 16-bit data
from a 32-bit port; the data may appear on the top or
bottom half of the bus, depending on the address of the
data. The MC68020 determines which portion of the bus
is needed to support the transfer and dynamically adjusts
to read or write the data on those data lines.
The MC68020 will always transfer the maximum amount
of data on all bus cycles; i.e., it always assumes the port
is 32 bits wide when beginning the, bus cycle. In addition,
the MC68020 has. no restrictions concerning alignment
of operands in memory; long word operands need not
be aligned on long word address boundaries. When misaligned data requires multiple bus cycles, the MC68020
automatically runs the minimum number of bus cycles.

The M68000 coprocessor interface is designed to extend the programmers model and it provides full support
for the sequential, non-concurrent instruction execution
model. Hence, instruction execution by the coprocessor
is assumed to not overlap with instruction execution with
the main microprocessor. Yet, the M68000 coprocessor
interface does allow concurrent operation when concurrency can be properly accommodated. For example, the
MC68881 floating-point coprocessor will allow the
MC68020 to proceed executing instructions while the
MC68881 continues a floating-point operation, up to the
point that the MC68020 sends another request to the
MC68881. Adhering to the sequential execution model,
the MC68881 completes each MC68881 instruction before
it starts the next, and the MC68020 is allowed to proceed
as it can in a concurrent fashion.
Coprocessors are divided into two types by their bus
utilization characteristics. A coprocessor is a DMA coprocessor if it can control the bus independent of the
main processor. A coprocessor is a non-DMAcoprocessor if it does not have the capability of controlling the
bus. Both coprocessor types utilize the same protocol and
main processor resources., Implementation of a coprocessor as a DMA or non-DMA type is based primarily on
bus bandwidth requirements of the coprocessor, performance, and cost issues.
The communication protocol between the main processor and the coprocessor necessary to execute a coprocessor instruction is based on a group of coprocessor
interface registers (Table 3)' which are defined for the
M68000 Family coprocessor interface. The MC68020
hardware uses standard M68000 asynchronous bus cycles
to access the registers. Thus, the coprocessor doesn't
require a special bus hardware; the bus interface implemented by a coprocessor for its interface register set

Table 3. Coprocessor Interface
Register

THE COPROCESSOR CONCEPT
The coprocessor interface is a mechanism for extending the instruction set ofthe M68000 Family. Examples
of these extensions are the addition' of specialized data
operands' for the existing data types or, for the case of
floating point, the inclusion of new data types and operations for them as implemented by the MC68881 floating-point coprocessor.
The programmer's model for the M68000 Family of
microprocessors is based on sequential, non-concurrent
instruction execution. This means each instruction is
completely executed prior to the beginning of the next
instruction. Hence, instructions do not operate concurrently in the programmer's model. Most microprocessors
implement the sequential model which greatly simplifies
the programmer responsibilities since sequencing control is automatic and discrete.

M68000 FAMILY
REFERENCE

R~gisters

R/Vil

Function

Response

Requests Action from CPU

Control

CPU Directed Control

Save

Initiate Save of Internal State

Restore

Initiate Restore of Internal
State

Operation Word

Current Coprocessor
Instruction

ViI

Command Word

Coprocessor Specific
Command

Condition Word

Condition to be Evaluated,

Operand

32-Bit Operand

Specifies CPU Register or Mask

Instruction Address

Pointer to Coprocessor
Instruction

RfW

Operand Address

Pointer to Coprocessor
Operand

RNV

ViI
RNV
R

MOTOROLA
3-93

MC68020

must only satisfy the MC68020 address, data, and control
signal timing to guarantee proper communication with
the main processor. The MC68020 implements the communication protocol with all coprocessors in hardware
(and microcode) and handles all operations automatically
so the programmer is only concerned with the instructions and data types provided by the coprocessor as extensions to the MC68020 instruction set and data types.
Other microprocessors in the M68000 Family can operate any M68000 coprocessor even though they may not
have the hardware implementation of the coprocessor
interface as does the MC68020. Since the coprocessor is
operated through the coproce!isor interface registers
which are accessed via normal asynchronous bus cycles,
the coprocessor may be used as a peripheral device. Software easily emulates the communication protocol by addressing the coprocessor interface registers appropriately
and passing the necessary commands and operands required by the coprocessor.
The coprocessor interface registers are implemented
by the coprocessor in addition to those registers implemented as extensions· to the MC68020 programmer's
model. For example, the. MC68881 implements the coprocessor· interface registers shown in Table 3 and the
registers in the programming model, including eight 80bit floating-point data registers and three 32-bit controll
status registers used by the MC68881 programmer.
Up to eight coprocessors are supported in a single system with a system-unique coprocessor identifier encoded
in the coprocessor instruction. When accessing a coprocessor, the MC68020 executes standard read and write
bus cycles in CPU address space, as encoded by the function codes, and places the coprocessor identifier on the
address bus to be used by chip-select logic to select the
particular coprocessor. Since standard bus cycles are used
to access the coprocessor, the coprocessor may be located according to system design requirements, whether
it be located on the microprocessor local bus, on another
board on the system bus, or any other place where the
chip-select and coprocessor protocol using standard
M68000 bus cycles can be supported.

The response may indicate some exception
condition; the main processor acknowledges the exception and begins exception
processing.
3) The response may indicate that the coprocessor needs the main processor to perform
some service such as transferring data to or
from the coprocessor. The coprocessor may
also request that the main processor query
the coprocessor again after the service is
complete.
4) The response may indicate that the main
processor is not needed for further processing of the instruction. The communication is
terminated, and the main processor is free
to begin execution of the next instruction. At
this point in the coprocessor protocol, as the
main processor continues to execute the instruction stream, the main processor may
operate concurrently with the coprocessor.
When the main processor encounters the next coprocessor instruction, the main processor queries the coprocessor until the coprocessor is ready; meanwhile, the
main processor can go on to service interrupts and do a
context switch to execute other tasks, for example.
Each coprocessor instruction type has specific requirements based on this simplified protocol. The coprocessor
interface may use as many extension words as required
to implement a coprocessor instruction.
PRIMITIVES/RESPONSE

The response register is the means by which the coprocessor communicates service requests to the main
processor. The content of the coprocessor response register is a primitive instruction to the main processor which
is read during coprocessor communication by the main
processor. The main processor "executes" this primitive,
thereby providing the services required by the coprocessor. Table 4 summarizes the coprocessor primitives that
the MC68020 accepts.

COPROCESSOR PROTOCOL

Interprocessor transfers are all initiated by the main
processor during coprocessor instruction execution. During the processing of a coprocessor instruction, the main
processor transfers instruction information and data to
the associated coprocessor, and receives data, requests,
and status information from the coprocessor. These
transfers are all based on the M68000 bus cycles.
The typical coprocessor protocol which the main processor follows is:
a) The main processor initiates the communication
by writing command information to a location in
the coprocessor interface.
b) The main processor reads the coprocessor response to that information.
1) The response may indicate that the coprocessor is busy, and the main processor should
again query the coprocessor. This allows the
main processor and coprocessor to synchronize their concurrent operations.

MOTOROLA
3-94

EXCEPTIONS
KINDS OF EXCEPTIONS

Exceptions can be generated by either internal or external causes. The externally generated exceptions are
the interrupts, the bus error, and reset requests. The interrupts are requests from peripheral devices for processor action while the bus error and reset pins are used for
access control and processor restart. The internally generated exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc, TRAPV,
cpTRAPcc, CHK, CHK2, and DIV instructions can all generate exceptions as part of their instruction executipn.
Tracing behaves like a very high priority, internally generated interrupt whenever it is processed. The other internally generated exceptions are caused by illegal
instructions, instruction fetches from odd addresses, and
privilege violations.

M68000 FAMILY

REFERENCE

MC68020

Table 4. Coprocessor Primitives
Processor Synchronization
Busy with Current Instruction
Proceed with Next Instruction, If No Trace
Service Interrupts and Re-query, If Trace Enabled
Proceed with Execution, Condition True/False
Instruction Manipulation
rransfer Operation Word
Transfer Words from Instruction Stream
Exception Handling
Take Privilege Violation if S Bit Not Set
Take Pre-Instruction Exception
Take Mid-Instruction Exception
Take Post-Instruction Exception
General Operand Transfer
Evaluate and Pass (ea)
Evaluate (ea) and Transfer Data
Write to Previously Evaluated (ea)
Take Address and Transfer Data
Transfer to/from Top of Stack
Register Transfer
Transfer CPU Register
Transfer CPU Control Register
Transfer Multiple CPU Registers
Transfer Multiple Coprocessor Registers
Transfer CPU SR and/or ScanPC

EXCEPTION PROCESSING SEQUENCE
Exception processing occurs in four steps. During the
first step, an internal copy is made of the status register.
After the copy is made, the special processor state bits
in the status register are changed. The S bit is set, putting
the processor into supervisor privilege state. Also, the T1
and TO bits are negated, allowing the exception handler
to execute unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is also updated.
In the second step, the vector number of the exception
is determined. For interrupts, the vector number is obtained by a processor read that is classified as an interrupt
acknowledge cycle. For coprocessor detected exceptions,
the vector number is included in the coprocessor exception primitive response. For all other exceptions, internal
logic provides the vector number. This vector number is
then used to generate the address ofthe exception vector.
The third step is to save the current processor status.
The exception stack frame is created and filled on the
supervisor stack. In order to minimize the amount of machine state that is saved, various stack frame sizes are
used to contain the processor state depending on the
type of exception and where it occurred during inst"ruction execution. If the exception is an interrupt and the M
bit is on, the M bit is forced off, and a short four word
exception stack frame is saved on the master stack which
indicates that the exception is saved on the interrupt stack.
If the exception is a reset, the M bit is simply forced off,
and the reset vector is accessed.
The MC68020 provides an extension to the exception
stacking process. If the M bit in the status register is set,

M68000 FAMILY
REFERENCE

the master stack pointer (MSP) is used for all task related
exceptions. When a non·task related exception occurs
(i.e., an interrupt), the M bit is cleared and the interrupt
stack pointer (lSP) is used. This feature allows all the
task's stack area to be carried within a single processor
control block and new tasks may be initiated by simply
reloading the master stack pointer and setting the M bit.
The fourt~ and last step of exception processing is the
same for all exceptions. The exception vector offset is
determined by multiplying the vector number by four.
This offset is then added to the contents of the vector
base register (VBR) to determine the memory address of
the exception vector. The new program counter value is
fetched from the exception vector. The instruction at the
address given in the exception vector is fetched, and normal instruction decoding and execution is started.

ON·CHIP INSTRUCTION CACHE
Studies have shown that typical programs spend most
of their execution time in a few main routines or. tight
loops. This phenomenon is known as locality of reference, and has an impact on performance of the program.
The MC68010 takes limited advantage of this phenomenon in the form of its loop mode operation which allows
certain instructions, when coupled with the DBcc instruction, to execute without the overhead of instruction
fetches. In effect this is a three word cache. Although the
cache hardware has been supplied in a full range of computer systems for many years, technology now alloyvs
this feature to be integrated into the microprocessor.

MC68020 CACHE GOALS
There were two primary goals for the MC68020 microprocessor cache. The first design goal was to reduce the
processor external bus activity. In a given M68000 system, the MC68000 processor will use approximately 80
to 90 percent (or greater) of the available bus bandwidth.
This is due to its extremely efficient prefetching algorithm
and the overall speed of its internal architecture design.
Thus, in an M68000 system with more than one bus master (such as a processor and DMA device) or in a multiprocessor system, performance degradation can occur
due to lack of available bus bandwidth. Therefore, an
important goal for an MC68020 on-chip cache was to
provide a substantial increase in the total available bus
bandwidth.
The second primary design goal was to increase effective CPU throughput as larger memory sizes or slower
memories increased average access time. By placing a
high speed cache between the processor and the rest of
the memory system, the effective access time now becomes:
tacc = h*tcache + (1 - h)*t ext
where tacc is the effective system access time, tcache is
the cache access time, text is the access time of the rest
of the system, and h is the hit ratio or the percentage of
time that the data is found in the cache. Thus, for a given
system design, an MC68020 on-chip cache provides a
substantial CPU performance increase, or allows much
slower and less expensive memories to be used for the
same processor performance.

MOTOROLA
3-95

MC68020

The throughput increase in the MC68020 is gained in
two ways. First, the MC68020 cache is accessed in two
clock cycles versus the three cycles (minimum) required
for an external access. Any instruction fetch that is currently resident in the cache will provide a 33% improvement over the corresponding external access.
Second, and probably the most important benefit of
the cache, is that it allows instruction stream fetches and
operand accesses to proceed in parallel. For example, if
the MC68020 requires both an instruction stream access
and an operand access, and the instruction is resident in
the cache, the operand access will proceed unimpeded
rather than being queued behind the instruction fetch.
Similarly, the MC68020 is fully capable of executing several internal instructions (instructions that do not require
the bus) while completing an operand access for another
instruction.
The MC68020 instruction cache is a 256-byte direct
mapped cache organized as 64 long word entries. Each
cache entry consists of a tag field made up of the upper
24 address bits, the FC2 (user/supervisor) value, one valid
bit, and 32 bits of instruction data (Figure 5).
The MC68020 employs a 32-bit data bus and fetches
instructions on long word address boundaries. Hence,
each 32-bit instruction fetch brings in two 16-bit instruction words which are then written into the on-Chip cache.
When the cache is enabled, the subsequent prefetch will

find the next 16-bit instruction word is already present in
the cache and the related bus cycle is saved. If the cache
were not enabled, the subsequent prefetch will find the
bus controller still holds the full 32 bits and can satisfy
the prefetch and again save the related bus cycle. So,
even when the on-chip instruction cache is not enabled,
the bus controller provides an instruction "cache hit" rate
up to 50%.

SIGNAL DESCRIPTION
The MC68020 is offered in a 114 lead pin-grid array
package (PGA). Figure 6 illustrates the functional signal
groups and Table 5 lists the signals and their function.
The VCC and GND pins are separated into four groups
to provide individual power supply connections for the
address bus buffers, data bus buffers, and all other output
buffers and internal logic.
Group
Address Bus

Vee

GND

A9,03

A10, B9, C3, F12

M8, N8, N13

L7, L11, N7, K3

Logic

01.02, E3, G11, G13

G12. H13, J3, K1

Clock

Data Bus

MC68020 PRETCH ADDRESS
A
A A.A A A A A A A A A A A
3--2
1

A A A A A A A A A A A
0000000000
98
65
0

~ f.- ~I·-2-4- - - T A G -'-------..I·~,NDEX~ I~

DF~

SELECT.

WORD
25

TAG

SELECT

WORD

'---t-.&...-+-- REPLACEMENT DATA

TAG REPLACE
25

TO INSTRUCTION PATH

--""-----;~

CACHE CONTROL

Figure 5. MC68020 On-Chip Cache Organization

MOTOROLA
3-96

M68000 FAMILY
REFERENCE

MC68020

FCO-FC2

FUNCTION CODES

AO-A3 I

ADDRESS BUS

00-03 1

TRANSFER SIZE

<: :>

{

DATA BUS

SIZO
SIZI

CDiS

CACHE CONTROL

~RRUPT PRIORI TV IPlO_IP12)
INTERRUPT CONTROL
IPEND
MC68020
MICROPROCESSOR

AVEC

BR
BG

} BUS ARBITRATION CONTROL

BGACK
ECS
OCS

ASYNCHRONOUS BUS CONTROL

RESET

RMC

HALT

AS
OS

BERR

ClK

} BUS EXCEPTION CONTROL

DBEN
DSACKO

VCC (101

OSACKI

GND (131

Figure 6. Functional Signal Groups

M68000 FAMILY

REFERENCE

MOTOROLA
3-97

MC68020

Table 5. Signal Index
Signal Name
Address Bus

Mnemonic

Function

AO-A32

32-bit address bus used to address any of 4,294,967,296 bytes.

Data Bus

DO-D31

32-bit data bus used to transfer 8, 16,24, or 32 bits of data per bus cycle.

Function Codes

FCO-FC2

3-bit function code used to identify the address space of each bus cycle.

SIZO/SIZl

Indicates the number of bytes remaining to be transferred for this cycle.
These signals, together with AO and A 1, define the active sections of the
data bus.

Size

Read-Modify-Write Cycle

-RMC

Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.

External Cycle Start

ECS

Provides an indication that a bus cycle is beginning.

Operand Cycle Start

OCS

Identical operation to that of ECS except that OCS is asserted only during
the first bus cycle of an operand transfer.

Address Strobe

Indicates that a valid address is on the bus.

Data Strobe

Indicates that valid data is to be placed on the data bus by an external
device or has been placed on the data bus by the MC68020.

ReadlWrite
Data Buffer Enable
Data Transfer and Size Acknowledge

Cache Disable
Interrupt Priority level

RiW
DBEN

Defines the bus transfer as an MPU read or write.
Provides an enable signal for external data buffers.

DSACKO/DSACK 1 Bus response signals that indicate the requested data transfer operation
is completed. In addition, these two lines indicate the size of the external
bus port on a cycle-by-cycle basis.

-CDIS

---IPlO-IPl2

Dynamically disables the on-chip cache to assist emulator support.
Provides an encoded interrupt level to the processor.

Autovector

AVEC

Requests an autovector during an interrupt acknowledge cycle.

Interrupt Pending

IPEND

Indicates that an interrupt is pending.

Bus Request
Bus Grant

Indicates that an external device requires bus mastership.

Indicates that an external device may assume bus mastership.

Bus Grant Acknowledge

BGACK

Indicates that an external device has assumed bus mastership.

Reset

RESET

System reset.

Halt

HALT

Indicates that the processor should suspend bus activity.

Bus Error

BERR

Clock

ClK

Indicates an invalid or illegal bus operation is being attempted.
Clock input to the processor.

Power Supply

VCC

+ 5 volt

Ground

GND

Ground connection.

MOTOROLA
3-98

± 5% power supply.

M68000 FAMILY
REFERENCE

MC68020

ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Rating

Symbol

Value

Unit
V

Supply Voltage

VCC

-0.3 to +7.0

Input Voltage

Vin

,- 0.3 to + 7.0

Operatinf-) Temperature Range

o to 70

°c

Tstg

-55 to 150

°c

Symbol

Value

Rating

°JA

30
11

f-.

Storage Temperature Range

THERMAL CHARACTERISTICS Characteristic
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case

This device contains protective circuitry against
damage due to high static voltages or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any
voltages higher than maximum-rated voltages
to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g., either
GNO or VCC!.

PGA PACKAGE

°CIW

OJC

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in DC can be
obtained from:
(1)

where:
TA = Ambient Temperature, DC
()JA = Package Thermal Resistance, Junction-toAmbient, DC/W
PD = PINT+ PliO
PINT= ICC x VCC, Watts - Chip Internal Power
PliO = Power Dissipation on Input and Output
Pins - User Determined
For most applications PI/O < PINT and can be neglected.
An approximate relationship between PD and TJ (if PI/O is
neglected) is:
PD = K -+- (TJ +273 DC)
(2)
Solving equations (1) and (2) for K gives:
K= PDo(TA + 273 DC) + ()JAoPD 2
(3)
where K is a constant pertaining to the particular part. K can
be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of
PD and TJ can be obtained by solving equations (1) and (2)
iteratively for any value of T A.

The total thermal resistance' of a package (()JA) can be
separated into two components, ()JC and 0CA, representing
the barrier' to heat flow from the semiconductor junction to
the package (case) surface (()JC) and from the case to the
outside ambient WCA). These terms are, related by the
equation:
()JA = ()JC + ()CA
(4)
()JC is device related and cannot be influenced by the user.
However, ()CA is user dependent and can be minimized by
such thermal management techniques as heat sinks, ambient
air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce ()CA
so that ()JA approximately equals ()JC. Substitution of ()JC for
()JA in equation (1) will result in a lower semiconductor junction
temperature.
Values for thermal resistance presented in this document,
unless estimated, were derived using the procedure described
in Motorola Reliability Report 7843, "Thermal Resistance Measurement Method for MC68XX Microcomponent Devices,"
and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup.
User derived values for thermal resistance may differ.
+

+5 V

1420

130 pF

Figure 7. RESET Test Load

M68000 FAMILY
REFERENCE

TEST

MM06150

POINT

OR EQUIVALENT

+5 V

1420

I130 pF

Figure 8. HALT Test Load

MM07000
OR EQUIVALENT

CL = 50 pF for ECS and OCS
CL = 130 pF for all other !includes all parasitics)
RL=6.0 k!1
R *= 1.22 k!l for AO-A31. 00-031. BG. FCO-FC2. SIZO-SIZl
R = 2 k!l for ECS, OCS
R = 740 !l for AS, OS. R/W. RMC, DBEN. IPEND

Figure 9. Test Load

MOTOROLA
3-99

MC68020

DC ELECTRICAL CHARACTERISTICS (VCC=5.0 Vdc::!::5%;GNO=0 Vdc; TA=O to 70°C; see Figures 7, 8, and 9)
Symbol

Min

Max

Unit

Input High Voltage

VIH

2.0

VCC

Input Low Voltage

VIL

GNO
-0.5

0.8

lin

-1.0
-20

1.0
20

!LA

AO-A31, AS, OBEN, OS, 00-031, FCO-FC2,
RNV, RMC, SIZO-SIZl

ITSI

-20

!LA

Output High Voltage
IOH=400 !LA

AO-A31, AS, BG, 00-031, OBEN, OS, ECS, RIW, IPENO,
OCS, RMC, SIZO-SIZ1, FCO-FC2

VOH

2.4

Output Low Voltage
IOL =3.2 rnA
IOL =5.3 rnA
IOL =2.0 rnA
IOL = 10.7 rnA

AO-A31, FCO-FC2, SIZO-SIZ1, BG, 00-031
AS, OS, RNV, RMC, OBEN, IPENO
ECS,OCS
HALT,RESET

0.5
0.5
0.5
0.5

2.0

Cin

Characteristic

·Input Leakage Current
GNO ~ V in ~ VCC

BERR, BR, BGACK, CLK,IPLO-IPL2, AVEC, COIS, OSACKO, OSACKl
HALT,RESET

Hi-Z (Off-State) Leakage Current
(0 2.4 VIO.5 V

Power Oissipation (TA = O°C)

f=25 MHz
f=33.33 MHz

Capacitance (see Note 1)
Vin=OV, TA=25°C,f=1 MHz
NOTE 1.

VOL

CapaCitance is periodically sampled rather than 100% tested.

AC ELECTRICAL SPECIFICATIONS - CLOCK INPUT (see Figure 10)
Num.

12.5 MHz

Characteristic

Min

Max

16.67 MHz

20 MHz

Min

Max

Min

25 MHz*

Max

Min

Max

33.33 MHz
Min

Max

Unit

Frequency of Operation

12.5

16.67

12.5

33.33

MHz

Cycle Time

125

.30

2,3

Clock Pulse Width (Measured from 1.5 V
to 1.5 V for 25 and 33.33 MHz)

4,5

Rise and Fall Times

*These specifications represent an improvement over previously published specifications for the 25 MHz MC68020 and are valid
only for product bearing date codes of 8827 and later.

NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
The voltage swing through this range should start outside, and pass through, the range suchthat the rise or fall will be linear between
0.8 volts and 2.0 volts.
Figure 10. Clock Input Timing Diagram

MOTOROLA
3-100

M68000.FAMILY

REFERENCE

MC68020

AC ELECTRICAL SPECIFICATIONS - READ AND WRITE CYCLES (VCC=5.0 Vdc :t5%; GND=O Vdc; TA=O to 70°C;
see Figures 12, 13, and 14)
Num.

. Characteristic

12.5 MHz

16.67 MHz

20 MHz

25 MHz*

33.33 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock High to Address, FC, Size, RMC Valid

Clock High to ECS, OCS Asserted

Clock High to Address, Data, FC, Size, RMC,
High Impedance

Clock High to Address, FC, Size, RMC Invalid

Clock Low to AS, DS Asserted

-20

-15

-10

.10

6
6A

9A'

AS to DS Assertion (Read) (Skew)

9B"

AS Asserted to DS Asserted (Write)

ECS Width Asserted

lOA OCS Width Asserted

Address, FC, Size, RMC Valid to AS
(and DS Asserted Read)

Clock Low to AS, DS Negated

10B7 ECS, OCS Width Negated

12A Clock Low to ECS, OCS Negated

15
15

AS, OS Negated to Address, FC, Size,
RMC Invalid

AS (and DS Read) Width Asserted

120

100

14A DS Width Asserted Write
15

AS, DS Width Negated

15A8 DS Negated to AS Asserted

50
50

Clock High to AS, DS, RIW, DBEN
High Impedance

AS, DS Negated to RIW Invalid

Clock High to RIW High

Clock High to RIW Low

RIW High to AS Asserted

RIW Low to DS Asserted (Write)

Clock High to Data Out Valid

DS Negated to Data Out Invalid

25A9 DS Negated to DBEN Negated (Write)

Data Out Valid to DS Asserted (Write)

Data-In Valid to Clock Low (Data Setup)

27A

Late BERR/HAL T Asserted to Clock Low
Setup Time

AS, DS Negated to DSACKx, BERR, HALT,
AVEC Negated

110

DS Negated to Data-In Invalid
(Data-In Hold Time)

29A

DS Negated to Data-In (High Impedance)

DSACKx Asserted to Data-In Valid

31 2

31A3 DSACKx Asserted to DSACKx Valid
(DSACK Asserted Skew)

M68000 FAMILY
REFERENCE

MOTOROLA
3-101

MC68020

AC ELECTRICAL SPECIFICATIONS DEFINITIONS
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times.
All signals are specified relative to an appropriate edge
of the MC68020 clock input and, possibly, relative to one
or more other signals.
The measurement of the AC specifications is defined
by the waveforms in Figure 11. In order to test the parameters guaranteed by Motorola, inputs must be driven
to the voltage levels specified in Figure 11. Outputs of

the MC68020 are specified with minimum and/or maximum limits, as appropriate, and are measured as shown.
Inputs to the MC68020 are specified with minimum and,
as appropriate, maximum setup and hold times, and are
measured as shown. Finally, the measurements for signal-to-signal specifications are also shown.
Note that the testing levels used to verify conformance
of the MC68020 to the AC specifications does not affect
the guaranteed DC operation of the device as specified
in the DC electrical characteristics.

DRIVE

TO 2.4 V ~
elK

OUTPUTSlll elK

2.0 V

VALID

OUTPUT n

VALID

OUTPUT n t I

2.0 V
VALID
0.8 V OUTPUT n • 1

OUTPUTSI21 elK

DRIVE - - - . .

INPUTSI31 elK

TO 2.4 V
ORIVE - - - - .

TO 0.5 V

+--- DRIVE
TO 2.4 V

INPUTI41 elK

~DRIVE

TO 0.5 V

All SIGNAlSI51

2.0 V
0.8 V

NOTES:
1. This
2. This
3. This
4. This
5. This

LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimuml.

Figure 11. Drive Levels and Test Points for AC Specifications

M68000. FAMILY

REFERENCE

MOTOROLA
3·103

MC68020

These waveforms should only be, referenced in regard to the edge-to-edge measurement of the timing specifications.
Theyare not intended as a functional description, of the input and output signals. Refer to other functional descriptions
and their related diagrams for device operation.
SO

CLK

---i~~~~~~'

"10~

.'.

.'~

'KV'

-"1('--_ _ __

AO·A31

FCO·FC2

(
(

SIZE

Car

... ~
14

13
~

@-+

R/W

--------------~~--~,
ALL _ _ _ _ _ _ _ _""

~~~--------------------I~

ASYNCHRONOUS
\.
INPUTS ---------.,....--1~-.-,;..,...~-----------....;,.

--l e

~ ~@

NOTE:

Timing measurements are referenced to and from a low voltage of 0.8 volts and ahigh 'voltage of 2.0 volts, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between
0.8 volts and 2.0 volts.

" Figure 12. Read-Cycle Timing Diagram

MOTOROLA
3-104

M68000 FAMILY

REFERENCE

MC68020

.rd.~r--..J~~r-J
6
.......
-.
AD·A31 )
ClK

- -

~
(

FCD·FC2

SIZ E

~
- -r-Jr-.
~

(
~(

®
'1

--. l0 ..-

~ ~ B-+,
.,
~

.... 1~

-. {9_ "'r
~®

~21

I ...

00·03 1

)

....

.... ~

....

Is'

~ :.;/

¥
J
-I

'46'

'C,I

~ r-

'i
K§'

I~D
~

~'f-J~ SEE
. NOTE 5 .

--.-@
HALT

§ I'

R/W

~ r--

'r
@--..

--.@~

-... ~
NOTE:

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between
0.8 volts and 2.0 volts.

Figure 13. Write-Cycle Timing Diagram

M68000 FAMILY

REFERENCE

MOTOROLA
3-105

MC68020

. S2

CLK

AO·A31

00·031

FCO·FC2

SIZO·SIZI

ECS

OCS

AS
OS
A/Vi

OBEN

iiSAcKo
OSACKI

Bii
iiG
BGACK

NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.
The voltage swing through this range should star! outside and pass through the range such that the rise or fall will be linear between
0.8 volts and 2:0 volts.

Figure 14. Bus Arbitration Timing Diagram

MOTOROLA
3-106

M68000 FAMILY

REFERENCE

MC68020

PIN ASSIGNMENT

a a a a a a a a
GNO VCC 014 012 09 08 VCC
M
0
a 0 a 0 a a a a a a a a
os 029 026 024 021 018 016 VCC 013 010 06 05 04
a a a a a a a a a a a a a
AS RlW 030 027 023 019 GNO 015 011 07 GNO 03 02
a a a
a a
K
GNO HALT GNO
01
DO
o a a
a a
OSACKI BERR GNO
IPLO IPLI
H
000
a a
IPL2 GNO
CDiS AVEC OSACKO
G
a 0
a a a
0
ECS SIZI OBEN
VCC GNO VCC
a 0
a 0
0
GNO IPENO
SIZO FC2 FCI
0
a 0
a 0
FCO RMC VCC
A2 DCS
0
0
a 0
0
0
A4
A3
VCC VCC VCC
000 a a a a a a a a a a
RESET CLOCK GND AO A29 A25 A21 A17 A16 A12 A9
A7
A5
B
0
a a a 0 a a a a a a a a
GND BG BR A30 A27 A24 A20 A18 GNO A15 A13 Al0 A6
A
a a 0 a a a a a a a a a a
N

031

028

025

022

020

017

GACK Al

A31

A2B

A26

A23

A22

A19
B

M68000 FAMILY
REFERENCE

VCC GND
10

A14

All

MOTOROLA
3-107

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68030

Technical Summary

Second Generation
32-Bit Enhanced Microprocessor
The MC68030 is the industry's second generation 32-bit enhanced microprocessor. The MC68030 is
a virtual memory microprocessor based on an MC68020 core with additional enhanced performance
features. Increased internal parallelism is provided by multiple internal data buses and address buses
and a versatile bus controller that supports two-clock cycle bus accesses and one-clock cycle burst
accesses in order to maximize performance with paged mode, nibble mode, and static column DRAM
technology. A 256-byte on-chip instruction cache in addition to a 256-byte data cache improves data
flow to the execution unit and further boosts performance. On-chip paged memory management reduces the minimum physical QUs cycle time to two clocks, and provides zero translation time to any
bus cycle. The page~ memory management structure can be enabled/disabled by software for applications not requiring the memory management feature. The rich instruction set and addressing modes
of the MC68020 have been maintained allowing a clear migration path for M68000 systems.
The main features of the MC68030 are:
•
•
•
•
•
•
•

Object Code Compatible with the MC68020 and Earl.ier M68000 Microprocessors
Complete 32-Bit Non-Multiplexed Address and Data Buses
Sixteen 32-Bit Generfil Purp!Jse Data and Address Registers
Two 32-Bit Supervisor ?t(lck Pointers and 10 Special Purpose Control Registers
256-Byte Instructi,on C:,ache a,nd 2~6-l;lyte Data Cache that can be Accessed Simultaneously
Paged Memory Management Unit that Translates Addresses in Parallel with Instruction Execution
Two Transparent 'Segrn.ents Allow Untranslated Blocks to be Defined for Systems that Transfer
Large Blocks of Data ~o' Predefi l1 ed Addresses, e.g., Graphics Applications
• Pipelined Architectt,Jre with Increased Parallelism Allows Accesses from Internal Caches to Occur in
Parallel with Bus T~a~sfers and Multiple Instructions to be Executing Concurrently
• Enhanced Bus ControUer Supports Asynchronous Bus Cycles, Synchronous Bus Cycles that can Operate in Two Clocks, and Bl!rst'Data Transfers that can Operate in One Clock, all with Physical Addresses
• Dynamic Bus Sizing ~,upports 8-/16-/~2-Bit Memories and Peripherals
• Complete Support for Coprocessors with the M68000 Coprocessor Interface
• 4-Gigabyte Direct Addr~ssing Range
• Implemented in Motorola's HCMPS Technology that Allows CMOS and HMOS (High Density NMOS)
Gates to be Combined for MaxImum Speed, Low Power, and Small Die Size
• Selection of Processors Speeds: 16.67 and 20 MHz

This document contains information ,on a new p.roduct. Specifications and information herein are subject to change without notice .

·'~

. . . .·M·O·TO·R·O·LA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-108

MOTOROLA . .
M68000 FAMILY

REFERENCE

::Jl~

men
'T100
me
::Jle
me

MICROSEQUENCER AND CONTROL
CONTROL
STORE

2'T1
0»

INTERNAL
DATA
BUS

INSTRUCTION
CACHE

V'---------'

INSTRUCTION
ADDRESS
BUS

ADDRESS
BUS

SIZE

DATA
BUS

DATA
ADDRESS
BUS
DATA
CACHE

b
w:JJ

S
n
0)

BUS CONTROL
SIGNALS

..:...0

or-

(0»

Figure 1. MC68030 Block Diagram

MC68030

INTRODUCTION
The MC68030 is an enhanced 32-bit HCMOS microprocessor that incorporates the capabilities of the MC68020
MPU, an on-chip data cache, an on-chip instruction cache,
an improved bus controller, multiple internal data buses,
multiple internal instruction buses, and an on-chip paged
memory management structure defined by the MC68851'
Paged Memory Management Unit. The MC68030 main:
tains the 32-bit registers available with the entire M68000
Family as well as the 32-bit address and data paths, rich
instruction set, versatile addressing modes, and flexible
coprocessor interface provided with the MC68020. In addition, the internal operations of this integrated processor
are designed to operate in parallel, allowing mUltiple instructions to be executed concurrently. It allows. allows
instruction execution to proceed in parallel with accesses
to the internal caches, the on-chip memory management
unit, and the bus controller.
The MC68030 fully supports the non-multiplexed asynchronous bus of the MC68020 as well as a dynamic bus
sizing mechanism that allows the processor to transfer
operandsto or from external devices while automatically
determining device port size on a cycle-by-cycle basis. In
addition to the asynchronous bus, the MC68030 also supports a fast synchronous bus for off-chip caches and fast
memories. Further, the MC68030 bus is capable of fetching up to four long words of data in a burst mode compatible with DRAM chips that have burst capability. Burst
mode can reduce by up to 50% the time necessary to
fetch the four long words. The four long words are used
to prefill the on-chip instruction and data caches so that
the hit ratio of the caches improves and the average access time for operand fetches is minimized.
The block diagram shown in Figure 1 depicts the major
sections of the MC68030 and illustrates the autonomous
nature of these blocks. The bus controller consists of the
address and data pads, the multiplexors required to support dynamic bus sizing, and a macro bus controller which
schedules the bus cycles on the basis of priority. The
micromachine contains the execution unit and all related
control logic. Microcode control is provided by a modified
two-level store of micro rom and nanorom contained in
the micromachine. Programmed logic arrays (PLAs) are
used to provide instruction decode and sequencing information. The instruction pipe and other individual control sections provide the secondary decode of instructions
and generate the actual control signals that result in the
decoding and interpretation of nanorom and microrom
information.
The instruction and data cache blocks operate independently from the rest of the machine, storing· information read by the bus controller for future use with very
fast access time. Each cache resides on its own address
and data buses, allowing simultaneous access to both.
Both the caches are organized as 64 long word entries
(256 bytes) with a block size of four long words. The data
cache uses a write-through policy with no write allocation
on cache misses.
Finally, the memory management unit controls the
mapping of addresses for page sizes ranging from 256
bytes to 32K bytes. Mapping information stored in descriptors resides in translation tables in memory that are

MOTOROLA
3-110

automatically searched by the MC68030 on demand. Recently-used descriptors are maintained in a 22-entry fully
associative cache called the Address Translation Cache
(ATC) allowing address translation and other MC68030
functions to occur simultaneously. Additionally, the
MC68030 contains two transparent translation registers
that can be used to define a one-to-one mapping for two
segments ranging in size from 16M bytes to 4G bytes
each.

PROGRAMMING MODEL
As shown in the programming models (Figures 2 and
3), the MC68030 has sixteen 32-bit general purpose registers, a 32-bit program counter, two 32-bit supervisor
stack pointers, a 16-bit status register, a 32-bit vector base
register, two 3-bit alternate function code registers, two
32-bit cache handling (address and control) registers, two
64-bit root pointer registers used by the MMU, a 32-bit
translation control register, two 32-bit transparent translation registers, and a 16-bit MMU status register .. Registers 00-07 are used as data registers for bit and bit field
(1 to 32 bit), byte (8 bit). word (16 bit), long word (32 bit).
and quad word (64 bit) operations. Registers AO-A6 and
the user, interrupt, and master stack pointers are address
registers that may be used as software stack pointers or
base address registers. In addition, the address registers
may be used for word and long word operations. All of
the 16 (00-07, AO-A7) registers may be used as index
registers.
The status register (Figure 4) contains the interrupt
priority mask (three bits) as well as the condition codes:
extend (X), negate (N), zero (Z), overflow (V). and carry
(C). Additional control bits indicate that the processor is
in the trace mode (T1 or TO), supervisor/user state (5),
and master/interrupt state (M).
All microprocessors of the M68000 Family support instruction tracing (via the TO status bit in the MC68030)
where each instruction executed is followed by a trap to
a user-defined trace routine. The MC68030 also has the
capability to trace only on the change of flow instructions
(branch, jump, subroutine call and return, etc.) using the
T1 status bit. These features are important for software
program development and debug.
The vector base register is used to determine the runtime location of the exception vector table in memory,
hence it supports multiple vector tables so each process
or task can properly manage exceptions independent of
each other.
The M68000 Family processors distinguish address
spaces as supervisor/user, program/data, and CPU space.
These five combinations are specified by the function
code pins, FCO-FC2, during bus cycles, indicating the particular address space. Using the function codes, the memory subsystem (hardware) can distinguish between
supervisor mode accesses and user accesses as well as
program accesses, data accesses, and CPU space accesses. Additionally, the system software can configure
the on-chip MMU so that supervisor/user privilege checking is performed by the address translation mechanism
and the look-up of translation descriptors can be differentiated on the basis of function code. To support the full

M68000 FAMILY
REFERENCE

MC68030

16 15

8 7
DO
01

03
DATA REGISTERS
04

05
06

16 15
AO

Al
A2

ADDRESS REGISTERS

A3
A4

A5
A6

16 15
A7 (USP)} USER STACK POINTER

____________________________________________
15

~I PC

}

PROGRAM COUNTER

}

CONDITION CODE REGISTER

C===o===-L...I____----'

CCR

Figure 2. User Programming Model

privileges of the supervisor, the alternate function code
registers allow the supervisor to specify the function code
for an access by preloading the SFC/DFC registers appropriately.
The cache registers (control - CACR, address - CAAR)
allow supervisor software manipulation of the on-chip
instruction and data caches. Control and status accesses
to the caches are provided by the cache control register
(CACR), while the cache address register (CAAR) specifies
the address for those cache control functions that requfre
an address.
All of the MMU registers (CRP, SRP, TC, TIO, TI1, and
PSR) are accessible by the supervisor only. The CPU root
pointer contains a descriptor for the first pointer to be
used in the translation table search for page descriptors
pertaining to the current task. If the SRE (Supervisor Root

M68000 FAMILY

REFERENCE

pointer Enable) bit of the translation control register is
set, the supervisor root pointer is used as a pointer to
the translation tables for all supervisor accesses. If the
SRE bit is clear, this register is unused and the CPU root
pointer is used for both supervisor and user translations.
The translation control register configures the table lookup mechanism to be used for all table searches as well
as the page size and any initial shift of logical address
required by the operating system. In addition, this register has an enable bit that enables the MMU. The transparent translation registers can be used to define two
transparent windows for transferring large blocks of data
with untranslated addresses. Finally, the MMU status register (PSR) contains status information related to a specific address translation and the results generated by the
PTEST instruction. This information can be useful in locating the cause of an MMU fault.

MOTOROLA
3-111

MC68030

16 15

~_____~_______~_____________~IA7"~~~rum~~~
15

'--_ _ _ _ _ _........._ _ _(_CC_R_1_ _
31

---a

______________________________________________

r
- - -------------- ------ - --L ____________________________
_

~I VBR

IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

SFC
DFC

}

STATUS REGISTER

}

VECTOR BASE REGISTER

J-. .
J-

ALTERNATE FUNCTION

CODE REGISTERS

I CACR

}

CACHE CONTROL REGISTER

I CAAR

}

CACHE ADDRESS REGISTER .

}

CPU ROOT POIN'" REGISTER

CRP

SUPERVISOR ROOT POINTER
REGISTER

SRP
}.

I TC

}

I no

}

TIl

}

. TRANSLATION CONTROL
REGISTER

TRANSPARENT TRANSLATION
REGISTER 0

31
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____I.

TRANSPARENT TRANSLATION
REGISTER 1

'--_____________~I

MMUSR} MMU STATUS REGISTER

. Figure 3. Supervisor Programming Model Supplement

MOTOROLA
3-112

M68000 FAMILY

REFERENCE

MC68030

USER BYTE
(CONDITION CODE REGISTER)

SYSTEM BYTE

I
15

II
11

CARRY
TRACE
ENABLE

INTERRUPT
PRIORITY MASK

OVERflOW
1--_ _ _ _

ZERO

SUPERVISOR/USER
STATE-----J
L..-_ _ _ _ _ _

MASTER/INTERRUPT
STATE _ _ _ _---J

1-.-_ _ _ _ _ _ _

NEGATIVE
EXTEND

Figure 4. Status Register

DATA TYPES AND ADDRESSING MODES

INSTRUCTION SET OVERVIEW

Seven basic data types are supported on the MC68030.
These are:

The MC68030 instruction set is shown in Table 2. Each
instruction, with few exceptions, operates on bytes, words,
and long words, and most instructions can use any of
the 18 addressing modes. The MC68030 is upward sourceand object-level code compatible with the M68000 Family
because it supports all of the instructions that previous
family members offer. Included in this set are the bit field
operations, binary coded decimal support, bounds checking, additional trap conditions, and additional mutli-processing support (CAS and CAS2 instructions) offered by
the MC68020. The new instructions supported by the
MC68030 are a subset of the instructions introduced by
the MC68851 paged memory management unit and are
used to communicate with the MMU.

• Bits
• Bit Fields (String of consecutive bits, 1-32 bits long)
• BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digiti
byte)
• Byte Integers (8 bits)
• Word Integers (16 bits)
• Long Word Integers (32 bits)
• Quad Word Integers (64 bits)
In addition, operations on other data types, such as memory addresses, status word data, etc., are provided in the
instruction set. The coprocessor mechanism allows direct
support of floating-point data types with the MC68881
floating-point coprocessor, as well as specialized userdefined data types and functions.
The 18 addressing modes, shown in Table 1, include
nine basic types:
• Register Direct
• Register Indirect
• Register Indirect with Index
• Memory Indirect
• Program Counter Indirect with Displacement
• Program Counter Indirect with Index
• Program Counter Memory Indirect
• Absolute
• Immediate
The register indirect addressing modes support postincrement, predecrement, offset. and indexing. These
capabilities are particularly useful for handling advanced
data structures common to sophisticated applications and
high level languages. The program counter relative mode
also has index and offset capabilities; programmers find
that this addressing mode is required to support positionindependent software. In addition to these addressing
modes, the MC68030 provides index sizing and scaling;
these features provide performance enhancements to the
programmer.

M68000 FAMILY
REFERENCE

INSTRUCTION AND DATA CACHES
Studies have shown that typical programs spend most
of their execution time in a few main routines or tight
loops. This phenomenon is known as locality of reference, and has an impact on the performance of the program. The MC68010 takes limited advantage of this
phenomenon with the loop mode of operation that can
be used with the DBcc instruction. The MC68020 takes
much more advantage of locality with its 256-byte onchip instruction cache. The MC68030 takes further advantage of cache technology to provide the system with
two on-chip caches, one for instructions and one for data.
MC68030 CACHE GOALS

Similar to the MC68020, there were two primary goals
for the MC68030 microprocessor caches. The first design
goal was to reduce the processor external bus activity
even more than what was accomplished with the
MC68020. The second design goal was to increase effective CPU throughput as larger memory sizes or slower

MOTOROLA
3-113

MC68030

Table 1. MC68030 Addressing Modes
Syntax

Addressing Modes
Register Direct
Data Register Direct
Address Register Direct

Dn
An

(An)
(An)+
-(An)
(d 16,An)

Indirect
Indirect with Post Increment
Indirect with Predecrement
Indirect with Displacement

Register Indirect with Index
Address Register Indirect with Index (a-Bit Displacement)
Address Register Indirect with Index (Base Displacement)

(da,An,Xn)
(bd,An,Xn)

Memory Indirect
Memory Indirect Post-Indexed
Memory Indrect Pre-Indexed

([bd,Anl.Xn,od)
([bd,An,Xnl.od)

Program Counter Indirect with Displacement

(d 16,PC)

Program Counter Indirect with Index
PC Indirect with Index (a-Bit Displacement)
PC Indirect with Index (Base Displacement)

(da,PC,Xn)
(bd,PC,Xn)

Program Counter Memory Indirect
PC Memory Indirect Post-Indexed
PC Memory Indirect Pre-Indexed

([bd,PC1,Xn,od)
([bd,PC,Xnl.od)

Absolute
Absolute Short
Absolute Long

xxx.W
xxx.L

Immediate

#(data)

NOTES:
Dn = Data Register, DO-D7
An = Address Register, AO-A7
d a , d 16 = A twos-complement, or sign-extended displacement; added as part of the
effective address calculation; size is a (d a ) or 16 (d 16 ) bits; when omitted,
assemblers use a value of zero.
Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE,
where SIZE is.W or.L (indicates index register size) and SCALE is 1, 2,4, or
a (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional.
bd = A twos-complement base displacement; when present, size can be 16 or 32
bits.
od = Outer displacement, added as part of effective address calculation after any
memory indirection; use is optional with a size of 16 or 32 bits.
PC = Program Counter
(data) = Immediate value of a, 16, or 32 bits
( ) = Effective Address
[I = Use as indirect address to long word address.

memories increased average access time. By placing a
high speed cache between the processor and the rest of
the memory system, the effective memory access time
becomes:
tacc = h*tcache + (1 - h)*t ext
where tacc is the effective system access time, tcache is
the cache access time, text is the access time of the rest
of the system, and h is the hit ratio or the percentage of
time that the data is found in the cache. Thus, for a given
system design, two MC68030 on-chip caches provide an
even more substantial CPU performance increase over
that obtainable with the MC68020with its instruction
cache. Alternately, slower and less expensive memories
can be used for the same processor performance.

MOTOROLA
3-114

The throughput increase in the MC68030 is gained in
three ways. First, the MC68030 caches are accessed in
less time than is required for external accesses, providing
improvement in the access time for items residing in the
cache. Second, the burst filling of the caches allows instruction and data words to be found in the on-chip caches
the first time they are accessed by the micromachine,
with the time required to bring those items into the cache
minimized. This has the capability of lowering the average access time for items found in the caches even further.
Third, and perhaps most importantly, the autonomous
nature of the caches allows instruction stream fetches,
data fetches, and a third external access to all occur si-

M68000 FAMILY

REFERENCE

MC68030

Table 2. Instruction Set
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL, ASR

Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
Arithmetic Shift Left and Right

Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST

Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit-Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit

CAS
CAS2
CHK
CHK2

Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and
Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and
Lower Bounds

CLR
CMP
CMPA
CMPI
CMPM
CMP2

Description

Mnemonic

Description

DBcc
DIVS, DIVSL
DIVU, DIVUL

Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide

EOR
EORI
EXG
EXT, EXTB

Logical Exclusive OR
Logical Exclusive OR Immediate
Exchange Registers
Sign Extend

ILLEGAL

Take Illegal Instruction Trap

JMP
JSR

Jump
Jump to Subroutine

LEA
LINK
LSL, LSR

Load Effective Address
Link and Allocate
Logical Shift Left and Right

MOVE
MOVEA
MOVE CCR
MOVE SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU

Move
Move Address
Move Condition Code Register
Move Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quck
Move Alternate Address Sapce
Signed Multiply
Unsigned Multiply

NBCD
NEG
NEGX
NOP
NOT

Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement

OR
ORI

Logical Inclusive OR
Logical Inclusive OR Immediate

PACK
PEA

Pack BCD
Push Effective Address

RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
RTS

Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore Codes
Return from Subroutine

SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP

Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words

TAS
TRAP
TRAPcc
TRAPV
TST

Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand

UNLK
UNPK

Unlink
Unpack BCD

MMU INSTRUCTIONS
r-----------,----------------------------,
r-----------,----------------------------,

PMOVE
PLOAD

Move to or from
MMU Registers
Load Page Descriptor into ATC

PTEST
PFLUSH
PFLUSHA

Test Translation
Flush Selected ATC Entries
Flush Entire ATC

COPROCESSOR INSTRUCTIONS

r-----------,----------------------------,
cpBCC
cpDBcc
cpGEN

M68000 FAMILY

REFERENCE

Branch Conditionally
Test Coprocessor Condition,
Decrement and Branch
Coprocessor General Instruction

.-----------~----------------------------,

cpRESTORE
cpSAVE
cpScc
cpTRAPcc

Restore Internal State of Coprocessor
Save Internal State of Coprocessor
Set Conditionally
Trap Conditionally

MOTOROLA
3~115

MC68030

multaneously with instruction execution. For example; if
the MC68030 requires both an instruction stream access
and an external peripheral access, and the instruction is,
resident in the on-chip cache, the peripheral access will
proceed unimpeded rather than being queued behind the'
instruction fetch; Additionally, if a data operand was also
required, and it was resident in the data cache, it ccould
also be accessed without hindering either the instruction
access from its cache or the peripheral access external
to the chip. The parallelism designed into the MC68030
also allows multiple instructions to execute concurrently
so that several insternal instructions (those that do not
require any external accesses) could execute while the
processor is performing an external access for a previous
instruction.
INSTRUCTION CACHE

The instruction cache resident on the MC68030 is a 256byte direct mapped cache organized as 16 blocks consisting of four long words per block. Each long word is
independently accessible yielding 64 possible entries, with
A 1 selecting the correct word during an access. Thus each
block has a tag field made up of the upper 24 address
bits, the FC2 (supervisor/user) value, four valid bits (one
for each long word entry) and the four long word entries
(see Figure 5). The instruction cache is automatically filled
by the MC68030 whenever a cache miss occurs and using
the burst transfer capability, up to four long words can
be filled in one burst. Neither the instruction or data caches
can be manipulated directly by the programmer' except
by the use of the CACR register which provides cache
clearing and cache entry clearing facilities. The caches
can also be enabled/disabled through the use of this register. Finally, the system hardware can disable the onchip caches at any time by the assertion of the CDIS
signal.
DATA CACHE

The organization of the data cache is similar to that of
the instruction cache as shown in Figure 6. However,the
tag is composed of the upper 24 address bits, the four
valid bits, and all three function "code bits, explicitely
specifying the address space associated with each block.
The data cache employs a write-through policy with no
write allocation of data writes. In other words, if a cache
hit occurs on a write cycle, both the data cache and the
external device are updated with the new data. If a write
cycle generates a miss in the data cache, only the external
device is updated and no data cache entry is replaced or
allocated for that address.

OPERAND TRANSFER MECHANISMS
The MC68030 offers three different mechanisms by
which data can be transferred into and out of the chip.
Asynchronous bus cycles, compatible with the asynchronous bus on the MC68020, can transfer data in a
minimum of three clock cycles and the amount of data,
transferred on each cycle is determined by the dynamic
bus sizing mechanism on a cycl,e-by-cycle basis with the
DSACKx signals. Synchronous bus cycles are terminated
with the STERM (Synchronous Termination) signal and

MOTOROLA
3-116

always transfer 32-bits of data in a minimum of two clock
cycles, increasing the bus bandwidth available for other
bus masters, therefore increasing possible performance.
Burst mode transfers can be used to fill blocks of the
instruction and data caches when the MC68030 asserts
CBREQ (Cache Burst Request). After completing the first
cycle with STERM, subsequent cycles may accept data
on every clock cycle where STERM is asserted until the
burst is completed. Use of this mode can further increase
the available bus bandwidth in systems that use DRAMs
with page, nibble, or static column mode operation.
ASYNCHRONOUS TRANSFERS

Though the MC68030 has a full 32-bit data bus, it offers
the ability to automatically and dynamically downsize its
bus to 8 or 16 bits if peripheral devices are unable to
accommodate the entire 32 bits. This feature allows the
programmer the ability to write code that is not bus-width
specific. For example, long word (32 bit) accesses to pe-'
ripherals may be used in the code, yet the MC68030 will
transfer only the amount of data that the peripheral can
manage at one time. This feature allows the peripheral
to define its port size as 8, 16, or 32 bits wide and the
MC68030 will dynamically size the data transfer accordingly. using mutliple bus cycles when necessary. Hence.
programmers are not required to program for each device port size or know the specific port size before coding;
hardware designers have flexibility to choose implementations independent of software prejudices.
The dynamic bus sizing Is invoked with the use of the
DSACKx pins and occurs on a cycle-by-cycle basis. For
example, if the processor is 'executing an instruction that
requires the reading of a long word operand, it will attempt to read 32 bits during the first bus cycle to a long
word address boundary. If the port responds that it is 32
bits wide, the MC68030 latches all 32 bits of data and
continues. If the port responds that it is 16 bits wide. the
MC68030 latches the 16 valid bits of data and runs another cycle to obtain the other 16 bits of data. An 8-bit
port is handled similarly but with four bus read cycles.
Each port is fixed in the assignment to particular sections
of the data bus. However, the MC68030 has no restrictions concerning the alignment of operands in memory;
long word operands need not be aligned to long word
address boundaries. When misaligned data requires multiple bus cycles, the MC68030 automatically runs the minimum number of bus. cycles. Instructions must still be
aligned to word boundaries.
The timing of asynchronous bus cycles is also determined by the assertion of the DSACKx signals on a cycleby-cycle basis. If the DSACKx signals are valid 1.5 clocks
after the beginning of the bus cycle (with the appropriate
setup time), the cycle terminates in its minimum amount
of time corresponding to three clock cycles total. The
cycle can be lengthened by delaying DSACKx (effectively
inserting wait states in, one clock increments) until the
device being accessed is able to terminate the cycle. This
flexibility gives the processor the ability to communicate
with devices of varying speeds while operating at the
fastest rate possible for ,each device.
Use of the asynchronous transfer mechanism allows
external errors to abort cycles upon the assertion of BERR
'(BUS Error),or individual bus cycles to be retried with the

M68000 FAMILY
REFERENCE

:CS:
men

LONG WORD
SELECT

"T1co
mo
:Co
mo
2."

I~~

TAG

OJ>

ms:

F
C C C

A ••• A A A A A A A A A A A A A A A A A A A A A A A A

3 ••• 2 2
1 ••• 3

1 1

098

0 0 0 0 0 0 0 0 01

ACCESS ADDRESS

III

1 OF 16
SELECT

TAG

IIII

V V V V

TAG
REPLACE

DATA FROM INSTRUCTON
CACHE DATA BUS
DATA TO INSTRUCTION
CACHE HOLOING REGISTER

VALID

COMPARATOR

o
-;
o

w:::O
~O

..... r

-..J»

I-----.-.,L-)

ENTRY HIT

CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1

•

CACHE CONTROL LOGIC

s:
C')
0')

Figure 5. MC68030 On-Chip Instruction Cache Organization

o
Co\)

~~
~~I
00

LONG WORD
SElECT

TAG

::0

~
C C C

(")
0')

IP;~

00
0

A ••• A A A A A A A A A A A A A A A A A A A A A A A A

3 ••• 2 2

2 1 1 1 1 1 1

1 ••• 32109

654

1 0 000 0 0 0 0001

2 1 0 9 8

TAG

IVIVIVIV

.. .. .
..-I-I-I-

1 OF 16
SELECT

ACCESS ADDRESS

43210

---

TAG
REPLACE

DATA FROM DATA CACHE
DATA BUS
DATA TO
EXECUTION UNIT

VALID

COMPARATOR

s:en
00

::CO

"nO
m"n

::c»

m:s:

~r=

m-<

t------~

ENTRY HIT

CACHE SIZE =64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE 1

Figure 6. MC68030 On-Chip Data Cache Organization

•

CACHE CONTROL LOGIC

MC68030

simultaneous assertion ofBERR and HALT, after the
DSACKx signals have been asserted.
SYNCHRONOUS TRANSFERS

Synchronous bus cycles are terminated with the assertion of the STERM signal which automatically indicates that the bus transfer is for 32 bits. This input is not
synchronized internally thereby allowing two clock cycle
bus accesses to be performed if the signal is valid one
clock after the beginning of the bus cycle with the appropriate setup time. However, the bus cycle may be
lengthened by delaying STERM (inserting wait states in
one clock increments) until the device being accessed is
able to terminate the cycle as in the case of asynchronous
transfers. Additionally, these cycles may be aborted upon
the asserting of BERR, or they may be retried with the
simultaneous assertion of BERR and HALT, after the assertion of STERM.
BURST READ CYCLES

The MC68030 provides support for burst filling of its
on-chip instruction and data caches, adding to the overall
system performance. The on-chip caches are organized
with a block size of four long words, so that there is only
one tag for the four long words in a block. Since locality
of reference is present to some degree in most programs,
filling of all four entries when a single entry misses can
be advantageous, especially if the time spent filling the
additional entries is minimal. When the caches are burstfilled, data can be latched by the processor in as little as
one clock for each 32 bits.
Burst read cycles can be performed only when the
MC68030 requests them (with the assertion of CBREO)
and only when the bus cycles are terminated with STERM
as described above. If the CBACK (Cache Burst Acknowledge) input is valid at the appropriate time in the synchronous b~s cycle, the processor will keep the original
AS, DS, RIW, address, function code, and size outputs
asserted and will latch 32 bits from the data bus at the
end of each subsequent clock cycle that has STERM asserted. This procedure continues until the burst is complete (the entire block has been transferred), BERR is
asserted in lieu of STERM, or the CBACK input is negated.

EXCEPTIONS
KINDS OF EXCEPTIONS

M68000 FAMILY
REFERENCE

Tracing behaves like a very high priority, internally generated interrupt whenever it is processed. The other internally generated exceptions are caused by illegal
instructions, instruction fetches from odd addresses, and
privilege violations. Finally, the MMU can generate exceptions when it detects an invalid translation in the ATC
(Address Translation Cache) and an access to the corresponding address is attempted, or when it is unable to
locate a valid translation for an address in the translation
tables.

EXCEPTION PROCESSING SEQUENCE

Exception processing occurs in four steps. During the
first step, an internal copy is made of the status register.
After the copy is made, the special processor state bits
in the status register are changed. The S bit is set, putting
the processor into supervisor state. Also, the T1 and TO
bits are negated, allowing the exception handler to execute unhindered by tracing. For the reset and interrupt
exceptions, the interrupt priority mask is also updated.
In the second step, the vector number of the exception
is determined. For interrupts, the vector number is obtrained by a processor read that is classified as an interrupt acknowledge cycle. For coprocessor detected
exceptions, the vector number is included in the coprocessor exception primitive response. For all other exceptions, internal logic provides the vector number. This
vector number is then used to generate the address of
the exception vector.
The third step is to save the current processor status.
The exception stack frame is created and filled on the
supervisor stack. In order to minimize the amount of machine state that is saved, various stack frame sizes are
used to contain the processor state, depending on the
type of exception and where it occurred during instruction execution. If the exception is an interrupt and the M
bit is on, the M bit is forced off, and the short four word
exception stack frame is saved on the master stack which
indicates that the exception is saved on the interrupt stack.
If the exception is a reset, the M bit is simply forced off
and the reset vector is accessed.
The MC68030 provides the same extensions to the exeption stacking process as the MC68020. If the M bit in
the status register is set, the master stack pointer (MSP)
is used for all task related exceptions. When a non-task
related exception occurs (i.e., an interrupt), the M bit is
cleared and the interrupt stack pointer (lSP) is used. This
feature allows all the task's stack area to be carried within
a single processor control block and new tasks may be
initiated by simply reloading the master stack pointer and
setting the M bit.
The fourth and last step of exception processing is the
same for all exceptions. The exception vector offset is
determined by mutliplying the vector number by four.
This offset is then added to the contents of the vector
base register (VBR) to determine the memory address of
the exception vector. The new program counter is fetched
from the exception vector. The instruction at the address
given in the exception vector is fetched and normal instruction decoding and execution is started.

MOTOROLA
3-119

MC68030

MC68030 ON-CHIP
PAGED MEMORY MANAGEMENT
The full addressing range of the MC68030 is four gigabytes (4,294,967,296 bytes). However, most MC68030
systems implement a smaller physical memory. Nonetheless, by using virtual memory techniques, the system
can be made to appear to have a full four gigabytes of
physical memory available to each user program. In a
similar fashion, a virtual system provides user programs
access to other devices that are not physically present in
the system such as tape drives, disk drives, printers, or
terminals. The paged Memory Management Unit (MMU)
on the MC68030 provides the capability to easily support
a virtual system and virtual memory. In addition, it provides protection of supervisor areas from accesses by
user programs and also provides write protection on a
page basis. All this capability is provided along with maximum performance'as address translations occur in parallel with other' processor activities. For applications not
requiring the paged Memory Management Unit a register
bit is used to enable/disable this feature.
DEMAND PAGED IMPLEMENTATION

A typical system with a large addressing range such
as one with the MC68030 provides a limited amount of
high-speed physical memory that can be accessed directly by the processor while maintaining an image of a
much larger "virtual" memory on secondary storage devices such as large capacity disk drives. When the processor attempts to access a location in the virtual memory
map that is not resident in physical memory, the access
to that location is temporarily suspended while the nec c
essary data is fetched from secondary storage and placed
in physical memory; the suspended access is then either
restarted Or continued.
A paged system is one in which the physical memory
is subdivided into equal sized blocks called page frames
and the logical (untranslated) address space of a task is
divided into pages which have the same size as the page
frames. The operating system controls the allocation of
pages to page frames so that when data is needed from
the secondary storage device, it is brought in on a page
basis. The memory management scheme employed by
the MC68030 is called a "demand" implementation because a process does not need to specify in advance what
areas of its logical address space it requires. An access
to a logical address ,is interpreted by the system as a
request for the corresponding page.
The MMU on the MC68030 employs the same address
translation mechanism introduced by the MC68851 Paged
Memory Management Unit with possible page sizes
ranging from 256 bytes to 32K bytes.
TRANSLATION MECHANISM

Logical-to-physical address translation is the most frequently executed operation of the MC68030 MMU, so this
task has been optimized and can function autonomously.
The MMU initiates address translation by searching for
a descriptor with the address translation information (a
page descriptor) in the on-chip address translation cache

MOTOROLA
3-120

(ATC). The ATC is a very fast fully-assocative cache memory that stores recently used page descriptors. If the descriptor does not reside in the ATC then the MMU requests
external bus cycles of the bus controller to search the
translation tables in physical memory. After being located, the page descriptor is loaded into the ATC and the
address is correctly translated for the access, provided
no exception conditions are encountered.
The status of the page in question is easily maintained
in the translation tables. When a page must be brought
in from a secondary storage device, the table entry can
signal that this descriptor is invalid so that the table search
results in an invalid descriptor being loaded into the ATC.
In this way, the access to the page is aborted and the
processor initiates bus error exception processing for this
address. The operating system can then control the allocation of a new page in physical memory and can load
the page all within the bus error handling routine.
ADDRESS TRANSLATION CACHE

An integral part of the translation function described
above is the cache memory that stores recently used
logical-to-physical address translation information, or
page descriptors. This cache consists of 22 entries and
is fully-associative. The ATC compares the logical address and function code of the incoming access against
its entries. If one of the entries matches, there is a hit and
the ATC sends the physical address to the bus controller,
which then starts the external bus cycle (provided there
was no hit in the instruction or data caches for the access).
The ATC is composed of three major components: the
content-addressable memory (CAM) containing the logical address and function code information to be compared against incoming logical addresses, the physical
address store that contains the physical address associated with a particular CAM entry, and the control section
containing the entry replacement circuitry that implements the replacement algorithm (a variation of the leastrecently-used algorithm).
TRANSLATION TABLES

The translation tables supported by the MC68030 have
a tree structure, minimizing the amount of memory necessary to set up the tables for most programs, since only
a portion of the complete tree needs to exist at anyone
time. The root of a translation table tree is pointed to by
one or two root pointer registers that are part of the
MC68030 programmer's model; the CPU and supervisor.
Table entries at the higher levels of the tree (pointer tables) contain pointers to other tables. Entries at the leaf
level (page tables) contain page descriptors. The mechanism for performing table searches uses portions of the
logical address as indices for each level of the lookup.
All addresses contained in the translation table. entries
are physical addresses.
Figure 7 illustrates the structure of the MC68030 translation tables. Several determinants of the detailed table
structure are software selectable. The first level of lookup
in the table normally uses the function codes as an index
but this may be suppressed if desired. In addition, up to
15 of the logical address lines can be ignored for the
purposes of the table searching. The number of levels in

M68000 FAMILY
REFERENCE

MC68030

ROOT POINTER ------..

I
I

POINTER
TABLES

PAGE
TABLES

Figure 7. MMU Translation Table Tree Structure

the table indexed by the logical address can be set from
one to four, and up to 15 logical address bits can be used
as an index at each level. A major advantage to· using
this tree structure for the translation tables is the ability
to deallocate large portions of the logical address space
with a single entry at the higher levels of the tree. Additionally, portions of the tree itself may reside on a secondary storage device or may not exist at all until they
are required by the system.
The entries in the translation tables contain status information pertaining to the pointers for the next level of
lookup or the page themselves. These bits can be used
to designate certain pages or blocks of pages as supervisor-only, write-protected, or non-cacheable. If a page
is marked as non-cacheable, accesses within the page
will not be cached by the MC68030 instruction or data
caches and the ClOUT (cache inhibit out) signal is asserted for those accesses. In addition, the MMU automatically maintains history information for the pointers
and pages in the descriptors via the Used (U) and Modified (M) bits.
.
MMU INSTRUCTIONS
The MMU instructions supported by the MC68030 are
the PMOVE, PTEST, PLOAD, PFLUSH, and PFLUSHA instructions and they are completely compatible with the
corresponding instructions introduced by the MC68851
PMMU. Whereas the MC68851 required the coprocessor
interface to execute its instructions, the MC68030 MMU
instructions execute just like all other CPU instructions.
All of the MMU instructions are privileged (can be executed by the supervisor only) and are summarized below:
PMOVE
Used to move data to or from MMU registers.

M68000 FAMILY
REFERENCE

PTEST

Takes an address arid function code and
searches the ATC or the translation tables for
the corresponding entry. The results of the
search are available in the MMU status register (PSR)' and i5 often useful in determining
the cause of a fault.
Takes an address and function code and
PLOAD
searches the translation tables for the corresponding .page descriptor. It then loads the
ATC with the appropriate information.
PFLUSH
Flushes the ATC by function code or,function
code an~ logical address.
PFlUSHA Flushes all of the ATC entries.

TRANSPARENT TRANSLATION
Two transparent translation registers have been provided· on the MC68030 MMU to allow portions of the
logical address space to be transparently mapped and
accessed without corresponding entries resident in the
ATC. Each register can be used to define a range of logical
addresses from 16M bytes to 4G bytes with a base address and a mask. All addresses within these ranges will
not be mapped and protection is provided only on a basis
of read/write and function code.

COPROCESSOR INTERFACE
The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The interface
provided on the MC68030 is the same as that on the

MOTOROLA
3-121

MC68030

MC68020. Examples of these extensions are the addition
of specialized data operands for the existing data types.
or, for the case of floating point, the inclusion of new
data types and operations for them as implemented by
the MC68881 and MC68882 floating-point coprocessors.
Coprocessors are divided into two types by their bus
utilization characteristics. A coprocessor is a DMA coprocessor if it can control the bus independent of the
main processor. A coprocessor is a· non-DMA coprocessor if it does not have the capability of controlling the
bus. Both coprocessor types utilize the same protocol and
main processor resources. Implementation of a coprocessor as a DMA or non-DMA is based primarily on bus
bandwidth requirements of the coprocessor, performance, and cost issues.
The communication protocol between the main processor and the coprocessor necessary to execute a coprocessor instruction is based on a group of coprocessor
interface registers (CIRs) which have been defined for the
M68000 Family (see Table 3) and are implemented on
the coprocessor. The MC68030 hardware uses standard
read and write cycle to access the registers. Thus the
coprocessor interface doesn't require any special bus
hardware; the bus interface implemented by a coprocessor for its interface register set must only satisfy the·
MC68030 address, data, and control signal timing to guarantee proper communication with the CPU. The MC68030
implements the communication protocol with all coprocessors in hardware (and microcode) and handles all operations automatically so the programmer is only
concerned with the instructions and data types provided
by the coprocessor as extensions to the MC68030 instruction set and data types.
Since the CIRs are accessed via normal read and write
cycles, coprocessors can be used as peripheral devices

Table 3. Coprocessor Interface Registers
Register

Function

RJW

Response

Requests Action from CPU

Control

CPU Directed Control

Save

Initiate Save of Internal State

Restore

Initiate Restore of Internal
State

Operation Word

Current Coprocessor
Instruction

Command Word

Coprocessor Sl?ecific
Command

Condition Word

Condition to be Evaluated

Operand

32-Bit Operand

Specifies CPU Register or Mask

Instruction Address

Pointer to Coprocessor
Instruction

RiW

Operand Address

Pointer to Coprocessor
Operand

RiW

MOTOROLA
3-122

R
RiW

RiW
R

by other M68000 Family members that do not support
the coprocessor interface. The communcation protocol
can be easily emulated by addressing the CIRs appropriately and passing the necessary commands and operands required by the coprocessor. In addition to the
CIRs, the coprocessor contains those registers added to
the MC68030 programmer's model for specific coprocessor operations. For example, the Motorola floatingpoint coprocessors contain the CIRs as well as eight 80bit floating-point data registers and three 32-bit controll
status registers.
Up to eight coprocessors are supported in a single
MC68030 system with a system-unique coprocessor
identifier encoded in the coprocessor instruction. When
accessing a coprocessor, the MC68030 executes standard
bus cycles in CPU address space, as encoded by the function codes, and places the coprocessor identifier on the
address bus to be used by chip-select logic to select the
particular coprocessor. Since standard bus cycles are used,
the coprocessor may be located according to system design requirements, whether it be located on the microprocessor local bus, on another board on the system bus,
or any other place where the chip-select and coprocessor
protocol using standard bus cycles can be supported.
COPROCESSOR PROTOCOL
Interprocessor transfers are all initiated by the main
processor during coprocessor instruction execution. During the processing of a coprocessor instruction, the main
processor transfers instruction information and data to
the associated coprocessor, and receives data, requests,
and status information from the coprocessor. These
transfers are all based on standard read and write bus
cycles.
The typical coprocessor protocol which the main processor follows is:
a) The main processor initiates the communication
by writing command information to a location in
the coprocessor interface.
b) The· main· processor reads the coporcessor response to that information.
1) The response may indicate that the coprocessor is busy, and main processor should
again query the coprocessor. This allows the
main processor and coprocessor to synchronize their concurrent operations.
2) The response may indicate some exception
condition; the main processor acknowledges
the· exception and begins exception processing.
3) The response may indicate that the coprocessor needs the main 'processor to perform
some service such as transferring data to or
from the coprocessor. The coprocessor may
also request that the main processor query
the coprocessor again after the service is
complete.
4) The response may indicate that the main processor is not needed for further processing of
the instruction. The communication is terminated, and the main processor is free to
begin execution ofthe next instruction. Atthis

M68000 FAMILY

REFERENCE

MC68030

point in the coprocessor protocol, as the main
processor continues to execute the instruction stream, the main processor may operate
concurrently with the coprocessor.
When the main processor encounters the next coporcessor instruction, the main processor queries the coprocessor until the coprocessor is ready; meanwhile, the
main pro.:essor can go on to service interrupts and do a
context switch to execute other tasks, for example.
Each coprocessor instruction type has specific requirements based on this simplified protocol. The coprocessor
interface may use as many extension words as required
to implement a coprocessor instruction.
PRIMITIVE/RESPONSE
The response register is the means by which the coprocessor communicates service requests to the main
processor. The content of the coprocessor response register is a primitive instruction to the main processor which
is read during coprocessor communication by the main
processor. The main processor "executes" this primitive,
thereby providing the services required by the coprocessor. Table 4 summarizes the coprocessor primitives that
the MC68030 accepts.

SIGNAL DESCRIPTION

Table 4. Coprocessor Primitives
Processor Synchronization
Busy with Current Instruction
Proceed with Next Instruction, If No Trace
Service Interrupts and Re-query, If Trace Enabled
Proceed with Execution, Condition True/False
Instruction Manipulation
Transfer Operation Word
Transfer Words from Instruction Stream
Exception Handling
Take Privilege Violation if S Bit Not Set
Take Pre-Instruction Exception
Take Mid-Instruction Exception
Take Post-Instruction Exception
General Operand Transfer
Evaluate and Pass (ea)
Evaluate (ea) and Transfer Data
Write to Previously Evaluated (ea)
Take Address and Transfer Data·
Transfer to/from Top of Stack
Register Transfer
Transfer CPU Register
Transfer CPU Control Register
Transfer Multiple CPU Registers
Transfer Multiple Coprocessor Registers
Transfer CPU SR and/or ScanPC

Figure 8 and Table 5 describe the signals on the
MC68030 and provide an indication of their function.

M68000 FAMILY
REFERENCE

MOTOROLA
3-123

MC68030

_ IPLO

FCO·FC2

FUNcnON COOES {

.. IPLl

AOORESS BUS {

AO·A31

OATABUS {

DO·D31

TRANSFER SIZE {

-..
-

-_.
ASYNCHRONOUS
BUS CONTROL

~
~

-.. BGACK

SIZl

}

HALT

OCS
MC68030

ECS

BERR

}

- STERM

}

. BUS ARBITRATION
CONTROL

.. RESET

BUS EXCEPTION
CONTROL

R/W
RMC
AS

STATUS

CIIN

-ClOUT

SYNCHRONOUS
BUS CONTROL

REFILL

DBEN

- BGBR

SIZO

-DSACKl

IPEND

_ AVEC

DSACKO ..

CACHE CONTROL {

INTERRUPT
CONTROL

IPL2

MMUDIS

}

_ CLK
.. VCC

_ GND

CBREO

EMULATOR
SUPPORT

_ CDiS

(10)
(14)

CBACK ..
~

Figure 8. MC68030 Functional Signal Groups

MOTOROLA
3-124

M68000 FAMILY

REFERENCE

MC68030

Table 5. Signal Index
Mnemonic

Function

Function Codes

Signal Name

FCO-FC2

3-bit function code used to identify the address space of each bus cycle.

Address Bus

AO-A31

32-bit address bus used to address any of 4,294,967,296 bytes.

Data Bus

00-031

32-bit data bus used to transfer 8, 16,24, or 32 bits of data per bus cycle.

SIZO/SIZl

Indicates the number of bytes remaining to be transferred for this cycle.
These signals, together with AO and A 1, define the active sections of the
data bus.

OCS

Identical operation to that of ECS except that OCS is asserted only during
the first bus cycle of an operand transfer.

External Cycle Start

ECS

Provides an indication that a bus cycle is beginning.

ReadlWrite

RIW

Defines the bus transfer as an MPU read or write.

t--.

Size

Operand Cycle Start

Read-Modify-Write Cycle

-RMC

Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.

Address Strobe

Indicates that a valid address is on the bus.

Data Strobe

Indicates that valid data is to be placed on the data bus by an external
device or has been placed on the data bus by the MC68030.

Data Buffer Enable

-DBEN

Provides an enable signal for external data buffers.

Data Transfer and Size Acknowledge DSACKO/DSACK 1 Bus response signals that indicate the requested data transfer operation
is completed. In addition, these two lines indicate the size of the external
bus port on a cycle-by-cycle basis.

-CIIN

Prevents data from being loaded into the MC68030 instruction and data
caches.

Cache Inhibit Out

ClOUT

Reflects the CI bit in ATC entries or a transparent translation register;
indicates that external caches should ignore these accesses.

Cache Burst Request

CBRED

Indicates a miss in either the instruction or data cache.

CBACK

Indicates that accessed device can operate in burst mode.

Cache Inhibit In

Cache Burst Acknowledge
Interrupt Priority level

---IPlO-IPl2

Interrupt Pending

IPEND

Autovector

AVEC

Bus Request
Bus Grant

Provides an encoded interrupt level to the processor.
Indicates that an interrupt is pending.
Requests an autovector during an interrupt acknowledge cycle.
Indicates that an external device requires bus mastership.
Indicates that an external device may assume bus mastership.

Bus Grant Acknowledge

BGACK

Indicates that an externa'i device has assumed bus mastership.

Reset

RESET

System reset.

Halt

HALT

Indicates that the processor should suspend bus activity.

BERR

Indicates an invalid or illegal bus operation is being attempted.

Bus Error
Synchronous Termination

STERM

Bus response signal that indicates a port size of 32 bits and that data may
be latched on the next falling clock edge.
Dynamically disables the on-chip cache to assist emulator support.

Cache Disable

CDIS

MMU Disable

MMUDIS

Dynamically disables the translation mechanism of the MMU.

Microsequencer Status

STATUS

Status indications for debug purposes.

Pipe Refill

REFill

Indicates when the instruction pipe is beginning to refill

Clock

ClK

Clock input to the processor.

Power Supply

VCC

+ 5 volt::': 5% power supply.

Ground

GND

Ground connection.

M68000 FAMILY
REFERENCE

MOTOROLA
3-125

MC68030

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range

THERMAL CHARACTERISTICS Characteristic
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case

Symbol

Value

Unit

VCC

-0.3 to + 7.0

Vin

-0.5 to +7.0

o to 70

°c

Tsta

-55 to 150

°c

PGA PACKAGE
Symbol

Value

6JA
61('

30*
15*

Rating
°CfW

*Estimated

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °C can be obtained from:
(1)

where:
= Ambient Temperature, °C
= Package Thermal Resistance, Junction-toAmbient, °CfW
PD
= PINT+PIIO
= ICC x VCC ' Watts - Chip Internal Power
PINT
= Power Dissipation on Input and Output Pins PliO
User Determined
For most applications PIIO

FUNCTION
CODES

ms:

-I

I""AI ADDRESS

Ips

2 1 0 31

L----------t.~

PAO-PA(PS)

CRP

r - - - - - - - - - - - - - - " T - - - REPLACEMENT DATA
SRP

ORP

I 1

RPT

5
3 4

I 1

~~::::::;::::r=:===~~

____
1
_,

••

----I

1PA(PS+ 1)-PA31

COMPARATORS

PAGE SIZE=2 PS =256/51211K/2K/4K/BK/16K/32K BYTES
STATUS INCLUDES: ATC ENTRY LOCKED OR BUS ERROREO. CACHE INHIBIT. MODULE DESCRIPTOR GATE. MODIFIED. AND WRITE PROTECT BITS

o-;
o:0

o
~r

w»

Figure 3. ATC with Task Alias, RPT, and Caches

("')
0')

00
00
(J'1

MC68851

MC68851 detects no exceptional conditions (e.g., write
violation), it then asserts the physical address strobe (PAS).
In addition to the address mappings, each entry in the
ATC also contains bits that describe the protection information for that mapping (e.g., read-only), a data cache
inhibit indicator (used, for instance, when memorymapped I/O registers must not be cached), a lock-entry
flag (used to freeze individual ATC translation entries),
as well as history information used by the MC68851 (used
by the ATC replacement algorithm to keep active translations in the ATC).
In order to improve utilization of the MC68851 address
translation cache in a multi-tasking environment, translation descriptors for multiple tasks can reside in the ATC
simultaneously. To control this, the logical portion of each
ATC entry has three additional bits, a 'task alias', that are
included in the compare operation to determine if a cache
hit has occurred. The task alias identifies one of eight
tasks that may have translation descriptors resident· in
the ATC simultaneously and is used as an extension to
the logical address during the cache comparison operation.
The task alias mechanism works in conjunction with
the MC68851 root pointers and the root pointer caching
function of the MC68851 Root Pointer Table (RPT). When
the MC68020 starts a new, task, the operating system
loads the' MC68851 CPU Root Pointer register with the
pointer needed for translations of the new task. The CPU
Root Pointer register of the MC68851 then contains the
address, in physical memory, ofthe root of the translation
table for the currently executing task. The RPT is a table
of eight recently-used CPU Root Pointers maintained onchip by the MC68851. Each of the eight entries in the RPT
has a unique 3-bit task alias associated with it .. These
three bits are included in each ATC entry, so eight tasks
can be distinguished among all ATC entries.
When the operating system initiates a new task, or
restarts a suspended one, it writes a value to the MC68851
CPU Root Pointer register identifying the location of the
translation table for that task. When this value is written,
it is compared by the MC68851 against all entries currently in the RPT. This is fast because the RPT is a cache
also. If no RPT match is found, then a new entry is made
in the RPT and the task alias associated with that entry
is assigned to the current task. When the RPT is full, the
new entry overwrites the oldest RPT entry, and this task
alias becomes associated with the new task. In this case,
the MC68851 automatically flushes any entries in the ATC
that are currently identified with this task alias, since they
are associated with the old task.
If the value loaded into the CPU Root Pointer register
matches an entry in the RPT, then the MC68851 already
has a task alias assigned to identify those ATC entries
that belong to the new task. So, none of the ATC entries
are flushed as they can be reused for address translations
of the new task. The eight entries of the RPT and the 64
entries of the ATC are well balanced. When a task is
restarted, it is very likely the ATC holds some of its entries
so the task begins execution immediately. Without task
aliasing, the new task would be delayed while the needed
working set of translation descriptors are loaded into the
ATC from the translation table in memory.

MOTOROLA
4-4

In addition to the CRP, the MC68851 main,tains exclusive root pointers for the supervisor (SRP) and for DMAtype devices and coprocessors (DRP) which also require
logical-to-physical address translations.

ADDRESS TRANSLATION TABLES
When a logical bus master (e.g., the processor) initiates
a cycle that does not have a corresponding translation
resident in the ATC, the MC68851 performs bus operations to load the mapping for that cycle from the translation tables in memory pointed to by the relevant root
pointer. To perform this search operation, the MC68851
simultaneoulsy aborts the logical bus cycle, signals the
master to retry the operation, and requests mastership
of the logical bus. Upon receiving indication that the logical bus is free, the MC68851 completes the bus arbitration sequence, assumes mastership of the bus, and begins
to search the translation tables pointed to by the relevant
root pointer to locate the needed translation descriptor
that describes the page accessed by this logical address.
After loading the required translation descriptor, the
MC68851 returns control of the bus to the logical master
to retry the previous bus cycle which can now be checked
for access rights and properly translated by the MC68851.
The operation of searching the translation tables and
reloading the ATC is called a 'table search'. The MC68851
automatically searches the translation tables when a
translation misses in the ATC and does so completely in
hardware, without any software assist from the operating
system. Using' hardware, the MC68851 has significantly
minimized the table search overhead when compared to
previous memory management schemes that required
software assistance.
The translation tables supported by the MC68851 have
a tree structure. The root of a translation table tree is
pointed to by one of the three Root Pointer registers:
CPU; Supervisor, or DMA. Table entries at the higher
levels of the tree (pointer tables) contain pointers to other
tables. Entries at the leaf level (page tables) contain page
descriptors. All addresses contained in the translation
table entries are physical addresses. The three root pointers allow the MC68851 to manage three simultaneous
activities: the CPU root pointer points at the translation
table tree for the currently executing task, the Supervisor
root pointer points to the operating system's translation
table, and the DMA root pointer manages the space of
an alternate bus master which could be a DMA controller.
Figure 4 illustrates the structure of the MC68851 translation tables. Several determinants of the detailed table
structure are software selectable. The first level of lookup
in the table normally uses the function codes as an index,
but this may be suppressed. The function codes are control signals output by the MC68020 that distinguish memory accesses as Supervisor/User and Program/Data space
accesses. The function codes can be used by the MC68851
to separate the address map into address spaces that
protect any Supervisor space from being corrupted by a
faulty User program and/or to prevent a Data access from
corrupting a Program space. The logical address can be
limited between 17 and 32 bits (inclusive) to control the

M68000 FAMILY
REFERENCE

MC68851

ROOT POINTER

•

POINTER
TABLES

PAGE
TABLES'

}

Figure 4. Me68851 Translation Table Tree Structure

necessary size of the corresponding translation table. The
number of levels in the table indexed by the logical address can be set from one to four, and up to 15 logical
address bits can be used as an index at each level.

PROTECTION MECHANISM
The MC68851 supports a comprehensive protection
mechanism that facilitates implementation of fully protected systems. In addition to the option of enforcing the
distinction of User and Supervisor modes normally found
in an M68000 system, the MC68851 also supports the
Access Level mechanism that provides finer granularity
of protection within the User address spaces.
The Access Level mechanism subdivides the logical
address spaces of User mode operations into one, two,
four, or eight level(s) of privilege. Routines operating at
different access levels can have different privileges to
memory and a facility is provided to closely control
changes in Access level.
The Access' Level for a bus cycle is encoded in the
highest order (zero, one, two, or three) bits of the logical
address generated by the CPU. The Access Level mechanism, when enabled, compares this value against the
current Access Level as specified in the current access
level (CAL) register. The current Access Level specifies
the highest privilege level that a task may assume at that
time. If the privilege level presented by the bus cycle is
more privileged then the current level allowed, then the
cycle is requesting a privilege in excess of its rights and
is aborted by the MC68851.
In the MC68851 protection scheme, the privilege associated with a task is specified by its Access Level. Smaller
values for access levels represent higher privilege levels.
In a system using eight access levels, level zero is the

M68000 FAMILY
REFERENCE

highest privilege in the hierarchy and level seven is the
lowest.
In order to access code and/or data that require a higher
level of privilege than is possessed by the current task,
the MC68851 supports the MC68020 module call (CALLM)
and return (RTM) instructions that allow a routine to
transfer execution control to a module operating at the
same or higher level of privilege and to return from that
module after completion of the module function. When
the MC68020 executes a CALLM instruction that requests
an increase in Access Level, the MC68020 automatically
communicates with the MC68851 Access Level mechanism via Access Level Control CPU Space cycles, to determine if the requested change is valid. The MC68851
checks the request against a module descriptor for that
operation and indicates the validity of that request to the
MC68020. The RTM instruction operates similarly except
that control is always passed from a task to a task of the
same or lesser privilege.

BREAKPOINTS
The MC68851 provides a breakpoint acknowledge facility to support the MC68020 and other processors with
an on-chip cache. When the MC68020 encounters a breakpoint instruction it executes a breakpoint acknowledge
bus cycle by reading from a predetermined address in
the CPU address space. The MC68851 decodes this address and responds by either providing a replacement
opcode for the breakpoint opcode and completing the
bus cycle normally (by asserting the data transfer and
size acknowledge outputs) or terminating the bus cycle
with an exception (by asserting bus error to initiate illegal
instruction exception processing). The MC68851 can be
programmed to signal the illegal instruction exception

MOTOROLA

4-5

MC68851

on every breakpoint or to provide the replacement opcode n times (1 ,,-;; n ,,-;; 255) before signaling the exception.
With eight sets of breakpoint registers, the MC68851 supports eight breakpoints simultaneously.
Debugging a MC68020-based system which uses an
on-chip cache is simplified with the MC68851 breakpoint
support. Programmers typically use a debug monitor
when debugging programs, which can place up to eight
breakpoints in the program's code when using the breakpoint support of the MC68851. The debug monitor replaces each target instruction with a breakpoint
instruction, passing the target opcode to the MC68851
with a skip count. During execution of the program, the
MC68020 encounters the various breakpoint instructions.
The MC68851 automatically provides the correct target
opcode to the MC68020 for each execution of the corresponding breakpoint instruction and count down the
skip count to zero. The MC68020 executes the substituted
instruction as if it were still in program memory and the
program continues with only a small overhead to retrieve
the substituted opcode. Once the skip count is exhausted
during breakpoint processing, the debug monitor regains
control through the illegal instruction exception handler.

COPROCESSOR CONCEPT
The M68000 Family coprocessor interface is an integral
part of the design of the MC68020 advanced microprocessor, the MC68881 floating-point coprocessor, and the
MC68851 paged memory management unit. The coprocessor interface allows the execution of special purpose
instructions that are logical extensions to the microprocessor. Each coprocessor (e.g., MC68851 or MC68881)
has an instruction set that reflects its special function.
These instructions may be executed merely by placing
the instruction opcode and parameters in the MC68020
instruction stream. The MC68020 decodes the coprocessor instruction and performs bus communication with the
coprocessor registers specifying the nature of the action
to be taken. Both the MC68020 and the coprocessor execute parts of the instruction, depending on which processor is best suited to handle a particular task.
The interchange of information and the division of responsibility between the processor and the coprocessor
are controlled by the coprocessor interface and this activity is transparent to the user/programmer. The addition
of a coprocessing unit to an MC68020 system is a logical
extension that simply complements the instruction set
executable by the processor.
The coprocessor interface is designed to be flexible,
functional, and expandable. The interface is intended to
support the current M68000 Family of devices and future
extensions to the Motorola coprocessor family, as well
as user-defined coprocessors for single or multiple coprocessor systems.

MC688S1 INSTRUCTIONS
The MC68851 implements an extension to the M68000
Family instruction set using the coprocessor interface.

MOTOROLA
4-6

These instructions provide control functions for:
• Loading and storing of PMMU registers,
• Testing access rights, and conditionals based on
the results of this test, and
• PMMU control functions.
The MC68851 instruction set extension to the MC68020
instruction set provides the software programmer a programming model that allows the registers and functions
implemented by the MC68851 to appear to the programmer as if actually available on-chip with the MC68020.
The programming model is shown in Figure 5.
The instruction set extensions for the MC68851 are as
follows:
PMOVE
Moves data to/from MC68851 register.
PVALID
Compares access rights of a logical address against
the current access level and traps if address requires
a higher privilege than allowed. This instruction can
be used by a routine to verify that an address passed
to it by a calling routine is a valid address.
PTESTR
Searches the translation tables and loads the status
and access rights information of a logical address used
for a read cycle into the MC68851 status register. This
instruction allows the operating system to quickly determine the cause of faults generated by a read cycle
from a particular logical address.
PTESTW
Searches the translation tables and loads the status
and access rights information of a logical address used
for a write access into the MC68851 status register.
This instruction allows the operating system to quickly
determine the cause of faults generated by a write
cycle to a particular logical address.
PLOADR
Searches translation tables and loads the ATC with a
translation for the specified logical address. The history information in the external translation tables is
updated to reflect that the physical page corresponding to the logical address has been used.
PLOADW
Searches translation tables and loads the ATC with a
translation for the specified logical address. The history information in the external· translation tables is
updated to reflect that the physical page corresponding to the logical address has been modified.
PFLUSH
Flushes translation cache entries by logical address,
function code, or function code and effective address.
The PFLUSH instructions allow the operating system
to easily remove entries from the ATC after making
modifications to the external translation tables.
PFLUSHA
Flushes all entries from the translation cache.
PFLUSHR
Flushes root pointer table and translation cache entries by root pointer.
PFLUSHS
Flushes entries from the ATC by logical address and/
or function code including globally shared entries.

M68000 FAMILY

REFERENCE

MC68851

PMMU CACHE STATUS (PCSR)

STATUS
INFORMATION
REGISTERS

PMMU STATUS (PSR)

CAL

VAL

PROTECTION
MECHANISM
CONTROL
REGISTERS

SCC

ACCESS CONTROL

BAOO

BACO

BAOl

BACI

BA02

BAC2

BA03

BAC3

BA04

BAC4

BA05

BAC5

BAD6

BAC6

BAD7

BAC7

BREAKPOINT
CONTROl
REGISTERS

Figure 5. MC68851 Programming Model

PSAVE
Saves the internal state of the MC68851 in order to
support fast context switching and MC68020 virtual
memory/virtual machine capabilities.
PRESTORE
Restores the internal state of the MC68851 stored by
the PSAVE instruction.
PBcc
Branches conditionally on MC68851 condition. The
conditional instructions provide the operating system
with a means by which program flow can be controlled
by MC68851 conditions.
PDBcc
Tests MC68851 condition, decrements a CPU register,
and branches.
PScc
Sets operand according to MC68851 condition.

M68000 FAMILY
REFERENCE

TRAPcc
Traps on MC68851 condition.

SIGNAL DESCRIPTION
This following paragraphs provide a brief description
of the input and output signals of the MC68851 paged
memory management unit. The signals are functionally
grouped as shown in Figure 6.
NOTE
The terms assertion and negation are used
extensively. This is done to avoid confusion
when dealing with a mixture of 'active low'
and 'active high' signals. The term assert and
assertion is used to indicate that a signal is

MOTOROLA

4-7

MC68851

RMC

K...

LAS
PAS
OS
BUS
CONTROL

PHYSICAL ADDRESS

R/W
DSACKl

K
A

DBDIS

SHARED ADDRESS

BERR

RESET

PBR
PHYSICAL {
BUS
ARBITRATION

PBG

PA8-PA31

MC68851
PAGED
MEMORY
MANAGEMENT
UNIT

AO-A7

HALT

"
I"

OSACKO

BUS {
EXCEPTION
CONTROL

LA8-LA31

LOGICAL ADDRESS

FUNCTION CODE

FCO-FC3

10"

V
r'\.

-"
DO-031

DATA BUS
.10"

"
SIZO
SIZl

PBGACK

}

TRANSFER
SIZE

CD
LBRI

ASYNC

LBRO
LBGI

LOGICAL BUS {
ARBITRATION

CLOCK

LBGO

VCC (8)

LBGACK

GND (8)

Figure 6. Functional Signal Groups

active or true, independent of whether that
level is represented by a high or low voltage.
The term negate or negation is used toindicate that a signal is inactive or false.

MC68851 is the bus master, these pins output the low
order eight bits of the physical address. With the inclusion
of AO through A7, both the logical and physical buses
have a 32-bit (4 gigabyte) linear addressing range.

LOGICAL ADDRESS BUS (LAS through LA31)

FUNCTION CODE (FCO through FC3)

These inputs are the lines on which the MC68851 accepts a logical address for translation or for internal operations. The logical address bus should be connected to
the address outputs of all logical bus masters.
If the logical address is less than 32 bits (logical address
space <2 32 bytes) as determined by the translation control register, the unused bits are ignored and should be
tied to a constant voltage level (either VCC or ground).

These three-state, bidirectional signals indicate the address space of the current bus cycle. When the MC68851
is performing translations, these signals provide the address space being accessed by the current logical bus
master. The MC68851 uses the function code associated
with a bus cycle as an extension to .the logical address
when creating entries in the address translation cache.
The function code may also be used. as an index from
the root pointer in the first level of a translation table
search.
The 4-bit function code consists of the three function
code outputs of the M68000 Family processor and a fourth
bit that indicates that a DMA access is in progress.
When the MC68851 is bus master it drives the function
code pins as' outputs with a constant value of FC3FCO = $5, indicating the supervisor data space.

PHYSICAL ADDRESS BUS (PAS through PA31)
These three-state outputs provide the physical address
for both address translations and MC68851-initiated bus
operations.
SHARED ADDRESS BUS (AO through A7)
The use of these three-state, bidirectional lines is shared
between the functions of the logical and physical buses.
When the MC68851 is performing address translations,
these signalsare input in order that the MC68851.bEi able
to monitor the entire logical address in the event that a
CPU space cycle accesses one of its registers. When the

MOTOROLA
4-8

DATA BUS (DO through 031)
These three-state bidirectional signals provide the general purpose data path between the MC68851 and other
devices. This bus may be dynamically sized through use

M68000 FAMILY
REFERENCE

MC68851

of the OSACKx signals, transferring 8, 16,24, or 32 bits
of information during a bus cycle. The most significant
byte of the data bus is 024 through 031.
In systems that do not use the MC68020 (or any other
32-bit CPU) as the main processor, the width of the data
bus used to communicate between the processor and the
MC68851 may be fixed at 16, or 8 bits. In such systems,
the dynamic bus sizing mechanism still functions but the
maximum amount of data transferred in a single cycle is
limited to the bus size. In either case, the processor data
bus is aligned towards the high order portion of the
MC68851 data bus - that is. an 8-bit master is connected
to 024 through 031 and a 16-bit master is connected to
016 through 031.
When the RESET signal is asserted, the MC68851 inputs
configuration information from the least significant byte
of the data bus (00-07). This information determines the
bus size for coprocessor operations, sets the 'decision
time' for determining whether or not an ATC hit has occurred, determines whether the CLI signal is asserted for
all MC68851-initiated bus operations, and sets the timing
for PAS and OS assertion during table searches.
TRANSFER SIZE (SIZO, SIZ1)
These three-state, bidirectional signals are used in conjunction with the dynamic bus sizing capabilities of the
MC68851. When the MC68851 is the bus master, the SIZE
signals are driven as outputs and when accessed as a
slave, these signals are inputs. Otherwise, the size signals
are ignored. Regardless of the state (input or output) of
these signals, they indicate the number of bytes remaining to be transferred during the current operand cycle.
An operand cycle is a bus cycle or sequence of bus
cycles required to transfer a complete operand.
BUS CONTROL SIGNALS
The logical and physical bus control signals are described in the following paragraphs.
Read-Modify-Write (RMC)
This three-state, bidirectional signal is used to indicate
that the bus cycle in progress is an indivisible read-modify-write cycle. This signal is asserted for the duration of
the read-modify~write sequence and should be used as
a bus lock to ensure integrity of operation of these cycles.
When the MC68851 is translating addresses, the assertion of RMC by the logical bus master indicates that
the master is performing a read-modify-write cycle and
that a write operation to the same operand is likely to
follow. When RMC is asserted during a read cycle, the
MC68851 performs access and privilege checking for that
cycle as if it were a write cycle in order that the operation
not'be aborted after having partially completed the write
portion of the cycle. In addition, physical bus arbitration
is suspended once the physical bus cycle for the address
translation is initiated.
When the MC68851 is bus master, RMC may be asserted to indicate that the operation in progress should
not be interrupted by other bus traffic and, hence, all
arbitration for the physical bus is suspended by the
MC68851 when 'this signal is asserted.

M68000 FAMILY

REFERENCE

Logical Address Strobe (LAS)
The assertion of this input indicates that the logical bus
master has driven the logical address bus, function code,
and Rm valid. When the MC68851 is being accessed as
a slave, the assertion of LAS also indicates that the SIZE
signals are driven valid.
Physical Address Strobe (PAS)
This three-state output is asserted when the MC68851
has driven a valid address on the physical address bus.
When the MC68851 is master of the logical bus, the
assertion of PAS also indicates that the function code, RI
W, and SIZE signals are valid.
Data Strobe (OS)
This bidirectional, three-state signal is used to control
the flow of information on the data bus.
When the MC68851 is selected by the CPU, OS is an
input that indicates that the MC68851 should drive the
data bus on a read cycle, or that the CPU has placed valid'
data on the bus during a write cycle.
When the MC68851 is the bus master, OS indicates that
the slave device should drive the data bus in the case of
a read cycle, or that the MC68851 has placed valid data
on the bus in the case of a write cycle. '
The data strobe is ignored for the purposes of address
translation.
ReadIWrite (Rm)
This bidirectional, three-state signal is used to indicate
the direction of transfer for a bus cycle.
When the MC68851 is translating addresses, the state
of the Rm signal is input in order to support write-pro-'
tection checking.
When the MC68851 register set is accessed by the CPU
for an operation, the Rm output by the CPU determines
the direction of data transfer. If this signal is asserted
(low) the MC68851 latches data from the data bus at the
termation of the cycle. If the signal is negated (high), the
MC68851 outputs data on the data bus and signals that
the transfer is complete.
When the MC68851 is bus master, the Rm signal is
driven as an output. A high level indicates a read from'
an external device, a low indicates a write to an external
device.
Data Transfer and Size Acknowledge (DSACKO, DSACK1)
These bidirectional, three-state signals, whether used
as inputs or outputs, are used to normally terminate a
bus cycle and to indicate the port size of the responding
device.
When the MC68851 register set is accessed by the CPU.
the OSACKx signals are output to indicate that valid data
has been or will be (see below) placed on the data bus
for a read cycle, or that data has been accepted from the
data bus for a write cycle. Note that the relationship between OSACKx and data is dependent on the operating
mode of the MC68851. When operating in the synchronous mode, the MC68851 drives the data bus on the same
clock edge that OSACKx is asserted. Otherwise, the
MC68851 drives the data bus a minimum of one clock
period before asserting the OSACKx signals.

MOTOROLA
4-9

MC68851

The DSACKx signals are monitored as inputs when the
MC68851 arbitrates for the logical bus. After receiving a
bus grant from the CPU, the MC68851 waits until LBGACK,
LAS, and both DSACKx signals are negated before asserting logical bus grant acknowledge in order to ensure
that the previous slave device has released connection
from the bus.
When the MC68851 is executing bus cycles as the physical bus master, the DSACKx signals are inputs to indicate
that a data transfer is complete and the port size of the
external device being accessed. During a read cycle, when
the MC68851 recognizes DSACKx, it latches the data and
then terminates the bus cycle; during a write cycle, when
the MC68851 recognizes DSACKx, the bus cycle is terminated.
When operating as bus master, the MC68851 synchronizes the DSACKx inputs and allows skew between the
two inputs of up to one quarter of a clock.
Data Buffer Disable (DBDIS)
This active-high output provides an enable to external
data buffers connected to the MC68851 data bus.
When the logical bus master reads the contents of one
of. the MC68851 registers, the MC68851 drives the data
bus with the required operand. Typical systems directly
connect the MC68851 data bus with that of the main processor and the combined bus is buffered before being
routed to a large number of physical address space devices. In order to avoid contention, the buffers between
the MC688511CPU bus and the bus driving the physical
memory must be disabled when the MC68851 drives the
bus. The MC68851 provides the control necessary to perform this function with the DBDIS signal.
In addition, DBDIS performs a function similar to the
function of the MC68020 DBEN signal. DB DIS can be used
to control data bus transceivers in order to avoid contention between the transceivers and the MC68851 data
bus drivers during table search operations.
Finally, DBDIS is driven during reset in order to isolate
the MC68851 data bus while configuration information is
being input.
BUS EXCEPTION CONTROL SIGNALS
The following paragraphs describe the bus exception
control signals for the MC68851.
Reset (RESET)
Assertion of this input signals the MC68851 to disable
the address translation mechanism, clear all breakpoints,
set the internal state to idle, and input configuration information from the data bus.
Halt (HALT)
HALT is a bidirectional, three-state signal.
When the MC68851 is the logical bus master, HALT is
an input and assertion of HALT stops all MC68851 bus
activity atthe completion of the current bus cycle. When
the MC68851 has been halted using this input, all control
signals, with the exception of bus arbitration outputs, are
placed in their inactive states and the physical address
bus remains driven with the value used during the previous bus cycle. Bus arbitration functions normally when
the MC68851 is halted.

MOTOROLA
4-10

When the MC68851 is translating addresses, HALT is
used as an output in conjunction with BERR and/or LBRO
to signal the current logical bus master to perform either
a 'relinquish and retry' or a 'relinquish' operation.
During address translation, the assertion of HALT by
an external device does not effect translation operations
of the MC68851.
Bus Error (BERR)
This bidirectional, three-state signal is used to indicate
that a bus cycle should be terminated due to abnormal
conditions.
When the MC68851 is bus master, BERR is an input
and assertion of BERR by an external device signals that
there has been some problem with the bus cycle currently
being executed. These problems may be the result of:
1) Non-responding devices, or
2) Various other application-dependent errors (for
example, parity errors).
When the MC68851 is translating addresses, bus error
is used as an output to the logical bus master. Bus error
is asserted by the MC68851 for the following conditions:
1) The BERR bit is set in the matched ATC entry,
2) A write or read-modify-write cycle is attempted
to a write-protected page,
3) An instruction breakpoint is detected and the associated count register is zero or it is disabled,
4) As a portion of the relinquish and retry operation
if:
a) the required address mapping is not resident in the ATC,
b) a write operation occurs to a previously
unmodified page,
c) a read from the response CIR causes a suspended PLOAD or PTEST instruction to be
restarted,
d) a module call operation references a descriptor that does not have a corresponding entry in the ATC.
5) An RMC cycle is attempted and a corresponding
descriptor with appropriate status is not resident
in the ATC,
6) The access level protection mechanism detects
an access violation.
The bus error signal interacts with the HALT signal to
determine if the current bus cycle should be retried or
aborted.
CACHE LOAD INHIBIT (CLI)
.During address translation this three-state output is
asserted by the MC68851 if the matched address translation cache entry has its CI (cache inhibit) bit set. Assertion of this output signals to external caches that the
data associated with the current bus cycle is non-cacheable.
In order to maintain the distinction between CPU space
and other address spaces (for example, supervisor program, ... , etc.) the MC68851 does not assert PAS for CPU
space cycles. Cache load inhibit is used to generate a
CPU space address strobe during CPU space cycles that
do not access the MC68851. CLI is asserted on the falling

M68000 FAMILY

REFERENCE

MC68851

edge of the clock and external qualification of CLI with
lAS and a CPU space indicator provides a CPU space
address strobe. CPU space cycles that access the MC68851
registers are decoded internally and generate no physical
bus activity. Note that if the MC68851 is not master of
the physical bus, CLI is not asserted until ownership of
the physical bus is returned to the MC68851.
When the MC68851 is performing table search operations, it continuously asserts CLI in order to prevent caching of translation table information. This function may be
suppressed during reset configuration if desired.

PAS is negated, indicating that neither the
MC68851 nor the logical bus master is using the
physical bus,
3) DSACKx are negated, indicating that no external
device is still driving the data bus, and
4) PBGACK is negated, indicating that no other device is still claiming bus mastership.
PBGACK must remain asserted as long as any device
other than the MC68851 is bus master.

ASYNCHRONOUS CONTROL (ASYNC)

The following paragraphs describe the five-wire bus
arbitration pins used to determine which device in the
system is the master of the logical bus.

When a logical bus master does not present logical bus
control signals with the exact timing specifications of the
MC68020, this input must be driven, with appropriate
setup and hold times, to inform the MC68851 that input
synchronization must take place.
Operating in a synchronous mode, the MC68851 utilizes known signal relationships in order to perform faster
translations. If the logical bus master does not present
signals conforming to these relationships (different control strobe timings and/or different operating frequency),
it must assert ASYNC p'rior to initiating bus activity.
CLOCK (ClK)
The MC68851 clock input is a TTL-compatible signal
that is internally buffered to develop internal clocks for
the memory management unit. The clock must conform
to minimum and maximum period and pulse width specifications and must be of a constant frequency.
Note that the MC68851 and the logical bus master may
operate at different clock frequencies.
PHYSICAL BUS ARBITRATION
This section describes the three-wire physical busarbitration circuitry of the MC68851 used to determine which
device in a system is the master of the physical bus.
The MC68851 is the default master of the physical bus
and any other devices requiring access to the bus must
arbitrate for mastership.
Physical Bus Request (PBR)
This input is the wire-OR of the bus request signals
from all potential physical bus masters and indicates that
some device other than the MC68851 requires mastership
of the physical bus.
Physical Bus Grant (PBG)
This output signal indicates to potential bus masters
that the MC68851 will release ownership of the physical
bus when the current bus cycle is completed.
Physical Bus Grant Acknowledge (PBGACK)
This input indicates that some other device has become
master of the physical bus. This signal should not be
asserted until the following conditions have been met:
') A physical bus grant (PBG) has been received
through the arbitration process,

M68000 FAMILY
REFERENCE

LOGICAL BUS ARBITRATION

Logical Bus Request In (LBRI)
The lBRI input indicates that a device with higher priority than the MC68851 or the current logical bus master
requires ownership of the logical bus.
Logical Bus Request Out (LBRO)
This output is asserted to inform the processor that the
MC68851 requires ownership of the logical bus and is
used as a portion of the relinquish operation and the
relinquish and retry operation.
The request input to the logical bus arbiter (usually the
main processor) should consist of the wire-OR of requests input to lBRllogically ORed with the lBRO output
of the MC68851.
Logical Bus Grant In (LBGI)
This input, generated by the MC68020, indicates that
the MC68020 will release ownership of the bus at the
completion of the current bus cycle, or, if an alternate
master is currently the owner of the bus, that the MC68020
. will not claim the bus after the alternate master has released it.
Logical Bus Grant Out (LBGO)
This output indicates that the MC68851 has recognized
and synchronized the assertion of lBGI by the MC68020,
has detected the assertion of lBRl, and is passing the
bus grant to an alternate logical bus master or to arbitration prioritization circuitry.
Logical Bus Grant Acknowledge (LBGACK)
This bidirectional, three-state signal indicates that a
logical bus master, other than the CPU, has taken control
of the logical bus.
This signal is asserted by the MC68851 to indicate when
it is the current logical bus master. LBGACK is also monitored as an input to determine when the MC68851 can
become bus master.
SIGNAL SUMMARY
Table 1 provides a summary of the electrical characteristics of the signals discussed in the previous paragraphs.

MOTOROLA
4-11

MC68851

Table 1. Signal Summary
Signal Name

Input/Output

Active
State

ThreeState

Logical Address Bus

LA8rLA31

Input

High

Physical Address Bus

PA8rPA31

Output

High

Yes

MC68851 Owns Physical Bus

Shared Address Bus

AOrA7

Input/Output

High

Yes

MC68851 Owns Logical and
Physical Buses

Function Codes

FCOrFC3

Input/Output

High

Yes

MC68851 Owns Logical and
Physical Buses

Data Bus

DOrD31

Input/Output

High

Yes

Read from MC68851 Registers or
MC68851 Write Cycle

. SIZOrSIZl

Input/Output

High

Yes

MC68851 Owns Logical and
Physical Buses

Signal Function

1----

Size
Cache Load Inhibit
Asynchronous Control
Read-Modify-Write Cycle

Driven by Me688S1 When

CLI

Output

Low

Always

ASYNC

Input

Low

RMC

Input/Output

Low

Yes

MC68851 Owns Logical and
Physical Buses

Logical Address Strobe

LAS

Input

Low

Physical Address Strobe

PAS

Output

Low

Yes

MC68851 Owns Physical Bus

Data Strobe

Input/Output

Low

Yes

MC68851 Owns Logical and
Physical Buses

ReadlWrite

RIW

Input/Output

High/Low

Yes

MC68851 Owns Logical and
Physical Buses

DSACKOrDSACK 1

Input/Output

Low

Yes

Access to Address Map Occupied
by MC68851 Interface Register Set

Data Transfer and Size
Acknowledge
Data Bus Disable

DBDIS

Output

High

Always

Bus Error

BERR

Input/Output

Low

Yes

Exceptional Condition is Generated
by Address Translation

Halt

HALT

Input/Output

Low

Yes

Exceptional Condition is Generated
by Address Translation

Reset

RESET

Input

Low

PBR

Input

Low

PBG

Output

Low

Always

PBGACK

Input

Low

Physical Bus Request
Physical Bus Grant

Logical Bus Request In

LBRI

Input

Low

Logical Bus Request Out

LBRO

Output

Low

Always

Logical Bus Grant In

LBGI

Input

Low

Physical Bus Grant Acknowledge

LBGO

Output

Low

Always

LBGACK

Input/Output

Low

Yes

MC68851 Has Assumed Mastership
of the Logical Bus

Clock

CLK

Input

Power Supply

VCC

Input

Ground

GND

Input

Logical Bus Grant Out
Logical Bus Grant Acknowledge

MOTOROLA
4-12

M68000 FAMILY
REFERENCE

MC68851

ELECTRICAL SPECIFICATIONS

MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature

Symbol

Value

Unit

VCC

-0.3 to +7.0

Vin

-0.5 to +7.0

o to 70

°c

Tstg

-55 to +150

°c

This device contains protective circuitry
against damage due to high static voltages
or electrical fields; however, it is advised that
normal precautions be taken to avoid application of any voltages higher than maximumrated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage
level (e.g., either GND or VC C)'

THERMAL CHARACTERISTICS - PGA PACKAGE
Characteristic
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case

Symbol

Value

Rating

6JA
6JC

30*
15*

°C/W
°C/W

III

*Estimated

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in DC can be
obtained from:
(1)

where:
T A = Ambient Temperature, DC
(}JA = Package Thermal Resistance, Junction-toAmbient, DC/W
Po = PINT+ PlIO
PINT = ICC x VCC, Watts - Chip Internal Power
PlIO = Power Oissipation on Input and Output
Pins - User Oetermined
For most applications PI/O 512
Clocks) (see Figure 17)

Clk Per

53A

79A

M68000 FAMIL V

REFERENCE

MOTOROLA

4-17

Me688S1

AC ELECTRICAL SPECIFICATIONS -

ALL BUS OPERATIONS (Continued)

Characteristic

No.

Mode

MC68851RC12

MC68851RC16

MC68851RC20

Min

Max

Min

Max

Min

Max

Unit

RESET Asserted to Bus Control Signals
Negated (VCC Active and Stable)
(see Figure 17)

Clk Per

RESET Negated to LAS Asserted
(see Figure 17)

Clk Per

RESET Negated to Mode Select Data
Invalid (Hold) (see Figure 17)

Mode Select Data Valid to RESET Negated
(Setup) (see Figure 17)

Clk Per

Clock Transition to HALT/BERR/LBRO Asserted
(Logical Master Relinquish and Retry)
(see Figure 11)

86A

LAS Asserted to HALT/BERR/LBRO Asserted
(Logical Master Relinquish and Retry)
(see Figure 12)

0.5

1.59

0.5

1.59

0.5

1.5.9

Clk Per

868

LAS Asserted to HALT/BERR/LBRO Asserted
(Logical Master Relinquish and Retry)
(see Figure 12)

3.0 f

Clk Per

HALT Negated to LBGACK-o Asserted
(see Figure 12)

LAS Negated to BERR-o Negated (Termination
of Relinquish and Retry) (see Figure 12)

Logical Address, FC, RMC, RIW Valid to Clock
High (Setup) (see Figure 11)

MS/OS

92A

Logical Address, FC. RMC. RIW, Valid to LAS
Asserted (see Figures 11. 15, and 16)

MS/OS

928

Logical Address. FC. RMC. R/W Valid to LAS
Asserted (see Figures 13, 15, and 16)

MAlOA

93A

LAS~egated

to Logical Address. FC. RMC.
RIW Invalid (Synch Mode)
(see Figures 11, 15. and 16)

MS/OS

938

LAS~egated to Logical Address. FC, RMC.

MA/OA

RIW Invalid (Asynch Mode)
(see Figures 13. 15, and 16)
95

Logical Address Valid to Physical Address
Valid (Translation Cache Hit or CPU Space
Cycle) (see Figures 11, 13. 15, and 16)

50 s

45 s

Size, Shared Address Valid to LAS Asserted
(Access to MC68851 Register)
(see Figures 15 and 16)

LAS Negated to Size, Shared Address Invalid
(Access to MC68851 Register)
(see Figures 15 and 16)

100

LAS Asserted to Clock Low (Setup Time)
(see Figure 11)

103

LAS Width Asserted (see Figures 11 and 13)

1.5

Clk Per

0.5

1.5

LAS, DS Width Negated (see Figure 11)

0.5

Clk Per

104A

LAS, DS Width Negated (see Figure 13)

105

ASYNCH Asserted to LAS, DS Asserted
(see Figure 13)

1.5

104

1.5

1.!:i

MOTOROLA
4-18

ns
Clk Per

M68000 FAMILY
REFERENCE

MC68851

AC ELECTRICAL SPECIFICATIONS - ALL BUS OPERATIONS (Continued)
Characteristic

No.

Mode

MC68851RC12

MC68851RC16

Min

Max

MC68851 RC20
Min

Max

Unit

106

LAS, DS Negated to ASYNCH Negated
(see Figures 11 and 13)

107

ASYNCH Negated to LAS, DS Asserted (For
Synchronous Next Cycle) (see Figure 11)

1.5

Clk Per

108

Data Valid to DS Asserted (Write Setup Time
to MC68851) (see Figure 16)

109A

DS Negated to Data Invalid (Write Hold Time
to MC68851) (see Figure 16)

109B

LAS Negated to Data High Impedance'
(see Figure 16)

110

DSACKx-o Asserted to DSACKy-o Valid
(see Figures 15 and 16)

20 r

15 r

10 r

111

Clock High to DSACKx-o Asserted
(see Figures 15 and 16)

112A

LAS Asserted to DSACKx-o Asserted
(see Figures 15 and 16)

2.0

Clk Per

112B

LAS Asserted to DSACKx-o Asserted
(see Figures 15 and 16)

2.0

Clk Per

113

LAS Negated to DSACKx-o, BERR-o Negated
(see Figures 15 and 16)

114

LAS Negated to DSACKx-o, BERR-o
High Impedance (see Figure 15)

115

Clock Low to PAS Asserted (see Figure 11)

35 e

25 e

20 e

116

Clock Transition (Rising or Falling Edge) to
PAS Asserted (see Figures 11 and 13)

35 e

25 e

20 e

Clock Low to CLI Asserted
(see Figures 11 and 15)

40 e

30 e

25 e

117

LAS Asserted to PAS Asserted (Synchronous
Translation with ATC Hit) (see Figure 11)

0.59

1.59

0.59

1.59

0.59

1.59

Clk Per

118

LAS Negated to PAS Negated
(see Figures 11 and 13)

119

Physical Address Valid to PAS Asserted
(see Figure 11)

116A

120A

PAS Negated to Physical Address Invalid
(see Figure 13)

120B

PAS Negated to Physical Address Invalid
(see Figure 13)

0.5 f

121

LAS Asserted to PAS Asserted (Asynchronous
Operation Only) (see Figure 13)

0.5 f

3.0 i

122

LAS Negated to PAS High Impedance (PBR
Asserted by Alternate Physical Master)
(see Figures 11 and 14)

123

Physical Address Valid to CLI Asserted (CPU
Space Cycle Not Accessing MC68851)
(see Figures 15 and 16)

0.5 v

124A

LAS Asserted to CLI Asserted (CPU Space
Cycle Not Accessing MC68851)
(see Figures 15 and 16)

M68000 FAMILY

REFERENCE

3.0 i

0.5 f

3.0 i

Clk Per

3.0 v

0.5 v

3.0 v

0.5 v

3.0 v

Clk Per

MOTOROLA
4-19

•

MC68851

AC ELECTRICAL SPECIFICATIONS -

ALL BUS OPERATIONS (Concluded)
MC68851RC12

Characteristic

No.

Mode

MC68851RC16

MC68851 RC20

Min

Max

Min

Max

Min

Max

Unit

124B

LAS Asserted to CLI Asserted (CPU Space
Cycle Not Accessing MC68851)
(see Figures 15 and 16)

0.5 v

1.5v

0.5 v

1.5v

0.5 v

1.5v

Clk Per

126

LAS Negated to CLI Negated (CPU Space
Cycle Not Accessing MC68851)
(see Figures 15 and 16)

127

CLI Negated to Physical Address Invalid (CPU
Space Cycle Not Accessing MC68851)
(see Figures 15 and 16)

128

PAS Asserted to CLI Asserted (Not CPU Space
Access) (see Fig u re 11)

129

PAS Negated to CLI Negated (Not CPU Space
Access) (see Figu're 11)

15
30

NOTES:
a) In this specification the terms 'high', 'low', 'asserted', 'negated', 'valid', and 'invalid' are used frequently to describe a signal
state. For inputs to the MC68851, 'high' indicates that the signal conforms to the VIH voltage specification while 'low' indicates
that the VIL specification is satisfied. Similarly, a MC68851 output is 'high' if it conforms to the VOH specification and 'low' if
it conforms to the VOL parameter. An active·low input (output) is asserted if it satisfies the respective VIL (VOL) requirements
and negated if it satisfies the VIH (VOH) specification. A signal is 'valid' if it conforms to either the voltage high or the voltage
low specifications and is an appropriate value for the current operation (for example, Rlw should output a valid low during an
MC68851 initiated write cycle). A signal is 'invalid' if it either does not conform to the VH or VL specifications or is an inappropriate
value for the current operation as above.
b) In order to better understand the parameters given, a 'mode' identification is included with each specification: X indicates that
this specification is valid in any operating mode whatever; T indicates that the MC68851 is the current bus master and is
performing a table search operation; M indicates that the MC68851 is mapping translations for the current bus master with the
designation MS indicating that the master is operating synchronously with the MC68851, MA indicating an asynchronous
master, and MX indicating that the parameter is valid for any type of logical master; 0 indicates that the parameter ,is valid for
operations which access the internal registers of the MC68851.
c) Due to the numerous MC68851 signals that are used as inputs in one operating mode and as outputs in another, some attempt
has been made to clarify whether a particular signal is acting as an input or as an output in cases where ambiguity is possible.
The suffix "-0" indicates that the signal is an output of the MC68851 while the suffix "_i" indicates that this signal is acting as
an input to the MC68851.
d) The maximum value for parameter #47A is specified in order that the system designer may deterministically identify the clock
edge on which an asynchronous input to the MC68851 will be recognized. Any signal that meets the minimum specified setup
time to an appropriate clock edge (rising/falling) for that signal to be recognized on, and does not exceed the maximum time,
is guaranteed to be recognized as asserted on that edge. Signals that do not meet the minimum setup time mayor may not
be recognized; signals that exceed the maximum specified setup time may be recognized on the previous rising/falling clock
edge.
'
e) The actual assertion delay from the low-going clock edge that causes the strobe(s) to assert includes the time specified in the
parameter plus any additional delay specified on 03/04 during MC68851 configuration at RESET.
f) The actual assertion delay from the assertion of LAS when mapping in the asynchronous mode is the time specified in the
'
parameter plus any additional delay specified on 03/04 during MC68851 configuration at RESET.
g) The actual assertion delay from the assertion of LAS is the time specified in the parameter plus any additional delay specified
on 03/04 during MC68851 configuration at RESET. This specification has a range of one clock period in order to allow for cases
in which the CPU exhibits a best-case (minimum) assertion delay for the LAS signal relative to the clock while the MC68851
PAS or CLI outputs exhibit worst-case (maximum) assertion delays. When operating in the synchronous translation mode, the
MC68851 asserts PAS (CLI) on the falling edge of the clock (plus additional specified delay) one clock period afte'r the CPU
drives LAS.
h) The worst case assertion delay for this specification can be reduced to 5.5 clock periods if the early processing startup mode
of operation is disabled. '
This maximum can be reduced to 2.5 clock periods if the logical address strobe (LAS) high time (negated period) is one clock
period or greater.

j) This specification also applies to the signals AOrA7, FCOrFC3, SIZOrSIZ1, and RMC if the MC68851 is awaiting the negation of
PBGACK to initiate or complete a table search operation.
k) This number can be reduced to ± 5 nanoseconds if the strobes have equal load.

MOTOROLA
4-20

M68000 FAMILY

REFERENCE

MC68851

NOTES:
I) If the asynchronous setup time (#47) requirements are satisfied, the DSACKx low to data setup (#31) and DSACKx low to BERR
low setup time (#48) can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following
clock cycle. BERR must only satisfy the late BERR low to clock low setup time (#27A) for the following clock cycle.
m) This parameter specifies the maximum allowable skew between DSACKO to DSACK1 asserted or DSACK1 to DSACKO asserted.
Specification #47 must be met by either DSACKO or DSACK1.
n) In the absence of DSACKx, BERR is an asynchronous input using the asynchronous input setup time (#47).
0) DBDIS may stay asserted on consecutive write cycles (e.g., a retry of an MC68851 write operation).

p) Actual value depends on the clock input waveform.
q) This number can be reduced to 5 nanoseconds if CLI and PAS have equal loading.
r) This specification is valid only if the loading of the DSACKx outputs are equal (± 50 pF).
s) This specification can be reduced to 35 ns or 50 ns at 16.67 and 12.5 MHz, respectively for those bits of the logical address that
are not translated by the MC68851. This includes all bits of the logical address if the MC68851 translation mechanism is disabled,
and all bits, LAn, of the logical address (page size 2m) such that n ~ m.
u) This specification also applies to the signals AOrA7, FCOrFC3, and SIZOrSIZ1 if the MC68851 is granting physical bus mastership
to an alternate device during a table search operation.
v) The actual assertion delay from the assertion of LAS is the time specified in the parameter plus a delay derived from the reset
configuration. Although the reset configuration allows additional strobe delay in half clock increments, CLI is always asserted
relative to the falling edge of the clock and so can only be delayed by full clock increments. Therefore, if a 1 or 2 half clock
delay is specified in the reset configuration, then .CLI assertion is delayed by 1 full clock.

AC ELECTRICAL SPECIFICATION DEFINITIONS
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times.
All signals are specified relative to an appropriate edge
of the MC68851 clock input and, possibly, relative to one
or more other signals.
The measurement of the AC specifications is defined
by the waveforms below. In order to test the parameters
guaranteed by Motorola, inputs must be driven to the
voltage levels specified. Outputs of the MC68851 are

M68000 FAMILY
REFERENCE

specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs to the
MC68851 are specified with minimum and, as appropriate maximum setup and hold times, and are measured
as shown. Finally, the measurement for signal-to-signal
specifications are also shown.
Note that the testing levels used to verify conformance
of the MC68851 to the AC specifications does not affect
the guaranteed DC operation of the device as specified
in the DC electrical characteristics.

MOTOROLA
4-21

III

MC68851

DRIVE
TO 2.4 V

+
eLK

OUTPUTS 1

VALID
OUTPUT n

MAX
OUTPUTS 2

INPUTS 3

OUTPUT n

2,0 V
VALID
0.8 V OUTPUT n+1

DRIVE ---.
TO 2.4 V
DRIVE ---.
TO 0.5 V
. . - DRIVE
TO 2.4 V

INPUTS4

..-DRIVE
TO 0.5 V

ALL SIGNALS5

2.0 V
0.8 V

Notes:
1 - This output timing is applicable to all parameters specified relative to the rising edge of the clock
2 - This output timing is applicable to all parameters specified relative to the falling edge of the clock
3 - This input timing is applicable to all parameters specified relative to the rising edge of the clock
4 - This input timing is applicable to all parameters specified relative to the falling edge of the clock
5 - This timing is applicable to all parameters specified relative to the assertion/negation of another signal
Legend:
A - Maximum output delay specification
B - Minimum output delay specification
C - Minimum input setup time specification
D - Minimum input hold specification
E - Signal valid to signal valid specification (maximum or minimum)
F - Signal valid to signal invalid specification (maximum or minimum)

Drive Levels and Test Points for AC Specifications

MOTOROLA
4-22

M68000 FAMILY

REFERENCE

MC68851

CLOCK

PAS·PA3l, AO·A 7,
SIZO/SIZ1, FCO·FC3

RMC

eLI

PAS

Riw

DBDlS

DSACKx

DATA

BERR

Key:

Indicates
Indicates
Indicates
alternate

that the signal
that the signal
that the signal
bus master

driven by the MC68851
driven by the Main Processor
driven by an external device or

Note: The Clock Signal is always depicted with a normal width line

Figure 9. MC68851 Initiated Read Cycle

M68000 FAMILY
REFERENCE

MOTOROLA
4-23

Me688S1

CLOCK

PAO·PA3I, LAO·LAB,
SIZO/SIZI, FCO·FC3

RMC

PAS

R/W

DBOIS

DSACKx

DATA

BERR

ALL ASYNC - - - - - " " '
INPUTS

Figure 10. MC68851 Initiated Write Cycle

MOTOROLA
4~24

M68000 FAMILV
REFERENCE

Me688S1

CLOCK

LAB·LA31. FCO·FC3.
SIZO/SIZI. AMC. AiW _.----p;_ _ _ _ _~--+-----_+-....._-

'-__

PAB·PA31

BEAR. HALT - - - - - - - - - ; - - - - - 1 h o . l
LBAO

Figure 11. Synchronous Mode Translation

M68000 FAMILY

REFERENCE

MOTOROLA
4-25

,l::>.~

(j)~

CLOCK

);

LA8-LA31. FCO-FC3.
SilO/Sill. RMC. Riw

LAS

PA8-PA31

PAS

eli

DBDlS

BERR

HALT

LBRO

LBGO

LBRI

S
en

LBGI

:::00

mo
-nO

m-n
:::0»

LBGACK

mS
2_

Or-

m-<

n
0)
00
00
U1

:::0

Figure 12. Logical Master Relinquish and Retry Timing Diagram

:as:
men
"00

me
::Ce
me

CLOCK

0):-

ms:
~

LAS-LA3l. AO-A7.
FCO-FC3. SIZO/SIZ1. R/w' RMC

LAS

DBDlS

OSACKx

PAS-PA3l

PAS

LBRI

LBRD

LBGI

LBGD

LBGACK

s:
o~
o
:Xl

f"O

1'.)1

-....Jl>

( 105)

.. I

ASYNC

S
n
en
Figure 13. Logical Bus Arbitration by Asynchronous Master Timing Diagram

00
00
U1
~

f"S::

"
'0
00-1

o
:JJ
o
~

PAS

os
R/W

OSACKx

OBOIS

DATA

PBR

PBG

s:
0'1
00

PBGACK

m,,"
::JJl>

ms:
~F

m-<

LAS (SEE NOTE 11

::JJ0

(')

CO
CO

CLOCK

PAO-PA31. AO-A7. R/w'
SIZO/SIZI. RMC

,,"0

Figure 14. Physical Bus Arbitration Timing Diagram

MC68851

CLOCK

LA8-LA31. AO·A7.
SilO/Sill

FCO·FC2
(FC3=0)

R/W

LAS

DBDIS

DATA

DSACKx

PA8·PA31

fLi
Figure 15. CPU~ace Read From MC68851 or i=rom Other Coprocessor
(CLI Asserted by MC68851) Timing Diagram

M68000 FAMILY

REFERENCE

MOTOROLA
4-29

Me688S1

ClOCK

LAB·LA31. AO·A 7.
SIZO/SIZI

FCO·FC2
(FC3=0)

R/W

LAS

OBOIS

OATA

OSACKx

PAB·PA31

eLi
Figure 16. CPU Space Write To MC68851 or To Other Coprocessor
(CLI Asserted by MC68851) Timing Diagram

MOTOROLA
4-30

M68000 FAMILY
REFERENCE

Me68851

CLOCK

+5V,-______________________________
VCC

III

DATA BUS

CONTROL
BUS

l~~almala~~~:....------

Figure 17. Reset and Mode Select Timing Diagram

M68000 FAMILY

REFERENCE

MOTOROLA
4-31

MC68851

PIN ASSIGNMENTS

000
M

FCI

LA26

LA25

LA22

LA21

LA18

LA17

LA16

LA13

LA12

LA9

LA8

.LA30.

LA29

LA27

LA23

LA19

VCC

LA15

LAll

031

029

028

021

000
K.

FC2

LA31

LA28

LA24

FCO

000

000
025

000

LAIO

030

027

024

GNO

VCC

026

023

022

017

LA20

GNO

LA14

020

FC3

000

VCC

GNO

019

018

016

000

PA9

015

PA8

000
PAID

Vcc

014

013

000

GNO

000

VCC

012

000

PAll

PA12

PA13

010

011

PAI4

PA16

PA17

GNO

PA 15

PA20

PA21

PA24

000
VCC .

PA27. PA31

o
ASYNC

LBGO

GNO

BERR

OSACK 1

R/W

OBOIS

ifMc

GNO

PA18

PA22 .. CLK

o
PA19

PA25

PA26

PA28

PAS

UiGAEK

VCC

HALT

PsR

SilO

o
os

PA23

PA29

PA30

LAS

LBRO

liiGi

Iiiiii

IT!

The Vee and GND pins are separated into four groups to provide individual power supply connections for the address
bus buffers, data bus buffers, and all other output buffers and internal logic.

Pin Group
Physical Address
Logical Address, Internal Logic
00-031
Internal Logic, Clocks

MOTOROLA
4-32

Vee

GND

OS, G2, J4

E4, G3, K5

E10,OG12, K9

09, G11, J10

M68000 FAMILY
REFERENCE

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68881

Technical ,Summary

HCMOS Floating-Point Coprocessor
The MC68881 floating-point coprocessor is a full implementation of the IEEE Standard for Binary
Floating-Point Arithmetic (754) for use with the Motorola M68000 Family of microprocessors. It is
implemented using VLSI technology to give systems designers the highest possible functionality in
a physically smal'l device.
Intended primarily for use as a coprocessor to the MC68020 32-bit microprocessor unit (MPU), the
MC68881 provides a logical extension to the main MPU integer data processing capabilities. It does
this by providing a very high performance floating-point arithmetic unit and a set of floating-point
data registers that are utilized in a manner that is analogous to the use of the integer data registers.
The MC68881 instruction set is a natural extension of all earlier members of the M68000 Family,
and supports all of the addressing modes of the host MPU. Due to the flexible bus interface of the
M68000 Family, the MC68881 can be used with any of the MPU devices of the M68000 Family, and
it may also be used as a peripheral to non-M68000 processors.
The major features of the MC68881 are:
•

Eight general purpose floating-point data registers, each supporting a full 80-bit extended precision real data format (a 64-bit mantissa plus a sign bit, and a 15-bit signed exponent).

•

A 67-bit arithmetic unit to allow very fast calculations, with intermediate precision greater than
the extended precision format.

•

A 67-bit barrel shifter for high-speed shifting operations (for normalizing etc.).

•

Forty-six instructions, including 35 arithmetic operations.

•

Full conformation to the IEEE 754 standard, including all requirements and suggestions.

•

Support of functions not defined by the IEEE standard, including a full set of trigonometric and
transcendental functions.

•

Seven data types: byte, word and long integers; single, double, and extended precision real
numbers; and packed binary coded decimal string real numbers.

•

Twenty-two constants available in the on-chip ROM, including

•

Virtual memory/machine operations.

•

Efficient mechanisms for procedure calls, context switches, and interrupt handling.

TI/

•

Fully concurrent instruction execution with the main processor.

•

Use with any host processor, on an 8-/ 16-; or 32-bit data bus.

III

e, and powers of 10.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA M68000 FAMILY

REFERENCE

MOTOROLA
4-33

Me68881

THE COPROCESSOR CONCEPT

HARDWARE OVERVIEW

The MC68881 functions as a coprocessor in systems
where the MC68020 or MC68030 is the main processor
via the M68000 coprocessor interface. * It functions as a
peripheral processor in systems where the main processor is the MC68000, MC68008, or MC68010.
The MC68881 utilizes the M68000 Family coprocessor
interface to provide a logical extension of the MC68020
registers and instruction set in a manner which is transparent to the programmer. The programmer perceives
the MC68020/MC68881 execution model as if both de~
vices are implemented on one chip.
A fundamental goal of the M68000 Family coprocessor
interface is to provide the programmer with an execution
model based upon sequential instruction execution by
the MC68020 and the MC68881. For optimum performance, however, the coprocessor interface allows concurrent operations in the MC68881 with respect to the
MC68020 whenever possible. In order to simplify the programmer's model, the coprocessor interface is designed
to emulate, as closely as possible, non-concurrent operation between the MC68020 and the MC68881.
The MC68881 is a non-OMA type coprocessor which
uses a subset of the general purpose coprocessor interface supported by the MC68020. Features of the interface
implemented in the MC68881 are as follows:

The MC68881 is a high performance floating-point device designed to interface with the MC68020 as a coprocessor. This device fully supports the MC68020 virtual
machine architecture, and is implemented in HCMOS,
Motorola's low power, small geometry process. This
process allows CMOS and HMOS (high-density NMOS)
gates to be combined on the same device. CMOS structures are used where speed and low power is required,
and HMOS structures are used where minimum silicon
area is desired. The HCMOS technology enables the
MC68881 to be very fast while consuming less power
than comparable HMOS, and still have a reasonably small
die size.
With some performance degradation, the MC68881 can
also be used as a peripheral processor in systems where
the MC68020 is not the main processor (e.g., MC68000,
MC68008, MC68010). The configuration of the MC68881
as a peripheral processor or coprocessor may be completely transparent to user software (i.e., the same object
code may be executed in either configuration).
The architecture of the MC68881 appears to the user
as a logical extension of the M68000 Family architecture.
Coupling of the coprocessor interface, allows the MC68020
programmer to view the MC68881 registers as though
the registers are resident in the MC68020. Thus, a
MC68020/MC68881 device pair appears to be one processor that supports seven floating-point and integer data
types, and has eight integer data registers, eight address
registers, and eight floating-point data registers.
The MC68881 programming model is shown in Figures
1 through 6, and consists of the following:

•

The main processor(s) and MC68881 communicate via
standard M68000 bus cycles.

•

The main processor(s) and MC68881 communications
are not dependent upon the instruction sets or internal
details ofthe individual devices (e.g., instruction pipes
or caches, addressing modes).

•

The main processor(s) and MC68881 may operate at
different clock speeds.

•

MC68881 instructions utilize all addressing modes
provided by the main processor; all effective addresses are calculated by the main processor at the
request of the coprocessor.

•

All data transfers are performed by the main processor at the request of the MC68881; thus memory management, bus errors, address errors, and bus
arbitration function as if the MC68881 instructions are
executed by the main processor.

•

Overlapped (concurrent) instruction execution enhances throughput while maintaining the program. mer's model of sequential instruction execution.

•

Coprocessor detection of exceptions which require a
trap to be taken are serviced by the main processor
at the request of the MC68881; thus exception processing functions as if the MC68881 instructions were
executed by the main processor.

•

Support of virtual memory/virtual machine systems
is provided via the FSAVE and FRESTORE instructions.

•

Up to eight coprocessors may reside in a system simultaneously; multiple coprocessors of the same type
are also allowed.

•

Systems may use software emulation of the MC68881
without reassembling or relinking user software.

•

Eight 80-bit floating-point data registers (FPO-FP7).
These registers are analogous to the integer data registers (00-07) and are completely general purpose (i.e.,
any instruction may use any register).

•

A 32-bit control register that contains enable bits for
each class of exception trap, and mode bits to set the
user-selectable rounding and precision modes.

•

A 32-bit status register that contains floating-point
condition codes, quotient bits, and exception status
information.

•

A 32-bit instruction address register that contains the
main processor memory address of the last floatingpOint instruction that was executed. This address is
used in exception handling to locate the instruction
that caused the exception.

The connection between the MC68020 and the MC68881
is a simple extension of the M68000 bus interface. The
MC68881 is connected as a coprocoessor to the MC68020,
and the selection of the MC68881 is based upon a chip
select (CS), which is decoded from the MC68020 function
codes and address bus. Figure 7 illustrates the MC68881/
MC68020 configuration.
As shown in Figure 8, the MC68881 is internally divided
into three processing elements; the bus interface unit
(BIU), the execution control unit (ECU), and the microcode control unit (MCU). The BIU communicates with the
MC68020, and the ECU and MCU execute all MC68881
instructions.

*AII references to the MC68020, throughout this technical summary, also apply to the MC68030.

MOTOROLA
4-34

M68000 FAMIL V
REFERENCE

MC68881

79
I

FPO

FPl

FP2

FP3

FP4

FP5

FP6

FP7

FLOATING POINT
DATA REGISTERS

FPCR

CONTROL REGISTER

FPSR

STATUS REGISTER

FPIAR

INSTRUCTION ADDRESS
REGISTER

Figure 1. MCG8881 Programming Model

BSUN

14
SNAN

OPERR

12
OVFL

11
UNFL

10
DZ

INEX2

!NEXI

INEXACT DECIMAL INPUT
INEXACT OPERATION
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
OPERAND ERROR
SIGNALLING NOT A NUMBER
BRANCH/SET ON UNORDERED

Figure 2. Exception Status/Enable Byte

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _

ROUNDING MODE:
00
01
10
11

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

TO NEAREST
TOWARD ZERO
TOWARD MINUS INFINITY
TOWARD PLUS INFINITY

ROUNDING PRECISION:
00 EXTENDED
01 SINGLE
10 DOUBLE
" (UNDEFINED, RESERVEDI

Figure 3. Mode Control Byte

M68000 FAMILY
REFERENCE

MOTOROLA
4-35

III

MC68881

Figure 4. Condition Code Byte

QUOTIENT

' - - - - - - - - - - - - SEVEN LEAST SIGNIFICANT
BITS OF QUOTIENT
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SIGN OF QUOTIENT

Figure 5. Quotient Byte

lOP

OVFL

UNFL

INEX

I
INEXACT
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
INVALID OPERATION

Figure 6. Accrued Exception Byte

ADDRESS
DECODE

MC68881
FLOATING POINT
COPROCESSOR

110

MC68020
PROCESSOR

MEMORY

BUS EXTENSION

Figure 7. Typical Coprocessor Configuration

MOTOROLA
4-36

M68000 FAMILV
REFERENCE

r······················································..································s"iii"r···············.................................................................................................................................................................·····M·c·li""

jJ~

ma)

"00
mo

ClK

::00

mo
2."
n~

CLOCK GENERATOR

BUILT IN SELF TEST
REGISTERS

COPROCESSOR INTERFACE
REGISTER SELECT AND
DSACK CONTROL

AeSEf
CONTROL CIR

c
0
c

«c

~PC

SELECT PLA

MULTIPLEXOR

•. .

1 _ _ _ _...,..-_ _ _---'

RESTORE CIR
en

ffl

a:
c
c

~ROM

SAVE CIR

INSTRUCTION DECODE PLAS

I~
RESPONSE CIR

NROM

en
a:

:::IE

I:L

I
en

...J

INSTRUCTION ADDRESS CIR

VCC~

GND~

o
--i
o
:lJ
f"O
w'
-....Jl>

•

a:
a:
«m

!z
~
en
z
0

w
en

I-

a:
>
a:
~

a..
:::IE

I-

OPERAND CIR

L. . . . ~. . . . . . ~.~.~~~~.~.~.~.~~~~~. ~~~. . . . . . ~. :. .L............_..:..~..: ............!.. !. . . . . . .:~~.~:.:~:.~.~~~:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . . ..
Figure 8. MC68881 Simplified Block Diagram

S
n
0)
00
00
00
~

MC68881

The BIU contains the coprocessor interface registers,
and the 32-bit control, status, and instruction address
registers. In addition to these registers, the register select
and DSACK timing control logic is contained in the BIU.
Finally, the status flags used to monitor the status of
communications with the main processor are contained
in the BIU.
The eight 80-bit floating-point data registers (FPO-FP7)
are located in the ECU. In addition to these registers, the
ECU contains a high-speed 67-bit arithmetic unit used for
both mantissa and exponent calculations, a barrel shifter
that can shift from 1 bit to 67 bits in one machine cycle,
and ROM constants (for use· by the internal algorithms
or user programs).
The MCU contains the clock generator,a two-level microcoded sequencer that controls the ECU, the microcode
ROM, and self-test circuitry. The built-in self-test capabilities of the MC68881 enhance reliability and ease manufacturing requirements; however, these diagnostic
functions are not available to the user.
BUS INTERFACE UNIT

All communications between the MC68020 and the
MC68881 occur via standard M68000 Family bus transfers. The MC68881 is designed to operate on 8-, .16-, or
32-bit data buses.
The MC68881 contains a number of coprocessor interface registers (CIRs) which are addressed in the same
manner as memory by the main processor. The M68000
Family coprocessor interface is implemented via a protocol of reading and writing to these registers by the main
processor. The MC68020 implements this general purpose coprocessor interface protocol in hardware and microcode.
When the MC68020 detects a typical MC68881 instruction, the MC68020 writes the instruction to the memorymapped command CIR, and reads the response CIR. In
this response, the BIU encodes requests for any additional action required of the MC68020 on behalf of the
MC68881. For example, the response may request that
the MC68020 fetch an operand from the evaluated effective address and transfer the operand to the operand CIR.
Once the MC68020 fulfills the coprocessor request(s), the
MC68020 is free to fetch and execute subsequent insructions.
A key concern in a coprocessor interface that allows
concurrent instrucion execution is synchronization during main processor and coprocessor communication. If
a subsequent instruction is written to the MC68881 before
the ECU has completed execution of the previous instruction, the response instructs the MC68020 to wait. Thus,
the choice of concurrent or nonconcurrent instruction execution is determined on an instruction-by-instruction
basis by the coprocessor.
The only difference between a coprocessor bus transfer
and any other bus transfer is that the MC68020 issues a
function code to indicate the CPU address space during
the cycle (the function codes are generated by the M68000
Family processors to identify eight separate address
spaces). Thus, the memory-mapped coprocessor interface registers do not infringe upon instruction or data
address spaces. The MC68020 places a coprocessor ID
field from the coprocessor instruction onto three of the

MOTOROLA
4-38

upper address lines during coprocessor accesses. This
ID, along with the CPU address space function code, is
decoded to select one of eight coprocessors in the system.
Since the coprocessor interface protocol is based solely
on bus transfers, the protocol is easily emulated by software when the MC68881 is used as a peripheral with any
processor capable of memory-mapped 1/0 over an M68000
style bus. When used as a peripheral processor with the
8-bit MC68008 or the 16-bit MC68000, or MC68010, all
MC68881 instructions are trapped by the main processor
to an exception handler at execution time. Thus, the software emulation of the coprocessor interface protocol can
be totally transparent to the user. The system can be
quickly upgraded by replacing the main processor with
an MC68020 without changes to the user software.
Since the bus is asynchronous, the MC68881 need not
run at the same clock speed as the main processor. Total
system performance may therefore be customized. For
example, a system requiring very fast floating-point arithmetic with relatively slow integer arithmetic can be designed with an inexpensive main processor and a fast
MC68881.

COPROCESSOR INTERFACE
The M68000 Family coprocessor interface is an integral
part of the MC68881 and MC68020 design, with the interface tasks shared between the two. The interface is
fully compatible with all present and future M68000 Family products. Tasks are partitioned such that the MC68020
does not have to decode coprocessor instructions, and
the MC68881 does not have to duplicate main processor
functions such as effective address evaluation.
This partitioning provides an orthogonal extension of
the instruction set by permitting MC68881 instructions to
utilize all MC68020 addressing modes and to generate
execution time exception traps. Thus, from the programmer's view, the CPU and coprocessor appear to be integrated onto a single chip. While the execution of the
majority of MC68881 instructions may be overlapped with
the execution of MC68020 instructions, concurrency is
completely transparent to the programmer. The MC68020
single-step and program flow (trace) modes are fully supported by the MC68881 and the M68000 Family coprocessor interface.
While the M68000 Family coprocessor interface permits coprocessors to be bus masters, the MC68881 is
never a bus master. The MC68881 requests that the
MC68020 fetch all operands and store all results. In this
manner, the MC68020 32-bit data bus provides high speed
transfer of floating-point operands and results while simplifying the design of the MC68881.
Since the coprocessor interface is based solely upon
bus cycles and the MC68881 is never a bus master, the
MC68881 can be placed on either the logical or physical
side of the system memory management unit. This provides a great deal of flexibility in the system design.
The virtual machine architecture of the MC68020 is supported by the coprocessor interface and the MC68881
through the FSAVE and FRESTORE instructions. If the
MC68020 detects a page fault andlor task time out, the
MC68020 can force the MC68881 to stop whatever operation is in process at any time (even in the middle of

M68000 FAMILY

REFERENCE

"MC68881

the execution of an instruction) and save the MC68881
internal state in memory.
The size of the saved internal state of the MC68881 is
dependent upon what the ECU is doing at the time that
the FSAVE is executed. If the MC68881 is in the reset
state when the FSAVE instruction is received, only one
word of state is transferred to memory, which may be
examined by the operating system to determine that the
coprocessor programmer's model is empty. If the coprocessor is idle when the save instruction is received, only
a few words of internal state are transferred to memory.
If the MC68881 is in the middle of executing an instruction, it may be necessary to save the entire internal state
of the machine. Instructions that can complete execution
in less time than it would take to save the larger state in
mid-instruction are allowed to complete execution and
then save the idle state. Thus the size of the saved internal
state is kept to a minimum. The ability to utilize several
internal state sizes greatly reduces the average context
switching time.
The FRESTORE instruction permits reloading of an internal state that was saved earlier, and continues any
operation that was previously suspended. Restoring of
the reset internal state functions just like a hardware reset
to the MC68881 in that defaults are re-established.

OPERAND DATA FORMATS
The MC68881 supports the following data formats:
Byte Integer (B)
Word Integer (W)
Long Word Integer(L)
Single Precision Real (S)
Double Precision Real(D)
Extended Precision Real (X)
Packed Decimal String Real(P)
The capital letters contained in parenthesis denote suffixes added to instructions in the assembly language
source to specify the data format to be ·used.
INTEGER DATA FORMATS
The three integer data formats (byte, word, and long
word) are the standard data formats supported in the
M68000 Family architecture. Whenever an integer is used
in a floating-point operation; the integer is automatically
converted by the MC68881 to an extended precision floating-point operation, the integer is automatically converted by the MC68881 to an extended precision floatingpoint number before being used. For example, to add an
integer constant of five to the number contained in floating-point data register 3 (FP3), the following instruction
can be used:
.
FADD.W #5,FP3
(The Motorola assembler syntax "#" is used to
is used to denote immediate addressing.)
The ability to effectively use integers in floating-point
operaions saves user memory since an integer representation of a number, if respresentable, is usually smaller
than the equivalent floating-point representation.

M68000 FAMILY
REFERENCE

FLOATING-POINT DATA FORAMTS
The floating-point data formats single precision (32bits) and double precision (64-bits) are as defined by the
IEEE standard. These are the main floating-point formats
and should be used for most calculations involving real
numbers. Table 1 lists the exponent and mantissa size
for single, double, and extended precision. The exponent
is biased, and the mantissa is in sign and magnitude
form. Since single and double precision require normalized numbers, the most significant bit of the mantissa is
implied as one and is not included, thus giving one extra
bit of precision.
Table 1. Exponent and Mantissa Sizes
Data
Format

Exponent
Bits

Mantissa
Bits

Single

23(+1)

127

Double

52(+1)

1023

Extended

16383

Bias

The extended precision data format is also in conformance with the IEEE standard, but the standard does not
specify this format to the bit level as it does for single
and double precision. The memory format on the MC68881
consists of 96 bits (three long words). Only 80 bits are
actually used, the other 16 bits are for future expandability and for long-word alignment of floating-point data
structu res. Extended format has a 15-bit exponent, a 64bit mantissa, and a 1-bit mantissa sign.
Extended precision numbers are intended for use as
temporary variables, intermediate values, or in places
where extra precision is needed. For example, a compiler
might select extended precision arithmetic for evaluation
of the right side of an equation with mixed sized data
and then convert the answer to the data type on the left
side of the equation. It is anticipated that extended precision data will not be stored in large arrays, due to the
amount of memory required by each number.
PACKED DECIMAL STRING REAL DATA FORMAT
The packed decimal data format allows packed BCD
strings to be input to and output from the MC68881. The
strings consist of a 3-digit base 10 exponent and a 17digit base 10 mantissa. Both the exponent and mantissa
have a separate sign bit. All digits are packed BCD, such
that an entire string fits in 96 bits (three long words). As
isthe case with all data formats, when packed BCD strings
are input to the MC68881, the strings are automatically
converted to extended precision real values. This allows
packed BCD numbers to be used as inputs to any operation. For example:
FADD.P #-6.023E + 24,FP5
BCD numbers can be output from the MC68881 in a format readily used for printing by a program generated by
a high-level language compiler. For example:
FMOVE.P FP3,BUFFER{#-5}
instructs'the MC68881 to convert the floating-point data
register 3 (FP3) contents into a packed BCD string with
five digits to the right of the decimal point (FORTRAN F
format).

MOTOROLA
4-39

III

MC68881

[(TEMP_PTR,A7)),FP3
#1.23E25,FPO

FADD.X
FADD.P

DATA FORMAT SUMMARY
All data formats described above are supported orthogonally by ali arithmetic and transcendental operations, and by all appropriate MC68020 addressing modes.
For example, all of the fC?lIowing are legal instructions:
, FADD.B
#3,FPO'
,
,
FADD.W
D2,FP3
, FADD.L
BIGINT,FP7
FADD.S
#3.14159,FP5
' (SP) + ,FP6
FADD.D

On-chip calculations are performed to extended precision
format, and the eight floating point data registers always
contain exetended precision values. All data used in an
operation is converted to extended precision by the
MC68881 before the specific operation is performed, and
all results are in extended precision. This en'sures maximum accuracy without sacrificing performance.
"Refer to Figure 9 for a summary of the memory formats
for the seven data fo~mats support'ed by the MC68881.

B
7

0
BYTE INTEGER

15
, 16 BITS

'I WORD INTEGER

32 BITS

22
23-BIT
FRACTION

I,
'J

LONG INTEGER

SINGLE REAL

51
52-BIT' ,
FRACTION

DOUBLE REAL
I'

SIGN OF FRACTION

64-BIT

MANTISSA

EXTENDED REAL

IMPLICIT BINARY POINT

17-DIGIT
MANTISSA

PACKED DECIMAL REAL

IMPLICIT DECIMAL POINT
2 BITS. USED ONLY FOR:!:: INFINITY OR NANS. ZERO OTHERWISE
SIGN OF EXPONENT
SIGN OF MANTISSA
, . *UNLESS
A BINARY-TO-DECIMAL CONVERSION OVERFlOW OCCURS
,
r,(

Figure 9. MC68881 Data Format Summary

MOTOROLA
4-40

M68000 FAMILY

REFERENCE

MC68881

INSTRUCTION SET
The MC68881 instruction set is organized into six major
classes:
"
1. Moves between the MC68881 and memory or the
MC68020 (in and out),

an MC68020 data register. The result is always stored in
a floating-point data register. For example, the syntax for
square root is:
(ea),FPn or,
FPm,FPn or,
FPn

FSORT.(fmt)
FSORT.X
FSQRT.X

(ea),FPn
Move to MC68881
FMOVE.(fmt)
FMOVE.(fmt)
FPm,(ea)
Move from MC68881
FMOVE.X
FPm,FPn
Move within MC68881
where:
(ea) is an MC68020 effective address operand and (fmt)
is the data format size. FPm and FPn are floating-point
data registers.

The MC68881 monadic operations available are as follows:
Absolute Value
FABS
Arc Cosine
FACOS
Arc Sine
FASIN
Arc Tangent
FATAN
Hyperbolic Arc Tangent
FATANH
FCOS
Cosine
Hyperbolic Cosine
FCOSH
e to the x Power
FETOX
e to the x Power -1
FETOXM1
Get Exponent
FGETEXP
FGETMAN
Get Mantissa
FINT
Integer Part
Integer Part (Truncated)
FINTRZ
Log Base 10
FLOG10
FLOG2
Log Base 2
Log"Base e
FLOGN
Log Base e of(x + 1)
FLOGNP1
Negate
FNEG
FSIN
Sine
Simultaneous Sine and Cosine
FSINCOS
Hyperbolic Sine
FSINH
Square Root
FSORT
Tangent
FTAN
Hyperbolic Tangent
FTANH
10 to the x Power
FTENTOX
FTST
Test
FlWOTOX
2 to the x Power

MOVE MULTIPLES

DYADIC OPERATIONS

The floating-point move multiple instructions on the
MC68881 are much like the integer counterparts on the
M68000 Family processors. Any set of the floating-point
registers FPO through FP7 can be moved to or from memory with one instruction. These registers are always moved
as 96-bit extended data with no conversion (hence no
possibility of conversion errors). Some move multiple
examples are as follows:

Dyadic operations have two input operands. The first
input operand comes from a floating-point data register,
memory, or an MC68020 data register. The second input
operand comes from a floating-point data register. The
destination is the same floating-point data register used
for the second input. For example, the" syntax for add is:

2. Move multiple registers (in and out),
3. Monadic operations,
4. Dyadic operations,
5. Branch, set, or trap conditionally, and
6. Miscellaneous.
MOVES
All moves from memory (or from an MC68020 data
register) to the MC68881, cause data conversion from the
source data format to the internal extended precision
format.
All moves from the MC68881 to m"emory (or to an
MC68020 data register), cause data conversion from the
internal extended precison format to the destination data
format.
Note that data movement instructions perform arithmeic operations, since the result is always rounded to
the precision selected in the FPCR mode contol byte. The
result is rounded using the selected rounding mode, and
is checked for overflow and underflow.
" The syntax for the move is:

FMOVEM
FMOVEM

(ea),FPO-FP3/FP7
FP2/FP4/FP6,(ea)

Move multiples are useful during context switches and
interrupts to save or restore the state of a program. These
moves are also useful at the start and end of a procedure
to save and restore the calling routine's register set. In
order to reduce procedure call overhead, the list of registers to be saved or restored can be contained in a data
register. This allows run-time optimization by allowing a
called routine to save as few registers as possibre. Note
that no rounding or overflow/underflow checking is performed by these operations.

FADD.(fmt)
FADD.X

(ea),FPn or,
FPm,FPn

The MC68881 dyadic operations available are as follows:
FADD
FCMP
FDIV
FMOD
FMUL
FREM
FSCALE
FSGLDIV
FSGLMUL
FSUB

Add
Compare
Divide
Modulo Remainder
Multiply
"IEEE Remainder
Scale Exponent
Single Precision Divide
Single Precision Multiply
Subtract

MONADIC OPERATIONS

BRANCH, SET, AND TRAP-ON CONDITION

Monadic operations have one operand. This operand
may be in a floating-point data register, memory, or in

The floating-point branch, set, and trap-on condition
instructions implemented by the MC68881 are similar to

M68000 FAMILY
REFERENCE

MOTOROLA
4-41

III

MC68881

the equivalent integer instructions of the M68000 Family
processors, except that more conditions exist due to the
special values in IEEE floating-point arithmetic. When a
conditional instruction is executed, the MC68881 performs the necessary condition checking and tells the
MC68020 whether the condition is true or false; the
MC68020 then takes the appropriate action. Since the
MC68881 and MC68020 are closely coupled, the floatingpoint branch operations executed by the pair are very
fast.
The MC68881 conditional operations are:
FBcc
FDBcc
FScc
FTRAPcc

Branch
Decrement and Branch
Set Byte According to Condition
Trap-on Condition
(with an Optional Parameter)

where:
cc is one of the 32 floating-point conditional test specifiers as shown in Table 2.

Table 2. Floating-Point Conditional
Test Specifiers
Mnemonic

Definition
NOTE

The following conditional tests do not set the BSUN bit
in the status register exception byte under any circumstances.
F
EO
OGT
OGE
OLT
OLE
OGL
OR
UN
UEO
UGT
UGE
ULT
ULE
NE
T

False
Equal
Ordered Greater Than
Ordered Greater Than or Equal
Ordered Less Than
Ordered Less Than or Equal
Ordered Greater or Less Than
Ordered
Unordered
Unordered or Equal
Unordered or Greater Than
Unordered or Greater or Equal
Unordered or Less Than
Unordered or Less or Equal
Not Equal
True
NOTE

The following conditional tests set the BSUN bit in the
status register exception byte if the NAN condition code
bit is set when a conditional instruction is executed.
SF
SEO
GT
GE
LT
LE
GL
GLE
NGLE
NGL
NLE
NLT
NGE
NGT
SNE
ST

MOTOROLA
4-42

Signaling False
Signaling Equal
Greater Than
Greater Than or Equal
Less Than
Less Than or Equal
Greater or Less Than
Greater Less or Equal
Not (Greater, Less or Equal)
Not (Greater or Less)
Not (Less or Equal)
Not (Less Than)
Not (Greater or Equal)
Not (Greater Than)
Signaling Not Equal
Signaling True

MISCELLANEOUS INSTRUCTIONS
Miscellaneous instructions include moves toand from
the status, control, and instruction address registers. Also
included are the virtual memory/machine FSAVE and
FRESTORE instructions that save and restore the internal
state of the MC68881.
FMOVE
FMOVE

(ea),FPcr
FPcr,(ea)

FSAVE
FRESTORE

(ea)
(ea)

Move to Control Register(s)
Move from Control
Register(s)
Virtual Machine State Save
Virtual Machine State
Restore

ADDRESSING MODES
The MC68881 does not perform address calculations.
This satifies the criterion that an M68000 Family coprocessor must not depend on certain features or capabilities
that mayor may not be implemented by a given main
processor. Thus, when the MC68881 instructs the
MC68020 to transfer an operand via the coprocessor interface, the MC68020 performs the addessing mode calculations requested in the instruction. In this case, the
instruction is encoded specifically for the MC68020, and
the execution of the MC68881 is not dependent on that
encoding, but only on the value of the command word
written to the MC68881 by the main processor.
This interface is quite flexible and allows any addressing mode to be used with floating-point instructions. For
the M68000 Family, these addressing modes include immediate, postincrement, predecrement, data or address
register direCt, and the indexed/indirect addressing modes
of the MC68020. Some addressing modes are restricted
for some instructions in keeping with the M68000 Family
architectural definitions (e.g. PC relative addressing is not
allowed for a destination operand).
The orthogonal instruction set of the MC68881, along
with the flexible branches and addressing modes, allows
a programmer writing assembly language code, or a
compiler writer generating object or source code for the
MC68020/MC68881 device pair, to think of the MC68881
as though the MC68881 is part of the MC68020. There
are no special restrictions imposed by the coprocessor
interface, and floating-point arithmetic is coded exactly
like integer arithmetic.

TIMING TABLES FOR TYPICAL EXECUTION
This set of tables allows a quick determination of the
typical execution time for any MC68881 instruction when
the MC68020 is used as the main processor. The first table
presented is for effective address caculations performed
by the MC68020. Entries from this table are added to
entries in the other tables, if necessary, to obtain the total
number of clock cycles for an operation. The assumptions
for the following tables are:
•

The main processor is an MC68020 and operates on
the same clock as the MC68881. Instruction prefetches
do not hit in the MC68020 cache (or it is disabled) and
the instruction is aligned such that a prefetch occurs
before the command CIR is written by the MC68020.

M68000 FAMILY
REFERENCE

MC68881

•

A 32-bit memory interface is used, and memory accesses occur with zero wait states. All memory operands, as well as the stack pointers, are long-word
aligned.

•

Accesses to the MC68881 require 3 clock cycles, with
the exception of read accesses to the response and
save CIRs, which require 5 clock cycles.

•

No instruction overlap is utilized, so the coprocessor
interface overhead is 11 clocks. This can be reduced
to 2 clock cycles if optimized code sequences are used,
or may be 11 clock cycles if overlap is attempted and
a synchronization delay is required.

•

Typical operand conversion and calculation times are
used (i.e. input operands are assumed to be normalized numbers in the legal range for a given fuctionl.

•

No exceptions are enabled or occur, and the default
rounding mode and precision of round-to-nearest, extended precision, is used.

EFFECTIVE ADDRESS CALCULATIONS

For any instruction that requires an operand external
to the MC68881, an evaluate effective address and transfer data response primitive is issued by the MC68881
during the dialog for that instruction. The amount of time
that is required for the MC68020 to calculate the effective
address while processing this primiive for each addressing mode, excluding the transfer of the data to the
MC68881, is shown in Table 3.

ARITHMETIC OPERATIONS

The Table 4 gives the typical instruction execution time
for each arithmetic instruction. This group of instructions
includes the majority of the MC68881 operations such as
FADD, FSUB, etc. In addition to the instructions that perform arithmetic calculations as part of their function, the
FCMP, FMOVE and FTST instructions' are also included,

Table 3. Effective Address Calculations Execution Timing
Best Case

Cache Case

Worst Case

Dn or An

Addressing Mode

(An)

(An)+

-(An)

(d 16,An) or (d 16.PC)

(xxx.w)

(xxx).L

#(data)

(da.An.Xn) or (da.PC.Xn)

(d 16.An,Xn) or (d 16.PC.Xn)

(B)

(d 16·B)

(d 32 ·B)

([B).I)

([Bl.l.d 16 )

([B).I.d 32 )

([d 16·B).I)

([d 16·B).I.d 16)

([d 16·Bl.l.d32 )

([d 32 ·Bl.l)

([d 32 ·B).I.d 16 )

([d 32 ·BJ.I.d 32 )

B = Base address; O. An. PC. Xn, An + Xn, PC + Xn. Form does not affect timing.
I = Index; 0 or Xn.
Note that Xn cannot be in B and I at the same time. Scaling and size of Sn does
not affect timing.

M68000 FAMILY

REFERENCE

MOTOROLA
4-43

MC6888.1

Table 4. Arithmetic Operations Execution Timing
Memory Source or Destination Operand Format*

FPm
Source

Integer**

Single**

Double

Extended

FABS

872

FACOS

652

625

644

650

648

1462

Instruction

Packed

FADD

888

FASIN

581

608

600

606

604

1418

FATAN

403

430

422

428

426

1240

FATANH

693

720

712

7i8

716

1530

FCMP

870

FCOS

391

418

410

416

414

1228

FCOSH

607

634

626

632

630

·1444

FDIV

103

132

124

130

128

940

FETOX

497

524

516

522

520

1334

FETOXM1

545

572

564

570

568

1382

FGETEXP

882

FGETMAN

868

FINT

892

FINTRZ

892

FLOGN

525

552

544

550

548

1362

FLOGNP1

571

598

590

596

594

1408

FLOG10

581

608

600

606

604

1418

FLOG2

581

608

600

606

604

1418

FMOD

902

FMOVE to FPn

870

FMOVE to Memory***

100

1996

FMOVECR****

FMUL

100

908

FNEG

872

FREM

902

FSCALE

878

FSGLDIV

906

FSGLMUL

896

391

418

410

416

414

1228

FSIN
FSINCOS

451

478

470

476

474

1288

FSINH

687

714

706

712

710

1524

FSQRT

107

134

126

132

130

944

FSUB

888

FTAN

473

500

492

498

496

1310

FTANH

661

688

680

686

684

1498

FTENTOX

567

594

586

592

590

1404

FTST

870

FTWOTOX

567

594

586

592

590

1404

*Add the appropriate effective address calculation time.
**If the source or destination is an MC68020 data register, subtract 5 or 2 clock cycles, respectively.
***Assume a static K-factor is used if the destination data format is packed decimal. Add 14 clock cycles if a
dynamic K-factor is used,
****The source operand is from the constant ROM rather than a floating-point data register.

MOTOROLA
4-44

M68000 FAMILY
REFERENCE

MC68881

since an implicit conversion is performed by those operations. For memory operands, the timing for the appropriate effective addressing mode must be added to
the numbers in this table to determine the overall instruction execution times.

be included is the calculate effective address time for the
operand to be modified~
FSAVE AND FRESTORE INSTRUCTIONS
The time requred for a context save or restore operation is given in Table 7. The appropriate calculate effective
address times must be added to the values in this table
to obtain the total execution time for these operations.
For the FSAVE instruction, the MC68881 may use the not
ready format code to force the MC68020 to wait while
internal operations are completed in order to reduce the
size of the saved state frame or reach a point where a
save operation can be performed. The idle (minimum)
time occurs if the MC68881 is in the idle phase when the
save CIR is written. A time between the idle (minimum)
, and the idle (maximum) occurs if an instruction is in the
end phase when the save CIR is read. The busy (minimum) time. occurs if the MC68881 is in the initial phase,
or at a save boundary in the middle phase, when the save
CIR is read. Finally, the busy (maximum) time occurs if
the MC68881 has just passed a save boundary in the
middle phase when the save CIR is read.

MOVE CONTROL REGISTER AND MOVE MULTIPLE OPERATIONS
The Table 5 gives the execution times for the FMOVE
FPcr and FMOVEM instructions. The timing for the appropriate effective addressing mode must be added to
the numbers in this table to determine the overall instruction execution times.

CONDITIONAL OPERATIONS
The Table 6 gives the execution times for the MC68881
conditional instructions. Each entry in this table, except
those for the FScc instruction, is complete arid does not
require the addition of values from any other table. For
the FScc instruction, the only additional factor that must

Table 5. Move Control Register and
FMOVEM Operations Execution Timi~g
Operation·
FMOVE

FPcr,Rn
FPcr,(ea)
Rn,FPcr
(ea),FPcr
#(data),FPcr

FMOVEM

FPcr_list,(ea)
(ea),FPcr_list
#(data),FPcr_ list

FMOVEM

FPdr_list,(ea)
(ea),FPdr_list
Dn,(ea)
(ea),Dn

Best Case

Cache Case

29
31
26
31
30

31
33
28
33
30

Worst Case

25+6n
25+6n
24+6n

27+6n
27+6n
25+6n

30+6n
30+6n
29+6n

35+25n
33t23n
49+25n
47+23n

37+25n
35+23n
51 +25n
49+23n

40+25n
38+23n
54+25n
52+23n

34
36 .
31
36
31

*Add the appropriate effective address calculation time.
n is the number of registers transferred.

M6'SOOO FAMILY
REFERENCE

MOTOROLA
4-45

MC68881

Table 6. Conditional Instructions Execution Timing
Comments

Best Case

Cache Case

Worst Case

"FBcc.W

Branch Taken
Branch Not Taken

18
16

20
18

23
19

FBcc.L

Branch Take'n
Branch Not Taken

18
16

20
18

23
21 "

FDBcc

True, Not Taken
False, Not Taken
False, Taken

18
22
18

20
24
20

24
32
26

FNOP

No Operation

FScc

On
(An) + or - (An)*
Memory**

16
18
16

18
22
20

21
25
23

FTRAPcc

Trap Taken
Trap Not Taken

36
16

39
18

47
22

FTRAPcc.W

Trap Taken
Trap Not Taken

38
18

41
20

45
23

FTRAPcc.L

Trap Taken"
Trap Not Taken

40
20

43
22

52
27

Operation

*For condition true; subtract one clock for condition false.
**Add the appropriate effective address calculation time.

Table 7. FSAVE and FRESTORE Instructions Execution Timing
Operation*

State Frame

Best Case

Cache Case

Worst Case

FRESTORE

Null
Idle
Busy

19 "
55
312

21
57
314

22
58
315

FSAVE

Null
Idle (Minimum)
Idle (Maximum)
Busy (Minimum)
Busy (Maximum)

14
50
286
316
552

16
52
218
318
554

18
54
290
320
556

*Add the appropriate effective address calculation time.

FUNCTIONAL SIGNAL DESCRIPTIONS
VCC

This section contains a brief description of the input
and output signals for the MC68881 floating-point coprocessor. The signals are functionally organized into groups
as shown in Figure 10.
NOTE
The terms assertion and negation are used
extensively. This is done to avoid confusion
when describing "active-low" and "activehigh" signals. The term assert or assertion is
used to indicate that a signal is active or true,
independent of whether that level is represented by a high or low voltage. The term
negate or negation is used to indicate that a
signal is inactive or false.

MOTOROLA

4-46

GNO

-..

~
~

V'
MCG8881
FLOATING-POINT
COPROCESSOR

AO-A4

00-031

AS
RIW
~

ClK

SIZE

RESET

OSACKO

SENSE

OSACKl

Figure 10. MC68881 Input/Output Signals

M68000 FAMILY
REFERENCE

MC68881

Table 8. Coprocessor Interface Register Selection
A4·AO

Offset

Width

Type

OOOOx

$00

Read

Response

0001x

$02

Write

Control

0010x

$04

Read

Save

0011x

$06

Restore

0100x

$08

0101x

$OA

0110x

$OC

0111x

$OE

100xx

$10

1010x

$14

1011x

Write

(Reserved)
Command
(Reserved)

Write

Condition

Operand

Read

$16

110xx

$18

Read

Instruction Address

111xx

$1C

Operand Address

(Reserved)

ADDRESS BUS (AO through A4)

SIZE (SIZE)

These active·high address line inputs are used by the
main processor to select the coprocessor interface reg·
ister locations located in the CPU address space. These
lines control the register selection as listed in Table 8.
When the MC68881 is configured to operate over an 8·
bit data bus, the AO pin is used as an address signal for
byte acceses of the coprocessor interface registers. When
the MC68881 is configured to operate over a 16· or 32bit system data bus, both the AO and SIZE pins are strapped
high and/or low as listed in Table 9.

This active·low input signal is used in conjunction with
the AO pin to configure the MC68881 for operation over
an 8·, 16·, or 32·bit system data bus. When the MC68881
is configured to operate over a 16- or 32·bit system data
bus, both the SIZE and AO pins are strapped high and/or
low as listed in Table 9.

Table 9. System Data Bus Size Configuration
AO

SIZE

Data Bus

Low

8·Bit

Low

High

16·Bit

High

32·Bit

DATA BUS (DO through 031)
This 32·bit, bidirectional, three·state bus serves as the
general purpose data path between the MC68020 and the
MC68881. Regardless of whether the MC68881 is operated as a coprocessor or a peripheral processor, all inter·
processor transfers of instruction information, opera'nd
data, status information, and requests for service occur
as standard M68000 bus cycles.
The MC68881 will operate over an 8·, 16·, or 32·bit
system data bus. Depending upon the system data bus
configuration, both the AO and SIZE pins are configured
specifically for the applicable bus configuration. (Refer to
ADDRESS BUS (AO through A4) and SIZE (SIZE) for further details.)

M68000 FAMILY

REFERENCE

ADDRESS STROBE (AS)
This active·low input signal indicates that there is a
valid address on the address bus, and both the chip select
(CS) and read/write (RIW) signal lines are valid.

CHIP SELECT (CS)
This active·low input signal enables the main processor
access to the MC68881 coprocessor interface registers.
When operating the MC68881 as a peripheral processor,
the chip select decode is system dependent (i.e., like the
chip select on any peripheral). The CS signal must be
valid (either asserted or negated) when AS is asserted.
Refer to CHIP SELECT TIMING for further discussion of
timing restrictions for this signal.
READIWRITE (R/W)
This input signal indicates the direction of a bus trans·
action (read/write) by the main processor. A logic high
(1) indicates a read from the MC68881, and a logic low
(0) indicates a write to the MC68881. The RIW signal must
be valid when AS is asserted.
DATA STROBE (OS)
This active·low input signal indicates that there is valid
data on the data bus during a write bus cycle.

MOTOROLA

4-47

MC68881

DATA TRANSFER AND SIZE ACKNOWLEDGE
(DSACKO, DSACK1)
These active-low, three-state output signals indicate
the completion of a bus cycle to the main processor. The
MC68881 asserts both the DSACKO and DSACK1 signals
upon assertion of CS.
If the bus cycle is a main processor read, the MC68881
asserts DSACKO and DSACK1 signals to indicate that the
information on the data bus is vaEd. (Both DSACK signals
may be asserted in advance ofthe valid data being placed
on the bus.) If the bus cycle is a main processor write to
the MC68881, DSACKO and DSACK1 are used to acknowledge acceptance of the data by the MC68881.
The MC68881 also uses DSACKO and DSACK1 signals
to dynamically indicate to the MC68020 the "port" size
(system data bus width) on a cycle-by-cycle basis. Depending upon which of the two DSACKpins are asserted
in a given bus cycle, the MC68020 assumes data has been
transferred to/from an 8-, 16-, or 32-bitwide data port.
Table 10 lists the DSACK assertions that are used by the
MC68881 for the various bus cycles over the various bus
cycles over the various system data bus configurations.
Table 13 indicates that all accesses over a 32-bit bus
where A4 equals zero are to 16-bit registers. The MC68881
implements all 16-bit coprocessor interface registers on
data lines D16-D31 (to eliminate the need for on-chip
multiplexers); however, the MC68020 expects 16-bit registers that are located. in a 32-bit port at odd word addresses (A 1 = 1) to' be implemented on data lines DO-D15.
For accesses to these registers when configured for 32bit bus operation, the MC68881 generates DSACK signals
as listed in Table 10 to inform the MC68020 of valid data
on D16-D31 instead of DO-015.
An external holding resistor is required to maintain
both DSACKO and DSACK1 high between bus cycles. In
order to reduce the signal rise time, the· DSACKO and
DSACK1 lines are actively pulled up (negated) by the
MC6S881 following the rising edge of AS or DS, and both
DSACK lines are then three-stated (placed in the highimpedance state) to avoid interference with the next bus
cycle.
RESET (RESET)
This active-low input signal causes the MC68881 to
initialize the floating~point data registers to non-signaling
not-a-~umbers (NANs) and clears the floating-point control, status, and instruction address registers.
When performing a power-up reset, external circuitry
should keep the RESET line asserted for a minimum of

four clock cycles after VCC is within toleran<;.e. This assures correct initialization of the MC68881 when power
is applied. For compatibility with all. M68000 Family devices, 100 milliseconds should be used as the minimum.
When performing a reset of the MC68881 after V CC has
been within tolerance for more than the initial power-up
time, the RESET line must have an asserted pulse width
which is greater than two clock cycles. For compatability
with all M68000 Family devices, 10 clock cycles should
be used as the minimum.
CLOCK (ClK)
The MC68881 clock input is a nL-compatable signal
that is internally buffered for development of the internal
clock signals. The clock input should be a constant frequency square wave with no stretching or shaping techniques required. The clock should not be gated off at any
time and must conform to minimum and maximum period and pulse width times.
SENSE DEVICE (SENSE)
This pin maybe used optionally as an additional GND
pin, or as an indicator to external hardware that the
MC68881 is present in the system. This signal is internally
connected to the GND of the die, but it is not necessary
to connect it to the external ground for correct device
operation. If a pullup resistor (which should be larger than
10 kohm) is connected to this pin location~ external hardware may sense the presence of the MC68881 in a system.
POWER (VCC and GND)
These pins provide the supply voltage and system reference level for the internal circuitry of the MC68881. Care
should be taken to reduce the noise level on these pins
with appropriate capacitive decoupling.
NO CONNECT (NC)
One pin of the MC68881 package is designated as a no
connect (NC). This pin position is reserved for future use
by Motorola, and should not be used for signal routing
or connected to VCC or GND.
SIGNAL SUMMARY
Table 11 provides a summary of all the Me68881 signals described in this section.

Table 10. DSACK Assertions
Data Bus

DSACK1

DSACKO

32-Bit

Valid Oata on 031-00

Comments.

32-Bit

Valid Oata on 031-016

16-Bit

Valid Oata on 031-016 or 015~00

8-Bit

All

MOTOROLA
4-48

Valid Oata on 031-024, 023-016, 015-08, or 07-00

lrisert Wait States in Current Bus Cycle

M68000 FAMILY

REFERENCE

MeS8881

Table 11. Signal Summary
Mnemonic

Input/Output

Active State

Address Bus

AO-A4

Input

High

Data Bus

00-013

Input/Output

High

Yes

SIZE

Input

low

Input

low

Chip Select

Input

low

ReadtWrite

Input

High/low

Data Strobe

Input

low

. Yes

Signal Name

Size
Address Strobe

OSACKO, OSACKI

Output

low

Reset

RESET

Input

low

Clock

elK

Input

Data Transfer and Size Acknowledge

Sense Device

SENSE

Input/Output

Power Input

VCC

Input

Ground

GNO

Input

INTERFACING METHODS
MC68881/MC68020 INTERFACING
The following paragraphs describe how to connect the
MC68881 to an MC68020 for coprocessor operation via
an 8-, 16-, or 32-bit data bus.

Three State

low

the eight most significant data pins (024-031) when the
MC68881 is configured to operate over an 8-bit data bus
(i.e., connect 00 to 08, 016 and 024; 01 to 09, 017, and
025; ... and 07 to 015, 023 and 031). The OSACK pins
of the two devices are directy connected, although it is
not necessary to connect the OSACK1 pin since the
MC68881 never asserts it in this configuration.

32-Bit Data Bus Coprocessor Connection
FCO-FC2 ~r-CHIP
A20-A31 f-SELECT
~
A16-A19 ~ OECOOE

Figure 11 illustrates the coprocessor interface connection of an MC68881 to an MC68020 via a 32-bit data bus.
The MC68881 is configured to operate over a 32-bit data
bus when both the AO and SIZE pins are connected to
VCC'

A13-A15

'Figure 12 illustrates the coprocessor interface connec'tion of an MC68881 to an MC68020 via a 16-bit data bus.
The MC68881 is configured to operate over a 16-bit data
bus when the SIZE pin. is connected to VCC' and the AO
pin is connected to GNO. The sixteen least significant
data pins (00-015) must be connected to the sixteen most
significant data pins (016-031) when the MC68881 is configured to operate over a 16-bit data bus' (i.e., connect 00
to 016, 01 to 017, ... and 015 to 031). The OSACK pins
of the two devices are directly connected, although it is
not necessary to connect the OSACKO pin since the
MC68881 never asserts it in this configuration.
8-Bit Data Bus Coprocessor Connection
Figure 13 illustrates the connection of an MC68881 to
an MC68020 as a coprocessor over an 8-bit data bus. The
MC68881 is configured to operate over an 8-bit data bus
when the SIZE pin is connected to GNO. The twenty four
least significant data pins (00-023) must be connected to

M68000 FAMILY
REFERENCE

~L...--

A5-A12 ~
Al-A4

16-Bit Data Bus Coprocessor Connection

AO t-0
N
0

AS
OS

:::E

Vcc-'

Vcc~ AO
_

... AS
OS

00
00
00

:::E

RiW
~

...

....

024-031
016-023

08-015

00-07

OSACKO
OSACKI

SIZE
Al-A4

RiW
024-031
016-023

MAIN PROCESSOR
CLOCK

OSACKO
OSACKI

COPROCESSOR
CLOCK

Figure 11. 32-Bit Data Bus Coprocessor Connection

MOTOROLA

4-49

MC68881

MC68881·MC68000/MC68008/MC68010 INTERFACING
FCD-FC2
A20-A31

The following paragraphs describe how to connect the
MC68881 to an MC68000, MC68008, or MC68010 proces·
sor for operation as a peripheral via an 8- or 16-bit data
bus.

A16-A19
A13-A15

0
N

'-'

::E

A5-A12

SIZE

16·Bit Data Bus Peripheral Processor Connection

Al-A4

Figure 14 illustrates the connection of an MC68881 to
an MC68000 or MC68010 as a peripheral processor over
a 16-bit data bus. The MC68881 is configured to operate
over a 16-bit data bus when the SIZE pin is connected to
VCC' and the AO pin is connected to GNO. The sixteen
least significant data pins (00-015) must be connected to
the sixteen most significant data pins (016-031) when
the MC68881 is configured to operate over a 16-bit data
bus (i.e., connect 00 to 016, 01 to 017, ... and 015 to
031). The OSACK1 pin of the MC68881 is connected to
the OTACK pin of the main processor, and the DSACKO
pin is not used.
When connected as a peripheral processor, the MC68881
chip select (CS) decode is system dependent. If the
MC68000 is used as the main processor, the MC68881 CS
must be decoded in the supervisor or user data spaces.
However, if the MC68010 is used for the main processor,
the MOVES instruction may be used to emulate any CPU
space access that the MC68020 generates for coprocessor
communications. Thus, the CS decode logic for such systems may be the same as in an MC68020 system, such
that the MC68881 will not use any part of the data address
spaces.

AS
OS

024-031
016-023

co
co
co

<.0

'-'

::E

024-031
016-023
08-015
00-07

- - ------MAIN PROCESSOR
CLOCK

OSACKO
OSACKI

COPROCESSOR
CLOCK

Figure 12_ 16·Bit Data Bus Coprocessor Connection

FCO-FC2

'-'
::E

A5-A12

SIZE

Al-A4

AS
OS

Al-A4

::2;

co
co
co

'-'

A20-A23 OR A31
A16-A19
A13-A15
A5-A12

co
co
co

<.0

'-'

::E

~.
'-'

::E

<.0

'-'

::2;

UOS
LOS
Rm
024-031

024-031

016-023

08-015

00-07

----------MAIN PROCESSOR
CLOCK

OSACKD
OSACKI

COPROCESSOR
CLOCK

Figure 13. 8·Bit Data Bus Coprocessor Connection

MOTOROLA
4·50

OlACK

MAIN PROCESSOR
CLOCK

OSACKO
OSACKI

COPROCESSOR
CLOCK

Figure 14. 16·Bit Data Bus Peripheral
Processor Connection

M68000 FAMILY

REFERENCE

MC68881

8-Bit Data Bus Peripheral Processor Connection
Figure 15 illustrates the connection of an MC68881 to
an MC68008 as a peripheral processor over an 8-bit data
bus. The MC68881 is configured to operate over an 8-bit
data bus when the SIZE pin is connected to GNO. The
eight least significant data pins (00-07) must be connected to the twenty four most significant data pins (08031) when the MC68881 is configured to operate over an

FCO-FC2
A16-A19
A13-A15
A5-A12

- ....

.--.
r--.
-~

8-bit data bus (Le. connect 00 to 08, 016, and 024; 01
to 09, 017, and 025; ... and 07 to 015, 023, and 031).
The OSACKO pin of the MC68881 is connected to the
OTACK pin of the MC68008, and the OSACK1 pin is not
used.
When connected as a peripheral processor, the MC68881
chip select (CS) decode is system dependent, and the CS
must be decoded in the supervisor or user data spaces.

CHIP.
SELECT
OECOOE
(SYSTEM
OEPENOENT)

GNO--' SIZE
... A1-A4

A1-A4
AO
00
0
0
00
.~

AO
00
00
00
0
0'>--1

o
::0
o
~

CLOCK GENERATOR

BUILT IN SELF TEST
REGISTERS

COPROCESSOR INTERFACE
REGISTER SELECT AND
DSACK CONTROL

RESET
CONTROL CIR
)lPC
MULTIPLEXOR

)lPC SELECT PLA
RESTORE CIR

-----r------I

L.;I

SAVECIR
J.LROM

RESPONSE CIR

INSTRUCTION DECODE PLAS

1!1
NROM

en
a:
w
en

I-

<<"
en
< en
o ~

I-

I·········

::E

I-

:c
en

o
a:

~
en
z

I-

ti:

...J

iI:

D..

a:
a:

III

a:
~

ti:
~

::E
w

I-

s:en

:l:I~
mO
"nO

m"T1
:l:I»
ms:

~r=
m<

VCC~
GND~

I M·. . .· . .· . . ·. OP·ERANO..ciR"···......·........·)
i........................

• ,

FPCR, FPSR, AND FPIAR

u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •••••••••••••••••••••••.•••••••• u •••••••••••• •••••••• . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .;

Figure 8. MC68882 Simplified Block Diagram

00
00
00
N

MC68882

operands and results while simplifying the design of the
MC68882.
Since the coprocessor interface is based solely upon
bus cycles (to and from CPU space) and the MC68882 is
never a bus master, the MC68882 can be placed on either
the logical or physical side of the system memory management unit in an MC68020-based system. Since the
memory management unit of the MC68030 is on-chip,
the MC68882 is always on the physical side of the memory management qnit in an MC68030 system.
The virtual machine architecture of the MC68020 or
MC68030 is supported by the coprocessor interface and
the MC68882 through the FSAVE and FRESTORE instructions. If the MC68020 or MC68030 detects a page fault
and/or a task time out, the MC68020 or MC68030 can force
the MC68882 to stop whatever operation is in progress
at any time and save the MC68882 internal state in memory. During the execution of a floating-point instruction,
the MC68882 can stop at predetermined points as well
as at the completion of the instruction.
The size of the saved internal state of the MC68882 is
dependent upon the state of the APU at the time the
FSAVE is executed. If the MC68882 is in the reset state
when the FSAVE instruction is received, only one word
of state is transferred to memory, which may be examined by the operating system to determine that the coprocessor programmer's model is empty. If the
coprocessor is in the idle state when the save instruction
is received, only a few words of internal state are transferred to memory. If executing an instruction in the busy
state, it may be necessary to save the entire internal state
of the machine. Instructions completing execution in less
time than it takes to save the larger state in mid-instruction are allowed to complete execution and then save the
idle state. Thus, the size of the saved internal state is kept
to a minimum. The ability to utilize several internal state
sizes greatly reduces the average context switching time.
The FRESTORE instruction permits reloading of an internal state that was saved earlier and continues any operation that was previously suspended. An FRESTORE of
the null state frame re-establishes default register values,
a function identical to the MC68882 hardware reset.

MC68882 PERFORMANCE ENHANCEMENTS
The high performance of the MC68882 is the result of
the MC68882's abilty to execute multiple floating-point
instructions concurrently. The direct result of concurrency is to utilize the Arithmetic Processing Unit (APU)
more efficiently by decreasing its idle time.
When the MC68882 receives an instruction, the BIU,
along with the CU, can initiate the instruction, fetch the
necessary operands, and convert them· to the internal
extended format even though the ApU is busy complet~
ing execution of a previous instruction. Although the
MC68881 can only instruct the main processor to wait if
the APU is busy, the MC68882 CU can proceed with the
next instruction. When the APU is finally ready to perform
the calculation, it can do so immediately without incurring delay due to data movement and preparation functions.
Another factor in obtaining increased performance in
the MC68882 is the optimized FMOVE instructions for

M68000 FAMILY
REFERENCE

binary real data formats. These FMOVE instructions execute twice as fast as the corresponding FMOVE instructions of the MC68881. The FMOVE instructions are also
potentially fully concurrent and, therefore, can be completely executed during the execution of a previous instruction.
The MC68882 also has a more optimized coprocessor
interface than the MC68881. If an arithmetic instruction
has data formats of Single, Double or Extended, the dialogs are designed to increase the potential overlap with
subsequent instructions. This overlap can significantly
decrease the effective instruction execution time.

OPERAND DATA FORMATS
The MC68882 supports the following data formats:
Byte Integer (B)
Word Integer (W)
Long Word Integer IL)
Single Precision Real (S)
Double Precision Real (D)
Extended Precision Real (X)
Packed Decimal String Real (P) .
The capital letters contained in parentheses denote suffixes added to instructions in the assembly language
source specifying the data format to be used.

INTEGER DATA FORMATS
The three integer data formats (byte, word, and long
word) are the standard twos complement data formats
supported in the M68000 Family architecture. Whenever
an integer is used in a floating-point operation, the integer is. automatically converted by the MC68882 to an
extended precision floating-point number before being
used. For example, to add an integer constant of five to
the number contained in floating-point data register 3
(FP3), the following instruction can be used:
FADO.w #5,FP3
(The Motorola assembler syntax "#" is used to
denote immediate addressing.)
The ability to effectively use integers in floating-point
operations saves user memory since an integer representation of a number, if representable, is usually smaller
than the equivalent floating-point representation.

FLOATING-POINT DATA FORMATS
The floating-point data formats, single precision (32bits) and double precision (64-bits), are defined by the
IEEE standard. These data formats are the main floatingpoint formats and should be 'used for most calculations
involving real numbers. Table 1 lists the exponent and
mantissa size for single, double, and extended precision.
The exponent is biased, and the mantissa is in sign and
magnitude form. Since single and double precision require normalized numbers, the most-significant bit of the
mantissa is implied as a one and is not included, thus
giving one extra bit of precision.
The extended precision data format is also in conformance with the IEEE standard, but the standard does not
specify this format to the bit level whereas it does for

MOTOROLA
4-67

MC68882

Table 1. Exponent and Mantissa Sizes
Data
Format

Exponent
Bits'

Mantissa
Bits

Single

23(+1)

;27

Double

52(+1)

1023

Extended

16383

Bias

single and double precision. The memory format on the
MC68882 consists of 96 bits (three long words). Only 80
bits are actually used; the other 16 bits are for future
expandability and for long-word alignment of floatingpoint data structures. Extended format has a 15-bit exponent, a 64~bit mantissa, and a 1-bit mantissa sign.
Extended precision numbers are intended for use as
temporary variables, intermediate values, or in areas
where extra precision is needed. For example, a compiler
might select extended precision arithmetic for evaluation
of the right side of an equation with mixed sized data
and then convert the answer to the data type on the left
side of the equation. It is anticipated that extended precision data will not be stored in large arrays due to the
amount of memory required by each value.

Most on-chip calculations are performed in the extended precision format, and the eight floating'~point data
registers always contain extended precision values. All
operands used are converted to extended precision by
the MC68882 before a specific operation is performed,
and all results are in extended precision. The use of ex~
tended precision ensures maximum accuracy without
sacrificing performance. Refer to Figure 9 for a summary
of the memory formats for the seven data formats supported by the MC68882.

INSTRUCTION SET
The MC68882 instruction set is organized into six major
classes:
1. Moves between the MC68882 and memory or the
MC68020 or MC68030 (in and' out),
2. Move multiple registers (in and out),
3. Monadic operations,
4. Dyadic operations,
5. Branch, set, or trap conditionally, and
6. Miscellaneous.

PACKED DECIMAL STRING REAL DATA FORMAT

MOVES

The packed decimal data format allows packed BCD
strings to be transferred to and from the MC68882. The
strings consist of a 3-digit base 10 exponent and a 17digit base 10 mantissa. Both the exponent and mantissa
have a separate sign bit. All digits are packed BCD; an
entire string fits in 96 bits (three long words). As is the
case with all data formats when packed BCD strings are
supplied to the MC68882, the' strings are automatically
converted to extended precision real values. This conversion allows packed BCD numbers to be used as inputs
.
to any operation. For example:
FADD.P #-6.023E + 24,FP5
BCD numbers can be output from the MC68882 in a
format readily used for printing by a program generated
by a high-level language compiler. For example:
FMOVE.P FP3,BUFFER{# -:- 5}'
This instruction converts the floating-point data reg~
ister 3 (FP3) contents into a packed BCD string with five
digits to the right of the decimal point (FORTRAN F format).

On all moves from memory (or from an MC68020 .or
MC68030 data reg·ister) to the MC68882, data is converted
from the source data format to the internal extended precision format. On all moves fromthe MC68882 to memory
(or to an MC68020 or MC68030 data register), data is
converted from the internal extended precision format to
the destination data format. Note that data movement
instructions perform arithmetic operations, since the result is always rounded to the precision selected in the
FPCR mode control byte. The result is rounded using the
selected rounding mode and is checked for overflow and
underflow.
The syntax for the move is:
FMOVE. ;FPn Move to MC68882
FMOVE. FPm, Move from MC68882
FPm,FPn
Move within MC68882
FMOVE.X
where:
is an MC68020 or MC68030 effective address
operand .
. is the data. format size.
FPm and FPn are floating-point data registers.

DATA FORMAT SUMMARY

MOVE MULTIPLE REGISTERS

All data formats described above are supported orthogonally by all arithmetic and transcendental operations and by all appropriate MC68020 or MC68030
addressing modes. For example, all of the following are
legal instructions:
.
FADD.B .
#O,FPO
FADD.W
D2,FP3
FADD.L
BIGINT,FP7
FADD.S
#3.14159,FP5
(SP) +,FP6
FADD.D
FADD.X
[(TEMP_PTR,A7)],FP3
FADD.P
#1.23E25,FPO

The floating-point move mUltiple' instructions on the
MC68882 are much like the integer counterparts on the
M68000 Family processors. Any set of the floating-point
registers FPO through FP7 can be moved to or from memory with one instructiori. These registers are always moved
as 96-bit extended data with nO'conversion (hence no
possibility of conversion errors). Some examples of the
move multiple instruction are as follows:
FMOVEM
(ea>,FPO-FP3/FP7
FMOVEM
FP2/FP4/FP6,
The move multiple instructions are useful during context switches and interrupts to save or restore the state

MOTOROLA
4-68

M68000 FAMILY

REFERENCE

MC68882

B
7

0
BYTE INTEGER

15
16 BITS

WORD INTEGER

31
LONG INTEGER

32 BITS

22
23-BIT
FRACTION

\..111,--.. .

_.I~_~~_I.T_IL-

C:
94

FR_~_~B_T:_~N

_______

_ _ _ _ _ _ _..J1 DOUBLE REAL

SIGN OF FRACTION

64-BIT
MANTISSA
SIGN OF

MANTISS~' .....

SINGLE REAL

EXTENDED REAL

LIMPLICIT BINARY POINT

67
17-DIGIT
MANriSSA

. PACKED DECIMAL REAL

IMPLICIT DECIMAL POINT
2 BITS, USED ONLY FOR:!: INFINITY OR NANS, ZERO OTHERWISE
SIGN OF EXPONENT
SIGN OF MANTISSA
*UNLESS A BINARY-TO-DECIMAL CONVERSION OVERFLOW OCCURS

Figure 9. MC68882 Data Format Summary

of a program. These moves are also useful at the start
and end of a procedure to save and restore the 'register
set of the calling ro·utine. In order to reduce procedure
call overhead, the list of registers to be saved or restored
can be contained in a data register thus enabling runtime optimization by allowing a called routine to save as
few registers as possible. Note that no rounding or overflow/underflow checking is performed by these operations.

M68000 FAMILY
'REFERENCE

MONADIC OPERATIONS
Monadic operations have one operand.· This operand
may be in a floating-point data register, memory, or in
an MC68020 or MC68030 data register. The result .is always stored in a floating-point data register. For example,
the syntax for square root is:
.
FSQRT. ,FPn or,
FSQRT.X
FPm,FPn or,
FSQRT.X
FPn'

MOTOROLA
4-69

III

MC68882

The MC68882 monadic operations available are as follows:
FABS
Absolute Value
FACOS
Arc Cosine
FASIN
Arc Sine
FATAN
Arc Tangent
FATANH
Hyperbolic Arc Tangent
FCOS
Cosine
FCOSH
Hyperbolic Cosine
FETOX
e to the x Power,
FETOXM1
e to the X Power -1
FGETEXP
Get Exponent
FGETMAN
Get Mantissa
FINT
Integer Part
FLlNTRZ
Integer Part (Truncated)
FLOG10
Log Base 10
FLOG2
Log Base 2
FLOGN
Log Base e
FLOGNP1
Log Base e of (x + 1)
FNEG
Negate
FSIN
Sine
FSINCOS
Simultaneous Sine and Cosine
FSINH
Hyperbolic Sine
FSORT
Square Root
FTAN
Tangent
FTANH
Hyperbolic Tangent
FTENTOX
10 to the x Power
FTST
Test
FTWOTOX
2 to the x Power

DYADIC OPERATIONS
Dyadic operations have two operands each. The first
operand is in a floating-point data register, memory, or
an MC68020 or MC68030 data register. The second operand is the contents of a floating-point data register. The
destination is the same floating-point data register used
for the second operand. For example, the syntax for floating-point add is:
FADD.
,FPn
FADD.X
FPm,FPn
The dyadic operations available with the MC68882 are as
follows:
FADD
Add
FCMP
Compare
FDIV
Divide
FMOD
Modulo Remainder
FMUL
Multiply
FREM
IEEE Remainder
FSCALE
Scale Exponent
FSGLDIV
Single Precision Divide
FSGLMUL
Single Precision Multiply
FSUB
Subtract

BRANCH, SET, AND TRAP-ON CONDITION
The floating-point branch, set, and trap-on condition
instructions implemented by the MC68882 are similar to
the equivalent integer instruCtions of the M68000 Family
processors, except more conditions exist due to the special values in IEEE floating-point arithmetic. When a conditional instruction is executed, the MC68882 performs

MOTOROLA

4-70

the necessary condition checking and reports to the
MC68020 or MC68030 whether the condition is true or
false. The MC68020 or MC68030 then takes the appropriate action. Since the MC68882 and MC68020 or
MC68030 are closely coupled, the floating-point branch
operations execute very quickly.
The MC68882 conditional operations are:
FBcc
Branch
FDBcc
Decrement and Branch
FScc
Set According to Condition
FTRAPcc
Trap-on Condition
(with an Optional Parameter)
where:
cc is one of the 32 floating-point conditional test
specifiers as given in Table 2.

Table 2. Floating-Point Conditional
Test Specifiers
Mnemonic

Definition
NOTE

The following conditional tests do not set the BSUN bit
in the status register exception byte under any circumstances.
F
EQ
OGT
OGE
OLT
OLE
OGL
OR
UN
UEQ
UGT
UGE
ULT
ULE
NE
T

All the conditional tests below set the BSUN bit in the
status register exception byte if the NAN condition code
bit is set when a conditional instruction is executed.
SF
SEQ
GT
GE
LT
LE
GL
GLE
NGLE
NGL
NLE
NLT
NGE
NGT
SNE
ST

M68000 FAMILY
REFERENCE

MC68882

MISCELLANEOUS INSTRUCTIONS
Miscellaneous instructions include moves to and from
the status, control, and instruction address registers. Also
included are the virtual memory/machine FSAVE and
FRESTORE instructions that save and restore the internal
state of the MC68882.
FMOVE
FMDVE
FSAVE
FRESTORE

,FPcr
FPcr,

Move to Control Register(s)
Move from Control Register(s)
Virtual Machine State Save
Virtual Machine State Restore

ADDRESSING MODES
The MC68882 does not perform address calculations.
Thus, if the MC68882 instructs the MC68020 or MC68030
to transfer an operand via the coprocessor interface, the
MC68020 or MC68030 performs the addressing mode calculations requested in the instruction. In this case, the
instruction is encoded specifically for the MC68020 or
MC68030, and the execution of the MC68882 is dependent only on the value of the command word written to
the MC68882 by the main processor.
This interface is flexible and allows any addressing
mode to be used with floating-point instructions. For the
M68000 Family, these addressing modes include immediate, postincrement, predecrement, data or address
register direct, and the indexed/indirect addressing modes
of the MC68020 and MC68030. Some addressing modes
are restricted for instructions consistent with the M68000
Family architectural definitions (e.g., program counter
relative addressing is not allowed for a destination operand).
The orthogonal instruction set of the MC68882 and the
flexible branches and addressing modes of the MC68020/
MC68030 allow a programmer or a compiler writer to
think of the MC68882 as though it is part of the MC68020
or MC68030. There are no special restrictions imposed
by the coprocessor interface, and floating-point arithmetic is coded exactly like integer arithmetic.

(Overflow), DZ (Divide by Zero) and INEX (Inexact result)
. floating-point exception handlers must have these minimum requirements:
1. An FSAVE must be executed before any other
floating-point instruction.
2. A BSET or similar instruction that sets bit 27 of
the BIU flag word (located in the saved idle state
frame).
3. An FRESTORE instruction must be executed before the RTE instruction.
The above requirements are not applicable to interrupt
handlers that do not contain any floating-point instructions. For interrupt handlers that have floating-point instructions, only requirements #1 and #3 must be
implemented.

FUNCTION SIGNAL DESCRIPTIONS
The following paragraphs contain a brief description
of the input and output signals for the MC68882 floatingpoint coprocessor. The signals are functionally organized
into groups as shown in Figure 10.
VCC

GNO

j\s

MC68882
FLOATING-POINT
COPROCESSOR

i'J.....

AO-A4

00-031

AS
RIW

ClK
SIZE
~

RESET

OSACKO

SENSE

OSACKI

Figure 10. MC68882 Input/Output Signals

MC68881 COMPATIBILITY
Using the MC68882 in an existing MC68881 socket does
not require hardware changes nor user-software modifications. Implementation of multiple floating-point instruction execution concurrency gives the MC68882 a
performance advantage over the MC68881. However, to
guarantee that the floating-point exception model maintains the precepts of a sequential execution model, some
systems-level software modifications are needed to upgrade the system to operate properly with an MC68882.
First, note that the idle and busy state frames (generated by the FSAVE instruction) are both 32 bytes larger
with the MC68882 than the MC68881. The offsets for the
exceptional operand, the operand register word, and t~e
BIU flag word from the top of the saved idle state frame
are 32 bytes more than that of the MC68881. However, a
unique format word is generated by the MC68882 enabling the system software to detect this difference. The
unique format word prevents a saved MC68881 context
from being restored into an MC68882 and vice versa.
Second, the BSUN (Branch or Set on Unordered), SNAN
(Signaling Not-A-Number), OPERR (Operand Error), OVFL

M68000 FAMILY
REFERENCE

NOTE
The terms assertion and negation are used extensively to avoid confusion when describing "activelow" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active
or true, independent of whether that level is represented by a high or low voltage. The term negate
or negation is used to indicate that a signal is inactive or false.
ADDRESS BUS (AO through A4)
These active-high address line inputs are used by the
main processor to select the coprocessor interface register locations located in the CPU address space. These
lines control the register selection as listed in Table 3.
When the MC68882 is configured to operate over an 8bit data bus, the AO pin is used as an address signal for
byte accesses of the coprocessor interface registers. When
the MC68882 is configured to operate over a 16- or 32bit system data bus, both the AO and the SIZE pins are
strapped high and/or low as listed in Table 4.

MOTOROLA
4-71

_
~

MC68882

Table 3. Coprocessor Interface
Register Selection
A4-AO

Offset

Width

Type

00001<

$00

Read

Response

0001x

$02

Write

Control

0010x

$04

Read

Save

0011x

$06

RIW

Restore

0100x '

$08

(Reserved)
Command

0101><

$OA

Write

0110x

$OC

(Reserved)

0111x

$OE

Write

Condition

100xx

$10

RIW

Operand

1010x

$14

, 16

Read

1011x

$16

110xx

$18

Read

Instruction Address

111xx

$1C

Operand Address

(Reserved)

Table 4. System Dat~ B~s Size Configuration
AO

SIZE

Low

Data Bus
8-Bit

Low

High

16-Bit

High

32-Bit

DATA BUS (DO through D31)
This 32-bit, bidirectional, three-state bus serves as the
general purpose data path between the MC68020/
MC68030 and the MC68882. Regardless of whether the
MC68882 is operated as a coprocessor or a peripheral
processor, a" inter-processor transfers of instruction information, operand data, status information, and requests for service occur as standard M68000 bus cycles.
The MC68882 wi" operate over an 8-, ,16-, or 32~bit
system data bus. Depending upon the system data bus
configuration, both theAO and SIZE pins are configured
specifically for the applicable bus configuration. (Refer to
ADDRESS BUS (AO through A4) and SIZE (SIZE) forturther. detailsf. ,
SIZE (SIZE)
This active-low input signal is:used in conjunction with
the AO pin to configure the MC68882 for operation over
an 8-,16-, or 32-bit system data bus. When the MC68882
is configured !£...Qperate over a 16- or 32-bit system data
bus, both the SIZE and AO pins are strapped high and/or
low as listed in Table 4.
ADDRESS STROBE (AS)
This active-low input signal indicates that there is a
valid address on the address bus, and both the chip select
(CS) and read/write (RtW) signal lines are valid.

MOTOROLA
4-72

CHIP SELECT (CS)
This active-low input signal enables the main processor
access to the MC68882 coprocessor interface registers.
When operating the MC68882 as a peripheral processor,
the chip select decode is system dependent (i.e., like the
chip select on any peripheral).
READIWRITE (RtW)
This input signal indicates the direction of a bus transaction (read/write) by the main processor. A logic high
(1) indicates a read from the MC68882, and a logic low
(0) indicates a write to the MC68882. The R/W signal must
be valid when AS is asserted.
'
DATA STROBE (DS)
This active-low input signal indicates that there is valid
data on the data bus during a write bus cycle.
DATA TRANSFER AND SIZE ACKNOWLEDGE
(DSACKO, DSACK1)
These active-low, three-state output signals indicate
the completion of a bus cycle to the main processor. The
MC68882 asserts both the DSACKO and DSACK1 signals
upon assertion of CS.
.
·If the bus cycle is a main processor read, the MC68882
asserts DSACKO and DSACK1 signals to indicate that the
informatin on the data bus is valid. (Both DSACK signals
may be asserted in advance of the valid data being placed
on the bus.) If the bus cycle is a main processor write to
the MC68882, DSACKO and DSACK1 are used to acknowledge acceptance of the data by the MC68882.
The MC68882 also uses DSACKO and DSACK1 signals
to dynamically indicate to the MC68020/MC68030 the
"port" size (system data bus width) on a cycle-by-cycle
basis. Depending Lipon which of the two DSACK pins are
asserted in a given bus cycle, the MC68020/MC68030 assumes data has been transferred to/from an 8-, 16-, or
32-bit wide data port. Table 5 lists the DSACK assertions
that are used by the MC68882 for the various bus cycles
over the various system data bus configurations.
Table 5 indicates that a" accesses over a 32-bit bus
where A4 equals zero are to 16-bit registers. The MC68882
implements a" 16-bit coprocessor interface registers on
data lines D16-D31 (to eliminate the need for on-chip
multiplexers); however, the MC68020/MC68030 expects
16-bit registers that are located in a 32-bit port at odd
word addresses (A 1 = 1) to be implemented on data lines
DO-D15. For accesses to these registers, when configured
for 32-bit bus operation, the MC68882 generates DSACK
signals as listed in Table 5 to inform the MC68020/
MC68030 of valid data on D16-D31 instead ofDO-D15.
An external holding resistor is required to maintain
both DSACKO and DSACK1 high between bus cycles. In
order to reduce the signal rise time, the DSACKO and
DSACKl lines are actively pulled up (negated) by the
MC68882 following the rising edge of AS or DS, and both
DSACK lines are then three-stated (placed in the highimpedance state) to avoid interference with the next bus
cycle.

M68000 FAMILY
REFERENCE

MC68882

Table 5. DSACK Assertions

Data bus

DSACK1

DSACKO

32-Bit

Low

32-Bit

Low

High

Valid Oata on 031-016

16-Bit

Low

High

Valid Oata on 031-016 or 015-00

8-Bit

High

Low

Valid Oata on 031-024, 023-016, 015-08, or 07-00

All

High

Insert Wait States in Current Bus Cycle

Comments
Valid Data on 031-00

RESET (RESET) ,

SENSE DEVICE (SENSE)

This active-low input signal causes the MC68882 to
initialize the floating-point data registers to non-signaling
not-a-numbers (NANs) and clears the floating-point control, status, and instruction address registers.
When performing a power-up reset, external circuitry
should keep the RESET line asserted for a minimum of
four clock cycles after VCC is within tolerance. This as~
sures correct initialization of the MC68882 when power
is applied. For compatibility with all M68000 Family devices, 100 milliseconds should be used as the minimum.
When performing a reset of the MC68882 after VCC has
been within tolerance for more than the initial power-up
time, the RESET line must have an asserted pulse width
which is greater than two clock cycles. For compatibility
with all M68000 Family devices, 10 clock cycles should
be used as the minimum.

This pin may be used optionally as an additional GND
pin or as as indicator to external hardware that the
MC68882 is present in the system. This signal is internally
connected to the GND of the die, but it is not necessary
to connect it to the external ground for correct device
operation. If a pullup resistor (which should be larger than
10 kohm) is connected to this pin location, external hardware may sense the presence of the MC68882 in a system.
POWER (VCC and GND)

These pins provide the supply voltage and system reference level forthe internal circuitry ofthe MC68882. Care
should be taken to reduce the noise level on these pins
with apropriate capacitive decoupling.
NO CONNECT (NC)

CLOCK (CLK)

The MC68882 clock input is a TTL-compatible signal
that is internally buffered for development of the internal
clock signals. The clock input should be a constant frequency square wave with no stretching or shaping techniques required. The clock should notbe gated off at any
time and must conform to minimum and maximum period and pulse width times.

One pin of the MC68882 package is designated as a no
connect (NC). This pin position is reserved for future use
by Motorola, and should not be used for signal routing
or connected to VCC or GND.
SIGNAL SUMMARY

Table 6 provides a summary of all the MC68882 signals
described in the above paragraphs.

Table 6. Signal Summary

Signal Name

Mnemonic

Input/Output

Active State

Address Bus

AO-A4

Input

High

Three State

Oata Bus

00-013

Input/Output

High

Yes

SIZE

Input

Low

Address Strobe

Input

Low

Chip Select

Input

Low

ReadlWrite

RIW

Input

High/Low

Oata Strobe

Input

Low

OSACKO,OSACK1

Output

Low

Yes

Reset

RESET

Input

Low

Clock

CLK

Input

Sense Oevice

SENSE

Input/Output

Low

Power Input

VCC

Input

Ground

GNO

Input

Size

Oata Transfer and Size Acknowledge

M68000 FAMILY

REFERENCE

MOTOROLA
4-73

MC68882

INTERFACING METHODS
FCO-FC2

MC68882/MC68010 OR MC68030 INTERFACING

A20-A31

The following paragraphs describe how to connect the
MC68882 to an MC68020 or MC68030 for coprocessor·
operation via an 8-, 16-, or 32-bit data bus.
32-Bit Data Bus Coprocessor Connection

A16-A19
A13-A15
A5-A12
0
M
0

Figure 11 illustrates the coprocessor interface connection of an MC68882 to an MC68020/MC68030 via a 32-bit
data bus. The MC68882 is configured to operate over a
32-bit data bus when both the AO and SIZE pins are connected to VCC:

FCO-FC2 ~,.....-CHIP
A20-A31 r-SELECT
A16-A19 ~ OECOOE
A13-A15

~'----

A5-A12 ~
Al-A4
0

::E

0
N
0
0:>
<0

AO
N

cr:
0

AS
OS

RtW

-.. cs

co
co
co
u

::E

RtW

::E

024-031
016-023

08-015

00-07
OSACKO
OSACKI

00-07

--------

OSACKO
OSACKI

VCC~ SIZE

Figure 12. 16-Bit Data Bus Coprocessor Connection

co
co
co

.... os

::E

RtW

COPROCESSOR
CLOCK

MAIN PROCESSOR
CLOCK

Al-A4
VCC ....... AO

cr:

'"
::E

Al-A4

8-Bit Data Bus Coprocessor Connection

::E

024-031
016-023 .-.

...

024-031
016-023

...

00-07

08-015
00-07 .OSACKO
OSACKI

08-015

OSACKO
OSACKI

MAIN PROCESSOR
CLOCK

COPROCESSOR
CLOCK

Figure 11. 32-Bit Data Bus Coprocessor Connection

Figure 13 illustrates the connect of an MC68882 to an
MC68020/MC68030 as a coprocessor over an 8-bit data
bus. The MC68882 is configured to operate over an 8-bit
data bus when the SIZE pin is connected to GND. The
twenty-four least-significant data pins (DO-D23) must be
connected to the eight most-significant data pins (D24D31) when the MC68882 is configured to operate over an
8-bit data bus (Le., connect DO to D8, D16 and D24; D1
to D9, D17, and D25; ... and D7 to D15, D23 and D31).
The DSACK pins of the two devices are directly connected, although it is not necessary to connect the DSACK1
pin since the MC68882 never asserts it in this configuration.
MC68882-MC68000/MC68008/MC68010 INTERFACING

16-Bit Data Bus Coprocessor Connection
Figure 12 illustrates the coprocessor interface connection of an MC68882 to an MC68020/MC68030 via a 16-bit
data bus. The MC68882 is configured to operate over a
16-bit 5 data bus when the SIZE pin is connected to VCC,
and the AO pin is connected to GND. The sixteen leastsignificant data pins (DO-D15) must be connected to the
sixteen most-significant data pins (D16-D31) when the
MC68882 is configured to operate over a 16-bit data bus
(Le., connect DO to D16, D1 to D17, ... and D15 to D31).
The DSACK pins of the two devices are directly connected, although it is not necessary to connect the DSACKO
pin since the MC68882 never asserts it in this configuration.

MOTOROLA
4-74

The following paragraphs describe how to connect the
MC68882 to an MC68000, MC68008, or MC68010 processor for opertion as a peripheral via an 8- or 16-bit data
bus.
16-Bit Data Bus Peripheral Processor Connection
Figure 14 illustrates the connection of an MC68882 to
an MC68000 or MC68010 as a per'ipheral processor over
a 16-bit data bus. The MC68882 is configured to operate
over a 16-bit data bus when the SIZE pin is connected to
VCC, and the AO pin is connected to GND. The sixteen
least-significant data pins (DO-D15) must be connected to
the sixteen most-significant data pins (D16-D31) when the
MC68882 is configured to operate over a 16-bit data bus
(Le.,connect DO to D16, D1 to D17, ... and D15 to D31).

M68000 FAMILY
REFERENCE

MC68882

FCO-FC2
A20-A31

A16-A19
A13-A15
acry
a
ex)
CD

A5-A12

SIZE

Al-A4

AS
OS

a
aex)

ex)
ex)
ex)

The OSACK1 pin of the MC68882 is connected to the
OTACK pin of the main processor, and the OSACKO pin
is not used.
When connected as a peripheral processor, the MC68882
chip select (CS) decode is system dependent. If the
MC68000 is used as the main processor, the MC68882 CS
must be decoded in the supervisor or user data spaces.
,However, if the MC68010 is used for the main processor,
the MOVES instruction may be used to emulate any CPU
space access that the MC68020/MC6803..Q...generates for
coprocessor communications. Thus, the CS decode logic
for such systems may be the same as in an MC680201
MC68030 system, such that the MC68882 will not use any
part of the data address spaces.

024-031

016-023

8-Bit Data Bus Peripheral Processor Connection

08-015

00-07

Figure 15 illustrates the connection of an MC68882 to
an MC68008 as a peripheral processor over an 8-bit data
bus. The MC68882 is configured to operate over an 8~bit
data bus when the SIZE pin is connected to GNO. The
eight least-significant data pins (00-07) must be connected to the twenty-four most-significant pins (08-031)
when the MC68882 is configured to operate over an 8bit data bus (i.e., connect 00 to 08, 016, and 024; 01 to
09,017, and 025; ... and 07 to 015, 023; and 031). The
OSACKO pin of the MC68882 is connected to the OTACK
pin of the MC68008, and the OSACK1 pin is not used.
When connected as a peripheral processor, the MC68882
chip select (CS) decode is system dependent, and the CS
must be decoded in the supervisor or user data spaces.

OSACKO

----------MAIN PROCESSOR
CLOCK

OSACKI

COPROCESSOR
CLOCK

Figure 13. 8-Bit Data Bus Coprocessor Connection

FCO-FC2

A20-A23 OR A31
A16-A19
A13-A15
'A5-AI2

a
a
ex)

A16-A19
A13-A15
A5-A12

~.
u

..
1--.
-

"':--.

ex)
ex)
ex)

UOS
LOS

CHIP
SELECT
DECODE
(SYSTEM
OEPENOENTI

--.. cs

GNO--" SIZE
... Al-A4

Al-A4

r---.

ex)

a
aex)

AS
OS

-'"

016-023

016-023
00-07

OTACK

08-015
00-07

OTACK

OSACKO
OSACKI

COPROCESSOR
CLOCK

Figure 14. 16-Bit Data Bus Peripheral
Processor Connection

M68000 FAMILY
REFERENCE

08-015
00-07

00-07
~

OSACKO

MAIN PROCESSOR
CLOCK

024-031

024-031
08-015

AS
OS

MAIN PROCESSOR
CLOCK

OSACKI

COPROCESSOR
CLOCK

Figure 15. 8-Bit Data Bus Peripheral
Processor Connection

MOTOROLA
4-75

MC68882

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

VCC

-0.3 to +7.0

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature

oto 70

Tsta

-55 to + 150

°c
°c

Symbol

Value

Rating

9JA
9JC

33
15

Storage Temperature

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
'
voltage level (e.g., either GND or VCC).

°CIW

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ=TA + (PD· 6JA)
(1)
where:
TA
= Ambient Temperature,OC
6JA·= Package Thermal Resistance,
Junction-to-Ambient, °CIW .
Po
= PINT+PIIO
PINT = ICC x VCC, Watts - Chip ,Internal Power
PI/O = Power Dissipation on Input and Output
Pins - User Determined
For most applications PI/O

7
041

6
XRM

5
I

OPERATION CONTROl REGISTER

3
2
I DPS 1

--------

PCL

051 DIR

SliE

CHAIN

~
o BBIT
I

00
01
10
11
00
01
10
11

00 1 C?C I

061

SEQUENCE CONTROL REGISTER
5
3
2

----I
MAC

DAC

071 STR

CHANNEL CONTROL REGISTER
5
5
4
3
2

I CNT I HLT I SAB liNT I

rio

00
01
10
11

NO COUNT
01 COUNT UP
10 (MC684501
11 IUNOEFINEDI

I0 I0 I

iNTERRUPT ENABLE

SOFTWARE ABORT
SOFTWARE HALT

NO COUNT
COUNT UP
(MC68450!
(UNDEFINEDI

CONTINUE OPERATION
START CHANNEl

00 BYTE
01 WORO
10 IMC68450!
11 IUNOEFINEO!

116·BIT

oMEMORY TO DEVICE
1 DEVICE TO MEMORY

BURST
(UNDEFINED!
CYCLE STEAL
(MC68450!

B~C I N?T I ERIR I AC1T I RLID I

REali )

EXPLICIT M68000
(MC6845Oi
IMPLICIT w/ACK
IMPLICIT w/ACK AND ROY

CHANNEl STATUS REGISTER
5
3
2

010 INTERNAL LIMITED RATE
a1 INTERNAL MAXIMUM RATE
10 EXTERNAL
11 (MC684501
00 DISABLED
01 (UNDEFINED!
10lMC6B45DI
11 (MC68450!

000 STATUS
00 1 INTERRUPT
1 IMC68450!
011 ABORT
100 RElOAD
101 IUNDEFINED!
110 IUNDEFINEDI
111 (UNDEFINED(

TP~:LILEVEl

all

CHANNEl PRIORITY REGISTER

CHANNEl ERROR REGISTER
3
2

ERROR
00000
00001
00010
00011
oo 1rr
oIOrr
011 rr
10000
10001

PCL TRANSITION
RElOAD OCCURRED
CHANNEl ACTIVE
ERROR
NORMAL DEVICE TERMINATION
BLOCK TRANSFER COMPLETE
CHANNEL OPERATION COMPLETE

IaI

3
0

NO ERROR
CONFIGURATION ERROR
OPERATION TIMING ERROR
(UNDEFINEDI
ADORESS ERROR
BUS ERROR
COUNT ERROR
. EXTERNAL ABORT
SOFTWARE ABORT

GENERAL CONTROL REGISTER
1

---CP

00
01
10
11

PRIORITY
PRIORITY
PRIORITY
PRIORITY

I0 I0

2
BT

cio

0 IHIGHEST!
1 ILOWEST!
2 IMC68450!
3 IMC68450i

00
01
10
11

16
32
64
12B

50.00'1\
0125.00'1\
1012.50'1\
11 6.25'1\
CLOCKS
CLOCKS
CLOCKS
CLOCKS

10010}
IUNOEFINEDI
•
11111

00 MAR ANO OAR
01 MAR/MTCR
ERROR INTERRUPT VECTOR REGISTER

NORMAL INTERRUPT VECTOR REGISTER

1---1

251

271

15
OA

DEVICE FUNCTION COOE REGISTER·
3

o-i
o::0

(.TIO
~,

~»

29 _'---'-_L----'

lAI

141

oci

BASE TRANSFER COUNT REGISTER

·1

I I

MEMORY ADDRESS REGISTER

I I 1 I

391

lci

BASE ADDRESS· REGISTER

I I I I

Figure 10. Register Summary

(")

1...1

BASE FUNCTION CODE REGISTER
3
a

DEVICE ADDRESS REGISTER

, - I_ ' - - - ' - _ ' - - - '

MEMORY FUNCTION CODE REGISTER

IaI

MEMORY TRANSFER COUNT REGISTER

I
31

10 OAR
11 BARiBTCR

-I

~
(")
en

MC68440/MC68442

The register memory map is identical to the register
memory map for the MC68450 DMAC, including the individual bit assignments within the registers. However,
not all functional options available on the DMAC are
available on the DDMA and vice versa, and the channel
2 and 3 registers on the DMAC are treated as null registers
on the DDMA. If any programmable options labeled
'MC68450 Reserved' or 'Undefined, Reserved' are programmed into a DDMA channel, a configuration error will
occur when the MPU attempts to start that channel.
All registers within the DDMA are always accessible as
bytes or words by the MPU (assuming that the MPU can
gain control of the DMA bus); however, some registers

may not or should not be modified while a channel is
actively transferring data. If a register may not be modified during operation and an attempt is made to write
to it, an operation timing error will be signaled and the
channel operation aborted.
RESET OPERATION RESULTS
When the DDMA is reset, either during a system powerup sequence or to re-initialize the DDMA, many of the
registers will be affected and will be set to known values.
Table 2 shows the hexadecimal value that will be placed
in each register by a reset operation.

Table 2. Reset Operation Results
Register
MARc
DARc
BARc

Value

Comments

XXXXXXXX
XXXXXXXX
XXXXXXXX

MFCRc

DFCRc

BFCRc

MTCRc
BTCRc

XXXX
XXXX

NIVRc

Uninitialiled Vector

EIVRc

Uninitialiled Vector

CPRc

DCRc

OCRc

SCRc

CCRc

CSRc

00 or 01

CERc

GCR

Channel Not Active, Interrupts Disabled
(Depending on the Level of PCLc)
No Errors

X r Indicates an unknown value or the previous value of the register.
c r Is the channel number (Le., 0 or 1).

MOTOROLA
5-12

M68000 FAMILY

REFERENCE

MC68440/MC68442

ElECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

VCC

-0.3 to +7.0

Input Voltage

Vin

-0.3 to +7.0

o to 70

°c

Tstg

-55 to 150

°c

Operating Temperature Range
Storage Temperature

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are
tied to an appropriate logic voltage level (e.g.,
either GND or Vce).

THERMAL CHARACTERISTICS
Characteristic

Symbol

Thermal Resistance
Ceramic (L Suffix)
Plastic (P Suffix)
Pin Grid Array (R/RC Suffix)

6JA

Value Symbol

Value

30
30
33

Unit
°CIW

6JC
15*
15*
15

*Estimated

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °c can
be obtained from:
TJ=TA+(PooOJA)
(1)
where:
= Ambient Temperature, °c
TA
flJA = Package Thermal Resistance,
Junction-to-Ambient,OC/W
Po
= PINT+PIIO
PINT = ICC x VCC' Watts - Chip Internal Power
PliO = Power Oissipation on Input and Output
Pins - User Oetermined
For most applications PI/O

a:
.....
.....

~~g
:cc::o~

;:=
<
c::o

-=-

K=>

r;:

I~ I~

...~ 11k
~

Lt)

o c::o

I~ Ii I~

RE01
ACK1
PCll

c::o

I CLOCK

AS
LOS
UDS
RfW
DTACK
FCO·FC2

MC6B450
DMAC

RE02
ACK2
PCL2

DTC
I'
DONE
CLK

CLK

•

/3
f'--

::f-+

AS
LOS
UDS
R/W
DTACK
FCO·FC2
ERROR

f--

~~~

~- ~
-

00·015

...

liS

R/W
DTACK
lACK

r--

AS
RESET

i~
0
0
0

iiiQ

r--

LOS
UDS
R/W
DTACK
VPA
VMA
E
3

r--

Al·A23

MEMORY

DO.D15 V

IPLO·IPL2

C/)rr-

FCO·FC2

MC6BOOO
OR
MC68010
MPU

00015
A1·A23

§r-~
~~

L..-

PCL2
ACK2

R/Vi

SN74LS373
80

K'I

MC68450
DMAC

-V

A8iOOA23ID15
OBEN
OOIR

L-

Figure 2. Typical System Configuration with M6800-Type Peripheral Devices

MOTOROLA
5-32

M68000 FAMILY

REFERENCE

MC68450

OPERAND TRANSFER MODES

DATA

The DMAC can perfarm implicit address af explicit address data transfers using any af the fallawing pratacals:
1. explicitly addressed, MC68000 campatible device,
2. explicitly addressed, MC6800 campatible devices,
3. implicitly addressed, device with acknawledge, and
4. implicitly addressed, device with acknawledge and
ready.

ADDRESS

J
DEVICE
(OR MEMORY)

In the first twa pratacals, data is transferred fram the
saurce to' an internal DMAC halding register,· and thEm
an the next bus cycle maved from the halding register
to' the destinatian. Pratacals 3 and 4 require anly ane bus
cycle far data transfer, since anly ane device needs to' be
addressed. With these pratacals, cammunicatian is perfarmed using a twa-signal and three-signal handshake,
respectively.
Implicitly addressed devices do. nat require the generatian af a device data register address far a data transfer. Such a device is cantrolled by a five signal device
cantral interface an the DMAC during implicit address
transfers as shawn in Figure 3. Since anly memary is
addressed during such a data transfer, this methad is
called the single-address methad.

'<:.~
INTERNAL
HOLDING
REGISTER
DDMA

BUS CYCLE # 1 '
DATA

DEVICE
(OR MEMORY)

MEMDRY

BUS CYCLE #2

Figure 4. Dual-Address Transfer Sequence

Figure 3. Implicitly Addressed Device Interface

Explicitly addressed devices require that a data register
within the peripheral device be addressed. No. signals
ather than the M68000 asynchranaus bus cantral signals
are needed to' interface with such a device, altha~gh any
af the five device cantral signals may also. be used. Because the address bus is used to' access the peripheral,
the data cannat be directly transferred ta/fram memary
since memary also. requires addressing. Therefare, data
is transferred fram the saurce to' an internal halding register in the DMAC and then transferred to' the destinatian
during a secand bus transfer as shawn in Figure 4. Since
bath memary and the device are addressed during such
a data transfer, this methad is called the dual-address
methad.

CHANNEL OPERATING MODES
There are three types af channel aperatians: 1) single
black transfers, 2) cantinued aperatian, and 3) chained
aperations. The first twa mades utilize an-chip registers
while the last made uses an an-chip address register to'

M68000 FAMILY

REFERENCE

paint to' address and caunt parameters stared in system
memary.
When transferring single blacks of data, the memary
address and device address registers are initialized by
the user to' specify the saurce and destinatian af the transfer. Also. initialized is the memary transfer caunt register
to' caunt the number af aperands transferred in a black.
Repeated transfers are passible with the cantinue made
af aperatian, where the memary address and transfer
caunt registers are autamatically loaded fram internal
registers upan campletian af a black transfer. See Figure
5.
The twa chaining mades are array chaining and linked
array chaining. The array chaining made aperates fram
a cantiguaus array in memary cansisting af memary addresses and transfer caunts. The base address register
and base transfer caunt register are initialized to' paint to'
the beginning address af the array and the number af
array entries, respectively. As each black transfer is campleted, the next entry is fetched from the array, the base
transfer caunt is decremented, and the base address is
incremented to' paint to' the next array entry. When the
base transfer caunt reaches zero., the entry just fetched
is the last black transfer defined in the array. See Figure

6.
The linked array chaining made is similar to' the array
chaining made, except that each entry in the memary
array also. cantains a link address which paints to' the
next entry in the array. This allaws a nan-cantiguaus
memary array. The last entry cantains a link address set
to' zero.. No. base transfer caunt register is needed in this
made. The base address register is initialized to' the address af the .first entry in the array. The link address is

MOTOROLA

5-33

MC68450

MEMORY

M68000
PROCESSOR

SUPPLIES:
DEVICE ADDRESS
MEMORY ADDRESS
MEMORY TRANSFER COUNT

BLOCK

MC68450
DMAC

DEVICE
OR
MEMORY

Figure 5.

Si~gle

used to update the base address register at the beginning
of each block transfer. This chaining mode allows array
entries to be easily moved or inserted without having to
reorganize the array into sequential order. Also, the number of entries in the array need not be specified to the
DMAC. See Figure 7.

Block Transfer

vector register, for use in the M68000 vectored interrupt
structure. Two vector registers are available for each
channel.

CHANNEL PRIORITY

Each channel may be given a priority level of 0, 1, 2,
or 3. If several channel requests occur at the same priority
level, a round-robin is entered automatically.
INTERRUPT OPERATION

The DMAC will interrupt the MPU for a number of event
occurrences such as the completion of a DMA operation,
or at the request of a peripheral device using a PCl line.
The user must write interrupt vectors into an on-chip

MOTOROLA
5-34

REQUEST MODES

. Requests may be externally generated by a device or
internally generated by the auto-request mechanism of

M68000 FAMILV

REFERENCE

MC68450

MEMORY

M6BOOO
PROCESSOR

MEMORY

INITIAL
BASE ADDRESS

BASE COUNT ~

SUPPLIES:
DEVICE ADDRESS
BASE ADDRESS
BASE TRANSFER COUNT

MEMORY
ADDRESS A
MEMORY
COUNT A
MEMORY
ADDRESS B
MEMORY
COUNT B
MEMORY
ADDRESS C
MEMORY
COUNT C
MEMDRY
ADDRESS D
MEMORY
COUNT D

{

COUNT D

CDUNT B

{

BLOCK D

BLOCK B

MC68450
DMAC

BLOCK C

{

BLOCK A

DEVICE OR
MEMORY

Figure 6. Array Chain Transfer

the DMAC. Auto-requests may be generated either at the
maximum rate, where the channel always has a request
pending, or at a limited rate determined by selecting a
portion of the bus bandwidth to be available for DMA
activity. External requests can be either burst requests or
cycle steal requests that are generated by the request
signal associated with each channel.

REGISTERS
The DMAC contains 17 registers for each of four channels plus one general control register, all of which are

M68000 FAMILY

REFERENCE

under complete software control. The user programmer's
model of the registers is shown in Figure 8.
The DMAC registers contain information about the data
transfers such as the source and destination address and
function codes, transfer count, operand size, device port
size, channel priority, continuation address and transfer
count, and the function of the peripheral control line. One
register also provides status and error information on
channel activity, peripheral inputs, and various events
which may have occurred during a DMA transfer. A general control register selects the bus utilization factor to
be used in limited rate auto-request DMA operations.

MOTOROLA
5-35

MC68450

MEMORY

M68000
PROCESSOR

SUPPLIES:
DEVICE ADDRESS
BASE ADDRESS

MEMORY

COUNT C

BLOCK C

itt

INITIAL
BASE ADDRESS

g,§
MEMORY
ADDRESS A
MEMORY
COUNT A
LINK TO
B

MEMORY
ADDRESS C
MEMORY
COUNT C

If;

COUNT A

{

BLOCK A

MC68450
DMAC

-0(TERMINATOR I

MEMORY
ADDRESS B
MEMORY
COUNT B
LINK TO
C

COUN\ {

BLOCK B

MEMORY

Figure 7. Linked Array Chain Transfer

SIGNAL DESCRIPTION
The following paragraphs contain a brief description
of the DMAC input and output signals. Included at the
end of the functional description of the signals is a table
describing the electrical characteristics of each pin (i.e.,
the type of driver used).

NOTE
The terms assertion and negation will be used
extensively. This is done to avoid confusion
when dealing with a mixture of "active-low"
and "active-high" signals. The term assert or
assertion is used to indicate that a signal is
active or true, independent of whether that
level is represented by a high or low voltage.

MOTOROLA
5-36

The term negate or negation is used to indicate that a signal is inactive or false.

SIGNAL ORGANIZATION
The input and output signals can be functionally organized into the groups shown in Figure 9. The function
of each signal or group 'of signals is discussed in the
following paragraphs.
Address/Data Bus (AS/DO through A23/D15)
This 16-bit bus is time multiplexed to provide address
outputs during the DMA mode of operation and is used
as a bidirectional data bus to input data from an external
device (during an MPU write or DMA read) or to output

M68000 FAMILY
REFERENCE

MC68450

GENERAL CONTROL

DEVICE CONTROL

OPERATION CONTROL
SEQUENCE CONTROl
CHANNEL CONTROL
CHANNEL PRIORITY

CHANNEL STATUS
CHANNEL ERROR
NORMAL INTERRUPT VECTOR
ERROR INTERRUPT VECTOR
MEMORY FUNCTION COOE
DEVICE FUNCTION CODE
BASE FUNCTION COOE

CH3
CH2
CHl
HO

MEMORY TRANSFER COUNT
BASE TRANSFER COUNT
MEMORY AOORESS
DEVICE ADDRESS
BASE AODRESS
23

*Word Aligned Register Pairs

Figure 8. DMAC Programmer's Model

FCO·FC2

} DEVICE
CONTROL
CHO

AB/DO·A23/D 15

REOl
ACKl
PCl1

} DEVICE
CONTROL
CHl

REQ2
ACK2
PCl2

} DEVICE
CONTROL
CH2

UDS
lOS
OTACK

RE03
ACK3
PCl3

} DEVICE
CONTROL
CH3

BECO·BEC2

DTC
DONE

}
}

A1·A7

ASYNCHRONOUS
BUS CONTROL

Riw

OWN
MULTIPLEX
CONTROL

ufiS

iRQ

DB EN
DDIR
HIBYTE
ClK

lACK

iiR
iiG
BGACK

}

DEVICE
CONTROL
INTERRUPT
CONTROL
BUS
ARBITRATION

Figure 9. Signal Organization

M68000 FAMILY

REFERENCE

MOTOROLA
5-37

MC68450

data to an external device (during an MPU read or a DMA
write). This is a three-state bus arid is demultiplexed using external latches and buffers controlled by the multiplex control lines.
Lower Address Bus (A1 through A7)
These bidi'rectional three-state ·Iines are used to address the DMAC internal registers in the MPU mode and
to provide the lower seven address outputs in the DMA
mode.
.
Function Codes (FCO through FC2)
These three-state output lines are used in the DMA
mode to further qualify the value on the address bus to
provide eight seperate address spaces that may be defined by the user. The value placed on these lines is taken
from one of the internal function code registers, depending on the register that provides the address used during
a DMA bus cycle.
Asynchronous Bus Control
Asynchronous data transfers are handled using the following control signals: chip select, address strobe, read/
write, upper and lower data strobes, and data transfer
acknowledge. These signals are described in the following paragraphs.
CHIP SELECT (CS). This input signal is used to .select the
DMAC for an MPU bus cycle. When CS is asserted, the
address on A 1-A7 and the data strobes (or A when using
an 8-bit bus) select the internal DMAC register that will
be involved in the transfer. CS should be generated by
qualifying an address decode signal with the address and
data strobes.
ADDRESS STROBE (AS). This bidirectional signal is used
as an output in the DMA mode to indicate that a valid
address is present on the address bus. In the MPU or
IDLE modes, it is used as an input to determine when the
DMAC can take control of the bus (if the DMAC has requested and been granted use of the bus).
READIWRITE (RtW). This bidirectional signal is used to
indicate the direction of a data transfer during a bus cycle.
In the MPU mode, a high level indicates that a transfer
is from the DMAC to the data bus and a low level indiates
a transfer from the data bus to the DMAC. In the DMA
mode, a high level indicates a transferfrom the addressed
memory or device to the data bus, and a low level indicates a transfer from the data bus to the addressed memory or device.
UPPER AND LOWER DATA STROBE (UDS) AND (LOS).
These bidirectional lines indicate when data is valid on
the bus and what portions of the bus should be involved
in the transfer.
DATA TRANSFER ACKNOWLEDGE (DTACK). This bidirectionalline is used to signal that an asynchronous bus
cycle may be terminated. In the MPU mode, this output
indicates that the DMC has accepted data from the MPU

MOTOROLA
5-38

or placed data on the bus for the MPU. In the DMA mode,
this input is monitored by the DMAC to determine when
to terminate a bus cycle. As long as DTACK remains negated, the DMAC will insert wait cycles into a bus cycle
and when DTACK is asserted, the bus cycle will be terminated (except when PCl is used as a ready signal, in
which case both signals must be asserted before the cycle
is terminated).
BUS EXCEPTION CONTROL (BECO THROUGH BEC2).
These input lines provide an encoded signal that indicates an abnormal bus condition such as a bus error or
reset.
Multiplex Control
These signals are used to control external multiplex!
demultiplex devices to separate the address and data
information on the A8/DO-A23/D15 lines and to transfer
data between the upper and lower halves of the data bus
during certain DMA bus cycles.
Figure 10 shows the five external devices needed to
demultiplex the address/data pins and the interconnection of the multiplex control signals. The SN74lS245 that
may connect the upper and lower halves of the data bus
is needed only if an 8-bit device is used during single
address transfers.
OWN (OWN. This three-state output indicates that the
DMAC is controlling the bus. It is used as the enable
signal to turn on the external address drivers and control
signal buffers.
UPPER ADDRESS STROBE (UAS). This three-state output
is used as the gate signal to the transparent latches that
capture the value of A8-A23 on the multiplexed address/
data bus.
DATA BUFFER ENABLE (DBEN). This three-state output
is used as the enable signal to the external bidrectional
data buffers.
DATA DIRECTION (DDIR). This three-state output controls
the direction of the external bidirectional data buffers. If
DDIR is high, the data transfer is from the DMAC to the
data bus. If DDIR is low, the data transfer is from the data
bus to the DMAC.
HIGH BYTE (HI BYTE). This three-state output indicate that
data will be present on data lines D8-D15 that must be
transferred to data lines DO-D7, or vice versa, through an
external buffer during a single address transfer between
an 8-bit device and memory.
Bus Arbitration Control
These three signals forma bus arbitration circuit used
to determine which device in a system will be the current
bus master.
BUS REQUEST (BR). This output is asserted by the DMAC
to request control of the bus.

M68000 FAMILY

REFERENCE

MC68450

......
M

.........

OWN

A23·A 16

UAS

MC68450

AI5·AB
DB EN
DOIR
HIBYTE

OIR

R/W

DlR

DIR

Figure 10. Demultiplex Logic

BUS GRANT (BG). This input is asserted by an external
bus arbiter to inform the OMAC that it may assume bus
mastership as soon as the current bus cycle is completed.
The OMAC will not take control of the bus until CS, lACK,
AS, and BGACK are all negated.
BUS GRANT ACKNOWLEDGE (BGACK). This bidirectional signal is asserted by the OMAC to indicate that it
is the current bus master. BGACK is monitored· as an
input to determine when the OMAC can become bus mater and if a bus master other than the system MPU is a
master during limited rate auto-request operation.
Interrupt Control
These two signals form an interrupt request/acknowledge handshake circuit with an MPU.
INTERRUPT REQUEST (IRQ). This output is asserted by
the OMAC to request service from the MPU.

M68000 FAMILY

REFERENCE

INTERRUPT ACKNOWLEDGE (lACK). This input is asserted by the MPU to acknowledge that it has received
an interrupt from the OMAC. In response to the assertion
of lACK, the OMAC will place a vector on 00-07 that will
be used by the MPU to fetch the address of the proper
OMAC interrupt handler routine.
Device Control
These eight lines perform the interface between the
OMAC and four peripheral devices. Four sets of three
lines are dedicated to a single OMAC channel and its
associated peripheral; the remaining two lines are global
signals shared by all channels.
REQUEST (REQO THROUGH REQ3). These inputs are asserted by a peripheral device to request an operand transfer between that peripheral device and memory. In the
cycle steal request generation mode, these inputs are
edge sensitive; in burst mode, they are level sensitive.

MOTOROLA
5-39

MC68450

indicate that the data being transferred is the last item in
a block. The DMAC will assert this signal during a bus
cycle when the memory transfer count register is decremented to zero.

ACKNOWLEDGE (ACKO THROUGH ACK3). These outputs
are asserted by the DMAC to signal to a peripheral that
an operand is being transferred in response to a previous
transfer request.
PERIPHERAL CONTROL LINE (PCLO THROUGH PCL3).
These bidirectional lines are mUlti-purpose signals that
may be programmed to function as ready, abort, reload,
status, interrupt, or enable clock inputs or as start pulse
outputs.

Clock (CLK)
The clock input is a TTL-compatible signal that is internally buffered for development of the internal clocks
needed by the DMAC. The clock input should not be gated
off at any time and the clock signal must conform to
minimum and maximum pulse width times.

DATA TRANSFER COMPLETE (DTC). This output is asserted by the DMAC during any DMAC bus cycle to indicate that data has been successfully transferred (i.e.,
the bus cycle was not terminated abnormally).

SIGNAL SUMMARY
Table 1 is a summary of all the signals discussed in
the previous paragraphs.

DONE (DONE). This bidirectional signal is asserted by the
DMAC or a peripheral device during DMA bus cycle to

Table 1. Signal Summary

Direction

Active State

Driver Type

Synchronizing
Clock Edge

A8/DO-A23/D 15

In/Out

High

Three State

Falling**

A1-A7

In/Out

High

Three State

Falling**

Out

High

Three State

Signal Name

FCO-FC2
CS

Low

In/Out

Low

Three State*

Falling

RIW

In/Out

High/Low

Three State*

Falling

UDS

In/Out

Low/High

Three State*

Falling

LDS

In/Out

Low

Three State*

Falling

DTACK

In/Out

Low

Three State*

Rising

OWN

Out

Low

Open Drain*

UAS

Out

Low

Three State*

DBEN

Out

Low

Three State*

DDIR

Out

High/Low

Three State*

HIBYTE

Out

Low

Three State*

Low

Out

Low

BECO-BEC2
BR
BG
BGACK
IRQ

Low

In/Out

Low

Falling

Rising
Open Drain
Rising
Open Drain*

.In

Low

lACK

Low

REQO-REQ3

Low

ACKO-ACK3

Out

Low

PCLO-PCL3

In/Out

Programmed

Three State

Out

Low

Three State*

In/Out

Low

Open Drain

DTC
DONE
CLK

Falling
Ris'ing
Always Driven
Rising

Rising

*These signals require a pullup resistor to maintain a high voltage when in the high-impedance or negated
state. When these signals go to the high-impedance or negated state, they will first drive the pin high
momentarily to reduce the signal rise time,
'.
.
**These signals are latched on a clock edge, but are not synchronized (i.e., the latched value is used immediately,
rather than delayed by one clock).

MOTOROLA
5-40

M68000 FAMILY

REFERENCE

MC68450

REGISTER DESCRIPTION
Figure 11 shows the memory mapped locations of the
registers for each channel. Figure 12 shows the register
summary and may be used as a quick reference to the
bit definitions within each register.
The register memory map for the MC68450 DMAC is
identical to the register memory map for the MC68440

CHANNEL
BASE
CHO
CHI
CH2
CH3

Dual Channel DMA Controller (DDMA), including the individual bit assignments within the registers. However,
not all functional options available on the DMAC are
available on the DDMA and vice versa. If any programmable options labeled "MC68440 Reserved" or "Undefined, Reserved" are programmed into a DMAC channel,
a configuration error will occur when the MPU attempts
to start that channel.

-00
-40
-80
-CO

01
03
05
07
09
DB
00

OF
11

13
15
17

19
1B
lC

~ Null Bit Position
*The GCR is located at FF only.

Figure 11. Register Memory Map

M68000 FAMILY
REFERENCE

MOTOROLA

5-41

U'lS::
.&0
N-I

o
::c
o
~

6
041

XRM

DEVICE CONTROL REGISTER
3
1
I DTYP lops I
PCL

7
051 DlR I
I

000
001
010
011
100
101
110
111

o
I

00
01
10
11
DO
01
10
11

8·BIT
116·BIT

EXPLICIT
EXPLICIT
IMPLICIT
IMPLICIT

STATUS
INTERRUPT
START PULSE
ABORT
(MC68440)
(UNDEFINED)
(UNDEFINED)
(UNDEFINED)

[C~C I B!C I NOT I ERIR I AC1T I

TP~LILEVEL

0 I

I I
15

DO
01
10
11

NO COUNT
COUNT UP
COUNT DOWN
(UNDEFINED)

. . I I

'"--'I'

NO COUNT
COUNT UP
COUNT DOWN
(UNDEFINED)

INTERRUPT ENA8LE

311I....- - - - ' _ - ' - - - ' - - - - '

SOFTWARE HALT
CONTINUE OPERATION
START CHANNEL

Or-

CHANNel BASE ADDRESSES: CHO·OO
CH1·40'

391....1----"_-'---'----'

7
FFlolo

GENERAL CONTROL REGISTER
5
4
3
1

00000
0000 1
00010
00011
001 rr
010rr
011 rr
10000
10001

NO ERROR
CONFIGURATION ERROR
OPERATION TIMING ERROR
(UNDEFINED)
ADDRESS ERROR
BUS ERROR
COUNT ERROR
EXTERNAL ABORT
SOFTWARE ABORT

010

00
01
10
11

PRIORITY
PRIORITY
PRIORITY
PRIORITY

0 (HIGHEST)
1
2
3 1l0WESTi

00 16
01 32
10 64
11 128

00 50.00%
01 25.00%
10 12.50%
11 6.25%
CLOCKS
CLOCKS
CLOCKS
CLOCKS

10010}
IUNDEFINED)
•
11111

_ rr

00
01
10
11

IMC68440)
MAR/MTCR
OAR
BARIBTCR

I I

I=:::LJ

BASE TRANSFER COUNT REGISTER

tAl

~3~1~~~~II_r_r_r~~~~~--rDE~VICrE=ADDTRE=SSTRE~GIS~TE~R.__._r_r_._,-.-.-,,-.-~~~
31

BASE FUNCTION CODE REGISTER

MEMORY ADDRESS REGISTER

I I I I I

Dcl
31

I I

'BASE ADDRESS REGISTER

lci
CH2-80
CH3·CO

I
*Sits 7-4 read as zeros and are ignored on writes.

(')

co
~

14LI~~~~~__L-L-L-~~~~~-L-L-L~~~~L-L-L-~~~~-L-L-L~~~

MEMORY FUNCTION CODE REGISTER
29 1
.....--''--1----'_-'

0 I 0 I

SOFTWARE ABORT

CHANNEL PRIORITY REGISTER
201 0 I 0 I 0 I

MEMORY TRANSFER COUNT REGISTER
I

DEVICE FUNCTiON CODE REGISTER·

DAC

ERROR INTERRUPT VECTOR REGISTER

I I

OA I

ms:
Z_

-I
MAC

00
01
10
11

2
ERROR

NORMAL INTERRUPT VECTOR REGISTER

-n

CHANNEL CONTROL REGISTER
7
6
5
4
3
2
1 I
071 STR I CNT I HLT I SAB liNT I 0 I 0 I

ERROR
NORMAL DEVICE TERMINATION
BLOCK TRANSFER COMPLETE
CHANNel OPERATION COMPlETE

06101001

CHANNEL ERROR REGISTER
011

PCL TRANSITION

CONTROL REGISTER

BURST
(UNDEFINED)
CYCLE STEAL WITHOUT HOLD
CYCLE STEAL WITH HOLD

CHANNEL ACTIVE
.

::c~
me
e

00 BYTE.
01 WORD
10 LONG WORD
11 BYTE. NO PACKING
oMEMORY TO DEVICE
1 DEVICE TO MEMORY

M68000
M6800
WIACK .
WIACK AND ROY

SE~UENCE

010 INTERNAL LIMITED RATE
01 INTERNAL MAXIMUM RATE
10 EXTERNAL
11 AUTO START. EXTERNAL
DISABLED
(UNDEFINED)
ARRAY CHAINING
LINKED ARRAY CHAINING

00
01
10
11

CHANNEL STATUS REGISTER

OPERATION CONTROL REGISTER
5
4
3
2
SI?E
CH~IN
REDG

Figure 12. Register Summary

MC68450

All registers within the DMAC are always accessible as
bytes or words by the MPU (assuming that the MPU can
gain control of the DMA bus); however; some registers
may not or should not be modified while a channel is
actively transferring data. If a register may not be modified during operation and an attempt is made to write
to it, an operation timing error will be signaled and the
channel operation aborted.

RESET OPERATION RESULTS
When the DMAC is reset, either during a system powerup sequence or to re-initialize the DMAC, many of the
registers will be affected and will be set to known values.
Table 2 shows the hexadecimal value that will be placed
in each register by a reset operation.

Table 2. Reset Operation Results
Register

Value

Comments

MARc

XXXXXXXX

Not Affected

DARc

XXXXXXXX

Not Affected

BARc

XXXXXXXX

Not Affected

MFCRc

Not Affected

DFCRc

Not Affected

BFCRc

Not Affected

MTCRc

XXXX

Not Affected

BRCRc

XXXX

NIVRc

Uninitialized Vector

EIVRc

Uninitialized Vector

CPRc

DCRc

OCRc

SCRc

CCRc

CSRc

00 or 01

CERc

GCR

Not Affected

Channel Not Active, Interrupts Dis·
abled
(Depending on the Level of PCLc)
No Errors

X-Indicates an unknown value or the previous value of the
register.
c-is the channel number (i.e., 0,1,2, or 3)

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit
V

Supply Voltage

VCC

-0.3 to + 7.0

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature Range

Storage Temperature

o to

+70

- 55 to + 150

Tstg

V
°C
°C

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or VCC).

THERMAL CHARACTERISTICS
Value
Characteristic
Thermal Resistance (Still Air)
Ceramic, (ULC)
Plastic, (P)
Pin Grid Array (R/RC)

M68000 FAMILY
REFERENCE

Rating
IlJA

IlJC

30
30
30

15*
15*
15

°CIW

MOTOROLA
5-43

MC68450

POWER CONSIDERATIONS
The average chip-junction temperature, T J' in °c can
be obtained from:
TJ=TA+(PO·6JA)
(1)
where:
= Ambient Temperature, °C
TA
6JA = Package Thermal Resistance,
Junction-to-Ambient, °CIW
Po
= PINT+PI/O
PINT = ICC x V CC, Watts-Chip Internal Power
PliO = Power Dissipation on Input and Output
Pins-User Determined
For most applications PIIO-j

);

TxO

Transmitter
Enabled

TxROY
(SR2)

w
01

Start
Break

CTS1

Stop
Break

05 Will
Not Be
Transmitted

oPo)

RTS2

-----,.

(OPo)

rJ_
I

OPR(O) = 1

OTES:
1. Timing shown for M R2(4) = 1.
2. Timing shown for MR2(5) = 1.

Figure 10. Transmitter Timing

en
CX)

::go

mo
.,,0
m."

::gl>
m3:
Z_
Or-

m-<

QOPR(Q)= 1

::C:S:

men
-nco

mo
::Co
mo

2-n

OJ>

m:s:

RxD

-<
Receiver
Enabled

RxRDY

(SROI

FFULL
(SRll
RxRDY/

FroIT
(OP51 2

R
Status Data

" "D1
-"'
Overrun
(SR41

RTsl
(OPal

NOTES
1. Timing shown for M R1(71 = 1.
2. Shown for OPCR(41 = 1 and MR(61 =0.

o
-I
o

:::0

,?>O
Nt
wl>

Figure 11. Receiver Timing

3:
(")

en
CO
~

n
N

~-t

::a

S;
M.ot"Sta';.'
TxD

AID

I A~D I I I
; 1

c::
iI I

j I A~D ! I

AID
DO

AlD.....------.A--

Transmitter
Enabled

TxRDY
. (SR2)

W
MR1l4- 3) = 11
MR1(2) = 1

ADD1 .MR1l2l=0

MR1(2) = 1

ADD 2

RxD

Receiver
Enabled

_ _ _ _----1

RxRDY
. (SROl

R/W

13
MR1(4-3l=11

-~~

~I~
1i~
ADD1

_~tatusDat~

3:
en
:zJ~
mo
.,,0
m."
21):-

m3:

fir::

Fig':lre 12. Wake-Up Mode Timing

~
~rI--~

ADD2

MC2681

PIN ASSIGNMENTS
DUAL·IN·LlNE

vcc

RS1
39

IP3

IP4

RS2

IP5

IP1

IP6

RS3

IP2

RS4

IPO

RESET

X2
XlICLK

Vii
R

RxOB

TxOB

OP1

OP3

OP2

OP5

OP4

OP7

OP6

RxOA
TxOA
O~O

GNO

IRQ

PLASTIC LEADED CHIP CARRIER
0

8S3~~~~b~8o
~

OP6
OP4
OP2
OPO
TxOA
NC
RxOA
X1ICLK
X2
RESET

OP7
OP5
OP3
OP1
TxOB
NC
RxOB

R
Vii
IPO
RS4

I~ III '
.A

OB7·0BO

MC68652/
MC2652
MPCC

.J\.

~TxO
~RxO

A2
AD

.-TxC

R/W
CPU
&
SUPPORT
LOGIC

~RxC

OBEN
CE

OB7·0BO

CEO MC68653/
MC2653
PGC
Al

R/W
AO
CEI

iNf

(OPEN DRAIN)

(> 5 V
(>

Figure 20. MC68652/MC68653 Interface
Typical Protocols: BISYNC, OOCMP, SOLC, HOLC

M68000 FAMILY

REFERENCE

MOTOROLA
6-49

MC68652/MC2652

MC6BOOO

NC6B652
MC2652

00·D15
A1

A1
A2
+5 V

ADDRESS
DECODE

CE
AO

BYTE
As~------.--J
l~S~----'---------------~~
UDS~~--~--------------~--~

RW~~--~--------------~----------------~

~----------~

ClR

DBEN

I-----+--+-~

PRE

SN74LS74
Q

+5 V

ClK

[»

-OPEN COLLECTOR GATES

Figure 21. MC68000/MC68652 Interface Circuit

MOTOROLA
6-50

M68000 FAMILV
REFERENCE

MC68652/MC2652

00·015

AI·A23

51 52 53 54 5W 5W 5W 5W 55 56

57 50

---<'-_____

-'»)----

---<'-_____

----I»)----

V_Al_ID_ _ _ _

VA_lI_O_ _ _

R/Vi

Figure 22. MC68000 Write Cycle Timing

PIN ASSIGNMENT

CE Ie
RxC 2
Rx51 3
5/F 4
RxA 5
RxoA 6
RxSA
RxE
GNO
OB8 10
OB9 11
OB10 12
OBll 13
OB12 14
OB13 15
OB14 16
OB15 .17
R/W 18
A2 19
Al 20

M68000 FAMILY

REFERENCE

MM
TxC
Tx5Q
TxE
TxU
TxBE
TxA
RE5ET
VCC
OBo
OBI
OB2
OB3
OB4
OB5
OB6
OB7
OBEN
BYTE
AD

MOTOROLA
6-51

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68681

TechnicalSummary

Dual Asynchronous
Receiver/Transmitter (DUART)
The MC68681 dual universal asynchronous receiver/transmitter (DUART) is part of the M68000
Family of peripherals and directly interfaces to the MC68000 processor via an asynchronous bus
structure. The MC68681 consists of eight major sections: internal control logic, timing logic, interrupt control logic, a bidirectional 8-bit data bus buffer, two independent communication channels (A
and B), a 6-bit parallel input port, and an 8-bit parallel output port.
Figure 1 illustrates the basic block diagram of the MC68681 and should be referred to during the
discussion of its features which include the following:
• M68000 Bus Compatible
.
• Two Independent Full-Duplex Asynchronous ReceiverlTransmitter.Channels
• Maximum Data Transfer
lX-l MB/second
- 16X-125 kB/second
• Quadruple-Buffered Receiver Data Registers
• Double-Buffered Transmitter Data Registers
• Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable From:
- 18 Fixed Rates: 50 to 38.4k Baud
- One User Defined Rate Derived from a Programmable Timer/Counter
- External 1X Clock or 16X Clock
• Programmable Data Format
- Five to Eight Data Bits plus Parity
- Odd, Even, No Parity, or Force Parity
- One, One and One-Half, or Two Stop Bits Programmable in One-Sixteenth Bit Increments
• Programmable Channel Modes
- Normal (Full Duplex)
- Automatic Echo
- Local Loopback
- Remote Loopback
• Automatic Wake-up Mode for Multidrop Applications
• Multi-Function 6-Bit Input Port
- Can Serve as Clock or Control Inputs
- Change-of-State Detection on Four Inputs
• Multi-Function 8-Bit Output Port
- Individual Bit Set/Reset Capability
- Outputs Can be Programmed to be Status/Interrupt Signals
• Multi-Function 16-Bit Programmable CounterlTimer
• Versatile Interrupt System
- Single Interrupt Output with Eight Maskable Interrupting Conditions
- Interrupt Vector Output on Interrupt Acknowledge
- Output Port Can be Configured to Provide a Total of Up to Six Separate Wire-ORable Interrupt
Outputs

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MOTOROLA
6-52

M68000 FAMILY
REFERENCE

MC68681

DTACK

R/IN

r.s
Internal Control Logic

RESET
RS1-RS4

Timing Logic
Xl/ClK

---------+-+-----.t-----""1

X2 ------------------~----------~ ~------~

External
Interface

Processor
Interface

TxDA
RxDA
DO-D7

TxDB
RxDB
IRQ ------"1---..;;..,.:,;..;;..---{.,j
lACK

IPO-IP5
VCC-+

GND~

OPO-OP7

Figure 1.

M68000 FAMILV
REFERENCE

~Iock

Diagram

MOTOROLA
6-53

MC68681

FEATURES (Continued)
• Parity, Framing, and Overrun Error Detection
• False-Start Bit Detection
• Line-Break Detection and Generation
• Detects Break Which Originates in the Middle of a Character
• Start-End Break Interrupt/Status
• On-Chip Crystal Oscillator
• TTL Comaptible
• Single + 5 V Power Supply

INTERNAL CONTROL LOGIC
The internal control logic receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to
control device operation. It allows the registers within the
DUART to be accessed and various commands to be performed by decoding the four register-select lines (RS1
through RS4). Besides the four register-select lines, there
are three other inputs to the internal control logic from
the CPU: read/write (RNh which allows read and write
transfers between the CPU and DUART via the data bus
buffer; chip select (CS), which is the DUART chip select;
and reset (RESET),whichis used to initialize or reset the.
DUART. Output from the internal control logic is the data
transfer acknowledge (DTACK) signal which is asserted
during read, write, or interrupt acknowledge cycles.
DTACK indicates to the CPU that data has been latched
on a CPU write cycle or that valid data is present on the
data bus during a CPU read cycle or interrupt acknowledge (lACK) cycle.

TIMING LOGIC

The timing logic consists of crystal oscillator, a baudrate generator (BRG), a programmable 16-bit counter/
timer (CIT), and four clock selectors. The crystal oscillator
operates directly from a 3.6864 MHz crystal connected
across the X1/CLK and X2 inputs orfroman external clock
of the appropriate frequency con'nected to X1/CLK. The
clock serves as the basic timing reference for the baudrate generator, the counter/timer, and other internal circuits. A clock signal, within the limits given in ELECTRICAL SPECIFICATIONS, must always be supplied to the
DUART.
The baud-rate generator operates from the oscillator
or external clock input and is capable of generating 18
commonly used data communication baud rates ranging
from 50 to 38.4k by producing internal clock outputs at
16 times the actual baud rate. The counter/timer can be
used in the timer mode to produce a 16X clock for any
other baud rate by counting down the crystal clock or
external clock. Other baud rates may also be derived by
connecting 16X or 1X clocks to certain input port pins
which have alternate functions as receiver or transmitter

MOTOROLA

6-54

clock inputs. The four clock selectors allow the independent selection, for each receiver and transmitter, of
any of these baud rates.
The 16-bit counter/timer (C/T) included within the
DUART and timing logic can be programmed to use one
of several timing sources as its input. The output of the
counter/timer is available to the internal clock selectors
and can also be programmed to be a parallel output at
OP3. In the timer mode, the counter/timer acts as a programmable divider and can be used to generate a squarewave output at OP3. In the counter mode, the contents
of the counter/timer can be read by the CPU and it can
be stopped and started under program control. The
counter counts down the number of pulses stored in the
concatenation of the counter/timer upper register and
counter/timer lower register and produces an interrupt.
This is a system oriented feature which may be used to
keep track of timeouts when implementing various application protocols.

INTERRUPT CONTROL LOGIC
The following registers are associated with the interrupt control logic: interrupt mask register (lMRI. interrupt
status register (lSR), auxiliary control register (ACR), and
interrupt vector register (lVR).
A single active-low interrupt output (IRQ) is provided
which can be used to notify the processor that any of
eight internal events has occurred. The interrupt mask
register (lMR) can be programmed to select only certain
conditions which cause IRQ to be asserted while the interrupt status register (lSR) can be read by the CPU to
determine' all currently active interrupting conditions.
When an active-low interrupt acknowledge signal (lACK)
from the processor is assserted while the DUART has an
interrupt pending, the DUART will place the contents of
the interrupt vector register (lVR) (i.e., the interrupt vector) on the data bus and assert the data transfer acknowledge signal (DTACK).
In addition, the DUART offers the ability to program
the parallel outputs OP3 through OP7 to provide discrete
interrupt outputs for the transmitters, the receivers, and
the counter/timer.

DATA BUS BUFFER
The data bus buffer provides the interface between the
external and internal data buses. It is controlled by the
internal control logic to allow read and write data transfer
operations to take place between the controlling CPU and
DUART by way of the eight parallel data lines (DO through
D7).

COMMUNICATION CHANNELS A AND B
Each communication channel comprises a full-duplex
asynchronous receiver/transmitter (UART). The operating frequency for each receiver and each transmitter can
be selected independently from the baud-rate generator,
the counter/timer, or from an external clock.

M68000 FAMILY
REFERENCE

MC68681

The transmitter accepts parallel data from the CPU,
converts it to a serial bit stream, inserts the appropriate
start, stop, and optional parity bits, and outputs a composite serial stream of data on the TxO output pin. The
receiver accepts serial data on the RxO pin, converts this
serial input to parallel format, checks for a start bit, stop
bit, parity bit (if any). or break condition, and transfers
an assembled character to the CPU during read operations.

INPUT PORT
The inputs to this unlatched 6-bit port (lPO through IP5) .
can be read by the CPU by performing a read operation.
High or low inputs to the input port result in the CPU
reading a logic one or logic zero, respectively; that is
there is no inversion of the logic level. Since the input
port is a 6-bit port, performing a read operation will result
in 07 being read as a logic one and 06 reflecting the logic
level of lACK. Besides general-purpose inputs, the inputs
to this port can be individually assigned specific auxiliary
functions serving the communication channels.
Four change-of-state detectors, also provided within
the input port, are associated with inputs IPO, IP1, IP2,
and IP3. A high-to-Iow or low-to-high transition of these
inputs lasting longer than 25 to 30 microseconds (bestto-worst case times) will set the corresponding bit in the
input port change register (lPCR). The bits are cleared
when the register is read by the CPU. Also, the OUART
can be programmed so any particular change of state can
generate an interrupt to the CPU. The DUART recognizes
a level change on an input pin internally only after it has
sampled the new level on the pin for two successive
pulses of the sampling clock. The sampling clock is 38.4
kHz and is derived from one of the baud-rate generator
taps. The resulting sampling period is slightly more than
25 microseconds (this assumes that the clock input is
3.6864 MHz). Subsequently, if the level change occurs on
or just before a sampling pulse, it will be recognized
internally after 25 microseconds. However, if the level
change occurs just after a sampling pulse, it will be sampled the first time after 25 microseconds. Thus, in this
case the level change will not be recognized internally
until 50 microseconds after the level change took place
on the pin.

OUTPUT PORT
This 8-bit multi-purpose output port can be used as a
general-purpose output port. Associated with the output
port is an output port register (aPR).
All bits of the output port register can be individually
set' and reset. A bit is set by performing a write operation
at the appropriate address with the accompanying data
specifying the bits to be set (one equals set and zero
equals no change). Similarly, a bit is reset by performing
a write operation at another address with the accompanying data specifying the bits to be reset (one equals reset
and zero equals no change).

M68000 FAMILY
REFERENCE

The output port register stores data that is to be output
at the output port pins. Unlike the input port, if a particular
bit of the output port register is set to a logic one or logic
zero the output pin will be at a low or high level, respectively. Thus, a logic inversion takes place internal to
the OUART with respect to this register. The outputs are
complements of the data contained in the output port
register.
Besides general-purpose outputs, the outputs can be
individually assigned specific auxiliary functions serving
the communication channels. The assignment is accomplished by appropriately programming the channel A and
B mode registers (MR1A, MR1B, MR2A, and MR2B) and
the output port configuration register (OPCR).

SIGNAL DESCRIPTION
The following paragraphs contain a brief description
of the input and output signals.
NOTE
The terms assertion and negation will be used
extensively. This is done to avoid confusion
when dealing with a mixture of "active low"
and "active high" signals. The term assert or
assertion is used to indicate that a signal is
active or true, independent of whether that
level is represented by a high or low voltage.
The term negate or negation is used to indicate that a signal is inactive or false.
VCC AND GND

Power is supplied to the OUART using these two signals. VCC is power (+ 5 volts) and GNO is the ground
connection.
CRYSTAL INPUT OR EXTERNAL CLOCK (X1/CLK)

This input is one of two connections to a crystal or a
connection to an external clock. A crystal or a clock, within
the specified limits, must be supplied at all times. If a
crystal is used, a capacitor of approximately 10 to 15
picofarads should be connected from this pin to ground.
CRYSTAL INPUT (X2)

This input is an additional connection to a crystal. If an
external TTL-level clock is used, this pin should be tied
to ground. If a crystal is used, a capacitor of approximately 0 to 5 picofarads should be connected from this
pin to ground.
RESET (RESET)

The OUART can be reset by asserting the RESET signal
or by programming the appropriate command register.
A hardware reset, assertion of RESET, clears status registers A and B (SRA and SRB), the interrupt mask register
(lMR), the interrupt status register (lSR), the output port
register (aPR), and the output port configuration register
(OPCR). RESET initializes the interrupt vector register (lVR)
to OF16' places parallel outputs OPO through OP3 in the
high state, places the counter/timer in timer mode, and

MOTOROLA
6-55

MC68681

places channels A and B in the inactive state with the
channel A transmitter serial-data output (TxDA) and
channel B transmitter serial-data output (TxDB) in the
mark (high) state.
Software resets are -not as encompassing and are
achieved by appropriately programming the channel A
and/or B command register. Reset commands can be programmed through the command register to reset the receiver, transmitter, error status, or break-change interrupts
for each channel.
CHIP SELECT (CS)
This active low input signal, when low, enables data
transfers between the CPU and DUARTon the data lines
(DO through D7). These data transfers are controlled by
read/write (R/W) and the register-select inputs (RS,
through RS4). When chip select is high the DO through
D7 data lines are placed in the high-impedance state.

mode. (Mark is high and space is low.) Data is shifted
out this pin on the falling edge of the programmed clock
source.
CHANNEL A RECEIVER SERIAL-DATA INPUT (RxDA)
This signal is the receiver serial-data input for-channel
A. The least-significant bit is received first. Data on thl~
pin is sampled on the rising edge of the programrnE:!c
clock source.
CHANNel B TRANSMITTER SERIAL-DATA OUTPUT
(TxDB)
This signal is the transmitter senal-data output fCJ'
channel B. The least-significant bit IS transmitted first
The output is held high Imark condition) when the transmitter is disabled, idle, or operating in the local loopback
mode. Data is shifted out this pin on the tailing edge of
the programmed clock source.

READIWRITE (RtW)
When high, this input indicates a read cycle, and when
low, it indicates a write cycle. A cycle is initiated by assertion of the chip-select input.
DATA TRANSFER ACKNOWLEDGE (DTACK)
This three-state active low open-drain output is asserted in read, write, or interrupt acknowledge (lACK)
cycles to indicate the proper transfer of data between the
CPU and DUART.
REGISTER-SELECT BUS (RS1 THROUGH RS4)

CHANNEL B RECEIVER SERIAL-DATA INPUT (RxDB)
This signal is the receiver serial-data input for channel
B. The least-significant bit is received first. Data on this
pin is sampled on the rising edge of the programmed
clock source.
'
PARALLel INPUTS (lPO THROUGH IPS)
Each of the parallel inputs (IPOthrough IP5) can be used
as general-purpose inputs. However, each one has an
alternate function(s) which is described in the following
paragraphs.

The register-select bus lines during read write operations select the DUART internal registers, ports, or commands.

IPO

This input can be used as the channel A clear-tosend active low input (CTSA). A change-of-state detector is also sassociated with this input.

DATA BUS (DO THROUGH D7)

IP1

This input can be used as the channel B clear-tosend active low input (CTSB). A change-of-state detector is also associated with this input.

IP2

This input can be used as the channel B receiver
external clock input (RxCB); or the counter'timer
external clock input. When this input is used as the
external clock by the receiver, the received data is
sampled on the rising edge of the clock. A changeof-state detector is also associated with this input.

INTERRUPT ACKNOWLEDGE (lACK)

IP3

This active low input indicates an interrupt acknowledge cycle. If there is an interrupt pending (IRQ asserted)
and this pin asserted, the DUART responds by placing
the interrupt vector on the data bus and then asserting
DTACK.lf there is not an interrupt pending (IRQ negated!.
the DUART ignores the status of this pin.

This input can be used as the channel A transmitter
external clock input (TxCA). When this input is used
as the external clock by the transmitter, the transmitted data is clocked on the falling edge of the
clock. A change-of-state detector is also associated
with this input.

IP4

This input can 'be used as the channel A receiver
external clock input (RxCA). When this input is used
as the external clock by the receiver, the received
data is sampled on the rising edge of the clock.

IPS

This input can be used as the channel B transmitter
external clock (TxCB).When this input is used as
the external clock by the transmitter, the transmitted data is clocked on the falling edge of the clock.

_ These bidirectional three-state data lines are used to
transfer commands, data,and status between the CPU
and DUART. DO is the least-significant bit.
INTERRUPT REQUEST (IRQ)
This active low, open-drain output signals the CPU that
one or more of the eight maskable interrupting conditions
are true.

CHANNel A TRANSMITTER SERIAL-DATA OUTPUT
(TxDA)
This signal is the transmitter serial-data output for
channel A. The least-significant bit is transmitted first.
This output is held high (mark condition) when the transmitter is disabled, idle, or operating in the localloopback

MOTOROLA
6-56

M68000 FAMILY

REFERENCE

MC68681

PARALLEL OUTPUTS (OPO THROUGH OP7)
Each of the parallel outputs can be used as generalpurpose outputs. However, each one has an alternate
function(s) which is. described in the following paragraphs.
OPO This output can be used as the channel A active
low request-to-send (RTSA) output. When used for
this function, it is automatically negated and reasserted by either the receiver or transmitter.
OP1 This output can be used as the channel B active low
request-to-send (RTSB) output. When used for this
function, it is negated and reassert-ed automatically
by either the receiver or transmitter.
OP2 This output can be used as the channel A transmitter 1X-clock or 16X-clock output, or the channel
A receiver 1X-clock output.
OP3 This output can be used as the open-drain active
low counter-ready output, the open-drain timer output, the channel B transmitter 1X-clock output, or
the channel B receiver 1X-clock output.

OP4 This output" can be used as the channel A opendrain active-low receiver-ready or buffer-full interrupt outputs (RxRDYAlFFULLA) by appropriately
programming bit 6 of mode register 1A.
OPS This output can be used as the channel B opendrain active-low receiver-ready or buffer-full interrupt outputs (RxRDYB/FFULLB) by appropriately
programming bit 6 of mode register 1B.
OPS This output can be used as the channel A opendrain active-low transmitter-ready interrupt output
(TxRDYA) by appropriately programming bit 6 of
the output port configuration regiser.
OP7 This output can be used as the channel B opendrain active-low transmitter-ready interrupt output
(TxRDYB) by appropriately programming bit 7 of .
the output port configuration register.
SIGNAL SUMMARY
Table 1 provides a summary of all the MC68681 signals
described above.

Table 1. Signal Summary (Sheet 1 of 2)
Signal Name

Mnemonic

Pin No.

Input/Output

Active State

Power Supply ( + 5 V)

VCC

Input

High

Ground

GND

Input

Low

X1/CLK

Input

Crystal Input or External Clock
Crystal Input
Reset

RESET

Input

Chip Select

Input

Low

ReadtWrite

RtW

Input

High/Low

Data Transfer Acknowledge

Low

DTACK

Output*

Low

RS4

Input

High

RS3

Input

High

RS2

Input

High

RS1

Input

High

Bidirectional-Data Bus Bit 7

Input/Output

High

Bidirectional-Data Bus Bit 6

Input/Output

High

Bidirectional-Data Bus Bit 5

Input/Output

High

Bidirectional-Data Bus Bit 4

Input/Output

High
High

Bidirectional-Data Bus Bit 3

Input/Output

Bidirectional-Data Bus Bit 2

Input/Output

High

Bidirectional-Data Bus Bit 1

Input/Output

High

Bidirectional-Data Bus Bit 0
(Least-Significant Bit)

Input/Output

High

Interrupt Request

IRQ

Output*

Low

Interrupt Acknowledge

lACK

Input

Low

Channel A Transmitter Serial Data

TxDA

Output

Chanrlel A Receiver Serial Data

RxDA

Input

M68000 FAMILY
REFERENCE

MOTOROLA
6-57

MC68681

Table 1. Signal Summary (Sheet 2 of 2)
Mnemonic

Pin No.

Input/Output

Active State

Channel B Transmitter Serial Data

TxDB

Output

Channel B Receiver Serial Data

RxDB

Input

Parallel Input 5

IP5

Input

Parallel Input 4

IP4

Input

Parallel Input 3

IP3

Input

Parallel Input 2

IP2

Input

Parallel Input 1

IP1

Input

IPO

Input
Output**

Signal Name

Parallel Input

Parallel Output 7

OP7

Parallel Output 6

OP6

Output**

Parallel Output 5

OP5

Output**

Parallel Output 4

OP4

Output**

Parallel Output 3

OP3

Output**

Parallel Output 2

OP2

Output

Parallel Output 1

OP1

Output

OPO

Output

Parallel Output

*Requires a pullup resistor.
**May require a pullup resistor, depending upon its programmed function,

PROGRAMMING AND
REGISTER DESCRIPTION
The operation of the DUART is programmed by writing
control words into the appropriate registers. Operational
feedback is provided by way of the status registers which
can be read by the CPU. The DUART register address and
address-triggered commands are described in Table 2.
Figure 2 illustrates a block diagram of the DUART from
a programming standpoint and details the register configuration for each block. The locations marked "do not
access" should never be read during normal operation.
They are used by the factory for testing purposes.
Tables 3 and 4 are provided to illustrate the various
input port pin functions and output port pin functions
respectively.
Table 5 is provided to illustrate the various clock sources
which may be selected for the counter and timer. More
detailed information can be obtained from Table 6.
Care should be exercised if the contents of a register
is changed during receiver/transmitter operation since
certain changes may cause undesired results. For example, changing the number of bits-per-character while
the transmitter is active may cause the transmission of
an incorrect character. The contents ofthe mode registers

MOTOROLA
6-58

(MR), the clock-select register (CSR), the output port configuration register (OPCR), and bit 7 of the auxiliary control register (ACR[7)) should only be changed after the
receiver(s) and transmitter(s) have been issued software
Rx and Tx reset commands. Similarly, certain changes to
the auxiliary control register (ACR bits six through four)
should only be made while the counter/timer (CIT) is not
used (i.e., stopped if in counter mode, output and/or interrupt masked in timer mode).
Mode registers one and two of each channel are accessed via independent auxiliary pointers. The pointer is
set to channel A mode register one (MR1A) and channel
B mode register one (MR1B) by RESET or by issuing a
"reset pointer" command via the corresponding command register. Any read of write of the mode register
while the pointer is at MR1A or MR1 B switches the pointer
to channel A mode register,two (MR2A) or channel B
mode register 2 (MR2B). The pointer then remains at
MR2A or MR2B. So, subsequent accesses will address
MR2A or MR2B, unless the pointer is reset to MR1A or
MR1 B as described above.
Mode, command, clock-select, and status register are,
duplicated for each channel to provide total independent
operation and control. Refer to Table 6 for descriptions
of the register and input and output port bits.

M68000 FAMILY
REFERENCE

MC68681

=.~==:

Internal Control Logic

R"Em-

'S4'SI~
~~--------~l----~~------------~
Timing Logic

I Channel A Clock Selecl

Reglsler

i Channel B Clock SeleclReglsler wi
!.AuI,h.rvCootrolRlly,stefI4BIISI

~ Ip~~~;~~;~::, wJ!i.~~~~f:2:~, w.1
.Current Counl In Counter Mo =

"--~..---t

Open Collector OuL-tP-u-ts-_....

NOTE: Board layout should be such that the crystal and capacitorls) are as close as possible to the pins 01 the DUART to minimize stray
capacitance. Also, crystal series resistance should be less than 180 ohms

Figure 9. Clock Timing

AC ELECTRICAL CHARACTERISTIC-TRANSMITTER TIMING
(see Figure 10 and Note 1)
Characteristic
TxD Output Valid from TxC low
TxC low to TxD Output Valid

Symbol
tTxD
tTCS

Min

Max

Unit

350

150

NOTE:
1. All voltage measurements are referenced to ground (GND). For testing, all signals except Xl/ClK swing between 0.4 volt and
2.4 volts with a maximum transition time of 20 nanoseconds. For Xl/ClK, this swing is between 0.4 and 4.4 volts. All time
measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for noninterrupt outputs: Cl = 150 picofarads, Rl = 750 ohms to VCC. Test conditions for interrupt outputs: Cl = 50 picofarads, Rl = 27
kilohms to VCC'

M68000 FAMILY
REFERENCE

MOTOROLA
6-75

MC68681

TxC
(lnputl

lBitTime

i1 m

16 C"""

'------

.... i
hD

TxD

. TxC

(lX Outputl

. Figure 10. Transmit Timing

AC ELECTRICAL CHARACTERISTICS-RECEIVER TIMING
(see Figure 11 and Note 1)
Characteristics

Symbol

Min

Max

Unit

tRxS

240

tRxH

200

RxD Data Setup Time to RxC High
RxD Data Hold Time from RxC High

NOTE:
1. All voltage measurements are referenced to ground (GND). For testing, all signals except Xl/ClK swing between 0.4 volt and
2.4 volts with a maximum transition time of 20 nanoseconds. For Xl/ClK, this swing 'is between 0.4 and 4.4 volts. All time
measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for noninterrupt outputs: Cl = 150 picofarads, Rl =750 ohms to VCC. Test conditions for interrupt outputs: Cl =50 picofarads, Rl =27
kilohms to VCC.

RxC

(lX Inpull

\--~-tRxs-:.1~1~ ---1\~--'R,H

RxD ======~~~~~_-_-_-:_-_-_-_-_"""'-'~

~'-__________

Figure 11. Receive Timing

MOTOROLA
6-76

M68000 FAMILY

REFERENCE

MC68681

TxD

Transmitter
Enabled

TxRDY
(SR21

DTACKl
(Write)

CTS2
(I POI

RTS3
(OPO)

--:J

_____________________________________________________

OPR(Q)= 1
NOTES:
.1. If CS is negated within one clock cycle after
cause the transitions.
2. Timing shown for MR2(4) = 1.
3. Timing shown for MR2(5) = 1.

CS is recognized,

DTACK will not be asserted. In this case the negation of

CS will

Figure 12. Transmitter Timing

M68000 FAMILY

REFERENCE

MOTOROLA
6-77

MC68681

RxD

Receiver
Enabled

RxRDY
(SRO)

FFull
(SRl) ____~~____________~--------------~

DTACK2
(Readl
Status Data

"--'
Dl

Overrun
(SR41

RTS3
(OPO)

NOTES:
1. Shown for OPCR(4) = 1 and MRl (6) = O.
2. If CS is negated within one clock cycle after
cause the transitions.
3. Timing shown for M R1(7) = 1.

CS is

recognized, DT ACK will not be asserted. In this case the negation of

will

Figure 13. Receiver Timing

MOTOROLA
6-78

M68000 FAMILY
REFERENCE

MC68681

Master Station

AID

A/D~

llrEIl I

TxD

I
I

~~~

H~~~___~~ LTh L1-.ty-

Transmitter
Enabled

TxRDY
(SR2)

DTACKl
(Write)

Peripheral Station

AID

RxD

AID

l [ ] l IA~DH IiI

AID
I DO

I
I

Receiver
Enabled

~
MR1(4:3)=11

+J
ADD 1

AID

IA~D!lll1l
I
I

AID

!aI

1\
I
~

RxRDY
(SRO!

DTACKl

101:

Status Data

~
Status Data

ADD 2

NOTE 1: If CS is negated within one clock cycle after CS is recognized, DTACK will not be asserted, In this case the negation of
cause the transitions,

Cs will

Figure 14. Wake-Up Mode Timing

M68000 FAMILY

REFERENCE

MOTOROLA
6-79

MC68681

PIN ASSIGNMENTS
DUAL·IN·LlNE

vcc

RSI
39

IP4

IP3

RS2

IPI

lACK

RS3

IP2

IPO

RESET

R/W

X2
Xl/ClK

IP5

RxOB

RxOA

TxOB

TxOA

OPI

OP3

OP2

OP5

OP4

OP7

OP6

OTACK

OPO

05
07

GNO

06
21

IRO

PLASTIC LEADED CHIP CARRIER

Cl
.
O N " , " <0
u Z ,.... L!) M ~
Cl Cl ClCl~ Zt.:lClClClCl
(Xl

OP6
OP4
OP2
OPO
TxOA
NC
RxDA
Xl/ClK
X2
RESET
CS

OP7
OP5
OP3
OP1

TxDB
NC

RxDB
DTACK
RMi
IPO

RS4

39
40
N I:":: L!) "'" U U ~ M N ~ M
a..ua..a..
UZVla..Vla..Vl
-~-->

MOTOROLA
6-80

a:-a:-a:

M68000 FAMILY
REFERENCE

NETWORK DEVICES

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68184

Advance Information

Broadband Interface Controller (BIC)
The CMOS LSI MC68184 Broadband Interface Controller (BIC) is used in conjunction with a protocol handler such as the MC68824 Token Bus Controller to implement a broadband IEEE 802.4 Token
Bus node. The BIC handles both data manipulation and management control for R.F. transmitter
and receiver circuitry.
• Implements Digital Portion of IEEE 802.4 Broadband Physical Layer
• Provides Station Management for Physical Layer
• Supports Serial Data Rates Up to 10 Mbps
• Twenty Lines for ReceiverlTransmitter Control Including Thirteen User-Defined
• Includes Ability to Scramble and Unscramble Data
• Kicker Insertion and Deletion
• Post-Error Correction Capability
• Pseudo-Silence Deletion·
• Two Loopback Modes
• Interfaces Via a Standard Serial Interface to a Protocol Handler Either Directly or Through An
Arbitrary Length of Cable

PIN ASSIGNMENTS

TRANSMIT DISABLE

EXTERNAL LOOPBACK

RXSYMO

OUn3

RXSYMl

OUT12

RXSYM2

IMPULSEO

IMPULSEl

SMIND
RXCLK

RESET

TEST

IMPULSE CLOCK

TXCLK

CARRIER DETECT

SMREQ
TXSYM2

VDD (Vce)

VSS (GND)

VDD (Vce)

JABBER TIME OUT

VSS (GND)

FAULT DETECT

TXSYMl

LEVELO

TXSYMO

LEVELl

IN/OUTl

AGCHOLD

IN/OUT2

OUTll

IN/OUT3

ouno

IN/OUT4

OUT9

IN/OUT5

IN/OUT8

IN/OUT6

IN/OUT7

Motorola Order Number: MC68184P

This document contains information on a new product. Specifications and information herein are subject to change without notice.

M68000 FAMILY
REFERENCE

MOTOROLA MOTOROLA
7-1

MC68184

SECTION 1
INTRODUCTION
1.1 BROADBAND LOCAL AREA NETWORK OVERVIEW
A broadband network consists of a coaxial cable, a
headend remodulator, and several nodes or stations as
shown in Figure 1-1'. The purpose of the network is to
permit information to be exchanged between any two
nodes in an orderly and efficient manner. In a broadb'and system, data is transmitted in frequency channels
similar to CATV. All nodes receive on one channel called
the forward channel and transmit on another channel
called the reverse channel. The headend does the translation between the two channels. For a 10 Mbps data
rate, the two channels are each 12 MHz wide. For example, if Node A wants to send data to Node B, No'ie A
transmits the data on the reverse channel to the headend. The headend receives the data from the reverse
channel and retransmits it on the forward channel. All
the nodes receive the data on the forward channel but
Node B recognizes that the data is addressed to itself
and therefore copies the data.

In addition to translating the data, the headend also
provides the clock source for the network on the forward
channel. The clock is used to recover data from the
forward channel and also to transmit data on the reverse
channel. Therefore, data is always transmitted at the
rate determined by the headend. Because the data
received by the headend is guaranteed to be at the same
data rate as the data transmitted, the headend does not
have to do store and forward of the message. So that
all nodes can recover the clock at all titTles, the headend
must provide the clock signal at all times. This has two
influences on the network.

FIGURE 1-1 -

MOTOROLA
7-2

1) Because clock edges are derived from data edges, a
node transmitting a very long string of ones or zeros
will therefore not be providing a clock signal. The
transmitting node must therefore scramble the data
to eliminate any long string of ones and zeros. The
receiving nodes automatically unscramble the data.
See ANSI/IEEE Std 802.4-1985 and the scrambler and
kicker' inserter block descriptions (Subsections 3.2
and 3.3) for more details.
2) When no stations are transmitting, if the headend
faithfully replicated this silence, all the nodes would
lose clock synchronization. To prevent this, the headend transmits a special sequence called pseudosilence. The receiving nodes use this' sequence to
recover the clock but report it as silence.
1.2 BROADBAND NODE
A typical Token Bus Local Area Network (LAN) node
consists of a host processor, memory, Token Bus Controller (TBC), BIC and R.F. circuitry as shown in Figure
1-2. The Token Bus Controller fetches messages out of
memory, serializes them, and passes the data to the
physical layer (BIC and R.F. circuitry) to be transmitted
over the coaxial cable. When data is received from the
coaxial cable, the physical layer decodes the data, and
passes it up to the Token Bus Controller which deserializes it and places the data in memory. The BIC performs the digital functions of an IEEE 802.4 physical
layer when implementing a broadband token bus node.
The BIC provides data and control for the R.F. transmitter/receiver circuitry as well as a standard serial
interface to connect the BIC to the Token Bus Controller
(MC688241.

BROADBAND NETWORK

M68000 FAMILV
REFERENCE

MC68184

MC68000
Processor

LLC
&
Upper
System Bus
Interface

Memory

LT'
MAC
Sub-Layer

Serial

Encoder

S
t
a

M
9
m

Interface

BIC

i
0

Physical
Layer

Media
Layer

t
Token Bus Coaxial Cable
FIGURE 1-2 -

TOKEN BUS BROADBAND NODE

1.3 BROADBAND SIGNALS
When the processor wants to put a message onto the
cable, it puts the message on the transmit queue which
is located in the memory shared with the TBC. The TBC
pulls the message out of the memory, serializes it, and
outputs it to the BIC. Each bit time, the TBC can request
one of five things to be transmitted:
1) Silence. Requesting silence instructs the modem not
to output any energy onto the cable. In the network,
only one station is normally transmitting on the
reverse channel so the rest of the stations are "transmitting" silence. There is a minimum requirement
of at least two silence bits between messages to
allow the transmitter time to ramp· down and up
gracefully.
2) Pad-idle. Before each transmission some integer
number of octets (eight bits) of pad-idle are transmitted. Pad-idle is used to provide a training signal
for the headend to lock to before the actual data is
transmitted. Between consecutive messages, pad- .
idle is used to separate the messages to allow the
receiving TBC time to process the current message
before the next message comes in. Before transmitting, the BIC translates pad-idle into a repeating onezero sequence which is the proper training signal.

M68000 FAMILY

REFERENCE

At the receiver, ones and zeros are reported instead
of pad-idles.
3) Non-data. Non-datas are used to determine the start
and end of messages. The start of a message is called
the start delimiter and consists of the following eight
bits: non-data, non-data, zero, non-data, non-data,
zero, zero, zero. An end delimiter signals the end of
the message and consists of the following eight bits:
non-data, non~data, one, non-data, non-data, one,
one or zero, one or zero. The last two bits of the end
delimiter are used as status bits by the TBC. The start
and end delimiters are the only time that the TBC
will request a non-data. Therefore, non-datas from
the TBC will always come in pairs and there will
never be more than two non-datas in a row. Nondatas are also used by the BIC to create "kickers"
and "pseudo-silence." See the block descriptions for
the kicker inserter and the psuedo-silence inserter
for more details.
4) One. Ones are transmitted as part of the "information" or data part of the message (between the start
and end delimiter), as part of the end delimiter, and
as part of the pad-idle training signal. The ones in
the pad-idle can be used to lock up the AGC of the
receiver.

MOTOROLA
7-3

MC68184

5) Zero. Zeros are transmitted as part of the "information" part of the message (between the start and
end delimiter), as part of the start delimiter, and as
part of the pad-idle training signal. Zero's can also
be present in the last two bits of the end delimiter.
A message from the TBC to the BIC consists of: some
number of octets of pad-idle, a start delimiter, some
number of octets of ones and zeros - the "information," an end delimiter, followed by either pad-idle for
the next message or at least two bits of silence. With P
representing pad-idle, S silence, N non-data, a typical
message would look like:

the TBC is translated into a form which is acceptable
for the broadband network. This includes inserting any
necessary clock information.
The Decoder section accepts the encoded receiver
levels from the R.F. receiver circuitry and outputs data
to the TBC using the serial interface. LEVELO and LEVEL 1
signals are inputs from the R.F. receiver which are
encoded as shown in Table 2. The receiver must perform the opposite function as the encoder in order to
make the broadband network transparent to the TBC's.
The Station Management Interface controls the
encoder, decoder and the R.F. transmitter/receiver. This
START

SILENCE I.
PAD-IDLE
SSSSSSSS SSSSSSSS PPPPPPPP PPPPPPPP PPPPPPPP PPPPPPPP

I DELIMITER I
NNONNOOO

DATA
00001110

01010100
END

DATA CONTINUED
11111000 11001011 11111001 00000100 10101000 11101001
Before transmitting, the R.F. transmitter performs a
duo-binary AM-PSK translation on the data. Duo-binary
is a bandwidth compression technique which converts
the data into an analog waveform. At the output of the
duo-binary encoder, ones have a full amplitude, either
positive or negative, zeros have almost no amplitude,
and non-datas are at half amplitude, either positive or
negative. This analog waveform is then impressed onto
a carrier using AM-PSK modulation. With AM-PSK, the
amplitude of the carrier represents the amplitude of the
duo-binary output (Amplitude Modulation). The phase
of the carrier shows whether the amplitude is positive
or negative (Phase Shift Keying). AM-PSK puts the spectrum of the output into a frequency "channel" similar
to a TV channel. Twelve megahertz of bandwidth is
required to send data at a rate of 10 megabits per second. Two twelve megahertz channels are used, one for
the nodes to transmit to the headend (the reverse channel), and the other for the headend to transmit to all the
nodes (the forward channel). This method is similar to
cable TV (CATV) and in fact IEEE 802.4 was patterned
after CATV systems. The advantage of having the data
in a specific channel is that the rest of the cable
bandwidth is free for other uses such as video information, point-to-point modems, and other networks.
At the receiver, the data can be recovered by comparing the amplitude in the middle of the bit time
against the maximum amplitude. A maximum amplitude indicates a one, a half-amplitude is a non-data, and
very little amplitude is a zero .. Silence at the node
receiver is an error condition since the headend is supposed to be transmitting at all times. The node also
recovers the clock by sensing the transitions between
no amplitude and maximum amplitude or visa-versa.

1.4 BIC OVERVIEW
The functional block diagram of the BIC is shown in
Figure 1-3: The Encoder accepts data from the serial
interface and outputs to the R.F. transmitter using outputs IMPULSEO and IMPULSE1 encoded as shown in
Table 1 (Section 2.1.1). In the encoder, the data from

MOTOROLA
7-4

I DELIMITER I
01000011

NN1NN100

SILENCE
SSSSSSSS

interface accepts commands from the TBC and inputs
from JABBER TIME OUT, FAULT DETECT and CARRIER
DETECT to determine the proper mode of operation.
RESET is a bidirectional signal which is normally an
input from external circuitry and becomes an output
when the BIC receives a reset command from the TBC.
The R.F. transmitter/receiver is controlled using RESET,
TRANSMIT DISABLE, EXTERNAL LOOPBACK, AGC
HOLD, OUT13 to OUT9, and IN/OUT8 to IN/OUT1.

1.5 BROADBAND MODEM
The BIC provides the digital portion of the broadband
physical layer. To complete the broadband modem, the
R.F. and clock functions shown to the right of the BIC
in Figure 1-4 are required.
The duo-binary encoder uses the BIC outputs
IMPULSEO and IMPULSE1 to produce the correct analog
waveform as described in ANSI/IEEE 802.4 Std-1985,
Section 14. This analog waveform is applied to the carrier by the AM-PSK R.F. TRANSLATER. This modulated
carrier is placed on the coax cable by the power stage.
The power stage can be. disabled by the BIC output
TRANSMIT DISABLE. The R.F. receiver detects the
amplitude modulated carrier and converts it to an analog signal. The receiver reports this signal to the clock
recovery circuit which uses the transitions to recover
the clock. The data then can be recovered and put into
the BIC on LEVELO and LEVEL 1. The automatic gain
control of the receiver maintains the current gain when
the BIC output AGC HOLD is asserted. In addition, a
power-up detect circuit is required to reset the BIC at
power-up and hold the BIC in reset until ten clocks after
power becomes stable. The jabber timer is required by
ANSI/IEEE 802.4 Std-1985 to detect if the modem transmits for more than 112 second. If so, the jabber timer
asserts JABBER TIME OUT which will stop the BIC from
transmitting. The modem failure detect is optional and
asserts FAULT DETECT in case of a modem error. The
jabber timer and the modem failure detect should be
put to the inactive state by reset.

M68000 FAMILY

REFERENCE

MC68184

,---------,

TXCLK

TXSYM 1
TXSYMO

SMREQ

Encoder

Serial
Interface

Control

RXCLK

I"I"
I"
."I

RXSYM2
RXSYM1
RXSYMO
SMIND

Control

CARRIER
DETECT
RESET
TRANSMIT
DISABLE

FIGURE 1-3 -

M68000 FAMILY

REFERENCE

:
i

I
I

TX Signals

IMPULSEO
IMPULSE1

LEVELO
LEVEL 1

Decoder

RX Signals
AGC HOLD

fControl
10_
II

II
II

Station
Management
Interface

IMPULSE CLOCK

I
1

JABBER
TIME OUT

Bad Input

Data

EXTERNAL
LOOPBACK

OOPb

I" r--.

FAULT
DETECT

TXSYM2

:
II

I ..
I

II •..
i:
I•
I
I

I
I

L- _ _ _ _ _ _ _ --.JI

IN/OUT1
IN/OUT2
IN/OUT3
IN/OUT4
IN/OUT5
IN/OUT6
IN/OUT7 User
IN/OUTS Defined
OUT9
OUT10
OUT11
OUT12
OUT13
TEST

FUNCTIONAL BLOCK DIAGRAM FOR BROADBAND INTERFACE CONTROLLER

MOTOROLA
7-5

MC68184

TBC

BIC

SMREQ

IMPULSE CLOCK
IMPULSEO
TXSYM2
IMPULSE1
TXSYM1
TRANSMIT
DISABLE
TXSYMO
JABBER TIME OUT
TXCLK
FAULT DETECT
SMREQ

TXSYM2
TXSYM1
TXSYMO

TXCLK

RESET
SMIND

SMIND
RXSYM2

RXSYM2

RXSYM1

RXSYMO

RXSYMO
RXCLK

RXCLK

IN/OUT1

OUT9
OUT10
OUT11
OUT12
OUT13
EXTERNAL
LOOP
LEVELO
LEVEL1

IN/OUT2
IN/OUT3
To/From
User
Defined
Functions

R.F.

IN/OUT4
IN/OUTS
IN/OUT6

CARRIER
DETECT

Receiver

IN/OUn
IN/OUTS

FIGURE 1-4 -

MOTOROLA
7-6

AGC HOLD

PHYSICAL LAYER BLOCK DIAGRAM

M68000 FAMILY
REFERENCE

MC68184

SECTION 2
SIGNAL DESCRIPTION
The BIC signals can be broken into several groups
including the serial interface, R.F. transmitter signals,
R.F. receiver signals, and control signals. The twenty
control signals have thirteen that are user-definable.
The terms assertion and negation will be used extensively. This is done to avoid confusion when dealing
with a mixture of "active-low" and "active-high" signals. The term assert or assertion is used to indicate
that a signal is active or true, independent of whether
that level is represented by a high or low voltage. The
term negate or negation is used to indicate that a signal
is inactive or false. Positive logic is used thOroughout so
a high logic level is equivalent to a one state.
Internal pullup resistors (>100 k) are provided on
some inputs. These pullups are intended to drive the
input to a known state if the input is disconnected.
Because of the very small external drive capability
(4.0/LA), it is not recommended to use the internal
pullup resistors to drive external loads.
2.1 R.F. TRANSMITTER SIGNALS
The R.F. transmitter signals consist of IMPULSEO,
IMPULSE1, and IMPULSE CLOCK.
2.1.1 IMPULSEO AND IMPULSE1
IMPULSEO and IMPULSE1 are output signals from the
BIC encoder and pass duo-binary signals to the R.F.
transmitter circuitry with the meanings as shown in

TXCLK
Physical Data
Request Channel

Table 1. IMPULSEO and IMPULSE1 can have one of two
possible meanings depending on whether the duobinary precoder is enabled or not. See Section 3.5 on
the duo-binary precoder for more details.
TABLE 1 - ENCODINGS OF IMPULSEO AND IMPULSE1
(Duo-binary encoding defined by ANSI/IEEE Std 802.4-1985
Table 14-1)
Duo-Binary Precoder
IMPULSEO

IMPULSE1

Enabled

0
0
1
1

0
1
0
1

0
-2
+2
Silence

Disabled
Zero
One
Non-Data
Silence

2.1.2 IMPULSE CLOCK
IMPULSEO and IMPULSE1 are clocked out on the rising edge ofthe IMPULSE CLOCK. IMPULSE CLOCK must
be at the same frequency as TXCLK and is normally
either connected to TXCLK or RXCLK. As long as the
synchronizer (see Subsection 3.6 on the synchronizer)
is enabled, TXCLK, RXCLK, and IMPULSE CLOCK may
have any phase relationship. All three must be at the
exact same frequency, however.

IMPULSEO

TXSYM2

IMPULSE1

TXSYM1

IMPULSE CLOCK

TXSYMO

LEVELO

TX Signals

RX Signals

SMREQ
AGC HOLD

Physical Data
Indication Channel

RXCLK

IN/OUT1

RXSYM2

IN/OUT2

RXSYM1

MC68184

IN/OUT3

RXSYMO

IN/OUT4

SMIND

IN/OUTS
IN/OUT6

EXTERNAL LOOP

IN/OUn

JABBER TIME OUT

IN/OUT8

FAULT DETECT
Control
Signals

UserDefined
Control
Signals

OUT9

CARRIER DETECT

OUT10

RESET

OUT11

TRANSMIT DISABLE

OUT12
OUT13

POWER
FIGURE 2-1 -

M68000 FAMILY
REFERENCE

TEST
MC68184 FUNCTIONAL PINOUT

MOTOROLA

7-7

MC68184

2.2 R.F. RECEIVER SIGNALS
The R.F. receiver signals consist of LEVELO, LEVEL 1,
and AGC HOLD.

2.2.1 LEVELO AND LEVEL1
LEVELO and LEVEL 1 are input signals to the BIC
decoder from the R.F. receiver circuitry. These signals
are decoded by the BIC decoder as shown below and
are clocked in on the falling edge of RXCLK, LEVELO
and LEVEL 1 are created in the R.F. receiver by comparing the amplitude of the received signal against preset
levels. See subsection 3.10 on the error corrector for
more details.
TABLE 2 -

LEVELO AND LEVEL 1 ENCODINGS

LEVELO

LEVEL1

0
0
1
1

0
1
0
1

Encoding
Data Zero
Data One
2-0 Non-Data
2-4 Non-Data

2.2.2 AGC HOLD
The Automatic Gairi Control (AGC HOLD) pin is
negated whenever the CARRIER DETECT control pin is
negated. If the CARRIER DETECT signal is asserted, the
AGC HOLD pin will be high one "and one-half RXCLK's
after a start delimiter is presented on LEVELO and
LEVEL 1 pins. A start delimiter consists of the following
sequence of eight bits: 2-0 or 2-4, 2-0 or 2-4, data zero,
2-0 or 2-4, 2-0 or 2-4, data zero, data zero, data zero.
When the CARRIER DETECT signal is asserted, the
AGC HOLD will go low after one of the following occurs:
1) Twenty four of the same inputs are received on
LEVELO and LEVEL 1 (the encodings 2-0 and 2-4 are
considered different inputs)
2) If two, three, or four Non-Datas (2-0 or 2-4) are contained in bits positions 1, 2, 4, and 5 relative to the
start delimiter
3) If the error correcter is disabled (Bit 7 of Register 1
is set) and a Non-Data in bit positions 3, 6, 7, or 8
not belonging to a kicker is present
4) If the descrambler disable bit is set (Register 1 Bit
4), the error corrector is disabled, and a kicker is
present
5) During reset.
The following shows a start delimiter and the bit positions of a message:

non-data in these positions would be considered an
error and not be reported to the TBC. With the error
corrector disabled and noise on the cable, a non-data
could occur in any bit position and would in this case
be reported. The non-datas belonging to "kickers"
would. be eliminated as long as the descrambler is
enabled.
2.3 PHYSICAL DATA REQUEST CHANNEL
Five signals comprise the physical data request channel: TXCLK, SMREO, TXSYM2, TXSYM1, and TXSYMO.
Three of these signals (TXSYM2, TXSYM1 and
TXSYMO) are multiplexed and have different meanings
depending on the mode selected by the state of SMREO.
Internal pullup resistors (>100 kn) are also provided to
drive SMREO, TXSYM2, TXSYM1 and TXSYMO to the
high state if disconnected.

2.3.1 TXCLK
The transmit clock is an input which can be upto 10.5
MHz. TXSYM2, TXSYM1, TXSYMO and SMREO are synchronizedby the TBC to the positive edge of TXCLK.
The IEEE 802.4 standard for broadband allows 1.0, 5.0,
or 10 MHz clocks but requires TXCLK to be at exactly
the same frequency as RXCLK.
2.3.2 SMREO
SMREO indicates if the physical layer is in the MAC
mode (SMREO = 1) or in the Station Management
mode (SMREO = 0) of operation. In MAC mode, the
node is on-line and data requests and data indication
signals are passed over the serial interface. In Station
Management Mode, the node is offline and accepts station management commands from the TBC.
2.3.3 TXSYM2, TXSYM1, TXSYMO
In Management Mode TXSYM2, TXSYM1 and
TXSYMO have the meanings shown in Table 3:
TABLE 3 -

REQUEST CHANNEL MANAGEMENT MODE
ENCODING (SMREQ = 0)
State

Reset
Loopback Disable
Enable Transmitter
Serial SM Data/Idle

TXSYM2 TXSYM1 TXSYMO
1
1
0
0

1
0
1
0

1
1
1
0/1

N NON NOOO 12345678 12345678 12345678 12345678 ...
In general, AGC HOLD will go high at the start of
receiving a message and go low at the end of a message
or if an uncorrectable error occurs in the message. The
no transition detector (Subsection 3.8) performs condition 1 and essentially, conditions 2, 3, and 4 happen
whenever a non-data is reported to the TBC ..With the
error corrector (Subsection 3.10) and the descrambler
(Subsection 3.12) enabled, the only non-datas that can
be reported are those in bit positions 1,2,4,5. A single

MOTOROLA
7-8

In Management mode, the Token Bus Controller
(MC68824) can pass commands to the BIC. In addition
to the three standard commands of reset, loopback disable and enable transmitter, user generated commands
can be passed to the BIC to control or monitor the R.F.
circuitry. See Section 5 for more details on management
mode. Encodings not included in Table 3 are illegal
commands. The BIC will NAK all illegal commands but
take no other actions.

M68000 FAMILV

REFERENCE

MC68184

In MAC mode, the encodings for TXSYM2, TXSYM1,
and TXSYMO are shown in Table 4:

The encoding of RXSYM2, RXSYM1, and RXSYMO in
MAC mode are shown in Table 6:

TABLE 4 - REQUEST CHANNEL DATA MODE ENCODING
(SMREQ = 11

TABLE 6 - INDICATION CHANNEL DATA MODE ENCODING
(SMIND = 11

Symbol
ZERO
ONE
NON-DATA
PAD-IDLE
SILENCE

TXSYM2 TXSYM1 TXSYMO
0
0
1

0
0
0
1
1

0
1

*
*
*

Where
ZERO is a data zero.
ONE is a data one.
NON-DATA is a delimiter flag and is always requested
in pairs.
PAD-IDLE is one symbol of preamble/interframe idle.
SILENCE is silence or pseudo-silence.
*Don't care.
2.4 PHYSICAL DATA INDICATION CHANNEL
Five signals comprise the physical data indication
channel: RXCLK, SMIND, RXSYM2, RXSYM1, and
RXSYMO. Three of these signals (RXSYM2, RXSYMl
and RXSYMO) are multiplexed and have different meanings depending on the state of SMIND.
2.4.1 RXCLK
The receive clock can be up to 10.5 MHz. RXSYM2,
RXSYM1, RXSYMO, and SMIND are synchronized to rising edge of RXCLK. The IEEE 802.4 standard for broadband networks allows 1.0, 5.0, or 10 MHz clocks.
2.4.2 SMIND
SMIND signal indicates whether the BIC is in MAC
mode (SMIND = 1) or Station Management mode
(SMIND = 0) of operation. When in MAC mode of operation, RXSYM2, RXSYM1, and RXSYMO are encoded
indications of data reception. When in Station Management mode of operation, RXSYM2, RXSYMl and
RXSYMO are encoded to confirm response to management commands.
2.4.3 RXSYM2, RXSYM1, RXSYMO
In management mode, the encoding for RXSYM2,
RXSYM1, and RXSYMO are shown in Table 5:
TABLE 5 - INDICATION CHANNEL MANAGEMENT MODE
ENCODING (SMIND = 01
RXSYM2 RXSYM1 RXSYMO
State
NACK (non-acknowledgement)
1
0
+
ACK (acknowledgement)
0
1
+
Idle Response
1
0
0
Physical Layer Error
1
1
1
+ Indicates RXSYMO contains the SM RXdata when responding to a
serial data command.

M68000 FAMILY

REFERENCE

Symbol
ZERO
ONE
BAD-SIGNAL
NON-DATA
SILENCE

RXSYM2 RXSYM1 RXSYMO
0
0
0
1
1

0
0

1
1

Where
ZERO is a data zero.
ONE is a data one.
BAD-SIGNAL indicates lack of carrier
NON-DATA is a delimiter flag. In the absence of errors,
NON-DATAs will always be present in pairs.
SILENCE is silence or pseudo-silence.
2.5 CONTROL SIGNALS
The BIC has twenty control signals with thirteen of
these being user-defined.
2.5.1 RESET
The reset pin is a bidirectional signal which is open
drain as an output. Whenever RESETis driven low, the
BIC will reset. The reset pin must be driven· low at
power-up and held low for at least ten clock cycles after
VDD reaches recommended operation conditions. A
pullup resistor (>100 kf1) is provided to drive this pin
to the inactive state if disconnected. An external pullup
resistor of between 15 k!1 and 1.0 k!1 on the reset pin
is recommended in order to have reasonable rise times
(less than 4 clocks). In addition, when the BIC receives
a reset command from the TBC, it will drive RESET low
for as long as the reset command is asserted.
2.5.2 JABBER TIME OUT
The JABBER TIME OUT pin is an input to the BIC from
the external Jabber Timer circuitry as shown in Figure
1-4. When the JABBER TIME OUT pin is asserted, the
BIC will drive IMPULSEO and IMPULSEl high (silence
state), drive TRANSMIT DISABLE and SMIND low, and
drive RXSYM2, RXSYM1, and RXSYMO high. These pins
will continue in these states until a reset is received by
the BIC. The reset can occur by either driving the RESET
pin low or sending a reset command to the BIC. A pullup
resistor (>100 k!1) is provided to drive the JABBER TIME
OUT pin to the inactive state if disconnected.
2.5.3 FAULT DETECT
The FAULT DETECT pin operates in the same manner
as the JABBER TIME OUT pin. When the FAULT DETECT
pin is driven low, the BIC will drive IMPULSED and
IMPULSEl high, drive TRANSMIT DISABLE and SMIND
low, and drive RXSYM2, RXSYM1, and RXSYMO high.
These pins will continue in these states until a reset is

MOTOROLA
7-9

MC68184

received by the BIC. The reset can occur by either driving the RESET pin low or sending a reset command to
the BIC. An internal pullup resistor (>100 kfl) is provided
to drive the FAULT DETECT pin to the inactive state if
disconnected.
2.5.4 CARRIER DETECT
When the CARRIER DETECT pin is not asserted, it
indicates no carrier is present. This pin is driven by
external circuitry which senses when the carrier is lost
on the broadband cable. The AGC HOLD signal is driven
low when CARRIER DETECT is negated. When CARRIER
DETECT is negated and the BIC is not in internal loopback mode or in Management mode, then RXSYM2,
RXSYM1, and RXSYMO are driven to the LOW, HIGH,
HIGH states, respectively. This is the bad-signal indication. When CARRIER DETECT is negated and the BIC
is not in external loopback, then TRANSMIT DISABLE
is asserted and IMPULSEO and IMPULSE1 are driven
high (silence). An internal pullup resistor (>100 kfl) is
provided to drive the CARRIER DETECT pin to the active
state if disconnected.
2.5.5 EXTERNAL LOOPBACK
The EXTERNAL LOOPBACK pin is asserted if, since
the last reset, Bits 1 and 2 of Register 1 have been set
to 0 and 1 respectively and a loopback disable command
has not been received by the BIC from the TBC. In this
condition, the BIC is in external loopback mode.
2.5.6 TRANSMIT DISABLE
TRANSMIT DISABLE is asserted (low) by anyone of
the following conditions:
1) During a reset
2) When the transmitter is disabled as indicated by Bit
4 of Register 0
3) When SMREQ is low
4) When in internal loopback
5) When CARRIER DETECT AND EXTERNAL LOOPBACK are negated
6) When TXCLK is at zero frequency
7) When IMPULSEO AND IMPULSE1 are high
8) When a physical error is being reported (RXSYM2
= 1, RXSYM1 = 1, RXSYMO = 1 and SMIND = 0).
Whenever TRANSMIT DISABLE is asserted,
IMPULSEO and IMPULSE1 will both be forced high
.
(silence condition).
TRANSMIT DISABLE allows smooth transmitter turnon and turn-off by being negated a little before data

MOTOROLA

7-10

starts coming out of IMPULSEO and IMPULSE1 and by
being asserted a little after data stops coming out of
IMPULSEO and IMPULSE1. In particular, ten IMPULSE
CLOCKS after both IMPULSEO and IMPULSE1 go high,
TRANSMIT DISABLE will be asserted. Between four and
ten IMPULSE CLOCKS before either IMPULSEO or
IMPULSE1 go low (from the high-high or silence state),
TRANSMIT DISABLE will be negated unless some other
condition is overriding. Note that TRANSMIT DISABLE·
will be asynchronous to IMPULSE CLOCK. The exact
number of clocks depends on the mode of operation
(such as whether the synchronizer is enabled) and the
phase relationship between TXCLK and IMPULSE
CLOCK.
If TXCLK is at a zero frequency, after approximately
16 RXCLKs, TRANSMIT DISABLE will be asserted. This
is intended as a failsafe for remote systems. If the BIC
is remote from the TBC, then in order to maintain
proper timing, TXCLK is provided by the TBC -as
shown in Figure 1-4. If the cable between the BIC and
the TBC is disconnected, the TXCLK frequency will go
to zero while the RXCLK frequency, which is generated
on the modem, will remain the same. The BIC will
recognize this difference in frequency and assert
TRANSMIT DISABLE .. Note that TXCLK into the BIC
must be at a valid input level, that is, it must not
"float".
2.6 TEST SIGNAL
TEST is used during product testing and must be
held high for normal operations.
2.7 USER DEFINED CONTROL SIGNALS
2.7.1 IN/OUT1-IN/OUT8
These eight independent pins are bidirectional. Register 3E contains the state of these eight pins. Register
3F determines if these pins are inputs or outputs. Each
pin can be individually programmed as an output to
control the R.F. section as needed. As inputs, these
pins can be used to monitor the R.F. section. An internal pullup resistor (>100 kil) is provided for each INI
OUT pin.
2.7.20UT9-0UT13
These five output signals are user-defined. OUT9,
OUT10, OUT11 are driven low at reset while OUT12
and OUT13 are driven high at reset. These outputs are
controlled by Register 3D and can be used to control
the R.F. section as required.

M68000 FAMILY

REFERENCE

MC68184

SECTION 3
BIC BLOCK DESCRIPTION
3.0 DETAILED BLOCK DESCRIPTION
Figure 3-1 shows a detailed block diagram of the BIC.
The encoder includes the scrambler, kicker inserter,
pseudo-silence adder, duo-binary precoder, and the
impulse clock synchronizer. The decoder includes the
start delimiter detector, no transition detector, kicker
deleter, error corrector, pseudo-silence deleter, and the
descrambler. The station management interface
includes the command/data decoder and encoder, bad
input detector, error monitor, TXCLK alive monitor, register control, and five registers.
3.1 COMMAND/DATA DECODER
The command/data decoder interprets the commands
to the BIC and the data to be transmitted coming from
the TBC. When SMREO is low, the BIC is receiving commands as shown in Table 3 and when SMREO is high,
the BIC is receiving data as shown in Table 4.

3.1.1 DATA
Silence on SMREO, TXSYM2, TXSYM 1, TXSYMO indicates that no energy is to be transmitted. Since the
minimum number of silence bits is two, a single silence
bit is illegal. After silence must always come at least
four octets (32 bits) of pad-idle. Pad-idle is generated in
order to provide a signal for the headend to lock onto.
The data decoder translates pad-idles into a repeating
one-zero pattern. Note that the scrambler is disabled
during the ones and zeros of pad-idle but not during
the ones and zeros of a message. Following the padidle is a start delimiter. The start delimiter denotes the
start of a frame and consists of the following eight bits:
non-data, non-data, zero, non-data, non-data, zero, zero,
zero. Following the start delimiter are up to 8191 octets
of zeros or ones. This is the "information" part of the
message. Following this is the end delimiter which indicates the end of the frame and consists of the following
eight bits: non-data, non-data, one, non-data, non-data,
one, one or zero, one or zero. Non-datas are only present in the start and end delimiters, must always come
in pairs, and must have at least one data bit (zero or
one) separating each non-data pair. Following the end
delimiter is silence if this was the last frame to be transmitted, or pad-idle if another frame is to follow.
3.1.2 COMMANDS
In order to enter management mode and give a command, SMREO is brought low. This will cause the BIC
to bring SMIND low within eight RXCLKs. SMIND will
also go high within eight RXCLKs of SMREO going high
(unless a physical error indication is present). In management mode, the TBC can control and interrogate the
BIC by sending commands and by addressing registers
internal to the BIC.
3.1.2.1 RESET COMMAND
When the BIC receives a reset command from the
TBC it:

M68000 FAMILY
REFERENCE

1) Stores whether a physical error indication is being
caused by a bad input, JABBER TIME OUT, and/or
FAULT DETECT.
2) Attempts to pull the RESET pin low.
3) Initializes the register control so that the next byte
of serial station management data received will be
considered the first byte of two.
4) If a physical error indication (SMIND = 0, RXSYM2
= RXSYM1 = RXSYMO = 1) is not present, the BIC
acknowledges the reset command (SMIND =
RXSYM2 = 0, RXSYM1 = RXSYMO = 1) within eight
RXCLKs after the command is present. If a physical
error indication is present, the RESET pin must go
low before the reset command will be
acknowledged.
While the RESET pin is low, either pulled low by the
BIC after receiving a reset command or by external circuitry (such as the power up detector)' a reset occurs.
A reset has the following effects:
1) If a physical error indication is present, it is cleared.
2) All bits in Register 3F are forced low, which makes
IN/OUT1 to IN/OUT8 inputs.
3) All bits in Register 3E are forced low. Since, at reset,
IN/OUT1 to IN/OUT8 are inputs, this will have no
effect until Register 3F is changed.
4) Bits 6, 7 of Register 3D are forced high, bits 1, 2, 3,
4 5 are forced low. This will cause OUT12, OUT13
high, force OUT9, OUT10, OUT11 low and enable
the duo-binary precoder, the bad input detector, and
the impulse clock synchronizer.
5) Bits 0, 2, 3,4, 6, 7 of Register 1 are forced low and
bits 1, 5 are forced high. This selects internal loopback, enables the scrambler, kicker inserter, descram bier, kicker deleter, pseudo-silence subtracter,
error corrector and disables the pseudo-silence
adder.
6) Bits 4, 5, 7 of Register 0 are forced high and Bit 6
is forced low indicating internal loopback mode.
7) The loopback mode is enabled. Since Bits 1, 2 of
Register 1 are forced to a high, low respectively, a
reset places the BIC in the internal loopback mode.
8) The transmitter is disabled. This forces IMPULSEO,
IMPULSE1 high and TRANSMIT DISABLE low.
9) AGC HOLD is forced low (after one RXCLK low to
high transition).
10) If SMREO is high (reset was caused by an external
source pulling the RESET pin low), silence is
reported (SMIND = RXSYM2 = RXSYM1 =
RXSYMO = 1).
The. RESET pin must be driven low at power-up and
held low for at least ten clock cycles (of TXCLK and
RXCLK) after power becomes valid. During normal
operation, the RESET pin must be held low for a minimum of two clock cycles of TXCLK and RXCLK for a
valid reset to occur.

MOTOROLA
7~ 11

MC68184

SMREQ
TXSYM2
TXSYMl
TXSYMO

~------------_EXTERNALLOOPBACK

INTERNAL LOOPBACK
CARDET & EXTERNAL LOOPBACK--------i
RESET--------------~
SMREQ------------~

TRANSMIT DISABLE

TRANSMITTER ENABLE---------I

IMPULSEO

TXCLK
RESET

IMPULSEl

Binary
Precoder

PseudoSilence

Synchro-'
nizer

Error

Descrambler

Kicker
Deleter

LEVELO
LEVELl

SMIND
RXSYM2
RXSYMl
RXSYMO
RXCLK

AGC HOLD
CARRIER DETECT

IN/OUTl to IN/OUTS
FIGURE 3-1 -

3.1.2.2 LOOPBACK DISABLE COMMAND
When the BIC receives the loopback disable command (SMREO = TXSYM1 = 0, TXSYM2 = TXSYMO
= 1), it goes out of loopback mode and forces Bits 5, .
6, 7 of Register 0 low. A reset is required to bring Bit 7
of Register 0 back high. The register control is also initialized so that the next byte of serial station management data received will be considered the first byte of

MOTOROLA
7-12

BIC BLOCK DIAGRAM

two. If a physical errOr indication is not present, the BIC
acknowledges the loopback disable command SMIND = RXSYM2 = 0, RXSYM1 = RXSYMO = 1
within eight RXCLKs after the command is present.
3.1.2.3 ENABLE TRANSMITTER COMMAND
When the BIC receives the enable transmitter command, it forces Bit 4 of Register 0 low. Bit 4 of Register

M68000 FAMILY

REFERENCE

MC68184

o must be low before the TRANSMIT DISABLE

pin can
go high and before IMPULSEO or IMPULSE1 can go low.
(See signal descriptions for additional restrictions.) A
reset is required to bring Bit 4 of Register 0 back high.
The register control is initialized so that the next byte
of serial station management data received will be considered the first byte of two. If a physical error indication
is not present, the BIC acknowledges the enable transmitter command - SMIND = RXSYM2 = 0, RXSYM1
= RXSYMO = 1 within eight RXCLKs after the command
is present.
3.1.2.4 SERIAL SM DATAIIDLE COMMANDS
These commands are passed to the register control
which handles the reading and writing of the five registers as explained in sub-section 5.
3.2 SCRAMBLER
The scrambler algorith"m is described in 14.9.2.3 of
ANSI/IEEE Std 802.4-1985. The basic function is to take
the" data (consisting of only ones and zeros) in a message, divide it by the polynomial 1 +X-6+X-7, and output this result. This has two stated purposes: first, it
helps randomize the spectral components of the transmitted modulation and second, it reduces the chance
of transmitting a long string of zeros or a long string of
ones. The receiver uses one to zero or zero to one transitions to recover the clock. If a long enough string of
ones (or zeros) were allowed to be transmitted, the
receiver would lose clock and start reporting erroneous
data. Therefore, the scrambler is used to transform the
data so that most long strings are eliminated. Even after
being scrambled, however; there is still a small possibility of encountering just the right input pattern to produce a long output string of ones (or zeros). These are
handled by the kicker inserter. The scrambler is disabled
when Bit 3 of Register 1 is high (which also disables the
kicker inserter) or when transmitting pad-idles.
3.3 KICKER INSERTER
The kicker inserter compares the current octet (eight
bits) of data with the previous octet. If all the bits are
the same, that is, there are sixteen ones or sixteen zeros,
the last three bits of the current octet is replaced with
a "kicker." Notice that since a kicker consists of three
bits, the total number of bits transmitted is unchanged.
The two possibilities are:

is replaced with

11111111 11111111
11111111 111110NN

kicker

is replaced with

00000000 00000000
00000000 000001 NN

kicker

M68000 FAMILY

REFERENCE

where N indicates a non-data bit.
The end result is that after kickers are insQrted, the
maximum number of consecutive bits that can be the
same is 22. Any longer string will result in a kicker being
inserted which contains a one to zero (or a zero to one)
transition. The following shows the longest possible
output string of consecutive zeros. Notice that the maximum number of consecutive zeros with a kicker would
be 21.
10000000

00000000

00000001

The octet boundary is established at the start of the
frame by the start delimiter and is maintained throughout the frame. The kicker inserter is disabled when Bit
3 of Register 1 is high (which also disables the scrambler) or when transmitting pad-idles.
3.4 PSEUDO-SILENCE ADDER
The pseudo-silence adder, if enabled, will replace
silence with pseUdo-silence. Pseudo-silence is the
repeating sequence: non-data, non-data, zero, one. The
pseudo-silence adder is used in loopback to simulate
one ofthe headend functions. Normally, when the headend detects that no station is transmitting, it transmits
pseudo-silence. This guarantees that the receivers will
always have a clock signal (either valid signals or
pseudo-silence) and can therefore have very long lockup times. When the BIC is in internal loopback, the
pseudo-silence adder can be enabled in order to test
the pseudo-silence subtracter. In externalloopback, the
pseudo-silence adder acts like the head end so that a
receiver with long lock-up times can be tested under
"normal" conditions. The pseudo·silence adder is disabled when Bit 5 of Register 1 is high. It is also disabled
when in reset, when not in external or internalloopback,
and when SMREO is low if in internal loopback. When
in internal loopback and the pseudo-silence adder' is
disabled, such as after a reset, any silence sent to the
BIC will be returned as non-data.
3.5 DUO-BINARY PRECODER
The duo-binary precoder does the translation
described in Table 14-1 of ANSI/IEEE Std 802.4-1985. Its
inputs are zero, one, non-data, silence and its outputs
are 0, + 2, - 2, silence. A + 2 output tells the duo-binary
encoder (external to the BIC) to output a positive
impulse. A - 2 output indicates a negative impulse, a 0
output indicates no impulse, and silence indicates that
the transmitter is to be turned off.
The duo-binary precoder formats the data for the
external duo-binary encoder. In order to create a waveform of the correct amplitude, the duo-binary encoder
adds the current amplitude to the amplitude of the previous bit. Therefore, the precoder must change the data
to a form where this addition will produce the correct
output. The terminology used is that a one, which is a
maximum amplitude, either positive or negative, is a + 4

MOTOROLA
7-13

MC68184

or a - 4. A non-data, which is ha If amplitude either
positive or negative, is a + 2 or a - 2. A zero, which is
almost no energy, is a O. In order to create a one, if the
previous output of the precoder was a + 2, the current
output should be a + 2. These add to produce the +4.
If the previous output was a - 2, the current output
should be a - 2 which makes a - 4. In order to create
a zero, if the previous output was a + 2, the current
output should be a - 2 to add up to O. If the previous
'output was a - 2, the cu rrent output shou Id be a + 2.
Creating non-datas is a little more difficult. Non-datas
can only be output in pairs. The first non-data is created
by outputting a O. Since the previous output was either
a + 2 or a' - 2, this makes either a + 2 or a - 2, respectively. The second non-data is created by outputting a
+ 2 or a - 2. Either will add with the 0 to create a + 2
or - 2 respectively. The choice of either a + 2 or a - 2
in this case is not random. The second non-data must
be the same output as the bit prior to the first 'non-data.
The following example shows the input to the duobinary precoder and the corresponding output:
input S S S S
output- ' S S S' + 2

3.6 IMPULSE CLOCK SYNCHRONIZER
. The impulse clock synchronizer' is used if IMPULSE
CLOCK is not externally connected to TXCLK. IMPULSE
CLOCK must always be' at the exact same frequency as
TXCLK,(except when in internal loopback) but the
impulse clock synchronizer permits IMPULSE CLOCK to
have an arbitrary phase relation to TXCLK. An example
of where the impulse clock synchronizer would be used
is if RXCLK is externally connected to IMPULSE CLOCK.
Since RXCLK is used to generate TXCLK, they are
always at the same frequency. However." because of
buffer and signal path delays, the phase relationship of
TXCLK and RXCLK may hot be known.
The impufse clock synchronizer is a FIFO with TXCLK
being used to write data to the FIFO and IMPULSE
CLOCK being used to read the data from the FIFO.

MOTOROLA

3.7 START DELIMITER DETECTOR
The start delimiter detector looks at LEVELO and
LEVEL 1 to determine if a start delimiter has been
received., The output of the start, delimiter detector,
SDFOUND, is ANDed with CARRIER DETECT to produce

0 1 0
0 1 0 N NON N' 0 0 0
- 2 - 2 +2 +2 - 2 - 2 +2 0 +2 - 2 0 - 2 +2 - 2 +2 +2

As shown above, input silence is changed to output
silence except for the first and last silence in a string of
silences. The last silence (which comes right before
transmitting) is changed to an output + 2. The first
silence is changed to an output O. These are required
to "ramp" the transmitter up and down by starting and
stopping all transmissions with a non-data. The duobinary precoder will give an incorrect output if silence
is immediately followed ,by non-data. Silence should
always be followed by pad-idle (or equivalent data).
The precoding functions ,(described above) will not
be performed when the precoder is disabled, which is
when Bit 0 of Register 3D is set or when in internal
loopback. Instead, the duo-binary precoderoutputs will
be the same as the inputs with one exception. The last
silence will be changed to a data one which provides a
ramp-up function.

7,-14

Because the FIFO is of very limited length, it is important
that TXCLK and IMPULSE CLOCK be at the same frequency to prevent an underrun or overrun. The impulse
clock synchronizer is reset on the low to high transition
of SMREQ. Therefore, in order to initialize correctly, the
management state should be entered after power-up
and before the first data transmission.
The impulse clock synchronizer is used when in internalloopback to synchronize data from TXCLK to RXCLK
and so should not be disabled. When not in internal
loopback, the impulse clock synchronizer should only
be disabled if TXCLK is connected to IMPULSE CLOCK.
The impulse clock synchronizer is disabled when Bit 2
of Register 3D is high.

1 S S S

+2 +2 0 S S

AGC HOLD. SDFOUND is forced low after anyone of
the following occurs:
1) 24 of the same input are received on LEVELO and
LEVEL 1 (see no transition detector 3.8)
2) If a non-data is present at the descrambler output
3) If not in internal loopback and CARRIER .DETECT
goes low
4) During reset
Typically, SDFOUNDwili be hig h after a start delimiter
is found and low when the, non-data's in the following
end delimiter are encountered. When low, SDFOUND
disables those functions that are only to be performed
on the data section of a message - the kicker deleter,
error corrector, and the descrambler. When high,
SDFOUND disables th~ pseuqo-silence subtracter.
In internalloopback SDFOUND is not affected by CARRIER DETECT. Therefore, if SDFOUND is high and the
BIC is in internal loopback, AGC HOLD will follow the
state of CARRIER DETECT. If not in internal loopback,
AGC HOLD will go low when CARRIER DETECT goes
low and will not go high until CARRIER DETECT goes
high and another start delimiter is found (in that order).

3.8 NO TRANSITION DETECTOR
The no transition'detector looks ,at LEVELO and
LEVEL 1 to determine if the same input has been present
for 24 clocks. (The encodings 2-0 and 2-4 are considered
different inputs.) If so, a reset command is given to the
start delimiter, detector which forces AGC HOLD low.
Forcing the AGC HOLD output low will correct the most
probable cause of error, the external automatic gain
control in the receiver being held at the wrong level.
Note: because of the kicker inserter on the transmitter,
the receiver is guaranteed that in the absence of errors
there will never be more than 22-bits of the same input.

M68000 FAMILY

REFERENCE

MC68184

3.9 KICKER DELETER
The kicker deleter looks at LEVELO and LEVEL 1 and
removes any kickers that are present. This is the inverse
of the function of the kicker inserter. The kicker deleter
is disabled when SDFOUND is low or if Bit 4 of Register
1 is high (which also disables the descrambler). If the
kicker deleter is disabled and a kicker is present in the
message, SDFOUNDwili go low once the start delimiter
detector sees the kicker. This will enable the pseudosilence subtracter which can cause the corruption of the
end delimiter. For this reason, it is not recommended
to disable the pseudo-silence subtracter except for testing purposes.

If the error corrector is not needed, it can be disabled
by setting Bit 7 of Register 1 high. If the error corrector
is disabled, only the no transition detector makes any
distinction between a non-data 2-0 and non-data 2-4 on
LEVELO, LEVEL 1.
3.11 PSEUDO-SILENCE SUBTRACTER
When the headend detects that no station is transmitting, instead of repeating the silence, the headend
transmits pseudo-silence. Pseudo-silence consists of
the repeating sequence: non-data (2-0 or 2-4), non-data
(2-0 or 2-4), data zero, data one. This sequence can be
terminated at any' time and followed by data. The
pseudo-silence subtracter replaces pseudo-silence with
silence to make the pseudo-silence insertion (by the
headend) transparent to the TBC. The pseudo-silence
subtracter is disabled when a frame is being received
on LEVELO and LEVEL 1, that is, when SDFOUND is high.
The pseudo-silence subtracter is also disabled when Bit
6 of Register 1 is high. When enabled, the pseudosilence subtracter will:

3.10 ERROR CORRECTOR
The error corrector attempts to correct errors in transmission to improve the bit error rate of the receiver.
This is done by knowing what patterns of data's and
non-data's are valid in a message. The error corrector
can only be enabled when SDFOUND is high. Because
SDFOUND is only high after a start delimiter, only data
and the end delimiter should be present when the error
corrector is enabled. Therefore, any non-datas that are
not part of the end delimiter are errors that should be
converted to datas. As shown below, a bit that is
reported as a 2-4 (non-data) that should really be a data
is much more likely to have been a one than a zero.
Therefore, the error corrector will change invalid 2-4s
to data ones and invalid 2-0s to data zeros.
Maximum

Z"o Ampl;,"d,

2-4
. 2-0

M68000 FAMILY

REFERENCE

,
.

. . . • . ..Data Zero

This technique assumes that the error was caused by
a small amount of noise which pushed the, data out of
its normal range into the nearest non-data range. In
order to determine if a non-data. is part of an end delimiter or not, four rules are used: (See 2.2.2 AGC HOLD
for bit positions.)
1) Non-datas in bit positions 3, 6, 7, 8 can never be part
of an end delimiter so always convert them to datas.
2) There must be four non-datas in bit positions.1, 2,
4, 5 to make an end delimiter so if there is only one
non-data in these bit positions, make that non-data
into a data.
3) If there are three non-datas in bit positions 1, 2, 4, 5
, then an end delimiter probably had one of its nondatas converted by noise to a data so the error corrector converts the data into a non-data.
4) If two or four non-datas are present in bit positions
1, 2, 4, 5 the error corrector does nothing. Note that
in cases 3 and 4, two or four non-datas will pass by
the error corrector; which will reset the start delimiter detector; which will disable the error corrector
(until the next start delimiter is found).

NN01
NNOO
NN10
N101
N010

to
to
to
to
to

SSSS;
SSSS;
SSlO;
S101 ;
S010;

where N represents non-data (2-0 or 2-4) and S represents silence.

AmplitUde~ Data One

Half Amplitude

SUen"

change
change
change
change
change

3.12 DESCRAMBLER
The descrambler performs the opposite function of
the scrambler. Therefore, data that is scrambled and
unscrambled is identical to the original data. This means
that, in the absence of errors, the scrambling and descrambling of the data is transparent to the user (TBC).
The descrambler is disabled when SDFOUND is low or
if Bit 4 of Register 1 is set (which also disables the kicker
deleter).
3.13 BAD INPUT DETECTOR
The bad input detector looks for an invalid sequence
of data from the TBC (on SMREQ, TXSYM2, TXSYM1,
TXSYMO). The possible invalid sequences are:
1) A single non-data. That is,a non-data preceded and
followed by data or silence or preamble. Non-datas
are always supposed to come in pairs.
2) Three consecutive non-datas. There must always be
at least one data between non-data pairs. Note: The
output of the BIC to the RF transmitter could have
four consecutive non-datas, if a kicker is inserted
immediately prior to the end delimiter.
3) A single silence. In broadband systems, a minimum
of two silences are required in order to correctly
ramp down and ramp up. See the duo-binary precoder (3.5) description for more details on first and
last silence.
When an invalid sequence is detected, it is reported
to the error monitor. The bad input detector is disabled
when Bit 1 of Register 3D is high. When the bad input

MOTOROLA
7-15

MC68184

detector is disabled, Bit 2 of Register 0 will be low after
a reset command.
Q

3.14 ERROR MONITOR
Three sources of errors are possible, a fault in the
modem, a jabber time out, and a bad input sequence
from the TBC. The error monitor controls the reporting
of these errors. FAULT DETECT is an input that is generated by an external modem failure detect circuitry and
when activated, indicates that a failure has occurred and
transmission should stop. JABBER TIME OUT is generated by an external jabber timer and when activated,
indicates that the transmitter has been continuously
putting out energy (transmitting) for approximately 1/2
second. The jabber timer is required by the ANSI/IEEE
Std 802.4-1985 so that a modem will automatically shut
itself off if its transmitter is "stuck on." Lastly, the bad
input indication is generated internally as described
previously.

When ;FA-=-:"':U"""LT=-"""'D""'E=T=E"""C=T goes low, the error monitor
forces a physical error indication, that is, SMIND is
forced low and RXSYM2, RXSYM1, RXSYMO are forced
high. In addition, in order to stop transmission, TRANSMIT DISABLE is forced low and IMPULSEO, IMPULSE1
are forced high. The error monitor will maintain this
state until a reset occurs, even if FAULT DETECT goes
high. Typically, the physical error indication will cause
the TBC to interrupt the host processor. The host processor can then execute an error recovery program. The
error recovery program would give a reset command
to the BIC, read Register 0 to determine what the error
was, and then decide whether to continue or to stop all
transmissions. When the BIC receives the reset command from the TBC; it pulls the RESET pin low. This
resets the BIC and should also reset the external modem
failure detector (and the jabber timer), forcing FAULT
DETECT (and JABBER TIME OUT) high.
When a reset command is received by the BIC from
the TBC, the error monitor will save whether the FAULT
DETECT pin has gone low (in Bit 1 of Register 0) since
the last reset. After the reset, Bit 1 of Register 0 will be
set if the FAULT DETECT pin was the cause of the physical error indication. Figure 3-2 shows how the information is stored. Since this bit is unaffected by the reset
pin, before the first reset command is received by the
BIC this bit has no meaning. If the FAULT DETECT pin
is permanently held low, the BIC will hold the physical
error indication until a reset occurs which will override
FAULT DETECT. Therefore, if the FAULT DETECT pin is
held low and a reset command is given to the BIC, the
BIC will pull the RESET pin low, overriding the FAULT
DETECT, and then give an acknowledgement to the
reset command (SMIND = RXSYM2 = 0, RXSYM1 =
RXSYMO = 1) while holding IMPULSEO, IMPULSE1 high
and TRANSMIT DISABLE low. When the reset command
goes away, the BIC will release the RESET pin. When

MOTOROLA
7-16

Bit 1. Register 0

To Error Monitor

Reset Command from TBC

=
FIGURE 3-2 -

FAULT DETECT INPUT

the RESET pin goes inactive, a physical error will again
be generated by the error monitor. Note that, in this
case, (FAULT DETECT is always low) it is impossible for
the TBC to read any of the registers on the BIC.
The JABBER TIME OUT pin acts identically to the
FAULT DETECT pin except that Bit 0 of Register 0 is
used instead of Bit 1 to indicate that the external jabber
timer was the cause of the error.
When the bad input detector indicates a bad input,
the error monitor forces a physical error indication,
forces TRANSMIT DISABLE low, and forces IMPULSEO,
IMPULSE1 high. When a reset command is received,
the error monitor saves (in Bit 2 of Register 0) whether
a bad input was present. Reset clears the bad input
detector but does not affect Bit 2 of Register O. Therefore, Bit 2 of Register 0 has no meaning before the first
reset is received by the BIC.
The FAULT DETECT, :"":JA:;';B~B;""E=R"-:T=IM'"""'"=E-=O"""U=T, and the bad
input are independent errors. Therefore, if a physical
error indication is present, then at least one ofthe errors
has occurred but possibly two or even all three could
have happened. This will be indicated in bits 0, 1, 2 of
Register 0 if a reset command is used to clear the physical error indication. External circuitry can be used to
clear a physical error indication by asserting the RESET
pin. In this case, however, bits 0, 1,2 of Register 0 will
not reflect the current cause of the physical error
indication.
3.15 REGISTER CONTROL
The register control is used to read and write the five
registers (Register 0 is read only). In order to write (or
read) a register, two octets of serial station management
data are sent to TXSYMO while SMREQ, TXSYM2,
TXSYM1are held low. The BIC responds to each octet
on the TXSYM pins with an octet on the RXSYM pins.
The first octet to the BIC (on TXSYMO) defines which
register is to be written (or read) and whether a write
or a read is to be performed. The BIC responds to this

M68000 FAMILV

REFERENCE

MC68184

by repeating the same octet on RXSYMO. The format of
the first octet is:
start bit

six bit address
LSB
MSB

don't care bit

read/write bit

The start bit is a zero and the stop bit is a one. Following the register address is a don't care bit. The BIC
does not use this bit but the current IEEE 802.4 recommendation defines this bit as low. Following the
don't care bit is the read/write bit. The read/write bit is
high if a read is to be performed and low if a write is
to be performed. The second octet to the BIC (on
TXSYMO) contains the data to be written to the selected
register. The format of the second octet is:
start bit

bit position 0, bit position 1, ... , bit position 7

If a read function is being performed, the second octet
contains no useful information but is a place holder to
tell the BIC when to respond with the second octet. The
BIC responds to receiving the second octet by transmitting the contents of the selected register on
RXSYMO. In the case of a write, the register is first written and then the contents of the selected register are
transmitted. A write to Register 0 is interpretted the
same as a read to Register O. If the selected register is
not one of the five supported by the BIC, the second
octet from the BIC (on RXSYMO) will contain the contents of Register O.
In order to determine the start bit and stop bit of the
octets, the following ordering is used. Before an octet
is presented to the BIC (on TXSYMO), the TBC can generate any number of "idle requests" (SMREQ =
TXSYM2 = TXSYM 1 = 0, TXSYMO = 1). The TBC then
generates a start bit (SMREQ = TXSYM2 = TXSYM1
= TXSYMO = 0), eight data bits (SMREQ = TXSYM2
= TXSYM1 = 0, TXSYMO = datal. and a stop bit
(SMREQ = TXSYM2 = TXSYM1 = 0, TXSYMO = 1).
This must be followed by idle requests until the BIC has
put the stop bit of the response octet on the RXSYM
pins.
When the BIC receives an idle request, it generates
an "idle response" (SMIND =:' RXSYM2 = RXSYM1 =
0, RXSYMO = 1). The idle response is overridden by a
response octet as described below.
In response to an octet (first or second) from the TBC,
the BIC will:
1) Approximately six clocks after the stop bit (of the
octet from the TBC), the BIC will bring RXSYM1 high
and RXSYM2 low if the selected register is valid
(acknowledgement) or bring RXSYM2 high and
RXSYM1 low if the selected register is invalid (nonacknowledgement). RXSYM2, RXSYM1 are held in
one of these states until after the stop bit has been
sent.
2) Five RXCLKs later, the BIC will bring RXSYMO low
for one bit to create a start bit.

M68000 FAMILY
REFERENCE

3) The eight data bits of the response octet are then
presented on RXSYMO, LSB first.
stop bit

4) RXSYMO is then held high for one bit to create a stop
bit.
5) The idle response is then given as long as the idle
request is present.
In order to determine which octet of two that the BIC
is receiving, it uses the following algorithm: The BIC
will always expect the first octet after receiving a reset
command, a loopback disable command, an enable
transmitter command, or after SMREQ has been high.
stop bit
After receiving the first octet, the BIC will expect the
second unless one of the above occurs. If the first octet
selects an invalid register, the BIC will give a nonacknowledgement while transmitting the first octet to
the TBC. The BIC will then be expecting the second octet
(unless one of the above occurs first). When the BIC
receives the second octet, it will again give a nonacknowledgement and will transmit the contents of
Register 0 with the non-acknowledgement.
Note that when writing to a register, some bits may
not read the same as written. Except for the following
cases, this would be an error. All of Register 0 and Bit
o of Register 1 are read only and are not affected by an
attempt to write to them. (Bit 0 of Register 1 is not used
and is always read as low.) Also, any bits in Register
3E that are inputs (as defined by Register 3F) will show
the state of the respective IN/OUT pin, not what is written. When in internal loop back the duo-binary precoder
is always disabled. Therefore, Bit 0 of Register 3D will
always read high when in internal loopback. Since
errors due to noise are possible, it is recommended that
after writing to a register, several reads be performed
to verify the contents.
3.16 LOOPBACK MODES OF OEPRATION
Two loopback modes, internal loop back and external
loopback, provide a method to test the BIC and the
modem. Internalloopback is used to test the connection
to the BIC and most of the encoder and decoder of the
BIC.

3.16.1 INTERNAL LOOPBACK
Internalloopback is entered if a loop back disable command has not been received since the last reset and
Bits 1, 2 of Register 1 are high, low respectively. After
a reset, the BIC goes to internal loopback mode.
When in internal loopback, the BIC:
1) Forces high Bits 5 and 7 of Register 0 and Bit 6 of
Register 0 low.
2) Forces TRANSMIT DISABLE low. This, in turn, will
force IMPULSEO, IMPULSE1 high.

MOTOROLA

7-17

MC68184

3) Disables the duo-binary precoder which forces Bit 0
of Register 3D low. The decoder can not interpret
the output of the precoder so it must be turned off.
This means the duo-binary precoder is not tested in
internal loopback mode.
.
4) Disables the pseudo-silence adder while SMREQ is
low.
5) Disconnects IMPULSE CLOCK from the impulse clock
synchronizer and connects RXCLK instead. This
means that RXCLK can have an arbitrary (but constant) phase relationship with TXCLK but the synchronizer must not be disabled in internal loopback.
6) Disables the no transition detector.
7) Allows SDFOUND to go high, even if CARRIER
DETECT is low. This permits the testing of the descrambler, error corrector, and the kicker deleter. Note
that AGC HOLD will still go low if CARRIER DETECT
is low.
Note that in internal loopback, if the pseudo-silence
adder is disabled, silence on the TXSYM pins is translated to non-data on the RXSYM pins (after the encoder
and decoder delays).

3.16.2 EXTERNAL LOOPBACK
External loopback is used to test the modem circuitry
external to the BIC. External loopback is entered if a
loopback disable command has not been received since
the last reset and Bits 1, 2 of Register 1 are low, high
respectively.
When in external loopback, the BIC:
1) Asserts the EXTERNAL LOOPBACK pin.
2) Forces Bits 6 and 7 of Register 0 high and Bit 5 of
Register 0 low.
3) CARRIER DETECT negated does not assert TRANSMIT DISABLE or bring IMPULSEO, IMPULSE1 high
when in external loopback.
3.16.3 INVALID LOOPBACK
If Bits 1, 2 of Register 1 are high-high or low-low and
a loop back disable command has not been received
since the last reset command, then the BIC is in neither
internal loopback or external loopback. In this case, the
effect is the same as if loopback was disabled.

SECTION 4
BIC REGISTERS

Five registers are present in the BIC. All registers are
read/write except Register 0 which is a read only register. Bit 0 is the LSB for all registers and therefore is
the first bit transmitted on. the serial SM commands.

Before the first reset command is given, (after
the BIC is powered up). this bit has no meaning.
CABLE FAILURE. This bit indicates the inverse of
the state of the Carrier Detect pin.
TRANSMIT DISABLE. This bit indicates that the
transmitter has been disabled (by reset) when
high.
INTERNAL LOOPBACK. This bit indicates that the
BIC is currently in internal loopback state when
high.
EXTERNAL LOOPBACK. This bit indicates that the
BIC is currently in external loopback state when
high.
LOOPBACK ENABLE. This bit indicates thatloopback has been enabled by a reset when high. If
this bit is high and neither internal loopback or
external loopback is high, the BIC will take no
action.

CF
TD

4.1 REGISTER 0
Register 0 is an8-bit, read-only register with the following format:

JTO

MF I JTO I

JABBER TIME OUT. This bit indicates the JABBER
TIME OUT pin was active (low) prior to the last
reset command from the TBC when high. Before
the first reset command is given (after the BIC is
powered up), this bit has no meaning.
MODEM FAILURE. This bit indicates the FAULT
DETECT pin was active (low) prior to the last reset
command from the TBC when high. Before the
first reset command is given, (after the BIC is
powered up). this bit has no meaning.
INPUT FAILURE. This bit indicates the bad-input
detector (from the encoder). received an invalid
state prior to the last reset command from the
TBC when high. If the bad-input detector is disabled, this bit will be low after a reset command.

MOTOROLA
7-18

o
EL

4.2 REGISTER 1
Register 1 is an 8-bit read/write register with the following format:
7

.
5

I ECD I PSD IpSA I DD

LS2

0
LS1

M68000 FAMILY
REFERENCE

MC68184

NOT USED. Read always as zero. Should always
be written as zero.
LS1& LOOPBACK SELECT 1 AND LOOPBACK SELECT
LS2 2. These bits determine which loopback state to
go into when loopback is enabled as shown in
the table below:

LOOPBACK
SELECT 1

LOOPBACK
SELECT 2

0
0
1
1

0
1
0
1

DD
PSA

PSD

ECD

Mode
None
External Loopback
Internal Loopback
None

SCRAMBLER DISABLE. This bit disables the
encoder scrambler and the kicker inserter when
high.
DESCRAMBLER DISABLE. This bit disables the
descrambler and kicker deleter when high.
PSEUDO-SILENCE ADDER DISABLE. This bit disables the pseudo-silence adder in the encoder
when high. The pseudo-silence adder only operates when the BIC is in either internal loopback
or external loopback mode.
PSEUDO-SILENCE SUBTRACTER DISABLE. This
bit disables the pseudo-silence. subtracter in the
BIC decoder when high.
ERROR CORRECTOR DISABLE. This bit disables
the BIC decoder error corrector when high.

4.3 REGISTER 3D
Register 3D is an 8-bit read/write register which can
disable functions of the BIC as well as control the state
of the five user-defined output pins. Register 3D has the
following format:
765432
013
DBD

BID
SYD
09

010

012

011

010

I SYD I

0
BID

I DBD I

DUO-BINARY DISABLE. This bit disables the duobinary precoder when high. The duo-binary precoder is automatically disabled when in internal
loopback. In internal loopback, this bit is always
low.
BAD INPUT DISABLE. This bit disables the bad
input detector in the BIC encoder when high.
SYNCHRONIZER DISABLE. This bit disables the
IMPULSE CLOCK synchronizer when high.
OUT9. This bit controls the state of OUT9. Wnen
this bit is read, it indicates the actual TTL state
of OUT9 and not the requested state. A reset
forces OUT9 low.
OUT10. This bit controls the state of OUT10.
When this bit is read it indicates the actual TTL
state of OUT10 and not the requested state. A
reset forces OUT10 low.

M68000 FAMILY

. REFERENCE

011

OUT11. This bit controls the state of OUT11.
. When this bit is read it indicates the actual TTL
state of OUT11 and not the requested state. A
reset forces OUT11 low.
012 OUT12. This bit controls the state of OUT12.
When this bit is read it indicates the actual TTL
state of OUT12 and not the requested state. A
reset forces OUT12 high.
013 OUT13. This bit controls the state of OUT13.
When this bit is read it indicates the actual TTL
state of OUT13 and not the requested state. A
reset forces OUT13 high.
4.4 REGISTER 3E
Register 3E is an 8-bit read/write register which allows
the control bits to be read or written. When read, this
register always indicates the actual TTL state of the IN/
OUT1 to IN/OUT8 pins. Writing to a bit of Register 3E
that has been defined as an input by the respective IN/
OUT DIRECTION bit in Register 3F does not affect what
is read. However, it will change the pin state when
changed to an output. IN/OUT1 is the LSB of Register
3D and therefore is the first bit transmitted on serial SM
commands to/from the TBC.
4.5 REGISTER 3F
Register 3F is an 8-bit read/write register which determines if the IN/OUT pins are being read from or written
to. Reset forces IN/OUT DIRECTION1 to IN/OUT
DIRECTION8 bits low defining IN/OUT1 to IN/OUT8 as
inputs.
4.6 REGISTER RESET CONDITIONS
A reset has the following effects on the BIC registers:
1) All eight bits of Register 3F are forced low which
makes IN/OUT1-IN/OUT8 inputs.
2) All eight bits of Register 3E are forced low.
3) Bits 6 and 7 of Register 3D are forced high and Bits
5 to 0 are forced low. This forces OUT13 and OUT12
high and OUT11, OUT10, and OUT910w at reset and
enables the duo-binary precoder, the bad input
detector and the synchronizer.
4) Bits 5 and 1 of Register 1 are forced high and Bits 7,
6,4, 3, and 2 are forced low. This forces the internal
loopback mode with the pseudo-silence adder
'disabled.
5) Bits 7, 5, and 4 of Register 0 will be forced high and
Bits 6 will be forced low which enables loopback and
disables the transmitter.
4.7 PROGRAMMING CONSIDERATIONS
To have the BIC operate as expected, some care must
be taken when writing the software that provides management of the BIC.
1) After power-up, and before transmitting on the network, the TBC must enter management mode at least
once. This is required in order to reset the synchronizer. This is normally not a problem because man-

MOTOROLA

7-19

MC68184

agement mode must be entered to disable loopback
mode, enable the transmitter, etc. (Note that at
power-up, the BIC must receive a reset in order to
put it in a known condition.)
2) When a physical error occurs, the BIC will indicate
it to the TBC on the serial interface. The TBC will then
1if enabled) interrupt the processor. The interrupt
routine must provide some sort of error recovery.
There are three types of errors: jabber time out, fault
detect, and bad input. The interrupt routine should
first give a reset command to the BIC so the type of
error can be determined. Bits 0, 1, 2 of Register 0
will then indicate whether the error was a jabber time
out, fault detect, and/or bad input, respectively. A
jabber time out error happens when the transmitter
has been on longer than the protocol will allow (1/2
second). This can happen because of a hardware
fault in the modem, a hardware fault in the TBC, or
a software problem in the TBC. The last can occur,
for example, if one of the data buffers on the transmit
queue has been linked back to itself. A reset of the
TBC might be required to reinitialize the queues. As
with all of these errors, the error recovery routine
could keep track of the error as to cause and' how
many so that corrective action can take place. If a
jabber time out keeps reoccurring, the system should
stop transmitting and report the failure. The fault
detect failure is a hardware failure in the modem.
Depending on what type of failure is indicated, the
modem mayor may not be able to recover by being
reset. The bad input error indicates that the TBC gave
an incorrect input to the BIC. This could be caused
by a hardware error or by noise on the serial interface
between the TBC and the BIC. Since noise is much
more likely, resetting the BIC and reprogramming it
should be sufficient.
3) BITS 0, 1, 2 of Register 0 are different from the rest
of the bits in the BIC because they do not indicate
the current condition of the BIC, but the prior history.
These bits are not valid until a reset command is
given to the BIC. As stated above, after a reset command, these bits indicate the source(s) of an error,
if any,and are used to track down the error problem.
More than one bit can be high at a time, indicating
that more than one error condition occurred since
the last reset. It is not possible in this case to determine which error occurred first;
4) When giving a reset command to the BIC, some
guidelines are necessary. The BIC will drive it's
RESET pin low when it receives the reset command.
The BIC will not completely reset itself until .the
RESET pin goes low (for two clocks). The loading on

MOTOROLA
7-20

the RESET pin should be kept to less than 50 pF and
12 mA so that the normal reset command used by
the TBC will be sufficient. Secondly, after the reset
command, the BIC is not ready forthe next command
until the RESET pin has gone high. If a 15 kn or less
resistor is used as a pullup on the RESET pin, a waiting period is not required after the reset command.
If a large external load is present on the RESET pin,
or a larger value resistor is used, it becomes necessary to wait before giving the next command after
every reset command to the BIC.
5) Register 3D is used to program the outputs OUT9,
OUT1 0, OUT11, OUT12, and OUT13. When writing
to Register 3D, the state requested is first put on the
pins. Then the actual state of the pins is read and
returned to the TBC. If there is a discrepancy between
what is written and what is read, it could be caused
by either noise on the serial interface or a hardware
failure in the modem. To eliminate the noise problem, the register should be read several times and
the results compared. If this does not clear up the
problem, several writes (with several reads per write)
should be attempted. If incorrect data is still read
back, then a hardware error is likely.
6) When programming the BIC, in several cases what
is read will not correspond to what is written. For
example, Register 0 is read only. Therefore, a write
to Register 0 is seen the same as a read by the BIC.
Register 3E, when read, will always indicate the true
(TTL) state of the IN/OUT1 to IN/OUT8 pins. What is
written is the state the output pins will go to. Register
3F controls which pins are inputs and which pins are
outputs. Therefore, when writing to Register 3E, you
should compare what is read back but mask out the
bits that ARE inputs, which are the bits that are low
in Register 3F. After a reset, IN/OUT1-IN/OUT8 are
all inputs. If some or all of IN/OUT1-IN/OUT8 are to
be outputs, it is recommended to first write to Register 3E the state that the output is to go to~ What is
read back will not correspond to what is written and
should be ignored. Then Register 3F should be written to make outputs where needed. At this point,
Register 3E should be read to make sure the outputs
are in the correct state. Bit 0 of Register 1 is currently
not used and will read as a zero. It is recommended
that writes to Register 1 always contain zero in Bit
position O. Bit 0 of Register 3D (DBD) will read as a
zero when in internal loopback. If a one is written to
DBD and then internal loopback mode is disabled,
DBD will then indicate a one when read.

M68000 FAMILY

REFERENCE

MC68184

SECTION 5
SERIAL INTERFACE
The BIC serial interface consists of ten signals (TXCLK,
TXSYM2, TXSYM 1, TXSYMO, SMREQ, RXCLK,
RXSYM2, RXSYM1, RXSYMO, and SMIND) as shown in
Figure 5-1. The serial interface has two modes of operation, MAC mode and Station Management Mode. In
MAC mode of operation, this interface provides a means
for the Token Bus Controller to transfer requests for data
transmission and for the BIC to indicate data reception.
In Station Management Mode of operation, the serial
interlace allows the TBC to reset the BIC, enable the
transmitter, disable loopback, and read and write the
BIC internal registers.

TXCLK
TXSYM2.
TXSYM1.
TXSYMO

FIGURE 5-2 -

TRANSMISSION ON SERIAL INTERFACE

RXCLK

TXCLK
SMREQ
TXSYM2

RXSYM2.
RXSYM1.
RXSYMO

TXSYMl
TXSYMO
'IJIC68184

MC68824
RXCLK
SMIND
RXSYM2

..
FIGURE 5-1 -

MAC Mode

RXSYMl
RXSYMO

SERIAL INTERFACE

5.1 PHYSICAL DATA REQUEST CHANNEL
In MAC operation mode, the physical data request
channel provides encoded requests for data unit transmission. Figure 5-2 shows the signals on the physical
data request channel during data transmission. SMREO
goes high indicating MAC mode and TXSYM2, TXSYMl
and TXSYMO indicate the Physical symbol encodings
shown in Table 4.
5.2 PHYSICAL DATA INDICATION CHANNEL
In MAC operation mode, the physical data indication
channel provides encoded indications of data unit
reception. Figure 5-3 shows the signals on the physical
data indication channel during reception of data. SMIND
goes high indicating MAC mode and RXSYM2, RXSYMl
and RXSYMO indicate the Physical symbols encodings
shown in Table 6.
5.3 PHYSICAL LAYER MANAGEMENT
In Station Management mode, commands are sent to
the BIC from the Token Bus Controller and confirmations of those commands are sent back to the Token
Bus Controller. Valid commands for the request channel
are RESET, LOOPBACK DISABLE, ENABLE TRANSMITTER, and SERIAL SM DATA/IDLE as shown in Table 3.

M68000 FAMILY
REFERENCE

Management Mode

FIGURE 5-3 -

RECEPTION ON SERIAL INTERFACE

The following is a typical station management
sequence which could be used to place the BIC in external loopback mode.
1) First a reset command is issued on the physical data
request channel.
2) Within eight RXCLKs, the BIC will respond to the
reset command with an ACK on the physical data
indication channel. As shown in Table 5, an ACK has
SMIND low, RXSYM2 low, and RXSYMl high. Since
the reset command is not a serial data command,
RXSYMO is high.
3) Next, an idle request (SMREO asserted, TXSYM2
negated, TXSYMl negated and TXSYMO asserted)
is given on the physical request channel. Since there
is never a stiHt bit (TXSYMO low), no serial SM data
is transferred. See the next section for more details
on serial SM data.
4) Within eight RXCLKs, the BIC will respond to the idle
request with an idle response (SMIND asserted,
RXSYM2 negated, RXSYMl negated and RXSYMO
asserted) on the physical indication channel.
5) An ENABLE TRANSMITTER COMMAND is given on
the request channel. This is necesary to enable
IMPULSEO and IMPULSE1 and before TRANSMIT
. DISABLE can be negated.
6) Within eight RXCLKs, the BIC gives an ACK response.
Once again, RXSYMO is high because ENABLE
LOOPBACK is not a serial SM command.

MOTOROLA

7-21

MC68184

Idle Request

First
Command

Idle Response

Idle Request

Second
Command

Idle Response

FIGURE 5·4 -

STATION MANAGEMENT ISM) RESET AND
LOOPBACK SEQUENCE

7) An idle request is again given on the request channel.
8) Within eight RXCLKs, the idle response is given on
the physical data indication channel.
9) Register 1, is then written to, so that Bits 1 and 2 are
low, high respectively. This is done using serial SM
commands described below.
5.4 STATION MANAGEMENT COMMANDS AND
RESPONSES
When the serial interface is in statio'n management
mode, the serial SM data command (TXSYM2 = 0,
TXSYM1 = 0) is used to send data to the Physical Layer.

MOTOROLA
7-22 .

Data is sent via TXSYMO. TXSYMO = 1 is used as a
data "one" and as a stop bit. TXSYMO = 0 is used as
a start bit and as a data "zero."
When TXSYM2 and TXSYM1 are negated, TXSYMO
is typically asserted first. This is an idle request until
TXSYMO is negated. A start bit is formed when TXSYMO
is negated for the first time. The next eight bits on
TXSYMO, following the start bit, is the first octet of a
two octet "command." TXSYMO is then asserted for one
bit to produce a stop bit. TXSYMO should remain
asserted until the response is complete on the physical
data indication channel. The BIC will respond to the

M68000 FAMILY
REFERENCE

MC68184

original idle request with an idle response as decribed
previously. After the BIC receives the start bit, eight data
bits, and the stop bit, it will continue to give the idle
response for approximately six RXCLKs, and then will
either assert RXSYM2, and negate RXSYMl (NACK) or
will negate RXSYM2 and assert RXSYMl (ACK). Five
RXCLKs later, RXSYMO will be negated for one bit to
provide a start bit, following the start bit will be eight
data bits on RXSYMO; RXSYMO will then be asserted
for one bit to produce the stop bit, RXSYM2 and
RXSYMl will be negated after the stop bit producing
an idle response.
After the first octet, a second octet is transferred to
complete the command. See 3.15 Register Control for
more details on the format of the first and second octets.
After receiving the first octet, the BIC will be expecting
the second octet of data. If, before receiving the second
octet, SMREQ is negated or a valid command (reset,
loop back disable, transmitter enable) is present, then
the BIC will go back to expecting the first octet.

Figure 5-5 shows the case of a serial SM data command, a write to Register 3D, being issued on the
request channel to the BIC. This figure does not show
the 5 to 6 clock delay between the end of the command
and the start of the response. The 6 bit address for
Register 3D is 111101. Since the least significant bit of
the address is sent first, the address field is 101111. The
format of the SM data command octet is: start bit = 0,
6 bit address = 101111, don't care bit = 0, read/write
bit equal 0 and stop bit = 1. The first octet plus the start
and stop bits is 0101111001. Within 5 to 6 clocks, the
BIC will respond to the command with either an ACK
or NACK. After the ACK to the SM data command, the
data indication channel repeats the data sent to the BIC.
In this example, the second octet sent will control
OUT9, OUT10, OUT1 1 and OUT12 to set these outputs
to 1101, respectively. The data word 0001 1010 is passed
with the least significant bit first. Adding the start and
stop bits to the data gives 0000110101.

TXCLK

_______________________________________________________________
TXSYM2r--lL-__________________________________________________________________
SMREQr--l~

TXSYMl r--l~____________~----~--------------------------------~------------TXSYMOL--J~-----~~----~~r---------------------------------------

Idle

First Octet, Write to
Register 3D

RXCLK
SMINDI~------------~

RXSYM211j"______________
RXSYMl
RXSYMO I

Idle Request

________________________________________________________

~============================r=::::::::::::::::::::::=l===
L-~
ACK to First Octet, Repeat
of DatCl

L..r"LJ

Idle

TXCLK

SMREQ~I____________~~--------------------------------------------------~--~
______________________________________________________________________

TXSYM21~

TXSYMl
TXSYMO

I~::::~--------;:::~~~~:::::::::::::::::::::::::::::::::::::::::::::::
r----l'---_____r---u--u
Second Octet, Data
= 58

Idle Request

RXCLK ...JU
____________________________________________________________

SMIND~I

________

RXSYM2~1----------------------------~==============================~--~
RXSYMl
______________________________
~I

Idle Response

FIGURE 5-5 -

M68000 FAMILY
REFERENCE

'--____---'~

RXSYMO I

ACK to Second Octet, Data After
Writing = 58

STATION MANAGEMENT SEQUENCE

MOTOROLA
7-23

MC68184

SECTION 6
, ELECTRICAL SPECIFICATIONS
This section contains electrical specifications and
associated timing information. All voltages are referenced to VSS. This device contains circuitry to protect
the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal pre-

cautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high
impedance circuit. For proper, operation it is recommended that Yin and Vout be constrained to the range
VSS :s; (Yin or Vout) :s; VDD.

6.1 ABSOLUTE MAXIMUM RATINGS
Parameter

Symbol

Value

Unit

VDD

-0.5 to 7.0

Vin, Vout

-0.5 to
VDD + 0.5

DC Supply Voltage
DC Input, Output Voltage

DC Current Drain Per Pin, Any Input or Output
Storage Temperature
Lead Temperature (10 second soldering)

Tstg

-65 to + 150

°C

300

°C

6.2 RECOMMENDED OPERATING CONDITIONS (to guarantee functionality)
Parameter

Symbol

Min

Max

Unit

VDD

3.0

6.0

DC Supply Voltage
Input Voltage, Output Voltage

VDD

-40

+85

°C

Vin' Vout

Operating Temperature

6.3 DC ELECTRICAL CHARACTERISTICS (Note: CARRIER DETECT, JABBER TIME OUT, RESET, FAULT DETECT are CMOS
level inputs and all others are TTL

VOO

25°C
Typical

-40 to +85°C
Guaranteed
Limit

4.5
5.5

2.4
2.9

3.15
3.85

VIL

4.5
5.5

1.8
2.2

1.35
1.65

Minimum High-Level Input Voltage, TTL input.

VIH

4.5
5.5

1.6
1.6

2.0
2.0

Maximum Low-Level Input Voltage, TTL input.

VIL

4.5
5.5

1.2
1.2

0.8
0.8

Minimum High-Level Output Voltage
(Vin = VIH or VIL, lout = - 20 p.A)

VOH

4.5
5.5

4.499
5.499

4.4
5.4

Minimum High-Level Output Voltage
(Vin = VIH or VIL, lout = -4.0 mA)1

VOH

4.5

4.0

3.7

Maximum Low-Level Output Voltage
(Vin = VIH or VIL, lout = 20 p.A)

VOL

4.5
5.5

0.001
0.001

0.1
0.1

Maximum Low-Level Output Voltage
(Vin = VIH or VIL, lout = 4.0 mA)1

VOL

4.5
5.5

0.2
0.2

0.4
0.4

Maximum Input Leakage Current, No Pull-Up Resistor
(Vin = VDD or VSS)

lin

5.5

±0.0001

±1.0

p.A

Maximum Input Current, with Pull-Up Resistor
(Vin = VSS)

lin

5.5

-45

p.A

Minimum Input Current, with Pull-Up Resistor
(Vin = 2.0 V)

lin

4.5

-4.0

p.A

Maximum Output Leakage Current,
Three-State Output = High Impedance
(Vout = VDD or VSS)

IOZ

5.5

±5.0

p.A

Symbol

Minimum High-Level Input Voltage, CMOS input.

VIH

Maximum Low-Level Input Voltage, CMOS input.

Parameter

±0.05

Unit

(continued)

MOTOROLA
7-24

M68000 FAMILY
REFERENCE

MC68184

6.3 DC ELECTRICAL CHARACTERISTICS -

(continued)

Parameter
Maximum Ouiescent Supply Current
(Vin = VOD or VSS, lout = 0 /lA, Clocks

0 MHz)

Maximum Supply Current
(Vin = VDD or VSS, lout

10 MHz)

0/lA. Clocks

Maximum Input Capacitance 2
Maximum Output Capacitance 3
Maximum 1/0 Capacitance 4
Power Dissipation, Clocks

10 MHz

-40 to +85°C
Guaranteed
Limit

Unit

Symbol

VOO

25°C
Typical

1000

5.5

0.025

0.65

IDO

5.5

Cin

CliO

Cout

5.5

0.3

0.14

1. Iioutl equals 20 rnA for TXDISP and AGC HOLD. 12 rnA for OUT12 and OUT13 and RESET, 8.0 rnA for EXTERNAL LOOPBACK
2. RXSYMO. RXSYM1, RXSYM2, SMIND, RXCLK, TEST, TXCLK. SMREQ. TXSYM2. TXSYM1, TXSYMO. IMPULSE CLOCK. CARRIER DETECT. JABBER
TiME"ODT. FAULT DETECT, LEVELO, LEVEL1
3. TRANSMIT DISABLE. EXTERNAL LOOPBACK. IMPULSEO. IMPULSE1. AGC HOLD
4. IN/OUT1.IN/OUT2.IN/OUT3.IN/OUT4.IN/OUTS.IN/OUT6.IN/OUT7.IN/OUT8. OUT9. OUT10. OUT11. OUT12. OUT13. RESET

6.4 AC ELECTRICAL CHARACTERISTICS (Output Load equals 0 pF to 50 pF)
Number
. (See Figures
6-2.6-3)

Characteristic

Symbol

Min

Max

Unit

RXCLK. TXCLK. IMPLUSE CLOCK frequency

10.5

MHz

RXCLK. TXCLK. IMPULSE CLOCK period

tcp

TXCLK, RXCLK. IMPULSE CLOCK width high

tCWH

TXCLK, RXCLK, IMPULSE CLOCK width low

tCWL

TXCLK, RXCLK, IMPULSE CLOCK rise/fall time

tCRF

RXSYM2, RXSYM1, RXSYMO, SMIND delay time

tRXD

SMREO, TXSYM2, TXSYM1, TXSYMO setup time

tTXSU

SMREO, TXSYM2, TXSYM1, TXSYMO hold time

tTXHT

5.0

LEVELO and LEVELl setup time

tLSUT

LEVELO and LEVELl hold time

tLHT

ns
ns
ns

USER 1/0 delay from serial interface

tllOO

2.0

2.0+ 70 ns

TXCLKs

IMPULSEO, IMPULSEl delay time

tlMD

5.0

JABBER TIME OUT, FAULT DETECT width low

tJFWL

RESET minimum width low

tRWL

2.0

CLKs

6.5 THERMAL INFORMATION
ROJA = 45°CIW (Max)
TJ = TA + (PO x ROJA)
Po = (VOO x 100) + Pia

Where Pia is the Po on pins (user determined) which
can be neglected in most cases, e.g., when TA = 85°C
and Po = 0.3 Watts; TJ is calculated to be 99°C.

M68000 FAMILY
REFERENCE

MOTOROLA
7-25

MC68184

RXCLK

SMIND,
RXSYM2, - - -.....
RXSYM1, _ _ _J
RXSYMO

r--i----_II_-----''' ,.-----.....,. -----

'--+-___- t l ' -_ _ _ _ _J

LEVELO, ---,Jt-----~

'-_ _ __

,._----.....,. ,._--.....;..--"" ,.----

LEVELl --~'l'"--------Jr'------FIGURE 6-1 -

'- _ _ _ _ _J

'-_____

.1 '-_ _ __

SERIAL INTERFACE RECEIVER TIMING

TXCLK

SMREQ,
TXSYM2, - - - - l l - - " " 1,;-----"'"""'\1 ,._----.....,. _ - - - - - " "
TXSYM1.
TXSYMO - - - - l l - - J

OUTS-

IN~~~l~

1 ' - - - - - - - ' 1 "'-_ _ _ _~ _ _ _ _ _.....J

---ll---~~

,.
.
I

~r--------------

--------------------

IN/OUTB
FIGURE 6-2 -

SERIAL INTERFACE TRANSMITTER TIMING

IMPULSE
CLOCK

--V

x____

_ _ _b--

IMPULSEO,
IMPULSE1 - - "......._ _ __

_ _ _---J

"'"FA
...U
......L"""'T'""D=E""TE"""'C'=T,
JABBER TIME OUT

FIGURE 6-3 -

MOTOROLA
7-26

IMPULSE OUTPUTS AND FAULT INPUTS

M68000 FAMILY

REFERENCE

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68185

Product Preview

Twisted-Pair Modem
The MC68185 twisted-pair modem (TPM) chip is used in conjunction with the MC68824 token bU's
controller (TBC), an RS485 transceiver, and twisted-pair media to implement a very low-cost token
bus node. The TPM interfaces to the TBC via the IEEE 802.4 recommended exposed DTE-DCE interface, thus providing physical layer management, including media access control (MAC) symbol en'
coding/decoding at data rates up to 2 Mbps.
The MC68185 provides the following features:
• Implements Manchester, Differential Manchester, or Level Encoding
• On-Chip Clock Recovery without External Components
• Interfaces to the MC68824 TBC via IEEE 802.4 Recommended Exposed DTE-DCE Interface
• Physical Layer Management Includes Local Loopback Mode, Transmitter Enable, and Reset
• Supports Data Rates up to 2 Mbps
• Supports Dual Media for Redundant Applications
• On-Chip Jabber-Inhibit Timer for 1 or 2 Mbps Data Rates
• Noise Reduction for Received Data
• External Clock Rate from dc to 2 MHz
• Crystal Oscillator to Generate a Transmit Clock (3 kHz to 2 MHz)
• Low-Power CMOS
• 44-Lead PLCC Package

PIN ASSIGNMENT
-

<:>

:E:E
1~1n
:E
~ou8
~ozzzuxxu:Ex

1n1n

XXt!lwwZa:a:zena:

vee

GND
NC
SEL
RSELA
RSELB
INA
SILA
NC
ACTA
aUTA
VCC

RCLK
GND
NC
LBKEN
RESET
TSXYMI
TSXYM2
VCC
TXSYMO
SMREQ

CD CD u ICD CD -' u ICD I- ::..: ILl..
I-I-Z-'ZWZ«::>-'LI..
g~
Ci5-~
ci~~O
en
Z

This document contains information on a new product. Specifications and information herein are subject to change without notice.

M68000 FAMILv'
REFERENCE

MOTOROLA MOTOROLA
7~27

MC68185

GENERAL DESCRIPTION
As a part of Motorola's token bus node, shown in Figure 1, the TPM provides a very low-cost local area network
solution. The twisted-pair modem chip, with the RS485 drivers and receivers, performs the functions of the physical
layer of the seven-layer open system interconnect (OS I) network model, using twisted-pair wires for the media. The
TPM modulates the data transmission to the twisted-pair bus, receives and demodulates data from the bus, and manages
the physical layer upon request by the TBC. The RS485 drivers and receivers translate the TPM TIL levels to and from
RS485 levels.
Station management commands are passed from the TBC over the IEEE 802.4 recommended exposed DTE-DCE
interface to the TPM. The management commands provide the ability to reset the TPM, to select the transmitters and
receivers for redundant configuration, and to enable a local loop back mode for testing. An on-chip timer provides a
jabber-inhibit function to turn off the transmitter and report an error condition if the transmitter is on beyond a user·
specified time. A digital filter mode aids the bit integrity of the incoming data.

TWISTED-PAIR BUS

Figure 1. Token Bus Node

MOTOROLA

7·28

M68000 FAMILY
REFERENCE

MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC68194

Technical Summary

Carrierband Modem (CBM)
The bipolar LSI MC68194 Carrierband Modem (CBM) when combined with the MC68824 TokenBus Controller provides an IEEE 802.4 single-channel, phase-coherent carrierband LAN connection.
The CBM performs the Physical Layer function including symbol encoding/decoding, signal transmission and reception, and physical management.
Features include:
• Implements IEEE 802.4 Single-Channel, Phase-Coherent FSK Physical Layer Including End-ofTransmission Receiver Blanking
• Provides Physical Layer Management
• Supports Data Rates from 1 to 10 Mbps -IEEE 802.4 Standards use 5 or 10 Mbps
• Interfaces via Standard Serial Interface to MC68824 Token-Bus Controller
• Crystal Controlled Transmit Clock
• Local Loopback Mode for Testing
• Recovery of Clocked Data through Phase-Locked Loop
• Adjustable Signal-Detection Threshold
• RC Controlled Jabber-Inhibit Timer
• Single + 5.0-Volt Power Supply

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA _
M68000 FAMILY
REFERENCE

MOTOROLA
7-29

MC68194

.. GENERAL DESCRIPTION
The MC68194 Carrierband Modem (CBM) is part of
Motorola's solution for an IEEE 802.4 token bus
carrierband LAN node. The CBM integrates the function
of the single-channel phase-coherent FSK physical layer.
Figure 1 illustrates the architecture of a token bus LA!';
node as commonly used in MAP industrial communications. Based on the 150-051 model shown in Figure 2,
the LLC Sublayer and additional upper layers are typically
supported by a local MPU SUbsystem, while the IEEE
802.4 token bus MAC Sublayer and Physical Layer are
implemented by the MC68824 Token-Bus Controller (TBC)
and MC68194 CBM respectively.
The MC68194 provides the three basic functions of the
physical layer including data transmission to the coax
cable, data reception from the cable, and management
of the physical layer. For standard data mode (also called
MAC mode). the carrierband modem receives a serial
transmit data stream from the MC68824 TBC (called sym-

bois or atomic symbols), encodes, modulates the carrier,
and transmits the signal to the coaxial cable. Also in the
data mode, the CBM receives a signal from the cable,
demodulates the signal, recovers the data, and sends the
received data symbols to the TBC. End-of-transmission
receiver blanking as required by IEEE 802.4 is supported.
Communication between the TBC and CBM is through a
standardized serial interface consistent with the IEEE 802.4
DTE-DCE interface.
The physical layer management provides the ability to
reset the CBM, control the transmitter, and do loopback
testing.AlsQ, an on-board RC timer provides a "jabber"
inhibit function to turn off the transmitter and report an
error condition if the transmitter has been continuously
on for .too long. Similar to the data mode, the CBM
management mode makes use of the TBC serial interface.
The CBM uses phase-coherent shift keying (FSK) modulation on a single channel system. In this modulation
technique, the two signaling frequencies are integrally
related to the data rate, and transitions between the two

MC6BOOO
PROCESSOR

I ~

SYSTEM
BUS
INTERFACE

LCC
&
UPPER

...

MEMORY

TOKEN BUS
CONTROLLER

MC68824

SERIAL INTERFACE

\ ~

MODULATORI
TRANSMITIER

S
T
A
T
I
0
N

LT"

DEMODULATORI
RECEIVER

MC68194

PHYSICAL
LAYER

M
G
M
T

•

TOKEN BUS COAX

MOTOROLA
7-30

Figure 1. Token Bus Node

M68000 FAMILY
REFERENCE

MC68194

APPLICATION

!z
w

PRESENTATION

:::I:

SESSION

C!l

~
<

TRANSPORT

:::I:

i5
i=

NETWORK

r.n

DATA LINK

PHYSICAL

LOGICAL LINK
CONTROL SUBLA YER

IEEE 802.2

MEDIA ACCESS
CONTROL SUBLA YER

MC68824
TOKEN BUS
CONTROLLER

PHYSICAL LAYER

MC68194
CARRIERBAND
MODEM

Figure 2. OSI Model

signaling frequencies are made at zero crossings of the
carrier waveform. Table 1 shows the data rate and signaling frequencies. An {l} is represented as one-half cycle
of a signal, starting and ending with a nominal zero
amplitude, whose period is equal to the period of the
data rate, with the phase of one-half cycle changing at
each successive ill. An {H} is represented as one full cycle
of a signal, starting and ending with a nominal zero
amplitude whose period is equal to half the period of the
data rate. In a 5 Mbps implementation. the frequency of
{l} is 5 MHz and for {H} is 10 MHz. For a 10 Mbps implementation, the frequency of {l} is 10 MHz and for{H} is
20 MHz. The other possible physical symbol is when no
signal occurs for a period equal to one half of the period
of the data rate. This condition is represented by {off}.
Table 1. Data Rate vs Signaling Frequencies

Data Rate
Mbps

Frequency of
Lower Tone MHz
lL}

Frequency of
Higher Tone MHz
lHI

5.0

10.0

20.0

The specified physical symbols ({l}, {H}, and {off}) are
combined into pairs which are called MAC-symbols. The
MAC-symbols are transferred across the serial link. The
encodings for the five MAC-symbols are shown in Table
2. Figure 3 shows the phase coherent FSK modulation
scheme for ONE, ZERO, and NON-DATA. The IEEE 802.4
document does not specify the polarity used to transmit
data on the physical cable. The receiver must operate
without respect to polarity.
Figure 4 illustrates the functional blocks of the CBM
and peripheral circuitry required for an IEEE 802.4 carrierband 5 Mbps or 10 Mbps data rate phase-coherent

M68000 FAMILY

REFERENCE

Table 2. MAC Symbol Encodings
MAC-Symbol

Encoding

SILENCE

I OFF OFF:

PAD-IDLE PAIRS

ILL II H H I

ZERO

I HHI

ONE

ILL I

NON-DATA
ND1
ND2

IHLI
lLHl

FSK physical layer. A number of passive components
directly support CBM operation to set the jabber inhibit
timer and data recovery timing. In addition. an external
crystal or clock source is required (20 MHz for 5 Mbps
data rate or 40 MHz for 10 Mbps data rate). The receive
clock recovery is based on a phased-locked loop which
uses an active filter with an external op amp.
For the coaxial cable interface. the CBM can directly
receive the filtered signal from the cable, meeting the
IEEE 802.4 requirement of a 4 dB to 10 dB (1 mV. 75
[dBmVJ threshold window. The receive threshold is
trimmable if desired by the user. For signal transmission,
the CBM provides a set of differential transmit outputs
(ECl signals referenced to VCC, i.e., logic high = 4.1 V
and logic low = 3.3 V) and a TX disable signal. The IEEE
802.4 requires a + 63 dBmV to + 66 dBmV transmit level
and as a result an amplifier with waveshaping is required.
Typically. an RF transformer is used for connection to the
cable.
Although primarily intended for the IEEE 802.4 carrierband, the CBM is also an excellent device for point-topoint data links, fiberoptic modems, and proprietary LANs.
The MC68194 can be used over a wide range of frequencies and interfaces easily into different kinds of media.

MOTOROLA
7-31

MC68194

ONE

ZERO

NON-DATA
PAIR

1 BIT TIME

BIT TIME

Figure 3. Phase-Coherent FSK Modulation Scheme

SERIAL INTERFACE
The serial interface is composed of the physical data
request channel and the physical data indication channel.
Five signals comprise the physical data request channel
including TXSYMO, TXSYM1, TXSYM2, TXCLK, and

MOTOROLA
7-32

SMREQ. The physical data indication channel is composed of RXSYMO, RXSYM1, RXSYM2, RXCLK, and
SMIND. The serial interface is used to pass commands
and data frames between the TBC and the CBM. This
interface is based on the IEEE 802.4 DTE-DCE interface.

M68000 FAMILV
REFERENCE

:CS:

men
mo
mo

"'00

AMPLIFICATlDN
AND
WAVESHAPING

:Co

TXDIS

RESET

2."

-- -

OJ>

ms:
~

DATA CDMMANDS

SERIAL
INTERFACE
DECDDER
A
STATION
XCLK . . ~ MANAGEMENT
COMMANDS

:TALI

JL
~.T
=-XTAL2
I1IND
;YM2
;YMI
R ;YMO
TOIS

- ......

D-

XCLK

TRANSMIT
MODULATOR

RECEIVE I
DEMODULATORj.;..

+
ONE SHOT

JAB-RC

•

RECEIVE
AMPLIFIER
AND SQUELCH

D
VCM-C2

f I~II..

RXIN1~

I · -=

"F"" CONNECTOR

-t;

RXIN

lii2\
FILTER

-< •
-<
-<

FDBK
THRESHOLD
-, GAIN
- HYST

CARRIER
DETECT

CLOCK RECOVERY
AND SYNCHRONIZE

...L.

JAB
FDBK

I I

RPW
VCM-CI
SET-PW

:D
~O

BUFFER

w'
w»

MUX

I...

JABBER
CONTROL

MANAGEMENT

OUTPUT
MUX

TXDUT
TXDUT

BUFFER

'. LOOPBACK

•

~ SM M~ PHYSICAL

CPW

T
CLOCK
GENERATOR

VCC

•

I
.-lREO
5YM2
iYMI
T iYMO

}llOCK
VCX

*
Figure 4. Functional Block Diagram

3:
n
en

CO
U)

,J:Io.

MC68194

PIN ASSIGNMENTS

>(I)

x
cr:

:E>-

(I)

x
cr:

:5
u
x
cr:

cO
=>

(I)

u
u

~
cr:

RXSYM2

GND-VCM

N.C.

VCC-VCM

VCC-TTL

VCM-C2

GND-TTL

VCM-Cl

RESET

VCX

CPW

RPW

SET-PW

SMREQ

RXIN

TXCLK

RXIN

JAB

FDBK

EDTDIS

FDBK

vcc-bsc

THRESHOLD

TXSYMO

MC68194
CBM
(PLCC)

TXSYMI
TXSYM2

Motorola Order Number:

=>
x

u
cr:

cD
~

:I:

u>
cr:

U
u
>

>
u
cr:

MC68194 FN

--t--

+<-----paCkage Designation
" - - - - - - Device
,. .

MOTOROLA
7-34

M68000 FAMILY
REFERENCE

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68605

Technical Summary

X.25 Protocol Controller (XPC)
The MC68605 X.25 Protocol Controller (XPC) is an intelligent HCMOS communications protocol
controller that implements the 1984 International Telegraph and Telephone Consultative Committee
(CCITT) X.25 Recommendation, data link access procedure (LAPB). It supports full duplex point-topoint serial communication at up to 10 megabits per second (MBPS) and relieves the host processor of managing the communications link by providing sequencing using HDLC framing, error control, retransmission based upon a cyclic redundancy check (CRC), and flow control using the receive
not ready supervisory frame. The XPC directly supports the physical level interfaces (Recommendation X.21 physical level, X.21 bis, and V-series) and also provides an efficient interface to the packet
level for information and control exchange. Key features of the XPC include:
• Fully Implements X.25 Recommendation LAPB Procedure by Independently Generating Link
Level Commands and Responses
• Option to Implement X.75 Recommendation
• Optional Transparent Operation (Monitor Mode) where XPC Provides HDLC/SDLC Framing
Functions for User Generated Frames
• Performs DMA Transfer of Information Frames To and From Memory Using Two On-Chip 22Byte FIFOs
• Primary Communication Through Shared Memory Structures with a Powerful Command Set
to Off-Load Data Link Management
• Flexible RxlTx Linked Memory Structures Minimize Host Intervention and Simplify Memory
Management
• Basic (Modulo 8) and Extended (Modulo 128) Operation
• Automatic Comparison of the Programmable Local and Remote Addresses
• Detection of Programmable Timeout and Retries Limit Conditions
• 16- or 32-Bit CRC Generation and Checking
•
•
•
•

Standard Modem Interface
NRZ or NRZI Encoding/Decoding
Vectored Interrupts and Status Reporting
Built-In Diagnostics Provide Local Loopback and External Loopback Testing

• Up to 10 Mbps Synchronous Serial Data Rate
• 12.5 and 10 MHz System Clock Versions
• 8- and 16-Bit Data Bus Support
• 32-Bit Address Bus with Virtual Address Capability
• M68000 Family Asynchronous Bus Structure
• Programmable Byte Ordering of Data for Alternate Memory Organization Schemes

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA _
M68000 FAMILY

REFERENCE

MOTOROLA
7-35

MC68605

GENERAL DESCRIPTION

INTERNAL REGISTERS

The XPC supports high-speed X.25 communications
between host computers, between host computers and
remote units, and between remote units. The XPC also
supports a transparent operation mode which does not
apply the LAPB procedure. Data is passed between the
XPC and the host processor through shared memory
structures. This permits a minimum command set for
host processor/XPC communication. Additionally the XPC
is a full M68000 bus master, providing on-chip DMA
capability for management of memory tables and frame
buffers. Since the XPC data bus interface is configurable,
the XPC can handle both 8-bit and 16-bit data transfers.
When the X.25 mode is selected by the user, the XPC
is configured as a combined station for full duplex pointto-point communication. The XPC supports a non-operational mode and two operational modes as defined by
the LAPB procedure. The non-operational mode is asynchronous disconnect mode (ADM). In this balanced data
link mode, the combined station is logically disconnected
from the data link and is not permitted to transmit or
accept· information. Operational modes include asynchronous balanced mode (ABM) and asynchronous mode
extended (ABME). A balanced data link allows a combined station to send a command or initiate a response
frame transmission without receiving explicit permission
from the other station. In ABM/ABME the XPC performs
the following operations:
1) Transmission of a chain of information (I) frames
when instructed by the host,
2) Transmission of supervisory (S) frames as defined
by the X.25 LAPB Recommendation,
3) Transmission of unnumbered (U) commands as
required or when instructed by the host, and
4) Transmission of unnumbered (U) responses as
defined by the X.25 LAPB Recommendation.
When the transparent mode is selected, the XPC can
be configured as a master, a slave or a combined station
for full duplex operation. The XPC can support any HDLCI
SDLC defined operational mode. All frames are user-generated and are transmitted only when instructed by the
host.

The XPC has four functional blocks including: serial,
DMA, microcode controller, and register-file/ALU. Each
of these sections contain user visible and nonvisible registers that define and control the operation of the XPC.
A block diagram of the MC68605 is shown in Figure 2.
Because the XPC communicates with the host primarily
through shared memory, a minimum number of host
processor accessible registers are required. Registers in
the XPC fall into two groups. One group is directly accessible by the user and the other group is indirectly
accessible through the station table. The directly accessible registers include the command register, semaphore
register, interrupt vector register, and data register. The
complete register set is shown in Table 1.

SHARED MEMORY STRUCTURES
The host processor communicates with the XPC using
three tables located in shared memory (Figure 3). The
station table allows the host processor to initialize and
update the XPC operating parameters and table pointers,
and to receive status and error information. The transmit
frame specificaton table queues frames to be transmitted
by the XPC, and the receive frame specification table
queues available receive buffers for the XPC to store received information frames. The XPC is given a pointer to
the station table during initialization. The transmit frame
specification table and receive frame specification table
pointers are contained in the station table.
STATION TABLE
The station table format is shown in Table 2. The first
19 words of the station table are written by the host processor and are read by the XPC. This portion of the table
contains the XPC operating information. The XPC accesses this table area as the result of a host processor
command. The next 22 words of the table are written by
the XPC and read by the host processor. Some of these
entries are written by the XPC as the result of a command
while other entries are updated by the XPC when a change
occurs. When the XPC accesses the table as the result of
a host processor command, it sets the semaphore register to hex 'FF' upon completion of the access. While the
XPC is processing a command, the semaphore register
is hex 'FE'.
TRANSMIT FRAME SPECIFICATION TABLE

Figure 1. XPC System Configuration

MOTOROLA
7-36

The transmit frame specification table queues transmit
frames for the XPC. These frames are stored in memory
buffers located throughout memory. The transmit frame
specification table contains a sequential list of transmit
frame specification blocks. The transmit frame specification blocks describe the location oftransmit buffers and
provide information about the transmit queue. The transmit table pointer location in the station table points to
the first transmit frame specification block. See Figure 4.
When the host processor instructs the XPC to load
transmit table pointer, the XPC loads the transmit table

M68000 FAMILY
REFERENCE

MC68605

SYSTEM INTERFACE

MICRO·
CONTROLLER
PHYSICAL LAYER
SERIAL INTERFACE

TRANSMIT
MACHINES

Figure 2. MC68605 Block Diagram

Table 1. XPC Register Set
Register

Description

Directly Accessible Registers

VIS)

Mnemonic
VIS)

Command

a-Bit Write Only

VIR)

Semaphore

a-Bit Read Only

Time Scale Divider

TSD

Interrupt Vector

a-Bit Write Only. Read on Host Processor Interrupt Acknowledge Cycle

Transmit Table Pointer

32-BitWrite Only

Transmit Table Function Code

Data

Indirectly Accessible Registers
Register

Mnemonic

Retries Count

RC
TIP
TIFC

Transmit Buffer Pointer

TBP

Transmit Buffer Function Code

TBFC
TBC

Station Table Pointer

STP

Transmit Buffer Count

Station Table Function Code

STFC

Receive Table Pointer

RTP
RTFC

Local Address

Receive Table Function Code

Remote Address

Receive Buffer Pointer

RBP

Hardware Configuration

Receive Buffer Function Code

RBFC

Station Configuration

Receive Buffer Count

RBC

Option Bits

Time-Out Preset

TOP

Mode Descriptor

Retries Limit

Frame Reject Descriptor

FRD

Outstanding Frames Limit

Rx/Host Status

RHS

Pad Time Select

PTS

Tx/Link Status

TLS

Last Received N(R)

LRN

M68000 FAMILY

REFERENCE

RL
OFL

MOTOROLA

7-37

MC68605

Rx FRAME SPECIFICATION TABLE
STATUS/FC
BUFFER POINTER
BUFFER LENGTH

...-t---'l"
L -_ _ _....

FINAL COUNT
STATION TABLE
Rx TABLE
POINTER

e--+--....

Tx TABLE

e--+---.

POINTER
STATUS/FC
BUFFER POINTER
BUFFER LENGTH

"'-f---I~
L--_ _ _.......

Figure 3. Shared Memory Tables

pointer and transmit table function code registers from
the corresponding station table entries. The transmit table pointer register then has the address of the first transmit frame specification block. Before the transmission of
each frame, the XPC accesses the current transmit frame
specification block to load the transmit buffer function
code, transmit buffer address, and the transmit buffer
length into the corresponding internalregisters. The XPC
presents a transmit buffer address and function code to
the system to load the information contained in the transmit buffer.
During transparent operation, the XPC accesses the
next transmit frame specification block and transmits the
corresponding frame buffer until the end of the transmit
frame specification table is reached. The XPC updates its
internal VIS) register after the transmission of each frame.
When all frames have been transmitted; the XPC sets the
IFAK bit (information frames acknowledged) in the Tx/
link status register.
.
During X.25 operation, the XPC accesses the next transmit frame specification block and transmits the corresponding frame buffer according to the X.25
Recommendation until either the outstanding frames limit
or the end of the transmit frame specification table is
reached. The XPC updates its internal VIS) registers after
the transmission of an information frame. The XPC monitors the N(R) of incoming frames until all transmitted
frames have been acknowledged. After all frames have
been ackriowledged, the XPC sets the IFAK bit in the Tx/.
link status register.
RECEIVE FRAME SPECIFICATION TABLE
The receive frame specification table queues receive
buffers for the XPC. These buffers are stored throughout
memory. The receive frame specification table contains

MOTOROLA
7-38

a sequential list of receive frame specification blocks. The
receive frame specification blocks describe the location
of the receive buffers and provide information about the
queue. The receive table pointer in the station table points
to the first receive frame specification block. See Figure
5.
When the host processor instructs the XPC to load receive table pointer, the XPC loads the receive table function code and receive table pointer registers from the
corresponding station table entries. The receive table
pointer register then contains the address of the first receive frame specification block.· The XPC accesses the
receive frame specification block to load the receive buffer
function code, receive buffer address, and the receive
buffer length into its internal registers. The XPC then
presents the receive buffer address and function code to
the system to store the received information field in the
memory buffer. After reception of a frame, the XPC writes
the number of unused bytes in the final count entry in
the current receive frame specification block and updates
its internal VIR) register. Next the XPC sets the RXI bit
(receive information frame) in the Rx/host status register.
The XPC accesses the next receive frame specification
block to store incoming frames, until the end of the receive frame specification table is reached.
To decrease the possibility of a receive not ready condition due to a lack of available receive buffers, a method
is provided for linking receive frame specification tables.
When the EDT (end of table) bit is set in a receive frame
specification block, the XPC inspects the link bit value. If
the link bit is set, then the XPC loads the receive table
pointer and Fe registers from the corresponding station
table locations. The XPC then sets the RTE (receive table
ended) bit in the Rx/host status register and issues an

M68000 FAMILY
REFERENCE

MC68605

Table 2. Station Table Structure
12

Word 15

o
1
2

Time Out Preset
Time

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

S~ale

23
24
25
26

27
28
29
30

34
35
36
37
38
39
40

Pad Time Select

Retries Limit
Outstanding Frames Limit
Rx/Host Mask Bits
Tx/Link Mask Bits
Rx/Host Status Clear Bits

0 0 0 0
0 0 0 0
0 0 0 0

Tx/Link Status Clear Bits
Local Address
I-

1 0 0 0 0
0 0 0 0
1 0 0 0 0

Remote Address

1 0 0 0

RTFC

o I

TIFC

Host Processor
Area Read by the
XPC Written by
Host Processor

Receive Table Pointer - High Word
Receive Table Pointer - Low Word

0 0 0 0

0 0 0

Transmit Table Pointer - High Word
Transmit Table Pointer";' Low Word

0 0 0 0

0 0 0

o I

DAFC

Dump Area Pointer - High Word
Dump Area Pointer - Low Word
Rxl Host Status
Tx/Link Status

Mode Descriptor
VS

0 0 0 0

Frame Reject Descriptor

1
1 0 0 0

1 0 0 0 0

o 1

FUFC

First Unacknowledged Pointer - High Word
First Unacknowledged Pointer - Low Word

0 0 0 0

0 0 0

o I

TFC

Transmit Pointer";' - High Word
XPC Area Read

Transmit Pointer - Low Word

0 0 0 0

1 0 0 0 0

Receive Pointer - High Word

32
33

Divider

20
21
22

Option Bits

RFC

REFC

by the XPC

Receive Pointer - Low Word

0 0 0 0

by the Host
Processor Written

Receive Busl Address Error Pointer - High Word
Receive Busl Address Error Pointer -

0 0 0 0

0 0 0

Low Word

o I

TEFC

Transmit Busl Address Error Pointer - High Word
Transmit Busl Address Error Pointer - Low Word
Received FRMR Informatiol'l Field - Word 1
Received FRMR Information Field - Word 2
Received FRMR Information Field - Word 3

CURRENT TRANSMIT FRAME
SPECIFICATION BLOCK

ON· CHIP REGISTERS

TRANSMIT TABLE POINTER _'-_ _.....
TRANSMIT TABLE FC

FC
DATA

TRANSMIT BUFFER POINTER
TRANSMIT BUFFER FC

TRANSMIT BUFFER LENGTH

TRANSMIT BUFFER COUNT

Figure 4. Transmit Frame Specification Table

M68000 FAMILY

REFERENCE

MOTOROLA
7-39

MC68605

CURRENT RECEIVE FRAME
SPECIFICATION BLOCK

ON·CHIP REGISTERS
RECEIVE TABLE POINTER
RECEIVE TABLE FC

FC
DATA

RECEIVE BUFFER POINTER
RECEIVE BUFFER FC

RECEIVE BUFFER LENGTH

RECEIVE BUFFER COUNT

FINAL COUNT

Figure 5. Receive Frame Sepcification Table

interrupt if enabled. The link operation can be used to
implement a cyclical queue by using the original RTP and
FC values in the station table. However, the user must
read filled receive buffers expediently to ensure that the
XPC does not overwrite the buffers with incoming frames.

COMMAND SET

• Zero Remote Address and Local Address Registers
• Zero VIR), VIS), and Last Received N(R) Registers
• Zero Preset Values and Retries Count Register
Set Station Configuration
The set station configuration command specifies protocol parameters. The command has the following format.
7

The host processor issues commands to the XPC to
perform various functions by writing to the XPC command register. There are 23 commands that fall in the
following four categories:
1) Initialization
2) Table Handling
3) Link Handling
4) Test/Diagnostics
INITIALIZATION COMMANDS
Initialization commands configure the XPC for operation after a hardware or software reset. The four initialization commands specify various system attributes,
communication protocol options, and the location of the
station table in memory.
Reset
The reset command and hardware reset causes the
following actions:
• Reset the Receive Channel and Isolate RxD
• Reset the Transmit Channel, Negate RTS, and
Transmit Ones
• Immediately Relinquish the System Bus
• Set the Interrupt Vector Register to 'OF' Hex
• Disable Transmit and Receive Memory Buffers
• Clear all Rx/Host and Tx/Link Status Bits
• Clear all Hardware and Station Configuration Bits
• Clear all Option Bits
• Clear all Mode Descriptor and Frame Reject Descriptor Bits
• Zero Station Table Pointer and Station Table FC
Registers
• Zero Transmit Table Pointer and Transmit Table
FC Registers
• Zero Receive Table Pointer and Receive Table FC
Registers

MOTOROLA
7-40

ECRC

ECNT

ECRC -

Extended CRC
16-Bit CRC
CRC CCITT (X16+X12+X5+ 1)
32-Bit CRC
(X32+X26+X23+X22+X16+X12+ 11
+X10+X8+ X7 +X5+X4+X2+X1 + 1)
ECNT - Extended Control
o Basic Control Field Format (Modulo 8)
1 Extended Control Field Format (Modulo 128)

Set Hardware Configuration
The set hardware configuration command defines the
data decoding/encoding scheme, DMA burst control, data
organization in memory and data bus size. The format of
the command is shown below.

NRZI

BRSC

DORGM 1 BUSW

NRZI -

Non-Returned to Zero Invert
NRZ Decoding/Encoding
1 NRZI Decoding/Encoding
BRSC - Burst Control
o DMA Burst is Unlimited
1 DMA Burst is Limited to Eight Successive Memory Cycles
DORGM - Data Organization in Memory for a 16-Bit Data
Bus System
o Data in Memory is Organized with High-Order Byte
in Lower Memory. Address (Motorola and IBM
Convention)
Data in Memory is Organized with Low-Order Byte
in Lower Memory Address (DEC and Intel Convention)

M68000 FAMILY
REFERENCE

MC68605

(This capability is available only for I frame buffers and not for parameters or tables.)
BUSW - Bus Width
o 8-Bit Data Bus
1 16-Bit Data Bus
Load Function Code
The load FC command writes the function code value
in the data register into the station table FC register. This
command is issued after the host processor has written
the function code to the data register.
Load Station Table Pointer
The load station table pointer command writes the station table address from the data register into the station
table pointer register. This command is issued after the
host processor has written the station table pointer to
the data register.
TABLE HANDLING COMMANDS
The 11 table handling commands cause the XPC to
access the station table, transmit frame specification table, or receive frame specification table.

station table into the corresponding XPC re~isters and
enables the transmission of a chain of information frames.
Continue Transmit
The continue transmit command (hex '95') is used to
extend the transmit queue after adding entries to the
transmit frame specification table. The user should set
the EOT bit in the transmit status location of the last
added entry and then clear the EOT bit at the previous
end of table. Finally, the user should instruct the XPC to
"continue transmit". This command is useful in the case
where the XPC has already detected the previous EOT
and will not read a new table entry. Instead, it is waiting
for all transmitted frames to be acknowledged, and during this period, it will not accept a new load transmit
table pointer command.
Load Receive Table Pointer
The load receive table pointer command loads the receive table pointer and the receive table FC from the
station table into the corresponding XPC registers and
enables the reception of information frames.
Load Station Parameters

Load Option Bits
The load option bits command loads the option set
from the station table into the option bits register.
B

This command combines the load option bits, load preset values, and load addresses commands.
Update Status

X.75

The update status command allows the host tO,request
current XPC status information.
Clear TX/Link Status

ICRCNDA I
X.75 -

X.75 Option
X.25 Operation
1
X.75 Operation
CRCNOA - CRC Bypass Option
o Non-octet aligned frames or frames witt,l a CRC
error are not accepted
Non-octet aligned frames or frames with a CRC
error are accepted

Load Addresses
The load addresses command loads the local and remote addresses from the station table into the internal
XPC registers. After these registers are loaded, the XPC
is ready to establish the link. The XPC monitors the receive line and transmits continuous flags.

The clear TX/link status command clears the status bits
in the Tx/link status register as specified by the Tx/link
status clear bits in the station table.
Clear RX/Host Status
The clear Rx/link status command clears the Rx/host
status register as specified by the Rx/host status clear
bits in the station table.
Clear Status
The clear status command clears both the Tx/link and
Rx/host status bits in the respective XPC registers as
specified by the Tx/link status clear bits and the Rx/host
status clear bits in the station table.
Dump Parameters

The load preset values command loads the time out
preset value, time scale divider, pad time select, outstanding frames limit, and retries limit from the station
table into the respective XPC internal registers.

The dump parameters command writes the following
XPC parameters into the corresponding status table locations in the order given: Rx/host status, Txllink status,
mode descriptor, frame reject descriptor, VIR), VIS), first
unacknowledged transmit block FC and pointer, next
transmit block FC and pointer, and next receive block FC
and pointer.

Load Transmit Table Pointer

LINK HANDLING COMMANDS

The load transmit table pointer command loads the
transmit table pointer and the transmit table FC from the

The two link handling commands cause the XPC to set
the link to a new operation mode and to automatically

Load Preset Values

M68000 FAMILY

REFERENCE

MOTOROLA

7-41

MC68605

XPC IMPLEMENTATION OF
LAPB PROTOCOL

handle communication on both channels according to the
predefined configuration and option bits.
Start Link

INITIALIZATION PROCEDURE

The start link command initiates the link setup procedure.

The XPC enters the initialization procedure as the result
of a hardware or software reset. During this initialization,
the station table address and function code (FC), system
configuration information, and the XPC interrupt vector
are loaded by the XPC under the direction of the host, as
shown in the sample program below. Internal XPC registers directly accessed during the initialization procedure
are the command register (CR), data register (DR), interrupt vector register (IV), and semaphore register (SR).

Stop Link

The stop link command initiates the link disconnect
procedure.
TEST/DIAGNOSTICS

The five commands in the text/diagnostics category test
the XPC circuit and run diagnostics on the link.
Dump Registers

The dump registers command writes the XPC registers
to a user specified dump area in external memory.
DMA Transfer

The DMA transfer command tests the handling of parallel data. The XPC reads the data from a transmit memory buffer and writes it to a receive memory buffer. The
XPC transfers data from the transmit buffer to the receive
buffer via the data register without using the internal
transmit or receive FIFOs. The serial link is not affected
by this operation.
Serial Loopback

The serial loop back command tests the handling of
parallel and serial data. The XPC reads data from the
transmit memory buffer into the transmit FIFO. The data
is then serialized and shifted internally into the receive
FIFO and onto the TxD line. Finally the data is stored in
the receive memory buffer. RTS is not active during serial
loopback.
Monitor'

The monitor command allows the XPC to check the
communication channel by reading/writing the entire
frame from/to memory. The monitor command may be
used to perform an external loopback test of the system
or to implement any HDLC/SDLC operation mode where
all frames are user generated. The XPC transmits and/or
receives multiple information frames using the transmit
and receive frame specification tables until an end monitor command is received.
In each transmit buffer the user places the address,
control, and data (if any) fields. The XPC only provides
framing, zero insertion, and CRC for each frame. On the
receive side, the XPC strips off flags, handles zero deletion, and writes the address control and data fields into
the receive buffer. The received CRC is also appended to
the end of each memory buffer and is verified by the
XPC.
End Monitor

The end monitor command terminates the monitor
command. '

MOTOROLA
7-42

RESET

Repeat:
Write CR:
Repeat:
Write CR:
Repeat:
Write DR:
Write CR:
Repeat:
Write DR:
Write CR:
Repeat:
Write IV:
Write CR:
Repeat:

Read Semaphore Register Until it is 'FF'
Set Hardware Configuration
Read Semaphore Register Until it is 'FF'
Set Station Configuration
Read Semaphore Register Until it is 'FF'
4-Bit Function Code Value for Station Table
Access
Load Function Code
Read Semaphore Register Until it is 'FF'
32-Bit Address of Station Table
Load Station Table Pointer (STP)
Read Semaphore Register Until it is 'FF'
Load Interrupt Vector
Load Station Table Parameters
Read Semaphore Register Until it is 'FF'
NOTE

The XPC will not come out of hardware or software
reset without the system clock and the transmit
clock. The transmit clock is used to initialize the
serial section of the chip.
INFORMATION FRAME TRANSMISSION

After the XPC enters asynchronous balanced mode
(ABM) or asynchronous balanced mode extended (ABME),
the host processor can instruct the XPC to transmit a
chain of information frames by issuing the load transmit
table pointer command. In response the XPC loads the
transmit table pointer and the transmit table function code
from the station table into its internal registers. Next the
XPC loads the first transmit buffer pointer,'transmit buffer
function code, and transmit buffer count from the transmit frame specification table into the corresponding XPC
registers. Now the XPC ,is ready to build the first frame.
The remote address is copied from the remote address
register into the XPC transmit FIFO. Next the control field
is generated and placed in the FIFO. The information field
pointed to by the transmit buffer pointer register is then
read from the memory buffer into the transmit FIFO until
the transmit buffer count is satisfied. A frame check sequence is attached to complete the frame. Zero insertion
is performed throughout the transmission. After frame
transmission the send state variable, VIS), is updated and
timer T1 is started (if it is not already running) to determine when the programmed time period permitted for a
reply to be received has elapsed.

M68000 FAMILY
REFERENCE

MC68605

This transmission sequence repeats for each frame until the end of the transmit chain is reached, or until the
outstanding frames limit is reached. The XPC continues
to transmit any available information frames even when
the XPC receiver is in the busy condition. The XPC prematurely terminates frame transmission if a link command interrupts the information frame transmission or
an error condition arises.
Transmission begins when six bytes are present in the
transmit FIFO. Transmission can begin when less than
six bytes are present in the FIFO if the entire frame is less
than six bytes in length. Between frames the XPC transmits the. user selected number of pad flags. Additional
flags are transmitted if the required number of bytes are
not present in the transmit FIFO. While transmitting an
information frame, the XPC requests the bus when there
are at least six empty bytes in the transmit FIFO.

INFORMATION FRAME RECEPTION
The host processor enables information reception by
instructing the XPC to load receive table pointer. The XPC
will load the receive table pointer and function code into
its internal registers. Next the receive buffer pointer and
function code, and the receive buffer count are loaded
into the corresponding XPC registers. The XPC is now
ready to receive information frames.
The address field of an incoming I frame is compared
to the local address register and the remote address register. If the address does not match the local or remote
address, the frame is ignored. Ifthe address field matches
the remote address, a frame reject (FRMR) is transmitted
and the W (invalid or unimplemented control field) bit of
the frame reject descriptor register (FRO) is set. If the
address field matches the local address, the frame is accepted by the XPC and the received N(R) acknowledges
previously transmitted I frames.
Next, the send sequence number N(S) of the incoming
frame is compared to the XPC internal receive state variable VIR). If the frame is in sequence, then the information field is transferred through the receive FIFO to
the receive memory buffer. Out-of-sequence frames are
rejected.
Lastly, the XPC performs a CRC check on the incoming
information frame. If an error-free frame is received, the
XPC acknowledges the frame reception with a supervisory frame (receive ready RR or receive not ready RNR)
or with an updated receive sequence number N(R) in the
next information frame.
Zero deletion is performed throughout the reception
process. The XPC requests the bus when there are six
bytes in the receive FIFO. Only a single frame can reside
in the receive FIFO. Frames are received in sequence as
long as memory buffers are available.
XPC STATE DIAGRAM
The XPC state diagram (Figure 6 which is located on
the last page of this document) is a detailed description
of the XPC implementation of the LAPB procedure. The
state diagram defines the various XPC states based on
command frames received (no errors), response frames
received (no errors), and miscellaneous inputs received.

M68000 FAMILY
REFERENCE

For example, referring to Figure 6, if the command received was an RR with the poll bit set to one while in the
remote .station busy condition (state 9), then the XPC
responds with an RR with the final bit set to a one and
changes to information transfer (state 5).

XPC TRANSPARENT
MODE OF OPERATION
The XPC transparent mode of operation can be used
to implement a variety of bit oriented protocols. The following paragraphs describe the XPC transparent mode
of operation.

INITIALIZATION PROCEDURE
The XPC enters the initialization procedure as the result
of a hardware or software reset. During initialization, the
station table address and function code, system configuration information, and the XPC interrupt vector should
be loaded by the XPC under the direction of the host, as
shown in the sample program below. Note that the XPC
will not come out of hardware or software reset without
the system clock and the transmit clock. The transmit
clock is used to initialize the serial section of the chip.
ENTERING TRANSPARENT OPERATION
Transparent operation is entered when the host issues
the monitor command. After the monitor command, the
XPC asserts RTS, transmits flags, and monitors RxD. Since
handshaking between nodes is not possible before the
monitor command is executed, the host processor at each
node must issue the monitor command in order for the
two nodes to communicate.
FRAME TRANSMISSION
After the monitor command is issued, the XPC begins
transmission of frames only after receiving a load transmit table pointer command from the host. All frames are
user-generated and may contain user-provided address,
control, and/or data fields. After the host issues the load
transmit table pointer command, the XPC loads the transmit table pointer and the transmit table funtion code from
the station table into its internal registers. Next, the XPC
loads the first trasmit buffer pointer, transmit buffer function code, and transmit buffer count from the transmit
frame specification table into the corresponding XPC registers. Now the XPC is ready to transmit the first frame.
The frame pointed to by the transmit buffer pointer
register is read from the memory buffer into the transmit
FIFO until the transmit buffer count is satisfied. An XPCgenerated frame check sequence is then attached to complete the frame. After each frame transmission, the internal VIS) register is incremented without regard to the
frame type. This transmission sequence repeats for each
frame until the end of the transmit chain is reached. Zero
insertion is performed throughout the transmission process.
In transparent operation, the XPC transmits frames until the end of the transmit specification table is reached.
After the last frame is transmitted, the XPC sets the IFAK

MOTOROLA
7-43

MC68605

(information frames acknowledged) bit in the Tx/link status register to indicate the end of the transmit table. The
XPC does not analyze any incoming frames for acknowledgements or link control information during transparent
operation. The only errors reported in the Txllink status
register are address error, bus error, clear-to-send lost,
and underrun.
Transmission begins When six bytes are present in the
transmit FIFO. Transmission can begin when less than
six bytes are present in the FIFO; if the entire frame is
less than six bytes in length. Between frames, the XPC
transmits the user-selected number of pad flags. Additional pad flags are transmitted if the required number
of bytes are not present in the transmit FIFO for transmission to begin. While transmitting a frame, the XPC
requests the bus when there are at least six empty bytes
in the transmit FIFO.

The XPC does not analyze the address and control fields
of incoming frames, but does perform a CRC check on
incoming frames. After the flags are stripped off, the entire frame including CRC is written into the current receive
buffer and the RXI (received information frame) bit is set
in the Rx/host status register. If a frame is received with
a CRC error, the XPC sets the E bit in that frame's receive
specification block. After a frame is received, the XPC
increments VIR) without regard to frame type. Zero deletion is performed throughout the reception process.
In transparent operation, the XPC continues to receive
frames until the end of the receive specification table is
reached. The XPC then sets the RTE (receive table ended)
bit in the Rx/host status register.
The XPC requests the bus when there are six bytes in
the receive FIFO. Only a single frame can reside in the
receive FIFO. Frames are received in sequence as long
as memory buffers are available.

FRAME RECEPTION

The host processor enables frame reception by
instructing the XPC to load receive table pointer. The XPC
then loads the receive table pointer and function code
into its internal registers. Next, the receive buffer pointer
and function code, and the receive buffer count are loaded
into the,corresponding XPC registers. The XPC is now
ready to receive frames.

00·015

A3·A31

Al·A2

DATA 'US

SIGNAL DESCRIPTION
The input and output signals can be functionally organized into the groups shown in Figure 7.

fiTS

ADDRESS BUS

ADDRESS

'u(>

FCO·FC3

} MODEM CONTROl

TCLK
MC68605

TxD

}

TRANSMIT

}

RECEIVE

}

INTERRUPT CONTROL

ii'ECO·em

BUS CONTROL'

UDS/AO

RCLK

m/OS

RxD

R/W" .

iRli

DTACK

lACK

Bii
.US "BlTRA nON {

iiil

CLK

BGACK

Figure 7. MC68605 Signals

MOTOROLA
7-44

M68000 FAMILY

REFERENCE

MC68605

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Voo

-0.3 to +7.0

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature Range
MC68605
MC686051

Rating

Storage Temperature Range

Tstg

V
°C

o to 70
o to 85
-55 to +150

°C

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GNO or VOO).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance for PGA

Value
33

TJ = TA+(POeSJA)
Po = (VOOeIOO) + PI/O
where:
PliO is the power dissipation on pins (user determined) which can be neglected
in most cases.
For TA = 70°C and PO=0.55 W @! 12.5 MHz
TJ =88°C

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °C can
be obtained from:
TJ=TA+(PooOJA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
°JA
Junction-to-Ambient, °CIW
Po
= PINT+PPORT
= 100 x VOO' Watts - Chip Internal Power
PINT
= Power Oissipation on Input and Output Pins,
PI/O
Watts - User Oetermined

M68000 FAMILY
REFERENCE

For most applications PI/O

Figure 13. Write Cycle Timing Diagram _

C')

co
en
o

U'1

-;-J~I
CJ10

';:'--1

ClK
(INPUT)

(")

en
00
en
o

::0

»-

Al·A31
(OUTPUT)

BGACK
(OUTPUT)

AS
(OUTPUT)

R/W
(OUTPUT)

00·015
(INPUT)

DTACK
(INPUT)

RETRY
ON BECO·BEC2
(INPUT)

0'1

::tI~
mo
.,,0

111;

CASE 1: If DTACK satisfies
then (48) and (58) are required; if DTACK is active but does not satisfy (1), then (49) and (57) are required.
CASE 2: If DTACK is not active, then (59) is required for the exception active setup time. Parameter (61) is always required for the exception inactive setup time .

m."
::tI»
ms:
2_

orm<

~
~

~--I:~~

DTACK
(INPUT)

Figure 14. XPC Read Cycle with Retry Timing Diagram

:JJ~

men

"T1co
mo
:JJo
mo

ClK
(INPUT)

2"T1
0»
m~

A1·A31
(OUTPUT)

FCO·FC3
(OUTPUT)

AS
(OUTPUT)

'uos, lOS
(OUTPUT)

RiW
(OUTPUT)

00·015
(lNPUTI

OTACK
(INPUT)

BERR ON
BECO·BEC2
(INPUT)

BBACK
(OUTPUT)

s:
o

-;J~
(.TIl
(.TI»

EARLY ASYNCHRONOUS EXCEPTION
OTACK INACTIVE

lATE SYNCHRONOUS EXCEPTION
OTACK ACTIVE

s:n
0')

Figure 15. Read Cycle with Bus Error Timing Diagram

co
o

0')

CJ1

MC68605

ClK
(INPUT)

AS
(OUTPUT)

EXCEPTION
ON BECO·BEC2
(INPUT)

--+---.....--.. . . .

--~

Bli
(OUTPUT)

r-\
1 .._---------

BGACK
(OUTPUT) _ _ _ _ _ _ _.-;._ _ _ _ _ _ _ _ _ _ _-...J

The above occurs when the XPC requires the bus cycle after a previous exception.

Figure 16. BR After Previous Exception Timing Diagram

ClK
(INPUT)

AS
(OUTPUT)

ON EXCEPTION
BECO·BEC2
(INPUT)

~~~E

-----H----+---r--OTACK
(INPUT)

EXCEPTION
ON BECQ·BEC2
(INPUT)

------......j""'"'-

l~'

DTACK
(INPUT)

--Jr-\.

BGACK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
(OUTPUT)

! .-

Two alternatives of DTACK and exception. Case one has DTACK occur
after exception and case two has exception occur after DTACK. Note that
a HALT cycle can be terminated only by DTACK.

Figure 17. Short Exception Cycle Timing Diagram

MOTOROLA
7-56

M68000 FAMILY
REFERENCE

MC68605

24V--1l@

0.5 V

Figure 18. Clock (CLK) Timing Diagram

RCLK
!INPUT) - - - - - ' 1

RxO
!INPUT)

TCLK
!INPUT)

TxO
(OUTPUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

Figure 19. XPC Serial Data RxD, TxD, and Serial Clocks
(RCLK, TCLK) Timing Diagram

M68000 FAMILY

REFERENCE

MOTOROLA

7-57

MC68605

I FRAME
WITH
POll

I FRAME
WIO POll

RR
WITH
POll

RR
WIO POll

REJ
WITH
POll

REJ
WIO POll

RNR
WITH
POll

RNR
WIO POll

OM, F=1

UA, F=P
TO S5

FRMR,
F=1

FRMR,
F=O

FRMR,
F=1

FRMR,
F=O

FRMR,
F=I

FRMR,
F=O

FRMR,
F=I

S4
DISCONNECT
REQUEST

S5
INFORMATION
TRANSFER

RR, F=1

RR, F= I

S6
REJ FRAME
SENT

RR, F=1
TO S5

TO S5

RR, F=1

S7
WAITING
ACKNOWLEDGE·
MENT

RR, F=1

RR, F=O

RR, F=1

RR, F=O

STATE

S1
DISCONNECTED

S2
LINK SETUP

S3
FRAME REJECT

S8
STATION
BUSY

RNR, F=1

RNR, F=O RNR, F=1

S9
REMOTE
STATION BUSY

RR, F= 1

RR, F=O

S10
BOTH STATIONS
BUSY

RNR, F= I RNR,F=O

S11
WAITING ACK
AND
STATION BUSY

RNR,

Fo~

SABM
DISC.
WITH OR WITH OR
WIO POll WIO POll

RR
WITH
FINAL

RR
WIO
FINAL

REJ
WITH
FINAL

REJ
WIO
FINAL

RNR
WITH
FINAL

OM, F=P

UA, F=P

OM, F=·P
TO S1

FRMR,
F=O

UA, F=P
TO S5

UA, F=P
TO SI

DM, F=P
TO Sl

UA, F= P

RR, F= 1
TO S9

RR, F=O
TO S9

UA, F=P

UA, F=P
TO SI

{UNXFI
SABM
TO S2

''*

{UNXFI
SABM
TO S2

RR, F= 1
TO S14

RR, F=O
TO S14

UA, F=P
TO'S5

UA, F= P
TO S1

{UNXFI
SABM
TO S2

RR, F=1

RR, F=O

RR, F= I
TO SI2

RR, F=O
TO S12

UA, F=P
TO S5

UA, F=P
TO S1

..*
TO S5

TO S9

RNR, F=1

RNR, F=1
TO S10

RNR, F=O
TO S10

UA, F= P

UA, F=P
TO SI

{UNXFI
SABM
TO S2

'**

IUNXFI
SABM
TO S2

TO S10

TO S5

RR, F=1
TO S5

TO S5

RR, F=1
TO S5

TO S5

RR, F= I

RR, F=O

UA, F=P
TO S5

UA, F= P
TO S1

IUNXFI
SABM
TO S2

***
TO S5

IUNXFI
SABM
TO S2

RNR, F=1
TO S8

'N
TO S8

RNR, F=1
TO S8

*N
TO S8

RNR, F=1

RNR, F=O

UA, F=P
TO S8

UA, F=P
TO S1

IUNXFI
SABM
TO S2

***
TO S8

IUNXFI
SABM
TO S2

RNR, F=O RNR, F= 1 RNR,f=O

RNR, F=1
TO SI3

RNR, F=O
TO S13

UA, F=P
TO S8

UA, F= P
TO SI

'*'
TO S8

RR, f= I
TO S7

RR, F= 1

RR, F=O

UA, F= P
TO S5

UA, F=P
TO Sl

***
TO S5

TO S7

RNR,F=O
RNR, F=1
TO S11

RNR, F=O

UA, F=P
TO S8

UA, F=P
TO SI

*'*
TO S8

TO Sll

TO S8

RR, F=O

UA, F=P
TO S5

UA, F=P
TO S1

IUNXFI
SABM
TO S2

1 RNR, F=O RNR, F=1

TO S8

SI2
WAITING ACK
AND REMOTE
STATION BUSY

RR, F=1

RR, F=O

RR, F=1
TO S7

S13
WAITING ACK
AND BOTH
STATIONS BUSY

RNR, F=1

RNR, F=O

RNR, F=1
TO Sl1

SI4
REJ FRAME SENT
AND REMOTE
STATION BUSY

RR, F= 1
TO S9

RR, F=O
TO S9

RR, F= 1
TO S6

RR, F=O
TO S7

RNR,F=O RNR, F=1
TO SII
TO SI1

TO S6

RR, F=I
TO S6

RR, F=O
TO S7

TO S6

RR, F= I

TO S6

"*
TO S5

TO S5

TO S8

TO S7

TO S9

TO Sl1

TO SIO

{UNXFI
SABM
TO S2

TO S6

If I available then Tx I frame else Tx RR, F = 0
If I available then Tx I frame else do nothing
If I available then Tx I frame else Tx RNR, F = 0
If P= 1 then Tx RNR, F= 1 else if I available then Tx I frame e!se Tx RNR, F=O
If P= 1 then Tx FRMR, F= 1 else if P=O then Tx FRMR, F=O else do nothing
If P = 1 then Tx OM, F = 1 else do nothing
If no REJ FRAME is outstanding then transmit REJ, F = P else if P= 1 then Tx RR, F = 1 else do nothing
*, J If the I field of a correctly received frame has been discarded (due to the busy condition I then Tx REJ, F = 0 else Tx RR, F = 0
Do nothing
X This event never occurs in this state
UNXF Unexpected final bit
'N
'*N
'FR
'OM
*J

Figure 6. XPC State Diagram

MOTOROLA
7-58

M68000 FAMILY
REFERENCE

MC68605

RNR
W/O
FINAL

UA WITH
ORW/O
FINAL

OM
WITH
FINAL

OM
W/O
FINAL

FRMR
WITH OR
W/O FINAL

LOCAL
START
COMMAND

LOCAL
STOP
COMMAND

STATION
BECOMES
BUSY

BUSY
CONDITION
CLEAR

TI
EXPIRES

N2=T1
IS
EXCEEDED

NS
SEOUENCE
ERROR

INVALID
NR
RECEIVED

UNRECOGNIZED
FRAME
RECEIVED

SABM
TO S2

DISC
TO S4

"OM

TO S5

TO SI

SABM

TO SI

SABM
TO S2

DISC
TO S4

FRMR

SABM
TO S2

"FR

TO SI

DISC

TO SI

TO S9

SABM
TO S2

SABM
TO 52

DI5C
TO 54

RNR,F=P
TO 58

RR, P= 1
TO S7

5ABM
TO S2

"J
TO S6

FRMR(Z)
TO S3

FRMR(W)
TO 53

TO S14

5ABM
TO,S2

SABM
TO S2

SABM
TO 52

DI5C
TO S4

RNR, F= P
TO S8

RR, P=1
TO S7

SABM
TO S2

IF P= 1
TxRR,F=1

FRMR(Z)
TO S3

FRMR(W)
TO S3

TO S12

SABM
TO 52

5ABM
TO S2

SABM
TO S2

DI5C
TO S4

RNR,F=P
TO SII

RR, P= 1

5ABM
TO S2

FRMR(Z)
TO 53

FRMR(W)
TO S3

TO S10

5ABM
TO 52

SABM
TO 52

5ABM
TO 52

DI5C
TO 54

""J
TO 55

RNR, P= 1
TO 511

SABM
TO 52

RNR, F=P

FRMR(Z)
TO S3

FRMR(W)
TO 53

5ABM
TO 52

SABM
TO S2

5ABM
TO 52

DI5C
TO S4

RNR, F=P
TO S10

RR, P= 1
TO S12

SABM
TO 52

FRMR(Z)
TO S3

FRMR(W)
TO 53

5ABM
TO S2

5ABM
TO 52

DI5C
TO 54

RNR, P=1
TO 513

5ABM
TO S2

RNR, F=P

FRMR(Z)
TO S3

FRMR(W)
TO S3

TO S13

5ABM
TO S2

5ABM
TO 52

DI5C
TO 54

RNR. P=1

5ABM
TO S2

RNR, F=P

FRMR(Z)
TO S3

FRMR(W)
TO S3

5ABM
TO S2

SABM
TO S2

DISC
TO S4

RNR, F=P
TO S13

RR, P=1

SABM
TO S2

FRMR(Z)
TO S3

FRMR(W)
TO S3

5ABM
TO 52

SABM
TO 52

DISC
TO 54

TO 512

RNR, P= 1

SABM
TO S2

RNR, F=P

FRMR(Z)
TO S3

FRMR(W)
TO 53

SABM
TO 52

SABM
TO S2

DISC
TO 54

RNR, F= P
TO S10

RR, P= 1
TO S12

SABM
TO 52

IF P=1
Tx RR, F=1

FRMR(Z)
TO S3

FRMR(W)
TO S3

M68000 FAMILY
REFERENCE

oOJ
TO 59

oOJ
TO 57

oOJ

oJ
TO 514

MOTOROLA
7-59

MC68605

PIN ASSIGNMENT

Pin Grid Array

0
TxO

0
GNO

0
A3

0
AB

0
Al0

0
A12

0
A14

0
AlB

0
RCLK

0
GNO

0
A2

0
A5

0
A9

0
A13

0
A15

0
A17

0
A20

0
CTS

0
RxO

0
TCLK

0
Al

0
A4

0
A7

0
All

0
AlB

0
A19

0
A21

0
BECI

0
BEC2

0
RTS

0
A22

0
A23

0
A24

0
CLK

0
BECO

0
GNO

0
A25

0
A2B

0
GND

0
VOO
0
A27

0
A29

0
A2B

0
GNO

0
A30

BOTTOM
VIEW

0
BGACK lACK

iRil

0
VOO
0
0
OTACK GNO

0
00

0
OB

0
09

0
012

0
FCI

0
A31

0
RJW

0
0
GNO UOS/AO

0
02

0
05

0
DB

0
011

0
015

0
FC3

0
03

0
04

0
07

0
010

0
013

0
014

0
FCD
0
FC2

0
LOS/OS

0
01

Plastic-Leaded Chip Carrier

AlB

TxO
RxO

A24
A25
A2B
VOO
A27

BEC2
BECI
BECD
GNO
GNO

~
~

A31
GNO
GNO
FCO
FCI
FC2
FC3

MOTOROLA

7~60

r+.",..;.;.---------=::....:..:-------:..:..".,+, RCLK

A19
A20

C~
~
~

BGACK
lACK
IRQ
OTACK
VOO
RiW
GNO

M68000 FAMILY
REFERENCE

MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC68606

Technical Summary

Multi-Link LAPD (MLAPD) Protocol
Controller
The Motorola MC68606 Multi-Link LAPD (MLAPD) protocol controler is an integrated circuit implementing the link access procedure (LAPD) protocol. LAPD is the proposed protocol for use at the
link layer (ISO-Layer 2) for both signalling and data transfer applications in Integrated Services Digital Network (ISDN) configurations. The LAPD protocol is specified in CCITI Recommendation 0.920/
0.921.
Current product implementations of this link level protocol are accomplished with firmware. This
significantly loads the local processor, and presents limitations to both the maximum potential
throughput of data and to the number of logical links which may be supported by such packet data
interfaces. A generic view of where the MLAPD device can be used to interconnect a diversity of
data endpoints in a high speed packet switch network is shown in Figure 1. The data links illustrated could differ functionally and provide data rates in the range of 64 kbps to 2.048 Mbps.
The MLAPD functions as an intelligent peripheral device to a central processing unit (CPU) in a
microcomputer system. An on-chip DMA controller transfers data packets to and from a buffer
memory. A microcoded buffer management scheme queues packets during transmission and reception. All link management duties are handled by the MLAPD device to maximize the bandwidth
available for CPU operation and to increase the throughput for packet data transfer. This VLSI implementation provides a cost effective solution, while encouraging a universal implementation of
the LAPD protocol. Key features of the MLAPD device include:
• Full Implementation of CCITI Recommendation 0.920/0.921 Link Access Procedure (LAPD)
with Independent Generation of Commands and Responses for Each Logical Link
• Control of up to 8192 Logical Links Using a Memory-Based Architecture, Wherein the Protocol Controller and the Supervising Microprocessor Communicate Through Shared Memory
• Reliable, Interleaved Data Transfers for Multiple Logical Links with the Following Protocol
Actions:
- HDLC framing with zero-bit insertion/deletion for a serial bit stream; or optional parallel
assist mode where zero insertion/deletion is disabled and frame delineation is provided
by external pins for supporting a parallel interface to the physical level.
Error control using a 16-bit CRC.
Flow control to prevent data from accumulating at the receiving end faster than the data
can be processed.
• Termination of a Non-Channelized Serial Bit Stream with an Aggregate Rate in Excess of
2.048 Mbps or Optional Memory-to-Memory Operation Allowing the MLAPD to Act as a LAPD
Controller Independent of the System's Physical Level Characteristics

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA _
M68000 FAMILY

REFERENCE

MOTOROLA
7-61

MC68606

•
•
•

•
•

•

•
•
•

Supports User Prioritization of I Frame and XID/UI Frame
Transmission
Supports Optional Receive and Transmit of a User-Defined,
Non-Standard LAPD Unnumbered (U) Frame
On-Chip, Content-Addressable Memory (CAM) Provides
Address Translation for Up to 16 Logical Links. When
Supporting More Than 16 Logical Links, Translation is
Provided Via a Translation Table in Shared Memory
Provides Error/Statistical Counters and Maskable
Interrupts to the Level 3 Process
Supports Optional Non-Protocol Mode on a Per-Logical
Link Basis, Which Allows the Host to Receive and
Transmit Frames Without Application of the LAPD
Procedures by the MLAPD
Supports Promiscuous Receive Mode in Which the MLAPD
Receives All Frames From the Line and Transfers the
Entire Frame to Memory
System Interface Tailored for Different Microprocessor
System Implementations:
Motorola M68000 and Intel iAPX86 Family Bus
Interface Options
8- and 16-Bit Data Bus Support
Direct Addressing of 16 Mbytes of System Memory
Available in 12.5 MHz and 16.67 MHz System Clock
Versions
84 Lead PGA and PLCC J-Lead Surface Mount Packages
1.5 Micron HCMOS Technology

GENERAL DESCRIPTION
SUBSYSTEM ENVIRONMENT
The MLAPD protocol controller provides simultaneous control of a maximum of 8192 logical links, while under the overall
supervision of a microprocessor. Refer to Figure 2. The host
can be any 8- or 16-bit microprocessor that supports general
multimaster bus capability, operating with either the Motorola
M68000 family or the Intel iAPX86 family bus interface definition. The desired MLAPD bus operation mode is determined
by the level on the Motorolallntel Mode pin.
The MLAPD serial interface provides HDLC-type framing
functions for the bit stream entering/exiting the full duplex
serial interface. NRZ data encoding/decoding is implemented.
The MLAPD may also be optionally configured to interface to
a physical level which implements a parallel interface, such as
a backplane in a switching controller or host computer system.
In this mode zero insertion/deletion is disabled and flag sequences are not generated. Instead, the RTS and CTS signals
function as TSTART and RSTART, respectively, to delineate
a frame for the transmit and receive data lines.
Shared Memory Control Components
The communication between the microprocessor and the
protocol controller is established through command and data
block structures stored in shared memory. The shared memory

TERMINAL
CONCENTRATOR

~ Possible application of MLAPD device

Figure 1. High Speed Data Switching

MOTOROLA
7-62

M68000 FAMILY

REFERENCE

MC68606

ROM
LEVELS 3+

MICROPROCESSOR BUS

DATA
COMMAND
SEMAPHORE

MLAPD
CONTROLLER

PHYSICAL
INTERFACE

SERIAL COMMUNICATIONS LINK

INT. VECTOR

Figure 2. MLAPD System Environment
structures include the Global Configuration Block (GCB), Logical Link Tables (LLTs), receive and transmit data structures,
and an Interrupt Queue. In addition to these structures, there
are also four memory tables required for the implementation
of the LAPD procedure. These tables include the Match Table,
LLiD-LLT Table, Timer Table, and the Level 2 Queue. Figure
3 shows a concise summary of the functions performed by
these blocks.
BLOCK TYPE

PURPOSE

GLOBAL
CONFIGURATION
BLOCK

CONTAINS
TABLES.
CONTAINS
LOGICAL
CONTAINS

LOGICAL LINK TABLES

CONTAINS SPECIFIC LINK CONTROL PARAME·
TERS FOR THE GIVEN LINK. ALSO CONTAINS
POINTERS TO THE RECEIVEfTRANSMIT QUEUES.
CONTAINS WORKING PROTOCOL STATUS FOR
THE LINK.

RECEIVE AND
TRANSMIT QUEUES

CONTAINS LINKED LIST OF RECEIVE AND
TRANSMIT FRAME DESCRIPTORS FOR I. UI. AND
XID FRAMES.

RECEIVE POOLS

LINKED UST OF AVAILABLE RECEIVE FRAME DE·
SCRIPTORS WITH ASSOCIATED DATA BUFFERS.

INTERRUPT QUEUE

CONTAINS TIME SEQUENTIAL LIST OF INTER·
RUPT STATUS FOR EACH INTERRUPT EVENT.

MATCH TABLE

CONTAINS TRANSLATION FROM DATA LINK
CONNECTION IDENTIFIER (DLCn TO LOGICAL
LINK IDENTIFIER (LLlD) FOR INCOMING FRAMES
(EXPANDED OPERATION MODE).

LLID TO LLT TABLE

TRANSLATES LLID INTO THE ADDRESS OF THE
CORRESPONDING LOGICAL LINK TABLE.

LEVEL 2 TRANSMIT
QUEUE

CONTAINS LEVEL 2 SUPERVISORY AND UNNUM·
BERED FRAMES GENERATED BY THE MLAPD.

TIMER TABLE

IMPLEMENTS T200{T203 FOR ALL LOGICAL
LINKS THAT ARE IN MULTIPLE FRAME ESTAB·
LlSHED MODE OF OPERATION.

POINTERS TO OTHER MEMORY
GLOBAL INFORMATION FOR ALL
LINKS.
USER SYSTEM AND LINK OPTIONS.

Figure 3. Shared Memory Guide

M68000 FAMILY
REFERENCE

During initialization, the host processor specifies protocol
and system parameters and the addresses of the various memory tables via the Global Configuration Block. Then the host
programs the MLAPD controller with the address of the Global
Configuration Block and commands the MLAPD to initialize
itself by loading its internal registers from the shared memory
tables. After this point, the host and the MLAPDcommunicate
primarily via software flags and an Interrupt Queue in shared
memory.
Command Structure Overview
The host issues a command to the MLAPD by first writing
the command arguments (if any) into the command parameter
fields in the Global Configuration Block in shared memory.
Next, the host performs a write operation to enter the command into the on-chip command register. Upon reception of
a command, the MLAPD sets its on-chip semaphore register
to the value 'FE' hex. After either command completion or
command acceptance, depending on the specific command,
the MLAPD sets the value of the semaphore register to 'FF'
hex. The host must always read the semaphore register before
writing a ne)V command.
There are-32 commands which belong to one of the following
five categories:
Initialization-These commands configure the MLAPD for
operation after a hardware or software reset by specifying the
system data bus width and the location of the Global Configuration Block in memory.
Host/MLAPD Interface-These commands instruct the
MLAPD to perform operations that are not explicitly named
in the LAPD protocol, but which are required by the host to
interface with the MLAPD.
Protocol Handling-These commands are the primitives
explicitly defined in the LAPD protocol. The protocol commands allow the host to set-up and resume link operation, as
well as to control the flow of frames on the link.
Protocol Extension Handling - These commands are not
defined in the LAPD protocol. These commands allow the
host to intercede in the normal flow of the MLAPD protocol
processing.

MOTOROLA
7~63

MC68606

Test/Diagnostics- These commands allow the host to access all internal MLAPD registers or to test the DMA interface.
Figure 4 summarizes the MLAPD command set.
Exception Processing
An Interrupt Queue is located in shared memory to support
the speed requirement of reporting many interrupting events
occurring in rapid succession across the various active logical
links. Each entry in this Interrupt Queue consists of a logical
link identification number (LLlD) if applicable, and a cause
indication. Each of the 31 potential interrupt sources, with the
exception of bus error/address error and interrupt queue overflow, may be individually masked by the host to prevent the
reporting of a specific event.
After the MLAPD has written an entry into the Interrupt
Queue, a hardware interrupt request may be activated. If polled
operation is desired, this external interrupt indication is disabled by the host during MLAPD initialization. If an interrupt
acknowledgement cycle is to be implemented in an interrupt
driven system, the· interrupt vector register must be programmed by the host during the initialization procedure. The
interrupt vector register is located on-chip and allows the
MLAPD to return an indication of the interrupt cause as part
of an interrupt acknowledgement cycle on the system bus.
The two possible vectors reported across the bus are:

COMMAND GROUP

COMMAND

The two possible vectors reported across the bus are:
•
•

Normal Interrupt
Severe Interrupt (bus error/address error!

Interrupt information is written into the Interrupt Queue to
fully identify the specific cause of the interrupt in either a polled
or interrupt driven system. Interrupts are the principle mechanism to report protocol events and errors (including error
thresholds exceeded). Since the Interrupt Queue is circular
and of limited size, the host is responsible for "reading" the
interrupt information and maintaining free entries to record
new interrupt events.
Initialization Overview
As a part of initialization, the host must:
• Prepare the Global Configuration Block (GCB). The host
specifies the addresses of the various memory tables in
the GCB. The GCB is also programmed with several
global parameters that are required to process the LAPD
protocol for all links.
• Clear these tables: Match Table, Interrupt Queue, and
Timer Table.
• Prepare the Logical Link Table(s) (LLT) with the local
parameters for the link(s) in service.
• Construct receive pool(s) of frame descriptors.

FUNCTIONAL DESCRIPTION

INITIALIZATION

RESET
SET BUS WIDTH 8
SET-BUS-WIDTH-'6
INIT- -

SOFTWARE RESET.
DATA BUS WIDTH IS B BITS.
DATA BUS WIDTH IS '6 BITS.
MLAPD LOADS REGISTERS FROM THE GCB.

HOSTIMLAPD
INTERFACE

OFF·L1NE
ON·L1NE
RElOAD
DUMP STATISTICS
PRESET STATISTICS
ENABL(IRQ
ASSIGN -POOL POINTER

MLAPD ONLY EXECUTES HOST COMMANDS.
MLAPD EXECUTES COMMANDS, RECEIVES FRAMES, AND TRANSMITS FRAMES.
MLAPD LOADS REGISTERS FROM RELOADABLE AREA OF GCB.
MLAPD WRITES GLOBAL COUNTERS TO SPECIFIED MEMORY AREA.
MLAPD LOADS GLOBAL COUNTERS FROM STATISTICS THRESHOLD AREA OF GCB.
ALL PENDING INTERRUPT ENTRIES HANDLED. ENABLE EXTERNAL INTERRUPT SIGNAL.
HOST HAS CREATED A NEW RECEIVE POOL.

PROTOCOL

MDL ASSIGN REQUEST
DL ESTABLISH REQUEST
DL-DATA REQUEST
RELINK REQUEST
GLOBAL XID/UI REQUEST
XID/UI QUEUE Ii REQUEST
XID/UI-QUEUE-,-REQUEST
MDL ERROR RESPONSE
DL RElEASE-REQUEST
MDL REMOVE REQUEST

PLACE SPECIFIED LOGICAL LINK IN THE TEl ASSIGN STATE.
SET·UP LINK. LINK ENTERS MULTIPLE FRAME ESTABLISHED MODE.
REQUEST TRANSMISSION OF AN I FRAME QUEUE FOR THE SPECIFIED LOGICAL LINK.
FRAMES WERE ADDED TO A QUEUE IN WHICH ALL FRAMES WERE 'Tx AWAITING ACK'.
REQUEST TRANSMISSION OF XID/UI FRAMES IN THE GLOBAL XID/UI QUEUE.
REQUEST TRANSMISSION OF XID/UI FRAMES IN XID/UI QUEUE O.
REQUEST TRANSMISSION OF XID/UI FRAMES IN XID/UI-QUEUE-,.
INDICATION THAT NO OlCI ASSIGNED. THE LOGICAL LINK IS IN TEI_UNASSIGN STATE.
RElEASE LINK FROM THE MUlTIPLE FRAME ESTABLISHED MODE.
REMOVE SPECIFIED LOGICAL LINK FROM LAPD SERVICE.

PROTOCOL
EXTENSION

ACTIVATE LL
DEACTIVATE LL
REMOTE STATUS REQUEST
SET LOCAL BUSYmAR LOCAL BUSY
STOP TX I STOP-GLOBAL XID/UI
STOP- XID/UI QUEUE 0
STOP- XID/UI-QUEUE-'

PLACE SPECIFIED LOGICAL LINK IN THE TEl UNASSIGN STATE.
REMOVE DLCI·LLlD PAIR. PLACE LOGICAL LINK IN TEl UNASSIGN STATE.
SEND FRAME WITH P BIT SET TO CHECK REMDTE STATION STATUS FOR SPECIFIED LINK.
SPECIFIED LOGICAL LINK ENTERS THE LOCAL BUSY CONOITION.
SPECIFIED LOGICAL LINK EXITS THE LOCAL BUSY CONDITION.
STOP TRANSMISSION OF THE SPECIFIED LOGICAL LINK'S I TRANSMIT QUEUE.
STOP TRANSMISSION OF FRAMES IN THE GLOBAL XID/UI QUEUE.
STOP TRANSMISSION DF FRAMES IN THE XID/UI QUEUE O.
STOP TRANSMISSIDN OF FRAMES IN THE XID/UI-QUEUE-'.

TEST/
DIAGNOSTIC

DMA TEST
DUMP

TEST DMA OPERATION.
DUMP ALL INTERNAL MLAPD REGISTERS AND CAM.

Figure 4. Command Set Summary

MOTOROLA
7-64

M68000 FAMILY
REFERENCE

MC68606

•
•
•

Construct the necessary entry(s) in the LLiD-LLT Table.
Issue a RESET command to the MLAPD.
Issue a SET BUS WIDTH 16,(8) command to the
MLAPD, which specifies a-n 8- or 16-bit data bus
configuration.
• Load the interrupt_vector register in the MLAPD device.
• Load the address of the Global Configuration Block into
the data register in the MLAPD device.
• Issue the INIT command to the MLAPD.
The directly addressible MLAPD registers are shown in Figure 5.
Al

A2 15

UNDEFINED/RESERVED

UNDEFINED/RESERVED
I---

COMMAND/SEMAPHORE
INTERRUPT_VECTOR

DATA

Figure 5. Directly Accessible Registers
Frame transmission and reception is enabled for a specific
logical link after initialization by performing a Data Link Connection Identifier (DLC!) assignment procedure. (The DLCI is
contained in the address field of LAPD frames. The DLCI is
formed by the concatenation of the 6-bit service access point
identifier, SAPI, and the 7-bit terminal endpoint identifier, TEL)
This logical link then enters a protocol-defined state in which
it can receive and transmit unnumbered information frames.
After the exchange of SABME and UA frames, the link setup procedure is complete and the data connection is established. The M LAPD device is now ready to receive and transmit
numbered information (I) frames that contain the assigned
DLCI.

RECEIVE PROCESS
RECEIVE DATA STRUCTURES
The host maintains receive pools that contain free receive
frame descriptors with associated data buffers. The host can
create up to 8192 receive pools and can assign any number
of logical links to the same receive pool. The data buffers in
a pool must be of a length at least equal to the largest

USER Rx NEXT POINTER

RECEIVE FRAME
DESCRIPTOR

N201 value specified for any logical link assigned to the pool.
The receive data structure is shown in Figure 6. The format
of a receive frame descriptor is shown in Figure 7.
A receive pool must always contain at least one frame descriptor. The last frame descriptor in the pool is the pool
dummy frame descriptor and the last in pool bit in this frame
descriptor's control bits entry is set. - When the receive
pool pointer points to this pool dummy frame descriptor, the
receiVe pool is defined to be empty.
The host can add frame descriptors to a receive pool dynamically. The host maintains a user_Rx_pool tail_pointer for
each receive pool, which points to the pooLdummy frame
descriptor, for this operation. The host may also request a
red line interrupt when the MLAPD uses a frame descriptor
nea~ the end of the receive pool, 'allowing the host to add
frame descriptors to avoid a receive busy condition.
After creating a receive pool, the host specifies a receive_
pool pointer, which is the address of the first frame descriptor
in the receive pool, and issues an ASSIGN_POOL_POINTER
command to cause the MLAPD to load the receive_pool_
pointer into the Receive Pool Pointers Table. The MLAPD
stores the first sixteen receive pool pointers (0 to 15) on-chip
and stores any additional receive pool pointers (16 to 8191)
in the Receive Pool Pointers Tabie in -shared memory. The
address of the memory table is specified by the host in the
Global Configuration Block.
The host assigns each logical link to a receive pool via the
receive pool number entry in the link's LLT. During frame
reception, the MLAPD uses the receive_pool_number entry
for the addressed link as an offset into the Receive Pool Pointers Table to locate the first receive frame descriptor in the
assigned pool. Refer to Figure 8. When the frame is successfully received, the MLAPD indicates the frame type and stores
the associated LLiD in the receive frame descriptor. Then the
M LAPD reads the next rx frame descriptor entry in this frame
descriptor and updatesthe receive pool pointer for this pool
in the Receive Pool Pointers Table: Although the linkage to
the receive pool is not broken, the frame descriptor can now
be considered part of a receive queue. All logical links that
share the same receive pool will also share a common receive
queue. It is the responsibility of higher level software to remove
valid frames from the receive queue and eventually return the
frame descriptors to the receive pool.

(MLAPD) RECEIVE POOL POINTER (X)

RECEIVE FRAME
DESCRIPTOR

USER Rx POOL TAIL POINTER
POOL DUMMY
FRAME DESCRIPTOR

11-..01 - - - - - - - - RECEIVE OUEUE --------'l.,~1 I. ...I------RECEIVE POOL ------'l.,~1
Figure 6. Receive Structures

M68000 FAMilY
REFERENCE

MOTOROLA
7-65

MC68606

CONTROL BITS
CONTROL BITS

NEXT RECEIVE FRAME
OESCRIPTOR POINTER

I'--

DATA BUFFER POINTER

.DATA INDICATION
[ RED LINE
LAST IN POOL

DATA LENGTH

FRAME
TYPE

LUD

TIME STAMP

---+

ERROR CODE

USED ONLY IN
PROMISCUOUS RECEIVE MODE
USED WHEN RECEIVE ERROR
MASK ENABLED

Figure 7. Receive Frame Descriptor
LOGICAL LINK TABLE
(LLlD=O)

RECEIVE POOL NUMBER 1

. RECEIVE POOL POINTERS TABLE
RECEIVE POOL POINTER (01
RECEIVE POOL POINTER (11

.. .
-

··
·

LOGICAL LINK TABLE
(LLlD=4)

r-:

RECEIVE POOL POINTER (151
RECEIVE POOL NUMBER 1

LOGICAL LINK TABLE
(LLID= 52)

RECEIVE POOL NUMBER 18

RECEIVE POOL POINTERS TABLE

RECEIVE POOL POINTER (161
RECEIVE POOL POINTER (171
RECEIVE POOL POINTER (18)

---,
I

RECEIVE POOL POINTER (8191)

RECEIVE POOL 8191
RECEIVE POOL 8190
RECEIVE POOL 8189

RECEIVE POOL 17
RECEIVE POOL 16

Figure 8. Receive Pool Lookup
Information Frame Reception
As the first step in the receive process, the MLAPD must
determine whether the DLel in an incoming frame has been
assigned to an active logical link by Level 3. When the expanded system operation mode is selected by the host, the
MLAPD uses the incoming DLel as an offset into the external
Match Table. If this entry is marked as invalid, then the incoming DLel has not been assigned to a logical link and the
frame is ignored. An error counter is also incremented. The
receive process for expanded system operation mode is shown
in Figure 9.

MOTOROLA
7-66

If the DLel entry is marked as valid, then the entry also
contains an associated logical link identification number
(LLlD). (Level 3 defines a 13-bit logical link identification num. ber corresponding to each active DLel. The LLiD is used during
link level processing and is only of local significance. The LLiD
serves to reduce the external memory requirements for LAPD
processing.) The MLAPD uses the LLiD as an offset into the
LLID-LLT Table to locate this link's Logical Link Table (LLT).
The MLAPD accesses the link's LLT to obtain the specific
protocol parameters for this link which are required for subsequent protocol processing of the received frame. In the case

M68000 FAMILY

REFERENCE

MC68606

of an information bearing frame, the MLAPO uses the receive pool number entry in the LLT as an offset into the Receive-Pool-Pointers Table to locate the first available receive
frame-descriptor for this logical link. (The first 16 pool pointers
are stored on-chip to reduce the number of memory accesses
for the receive operation.) If the receive pool associated with
this logical link is empty or the link's local busy flag is set,
then a Level 2 frame (RNR) is queued for transmission and
the data is ignored. Otherwise the MLAPO continues to process the I frame by comparing the N(S) to the logical link's
state variable V(R), also contained in the LLT. If the frame is
in sequence, then the information field is transferred through
the receive FIFO into the receive buffer. An out-of-sequence
frame causes a Level 2 frame (REJ) to be queued for transmission and the out-of-sequence frame's information field is
discarded. A frame received with an invalid N(R) causes a
Level 2 frame (FRMR) to be queued for transmission (when

the Tx FRMR select option is enabled) and the information
field ofthe frame with an invalid N(R) is discarded.
Lastly the MLAPO checks the CRC of the incoming frame.
If no CRC error is detected, the MLAPO updates the LLT state
variable VIR) and acknowledges the frame reception by
queuing a RR or RNR frame for transmission.
Zero deletion is performed throughout the reception process. The MLAPO requests the system bus when there are at
least four words in the receive FIFO. Frames are received in
sequence as long as memory buffers are available and adequate
bandwidth is provided for OMA on the system bus.
When the application is limited to supporting 16 logical links
or less, the host selects on-chip system operation mode. In
the on-chip operation mode, the OLCI match operation is performed by an internal CAM circuit, reducing external memory
requirements. Figure 10 shows how the MLAPO uses the received OLCI field to search the CAM as part of the receive
process.

INCOMING FRAME
OROER OF RECEPTION

LLID TO LLT
TABLE

MATCH TABLE

OFFSU

{I---.-----'~

8192 WOROS

OFFSET

{I--___~

LOGICAL LINK
TABLE

LlT(X) PTR
LLlD(X)
PARAMETERS
&
STATUS

L--_ _ _~

(2 x MAX # OF LLs) WOROS

Figure 9. Receive Process for Expanded Mode

INCOMING FRAME
ORDER OF RECEPTION

LLID TO LLT
TABLE

MATCH TABLE
CAM

16 '--_ _ _ _ _ _ _

~~-~---I~

LOGICAL LINK
TABLE

OffID {
LLT(X) PTR

MLAPD
LLlD(X)
PARAMETERS

RECEIVE
QUEUE

STATUS
(2 x MAX # OF LLs) WORDS

Figure 10. Receive Process for On"Chip Mode

M68000 FAMILY
REFERENCE

MOTOROLA
7-67

MC68606

XID/UI Frame Reception
The MLAPD handles reception of exchange identification
(XI D) frames, unnumbered information (UI) frames, and
frames containing a user-defined non-standard control field in
a similar manner as I frame reception. Received XID, UI, and
non-standard control frames are placed in the logical link's
receive queue. To differentiate between types of received
frames in the receive queue, the MLAPD encodes the frame_type bits in each receive frame descriptor.
Collecting Received Frames
The user must maintain a user Rx next pointer for each
queue that points to the first recei~e frame to be collected by
the host. The host collects received frames by traversing the
linked list of frame descriptors until a frame. descriptor. is
reached with frame type bits indicating that this frame descriptor still belongs to the receive pool and has not been used
for frame reception. The host may set the data indication bit
in this frame descriptor to request an interrupt on the removal
of this frame descriptor from the receive pool. After collecting
receive frames, the host should update the user_
Rx_next_pointer.

FRAME TRANSMISSION OVERVIEW
TRANSMIT SERVICING SCHEME
The MLAPD services several transmit queues. The frames
in any single queue can be categorized as: Level 2 generated
frames, XID/UI frames" (including non-standard_control

frames), or numbered information (I) frames. A fixed internal
servicing scheme determines when each transmit queue is
handled.
The highest priority transmit queue is the Level 2 Transmit
Queue~ The Level 2 Queue contains unnumbered (U) and supervisory (S) frames generated by the MLAPD in response to
received frames and host commands. These frames are referred to as "Level 2 frames".
The next lower priority transmit queue contains XID and UI
frames for transmission on the logical link specified in the frame
descriptor." It is recommended that system implementations
use this Global XID/UI Queue for frames generated by the
Level 3 management entity. "
The lowest priority transmit queues contain either I frames
or XID/UI frames. The MLAPD supports up to four transmit
I frame queu"es (I frame Queues 0-3) and up to two XID/UI
queues (XID/UI Queues 0,1). The user defines the relative
servicing for these six queues by the MLAPD transmit task by
programming a scan length for each queue. The scan length
defines the maximum number of frames to be transmitted from
the queue before switching to service the next queue. When
a scan length of zero is programmed, the corresponding queue
is never serviced. In this way the user can implement zero,
one, tWo, three, or four queues for I frame transmission, and
zero, one, or two queues for XID/UI frame transmission.
Before each frame from the lowest priority queues is transmitted, the MLAPD transmits all frames in the Level 2 Queue
and all frames in the Global XID/UI Queue. The MLAPD services the lowest priority queues in round robin fashion. The
MLAPD transmit servicing scheme is shown in flowchart form
in Figure 11.

Tx SERVICING SCHEME
I

t
YES

Tx FRAME

LEVEL 2 QUEUE FRAME PENDING?

GLOBAL XID/UI QUEUE FRAME PENDING?

YES

Tx FRAME

YES

SCAN COUNT = SCAN LENGTH n1

USER-DEFINED SERVICING
QUEUE n FRAME PENDING?

YES

Tx FRAME FROM QUEUE n
SCAN COUNT = SCAN COUNT + 1

SERVICE NEXT XID/UI
OR I FRAME QUEUE
SCAN COUNT = 0

I
Figure 11. Transmit Servicing Scheme

MOTOROLA
7-68

M68000 FAMILY
REFERENCE

MC68606

I FRAME TRANSMISSION PROCESS
I Frame Queues and Logical Link Transmit Queues
Each I frame Queue is organized as a linked list, where the
linkage mechanism is implemented by each queued link's
Tx next LLT entry in its associated Logical Link Table (LLT).
To-minimize context switching, each link has its own transmit
queue for I' frames. The Tx next pointer entry in each LLT
points to the first frame descriptor Tn the link's transmit queue.
An I frame Queue is shown in Figure 12.
The host assigns each logical link to one of the four I frame
Queues for all its numbered information frame transmissions.
When the logical link's transmit queue is linked to its assigned
I frame Queue, the pending I frames can be transmitted as
part of the MLAPD transmit servicing scheme.
I Frame Transmission Queueing
When the host has data ready for transmission on a logical
link, the host prepares one or more frame descriptors which
contain information required by the MLAPD to transmit the
associated frame(s). The format of a transmit I frame descriptor
is shown in Figure 13. The host then links the frame descriptor(s) to the desired logical link's transmit queue. The
transmit queue structure for numbered I frames is shown in
Figure 14. If the logical link's transmit queue is empty when
the new frame descriptor(s) is (are) linked to the queue, the
host must issue a DL_DATA_REQUEST command for this link

ON·CHIP REGISTERS
I FRAME OUEUE_i HEAD PTR
I FRAME QUEUE_i TAIL PTR

and specify the head of the transmit queue. This command
causes the MLAPD to place this logical link into'its assigned
I frame Queue for transmit servicing. However, if frames are
waiting for transmission in the link's transmit queue when the
new frame descriptor(s) is (are) added, the linking of the descriptor(s) is sufficient for the associated frame(s) to be transmitted. If all the frames for this logical link were already
transmitted but there are still some frames awaiting acknowledgement, the host must issue a RELlNK_REQUEST command to enable transmission.
MLAPD I Frame Queue Processing
When an information frame is to be transmitted from an I
frame Queue, the MLAPD first fetches the link's context from
its associated Logical Link Table (LLT). This context information is used to build the address and control fields for the
frame; which are then placed in the transmit FIFO. The
Tx next pointer entry in the LLT identifies the address of the
next I frame descriptor to be handled. The MLAPD uses information contained in this frame descriptor to locate the data
to be sent, and then transfers this data into its transmit FIFO.
As the MLAPD sends the frame, zeros are inserted when
necessary for transparency and the MLAPD attaches a frame
check sequence to complete the frame. After frame transmission, VIS) is updated and T200 is started if it is not already
running. The MLAPD sets the transmit bit in the frame descriptor and updates the Tx_next_pointer entry.

LOGICAL LINK TABLE
(LLlO=4)
I FRAME QUEUE i
Tx NEXT ACKNOWLEOGE PTR
Tx NEXT PTR
Tx NEXT LLT PTR

LOGICAL LINK TABLE
(LLlO=6)

TRANSMIT QUEUE

I FRAME QUEUE i
Tx NEXT ACKNOWLEDGE PTR
Tx NEXT PTR
Tx NEXT LLT PTR

LOGICAL LINK TABLE
(LLlD=3)

TRANSMIT QUEUE

I FRAME QUEUE i
Tx NEXT ACKNOWLEDGE PTR
Tx NEXT PTR
Tx NEXT LLT PTR

Figure 12. I Frame Queue Structure

M68000 FAMILY
REFERENCE

MOTOROLA
7-69

MC68606

STATUS BITS
STATUS BITS
[

NEXT TRANSMIT FRAME
DESCRIPTOR POINTER

DATA BUFFER POINTER

EMPTY
ACKNOWLEDGE
TRANSMIT

.--'--

CONTROL BITS
CDNTROL BITS/DATA LENGTH

[

LAST
HEADER VALID

NOT USED * *

10
12
14

HEADER BUFFER POINTER

lOPTIONAL
HEADER LENGTH
OPTIONAL FOR I FRAMES ONLY

RETRANSMISSION CDUNT

**Contains frame type and LLiD for XID/UI fra~es.
Contains CRC enable and address enable bits for non-protocol links.

Figure 13. Transmit Frame Descriptor

IMLAPD) Tx NEXT POINTER
USER Tx NEXT CONFIRM POINTER

IMLAPO) Tx NEXT ACKNOWLEDGE POINTER

1+------ CONFIRMED - - - - - - - ' l..~1

USER Tx LAST QUEUED POINTER

1. .....-------- ACTIVE TRANSMIT QUEUE - - - - - - - - l..~1

Figure 14. Logical Link Transmit Queue Structure

Transmission begins when ten bytes are present in the transmit FIFO, in addition to the address and control fields, or when
the entire frame is present in the transmit FIFO. Between
frames the MLAPD transmits the user selected number of pad
flags. Additional flags may be transmitted, until the requirements for start of transmission are met. While transmitting a
frame, the MLAPD requests the system bus when there are
six to eight empty bytes in the transmit FIFO.
The MLAPD continues transmitting frames for the same
logical link until one of the following events occur:

The MLAPD may also temporarily remove this link's transmit
queue from its I frame Queue as the result of link conditions
and host commands. The link conditions that cause removal
are:
•
•
•
•
•

Remote busy condition;
Outstanding remote status request (command frame
sent with poll bit set to one);
Outstanding frames limit (K);
Link reset;
Timer recovery condition .

• The logical link's' transmit queue is exhausted;
• The MLAPD transmitter switches to service another
queue according to the transmit servicing scheme.

MOTOROLA
7-70

M68000 FAMILY
REFERENCE

MC68606

Stopping I Frame Transmission
At any time, the host may instruct the MLAPD to immediately suspend all transmit activity for a logical link's transmit
queue by issuing a STOP_TX_I command. Upon receiving this
command, the MLAPD aborts any current frame transmission
for this link and removes the specified link from its assigned
I frame Queue. The host is later notified when all outstanding
acknowledgments have been received. At this point, the host
is free to manipulate the transmit queue as desired, since the
MLAPD is deactivated for that queue. This stop mechanism
may be used to provide faster servicing of certain I frames or
this mechanism may be necessary for various types of error
recovery.
Collecting Acknowledged I Frames
To collect acknowledged frames, the host reads the status_bits in each frame descriptor, beginning with the frame
descriptor indicated by the· user Tx next confirm pointer.
When the acknowledge bit is set, the-associated data buffer
has been transmitted and acknowledged. Acknowledged
frames may be collected by the host dynamically (while other
frames await acknowledgement) or after being notified by the
MLAPD that all frames in the queue are acknowledged via a
DL_data_confirmation interrupt. The host should update the
user_Tx_next_confirm _pointer after each frame is collected.
XID/UI FRAME TRANSMISSION PROCESS
XID/UI Transmit Servicing
An XID/UI frame may be an unnumbered information (UI)
frame, an exchange identification (XID) frame, or a frame with
a user~defined non-standard_control field. In most ISDN applications it is anticipated that these frames will be used infrequently by Level 3 entities. However in some applications,
such as bridges which interface to connectionless-oriented
networks, UI frames may be used heavily for data transfer.
To address the varying usage of XID, UI, and non-standardcontrol frames, the MLAPD provides two methods of ser~icing XID/UI queues. When frames are queued to the Global
XID/UI Queue, the MLAPD will transmit all pending frames

each time this queue is serviced. When frames are queued to
either XID/UI Queue 0 or XID/UI Queue 1, the MLAPD will
transmit only the number of frames specified by the corresponding user-defined scan length. It is recommended that
the Global XID/UI Queue be reserved for management information exchange.
All XI D lUI queues are linked lists of frame descriptors, where
the frame descriptor specifies the logical link associated with
the queued frame and the frame type. The structure o(the
XID/UI queues is shown in Figure 15.
XID/UI Frame Transmission Queueing
When XID/UI (or non-standard control) information is
ready for transmission on a logicallini, the host prepares one
or more frame descriptors which contain.the information required by the MLAPD to transmit the frame(s). Then the host
links the frame descriptor(s) to the appropriate XID/UI queue,
depending on the servicing desired by the host for these
frames. If the queue is empty when the new frame descriptor(s)
is (are) linked, the host must issue the appropriate command
(GLOBAL XID/UI REQUEST, XID/UI QUEUE 0 REQUEST,
or XID/UI- QUEU{ 1 REQUEST) and specify the head of this
queue. When this command is issued, the MLAPD places the
corresponding XID/UI queue into the transmit servicing
scheme. If frames are awaiting transmission when the new
frame descriptor(s) is (are) added, the linking· of the frame
descriptor(s) is sufficient for the associated frame(s) to be
transmitted.
MLAPD XID/UI Queue Processing
When an XID/UI or non-standard control frame. is to be
transmitted, the MLAPD uses the LLIDentry in the frame
descriptor to index into the LLID-LLT Table to obtain the appropriate DLCI for the frame. The MLAPD places this DLCI
and the correct control field into its transmit FIFO. Next, the
address of the frame data is read from the frame descriptor
and the MLAPD transfers this data into the transmit FIFO. As
the frame is transmitted, zeros are inserted when necessary
for transparency. CRC is calculated and appended to complete
the frame.

(MLAPDI XID/UI Tx NEXT POINTER
USER XID/UI Tx LAST QUEUED POINTER
USER XID/UI Tx NEXT CONFIRM POINTER

TRANSMITTED

-------I~

. . . - - - - - - - - - ACTIVE TRANSMIT QUEUE - - - - - - - -..
~I

Figure 15. XID/UI Queue Structure

M68000 FAMILY

REFERENCE

MOTOROLA
7-71

MC68606

Stopping XU)/UI Frame Transmission
At any time the host may instruct the MLAPD to immediately
suspend all transmit activity for the Global XID/UI Queue, for
XID/UI Queue 0 or for XID/UI Queue 1. This result is produced by the -corresponding STOP TRANSMIT command
(STOP GLOBAL XID/UI, STOP XID/lJl QUEUE 0, or STOP
XID/UI QUEUE -11. Upon recei~ing one- of these commands~
the MLAPD aborts any current XID/UI (or non-standardcontrol) frame transmission and does not service additional
XID/UI frame descriptors in the specified queue. At this point,
the host is free to manipulate the queue as desired, since the
MLAPD is deactivated for that queue. This stop mechanism
may be used to provide faster servicing of certain XID, UI, or
non-standard control frames for a particular logical link, or
this mechanism may be necessary for various types of error
recovery.
Collecting Transmitted XID/UI Frames
The collection of transmitted XID/UI frames is the same for
all three XID/UI Queues. To collect transmitted frames, the
host reads the status bits in each frame descriptor, beginning
with the frame descriptor indicated by the user XIDI
UI T.x next confirm pointer associated with the queue. When
either the positive confirmation bit or the negative confirmation bit is set, the associated data buffer has been handled
by the MLAPD.
The positive confirmation bit indicates that the associated
data buffer has been transmitted, while the negative confirmation bit indicates that the associated data buffer cannot be
transmitted. A negative indication is generated when a frame
transmission is requested in conflict with the services available
in the current link state (TEl UNASSIGN or EST WAIT TEl).
The host should later resubmit the DL_Ul frame for
transmission.
Transmitted frames may be collected by the host dynamically (while other frames await transmission) or after being
notified by the MLAPD via an XID/UI confirmation interrupt
that all frames in the queue have been sent. After each frame
is collected from an XID/UI queue, the host should update
the associated user XID/UI_Tx_next_confirm_pointer.

MLAPD IMPLEMENTATION OF SPECIAL MODES

the associated frames to be transmitted. Note that for nonprotocol links, the MLAPD does not recognize any incoming
acknowledgements and the RELlNK_REQUEST command is
not meaningful.
MLAPO Frame Transmission
When a frame is to be transmitted for a non-protocol link,
the MLAPD first fetches the link's context from its LLT. Then,
based upon the transmit address enable bit in the frame descriptor, the MLAPD mayor may not append the DLCI associated with this logical link to the beginning of the transmit
frame. Next the MLAPD uses the information contained in the
frame descriptor to locate the transmit memory buffer, and
then transfers this information into its transmit FIFO. The
MLAPD transmits the frame inserting zeros when necessary
for transparency. After the transmit buffer is transmitted, the
MLAPD mayor may not append a CRC to the frame, based
upon the transmit CRC enable bit in the frame descriptor.
Transmission begins when ten bytes are present in the transmit FIFO or when the entire frame is present in the transmit
FIFO. Between frames the MLAPD transmits the user selected
number of pad flags. Additional flags may be transmitted, until
the requirements for start of transmission are met. While transmitting a frame, the MLAPD requests the system bus when
there are six to eight empty bytes in the transmit FIFO.
Once the MLAPD begins handling a non-protocol link's
transmit queue, the MLAPD will continue servicing the queue
until all frames are transmitted or until the scan length associated with the I frame Queue is exhausted.
Stopping Frame Transmission
At any time, the host may.instruct the MLAPD to immediately suspend all transmit activity on a non-protocol link by
issuing a STOP TX I command. Upon receiving this command, the MLAPD a-borts any current frame transmission for
this link and does not service additional frame descriptors. At
this point, the host is free to manipulate the transmit queue
as desired, since the MLAPD is deactivated for this link. This
stop mechanism may be used to provide faster servicing of
certain frames for this link or this mechanism may be necessary
for various types of error recovery.

NON-PROTOCOL LINKS

Collecting Transmitted Frames

The M LAPD can simultaneously support links which operate
according to the LAPD protocol and links which do not operate
according to the LAPD protocol. The host specifies that the
link will operate in non-protocol mode by programming the
non-protocol select bit in the link's Logical Link Table. When
supporting a-non-protocol link, the MLAPD functions as a
HDLC framer with DMA capability.

To collect transmitted frames, the host reads the status_bits
in each frame descriptor, beginning with the frame descriptor
indicated by the user Tx next cOhfirm pointer. When the
transmit bit is set, the associated data buffer has been transmitted. Transmitted frames may be collected by the host dynamically (while other frames await transmission) or after being
notified by the MLAPD that all frames in the queue are transmitted via a DL data confirmation interrupt. The host should
update the use;:- Tx ~ext confirm pointer after each frame is
collected.
- -

Queueing Frames for Transmission
To queue frames for transmission on a non-protocol link,
the host first creates a transmit queue. The structure of the
transmit queue is identical to a transmit queue which is used
for I frames for LAPD links. To enable transmission of the
transmit queue for a non-protocol link, the host issues a
DL DATA REQUEST command which causes the MLAPD to
place this iOgicallink into its assigned I frame Queue for transmit servicing. If the host adds frames to a non-empty transmit
queue, the linking of the frame descriptor(s) is sufficient for

MOTOROLA
7-72

Receive Structures
The receive structures for a non-protocol link are identical
to the structures for a LAPD link. A non-protocol link is assigned to a receive pool by the· host using the receive_
pool number entry in the link's LLT. Any number of links may
share a receive pool, although it is anticipated that most system

M68000 FAMILY

REFERENCE

MC68606

implementations will not assign LAPD links and non-protocol
links to the same receive pool. Note that the N201_value specified for a non-protocol link defines the maximum length for
a received frame.
MLAPD Frame Reception
As an incoming frame is received in on-chip system operation mode, the DLCI field in the frame is compared to the
on-chip CAM to identify the corresponding logical link, if any.
In expanded system operation mode, the MLAPD accesses
the external Match Table to determine the associated logical
link. If no DLCI match is found, then the incoming DLCI has
not been assigned to a logical link, and the frame is ignored.
If a DLCI match is found, the corresponding entry in the
Match Table or CAM specifies both the LLiD and whether the
link is assigned to LAPD protocol operation or non-protocol
operation. If the frame is for a non-protocol link, the MLAPD
proceeds to locate a free buffer to store the information between the opening and closing flags of the frame, minus the
16-bit address field. (The associated LLiD is written into the
frame descriptor.) The MLAPD locates the link's receive pool
by using the link's receive_pool_number LLT entry to index
into the Receive Pool Pointers Table. If the receive pool associated with this logical link is empty, then the frame is ignored
and a local busy interrupt is generated.
Otherwise the MLAPD begins to transfer the frame into the
memory buffer. During frame reception, the MLAPD performs
zero deletion, checks for receive errors, and calculates the
CRC. The host may save erroneous frames for inspection based
upon a non-protocol_error_mask. For non-protocol links, the
host may also choose to have the MLAPD access multiple
receive buffers as needed to store a received frame.
PROMISCUOUS RECEIVE MODE
Promiscuous receive mode is a special case of non-protocol
link operation. This mode only affects the MLAPD receiver
operation; the MLAPD transmitter operation is not affected.
When promiscuous receive mode is selected, the MLAPD does
not perform LAPD frame processing on the incoming serial
bit stream. The MLAPD strips flags, performs zero deletion,
and checks the frame CRC .. No address matching or control
field analysis is performed. The entire frame, as delineated by
the HDLC flag characters, is stored in memory. The MLAPD
uses the receive pool assigned by the host to the logical link
associated with DLCI = O.
The host may choose to accept erroneous frames based
upon the non-protocol_error_mask. The host may also choose
to have the MLAPD access multiple receive buffers as needed
to store a received frame. As each receive buffer is filled, the
MLAPD writes a time stamp into the associated frame descriptor. This time stamp indicates the "time", with respect
to an internal 32-bit timer, when the MLAPD completed transferring the incoming frame to the receive buffer. When the
MLAPD is in promiscuous receive mode, the host may enable
a filtering option which allows the host to selectively receive
frames from the serial link based upon the first 32 bits of each
frame. This provides a built-in logic analyzer trigger-type diagnostic capability.
LINE MONITOR
This mode allows the user to monitor all the bits on the data
link. When the RSTART pin is asserted, the receive operation

M68000 FAMILY

REFERENCE

begins. As long as RSTART remains asserted, the chip will
pack all received bits to words and write them into receive
buffers from a single receive pool. This mode may be very
useful in analyzing line problems, bit errors, zero insertion
errors and special bit patterns such as flags, abort, and idle
sequences, that are not normally dumped into memory.
SYSTEM LOOPBACK TESTING
To allow the MLAPD to perform the LAPD procedures during a system loop back test, the MLAPD provides a "flip"
option. When enabled, the MLAPD will invert the least significant bit of the DLCI field for each received frame. To implement this mode, the host activates pairs of logical links with
DLCls that differ only in the least significant bit position. For
each pair, one link is assigned as network and the other link
is assigned as user. Then when a frame is transmitted for one
logical link, it is received for the other logical link. Thus enabling
the MLAPD to implement the LAPD procedures while in loopback mode.
The system loopback can be internal or external. When
internal loopback is selected, the host may also specify that
any bits received on RxD should be echoed back to the network
on TxD. Note that when the flip option is not enabled, the
host may only operate non-protocol links under the internal
or externalloopback configuration.
MEMORY-TO-MEMORY OPERATION
The MLAPD can be configured for operation in systems
which do not implement a non-channelized serial interface,
such as channelized T1 networks or LANs. It is assumed that
a device in the system, labeled "Device A" in Figure 16, directly
interfaces to the physical level. Received frames are placed
into memory and transmit frames are placed into Device A
using either DMA or host I/O capabilities. In memory-to-memory operation, the MLAPD performs the LAPD procedures on
these memory resident receive and transmit frames. This mode
allows the system designer to select the MLAPD to implement
the LAPD procedures independent of the physical level characteristics of the system.
To enable memory-to-memory operation, the host sets an
option bit in the Global Configuration Block. In this configuration: the MLAPD transmitter and receiver are internally
connected. The RxD and TxD pins are not used. The MLAPD
on-chip DMA controller feeds the receive and transmit machines via their associated FIFOs. The host activates a logical
link with DLCI = 0 as a non-protocol link and assigns this link
to I frame Queue O. Note that I frame Queue_0 should be
reserved for use -only by this logical link associated with
DLCI=O.
As frames are received from the physical level, the host is
responsible for placing these received frames into the memory
format defined for a MLAPD transmit queue. Each transmit
buffer contains an entire received frame. The host then issues
a DL DATA REQUEST with the LLiD associated with DLCI = 0
as command argument 1 and the address of the first transmit
frame descriptor as command argument 2. In response, the
MLAPD begins transmitting frames from I frame Queue_O
according to the transmit servicing scheme described in Transmit Servicing Scheme. Since the logical link associated with
DLCI =0 is assigned to non-protocol operation, the MLAPD
acts as a simple HDLC framer. The MLAPD may optionally

MOTOROLA
7-73

MC68606

add the frame CRC as described in MLAPD Frame Transmission. The frame address should be contained in the transmit data buffer (passed through from the physicallevell. When
the frame is received via the internal loopback path, the
MLAPD analyzes the address field, .determines whether the
addressed logical link is assigned to LAPD or non-protocol
operation and then handles the frame as described in Information Frame Reception, XID/UI Frame Reception, and
MLAPD Frame Reception. The MLAPD continues to transmit frames from I frame Queue 0 until the scan length specified
for I frame Queue 0 is exhausted or until all queued frames
are transmitted. A DL data confirmation interrupt is issued to
the host when all frames are transmitted. This interrupt indicates that all frames received from the physical level have been
handled by the MLAPD. Level 3 collects the received I, XID,
UI, and non-standard control frames for the various logical
links as described in Collecting Received Frames.
The memory-to-memory operation mode does not affect

the procedure for passing transmit frames from Level 3 to the
MLAPD for Level 2 handling. Level 3 queues I, XID, UI, and
non-standard control frames to the Global XID/UI Queue, I
frame Queues 1-3, and XID/UI Queues 0,1. The MLAPD independently generates U and S frames-and places them on
the Level 2 Queue. The transmit servicing scheme for these
transmit queues and the protocol actions provided by the
MLAPD are unchanged. During the transmit process, the
MLAPD appends the appropriate DLCI, control field and CRC
to queued transmit frames for LAPD links, and the MLAPD
may optionally append theDLCI and CRC for non-protocol
links. As each transmitted frame is received via the internal
loopback path, the MLAPD receiver handles the frame as for
promiscuous receive mode; The entire frame is stored in memory. The MLAPD uses the receive pool assigned by the host
to the logical link associated with DLCI = O. It is the responsibility of the host to enable transmission of these frames by
the physical level.

Rx POOLS/QUEUES
NON·PROTOCOL Tx
PROMISCUOUS Rx

c8§

PROTOCOL Ax
PROTOCOL Tx

Rx
POOL/OUEUE
DLCI=O

I FRAME
QUEUE 0

MLAPD

LEVEL 2
QUEUE

"DEVICE A"

PHYSICAL LEVEL

I
GLOBAL
XIO/UI
QUEUE

J
I FRAME
QUEUES
1-3

I
XIO/UI
QUEUES
0.1

+
Figure 16. Memory-to-Memory Operation

MOTOROLA

7-74

M68000 FAMILY

REFERENCE

MC68606

PIN ASSIGNMENT

PIN GRID ARRAY
0

CLK

GNO

RxO

VOO

RCLK

VOO

A23

GNO

AlB

VOO

GNO

MOTOI

RTSI
TSTART

TxO

VOO

A20

A19

A17

A15

iNf

RESET

RETRY

GNO

CTSI
RSTART

GNO

TCLK

A22

A16

VOO

A14

lACK
(lNTA)

BERR

HALT

A13

A12

GNO

iiG

iiii

(HOLOA) (HRQ)

iiiii

GNO

OTACK
(REAOY)

BOTTOM
VIEW

(lNTR)

0
RfiJ
(WR)

0
All"

0
AID

VOO

GNO

BGACK

VOO

UOSIAO
(AD)

VOO

(iiii)

0'
A21

LOS
(BHE)

GNO

VOO

010

012

GNO

015

011

013

014

A3
10

M68000 FAMILY
REFERENCE.

MOTOROLA

7-75

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

M68606ESP

Product Preview

Evaluation and Support Package (ESP) for
the MC68606
The M68606ESP is a tool intended for evaluating'the MC68606 multi-link access procedure
(MLAPD) protocol controller as well as developing and debugging MC68606-based products. The
Motorola MC68606 MLAPD is an integrated circuit that implements the link access procedure
(LAPD) protocol. The M68606ESP provides the user with both hardware and software platforms for
developing MLAPD applications as indicated in Figures 1 and 2.
The ESP hardware consists of a single board, which may be run as a stand-alone unit or connected to other devices, such as a host or printer, by serial or parallel I/O interfaces. The MC68606
serial interface signals are TIL buffered and made available to the user through a connector.
Through this connector, the user can run the MLAPD serial clocks at a variable speed (e.g., dc to
2.048 Mbps) and interface to other devices, such as another ESP or a protocol analyzer. As shown
in Figure 1, this package requires a power supply, an external clock generator for the MC68606 receive and transmit clocks, and a VT100-compatible CRT. The hardware features of the M68606ESP
.
are as follows:
•
•
•
•
•
•
•
•

Stand-Alone Operations (i.e., No Host Computer Necessary)
MC68606 Running at 16.67 MHz
MC68020 Running at 16.67 MHi
1/2-Mbyte Dynamic RAM
256-Kbytes EPROM
2-Kbytes EEPROM
Two RS-232 Serial Ports (Terminal and Host)
Parallel I/O Interface (Host or Printer)

To ease integration of user prototype software products with the MC68606, the ESP software provides powerful windows to all of the MC68606 memory structures and high-level software interfaces. The ESP software consists of two main modules provided in EPROM. The first module fully
implements the layer-3 protocol defined for ISDN primary rate and DMI mode-3 data-transfer applications, namely CCITI Recommendation X.25 data phase. Shown in Figure 2, the source code for
this module, called M68606SW3D, is also available. The layer-3 software accesses the MC68606 by
a set of chip drivers, which comprise the layer 2/3 interface. The second module provides a menudriven interface to the MC68606. This module includes the MC68606 chip drivers shown in Figure 2.
The menus provided enable the user to issue single commands to the MC68606, to read and write
all MC68606 memory structures, and to single-step execute protocol primitives at either layer 2 or

3.
The main software features are as follows:
• X.25 Data-Phase Layer-3 Protocol
• User-Software Interface from Either Layer 2 or 3
• MC68606 Chip Drivers
• Menu-Driven Software Allows User to Perform:
- Single Command Loading of MC68606
- Symbolic ReadIWrite Access to All MC68606 Memory Structures
- Execution of Single Protocol Primitives at Lay~r 2 or 3
• Board-Level Monitor

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA _
MOTOROLA
7-76

M68000 FAMILV
REFERENCE

MC68606ESP

+5V
+12 V
-12 V
GND

B G

SERIAL
CLOCK
FOR
MC68606

RS-232
INTERFACES
AND
PARALLEL
PORT

RAM
EPROM
EEPROM

VT100

Figure 1. M68606ESP Minimum-Hardware Support

LAYER 4 TO LAYER 3 INTERFACE

M68606SW3D

X.25 DATA PHASE

-=::::::>

USER
SIGNALING
SOFTWARE

LAYER 3 TO LAYER 2 INTERFACE

LAYER 3

LAYER 2

MC68606 CHIP DRIVERS

MC68606 CHIP
Q.921 LAPD PROTOCOL

Figure 2. M68606ESP Software Support

M68000 FAMILY

REFERENCE

MOTOROLA
7-77

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68824

Technical Summary

Token-Passing Bus Controller (TBC)
The Motorola MC68824 Token Bus Controller (TBC) is a silicon integrated circuit which implements the Media
Access Control (MAC) function for an IEEE 802.4 LAN station anq the receiver portion for IEEE 802.2 Logical Link
Control (LLC) type 3 as well as providing support for LLC type 1 and type 2 (see Figure 1). IEEE 802.4 defines the
physical and MAC portion of the data link layer of the Manufacturing Automation Protocol (MAP) specification. The
LLC functions implemented on chip are those associated with real time applications, namely "Acknowledged Connectionless Service" (type 3) as required in the Enhanced Performance Architecture (EPA) specified in Manufacturing
Automation Protocol (MAP) 3.0.

EZ:d SPECIFIED BY MAP 3.0
r - -, MC68824 SUPPORTS

L_.J LCC TYPE 1 AND 2

1::::::::::::;:1

DATA
LINK
LAYER

MC68824 IMPLEMENTS MAC
AND RECEIVER PORTION
OF LLC TYPE 3

PHYSICAL
LAYER

Figure 1. IEEE Standard Model

The
•
•
•
•

major features of the MC68824 are:
Implementation of the MAC portio.n of the IEEE 802.4 Standard
Implementation of the Receiver Portion of IEEE 802.2 LLC Acknowledged Connectionless Service (type 3)
Support of IEEE 802.2 LLC Type 1 and Type 2
.
Support of ANSI/ISA-n.01 PROWAY PLC Send Data with Acknowledge (SDA) and Request Data with Reply
(RDR)

• MAC Options Suitable for Real Time Environments
- Four Receive and Four Transmit Queues Supporting Four Priority Levels
- Immediate Response Mechanism
• On-Chip Network Monitoring a~d Diagnostics
• Simple Interface to Higher Level Software by means of Powerful, Fully Linked Data Structure
• Options for Bridging Include: Hierarchical and IBM Defined Source Routing as well as Support for Flat Bridges
• Powerful Addressing; Group Address Recognition and Multidrop Capability
• Contains Several Modes to Increase Reliability and Flexibility Including:
- Reduced Data Structure Mode ·for Increased Performance
- Control Frame Preference for Increased Reliability
- Address Comparison Options for Increased Performance
- Bus Analyzer Mode to Enable Running the ·T·BC as a Powerful Protocol Analyzer
- Continued -

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA·_
MOTOROLA

7-78

M68000 FAMILY

REFERENCE

MC68824

Features (Continued)
•
•
•
•

System Clock Rate up to 16.67 MHz
Serial Data Rates from 10 Kbits/Second to 12.5 Mbits/Second
IEEE 802.4 Recommended Serial Interface Supporting Various Physical Layers
Highly Integrated M68000 Family Bus Master/Slave Interface
- Four Channel DMA for Transfer of Data Frames to and from Memory
- 40-Byte FIFO to Efficiently Support High Data Rate
- 32-Bit Address Bus with Virtual Address Capabilities
• Simplified Interface to Other Processor Environments
- Byte Swapping Capability for Alternate Memory Structures
- 8- or 16-Bit Data Bus
• Low Power Consumption through 1.5 Micron HCMOS Fabrication

GENERAL DESCRIPTION
The TBC functions as an intelligent peripheral device
to a microprocessor. An on-chip DMA transfers data
frames to and from a buffer memory with minimal microprocessor interference required. A microcoded fully
linked buffer management scheme queues frames during
transmission and reception, and optimizes memory use.
The TBC simplifies interfacing a microcomputer to a token bus network by providing the link layer services including: managing ordered access to the token bus
medium, providing a means for admission and deletion
of stations, and handling fault recovery. This allows the
host to operate almost totally isolated from the task of
ensuring error free transmission and reception of data.
The TBC can be used in a var-iety of machines in the
factory from programmable controllers to large computers. Although token bus is especially well suited to
the factory because of its deterministic characteristics,
the TBC can be used in other networking applications
such as office automation. The TBC provides the capability to swap the byte ordering of data to support alternate memory organizations. Additionally, the TBC is a
full M68000 bus master, providing on-chip DMA capability for management of memory tables and frame buffers. Since the TBC bus interface is configurable; the TBC
can handle both 8-bit and 16-bit data transfers. Figure 2
shows the TBC in a typical intelligent I/O processor system environment.

The following sections summarize the MC68824's operational modes, data structures, and commands. Refer
to Table 1 for an explanation of the abbreviations used
throughout this document.

INTERNAL ARCHITECTURE
The TBC has four functional blocks including: serial,
DMA, microcoded controller, and register file/ALU. Each
of these sections contain user visible and non-visible registers that define control and operation of the TBC. A
block diagram of the MC68824 is shown in Figure 3.
Because the TBC communicates with the host primarily
through shared memory, a minimum number of host
processor accessible registers are required. These directly accessible registers include the command register,
semaphore register, interrupt vector register, and data
register. Internal registers not directly accessible to the
host processor can be accessed through the initialization
table in shared memory.

OPERATIONAL MODES
The MC68824 has three main operational modes, TBC
mode, EPA mode, and Bus Analyzer mode. In the TBC
mode, which is the default mode, the MC68824 provides
a full MAC implementation; it only supports and does

STANDARD
MAC-PHYSICAL
INTERFACE

COAX
CABLE

Figure 2. Token Bus LAN Node

M68000 FAMILY
REFERENCE

MOTOROLA
7-79

MC68824

Table 1. Abbreviations
Abbreviation
ACM
BD

Explanation

Abbreviation

Access Control Machine

Logical Link Control

LLC

Buffer Descriptor

LSAP

Link Service Access Point

Cyclic Redundancy Check

LSDU

Link Service Data Unit

Destination Address

MAC

Media Access Control

Data Buffer

RDS

Reduced Data Structure

RWR

Request with Response

CRC

DMA

Direct Memory Access

DSAP

Destination Service Access Point

Receive

EOQ

End of Queue

Source Address

EPA

Enhanced Performance Architecture

FD
HOQ
IA

SSAP

Frame Control

Source Service Access Point
Token Bus Controller

TBC

Frame Descriptor

This Station Address

Head of Queue

Transmit

Individual Address

SYSTEM INTERFACE
INTERN AL
DATA Bus

,~
\~

BUS INTERFACE

DMA

CONTROL BUS

MICROCONTROLLER

r
~

I
I
I
I
II

-- ----------,
I -

FIFO

I
~

SERIAL

I
I

I
RECEIVE AND
TRANSMIT
MACHINES

--.

I
I
I

PHYSICAL
LAYER
SERIAL
INTERFACE

Figure 3. MC68824 Block Diagram

MOTOROLA
7-80

M68000 FAMILY

REFERENCE

MC68824

not implement LLC type 3. Running in the default mode
allows the userto perform the LLC functions or equivalent
in software. In the EPA mode, the MC68824 performs the
receiver portion of the 'Acknowledged Connection less
Service' of the LLC type 3 sublayer, as well as operating
normally when a non-request with response frame is received. In the Bus Analyzer mode, the MC68824 is not
part of the logical ring. In this mode, the MC68824 receives all frames which makes the TBC an ideal chip to
be used in a protocol analyzer application. The MC68824
also offers several additional modes and options which
can be used to tailor the TBC to a specific application.
The TBC/EPA mode is selected via the Mode Selector
Word located in the initialization table. Several other options are available to the user by using the SET MODE
commands. Table 2 summarizes all the modes available
on the MC68824 while running in either the TBC mode
or the EPA mode excep.t where noted. Refer to Table 1
for the explanation of abbreviations.

Interrupt Status Words Definitions
Interrupt Status Word 1

Interrupt Status Word 2

TBC Command Complete
Frame Descriptor Pool Empty
Buffer Descriptor Pool Empty
Transmit Queue Empty
Token Skipped
Token Passed
Bus/Address Error
Frame Descriptor Pool Low
Buffer Descriptor Pool Low
Overrun
Underrun
Transmitted RWR Frame
Transmitted Response Frame
Transmitted Data Frame
Received RWR Frame
Received Data Frame

Duplicate MAC Address
Detected
Faulty Transmitter
Successor Changed
No Successor/No Successor 1
Unexpected Frame 6
Solicit Any Arc of the ACM
Performed
Unexpected Frame 10
Receive Claim Token
No Response Received (ACM
in the Await Response
State)
Win Address Sort
Bus Idle Timer Expired
Threshold Counter Exceeded
Lose Address Sort
Modem Error

SHARED MEMORY STRUCTURES
The TBC and host processor communicate through a
memory structure which consists oftwo tables and a fully
linked buffer structure. The initialization table allows the
host processor to set and update the TBC operating parameters and table pointers, and to receive status and
error information. The TBC is given a pointer to the initialization table during initialization. The private area is
the other table which is used by the TBC to store MAC
parameters. The fully linked buffer structure consists of
frame descriptors, buffer descriptors, and data buffers.
There is one frame descriptor for each frame. Each frame
descriptor contains pointers to a buffer descriptor which
in turn points to a data buffer where the message data
is stored. If more than one data buffer is needed, the
buffer descriptor will point to another buffer descriptor
which in turn points to another data buffer.
INITIALIZATION TABLE
The initialization table format is shown in Table 3. The
first 124 bytes (0-7C hex) initialize the TBC and the TBC's
private area in memory. The command parameter area
(CPA) is most frequently used by the host to set and read
internal TBC parameters. The CPA is divided into the
command area and the command return area. The commands dedicated to reading and setting internal TBC parameters are SET ONE WORD, SET TWO WORDS, and
READ VALUE.
The TBC continuously updates the two Interrupt Status
Words as status changes. The interrupt status word, combined with the interrupt status mask, determines whether
an interrupt will be generated. If an interrupt condition
occursand the corresponding bit in the interrupt status
mask is set the MC68824 will assert IRQ. The host must,
after determining the interrupting event, issue a CLEAR
INTERRUPT STATUS command which will negate IRQ
and clear the interrupt bit. The following lists the events
which are updated in the interrupt status words by the
TBC.

M68000 FAMILY
REFERENCE

The initialization table also contains statistics about the
operation of the network. The statistics are 16-bit wrap
around counters. Every counter has a threshold variable
which the TBC checks against. If the threshold is reached,
the host may be notified through the interrupt status bit.
The host may select to collect all statistics or may disable
the collection of the two most frequent statistics which
are number of tokens passed and number of tokens heard.
When the MC68824 is the EPA mode, the initialization
table must be extended by 1024 words to accomodate
the LSAP table. The LSAP table consists of 2 x 128 entries,
one for each possible LSAP address, individual and group.
Each ofthe first 128 entries represents an individual LSAP
while each of the following 128 entries represents group
LSAPs. Figure 4 shows the format of each entry in the
LSAP table, while Table 4 shows the entries in the initialization table which are different when the MC68824 is
in the EPA mode.
Note that if the MC68824 is running in the EPA mode
and the user wishes to enable the flow control mode, the
initialization table must be extended beyond the LSAP
table by 512 words to accomodate the message counter
table.
PRIVATE AREA
The MC68824 private area is a 128-byte area of RAM
reserved for use by the TBC to store internal variables
and statistical information associated with the MAC operation. During initialization, the host specifies the appropriate initial values of the private area parameters in
the initialization table (see displacement 08 hex through
76 hex in the initialization table shown in Table 3). The
private area should never be directly accessed by the host
as this would not guarantee IEEE 802.4 operation. The
parameters in the private area must only be set and read
by the SET/READ VALUE commands. When the MC68824
is operating in the EPA mode, the private area must be
doubled to 256 bytes to provide for extra storage to save
protocol variables.

MOTOROLA
7-81

MC68824

Table 2. M,C68824 Modes and Options
Description

Selected By

EPA

Enables the TBC to implement LLC type 3 functions. The TBC
mode is the default

Mode Selector Word

Reduced Data Structure

Optimizes the number of back to back frames the TBC can
receive by modifying the frame structures in memory

Mode Selector Word

Copy all Data Frames

Determines whether the TBC copies to men-lOry all non RWR
data frames that are heard. Station may still be part of logical
ring. Useful mode for bridge implementations. Valid only in
Reduced Data Structure Mode.
-

Mode Selector Word

Control Frames Preference

Ensures that the TBC will not lose control frames if adequate
system performance is provided

Mode Selector Word

No Mask Mode

Indicates to the TBC that only individually addressed frames with
DA = TS exactly or all group addressed frames regardless of the
mask will be received

Mode Selector Word

Receive Erroneous Frames in RDS

Allows the TBC to store erroneous frames while in the
reduced data structure mode

Mode Selector Word

MAC Address Length

Allows the user to select 16- or 48-bit MAC addresses

Mode Selector Word

Bus Analyzer

Enables the bus analyzer mode

SET MODE 1

Copy Frames with Undefined FC

Allows user to store frames with undefined frame control.

SET MODE 1

Copy all Control Frames

May be used to set the TBC in promiscuous mode to monitor
network traffic

SET MODE 1

Limited Statistics Tracking

TBC can keep track of all statistics or of a subset
(see Initialiiation Table).

SET MODE 1

Response SA Filtering

Allows the TBC to selectively store response frames according
to a mask on the SA while running in the EPA mode only

SET MODE 1

Lower Bridge Mode

Puts the TBC in lower bridge mode which is used in
hierarchical 'bridging

SET MODE 2

In_ring Desired

Determines whether or not the TBC is a member of the logical
ring while in the steady state condition

SET MODE 2

Source Routing Limited Broadcast

If source routing is enabled then broadcast frames can be
recognized

SET MODE 2

Bridge Delay Mode

To be used in bridges when SA can be unequal to TS for long
distance broadband networks.

SET MODE 2

Recognize Source Routing

Allows theTBC to act as part of a source routing bridge
between interconnected networks

SET MODE 2

Copy CRC to Memory

Causes the TBC to copy the 4 byte CRC of data frames to memory
as part of the data unit

SET MODE 3

Suppress CRC Generation (All Frames) Disables CRC generation for all data frames transmitted by the
TBC

SET MODE 3

Halt Generator Enable

Controls the maximum number of DMA transfers that the TBC
performs in one DMA burst

SET MODE 3

Data Byte Swap Mode

Allows the user to select either the Motorola/lBM or the Intell
DEC data organization for data buffers

SET MODE 3

Prescaler

Determines whether a prescaler of 3 or 6 should be used for
octet timers

SET MODE3

Flow Control

Enables the flow control algorithm to allo';" the user to
selectively copy RWR frames to memory while in
the EPA mode only

LSAP Only

Suppress CRC Generation
(Per Frame)

Disables transmission of CRC on a frame by frame basis

Frame Only

Mode

MOTOROLA
7-82

M68000 FAMILY
REFERENCE

MC68824

Table 3. Initialization Table Format
Displacement
(In Bytes)

Description
of Field

Displacement
(In Bytes)

00
02
03
05
08
OA
OC
OE

Private Area Function Code
Private Area Pointer High
Private Area Pointer Low
Zero
Initial HLPriority_Token_Hold_Time
Zero
Zero
Initial TargeLRotation_ Time for Access Class 4

10
12
14
16
18
1A
1C
1E

Zero
Initial TargeLRotation_ Time for Access Class 2
Zero
Initial TargeLRotation_ Time for Access Class 0
Zero
Initial TargeLRotation_ Time for
Ring Maintenance
Initial Ring Maintenance Time Initial Value
Initial Source Segment/Bridge ID (SID)

20
22
24
26
28
2A
2E

Initial
Initial
Initial
Initial
Initial
Initial
Zero

Target Segment/Bridge ID (TID)
Segment Number Mask for Source Routing
Max_Jnter-SoliciLCount
RX Frame Status Error Mask
TX Queue Access Class 6 Status
TX Queue Access Class 6 HOQ Pointer

A8
AA
AC
AE

30
32
36
38
3A
3E

Initial
Initial
Zero
Initial
Initial
Zero

TX Queue Access Class 4 Status
TX Queue Access Class 4 HOQ Pointer

gO
B2
B4
B6
B8

40
42
46
48
4C

Initial
Initial
Zero
Initial
Initial

TX Queue Access Class 0 Status
TX Queue Access Class 0 HOQ Pointer

50
54
58

Initial RX QUflue Access Class 2 EOQ Pointer
Initial RX Queue Access Class 0 EOQ Pointer
Initial Ffee Frame Descriptor Pool Pointer to
First FD
Initial Free Buffer Descriptor Pool Pointer to
First BD

5C
60
62
64
66
68
6A
6C
6E

Initial
Initial
Initial
Initial
Initial
Initial
Initial
Initial

TX Queue Access Class 2 Status
TX Queue Access Class 2 HOQ Pointer

RX Queue Access Class 6 EOQ Pointer
RX Queue Access Class 4 EOQ Pointer

Group Address Mask - Low
Group Address Mask - Medium
Group Address Mask - High
Individual Address Mask - Low
Individual Address Mask - Medium
Individual Address Mask - High
Non-RWR Maximum Retry Limit
RWR Maximum Retries Limit

70
72
74
76
78
7A
7C"

Initial Slot Time
Initial This Station Address - Low
Initial This Station Address - Medium
Initial This Station Address - High
Initial Pad Timer Preset (PTP)
Mode Selector Word
Response SA Mask - Low

7E"
80"
82
84*
88*
8C*

Response SA Mask - Medium
Response SA Mask - High
Zero
Response Destination Address Pointer
Response Pointer
RWR Pointer

Description
of Field
COMMAND PARAMETER AREA

90
92
94
96
98
9A
9C
9E

AD
A2

A4
A6

Command
Command
Command
Command
Command
Command
Command
Zero
Zero
Zero
Zero
Zero

Parameter Area VALO
Parameter Area VAL 1
Parameter Area VAL2
Return Area RETO
Return Area RET1
Return Area RET2
Status and Done Bit

INTERRUPT STATUS AREA
Interrupt
Interrupt
Interrupt
Interrupt

Status Word 0
Mask 0
Status Word 1
Mask 1
STATISTICS

BA
BC
BE
CO
C2
C4
C6
C8
CA
CC
CE
DO
D2
D4
D6
D8
DA
DC
DE

Number of Tokens Passed (Threshold)
Number of Tokens Passed
Number of Tokens Heard (Threshold)
Number of Tokens 'Heard
Number of Tokens Passed Through
No_Successor-8 Arcs (Threshold)
Number of Tokens Passed Through
No_Successor_8 Arcs
Number of Who_Follows Transmitted
(Threshold)
Number of Who_Follows Transmitted
Number of Token Passes That Failed
(Threshold)
Number of Token Passes That Failed
Number of Non-Silence (Threshold)
Number of Non-Silence
Number of FCS Errors (Threshold)
Number of FCS Errors
Number of E-Bit Errors (Threshold)
Number of E-Bit Errors
Number of Frame Fragments (Threshold)
Number of Frame Fragments
Number of Frames Too Long (>8K Bytes)
(Threshold)
Number of Frames Too Long (>8K Bytes)
Number of No FD/BD Errors (Threshold)
Number of No FD/BD Errors
Number of Overruns (Threshold)
Number of Overruns
DMA DUMP AREA

EO
E2
E6
E8
EC
EE
F2
F4
F8-FE

FC1
DPTR1
FC2
DPTR2
FC3
DPTR3
FC4
DPTR4
Zero

*See Table 4.
"In Response SA Filtering' Mode Only

M68000 FAMILY
REFERENCE

MOTOROLA
7-83

MC68824

FL VRJ N-

ENABLE FLOW CONTROL ALGORITHM - - - - - - - - - - - - - - .
RESPONSE POINTER IS VAllO - - - - - - - - - - - - - - - .
REJECT RX RWR FRAME WITH LSDU = NULL - - - - - - - ,
DO NOT COPY RX FRAME - - - - - - - - - - - - .

;I:TL:~; ;:A:CST~~~T-ED-

-,----,1 1

--------------------------------

! !
12

USER STATUS

I I I I I I
RJ

RESERVED

RESPONSE POINTER HIGH
RESPONSE POINTER LOW
RESERVED =0

Figure 4. LSAP Table Entry

Table 4. Initialization Table Entries
in EPA Mode
Displacement
in Hex Bytes
84

Description of Field
Not Used

Not Used

RX Retry RWR Frame:" Threshold

RX Retry RWR Frame - Counter

RX RWR with LSDU = Null - Threshold

RX RWR with LSDU = Null - Counter

LINKED BUFFER STRUCTURES

The fully linked buffer structures include frame descriptors (FD), buffer descriptors (BD), and data buffers
(DB). One frame descriptor is required per received or
transmitted frame. Each frame descriptor contains information pertaining both to the frame sent or received plus
a pointer to the next FD as well as a pointer to its first
BD. Buffer descriptors contain the pointer to a data buffer
as well as that buffer's attributes, and a pointer to the
next buffer descriptor in the frame if used. The data buffers are used to store message data; one data buffer is
associated with each buffer descriptor. Figure 5 illustrates
the linked buffer structure.
To fully support the IEEE 802.4 message priorities, the
TBC provides four transmit queues and four receive
queues. Before transmission of a message, the host processor creates frame descriptors, buffer descriptors, and
data buffers for that message and then links the frame
descriptors to the appropriate transmit queue. Transmission queues may be enabled or disabled using the SET
ONE WORD command. The TBC confirms transmission
of the frames in each frame descriptor as they are sent
out. During reception, the TBC reverses the process to

MOTOROLA
7-84

use frame descriptors and buffer descriptors from the
pre-linked free frame descriptors pool and free buffer
descriptors pool as frames are received, assigning these
frames to the proper reception queue. Receive queues
may not be disabled. The free frame descriptor and buffer
descriptor pool pointers, which are located in the private
area, must be valid at initialization time and may be
changed thereafter using the SET TWO WORDS command while the TBC is OFFLINE. Finally, the host processor removes the frame data, from these reception
queues as programmed. Figure 6 illustrates the linking
between the queues, FDs, BDs, and DBs.
If the MC68824 is programmed to run in the Reduced
Data Structure mode, a separate data structure is used
for storing received frames while the TX frame queue
structure remains the same as previously explained. In
the Reduced Data Structure, there is only one receive
queue; frames of all priority classes are copied to the
same receive queue.

COMMAND SET
The host processor issues commands to the TBC to
perform various functions by writing to the TBC command register. The commands fall into seven categories
and are listed in Table 5.
INITIALIZATION COMMANDS

Initialization commands configure the TBC for operation after a hardware or software reset. The five initialization commands specify various system attributes and
the location of the initialization table in memory.
RESET Command

Both the RESET command and hardware reset cause
the TBC to perform a reset operation.

M68000 FAMILY
REFERENCE

MC68824

DATA BUFFER
BUFFER DESCRIPTOR

FRAME DESCRIPTOR

CONFIRMATION/INDICATION WORD
RECEIVE STATUS WORD
CONTROL FOR NEXT FD POINTER
NEXT FD POINTER
POINTER TO FIRST BD
FRAME DATA LENGTH
LLC
STATUS BYTE
IMMEDIATE RESPONSE FD POINTER
FRAME CONTROL
MAC DESTINATION ADDRESS
MAC SOURCE ADDRESS

DATA

DATA BUFFER POINTER
BD CONTROL AND OFFSET
BUFFER LENGTH
RECEIVE INDICATION WORD
NEXT BD POINTER

DATA BUFFER
BUFFER DESCRIPTOR

DATA

DATA BUFFER POINTER
BD CONTROL AND OFFSET
BUFFER LENGTH
RECEIVE INDICATION WORD
NEXT BD POINTER

Figure 5. Linked Buffer Structures

PRIVATE AREA

TX
TX
TX
TX

HOG
HOG
HOG
HOG

ACClSS
ACCESS
ACCESS
ACCESS

CLASS
CLASS
CLASS
CLASS

6
4
2
0

RX
RX
RX
RX

EOG
EOG
EOO
EOG

ACCESS
ACCESS
ACCESS
ACCESS

CLASS
CLASS
CLASS
CLASS

6
4
2
0

Figure 6. MC68824 Queues

M68000 FAMILY

REFERENCE

MOTOROLA
7-85

MC68824

Table 5. MC68824 Commands by Categories
Initialization
. LOAD INITIAL TABLE FUNCTION CODE
INITIALIZE
OFFLINE
IDLE
RESET

TEST
INTERNAUEXTERNAL LOOPBACK MODE
RECEIVER TEST
TRANSMITTER TEST
HOST INTERFACE TEST
FULL DUPLEX LOOPBACK TEST
SELF TEST
MEASURE SLOT TIME

SET OPERATION MODE
SET MODE 0
SET MODE 1
SET MODE 2
SET MODE 3
SET/CLEAR IN_RING_DESIRED

NOTIFY TBC
CLEAR INTERRUPT STATUS
RESPONSE READY
SET RESPONSE

TX DATA FRAMES
STOP
RESTART
START

MODEM CONTROL
PHYSICAL
END PHYSICAL

SET/READ VALUE
READ VALUE
SET FUNCTION CODE OF BUFFER DESCRIPTORS
SET FUNCTION CODE OF FRAME DESCRIPTORS
SET FUNCTION CODE OF RX AND TX DATA BUFFERS
SET PAD TIMER PRESET (PTP) REGISTER
SET ONE WORD
SET TWO WORDS

OFFLINE Command
The OFFLINE command causes the TBC to transition
to the offline state. The OFFLINE command is typically
used to end an internal diagnostic test on the TBC.
IDLE Command
The IDLE command causes the TBC to transition from
the offline state to the idle state. The IDLE command is
used after initialization is complete.
LOAD INITIALIZATION TABLE FUNCTION CODE Command
The LOAD INITIALIZATION TABLE FUNCTION CODE
writes the initialization table function code value in the
data register into the TBC and sets the bus width to 8 or
16 bits.
INITIALIZE Command
The INITIALIZE command loads the initialization table
pointer from the data register, loads initial values from
the initialization table into the TBC and the TBC private
area. This command should only be given while in the
offline state after reset.

UPDATE LSAP STATUS
UPDATE LSAP COUNTERS
RESET TRT

SET MODE 0 Command
The SET MODE 0 command allows the user to dynamically change the No Mask mode, the Control Frames
Preference mode, and the ability to receive erroneous
frames while in the Reduced Data Structure mode. See
Table 2 for a description of these modes.
SET MODE 1,2, AND 3 Commands
The SET MODE 1, 2, and 3 are commands used at
initialization time to set up various options of the MC68824.
. See Table 2 for a description of these modes.
SET/CLEAR IN_RING_DESIRED Command
The SET/CLEAR IN_RING DESIRED command is used
to change the value of the IEEE 802.4 boolean in_ring_
desired during normal operation.
TRANSMIT DATA FRAMES
Transmit data frames commands are used to stopirestart transmission of data frames or to start an empty
transmission queue.
STOP Command
The STOP command suspends transmission of data
frames by the TBC.

SET OPERATION MODE
The five commands in the set operation mode category
are used to set various operation modes and options in
the TBC. Defaults are off except for the Halt Generator
Enable bit which comes up set after a reset.

MOTOROLA
7-86

RESTART Command
The RESTART command restarts transmission of data
frames by the TBC after transmission has been stopped
via the STOP command.

M68000 FAMILY

REFERENCE

MC68824

START Command
The START command is used by the host processor
whenever new frame(s) is (are) added to an empty transmit queue. Before issuing this command, the command
parameter area must contain the code of the appropriate
transmit queue status, and the next two words must contain the pointer to the new frame(s).
SET/READ VALUE
SET/READ VALUE commands are used by the host processor to set and read TBC parameters. The parameters
which may be modified include function codes, pad timer
preset register, and some of the parameters which reside
in the private area or initialization table.
READ VALUE Command
The read value command reads internal TBC parameters and statistical information. The opcode of the parameter to be read is placed into the first word of the
command parameter area, the read value command is
issued, and the TBC returns the value of the parameter
in the command return area in the initialization table.
SET ONE WORDITWO WORDS Command
The SET ONE WORDITWO WORDS commands allow
the user to set a number of MAC parameters and TBC
pointers. The opcode of the parameter to be set must be
placed in the first word of the command parameter area
with the value in the next three words.
SET PTP Command
This command allows the user to set the pad timer
preset register which is used by the MC68824 to set the
length and pattern of the preamble and the minimum
number of preamble octets transmitted between frames.
SET FUNCTION CODES Command
There are three commands available to the user to set
the function codes. The MC68824 utilizes function codes
to access the buffer descriptors, frame descriptors, and
RX and TX data buffers. If function codes are not used,
these commands may be ignored.
UPDATE LSAP STATUS Command
The UPDATE LSAP STATUS command can be used to
activate, deactivate, or update user status when the TBC
is online. This command can only be issued when the
MC68824 is in the EPA mode.
UPDATE LSAP COUNTERS Command
The UPDATE LSAP COUNTERS command allows the
user to set the flow control counters to new values without disabling the specific LSAP. This command can only
be issued when the MC68824 is in the EPA mode and
with the Flow Control mode enabled.

Since the last value of the token rotation timer is also
returned to the host, this command may be used to make
time calculations. This command must only be issued
when the MC68824 is in the Bus Analyzer mode.
TEST
Test commands are used to test the interface from the
host to the TBC, the transmitter, the receiver, and the
serial section as well as the internal sections of the TBC.
SET INTERNAL/EXTERNAL. LOOPBACK MODE Command
This command determines whether the TBC is in internal or external loopback mode while running the receiver, transmitter, and full duplex loopback tests.
Tests
There are five available tests which can be run on the
TBC while in the offline state. The five tests are HOST
INTERFACE TEST, RECEIVER TEST, TRANSMITIER TEST,
FULL DUPLEX LOOPBACK TEST, and SELF TEST.
MEASURE SLOT TIME Command
The MEASURE SLOT TIME command is used when the
MC68824 is offline to enable the user to monitor the length
of a response window opened by a station already in the
ring. Upon issuance of this command, the MC68824 waits
until the first soliciLsuccessor_l frame is heard. Then,
the time is measured until a successive token is heard.
NOTIFY TBC
The seven commands in this category are used to notify
the TBC to perform an action dynamically.
CLEAR INTERRUPT STATUS Command
The CLEAR INTERRUPT STATUS command resets the
interrupt request signal and clears specific status bits in
the status words.
RESPONSE READY Command
The RESPONSE READY command notifies the TBC that
the host has completed preparing a response frame for
the TBC in answer to a request with response frame. This
command is only valid when not in predefined response
mode.
SET RESPONSE Command
The SET RESPONSE command is used to notify the
MC68824 that an updated response frame is to be sent
out at a later time when requested by another station.
The SET RESPONSE command performs a function
equivalent to LREPLY_UPDATE defined in IEEE 802.2.
This command can only be issued when the MC68824 is
in the EPA mode.
MODEM CONTROL

RESET TRT Command
The RESET TRT command when issued causes the
MC68824 to reset the internal token rotation timer to zero.

M68000 FAMILY

REFERENCE

Two commands are provided that allow the TBC to
provide management services to the physical layer of the
node.

MOTOROLA
7-87

MC68824

PHYSICAL Command

RECEPTION OF A FRAME

The PHYSICAL command is used by the host processor
to control the physical layer. This command allows the
TBC to either pass commands or send serial data to the
physical layer while in station management. Status or
data is returned in the last word in the command return
area.
END PHYSICAL Command
The END PHYSICAL command removes the TBC from
the station management mode. The TBC negates SMREQ
and waits for the modem to negate SMIND before setting
the command confirmation bit.

TRANSMISSION OF A FRAME
Data frames are transmitted from one of four transmission priority queues. The host processor passes the
pointer from the start of the queue to be transmitted to
the TBC using the start command. Upon reception of the
token by the station, the TBC checks the transmission
queues for frames to be sent. If frames are present in one
or more of the queues, the TBC will send frames based
on their priorities until its allotted transmission time expires. At the end of the frame transmission, the TBC writes
into the frame descriptor the status of the frame. The TBC
may then generate an interrupt request according to the
frame type (non-RWR, RWR, response), interrupt status,
and the interrupt mask. The host processor services the
interrupt and checks for the status of the frame, i.e., if
transmission was successful or not. The TBC can transmit
frames with lengths of up to 64K bytes. TheTBC does
not check if the frame is longer than 8K bytes. (The IEEE
standard specifies frame lengths of up to 8K bytes.) The
TBC does not check if the frame control, destination address, and source address are correct buttakes them from
the frame descriptor as they are. This means that the host
must be sure to write them correctly.

If the incoming frame's destination address matches
the individual station's address, the individual station's
group address, or the broadcast address, then the TBC
will accept the frame. The TBC can accept frames with
undefined frame control field and data frames, can treat
control frames as data frames, and can write the CRC of
a received frame into the data buffer as defined by the
SET MODE commands. The CRC is always calculated and
compared with the CRC of the frame. When a frame is
accepted, the frame is placed into the appropriate RX
priority queue in memory, and its frame descriptor. is
linked to the last frame descriptor in the queue. If an error
occurred on frame reception, the RX status error mask
(set by the user initialization) in the TBC private area
determines whether to accept or reject the frame. The
TBC may generate interrupts upon detecting error conditions. A normal interrupt may also be generated according to the frame's type (RWR or request with no
response), the interrupt status, and the interrupt 'mask.

LLC TYPE 3 PROTOCOL IMPLEMENTATION
While running in the EPA mode the MC68824 provides
the user with the IEEE 802.2 Acknowledged Connectionless Service primitives described in Table 6. These services provide the means at the data link level to exchange
link service data units point to point which have been
acknowledged at the LLC sublayer without establishing
a data link connection. Upon receiving an RWR frame,
the MC68824, if in the EPA mode will first check if data
is requested in the response. If data is not requested, the
MC68824 sends an ACK as a response to acknowledge
the RWR frame's reception. If data is requested in the
response, then the MC68824 checks for a response associated with the specific DSAP ofthe request.lfthe LSAP
is active and the response is ready, the response is sent
back to the requester with the appropriate status; otherwise, a NACK is sent.

Table 6. LLC Type 3 Primitives Provided by the MC68824
Acknowledged Connectionless Data Unit Transmission Service
Primitive

Description
Used to send a data unit with acknowledgement to another node
Used to indicate the reception of a non-null, non-duplicate LSDU from
a remote data link node
Used to indicate whether the previous LSDU transmission
request was successful

LDATA-ACK.request
LDATA-ACK.indication
LDATA-ACICSTATUS.i ndication

Acknowledged Connectionless Data Unit Exchange Service
Primitive
LREPL V.request
LREPLV.indication
LREPLLSTATUS.indication

Description
Used to request an acknowledged connection less data unit exchange
Used to indicate reception of an acknowledged connectionless data
frame
Used to confirm acknowledged connectionless data frames
Reply Data Unit Preparation

Primitive
LREPLV_UPDATE.request
LREPLV_UPDATE_STATUS.indication

MOTOROLA
7-88

Description
Used to indicate the need to update a response
Used to confirm that a response was updated

M68000 FAMILY
REFERENCE

MC68824

SYSTEM INTERFACE

VOO

ADDRESS BUS {

A3-A31
ClK

00-D15

OATABUS {

"'-

~
FCO

GND

FCI
FC2

fUNCTIDNeDD" {

SERIAL INTERFACE

FC3
MC68824
DTACK
R/W
UDS/AD

BUS
CONTROL

lDS/DS

AS
CS
~

BUS {
ARBITRATION

SMREQ
TXClK
TXSYM2
TXSYMI
TXSYMD

Bii
BG
BGACK

SMIND
RXClK

INTERRUPT {
CONTROL

iRQ

RXSYM2

lACK

RXSYMI
RXSYMD

BECD
BUS EXCEPTION {
CONOITIONS

}

PHYSICAL
DATA
REQUEST
CHANNEL

}

PHYSICAL
DATA
INDICATION
CHANNEL

BECI
BEC2

Figure 7. MC68824 Signals

M68000 FAMILY

REFERENCE

MOTOROLA
7-89

MC68824

ELECTRICAL SPECIFICATIONS
This sections contains the electrical specifications and associated timing information for the MC68824. See Figure 7
for a diagram of the MC68824 signals.

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Supply Voltage

VOO

-0.3 to +7.0

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature Range
MC68824
MC688241

Storage Temperature Range

Tstg

o to 70
o to 85
-55 to + 150

V
°C

°C

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GNO or VOO).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance for PGA
TJ = TA+(POe!lJA)
Po = (VOOeIOO) + PliO
where:
PliO is the power dissipation on pins (user determined) which can be neglected
in most cases.
For TA=70°C and PO=0.55 W (il 12.5 MHz
TJ = 88°C

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
'
TJ=TA+(POoSJA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
!lJA
Junction-to-Ambient,OCIW
Po
= PINT+ PPORT
= 100 x VOO, Watts - Chip Internal Power
PINT
= Power Oissipation on Input and Output Pins,
PlIO
Watts - User Oetermined

MOTOROLA
7-90

For most applications PI/Oo.
r---

d
e
r

IR01

--ft>o.

IR02

--fDo.

IR03

--fDo.

IR04

--fDo.

IROS

IR06

IR07

t
c
h

Bits 0,1.2

t
c.

0
e
c

r----.,---

Bit 4

Logic

0
e
c

CR1

t--

From
Control

m
p.

Bits 0,1,2

I r~I-+-I-+--+--+....L.----.
- - - -i
/

fti:B

E
n
c

y r

Control Registers

f--4

m
p.

..---

r
i
o
r
i
t

,--.

~A73
A
Bits 0,1.2

Match

r:-

To Other Blocks

.--

_~IToCont rol

Bits 0,1,2

A = B

0
e
c
0

Bit4

E
Bits 0,1,2

d
e
r

e
c
o

Bit 4

..-,-----,E
~
From Control

logic

~------------------------~~~

.''--------------------------4
~tor Regist~

VRO

' - - -_ _ _ _ _
lO_9iC--lt-..

r--- I
I
1--:'

::~

I r---;;;;--

Fro~o~~cntrol

Control Data Out Bus

Vector Data Out Bus

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _0_a_ta_ln_8_us________________
L..

-.L

~ ~
"

INT2

INn

INTO

T..

_~_ _ _ _ _ _ _ _ _ _

From Control

INTJ

~~
c :4---

f4----

~ D7

r - - - D4

t=:) ~.. ~
I

r---

~illC==~
.

~
Buffer

FIGURE 2 -

MOTOROLA
8~2

MC68153 FUNCTIONAL BLOCK DIAGRAM

.M68000 FAMILY
REFERENCE

MC68153

ABSOLUTE MAXIMUM RATINGS (Beyond which useful life may be impaired.)
Symbol

Value

Unit

Supply Voltage

VCC

-0.5to +7.0

Input Voltage

Vin

-0.5 to +7.0

Input Current

lin

-30 to +5.0

Parameter

Output Voltage

Vout

-0.5 to +5.5

Output Current

10L

Twice Rated 10L

Storage Temperature

Tstg

-65 to + 140

°c

-55 to + 140

°c

Junction Operating Temperature

DC ELECTRICAL SPECIFICATIONS (VCC

BURN-IN LIMITS: A maximum
TJ of + 175°C may be used for
periods not to exceed 250 hours.

= 5.0 V -+5%. TA = O°C to 70°C)

Parameter

Symbol

Min

Max

Unit

VIH

2.0

High Level Input Voltage
Low Level Input Voltage

VIL

Input Clamp Voltage

VIK

High Level Output Voltage(1)

VOH

2.7

Low Level Output Voltage

VOL

Output Short Circuit Current(2)

lOS

-15

High Level Input Current

IIH

Test Conditions

0.8

-1.5

VCC

VCC
, VCC

0.4

-130

VCC

JLA

VCC

= MIN. liN = -18 mA
= MIN. 10H = -400 JLA
= MIN. 10L = 8.0 mA
= MAX. VOUT = 0 V
= MAX. VIN = 2.7 V
= MAX. VIN = 0.4 V

Low Level Input Current

IlL

-0.4

VCC

Supply Current

lee

225

385

Vee = MAX

Output Off Current (High)

10ZH

10ZL

!LA
JLA

VCC

Output Off Current (Low)

-20

VCC

= MAX. VOUT = 2.4 V
= MAX. VOUT = 0.4 V

r~-------------"
VCC = 5.0 V
6.5V

1000 n

9
10
11

Pin Under Test

ll)

0;
(0

31
30

500

CL '5P'1

':'

L _______________ _
NOTES:
1. Not applicable to open-collector outputs,
2, Not more than one output should be shorted at a time for longer than one second.
3, CS Low to CLK High (Setup Time) of 15 ns Min must be observed,
4. lACK Low to CLK High and IACKIN Low to CLK High (Setup Times) of 15 ns Min must be observed.
5. See Table 1 for additional performance guidelines.

AC TEST CIRCUIT -

M68000 FAMILY
REFERENCE

AC Testing of All Outputs

MOTOROLA
8-3

MC68153

TABLE 1
AC PERFORMANCE SPECIFICATIONS
(VCC = 5.0 V ± 5%, TA = O°C to 70°C)
Number
1
2
3
4
5

Characteristic
RIW, A1-A3 Valid to CS low (Setup Time)
CS low to RiW,A1-A3 Invalid (Hold Time)
CS low to, ClK High (Setup Time)
ClK High to Data Out Valid (Delay)
ClK High to DTACK low (Delay)

6
7
8
9
10

DTACK low to CS High
CS High to DTACK High (Delay)
CS High to Data Out Invalid (Hold Time)
CS High to Data Out High-Impedance (Hold Time)
CS High to CS or lACK low

11
12
13
14
15

Data In Valid to CS low (Setup Time)
CS low to Data In Invalid (Hold Time) ,
DTACKHigh to Data,Out High-Impedance,
lACK low to ClK High (Setup Time)
A1-A3 Valid to lACK low (Setup Time)

16
17
18
19
20

lACK lowto'A1-A3 invalid (Hold Time)
IACKIN low to ClK High (Setup Time)
, ClK High to Data Out Valid (Delay)
ClK High to DTACK low (Delay)
" ClK High to INTAE low (Delay)

22
23
24
25
26

DTACK low to IACKIN High
DTACK low to lACK High
.IACK High to Data Out Invalid (Hold Time)
lACK High to Data Out High Impedance (Delay) ,
lACK High to DTACK High (Delay)

27
28
29
30
31

lACK High to INTAE High (Delay)
INTAlO, INTAl1 Valid to INTAE low (Setup Time)
INTAE High to INTAlO, INTAl1 Invalid (Hold Time)
lACK High to IRQx High (Delay)
lACK High to lACK or C,S low

32
33
34
35
36

Min

Max

10
5.0
15

55
40

20
10
5.0

15
10
5.0
15

55
40
40

0
0
0

-.
-

1.0
1.0

60
45
,35
2.0
2.0
50

ClK High to IACKOUT low (Delay)
IACKIN low to IACKOUT low (Delay)
IACKOUT low to IACKIN, lACK High
lACK High to IACKOUT High (Delay)
lACK and CS both low to ClK High (Setup Time)

40
30

37
38
39
40
41

ClK Hig~o lACK or CS High (Hold Time)
lACK or CS High to lACK and CS High (Skew)
Clock Rise Time
Clock Fall Time
Clock High Time

42
43

Clock low Time
Clock Period

.:...-

i.o

20
20
40

10
10

Units

Notes

ns
ns
ns
ns
ns

1
2
2

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
,ns
ns
ns
ns
ns
ns
ns
ns
ns
ClK Per
ClK Per
ns
, ns
ns
ns
ns
ns
ns
ns
ClK Per
ns
ns
ns

10
1

1,,8
3
3
3
8

7,10
5
4,8
8
9
6

ns
ns

NOTES:
1. This specification only applies if the VBIM had completed all operations initiated by'the previous bus cycle when CS or lACK was asserted, Following
a normal bus cycle, all operations are completed within 2 clock cycles after CS or lACK have been negated, If lACK or CS is asserted prior to
completion of these operations, the new cycle, and hence, DTACK is postponed.

If the lACK, IACKIN or CS setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later (i.e. lACK will not be
recognized until the next rising edge of the clock).

2. Assumes that 3 has been met.
3. Assumes that 14 and 17 have both been met.
4. Assumes that 14 has been met. (lACKOUT cannot go low prior to IACKIN goirig low).

5. Assumes that 14 has been met and IACKIN has been low for at least the amount of time specified by 33.
6. 38 is the minimum skew between the last moment when both lACK and CS are asserted to when both 'are negated, to insure that an access cycle
is not unintentionally started.

7. Assumes no other INTx input is causing IRQx to be driven low.
8. In non-daisy chain systems, IACKIN may be tied low.
9. Failure to meet this spec. causes RESET to be ignored for 1 clock period. It is then' necessary to ke~p these signals low for 3 clock periods instead
of 2.
10. Delay time is specified from Input signal to Open-Collector Output pulled High thru 1.0kO resistor to +6.5 V.

MOTOROLA
8-4

M68000 FAMILY

REFERENCE

MC68153

AC ELECTRICAL SPECIFICATIONS (VCC

= 5.0 V ::t 5%, TA = O°C to 70°C)

Parameter
ClK High to Data Out Valid (Delay)(3)
ClK High to DTACK low (Delay)(3)
CS High to DTACK High (Delay)
ClK High to Data Out Valid (Delay)(4)
ClK High to INTAE low (Delay)(4)
lACK High to Data Out High Impedance (Delay)
lACK High to DTACK High (Delay)
CS High to Data Out High (Delay)
CS High to IRQ High (Delay)
lACK High to INTAE High (Delay)

Test
Number(51

Max
(nsl

55
40
35
55
40
60
45
45
60
35

3
4
5
6
7
8
9

GENERAL DESCRIPTION

SIGNAL DESCRIPTION

The MC68153 8us Interrupter Module (81M) is designed to serve as an interrupt requester for peripheral
devices in a microcomputer system. Up to 4 independent devices can be interfaced to the system bus by the
MC68l53. Intended for asynchronous master/slave bus
operation, the 81M is compatible with VERSAbus, VMEbus, MC68000 device bus, and other system buses. Figure 1 shows a block diagram of a typical configuration.
In this example, three peripheral devices (bus slaves)
are connected to the system data bus. Each of these
devices could be parallel liD, serial I/O, or some other
function. An interrupt request from any device is routed
to the MC68l53, and the 81M handles all interface to
the system bus. It generates a bus interrupt request as
a result ofthe device interrupt request. When the system
interrupt handler or processor responds with an interrupt acknowledge cycle, the MC68153 can answer supplying an interrupt vector and handling all timing.

Throughout the data sheet, signals are presented usingthe terms asserted and negated independent of
whether the signal is asserted in the high voltage or
low voltage state. Active low signals are denoted by a
superscript bar.

The functional block diagram of the MC68153 is
shown in Figure 2. The device contains circuitry to accept four separate interrupt sources (INTO-INT3). Interface to the system bus includes generation of bus
interrupt requests (lROl - IR07), response to a bus interrupt acknowledge cycle (either supplying a vector or
passing on a daisy chain signa!), and'releasing the bus
interrupt request signal at the proper time. The 81M has
flexibility provided by eight programmable read/write
registers. Four 8-bit vector registers (VRO - VR3) contain
status/address information and supply a byte vector in
response to an interrupt acknowledge cycle for the corresponding interrupt source; Four other 8-bit control
registers (CRO - CR3) contain information that oversees
operation of the interrupt circuitry. The control information is programmable and includes interrupt request
level and interrupt enable and disable. Also contained
in the control registers are flag-bits. These flags are
useful for task coordination, resource management, and
interprocessor communication.

M68000 FAMILV
REfERENCE

BIDIRECTIONAL DATA BUS - DO - 07
Pins DO - D7 form an 8-bit bidirectional data bus tot
from the system bus. These are active high, 3-state pins.
D7 is the most significant bit.
ADDR':SS INPUTS - A 1 - A3
These active high inputs serve two functions. One
function is to select one of the eight possible,registers
during a read or write cycle. Secondly, during an interrupt acknowledge Al - A3 show the level of interrupt
being acknowledged, and the 81M uses these to determine if a match exists with an internal level.
CHIP SELECT - CS
CS is an active low input used to select the 81M's
registers for the current bus cycle. Address strobe, data
strobe, and appropriate address bits must be includ'ed
in the chip'selectequation.
READIWRITE - RiW
The RNV input is a signal from the system bus used
to determine if the current bus cycle is a read (high) or
write (low).
DATA TRANSFER ACKNOWLEDGE - DTACK
DTACK is an open-collector, active low output that
signals the completion of a read, write, or interrupt acknowledge cycle. During read or interrupt acknowledge
cycles, DTACK is asserted by the MC68153 after data
has been provided on the data b'us; during write cycles
it is asserted after data has been accepted from the data
bus. A pullup resistor is required to maintain DTACK
high between bus cycles.

MOTOROLA
8-5

MC68153

Oata Bus
00-07
A3
A2
A1

BIM

INTO
INT1
INT2
. INT3

lACK
IACKIN
IACKOUT

INTAE
INTAlO
INTAl1

ClK
+5.0 (4)

GNO (4)

FIGURE 3 -

LOGICAL PIN ASSIGNMENT

INTERRUPT ACKNOWLEDGE SIGNALS - lACK,
IACKIN, IACKOUT
These three pins support the interrupt acknowledge
cycle. A low level on the lACK. input indicates an interrupt acknowledge cycle has been initiated. This signal
is conditioned externally with Address Strobe and the
lower data strobe of an MC68000 type bus. After lACK
is asserted the 81M compares the interrupt level presented on address lines A 1, A2, and A3 with the current
levels generated internally and determines if a match
exists. Then, if input IACKIN is asserted (driven low),
the 81M will either complete the interrupt acknowledge
cycle if a match exists or assert output IACKOUT if no
match exists.
IACKIN and ""IA""'C:C:K~O=-O-:U=T form part of a prioritized interrupt acknowledge daisy chain. The daisy chain prioritizes interrupters and guarantees that two or more devices requesting an interrupt on the same level will not
respond to the same cycle. The requesting device (or
interrupter) must wait untillACKIN is asserted and not
pass the signal on (assert IACKOUT) if it is to complete
the interrupt acknowledge cycle.
BUS INTERRUPT REQUEST SIGNALS - IRQ1 - IRQ7
These open-collector outputs are low when asserted,
indicating a bus interrupt is requested at the corresponding level. An open-collector buffer is normally required for sufficient drive when interfacing to a system
bus. A pullup resistor is required to maintain IRQ1 IR07 high between interrupt requests.

MOTOROLA
8-6

DEVICE INTERRUPT REQUEST SIGNALS INTO-INT3
INTO - INT3 are active low inputs used to indicate to
the 81M that a device wants a bus interrupt.
INTERRUPT ACKNOWLEDGE ENABLE - INTAE
During an interrupt acknowledge cycle, this output
pin is asserted low to indicate that outputs INTAlO and
INTAl1 are valid. These two outputs contain an encoded
number (x) corresponding to the interrupt (lNTx) being
acknowledged. This feature can be used to signal interrupting devices, which supply their own vector, when
to respond to the interrupt acknowledge cycle with the
vector and a DTACK signal.
INTERRUPT ACKNOWLEDGE LEVEL - INTALO,
INTAL1
These active high outputs contain an encoded number corresponding to the interrupt level being acknowledged. They are valid only when INTAE is asserted low.
CLOCK-CLK
The ClK input is used to supply the clock for internal
operations of the MC68153.
RESET - CS, lACK
Although a reset input is not supplied, an on-board
reset is performed if CS and lACK are asserted
simultaneously.

M68000 FAMILY

REFERENCE

MC68153

ADDRESS BIT
A3
A2
Al
a

o
o

a
a

FAC

X1IN

IRE

IRAC

CONTROL REGISTER a

FAC

X/IN

IRE

IRAC

CONTROL REGISTER 1

FAC

X/IN

IRE

IRAC

CONTROL REGISTER 2

FAC

X1IN

IRE

IRAC

CONTROL REGISTER 3

VECTOR REGISTER a

VECTOR REGISTER 1

VECTOR REGISTER 2

VECTOR REGISTER 3

4
3
REGISTER BIT

FIGURE 4 -

MC68153 REGISTER MODEL

REGISTER DESCRIPTION
The MC68153 contains 8 programmable read/write
registers. There are four control registers (CRO - CR3)
that govern operation of the device. The other four
(VRO - VR3) are vector registers that contain the vector
data used during an interrupt acknowledge cycle. Figure
4 illustrates the device register model.
CONTROL REGISTERS
There is a control register for each interrupt source,
i.e., CRO controls INTO, CR1 controls INT1, etc. The control registers are divided into several fields:
1. Interrupt level (L2, L1, LO) - The least significant
3-bit field of the register determines the level at
which an interrupt will be generated:
L2

IRQ LEVEL

o
o
o
o

0
0
1
1
0

0
1
0
1
0
1
0
1

DISABLED
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7

o
1
1

A value of zero in the field disables the interrupt.
2. Interrupt Enable (IRE) - This field (Bit 4) must be set
(high level) to enable the bus interrupt request associated with the control register. Thus, if the INTX
line is asserted and IRE is cleared, no interrupt request (lRQX) will be asserted.
3. Interrupt Auto-Clear (lRAC) - If the IRAC is set (Bit
3), IRE (Bit 4) is cleared during an interrupt acknowledge cycle responding to this request. This action of

M68000 FAMILY
REFERENCE

clearing IRE disables the interrupt request. To reenable the interrupt associated with this register, IRE
must be set again by writing to the control register.
4. External/Internal (X/iN) - Bit 5 of the control register
determines the response of the MC68153 during an
interrupt acknowledge cycle. If the X/iN bit is clear
(low level) the BIM will respond with vector data and
a DTACK signal, i.e., an internal response. If X/iN is
·set, the vector is not supplied and no DTACK is given
by the BIM, i.e., an external device should respond.
5. Flag (F) - Bit 7 is a flag that can be used in conjunction with the test and set instruction of the
MC68000. It can be changed without affecting chip
operation. It is useful for processor-to-processor
communication and resource allocation.
6. Flag Auto-Clear (FAC) - I f FAC (Bit 6) is set, the Flag
bit is automatically cleared during an interrupt acknowledge cycle.
VECTOR REGISTERS
Each interrupt input has its own associated vector
register. Each register is 8 bits wide and supplies a data
byte during its interrupt acknowledge cycle if the associated External/Internal (X/iN) control register bit is
clear (zero). This data can be status, identification, or
address information depending on system usage. The
information is programmed by the system user.
DEVICE RESET
When the MC68153 is reset, the registers are set to a
known condition. The control registers are set to all
zeros (low). The vector registers are set to $OF. This
value is the MC68000 vector for an uninitialized interrupt
vector.

MOTOROLA
8-7

MC68153

FUNCTIONAL DESCRIPTION
SYSTEM OVERVIEW
The MC68153 can be used with many system buse's,
however, it is primarily intended for VMEbus, VERSAbus and MC68000 applications. Figure 5 shows a system
configuration similar to VMEbus. In the figure only one
system Oata Transfer Bus (OTB) master is used. The .. ,
Priority Interrupt structure provides a means for peripheral slave devices to ask for an interrupt of other
processor (OTB master) activity and receive service
from the processor. The MC68153 BIM acts as an interface device requesting and responding to interrupt acknowledge cycles for up to 4 independent slaves.
In Figure 5, function'al modules are identified as In'terrupters and an Interrupt Handler. An Interrupter (such
as the MC68153) receives slave requests for an interrupt
and handles all interface to the system bus required to
ask for and respond to interrupt requests. The Interrupt'
,Handler receives the bus interrupt requests, determines
when an interrupt acknowledge will occur and at which
level, and finally either performs the interrupt acknowledge (lACK) cycle or tells the OTB master to execute the
lACK cycle.

The signal lines in the Priority Interrupt structure include (* - indicates active low):
1.IRQ1 *-IRQ7* - seven prioritized interrupt request lines.

,2. IACK* -signal line that indicates an interrupt acknowledge cycle is occurring.
3. IACKIN*/IACKOUT* - two signals that form part
of a daisy chain that prior-'
itizes interrupters.
In addition Oata Transfer Bus control signals are involved in the lACK bus cycle:
'
1. AS" ---:- the 'Address Strobe asserted low indicates
a valid address is on the bus.
2. OSO* - the lower OataStrobe asserted low indicates a data transfer will occur on bus
bits 000-007.
3. WRITE* - the ReadlWrite is negated indicating
the data is to be read from the Interrupter.
4. A01-A03 - Address lines A01-A03 contain the
encoded priority level of the lACK
cycle.
5. 000-007 - Oata bus lines 000-007 are used to
pass the interrupt vector from the responding Interrupter to the Interrupt
Handler.
6. OTACK* - Oata Transfer Acknowledge'asserted
low signals that the .Interrupter has
put the vector on the data bus.

r'-:-- --- -- ---, r- -------,--, r----------------------...,
I

.------, I

I
I

'-----::>~I

I
I
,I
I
I

I
I

1'1

I 1*
_...Ilz

Syste~ I

:;;::
u
::!;

1 - - -..... To Next Interrupter

Bus

Priority

~----------------------------------------------v Interrupt
FIGURE 5 -

MOTOROLA
8-8

SIMPLE VMEbus CONFIGURATION

M68000 FAMILV
REFERENCE

MC68153

Figure 6 shows a flow diagram of a typical interrupt
request and acknowledge .operation. Briefly, the sequence of events is first, an Interrupter makes a request,
next the Handler responds with an lACK cycle, then the
Interrupter passes a vector to the Handler completing
the lACK cycle, and finally the Handler uses the vector
to determine additional action. Typically, an interrupt
service routine is stored in software and the vector determines where its starting address is stored.

INTERRUPTER

Note the daisy chain operation. If the lACK level (on
A01-A03) does not match the Interrupter's request level
or if no request is pending,. the Interrupter passes the
IACKIN* signal on and asserts IACKOUT*. This sequential action automatically prioritizes Requesters on the
same level (first one in line with a request pending gets
serviced) and prevents two or more Interrupters from
responding simultaneously.

INTERRUPTER

(j)

iNTERRUPT
HANDLER

(Slave B
Requests Interrupt)
Drive IRQ4* Low

Detect IRQ4* Low.
Initiate lACK Cycle:
Place 3-bit
level 4 code on A01-A03.
Drive IACK* Low
(causing lACK
Daisy Chain to go Low.)
Drive AS* to Low.
Drive Write* High.
Drive DSO* to Low.
(Daisy Chain)

.~--------------------~( ~(----------~( ~(--------------------~
Detect IACK* Low.
Detect AS* Low.
Check 3-bit Interrupt
Acknowledge Code
(Detect Match).
Detect DSO* Low.
Detect IACKIN* Low
from Daisy Chain.
Place Vector Byte
on Data Bus.
Drive DTACK* to Low.

I
Detect DTACK* Low.
Read Vector.
Release lACK Cycle.
(Release AS*,
A01-A03, DSO*,
Write*, IACK*).
Initiate Interrupt
Service Sequence.

FIGURE 6 -

M68000 FAMILV

REFERENCE

INTERRUPT REQUEST AND ACKNOWLEDGE
OPERATION FLOW DIAGRAM

MOTOROLA
8·9

MC68153

This discussion is a very cursory look at the bus operation. For more details including situations with multiple bus masters, the user is directed to the VMEbus
Specification MVMEBS or VERSAbusSpecification
M68KVBS. Also, the MC68153 can be used with other
buses having similar interrupt structures.
BIM BUS INTERFACE
Figure 7 shows a simplified block diagram of the
MC68153 interface to VERSAbus or VMEbus. Address
Decode and Control Logic are dependent on the application and must be designed to guarantee BIM ac specifications. It is possible in most cases that the decode
logic can be shared with the slave devices. Buffers are
provided where shown to comply with bus loading and
drive specifications. It is also possible that buffers can
be shared with the slave bus interface.
READIWRITE OPERATION
All eight BIM registers can be accessed from the sys-

tem bus in both read and write modes. The BIM has an
asynchronous bus interface, primarily designed for
MC68000-like buses. The following BIM signals gener~
ate read and write cycles: Chip Select (CS), ReadlWrite
(RNV), Address Inputs (A1-A3), Data Bus (00-07). and.
Data Transfer Acknowledge (DTACK). During read and
write cycles the internal registers are selected by A 1,
A2,and A3 in.compliance with the Figure 4 Truth Table.
Figure 8 shows the device timing for a read cycle. RI
Wand A1-A3 are latched on the falling edge of CS and
must meet specified setup and hold times. Chip access
time for valid data and DTACK are dependent on the
clock frequency as shown in the figure.
Figure 9 shows the device timing for a write cycle. RI
W, A1-A3, and 00-07 are latched on the falling edge
of CS and must meet specified setup and hold times.
Chip access time for DTACK isdepelident on the clock
frequency as shown in the figure.

System Bus
7

IRQ1*
-IRQ7*

+5.0 V
IRQ7

000-007

IRQ6
IRQ5

(/)

:::l

(;

OTACK*

MC68153
BIM

(/)

:::l

.c
w

A04A23

INTO

AMOAMX

OSO*
AS*
IACK*
SYSRESET*

INT1
INT2
INT3

INTAE
INTALO
INTAL1

Dov;"
Device A
B
Device C
Device 0

Device
Interrupt
Requests

To Slave device
for external
Interrupt Ackknowledge

IACKIN*
IACKOUT*
SYSCLK

FIGURE 7 -

MOTOROLA
8-10

VMEbusNERSAbus INTERFACE BLOCK
DIAGRAM

M68000 FAMILY

REFERENCE

MC68153

FIGURE 8 -

FIGURE 9 -

M68000 FAMILY

REFERENCE

READ CYCLE

WRITE CYCLE

MOTOROLA

8·11

MC68153

INTERRUPT REQUESTS
The MC68153 accepts device interrupt requests on
inputs INTO; INT1, INT2, and INT3. Each input is regulated by Bit 4 (IRE) of. the associated, control register
(CRO controls INTO, CR1 controls INT1, etc). If IRE (Interrupt Enable) is set and a device input is asserted, an
Interrupt Request open-collector output (lRQ1-IRQ7) is
asserted. The asserted IRQX output is selected by the
value programmed in Bits 0, 1, and 2 of the control
register (LO, L1, and L2). This 3-bit field determines the
interrupt request level as set by software.
Two or more interrupt sources can be programmed
to the same request level. The corresponding IRQX output will remain asserted until mUltiple interrupt I acknowledge cycles respond to all requests.
.I ,
Ifthe interrupt request level is set to z'ero,the interrupt
is disabled because there is no corresponding IRQ out,:'1"
,
put.

INTERRUPT ACKNOWLEDGE,
The response of an Interrupt Handler to a bus interrupt request is an interrupt acknowledge cycle. The
lACK cycle is initiated in the MC68153 by receiving lACK
low. R/W, A1, A2, A3 are latched, and the interrupt level
on line A1-A3 is compared with any interrupt requests
pending in the chip. Further activity can be one of four
cases:
1. No further action required - This occurs if IACKIN
is not asserted. Asserting lACK only starts the BIM
activity. If the daisy chain signal never reaches the
MC68153 (lACKIN is not asserted), another Interrupter has responded to the lACK cycle. The cycle
will end, the chip lACK is negated, and no additional action is required.
2. Pass on the interrupt acknowledge daisy chain For this case, IACKIN input is asserted by the preceding daisy chain Interrupter, and IACKOUT output is in turn asserted. The daisy chain signal is
passed on when no interrupts are pending on a
matching level or when any possible interrupts are
disabled. The Interrupt Enable (IRE) bit of a control
register can disable any interrupt'requests, and in
turn, any possible matches.
3. Respond internally - For this case, IACKIN is asserted and a match is found. The MC68153 completes the lACK cycle by supplying an interrupt
vector from the proper vector register followed by
a DTACK signal asserted.IACKOUT is not asserted
because the interrupt acknowledge cycle is completed by this device.
For the MC68153 to respond in this mode of operation, the EXTERNAUINTERNAL control register
bit (X/iN) must be zero. For each source of interrupt
request, the associated control register determines
the BIM response to an lACK cycle, and the X/iN

MOTOROLA
8-12

bit sets this response either internally (X/iN = 0)
or externally (X/iN = 1).

4. Respond externally''''':' For the final case, IACKIN is
also asserted, a match is found andthe associated
control register has x/TN bit set to one. The
MC68153 does not assert IACKOUT and does assert INTAE iow. INTAE signals that the requesting
device must complete the lACK cycle (supplying a
vector and DTACK) and that the 2-bit code contained on outputs INTALO and INTAL 1 shows
which interrupt source is being acknowledged.
These cases are discussed in more detail in the fol, lowing paragraphs.
Internal Interrupt Acknowledge
For an ,internal interrupt acknowledge to occur, the
following conditions must be met:
1., One or more device interrupt inputs (lNTD-INT3)
has been asserted and corresponding control bit
IRE value is one.
'2. lACK asserted.
3. A match exists between [A3, A2, A 1) and the [L2,
L1, LO) field of an enabled, requesting control register. If two or more devices are requesting at the
same interrupt level, preference is given to the
highest number requester, that is, INT3 has highest
priority and INTO has lowest.
4. Control regfster bit X/iN of matching interrupt
source must be zero; .
5. IACKIN asserted.
The internal interrupt acknowledge cycle timing is
shown in Figure 10. The 8-bit interrupt acknowledge
vector is presented to. the data bus and bTACK is asserted. Note also thatlNTALO and INTAL 1 are valid and
INTAE is asserted during this cycle although they would
normally not be used. The cycle is terminated (data and
DTACK released) after lACK is negated.
During the IACKcycle,the INTERRUPT AUTO-CLEAR
control bit (lRAC) comes into play. If the IRAC = one
for the responding interrupt source, the INTERRUPT ENABLE (IRE) bit is automatically cleared during the lACK
cycle, thus disabling the associated interrupt input and
any IRQX output asserted due to this interrupt input.
Before another interrupt can be requested from this
source, IRE must be set to one by writing to the control
register.
Note that IACKOUT is not asserted because this device is responding to the lACK and does not pass the
daisy chain signal on. Also, new device interrupt requests occurring on INTD-INT3 after lACK is asserted
are locked out to prevent any race conditions on the
daisy chain.

M68000 FAMILY

REFERENCE

MC68153

elK

A3-A1

07-00

INTAlO, INTAl1

FIGURE 10 -

INTERRUPT ACKNOWLEDGE CYCLE -

External Interrupt Acknowledge
For an external interrupt acknowledge, the same conditions as listed above are met with one exception. Control register bit XlIN of matching interrupt source must
be set to one. The timing is shown in Figure 11. For this
cycle, the interrupt vector and DTACK must be supplied
by an external device. INTAE is asserted indicating that
INTALO and INTAL 1 are val:d. The external device can
use these signals to enable the vector and DTACK. The
cycle is terminated after lACK is negated.
The IRAC control bit acts in the external interrupt acknowledge the same as described for the internal response (see above). Also, IACKOUT is not asserted and
new device interrupts are disabled for reasons dis-.
cussed above.

M68000 FAMILY

REFERENCE

INTERNAL VECTOR

Pass On lACK Daisy Chain
If the MC68153 has no interrupt request pending at
the same level as the interrupt acknowledge, the lACK
daisy chain signal is passed· on to the next device if
IACKIN is asserted. The following conditions are thus
met:
1. lACK asserted.
2. No match exists between [A3, A2, A 1) and the [L2,
L1, LO) field of an enabled, requesting control register.
3. IACKIN is asserted.
IACKOUT is asserted if these conditions are valid. This
output drives IACKIN of the next Interrupter on the daisy
chain, passing the signal along. Figure 12 shows the
timing for this case. IACKOUT is negated after lACK is
negated.

MOTOROLA
8-13

MC68153

elK
A3-A1

INTALO, INTAL 1

FIGURE 11 -

INTERRUPT ACKNOWLEDGE CYCLE -

EXTERNAL VECTOR

elK

A3-A1

FIGURE 12 -

MOTOROLA
8-14

INTERRUPT ACKNOWLEDGE CYCLE -

IACKOUT

M68000 FAMILY
REFERENCE

MC68153

CONTROL REGISTER FLAGS
Each control register contains a Flag bit (F) and a Flag
Auto-Clear bit (FAC). Both bits can be read or altered
via a register write without affecting the interrupt operation of the device. The Flag is useful as a status
indicator for resource management and as a semaphor
in multitasking or multiprocessor systems. Flag (F) is
located in bit position 7 and can be used with the
MC68000 Test and Set (TAS) instruction.

RESET
There is no reset input, however, a chip reset is activated by asserting both CS and lACK simultaneously
(Figure 13). These inputs should be held low for a minimum of two clock cycles for a full reset function. The
control registers are reset to all zeroes and the Vector
Registers are set to a value of $OF. This vector value is
the uninitialized vector for the MC68000. See the
MC68000 Users Manual for more details on this vector.

The Flag Auto-Clear (FAC) is used to manipulate the
Flag bit. If the Flag is set to one and the FAC is also one,
an interrupt acknowledge cycle to the associated interrupt source clears the Flag bit. This feature is useful in
determining the interrupt status and passing messages.

CLOCK
The chip clock is required for internal operation to
occur. Typical frequency is 16 MHz in VMEbus and
VERSAbus applications derived from the system clock.
Any frequency can be used, however, up to 25 MHz
(Figure 14).

FIGURE 13 -

RESET

ClK

FIGURE 14 -

CLOCK WAVEFORM

TYPICAL THERMAL CHARACTERISTICS
Package

OJA (Junction to Ambient)
Still Air

Junction Temperature
Still Air @ 70·C Ambient

L Suffix
P Suffix 1

40°CIW
35°CIW

13rC

147°C

NOTES:
1. For reliable system operation the maximum allowable junction temperature (TJ) for plastic encapsulated packages has been limited to + 140°C.
Exceeding this limit will accellerate "wear-out" mechanisms associated with industry standard assembly methods using thermosonic bali bonds to
attach gold (AI') bond wire to aluminum (AI) bond pads on the die surface.
2. At TJ = 140°C, time to 0.1% failure due to AJJlAI interconnect = 8.920 Hours.

M68000 FAMILY
REFERENCE

MOTOROLA
8-15

MC68153

PIN ASSIGNMENTS

MOTOROLA
8-16

VCC

. Rm.

OTACK

lACK

'IACKIN

IACKOUT

IR01

GNO

VCC

IR02

IR03

IR04

INTAE

IR05

INTAL1

IR06

INTALO

IR07

INT3

ClK

INT2

I~TO

INT1

GNO

Vce

M68000 FAMILY.

REFERENCE

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68230

Technical Summary
Paraliellnterface/Timer (PI/T)
The MC68230 parallel interface/timer (PIIT) provides versatile double buffered parallel interfaces
and a system oriented timer for MC68000 systems. The parallel interfaces op'erate in unidirectional
'or bidirectional;modes. either 8 or 16 bits wide. In the unidirectional modes. an 'associated data
direction register determines whether each port pin is an input or output. In the bidirectional modes
the data direction registers are ignored and the direction is determined dynamically by the state of
four handshake pins. These programmable handshake pins provide an ir:'terface fl~xibleenough for
connection to 'a wide variety of low. medium. or high speed peripherals or other computer systems.
The PIIT ports allow use of vectored or autovectored interrupts; and also provide a DMA request
pin for connection to the MC68450 direct memory access controller (DMAC) or a similar circuit. The'
PIIT tim'er contains a 24-bit wide counter and a5-bit prescaler. The timer may be clocked by the
system clock (PIIT ClK pin) or by an external clock (TIN pin). and a 5-bit prescaler can be used. It
can generate periodic interrupts. a square wave;or a single interrupt after a programmed time period. It can also be used for elapsed time measurement or as a device watchdog.
Features of the PIIT include:
• M68000 Bus Compatible
• Port Modes Include:
Bit I/O
Unidirectional 8 Bit and 16 Bit
Bidirectional 8 Bit and 16 Bit
• Programmable Handshaking Options
• 24-Bit Programmable Timer Modes
• Five Separate Interrupt Vectors. Four of Which May be Dedicated to External Interrupt Service Requests
• Separate Port and Timer Interrupt Service Requests
• Registers are ReadlWrite and Directly Addressable
:
• Registers are Addressed for MOVEP (Move Peripheral) and DMAC Compatibi'lity

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA M68000 FAMilY

REFERENCE

MOTOROLA
8-17

MC68230

The system bus interface provides for asynchronous
transfer of data from the PI/T to a bus master over the
data bus (00-07). Data transfer acknowledge (OTACK),
register selects (RS1-RS5), timer interrupt acknowledge
(TIACK), readlwrite line (R/W), chip select (CS), or port
interrupt acknowledge (PlACK) control data transfers between the PI/T and an M68000 processor ..

INTRODUCTION
The PI/T consists oftwo logically independent sections:
the ports and the timer. The port section consists of port
A (PAO-PA7I, port B (PBO-PB7), four handshake pins (H1,
H2, H3, and H4), two general input/output (1/0) pins, and
six dual-function pins. The dual-function pins can individually operate as a third port (port C) or an alternate
function related to either port A, port B, or the timer. The
four programmable handshake pins,. depending on the
mode, can control data transfer to and from the ports,
can be used as general-purpose 110 pins, or can be used
as interrupt-generating edge-sensitive inputs with corresponding interrupt vector numbers. Refer to Figure 1.
The timer consists of a 24-bit counter; optionally clocked
by a 5-bit prescaler. Three pins provide complete timer
1/0: PC21T1N, PC3/TOUT, and PC7IT1ACK. Only the ones
needed for the given configuration perform the timer
function, while the others remain port ClIO.
38
GNO

REm'

40
ClK

42
OTACK

43
R/Vi

44
DO

PORT
INTERRUPT/
OMA
CONTROL
lOGIC

45
01

PORT MODE DESCRIPTION
The primary focus of most applications will be on port
A, port B, the handshake pins, the port interrupt pins, and
the OMA request pin. They are controlled in the following
way: the port general control register contains .a 2-bit
field that specifies one of four operation modes. These
govern the overall operation of the ports and determine
46
02

47
03

48
04

1
05

PAD 4
PAl
5
PA2 6
PA3 7
PA4 8
PA5 9
PA6 10
PA7 11

INTERNAL
OAT A BUS

12
HANOSHAKE
CONTROLLERS
ANO
MOOE lOGIC

HI
H2
H3
H4

13
14
15
16

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

18
19
20
21
22
23
24

PORT C ANO PIN FUNCTION MULTIPLEXER

PC7/
TIACK
37

PC6/
PlACK
36

PC5/
PIRO
35

PC4/
OMAREO
34

PC3/TOUT PC2/TIN
• 33
32

PCI
31

PCO
30

t t t t t

RSI
29

RS2
28

RS3
27

RS4
26

RS5
25

Figure 1. Block Diagram

MOTOROLA
8-18

M68000 FAMILY
REFERENCE'

MC68230

their interrelationships. Some modes require additional
information from each port's control register to further
define its operation. In each port control register, there
is a 2-bit submode field that serves this purpose. Each

port mode/submode combination specifies a set of programmable characteristics that fully define the behavior
of that port and two of the handshake pins. This structure
is summarized in Table 1 and Figure 2.

Table 1. Port Mode Control Summary
Mode 0 (Unidirectional 8-Bit Mode)
Port A
Submode 00 - Pin-Definable Double-Buffered Input or Single-Buffered Output
H1 - Latches input data
,
H2 - Status/interrupt generating input, general-purpose output, or operation with H1 in the interlocked or
pulsed handshake protocols
Submode 01 - Pin-Definable Double-Buffered Output or Non-Latched Inpu't
H1 - Indicates data received by peripheral
H2 - Status/interrupt generating input, general-purpose output, or operation with H1 in the interlocked or
pulsed handshake protocols
Submode 1X - Pin-Definable Single-Buffered Output or Non-Latched Input
H1 - Status/interrupt generating input
H2 - Status/interrupt generating input or general-purpose output
Port B
H3 and H4 - Identical to port A, H l' and H2
Mode 1 (Unidirectional 16-Bit Mode)
Port A - Most Significant Data Byte or Non-Latched Input or Single Buffered Output
Submode XX - (Not Used)
H1 - Status/interrupt generating input
H2 - Status/interrupt generating input or general-purpose output
Port B - Least-Significant Data Byte
Submode XO - Pin-Definable Double-Buffered Input or Single- Buffered Output
H3 - Latches input data
H4 - Status/interrupt generating input, general-purpose output, or opereation with H3 in the interlocked or
pulsed handshake protocols
Submode X1 - Piri-Definable Double-Buffered Output or Non-Latched Input
H3 - Indicates data received by peripheral
H4 - Status/interrupt generating input, general-purpose output, or operation with H3 in the interlocked or
pulsed handshake protocols
Mode 2 (Bidirectional 8-Bit Mode)
Port A- Bit 110
Submode XX - (Not Used)
Port B - Double-Buffered Bidirectional Data '
Submode XX - (Not Used)
H1 - Indicates output data received by the peripheral and controls output drivers
H2 - Operating with H1 in the interlocked or pulsed output handshake protocols
H3 - Latches input data
H4 - Operation with H3 in the interlocked or pulsed input protocols
Mode 3 (Bidirectional 16-Bit Mode)
Port A - Double-Buffered Bidirectional Data (Most-Significant Data Byte)
Submode XX - (Not Used)
Port B - Double-Buffered Bidirectional Data (Least-Significant Data Byte)
Submode XX - (Not Used)
H1 - Indicates output data received by peripheral and controls output drivers
H2 - Operation with H1 in the interlocked or pulsed output handshake protocols
H3 - Latches input data
H4 - Operation with H3 in the interlocked or pulsed input handshake protocols

M68000 FAMILY
REFERENCE

MOTOROLA
8-19

MC68230

LEGEND:

, !

. MODE 1 PORT B
SUBMOOE XO
PIN-DEFINABLE DOUBLE-BUFFERED INPUT
OR SINGLE-BUFFEREO OUTPUT
....- - - Hl

DOUBLE BUFFER EO

....---I~ H2

MC6B230
....._ -....

... ... }

.....~
___-1___-

A AND B
116)

..._---i~H4

SINGLE BUFFERE.D

NON-LATCHED
MODE 1 PORT B
SUBMODE XO
PIN-OEFINABLE OOUBLE-BUFFERED OUTPUT
OR NON-LATCHED INPUT

MODE 0
SUBMODE DO
PIN-DEFINABLE ODUBLE-BUFFERED INPUT
OR SINGLE-BUFFEREO OUTPUT

, . . . - - - - H1
MC6B230

,...-----i~

A AND B
116)

MC6B23D

MODE 0
SUBMODE 01
PIN-DEFINABLE DOUBLE-BUFFERED OUTPUT
OR NON-LATCHED INPUT

MODE 2
PORT A - BIT I/O
PORT B - DOUBLE· BUFFERED BIDIRECTIONAL
DATA
•• __ _ .. AlB)

AlB)
B

MC6B23D
BIB)

MC6B23D

14--':':':~~~} OUTPUT TRANSFERS

H1(H3)

H21H4)

}

INPUT TRANSFERS

'-------'

MODE 0
SUBMODE 1X
PIN-DEFINABLE SINGLE-BUFFERED OUTPUT
DR NON· LATCHED INPUT

MODE 3
BIDIRECTIONAL 16·BIT
A AND B
(16)

_ _ . . . . . AIB)
B
MC6B23D

MC6B230

14------ H1(H3)
...-----I-::~

H21H4)

I--.....;.;;~~~~ }
H3

I--.......;,;.H4~~

}

OUTPUT TRANSFERS
INPUT TRANSFERS

Figure 2. Port Mode Layout

MOTOROLA
8-20

FAMILY
REFERENCE

M68000

MC68230

SIGNAL DESCRIPTION

RESET (RESET)

The input and output signals are illustrated functionally
in Figure 3 and described in the following paragraphs.
00·07
RSI·RS5
R/W

CS
OTACK
RESET
CLK
VCC
GNO

PAO·PA7
PBO·PB7
HI
H2
H3
H4
PC7JTIACK *
PC6/PIACK*
PC5/PJJm*
PC4JDMAREO*
PC3/TOUT*
PC2/TIN*
PCI
PCO

* Individually Programmable Dual-Function Pin
Figure 3. logical Pin Assignment

RESET is a high-impedance input used to initialize all
PI/T functions. All control and data direction registers are
cleared and most internal operations are disabled by the
assertion of RESET (low).
CLOCK (ClK)

The clock pin is a high-impedance TIL-compatible signal
with the same specifications as the MC68000. The PI/T
contains dynamic logic throughout, and hence this clock
must not be gated off at any time_ It is not necessary that
this clock maintain any particular phase relationship with
the M68000 system clock. It may be. connected to an
independent frequency source (faster or slower) as long
as all bus specifications are met.
PORT A AND PORT B (PAO-PA7 and PBO-PB7)

Ports A and Bare 8-bit ports that may be concatenated
to form a 16-bit port in certain modes. The ports may be
controlled in conjunction with the handshake pins H1-H4.
For stabilization during system power up, ports A and B
have internal pullup resistors to Vce. All port pins are
active h i g h . ·
. .

BIDIRECTIONAL DATA BUS (00-07)

The data bus pins, DO-D7, form an 8-bit bidirectional
data bus to/from an M68000 bus master. These pins are
active high.
REGISTER SELECTS (RS1-RS5)

The register select pins, RS1-RS5, are active high highimpedance inputs that determine which ofthe 23 internal
registers is being selected. They are provided by the
M68000 bus master or other bus master.
READIWRITE (A/W)

RfW is a high-impedance read/write input signal from
the M68000 bus master, indicating whether the current
bus cycle is a read (high) or write (low) cycle.
CHIP SELECT (CS)

CS is a high-impedance input that selects the PI/T registers for the current bus cycle. The data strobe (upper
or lower) of the bus master, along with the appropriate
address bits, must be included in the chip-select equation. A low level corresponds to an asserted chip select.
DATA TRANSFER ACKNOWLEDGE (DTACK)

DTACKis an active low output that signals the
completion of the bus cycle. During read or interrupt
acknowledge cycles, DTACKis asserted after data has
been provided on the data bus; during write cycles it is
asserted after data has been accepted at the data bus.
Data transfer acknowledge is compatible with the
MC68000 and with other M68000 bus mastsers such as
the MC68450 direct memory access controller (DMAC).
A pullup resistor is required to maintain DTACK high
between bus cycles.

M68000 FAMILY
REFERENCE

HANDSHAKE PINS (H1-H4)

Handshake pins H1-H4 are mUlti-purpose pins that (depending on the operational mode) may provide an interlocked handshake, a pulsed handshake, interruptgenerating edge-sensitive inputs· (independent of data
transfers), or simple I/O pins. For stabilization during system power up, H2 and H4 have internal pullup resistors
to VCC' The sense of H1-H4 (active high or low) may ,be
programmed in bits 3-0 of the port general control register. Independent of the mode, the instantaneous level
of the handshake pins can be read from the port status
register.
PORT C (PCO-PC7/AlTERNATE FUNCTION)

This port can be used as eight general purpose I/O pins
(PCO-PC7) or any combination of six special function pins
and two general purpose I/O pins (PCO-PC1). Each dualfunction pin can be a standard I/O or a special function
independent of the other port C pins. When used as a
port C pin, these pins are active high. They may be individually programmed as inputs or outputs by the port
C data direction register. The dual function pins are defined in the following paragraphs.
The alternate functions TIN, TOUT, and TIACK are timer
I/O pins. TIN may be used as a rising-edge triggered external clock input or an external run/halt control pin (the
timer is in the run state if run/halt is high and in the halt
state if run/halt is low). TOUT may provide an active low
timer interrupt request output or a general-purpose
square-wave output, initially high. TIACK is an active low
high-impedance input used for timer interrupt acknowledge.
The port functions of the PI/T (portsAand B) have an
independent pair of active low interrupt request (PIRQ)
. and interrupt acknowledge (PlACK) pins.

MOTOROLA
8-21

MC68230

The DMAREQ (direct memory access request) pin provides an active low direct memory access controller request pulse for three clock cycles, completely compatible
with the MC68450 DMAC. Note that if these pins are used
for an alternate function, the corresponding bit in the Port
C Data Direction Register must be programmed as an
input (0).

SIGNAL SUMMARY
Table 2 is a summary of all the signals discussed in
the previous paragraphs.

The following si,9!!als generate rio!!!1al read and write
cycles to the PI/T: CS (chip select), RIW (read/write), RS1RS5 (five register select bits), DO-D7 (the 8-bit bidirectional data bus), and DTACK (data transfer acknowledge).
To generate interrupt acknowledge cycles, PC6/PIACK or
PC71T1ACK is used instead of CS, and the register select
pins are ignored. No combination of the following pin
functions may be asserted simultaneously: CS, PlACK,
or TIACK.

TIMER OPERATION
BUS INTERFACE OPERATION
The PI/T has an asynchronous bus interface, primarily
designed for use with an MC68000 microprocessor. With
care, however, it can be connected to synchronous
microprocessor buses.
In an asynchronous system the PI/T clock may operate
at a significantly different frequency, either higher or
lower, than the bus master and other system components, as long as all bus specifications are met. The
MC68230 ClK pin has the same specifications as the
MC68000 ClK pin, and must not be gated off at any time.

The MC68230 timer can provide several facilities needed
by MC68000 operating systems. It can generate periodic'
interrupts, a square wave, or a single interrupt after a
programmed time period. Also, it can be used for elapsed
time measurement or as a device watchdog.
The PI/timer contains a 24-bit synchronous down
counter that is loaded from three 8-bit counter preload
registers. The 24-bit counter may be clocked by the output
of a 5-bit (divide-by-32) prescaler or by an external timer
input (TIN). If the prescaler is used, it may be clocked by
the system clock (ClK pin) or by the TIN external input.
The counter signals the occurrence of an event primarily

Table 2. Signal Summary
Signal Name
CLK
CS

Input/Output
"

Active State

Input

Edge/Level Sensitive

Output States

Falling and Rising Edge

Input

Low

Level

Input/Output

High= 1, low=O

Level

OMAREO

Output

Low

High, Low

OTACK

Output

Low

High, Low, High Impedance*

00-07

H1(H3)***

High, Low, High Impedance

Input

Low or High

Asserted Edge

H2)H4**

Input or Output

Low or High

Asserted Edge

High, Low, High Impedance

PAO-PA7**, PBO-PB7**
PCO-PC7

Input/Output
Input or Output

High=1, Low=O

Level

High, Low, High Impedance

PlACK

. Level

Input

Low

Output

Low

RS1-RS5

Input

High=1, Low=O

Level

RNi

Input

High Read, Low Write

Level
Level

PIRO

Low, High Impedance*

RESET

Input

Low

TIACK

Input

Low

TIN (External Clock)

Input

TIN (Run/Halt)

Input

High

TOUT (Square Wave)

Output

Low

High, Low

TOUT (TIRO)

Output

Low

Low, High Impedance*

Level
Rising Edge
Level

*Pullup resIstors reqUIred.
**Note these pins have internal pullup resistors.
***H1 is level sensitive for output buffer control in modes 2 and 3.

MOTOROLA
8-22

M68000 FAMILY
REFERENCE

MC68230

through zero detection. (A zero is when the counter of
the 24-bit timer is equal to zero). This sets the zero detect
status (ZDS) bit in the timer status register. It may be
checked by the processor or may be used to generate a
timer interrupt. The ZDS bit can be reset by writing a one
to the timer status register in that bit position independent of timer operation.
The general operation of the timer is flexible and easily
programmable. The timer is fully configured and controlled by. programming the 8-bit timer control register.
It controls:-') ~he choice between the port C operation of

three timer pins, 2) whether the counter is loaded from
the counter preload register or rolls over when zero detect
is reached, 3) the clock input, 4) whether the prescaler is
used, and 5) whether the timer is enabled.

Table 3. Register Mode.1 (Sheet 1 of 2)

H34
Enable

H12
Enable

H4
Sense

H3
Sense

0 0 0 0 0

Port Mode
Control

0 0 0 0 1

0 0 0 1 0

Bit

0 0 0 1 1

SVCRQ
Select

H2
Sense

Hl
Sense

Port Interrupt
Priority Control

IPF
Select
Bit
4

Bit
3

Bit
2

Bit
1

Bit

Bit
4

Bit
3

Bit
2

Bit
1

Bit

Port General
Control Register

Port Service
Request Register

Port A Data
Direction Register

Port B Data
Direction Register

Port C Data
Direction Register

0 0 1 0 0

Bit

0 0 1 0 1
0 0 1 1 0

0 0 1 1 1

0 1 0 0 0

- Port Interrupt
Vector Register

H2
Int
Enable

Hl
SVCRQ
Enable

Hl
Stat
Control

Port A Control
Register

Port B
Submode

H4
Int
Enable

H3
SVCRQ
Enable

H3
Stat
Control

H4 Control

Port B Control
. Register

Bit

Port A Data
Register

Port B Data
Register

. Bit
4

Bit
3

Bit
2

Bit
1

Bit
4

Bit
3

Bit
2

Bit
1

Bit
4

Bit
3

Bit
2

Bit
1

Bit

Bit
4

Bit
3

Bit
2

Bit
1

Bit

Bit
4

Bit
3

Bit
2

Bit
1

Bit

5
H2
Level

Hl
Level

H4S

H3S

H2S

H1S

(Null)

o·

(Null)

Bit

Bit
6

Bit

Bit
6

Bit

Bit
6

Bit

Bit
6

Bit

7
0 1 1 0 1

H4
Level

H3
Level

0 1 1 1 0

0 1 1 1 1

7
Bit

7
0 1 1 0 0

Bit

H2 Control

Bit

0 1 0 1 1

Bit
1

Port A
Submode

0 1 0 1 0

Bit
2

Interrupt Vector Number

Bit

0 1 0 0 1

Bit
3

Bit
4

Bit

5
5
5

0
Bit

-0
0
0
0

***

Port A Alternate
Register

***

Port B Alternate
Register

it***

Port C Data
Register _

****

Port Status
Register

*Unused, read as zero
**Value before RESET
***Current value on pins
****Undetermined value

M68000 FAMILY
REFERENCE

MOTOROLA
8-23

MC68230

Table 3. Register Model (Sheet 2 of 2)

TOUTITIACK
Control
Bit
Bit
Bit
7
6
5

ZD
Control

Clock
Control

Bit
4

Bit
3

Bit
1

Bit
2

Timer
Enable

Timer Control
Register

Bit
0

Timer Interrupt
Vector Register

1 0 0 1 0

(Null)

1 0 0 1 1

Bit
23

Bit
22

Bit
21

Bit
20

Bit
19

Bit
18

Bit
17

Bit
16

Counter Preload
Register (High)

1 0 1 0 0

Bit
15

Bit
14

Bit
13

Bit
12

Bit
11

Bit
10

Bit
9

Bit
8

Counter Preload
Register (Mid)

1 0 1 0 1

Bit
7

Bit
6

Bit
5

Bit
4

Bit
3

Bit
2

Bit
1

Bit
0

Counter Preload
Register (Low)

1 0 1 1 0

(Null)

1 0 1 1 1

Bit
23

Bit
22

Bit
21

Bit
20

Bit
19

Bit
18

Bit
17

Bit
16

Count Register
(High)

1 1 0 0 0

Bit
15

Bit
14

Bit
13

Bit
12

Bit
11

Bit
10

Bit
9

Bit
8

Count Register
(Mid)

1 1 0 0 1

Bit
7

Bit
6

Bit
5

Bit
4

Bit
3

Bit
2

Bit
1

Bit
0

Count Register
(Low)

1 1 0 1 0

ZDS

Timer Status

(Null)

1 1 0 1 1

1 1 1 0 0

(Null)

1 1 1 0 1

(Null)

1 1 1 1 0

(Null)

1 1 1 1 1

(Null)

*Unused, read as zero
**Value before RESET

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to +7.0

Input Voltage

Vin

-0.3 to +7.0

Operating Temperature Range

o to 70

·oC

Tstg

-55 to +150

°C

Characteristic

Storage Temperature

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precuations be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either GND or VCC)'

THERMAL CHARACTERISTICS

Characteristic
Thermal Resistance
Ceramic (ULC)
Plastic (P)

MOTOROLA
8-24

Symbol

Value
(Max)

Symbol

Value
(Max)

°CIW

6JC

6JA
40
40

Rating

15*
20*

M68000 FAMILY
REFERENCE

MC68230

DC ELECTRICAL CHARACTERISTICS (VCC=5.0 Vdc±5%; TA=O to 70°C; unless otherwise noted)
Symbol

Min

Max

Unit

All Inputs

VIH

GND +2.0

VCC

All Inputs

VIL

GND -0.3

H1, H3, RiW, RESET,
CLK, RS1-RS5, CS

lin

Characteristic
Input High Voltage
Input Low Voltage
Input Leakage Current (Vin = 0 to 5.25 V)
Hi-Z (Off State) Input Current (Vin = 0.4 to

2.4 V)

Output High Voltage
(lLoad= -400 flA, VCC=Min)
(lLoad= -150 flA, VCC=Min)
(ILoad= -100 flA, VCC=Min)
Output low Voltage
(lLoad=8.8 mA. VCC=Min)
(lLoad=5.3 mA, VCC=Min)
(lLoad=2.4 mA, VCC=Minl

DTACK, PCO-PC7, DO-D7
H2, H4, PAO-PA7, PBO-PB7

ITSI

GND +0.8

10.0

I-LA

20
-1.0

I-LA
mA

-0.1

DTACK, DO-D7
H2, H4, PBO-PB7, PAO-PA7
PCO-PC7

VOH

GND +2.4

VOL

0.5

750

PC31T0UT, PC5/PIRQ
DO-D7, DTACK
PAO-PA7, PBO-PB7, H2, H4, PCO-PC2,
PC4,PC6,PC7

Maximum Internal Power Dissipation (Measured at T A = O°C)

PINT

Input Capacitance (V in = 0, TA = 25°C, f= 1 MHz)

Cin

AC ELECTRICAL SPECIFICATIONS - CLOCK TIMING (see Figure 4)
Characteristic
Frequency of Operation

Symbol

8 MHz
Min

Max

10 MHz
Unit

Min

Max

2.0

8.0

2.0

10.0

MHz

Cycle Time

tCYC

125

500

100

500

Clock Pulse Width

tCL
tCH

55
55

250
250

45
45

250
250

Clock Rise and Fall Time

tCr
tCf

10
10

~------ teye ----_+

NOTE:
Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. The voltage
swing through this range should start outside, and pass through, the range such that the rise or fall will be linear between 0.8 volt and 2.0 volts.

Figure 4. Clock Input Timing Diagram

M68000 FAMILY

REFERENCE

MOTOROLA
8-25

MC68230

AC ELECTRICAL SPECIFICATIONS (V CC = 5.0 Vdc ± 5%; GND =0 Vdc; TA =O°C to 70°C; unless otherwise noted)
(see Figures 5, 6, 7, 8, and 9)

Num.

Characteristic

10 MHz

B MHz

Unit

Min

Max

Min

Max

ns.

RiW, RS1-RS5 Valid of CS low (Setup Time)

CS low to RiW and RS1-RS5. Invalid (Hold Time

100

CS low to ClK low (Setup Time)

CS low to Data Out Valid

RS1-RS5 Valid to Data Out Valid

140

100

ClK low to DTACK low (ReadIWrite Cycle)

DTACK low to CS High (Hold Time)

CS or PlACK or TIACK High to Data Out Invalid (Hold Time

CS or PlACK or TIACK High to 00-07 High Impedance
CS or PlACK or TIACK High to DTACK High

10
11

CS or PlACK or TIACK High to DTACK High Impedance

100 .

Data In Valid to CS low (Setup Time)

CS low to Data In Invalid (Hold Time)

100

Port Input Data Valid to Hl(H3) Asserted (Setup Time)

100

H1(H3) Asserted to Port Input Data Invalid (Hold Time)

Handshake Input Hl(H4) Pulse Width Asserted

Handshake Input H1(H4) Pulse Width Negated

H1(H3) Asserted to H2(H4) Negated (Delay Time)

19 .

ClK low to H2(H4j Asserted (Delay Time)

150

120

100

ns
ns
ns
ns

20 4

H2(H4) Asserted to Hl(H3) Asserted

21 5

ClK low to H2(H4) Pulse Negated (Delay Time)

125

Synchr~nized Hl(H3) to ClK low on which DMAREO

2.5

3.5

2.5

3.5

Clk. Per.

22 9 ,10

is Asserted
23

ClK low on which DMAREO is Asserted to ClK low
on which DMAREO is Negated

2.5

Clk. Per.

ClK low to Port Output Data valid (Delay Time)
(Modes 0 and 1)

150

120

25 9 ,10

Synchronized Hl(H3) to Port Output Data Invalid
(Modes 0 and 1)

1.5

2.5

1.5

2.5

Clk. Per.

Hl Negated to Port Output Data Valid (Modes 2 and 3)

Hl Asserted to Port Output Data High Impedance
(Modes 2 and 3)

Read Data Valid to DTACK low (Setup Time)

ClK low to Data Output Valid, Interrupt Acknowledge Cycle

120

100

307

H1(H3) Asserted to ClK High (Setup Time)

PlACK to TIACK low to ClKLow (SetupTime)

Synchronized CS to ClK low on which DMAREO is Asserted

Clk. Per.

32 10
33 9 ,10
34

Synchronized Hl(H3) to ClK low on which H2(H4) is Asserted

3.5

4.5

3.5

4.5

elk. Per.

ClK low to DTACK low Interrupt Acknow,ledge Cycle
(Delay Time)

100

MOTOROLA
8~26

M68000 FAMILy

REFERENCE

MC68230

AC ELECTRICAL SPECIFICATIONS (Continued)
8MHz
Num.

Characteristic

10 MHz

Min

Max

Min

Max

Unit

ClK low to DMAREO low (Delay Time

120

100

ClK low to DMAREO High (Delay Time)

120

100

3.5

Clk. Per.
Clk. Per.

37 10

Synchronized Hl(H3) to ClK low on which PIRO is Asserted

38 10

Synchronized CS to ClK low on which PIRO is High Impedance

ClK low to PIRO low or High Impedance

250

225

408

TIN Frequency (External Clock) -

Prescaler Used

fclk (Hz)6

TIN Frequency (External Clock) -

Prescaler Not Used

118

1/8

fclk (Hz)6

TIN Pulse Width High or low (External Clock)

ns
Clk. Per.

TIN Pulse Width low (Run/Halt Control)

elK low to TOUT High, low, or High Impedance

250

225

CS, PlACK, or TIACK High to CS, PlACK, or TIACK low

NOTES:
1. This specification only applies if the Pill had completed all operations initiated by the previous bus cycle when CS was asserted.
Following a normal read or write busy cycle, all operations are complete within three clocks after the falling edge of the ClK
pin on which DTACK was asserted. If CS is asserted prior to completion of these operations, the new bus cycle, and hence,
DTACK is postponed. If all operations of the previous bus cycle were complete when CS was asserted, this specification is
made only to insure that DTACK is asserted with respect to the falling edge of the ClK pin as shown in the timing diagram not
to guarantee operation of the part. If the CS setup time is violated, DTACK may be asserted as shown, or may be asserted one
clock later.
2. Assuming the RS1·RS5 to data valid time has also expired.
3. This specification imposes a lower bound on CS low time, guaranteeing that CS will be low for at least 1 ClK period.
4. This specification assures recognition of the asserted edge of Hl (H3).
5. This specification applies only when a pulsed handshake option is chosen and the pulse is not shortened due to any early
asserted edge of Hl (H3).
6. ClK refers to the actual frequency of the ClK pin, not the maximum allowable ClK frequency.
7. If the setup time on the rising edge of the clock is not met, Hl (H3) may not be recognized until the next rising of the clock.
8. This limit applies to the frequency of the signal at TIN compared to the frequency of the ClK signal during each clock cycle. If
any period of the waveform at TIN is smaller than the period of the ClK signal at that instant, then it is likely that the timer
circuit will completely ignore one cycle of the TIN signal. If these two signals are derived from different sources they will have
different instantaneous frequency variations. In this case the frequency applied to the TIN pin must be distinctly less than the
frequency at the ClK pin to avoid lost cycles of the TIN signal. With signals derived from different crystal oscillators applied to
the TIN and ClK pins with fast rise and fall times, the TIN frequency can approach 80 to 90% of the frequency of the ClK signal
without a loss of a cycle of the TIN signal. If these two signals are derived from the same frequency source then the frequency
of the signal applied to TIN can be 100% of the frequency at the ClK pin. They may be generated by different buffers from the
same signal or one may be an inverted version of the other. The TIN signal may be generated by an "AND" function of the
.
clock and a control signal.
9. The maximum value is caused by a peripheral access (Hl (H3) asserted) and bus access (CS asserted) occurring at the same
time.
10. Synchronized means that the input signal has been seen by the Pill on the appropriate edge of the clock (rising edge for H 1(H3)
and falling edge for CS).

M68000 FAMILY

REFERENCE

MOTOROLA
8-27

MC68230

eLK ~

RS1·RS5

00·07

OMAREQ-----------------------------------------~~--~I

~--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ J

Figure 5. Read Cycle Timing Diagram
eLK

R/W

RS1·RS5

00·07

OMAREQ-------------------~----------~----------~--~~~----------------------~

Figure 6. Write Cycle Timing Diagram

eLK

PiA"Ci( -

OR fiACK _

00·07

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted.

Figure 7. lACK Timing Diagram

MOTOROLA
8-28

M68000 FAMILY
REFERENCE

:OS:
men

"'00
mo
:00
mo
2."

0»
ms:
~

elK

PA(PB)D-7

H1(H3)

H2(H4)
(lNTL) _

--------t--..J

DMAREO

H2(H4)
(PULSED) _

NOTES
1. Timing diagram shows Hl, H2, H3 and H4 asserted low_
2. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted.

Figure 8. Peripheral Input Timing Diagram

o
o
:lJ
CPO
-i

f',)'
CD:l>

CO
N
W

cos:

0-j

n
0)

CO
N
W

o
o
~

eLK

PA(PB)O·7 (MDO,l)-

141
• -f\---.- - t - - - - - - + - - -

PA(PB)O·7 IMD 2, 3) H2(H4)
(PULSED) Hl(H3)

DMAREQ

H2(H4) (INTL) -

NOTES

1. Timing diagram shows Hl, H2, H3and H4 asserted low.
2. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted.

Figure 9. Peripheral Output Timing Diagram

s:en

::a~
mo

-no
m-n
:Ill>

ms:

~r=
m<

:liS:

men

"110)

me
mo

:lie
2"11
0»

ms:
i=

ClK
TIN -

(EXT. ClK) TIN (RUN/HALT) -

-------------t-----t----+----.!~~~-=:"

TOUT
H1(H3) -

.. I

PIRQ -

cs-

,f:""""---

NOTES:
1. Timing diagram shows H1, H2, H3, and H4 asserted low.
2. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise
noted.

Figure 10. TIN, TOUT, PIRQ Timing Diagram

-f

o
::0

CPO

w'
.....
:t>

00
N
W

MC68230

PIN ASSIGNMENTS

DUAL·IN·PACKAGE
05

03
02
01

PAl

PA3

OTACK

PA4

PA6

RESET

RJW

CLK
GNO
VCC
HI

PC7JTIACK

PC5JPIRO

PC4JDMAREO
PC3JTOUT

PC6JPIACK

H4
PBO

PC2JT1N

PBl

PCl

PB2

PCO

PB3

RSI

PB4

RS2

PB5

RS3

PB6

RS4

PB7

RS5

QUAD PACK
g

-NM"d'"Lf'),....,C'OLn~MN

Cl)C/)CI)U')(I)CCQJcccacoccu

a:O:a:a:a:a..a..a..a..a..a..c:

21
PCO
PCl
PC2fT1N
PC3ITOUT
PC4/0MAREO
PC5/PIRO
PC6/PIACK
PC7fT1ACK
GNO
RESET
CLK

PBl
PBO
H4
H3
H2
HI
VCC
PA7
PA6
PA5
PA4

CS
OTACK

I~ g 0 ~ 8 b cg :g b ~ ~ ~ ~

MOTOROLA
8-32

M68000 FAMILY

REFERENCE

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68452

Bus Arbitration Module
The MC68452 is a bipolar asynchronous bus controller which allows multiple local MPU buses to
be multiplexed onto a common global bus enabling the local buses to share memory, 1/0 devices,
and communicate with each other easily and efficiently.
• Performs Arbitration For Eight Users Of A Global Bus
• Expandable
• Implements Fixed Physical Priority
• Supports Cycle By Cycle Or Block Mode Arbitration
• 52 ns Max Arbitration Time
• Performs Arbitration For Eight Users Of A 68000 Bus
• 28 Pin Package
• + 5.0 Volt Only Operation,

Local Address Bus
MC6S000

Global
Bus
Interface'

Local Data Bus

,
1

Bus Control

~
Local
Devices ~

Local
BAM

Lo",' Momo",
I/O

~
BG

....

DBR7

~
Local
Devices

r---.

Bus Control
MC6S000

Local Data Bus
Local Address Bus

FIGURE 1 -

Local
BAM

Global Data Bus

Global Address Bus

DBR6

r--l BR'
Global
BAM

DBG6
I-~

Lo,,' Momo",
liD

I-DBG7

+BGACK

Global
Memory

...
....

Global
liD

Global
Bus
Interface

MC68452IN A MODERATELY COUPLED MULTI-PROCESSOR SYSTEM

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA _
M68000 FAMILY
REFERENCE

MOTOROLA
8-33

MC68452

ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol

Unit

Value

Supply Voltage

VCC

-0.5 to +7.0

Input Voltage

Vin

-0.5 to +7.0

Operating Temperature

o to

+70

°c

-65 to + 150

°c

Storage Temperature

TSTG

DC ELECTRICAL SPECIFICATIONS (VCC

= 5.0 V

±5%, TA

= O°C to 70°C)

Parameter

Min

VIH High Level Input Voltage

Max

Unit

2.0

VIL Low Level Input Voltage
VIK Input Clamp Voltage
VOH High Level Output Voltage

Test Conditions

V
0.8

-1.5

VCC

2.4

VOL Low Level Output Voltage

= MIN, lin = -18 mA
= MIN, 10H = 2.6 mA
= MIN, IOL = 24 mA
= MAX, VOUT = 0 V

0.5

VCC

-130

VCC

IIH High Level Input Current

VCC ':" MAX, Vin = 2.7 V

IlL Low Level Input Current

-0.4

VCC

-130

VCC = MAX

lOS Output Short Circuit Current(2)

-15

ICC Supply Current

= MAX, Vin = 0.4 V

AC ELECTRICAL SPECIFICATIONS (VCC = 5.0 V ± 5%, TA = O°C to 70°C,
,
trise = tfall = 6 ns max)
Number·

Min

Max

Units

DBRn Low to BR Low

DBRn High to BR High

BG Low to DBGn Low

BGACK Low to DBRn High

2.0

BGACR Low to

DBGn High

·52

BGACK High to DBGn Low

DBRn Low to BCLR Low(1)

BGACK High to BCLR High

DBRn High to BGACK High

Parameter

·See Figure 2.
NOTES:
1. Assuming pending request is higher priority than current user.
2. No more than one output should be shorted at a time for no more than one second.

6.5 V

AC TEST CIRCUIT - Functional and Ac Testing of All Outputs
1.0 k

500

MOTOROLA
8~34·

M68000 FAMILY

REFERENCE

MC68452

~~------------~

FIGURE 2 -

SIGNAL DESCRIPTION
DEVICE BUS REQUEST (DBR7 - DBRO) - These eight
inputs are active low and are used to indicate that a
user demands a bus cyele(s). The DBR inputs are prioritized with DBR7 as the highest and DBR0 the lowest.
This priority scheme is only used when two or more
devices have pe'nding requests. '
DEVICE BUS GRANT (DBG7 - DBG0) - These active
low outputs indicate that a user has obtained the bus,
should bring BGACK active, and begin the transfer. The
DBGn is removed when the user brings BGACK active.
BUS REQUEST (BR) - This output is the logical AND
of all the DBRn inputs. This active low signal indicates
that one or more of the DBR inputs are active.
BUS GRANT (BG) -:- This active low input is used to
enable the DBGn outputs.

M68000 FAMILY
REFERENCE

TIMING DIAGRAM

BUS GRANT ACKNOWLEDGE (BGACK) - This active
low input indicates that a user has taken control of the
bus. Each' user must be able to generate this. signal.
When BGACK becomes active the DBGn will be removed.
BUSClEAR (BClR) - This active low output indicates
that a higher priority device has a request pending. This
signal is enabled by the BGACK being active. How this
signal is used is totally up to the system designer. The
'
BAM cannot force any device off the bus.
LATCH ENABLE INPUT (lEI) - This active low input
is used to cascade BAMs to allow more than eight bus
users. This signal should be the logical AND of all BR
outputs of the BAM circuits. This signal is used to elose
the input request latch in all BAM circuits whenever
there is a request pending in any part. This allows the
encoding/decoding to proceed in all. parts without spiking the outputs of any parts.

MOTOROLA
8-35

MC68452

THEORY OF OPERATION
The BAM provides a central arbitration function by
utilizing a separate request-grant pair for each user as
opposed to multiplexing all requests onto a single line
and daisy-chaining the grant. Each BAM circuit has eight
DBR-DBG request-grant pairs. When a device desires to
use the bus it brings its DBR low (active). Since the BAM
circuit operates asynchronously there are no restrictions placed on the active transition of the DBRn signals.
There are however, two minor restrictions placed on
the inactive transition. The restrictions are: 1) all requests must remain active until they receive their grant
signal and bring the BGACK active, and 2) the request
is removed before the BGACK is released.
Each bus request line has a corresponding bus grant
line (DBGn). After a requesting device brings its request
active it must monitor the DBGn signal. When this signal
becomes active the user has obtained the bus, should
bring BGACK active, and begin transferring. The device
can maintain control of the shared bus as long as the
BGACK signal remains active. This three level handshake (request-grant-acknowledge) allows the BAM to
support single or block type transfers with equal ease.
When the device transfer is complete it should remove the BGACK signal to allow the arbiter to determine the next user. In order for the BAM to operate
properly the three level handshake must be used even
if only single transfers are supported. When the BAM
detects the BGACK going inactive it initiates another
arbitration cycle, therefore the BGACK signal must be
used properly. Although the DBGn outputs are disabled
when BGACK is active the BAM has the current user
number latched internally. During the transfer the current user number is compared with the highest active
pending request. lfthe pending device is higher priority
the BUS CLEAR (BClR) will become active. Any circuitry
for forcing devices off the bus and re-arbitrating must
be provided external to the BAM.
Since the BAM is an asynchronous device, the bus
grant outputs are not guaranteed to be spike free, although the internal delay paths have been equalized to
minimize the occurrence of output spikes. The spikes
are caused by metastabling of the internal request input

latch. The arbitration cycle begins when one of the request inputs makes an active going transition. The request inpiJt latch is closed to prevent the encoder/decoder path from changing during the cycle. Requests
that change just as the latches are closing may cause
the latch to metastable or in essence attempt to latch
in an analog level in the feedback path of the latch. If
this metastable occurs in a request that is higher priority
than the request that initiated the cycle the two bus
grant outputs will spike alternately for approximately
50 ns. The metastable state should resolve itself into a
valid digital state within this time and the outputs will
stabilize to a valid state. These spikes can be removed
by disabling the bus grant outputs during the arbitration
cyle as shown in the circuit of Figure 3.
The BAM is an asynchronous state machine and is
sensitive to noise at certain state transition times. The
first critical time is the active transition of the DBRn
inputs. These inputs must have a 6.0 ns maximum fall
time to insure proper state transitions inside the part.
This 6.0 ns specification can be easily met by having an
lSTTl buffer drive a single DBRn input directly. Violation ofthis parameter mayforce the BAM into an invalid
state. In this state the part will ignore all inputs except
BGACK. The state can be cleared by bringing BGACK
active for at least 20 ns and returning it to the inactive
.
state.
The second critical time is the inactive transition of
BGACK. This signal must have a 6.0 ns maximum rise
time with no transitions for a minimum of 15 ns after
reaching threshold. Violation of these two parameters
may force the BAM into the same invalid state as discussed in the previous paragraph. Recovery procedures
are the same as above.

MODES OF OPERATION
local Central Arbiter
Figure 4 shows the BAM circuit in a local bus configuration. In this mode, the BAM serves as a central bus
controller as opposed to the distributed control of a
daisy-chain arbitration scheme. As shown, the BAM
provides the interface between the local bus masters
and the MC68000 MPU. The BR-BG pair of each local

MC68452

FIGURE 3 -

MOTOROLA
8-36

CIRCUIT TO DISABLE GRANT OUTPUTS
DURING ARBITRATION CYCLE

M68000 FAMILY
REFERENCE

MC68452

Address Bus
Data Bus
MC68000

BR
BG

BGACK
BG
~

DMAC

DBR7

DBG7

Memory

t
liD

IBGACK
~

Disk
Contr

DBR6

DBG6

MC68452
BAM

IBGACK
~

CRTC

BR
BG

DBR5
DBG5

iBGACK
FIGURE 4 -

LOCAL BUS ARBITER CONFIGURATION

bus master connect directly to the DBRn-DBGn pair of
BAM. The BR-BG pair of the processor connect directly
to the BR-BG pair of the BAM.
Whenever a device desires bus access it brings its BR
(DBRn) active. The BAM detects the active request and
makes a bus request (BR) to the processor. Within 1.5
clocks the MPU will return the BG to the BAM. This
signifies that the requesting device can obtain control
of the bus at the end of the current bus cycle. When the
BAM receives the BG from the processor it will issue
the DBGn to the highest priority requesting device.
When the next bus master observes the end of the current bus cycle, it should bring BGACK active and begin
to transfer. As long as the BGACK is held active the user
can continue bus cycles indefinitely. When the current
user completes the transfer it should release the BGACK
to allow others to use the bus. If there is another request
pending, the MC68000 MPU will remain in the idle state
and another device will be allowed to become'bus master. When no devices have a pending request the BAM
will remove the BR from the MPU and allow the processor to resume execution.

Global Bus Arbiter
Figure 1 shows a moderately coupled multiprocessor
system utilizing the BAM circuit. The global BAM serves
as the central bus controller of the shared global bus.

M68000 FAMILY

REFERENCE

f BGACK
This allows multiple local buses to share mass storage
and the addition of the more local processors to increase system throughput.
Figure 5 shows the global interface of each local bus.
Please note that this circuit is used as an example. It
will only support local bus masters with arbitration at
the end of every bus cycle. However, the BAM does not
preclude global bus masters and will certainly support
block transfers with the proper interface circuitry. The
local bus generates the DBRn by detecting some global
address on the address bus. As shown, the AS is used
in the DBRn equation to eliminate any switching noise
on the address decode signal. The local DTACK signal
also enters the DBRn equation to remove the request
before BGACK is released. In this configuration there is
no MPU to be removed from control of the global bus.
Therefore, the BR output is connected directly to the BG
input of the BAM. This allows a short delay before the
DBGn outputs are enabled to allow encoding/decoding
to proceed without switching noise appearing on the
outputs. The rest of the circuitry shown in Figure 4 is
used to generate the output enable for address/data
three-state drivers and the BGACK for this user. Since
the DBGn signal is removed when BGACK becomes
active the OEn is the logical OR of the DBGn and the
BGACKn for each user. The BGACK is generated when
the global bus generates the global DTACK (GDTACK).

MOTOROLA
8-37

MC68452

This will bring the clear active on the flip-flop which
brings BGACK low and removes the DBGn. After the
local bus recognizes the DTACK it will finish the cycle
by removing ASn. The rising edge of the AS clocks the
flip-flop and removes the BGACK which initiates another arbitration cycle. By removing BGACK at the end
of every cycle this circuit implements single cycle transfers. This is probably the most efficient way to operate

A1-A23

1---....,

Local Address Bus

if the MPU is performing the transfers. However, this
circuit can support local bus masters other' than the
MPU. If a DMA is performing the transfer, the clock to
the BGACK flop might be the END signal from the DMA
controller. Certainly both modes could be supported
easily by multiplexing these two clocks together using
single cycle for program I/O cycles and block mode for
DMA cycles.

3-State
Buffer

Global Address Bus

MC68000

00- 015

Global Data Bus

RIW
AS

3·State
Buffer

ODS
LDS
OTACK

GRIW
GAS
GUDS
GLOS
GDTACK

MC68452

....---(] LEi BGACR
+5 __JV~----~------------~
FIGURE 5 - GLOBAL BUS ARBITER CONFIGURATION

Expanding the Arbiter
If a system requires more than eight bus masters the
BAMs can be cascaded to any number of users required.
Figure 6 shows a circuit that can support up to 64 bus
masters. To support 64 users, nine BAMs are required.
Eight,parts supply the DBRn-DBGn request-grant pairs,
and one piut monitors status of the eight parts in parallel to supply the BCLR signal and handle the eight

MOTOROLA
8-~8

asynchronous BR outputs. As shown, the BR outputs
of the parallel parts are connected to the DBRn inputs
of the expansion BAM. This preserves the physical
priority and handles the asynchronous expansion. By
expanding in this way, the BAMs can operate correctly,
however, the arbitration cycle will now require 80ns
max.

M68000 FAMILY
REFERENCE

MC68452

.•
:

~'------"-'...,

SYSBGACK~~---~--------------~

FIGURE 6 - EXPANDED BAM CONFIGURATION

BAM SIGNAL DIAGRAM

VCC
VCC
DBG4
DBR3
DBG5
DBR2
DBR1
GND
DBRO
LEI
BGACK
DBG7
DBG6
GND

M68000 FAMILY
REFERENCE

GND
BCLR
DBGO
DBR4
DBG1
DBR5
DBR6
DBR7
BG
BR
DBG2
DBG3
VCC
VCC

MOTOROLA
8-39

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

MC68901

Technical Summary

Multi-Function Peripheral
The MC68901 multi-function peripheral (MFP) is a member of the M68000 Family of peripherals.
The MFP directly interfaces with the MC68000 microprocessor via the asynchronous bus structure.
Both vectored and polled interrupt schemes are supported with the MFP providing unique vector
number generation for each of its 16 interrupt sources. Additionally, handshake lines are provided
to facilitate DMAC interfacing.
The MC68901 performs many of the functions common to most microprocessor-based systems.
The resources available to the user include:
• Eight Individually Programmable I/O Pins with Interrupt Capability
• 16-Source Interrupt Controller with Individual Source Enable and Masking
• Four Timers, Two of which are Multi-Mode Timers
.
• Single-Channel Full-Duplex Universal Synchronous/Asynchronous Receiver-Transmitter
(USART) that Supports Asynchronous and with the Addition of a Polynomial Generator
Checker that Supports Byte Synchronous Formats

BLOCK DIAGRAM
ClK

RESET

VCC

GND

TCO
TOO
XTAL1
XTAL2

DATA
(81

TAO
TAl

--+- TBO
TBI

Rm
OS
DTACK

USART

SI
RC
SO
TC

fA
10-17

This document contains information on a new product. Sp~cifications and information herein are subject to change without notice.

MOTOROLA MOTOROLA
8~40

M68000 FAMILY

REFERENCE

MC68901

By incorporating multiple functions within the MFP, the
system designer retains flexibility while minimizing device count.
From a programmer's point of view, the versatility of
the MFP may be attributed to its register set. The registers
are well organized and allow the MFP to be easily tailored
to a variety of applications. All ofthe 24 registers are also
directly addressable which simplifies programming. The
register map is shown in Table 1.

SIGNAL DESCRIPTION
The following paragraphs contain a brief description
of the input and output signals. These signals can be
functionally organized into groups as shown in Figure 1.

NOTE
The terms assertion and negation will be used extensively. This is done to avoid confusion when

dealing with a mixture of "active low" and "active
high" signals. The term assert or assertion is used
to indicate that a signal is active or true, independent of whether that level is represented by a high
or low voltage. The term negate or negation is used
to indicate that a signal is inactive or false.

VCC AND GND
These inputs supply power to the MFP. The Vee is
powered at + 5 volts, and GND is the ground connection.

CLOCK (ClK)
The clock input is a single-phase TTL-compatible signal
used for internal timing. This input should not be gated
off at any time and must conform to minimum and maximum pulse width times. The clock is not necessarily the
system clock in frequency or phase.

Table 1. MFP Register Map
Address
Hex

Binary

Abbreviation

RSS

RS4

RS3

RS2

RS1

GPDR

AER

DDR

Data Direction Register

IERA

Interrupt Enable Register A

General Purpose 110 Data Register
Active Edge Register

IERB

Interrupt Enable Register B

IPRA

Interrupt Pending Register A

IPRB

Interrupt Pending Register B

ISRA

Interrupt In-Service Register A

ISRB

Interrupt In-Service Register B

IMRA

Interrupt Mask Register A

IMRB

Interrupt Mask Register B

TACR

Timer A Control Register
Timer B Control Register

Vector Register

·0

TBCR

·1

TCDCR

Timers C and D Control Register

TADR

Timer A Data Register

TBDR

Timer B Data Register

TCDR

Timer C Data Register

TDDR

Timer D Data Register

·1

SCR

Synchronous Character Register

UCR

USART Control Register

RSR

Receiver Status Register

TSR

Transmitter Status Register

UDR

USART Data Register

NOTE: Hex addresses assume that RS1 connects with A1, RS2 connects with A2, etc. and that DS is connected to LDS on the MC68000
or DS is connected to DS on the MC68008.

M68000 FAMILY
REFERENCE

MOTOROLA
8-41

MC68901

VCC

10-17

GND
ClK

DO-D7

TAl

~TA ":Y

TBI
TAO
TBD

ASYNCHRONOUS
BUS CONTROL

{OSOS

TIMER
CONTROL

TCO
TOO

RMi

MFP

DTACK

XTALl
XTAL2

RS1-RS5
SI
RESET

INTERRUPT
CONTROL

{

SO } SERIAL 110
CONTROL
RC
TC

IRO
lACK

lEi

lEO

} DIRECT MEMORY
ACCESS
CONTROL

Figure 1. Input and Output Signals
DATA BUS (DO through 07)
This three-state bidirectional bus is used to transmit
data to or receive data from the MFP's internal registers
during a processor read or write cycle, respectively. Ouring an interrupt acknowledge cycle, the data bus is used
to pass a vector number to the processor. The MFP must
be located on data bus lines 00-07 when used with an
MC68000, MC68008, or MC68010 and on data lines 024031 when used with an MC68020, if vectored interrupts
are to be used.
ASYNCHRONOUS BUS CONTROL
Asynchronous data transfers are controlled by chip select, data strobe, read/write, and data transfer acknowl~
edge. The register select lines, RS5-RS1, select an internal
MFP register for a read or write operation. The reset line
initializes the MFP registers and the internal control signals.
Chip Select (CS)
This active low input activates the MFP for internal
register access. CS and lACK must not be asserted at the
same time.

OTACK to indicate that the information on the data bus
is valid. If the bus cycle is a processor write to the MFP,
OTACK acknowledges the acceptance of the data by the
MFP. OTACK will be asserted only by an MFP that has
CS or lACK (and iIi) asserted.
REGISTER SELECT BUS (RS1 through RS5)
The register select bus selects an internal MFP register
during a read or write operation.
RESET (RESET)
This active low input will initialize the MFP during powerup or in response to a total system reset.
INTERRUPT CONTROL
The interrupt request and interrupt acknowledge signals are handshake lines for a vectored interrupt scheme.
Interrupt enable in and interrupt enable out implement a
daisy-chained interrupt structure.

ReadIWrite (RIW)
This input defines the current bus cycle as a read (high)
or a write (low) cycle.

Interrupt Request (IRQ)
This active low, open-drain output signals to the processor that an interrupt is pending from the MFP. There
are 16 interrupt channels that can generate an interrupt
request. Clearing the interrupt pending registers (lPRA
and IPRB) or clearing the interrupt mask registers (lMRA
and IMRB) will cause the IRQ to be negated. IRQ will also
be negated as the result of an interrupt acknowledge
cycle, unless additional interrupts are pending in the MFP.

Data Transfer Acknowledge (DTACK)
This active low,three-state output signals the completion of the operation phase of a bus cycle to the processor. If the bus cycle is a processor read, the MFP asserts

Interrupt Acknowledge (lACK)
If both IRQ and iIi are asserted, the MFP will begin an
interrupt acknowledge cycle when lACK and OS are asserted. The MFP will supply a unique vector number to

Data Strobe (OS)
This active low input is part of the internal chip select
and interrupt acknowledge functions.

MOTOROLA
8-42

M68000 FAMILY

REFERENCE

MC68901

the processor which corresponds to the particular channel requesting interrupt service. In a daisy-chained interrupt structure, all devices in the chain must have a
common lACK. CS and lACK must not be asserted at the
same time.
Interrupt Enable In (lEI)
This active low input, together with the lEO signal, provides a daisy-chained interrupt structure for a vectored
interrupt scheme. iEi indicates that no higher priority device is requesting interrupt service. So, the highest priority MFP in the chain should have its iEi pin tied low.
During an interrupt acknowledge cycle, an MFP with a
pending interrupt is not allowed to pass a vector number
to the processor until its iEi pin is asserted. When the
daisy-chain option is not implemented, all MFPs should
have their iEi pin tied low.
Interrupt Enable Out (lEO)
This active low output, together with the iEi signal,
provides a daisy-chained interrupt structure for a vectored interrupt scheme. The lEO of a particular MFP signals lower priority devices that neither it nor any other
higher priority device is reques!!!!.g interrupt service.When
a daisy-chain is implemented,lEO is tied to the next lower
priority MFP's iEi input. The lowest priority MFP's lEO is
not connected. When the daisy-chain option is not implemented, lEO is not connected.
GENERAL PURPOSE I/O INTERRUPT LINES (10 through
17)
These lines constitute an 8-bit pin-programmable I/O
port with interrupt capability. The data direction register
(DDR) individually defines each line as either a highimpedance input or a TTL-compatible output. As an input,
each line can generate an interrupt on the user selected
transition of the input signal.
TIMER CONTROL
These lines provide internal timing and auxiliary timer
control inputs required for certain operating modes. Additionally, the timer outputs are included in this group.
Timer Inputs (TAl and TBI)
These inputs are control signals for timers A and B in
the pulse width measurement mode and the event count
mode. These signals generate interrupts at the same
priority level as the general purpose I/O interrupt lines 14
and 13, respectively, when in the pulse width measurement mode. While 14 and 13 do not have interrupt capability when the timers are operated in this mode, they
may still be used for I/O.
Timer Outputs (TAO, TBO, TCO, and TOO)
Each timer has an associated output which toggles when
its main counter counts through 01 (hexadecimall regardless of which operational mode is selected. When in
the delay mode, the timer output will bea square wave
with a period equal to two timer cycles. This output may
be used to supply the universal synchronous/asynchronous receiver-transmitter (USART) baud rate. clocks.

M68000 FAMILY

REFERENCE

Timer Clock (XTAL 1 and XTAL2)
This input provides the timing signal for the four timers.
A crystal can be connected between the timer clock inputs, XTAL 1 and XTAL2, or XTAL 1 can be driven with a
TTL-level clock while XTAL2 is not connected. The following crystal parameters are suggested:
a) Parallel resonance, fundamental mode AT-cut, HC6
or HC33 holder
b) Frequency tolerance measured with 18 picofarads
load (0.1% accuracy) - drive level 10 microwatts
c) Shunt capacitance equals 7 picofarads
d) Series resistance:
2.0 < f < 2.7 MHz; Rs 0.13 (O.OOS) ®ITIA®IB®I
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.SM, 1982.
4. CONTROLLING DIMENSION: INCH.

1+1

DIM
A
B
C
0
G
K

M68000 FAMILV.

REFERENCE

MILLIMETERS
MAX
MIN
26.67
27.17
26.67
27.17
2.09
2.59
O.SO
0.43
2.54 BSC
4.82
4.32

INCHES
MIN
MAX
1.0SO
1.070
1.0SO
1.070
0.082
0.102
0.017
0.020
0.100 BSC
0.170
0.190

MOTOROLA
9-11

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 84-Terminal

CASE 793-03

-fr

K @@@@@@@m

@@@@@,@@ 0
@@@@@I@@@ 0 0
G @@@
@@@
J

@@@
@@~

@@@
~@@

o @@@

.A
IC
--.-1 B

.-I.----I[[]I----.j

L
I I

I
@@@
@@@@@@@@@@
@@@@@'@@@@@
@@@@@@@@@@
1 2

3 4

5 6

7 8

9 10

~D_M_P_L____~~__~~
t cf> 0.13 (0.005) @ T A @ B@

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.

DIM
A
B
C
D
G
K

MOTOROLA
9-12

MILLIMETERS
MIN
MAX
27.43
27.43
2.04
2.66
0.44
0.60
2.54 BSC
4.32
4.82

INCHES
MIN
MAX
1.080
1.080
0.080
0.105
0.017
0.024
0.100 BSC
0.170
0:190

M68000 FAMILY

REFERENCE

_ _ _ _ _ _ _ _ _ _ _ _ _.114-Terminal _ _ _ _ _ _ _ _ _ _ _ _ __

CASE 791-01

N ®®®®®®®®®® o·H+ti+*-~
M® ®® ®® ®®® ®® o.}f+1f+)f---':;:'"
l ®®®®®®®®®®®
K®®®
®®
J®®®
®®
H®®®
®®
G ®®®
®®®
F®®®
®®
E®®®
®®
D®®®
®®
C®®®®®®®®®®®®®
B®®®®®®®®®®®®®
A@)®®®®®®®®®®®®
0

1 2 3 4 5 6 7 8 9 10 11 12 13

NOTES:
1. A AND B ARE DATUMS AND T IS A DATUM
SURFACE.
2. POSITIONAL TOLERANCE FOR LEADS
(114 PLACES).
1+1 0.13 (0.005) ® 1T 1A ® 1B ® 1
3. DIMENSIONING AND TOLERANCING PER Y14.5M,
1982.
4. CONTROLLING DIMENSION: INCH

DIM
A
B
C
D
G

M68000 FAMILY

REFERENCE

MllUMETERS
MIN
MAX
34.04
35.05
34.04
35.05
2.54
3.81
0.43
0.55
2.54 BSC
4.32
4.95

INCHES
MIN
MAX
1.340
1.380
1.340
1.380
0.100
0.150
0.017
0.022
0.100 BSC
0.170
0.195

MOTOROLA
9-13

_ _ _ _ _ _ _ _ _ _ _ _ _.128-Terminal _ _ _ _ _ _ _ _ _ _ _ _ __

CASE 789C-Ol

-FF

n
·A·

~
[±J

'
l
~

I.-

N ®@@@@@@@@@(OoJ~m-~
M @@@@@@@@@@~o~m---r
L @@@@@@@@@@@ 0 0
K@@@@@
@@@@
G
J @@@
@@@
H @@@
@@@
G @@@
@@@
F @@@@
@@@@
E @@@
@@@
D@@@@@
@@@@
C@@@@@@@@@@@,@,@
B@@@@@@@@@@@@@
A@@@@@@@@@@@@@
1

2 3 4 5 6 7 8 9 10 11 12 13

o 1+1 cf> 0.13 (O.OOS) ®I T IA@IB@I

NOTES:
1. A AND B ARE DATUMS AND T IS A DATUM
SURFACE.
2. DIMENSIONING AND TOLERANCING PER YI4.5M.
1982.
3. CONTROLLING DIMENSION: INCH.

DIM
A
B
C
D
G
K

MOTOROLA
9-14

MIWMETERS
MIN
MAX
34.04 35.05
34.04 35.05
2.54
3.81
0.44
0.55
2.54BSC
4.95
4.32

INCHES
MIN
MAX
1.340
1.380
1.340
1.380
0.150
0.100
0.017
0.022
0.100 BSC
0.170
0.195

M68000 FAMILY

REFERENCE

_ _ _ _ _ _ _ _ _ _ _ _ _.132-Terminal _ _ _ _ _ _ _ _ _ _ _ _ __

CASE 789B-01

-FrK

N 0 ®® ®® ®®® ® ® o}#t(+tf-.,.--.L..
M ®®®®®®®®®® o·Htt~-..
L ®®®®®®®®®®® 0 0
K®®®®®
®®®®®
G
J ®®®®
®®®®
H ®®®
®®®
G ®®®
®®®
F ®®®
. ®®®
E ®®®®
®®®®
o ®®®®®
®®®®®
c®®®®®®®®®®®®®
B®®®®®®®®®®®®®
OD A®®®®®®®®®®®®@

'r
B

_t
t

1 2 3 4 5 6 7 8 9 10 11 12 13

NOTES:
1. A AND BARE DATUMS AND T IS A DATUM
SURFACE.
2. POSITIONAL TOLERANCE FOR LEADS 1132 PLI.
1+14>0.13(0.0051 ®I T 1A@I B@I
3. DIMENSIONING AND TOLERANCING PER Y14.5M.
1982.
4. CONTROLLING DIMENSION: INCH.

DIM
A
B
C
D
G
K

M68000 FAMILY

REFERENCE

MILUMETERS
MAX
MIN
35.05
34.04
35.05
34.04
2.54
3.81
0.43
0.55
2.54 BSC
4.32
4.95

INCHES
MIN
MAX
1.340
1.380
1.380
1.340
0.100
0.150
0.022
0.017
0.100 BSC
0.195
0.170

MOTOROLA
9-15

9.4 QUAD PACKAGES

52-Lead

CASE 778-02

B 1+10.18 (0.0071 ®

YBRK

\-D

I TIN ®-p®1

L(:~-M ®I

u 1+lo.18(0.007l® ITI N®-p®1 L®-M®\

. . - - - - - - - - t - A 1+\0.18(0.0071 ® \T\ L®-M®I N®-P®\

~-----tt-R

1+10.18 (0.0071 ®

1+10.25(0.010) ® ITI N®-P®I L®-M®I
VIEWD-D

I TIL ®-M ®I N ®-P ® I

DETAIL S

1+10.25 (0.0101 ®

DIM

A
B
C
E

F
G
H

J
K
R
U

V
W
X
Y

Z
Gl
Kl
Zl

MOTOROLA
9-16

MILUMETERS
MIN
MAX
19.94
20.19
19.94
20.19
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
19.05
19.20
19.05
19.20
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
18.04
18.54
1.02
10°
2°

INCHES
MIN
MAX
0.785
0.795
0.785
0.795
0.165
0.180
0.110
0.090
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.756
0.750
0.750
0.756
0.048
0.042
0.042
0.048
0.042
0.056
0.020
2°
10°
0.710
0.730
0.040
2°
10°

NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL
BE REPRESENTED BY A GENERAL (SMALLERI
CASE OUTLINE DRAWING RATHER THAN
SHOWING ALL 52 LEADS.
2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT PLASTIC
BODY AT MOLD PARTING LINE.
3. DIM G1. TRUE POSITION TO BE MEASURED AT
DATUM -T-, SEATING PLANE.
4. DIM RAND U DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.25 (0.0101 PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M,1982.
6. CONTROLLING DIMENSION: INCH.

M68000 FAMILY

REFERENCE

S8-Lead

CASE 779-02

B 1--.10.18(0.007)

YBRK

I-D

® ITI N®-p®1 L®-M®I

1... 10.18(0.007)

® ITI N®-p®1 L®-M®I

t - - - - - - - - + - A 1--.10.18/0.0071

ITI L®-M®I N®-P®I

Ho------H--R 1--.10.18 (0.0071

I TIL ®-M ®I N ®-P ® I

1--.10.25(0.0101
VIEWD·D

1TI N®-P®I L®-M®I

DETAIL S

1+10.25 (0.0101 ®

1TIL ®-M ®I N ®-P ® 1

DIM
A
B
C
E

F
G
H

J
K
R
U
V

W
X
Y

Z
G1
K1

M68000 FAMILY

REFERENCE

MILUMETERS
MIN
MAX
25.02
25.27
25.02
25.27
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
0.64
24.13
24.28
24.13
24.28
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
23.62
23.12
1.02
2°
10°

INCHES
MIN
MAX
0.985
0.995
0.985
0.995
0.180
0.165
0.110
0.090
0.013
0.019
0.050 BSC
0.026
0.032
0.020
0.025
0.950
0.956
0.956
0.950
0.042
0.048
0.042
0.048
0.042
0.056
0.020
2°
10°
0.910
0.930
0.040
2°
10°

NOTES:
1. DUE TO SPACE LIMITATION, CASE 779-02 SHALL
BE REPRESENTED BY A GENERAL (SMALLER I
CASE OUTLINE DRAWING RATHER THAN
SHOWING ALL 68 LEADS.
2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT PLASTIC
BODY AT MOLD PARTING LINE.
3. DIM Gl, TRUE POSITION TO BE MEASURED AT
DATUM -T-, SEATING PLANE.
4. DIM RAND U DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.25 (0.0101 PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
6. CONTROLLING DIMENSION: INCH.

MOTOROLA

9-17

MOTOROLA
9-18

M68000 FAMILY
REFERENCE

TECHNICAL SUPPORT

SECTION 10
TECHNICAL SUPPORT
The technical support described in this section includes literature and training offered by Motorola.
The section also lists sources of literature and training and the Motorola Sales Offices.

10.1 LITERATURE
The M68000 Family, along with the entire high-end MPU product line, is supported by publicly
available technical documentation at three levels: product previews, technical summaries, and

user's manuals.
During the early stages of the development of a product, a product preview is prepared and
published. A product preview provides a very high-level generalization of the product arid its
major features. The purpose of the product preview is to document specific information about
Motorola's future plans. The audience for this document ranges from the technical and trade
press to the engineering community.
The product preview is supplied in response to requests for. information about a product under
development. The information in the product preview is purposely limited in order to avoid
disclosure of patentable or other proprietary information and to withhold information from competitors. The availability of a product preview for a new product usually indicates that further
information required to support specific design-ins is available to those willing to sign nondisclosure agreements.
As the development of a new product approaches completion, the technical summary replaces
the product preview. Typically, the technical summary provides a block diagram of the component
and a brief description of each of the major elements of the block diagram. A summary of the
major features of the device is included with sufficient information to allow a system architect,
planner, or engineering manager to determine whether the product meets design objectives. The
technical summary may show a signal list, register models, instruction set summaries, etc. The
product description in the technical summary may vary in the amount of detail included, as
required for a specific product, but typically does not discuss implementation details. For example,
signal lists and register descriptions may be shown in general tables but are not addressed in
any detail. Detail is limited to provide a good understanding of the important aspects of the
product without the exhaustive detail appropriate for the user's manual. The audience of the
technical summary includes design engineers, systems architects, all levels of engineering management, the press, etc.
The technical summary is intended to provide enough information about the product to allow
decision-makers to determine whether the product meets the gross requirements fortheir systems.
It is also intended to inform the technical and trade press, enabling them to answer commonly
asked questions and to write accurate editorial comments. The technical summary is not intended
to provide enough information for detailed design.
.
Additionally, the technical summary is the vehicle for publishing the initial electrical specifications
and updating electrical specifications throughout the life cycle of the product. Prior to publication

M68000 FAMILY

REFERENCE

MOTOROLA
10-1

1m
•

of a user's manual, the technical summary is the means by which Motorola publishes preliminary
specifications to facilitate design activities with the product. These preliminary specifications are
typically used with the proprietary design specifications (available under nondisclosure) for designs that include the product. As new electrical specifications become available, the specifications
in the technical summary are updated. Because the technical summary can be quickly revised, it
is used for fast publication of new information.
The user's manual provides the comprehensive, detailed information required to design a system
that uses an M68000 component. It includes a complete description of the device and its operation,
information about the use of the part, and relevant programming information. The user's manual
is the authoritative source of product information. The audience for the user's manual includes
systems architects and designers, software engineers and programmers, and the first tier of
engineering management. Component engineering and other support functions also require the
information in the user's manual. The user's manual is expected to provide a detailed description
of all user-visible aspects of the component and to answer applications-related questions about
each of these aspects.

User's manuals vary in length, but often contain several hundred pages. These manuals are
updated infrequently because of their size. Motorola recommends that design engineers always
have up-to-date. copies of the user's manual and the technical summary at hand during the design
activities.
Advance information data sheets provide the user's manual information for M68000 Family peripheral products. User's mimuals are not available for these devices. Table 10-1 summarizes the
literature provided for the high-end products.
To fill the need for information about third-party software that is available for Motorola microprocessors, Motorola publishes a catalog of software products. The catalog lists the products and
the suppliers from whom they can be purchased. Listings in the catalog contain descriptions
supplied by the vendors. To obtain a copy, order:
BR506/D

The SOURCE

Literature is listed in this manual for your information. Call or write the Motorola Semiconductor
Product Sector Literature Distribution Center for latest listings and price information at:
Motorola Semiconductor Products Sector
Literature Distribution Center
P.O. Box20924
Phoenix, AZ 85036-0924
Phone: (602) 994-6561
Literature is available to the educational community on a special basis, described in the University
,Support Program, brochure. For a copy, or for details and prices, call or write the University
Support Organization:
Motorola Technical Operations
University Support Program/HW68
P.O. Box 21007
Phoenix, AZ 85036
, Phone: (602) 244-6777 'or (602)244-7130

.MOTOROLA

10-2

M68000 FAMILY

REFERENCE

Table 10-1. MPU Product Literature
Product

Technical Summary

Data Sheet

User's Manual

MC68000

BR245/D

M68000UM/AD Rev. 5

MC68851

BR299/D

MC68881

BR265/D

MC68882

BR509/D

MC68153

BR530/D

MC68153/D

MC68184

BR286/D

MC68184/D

MC68194

BR287/D

MC68194/D

MC68230

BR263/D

MC68230/D

MC68440

BR260/D

MC68440/D

MC68450

BR251/D

MC68HCOOO

BR275/D

MC68008

BR259/D

MC68010

BR269/D

MC68020

BR243/D

MC68030

BR508/D

MC68452

M68000UM/AD Rev. 5
M68000UM/AD Rev. 5
M68000UM/AD Rev. 5
MC68020UM/AD
MC68030UM/AD
MC68851UM/AD
MC68881UM/AD
MC68881 UM/AD

MC68450/D
MC68452/D

MC68605

BR272/D

MC68605/D

MC68606

BR520/D

MC68606/D

MC68652

MC68652/D

MC68661

MC686611D

MC68681

BR220/D

MC68681/D

MC68824

BR280/D

MC68824/D

BR587/D

MC68901/D

MC68901

10.2 TECHNICAL TRAINING
Training is available on audio cassettes as well as in-class s~ssions at Motorola's training centers.
Motorola technical training courses are scheduled throughout the world, with training centers in
the United States, Canada, South America, Europe, Australia, and the Asia-Pacific area. Motorola
also conducts courses at customer's facilities. Training is provided under the direction of Technical
Operations whose address is:
Motorola Semiconductor Products Sector
Technical Operations, HW68
P.O. Box 21007
Phoenix, AZ 85036
Complete information about Motorola's technical training, including descriptions, schedules, and
prices of all ~ourses, is listed in the Technical Training Catalog (BR348/D).
10.2.1 Audio Cassette Courses
Three M68000 Family audio cassette courses follow the evolutionary, upward-compatible growth
of the Family. Figure 10-1 shows the flow from the first MPU'on the Family, the MC68000, through

M68000 FAMILY

REFERENCE

MOTOROLA
10-3

NO KNOWLEDGE
OF M6BOOO FAMILY

MC68000

COURSE

t---,--+-I WORKING KNOWLEDGE

OF M6BOOO FAMILY
FAMILIAR WITH M6BOOO FAMILY

IMC6BOOO, MC6B010, OR MC6BOOB

MC68020

COURSE

I-----.J

WORKING KNOWLEDGE
OF MC6B020

FAMILIAR WITH
MC6B020 '

MC68030

COURSE

'-----.J

WORKING KNOWLEDGE
OF MC6B030

NOTE: While the material in an audio or instructor-led course is similar, the audio casette courses are intended for those
who do not require the full content and labs available in an instructor-led course.

Figure 10-1. Audio

C~~sette

Courses

the 32-bit MC68020, to the MC68030, the newest member of the Family. The material in the audio
cassettes is similar to the content of courses taughtatthe training centers, but those who require
an instructor-led course with lab sessions should choose training center courses rather than audio
cassette training.
The courses are:
MITA 1 An Introduction to the MC68000 16-Bit Microprocessor
Prerequisites: The student should be familiar with memory concepts, binary numbers, hexadecimal number notation, binary arithmetic, and standard logic operations. Experience with an 8bit microprocessor, a 16-bit minicomputer, or a mainframe is helpful.
Content: This course covers the major functions of the MC68000: pins and bus operation, programming model, addressing modes, instruction set, and exception processing (including interrupts). Software and hardware examples are included. Upon successful completion, the student
will have a working technical knowledge of the. MC68000.

MOTOROLA
10-4

M68000 FAMILY

REFERENCE

MITA2 An Introduction to the MC68020 32-Bit Microprocessor
Prerequisites: MTTA 1 or equivalent knowledge of the MC68000 is required.
Content: This course covers the major features of the MC68020: internal architecture, programming model, pins and bus operation, addressing modes, instruction set, and exception processing.
Upon successful completion, the student will have a working technical knowledge ofthe MC68020.
MITA3 An Introduction to the MC68030 32-Bit Microprocessor
Prerequisites: MTTA2 or equivalent knowledge of the MC68020 is required.
Content: This course covers the major features of the MC68030: data cache; burst mode, synchronous bus, and the internal memory management unit. Upon successful completion, the
student will have a working technical knowledge of the MC68030.
10.2.2 Classroom Courses
The following courses, particularly oriented to the M68000 Family of microprocessors, are offered
at Motorola's Technical Training Centers:
MIT7 Understanding Microprocessor Basics -

1 day

Prerequisites: None.
Content: This course is for individuals who do not already possess a working knowledge of
microprocessors. It is a nontechnical course to acquaint managers, secretaries, buyers, salespeople, and others with microprocessors. Upon successful completion, the student will know the
terminology and understand basic concepts.
MIT8 MC68000 16-/32-Bit Microprocessor -

4 days

Prerequisites: The student should be familiar with memory concepts, binary numbers, hexadecimal number notation, binary arithmetic, and standard logic operations. Experience with an 8bit microprocessor, a 16-bit minicomputer, or a mainframe is helpful.
Content: This course introduces the student to the MC68000 microprocessor. It describes the
general features of the MC68000, such as pin functions, registers, addressing modes, and the
instruction set. It also discusses the unique features such as primitive instructions for high-level
software, exception handling, and position independent machine code generation. The course
includes two lab sessions to provide hardware and software experience. Upon successful completion, the student will be prepared to use and design with the MC68000, the MC68008, or the
MC68010.
'
MIT20 MC68020 32-Bit Microprocessor - 4 days
Prerequisites: The student must have detailed knowledge ofthe MC68000, MC68008, or MC68010
(course MTT8 or equivalent).
Content: This course introduces the student to the MC68020 32-bit microprocessor. It discusses
the general features: pin functions, registers, addressing modes, and the instruction set. It also

M68000 FAMILY

REFERENCE

MOTOROLA'

10-5

describes the unique features, such as primitive instructions for high-level software, exception
handling, and modular code generation. The course includes one lab session, which provides
experience with the hardware and software. Upon successful completion, the student will be
prepared to use and design with the MC68020.

MTT30 MC68030 Enhanced 32-Bit Microprocessor
Prerequisites: The student must have detailed knowledge of the. MC68020 (course MTT20 or
equivalent).
Content: This course introduces the student to the MC68030 enhanced 32-bit microprocessor. It
discusses the major features: data cache, burst mode, synchronous bus, and the internal memory
management unit. Upon successful completion, the student will be prepared to use and design
with the MC68030.

To enroll in a class at a domestic training center, call (800) 521-6274. For more information abo·ut
courses, including schedules and prices, call (602) 244-7126. Outside the U.S., call thenulTlberof
the training center nearest you; numbers of these training centers are listed with their addresses
in the first part of this section.
.
Training is offered at the following training centers i'n·the United States:
Austin
Motorola Traini'lg and Education Center
1701' Director's Blvd., Suite 480
Austin, TX' 78744 '
'
Phone: (512) 444~7725

Phoenix
Motorola Technical Training Center
4902 E. McDowell Rd., Suite 115
Phoenix, AZ 85008
Phone: (602) 244-7126

Boston
Motorola Technical, Training Center
300 Unicorn Park Dr.
'
'
Wobu'rn, MA 01801
Phone: (617) 932-9700

San Jose
Motorola Technical Training Center
1150 Kifer Road.
Sunnyvale, CA 94086
Phone:' (408) 749-0510

Chicago
Motorola Technical Training Center
1295 E. Algonquin
.
Schaumburg,IL 60196
Phone: (312) 576-8600

Toronto
Motorola Technical Training Center
4000 Victoria .Park Ave.
North York, Ontario M2H 3P4
Phone: (416) 497-8181

Dallas
Motorola Technical Training Center
1200 E. Campbell Rd., Suite 108
Richardson, TX 75081
Phone: (214) 699-3900

Washington, D.C~
Motorola Technical Training Center
8200 Professional Place, Suite 114.
Hyattsville, MD 20785
Phone: (301) 577-2600

MOTOROLA
10-6

MS8000 FAMILV

REFERENCE

Worldwide, Motorola operates training centers in the following countries:'

FRANCE
Motorola Semiconducteurs Commercial S.A.
Main Sales Office
2 Rue Auguste Comte BP39
92173 Vanves Cedex, France
Phone: (1) 47 36 03 41
GERMANY
Motorola GMBH
Schulungszentrum
Arabellastr. 17
0-8000 Muenchen 81, Germany
Phone: (89) 9272-142
HONG KONG
Motorola Technical Training
Profit Industrial Building,
7th Floor, Phase 2,
1-15 Kwai Fung Crescent
Kwai Chung, N.T.
Hong Kong
,Phone: 0-223111
ISRAEL
Motorola Israel Semiconductors & Systems (SPS) Ltd.
145 Bialik Street
Ramat, Israel
Phone: ·972-3-7538288
ITALY
Motorola S.P.A. ,
Oivisione Semiconduttori
Centro Milanofioro-Strade 2-C2
20090 Assago Milano, Italy
Phone: 928 22 01 .
SPAIN
Motorola Espania S.A.
Albert Alocer, 46 OPOO
28016 Madrid, Spain
Phone: 457 82 04
SWEDEN
Motorola' AB, Oalvaegen 2,
S-171 36 Solna, Sweden,
Phone: (8) 8300200
ENGLAND
Motorola Technical Training
Fairfax House
69 Buckingham Street
Aylesbury
Buckinghamshire, United Kingdom
Phone: (0296) 393312

M68000 FAMILY
REFERENCE

MOTOROLA
10-7

10.3 MOTOROLA SALES OFFICES
All Motorola semiconductor products are supported throughout the U. S. and worldwide by local
and regional sales offices. In addition to Motorola's professional sales staff, highly experienced
field application engineers provide local techical support through these sales offices.
The cities in which Motorola Semiconductor Products Sector sales offices are located and the
telephone numbers of those offices are: .

DISTRICT OFFICES
ALABAMA, Huntsville .................................................................. (205)
ARIZONA, Phoenix ......................................................................(602)
CALIFORNIA, Agoura Hills ............................................................ (818)
CA.LlFORNIA, Los Angeles ............................................................. (213)
CALIFORNIA, Orange .............................................................. ~ ..... (714)
CALIFORNIA, Sacramento ............................................................. (916)
CALIFORNIA, San Diego ............................................................... (619)
CALI FORNIA, San Jose ................................................................ (408)
COLORADO, Colorado Springs ....................................................... (303)
COLORADO, Denver .................................................................. :.(303)
CON NECTICUT, Wallingford .......................................................... (203)
FLORIDA, Maitland ...................................................................... (305)
FLORIDA, Pompano Beach/Ft. Lauderdale ......... : ............................... (305)
FLORIDA, St. Petersburg.; ................... : .... ; .................................... (813)
GEORGIA, Atlanta ....................................................................... (404)
ILLINOIS, Chicago/Schaum bu rg ..................................................... (312)
INDIANA, Fort Wayne ............................................................ ,....... (219)
INDIANA, Indianapolis ....... ; ......................................................... (317)
INDIANA, Kokomo ...................................................................... (317)
IOWA, Cedar Rapids ....................................................................(319)
KANSAS, Kansas City/Mission ....................................................... (913)
MASSACHUSETTS, Marlborough ............ ; ...................................... (617)
MASSACHUSETTS, Woburn ......... ; ................................................ (617)
MICHIGAN, DetroitlWestland ......................................................... (313)
MINNESOTA, Minneapolis ............................................................ (612)
MISSOURI, St. Louis ....................................................................(314)
NEW JERSEY, Hackensack ............................................................. (201)
NEW YORK, Fairport ....................................................................(716)
NEW YORK, Hauppage .................................................................(516)
NEW YORK, Poughkeepsie/Fishkill .................................................. (914)
NORTH CAROLINA, Raleigh .......................................................... (919)
OHIO, Cleveland ......................................................................... (216)

MOTOROLA
10-8

830-1050
244-7100
706-1929
417-8848
634-2844
922-7152
560-4644
985-0510
599-7404
337-3434
284-0810
628-2636
486-9775
576-6030
449-0493
576-7800
484-0436
849-7060
457-6634
373-1328
384-3050
481-8100
932-9700
261-6200
941-6800
872-7681
488-1200
425-4000
361-7000
473-8102
876-6025
349-3100

M68000 FAMILV

REFERENCE

DISTRICT OFFICES (Continued)

OHIO, ColumbuslWorthington .............................................. ~ ........ (614)
OHIO, Dayton .............................................................................. (513)
OKLAHOMA, Tulsa ...................................................................... (918)
OREGON, Portland ...................................................................... (503)
PENNSYLVANIA, Philadelphia/Horsham ........................................... (215)
TENNESSEE, Knoxville ................................................................. (615)
TEXAS, Austin ........................................................................... (512)
TEXAS, Houston ......................................................................... (713)
TEXAS, Irving .~ .......................................................................... (214)
TEXAS, Richardson ..................................................................... (214)
VIRGINIA, Charlottesville .............................................................. (804)
WASHINGTON, Bellevue ............................................................. ;(206)
Seattle Access ......................................................................... (206)
WASHINGTON, DC/MARYLAND, Hyattsville ...................................... (301)
WISCONSIN, MilwaukeelWauwatosa ............................................... (414)

846-9460
294-2231
664-5227
641-3681
443-9400
690-5592
452-7673
783-6400
550-0770
699-3900
977-3691
454-4160
622-9960
577-2600
792-0122

CANADA

BRITISH COLUMBIA, Burnaby ........................................................ (604)
MANITOBA, Winnipeg ................................................................. (204)
ONTARIO, North York .................................................................. (416)
ONTARIO, Ottawa ....................................................................... (613)
QUEBEC, Montreal ...................................................................... (514)

434-9134
783-3388
497-8181
226-3491
731-5483

INTERNATIONAL SALES OFFICES

AUSTRALIA, Melbourne ................................................................ (03) 561-3555
AUSTRALIA, Sydney ..................................................................... (02) 438-1955
AUSTRIA, Vienna ....................................................................... (0222) 31 65 45
BRAZIL, Sao Paulo ...................................................................... (011) 572 3553
DENMARK, Soborg ....................................................................... (02) 92 00 99
FINLAND, Helsinki ..................•...................................................... (0) 69 48 455
FRANCE, Grenoble ...................................................................... (076) 90 22 81
FRANCE, Paris ........................................................................... (014) 736-01-99
FRANCE, Toulouse ...................................................................... (061) 41 90 00
GERMANY, Langenhagen/Hannover. .............................................. (0511) 78-99-11
GERMANY, Munich ..........................................................................(089) 92720

M68000 FAMILY

REFERENCE

MOTOROLA
10-9

INTERNATIONAL SALES OFFICES (Continued)
GERMANY, Nuremberg ......................................................... : ....... (0911) 643044
GERMANY, Sindelfingen .............................................................. (07031) 83074
GERMANY, Wiesbaden ...... :: .. : ........ : .......... : ............................... (06121) 76-1921
HONG KONG, Kwai Chung ............ ; .................... ; ............................... (0) 223111
ISRAEL, Tel Aviv ................ ·... '...........·........ ·..........................:.: ............ 03-7538222
ITALY, Milan .............................................................................·.......... (2) 8220f
ITALY, Rome ................................................................................... (06) 831 4746
JAPAN, Osaka .............................................................................. (06) 305 1801
JAPAN, Tokyo ............... ; ....................................................... ; ....... 03-440-3311
KOREA, Pusan ................................................................................. (51) 463-5035
KOREA, Seoul.··.......................................................................... (2) 554-5118-21
MALAYSIA,' Penang ............. ·.............. ·... '.................. ·.......................... 04-374514 '
MEXICO, D.F ..... :.; ........................................ ; ......... (525) 540-5187/(525) 540-5429'
NETHERLANDS; Maarssen ..... ;;: ............. : ........................... ; ........... (030) 439 653
NORWAY, Oslo .'............................................................................... (02) 19 80 70
PHILIPPINES, Manila ...................................................................... (2) 827-59-11
PUERTO RICO, San Juan ............................................................... 809-721-3070
SCOTLAND, East Kilbride ............................................................. (03552) 39 101
SiNGAPORE ........................................................................................ 2945438
SPAIN, Madrid ............................................................................ (01) 458 1061
SWEDEN, Solna ........................................·...·...................... ·..... : ......• (08) 83 02 00
SWITZERLAND, Geneva ................................................................ (022) 991 111
SWITZERLAND, Zurich ................................................................. (01) 730 40 74
TAIWAN, Taipei .. :: ........................................................................ (02) 752 8944·
UNITED KINGDOM, Aylesbury ................. ; ...................... ; ................ (296)395252

MOTOROLA
10-10

M68000 FAMILY
REFERENCE

DEVELOPMENT SYSTEMS

III

SECTION 11
DEVELOPMENT SYSTEMS
Motorola's total development system solutions include in-circuit emulators, host computer systems, and control stations. The host computer system integrates the tool set into a complete
development system for hardware and software development.
The Motorola tool set includes:
1. In-Circuit-Emulators, for all the M68000 Family of microprocessors: 16-bit MC68000,
MC68HCOOO, MC68008, and MC68010; and 32-bit MC68020 and MC68030.
2. Hardware Control Station, a controller that services each emulator and establishes the
linkage to the host computer and user terminal.
3. System Performance Analyzer or Bus State Monitor, which monitors all the microprocessor
activity and traces each selected bus cycle of the target microprocessor.
4. Source Level Debug, used with a host computer system to provide unprecedented debugging capability at the source code level.
5. Cross Support Software, consisting of the assemblers, disassemblers, linkers, "C" compilers, and debuggers used for software development on different host computers.
6. Development System Host Computer, a mUlti-user, multi-tasking computer system running UNIX@) System V, that hosts the hardware control station and cross support software.
Motorola's approach to development systems is to be "host independent." The development
systems equipment uses the EIA RS-232-C asynchronous serial interface to connect the control
station and its emulator to the host computer system, as shown in Figure 11-1. The control station

HDS-300
CONTROL STATION

16-81T EMULATOR

32-81T EMULATOR

III

Figure 11.1 The Total Development System Solution
UNIX is a registered trademark of AT&T Bell Laboratories

M68000 FAMILY
REFERENCE

MOTOROLA
11-1

and emulator look like an ASCII asynchronous terminal to the host computer. For standalone
operation, an ASCII asynchronous terminal can be connected to the control station in place of
the host computer. With the host-independent approach, the user is free to use, as the host, any
computer system that can execute basic software development tools, like an assembler, and
download code to the emulatorlcontrol station via the asynchronous link.
The centerpiece of Motorola development systems is the HDS-300@) hardware control station.
The HDS-300 connects the emulator to the host computer to provide a universal debug capability
for all Motorola 16- and 32-bit microprocessors. The system performance analyzer plugs into the
HDS-300 to monitor 32-bit microprocessor activity by tracing the bus. The source level debug
software executes on the host computer and works with the HDS-300 and emulatorto give program
visibility in the target system at the source code leveL

11.1 HOST SYSTEMS
Microprocessor development is typically done with the aid of a host computer that is used to
develop software for the target microprocessor system. Software developed on the host computer
is downloaded through the HDS-300 via an asynchronous terminal interface on the host computer
connected to the HDS-300 host port. The HDS-300 looks like an ASCII terminal to the host computer.
Future enhancements will allow high-speed download via' a Centronics interface.
Motorola's cross development software has been ported to several host computer systems. The
microcomputer .designer can use either Motorola's M68DVLP, a VAX@) system, a Macintosh@)
computer, ora SUN-3@) workstation as the host.

11.1.1 M68DVLP Host Computer System
The MotorolaM68DVLP host computer system is a mUlti-user, multi-tasking development system
that supports cross software development for Motorola's M68000 Family of microprocessors and
serves as host for the HDS-300 and emulator. The M68DVLP runs the SYSTEM V/68@) Operating
System, the first AT&T-validated version of UNIX System V, and is based on the 32-bit MC68020
VME system built and serviced by Motorola. This system includes a 70-megabyte Winchester
disk, a 5.25 inch 655K byte floppy, a QIC-02 streaming tape, eight serial ports and 2 megabytes
of memory. The system includes cross development software consisting of 16- and 32-bit assemblers, linkers, C compilers, and source level debug (SLD) packages.
Motorola offers the M68DVLP host development system for software development and hosted
debug with the HDS-300 control station 'and emulator. Using the software control facilities of the
SYSTEM V/68 and Motorola's assemblers and compilers for cross software development, M68DVLP
support for a team of designers contributes to a well-coordinated development project.
The HDS-300 control station, with an appropriate emulator, can be used standalone or in the
hosted configuration to support microprocessor application studies without requiring a target
system. Using the emulator's memory, test code can be downloaded from a host computer and
benchmarks can be run. In this way, benchmarks that do not require interfacing to a target liD
device can be run and measured in the emulator.

III

HDS-300 is a trademark of Motorola Inc.
VAX is a trademark of Digital Equipment Corporation
Macintosh is a trademark of Apple Computer Inc.
SUN-3 is a trademark of Sun Microsystems, Inc.
SYSTEM V/68 is a trademark of Motorola Inc.

MOTOROLA

11-2

M68000 ,FAMILY

REFERENCE

Motorola's cross development software has been ported for other popular computer systems as
described previously.

11.1.2 VAX Host System
Digital Equipment Corporation's VAX system is a multi-user, multi-tasking minicomputer that can
serve as the host computer system. VMS@I, release 4.6 or later, is required.
11.1.3 Macintosh Host System
The Apple Macintosh is a single-user desktop system that runs the Apple Operating System. The
cross software runs on the Macintosh Plus, SE, and Macintosh II models with a minimum of 1
megabytes of memory and a hard disk (required to contain the volume of cross software). Apple
Operating System, release 5.0 or later, is required.

11.1.4 SUN-3 Host System
Another alternative host computer system is the SUN-3 workstation. The SUN-3is a single-user
multi-tasking networking workstation.

11.2 HDS-300 CONTROL STATION
The HDS-300 is the universal control station supporting all Motorola emulators for the M68000
Family: 16-bit MC68000, MC68HCOOO, MC68008, and MC68010; and 32-bit MC68020 and MC68030.
An HDS-300 consists of the control station and station software, which are connected to an
emulator via a four foot cable set. This configuration can operate standalone by simply attaching
an ASCII terminal to the asynchronous serial port of the HDS-300.
The powerful HDS-300 control station greatly simplifies the development task. There is no need
to memorize operating procedures, since a powerful HELP command in the HDS-300 can guide
inexperienced users through the most complex function sequences. An in-depth tutorial can be
called up instantly to provide an "on-line manual" for any function requested. Menus guide the
user through the options of an operation. The HDS-300 supports user-defined macros for various
operations; For example, a macro can save blocks of code or record complex repetitive tasks for
recall later with a single command. The HDS-300 provides easy-to-use "window" displays that
are user controlled, and show the status of a variety of activities simultaneously. The HDS-300 is
a universal control station for all the M68000 Family emulators. Using BNC connectors mounted
on the HDS-300, up to eight control stations, each with a different emulator, can be connected
for a single coordinated multi-processor debug session.
Because the HDS-300 control station and emulator replicates all functions of the target system
microprocessor in its application environment, it can operate in a non-invasive mode supporting
the traditional mechanisms for hardware and software debugging. This mode includes the fundamental capabilities of starting and stopping code execution in order to exercise the entire target
system, of examining and altering processor registers and system memory, and of stepping
through code by executing one instruction at a time.

III

VMS is a trademark of Digital Equipment Corporation

M68000 FAMILY

REFERENCE

MOTOROLA

11-3

The design features of the HDS-300 are:,
1. Supports all Motorola M68000 Family emulators
2. Macro utility, for user-defined macro sequences of commands
3. On-line HELP facility, to provide a quick reference, always available on the screen
4. Two asynchronous RS-232-C serial ports, one for host connection and one for local terminal
connection.
5. Built-in Centronics-compatible parallel printer port for hard copy of screen displays.
6. 5.25 inch floppy disk drive supports user-written macros, terminal configuration definition,
storage of downloaded code, and powerful multi-level HELP files.
7. External synchronization input/output, for operation with multiple control stations in multiprocessor development projects.
8. Power-up self-test, with more extensive diagnostics available on floppy disk.
11.2.1 Real-Time Bus Analysis
In-circuit emulation is supported by the bus state monitor (BSM), for the 16-bit microprocessors,
and by the system performance analyzer (SPA) for the MC68020. The BSM and SPA work much
like a standalone logic analyzer, but are integrated with the emulators and capture bus cycle data
via the emulator's in-circuit probe. Both the BSM and SPA can capture all bus cycles in a trace
buffer or selectively capture bus cycles as specified by the user. The user-specified qualifiers
decide which bus cycles are captured. Qualifiers may be combined for more complex triggers,
which may be sequenced for very sophisticated debugging of system software.
11.2.1.1 BUS STATE MONITOR. The BSM is integrated into the HDS-300 and is used with the
emulators for the MC68000, MC68HCOOO, MC68008, and MC68010 microprocessors. The capabilities of theBSM provide:
1. Capture of microprocessor bus cycles
2. Selection of specific bus cycles by user-selected qualifiers
3. Display of the bus cycles captured in the trace buffer
4. Reverse assembly of the microprocessor instructions
5. Performance analysis of the most/least heavily executed program code
The BSM offers two bus cycle recording modes. In one mode, all bus cycle data is recorded
continuously from initiation of emulated execution until execution is stopped manually or by a
breakpoint. In the other mode, the BSM is triggered by a pre-defined event and continues for a
specified number of occurrences of that event or for a specified number of bus cycles after being
triggered.
A trigger event is a collective logical state ofthe emulated microprocessor's data, address, control,
and other lines used during emulation for starting or stopping the acquisition of data representing
bus cycle activity. Hence, an event is defined by specifying the logical level of particular data and
address lines to be used for triggering. An additional cable is provided so eight additional lines
may be connected to points of interest in the target system. The logical states of these points as
well as an external signal can be included in 'the trace and in the trigger event. The BSM provides
an external trigger event signal for use by external equipment. The BSM can also trigger the
emulator to halt emulation, which provides an additional hardware breakpoint.

III

The trace buffer can record 1024 selected bus cycles. Display of the buffer may be modified to
show disassembled instructions, hexadecimal dump, or a combination. Filter patterns may be
used to search through the buffer data.

MOTOROLA
11-4

M68000 FAMILY

REFERENCE

Histograms are used to display relative activity for address ranges with up to 16 user,-selected
sub-divisions. The 8SM captures data in the trace buffer and optionally can halt the emulator
each time the 8SM records the selected bus cycle. Alternatively, the 8SM is allowed to continue
to process the recorded bus cycles non-invasively as the test program continues execution.
11.2.1.2 SYSTEM PERFORMANCE ANALYZER. The SPA is an option of the HDS-300 used with
the MC68020 emulator. The capabilities of the SPA are similar to the 8SM with enhanced definition
of the bus event used as a trigger and enhanced recording of bus cycle data.
For event definition, 112 address, data, and control signals, and eight user-option input signals
are available. An additional 32 bits in the trace buffer are used to time tag the collected data.
Address, data, and control signals of the MC68020 or MC68030 are used to define simple events.
These inputs, in combination with an external trigger, a timer value, and up to three hardware
breakpoints, are used to define complex events. Simple and complex events can be combined
for even more precise event definition to more accurately analyze the target activity. The SPA
also allows dynamic control over the emulator's hardware breakpoints and definition of breakpoint
events.
The SPA trace buffer is 144 bits wide and 4096 events deep. The 4096 events can be divided into
as many as 16 separate blocks. For each block, a unique event can be defined to trigger data
capture, and any detected occurrence of the event from the first to the 256th can be selected as
the recording trigger. Finally, events can be enabled dynamically under program control, including
the control of the first three hardware breakpoints.
The SPA can be used with the MC68030, but the synchronous bus and burst mode can sequence
faster than the SPA. In such cases, the SPA can miss some bus cycles of the MC68030.
11.2.2' User Interface
The HDS-300 design employs "fill in the blanks" screen layouts and provides several helpful
utilities to simplify the use of its many capabilities. The various capabilities of related HDS-300
commands are grouped according to major function into "operating environments" each of which
displays a unique screen used to enter commands. The screens are organized as templates that
plainly indicate what information is required and where it is to be entered. A scroll region is used
by HDS-300 to displayregister values, bus analysis histograms, or other results of command
execution. The scroll region is also used by the HELP utility.
Several capabilities extremely useful for hardware development are provided by the macro utility.
The macro utility offers a full screen text editing capability as a means of creating macros from
sequences of commands, a macro library buffer in memory, and support of floppy files for creating
,and invoking macros. Macro capabilities are often used for automatic initialization and setup at
powerup and for the recording and re-execution of a sequence of commands. The macro editor
is used for creating named macros and saving them in the macro library.
11.2.3 HDS-300 as a Test Tool
While the power of a debug tool as sophisticated as the HDS-300 is obviously well applied in the
microprocessor design activity, it likewise applies effectively in the production test and service/
repair activities. Here, the floppy drive is very important to hold production' final tests, more
narrow system/board diagnostics, and all software downloaded to floppy for use in the target

M68000 FAMILY

Rf:FERENCE

MOTOROLA
11-5

III

test phases. Also, the Macro utility is invaluable to sequence the diagnostic tests and interact with
the diagnostician. Macros can: .,
1. Start and stop test execution
2. Accept commands and directives from the diagnostician
3. Execute commands and directives and display requested information
4. Call and execute other macros when a breakpoint is encountered
5. Copy all data sent to the screen on a printer for a paper trail
6. Restart test code
'
7. Display understandable, self~explanatory error messages as well as provide extensive help
info~mation for, the diagnostician' '
11.3 IN-CIRCUIT EMULATION

In-circuit emulation allows the microprocessor chip to be lifted from the target system and the
emulator to be plugged directly into the same socket, which provides the proper electrical connections to duplicate the normal microprocessor functions in the target system. With real-time
in-circuit emulation, hardware and software debug is supported by the standard emulator techniques including breakpoints, single-cycle instruction execution, tracing bus cycles, and substitution by emulator memory and certain emulator control signals for those nonfunctioning elements
of the target system;
Emulation memory is used as a substitute for the target memory. The HDS-300 remaps emulation
memory to exactly reflect the target memory map. In support of ROM applications, emulation
memory provides a means to detect unwanted writes to target memory as well as writes to blocks
of emulation memory that are write protected.
The HDS-300 provides 32K bytes of emulation memory for the 16-bit emulators. This is expandable
to 64K, 128K, or 256K bytes. The MC68020 and MC68030 emulators carry emulation memory
within the emulator enclosure; memory configurations are 64K minimum, with' 256K- and 1Mbyte configurations availab!e.
11.3.1 ,16-Bit Emulators: MC68000,MC68HCOOO, MC68008, MC68010

III

The general features of the '16-bit emulators include:
1: Real-time emulation to 12.5 MHz
2. Probes available for dual-in-line, PGA, and PLCC package types
3. Zero wait states to 10 MHz; one wait state at 12.5 MHz
a. When operating inemulatioh 'memory'
b. Target memory may meet zero wait states at 12.5 MHz
4. Sixteen software breakpoints can be assigned to any four blocks of 4K bytes'each anywhere
in memory
,
5. 32K bytes of emulation memory is standard
a. Expandable to 68K, 128K, or 256K bytes'
b. Mapped as substitute memory in 4K-byte blocks anywhere in 16M-byte address space
6. Built-in bus state monitor with analysis
a. 63-bit wide trace buffer is 1024 entries deep
b.. Works like a "sliding window" ,
'.
,
c. Tracing controlled by user-defined qualifiers, which can also control the emulator and
be used with an external trigger
"
"
'
'
d. Analysis highlights code bottlenecks via histograms and instruction disassembly is
supported
'

MOTOROLA
11-6

M68000 FAMILY

REFERENCE

'11.3.2 32-Bit Emulator: MC68020
The general features of the MC68020 emulator include:
1. Real-time emulation to 25 MHz
2. Zero wait states to 20 MHz; one wait state maximum at 25 MHz when using emulation
memory; target memory may meet zero wait states at 25 MHz
3. 64K standard emulation memory, with 256K and 1M bytes available
a. First 256K is high-speed memory with zero wait states to 20 MHz (synchronous and
asynchronous) and one wait state above 20 MHz (asynchronous only)
b. Additional emulation memory has 1 wait state
c. Selectable, with 8-/16-/32-bit port sizes, write protection; up to seven wait states
4. Three hardware breakpoints and 64 software breakpoints
5. Optional system performance analysis
a. 144-bit wide trace buffer is 4000 entries deep
b. Works like a "sliding window"
c. Tracing controlled by user-defined qualifiers, which can also control the emulator and
be used with an external trigger
d. Instruction disassembly supported .
The following table lists the part numbers for MC68020 emulator configurations by speed and
memory size.
Maximum Speed

64K Bytes

256K Bytes

1M Bytes

16 MHz
25 MHz

M68020HM3C-1
M68020HM3C-4

M68020HM3C-2
M68020HM3C-5

M68020HM3C-3
M68020HM3C-6

11.3.3 32-Bit Emulator: MC68030
The general features of the MC68030 emulator include:
1. Real-time emulation to 25 MHz
2. Emulation memory with zero wait states to 20 MHz (synchronous and asynchronous);
target memory access may see one wait state maximum (ynchronous and asynchronous)
3. 64K standard emulation memory, with 256K, and 1M bytes available
a. First 256K is high-speed memory with zero wait state to 20 MHz (synchronous and
asynchronous) and one wait state above 20 MHz (asynchronous only)
b. Additional emulation memory has one wait s t a t e '
,
c. Selectable, with 8-/16-/32-bit port sizes, write-rrotection, up to seven wait states
4. Three hardware breakpoints and 64 software breakpoints.
5. Power-up self test, with sophisticated diagnostic set included on floppy disk
The following table lists the part numbers for MC68030 emulator configurations by speed and
memory size.
Maximum Speed

64K Bytes

256K Bytes

1M Bytes

25 MHz

M68030HM3C-4

M68030HM3C-5

M68030HM3C-6

M68000 FAMILY

REFERENCE

III
MOTOROLA

11-7

Details of MC68030 emulator operation are listed under the following five headings.
Target Memory Access:
1. User application can make use of full 4G-byte address space
2. Maximum of one wait cycle required when accessing target memory (both asynchronous
and synchronous)
3. Target (and emulation) memory can be displayed, modified, dumped, loaded, filled,
searched, and tested
4. Emulator supports all address spaces
5. Emulator supports dynamic bus sizing (byte, word, and long)
6. Emulator supports three data widths (byte, word, and long) independent of bus width
Emulation Memory Access:
1. First 256K bytes can be used for synchronous emulation memory and supports burst mode
with zero wait states up to 20 MHz
2. Emulation memory can be mapped anywhere in the 4G-byte address space
3. Emulation memory can be mapped in 4K-byte blocks
4. All emulation memory must be in the same 16M-byte sector
5. Up to seven wait states can be inserted for each block of asynchronous emulation memory
6. User-selectable bus sizes for each block of emulation memory
7. Four primary address spaces supported: user/supervisor program/data
8. Each block can be write protected
Signal Support:
1. To overcome delays from the target to the emulator, the emulator can provide the STERM,
CIIN, and CBACK, signals
2. These signals are independent of the mapping of synchronous emulation memory
3. Up to two wait states can be inserted for synchronous signals supplied by the emulator
Execution Control:
1. Single-step mode is available
2. Three hardware breakpoints are available
3. Hardware breakpoints do not alter target memory
4. Hardware breakpoints may be enabled/disabled with caches enabled or disabled
5. Hardware breakpoint event counter counts up to 64K events
6. Hardware breakpoints can be used as triggers by the SPA
7. Up to 64 software breakpoints can be used
8. Breakpoints can be specific to user or supervisor space
Processor Signals:

III

Signals that can be enabled or disabled:
DSACKx
BERR
BR
ClOUT
CBREQ
STERM
AVEC
Interrupts

MOTOROLA
11-8

M68000 FAMILY

REFERENCE

Signals that are displayed by the emulator:
Target Power
BR
Target Clock Stopped
Bus Timeout
Double-Bus Fault Condition

Bus Error
BGACK
Interrupt Line Status
HALT
RESET

Signals that can be substituted by the emulator:

BEAR

CDIS

DSACKx
CBREQ

CTIJOT
MMUDIS

ClK
Signals that can be substituted by the emulator based on selected address ranges:
STERM
CBACK
CIIN

11.4 DEVELOPMENT SOFTWARE

Usually a host computer system is used for software program development, editing, assembling,
compiling, linking, and downloading .to the HDS-300. The HDS-300 supports Motorola S record
and UNIX "coft" download formats.
The 5.25 inch floppy disk drive can be used to save the downloaded code and to store macros
written by the user for the target under development. Downloaded code may be patched using
the HDS-300 reverse assembler and line-by-line assembler, then saved on the floppy disk as
testing continues. Code can be quickly reloaded into the emulator from the floppy disk when
software and hardware bugs cause target errors.

11.4.1 Source-Level Debug

The SLD works with Motorola's well-known C high-level language compiler to permit debug at
the C statement level rather than at the assembly or hexadecimal levels. Debugging at this level
provides breakpoints at the statement level and displays of program variables by name and typed
value. The host-resident SLD works with the HDS-300 control station to provide a powerful, yet
easy-to-use debugging tool that takes advantage of all the advanced capabilities of the HDS-300.
This versatile debugging tool allows the user to view and manipulate the target system via source
language when programming in assembler or in C and downloading code in the UNIX "coft"
format. Single lines may be stepped through, breakpoints set, and variables displayed and set,
using the program source code rather than hexadecimal memory representations. Positions within
the source code (such as those required for setting breakpoints or moving the browse cursor)
can be referred to by line number or address or by a line number within a named function or
source module.
Cursor movement, windowing, and other capabilities are provided. Windowing provides continuous source context display as code is executed. High-level mode windowing displays source
while mixed mode windowing displays both source and the corresponding assembler level code.

M68000 FAMILY

REFERENCE

MOTOROLA
11-9

Within the source window, two cursors may be displayed: an execution,cursor that indicates the
next source line to be executed and a browse cursor that may be positioned on any line in any
text file for which the user has host operating system -read-access permission.
SLD provides two additional windows. The variable window displays the current values of one
or more user-specified variables at selected times as a check on the state of the program being
debugged. The command log window displays the results obtained from executing the most
recently entered commands.

11.4.2 Cross-Support Software

The system includes cross-development software consisting of 16- and 32-bit assemblers, linkers,
C compilers, and SLD packages.
'
Cross-support software allows development of software and hardware in parallel. Software can
be developed on a host, such as the M68DVLP system or an existing microcomputer, without
having to wait for the microcomputer under development to be operational. Only the final testing
and verification of the software needs to be done on the completed hardware.
All the cross-development software has been ported to several host computer systems. The'
microcomputer designer can use either Motorola's M68DVLP, a VAX system, a Macintosh computer, or a SUN-3 workstation as the host.

11.5 PART NUMBERS
SOFTWARE DEVELOPMENT HOST
Part Number
M68DVLP
M68DVLP2

Description
Multi-User UNIX Host System Including ALL 8-/16-/32-8it Languages, SLD, and Tools
220V Version of M68DVLP

HARDWARE/SOFTWAREDEVELOPMENT STATION
Part Number
M68HDS300
M68HDS302

Description
HDS-300 Control Station
220V Version of HDS-300 Control Station

16-BIT EMULATOR MODULES
Part Number

M68000HM3A
M68000HM38
M68000HM3C
M68008HM3A
M68008HM38
M68010HM3A
M68010HM38
M68010HM3C

MOTOROLA
11-10

Description
MC68000
MC68000
MC68000
MC68008
MC68008
MC68010
MC68010
MC68010

Emulator and
Emulator and
Emulator and
Emulator and
Emulator and
Emulator and
Emulator and
Emulator and

8SM
8SM
8SM
8SM
8SM
8SM
8SM
8SM

with
with
with
with
with
with
with
with

DIP Cable for HDS-300
PLCC Cable for HDS-300
PGA Cable for HDS-300
DIP Cable for HDS-300
PLCC Cable for HDS-300
DIP Capbe for HDS-300
PLCC Cable for HDS-300
PGA Cable for HDS-300

M68000 FAMILY

REFERENCE

32-BIT EMULATOR MODULES
Part Number
M6S020HM3C-1
M6S020HM3C-2
M6S020HM3C-3
M6S020HM3C-4
M6S020HM3C-5
M6S020HM3C-6
M6S030HM3C-4
M6S030HM3C-5
M6S030HM3C-6

Description
MC6S020
MC6S020
MC6S020
MC6S020
MC6S020
MC6S020
MC6S030
MC6S030
MC6S030

Emulator
Emulator
Emulator
Emulator
Emulator
Emulator
Emulator
Emulator
Emulator

with
with
with
with
with
with
with
with
with

64K RAM and PGA Cable for HDS-300 (16 MHz)
256K RAM and PGA Cable for HDS-300 (16 MHz)
1M RAM and PGA Cable for HDS-300 (16 MHz)
64K RAM and PGA Cable for HDS-300 (25 MHz)
256K RAM and PGA Cable for HDS-300 (25 MHz)
1M RAM and PGA Cable for HDS-300 (25 MHz)
64K RAM and PGA Cable for HDS-300 (25 MHz)
256K RAM and PGA Cable for HDS-300 (25 MHz)
1M RAM and PGA Cable for HDS-300 (25 MHz)

SYSTEM PERFORMANCE ANALYZER
Part Number
M6SHDS300SPA

Description
System Performance Analyzer for 32-Bit Emulation

MEMORY EXPANSION
Part Number
M6SHDS3EMM1
M6SHDS3EMM2
M6SHDS3EMM3
M6SHDS3FDKT

Description
64K Emulation Memory Expansion for HDS-300; MC6S000/MC6S00S/MC6S010
12SK Emulation Memory Expansion for HDS-300; MC6S000/MC6S00S/MC6S010
256K Emulation Memory Expansion for HDS-300; MC6S000/MC6S00S/MC6S010
HDS-300 Second Floppy Drive Kit

CABLES/HARDWARE
Part Number
M6S000/10DIPT
M6S000/10PCCT
M6S000/10PGAT
M6S00SDIPT
M6S00SPCCT

Description
MC6S000/MC6S010 DIP Cable Probe for HDS-300
MC6S000/MC6S010 PLCC Cable Probe for HDS-300
MC6S000/MC6S010 PGA Cable Probe for HDS-300
MC6S00S DIP Cable Probe for HDS-300
MC6S00S PLCC Cable Probe for HDS-300

CROSS SOFTWARE
Part Number
M6SKTUTOR-D4
M6SKTUTORS

Description
Tutor@' Source Listing, Rev. 1.3
Tutor Source Code for MEX6SKECB or VERSAdos@ S-Inch Diskette

APPLE MACINTOSH CROSS SOFTWARE
Part Number
M6SHGBASM2
M6SJGBCC2A
M6SHGBSLDOO
M6SJGBSLD10
M6SJGBSLD20
M6SJGBSLD30

Description
M6S000 Family Macro Assembler/Linker for Apple Macintosh, 3.5 Inch Diskette
MC6S020/MC6S030 Cross C Compiler/Linker for Apple Macintosh, 3.5 Inch Diskette, 1-2 Users
MC6S000/MC6S00S Source Level Debug for HDS-300 and Apple Macintosh, 3.5 Inch Diskette
MC6S010 Source Level Debug'for HDS-300 and Apple Macintosh, 3.5 Inch Diskette
MC6S020 Source Level Debug for HDS-300 and Apple Macintosh, 3.5 Inch Diskette
MC6S030 Source Level Debug for HDS-300 and Apple Macintosh, 3.5 Inch Diskette

III

Tutor is a trademark of Motorola Inc.
VERSAdos is a trademark of Motorola Inc.

M68000 FAMILY

REFERENCE

MOTOROLA
11-11

M68DVLP CROSS SOFTWARE
Part Number

Description

M6SN2XBASM
M6SN2QSASM
M6SN2XSASM
M6SNXBASM2
M6SNNXBPASMLK
M6SNNXSPASMLK

MC6S020 Macro Assembler for M6SDVLP,2, Object Code on 5.25 Inch Diskette
MC6S020 Macro Assembler for M6SDVLP,2, Source Code on Mag Tape
MC6S020 Macro Assembler for M6SDVLP,2, Source Code on 5.25 Inch Diskette
M6S000 Family Macro Assembler/Linker for M6SDVLP,2, Object Code, 5.25 Inch Diskette
PAL Port Assembler/Linker for M6SDVLP,2, on 5.25 Inch Diskette
PAL Port Assembler/Linker Source Code for M6SDVLP,2, on 5.25 Inch Diskette

M6SN2XBCC
M6SNNXBCC20B
M6SNNXBCC20C
M6SNNXSCC20-2

MC6S000/MC6S00S/MC6S010 C Compiler/Assembler/Linker for SYSTEM V/6S, 1-S Users
MC6S020 C Compiler/Assembler/Linker on 5.25 Inch Diskette,1-S Users
MC6S020 C Compiler/Assembler/Linker on 5.25 Inch Diskette, 1-6 Users
MC68020 C Compiler/Assembler/Linker, Source on 5.25 Inch Diskette

M6SBNQBCC20C
M68BNQBCC20D
M6SBNQBCC20E
M6SBNQBCC20F
M6SBNQSCC20-2
M6SBNQSOPT
M6SNXBCC2A
M6SNXBCC2B

MC6S020 C Compiler/Assembly/Linker on Mag Tape, 1-16 Users
MC6S020 C Compiler/Assembler/Linker on Mag Tape, 1-32 Users
MC68020 C Compiler/Assembler/Linker on Mag Tape, 1-64 Users
MC6S020 C Compiler/Assembler/Linker on Mag Tape, >64 Users
MC6S020 C Compiler/Assembler/Linker Source Code on Mag Tape
Hi-Level C Optimizer, Source on Mag Tape
MC6S020/MC68030 C Compiler/Assembler/Linker on 5.25 Inch Diskette, 1-2 Users
MC68020/MC6S030 C Compiler/Assembler/Linker on 5.25 Inch Diskette, >2 Users

M6SNNXBSLDOO
M68NNXBSLD20
M68NXBSLD30

M6S000/MC6S00S/MC6S010 Source Level Debug for HDS-300 and M68DVLP,2
M6S020 Source Level Debug for HDS-300 and M6SDVLP,2
MC6S030 Source Level Debug for HDS-300 and M6SDVLP,2, 5.25 Inch Diskette

M6SNNXBTLKT
M6SNNXSTLKT

VERSAdos Tool Kit, SYSTEM V/6S, on 5.25 Inch Diskette
VERSAdos Tool Kit, SYSTEM V/6S, Source on 5.25 Inch Diskette

VAX VMS CROSS SOFTWARE
Part Number

Description

M68DOBASM2
M6SDOBCC2A
M6SDOBCC2B
M6SDOBSLDOO
M6SDOBSLD10
M6SDOBSLD20
M6SDOBSLD30

M6S000 Macro Assembler/Linker for VAX VMS, 600 Foot 9-Track Tape
MC6S020/MC6S030 C Compiler/Linker for VAX VMS, 1-2 Users, 600 Foot 9-Track Tape
MC6S020/MC6S030 C Compiler/Linker for VAX VMS, >2 Users, 600 Foot 9-Track Tape
MC6S000/MC6S00S Source Level Debug for HDS-300 and VAX VMS, 600 Foot 9-Track Tape
MC68010 Source Level Debug for HDS-300 and VAX VMS, 600 Foot 9-Track Tape
MC68020 Source Level Debug for HDS-300 and VAX VMS, 600 Foot 9-Track Tape
MC68030 Source Level Debug for HDS-300 and VAX VMS, 600 Foot 9-Track Tape

M6SDHBASM2
M6SDHBCC2A
M6SDHBCC2B
M6SDHBSLDOO
M6SDHBSLD10
M68DHBSLD20
M6SDHBSLD30

M6S000 Macro Assembler/Linker for VAX VMS, TK50 Tape
MC6S020/MC6S030 Cross C Compiler/Linker for VAX VMS, 1-2 Users, TK50 Tape
MC6S020/MC6S030 Cross C Compiler/Linker for VAX VMS, >2 Users, TK50 Tape
MC6S000/MC6S00S Source Level Debug for HDS-300 and VAX VMS, TK50 Tape
MC6S010 Source Level Debug for HDS~300 and VAX VMS, TK50 Tape
MC6S020 Source Level Debug for HDS-300 and VAX VMS, TK50 Tape
MC6S030 Source Level Debug for HDS-300 and VAX VMS, TK50 Tape

M6SDOSASM2
M6SDOSCC2
M6SDOSSLDOO
M6SDOSSLD10
M6SDOSSLD20
M68DOSSLD30

M68000 Family Macro Assembler/Linker for VAX VMS, 600 Foot 9-Track Tape, Source Code
MC6S020/MC6S030 Cross C Compiler/Linker for VAX VMS, 600 Foot 9-Tack Tape, Source Code
MC6S000/MC6S00S Source Level Debug for VAX VMS, 600 Foot 9-Track Tape, Source Code
MC6S010 Source Level Debug for VAX VMS, 600 Foot 9-Track Tape, Source Code
MC6S020 Source Level Debug for VAX VMS, 600 Foot 9-Track Tape, Source Code
MC68030 Source Level Debug for VAX VMS; 600 Foot 9-TrackTape, Source Code

M68DHSASM2
M6SDHSCC2
M6SDHSSLDOO
M6SDHSSLD10
M6SDHSSLD20
M68DHSSLD30

M6S000 Family Macro Assembler/Linker for VAX VMS, TK50 Tape, Source Code
MC6S020/MC6S030 Cross C Compiler/Linker for VAX VMS, TK50 Tape, Source Code
MC6S000/MC6S00S Source Level Debug for VAX VMS, TK50 Tape, Source Code
MC6S010 Source Level Debug for VAX VMS, TK50 Tape, Source Code
MC6S020 Source Level Debug for VAX VMS, TK50 Tape, Source Code
MC6S030 Source Level Debug for VAX VMS, TK50 Tape, Source Code

III
MOTOROLA
11-12

. M68000 FAMILY

REFERENCE

MPU SOFTWARE SUPPORT
Part Number
MC68KTBFA

Description
Token Bus Frame Analyzer

EVALUATION MODULES
Part Number
MEX68KECB

Description
MC68000 Educational Computer Board (includes Tutor 8IW in ROM)

III
M68000 FAMILY

REFERENCE

MOTOROLA
11-13

-~~"~~~"""""""""""""""""""""""-:M:6~80~O~O;F~A~MIL~V:-'"
:

MOTOROLA
11-14

REFERENCE

MOTOROLA'S M68000 FAMILY
SELECTOR GUIDE
PROCESSORS
COPROCESSORS
DMA CONTROLLERS
DATA COMMUNICATION DEVICES
NETWORK DEVICES
GENERAL-PURPOSE PERIPHERAL DEVICES
MECHANICAL DATA

TECHNICAL SUPPORT.
DEVELOPMENT SYSTEMS

III

MOTOROLA'S 'M68000 FAMILY
SELECTOR'GUIDE
PROCESSORS
COPROCESSORS
DMA CONTROLLERS
DATA· COMMUNICATION DEVICES
NETWORK'DEVICES
GENERAL-PURPOSE: PERIPHERAL DEVICES
MECHANICAL:DATA
•

TECHNICAL·SUPPORT

III DEVELOPMENT SYSTEMS

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EXIF Metadata provided by EXIF.tools

M68000_Family_Reference_1988 M68000 Family Reference 1988

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