MC14500B_Industrial_Control_Unit_Handbook_1977 MC14500B Industrial Control Unit Handbook 1977

User Manual: MC14500B_Industrial_Control_Unit_Handbook_1977

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MC14500B
INDUSTRIAL CONTROL UNIT
HANDBOOK.

Authors
VemGregory
Brian DeUaRde

Principal Contribntors
Ray DiSilvestro
Terry Malarkey
Phil Smith
Mike Hadley

MOTOROI.A Senriconducf:or Producf:s Inc_

PREFACE
A large number of the problems found in controlling electronic and
electromechanical devices involve decision oriented tasks. In addition,
these decisions usually result in commands as simple as turning something on or off. Some examples are: Is the limit switch closed? Has the
timer interval ended? Turn 011 pump PI7 when relays A, B, and Care
closed. Send 20 pulses to the triac. Turn on the TlO: light. Count 60
pulses and start motor M I, and an infinity of like jobs.
There are, of course, many ways to solve these types of problems.
Originally, conceptually simple and easily maintained relays were used
extensively. However, relays are bulky, expensive, consume a great deal
ofpower, suffer in terms of long range reliability and also from the fact
that they do not lend themselves easily to system changes.
Next came solid state logic. These devices are quite small, have
become extremely inexpensive, consume afraction ofthe power ofa relay
and have tremendous long term reliability while remaining conceptually
simple and easily maintainable. However, they still suffer from the fact
that, once in the system, they are not easily programmable and system
changes cannot be made quickly and inexpensively.
Computers alld microcomputers may also be used, but they telld to
overcomplicate the task and often require highly trained personnel to
develop and maintain the system.
A simpler device, designed to operate on inputs and outputs one-at-atime and configured to resemble a relay system, was introduced. These
devices became known to the controls industry as Programmable Logic
Controllers (PLC).
The Motorola MCI4500B Industrial Control Unit (ICU) is the
monolithic embodiment of the PLC's central architecture. Some of the
features of the Motorola MC14500B ICU are:
• 16 instructions.
• Easily programmed, uncomplicated, no fear of the urifamiliar.
• Easily learned, can be maintained by existing personnel.
• Uses external memory for versatile system design.
• Can be uniquely tailored to a user's particular requirements.
• Readily expandable to any size and complexity.
• Offers the advantages of programmability.
• B series CMOS lEDEC specification
• High noise immunity.
• Low quiescent current.

• 3-18 volt operation.
• Static operation.
• Wide range of clockfrequencies, typical I MHz operation @ VDD
= 5V with I instruction/clock period.
• instruction inputs-TTL compatible.
• Outperforms microprocessors for decision oriented tasks.
• Wide range of opplications, from relay ladder logic processing, to
moderate speed serial data manipulations, to the unloading of
overtaxed microprocessor based systems.
This handbook serves as a design and application manual/or the part.

Table of Contents
Prerace ........................................................... .i
CHAPTER 1 - Introduction ...................... , . . . . . . . . . . . . . . .. 1
CHAPTER 2 - Basic Concepts ................................... , 9
CHAPTER 3 -

Basic Programming and Instruction Set .............. 15

CHAPTER 4 - Hardware Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25
CHAPTER 5 - Demonstration System ............................. 31
CHAPTER 6 - Timing, Signal Conditioning and 110 Circuits ......... 41
CHAPTER 7 - OEN and the IF-THEN Structure ................... 55
CHAPTER 8 - IF-THEN-ELSE Structure .......................... 59
CHAPTER 9 -

While Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 63

CHAPTER 10 - Complete EnabUng Structures. . . . . . . . . . . . . . . . . . . . .. 67
CHAPTER 11- Traffic Intersection Controller ...................... 75
CHAPTER 12 - Adding Jumps, Conditional Brancbing and Subroutines 87
CHAPTER 13 -

Modularizing Hardware Systems .................... 91

CHAPTER 14 - Arithmetic ROlitines ............................... 97
CHAPTER 15 - Translating to ICU Code ........................... tot
APPENDIX A -

MCI4599B Addressable Latch ...................... 105

iii

CHAYfER 1 INTRODUCTION
The Motorola MC14500B is a single chip, one-bit static CMOS processor optimized
for decision-oriented tasks. The processor is housed jn a 16-pin package and features
16-four-bit instructions. Tht! instructions perform logical operations on data appearing on a
one-bit bidirectional data line and data in a one-bit accumulating Result Register within the
lCU. All operations are performed at the bit level.
.
The ICU is timed by a single phase clock signal, generated by an internal oscillator that
uses one external resistor. Alternatively, the clock signal may be controlled by an external
oscillator. In either case, the clock signal is available for synchronization with other
systems. Each of the ICU's instructions execute in a single clock period. The clock
frequency may be varied over a wide range. At a clock frequency of 1 MHz, some 8300,
plus, instructions, may be executed in a 60 Hz power line half cycle.
In a system, the ICU may be used in conjunction with the complete line of over 100
standard B-series CMOS logic devices. This allows tailoring a system to an application, and
allows a judicious mix of customized hardware and software to be achieved.
As an initial example, Figure 1.1 shows a block diagram of a minimal ICU system
with four component blocks in addition to the ICU. The blocks are:
•
The lCU, or central controller of the system.
•
The memory, either permanent Read Only Memory (ROM) or temporary Random
Access Memory (RAM). Here, the steps of the program are stored, both individual
instructions and addresses of inputs and outputs.

Figur. 1.1 Basic ICU System

•
•

The program counter, used to step the machine through the sequence of instructions.
Inputs and outputs, each individually selected by the machine, from information
contained in the memory.
Note that this system can be expanded almost without bound, in terms of inputs and outputs,
so long as the memory is sufficiently wide to address the I/O structure.
There are functions for which one bit machines are poorly suited. These functions are
complex calculations or parallel word data processing. When there are many calculations, a
one-bit machine is at a disadvantage. When a job is dominated by calculations or data
logging,. a multi-bit processor is appropriate. When the task is decision and command
oriented, a one-bit machine is an excellent choice. The tasks that are mixed between
decisions and calculations will be decided upon by economics, the designer's familiarity
with alternatives, and how comfortable the designer is with the alternatives. Under some
circumstances, a combination of an MC6800 MPU and an MC14500B ICU may be the best
solution.
A functional diagram of the MC14500B is shown in Figure 1.2. Central to the ICU is
the Result Register, (RR), a one-bit accumulator that stores the results of Boolean manipulations. These results are generated in the Logic Unit, (LU), which has as its inputs, signals
from external data and the RR. Instructions are presented to the chip on the 4 instruction
pins, (10, 11, 12, 13), and are latched into the Instruction Register, (IR), on the negativegoing edge of Xl.

Ar-@JMP
A~ATN

ArB

FLGO

A~FLGF

RST~

Figure 12 MCI4500B Block Diagram

The instructions, listed in Figure 1.3, are decoded in the Control Logic (CTL), sending
the appropriate logic commands to the LU. Further decoding is also perfonned in the CTL to
send a number of output flags (JMP, RTN, FLGO, FLOF) to pins 9 through 12. These are
used as external control signals and remain active for a full clock period after the negativegoing edge of Xl.
I nstruction Code

#0
#1

#2
#3
#4
#5
#6
#7
#8
#8
#A
#B
#C
#0
#E
#F

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
lOll
1100
1101
1110
1111

Mnemonic

Action

NOPO
lO
lOC
AND
ANDC
OR
ORC
XNOR
STO
STOC
lEN
OEN
JMP
RTN
SKZ
NOPF

No change in registers. R ~ R. FlGO +- S1..
Load Result Reg. Data -+ RR
Load Complement Data -+- RR

logical AND. RR • 0 ..... RR
logical AND Compl.RR· 0 ..... RR
logical OR. RR + 0'" RR
logical OR Compl. RR +0'" RR
Exclusive NOR. If RR = 0, RR +-1
Store. RR -+ Data Pin, Write +-1
Store Compl. RR -+ Data Pin, Write +-1

Input Enable. 0 -+IEN Reg.
Output Enable. 0'" OEN Reg.
Jump. JMP Flag <- .n..
Return. RTN Flag +-Jl.. Skip next Inst.
Skip next instruction if RR = 0

No change in Registers RR -+RR, FlGF +-Jl.

Figur. 1.3 MCI4500B Instruction Set

The timing signals are generated from an on-chip oscillator, (OSC), with the operating
frequency set via an external resistor connected between pins 13 and 14. Figure 1.4 shows
the relationship between frequency and resistor values. The resultant square wave output
appearing at pin 14 is used both within the leu and as a general system clock. Alternatively,
the system may be externally clocked at pin 13.

IOkLLLWIO~k~ll~-L-L~LUI~OO~k~ll-L~-L~~UIM~ll~-L~~

Rc. CLOCK FREQUENCY RESISTOR

Figure lA Typical Cloek Frequency Versus Resistor (RC)

Two internal latches, Input Enable Register, (mN), and Output Enable Register,
(OEN), control data transfers to and from the ICU. The mN acts to enable the data path to
the LU when in the high state. The OEN, in the high state, enables the Write signal. It
should be noted that both of these registers are set via the Data pin.

RST

V DD

RR
XI

Write

Data
13

JMP

RTN

FLGO

VSS

FLGF

Figure 1.5 Pin Assignment

A Master Reset pin (RSl), active high, is provided to clear all registers and hold the
FLAG signals within the lCU at zero. The oscillator pin (Xl) is held in the high state when
RST is high. When RST goes low, the oscillator starts after a delay. In addition, the state of
RR is available at the buffered RR pin 15.
The ICU chip is housed in a 16-pin dual-in-line package, available in either plastic or
ceramic. The various temperature ranges and package types are as follows:
MC145OOBAL: Ceramic package; MIL temperature range
MC145OOBCL: Ceramic package, Commercial temperature range
MC145OOBCP: Plastic package, Commercial temperature range
Pin assignments are shown in Figure 1.5.
The maximum ratings and the electrical characteristics of the ICU are shown in Figure
1.6. These characteristics conform to JEDEC B-Series specifications governing CMOSB-Series devices which have a recommended supply voltage operating range from 5 to 15
Vdc. In electrically noisy industrial environments, supply voltages of 15 Vdc are recommended to make best use of the excellent noise immunity characteristics of CMOS logic. In
addition to being able to work in conjunction with over 100 B-series devices, the ICU also
works with non-B-series CMOS parts. Refer to Motorola Semiconductor Data Library,
CMOS Volume 5/Series B, for further information regarding the many devices that are
compatible with the lCU.
The switching characteristics and explanatory waveforms are shown in Figures 1.7 and
1.8, respectively. All times are related to the pin 14 clock signal, Xl. At this printing, only
specifications for typical times, at VDD = 10 Vdc, were available. Refer to the MC14500B
data sheet for up-to-date specifications.
4

ELECTRICAL CHARACTERISTICS

Symbol

Characteristic

Output Voltage ;
Vin

Von drO

Vln

OorVDD

"0" level

"0" Level

VIL

"1" Level

VIH

1.0 or 9.0 Vde)

Input Voltage

"0" Level

VIL

"1" Level

VIH

10. II, 12, 13
(Va c 9.0 or 1.0 Vde)
(Va

= 1.0 or 9.0 Vdc)

Output Drive Current

0, Write
(VOH

(VOL c

9.5 Vde)
0.5 Vde)

Source

9.5 Vde)

Sink

IOL
IOH

Source

IOH
IOL
IOH

Sink
(VOL = 0.5 Vde)
Output Drive Current (CL/CP Device)

Unit

Vdc
Vdc
Vde
10

4.50

5.50

Vdc
Vde
10

2.2

3.1

10
10

-6.0
6.0

10
10

-2.25

Vde
mAde

IOH

Output Drive Current fAL Device)

Outputs
(VOH

10
VOH

RST,D,X2
(Va = 9.0 or 1.0 Vdcl
(Va

-tp

VOL'

"1" Level
Input Voltage*

250

VDD
Vdc

mAde
mAde

2.25

mAde
mAde
mAde

Other Outputs

(VOH =9.5 Vdcl
Source
Sink
(VOL = 0.5 Vde)
Input Current (RST)
Input Current (AL Device)
Input Current (CL/CP Device)
Input Capacitance (DATA)
Input Capacitance (All Other Inputs)
(Vin = 0)

2.25
150

mAde

±O.ooool
±0.00001

15
5.0

"Ade
,.Adc
pF
pF

100

0.010

"Ade

100

0.010

"Ade

lin
lin
Cln
Cln

Quiescent Current (At Device)

-2.25

10
10
15
15
16

IOL
lin

,.Ade

(Per Package)
Quiescent Currant (CL/CP Device)

(Per Package)

"Tlow"" -5So C for AL Device. -40°C for CL/CP Device

Thigh

+125 0 C lor A L Device, +850 C for CL/CP Device.

Noise Margin for both "1" and "0"
= 2.0 Vde min @ VOO = 10 Vde

level

Figure 1.6

SWITCHING CHARACTERISTICS
Symbol

Characteristic

VDD
Vdc

All Types
Typ

10
10
10
10
10
10
10
10
10
10

110
100
125
120
110
120
90
110
40
50

Unit

Propagation Delay Time

Xl toRR
Xl to FLAGF, FLAGO, RTN, JMP
Xl to WRITE
Xl to DATA
RSTtoRR
RST to Xl
RST to FLAGF, FLAGO, RTN, JMP

tdR
'dF
tdW
tdO
tdRRR
tdRX
tdRF

RST to WRITE, DATA
Minimum Clock Pul•• Width, Xl

'dRW
PWC

Minimum Reset Pulse Width, RST

PWR

n.
n.
n.
ns
ns
ns
ns
n.
n.
ns

Setup Time
Instruction

tiS
'OS

10
10

125
50

DATA

tlH
tOH

·10
10

0
30

ns
ns

Hold Time
Instruction

DATA

IT A = 25°C; = 'I = 20 for X and I inputs; CL = 50 pF for JMP, X, RR,
FLAGO, FLAGF; CL = 130 pF + 1 TTLIoad for DATA and WRITEJ

Figure 1.7

RST

I
lEN
RegIster
OEN
Register

\
\

:;j
4 bit

Instruction

FLAGO

/4- 'dRRR

>---C)--CJ--

------:N70:cp~O:I

NOP F

J /~

tdF

k-I'L
\~___

FLAGF
~
________________1~1
Instructions NOPO, NOPF

RR. lEN, OEN remain unaffected

Figure 1.8 Timing Waveforms

NOP 0

(CLK)

lEN

1~~
o-------JC11~._t_IH_ _ _ _~\
LO.te.

_R.R_·_ _

LO etc.

~tOH
!X~____________________
-I

f-'dR

\L-___

lEN Register
(Internal)

Instructions lO,lOC, AND, ANDC, OR, ORC, XNOR & lEN
Valid when RST "" L

(CLK)

STO

NOP

OEN

STO

~_:.R.__~S~T_O~~!_j~~t~_______\ ___I_S_TOC_
OEN R.g'".,
(lnt.rnal)

~ ~'dO

1.._ _ __

~W~RI~TE~~~~-----------Inst,"ctions STO, STOC, OEN
Valid when RST

Figure 1.8 Timing Waveforms (Continued)

JMP
JMP
RTN
SKZ
~RS~T__________________________________________~'---

I
I

~M~P~F~L~A~G~______________________~I

tdRF~ ( l

~~~
__________________~/I~----~\L.
____~
____
~
FLAG
"
\

SKP F/F

Interna!

• Instructions Ignored.
Instructions SKZ, .INIP, RTN

RR. tEN, OEN remain unaffected.

Figure 1.8 Timing Waveforms (Continued)

CHAPTER 2 BASIC CONCEPTS
The block diagram in Figure 2.1 shows an example of a small leu-based PLC system.
The components, in addition to the leu, are compose9 ofstandard CMOS parts, except for
the memory.
.
.
The ICU system operates on the principle of a stored program processor. A set of
commands, called instructions, reside in the memory .of the leu system. Each command
instructs the ICU system to perform one of 16 operations.
The system "fetches" a command, and the necessary information to execute the
command, from memory, then "executes" the command. After executing a command, the
next sequential command is "fetched" from memory, and the process is repeated ad
infinitum.

LD & STO Commands
A typical command might be, LOAD (abbreviated LD). This command instructs the
ICU system to read the logic level (logic 1 or logic 0) of an input and store this information in
the Result Register within the ICU. To use the LD command, the user programs the memory
with the LD lnstruction and the address of the input to be sampled ..The operation of the

MC14516B
Clock

t Bit
Data Bus

I
~

<{
Q

.t:

4 bit
Instruetlon
(O~ Codel

Lb
1/0
Address

or
"I
EI
.~I
.a.

-.~
8 Inputs

Figure 2.1 Typical Small System Organization & Data Flow

system is as follows: The system memory supplies the lCU with the LD instruction (the
instruction is fetched), and supplies the input selector with the address of the input to be
sampled. The logic level of the selected input is then transferred over the lCU's one bit data
bus to the I bit Result Register. (See Figure 2.1).
Another typical command is STORE (abbreviated STO). This command instructs the
ICU system to transfer the data contained in its 1 bit Result Register to an output latch. To
use the STO command, the user programs the memory with the STO instruction and the
address of the output latch which is to receive the data. The operation of the system is as
follows. The system memory supplies the ICU with the STO instruction and supplies the
output devices with the address of the selected output latch. The data in the ICU's Result
Register is then routed to this latch over the ICU's one bit data bus. (See Figure 2.2).
Thus, data can be brought into the system, and also sent out of the system.

Write

MC14516B

Clock

iii

STO

I~
~

Figure 2.2 System Operation of STO Instruction

SYSTEM COMPONENTS
Memory
The system memory (see Figure 2.3) contains the program which instructs the system
to perform its assigned tasks. This program consists ofinstructions to the ICU in the form of
4 bit operation codes (op-codes) and addresses. The addresses (in binary number form)
route the data to and from the ICU's I-bit bidirectional data bus to the input and output
.~es.!
.
ICU
The lCU is the central control unit in the system. It controls the flow of data between its
internal registers and its I-bit bidirectional data line, performs logical operations between
data in its Result Register and data on its I-bit bidirectional data line, and sends control
signals to the other system components to coordinate the operation of the system.

Program Counter
The program counter (PC) supplies the lCU system memory with the address of the
command to be executed. The PC counts up sequentially in binary to its highest value and
"wraps around" to zero and counts up again. This causes the sequence of commands in
memory to be repeated creating what is known as a looping program.

MC14516B

MC14512
MC14599B
or MC140998

Figure 2.3 Basic System

Input Selectors
The input selectors are used to decide which of the inputs will be used in a particular
operation. The leu system memory supplies the input selectors with the address of the
input, then the selector demultiplexes this data onto the lCU's I-bit bidirectional data line
for use by the lCU. Thus, one input is selected from the many inputs.

Output Selectors
The output latches are very similar to the input selectors except the data flow is
reversed. When the leu receives a command to store its Result Register data, it transfers
this data to its I bit bidirectional data line and signals the output latch with the WRITE
control line. The output device then routes this data to the latch specified by the address
coming from memory.

The AND Instruction
Before continuing with an example, one more instruction is required - the AND
instruction. The operation of the AND instruction is as follows. The system memory
supplies the leU with the AND instruction op-code and supplies the input selectors with the
address of an input. The addressed input data is then demultiplexed onto the leU's
bidirectional data line. The information on this line is then logically' 'ANDed" with the data
which is residing in the Result Register. The result of this operation becomes the new
content of the Result Register. Notice that the final content of the Result Register will be a
logic I if and only if the previous content of the Result Register was a logic I and the input
data was a logic 1. The truth table is:

"AND"
Input

o
o
I
I

Initial Result
Register Contents

o
I

New Result
Register Contents

o
o

Example
The basic systc;m of Figure 2.3 is well suited to solving problems presented in the form
of relay ladders or solid state logic. Figure 2.4 shows the problem LOAD = A· B in both
these forms.
Thus, when A and B are closed (or a logical I), LOAD is energized (a logical 1).
The leU solves this problem not once and once only, but once per program loop. Thus,
if there are 1000 instructions in the program and the clock frequency is 500 KHz, the inputs
will be sampled 500 times per second (every 2 mS) and the output will be energized or
de-energized within 2 mS of an input changing. This is known as a looping control
structure.
12

Line

Return

~AI--I--li~
'~l

Figure 2.4A Relay ladder Rung

f"::::\

A
Load
=B_ _ _~~}---=O::

Figure 2.48 Solid State Equivalent of Figure 2AA

Figure 2.4 load· A • B

Figure 2.5 shows the leU program required to solve this problem.
Of course, the sequence could just as readily have been: LD B; AND A; STO LOAD.

Loads the state of Input A onto the
ICU's Result Register (RR)

Logically ANDs the state of input B
with the data In the leu Result Register
(which now contains A). The result of
this operation becomes the new contents
of the Result Register.
Transfers the data In the RR to the

output designated LOAD, thus activating
or deactivating the load device
Performs remainder of program Bnd

loops back

Figure 2.5 Example LOAD = A • 8 Program

CHAPTER 3 BASIC PROGRAMMING
AND INSTRUCTION SET
Accumulating Result R~gister
The reader will note that the AND instruction introduced the concept of an accumulating Result Register. In the execution of this instruction, the ICU logically performed an
AND function on the data on its bidirectional data line with the data in its internal Result
Register. The result of this operation became the new content of the Result Register. The
point to be made here is that the Result Register always receives the result of any of the
lCU's logical instructions. The Result Register therefore accumulates the logical result of
each lCU logical instruction. This is analogous to an adding machine which always displays
.
the subtotal after each operation.
Complement Instruction
It is sometimes desirable to activate an output when one input is in the logic 0 state and
another input is in the logic I state. This situation occurs in relay controlled systems where
"normally closed" relays are used, and occurs in solid state logic systems where inverters
are present. Figure 3.1 shows an example of this situation.
The lCU instruction set is prepared for this event. Several logical "complement"
instructions invert the logic level of the data on the ICU's bidirectional data line before
operation on this data.

~A~
Line

Return

Figure 3.1 Examples of Complemented Signals

The LDC Instruction
An example of one of these instructions is the load complement instruction, abbreviated (LDC). The operation of this instruction is as follows. The lCU system memory
supplies the ICU with the LDC instruction and the input selectors with the address of the
input to be used in the operation. The input selector then demultiplexes the data of the
selected input to the ICU's bidirectional data line. The ICU complements this data and stores
the result in its one bit Result Register. The Result Register will receive a logic 1 if the
selected input was in the logic 0 state. Figure 3.2 shows an lCU program which solves the
problem shown in Figure 3.1, using the LDC command. The reader should be convinced of
the operation of this program before reading further.
15

~B~
LOAD Return

Line

I LDC

I AND

I STO LOADI

Loads the logical complement of the A input
Into the Result Register.
Logically AND's the B Input with the content
of the Result Register (which conte Ins the
complement of the A input). The result of this
operation becomes the new content of the Result
Register.
Transfers the Result Register data to the output
latch designated LOAD.

Note that the STO Instruction will only transfer a logic 1 slgne' to the output fatch If the A signal Is logic O·
and the B signal is logic 1.

Figure 3.2 Using the LOe Command

The ANDC Instruction
Another example of a logical complement instruction is the "and complement"
instruction abbreviated (ANDC). The operation of the ANDC instruction is as follows. The
ICU system memory supplies the ICU with the ANDC instruction and the input selectors
with the address of a selected input. The input selector then demultiplexes this data onto the
ICU's one bit bidirectional data line. The leU complements this data and logically AND's
this data with the data in the Result Register. The result of this operation becomes the new
content of the Result Register. The Result Register will receive a logic 1 if the input selected
was at logic zero and the Result Register previously contained a logic 1.
With the addition of this instruction the leU is able to attack some more complicated
"chain" calculations. Figure 3.3 shows one such example. Figure 3.4 shows an leU
program which solves the problem depicted in Figure 3.3.
In reviewing the operation of these instructions, the reader should be convinced that
the load device will only receive a logic 1 signal if A = 1, B = 0, C = 1, and D = o.
16

Figure 3.3 Example of a Chain Calculation

Statement

Operator

Operand

LD
ANDC
AND
ANDC
STO

A
B
C
D
LOAD

#2
#3

#4
#5

Comments
Result Register +- A
Result Register +- A· B
Result Register +- A • B• C
Result Register of- A • B • C • i5
Result Register: A • B • C • 5 -+ LOAD

Figure 3.4 Program to Solve the Chain Calculation of Figure 3.3

ORandORC
In many cases, it is also desirable to activate an output when eitherinput is in the logic 1
state. In this event, the "or" instruction, (OR), should be used. The operation of the OR
instruction is as follows. The lCU system memory snpplies the OR instruction to the ICU
and the address of the input to be used in the operation to the input selectors. The input
selector then demultiplexes the addressed data onto the leu's bidirectional data line. The
leu then logically OR's this data with the content of the leu's Result Register and returns
the result of the operation to the Result Register.
The leu also has an "or complement" instruction, abbreviated ORC, in the event
complement logic is needed. The operation of this instruction is exactly like the OR
instruction except the incoming data is complemented before the OR operation is performed. Figure 3.5 shows some examples where the OR and ORC instructions may be used.

~A~

t=:~

Line

Return

LINE

#2
#3

LD
OR
STO

A
B
LOAD

RETURN

~
#1

Ct1

RR +-A
RR+-A+B
A + B : RR -+ LOAD

#2
#3

LD
ORC
STO

RR +-A
RR+-A+B

LOAD

Use of the ORC instruction

Use of the OR instruction

Figure 3.5 USB of the OR and ORC Instructions

+ B:

RR -+ LOAD

In the example of using the OR instruction, the load device will receive a logic 1 signal
if the Aor B or both inputs are in the logic 1 state. In the example of the ORC instruction, the
load device receives a logic 1 signal ifthe A input is in the logic 1 state or the B input is in the
logic 0 state.

Use of Temporary Locations
Many of the logic structures found in the controls industry are branches of several
series relays, in parallel with another branch of series relays. Figure 3.6 shows an example
of this structure.

RELAY LADDER LOGIC

SOLID STATE EQUIVALENT

Figure 3.6 Series·Paraliel Combinations

When dealing with this type of problem, it is not always possible to directly "chain" a
series of LD, LDC, AND, ANDC, OR, and ORC instructions together to correctly evaluate
the logic function required. In some cases, it may be necessary to temporarily store the
intermediate results before processing the remainder of the problem. In these cases, the
programmer must evaluate the series branches using LD, AND, and ANDC instructions as
necessary to evaluate the expression and then store the result in a temporary location. The
second series branch must then be evaluated and ORed with the data saved in the temporary
location. The result of this operation should then be used to activate or deactivate the load
device. Figure 3.7 shows a common error in programming this type of problem and Figure
3.8 describes and the correct approach to the problem. Figure 3.8 shows the correct method
for solving this problem by using a temporary storage location.

tj~B~
LINE

#2
#3

#4
#5

LD
AND
OR
AND

STO

A
B

C
0
LOAD

RETURN

RR +-A
RR+-A' B
**ERROR
RR+-A'B+C
RR +- (A • B + C) 0
RR .... LOAD

**Note that the final expression Incorrectly resulted in the D term being distributed
across all other terms. For example, if A, Band C are logic 1 and the 0 Input is logic 0,
the load device would receive a 10gic 0; this is incorrect because the load device should
be activated when the A and B inputs are logic 1.
Figure 3.7 Example of Incorrect Programming

~ f----l

b-Qj

f----l

Line

#2
#3

#4
#5
#6
#7

LD
AND
STO
LD
AND
DR
STO

LOAD Aeturn

RR +-A
RR +-A· B
AR = A • B -+TEMP
RR +-C
RR+-C·D·
RR +-C' 0 + (TEMP = A • BI = A • B
RR = A • B + C • 0 -+ LOAD

A
B
TEMP
C

0
TEMP
LOAD

• 0

In this program. the logical result of ANDing A and 8 is stored temporarily, then the logical
AND of C and 0 is ORed with the data previously stored in the temporary location. The
correct logical signal is then transferred to the load device. This example demonstrates
the need for temporary storage locations before proceeding.

Figure 3.8 Correct Method of Solving the Problem

The XNOR Instruction
The "exclusive nor" instruction, abbreviated (XNOR), is the final logical instruction
in the ICU's repertoire of logical instructions. The XNOR instruction can be thought of as a
"match" instruction. That is, whenever the input data is identical to the data in the Result
Register, the new content of the Result Register will be a logic 1. Figure 3.9 shows the truth
table for the XNOR function and Figure 3.10 an example using the XNOR function. Note
the reduction in code that may result from the use of this instruction.

Input

Old
Result
Register

Data

New
Result
Register
Data

0
0
1
1

0
1
0
1

1
0
0
1

Figure 3.9 XNOR Truth Table

EQUALS

LINE

#1
#2

#3
#4
#5

#6
#7

LD
AND
5TO
LDC
ANDC
OR
5TO

A
B
TEMP
A
B
TEMP
LOAD

EQUALS

LD
XNOR
STO

A
B

LOAD

Figure 3.10 Example of use of XNOR Instruction

The STOC Instruction
When transferring a signal to activate a load device, it is very useful to be able to store
the logical complement of an expression. The leu therefore has a "store complement"
instruction, abbreviated (STOC). The STOC instruction is exactly like the store (STO)
instrnction, except the logical complement of the Result Register is transferred to the output
latch. It should be pointed out that the Result Register retains its original value (i.e. the
STOC does not change the Result Register value, it merely transfers the complement of the
Result Register to the bidirectional data line for routing to the output latches). This
instruction is quite useful when dealing with negative logic or so called "low active"
devices. Figure 3.Il shows an example usage of the STOC instruction. Figure 3 .12 shows a
problem in both the relay ladder and logic formats. Figure 3.13 shows the problem reduced
to code.

:~D--------~
#1
#2

#3
#4
#5
#6
#7

LD
AND
5TO
LD
AND
OR
sToe

A
B
TEMP
e
0
TEMP
OUTPUT

RR-A

RR+-A'B
A'B-+1EMP
RR +-c
RR +-c· D
RR+-C'D+A'B
A • B + C • 0 --> OUTPUT

Figure 3.11 Example of the STOC Instruction

A~_.tHC~G

~
I :k
o

F
LOAD

RETURN

LINE

Figure 3.12 Complex Problem

#1
#2

#3
#4
#5
#6
#7

#6
119
#10
#11
#12
#13
#14
#15

LO
AND
AND
STO
LO
ANOC
AND
OR
AND
ANOC
STO
LO
ANOC
OR
STO

A
B
C
TEMP
0
E
F
TEMP
G
H
TEMP

TEMP
LOAD

RR .... A
RR .... A· B
RR .... A· B' C
A' B' C->TEMP
RR <-0
RR .... O
RR .... O· E' F
RR .... A·B·C+O·E·F
RR <- (A • B • C + 0 • E • F) • G
RR <- (A • B • C + 0 • E • F) • G • H
(A • B • C + 0 • E' F) • G • H .... TEMP
RR<-I
RR <-I' J
RR .... (A • B • C + 0 • E . F) • G • H + 1 • J
fA • B • C + 0 • E . F) • G • H + 1 • J -> LOAD

·e

Figure 3.13 Complex Example Problem Code

The Enabling Instructions, lEN and OEN
In addition to the lCU's logic instructions, the lCU provides two instructions for
controlling the program flow in a looping control structure. The reader will remember that,
in a looping control structure, each instruction is fetched from memory in sequential order.
In some instances, it may be desirable to effectively' 'jump" over a certain section of the
lCU program or to inhibit input data from effecting the system's output.
lEN
The first of these instructions is the "input enabling" instruction, abbreviated (lEN).
The operation of the input enabling instruction is as follows. The lCU system memory
supplies the ICU with the lEN instruction and the input selectors with the address of the
selected input to be used. The input selector demultiplexes the data of the addressed input
onto the ICU's bidirectional data line. The leu then latches the input data into its "input
enabling" register. If the input enabling registeris loaded with a logic 0, all future input data
will be interpreted as logic 0 until the lEN register is loaded with a logic 1 by another lEN
instruction. This instruction can be used in a manner similar to the way" master contacts"
are used in relay ladderlogic. Figure 3.14 shows an example usage of the lEN instruction.
Note, (statement #5), that if the lEN register was loaded with a logic 0 the Result
Register can only receive logic 0 data because only LD and AND instructions are used to
decide if the load device will be activated.

ABC

HH
w

~H
o

#1
#2
#3
#4
#5
#6
#7
#8

#9
#10
#11
#12
#13
#14
#15

LD
AND
AND
STO
lEN
LD
AND
STO
LD
AND
STO
ORC
lEN
LD
STO

A
B

f---I

C
W

MC
D
E
X

LINE

F
G

y
RESULT REGISTER}
RESULT REGISTER
H

Forces a 1 into the result
register, then forces a 1
into the tEN register.

Figure 3.14 Example of Using the lEN Instruction

RETURN

Caution
Care must be taken using the lEN instruction properly; remember that when the lEN
register contains a logic 0 all input data for the lCU will be interpreted as logic O. This can be
tricky. For example, assume the lEN register contains a logic O. If either an LDC or an ORC
instruction is executed, the Result Register will receive a logic I regardless of the actual
state of the inputs. Additional care must be takell to reload the lEN register with a logic I
after executing the block/of code to be controlled by the lEN register. In the example of
Figure 3.14, this is done in statements 12 and 13. Statement 12 forces the Result Register to
logic I and statement 13 loads the lEN register from the Result Register. Notice that the
Result Register data is "pinned out" on the MCI4500B and is here assumed to be
connected to one of the inputs ofthe system. In most systems, this connection will be made.
OEN
The second lCU instruction for controlling the operatiQ

STOC instructions. The key point is that once the OEN register is loaded with a logic 0, the
system outputs remain in their present state until the OEN register is loaded with a logic 1 by
another OEN instruction. Then and only then can the system outputs be changed by STO
and STOC instructions. Using the OEN instruction, the programmer can effectively
"jump" over a block of code by conditionally setting the OEN register to logic 0, causing
subsequent instructions to have no effect on the system outputs. The programmer can then
set the OEN register back to logic 1 so that future ICU code will operate in normal fashion.
Figure 3.15 shows an example use of the OEN instruction. In the example, the program
again assumes that the Result Register (RR) is available as a system input. Chapters 7
through 10 describe the OEN structures in greater detail.
In the example of Figure 3 .15, if A and B are both true statements 4 through 7 send two
pulses to output Z and statements 10 and Ii will not influence output Z effecting a
"pseudo" branch around these instructions. If the tested condition fails, statements 4
through 7 will have no effect on the output and statements 10 and 11 will send one pulse to
output Z. Statements 12 and 13 return the OEN register to logic 1 so that the Q output will
receive a logic 1, and future code will operate in normal fashion. Much more will be said
about the use and advantages of an OEN instruction in Chapters 7, 8, and 9.
Thus far, we have studied the LD, LDC, AND, ANDC, OR, ORC, XNOR, STO,
STOC, lEN, and OEN instructions. Of the remaining five instructions, two are no operation
(NOP) instructions and the other three are for optional use in larger systems which do not
have a looping control structure. These will be discussed later.

CHAPTER 4 HARDWARE SYSTEMS
The purpose of this chapter is to begin to acquaint systems designers with the
components which are ushd in a basic ICU looping control system. The system illustrated
was not specifically intended to be used in apractical design, however, it illustrates how the
components, which comprise the building blocks of an ICU system, might be used. From
this point, the system designer can delete, .augment or otherwise modify the system
illustrated to his own particular needs.
Figure 4.1 is a schematic diagram of a small ICU based system. The system has a
looping control structnre (i.e. the program counter is never altered by any operation of the
ICU.)
System Features
The scheme depicted on Figure 4.1 is a PLC-Iike system, deSigned to operate on the
principle of a looping control structure. It has 8 inputs, 8 outputs and 8 additional outputs
which can be "read" back by the lCU. These outputs can be used for temporary storage.
The system memory is capable of holding two separate ICU programs; each individual
program can be 256 ICU statements long.
Program Counter
The program counter is composed of two MCI4516B binary up-counters chained
together to create 8 bits of memory address. This gives the system the capability of
addressing 256 separate memory words. The counters are configured to count up on the
rising edge of the ICU clock (CLK) signal and reset to zero when the ICU is reset. Notice
that the program counter couut sequence cannot be altered by any operation of the ICU. This
confirms that the system is configured to have a looping control structure.
Memory
The memory for this system is composed of one MCM7641 512-word by 8 bit PROM
memory. Because the program counter is only 8 bits wide, only 256 words, (half of the
memory), can be used at anyone time. However, by wiring the most significant bit of the
memory's address high or low, the system designer can select between two separate
programs with only a jumper option. This might be a desirable featnre if extremely fast
system changes are required. Optionally, the designer could chain another counter chip or a
single, divide-by-two of flip-flop to the program counter and use the additional memory
space for more programming statements. If less than 256 program statements are needed
and fast tum aronnd is not needed, a smaller memory may be more economical.
Figure 4.2 shows the fonnat of each memory word. The most significant 4 bits contain
the instruction operation code which is routed to the ICU. The 4 least significant bits are
routed to the system's input selectors and output latches to address the system's inputs,
outputs, and "readable" outputs.
Memory Options
There are, of course, many ways to configure the memory of an ICU system.
25

+5 V

T T T I

CLK

U/D

,-,

v---o

MC14516S'"

PEF!

i~ T

I
+5

CLK

":,;:.

I T T T

PI
U/D
MC14516B'"
CO

CO P4

1JC=

0201

.u:
MC14040B
for low
cost, slow

II I

speed
operation

A8A7A6A5A4A3A2AI~

_
-

+5 V

~'~

MCM7641

CS4

CS2

~:~f ~o'ooo'~r" ~

+5V

RR
W

r"'!"""" X 2
Rx

~
D

03 02 II 10

-=.;:-

Reset

MCI4500B
XI

L-.J
I I I
Z C

MC14599B Reset

MCI4512

00--- -- -

XO- - - - - - -X7

TI I

DWCWA2A1AO
(V2) E 0

8 A

-01

11111111

System
Outputs & Scratch Bits

System
Inputs
"'Pull Down Resistors on Each Input

Figure 4.1 A Minimal leU System

C WA2A1AO

DW
(VI)

E 0

Reset MC145998
00- - -

-Q7

11111111
System

Outputs

Memory Word

To the

leu

To Input Selectors
& Output Latches

Figure 4.2 Parallel Memorv Word Format

Expansion
Figure 4.3 shows a simple approach to expanding the I/O address capability of an ICU
system. In this approach, the system memory is broken into two separate sections which
share common address lines and bring their data out in parallel. The first of these memories
is an N by 4 bit' 'instruction memory," used to hold only lCU instructions. The MCM7643
I K by 4 bit PROM is capable of holding 1024 ICU instructions and would be a good choice
for problems requiring moderate length programs. The second memory is an N word by M
bit "address memory" used to hold the address of the operand for each ICU instruction. The
MCM7641512 by 8 bit PROM is a good choice for this application. Two MCM764 1, 512
by 8 bit memories and one MCM7643 lK by 4 bit memory would comprise an lCU system
memory capable of holding 1024 complete ICU program statements and be capable of
addressing 256 inputs and 256 outputs.

NxM
I/O Address
Memory

Nx4

Instruction

Memory

MCM7641
512 x 8 PROM
MCM7641
512 x 8 PROM
_M
_

TolCU

To Input Selectors
& Outpu t Latches

Figure 4.3 An Approach to I/O Address Expansion

Using 4-Bit Wide Memories
It is also possible to "interlace" the instruction operation codes with the
addresses
in the same memory. In this type of structure, the CLK signal will become the least
significant address bit. When the clock signal is high, the memory supplies the ICU with an
instruction which will be latched into the ICU on the falling edge of the CLK signal. The
memory is then free to supply the Va sections of the ICU system with an address when the
clock signal is low. Figure 4.4 shows this. Thus, a 4 bit wide memory may contain the
instructions and addresses for 16 inputs and 16 outputs. This method is used in the
demonstration system. Note that as the clock-high and clock-low signals are still used, there
is no time penalty involved.

r'~_

Instruction

I/O Address

Instruetlon

''0 Address
Instruction

~
Figure 4.4 Interlaced Memory

Hybrid Expansion
It is also possible to interleave with 8 bit wide memory and thus create a 12 bit wide
(4096) Va structure. See Figure 4.5.

ClK: 1

Latched when elK falls

CLK: 0

~Fl
1--- 4 Bit - . ,

~----12 8it I/O Address

Figure 4.5 Interlaced 8 Bit Memory

----.,,0011

Input/Output Structure
The system shown in Figure 4.1 will be considered in more detail here. Figure 4.6
shows the complete IiO map.

Input Selectors
The input selectors used are MC14512 8-channe! data selectors. In the example system
of Figure 4.1, there is oilly I MCI4512 supplyiDg the"'system with 8 inputs. These inputs
occupy addresses 0 through 7 (see Figure 4.6). The input selectors multiplex the addressed
input onto the leu's bidirectional data during the CLK low phase of each ICU machine
cycle for all instructions except the STO and Sl'OC instructions. The number of inputs can
be expanded easily by adding additional address lines, the proper address decode, and
timing.

Output Latches
The output latches are composed of MC14599B 8 bit (biilirectionaI data port) latches.
In the example system of Figure 4.1, the MC14599B labeled Y 1 is used strictly as an output
latch supplying the system with 8 outputs. These outputs occupy addresses 0 through 7.
(See Figure 4.6.) The MCI4599 labeled Y2 is configured as a "readable" output latch. In
this configuration the part can be thought of as an 8 bit RAM with the outputs of each
location pinned out. Because this chip has the read/write feature implemented, it occupies
space in both the input and output sections of the IiO address map. The assigned addresses
are 8 through 15.
The output selectors receive the data coming from the leu over the lCU's bidirectional
data line. The information is transmitted during the clock low phase of a machine cycle
when the ICU executes an STO or STOC instruction, provided the OEN register contains a
logic I. The leu signals the output latches that a STO or STOC instruction is being
executed. The addressed output latches then receive the data and retain its value until the
latch is once again addressed and changed. Again, the number and configuration of the
output latches can be expanded easily by adding additional address lines, the proper address
decode and timing.

15
8

o
15

8
7

MCI4599B output latch #Y2
configured as read/write
here is written to

Output Addresses
Write"" 1
for STO & STOC

instructions
MC14599B output latch #Yl
configured as write only
MC14599B output latch #Y2
configured as read/write
here is read from

MC14512 input
selector

Figura 4.6 1/0 Map

Input addresses
Write "'0
for LD, LDC,
AND, ANDC, OR,
ORC, XNOR, feN
& DEN instruction

I/O Options
In the system shown in Figure 4.1, it may be more desirable to have more system inputs
and less temporary storage bits. In this event, the designer can reconfigure the Y2
MC 14599B to be a "write-only" output latch. This action would free 8 locations on the JiO
address map for 8 more inputs; another MC14512 could be used. The system would then
have 16 inputs and 16 outputs. The designer could create temporary storage bits by tying
outputs back to inputs. The memory options description showed how memory, and therefore, I/O, may be expanded.
Adding RAM
If the system requires a large number of inputs, outputs and temporary storage bits, it
may be more economical to put an N by I bit RAM on the data bus rather than using the
output latches and input selectors to effect temporary storage bits. See Figure 4.7 ..
ICU
The MC14500B is the central control element within the system. It coordinates the
actions of all the system's components. The system of Figure 4.1 was designed to use the
looping control structure of the ICU. In this type of structure, the Result Register is usually
tied to one of the system's inputs and in this example, the Result Register is returned to input
Xo. The ICU's RESET line is connected to a latch, which is set or reset by two momentary
contact switches, giving the system a HALT/RUN feature. Note that when the ICU is
halted, the output latches are cleared to zero.
Because the ICU is to be used in a looping control structure, the pulses created by the
JMP and RTN instructions are not required. Also, the pulses created by the NOP instructions are not used.
Notice that the lCU has NOP instructions of alii's or all O's. This was done because the
unprogrammed states of PROM's are all O's or all I's. Therefore, in a looping control
structure, the ICU can be allowed to sequence through these unprogrammed locations
without affecting the logical operation of the system.
Chapter 5 contains an example of an "interlaced" memory system and Chapter 12
contains an example of a hybrid (parallel/interlaced) memory system with a scratchpad
RAM.

Address
From ROl'y'l

Temporary

Storage

Address
From ROM

Figure 4.7 Adding RAM to a System

CHAPTER 5 DEMONSTRATION SYSTEM
General Description anf Capability
This chapter describ~ a 16 input and 16 output PLC (Programmable Logic Controller)
demonstration system featuring the Motorola MC14500B Industrial Control Unit as the
main control element within the system. The system is primarily designed to be used as an
educational tool to illustrate the simplicity and power ofthe Motorola MCI4500B leu. The
system illustrates the power of the "looping control structure" found in PLC systems.
Therefore, the jumping, conditional branching and subroutine capabilities available in the
ICU are not implemented in the system. (However, the programmer will discover that those
conventional program control techniques are not necessary, even when writing programs to
solve complex control problems.) The unit may also be used as a model for a small system
implementation.
The system has 16 inputs and 16 outputs, each numbered from 0 to 15, and a RAM
capable of holding 128 leu program statements. The user is able to examine or change the
contents of any location in memory, and has the option of running or single-stepping
programs. Alternatively, programmed PROM may be installed in the socket available, and
the system run from the PROM. In addition, the demonstration unit displays on LED's, the
content of the program counter, the 4 memory data lines, the content of the ICU's Result
Register and the current phase of each machine cycle when loading and single-stepping
programs. These features provide an easy means to understand the operation of the leu
system and to verify and trouble-shoot ICU programs.
Figure 5.1 shows the basic block diagram of the demonstration system. A schematic of
the system is shown in Figure 5.7.

Memory
To reduce cost, a 4-bit wide memory rather than an 8-bit wide memory has been used.
This means that the demonstration system is configured with "interlaced" memory such
that alternate locations in the memory contain the instruction and its corresponding operand
address. During the clock-high phase of a machine cycle, the memory supplies thelCU with
an instruction which is latched into the leu when the clock signal falls. The address of the
operand is found in the next memory location and is supplied to the I/O circuitry during the
clock-low phase of the machine cycle. This address is used in the execution phase of the
leu instruction. Therefore, the CLK signal is used as the least significant bit of the memory
address. The 256 X 4 bit RAM installed in the demonstration unit will hold 128 complete
8-bit ICU program statements. Most statements will result in a 4-bit op-code and a 4-bit
operand address being loaded into memory. Note that not all leu instructions require a
corresponding I/O address. In these cases, the I/O address location in memory may be left
unprogrammed.
In Figure 5.2 the progression from a normal Instruction-Operand in parallel, to
Instruction-Operand in series, and to actual RAM Operation code is shown. Note that there
is no difference in program time between the two structures, since both clock phases are
used in each case.
31

PC
_ _ S~I~h.!' _

-+---'W'v-o

I/O

QP·Code

Address

Light

Figure 5.1 Demonstration Syst9m Block Diagram

Instruction

Operand

Mnemonic Code

Input

AND

Input # 1

SKZ

IN/AI

STO

Output 'it 7

OP Code in RAM

#2
AND

#1
SKZ
OO,n't Care

5TO
#7

0001
0010
0011
0001
1110

xxx X
1000
0111

Figure 5.2 Interlaced Memory Structure of Demonstration System

Program Counter
The program counter supplies the memory of the ICU s..ystem with its most significant
address bits. The least significant address bit is supplied by the clock (CLK) signal, as
explained above. The program counter normally increments on the rising edge of each clock
pulse, sequencing the ICU through the programmed instructions in memory. In a nonjumping, non-branching system, the count sequence of the program counter is not altered by
the ICU program statements. Therefore, the control program statements are executed in
order, until the program counter "wraps around," and the sequence is repeated. This is
known as a "looping control structure."
The program counter can be thought of as a statement counter; for each unique count,
the clock signal will be high and low, causing the memory to supply the ICU system with an
instruction and its operand address. This constitutes I machine cycle and the completion of
I ICU instruction.
In the demonstration system, the NOPF instruction (which canses the FLAGF output to
pulse for one clock cycle, when the NOPF instruction is encountered) is used to by-pass
unprogrammed memory space, to avoid tediously coding to NOPO's and stepping through
unused locations. This is done by using the FLAGF output from Pin 9 to preset the program
counter to the setting of the program counter switches. Figure 5.3 is an illustration of this,
with the program counter toggle switches to zero.

AND
AND

~fo

GOPF

INPUT # 1
INPUT #2
INPUT #3
INPUT #4
OUTPUT # 1
Causes the prograro counter

to be preset to zero

Unprogrammed Locations
In Memory
Assume the program starts at location zero in memory and the
program counter toggle switches are set to zero.

Figure 5.3

ICU and Input/Output System
The MCI4500B operates synchronously with a single phase clock which divides the
leu machine cycle into two phases. The first phase (CLKHIGH) is the "fetch" phasethe ICU fetches an instruction from the memory. When the clock signal falls from the high
level, the instruction is latched into the leu's instruction register. Then, during the second
phase, (CLK LOW), the instruction is executed.
There are three types of I/O related instructions-logical, input, and output. During the
execution phase of input or logical instructions the operand of the instruction is demultiplexed onto the lCU's data bus by the input data selectors. The memory supplies the input
selectors with the address of the bit to be used in the operation. During the execution phase
of an output instruction, the ICU puts the data in its Result Register (or its complement) on
its data bus and raises the (WRITE) control line. The data bit is then multiplexed to an output
line where it is latched on the rising edge of the clock signal. The memory supplies the
address of the output latch, to which, the data is to be routed.
Display Lights
The Program Counter lights show, in binary, the current count of the program counter.
These lights can be used to determine which ICU statement is currently being executed
when single stepping, and are also useful in keeping track of ICU statements when loading
program.
The memory data lights show the content of the memory location currently addressed
by the program counter and the clock signal. After data has been loaded into memory, it is
displayed by the memory data lights. The lights are also useful in verifying programs
entered in memory. This can be done by resetting the ICU, then single stepping through the
memory locations with the single step push-button and observing the memory data lights.
The OP-CODE and I/O ADDRESS lights actually reflect the state of the clock (CLK)
signal. The OP-CODE light indicates that the clock is high and the I/o ADDRESS light
indicates that the clock is low. These lights are very useful when loading programs into
memory. The lights indicate to the user whether the operation code of an instruction or the
operand address should be entered. The lights also indicate the state of the system, (Fetch or
Execute), when single stepping programs.
The Result Register light indicates the content of the Result Register. This is useful in
understanding the operation of the leu logical instructions in the single-step mode.
Functional Switches
RAM!PROM selects which memory, the RAM or the PROM, will be enabled for use
by the ICU.
RUN/SINGLE STEP selects which mode the ICU will operate in when the ICU's
RESET line is pulled to logic zero.
DATA switches setthe data, either instruction op-codeor I/O address, tobe loaded into
the memory.
PROGRAM COUNTER switches set the memory location to which the data is sent.
LOAD loads the data selected by the data switches into the RAM location indicated by
the program counter display lights and the op-code, I/O address lights. Mter loading data
into RAM, the data entered will be displayed by the data display lights.
SINGLE STEP advances the ICU's clock (CLK) one half cycle per depression. (Le.
the single step push button toggles the clock signal.) The present state of the CLK signal is
indicated by the op-code and I/O address lights. (op-code light --> CLK = I, I/O address
light --> CLK = 0.)
34

LOAD PC enters the data selected by the program counter switches, into the program
counter. After loading the program counter, the value loaded will be displayed by the PC
display lights.
RUN latches the lCU's RESET line to logic zero. The leu will then sequence through
the program in memory or the program may be "single stepped" using the single step push
button.
HALT/RESET latch~ the leu's RESET line higli. resetting the lCU. In addition, the
system's output latches and program counter are cleared to zero.

Example Problem
The following example shows a typical problem that the lCU may be used to solve.
The example illustrates how a problem is reduced to code, and how, using the demonstration
system. the code is entered into memory, verified, and executed. The example problem
illustrates how an leu program solves a typical relay ladder logic network, shown in Figure
5.4. In this problem the load device is to be activated if relay A and relay B are closed or if
relay C is closed. For the purpose of illustration relays A, B, and C will be represented by
switches and the load device activation will be indicated by an LED.
For this problem the following assignments are made:
INPUT # 6
IS TIED TO LOGIC I
SWITCH # 6 IS ALWAYS HIGH
INPUT # I
REPRESENTS RELAY A
SWITCH # I
INPUT # 2
REPRESENTS RELAY 8
SWITCH # 2
INPUT # 3
REPRESENTS RELAY C
SWITCH # 3
OUTPUT # 1 REPRESENTS THE LOAD DEVICE
LED # 1

LlNE~~0RETURN
LOAD

Figura 5A

Figure 5.5 shows an lCU program which will implement this function and the code to be
loaded into memory. The" A" portion of Figure 5.5 shows the lCU interpretation, the "8"
portion shows the programming steps.

CAUTION: Note that input zero (0000) is reserved for the Result Register. Therefore,
input zero must not be used; if violated, improper system operation will result.

Explanation of Program
Statement # I loads the lEN register with a logic 1. If the lEN register contained a

logic 0, all future input data for the logical instructions would be interpreted as logic o.
Statement # 2 loads the OEN register with alogic 1 to enable the output instructions. If
the OEN register contained a logic 0, the WRITE strobe from the leu would be inhibited
and the output latches could not be signalled to activate the load.
35

A: leu tntepretation

1 START
2
3
4

5
6
7END

Instruction

Operand

lEN
OEN
lD
AND
OR
STO
NOPF

lOGIC 1
lOGIC 1
A
B
C
lOAD

Notes
Enable the input register
Enable the output register
Load the state of switch A into the Result Register
Logically "AND" switches A and B
Logically "OR" A • B with switch C
Transfer the result to the load to activate/deactivate it
Causes the program to repeat th is sequence

8: Programming Steps

Op-Code
Program
Counter

PC= 0
PC= 1
PC= 2
PC= 3

Clock
State

1ClK
High
ClK low
1ClK
High
ClK low
1ClK
High
ClK low

1ClK
High
ClK Low

PC=4

PC= 5

PC=6

ClK
ClK
ClK
ClK
{ClK
elK

High
Low
High
low
High
low

1/0 Address

Hex4·Bits
A
0
B
0
1
1
3
2
5
3
8
0
F

Binary

1010
0110
1011
0110
0001
0001
0011
0010
0101
0011
1000
0001
1111
xxxx

Notes
lEN Instruction

Address of Logic 1
DEN Instruction
Address of Logic 1

i.e. Input #6
i.e. Input # 6

lD Instruction

Address of A

i.e. Input # 1

AND Instruction

Address of B
OR Instruction
Address of C
STO Instruction
Address of load
NOP Instruction

i.e. Input # 2

i.e. Input #3
i.e. Output # 1

No Address needed

*Don't Care

Figure 5.5 Solution to Typical Problem

Statement # 3 loads the Result Register with the state of switch A.
Statement # 4 logically AND's the state of switch B with the contents of the Result
Register; this result is then returned to !lie Result Register. The Result Register will now
contain a logic 1 if and only if switches A and B were both high.
Statement # 5 logically OR's the state of switch C with the content of the Result
Register; this result is then returned to the Result Register. The Result Register will now
contain a logic I if and only if switches A and B were high or switch C was high.
36

Statement # 6 stores the content of the Result Register in the output latch. If the Result
Register contained a logic I, the output latch would receive a logic I to activate the load.
The STO instruction does not alter the content of the Result Register.
Statement # 7 creates a pulse on pin # 9 of the ICU chip. This signal is used to preset
the program counter to the beginning ofthe program. The entire sequence is then repeated.
The following is a ~etailed procedure for entering, verifying, single stepping and
running the example program.

I. Entering the program to RAM.
A. Set the RAM/ROM and RUN/SINGLE STEP switches to RAM and SINGLE
STEP RESPECTIVELY.
B. Set all the PC switches to zero.
C. Press the HALT/RESET push button. This resets the PC to zero, resets the ICU,
the output latches and sets the CLK signal high. The OP-CODE light will
indicate that the CLK signal is high and an instrUction should be loaded into
memory.
D. Set the data switches to hex A (OP-CODE ofthe first instruction), binary 1010
and press the LOAD push button. The 1010 pattern will be displayed by the data
lights.
E. Press the SINGLE STEP push button once. This toggles the CLK. The I/O
address lights will indicate that the CLK is low and an I/O address should be
loaded into memory.
F. Set the data switches to hex 6 (ADDRESS of switch six), binary 0110 and press
the LOAD push button.
G. Press the SINGLE STEP push button once. Note the PC has incremented and the
CLK is high indicating the next complete statement should be entered.
H. Set the data switch to the bit pattern of the next piece of data to be enteredlOll in this case.
I.
Press the LOAD push button.
1. Press the SINGLE STEP push button once.
K. REPEAT STEPS H, I, 1 UNTIL THE ENTIRE PROGRAM HAS BEEN
ENTERED.
L. NOTE: The NOPF instruction does not require that an I/O address be entered in
memory. The I/O address location in memory for this instruction may he left
unprogrammed.
M. Press the HALT/RESET push button.
STOP
2. Verifying the program entered in RAM.
A. Press the HALT/RESET push button. The PC will be reset to zero, the CLK will
be high and the first piece Of data entered, (1010), will be displayed by the data
lights.
B. Press the SINGLE STEP push button once. The second piece of data entered,
(0110), will be displayed by the data lights. The entire program may be verified
by sequencing through memory with the single step feature, while observing the
data display lights. The PC lights and the OP-CODE and I/O address light will
aid in keeping track of particular lCU statements.
C. Press the HALT/RESET push button.
STOP
37

3. Single stepping the program.
Set switch # 6 and switch # 3 high. Setting these switches high will cause light # 1 to
activate on the (CLK LOW) phase of the 6th (STO) instruction.
A. Press the HALT/RESET push button.
B. Press the RUN push button.
The processor may now be sequenced through the program entered in memory
by using the single step feature. Each depression of the SINGLE STEP push
button advances the CLK 1/2 cycle. The display lights will aid in understanding
the operation of the system as it is single stepped.
C. Press the HALT/RESET push button.
STOP
4. Running the program.
A. Press the HALT/RESET push button.
B. Set the RUN/SINGLE STEP switch to RUN.
C. Press the RUN push button.

Switch # 6 should be set high. This enables the lEN and OEN registers. The reader
will now note that light # 1 is activated when switches 1 and 2 are both high or when switch
# 3 is high. The processor may be halted by pushing the HALTIRESET push button. The
following Figure 5.6 is a program the reader may implement as an exercise. (The ANDC
and aRC instruction will be useful). Figure 5.7 is the schematic of the system, with the
major areas partitioned and labeled.

Figura 5.6 Reader's Problem

Figure 5.7

leu Demonstration Unit Schematic

Address

00000000&&&&&>&&&
A7

L - -_ _ _ _ _ _ _ _ _- - - - - ,

Load

I~@":
Op

Code

I/O

RO~

Addr.

Reg.

RAM

@ @
Reset

RU---,
Key"" K1· K2 ....... KN;

code for time of day.
FLAG bit Indicates this
routine started

Old F LAG Indicates other
routines started
Start

r - ____

I
:

t; _____ ,

Instructions for
this Routine or

L__ ~'.:"~~~r~o!__

I
,

LD
AND

Kl
K2

AND
ANDC
OEN
STO
STOC

KN
FLAG
RR
FLAG
OLD FLAG

Instructions for

this routine

End

ORC

OEN

End

Figure 6.6 Time·of·Day Routine

MeMOS RELIABILITY AND DEVICE
HANDLING PROCEDURES
Confident use of a family of components requires assurance of the reliability of a
component under normal operating conditions and the ability of the device to survive
abnormal conditions that may occur. CMOS, and specifically Motorola McMOS, has
achieved the high confidence level for equipment usage that has been enjqyed by many
other semiconductor products.

RELIABILITY
Figure 6.7 shows the composite failure rate of commercial ceramic and plastic
packaged McMOS integrated circuits as a function of temperature. Note that CMOS
devices dissipate little power and work nominally close to ambient temperature. This
feature adds to CMOS reliability. The data shown represent over 40 million equivalent
device hours and give failure rates to the factory set of test limits. This standard of failure is
more severe than a catastrophic failure rate.
46

25
O. 1

V~D -}O V

rz::

0.01

75 %/l000.HOURS

'" 1\

0.00 1

0.000 1

0.00022%/1000 HOURS

'" \

0.00001
130120110100 90

TEMPERATURE

1'\
30

0.000011%/1000 HO URS
20

°c

This device contains circuitry to protect the inputs against damage due to high static voltages Dr electric fields; however. it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit. For proper operation it Is recommended that Vin and Vout be constrained to the
range VSS" (Vln or Vout )" VOO.
Unused Inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or

VOOI.

Figure 6.7 - Failure Rate of

Commercial MeMOS Integrated Circuits
(Ceramic and Plastic Packaged Devices)

HANDLING PRECAUTIONS
All McMOS devices have diode input protection against adverse electrical environments such as static discharge. The following statement is included on each data sheet:

Unfortunately, there can be severe electrical environments during the process of
handling. For example, static voltages generated by a person walking across a common
waxed floor have been measured in the 4 to 15 kV range (depending on humidity, surface
conditions, etc.). These static voltages are potentially disastrous when discharged into a
CMOS input considering the energy stored in the capacity ( =300 pF) of the human body at
these voltage levels.
47

Present McMOS gate protection structures can genemlly protect against overvoltages.
This is usually sufficient except in the severe cases. Following are some suggested handling
procedures for McMOS devices, many of which apply to most semiconductor devices.
1. All MOS devices should be stored or transported in materials that are somewhat
conductive. MOS devices must not be inserted into conventional plastic
"snow" or plastic trays.
2. All MOS devices should be placed on a grounded bench surface and operators
should ground themselves prior to handling devices, since a worker can be
statically charged with respect to the bench surface.
3. Nylon clothing should not be worn while handling MOS circuits.
4. Do not insert or remove MOS devices from test sockets with power applied.
Check all power supplies to be used for testing MOS devices to be certain there
are no voltage transients present.
S. When lead straightening or hand soldering is necessary, provide ground straps
for the appamtus used.
6. Do not exceed the maximum electrical voltage ratings specified by the data
sheet.
7. Double check test equipment setup for proper polarity of votlage before conducting parametric or functional testing.
8. Cold chambers using C02 for cooling should be equipped with baffles, and
devices must be contained on or in conductive material.
9. All unused device inputs should be connected to VDD or Vss.
When external connections to a PC board address only an input to a CMOS integrated
circuit, it is recommended that a resistance 10 kO or greater be used in series with the input.
This resistor will limit accidental damage if the PC board is removed and wiped across
plastic, nylon carpet or inserted into statically charged plastic "snow".
The input protection circuit, while adding some delay time, provides protection by
clamping positive and negative potentials to VDD and Vss, respectively. Figure 6.8 shows
the internal circuitry for the diode-resistor protection.
The input protection circuit consists of a series isolation resistor Rs, whose typical
value is 1.5 k~, and diodes Dl and D2, which clamp the input voltages between the power
supply pins VDD and Vss. Diode D3 is a distributed structure resulting from the diffusion
fabrication of Rs.

Input

o--+.....'VV'_-+-~

All present Motorola integrated circuits have the above diode

protection with the exception of the MC14049 and MCl4050.
Figure 6.8 - Schematic Diagram, Diode-Resistor Input Protection

Isolating Inputs
Many applications require electrical isolation between a signal source and the control
logic. There are four usual way,s of doing so: Optical isolators, transformer and capacitive
coupling and relay contacts. The relay contacts are simply used as a switch closure to the
logic supply or to ground. The other schemes require more discussion.
Optical Isolated Inpu"
Figure 6.9 shows two typical examples of opto isolation.
+vn---------------~r_~------------~----------~

tnpu"O

curren.!.!O>------lf----l
Ground O~-----l~

+vo---------------~~--------------~------~>--~

tnpu~~

curr9n.,!c.J~
L ______ J
Ground O>------~l

Figure 6.9 Optically Isolated Inputs

Transformer Coupled Inputs
Transformer coupling is used, most often, for detecting the phase or amplitude of a
power line derived signal. Figure 6.10 shows a voitage level-sensing scheme. Figure 6.11
has a connection for detecting the phase of an AC signal.

Ac::J11
Figure 6.10 Amplitude Detection of AC Signal

:JII
Figure 6.11 Phase Detection of AC Signals

Capacitively Coupled AC Signals

For convenience or economy, a designer can sometimes replace a transformer with a
capacitor. Figure 6.12 shows the way this might be done. The capacitive divider technique
might be preferred for true ratioing of voltages up to the zener value.

Voo

AC 5ig ,>----ll-----~--_'VIIV_---_I

Vz';;Vr;>o
Gnd

>----------i

Note: The diode also
give open input protection

Zener Clamped Capacitive Input

AC 51g »----lI-----.----'\IIIIr--~_I

Gnd

)>-------.1
Capacitive Divider Input

Figure 6.12 Capacitive Input Schemes

Sampling Inputs
It is possible that a signal might change status during a loop of a program. If an initial
sample of a signal and a later sample of the same signal were of different values, some
undesired result might be obtained. The simple avoidance of this problem is to sample all
the variables at the beginning of a program and to store them in temporary stores. Whenever
the values are needed l*er in the program, the.tempgrary store contents should be used in
lieu of the input signal( The rule is:
Only sample an input signal once in any program.

OUTPUT CONDIT10NING
High Current
Figure 6.13 shows an interface between a low impedance load and an MC14599B ICU
output device. The MCI413 interface ports will drive 300 rnA loads when saturated, with
Vee up to SOV. Inrush currents of 600 rnA may be handled.by the MCI413, which allows
incandescent lamp loads of 300 rnA to be driven without derating for inrush. The interual
diodes are useful for damping inductive load switching transients.

MC14599B

07
1

01 02 Q3 04 05 Q6
11
12 13 14 15 16 17

Load

2.7 k

Typical

-=-

Section

Figure 6.13 High CUrrent Output Buffers

Relay Driving
A typical interface to a machine must often be made using electromechanical relay
contacts for loading switching. This occurs because the original wiring of the machine was
desigried before electronic control was contemplated. As shown· on Figure 6.14, the
MC 1413 can also serve as a relay coil driver.
51

+28 V

Signal
from

Pins
1·7

ICU
System

9_S~:;~i:ci~3

load
Relav

Detail

Pin.
10·16

1/7
MC1413

Figure 6.14 Driving Relays

LED Driving
Driving LED's or opto-couplers is much like driving a relay load, except that an
external current limiting resistor is used to control the current through the LED, coupler or
solid-state-switch. See Figure 6.15. High-efficiency LEDs can be driven directly from
CMOS circuits.

+v
R ~ +V -2.0

Signal
from

ICU

Pins

1·7

Pins
10·16

I~'

LED, Switch
or Coupler

System

117
MC14137

Figure 6.15 Driving LED loads

Driving Thyristors (SCRs & Triacs)
There are many different means for driving thyristors. One of the simplest and most
reliable will be shown here. The method uses pulse transformers and is called the "picket
fence" technique. The name is due to the scope trace of a pulse transformer's secondary
•
voltage when the primary is pulsed many times each millisecond.
Given an adequate supply voltage and a resistive load, a triac or SCR will usually tum
on when driven by a single gate pulse. However, combinations of low voltage and reactive
loads can keep a device from reaching the on (latched), state. The picket fence approach is
to supply a train of gate pulses so that the SCR or triac will latch on during the first pulse time
when sustaining conditions are met. This allows the devices to turn on as close to zero
crossings of load voltage as possible. Additionally, the technique is quite economical.
There are three key parameters to satisfy: Minimum pulse width, maximum pulse
width and gate currerit requirements. Additionally, a check of the insulation specifications
of pulse transformers is in order.
52

Minimum pulse width and thyristor gate current numbers are obtained from device
data sheets. After defining minimum pulse width, a rule-of-thumb is to exceed the
minimum, say by a factor of two. The maximum pulse width requirement is dependent upon
the volt-second-product (VSP) of the transformer. The importance of VSP is to insure that
the pulse transformer will not saturate, the driver will not bum up, and a current limiting
resistor need not be used.
The maximum pulhe width as a function of supply voltage is:
PWMAX = vVSP

seconds

supply .

An lCU system that has a clock period of four times PWMAX can pulse a triac driver by
storing a "I" in the driver and removing it three clock periods later:
(RR = I, OEN = I)
STO
TRIAC
NOP
DON'T CARE
NOP
DON'T CARE
STOC
TRIAC
This code would need to be repeated many times; to conserve memory space, a
subroutine could be called over and over, to make a picket fence gate drive effective. As
shown on Figure 6.1, the output of a pulse oscillator is "ANDed" with the ICU output.

4
5

9
B

Rl •

R2 • C"" Pulse Space

Figure 6.16 Picket Fence Triac Firing

Adding Hysteresis to Inputs by Using Outputs
A simple, but useful, trick in an ICU system is to add hysteresis to an input signal,
under program control. In Figure 6.17, the input pin on an MC14512 device can be an input
and an output signal. The ICU reads the input signal, stores the result in the output (positive
feedback) and then reads the input again.

LD
STO
LD

INPUT
OUTPUT
INPUT

Gang Transfer of Outputs
While looping through a program, the ICU addresses each output bit in a sequential
manner. If a particular controller configuration requires that all output bits be available
simultaneously, then the output values can be stored in additional latches or flip-flops. A
simple routine can be added to the program to strobe the lCU outputs into the latches. The
latch outputs are then available to the rest of the system. The strobe, or pulse-generating
routine is:
START
STOP

ORC
STO
STOC

RR
PULSE
PULSE

FORCERR TO 1
PULSE GOES HIGH
PULSE GOES LOW

End of Program
Often, one wants to return to the top of the program immediately after completing the
last written instruction. Usually, there is a pulse output on the MCI4500B device that is not
being used in the system. For example, if FLAG 0 is not being used elsewhere in the system,
then it can simply be OR'd with the program counter's reset signal.
In other words, the PC will jump to 0 whenever a FLAG 0 instruction (Nap 0) is
executed. The Nap commands do not need an address (operand); hence, the ROM's
operand field can be AND'ed with NaP's (FLAG pulses) to generate user defined functions.

Figure 6.17 Adding Input Signal Hysteresis

CHAPTER 7 OEN AND
THE IF-THEN STRUCTURE
The OEN Instruction
The Output Enable (OEN) instruction is the most unusual and powerful instruction in
the MCI4500B. This is the instruction that makes the looping, (as opposed to jumping),
program flow powerful aiid practical.
All the concepts required to exploit the OEN's power are shown in Figure 7 .1. The four
important ideas are:
1. If the OEN register holds a I, the ICU can write to output or memory devices. If
OEN holds a 0, the WRITE pulse carinot be generated and no output device or
memory content will change. OEN thus controls whether or not the leu system
is "working" at any moment.
2. Any input signal can be directly loaded into the OEN register. An input can be
wired to the supply or ground to give an addressable 1 or O. The Result Register
output can also be used as an input signal.
3. The physical connection allowing the Result Register to be addressed as an input
is so useful it should always be utilized.
4. A block of instructions can be used that calculates whether or not a subsequent
block of code is to be executed. As this result resides in the Result Register, the
Output Enable Register should be loaded with OEN RR.
IF-THEN (OEN Step 1)
In this section, the Output Enable instruction (OEN) will be used to simplify the logic
controlling the program's execution. The title IF-THEN implies exactly what we want to do.
If a condition is satisfied TIIEN a block of code will be enabled. If not, the code should be
disabled (ignored) so it cannot change the state of any output or internally stored bits.
For example, if overtemperature switch OTS is closed (= I), sound horn H, turn off
oven power OP, and turn on oven temperature light OTL. The leu routine is as follows:
I
2

START

3
4

5
6
7

END

LD
OEN

OTS
RR

STO
STOC
STO
ORC
OEN

H
OP
OTL
RR
RR

LOAD SWITCH STATE
ENABLE OUTPUTS IF I
IN RESULT REGISTER
TURN ON HORN
TURN OFF POWER
TURN ON LIGHT
FORCE RR TO I (RR + RR = 1)
ENABLE OUTPUTS

The first two statements disabled the outputs if the overtemperature switch was not
closed. Two statements are nsed, one to load the state of OTS into the Result Register, the
other to enable the output or WRITE signal.
This is an example of a conditional program. The program can affect outputs only
when the OEN register has a stored 1. Otherwise, nothing is changed by the leu's execution
of the seven instructions. The same number of clock cycles are used in either case. This is an
55

MC145DOB

r-----------------------------,
I
I
~_t

Data

I
:
I

Enabling
Register

:
I
I

QEN

Write pulse output when
store or store-complement
instruction is used AND
output enabled (OEN - 0

I
I
I

Flow of
Looping
Program

STO or
STOC
Instruction

DEN
Instruction

I
I

Block of
Enebling InstructIons

I
I
I
I

I
I
I
I
I

I RR

Result
Register

I
I
I
IL_____________________________ JI

When this Connection
Exists, Result Register
Loads Output Enabling
Register with Instructions
OEN RR

I
I

Any Il1put in
Loads Output
Enabling Register
with Instruction

Enabled
Block of
Instructions

Block of
Enabling Instructions

Enabled Block
of Instructions

I
I

OEN'N

Figura 7.1 Output Enable Concepts

example of an IF-TIlEN block of code. The last two statements re-enable OEN for use by
other blocks or sections of code. Figure 7.2 shows a flow chart representation of this
IF-THEN block. The instructions that are executed in each block are written beside the
blocks.
It is important to notice that when the IF test fails, nothing happens. This distinguishes
IF-TIlEN blocks from other code or the flow chart structures we will examine in other
chapters.
To Review: IF-THEN code blocks ask a question. If the question is answered yes (OEN
= 1), the code following the question is enabled and the programs section is enabled.
Otherwise, the code following is not workable because the WRITE pulse is not produced by
the leu when OEN = O.
56

Start

1. ·LD
2.
OEN

OTS
RR

(RR <-OTS)
(OEN <-RR)

3.
6.

STO
STO
STOC

H
OTL
FP

(H<-RR)
(OTL +- RR)
(FR<-RR)

6.
7.

ORC
OEN

RR
RR

(RR <-1)
(OEN <-RR)

End

figure 7.2 An If·Then Program Block

There is no restriction on the structure of the block of code or instructions enabled by
the IF question in an IF-THEN structure. The block can contain other IF-THEN structures,
as shown in Figure 7 :3, or any of the other two program structures to be described in the next
two chapters.
Start

Start

r--------I
I

I
I

II
I
I

I
I

End

I
I

I
I
I

IL ________ _

I
I

_________ JI

End

Figure 7.3 The Instruction Block May Be Complex

CHAPTER 8 THE IF-THEN-ELSE
STRUCTURE (OEN STEP 2)
In the IF-THEN an;angement of Chapter 7; we~w that an action could be taken if a
condition was satisfied. For example, if the limit switc6 is closed, tum off the motor. There
is no statement about what is to happen if the switch is /lOt closed; The IF-THEN-ELSE has
the alternate action instructions not provided for in the IF-THEN structure.
The IF-THEN-ELSE structure is shown in Figure 8.1. A question is asked, if the
answer is "no," block B's instructions are enabled and executed. We can see now that if
block B contains no instructions, we once again have the simple IF-THEN structure. Once
again, the output enable OEN is used. The "A" block is enabled by loading the OEN
register from the Result Register (assuming RR = 1). To enable B, the complement of RR is
stored, to be recalled later to either enable or not enable B. Thus the IF-THEN-ELSE
sequence is as follows:
1. Resolve the enabling condition.
2. Store the complement of the result in some temporary location ("TEMP").
3. Load the Output Enable Register OEN from the Result Register RR.
4. Do the A Block.
5. Load the Output Enable Register from "TEMP."
6. Do the B Block.
7. Restore the OEN's condition to enable (OEN = 1) to allow subsequent code to be
enabled.

Start

Figure 8.1 IF·THEN·ELSE

An example follows:
A simple IF-THEN-ELSE usage is to "turn on" a load if a condition exists, and to
"turn off" the load otherwise. Such a function can be directly done, without the IFTHEN-ELSE structure. However, it is the enabling logic that is to be illustrated, not the
control function.
The example is illustrated in Figure 8.2. The motor M is to run if the A and B contacts
are both closed. Otherwise, themotoris nottorun. If A . B = I, thenM = 1, elseM = O. To
start the routine, assume lEN = 1 (input enabled).

LD
A
RR ~ A
ANDC
B
RR ~ A . B
2.
STOC
TEMP
TEMP = A . Ii = A + B
NOTICE: THE RESULT REGISTER STILL CONTAINS THE ENABLE CONDITION AND ITS COMPLEMENT ENABLE IS IN "TEMP"
3.
OEN
RR
ENABLE "RUN" CODE
4.
STO
M
THE MOTOR RUNS
5.
OEN
TEMP
OEN ~ TEMP
6.
STO
M
THE MOTOR STOPS
7A.
ORC
RR
RR ~ RR + RR = I
7B.
OEN
RR
OEN ~ 1
START

IA.
lB.

In this example, the executable blocks consisted of single store instructions, which
took advantage of the fact that the Result Register RR contained a 1 in the first "block" if
the motor was to run, and a 0 in the second "block" if the motor was to stop.
LD
ANDC
STO

A
B
M

RR~A

RR~A·B
M~A·

= ~.f-__-::I/lI(f[_,--_-{&:·rurn

Figure 8.2 Function for IF-THEN-ELSE

It would have been six instructions briefer, but our example would be lost. The extra

statements will allow us to write very complex programs in a straight forward and organized
fashion. Notice, in Figure 8.3, that a "block" of instructions in our IF-THEN-ELSE
structure could contain other IF-THEN or IF-THEN-ELSE structures. In that case, we
wonld say the structures were "nested".

Start

'""'-'II!I--------

....1-1--""'1---\--/---

...-+-+-+--

IF·THEN-ELSE Question

IF Block Is an IF·THEN
Nested IF-THEN auestion

X Block of Instructions

--------'1....1 - - - - ~~~~!I·~~~-~~eN-ELsE
""'- (0, 0, 1); Multiple~
in left turn time from thumbwheel switches, pulse parallel
enable of timer chip, tllm left
turn arrow on,

Change fla!.J bits from 51 to 52
(0, O. 1) ...... (0, " 0); Turn left
turn arrow off; MultipleK In the
red overlap time from the thumb
wheel switches, pulse the parallel
enable of the timer chip.

Change flag bits from SO to 53
(0, D. 0) -I> (0,1, 1); Multiple~
in the North-South green time
from the thumbwheel switches,
pulse parellel enable qf tfmer
chip,lurn North-Soulh green on.

Change flag bits from 52 to S3
(0,1,0) -+ (0,1,1); Multiplex
In the North-South green time
from the thumbwheel switches,
pulse the parallel enable of the
timer chip, turn the North-South
green light on,

Change flag bits from SO to 56
(0,0,0) --+- (1, 1, 0); Multiplex
In the East-West green time from
the thumbwheel switches, pulse
perellel enable of timer chip,
turn East-West green on.

Change the flag bits from S3 to 54
(0.1,1) 4 (1, D, OJ; TUrn the NorthSouth yellow on, and the NorthSouth green off; MultipleJ( In the
yellow time from the thumbwheel
switches, pulse the paralfer eneble
of the timer chip.

Figure 11.3 Flow Chart

Change flag bits from 54 to 55
(1.0,0) -+ (1,0,1); Turn the
North-South y"now off; MultIplex in the red overlap time
from the thumbwheel switches,
pulse the parallel enable of the
timer chip_

Change flag bits from 56 to 57
11.1,0) -+ (1,1,1); Turn EastWest yellow on. turn East-West
green off; Multiplex In the vellow
time from the thumbwheel switches.
pulae the parallet enable of the timer
chip.

Change flag bits from 55 to S6
(1. D. t) -+(1, 1.0); Turn EastWest green light on; Multiplex
in the East-Wast green tIme
from the thumbwheel switches.
pulse the parallel enable of the
timer chlp_

Change the flag bits from 57 to SO
(1, 1, 1) -+(0, 0, 0); Turn East-West

yellow off; Multiplex in the red overlap time from the thumbwheel
switches, pulse the parallal enable
of the timer chip.

Change the flag bits from 55 to 51
(1.0, 1) -+ (0. 0,1); Turn left turn
arrow on; Multiplex in the left turn
tima from the thumbwheel switches,
puIs. the parallel enable of the timer
chip_

Figure 11.3 Flow Chart (continued)

Table 11.1 Intersection Controller Input/Output Listing
ICU Inputs
Input #
0

Name
RR

1
2

LR
MOD

TMz

4
5
6
7
8

NSR
EWR

Function
The pinned out Result Register is connected to this Input so the ICU can condItionally load the lEN and OEN register, and manipulate the result register
content.
Signal indicating that a request for a left turn has been made.
Selects the mode of operation the intersection will function in MOD = 1 smart;
MOD = 0 sequence.
This Is the (low active) carry out of the timer chip. the monitoring of this
input determines when time has elapsed.
Inputs 4, 5, and 6 are tied to outputs 8, 9, and 10 respectively. The soltware
uses these three bits as flags to determine which block of code will be Uactlve"
as the ICU .equences through the Instructions in memory.
Signal indicates that a request for the North-South green light has been made.
Signal indicates that a request for the East-West green light has been made.

ALL SIGNALS ARE HIGH ACTIVE UNLESS OTHERWISE SPECIFIED
ICU Outputs
Output #
0
1
2
3
4
5
6
7
8

11
12
13

Name
LeftTMR
PE
ARROW
NSGRNTMR
NSG
EWGRNTMR
EWG
EWY

Function
Multiplexes the left turn time to the inputs of the down counter.
Parallel enable of the down counter.
Left tum arrow light.
Multiplexes the North-South green time to the Inputs of the down counter.
North-5outh grean light.
Multiplexes the East-West green time to the input of the down counter.
East..west green light.
East-West yellow light,
Outputs 8, 9, and 10 are tied to Inputs 4, 5, and 6 respectively. The software
uses these three bits as flags to determine which block of code wfll be active as
the ICU sequences through the instruction in memory.
North-5outh yellow light.
NSY
YTMR
Multiplexes the yellow time to the inputs of the down counter.
REDSFTMR Multiplexes the red overlap time to the inputs of the down counter.
Table 11.2 Intersection Controller Program

Memory
Location

Op
Code

I/O
Address

00
01

7
A

0
0

Mnemonic
OpCod.
XNOR
lEN

Symbolic
Address

LD
ORC
ANDC
ANDC
ANDC
ANDC
OEN
STO
STO
STO
STOC

LR
MOD
BO
B1
82
TMZ
RR
BO
LEFTMR
PE
PE
LEFTMR
ARROW

RR
RR

Comment

Force RR to 1
Enable Input

IF THEN BLOCK \al
02
03
04
05

06
07
08
09
OA
OB
OC
OD
OE

6
4
4
4
4
B
8
8
8
9

9
8

1
2
4
5
6
3
0

8
0
1
1
0
2

STOC
STO

Load LR
OR with MOD
AND with BO
AND with B1
AND with B2
AND with TMZ (Low Active)
Enable II R = 1
Change State to SI
Enable Left Time SW
Pulse Timer Loed
Pulse Off
Disable LeltTime SW
TUrn On Left Arrow

IF-THEN BLOCK Cb)
Memory

Location
OF
10
11
12
13
14
15
16

17
18
19
lA
lB
lC

10
IE

Op
Code

I/O
Address

Mnemonic
OpCode

Symbolic
Address

1
6

7
8
,1
)2
'3
4

NSR
EWR
LR
.MOD
TMZ
BO
Bl
B2
RR
80
Bl
NSGRNTMR
PE
PE
NSGRNTMR
NSG

B
8
8

6
0
8
9

1
1
3
4

LD
ORC
ANDC
AND
ANDC
ANDC
ANDC
ANDC
OEN
STO
STO
STO
STO
STOC
STOC
STO

Op
Cod.

I/O
Address

Mnemonic
OpCode

Symbolic
Address

4
5

BO
81
82
MOD
EWR
LR
NSR
TMZ
RR
Bl
82
EWGRNTMR
PE
PE
EWGRNTMR
EWG

4
3

4
4
4

9
9
8

.,'5

Comment

Code in this Block follows Com·
ments in Block (a)

IF-THEN BLOCK (el
Memory

Location
IF
20
21
22

6
·2
8
1

27
28
29
2A
2B
2C

4
3
3
4
4
4
8
8
8
8

8
9

1
1

6
6

LoC
AN DC
AN DC
AND
AND
ANoC
ANDC
AN DC
OEN
STO
STO
STO
STO
STOC
SToC
STO

I/O
Address

Mnemonic
OpCode

Symbolic
Address

4
5
6
3
0
8
9

Lo
ANDC
ANoC
ANoC
OEN
STOC
STO
STOC
STO
STO
STOC
STOC

80
Bl
82
TMZ
RR
80
Bl
ARROW
REDSFTMR
PE
PE
REDSFTMR

23
24
25

7
3
0
9
A

Comment

logic Flow is same as Block fal

IF-THEN BLOCK Cd)
Memory
Location

2F
30
31
32
33
34
35
36
37
38
39
3A

Op
Code

1
4

4
4
B
9
8
9
8
8
9
9

2
0
1
1

Comment
See Block (a) for Comments

IF·THEN BLOCK leI

3S
3C
3D
3E
3F
40
41
42

U
44
45

2
3
4
4
B

8
8
8
9

9
8

4
5

6
3
0

8
3
1
1
3

LOC
AND
ANDC
ANDC
OEN
STD
STO
STO
STOC
STOC
5TO

BO
Bl
82
TMZ
RR
BO
NSGRNTMR
PE
PE
NSGRNTMR
NSG

Form Same as Block

lal

IF·THEN BLOCK III
Memory
Location

Op
Code

1/0
Address

Mnemonic

OpCode

Symbolic
Address

1
5

8
1
2
3
4

4
C
1
1
C

LD
OR
ORC
ANDC
AND
AND
ANDC
OEN
STOC
STOC
STO
STO
STOC
5TO
5TO
STOC
STOC

EWR
LR
MOD
TMZ
BO
Bl
B2
RR
BO
Bl
B2
NSY
NSG
Y1MR
PE
PE
Y1MR

Op
Code

I/O
Address

Mnemonic
OpCode

Symbolic
Address

4
5

LDC
ANDC
AND
ANDC
OEN
STO
STOC
STD
STO
STOC
STOC

80
81
82
TMZ
RR
BO
NSY
REDSFTMR
PE
PE
RED5FTMR

47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55

6
4
3

3
4
B

9
9
8
8
9
8

8
9
9

5
6
0

9
A

Comment

See Block lal

IF·THEN BLOCK 191

Memorv
Location

57
58
59
5A
58
5C
5D
5E
SF

60
61

3
4
8
8

9
8
8

9
9

6
3
0

8
8
D
1
1
D

Comment
Same Structure as Block (a)

IF-THEN BLOCK (hI
62
63

1
6

65
66
67
68

4
3

6A
68
6C
60
6E
6F

8
8
8
8
9
9

IF-THEN BLOCK

8
2
3

)6
'0
8
,9
6'
5
1
1
5

LD
ORC
ANDC
AND
ANDC
AND
OEN
STOC
STO
5TO
STO
5TO
STOC
STOC

EWR
MOD
TM2
80
81
' 82
RR
80
81
EWG
EWGRNTMR
PE
PE
EWGRNTMR

iii

Memorv

110

Mnemonic

Location

Code

Address

OpCode

Symbolic
Address

70
71
72

4
5

74
75
76

3
3
4
8
9

LD
ANDC
AND
ANDC
AND
AND
ANDC
OEN
STOC
5TO
5TO
STO
STOC
STOC

80
81
82
TM2
MOD
LR
EWR
RR
82
ARROW
LEFTTMR
PE
PE
LEFTTMR

LDC
AND
AND
ANDC
OEN
5TO
5TO
5TOC
5TO
5TO
STOC
STOC

BO
Bl
B2
TM2
RR
BO
EWY
EWG
YTMR
PE
PE
YTMR

77
78
79
7A
7B
7C
70

IF-THEN BLOCK
7E
7F
80
81
82

83
84
85
86
87
88
89

Structure or Block fal Repeated

8
8
8
9
9

6
3
2
1
8
0
A
2
0
1
1
0

Comment

Structure repeats again.

iii
2
3
3
4
B
8
8
9
8
8
9
9

4
5
6
3
0
8
7
6
C
1
1
C

And again . ..

IF·THEN BLOCK (kl
Memory

Location
BA
86
8C

80
BE
BF
90
91
92
93
94
95
96
97

Op
Code

1/0
Address

Mnemonic

I
3
3
4
6
9
9
9

4
5
6
3
0
B
9
A
7
D

LO
AND
AND
ANDC
OEN
STOC
STOC
STOC
STOC
STO
STO
STOC
STOC
NOPF

9
B
8
9
9
F

1
1
0

OpCode

Symbolic
Address
BO
81
62

Comment
Start Last Block

fMZ
RR
60

81
62
EWY
REDSFTMR
PE
PE
REDSFTMR

NOPF

End Last 610ck & Prog.
Flag F can be used to r&set program
counter after last instruction If Flag
F resets PC
or
the balance of ROM will contain

FF
97

F
0

X
X

NOPF
NOPO

program will

NOPO

No Address

NOP's when the rest of the loea·
tions are unprogrammed and the

automatlcallv loop
around to the first instruction.

INTERSECTION CONTROLLER HARDWARE
Display Board
The traffic intersection display board is controlled by the lCU and the control program
located in the demonstration board ROM. Two 16-wire cables interface the display board to
the lCU system inputs and outputs. The display uses a separate power supply. The display
board has a "hard wired" flash feature where the red lights flash in both directions when the
ICU is in the reset state. The display bolird has three request buttons which are used to
simulate traffic conditions. When the request button has been pushed, the request is latched
and displayed by an LED. The request light will go off after the request has been serviced
(Le. that particular direction gets a green light).

Timing
There are five different time intervals in the traffic controller, each settahle by a
thumbwheel switch. The intervals are: N-S Green Time, E-W Green Time, N-S Left Turn
Time, Common Yellow Time and Red Overlap Time. The Red Overlap"or Red Safety
interval allows the last car traveling on Yellow to clear the intersection before the next
direction starts a Green interval. During red overlap or clearance time, all red lights are on.
When a state is entered, a common counter is loaded with the state of the proper
thumbwheel switch. The thumbwheel switches are connected by diodes to a common four
wire bus used to load a down counter. When a particular time is to be used, an ICU output is
sent high to drive the common line of one of the switches. The counter's load pin is then
pulsed by another ICU system output, and the switch's common line is returned to a low
state. (See the section on timers, Chapter 6). The switches and the counter/timer are on the
Display Board shown in Figure 11.4.
84

~=:j~~====~

3 AO

AFlFlOW

a"",
1'1-8

D.....v
Syltam

N-SR-auln

MC14D43B

Slgnll

NI'

MOD

i'iif.

uewl'l
00
lOOk) resistors. This provides for another way to modularize an ICU
system. ROM can be placed on a card together with the VO devices required to perform a
function. The ROM is addressed from the central program counter and enabled by an enable
decoder.
If the "feature card" is installed in t/le. system, the feature card's ROM is enabled
during some interval of the program count and the ROM controls the system. All other
ROM's in the system are, of course, disabled at this time. If the feature card is missing from
the system, the program counter increments through the states assigned to the feature's
program, but receiving no instructions, the lCU does "NOP's" until some ROM that is in
the system furnishes the lCU with instruction codes. The only restriction to the use of a
feature card is that of" Jumping" the program counter off the feature ROM's enabled block.
Users who write such a jumping command must therefore exactly understand the implications of their code.
95

CHAPTER 14 ARITHMETIC ROUTINES
Occasionally, in a decision oriented controller,spme arithmetic may be required for
timirig, parts counting ot part of the enabling routine for some control functions. A nUcleus
of arithmetic coding follows. Programs which do large amounts of arithmetic can be
assembled by buildingVi!th the listed routines.
Binary Addition

Binary addition is an operation involving five bits: two bits to be added or operands,
carry-in and carry-out bits and a sum bit. About 12 operations are required to do a one bit
add. Addition, as well as other more complex functions, can be sent to a companion
microprocessor or calculator. For example, if addition were the only arithmetic function,
relegating the task to a CMOS adder might be appropriate. If the percentage of processing
time required for addition is small, it is generally more economical to do the task completely
with the ICU system. This is an instance of effective usage of the ICU's sub routine
capabilities.
The code for single bit add with carry follows.

Cout

1+:

Sum
A
+B Cin

(sum

+- Ci

LD
XNOR
XNOR
STO

Cin
B
A
SUM

GENERATING THE SUM
S = A$(B$C)
= A Ef) (ifEIrC) .
SIMILAR TO GENERATING PARITY

LD
OR
AND
lEN
OR
STO

B
Cin
A
B
Ci
CARRYout

ORC
lEN

RR
RR

RESTORES THE lEN MASK

= A·B + A·Ci + B·Cin

= A·(B + Cin) + B·Cin
RR +- A·(B + Cin)

ACTUALLY PERFORMS B· Cin
RR = A·(B + Cin) +B·Cin ~ Co

ONE BIT ADD WITH CARRY

Incrementation
Adding 1 to a stored number, or incrementing by 1, is perhaps the simplest and most
common arithmetic function. It is used in parts counting, measuring frequency, etc.
In the code below we operate upon a single bit position at a time. For the Nth sum bit
the variables' name is Sn. The carry in for the Nth Sn bit is denoted Cn. The carry out for the
next bit position is denoted (n+ I). Notice that incrementing is analogous to forcing the
initial carry in to I and adding zero to the number to be incremented. When the routine,
starts, Carry is set to 1 if the incrementation is to start. Otherwise, the initial value for Carry
is o.

C"I

~
.

And

+Bn +- + Cn
Sn

Sn = BnEB Cn
Cn+ I = (Bn EBCn)· Bn
LD
Bn
XNOR
Cn
STOC
Sn
AND
Bn
STO
Cn+l

The routine is repeated N times for an N bit incrementation.

Counting Rising Edges
As a matter of practicality, counting rising signal edges is a simple and straightforward
method of incrementing a sum.

OLD (STORED)
The code is:
START LD
XNOR
OR
STOC
LD
STO
END

,NEW

OLD (STORED)

NEW

+
NEW
OLD

QLD
CARRY
NEW
. OLD

COMPARE OLD/NEW; 1 IF EQUAL
1 IF OLD .wAS,ffiGH
CARRY ZERO .iF NO RISING EDGE
PUT NEW IN OLD FOR NEXT TEST

Notice that NEW is sampled twice. To avoid this, use a Temp Store, e.g.
START

END

LD
STO
ANDC
STO
LD
STO

NEW
TEMP
OLD
CARRY
TEMP
OLD

CARRY GETS RESULT
AVOIDS 2nd SAMPLING

Magnitude Comparison
The Algorithm: Magnitude comparison compares two binary numbers to see which is
greatest or if they are equal. Only three results are possible.
To compare two binary words, it is convenient to start with the most significant bits. In
each bit position a comparison is made to see if the bits are identical. If they are, continue to
the next bit position. If the bits are different, set EQUAL to 0 and set a flag indicating that
the word wi th the 1 is greatest.
Three variables or flags are used, AGTR, BGTR and EQU. These correspond to A
Greatest, B Greatest, and Equal. Initially set AGTR = 0, BGTR = 0 and EQ = 1.
Assume lEN

OEN

START

ORC
STO
STOC
STOC

RR
EQ
AGTR
BGTR

FORCERRTO I
!NIT EQ
INIT AGTR
INIT BGTR

NTH BIT

OEN
LD
XNOR
STO
OR
STOC
LD
OR
STOC
OEN

EQ
AN
BN
EQ
AN
BGTR
EQ
BN
AGTR
EQ

ENABLE IF EQ = 1
LOAD NTH A BIT
COMPARE TO NTH B BIT
NEW VALUE TO EQ
BGTR = EQ + AN
STORE NEW BGTR
LOADEQ
AGTR = EQ + AN
STORE NEW AGTR
ENABLE IF EQ 1

END NTH BIT
N-I ST BIT

REPEAT FOR EACH BIT POSITION
99

leu System
________________
__________________
~A~

Outputs

Flgur. 14.1 ROM for I·Blt Add

Look-Up Tables
The processor overhead "expense" of a 1 bit add shows the need for a better
implementation. One answer is a LOOK-UP TABLE as shown on Table 14.1. The
operands and operator in an arithmetic expression are used as the address to a ROM. The
ROM supplies the answer to the input pins in an lCU system.
As an example, a "1 bit ADD with Carry" will be examined. There are three operands
- A, B and Carry-In; the operator is Add; the results are Carry-Out and Sum.
The ROM organization is summarized in Table 14.1. The binary addition of three
single-bit operands can only result in 23 =8 possible outcomes. The sum and carry outputs
of the ROM are simply the known results of any possible combination. The operator, ADD
"vectors" (points) the lCU to the addition look-up table in system memory. The Look-Up
ROM needs, at the most, 16 bits! The Look-Up Table idea can be extended to nearly any
type function. Look-Up Tables for sine values, as an example, have long been standard
semiconductor parts.

Tabl. 14.1 The ROM Look·up Tabl.
ADDRESS
Operator
(Add)

Operand

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

(A)

DATA

Operand
(B)

Operand

0
0
1
1
0
0

0
1
0
1
0
1

(CI)

ROM Add..... _ _ _ _..J)

Result
(Sum)

Result

0
1
1
0
1
0
0
1

0
0
0
1
0
1
1
1

(CO)

\.. ROM Content-'

Note that Operator (Add) "" 0 could easify "vector" the ROM to a Subtract Table

lOO

CHAPTER 15 TRANSLATING
ICUCODE
Repacing combinatorial logic with an lCU system is very simple and straightforward.
All that is involved is the Writing of the short codes which describe.the logic devices. Logic
functions and their associated codes
depicted in the following diagrams.

are

AND

NAND

NOR

XOR

j:[y

Lo
AND
STO

~
J[>

A
N
Z

"" Load A
And each Input In turn
Store In Z

Lo
AND
STOC

A
N

And each Input In tum

Store complement In Z

Lo
OR
STO

A
N

Or each 'nput In turn

Store In Z

J[>-

Lo
OR
STOC

A
N

Load A
Or each Input In turn

Store compo in Z

Lo
XNOR
STOC

l.oad A

B
Z

Compare to B
Store compo In Z

Lo
XNOR
STO

A
B
Z

Store In Z

XNOR

101

Load A

XNOR B

INVERTER

lD
STOC

----~

load A

Store In A 1

Notice: This code Is never required
as the leu can load and store complements.

o FLIP FLOP

To clock on rising edgfls. clock is stored in
old el.K to compare with current eLK.

Start

End

lD
STO
lD
STO
ANDC
OEN
lD
ST
ORC
OEN

OLD ClK
TEMP
ClK
OLDCLK
TEMP
RR

RR "" eLK· OLD eLK
ENABLE STORE

D
Q

RR
RR

RESTORE OEN
IF NO Q CHANGE

SA FLIP FLOP

lD
ANDC
STO

lOADS
_
AND WITH R

S
R
Q

a=-O'ST+Q'ST
SINGLE lATCH
lD
AND
STO
lD
ANDC
OR
STO

JK FLIP FLOP

0." + 1 =

o
ST
TEMP
Q

ST
TEMP
Q

LOADD
AND WITH STROBE
STORE IN TEMP
LOADQ
_ __
AND WITH STROBE
OR WITH TEMP
STORE IN Q

an • K + an • J.

CLOCK ON RISING EDGES, CLOCK STORED IN OLD CLK.

01---

Start

End

LD
STO
LD
STO
ANDC
OEN
LD
ANDC
STO
LDC
AND
OR
STO
ORC
OEN

102

OLDCLK
TEMP
CLK
OLDCLK
TEMP

1'1
Q

K
TEMP
Q

J
TEMP

R
R

MOVE OLD CLK
TO TEMP.
FIND RISING
EDGE.
ENABLE OUTPUT
IF EDGE FOUND.
} AND QWITH
KCOMP.
STORE IN TEMP.
} AND Q COMPo
WITHJ,
_
OR WITH Q. K
STORE NEwn.
RE ENABLE
OUTPUTS.

r
I
r
t
r

Reducing Boolean Equations to ICU Code
The following procedure is a straightforward way of writing ICU Code for evaluating
Boolean expressions. One temporary storage location, "TEMP", is used. It is generally
possible to avoid the use of "TEMP", however, the code will not be as easy to read.
Procedure:
1. Reduce the Boolean expression. The result will be a "Sum of Products" form
(e.g.,A· B +C' D· E+" ·+X· y. Z) oraproductofsumsform(e.g., (A + B) . (C+
D + E)' ... '(X + Y
Z).
2. Use the Sum of Products Procedure or Product of Sums Procedure, both below.

Sum of Products Procedure
A. Factor common terms from the Sum of Products Expression, giving an Expression in the form
J . K . L (A . B . C + D . E + ... + X . Y . Z).
The distributed term (J . K . L) which was factored from the Sum of Products
form will be used as an "INPUT ENABLE TERM". That is, if the INPUT
ENABLE TERM is not 1 or true, then everything following will be evaluated as
o or FALSE.
B.

Evaluate the INPUT ENABLE TERM and store in INPUT ENABLE.
START
ORC
RR
SETRRTO I
lEN
RR
ENABLE INPUT
LD
J
LOAD 1st ELEMENT
K
AND WITH NEXT
AND

END

AND
lEN

L
RR

AND WITH LAST
STORE RESULT in lEN

Reduce the fIrst INNER TERM and store in "TEMP".
START
LD
A
RR GETS A
AND
B
AND WITH B
AND
C
AND WITH C
END
STO
TEMP
STORE IN TEMP

Reduce the next INNER TERM and/or with TEMP, store result in TEMP.
LD
D
RR GETS D
START
AND
E
AND WITH E
OR
TEMP
END
STO
TEMP
TEMP now has A . BC . + DE, providing lEN = 1. If lEN = 0, TEMP = O.

Repeat D. for all the remaining inner terms.

The Sum of Products value is now in the Result Register and stored in TEMP. To
unconditionally enable the lCU for other routines, restore lEN and OEN to the
I's state.
START
ORC
RR
RR GETS I
RR
lEN GETS 1
lEN
OEN
RR
OEN GETS 1
END
103

Product of Sums Procedure
A. Factor common terms from the Produce of Sums form, giving an expression in
the form
(J + K + L) (A + B + C) . (D + E) . . . . . (X + y + Z).

The distributed term which was factored out will be used as an "INPUT
ENABLE TERM" .
START LD
J
RRGETSJ
OR
K
OR WITHK
OR
L
OR WITHL
END
lEN
RR
lEN GETS RR

Reduce the first INNER TERM and store in "TEMP".
START LD
A
RR GETS A
OR
B
OR WITHB
OR
C
OR WITHC
END
STO TEMP STORE IN TEMP

Reduce the next
START LD
OR
AND
END
STO

Repeat D. for each of the other INNER TERMS.

The evaluated product of sums is in RR and stored in TEMP. The following
routine will completely enable the lCU for other uses.
START ORC RR
RRGETS 1
lEN
RR
lEN = I
END
OEN RR
OEN = I

INNER TERM, and with TEMP, store result in TEMP.
D
RR GETS D
E
OR WITHE
TEMP
TEMP

104

APPENDIX A. THE MC14S99B 8-BIT ADDRESSABLE LATCH

Features
... Parallel Buffered Output

The MC14599B Is an 8 bit eddressable latch capable of reading

previously stored data. The device has a chip enable Input for
easy address expansion, buffered Qutputs, and a master reset
pin for system clean.

• Bidirectional Addressable Input/Output

-.. Master Reset
• WRITE/READ Control
... Write Disabfe
... Chip Enable
... B Series CMOS

Control
Logic

W/i'!

Reset

Date

8
Latches

MC14599B Block Diagram

105

MC14599B Truth Tabl.

Internal States &: Data

Inputs

Addressed

Other

Latch

latches

DatB
Pin
Z

ON
(Output)

1
0

Data

Input

1
0

x == Don't Care
NC = No Change

Z :::: Open Circuit
ON

=State of Addressed Cell

Voo

Reset

Data

Write Disable

(MSB)A2

Chip Enable

WRITE/READ

VSS

MC14599B

106

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MC14500B_Industrial_Control_Unit_Handbook_1977 MC14500B Industrial Control Unit Handbook 1977

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