MC68HC05P1_Technical_Data_Jan91 MC68HC05P1 Technical Data Jan91

User Manual: MC68HC05P1_Technical_Data_Jan91

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MC68HC05PlID
REV 1

MC68HC05Pl
TECHNICAL
DATA

®

MOTOROLA

MC68HC05P1
HCMOS MICROCONTROLLER UNIT

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body. or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola,
Inc. is an Equal Opportunity/Affirmative Action Employer.

®

©MOTOROLA INC., 1990

TABLE OF CONTENTS
Paragraph
Number

Title

Page
Number

Section 1
Introduction
Section 2
Pin Descriptions

2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10

VDD and VSS ...................................................................................................2-1

OSC1 and OSC2 (Oscillator Inputs) ..........................................................2-2
Crystal .....................................................................................................2-2
Ceramic Resonator...............................................................................2-2
External Clock .......................................................................................2-3
RC Oscillator ..........................................................................................2-4
RESET .............................................................................................................2-5
External Interrupt Request (IRQ) .................................................................2-5
I/O Port Function .............................................................................................2-5
PortA................................................................................................................2-7
Port B................................................................................................................2-7
Port C ...............................................................................................................2-8
Port D and Timer Capture (TCAP) ..............................................................2-8
Timer Compare (TCMP) ...............................................................................2-9

Section 3
Central Processor Unit
3.1
CPU Registers ................................................................................................3-1
3.1.1
Accumulator (A) .....................................................................................3-2
3.1.2
Index Register (X) .................................................................................3-2
3.1.3
Stack Pointer (SP) ................................................................................3-3
Program Counter (PC) .........................................................................3-4
3.1.4
3.1.5
Condition Code Register (CCR) .........................................................3-4
Half-Carry Bit (H Bit) .................................................................3-5
3.1.5.1

MC68HC05P1

MOTOROLA
iii

TABLE OF CONTENTS (Continued)
Paragraph
Number
3.1.5.2
3.1.5.3
3.1.5.4
3.1.5.5
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.5
3.5.1
3.5.2

Title

Page
Number

Interrupt Mask (I Bit) ..................................................................3-5
Negative Bit (N Bit) ....................................................................3-5
Zero Bit (Z Bit) ............................................................................3-5
Carry/Borrow Bit (C Bit) ............................................................3-5
Arithmetic/Logic Unit (ALU) and CPU ControL .......................................3-6
Addressing Modes.........................................................................................3-6
Inherent. ..................................................................................................3-6
Immediate...............................................................................................3-7
Direct .......................................................................................................3-8
Extended ................................................................................................3-9
Indexed, No Offset ................................................................................3-10
Indexed, 8-Bit Offset .............................................................................3-10
Indexed, 16-Bit Offset ...........................................................................3-11
Relative ...................................................................................................3-12
Instruction Set. ................................................................................................3-13
Register/Memory Instructions .............................................................3-14
Read-Modify-Write Instructions ..........................................................3-14
Jump/Branch Instructions ....................................................................3-15
Bit Manipulation Instructions...............................................................3-16
Control Instructions...............................................................................3-17
Instruction Set Summary .....................................................................3-18
Opcode Map ..........................................................................................3-23
Low-Power Modes.........................................................................................3-24
STOP Mode ...........................................................................................3-24
WAIT Mode.............................................................................................3-25

Section 4
Resets and Interrupts
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.3

MOTOROLA
iv

Resets ..............................................................................................................4-1
Power-On Reset (POR) ........................................................................4-2
External RESET Input ..........................................................................4-2
Interrupts..........................................................................................................4-2
Extemallnterrupt. ..................................................................................4-5
Software Interrupt (SWI) ......................................................................4-6
Capture/Compare Timer Interrupt. .....................................................4-6

MC68HC05P1

TABLE OF CONTENTS (Continued)
Paragraph
Number

5.1
5.2

Title
Section 5
Memory

Page
Number

Memory Map ...................................................................................................5-1
Data-Retention Mode ....................................................................................5-4

Section 6
Capture/Compare Timer
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.3
6.4
6.5
6.6
6.7
6.8

Timer Counter.................................................................................................6-2
Timer Counter Register (TCNT) .........................................................6-3
Alternate Counter Register (ALTCNT) .............................................. 6-3
Timer Functions..............................................................................................6-4
Input Capture .........................................................................................6-4
Output Compare ....................................................................................6-5
Input Capture Register (ICR) ........................................................................6-5
Output Compare Register (OCR) ................................................................6-6
Timer Status Register (TSR) ........................................................................6-7
Timer Control Register (TCR) ......................................................................6-8
Timer during WAIT Mode ..............................................................................6-9
Timer during STOP Mode ............................................................................6-9

Section 7
Self-Check Mode
7.1·
7.2

Self-Check Circuit..........................................................................................7-1
Self-Check Results ........................................................................................7-1

Section 8
Electrical Specifications
8.1
8.2
8.3
8.4
8.5
8.6
8.7

Maximum Ratings ..........................................................................................8-1
Thermal Characteristics................................................................................8-1
Power Considerations ..................................................................................8-2
DC Electrical Characteristics (Voo = 5.0 Vdc) .......................................... 8-3
DC Electrical Characteristics (Voo = 3.3 Vdc) .......................................... 8-4
Control Timing (Voo = 5.0 Vdc) ...................................................................8-7
Control Timing (Voo = 3.3 Vdc) ...................................................................8-9

MC68HC05P1

MOTOROLA

v

TABLE OF CONTENTS (Concluded)
Paragraph
Number

Title

Page
Number

Section 9
Mechanical Specifications
9.1
9.2

Dual-In-Line Package (DiP) .........................................................................9-1
Small Outline Integrated Circuit (SOIC) ....................................................9-2

Section 10
Ordering Information
10.1
ROM Pattern Media .......................................................................................10-1
10.1.1
Flexible Disks ..................... ~ ..................................................................10-1
10.1.2
EPROMs .................................................................................................10-2
10.2
ROM Pattern Verification ..............................................................................10-2
10.2.1
Verification Media .................................................................................10-2
10.2.2
ROM Verification Units (RVUs) ...........................................................10-2
10.3
MC Order Numbers .......................................................................................10-2

MOTOROLA

vi

MC68HC05P1

LIST OF FIGURES
Figure
Number

Title

Page
Number

1-1

MC68HC05P1 Block Diagram ....................................................................1-2

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10

Pin Assignments ............................................................................................2-1
Crystal/Ceramic Resonator Connections ..................................................2-3
External Clock Source Connections ..........................................................2-3
RC Oscillator Connections ...........................................................................2-4
RC Oscillator Frequency vs Resistance .....................................................2-4
Parallel I/O Port Circuit. .................................................................................2-6
Port A Data Register and DDRA. .................................................................2-7
Port B Data Register and DDRB..................................................................2-7
Port C Data Register and DDRC .................................................................2-8
Port D Data Register and DDRD .................................................................2-8

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9

CPU Block Diagram ......................................................................................3-1
Programming ModeL .....................................................................................3-2
Accumulator (A) ..............................................................................................3-2
Index Register (X) ..........................................................................................3-3
Stack Pointer (SP) .........................................................................................3-3
Program Counter (PC) ..................................................................................3-4
Condition Code Register (CCR) ..................................................................3-4
STOP Function Flowchart ............................................................................3-24
WAIT Function Flowchart..............................................................................3-26

4-1
4-2
4-3

Interrupt Stacking Order ...............................................................................4-3
Reset and Interrupt Flowchart......................................................................4-4
Extemallnterrupt Logic.................................................................................4-5

5-1
5-2

MC68HC05P1 Memory Map .......................................................................5-2
I/O and Control Register Summary.............................................................5-3

6-1
6-2
6-3

Capture/Compare Timer Block Diagram ...................................................6-1
16-Bit Counter Reads ....................................................................................6-2
Timer Counter Register (TCNT) ..................................................................6-3

MC68HC05P1

MOTOROLA
vii

LIST OF FIGURES (Concluded)
Figure
Number

Title

Page
Number

6-4
6-5
6-6
6-7
6-8
6-9
6-10

Alternate Counter Register (ALTCNT) .......................................................6-3
Input Capture Operation ...............................................................................6-4
Output Compare Operation ..........................................................................6-5
Input Capture Register (ICR) ........................................................................6-5
Output Compare Register (OCR) ................................................................6-6
Timer Status Register (TSR) ........................................................................6-7
Timer Control Register (TCR) ......................................................................6-8

7-1

Self-Check Circuit. .........................................................................................7-2

8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10

Test Load .........................................................................................................8-2
Typical High-Side Driver Characteristics ..................................................8-5
Typical Low-Side Driver Characteristics ...................................................8-5
Typical Supply Current vs Clock Frequency ............................................ 8-6
Maximum Supply Current vs Clock Frequency ........................................8-6
TCAP Timing ...................................................................................................8-7
STOP Recovery Timing ................................................................................8-8
External Interrupt Timing ..............................................................................8-8
Power-On Reset Timing ................................................................................8-10
External Reset Timing ...................................................................................8-10

9-1
9-2

Case 710-02 Dimensions ............................................................................9-1
Case 751 F-02 Dimensions ..........................................................................9-2

MOTOROLA
viii

MC68HC05P1

LIST OF TABLES
Table
Number

Title

Page
Number

2-1

I/O Pin Functions ............................................................................................2-6

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13

Inherent Addressing Instructions ................................................................3-7
Immediate Addressing Instructions ............................................................3-8
Direct Addressing Instructions .....................................................................3-9
Extended Addressing Instructions ..............................................................3-10
Indexed Addressing Instructions.................................................................3-12
Relative Addressing Instructions.................................................................3-13
Register/Memory Instructions ......................................................................3-14
Read-Modify-Write Instructions ...................................................................3-15
Jump and Branch Instructions .....................................................................3-16
Bit Manipulation Instructions........................................................................3-16
Control Instructions........................................................................................3-1 7
Instruction Set.................................................................................................3-19
Opcode Map ...................................................................................................3-23

7-1

Self-Check Results ........................................................................................7-1

8-1
8-2
8-3
8-4
8-5
8-6

Maximum Ratings ..........................................................................................8-1
Thermal Characteristics................................................................................8-1
DC Electrical Characteristics (Voo = 5.0 Vdc) .......................................... 8-3
DC Electrical Characteristics (Voo = 3.3 Vdc) ..........................................8-4
Control Timing (Voo = 5.0 Vdc) ...................................................................8-7
Control Timing (Voo = 3.3 Vdc) ...................................................................8-9

10-1

MC Order Numbers .......................................................................................10-2

MC68HC05P1

MOTOROLA
ix

MOTOROLA

x

MC68HC05P1

SECTION 1
INTRODUCTION
The MC68HC05P1 high-density complementary metal-oxide semiconductor
(HCMOS) microcontroller unit (MCU) is a member of the popular M68HC05
Family of microcontrollers. This high-performance, low-cost MCU is a complete
system on a single chip. The MCU features include the following:
o
o
o
o

o

•
o

o
o

•
•
o
o

G

Popular M68HC05 Central Processor Unit (CPU)
Memory-Mapped Input/Output (I/O) Registers
2112 Bytes of User ROM Including 16 User Vector Locations
128 Bytes of User Static Random Access Memory (SRAM) (Contents
Saved in Data-Retention Mode)
20 Bidirectional I/O Lines plus One Fixed Input and One Timer Output
Fully Static Operation (No Minimum Clock Speed)
On-chip Oscillator with Crystal and Resistor/Capacitor (RC) Mask Options
16-Bit Capture/Compare Timer
Self-Check Mode
Power-Saving STOP, WAIT, and Data-Retention Modes
Single 3.0-Volt to 5.5-Volt Power Requirement
8 x 8 Unsigned Multiply Instruction
28-pin Dual-In-Line Package (DIP) or Small Outline Integrated Circuit
(SOIC)
Edge Sensitive or Edge- and Level-Sensitive External Interrupt Trigger
Mask Options

Figure 1-1 shows the structure of the MC68HC05P1 MCU.

MC68HC05P1

INTRODUCTION

MOTOROLA
1-1

<
z
0

;::
()
w
a:
5

ROM - 2112 BYTES

<

<

Ii:
0

"-

!;(

(2K +48 + 16)

0

PB7
PB6
PB5

SELF-CHECK ROM - 240 BYTES
IXl

z

0

;::
()

RAM -128 BYTES

W

a:

5

<

PA7
PA6
PAS
PM
PA3
PA2
PA1
PAO

IXl
I-

a:
0

"-

!;(
0

PC7
PCG
PC5
PC4
PC3
PC2
PC1
PCO

M68HC05CPU
CPU REGISTERS

I

ACCUMULATOR

I

I

INDEX REGISTER

I

101010101011111 STACK POINTER I
PROGRAM COUNTER
10I 0101
I
CONDITIONCODEREGISTERl 111111H IIIN Iz Ic I

PD7rrCAP
PD5
0

OSC1

Ii:
0

"-

OSC2

VDD~
VSS

16-BIT
CAPTURE/COMPARE
TIMER SYSTEM

POWER

TCMP

'-------'

Figure 1-1. MC68HC05P1 Block Diagram

MOTOROLA
1-2

INTRODUCTION

MC68HC05P1

SECTION 2
PIN DESCRIPTIONS
This section describes the functions of the MC68HC05P1 pins.
shows the pin assignments.

PA4
PA3
PA2
PA1
PAO
PB5
PB6
PB7

Vss

6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Figure 2-1

Voo
OSC1
OSC2
TCAP/P07
TCMP
P05
PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

Figure 2-1. Pin Assignments

2.1 VDD and Vss
Power is supplied to the MCU through VDD and Vss. VDD is the power supply,
and Vss is ground. The MCU operates from a single 5-volt (nominal) power
supply.
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power
supply bypassing at the MCU. Bypass capacitors should have good
high-frequency characteristics and be as close to the MCU as possible.
Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.

MC68HC05P1

PIN DESCRIPTIONS

MOTOROLA
2-1

2.2 OSC1 and OSC2 (Oscillator Inputs)

OSC1 and OSC2 are the control connections for the on-chip oscillator. The
OSC1 and OSC2 pins can accept the following:
•
•
•
•

A crystal (Refer to Figure 2-2.)
A ceramic resonator (Refer to Figure 2-2.)
An external clock signal connected to OSC1 (Refer to Figure 2-3.)
A resistor between OSC1 and OSC2 to form an RC circuit with an
internal capacitor (Refer to Figure 2-4 for connections and Figure 2-5 for
.
resistance-frequency relationship.)

A factory-set mask option selects either a crystal/ceramic resonator or a resistor
as the frequency-determining element. The frequency (fose) of the oscillator
connected to OSC1 and OSC2 is divided by two to produce the internal
operating frequency, fop.

2.2.1 Crystal

The circuit in Figure 2-2 shows a typical crystal oscillator circuit for an AT-cut,
parallel resonant crystal. Follow the crystal supplier's recommendations, as the
crystal parameters determine the external component values required to
provide maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray layout capacitances.
Mount the crystal and components as close as possible to the input pins to
minimize output distortion and start-up stabilization time.
2.2.2 Ceramic Resonator

A ceramic resonator can be used in place of the crystal in cost-sensitive
applications. The circuit in Figure 2-2 can be used for a ceramic resonator.
Follow the resonator manufacturer's recommendations, as the resonator
parameters determine the external component values required to provide
maximum stability and reliable starting. The load capacitance values used in
the oscillator circuit design should include all stray layout capacitances.

MOTOROLA
2-2

PIN DESCRIPTIONS

MC68HC05P1

05C1

05C2
4.7MO

XTAL

D
37pF

37pF

l--

l--

Figure 2-2. Crystal/Ceramic
Resonator Connections

2.2.3 External Clock
An external clock from another CMOS-compatible device can be connected to
the OSC1 input, with the OSC2 input not connected, as shown in Figure 2-3.
When ordering the MCU to use with an external clock, specify the
crystal/ceramic resonator mask option.

05C1

05C2

UNCONNECTED

<

L..-_ _ _ _ _ _

EXTERNAL
CM05CLOCK

Figure 2-3. External Clock Source Connections

MC68HC05P1

PIN DESCRIPTIONS

MOTOROLA
2-3

2.2.4 RC Oscillator
With this option, a resistor is connected to the oscillator pins as shown in Figure
2-4. The relationship between R and fop is shown in Figure 2-5. Because the
accuracy of the RC oscillator is ±50%, the nominal design frequency must be
limited to 66% of the maximum frequency. This ensures that the operating
frequency remains below the upper limit. This 50% tolerance only allows for the
MCU variation. Make additional allowance for the tolerances of any external
components. Operation with a crystal (or ceramic resonator) is preferred.

OSCl

OSC2

R

Figure 2-4. RC Oscillator Connections
10 MHz
N

5 MHz

+

~

2 MHz

~

1 MHz

w

is

.......

r-... ......

0.5MHz

......

IE

:.:: 200 KHz

.....
~ ....

8

o 100KHz
~
~

50KHz
20KHz
10KHz
lK

2K

5K

10K

20K

SOK

lOOK

200K

SOOK

1M

EXTERNAL RESISTOR (n)

Figure 2-5. RC Oscillator Frequency vs Resistance

MOTOROLA
2-4

PIN DESCRIPTIONS

MC68HC05P1

2.3 RESET
A logical zero on the RESET pin forces the MCU to a known start-up state.
(Refer to 4.1 Resets for more information.)

2.4 External Interrupt Request (IRQ)
The IRQ pin allows the application of asynchronous external interrupt requests
to the MCU. Two different external interrupt triggering sensitivities are
available. The factory-set mask options are the following:
e

•

Negative edge-sensitive triggering only
Both negative edge-sensitive triggering and level-sensitive triggering

Refer to 4.2 Interrupts for more information.
The IRQ pin is also used in changing operating modes.
7.1 Self-Check Circuit.)

(Refer to

2.5 1/0 Port Function

The MCU's 20 1/0 pins form four I/O ports. Each I/O pin is programmable as an
input or an output. The contents of the data direction register (DDR) determine
the data direction for the port. Writing a logical one to a DDR bit enables the
output buffer for that pin; a logical zero disables the output buffer. On reset, all
implemented DDR bits are initialized to logical zero to put the pins in the input
mode.

NOTE
Connect any unused inputs and I/O pins to an appropriate logical
level (e.g., either VDD or Vss). Although the I/O ports do not
require termination for proper operation, termination is
recommended to reduce the possibility of electrostatic damage.

A reset does not initialize the four port data registers. The data registers for
ports A, B, C, and D are at addresses $0000, $0001, $0002, and $0003,
respectively. To avoid undefined levels, write the data registers before writing
the DDR bits.

MC68HC05P1

PIN DESCRIPTIONS

MOTOROLA
2-5

When a pin is programmed as an output, reading the associated port bit actually
reads the value of the output data latch and not the voltage on the pin itself.
When a pin is programmed as an input, reading the port bit reads the voltage
level on the I/O pin. The output data latch can always be written, regardless of
the state of its DDR bit. (Refer to Figure 2-6 for typical port circuitry, and Table
2-1 for a summary of I/O pin functions.)

[1 [ Output buffer. Enables latched output to drive pin when DDR bit is 1 (output mode).
[2] Input buffer. Enabled when DDR bit is 0 (input mode).
[3] Input buffer.. Enal;lled when DDR bit is 1 (output mode).

Figure 2-6. Parallel I/O Port Circuit

Table 2-1. I/O Pin Functions
R/W
0
0
1
1

DDR
0
1
0
1

I/O Pin Functions
The 110 pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch, which drives the 110 pin.
The state of the 110 pin is read.
The 110 pin is in output mode. The output data latch is read.

NOTE: RN.J is an internal signal.

MOTOROLA

2-6

PIN DESCRIPTIONS

MC68HC05P1

2.6 Port A
PA7-PAO form an 8-bit general-purpose bidirectional I/O port. The contents of
data direction register A (DDRA) determine whether each pin is an input or an
output. Figure 2-7 shows the port A data register and DDRA.

Bit7

6

4

3

BitO

2

II

$0000 PORTA

PORT OUTPUT REGISTER STATES NOT CHANGED BY RESET

RESET CONDITION

I DDRA71 DDRASI DDRA51 DDRMII DDRA31 DDRA21 DDRA1 I DDRAO I $0004 DORA
0

0

0

0

0

0

0

0

RESET CONDITION:
INPUT MODE

1/0

I/O

1/0

1/0

VO

VO

VO

VO

PIN DIRECTIONS

PA7

PAS

PA5

PM

PA3

PA2

PA1

PAO

PIN NAMES

Figure 2-7. Port A Data Register and DORA

2.7 Port B
PB7-PB5 form a 3-bit general-purpose bidirectional I/O port. The contents of
data direction register B (DDRB) determine whether each pin is an input or an
output. Figure 2-8 shows the port B data register DDRB. Bits 4-0 of these
registers are not implemented.

Bit 7

6

5

4

:9 \1 I

3

2

Bit 0

1

g :I( %1 I :fQ

:~f

I i9 ::1

PORT OUTPUT REGISTER STATES NOT CHANGED BY RESET

o

0

$0001 PORTS
RESET CONDITION

0

RESET CONDITION:
INPUT MODE

VO

VO

VO

PIN DIRECTIONS

PB7

PB6

PB5

PIN NAMES

Figure 2-8. Port B Data Register and DDRB

MC68HC05P1

PIN

DESCRIPTIONS

MOTOROLA
2-7

2.8 Port C
PC7-PCa form an 8-bit general-purpose bidirectional I/O port. The contents of
data direction register C (DDRC) determine whether each pin is an input or an
output. Figure 2-9 shows the port C data register and DDRC.

Bit 7

S

5

4

3

2

Bit 0

II

$0002 PORTC

PORT OUTPUT REGISTER STATES NOT CHANGED BY RESET

RESET CONDITION

IDDRC71 DDRCsl DDRC51 DDRC411 DDRcal DDRC21 DDRC1 IDDRCO I $0006
0

0

0

0

0

0

0

OORC

0

RESET CONDITION:
INPUT MODE

VO

VO

VO

VO

110

110

110

I/O

PIN DIRECTIONS

PC7

PCS

PC5

PC4

pca

PC2

PC1

PCO

PIN NAMES

Figure 2·9. Port C Data Register and DDRC

2.9 Port D and Timer Capture (TCAP)
PD7/TCAP and PD5 form a 2-bit special-function I/O port. The PD7ITCAP pin
serves both as the edge-detecting input capture line for the capture/compare
timer and as a general-purpose digital input. PD7ITCAP can be used as a
digital input even when the timer is using it as the input capture pin. There is no
output driver associated with the PD7ITCAP pin. PD5 is a general-purpose
digital I/O pin whose direction is controlled by bit 5 of DDRD. Figure 2-1 a shows
the port D data register and DDRD.

Bit 7

S

5

!t:MItW:i1

4

3

2

1

Bit 0

IlttEMllwmm:l'MlfmltltiW@]
INH
!Xl
IX1
IX
?C=O
REL
Mn<-O
DIR(bO)
DIR(bl)
DIR(b2)
DIR(b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR(b7)
?C=I
REL
Description

,

42"
.7

REL
REL
REL
REL

27
28
29
22

?C=O
?IRO=I

REL
REL

24
2F

Branch if 1RQ pin low
?TRo=O
Bit test accumulator contents with (A)·(M)
memory contents

BLOrel
BLSrel
BMCrel
BMlrel

Branch if lower
Branch if lower or sarne
Branch if interrupt mask clear
Branch if minus

BMSrel
BNErel

Branch if interrupt mask set
Branch if not equal
Branch if plus

BPLrel

MC68HC05P1

38
48
58
68
78
37
47
57
67
77
24
II
13
15
17
19
IB
10
1F
25

?Z=I
?H=O
?H=I
?C+Z_O

BIT rei

BILrel

,

Machine Coding
(hexadecimal)
Opcode Operand
A9
ii
B9
dd
C9
hh II
D9
ee If
E9
If
F9
AB
ii
BB
dd
CB
hh II
DB
ee If
EB
If
FB
A4
ii
dd
B4
C4
hh II
D4
ee If
E4
If
F4

?C=I
?C+X=I
?I=O
?N=I
?I=O
?Z=O
?N=O

REL

2E

IMM
DIR
EXT
IX2
IXI
IX
REL
REL
REL
REL
REL
REL

AS
B5
C5
D5
E5
F5
25
23
2C
2B
2D

REL

26
2A

CENTRAL PROCESSOR UNIT

dd

If
dd

If

rr
dd
dd
dd
dd
dd
dd
dd
dd

rr
rr
rr
rr
rr
rr
rr
rr
ii
dd
hh II
ee ff
If

rr
rr
rr
rr
rr
rr
rr

H

Condition
Code
I
N Z

C

~

-

Cycles
2
3
4
5
4
3
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
3
5
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
2
3
4
5
4
3
3

3
3
3
3

3
3

~

~

~

~

;

;

~

-

-

;

;

-

-

-

;

;

~

- -

;

;

;

- - - - - - - - -

-

- - - - - - - - - - - - - - - - - - - - - - - - - ; ; -

- - - - - - - - - - - - - - - - - - - -

-

MOTOROLA
3-19

Table 3·12. Instruction· Set (Sheet 2 of 4)
Source
Form(s)

Operation

Branch always
BRA rei
BRClR n opr rei Branch if bit n clear

BRNrel
Branch never
BRSET n opr rei Branch if bit n set

BSET nopr

Setbitn

BSRrel

Branch to subroutine

CLC
CLI
ClRopr
CLRA
ClRX
CLR opr
CLRopr
CMPopr

Clear carry bit
Clear Interrupt mask
Clear register

COMopr
COMA
COMX
COMopr
COMopr
CPXopr

Complement register
contents
(ones complement)

DECopr
DECA
DECX
DECopr
DECopr

Compare accumulator
contents with memory
contents

Addressing
Mode for
Operand
?, =,
REl
DIR(bO)
?Mn=O
DIR(b,)
DIR (b2)
DIR(b3)
DIR(b4)
DIR(b5)
DIR(b6)
DIR(b7)
?,=O
REl
DIR(bO)
?Mn='
DIR(b,)
DIR (b2)
DIR(b3)
DIR(b4)
DIR(b5)
DIR(b6)
DIR(b7)
Mn<- ,
DIR (bO)
DIR(b')
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR(b6)
DIR(b7)
PC <- (PC) + 2; push (PCl) REl
SP <- (SP) - '; push (PCH)
SP<-(SP)-,
PC <-(PC) + rei
C<-O
INH
1<-0
INH
DIR
f':I <-!?.?
A <-$00
INH
X<- $00
INH
M<-$OO
M <-$00
IX'
IX
(A)-(M)
IMM
DIR
EXT
IX2
IX,
IX
M <-}'I~ $FF (M)
DIR
A<-A=$FF-(A)
INH
X<-X=$FF-(X)
INH
M<-liiI=$FF-(M)
Description

M <-liiI= $FF-(M)
Compare index register
contents with memory
contents

Decrement register
contents

MOTOROLA
3-20

(X)-(M)

IM<-(M)-'
A<-(A)-,
X<-(X)-,
M<-(M)-'
M <-(M) -,

IX'
IX
IMM
DIR
EXT
IX2
IX'
IX
DIR
INH
INH
IX'
IX

Machine Coding
(hexadecimal)
Opcode Operand
20
rr
dd rr
0'
03
dd rr
05
dd rr
07
dd rr
09
dd rr
OB
dd rr
OD
dd rr
OF
dd rr
rr
2'
00
dd rr
02
dd rr
04
dd rr
06
dd rr
08
dd rr
OA
dd rr
OC
dd rr
OE
dd rr
dd
'0
dd
'2
dd
'4
dd
'6
18
dd
,A
dd
,C
dd
,E
dd
AD
rr

98
9A
3F
4F
SF
6F
7F

dd

If

A'
B,
C,
D,
E,
F,

ii
dd
hh II
ee If
If

33
43
53
63
73
A3
B3
C3
D3
E3
F3
3A
4A
5A
6A
7A

dd

CENTRAL PROCESSOR UNIT

If

ii
dd
hh II
ee If
If
dd

If

H

Condition
Code
I
N Z

3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6

-

-

2
2
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5

-

Cycles

- -

--

- - - - -

-

-

C

~

-

-

-

~

- - - -

- - -

- -

- - - 0 - -,
- - 0

-

- -

~

~

~

-

-

~

~

,

-

-

~

~

~

-

-

~

;

-

0

MC68HC05P1

Table 3-12. Instruction Set (Sheet 3 of 4)
Source
Form(s)

OperatIon

DescriptIon

EORopr

A <- (A) Ell (M)
Exclusive OR accumulator
contents with memory contents

INCopr
INCA
INCX
INCopr
INCopr
JMPopr

Increment memory or register
contents

IY'<-J!"1) + 1
A<-(A) +1
X<-(X) +1
M<-(M) +1
M<-(M) + 1

Unconditional jump

PC <- jump address

JSRopr

Jump to subroutine

PC<- (PC) +n (n = 1, 2, or3)
Push (PCL): SP <- (SP) - 1
Push (PCH): SP <- (SP) - 1
PC <- conditional address

LDAopr

Load accumulator with
memory contents

A <-(M)

LDXopr

Load index register with
memory contents

X ... (M)

LSLopr
LSLA
LSLX
LSLopr
LSL opr
LSRopr
LSRA
LSRX
LSRopr
LSRopr
MUL
NEGopr
NEGA
NEGX
NEG opr
NEG opr
NOP
ORAopr

ROLopr
ROLA
ROLX
ROLopr
ROLopr

Logical shift left

,
IIDH

I I I I I I I 1+-0

Logical shift right

,
o~

b7

Unsigned multiply
Negate memory or register
contents (twos complement)

00

b1

I I I I I I I t-l@]
00

X :A<-(x) x (A)
M <- ~!"1) ~.~~o - (M)
A <- -(A) = $00 - (A)
X <- -(X) = $00 - (X)
M <- -(M) = $00 - (M)
M <- -(M) = $00 - (M)

No operation
[A<- (A) + (M)
Inclusive OR accumulator
contents with memory contents

Rotate left through carry

MC68HC05P1

LID=! [ [ [ III [;J
b7

00

Addressing
Mod. for
Operand
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
INH
DIR
INH
INH
IX1
IX
INH
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX

Machine Coding
(hexadecimal)
Opcode Operand
A8
ii
B8
dd
hh II
C8
D8
ee If
E8
If
F8
3C
dd
4C
5C
If
6C
7C
BC
dd
CC
hh II
ee If
DC
EC
If
FC
dd
BD
CD
hh II
DD
ee If
ED
If
FD
A6
ii
dd
B6
C6
hh II
D6
ee If
If
E6
F6

AE

ii

BE
CE

dd
hh II
ee If

DE
EE
FE
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
9D

If

M
SA

Ii

dd

If
dd

If

dd

dd
hh II
ee If

EA

If

C

- -

: :

-

-

:

:

-

-

-

- -

-

- -

-

-

-

- - : :

-

-

-

:

:

-

-

:

: :

-

-

0

:

:

0

- - -

0

-

-

- : : :

6
5
2
2
3
4
5
4

-

- - -

:

~

-

-

-

~

~

~

3

FA

CENTRAL PROCESSOR UNIT

H

2
3
4
5
4
3
5
3
3
6
5
2
3
4
3
2
5
6
7
6
5
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
11
5
3

Condition
Code
I
N Z

3
If

CA
DA

39
49
59
69
79

Cycles

dd

5

3
3
If

6
5

MOTOROLA
3-21

Table 3·12. Instruction Set (Sheet 4 of 4)
Source
Form(s)

Operation

RORopr
RORA
RORX
RORopr
RORopr

Rotate right through carry

RSP
RTI

Reset stack pointer
Return lrom interrupt

L;ill
.7

RTS

Return Irom subroutine

SBCopr

Subtract memory contents and
carry bit Irom accumulator
contents

SEC
SEI
STAopr

STOP
STXopr

SUB opr

Set carry bit
Set interrupt mask
Store accumulator contents in
memory

Enable fRO; stop oscillator
Store index register contents in
memory

II I I IH@}J

Software interrupt

TAX

Transfer accumulator contents
to index register

TSTopr
TSTA
TSTX
TSTopr
TSTopr
TXA

Test memory, accumulator, or
index register contents for
negative or zero

SP<- $OOFF

SP ~ W~l + 1; pul,: WCt?
SP<- SP +1;pull PCl
A<-(A)-(M)-l;

Il; <-1
1.... 1
M .... (A)

M .... (X)

Addressing
Mode for
Operand
DIR
INH
INH
IXl
IX
INH
INH

(M)-$OO

Machine Coding
(hexadecimal)
Opcode Operand
36
dd
46
56
66
If
76

9C
80

Cycles
H

5
3
3
6
5

-

Condition
Code
I
N Z

C

;

;

-

;

From Stack

2
9

;

;

;

;

3:

INH

81

6

-

- - - -

IMM
DIR
EXT
.1X2
IXl
IX
INH
INH
DIR
EXT
1X2
IX1
IX
INH
OIR
EXT
1X2
IX1
IX
IMM
OIR
EXT
1X2
IX1
IX
INH

A2

ii

2

-

-

B2
C2
D2
E2
F2
99
9B
B7
C7
07
E7
F7
8E

dd
hh II
ee If

3

PC .... (PC) + 1; push (~~.L)
SP .... (SP) -1; push (PCH)
SP <- (SP) -1; push (X)
SP <- (SP) - 1; push (A)
SP <- (SP) - 1; push (CCR)
SP<-(SP)-1; f <-1
PCH <- ($xFFC)
PCl .... ($xFFOi (Vector fetch)
X .... (A)
INH

Transfer index register contents A .... (X)
to accumulator
Enable interrupts; halt CPU

MOTOROLA
3-22

bO

I::il' <- (::il') + 1; PUll (l;l;H)
SP<- (SP) + 1; pull (A)
SP<- (SP) + 1; pull (X)
SP <- (SP) + 1; pull (PCH)
SP <- (SP) + 1; pull (PCl)

Subtract memory contents from A .... (A)-(M)
accumulator contents

SWI

WAIT

Description

BF
CF
OF
EF
FF
AO
BO
CO
DO
EO
FO
83

If

dd
hh II
ee If

If

dd
hh II
ee If

If
ii
dd
hh II
ee If

If

97

DIR
INH
INH
IX1
IX
INH

3D
40
50
60
70
9F

INH

8F

CENTRAL PROCESSOR UNIT

4
5
4
3
2
2
4
5
6
5
4
2
4
5
6
5
4
2
3
4
5
4
3
10

2
dd

If

4
3
3
5
4
2
2

;

;

3:

- 1 - - ;

3:

-

1

- 0
- -

;

;

-

-

-

3:

3:

3:

-

1

- -

-

- - - - - - 3: 3: 0

- -

-

-

-

-

-

-

-

0

MC68HC05P1

:s::

o

(Xl

I

oo

01

-a

HI
LO

a

0000
1
0001
2
0010
3
0011

4

o
m
z

0100
5

:t1

0101
6

-oj

,»

"C
:t1

o

o
m
en
en

o

:t1

c:
Z

::::j

:s::

~:0

'fa
1\),

w»

CJJ

Table 3-13. Opcode Map

OJ

0110

7
0111
8
1000
9

Bit-Manipulation
DIR
_ DIR
a
1
0000
0001
5

BRSETO
OIR
3
5
BRCLRO
OIR
3
5
BRSETl
OIR
3
5
BRClRl
OIR
3
5
BRSET2
OIR
3
5
BRClR2
OIR
3
5
BRSET3
OIR
3
5
BRClR3
OIR
3
5
BRSET4
OIR
3

5
BSETO
2
OIR
5
BClRO
OIR
2
5
BSETl
2
OIR
5

BSClRl
2
DlR
5

BSET2
2
OIR
5

BClR2
2
OIR
5
BSET3
2
OIR
5

BClR3
OIR
2
5
BSET4
2
OIR

5

5

BRClR4 BClR4
OIR
OIR 2
1001 3
5
5
A
BRSET5 BSET5
OIR
OIR
2
1010 3
5
5
B
BRClR5 BClR5
OIR 2
OIR
1011 3
5
5
C
BRSET6 BSET6
DlR 2
OIR
1100 3
5
5
u
BRClR6 BClR6
OIR
DlR 2
1101 3
5
5
E
BRSET7 BSET7
OIR 2
OIR
1110 3
5
5
F
BRClR7 BClR7
OIR
OIR 2
1111 3

Branch
REL
2
0010
3
BRA
2
REl
3
BRN
2
REL
3
BHI
2
REL
3
BlS
REL
2
3
BCC
2
REL
3
BCS
2
REL
3
BNE
2
REL

Read-Modify-Write
Control
DIR
INH
INH
IXl
IX
INH
INH
5
3
4
6
a
9
7
0011
0100
0101
0110
0111
1000
1001
3
6
5
9
5
NEGA
NEG
NEG
RTI
NEG
OIR 1
INH
2
IXl 1
IX 1
INH
2

IMM
A
1010
2

6

1

RTS
INH

2

11
MUl
1
INH
5
3
3
6
5
10
COMA
COM
COMX
COM
SWI
COM
2
OIR 1
INH 1
INH 2
IXl 1
IX 1
INH
5
3
3
6
5
lSR
lSRA
LSRX
lSR
lSR
2
OIR 1
INH 1
INH 2
IXl 1
IX

2
2
2
2

5
3
3
ROR
RORA
RORX
OIR 1
INH 1
INH
3
5
3
3
ASRA
BEQ
ASR
ASRX
2
REL 2
OIR 1
INH 1
INH
5
3
3
3
BHCC
lSl
lSlA
lSlX
REL 2
OIR 1
INH 1
INH
2
3
5
3
3
BHCS
ROl
ROlA
ROlX
2
REL 2
OIR 1
INH 1
INH
3
5
3
3
BPl
DEC
DECA
DECX
2
REL 2
OIR 1
INH 1
INH
3
BMI
REL
2
3
5
3
3
BMC
INC
INCA
INCX
REL 2
OIR 1
INH 1
2
INH
3
3
3
4
TSTA
TSTX
BMS
TST
OIR 1
2
REL 2
INH 1
INH
3
Bil
REL
2
3
3
5
3
ClRA
BIH
ClR
ClRX
2
REL 2
OIR 1
INH 1__ .'!:!.!:!.

2

6
5
ROR
ROR
IXl 1
IX
6
5
ASR
ASR
2
IXl 1
IX
6
5
lSl
lSl
2
IXl 1
IX
6
5
ROl
ROl
1
IX

2

6

2

2
1
1
1

5

DEC
DEC
INH 1
IX

1
1

6

2

INC
INC
INH 1
IX
6

2

5
1

4

TST
TST
INH 1
IX

1

2
TAX
INH
2
ClC
INH
2
SEC
INH
2
CLI
INH
2
SEI
INH
2
RSP
INH
2
NOP
INH

2
STOP
1
INH
6
5
2
2
WAIT
TXA
ClR
ClR
INH 1
INH
2_'!'!..'::!. 1_ _...0.c!.....

~

DIR

2
SUB
IMM
2
CMP
IMM
2
SBC
IMM
2
CPX
IMM
2
AND
IMM
2
BIT
IMM
2
lDA
IMM

1~11

2
2
2
2
2
2
2

4

2
2
2
2
2

2
EOR
IMM
2
ADC
IMM
2
ORA
IMM
2
ADD
IMM

2
2
2
2
2

6

BSR
REL 2
2
lDX
IMM 2
2
2

Inherent
Immediate
Direct
Extended

REL
IX
IXl
IX2

Relative
Indexed, No Offset
Indexed, a-Bit Offset
Indexed, 16-Bit Offset

STA
OIR
3
EOR
OIR
3
ADC
OIR
3
ORA
OIR
3
ADD
OIR
2
JMP
OIR
5
JSR
OIR
3
lDX
OIR
4

2

STX
OIR

:.....
IX
F
1111

IHI LO
3

SUB
CMP
SBC

a

0
Q.

IX 0001
3
2

W

IX 0010
4
5
4
3
3
CPX
CPX
CPX
CPX
EXT 3
IX2 2
IXl 1
3
IX 0011
4
5
4
3
4
AND
AND
AND
AND
EXT 3
IX2 2
IXl 1
3
IX 0100
4
3
5
5
4
BIT
BIT
BIT
BIT
IX2 2
IXl 1
IX ~Q1.
3
EXT 3
----3
5
4
4
6
lDA
lDA
lDA
lDA
EXT 3
IX2 2
IXl 1
3
IX 0110
6
5
4
5
7
STA
STA
STA
STA
IX2 2
IXl 1
3
EXT 3
IX 0111
3
4
5
4
8
EOR
EOR
EOR
EOR
EXT 3
IX2 2
IXl 1
3
IX 1000
4
5
4
3
9
ADC
ADC
ADC
ADC
EXT 3
IX2 2
IXl 1
3
IX 1001
4
5
4
3
A
ORA
ORA
ORA
ORA
EXT 3
IX2 2
IXl 1
3
IX 1010
4
4
5
3
B
ADD
ADD
ADD
ADD
IXl 1
EXT 3
IX2 2
3
IX 1011
4
3
2
3
C
JMP
JMP
JMP
JMP
IX2 2
IXl 1
3
EXT 3
IX 1100
7
6
5
6
0
JSR
JSR
JSR
JSR
IXl 1
EXT 3
IX2 2
3
IX 1101
4
5
4
3
E
lDX
lDX
lDX
LOX
EXT 3
IX2 2
IXl 1
3
IX 1110
5
6
5
4
F
STX
STX
STX
STX
IXl 1
EXT 3
IX2 2
3
IX 1111

High Byte of Opcode In Hexadecimal
0

"C

CD

Q: ()

w

!---..!....!...!.Jl...".j..!H~i!!}.!!h~Byte of Opcode in Binary

Number of Cycles
Opcode Mnemonic
Number of Byles/Addressing Mode

-; 0

nl

IX 0000
3
1

lEGEND

ABBREVIATIONS FOR ADDRESSING MODES
INH
IMM
DIR
EXT

3
SUB
OIR
3
CMP
OIR
3
SBC
OIR
3
CPX
OIR
3
AND
OIR
3
BIT
OIR
3
lDA
OIR

Register/Memory
EXT
IX2
IXl
C
0
1101
1100
l lEl0
4
5
4
SUB
SUB
SUB
EXT 3
IX2 2
IXl 1
3
4
5
4
CMP
CMP
CMP
IX2 2
IXl 1
3
EXT 3
4
4
5
SBC
SBC
SBC
3
EXT 3
IX2 2
IXl 1

Low Byte of Opcode in Hexadecimal
Low Byte of Opcode in Binary

......
I

en
nl
::::I

0
"0
()

0

a.
CD

3

nl

-....

"0

-s:
0

: ::;
CD

0

0>

CD

I

0

0
01

'"U
......

::::I

en
.-

....
C

U

o·
::::I

!'>

(I)

:s:
nl

"C

3.5 Low-Power Modes
The following paragraphs describe the STOP and WAIT modes. (Refer also to
5.2 Data-Retention Mode.)

3.5.1 STOP Mode
The STOP instruction places the MCU in its lowest power-consumption mode.
In STOP mode, the internal oscillator turns off, halting all internal processing,
including capture/compare timer operation and computer operating properly
(COP) timer operation. (Refer to Figure 3-8.)

STOP OSCILlATOR
AND ALL CLOCKS.
CLEAR I-BIT IN CCR.

YES

(1) FETCH RESET VECTOR or
(2) SERVICE INTERRUPT.
a SAVE CPU REGS ON STACK
b. SET I-BIT IN CCR.
c. VECTOR TO INTERRUPT
SERVICE ROUTINE.

Figure 3-8. STOP Function Flowchart

MOTOROLA
3-24

CENTRAL PROCESSOR UNIT

MC68HC05P1

During STOP mode, the input capture interrupt enable bit (ICIE), the output
compare interrupt enable bit (OCIE), and the timer overflow interrupt enable bit
(TOlE) in the timer control register (TCR) are cleared to remove any pending
timer interrupt requests and to disable any further timer interrupts. The interrupt
mask (I bit) in the condition code register is cleared to enable external
interrupts. All other registers and memory locations remain unchanged. All I/O
lines remain unchanged. The MCU can be brought out of STOP mode only by
an external interrupt or a reset. An external interrupt automatically loads the
program counter with the contents of $1 FFA and $1 FFB, the locations of the
vector address of the interrupt service routine. A reset automatically loads the
program counter with the contents of $1 FFE and $1 FFF, the locations of the
vector address of the reset service routine.

3.5.2 WAIT Mode
The WAIT instruction places the MCU in an intermediate power-consumption
mode. All CPU action stops, but the capture/compare timer remains active. If
the AID converter is enabled, it is also active in WAIT mode. An interrupt from
the capture/compare timer can cause the MCU to exit WAIT mode. (Refer to
Figure 3-9.)
The COP timer is not disabled in WAIT mode. To prevent a timer reset, exit from
WAIT and reset the COP timer before timeout.

MC68HC05P1

CENTRAL PROCESSOR UNIT

MOTOROLA
3-25

(1) FETCH RESET VECTOR or
(2) SERVICE INTERRUPT.
a SAVE CPU REGS ON STACK.
b. SET I-BIT IN CCR.
c. VECTOR TO INTERRUPT
SERVICE ROUTINE.

Figure 3-9. WAIT Function Flowchart

During WAIT mode, the interrupt mask (I bit) in the condition code register is
cleared to enable interrupts. All other registers, memory locations, and 1/0 lines
remain in their previous states.

MOTOROLA

3-26

CENTRAL PROCESSOR UNIT

MC68HC05P1

SECTION 4
RESETS AND INTERRUPTS
This section describes CPU resets and interrupts.

4.1 Resets
A reset immediately stops execution of the current instruction. A reset forces the
internal address bus to a known starting address and forces certain control and
status bits to known conditions. The CPU can be reset in the following ways:
«I

o

Initial power-up (power-on reset)
An external, logical zero signal on the reset pin (RESET)

NOTE
The current instruction is the one already fetched and being
operated on.

The following internal actions occur as a result of a reset:
iii

•
•
•

•
•
•

MC68HC05P1

All implemented data direction register bits are cleared, so the
corresponding I/O pins become high-impedance inputs.
The stack pointer is loaded with $FF.
The interrupt mask (I-bit) is set, inhibiting interrupts, and the IRQ request
latch is cleared.
The capture/compare timer clock divider stages are cleared. The
capture/compare timer is loaded with $FFFC. The output compare bit
(TCMP) and the output level bit (OLVL) are cleared. All capture/compare
timer interrupt enable bits (ICIE, OCIE, and TOlE) are cleared to disable
timer interrupts.
The STOP latch is cleared to enable MCU clocks.
The WAIT latch is cleared to wake the CPU from the WAIT mode.
The program counter is loaded with the user-defined reset vector
address; the high byte of the program counter is loaded with the contents
of location $1 FFE, and the low byte of the program counter is loaded from
location $1 FFF.

RESETS AND INTERRUPTS

MOTOROLA

4-1

4.1.1 Power-On Reset (PaR)
A reset is generated on power-up when a positive transition occurs on VDD.
The POR is strictly for power-up conditions. It cannot be used to detect a drop in
the power supply voltage.
To allow the clock generator to stabilize, there is a 4064 teye (internal clock
cycle) delay after the oscillator becomes active. If the RESET pin is at logical
zero at the end of 4064 t eye , the CPU remains in the reset condition until RESET
goes to logical one.

4.1.2 External RESET Input
The CPU is reset when a logical zero is applied to the RESET input for a period
of one and one-half internal clock cycles (teyc). The RESET input consists of a
Schmitt trigger that senses the logic level at the RESET pin.
RESET is an input-only pin and does not become active (go to logical zero)
when a power-on reset occurs.

4.2 Interrupts
An interrupt temporarily stops normal processing so that some unusual event
can be processed. Unlike a reset, an interrupt does not stop the current
instruction. An interrupt is considered pending until the current instruction is
complete. There are three types of interrupts:
•

•

•

External interrupt - If the interrupt mask is a logical zero, and the
external interrupt pin (IRQ) goes to logical zero, then the CPU recognizes
an external interrupt.
Capture/compare timer interrupt - When the interrupt mask is a logical
zero, the CPU can recognize interrupts from the capture/compare timer.
If one of the three timer interrupt flags (ICF, OCF, TOF) in the timer status
register goes to logical one, and its corresponding interrupt enable bit
(ICIE, OCIE, TOlE) in the timer control register is a logical one, a timer
interrupt is requested.
Software interrupt - The software interrupt is an instruction executed
regardless of the state of the interrupt mask.

The following internal actions occur as a result of an interrupt:
•
•

MOTOROLA
4-2

CPU register contents are stored on the stack in the order PCl, PCH, X,
A,CCR.
The interrupt mask is automatically set to prevent additional interrupts.

RESETS AND INTERRUPTS

MC68HC05P1

•
•

An interrupt vector that causes processing to continue at the starting
address of the interrupt routine is fetched.
The RTI (return from interrupt) instruction causes the register contents to
be recovered from the stack in the order CCR, A, X, PCH, PCL. Normal
processing resumes.

Figure 4-1 shows the stacking and recovery sequence.
TOWARD LOWER ADDRESSES
(LOWEST STACK ADDRESS IS $OOCO)

.,---.------.-_1r"~_r___,_---r....;O_.

STACK ,..:-7
1

I I I

o

I I I P~OG C?UN~R HI~H

1

0

:

1

~ONDI!ION ?ODE~

0

P~OG~ C?UNT~R LO~

:

I

L..-...J..._.L..-..I...---J.'--..I...---J._.J....- - I

UNSTACK

.JJ.
TOWARD HIGHER ADDRESSES
(HIGHEST STACK ADDRESS IS $OOFF)

Figure 4-1. Interrupt Stacking Order
As each instruction is completed, the CPU checks for the presence of enabled
external interrupt requests and enabled timer interrupt requests. For an
external interrupt request to be recognized, the interrupt mask (I-bit) in the
condition code register (CCR) must be a logical zero. If the interrupt mask is set
or if no qualified interrupt request is pending, the processor fetches and
executes the next program instruction.
Recognition of a timer interrupt request requires two conditions: the interrupt
mask must be a logical zero, and the corresponding interrupt enable bit (OCIE,
ICIE, or TOlE) in the timer control register (TCR) must be a logical one. If the
interrupt mask is set, or if no qualified interrupt request is pending, the
processor fetches and executes the next program instruction.
If both an external interrupt and a capture/compare timer interrupt are pending
at the end of an instruction execution, the external interrupt is serviced first.
A software interrupt (SWI) is executed as an instruction, regardless of the state
of the interrupt mask. Figure 4-2 shows how interrupts relate to normal
instruction execution. CPU control logic determines the sequence of
operations.

MC68HC05P1

RESETS AND INTERRUPTS

MOTOROLA
4-3

YES

CLEAR IRQ
REQUEST
LATCH.

STACK
PCL, PCH. X. A. CCR.
NO

SET I BIT IN CCR.
LOAD PC FROM VECTOR:
SWI: $1 FFC.$l FFD
IRQ: $1 FFA. $1 FFB
TIMER: $1 FF8. $1 FF9

>~~~

RESTORE REGISTERS
FROM STACK
I----~
CCR. A. X. PCH. PCL

EXECUTE
INSTRUCTION.

Figure 4-2. Reset and Interrupt Flowchart

MOTOROLA
4-4

RESETS AND INTERRUPTS

MC68HC05P1

4.2.1 External Interrupt
The CPU recognizes an external interrupt when the external interrupt pin (IRQ)
goes to a logical zero while the interrupt mask (I-bit) is at logical zero. At this
time, a small synchronization delay occurs, and a logical one is latched
internally to signify that an external interrupt has been requested. When the
CPU completes its current instruction, the interrupt latch is tested. If the interrupt
latch contains a logical one, and the interrupt mask is a logical zero, the CPU
then begins the interrupt sequence. The current state of the CPU is pushed
onto the stack, and the interrupt mask is set to inhibit further interrupts until the
present one is serviced. The address of the interrupt service routine is
contained in memory locations $1 FFA and $1 FFB.
An edge sensitive and level sensitive external interrupt trigger, and an
edge sensitive only external interrupt trigger are available as factory-set mask
options. Figure 4-3 shows the internal logic of with this mask option. The
interrupt latch is cleared while the interrupt vector is being fetched. During the
interrupt service routine, a new external interrupt request can be initiated and
latched. As soon as the interrupt mask is cleared (usually during the return from
interrupt), the latched request is recognized and serviced.
The level sensitive trigger option allows multiple interrupt sources to be
wire-ORed to the IRQ pin. As long as any source is holding the IRQ pin at
logical zero, an external interrupt request is considered to be pending.

LEVEL·SENSITIVE TRIGGER
(MASK OPTION)

------------------

I BIT (IN CCR)

V DD

D

Q 1-----1

EXTERNAL
INTERRUPT
REQUEST

IRQ
INTERRUPT
PIN
RESET

EXTERNAL INTERRUPT
BEING SERVICED
(VECTOR FETCH)

Figure 4-3. External Interrupt Logic

MC68HC05P1

RESETS AND INTERRUPTS

MOTOROLA
4-5

4.2.2 Software Interrupt (SWI)
The SWI is an executable instruction. The SWI instruction is executed
regardless of the state of the interrupt mask (I-bit) in the condition code register.
The address of the SWI interrupt service routine is in memory locations $1 FFC
and $1FFD.

4.2.3 Capture/Compare Timer Interrupt
The capture/compare timer can generate three interrupts when the interrupt
mask is a logical zero. When one of the three timer interrupt flags in the timer
status register is at logical one, and the corresponding interrupt enable flag in
the timer control register is at logical one, the CPU recognizes a timer interrupt.
(Refer to SECTION 6 CAPTURE/COMPARE TIMER for more information.)
All three timer interrupts use the same interrupt vector at $1 FF8 and $1 FF9.

MOTOROLA
4-6

RESETS AND INTERRUPTS

MC68HC05P1

SECTION 5
MEMORY
Section 5 describes the organization of the on-chip memory. The CPU of the
MC68HC05P1 MCU can address 8K bytes of memory space.

5.1 Memory Map
The program counter normally advances one address at a time through the
on-chip memory, reading the instructions and data necessary to execute the
program. The ROM portion of memory holds the program instructions,
user-defined vectors, and service routines. The RAM portion of memory holds
variable data. 1/0, control, and status registers are memory-mapped so that the
CPU can access their locations the same way it accesses any other memory
location.
On-chip ROM includes 2112 bytes of factory-programmed memory for storage of
application program instructions and fixed data. The last eight ROM addresses
($1 FF8-$1 FFF) contain user-defined vectors for servicing interrupts and resets.
When ordering the MCU, the user specifies the instructions and data to be
programmed into the user ROM.
The 240 bytes between $1 Faa and $1 FEF are reserved ROM addresses that
contain the instructions for a series of self-check tests.
The MCU has 128 bytes of fully static read-write memory for storage of variable
and temporary data during program execution. The CPU uses the top 64 RAM
addresses ($OOCO-$OOFF) for the stack. The CPU uses the stack to save CPU
register contents before processing .an interrupt or subroutine call. The stack
pointer decrements during pushes and increments during pulls.
The first 32 bytes of the memory space contain port data registers, port data
direction registers, and timer control, status, and counter registers.
Figure 5-1 is a memory map of the MCU. Refer to Figure 5-2 for a more detailed
memory map of the 32-byte I/O register area.

MC68HC05P1

MEMORY

MOTOROLA
5·1

$0000

I/O
32 BYTES

$OOlF
$0020

USER ROM
48 BYTES

$004F
$0050

UNUSED
48 BYTES

$007F
$0080
RiM
128 BYTES
$OOBF
$OOCO-

$OOFF
$0100

---

-----~---

'If

STACK
64B1ES

USER ROM
2048 BYTES
$08FF
$0900

UNUSED
5632 BYTES

PORT A DATA REGISTER
PORT B DATA REGISTER
PORTC DATA REGISTER
PORT 0 DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
PORT 0 DATA DIRECTION REGISTER
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER HIGH
INPUT CAPTURE REGISTER fLOWL
OUTPUT COMPARE REGISTERiHIG\:IL
OUTPUT COMPARE REGISTERfLOWL
COUNTER REGISTER HIGH
COUNTER REGISTER LOW
COUNTER ALTERNATE REGISTER HIGH
COUNTER ALTERNATE REGISTER LOW
UNUSED
UNUSED
UNUSED
RESERVED

$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$OOOA
$oooB
$OOOC
$0000
$OOOE
$ooOF
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001 A
$oolB
$001C
$0010
$COlE
$C01F

I

$lFFO

USER ROM
8 BYTES

$lEFF
$lFOO

f

SELF-CHECK
ROM
AND VECTORS
240 BYTES

TIMER VECTOR HIGH
TIMER VECTOR LOW
IRO VECTOR HIGH
IRO VECTOR fLOW)
SWI VECTOR HIGH
SWI VECTORiLOWL
RESET VECTOR HIGH BYTE
RESET VECTOR LOW BYTE

$lFEF
$lFFO
USER VECTORS
16 BYTES
$lFFF

$lFF7
$lFF8
$lFF9
$lFFA
$lFFB
$lFFC
$lFFD
$lFFE
$lFFF

Figure 5·"1. MC68HC05P1 Memory Map

NOTE

Using the stack area for data storage or as a temporary work area
requires care to prevent data from being overwritten during
stacking from an interrupt or subroutine call.

MOTOROLA
5-2

MEMORY

MC68HC05P1

$0000
$0001
$0002
$0003

I

Bit 7

6

5

4

1/0

I/O

I/O

I/O

3
PA7

4
PA6

5
PAS

6
PA4

I/O

I/O

I/O

0

13
PB7

12
PB6

11
PB5

1/0
15
PC7

1/0
16
PC6

1/0
17
PC5

I/O
23
PD5

I lonly I
25
PD7ffCAP

0

I

II

Bit 0

3

2

I/O

I/O

I/O

I/O

PORTA

7
PA3

8
PA2

9
PA1

10
PAO

PORT A PIN NUMBERS (REF.)
PORT A PIN NAMES (REF.)

II

0

I/O
18
PC4

II

1/0

1

II

I

I

I

0

0

I

1/0
21
PC1

1/0
20
PC2

19
PC3
0

0

I

0

0

PORT B PIN NUMBERS (REF.)
PORT B PIN NAMES (REF.)

1/0
22
PCO

I

I PORTS

0

PORTC
PORT C PIN NUMBERS (REF.)
PORT C PIN NAMES (REF.)

PORTD
I PORT
0 PIN NUMBERS (REF.)
PORT 0 PIN NAMES (REF.)

$0004
$0005
$0006
$0007

DDRA
DDRB
DDRC
DDRD

Unused

RESERVED
Figure 5-2. I/O and Control Register Summary

MC68HC05P1

MEMORY

MOTOROLA
5-3

5.2 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU register
contents at VDD voltages as low as 2.0 Vdc. Before the VDD voltage is lowered,
drive the RESET pin to logical zero. During data-retention mode, RESET must
remain low continuously. The data-retention mode allows the MCU to be left in
a low power-consumption mode during which data is held, but the CPU cannot
execute instructions. To exit the data-retention mode, VDD must be returned to
its normal operating voltage before RESET is returned to logical one.

MOTOROLA
5-4

MEMORY

MC68HC05P1

SECTION 6
CAPTURE/COMPARE TIMER
This section describes the operation of the capture/compare timer. Figure 6-1
shows the structure of the capture/compare timer system.
INTERNAL PROCESSOR CLOCK (XTAL + 2)

@PIN

EDGE
SELECT
AND
DETECT

r-

~

r---r-

If

0

FIXED

16-BIT INPUT CAPTURE REGISTER

II

15

,,""'ffi

8 7

lATCH 15

H

DIVI~EBY

II

8 7

0

.J.1-

~

I

I

I
J

16-BIT TIMER COUNTER
I LSB BUFFER

ICONTROL
PIN

...

16·BIT COMPARATOR

I

=?

ii

~
PIN

~

16·BIT OUTPUT COMPARE REGISTER

8 7

15

LOGIC

0

I

I
w!!! w

(!l-'
t:l ::;

28 ~

!!!o
I

I

0-

u.. u.. u..

28
\

I

l TIMER CONTROL REGISTER I

I

~

I

I

I

I

I

TIMER STATUS REGISTER

I

-

-

-J

I

TIMER
INTERRUPT
REQUEST

INTERNAL
DATA BUS

Figure 6-1. Capture/Compare Timer Block Diagram

MC68HC05P1

CAPTURE/COMPARE

TIMER

MOTOROLA
6-1

6.1 Timer Counter
The key element in the programmable capture/compare timer is a 16-bit,
free-running counter, preceded by a prescaler that divides the internal clock by
four. The counter provides the timing reference for the input capture and output
compare functions. Software can read the counter value at any time from either
of the following two registers with no effect on the counter sequence:
•
•

Timer Counter Register (TCNT)
Alternate Counter Register (ALTCNT)

Reading the high byte of the timer counter register or alternate counter register
accesses the high byte value at the time of the read and causes the low byte to
be latched into a buffer. (Refer to Figure 6-2.) This buffer value remains fixed
after the first high-byte read, even if the high byte is read more than once. The
buffer is accessed when the read sequence is completed by reading the low
byte of the timer counter register or the alternate counter register. If the high
byte is read, the low byte must also be read to complete the read sequence.

$18
($1 A)

READ COUNTER - - - 4 - - 1
HIGH BYTE
$19
($1 B)

READ COUNTER - - - - - I
LOW BYTE

[1] The LSB latch is normally transparent, becomes latched when high byte of counter
is read, and becomes transparent again when low byte of counter is read.

Figure 6-2. 16-Bit Counter Reads

The free-running counter is preset to $FFFC during reset. During a power-on
reset, the counter is preset to $FFFC and begins running after the oscillator
startup delay. Because the free-running counter is 16 bits long and preceded
by a fixed divide-by-four prescaler, the value in the counter repeats every
262,144 internal clock cycles.

MOTOROLA
6-2

CAPTURE/COMPARE

TIMER

MC68HC05P1

6.1.1 Timer Counter Register (TCNT)
The high and low bytes of the free-running counter can be read from the timer
counter register at locations $0018 and $0019. (Refer to Figure 6-3.) Reading
the low byte ($0018) of the timer counter register after reading the timer status
register clears the timer overflow flag (TOF).

Bit 7

5

6

I Bit15 I
I Bit7 I

I
I

14

6

13
5

4

I
I

3

II
II

12
4

Bit 0

2

I
I

11
3

I
I

10
2

I
I

9
1

BitS
BitO

I $18
I $19

TCNT(HIGH)
TCNT(LOW)

RESET CONDITION

RESET TO $FFFC

Figure 6-3. Timer Counter Register (TCNT)

6.1.2 Alternate Counter Register (ALTCNT)
The high and low bytes of the free-running counter can be read from the
alternate counter register at locations $001A and $001 B. (Refer to Figure 6-4.)
Reading the alternate counter register does not affect the timer overflow flag
(TOF). The alternate counter register can be read at any time without risk of
clearing TOF inadvertently. Normally, the timer value is read from the alternate
counter register unless the read sequence is intended to clear TOF.

Bit 7

I Bit15 I
I Bit7 I

6

14
6

I
I

5

4

13

12

5

4

3

II
II

11
3

BitO

2

I
I

10
2

I
I

9
1

I
I

BitS
BitO

RESET TO $FFFC

I $1A
I $18

ALTCNT (HIGH)
ALTCNT (LOW)

RESET CONDITION

Figure 6-4. Alternate Counter Register (ALTCNT)

NOTE
To prevent interrupts from occurring between readings of the high
and low bytes of the timer counter register or the alternate counter
register, the interrupt mask (I-bit) in the condition code register can
be set before reading the high byte and cleared after reading the
low byte.

MC68HC05P1

CAPTURE/COMPARE

TIMER

MOTOROLA
6-3

6.2 Timer Functions
The input capture and output compare functions provide a means to latch the
times at which external events occur, to measure input waveforms, and to
generate output waveforms and timing delays.

6.2.1 Input Capture
The input capture feature provides a means to record the time at which an
external event occurs. When the timer detects a selected (negative-going or
positive-going) edge on the TeAP pin, it latches the contents of the timer
counter register into the input capture register. The IEDG bit in the timer control
register allows software to select the edge polarity that triggers the input capture
function. The lelE bit in the timer control register allows software to determine
whether or not the input capture function generates a hardware interrupt
,
request. (Refer to Figure 6-5.)

LATCH

$14
~---I ICF

IEDG = 0 for falling edges
IEDG = 1 for rising edges

$15

STATUS FLAG

}-_~~

REQUEST A TIMER
INTERRUPT

Figure 6-5. Input Capture Operation
Latching values into the timer counter register at successive edges of the same
polarity measures the period of the input signal on the TeAP pin. Latching the
counter values at successive edges of opposite polarity measures the pulse
width of the signal.

MOTOROLA
6-4

CAPTURE/COMPARE

TIMER

MC68HC05P1

6.2.2 Output Compare
The output compare feature provides a means of generating an output signal
when the timer counter register reaches a selected value. The selected value is
written into the output compare register. On every fourth internal clock cycle the
capture/compare timer compares the value of the timer counter register to the
contents of the output compare register. When a match occurs, the timer
transfers the output level bit (OLVL) from the timer control register to the TCMP
output pin. (Refer to Figure 6-6.)
OLVL = 0 to force TCMP pin
low on valid compare
OLVL = 1 to force TCMP pin
high on valid compare

lor l

9 - - - - / OCF STATUS FLAG
$16

$17

1--_--,;> REQUEST A TIMER
INTERRUPT

lOCAL INTERRUPT ~ OCIE
MASK (ENABLE)

Figure 6-6. Output Compare Operation
The programmer can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or a pulse
train of specific frequency and duty cycle on the TCMP pin.

6.3 Input Capture Register (ICR)
The high and low bytes of the input capture register are at memory locations
$0014 and $0015. (Refer to Figure 6-7.) The input capture register is read-only
and is not affected by a reset.
Bit 7

6

5

4

I Bit15

1 14

1 13

1 12

II

3

2

11

1 10

Bit 0
1

9

BitS 1

:=1==Bi==t7~1=6:==~1=5:==~1=4=1~1===3~I===2~I=1===*'==B==it0=:1
INPUT CAPTURE REGISTER NOT AFFECTED BY RESET

$14 TCAP (HIGH)
$15 TCAP (LOW)
RESET CONDITION

Figure 6-7. Input Capture Register (ICR)

MC68HC05P1

CAPTURE/COMPARE

TIMER

MOTOROLA

6-5

When the input capture edge detector senses a defined transition on the TCAP
pin, the input capture flag (ICF) is set, and the input capture register latches the
value of the timer counter register. The contents of the timer counter register are
transferred to the input capture register on every defined signal transition
whether or not ICF was previously set. The input capture register always
contains the value in the timer counter register at the time of the most recent
input capture. The polarity of the level transition that triggers the counter
capture is defined by the input edge bit (IEDG).
The timer counter register increments every fourth cycle of the internal clock.
The counter value latched into the input capture register is one count more than
the count at the time of the last riSing edge of the clock before the defined
transition on the TCAP pin occurred. This delay is required for internal
synchronization.
Reading the high byte of the input capture register inhibits the input capture
function until the low byte is also read. If the high byte is read first, both bytes
must be read. Reading only the low byte does not inhibit the input capture
function.

NOTE
To prevent interrupts from occurring between readings of the high
and low bytes of the input capture register, set the interrupt flag
before reading the high byte and clear the flag after reading the
low byte.

6.4 Output Compare Register (OCR)
The high and low bytes of the output compare register are at memory locations
$0016 and $0017. (Refer to Figure 6-8.) All bits are readable and writable and
are not altered by the capture/compare timer hardware or by a reset. If the
compare function is not needed, the two bytes of the output compare register
can be used as storage locations.

Bit 7

14
6

4

5

6

I Bit15 I
I Bit7 I

I
I

13

5

I
I

12
4

2

3

II
II

11
3

I
I

10
2

Bit 0

I
I

9
1

I
I

BitS
BitO

OUTPUT COMPARE REGISTER NOT AFFECTED BY RESET

I $0016
I $0017

OCR (HIGH)
OCR (LOW)

RESET CONDITION

Figure 6-8. Output Compare Register (OCR)

MOTOROLA
6-6

CAPTURE/COMPARE

TIMER

MC68HC05P1

Output compare register contents are continually compared with the contents of
the timer counter register. When a match occurs, the output compare flag (OCF)
is set, and the OLVL bit is clocked to the TCMP output pin. OLVL appears on
TCMP whether or not OCF was previously set. An output compare interrupt is
enabled if the output compare interrupt enable bit (OCIE) is set. The output
compare register values and the output level bit are typically changed after
each successful comparison to establish a new timeout period. Writing to either
byte of the output compare register does not affect the other byte.
Writing the high byte of the output compare register inhibits the output compare
function until the low byte is also written. If the high byte is written first, both
bytes must be written. Writing only the low byte does not inhibit the output
compare function.

6.5 Timer Status Register (TSR)
The read-only timer status register shown in Figure 6-9 has status flags to
indicate the following conditions:
.. A selected transition occurred at the TCAP pin, and the contents of the
timer counter register were transferred to the input capture register.
o A match occurred between the timer counter register and the output
compare register, and the OLVL bit was transferred to the TCMP pin.
• A timer counter register transition from $FFFF to $0000 occurred.
Bitl

6

ICF

loa:

U

U

5
TOF
U

4

I

0

0

2

3

II

0

0

I

0
0

Bit 0

I

0

I

0

0

$0013 TSR

0

RESET CONDITION

(U =UNAFFECTED)

Figure 6-9. Timer Status Register (TSR)

ICF - Input Capture Flag
ICF is automatically set when an edge of the selected polarity occurs on
TCAP. Clear ICF by reading the timer status register with ICF set, and then
reading the low byte ($0015) of the input capture register.
OCF - Output Compare Flag
OCF is automatically set when the value of the timer counter register
matches the contents of the output compare register. Clear OCF by reading
the timer status register with OCF set, and then accessing the low byte
($0017) of the output compare register.

MC68HC05P1

CAPTURE/COMPARE TIMER

MOTOROLA

6-7

TOF - Timer Overflow Flag
TOF is automatically set when the timer counter register changes from
$FFFF to $0000. Clear TOF by reading the timer status register with TOF set,
and then accessing the low byte ($0019) of the timer counter register.
Bits 4-0 -

Not used; always read zero

To clear a status bit, read the timer status register. Then access the low byte of
the register associated with the status bit.
When using the timer overflow function and reading the timer counter register at
random times to measure elapsed time, TOF could unintentionally be cleared.
This problem can occur when reading the timer status register and the low byte
of the timer counter register, but not for the purpose of servicing the TOF flag.
The alternate counter register at locations $001 A and $001 B contains the same
value as the timer counter register at locations $0018 and $0019. Because
reading the alternate counter register has no effect on the timer status register,
the alternate counter register can be read at any time without clearing TOF.

6.6 Timer Control Register (TCR)
The read/write timer control register has five control bits. (Refer to Figure 6-10.)
Three bits control interrupts associated with the timer status register flags ICF,
OCF, and TOF. Another bit determines the edge polarity (positive-going or
negative-going) that activates the input capture edge detector. Another bit
determines the output level clocked onto TCMP when a successful output
compare occurs.

Bit 7

ICIE

o

6

5

I OCIE I TOlE I
o

o

4

0

o

3

II

0

2

I

o

0

o

1

Bit 0

I IEDG I om I
U

o

$0012 TCR
RESET CONDITION

(U = UNAFFECTED)

Figure 6-10. Timer Control Register (TCR)

ICIE -

MOTOROLA
6-8

Input Capture Interrupt Enable
1 = ICF interrupt enabled
o = ICF interrupt disabled

CAPTURE/COMPARE

TIMER

MC68HC05P1

OCIE -

Output Compare Interrupt Enable
1 = OCF interrupt enabled
o = OCF interrupt disabled

TOlE - Timer Overflow Interrupt Enable
1 = TOF interrupt enabled
o = TOF interrupt disabled
IEDG - Input Edge
This bit determines which transition on the TCAP pin triggers a transfer of the
contents of the timer counter register to the input capture register.
1 = Positive edge (low level to high level)
o = Negative edge (high level to low level)
OLVL - Output Level
This bit determines the output level on the TCMP pin when a successful
output compare occurs.
1 = High output
o = Low output
Bits 4, 3, and 2 -

Not used; always read zero

6.7 Timer during WAIT Mode
The internal clock halts during WAIT mode, but the capture/compare timer and
COP counter remain active. An interrupt from the capture/compare timer causes
the processor to exit WAIT mode.

6.8 Timer during STOP Mode
In STOP mode, the capture/compare timer stops counting and holds the last
count value. If IRQNpp is used to exit STOP mode, the timer resumes counting
from the count value that was present when STOP mode was entered. If
RESET is used, the counter is forced to $FFFC.
If a defined transition occurs on the TCAP pin during STOP mode, ICF goes
high as soon as an external interrupt brings the MCU out of STOP mode. If a
power-on reset or a logical zero on the RESET pin brings the MCU out of STOP
mode, all timer interrupt enable bits are cleared.

MC68HC05P1 .

CAPTURE/COMPARE

TIMER

MOTOROLA
6-9

MOTOROLA
6-10

CAPTURE/COMPARE

TIMER

MC68HC05P1

SECTION 7
SELF-CHECK MODE
The self-check mode described in this section tests the operation of the MCU.

7.1 Self-Check Circuit
The self-check function determines if the MCU is functioning properly. The
self-check circuit is shown in Figure 7-1. If 9 Vdc is applied to the IRQ pin, and a
logical one is applied to the PD7/TCAP pin, the MCU enters the self-check
mode when reset. Port C pins PC3-PCa are monitored for the self-check
results. After a reset in self-check mode, the following self-check tests are
performed automatically in self-check mode:
•
•
•
•
•

I/O - Functional test of ports A, S, and C
RAM - Counter test for each RAM byte
ROM - Checksum of entire ROM pattern
Capture/compare timer - Test of counter register and OCF bit
Interrupts - Test of external and capture/compare timer interrupts

7.2 Self-Check Results
Table 7-1 lists the codes displayed by the light-emitting diodes (LEDs) to
indicate the self-check results.

Table 7-1. Self-Check Results
PC3

PC2

PC1

PCO

1

0

0

1

1

0

1

0

Bad RAM

1

Bad Capture/Compare Timer
Bad ROM

0

1

1

1

0

0

1

1

0

1

1

Flashing
All Others

Remarks
Bad I/O

Bad Interrupts or IRQ Request
Good Device
Bad Device, Bad Port C, etc.

NOTE: Zero indicates LED is on; 1 indicates LED is off.

MC68HC05P1

SELF·CHECK MODE

MOTOROLA

7-1

+9Vdc

~...kn
'Y"

~4.7kn

IRQ

RESET

2N3904
VDD

+5V
>10kn

-=-

OSCI
25

~
4
5
6

~
8
9
10

.

PA7
PAS
PA5
PM
PA3
PA2
PAl
PAO

OSC2

TCMP
PD5

PCl

-==-

PC2
PC3

14

--.C"""

.. ~lbkn

28

27

26

+5V
20pF

.:i ~~
o 4.0 MHz -=-

~

T

20pF

PCO

11
12
13

1

10kn ~

TCAPIPD7

j.l0kn

I

'1Q--

MC68HC05Pl
2

PB5
PBS
PB7

--

24

~

21

"

20

.-,

19

"

18
PC4 I 17
PCS
16

.
~

22

470n

VDO
~

.-, 4Jon T
470n

'-' 4Jon

'T

.-,

pes

PC7

15

VSS

Figure 7-1. Self-Check Circuit

MOTOROLA

7-2

SELF-CHECK MODE

MC68HC05P1

SECTION 8
ELECTRICAL SPECIFICATIONS
This section contains MCU electrical specifications and timing information.

8.1 Maximum Ratings
The MCU contains circuitry that protects the inputs against damage from high
static voltages; however, take precautions to avoid applying voltages higher
than those shown in Table 8-1. Yin and Vout should be kept within the range
Vss s:; (Vin or Vout) s:; Voo. Connect unused inputs to an appropriate logical
voltage level (e.g., either Vss or Voo).

Table 8-1. Maximum Ratings
Symbol

Value

Supply Voltage

Veo

-0.3 to +7.0

V

Input Voltage

Yin
Yin

Vss - 0.3 to VDD + 0.3

V

Vss - 0.3 to 2 x VDD + 0.3

V

I

25

mA

TA

TL to TH

'C

Rating

Self-Check Mode (IRQ pin only)
Current Drain per Pin (excluding VDD and Vss)
Operating Temperature Range
MC68HC05P1 P, OW

Unit

Oto+70

MC68HC05P1CP, COW

--40°C to +85°C

MC68HC05P1 VP

--40°C to + 105°C

Storage Temperature Range

Tstg

'C

-65 to +150

8.2 Thermal Characteristics

Table 8-2. Thermal Characteristics
Characteristic
Thermal Resistance

MC68HC05P1

Symbol

Value

Plastic

60

SOIC

60

ELECTRICAL

SPECIFICATIONS

Unit
°cm

RaJA

MOTOROLA
8-1

Voo
R2
(SEE TABLE)
TEST
POINT

o - - e - - - -...

l

~EETABLE)

Voo = 4.5 V
Pins
R1
PA7-PAO
3.26 kn

(SEE TABLE)

C
50pF

R2
6.32 kG

50pF

PB5-PBO
PC7-PCO
PD5, TCMP

Voo = 3.0 V
Pins
R1
Rl

R2
2.38 kG

PA7-PAO
10.91 kn
PB7-PB5
PC7-PCO
PD5, TCMP

C

Figure 8-1. Test Load

8.3 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (Po x RaJA)

(1 )

where:
T A = Ambient temperature in °C
RaJA = Package thermal resistance, junction to ambient in °C/W
Po = PINT + PI/O
PINT = 100 x Voo, watts - chip internal power
PI/O = Power dissipation on input and output pins - user-determined
For most applications PI/O « PINT and can be neglected.
The following is an approximate relationship between Po and TJ (if PI/O is
neglected):
(2)

Solving equations (1) and (2) for K gives:
K =Po x (TA + 273°C) + RaJA x Po

(3)

where K is a constant pertaining to the particular part. K can be determined
from equation (3) by measuring Po (at equilibrium) for a known T A. Using this
value of K, the values of Po and TJ can be obtained by solving equations (1)
and (2) iteratively for any value of TA.

MOTOROLA
8-2

ELECTRICAL SPECIFICATIONS

MC68HC05P1

8.4 DC Electrical Characteristics (Voo

=5.0 Vdc)

Table 8-3. DC Electrical Characteristics (Voo
(Voo

=5.0 Vdc)

=5.0 Vdc ± 10%, Vss =0 Vdc, TA =TL to TH, unless otherwise noted)
Characteristic

Output Voltage (ILoad ~ 10.0).LA)

= 0.8 mAl

Output High Voltage (ILoad

Symbol

Min

Typ

Max

Unit

VOL

-

0.1

V

VOH

Voo -0.1

-

0.4

V

V

VOH
VOL

-

-

VIH

0.7xVoo

-

Voo

V

VIL

Vss

-

0.2xVOO

V

Data-Retention Mode Supply Voltage (0 to 70°C)

VRM

2

-

-

V

Supply Current (refer to NOTES)

100
3.5

7.0

1.6

4.0

mA
mA

2.0

50

PA7-PAO, PB7-PB5, PC7-PCO, PD5, TCMP
Output low Voltage (ILoad

Voo -0.8

= 1.6 mAl

PA7-PAO, PB7-PB5, PC7-PCO, PD5, TCMP
Input High Voltage
PA7-PAO, PB7-PB5, PC7-PCO, PD5, PD7ITCAP,
IRQ, RESET, OSC1
Input low Voltage
PA7-PAO, PB7-PB5, PC7-PCO, PD5, PD7ITCAP,
IRQ, RESET, OSC1

-

RUN
WAIT
STOP

ilL

-

lin

25°C

oto 70°C (standard)
I/O Ports Hi-Z leakage Current

-

).LA
!LA

140

-

±10

).LA

-

-

±1

).LA

-

-

12

pF
pF

PA7-PAO,PB7-PB5,PC7-PCO,PD5
Input Current
RESET,IRQ, OSC1,PD5, PD7ITCAP
Capacitance
Ports (as input or output)

Cout

RESET, IRQ, PD5,PD7ITCAP

Cin

8

NOTES:
1. Typical values at midpoint of voltage range, 25°C only.
2. RUN (operating) 100, WAIT 100 measured using external square wave clock source (fose =4.2 MHz),
all inputs 0.2 V from rail; no de loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
3. WAIT 100, STOP 100: all ports configured as inputs, VIL = 0.2 V, VIH = Voo - 0.2 V.
4. STOP IDO measured with OSC1 = VSS.
5. Standard temperature range is 0 to 70°C.
6. WAIT IDO is affected linearly by the OSC2 capacitance.

MC68HC05P1

ELECTRICAL

SPECIFICATIONS

MOTOROLA
8-3

8.5 DC Electrical Characteristics (Voo

= 3.3

Vdc)

Table 8-4. DC Electrical Characteristics (Voo
(Voo

= 3.3 Vdc ± 10%, Vss = 0 Vdc, TA =TL to TH

= 3.3 Vdc)

unless otherwise noted)

Characteristic
Output Voltage (ILoad S 10.0 flA)

Symbol

Min

Typ

Max

Unit

Va..
VOH

-

-

0.1

V

0.3

V

VOO-0.1

V

Output High Voltage (ILoad = 0.2 rnA)
PA7-PAD, PB7-PB5, PC7-PCO, PD5, TCMP

VOH

Output Low Voltage (ILoad = 0.4 rnA)
PA7-PAD, PB7-PB5, PC7-PCO, PD5, TCMP

VOL

-

-

Input High Voltage
PA7-PAD, PB7-PB5, PC7-PCO, PD5, PD7fTCAP,

VIH

0.7 x VOO

-

Vro

V

VIL

Vss

-

0.2xVOO

V

V~

2.0

-

-

V

-

1.0
0.5

2.5
1.4

rnA
rnA

2.0

-

30
80
±10

flA
flA
flA

Vro -0.3

IRQ, RESET, OSC1
Input Low Voltage
PA7-PAD, PB7-PB5, PC7-PCO, PD5, PD7fTCAP,
IRQ, RESET, OSC1
Data-Retention Mode Supply Voltage (0 to 70°C)
Supply Current (refer to NOTES)
RUN
WAIT
STOP
25°C
oto 70°C (Standard)

100

I/O Ports Hi-Z Leakage Current
PA7-PAO,PB7-PB5,PC7-PCO,PD5

hL

-

Input Current

lin

-

-

±1

flA

-

-

12
8

pF
pF

-

RESET,IRQ, OSC1, PD5, PD7fTCAP
Capacitance
Ports (As Input or Output)
RESET, IRQ, PD5, PD7fTCAP

CaUl

On

NOTES:
1. Typical values at midpoint of voltage range, 25°C only.
2. RUN (operating) 100, WAIT 100 measured using external square wave clock source (lose =4.2 MHz),
all inputs 0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
3. WAIT 100, STOP 100: all ports configured as inputs, VIL =0.2 V, VIH =Voo - 0.2 V.
4. STOP IDD measured with OSC1 =Vss.
5. Standard temperature range is 0 to 70°C.
6. WAIT 100 is affected linearly by the OSC2 capacitance.

MOTOROLA
8-4

ELECTRICAL

SPECIFICATIONS

MC68HC05P1

SOOmV

SOOmV

700mV

700mV

1

1

600mV

:r:

~
I

CI
CI
>

600mV

500mV

500mV

:r:

>0

400 mV

I

0
>CI

300mV

400mV
300mV

200mV

200mV

100mV

100mV

0

0

o

-1.0mA

-2.0mA

-3.0mA

-4.0mA

-5.0mA

0

-1.0 mA

-2.0 mA

-3.0 mA

-4.0 mA

-5.0 mA

:>

IOH

• At VDD = 5.0 V, devices are specified and tested for
(VDD -VOH)SSOOmV@IOW-o.SmA.

• At VDD = 3.3 V, devices are specified and tested for
(VDD - VOH) s 300 mV@ I OH= - 0.2 mAo

Shaded area indicates variation in driver characteristics caused by changes in temperature and for n~rmal processing tolerances.
Within the limited range of values shown, V vs. I curves are approximately straight lines.

Figure 8-2. Typical High-Side Driver Characteristics

f:--SPEC.

o

2.0mA

4.0mA

, : .~

6.0mA
IOL

0

S.OmA

10.0mA

o

2.0 mA

:>

4.0 mA

6.0 mA

8.0 mA

>

IOL

• At VDD = 5.0 V, devices are specified and tested for
VOL S400mV@I OL =1.6mA.

10.0 mA

• At V DD = 3.3 V, devices are specified and tested for
VOL S 300 mV@ I OL =0.4 mAo

Shaded area indicates variation in driver characteristics caused by changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V vS. I curves are approximately straight lines.

Figure 8-3. Typical Low-Side Driver Characteristics

MC68HC05P1

ELECTRICAL

SPECIFICATIONS

MOTOROLA
8-5

-r-------..,..-----,.-----...

3.SmA -r-------"'T""----r-----,

T =2SoC
RUN MOOE
(OPERATING)
3.0 mA -I-----,----+----+---.#-_I

3.0 mA -I-------,r-------+-----+--_I

2.S mA

2.S mA +---11----+-----+----___1

3.S mA

-I-----I----+----,~--I-_I

Cl
Cl

~ 2.0mA +---I~---hr~y..---I

z

Cl
Cl

~ 2.0mA

~

::::J

-'
c..

'-'
0.

~

>- 1.S mA -1-----11-----:#--#----+--_1
c..

~ 1.S mA -f-----II------+-----+----:~

0.

::::J

iil

U)

+---I~~---:oof-....=.!::--+---I

1.0mA

+---I---+~~"'-t---___1

SOO jJA -I---:H--7A""----l----+--_I

500 jJA

-I-----I~O<....-__:::o""'-...::..::.--+--_I

1.0 mA

o+----I----+----+--~

o

O-F---Ir----+----+---~

SOO KHz
1 MHz
1.S MHz
2 MHz
INTERNAL CLOCK FREQUENCY (XTAL + 2)

o

SOO KHz
1 MHz
1.5 MHz
2 MHz
INTERNAL CLOCK FREQUENCY (XTAL + 2)

Figure 8-4. Typical Supply Current vs Clock Frequency
7.0 mA

-r--------..,..-----,.------...
T =- 40° to 8SoC
Voo =5V±10%

6.0 mA -I-----,----+----+---.#-_I

S.OmA + - - - 1 - - - - / - - 4 + - - - - 1

2.SmA

-r-------"'T"""-----r----~

T =_40° to 8SOC

c,

Voo =3.3V±10%

Cl

~

4.0 mA -1-----1---+-,#---+---..1

2.0 mA +-----,------j------I-,...--I

z

ti!

Cl

~
~ 3.0 mA + - - - 1 -

.P
;::- 1.S mA + - - - 1 ' - - - -

z

~

ti!

c..

::::J

U)

2.0 mA

-+-----I#--~'"I----+--_I

B1.0 mA
~

+---II-~<--+-~"9----I

8:
iil
1.0 mA

+---;r~----/----I---___1

STOP 100

(100 jJA)

o~===t==~====t===~
o

500 KHz
1 MHz
1.S MHz
2 MHz
INTERNAL CLOCK FREQUENCY (XTAL + 2)

5OOjJA-+--~Y_7fI""--__+-----t--__I

(SO jJA)
O~====~====*=====~==~
o
500 KHz
1 MHz
1.5 MHz
2 MHz
INTERNAL CLOCK FREQUENCY (XTAL + 2)

Figure 8-5. Maximum Supply Current vs Clock Frequency

MOTOROLA
8-6

ELECTRICAL

SPECIFICATIONS

MC68HC05P1

8.6 Control Timing (Voo

= 5.0

Vdc)

Table 8-5. Control Timing (Voo
(Voo

= 5.0

Vdc)

= 5.0 Vdc ± 10%, Vss = 0 Vdc, TA =Tl to TH)
Characteristic

Oscillator Frequency

Symbol

Min

Max

Unit

MHz
MHz

lose

Crystal Option
External Clock Option
Internal Operating Frequency

-

4.2

dc

4.2

lop

Crystal (lose + 2)
External clock (lose + 2)

-

2.1

dc

2.1

MHz
MHz

-

teye

Internal clock cycle time

teye

480

RESET Pulse Width

tRl

1.5

ns

Capture/Compare Timer
tRESl

4.0

Input Capture Pulse Width

ITH. t1L

125

Input Capture Pulse Period

ITl1L

(refer to NOTE 2)

-

tlLlH

125

-

tlLlL

(reler to NOTE 3)

-

teyc

tOH. tOl

90

-

ns

Resolution (relerto NOTE 1)

Interrupt Pulse Width Low (Edge Triggered)
Interrupt Pulse Period
OSC1 Pulse Width

tcyc
ns
tcyc
ns

NOTES:
1. Because a 2·bit prescaler in the capture/compare timer must count lour internal cycles (teye), this is
the limiting minimum lactor in determining the timer resolution.
2. The period tTlTl should not be less than the number 01 cycles it takes to execute the capture
interrupt service routine plus 24 teyc.
3. The period tlLll should not be less than the number 01 cycles it takes to execute the interrupt service
routine plus 21 teye.

r- -1 -1 r-1 r---LJl__---InL.__---1.------iU
tTm

TCAP PIN

tTH

tTL

Figure 8-6. TCAP Timing

MC68HC05P1

ELECTRICAL

SPECIFICATIONS

MOTOROLA

8-7

OSC 1

- - - - , 4 - t RL ~

\

~

•

/

~tILlH ~

\

L

I

1<

----,

4064 tcyc

\

~
•

r--,

INTERNAL
,
,
CLOCK _ _ _ _ _ _ _ _ _ _ _.J.'_...'_-'
INTERNAL -..-.,.............-'l<"""'7.........-.-.,.......,............,..
ADDRESS
BUS _.L.....IO'-"--"-"'--''--''--''-",,-,'--''-..JI
~

RESET OR INTERRUPT
VECTOR FETCH

NOTES:
1. Represents the internal clocking of the OSC 1 pin.
2. IRQ pin edge-sensitive mask option.
3. IRQ pin level- and edge-sensitive mask option.
4. RESET vector address shown for timing example.

Figure 8-7. STOP Recovery Timing

IRQ (PIN)

U

Edge-SensHive Trigger Condition
The minimum pulse widlh (t iLlH) is
either 125 ns (V DD= 5 V) or 250 ns
(VDD = 3 V). The period t ILiL should
not be less than the number of t cyc
cycles it takes to execute the interrupt
service routine plus 19 t cyc cycles.

~tILlH
1<
tlLlL ---:>~I

Level-Sensitive Trigger Condition
If after servicing an interrupt the IRQ
remains low, the next interrupt is
recognized.
NORMALLY
USED WITH
WIRE-QRed
CONNECTION
IRQ (MCU) :

r-

IL..--._ _-----II

Figure 8-8. External Interrupt Timing

MOTOROLA
8-8

ELECTRICAL

SPECIFICATIONS

MC68HC05P1

8.7 Control Timing (Voo

= 3.3 Vdc)

Table 8-6. Control Timing (Voo

= 3.3

Vdc)

(VDD = 3.3 Vdc± 10%, Vss = 0 Vdc, TA= TL to TH.)
Characteristic

Symbol

Min

Max

Unit

-

2.0
2.0

MHz
MHz

1.0
1.0

MHz
MHz

fosc

Oscillator Frequency
Crystal Option

dc

External Clock Option
fop

Internal Operating Frequency
Crystal (fosc + 2)

dc

External clock (fosc + 2)
Cycle Time

tcyc

1000

-

ns

STOP Recovery Startup Time (Crystal Oscillator)

tlLCH

-

100

ms

tRL

1.5

-

tcyc

tRESL
tTH, tTL
tTLTL

4.0
250
(refer to NOTE 2)

tlLlH

250

tlLlL

(refer to NOTE 3)

tOH,tOL

200

RESET Pulse Width, Excluding Power-Up
Capture/Compare Timer
Resolution (refer to NOTE 1)
Input Capture Pulse Width
Input Capture Pulse Period
Interrupt Pulse Width Low (Edge Triggered)
Interrupt Pulse Period
OSC1 Pulse Width

-

-

tcyc
ns
tcyc
ns
tcyc
ns

NOTES:
1. Because a 2-bit prescaler in the capture/compare timer must count four internal cycles (tcyc), this is the
limiting minimum factor in determining the timer resolution.
2. The period tTLTL should not be less than the number of cycles it takes to execute the capture interrupt service
routine plus 24 tcyc.
3. The period tlLlL should not be less than the number of cycles it takes to execute the interrupt service routine
plus 21 tcyc.

MC68HC05P1

ELECTRICAL

SPECIFICATIONS

MOTOROLA
8-9

VDD

c;<

VDD 'THRESHOLD (TYPICALLYl-2Vj

I

OSCl PIN

I

.~~::~::~~~:~~~
I...

4064 t eye

>1

...-, ......·----1

INTERNAL
,/'
I
CLOCK .~~:: _______ I
INTERNAL
ADDRESS
BUS

,,,.. ........ '

",

.~~:: ______ _

INTE~~~k
BUS

,
I

/,,/,/
________ _

.~~

NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. An internal paR reset is triggered as V DO rises through a threshold (typically 1-2 V).

Figure 8-9. Power-On Reset Timing

INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
INTERNAL
DATA
BUS

~

RESET

~

~______~

-

\r--~'t-L-

NOTES:
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. The next rising edge of the internal processor clock after the rising edge of RESET initiates the reset sequence.

Figure 8-10. External Reset Timing

MOTOROLA
8-10

ELECTRICAL

SPECIFICATIONS

MC68HC05P1

SECTION 9
MECHANICAL SPECIFICATIONS
This section describes the dimensions of the DIP (Dual-In-line Package) and
SOIC (Small Outline Integrated Circuit) MCU packages.

9.1 Dual-In-Line Package (DIP)
P SUFFIX
PLASTIC PACKAGE
CASE 710-02

T

~rr-T"T""'T"'T'T""'T"'T""'T"rT"T'""'T""1

I

~I

A

E

c

~;!

-~H~

JGL

fC---L.--~

~ ~ J~~~nHO:'"

NOTES:
1. POSITIONAL TOLERANCE OF LEADS
(D). SHALL BE WITHIN 0.25mm (0.010)
AT MAXIMUM MATERIAL CONDITION.
IN RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

DIM
A
B
C
D
F
G
H

J
K
L
M
N

MILLIMETERS
MIN MAX

INCHES
MIN MAX

36.45 37.21
13.72 14.22
5.08
3.94
0.36
0.56
1.02
1.52
2.54BSC
1.65
2.16
0.20 I 0.38
2.92 I 3.43
15.24BSC
00
150
0.51
1.02

1.435 1,465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
O.l00BSC
0.065 I 0.085
0.008 I 0.015
0.115 I 0.135
O.600BSC
00 I 150
0.020

I

M

0.040

Figure 9-1. Case 710-02 Dimensions

MC68HC05P1

MECHANICAL SPECIFICATIONS

MOTOROLA
9-1

9.2 Small Outline Integrated Circuit (SOIC)
OW SUFFIX
SMALL OUTLINE INTEGRATED CIRCUIT
CASE 751F-02

1-$-1

0.25 (0.010)

@ 1B @ 1

14PL

~

[!LEb~H~~H~H~H~H;:;;H;:;;H~H~H~H~H~H~H~d
L-J

Ii

L-J

L-J

L-J

L-J

L-J

L-JL-J

L-J

L-J

L-J

L-J

L-J

t

c

KJ t

lrRX450

~~~~G Ldl (
~M

-4 ~D28PL
1-$-1

0.25(0.010)

)\Sl

F 1/ t

--1 ~
® 1T 1B ® IA ® 1

NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. CONTROLLING DIMENSION: MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (O.OOS)
PER SIDE.

DIM

MILLIMETERS
MIN MAX

INCHES
MIN
MAX

A
B
C
D
F
G
J
K
M
P
R

17.80
18.05
7.40
7.80
2.35
2.S5
0.35
0.49
0.90
0.50
1.27BSC
0.25
0.32
0.25
0.10
00
70
10.05
10.55
0.25
0.75

0.701
0.710
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050BSC
0.010
0.012
0.004
0.009
00
70
0.395
0.415
0.010
0.029

Figure 9·2. Case 751 F·02 Dimensions

MOTOROLA
9-2

MECHANICAL

SPECIFICATIONS

MC68HC05P1

SECTION 10
ORDERING INFORMATION
Use the information contained in this section to order the MCU.

10.1 ROM Pattern Media

Ordering information can be delivered to Motorola in the following media:
o

o

MSTM-DOS1 or PC-DOS flexible disk (360K)
EPROM(s) 2764, MCM68764, MCM68766

To initiate a ROM pattern for the MCU, first contact the local field service office, a
sales person, or a Motorola representative.

10.1.1 Flexible Disks

A flexible disk containing the customer's program (using positive logic for
address and data), can be submitted for pattern generation. Clearly label the
disk with the customer's name, data, project or product name, and the name of
the file containing the pattern.
In addition to the program pattern, a file containing the program source code list
can be included. This data is kept confidential and used to expedite the
process in case of any difficulty with the pattern file.
MS-DOS is the Microsoft Disk Operating System. PC-DOS is the IBM®2
Personal Computer (PC) Disk Operating System. Disks submitted must be
standard density (360K) double-sided 5-1/4 in. The disks must contain object
file code in Motorola's S-record format, a character-based object file format
generated by M6805 cross assemblers and linkers on IBM PC-style machines.

1MS-DOS is a trademark of Microsoft, Inc.
21BM is a registered trademark of International Business Machines Corporation.

MC68HC05P1

ORDERING INFORMATION

MOTOROLA
10-1

10.1.2 EPROMs
A type 2764, 68764, or 68766 EPROM containing the customer's program
(using positive logic for address and data), can be submitted for pattern
generation. User ROM is programmed at EPROM addresses $0020 through
$004F (page zero) and $0100 through $08FF with vectors at addresses $1 FFO
to $1 FFF. Set at logical zero all unused bytes, including those in the user's
space. For shipment to Motorola, pack EPROMs securely in a conductive Ie
carrier. Do not package the EPROMs in a Styrofoam container.

10.2 ROM Pattern Verification

10.2.1 Verification Media
All original pattern media are filed for contractual purposes and are not
returned. A computer list of the ROM code is generated and returned along with
a listing verification form. Thoroughly check the list, and complete, sign and
return the verification form to Motorola. The signed verification form constitutes
the contractual agreement for the creation of the customer mask. To aid in the
verification process, Motorola programs the customer-supplied blank EPROMs
or DOS disks from the data file used to create the custom mask.

10.2.2 ROM Verification Units (RVUs)
Ten RVUs containing the customer's ROM pattern are sent for program
verification. These units are made using the custom mask, but are for the
purpose of ROM verification only. For expediency, the RVUs are unmarked,
packaged in ceramic, and tested with 5 V at room temperature. These RVUs
are free of charge with the minimum order quantity, but are not production parts.
RVUs are not backed or guaranteed by Motorola Quality Assurance.

10.3 MC Order Numbers
Table 10-1 provides ordering information for available package types.

Table 10-1. MC Order Numbers

MOTOROLA
10-2

Package Type

Temperature

Plastic DIP

O·Cto+ 70·C

MC68HC05P1 P

SOIC

O·Cto+ 70·C

MC68HC05P1DW

ORDERING INFORMATION

MC Order Number

MC68HC05P1

MC68HC05P1 MCU ORDERING FORM
Customer PO Number
------------------Customer Company
Date

Address
City ___________________________ State _____________ Zip
Country
Phone

-------------------------------------------

Extension

Customer Contact Person
Customer Part Number (if applicable - 12 characters maximum)
Application
Internal Oscillator Input:
Crystal/Resonator

Interru,e!...Jrigger:
U Edge-Sensitive

o

o

o

Resistor

Edge- and Level-Sensitive

TemRerature Range:
0 to 70·C (Standard)

o

o

--40 to +85°C

Special Electrical Provisions:
(Customer specifications required)
Pattern Media:
MS-DOS Disk File

o

D

PC-DOS Disk File

D

Other

D

2764 EPROM

D

MCM68764 EPROM

D

MCM68766 EPROM

(Requires prior factory approval)
Device Marking:
Motorola Standard
Motorola Logo
Motorola Part Number
Mask and Datecode

o

D

o

Standard with Customer Part Number
Motorola Logo
Motorola Part Number
Customer Part Number
Mask and Datecode

Other
_______________________ Device marking other than the two standard
_______________________ forms requires prior factory approval.

__________--=-=-::-:-:-:=-:-:=,--_ _ _ _ _ _ _

(SIGNATURE)
__________--:=-:=:-:-:::::-::=:--_______

(SIGNATURE)

Device to be tested to Motorola data sheet
specifications. Customer part number, if used as
part of marking, is for reference purposes only.
Device to be tested to customer specifications. (Customer
specifications required)

ONLY ONE SIGNATURE IS REQUIRED TO PROCESS THIS ORDERING FORM.

MC68HC05P1

ORDERING INFORMATION

MOTOROLA
10-3

MOTOROLA
10-4

ORDERING INFORMATION

MC68HC05P1

A23036-1

PRINTED IN USA

1/91

IMPERIAL LITHO

C76732

18,000

Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No.2 Dai King Street, Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong.

®

MOTOROLA



---

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