M68HC11E/D Motorola MC68HC11E Family

• Revision History
• List of Sections
• Table of Contents
• List of Figures
• List of Tables
• Section 1. General Description
  • 1.1 Contents
  • 1.2 Introduction
  • 1.3 Features
  • 1.4 Structure
• Section 2. Pin Descriptions
  • 2.1 Contents
  • 2.2 Introduction
  • 2.3 VDD and VSS
  • 2.4 RESET
  • 2.5 Crystal Driver and External Clock Input (XTAL and EXTAL)
  • 2.6 E-Clock Output (E)
  • 2.7 Interrupt Request (IRQ)
  • 2.8 Non-Maskable Interrupt (XIRQ/VPPE)
  • 2.9 MODA and MODB (MODA/LIR and MODB/VSTBY)
  • 2.10 VRL and VRH
  • 2.11 STRA/AS
  • 2.12 STRB/R/W
  • 2.13 Port Signals
    • 2.13.1 Port A
    • 2.13.2 Port B
    • 2.13.3 Port C
    • 2.13.4 Port D
    • 2.13.5 Port E
• Section 3. Central Processor Unit (CPU)
  • 3.1 Contents
  • 3.2 Introduction
  • 3.3 CPU Registers
    • 3.3.1 Accumulators A, B, and D
    • 3.3.2 Index Register X (IX)
    • 3.3.3 Index Register Y (IY)
    • 3.3.4 Stack Pointer (SP)
    • 3.3.5 Program Counter (PC)
    • 3.3.6 Condition Code Register (CCR)
      • 3.3.6.1 Carry/Borrow (C)
      • 3.3.6.2 Overflow (V)
      • 3.3.6.3 Zero (Z)
      • 3.3.6.4 Negative (N)
      • 3.3.6.5 Interrupt Mask (I)
      • 3.3.6.6 Half Carry (H)
      • 3.3.6.7 X Interrupt Mask (X)
      • 3.3.6.8 STOP Disable (S)
  • 3.4 Data Types
  • 3.5 Opcodes and Operands
  • 3.6 Addressing Modes
    • 3.6.1 Immediate
    • 3.6.2 Direct
    • 3.6.3 Extended
    • 3.6.4 Indexed
    • 3.6.5 Inherent
    • 3.6.6 Relative
  • 3.7 Instruction Set
• Section 4. Operating Modes and On-Chip Memory
  • 4.1 Contents
  • 4.2 Introduction
  • 4.3 Operating Modes
    • 4.3.1 Single-Chip Mode
    • 4.3.2 Expanded Mode
    • 4.3.3 Test Mode
    • 4.3.4 Bootstrap Mode
  • 4.4 Memory Map
    • 4.4.1 RAM and Input/Output Mapping
    • 4.4.2 Mode Selection
    • 4.4.3 System Initialization
      • 4.4.3.1 System Configuration Register
      • 4.4.3.2 RAM and I/O Mapping Register
      • 4.4.3.3 System Configuration Options Register
  • 4.5 EPROM/OTPROM
    • 4.5.1 Programming an Individual EPROM Address
    • 4.5.2 Programming the EPROM with Downloaded Data
    • 4.5.3 EPROM and EEPROM Programming Control Register
  • 4.6 EEPROM
    • 4.6.1 EEPROM and CONFIG Programming and Erasure
      • 4.6.1.1 Block Protect Register
      • 4.6.1.2 EPROM and EEPROM Programming Control Register
      • 4.6.1.3 EEPROM Bulk Erase
      • 4.6.1.4 EEPROM Row Erase
      • 4.6.1.5 EEPROM Byte Erase
      • 4.6.1.6 CONFIG Register Programming
    • 4.6.2 EEPROM Security
• Section 5. Resets and Interrupts
  • 5.1 Contents
  • 5.2 Introduction
  • 5.3 Resets
    • 5.3.1 Power-On Reset (POR)
    • 5.3.2 External Reset (RESET)
    • 5.3.3 Computer Operating Properly (COP) Reset
    • 5.3.4 Clock Monitor Reset
    • 5.3.5 System Configuration Options Register
    • 5.3.6 Configuration Control Register
  • 5.4 Effects of Reset
    • 5.4.1 Central Processor Unit (CPU)
    • 5.4.2 Memory Map
    • 5.4.3 Timer
    • 5.4.4 Real-Time Interrupt (RTI)
    • 5.4.5 Pulse Accumulator
    • 5.4.6 Computer Operating Properly (COP)
    • 5.4.7 Serial Communications Interface (SCI)
    • 5.4.8 Serial Peripheral Interface (SPI)
    • 5.4.9 Analog-to-Digital (A/D) Converter
    • 5.4.10 System
  • 5.5 Reset and Interrupt Priority
    • 5.5.1 Highest Priority Interrupt and Miscellaneous Register
  • 5.6 Interrupts
    • 5.6.1 Interrupt Recognition and Register Stacking
    • 5.6.2 Non-Maskable Interrupt Request (XIRQ)
    • 5.6.3 Illegal Opcode Trap
    • 5.6.4 Software Interrupt (SWI)
    • 5.6.5 Maskable Interrupts
    • 5.6.6 Reset and Interrupt Processing
  • 5.7 Low-Power Operation
    • 5.7.1 Wait Mode
    • 5.7.2 Stop Mode
• Section 6. Parallel Input/Output (I/O) Ports
  • 6.1 Contents
  • 6.2 Introduction
  • 6.3 Port A
  • 6.4 Port B
  • 6.5 Port C
  • 6.6 Port D
  • 6.7 Port E
  • 6.8 Handshake Protocol
  • 6.9 Parallel I/O Control Register
• Section 7. Serial Communications Interface (SCI)
  • 7.1 Contents
  • 7.2 Introduction
  • 7.3 Data Format
  • 7.4 Transmit Operation
  • 7.5 Receive Operation
  • 7.6 Wakeup Feature
    • 7.6.1 Idle-Line Wakeup
    • 7.6.2 Address-Mark Wakeup
  • 7.7 SCI Error Detection
  • 7.8 SCI Registers
    • 7.8.1 Serial Communications Data Register
    • 7.8.2 Serial Communications Control Register 1
    • 7.8.3 Serial Communications Control Register 2
    • 7.8.4 Serial Communication Status Register
    • 7.8.5 Baud Rate Register
  • 7.9 Status Flags and Interrupts
  • 7.10 Receiver Flags
• Section 8. Serial Peripheral Interface (SPI)
  • 8.1 Contents
  • 8.2 Introduction
  • 8.3 Functional Description
  • 8.4 SPI Transfer Formats
  • 8.5 Clock Phase and Polarity Controls
  • 8.6 SPI Signals
    • 8.6.1 Master In/Slave Out
    • 8.6.2 Master Out/Slave In
    • 8.6.3 Serial Clock
    • 8.6.4 Slave Select
  • 8.7 SPI System Errors
  • 8.8 SPI Registers
    • 8.8.1 Serial Peripheral Control Register
    • 8.8.2 Serial Peripheral Status Register
    • 8.8.3 Serial Peripheral Data I/O Register
• Section 9. Timing System
  • 9.1 Contents
  • 9.2 Introduction
  • 9.3 Timer Structure
  • 9.4 Input Capture
    • 9.4.1 Timer Control Register 2
    • 9.4.2 Timer Input Capture Registers
    • 9.4.3 Timer Input Capture 4/Output Compare 5 Register
  • 9.5 Output Compare
    • 9.5.1 Timer Output Compare Registers
    • 9.5.2 Timer Compare Force Register
    • 9.5.3 Output Compare Mask Register
    • 9.5.4 Output Compare Data Register
    • 9.5.5 Timer Counter Register
    • 9.5.6 Timer Control Register 1
    • 9.5.7 Timer Interrupt Mask 1 Register
    • 9.5.8 Timer Interrupt Flag 1 Register
    • 9.5.9 Timer Interrupt Mask 2 Register
    • 9.5.10 Timer Interrupt Flag Register 2
  • 9.6 Real-Time Interrupt (RTI)
    • 9.6.1 Timer Interrupt Mask Register 2
    • 9.6.2 Timer Interrupt Flag Register 2
    • 9.6.3 Pulse Accumulator Control Register
  • 9.7 Computer Operating Properly (COP) Watchdog Function
  • 9.8 Pulse Accumulator
    • 9.8.1 Pulse Accumulator Control Register
    • 9.8.2 Pulse Accumulator Count Register
    • 9.8.3 Pulse Accumulator Status and Interrupt Bits
• Section 10. Analog-to-Digital (A/D) Converter
  • 10.1 Contents
  • 10.2 Introduction
  • 10.3 Overview
    • 10.3.1 Multiplexer
    • 10.3.2 Analog Converter
    • 10.3.3 Digital Control
    • 10.3.4 Result Registers
    • 10.3.5 A/D Converter Clocks
    • 10.3.6 Conversion Sequence
  • 10.4 A/D Converter Power-Up and Clock Select
  • 10.5 Conversion Process
  • 10.6 Channel Assignments
  • 10.7 Single-Channel Operation
  • 10.8 Multiple-Channel Operation
  • 10.9 Operation in Stop and Wait Modes
  • 10.10 A/D Control/Status Register
  • 10.11 A/D Converter Result Registers
• Section 11. Electrical Characteristics
  • 11.1 Contents
  • 11.2 Introduction
  • 11.3 Maximum Ratings for Standard and Extended Voltage Devices
  • 11.4 Functional Operating Range
  • 11.5 Thermal Characteristics
  • 11.6 DC Electrical Characteristics
  • 11.7 Supply Currents and Power Dissipation
  • 11.8 MC68L11E9/E20 DC Electrical Characteristics
  • 11.9 MC68L11E9/E20 Supply Currents and Power Dissipation
  • 11.10 Control Timing
  • 11.11 MC68L11E9/E20 Control Timing
  • 11.12 Peripheral Port Timing
  • 11.13 MC68L11E9/E20 Peripheral Port Timing
  • 11.14 Analog-to-Digital Converter Characteristics
  • 11.15 MC68L11E9/E20 Analog-to-Digital Converter Characteristics
  • 11.16 Expansion Bus Timing Characteristics
  • 11.17 MC68L11E9/E20 Expansion Bus Timing Characteristics
  • 11.18 Serial Peripheral Interface Timing Characteristics
  • 11.19 MC68L11E9/E20 Serial Peirpheral Interface Characteristics
  • 11.20 EEPROM Characteristics
  • 11.21 MC68L11E9/E20 EEPROM Characteristics
  • 11.22 EPROM Characteristics
• Section 12. Mechanical Data
  • 12.1 Contents
  • 12.2 Introduction
  • 12.3 52-Pin Plastic-Leaded Chip Carrier (Case 778)
  • 12.4 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B)
  • 12.5 64-Pin Quad Flat Pack (Case 840C)
  • 12.6 52-Pin Thin Quad Flat Pack (Case 848D)
  • 12.7 56-Pin Dual in-Line Package (Case #859)
  • 12.8 48-Pin Plastic DIP (Case 767)
• Section 13. Ordering Information
  • 13.1 Contents
  • 13.2 Introduction
  • 13.3 Standard Device Ordering Information
  • 13.4 Custom ROM Device Ordering Information
  • 13.5 Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc)
• Appendix A. Development Support
  • A.1 Contents
  • A.2 Introduction
  • A.3 Motorola M68HC11 E-Series Development Tools
  • A.4 EVS — Evaluation System
  • A.5 Motorola Modular Development System (MMDS11)
  • A.6 SPGMR11 — Serial Programmer for M68HC11 MCUs
• Appendix B. EVBU Schematic
• AN1060
  • Introduction
  • Basic Bootstrap Mode
  • Bootstrap Mode Logic
  • Boot ROM Firmware
  • Automatic Selection of Baud Rate
  • Main Bootloader Program
  • UPLOAD Utility
  • EPROM Programming Utility
  • Allowing for Bootstrap Mode
    • Mode Select Pins
    • RESET
    • RxD Pin
    • TxD Pin
    • Other
  • Driving Boot Mode from Another M68HC11
  • Listing 1. MCU-to-MCU Duplicator Program
  • Driving Boot Mode from a Personal Computer
    • Hardware
    • Software
    • Modifications
    • Operation
  • Listing 2. BASIC Program for Personal Computer
  • Common Bootstrap Mode Problems
    • Reset Conditions vs. Conditions as Bootloaded Program Starts
    • Connecting RxD to VSS Does Not Cause the SCI to Receive a Break
    • $FF Character Is Required before Loading into RAM
    • Original M68HC11 Versions Required Exactly 256 Bytes to be Downloaded to RAM
    • Variable-Length Download
    • EPROM/OTP Versions of M68HC11 Have an EPROM Emulation Mode
    • Bootloading a Program to Perform a ROM Checksum
    • Inherent Delays Caused by Double Buffering of SCI Data
  • Boot ROM Variations
  • Commented Boot ROM Listing
  • Listing 3. MC68HC711E9 Bootloader ROM
• EB184
  • Introduction
  • To Execute the Program
• EB188
  • Introduction
  • To Execute the Program
• EB296
  • Introduction
  • Programming Procedure