MCS 4 Assembly Language Programming Manual Dec73
MCS-4_Assembly_Language_Programming_Manual_Dec73 MCS-4_Assembly_Language_Programming_Manual_Dec73
msc-4-asm-manual-1973
msc-4-asm-manual-1973
MCST%7E4%20(Intel%204004)%20Assembly%20Language%20Programming%20Manual%20PRELIMINARY%20EDITION
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INTEL CORP. 3065 Bowers Avenue, Santa Clara, California 95051 • (408) 246-7501
Assemblv
Language Programming
Manual
MCST~4
PRELIMINARY EDITION
December 1973
"@ I ntel Corporation 1973
The INTELLEC 4 Microcomputer System
Programming Manual
PAGE No.
1.0
INTRODUCTION . • . • • • . • • . • • • • • • • • • • • • •
1-1
2.0
COMPUTER ORGANIZATION
2-1
2.1
2.2
2.3
2-2
WORKI NG REGl STERS (INDEX REGISTERS)
THE ACCUMULATOR
• • • . • • • . • •
MEMORIES • • • • . • • • • •
2.3.1
2.3.2
·2.3.3
2.4
2.5
2.6
2.7
THE STACK • • • • • • • • • • • • • '" • . • •
INPUT/OUTPUT
.••.••.
••
••
COMPUTER PROGRAM REPRESENTATION IN MEMORY
MEMORY ADDRESSING • • • •
• ••
2.7. 1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.8
3.0
READ-ONLY MEMORY
PROGRAM RANDOM ACCESS MEMORY . • .
DATA RANDOM ACCESS MEMORY
DIRECT ADDRESSING
SAME PAGE ADDRESSING
INDIRECT ADDRESSING
.
IMMEDIATE ADDRESSING
PROGRAM RAM ADDRESSING
DATA RMv1 ADDRESSING . .
.
SUBROUTINES AND USE OF THE STACK
FOR ADDRESSING
3.1
2-3
2-4
2-5
2-7
2-9
2-10
2-13
2-13
2-14
2-15
2-16
2-16
2-16
2-17
2-20
CARRY BIT
THE 4004 INSTR.UCTION SET
2-3
2-3
•••
3-1
ASSEMBLY LANGUAGE
3-1
3.1 .1
3. 1 .2
3-1
HOW ASSEMBLY LANGUAGE IS USED
STATEMENT MNEMONICS
i
3-4
rn'.bl\ffiILJE
(Q)}f'
(G;(Q)mJrn'I:Emf1rfB> -- (Continued)
The INTELLEC 4 Microcomputer System
Programming Manual
PAGE No.
3.1.3
3.1.4
3.1.5
3.1 • 6
3.2
DATA STATEMENTS
3.2.1
3.2.2
3.3
3.3.2
TWO'S COMPLE!v1ENT
CONSTANT DATA
INC
FIN
INCREMENT REGISTER
FETCH INDIRECT • • •
INDEX REGISTER TO ACCUMULATOR INSTRUCTIONS.
3.4.1
3.4.2
3.4.3
3.4.4
3.5
••••
INDEX REGISTER INSTRUCTIONS
3.3.1
3.4
LAB EL FIELD • • •
CODE FIELD . • •
OPERAND FIELD
COMMENT FIELD
ADD ADD REGISTER TO ACCUMULATOR
WITH CARRY • • • • • • • • . . . •
SUB SUBTRACT REGISTER FROM ACCUMULATORWITH BORROW • . • • • • •
LD
LOAD ACCUMULATOR • • • . • • • .
XCH EXCHANGE REGISTER AND ACCUMULATOR . . • • •
3-5
3-6
3-7
3-11
3-12
3-12
3-15
3-16
3-17
3-18
3-20
3-21 .
3-22
3-24
3-25
ACCUMULATOR INSTRUCTIONS.
3-26
3.5.1
3-27
3-27
3.5.6
CLB
CLC
lAC
CMC
CMA
RAL
3.5.7
RAR
3.5.2
3.5'-3
3.5.4
3.5.5
3.5.8
3.5.9
TCC
DAC
CLEAR BOTH ••
CLEAR CARRY. •
INCREMENT ACCUMULATOR • • • •
COMPLEMENT CARRY • • • . •
COMPLEMENT ACCUMULATOR •
ROTATE ACCUMULATOR LEFT
TH ROUGH CARRY ~ • . • • . • •
ROTATE ACCUMULATOR RIGHT
THROUGH CARRY . • • • • • .
TRANSMIT CARRY AND CLEAR.
DECREMENT ACCUMULATOR •
ii
3-28
3-29
3-29
3-30
3-31
3-32
3-32
TABLE
OF
CONTENTS --
(Continued)
The INTELLEC 4 Microcomputer System
Programming Manual
PAGE No.
3.5.10
3.5.11
3.5.12
3.5.13
3. 6
3.7
3.8
3.10
3.11
TRANSFER CARRY SUBTRACT • • • • •
SET CARRY . • • . • • • • • . . . •
DECIMAL ADJUST ACCUMULATOR . .
KEYBOARD PROCESS ••
3-33
3-34
3-34
3-35
IMMEDIATE INSTRUCTIONS • • . •
3-36
3. 6. 1
3.6.2
3-36
3-37
FIM
LDM
FETCH IMMEDIATE
LOAD ACCUMULATOR. • •
TRANSFER OF CONTROL INSTRUCTIONS
3-38
3,7.1
3.7.2
3.7.3
3.7.4
3-38
3-40
3-41
3-43
JUN
JIN
JCN
ISZ
JUMP UNCONDITIONALLY
JUMP INDIRECT • • • • ...
JUMP ON CONDITION
INCREMENT AND SKIP IF ZERO .
SUBROUTINE LINKAGE COMMANDS
3.8.1
3.8.2
3.9
TCS
STC
DAA
KBP
JMS
BBL
~
,
JUMP TO SUBROUTINE . '
BRANCH BACK AND LOAD
3-45
3-45
3-46
NOP INSTRUCTION NO OPERATION . .
:tv1EMORY SELECTION INST!{UCTIONS
3-48
3-48
3. 10.1
3.10.2
3-48
3-50
DCL DESIGNATE COMMAND LINE
SRC SEND REGISTER CONTROL .
INPUT/OUTPUT RAM INSTRUCTIONS
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.11.6
•..
RDM READ DATA RAM DATA CHARACTER •.
RDn READ DATA RAM STATUS CHARACTER •
RDR READ ROM PORT . . . . . . . . . . .
WRM VvRITE DATA RAlvI CHARACTER • . . .
WRn WRITE DATA RAM STATUS CHARACTEH
vVMP WRITE RAIvI PORT . . . . . . . . . . .
iii
3-53
3-54
3-54
3-55
3-56
3-57
3-58
TAB LEO F
G 0 N TEN T S - -
( Continu ed )
The INTELLEC 4 Microcomputer System
Programming Manual
PAGE No.
3.11. 7
3.11.8
3.11.9
WRR
ADM
SBM
3.11.10 WPM
3.12
PSEUDO INSTRUCTION
3.12.1
3.12.2
4.0
WRITE ROM PORT • • • • • • • • • •
ADD DATA RAM TO ACCUMULATOR
WITH CARRY . • • . • • . •
SUBTRACT DATA RAM FROM
MEMORY WITH BORROW
WRITE PROGRAM RAM
•••••
EQUATE FUNCTION
ORIGIN FUNCTION
3-59
3-60
3-61
3-62
3-65
3-65
3-66
PROGRAMMING TECHNIQUES • • • •
4-1
4.1
4.2
4.3
4-3
4-5
4.4
CROSSING PAGE BOUNDARIES
SUBROUTINES • • • • . . . • •
BRANCH TABLE PSEUDOSUBROUTINE
LOGICAL OPERATIONS
4.4.1
4.4.2
4.4.3
4.5
4.6
4.7
4.8
4.9
APPENDIX
APPENDIX
APPENDIX
APPENDIX
"A"
"B"
"C"
"DII
LOGICAL "AND" .
LOGICAL II OR"
• . • .
LOGICAL "XOR" EXCLUSIVE-OR
4-1
4-8
4-8
4-9
4-11
MULTI-DIGIT ADDITION •.
MULTI-DIGIT SUBTRACTION
DECIMAL ADDITION
DECIMAL SUBTRACTION. •
FLOATING POINT NUMBERS
4-13
INSTRUCTION SUMMARY
INSTRUCTION MACHINE CODES
ASCII TABLES . . . • . . • • . •
. • • • .
BINARY-DECIMAL-HEXADECIMAL CONVERSION
TABLES • • • • • . • • . • • • • • • . • • • • .
A-I
B-1
C-1
iv
4-15
4-18
4-20
4-24
D-l
-- TERMS
AND
ABBREVIATIONS --
Address
A 12 bit number as signed to a read -only-memory or program
random -access memory location corresponding to its sequential
position.
Bit
The smallest unit of information which can be represented.
bit may be in one of two states 0 or 1).
(A
I
Byte
A group of 8 contiguous bits occupying a single memory location.
Character
A group of 4 contiguous bits of data.
Instruction The smallest single operation that the computer can be directed
to execute.
Obj ect
Program
A program which can be loaded directly into the computer's memory
and which requires no alteration before execution. An object program
is usually on paper tape and is produced by assembling
a source program. Instructions are represented by binary machine
code in an object program.
I
Program
A sequence of instructions which l taken as a group I allow the
computer to accomplish a desired task.
Source
Program
A program which is readable by a programmer but which must be
transformed into object program format before it can be loaded into
the computer and executed. Instructions in an as sembly language
source program are represented by their assembly language mnemonic.
System
Program
A program written to help in the process of creating user programs.
User
Program
A program written by the user to make the computer perform any
nnnB
nnnH
nnn represents a number in binary format.
nnn represents a number in hexadecimal format.
desired ta sk.
Note:
All numbers in this manual are assumed to be decimal unless otherwise specified.
A representation of a byte in memory. Bits which are fixed as
o or 1 are indicated by 0 or 1; bits vvhich may be either 0 or 1
in different circumstances are represented by letters; thus RP
represents a three-bit field which contains one of the eight
possible combinations of zeroes and ones.
1.0
INTRODUCTION
This manual has been written to help the reader program the INTEL 4004
microcomputer in assembly language, and to show how it is economical and
practical to do so. Accordingly this manual assumes that the reader has a good
understanding of logic, but may be unfamiliar with programming concepts.
I
For those readers vlho do understand programming concepts, several features of the
INTEL 4004 microcomputer are described below. They include:
• 4 bit pa.rallel CPU on a single chip.
• 46 instructions, including conditional branching,
subroutine capability and binary and decimal
arithmetic modes.
I
• Direct addressing for 32,768 bits of read-only
memory, 5120 bits of data random-access memory
and 32 768 bits of program random-access
memory .
I
• Sixteen 4 -bit index registers and a three 12 -bit
register stack.
INTEL 4004 microcomputer users will have widely differing programming needs.
Some users may wish to write a few short programs, while other users may have
extensive programming requirements.
For the user with limited programming needs two system programs resident on the
INTELLEC 4 (Intel! s development system for the MCS-4microcomputer) are provided;
they are an Assembler and a System Monitor. Use of the INTELLEC 4 and its system
programs is described in the INTELLEC 4 Operator's Manual.
I
For the user with extensive programming needs, cross assemblers are available
which allow programs to be generated on a computer having a FORTRAN compiler
whose word size is 32 bits or greater, limiting INTELLEC 4 use to final checkout of
programs only.
1 --1
2.0
COMPUTER ORGANIZATION
This section provides the programmer with a functional overview of the 4004
computer. Information is presented in this section at a level that provides a programmer with necessary background in order to write efficient programs.
To the programmer the computer is represented as consisting of the following
parts:
I
(1)
Sixteen working registers which serve a s temporary storage for data I
and provide the means for addressing memory.'
(2 )
The accumulator in vvhich data is processed.
(3)
Memories which may hold program instructions or data (or sometimes
both) and which must be addressed location by location in order to
access stored information.
I
I
I
(4 )
The stack which is a device used to facilitate execution of subroutines,
as described later in this section.
(5 )
Input/Output I which is the interface between a program and the outside
world.
I
2-1
2.1
WORKING REGISTERS
(INDEX REGISTERS)
The 4004 provides the programmer with sixteen 4-bit registers. These may be referenced individually by the integers 0 through 15 or as 8 register pairs by the even
integers from 0 through 14. The register pairs may also be referenced by the symbols
OP through 7P. These correspondences are shown as follows:
I
INDIVIDUAL REGISTER REFERENCE
Register 0
....
0
1
.....
Register 1
Register 2
~
2
3
.....
Register 3
Register 4
~
4
5
.......
Register 5
Register 6
....
6
7
......
8
9
...
Register 7
10
11
.....
Register 11
12
'13
14
15
Register 8
Register 10
Register 12
Register 14
...
....
..
--...
Register 9
Register 13
Regi'ster 15
REGISTER PAIR REFERENCE
o or OP
...
0
1
Register Pair 2 or IP
....
2
3
Register Pair
Regi ster Pair 4 or 2P
..
4
5
Register Pair
....
6
7
8
9
6 or 3P
Register Pair 8 or 4P
)III
Register Pair 10 or SP
....
10
11
Register Pair 12 or 6P
....
12
13
14
15
Register Pair 14 or 7P
..
2-2
2. 2
THE ACCUMULATOR
The accumulator is a special 4-bit register in which data may be transformed by
program instructions.
2.3
MEMORIES
The 4004 can be used with three different types of memory which have different
organizations and characteristics, and are used for different purposes. These
are described below.
2.3.1
READ-ONLY MEMORY
Read-only memory (ROM) is used for storing program instructions and constant
data which is never changed by the program. This is because the program can
read locations in ROM, but can never alter (write) ROM locations.
ROM may be visualized as in Figure 2-1, as a sequence of bytes, each of which
may store 8 bits (two hexadecimal digits). Up to 4096 bytes of ROM may be present, and an individual byte is addressed by its sequential number between 0 and
4095.
ROM is further divided into pages each of which contains 256 bytes. Thus locations
o through 255 comprise page 0 of ROM location 256 through 511 comprise page
1 and so on.
I
I
2-3
DECIMAL
ADDRESS
0
HEXADECIMAL
ADDRESS
~
8 bits
----
0
PAGE 0
255
256
FF
100
------------------------PAGE 1
511
IFF
------------- •
3840
FOO --------------
•
PAGE 15
4095
FFF --------------
.,
FIGURE 2-1.
ROM ORGANIZATION
f\s described in Section 3, certain instructions function differently when located
in the last byte (or bytes) of a page than when located elsewhere.
2.3.2
PROGRAM RANDOM ACCESS MEMORY
Program random access memory (RAM) is organized exactly like ROM. 4096
locations are always available, which are used to hold program instructions
or data. Unlike ROM, however, program RAM locations can be altered by
program instructions.
2-4
2.3.3
DATA RANDOM ACCESS MEMORY
As its name implies I data random access memory (DATA RAM) is used for the
temporary storage of data by programs.
Figures 2-2 and 2-3 show how this memory is addressed:
"DCL" INSTRUCTION CHOOSES 1 OF 8
DATA RAM BANKS
/
I
~~
•
•
\
0
DATA RAM
CHIP 0
DATA RAM
CHIP 0
DATA RAM
CHIP 1
DATA RAM
CHIP 1
DATA RAM
CHIP 2
DATA RAM
CHIP 2
DATA RAM
CHIP 2
DATA RAM
CHIP 3
DATA RAM
CHIP 3
DATA RAM
CHIP 3
DATA RAM
BANK 0
DATA RAM
BANK 1
DATA RAM
CHIP 0
.
.
.
.
.
.
FIGURE 2-2.
DATA RAM BANK ORGANIZATION.
2-5
.
DATA RAM
CHIP 1
DATA RAM
BANK 7
Decimal
Addresses
16 Directly Addres sable
4-bit characters per
DATA RAM Register.
Hexadecimal
Addresses
4 Specially Addressable
4 bit status characters
per DATA RAM Register.
, , ._ _ _ _---.JA _ _ _ _ _ _
,
0-15
16-31
32-47
48-63
...
OO-OF
10-1F
20-2F
30-3F
1:111.
111111
DATA
DATA
DATA
DATA
RAM
RAM
RAM
RAM
REGISTER
REGISTER
REGISTER
REGISTER
0
1
2
3
FIG URE 2-3.
DATA RAM CHIP 0 ORGANIZATION
In order to address 0. 4 bit character of DATA RAM, the programmer first uses a
"DeL" instruction as described in Section 3.10.1 to choose one of a maximum of
eight DATA RAM BANKS. An eight bit address is then sent via an "SRC" instruction as described in Section 3.10,2 which chooses one of four DATA RAM CHIPS
within the DATA RAM BANK, one of four 16-character DATA RAM REGISTERS within
the DATA RAM CHIP and one of 16 4-bit characters within the DATA RAM REGISTER.
Within any particular DATA RAM BANK then addres ses 0- 63 indicate which of
the 64 directly addressable characters of DATA RAM CHIP 0 is to be addressed.
Addresses 64-127 correspond to the characters of CHIP I, addresses 128-191
correspond to CHIP 2, and addresses 192-255 correspond to CHIP 3.
I
I
I
In addition, each DATA RAM REGISTER has four 4-bit STATUS characters associated
with it. These status characters may be read and written like the data characters
but are accessed by special instructions as described in Section 3.
I
2-6
2.4
THE STACK
The stack consists of three 12-bit registers used to hold addresses of program instructions. Since progra~s are always run in ROM or program RAM the
stack registers will always refer to ROM locations or program RAM locations.
I
Stack operations consist of writing an address to the stack and reading an address
from the stack. In order to understand the se operations it may be helpful to visualize the stack as three registers on the surface of a cylinder as shown below:
I
I
I
a
represents an address
Each stack register is adjacent to the other two stack registers.
pointer to the next stack register available.
'
The 4004 keeps a
Writing An Address To The StacJs.:
To perform a stack write operation;
(1 )
The address is written into the register indicated by the pointer.
(2 )
The painter is advanced to the next sequential register.
Any register may be used to hold the first address written to the stack. More than
three addresses may be written to the stack; however this will cause a corresponding number of previously stored addresses to be overwritten and lost. This is
illustrated in Figure 2-4.
I
2-7
After 2 Writes
aI bI
......
C
I
After 3 Writes
After 4 Writes
a
a
d
b
b
b
c
c
d represent any 4 memory addres ses •
represents the stack pointer.
FIGURE 2-4.
STACK WRITE OPERATIONS
Storing the fourth address (d) overwrites the first address stored (a).
Reading An Address From The Stack:
To perform a stack read operation;
(1 )
The pOinter is backed up one register.
(2 )
The memory addres s indicated by the pOinter is read.
The address read remains in the stack undisturbed. Thus I if 4 addresses are
written to the stack and then three reads are performed, the stack will appear as
in Figure 2 -5 •
2-8
First read:
Address d is read
d
Second read:
Address c is read
Third read:
Address b is read
§
d
b
b
c
d
b
c
b, c, d represent any 3 memory addres ses .
-repres ents the stack pointer.
,'!'111;-
FIGURE 2-5.
STACK READ OPERATIONS.
Section 2.7.7
2.5
describes how the stack is used by. programs.
INPUT/OUTPUT
Programs communicate with the outside world via 4-bit input or output ports. The
operation of these ports is controlled by special I/O instructions described in Section 3.
These ports are physically located on the same devices which hold ROMs and
DATA RAMs; therefore, they are referred to as ROM ports or RAM ports. These
are totally separate from the instruction or data locations provided in ROM or
RAM, and should not be confused with them.. The ports associated with RAMs may
be used only for output.
2-9
2. 6
COMPUTER PROGRAM REPRESENTATION IN MEMORY
A computer program consists of a sequence of instructions. Each instruction performs an elementary operation such as the movement of data an arithmetic
operation on data, or a change in instruction execution sequence. Instructions are described individually in Section 3.
I
A program will be stored in Read -Only Memory or Program Random Acces s
Memory. It will appear as a sequence of hexadecimal digits which represent the
instructions of the program. The memory address of the instruction being executed
is recorded in a 12-bit register called the Program Counter and thus it is pos sible
to track a program a s it is being executed. After ea ch instruction is executed the
program counter is advanced to the address of the next instruction. Program execution
proceeds sequentially unless a transfer-of-control instruction (jump or skip) is
executed which causes the program counter to be set to a specified address.
Execution then continues sequentially from this new address in memory.
I
I
I
Upon examining the contents of a ROM or program RAM memory location
there is no way of telling whether a byte contains Ln encoded instruction or constant data. For example, the hexadecimal code F2 has been selected to represent
the instruction lAC (increment accumulator). Thu s the hex; value F2 stored in a memory
byte could represent either the instruction lAC or the hex data value F2.
I
I
It is up to the programmer to insure that data is not misinterpreted as an instruction code, but this is Simply done as follows:
Every program ha s a starting memory address, which is the memory address of the
location holding the first instruction to be executed. Just before the first instruction is executed, the program counter will automatically be set to this address,
and this procedure will be repeated for every instruction in the program. 4004
instructions may require 8 or 16 bits for their encoding; in each ca se the program
counter is set to the corresponding address as shown in Figure 2-6.
2-10
MEMORY
ADDRESS
(Hexadecimal)
INSTRUCTION
NUMBER
PROGRAM COUNTER
CONTENTS
(Hexadecimal)
13A
13A
}
1
13B
}
2
3
13E
}
13F
}
4
13F
}
5
140
13C
13D
140
141
13B
13D
FIGURE 2-6.
PROGRAM COUNTER CONTENTS AS INSTRUCTIONS ARE EXECUTED.
In order to avoid errors, the programmer must be sure that a byte of constant data
does not follow an instruction when another instruction is expected. Referring to
Figure 2-6, an instruction is expected in location 13FH, since instruction 4 is to
be executed after instruction 3. If location 13 FH held constant data, the program
would not execute correctly. Therefore, when writing a program, do not place
constant data in between adjacent instructions that are to be executed consecutiv-ely.
A cIa ss of instructions (referred to as transfer-of-control instructions) cause program
execution to branch to an instruction other than the next sequential instruction. The
memory address specified by the transfer of control instruction must be the address
of another instruction; if it is the address of a memory location holding data, the
program will not execute correctly. For example, referring to Figure 2-6, suppose
instruction 2 specifies a jump to location 14 OR and instructions 3 and 4 were replaced by data. Then following execution of instruction 2, the program counter would
be set to 140H and the program would execute correctly. But if, in error, instruction
2 were to specify a jump to 13EH, an error would result since this location now holds
data. Even if instructions 3 and 4 were not altered, a jump to location 13EH would
cau sean error, since this is not the first byte of the instru ction.
I
2-11
Upon reading Section 3, you will see that it is easy to avoid writing an assembly
language program with jump instructions which have erroneous memory addresses.
Information on this subject is given here rather to help the programmer who is debugging programs by entering hexadecimal codes directly into program RAM
(Programs usually exist in ROM I and therefore cannot be altered in this manner).
2-12
2. 7
MEMORY ADDRESSING
By now it will have become apparent that addressing specific memory bytes constitutes an important part of any computer program. There are a number of ways in
which this can be done as described in the following subsections.
I
2.7. 1
DIRECT ADDRESSING
With direct addressing I as the name implies I an instruction provides an exact
memory address. The following instruction provides an example of direct addressing:
"Jump to location3A2 H
lJ
This instruction is represented by 4 hexadecimal digits in RQM or program
RAM. The first digit is a 4, signifying a jump instruction while the final 3 digits
specify the address.
I
This instruction would appear in memory as follows:
ARBITRARY MEMORY
ADDRESS·
(Hexadecimal)
any
any + 1
MEMORY
tJd}
~
J
.
ump 'Instructlon
....._ _ _...)
Address 3A2H specified.
3A2
3A3
3A4
2-13
2.7.2
SAME PAGE ADDRESSING
Some instructions supply two hexadecimal digits which replace the lo·vvest 8 bits
of the program counter addressing a ROM or program RAM location on the
same page as the instruction being executed. (Two addresses are on the same
pcge if the highest order hexadecimal digit of their addresses are equal. See
S e cti on 2. 3 • 1 ) •
I
The following instruction provides an example of same page addressing:
II
Jump on condition 2 to location 3BH of this page.
II
This instruction would appear in memolY a s follows:
MEMORY
MEMORY ADDRESS
(Hexadecimal)
30F
310
l
3AO
3Al
E1
·
~___ code for jump on condition
{ ~I
__
2
address within this page
The identical encoding 120FH if-located at location 501H, would cause a jump to
memory address 50FH.
2-14
2.7.3
INDIRECT ADDRESSING
With indirect addressing an instruction specifies a register pair which in tum holds
an 8 bit value used for same page addressing (Section 2. 7 .2). Suppose that registers
4 and 5 hold the 4-bit hexadecimal numbers 1 and B I respectively. Then the instruction:
I
"Jump indirect to contents of register pair 4"
would appear a s follows:
MEMORY
ADDRESS
(Hexadecimal)
200
21B
21C
MEMORY
~
REGISTER PAIR
4
)lI.-
S·
I
B
17
The 3 indicates a "jump indirect" instruction; the 5 indicates that the address indicated
on this page is held in register pair 4. If register pair 4 had held the hex numbers 3 and
C, a jump to location 23CH would have occurred.
2-15
2.7.4
IMMEDIATE ADDRESSING
An immediate instruction is one that provides its own data.
ample of immediate addres sing:
II
The following is an ex-
Load the accumulator with the hexadecimal number 3" •
This instruction would be coded in memory a s follows:
MEMORY
The digit D signifies a "load accumulator immediatefl instruction; the digit 3 is the
number to be loaded.
2.7.5
PROGRAM RAM ADDRESSING
When a program stores an 8 bit value into a program RAM location a· special
sequence of instructions must be used as described in Section 3.11. 10 {the WPM
instruction) •
2.7. 6 DATA RAM ADDRESSING
To address a location in DATA RAM, the DeL and SRC instructions must be used as
described in Sections 2.3.3 3.10.1, and 3.10.2. When the DeL has chosen a
specific DATA RAM bank, the address of the specific character is held in a register
pair accessed by the SRC instruction.
I
2-10
2.7. 7
SUBROUTINES AND USE OF THE STACK FOR ADDRESSING
Before understanding the purpose or effectiveness of the stack
understand the concept of a subroutine.
I
it is necessary to
Consider a frequently used operation such as addition. The 4004 provides instructions to add one character of data to another, but what if you wish to add numbers
outside the range of 0 to 15 (the range of one character)? Such addition will require
a number of instructions to be executed in sequence. It is quite possible that this
addition routine may be required many times within one program; to repeat the identical code every time it is needed is possible, but very wasteful of memory:
,i
I
Program
,•
I
Addition
,i
•
Program
,
Addition
•••
Program
,
Addition
I
Etc.
2-17
A more efficient means of accessing the addition routine would be to store it once
and find a way of accessing it when needed:
I
I
Program'
Program
l
I
:
-------"":Addltion
-----.
..
~--I
.
Program
t
I
1
1
A frequently accessed routine such as the addition above is called a subroutine,
and the 4004 provides instructions that call subroutines and return from subroutines.
When a subroutine is executed, the sequence of eve41ts may be depicted as follows:
.
.
Main Pro ram
'~all instruction_~........._ _ _-:..~~_
The arrows indicate the execution sequence.
When the" Call" instruction is executed I the address of the" next JJ instruction is
written to the stack (see Section 2.4), and the subroutine is executed. The last
executed instruction of a subroutine will always be a special II Return Instruction"
which reads an address from the stack into the program counter, and thus causes
program execution to continue at -the "Next" instruction as illu strated on the next
page.
2-18
I
Memory
Address
(Hexadecima 1)
C02
C03
C04
COS
C06
FOO
FOI .
F02
F03
Write addres s of next instruction
COSH to the·stack.
In struction
CALL SUBROUTINE
AT F02H""'NEXTINSTRUCTION----------------~
Branch to
subroutine
starting at FO 2 H
FIRST SUBROUTINE INSTRUCTION ......--~----.a
Return to next
instruction
Body of Subroutine
F4E
F4F
RETURN
Read return address
( COS H) from stack.
Since the stack provides three registers subroutines may be nested up to three
deep; for example, the addition subroutine could itself call some other subroutine
and so on. An examination of the sequence of write and read stack operations will
show that the return path will always be identical to the call path, even if the same
subroutine is called at more than one level; however, an attempt to nest subroutines
to a depth of more than 3 will cau se the program to fail, since s·.orne addresses will
have been overwritten.
I
t
2-19
2 •8
CARRY BIT
To make programming easier/ a carry bit is provided by the 4004 to reflect the
results of data operations. The descriptions of individual instructions in Section
3 specify which instructions affect the carry bit and '\¥hether the execution of
the instruction is dependent in any wayan the prior status of the carry bit. The
carry bit is "set" if 1 and" reset" if o.
Certain data operations can cause an overflow out of the high-order 3-bit. For
example/ addition of two hexadecimal digits can give rise to an answer that
does not fit in one digit:
321 0
Bit Number
1 0 1 a
a1 11
A
+7
2J
0001
L..-Carry:::: 1
An operation that results in a carry out of bit 3 will set the carry bit.
An operation that could have resulted· in a carry out of bit 3 but did not will reset
the carry bit.
2-20
3.0
THE 4004 INSTRUCTION SET
This section describes the 4004 assembly language instruction set.
For the reader who understands assembly language, Appendix A provides a complete summary of the 4004 instructions.
For the reader who is not completely familiar with assembly language, this section
describes individual instructions with examples and machine code equivalents.
3.1
ASSEMBLY LANGUAGE
3. 1 • 1
HOW ASSEMBLY LANGUAGE IS USED
Upon examining the contents of read-only memory or program random-access
memory, a program would appear as a sequence of hexaaecimal digits which are
interpreted by the machine a s instruction codes, addresses, or constant data. It is
possible to write a program as a sequence of digits (just as they appear in memory) ,
but that is slow and expensive. For example, several instructions reference memory
to addres s -another instruction:
HEXADECIMAL
MEMORY ADDRESS
332
FO
333
43
334
56
354
20
355
FF
356
60
The above program operates as follows:
3-1
Byte 332H specifies that the accumulator and carty bit are to be cleared.
Bytes 333H and 334H specify that program execution is to continue at location 35 6H.
Byte 356H specifies that register 0 is to be incremented.
Now suppose thqt an error discovered in the program logic neces sitates placing
a new instruction after byte 332H. Program code would have to change as follows:
HEXADECIMAL
MEMORY ADDRESS
332
333
334
335
354
355
356
357
OLD CODE
NEW CODE
FO
FO
43
56
New In s tru ction
43
57
2-D
FF
. 2:0
60
FF
60
Note that many instructions have been moved and as a result some must be changed
to reflect the new addresses of instructions. The potential for making mistakes
is very high and is aggravated by the complete unreadability of the program.
Writing programs in assembly language is the first and most significant step towards economical programming; it provides a readable notation for instructions,
and separates the programmer from a need to know or specify absolute memory
addresses.
Assembly language programs are written as a sequence of instructions which are
converted to executable hexadecimal code by a special program caned an ASSEMB-
LER.
3-2
Assembly language
program written by
programmer
----
ASSEMBLER
PROGRAM
Executable hexadecimal machine
code
-
OBJECT PROGRAM
SOURCE PROGRAM
FIGURE 3-1.
ASSEMBLER PROGRAM CONVERTS ASSEMBLY LANGUAGE
SOURCE PROGRAM TO HEXADECIMAL OBJECT PROGRAM
As illustrated in Figure 3-1, the assembly language program generated by a programmer is called a SOURCE PROGRAM. The assembler converts the SOURCE
PROGRAM into an equivalent OBJECT PROGRAM I which consists of a sequence of
hexadecimal codes that can be loaded into ROM or program RAM and executed.
For example:
Source Program
NOW,
CLB
JUN
FIM
NXT I
INC
is converted by
the As sembler to
On-e Pas sible Version of
the Obj ect Program
FO
NXT
4356
o
o
2-OFF
255
60
3-3
Now if a new instruction must be added, only one change is required. Even
the reader who is not yet familiar with assembly language will see how simple
the addition is:
NOW,
NXT
I
CLB
(New instruction inserted here)
TUN
NXT
FIM
INC
o
o
255
The assembler takes care of the fact that a new instruction will shift the rest
of the program in memory.
3.1.2
STATEMENT MNEMONICS
Assembly language instructions must adhere to a fixed set of rules as described
in this section. An instruction has four separate and distinct parts or FIELDS.
Field 1 is the LABEL field. It is the instruction location's label or name, and it
is used to reference the instruction.
Field 2 is the CODE field.
instruction.
It defines the operation that is to be performed by the
Field 3 is the OPERAND field.
by the CODE field.
It provides any address or data information needed
Field 4 is the COMMENT field. It is present for the programmer's convenience
and is ignored by the assembler. The programmer uses comment fields to describe
the operation and thus make the program more readable.
The assembler uses free fields; that is I any number of blanks may separate fields.
3-4
Before describing each field in detail, here are some general examples:
LABEL
CODE
CMI,
CLB
LAB,
INC
3
/ Increment register 3.
JUN
CMI
/ Jump to instruction CMI.
FIM
OP 255
/ Load hex FF (decimal 255) into
/ register pair o.
FCH,
3.1.3
OPERAND
COMMENT
/ Clear accumulator and carry.
LABEL FIELD
This is an optional field. If present, the first character of a label mu st be a
letter of the alphabet. The remaining characters may be letters or decimal digits
The label field must end with a comma, immediately following the last character of
the label. Labels may be any length, but should be unique in the first three characters; the assembler cannot always distinguish between labels whose first three
characters are identical. If no label is present, at least one blank must begin the line.
e
Here are some examples of valid label fields:
CMO,
NUL,
EGO,
Here are some invalid labels:
4GE,
AGE
A/A,
does not begin with a letter.
valid label, but label field does not end with a comma.
contains invalid character.
The following label ha s more than 3 characters:
STROB
The assembler may not be able to differentiate, this label from others beginning
with the characters STR.
3-5
Since labels serve as instruction addresses, they cannot be duplicated.
example, the sequence:
NOW,
JUN
NXT
NXT,
INC
2
NXT I
CLB
For
is ambiguous; the ·assembler cannot detennine which NXT address is referenced
by the rUN instruction.
3.1.4
CODE FIELD
This field contains a code which identifies the machine operation (add, subtract I
jump, etc.) to be performed: hence the term operation code or op-code. The
instructions described i~ Sections 3. 3 thru 3. II,
are each identified by a
mnemonic label which must appear in the code field. For example, since the
II jump unconditionally" instruction is identified by the letters "JUN", these
letters mu st appear in the code field to identify the instruction a s jump unconditionally" •
II
There must be at least one space following the code field.
LAB,
rUN
LAB,
rUNAWY
AWY
is legal, but:
is illegal.
3-6
Thus:
OPERAND FIELD
3.1.5
This field contains information used in conjunction with the code field to define
precisely the operation to be performed by the instruction. Depending upon the
code field, the operand field may be absent or may consist of one item or two
items separated by blanks.
There are five types of information [( a) through (e ) below] that may be requested
as items of an operand field, and the information may be specified in five ways
[( 1 ) through (5) below].
The five ways of specifying information are as follows:
( 1)
A decimal number.
Example:
LABEL
ABC,
CODE
LDM
OPERAND
14
COMMENT
/Load accumulator with decimal
/14 (Il10 binary).
The current program counter. This is specified as the character' *' and
is equal to the address of the first byte of the current instruction.
( 2)
Example:
LABEL.
GO,
CODE
OPERAND
JUN
*+6
If the instruction above is being as sembled at location 213, it will cause
program control to be transferred to address 219.
3-7
( 3)
Labels that have been a ssigned a decimal number by the assembler.
(See Section 3.12. 1 for the equate procedure) .
Example:
Suppose label VAL ha s been equated to the number 42 and ZER
has been equated to the number O. Then the following instructions all load register pair zero with the hexadecimal value 2A (decimal 42):
I
LABEL
CODE
AI,
FIM
FIM
FIM
A2,
A3
OPERAND
42
0
ZER
ZER
42
VAL
~
(4)
Labels that appear in the label field of another instruction.
Example:
CODE
LABEL
(5)
LPl,
TUN
LP2,
CMA
OPERAND
COMMENT
LP2
/ Jump to instruction at LP2.
Arithmetic expressions involving data types (1) to (4) above connected by the operators + (addition) and - (subtra ction). Th-e se operators
treat their arguments as 12-bit quantities, and generate 12-bit quantities
as their result. If a value is generated which exceeds the number of
bits available for it in an instruction the value is truncated on the left.
I
For example if VAL refers to hexadecimal address FFE, the instruction:
I
TUN
VAL
is encoded as 4FFEH; a 4 -bit operation code and 12 bi-t value.
instruction:
TUN
VAL +
However the
J
9
will be encoded as 4007H, where the value i007H has been truncated on the left
to 12 bits (three hex digits) giving a value oi ::007 H.
3-8
Using some or all of the above data specifications, the following five types
of information may be requested:
(a)
A register to serve as the source or destination in a data operation.
Methods I, 3, or 5 may be used to specify the register, but the
specification must finally evaluate to one of the decimal numbers
o to 15.
Example:
LABEL
CODE
II,
I2,
13,
INC
INC
INC
OPERAND
4
R4
16-12
As suming label R4 ha s been equated to 4, all the above instructions
will increment register 4.
(b)
A register pair to serve a~ the source or destination in a data op-
eration. The specification must evaluate to one of the even decimal numbers from 0 through 14 (corresponding to register pair designators OP through 7P) •
Example:
LABEL
CODE
OPERAND
II,
12,
13,
SRC
SRC
SRC
IP
2
RG2
Assuming label RG2 has been equated to 2, all of the above instructions
refer to register pair 1 P (registers 2 and 3).
(c)
Immediate data, to be used directly as a data item.
3-9
Example:
LABEL
CODE
ACl,
LDM
OPERAND
DATA
COMMENT
/Load the accumulator with
/the value of DATA.
DATA could take any of the following fonns:
19
12 + 72 - 3
VAL
{where VAL has been equated to a number} •
(d)
A 12 bit addres s, or the label of another location in memory.
Example:
LABEL
HR,
( e)
CODE
TUN
TUN
OPERAND
OVR
513
COMMENT
/Tump to instruction at OVR.
/Tump to hex address 201 (decimal 513).
A condition code for use by the TCN (jump on condition) instruction.
This must evaluate to a number from 0 to 15.
Example:
LABEL
CODE
TCN
TCN
OPERAND
4 LOC
2+2 LOC
The above instructions cause program control to be transferred to address LOC if
condition 4 (accumulator zero) is true.
3.1.6
COMMENT FIELD
The only rule governing this field is that it must begin with a slash (/).
terminated by the end of the line.
A comment field may appear alone on a line:
LOC,
CLB
/This is a comment
/This is a comment line
3-11
It is
3.2
DATA STATEMENTS
This section describes ways in which data can be specified in and interpreted
by a program. Any 4 bit character in DATA RAM contains one of the 16 possible
combinations of zeros and ones.
Arithmetic instructions assume that the DATA RAM characters upon which they
operate are in a special format called "two's complement" I and the operations
performed on these bytes are called "two's complement arithmetic" •
3.2.1
TWO'S COMPLEMENT
When a character is interpreted as a signed two's complement number I the low
order 3 bits supply the magnitude of the number, while the high order bit is
interpreted as the sign of the number (0 for positive numbers 1 for negative).
I
The range of positive numbers that can be represented in signed two's complement notation is, therefore, from 0 to 7~
0:::
OOOOB
I
0001B·
:::
6 0 1 lOB
7
0 1 lIB
To change the sign of a number represented in two's complement I the following
rules are applied:
(a)
Invert each bit of the number (producing the -so-called
one's complement).
(b)
Add one to the result ignoring any carry out of the
high order bit position.
Example:
I
Produce the two's complem-ent r-epresentation of -6
Following the rules above
I
+6:::
Invert each bit:
Add one
0110B
100 1 B
101 0 B
3-12
.
Therefore the two' s complement representation of -6 is the hexadecimal number
r A'.
(Note that the sign bit is set indicating a negative number.)
I
I
Example: What is the value of the hexadecimal number' C' interpreted as a signed
two's complement number? The high order bit is set, indicating that this is a
negative number. To obtain its value, again invert each bit and add one. (This is
equivalent to subtracting one f:um the number and inverting each bit) .
CH
=
1 1 0 0B
ODIIB
Invert ea ch bit
Add one
o1
0 0B
Thus, the value of -CH is - 4.
The range of negative numbers that can be represented in signed two's complement notation is from -1 to -8.
-1
-2
-7
-8
=
=
=
=
III 1 B
1 1 1 0B
100 1 B
100 0 B
To perform the subtracti()n 6-3
I
the following operations are performed:
Take the two' s complement of 3 = 1 1 0 1 B
Add the result to the minuend:
6
+ (-3)
=
=
all0B
1 1
a1
B
o 0 lIB
= 3 I the correct answer
When a data character is interpreted as an unsigned two's complement number
value is considered positive and in the range a to 15.
O=OODO B
1=0001 B
o1 1 1 B
8 = 1 0 0 0 B
7 =
15
1 1 1 1 B
3-13
I
its
Two's complement arithmetic is still valid. When performing an addition operation, the carry bit is set when the result is greater than 15. When performing
subtraction, the carry bit is set when the result is positive". If the carry bit
is reset, the result is negative and present in its two's complement form.
Example:
Subtract 3 from 10 using unsigned two's complement arithmetic.
10 = 1 0 lOB
-3 = 1 1 0 1 B
-L1
0111B
Lcarry
=
1
Since the carty bit is set, the result (7) is correct and positive.
Example:
Subtract 15 from 12 u sing unsigned two's complement arithmetic.
12
-15
=
=
JU
1 1 0 0 B
0 0 0 1 B
1101 B =
L..-Carry
-3
=0
Since the carry bit is reset, the result is negative and in its two's complem€nt
form.
WHY TWO'S COMPLEMENT?
Using two's complement notation for negative numbers any subtraction problem
becomes a sequence of bit inversions and additions. Therefore fewer circuits
are needed to perform subtraction.
I
I
3-14
3.2.2
CONSTANT DATA
Eight-bit data values can be assembled into ROM or program RAM locations by writing a blank code field and an operand field beginning with a positive number. If the operand is greater than 8 bits it will be truncated on the
left.
I
Assume that label VAL has been equated to 14 and the label
LOC appears on an instruction a s sembled at hexadecimal
location 34B.
Example:
I
LABEL
Cl
C2
CODE
OPERAND
ASSEMBLED DATA
1
O+VAL
1
4095
FF
O+LOC
4B
C3,
OE
The following are irivalid data statements.:
LABEL
C4,
C5,
CODE
OPERAND
ABC
-18
COMMENT
/Does not begin with a number.
/Number is not positive.
3-15
3.3
INDEX REGISTER INSTRUCTIONS
This section describes two instructions which involve index registers or register pairs.
These instructions occupy one byte a s follows:
FIN:
10
_
f
a
1
••
1
I
I01
R P
'.
_t
_
~
Looo
for register
001 for register
010 for register
all for register
100 for register
101 for register
110 for register
III for register
INC:
pair a or OP.
pair 2 or 1 P.
pair 4 or 2P.
pair 6 or 3~.
pair 8 or 4P.
pair 10 or 5P.
pair 12 or 6P.
pair 14 or 7P.
E~
'W
Loooo
0001
OOlD
0-011
01-00
0101
0110
0111
3-16
for
for
for
for
for
for
for
for
regi ster
register
register
register
regis"ter
"reg! ster
regi ster
regi ster
0
1
2
3
4
5
6
7
1000
1001
1010
1011
lIDO
1101
1110
1111
for
for
for
f-Or
for
for
for
for
regi ster
register
register
register
register
register
register
register
8
9
1{)
11
12
13
14
15
3.3.1
INC
INCREMENT REGISTER
Format:
LABEL
CODE
OPERAND
INC
REG
I
011
1
_
f
I
/
I
OI:E G'I
_,
,
I
.
Description:
The index register indicated by REG is incremented by one.
The carry bit is not affected.
Example:
If register 3 contains the number 6, the instruction:
INC
3
will cause register 3 to contain the number 7.
If register 8 contains the number 15 (1 1 1 1 binary)
INC
I
the instruction:
8
will cause register 8 to contain -{) I leaving the carry bit unchanged.
3-17
3 • 3 .2
FIN
FETC HIND IRECT
Format:
LABEL
CODE
OPERAND
FIN
RP
I
1,-----'/
--.......-..
. Description:
The contents of registers 0 and 1 are concatenated to form the lower 8 bits of a
ROM or program. RAM address. The upper 4 bits of the address are assumed
equal to the upper 4 bits of the address at which the FIN instruction is located
(that is the address of the FIN instruction and the address referenced by register
o and 1 are on the same page). The 8 bits at the designated addres s are loaded
into the register pair specified by RP. The 8 bits at the designated address are
unaffected; the contehts of registers 0 and I are unaffected unles s RP = O.
I
The carry bit is not affected.
Example:
Suppose a program in memory appears as follows:
DECIMAL
ADDRESS
HEXADECIMAL
ADDRESS
INSTRUCTION
ASSEMBLED
DATA
603
25B
110
6E
681
2A9
FIN 7P
3E
If register 0 contains the hex digit 5 and register 1 contains the hex digit B when
the FIN instruction is executed the 8 bits located at hex addres s 25B vvill be
loaded into register pair 7 P. Thus regi ster 14 will ~ontain the hex digit 6 (D 11 0
binary) and register 15 will contain the hex .nigit E {1 11 {j binary) .
I
3-1B
If registers 0 and 1 had conta:ined CH and 4 when the FIN was executed the 8
bits at hex address 2C4 '\vould have been loaded into registers 14 and 15.
I
NOTE: If a FIN instruction is located in the last location of a page I the upper
4 bits of the designated address will be assumed equal to the upper 4 bits of the
next page.
Thu s if the in struction :
FIN
7P
is located at decimal addres s 511 (hex 1 IT) and registers 0 and I contain 3 and
CH I the 8 bits at hex address 13C (not 13C) will be loaded into registers 14 and 15.
This is dangerous programming practice and should be avoided whenever possible.
3-19
3.4
INDEX REGISTER TO ACCUMULATOR INSTRUCTIONS
This section describes instructions which involve an operation between an index
register and the accumulator. Instructions in this clas s occupy one byte as
follows:
00
01
10
·11
for
ADD~
for SUB
for LD
for XCH
L
0000
0001
0010
0011
0100
0101
0110
oIII
for register
a
for
for
for
for
for
for
for
1
2
3
4
5
6
7
register
register
register
register
register
register
register
1000
100 1
1010
1011
1100
110 1
1110
1111
for
for
for
for
for
for
for
for
register
register
register
register
register
register
register
register
The general assembly language instruction format is:
LABEL
CODE
OPERAND
LABEL,
OP
REG
"-v-'"
I
t
T____ o through 15
~--...,-------
ADD
I
SUB, LD
I
or XCH
Optional instruction label
3-2{)
8
9
10
11
12
13
14
15
3.4.1
ADD
ADD REGISTER TO ACCUMULATOR WITH CARRY
Format:
LABEL
CODE
OPERAND
ADD
REG
I
~
~
11 1 01 ~
1
0
0
E G
I
I
Description:
The contents of the index register REG plus the contents of the carry bit are
added to the accumulator. The result is kept in the accumulator; the contents
of REG are unchanged. The carry bit is set if there is, a carry out of the highorder bit position, and reset if there is no carty.
Example:
Suppose the accumulator contains 6, register 14 contains 9
I
and the carry bit
= o.
Then the instruction:
ADD
14
will perform the following operation:
Accumulator
Register 14
Carry
=
o 11 0
=
1001 B
=
.JLI
B
0
1 11 1 B
t
=
Result
=
Carry
=
15
The accumulator contains 15 and the carry bit is reset. If the carry bit had been
one at the start of the previous operation, the following woul-d have occurred:
3-21
0110 B
1 001 B
1
Accumulator
Register 14
Carry
...LJ
OOOOB
+
The accumulator would contain 0
3.4.2
SUB
I
=
Result = 0
=
Carry
while the cany bit would be set.
SUBTRACT REGISTER FROM ACCUMULATOR WITH BORROW
Format:
LABEL
OPERAND
CODE
REG
SUB
\ _.--I
~
Description:
The contents of index register REG are subtracted with borrow from the accumulator.
The result is kept in the accumulator; the contents of REG are unchanged. A borrow
from the previous subtraction is indicated by the carry bit being equal to one ·at
the beginning of this instruction. If the carry bit equals zero at the beginning of
this instruction it is assumed that no borrow occurred from the previous subtraction.
This instruction sets the carry bit if there is no borrow out of the high order bit
position, and resets the carry bit if there is a borrow.
The subtract with borrow operation is actually performed by complementing each bit
of the contents of REG and adding the resulting value plus the complement of the
carry bit to the accumulator.
Note: This instruction may he used to subtract numbers greater than 4 bits in
The carry bit must be complemented by the program between each required
subtraction operation. For an example of this, see Section 4.8.
lengt~.
Example: In order to perform a normal subtraction, the carry bit should = O.
Suppose the accumulator contains 6, register +0 contains 2 and the carry bit = O.
Then the instruction:
SUB
10
I
will penorm the followif:}g operation:
3-22
Accumula tor
Register 10. = 001 0
Complemented
Complement of carry
=
0110 B
=
1101 B
1
l..J o 1 0 0 B =
Re suI t = 4
\ - - - -__ Carry = 1 indicating no borrow
Had the carry bit been = 1/ the operation would have produced the following:
Accumulator
10
Complement of register 14
Complement of carry
=
0110 B
1101 B
0
=
=
2J
\
3-23
001 1 B
= 3
. Carry = 1 indicating no borrow .
Result
3.4.3
LD
LOAD ACCUMULATOR
Format:
LABEL
CODE
OPERAND
LD
REG
\ I
Description:
The contents of REG are stored into the accumulator I replacing the previou s contents
of the accumulator. The contents of REG are unchanged. The carry bit is not
affected.
Example:
If register 12 contains 0 1 0 0 B the instruction
I
LD
12
will cause the accumulator also to contain 0 1 0 0 B.
3-24
3.4.4
XCH
EXCHANGE REGISTER AND ACCUMULATOR
Format:
LABEL
CODE
OPERAND
XCH
REG
\
.----..
11
I
01 ~
&,1 ]
~
I
E G,
•
Description:
The contents of the register specified by REG are exchanged with the contents of
the accumulator.
The carry bit is not affected.
Example:
If the accumulator contains 1 100 B and register 0 contains 0 0 lIB
then the in struction
I
XCH
0
will cause the accumulator to contain 00 lIB and register 0 to
contain 1 100 B.
3-25
I
3.5
ACCUMULATOR INSTRUCTIONS
This section describes instructions which operate only on the contents of the
accumulator and/or the carry bit.
Instructions in this class occupy one byte as follovvs:
[1,1 ,I ,I J~iX;~ ]
-
, ' - - - - - - 0000
0001
0010
0011
0100
0101
for
for
for
for
for
for
CLB
CLC
lAC
CMC
CMA
RAL
0110
0111
1000
1001
1010
1011
1100
for
for
for
for
for
for
for
RAR
TCC
DAC
TCS
STC
DAA
KBP
The general assembly language instruction format is:
LABEL
CODE
LABEL,
OP
-....-
t
OPERAND
~
t-----AIWayS blank.
- - - - - - - - - - C L B , CLC, lAC, CMC, CMA, RAL,
RAR, TCC, DAC, TCS STC DAA,
or KBP •
I
' " - - - - - - - - - - - - - - - - Optional instruction label.
3-26
I
3.5 • 1
CLB
CLEAR BOTH
Format:
LABEL
CODE
OPERAND
CLB
~
Description:
The accumulator is set to 0000 B and the carry bit is reset.
I
3.5.2
CLC
CLEAR CARRY
Format:
LABEL
CODE
OPERAND
GLC
~
Description:
The earlY bit is reset to ().
3-27
3.5.3
lAC
INCREMENT ACCUMULATOR
Format:
LABEL
OPERAND
De scription:
The contents of the accumulator are incremented by one. The carry bit is set if
there is a carry out of the high order bit position I and reset if there is no carry.
Example:
If the accumulator contains 1001 B the instruction rAC will perform
the following operation:
I
=
+
1001B
0001B
.JU
1 0 lOB
Accumulator
=
Ne"\v contents of accumulator.
, , ' - - - - - Carry =
If the accumulator contains 1111 B
operation:
Accumulator
I
=
+
1 1 lIB
OOOlB
-1J
0000B
0
the instruction rAC will perform the following
=
N GW contents of accumulator.
\~---- Carry =
3-28
1
CMC
3.5.4
COMPLElvlENT CARRY
Format:
LABEL
OPERAND
CODE
Description:
If the carry bit
3.5.5
CMA
=
0 I it is set to 1.
If the carry bit is = 1, it is set to O.
COMPLEMENT ACCUMULATOR
Format:
LABEL
CODE
OPERAND
CMA
~
Description:
Each bit of the contents of the accumulator is complemented (produ-cing the socalled one's complement).
The carry bit is not affected.
Example:
If the accumulator contains 0110 B, the instruction CMA v;ill caus-e
the accumulator to contain lODl B.
3-29
3.5.6
RAL
ROTATE ACCUMULATOR LEFT THROUGH CARRY
Format:
CODE
LABEL
OPERAND
RAL
""
-~
Description:
The contents of the accumulator are rotated one bit position to the left.
The high-order bit of the accumulator replaces the carry bit
replaces the low-order bit of the accumulator.
Example:
I
while the carry bit
Suppose the accumulator contains 1101 B, and the carry bit = O.
Before RAL is executed:
Carry
Accumulator
After RAL is executed:
1 ,0 1
t
,_ 0
Carry
=1
Accumulator
3-30
3.5.7
RAR
ROTATE ACCUMULATOR RIGHT THROUGH CARRY
Format:
CODE
LABEL
OPERAND
RAR
'\
Description:
The contents of the accumulator are rotated one bit position to the right.
The low-order bit of the accumulator replaces the carry bit, while the carry bit
replaces the high-order bit of the accumulator.
\7
Example:
Suppose the accumulator contains 0110B, and the carry bit = 1
Before RAR is executed:
Carry
Accumulator
r
lO ,1
,I , 0
I
After RAR is executed:
.
101
,
,1
Carry
Accumulator
3-31
=0
3.5.8
TCC
TRANSMIT CARRY AND CLEAR
Format:
LABEL
OPERAND
CODE
TCC
~
(1 .1 ,1 .1
10 .1 ,1
.1
. Description:
If the carry bit = a I the accumulator is set to OOOOB. If the carry bit = I, the
accumulator is set to 0001B. In either case the carry bit is then reset.
I
3.5.9
DAC
DECREMENT ACCUMULATOR
Format:
LABEL
OPERAND
CODE
DAC
~
Description:
The contents of the accumulator are decremented by one. The cany bit is set
if there is no borrow out of the high-order bit position and reset if there is a
borrow.
I
Example:
If the accumulator contains 1001 B, the instruction DAC will perform
the following operation:
3-32
Accumulator
+
( -1 )
=
=
..LI
10 0 1B
11 11B
10 00B=
New contents of accumulator
=
'--------Carry
1 indicating no borrow.
If the accumulator contains 0000, the instruction DAC will perform the following:
Accumulator =
+ (-1)
-
JLJ
0000 B
1 1 lIB
11 11 B=
New contents of accumulator
,'------Carry
3.5.10
TCS
=0
indicating a borrow.
TRANSFER CARRY SUBTRACT
Format:
LABEL
CODE
OPERAND
TeS
~
Description:
If the carry bit = -0, the accumulator is set to 9. If the carry bit = I, the
accumulator is set to 10. In either case~ the carry bit is then reset.
NOTE: This instruction is used when subtracting decimal numbers greater than
4 bits in length. For an example of this, see Section 4.8.
3-33
3.5.11
STC
SET CARRY
Format:
LABEL
CODE
OPERAND
STC
~
Description:
The carIY bit is set to 1.
3.5.12
DAA. DECIMAL ADJUST ACCUMULATOR
Format:
LABEL
CODE
OPERAND
DAA
~
Description:
If the contents of the accumulator are greater than 9, or if the carty bit = I,
the accumulator is incremented by 6. Otherwise, the accumulator is not affected.
If the result of incrementing the accumulator produces a carry out of the high order
bit position, the cany bit is set. Otherwise the carry bit is unaffected (in particular
it is not reset) .
NOTE:
This instruction is used when adding decimal numbers.
this see Section 4. 7 •
I
3-34
For an example of
I
3.5.13
KBP
KEYBOARD PROCESS
Format:
LABEL
CODE
OPERAND
KBP
~
Description:
If the accumulator contains OOOOB, it remains unchanged. If one bit of the accumulator is set, the accumulator is set to a number from 1 to 4 indicating which bit was
set.
If more than one bit of the accumulator is set, the accumulator is set to 1111 B.
This process is summarized as
foll~ws:
BINARY CONTENTS OF
ACCUMULATOR BEFORE
KBP
BINARY CONTENTS OF
ACCUMULATOR AFTER
KBP
0000
0001
0010
0100
1000
0011
0101
0110
0111
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
1111
1111
1111
1111
1111
1111
1111
1111
1-111
1111
tIll
The carry bit is not affected.
3-35
3.6
IMMEDIATE INSTRUCTIONS
This section describes two instructions which use data that is part of the instruction itself.
3.6.1
FIM
FETCH IMMEDIATE
The FIM instruction occupies two bytes.
Format:
LABEL
CODE
OPERAND
F~
RP
DATA
~/."
~,
"
10,0,110'* rio I. p, l} ..,;r
k
L
~
lA,
....
000
001
010
011
100
101
110
III
for
for
for
for
f-or
for
for
for
I
./
8-bit data quantity
register
register
register
regi ster
regi ster
register
register
register
pair
pair
pair
pair
pair
pair
pair
pair
a
2
4
6
8
10
12
14
or
or
or
or
or
or
or
or
OP
IP
2P
3P
4P
SP
6P
7P
Description:
The 8 bits of immediate data are loaded into the register pair specified by RP.
The earlY bit is not affected.
3-36
Example:
The instruction
FIM
254
2
will cause register 2 to contain 15, and register 3 to con~ain 14. This is because
254 decimal is encoded as FE hexadecimal; the upper four. bits are loaded into
register 2 and the lower four bits are loaded into register 3.
The instruction:
FIM
6
IP
will cause register 2 to contain 0, and register 3 to contain 6.
3.6.2
LDM
LOAD ACCUMULATOR IMMEDIATE
The LDM instruction occupies one byte.
Format:
LABEL
CODE
OPERAND
LDM
DATA
/
11
-
1 0 liD
,"
_
A T AI
.,
1_
L
A 4-bit data quantity
Description:
The 4 bits of immediate data are loaded into the accumulator.
The carry bit is not affected.
Example:
The instruction:
LDM
0
will clear the accumulator.
3-37
The instruction:
LDM
15
will set each bit of the accumulator.
3.7
TRANSFER OF CONTROL INSTRUCTIONS
This section describes instructions which alter the normal execution sequence of
instructions.
3.7.1
rUN
rUMP UNCONDITIONALLY
The rUN instruction occupies two bytes:
Format:
CODE
OPERAND
rUN
ADDR
I
______
.~A,
________
~
~
'
~
~
LABEL
________
~~
_________
J
~A
12-bit memory address.
Description:
Program execution is transferred to the instruction at location ADDR, which may
be anywhere in memory. (If the rUN is located in ROM, ADDR is a ROM address;
if located in program RAM, ADDR is a program RAM addres s).
The carry bit is not affected.
NOTE: This instruction and the rMS instruction (Section 3.8.1),
use a 12
bit address, and can reference any memory location. Their operation is not influenced by their position within a page of memory wherea s some other instrucI
3-38
tions are. Therefore, only a rUN or rMS instruction should be u sed to transfer
control from one page of memory to another.
Example:
Arbitrary Memory
Address (Hex)
360
362
Operand
As sembled Data
Label
Code
AD,
rUN
ADD
LRG
1
43EO
82
370
371
LAC,
LDM
rUN
3
AD
D3
4362
3EO
3E2
LRG,
FIM
rUN
OP 4
LAC
2004
4370
Normally, program instructions are executed sequentially. A 12-bit register
called the program counter holds the address of the instruction to be executed.
The rUN instruction replaces the program counter contents, causing program
execution to continue at that address.
Thus the execution sequence of this example is as follows:
The rUN instruction at 360H replaces the contents of the program counter with 3EOH.
The next instruction .executed is the FIM at" location LRG which loads register
o with the value 0, and register 1 with the value 4. The rUN at 3E2H is then
executed.
The program counter is set to 370H, and the LDM at this address loads the accumulator with the value 3. The rUN at 37lH sets the program counter to 362H, where the
ADD instruction adds the contents of register I plus the carry bit to the accumulator.
From here, normal program execution continues at location 36 3H .
3-39
3.7.2
JIN
JUMP INDIRECT
The JIN instruction occupies one byte.
Format:
LABEL
CODE
OPERAND
JIN /RP
~
IO,O,l,d~ ~hl
~
Looo
001
OJ.O
011
100
101
110
111
for register pair
for register pair
for register pair
for register pair
for register pair
for -regi ster pair
for regi ster pair
for register pair
0
2
4
6
8
10
12
14
or
or
or
or
or
or
or
or
OP
IP
2P
3P
4P
SP
6P
7P
Description:
The 8 bits held in the register pair specified by RP are loaded into the lower 8
bits of the program counter. The highest 4 bits of the program count-er are unchanged. Therefore I program execution continues at this address on the same
page of memory in which the JIN instruction is loaded.
The carry bit is not affected.
Example:
Hexadecimal
Memory Address
Code
3E4
3E6
FIM
JIN
Operand
OP
OP
3-40
21
Assembled Data
2015
The FIM instructions loads register 0 with the value I and register I with the
value 5. The JIN instruction then causes a jump to hexadecimal location 315.
NOTE:
If the JIN instruction is located in the last location of a page in
memory, the highest 4 bits of the program counter are incremented by one, causing
control to be transferred to the corresponding location on the next page.
If the above example, the JIN had been located at address 255 decimal (OFF hexadecimai) control would have been transferred to address 115 hexadecimal, not 015
hexadecimal. Thi s is dangerous programming practice and should be avoided
whenever possible.
I
I
3.7.3
TCN
JUMP ON CONDITION
The JCN instruction occupies two bytes.
Format:
LABEL
CODE
OPERAND
JCN
CN
ADDR
//
---
L
An 8-bit address
" - - - - - - - A four bit condition code
Description:
If the condition specified by eN is false no action occurs and program execution
continues with the next sequential instruction. If the condition specified by
eN is true I the 8 bits specified by ADDR replace the lower 8 bits of the program
counter. The highest 4 bits of the program counter are unchanged. Therefore I
program execution continues at the specified addres s on the same page of memory
in which the JCN instruction is located. The carry bit is not affected.
I
3-41
The condition code is specified in the assembly language statement as a decimal
value from 0 to 15, which is represented in the assembled instruction as the
corresponding 4 bit hexadecimal digit. Each bit of the condition code has a
meaning, as follows:
CN
l
,
I
~ L-. If this bit = 1, jump if the test signal of the 4004 is = O.
~ If this bit = 1, jump if the carry bit = 1.
If this bit
If this bit
= I,
= I,
jump if the accumulator
= o.
invert the other jump conditions.
More than one condition at a time may be tested. If the leftmost bit of the condition
code is zero a jump occurs if any of the remaining specified conditions is true (an
.. or" condition). If the leftmost bit is one a jump occurs if the logical inverse of the
"ortl condition is true. In Boolean notation the equation for the jump condition is as
follows:
JUMP = C, •
( (ACC = 0 ) • ~ . + (carry = 1) • ..,£3 + TEST • C
CJ •
«(ACC =f:. 0) + C2} • «carry = 0) +C 3 ' 8 (TEST + C4))
Example:
I
I
I
40
Hexadecimal
Memory Address
302
Label
Code·
LOG,
LDM
4
D4
JCN
bLOC
1602
Operand
Assembled Data
..
38B
38D
The condition code is encoded as 0110 B. Therefore the JCN will cause a jump to
address .302 H if the accumulator = 0, or if the carry bit = 1. If neither of these is
true program execution continues with the instruction at location 3BDH.
I
I
NOTE: If the JCN instruction is located in the last two locations of a page in
memory and the jump condition is true the highest 4 bits of the program counter
are incremented by 1, causing control to be transferred to the corresponding location on the next page.
f
3-42
If in the above example, the JCN had been located at addresses 254 and 255
decimal (OFE and OFF hexadecimal) a true condition would have caused jump
to location 102 hexadecimal rather than 002 hexadecimal. This is dangerous
programming practice { and should be avoided whenever pos sible.
3.7.4
ISZ
INCREMENT AND SKIP IF ZERO
The ISZ instruction occupies two bytes.
Format:
CODE
LABEL
ISZ
OPERAND
REG
ADDR
-,---~-------j"'---.,
ADD R
L''----..L
, - - -_ _-"'1
An B bit addres s
000 0 for register a
0001 for register 1
1111 for register 15
Description:
The index register specified by REG is incremented by one. If the result is 0000 B,
program execution continues with the next sequential instruction. If the result
does not equal 0000 B the 8 bits specified by ADDR replace the lovve st 8 bits of
the program counter. The highest 4 bits of the program counter are unchanged.
Therefore I program execution continues at the specified address on the same page
of memory in which the ISZ instruction is located.
I
The carry bit is not affect€d.
3-43
Example:
Hexad ecima I
Memory Addres s
30F
311
31A
31C
Label
Code
Operand
Assembled Data
FIM
XCH
OP
2
0
LP,
2000
B2
ISZ
0
LP
7011
The FIM instruction loads registers 0 and 1 with O.
The XCH is then executed. Program execution continues until the ISZ is reached.
Register 0 is incremented to contain l, and since this result is non-zero, program control is transferred back to location 311H. This process continues until
register 0 = 1111B. Then the ISZ increments register 0 producing a result of OOOOB,
and execution continues with the instruction at 31CH. '
I
If the ISZ instruction is located in the last two locations of a page in
NOTE:
memory and the incrementation produces a non-zero result, the highest 4 bits of
the program counter are incremented by I, causing control to be transferred to the
corresponding location on the next page.
If in the above example, the ISZ had been located at decimal addresses 1022 and 1023
(3FE and 3FF hexadecimal), control would have been transferred to location 411
hexadecimal and the XCH and remaining instructions would have been executed
only once. Thus this is dangerous programming practice ( and should be avoided
whenever possible.
I
3-44
3.8
SUBROUTINE LINKAGE COMMANDS
This section describes the commands which call and cause return from subroutines.
They cause a transfer of program control and use the address stack (see Sections 2.4
and 2. 7 • 7) •
3.8.1
JMS
JUMP TO SUBROUTINE
The JM S instruction occupie s two bytes.
'Format:
LABEL
CODE
OPERAND
JMS
ADDR
/
________
r~------~A
,
v~------~I
LA
12-bit memory address
Description:
The address of the instruction immediately following the JMS is written to the
address stack for later use by a BBL instruction. Program execution continues at
memory address ADDR, which may be on any page.
The carty bit is not affected.
NOTE:
Since the JMS uses a 12 bit memory address it operates the same wherever it is located in memory and can reference any address in memory. For this
reason I only a JMS or JUN instruction should be used to transfer program control
from one page of memory to another.
I
I
3-45
Example:
Hexadecimal
Memory Address
011
013
3AO
Label
SUB,
Operand
Code
As sembled Data
JMS
XCH
SUB
0
53AO
DO
INC
1
61
BBL
6
C6
The JMS instruction causes the 12 bit address 013H (the address of the instruction
following the JMS) to be written to the address stack. Execution continues with
the INC instruction at SUB, and proceeds sequentially from this pOint.
3.8.2
BBL
BRANCH BACK AND LOAD
The BBL instruction occupies one byte.
Format:
LABEL
OPERAND
CODE
BBL
(1 11 I 0 I 0
DATA
I
/
D A
I
.T IA
I
LA 4-bit DATA value
Description:
The 4 bits of immediate data encoded in the instruction are loaded into the accumu1ator. Then the last 12 bit address saved on the address stack (by a JMS instruction)
3-46
is read from the stack and placed in the program counter. Thus, ~xecution continues with the instruction immediately following the last JMS instruction.
The carry bit is not affected.
Example: In the example of Section 3.8. I, the BBL instruction load s the value
6 into the accumulator. The address 013 is read into the program counter, and program execution proceeds with the XCH instruction.
3-47
3.9
NOP INSTRUCTION
NO OPERATION
This instruction occupies one byte.
Format:
LABEL
OPERAND
CODE
NOP
Description:
No operation is performed. The program counter is incremented by one and execution continues with the next sequential instruction.
The carry bit is not affected.
MEMORY SELECTION INSTRUCTIONS
3.10
This section describes instructions which specify DATA RAM data and status characters RAM output ports and ROM input and output ports to be operated on by
I/O and RAM instructions described in Section 3. 11 .
I
3.10. 1
DCL
DESIGNATE COMMAND LINE
The DCL instruction occupies one byte.
Format:
LABEL
CODE
OPERAND
DCL
3-48
Description:
As described in Section 2.3. 3 there may be up to 8 DATA RAM BANKS each of
which consists of four DATA RAM units. The DCL instruction uses the rightmost
3 bits of the accumulator to determine which of the 8 DATA RAM BMJKS will be
referenced during subsequent operations.
I
The selection is made as follows:
RIGHTMOST 3 BITS
OF ACCUMULATOR
DATA RAM BANK
SELECTED
0,
000
001
010
all
100
101
110
5
6
III
7
0
1
2
3
4
This choice remains in effect until the next DCL is executed, or an external RESET
signal is received. A RESET causes DATA RAM BANK a to be selected.
The carry bit is not affected.
Example: The following instructions will select DATA RAM BANK 3:
LDM
DCL
3
/Load accumulator with 0011 B
3-49
3.10.2
SRC
SEND REGISTER CONTROL
The SRC instruction occupies one byte.
Format:
LABEL
OPERAND
CODE
SRC
1°,0,1,0
~
RP
If. f 11 I
"-v--
L
000 for
001 for
010.for
011 for
100 for
101 for
110 for
III for
register pair
register
register
register
regi·ster
register
register
register
pair
pair
pair
pair
p.air
pair
pair
a or OP
2
4
6
8
10
12
14
or
or
or
or
or
or
or
1P
2P
3P
4P
5P
6P
7P
Description:
The 8 -hits contained in the register pair specified byRP are used as an address.
This address may designate a particular DATA RAM data character, a DATA RAM
status character, a RAM output port, or a ROM input/output port. (A description
of these elements appears in Section 2). In fact, the address designates
all of these simutaneously; it is up to the programmer to then write the correct
I/O or RAM instruction (described in Section 3.11) to access the proper entity.
The address sent by the SRC remains in effect until changed by a subsequent
SRC.
The only DATA RAM bank which receives the SRC address is the one selected by
the last previous DCL instruction.
The carry bit and the contents of the register pair are unaffected.
The 8 bits of the address sent by the SRC are interpreted as follows:
3-50
(1)
When referencing a DATA RAM data character:
~ -v- - - - - - -
I
1
!
1 of 16 4-bit data characters within
i:-======~_-_-_the register.
'--_ _ _
~
1 of 4 registers within the DATA RAM
chip.
1 of 4 DATA RAM chips within the DATA
RAM bank previously selected by a DeL
instruction.
(2)
When referencing a DATA RAM status character:
I . I'
~-----
1
~l-
_____
These bits are not relevant for this reference.
1 of 4 registers within the DATA RAM chip.
1 of 4 DATA RAM chips within the DATA RAM
bank previously selected by a DeL instruction.
( 3)
When referencing a RAM output port:
I
I
I
~
,
+-J-----._----
These bits are not relevant for this reference.
'-._ _ _ _ _ _ _ _ _ The port associated with 1 of 4 DATA RAM
chips within the DATA RAM bank previously
selected by a DeL.
3-51
( 4)
When referencing a ROM input or output port:
I . •
I
Example:
I
I
t. .________
These bits are not relevant for this
reference.
The port associated with 1 of 16
ROM's.
The instructions:
FIM
SRC
IP
IP
180
will cause the eight bit value 101101 OOB to be used as an address. Subsequent
instructions could then reference DATA RAM data character number 4 of register
3 of chip 2/ any of the status characters associated with DATA RAM register 3
of chip 2/ RAM output port number 2 (the port a ssociated with DATA RAM chip 2) ,
or ROM port number 11 (the port associated with ROM number 11). The address
remains in effect until another SRC instruction is executed.
3-52
3. 11
INPUT/OUTPUT AND RAM INSTRUCTIONS
This section describes instructions which access DATA RAM characters or perform input or output operations. One instruction, WPM, allows the programmer
to read or write 8-bit program RAM locations. These instructions use
addresses selected by the DCL and SRC instructions described in Section 3. 1 . o.
Instructions in this class occupy one byte as follows:
1
0000
0001
0010
0011
0100
0101
0110
0111
for
for
for
for
for
for
for
for
1 1 0
1o
P
!
WRM
WMP
WRR
WPM
WRO
WRI
WR2
WR3
1000
1001
1010
1011
1100
1101
1110
1111
for
for
for
for
for
for
for
for
SBM
RDM
RDR
ADM
RDO
RDl
RD2
RD3
The general assembly language instruction format is:
LABEL
CODE
LAB,
I
-...---.-
OPERAND
OP
L
Always blank
WRM, WMP, WRR, WPM, WRO, WRI, WR2, WR3,
SBM, RDM RDR, ADM RDO RDl, RD2 or RD3
I
' ' - - - - - - Optional instruction label.
3-53
I
I
I
3.11.1
RDM
READ DATA RAM DATA CHARACTER
Format:
CODE
LABEL
\1,1, 1 1
OPERAND
°11,0,° 11 I
Description:
The DATA RAM data character specified by the last SRC instruction is loaded into
the accumulator. The carry bit and the data character are not affected.
Example:
CODE
LABEL
OPERAND
rIM
2P
SRC
RDM
2P
5
The above instructions will read the contents of DATA RAM data character number
5 of register 0 of chip 0 of the currently selected DATA RAM bank into the accumulator.
3.11.2
RDn
READ DATA RAM STATUS CHARACTER
Format:
LABEL
OPERAND
CODE
RDn
1
\ 1 ! 1 I 1I 0 1
I
!
'-y-J
t
n =
3-54
b,
1
I
2, or 3
De"scription:
The DATA RAM status character whose number from 0 to 3 is specified by n associated with the DATA RAM register sp'ecified by the last SRC in'struction, is loaded
into the accumulator.
I
The carry bit and the status character are not affected.
Example:
LABEL
CODE
OPERAND
FIM
SRC
RD3
2P
2P
5
The above instructions will read the contents of DATA RAM status character 3 of
register 0 of chip 0 of the currently selected DATA RA11 bank into the accumulator.
3.11.3
RDR
READ ROM PORT
Format:
LABEL
CDDE
OPERAND
RDR~
~
3-55
Description:
The ROM port specified by the last SRC instruction is read. When using the 4001
ROM each of the 4 lines of the port may be an input or an output line; the data on
the input lines is transferred to the corresponding bits of the accumulator. Any
output lines cause either a 0 or a 1 to be transferred to the corresponding bits of
the accumulator. Whether a 0 or a 1 is transferred is a function of the hardvv:are
not under control of the programmer.
I
I
The carry bit is not affected.
Example:
LABEL
CODE
OPERAND
FIM
SRC
RDR
3P
3P
160
The above instructions will read the contents of the port associated with ROM number
ten into the accumulator. If the leftmost I/O line is an output line and the remaining
I/O lines are input lines containing 01 OB the accumulator will contain either 101 OB
or OOIOB.
I
NOTE: On the INTELLEC 4, a ROM port may be used for either input or output. If
programs tested on the INTELLEC 4 are to be run later with a 4001 ROM I the programmer
must be careful not to use one port for both functions.
3. 11 .4
WRM
WRITE DATA RAM CHARACTER
Format:
LABEL
CODE
OPERAND
WRM
\
.---A-....
Description:
The contents of the accumulator are written into the DATA RAM data character specified by the la st SRC instruction.
The carry bit and the accumulator are not affected.
3-56
Example:
LABEL
CODE
FIM
SRC
LDM
OPERAND
OP
OP
15
180
WRM
The above instruction will cause DATA RAM data character number 4 of register 3
of chip 2 of the DATA RAM bank selected by the last DCL instruction to contain
15 (1111B).
3. 11. 5
WRn
WRITE DATA RAM STATUS CHARACTER
Format:
LABEL
CODE
OPERAND
WRn
0, I, 2, or 3
-Description:
The contents of the DATA RAM s:tatus character whose number from 0 to 3 is specified by n, associated with the DATA RAM register specified by tbe last SRC'
instruction, are repla ced by the contents of the accumulator.
The carry bit and the a-ccumulator are not affected.
3-57
Example:
LABEL
CODE
OPERAND
FIM
SRC
LDM
WRI
OP
OP
o
2
The above instructions will write the value 2 into status character 1 of DATA RAM
register 0 of chip 0 of the currently selected DATA RAM bank.
3.11.6
WMP
WRITE RAM PORT
Format:
LABEL
CODE
WMP
OPERAND
"-
...--"----..
11 ,1,1,01 0,0,0,11
Description:
The contents of the accumulator are written to the output port as sociated with the
DATA RAM chip selected by the la st SRC instruction. This value will stay at th€
output port until overwritten.
The carry bit and the accumulator are unchanged •
Example:
LABEL
CODE
OPERAND
FIM
SRC
LDM
WMP
3P
3P
6
3-58
64
The above instructions will write the value 6 to the output port associated with
DATA RAM chip 2 of the currently selected DATA RAM bank.
3.11. 7
WRR
WRITE ROM PORT
Format:
LABEL
CODE
11 ,1,1,01
OPERAND
0 ,0,1
1
°I
Description:
The contents of the accumulator are written to the output port associated with the
ROM selected by the last SRC instruction. This value will stay at the output port
until overwritten.
The carry bit and the accumulator are unchanged.
Example:
LABEL
CODE
OPERAND
FIM
SRC
LDM
WRR
4P
4P
64
15
The above instructions will write the 'value 15 to the output port associated with
ROM number 4.
3-59
3.11.8
ADM
ADD DATA RAM TO ACCUMULATOR WITH CARRY
Format:
CODE
LABEL
OPERAND
ADM
"-
....- " -
Description:
The DATA RAM data character specified by the last SRC instruction, plus the
carry bit, are added to the accumulator.
The carry bit will be set if the result generates a carry
wise.
I
and will be reset other-
The data character is not affected.
Example:
CODE
LABEL
OPERAND
OP
OP
FIM
SRC
ADM
o
If the carry bit = 0 the accumulator contains 10 , and DATA RAM data character
o of register 0 of chip 0 contains 7 the ADM will perform the following operation:
I
I
Accumulator
Data character
Carry bit
=
1 0 lOB
o 1 11 ~
o
1I __0_0_0_1_B_=_
=
=
~
3-60
New contents. of accumulator.
Carry bit will be set.
3.11.9
SBM
SUBTRACT DATA RAM FROM MEMORY WITH BORROV\T
Format:
LABEL
OPERAND
CODE
SBM~
~
\1,1,1,0111°1°1° I
De scription:
The value of the DATA RAM character specified by the last SRC instruction is subtracted
from the accumulator with borrow. The data character is unaffected. A borrow from the
previous subtraction is indicated by the carry bit being equal to one at the beginning
of this instruction. No borrow from the previous subtraction is indicated by the carry
bit being equal to zero at the beginning of this instruction.
This instruction sets the carry bit if the result generates no borrow and resets the
carry bit if the result generates a borrow.
I
The subtract with borrow operation is actually performed by complementing each bit of
. the data character and adding the. resulting value plus the complement of the carry bit
to the accumulator.
NOTE: When this instruction is used to subtract numbers greater than 4 bits in
length the carry bit must be complemented by the program between each required
subtraction operation. For an· example of this, s€e Section 4.8.
J
Example:
LABEL
CODE
FIM
SRC
SBM
OPERAND
1P
1P
1
If the carry bit = I, the accumulator contains 7, and DATA RAM character 1 of
register 0 of chip 0 contains 5, the SBM will perform the following operation:
Accumulator
Data character = 0101
Complemented
Complement of Carry
=
o 11
1B
B
=
=
101 0 B
·0
.QJ
000 1 B
== New contents of accumulator.
, ' - - - - - - - - Carry bit will be reset indicating a borrow.
3-61
3 . 11 . 10
v'lPM
WRITE P ROG RAM RAM
Format:
LABEL
CODE
OPERAND
111,1010,0,1,1\
Description:
This is a special instruction which may be used to write the contents of the accumulator into a half byte of program RAM I or read the contents of a half byte of program
RAM into a ROM input port where it can be acces sed by a program.
The carry bit is unaffected.
NOTE:
Two WPM instructions must always appear in close succes sion; that is,
each time one WPM instruction references a half byte of program RAM as indicated by
an SRC address, another WPM must access the other half byte before the SRC
address is altered. An internal counter keeps track of which half-byte is being
accessed. If only one WPM occurs, this Gounte-r will be out of sync with the program
and errors will occur. In this situation a RESET pulse must -be used to re-initialize
the machine.
I
NOTE:
A vVPM instruction requires an SRC address to access program RAM.Whenever a WPM is executed, the DATA RAM which happens to correspond to this SRC
address will also be written. If data needed later in the program is being held in
such a DATA RAM, the programmer must save it elsewhere before executing the
WPM instruction.
Storing Data Into Program RAM:
A program must perform the following actions in order to store eight bits of data into
a program RAM location:
(1)
The value 1 must be written to ROM port number 14.
signal, permitting the store operation to work.
{2}
The highest 4 bits of the program RAM address to be accessed must be
written to ROM port number 15.
(3)
The lowest 8 bits of the program RAM address to be accessed must be sent
out by an SRC instruction.
3-62
Thi sis a "write enable"
(4 )
The higher 4 bits of data to be written must be loaded into the accumulator and.written with the first WPM; the lower 4 bits of data must then
be loaded into the accumulator and written with the second WPM.
(5)
The value 0 must be written to ROM port number 14, clearing the "write
enable" .
Reading Data From Program RAM:
A program must perform the following actions in order to read eight bits of data
from a program RAM location:
( 1)
The highest 4 bits of the program RAM address to be accessed must be
written to ROM port 15.
( 2)
The lowest 8 bits of the program RAM address to be accessed must be sent
out by an SRC instruction.
(3)
Two WPM instructions in succession must be executed. The first reads,
the leftmost 4 bits of the program RAM location into ROM port 14; the second
reads the rightmost 4 bits of the program RAM location into ROM port 15 ..
Example:
The following routines access a program RAM location whose address
is held in status characters 0, 1, and 2 of DATA RAM register 0 of DATA RAM chip
DATA RAM
Register
Regi-ster
Register
Register
PROGRAM RAM
cmp 0
Hex Address
0
1
2
3
4AA
4AB
4AC
'----v-'"
Status Cnara cters
Routine STR stores the contents of registers 2 and 3 into the addressed location;.
routine FeR reads the contents of the addressed location into registers 2 and 3.
3-63
o.
LABEL
CODE
STR ,
rIM
SRC
LDM
WRR
JMS
LD
WPM
LD
WPM
FIM
SRC
CLB
WRR
BBL
COMMENT
OPERAND
OP
OP
1
224
/ Select ROM port 14.
I
/
/
/
/
COM
2
I
3
OP
OP
Turn on write enable.
Routine COM sets up PRAM
address.
High 4 data bits to accumulator.
Write to PRAM
Low 4 data bits to accumulator.
224
/ Select ROM port 14.
/ Turn off write enable.
/ Return to program
0
/
/
COM 1
FIM
SRC
RDI
XCH
RD2
XCH
RDO
FIM
SRC
WRR
SRC
BBL
OP
OP
JMS
W-FM
WPM
FIM
SRC
RDR
XCH
INC
SRC
RDR
XCH
BBL
COM
0
/
/
/
/
/
/
10
11
OP
OP
Select DATA RAM chip 0 register
Read mid-dle 4 bits of address.
Save in register 10.
Read lowest 4 bits of address.
Save in regi ster 11.
Read highest 4 bits of address.
o.
240
I
Select ROM port 15.
/ Write high address
/ Write middle + low address
I Return to STR or FCH
SP
0
/
/
FCH
OP
OP
/ Routine COM sets up PRAM address.
data to ROM port 14.
/PAAM
data to ROM port 15 •
I_PRAM
224
/ Select port 14.
/ Read to accumulator.
/ -Save in register 2.
2
{)
OP
/ Select port 15.
/ Read to accumulator
. / Save in register 3.
! Return to progra m
3
0
3~£4
3. 12
PSEUDO INSTRUCTION
This section describes the functions of the pseudo instruction recognized by the
assembler. The pseudo instruction is indicated by the character = (equal sign)
written in the code field of an assembler statement. No executable object code
is generated by the pseudo instruction. It acts merely to provide the assembler
with information to be used subsequently while generating obj ect code.
3. 12. 1 EQUATE FUNCTION
Format:
CODE
LABEL
SYM
OPERAND
-
'-v-'
L
EXP
"-v-'"
L-
An
expres~ion
Required symbol
Des cription:
The symbol SYM is assigned the value EXP by the a.ssembler. Whenever the symbol
SYM is encountered subsequentlY by the assembler, this value will be used.
Example: The statements
CZ
=
10
JeN
CZ
ADDR
are equivalent to the statement
TCN
10
ADDR
The statements .
DAT =
5
LDM DAT
will load the value 5 into the accumulator.
3-65
3. 12. 2
ORIGiN FUNCTION
Format:
LABEL
~
L
,--------
OPERAND
CODE
-
~p
~
An expression
Blank label field
Description:
The assembler's location counter is set to the value of EXP. The next machine
instruction or data byte-generated will be assembl~d at address EXP.
I
NOTE:
The equal sign may appear in the first position of the line.
Example:
LABEL
CODE
OPERAND
o
rUN
=
LO,
LDM
The rUN instruction will be
RAM. The location counter
assembled at location 512,
will therefore cause a jump
LO
512
7
assembled in locations 0 and 1 of ROM or program
is ihen set to 512 causing the LDM instruction to be
the first location on the second memory pa-ge. The rUN
to location 512.
I
NOTE: The pseudo instruction also makes -it possible to assemble constant data
values into a program. For a description of how to do this, see Section 3.2.2.
3-66
4.0
PROGRAMMING TECHNIQUES
This section describes some techniques which may be of help to the programmer.
4.1
CROSSING PAGE BOUNDARIES
As described in Section 2 programs are held in either ROM or program
RAM both of which are divided into pages. Each page consists of 256 8 -bit
locations. Addresses 0 through 255 comprise the first page,256-511 comprise the
second page and so on.
I
I
I
In general it is good programming practice to never allow program flow to cross .
a page boundary except by using a TUN or TMS instruction. The following example
will show why this is true. Suppose a program in memory appears as below:
I
Decimal Addres s
PAGE 0
o
200
253
255
PI
LDM
o
TCN 12
XCH
PI
3
If the accumulator is non-zero when the TCN is executed, program control will be
transferred to location 200, as the programmer intended.
Suppose now that an error discovered in the program requires that a new instruction be inserted somewhere between locations 200 and 253. The program would
now appear as follows:
4-1
Decimal Address
PAGE 0
o
200
PI
LDM
0
254
TCN
256
PAGE 1
XCH
456
12
PI
I--
3
:~
511
Since the TCN is now located in the last two locations of a page it functions
differently. Now if the accumulator is non-zero ~Nhen the TCN is executed program
control will be erroneously transferred to location 456, causing invalid results.
I
I
Since both the TUN and TMS instructions use 12-bit addresses to directly address
locations on any page of memory
page boundaries.
I
only thesE instructions should be used to eros s
4-2
4.2
SUBROUTINES
Frequently a group of instructions must be repeated many times in a program.
The group may be written lin" times if it is needed at lin different points in a
program but better economy can be obtained by using subroutines.
I
II
I
A subroutine is coded like any other group of assembly language statements, and
is referred to by its name, which is the label of the first instruction. The programmer reference s a subroutine by writing its name in the operand field of a JMS
instruction. When the JMS is executed the address of the next sequential instruction after the JMS is written to the address stack (see Section 2.4),
and
program execution proceeds with the first instruction of the subroutine. When
the subroutine has completed its work a BBL instruction is executed, which loads
a value into the accumulator and causes an address to be read from the stack into
the program counter causing program execution to continue with the instruction
following the JMS. Thus ,one copy of a subroutine may be called from many
different points in memory, preventing duplication of code. Note also that since
the address stack and the JMS instruC?tion use l2-bit addresses, calling programs
and subroutines may be located anywhere in ROM or control program RAM (they
need not be on the same page in memory) .
I
I
I
Example: Subroutine IN increments an 8 bit number passed in index register 0
and 1 and then returns to the instruction following the last JMS instruction executed.
LABEL
IN,
CODE
---
XCH
OPERAND
1
lAC
XCH
NC,
JCN
INC
BBL
1
10 NC
o
o
/ Reg 1 to Accum.
/ Increment value and produce carry
/ Restore reg 1.
/ Jump if Carry = o.
/ Increment high order 4 bits
/ Return
Assume IN appears as follows:
4-3
Arbitrary Memory
Address
(Hex)
3CO
3C2
JMS
IN
401
403
JMS
IN
~
I~~---/'-----~
When the first JMS is executed address 3C2H is written to the address stack and
control is transferred to IN. Execution of the BBL statement will cause the addres s
3C2H to be read from the stack and placed in the program counter causing execution to continue at 3C2H (since the JMS occupies two bytes) .
I
I
I
Address Stack
Before JMS
Stack While IN
Is Executing
ADR 1
3C2H
ADR 2
ADR 2-
ADR 3
ADR 3
_Stack After BBL
Is Perfromed.
3C2 H
.......
ADR 2
ADR 3
When the second JMS is executed address 403H is written to the stack and control
is again transferred to IN. This time the BBL will cause execution to resume at
403H.
I
I
I
Note that IN could have called another subroutine during its execution causing
another address to be written to the stack. This can occur only up to three levels
however since the stack can hold only three addres ses • Beyond this point
some addresses will be overwritten and BBLls will transfer program control to
incorrect addresses.
I
I
I
4-4
I
4.3
BRANCH TABLE PSEUDOSUBROUTINE
Suppose a program consists of several separate routines, any of which may
be executed depending upon some initial condition {such as a bit set in the
accumulator}. One way to code this would be to check each condition sequentially and branch to the routines accordingly as follows:
CONDITION =
IF YES BRANCH
CONDITION =
IF YES BRANCH
CONDITION
TO ROUTINE
CONDITION
TO ROUTINE
1 ?
1
2 ?
2
BRANCH TO CONDITION N
A sequence as above 'is inefficient
I
and can be improved by using a branch table.
The logic at the beginning of the branch table program computes an index into
the branch table. The branch table itself consists of a list of starting addresses
for the routines to be selected. Using the table index, the branch table program
loads the selected routine's starting addres s into a register pair and executes a
"jump indirect" to that address. For example consider a program that executes
one of five routines depending upon which bit (possibly none) of the accumulator
is set:
I
Jump
Jump
Jump
Jump
Jump
to
to
to
to
to
a if
routine 1 if
routine 2 if
routine 3 if
routine 4 if
routine
accumulator =
accumulator =
accumulator =
accumulator =
accumulator =
0000
0001
0010
0100
1000
B
B
B
B
B
A program that provides the above logic is given at the end of this section. The
prog!,am is termed a "pseudosubroutine" because it is treated as a subroutine by
the programmer, (i. e. it appears ju st once in memory) but it is entered via a
regular "jump" instruction rather than via a JMS instruction. This is possible
because the branch routines control subsequent execution and will never return
to the instruction following JMS;
I
I
I
4-5
BRANCH TABLE
PROGRAM
MAIN PROGRAM
~
JUMP ROUTINES
-- - - -.-----~
NORMAL SUBROUTINE
RETURN SEQUENCE NOT
FOLLOWED BY BRANCH
TABLE PROGRAM.
LABEL
ST,
CODE
OPERAND
/ Convert Accum to branch table
/ index •
KBP
.I
lAC
JeN
4
ERR
DAC
FIM
OP
B.TL
1
1
10
NC
NC,
JCN
INR
FIN
JIN
BTL,
o
=
1111 B ERRO R
I
/ Jump if lAC produced zero.
/ O.K., restore accumulator.
/ Regs 0 and 1 = addr-es s of
/ branch table.
/ Carry = 0
/ Add index to branch tab-le address
/ Store back in reg 1
/ Jump if no carry
/ If carry, increment reg O.
/ Regs 0 and 1 = address of
/ routine.
I Jump to correct routine.
CLC
ADD
XGH
If
OP
OP
/ Branch table. Each-entry
/ is an a-bit a-ddress
0+ RTO
0+ RTI
0+ RT2
0+ RT3
0+ RT4
/ Error handling routine.
ERR,
4-6
NOTE:
Since FIM, FIN, and TIN operate with 8-bit addresses, routines ST,
BTL, and RTO through RT4 must all reside in the same page of memory_
If the accumulator held 01 OOB when location ST was reached, the KBP would
convert it to 00 11 B _ The 8 bit addres s at BTL + 3 would therefore be loaded into
registers 0 and I, and the TIN would cause program control to be transferred to
routine RT3_
4-7
4.4
LOGICAL OPERATIONS
This section gives three subroutines which produce the logical operations
AND
"0R
and "XOR (exclusive -OR).
II
II
II I
II
I
4.4.1 LOGICAL "AND"
The AND function of two bits is given by the following truth table:
a
1
oQJTI
lL±J
Since any bit ANDed with a zerC? produces a zero, and any bit ANDed with a one
remains unchanged the AND function is often used to zero groups of bits.
I
The following subroutine produces the AND, bit by bit, of the two 4-bit quantities
held in index registers a and 1. The result is placed in register 0, while register
1 is set to O. Index registers 2 and 3 are also us-ed.
For example ,.: if register
- replaced with 00 lOB.
a =
11 lOB and register 1 = OOllB register
I
a will
be
1110 B
AND
-0011 B
0010 B
The subroutine produces the AND of two bits by placing the bits in the leftmost
position of the accumulator and register 2, respectively and zeroing the rightmost three bits of the accumulator and register 2,. Register 2 is then added to the
accumulator and the resulting carry is equal to the AND of the two bits.
I
I
4-8
LABEL
CODE
OPERAND
AND,
Ll,
FIM
LDM
XCH
RAL
XCH
INC
XCH
JCN
XCH
RAR
XCH
XCH
RAL
XCH
RAR
ADD
JUN
BBL
IP
0
0
L2,
4.4.2
0
3
3
4
3
/ REG 2 ::: 0, REG 3 = 11
11
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
L2
2
1
1
2
Ll
0
GET BIT OF REG 0; SET ACC = 0
REG 0 DATA TO ACC; REG 0 = 0
1st "AND' BIT TO CARRY
SAVE SHIFTED DATA IN REG 0; ACC={)
DONE'IF REG 3 = 0
REG 3 TO ACC
RETURN IF ACC = 0
OTHERWISE RESTORE ACC AND REG3
BIT OF REG 0 IS ALONE IN ACC
SAVE 1 st 'AND' BIT IN REG 2
GET BIT OF REG 1
LEFT BIT TO CARRY
SAVE SHIFTED DATA IN REG 1
2ND lAND' BIT TO ACC
'ADD' GIVES 'AND' OF THE 2 BITS
IN CARRY
RETURN TO MAIN PROGRAM.
LOGICAL "0R"
The OR function of two bits is given by the following truth table:
o
1
:GI8
Since any bit ORed with a one produces a one and. any bit ORed with a zero
remains unchanged, the OR function is often used to set groups of bits to one.
I
The following subroutineprodu~es t-he OR, bit by bit of the -two 4"""bit quantities
held in index registers 0 and 1. The result is place-d in register 0 while register
1 is set to o. Index registers 2 and 3 are also used.
I
I
4-9
For example, if register 0:::: 0100B and register l:::: 0011B, register 0 will be
replaced with 0 I11B.
OR
0100 B
0011 B
0111 B
The subroutine produces the OR of two bits by placing the bits in the leftmost
position of the accumuiator and register 2 respectively, and zeroing the rightmost
three bits of the accumulator and register 2. Register 2 is then added to the
accumulator. If the resulting carry = I, the OR of the two bits:::: 1. If the resulting
carry :::: 0, the OR of the two bits is equal to the leftmost bit of the accumulator.
I
LABEL
CODE
OPERAND
OR,
Ll,
FIM
LDM
XCH
IP
0
0
11
RAL
XCH
INC
XCH
JCN
XCH
RAR
XCH
LDM
XCH
RAL
XCH
RAR
L2,
0
~
3
4
L2
3
2
0
1
1
ADD
2
TCN
RAL
TUN
BBL
2
L1
Ll
0
4-10
I
I
I
REG 2 :::: 0, REG 3 :::: 11
GET BIT OF REG 0; SET ACC = 0
REG 0 DATA TO ACC; REG 0 :::: 0
lIst 'OR' BIT TO CARRY
I SAVE SHIFTED DATA IN REG 0; ACC::::O
I DONE IF REG 3 :::: 0
/ REG 3 TO ACC
I RETURN IF ACe :::: 0
I OTHERWISE RESTORE ACC ANDREG3
I BIT OF REG .() IS ALONE IN ACC
I SAVE 1st 'OR' BIT IN REG 2
I GET BIT IN REG 1; SET ACC :::: 0
I
I
I
I
I
I
I
I
LEFT BIT TO GARRY
SAVE SHIFTED DATA IN REG 1
2ND 'OR' 'BIT TO ACC
PRODUCE THE OR OF THE BITS.
JUMP IF CARRY = 1 BECAUSE 'OR ::::l
OTHERvVISE 'OR' = LEFT BIT OF
ACCUMULATOR
TRANSMIT TO CARRY BY RAL
i
4.4.3
LOGICAL "XOR" EXCLUSIVE-OR
The XOR (exclusive -OR) function of two bits is given by the following truth
table:
o
o
1
1
ffiB
Since the e~clusive OR of two equal bits produces a zero and the exclusive OR
of two unequal bits produces a one, the exclusive OR function can be used to
test two quantities for equality. If the quantities differ in any bit position, a
one will be produced in the result.
The following subroutine produces the exclusive - OR of the two 4-bit quantities
held in index registers a and I. The result is placed in register 0, while register
1 is set to O. Index registers 2 and 3 are also u.sed.
For example if register 0 = OOIIB and register 1 = 0010B, register 0 will be
replaced with OOOlB.
0011 B
XOR
0 010
B
0001
B
, The .s.ubroutine produces the XOR of two bits by placing the bits in the leftmost
POSItlO~ of the accumulator and register 2, respectively, and zeroing the rightmost
three bIts of the accumulator and register 2. Register 2 is then added to the
accumulator. The XOR of the two bits is then equal to the leftmost bit of the
a ccum ula tor.
.
4-11
LABEL
CODE
OPERAND
XOR,
Ll,
FIM
IP
0
LDM
XCH
RAL
XCH
INC
XCH
JCN
XCH
RAR
XCH
2
LDM
XCH
0
1
11
@
0
3
3
4
3
L2
L2,
REG 2 = 0, REG 3 = 11
GET BIT OF REG 0; SET ACC =0
'REG 0 DATA TO ACC; REG 0=0
1ST XOR BIT TO CARRY
SAVE SHIFTED DATA IN REG 0; ACC = 0
DONE IF. REG 3 = 0
REG 3 TO ACC
RETURN IF ACC = O.
OTHERWISE RESTORE ACC & REG 3
BIT OF REG 0 IS ALONE IN ACC
SAVE 1ST XOR BIT IN REG 2
/ GET BIT IN REG 1; SET ACC = 0
RAL
XCH
RAR
ADD
RAL
rUN
BBL
/
/
/
/
/
/
/
/
/
/
/
/ LEFT BIT TO CARRY
/ SAVE SHIFTED DATA IN REG 1
/ 2ND 'XOR1 BIT TO ACC
I PRODUCE THE XOR OF THE BITS
/ XOR'= LEFT BIT OF ACCUM; TRANSMIT
/ TO CARRY BY RAL.
1
2
Ll
0
4-12
4.5
MULTI-DIGIT ADDITION
The carry bit may be u sed to add unsigned data quantities of arbitrary length.
Consider the following addition of two 4-digit hexadecimal numbers:
381 C
+
69F2
A20E
This addition may be performed by setting the carry bit = 0 adding the two
low-order digits of the numbers then adding the resulting carry to the two next
higher order digits and so on:
I
I
I
r
3
8
1
6
9
F
C
2
A
2
o
E
Carry
=1
Carry = 1
Carry = 0
The following subroutine will perform a sixteen .digit addition
tions:
The two numbers to be added are stored in DATA RAM chip 0
I
I
making these assump-
registers 0 and 1.
The numbers are stored with the least significant digit first (in character 0) .
The result will be stored least significant digit first in register C replacing the
contents of register 1.
Index register 8 will count the number of digits (up to 16)
4-13
which have been added.
Status Chars.
DATA RAM CHIP 0 BEFORE ADDITION
,---A----..
Register
0
C
1 8
3 0 0 0 0
0
0
0
0
0
0
0
0
1
2
F 9
6 0
0
0
0
0
0
0 0
0
0
0
0
2
3
DATA RAM CHIP 0 A;FTER ADDITION
Register 0
1
C
1 8 3 0 0 0 0 0
E 0
0 0
0
0 0
0
0
2 A 0 0 0 0 0 0 0 0 0 0 0 0
2
3
AD,
ADl,
OVR,
FIM
2P
0
FIM
3P
16
CLB
XCH
SRC
RDM
SRC
ADM
8
2P
3P
WRM
INC
5
INC
7
ISZ
8
BBL
0
ADI
4-14
/ REG PAIR 2P -= RAM CHIP 0 OF
/ REG 0
/ REG PAIR 3P = RAM CHIP 0 OF
-I REG 1
/ SET CARRY = 0
/ SET DIGIT COUNTER = 0
/ SELECT RAM REG 0
/ READ DIGIT TO ACCUMULATOR
/ SELECT RAM REG 1
/ ADD DIGIT + CARRY TO ACCUMU/ LATOR
/ WRITE RESULT TO REG 1
/ ADDRESS NEXT CHAR. OF RAM
/ REG 0
/ ADDRESS NEXT CHAR OF RAM
/ REG 1
/ BRANCH IF DIGIT COUNTER
< 16 (NON ZERO)
When location OVR is reached, RAM register I will contain the sum of the two 16
digit numbers arranged from low order digit to high order digit. {The reason
multi-digit numbers are arranged this way is that it is easier to add numbers
from low order to high order digit, and it is easier to increment addresses than
to decrement them.
The first time through the program loop, index register pair 2 (index register 4
and 5) contains 0 and index register pair 3 (index registers 6 and 7) contains 16,
referencing the first data characters of DATA RAM registers 0 and I, respectively.
On succeeding repitions of the loop, index registers 5 and 7 are incremented,
referen cing sequential data characters, until all 16 digits have been added.
4.6
MULTI-DIGIT SUBTRACTION
The earlY bit may be used to subtract unsigned data quantities of arbitral}' length.
Consider the following subtraction of two 4-digit hexadecimal numbers:
54BA
-
14F6
3FC4
This subtraction may be performed by first setting the carry bit = 1. Then for each
pair of digits, the program must complement the carty bit and perform the subtraction. By this process I the carry bit will adjust the differences, taking into account
any borrows which may have occurred.
This process applied to the above subtraction proceeds as follows:
=
(1 )
Set carry bit
1.
(2 )
Complement carry bit.
(3)
Subtract low -order digits:
Carry now
=
A = 1010B
6= 1001B
carry =
1
. ..u0100B=
4
4-15
O.
(4 )
Complement resulting carry.
(5 )
Subtract next digits:
B
F
carry
=
=
=
Carry now
=
O.
=
1 ..
=
1.
1011 B
0000 B
1
..QjIIOO B
=
CH
(6)
Complement resulting carry. Carry now
(7 )
Subtract next digits:
=
4" =
0100 B
101 1 B
carry =
0
4
.JLllll1 B = FH
(8)
Complement resulting carry.
(9)
Subtract next digits:
Carry now
=
T =
5
carry
0101 B
III 0 B
=
0
.1JOOll B
=
3
Thus the correct result, 3FC4H,. is bbtained. The following subroutine will
perform a sixteen digit subtraction, making these assumptions;
As in the example of Section 4. 2 I the two numbers are stored in DATA RAM chip
0, registers 0 and 1 (register 1 containing the subtrahend). The numbers are
stored with the lea st significant digit in character 0, and the result is stored back
into register 1. Index register 8 will count the number of digits (up to 16) which
have been subtracted.
4-16
SB,
SB1,
OV,
FIM
2P
0
FIM
3P
16
CLB
XCH
STC
CMC
SRC
RDM
SRC
SBM
/
/
/
/
8
2P
3P
WRM
INC
5
INC
7
ISZ
8.
BBL
0
SBl
REG
REG
REG
REG
PAIR 2P
0
PAIR 3P
1
::=
RAM CHIP 0
::=
RAM CHIP 0
/
/
/
/
/
/
/
/
/
/
/
/
/
/
SET DIGIT COUNTER = 0
SET CARRY = 1
COMPLEMENT CARRY BIT
SELECT RAM REG 0
READ DIGIT TO ACCUMULATOR
SELECT RAM REG 1
SUBTRACT DIGIT AND CARRY
FROM ACCUMULATOR
WRITE RESULT TO REG 1
ADDRESS NEXT CHAR. OF RAM
REG 0
ADDRESS NEXT CHAR. OF RAM
REG 1
BRANCH IF DIGIT COUNTER
/.< 16 (NON-ZERO).
When location OV is reached RAM register 1 will contan the difference of the two
16 digit numbers. Note that the carry bit from the previous subtraction is com-:
p1emented by the CMC instruction each time through the program loop.
I
4-17
4. 7
DECIMAL ADDITION
Each 4 bit data quantity may be treated as a decimal number as long as it represents one of the decimal digits from 0 through 9, and does not contain any of the
bit patterns representing the hexadecimal digits A through F. In order to preserve
this decimal interpretation when perfonning addition, the value 6 must be added
to the accumulator whenever an addition produces a result between 10 and 15.
This is because each 4 bit data quantity can hold 6 more combinations of bits
than there are decimal digits.
The DAA (decimal adjust accumulator) instruction is provided for this purpose.
Also, to permit addition of multi-digit decimal numbers I the DM adds 6 to the
accumulator whenever the carry bit is set indicating a decimal carry from previous additions. The carry bit is unaffected unless the addition of 6 produces
a carry in which case the carry bit is set.
I
To perform the decimal addition:
469
+
329
798
the process works as follows.
( 1)
Clear the carry and add the lowest-order digits
9 == 1001 B
9 = 1001B
carry ==
0
2..10 0 10B
"'-carry =
(2)
1
Perform aDAA operation, which will add 6 to the accumulator. Since no
carry is produced by this operation I the carry bit is left unaffected I
remaining = 1.
4-18
Accum.
6
=
=
0010 B
0110 B
a
=
Carry
~ 1000 B
(3)
8
=
9
Add the next two digits.
6
2
Carry
= a 11 a
B
=
=
0010 B
1
..Qj
1001 B
'carry
(4)
=
= a
Perform a DAA operation. Since the accumulator is not greater than 9 and
the carry is not set no action occurs.
I
(5 )
Add the next two digits:
4
:3
Carry
=
=
=
0100 B
0011 B
a
J2.I a 11 1
"
Carty
(6)
B
=
7
= a
Perform a DAA operation. Again, no action occurs. Thus the correct
decimal result 798 is generated in three 4 bit data characters.
A subrout1ne which adds two 16 digit decimal numbers, then, is exactly analagous
to the 16 digit hexadecimal addition subroutine of Section 4.2, and may be produced by inserting the instruction DAA after the ADM instruction of that example.
4-19
4.8
DECIMAL SUBTRACTION
Each 4 bit data quantity may be treated as a decimal number as long as it represents one of the decimal digits 0 through 9. The TCS (transfer carry subtract)
and DAA (decimal adjust accumulator) may be used to subtract two decimal numbers
and produce a decimal number. In fact, the TCS instruction permits subtraction
of multi-digit decimal numbers.
The process consists of generating the ten's complement of the subtrahend digit
(the difference between the subtrahend digit and 10 decimal), and adding the
result to the minuend digit. For instance, to subtract 2 from 7, the ten's complement of 2 (l 0-2 = 8) is added to 7, producing 15 decimal which, when truncated
to a 4 bit quantity gives 5 (the required result). If a borrow was generated by
the previous subtraction, the 9' s complement of the subtrahend digit is produced
to compensate for the borrow.
In detail, the procedure for subtracting one multi -digit decimal number from
another is as follows:
= 1 indicating
(1)
Set the carry bit
no borrow.
(2 )
Use the TCS instruction to set the accumulator to either 9 or 10 decimal.
(3)
Subtract the subtrahend digit from the accumulator, producing either
the 9' s or 10' s complement.
(4)
Set the carry bit =
(5 )
Add the minuend digit to the accumulator.
(6)
Use the DM instruction to make sure the result in the accumulator is
in decimal fonnat, and to indicate a borrow in the carry bit if one
occurred.
o.
Save this re suI t •
(7)
If there are more digits to subtract, gO to step 2.
Otherwise stop,
4-20"
Example:
Perfonn the decimal subtraction
51
- 38
13
=
(1 )
Set ca rlY
1. '
(2 )
TCS sets accumulator = 101 OB and carry
(3)
Subtract the subtrahend digit 8 from the accumulator.
Accumulator
=
=
O.
1 0 lOB
B
1
8= 0111
-=--CarlY
=
0010 B
(4 )
Set carlY = O.
(5 )
Add minuend digit 1 to accumulator.
Accumulator = 0 0 lOB
1 - 0001 B
earlY =
a
JU
(6)
0011B = 3
...
Carry = a
DAA leaves accumulator = 3 = first digit of result, and' carry
indicating that a borrow occurred.
= 1001B and
TCS sets accumulator
(8)
Subtract the subtrahend digit 3 from the accumulator.
Accumulator
3"
carry
= o.
(7)
1 001 B
11 0 OB
Carry
1
011
a
B
4-21
=
0,
(9 )
Set carry = O.
( 10) Add minuend digit 5 to accumulator.
Accumulator
5
Cany
= o1 1 0
= 0101
0
=
B
B
..2J 1011
B
"-Carry
= 0
(11) DAA adds 6 to accumulator and sets carry
occurred.
Accumulator
6
=
=
=
I, indicating that no borrow
1 0 lIB
0110 B
~ 0 0 0 1 B =1
=
Second digit of result.
"
Carry = 1
Therefore the result of subtracting 38 from 51 is 13.
The following subroutine will subtract one 16 digit decimal number from another
using the following assumptions.
I
The minuend is stored least significant digit first in DATA RAM chip 0 I register
O.
The subtrahend is stored least significant digit first in DATA RAM chip 0 I register
1.
The result will be stored lea st significant digit first in DATA RAM chip 0
oI replacing the minuend.
I
register
Index register 8 will count the number of digits (up to 16) which have been subtracted.
4-22 '
SD,
SDl,
FIM
FIM
CLB
XCH
STC
TCS
SRC
SBM
CLC
SRC
ADM
DN,
2P
3P
/ REG PAIR 2P = RAM CHIP 0, REG 0
/ REG PAIR 3P = RAM CHIP 0
/ REG 1
0
16
8
3P
2P
DM
WRM
INC
5
INC
7
ISZ
8
BBL
0
SDI
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
I
4-23
SET DIGIT COUNTER = 0
SET CARRY = 1
ACCUMULATOR = 9 OR 10
SELECT RAM REG 1
PRODUCE 9's OR la's
COMPLEMENT
SET CARRY = 0
SELECT RAM REG 0
ADD MINUEND TO ACCUMULATOR
ADJUST ACCUMULATOR
WRITE RESULT TO REG 0
ADDRESS NEXT CHAR. OF RAM
REG 0
ADDRESS NEXT CHAR. OF RAM
REG 1
BRANCH IF DIGIT COUNTER <. 16
(NON -ZERO) •
4.9
FLOATING POINT NUMBERS
The structure of DATA RAM chips is fully described in Section 2.3.3.
One use to which a 16-character DATA RAM register and its 4 status characters
can be put is to store a 16 digit decimal floating point number.
Such a number can be represented in the form:
+ .DDDDDDDDDDDDDDDD * 10+ EE
The 16 data characters of a RAM register could then be used to store the digits
of the number I two status characters could be used to hold the digits of the
exponent while the remaining two status characters would hold the signs of the
number and its exponent.
I
If a value of one is chosen to represent minus and a value of zero is chosen to
represent plus, status characters 0 and 1 hold the exponent digits status character 2 holds the exponent sign and status character 3 holds the number's sign,
then the number
I
+.12345.67890812489 x 10-
23
would appear in a RAM register as follows:
RAM CHIP
RAM
RAM
RAM
RAM
REGISTER
REGISTER
REGISTER
REGISTER
0
1
2
3
1 2 3 4 5
6 7 8 9 0 8 1 2 4 8 9
2 3 1 0
~-----------------v------------------~~
DATA CHARACTERS
4-24
Status
Characters
APPENDIX "A"
INSTRUCTION
SUMMARY
This appendix provides a summary of 4004 instructions. Abbreviations used are as
follows:
DESCRIPTION
ABB REVIATION
A
The accumulator.
An
Bit n in the accumulator, where n may have
any value from 0 to 3.
ADDR
A read-only memory or program random-access
memory address.
carry
The carry bit.
PC
The 12 bit Program Counter.
peR
The high-order
PCL
PCM
The low-order 4 bits of the Program Counter.
The middle 4 bits of the Program Counter.
RAM
Random-access memory.
REG
Any index register from 0 to 15 ..
RO
Index register 0 ~
Rl
Index register 1.
ROM
Read-only memory.
RP
Any index register pair from
STK
The address stack.
value
The number obtained by comp1ementing each bit
of value.
A-I
4 bits of the Program Counter.
.op to
7P.
( Continued) :
DESCRIPTION
ABBREVIATION
X:Y
The value' obtained by concatenating the values
X and Y.
[ ]
An optional field enclosed by brackets.
(
Contents of register or memory enclosed by
parentheses.
)
Replace value on left hand side of arrow with value
on right hand side of arrow.
A-2
A.I
INDEX REGISTER INSTRUCTIONS
Format:
[LABEL I
FIN
]
RP
-- or-(LABEL ,]
INC
Code
REG
Description
FIN
( RP) ---- ({ PCR: RO: Rl) )
Load RP with 8 bits of ROM data
addressed by register pair O.
INC
( REG) --- ( -REG) + 1
Increment register REG.
A.2
INDEX REGISTER TO ACCUMULATOR INSTRUCTIONS
Format:
[LABEL, ]
CODE
Code
REG
Des cription
-
( A) - - - ( A) + (REG) + (carry)
Add REG plus carry bit to accumulator.
SUB
(A) --- (A) + (REG) +(carry)
Subtract REG from a ccumu lator
with borrow.
LD
(A)
XCH
( A)
ADD
..
....
•
(REG)
Load accumulator from REG •
(REG)
Exchange -contents of accumulator
and REG.
A-3
A.3
ACCUMULATOR INSTRUCTIONS
Format:
[LABEL]
CODE
Description
Code
a
Clear both accumulator and carry.
(carry) - - - 0
CLB
(A)----
CLC
(carry)--- a
lAC
(A)--- (A) + 1
CMC
(carry) ---- (carry)
CMA
(A)----
I
I
Clea r carry.
. Increment accumulator.
Complement carry.
Comp"lement each bit of the accumulator.
(10
Rotate accumulator left
through carry.
RAL
RAR
An ---- An+ 1 , (carry) ~AO' .A --- (carry)
.
3
Rotate accumulator right
through carry.
TCC
(A)--'- 0 . AO--'- (carry), (cair.y)~ 0
Transmit the value of the
carry to the accumulator
then clear carry.
l
DAC
(A)-.-(A) -1
Decrement accumulator
TCS
If (carry) = 0 (A) --- 9
10
If (carry) = 1, (A)~IOIO
Adjust accumulator for decimal
subtract.
I
(carry)---- 0
STC
(c."'-arry) --- 1
Set carry.
DM
If( A) > 9
Adjust accumulator for decimal
add.
or (carry)
= 11 (A).....-(A) + 6
10
Convert accumulator from I of n code
to
binary
value
.
...- - _...._ _ _ _ _ _ _ _ _ _ _ _...u..._ _ _ _
___
__
.. _ _ _ _' "
KBP
I!IIInIil~.$H.~~1~'I::~;::iII
A-4
A.4
IMMEDIATE INSTRUCTIONS
Format:
[LABEL, ]
FIM
RP
DATA
-- or-[LABEL, ]
Code
LDM
DATA
Description
Load 8 bit immediate DATA into register
pair RP.
FIM
( RP)~DATA
LDM
( A)
A.S
TRANSFER OF CONTROL INSTRUCTIONS
-lIE-
DATA
Load 4 -bit immediate DATA into the
accumulator.
Format:
(LABEL,]
JCN
eN
ADDR
-- or--[LABEL,]
JIN
RP
-- or-[LABEL, ]
ISZ
REG
-- or-{LABEL,]
JUN
ADDR
A-S
Description
Code
JUN
(PCH:PCM:PCL)-'-ADDR
Jump to location ADDR.
JIN
(peM: PCL) ----(RP)
Jump to the address in register
pair RP.
JCN
If CN true, (PCM: PCL)--- ADDR
If CN false, (PL) --- (PL) + 2
Jump to ADDR if condition true.
ISZ
CREG) --- ( REG) +
A.6
SUBROUTINE LINKAGE INSTRUCTIONS
Increment REG. If zero, skip.
1
If non zero, jump to ADDR
If re suI t = 0, (PL) --- ( PL) + 2
If result = 1, (PCM: PCL)---ADDR
Format:
[LABEL, ]
ADDR
JMS
-- or-BBL
[LABEL, ]
DATA
Description
Code
JMS
(STK) --- (PC)
BBL
(PC)--- (STK)
(PC)---ADDR
I
I
( A) ---- DATA
A-6
Call subroutine and push return
address onto stack.
Return from subroutine and load
accumulator with immediate DATA.
I
A.7
NOP INSTRUCTION
Format:
[ LAB EL , ]
NO P
De scription
Code
NOP
A.8
-------------------
No operation
MEMORY SELECTION INSTRUCTIONS
Format:
[LABEL,]
SRC
RP
-- or-[LABEL,]
DCL
Code
.SRC
DeL
Description
DATA BUS---( RP)
Contents of RP select a RAM or
ROM address to be used by I/O
and RAM instructions.
CPU:~A2: Al : AD
Select.a particular RAM bank.
A-7
A.9
I/O AND RAM INSTRUCTIONS
Format:
CODE
[LABEL, ]
Description
Code
WRM
( RAM)---A
Write accumulator to RAM.
WMP
RAM output port ........ (A)
Write accumulator to RAM output port.
WRR
ROM output port -.;1-( A)
Write accumulator to ROM output port.
WPM
(PRAM)
Write accumulator to Program RAM.
WRn
RAM status
character n~(A)
Write accumulator to RAM status char&cter
n (n = 0, 1 i 2 or 3).
RDM
(A)--- RAM
Load accumulator from RAM.
RDR
( A) --- ROM input port
Load accumulator from ROM input port.
RDn
(A)~
Load accumulator from RAM status
character n (n = 0, I, 2, or 3) .
·ADM
---( A)
RAM status
character n
(A)---(A) + (RAM)"
Add RAM data plus carry to accumulator.
+ (carry)
SBM.
(A)--- (A) + (RAM) + (carry)
A-8
Subtract RAM data from accumulator with
borrow.
APPENDIX "BII
-- INSTRUCTION MACHINE CODES --
In order to help the programmer examine memory when debugging programs this
appendix provides the as sembly language instruction represented by each of the
256 possible instruction code bytes.
I
Where an instruction occupies two bytes
I
only the first (code) byte is given.
B-1
DEC
0
1
2
3
4
5
6
7
8
9
10
II
12
13
14
IS
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
OCTAL
000
001
002
003
004
005
006
007
010
all
012
013
014
015
016
017
020
021
022
023
024
025
026
027
030
031
032
033
034
035
036
037
040
041
042
043
044
045
046
047
050
HEX
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
IA
IB
IC
ID
IE
IF
20
21
22
23
24
25
26
27
28
MNEMONIC
COMMENT
NOP
---
---------
--.-
-------------------
JeN
CN =
eN'=
eN =
eN =
CN=
eN=
CN =
CN =
eN =
eN =
CN =
CN =
CN =
CN =
eN =
CN =
TeN
TeN
JCN
JCN
JeN
JCN
JCN
JCN
JCN
JeN
JCN
JCN
JeN
JCN
JCN
FIM
SRC
FIM
SRC
FIM
SRC
FIM
SRC
FIM
B~2
OP
OP
1P
1P
2P
2P
3P
3P
4P
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DEC
OCTAL
HEX
MNEMONIC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
051
052
053
054
055
056
057
060
061
062
063
064
065
066
067
070
071
072
073
074
075
076
077
100
101
102
103
104
105
106
107
110
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
SRC
FIM
SRC
FIM
SRC
FIM
SRC
FIN
JIN
FIN
TIN
FIN
TIN
FIN
TIN
FIN
TIN
FIN
TIN
FIN
JIN
FIN
JIN
JUN
JUN
JUN
JUN
JU,N
rUN
JUN
JUN
JUN
JUN
TUN
TUN
rUN
TUN
JUN
TUN
III
112
113
114
115
116
117
120
121
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
JMS
JMS
B-3
COMMENT
4P
5P
5P
6P
6P
7P
7P
OP
OP
IP
IP
2P
2P
3P
3P
4P
4P
5P
SP
6P
6P
7P
7P
"
Second hex digit is
> part of jump addres s.
DEC
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
118
119
120
121
122
OCTAL
HEX
122
123
124
125
126
127
130
131
132
133
134
135
136
137
140
141
142
143
144
145
146
147
150
151
152
153
154
155
156
15'7
160
161
162
163
164
165
166
167
170
171
172
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
SF
60
61
62
63
64
65
66
67
68
69
6A
MNEMONIC
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
JMS
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
6B
6C
6D"
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
ISZ
ISZ
ISZ
ISZ
ISZ
ISZ
ISZ
ISZ
ISZ
ISZ
ISZ
£-4
COMMENT
"
Second hex digit
is part of jump
address.
0
1
2
3
'1
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
DEC
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
OCTAL
173
174
175
176
177
200
201
202
203
204
205
206
207
210
211
212
213
214
215
216
217
220
221
222
223
224
225
226
227
230
231
232
233
234
235
236
237
240
241
242
243
MNEMONIC
HEX
ISZ 11
ISZ 12
ISZ 13
ISZ 14
ISZ 15
ADD 0
ADD 1
ADD 2
ADD 3
ADD 4
ADD 5
ADD 6
ADD 7
ADD 8
ADD 9
ADD 10
ADD 11
ADD 12
ADD 13
ADD 14
ADD 15
SUB 0
SUB 1
SUB 2
SUB 3
SUB 4
SUB 5
SUB 6
SUB 7
SUB 8
SUB 9
SUB 10
SUB 11
SUB 12
SUB 13
SUB-" 14
SUB 15
LD
D
LD
1
2
LD
3
LD
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
888e."
8D .~i
8E -:"'
8F
90
91
92
93
f
94 "
95 j
96
97
98
99
9A
9B
9C
9D
9E
9F
AD
Al
A2
A3
B-S
COMMENT
..
DEC
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
OCTAL
HEX
244
245
246
247
250
251
252
253
254
255
256
257
260
261
262
263
264
265
266
267
270
271
272
273
274
275
276
277
300
301
302
303
304
305
306
307
310
311
312
313
314
A4
AS
A6
A7
A8
A9
MNEMONIC
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
XCH
BBL
BBL
BBL
BBL
BBL
BBL
BBL
BBL
BBL
BBL
BBL
BBL
BBL
AA
AB
AC
AD
AE
AF
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
COMMENT
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
'.i!~~
B-6
DEC
OCTAL
HEX
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
-233
234
235
236
237
238
239
240
241
242
243
244
245
315
316
317
320
321
322
323
324
325
326
327
330
331
332
333
334
335
336
337
340
341
342
343
344
345
346
347
350
351
352
353
354
355
356
357
360
361
362
363
364
36-5
CD
CE
CF
DO
Dl
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
BBL
BBL
BBL
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
WRM
WMP
WRR
WPM
WRO
WR1
WR2
WR3
SBM
RDM
RDR
ADM
RDO
RDI
RD2
RD3
FO
CLB
Fl
F2
F3
F4
F5
CLC
lAC
CMC
CMA
RAL
MNEMONIC
B-1
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COMMENT
I
DEC
OCTAL
HEX
246
247
248
249
250
251
252
253
254
255
366
367
370
371
372
373
374
375
376
377
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
MNEMONIC
RAR
TCC
DAC
TCS
STC
DAA
KBP
DCL
B-8
COMMENT
APPENDIX "C"
-- ASCn TABLE--
The 4004 uses a seven-bit ASCII code, which is the normal 8 bit ASCII code
with the parity (high order) bit always reset.
Graphic or Control
ASCII (Hexadecimal)
NULL
SOM
00
EOA·
EOM
EOT
02
WRU
RU
BELL
OS
01
03
04
06
07
08
09
FE
H.Tab
OA
OB
OC
OD
OE
Line Feed
V. Tab
Fonn
Return
SO
SI
OF
DCO
10
11
12
X-On
Tape Aux. On
13
14
15
16
X-Off
Tape Aux. Off
Error
Sync
17
18
LEM
SO .
Sl
S2
83
S4
S5
'19
lA
IB
lC
ID
86
lE
S.7
IF
C-l
Graphic or Control
ACK
Alt~ Mode
Rub out
.1
"
#
$
%
&
(
)
'It
+
"
•
/
,
.
,
(
=
ASCII Hexadecimal
,"
7C
7D
7F
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D2E
2F
3A
3B
3C
. 3D.
')
3E
?
'[
3F
I
J
It(-
@
blank,
0
1
2
3
4
5
6
7
8
9
'5B
50
SD
SE
SF
40
20
30
31
32
33
34
35
36
37
38
39
,
C-2
.
Graphic or Control
A
ASCII Hexadecimal
B
4'1
42
C
43
n·
44
E
·45
F
G
., H
. 46
I
J
·47
48
49
4A
K
4B
L
M
N
4C
4D
o
P
4E
4F
... 50
o
51
R
S
T
52 .
U
V
W
53
. 54
y,
55
56
57
58
.59
Z
SA
X
C-3
'."
.
APPENDIX liD"
-- BINARY-DECIMAL-HEXADECIMAL CONVERSION TABLES --
D-l
HEXADECIMAL ARITHMETIC
ADDITION TABLE
9
A
09
OA
OA
08
OS
08
ex:
OC
00
DC
00
00
OE
OE
Of
OF
5
8
7
D
E
F
OD
OE
OF
10
Of
OF
10
11
OE
OF
10
11
12
oe
OF
10
11
12
13
OE
OF
10
11
12
13
14
OE
OF
10
11
12
13
14
15
OE
OF
10
11
13
14
14
10
11
12
12
OF
15
15
16
16
17
OF
10
11
12
13
15
16
17
18
10
11
12
14
16
17
18
19
15
15
16
17
18
19
lA
16
17
18
19
lA
18
17
19
lA
18
lC
lA
lB
lC
10
18
lC
10
1E
0
1
2
3
4
6
1
02
03
04
05
06
07
08
2
03
04
OS
06
07
08
09
3
04
05
06
07
08
09
OA
4
OS,,'
06
07
08
09
OA
5
06
07
08
09
OA
OB
6
07
08
09
OA
OB
7
8
08
09
OA
OB
09
OA
OB
ex:
9
OA
OB
OC
00
A
OB
DC
00
8
C
OB
OC
OC
00
OC
OD
OC
OD
00
13
14
8
ex:
00
OE
OF
10
11
12
13
13
14
C
00
DE
OF
10
11
12
13
14
15
0
OE
OF
10
11
12
13
14
15
16
E
OF
10
11
12
13
14
15
16
17
18
18
19
F
10
J1
12
13
14
15
16
17
18
19
lA
I
MUL l'IPLICATION TABLE
1
2
3
4
5
6
7
8
9
A
8
C
0
E
F
2
04
06
OB
OA
ex:
DE
10
12
14
16
18
lA
lC
IE
3
06
09
OC
OF
12
15
18
18
IE
21
24
27
2A
20
24
4
08
ex:
IE
lC
23
20
28
20
28
32
2C
37
30
3C
34
41
3C
Of
14
19
38
OA
10
14
18
5
46
48
6
OC
12
18
IE
24
2A
30
36
3C
42
48
4E
54
5A
7
OE
15
lC
23
2A
31
38
3F
46
40
54
5B
62
69
8
10
18
20
28
30
38
40
48
50
58
60
68
70
78
9
12
1B
24
20
36
3F
48
51
5A
63
6C
75
7E
87
A
14
32
3C
46
50
5A
64
82
37
42
40
63
8F
18
24
3C
48
54
6C
6E
78
84
C
58
60
8C
9A
96
2C
30
6E
79
78
16
IE
21
28
8
84
90
9C
A8
84
0
lA
27
34
41
4E
58
68
75
82
9C
A9
86
E
lC
38
46
54
62
70
7E
BC
A8
86
C4
C3
02
F
IE
2A
20 '
8f
9A
3C
48
SA
69
78
87
96
AS
64
C3
02
El
D-2
A5
POWE RS 0 F
nvo
tot.o
2
I 0.5
2 0.25
3 0.12'
~.
8
16
4
32
5 0.031 2'
64
128
256
512
I 024
2 0.48
0.062'
6 0.015 6ZS
7 0.007 812 S
,
8 0.003
0.001
1O 0.000
0.000
"
9'06 25
953 125
976 S61 5
488 281 25
.096 12 0.000 2-«
8 192 13 0.000 122
16 384 14 0.000 061
32 768 tS 0.000 030
65 536
131 072
262 1'4
52. 288
, 0.48 576
2 097 152
4194m
• 388 609
I,
m
21,
140
070
OJ,
511
625
312 5
156 25
578 125
\6 0.000 015 258 789
'7 0.000 007 629 394
18 0.000 (0) 814 691
IV 0.000 001 907 3.118
~
0.000
0.000
22 . 0.000
23 0.000
'I
062
531
265
632
5
25
625
812 S
000 953 674 31' 406 25
000 '76 817 158 X>J 125
000 238 .18 579 101 562 5
000 119 209
5:)() 781 25
m
33 S5-4 '32
67 lOS U4
134 217 728
24 0.000 000
25 0.000 000
26 0.000 000
27 0.000 OOQ
268 .3S 456
28
OS9
029
01.
001
6« n5' 390625
B02 322 387 1)95 312 5
9()1 161 193 8~] 656 .15
"SO sao 596 923 828 12S
6().C
0.000 000 003 n5 29() 298 461 "".062"
536 870 '12 29 0.000 000 001 862 645 149 230 9S7 031 2'
I 073 i'4I 824 30 0.000 000 000 931321 57. 61S .78 sa 625
J 147 483648 31 0.000 000 000 465 661 281 307 739 257 812 S
4 294 967 296
• 589 934 592
11 179 869 1M
3-4 3Sf 738 368
32 0.000 000
33 0.000 000
0.000 000
3l 0.000'000
~
68 7" 476 736 36 0.000 000
137 438 953 412 31 0.000 000
274 8n 906 9« 38 0.000 000
"'9 75S 813 888 39 0.000 000
1 099 SII 627 n6 40
2 199 023 2j5 552 41
4 398 ~ 511 104 42
796 093 022 208 "3
e
17 592 ,~ 0« 416
351M 372 088 832
10 368 7« 177 664
140 737 "S8 355 328
281 47.c 976 710 656
562 949 953 421 312
I 125 899 906 8.t2 6H
2 251 799 813 695 248
.c 503 599 627 370 496
9 007 199 25-4 740 992
18 014 398 509 ~81 984
36 o'a 797 018 963 968
n 051
l.e4 115
230
576 460
031
075
151
303
«
0.000
0.000
46 0.000
41 il.OOO
830 6-43 6.53 ~9 628 9Or6
o4lS 311 826 934 814 "53
207 ~., 9\3 467 407 226
103 83 ... 56 733 703613
2'
125
562 5
281 25
000- 014 551 '1.5 229 366 as, 806 6.&0 625
000 007 275957 614 183 425 903 320 312 5
coo 003 631 978 807 091 712 951 660 156 25
000 001 818 989 403 545 856 475 Bla 078 U5
0.000000 000
0.000 000000
0.000 000 000
0.000 000 ClOO
H
732
116
058
029
000 909 "'" 701
OOJ 45-4747350
000 227 373 675
000 113 686 837
000 000 000 056 843
000 000 000 028 421
000 000 000 014 210
000 OOR 000 007 105
418
709
e54
"21
777 928 217
886 0464·118
U3 232 OS9
721 616 029
915 039
95751'
478 159
139 379
860
430
715
351
869
434
717
858
800
404
202
601
014
007
003
001
689
8 ••
422
711
062 5
53125
765 625
882 812 S
941
970
..es
242
406
703
JSI
675
25
US
562 5
78\ 25
"8 0.000 000 000 000 003 552 713 678 800 SOO 929 355621 337 890 625
4' 0.000 000 000 000 OOt 776 356 B39 400 250 4604 677 810 668 945 312 5
so 0.000 000 000 000 000 88B 178 419 700 125232 339905 334 .72 656 25
51 0.000 000 000 000 000 4.. 089 209 850 062 616 169 .52 667 236 328 I2S
52
53
5.
55
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
222
III
05S
027
0.'
022
511
755
927
855
'711
423
936
872
744
56 0.000 000 000
57 0.000 000 000
58 0.000 000 (tOO
488, 59 0.000 000 000
000 000 013 877
000 000 006 938
000 000 003 "69
000 000 001 734
, 152 921 S04 606 846
2 305 9.e3 009 213 693
.c 611 686 018 "27 381
t 223 311 036 ~4 115
976
952
90.
IlO8
000
000
000
000
2~
594
188
376
752
000
000
000
000
60
6t
62
6l
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
ClOG
604
302
151
575
925031
462 515
231 257
615 628
309
65.
827
913
787 807 81. 456
893 9()3 907 228
446951 953614
723 "75976 80]
000 000 867 361 737
000 000 .el3 680 868
000 000 216 8.(0 4304
(100 000 101 420211
988
994
491
241
D-3
oe4
042
021
510
726
l6J
181
590
33J 618
166 809
583".1104
791 702
164
062
5·"
270
062 5
031 2S
015 625
S07112 5
755 295 395 851 135 253
377 6~7 697 925 567 626
18e 823 9.c8 962 783813
09 .. 4" 924.8\ 391 906
40J 5-47 205
201 773602
100 886 eol
5SO 44J 400
962 2.0 695 953
981 120 ~7 916
490 560 173 988
14" .210 OM "4
906
'5l
476
738
2S
125
562 5
281 25
369
684
)"2
171
1.0 625
510 312 5
21' 156 25
142 57. 125
, TABLE
or
POWEPS
or
SIXTEEN 10
4 503 599 627 370 496
13
72 057 594 037 927 936
14
1~"
0.10000 00000 00000 00000 x 10
1
0.62500 00000 00000 00000 x .102
0.39062 50000 00000 00000 x 103
0.24414 06250 00000 00000 x '104
0.15258 78906 25000 00000 x 106
0.95367 43164 06250 00000 x 10.
7
0.59604 64477 53906 25000 x 108
0.37252 90298 46191 40625 x 109
0.23283 06436 53869 62891 x 1010
0.J4551 91522 8~668 51807 x 10.
12
0.90949 47017 72928 23792 x 10.
13
0.56843 41886 08080 14870 x 1014
0.35527 J3678 80050 09294 x 10.
15
0.22204 46049 25031 30808 x 1016
0.13877 78780 78144 56755 x 10.
15
0.86736
16"
"
1
o
16
256
2
006
3
65 536
4
I 048 576
5
4
216
6
268 435 456
16 777
7
4 294 967 296
8
68 719 476 736
9
099' 511 '627 776
10
17 592
281
152 921
186 044 416
11
474 976 710 656
12
504 606 846 976
TAB I
10"
,.
or
.
POWER::>
or
17379 88403 54721
x
10. 18
1016
"o
I~OOO
0000
0000
0000
A
1
0.1999
9999
9999
999A
64
2
0.2 8F 5
C2SF
5C28
F5e3
x
3ES
3
0.4189
3748
C6A7
EF9E
x
16- 1
16- 2
2710
4
0.6808
88AC
710e
8296
x
J6- 3
86AO
5
O.A7C5
AC47
1847
8423
x
16- 4
F
4240
6
0.10C6
F 7 AD
B 5E 0
8037
x
16- 4
98
9680
7
0.IA07
F 29A
BCAF
4858
x
16- 5
5F5
E 100
8
0.2 AF 3
IOC4
6118
73BF
x
16- 6
389A
CAOO
9
0.4 4B 8
2FAO
9B5A
52(e
x
2
5408
E 400
10
0.6 OF 3
7F67
5EF6
EADF
x
16- 7
16- 8
17
4876
E SOO
11
O.AF E B
FFOB
(824
AAFF
x
16~9
ES
04A5
1000
12
0.1197
9981
20E A
1119
x
916
4E72
AOOO
13
0.IC25
e268
4976
81C2
)(
16- 9
16- 10
5AF3
107A
4000
14
0.2009
370D
4257
3604
)(
16 -11
3
S07E
A4C6
8000
15
0.480E
8E78
9058
566D
x
16- 12
23
8652
6FCI
0000
16
0.734A
eASF
6226
FOAE
x
16- 13
163
4578
5D8A
0000 .
17
0.8877
AA32
36A4
8449
x
16- 14
OEO
8683
A764
0000
18
0.127'2
5001
024 J
ABAI
x
8AC7
2304
89E8
0000
19
0.1083
C94f
8602
AC35
x
16- 14
16- 15
D-4
HEXADECIMAL·DECIMAL INTEGER
CONVERSIOr~
The table below proyldes (or direct conversions betweon hexo- ,
decimal Integers.>ln the range O-FFF and decImal Integers In
the range 0-4095. For eorlY.rslon of largt"r Integer., 'he '
table values may be added to the following figures:
Hexadecimal
OIOVO
4096
8 192
12288
16384
20480
24576
28672
32768
36 864
40960
45056 .
49 152
53248
57344
61440
65536
69632 .
73728 '
77824
81 920 .
86 016
90 112
94208
98304
102400
106 496
110592
02000
03000
04 000
05000
06 000
07000
08000
09000
OA 000
OB 000
OC 000
00000
OE 000
OF 000
10000
11 -000
12000
13000
14000
15 000,
16000
17000
t8000
19000
lA 000
18000
lC 000
000
010
070
030
O~O
0
1
0000 0001
0016 0017
0032 0033
0().i8 0049
2
3
0002
0018
0003
0019
0035
0034
0050 0051
20000
30000
40000
50000
60000 .
70000
80000
90000
AOOOO
80000
000
00000
EO 000'
FO 000
100000
200000
300 000
400 000
500000
600 000
700000
aoo 000
900000
AOO 000
BOO 000
COO 000
000000
Eoo 000
FOO 000
131072
196608
262 144
327660
393216
458752
524 288
589824
655 360
7208%
786 432
851 968
917504
983040
1 048576
2097 152
. 3 145728
' 4 194304
5 242 880
6 291 456
'1,340032
8388608
9437 164
10 485 760
11 534336
12582912
13631 408
14 680 ()6.4
co
1-000000
16777 216
IF 000
126 976
2000 000
33554432
4
S
0005
0020 0021
0036 0037
0052 0053
0004
6
7
0065
0001
0097
0113
OOB2
0098
0114
0067
0083
0099
0115
0100
0116
080
090
OAO
OBO.
0128
0144
0160
0176
0129 0130
0145 0146
0161 0162
0177 0178
0131
0147
0163
0179
0132 0133
0148 0149
0164 0165
0160 01BI
oeo
0192
0208
0224
0240
0193 0194 0195
0209 0210 0211
0225 0226 0227
0241 0242 02.3
0196
0212
0228
0244
0101
0117
8
9
IS 72861$0
A
8
0006 0007
0000 0009 0010 0011
0022
0038
0054
0024
0023
0039
0055
0068 <>ru9 0070 0071
0084 0085 0006 0087
0064
0080
0096
0112
OD<>
OEO
Of 0
Decimal
•
1E 000
050
060
070
0066
Hexadecimal
114668
118784
122 800
10000
,---
-
DecJma!
0102
0118
0103
0119
0134 0135
0150 0151
0166 0167
0)82 0183
0197 0198
0213 0214
0229 0230
0245 '0246
0199
0215
0231
0241
C
0
E
F
0014
0030
0062
0015
0031
0047
0063
0027
0043
0059
0012 0013
0028 0029
00« 0045
0060 0061
0075
0091
0107
0123
0076
0092
0108
0124
0077 0078
0093 0094
0109 0110
0125 0126
0079
0095
0111
0127
0136 0137 0138 0139
0152 0153 0154 0155
0168 0169 0170 017)
0184 0185 0186 0187
0140
0156
0172
0188
0141 0142
0157 0158
0173 0174
0189 0190
0143
0159
0175
0191
0204
0205
0206
0207
0040
0056
0025 0026
0041 ()().i2
0057 0058
0072 0073
0088 - nOB9
0104 0105
0120 0121
0074
0090
0106
0122
0200 0201 0202
0216 0217 0218
0232 0233 023-4
0248 0249 0250
D-5
0046
0203
02)9
0235
0220 0221 0222 0223
0251
0252 0253 0254 0255
0236
0237
0236
0239
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont.)
0
I
2
3
4
5
6
7
8
100
110
120
130
0256
0272
0289
0304
0257
0273
0289
0305
0258
0274
0290
0306
0259
0275
0291
0307
0260
0276
0292
0308
0261
0277
0293
0309
0262
0278
0294
03tO
0263
0279
0295
0311
0264
0280
0296
0312
140
150
160
170
0320
0336
0352
0368
0321
0337
0353
0369
0322
0338
0354
0370
0323
0339
0355
0371
032" 0325 0326
0340 0341 0342
0336 0357 0359
0372 0373 03704
034J
OJM
0328 0329
03-45
0359 , 0360 0361
0376 0377
0375
0330
0346
0362
0378
180
190
0384
0400
0416
0432
0385
0401
0417
0433
0386
0402
()418
0434
0387
0403
0419
0435
0388 0389 0390
0404 0405 a.. 06
0420 0421 0422
().436 0437 0438
0391
0407
0423
0439
0392
0.(08
0424
0440
0393
0409
0425
0441
0394
0410
0426
0442
0449
0465
0481
().497
()4S0 0451
0466 0467
0482 0483
0498 0499
0452
0468
0484
0500
0453
0469
0485
0501
0454
0470
0486
0502
0455
IFO
04-48
0464
0480
0496
0456
0472
0488
0504
0457
0473
0489
0505
200
210
220
230
0512
0528
0544
0560
0513 051~ 0515
0529 0530 0531
0545 • 0546 0547
0561 0562 0563
0516
0532
05-48
0564
0517
0533
0549
0565
0518 0519
0534 0535
0550 0551
0566 0567
0520 0521
0536 0537
0552 0553
()568 056~
240
250
260
270
0576 0577 0578
0592 0593 0594
0608 0609 0610
0624 0625 0626
0579
0595
0611
0627
0582
0598
0614
0630
280
290
2AO
280
0640 0641
0656 0657
0672 0673
0688 0689
0643
0659
2CO
200
2EO
2FO
lAO
IBO
lCO
100
lEO
0580 0581
0596 0597
" 0612 0613
0628 0629
0583
0599
9615
0631
06-45 0646 0647
0662 01>63
0677 0678 0679
0691
0644
0660
0676
0692
0693
069..
0695
0704
0720
0736
0752
0705 0706 0707
0721 0722 0723
0737 0738 0739
0753 0754 0755
0708
0724
0740
0756
0709
0725
0741
0757
0710
0126
0742
0758
0711
0727
300
310
320
330
0768
0784
0800
0816
0769
0785
0801
0817
0770
0786
0802
0818
0771
0787
0803
0819
0772
0788
0804
0820
0773
0789
0805
0821
0774
0790
0806
0822
0775
0791
340
350
360
370
0832
0848
0864
0880
0833
0849
0865
0881
0834
0850
0866
0882
0835
0851
0867
0883
0836
0852
0868
0884
0837
0B53
0869
0885
380
0896
0912
0928
0944
0897
0913
0929
0945
0898
0914
0930
0946
0899
0915
0931
0947
0900
0916
0932
0948
0901
0917
0933
0949
0642
0658
0674
0690
0675
8
0
E
F
0268
0284
0300
0316
0269
0285
0301
0317
0270
0286
0302
0318
0271
0287
0303
0319
0331
0347
0363
0379
0332
0348
0364
0380
0333
0349
0365
0381
0334
0350
0366
0382
0335
0351
0367
0383
0395
0427
0443
0396
0412
0428
0444
0397
0413
0429
0445
0398
0414
0430
0440
0399
0415
0431
0447
0458
0474
0490
0506
0459
0475
0491
0507
0460 0461 0462 0463
0476 0477 0478 0479
0491 ()493 0494 0495
0508 0509 0510 0511
0522
0538
0554
0570
0523
0539
0555
0571
0524
0540
0556
0572
0584 0585 0586
0600 0601 0602
~16
0617 0618
0632 0633 0634
. 0587
0265 0266 0267
0281 0282 0283
0297 0298 0299
0313 0314 0315
0327
0471
0487
0503
A
C
9
0411
0603
0619
0635
0648
0664
0680
0696
0649 0650 0651
0665 0666 0667
0681 0682 0683
0697 0698 0699
0712
0728
0744
0760
Oll3
0729
0745
0761
0714
0730
0746
0762
0823
0776
0792
0808
0824
0777
0793
0809
0825
0838
0854
0870
0886
0839
0B55
0871
0887
0640
0856
0872
0888
0902
0918
0934
0950
0903
0919
0935
0951
0904
0920
0936
0952
0661
0/43
0759
0807
0525
0541
0557
0573
0526
0542
0558
0574
0527
0543
0559
0575
0588 0589 0590 0591
0604 0605 0606 0607
0620 0621 0622 0623
Q6JO 0637 0638 0639
0654
0670
0685 0686
0701 0702
0655
0671
0687
0703
0715 ' 0716
0731
0732
0747 ," 0748
0764
0763
0717
0733
0749
0765
0719
0735
0751
0767
0778
0794
0810
0826
0779
0795
0811
0827
0780
0796
0812
0828
0781
0797
0813
0829
0841
OBS7
0873
0889
0842
OSS8
0874
0890
0843
0859
0875
0891
0844 0845 OW> 0847
0860 086\ 0862 0863
0876 0877 0878 0879
0892 0893 0894 0895
0905
0921
0937
0953
0906
0922
0938
0954
0907
0923
0939
0955
0908
0924
0940
0956
0652
0668
0684
0700
0653
0669
...
~
0718
0734
0750
0766
..
0782 0783
0798 0799
0814 0815
0830 0831
j
390
3AO
3BO
3CO
JOO
JEO
JFO
0960 0961
0976 0977
0992 0993
l00S 1009
0962 0963
0978 0979
0994 0995
1010 1011
0964 0965 0966 0967
0980 0981 0982 0903
0996 0997 0998 0999
lOl2 1()13 1014 1015
D-6
0968 0969 0970 0971
09&4 0985 0986 0987
1000 fOOl 1002 1003
1016 1017 lOIS lO19
0909
0925
0941
0957
0910
0926
0942
0958
091 I
0927
0943
0959
0972 0973 0974 0975
0988 0989 0990 0991
1004 1005 1006 t007
1020 102l t022 )023
HEXADEClMAL- DECIMAL INTEGER CONVERSION (Cont.)
0
1
2
400
410
420
430
1024
1040
1056
1072
1025
1041
1057
1073
1026
1042
105B
1074
440
450
460
470
1088
1104
1120
1136
1089
1105
1121
1137
1090
1106
1122
1138
C
0
E
F
1032 1033 1034 1035
1048 1049 1050 1051
1064 1065 1066 1067
1080 1081 1082 1083
1036
1052
I06B
1084
1037
1053
1069
1085
1038
1054
1070
1086
1039
1055
1071
1087
1095
1111
1127
1143
1096
1112
112B
1144
1099
1115
1131
1147
1100
1116
·1132
1148
. 1101
1117
1133
\149
1102
1118
1134
1150
1103
1119
1135
1151
1159
1175
1191
1207
1160 1161
1176 1177
1192 1193.
1208 1209
1163
1179
1195
1211
1164
1180
1196
1212
1165 1166
1181 1182
1197 1198
1213 1214
1167
1183
1199
1215
1223
1239
1255
1271
1224
1240
1256
1272
1225
1241
1257
1273
1226 1227
1242 1243
1258 1259
1274 1275
1228
1244
1260
1276
1229
1245
1261
1277
1230
1246
1262
1278
1231
1247
1263
1279
1285 12M 1287
1301 1302 1303
1317 1318 1319
1333 1334 1335
1288
1304
1320
1336
1289
1305
1321
1337
1290
1306
1322
1338
1291
1307
1323
1339
1292
. 1308
" 1324
1340
1293
1309
1325
1341
1294
1310
1326
1342
1295
1311
1327
1343
1354 1355
1370 1371
1386 1387
1402 1403
1356
1372
1388
1404
1357
1373
1389
1405
1358
1374
1390
1406
1359
1375
1391
1407
3
4
5
6
7
1027
1059
1075
1028
1044
1060
1076
1029
1045
1061
1077
1030
1046
1062
1078
1031
1047
1063
1079
1091
1107
1123
"39
1092
1108
1124
1140
1093
1109
1125
1141
1094
1110
1126
1142
1043
480
490
4AO
4BO
1152
1168
1184
1200
1153
1169
1185
1201
1154 1155
1170 1171
1186 1187
1202 1203
1156 1157
1172 1173
1188 1189
1204 1205
1158
1174
1190
1206
ACO
400
4EO
4fO
1216
1232
1248
1264
1217
1233
1249
1265
1218
1234
1250
1266
·1219
1235
1251
1267
1220 1221
1236 1237
1252 1253
1268 1269
1222
1238
1254
1270
500
510
520
530
1280
1296
1312
1328
1281
1297
1313
1329
1282
1298
\314
1330
1283
1299
1315
1331
128-i
1300
1316
1332
. •5.:4~
550.
560
570
\344
1360
1376
1392
1345
1361
1377
1393
1346
1362
1378
1394
1347
1363
1379
1395
1348 1349
1364 1365
1380 1381
1396 1397
580
590
SAO
580
1408
1424
1440
1456
1409
1425
1441
1457
1410
1426
1442
1.-i5S
1411
1427
1443
5CO
5DO
5EO
5FO
1472
1488
1504
1520
1473
1489
1505
1521
600
610
620
630
1536
1552
1568
1584
640
650
660
670
8
9
\
1097
1113
1129
1145
1350
1366
1382
1398
1351
1367
1383
1399
1352
1368
1364
1400
1353
1369
1385
1401
1459
1412
1428
1444
1460I,'
1413 1414
1429 1430
1445 1446
1461 1462
1415
1431
1447
1463
1416
1432
1448
1464
1417
1433
1449
1465
1474
1490
1506
1522
1475
1491
1507
1523
1476
1492
1508
1524
1477
1493
1509
1525
1478
1494
1510
1526
1479
1495
1511
1527
1537
1553
1569
1585
153B
1554
1570
1586
1539
1555
15it
1581
1540
15511
1572
1588
1541
1557
1573
1589
1542
1558
1574
1590
1600
16\6
1632
1648
1601
1617
1633
1649
1602
16J8
1634
1650
1603
1619
1635
1651
1604
1605
1620 1621
1636 1637
1652 1653
680
690
6AO
680
1664
1680
1696
1712
1665
1681
1697
1713
1666
1682
1698
1714
1667
1683
1699
1715
6(0
6DO
6EO
6FO
1728
1744
1760
1776
1729
1745
1761
1777
1730 1731
1746 1747
1762 1763
1778 1779
A
1098
1114
1130
1146.
1162
1178
,1194
1210
8
·1418
1434
1450
1466
1419
1435
1451
1467·
1420
1436
1452
1468
1421
1437
1453
1469
1422
1438
1454
. 1470
1423
1439
1455
1471
1480
14Bl 1482
1496 1497 1498
1512 1513 1514
1528 1529 1530
1483
1499
1515
1531
·1484
1500
1516
1532
1485
1501
.1517
1533
1486
1502
1518
1534
1487
1503
1519
1535
1543
1559
1575
1591
1544
1560
1576
1592
1545 1546 1547
1561 1562 1563
1577 1578 1579
1593 1594 1595
1548
1564
1580
1596
1549
1565
1581
1597
1550 1551
1566 1567
1582 1583
1598 1599
1606
1622
1638
1654
1607
1623
1639
1655
160B
1624
1640
1656·
1609
1625
1641
1657
1610
1626
1642
1658
1611
1627
1643
1659
1612
1628
1644
1660
1613
1629
1645
1661
1614
1630
1646
1662
1615
1631
1647
1663
1668 1669 1670
1684 1685 1686
1700 1701 1702
1716 1717 1718
1671
1687
1703
1719
1672
1688
1704
1720
1673
1689
1705
1721
1674 1675
1690 1691
1706 1707
1722 1723
1676 1677
1692 1693
1708 1709
1724 1725
1678
1694
1710
1726
1679
1695
1711
1727
1734
1750
1766
1782
1735
1751
1767
1783
1736
1752
1768
1784
1737
1753
1769
1785
1738
1754
1770
1786
1741
1757
1773
1789
1742
1758
1774
1790
1743
1759
1775
1791
1732
1748
1764
1780
1733
1749
1765
1781
':'
D-7
1739
1755
1771
1787
1740
1756
1772
1788
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont.)
0
1
2
3
4
1794
1810
1826
1842
1795
1811
1827
1843
1796
1812
1828
1844
5
7
8
9
1799
1815
1831
1847
1800
1816
1832
1848
1801
1817
1833
1849
1862 1863
1878 1879
1894 1895
1910 ·1911
1864
1880
1896
1912
1865
1881
1897
1913
1926
1942
1958
1974
1928
1944
1960
1976
6
1797
1798
1814
1829 1830
1845 1846
A
B
C
0
E
F
1802 1803
1818 1819
1834 1835
1850 1851
1804
1820
1836
1852
1805
1821
1837
1853
1806
1822
1838
1854
1807
1823
1839
1855
1866
1882
1898
1914
1867
1883
1899
1915
1868
1884
1900
1916
1869
1885
1901
1917
1870
1886
1902
1918
1871
1887
1903
1919
1929 1930
1945 1946
1961 1962
1977 1978
1931
1947
1963
1979
1932
1948
1964
1980
1933
1949
1965
1981
1934
1950
1966
1982
1935
1951
1967
1983
700
710
720
730
1792 1793
1808 1809
1824 1825
1840 1841
740
750
760
770
1856 1857 1858 1859
1872 1873 1874 1875
1888 1889 1890 1891
1904 1905 1906 1907
1860 1861
1876 1877
1892 1893
1908 1909
780
790
7AO
7BO
1920
1936
1952
1968
1921 1922
1937 1938
1953 1954
1969 1970
1923
1939
1955
1971
1924
1940
1956
1972
7CO
700
7EO
7FO
1984 1985 1986
2000 2001 2002
2016 2017 2018
2032 2033 2034
1987
2003
2019
2035
1988 1989 1990 1991
2004 2005 2006 2007
2020 2021 2022 2023
2036 2037 2038 2039
1992 1993 1994 1995
2008 2009 2010 2011
2024 2025 2026 2027
2040 2041 2042 2043
1996 1997 1998 1999
2012 2013 2014 2015
2028 2029 2030 2031
2044 2045 2046 2047
800
810
820
830
2048
2064
2080
2096
2049
2065
2081
2097
2050
2066
2082
2098
2051
2067
2083
2099
2052 2053
2068 2069
2084 2085
2100 2101
2060
2076
2092
2108
840
850
860
870
2112
2128
2144
2160.
2113
2129
2145
2161
2114 2115
2130 2131
2146 2147
2162 2163
880
890
8AO
880
2176
2192
2208
2224
2177
2193
2209
2225
2178
2194
2210
2226
aco
8FO
2240 2241
2256 2257
2272 2273
2288 2289
900
910
920
930
2304
2320
2336
2352
2305
940
950
960
970
2368
2384
2400
2416
2369
2385
2401
2417
980
800
BEO
2179
2195
2211
2227
2242 2243
2258 2259
2274 2275
2290 2291
1813
1925
1941
1957
1973
1927
1943
1959
1975
2054
2070
2086
2102
2055
2071
2087
2103
2056
2072
2088
2104
2057
2073
2089
2105
2058
2074
2090
2106
2116 2117 2118
2132 2133 2134
2148 2149 2150
2164 2165 2166
2119
2135
2151
2167
2120
2136
2152
2168
2121
2137
2153
2169
2122 2123
2138 2139
2154 2155
2170 2171
2180 2181
2196 2197
2212 2213
2228 2229
2182 2183
2198 2199
2214 2215
2230 2231
2245 2246 2247
2260 2261 2262 2263
2276 2277 2278 2279
2292 2293 2294 2295
2244
2059
2075
2091
2107
2061 2062 2063
2077 2078 2079
2093 2094 2095
2109 2110 2111
2124 2125
2140 2141
2156 2157
2172 2173
2126
2142
2158
2174
2127
2143
2159
2175
2184 2185 .2186 2187
2200 2201 2202 2203
2216 2217 2218 2219
2232 2233 2234 2235
2188 2189 2190
2204 2205 2206
2220 2221 2222
2236 2237 2238
2191
2207
2223
2239
2248
2253 2254
2269 2270
2285 2286
2301 2302
2255
2271
2287
2303
2249
2265
2280 2281
2296 2297
2250
2266
2282
2298
2251
2267
2283
2299
2252
2268
2284
2300
2264
2339
2355
2308 2109 2310
2324 2325 2326
2340 2341 2342
2356 2357 2358
2311
2327
2343
2359
2312 2313
2328 2329
23M 2345
2360 2361
2314
2330
2346
2362
2315
2331
2347
2363
2316 2317
2332 2333
2348 2349
2364 2365
2318 2319
2334 2335
2350 2351
2366 2367
2370
2386
2402
2418
2371
2387
2403
2419
2372
2388
2404
2420
2373
2389
2405
2421
2374
2390
2406
2422
2375
2391
2407
2423
2376 2377 2378
2392 2393 2394
2408 2409 2410
2424 2425 2426
2379
2395
2411
2427
2380 2381
2396 2397
2412 2413
2428 2429
2382
2398
2414
2430
9AO
980
2432
2448
2464
2480
2433 243.~
2449 2450
2465 2466
2481 2482
2435
2451
2467
2483
2436 2437
2452 2453
2468 2469
2484 2485
2438
2454
2470
2486
2439
2455
2471
2487
2440
2456
2472
2488
24-4·3
2459
2475
2491
2444 2445 2446 2447
2460 2461 2462 2463
2476 2477 2478 2479
2492 2493 2494 2495
9(0
900
9EO
9FO
2496
2512
2528
2544
2497
2513
2529
2545
2499
2515
2531
2547
2500 2501
2516 2517
2532 2533
2548 2549
2502 2503
2518 2519
2534 2535
2550 2551
2504
2508
2520
2524
990
2306
2321 2322
2337 2338
2353 2354
2498
2514
2530
2546
2307
2323
2441
2457
2473
2489
2442
2458
2474
2490
2505 2506 2507
2521 2522 2523
2536 2537 2538 2539
2552 2553 2554 2555
""~WII
D-8
2383
2399
2415
2431
2509 2510 7511
2525 2516 2527
2540 2541 2542 2543
2556 2557 2558 2559
d!I.-!.\lf'~"
all:
illj~.,~~
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont.)
.
0
,
2
3
4
5
6
7
8
9
A
B
._ C
0
AOO
Al0
A20
A30
2560'
2576
2592
2608
2561
2577
2593
2609
2562
2578
2594
2610
2563
2579
2595
2611
256"4
2580
2596
2612
256.S
2581
2597
2613
2566
2582
2598
2614
2567
2583
2599
2615
2568
2584
2600
2616
2569
2585
2601
2617
2570
2586
2602
2618
2571
2587
2603
2619
2572
2588
2604
: 2620
2573
2589
2605
2621
A40
A50
A60
A70
2624
2625
2640
2641
2628
2644
2660
2676
2629
2645
2661
2677
2630
2646
2662
2678
2631
2647
2663
2679
A80
A90
AAO
ABO.
2688 2689
2704 2705
2720 2721
2736 2737
2690
2706
2722
2738
2691
2707
2723
2739
2692
2708
2724
2740
2693
2709
2725
2741
2694
2710
2726
2742
2695
2711
2727
2743
ACO
ADO
AEO
AFO
2752 2753
2768 2769
2784 2785
2800 2801
2754
2770
2796
2802
2755
277i
2787
2803
2756
2772
2788
2804
2757
2773
2789
2805
2758
2774
2790
2806
2759
2775
2791
2007
BOO
BIO
B30
2816 2817 2818 2819
2832 2833 2834 2835
2848 2849 2850 2851
2864 2865 2866 2867
2820
2836
2852
2868
2821
2837
2853
2869
2822
2838
2854
2870
2823
2839
2855
2871
B40
B50
860
870
2880
?896
2912
2928
2881
2897
2913
2929
2884
2900
2916
2932
2885 2886 2e87
2901 2902 2903
2917 2918 2919
2933 2934 2935
B80
890
BAO
BBO
2944
2960
2976
2992
2945 2946 2947
2961 2962 2963
2977 2978 2979
2993 2994 2995
2948 2949 2950
2964 2965 2966
2980 2981 2982
2996 2997 2998
BCO
3009
3025
3041
3057
B20
2626 2627
2642 2643
2656 2657 2658 2659
2672 2673 2674 2675
i
'
E
r-
2574 2575
2590 2591
2606 2607
2622 2623
2632 2633
2649
2664 2665
2680 2681
2634 2635
2650 2651
2666 2667
2682 2683
2636 2637 2638
2652 2653 2654
2668 2669 2670
2684 2685 2686
2639
2655
2671
2687
2696
2712
2728
2744
2698
2714
2730
2746
2700
2716
2732
2748
2702
2718
2734
2750
2703
2719
2735
2751
2648
2697
2713
2729
2745
2699
2715
2731
2747
2760 2761 2762 2763
2777 2778 2779
2792 2793 2794 2795
2808 2809 2810 2811
2776
2824 2825
2840 2841
2856 2857
~872 2873
2701
2717
. 2733
2749
2766 2767
2782 2783
2798 2799
2764 2765
- 2780 2781
2796 2797
. 2812 2813
2814
281S
2826
2842
2858
2874
2827
2843
2859
2875
2828
2844
2960
2876
2829
2845
2861
·2877
2930
2846
2862
2878
2831
2847
2863
2879
2891
2907
2923 . .
2939
2892
2908
2924
2940
2893
2909
2925
2941
2894
2910
2926
2942
2895
2911
2927
2943
\
2882 2883
2898 2899
2914 2915
2930 2931
2888
2904
2920
2936
2889
2905
2921
2937
2890
2906
2922
2938
299.9
2952
2968
2984
3000
2953
2969
2985
3001
295" 2955
2970 2971
29U 2987
3002 3003
2951
2967
2983
·2956 2957
2972 2973
2988 2989
3004 3005
2958 2959
2974 2975
2990 2991
3006 3007
BEO
BfO
3008
3024
3040
3056
3010
3026
3042
3058
301t
3027
3043
3059
3012 3013
30'~8 3029
3044 3045
3060 3061
3014
3030
3046
3062
3015
3031
3047
3063
3016
3032
3048
3064
3017 3018 3019
3033 3034 3035
3049 3050 3051
3065 3~6 3067
3020
3036
3052
3068
3021
3037
3053
3069
3022
3038
3054
3070
3023
3039
3055
3071
COO
C10
C20
C30
3072 3073 3074
J088 3089 3090
3104 3105 3106
3120 3121 3122
3075
3091
3107
3123
3076
3092
3108
3124
3077
3093
3109
3125
3078
3094'
3110
3126
3079
3095
3 I t1
3127
3080
3096
3112
3128
3081
3097
3113
3129
3082
3098
31U
3130
30B3
3099
3115
3131
3084
3100
3116
3132'
3065
3101
3117
3133
3086
3102
3118
3134
3087
3103
3119
3135
C40
C50
C60
C70
3136
3152
3168
3184
3137
3153
3169
3185
3138
3154
3170
3186
3139
3155
3171
3187
3140
3156
3172
3188
3141
3157
3173
3189
3142
3158
3174
3190
3143
3159
3175
3191.
3144
3160
3176
3192
3145
316i
3177
3193
3146
3162
3178
3194
3147
3163
3179
3195
3148
3164
3180
3196
3149
3165
318-1
3197
3150
3166
3182
3198
3151
3167
3183
3199
C80
C90
CAO
3200
3216
3232
3248
3201
3217
3233
3249
~ 3202
3203
3218 3219
3234 3235
3250 3251
3204
3220
3236
3252
3205
3221
3237
3253
3206
3222
3238
3254
3207
3223
3239
·3255
3208
3224
3240
3256
3209
3225
3241
3257
3210
3226
3242
3258
3211
3227
3243
3259
3212
3228
3244
3260
3213
3229
3245
3261
3214
3230
3246
3262
3215
3231
3247
3263
3264 3265
3280 3281
3296 3797
3312 3313
3266
3282
3298
3314
3267
3283
3299
3315
3268
3284
3300
33;6
3269
3285
3301
3317
3270
3286
3302
3318
!2;1
3287
3303
3319
3272
3288
3304
3320
3273 3274 3275
3289 3290 3291
3305 3306 3307
3321 3322 3323
3276
3292
3308
3324
3277 3278
3293 3294
3309 3310
3325 3326
3279
3295
331 I
3327
BOO
ceo
ceo
COO
CEO
efO
D-9
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont.)
000
010
020
030
040
050
060
070
080
090
DAQ
080
oeD
DDO
DEO
DFO
EOO
0
I
2
3
..
5
6
7
8
"9.
A
8
C
0
3328
3344
3360
3376
3329
3345
3361
3377
3330
3346
3362
3378
3331
3347
3363
3379
3332
3348
3364
3380
3333
3349
3365
3381
3334
3350
3366
3382
3335
3351
3367
3383
3336
3352
3368
3384
3337
3353
3369
3385
3338
3354
3370
3386
3339
3355
3371
3387
3340
3356
3372
3388
3341
.3357
3373
33B9
3392 3393
3409
3424 3425
3440 3441
3394
3410
3426
3442
3395
3411
3427
3443
3396
3412
3423
3444
3397
3413
3429
3445
3398
3414
3430
3446
3399
3415
3·Ut
3447
3400 3401
3416 3417
3432 3~33
3448 3449
3402
3418
3434
3450
3403
3419
3451
3404
3420
3436
3452
3405 3406 3407
3421 3422 3423
3437 3438 3439
3453 3454 3455
3456 3457 3458 3459
3472 3473 3474 3475
3488 3489 3490 3491
3504 3505 3506 3507
3460
3476
3492
3508
3461
3477
3493
3509
3462 3463
3478 3479
3494 3495
3510 3511
3464
3480
3496
3512
3465 3466 3467
3481 3482 3483
3497 3498 3499
3513 3514 35.15
3468
3484
3500
3516
3469
3485
3501
3517
3470
3486
3502
3518
3471
3487
3503
3519
3520 3521
3536 3537
3552 3553
3568 3569
3524
3540
3556
3572
3525
3541
3557
3573
3526 3527
3542 3543
3558 3559
3574 3575
352'8
3544
3560
3576
3529
3545
3561
3577
"3530
3546
3562
3578
3531
3547
3563
3579
3532
3548
3564
3580
3533
3549
3565
3581
3534
3550
3566
3582
3535
3551
3567
3583
3588
3604
3620
3636
3589 3590 3591
3605 ~606 3607
3621 3622 3623
3637 3638 3639
3592
3608
3624
3640
3593
3609
3625
3641
3594
361-0
3626
3642
3595
3611
3627
3643
3596
3612
3628
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inter
West: 17291 Irvine Blvd., Suite 262/(714)838-1126, TWX: 910-595-1114/Tustin, California 92680
Mid-America: 800 Southgate Office Plaza/501 West 78th St./(612)835-6722, TWX: 910-576-2867/Bloomington, Mi"nnesota 55437
Northeast: 2 Militia Drive, Suite 4/(617)861-1136, Telex: 92-3493/Lexington, Massachusetts 02173
Mid-Atlantic: 21 Bala Avenue/(215)664-6636/Bala Cynwyd, Pennsylvania 19004
Europe: Intel OfficelVester Farimagsgade 7/45·1-11 5644, Telex: 19567/DK 1606 Copenhagen V
Orient: Intel Japan Corp.lHan·Ei 2nd Building/1-1, Shinjuku, Shinjuku-Ku/03-354-8251, Telex: 781-28426/Tokyo 160
© 1973/Printed in U.S.A./MCS-030-1273-150
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2010:11:15 14:47:47-08:00 Modify Date : 2010:11:15 17:27:51-07:00 Metadata Date : 2010:11:15 17:27:51-07:00 Producer : Adobe Acrobat 9.4 Paper Capture Plug-in Format : application/pdf Document ID : uuid:fcf08d1d-1650-4959-bc1a-0c6c6b7610e7 Instance ID : uuid:19f5e6d5-1cc8-4981-b48e-c7327243638b Page Layout : SinglePage Page Mode : UseOutlines Page Count : 149EXIF Metadata provided by EXIF.tools