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MCS·51® FAMILY OF
SINGLE CHIP MICROCOMPUTERS
USER'S MANUAL
JANUARY 1981
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which
may appear in this document nor does it make a commitment to update the information contained herein.
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or
disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7-104.9 (a) (9). Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No
other circuit patent licenses are implied.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of Intel Corporation.
The following trademarks of Intel Corporation and its affiliates may only be used to describe their products:
BXP
CREDIT
i
ICE
ICS
im
Insite
Intel
Intelevision
Intellec
iSBC
iSBX
Library Manager
MCS
Megachassis
Micromap
MULTIBUS*
MULTIMODULE
PROMPT
Promware
RMX
UPI
/AScope
and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of
Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
© INTEL CORPORATION, 1981
AFN·01300A·1
Table of Contents
CHAPTER 1
Introduction
ManualOrganization .................................... 1-1
Product Overview ....................................... 1-1
CHAPTER 2
Functional Description
8051 CPU Architecture ................................... 2-1
CPU Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
On-Chip Peripherals ..................................... 2-5
CHAPTER 3
Memory Organization, Addressing Modes and Instruction Set
Memory Organization .................................... 3-1
Addressing Modes ...................................... 3-2
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
CHAPTER 4
Expanded 8051 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
CHAPTER 5
8051 Software Routines
8051 Programming Techniques ............................. 5-1
Peripheral Interfacing Techniques ......................... 5-9
CHAPTER 6
Device Specifications ................................... 6-1
CHAPTER 7
Component Data Sheets
8048 Family
8021 Single Component 8-Bit Microcomputer ........... 7-1
8021 L Single Component 8-Bit Low Power (10mA)
Microcomputer ................................. 7-4
8022 Single Component 8-Bit Microcomputer with On-chip
AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·6
8022H High Performance Single Component 8-Bit Microcomputer with On-chip AID Converter ............. 7-12
8048H/8048H-1/8035HLl8035HL-1 HMOS Single Component
8-bit Microcomputer ........................... 7-13
8048L Special Low Power Consumption Single Component
8-Bit Microcomputer ........................... 7-20
8049H/8039HL HMOS Single Component 8-Bit
Microcomputer ................................ 7-27
8243 MCS-48® Input/Output Expander ............... 7-34
iii
AFN·01739A
~
••• -
...........
'-'MAt" I
en
, ' ' ' _ _ .& \
I ,\JUIU.,
8085 Peripherals
8155/8156/8155-2/8156-2 2048 Bit Static MaS RAM with 1/0
Ports and Timer ................................ 7-40
8185/8185-2 1024 x 8-Bit Static RAM for MCS-85® ....... 7-47
8355/8355-2 16,384-Bit ROM with 1/0 ............... '" 7-51
8755A/8755A-2 16,384-Bit EPROM with 1/0 ............. 7-56
Standard Peripherals
8041A/8641A/8741A Universal Peripheral Interface 8-Bit
Microcomputer ................................ 7-65
8205 High Speed lout of 8 Binary Decoder ............ 7-74
8251A/S2657 Programmable Communication Interface .. 7-78
825318253-5 Programmable Interval Timer ............. 7-83
8255A/8255A-5 Programmable Peripheral Interface ..... 7-92
8271/8271-6/8271-8 Programmable Floppy Disk
Controller ................................... 7-100
8273/8273-4/8273-8 Programmable HDLCISDLC Protocol
Controller ................................... 7-108
8275 Programmable CRT Controller ................. 7-115
8279/8279-5 Programmable KeyboardlDisplay Interface. 7-139
8282/8283 Octal Latch ............................. 7-148
8286/8287 Octal Bus Transceiver .................... 7-153
8291 GPIB TalkerlListener ......................... 7-158
8292 GPIB Controller ............................. 7-173
8293 GPIB Transceiver .......................... " 7-175
8294 Data Encryption Unit ....................... " 7-188
8295 Dot Matrix Printer Controller ................... 7-189
RAM
2114A 1024 x 4-Bit Static RAM .................... "
2142 1024 x 4-Bit Static RAM .......................
2148 1024 x 4-Bit Static RAM .......................
2148H 1024 x 4-Bit Static RAM ......................
2118 Family 16,384 x 1-Bit Dynamic RAM ........... "
2147H High Speed 4096 x 1-Bit Static RAM ...........
7-198
7-202
7-206
7-210
7-214
7-225
EPROM
2716 16K (2K x 8) UV Erasable PROM ................
2732 32K (4K x 8) UV Erasable PROM ................
2732A 32K (4K x 8) UV Erasable PROM ...............
2758 8K (1 K x 8) UV Erasable Low Power PROM
7-229
7-234
7-238
7-239
CHAPTER 8
Development Support Tools
Intellec® Series 11/85 Model 225 ........................... 8-2
Intellec® SjngleIDouble Density Flexible Disk System ........ 8-7
8051 Software Development Package ..................... 8-11
ICE-51TM 8051 In-Circuit Emulator ......................... 8-14
UPP 103 Universal PROM Programmer ..................... 8-20
SDK-51 MCS-51 System Design Kit ........................ 8-22
iv
AFN·01739A
APPENDIX A
PUM-80 Description of 8051 Instruction Set ................. A-1
APPENDIX B
An Introduction to the Intel MCS-51 Single-Chip Microcomputer
Family ............................................ B-1
APPENDIX C
Using the Intel MCS-51 Boolean Processing Capabilities ...... C-1
v
AFN·01739A
I
CHAPTER 1
INTRODUCTION
MANUAL ORGANIZATION
8051 Family
This publication describes Intel's 8051 family of single
chip microcomputers. It is written for engineers, technicians and students who understand basic microcomputer operating principles. The manual provides a comprehensive reference guide for the 8051 family.
The 8051 family has three members: The 8031, 8051,
and 8751. The 8031 is a CPU-only device, the 8051 has
4K bytes of factory-masked ROM and the 8751 has 4K
bytes of EPROM. The generic term "8051" is used to
refer collectively to the 8031, 8051 and 8751.
The manual organization is by chapters and appendices.
Chapter 1 provides a brief introduction to the
MCS-51® family, its software tools, and its development support in the most general terms.
Supporting the applications of the '80s is the target of
the 8051 family. On a single die the 8051 microcomputer
combines CPU; non-volatile 4K x 8 read-only program
memory (8051 and 8751); volatile 128 x 8 read/write
data memory; 32 110 Hnes; two 16-bit timer/event
counters; a five-source, two-priority-Ievel, nested interrupt structure; serial 110 channel for either
multiprocessor communications, I/O expansion, or full
duplex UART; and on-chip oscillator and clock circuits.
The second chapter provides a functional description of
the 8051 family hardware.
The third chapter describes the 8051's family memory
organization, addressing modes, data types and its instruction set.
The CPU is in a 40-pin package and uses a single 5V
power supply. Intel's HMOS process technology is the
driving force behind the 8051's ability to bring many
peripheral functions on-board a single-chip microcomputer.
The fourth chapter is an expanded 8051 family configured system using peripherals and external program
and external data memories.
Chapter 5 lists software routines that handle programming applications such as radix conversions and stack
mani pulations.
Along with 4K program memory on-board, the 8051 can
address another 60K of external program memory. If
external data memory is needed the 8051 can also address 64K of external RAM. When an 8031 is used, all
program memory execution is external and it, too, can
address 64K of both external program and data
memory. The 8051 contains many features for ease of
manipulating variables in Internal Data Memory. The
stack may be located anywhere within the internal RAM
space. There are 4 banks of registers (eight registers in
each bank) that facilitate context switching and provide
byte efficiency. Also within the Internal Data Memory
are the Special Function Registers. These are memorymapped locations for the ports, arithmetic registers,
control and status registers and the timer/counters.
The chapter following, the sixth, is the specification section for the 8051 family. A.C. and D.C. characteristics
of the 8051 family are located here.
Chapter 7 provides data sheets on Intel products that
can be used in conjunction with the 8051.
The next chapter describes the development support
available for the 8051 family.
That's the end of the chapters, but there are two appendices. Appendix A is a PL/M-80 description of the 8051
instruction set. Appendix B is the AP Note section
where AP-69 and AP-70 are reproduced in their entirety. AP-69 is titled, "An Introduction to the Intel®
MCS-51 ® Single-Chip Microcomputer Family" and
AP-70 is titled, "Using the Intel® MCS-51® Boolean
Processing Capabilities."
Within the Internal Data Memory are 256 individually
addressable bits. 128 bits are located in the Internal
Data RAM and the second 128 bits are located in the
Special Function Register. These 256 addressable bits
provide a new dimension in controller applications. The
programmer/designer may now manipulate individual
bits with specific bit instructions! This new feature is the
Boolean Processor, which is actually a bit processor
with its own accumulator, 110 and instruction set.
PRODUCT OVERVIEW
Introduced in May, 1980, Intel's 8051 family of singlechip microcomputers is the next generation microcomputer for the controller marketplace. With an expandable and flexible architecture the 8051 family provides
high performance for the applications of the future.
To increase programming ease the 8051 added new addressing modes. Direct Addressing was added to
manipulate variables within the 128-byte Data RAM
1·1
INTRODUCTION
and the Special Function Registers. Base-Register plus
Index-Register Indirect Addressing gives the programmer the ability to easily manipulate constants in program memory for table look-ups. Table look-ups are
supported over the entire 64K range by using 16-bit
registers.
3)
Since microcontrollers are real-time oriented, the 8051
has four 8-bit ports for interfacing to the external
world. Three of the four ports, under software control,
can have additional capabilities. Port 0 is a time multiplexed bus. It outputs the lower 8 bits of the 16-bit address and also receives data and instruction during an
external RAM read or external program memory operation. Port 0 also outputs the data when a write operation is performed. Port 2 emits the upper 8-bits of the
16-bit address when external memories are being accessed. Port 3 contains the special control signals such
as the read and write strobes, the two external interrupt
inputs, the two counter inputs and the transmit and
receive pins of the serial channel. Port 1 is strictly an
8-bit quasi-bidirectional port.
A more in-depth explanation of the 8051 's memory
spaces, addressing modes and instruction set is provided
in Chapter 3.
The 8051 hardware and on-chip peripherals have been
briefly described a few paragraphs earlier. Let's add a
little more detail in the following paragraphs. For complete operational and functional explanation of the
following features please read Chapter 2.
MCS-51 family has two independent, 16-bit timer/
counters. Under software control, each timer/counter
may be placed in one of four modes:
0)
1)
2)
3)
Development Support Tools
An 8-bit timer/counter with a divide-by-32
prescaler
A 16-bit timer/counter
An auto-reload 8-bit timer/counter
A mode which provides the programmer/designer
with two timers and a counter for added flexibility
Intel provides the tools needed for efficient, low risk
development of products using the 8051 family. These
development tools are based on the Intellec® Series II
Microcomputer Development System. The Intellec
system runs ISIS-II, a disk-based operating system being used in thousands of customer installations. This
same hardware and operating system can also be used to
develop systems based on other Intel microprocessor
families such as the iAPX 86, iAPX 88, 8085 and 8048.
There is a five-source interrupt system. The user has
software control over enabling/disabling the interrupts
and assigning priority levels to the interrupt sources.
The two external interrupts, under software control, can
be either transition or low-level activated.
ASM-51, the 8051 macro assembler provides assembly
language programming for the 8051. Symbolic references (i.e., names) to 8051 hardware features are supported.
Two of the three internal interrupt sources generate an
interrupt request when the overflow of the timer/
counters occurs. The third interrupt source generates an
interrupt request from the serial channel when the
receiver register is full or when the transmitter register is
empty.
The Universal PROM Programmer can program any of
Intel's PROM memories. To program and verify the
8751, an 8751 personality card adapter should be used.
Programming and verification operations are initiated
from the Intellec development system console and are
controlled by the Universal PROM Mapper program.
Serial data communication is accomplished by the
8051's serial channel. Operation is flexible by providing
user-programmable baud rates, two choices of frame
size and multiprocessor communications. There are
four modes of operation:
0)
1)
2)
A programmable baud rate from 122 to 31,250 bits
per second (12MHz operation) for a 9-bit frame
and asynchronous operation.
The SDK-51, System Design Kit, is an 8031-based prototyping and evaluation kit. It includes the CPU, RAM,
I/O ports and a breadboard area for interfacing to
customer circuits. A ROM-based monitor program,
single-line assembler and disassembler are supplied with
the kit. Monitor commands may be entered from an onboard keypad or from a terminal. Monitor commands
allow programs to be entered, run, stopped and singlestepped; memory contents can be altered as well as
displayed.
An 8-bit frame, synchronous mode which allows
110 expansion using shift registers. A clock output
is provided by the 8051.
An 8-bit frame, asynchronous mode handling programmable baud rates from 122 to 31,250 bits per
second (l2MHz operation).
A 9-bit frame, asynchronous mode that has a fixed
baud rate of 187 .5K bits per second (l2MHz operation)
The ICE-5 FM In-Circuit Emulator provides real-time
1-2
AFN-01739A
INTRODUCTION
symbolic debugging support for the 8051 microcomputer. A 40-pin probe replaces the 8051 in the system
under test. This probe is connected to a specifically configured 8051 "bond-out" chip which makes internal 8051
hardware available to ICE-51 circuitry. The ICE-51
module emulates the 8051 in the system under test in
response to commands entered through the Intellec console. These commands allow the user to debug the
system by setting breakpoints, tracing the flow of execution, single-stepping, examining and altering memory
and flO, etc.
All references to program variables and labels are symbolic (i.e., their ASM-51 names). Software testing can
also map "system under test" memory into the full speed
ICE-51 memory to permit software testing to begin
before prototype hardware has been developed.
1-3
AFN-01739A
1,1\
i
CHAPTER 2
FUNCTIONAL DESCRIPTION
This chapter explains the functions of the 8051. The
first part begins with a brief description of the memory
spaces and addressing modes. (For more in-depth information, please see Chapter 3.) The chapter then explains
the hardware registers, the ALU, and Boolean Processor.
Conditional branches are performed relative to the Program Counter. The register-indirect jump permits
branching relative to a 16-bit base register with an offset
provided by an 8-bit index register. Sixteen-bit jumps
and calls permit branching to any location in the contiguous 64K Program Memory address space.
The second part of Chapter 2 explains in detail the
workings of the on-chip peripherals: the interrupt
system, the I/O pins, the timer/counters and the serial
channel.
The 8051 has five methods for addressing source
operands: Register, Direct, Register-Indirect, Immediate, and Base-Register-plus Index Register-Indirect
Addressing.
The first three methods can be used for addressing
destination operands. Most instructions have a "destination, source" field that specifies the data type, addressing methods and operands involved. For operations
other than moves, the destination operand is also a
source operand.
8051 CPU ARCHITECTURE
The 8051 CPU manipulates operands in four memory
spaces. These are the 64K-byte Program Memory,
64K-byte External Data Memory, 384-byte Internal
Data Memory and 16-bit Program Counter spaces. The
Internal Data Memory address space is further divided
into the 256-byte Internal Data RAM and 128-byte
Special Function Register (SFR) address spaces shown
in Figure 2-1. Four Register Banks (each bank has eight
registers), 128 addressable bits, and the stack reside in
the Internal Data RAM. The stack depth is limited only
by the available Internal Data RAM. Its location is
determined by the 8-bit Stack Pointer. All registers except the Program Counter and the four 8-Register
Banks reside in the Special Function Register address
space. These memory mapped registers include
arithmetie registers, pointers, I/O ports, and registers
for the interrupt system, tim~rs and serial channel. 128
bit locations in the SFR address space are addressable
as bits. The 8051 currently contains 128 bytes of Internal Data RAM and 20 Special Function Registers.
I
Registers in the four 8-Register Banks can be accessed
through Register, Direct, or Register-Indirect Addressing; the 128 bytes of Internal Data RAM through Direct
or Register-Indirect Addressing; and the Special Function Registers through Direct Addressing. External Data
Memory is accessed through Register-Indirect Addressing. Look-up Tables resident in Program memory can
be accessed through Base Register-plus Index RegisterIndirect Addressing.
The 8051 is classified as an 8-bit machine since the internal ROM, RAM, Special Function Registers, Arithmetic/Logie Unit and external data bus are each 8-bits
wide. The 8051 performs operations on bit, nibble, byte
and double-byte data types.
64K
64K
EXTERNAL
OVERLAPPED SPACE
I
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4095
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255 I
INTERNAL
I
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PROGRAM
COUNTER
0
12~
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Il
255
128
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PROGRAM
MEMORY
INTERNAL
DATA RAM
SPECIAL
FUNCTION
REGISTERS
EXTERNAL
DATA
MEMORY
INTERNAL DATA MEMORY
Figure 2·1. 8051 Family Memory Organization
2-1
AFN·01739A
FUNCTIONAL DESCRIPTION
Register Banks
The 8051 has extensive facilities for byte transfer, logic,
and integer arithmetic operations. It excels at bit handling since data transfer, logic and conditional branch
operations can be performed directly on Boolean
variables.
There are four Register Banks within the Internal Data
RAM. Each Register Bank contains registers R7-RO.
128 Addressable Bits
The 8051 's instruction set is an enhancement of the instruction set familiar to MCS-48 users. It is enhanced to
allow expansion of on-chip CPU peripherals and to optimize byte efficiency and execution speed. Op codes
were reassigned to add new high-power operations and
to permit new addressing modes which make the old
operations more orthogonal. Efficient use of program
memory results from an instruction set consisting of 49
single-byte, 45 two-byte and 17 three-byte instructions.
When using a 12MHz crystal, 64 instructions execute in
1 ~s and 45 instructions execute in 2 ~s. The remaining
instructions (multiply and divide) require only 4 ~s. The
number of bytes in each instruction and the number of
oscillator periods required for execution are listed in the
Instruction Set in Chapter 3 in Table 3-2.
There are 128 addressable software flags in the Internal
Data RAM. They are located in the 16 byte locations starting at byte address 32 and ending with byte location 47 of
the RAM address space.
Stack
The stack may be located anywhere within the Internal
Data RAM address space. The stack may be as large as 128
bytes on the 8051.
SPECIAL FUNCTION REGISTERS
The Special Function Registers include arithmetic
registers (A, B, PSW), pointers (SP, DPH, DPL) and
registers that provide an interface between the CPU and
the on-chip peripheral functions. There are also 128 addressable bits within the Special Function Registers. The
memory-mapped locations of these registers and bits are
discussed in Chapter 3.
CPU HARDWARE
This section describes the hardware architecture of the
8051's CPU in detail. The interrupt system and on-chip
functions peripheral to the CPU are described in subsequent sections. A detailed 8051 Functional Block
Diagram is displayed in Figure 2-2.
The A register is the accumulator.
Instruction Decoder
B Register
Each program instruction is decoded by the instruction
decoder. This unit generates the internal signals that control the functions of each unit within the CPU section.
These signals control the sources and destination of data,
as well as the function of the Arithmetic/Logic Unit
(ALU).
The B register is dedicated during multiply and divide and
serves as both a source and a destination. During all other
operations the B register is simply another location of the
Special Function Register space.
Program Counter
The carry (CY), auxiliary carry (Aq, user flag 0 (FO),
register bank select (RSO and RSl), overflow (OV) and
parity (P) flags reside in the Program Status Word (PSW)
Register. These flags are bit-memory-mapped within the
byte-memory-mapped PSW. The PSW flags record processor status information and control the operation of
the processor.
A Register
Program Status Word Register
The 16-bit Program Counter (Pq controls the sequence in
which the instructions stored in program memory are executed. It is manipulated with the Control Transfer instructions listed in Chapter 3.
Internal Program Memory
The 805118751 have 4K bytes of program memory resident on-chip.
INTERNAL DATA RAM
The CY, AC, and OV flags generally reflect the status of
the latest arithmetic operations. The P flag always reflects
the parity of the A register. The carry flag is also the
Boolean accumulator for bit operations. Specific details
on these flags are provided in the Arithmetic Flags section
of Chapter 3. FO is a general purpose flag which is pushed
onto the stack as part of a PSW save. The two Register
Bank select bits (RSI and RSO) determine which one of the
four Register Banks is selected.
The Internal Data RAM provides a convenient 128-byte
scratch pad memory.
The 8~bit Stack Pointer (SP) contains the address at which
Internal Data Memory
The 8051 contains a 128-byte Internal Data RAM (which
includes registers R7-RO in each of four Banks), and twenty memory-mapped Special Function Register.
Stack Pointer
2-2
AFN-01739A
FUNCTIONAL DESCRIPTION
11
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2-3
AFN-01739A
FUNCTIONAL DESCRIPTION
Hie last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. SP can be read or written to
under software control.
Serial Data Buffer
The Serial Data Buffer (SBUF) register is used to hold
serial port input or output data depending on whether the
serial port is receiving or transmitting data.
Data Pointer (High) and Data Pointer (Low)
The 16-bit Data Pointer (DPTR) register is the concatenation of registers DPH (data pointer's high-order byte) and
DPL (data pointer's low-order byte). The DPTR is used in
Register- Indirect Addressing to move Program Memory
constants, to move External Data Memory variables, and
to branch over the 64K Program Memory address space.
ARITHMETIC SECTION
The arithmetic section of the processor performs many
data manipulation functions and is comprised of the
Arithmetic/Logic Unit (ALU), A register, B register and
PSW register. The ALU accepts 8-bit data words from one
or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the
arithmetic operations of add, subtract, multiply, divide,
increment, decrement, BCD-decimal-add-adjust and
compare, and the logic operations of and, or, exclusiveor, complement and rotate (right, left, or nibble swap (left
four».
Port 3, Port 2, Port 1, Port 0
The four ports provide 32 I/O lines to interface to the external world. All four ports are both byte and bit addressable. The 8051 also allows memory expansion using
Port 0 (PO) and Port 2 (P2) while Port 3 (P3) contains
special control signals such as the read and write strobes.
Port 1 (PI) is used for 110 only.
PROGRAM CONTROL SECTION
Interrupt Priority Register
The program control section controls the sequence in
which the instructions stored in program memory are executed. The conditional branch logic enables conditions
internal and external to the processor to cause a change in
the sequence of program execution.
The Interrupt Priority (lPC) register contains the control
bits to set an interrupt to a desired level. A bit set to a one
gives the particular interrupt a high priority listing.
Interrupt Enable Register
OSCILLATOR AND TIMING CIRCUITRY
The Interrupt Enable (lEC) register stores the enable bits
for each of the five interrupt sources. Also included is a
global enable/disable bit of the interrupt system.
Timing generation for the 8051 is completely selfcontained, except for the frequency reference which can
be a crystal or external clock source. The on-board
oscillator is a parallel anti-resonant circuit with a frequency range of 1.2MHz to 12MHz. There is adivide-by-12 internal timing which gives the 8051 a minimum instruction
cycle of 1 iJ.sec. with a 12MHz crystal. The XT AL2 pin is
the output of a high-gain amplifier, while XT ALl is its input. A crystal connected between XT ALl and XT AL2
provides the feedback and phase shift required for oscillation. U XT ALl is being driven by an external frequency
source, XT AL2 should be a no connect. The 1.2MHz to
12MHz range is also accommodated when an external
clock is applied to XT ALl as the frequency source.
Timer/Counter Mode Register
Within the Timer Mode (TMOD) register are the bits that
select which operations each timer/counter will do.
Timer/Counter Control Register
The timer/counters are controlled by the Timer/
Counter Control (TCON) register bits. The start/stop bits
for the timer/counters along with the overflow and interrupt request flags are mapped in TCON.
Timer/Counter 1 (High), Timer/Counter 1 (Low),
Timer/Counter 0 (High), Timer/Counter 0 (Low)
BOOLEAN PROCESSOR
There are four register locations for the two 16-bit timer/
counters. These registers can be read or written to, to give
the programmer easy access to the timer/counters. THI
and THO refer to the 8 high-order bits of timer/counter 1
and 0, respectively. TLl and TLO refer to the low-order
bits of both timer/counter 1 and O.
The Boolean Processor is an integral part of the 8051 's architecture. It is an independent bit processor with its own
instruction set, its own accumulator (the carry register)
and its own bit-addressable RAM and 110. The bit
manipulation instructions allow the Direct Addressing of
128 bits within the Internal Data RAM and 128 bits within
the Special Function Registers as shown in Figures 2-3 and
2-4. The Special Function Registers with an address evenly
divisable by eight (PO, TCON, PI, SCON, P2, lEe, P3,
IPC, PSW, A, and B) contain Directly Addressable bits.
Serial Control Register
This control register (SCON) has bits that enable reception of the serial port. Selecting the operating mode of the
serial port is accomplished with bits in this register also.
2-4
AFN-01739A
FUNCTIONAL DESCRIPTION
A resource requests an interrupt by setting its associated
interrupt request flag in the TCON or SCON register, as
detailed in Table 2-2. The interrupt request will be
acknowledged if its interrupt enable bit in the Interrupt
Enable register (shown in Table 2-3) is set and if it is the
highest priority level as established by the polarity of a bit
in the Interrupt Priority register. These bit assignments
are shown in Table 2-4. Setting the resource's associated
bit to a one (1) programs it to the higher level. The priority
of multiple interrupt requests occurring simultaneously
and assigned to the same priority level is also shown in
Table 2.4.
a.) RAM Bit Addresses.
RAM
BYTE
7FH
1....----------.,1
(MSB)
(lSB)
.
78
2FH
7F
7E
70
7C
7B
7A
79
2EH
77
76
75
74
73
72
71
70
20H
6F
6E
60
6C
6B
6A
69
68
2CH
67
66
65
64
63
62
61
60
2BH
SF
5E
50
5C
5B
SA
59
58
2AH
57
56
55
54
53
52
51
50
29H
4F
4E
40
4C
4B
4A
49
48
28H
47
46
45
44
43
42
41
40
b.) Hardware Register Bit Addresses.
Direct
27H
3F
3E
3D
3C
3B
3A
39
:~~ress
38
Bit Addresses
(lSB)
(MSB)
26H
37
36
35
34
33
32
31
30
OFFH
25H
2F
2E
20
2C
2B
2A
29
28
OFOH
F7
I
F6
I
F5
24H
27
26
25
24
23
22
21
20
23H
1F
1E
10
1C
1B
1A
19
18
OEOH
E7
I
E6
I
E5
22H
17
16
15
14
13
12
11
10
21H
OF
OE
00
OC
OB
OA
09
08
OOOH
07
I
06
I
D5
I
04
I
03
I
02
I
01
20H
07
06
05
04
03
02
01
00
OB8H
- I- I- I
BC
I
BB
I
BA
I
OBOH
B7
I
I
B4
I
B3
I
B2
OA8H
AF
I- I- I
AC
I
AB
I
OAOH
A7
I
A6
I
AS
I
A4
1 I
98H
9F
I
9E
I
90
I
9C
I
9B
90H
97
I
96
I
95
I
94
I
88H
8F
I
8E
I
80
I
8C
80H
87
I
86
I
85
I
84
I
F4
I
F3
I
F2
I
F1
I
1 1 1 1 1
FO
EO
ACC
I
DO
PSW
B9
I
B8
IP
I
B1
I
BO
P3
AA
I
A9
I
A8
IE
A2
I
A1
1
AO
P2
I
9A
I
99
I
98
SCON
93
I
92
I
91
I
90
P1
I
8B
I
8A
I
89
I
88
TCON
I
83
I
82
1 1
80
PO
E4
E3
E1
Hardware
Register
Symbol
E2
1FH
Bank 3
18H
17H
Bank 2
10H
B6
I
B5
OFH
Bank 1
08H
07H
Bank 0
OOH
Figure 2·3. Data RAM Bit Address Space
On any addressable bit, the Boolean processor can perform the bit operations of set, clear, complement, jumpif-set, jump-if-not-set, jump-if-set-then-clear and move
to/from carry. Between any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical and/ or logical or with the result returned to
the carry flag.
A3
81
Figure 2·4. Special Function Register Bit
Address Space
ON·CHIP PERIPHERALS
The second section of Chapter 2 describes the on-chip
peripherals and external memory timing. This section
begins with the interrupt system.
Interrupt System
The servicing of a resource's interrupt request occurs at
the end of the instruction-in-progress. The processor
transfers control to the starting address of this
resource's interrupt service program and begins execution.
Interrupts result in a transfer of control to a new program
location. The program servicing the request begins at this
address. In the 8051 there are five hardware resources that
can generate an interrupt request. The starting address of
the interrupt service program for each interrupt source is
shown in Table 2-1.
Within the Interrupt Enable register (IE) there are six
addressable flags. Five flags enable/disable the five
interrupt sources when set/cleared. Setting/clearing the
sixth flag permits a global enable/disable of each enabled interrupt request.
2-5
AFN·01739A
FUNCTIONAL DESCRIPTION
Setting/ clearing a bit in the Interrupt Priority (IP)
rupt request flags (lEO, lEI, TFO and TFI) are cleared
when the processor transfers control to the first instruction of the interrupt service program. The T! and RI interrupt request flags are the exceptions and must be
cleared as part of the serial port's interrupt service program.
register establishes its associated interrupt request as a
high/low priority. If a low-priority level interrupt is being serviced, a high-priority level interrupt will interrupt
it. However, an interrupt source cannot interrupt a service program of the same or higher level.
The processor records the active priority level(s) by setting internal flip-flop(s). One of these non-addressable
flip-flops is set while a low-level interrupt is being serviced. The other flip-flop is set while the high-level interrupt is being serviced. The appropriate flip-flop is set
when the processor transfers control to the service program. The flip-flop corresponding to the interrupt level
being serviced is reset when the processor executes an
RET! Instruction. To summarize, the sequence of
events for an interrupt is: A resource provokes an interrupt by setting its associated interrupt request bit to let
the processor know an interrupt condition has occurred.
The CPU's internal hardware latches the internal request near the falling-edge of ALE in the tenth, twentysecond, thirty-fourth and forty-sixth oscillator period of
the instruction-in-progress. The interrupt request is conditioned by bits in the interrupt enable and interrupt
priority registers. The processor acknowledges the interrupt by setting one of the two internal "priority-level active" flip-flops and performing a hardware subroutine
call. This call pushes the PC (but not the PSW) onto the
stack and, for most sources, clears the interrupt request
flag. The service program is then executed. Control is
returned to the main program when the RET! instruction is executed. The RETI instruction also clears one of
the internal "priority-level active" flip-flops. Most inter-
Table 2·3. Interrupt Enable Flags
Interrupt Source
External Request 0
Internal Timer / Counter 0
External Request 1
Internal Timer/ Counter 1
Internal Serial Port
Reserved
Reserved
All Enabled
External Request 0
Internal Timer/ Counter 0
External Request I
Internal Timer/ Counter I
Internal Serial Port
Bit
Location
EXO
ETO
EXI
ETI
ES
None
None
EA
IE.O
1E.1
IE. 2
1E.3
lEA
1E.5
1E.6
1E.7
Table 2·4. Interrupt Priority Flags
Priority
Within
Level
Bit
Location
PXO
.0 (highest)
IP.O
PTO
PXI
.1
.2
IP.l
IP.2
Priority
Interrupt Source
Flag
External Request 0
Internal Timer /
Counter 0
External Request 1
Internal Timer /
Counter 1
Internal Serial Port
Reserved
Reserved
Reserved
Table 2·1. Starting Address for Interrupt Service
Programs
Interrupt Source
Enable
Flag
PTl
PS
None
None
None
.3
.4 (lowest)
IP.3
IPA
IP.5
IP.6
IP.7
Starting Address
The process whereby a high-level interrupt request interrupts a low-level interrupt service program is called
nesting. In this case the address of the next instruction in
the low-priority service program is pushed onto the stack,
the stack pointer is incremented by two (2) and processor
control is transferred to the Program Memory location of
the first instruction of the high-level service program. The
last instruction of the high-priority interrupt service program must be an RET! instruction. This instruction clears
the higher "priority-level-active" flip-flop. RET! also
returns processor control to the next instruction of the
low-level interrupt service program. Since the lower
"priority-level-active" flip-flop has remained set, high
priority interrupts are re-enabled while further lowpriority interrupts remain disabled.
3 (0003 H)
11 (OOOB H)
19 (0013 H)
27 (OOIB H)
35 (0023 H)
Table 2·2. Interrupt Request Flags
Interrupt Source
Request
Flag
Bit
Location
External Request 0
Internal Timer/ Counter 0
External Request I
Internal Timer/ Counter I
Internal Serial Port (xmit)
Internal Serial Port (rcvr)
lEO
TFO
lEI
TFI
TI
RI
TCON.I
TCON.S
TCON.3
TCON.7
SCON.I
SCON.O
The highest-priority interrupt request gets serviced at the
,end of the instruction-in-progress unless the request is
2-6
AFN·01739A
FUNCTIONAL DESCRIPTION
made in the last fourteen oscillator periods of the
instruction-in-progress. Under this circumstance, the
next instruction will also execute before the interrupt's
subroutine caIl is made. The first instruction of the service
program will begin execution twenty-four oscillator
periods (the time required for the hardware subroutine
call) after the completion of the instruction-in-progress
or, under the circumstances mentioned earlier, twentyfour oscillator periods after the next instruction.
When ITO and ITI are set to one (1), interrupt requests on
INTO and INTI are transition-activated (high-to-Iow), or
else they are low-level activated. lEO and lEI are the interrupt request flags. These flags are set when their corresponding interrupt request inputs at INTO and INTI,
respectively, are low when sampled by the 8051 and the
transition-activated scheme is selected by ITO and ITI.
When ITO and ITI are programmed for level-activated in~
terrupts, the lEO and lEI flags are not affected by the inputs at INTO and INTI, respectively.
Thus, the greatest delay in response to an interrupt request
is 86 oscillator periods (approximately 7\Jsec @ I2MHz).
Examples of the best and worst case conditions are illustrated in Table 2-5.
Transition·Activated Interrupts
The external interrupt request inputs (INTO and INTI)
can be programmed for high-to-Iow transition-activated
operation. For transition-activated operation, the input
must remain low for greater than twelve oscillator
periods, but need not be synchronous with the oscillator.
It is internally latched by the 8051 near the falling-edge of
ALE during an instruction's tenth, twenty-second, thirtyfourth and forty-sixth oscillator periods and, if the input is
low, lEO and lEI is set. The upward transition of a
transition-activated input may occur at any time after the
twelve oscillator period latching time, but the input must
remain high for twelve oscillator periods before reactivation.
Table 2·5. Best and Worst Case Response to
Interrupt Request
Time
(Oscillator Periods)
Instruction
Best
Case
Worst
Case
1) External interrupt request
generated immediately
before (best) / after (worst)
the pin is sampled. (Time
until end of bus cycle.)
2) Current or next instruction
finishes in 12 oscillator
periods
3) Next instruction is MUL
or DIV
4) Internal latency for hardware subroutine call
2+ E
2-E
12
12
don't
care
24
48
38
86
Level·Activated Interrupts
The external interrupt request inputs (INTO and INTI)
can be programmed for level-activated operation. The input is sampled by the 8051 near the falling-edge of ALE
during the instruction's tenth, twenty-second, thirtyfourth and forty-sixth oscillator periods. If the input is
low during the sampling that occurs fourteen oscillator
periods before the end of the instruction in progress, an interrupt subroutine caIl is made. The level-activated input
need be low only during the sampling that occurs fourteen
oscillator periods before the end of the instruction-inprogress and may remain low during the entire e.xecution
of the service program. However, the input must be raised
before the service program completes to avoid possibly envoking a second interrupt.
24
EXTERNAL INTERRUPTS
The external interrupt request inputs (INTO and INTI)
can be programmed for either transition-activated or
level-activated operation. Control of the external interrupts is provided by the four low-order bits of TCON as
shown in Table 2-6.
Ports and 1/0 Pins
There are 32 110 pins configured as four 8-bit ports. Each
pin can be individually and independently programmed as
input or output and each can be configured dynamically
(Le., on-the-fly) under software control.
Table 2·6. Function of Bits in TCON
(Lower Nibble)
Function
External Interrupt Request Flag I
Input INTI Transition-Activated
External Interrupt Request Flag 0
Input INTO Transition Activated
Flag
Bit
Location
lEI
ITI
lEO
ITO
TCON.3
TCON.2
TCON.I
TCON.O
An instruction that uses a port's bit/byte as a source
operand reads a value that is the logical arid of the last
value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes
that none of the 8051 's electrical specs are being
violated). An instruction that reads a bit/byte, operates
2-7
AFN·01739A
FUNCTIONAL DESCRIPTION
on the content, and writes the result back to the
bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. Pins comprising
a single port can be made a mixed collection of inputs
and outputs by writing a "one" to each pin that is to be
an input. Each time an instruction uses a port as the
destination, the operation must write "ones" to those
bits that correspond to the input pins. An input to a port
pin need not be synchronized to the oscillator. Each
port pin is sampled near the falling-edge of ALE during
the read instruction's tenth or twenty-second oscillator
period. If an input is in transition when it is sampled
near the falling-edge of ALE it will be read as an indeterminate value.
IRE,6.D (READMODIFY-WRITE)
+5V
INTERNAL
BUS
D
FLIP
FLOP
a
CLK
WRITE PULSE
ZERO TO 1
TRANSITION
The instructions that perform a read of, operation on,
and write to a port's bit/byte are INC, DEC, CPL, JBC,
CJNE, DJNZ, ANL, ORL, and XRL. The source read
by these operations is the last value that was written to
the port, without regard to the levels being applied at
the pins. This insures that bits written to a one (1) for
use as inputs are not inadvertently cleared; see Figure
2-5.
READ
(NON READMODIFYWRITE)
Figure 2·6. "Quasi·Bidirectional" Port Structure
In Ports 1, 2 and 3 the output driver provides source
current for two oscillator periods if, and only if, software updates the bit in the output latch from a zero (0)
to a one (1). Sourcing current only on "zero to one"
transition prevents a pin, programmed as an input,
from sourcing current into the external device that is
driving the input pin. The output drivers in Ports 1, 2
and 3 can sink/ source one TTL load.
READ (READMODIFY-WRITE) --~
+5V
INTERNAL
BUS
a
D
a
D
D
FLIP
FLOP
Secondary functions (RD, WR, etc.) can be selected individually and independently for the pins of Port 3.
Port 3 generates these secondary control signals
automatically as long as the pin corresponding to the
appropriate signal is programmed as an input.
1/0
a
PIN
PORT
0
CLK
Accessing External Memory
WRITE PULSE
BUS CYCLE
TIMING
When accessing external memory the 8051 emits the upper address byte from Port 2 and the lower address byte,
as well as the data, from Port O. It uses ALE, PSEN and
two pins from Port 3 (RD ·and WR) for memory control. ALE is used for latching the address into the external memory. The PSEN signal enables the external Program Memory to Port 0, the RD signal enables External
Data Memory to Port 0 and the WR signal latches the
data byte emitted by Port 0 into the External Data
Memory. Externally the PSEN and RD signals can be
combined logically if a contiguous external program
and data memory space (similar to a "von Neuman"
machine) is desired. The P3.7 (RD) and P3.6 (WR) output latches must be programmed to a one (1) if External
Data Memory is to be accessed. When P3.7 and P3.6 are
programmed as RD and WR, respectively, the remain-
READ
(NON READMODIFY-WRITE)
Figure 2·5. "Bidirectional" Port Structure
When used as a port, Port 0 has an open-drain output.
When used as a bus, it has a standard three-state driver.
The Port 0 output driver can sink/source two TTL
loads.
Ports 1, 2 and 3 have quasi-bidirectional output drivers
which incorporate a pull-up resistor of lOK-to-20K
Ohms as shown in Figure 2-6.
2·8
AFN-01739A
FUNCTIONAL DESCRIPTION
ing pins of Port 3 may be individually programmed as
desired. The 8051 can address 64K bytes of external
Program Memory when the EA pin is tied low. When
EA is high, the 8051 fetches instructions from internal
Program Memory when the address is between 0 and
4095, and from external Program Memory when the addressed memory location is between 4096 and 64K. In
either case, Ports 2 and 0 are automatically configured
as an external bus, based on the value of the Pc. Instruction execution times are the same for code fetched
from internal or external Program Memory.
ACCESSING EXTERNAL MEMORY-OPERATION
OF PORTS
The Port 0 bus is time-multiplexed to permit transfer of
both addresses and data. This bus is used directly by
memory and peripheral devices that incorporate on-chip
address latching (MCS-85 memories with peripherals),
or it can be de-multiplexed with an address latch to
generate a non-multiplexed bus (MCS-80 peripherals
and memory). During an external access, the low-order
byte of the address and the data (for a write) is emitted
by the Port 0 output drivers. Ones (l's) are automatically written to Port 0 at the very end of the bus cycle.
Since the Port 0 output latches will contain ones (l's) at
the end of the bus cycle, Port 0 will be in its high impedance state when a bus cycle is not in progress. Port 2
emits the upper 8-bits of the address when a MOVX instruction using DPTR is executed. Port 2's output
drivers provide source current for two oscillator periods
when emitting the address. Port 2's internal pull-up
resistors sustain the high level.
Up to 64K of External Data Memory can be accessed using the MOVX instructions. These instructions
automatically configure Port 0, and often Port 2, as an
external bus. The MOVX instructions use the DPTR,
Rl or RO register as a pointer into the External Data
Memory. The 16-bit DPTR register is used when successive accesses cover a wide range of the 64K space.
The 8-bit Rl and RO registers provide greatest byte efficiency when successive accesses are constrained to a
256-byte block of the External Data Memory space.
When using Rl and RO, a subsequent block can be accessed by updating the output latch of Port 2. Port 2 is
not affected by execution of a MOVX instruction that
uses Rl or RO. If, for example, 32K or less of external
data memory is present, only part of Port 2 needs to be
used for selecting the desired block; the remaining pins
of Port 2 can be used for 110. When a MOVX using
DPTR is executed, the value in Port 2's output latch is
altered only during the external access and then is
returned to its prior value. This permits efficient external block moves by interleaving MOVX instructions
that use DPTR and Rl and RO.
ACCESSING EXTERNAL MEMORY-BUS CYCLE
TIMING
(The following section is a description of the 8051 's timings. For design purposes, please refer to the specification section in Chapter 6 for 8051 timing parameters.)
Each Program Memory bus cycle consists of six
oscillator periods. These are referred to as Tl, T2, T3,
T4, T5 and T6 on Figure 2-7. The address is emitted
from the processor during T3. Data transfer occurs on
the bus during T5, T6, and the following bus cycle's Tl.
When fetching from external Program Memory, the
8051 will always fetch an even number of bytes. If an
odd number of bytes are executed prior to a branch, or
an External Data Memory access, the non-executed byte
will be ignored by the 8051. An even number of idle bus
cycles (each 6 oscillator periods in duration) can occur
between external bus cycles when the processor is fetching from internal Program Memory. The read cycle
begins during T2, with the assertion of address latch
enable signal ALE CD. The falling edge of ALE @ is
used to latch the address information, which is present
on the bus at this time Q), into the 8282 latch if a nonmultiplexed bus is required. At T5, the address is
removed from the Port 0 bus and the processor's bus
drivers go to the high-impedance state ®. The program
memory read control signal (PSEN) ~ is also asserted
during T5. PSEN causes the addressed device to enable
its bus drivers to the now-released bus. At some later
time, valid instruction data will become available on the
bus @. When the 8051 subsequently returns PSEN to
the high level (J), the addressed device will then float its
bus drivers, relinquishing the bus again ®.
The ALE signal is generated every sixth oscillator period
during reads from either internal or external Program
Memory. The PSEN signal is generated every sixth
oscillator period when reading from the external Program Memory. When a read or write from External
Data Memory is being performed, a single ALE and a
RD or a WR signal is generated during a twelve
oscillator period interval. The 8051 always fetches an
even number of bytes from its Program Memory. If an
odd number of bytes are executed prior to a branch or
to an External Data Memory access, the nonexecuted
byte is ignored by the 8051. If an instruction requires
more oscillator periods for its execution than for its
fetch, the first byte of the next instruction is fetched
repeatedly while the first instruction completes execution. If the CPU does not address External Data
Memory, then ALE is generated every sixth oscillator
period and can be used as an external clock. When External Data Memory is present, external logic may be
used to combine the occurrence of RD, WR, and ALE
to generate an external clock with a period equal to six
oscillator periods.
2·9
AFN·01739A
FUNCTIONAL DESCRIPTION
OSC
T3
T2
T1
T12
TS
T4
T7
T6
T8
T9
no
n1
n
T12
T2
ALE
Ro,WR
PORT 2
PORTO
Figure 2·7. Program Memory Read Cycle Timing
ALE
8V
II
\0
II
®
rx
PORT 2
ADDRESS A1S-AS
®
PORTO
011
~0
RD
INST
I~ IFLOAT
I
I
A7- A O
I
8)
1
®
r&l
FLOAT
I
K
DATA IN
I
I
FLOAT
ADD RESS
OR FLOAT
I
Figure 2·8. Data Memory Read Cycle Timing
and T6 is the period during which the direction of the
bus is changed for the r(;!ad operation. The read cycle
begins during T2, with the assertion of address latch
enable signal ALE CD: The falling edge of ALE (2) is
used to latch the address information, which is present
on the bus at this time Q) , into the 8282 latch if a nonmultiplexed bus is required. At T5, the address is
removed from the Port 0 bus and the processor's bus
drivers go to the high-impedance state ®. The data
memory read control signal RD ~, is asserted during
T7. RD causes the addressed device to enable its bus
drivers to the now-released bus. At some later time,
valid data will be available on the bus ®. When the
8051 subsequently returns RD to the high level Q), the
For the MOVe instruction, the op-code is fetched in the
first six-oscillator period, the first byte of the next instruction is fetched during the second six-oscillator
period, the table entry is fetched in a third six-oscillator
period and the first byte of the next instruction is again
fetched in the fourth six-oscillator period.
Each External Data Memory bus cycle consists of twelve
oscillator periods. These are shown as Tl through TI2
on Figure 2-8. The twelve-period External Data
Memory cycle allows the 8051 to use peripherals that are
relatively slower than its program memories. The address is emitted from the processor during T3. Data
transfer occurs on the bus during T7 through T12. T5
2-10
AFN-01739A
FUNCTIONAL DESCRIPTION
addressed device will then float its bus drivers, relinquishing the bus again ® .
Mode 1)
Configures counter 1 as a 16-bit timer/
counter.
The write cycle, like the read cycle, begins with the
assertion of ALE Q) and the emission of an address ~
as shown in Figure 2-9. In T6, the processor emits the
data to be written into the addressed data memory location Q). This data remains valid on the bus until the
end of the following bus cycle's T2 @. The write signal
WR goes low at T6 CI> and remains active through T12
Mode 2)
Configures counter 1 as an 8-bit autoreload timer/counter. THI holds the
reload value. TLl is incremented. The
value in THI is reloaded into TLl when
TLl overflows from all ones (l's). An 8048
compatible counter is achieved by configuring to mode 2 after zeroing THI.
Mode 3)
When counter 1's mode is reprogrammed
to mode 3 (from mode 0, 1 or 2), it disables
the incrementing of the counter. This mode
is provided as an alternative to using the
TRI bit (TCON.6) to start and stop
counter 1.
@.
Timer/Counters
Two independent 16-bit timer/counters are on-board
the 8051 for use in measuring time intervals, measuring
pulse widths, counting events, and causing periodic
(repetitious) interrupts.
The serial port receives a pulse each time that counter 1
overflows. The standard UART modes divide this pulse
rate to generate the transmission rate.
TIMER/COUNTER MODE SELECTION
Counter 1 can be configured in one of four modes:
Counter 0 can also be configured in one of four modes:
Mode 0)
Modes 0-2) Modes 0-2 are the same as for counter 1.
Provides an 8-bit counter with a divideby-32 prescaler or an 8-bit timer with a
divide-by-32 prescaler. A read/write of
THI accesses counter l's bits 12-5. A
read/write of TLI accesses counter l's bits
7-0. TLl bits 4-0 are the prescalar (counter
l's bits 4-0), while bits 7-5 are indeterminate and should be ignored. The programmer should clear the prescaler
(counter 1's bits 4-0) before setting the run
flag.
(i{
ALE
Mode 3)
In Mode 3, the configuration of THO is not
affected by the bits in TMOD or TCON
(see next section). It is configured solely as
an 8-bit timer that is enabled for incrementing by TCON's TRI bit. Upon THO's
overflow, the TFI flag gets set. Thus,
neither TRI nor TFI is available to counter
1 when counter 0 is in Mode 3. The function of TRI can be done by placing counter
I
\
V
®V
1\0
WR
0
~
PORT 2
PORTO
INST
I~ IFLOAT
I
I
ADDRESS A15-AS
CD
G)
(3)
A7- AO
I
X
DATA OUT
I
ADD RESS
OR FLOAT
I
Figure 2·9. Data Memory Write Cycle Timing
2-11
AFN-01739A
FUNCTIONAL DESCRIPTION
Table 2·7. Function of Bits in TCON
(Upper Nibble)
1 in Mode 3, so only the function of TFI is
actually given up by counter 1. In Mode 3,
TLO is configured as an 8-bit timer/counter
and is controlled, as usual, by the Gate
(TMOD.3) clf (TMOD.2), TRO
(TCON.4) and TFO (TCON.5) control bits.
Function
Counter interrupt request and
overflow Flag
Counter enable/disable bit
Counter interrupt request and
overflow Flag
Counter enable/disable bit
CONFIGURING THE TIMER/COUNTER INPUT
The use of the timer/counter is determined by two 8-bit
registers, TMOD (timer mode) and TCON (timer control). The counter input circuitry is shown in Figures
2-10 and 2-11. The input to the counter circuitry is from
an external reference (for use as a counter), or from the
on-chip oscillator (f~ use as a timer), depending on
whether TMOD's CIT bit is set or cleared, respectively.
When used as a time base, the on-chip oscillator frequency is divided by twelve (12) before being input to
the counter circuitry. When TMOD's Gate bit is set (1),
the external reference input (Tl, TO) or the oscillator input is gated to the counter conditional upon a second external input (INTO), (INTI) being high. When the Gate
bit is zero (0), the external reference, or oscillator input,
is unconditionally enabled. In either case, the normal interrupt function of INTO and INTI is not affected by
the counter's operation. If enabled, an interrupt will occur when the input at INTO or INTI is low. The
counters are enabled for incrementing when TCON's
TRI and TRO bits are set. When the counters overflow
the TFI and TFO bits in TCON get set, and interrupt re~
quests are generated. The functions of the bits in TCON
are shown in Table 2-7.
Flag
Bit
Location
TFI
TCON.7
TRI
TFO
TCON.6
TCON.5
TRO
TCON.4
The functions of the bits in TMOD are shown in Table
2-8. Recall that the bits in TMOD are not bit addressable.
Table 2·8. Functions of Bits in TMOD
Function
Flag
Bit
Location
Enable input at TI using INTI
Counter I/Timer I select
C I/T I Mode select MSb
C I/T I Mode select LSb
Enable input to TO using INTO
Gate
MI
MO
Gate
TMOD.7
TMOD.6
TMOD.5
TMOD.4
TMOD.3
Counter 0/ Timer 0 select
C OfT 0 Mode select MSb
C OfT 0 Mode select LSb
CIT
MI
MO
TMOD.2
TMOD.I
TMOD.O
CjT
COUNTER 0
MODE 0: 8-BIT TIMER WITH PRESCALER/
8-BIT COUNTER WITH PRESCALER
MODE 1: 16-BIT TIMER/COUNTER
MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER
MODE 3: 8-BIT TIMER/COUNTER (TLO)
TO---.....I
XTAL1
Figure 2·10. Timer/Event Counter 0 Control and Status Flag Circuitry
2-12
AFN·01739A
FUNCTIONAL DESCRIPTION
PULSE TO
SERIAL PORT
COUNTER 1
MODE 0: 8-BIT TIMER WITH PRESCALER/
8-BIT COUNTER WITH PRESCALER
MODE 1: 16-BIT TIMER/COUNTER
MODE 2: 8-BIT AUTO-RELOAD T/C
MODE 3: PREVENTS INCREMENTING
OFT/C
COUNTER 0
Figure 2·11. Timer/Event Counter 1 Control and Status Flag Circuitry
the time when a toggled input (transition from high to
low) is sampled to the time when the counter is incremented.
OPERATION
The counter circuitry counts up to all 1's and then
overflows to either O's or the reload value. Upon
overflow, TFI or TFO gets set. When an instruction
changes the timer's mode or alters its control bits, the
actual change occurs at the end of the instruction's execution.
Serial Channel
The 8051 has a serial channel useful for serially linking
UART (universal asynchronous receiver/transmitter)
devices and for expanding I/O. This full-duplex serial
I/O port can be programmed to function in one of four
operating modes:
The Tl and TO inputs are sampled near the falling-edge
of ALE in the tenth, twenty-second, thirty-fourth and
forty-sixth oscillator periods of the instruction-inprogress. They are also sampled in the twenty-second
oscillator period of MOVX, despite the absence of
ALE. Thus, an external reference's high and low times
must each be a minimum of twelve oscillator periods in
duration. There is a twelve oscillator period delay from
•
Mode 0)
Synchronous I/O expansion using TTL or
CMOS shift registers
Mode 1)
UART interface with lO-bit frame and
variable transmission rate
•
~
,
•
TXD
RXD
TXD
RXD
TXD
RXD
RXD
r
TXD
TXD
r
RXD
TXD
!
RXD
TXD ~ RXD
RXD
PORT PIN
8051
8051
8051
A. MULTI-80S1 INTERCONNECT -HALF DUPLEX
8051
8051
8051
B. MULTI-80S1 INTERCONNECT -FULL DUPLEX
8051
14f...---...-.
TXD
CTS
8251
C. 8051-8251 INTERFACE
Figure 2·12. UART Interface Technique
2-13
AFN-01739A
FUNCTIONAL DESCRIPTION
Mode 2)
UART interface with ll-bit frame and fixed
transmission rate
Mode 3)
UART interface with II-bit frame and
variable transmission rate
Table 2·9. Functions of Bits in SCON
Function
Serial Port Operation
Mode (MSb)
Serial Port Operation
Mode (LSb)
Conditional Receiver
Enable
Receiver Enable
Transmitter Data Bit 8
Received Data Bit 8
Transmission Complete
Interrupt Flag.
Reception Complete
Interrupt Flag
Modes 2 and 3 also provide automatic wake-up of slave
processors through interrupt driven address-frame
recognition for multiprocessor communications.
Several schemes of UART interfacing are shown in
Figure 2-12, and an I/O expansion technique is shown
in Figure 2-13.
8051
Flag
Bit
Location
SMO
SCON.7
SMI
SCON.6
SM2
SCON.5
REN
TB8
RB8
TI
SCON.4
SCON.3
SCON.2
SCaN. 1
RI
SCaN. 0
DATA
CLOCK
PORT PIN
Mode control bits SMO and SMI program the serial port
in one of four operating modes. A detailed description
of the modes is provided later in the text. The receiverenable bit (REN) resets the receiver's start/stop logic.
When software sets REN to one (1), the receiver's
transmission-rate generator is initialized and reception
is enabled. REN must be set as part of the serial
channel's initialization program. When REN is cleared,
reception is disabled.
A. 1/0 INPUT
EXPANSION
8051
DATA
CLOCK
PORT PIN
OS
EN
B. 1/0 OUTPUT
EXPANSION
The CPU is informed that the transmitter portion of
SBUF is empty, or the receiver portion is full, by TI and
RI, respectively. TI and RI must be cleared as part of
the interrupt service program so as not to continuously
interrupt the CPU. Since TI and RI are "or-ed" together
to generate the serial port's interrupt request, they must
be polled to determine the source of the interrupt.
Figure 2·13. 1/0 Expansion Technique
SERIAL CHANNEL CONTROL AND
DATA REGISTERS
Data for transmission and from reception reside in the
serial port buffer register (SBUF). A write to SBUF updates the transmitter register, while a read from SBUF
reads a buffer that is updated by the receiver register
if/when flag RI is reset. The receiver is double-buffered
to eliminate the overrun that would occur if the CPU
failed to respond to the receiver's interrupt before the
beginning of the next frame. In general, double buffering of the transmitter is not needed for the high performance 8051 to maintain the serial link at its maximum
rate. A minor degradation in data rate can occur in rare
events, such as when the servicing of the transmitter has
to wait for a lengthy interrupt service program to complete. In asynchronous mode, false start-bit rejection is
provided on received frames. A two-out-of-three vote is
taken on each received bit for noise rejection. The serial
port's control and the monitoring of its status is provided by the serial port control register (SCaN). The contents of the 8-bit SCON register are shown in Table 2-9.
OPERATING MODES
Operating Mode 0
The I/O expansion mode, Mode 0, is used to expand the
number of input and output pins. In this mode, a clock
output is provided for synchronizing the shifting of bits
into, or from, an external register. Eight bits will be
shifted out each time a data byte is written to the serial
channel's data buffer (SBUF), even if TI is set. Each
time software clears the RI flag, eight bits are shifted into SBUF before the RI flag is again set. The receiver
must be enabled [Le., REN set to (1)] for reception to
occur.
The synchronizing clock is output on pin P3.1 and toggles from high to low near the falling-edge of ALE in
the fifteenth oscillator period following execution of the
2-14
AFN·01739A
FUNCTIONAL DESCRIPTION
instruction that updated SBUF or cleared the RI flag. It
then toggles near the falling-edge of ALE in each subsequent sixth oscillator period until S-bits are transferred.
The eighth rising-edge of clock (P3.1) sets the RI or TI
flag. At this point, shifting is complete and the clock is
once again high. The first bit is shifted out of P3.0 at the
beginning of the eighteenth oscillator period, following
the instruction that updated SBUF. The first bit shifted
in from P3.0 is latched by the clock's rising-edge in the
twenty- fourth oscillator period, following the instruction that cleared the RI flag. One bit is shifted every
twelfth oscillator period, until all eight bits have been
shifted.
In Modes 2 and 3, if SM2 is set, frames are received, but
an interrupt request is generated only when the received
data bit S (RBS) is a one (1). This feature permits interrupt generated wake-up during interprocessor communications when multiple S051's are connected to a
serial bus. Thus, data bit S (RBS) awakens all processors
on the serial bus only when the master is changing address to a different processor. Each processor not addressed then ignores the subsequent transmission of
control information and data. A protocol for
multi-S051 serial communications is shown in Figure
2-14. The SM2 bit has no effect in Modes 0 and l.
Operating Modes 1 through 3
1.
In the UART Modes (i.e., 1 through 3), the transmission rate is subdivided into 16 "ticks." The value of a
received bit is determined by taking a majority vote
after it has been sampled during the seventh, eighth and
ninth "ticks." If two or three ones (1 's) are detected, the
bit will be given a one (1) value; if two or three zeros
(O's) are detected, the bit will be given a zero (0) value.
2.
3.
Until a start bit arrives, the receiver samples the RXD
input pin (P3.0) every "tick." Approximately one-half
bit time (eight "ticks") after the start bit is detected (i.e.,
a low input level was sampled on "tick" one), the serial
port checks its validity (majority vote from "ticks"
seven, eight and nine) and accepts or rejects it. This provides rejection of false start bits.
4.
5.
The contents of the receiver's input shift register is moved to SBUF and RBS (Modes 2 and 3), and RI is set
when a frame's ninth (Mode 1) or tenth (Modes 2 and 3)
bit is received. Upon reception of a second frame's ninth
or tenth bit, the data bits in the shift register are again
transferred to SBUF and RBS, but only if software has
reset the RI flag. If RI has not been reset, then overrun
will occur, since the shift register will continue to accept
bits. Double buffering the receiver provides the CPU
with one frame-time in which to empty the SBUF and
RBS registers. The RI flag is set and bit RBS is loaded
during the ninth "tick" of the received frame's ninth or
tenth bit. The serial port begins looking for the next
start bit approximately one-half bit time after the center
of a stop bit is received.
The hardware in each slave's serial port
begins by listening for an address. Receipt of
an address frame wi" force an interrupt if the
slave's 5M2 bit is set to one (1) to enable "in·
terrupt on address frame only".
The master then transmits a frame containing
the 8·bit address of the slave that is to receive
the subsequent commands and data. A
transmitted address frame has its ninth data
bit (TB8) set equal to one (1).
When the address frame is received, each
slave's serial port interrupts its CPU. The CPU
then compares the address sent to its own.
The 8051 slave which has been addressed
then resets its 5M2 bit to zero (0) to receive a"
subsequent transmissions. A" other 8051's
leave their 5M2 bits at a one (1) to ignore
transmissions until a new address arrives.
The master device then sends control informa·
tion and data, which in turn is accepted by the
previously addressed 8051 [i.e., the one that
had set its 5M2 bit to zero (0)].
Figure 2·14. Protocol for Multi·Processor
Communications
THE SERIAL FRAME
A frame is a string of bits. The frame transmitted and
received in Mode 0 is S bits in length. The data bits of
the frame are transmitted SBUF.O first and SBUF.7
last.
The frame transmitted and received in Mode 1 is ten bits
in length. The frame transmitted and received in Modes
2 and 3 is eleven bits in length. These frames consist of
one start bit, eight or nine data bits and a stop bit. Data
bits 0-7 are loaded into SBUF.0-SBUF.7, respectively,
and data bit S into RBS (receive) or TBS (transmit).
With nominal software overhead, the last data bit can
be made a parity bit, as shown in Figure 2-15.
Data is transmitted from the TXD output pin (P3.1)
each time a byte is written to SBUF, even if TI is set.
Transmission of the start bit begins at the end of the instruction that updates SBUF. TI is set at the beginning
of the transmitted tenth (Mode 1) or eleventh (Mode 2
or 3) bit. After TI becomes set, if SBUF is written-to
prior to the end of the stop (tenth or eleventh) bit, the
transmission of the next frame's start bit will not begin
until the end of the stop bit.
Figure 2-16 shows some typical frame formats' for different applications. The data bits of the frame are
transmitted least significant bit first (SBUF.O) and TBS
last.
2-15
AFN·01739A
FUNCTIONAL DESCRIPTION
First, the 8051 's serial channel provides no indication
that a valid stop bit has been received. However, since a
start bit is detected as a high-level to low-level transition, the UART will not receive additional frames if a
stop bit is not received. Second, the RI flag is set and
SBUF and RB8 are loaded from the receiver's input shift
register when the received last data bit (Le., ninth or
tenth received bit) is sampled. As long as RI is set, the
loading of SBUF, the updating of RB8, and the generation of further receiver interrupts is inhibited. Thus,
overrun will occur if the programmer does not reset RI
before reception of the next frame's last data bit, since
the receiver's input shift register will shift in a third
frame.
MOV C, P
; Parity moved to carry (byte
already in A).
MOV TB8, C ; Put carry into Transmitter Bit 8
MOV SBUF, A; Load Transmit Register
Figure 2·15. Generating Parity and Transmitting
Frame
110 BAUD TTY
I
I
START DATA.O
I 1·21 .31 .41 .Sl .61
.1
PARITY
TYPICAL ASCII TERMINAL
I
I
I
START
I
DATA .0
I I I I I .S I I
.1
.2
.3
.4
.6
PARITY
I
STOP
I
I
STOP
I
OR
I .01 I .21 .31 .41 .Sl .61.71
START DATA
I
PARITY
.1
I
STOP
OR
START DATA.O
I I .21 .31 .4 I .SI .6 1·7 I I
.1
.8
STOP
STOP
I
I
Processor Reset and Initialization
Processor initialization is accomplished with activation
of the RST/VPD pin. To reset the processor, this pin
should be held high for at least twenty-four oscillator
periods. Upon powering up, RST/VPD should be held
high for at least 24 oscillator periods, after the power
supply stabilizes, to allow the oscillator to stabilize.
Crystal operation below 6MHz will increase the time
necessary to hold RST IVPD high. 24 oscillator periods
after receipt of RST, the processor ceases instruction execution and remains dormant for the duration of the
pulse. The low-going transition then initiates a sequence
which requires approximately twelve oscillator periods
to execute before ALE is generated and normal operation commences with the instruction at absolute location OOOOH. Program Memory locations OOOOH through
0003H are reserved for the initialization routine of the
microcomputer. This sequence ends with registers initialized as shown in Table 2-10.
I
Figure 2·16. Typical Frame Formats
TRANSMISSION RATE GENERATION
The proper timing for the serial I/O data is provided by
a transmission-rate generator. On-board the 8051, three
different methods of transmission rate generation are
provided. The transmission-rate achievable is dependent
upon the operating mode of the serial port.
In the I/O expansion mode (Mode 0) the oscillator frequency is simply divided by 12 to generate the transmission rate. This produces a transmission rate of 1M bits
per second at 12MHz. If Modes 1 or 3 are being used,
the transmission rate can be generated from the
oscillator frequency or from an external reference frequency. In these modes, either one-twelfth the oscillator
frequency, or the T1 input frequency, is divided by
256-minus-the-value-in-THI (counter 1 must be configured in auto-reload mode by software) and then
divided by 32 to generate the transmission rate. When
the oscillator frequency input (rather than Tl) is
selected, this method produces a transmission rate of
122 to 31,250 bits per second (including start and stop
bits) at 12MHz. The Tl external input is selected by setting the CIT bit to one (1). When Mode 2 is used, the
oscillator frequency is simply divided by 64 to generate
the transmission rate. This produces a transmission rate
of 187,500 bits per second (including start and stop bits)
at 12MHz.
Table 2·10. Register Initialization
Register
Content
PC
SP
PSW, DPH, DPL, A, B.
IP, IE, SCON, TCON,
TMOD, THI, THO,
TLl, TLO
IP
IE
SBUF
Port 3-PQrt 0
OOOOH
07H
OOH
OOH
DOH
OOH
EOH
60H
Indeterminate
FFH (configures all I/O
pins as inputs)
Unchanged if VPD
applied; else
indeterminate
Internal RAM
UART ERROR CONDITIONS
There are two UART error conditions that should be accounted for when designing systems that use the serial
channel.
2-16
AFN·01739A
FUNCTIONAL DESCRIPTION
In addition, certain of the control pins are driven to a
high level during reset. These are ALE/PROG and
PSEN. Thus, no ALE or PSEN signals are generated
while RST /VPD is high. After the processor is reset, all
ports are written with one (I's). Outputs are undefined
until the reset period is complete. An external reset circuit, such as that in Figure 2-17, can be used to reset the
microcomputer.
supply to RST /VPD pin. Applying power to the
RST /VPD pin resets the 8051 and retains the internal
RAM data valid as the vee power supply falls below
limit. Normal operation resumes when RST /VPD is
returned low. Figure 2-18 shows the waveforms for the
power-down sequence.
,i'--...---/'TI---,
I
'
vee - - - - - - - -....
INTO - - - - - - - "
(POWER-FAIL)
INL.T=ER-=-R-UP=T-J-,_ _ _ _
+5V
I
I
I
I
RST/VPD - - - - - - - - - '
8051
....
RSTNPD
-----~.~I~
NORMAL OPERATION SERVICE PROGRAM
!
EPROM Programming
The 8751 is programmed, and the 8051 and 8751 are
verified, using the UPP-851 programming card. For
programming and verification, address is input on Port
1 and Port pins 2.0-2.3. Pins P2,4 and P2.5 are held to a
TTL low (VIU. Data is input and output through Port
O. RST /VPD is held at a TTL high level (VIHO and
PSEN is held at TTL low level (VIU during program
and verify. To program, ALE/PROG is held at a TTL
low level (VIU. The programming supply voltage is
held at 21 V. The EA/VDD pin receives this programming supply voltage. ALE/PROG is held at TTL high
level (VIH) to verify the program. Port pin 2.7 forces
the Port 0 output drivers to the high impedance state
when held at a TTL high level and is held at a TTL low
level for verification. Erasure of an 8751 will leave the
EPROM programmed to an all one's (I's) state.
8051
RSTNPD
t
NORMAL OPERATION
Figure 2·18. Power· Down Sequence
+5V
L~
..L...\- - - -
,
~
\7
Figure 2·17. External Reset
Power Down (Standby) Operation of
Internal RAM
Data can be maintained valid in the Internal Data RAM
while the remainder of the 8051 is powered down. When
powered down, the 8051 consumes about 10070 of its
normal operating power. During normal operation,
both the epu and the internal RAM derive their power
from vee. However, the internal RAM will derive its
power from RST /VPD when the voltage of vee is
zero.
Data is introduced by programming "O's" into the
desired bit locations. Although only "O's" will be programmed, both "1's" and "O's" can be presented in the
d-ata word. The only way to change a "0" to a "1" is by
ultra-violet light erasure.
When a power-supply failure is imminent, the user's
system generates a "power-failure" signal to interrupt
the processor via INTO or INTI. This power-failure
signal must be early enough to allow the 8051 to save all
data that is relevant for recovery before vee falls
below its operating limit. The program servicing the
power-failure interrupt request may save any important
data and machine status into the Internal Data RAM.
The service program must also enable the backup power
When EA/VDD is at 21 V, the 8751 is in the programming mode. It is necessary to put a capacitor between
EA/VDD and ground to block spurious voltage transients. ALE/PROG receives the 50 msec, active low TTL
program pulse when the address and data are stable. A
program pulse must be applied at each address location
to be programmed. You can program any location at
any time - either sequentially or at random.
2-17
AFN-01739A
FUNCTIONAL DESCRIPTION
A verify may be performed on the programmed bits to
ensure correct programming. Data is output on Port 0
when pin 2.7 is at a TTL low level (VIH). Pull-up
resistors must be provided on Port 0 pins during
verification. This verification mode can also be used to
check the 8051 's ROM pattern.
Table 2-11 describes the levels needed on the pins to program and verify the 8751.
Table 2·11. Voltage Inputs for EPROM ProgrammingNerifying
~
VPD/RST
PSEN
PROG/ALE
PROGRAM
VERIFY
VIHI
VIHI
VIL
VIL
VIH
Vpp
VIL
VIL
VIL
Vee
VIL
VIL (enable)
VIH (disable)
MODE
2-18
VDD/EA
P27
P24-26
AFN-01739A
I
i~
II
'II'
II
CHAPTER 3
MEMORY ORGANIZATION, ADDRESSING MODES
AND INSTRUCTION SET
Chapter 3 is divided into these categories:
•
Memory Organization
•
Addressing Modes
•
Instruction Set
In the 8051 and 8751, the lower 4K of the 64K Program
Memory address space is filled by internal ROM and
EPROM, respectively. By tying the EA pin high, the
processor can be forced to fetch from the internal
ROM/EPROM for Program Memory addresses 0
through 4K. Bus expansion for accessing Program
Memory beyond 4K is automatic, since external instruction fetches occur automatically when the Program
Counter increases above 4095. If the EA pin is tied low,
all Program Memory fetches are from external memory.
The execution speed of the 8051 is the same, regardless
of whether fetches are from internal or external Program Memory. If all program storage is on-chip, byte
location 4095 should be left vacant to prevent an
undesired pre-fetch from external Program Memory address 4096.
The first part, Memory Organization, describes the
memory spaces of the 8051. The Addressing Modes section describes addressing techniques used to reach the
memory spaces. The final section explains the instruction
set, including functional groupings, opcodes and a software example.
MEMORY ORGANIZATION
In the 8051 family the memory is organized over three
address spaces and the program counter. The memory
spaces shown in Figure 3-1 are the:
•
16-bit Program Counter
•
64K-byte Program Memory address space
•
64K-byte External Data Memory address space
•
384-byte Internal Data Memory address space
Certain locations in Program Memory are reserved for
specific programs. Locations 0000 through 0002 are
reserved for the initialization program. Following reset,
the CPU always begins execution at location 0000.
Locations 0003 through 0042 are reserved for the five
interrupt-request service programs.
The 64K-byte External Data Memory address space is
automatically accessed when the MOVX instruction is
executed.
The 16-bit Program Counter register provides the 8051
with its 64K addressing capabilities. The Program
Counter allows the user to execute calls and branches to
any locations within the Program Memory space. There
are no instructions that permit program execution to
move from the Program Memory space to any of the
data memory spaces.
!
Functionally, the Internal Data Memory is the most
flexible of the address spaces. The Internal Data
Memory space is subdivided into a 256-byte Internal
Data RAM address space and a 128-byte Special Function Register address space. Within these address spaces
are 256 individually addressable bits. Figure 3-2 shows
the locations of the address spaces.
64K
64K
EXTE1RNAL
OVERLAPPED SPACE
409S
INTERNAL
t
I
'___
____L-___ ~~-------~-
PROGRAM
COUNTER
-------Lml,----A--2S-S-----~Il
I
0:.'-_ _ _....
12:1
12810..-----'
~----~,~-===:==~------_~
PROGRAM
MEMORY
INTERNAL
DATA RAM
SPECIAL
FUNCTION
REGISTERS
0
,10..-____--',
EXTERNAL
DATA
MEMORY
INTERNAL DATA MEMORY
Figure 3-1. 8051 Family Memory Organization
3-1
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
The Internal Data RA~,,1 address space is 0 to 255. Four
banks of eight registers occupy locations 0 through 31.
The stack can be located anywhere in the Internal Data
RAM address space. In addition, 128 bit locations of
the on-chip RAM are accessible through Direct Addressing. (See next section, Addressing Modes.) These
bits reside in Internal Data RAM at byte locations 32
through 47, as shown in Figure 3-3. Currently locations
o through 127 of the Internal Data RAM address space
are filled with on-chip RAM. Locations 128 through 255
may be filled on later products without affecting existing software.
thf?m to he accessed as easily as internal RAM. As such,
they can be operated on by most instructions. In addition, 128 bit locations within the Special Function
Register address space can be accessed using Direct Addressing as shown in Figure 3-4. These bits reside in the
Special Function Register address space and can be accessed using Direct Addressing. The addressable bits are
located at byte addresses divisible by eight. An easy way
to determine which byte locations are bit addressable
are those byte locations ending in zero (0) or eight (8)
when represented in hexadecimal notation. The twenty
Special Function Registers are listed in Table 3-1. Their
mapping in the Special Function Register address space
is shown in Figure 3-5.
The stack depth is limited only by the available Internal
Data RAM, thanks to an 8-bit reload able Stack Pointer.
The stack is used for storing the Program Counter during subroutine calls, and may be used for passing
parameters. Any byte of Internal Data RAM or Special
Function Register'S accessible through Direct Addressing can be pushed/popped.
ADDRESSING MODES
Since the MCS-51 architecture differentiates between
Data Memory and Program Memory, there are different addressing modes for each. These are explained
below.
The Special Function Register address space is 128 to
255. All registers except the Program Counter and the
four banks of eight working registers reside here.
Memory mapping the Special Function Registers allows
a,) RAM Bit Addresses,
RAM
BYTE
7FH
-
SPECIAL
FUNCTION
REGISTERS
INTERNAL DATA RAM
( _ _A - - _ V_ _~
255
(lSB)
(MSB)
l~-------'l
255
255
248 F8H'
FOH
2FH
7F
7E
70
7C
7B
7A
79
78
47
2EH
77
76
75
74
73
72
71
70
46
2DH
6F
6E
60
6C
6B
6A
69
68
45
2CH
67
66
65
64
63
62
61
60
44
2BH
SF
5E
50
5C
5B
SA
59
58
43
2AH
57
56
55
54
53
52
51
50
42
29H
4F
4E
40
4C
4B
4A
49
48
41
28H
47
46
45
44
43
42
41
40
40
E8H
EOH
D8H
DOH
C8H
COH
B8H
BOH
ADDRESSABLE
BITS IN
SFRs
(128 BITS)
A8H
27H
3F
3E
3D
3C
3B
3A
39
38
39
26H
37
36
35
34
33
32
31
30
38
25H
2F
2E
20
2C
2B
2A
29
28
37
24H
27
26
25
24
23
22
21
20
36
23H
1F
1E
10
1C
1B
1A
19
18
35
22H
17
16
15
14
13
12
11
10
34
21H
OF
DE
00
DC
DB
OA
09
08
33
20H
07
06
05
04
03
02
01
00
32
AOH
98H
90H
128
135
...127....:::.-
128
ADORE SSABLE
BITS IN
RAM
(128BIT S)
48
127
;>E.
24
7
R7
RO
R7
REGISTE RS -<
88H
128 80H
16
RO
R7
.!..
-'!..
RO
R7
RO
120
31
0
lFH
BANK 3
24
18H
23
17H
BANK 2
Bank 2
10H
BANK 1
16
15
OFH
Bank 1
BANKO
08H
07H
~
INTERNAL
DATA RAM
Bank 3
Bank 0
SPECIAL FUNCTION
REGISTERS
DOH
Figure 3·2. Internal Data Memory Address Space
Figure 3·3. RAM Bit Addresses
3-2
AFN-01739A ,
MEMORY, ADDRESSING, INSTRUCTION SET
There are five general addressing modes operating on
bytes. One of these five addressing modes, however,
operates on both bytes and bits.
is appended to the instruction opcode to provide the
memory location address. The highest-order bit of this
byte selects one of two groups of addresses: values between 0 and 127 (00H-7FH) access internal RAM locations, while values between 128 and 255 (80H-OFFH) access one of the Special Function Registers. In the
assembly language, direct addresses are specified with
the address of the variable or register, or a symbolic
name defined earlier as a direct address. The instruction
set mnemonic for Direct Byte Addressing is "direct".
Register Addressing
Register addressing encodes, in the low-order three bits
of the instruction opcode, the number of a register in
the currently enabled register bank. RSI (PSW.4) and
RSO (PSW.3) determine which register bank is enabled.
In the MCS-51 assembly language, register addressing is
indicated by the register symbols RO through R7, or by a
symbolic name defined earlier as a register. The instruction set mnemonic for Register Addressing is "Rn"
where n can be any value from 0 to 7.
BIT OPERANDS
Direct Bit addressing (bit) lets a number of instructions
manipulate or test any of 128 user-defined software
flags in internal data RAM, and manipulate or test 128
bits in the Special Functions Registers address space. An
additional byte appended to the opcode specifies the
flag or bit to be accessed. Values between 0 and 127
(00H-7FH) correspond to software flags in sixteen internal RAM locations, addresses 20H-2FH. Bit addresses
00H-07H correspond to bits 0-7 of RAM location 20H,
respectively; addresses 77H-7FH correspond to bits 0-7
of RAM location 2FH. Bit address values between 128
Direct Addressing
BYTE OPERANDS
Direct Byte addressing specifies an on-chip RAM location or a Special Function Register. An additional byte
Table 3·1. Special Function Registers
~pecial
Function
Register
ASM·51
Byte
Location
in Memory
b.) Hardware Register Bit Addresses.
Direct
Symbolic Name
Accumulator*
Arithmetic B register*
Registers
Program Status
Word*
Pointers
Parallel
I/O
Ports
Interrupt
System
Timers
Serial I/O
Channel
Stack Pointer
Data Pointer
(high)
Data Pointer
(low)
ACC
B
PSW
224(EOH)
240(FOH)
208(DOH)
SP
DPH
129(8IH)
131(83H)
DPL
130(82H)
P3
P2
PI
PO
I 76(BOH)
160(AOH)
I 44(90H)
128(80H)
IPC
184(B8H)
IEC
168(A8H)
Timer Mode
Timer Control*
Timer I (high)
Timer I (low)
Timer 0 (high)
Timer 0 (low)
TMOD
TCON
THI
THO
THO
TLO
137(89H)
136(88H)
141(8DH)
139(8BH)
140(8CH)
138(8AH)
Serial Control*
Serial Data
Buffer
SCON
SBUF
152(98H)
153(99H)
Port
Port
Port
Port
3*
2*
1*
0*
Interrupt Priority
Control*
Interrupt Enable
Control*
Bit Addresses
Hardware
Register
Symbol
!~:ress
(MSB)
240
F7
I
F6
I
F5
I
F4
I
F3
I
F2
I
F1
I
FO
224
E7
I
E6
I
E5
I
E4
I
E3
I
E2
I
E1
I
EO
ACC
208
07
I
06
I
05
I
04
I
03
I
02
I
01
I
DO
PSW
184
- I- I- I
BC
I
BB
I
BA
I
B9
I
B8
IP
176
B7
I
I
B4
I
B3
I
B2
I
B1
I
BO
P3
168
AF
I- I- I
AC
I
AB
I
AA
I
A9
I
A8
IE
160
A7
I
A6
I
A5
I
A4
I
A3.
I
A2
I
A1
I
AO
P2
152
9F
I
9E
I
90
I
9C
I
9B
I
9A
I
99
I
98
SCON
144
97
I
96
I
95
I
94
I
93
I
92
I
91
1
90
P1
136
8F
I
8E
I
80
I
8C
I
8B
I
8A
I
89
I
88
TCON
128
87
I
86
I
85
I
84
I
83
I
82
I
81
I
80
PO
(lSB)
B6
I
B5
Figure 3·4. Special Function Register Bit Address
*Bit addressable byte location
3·3
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
SYMBOLIC
ADDRESS
224
(EOH)
contents of RO or Rl, according to bit 0 of the instruction opcode. In the 8051 assembly language, indirect addressing is represented by a commercial "at" sign ("@")
preceding RO, Rl, or a symbol defined by the user to be
equal to RO or Rl. The instruction set mnemonic for
Register-Indirect Addressing uses the "at" ("@") also.
208
(DOH)
Immediate Addressing
184
(B8H)
176
(BOH)
168
(A8H)
1~
(AOH)
BYTE
ADDRESS
BIT ADDRESS
,-"--,~~
BF
ACC
231
PSW
1
215
IPC
P3
1I
1
1
A
~l~
224
208
184
191
183
IEC
B
176
175
~
'BU' !'"
SCON
1
159
P1
168
I
I
1
1
I
'" II'"
152
(99H)
152
(98H)
144
(90H)
m'~'"
THO
(FOH)
140
(8DH)
TL1
139
(8BH)
138
(8AH)
TMOD
TCON
1U
136
(88H)
DPL
SP
~
§
135
SFR's
CONTAINING
DIRECT
ADDRESSABLE
BITS
(8CH)
TLO
DPH
Immediate Addressing (#data) appends an additional
byte to the instruction to hold the source variable. In the
8051 assembly language and the 8051 instruction set, a
number sign (#) precedes the value to be used, which
may refer to a constant, an expression, or a symbolic
name. Since the value used is fixed at the time of ROM
manufacture or EPROM programming, it may not be
altered during program execution. (A special case of immediate addressing exists for the instruction MOV
DPTR, #dataI6. Two bytes following the opcode hold
the 16 bits of data loaded into the data pointer.)
Figure 3-6 illustrates how the addressing modes reach
different Internal Data Memory.
(89H)
131
(83H)
130
(82H)
129
(81H)
1U
(80H)
SPECIAL
FUNCTION
REGISTERS
INTERNAL
DATA RAMI
STACK
~r-~
128
255 255
248
240
232
224
216
255
Figure 3·5. Special Function Registers Address
Space
248 F8H
FOH
E8H
EOH
D8H
DOH
208
C8H
200
192
and 255 (80H-OFFH) select bits in the special function
registers; the high-order five-bit field of the address byte
is the same as that of the register used, while the low
or&'r three bits give the bit position within that register.
The assembly language allows three representations for
a direct bit address: by the bit's sequential number
(0-255), by specifying the register or RAM location
which contains the bit, and the bit's position therein
(e.g., 32.6), separated by a period (.) or by a symbol
previously defined as a direct bit address. The instruction set signifies a bit location by the mnemonic "bit".
COH
184
176
168
160
B8H
152
144
98H
BOH
DIRECT
AD~RESS-
ING
(BITS)
A8H
AOH
90H
136
88H
128 135
128 80H
.....~
~
DIRECT
ADDRESSING
(BITS)
>
Base·Register·Plus Index Register·
Indirect Addressing
Base-Register-plus Index Register-Indirect Addressing
simplifies accessing look-up tables (LUT) resident in
Program Memory. A byte may be accessed from an
LUT via an indirect move from a location whose address is the sum of a base register (the DPTR or PC) and
the index register (A).
REGISTER
ADDRESSING
E
127
7
R7
120
0
..?!
RO
R7
~
RO
R7
~ RO
R7
~ RO
BANK 3
BANK2
BANK 1
BANKO
~
~
DIRECT ADDRESSING
STACK-POINTER REGISTER-INDIRECT AND
REGISTER-INDIRECT ADDRESSING
Register·lndirect Addressing
Figure 3·6. Internal Data Memory Addressing
Modes
Register-Indirect Addressing (@Ri) accesses a RAM
location whose address is determined by the current
3-4
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Branch Destination Addressing Modes
If both accumulators are accessed as memory locations
Three program memory addressing modes are used by
conditional and unconditional branch operations.
using Direct Addressing, different mnemonics are used.
"ACC" is the symbol for the byte accumulator and
"CY" is the symbol for the bit accumulator.
RELATIVE ADDRESSING (rei)
Even though there are two different addressing modes
and a set of mnemonics for each accumulator, both accumulators have only one physical space on the chip.
Relative addressing (reI) encodes an 8-bit signed
displacement value in the last instruction byte. During
execution, the CPU computes the destination address by
extending the sign-bit of this byte to 16 bits and adding
this value to the incremented program counter. In the
8051 assembly language, the programmer only needs to
specify the address or label assigned to the desired
destination instruction. The assembler will compute the
signed displacement needed and produce an error
message if the destination is "out of range."
When an I/O port or pin is the destination of a data
move instruction, data is written into a corresponding
data latch. When an I/O port or pin is the source for a
data transfer, or other two operand instructions, the
data present at the input pins is read.
Instructions which use the port as both a source and
destination (such as INC PI or ORL PI, #20H) read the
internal buffer rather than the input pins, so only the
desired output latch bits will be affected.
ABSOLUTE ADDRESSING (addr11)
Absolute Addressing (addr11) encodes the low-order 11
bits of the destination address in three bits of the opcode
and the second instruction byte. The high-order five bits
of the destination address are taken from the high-order
five bits of the incremented program counter. Note that
this means that an AJMP or ACALL instruction
located in addresses 07FEH, for example, will reach a
destination between addresses 0800H and OFFFH.
When an I/O pin is the destination of a SETB, CLR,
CPL, or MOV instruction, the on-chip data latch corresponding to that pin is affected. When an I/O pin is
the source operand for a Boolean move or two-operand
instruction, the instruction reads the data present at the
input pin. The CPL and JBC instructions read the internal buffer rather than the input pin state.
LONG ADDRESSING (addr16)
Since the parity flag (pSW.O) is updated after every instruction cycle, instructions which explicitly alter the
PSW or this bit will have no apparent effect on P, as if
PSW.O is a read-only bit. Bits 7, 6, and 5 of register
IPC, and bits 6 and 5 of register IEC are not implemented on the 8051 and are reserved.
Long Addressing (addr16) uses the second and third
byte of the instruction to hold the high-order and loworder bytes of the 16-bit destination address, respectively. The destination can be anywhere in the full 64
kilobyte program memory address space.
In the MCS-51 assembly language, only the address or
label of the destination instruction is given in each case.
The assembler computes the address encoding needed
by the operation mnemonic and produces an error
message if the destination is "out of range."
INSTRUCTION SET OVERVIEW
The MCS-51 instruction set includes 51 fundamental
operations broken into five functional groupings. Combining them with various addressing modes for Boolean
(I-bit), nibble (4-bit), byte (8-bit), and address (I6-bit)
data types produces the III instructions listed in Table
3-2.
Special Addressing Considerations
If an indirect on-chip RAM or stack address is greater
than the amount of RAM provided (e.g., greater than
127 on the 8051), or if no special function register corresponds to a direct byte or bit address, then the result
of the instruction is undefined.
Each assembly language instruction consists of an
operation mnemonic and (depending on the operation)
up to four operands. The mnemonic abbreviates the
basic function or operation to be performed, while the
operands, separated by commas, clarify which variables
are involved, what data to use, or what instruction to
execute next. Instructions which need two data
operands always specify the destination first, followed
by the source variable, except for the move operation
between two Directly addressable bytes. In this case the
source operand is first and the destination operand is
second.
Note also that the two accumulators, the byte accumulator and the bit accumulator, (the Boolean Processor) can be addressed in two ways using different
ASM-51 mnemonics.
When using Register Addressing, the byte accumulator
may be reached using the "A" mnemonic, while the bit
accumulator may be reached using the "c" mnemonic.
3-5
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
iable 3·2. 8051 InstiUction Set Summary
Interrupt Response Time: To finish execution of current instruction, respond to the interrupt request, push the PC
and to vector to the first instruction of the interrupt service
program requires 38 to 81 oscillator periods (3 to 7,.,.s @ 12
MHz).
Notes on instruction set and addressing modes:
Rn
- Register R7-RO of the currently selec.ted
Register Bank.
data
- 8-bit internal data location's address. This
could be an Internal Data RAM location
(0-127) or a SFR [i.e. 110 port, control
register, status register, etc. (128-255)].
@Ri
- 8-bit internal data RAM location (0-255) addressed indirectly through register RI or RO.
#data
- 8-bit constant included in instruction.
#data 16 -16-bit constant included in instruction
addrl6
-16-bit destination address. Used by LCALL &
LJMP. A branch can be anywhere within the
64K-byte Program Memory address space.
addrll
-II-bit destination address. Used by ACALL &
AJMP. The branch will be within the same
2K-byte page of program memory as the first
byte of the following instruction.
reI
- Signed (two's complement) 8-bit offset byte.
Used by SJMP and all conditional jumps.
Range is -128 to + 127 bytes relative to first
byte of the following instruction.
bit
- Direct Addressed bit in Internal Data RAM or
Special Function Register.
- New operation not provided by 8048/8049.
INSTRUCTIONS THAT AFFECT FLAG SETTINGS'
INSTRUCTION
ADD
ADDC
SUBB
MUL
FLAG
COY AC
X X X
X X X
X X X
o X
DIY
o
DA
RRC
RLC
SETB C
X
X
X
X
INSTRUCTION
CLR C
CPL C
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,bit
MOY C,bit
CJNE
FLAG
COY AC
o
X
X
X
X
X
X
X
I
'Note that operations on SFR byte address 208 or bit addresses 209-215 (i.e. the PSW or bits in the PSW) will also
affect flag settings.
ARITHMETIC OPERATIONS Cont.
ARITHMETIC OPERATIONS
ADD
Mnemonic
A,Rn
ADD
A,direct
ADD
A,@Ri
ADD
A,#data
ADDC
A,Rn
ADDC
A,direct
ADDC
ADDC
SUBB
A,@Ri
A,#data
A,Rn
Byte
Description
Add register to
I
Accumulator
Add direct
2
byte to
Accumulator
Add indirect
Ram to
Accumulator
Add immediate 2
data to
Accumulator
Add register to
Accumulator
with Carry
Add direct
2
byte to
Accumulator
with Carry
Add indirect
RAM to
Accumulator
with Carry
Add immediate 2
data to Acc
with Carry
Subtract
register from
Accwith
borrow
Oscillator
Period
12
Byte
Description
Subtract direct
2
byte from Acc
with borrow
Subtract
indirect RAM
from Acc with
borrow
Subtract
2
immediate data
from Acc with
borrow
Increment
Accumulator
Increment
register
2
Increment
direct byte
Increme.nt
indirect RAM
Decrement
Accumulator
Decrement
Register
Decrement
2
direct byte
Decrement
indirect RAM
Mnemonic
SUBB
A,direct
12
SUBB
A,@Ri
SUBB
A,#data
INC
A
INC
Rn
INC
direct
INC
@Ri
DEC
A
DEC
Rn
DEC
direct
DEC
@Ri
12
12
12
12
12
12
12
All mnemonics copyrighted
3-6
,<
Oscillator
Period
12
12
12
12
12
12
12
12
12
12
12
Intel Corporation 1980
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
MEMORY, ADDRESSING, INSTRUCTION SET
Table 3·2. Instruction Set Summary (continued)
OAT A TRANSFER Cont.
DATA TRANSFER
Description Byte
Move register
1
to
Accumulator
A,direct
Move direct
2
byte to
Accumulator
A,@Ri
Move indirect
RAM to
Accumulator
A,#data
Move
2
immediate data
to
Accumulator
Rn,A
Move
Accumulator
to register
Rn,direct
Move direct
2
byte to register
Rn,#data
Move
2
immediate data
to register
direct,A
Move
2
Accumulator
to direct byte
Move register
2
direct,Rn
to direct byte
direct,direct
Move direct
byte to direct
direct,@Ri
Move indirect
2
RAM to direct
byte
direct,#data
Move
immediate data
to direct byte
@Ri,A
Move
Accumulator
to indirect
RAM
@Ri,direct
Move direct
2
byte to indirect
RAM
@Ri,#data
Move
2
immediate data
to indirect
RAM
DPTR,#dataI6 Load Data
Pointer with a
16-bit constant
A,@A+DPTR Move Code
byte relative to
DPTR to Acc
A,@A+PC
Move Code
byte relative to
PC and Acc
A,@Ri
Move External
RAM (8-bit
addr) to Acc
A,@DPTR
Move External
RAM (16-bit
addr) to Acc
Mnemonic
MOV
A,Rn
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVe
MOVX
MOVX
Oscillator
Period
12
Mnemonic
MOVX @Ri,A
12
MOVX
@DPTR,A
12
PUSH
direct
POP
direct
XCH
A,Rn
XCH
A,direct
XCH
A,@Ri
XCHD
A,@Ri
12
12
24
12
12
24
Description Byte
Move Acc to
1
External RAM
(8-bit addr)
Move Acc to
External Ram
(l6-bit addr)
Push direct
2
byte onto stack
Pop direct byte 2
from stack
Exchange
register with
Accumulator
Exchange
2
direct byte
with
Accumulator
Exchange
indirect RAM
with
Accumulator
Exchange loworder Digit
indirect RAM
with Acc
Oscillator
Period
24
24
24
24
12
12
12
12
24
24
24
12
24
12
24
24
24
24
24
All mnemonics copyrighted ©Intel Corporation 1980
3-8
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Table 3·2. Instruction Set Summary (continued)
PROGRAM BRANCHING Cont.
BOOLEAN VARIABLE MANIPULATION
Mnemonic
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL
bit
ANL
C,bit
ANL
C,/bit
ORL
C,bit
ORL
C,/bit
MOY
C,bit
MOY
bit,C
JC
rei
JNC
rei
JB
bit,rel
JNB
bit,rel
JBC
bit,rel
Oscillator
Description Byte Period
12
Clear Carry
1
12
Clear direct bit
2
12
Set Carry
1
12
Set direct bit
2
12
Complement
1
Carry
12
Complement
2
direct bit
AND direct bit
24
2
to Carry
AND
24
2
complement of
direct bit to
Carry
OR direct bit
24
2
to Carry
OR
2
24
complement of
direct bit to
Carry
Move direct bit 2
12
to Carry
24
Move Carry to
2
direct bit
Jump if Carry
2
is set
Jump if Carry
24
2
not set
Jump if direct
24
Bit is set
Jump if direct
24
Bit is Not set
Jump if direct
24
3
Bit is set &
clear bit
JNZ
Mnemonic
rei
CJNE
A,direct,rel
CJNE
A,#data,rel
CJNE
RN ,#data,rel
CJNE
@Ri,#data,rel
DJNZ
Rn,rel
DJNZ
direct,rel
NOP
Description Byte
Jump if
2
Accumulator is
Not Zero
Compare direct
byte to Acc
and Jump if
Not Equal
Comare
3
immediate to
Acc and Jump
if Not Equal
Compare
immediate to
register and
Jump if Not
Equal
Compare
immediate to
indirect and
Jump if Not
Equal
Decrement
3
register and
Jump if Not
Zero
Decrement
3
direct byte and
Jump if Not
Zero
No Operation
Oscillator
Period
24
24
24
24
24
24
24
12
PROGRAMING BRANCHING
Mnemonic
ACALL addrll
LCALL addr16
RET
RETI
AJMP
LJMP
SJMP
addrl1
addr16
rel
JMP
@A+DPTR
JZ
rel
Description Byte
Absolute
2
Subroutine
Call
Long
Subroutine
Call
Return for
Subroutine
Return for
interrupt
Absolute Jump 2
Long Jump
3
Short Jump
2
(relative addr)
Jump indirect
relative to the
DPTR
Jump if
2
Accumulator is
Zero
Oscillator
Period
24
24
24
24
24
24
24
24
24
All mnemonics copyrighted ©Intel Corporation 1980
3-9
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Functional Groupings
than the second operand; otherwise it is cleared. A summary of the two-operand add/subtract operations is
shown in Figure 3-7.
The five functional groupings are as follows:
There are three arithmetic operations that operate exclusively on the A register (the accumulator). These are the
decimal-adjust for BCD addition and the two-test conditions shown in Figure 3-8. The decimal-adjust operation
converts the result from a binary addition of two two-digit
BCD values to yield the correct two-digit BCD result. During this operation the auxiliary-carry flag helps effect the
proper adjustment. Conditional branches may be taken
based on the value in the accumulator being zero or not
zero.
ARITHMETIC OPERATIONS
The 8051 implements the arithmetic operations of add, increment, decrement, compare-to-zero, decrement-andcompare-to-zero, decimal-add-adjust, subtract-withborrow, compare, multiply and divide.
Only unsigned binary integer arithmetic is performed in
the Arithmetic/Logic Unit. In the two-operand operations of add, add-with-carry and subtract-with-borrow
the A register (the accumulator) is the first operand and
receives the result of the operation. The second operand
can be an immediate byte, a register in the selected Register
Bank, a Register-Indirect Addressed byte or a Direct Addressed byte. These instructions affect the overflow (OV),
carry (C), auxiliary-carry (AC), and parity (P) flags in the
Program Status Word (PSW). The carry flag facilitates
nonsigned integer arithmetic and multi-precision rotations. Handling two's-complement-integer (signed) addition and subtraction can easily be accommodated with
software's monitoring of the PSW's overflow flag. The
auxiliary-carry flag simplifies BCD arithmetic. An operation that has an arithmetic aspect similar to a subtract is
the compare-and-jump-if-not-equal operation. This
operation performs a conditional branch if a register in the
selected Register Bank, or a Register-Indirect Addressed
byte of Internal Data RAM, does not equal an immediate
value; or ifthe A register does not equal a byte in the Direct
Addressable Internal Data RAM, or a Special Function
Register. While the destination operand is· not updated
and neither source operand is affected by the compare
operation, the carry flag is set if the first operand is less
•
•
•
•
The 8051 simplifies the implementation of software
counters since the increment and decrement operations
can be performed on the accumulator, a register in the
selected Register Bank, Register-Indirect Addressed byte
in the Internal Data RAM or a byte in the Direct Addressed Internal Data RAM or Special Function
Register. The 16-bit Data Pointer can be incremented.
For efficient loop control, the decrement-and-jump-ifnot-zero operation is provided. This operation can
decrement a register in the selected Register Bank, any
Special Function Register or any byte of Internal Data
RAM accessible through Direct Addressing, and force a
branch if the result is not zero. The increment/ decrement operations are summarized in Figure 3-9.
The multiply operation multiplies the one-byte A register
by the one-byte B register and returns a double-byte result
• . Declmal-Add·Adjust
• Jump.If.A.ls.Zero
• Jump·lf-A·ls-Not·Zero
I
REG~TER
I
Figure 3·8. Internal Data Memory Arithmetic
Operations (Register A Specific)
Add
Add-Wlth·Carry
Subtract·Wlth-Borrow
Compare-And-Jump·lf·Not·Equal (•••• )
DIRECT
Data
• Increment (INC)
• Decrement (DEC)
• Decrement·And·Jump·lf-Not·Zero
(DJNZ)
DIRECT
Data
(INC, DEC, DJNZ)
REGISTER
DPTR
(INC)
REGISTER
A
(INC, DEC)
REGISTER· INDIRECT
@R1,@RO
REGISTER
R7-RO
(INC, DEC, DJNZ)
Figure 3·7. Internal Data Memory Arithmetic
Operations
REGISTER-INDIRECT
@R1,@RO
(INC, DEC)
Figure 3·9. Internal Data Memory Arithmetic
Operations
3-10
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
(MSB in B, LSB in A). The divide operation divides the
one-byte accumulator by the one-byte B register and
returns a byte quotient to the A register and a byte remainder to the B register. These are shown in Figure 3-10.
Multiply
•• Divide
~
REGISTER
!I
REGISTER
AlB
• And (ANL)
• Or (ORL)
• Exclusive-or (XRL)
I
Figure 3·10. Internal Data Memory Arithmetic
Operations (Register A with
Register B)
IMMEDIATE
# data
LOGIC OPERATIONS
Figure 3·11.lnternal Data Memory Logic Operations
The 8051 permits the logic operations of and, or, and
exclusive-or to be performed on the A register by a second
operand which can be an immediate value, a register in the
selected Register Bank, a Register-Indirect Addressed
byte of Internal Data RAM or a Direct Addressed byte of
Internal Data RAM or Special Function Register. In addition, these logic operations can be performed on a Direct
Addressed byte of the Internal Data RAM or Special
Function Register using the A Register as the second
operand. Also, use of Immediate Addressing with Direct
Addressing permits these logic operations to set, clear or
complement any bit anywhere in the Internal Data RAM
or Special Function Registers without affecting the PSW,
Register Bank registers or accumulator. When one takes
into account that the registers R7-RO and the accumulator
can be Direct Addressed, the two-operand logic operations allow the destination (first operand) to be a byte in
the Internal Data RAM, a Special Function Register,
Register Bank registers (R7 -RO) or the accumulator, while
the choice of the second operand can be any of the
aforementioned or an immediate value. The 8051 can also
perform a logical or, or a logical and, between the Boolean
accumulator (i.e., the carry register) and any bit, or its
complement, that can be accessed through Direct Addressing. The and, or, and exclusive-or logic operations
are summarized in Figure 3-11.
••
•
•
•
•
•
Clear
Complement
Rotate-Left
Rotate-Left-Through-Carry
Rotate-Right
Rotate-Rlght-Through-Carry
Swap-Nibbles (Rotate Lelt Four)
I
REGIASTER
J
Figure 3·12. Internal Data Memory Logic Operations
(Register A Specific)
•
•
•
•
Set (SETB)
Clear (CLR)
Complement (CPL)
Jump-II-Blt-Set-Then-Clear-BIt (JBC)
REGISTER
C
(SETB,
CLR, CPL)
Figure 3·13. Internal Data Memory Logic Operations
(Bit·Specific)
DATA TRANSFER OPERATIONS
Look-up tables resident in Program Memory can be accessed by indirect moves. A byte constant can be transferred to the A register (i.e., accumulator) from the Program Memory location whose address is the sum of a base
register (the PC or DPTR) and the index register ,A). This
provides a convenient means for programming translation algorithms such as ASCII to seven segment conversions. The Program Memory move operations are shown
diagrammatically in Figure 3-14.
In addition to the logic operations that are performed on
Internal Data Memory as shown in Figure 3-11, there are
also logic operations that are performed specifically on
the accumulator. These are summarized in Figure 3-12.
In addition to the "and" and "or" bit logicals shown in
Figure 3-11, there are logicals that can operate exclusively
on a Direct Addressed bit. These operations are listed in
Figure 3-13. The carry flag is also addressed as a register
and can be set, cleared, or complemented with one-byte
instructions.
A byte location within a 256-byte block of External Data
Memory can be accessed using Rl or RO in RegisterIndirect Addressing. Any location within the fu1l64K External Data Memory address space can be accessed
through Register-Indirect Addressing using a 16-bit base
3-11
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
BOOLEAN VARIABLE OPERAT!ONS
A powerful set of instructions perform data transfer, conditional and logical operations on Boolean (i-bit)
variables. The 8051 's Boolean Processor can move any of
256 bits to or from the carry register (C) using Direct Addressing. Individual instructions will set, clear, or complement these 256 addressable bits or the carry register with
Direct Addressing. In conjunction with the bit-test instructions described below, these instructions provide
direct 8051 code for logic equations and Boolean expressions.
REGISTER
A
BASE-REGISTER- PLUS
INDEX-REGISTER-INDIRECT
@PC+A
(PROG MEM D-64K)
BASE-REGISTER- PLUS
INDEX-REGISTER-INDIRECT
@DPTR+A
(PROG MEM 0-64K)
Figure 3·14. Program Memory Move Operations
The carry register is a "Boolean Accumulator" for logical
"and" or logical "or" operations on Boolean variables.
The carry register acts as a source operand and the
destination for the logical operations. The source
operand can be one of the 256 addressable bits or its
complement.
REGISTER
A
REGISTER-INDIRECT
@R1,@RO
(EXT DATA 0-255)
The 8051 also provides test operations of jump-if-bit-set,
jump-if-bit-not-set and jump-if-bit-set-then-clear. These
branching instructions are relative to the address of the
next instruction (PC + 127 to PC - 128). Jumps can also
betaken on the status of the Carry register. Ajump can be
taken if the carry is set or not set.
REGISTER-INDIRECT
@DP
(EXT DATA 0-64K)
Figure 3·15. External Data Memory Move
Operations
CONTROL TRANSFER
register (i. e., the Data Pointer). These moves are shown in
Figure 3-15.
The 8051 has a non-paged Program Memory to accommodate relocatable code. The advantage of a non-paged
memory is that a minor change to a program that causes a
shift of the code's position in memory will not cause page
boundary readjustments to be necessary. This also makes
relocation possible. Relocation is desirable since it permits
several programmers to write relocatable modules in
various assembly and high-level languages which can later
be linked together to form the machine-object code.
The byte in-code-constant (immediate) moves and byte
variable moves within the 8051 are highly orthogonal as
detailed in Figure 3-16. When one considers that the accumulator and the registers in the Register Banks can be
Direct Addressed, the two-operand data transfer operations allow a byte to be moved between any two of the
Register Bank registers, Internal Data RAM, accumulator and Special Function Registers. Also, immediate operands can be moved to any ofthese locations.
Of particular interest is the Direct Address to Direct Address move which permits the value in a port to be moved
to the Internal Data RAM without using any Register
Bank registers or the accumulator. The Data Pointer
register can be loaded with a double-byte immediate
value.
Sixteen-bit jumps and calls are provided to allow branching to any location in the contiguous 64K Program
Memory address space and pre-empt the need for Program Memory bank switching. Eleven-bit jumps and calls
are also provided to maintain compatibility with the 8048
and to provide an efficient jump within a 2K program
module. Unlike the 8048, the 8051 's call operations do not
push the Program Status Word (PSW) to the stack along
with the Program Counter, since many subroutines written for the 8051 do not affect the PSW. Hence the 8051
return operations pop only the Program Counter. The
8051 's branch, call and return operations are shown
diagrammatically in Figures 3-18,3-19, and 3-20, respectively.
The A Register can be exchanged with a register in the
selected Register Bank, with a Register-Indirect Addressed
byte in the Internal Data RAM, or with a Direct Addressed
byte in the Internal Data RAM, or Special Function
Register. The least significant nibble of the A register can
also be exchanged with the least significant nibble of a
Register-Indirect Addressed byte in the Internal Data
RAM. The exchange operation is shown in Figure 3-17.
The 8051 also provides a method for performing condi3-12
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
REGISTER
C
REGISTER
DPTR
16
REGISTER
R7-RO
IMMEDIATE
# dete
REGISTER
A
REGISTER-INDIRECT
@R1.@RO
REGISTER-INDIRECT
@SP
Figure 3·16. Internal Data Memory Move Operations
REGISTER
R7-RO
DIRECT
Dala
·SP is pre-incremented.
REGISTER
A
REGISTER-INDIRECT
@R1.@RO
4 LOW
NIBBLE
·SP is pre-incremented.
Figure 3·17. Internal Data Memory Exchange
Operations
Figure 3·19. Call Operations
REG~~TER
REGplSCTER
~""""_-I-I,-_
7 16 _ _~_IM_M_E_D_IA_TE--,
_
Addr16
1..........-"--"'1/<-16----;1
REGIST':~~~DIRECT 1
·SP is post-decremented.
Figure 3·20. Return Operations
Figure 3·18. Unconditional Branch Operations
3·13
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
tional and unconditional hranching, relative to the starting address of the next instruction (PC + 127 to PC 128). The accumulator test operations allow a conditional
branch based on the accumulator being zero or non-zero.
Also provided are compare-and-jump-if-not-equal and
decrement-and-jump-if-not-zero. These are shown in
Figure 3-21. The register-indirect jump in the 8051 permits
branching relative to a base register (DPTR) with an offset
provided by the non-signed integer value in the index
register (A). This accommodates N-way branching. The
indirect jump is shown in Figure 3-22.
•
•
•
•
Short Jump
Jump-II-Bit-Set
Jump-II-Bit-Not-Set
Jump-II-Bit-Set-Then-Clear-Bit
•
•
•
•
Auxiliary Carry: The auxiliary-carry flag (AC) is set if an
arithmetic instruction results in a carry-out of bit 3 (from
addition) or a borrow into bit 3 (for subtraction); otherwise it is cleared. This flag is useful for BCD arithmetic.
Overflow: The overflow flag (OV) is set if the addition or
subtraction of signed variables produces an overflow error (i.e., if the magnitude of the sum or difference is too
great for the seven magnitude bits in two's complement
representation); otherwise it is cleared. The same flag also
indicates when the product resulting from multiplication
overflows one byte, and if division by zero was attempted.
parity: The parity flag (P) is updated after every instruc-·
tion cycle to indicate the parity of the accumulator. It is set
if the number of"1" bits in the accumulator is odd, otherwise, it is cleared.
Jump-II-A-Zero
Jump-II-A-Not-Zero
Decrement-And-Jump-II-Not-Zero
Compare-And-Jump-II-Not-Equal
The other four PSW bits consist of a general purpose flag,
FO, two bits, RS1 and RSO, which select one offour working register banks, and a reserved bit location.
Instruction Definitions
The rest of this chapter defines all the instructions and
operations which the MCS-51 CPU can perform. There is
a separate section for each of the 51 basic operations,
ordered alphabetically according to the operation
mnemonic.
Figure 3·21. Unconditional Short Branch and
Conditional Branch Operations
When an operation may apply to more than one data type
(generally bit and byte data), the MCS-51 assembly
language uses the same mnemonic for each, reducing the
number of mnemonics the programmer must remember.
The assembler determines which instruction is appropriate from the operands specified. Thus, the
mnemonic "CLR" can operate on the eight-bit accumulator ("CLR A"), or on one-bit variables ("CLR
FO"). The mnemonics ANL, ORL, CPL, and MOV can
relate to more than one data type as well. These operations
present each data type in a separate section.
Figure 3·22. Unconditional Branch (Indirect)
Operation
Each section then describes the action taken by the operation, the flags and registers affected, and shows a short example of how an instruction might be used in a program.
Next comes the number of bytes and machine cycles required, the corresponding binary machine-language encoding, and a symbolic description or restatement of the
function implemented.
Arithmetic Flags
The program status word (PSW) contains eight bits. Four
bits are hardware status flags set or cleared by the CPU to
show the result of certain calculations. In general, these
flags are used for the following purposes:
Carry: The carry flag (CY) is set by an arithmetic instruction ifthere is a carry-out of the highest order bit (from addition) or if a borrow is needed for the highest-order bit
(from subtraction or a comparison); otherwise it is
cleared. It is also affected by several rotate operations.
The carry flag is also the Boolean accumulator. When
treated as a Boolean accumulator, the carry mnemonic is
"C"; otherwise it is CY which denotes an address.
Note: Only the carry, auxiliary-carry, and overflow flags
are discussed in these instruction descriptions. Since the
parity bit (PSW _0) is recomputed after every instruction
cycle any instruction that alters the accumulator - either
inherently or as a special function register - could affect
the parity flag. Similarly, instructions which alter directly
addressed registers could affect the other status flags if the
3·14
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
instruction is applied to the PSW. Status flags can also be
modified by the generalized bit-manipulation instructions.
are allowed, and gives the assembly language notation,
byte and cycle counts, encoding format, and a symbolic
description for each.
Nineteen operations allow more than one addressing
mode for the source and/or destination operand. The
headings for these sections show the instruction format
with such operands enclosed in angle brackets (for example, MOV ,
Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents,
leaving the result in the accumulator. The carry and auxiliary-carry flags are set, respectively, if there is
a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
Function:
Description:
OV is set if there is a carry-out of bit 6 but not out of bit 7, or acarryout of bit 7 but notoutofbit6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum
of two positive operands or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
The accumulator hoidsOC3H (llOOOOllB) and register 0 hoidsOAAH (lOlOlOlOB) with the carry flag
set. The instruction,
Example:
ADDC
A,RO
will leave6EH (01 1011 lOB) in the accumulator with ACcleared and both the carry flag and OV set to 1.
ADDC
A,Rn
Bytes:
Cycles:
Encoding:
I0
Operation:
ADDC
0
111
1
(A)~(A)
r
r
r
+ (C) + (Rn)
ADDC
A,direct
Bytes:
2
Cycles:
Encoding:
I
Operation:
ADDC
0 0
I
1 1 0
(A)~(A)
1 0
1
I
direct address
I
+ (C) + (direct)
ADDC
A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
0 01
110
AD DC
(A)-+-(A)
+
1
(C)
+
«Rm
ADDC
A,#data
Bytes:
2
Cycles:
1
Encoding:
I0
Operation:
AD DC
0
1
(A)~ (A)
I
1 0
1 0
0
I Iimmediate data I
+ (C) + #data
3-17
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
A ..UID
"",,'W.I
.. """".0101
I.
u. ........
Function:
Description:
Example:
Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and
the second byte of the instruction. The destination must therefore be within the same 2K block of
program memory as the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location OI23H. The instruction,
AJMP
Bytes:
Cycles:
Encoding:
Operation:
AN L
JMPADR
is at location 0345H and will load the PC with OI23H.
2
2
I
a10
a9
a8
0
I
0
0
0
I
a7
a6
a5
a41 a3
a2
al
aO
AJMP
(PC)..-(PC) +2
(PC I 0-0) ~ page address
,
Function:
Description:
Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores the
results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the
destination is a direct address, the source can be the accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
Example:
If the accumulator holds OC3H (l1OOOOIIB) and register 0 holds OAAH (1010101OB) then the instruction,
ANL
A,RO
will leave 4lH (01OOOOOlB) in the accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of bits in
any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared
would either be a constant contained in the instruction or a value computed in the accumulator at
run-time. The instruction,
ANL
PI ,#01110011 B
will clear bits 7, 3, and 2 of output port 1.
ANL
A,Rn
Bytes:
Cycles:
Encoding:
Operation:
1
0
r
r
r
ANL
(A) .... (A) A (Rn)
3-18
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
ANL
A,direct
Bytes:
2
Cycles:
Encoding:
Operation:
ANL
1
1° °
1
Operation:
A,#data
Bytes:
Cycles:
Encoding:
Operation:
1
10
i
I
ANL
(A) .... (A) 1\ «Ri»
2
1....0
_ _ _0__
1 .....1_0.......1_0__0....1
I
immediate data
I
ANL
(A) 1\ #data
direct,A
Bytes:
2
Cycles:
Encoding:
I-I_o__o__I...I_o_o__I_o.....J
Operation:
ANL
(direct) .... (direct) 1\ (A)
AN L
direct address
° 11
ANL
(A)'--(A) 1\ (direct)
(A)~
AN L
10
A,@Ri
Bytes:
Cycles:
Encoding:
ANL
1° °
direct,#data
Bytes:
3
Cycles:
2
Encoding:
1-10___0__1....1_°_°__1 _.....J
Operation:
ANL
(direct) .... (direct)
1\
I
immediate data "
#data
3-19
AFN,01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Function:
Description:
Logical-AND for bit variables
°
If the Boolean value of the source bit is a logical then clear the carry flag; otherwise leave the carry
flag in its current state. A slash ("I") preceding the operand in the assembly language indicates that
the logical complement of the addressed bit is used as the source value, but the source bit itself is not
affected. No other flags are affected.
Example:
Only direct bit addressing is allowed for the source operand.
Set the carry flag if, and only if, Pl.O = 1, ACe. 7 = 1, and OV = 0:
MOV C,Pl.O
ANL C,ACe.7
ANL C,/OV
ANL
C,bit
Bytes:
Cycles:
2
2
° ° °1° ° 1 °I
Encoding:
11
Operation:
ANL
(C)~
ANL
C,/bit
Bytes:
Cycles:
;LOAD CARRY WITH INPUT PIN STATE
;AND CARRY WITH ACCUM. BIT 7
;AND WITH INVERSE OF OVERFLOW FLAG
(C) /\ (bit)
2
2
En~oding:
11-_1_0___
1 ..&.1_0_0_0__
0-,
Operation:
ANL
(C).- (C)
( bit address
I
.., (bit)
3-20
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
CJNE
,,rel
Function:
Description:
Example:
Compare and Jump if Not Equal.
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry
flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant.
The accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CJNE
NOT_EQ:
R7,#60H, NOT_EQ
R7 = 60H.
IF R7<60H.
R7>60H.
JC
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this
instruction determines whether R7 is greater or less than 60H.
If the data being presented to port 1 is also 34H, then the instruction,
WAIT:
CJNE
A,P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the accumulator does
equal the data read from PI. (If some other value was being input on PI, the program will loop at
this point until the PI data changes to 34H.)
CJ N E
A,direct,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
1~1_0___1....LI_o__l_0_1--1
Idirect address
rel. address
I
CJNE
+3
IF (direct) < (A)
THEN (PC)~(PC) + rei and (C)'-O
OR
IF (direct) > (A)
THEN (PC)~(PC) + reI and (C).-1
(PC)~(PC)
CJNE
A,#data,rel
Bytes:
3
Cycles:
2
I
immediate data
Encoding:
1_1_o
....
___1.....1_o__
1 _0_0_1
Operation:
CJNE
(PC) -+- (PC) + 3
IF #data < (A)
THEN (PC) ~(PC) + reI and (C)~
OR
IF #data > (A)
THEN (PC) '--(PC) + reI and (C)1-1
I I
rel. address
°
3-21
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
CJ N E
Rn,#data,re!
Bytes:
3
Cycles:
2
I immediate data
Encoding:
LI_l_o_ _ _l...1.l_l_r_r__
r--,
Operation:
CJNE
(PC) "--(PC) + 3
IF #data < (Rn)
THEN (PC) ~(PC) + rei and (C)..-O
OR
IF #data > (Rn)
THEN (PC)~(PC) + rei and (C)..-1
I rei. address
I
CJNE
@Ri,#data,rel
Bytes:
3
Cycles:
2
Iimmediate data I
Encoding:
,-1_1_o__11-10_ _ _1--,'1
Operation:
CJNE
(PC)..-(PC) + 3
IF #data < «Ri»
THEN (PC~(PC) + rei and (C)..-1
OR
IF #data > «Ri»
THEN (PC)~(PC) + rei and (C).-O
CLR
I rei. address 1
A
Function:
Description:
Example:
Clear Accumulator
The accumulator is cleared (all bits set to zero). No flags are affected.
The accumulator contains 5CH (01011100B). The instruction,
CLR
A
will leave the accumulator set to OOH (OOOOOOOOB).
Bytes:
Cycles:
1
1
Encoding:
LI_l_ _ _ _
0...l.1_0_l__
0_0--'
Operation:
CLR
(A)~O
3-22
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
CLR
bit
Function:
Description:
Example:
Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag
or any directly addressable bit.
Port 1 has previously been written with 5DH (010111OIB). The instruction,
CLR
P1.2
will leave the port set to 59H (OlOllOOIB).
CLR
C
Bytes:
Cycles:
Encoding:
11
Operation:
CLR
(C)..-O
CLR
bit
Bytes:
Cycles:
0 01 0 0
I
2
Encoding:
11
Operation:
CLR
(bit)..-O
CPL
1 1
0 01 0 0
1 01
A
Function:
Description:
Example:
Complement Accumulator
Each bit of the accumulator is logically complemented (one's complement). Bits which previously
contained a one are changed to zero and vice-versa. No flags are affected.
The accumulator contains 5CH (OlOlllOOB). The instruction,
CPL
Bytes:
Cycles:
A
will leave the accumulator set to OA3H (lOlOOOllB).
1
Encoding:
L-I_l_ _ _1--,-1_o_1_0__
0-,
Operation:
CPL
(A)~
-, (A)
3-23
MEMORY, ADDRESSING, INSTRUCTION SET
CPL
bit
Function:
Description:
Example:
Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero and viceversa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original data will
be read from the output data latch, not the input pin.
Port 1 has previously been written with 5BH (01011101B). The instruction sequence,
CPL
CPL
P1.1
P1.2
will leave the port set to 5BH (0101101IB).
CPL
C
Bytes:
Cycles:
Encoding:
Operation:
11
bit
Bytes:
Cycles:
, (C)
2
1
Encoding:
11
Operation:
CPL
(bit)..... ,
DA
1 11
CPL
(C~
CPL
I
1 0 0
0
0
I
1 0 0
1 01
bit address
(bit)
A
Function:
Description:
Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition.
If accumulator bits 3-0 are greater than nine (xxxxlOlO-xxxxl111), or if the AC flag is one, six is
added to the accumulator producing the proper BCD digit in the low-order nibble. This internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all
high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (101Oxxxx-l111xxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't
clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater
than 100, allowing multiple precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal
conversion by adding OOH, 06H, 60H, or 66H to the accumulator, depending on initial accumulator
and PSW conditions.
3-24
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Example:
Note: DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation, nor
does DA A apply to decimal subtraction.
The accumulator holds the value 56H (0101011OB) representing the packed BCD digits of the
decimal number 56. Register 3 contains the value 67H (01100111 B) representing the packed BCD
digits of the decimal number 67. The carry flag is set. The instruction sequence,
ADDC
DA
A,R3
A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the accumulator to the value 24H (00100100B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal
sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and 1 is 124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the accumulator initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD
DA
Bytes:
Cycles:
A,#99H
A
will leave the carry set and 29H in the accumulator, since 30 + 99
sum can be interpreted to mean 30 - 1 = 29.
1
=
129. The low-order byte of'the
Encoding:
Operation:
DA
-contents of Accumulator are BCD
IF [[(A3-0) >9] V [(AC) = 1]]
THEN (A3-0).-(A3-0) + 6
AND
IF [[(A7-4) >9] V [(C) = 1]]
THEN (A7-4).-(A7-4) + 6
3-25
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
I"'lr-,...
1.11:""
L. •• &_
uyn::
Function:
Description:
Example:
Decrement
The variable indicated is decremented by 1. An original value of OOH will underflow to OFFH. No
flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or
register = indirect.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain OOH and 40H,
respectively. The instruction sequence,
DEC
DEC
DEC
@RO
RO
@RO
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to OFFH and 3FH.
DEC
A
Bytes:
Cycles:
Encoding:
Operation:
I 0 0 0
1 1. 0
I
DEC
(A) ...... (A) -
DIV
1 0 0
1
AB
Function:
Description:
Example:
Divide
DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in
register B. The accumulator receives the integer part of the quotient; register B receives the integer
remainder. The carry and OV flags will be cleared.
Exception: if B had originally contained OOH, the values returned in the accumulator and B-register
will be undefined and the overflow flag will be set. The carry flag is cleared in any case.
The accumulator contains 251 (OFBH or 11111011B) and B contains 18 (l2H or 0001001OB). The instruction,
DIV
Bytes:
Cycles:
Encoding:
Operation:
AB
will leave 13 in the accumulator (OOH or 00001101B) and the value 17 (lIH or 00010001 B) in B,
since 251 = (13 x 18) + 17. Carry and OV will both be cleared.
1
4
1 1000 \0100\
DIV
(A) 15-84- (A) / (B)
(B)7-0
DEC
Rn
Bytes:
Cycles:
3-26
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Encoding:
Operation:
DEC
direct
Bytes:
Cycles:
111
r
(Rn)...- (Rn) -
1
1
0
DEC
r
0
11
1
1
0 0
0
I
1
0
1
DEC
(direct) +- (direct) -
DEC
r
2
Encoding:
Operation:
0 0
direct address
1
@Ri
Bytes:
Cycles:
Encoding:
Operation:
10
0 0
11
0
1 1
i
I
DEC
«Ri»..--«Ri» -
1
3-27
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
DJNZ
< byte>,
Function:
Description:
Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the second
operand if the resulting value is not zero. An original value of OOH will underflow to OFFH. No
flags are affected. The branch destination would be computed by adding the signed relativedisplacement value in the last instruction byte to the PC, after incrementing the PC to the first byte
of the following instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
Example:
Internal Ram locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively.
The instruction sequence,
DJNZ
DJNZ
DJNZ
40H,LABEL_l
50H,LABEL~
60H,LABEL_3
will cause a jump to the instruction at label LABEL~ with the values OOH, 6FH, and 15H in the
three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times, or for
adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruction sequence,
TOGGLE:
MOV
CPL
DJNZ
R2,#8
P1.7
R2,TOGGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output port 1. Each
pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ
Rn,rel
Bytes:
Cycles:
Encoding:
Operation:
2
2
1'---1_ _0__
I ......I_l_r_r_......
r1
direct address
DJNZ
+ 2
- 1
(Rn) > 0 or (Rn) < 0
THEN
(PC)~(PC)
(Rn)~(Rn)
IF
(PC~(PC)
+ rei
DJNZ
direct,rel
Bytes:
3
Cycles:
2
Encoding:
Operation:
L.1_l_ _0_l.....l..I_0_l_0_l.....11
1 direct address I
reI. address
I
DJNZ
(PC)~(PC)
+2
(direct)~(direct)
IF
(direct) > 0 or (direct) < 0
THEN
(PC)~(PC) + rei
3-28
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
INC
Function:
Descrip.tion:
Example:
Increment
INC increments the indicated variable by I. An original value of OFFH will overflow to OOH. No
flags are affected. Three addressing modes are allowed: register, direct, or register = indirect.
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
Register 0 contains 7EH (01 11 111 lOB). Internal RAM locations 7EH and 7FH contain OFFH and
40H, respectively. The instruction sequence,
INC
INC
INC
@RO
RO
@RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) OOH
and 41H.
INC
A
Bytes:
Cycles:
Encoding:
Operation:
INC
Operation:
1 0 0
INC
(A).-(A) +
direct
Bytes:
Cycles:
I0
11
r
r
r
1
0
1
2
1
1
Operation:
0 0 0
INC
(Rn) . - (Rn) +
Encoding:
INC
I
0 0 0 0
Rn
Bytes:
Cycles:
Encoding:
INC
I0
0 0 0 01 0
I
I direct address
INC
(direct).-(direct) +
@Ri
Bytes:
Cycles:
Encoding:
Operation:
10
I
0 0 0 0
INC
«Ri».-«Ri» +
3-29
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
INC
DPTR
Function:
Description:
Example:
Increment Data Pointer
Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an overflow
of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment the high-order
byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence,
INC
INC
INC
Bytes:
Cycles:
DPTR
DPTR
DPTR
will change DPH and DPL to 13H and 01H.
1
2
Encoding:
IL-..l_0_ _0--,-10__
0_1_1......1
Operation:
INC
(DPTR).-(DPTR) + 1
JB
bit,rel
Function:
Description:
Example:
Jump if Bit set
If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit
tested is not modified. No flags are affected.
The data present at input port 1 is 1100101OB. The accumulator holds 56 (010101IOB). The instruction sequence,
PI.2,LABELl
ACC.2,LABEL2
JB
JB
will cause program execution to branch to the instruction at label LABEL2.
Bytes:
Cycles:
Encoding:
Operation:
3
2
I° °
1
°I° ° ° °
1
bit address
I
reI. address
I
JB
(PC) + 3
(bit) = 1
THEN
(PC)"-(PC) + reI
(PC)~
IF
3-30
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
JBC
bit,rel
Function:
Description:
Example:
Jump if Bit is set and Clear bit
If the indicated bit is one, branch to the address indicated: otherwise proceed with the next
instruction. In either case, clear the designated bit. The branch destination is computed by adding
the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC
to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data will be
read from the output data latch, not the input pin.
The accumulator holds 56H (OlOlOllOB). The instruction sequence,
JBC
JBC
ACC.3,LABELl
ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2, with the
accumulator modified to 52H (OlOlOOlOB).
Bytes:
Cycles:
Encoding:
Operation:
3
2
1
0
0 0
11
I
0 0 0 01
bit address
I
reI. address
I
JBC
(PC)~ (PC)
IF
(bit) =
THEN
1
+3
(bit)..-- 0
(PC)~(PC)
JC
+ reI
rei
Function:
Description:
Example:
Jump if Carry is set
If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction.
The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected.
The carry flag is cleared. The instruction sequence,
JC
CPL
JC
Bytes:
Cycles:
LABELl
C
LABEL2
will set the carry and cause program execution to continue at the instruction identified by the label
LABEL2.
2
2
Encoding:
I
Operation:
JC
0
1 0 0
I
0 0 0 0
(PC)~(PC)
IF
I
I
reI. address
I
+2
(C) = 1
THEN
(PC)~(PC)
+ reI
3-31
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
JMP
@A+DPTR
Function:
Description:
Example:
Jump indirect
Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load
the resulting sum to the program counter. This will be the address for subsequent instruction
fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order eight bits
propagates through the higher-order bits. Neither the accumulator nor the data pointer is altered.
No flags are affected.
An even number from to 6 is in the accumulator. The following sequence of instructions will
branch to one of four AJMP instructions in a jump table starting at JMP_ TBL:
°
MOV
JMP
JMP_ TBL: AJMP
AJMP
AJMP
AJMP
DPTR,#JMP_TBL
@A+DPTR
LABELO
LABELl
LABEL2
LABEL3
If the accumulator equals 04H when starting this sequence, execution will jump to label LABEL2.
Remember that AJMP is a two-byte instruction, so the jump instructions start at every other address.
Bytes:
Cycles:
Encoding:
Operation:
JNB
1
2
1....o___1. . 1_o_o_1
.
_____I 1
JMP
(PC).-(A) + (DPTR)
bit,rel
Function:
Description:
Example:
Jump if Bit Not set
If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next in-
struction. The branch destination is computed by adding the signed relative-displacement in the
third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
The bit tested is not modified. No flags are affected.
The data present at input port 1 is 1100 10 lOB. The accumulator holds 56H (010101 lOB). The instruction sequence,
JNB
JNB
Bytes:
Cycles:
P1.3,LABELl
ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.
3
2
I bit address 1 IreI. address 1
Encoding:
1.....0_0_ _
1......
1_0_0_0_0-,1
Operation:
JNB
(PC).-(PC) + 3
IF (bit) =
THEN (PC)..-- (PC) + reI.
°
3-32
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
JNC
rei
Function:
Description:
If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruc-
Example:
tion. The branch destination is computed by adding the signed relative-displacement in the second
instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The
carry flag is not modified.
The carry flag is set. The instruction sequence,
Jump if Carry not set
JNC LABELl
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by the label
LABEL2.
Bytes:
Cycles:
Encoding:
Operation:
2
2
reI. address
I
JNC
+ 2
(PC)~(PC)
IF (C) =
THEN
JNZ
I
I-Io___o_l-al_o_o__o_o-J
°
(PC)~(PC)
+ reI
rei
Function:
Description:
If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the
Example:
next instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not
modified. No flags are affected.
The accumulator originally holds OOH. The instruction sequence,
Jump if accumulator Not Zero
JNZ LABELl
INC A
JNZ LABEL2
will set the accumulator to OIH and continue at label LABEL2.
Bytes:
Cycles:
2
2
Encoding:
1-1
Operation:
°__°_°_°-11
0
_ _ _ _.....
1
1 reI. address I
JNZ
(PC)~(PC)
IF (A) ~
THEN
°
+ 2
(PC)~(PC)
+ reI
3-33
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
JZ
rei
Jump if Accumulator Zero
Function:
Description:
If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the
Example:
next instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not
modified. No flags are affected.
The accumulator originally contains 01H. The instruction sequence,
JZ
DEC
JZ
LABELl
A
LABEL2
will change the accumulator to OOH and cause program execution to continue at the instruction
identified by the label LABEL2.
Bytes:
Cycles:
Encoding:
Operation:
2
2
1_o
..... ____
0...LI_o_o__o_o. . 1.
I
JZ
(PC) + 2
(A) =
THEN (PC)~(PC) + rei
(PC)~
IF
LCALL
reI. address
°
addr16
Function:
Description:
Example:
Long Call
LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto
the stack (low byte first), incrementing the stack pointer by two. The high-order and low-order
bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may
therefore begin anywhere in the full 64K-byte program memory address space. No flags are affected.
Initially the stack pointer equals 07H. The label "SUBRTN" is assigned to program memory location 1234H. After executing the instruction,
LCALL
Bytes:
Cycles:
SUBRTN
at location 0123H, the stack pointer will contain 09H, internal RAM locations OSH and 09H will
contain 26H and 01H, and the PC will contain 1235H.
3
2
Encoding:
10
......__
0_0_--'-10__0_1_0.......1
Operation:
LCALL
addr 15 - addrS
addr7 - addrO
I
(PC)~ (PC) + 3
(SP).-(SP) + 1
«SP»~ (PC7-0)
(SP).-(SP) + 1
«SP»1-( PC I5-S)
(PC).- addr I5-0
3-34
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
LJMP
addr16
Function:
Description:
Example:
Long Jump
LJMP causes an unconditional branch to the indicated address, by loading the high-order and loworder bytes of the PC (respectively) with the second and third instruction bytes. The destination
may therefore be anywhere in the full 64K program memory address space. No flags are affected.
The label "JMPADR" is assigned to the instruction at program memory location 1234H. The instruction,
LJMP
Bytes:
Cycles:
Encoding:
Operation:
JMPADR
at location 0123H will load the program counter with 1234H.
3
2
I0
I
0 0 0 0 0
Iaddr15 - addr8 I
1 0
addr7 - addrO
I
LJMP
(PC)~addq5-0
MOV
,
Function:
Description:
Example:
Move byte variable
The byte variable indicated by the second operand is copied into the location specified by the first
operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination addressing modes are allowed.
Internal RAM location 30H holds 40H. The value of RAM location 40H is lOH. The data present at
input port 1 is 1lOO lO lOB (OCAH).
MaV
MaV
MaV
MaV
MaV
MaV
RO,#30H
A,@RO
Rl,A
R,@Rl
@Rl,Pl
P2,P!
;RO<= 30H
;A <= 40H
;Rl < = 40H
;B <= lOH
;RAM (40H) <= OCAH
;P2 #OCAH
leaves the value 30H in register 0, 40H in both the accumulator and register 1, lOH in register B, and
OCAH (llOOlOlOB) both in RAM location 40H and output on port 2.
MOV
A,Rn
Bytes:
Cycles:
Encoding:
11
Operation:
Mav
011
r
r
r
I
1
I Idirect address
(A)~(Rn)
MOV
A,direct
Bytes:
2
Cycles:
1
Encoding:
11
Operation:
Mav
(A}'-( direct)
01 0
1 0
3-35
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
MOV
A,@R!
Bytes:
Cycles:
01 0 1 1 i I
Encoding:
11
Operation:
MOV
(A) ' 4 - - «Ri»
MOV
A,#data
Bytes:
2
Cycles:
Encoding:
Operation:
MOV
1
10
11 0 1 0 01
1immediate data 1
MOV
(A)'-#data
Rn,A
Bytes:
Cycles:
Encoding:
Operation:
I1
111
r
r
r
I
r
r
r
I
r
r
r
MOV
(Rn)~(A)
MOV
Rn,direct
Bytes:
2
Cycles:
2
Encoding:
Operation:
MOV
11 0
o 11
direct addr.
MOV
(Rn).-(direct)
Rn,#data
Bytes:
2
Cycles:
1
Encoding:
Operation:
1I 1
I0
I immediate data
MOV
(Rn)~#data
MOV
direct,A
Bytes:
2
Cycles:
Encoding:
Operation:
1
1
1I 0 1 0 1I
I
I
direct address
I
MOV
(direct)~
MOV
direct address
(A)
direct,Rn
Bytes:
2
Cycles:
2
Encoding:
0 0 o 11
r
r
r
I
3-36
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Operation:
Mav
(direct)~
MOV
(Rn)
direct,direct
Bytes:
3
2
Cycles:
Encoding:
11
Operation:
Mav
0
0
o 10
1
0
1
I I dir. addr. (src) I
I dir. addr. (dest)
I
(direct)~ (direct)
MOV
direct,@Ri
2
Bytes:
Cycles:
2
Encoding:
Operation:
11
0
0
01 0
1
1 i
I
I direct addr. I
Mav
( direct)~«Ri»
MOV
direct,#data
Bytes:
3
Cycles:
2
Encoding:
Operation:
MOV
I
I0
1 0
1 0
1
I I direct address I I immediate data I
i
I
Mav
(direct)~
#data
11
1
@Ri,A
Bytes:
Cycles:
Encoding:
Operation:
I0
1
1
01 0
1
1
1
1
Mav
«Ri»~(A)
MOV
@Ri,direct
Bytes:
2
2
Cycles:
Encoding:
Operation:
11
0
I
direct addr·1
MaV
«Ri»~( direct)
MOV
@Ri,#data
Bytes:
2
Cycles:
Encoding:
0
1
Operation:
11 0
immediate data
Mav
«RI)~ #data
3-37
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
MOV
,
Function:
Description:
Example:
Move bit data
The Boolean variable indicated by the second operand is copied into the location specified by the
first operand. One of the operands must be the carry flag; the other may be any directly addressable
bit. No other register or flag is affected.
The carry flag is originally set. The data present at input port 3 is 11000101 B. The data previously
written to output port 1 is 35H (00110101B).
MOV
MOV
MOV
P1.3,C
C,P3.3
Pl.2,C
will leave the carry cleared and change port 1 to 39H (00111001 B).
MOV
C,bit
Bytes:
Cycles:
Encoding:
Operation:
2
1
1...._1_o_ _0--L..I_o_0_1_0....J1
I bit address
MOV
(C)~(bit)
MOV
bit,C
Bytes:
Cycles:
2
2
° ° I° ° °
Encoding:
11
Operation:
MOV
(bit) 4 - (C)
MOV
1
1
Ibit address
DPTR,#data16
Function:
Description:
Example:
Load Data Pointer with a 16-bit constant
The data pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded into the
second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the
third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.
The instruction,
MOV
Bytes:
Cycles:
DPTR,#1234H
will load the value 1234H into the data pointer: DPH will hold 12H and DPL will hold 34H.
3
2
°°
1 10
° ° °I I
Encoding:
11
Operation:
MOV
(DPTR)4- #data15-0
immed. data15 - 8
3·38
I
immed. data7 -
°I
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
MOVC
A,@A+
Function:
Description:
Example:
Move Code byte
The MOVC instructions load the accumulator with a code byte, or constant from program memory.
The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents
and the contents of a sixteen-bit base register, which may be either the data pointer or the PC. In the
latter case, the PC is incremented to the address of the following instruction before being added
with the accumulator: otherwise the base register is not altered. Sixteen-bit addition is performed so
a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected.
A value between 0 and 3 is in the accumulator. The following instructions will translate the value in
the accumulator to one of four values defined by the DB (define byte) directive.
REL_PC:
INC
A
MOVC
A,@A+PC
RET
DB
66H
DB
77H
DB
88H
DB
99H
If the subroutine is called with the accumulator equal to 01H, it will return with 77B in the accumulator. The INC A before the MOVC instruction is needed to "get around" the RET instruction
above the table. If several bytes of code separated the MOVC from the table, the corresponding
number would be added to the accumulator instead.
MOVC A,@A+ DPTR
Bytes:
1
Cycles:
2
Encoding:
Operation:
.....
1_l_0_0_----'I_O_O__l_-.J
MOVC
(A)~
«A) + (DPTR»
MOVC A,@A+ PC
Bytes:
1
Cycles:
2
Encoding:
Operation:
11
0 0
°I°
0
1
MOVC
+1
+ (PC»
(PC)~(PC)
(A)~«A)
3-39
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
MOVX
< dest·byte> ,
Function:
Description:
Move External
The MOVX instructions transfer data between the accumulator and a byte of external data
memory, hence the "X" appended to MOV. There are two types of instructions, differing in whether
they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or RI in the current register bank provide an eight-bit address
multiplexed with data on po. Eight bits are sufficient for external I/O expansion decoding or a
relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output
higher-order address bits. These pins would be controlled by an output instruction preceding the
MOVX.
In the second type of MOVX instruction, the data pointer generates a sixteen-bit address. P2 outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the low-order
eight bits (DPL) with data. P2 retains the high-order bits; any data previously on P2 is lost. This
form is faster and more efficient when accessing very large data arrays (up to 64K bytes), since no
additional instructions are needed to set up the output ports.
Example:
It is possible in some situations to mix the two MOVX types. A large RAM array with its highorder address lines driven by P2 can be addressed via the data pointer, or with code to output highorder address bits to P2 followed by a MOVX instruction using RO or RI.
An external 256 byte RAM using mUltiplexed address/data lines (e.g., an Intel® 8155
RAM/I/O/Timer) is connected to the '8051 Port O. Port 3 provides leontrol ones for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H. Location
34H of the external RAM holds the value 56H. The instruction sequence,
MOVX
MOVX
A,@Rl
@RO,A
copies the value 56H into both the accumulator and external RAM location 12H.
A,@Ri
Bytes:
1
Cycles:
2
MOVX
Encoding:
11
Operation:
MOVX
(A).-«Ri»
0 0 0
1
1
MOVX A,@DPTR
1
Bytes:
Cycles:
2
Encoding:
11
Operation:
MOVX
(A)-«DPTR»
01 0 0 0 01
MOVX
@Ri,A
Bytes:
1
Cycles:
2
Encoding:
11
11 0 0 1
Operation:
MOVX
«Ri»-(A)
3-40
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
MOVX @DPTR,A
Bytes:
1
Cycles:
2
Encoding:
Operation:
MUL
11
1 1 1
I° ° ° °
MOVX
(DPTR»..-- (A)
A
Function:
Description:
Example:
Multiply
MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order
byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (OFFH) the overflow flag is set; otherwise it is cleared. The carry flag is
always cleared.
Originally the accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH). The instruction,
MUL
AB
will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the accumulator is
cleared. The overflow flag is set, carry is cleared.
Bytes:
Cycles:
1
4
Encoding:
I'-_1_0_ _0.....J1,-0__
1 _0_0......1
Operation:
MUL
(B) 15-8"-- (A) X (B)
(A) 7-0
NOP
Function:
Description:
Example:
No Operation
Execution continues at the following instruction. Other than the PC, no registers or flags are affected.
It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. A simple
SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must be inserted.
This may be done (assuming no interrupts are enabled) with the instruction sequence,
CLR
NOP
NOP
NOP
NOP
SETB
P2.7
P2.7
Bytes:
Cycles:
° ° ° °I° ° ° °
Encoding:
I
Operation:
NOP
(PC)~(PC)
+1
3-41
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
ORL
Function:
Description:
Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the results
in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the
destination is a direct address, the source can be the accumulator or immediate data.
Example:
Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.
If the accumulator holds OC3H (11000011B) and RO holds 55H (01010101B) then the instruction,
.ORL
A,RO
will leave the accumulator holding the value OD7H (11010111B).
When the destination is a directly addressed byte, the instruction can set combinations of bits in any
RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which
may be either a constant data value in the instruction or a variable computed in the accumulator at runtime. The instruction,
ORL
Pl,#00I1001OB
will set bits 5,4, and 1 of output port 1.
ORL
A,Rn
Bytes:
Cycles:
Encoding:
L..1_o_ _o__o--,-ll__r_r_r--l
Operation:
ORL
(A)"-(A) V (Rn)
ORL
A,direct
Bytes:
2
Cycles:
1
Encoding:
Operation:
ORL
1
0 01 0
0
direct address
ORL
(A)..-(A) V (direct)
A,@Ri
Bytes:
Cycles:
Encoding:
0
0 01 0
1
Operation:
i
I
ORL
(A)~(A)
ORL
0 11
V «Ri»
A,#data
Bytes:
2
Cycles:
1
Encoding:
1
0
1 0 01 0
1 0 01
immediate data
3·42
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Operation:
ORL
V #data
direct,A
Bytes:
2
Cycles:
1
Encoding:
Operation:
ORL
ORL
(A)'-(A)
1_0
..... __0_0--'-1_0_0_1_0. . .1
Operation:
ORL
(direct).-(direct) V (A)
1_0___0_0-,-'_0__0_1_1. . 1. I direct addr.
.....
immediate data
I
V #data
C,
Function:
Description
Example:
Logical-OR for bit variables
Set the carry flag if the Boolean value is a logical I; leave the carry in its current state otherwise. A slash
("I") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected.
Set the carry flag if and only if Pl.O = 1, ACe. 7 = 1, or OV = 0:
MOV C,Pl.O
ORL C,ACe.7
ORL C,IOV
C,bit
Bytes:
Cycles:
Encoding:
Operation:
C,/bit
Bytes:
Cycles:
Encoding:
Operation:
°
; LOAD CARRY WITH INPUT PIN PI
;OR CARRY WITH THE ACe. BIT 7
:OR CARRY WITH THE INVERSE OF OV
2
2
10
11° ° 1 01
I bit address I
ORL
(C)~(C)
ORL
I
ORL
(direct)~ (direct
ORL
direct address
direct,#data
Bytes:
3
Cycles:
2
Encoding:
ORL
1
V (bit)
2
2
11 °
01 0 ° ° 01
1bit address I
ORL
(C)~(C)
V I(bit)
3·43
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
POP
direct
Pop from stack
The contents of the internal RAM location addressed by the stack pointer is read, and the stack
pointer is decremented by one. The value read is the transfer to the directly addressed byte
indicated. No flags are affected.
The stack pointer originally contains the value 32H, and internal RAM locations 30H through 32H
contain the values 20H, 23H, and 01H, respectively. The instruction sequence,
Function:
Description:
Example:
POP
POP
DPH
DPL
will leave the stack pointer equal to the value 30H and the data pointer set to 0123H. At this point
the instruction,
POP
Bytes:
Cycles:
will leave the stack pointer set to 20H. Note that in this special case the stack pointer was
decremented to 2FH before being loaded with the value popped (20H).
2
2
Encoding:
Operation:
PUSH
SP
0110
° ° 01
1 direct address
POP
(direct).-- «SP»
(SP) ~(SP) - 1
direct
Function:
Description:
Example:
Push onto stack
The stack pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected.
On entering an interrupt routine the stack pointer contains 09H. The data pointer holds the value
0123H. The instruction sequence,
PUSH
PUSH
DPL
DPH
will leave the stack pointer set to OBH and store 23 Hand 01 H in internal RAM locations OAH and
OBH, respectively.
Bytes:
Cycles:
2
2
Encoding:
1-1_1_ _0_0--1-1_0_o_o_0--JI
Operation:
PUSH
(SP)'-(SP) + 1
«SP».--(direct)
direct address
3-44
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
RET
Function:
Description:
Example:
Return from subroutine
RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the stack
pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected.
The stack pointer originally contains the value OBH. Internal RAM locations OAH and OBH contain
the values 23H and 01 H, respectively. The instruction,
RET
will leave the stack pointer equal to the value 09H. Program execution will continue at location 0123H.
Bytes:
Cycles:
Encoding:
Operation:
1
2
1_o_o
....
__o_l,-o_O__I_0...J1
RET
(PC 15-8)'-((SP»
(SP).-(SP) - 1
(PC 7-0)'-( (SP»
(SP)~SP) - 1
RETI
Function:
Description:
Example:
Return from interrupt
RET! pops the high- and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack
pointer is left decremented by two. No other registers are affected; the PSW is not automatically
restored to its pre-interrupt status. Program execution continues at the resulting address, which is
generally the instruction immediately after the point at which the interrupt request was detected. If a
lower- or same-level interrupt had been pending when the RET! instruction is executed, that one instruction will be executed before the pending interrupt is processed.
The stack pointer originally contains the value OBH. An interrupt was detected during the instruction
ending at location 0122H. Internal RAM locations OAH and OBH contain the values 23H and 01H,
respectively. The instruction,
RET!
Bytes:
Cycles:
Encoding:
Operation:
will leave the stack pointer equal to 09H and return program execution to location 0123H.
1
2
1_0_0_ _--'-10__
.....
0_1_0.. J1
RETI
(PCI5-8)~«SP»
(SP)~(SP) - i
(PC7 _O)~ «SP»
.(SP~(SP) - 1
3-45
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
Rl
A
Function:
Description:
Example:
Rotate accumulator Left
The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No
flags are affected.
The accumulator holds the value OC5H (11000101B). The instruction,
RL
Bytes:
Cycles:
A
leaves the accumulator holding the value 8BH (10001011B) with the carry unaffected.
1
1
Encoding:
10 0
1 010
Operation:
RL
(An+
})~(An)
0
1
n=0-6
(AO~(A7)
RLC
A
Function:
Description:
Example:
Rotate accumulator Left through the Carry flag
The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected.
The accumulator holds the value OC5H (11000101 B), and the carry is zero. The instruction,
RLC
Bytes:
Cycles:
A
leaves the accumulator holding the value 8BH (1 000 10 lOB) with the carry set.
1
1
Encoding:
L.1_O_O_ _l_L..IO__
O_I_......J
Operation:
RLC
(An +
t)~
(An)
n=0-6
(AO)~(C)
(C)'-(A7)
RR
A
Function:
Description:
Example:
Rotate accumulator Right
The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected.
The accumulator holds the value OC5H (11000101B). The instruction,
A
RR
Bytes:
Cycles:
Encoding:
Operation:
leaves the accumulator holding the value OE2H (1110001OB) with the carry unaffected.
1
1
I0
0
0
I
0 0
0
1
RR
(An)~(An
+ I)
n=0-6
(A7)~(AO)
3-46
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
RRC
A
Rotate accumulator Right through Carry flag
The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0
moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other
flags are affected.
The accumulator holds the value OC5H (11000101B), the carry is zero. The instruction,
Function:
Description:
Example:
RRC
A
leaves the accumulator holding the value 62 (011000IOB) with the carry set.
1
1
Bytes:
Cycles:
I
Encoding:
I0
Operation:
RRC
(An)'-(An + I)
0 0
1 0 0
1
n=0-6
(A7)~(C)
(C)..-(AO)
SETB
Function:
Description:
Example:
Set Bit
SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable
bit. No other flags are affected.
The carry flag is cleared. Output port 1 has been written with the value 34H (00110100B). The instructions,
SETB
SETB
C
Pl.O
will leave the carry flag set to 1 and change the data output on port 1 to 35H (00110101B).
SETB
C
Bytes:
Cycles:
Encoding:
Operation:
11
0
I
I
1 0 0
1 1
1 10 0
1 01
SETB
(C)~1
SETB
bit
Bytes:
Cycles:
2
0
Encoding:
11
Operation:
SETB
(bit)-1
Ibit address
3-47
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
SJfv1P
ial
Function:
Description:
Example:
Short Jump
Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.
The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction,
SJMP
RELADR
will assemble into location OlOOH. After the instruction is executed, the PC will contain the value
0123H.
Bytes:
Cycles:
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore, the
displacement byte of the instruction will be the relative offset (OI23H-0102H) = 21 H. Put another
way, an SJMP with a displacement of OFEH would be a one-instruction infinite loop.)
2
2
Encoding:
11 0 0 010 0 0 0
Operation:
SJMP
(PC~(PC)
(PC)~(PC)
SUBB
I reI. address
+ 2
+ reI
A,
Function:
Description:
Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the
result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and
clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow
was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from
the accumulator along with the source operand.) AC is set if a borrow is needed for bit 3, and
cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not
bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative value is
subtracted from a positive value, or a positive result when a positive number is subtracted from a
negative number.
Example:
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.
The accumulator holds OC9H (11001001B), register 2 holds 54H (01010100B), and the carry flag is
set. The instruction,
SUBB
A,R2
will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV
set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due to the
carry (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by a CLR C instruction.
3·48
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
SUBB
A,Rn
Bytes:
Cycles:
Encoding:
11
0
0
1 11
r
r
r ]
Operation:
SUBB
(A)..-(A) - (C) - (Rn)
SUBB
A,direct
Bytes:
2
Cycles:
0
Encoding:
11
Operation:
SUBB
0
(A)~(A)
I
1 0
1 0
1
I
I direct address
- (C) - (direct)
SUBB
A,@Ri
Bytes:
Cycles:
0
0
I
1 0
i
I
Encoding:
11
Operation:
SUBB
(A)...--(A) - (C) - «Ri»
SU B B
A,#data
Bytes:
2
Cycles:
1
Encoding:
11
0
Operation:
SUBB
(A)~
SWAP
0
I
1 0
1 0
0
I
I immediate data I
(A) - (C) - #data
A
Function:
Description:
Example:
Swap nibbles within the Accumulator
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the accumulator (bits 3-0
and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No flags are affected.
The accumulator holds the value OC5H (11000101 B). The instruction,
SWAP
Bytes:
Cycles:
A
leaves the accumulator holding the value 5CH (01011100B).
1
Encoding:
11
1 0
Operation:
SWAP
0
I
0
1 0
0
I
(A3-0)~(A7-4), (A7-4)~(A3-0)
3-49
AFN-01739A
MEMORY, ADDRESSING, INSTRUCTION SET
XCH
A,
Function:
Description:
Example:
Exchange Accumulator with byte variable
XCH loads the accumulator with the contents of the indicated variable, at the same time writing the
original accumulator contents to the indicated variable. The source/destination operand can use
register, direct, or register-indirect addressing.
RO contains the address 20H. The accumulator holds the value 3FH (00111111 B). Internal RAM
location 20H holds the value 75H (01110101B). The instruction,
XCH
A,@RO
will leave RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in the accumulator.
XCH
A,Rn
Bytes:
Cycles:
Encoding:
Operation:
1...._1_ _0
__0-'-11__r_r_r--l
XCH
(A). ·(Rn)
XCH
A,direct
Bytes:
2
Cycles:
1
Encoding:
1L...-1 _ _O_ 0--L..1_0_1_0_1-.J1
Operation:
XCH
Idirect address
(A)~ (direct)
A,@Ri
XCH
Bytes:
Cycles:
Encoding:
Operation:
XCHD
1_1
.... _ _0__
0......I_o____i .....1
XCH
(A)~«Ri»
A,@Ri
Function:
Description:
Example:
Exchange Digit
XCHD exchanges the low-order nibble of the accumulator (bits 3-0),generally representing a hexadecimal or BCD digit) with that of the internal RAM location indirectly addressed by the specified
register. The high-order nibbles (bits 7-4) of each register are not affected. No flags are affected.
RO contains the address 20H. The accumulator holds the value 36H (00110110B). Internal RAM
location 20H holds the value 75H (01110101 B). The instruction,
XCHD
A,@RO
will leave RAM location 20H holding the value 76H (0111011OB) and 35H (00110101B) in the accumulator.
Bytes:
Cycles:
Encoding:
Operation:
1
11 1
° I°
XCHD
(A3-0)~«Ri3-0»
3-50
AFN·01739A
MEMORY, ADDRESSING, INSTRUCTION SET
XRL
,
Function:
Description:
Logical Exclusive-OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing
the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the
destination is a direct address, the source can be the accumulator or immediate data .
Example:
.(Note: When this instruction is used to modify an output port, the value used as the original port
data will be read from the output data latch, not the input pins.)
If the accumulator holds OC3H (llOOOOIIB) and register 0 holds OAAH (lOlOlOlOB) then the instruction,
XRL
A,RO
will leave the accumulator holding the value 69H (01 101001 B).
When the destination is a directly addressed byte, this instruction can complement combinations of
bits in any RAM location or hardware register. The pattern of bits to be complemented is then
determined by a mask byte, either a constant contained in the instruction or a variable computed in
the accumulator at run-time. The instruction,
XRL
Pl,#OOllOOOIB
will complement bits 5, 4, and 0 of output port 1.
XRL
A,Rn
Bytes:
Cycles:
Encoding:
....
1_O____0---LI_l_r__r_r-J
Operation:
XRL
(A)~(A)
XRL
Encoding:
Operation:
XRL
1
0
01 0
1
0
11
direct address
XRL
(A).-(A) EB (direct)
A,@Ri
Bytes:
Cycles:
Encoding:
Operation:
I0
A,#data
Bytes:
Cycles:
Encoding:
01 0
i I
XRL
(A)~(A)
XRL
EB (Rn)
A,direct
Bytes:
2
Cycles:
EB «Ri»
2
1
0
01 0
1
0 01
I immediate data
3-51
AFN-017:1~A
MEMORY, ADDRESSING, INSTRUCTION SET
Operation:
XRL
(A)~
XRL
direct,A
Bytes:
2
Cycles:
Encoding:
Operation:
XRL
(A) EB #data
0____0_11-°__0_1_°-11
1-1
1
direct address
1
XRL
(direct)..- (direct) EB (A)
direct,#data
Bytes:
3
Cycles:
2
Encoding:
L.. 1_O____0..J.I_O_O__1_~
Operation:
XRL
(direct)~
Idirect address
1 immediate data 1
(direct) EB #data
3-52
AFN-01739A
I
!
I
I'
'I
Chapter 4
EXPANDED 8051 FAMILY
This chapter shows in very general terms some basic
circuits for expanding the 8051 Family. As the product
matures and Intel tests specific circuits, the User
Manual will be updated. Also application notes wiII be
published to help show actual, tested circuits designed
by Intel personnel. The schematics included in this
chapter should give the designer an insight into connecting external peripherals and memories to the 8051.
AFN-01739A
4-1
EXPANDED 8051 FAMILY
Figure 4·1. The Standalone 8051
AFN-01739A
4·2
EXPANDED 8051 FAMILY
+5V
+ 5V
40
Vee
:~~ !~
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
D
18 XTAL 2
9
>----.----+1 RESET/VPD
5
6
7
8
P40
P41
P42
P43
2
3
4
5
P50
P51
P52
P53
1
23
22
21
P20
P21
P22
P23
P60
P61
P62
P63
20
19
18
17
PROG
13
P70 14
P71
}I/O
8243
1/0
EXPANDER
110
8051
8751
11
10
9
8
7
31 _
'------10-1 EAIVDD
10
11
12
13
14
15
16
17
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
P72
P73
;~
37
36
35
34
33
32
Any 110 Port Pins can be used.
~~
1/0
The following software driver is required to
Interface to the 8243.
Mixing Parallel Output. Input. and
Control Strobes on Port 2
;IN8243
INPUT DATA FROM AN 82431/0 EXPANDER
CONNECTED TO P23·P20
P25 & P24 MIMIC CSI & PROG
P27·P26 USED AS INPUTS
PORT TO BE READ IN ACC
IN8243:
ORL
MOV
CLR
ORL
MOV
SETB
A,'11010000B
P2,A
;OUTPUT INSTRUCTION CODE
P2,4
;FALLING EDGE OF PROG
,SET FOR INPUT
P2, '00001111 B
A,P2
;READ INPUT DATA
P2,4
;RETURN PROG HIGH
Figure 4·2. 110 Expansion Using an 8243
AFN-01739A
4-3
EXPANDED 8051 FAMILY
+5V
40
Vee
lo
lo
lo
P~RT
8051
8751
-=
9
RESETIVpo
P0 RT
2
31
EAIVOO
~~
,{
12
13
14
15
16
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
17
:~:~
RT
P'1
(Any 110 Port Line Can Be Used)
Additional Inputs
3
L-t-+---.::t 08
16
+5V
Voo
8v~
Serial 11
3
In,...-----1"'"'6 08
CD4014
CMOS SHIFT REG.
+5V
8 voo
v~
11
CD4014
CMOS SHIFT REG.
'-------------+-----------,---------4- - - - -- - - --
Figure 4·3. Expanding Input Lines via Serial Port
4-4
AFN-01739A
EXPANDED 8051 FAMILY
+5V
40
VCC
D
8051
8751
=
RESETIVPO
31 _
EAIVOO
,,{
10
11
12
13
14
15
16
17
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
1
2
3
4
5
6
7
8
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
(RXO)
(TXO)
(INTO)
(INT1)
(TO)
lo
lo
lo
P0 RT
1
P~RT
POORT
(T1)
(WR)
(RD)
29
(Any I/O Port Line Can Be Used)
Additional Outputs
~1~0______~2~OATA
2
L-f-+--~OATA
+5V
16 VOO
8 Vss
CD4094
CMOS SHIFT REG.
+5V
OE 15
16 VOO
8 Vss
CD4094
CMOS SHIFT REG.
OE 15
Figure 4·4. Expanding Output Lines via Serial Port
4·5
AFN-01739A
+5V
r
40
Vee
.J:>,
m
+5
805
for
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
8031
8051
8751
31 _
EAIVDD
{~
~
~.
PO.2
PO.3
PO.4
PO.5
PO.6
PO.?
(fNT1)
(TO)
(T1)
(WR)
(AD)
ALE/PROG
30
.---
DIO
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DOO
D01
D02
D03
D04
D05
D06
D07
8282
Vee
112
Vpp
L~
-
STB
110
CE
-
; A2
8 A1
Ao
A8~
A9~
2716
m
><
»
"z
~
"'T1
1~
11
13
14
15
16
17
;~
35
34
33
32
»
3:
00
01
02
03
04
05
06
07
r-
-<
6E
20
----
~
U'I
t
1
-
A10
co
o
6E
1
-
A7
A6
A5
A4
A3
c
PSEN
29
-
1
2
3
4
5
m
c
-------------
-
-
-
-
-
For 8751, 8051 CE of the 2716 must be
driven by P2.4 through an inverter
»
-n
Z
~»
1,,,
~
GND
PO.O 39
PO.1 38
(RXD)
(TXD)
(INTO)
1
I/O
~
~
~}
8751,
IGND
I/O
t=}
t=
21
P2.0
22
P2.1
23
P2.2
P2.3
P2.4
P2.5 ~
P2.6 ~
P2.7 ~.
RESET/VPD
P3.0
P3.1
~ P3.2
~ P3.3
~ P3.4
--l§ P3.5
~ P3.6
_-17 P3.7
20
Vee
VSS
XTAL 2
9
'"..
[l:
XTAL 1
~
+(
Figure 4·5. External Program Memory Using a 2716
I
+5V
~
40
Vee
~
~
+5
805
for
~
8031
8051
8751
P2.0
P2.1
P2.2
P2.3
P2,4
P2.5
P2.6
P2.7
9
.....
~
P1.0
PU
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
XTAL 2
RESETIVPO
'"
B751.
IGNO
31 _
EAlVoO
I/O
{~
P3.0
~ P3.1
P3.2
~
13
P3.3
~ P3,4
P3.5
P3.6
P3.7
15
16
.:E
(RXO)
(TXO)
(INTO)
(INT1)
(TO)
(T1)
(WR)
PO.O
PO.1
PO.2
PO.3
POA
PO.5
PO.6
PO.7
(RO)
ALE/PROG
30
1
124
GNO
Vee
~l
~
1
2
3
4
5
6
7
~
t=J
~
~.
~
010
011
012
013
014
015
016
017
8282
000
001
002
003
004
19
18
17
16
15
005
~~
~~~
12
1
2
3
4
5
6
A7
A6
A5
A4
A3
l·12
GNO
~
I
I
23
'
A8~
A9~
M
7 A1
8 AO
A10
2732A
~}
~
STB
26
OE
~.
;~
:~
29
s:
r-
-<
OElVpp
20
1
1
-
-
-
-
-
-
-
-----------_._-
~
z
Figure 4·6. External Program Memory Using a 2732
"Z
l>
00
01
02
13
14 03
04
15
05
16
17 06
07
PSEN
><
l>
~
9
37
36
35
34
33
32
~
m
.....
~
1/0
An
r!L-
c
m
c
Q)
o(J'1
23
24
6
~
eE
~
22
For 8751, 8051 CE on 2732A must be
driven by P2.4 through an Inverter.
~
118
I
I
I
Vss
XTAL 1
[1-
+r:
Vee
I
+5V
EXPANDED 8051 FAMILY
+5V
19
40
VCC
20
VSS
-=
P1.0
P1.1
P1.2
P1.3
XTAL 1
CJ
P1.4 ~
P1.5 7
P1.6 8
P1.7
18 XTAL 2
-=
1
2
3
4
8051
8751
~~
P2.0
P2.1 23
P2.2 24
P2.3 25
9
RESETIVPD
:~::
26
P2.6 27
P2.7 28
31 _
EA/VDD
,,{
10
11
12
13
14
15
16
17
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PO.2
;~
GND
20
~:
AD2
16 AD3
17 AD4
18 AD5
:~~
35
PO.5 34
PO.6 33
PO.7 32
(WR)
(RO) _ _
+ 5V
12 ADO
13 AD1
PO.O 39
PO.1 38
(RXD)
(TXD)
(INTO)
(INT1)
(TO)
(T1)
ALE/PROG
30
Jo
}o
19
PSEN
29
~~~
8155
256 x 8
RAM
101M
9_
RD
10_
WR
11
ALE
PAO
PA1
PA2
PA3
PM
PA5
PA6
PA7
21
22
23
24
25
26
27
28
PCO
PC1
PC2
PC3
PC4
PC5
37
38
39
1
2
5
PBO
PB1
PB2
PB3
29
30
31
32
110
~~
PB4
PB5 35
::~
36
CAN BE SUPPLIED BY SYSTEM RESET L....--.:;:.;r.~--..:r:::----'
OR PORT LINE OF 8051
• Both I/O and RAM are addressed as data memory.
• Writing a bit to P2.0 determines whether RAM or I/O is to be accessed.
Figure 4·7. Adding a Data Memory and 110 Expander
4·8
AFN·01739A
EXPANDED 8051 FAMILY
EXTERNAL
2581-------1
2571-------1
2561-------1
255
4095
INTERNAL
0
0
PROGRAM
MEMORY
21 A8
22 A9
23 A10
EXTERNAL
DATA
MEMORY
+5V
+5V
GND
I
I
I
I
VCC
VDD
VSS
CE
GND
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
+5V
[l
40
r
Vee
VSS
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
XTAL 1
CJ
~
XTAL2
8051
8751
RESETIVPD
+5 V for 8751,
805 1, and GND
for 8031
31 _
EAIVDD
{~
::::::U
P3.0
P3.1
12
P3.2
P3.3
P3.4
P3.5
-~
16 P3.6
P3.7
110
-.J4
,.--1Z
PO.O
PO.1
PO.2
PO.3
PO.4
P05
PO.6
PO.7
(RXD)
(TXD)
(INTO)
(INT1)
(TO)
(T1)
(WR)
(AD)
ALEIPROG
30
"-l
~
~
t=J
12
13
14
15
16
17
18
19
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD?
8755A
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
8 _
lOR
~9
iL-
~
~
lOW
_
RD
~
~
~
~
~
~
~
~
~
~
I/O
a-
~
ALE
2_
CE
RESET
P2.0 ~
22
P2.1
23
P2.2
P2.3 ~IIO
25
P2.4
P2.5 ~--,
P2.6 ~IIO
P2.7 ~--1
9
-1.l
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.?
~
~
~
~
~
~4
~
12
13
14
15
16
17
18
19
PSEN
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
7
NC
+r
G,D
20
Vec
VSS
40
39 ADO
38 AD1
37 AD2
36 AD3
35 AD4
34 AD5
33 AD6
32 AD7
16
[3
NC
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
8155
PCO
PC1
PC2
PC3
PC4
PC5
9 _
RD
10_
WR
11
ALE
8-
For 8031 P2.4 should connect
to Pin 1 (CE) of 8755
CE
CAN BE SUPPLIED BY
SYSTEM RESET OR PORT LINE OF 8051
~
lL
~
~
~
~
~
~
-
101M
f29
~
RESET
'i'iME"R
TIMER
IN
OUT
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
a~
~
~
110
~
~
~
~
~
~
~
~
~
~
P
.6
i
TIMER
Figure 4·8. The Three·Chip System
4-9
AFN·01739A
EXPANDED 8051 FAMILY
+5V
40
Vee
XTAL 1
CJ
8031
8051
8751
-=
RESET/VPD
+5V for 8751.
8051. and GND
for 8031
I/O
31 _
EA/VDD
,,{
10
11
12
13
14
15
16
17
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
29
+5V
40
Vee
0
8031
8051
8751
-=
Pl.0
Pl.1
P1.2
Pl.3
Pl.4
P1.5
P1.6
PH
1
2
3
4
5
6
7
8
RESETIVPD
+5V for 8751.
8051. and GND
for 8031
I/O
31 _
EAIVDD
I
I
I
I
I
I
I
I
I
I Asynchronous
:
Line
"o{
10
11
12
13
14
15
16
17
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Figure 4·9. Multiple 8051'5 Using Half·Duplex Serial Communication
4·10
AFN-01739A
EXPANDED 8051 FAMILY
+5V
40
VCC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
1
2
3
4
5
6
7
8
31 EAIVDD
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
39
38
37
36
35
34
33
32
D
8051
8751
-=
RESET/VPD
OPEN
COLLECTOR
INVERTERS
DEVICE
1
+ 5V
1/0-[
,,{
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
(RXD)
(TXD)
(iNfO)
(lNT1)
(TO)
(T1)
(WR)
(AD)
ALE/PROG
I/O
29
-All devices equal priority
-Processor polls Port 0 to determine interrupting device
Figure 4·10. Multiple Interrupt Sources
4·11
AFN-01739A
I
11
I
,
"
li,l
i
I
CHAPTER 5
8051 SOFTWARE ROUTINES
8051 PROGRAMMING TECHNIQUES
Chapter 5 contains two sections:
• 8051 Programming Techniques
• Peripheral Interfacing Techniques
The first section has 8051 software examples for some
common routines in controller applications. Some
routines included are multiple-precision arithmetic and
table look-up techniques.
Radix Conversion Routines
The divide instruction can be used to convert a number
from one radix to another. BINBCD is a short
subroutine to convert an eight-bit unsigned binary integer in the accumulator (between 0 & 255) to a threedigit (two byte) BCD representation. The hundred's
digit is returned in one variable (HUND) and the ten's
and one's digits returned as packed BCD in another
(TENONE).
Peripheral Interfacing Techniques include routines for
handling the 8051 's 110 ports, serial channel and
timer/counters. Discussed in this section is 110 port
reconfiguration, software delay timing, and transmitting serial port character strings along with other
routines.
,
;BINBCD
CONVERT 8·BIT BINARY VARIABLE IN ACCUMULATOR
TO 3·DIGIT PACKED BCD FORMAT.
HUNDREDS' PLACE LEFT IN VARIABLE 'HUND',
TENS' AND ONES' PLACES IN 'TENONE'.
,
HUND
TENONE
DATA
DATA
21H
22H
MOV
DIV
MOV
MOV
XCH
DIV
B,#100
AB
HUND,A
A,#10
A,B
AB
SWAP
ADD
MOV
RET
A
A,B
TENONE,A
,
BINBCD:
;DIVIDED BY 100 TO
;DETERMINE NUMBER OF HUNDREDS
;DIVIDE REMAINDER BY TEN TO
;DETERMINE NUMBER OF TENS LEFT
;TEN'S DIGIT IN ACC, REMAINDER IS
;ONE'S DIGIT
;PACK BCD DIGITS IN ACC
the digits can be processed individually. This example
receives two packed BCD digits in the accumulator,
separates the digits, computes their product, and returns
the product in packed BCD format in the accumulator.
The divide instruction can also separate data in the accumulator into sub-fields. For example, dividing packed
BCD data by 16 will separate the two nibbles, leaving
the high-order digit in the accumulator and the loworder digit (remainder) in B. Each is right-justified, so
,
;MULBCD
UNPACK TWO BCD DIGITS RECEIVED IN ACCUMULATOR,
FIND THEIR PRODUCT, AND RETURN PRODUCT
IN PACKED BCD FORMAT IN ACCUMULATOR
5-1
8051 SOFTWARE ROUTINES
iviUi..BCD:
..,,"
IYIVY
a U1nu
u,rr • "I'
DIV
AB
MUL
AB
MOV
DIV
B,#10
AB
SWAP
ORL
RET
A
A,B
;D!V!DE !NPUT BY 16
;A & B HOLD SEPARATED DIGITS
;(EACH RIGHT JUSTIFIED IN REGISTER).
;A HOLDS PRODUCT IN BINARY FORMAT (0·
;99 (DECIMAL) = 0 - 63H)
;DIVIDE PRODUCT BY 10
;A HOLDS NUMBER OF TENS, B HOLDS
;REMAINDER
;PACK DIGITS
Multiple Precision Arithmetic
The AD DC and SUBB instructions incorporate the
previous state of the carry (borrow) flag to allow
mUltiple-precision calculations by repeating the operation with successively higher-order operand bytes. If the
input data for a multiple-precision operation is an unsigned string of integers, the carry flag will be set upon
completion if an overflow (for ADDC) or underflow
(for SUBB) occurs. With two's complement signed data,
the most significant bit of the original input data's most
significant byte indicates the sign of the string, so the
overflow flag (OV) will indicate if overflow or
underflow occurred.
,
;SUBSTR
,
SUBSTR:
SUBS1:
SUBTRACT STRING INDICATED BY R1
FROM STRING INDICATED BY RO TO
PRECISION INDICATED BY R2.
CHECK FOR SIGNED UNDERFLOW WHEN DONE.
CLR
MOV
SUBB
MOV
INC
INC
DJNZ
C
A,@RO
A,@R1
@RO,A
RO
R1
R2,SUBS1
;BORROW =0.
;LOAD MINUEND BYTE
;SUBTRACT SUBTRAHEND BYTE
;STORE DIFFERENCE BYTE
;BUMP POINTERS TO NEXT PLACE
;LOOP UNTIL DONE
WHEN DONE, TEST IF OVERFLOW OCCURRED
ON LAST ITERATION OF LOOP.
JNB
OV,OV_OK
OV·OK: RET
(OVERFLOW RECOVERY ROUTINE)
;RETURN
Table Look-Up Sequences
The two versions of the MOVC instructions are used as
part of a three-step sequence to access look-up tables in
ROM. To use the DPTR version, load the Data Pointer
with the starting address of a look-up table; load the accumulator with (or compute) the index of the entry
desired; and execute MOVC A,@A+DPTR. The data
pointer may be loaded with a constant for short tables,
or to allow more complicated data structures, and tables
with more than 256 entries, the values for DPH and
DPL may be computed or modified with the standard
arithmetic instruction set.
significant. Again, a look-up sequence takes three steps:
load the accumulator with the index; compensate for the
offset from the look-up instruction's address to the start
of the table by adding that offset to the accumulator;
then execute the MOVC A,@A+PC instruction.
As a non-trivial situation where this instruction would
be used, consider applications which store large multidimensional look-up tables of dot matrix patterns, nonlinear calibration parameters, and so on in the linear
(one-dimensional) program memory. To retrieve data
from the tables, variables representing matrix indices
must be converted to the desired entry's memory address. For a matrix of dimensions (MDIMEN x
NDIMEN) starting at address BASE and respective indices INDEXI and INDEXJ, the address of element
The PC-based version is used with smaller, "local"
tables, and has the advantage of not affecting the data
pointer. This makes it useful in interrupt routines or
other situations where the DPTR contents might be
5-2
AFN-01739A
8051 SOFTWARE ROUTINES
the assembly object code as part of the accessing
subroutine itself.
(lNDEXI, INDEXl) is determined by the formula,
Entry Address = [BASE + (NDIMEN x INDEXI) +
INDEXl]
To handle the more general case, subroutine MATRX2
allows tables to be unlimited in size, by combining the
MUL instruction, double-precision addition, and the
data pointer-based version of MOVe. The only restriction is that each index be between 0 and 255.
The subroutine MATRXI can access an entry in any array with less than 255 elements (e.g., an 11x21 array
with 231 elements). The table entries are defined using
the Data Byte ("DB") directive, and will be contained in
,
;MATRX1
LOAD CONSTANT READ FROM TWO DIMENSIONAL LOOK·UP
TABLE IN PROGRAM MEMORY INTO ACCUMULATOR
USING LOCAL TABLE LOOK·UP INSTRUCTION, 'MOVC A,@A+PC'.
THE TOTAL NUMBER OF TABLE ENTRIES IS ASSUMED TO
BE SMALL, I.E. LESS THAN ABOUT 255 ENTRIES.
TABLE USED IN THIS EXAMPLE IS 11 x 21.
DESIRED ENTRY ADDRESS IS GIVEN BY THE FORMULA,
[(BASE ADDRESS) + (21 X INDEXI) + (INDEXJ)]
,
INDEXI
INDEXJ
Eau
DATA
R6
23H
;FIRST COORDINATE OF ENTRY (0·10).
;SECOND COORDINATE OF ENTRY (0·20).
MOV
MOV
MUL
ADD
A,INDEXI
B, #21
AB
A,INDEXJ
;(21 X INDEXI)
;ADD IN OFFSET WITHIN ROW
,
MATRX1:
ALLOW FOR INSTRUCTION BYTE BETWEEN "MOVC" AND
ENTRY (0,0).
BASE1:
MATRX2:
INC
MOVC
RET
DB
DB
A
A,@A+PC
1
2
;(entry 0,0)
;(entry 0,1)
DB
DB
21
22
;(entry 0,20)
;(entry 1,0)
DB
42
;(entry 1,20)
DB
MOV
MOV
MUL
ADD
MOV
MOV
ADDC
MOV
MOV
MOVC
RET
231
A,INDEXI
B,#NDIMEN
AB
A,#LOW(BASE2)
DPL,A
A,B
A,#HIGH(BASE2)
DPH,A
A,INDEXJ
A,@A+DPTR
;(entry 10,20)
;LOAD FIRST COORDINATE
:INDEXI X NDIMEN
;ADD IN 16·BIT BASE ADDRESS
;DPTR=(BASE ADDR) + (INDEXI+NDIMEN)
;ADD INDEXJ AND FETCH BYTE
5·3
8051 SOFTWARE ROUTINES
BASE2:
DB
·t
.... +r" n
n\
,\-.wl"'.,
"',""'/
DB
0
0
;(entry 0,1)
DB
DB
0
0
;(entry 0, NDIMEN·1)
;(entry 1,0)
DB
0
;(entry 1, NDIMEN·1)
DB
0
;(entry MDIMEN·1, NDIMEN·1)
Saving CPU Status during Interrupts
When the 8051 hardware recognizes an interrupt request, program control branches automatically to the
corresponding service routine, by forcing the CPU to
process a Long CALL (LCALL) instruction to the appropriate address. The return address is stored on the
top of the stack. After completing the service routine,
an RETI instruction returns the processor to the
background program at the point from which it was interrupted.
second method of 110 port reconfiguration.) Resources
used or altered by the service routine (Accumulator,
PSW, etc.) must be saved and restored to their previous
value before returning from the service routine. PUSH
and POP provide an efficient and convenient way to
save such registers on the stack.
If the SP register held 1FH when the interrupt was
detected, then while the service routine was in progress
the stack would hold the registers shown in Figure 5-1;
SP would contain 26H. This is the most general case; if
the service routine doesn't alter the B-register and data
pointer, for example, the instructions saving and restoring those registers could be omitted.
Interrupt service routines must not change any variable
or hardware registers modified by the main program, or
else the program may not resume correctly. (Such a
change might look like a spontaneous random error. An
example of this will be given later in this section, in the
,
LOC_TMP
SERVER:
EQU
$
;REMEMBER LOCATION COUNTER
ORG
LJMP
0003H
SERVER
;STARTING ADDRESS FOR INTERRUPT ROUTINE
;JUMP TO ACTUAL SERVICE ROUTINE LOCATE
;ELSEWHERE
ORG
PUSH
PUSH
LOC_TMP
PSW
ACC
;RESTORE LOCATION COUNTER
PUSH
PUSH
PUSH
MOV
B
DPL
DPH
PSW,#00001000B
POP
POP
POP
POP
POP
DPH
DPL
B
ACC
PSW
RETI
;SAVE ACCUMULATOR (NOTE DIRECT ADDRESS
;NOTATION)
;SAVE B REGISTER
;SAVE DATA POINTER
,
;SELECT REGISTER BANK 1
;RESTORE REGISTERS IN REVERSE ORDER
;RESTORE PSW AND RE·SELECT ORIGINAL
;REGISTER BANK
;RETURN TO MAIN PROGRAM AND RESTORE
;INTERRUPT LOGIC
5-4
. AFN·01739A
8051 SOFTWARE ROUTINES
Passing Parameters on the Stack
RAM
ADDR
The stack may also pass parameters to and from
subroutines. The subroutine can indirectly address the
parameters derived from the contents of the stack
pointer, or simply pop the stack into registers before
processing.
7FH
One advantage here is simplicity. Variables need not be
allocated for specific parameters, a potentially large
number of parameters may be passed, and different
calling programs may use different techniques for determining or handling the variables.
ASCTBL:
MOV
DEC
DEC
XCH
ANL
ADD
MOVC
XCH
RET
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
RO,SP
RO
RO
A,@RO
A,#OFH
A,#2
A,@A+PC
A,@RO
'0'
'1 '
'2'
'3'
'4'
'5'
'6'
'7'
'8'
'9'
'A'
'B'
'c'
'D'
'E'
'F'
DPH
DPL
24H
B
23H
ACC
22H
PSW
21H
PC (HIGH)
20H
PC (LOW)
_(SP)
1FH
For example, the subroutine HEXASC converts a hexadecimal value to ASCII code for its low-order digit. It
first reads a parameter stored on the stack by the calling
program, then uses the low-order bits to access a local
16-entry look-up table holding ASCII codes, stores the
appropriate code back in the stack and then returns.
The accumulator contents are left unchanged.
HEXASC:
26H
25H
OOH
Figure 5-1. Stack contents during interrupt
;ACCESS LOCATION PARAMETER PUSHED INTO
;READ INPUT PARAMETER AND SAVE ACCUMULATOR
;MASK ALL BUT LOW-ORDER 4 BITS
;ALLOW FOR OFFSET FROM MOVC TO TABLE
;READ LOOK-UP TABLE ENTRY
;PASS BACK TRANSLATED VALUE AND RESTORE
;ACCUMULATOR
;RETURN TO BACKGROUND PROGRAM
;ASCII CODE FOR OOH
;ASCII CODE FOR 01 H
;ASCII CODE FOR 02H
;ASCII CODE FOR 03H
;ASCII CODE FOR 04H
;ASCII CODE FOR 05H
;ASCII CODE FOR 06H
;ASCII CODE FOR 07H
;ASCII CODE FOR 08H
;ASCII CODE FOR 09H
;ASCII CODE FOR OAH
;ASCII CODE FOR OBH
;ASCII CODE FOR OCH
;ASCII CODE FOR ODH
;ASCII CODE FOR OEH
;ASCII CODE FOR OFH
be needed until later. The example below converts the
three-digit BCD value computed in the Radix Conversion example above to a three-character string, calling a
subroutine SP _OUT to output an eight-bit code in the
accumulator.
The background program may reach this subroutine
with several different calling sequences, all of which
PUSH a value before calling the routine and POP the
result to any destination register or port later. There is
even the option of leaving a value on the stack if it won't
5-5
AFN-01739A
8051 SOFTWARE ROUTINES
PUSH
CALL
POP
CALL
PUSH
CALL
HUND
HEXASC
ACC
SP_OUT
TENONE
HEXASC
MOV
SWAP
PUSH
CALL
POP
CALL
POP
CALL
A, TENONE
A
ACC
HEXASC
ACC
SP_OUT
ACC
SP_OUT
;CONVERT HUNDREDS DIGIT
;TRANSMIT HUNDREDS CHARACTER
;CONVERT ONE'S PLACE DIGIT
;BUT LEAVE ON STACK!
;RIGHT·JUSTIFY TEN'S PLACE
;CONVERT TEN'S PLACE DIGIT
;TRANSMIT TEN'S PLACE CHARACTER
;TRANSMIT ONE'S PLACE CHARACTER
N·Way Branching
There are several different means for branching to sections of code determined or selected at run time. (The
single destination addresses incorporated into conditional and unconditional jumps are, of course, fixed at
assembly time.) Each has advantages for different applications.
execution. The instruction adds the eight-bit unsigned
accumulator contents with the contents of the sixteenbit data pointer, just like MOVe A,@A+ DPTR. The
resulting sum is loaded into the program counter and is
used as the address for subsequent instruction fetches.
Again, a sixteen-bit addition is performed: a carry-out
from the low-order eight-bits may propagate through
the higher-order bits. In this case, neither the accumulator contents nor the data pointer is altered.
In a typical N-way branch situation, the potential
destinations are generally known at assembly time. One
of a number of small routines is selected according to
the value of an index variable determined while the program is running. The most efficient way to solve this
problem is with the MOVe and an indirect jump instruction, using a short table of offset values in ROM to
indicate the relative starting addresses of the several
routines.
The example subroutine below reads a byte of RAM into the accumulator from one of four alternate address
spaces, as selected by the contents of the variable
MEMSEL. The address of the byte to be read is determined by the contents of RO (and optionally Rl). It
might find use in a printing terminal application, where
four different model printers all use the same ROM
code but use different types (and sizes) of buffer
memory for different speeds and options.
JMP @A+ DPTR is an instruction which performs an
indirect jump to an address determined during program
,
MEMSEL
EQU
R3
MOV
MOV
MOVC
JMP
DB
DB
DB
DB
MOV
RET
MOVX
RET
MOV
MOV
MOVX
RET
A,MEMSEL
DPTR,#JMPTBL
A,@A+DPTR
@A+DPTR
MEMSPO·JMPTBL
MEMSP1·JMPTBL
MEMSP2·JMPTBL
MEMSP3·JMPTBL
A,@RO
;READ FROM INTERNAL RAM
A,@RO
;READ 256 BYTE EXTERNAL RAM
DPL,RO
DPH,R1
A,@DPTR
;READ 64K BYTE EXTERNAL RAM
,
JUMP_4:
JMPTBL:
MEMSPO:
MEMSP1:
MEMSP2:
5-6
AFN·01739A
8051 SOFTWARE ROUTINES
MEMSP3:
MOV
ANL
ANL
ORL
MOVX
RET
A,R1
A,#07H
P1,#11111000B
P1,A
A,@RO
;READ 4K BYTE EXTERNAL RAM
For applications where up to 128 destinations must be
selected, all residing in the same 2K page of program
memory, the following technique may be used. In the
printing terminal example, this sequence could process
128 different codes for ASCII characters arriving via the
80S! serial port.
To use this approach, the size of the jump table plus the
length of the alternate routines must be less than 256
bytes. The jump table and routines may be located
anywhere in program memory and are independent of
256-byte program memory pages.
,
OPTION
EOU
R3
JMP128:
MOV
RL
MOV
JMP
A,OPTION
A
DPTR,#INSTBL
@A+DPTR
AJMP
AJMP
AJMP
PROCOO
PROC01
PROC02
AJMP
AJMP
PROC7E
PROC7F
;MULTIPLY BY 2 FOR 2·BYTE JUMP TABLE
;FIRST ENTRY IN JUMP TABLE
;JUMP INTO JUMP TABLE
,
INSTBL:
;128 CONSECUTIVE
;AJMP INSTRUCTIONS
The destinations in the jump table (PROCOO-PROC7F)
are not all necessarily unique routines. A large number
of special control codes could each be processed with
their own unique routine, with the remaining printing
characters all causing a branch to a common routine for
entering the character into the output queue.
handled by computing the destination address at runtime with standard arithmetic or table look-up instructions, then performing an indirect branch to that address. There are two simple ways to execute this last
step, assuming the 16-bit destination address has
already been computed. The first is to load the address
into the DPH and DPL registers, clear the accumulator
and branch using the JMP @A + DPTR instruction; the
second is to push the destination address onto the stack,
low-order byte first (so as to mimic a call instruction)
then pop that address into the PC by performing a
return instruction. This also adjusts the stack pointer to
its previous value. The code segment below illustrates
the latter possibility.
Computing Branch Destinations
at Run Time
In some rare situations, 128 options are insufficient, the
destination routines may cross a 2K page boundary, or a
branch destination is not known at assembly time (for
whatever reason), and therefore cannot be easily included in the assembled code. These situations can all be
RTEMP
EOU
R7
JMP256:
MOV
MOV
CLR
RLC
JNC
INC
DPTR,#ADRTBL
A,OPTION
C
A
LOW128
DPH
;FIRST ADDRESS TABLE ENTRY
;LOAD INDEX INTO TABLE
;MULTIPLY BY 2 FOR 2·BYTE JUMP TABLE
;FIX BASE IF INDEX >127.
5-7
AFN·01739A
8051 SOFTWARE ROUTINES
LOW128:
MOV
INC
MOVC
PUSH
MOV
MOVC
PUSH
RTEMP,A
A
A,@A+DPTR
ACC
A,RTEMP
A,@A+DPTR
ACC
;SAVE ADJUSTED ACC FOR SECOND READ
;READ lOW·ORDER BYTE FIRST
;GET lOW·ORDER BYTE FROM TABLE
;RElOAD ADJUSTED ACC
;GET HIGH·ORDERED BYTE FROM TABLE
THE TWO ACC PUSHES HAVE PRODUCED
A "RETURN ADDRESS" ON THE STACK WHICH CORRESPONDS
TO THE DESIRED STARTING ADDRESS.
IT MAY BE REACHED BY POPPING THE STACK
INTO THE PC.
RET
,
ADRTBl:
OW
OW
PROCOO
PROC01
OW
PROCFF
;UP TO 256 CONSECUTIVE DATA
;WORDS INDICATING STARTING ADDRESSES
In-line-Code Parameter-Passing
variable in internal RAM and stores the sum in a different two-byte buffer. The utility must be given the
constant and both buffer addresses. Rather than using
four working registers to carry this information, all four
bytes could be inserted into program memory each time
the utility is called. Specifically, the calling sequence
below invokes the utility to add 1234 (decimal) with the
string at internal RAM address 56H, and store the sum
in a buffer at location 78H.
Parameters can be passed by loading appropriate
registers with values before calling the subroutine. This
technique is inefficient if a lot of the parameters are
constants, since each would require a separate register
to carry it, and a separate instruction to load the register
each time the routine is called.
If the routine is called frequently, a more code-efficient
way to transfer constants is "in-line-code" parameterpassing. The constants are actually part of the program
code, immediately following the call instruction. The
subroutine determines where to find them from the
return address on the stack, and then reads the
parameters it needs from program memory.
The ADDBCD subroutine determines at what point the
call was made by popping the return address from the
stack into the data pointer high- and low-order bytes. A
MOVC instruction then reads the parameters from program memory as they are needed. When done, ADDBCD resumes execution by jumping to the instruction
following the last parameter.
For example, assume a utility named ADDBCD adds a
16-bit packed-BCD constant with a two-byte BCD
CAll
OW
DB
DB
ADDBCD
1234H
56H
78H
;BCD CONSTANT
;SOURCE STRING ADDRESS
;DESTINATION STRING ADDRESS
;CONTINUATION OF PROGRAM
5·8
AFN-01739A
8051 SOFTWARE ROUTINES
ADDBCD:
pOP
POP
MOV
MOVC
MOV
MOV
MOVC
MOV
MOV
MOVC
ADD
DA
MOV
INC
INC
CLR
MOVC
ADDC
DA
MOV
MOV
JMP
DPH
DPL
A,#2
A,@A+DPTR
RO,A
A,#3
A,@A+DPTR
R1,A
A,#1
A,@A+DPTR
A,@RO
A
@R1,A
RO
R1
A
A,@A+DPTR
A,@RO
A
@R1,A
A,#4
@A+DPTR
;POP RETURN ADDRESS INTO DPTR
;INDEX FOR SOURCE STRING PARAMETER
;GET SOURCE STRING LOCATION
;INDEX FOR DESTINATION STRING PARAMETER
;GET DESTINATION ADDRESS
;INDEX FOR 16·BIT CONSTANT LOW BYTE
;GET LOW·ORDER VALUE
;COMPUTE LOW·ORDER BYTE OF SUM
;DECIMAL ADJUST FOR ADDITION
;SAVE IN BUFFER
;INDEX FOR HIGH·BYTE == 0
;GET HIGH·ORDER CONSTANT
;DECIMAL ADJUST FOR ADDITION
;SAVE IN BUFFER
;INDEX FOR CONTINUATION OF PROGRAM
;JUMP BACK INTO MAIN PROGRAM
pushed these registers onto the stack (after popping
the parameter list starting address), and popped
before returning.
This example illustrates several points:
1) The "subroutine" does not end with a normal return
statement; instead, an indirect jump relative to the
data pointer returns execution to the first instruction following the parameter list. The two initial
POP instructions correct the stack pointer contents.
2)
3)
Passing parameters through in-line-code can be used in
conjunction with other variable passing techniques.
The utility can also get input variables from working
registers or from the stack, and return output variables
to registers or to the stack.
Either an ACALL or LCALL works with the
subroutine, since each pushes the address of the
next instruction or data byte onto the stack. The
call may be made from anywhere in the full 8051
address space, since the MOVC instruction accesses
all 64K bytes.
PERIPHERAL INTERFACING
TECHNIQUES
1/0 Port Reconfiguration (First Approach)
The parameters passed to the utility can be listed in
whatever order is most convenient, which may not
be that in which they're used. The utility has essentially "random access" to the parameter list, by
loading the appropriate constant into the accumulator before each MOVC instruction.
110 ports must often transmit or receive parallel data in
formats other than as eight-bit bytes. For example, if an
application requires three five-bit latched output ports
(called X, Y, and Z), these "virtual" ports could be
mapped onto the pins of "physical" ports 1 and 2 as
shown below:
4) Other than the data pointer, the whole calling and
processing sequence only affects the accumulator,
PSW and pointer registers. The utility could have
PORT "Z"
P2.7
PZO PZI
P2.6 P2.5
PZ2 PZ3
P2.4 P2.3
PORT "Y"
PZ4
P2.2
PY4
P2.I
PY3 PY2 PYI PYO
P2.0 Pl.7 Pl.6 Pl.5
PORT "X"
PX4 PX3 PX2 PXI
PIA Pl.3 Pl.2 PI.I
PXO
PI.O
This pin assignment leaves P2.7 free for use as a test
pin, input data pin, or control output through software.
5·9
AFN-01739A
8051 SOFTWARE ROUTINES
Notice that the bits of port Z are reversed. The highestorder port Z pin corresponds to pin P2.2, and the
lowest-order pin of port Z is P2.6, due to P.e. board
layout considerations. When connecting an 8051 to an
immediately adjacent keyboard column decoder or
another device with weighted inputs, the corresponding
pins may not be aligned. The interconnections must be
"scrambled" to compensate either with interwoven
circuit board traces or through software (as shown
below).
Writing to the virtual ports must not affect any other
pins. Since the virtual output aigorithms are non-trivial,
a subroutine is needed for each port: OUT_PX,
OUT_PY and OUT_PZ. Each is called with data to
output right-justified in the accumulator, and any data
in bits ACe.7-ACC.5 is insignificant. Each subroutine
saves the data in a "map" variable for the virtual port,
then calls other subroutines which use the data in the
various map bytes to compute and output the eight-bit
pattern needed for each physical port affected.
PX_MAP
PY_MAP
PZ_MAP
DATA
DATA
DATA
20H
21H
22H
OUT_PX:
ANL
MOV
ACALL
RET
A,#00011111 B
PX_MAP,A
OUT_P1
;CLEAR BITS ACC.7· ACC. 5
;SAVE DATA IN MAP BYTE
;UPDATE PORT 1 OUTPUT LATCH
OUT_PY:
MOV
ACALL
ACALL
RET
PY_MAP,A
OUT_P1
OUT_P2
;SAVE IN MAP BYTE
;UPDATE PORT 1
;AND PORT 2 OUTPUT LATCHES
MOV
ACALL
RET
PZ_MAP,A
OUT_P2
;SAVE DATA IN MAP BYTE
;UPDATE PORT 2.
MOV
SWAP
RL
ANL
ORL
MOV
RET
A,PY_MAP
A
A
A,#11100000B
A,PX_MAP
P1,A
;OUTPUT ALL P1 BITS
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
SETB
MOV
RET
C,PZ_MAP.O
A
C,PZ_MAP.1
A
C,PZ_MAP.2
A
C,PZ_MAP.3
A
C,PZ_MAP.4
A
C,PZ_MAP.4
A
C,PZ_MAP.3
A
ACC.7
P2.A
;LOAD CY WITH P2.6 BIT
;AND SHIFT INTO ACC.
;LOAD CY WITH P2.5 BIT
;AND SHIFT INTO ACC.
;LOAD CY WITH P2.4 BIT
;AND SHIFT INTO ACC.
;LOAD CY WITH P2.3 BIT
;AND SHIFT INTO ACC.
;LOAD CY WITH P2.2 BIT
;AND SHIFT INTO ACC.
;LOAD CY WITH P2.1 BIT
;AND SHIFT INTO ACC.
;LOAD CY WITH P2.0 BIT
;AND SHIFT INTO ACC.
;(ASSUMING INPUT ON P2.7)
,
OUT_PZ:
,
OUT_P1:
;SHIFT PY_MAP LEFT 5 BITS
;MASK OUT GARBAGE
;INCLUDE PX_MAP BITS
,
OUT_P2:
The two level structure of the above subroutines can be
modified somewhat if code efficiency and execution
speed are critical: incorporate the code shown as
subroutines OUT_PI and OUT_P2 directly into the
code for OUT_PX and OUT_PZ, in place of the
corresponding ACALL instructions. OUT_PY would
not be changed, but now the destinations for its
ACALL instructions would be alternate entry points in
OUT_PX and OUT_PZ, instead of isolated
subroutines.
5-10
AFN·01739A
8051 SOFTWARE ROUTINES
1/0 Port Reconfiguration
(Second Approach)
A trickier situation arises if two sections of code which
write to the same port or register, or call virtual output
routines like those above, need to be executed at
different interrupt levels. For example, suppose the
background program wants to rewrite Port X (using the
port associations in the previous example), and has
computed the bit pattern needed for PI. An interrupt is
detected just before the MOY Pl,A instruction, and the
service routine tries to write Port Y. The service routine
would correctly update PI and P2, but upon returning
to the background program PI is immediately re-written
with the data computed before the interrupt! Now pins
P2.1 and P2.0 indicate (correctly) data written to port Y
in the interrupt routine, but the earlier data written to
PI.7-Pl.5 is no longer valid. The same sort of confusion
could arise if a high-level interrupt disrupted such an
output sequence.
One solution is to disable interrupts around any section
of code which must not be interrupted (called a "critical
section"), but this would adversely affect interrupt
latency. Another is to have interrupt routines set or
clear a flag ("semaphore") when a common resource is
altered - a rather complex and elaborate system.
An easier way to ensure that any instruction which
writes the port X field of PI does not change the port Y
field pins from their state at the beginning of that
instruction, is shown next. A number of 8051 operations
read, modify, and write the output port latches all in
one instruction. These are the arithmetic and logical
instructions (INC, DEC, ANL, ORL, etc.), where an
addressed byte is both the destination variable and one
of the source operands. Using these instructions, instead
of data moves, eliminates the critical section problem
entirely.
OUT_PX:
ANL
ORL
RET
P1 ,#111 OOOOOB
P1,A
;CLEAR BITS P1.4 . P1.0
;SET P1 PIN FOR EACH ACC BIT SET.
OUT_ PY:
MOV
MUL
ANL
ORL
MOV
ANL
ORL
RET
B,#20H
AB
P1,#00011111B
P1,A
A,B
P2,#11111100B
P2,A
;SHIFT LEFT 5 BITS.
;CLEAR PY FIELD OF PORT 1
;SET PY BITS ON PORT 1
;LOAD 2 BITS SHIFTED INTO B
;AND UPDATE P2
RRC
MOV
RRC
MOV
RCC
MOV
RRC
MOV
RRC
MOV
RET
A
P2.6,C
A
P2.S,C
A
P2.4,C
A
P2.3,C
A
P2.2,C
;MOVE ORIGINAL ACC.O INTO
;AND STORE TO PIN P2.6.
;MOVE ORIGINAL ACC.1 INTO
;AN D STORE TO PIN P2.S.
;MOVE ORIGINAL ACC.2 INTO
;AND STORE TO PIN P2.4.
;MOVE ORIGINAL ACC.3 INTO
;AND STORE TO PIN P2.3.
;MOVE ORIGINAL ACC.4 INTO
;AND STORE TO PIN P2.2.
,
OUT
PZ:
CY
CY
CY
CY
CY
8243 Interfacing
Even though the 8051 does not include 8048-type
instructions for interfacing with an 8243, the parts can
be interconnected and the protocol may be emulated
with simple software; see Figure 5.2.
The 8051's quasi-bidirectional port structure lets each
110 pin input data, output data, or serve as a test pin or
output strobe under software control. An example of
these modes operating in conjunction is the hostprocessor interface expected by an 8243 110 expander.
5-11
AFN-01739A
8051 SOFTWARE ROUTINES
,
;IN8243
,
INPUT DATA FROM AN 8243 I/O EXPANDER
CONNECTED TO P23·P20.
P25 & P24 MIMIC CS &PROG.
P27·P26 USED AS INPUTS. CODE FOR
PORT TO BE READ IN ACC.1·ACC.0
PROG
BIT
P2.4
;SYMBOLIC PIN DESCRIPTION
IN8243:
ORL
MOV
CLR
ORL
MOV
ORL
A,#11010000B
P2,A
PROG
P2,#00001111 B
A,P2
P2,#00110000B
;SET PROG AND PINS USED AS INPUT
;OUTPUT PORT CODE AND OPERATION CODE
;LOWER PROG TO LATCH ADDRESS
;SET LOW ORDER PINS FOR INPUT
;READ IN PORT DATA
;SET PROG AND CS HIGH
,
Software Delay Timing
Many 8051 applications involve exact control over
output timing. A software-generated output strobe, for
instance, might have to be exactly 50 p.sec. wide. The
DJNZ operation can insert a one instruction software
CLR
MOV
DJNZ
SETB
delay into a piece of code, adding a moderate time delay
of two instruction cycles per iteration. For example, two
instructions can add a 49-p.sec. software delay loop to
code to generate a pulse on the WR pin.
WR
R2,#24
$2,$
WR
The dollar sign in this example is a special character
meaning "the address of this instruction." It can be used
to eliminate instruction labels on nearby source lines.
8351
8751
8243
P4
P2.7
P2.&
P2.5
P2.4
Serial Port and Timer Mode Configuration
Configuring the 8051's Serial Port for a given data rate
and protocol requires essentially three short sections of
software. On power-up or hardware reset the serial port
and timer control words must be initialized to the
appropriate values. Additional software is also needed
in the transmit routine to load the serial port data
register and in the receive routine to unload the data as
it arrives.
P2.3
P2.2
P2.1
P2.0
} INPUTS
cs
P5
PROG
P23
P&
P22
P21
P20
P7
Figure 5·2. Connecting an 8051 with an 8243
1/0 Expander
To choose one arbitrary example, assume the 8051
should communicate with a standard CRT operating at
2400 baud (bits per second). Each character is
transmitted as seven data bits, odd parity, and one stop
bit. The resulting character rate is 2400 baud/9bits,
approximately 265 characters per second.
the output software know the output register is
available. All this can be set up with instruction at label
SPINIT.
Timer 1 will be used in auto-reload mode as a baud rate
generator. To achieve a data rate of 2400 baud, the
timer must divide the IMHz internal clock by
For the sake of clarity, the transmit and receive
subroutines here are driven by simple-minded software
status polling code rather than interrupts. The serial
port must be initialized to 8-bit UART mode (SMO,
SMI = 01), enabled to receive all messages (SM2=0,
REN = 1). The flag indicating that the transmit register
is free for more data will be artificially set in order to let
1 x 106
(32) (2400)
which equals 13 (actually, 13.02) instruction cycles. The
5·12
AFN·01739A
8051 SOFTWARE ROUTINES
timer must reload the value -13, or OF3H, as shown by
the code at label TIINIT. (ASM51 will accept both the
signed decimal or hexadecimal representations.)
,
SPINIT:
;TIINIT:
INITIALIZE SERIAL PORT
FOR a·BIT UART MODE
& SET TRANSMIT READY FLAG.
MOV
SCON,#01010010B
INITIALIZE TIMER 1 FOR
AUTO·RELOAD AT 32 X 2400HZ
(TO USED AS GATED 16·BIT COUNTER.)
MOV
TCON,#11010010B
MOV
TH1,#·13
SETB
TR1
Simple Serial 1/0 Drivers
SP _OUT is a simple subroutine to transmit the
character passed to it in the accumulator. First it must
compute the parity bit, insert it into the data byte, wait
until the transmitter is available, output the character,
and then return.
SP _IN is an equally simple routine which waits until a
character is received, sets the carry flag if there is an
odd-parity error, and returns the masked seven-bit code
in the accumulator.
,
;SP_OUT
ADD ODD PARITY TO ACC AND
TRANSMIT WHEN SERIAL PORT READY.
,
SP_OUT:
C,P
C
ACC.7,C
TI,$
TI
SBUF,A
INPUT NEXT CHARACTER FROM SERIAL PORT.
SET CARRY IF ODD·PARITY ERROR
,
SP
MOV
CPL
MOV
JNB
CLR
MOV
RET
IN:
JNB
CLR
MOV
MOV
CPL
ANL
RET
RI,$
RI
A,SBUF
C,P
C
A,#7FH
Transmitting Serial Port Character
Strings
messages, diagnostics, or operator instructions. These
character strings are most easily defined with in-line
data bytes defined with the DB directive.
Any application which transmits characters through a
serial port to an ASCII output device will on occasion
need to output "canned" messages, including error
5-13
AFN-01739A
8051 SOFTWARE ROUTINES
CR
LF
ESC
EaU
EaU
EaU
ODH
OAH
1BH
;ASCII CARRIAGE RET
;ASCII LlNE·FEED
;ASCII ESCAPE CODE
CALL
DB
DB
DB
XSTRING
CR,LF
'INTEL DELIVERS'
ESC
;NEW LINE
;MESSAGE
;ESCAPE CHARACTER
(CONTINUATION OF PROGRAM)
,
XSTRING:
XSTR_1:
XSTR_2:
POP
POP
CLR
MOVC
JNB
CLR
MOV
INC
CLR
MOVC
·CJNE
MOV
JMP
DPH
DPL
;LOAD DPTR WITH FIRST CHARACTER
A
;(ZERO OFFSET)
;FETCH FIRST CHARACTER OF STRING
;WAIT UNTIL TRANSMITTER READY
;MARK AS NOT READY
;OUTPUT NEXT CHARACTER
;BUMP POINTER
A,@A+DPTR
TI,$
TI
SBUF,A
DPTR
A
A,@A+DPTR
A,#ESC,XSTR_2
A,#1
@A+DPTR
;GET NEXT OUTPUT CHARACTER
;LOOP UNTIL ESCAPE READ
;RETURN TO CODE AFTER ESCAPE
Recognizing and Processing
Special Cases
Before operating on the data it receives, a subroutine
might give "special handling" to certain input values.
Consider a word processing device which receives
ASCII characters through the 8051 serial port and
drives a thermal hard-copy printer. A standard routine
translates most printing characters to bit patterns, but
certain control characters «DEL>, , ,
,, or
value, OOH, and processed with the printing characters.
The CJNE operation provides essentially a oneinstruction CASE statement.
,
CHAR
EaU
R7
;CHARACTER CODE VARIABLE
INTERP:
CJNE
CHAR,#7FH, INTP_1
;SKIP UNLESS RUBOUT
(SPECIAL ROUTINE FOR RUBOUT CODE)
INTP_1:
RET
CJNE
CHAR,#07H,INTP _2
;SKIP UNLESS BELL
(SPECIAL ROUTINE FOR BELL CODE)
INTP_2:
RET
CJNE
CHAR,#OAH,INTP_3
;SKIP UNLESS LFEED
(SPECIAL ROUTINE FOR LFEED CODE)
INTP_3:
RET
CJNE
CHAR,#ODH,INTP_4
;SKIP UNLESS RETURN
(SPECIAL ROUTINE FOR RETURN CODE)
INTP_4:
RET
CJNE
CHAR,#1 BH,INTP_5
;SKIP UNLESS ESCAPE
(SPECIAL ROUTINE FOR ESCAPE CODE)
INTP_5:
RET
CJNE
CHAR,#20H,INTP _6
;SKIP UNLESS SPACE
(SPECIAL ROUTINE FOR SPACE CODE)
RET
JC
MOV
PRINTC
CHAR,#O
;JUMP IF CODE> 20 H
;REPLACE CONTROL CHARACTER WITH
;NULL CODE
INTP_6:
5·14
AFN-01739A
8051 SOFTWARE ROUTINES
PRINTC:
;PROCESS STANDARD PRINTING
;CHARACTER
RET
Buffering Serial Port Output Characters
It is not always efficient to transmit characters through
the serial port one-at-a-time. Most applications generate
a short burst of characters all at once (English words or
multi-digit numbers, for instance), with the bursts
themselves occurring at longer intervals. Instead of
waiting while the UART outputs each character, it
would be more efficient if the background program
could enter all the characters into a first-in first-out
(FIFO) data structure, and continue about its business,
QHEAD
QTAIL
BOTLIM
TOPLIM
DATA
DATA
EQU
EQU
6EH
6FH
70H
7FH
letting an interrupt routine transmit each character as
the serial port becomes available.
Assume there is a 16-byte output data buffer starting at
70H. QHEAD and QT AIL keep track of the head and
tail portion of the buffer being used. The subroutine
ENTERQ waits until there is space in the queue, then
copies a character code from the accumulator to the
queue.
;LAST BYTE ENTERED INTO QUEUE
;LAST BYTE READ FROM QUEUE.
QUEUE IS EMPTY WHEN QHEAD = QTAIL AND
FULL WHEN QHEAD + 1 (WITHIN RANGE) = QTAIL.
QHEAD,#TOPLIM
MOV
MOV
QTAIL,#TOPLIM
ENTERQ:
ENTQ_1:
ENTQ_2:
MOV
MOV
INC
CJNE
MOV
CJNE
SJMP
XCH
MOV
MOV
SETB
RET
RO,A
A,QHEAD
A
A,#TOPLIM + 1,ENTQ_1
A,#BOTLIM
A,QTAIL,ENTQ_2
ENTQ_1
A,RO
@RO,A
QHEAD,RO
ES
;SAVE ACC DATA
;LOAD HEAD POINTER
;PRE·INCREMENT POINTER
;RELOAD ON OVERFLOW
;TEST IF QUEUE FULL
;LOOP UNTIL SPACE AVAILABLE
;STORE POINTER AND RELOAD ACC
;ENTER INTO QUEUE
;UPDATE HEAD POINTER
;ENABLE SERIAL PORT INTERRUPTS
fer (SBUF) and the pointers are updated. If not,
DQUEUE disables serial port interrupts and returns to
the background program. ENTERQ will re-enable such
interrupts as more data is available. (This example does
not consider interrupt-driven serial input.)
The interrupt routine DQUEUE is invoked when the
transmitter is ready for another character. First it determines if any characters are available for transmission,
indicated by QHEAD and QT AIL being not equal. If
more data is available, it is written to the transmit buf-
DQUEUE:
ORG
PUSH
PUSH
MOV
MOV
CJNE
CLR
SJMP
0023H
ACC
PSW
PSW,#30Q
A,QTAIL
A,QHEAD,DQ_1
ES
TI_RET
;SAVE CPU STATUS
;SELECT BANK 3
;TEST IF QUEUE EMPTY
;IF SO, CLEAR ENABLE BIT AND RETURN
5·15
AFN-01739A
8051 SOFTWARE ROUTINES
CLR
INC
CJNE
MOV
MOV
MOV
MOV
POP
POP
RETI
TI
A
A,#TOPLIM + 1,DQ_2
A,#BOTLIM
RO,A
SBUF,@RO
QTAIL,A
PSW
;ELSE ACKNOWLEDGE REQUEST
;COMPUTE NEXT BYTE'S ADDRESS
:REVISE ACC IF POI'NTER OVERFLOWED
;LOAD INDEX REGISTER
;RELOAD TRANSMITTER
;SAVE LAST POINTER USED.
;RESTORE STATUS AND RETURN
A
Synchronizing Timer Overflows
8051 timer overflows automatically generate an internal
interrupt request, which will vector program execution
to the appropriate interrupt service routine if interrupts
are enabled and no other service routines are in progress
at the time. However, it is not predictable exactly how
long it will take to reach the service routine. The service
routine call takes two instruction cycles, but 1, 2, or 4
additional cycles may be needed to complete the instruction in progress. If the background program ever
disables interrupts, the response latency could further
increase by a few instruction cycles. (Critical sections
generally involve simple instruction sequences - rarely
multiplies or divides.) Interrupt response delay is
generally negligible, but certain time-critical application
must take the exact delay into account. For example,
generating interrupts with timer 1 every millisecond
(1000 instruction cycles) or so would normally call for
reloading it with the value - 1000 (OFC30H). But if the
CLR
CLR
MOV
ADD
MOV
MOV
ADDC
MOV
SETB
EA
TR1
A,#LOW(-1000+ 7)
A,TL1
TL1,A
A,#HIGH(-1000+ 7)
A,TH1
TH1,A
TH1
interrupt interval (averaged over time) must be accurate
to 1 instruction cycle, the 16-bit value reload into the
timer must be computed, taking into account when the
timer actually overflowed.
This simply requires reading the appropriate timer,
which has been incremented each cycle since the
overflow occurred. A sequence like the one below can
stop the timer, compute how much time should elapse
before the next interrupt, and reload and restart the
timer. The double-precision calculation shown here
compensates for any amount of timer overrun within
the maximum interval. Note that it also takes into account that the timer is stopped for seven instruction
cycles in the process. All interrupts are disabled, so a
higher priority request will not be able to disrupt the
time-critical code section.
;DISABLE ALL INTERRUPTS
;STOP TIMER 1
;LOAD LOW·ORDER DESIRED COUNT
;CORRECT FOR TIMER OVERRUN
;RELOAD LOW·ORDER BYTE.
;REPEAT FOR HIGH·ORDER BYTE.
;RESTART TIMER
Reading a Timer/Counter "On·the·Fly"
a sixteen-bit value indicating the count in timer O.
The instant at which the count was sampled is not as
critical as the fact that the value returned must have
been valid at some point while the routine was in progress. There is a potential problem that between reading
the two halves, a low-order register overflow might increment the high-order register, and the two data bytes
returned would be "out of phase." The solution is to
read the high-order byte first, then the low-order byte,
and then confirm that the high-order byte has not
changed. If it has, repeat the whole process.
The preceding example simply stopped the timer before
changing its contents. This is normally done when
reloading a timer so that the time at which the timer is
started (i.e. the "run" flag is set) can be exactly controlled. There are situations, though, when it is desired
to read the current count without disrupting the timing
process. The 8051 timer/counter registers can all be read
or written while they are running, but a few precautions
must be taken.
Suppose the subroutine RDTIME should return in
5-16
AFN·01739A
8051 SOFTWARE ROUTINES
RDTIME:
MOV
MOV
CJNE
MOV
RET
A,THO
RO,TLO
A,THO,RDTIME
R1,A
;SAMPLE TIMERO (HIGH)
;SAMPLE TIMERO (LOW)
;REPEAT IF NECESSARY
;STORE VALID READ
5-17
AFN·01739A
8031/8051/8751
SINGLE-COMPONENT 8-BIT MICROCOMPUTER
• 8031 . Control Oriented CPU With RAM and I/O
• 8051 . An 8031 With Factory Mask·Programmable ROM
• 8751 . An 8031 With User ProgrammabletErasable EPROM
x 8 ROM/EPROM
• 4K
128x
8 RAM
• Four 8·Bit
32 I/O Lines
• Two 16·BitPorts,
Timer/Event Counters
Processor
• Boolean
MCS·48® Architecture Enhanced with:
• • Non·Paged Jumps
• High·Performance Full·Duplex
• Serial Channel
External Memory Expandable to 128K
• Compatible
with MCS·80® /MCS·85®
•
•
• Peripherals
• Direct Addressing
• Four 8·Register Banks
• Stack Depth Up to 128·Bytes
• Multiply, Divide, Subtract, Compare
Most Instructions Execute in 1jJs
4J.Js Multiply and Divide
The Intel® 8031/8051/8751 is a stand-alone, high-performance single-chip computer fabricated with Intel's highly-reliable
+ 5 Volt, depletion-load, N-Channel, silicon-gate HMOS technolgy and packaged in a40-pin DIP.lt provides the hardware
features, architectural enhancements and new instructions that are necessary to make it a powerful and cost effective
controller for applications requiring up to 64K bytes of program memory and/or up to 64K bytes of data storage.
The 8051/8751 contains a non-volatile 4K x 8 read only program memory; a volatile 128 x 8 read/write data memory; 32110
Iines; two 16-bit timer/counters; a five-source, two-priority-Ievel, nested interrupt structure; a serial 110 port foreither multiprocessor communications, I/O expansion, or full duplex UART; and on-chip oscillator and clock circuits. The 8031 is indentical, except that it lacks the program memory. For systems that require extra capabi lity, the 8051 can be expanded using standard TTL compatible memories and the byte oriented MCS-80 and MCS-85 peripherals.
The 8051 microcomputer, like its 8048 predecessor, is efficient both as a controller and as an arithmetic processor. The
8051 has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions.
With a 12 MHz crystal, 58% of the instructions execute in 1 ).IS, 40% in 2).1s and multiply and divide requireonly4 ).Is. Among
the many instructions added to the standard 8048 instruction set are multiply, divide, subtract and compare.
FREQUENCY
REFERENCE
-1
I
I
'--~--'
,
I
,
""-----'""---.',
I
.........--,--' I
L
r
RXD
__
TXO~
n __
PARALLEL PORTS,
ADDRESS/DATA BUS,
AND 1/0 PINS
SERIAL
IN
SERIAL
OUT
t
;:=: ;
t
TO--.
WA4RD4-
Figure 2.
Logic Symbol
Figure 1.
Block Diagram
wAD
~
Figure 3. Pin
Configuration
Intel Corporalion Assumes No Responsibilily for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
©INTELCORPORATION,1980
6-1
8031/8051/8751
for cou nter O.
- INT1 (P3.3). Interrupt 1 input or gate control
input for counter 1.
- TO (P3.4). Input to counter O.
-- T1 (P3.5). Input to counter 1.
- WR (P3.6). The write control signal latches the
data byte from Port 0 into the External Data
Memory.
- RD (P3.7). The read control signal enables External
Data Memory to Port O.
8051 FAMilY PIN DESCR!PTION
Vss
Circuit ground potential.
Vee
+5V power supply during operation, programming
and verification.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory. It is used for data
input and output during programming and verification. Port 0 can sink/source two TTL loads.
RST/VPD
A low to high transition on this pin (at approximately
3V) resets the 8051. If VpD is held within its spec
(approximately +5V), while VCC drops below spec,
VpD will provide standby power to the RAM. When
VpD is low, the RAM's current is drawn from VCe-
Port 1
Port 1 is an 8-bit quasi-bidirectional I/O port. It is
used for the low-order address byte during programming and verification'. Port 1 can sink/source one
TTL load.
ALE/PROG
Port 2
Provides Address Latch Enable output used for
latching the address into external memory during
normal operation. Receives the program pulse
input during EPROM programming.
Port 2 is an 8-bit quasi-bidirectional I/O port. It also
emits the high-order 8 bits of address when accessing
external memory. It is used for the high-order address
and the control signals during programming and
verification. Port 2 can sink/source one TTL load.
PSEN
The Program Store Enable output is a control signal
that enables the external Program Memory to the
bus during normal fetch operations.
Port 3
Port 3 is an 8-bit quasi-bidirectional I/O port. It also
contains the interrupt, timer, serial port and RD and
WR pins that are used by various options. The output latch corresponding to a special function must
be programmed to a one (1) for that function to
operate. Port 3 can sink/source one TTL load. The
special functions are assigned to the pins of Port 3,
as follows:
-RXD/data (P3.0). Serial port's receiver data input
(asynchronous) or data input/output (synchronous).
- TXD/clock (p3.1). Serial port's transmitter data
output (asynchronous) or clock output (synchronous).
EA/VDD
When held at a TTL high level, the 8051 executes
instructions from the internal ROM/EPROM when
the PC is less than 4096. When held at a TTL low
level, the 8051 fetches all instuctions from external
Program Memory. The pin also receives the 21V
EPROM programming supply Voltage.
XTAL1
Input to the oscillator's high gain amplifier. A crystal
or external source can be used.
XTAL2
Output from the oscillator's amplifier. Required when
a crystal is used.
- INTO (P3.2). Interrupt 0 input or gate control input
6-2
inter
8031/805·1/8751
* NOTICE.' Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
0
0
Ambient Temperature Under Bias .......... 0 C to 70 C
Storage Temperature ...... ,' .. , ... , .. , , -65 0 C to +1500 C
Voltage on Any Pin With
Respect to Ground (VSS) .. , , ... , , ....... -0.5V to +7V
Power Dissipation "'.,.,', .. " . , " ' .. ',.,.",. 2 Watts
D.C. CHARACTERISTICS
Symbol
TA = O°C TO 70°C; VCC = 5V ± 5%; VSS = OV
Max.
Units
-0.5
0.8
V
-0.5
TBD
V
2.0
VCC+0.5
V
TBD
VCC+0.5
V
Parameter
Min.
VIL
Input Low Voltage (All except XTAL 1)
VIL1
Input Low Voltage (XTAL1)
Typ.
VIH
Input High Voltage
(All Except XTAL 1, RSTIVPD)
VIH1
Input High Voltage (XTAL 1)
VIH2
Input High Voltage (RST)
3.0
VCC + 0.5
V
VIH3
Input High Voltage (VpD)
4.5
5.5
V
Test Conditions
Power Down Only
(VCC = 0)
VOL
Output Low Voltage
(All Outputs Except Port 0)
0.45
V
1,6mA
VOL1
Output Low Voltage (Port 0)
0.45
V
3.2mA
IOH=-100tJA
IOH:= -400 tJA
VOH
Output High Voltage (All Outputs
Except Port 0, ALE and PSEN)
2.4
V
VOH1
Output High Voltage (ALE and PSEN,
Port 0 In External Bus Mode)
2.4
V
ILO
Pullup Resistor Current (P1, P2, P3)
-500
tJA
.45V5. VIN 5.VCC
IL01
Output Leakage Current (PO)
:t10
pA
.45V 5. VIN 5. VCC
ICC
Power Supply Current
(All Outputs Disconnected)
150
mA
TA =25° C
IpO
Power Down Supply Current
20
mA
TA=25°C, VpO=5V,
VCC=OV
CIO
Capacitance Of 1/0 Buffer
10
pF
fc=1MHz
6-3
8031/8051/8751
A.C. CHARACTER!ST!CS
TA = O°C TO 70°C; VCC=5V±5%
Port 0, ALE and PSEN Outputs - CL
All Other Outputs - CL = 80PF
= 150 PF;
Program Memory Characteristics
Variable Clock
1/TCLCL=1.2 MHz to 12 MHz
12MHz Clock
Symbol
TCLCL
Parameter
Oscillator Period
Min.
Max.
Units
83
ns
Max.
Min.
Units
ns
12TCLCL
ns
TCY
Min Instruction Cycle Time
1.0
J,Js
12TCLCL
TLHLL
ALE Pulse Width
140
ns
2TCLCL-30
ns
TAVLL
Address Set Up To ALE
60
ns
TCLCL-25
ns
TLLAX
Address Hold After ALE
50
ns
TCLCL-35
ns
TPLPH
PSEN Width
230
ns
3TCLCL-20
ns
TLHLH
PSEN, ALE Cycle Time
500
ns
6TCLCL
TPLIV
TPHDZ
PSEN To Valid Data In
-Input Data Hold After PSEN
-Input Data Float After PSEN
TAVIV.
Address To Valid Data In
TAZPL
Address Float To PSEN
TPHDX
150
ns
0
ns
ns
3TCLCL-100
ns
ns
0
75
ns
TCLCL-10
ns
320
ns
5TCLCL-100
ns
ns
0
0
ns
External Data Memory Characteristics
12MHz Clock
Parameter
Symbol
-
Min.
TRLRH
RD Pulse Width
400
TWLWH
WR Pulse Width
RD To Valid Data In
400
Data Hold After RD
Data Float After RD
0
TRHDZ
TAVDV
Address To Valid Data In
TRLDV
TRHDX
TAVWL
Address To WR or RD
TQVWH
Data Setup Before WR
TWHQX
-
-
Data Held After WR
Max.
250
Variable Clock
Units
Min.
ns
6TCLCL-100
ns
6TCLCL-100
ns
ns
Max.
Units
ns
ns
5TCLCL-170
ns
ns
0
100
ns
2TCLCL-70
ns
600
ns
9TCLCL-150
ns
200
ns
4TCLCL-130
ns
400
ns
7TCLCL-180
ns
80
ns
2TCLCL-90
ns
NOTE:
There are 2 to 8 ALE cycles per instruction. Clocks and state timing are shown on the timing diagram for reference purposes only. They are
not accessible outside the package. TCV is the minimum instruction cycle time which consists of 12 oscillator clocks or two ALE cycles.
Address setup and hold time from ALE are the same for data and program memory.
6-4
8031/8051/8751
OSC
ALE
PSEN
RD, WR
ADDRESS OR
SFR P2
PORT 2
PORT 0
FLOAT
Program Memory Read Cycle
ALE
PSEN
TRLRH
~
RD
PORT 2
-TAVWL
r---
TRLDV-l
TAVDV
PORT 0
ADDR ESS OR
SFR P2
ADDRESS A1S-AS
INSTR
IN
!FLOAT)<
I
A7- A O
r---TRHDZ - .
TRHDX-t
)<
FLOAT
DATA IN
rI
FLOAT
"@
RESS
OR FLOAT
Data Memory Read Cycle
ALE
PSEN
~
WR
-
TWLWH
PORT 2
ADDR ESS OR
SFR P2
ADDRESS A1S-AS
TAVWL
TOVWH
PORTO
INSTR
IN
IFLOAT)<
A7- A O
DATA OUT
)<
Data Memory Write Cycle
6-5
TWHOX--1
ADDR ESS
OR Fl OAT
8031/8051/8751
Serial Port Characteiistics
Symbol
TDVPl
TPHDX
TAVQV
TElQV
TEHQZ
TVHPl
TPHVl
TPlPH
Variable Clock
12 MHz Clock
Max.
Min.
Parameter
Data Setup to PROG
Data Hold from PROG
Address to Data Valid
Output Enable (P27) to Data Valid
Output Enable Off to Data Float
VDD Setup to PROG
VDD Hold after PROG
PROG Width
Max.
3 Tey + 10/Js
3 Tey + 10IJs
10IJs
10IJs
0
10IJs
10",s
49ms
Min.
10IJs
10IJs
10IJs
0
10",s
10,",s
49ms
51ms
3 Tey + 1Ol-'S
3 Tey + 10/Js
3 Tey + 10/Js
51ms
Input and Output Waveforms for A.C. Tests
2.4
0.45
V
~A
______
_
2.0
_2.0V
0.8::' TEST POINTS -
0.8_
A"--_______
-
PROGRAM VERIFY
\~--1
PORT 27
PORT 10·17
TAVPL
ADDRESS
"I" -\
R-
r--+
TPHAX
ADDRESS
TAvav
ADDRESS
ADDRESS
ADDRESS. 1
ADDRESS
;,---------..~~T_EHaz
DATA OUT STABLE
PORT 00·07
I" ~ I"
T
1
_
DATA IN
TPLPH
-------------~\
~~---------------------------------------PROG/ALE
~
T_V_HP_L_~_p_PJ"~ ~ ~~
_V_DD_/E_A_ _ _ _
__
TP_H_V_L_____________________________________________
NOTES: 1) PSEN = VIL, VPD/RST = VIH1
2) MSB of address is Port 23, LSB is Port 0
3) All levels are VIL, VIH, VOL, VOH except VDD/EA.
6-6
8021
SINGLE COMPONENT 8-BIT MICROCOMPUTER
• 8-Bit CPU, ROM, RAM, I/O in Single
•
• Single SV Supply (+4.SV to 6.SV)
}lsec Cycle With 3.58 MHz XTAl;
• 8.38
All Instructions 1 or 2 Cycles
• Interval Timer IEvent Counter
• Clock Generated With Single Inductor
• Instructions- 8048 Subset
• High Current Drive Capability-2 Pins
• Zero-Cross Detection Capability
• Easily Expandable I I 0
28-Pin Package
1K x 8 ROM
64 x 8 RAM
21 I/O Lines
or Crystal
The Intel@ 8021 is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using Intel's Nchannel silicon gate MOS process. The features of the 8021 include a subset of the 8048 optimized for low cost,
high volume applications, plus additional I/O flexibility and power.
The 8021 contains 1K X 8 program memory, a 64 X 8 data memory, 21 I/O lines, and an 8-bit timer / event counter, in
addition to on-board oscillator and clock circuits. For systems that require extra I/O capability, the 8021 can be
expanded using the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 has bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results
from an instruction set consisting mostly of single byte instructions and no instructions over two bytes in length.
To minimize the development problems and maximize flexibility, an 8021 system can be easily designed using the
8021 emulation board, the EM-1. The EM-1 contains a 40-pin socket which can accommodate either the 8748
shipped with the board or an ICE-49 plug. Also, the necessary discrete logic to reproduce the 8021 's additional 1/0
features is included.
PORT
XTAL \
Jt()
PORT
#1
RESET
PORT
#2
TEST
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
Figure 2.
Logic Symbol
Figure 1.
Block Diagram
P22
VCC
P23
P21
PROG
P20
POO
P1l
POl
P16
P02
P15
P03
P14
P04
P13
P05
P12
P06
POl
ALE
P11
P10
RESET
Tl
XTAL 2
VSS
XTAL 1
Figure 3. Pin
Configuration
Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied
©INTELCORPORATION,1980
AFN·Q1567A·Q1
7-1
8021
ABSOLUTE MAXiiViUiVi RATINGS·
*i"}OTiCE: Stres,ses a.bova t"1ose listed under ",4bso!ute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Ambient Temperature Under Bias. . . . . . .. 0° C to 70° C
Storage Temperature ............... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .................... -0.5V to +7V
Power Dissipation .............................. 1 W
D.C. CHARACTERISTICS TA:;;: O°C to 70°C, VCC:;;: 5.5V ± 1V, VSS == OV
Symbol
Parameter
Min.
Limits
Typ. Max.
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage (All except
XTAL 1 & 2, T1 RESET)
3.0
Vee
V
VIH1
Input High Voltage (XTAL 1 & 2,
T1 RESET)
3.S
Vce
V
VIH(1o%)
Input high voltage (All except XTAL
1 & 2, T1, RESET)
2.0
Vee
V
Vee:;;: 5.0V ± 10%
VIH1 (10%)
Input high voltage (XTAL 1 & 2,
T1, RESET)
3.5
Vec
V
Vee:;;: 5.0V ± 10%
VOL
Output Low Voltage
OA5
V
IOL:;;: 1.6 mA
VOL1
Ovtput Low Voltage (P1 0, P11)
2.. 5
V
IOL:;;: 7 mA
VOH
Ol)tput High Voltage
(All unless Open Drain)
V
IOH:;;: 40 p.A
ILO
Output Leakage Current
(Open Drain Option - Port 0)
ICC
VCC Supply Current
T1 ZERO CROSS CHARACTERISTICS
Symbol
2.4
40
± 10
p.A
75
mA
TA:;;: ooe to 70°C, Vcc:;;: 5.5V
Parameter
VZX
Zero-Cross Detection Input (T1)
AZX
Zero-Cross Accuracy
FZX
Zero-Cross Detection Input Frequency (T1)
± 1V, VSS:;;: OV,
CL
= SOpF
Min.
Max.
Unit
Test Conditions
1
3
VPP
Ae Coupled, C =.2p.F
± 135
mV
60 Hz Sine Wave
1
kHZ
0.05
7-2
VSS+0.45::::;;VIN::::;;Vee
AFN-ol567 A-02
8021
Table 1. Pin Description
Designation
Pin
No.
Vss
14
Circuit GND potential
Vce
28
+5V power supply
PROG
POO-P07
3
Designation
Function
Pin
No.
Output strobe for 8243 I/O
Expander
RESET
17
Input used to initialize the processor by clearing status flip-flops
and setting program counters to
zero.
18·25 8-bit quasi-btdii'ectional port
ALE
12
Address Latch Enable. Signal
occurring once every 30 input
clocks, used as an output clock.
26-27 4-bit quasi-bidl-recti(mal port
XTAL 1
15
One side of crystal or inductor
input for internal oscillator. Also
input for external source. (Not
TTL compatible.)
XTAL2
16
Other side of timing control
element.
4-11
8-bit
quasi~bidirectional
port
Port 0
P10-P17
Port 1
P20-P23
Function
CNT instruction. Also allows
zero-crossover sensing of slowly
moving inputs.
Port 2
1-2
P20-P23 also s:erve as a 4-bit I/O
expander bus for 8243
T1
13
Input pin testable using the JT1
and JNT1 instructions. Can be
designated t~.timer/event
counter input using the STRT
Table 2. Instruction Set Summary
Mnemonic
Description
ADD A,R r
ADD A,@R
ADD A,#data
ADDC A,R r
ADDC A,@R
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with
carry
ADDC A,#data Add immediate with
carry
ANL A,R r
And register to A
ANL A,@R
And data memory to A
ANL A,#data
And immediate to A
ORL A,R r
Or register to A
Or data memory to A
C5 ORL A,@R
~ ORL A,#data Or immediate to A
:s
XRL A,R r
Exclusive Or register
to A
« XRL A,@R
Exclusive Or data
memory to A
XRL A,#data
Exclusive Or immediate
to A
INC A
Increment A
DEC A
Decrement A
CLR A
Clear A
CPL A
Complement A
DA A
Decimal adjust A
SWAP A
Swap nibbles of A
RL A
Rotate A left
RLC A
Rotafe A left through
carry
RR A
Rotale A right
RRC A
Rotate A right through
carry
~
IN A, Pp
'S OUTLPpA
~ MOVD A,P p
e'S
CI.
MOVD Pp,A
.E
ANLD Pp.A
ORLD Pp.A
Input port to A
Output A to port
Inpu~ expander port
to A
Output A to expander
port
And A to expander port
Or A to expander port
Bytes CYCle
Hexadecimal
Opcode
1
1
1
1
2
2
1
1
1
1
6S-6F
60-61
03
7S-7F
70-71
2
2
13
1
1
2
1
1
1
1
2
1
1
2
1
5S-5F
50-51
53
4S-4F
40-41
43
DS-DF
1
1
DO-Dl
2
1
IX:
Increment register
Increment sata memory
JMP addr
rn
RET
2
03
1
1
1
1
1
1
1
17
07
27
37
57
47
E7
F7
1
1
1
1
1
1
1
1
1
1
1
1
77
1
67
CI CLR C
III
Li: CPL C
MOV A,R r
MOV A,@R
MOV A,#data
MOV Rr,A
MOV@ R,A
MOV Rr,#data
til
~
0
::E
co
III
c
MOV@R,#data
XCH A,R,
XCH A,@R
1
1
1
'2
2
OS,09,OA
90,39,3A
OC-OF
1
2
3C-3F
1
2
1
2
9C-9F
SC-SF
2
1
1
l
1
lS-1F
ttl-l1
XCHDA,@R
MOVP A,@A
~
0
MOV A,T
MOV T,A
~ STRT T
iii STRT CNT
E
i= STOP TCNT
Nap
Hexadecimal
Opcode
2
04,24,44,64,
1
2
2
2
B3
ES-EF
2
2
2
2
2
2
2
2
2
2
F6
E6
C6
96
56
46
16
Jump to subroutine
1
2
14,34,54,74
Return
1
2
S3
Clear carry
Complement carry
1
1
1
97
A7
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to
register
Move immediate to
data memory
Exchange A and
register
Exchange A and data
memory
Exchange nibble of A
and register
Move to A from current
page
1
1
2
r
1
2
1
2
t
1
2
FS-FF
FO-Fl
23
AS-AF
AO-Al
B8-BF
2
2
BO-B1
1
1
2S-2F
1
1
20-21
1
1
30-31
1
2
A3
1
1
1
1
62
Jump indirect
JMPP @ A
DJNZ R,ro addr Decrement register and
jump on R not zero
III
Jump on carry= 1
~ JC addr
Jump on carry=O
JNC addr
Jump on A zero
JZ addr
Jump on A not zero
JNZ addr
JT1 addr
Jump on Tl=1
JNT1 addr
Jump on T1=0
Jump on timer flag
JTF addr
~e CALL addr
Byles Cycle
2
Jump unconditional
g
til
2
Description
J:.
-g
til
~ INC Rr
': INC@R
Mnemonic
2
2
2
:2
1
1
Read timer I counter
Load timer I counter
Start timer
Start counter
Stop timer I counter
1
1
42
1
1
1
55
45
1
65
No operation
1
1
00
8021L
SINGLE COMPONENT 8-BIT MICROCOMPUTER
LOW POWER 10mA
CPU, ROM, RAM, I/O in Single
• 8-Bit
28-Pin Package
ROM
• 641K x8x 8 RAM
21 I/O Lines
•
J..Lsec Cycle With 3.58 MHz XTAL;
• 8.38
All instructions 1 or 2 Cycles
Single 5V Supply (+4.5V to 8V)
• Interval Timer/Event Counter
Generated With Single Inductor
• orClock
Crystal
• Instructions - 8048 Subset
• High Current Drive Capability-2 Pins
• Zero-Cross Detection Capability
• Easily Expandable I/O
The Intel® 8021 L is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using
Intel's N-channel silicon gate MOS process. The features of the 8021 L include a subset of the 8048 optimized
for low cost, high volume applications, plus additional 1/0 flexibility and power.
The 8021 L contains 1 K X 8 program memory, a 64 X 8 data memory, 21 1/0 lines, and an 8-bit timerlevent
counter, in addition to on-board oscillator and clock circuits. For systems that require extra 1/0 capability, the
8021 L can be expanded using the 8243 or discrete logic.
This microprocessor is designed to be an efficient controller as well as an arithmetic processor. The 8021 L has
bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of single byte instructions and no instructions over
two bytes in length.
To minimize the development problems and maximize flexibility, an 8021 L system can be easily designed using
the 8021 L emulation board, the EM-1. The EM-1 contains a 40-pin socket which can accommodate either the
8748 shipped with the board or an ICE-49 plug. Also, the necessary discrete logic to reproduce the 8021 L's
additional 1/0 features is included.
P22
PORT
XTAL\
#Q
PORT
#1
RESET
PORT
#2
TEST
ADDRESS
LATCH
ENABLE
PORT
EXPANDER
STROBE
Figure 2.
Logic Symbol
Figure 1.
Block Diagram
VCC
P23
P21
PROG
P20
POD
P17
POl
P16
P02
P15
P03
P14
P04
P13
P05
P06
P07
ALE
Pll
Pl0
RESET
T1
XTAL 2
Vss
XTAL 1
Figure 3. Pin
Configuration
Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent licenses are Implied.
©INTELCORPORATION,1980
AFN-01813A-Ol
7-4
8021L
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Ambient Temperature Under Bias ••••••• O°C to 70°C
Storage Tem perature •••••••••••• -65° C to +150° C
Voltage on Any Pin with
Respect to Ground ••••••••••••••• -0.5V to +7V
Power Dissipation. • • • • • • • • • • • • • • • • • • • • •• 1 W
D.C. CHARACTERISTICS
Symbol
TA = O°C to 70°C, VCC = 5.5V
Parameter
Min.
± 1V, VSS = OV
Limits
Typ. Max.
Unit
Test Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage (All except
XTAL 1 & 2, T1 RESET)
3.0
VCC
V
VIH1
Input High Voltage (XTAL 1 & 2,
T1 RESET)
3.8
VCC
V
VIH(10%)
Input high voltage (All except
1 & 2, T1, RESET)
2.0
VCC
V
VCC = 5.0V ± 10%
3.5
VCC
V
VCC = 5.0V ± 10%
0.45
V
IOL + 1.6 mA
2.5
V
IOL = 7 mA
V
IOH=40jJ.A
VIH1(10%) I nput high voltage (XTAL 1 & 2,
T1, RESET)
VOL
Output Low Voltage
VOL1
Output Low Voltage (P10, P11)
VOH
Output High Voltage
(All unless Open Drain)
ILO
Output Leakage Current
(Open Drain Option - Port 0)
ICC
VCC Supply Current
2.4
40
T1 ZERO CROSS CHARACTERISTICS
Symbol
Parameter
± 10
jJ.A
75
mA
VSS+0.45~VIN~VCC
TA = O°C to 70°C, VCC = 5.5V ± 1V, VSS = OV, CL = 80 pF
Min.
Max.
Unit
1
3
VPP
AC Coupled, C =.2jJ.F
± 135
mV
60 Hz Sine Wave
1
kHZ
VZX
Zero-Cross Detection Input (T1)
AZX
Zero-Cross Accuracy
FZX
Zero-Cross Detection Input
Frequency (T1 )
0.05
tCY
Cycle Time
8.38
50.0
7-5
Test Conditions
3.58 MHz "XTAL =
8.38 jJ.s tCY
AFN-01813A-02
8022
SINGLE COMPONENT a-BIT MICROCOMPUTER
WiTH ON-CHiP AID CONVERTER
• 8-Bit CPU, ROM, RAM, I/O in Single 40-Pin
• 2K x 8 ROM, 64 x 8 RAM, 28 I/O Lines
• On-Chip 8-Bit A/D Converter; Two Input
• 8.38 ~sec Cycle;
• 8 Comparator Inputs (Port 0)
• Zero-Cross Detection Capability
• Single SV Supply (4.SV to 6.SV)
• High Current Drive Capability-2 Pins
• Two Interrupts-External and Timer
• Instructions-8048 Subset
• Interval Timer / Event Counter
• Clock Generated with Single Inductor or
Package
All Instructions 1 or 2
Cycles
Channels
Crystal
• Easily Expanded I/O
The Intel@ 8022 is the newest member of the MCS-48™ family of single chip 8-bit microcomputers. It is designed to
satisfy the requirements of low cost, high volume applications which involve analog signals, capacitive touchpanel
keyboards, and / or large ROM space. The 8022 addresses these applications by integrating many new functions onchip, such as A / 0 conversion, comparator inputs and zero-cross detection.
The features of the 8022 include 2K bytes of program memory (ROM), 64 bytes of data memory (RAM), 28 I/O lines,
an on-chip A / 0 converter with two input channels, an 8-bit port with comparator inputs for interfacing to low voltage
capacitive touchpanels or other non-TTL interfaces, external and timer interrupts, and zero-cross detection capability. In addition, it contains the 8-bit interval timer / event counter, on-board oscillator and clock circuitry, single 5V
power supply requirement, and easily expandable I/O structure common to all members of the MCS-48 family.
The 8022 is designed to be an efficient controller as well as an arithmetic processor. It has bit handling capability
plus facilities for both binary and BCD arithmetic. Efficient use of program memory results from using the MCS-48
instruction set which consists mostly of single byte instructions and has extensive conditional jump and direct table
lookup capability. Program memory usage is further reduced via the 8022' s hardware implementation of the A /0
Vee
XTAL
r
PORTO
- - - THRESHOLD
REFERENCE
~8~)PORTO
RESET •
P26
Vee
P27
P2S
AVec
P24
PROG
VAREF
ANI
TEST O.
a:)PORTl
8022
TEST I .
~-:>PORT2
AID
REFERENCE
ADDRESS
--LATCH
ENABLE
ANO.
ANl
PORT
--EXPANDER
STROBE
t t
AID
Vee
Figure 1.
Block Diagram
P23
ANO
P22
AVss
P21
TO
P20
VTH
PH
POO
P16
POl
P1S
P02
P14
P03
P13
P04
P12
POS
Pll
P06
Pl0
P07
RESET
ALE
XTAL 2
Tl
XTAL 1
Vss
SUBST
t
• AID SUBSTRATE
Vss
Figure 2.
Logic Symbol
Figure 3. Pin
Configuration
Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
©INTELCORPORATION,1980
7-6
AFN-00187A-Ol
8022
Table 1. Pin Description
Deslgnation
Pin
No.
Deslgnation
Function
20
Circuit GND potential.
VCC
40
+ SV circuit power supply.
PROG
37
Output strobe for Intel@ 8243
I/O expander.
VSS
POO-P07
Port 0
VTH
P10-P17
10-17 8-bit open-drain port with comparator inputs. The switching
threshold is set externally by
VTH. Optional pull-up resistors
may be added via ROM mask
selection.
9
33-36 8-bit quasi-bidirectional port.
Port 2
38-39 P20-23 also serve as a 4-bit I/O
1-2 expander for Intel@ 8243.
T1
19
24
Input used to initialize the processor by clearing status flipflops and setting the program
counter to zero.
AVSS
7
AID converter GND Potential.
Also establishes the lower limit of
the conversion range.
AVCC
3
AID + SV power supply.
SUBST
21
Substrate pin used with a bypass
capacitor to stabilize the substrate voltage and improve AID
accuracy.
VAREF
4
AID converter reference voltage.
Establishes the upper limit of the
conversion range.
P20-P27
8
Function
RESET
Port 0 threshold reference pin.
2S-32 8-bit quasi-bidirectional port.
Port 1
TO
Pin
No.
Interrupt input and input pin
testable using the conditional
transfer instructions JTO and
JNTO. Initiates an interrupt following a low level input if interrupt is enabled. Interrupt is
disabled after a reset.
Input pin testable using the JT1
and JNT1 conditional transfer
instructions. Can be designated
the timerlevent counter input
using the STRT CNT instruction.
Also serves as the zero-cross
detection input to allow zerocrossover sensing of slowly moving AC inputs. Optional pull-up
resistor may be added via ROM
mask selection.
ANO, AN1
6,S
Analog inputs to AID converter.
Software selectable on-chip via
SEL ANO and SEL AN1 instructions.
ALE
18
Address Latch Enable. Signal
occurring once every 30 input
clocks (once every cycle), used
as an output clock.
XTAL 1
22
One side of crystal or inductor
input for internal oscillator. Also
input for external frequency
source. (Not TTL compatible.)
XTAL 2
23
Other side of timing control element. This pin is not connected
when an external frequency
source is used.
+SV
P10
Pll
P12
VAAEF
P13
P14
AVec
P1S
10-200"F
P16
P17
AVss
20
Vss
1"F
8022
SUBST
AID INPUTS
I
P21
P22
P23
P24
P2S
ANO
25
26
27
28
29
30
31
32
33
34
35
36
38
39
P26
P27
VTH
ANl
POO
POl
P02
XTALl
1M
P03
XTAL2
P04
POS
T1
P06
P07
1"F
10
11
12
13
14
15
16
}-,
}-,
},~o
17
Figure 3.The Stand Alone 8022
7.7
[ INPUT]
AND
OUTPUT
[ INPUT]
AND
OUTPUT
[ INPUT]
AND
OUTPUT
8022
........
~
• • • ~.- . . . . "
AI:J~VLU
•••••••
ft .........
"r-*
"'''vOTiCE: Stresses above those listed undei "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
I C MAAIMUM ""'. lI'fUo:J
Ambient Temperature Under Bias ....... 0° C to 70° C
Storage Temperature ............... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .................... -0.5V to +7V
Power Dissipation ............................ 1 Watt
D.C. CHARACTERISTICS
Symbol
TA = O°C to 70°C, VCC = 5.5V ± 1V, VSS = OV
Limits
Parameter
Min.
Unit
Typ.
Test Conditions
Max.
VIL
Input Low Voltage
-0.5
0.8
V
VIH1
Input Low Voltage (Port 0)
-0.5
VTH-Q.1
V
VIH
High Voltage
(All except XTAL 1, RESET)
2.0
VCC
V
VCC =5.0V ± 10%
VTH Floating
VIH1
Input High Voltage
(All except XTAL 1, RESET)
3.0
VCC
V
VCC =5.5V ± 1V
VTH Floating
VIH2
Input High Voltage (Port 0)
VTH+0.1
VCC
V
VIH3
Input High Voltage (RESET, XTAL 1)
3.0
VCC
V
VTH
Port 0 Threshold Reference Voltage
0
.4VCC
V
VTH Floating
VCC
=1.6 mA
=7 mA
IOH =50 p.A
VOL
Output Low Voltage
0.45
V
IOL
VOl1
Output Low Voltage (P10, P11)
2.5
V
IOl
VOH
Output High Voltage (all unless
Open Drain Option - Port 0)
V
2.4
=5.0V ± 10%
III
Input Current (T1)
±200
p.A
VCC~VIN;;?,VSS+.45V
ILO
Output Leakage Current
(Open Drain Option-Port 0)
± 10
p.A
VCC~VIN~
ICC
VCC Supply Current
100
mA
A.C. CHARACTERISTICS
Symbol
tcv
50
VSS+O.45V
TA = O°C to 70°C, VCC = 5.5V ± 1V, VSS = OV
Parameter
Cycle Time
VZX
Zero-Cross Detection Input (T1)
AZX
Zero-Cross Accuracy
FZX
Zero-Cross Detection Input
Frequency (T1)
Min.
Max.
Unit
8.38
50.0
p.S
1
0.05
3
VACpp
± 135
mV
1
kHz
Test Conditions
3 MHz XTAL = 10 p's tcv
AC Coupled
60 Hz Sine Wave
AFN-00187 A-Q3
8022
A.C. CHARACTERISTICS
Test Conditions: CL =80 pF
TA = O°C to 70°C, VCC = 5.5V ± 1V, VSS = OV
tCy=8.38 J.LS
Symbol
Parameter
Min.
tcp
Port Control Setup Before Falling Edge of PROG
0.5
tpc
Port Control Hold After Falling Edge of PROG
0.8
PROG to Time P2 Input Must Be Valid
Expander tpR
Operation top
7.0
tpo
Output Data Hold Time
8.3
tpF
Input Data Hold Time
tpp
PROG Pulse Width
tpRL
ALE to Time P2 Input Must Be Valid
0
Unit
J.LS
J.Ls
J.Ls
J.LS
.150
8.3
J.LS
J.LS
3.6
J.LS
Output Data Setup Time
0.8
J.LS
Output Data Hold Time
1.6
J.Ls
tpFl
Input Data Hold Time
tLl
ALE Pulse Width
0
3.9
Notes
J.LS
1.0
Output Data Setup Time
Normal tpl
Operation tLP
Max.
J.LS
23.0
tCy=8.38 J.Ls for min
j.1S
Port 2 Timing
--l
I--
NORMAL OPERATION
ILL
1\
ALEr\
PORT
OUTPUT
:=x
y--omy
IPL--j
.-r
1\
ALEr\
(
PORT
INPUT
I-
I - I LP
IpRL
-I
X
DATA
-1 r-
IPFL
EXPANDER OPERATION
ALE
r\
1\
I
\
PROG
IPORT
OUTPUT
XC6~~JOLX
ICPi-r
X
I--IPC
IDPi
x:=
DATA
--r- ~lpD
1\
ALE/\
PROG
PORT
INPUT
-I
Ipp
I
\
XCb~nOL >---<:
'C'~L
IpR
7n
~
DATA
x==
--ll--IPF
8022
AID CONVERTER CHARACTERISTICS TA =O"C io 70"C, vee = 5.5V ± 1V, Vss = av, AVec =5.5V ± 1V,
AVSS = OV, AVCC/2 ~ VAREF ~ AVCC
Parameter
Min.
Resolution
Typ.
Max.
Unit
Absolute Accuracy
.8% FSR ± V2 LSB
LSB
Sample Setup Before Falling Edge of ALE (t55)
0.20
tey
Sample Hold After Falling Edge of ALE (t SH )
0.10
tey
1
pF
Input Capacitance (ANO, AN1)
Conversion Time
Comments
Bits
8
4
4
(Note 1)
tey
Analog Input Timing
ALE
ANALOG
INPUT
NOTE
1. The analog input must be maintained at a constant voltage during the sample time (tss + t SH )'
7-10
AFN-00187A-05
8022
Table 2. Instruction Set Summary
Mnemonic
Description
Bytes Cycle
ADD A,R r
ADD A,@R
ADD A,#data
AD DC A,R r
ADDC A,@R
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with
carry
ADDC A,#data Add immediate with
carry
ANL A,R r
And register to A
ANL A,@R
And data memory to A
ANL A,#data
And immediate to A
ORL A,R r
Or register to A
ORL A,@R
Or data memory to A
ORL A,#data
Or immediate to A
XRL A,R r
Exclusive Or register
to A
XRL A,@R
Exclusive Or data
memory to A
XRL A,#data
Exclusive Or immediate
to A
INC A
Increment A
DEC A
Decrement A
CLR A
Clear A
CPL A
Complement A
DA A
Decimal adjust A
SWAP A
Swap nibbles of A
RL -A
Rotate A left
RLC A
Rotate A left through
carry
RR A
Rotate A right
RRC A
Rotate A right through
carry
::0
~
~
~
IN A, Pp
OUTL Pp.A
MOVD A.Pp
MOVD Pp,A
ANLD Pp.A
ORLD Pp.A
Input port to A
Output A to port
Input expander port
to A
Output A to expander
port
And A to expander port
Or A to expander port
Hexadecimal
Opcode
1
1
2
1
1
1
1
2
1
1
68-6F
60-61
03
78-7F
70-71
2
2
13
1
1
2
1
1
2
1
1
1
2
1
1
2
1
58-5F
50-51
53
48-4F
40-41
43
D8-DF
1
1
00-01
2
2
03
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
17
07
27
37
57
47
E7
F7
1
1
1
1
77
67
1
1
1
2
2
2
08,09,OA
90,39,3A
OC-OF
1
2
3C-3F
1
1
2
2
9C-9F
8C-8F
Mnemonic
Increment register
Increment data memory
1
1
1
1
18-1F
10-11
JMP addr
Jump unconditional
2
2
.l:
u
c:
JMPP@ A
DJNZ R,addr
co
cD JC addr
JNC addr
JZ addr
JNZ addr
Jump indirect
Decrement register and
jump on R not zero
Jump on carry= 1
Jump on carry=O
Jump on A zero
Jump on A not zero
1
2
2
2
2
2
2
2
2
2
2
2
F6
E6
C6
96
2
2
2
2
2
36
26
56
46
16
Jump to subroutine
1
2
RET
Return
1
2
14,34,54,74
94,B4,D4,F4
83
CLR C
Clear carry
Complement carry
1
1
1
1
97
A7
MOV A,R r
MOV A,@R
MOV A,#data
MOV Rr.A
MOV@ R,A
MOV Rr,#data
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to
register
Move immediate to
data memory
Exchange A and
register
Exchange A and data
memory
Exchange nibble of A
and register
Move to A from current
page
1
1
2
1
1
2
1
1
2
1
1
2
F8-FF
FO-F1
23
A8-AF
AO-A1
B8-BF
2
2
BO-B1
1
1
28-2F
1
1
20-21
CII
0
~
en
III
g'
ii: CPL C
III
~
0
::Ii
MOV@R,#data
co
OJ XCHA,R r
Q
XCH A,@R
1
1
30-31
1
2
A3
Read timer I counter
Load timer / counter
Start timer
Start counter
Stop timer / counter
1
1
1
1
1
1
1
1
1
1
42
62
55
45
65
Move conversion resuli
register to A
Select analog input
zero
Select analog input one
1
2
80
1
1
85
1
1
95
1
1
05
1
1
15
1
1
25
1
1
35
RET I
Enable external
interrupt
Disable external
interrupt
Enable timer! counter
interrupt
Disable timer / counter
interrupt
Return from interrupt
1
2
93
NOP
No operation
1
1
00
XCHD a,@R
MOVP A,@A
~
MOV A,T
MOV T,A
~ STRT T
~ STRT CNT
E STOP TCNT
j::
0
!
~
u
e
RAD
SEL ANO
SEL AN1
oCt
EN I
a:
04,24,44,64,
84,A4,C4,E4
B3
E8-EF
on
on
on
on
on
Hexadecimal
Opcode
2
2
2
2
2
~ CALL addr
0
INC Rr
INC@R
Jump
Jump
Jump
Jump
Jump
Bytes Cycle
TO= 1
TO=O
T1=1
T1 =0
timer flag
JTOaddr
JNTOaddr
JT1 addr
JNT1 addr
JTF addr
III
~.~
Description
DIS I
III
~
~
EN TCNTI
DIS TCNT!
SYMBOLS AND ABBREVIATIONS USED
P
A
addr
ANO,AN1
CNT
data
I
Accumulator
11-Bit Program Memory Address
Analog Input 0, Analog Input 1
Event Counter
8-Bit Number or Expression
Interrupt
Pp
Rr
T
TO, T1
#
@
7_11
Mnemonic for "in-page" Operation
Port Designator (P=O, 1, 2 or 4-7)
Register Designator (r=O-7)
Timer
Test 0, Test 1
Immediate Data Prefix
Indirect Address Prefix
8022H
HIGH PERFORMANCE
SINGLE COMPONENT 8-BIT MICROCOMPUTER
WITH ON-CHIP AID CONVERTER
• 2K x 8 ROM, 64 x 8 RAM, 28 I/O Lines
Cycle; All Instructions 1 or 2
• 5 f1sec
Cycles (6 MHz Clock)
Subset
• IInstructions-8048
nterval Time/Event Counter
• Clock
• CrystalGenerated with Single Inductor or
• Easily Expanded I/O
CPU, ROM, RAM, I/O in Single 40-Pin
• 8-Bit
Package
8-Bit A/D Converter; Two Input
• On-Chip
Channels
Comparator Inputs (Port 0)
• 8Zero-Cross
Detection Capability
• Single SV Supply
(4.SV to 6.SV)
• Two Interrupts-External
and Timer
•
The Intel@ S022H is designed to satisfy the requirements of low cost, high volume applications which involve
analog signals, capacitive touch panel keyboards, and/or large ROM space. The S022H addresses these
applications by integrating many new functions on-chip, such as A/D conversion, comparator inputs and
zero-cross detection.
The features of the S022H include 2K bytes of program memory (ROM), 64 bytes of data memory (RAM), 2S
I/O lines, an on-chip A/D converter with two input channels, an S-bit port with comparator inputs for
interfacing to low voltage capacitive touch panels or other non-TTL interfaces, external timer interrupts, and
zero-cross detection capability. In addition, it contains the S-bit interval timer/event counter, on-board
oscillator and clock circuitry, single 5V power supply requirement, and easily expandable I/O structure
common to all members of the MCS-4S family.
The S022H is designed to be an efficient controller as well as an arithmetic processor. It has bit handling
capability plus facilities for both binary and BCD arithmetic. Efficient use of program memory results from
using the MCS-4S instruction set which consists mostly of single byte instructions and has extensive
conditional jump and direct table lookup capability. Program memory usage is further reduced via the S022H's
hardware implementation of the A/D converter which simplifies interfacing to analog signals.
Vss
Vee
XTAL
r
PORTO
- - THRESHOLD
REFERENCE
=<>
RESET _
P26
Vee
P27
P25
AVec
PORTO
P24
PROG
VAREF
AN1
P23
P22
TEST ()..
~)PORT1
8022
TEST 1
P21
P20
VTH
P17
po~
P16
~)PORT2
P15
P14
AID
REFERENCE
P13
P04
ADDRESS
-LATCH
ENABLE
AN1
PORT
--EXPANDER
STROBE
P12
P05
P11
P06
P10
P07
RESET
ALE
XTAL 2
T1
XTAL 1
Vss
SUBST
l l l
AID
Vee
Figure 1.
Block Diagram
AID SU BSTRATE
Vss
Figure 2.
Logic Symbol
Figure 3. Pin
Configuration
Intel Corporation Assumes No Responsibility for the Use of any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
©INTELCORPORATION,1980
AFN·01814A
7.12
S04SH/S04SH-1/S035HLlS035H L-1
HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER
• 8048H/8048H·1 Mask Programmable ROM
• 8035HLl8035HL·1 CPU Only with Power Down Mode
CPU, ROM, RAM, 110 in Single
• 8·BIT
Package
Performance HMOS
• High
Reduced Power Consumption
• 1.4 J,lsec and 1.9 J,lsec Cycle Versions
• All
Instructions 1 or 2 Cycles
Over 90 Instructions: 70% Single Byte
•
1Kx8 ROM
• 64x
RAM
•
•
•
•
27110 Lines
Interval Timer/Event Counter
Easily Expandable Memory and 110
Compatible with 8080/8085 Series
Peripherals
Two Single Level Interrupts
The Intel® 8048H/8048H·1/8035HU8035HL-1 are totally self-sufficient, 8-bit parallel computers fabricated on single
silicon chips using Intel's advanced N-channel silicon gate HMOS process.
The8048H containsa 1KX8 program memory, a64X8 RAM data memory, 271/0 lines, and an 8-bit timer/counterin addition
to on-board oscillator and clock circuits. For systems that require extra capability the8048H can be expanded using standard memories and MCS-80® IMCS-85® peripherals. The 8035HL is the equivalent of the8048H without program memory
and can be used with external ROM and RAM.
To reduce development problems toa minimum and provide maximum flexibility, a logically and functionally pin compatible version of the8048H with UV-erasable user-programmable EPROM program memory is available. The87 48 will emulate
the 8048H up to 6 MHz clock frequency with minor differences.
The 8048H is fully compatible with the 8048 when operated at 6MHz.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have extensive bit
handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of program memory results from
an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
Vee
TO
PORT
01
XTAL 1
T1
XTAL 2
P27
P26
RESET
PORT
02
B04BH
B035HL
B04BH-1
B035HL-1
Figure 1.
Block Diagram
Figure 2.
Logic Symbol
55
P25
INT
P24
EA
PH
AD
P16
PSEN
P15
Wi!
P14
ALE
P13
DBO
P12
DB1
P11
DB2
P10
DB3
Voo
OB4
PROG
DBS
P23
DB6
P22
DB7
P21
Vss
P20
Figure 3. Pin
Configuration
(top view)
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent licenses are Implied.
INTEL CORPORATION, 1980
7-13
AFN-01491B-Ol
S04SH/S04SH-1 IS035H L/S035H L-1
Table 1. Pin Description
Symbol
Pin No.
Function
Symbol
VSS
20
Circuit GND potential
VDD
26
Low power standby pin
VCC
40
Main power supply; +5V during
operation.
PROG
25
Output strobe for 8243 I/O
expander.
P10-P17
Port 1
27-34
8-bit quasi-bidirectional port.
P20-P27
Port 2
21-24
8-bit quasi-bidirectional port.
35-38
P20-P23 contain the four high
order program counter bits during an external program memory
fetch and serve as a 4-bit I/O
expander bus for 8243.
-
True bidirectional port which
can be written or read
synchronously using the RD, WR
strobes. The port can also be
statically latched.
ALE
DBO-DB7
BUS
12-19
1
Input pin testable using the
conditional transfer instructions
JTO and JNTO. TO can be
designated as a clock output
using ENTO CLK instruction.
T1
39
Input pin testable using the JT1,
and JNT1 instructions. Can be
designated the timer/counter
input using the STRT CNT
instruction.
-
INT
6
Function
Also testable with conditional
jump instruction. (Active low)
-
RD
--RESET
WR
8
Output strobe activated during a
BUS read. Can be used to enable
data onto the bus from an
external device.
Used as a read strobe to external
data memory. (Active low)
4
Input which is used to initialize
the processor. (Active low)
(Non TTL VIH)
10
Output strobe during a bus write.
(Active low)
Used as write strobe to external
data memory.
Contains the 8 low order program counter bits during an
external program memory fetch,
and receives the addressed
instruction under the control of
PSEN. Also contains the address
and data during an external RAM
data store instruction, under
control of ALE, RD, and WR.
TO
Pin No.
--
PSEN
Address latch enable. This signal
occurs once during each cycle
and is useful as a clock output.
The negative edge of ALE strobes
address into external data and
program memory.
9
Program store enable. This output occurs only during a fetch to
external program memory.
(Active low)
SS
5
Single step input can be used
in conjunction with ALE to "single
step" the processor through each
instruction. (Active low)
EA
7
External access input which
forces all program memory
fetches to reference external
memory. Useful for emulation
and debug, and essential for
testing and program verification.
(Active high)
XTAL1
2
One side of crystal input for
internal oscillator. Also input for
external source. (Non TTL VIH)
XTAL2
3
Other side of crystal input.
-
Interrupt input. Initiates an
interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
11
AFN-01491B-02
7-14
S04SH/S04SH-1 IS035H L/S035H L-1
Table 2. Instruction Set
Accumulator
Mnemonic
ADD A, R
ADD A, @R
ADD A. # data
ADDC A, R
ADDC A, @R
ADDC A, # data
ANl A, R
ANl A, @R
ANl A, # data
ORl A, R
ORl A@R
ORl A, # data
XRl A, R
XRl A, @R
XRl, A, # data
INC A
DEC A
ClR A
CPl A
DA A
SWAP A
Rl A
RlC A
RR A
RRC A
Subroutine
Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Bytes Cycles
1
1
Mnemonic
CAll addr
RETR
RETR
Description
Increment register
Increment data memory
Decrement register
Description
Jump unconditional
Jump indirect
Decrement register and skip
Jump on carry = 1
Jump on carry = a
Jump on A zero
Jump on A not zero
Jump on TO = 1
Jump on TO = a
Jump on T1 = 1
Jump on T1 = a
Jump on Fa" 1
Jump on F1 = 1
Jump on timer flag
Jump on INT = a
Jump on accumulator bit
Bytes Cycles
1
1
Data Moves
Bytes Cycles
1
2
Timer/Counter
Bytes Cycles
1
Description
Read timer/counter
load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
Bytes Cycles
1
1
Mnemonic
EN 1
DIS 1
SEl RBO
SEl RB1
SEl MBa
SEl MB1
ENT a ClK
Description
Enable external interrupt
Disable external interrupt
Select register bank a
Select register bank 1
Select memory bank a
Select memory bank 1
Enable clock output on TO
Bytes Cycles
1
1
Mnemonic
NOP
Description
No operation
Bytes Cycles
1
1
Mnemonic
MOV A, T
MOV T, A
STRT T
STRT CNT
STOP TCNT
EN TCNT1
DIS TCNT1
1
Control
Branch
Mnemonic
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JN1 addr
JBb addr
Description
Clear carry
Complement carry
Clear flag a
Complement flag a
Clear flag 1
Complement flag 1
Mnemonic
Bytes Cycles
Description
Move register to A
1
1
MOV A, R
MOV A. @R
Move data memory to A
MOV A, # data
Move immediate to A
Move A to register
MOV R, A
MOV@R,A
Move A to data memory
MOV R, # data
Move immediate to register
MOV @R, #data Move immediate to data memory
MOV A, PSW
Move PSW to A
MOV PSW, A
Move A to PSW
XCH A, R
Exchange A and register
Exchange A and data memory
XCH A, @R
XCHD A, @R
Exchange nibble of A and
register
MOVX A, @R
Move external data memory to A
MOVX@R, A
Move A to external data memory
MOVPA, @A
Move to A from current page
MOVP3 A, @
Move to A from page 3
Registers
Mnemonic
INC R
INC@R
DEC R
Bytes Cycles
2
2
Flags
Mnemonic
ClR C
CPl C
ClR Fa
CPl Fa
ClR F1
CPl F1
Input/Output
Description
Mnemonic
Input port to A
IN A, P
OUTl P, A
Output A to port
ANl P, # data
And immediate to port
Or immediate to port
ORl P, # data
INS A, BUS
Input BUS to A
Output A to BUS
OUTl BUS, A
ANl BUS, # data And immediate to BUS
ORl BUS, # data Or immediate to BUS
Input expander port to A
MOVD A,P
Output A to expander port
MOVD P, A
ANlD P, A
And A to expander port
Or A to expander port
ORlD P, A
Description
Jump to subroutine
Return
Return and restore status
Bytes Cycles
2
2
AFN-01491B-03
7-15
S04SH/S04SH-1 IS035H L/S03SHL-1
ABSOLUTE MAXIMUM RATINGS*
*NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of device at these 0; any othSi conditions above those
indicated in the operational sections of this specification
is not implied.
Ambient Temperature Under Bias ....... O°C to 70°C
Storage Temperature ................ -65°C to +150°C
Voitage On Any Pin 'vVith Respect
to Ground ........................... -0.5V to +7V
Power Dissipation .......................... 1.5 Watt
D.C. CHARACTERISTICS
(TA = O°C to 70°C, VCC = VOO = 5V + 10%, VSS = OV)
Limits
Test Conditions
Unit
Parameter
Symbol
Min.
Typ.
Max.
VIL
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.8
V
V IL1
Input Low Voltage
(RESET, X1, X2)
-.5
.6
V
V IH
Input High Voltage
(All Except XTAL 1, XTAL2, RESET)
2.0
VCC
V
VIH1
Input High Voltage (X1, X2, RESET)
3.8
VCC
V
VOL
Output Low Voltage (BUS)
.45
V
IOL = 2.0 mA
V OL1
Output Low Voltage
(RO, WR, PSEN, ALE)
.45
V
IOL = 1.8 mA
VOL2
Output Low Voltage (PROG)
.45
V
IOL = 1.0 mA
V OL3
Output Low Voltage
(All Other Outputs)
.45
V
IOL = 1.6 mA
VOH
Output High Voltage (BUS)
2.4
V
IOH = -400fLA
VOH1
O~p~igh
Voltage
(RO, WR, PSEN, ALE)
2.4
V
IOH = -100fLA
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH = -40fLA
1L1
Input Leakage Current (T1, INT)
±10
--fLA
VSS~VIN~VCC
I Ll1
Input Leakage Current _
(p10-P17, P20-P27, EA, SS)
-500
fLA
VSS + .45~VIN~VCC
ILO
Output Leakage Current (BUS, TO)
(High Impedance State)
±10
fLA
VSS + .45~VIN~VCC
100
100 +
ICC
VOO Supply Current
4
8
mA
Total Supply Current
40
80
mA
VOO
RAM Standby Pin Voltage
5.5
V
BUS
·50 mA
J:
2.2
-500 JlA
-30 mA
J:
9
P1. P2
·300 Jl
...J
9
9
·10 mA
OV
4V
mA
30 mA
10 mA
·1001lA
2V
so
Standby Mode, Reset
OV
OV
VOH
VOH
~0.6V
BUS, P1, P2
~
~
2V
4V
VOL
AFN-014918-04
7-16
S04SH/S04SH-1 /S035H L-1 /S035H L-1
A.C. CHARACTERISTICS
Symbol
(TA = O°C to 70°C, VCC = VDD = 5V ± 10%, VSS = OV)
Parameter
F (tCY)
8048H
8048H-1
8035HL
8035HL-1
Conditions
8 MHz
11 MHz
6 MHz
(Note 1)
Min. Max. Min. Max. Min. Max. Unit
tLL
ALE Pulse Width
7/30 tCY -170
410
260
150
tAL
Addr Setup to ALE
1/5 tCY -110
390
260
160
tLA
Addr Hold from ALE
1/15 tCY -40
120
80
50
tCC1
Control Pulse Width
(RD, WR)
1/2 tCY -200
1050
730
480
tCC2
Control Pulse Width (PSEN) 2/5 tCY -200
800
550
350
tDW
Data Setup before WR
13/30 tCY -200
880
610
390
tWD
Data Hold after WR
1/5 tCY -150
350
220
tDR
Data Hold (RD, PSEN)
1/10 tCY -30
0
tRD1
RD to Data in
2/5 tCY -200
800
550
tRD2
PSEN to Data in
3/10 tCY -200
550
360
tAW
Addr Setup to WR
2/5 tCY -150
tAD1
Addr Setup to Data (RD)
23/30 tCY -250
tAD2
Addr Setup to Data (PSEN) 3/5 tCY -250
220
850
0
600
0
210
300
1670
1190
750
1250
880
480
Addr Float to RD, WR
2/15 tCY -40
290
210
tAFC2
Addr Float to PSEN
1/30 tCY -40
40
20
10
tLAFC1
ALE to Control (RD, WR)
1/5 tCY -75
420
300
200
tLAFC2
ALE to Control (PSEN)
1/10 tCY -75
170
110
60
tCA1
Control to ALE
(RD, WR, PROG)
1/15 tCY -40
120
80
50
140
tCA2
Control to ALE (PSEN)
4/15 tCY -40
620
460
320
tcp
Port Control Setup to PROG 1/10 tCY -40
210
140
100
tpc
Port Control Hold to PROG 4/15 tCY -200
460
300
tpR
PROG to P2 Input Valid
1300
160
940
650
tPF
Input Data Hold from PROG 1/10 tCY
tDP
Output Data Setup
tPD
tpp
Output Data Hold
1/10 tCY -50
200
130
90
PROG Pulse Width
7/10 tCY -250
1500
1060
700
tPL
Port 2 I/O Setup to ALE
4/15 tCY -200
460
300
160
tLP
Port 2 I/O Hold to ALE
1/10 tCY -100
150
80
tpv
Port Output from ALE
3/10 tCY +100
tCY
Cycle Time
tOPRR
TO Rep Rate
2/5 tCY -150
3/15 tCY
110
350
tAFC1
17/30tCY
-120
(Note 2)
120
160
250
0
190
600
850
850
0
140
400
40
510
660
2.5
1.875
1.36
500
370
270
Notes:
1. Control Outputs CL = 80pF
BUS Outputs CL = 1S0pF
2. BUS High Impedance Load 20pF
AFN-014918-05
S04SH/S04SH-1 IS035H L/S035H L-1
••• a
'I..~~"r.
.....
YY"'Yl:rvnm~
~ILAFC1
L
ALE
I
J
RD
IAFC1
I
r-
I
ICC1
-j
ICA1
j It: -\I
1-
L
tlDR
FLOATING
BUS
ALE
~ IAD1 S I R D 1
L
Jr-----'I
i--
WR
FLOATING
Read From External Data Memory
Instruction Fetch From External Program Memory
ILAFC1n
~
ICC1
---------------------~
~X ::~ ~ TEST POINTS ~::: X
. . ____
2.4V ----------__
O.4SV __________
~----
BUS
Input and Output for A.C.Tests.
Write to External Data Memory
PORT 2 TIMING
ALE
J
\'---_ _ _~V
_IICA1~
I,,,-I·'''l
EXPANDER
PORT
OUTPUT
\'------~/
PCH
r'DP-r'PI
PORT CONTROL
I
OUTPUT DATA
EXPANDER
PORT
INPUT
PCH
PORT 20-23 DATA
PROG
AFN-01491B-06
7-18
S04SH/S04SH-1 IS035H L/S035H L-1
1/0 PORT TIMING
1ST CYCLE
ALE
J
2ND CYCLE
I'" 1~~r'" 1
\
PSEN
j"-------'L
1 1'----1
I
- - - - I
\'--_----'f
I
~~~~~T~------------PC-H------------~)(r--------p-O-R-T-2-0--2-3-D-A-TA---------,~~----N-E-W-P-2-0--23--DA-T-A----J)(~------PC-H------
x. .____________________
P24-27
___________________________________________
...J
P10-17
PORT 24-27, PORT 10-17 DATA
OUTPUT
NEW PORT DATA
1
Crystal Oscillator Mode
LC Oscillator Mode
C1
~
-=
t----:'---...----;XTAL1
c,;~,
m
XTAL1
=
d
-=
t-~!--+----;XTAL2
C3
C1 " 5pF . 1/2pF. STRAY
5pF
C2 CRYSTAL' STRAY • 8pF
C3 20pF , 1 pF . STRAY·. 5pF
0
0
c
1
f~--
21njLC'
C'-~
L
C
3
2
Cpp'" 5-10 pF
PIN-TO-PIN
XTAL2
CAPACITANCE
C
NOMINAL f
20pF
20pF
5.2 MHz
3.2 MHz
EACH C SHOULD BE APPROXIMATELY 20pF.
INCLUDING STRAY CAPACITANCE
Driving From External Source
+5V
470Q
D - - - - < . - - - - - - I XTAL1
+5V
OPEN COLLECTOR
TTL GATES
470Q
'---"'---1
XTAL2
AFN-01491 B-07
7-1~
8048L
SPECIAL LOW POWER CONSUMPTION SINGLE
COMPONENT 8-BIT MICROCOMPUTER
• Typical Power Consumption 100mW
Standby Power 10mW
• Typical
VOD minimum of 2.2V
CPU, ROM, RAM, I/O in Single
• S-Bit
Package
J,lsec Instruction Cycle.
• 4.17
All Instructions 1 or 2 Cycles.
• Over 90 Instructions: 70% Single Byte
ROM
• 641K xx SSRAM
271/0 Lines
• Interval Timer/Event Counter
• Easily Expandable Memory and I/O
• Compatible with SOSO/SOS5 Series
Peripherals
• Two Single Level Interrupts
The Intel® 8048L is a totally self-sufficient 8-bit parallel computer fabricated on a single silicon chip using
Intel's advanced N-channel silicon gate HMOS process, using special techniques to reduce operating and
standby power consumption. The 8048L contains a 1K X 8 program memory, a 64 X 8 RAM data memory,
27 I/O lines, and an 8-bit timer/counter in addition to on-board oscillator and clock circuits. For systems that
require extra capability the 8048L can be expanded using standard memories and MCS-80®/MCS-85® peripherals. The 8048L can be used with external ROM and RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally
pin compatible version of the 8048L with UV-erasable user-programmable EPROM program memory is available. The 8748 will emulate the 8048L with greater power and other minor differences.
This microcontroller is designed to be an efficient controller as well as an arithmetic processor. The 8048L has
extensive bit handling capability as well as facilities for both binary and BCD arithmetiC. Efficient use of program memory results from an instruction set consisting mostly of single byte instructions and no instructions
over two bytes in length.
PORT
TO
XTAL 1
PORT
2
8048L
BUS
Figure 1.
8048L Block Diagram
Figure 2.
8048L Logic Symbol
Vee
T1
XTAL 2
P27
RESET
P26
55
fNT
P2S
EA
PH
P24
AD
P16
PSEN
WR
P14
ALE
P13
P1S
DBO
P12
DBl
Pll
DB2
Pl0
DB3
VDD
DB4
PROG
DBS
P23
DB6
P22
DB7
P2l
VSS
P20
Figure 3.
8048L Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied .
. INTEL CORPORATION, 1980
7-20
AFN-Q1591A-Ol
intel"
[F)OO~[bn[M]n~~OO\1
8048L
PIN DESCRIPTION
=
Designation
Pin
VSS
VDD
20
Circuit GND potential
26
low power standby pin
VCC
40
Main power supply; +5V
during operation.
PROG
25
Output strobe for 8243 I/O
expander.
P10-P17
Port 1
P20-27
Port 2
27-34
8-bit quasi-bidirectional
port.
8-bit quasi-bidirectional
port.
P20-P23 contain the four
high order program counter
bits during an external program memory fetch and
serve as a 4-bit I/O expander
bus for 8243.
21-24
35-38
DBO-DB7
BUS
12-19
Function
Designation
RD
Input pin testable using the
JT1, and JNT1 instructions.
Can be designated the
timer/counter input using
the STRT CNT instruction.
INT
6
Interrupt input. Initiates an
interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also
8
Output strobe activated
during a BUS read. Can be
used to enable data onto the
bus from an external device.
RESET
4
Input which is used to
initialize the processor.
(Active low)
(Non TTL VIH)
WR
10
Output strobe during a bus
write. (Active low)
Used as write strobe to
external data memory.
ALE
11
Address latch enable. This
signal occurs once during
each cycle and is useful as a
clock output.
The negative edge of ALE
strobes address into external data and program
memory.
Input pin testable using the
conditional transfer instructions JTO and JNTO. TO
can be designated as a clock
output using ENTO ClK
instruction.
39
Function
Used as a read strobe to
external data memory.
(Active low)
True bidirectional port
which can be written or read
synchronously using the
RD, WR strobes. The port
can also be statically
latched.
T1
=
testable with conditional
jump instruction.
(Active low)
Contains the 8 low order
program counter bits during
an external program
memory fetch, and receives
the addressed instruction
under the control of PSEN.
Also contains the address
and data during an external
RAM data store instruction,
under control of ALE, RD,
and WR.
TO
Pin
7.?1
PSEN
9
Program store enable. This
output occurs only during a
fetch to external program
memory. (Active low)
SS
5
Single step input can be
used in conjunction with
ALE to "single step" the
processor through each
instruction. (Active low)
EA
7
External access input which
forces all program memory
fetches to reference external
memory. Useful for emulation and debug, and
essential for testing and
program verification.
(Active high)
XTAl1
2
One side of crystal input for
internal oscillator. Also
input for external source.
(Non TTL VIH)
XTAl2
3
Other side of crystal input.
AFN-01S91A-02
inter
[F)[ffi ~[}J ~OOO&[ffiW
8048L
INSTRUCTION SET
Accumulator
Mnemonic
ADD A, R
ADDA,@R
ADD A, # data
ADDC A, R
ADDC A, @R
ADDC A, # data
ANL A, R
ANLA,@R
ANL A, # data
ORL A, R
ORLA@R
ORL A, # data
XRL A, R
XRL A, @R
XRL, A, # data
INC A
DEGA
CLR A
CPL A
DA A
SWAP A
RL A
RLCA
RR A
RRGA
Subroutine
Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Mnemonic
CALL addr
RET
RETR
Bytes Cycles
1
1
1
1
2
2
Description
Increment register
Increment data memory
Decrement register
Description
Jump unconditional
Jump indirect
Decrement register and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
Jump on TO = 1
Jump on TO = 0
JumponTl = 1
Jump on Tl = 0
Jump on FO = 1
Jump on Fl = 1
Jump on timer flag
Jump on INT = 0
Jump on accumulator bit
Bytes Cycles
1
1
Data Moves
Bytes Cycles
1
2
Timer/Counter
Description
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
Bytes Cycles
1
1
Mnemonic
EN 1
DIS 1
SEL RBO
SEL RBI
SEL MBO
SEL MBI
ENT 0 CLK
Description
Enable external interrupt
Disable external interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output on TO
Bytes Cycles
1
1
1
Mnemonic
NOP
Description
No operation
Bytes Cycles
1
1
MnemoniC
MOV A, T
MOV T, A
STRT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
Bytes Cycles
1
Control
Branch
Mnemonic
JMP addr
JMPP@A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTOaddr
JT1 addr
JNTI addr
JFO addr
JF1 addr
JTF addr
JNl addr
JBb addr
Description
Clear carry
Complement carry
CLear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
,
Bytes Cycles
Mnemonic
Description
MOV A, R
Move register to A
1
1
MOVA,@R
Move data memory to A
MOV A, # data
Move immediate to A
Move A to register
MOV R, A
MOV@R,A
Move A to data memory
MOV R, # data
Move immediate to register
MOV @R, #data Move immediate to data memory
MOVA,PSW
Move PSW to A
MOV PSW, A
Move A to PSW
XCH A, R
Exchange A and register
Exchange A and data memory
XCH A, @R
XCHD A, @R
Exchange nibble of A and
register
MOVX A, @R
Move external data memory to A
2
MOVX@R, A
Move A to external data memory
2
Move to A from current page
MOVPA, @A
2
MOVP3 A, @
2
Move to A from page 3
Registers
Mnemonic
INC R
INC@R
DEC R
Bytes Cycles
2
2
2
Flags
Mnemonic
CLR C
CPL C
CLR FO
CPL FO
CLR Fl
CPL Fl
Input/Output
Description
Mnemonic
IN A,P
Input port to A
Output A to port
oun P, A
ANL P, # data
And immediate to port
Or immediate to port
ORL P, # data
Input BUS to A
INS A, BUS
oun BUS, A Output A to BUS
ANL BUS, # data And immediate to BUS
ORL BUS, # data Or immediate to BUS
Inpu,t expander port to A
MOVD A,P
Output A to expander port
MOVD P, A
And A to expander port
ANLD P, A
Or A to expander port
ORLD P, A
Description
Jump to subroutine
Return
Return and restore status
Bytes Cycles
2
2
7-?2
AFN-01591A-03
8048L
ABSOLUTE MAXIMUM RATINGS·
• COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied.
Ambient Temperature Under Bias ....... 00 C to 70 0 C
Storage Temperature ............... -65 0 C to + 125 0 C
Voltage On Any Pin With Respect
to Ground ............................ -0.5V to +7V
Power Dissipation ......................... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS TA = O°C to 70°C, VCC = VOO =
5V ± 10%, VSS = OV
Limits
Symbol
Test Conditions
Unit
Parameter
Min.
Typ.
Max.
V IL
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.8
V
V IL1
Input Low Voltage
(RESET, X1, X2)
-.5
.6
V
V IH
Input High Voltage
(All Except XTAL1, XTAL2, RESET)
2.0
VCC
V
V IH1
Input High Voltage (X1, X2, RESET)
3.8
VOL
V OL1
VCC
.45
V
Output Low Voltage (BUS)
V
VOL
= 2.0
Output Low Voltage
(RO, WR, PSEN, ALE)
.45
V
IOL
=1.8
V OL2
Output Low Voltage (PROG)
.45
V
IOL
VOL3
Output Low Voltage
(All Other Outputs)
.45
V
IOL
=1.0 mA
=1.6 mA
V OH
V OH1
mA
mA
Output High Voltage (BUS)
2.4
V
IOH = -400 /-L A
Outp~igh
Voltage
(RO, WR, PSEN, ALE)
2.4
V
IOH
=-100
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH
=-40 /lA
1L1
Input Leakage Current (T1, INT)
± 10
/-LA
VSS
< VIN < VCC
IU1
Input Leakage Current
(P10-P17, P20-P27, EA, SS)
-500
IlA
VSS + .45~VIN~YCC
I LO
Output Leakage Current (BUS, TO)
(High Impedance State)
± 10
I1A
VSS + .45 ~VIN ~Ycc
100
V DO Supply Current
2
4
mA
100+
ICC
Total Supply Current
20
40
mA
VOO
Ram Standby Pin Voltage
5.5
V
2.2
BUS, Pl, P2
50 rnA
-500 /1A
:I:
:I:
.9
-' 30 rnA
-300 /1
.9
.9
-10 rnA
OV
10 rnA
-100/1A
4V
2V
Standby Mode, Reset:50.6V
Pl, P2
BUS
·50 rnA
OV
4V
2V
VOH
VOH
7_?1.
/-LA
OV
~
0
2V
4V
VOL
AFN-01591A-04
8048L
A.C. CHARACTERISTICS (PORT 2 TIMING)
TA =
oDe to 7oDe,
TCY
=4.17 J,JS
vcc = 5V
-+-
10%, Vss - OV
Symbol
Min.
Parameter
Max.
Unit
tcp
Port Control Setup Before Falling
Edge of PROG
185
ns
tpc
Port Control Hold After Falling
Edge of PROG
160
ns
tpR
PROG to Time P2 Input Must Be Valid
tpF
Input Data Hold Time
0
1.35
J..ls
250
ns
Test Conditions
ns
tDP
Output Data Setup Time
420
tpD
Output Data Hold Time
110
ns
tpp
PROG Pulse Width
2.0
J..ls
tpL
Port 2 I/O Data Setup
585
ns
tLP
Port 2 I/O Data Hold
250
ns
PORT 2 TIMING
ALE
J
\~---~y
EXPANDER
PORT
PCH
OUTPUT
PORT CONTROL
I
OUTPUT DATA
I
EXPANDER
PORT
INPUT
PCH
PORT 20 3 DATA
I
PROG
V
114.---tPP'----
------------------4~
I
I
BUS TIMING AS A FUNCTION OF TCY *
SYMBOL
SYMBOL
TRD (1)
TRD (2)
TAW
TCC (1) : RD/WR TAD (1)
TAD (2)
T cc (2) : PSEN
TAFC (1)
TAFC (2)
TCA (1)
TCA (2)
• APPROXIMATE VALUES NOT INCLUDING GATE DELAYS.
TLL
TAL
TLA
TCC (1)
TCC (2)
TOW
TWO
TOR
FUNCTION OF TCY
MIN
TCY
MIN
TCY
MIN
TCY
MIN
TCY
MIN
TCY
MIN
TCY
MIN
TCY
MIN
7/30
2/15
1/15
1/2
2/5
13/30
1/15
0
7-?A.
FUNCTION OF TCY
MAX
2/5
TCY
MAX
3/10
TCY
MIN
1/3
TCY
MAX
11/15
TCY
MAX
8/15
TCY
MIN
2/15
TCY
MIN
1/30
TCY
MIN
1/15
TCY
MIN
2/15
TCY
TRD (1) : RD
T RD (2) : PSEN
TAD (1) : RD
TAD (2) : PSEN
TAFC (1): RD
T AFC (2): PSEN
TCA (1) : RD, WR
T CA (2) : PSEN
AFN-01591 A-OS
8048L
WAVEFORMS
i_
4
· - - t L - L - _ - I - - tCY
ALE
J
-------1
,--I_ _ _----'1..------.L
I
--tAFC!_TCC-1 TCA
f.-
r------------
--------~--r_~
ALE
J
I
! _ tCC
RD
--------~I
tAFCj
BUS
BUS
tCA
t
f-- -[
IFLOATING
~
\-
tOR
-F-L-OA-T-IN-G---
l-tAD~1
Instruction Fetch From External Program Memory
ALE
-1
1
L
J
Read From External Data Memory
L
WR
~-----
2.4V - - - - - - . . . . .
.JX ~:~ ~
O.4SV _ _ _ _ _ _
TEST POINTS
::~:~X'-____
BUS
Write to External Data Memory
A.C. CHARACTERISTICS
Symbol
TA
=ODC to 70 DC,
Input and Output for A.C.Tests,
Vcc
= Voo = 5V + 10%, Vss = OV
Parameter
Unit
Min.
tLL
ALE Pulse Width
600
tAL
Address Setup to ALE
150
ns
80
ns
ns
tLA
Address Hold from ALE
tcc
Control Pulse Width (PSEN, RD, WR)
1500
ns
tow
Data Setup before WR
640
ns
two
Data Hold After WR
120
tCY
Cycle Time
4.17
tOR
Data Hold
tRO
PSEN, RD to Data In
tAW
Address Setup to WR
tAO
Address Setup to Data In
tAFC
Address Float to RD, PSEN
tCA
Control Pulse to ALE
Note 1: Control outputs:
BUS Outputs:
CL
C
L
0
Conditions (Note 1)
Max.
ns
15.0
200
ns
750
ns
260
CL
= 20pF
gs
ns
1450
ns
0
ns
20
ns
= 80 pF
= 150 pF
AFN-01591A-06
8048L
CRYSTAL OSCILLATOR MODE
~:f-l -::-lr-:-:--,L
. . . -.-~
-C-2
~ ~3:1-
XTAll
_ _L...--_----<
T_.-----'-I3 XTAl2
<
Cl = 5pF ± 1/2pF + STRAY 5pF
C2 = CRYSTAL + STRAY < 8pF
C3 = 20pF ± lpF + STRAY < 5pF
CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 75S} AT 6 MHz LESS THAN l80Q AT 3.6MHz
LC OSCILLATOR MODE
l
45pH
120pH
C
20pF
20pF
NOMINAL 1
5.2 MHz
3.2 MHz
1
F---
2rrIjLC
rt
-=
2
XTAll
C
C + Cpp
2
~
Jl
).
"'[C
Cpp 5-10 pF PIN TO PIN
CAPACITANCE
0
3 XTAl2
EACH C SHOULD BE APPROXIAMTELY 2OpF. INCLUDING STRAY CAPACITANCE
DRIVING FROM EXTERNAL SOURCE
+5V
470,1;1
D-......- - - - - ;
XTAll
+5V
470,1;1
' - - -......---1 XTAl2
XTAL 1 MUST BE HIGH 35-65% OF THE PERIOD AND XTAL 2 MUST BE HIGH 35-65% OF THE
PERIOD. RISE AND FALL TIMES MUST NOT EXCEED 20n8.
AFN-01S91A-07
S049H/S039HL
HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER
• 8049H Mask Programmable ROM
• 8039HL CPU Only with Power Down Mode
1K x S ROM
• 64
x S RAM
CPU, ROM, RAM, 1/0 in Single
• S-BIT
Package
27 1/0 Lines
• High Performance HMOS
• Reduced Power Consumption
1.4 usec and 1.9
Cycle Versions
• All
Instructions 1 or 2 Cycles.
• Over 90 instructions: 70% Single Byte
• Interval TimerlEvent Counter
• Easily Expandable Memory and 1/0
with SOSO/SOS5 Series
• Compatible
Peripherals
~sec
• Two Single Level Interrupts
The Intel® 8049H/8039HL are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.
The 8049H contains a 2K X 8 program memory, a 128 X 8 RAM data memory, 27 I/O lines, and an 8-bit
timer/counter in addition to on-board oscillator and clock circuits. For systems that require extra capability
the 8049H can be expanded using standard memories and MCS-80®/MCS-85® peripherals. The 8039HL is
the equivalent of the 8049H without program memory and can be used with external ROM and RAM.
To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally
pin compatible version of the 8049H with UV-erasable user-programmable EPROM program memory will
soon be available. The 8749 will emulate the 8049H up to 1 MHz clock frequency with minor differences.
The 8049H is fully compatible with the 8049.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no
instructions over 2 bytes in length.
TO
PORT
01
T1
XTAL 2
P27
RESET
PORT
02
8049H
8039HL
Vee
XTAL 1
4
P26
55
P2S
EA
PH
P24
AD
PSEN
WR
P16
9
P1S
P14
P13
P12
DB1
P11
DB2
P10
DB3
BUS
Figure 1.
Block Diagram
Figure 2.
Logic Symbol
VDD
DB4
PROG
DBS
P23
DB6
P22
DB7
P21
VSS
P20
Figure 3.
Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied
'INTEL CORPORATION, 1980
7-27
AFN-01784A-01
S049H/S039HL
Table 1. Pin Description
Symbol
Pin No.
Function
VSS
20
Circuit GND potential
VDD
26
low power standby pin
VCC
40
Main power supply; +5V during
operation.
PROG
25
Output strobe for 8243 I/O
expander.
Symbol
-
RD
--RESET
P10-P17
Port 1
27-34
8-bit quasi-bidirectional port.
P20-P27
Port 2
21-24
8-bit quasi-bidirectional port.
35-38
P20-P23 contain the four high
order program counter bits during an external program memory
fetch and serve as a 4-bit I/O
expander bus for 8243.
DBO-DB7
BUS
12-19
-
WR
True bidirectional port which
can be written or read
synchronously using the RD, WR
strobes. The port can also be
statically latched.
Contains the 8 low order program counter bits during an
external program memory fetch,
and receives the addressed
instruction under the control of
PSEN. Also contains the address
and data during an external RAM
data store instruction, under
control of ALE, RD, and WR.
TO
1
Input pin testable using the
conditional transfer instructions
JTO and JNTO. TO can be
designated as a clock output
using ENTO ClK instruction.
T1
39
Input pin testable using the JT1,
and JNT1 instructions. Can be
designated the timer/counter
input using the STRT CNT
instruction.
INT
6
Pin No.
Function
8
Output strobe activated during a
BUS read. Can be used to enable
data onto the bus from an
external device.
Used as a read strobe to external
data memory. (Active low)
4
Input which is used to initialize
the processor. (Active low)
(Non TTL V IH )
10
Output strobe during a bus write.
(Active low)
Used as write strobe to external
data memory.
ALE
11
Address latch enable. This signal
occurs once during each cycle
and is useful as a clock output.
The negative edge of ALE strobes
address into external data and
program memory.
PSEN
9
SS
Program store enable. This output occurs only during a fetch to
external program memory.
(Active low)
5
Single step input can be used
in conjunction with ALE to "single
step" the processor through each
instruction. (Active low)
EA
7
External access input which
forces all program memory
fetches to reference external
memory. Useful for emulation
and debug, and essential for
testing and program verification.
(Active high)
XTAL1
2
One side of crystal input for
internal oscillator. Also input for
external source. (Non TTL V IH )
XTAl2
3
Other side of crystal input.
Interrupt input. Initiates an
interrupt if interrupt is enabled.
Interrupt is disabled after a reset.
Also testable with conditional
jump instruction. (Active low)
7-28
AFN-01784A-02
S049H/S039HL
Table 2. Instruction Set
Subroutine
Accumulator
Mnemonic
ADD A. R
ADD A.@R
ADD A. # data
ADDC A. R
ADDC A.@R
ADDC A. # data
ANL A. R
ANL A. @R
ANL A. # data
ORL A. R
ORL A@R
ORL A. # data
XRL A. R
XRL A. @R
XRL. A. # data
INC A
DEC A
CLR A
CPL A
DAA
SWAP A
RL A
RLC A
RR A
RRC A
Description
Add register to A
Add data memory to A
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
Mnemonic
CALL addr
RETR
RETR
Bytes Cycles
1
1
Description
Increment register
Increment data memory
Decrement register
Description
Jump unconditional
Jump indirect
Decrement register and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump on A not zero
Jump on TO = 1
Jump on TO = 0
Jump on T1 = 1
Jump on T1 = 0
Jump on FO = 1
Jump on F1 = 1
Jump on timer flag
Jump on INT = 0
Jump on accumulator bit
Bytes Cycles
1
1
Data Moves
Bytes Cycles
1
2
Timer/Counter
Bytes Cycles
1
1
Description
Read timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter interrupt
Disable timer/counter interrupt
Bytes Cycles
1
1
Mnemonic
EN 1
DIS 1
SEL RBO
SEL RB1
SEL MBO
SEL MB1
ENT 0 CLK
Description
Enable external interrupt
Disable external interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable clock output on TO
Bytes. Cycles
1
1
Mnemonic
NOP
Description
No operation
Bytes Cycles
1
1
Mnemonic
MOV A. T
MOV T. A
STRT T
STRT CNT
STOP TeNT
EN TCNT1
DIS TCNT1
1
Control
Branch
Mnemonic
JMP addr
JMPP@A
DJNZ R. addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JN1 addr
JBb addr
Description
Clear carry
Complement carry
CLear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Mnemonic
Bytes Cycles
Description
1
1
Move register to A
MOV A. R
Move data memory to A
MOVA.@R
Move immediate to A
MOV A. # data
Move A to register
MOV R. A
Move A to data memory
MOV@R.A
Move immediate to register
MOV R. # data
MOV @R. #data Move immediate to data memory
Move PSW to A
MOVA. PSW
Move A to PSW
MOV PSW. A
Exchange A and register
XCH A. R
XCH A. @R
Exchange A and data memory
Exchange nibble of A and
XCHD A. @R
register
Move external data memory to A
MOVX A. @R
Move A to external data memory
MOVX @R. A
MOVPA.@A
Move to A from current page
2
MOVP3 A. @
2
Move to A from page 3
Registers
Mnemonic
INC R
INC@R
DEC R
Bytes Cycles
2
2
Flags
Mnemonic
CLR C
CPL C
CLR FO
CPL FO
CLR F1
CPL F1
Input/Output
Description
Mnemonic
Input port to A
IN A. P
Output A to port
OUTL P. A
And immediate to port
ANL P. # data
ORL p. # data
Or immediate to port
INS A. BUS
Input BUS to A
OUTL BUS. A
Output A to BUS
ANL BUS. # data And immediate to BUS
ORL BUS. # data Or immediate to BUS
MOVD A.P
Input expander port to A
MOVD P. A
Output A to expander port
ANLD P. A
And A to expander port
ORLD P. A
Or A to expander port
Description
Jump to subroutine
Return
Return and restore status
Bytes Cycles
2
2
2
2
2
2
7-29
AFN-01784A-03
Intel
S049H/S039H L
*NOTlCE:Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ....... 0° C to 70° C
Stoiage Temperature .............. -65°C to + 150°C
Voltage On Any Pin With Respect
to Ground ........................... -0.5V to +7V
Power Dissipation .......................... 1.5 Watt
D.C. CHARACTERISTICS
Symbol
(TA = O°C to 70°C, VCC = VDD = 5V ± 10%, VSS = OV)
Limits
Parameter
Min.
Typ.
Unit
Test Conditions
Max.
VIL
Input Low Voltage
(All Except RESET, X1, X2)
-.5
.8
V
VIL1
Input Low Voltage
(RESET, X1, X2)
-.5
.6
V
V IH
Input High Voltage
(All Except XTAL 1, XTAL2, RESET)
2.0
VCC
V
VIH1
Input High Voltage (X1, X2, RESET)
3.8
VCC
V
VOL
Output Low Voltage (BUS)
.45
V
IOL = 2.0 mA
VOL1
Outp~ow
Voltage
(RD, WR, PSEN, ALE)
.45
V
IOL=1.8mA
VOL2
Output Low Voltage (PROG)
.45
V
IOL = 1.0 mA
VOL3
Output Low Voltage
(All Other Outputs)
.45
V
IOL = 1.6 rnA
VOH
Output High Voltage (BUS)
2.4
V
IOH=-400 JlA
VO H 1
Outp~High
Voltage
(RD, WR, PSEN, ALE)
2.4
V
IOH=-100 JlA
VOH2
Output High Voltage
(All Other Outputs)
2.4
V
IOH =-40 Jl A
1L1
Input Leakage Current (T1, INT)
:!:. 10
fLA
VSS $ VIN $ VCC
IU1
Input Leakage Current _
(P10-P17, P20-P27, EA, SS)
-500
fLA
VSS + .45 ~ VIN:5 VCC
ILO
Output Leakage Current (BUS, TO)
(High Impedance State)
.± 10
fLA
VSS + .45:$ VIN
IDD
V DD Supply Current
5
10
mA
IDD +
Total Supply Current
50
100
mA
:5 VCC
~CC
BUS, Pl, P2
Pl. P2
BUS
·50 mA
50 mA
-500/lA
:z: -300
:z:
9
/l
....I
9
9
10 mA
-100/lA
OV
4V
2V
OV
30 mA
4V
2V
VOH
VOH
7-30
OV
~
~
2V
4V
VOL
AFN-01784A-04
S049H/S039HL
A.C. CHARACTERISTICS
(TA = O°C to 70°C, VCC = VDD = 5V ± 10%, VSS =OV)
f (tCY)
Parameter
Symbol
(Note 3)
11 MHz
Min.
Max.
Unit
tLL
ALE Pulse Width
7/30 tCY -170
150
ns
tAL
Addr Setup to ALE
1I5tCy-110
160
ns
tLA
Addr Hold from ALE
1/15 tCY -40
50
ns
tCC1
Control Pulse Width (RD, WR)
1/2 tCY -200
480
ns
--
tCC2
Control Pulse Width (PSEN)
2/5 tCY -200
350
ns
tow
Data Setup before WR
13/30 tCY -200
390
ns
two
Data Hold after WR
1/5 tCY -150
120
ns
1/10 tCY -30
0
tOR
Data Hold
--(RD, PSEN)
-
110
ns
tRD1
RD to Data in
2/5 tCY -200
350
ns
tRD2
PSEN to Data in
3/10 tCY -200
210
ns
tAW
Addr Setup to WR
2/5 tCY -150
-
Addr Setup to Data (RD)
23/30 tCY -250
750
ns
tAD2
Addr Setup to Data (PSEN)
3/5 tCY -250
480
ns
t AFC1
-Addr Float to RD, WR
2/15 tCY -40
140
ns
tAFC2
Addr Float to PSEN
1/30 tCY -40
10
ns
200
ns
tLAFC1
ALE to Control, (RD, WR)
1/5t Cy-75
tLAFC2
ALE to Control (PSEN)
1/10 tCY -75
60
ns
tCA1
Control to ALE (RD, WR, PROG)
1/ 15t Cy-40
50
ns
tCA2
-Control to ALE (PSEN)
4/15 tCY -40
320
ns
tcp
-Port Control Setup to PROG
1110 tCY -40
100
ns
tpc
Port Control Hold to PROG
4/15 tCY -200
160
ns
tpR
PROG to P2 Input Valid
17/30 tCY -120
tpF
-Input Data Hold from PROG
1110 tCY
top
Output Data Setup
2/5 tCY -150
400
ns
tpD
Output Data Hold
1/10 tCY -50
90
ns
tpp
PROG Pulse Width
7/10 tCY -250
700
ns
tPL
Port 2 I/O Setu p to ALE
4/15 tCY -200
160
ns
t LP
Port 2 I/O Hold to ALE
1/10 tCY -100
40
ns
tpv
Port Output from ALE
3/10 tCY +100
tCY
Cycle Time
t
to Rep Rate
OPRR
Notes:
1. Control Outputs CL = 80pF
BUS Outputs CL = 150pF
3/15 tCY
2. BUS High Impedance Load 20pF
7-31
0
(Note 2)
ns
300
tAD1
--
Conditions
(Note 1)
650
ns
140
ns
510
ns
1.36
IJs
270
ns
3. Calculated values will be equal
to or better than published 8049 values.
AFN-01784A-05
S049H/S039HL
WAVEFORMS
----.l
TLAFC1
J---\L..__
RD
------i\
BUS
Jr"------.
r-
ICC1
-..j
~
IAD1
I~
FLOATING
i·
1-
ICA1
1
-I
tlDR
_ _ _ _ __
~
FLOATING
:IIRD1
Read From External Data Memory
Instruction Fetch From External Program Memory
ALE
L
1
1_ _ _ _.....
IAFC1j
---..j
L
ALE
T LAFC1
ICA1
1---
L
r----_____
WR
2.4V - - - - _ _
0.4SV _ _ _ _
--JX~:: ~ TEST POINTS ~:::X'"
BUS
Input and Output for A.C. Tests
Write to External Data Memory
PORT 2 EXPANDER TIMING
ALE
J
\
\----------!
/
'------~lrICA1
EXPANDER
PORT
OUTPUT
rIDP-ttPDl
PCH
PORT 20-23 DATA
I
PORT CONTROL
1001-----
EXPANDER
PORT
I
OUTPUT DATA
IpR - - - - - . I
I
INPUT
PCH
PORT 20-23 DATA
PORT CONTROL
PROG
7-32
AFN-01784A-06
S049H/S039HL
1/0 PORT TIMING
1ST CYCLE
2ND CYCLE
I-' 1-----,t 1
ec
ALE
J
\
1 1'-----1
I
PSEN
/'--'----'L
'ev
- - - - I
\-------1/
I
~~~~~T~~----------PC-H------------~)(~-------P-O-R-T-2-0--2-3-D-A-TA--------~)(~____N_E_W_P_2_0-_23__DA_T_A____J)(~
______
PC_H
______
I
P24-27
----------------------------------------------------------~xr---------------------------------OUTPUT __________________________________________________________
- J ~______________________________
___
P10-17
PORT 24-27, PORT 10-17 DATA
NEW PORT DATA
1
OSCILLATOR MODE
LC OSCILLATOR MODE
C1
1----,--.....--tXTAL1
~ e';t' =
3
C3
C1
C2
C3
m
JC
1-~!--....--tXTAL2
':'
XTAL1
=5pF ± 1/2pF + STRAY < 5pF
= CRYSTAL ± STRAY < 8pF
= 20pF + 1pF ± STRAY < 5pF
CRYSTAL SERIES RESISTANCE SHOULD
BE LESS THAN 75 II AT 6MHz; LESS THAN
180 II AT 3.6MHz.
~C
':'
L
3
DRIVING FROM
EXTERNAL SOURCE
,. - 1
+5V
27TVLC'
C = 3Cpp
C'=--2-
Cpp'" 5-10 pF
PIN-TO-PIN
CAPACITANCE
470Q
)o-~"""------1 XTAL1
+5V
XTAL2
C
NOMINAL'
20pF
20pF
5,2 MHz
3.2 MHz
EACH C SHOULD BE APPROXIMATELY 20pF,
INCLUDING STRAY CAPACITANCE.
OPEN
COLLECTOR
TTL GATES
470 Q
3
XTAL2
FOR THE 8048, XTAL 1 MUST BE HIGH
35-65% OF THE PERIOD AND XTAL2
MUST BE HIGH 35-65% OF THE PERIOD
RISE AND FALL TIMES MUST
NOT EXCEED 20n5
7-33
AFN-01784A-07
8243
MCS-48® INPUT/OUTPUT EXPANDER
•
•
•
•
Low Cost
Simple Interface to MCS-48®
Microcomputers
Four 4-Bit 1/0 Ports
AND and OR Directly to Ports
• 24-Pin DIP
• Single 5V Supply
• High Output Drive
• Direct Extension of Resident 8048 1/0
Ports
The Intel® 8243 is an input/output expander designed specifically to provide a low cost means of 1/0
expansion for the MCS-48® falT)ily of single chip microcomputers. Fabricated in 5 volts NMOS, the 8243
combines low cost, single supply voltage and high drive current capability.
The 8243 consists of four 4-bit bidirectional static 1/0 ports and one 4-bit port which serves as an interface to
the MCS-48 microcomputers. The 4-bit interface requires that only 4 1/0 lines of the 8048 be used for 1/0
expansion, and also allows multiple 8243's to be added to the same bus.
The 1/0 ports of the 8243 serve as a direct extension of the resident 1/0 facilities of the MCS-48 microcomputers
and are accessed by their own MOV, ANL, and ORL instructions.
PORT4
PORTS
PORT 2
PORT 6
PSO
vee
P40
PS1
1'41
P52
Pt12
PS3
P43
P60
CS
P61
PROG
P62
P23
P63
P22
P73
P21
P72
P20
P71
GND
P70
PORT 7
Figure 2. 8243
Pin Configuration
Figure 1. 8243
Block Diagram
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
'INTEL CORPORATION. t980
7-34
AFN-D0214A-Ol
8243
Table 1. Pin Description
Symbol Pin No.
PROG
7
Clock Input. A high to low transition on PROG signifies that address and control are available on
P20-P23, and a low to high transition signifies that data is available
on P20-P23.
CS
6
Chip Select Input. A high on CS
inhibits any change of output or
internal status.
P20-P23
GND
11-8
12
P40-P43
2-5
P50-P53 1, 23-21
P60-P63 20-17
P70-P73 13-16
VCC
24
Power On Initialization
Initial application of power to the device forces
input/output ports 4, 5, 6, and 7 to the tri-state and
port 2 to the input mode. The PROG pin may be
either high or low when power is applied. The first
high to low transition of PROG causes device to
exit power on mode. The power on sequence is
initiated if vee drops below 1V.
Function
P21 P20
Four (4) bit bi-directional port contains the address and control bits
on a high to low transition of
PROG. During a low to high transition contains the data for a selected output port if a write operation, or the data from a selected
port before the low to high transition if a read operation.
0
0
Address
Code
0
1
0
Port
Port
Port
Port
4
5
6
7
P23 P22
0
0
0
1
0
Instruction
Code
Read
Write
ORlD
ANlD
Write Modes
o volt supply.
The device has three write modes. MOVD Pi, A directly writes new data into the selected port and old
data is lost. ORlD Pi, A takes new data, OR's it with
the old data and then writes it to the port. ANlD Pi, A
takes new data, AND's it with the old data and then
writes it to the port. Operation code and port address are latched from the input port 2 on the high
to low transition of the PROG pin. On the low to high
transition of PROG data on port 2 is transferred to
the logic block of the specified output port.
Four (4) bit bi-directional I/O ports.
May be programmed to be input
(during read), low impedance
latched output (after write), or a tristate (after read). Data on pins
P20-P23 may be directly written,
ANDed or ORed with previous
data.
+5 volt supply.
After the logic manipulation is performed, the data
is latched and outputed. The old data remains
latched until new valid outputs are entered.
FUNCTIONAL DESCRIPTION
General Operation
The 8243 contains four 4-bit 1/0 ports which serve
as an extension of the on-chip 1/0 and are addressed as ports 4-7. The following operations may
be performed on these ports:
Read Mode
All communication between the 8048 and the 8243
occurs over Port 2 (P20-P23) with timing provided
by an output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles:
The device has one read mode. The operation code
and port add ress are latched from the input port 2 on
the high to low transition of the PROG pin. As soon
as the read operation and port address are decoded,
the appropriate outputs are tri-stated, and the input
buffers switched on. The read operation is terminated by a low to high transition of the PROG pin. The
port (4,5,6 or 7) that was selected is switched to the
tri-stated mode while port 2 is returned to the input
mode.
The first containing the "op code" and port address
and the second containing the actual 4-bits of data.
A high to low transition of the PROG line indicates
that address is present while a low to high transition
indicates the presence of data. Additional 8243's
may be added to the 4-bit bus and chip selected
using additional output lines from the 8048/87481
8035.
Normally, a port will be in an output (write mode) or
input (read mode). If modes are changed during
operation, the first read following a write should
be ignored; all following reads are valid. This is to
allow the external driver on the port to settle after
the first read instruction removes the low impedance drive from the 8243 output. A read of any port
will leave that port in a high impedance state.
•
•
•
•
Transfer Accumulator to Port.
Transfer Port to Accumulator.
AND Accumulator to Port.
OR Accumulator to Port.
7-35
AFN-00214A-02
8243
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ........ O°C to 70°C
Storage Temperature ............... -65°C to +150°C
Voltage on Any Pin
With Respect to Ground .............. -0.5 V to +7V
Power Dissipation ............................ 1 Watt
D.C. CHARACTERISTICS
Symbol
TA = O°C to 70°C, VCC = 5V
Min.
Parameter
10%
Typ.
Max.
Test
Conditions
Units
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC+0.5
V
VOL1
Output Low Voltage Ports 4-7
0.45
V
IOL = 4.5 mA'
VOL2
Output Low Voltage Port 7
1
V
IOL = 20 mA
VOH1
Output High Voltage Ports 4-7
2.4
1IL1
Input Leakage Ports 4-7
-10
-10
IIL2
Input Leakage Port 2, CS, PROG
VOL3
Output Low Voltage Port 2
ICC
VCC Supply Current
VOH2
Output Voltage Port 2
IOL
Sum of all IOL from 16 Outputs
V
10
IOH = 240/-LA
20
/-LA
Vin = VCC to OV
Vin = VCC to OV
10
/-LA
.45
V
20
mA
72
mA
IOL = 0.6 mA
2.4
IOH = 100/-LA
4.5 mA Each Pin
'See following graph for additional sink current capability
A.C. CHARACTERISTICS
Symbol
TA = O°C to 70°C, VCC = 5V
Min.
Parameter
10%
Max.
Units
Test Conditions
100
ns
Code Valid After PROG
60
ns
20 pF Load
Data Valid Before PROG
200
ns
80 pF Load
ns
20 pF Load
ns
20 pF Load
tA
Code Valid Before PROG
tB
tc
tD
Data Valid After PROG
tH
Floating After PROG
tK
PROG Negative Pulse Width
700
tcs
tpo
CS Valid Before! After PROG
50
tLP1
Ports 4-7 Valid Before! After PROG
tACC
Port 2 Valid After PROG
20
0
Ports 4-7 Valid After PROG
150
80 pF Load
ns
ns
700
100
ns
100 pF Load
ns
650
ns
80 pF Load
-----'X > <::x_
20
2.4
0 •.8
TEST POINTS
0.45----
7-36
AFN-00214A-03
8243
WAVEFORMS
PROG
IK
10
PORT2
FLOAT
'ACC
=>1 ~'Hx
FLOAT
OUTPUT
VALID
PORT2
IpO
PORTS 4-7
OUTPUT
VALID
PREVIOUS OUTPUT VALID
--
liP
PORTS 4-7
liP
INPUT VALID
ICS
ICS
7-37
AFN-00214A-04
Intel
8243
125
I
100
75
50
OF ANY I/O PORT PIN va. TOTAL
SINK CURRENT OF ALL PINS
25
10
11
12
13
MAXIMUM SINK CURRENT ON ANY PIN @ .45V
MAXIMUM 10L WORST CASE PIN (mAl
Figure 3
Example: This example shows how the use of the 20 mA
sink capability of Port 7 affects the sinking
capability of the other 1/0 lines.
Sink Capability
The 8243 can si nk 5 rnA @ .45V on each of its 16 I/O
lines simultaneously. If, however, all lines are not
sinking simultaneously or all lines are not fully
loaded, the drive capability of any individual line
increases as is shown by the accompanying curve.
An 8243 will drive the following loads simultaneously.
For example, if only 5 of the 16 lines are to sink
current at one time, the curve shows that each of
those 5 lines is capable of sinking 9 mA @ .45V (if
any lines are to sink 9 mA the total IOL must not
exceed 45 rnA or five 9 mA loads).
2 loads-20 mA @ 1V (port 7 only)
8 loads-4 mA @ .45V
610ads-3.2 mA @ .45V
Is this within the specified limits?
Example: How many pins can drive 5 TTL loads (1.6 mA)
assuming remaining pins are unloaded?
10l = 5 x 1.6 mA = 8 mA
flOl = 60 mA from curve
# pins =60 mA + 8 mAlpin
flOl = (2 x 20) + (8 x 4) + (6 x 3.2) = 91.2 mA.
From the curve: for 10l = 4 mA, flOl "'" 93 mA.
since 91.2 mA < 93 mA the loads are within
specified limits.
=7.5 =7
Although the 20 mA @ 1V loads are used in
calculating fiOL. it is the largest current required @ .45V which determines the maximum
allowable EiOl.
I n this case, 7 lines can sink 8 mA for a total of
56mA. This leaves 4 mA sink current capability
which can be divided in any way among the
remaining 8 1/0 lines of the 8243.
NOTE: A 10 to SOK 0 pullup resistor to +SV should be added to 8243 outputs when driving to SV CMOS directly.
7-38
AFN-oG214A-05
8243
-::-
cs
I/O
PROG
P4
I/O
P5
I/O
P6
I/O
P7
I/O
PROG
TEST
INPUTS
8048
8243
DATA IN
P2
P20·P23
Figure 4. Expander Interface
PROG
P20·P23
~\\....-._ _ _--J/
BITS 3,2
.IX'--_____.I)>-----
BITS 1,0
OO} READ
01
10
WRITE
OR
OO}
lL
AND
11
01
10
PORT
ADDRESS
- - { " '_ _ _
ADDRESS (4-BITS)
DATA (4-BITS)
Figure 5. Output Expander Timing
BUS
PORT 1
8048
PROG~---------------+----------------~----------------~~--------------~
Figure 6. Using Multiple 8243's
7-39
AFN-00214A-06
inter
8155/8156/8155-2/8156-2
2048 BIT STATIC MOS RAM WITH 1/0 PORTS AND TIMER
•
• 256 Word x 8 Bits
1 Programmable 6-Bit I/O Port
•
Single +5V Power Supply
•
•
Completely Static Operation
•
Internal Address Latch
Programmable 14-Bit Binary Counter/
Timer
• Compatible with 808SA and 8088 CPU
• Multiplexed Address and Data Bus
•
2 Programmable 8 Bit I/O Ports
• 40 Pin DIP
The 8155 and 8156 are RAM and I/O chips to be used in the 8085A and 8088 microprocessor systems. The RAM portion
is designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit use with
no wait states in 8085A CPU. The 8155·2 and 8156·2 have maximum access times of 330 ns for use with the 8085A·2 and
the full speed 5 MHz 8088 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status
pins, thus allowing the other two ports to operate in handshake mode.
A 14·bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse
for the CPU system depending on timer mode.
BLOCK DIAGRAM
PIN CONFIGURATION
PC 3
Vee
PC 4
pC 2
TIMER IN
PC,
RESET
PC o
PC s
PB 7
TIMER OUT
PB 6
101M
PBs
101M
256 X 8
ADo 7
STATIC
RAM
PB 4
AD
WR
*
PB 3
ALE
ALE
PB,
ADo
PB o
AD,
PA 7
PB 2
AD2
PA 6
AD3
PAs
AD4
PA 4
ADs
PA 3
AD6
PA 2
AD7
PAl
Vss
PAo
RD
0
PA o- 7
0
PBo--7
WR
TIMER
RESET
TIMER ClK
TIMER OUT
': 8155/8155·2
7·40
= CE, 8156/8156·2 = CE
G
PC O- 5
Lvcc
(+5VI
Vss (OVI
8155/8156/8155-2/8156-2
8155/8156 PIN FUNCTIONS
.§y'mbol
Function
~y'mbol
Function
RESET
(input)
Pulse provided by the 8085A to initialize the system (connect to 8085A
RESET OUT). Input high on this line
resets the chip and initializes the
three I/O ports to input mode. The
width of RESETpulseshouldtypically
be two 8085A clock cycle times.
ALE
(input)
Address Latch Enable: This control
signal latches both the address on the
ADo-7 lines and the state of the Chip
Enable and IO/M into the chip at the
falling edge of ALE.
10/M
(input)
Selects memory if low and I/O and
command/status registers if high.
3-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The 8-bit address is
latched into the address latch inside
the 8155/56 on the falling edge of
ALE. The address can be either for
the memory section or the I/O section
depending on the 10iM input. The
8-bit data is either written into the
chip or read from the chip, depending
on the WR or RD input signal.
PAO-7(8)
(input/output)
These 8 pins are general purpose I/O
pins. The in/out direction is selected
by programming the command
register.
Pl3o-7(8)
(input/output)
These 8 pins are general purpose I/O
pins. The in/out direction is selected
by programming the command
register.
PCo-s(6)
(input/output)
These 6 pins can function as either
input port, output port, or as control
signals for PA and PB. Programming
is done through the command register. When PCo-s are used as control
signals, they will provide the following:
PCo - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PCs - B STB (Port B Strobe)
TIMER IN
(input)
Input to the counter-timer.
TIMER OUT
(output)
Timer output. This output can be
either a square wave or a pulse depending on the timer mode.
Vee
+5 volt supply.
Vss
Ground Reference.
ADO_7
(input/output)
CE or CE
(input)
Chip Enable: On the 8155, this pin is
CE and is ACTIVE LOW. On the 8156,
this pin is CE and is ACTIVE HIGH.
RD
(input)
Read control: Input low on this line
with the Chip Enable active enables
and ADo-7 buffers. If 10iM pin is low,
the RAM content will be read out to
the AD bus. Otherwise the content
of the selected I/O port or command/
status registers will be read to the
AD bus.
WR
(input)
Write control: Input low on this line
with the Chip Enable active causes
the data on the Address/Data bus to
be written to the RAM or I/O ports and
command/status register depending
on 10iM.
7-41
8155/8156/8155-2/8156-2
ABSOLUTE MAXIMUM RATINGS·
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ................ 0°Cto+70°C
Storage Temperature ... . . . . . . . . . . .. -65°C to +150° C
Voltage on Any Pin
With Respect to Ground ............... -0.5V to +7V
Power Dissipation ..... . . . . . . . . . . . . . . . . . . . . . . .. 1.5W
D.C. CHARACTERISTICS
(TA = O°C to 70°C; Vee = 5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Ve e +O· 5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
IlL
I n put Lea kage
±10
iJ.A
= 2mA
= -400J.(A
VIN = Vee to OV
0.45V ~ VOUT ~ Vec
V
2.4
ILO
Output Leakage Current
±10
iJ.A
Ice
Vee Supply Current
180
mA
IldeE)
Chip Enable Leakage
8155
8156
+100
-100
p.A
p.A
7·42
TEST CONDITIONS
IOL
IOH
V,N
= Vee
to OV
8155/8156/8155-2/8156-2
A.C. CHARACTERISTICS
(TA
= o°c to 70°C; VCC = 5V ± 5%)
8155/8156
SYMBOL
PARAMETER
MIN.
MAX.
8155-2/8156-2
(Preliminary)
MIN.
MAX.
UNITS
tAL
Address to Latch Set Up Time
50
30
ns
tlA
Address Hold Time after Latch
80
30
ns
tLC
Latch to R EADIWR IT E Control
100
40
ns
ns
tRO
Valid Data Out Delay from READ Control
170
140
tAo
Address Stable to Data Out Valid
400
330
tll
Latch Enable Width
tROF
Data Bus Float After READ
tel
R EAD/WR ITE Control to Latch Enable
20
10
ns
tee
READ/WR ITE Control Width
250
200
ns
tow
Data In to WR ITE Set Up Time
150
100
ns
two
Data In Hold Time After WR ITE
0
0
ns
tRV
Recovery Time Between Controls
300
twp
WR ITE to Port Output
tpR
Port Input Setup Time
70
50
100
0
100
0
80
200
400
ns
ns
70
ns
ns
300
ns
50
ns
10
ns
tRP
Port Input Hold Time
tSBF
Strobe to Buffer Full
tss
Strobe Width
tRBE
READ to Buffer Empty
400
300
ns
tSI
Strobe to I NTR On
400
300
ns
300
ns
400
200
300
tROI
READ to INTR Off
tpss
Port Setup Time to Strobe Strobe
50
0
ns
tpHS
Port Hold Time After Strobe
120
100
ns
tSBE
Strobe to Buffer Empty
400
300
ns
tWBF
WR ITE to Buffer Full
400
300
ns
tWI
WR ITE to INTR Off
400
300
ns
tTL
TIMER-IN to TIMER-OUT Low
400
300
ns
tTH
TIMER-IN to TIMER-OUT High
300
ns
tROE
Data Bus Enable from READ Control
10
10
t1
TIMER-IN Low Time
80
40
ns
70
ns
t2
400
ns
ns
150
400
TIMER-IN High Time
120
Input Waveform for A.C. Tests:
7-43
ns
8155/8156/8155-2/8156-2
WAVEFORMS
8.
Read Cycle
CE (8155 )
\r-
~(
'\
jf-
~\
/
\
,/
'\
OR
CE (8156 )
101M
..
~
-'I
If-
-J
)t--
ADDRESS
- t Al -
AL E
tAD
J<-
~
r-
~
DATA VALID
~
..,
H
- t LA -
~I\.l" tROE
- tLL -
~~
.(
..
I--
,I{
_ t LC - - tcc -
t RoF ....
t><-
___ tRO_
--
~"-t CL -
- tRV -
b. Write Cycle
CE (8155)
OR
CE (8156)
101M
AD0-7
DATA VALID
ALE
_ t wo -
tRV-
Figure 12. 8155/8156 Read/Write Timing Diagrams
7-44
8155/8156/8155-2/8156-2
8.
Strobed Input Mode
BF
INTR
INPUT DATA
FROMPORT _____________________
~~_________~___~~~--------------------------------------------------------------------
b. Strobed Output Mode
BF
INTR
OUTPUT DATA
TOPORT ________________________________~~~------------------------------------------
Figure 13. Strobed I/O Timing
8155/8156/8155-2/8156-2
a. Basic Input Mode
DATA BUS"
==- =-= -=- -=- =><___________
b. Basic Output Mode
DATA BUS·
OUTPUT
"DATA BUS TIMING IS SHOWN IN FIGURE 7.
Figure 14. Basic I/O Timing Waveform
LOAD COUNTER FROM CLR
I
2
I
1
--l
I
RELOAD COUNTER FROM CLR
I
TIMER IN
TIMER OUT
(PULSE)
TIMER OUT
(SOUARE WAVE)
"
,
,
1)
'- (NOTE
___
J"
(NOTE 1)
'- _ _ _ _ _ _ _ _ J
I
I
NOTE 1: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC
RELOAD MODE (M MODE BIT = 1)
1
Figure 15. Timer Output Waveform Countdown from 5 to 1
7-46
2
I
1
-I
inter
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS-85™
• Multiplexed Address and Data Bus
• Low Standby Power Dissipation
• Directly Compatible with 808SA
and 8088 Microprocessors
• Single +5V Supply
• Low Operating Power Dissipation
• High Density 18-Pin Package
The Intel@ 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using
N-channel Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface directly
to the 8085A and 8088 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085A-2 and the full speed
5 MHz 8088.
PIN CONFIGURATION
ADO
Vee
AD,
RD
AD2
WR
AD3
ALE
AD4
CS
BLOCK DIAGRAM
CS
CE,
CE 2
AD5
CE,
@
AD6
CE 2
WR
ALE
AD7
As
Vss
As
.
R/W
LOGIC
l
-\
r---v
DATA
• BUS
BUFFER
lK x 8
RAM
MEM0RY
ARRAY
x·y DECODE
PIN NAMES
ADO·AD 7
As. As
CS
CE,
CE 2
~E
RD
WR
~~
~
ADDRESSIDATA LINES
ADDRESS LINES
CHIP SELECT
CHIP ENABLE (101M)
CHIP ENABLE
ADDRESS LATCH ENABLE
READ ENABLE
WRITE ENABLE
As. As
ALE
7-47
~
ADDRESS
LATCH
AFN-Q0201 A-D1
8185/8185-2
OPERATIONAL DESCRIPTION
Vss Vee
The 8185 has been designed to provide for direct interface
to the multiplexed bus structure and bus timing of the
8085A microprocessor.
At the beginning of an 8185 memory access cycle, the 8bit address on ADo-7, As and Ag, and the status of CE1 and
CE2 are all latched internally in the 8185 by the falling edge
of ALE. If the latched status of both CE1 and CE2 are
active, the 8185 powers itself up, but no action occurs until
the CS line goes low and the appropriate RD or WR control
signal input is activated.
----
!!!
x2
x,
TRAP
RESET IN
HOLD
RST7,5
RST6,5
8085A
RST5,5
ADDR
f--
SOD
f-
Is,i-i--
SID
INTR
INTA
I-
HLDA
ADDRI
DATA ALE
AD
RESET
So
OUT
WR 101M
RDY ClK
Vee
(8)
Tl
• (8)'"
~
r--
The CS input is not latched by the 8185 in order to allow
the maximum amount of time for address decoding in
selecting the 8185 chip. Maximum power consumption
savings will occur, however, only when CE1 and CE2 are
activated selectively to power down the 8185 when it is not
in use. A possible connection would be to wire the 808SA's
10iM line to the 8185's CE1 input, thereby keeping the
8185 powered down during 1/0 and interrupt cycles.
CE 2
1
CS
X
X
X
0
X
(CS*)[2]
0
0
PORT
8156 B
ALE
...
"
PORT
C
DATAl
ADDR
If
101M
RESET
IN
TIMER
OUT
ALE
Itr-
eE
j..
L--
r--
Power Down and
Function Disable[1]
0
Powered Up and
Function Disable[11
0
1
0
1
Powered Up and
Enabled
...
If
tttt
Vss Vee VDD PROG
WR
AD
GE, 8185
ALE
h--
CS,
!-t--
As, Ag
eE 2
"/
AD o.7
t t
Vss
X
X
Hi-Impedance
0
1
Data from Memory Read
1
1
0
Data to Memory
Write
1
1
1
Hi-Impedance
Reading, but not
Driving Data Bus
Vee
Vee
ADo_7 During Data
WR Portion of Cycle
8185 Function
1
W
~ elK
.II
0
PORT
B
ROY
TABLE 2.
TRUTH TABLE FOR
CONTROL AND DATA BUS PIN STATUS
RD
W
PORT
A
DATAl
ADDR
101M
Notes:
X: Don't Care.
1: Function Disable implies Data Bus in high impedance state
and not writing.
2: CS· = (CEl = 0) • (CE2 = 1) • (CS = 0)
CS· = 1 signifies all chip enables and chip select active
(CS*)
I--
8355/
8755A
V
RESET
1
(6)
r--
As.,o
"-
Power Down and
Function Disable[ll
1
(8)
AD
8185 StatuI
0
W
W
lOW
TABLE 1.
TRUTH TABLE FOR
POWER DOWN AND FUNCTION ENABLE
CE 1
POR~W
WR
_
RD
Vee
~
7 "
No Function
Figure 1. 8185 in an MCS-85 System.
4 Chips:
2K Bytes ROM
1.25K Bytes RAM
38 I/O Lines
1 Counter/Timer
2 Serial I/O Lines
5 Interrupt Inputs
Note:
X: Don't Care.
7-48
AFN-00201 A-Q2
8185/8185-2
ABSOLUTE MAXIMUM RATINGS*
'COMMENT
Temperature Under Bias .............. O°C to +70°C
Storage Temperature .............. -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .............. -0.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
Symbol
(TA
= O°C to 70°C;
Parameter
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
VCC
= 5V ±
5%)
Min.
Max.
Units
Test Conditions
Vil
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vcc+0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
III
Input Leakage
±10
~A
VIN = Vcc to OV
IlO
Output Leakage Current
±10
~A
0.45V 5: VOUT 5: Vcc
Icc
Vcc Supply Current
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100
mA
mA
A.C. CHARACTERISTICS
2.4
IOH = -
35
400~A
(TA = O°C to 70°C; Vcc = 5V ± 5%)
8185
Preliminary
Parameter
Symbol
IOl = 2mA
Min.
[1]
Max.
8185-2
Preliminary
Min.
Max.
Units
tAL
Address to Latch Set Up Time
50
30
ns
tlA
Address Hold Time After Latch
80
30
ns
tLC
Latch to READ/WRITE Control
100
40
tRO
Valid Data Out Delay from READ Control
170
140
ns
tLO
ALE to Data Out Valid
300
200
ns
80
ns
tLl
Latch Enable Width
tROF
Data Bus Float After READ
100
a
ns
ns
70
100
a
tCl
READ/WRITE Control to Latch Enable
20
10
ns
tcc
READ/WRITE Control Width
250
200
ns
tow
Data In to WRITE Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
20
20
ns
tsc
Chip Select Set Up to Control Line
10
10
ns
tcs
Chip Select Hold Time After Control
10
10
ns
tAlCE
Chip Enable Set Up to ALE Falling
30
10
ns
tLACE
Chip Enable Hold Time After ALE
50
30
ns
Notes:
1. All AC parameters are referenced at
a) 2.4V and .45V for inputs
b) 2.0V and .BV for outputs.
Input Waveform for A.C. Tests:
___..JX~::> TESTP'"NTS::::X"'-____
7-49
AFN-00201 A-03
8185/8185-2
ALE
(CE, =0)(C E 2' 1)
WR,RD
ADo-AD7
(READ CYCLE)
(AB, Ag)
--tcc----~I
(WRITE CYCLE)
(DESELECTED)
(SELECTED)
Figure 3.8185 Timing.
7-50
AFN-00201 A-04
inter
8355/8355-2
16,384-8IT ROM WITH 1/0
• Each 1/0 Port Line Individually
Programmable as Input or Output
• 2048 Words x 8 Bits
• Single
+ 5V Power Supply
• Multiplexed Address and Data Bus
• Directly compatible with 808SA
and 8088 Microprocessors
• Internal Address Latch
• 2 General Purpose 8-Bit 1/0 Ports
• 40·Pin DIP
The Intel@ 8355 is a ROM and I/O chip to be used in the 8085A and 8088 microprocessor systems. The ROM portion is organized as 2048 words by 8 bits. It has a maximum acess time of 400 ns to permit use with no wait states in
the 8085A CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines and each I/O port line is
individually programmable as input or output.
The 8355-2 has a 300ns access time for compatibility with the 8085A-2 and full speed 5 MHz 8088 microprocessors.
PIN CONFIGURATION
GE,
Vee
CE 2
PB 7
ClK
PBs
RESET
N.C. (NOT CONNECTED)
PBs
5
PB 4
READY
PB 3
101M
PB 2
PB,
AD
ClK
READY
AD _
o 7
As-,o
PB o
row
PA 7
ALE
PAs
PAs
AD,
BLOCK DIAGRAM
CE2
GE,
101M
ALE
AD2
PA 4
PA 3
lOW
AD3
PA 2
RESET
AD4
PA,
ADs
PAo
ADs
AlO
AD7
Ag
AD
~
~
G
ROM
PA o- 7
PB O- 7
iOR
~Vec
(+5V)
Vss (OV)
Vss
Intel Corporation Assumes No Responsibility tor the Use of Any CirCUitry Other Than Circuitry Embodied In an Intel PrOduct No Other CirCUit Patent licenses are Implied
7-51
8355/8355-2
Symbol
Function
Symbol
Function
ALE
(Input)
When ALE (Address latc~, Enable is
high, ADo-7, 10/M, A8-10, CE, and CE
enter address latched. The signals
(AD, 10/M, A8-10, CE, CE) are latched
in at the trailing edge of ALE.
ClK
(Input)
The
into
has
high
ADo-7
(Input)
Bidirectional Address/Data bus. The
lower 8-bits of the ROM or I/O address
are applied to the bus lines when ALE
is high.
READY
(Output)
Ready is a 3-state output controlled by
CE1, CE2, ALE and ClK. READY is
forced low when the Chip Enables are
active during the time ALE is high, and
remains low until the rising edge of the
next ClK (see Figure 6).
PAO-7
(Input/
Output)
These are general purpose I/O pins.
Their input/output direction is determined by the contents of Data Direction
Register (DDR). Port A is selected for
write operations when the Chip Enables
are active and iOW is low and a 0 was
previously latched from ADo.
During an I/O cycle, Port A or Bare
selected based on the latched value of
ADo. If RD or lOR is low when the latched
chip enables are active, the output
buffers present data on the bus.
A8-10
(Input)
These are the high order bits of the ROM
address. They do not affect I/O operations.
CE1
CE2
(Input)
Chip Enable Inputs: CE1 is active low
and CE2 is active.b.!.9!l. The 8355 can be
accessed only when BOTH Chip Enables are active at the time the ALE
signal latches them up. If either Chip
Enable input is not active, the ADo-7
and READY outputs will be in a high
impedance state.
10iM
(Input)
If the latched 10/M is high when RD is
low, the output data comes from an
I/O port. If it is low the output data
comes from the ROM.
RD
(Input)
If the latched Chip Enables are active
when RD goes low, the ADo-7 output
buffers are enabled and output either
the selected ROM location or I/O port.
When both RD and lOR are high, the
ADo-7 output buffers are 3-state.
lOW
(Input)
ClK is used to force the READY
its high impedance state after it
been forced low by CE low, CE
and ALE high.
Read operation is selected by either
lOR low and active Chip Enables and
ADo low, Q! 10/M high, RD low, active
chip enables, and ADo low.
If the latched Chip Enables are active,
a Iowan lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on ADo-7.
The state of 10/M is ignored.
7-52
PBo-7
(Input/
Output)
This general purpose I/O port is
identical to Port A except that it is
selected by a 1 latched from ADo.
RESET
(Input)
An input high on RESET causes all pins
in Port A and B to assume input mode.
lOR
(Input)
When the Chip Enables are active, a low
on lOR will output the selected I/O port
onto the AD bus. lOR low performs the
same function as the combination 10/M
high and RD low. When lOR is not used
in a system, lOR should be tied to Vee
("1" ).
Vee
+5 volt supply.
Vss
Ground Reference.
8355/8355-2
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating onlv and functional opera·
tion of the device at these or any other conditions above
Temperature Under Bias ................ aoc to +70°C
Storage Temperature ............... -65 0 C to +150° C
Voltage on Any Pin
With Respect to Ground ............... -0.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
SYMBOL
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliability.
(TA = o°c to 70°C; Vee = 5V ± 5%)
MIN.
PARAMETER
MAX.
UNITS
V
Input Low Voltage
-0.5
0.8
VIH
Input High Voltage
2.0
Vee +0.5
VOL
Output Low Voltage
0.45
VO H
Output High Voltage
VIL
TEST CONDITIONS
Vee
= 5.0V
V
Vee
= 5.0V
V
IOL
= 2mA
IOH = -400J.LA
V
2.4
= Vee to OV
IlL
Input leakage
10
J.LA
VIN
ILO
Output leakage Current
±10
J.LA
0.45V ~VOUT ~Vee
lee
Vee Supply Current
180
mA
A.C. CHARACTERISTICS
(TA = o°c to 70°C; Vee = 5V
± 5%)
8355-2
8355
Symbol
Parameter
Min.
tCYC
Clock Cycle Time
320
T1
ClK Pulse Width
80
T2
ClK Pulse Width
120
tf. tr
ClK Rise and Fall Time
tAL
Address to latch Set Up Time
Max.
Min.
Max.
200
40
70
30
ns
ns
ns
30
50
30
Units
ns
ns
tLA
Address Hold Time after latch
80
30
ns
tLC
latch to READ/WRITE Control
100
40
ns
tRO
Valid Data Out Delay from READ Control
170
140
ns
tAD
Address Stable to Data Out Valid
400
330
ns
tll
latch Enable Width
tROF
Data Bus Float after READ
85
ns
tCl
READ/WRITE Control to latch Enable
20
10
ns
tce
READ/WRITE Control Width
250
200
ns
tow
Data In to Write Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
10
10
twp
WRITE to Port Output
tpR
Port Input Set Up Time
50
50
tRP
Port Input Hold Time
50
50
tRYH
READY HOLD Time
0
tARY
ADDRESS (CE) to READY
tRY
Recovery Time Between Controls
300
200
ns
READ Control to Data Bus Enable
10
10
ns
tRoE
Note:
CLOAD =
150pF
Input Waveform for A.C. Tests:
100
0
ns
70
100
0
400
160
ns
400
0
160
ns
ns
ns
160
ns
160
ns
8355/8355-2
Figure 3. Clock Specification for 8355
A8-10
101M
1 4 - - - - - - - - tAo - - - - - - - - - . . I
ADo_7
DATA
ALE
1 + - - - - - tow - - - - - - - + I
Figure 4. ROM Read and 1/0 Read and Write
7-54
8355/8355-2
8.
Input Mode
d::,~
PORT
INPUT
==x
DATA*- BUS
-- -
-
-)(
-------
----------------------
b. Output Mode
GLITCH FREE
/OUTPUT
PORT
OUTPUT
DATA* - BUS
____ _
~
J\ _______..JX\._____
*DATA BUS TIMING IS SHOWN IN FIGURE 4.
Figure 5. 1/0 Port Timing
Figure 6. Wait State Timing (Ready = 0)
7-55
intel~
8755A /8755A·2
16,384·8IT EPROM WITH I/O
• 2048 Words )( 8 Bits
• 2 General Purpose 8·Bit 1/0 Ports
• Single + 5V Power Supply (V cd
• Each 1/0 Port Line Individually
Programmable as Input or Output
• Directly Compatible with 808SA
and 8088 Microprocessors
• Multiplexed Address and Data Bus
• U.V. Erasable and Electrically
Reprogrammable
• 40·Pin DIP
• Internal Address Latch
The Intel@ 8755A is an erasable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the 8085A
and 8088 microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum
access time of 450 ns to permit use with no wait states in an 8085A CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and each I/O port line is
individually programmable as input or output.
The 8755A-2 is a high speed selected version of the 8755A compatible with the 5 MHz 8085A-2 and the full speed 5
MHz 8088.
PROG AND CE,
CE 2
CLK-----,
CLK
RESET
READY-----t
CE2 - - - - I
IO/M----~
2K x 8
EPROM
VDD
PB 4
READY
PB 3
101M
lOR
PB 2
PB,
RD
PB o
lOW
ALE
ALE---_I
ADo
PA 5
Fill----I
AD,
PA 4
IOW----I
AD2
PA 3
RESET-----t
AD3
PA 2
iOR---_I
AD4
PA,
ADs
PA o
~VCC(+5VI
Vss (OVI
AD6
A,O
AD7
A9
Vss
Figure 1. Block Diagram
Figure 2. Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses 8Je Implied.
"INTEL CORPORATION. 1980
7-56
AFN-01841B
8755A/8755A-2
Table 1. Pin Description
Symbol
Type
Name and Function
Symbol
Typl;
ALE
I
Address Latch Enable: When Address
latch Enable goes high, ADO-7. 10/M,
Aa-10. CE2. and CE 1 enter the address
latches. The signals (AD, 10/M, AS-10.
CE) are latched in at the trailing edge of
ALE.
READY
0
Ready is a 3-state output controlled by
CE2, CE1 , ALE and elK. READY is forced
low when the Chip Enables are act ave
during the time ALE is high, and remains
low until the rising edge of the next ClK.
(See Figure 6.)
ADO-7
I
Bidirectional Address/Data Bus: The
lower 8-bits of the PROM or I/O address
are applied to the bus lines when ALE is
high.
PAO-7
110
Port A: These are general purpose 1/0
pins. Their input/output direction is determined by the contents of Data Direction Register (DDR). Port A is selected for
write operations when the Chip Enables
are active and lOW is low and a 0 was
previously latched from ADo, AD 1.
During an I/O cycle, Port A or Bare
selected based on the latched value of
ADo. IF RD or lOR is low when the latched
Chip Enables are active, the output buffers present data on the bus.
Aa-10
I
Address: These are the high order bits
of the PROM address. They do not affect
I/O operations.
PROG/CE1
CE2
I
Chip Enable Inputs: CE 1 is active low
and CE2 is active high. The 8755A can be
accessed only when both Chip Enables
are active at the time the ALE signal
latches them up. If either C; ;:p Enable
input is not active, the ADo ·1 and
READY outp~ will be in a
'T1pedance state.CE 1 is also used as a programming pin. (See section on
programming.)
10/M
I
I/O Memory: If the latched 10/M is high
when RD is low, the output data comes
from an I/O port. If it is low the output
data comes from the PROM.
RD
I
Read: If the latched Chip Enables are
active when RD goes low, the ADO-7
output buffers are enabled and output
either the selected PROM location or I/O
port. When both RD and lOR are high,
the ADo-7 output buffers are 3-stated.
lOW
I
I/O Write: If the latched Chip Enables are
active, a Iowan lOW causes the output
port pointed to by the latched value of
ADo to bewritte~with the data on AD o-7.
The state of 10/M is ignored.
ClK
I
Clock: The ClK is used to force the
READY into its high impedance state
after it has been forced low by CE1 low,
CE2 high, and ALE high.
Name and Function
Read Operation is selected by either lOR
low and active Chip Enables and ADo
and AD1 low,or 101M high, RD low, active
Chip Enables, and ADo and AD1 low.
PBO-7
I/O
Port B: This general purpose I/O port is
identical to Port A except that it is
selected by a 1 latched from ADo and a 0
from AD 1.
RESET
I
Reset: In normal operation, an input
high on RESET causes all pins in Ports A
and B to assume input mode (clear DDR
register).
lOR
I
I/O Read: When the Chip Enables are
active, a Iowan lOR will output the
selected I/O port onto the AD bus. lOR
low performs the s~me functio~s the
combination of IO/M high and RD low.
When lOR is not used in a system, lOR
should be tied to Vee ("1").
Vee
Power: +5 volt supply.
Vss
Ground:
Voo
Power Supply: Voo is a programming
voltage, and must be tied to Vee when
the 8755A is being read.
Reference.
For programming, a high voltage is
supplied with Voo = 25V, typical. (See
section on programming.)
7-57
AFN-01B41B
intel
8755A/8755A-2
87,5A
ONE BIT OF PORT A AND ODR A
FUNCTIONAL DESCRIPTION
PROM Section
The 8755A contains an 8-bit address latch which allows it
to interface directly to MCS-48, MCS-85 and iAPX 88/10
Microcomputers without additional hardware.
The PROM section of the chip is addressed by the 11-bit
address and CEo The address, CE 1 and CE2 are latched
into the address latches on the falling edge of ALE. If the
latched Chip Enables are active and 10iM is low when RD
goes low, the contents of the PROM location addressed
by the latched address are put out on the ADO-7 lines
(provided that Voo is tied to Vee.)
WRITE DDR A
DO
1/0 Section
The I/O section of the chip is addressed by the latched
value of ADo-1. Two 8-bit Data Direction Registers DDR
in 8755A determine the input/output status of each pin
in the corresponding ports. A "0" in a particular bit position of a DDR signifies that the corresponding I/O port bit
is in the input mode. A "1" in a particular bit position signifies that the corresponding I/O port bit is in the output
mode. In this manner the I/O ports of the 8755A are bit-bybit programmable as inputs or outputs. The table
summarizes port and DDR designation. DDR's cannot be
read.
AD1
ADo
0
0
1
1
0
1
0
1
Selection
Port
Port
Port
Port
A
B
A Data Direction Register mDR Al
B Data Direction Register (DDR B)
When lOW goes low and the Chip Enables are active, the
data on the AD is written into I/O port selected by the
latched value of ADo-1. During this operation all I/O bits
of the selected port are affected, regardless of their I/O
mode and the state of 10/M'. The actual output level does
not change until lOW returns high. ,glitch free output,
~
~
READ PA
WRITE PA' liOW'O)oICHIP ENABLES ACTIVElolPORT A ADDRESS SELECTEOI
WRITE ODR A' liOW'OloiCHIP ENABLES ACTIVElolDDR A ADDRESS SELECTEDI
READ PA i [110 IMo,) 0 lAD 'Olj • liOR '01; 0 ICH IP ENA BL ES ACTIVE I 0 (PORT A AD DR ESS SE LE CTE 0,
NOTE: WRITE PA IS NOT QUAlIFIEO BY 101M
Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch's output buffer to be
disabled, preventing the data In the Output Latch from
being passed through to the pin. This is equivalent to
putting the port in the input mode. Note also that the data
can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be initialized with a value prior to enabling the output.
The diagram also shows that the contents of PORT A and
PORT B can be read even when the ports are configured
as outputs.
TABLE 1. 8755A PROGRAMMING MODULE CROSS
REFERENCE
A port can be read out when the latched Chip Enables are
active and either RD goes low with 10/M high, or lOR goes
low. Both input and output mode bits of a selected port
wiil appear on lines ADo-7.
MODULE NAME
USE WITH
UPP 955
UPP UP2«2)
PROMPT 975
PROMPT 475
UPP(4)
UPP 855
PROMPT 80/85(31
PROMPT 48l 1/
NOTES:
1. Described on p.13-340f 1978 Data Catalog.
2. Special adaptor socket.
3. Described on p. 13-39 of 1978 Data Catalog.
4. Described on p. 13-71 of 1978 Data Catalog.
To clarify the function of the I/O Ports and Data Directior
Registers, the following diagram shows the configuration
of one bit of PORT A and DDR A. The same logic applies
to PORT Band DDR B.
7-58
AFN-01B41B
8755A/8755A-2
ERASURE CHARACTERISTICS
The erasure characteristics of the 8755A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
IAI. It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 8755A in
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight.
If the 8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels
are available from Intel which should be placed over the
8755 window to prevent unintentional erasure.
The recommended erasure procedure for the 8755A is
exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (AI. The integrated dose Ii.e.,
UV intensity X exposure time I for erasure should be a
minimum of 15W-sec/cm2. The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000pW/cm2 power rating. The
8755A should be placed within one inch from the lamp
tubes during erasure. Some lamps have a filter on their
tubes and this filter should be removed before erasure.
SYSTEM APPLICATIONS
System Interface with 808SA and 8088
A system using the 8755A can use either one of the two I/O
Interface techniques:
• Standard I/O
• Memory Mapped I/O
If a standard I/O technique is used, the system can use
the feature of both CE3 and CE 1. By using a combination
of unused address lines A II - 15 and the Chip Enable
inputs, the 8085A system can use up to 5 each 8755A's
without requiring a CE decoder. See Figure 2a and 2b.
If a memory mapped I/O approach is used the 8755A will be
by the combination of both the Chip Enables and
10/M using the ADs-15 address lines. See Figure 1.
sel~ted
/1
PROGRAMMING
)
K;8.15
Initially, and after each erasure, all bits of the EPROM
portions of the 8755A are in the "1" state. Information is
introduced by selectively programming "0" into the
desired bit locations. A programmed "0" can only be
changed to a "1" by UV erasure.
8085A
~D07
"V
'J
ALE
RD
WR
The 8755A can be programmed on the Intel® Universal
PROM Programmer (UPp i, and the PROMPr M 80/85 and
PROMPT-48™ design aids. The appropriate programming
modules and adapters for use in programming both
8755A's and 8755's are shown in Table 1.
elK 10.,21
READY
101M
vee
-
t
f---
r"'7 "(/
The program mode itself consists of programming a
single address at a time, giving a single 50 msec pulse
for every address. Generally, it is desirable to have a
verify cycle after a program cycle for the same address
as shown in the attached timing diagram. In the verify
cycle (i.e., normal memory read cycle I 'Voo' should
be at +5V.
A/Do_7
iDA
A_
s 10
I
RD elK
101M
ALE iOW READY CE
8755A
Preliminary timing diagrams and parameter values pertaining to the 8755A programming operation are contained in Figure 7.
Figure 3. 8755A in 80S5A System
(Memory-Mapped I/O)
7-59
8755A/8755A·2
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ................ O°Cto+70°C
Storage Temperature ............... -65°C to "150°C
Voltage on Any Pin
With Respect to Ground ............... -O.5V to +7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA
= O°C to 70°, Vee = Voo = 5V ± 5%;
Vee = VOO = 5V ±10% for 8755A-2)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0 . 5
V
Vee = 5.0V
VOL
Output Low Voltage
0.45
V
IOL
VOH
Output High Voltage
V
IOH
IlL
Input Leakage
ILO
lee
2.4
TEST CONDITIONS
Vee = 5.0V
= 2mA
= -400j1A
10
j1A
VSS ~ VIN ~ Vee
Output Leakage Current
±10
j1A
VSS"'; 0.45V ,.,; VOUT ,.,; Vee
Vee Supply Current
180
mA
Voo Supply Current
= Vee
= 1JLHz
fe = 1JLHz
30
mA
Voo
CIN
Capacitance of Input Buffer
10
pF
fe
CI/o
Capacitance of I/O Buffer
15
pF
100
D.C. CHARACTERISTICS- PROGRAMMING
Symbol
(TA = 0°Ct070°, Vee = 5V ± 5%, Vss = OV, Voo
Vee = Voo = 5V ±10% for 8755A-2)
Parameter
Voo
Programming Voltage (during Write
to EPROM)
IDO
Prog Supply Current
7·60
= 25V ±1V;
Min.
Typ.
24
25
26
V
15
30
mA
Max.
Unit
AFN-01841B
intel"
8755A18755A·2
A.C. CHARACTERISTICS
(TA = O°C to 70°, Vee = 5V ± 5%;
Vee = Voo = 5V ±10% for 8755A-2)
8755A·2
(Preliminary)
8755A
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
tCYC
Clock Cycle Time
320
200
T1
ClK Pulse Width
80
40
ns
T2
ClK Pulse Width
120
70
ns
ns
tt,t r
ClK Rise and Fall Time
tAL
Address to latch Set Up Time
50
30
ns
tlA
Address Hold Time after latch
80
45
ns
tlC
latch to READ/WRITE Control
100
40
tRO
Valid Data Out Delay from READ Control
170'
140'
ns
tAD
Address Stable to Data Out Valid
450
330
ns
85
ns
30
tll
latch Enable Width
tROF
Data Bus Float after READ
0
tCl
READ/WRITE Control to latch Enable
20
tcc
READ/WRITE Control Width
tDW
ns
30
100
ns
70
100
0
ns
10
ns
250
200
ns
Data In to Write Set Up Time
150
150
ns
two
Data In Hold Time After WRITE
30
10
twp
WRITE to Port Output
tPR
Port Input Set Up Time
50
tRP
Port Input Hold Time to Control
50
tRYH
READY HOLD Time to Control
0
tARY
ADDRESS (CEl to READY
tRv
Recovery Time Between Controls
300
200
ns
tRDE
READ Control to Data Bus Enable
10
10
ns
tLO
ALE to Data Out Valid
I
400
ns
ns
300
50
ns
50
160
0
160
ns
160
ns
160
ns
--
270
350
ns
NOTE:
eLOAD =
'Or
TAD -
150pF.
(TAL + he), whichever is greater.
A.C. CHARACTERISTICS-PROGRAMMING
Symbol
(TA =0°Cto70°, Vee = 5V± 5%, Vss= OV,Voo = 25V±1V;
Vee = Voo = 5V ±10% for 8755A-2)
Parameter
Min.
Typ.
Max.
Unit
tps
Data Setup Time
10
tPD
Data Hold Time
0
ns
ts
Prog Pulse Setup Time
2
}J.s
ns
tH
Prog Pulse Hold Time
2
tPR
Prog Pulse Rise Time
0.01
tPF
Prog Pulse Fall Time
0.01
2
}J.s
tPRG
Prog Pulse Width
45
50
msec
7-61
}J.s
2
}J.s
AFN-01841B
in1:el"
8755A/8755A·2
A.C. TESTING INPUT, OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
!NPUT/OUTPUT
,. ~"'O-----<
DATA
l-
ADDRESS
I-tLL--
ALE
,I
'kf.-tAL-
(PROGI/CE,
\k-
CE 2
)~
I------ t LA - - -
\
~\
--
-
I---tROE
k!----tLc _ _
~tR[)
....
L
I----- t-two
tow
-'~k-
lOW
1---
)~
-'1\
iORFili
tROF
,~
L
tcc
I----tCL-
Please note that
GEl
.
must remain low for the entire cycle.
7·62
tRV
AFN-Ol841B
8755A/8755A·2
WAVEFORMS (Continued)
1/0 PORT
A. INPUT MODE
ROOR
iiYR
B. OUTPUT MODE
lOW
GLITCH FREE
~ ~/ OUTPUT
6~~;UT =========~ ~ ~ Xl;..;;.-______
~~~A· -_____
-
-V
-A_______
X
--J.
It..._ _ _ __
WAIT STATE (READY = 0)
CLK
ICE=1) • ICE=O)
ALE
-l"'"
I
READY- -
-
4-
, ...... _-----.
I
tAAY'"
7·63
AFN-01B41B
8755A18755A·2
WAVEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION
I. . .~------
ALEJ
PROGRAM CYCLE
-------~
.. 11·.....- - - - - VERIFY CYCLE'
--1_
PROGRAM CYCLE
\_--_1\_DATA TO BE
PROGRAMMED
A/DO-7
tPD--
AS-l0
tH _ _
+25
VDD
-
+5--------------·------------~
'VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH VDD = +5V FOR 8755A)
7-64
AFN-01841B
8041 AJ8641AJ8741 A
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOMPUTER
CPU plus ROM, RAM, I/O, Timer
• 8·Bit
and Clock in a Single Package
One 8·Bit Status and Two Data Regis·
• ters
for Asynchronous Slave·to·Master
Interface
DMA, Interrupt, or Polled Operation
• Supported
1024 x 8 ROM/EPROM, 64 x 8 RAM,
• 8·Bit
Timer/Counter, 18 Programmable
I/O Pins
Compatible with MCS·48™,
• Fully
MCS·80™, MCS·85™, and MCS·86™
Microprocessor Families
Interchangeable ROM and EPROM
• Versions
• 3.6 MHz 8741A·8 Available
• Expandable I/O
• RAM Power·Down Capability
• Over 90 Instructions: 700/0 Single Byte
• Single 5V Supply
The Intel@ 8041A/8741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, 1/0
ports, timerlcounter, and clock in a single 40-pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48™, MCS-80™, MCS-85™, MCS-86™, and other 8-bit systems.
The UPI-41A™ has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM in the 8041A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041A are fully pin compatible for easy transition from prototype to production level designs. The 8641A is a
one-time programmable (at the factory) 8741A which can be ordered as the first 25 pieces of a new 8041A order. The
substitution of 8641A's for 8041A's allows for very fast turnaround for initial code verification and evaluation results.
The device has two 8-bit, TTL compatible 1/0 ports and two test inputs. Individual port lines can function as either inputs or outputs under software control. 1/0 can be expanded with the 8243 device which is directly compatible and has
16 1/0 lines. An 8-bit programmable timerlcounter is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041 A),
single-step mode for debug (in the 8741A), and dual working register banks.
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI interface devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include keyboard scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.
PIN CONFIGURATION
TEST 0
XTALl
XTAL2
P281DRQ
BLOCK DIAGRAM
r
...
~. .,. .- - - M-~-:-b~-R-:~l;:' , ~;::
,
P2s1iiiF
P2410BF
L..............,..,~~~
RANDOM
ACCESS
MEMORY
PERIPHERAL
INTERFACE
I-BIT
I'y------,/IEVEN~I~~~NTER
00188A
8041 AJ8641AJ8741 A
PIN DESCRIPTION
Signal
Description
Do- D7
(BUS)
Three-state, bidirectional DATA BUS BUFFER lines
used to interface the UPI-41A to an 8-bit master
system data bus.
UPI ™ INSTRUCTION SET
D••crlptlon
Mn.monlc
8-bit, PORT 2 quasi-bidirectional 110 lines. The lower
4 bits (P 20 -P 23) interface directly to the 8243 I/O expander device and contain address and data information during PORT 4-7 access. The upper 4 bits
(P 24 -P27) can be programmed to provide Interrupt
Request and DMA Handshake capability. Software
control can configure P24 as OBF (Output Buffer
Full), P25 as IBF (Input Buffer Full), P26 as DRO
(DMA Request), and P 27 as DACK (DMA
ACKnowledge).
I/O write input which enables the master CPU to
write data and command words to the UPI-41A INPUT DATA BUS BUFFER.
I/O read input which enables the master CPU to
read data and status words from the OUTPUT DATA
BUS BUFFER or status register.
Chip select input used to select one UPI-41A out of
several connected to a common data bus.
TEST 0,
TEST 1
IN A.Pp
OUTL Pp.A
ANL Pp.#data
ORL Pp.#data
IN A.DBB
OUT DBB.A
MOV STS,A
MOVD A.Pp
MOVD Pp.A
ANLD Pp.A
ORlD Pp.A
Input pins which can be directly tested using conditional branch instructions.
T1 also functions as the event timer input (under
software control). To is used during PROM programming and verification in the 8741A.
Inputs for a crystal, LC or an external timing signal
to determine the internal oscillator frequency.
SYNC
Output Signal which occurs once per UPI-41A instruction cycle. SYNC can be used as a strobe for
external circuitry; it is also used to synchronize
single step operation.
EA
External access input which allows emulation,
testing and PROM/ROM verification.
PROG
Multifunction pin used as the program pulse input
during PROM programming.
MOV A.Rr
MOV A.@Rr
MOV A.#data
MOV Rr.A
MOV @Rr.A
MOV Rr.#data
MOV @Rr.#data
MOV A.PSW
MOV PSW.A
XCH A.Ar
XCH A.@Rr
XCHD A.@Rr
MOVP A.@A
MOVP3. A.@A
Input used to reset status flip-flops and to set the
program counter to zero.
RESET is also used during PROM programming and
verification.
SS
Single step input used in the 8741A in conjunction
with the SYNC output to step the program through
each instruction.
Vee
+ 5V main power supply pin.
Voo
+ 5V during normal operation. + 25V during programming operation. Low power standby pin in
ROM version.
Vss
Circuit ground potential.
2
2
1
1
2
1
1
1
1
2
2
1
2
1
1
2
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
Input port to A
Output A to port
AND immediate to port
OR immediate to port
Input DBB to A. clear IBF
Output A to DBB. set OBF
A4-A7 to Bits 4-7 of Status
Input Expander port to A
Output A to Expander port
AND A to Expander port
OR A to Expander port
1
1
1
2
2
2
2
OATA MOVES
During I/O expander access the PROG pin acts as
an address/data strobe to the 8243.
RESET
1
1
1
1
2
1
1
1
1
INPUT /OUTPUT
Address input used by the master processor to indicate whether byte transfer is data or command.
XTAL 1,
XTAL2
Add register to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add data memory to A with carry
Add immed. to A with carry
AND register to A
AND data memory to A
AND immediate to A
OA register to A
OA data memory to A
OA immediate to A
Exclusive OR register to A
Exclusive OR data memory to A
Exclusive OR immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
ADD A.Rr
ADD A.@Rr
ADD A.#data
ADDC A.Ar
ADDC A.@Ar
ADDC A.#data
ANL A.Ar
ANL A.@Rr
ANL A.#data
ORL A.Rr
ORL A.@Rr
OAL A.#data
XRL A.Rr
XRL A.@Ar
XRL A.#data
INC A
DEC A
CLR A
CPL A
DA A
SWAP A
RL A
RLC A
RR A
RRC A
8-bit, PORT 1 quasi-bidirectional I/O lines.
Ao
Byt•• Cycl••
ACCUMULATOR
Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to register
Move immediate to data memory
Move PSW to A
Move A to PSW
Exchange A and register
Exchange A and data memory
Exchange digit of A and register
Move to A from current page
Move to A from page 3
1
1
1
1
2
2
1
1
1
1
2
2
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
TIMER/COUNTER
MOV AJ
MOV T,A
STAT T
STRT CNT
STOP TCNT
EN TCNTI
DIS TCNTI
7-66
Read Timer /Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer ICounter Interrupt
Disable Timer/Counter Interrupt
00 188A
8041 AJ8641 AJ8741 A
Mnemonic
De.crlptlon
Byte.
Mnemonic
Cycle.
CONTROL
EN DMA
EN I
DIS I
EN FLAGS
SEL RBO
SEL RB1
NOP
Enable DMA Handshake Lines
Enable IBF Interrupt
Disable IBF Interrupt
Enable Master Interrupts
Select register bank 0
Select register bank 1
No Operation
REGISTERS
INC Rr
INC@Rr
DEC Rr
Increment register
Increment data memory
Decrement register
SUBROUTINE
CALL addr
RET
RETR
Jump to subroutine
Return
Return and restore status
FLAGS
CLR C
CPLC
CLR FO
Clear Carry
Complement Carry
Clear Flag 0
Byte.
De.crlptlon
CPL FO
CLR F1
CPL F1
Complement Flag 0
Clear F1 Flag
Complement F1 Flag
BRANCH
JMP addr
JMPP @A
DJNZ Rr, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JT1 addr
JNT1 addr
JFO addr
JF1 addr
JTF addr
JNIBF addr
JOBF addr
JBb addr
Jump unconditional
Jump indirect
Decrement register and jump
Jump on Carry = 1
Jump on Carry = 0
Jump on A Zero
Jump on A not Zero
Jump on TO= 1
Jump on TO=O
Jump on T1 = 1
Jump on T1 =0
Jump on FO Flag = 1
Jump on F1 Flag = 1
Jump on Timer Flag = 1, Clear Flag
Jump on IBF Flag = 0
Jump on OBF Flag = 1
Jump on Accumulator Bit
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Cycl••
2
2
2
APPLICATIONS
DATA
W
808SA
ADDR
--TO
CONTROL
TO
PERIPHERAL
DEVICES
8048
AD
AD
WR
WR 8041A1
CS 8741A
W
W
AO
-TO
DBS
-T1
PORT
CONTROL
2
DATA BUS
8
TO
PERIPHERAL
DEVICES
A
--T1
BUS
~
Figure 2. S04S-S041A Interface
Figure 1. SOSSA-S041A Interface
KEYBOARD
MATRIX
8243
EXPANDER
z
0
i=
iii
0
z
0
~
a:
0
u..
11.
I-
u..
0
~
0
Z
11.
11.
I-
i=
iii
0
11.
0
UJ
UJ
u..
IU
Z
::.
PORT2
8041A/8741A
8041 Al8741 A
DATA SUS
CONTROL BUS
Figure 3. S041A-S243 Keyboad Scanner
Figure 4. S041A Matrix Printer Interface
7_~7
00 188A
8041 AJ8641AJ8741 A
·COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias. __ .... _.O·C to 70·C
Storage Temperature _. _. _.... _. _. - 65 c C to + 150 c C
Voltage on Any Pin With Respect
to Ground .......................... 0.5V to + 7V
Power Dissipation __ .......... _.. _......... 1.5 Watt
D.C. AND OPERATING CHARACTERISTICS
TA= O°C to 70·C, Vss= OV, 8041A: Vcc= Voo= +5V ± 10%, 8741A: Vce= Voo= +5V ± 5%
Test Conditions
Parameter
Min.
Max.
Unit
V il
Input Low Voltage (Except XTAL 1, XTAL2, RESET)
-0.5
0.8
V
V IL1
Input Low Voltage (XTAL1, XTAL2, RESET)
- 0.5
0.6
V
V IH
Input High Voltage (Except XTAL 1, XTAL2, RESET)
2.2
Vee
V IH1
Input High Voltage (XTAL 1, XTAL2, RESET)
3.8
VOL
VOL1
Output Low Voltage (0 0-0 7)
Vee
0.45
V
IOl= 2.0 rnA
0.45
V
IOl = 1.6 rnA
0.45
V
IOl = 1.0 rnA
2.4
V
IOH= - 400 p.A
2.4
V
Symbol
VOl2
Output Low Voltage (P1OP17, P20 P27 , Sync)
Output Low Voltage (Prog)
VOH1
Output High Voltage (0 0-0 7)
Output High Voltage (All Other Outputs)
III
Input Leakage Current (To, T 1, RD, WR, CS, A o, EA)
±10
loz
Output Leakage Current (0 0-0 7, High Z State)
III
ILl1
Low Input Load Current (P 1O P17 , P20 P27 )
Low Input Load Current (RESET, SS)
100
Voo Supply Current
Icc + 100
Total Supply Current
VOH
V
'OH= -50 p.A
p.A
Vss ::5 VIN ::5 Vee
±10
p.A
0.5
rnA
Vss+0.45::5 VIN ::5 Vee
V ll = 0.8V
0.2
rnA
15
rnA
V ll = 0.8V
Typical = 5 rnA
125
rnA
Typical = 60 rnA
A.C. CHARACTERISTICS
T A = O°C to 70·C, Vss= OV, 8041A: Vee= Voo=
+ 5V
± 10%, 8741A: Vee= Voo= + 5V ± 5%
DBB READ
Symbol
Min.
Parameter
Max.
Unit
0
ns
0
ns
Test Conditions
tAR
CS, Ao Setup to RDI
tRA
CS, Ao Hold After RDI
tRR
RD Pulse Width
tAD
t Ro
CS, Ao to Data Out Delay
225
ns
C l = 150 pF
RDI to Data Out Delay
225
ns
C l = 150 pF
tOF
Fml to Data Float Delay
100
ns
tey
Cycle Time (Except 8741A-8)
2.5
15
P.s
6.0 MHz XTAL
tey
Cycle Time (8741A-8)
4.17
15
P.s
3.6 MHz XTAL
Min.
Max.
Unit
ns
250
DBB WRITE
Parameter
Symbol
0
ns
0
ns
250
ns
tAW
CS, Ao Setup to WRI
tWA
CS, Ao Hold After WRf
tww
WR Pulse Width
tow
Data Setup to WRf
150
ns
two
Data Hold After WRf
0
ns
7-nR
Test Conditions
00188A
8041 AJ8641AJ8741 A
INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS
2.4 ----""')(2.2.........
_ _____
0.45
.-2.2V
sA' - - - - - -
O.S ......... TEST POINTS ......... •
O
CL =150 pF
WAVEFORMS
1. READ OPERATION-DATA BUS BUFFER REGISTER.
(SYSTEM'S
ADDRESS BUSI
~OR Ao
+-'AR----I
--+----1'
1---
---'RR------~_ _ _~
(READ CONTROLI
1
__ 'AD~___-~D=I
.-- l
'OF
~oA~T~~~~----------«I--- om "uod»--------2. WRITE OPERATION-DATA BUS BUFFER REGISTER.
~ OR
Ao
r
~
--fT--------------------'I
i-'AW-i
~__________
---'WW---~I.-~'WA~
1--
{~
._ _
~
'{
~-'ow---
(SYSTEM'S
ADDRESS BUSI
(WRITE CONTROL I
------ 'wo
'J -----DATAVALlD---X~____M_A_YDATA
--JI'I
_CH_A_NG_E_ _ __
DATA BUS
DATA
(I NPUTI _ _ _ _M_A_Y_CH_A_NG_E_ _
TYPICAL 8041/8741A CURRENT
80 rnA
60 rnA
40 rnA
20 rnA
40·
20·
60·
80·
TEMP (·C)
7-69
00l88A
8041 A/8641 Al8741 A
A.C. CHARACTERISTICS-PORT 2
T A= O'C to 70'C, 8041 A: Vcc=
+ 5V
± 10%, 8741A: Vcc =
+ 5V
P..arameter
Symbol
± 5%.
Port Control Setup Before Falling
Edge of PROG
110
tpc
Port Control Hold After Falling
Edge of PROG
100
tpR
PROG to Time P2 Input Must Be Valid
tpF
Input Data Hold Time
tDP
Output Data Setup Time
tPD
Output Data Hold Time
tpp
PROG Pulse Width
Max.
··Mln.
tcp
Unit
Test Conditions
ns
ns
0
810
ns
150
ns
250
ns
65
ns
1200
ns
PORT 2 TIMING
SYNC
EXPANDER
PORT
OUTPUT
PORT 20-3 DATA
EXPANDER
PORT
INPUT
peRT 20-3 DATA
PROG
A.C. CHARACTERISTICS-DMA
Symbol
Min.
Parameter
Max.
Unit
Test Conditions
ns
t ACC
DACK to WR orRD
0
t CAC
RD or WR to DACK
0
t ACD
DACK to Data Valid
225
ns
tCRQ
RD or WR to DRO Cleared
200
ns
ns
C L = 150 pF
WAVEFORMS-DMA
DATA BUS
DRQ
----t-+-____. ,-----,. ,..--------t-""""'
r--"",
r------
-----t---"I
7.7fl
DD188A
8041 AJ8641AJ8741 A
DRIVING FROM EXTERNAL SOURCE
CRYSTAL OSCILLATOR MODE
+5V
r-----
XTAL1
I
I
< 15 pF
(INCLUDES XTAL,
SOC:(ET, STRAY)
470Q
I
...,
....L
J>---+------i XTAL 1
I
I
L ____ _
+5V
I
15 - 25 pF
(INCLUDES SOCKET,
STRAY)
470Q
I-=-
' - - - - + - - - i XTAL2
CRYSTAL SERIES RESISTANCE SHOULD BE <75Q AT 6 MHz; <180Q AT 3.6 MHz.
BOTH XTAL 1 AND XTAL2 SHOULD BE DRIVEN.
RESISTORS TO Vcc ARE NEEDED TO ENSURE VIH = 3.8V
IF TTL CIRCUITRY IS USED.
LC OSCILLATOR MODE
..l..
..Q..
45 ~H
120 ~H
20 pF
20 pF
NOMINAL f
5.2 MHz
3.2 MHz
.--_-~
XTAL1
C'= C+3Cpp
2
l...--...+----i XTAL2
Cpp "5 -10 pF PIN·TO·PIN
CAPACITANCE
EACH C SHOULD BE APPROXIMATELY 20 pF. INCLUDING STRAY CAPACITANCE.
WARNING:
PROGRAMMING, VERIFYING, AND
ERASING THE 8741A EPROM
An attempt to program a missocketed 8741A will result in severe
damage to the part. An indication of a properly socketed part is the
appearance of the SYNC clock output. The lack of this clock may
be used to disable the programmer.
Programming Verification
In brief, the programming process consists of: activating
the program mode, applying an address, latching the
address, applying data, and applying a programming pulse.
Each word is programmed completely before moving on to
the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions:
Pin
1.
Function
XTAL1
Clock Input (1 to 6MHz)
Reset
Initialization and Address Latching
Test 0
The Program/Verify sequence is:
Selection of Program or Verify Mode
EA
Activation of Program/Verify Modes
BUS
Addre~s
2.
Insert 8741 A in programming socket
3.
TEST 0
4.
EA = 23V (activate program mode)
= Ov
(select program mode)
5.
Address applied to BUS and P2(}'1
6.
RESET
7.
Data applied to BUS
8.
V DO = 25v (programm ing power)
= 5v
(latch address)
= Ov followed by one 50ms pulse to
= 5v
TEST 0 = 5v (verify mode)
9.
PROG
10.
V OD
11.
and Data Input
Data Output During Verify
AO= OV, CS = 5V, EA = 5V, RESET = OV, TESTO = 5V,
V DD = 5V , clock applied or internal oscillator operating,
BUS and PROG floating.
23V
12.
Read and verify data on BUS
Address Input
13.
TEST 0
VOO
Programming Power Supply
14.
RESET = Ov and repeat from step 5
PROG
Program Pulse Input
15.
Programmer should be at conditions of step 1 when
8741 A is removed from socket.
P20-1
7-71
= Ov
00188A
8041 A/8641 A18741 A
should be placed over the 8741A window to prevent
unintentional erasure.
8741A Erasure Characteristics
The erasure characteristics of the 8741A are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8741A in approximately 3 years while it would take approximately one week to cause erasure when exposed
to direct sunlight. If the 8741 A is to be exposed to these
types of lighting conditions for extended periods of
time, opaque labels are available from Intel which
The recommended erasure procedure for the 8741A is
exposure to shortwave ultraviolet light which has a
wavelength of 2537 A. The integrated dose (Le., UV intensity x exposure time) for erasure should be a minimum
of 15 w-sec/cm 2. The erasure time with this dosage is
approximately 15 to 20 minutes using an ultraviolet
lamp with a 12,000 p.W/cm 2 power rating. The 8741A
should be placed within one inch of the lamp tubes during erasure. Some lamps have a filter on their tubes
which should be removed before erasure.
A.C. TIMING SPECIFICATION FOR PROGRAMMING
TA = 25°C ±5°C, Vee = 5V ±5%, Voo = 25V ± 1V
Min.
Parameter
Symbol
tAW
Address Setup Time to RESET I
4tcy
tWA
Address Hold Time After RESET I
4tcy
tow
Data in Setup Time to PROG I
4tcy
two
Data in Hold Time After PROG I
4tcy
tPH
RESET Hold Time to Verify
4tcy
tvoow
Voo Setup Time to PROG I
4tcy
tVOOH
Voo Hold Time After PROG I
0
tpw
Program Pulse Width
50
tTW
Test 0 Setup Time for Program Mode
4tcy
tWT
Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
tr, tf
Voo and PROG Rise and Fall Times
0.5
tey
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA I.
4tcy
Note: If
TEST 0 is high, too
can
be triggered
by
Max.
Unit
60
mS
Test Conditions
4tcy
2.0
}J.s
}J.s
RESET I.
D.C. SPECIFICATION FOR PROGRAMMING
T A = 25°C ± 5°C, Vee = 5V ± 5%, Voo = 25V ± 1V
Symbol
Parameter
Min.
Max.
Unit
24.0
26.0
V
Voo Voltage Low Level
4.75
5.25
V
PROG Program Voltage High Level
21.5
24.5
V
0.2
V
24.5
V
VOOH
Voo Program Voltage High Level
VOOL
VPH
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
VEAL
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
mA
IpROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
7_7?
21.5
Test Conditions
onlRRA
8041 AJ8641 AJ8741 A
WAVEFORMS FOR PROGRAMMING
COMBINATION PROGRAMiVERIFY MODE (EPROM'S ONLYI
23V
EA
5V
_----II
- - - - - - - - - - - - - PROGRAM -
_.'""1'>------------
----~+-- VERIFY
TESTO
J--
DBO-DB7
---<
DATA TO BE
PROGRAMMED VALID
PROGRAM - - - - -
NEXT ADDR
VALID
NEXT
ADDRESS
LAST
ADDRESS
,"oowa'"oo~w,
Voo '"
trr-TI
I'~ i-two- - - -
+5
W
~
PROG
x==
I
+5------------
r----------,~.-----------------
I
+0
'
----'
VERIFY MODE (ROM/EPROMI
RESET
~\\..-. _ _- J/
=>---
\\...-_---J/
\'-----
- - -- - - - - - - -
ADDRESS
10-7) VALID
S_S__
NEXT ADDRESS VALID
ADDRESS 18-9) VALID
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.e., *23V), OR IF TO = 5V FOR THE 8741A. FOR THE
8041A PROG MUST ALWAYS FLOAT.
2. XTAL 1 AND XTAL 2 DRIVEN BY 3.6 MHz CLOCK WILL GIVE 4.17 !,sec tCY' THIS IS ACCEPT·
ABLE FOR 8741A·8 PARTS AS WELL AS STANDARD PARTS.
3. AO MUST BE HELD LOW (I.e., = OV) DURING PROGRAMNERIFY MODES.
The 8741A EPROM can be programmed by either of two
Intel products:
1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP series) peripheral
of the Intellec® Development System with a UPP-848
Personality Card.
7-73
00188A
inter
8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
• 110 Port or Memory Selector
• Low Input Load Current - 0.25 mA
Max, 116 Standard TTL Input Load
• Simple Expansion -' Enable Inputs
• Minimum Line Reflection - Low
Voltage Diode Input Clamp
• High Speed Schottky Bipolar
Technology - 18 ns Max Delay
• Outputs Sink 10 mA Min
• Directly Compatible with TTL Logic
Circuits
• 16·Pin Dual In-Line Ceramic or Plastic
Package
The Intel@ 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory
components with active low chip select input. When the 8205 is enabled, one of its 8 outputs goes "low", thus a single
row of a memory system is selected. The 3-chip enable inputs on the 8205 allow easy system expansion. For very large
systems, 8205 decoders can be cascaded such that each decoder can drive 8 other decoders for arbitrary memory
expansions.
The 8205 is packaged in a standard 16-pin dual in-line package, and its performance is specified over the temperature
range of O°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to obtain fast switching speeds
results in higher performance than equivalent devices made with a gold diffussion process.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
16
V-cc
Ao
Al
15
00
Al
0,
A2
14
°1
A2
02
13
°2
12
03
11
°4
E,
05
10
°5
E2
Os
9
06
E3
07
4
El
03
8205
E2
6
E3
07
GRD
8
8205
04
ADDRESS
PIN NAMES
E I' E3
00' 07
ENABLE INPUTS
DECODED OUTPUTS
J
1
7-74
OUTPUTS
A,
A2
E,
E2
EJ
L
L
H
L
H
L
H
L
L
Ii
H
L
L
H
H
L
L
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
l
l
L
H
H
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
l
H
L
H
H
l
H
H
~' ~ADD~~ INPUTS.
ENABLE
Ao
H
L
L
L
L
H
H
H
0
1
2
3
4
S
6
7
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Ii
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
AFN-00204B-01
8205
FUNCTIONAL DESCRIPTION
Decoder
The 8205 contains a one out of eight binary decoder. It accepts a three bit binary code and by gating this input. creates
an exclusive output that represents the value of the input
code.
AO
~
A,
0,
A2
°2
°3
For example. if a binary code of 101 was present on the AO.
A 1 and A2 address input lines. and the device was enabled.
an active low signal wou Id appear on the 05 output line.
Note that all of the other output pins are sitting at a logic
high. thus the decoded output is said to be exclusive. The
decoders outputs will follow the truth table shown below in
the same manner for all other input variations.
DECODER
°4
Os
Os
0;
Enable Gate
When using a decoder it is often necessary to gate the outputs with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.
(E"1-E2"-E3)
Figure 1. Enable Gate
The 8205 has a bu ilt-in function for such gating. The three
enable inputs (El E2. E3) are ANDed together and create
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating function to help reduce package count in his system.
ADDRESS
OUTPUTS
A,
A2
E,
E2
E3
a
1
2
3
4
5
6
7
L
H
L
H
L
H
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
L
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
l
7-75
ENABLE
Ao
L
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
AFN-00204B-02
8205
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias:
"COMMENT
-65°C to +1250 C
-65°C to +75°C
-65°C to +160o C
Ceramic
Plastic
Storage Temperature
Stresses above those listed under "Absolute Maximum Rat·
ing" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
-0.5 to +7 Volts
All Output or Supply Voltages
-1.0 to +5.5 Volts
All Input Voltages
125 mA
Output Currents
D.C. CHARACTERISTICS
8205
PARAMETER
SYMBOL
-
LIMIT
MAX.
-0.25
MIN.
IF
INPUT LOAD CURRENT
IR
INPUT LEAKAGE CURRENT
Vc
INPUT FORWARD CLAMP VOLTAGE
VOL
OUTPUT "LOW" VOLTAGE
VOH
V1L
OUTPUT HIGH VOLTAGE
V 1H
INPUT "HIGH" VOLTAGE
Ise
OUTPUT HIGH SHORT
CIRCUIT CURRENT
Vox
OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT
lee
POWER SUPPLY CURRENT
UNIT
Vee = 5.25V, V F = 0.45V
10
J-IA
-1.0
V
Vee = 5.25V, V R = 5.25V
Vee = 4.75V, Ie = -5.0 mA
0.45
2.4
INPUT "LOW" VOLTAGE
0.85
2.0
-AO
TEST CONDITIONS
mA
-120
0.8
70
V
Vee = 4.75V, IOL = 10.0 mA
V
Vee = 4.75V, IOH = -1.5 mA
V
Vee = 5.0V
V
Vee = 5.0V
mA
Vee = 5.0V, VOUT = OV
V
Vee = 5.0V, lox = 40 mA
mA
Vee = 5.25V
TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
100
80
60
J
J'
TA = 75OC ........
20
r...... ~
~ TA -:: ooc
vee = 5.0V
40
I
V
TA = 7SOC __
TA = 2S"C ___
OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE
"
-
"
TA = O°C-
.4
,
-30
/J
-50
.8
OUTPUT "LOW" VOL TAGE (V)
1.0
,
1.0
TA = 75OC-
1.0
4.0
OUTPUT "HIGH" VOLTAGE (V)
7-76
[\ ~
TA = 25"C-\- --\1\
2.0
3.0
f--
TA = OOC
I
2.0
-
4.0
3.0
I
-40
.I
I
Vee = 5.0V
TA = 750C
I[
T~ = ooc
.6
uV
i;, =isoc
II
t- TA = 25"C
.2
W/.
I
-20
~
1. '- t..M
-Vee = 5.0V
-10
DATA TRANSFER FUNCTION
5.0
fl-.V
I .I.
5.0
o
.2
.4
.6
.8
1.0
-,
\
\
\ \
\.. ~ ~
\
1.2 1.4 1.6
1.8 2.0
INPUT VOLTAGE (V)
AFN-00204B-05
8205
SWITCHING CHARACTERISTICS
Conditions of Test:
Test Load
I nput pulse amplitudes:
390rl
2.5V
I nput rise and fall times: 5 nsec
between 1V and 2V
Measurements are made at 1.5V
All Transistors 2N2369 or Equivalent.
C = 30 pF
L
Test Waveforms
ADDRESS OR ENABLE
INPUT PULSE
OUTPUT
A.C. CHARACTRISTICS
TA
= QOCto
+75°C,V CC
= 5V
±5% unless otherwise specified.
PARAMETER
SYMBOL
MAX. LIMIT
t++
ADDRESS OR ENABLE TO
OUTPUT DE LA Y
t_+
t+_
--
t --
ns
18
ns
18
ns
18
CIN (1)
INPUT CAPACITANCE
1. This parameter
IS
periodically sampled and
IS
4(typ.)
5(typ.)
P8205
C8205
UNIT
18
TEST CONDITIONS
ns
pF
pF
f
=
Vee = OV
= 2.0V, T A ~ 250 e
1 MHz,
VBIAS
not 100% tested.
TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE
20,-----,-----,------,-----,
20,-------,--------.-1------.
Vec
=
CL
= 30 pF
5.0V
15r--------~-------.~1~----~
15
-:~~.:.~~-~------
10
50
100
150
O~------~------~------~
o
50
75
25
200
AMBIENT TEMPERATURE lOCI
LOAD CAPACITANCE (pFI
7-77
AFN-00204B-06
8251A/S2657
PROGRAMMABLE COMMUNICATION INTERFACE
Ii
Synchionous and Asynchronous
Operation
• Asynchronous Baud Rate 19.2K Baud
• Full Duplex, Double Buffered, Trans·
mitter and Receiver
• Synchronous 5·8 Bit Characters;
Internal or External Character Synchro·
nization; Automatic Sync Insertion
• Error Detection Framing
• Asynchronous 5·8 Bit Characters;
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation; 1,
1112, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect
and Handling.
• Synchronous Baud Rate Baud
DC to
Parity, Overrun and
• Fully Compatible with 8080/8085 CPU
• 28·Pin DIP Package
• All Inputs and Outputs are TTL
Compatible
• Single
DC to 64K
+ 5V Supply
• Single TTL Clock
The Intel® 8251A is the enhanced version of the industry standard, Intel® 8251 Universal Synchronous/Asynchronous
Receiver/Transmitter (USART), designed for data communications with Intel's new high performance family of
microprocessors such as the 8085. The 8251A is used as a peripheral device and is programmed by the CPU to operate
using virtually any serial data transmission technique presently in use (including IBM "bi-sync"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream for
transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the
CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has
received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNDET, TxEMPTY. The chip is constructed using N-channel silicon
gate technology.
~--
---~-~-----~--~~--
PIN CONFIGURATION
BLOCK DIAGRAM
DI
Do
RxD
Vel
GND
RxC
DTR
0 7 "0 0
RTS
Dr,
DSR
D,
RESET
TxC
ClK
WR
CS
TxEMPTY
TxD
CTS
C/O
SYNDET/SO
RD
RxRDY
--......----~
TxRDY
PIN NAMES
01- 0 0
C/O
fill
~R
CS
CLK
~;~~r~~~:8D~lt~11S
~::t~ ~:~: ~~~':nat~:1
!O
be Written or Redd
i
Commdnd
TxD
Chip Enable
Clock Pulse ITTLI
Reset
Transmitter Clock
Transmitter Data
RXC
Receiver Clock
RxD
Receiver Data
RxRDY
Receiver Ready (has chClracter for 80801
TxRDY
Transmitter Ready (ready for char from BOBOl
RESET
hl
--_._------OSR
Data Set Ready
OTR
Data Terminal Ready
SYNOET/SO
SyncOetectl
RTS
Request to Send Data
II
I
Break Detect
CTS
Clear to Send Data
TxE
Transmitter Empty
Vee
+5 Volt Supply
GNO
Ground
7-78
8251 A/~2t)5 7
FEATURES AND ENHANCEMENTS
• Tx Enable logic enhancement prevents a
Tx Disable command from halting transmission until all data previously written has
been transmitted. The logic also prevents
the transmitter from turning off in the middle
of a word.
8251 A is an advanced design of the industry standard USART, the Intel® 8251. The 8251A operates with an extended range of Intel microprocessors that includes the new 8085 CPU and maintains compatibility with the 8251. Familiarization
time is minimal because of compatibility and
involves only knowing the additional features and
enhancements, and reviewing the AC and DC specifications of the 8251 A.
• When External Sync Detect is programmed,
Internal Sync Detect is disabled, and an External Sync Detect status is provided via a
flip-flop which clears itself upon a status read.
• Possibility of false sync detect is. minimized
by ensuring that if double character sync is
programmed, the characters be contiguously
detected and also by clearing the Rx register
to all ones whenever Enter Hunt command is
issued in Sync mode.
The 8251A incorporates all the key features of
the 8251 and has the following additional features
and enhancements:
• 8251A has double-buffered data paths with
separate I/O registers for control, status,
Data In, and Data Out, which considerably
simplifies control programming and minimizes CPU overhead.
• As long as the 8251A is not selected, the
RD and WR do not affect the internal operation of the device.
• In asynchronous operations, the Receiver
detects and handles "break" automatically,
relieving the CPU of this task.
• The 8251 A Status can be read at any time
but the status update will be inhibited during
status read.
• A refined Rx initialization prevents the
Receiver from starting when in "break"
state, preventing unwanted interrupts from
a disconnected USART.
• The 8251 A is free from extraneous gl itches
and has enhanced AC and DC characteristics,
providing higher speed and better operating
margins.
• At the conclusion of a transmission, TxD
line will always return to the marking state
unless SBRK is programmed.
• Synchronous Baud rate from DC to 64K.
• Fully compatible with Intel's new industry
standard, the MCS-85.
7-79
00216A
8251 A/S2657
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tio{1 of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
.A.mbient Temperature Under Bias . . . . . . . . . O°C to 70
c
e
Storage Temperatur~ . . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
T A = O°C to 70°C; Vee = 5.0V ±5%; GND = OV
Parameter
Symbol
Min.
Unit
Max.
Test Conditions
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.2
Vee
V
VOL
Output Low Voltage
0.45
V
IOL = 2.2 mA
VOH
Output High Voltage
V
IOH = -400 J.lA
IOFL
Output Float Leakage
±10
IlL
Input Leakage
±10
J.lA
VIN= Vee TO 0.45V
Icc
Power Supply Current
100
mA
All Outputs = High
2.4
V OUT = Vee TO 0.45V
J.lA
CAPACITANCE
TA = 25°C; Vee = GND = OV
Symbol
Parameter
Min.
I nput Capacitance
CIN
I/O Capacitance
ClIO
Max.
Unit
10
pF
fc = 1MHz
20
pF
Unmeasured pins returned to GND
Test Conditions
+20
+10
0:
2V
>
~Cl
....
~
....
lN914
8251A
t-----,--+---o
::l
0
-1
OUT
-10
6K
-20 L--.....J.'--...J....._ _--L_ _ _. L -_ _
-50
. +50
+100
-100
~
Cl
=
150pF.
.:, CAPACITANCE (pF)
Figure 17. Typlcalll Output Delay vs. Il
Capacitance (pF)
Figure 16. Test Load Circuit
7·80
00216A
8251 A/S2657
A.C. CHARACTERISTICS
Bus Parameters (Note 1)
Read Cycle:
MIN.
PARAMETER
SYMBOL
MAX.
TEST CONDITIONS
UNIT
tAR
Address Stable Before READ (CS, C/D)
50
ns
Note 2
tRA
Address Hold Time for READ (CS, C/D)
50
ns
Note 2
tRR
READ Pulse Width
250
ns
tRD
Data Delay from READ
tDF
READ to Data Floating
10
250
ns
100
ns
MAX.
UNIT
3, CL = 150 pF
Write Cycle:
PARAMETER
SYMBOL
tAW
MIN.
Address Stable Before WRITE
50
ns
tWA
Address Hold Time for WR ITE
50
ns
tww
WRITE Pulse Width
250
ns
tDW
Data Set Up Time for WR ITE
150
ns
tWD
Data Hold Time for WR ITE
50
ns
tRV
Recovery Time Between WRITES
6
tCY
TEST CONDITIONS
Note 4
NOTES: 1. AC timings measured VOH = 2.0, VOL = 0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and Command/Data (C/O) are considered as Addresses.
3. Assumes that Address is valid before R Dt.
4. This recovery time is for Mode Initialization only. Write Data is allowed only when TxRDY = 1.
Recovery Time between Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
Input Waveforms for AC Tests
______X:::
2.4 - - - - - - , .
0.45
X_____
,.----------------...
p6~~is
7-81
:::
,....----
-
00216A
8251A/S2657
Other Timings:
SYMBOL
PARAMETER
tR, tF
Ciock
Clock
Clock
Clock
tDTx
TxD Delay from Falling Edge of TxC
fTx
Transmitter Input Clock Frequency
tCY
tq>
qj
Period
High Pulse Width
Low Pulse Width
Rise and Fall Time
IMIN.
320
MAX.
UNIT
TEST CONDITIONS
1350
ns
Notes 5, 6
140
90
tCY-9O
ns
ns
ns
ps
20
1x Baud Rate
16x Baud Rate
64x Baud Rate
1
DC
DC
DC
64
310
615
kHz
kHz
kHz
Transmitter Input Clock Pulse Width
tTPw
tTPD
fRx
tRPW
tRPD
tTxRDY
tTxRDY CLEAR
tRxRDY
tRxRDY CLEAR
tiS
1x Baud Rate
16x and 64x Baud Rate
12
1
tCY
tCY
Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
Receiver Input Clock Frequency
15
3
tCY
tCY
1x Baud Rate
16x Baud Rate
64x Baud Rate
Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
TxRDY Pin Delay from Center of last Bit
TxRDY t from Leading Edge of WR
DC
DC
DC
64
310
615
kHz
kHz
kHz
12
1
tCY
tCY
15
3
8
tCY
tCY
tCY
6
24
tCY
tCY
6
tCY
Note 7
Note 7
Note 7
24
tCY
Note 7
16
tCY
Note 7
RxRDY Pin Delay from Center of last Bit
RxRDY ,} from Leading Edge of RD
Internal SYNDET Delay from Rising
Edge of RxC
Note 7
tES
External SYNDET Set-Up Time Before
Falling Edge of RxC
tTxEMPTY
twc
TxEMPTY Delay from Center of Last Bit
Control Delay from Rising Edge of
WRITE {TxEn, DTR, RTS)
20
tCY
Note 7
8
tCY
Note 7
tCR
Control to READ Set-Up Time (DSR, CTS)
20
tCY
Note 7
5. The TxC and RxC frequencies have the following limitations with respect to ClK.
For 1x Baud Rate, fTx or fRx ,,;; 1/(30 tCY)
For 16x and 64x Baud Rate, fTx or fRx";; 1/(4.5 tCY)
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
7-82
00216A
inter
8253/8253·5
PROGRAMMABLE INTERVAL TIMER
• MCS-85™ Compatible 8253·5
• Count Binary or BCD
• 3 Independent 16·Bit Counters
• DC to 2 MHz
• Programmable Counter Modes
• Single + 5V Supply
• 24·Pin Dual In·Line Package
The Intel\!) 8253 is a programmable counter/timer chip designed for use as an Intel microcornputer peripheral. It uses
nMOS technology with a single +5V supply and is packaged in a 24-pin plastic DIP.
It is organized as 3 independent 16-bit counters, each with a count rate of up to 2 MHz. All modes of operation are software programmable.
PIN CONFIGURATION
D7
Vee
D6
Ds
WR
AD
D4
cs
D3
A,
D2
Ao
D,
eLK 2
BLOCK DIAGRAM
ClK 0
DATA
BUS
BUFFER
GATE 0
OUT 0
OUT 2
Do
eLK 0
GATE 2
OUT 0
eLK 1
RD---Cf
ClK 1
GATE 1
GATE 1
GATE 0
OUT 1
OUT 1
GND
CS--------'
PIN NAMES
D7 D O
CLK N
DATA BUS 18 BIT!
GATE N
COUNTER GATE INPUTS
OUT N
CLK 2
COUNTER
=2
COUNTER CLOCK INPUTS
GATE 2
-OUT2
COUNTER OUTPUTS
RD
READ COUNTER
WR
WRITE COMMAND OR DATA
CS
CHIP SELECT
Ao A
COUNTER SELECT
Vee
GND
GI'IOUND
+5 VOL TS
INTERNAL BUS /
INTel CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTel PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPliED.
'0 INTel CORPORATION. 1979
AFN-00745A-Ol
7-83
8253/8253·5
FUNCTIONAL DESCRIPTION
AO,A1
General
These inputs are normally connected to the address bus.
Their function is to select one of the three counters to be
operated on and to address the control word register for
mode selection.
The 8253 is a programmable interval timer/counter
specifically designed for use with the Intel n • Microcomputer systems. Its function is that of a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
CS (Chip Select)
A "low" on this input enables the 8253. No reading or
writing will occur unless the device is selected. The CS
input has no effect upon the actual operation of the
counters.
The 8253 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays undersoftware control. I nstead of setting up timing
loops in systems software, the programmer configures the
8253 to match his requirements, initializes one of the
counters of the 8253 with the desired quantity, then upon
command the 8253 will count out the delay and interrupt
the CPU when it has completed its tasks. It is easy to see
that the software overhead is minimal and that multiple
delays can easily be maintained by assignment of priority
levels.
Other counter/timer functions that are non-delay in
nature but also common to most microcomputers can be
implemented with the 8253.
• Programmable Rate Generator
• Event Counter
• Binary Rate Multiplier
• Real Time Clock
• Digital One-Shot
• Complex Motor Controller
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface
the 8253 to the system data bus. Data is transmitted or
received by the buffer upon execution of I Nput or OUTput
CPU instructions. The Data Bus Buffer has three basic
functions.
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus
and in turn generates control signals for overall device
operation. It is enabled or disabled by CS so that no
operation can occur to change the function unless the
device has been selected by the system logic.
Figure 1. Block Diagram Showing Data Bus Buffer and
Read/Write logic Functions
-
RD (Read)
CS
RD
WR
A,
Ao
A "low" on this input informs the 8253 that the CPU is
inputting data in the form of a counters value.
0
1
0
0
0
Load Counter No. 0
0
1
0
0
1
Load Counter No.1
WR (Write)
A "low" on this input informs the 8253 that the CPU is
outputting data in the form of mode information or loading
counters.
7·84
0
1
0
1
0
Load Counter No. 2
0
1
0
1
1
Write Mode Word
0
0
1
0
0
Read Counter No. 0
0
0
1
0
1
Read Counter No. 1
0
0
1
1
0
Read Counter No.2
0
0
1
1
1
No-Operation 3-State
1
X
X
1
1
X
X
X
X
Disable 3-State
0
No-Operation 3·State
AFN-0074SA-02
8253/8253·5
Control Word Register
The Control Word Register is selected when AO. A 1 are 11.
It then accepts information from the data bus buffer and
stores it in a register. The information stored in this
register controls the operational MODE of each counter.
selection of binary or BCD counting and the loading of
each count register.
The Control Word Register can only be written into; no
read operation of its contents is available.
Counter #0, Counter #1, Counter #2
These three functional blocks are identical in operation so
only a single Counter will be described. Each Counter
consists of a single. 16-bit. pre-settable. DOWN counter.
The counter can operate in either binary or BCD and its
input. gate and output are configured by the selection of
MODES stored in the Control Word Register.
The counters are fully independent and each can have
separate Mode configuration and counting operation.
binary or BCD. Also. there are special features in the
control word that handle the loading of the count value so
that software overhead can be minimized for these
functions.
The reading of the contents of each counter is available to
the programmer with simple READ operations for event
counting applications and special commands and logic
are included in the 8253 so that the contents of each_
counter can be read "on the fly" without having to inhibit
the clock input.
8253 SYSTEM INTERFACE
Figure 2. Block Diagram Showing Control Word
Register and Counter Functions
The 8253 is a component of the Intel™ Microcomputer
Systems and interfaces in the same manner as all other
peripherals of the family. It is treated by the systems
software as an array of peripheral I/O ports; three are
counters and the fourth is a control register for MODE
programming.
ADDRESS BUS (16)
CONTROL BUS
Basically. the select inputs AO. A 1 connect to the AO. A 1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method.
Or it can be connected to the output of a decoder. such as
an Intel® 8205 for larger systems.
8253
11
Figure 3. 8253 System Interface
7-85
AFN-00745A-03
8253/8253·5
MODE 3: Square Wave Generator
MODE 0: Interrupt on Terminal Count
CLOCK
CLOCK
2
WRn~
I
OUTPUT
In =4)
OUTPUT
In =5)
4
I
o
I
OUTPUT (INTERRUPT)
In=4)
I-+-n-:
I
I
I
I
WRm~
,
,
:L........Jr .....:.'----
GATE
5
4
.1
OUTPUT (INTERRUPT)
1m =5)
'----'
A
A+8=m
MODE 4: Software Triggered Strobe
MODE 1: Programmable One·Shot
TRIGGER
~
4
OUTPUT
~~--------~
LOADn~
TRIGGER~
OUTPUT
4
3
2
3
2
GATE
1
OUTPUT
MODE 2: Rate Generator
-----~~~------
o
- - , L_ _ _ _ _ _ _ _- '
------~----~~--~~
MODE 5: Hardware Triggered Strobe
CLOCK
GATE
-----1
4
OUTPUT
In
= 4)
LJ
GATE~
4343210
OUTPUT
In =
4)
U
Figure 5. 8253 Timing Diagrams
7·86
AFN-00745A-06
8253/8253-5
8253 READ/WRITE PROCEDURE
Write Operations
MODE Control Word
Counter n
The systems software must program each counter of the
8253 with the mode and quantity desired. The programmer must write out to the 8253 a MODE control word and
the programmed number of count register bytes (1 or 2)
prior to actually using the selected counter.
LSB
Count Register byte
Counter n
MSB
Count Register byte
Counter n
The actual order of the programming is quite flexible.
Writing out of the MODE control word can be in any
sequence of counter selection, e.g., counter #0 does not
have to be first or counter #2 last. Each counter's MODE
control word register has a separate address so that its
loading is completely sequence independent. (SCO, SC1)
Note: Format shown is a simple example of loading the 8253 and
does not imply that it is the only format that can be used.
The loading of the Count Register with the actual count
value, however, must be done in exactly the sequence
programmed in the MODE control word (RLO, RL 1). This
loading of the counter's count register is still sequence
independent like the MODE control word loading, but
when a selected count register is to be loaded it must be
loaded with the number of bytes programmed in the
MODE control word (RLO, RL 1). The one or two bytes to
be loaded in the count register do not have to follow the
associated MODE control word. They can be programmed
at any time following the MODE control word loading as
long as the correct number of bytes is loaded in order.
No. ,
MODE Control Word
Counter 0
No. 2
MODE Control Word
Counter'
No. 3
MODE Control Word
Counter 2
Figure 6. Programming Format
Al
All counters are down counters. Thus, the value loaded
into the count register will actually be decremented.
Loading all zeroes into a count register will result in the
maximum count (2 '6 for Binary or 104 for BCD). In MODE a
the new count will not restart until the load has been
completed. It will accept one of two bytes depending on
how the MODE control words (RLO. RL 1) are programmed. Then proceed with the restart operation.
AO
, ,
, ,
,
1
Count Register Byte
Counter'
0
1
Count Register Byte
Counter'
0
1
No.4
LSB
No. 5
MSB
No.6
LSB
Count Register Byte
Counter 2
No. 7
MSB
Count Register Byte
Counter 2
No.8
LSB
No.9
MSB
Count Register Byte
Counter 0
Count Register Byte
Counter 0
,
,
0
0
0
0
0
0
Note: The exclusive addresses of each counter's count register make
the task of programming the 8253 a very simple matter, and
maximum effective use of the device will result if this feature
is fully utilized.
Figure 7. Alternate Programming Formats
7-87
AFN-0074SA-07
8253/8253·5
Read Operation Chart
Read Operations
In most counter applications it becomes necessary to read
the value of the count in progress and make a
computational decision based on ihis quaniiiy. Eveni
counters are probably the most common application that
uses this function. The 8253 contains logic that will allow
the programmer to easily read the contents of any of the
three counters without disturbing the actual count in
progress.
There are two methods that the programmer can use to
read the value ot'the counters.' The first method involves
the use of simple 1/0 read operations of the selected
counter. By controlling the AD, A 1 inputs to the 8253 the
programmer can select the counter to be read (remember
that no read operation of the mode register is allowed AD,
A1-11). The only requirement with this method is that in
order to assure a stable count reading the actual operation
of the selected counter must ~ inhibited either by
controlling the Gate input or by external logic that inhibits
the clock input. The contents of the counter selected will
be available as follows:
Al
AO
0
0
0
Read Counter No.
O.
1
a
Read Counter No. 1
1
a
0
Read Counter No.2
1
1
a
Illegal
RD
a
Reading While Counting
first 1/0 Read contains the least significant byte (LSB).
In order for the programmer to read the contents of any
counter without effecting or disturbing the counting
operation the 8253 has special internal logic that can be
accessed using. simple WR commands to the MODE
register. Basically, when the programmer wishes to read
the contents of a selected counter "on the fly" he loads the
MODE register with a speCial code which latches the
present count value into a storage register so that its
contents contain an accurate, stable quantity. The
programmer then issues a normal read command to the
selected counter and the contents of the latched register is
ayatlable.
second 1/0 Read contains the most significant byte
(MSB).
MODE Register for Latching Count
Due to the .internal logic of the 8253 It is absolutely
necessary to complete the entire reading procedure. If two
bytes are programmed to be read then two bytes must be
read before any loading WR command can be sent to the
same counter.
AO, A1
11
se 1,SeD -
specify counter to be latched.
05,04
00 designates counter latching operation
X
don't care.
The same limitation applies to this mode of reading the
counter as the previous method. That is, it is mandatory
to complete the entire read operation as programmed.
This command has no effect on the counter's mode.
CLK
3MHz
• 1.5MHz
2
8085
CLK
8253-5
*If an 8085 clock output is to drive an 8253-5 clOck input, it must be reduced to 2 MHz or less_
Figure 8. r.1CS·8S™ Clock' Interface·
7-88
AFN-0074SA-08
8253/8253·5
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias
Storage Temperature
Voltage On Any Pin
With Respect to Ground
Power Dissipation
D.C. CHARACTERISTICS
device. This is a stress rating only and functional opera-
O°Cto 70°C
-65° C to +150° C
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliabili tv.
-0.5 Vto +7 V
1 Watt
D
(TA = ODC to 70 C; Vee = 5V ±5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.2
Vee+· 5V
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
2.4
IlL
Input Load Current
±10
IOFL
Output Float Leakage
±10
lee
Vee Supply Current
I
140
I
TEST CONDITIONS
V
Note 1
V
Note 2
f.1A
V IN = Vee to OV
f.1A
VOUT = Vee to OV
mA
Note 1: 8253, IOL = 1.6 mA; 8253-5, IOL = 2.2 mA.
Note 2: 8253, IOH = -150 f.1A; 8253-5, IOH = -400 f.1A.
CAPACITANCE
D
TA = 25 C; Vee = GND = OV
Symbol
Parameter
Max.
Unit
CIN
Input Capacitance
10
pF
fc = 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss
Min.
Typ.
7-89
Test Conditions
AFN-00745A-09
8253/8253·5
A.C. CHARACTERISTICS
TA
= o°c to 70°C; Vee = 5.0V ±5%;
GND
= OV
Bus Parameters (Note 1)
Read Cycle:
8253
SYMBOL
PARAMETER
8253-5
MAX.
MIN.
50
tAR
Address Stable Before READ
tRA
Address Hold Time for READ
tRR
READ Pulse Width
tRO
Data Delay From READI21
tOF
READ to Data Floating
25
tRY
Recovery Time Between READ
and Any Other Control Signal
1
MIN.
MAX.
30
UNIT
ns
5
5
ns
400
300
ns
300
125
25
200
ns
100
ns
1
J,LS
Write Cycle:
8253-5
8253
SYMBOL
MIN.
PARAMETER
MAX.
MIN.
MAX.
UNIT
tAW
Address Stable Before WR ITE
50
30
ns
tWA
Address Hold Time for WR ITE
30
30
ns
tww
WR ITE Pulse Width
400
300
ns
tow
Data Set Up Time for WR ITE
300
250
ns
two
Data Hold Time for WR ITE
40
30
ns
1
1
J1S
tRV
Recovery Time Between WRiTE
and Any Other Control Signal
Notes: 1. AC timings measured at Vo H = 2.2, Vo L = 0.8
2. Test Conditions: 8253, CL = 1OOpF; 8253-5: CL = 150pF.
Write Timing:
____
Ao-1. CS
Read Timing:
J~~--------------~~~-------
DATA BUS
Input Waveforms for A.C. Tests:
2 . 4 - - -...
>
X
2
•
_ '0 •. 8
TEST POINTS
0.45 _ _ _..J
7-90
<:::x'---AFN-00745A-l0
8253/8253·5
Clock and Gate Timing:
8253
SYMBOL
Note 1:
PARAMETER
8253·5
MIN.
MAX.
MIN.
MAX.
de
380
de
tCLK
Clock Per iod
380
tPWH
High Pulse Width
230
tPWL
low Pulse Width
tGW
Gate Width High
tGL
tGS
UNIT
ns
230
ns
150
150
ns
150
150
ns
Gate Width low
100
100
ns
Gate Set Up Time to ClKt
100
100
ns
50
50
ns
tGH
Gate Hold Time After ClKt
too
Output Delay From ClK-!-11 J
400
400
ns
tODG
Output Delay From Gate-!-11]
300
300
ns
Test Conditions: 8253: CL = 1OOpF; 8253·5: CL = 150pF.
7-91
AFN-Q0745A-11
8255A/8255A·5
PROGRAMMABLE PERIPHERAL INTERFACE
• MCS·85™ Compatible 8255A·5
• 24 Programmable I/O Pins
• Direct Bit Set/Reset Capability Easing
Control Application Interface
• Completely TTL Compatible
• 40·Pin Dual In·Line Package
• Fully Compatible with Intel® Micro·
processor Families
• Reduces System Package Count
• Improved Timing Characteristics
• Improved DC Driving Capability
The Intel@ 8255A is a general purpose programmable 1/0 device designed for use with Intel@ microprocessors. It has
241/0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In the first
mode (MODE 0), each group of 121/0 pins may be programmed in sets of 4 to be input or output. In MODE 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining 4 pins, 3 are used for handshaking and interrupt control signals. The third mode of operation (MODE 2) is a bidirectional bus mode which uses 8
lines for a bidirectional bus, and 5 lines, borrowing one from the other group, for handshaking.
PIN CONFIGURATION
8255A BLOCK DIAGRAM
S~~:L~~S { - - +5V
-_GND
10
PA7-PAO
10
pe7- pee
PIN NAMES
0 7 -0.
DATA BUS (BI-DIRECTIONAL)
RESET
RESET INPUT
CHIP SElECT
CS
RD
READ INPUT
WR
WRITE INPUT
AO.A1
PORT ADDRESS
PA7·PAO
PORT A (BIT)
P87·P80
PORTB (BIT)
PC7.f'CO
PORTe (BIT)
Vee
+5 VOLTS
GND
'VOLTS
7-92
AFN-00744A-01
8255A18255A·5
8255A FUNCTIONAL DESCRIPTION
General
The 8255A is a programmable peripheral interface (PPI)
device designed for use in Intel® microcomputer
systems. Its function is that of a general purpose 1/0
component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the 8255A is programmed by the system software
so that normally no external logic is necessary to interface peripheral devices or structures.
(RD)
Read. A "low" on this input pin enables the 8255A to
send the data or status information to the CPU on the
data bus. In essence, it allows the CPU to "read from"
the 8255A.
(WR)
Write. A "low" on this input pin enables the CPU to write
data or control words into the 8255A.
(Ao and A 1)
Port Select 0 and Port Select 1. These input signals, in
conjunction with the RD and WR inputs, control the
selection of one of the three ports or the control word
registers. They are normally connected to the least
significant bits of the address bus (Ao and A 1).
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface
the 8255A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information are also transferred through the data bus buffer.
8255A BASIC OPERATION
Read/Write and Control Logic
The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the
Control Groups.
INPUT OPERATION (READ)
Al
AO
RD
WR
CS
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
PORT A
DATA BUS
PORT B DATA BUS
PORT C DATA BUS
OUTPUT OPERATION
(WRITE)
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
DATA
DATA
DATA
DATA
X
1
X
1
X
0
X
1
1
0
DATA BUS
3-STATE
I LLEGAL CONDITION
X
X
1
1
0
DATA BUS=3-STATE
=
=
=
BUS
BUS
BUS
BUS
= PORT A
= PORT B
= PORT C
= CONTROL
DISABLE FUNCTION
(CS)
Chip Select. A "low" on this input pin enables the communiction between the 8255A and the CPU.
=
Figure 1. 8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions
7-93
AFN-00744A-02
8255A18255A·5
(RESEn
Ports At St and C
Reset A "high on this input clears the control register
and all ports (A, C, C) are set to the input mode.
The 8255A contains three a. bit ports (A, B, and C). All
can be configured in a wide variety of functional characteristics by the system software but each has its own
special features or "personality" to further enhance the
power and flexibility of the 8255A.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255A. The control word contains information such as "mode", "bit set", "bit reset",
etc., that initializes the functional configuration of the
8255.
Port A. One 8-bit data output latch/buffer and one 8-bit
data input latch.
Port B. One 8-bit data input/output latch/buffer and one
8-bit data input buffer.
Each of the Control blocks (Group A and Group B) accepts
"commands" from the Read/Write Control Logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.
Port C. One 8-bit data output latch/buffer and one 8-bit
data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control.
Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in
conjunction with ports A and B.
Control Group A - Port A and Port C upper (C7-C4)
Control Group B - Port B and Port Clower (C3-CO)
The Control Word Register can Only be written into. No
Read operation of the Control Word Register is allowed.
PIN CONFIGURATION
PAl
PA6
_ _ +,v
POWER
SUPPLIES
{
-_GNO
10
Do
FlA7-PAO
0,
0,
OJ
8255A
D.
0,
10
PC7-PC4
10
PC3-PCO
P85
PBl l
19
22 "l P84
P82f
20
21
1 PBJ
PIN NAMES
10
PB7-PBO
D7 Do
RESET
CS
:
DATA BUS (BIDIRECTION~
RESET INPUT
CHIP SelECT
RD
READ INPUT
WR
WRITE INPUT
AD. AT
PORT ADDRESS
PA7·PAD
PORT A (BIT)
PB7·PBD
PORT B (BIT)
Pe7·PCD
PORT C (BITI
----Vee
GND
~5VOL1S
(J
VOLTS
-
- --~=:1
_.
I
i
Figure 2. 8225A Block Diagram Showing Group A and
Group B Control Functions
7·94
AFN-00744A-03
's18255A18255Ao5
~
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for ex tended periods may affect device
reliabili tv.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . . -65"C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . . -O.5V to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
TA = O°C to 70°C. Vee = +5V ±5%; GND = OV
SYMBOL
V IL
PARAMETER
MIN.
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL (DB)
Output Low Voltage (Data Bus)
MAX. UNIT
VOL(PER) Output Low Voltage (Peripheral Port)
VOH (DB)
VOH(PER) Output High Voltage (Peripheral Port)
Darlington Drive Current
TEST CONDITIONS
V
Vee
V
0.45
V
IOL = 2.5mA
V
IOL = 1.7mA
0.45
Output High Voltage (Data Bus)
IOARI11
0.8
2.4
V
IOH
2.4
V
IOH = -200J.LA
-1.0
-4.0
mA
='
-400J.LA
R EXT = 750[2; VEXT= 1.5V
lee
Power Supply Current
120
mA
IlL
Input Load Current
±10
J.LA
VIN = Vce to OV
IOFL
Output Float Leakage
±10
J.LA
VOUT = Vec to OV
Note1:
Available on any 8 pins from Port Band C.
CAPACITANCE
TA = 25°C; Vee = GND =
SYMBOL
ov
PARAMETER
MIN.
TYP.
UNIT
MAX.
TEST CONDITIONS
CIN
I nput Capacitance
10
pF
fc=1MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to GN D
~~~!~
L:.:.J
l ___ :YV ------,..,
I
VEXT*
100PF
'VEXT is set at various voltages during testing to guarantee the specification.
Figure 24. Test Load Circuit (for dB)
7·95
AFN-00744A-17
8255A/8255A·5
A.C. CHARACTERISTICS
TA = o°c to 70°C; VCC = +5V ±5%; GND = OV
Bus Parameters
Read:
8255A
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tAR
Address Stable Before READ
0
ns
tRA
Address Stable After READ
0
ns
tRR
READ Pulse Width
tRD
Data Valid From R EAD[l)
tDF
Data Float After READ
tRV
Time Between READs and/or WR ITEs
ns
300
250
10
150
ns
ns
ns
850
Write:
8255A
SYMBOL
PARAMETER
MAX.
MIN.
UNIT
tAW
Address Stable Before WR ITE
a
ns
tWA
Address Stable After WR ITE
20
ns
tww
WR ITE Pulse Width
400
ns
tDW
Data Valid to WR ITE (T.E.)
100
ns
tWD
Data Valid After WR ITE
30
ns
Other Timings:
8255A
SYMBOL
PARAMETER
tWB
WR = 1 to Output[ 1)
tlR
Periphera I Data Before R D
MIN.
MAX.
350
UNIT
ns
a
ns
tHR
Peripheral Data After RD
a
ns
tAK
ACK Pulse Width
300
ns
tST
STB Pulse Width
500
ns
tps
Per. Data Before T. E. of STB
a
ns
tpH
Per. Data After T.E. of STB
tAD
ACK = a to Output[ 1)
ns
tKD
ACK = 1 to Output Float
tWOB
WR = 1 toOBF =0(1)
650
ns
tAOB
ACK = a to OBF = 1(1)
350
ns
tSIB
ST B = 0 to I B F = 1 (1)
300
ns
tRIB
RD = 1 to IBF = all)
300
ns
tRIT
RD = a to INTR = 0(1)
400
ns
tSIT
STB = 1 to INTR = 1(1 )
300
ns
tAIT
ACK = 1 to INTR = 1(1 )
350
ns
tWIT
WR = 0 to INTR = 0(1 )
850
ns
180
20
300
ns
250
ns
Notes: 1. Test Conditions: 8255A: CL = 100pF;8255A-5: CL = 150pF.
2. Period of Reset pulse must be at least 50~s during or after power on.
Subsequent Reset pulse can be 500 ns min.
7-96
AFN-00744A-18
8255A18255A·5
2.4------....
0.45 _ _ _ _
~2.0X
X
~
2.O -.
0.8';::' TEST POINTS ---...
O.~
'-_ _ _ __
Figure 25. Input Waveforms for A.C. Tests
RO
f""-1
['""--X______
. ______
['"'--1--------
INPUT _ _
CS.
Al. Ao-----------E=-:
° -°
7
0 -
________
~-+--+-i-----J.t
-+1 (
-=--=--=--=--=--=--. ;
- - tR- D
f . .- ' - - ---
f 4 .-
-
-
-
-
--
tDF - - - - - l
Figure 26. MODE 0 (Basic Input)
WR
--~-'wD-j
i------tAW--------i
i------'wA----~
CS. Al. AO
OUTPUT
Figure 27. MODE 0 (Basic Output)
7-97
AFN-00744A-19
8255A18255A·5
______________~I------t.T------Ir_--~------------------------------~~----------IBF
INTR
INPUT FROM _ _ _
PERIPHERAL
I-----tps-------I
Figure 28. MODE 1 (Strobed Inut)
INTR
OUTPUT
Figure 29. MODE 1 (Strobed Output)
7·98
AFN-00744A-20
8255A18255A·5
DATA FROM
~ 8080 TO 8255
/
INTR
IBF
PERIPHERAL _ _ _ _ _ _ _ _ _ _
BUS
DATA FROM
PERIPHERAL TO 8255
DATA FROM
8255 TO 8080
Figure 30. MODE 2 (Bidirectional)
NOTE:
Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(INTR = IBF • MASK· STB • RD + OBF • MASK' ACK • WR I
7.00
intel"
ft
'8ft .,..
I . - 6,'8 7"• • 8
ftft.,
O~
I ..II
~
~
PROGRAMMABLE FLOPPY DISK CONTROLLER
• IBM 3740 Soft Sectored Format Compatible
• Programmable Record Lengths
• Multl·Sector Capability
Maintain Dual Drives with Minimum Software
• Overhead
Expandable to 4 Drives
Read/Write Head Positioning and
• Automatic
Verification
• Internal CRC Generation and Checking
Step Rate, Settle· Time, Head
• Programmable
Load Time, Head Unload Index Count
• Fully MCS·SOTM and MCS·SS™ Compatible
• Single + SV Supply
• 40·Pln Package
The Intel~ 8271 Programmable Floppy Disk Controller (FOC) is an LSI component designed to interface one to 4 floppy
disk drives to an 8·bit microcomputer system. Its powerful control functions minimize both hardware and software
overhead normally associated with floppy disk controllers.
BLOCK DIAGRAM
PIN CONfiGURATION
FAULT RESET/OPO
Vee
SELECT 0
lOW CURRENT
4 MHz ClK
lOAD HEAD
RESET
DIRECTION
READY 1
SEEK/STEP
SELECT 1
WR ENBLE
DACK
INDEX
ORO
WR PROTECT
Ri5
READY 0
WR
TRKO
INT
COUNT/UP!
DBO
WR DATA
DBl
FAULT
DB2
UNSE~
DATA
DB3
DATA WINDOW
DB4
PLO/SS
DBS
CS
DB6
INSYNC
DB7
A,
GND
Ao
ORO
DACK
INT
AD
VIR
PIN NAMES
~~-DBo
DATA 8US IBI·DlRECTlONAl)
CLOCk INPUT ITTL)
PLOISS
DATA WINDOW
DATA WINDOW
SELECT 1,0
!~~~CTT~E:ET/OPTIONAl OUTPUT
UNSEPOATA
UNSE'AAA TE 0 DA T A
CHIPAESET
READY 1,0
OM" 4CkNOWLIEDGE
WRDATA
FAUlTR£SET/OPO
RUU
mIW'l .•
~
""Q
Ii!5
iII1I
~~S:NC
~
fAul'T
~
mo
WAPAOTECT
FAULT
WRITE DATA
COUNT/OPTIONAllNPUT
THACkO
WAITEPAOTECT
iNDEX
INDEX
WAITE ENABLE
SEEK/STEP
DIRECTION
SEEK/STEP
LOAD HEAD
lOWCUARENT
INTERNAL
DATA BUS
CPU INTERFACE
7·100
AFN-00223A
8271/8271·6/8271·8
8271 BASIC FUNCTIONAL DESCRIPTION
Pin
Name
General
The 8271 Floppy Disk Controller (FOC) interfaces either
two single or one dual floppy drive to an eight bit
microprocessor and is fully compatible with Intel's
new high performance MCS-85 microcomputer system.
With minimum external circuitry, this innovative controller
supports most standard, commonly-available flexible disk
drives including the mini-floppy.
The 8271 FOC supports a comprehensive soft sectored
format which is IBM 3740 compatible and includes
provision for the designating and handling of bad tracks. It
is a high level controller that relieves the CPU (and used of
many of the control tasks associated with implementing a
floppy disk interface. The FOC supports a variety of high
level instructions which allow the user to store and retrieve
data on a floppy disk without dealing with the low level
details of disk operation.
In addition to the standard read/write commands, a scan
command is supported. The scan command allows the
user program to specify a data pattern and instructs the
FOC to search for that pattern on a track. Any application
that is required to search the disk for information (such as
point of sale price lookup, disk directory search, etc.), may
use the scan command to reduce the CPU overhead. Once
the scan operation is initiated, no CPU intervention is
required.
Hardware Description
A,-Ao
DRQ
.---------Pin
No.
1/0 Description
(22-21)
I
These two lines are CPU Interface Register select lines.
(8)
0
The DMA request signal is used to
request a transfer of data between
the 8271 and memory.
(7)
The DMA acknowledge signal
notifies the 8271 that a DMA cycle
has been granted. For non-DMA
transfers, this signal should be
driven in the manner of a "Chip
Select".
(6)
(2)
0
These lines are used to specify the
selected drive. These lines are set
by the command byte.
Fault Reset/ (1)
OPO
0
The optional fault reset output line
is used to reset an error condition
which is latched by the drive. If
this line is not used for a fault
reset it can be used as an optional
output line. This line is set with
the write special register command.
Write Enable (35)
O· This signal enables the drive write
logic.
Select 1Select a
Seek/Step
(36)
0
This mUlti-function line is used during drive seeks.
Direction
(37)
0
The direction line specifies the
seek direction. A high level on
this pin steps the R/W head
toward the spindle (step-in), a
low level steps the head away
from the spindle (step-outl.
Load Head
(38)
0
The load head line causes the
drive to load the Read/Write head
against the diskette.
Low Current
(39)
0
This line notifies the drive that track
43 or greater is selected.
Ready 1,
Ready a
(5)
(32)
These two lines indicate that the
specified drive is ready.
Fault
(28)
This line is used by the drive to
specify a file unsafe condition.
Count/OPI
(30)
If the optional seek/direction/
count seek mode is selected, the
count pin receives pulses to step
the R/W head to the desired track.
Otherwise, this line can be used
as an optional input.
Write Protect (33)
This signal specifies that the
diskette inserted is write protected.
TRKO
(31)
This signal indicates when the RIW
head is positioned over track zero.
Index
(34)
The index signal gives an indication
of the relative position of the diskette.
PLO/SS
(25)
This pin is used to specify the type
of data separator used. PhaseLocked Oscillator/Single Shot.
Write Data
(29)
The 8271 is packaged in a 40 pin DIP. The following is a
functional description of each pin.
Pin
Name
Pin
No.
Vee
(40)
I/O
Description
+5V supply
GND
(20)
Ground
Clock
(3)
A square wave clock
Reset
(4)
A high signal on the reset input
forces the 8271 to an idle state.
The 8271 remains idle until a command is issued by the CPU. The
output signals of the drive interface are forced inactive (LOW).
Reset must be active for 10 or
more clock cycles.
(24)
The 1/0 Read and 1/0 Write inputs
are enabled by the chip select signal.
DBrDBo (19-12) 1/0 The Data Bus lines are bidirectional, three-state lines (8080 data
bus compatible).
(10)
The Write signal is used to signal
the control logic that a transfer of
data from the data bus to the 8271
is required.
(9)
INT
(11)
The Read signal is used to signal
the control logic that a transfer of
data from the 8271 to the data bus
is required.
0
The interrupt signal indicates that
the 8271 requires service.
7-101
0
Composite write data.
00223A
8271/8271·6/8271·8
Pin
Name
Result Register
Pin
No.
Description
I/O
Unseparated (27)
Data
This input is the unsepar::lted data
and clocks.
Data Window (26)
This is a data window established
by a single-shot or phase-locked
oscillator data separator.
(23)
INSYNC
The Result Register is used to supply the outcome of FOC
command execution (such as a goodlbad completion) to
the CPU. The standard Result byte format is:
oI0
This line is high when 8271 has
attained input data synchronization, by detecting 2 bytes of
zeros followed by an expected
Address Mark. It will stay high
until the end of the ID or data
field.
0
I
lilT L
I I
I0 I
~,"'m""
::::~::::: ~~::
DELETED DATA FOUND
L..-_ _ _ _ _ _ _ _ _ _ NOT USED = 00
CPU Interface Description
This interface minimizes CPU involvement by supporting
a set of high level commands and both DMA and non-OMA
type data transfers and by providing hierarchical status
information regarding the result of command execution.
The CPU utilizes the control interface (see the Block
diagram) to specify the FOC commands and to determine
the result of an executed command. This interface is
supported by five Registers which are addressed by the
CPU via the A1, AQ, RO and WR signals. If an 8080 based
system is used, the RO and WR signals can be driven by
the 8228's IIOR and IIOW signals. The registers are
defined as follows:
Command Register
The CPU loads an appropriate command into the
Command Register which has the following format:
Figure 1. 8271 Block Diagram Showing CPU
Interface Functions
Status Register
Reflects the state of the FOC.
A,
Ao
07
06
05 04
03
02 0,
Do
I 0 I0 I I
I0 I0 I
ill
L..-_ _ _ _ _ COMMAND OPCODE
SURFACE/DRIVE
(SELECT
o.
I I I I0 I0 I
.
I
11
,"OO,"~ "m "o"'~
1 = INTERRUPT REQUEST
1
= RESULT REGISTER
FULL
I = PARAMETER REGISTER FULL
L..--------'---1
L -_ _ _ _ _ _ _ _ _~
Parameter Register
Accepts parameters of commands that require further
description; up to five parameters may be required,
example:
= COMMAND
REGISTER FULL
1 = COMMAND BUSY
Reset Register
Allows the 8271 to be reset by the program. Reset must
be active for 11 or more chip clocks.
INT (Interrupt Line)
A,
Ao
07 06
05 04
03
02 0,
Do
I 0 11 I
' - - - - - - - - EXPECTED PARAMETER
Another element of the control interface is the Interrupt
line (INT). This line is used to signal the CPU that an FOC
operation has been completed. It remains active until the
result register is read.
7-102
00223A
8271/8271·6/8271·8
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ........ 0 °C to 70°C 1
Storage Temperature ............. - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground ................. - 0.5V to + 7V
Power Dissipation .......................... 1 Watt
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS
Vee= + 5.0V ± 5%
8721 and 8271-8: TA= O°C to 70°C; 8271-6: T A = O°C to 50°C
Symbol
Min.
Max.
Unit
Input Low Voltage
-0.5
0.8
V
V IH
Input High Voltage
2.0
(Vee + 0.5)
V
YOLO
Output Low Voltage (Data Bus)
0.45
V
IOL=2.0 rnA
VOLI
Output Low Voltage (Interface Pins)
0.5
V
IOL = 1.6 rnA
VOH
Output High Voltage
IlL
Input Load Current
± 10
loz
Off-State Output Current
lee
Vee Supply Current
V IL
Parameter
2.4
Test Conditions
V
IOH= -220 p.A
p.A
V IN = Vee to OV
± 10
p.A
VOUT= Vee to OV
180
rnA
CAPACITANCE
TA=25°C, Vcc=GND=OV
Min.
Typ.
Test Conditions
Symbol
Parameter
Max.
Unit
CIN
Input Capacitance
10
pF
tc= 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured Pins Returned to GND
NOTE:
1. Ambient temperature under bias for 8271-6 is
o·e to 5o·e.
7_1n~
nn??~A
8271/8271·6/8271·8
A.C. CHARACTERISTICS
Vcc= + 5.0V ± 5%
8271 and 8271·8: TA = ooe to 7o oe; 8271·6: T A:: ooe to 50 0 e
Read Cycle
Symbol
Unit
Test Conditions
tAc
Select Setup to RD
Parameter
Min.
0
Max.
ns
Note 2
tCA
Select Hold from RD
0
ns
Note 2
tRR
RD Pulse Width
250
ns
tAD
Data Delay from Address
250
ns
tRO
Data Delay from RD
150
ns
C L = 150 pF, Note 2
tOF
Output Float Delay
20
100
ns
C L = 20 pF for Minimum;
150 pF for Maximum
toc
DACK Setup to RD
25
tco
DACK Hold from RD
25
tKO
Data Delay from DACK
Note 2
ns
ns
250
ns
Max.
Unit
Write Cycle
Symbol
tAC
Parameter
Min.
Select Setup to WR
0
ns
tCA
Select Hold from WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup to WR
150
ns
two
Data Hold from WR
0
ns
toc
DACK Setup to WR
25
ns
tco
DACK Hold from WR
25
ns
Test Conditions
DMA
Parameter
Symbol
tca
Test Conditions
Request Hold from WR or RD (for Non·Burst Mode)
Other Timing
8271/8271·6
Symbol
Parameter
t RSTW
Reset Pulse Width
tr
Input Signal Rise Time
tf
Input Signal Fall Time
t RSTS
Reset to First IOWR
Min.
Max.
10
8271·8
Min.
10
20
20
2
Unit
Test Conditions
tCY
20 .
20
2
Max.
ns
ns
tCY
tCY
Clock Period
250
500
tCl
Clock Low Period
110
215
ns
tCH
Clock High Period
125
250
ns
tos
Data Window Setup to Unseparated Clock and Data
50
50
ns
tOH
Data Window Hold from Unseparated Clock and Data
0
0
ns
Note 3
NOTES:
1. All timing
measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at O.BV
Output "1" at 2.0V, "0" at 0.8V
2. tAD, tRO, tAC, and tCA are not concurrent ·specs.
3. Standard Floppy: tCY = 250 ns ± 0.4%
Mini-Floppy: tCY = 500 ns ± 0.4%
7·104
00223A
8271/8271·6/8271·8
WAVEFORMS
Read Waveform,
OACK
=>
X
-toc-
I---tco-------=I
)
I
~
-tAC-DATA BUS
1
~
tRO
--- ------------
.
.
tRR
tAD
tKO
1(
I-tcA-1
I-t
OF
- } _______
Write Waveforms
OACK
toc--"
-----:..-
~
-tco-
..
J(
i
I---tAC--' ,-
tww
-tCA-l
\... ,
)(
DATA BUS
)(
I
tow
tw~~
DMA Waveforms
ORQ
__~I
'cc~
r
\_--+-------------------------------
~ORWR ------------------~~
_______________________________________ _
CHIP CLOCK
7-105
·OO223A
827118271·618271·8
WRITE DATA
PW
r--F-·I
PULSE WIDTH PW = tCY ± 30 ns
H (HALF BIT CELL) = 8 tCY
F (FULL BIT CELL) = 16 tCY
*tCY
=
250 ns ± 0.4%
250 ns ±30 ns
2.0 lAS ± 8 ns
4.0 lAS ± 16 ns
**tCY = 500 ns ± 0.4%
500 ns ±30 ns
4.0 lAS ± 16 ns
8.0 lAS ±32 ns
Figure 24. Write Data
READ DATA
*tCY
=
**tCY = 500 ns
250 ns
F = 16 tCY ± 8 tCY
H = 8 tCY ± 4 tCY
Figure 25. Read Data
*STANDARD FLEXIBLE DISK DRIVE TIMING
**MINI·FLOPPY TIMING
7·106
00223A
8271/8271·6/8271·8
UNSEPARATED
DATA
DATA
WINDOW
tDH~Ons-
Figure 26. Single·Shot Data Separator
*DAfA
WINDOW
*DATA WINDOW MAY BE 180 0 OUT OF PHASE
IN PLO DATA SEPARATION MODE.
Figure 27. PLO Data Separator
7-107
00223A
8273, 8273-4, 8273-8
PROGRAMMABLE HOLC/SOLC PROTOCOL
CONTROLLER
• CCITT X.25 Compatible
• H OLC/SDLC Compatible
Full Duplex, Half Duplex, or Loop
• SOLC
Operation
Up to 64K Baud Synchronous
• Transfers
FCS (CRC) Generation and
• Automatic
Checking
Up to 9.6K Baud with On·Board Phase
• Locked
Loop
• Programmable N RZI Encode/ Decode
User Programmable Modem
• Two
Control Ports
Digital Phase Locked Loop Clock
• Recovery
• Minimum CPU Overhead
Fully Compatible with 8048/8080/8085/
• 8088/8086
CPUs
•
Single +5V Supply
The Intel@ 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the ISO/
CCITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high performance
microcomputer systems such as the MCS-88/86™. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the system CPU of the low
level real-time tasks normally associated with controllers.
BLOCK DIAGRAM
PIN CONFIGURATION
REGISTERS
FLAG DET
Vee
T.INT
PB.
CLK
PB3
RESET
IJII2
T.DACK
iiB,
T.DRQ
RfS
R.DACK
PAc
R.DRQ
PAl
T.INT RESULT
COMMAND
R.INT RESULT
TEST MODE
STATUS
RESUL T
PA;
RD
CD
WR
R.INT
rn
DBO
T.D
DBl
DB2
TiC
Axe
DB3
R.D
DB4
32.CLK
DB5
CS
DB6
DPLL
DB7
AI
GND
Ao
DBO-7
T.D
T.C
T.DRO
TxDACK
RxDRO
RxDACK
DPLL
32X CLK
RTS
ps, _,
TxlNT
CTS
RxlNT
CO
AD
ViR
PA 2 _,
Ao
A,
PIN NAMES
RESET
RxD
R;c
080-DB7
~
T.INT
CLK
RESET
~
T.DRQ
Rl5
iiII
R.DACK
R. DRQ
R. INT
AO-Al
l5nt
DATA BUS (8 BITS)
FLAG DETECT
TRANSMITTER INTERRUPT
CLOCK INPUT
RESET
TRANSMITTER DMA ACKNOWLEDGE
TRANSMITTER DMA REQUEST
READ INPUT
WRITE INPUT
RECEIVER OMA ACKNOWLEDGE
RECEIVER OMA REQUEST
RECEIVER INTERRUPT
COMMAND REGISTER SELECT ADDRESS
DIGITAL PHASE LOCKED LOOP
CS
CHIP SELECT
32 TIMES CLOCK
RECEIVER DATA
RECEIVER CLOCK
TRANSMITTER CLOCK
TRANSMITTER DATA
ill
CLEAR TO SEND
ED
CARRIER DETECT
PA2-PAC GP INPUT PORTS
Cs
32.CLK
R.D
R. C
T. C
T.D
CLK
CPU INTERFACE
~-P84 ~~g~::~~6~~~~
Vee
GND
+5 VOLT SUPPL Y
GROUND
7·108
FLAG DEl
MODEM INTERFACE
8273, 8273·4, 8273·8
types of frames; an Information Frame is used to transfer
data, a Supervisory Frame is used for control purposes,
and a Non-sequenced Frame is used for initialization and
control of the secondary stations.
A BRIEF DESCRIPTION OF HDLC/SDLC
PROTOCOLS
General
Frame Characteristics
The High Level Oata Link Control (HOLC) is a standard
communication link protocol established by International
Standards Organization (ISOl. HOLC is the discipline
used to implement ISO X.25 packet switching systems.
The Synchronous Oata Link Control (SOLC) is an IBM
communication link protocol used to implement the
System Network Architecture (SNAl. Both the protocols
are bit oriented, code independent, and ideal for full
duplex communication. Some common applications
include terminal to terminal, terminal to CPU, CPU to
CPU, satellite communication, packet switching and other
high speed data links. In systems which require expensive
cabling and interconnect hardware, any of the two
protocols could be used to simplify interfacing (by going
serial), thereby reducing interconnect hardware costs.
Since both the protocols are speed independent, reducing
interconnect hardware could become an important
application.
Network
In both the HOLC and SOLC line protocols, according to a
pre-assigned hierarchy, a PRIMARY (Control) STATION
controls the overall network (data link) and issues
commands to the SECONOARY (Slave) STATIONS. The
latter comply with instructions and respond by sending
appropriate RESPONSES. Whenever a transmitting
station must end transmission prematurely it sends an
ABORT character. Upon detecting an abort character, a
receiving station ignores the transmission block called a
FRAME. Time fill between frames can be accomplished by
transmitting either continuous frame preambles called
FLAGS or an abort character. A time fill within a frame is
not permitted. Whenever a station receives a string of
more that fifteen consecutive ones, the station goes into
an IDLE state.
An important characteristic of a frame is that its contents are made code transparent by use of a zero bit
insertion and deletion technique. Thus, the user can adopt
any format or code suitable for his system - it may even
be a computer word length or a "memory dump". The
frame is bit oriented that is, bits, not characters in each
field, have specific meanings. The Frame Check
Sequence (FCS) is an error detection scheme similar to
the Cyclic Redundancy Checkword (CRC) widely used in
magnetic disk storage devices. The Command and
Response information frames contain sequence numbers
in the control fields identifying the sent and received
frames. The sequence numbers are used in Error
Recovery Procedures (ERP) and as implicit acknowledgement of frame communication, enhancing the true fullduplex nature of the HOLC/SOLC protocols.
In contrast, BISYNC is basically half-duplex (two way
alternate) because of necessity to transmit immediate
acknowledgement frames. HOLC/SOLC therefore saves
propagation delay times and have a potential of twice the
throughput rate of BISYNC.
It is possible to use HOLC or SOLe over half duplex lines
but there is a corresponding loss in throughput because
both are primarily designed for full-duplex communication. As in any synchronous system, the bit rate is
determined by the clock bits supplied by the modem,
protocols themselves are speed independent.
A byproduct of the use of zero-bit insertion-deletion
technique is the non-return-to-zero invert (NRZI) data
transmission/reception compatibility. The latter allows
HOLC/SOLC protocols to be used with asynchronous
data communication hardware in which the clocks are
derived from the NRZI encoded data.
References
Frames
A single communication element is called a FRAME which
can be used for both Link Control and data transfer
purposes. The elements of a frame are the beginning eight
bit FLAG (F) consisting of one zero, six ones, and a zero,
an eight bit AOORESS FIELO (A), an eight bit CONTROL
FIELO (C), a variable (N-bit) INFORMATION FIELO (I), a
sixteen bit FRAME CHECK SEQUENCE (FCS), and an
eight bit end FLAG (F), having the same bit pattern as the
beginning flag. In HOLC the Address (A) and Control (C)
bytes are extendable. The HOLC and the SOLC use three
OPENING
FLAG (F)
ADDRESS
FIELD (A)
01111110
8 BITS
CONTROL
FIELD (C)
8 BITS
IBM Synchronous Data Link Control General Information, IBM, GA273093-1.
Standard Network Access Protocol Specification, DATAPAC, TransCanada Telephone System CCG111
Recommendation X.25, ISO/CCITT March 2, 1976.
IBM 3650 Retail Store System Loop Interface OEM Information, IBM, GA
27-3098-0
Guidebook to Data Communications, Training Manual, Hewlett-Packard
5955-1715
IBM Introduction to Teleprocessing, IBM, GC 20-8095-02
System Network Architecture, Technical Overview, IBM, GA 27-3102
System Network Architecture Format and ProtocOl, IBM GP. 27-3112
INFORMATION
FIELD (I)
VARIABLE LEN.GTH
(ONL Y IN I FRAMES)
Figure 1. Frame Format
7-109
FRAME CHECK
(FCS)
CLOSING
FLAG (F)
16 BITS
0' , , , '10
SE~UENCE
8273, 8273·4, 8273·8
FUNCTIONAL DESCRIPTION
TxDRQ (6)
a
Requests a transfer of data between memory and the 8273 for a
transmit operation
RxRDQ
a
Requests a transfer of data between the 8273 and memory for a
receive operation.
General
The Intel® 8273 HDlC/SDlC controller IS a microcomputer peripheral device which supports the International
Standards Organization (ISO) High level Data Link
Control (HDlC), and IBM Synchronous Data Link Control
(SDlC) communications protocols. This controller
minimizes CPU software by supporting a comprehensive
frame-level instruction set and by hardware implementation of the low level tasks associated with frame
assembly/disassembly and data integrity. The 8273 can be
used in either synchronous or asynchronous applications.
I n asynchronous applications the data can be programmed to be encoded/decoded in NRZI code. The clock is
derived from the NRZI data using a digital phase locked
loop. Th'e data transparency is achieved by using a zerobit insertion/deletion technique. The frames are automatically checked for errors during reception by verifying the
Frame Check Sequence (FCS); the FCS is automatically
generated and appended before the final flag in transmit.
(8)
TxDACK
(5)
The Transmitter DMA acknowledge Signal notifies the 8273 that
the TxDMA cycle has been
granted.
RxDACK
(7)
The Receiver DMA acknowledge
signal notifies the 8273 that the
RxDMA cycle has been granted.
Al-Aa (22-21)
These two lines are CPU Interface Register Select lines.
a
TxD (29)
This line transmits the serial data
to the communication channel.
The 8273 recognizes and can generate flags (01111110),
Abort, Idle, and GA (EOP) characters.
TxC (28)
The transmitter clock is used to
synchronize the transmit data.
The 8273 can assume either a primary (control) or a
secondary (slave) role. It can therefore be readily
implemented in an SDlC loop configuration as typified by
the IBM 3650 Retail Store System by programming the
8273 into a one-bit delay mode. In such a configuration, a
two wire pair can be effectively used for data transfer
between controllers and loop stations. The digital phase
locked loop output pin can be used by the loop station
without the presence of an accurate Tx clock.
RxD (26)
This line receives serial data from
the communication channel.
RxC
(27)
The Receiver Clock is used to
synchronize the receive data.
32X ClK (25)
The 32X clock is used to provide
clock .recovery when an asynchronous modem is used. In loop
configuration the loop station
can run without an accurate 1X
clock by using the 32X ClK in
conjunction with the DPll output. (This pin must be grounded
when not used).
Hardware Description
The 8273 is packaged in a 40 pin DIP. The following is a
functional description of each pin.
Pin Name (No.)
I/O Description
+5V Supply
Vee (40)
GND (20)
RESET (4)
CS (24)
DBl-DBa (19-12)
WR (10)
Ground
A high signal on this pin will force
the 8273 to an idle state. The 8273
will remain idle until a command
is issued by the CPU. The modem
interface output signals are forced high. Reset must be true for a
minimum of 10 TCY.
The RD and WR inputs are enabled by the chip select input.
I/O The Data Bus lines are bidirectional three-state lines which interface with the system Data Bus.
The Write signal is used to control the transfer of either a command or data from CPU to the
a
DPll (23)
FLAG DET
(1)
a
TxlNT
(2)
RxlNT (11)
a
a
The Read signal is used to control the transfer of either a data
byte or a status word from the
8273 to the CPU.
The Transmitter interrupt signal
indicates that the transmitter
logic requires service.
The Receiver interrupt signal indicates that the Receiver logic requires service.
Flag Detect signals that a flag
(01111110) has been received by
an active receiver.
RTS (35)
a
Request to Send signals that the
8273 is ready to transmit data.
CTS (30l
Clear to Send signals that the
modem is ready to accept data
from the 8273.
CD (31)
Carrier Detect signals that the
line transmission has started and
the 8273 may begin to sample
data on RxD line.
PA2-4 (32-34)
General purpose input ports. The
logic levels on these lines can be
Read by the CPU through the
Data Bus Buffer.
8273.
RD (9)
Digital Phase locked loop output can be tied to RxC and/or
TxC when 1 X clock is not available. DPll is used with 32X ClK.
PBl-4 (36-39)
ClK (3)
7-110
a
General purpose output ports.
The CPU can write these output
lines through Data Bus Buffer.
A square wave TTL clock.
8273, 8273·4, 8273·8
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
AmbientTemperatureUnderBias ........ O°Ct070°C
Storage Temperature ............... -65° C to +150°C
Voltage on Any Pin With
RespecttoGround ..................... -O.5Vto+7V
Power Dissipation ......... . . . . . . . . . . . . . . . . .. 1 Watt
D.C. CHARACTERISTICS (8273, 8273·4, 8273·8)
TA=O°C to 70°C, Vce= +5.0V±5%
Test Conditions
Parameter
Min.
Max.
Unit
V il
Input Low Voltage
-0.5
0.8
V
V IH
Input High Voltage
2.0
Vcc+ 0.5
V
VOL
Output Low Voltage
0.45
V
10l = 2.0 mA for Data Bus Pins
10l = 1.0 mA for Output Port Pins
10l = 1.6 mA for All Other Pins
VOH
Output High Voltage
V
10H = - 200 /-IA for Data Bus Pins
10H = -100/-IA for All Other Pins
III
Input Load Current
±10
/-I A
VIN = Vcc to OV
loz
Off·State Output Current
±10
/-I A
Vour= Vcc to OV
Icc
Vcc Supply Current
180
mA
Symbol
2.4
CAPACITANCE (8273,8273·4,8273·8)
TA=25°C, Vcc=GND=OV
Symbol
Parameter
Max.
Unit
C IN
Input Capacitance
10
pF
tc= 1 MHz
ClIO
I/O Capacitance
20
pF
Unmeasured Pins
Returned to GND
Unit
Test Conditions
Min.
Typ.
Test Conditions
A.C. CHARACTERISTICS
TA=O°C to 70°C, Vcc= +5.0V±5%
Clock Timing (8273)
Parameter
Min.
tCY
Clock
250
ns
tCl
Clock Low
120
ns
tCH
Clock High
120
ns
Symbol
Typ.
Max.
64K Baud Max
Operating Rate
Clock Timing (8273·4)
Parameter
Symbol
Min.
Typ.
Max.
Unit
tCY
Clock
286
ns
tCl
Clock Low
135
ns
tCH
Clock High
135
ns
Test Conditions
56K Baud Max
Operating Rate
Clock Timing (8273·8)
Typ.
Min.
Clock
330
ns
tCl
Clock Low
150
ns
tCH
Clock High
150
ns
7·111
Max.
Unit
Parameter
tCY
Symbol
Test Conditions
48K Baud Max
Operating Rate
8273, 8273·4, 8273·8
A.C. CHARACTERISTICS
(8273,8273-4,8273-8) TA=O°C to 70°C, VCC= +5.0V±5%
Read Cycle
Symbol
I
I
I
r
lalli'
I
M'lin.
Max.
I Iunh
I
I
.65, "onuhions
'&
tAC
Select Setup to RD
tCA
Select Hold from RD
tRR
RD Pulse Width
tAD
Data Delay from Address
300
ns
Note 3
tRD
Data Delay from RD
200
ns
Cl
ns
C l 20 pF for Minimum;
150pF for Maximum
0
ns
Note 3
0
ns
Note 3
250
ns
tOF
Output Float Delay
20
toc
DACK Setup to RD
25
tCD
DACK Hold from RD
25
tKD
Data Delay from DACK
100
= 150pF, Note 3
=
ns
ns
300
ns
Max.
Unit
Write Cycle
Symbol
tAC
Parameter
Select Setup to WR
Min.
0
ns
tCA
Select Hold from WR
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup to WR
150
ns
tWD
Data Hold from WR
0
ns
toc
DACK Setup to WR
25
ns
tCD
DACK Hold from WR
25
ns
Test Conditions
DMA
Symbol
tca
Parameter
Min.
Request Hold from WR or RD
(for Non-Burst Mode)
Max.
Unit
200
ns
Max.
Unit
20
tCY
ns
Test Conditions
Other Timing
Symbol
Parameter
tRSTW
Reset Pulse Width
tr
Input Signal Rise Time
tf
Inr.>ut Signal Fall Time
tRSTS
Reset to First IOWR
Min.
10
20
2
ns
tCY32
32X Clock Cycle Time
9.7' tCY
tCY
ns
tCl32
32X Clock Low Time
4' tCY
ns
ns
tCH32
32X Clock High Time
tOPll
DPLL Output Low
4' tCY
1 . tCY- 50
tOCl
Data Clock,Low
1 . tCY- 50
ns
tOCH
Data Clock High
2· tCY
ns
toCY
Data Clock'
tTD
Transmit Data Delay
tos
Data Setup Time
200
ns
tOH
t FlO
Data Hold Time
100
ns
8· tCY± 50
ns
FLAG DET Output Low
Test Conditions
ns
ns
62.5' tCY
200
ns
NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at 0.8V;
Output "1" at 2.0V, "0" at 0.8V.
2. tAD, tRO, tAC, and tCA are not concurrent specs.
7·112
8273, 8273-4, 8273-8
WAVEFORMS
Read Waveforms
DACK
--
I
~
~~ICO
i---'oc
-
_1~ICA--.:J
'RR
_IAC--
--
~I
)(
).
~
DATA BUS
1<.
~
IRD
~--------lAD
I KO
I---IDF-~
_______
Write Waveforms
DACK
~
I
:;;::;;
AO' A,.
csi
I 0
~
](
~IAC---~-
IWW
I--ICA~
)(
DATA BUS
](
I
IDW
two---J
DMA Waveforms
DRQ
R5
OR
WR
CHIP CLOCK
--II
__
ICO~
r
\~----~-------------------------------
--{L--_ _ __
t tCY =l
L."~.'" ----1--------J1
tCY32
=:1
1
CtCL32=--:CtCH32J-----J
~
32X CLOCK
7-113
00743A
8273,8273-4, 8273-8
Transmit Data Waveforms
j
,r
~~--------------~
- - - - - IDCl
---~----I
-'~
~~----------------1---
k - - - - - - - - - - - - IDCY -------
TxD
\J~
____________~---'A~~----------------------------------J
Receive Data Waveforms
DPLL Output Waveform
Flag Detect Output Waveform
7-114
00743A
8275
PROGRAMMABLE CRT CONTROLLER
Screen and Character
• Programmable
Format
• 6 Independent Visual Field Attributes
Fully MCS·SO™ and MCS·SS™
• Compatible
• Dual Row Buffers
• Programmable DMA Burst Mode
• Single + SV Supply
• 11 Visual Character Attributes
(Graphic Capability)
• Cursor Control (4 Types)
• Light Pen Detection and Registers
• 40·Pln Package
The Intell!> 8275 Programmable CRT Controller is a single chip device to interface CRT raster scan displays with
Intell!> microcomputer systems. Its primary function is to refresh the display by buffering the information from main
memory and keeping track of the display position of the screen. The flexibility designed into the 8275 will allow simple
interface to almost any raster scan CRT display with a minimum of external hardware and software overhead.
BLOCK DIAGRAM
PIN CONFIGURATION
vcc
LAO
LA,
LTEN
RVV
VSP
GPA,
GPAO
HLGT
IRa
CCLK
CC6
CC5
CC4
CC3
CC2
CC,
CCo
LC3
LC2
LC,
LCO
ORO
DACK
HRTC
VRTC
RD
WR
LPEN
DBo
DB,
DB2
DB3
DB4
DB5
DB6
DB7
GND
CCLK
0110-7
ORO _ - - - - - - ,
CCO_6
LCO_3
OACK
IRa
cs
AO
LAo-l
HRTC
VRTC
HLGT
RVV
LTEN
VSP
PIN NAMES
GPAO_l
~;-i- Bl-DIRECTIDNAL DATA BUS
LCO-3
LINE COUNTER OUTPUTS
DRO
LAo-l
LINE ATTRIBUTE OUTPUTS
HORIZONTAL RETRACE OUTPUT
lim
DMA REOUEST OUTPUT
DMA ACKNOWLEDGE INPUT
HRTC
INTERRUPT REOUEST OUTPUT
VRTC
VERTICAL RETRACE OUTPUT
1m
READ STROBE INPUT
HLGT
HIGHLIGHT OUTPUT
WI!
WRITE STROBE INPUT
i-liia--
1-1-=-csAo---+-c-CR=_HE=Glpl=STSE=ELRE=-=CAT=DID=NRPU=ESST=INP:::cU=-T_---tt_-H
RVV
LPEN
REVERSE VIDEO OUTPUT
-:C-=-vspLT~E=N=~~LIG~H~T~EN~AB~L~EO~U~TP~UT~=======:::i
VIDEO SUPPRESS OUTPUT
CCLK
CHARACTER CLOCK INPUT
GPAo-l
,-,-CC",-O_-'06-,-_C,-H_AR_A,,-,-CT-,-ER-,CO-,-DC-'E-,,-OU,,-,-T-,PU,--,TS= _LP_EN___
GENERAL PURPOSE ATTRIBUTE OUTPUTS
LIGHT PEN INPU'-T_ _ _ _ _--'
7-115
00224A
8275
PIN DESCRIPTIONS
Pin :# Pin Name 1/0
1
2
3
4
LC3
LC2
LCl
LCo
0
5
DRQ
0
6
DACK
7
HRTC
Pin Description
Line count. Output from the line counter which is used to address the character
generator for the line positions on the
screen.
o
Horizontal retrace. Output signal which
is active during the programmed horizontal retrace interval. During this period the VSP output is high and the
L TEN output is low.
8
VRTC
9
RD
Read input. A control signal to read
registers.
10
WR
Write input. A control signal to write
commands into the control registers or
write data into the row buffers during a
DMA cycle.
11
LPEN
12
13
14
15
16
17
18
19
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
20
Ground
Vertical retrace. Output signal which is
active during the programmed vertical
retrace interval. During this period the
VSP output is high and the L TEN output is low.
+5V power supply
39
38
LAO
LAl
o
Line attribute codes. These attribute
codes have to be decoded externally by
the dot/timing logic to generate the
horizontal and vertical line combinations
for the graphic displays specified by the
character attribute codes.
37
LTEN
o
Light enable. Output signal used to
enable the video signal to the CRT. This
output is active at the programmed
underline cursor position, and at positions specified by attribute codes.
36
RVV
o
Reverse video. Output signal used to
indicate the CRT circuitry to reverse the
video signal. This output is active at the
cursor position if a revel~e video block
cursor is programmed or at the positions
specified by the field attribute codes.
35
VSP
o
Video suppression. Output signal, ·ed to
blank the video signal to the CRT. This
output is active:
during the horizontal and vertical retrace intervals.
at the top and bottom lines of rows if
underline is programmed to be number
8 or greater.
when an end of row or end of screen
code is detected.
Light pen. Input signal from the CRT
system signifying that a light pen signal
has been detected.
I/O
Pin Description
VCC
DMA request. Output signal to the 8257
DMA controller requesting a DMA cycle.
DMA acknowledge. Input signal from
the 8257 DMA controller acknowledging
that the requested DMA cycle has been
granted.
0
Pln:# Pin Name 1/0
40
When a DMA underrun occurs.
at regular intervals (1/16 frame frequency for cursor, 1/32 frame frequency for character and field attributes) - to create blinking displays
as specified by cursor, character attribute, or field attribute programming.
Bi-directional three-state data bus lines.
The outputs are enabled during a read of
the C or P ports.
34
33
GPAl
GPAo
o
General purpose attribute codes. Outputs which are enabled by the general
purpose field attribute codes.
32
HLGT
o
Highlight. Output signal used to intensify the display at particular positions on
the screen as specified by the character
attribute codes or field attribute codes.
Ground
31
IRQ
o
Interrupt request.
30
CCLK
I
Character clock (from dotltiming logic).
29
28
27
26
25
24
23
CC6
CC5
CC4
CC3
CC2
CCl
CCo
o
Character codes. Output from the row
buffers used for character selection in
the character generator.
22
CS
Chip select. The read and write are enabled by CS.
21
AO
Port address. A high input on AO selects
the "c" port or command registers and a
low input selects the "P" port or parameter registers.
7-116
00224A
8275
FUNCTIONAL DESCRIPTION
Data Bus Buffer
CCLK
This 3-state, bidirectional, 8-bit buffer is used to interface
the 8275 to the system Data Bus.
This functional block accepts inputs from the System Control Bus and generates control signals for overall device
operation. It contains the Command, Parameter, and Status
Registers that store the various control formats for the
device functional definition.
AO
OPERATION
CCO_6
REGISTER
ORO
PREG
OACK
Write
PREG
IRa
Read
SREG
Write
CREG
0
Read
0
1
1
LCO_3
AD
LAo-l
RD (Read)
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO_l
cs
A "Iow" on this input informs the 8275 that the CPU is
reading data or status information from the 8275.
LPEN
WR (Write)
A "Iow" on this input informs the 8275 that the CPU is
writing data or control words to the 8275.
Figure 1. 8275 Block Diagram Showing Data Bus Buffer
.and ReadlWrlte Functions
CS (Chip Select)
A "Iow" on this input selects the 8275. No reading or writing will occur unless the device is selected. When CS is high,
the Data Bus in the float state and RD and WR will have no
effect on the chip.
DRQ (DMA Request)
A "high" on this output informs the DMA Controller that
the 8275 desires a DMA transfer.
Ao
RD
WR
CS
0
0
1
1
0
1
0
1
0
0
0
0
0
0
X
X
1
0
X
X
Write 8275 Parameter
Read 8275 Parameter
Write 8275 Command
Read 8275 Status
Three-State
Three-state
DACK (DMA Acknowledge)
A "Iow" on this input informs the 8275 that a DMA cycle
is in progress.
IRQ (Interrupt Request)
A "high" on this output informs the CPU that the 8275
desires interrupt service.
7-117
00224A
8275
Character Counter
CCLK
The Character Counter is a programmable counter that is
used to determine the number of characters to be displayed
per row and the length of the horizontal retrace interval. It
is driven by the CCLK (Character Clock) input, which
should be a derivative of the external dot clock.
CCO_6
Line Counter
The Line Counter is a programmable counter that is used to
determine the number of horizontal lines (Sweeps) per
character row. Its outputs are used to address the external
character generator ROM.
DRQ _ _ _- - ,
LCO-3
DACK
IRQ
Row Counter
The Row Counter is a programmable counter that is used to
determine the number of character rows to be displayed per
frame and length of the vertical retrace interval.
LAO_l
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO_l
Light Pen Registers
The Light Pen Registers are two registers that store the contents of the character counter and the row counter whenever there is a rising edge on the LPEN (Light Pen) input.
LPEN
Note: Software correction is required.
Figure 2. 8275 Block Diagram Showing Counter and
Register Functions
Raster Timing and Video Controls
The Raster Timing circuitry controls the timing of the
HRTC (Horizontal Retrace) and VRTC (Vertical Retrace)
outputs. The Video Control circuitry controls the generation of LAo_1 (Line Attribute), HGL T (Highlight), RVV
(Reverse Video), LTEN (Light Enable), VSP (Video Suppress), and GPAO-1 (General Purpose Attribute) outputs.
FIFOs
There are two 16 character FIFOs in the 8275. They are
used to provide extra row buffer length in the Transparent
Attribute Mode (see Detailed Operation section).
Buffer Input/Output Controllers
Row Buffers
The Row Buffers are two 80 character
filled from the microcomputer system
character codes to be displayed. While
displaying a row of characters, the other
the next row of characters.
buffers. They are
memory with the
one row buffer is
is being filled with
The Buffer Input/Output Controllers decode the characters
being placed in the row buffers. If the character is a character attribute, field attribute or special code, these controllers control the appropriate action. (Examples; An
"End of Screen-Stop DMA" special code will cause the
Buffer Input Controller to stop further DMA requests. A
"Highlight" field attribute will cause the Buffer Output
Controller to activate the HG i.. T output.)
7-118
00224A
8275
SYSTEM OPERATION
The 8275 is programmable to a large number of different
display formats. It provides raster timing, display row buffering, visual attribute decoding, cursor timing, and light
pen detection.
It is designed to interface with the 8257 DMA Controller
and standard character generator ROMs for dot matrix
decoding. Dot level timing must be provided by external
circuitry.
MEMORIES
U
<
(
SYSTEM BUS
DBO-7
MEMR
AO
DBO-7
WR
lOW
MEMW
lOR
lID
CS
CS
HRQ
HACK
IRQ
LCO-3
DRQ
8257
DMA
CONTROLLER
VIDEO SIGNAL
CHARACTER
GENERATOR
DACK
8275
CRT
CONTROLLER
HORIZONTAL SYNC
CCO-6
CCLK
DOT
TIMING
AND
INTERFACE
VERTICAL SYNC
INTENSITY
VIDEO CONTROLS
Figure 3. 8275 Systems Block Diagram Showing Systems Operation
7-119
00224A
8275
General Systems Operational Description
The 8275 provides a "window" into the microcomputer
system memory.
Display characters are retrieved from memory and dis, played on a row by row basis. The 8275 has two row buffers. While one row buffer is being used for display, the
other is being filled with the next row of characters to be
displayed. The number of display characters per row and
the number of character rows per frame are software programmable, providing easy interface to most CRT displays.
(See Programming Section.)
The 8275 requests DMA to fill the row buffer that is not
being used for display. DMA burst length and spacing is
programmable. (See Programming Section.)
The 8275 displays character rows one line at a time.
1st
Character
2nd
Character
3rd
Character
The number of lines per character row, the underline position, and blanking of top and bottom lines are programmable. (See Programrriing Section.)
The 8275 provides special Control Codes which can be used
to minimize DMA or software overhead. It also provides
Visual Attribute Codes to cause special action or symbols
on the screen without the use of the character generator
(see Visual Attributes Section).
The 8275 also controls raster timing. This is done by generating Horizontal Retrace (H RTC) and Vertical Retrace
(VRTC) signals. The timing of these signals is programmable.
The 8275 can generate a cursor. Cursor location and format
are programmable. (See Programming Section.)
The 8275 has a light pen input and registers. The light pen
input is used to load the registers. Light pen registers can be
read on command. (See Programming Section.)
4th
Character
5th
Character
6th
Character
7t'l
Character
-----------------------------------------------------------..--
00••••000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
First Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00•••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.00.000.00.000.0
Second Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
6th
Character
7th
Character
00••••000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00.0000000000000.000.00.000.00.000.0
Third Line of a Character Row
1st
Character
2nd
Character
3rd
Character
4th
Character
5th
Character
...---
6th
Character
7th
Character
~..---"--"-..
00•••• 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 •• 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0.00.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00 • • • • 0000000000 • • • • 000.000.00.0.0.0
0.0000.00.00.0.00.0000000000000.0.0000.000.00.0.0.0
o.oooo.oo.ooo ••co.ooooooooooooo.oo.ooo.ooo.oo.o.o.o
00••••000.0000.00 • • • • • 000000000.0 O. 0000 • • • 000 O. O. 0 0
Seventh Line of a Character Row
Figure 4. Display of a Character Row
7-120
00224A
8275
Display Row Buffering
After all the lines of the character row are scanned, the
roles of the two row buffers are reversed and the same
procedure is followed for the next row.
Before the start of a frame, the 8275 requests DMA and
one row buffer is filted with characters.
CCLK
CCLK
DBO_7
CCO_6
DATA
DBO_7
_"-E3t"~'-+E>fw
CCO-6
BUFFER
LCO_3
ORO
LCO_3
DACK
IRO
R5
LAO_l
HRTC
VRTC
HLGT
RVV
LTEN
LAO_l
AO--
HRTC
VRTC
HLGT
RVV
LTEN
cs
GPAO_l
vsp
GPAO_l
vsp
LPEN
LPEN
Figure 5. First Row Buffer Filled
When the first horizontal sweep is started, character codes
are output to the character generator from the row buffer
just filled. Simultaneously, DMA begins filling the other
row buffer with the next row of characters.
Figure 7. First Buffer Filled with Third Row,
Second Row Displayed
This is repeated until all of the character rows are displayed.
CCLK
DBO_7
CCO_6
LCO_3
READ/
WRITE/
WRAO--
CO~~~OL d
LOGIC
LAO_l
HRTC
VRTC
HLGT
RVV
LTEN
vsp
GPAO_l
LPEN
Figure 6. Second Buffer Filled, First Row Displayed
7-121
00224A
8275
Display Format
Row Format
Screen Format
The 8275 is designed to hold the line count stable while
outputting the appropriate character codes during each
horizontal sweep. The line count is incremented during
horizontal retrace and the whole row of character codes are
output again during the next sweep. This is continued until
the whole character row is displayed.
The 8275 can be programmed to generate from 1 to 80
characters per row, and from 1 to 64 rows per frame.
The number of lines (horizontal sweeps) per character row
is programmable from 1 to 16.
The output of the line counter can be programmed to be in
one of two modes.
In mode 0, the output of the line counter is the same as the
line number.
123456789 . . . . . . . . . . . . . . 80
2
3
4
In mode 1, the line counter is offset by one from the line
number.
5
Note: In mode 1, while the first line (line number 0) is being displayed, the last count is output by the line counter (see
examples).
6
7
8
9
Line
Number
64
0
1
2
3
4
5
\.
Figure 8. Screen Format
6
7
The 8275 can also be programmed to blank alternate rows.
In this mode, the first row is displayed, the second blanked,
the third displayed, etc. DMA is not requested for the
blanked rows.
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
•
0
0
0
0
0
0
•
0
0
0
0
8
9
0
10
11
12
13
14
15
0
0
•0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•••••••
•
•
•
•
•
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
001 1
0100
0101
01 10
0111
1000
1001
1010
1011
1100
1 101
1110
1111
1111
0000
0001
0010
0011
0100
0101
0110
01 1 1
1000
1001
1010
101 1
1 100
1 101
1110
Figure 10. Example of a 16·Llne Format
Line
Number
123456789 . . . . . . . . . . . . . . . 80
2
3
4
5
0
1
2
3
4
5
0
0
0
0
D.
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
6
0
0
0
0
7
0
0
0
0
8
0
0
0
0
0
0
0
9
0
0
0
0
0
0
0
0
0
0
0
• •
•
•
•
•
•••••
•
•
•
•
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
001 1
0100
0101
0110
0111
1000
1001
1001
0000
0001
0010
0011
0100
0101
01 10
01 1 1
1000
64
Figure 11. Example of a 10·Llne Format
Figure 9. Blank Alternate Rows Mode
Mode 0 is useful for character generators that leave address
zero blank and start at address 1. Mode 1 is useful for character generators which start at address zero.
7-122
00224A
8275
Underline placement is also programmable (from line number 0 to 15). This is independent of the line counter mode.
If the line number of the underline is greater than 7 (line
number MSB = 1). then the top and bottom lines will be
blanked.
Line
Number
a
0
0
0
0
0
[J
0
0
0
1
0
0
0
0
0
0
0
0
2
0
0
0
3
0
0
•
•
•
4
5
6
7
8
9
10
11
0
•
0
0
0
0
0
0
0
0
0
•
o
0
0
0
0
0
0
.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•••••••
•
•
•
•
•
•
•••••••••
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
0011
0100
a1a1
a 11 a
0111
1000
100 1
1010
1011
1011
0000
0001
0010
00 11
0100
0101
0110
011 1
1000
10 01
1010
Top and Bottom
Lines are Blanked
Dot Format
Dot width and character width are dependent upon the
external timing and control circuitry.
Dot level timing circuitry should be designed to accept the
parallel output of the character generator and shift it out
serially at the rate required by the CRT display.
LC
8275
cc
VIDEO
vSP
Figure 14. Typical Dot Level Block Diagram
Figure 12. Underline In Line Number 10
If the line number of the underline is less than or equal to 7
(line number MSB = 0). then the top and bottom lines will
not be blanked.
Dot width is a function of dot clock frequency.
Character width is a function of the character generator
width.
Horizontal character spacing is a function of the shift
register length.
Note: Video control and timing signals must be synchronized with
the video signal due to the character generator access delay.
Line
Number
0
1
2
3
4
5
6
7
0
0
0
0
0
•
•
0
0
0
0
•
0
0
•
•
•
•
•••••
•
•
•
•
•••••••
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Line
Counter
Mode 0
Line
Counter
Mode 1
0000
0001
0010
0011
0100
a 10 1
0110
0111
0111
0000
0001
0010
00 11
0100
a1a1
0110
Top and Bottom
Lines are not Blanked
Figure 13. Underline In Line Number 7
If the line number of the underline is greater than the maximum number of lines, the underline will not appear.
Blanking is accomplished by the VSP (Video Suppression)
signal. Underline is accomplished by the LTEN (Light
Enable) signal.
7-123
00224A
8275
Raster Timing
The character counter is driven by the character clock input
(CCLKI. !t counts out the characters being displayed
(programmable from 1 to 80). It then causes the line
counter to increment, and it 'starts counting out the horizontal retrace interval (programmable from 2 to 32). This
is constantly repeated.
The row counter is an internal counter driven by the line
counter. It controls the functions of the row buffers and
counts the number of character rows displayed.
.
ONE CHARACTER ROW
r
HRTC
----U--UU-U-
'''~''"~
INTERNAL
ROW COUNTER
CCLK
\
PROGRAMMXBLE 1 TO 16
LINE COUNTS
Figure 16. Row Timing
HRTC
PROGRAMMABLE 1 TO 80 CCLKS
LC0-3
______________________
J
PRESENT LINE COUNT
NEXT
LINE COUNT
After the row counter counts all of the rows in a frame
(programmable from 1 to 64), it starts counting out the
vertical retrace interval (programmable from 1 to 4).
Figure 15. Line Timing
ONE FRAME
4
"OW'~:;::''':i Jcx::><::x::x:2(:x:X:::x=
FIRST
DISPLAY
ROW
The line counter is driven by the character counter. It is
used to generate the line address outputs (LC _ ) for the
o
character generator. After it counts all of the lines in a
character row (programmable from 1 to 16), it increments
the row counter, and starts over again. (See Character For·
mat Section for detailed description of Line Counter
functions.)
LAST
DISPLAY
ROW
•
PROGRAMMABLE
1 TO 64 ROW COUNTS
FIRST
LAST
RETRACE RETRACE
ROW
ROW
•
PROGRAMMABLE
1 TO 4 ROW COUNTS
Figure 17. Frame Timing
The Video Suppression Output (VSP) is active during
horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize these outputs
with the video signal to the CRT Display.
7-124
00224A
8275
DMATlming
Interrupt Timing
The 8275 can be programmed to request burst DMA transfers of 1 to 8 characters. The interval between bursts is also
programmable (from 0 to 55 character clock periods ±1).
This allows the user to tailor his DMA overhead to fit his
system needs.
The 8275 can be programmed to generate an interrupt
request at the end of each frame. This can be used to
reinitialize the DMA controller. If the 8275 interrupt
enable flag is set, an interrupt request will occur at the
beginning of the last display row.
The first DMA request of the frame occurs one row time
before the end of vertical retrace. DMA requests continue
as programmed, until the row buffer is filled. If the row
buffer is filled in the middle of a burst, the 8275 terminates
the burst and resets the burst counter. No more DMA
requests will occur until the beginning of the next row.
At that time, DMA requests are activated as programmed
until the other buffer is filled.
INTERNAL~
ROW
COUNTER
L
I
DISPLAY RETRACE
ROW
ROW
VRTC
The first DMA request for a row will start at the first character clock of the preceding row. If the burst mode is used,
the first DMA request may occur a number of character
clocks later. This number is equal to the programmed burst
space.
~'r---e--..1
IRQ
Figure 19. Beginning of Interrupt Request
If, for any reason, there is a DMA underrun, a flag in the
status word will be set.
I RQ will go inactive after the status register is read.
INTERNAL
ROW
COUNTER
_----J
"Q
BUR~/
RD~~}-
-..---~ffi
;~
""'a:
:~
g~
~
g
..
ct
~:Ro~
NEXT
ROW BUFFER
FILLED
<~ ....
gC~
«
Q
--a:: 0
~~
}
a:
0..
Figure 20. End of Interrupt Request
ONE
ROW BUFFER
FILLED
Figure 18. DMA Timing
A reset command will also cause IRQ to go inactive, but
this is not recommended during normal service.
Another method of reinitializing the DMA controller is to
have the DMA controller itself interrupt on terminal count.
With this method, the 8275 interrupt enable flag should not
be set.
The DMA controller is typically initialized for the next
frame at the end of the current frame.
Note: Upon power-up, the 8275 Interrupt Enable Flag may be set.
As a result, the user's cold start routine should write a reset
command to the 8275 before system interrupts are enabled.
7-125
00224A
8275
Character Attribute Code.
VISUAL ATTRIBUTES AND SPECIAL
CODES
Character attribute codes are codes that can be used to geneiate Qiaphics symbols without the USe of a character
generator. This is accomplished by selectively activating the
Line Attribute outputs (LAo-11. the Video Suppression
output (VSP), and the Light Enable output. The dot level
timing circuitry can use these signals to generate the proper
svmbols.
The characters processed by the 8275 are 8-bit· quantities.
The character code outputs provide the character generator
with 7 bits of address. The Most Significant Bit is the extra
bit and it is used to determine if it is a normal display
character (MSB = 0), or if it is a Visual Attribute or Special
Code (MSB = 1).
Character attributes can be programmed to blink or be
highlighted individually. Blinking is accomplished with the
Video Suppression output (VSP). Blink frequency is equal
to the screen refresh frequency divided by 32. Highlighting
is accomplished by activating the Highlight output (HGLT).
There are two types of Visual Attribute Codes. They are
Character Attributes and Field Attributes.
Character Attributes
MSB
LSB
11CCCCBH
I
IL
L _____
OO~------------~~
HIGHLIGHT
BLINK
CHARACTER ATTRIBUTE CODE
__~________~
O,~--------+---r-~
__~________~
02~--------+---r-~__~--------~
CHARACTER
GENERATOR
~?,~ OJ~--------+---~~__~==~==~~r=J
SHIFT
REGISTER
05.1----------+---r\-__~--+_____I--__I
8275
06~---------+---.,----).___+_--_+_--_+_-_I......JI
HORIZ. LEFT HALF
LA,
VIDEO
LAO
VSP
LTEN
t---------------- HIGHLIGHT
HGLT
Figure 21. Typical Character Attribute Logic
7-126
00224A
8275
Character attributes were designed to produce the following graphics:
DESCRIPTION
0000
Top Left Corner
0001
Top Right Corner
0010
Bottom Left Corner
0011
Bottom Right Corner
0100
Top Intersect
0101
Right Intersect
0110
Left Intersect
0111
Bottom Intersect
1000
Horizontal Line
1001
Vertical Line
1010
Crossed Lines
1011
Not Recommended *
1100
Special Codes
1101
Illegal
1110
Illegal
1111
Illegal
*Character Attribute Code 1011 is not recommended for
normal operation. Since none of the attribute outputs are
active, the character Generator will not be disabled, and
an indeterminate character will be generated.
Character Attribute Codes 1101, 1110, and 1111 are illegal.
Blinking is active when B = 1.
Highlight is active when H = 1.
7-127
00224A
8275
Specla. Code.
Four special codes are available to help reduce memory,
software, or DMA overhead.
character following the code up to, and including, the
character which precedes the next field attribute code, or
up to the end of the frame. The field attributes are reset
during the vertical retrace interval.
Specla. Control Character
MSB
1 1 1
o
LSB
There are six field attributes:
1.
Blink - Characters following the code are caused
to blink by activating the Video Suppression output (VSP). The blink frequency is equal to the
screen refresh frequency divided by 32.
2.
Highlight - Characters following the code are
caused to be highlighted by activating the Highlight output (HG LT).
3.
Reverse Video - Characters following the code are
caused to appear with reverse video by activating
the Reverse Video output (RVV).
The End of Row Code (00) activates VSP and holds it to
the end of the line.
4.
The End of Row-Stop DMA Code (01) causes the DMA
Control Logic to stop DMA for the rest of the row when it
is written into the Row Buffer. It affects the display in the
same way as the End of Row Code (00).
Underline - Characters following the code are
caused to be underlined by activating the Light
Enable output (L TEN).
5,6.
1
S S
o
o
0
0 S S
~SPECIAL CONTROL CODE
FUNCTION
End of Row
End of Row-Stop DMA
o
End of Screen
End of Screen-Stop DMA
The End of Screen Code (10) activates VSP and holds it to
the end of the frame.
The End of Screen-Stop DMA Code (11) causes the DMA
Control Logic to stop DMA for the rest of the frame when
it is written into the Row Buffer. It affects the display in
the same way as the End of Screen Code (10).
Field Attribute Code
MSB
1 0
If the Stop DMA feature is not used, all characters after an
End of Row character are ignored, except for the End of
Screen character, which operates normally. All characters
after an End of Screen character are ignored.
Field Attribute.
LSB
U R G G B H
II
T. . _'__
L
__
- ~~~~~IGHT
-
L..-_ _ _ _ _ _ _
H
B
R
U
GG
Note: If a Stop DMA character is not the last character in a burst or
row, DMA is not stopped until after the next character is
read. In this situation, a dummy character must be placed in
memory after the Stop DMA character.
The field attributes are control codes which affect the
visual characteristics for a field of characters, starting at the
General Purpose - There are two additional 8275
outputs which act as general purpose, independently programmable field attributes. GPAO-t are
active high outputs.
GENERAL PURPOSE
REVERSE VIDEO
UNDERLINE
= 1 FOR HIGHLIGHTING
= 1 FOR BLINKING
= t FOR REVERSE VIDEO
= t FOR UNDERLINE
= GPA1, GPAo
*More than one attribute can be enabled at the same time.
If the blinking and reverse video attributes are enabled
simultaneously, only the reversed characters will blink.
7-128
00224A
8275
The 8275 can be programmed to provide visible or invisible
field attribute characters.
Each row buffer has a correspond ing FIFO. These F IFOs
are 16 characters by 7 bits in size.
If the 8275 is programmed in the visible field attribute
mode, all field attributes will occupy a position on the
screen. They will appear as blanks caused by activation of
the Video Suppression output (VSP). The chosen visual
attributes are activated after this blanked character.
When a field attribute is placed in the row buffer during
DMA, the buffer input controller recognizes it and places
the next character in the proper FIFO.
ABC 0 E
F G H I J K L M
NOPORSTUV
1 2 3 4 5
6 7 8 9
,'---------------------------------~
When a field attribute is placed in the Buffer Output Controller during display, it causes the controller to immediately put a character from the FIFO on the Character Code
outputs (CCO-6). The chosen Visual Attributes are also
activated.
Since the FIFO is 16 characters long, no more than 16 field
attribute characters may be used per line in this mode.
If more are used, a bit in the status word is set and the first
characters in the FIFO are written over and lost.
Note: Since the FIFO is 7 bits wide, the MSB of any characters put
in it are stripped off. Therefore, a Visual Attribute or Special
Code must not immediately follow a field attribute code. If
this situation does occur, the Visual Attribute or Special
Code wili be treated as a normal display character.
Figure 22. Example of the Visible Field Attribute Mode
(Underline Attribute)
If the 8275 is programmed in the invisible field attribute
mode, the 8275 FIFO is activated.
ABC 0 E F G H I J K L M
NOPORSTUV
1 234 5 6 7 8 9
I
Figure 24. Example of the Invisible Field Attribute
Mode (Underline Attribute)
Field and Character Attribute Interaction
Character Attribute Symbols are affected by the Reverse
Video (RVV) and General Purpose (GPAO-1) field attributes. They are not affected by Underline, Blink or Highlight field attributes; however, these characteristics can be
programmed individually for Character Attribute Symbols.
Figure 23. Block Diagram Showing FIFO Activation
7·129
00224A
8275
Cursor Timing
Device Programming
The cursor location is determined by a cursor row register
and a charactP.r position register which are loaded by command to the controller. The cursor can be programmed to
appear on the display as:
The 8275 has two programming registers, the Command
1.
2.
3.
4.
a
a
a
a
blinking underline
blinking reverse video block
non-blinking underline
non-blinking reverse video block
Register (CREG) and the Paiametei Register (PREG). It
also has a Status Register (SREG). The Command Register
can only be written into and the Status Registers can only
be read from. They are addressed as follows:
AO
The cursor blinking frequency is equal to the screen refresh
frequency divided by 16.
If a non-blinking reverse video cursor appears in a nonblinking reverse video field, the cursor will appear as a
normal video block.
If a non-blinking underline cursor appears in a non-blinking
underline field, the cursor will not be visible.
Light Pen Detection
A light pen consists of a micro switch and a tiny light
sensor. When the light pen is pressed against the CRT screen,
the micro switch enables the light sensor. When the raster
sweep reaches the light sensor, it triggers the light pen
output.
REGISTER
Read
PREG
0
Write
PREG
1
Read
SREG
1
Write
CREG
The 8275 expects to receive a command and a sequence
of 0 to 4 parameters, depending on the command. If the
proper number of parameter bytes are not received before
another command is given, a status flag is set, indicating an
improper comm·and.
Instruction Set
The 8275 instruction set consists of 8 commands.
COMMAND
Reset
Start Display
Stop Display
Read Light Pen
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
If the output of the light pen is presented to the 8275
LPEN input, the row and character position coordinates are
stored in a pair of registers. These registers can be read on
command. A bit in the status word is set, indicating that
the light pen signal was detected. The LPEN input must be
a 0 to 1 transition for proper operation.
Note: Due to internal and external delays, the character position
coordinate will be off by at least three character positions.
This has to be corrected in software.
OPERATION
0
NO. OF PARAMETER BYTES
4
o
o
2
2
o
o
o
In addition, the status of the 8275 (SREG) can be read by
the CPU at any time.
7-130
00224A
8275
1.
Reset Command:
Parameter - UUUU
DATA BUS
OPERATION AO
DESCRIPTION
MSB
lSB
U U U U
0 0 0 0
0 0 0 1
0 0
0
Write
1
Write
0
Write
0
Screen Comp
Byte 2
V V R R R R R R
Write
0
Screen Comp
Byte 3
U
U
0
Screen Comp
Byte 4
M
F C C Z Z Z Z
Command
Reset Command
Screen Comp
Byte 1
Parameters
Write
0
0
0 0
0
0
0
0
S H
H H
H
H
H
H
U
U
l
l
l
1
Parameter L
1
LLLL
L
L
L
000 0
000
000
As parameters are written, the screen composition is
defined.
FUNCTIONS
o
Normal Rows
Spaced Rows
1
1
Parameter - M
Parameter - HHHHHHH
Horizontal Characters/Row
H H H H H H H
16
Number of Lines per Character Row
NO. OF LINES/ROW
1
2
3
1
Line Counter Mode
o
Mode 0 (Non-Offset)
Mode 1 (Offset by 1 Count)
2
Parameter - F
3
Field Attribute Mode
FIELD ATTRIBUTE MODE
o
0 0
0
0 0
1 1 1
1
Parameter - VV
V V
1
Transparent
Non-Transparent
80
0 0
1
16
LINE COUNTER MODE
F
Undefined
1
Parameter - CC
C C
Undefined
o
o
0
1
Cursor Format
CURSOR FORMAT
Blinking reverse video block
Blinking underline
Nonblinking reverse video block
Nonblinking underling
o
Vertical Retrace Row Count
NO. OF ROW COUNTS PER VRTC
0
1
1
2
3
o
Parameter - ZZZZ Horizontal Retrace Count
4
Z Z Z Z
Parameter - RRRRRR
0 0 0 0
0 0 0 1
0 0
0
Vertical Rows/Frame
R R R R R R
NO. OF ROWS/FRAME
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0
0
1
2
3
1
1
3
M
NO. OF CHARACTERS
PER ROW
0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
0
1
1
2
Spaced Rows
S
o
o
LINE NUMBER OF
UNDERLINE
l
Action - After the reset command is written, DMA requests stop, 8275 interrupts are disabled, and the VSP
output is used to blank the screen. HRTC and VRTC continue to run. HRTC and VRTC timing are random on
power-up.
Parameter - S
Underline Placement
1
1
1
1
1
1
NO. OF CHARACTER
COUNTS PER HRTC
2
4
6
32
Note: uuuu MSB determines blanking of top and bottom lines
(1 = blanked, 0 = not blanked!'
64
7-131
00224A
8275
2.
Start Display Command:
I I
I
OPERATION AO
DESCRIPTION
I
DATA BUS
MSB
o
Command
0
LSB
1 S
S
S
B B
BURST SPACE CODE
SSS
0 0 0
0 0 1
0
0
0 1 1
0 0
0 1
0
5.
Load Cursor Position:
DATA BUS
IOPERAT!ON I AO I DESCRIPTION I MSB
Command
Write
1
Load Cursor
10000000
Parameters
Write
Write
o
o
Char. Number
Row Number
(Char. Position in Row)
(Row Numbed
Action - The 8275 is conditioned to place the next two
parameter bytes into the cursor position registers. Status
flags not affected.
NQ OF CHARACTER CLOCKS
BETWEEN DMA REQUESTS
S S S
I
0
7
15
23
31
39
6.
Enable Interrupt Command:
DATA BUS
IOPERATION AO
47
Command
55
J
Write
1
DESCRIPTION
MSB
Enable Interrupt
1
0
LSB
1 0
0
0 0
0
No parameters
BB
B B
BURST COUNT CODE
Action - The interrupt enable status flag is set and interrupts are enabled.
NO. OF DMA CYCLES PER
BURST
0 0
0 1
0
2
4
8
7.
Action - 8275 interrupts are enabled, DMA requests begin,
video is enabled, Interrupt Enable and Video Enable status
flags are set.
3.
Disable Interrupt Command:
I
DATA BUS
OPERATION AO
Command
Stop Display Command:
I
Write
1
DESCRIPTION
MSB
Disable Interrupt 1
1
LSB
0 0
0
0 0
0
No parameters
DATA BUS
IOPERATION AO
Commandl
Write
1
DESCRIPTION
Stop Display
MSB
0
1
LSB
000 0
0
0
Action - Interrupts are disabled and the interrupt enable
status flag is reset.
No parameters
Action - Disables video, interrupts remain enabled, HRTC
and VRTC continue to run, Video Enable status flag is
reset, and the "Start Display" command must be given to
re-enable the display.
8.
Preset Counters Command:
DATA BUS
4.
Read Light Pen Command
DATA BUS
OPERATION AO
DESCRIPTION
MSB
LSB
Command
Write
1
Read Light Pen
0
Parameters
Read
Read
0
0
Char. Number
Row Number
(Char. Position in Row)
(Row Number)
1
1 0
0
0
0
DESCRIPTION
MSB
I
Preset Counters
1
Write
1
1
LSB
1 0 0
0
0 0
No parameters
0
Action - The 8275 is conditioned to supply the contents
of the light pen position registers in the next two read
cycles of the parameter register. Status flags are not affected.
Nota: Software correction of light pen position is required.
Command
jOPERATION AO
Action - The internal timing counters are preset, corresponding to a screen display position at the top left corner.
Two character clocks are required for this operation. The
counters will remain in this state until any other command
is given.
This command is useful for system debug and synchronization of clustered CRT displays on a single CPU.
7·132
00224A
8275
Status Flags
IC
DATA BUS
MSB
OlE IR LP ICVE
Command
IE
-
(Improper Command) This flag is set when a
command parameter string is too long or too
short. The flag is automatically reset after a
status read.
(Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
LSB
au
FO
-
(lntp.rrupt Enable) Set or reset by command. It
enables vertical retrace interrupt. It is automatically set by a "Start Display" command
and reset with the "Reset" command.
VE -
IR -
(Interrupt Request) This flag is set at the beginning of display of the last row of the frame if
the interrupt enable flag is set. It is reset after
a status read operation.
DU -
(DMA Underrun) This flag is set whenever a
data underrun occurs during DMA transfers.
Upon detection of DU, the DMA operation is
stopped and the screen is blanked until after
the vertical retrace interval. This flag is reset
after a status read.
FO - (FIFO Overrun) This flag is set whenever the
FIFO is overrun. It is reset on a status read.
LP - This flag is set when the light pen input (LPEN)
is activated and the light pen registers have been
loaded. This flag is automatically reset after a
status read.
7-133
00224A
8275
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... OOC to 70°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground ............ -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
D.C. CHARACTERISTICS
T A = O°C to 70°C; Vee = 5V ±5%
SYMBOL
MIN.
MAX.
UNITS
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+ 0. 5V
V
VOL
Output Low Voltage
0.45
V
IOL = 2.2 mA
VOH
Output High Voltage
V
IlL
Input Load Current
±10
IOFL
Output Float Leakage
±10
~A
= -400~A
VIN = Vee to OV
VOUT = Vee to OV
lee
Vee Supply Current
160
mA
VIL
PARAMETER
2.4
~A
TEST CONDITIONS
IOH
CAPACITANCE
T A = 25°C; Vee = GND = OV
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
CIN
Input Capacitance
10
pF
fc= 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss.
7-134
TEST CONDITIONS
00224A
8275
Other Timing:
SYMBOL
tcc
tHA
tLC
tAT
tVA
tAl
twa
tAQ
tLA
tAL
tpA
tpH
PARAMETER
MIN.
Character Code Output Delay
Horizontal Retrace Output Delay
Line Count Output Delay
Control/Attribute Output Delay
Vertical Retrace Output Delay
IRO~ from ROt
DROt from WRt
DRO~ from WR~
DACK~ to WR~
WRt to DACKt
LPEN Rise
LPEN Hold
MAX.
UNITS
150
200
400
275
275
250
250
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
50
100
TEST CONDITIONS
CL =
CL =
CL =
CL =
CL =
CL =
CL =
CL =
50
50
50
50
50
50
50
50
pF
pF
pF
pF
pF
pF
pF
pF
Note: Timing measurements are made at the following reference voltages: Output "1" = 2.0V, "0" = O.BV.
Input "1 "=2.4V , "0"=0.45V
WAVEFORMS
EXT OOTCLK
CCLK'
l . .______. .
CCo-s
FIRST CHARACTER CODE
SECOND CHARACTER CODE
r------------'"""'"\ ,----------
CHARACTER - - - - - - - - " " ' "
GENERATOR.
FIRST CHARACTER
SECOND CHARACTER
OUTPUT _ _ _ _ _ _ _ _J
.... _ _ _ _ _ _ _ _ _ _ _ _.....J ......._ _ _ _ _ _ _ __
ATTRIBUTES
& CONTROLS
VIDEO
(FROM SHIFT
REGISTER)
ATTRIBUTES
& CONTROLS
(FROM
SYNCHRONIZER)
FIRST CHARACTE,R
SECOND CHARACTER
ATTRIBUTES & CONTROLS FOR FIRST CHAR.
ATTRIBUTES & CONTROLS
FOR 2ND CHAR.
'CCLK IS A MULTIPLE OF THE DOT CLOCK AND AN INPUT TO THE 8215.
Figure 25. Typical Dot Level Timing
7-135
00224A
8275
~
CCLK
r r
I '
I
n
CCO-6
HRTC
~l-tLC
-+-____P_RE_S_EN_T_L_IN_E_C_O_U_N_T_ _---I, 'r---------------.....~
LCO-3
NEXT LINE COUNT
VIDEO
CONTROLS
AND ATTRIBUTES'
'LAO_l' VSP, LTEN, HGLT, RVV, GPAO-l
Figure 26. Line Timing
CCLK
HRTC
LCO_3
f+----PROGRAMMABLE FROM 1 TO 16 LlNES----.\
INTERNAL - - - ' " ' " ' \
ROW _ _ _ _ _
COUNTER
Jr-----------.. . . \------"'"
I'-_ _ _PRESENT
_ _ _ROW
____
~
,.._ _ _ _ _.1
Figure 27. Row Timing
CCLK
~
AST
INTERNAL
ROW
COUNTER
RETRACE
ROW
VRTC
Figure 28. Frame Timing
7-136
00224A
8275
\
CCLK
CCO_&
LAST RETRACE
CHARACTER
IX
FIRST RETRACE
CHARACTER
-----+' '-----
FIRST LINE COUNT
LCO_3
HRTC
IRQ
INTERNAL
-:
------LAS-~-T-D-IS+-PL-A-f-'-OW-~t-I-R--~-_-_-_-_-_-
Figure 29. Interrupt Timing
CCLK
-JtKQt----..
DRQJ
\\,._ __
j ..}"'---_
LPEN _ _
••
Figure 30. DMA Timing
7-137
00224A
8275
A.C. CHARACTERISTICS
T A = O°C to 70°C; VCC = 5.0V ±5%; GND = OV
Bus Parameters (Note 1)
Read Cycle:
SYMBOL
PARAMETER
Address Stable Before READ
tAR
tRA
MIN.
0
0
250
Address Hold Time for READ
READ Pulse Width
Data Delay from READ
READ to Data Floating
tRR
tRO
tOF
MAX.
UNITS
ns
TEST CONDITIONS
ns
ns
200
100
ns
ns
MAX.
UNITS
20
CL=150pF
Write Cycle:
SYMBOL
PARAMETER
MIN.
Address Stable Before WR ITE
Address Hold Time for WR ITE
WR ITE Pulse Width
Data Setup Time for WR ITE
Data Hold Time for WR ITE
tAW
tWA
tww
tow
two
TEST CONDITIONS
ns
ns
ns
ns
ns
0
0
250
150
0
Clock Timing:
SYMBOL
tCLK
tKH
tKL
tKR
tKF
PARAMETER
Clock
Clock
Clock
Clock
Clock
MIN.
Period
High
Low
Rise
Fall
MAX.
UNITS
30
30
ns
ns
ns
ns
ns
480
240
160
5
5
Note 1: AC timings measured at VOH = 2.0, VOL = 0.8
Write Timing
V
1H
TEST CONDITIONS
=2.4, V1L=0.45
Read Timing
Ao.CS
INVALID
-Jt__
V_ALID_ _
---=:rtAR
RD
INVALID
Clock Timing
Input Waveforms (For A.C. Tests)
CCLK
2.4
0.45
7-138
=:x:::>
TEST POINTS
:x==
<:.
00224A
inter
8279/8279·5
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
• MCS·85™ Compatible 8279·5
• Dual 8· or 16·Numerical Display
• Simultaneous Keyboard Display
Operations
• Single 16·Character Display
• Right or Left Entry 16·Byte Display
RAM
• Scanned Keyboard Mode
• Scanned Sensor Mode
• Strobed Input Entry Mode
• Mode Programmable from CPU
• 8·Character Keyboard FI FO
• Programmable Scan Timing
• 2·Key Lockout or N·Key Rollover with
Contact Debounce
• Interrupt Output on Key Entry
The Intel@ 8279 is a general purpose programmable keyboard and display I/O interface deyice designed for use with
Intel@ microprocessors. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The
keyboard portion will also interface to an array of sensors or a strobed interface keyboard, such as the hall effect and
ferrite variety. Key depressions can be 2-key lockout or N-key rollover. Keyboard entries are debounced and strobed in
an 8-character FIFO. If more than 8 characters are entered, overrun status is set. Key entries set the interrupt output
line to the CPU.
The display portion provides a scanned display interface for LED, incandescent, and other popular display
technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279
has 16X8 display RAM which can be organized into dual 16X4. The RAM can be loaded or interrogated by the CPU. Both
right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM
can be done with auto-increment of the display RAM address.
PIN CONFIGURATION
LOGIC SYMBOL
PIN NAMES
IRQ
DATA
BUS
SHIFT
1---- - KEY DATA
RD
WR
CNTL'STB
CPU
INTERFACE
OUT B,
CS
OUTB2 -
SLO_3
SCAN
OUT B3
OUT Ao
AO
OUT A,
qUT
l-
OUT AO-3
I
A2
OUT A3
BD
cs
RESET
CLK
Vss
7_1~Q
OUT B()'3
DISPLAY
DATA
8279/8279·5
HARDWARE DESCRIPTION
SHIFT
The 8279 is packaged in a 40 pin DIP. The following is
a functional description of each pin.
No. Of
Pins
Designation
Function
8
DBo-DB7
ClK
RESET
Ao
2
IRO
Bi-directional data bus. All data
and commands between the
CPU and the 8279 are transmitted on these lines.
Clock from system used to generate internal timing.
A high signal on this pin resets
the 8279. After being reset the
8279 is placed in the following
mode:
1) 16 8-bit character display
-left entry.
2) Encoded scan keyboard-2
key lockout.
Along with this the program
clock prescaler is set to 31.
Chip Select. A low on this pin
enables the interface functions
to receive or transmit.
Buffer Address. A high on this
line indicates the signals in or
out are interpreted as a command or status. A low indicates
that they are data.
I nput/Output read and write.
These signals enable the data
buffers to either send data to
the external bus or receive it
from the external bus.
Interrupt Request. In a keyboard
mode, the interrupt line is high
when there is data in the FIFO/
Sensor RAM. The interrupt line
goes low with each FIFO/
Sensor RAM read and returns
high if there is still information in the RAM. In a sensor
mode, the interrupt line goes
high whenever a change in a
sensor is detected.
2
Vss , Vee
Ground and power supply pins.
4
Slo-Sl3
Scan Lines which are used to
scan the key switch or sensor
matrix and the display digits.
These lines can be either encoded (1 of 16) or decoded (1 of
4).
Rlo-Rl7
Return line inputs which are
connected to the scan lines
through the keys or sensor
switches. They have active internal pull ups to keep them
high until a switch closure pulls
one low. They also serve as an
8-bit input in the Strobed Input
mode.
8
No. Of
Pins
The shift input status is stored
along with the key position on
key closure in the Scanned
Designation Function
Keyboard modes. It has an active internal pullup to keep it
high until a switch closure pulls
it low.
CNTLlSTB
For keyboard modes this line is
used as a control input and
stored like status on a key closure. The line is also the strobe
line that enters the data into the
FIFO in the Strobed Input mode.
(Rising Edge). It has an active
internal pullup to keep it high
until a switch closure pulls it
low.
4
4
OUT Ao-OUT A3 These two ports are the outputs
OUT Bo-OUT B3 for the 16 x 4 display refresh
registers. The data from these
outputs is synchronized to the
scan lines (Slo-Sl3) for multiplexed digit displays. The two 4
bit ports may be blanked independently. These two ports may
also be considered as one 8 bit
port.
BD
Blank Display. This output is
used to blank the display during
digit switching or by a display
blanking command.
PRINCIPLES OF OPERATION
The following is a description of the major elements of the
8279 Programmable Keyboard/Display interface device.
Refer to the block diagram in Figure 1.
110 Control and Data Buffers
The I/O control section uses the CS, Ao, RD and WR lines
to control data flow to and from the various internal
registers and buffers. All data flow to and from the 8279 is
enabled by CS. The character of the information, given or
desired by the CPU, is identified by Ao. A logic one
means the information is a command or status. A logic
zero means the information is data. RD and WR determine
the direction of data flow through the Data Buffers. The
Data Buffers are bi-directional buffers that connect the
internal bus to the external bus. When the chip is not
selected (CS = 1), the devices are in a high impedance
state. The drivers input during WR-CS and output during
RD -CS.
Control and Timing Registers and Timing Control
These registers store the keyboard and display modes and
other operating conditions programmed by the CPU. The
modes are programmed by presenting the proper
command on the data lines with Ao = 1 and then sending
a WR. The command is latched on the rising edge of WR.
7-140
AFN-00742A-02
8279/8279·5
FUNCTIONAL DESCRIPTION
Since data input and display are an integral part of many
microprocessor designs. the system designer needs an
interface that can control these functions without placing
a large load on the CPU. The 8279 provides this function
for a-bit microprocessors.
• Scanned Sensor Matrix - with encoded (8 x a matrix
switches) or decoded (4x8 matrix switches) scan lines.
Key status (open orclosed) stored in RAM addressable
by CPU.
• Strobed Input -- Data on return lines during control
line strobe is transferred to FIFO.
The 8279 has two sections: keyboard and display. The
keyboard section can interface to regular typewriter style
keyboards or random toggle or thumb switches. The
display section drives alphanumeric displays or a bank of
indicator lights. Thus the CPU is relieved from scanning
the keyboard or refreshing the display.
Output Modes
• 8 or 16 character multiplexed displays that can be organized as dual 4-bit or single 8-bit (80 Do, A3 0 7 ).
=
=
• Right entry or left entry display formats.
The 8279 is designed to directly connect to the
microprocessor bus. The CPU can program all operating
modes for the 8279. These modes include:
Other features of the 8279 include:
• Mode programming from the CPU.
Input Modes
• Clock Prescaler
• Scanned Keyboard with encoded (8 x 8 key
keyboard) or decoded (4 x 8 key keyboard) scan lines.
A key depression generates a 6-bit encoding of key
position. Position and shift and control status are
stored in the FIFO. Keys are automatically debounced
with 2-key lockout or N-key rollover.
• Interrupt output to signal CPU when there is keyboard
or sensor data available.
CLK
DISPLAY
ADDRESS
REGISTERS
RESET
• An 8 byte FIFO to store keyboard information.
• 16 byte internal Display RAM tor display refresh. This
RAM can also be read by the CPU.
DBO-7
AD
WR
CS
IRQ
KEYBOARD
DEBOUNCE
AND
CONTROL
16 x 8
DISPLAY
RAM
TIMING
AND
CONTROL
OUT Ao.3
OUT B0-3
SL03
7-141
AFN-00742A-03
8279/8279·5
The command is then decoded and the appropriate
function is set. The timing control contains the basic
timing counter chain. The first counter is a + N prescaler
that can be piOgiammed to yield an intemal fiequency
of 100 kHz which gives a 5.1 ms keyboard scan time and
a 10.3 ms debounce time. The other counters divide
down the basic internal frequency to provide the proper
key scan, row scan, keyboard matrix scan, and display
scan times.
SOFTWARE OPERATION
8279 commands
The following commands program the 8279 operati!!S
modes. The commands are sent on the Data Bus with CS
low and Ao high and are loaded to the 8279 on the rising
edge of WR.
Keyboard/Display Mode Set
MSB
Scan Counter
The scan counter has two modes. In the encoded mode.
the counter provides a binary count that must be
externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode. the scan
counter decodes the least significant 2 bits and provides a
decoded 1 of 4 scan. Note than when the keyboard is in
decoded scan, so is the display. This means that only the
first 4 characters in the Display RAM are displayed.
In the encoded mode, the scan lines are active high
outputs. In the decoded mode, the scan lines are active
low outputs.
Code:
LSB
1010101010lKIKIKI
Where DD is the Display Mode and KKK is the Keyboard
Mode.
DO
o
o
0
8 8-bit character display 16 8-bit character display -
o
8 8-bit character display 16 8-bit character display -
Return Buffers and Keyboard Debounce
and Control
The 8 return lines are buffered and latched by the Return
Buffers. In the keyboard mode, these lines are scanned.
looking for key closures in that row. If the debounce
circuit detects a closed switch, it waits about 10 msec to
check if the switch remains closed. If it does, the address
of the switch in the matrix plus the status of SHIFT and
CONTROL are transferred to the FIFO. In the scanned
Sensor Matrix modes, the contents of the return lines is
directly transferred to the corresponding row of the
Sensor RAM (FIFO) each key scan time. In Strobed Input
mode, the contents of the return lines are transferred to
the FIFO on the rising edge of the CNTL/STB line pulse.
Display Address Registers and Display RAM
The Display Address Registers hold the address of the
word currently being written or read by the CPU and the
two 4-bit nibbles being displayed. The read/write
addresses are programmed by CPU command. They also
can be set to auto increment after each read or write. The
Display RAM can be directly read by the CPU after the
correct mode and address is set. The addresses for the A
and B nibbles are automatically updated by the 8279 to
match data entry by the CPU. The A and B nibbles can be
entered independently or as one word, according to the
mode that is set by the CPU. Data entry to the display can
be set to either left or right entry. See Interface
Considerations for details.
Left entry'
Right entry
Right entry
For description of right and left entry, see Interface
Considerations. Note that when decoded scan is set in
keyboard mode, the display is reduced to 4 characters
independent of display mode set.
KKK
0
0
0
0
Encoded Scan Keyboard -
0
2 Key Lockout*
Decoded Scan Keyboard - 2-Key Lockout
0
0
Encoded Scan Keyboard -
N-Key Rollover
0
1
Decoded Scan Keyboard -
N-Key Rollover
0
Encoded Scan Sensor Matrix
0
Strobed Input, Encoded Display Scan
0
0
FIFO/Sensor RAM and Status
This block is a dual function 8 x 8 RAM. In Keyboard or
Strobed Input modes, it is a FIFO. Each new entry is
written into successive RAM positions and each is then
read in order of entry. FIFO status keeps track of the
number of characters in the FIFO and whether it is full or
empty. Too many reads or writes will be recognized as an
error. The status can be read by an RD with CS low and
Ao high. The status logic also provides an IRQ signal
when the FIFO is not empty. In Scanned Sensor Matrix
mode, the memory is a Sensor RAM. Each row of the
Sensor RAM is loaded with the status of the corresponding row of sensor in the sensor matrix. In this mode, IRQ is
high if a change in a sensor is detected.
Left entry
Decoded Scan Sensor Matrix
Strobed Input, Decoded Display Scan
Program Clock
Code:
1.0 I 0 111
pip 1 pip 1P I
All timing and multiplexing Signals for the 8279 are
generated by an internal prescaler. This prescaler
divides the external clock (pin 3) by a programmable
integer. Bits PPPPP determine the value of this integer
which ranges from 2 to 31. Choosing a divisor that YJe.l.9s
100 kHz will give the specified scan and debounce
times. For instance, if Pin 3 of the 8279 is being clocked
by a 2 MHz Signal, PPPPP should be set to 10100 to
divide the clock by 20 to yield the proper 100 kHz operating frequency.
Read FIFO/Sensor RAM
Code:
I
0 11 1 0 1 AI 1 X 1 A
I TAl
A
X = Don't Care
The CPU sets up the 8279 for a read of the FIFO/Sensor
RAM by first writing this command. In the Scan Key'Default after reset.
7-142
AFN-00742A-04
8279/8279·5
board Mode, the Auto-Increment flag (AI) and the RAM
address bits (AAA) are irrelevant. The 8279 will automatically drive the data bus for each subsequent read (AD =0)
in the same sequence in which the data first entered the
FIFO. All subsequent reads will be from the FIFO until
another command is issued.
Clear
The <;,bits are available in this command to clear all rows
of the Display RAM to a selectable blanking code as follows:
r
1
0
AB
1
1
All Ones
Ie: r~ r
In the Sensor Matrix Mode, the RAM address bits AAA
select one of the 8 rows of the Sensor RAM. If the AI flag
is set (AI = 1), each successive read will be from the subsequent row of the sensor RAM.
All Z"o, (X • Don',
= Hex
20 (0010
Enable clear display when
=
ea,,)
ooom
1 (or by CA
=
1)
Read Display RAM
Code:
I
0 11 11 1 AliA 1 A 1 A 1 A 1
The CPU sets up the 8279 for a read of the Display RAM
by first writing this command. The address bits AAAA
select one of the 16 rows of the Display RAM. If the AI
flag is set (AI = 1), this row address will be incremented
after each following read or write to the Display RAM.
Since the same counter is used for both reading and
writing, this command sets the next read or write
address and the sense of the Auto-Increment mode for
both operations.
During the time the Display RAM is being cleared (""160 I-Is),
it may not be written to. The most significant bit of the
FIFO status word is set during this time. When the Display RAM becomes available again, it automatically
resets.
If the C F bit is asserted (C F = 1), the FIFO status is
cleared and the interrupt output line is reset. Also, the
Sensor RAM pointer is set to row O.
C A , the Clear All bit, has the combined effect of CD and
C F ; it uses the CD clearing code on the Display RAM and
also clears FIFO status. Furthermore, it resynchronizes
the internal timing chain.
Write Display RAM
End Interrupt/Error Mode Set
Code:
11 1 0 1 0 1 AliA 1 A 1 A 1 A 1
The CPU sets up the 8279 for a write to the Display RAM
by first writing this command. After writing the command with AD 1, all subsequent writes with AD 0 wi II
be to the Display RAM. The addressing and AutoIncrement functions are identical to those for the Read
Display RAM. However, this command does not affect
the source of subsequent Data Reads; the CPU will read
from whichever RAM (Display or FIFO/Sensor) which
was last specified. If, indeed, the Display RAM was last
specified, the Write Display RAM will, nevertheless,
change the next Read location.
=
=
Code:
11 11 11 IE IX Ix Ix Ix 1 X = Don't
care.
For the sensor matrix modes this command lowers the
IRQ line and enables further writing into RAM. (The IRQ
line would have been raised upon the detection of a
change in a sensor value. This would have also inhibited
further writing into the RAM until resetl.
For the N-key rollover mode - if the E bit is programmed
to "1" the chip will operate in the special Error mode. (For
further details, see Interface Considerations Section.)
Status Word
Display Write Inhibit/Blanking
The IW Bits can be used to mask nibble A and nibble B
in applications requiring separate 4-bit display ports. By
setting the IW flag (IW = 1) for one of the ports, the port
becomes marked so that entries to the Display RAM
from the CPU do not affect that port. Thus, if each nibble
is input to a BCD decoder, the CPU may write a digit to
the Display RAM without affecting the other digit being
displayed. It is important to note that bit Bo corresponds
to bit Do on the CPU bus, and that bit A3 corresponds to
bit 0 7,
If the user wishes to blank the display, the BL flags are
available for each nibble. The last Clear command issued
determines the code to be used as a "blank." This code
defaults to all zeros after a reset. Note that both BL
flags must be set to blank a display formatted with a
single 8-bit port.
The status word contains the FIFO status, error, and
display unavailable signals. This word is read by the CPU
when AD is high and CS and RD are low. See Interface
Considerations for more detail on status word.
Data Read
Data is read when AD, CS and RD are all low. The source
of the data is specified by the Read FIFO or Read Display
commands. The trailing edge of RD will cause the address
of the RAM being read to be incremented if the AutoIncrement flag is set. FIFO reads always increment (if no
error occurs) independent of AI.
Data Write
Data that is written with AD. CS and WR low is always
written to the Display RAM. The address is specified by the
latest Read Display or Write Display command. AutoIncrementing on the rising edge of WR occurs if AI set by
the latest display command.
7-143
AFN-00742A-05
8279, 8.279-5
ABSOLUTE MAXIMUM RATINGS·
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a Sti6SS iating only and functional opsiation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Ambient Temperature . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . -65°C to 125°C
Voltage on any Pin with
Respect to Ground . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1 Watt
D.C. CHARACTERISTICS
Symbol
TA
= ooe to 70 oe.
Vss = OV. Note 1
Min.
Max.
Unit
VIL1
Input Low Voltage for Shift Control
and Return Lines
Parameter
-0.5
1.4
V
VIL2
Input Low Voltage for All Others
-0.5
0.8
V 11_: 1
Input High Voltage for Shift, Control
and Return Lines
2.2
VIH2
Input High Voltage for All Others
2.0
VOL
Output Low Voltage
VOH
Output High Voltage on Interrupt
Line
IIL1
Input Current on Shift, Control and
Return Li nes
+10
-100
/lA
/lA
VIN = Vee
VIN = OV
Test Conditions
V
V
V
0.45
3.5
'V
Note 2
V
Note 3
IIL2
Input Leakage Current on All Others
±10
/lA
VIN = Vee to OV
IOFL
Output Float Leakage
±10
/lA
VOUT = Vee to OV
Icc
Power Supply Current
120
mA
Notes:
1. 8279, vee = +5V ± 5%; 8279-5, Vee = +5V ± 10%.
2. 8279, IOL = 1.6mA; 8279·5, IOL = 2.2mA.
3. 8279, IOH = -100,uA; 8279-5, IOH = -400,uA.
CAPACITANCE
TEST CONDITIONS
SYMBOL
TEST
TYP.
MAX.
UNIT
Cin
Input Capacitance
5
10
pF
Vin=Vee
Cout
Output Capacitance
10
20
pF
Vout=Vee
7·144
AFN-00742A-09
8279, 8279-5
A.C. CHARACTERISTICS
TA
=
o°c to 70°C, Vss
= OV,
(Note 1)
BUS PARAMETERS
READ CYCLE:
8279
Symbol
Parameter
8279-5
Max.
Min.
Min.
Max.
Unit
tAR
Address Stable Before READ
50
0
ns
tRA
Address Hold Time for READ
5
0
ns
tRR
tRO[2]
READ Pulse Width
420
250
ns
Data Delay from READ
300
150
tAO[2]
Address to Data Valid
450
250
ns
tDF
READ to Data Floating
10
100
ns
tRCY
Read Cycle Ti me
1
10
100
ns
1
iJ.s
WRITE CYCLE:
8279-5
8279
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tAW
Address Stable Before WR ITE
50
0
ns
tWA
Address Hold Time for WR ITE
20
0
ns
tww
WR ITE Pulse Width
400
250
ns
tDW
Data Set Up Time for WR ITE
300
150
ns
two
Data Hold Time for WR ITE
40
0
ns
Notes:
1. 8279, V CC =
+5V ± 5%; 8279-5, VCC = +5V ± 10%.
2. 8279, CL = 1OOpF; 8279-5, CL = 150pF.
OTHER TIMINGS:
8279-5
8279
Symbol
Parameter
Min.
tw
Clock Pu Ise Width
230
120
nsec
tCY
Clock Period
500
320
nsec
Keyboard Scan Time:
Keyboard Debounce Time:
Key Scan Time:
Display Scan Time:
Max.
Min.
Digit-on Time:
Blanking Time:
Internal Clock Cycle:
5.1 msec
10.3 msec
80 iJ.sec
10.3 msec
Max.
Unit
480 iJ.sec
160 iJ.sec
10 iJ.sec
INPUT WAVEFORMS FOR A.C. TESTS:
"=X
2.0
>
TEST POINTS
0.8
0.45
7-145
<
2.0
0.8
)C
AFN-00742A-10
8279, 8279-5
WAVEFORMS
1. Read Operation
AO,
ES
~-----------------------tAR - - 1....·>---------------------'RCy
(SYSTEM'S
ADDRESS BUS)
------+-'~-----------I
(READ CONTROL)
1.--------tAo--------·
DATA BUS
(OUTPUT)
~~~~~~~~~~~+-----------------~~~~~~~~~~~~~
2. Write Operation
AO,
(SYSTEM'S
ADDRESS BUS)
CS
(WRITE CONTROL)
DATA
DATA BUS
--J
(INPUT) ______________________
MAY CHANGE
- D A T A VALID
DATA
MAY CHANGE
3. Clock Input
7-146
AFN-00742A-11
8279 SCAN TIMING
SCAN WAVEFORMS
L
ENCODED
SCAN
L
L
~U
5.1
DECODED
SCAN
U
~
u
u
U
U
U
u
U
U
u
u
u
LJ
DISPLAY WAVEFORMS
1+-------640~$=64ICy------1
ASSUME INTERNAL FREQUENCY
SO ICY= 10~$
=100 kHz
~
Ao- A 3
ACTIVE HIGH
A(1)
"BLANK CODE IS EITHER ALL
O's OR ALL 1'$ OR 20 HEX
Bo-B3
ACTIVE HIGH
B(1)
NOTE: SHOWN IS ENCODED SCAN LEFT ENTRY
52-53 ARE NOT SHOWN BUT THEY ARE SIMPLY 51 DIVIDED BY 2 AND 4
7-147
AFN-00742A-12
intJ
8282/8283
OCTAL LATCH
•
Address Latch for iAPX 86,88,
MCS·80™, MCS·85™, MCS·48™ Families
•
3·State Outputs
•
High Output Drive Capability for
Driving System Data Bus
•
20·Pin Package with 0.3" Center
•
Fully Parallel 8·Bit Data Register and
Buffer
•
•
Transparent during Active Strobe
No Output Low Noise when Entering
or Leaving High Impedance State
The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers. They can be used to implement latches, buffers,
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with these devices.
Dlo
VCC
01 0
VCC
01 1
000
01 1
000
01 2
001
01 2
001
01 3
002
01 3
002
01 4
003
01 4
003
015
004
015
004
01 6
005
01 6
005
01 7
006
01 7
006
OE
007
OE
007
GNO
STB
GNO
STB
Figure 1. 8282 Pin Configuration
Figure 2. 8283 Pin Configuration
7-148
828218283
r-------,
8282
8---
I
8-.---+----f
-t-B
I
D
Q
L ______ _
I
I
I
I
>---,--s
L ______ _
-------;
m
'" FL------Dis
801
6
~-------
:::::J
L ______ _
{§j
-{:§TI
--*O~
-~
~
Figure 3. Logic Diagrams
PIN DEFINITIONS
Pin
STB
OPERATIONAL DESCRIPTION
Description
The 8282 and 8283 octal latches are 8-bit' latches with
3-state output buffers. Data having satisfied the setup
time requirements is latched into the data latches by
strobing the STB line HIGH to LOW. Holding the STB
line in its active HIGH state makes the latches appear
transparent. Data is presented to the data output pins by
activating the OE input line. When OE is inactive HIGH
the output buffers are in their high impedance state.
Enabling or disabling the output buffers will not cause
negative-going transients to appear on the data output
bus.
STROBE (Input). STB is an input control
pulse used to strobe data at the data input
pins (Ao-A7) into the data latches. This
signal is active HIGH to admit input data.
The data is latched at the HIGH to LOW
transition of STB.
OUTPUT ENABLE (Input). OE is an input
control signal which when active LOW
enables the contents of the data latches
onto the data output pin (Bo-B7). OE being
inactive HIGH forces the output buffers to
their high impedance state.
DATA INPUT PINS (Input). Data presented
at these pins satisfying setup time requirements when STB is strobed and
latched into the data input latches.
00 0-00 7
(8282)
000-00 7
(8283)
DATA OUTPUT PINS (Output). When OE is
true, the data in the data latches is presented as inverted (8283) or non-inverted
(8282) data onto the data output pins.
7-14Q
intJ
828218283
ABSOLUTE MAXIMUM RATINGS·
'NOTICE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is astress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Temperature Under Bias ................. 0 °C to 70°C
Storage Temperature ............. - 65°C to + 150°C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. - 1.0V to + 5.5V
Power Dissipation .....•.................... 1 Watt
D.C. CHARACTERISTICS
Conditions: Vee = 5V ± 10%, TA =
ooe to 70°C
Max
Units
Vc
Input Clamp Voltage
-1
V
Icc
Power Supply Current
160
mA
IF
Forward Input Current
-0.2
mA
V F = 0.45V
IR
Reverse Input Current
50
~
V R = 5.25V
VOL
Output low Voltage
.45
V
IOL = 32 mA
V OH
Output High Voltage
V
IOH = -5 mA
IOFF
Output Off Current
± 50
~
V OFF = 0.45 to 5.25V
V IL
Input low Voltage
V IH
Input High Voltage
Symbol
CIN
Parameter
Min
2.4
0.8
2.0
Input Capacitance
12
Test Conditions
Ic = -5 mA
V
Vcc= 5.0V
See Note
1
V
Vee= 5.0V
See Note
1
F = 1 MHz
V SIAS = 2.5V, Vee= 5V
TA=25°C
pF
NOTE: 1. Output Loading IOL = 32 mA, IOH = - 5 mA, e L= 300 pF.
A.C. CHARACTERISTICS
Conditions: Vee = 5V ± 10%, TA =
ooe to 70°C
Loading: Outputs - IOL = 32 mA, IOH = - 5 mA, C L = 300 pF
Symbol
TIVOV
TSHOV
Min
Max
Units
Input to Output Delay
-Inverting
-Non-Inverting
5
5
22
30
ns
ns
STB to Output Delay
-Inverting
-Non-Inverting
10
10
40
45
ns
ns
18
30
ns
Parameter
Test Conditions
(See Note 1)
TEHOZ
Output Disable Time
5
TElOV
Output Enable Time
10
TIVSl
Input to STB Setup Time
0
ns
TSLIX
Input to STB Hold Time
25
ns
TSHSl
STB High Time
15
ns
ns
NOTE: 1. See waveforms and test load circuit on following page.
7-150
AFN oo727B
828218283
WAVEFORMS
INPUTS
TlVSL
STB
~----~-TSHSL------~ ~------------------------------------------------------
TELOV
VO:~ _ _ _ _
OUTPUTS
-----+__________- J 'fo-oI.......- - - - - - - - - - - - - - - - - - - - - - - - - - - ,
-C
VOL +.1V
TSHOV
NOTE: 1.8283 ONLY -
OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOn€D.
Figure 4. Timing Diagram
1.5V
1.5V
-r
-
33Q
OUT 0 - - -
:
2.14V
-,...
S2.7Q
180Q
OUT C>----<
I~'F
I3OO'F
3·STATE TO VOL
3·STATE TO VOH
OUTC>-----4
I~"F
SWITCHING
Figure 5. Output Test Load Circuits
7-151
AFN 007278
ifltel'
828218283
50
8283
40
0
w
I/)
z
30
>-
00
Ta
C
Length of IFC or REN False
> 100/-ls
Tg
C
Delay for EOI **
::::: 1.5/-lstt
Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an
upper case T indicate the minimum time that a function must remain in a state before exiting.
If three-state drivers are used on the DIO, DAV, and EOI lines, T1 may be:
1. 2: 11 OOns
2. Or 2: 700ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or 2: 500ns for all subsequent bytes following the first sent after each false tranSition of ATN (the first byte must be sent in
accordance with (1) or (21.
4. Or 2: 350ns for all subsequent bytes following the first sent after each false transition of ATN under conditions specified in
Section 5.2.3 and warning note. See IEEE Standard 488.
Time required for interface functions to accept, not necessarily respond to interface messages.
{) Implementation independent.
** Delay required for EOI, NDAC, and NRFD signal lines to indicate valid states.
tt
Value
Settling Time for Multiline Messages
2: 600ns for three-state drivers.
7-169
8291
Appendix C
THE THREE WIRE HANDSHAKE
_TWRD15i
I
I
VALID
T1L
,
I
NOT VALID
I----n
TDVNRl
,
~ t--TWRDV2-
!--TNDDV1-
}'t
I\.
-TRDNR3-
I---)
!---TDVND3 ...
)
!--TDVND2
"
~mDD"J
DREO(SH)
~,"VD"J
DREO(AH)
VALID
\
U
WR
V
Figure C-1. 3-Wire Handshake Timing at 8291.
7·170
V
i\.I---- TNRDV2 ---
V-
8291
SOURCE
ACCEPTOR
YES
YES
DATA IS VALID AND MAY
NOW BE ACCEPTED
NDAC SIGNAL LINE STAYS LOW UNTIL
ALL ACCEPTORS HAVE ACCEPTED IT
DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME
NO
FLOW DIAGRAM OUTLINES SE~UENCE OF EVENTS DURING TRANSFER OF
DATA BYTE. MORE THAN ONE LISTENER AT A TIME CAN ACCEPT DATA
BECAUSE OF LOGICAL AND CONNECTION OF NRFD AND NDAC LINES.
Figure C.2. Handshake Flowchart.
7-171
8291
Appendix D
FUNCTIONAL PARTITIONS
A
DEVICE (APPARATUS)
\
\
\
\
\
\
\
\
\
\
\
\
\
\
DEVICE
FUNCTIONS
MESSAGE
CODING
DRIVERS
AND
RECEIVERS
~_ _ _,--_ _ _----JIIL _ _ _ _ _ _ _ _~------------ll LI_----,_ _--'
MCS'·
SYSTEM
8291
A B12 3 45 -
8293
CAPABILITY DEFINED BY THE 488·1978 STANDARD.
CAPABILITY DEFINED BY THE DESIGNER.
INTERFACE BUS SIGNAL LINES.
REMOTE INTERFACE MESSAGES TO AND FROM INTERFACE FUNCTIONS,
DEVICE DEPENDENT MESSAGES TO AND FROM DEVICE FUNCTIONS.
STATE LINKAGES BETWEEN INTERFACE FUNCTIONS.
LOCAL MESSAGES BETWEEN DEVICE FUNCTIONS AND INTERFACE
FUNCTIONS (MESSAGES TO INTERFACE FUNCTIONS ARE DEFINED,
MESSAGES FROM INTERFACE FUNCTIONS EXIST ACCORDING TO THE
DESIGNER'S CHOICE).
6 - CONTROL MESSAGES (8292 ONLY).
Figure 0.1. Functional Partition Within a Device.
7-172
8292
GPIB CONTROLLER
• Complete IEEE Standard 488 Controller
Function
• Complete Implementation of Transfer
Control Protocol
• Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or
Initialization of the Bus
• Synchronous Control Seizure Prevents
the Destruction of Any Data
Transmission in Progress
• Responds to Service Requests (SRQ)
• Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control
• Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker/ Listener/ Controller
The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener
to implement the full IEEE Standard 488 controller function, including transfer control protocol. The 8292 is a preprogrammed Intel® 8041A.
PIN CONFIGURATION
8291,8292 SYSTEM DIAGRAM
MICROPROCESSOR SYSTEM BUS
IFCL
X1
Vcc
COUNT
X2
REN
r--- ---.
DACK
RESET
OAV
I
DREO
Vec
IBFI
Cs
OBFI
GND
EOI
RD
SPI
AO
TCI
WR
CIC
SYNC
NC
DO
ATNO
01
NC
02
CLTH
03
VCC
04
NC
05
SYC
Os
IFC
07
ATNI
VSS
SRQ
I
I
I
DMA
CONTROLLER
(OPTIONAL)
8291
GPIB
TALKERI
LISTENER
I
I
L ______ I
8292
GPIB
CONTROLLER
T/R2
TiAl
8293
BUS
TRANSCEIVERS
GENERAL PURPOSE INTERFACE BUS
7-173
00741C
8292
PIN DESCRIPTION
~ymbOI I~~ I~i:"N~~ I ~. ,
Function
irvL.
I
I
I r v neCeiVeU \laIClleU} -
vee
I lie O~l1~
monitors the IFC Line (when not
system controller) through this
pin.
X 1, X2
I
2, 3
Inputs for a crystal, LC or an external timing signal to determine the
internal oscillator frequency.
RESET
I
4
Used to initialize the chip to a
known state during power on.
CS
I
6
Chip Select Input - Used to select
the 8292 from other devices on the
common data bus.
RO
I
8
1/0 write input which allows the
master CPU to read from the 8292.
Ao
I
9
Address Line - Used to select between the data bus and the status
register during read operations
and to distinguish between· data
and commands written into the
8292 during write operations.
-
WR
I
10
1/0 read input which allows the
master CPU to write to the 8292.
SYNC
0
11
8041A instruction cycle synchronization signal; it is an output
clock with a frequency of
XTAL+ 15.
0 0 -0 7
110
12-19
8 bidirectional lines used for communication between the central
processor and the 8292's data bus
buffers and status register.
Vss
P.S.
7, 20
Circuit ground potential.
SRO
I
21
Service Request - One of the
IEEE control lines. Sampled by the
8292 when it is controller in
charge. If true, SPI interrupt to the
master will be generated.
ATNI
I
22
Attention In - Used by the 8292 to
monitor the GPIB ATN control
line. It is used during the transfer
control procedure.
IFC
1/0
23
Interface Clear - One of the GPIB
management lines, as defined by
IEEE Std. 488-1978, places all devices in a known quiescent state.
SYC
I
24
System Controller - Monitors the
system controller switch.
CLTH
0
27
CLEAR LATCH Output - Used to
clear the IFCR latch after being
recognized by the 8292. Usually
low (except after hardware Reset),
it will be pulsed high when IFCR is
recognized by the 8292.
ATNO
0
29
COUNT.
Attention Out - Controls the ATN
control line of the bus through external logic for tcs and tca procedures. (ATN is a GPIB control
line, as defined by IEEE Std~
488-1978.)
7-174
t"".i). 0, ~O, QU
+ov supply
Function
inpUt. ~ IU70.
I
39
Count Input - When enabled by
the proper command the internal
counter will count external events
through this pin. High to low transition will increment the internal
counter by one. The pin is sampled
once per three internal instruction
cycles (7.5J.1sec sample period
when using 6 MHz XTAL). It can be
used for byte counting when connected to NOAC, or for block
counting when connected to the
EOL
REN
0
38
The Remote Enable bus signal
selects remote or local control of
the device on the bus. A GPIB bus
management line, as defined by
IEEE Std. 488-1978.
OAV
1/0
37
OAV Handshake Line - Used duro
ing parallel poll to force the 8291
to accept the parallel poll status
bits. It is also used during the tcs
procedure.
IBFI
o
36
Input Buffer Not Full - Used to
interrupt the central processor
while the input buffer of the 8292
is empty. This feature is enabled
and disabled by the interrupt
mask register.
OBFI
o
35
Output Buffer Full - Used as an
interrupt to the central processor
while the output buffer of the 8292
is full. The feature can be enabled
and disabled by the interrupt
mask register.
EOl2
110
34
End Or Identify - One of the GPIB
management lines, as defined by
IEEE Std. 488-1978. Used with ATN
as Identify Message during parallel poll.
SPI
o
33
Special Interrupt - Used as an
interrupt on events not initiated by
the central processor.
TCI
o
32
Task Complete Interrupt - Interrupt to the control processor used
to indicate that the task requested
was completed by the 8292 and
the information requested is ready
in the data bus buffer.
CIC
o
31
Controller In Charge - Controls
the SIR input of the SRO bus
transceiver. It can also be used to
indicate that the 8292 is in charge
of the GPIB bus.
00741C
8293
GPIB TRANSCEIVER
• Nine Open-collector or Three-state
Line Drivers
• On-chip Decoder for Mode
Configuration
• 48 mA Sink Current Capability on
Each Line Driver
• Power Up/Power Down Protection to
Prevent Disrupting the IEEE Bus
• Nine Schmitt-type Line Receivers
• Connects with the 8291 and 8292 to
Form an IEEE Standard 488 Interface
Talker/Listener/Controller with no
Additional Components
• High Capacitance Load Drive
Capability
• Single 5V Power Supply
• 28-Pin Package
• Only Two 8293's Required per GPIB
Interface
• Low Power HMOS Design
• On-Chip IEEE-488 Bus Terminations
The Intel® 8293 GPIB Transceiver is a high current, non-inverting buffer chip designed to interface the 8291 GPIB
Talker/Listener or the 8292 GPIB Controller with the 8291 to the IEEE Standard 488-1978 Instrumentation Interface
Bus. Each GPIB interface would contain two 8293 Bus Transceivers. In addition, the 8293 can also be used as a general
purpose bus driver.
PIN CONFIGURATION
8291,8292,8293 SYSTEM DIAGRAM
MICROPROCESSOR SYSTEM BUS
TIR1
Vee
r--- ---.
TIR2
OPTA
I
EOI
OPTB
I
I
ATN
DATA10
DATA1
I
8257
DMA
CONTROllER
(OPTIONAL)
DACR
8291
GPIB
TALKERI
LISTENER
DRO
I
I
L______ J
DArA8
DATA3
TIR 2
BUS9
BUS8
DATA5
GND
BUS7
TIR1
BUSS
BUSS
BUS4
8293
BUS
TRANSCEIVERS
GENERAL PURPOSE INTERFACE BUS
7-175
8292
GPIB
CONTROLLER
8293
PIN DESCRIPTION
Symbol·
Symbol
1/0
Pin No.
Function
BUSiBUS9
iiO
;2, ;3,
These are the IEEE·488 bus
interface driver/receivers.
Using the mode select pins,
they can be configured .differently to allow direct connections between the 8291 GPIB
Talker/Listener and the 8292
GPIB Controller.
DATA1DATA10
110
15-19,
21,22
5-11,
23-25
T/R1
These are the pins to be Gonnected to the 8291 and 8292 to
interface with the GPIB bus.
Their use is programmed by
the two mode select pins,
OPTA and OPTB. All these
pins are TTL compatible.
Transmit receive 1; this pin
controls the direction for
NDAC, NRFD, DAV, and D101D108. Input is TTL compatible.
T/R2
2
Transmit receive 2; this pin
controls the direction for EOL
Input is TTL compatible.
OPTA
OPTB
Function
1/0
Pin No.
I/O
3
End or Identify; this pin indicates the end of a multiple
byte transfer or, in conjunction with ATN, addresses the
device during a polling sequence. It connects to the
8291 and is switched between
transmit and receive by T/R2.
This pin is TTL compatible.
o
4
Attention; this pin is used by
the 8291 to monitor the GPIB
ATN control line. It specifies
how data on the DIO lines is to
be interpreted. This output is
TTL compatible.
27
These two pins are to control
the function of the 8293. A
truth table of how this programs the various modes is in
Table 1.
26
Vee
P.S. 28
Positive power supply (5V
± 10%).
GND
P.S. 14,20
Circuit ground potential.
Table 1. 8293 Mode Selection Pin Mapping
IEEE Implementation Name
Pin No.
Mode 0
Mode 1
Mode 2
Mode 3
OPTA
OPTB
27
26
0
0
1
0
0
1
1
1
DATA1
BUS1
DATA2
BUS2
DATA3
BUS3
DATA4
BUS4
DATA5
BUS5
DATA6
BUS6
DATA7
DATA8
BUS7
DATA9
BUS8
DATA10
BUS9
5
12
6
13
7
15
8
16
9
17
10
18
11
23
19
24
21
25
22
IFC
IFC·
REN
REN*
NC
EOI·
SRO
SRO·
NRFD
NRFD·
NDAC
NDAC·
T/R101
T/RI02
ATN·
GI01
G101·
GI02
G102·
DI08
D108·
DI07
D107·
Dl06
D106·
DI05
D105·
0{04
D104·
DI03
D103·
NC
DI02
D102·
DAV
DAV·
DI01
D101·
IFC
IFC·
REN
REN·
EOl2
EOI·
SRO
SRO·
NRFD
NRFD·
NDAC
NDAC·
ATNI
ATNO
ATN*
CIC
CLTH
IFCL
SYC
DI08
D108·
DI07
DI07*
DI06
D106·
DI05
D105·
DI04
D104·
DI03
D103·
ATNO
DI02
D102·
DAV
DAV·
DI01
D101·
T/R1
T/R2
EOI
ATN
T/R1
NC
EOI
ATN
T/R1
T/R2
EOI
ATN
TlR1
IFCL
EOI
ATN
Pin Name
T/A1
T/R2
EOI
ATN
1
2
3
4
• Note: These pins are the IEEE·488 bus non·inverting driver/receivers. They include all the bus terminations required by the Standard and may be
connected directly to the GPIB bus connector.
7-176
8293
MODEO
GENERAL DESCRIPTION
The 8293 is a bidirectional transceiver. It was designed
to interface the Intel 8291 GPIB Talker/Listener and the
Intel@ 8292 GPIB Controller to the IEEE Standard
488-1978. Instrumentation Bus (also referred to as the
GPIB Bus). The Intel GPIB Bus Transceiver meets or exceeds all of the electrical specifications defined in the
IEEE Standard 488-1978, Section 3.3-3.5, including the
required bus termination specifications.
OPTA
OPTB
THREE
STATE ONLY
GI01
TIRI01
THREE
STATE ONLY
GI02
GI0 1"
GI02"
TIRI02
INPUT ONLY
iF(:
The 8293 can be hardware programmed to one of four
modes of operation. These modes allow the 8293 to be
configured to support both a Talker/Listener/Controller
environment and Talker/Listener environment. In addition, the 8293 can be used as a general purpose threestate (push-pull) or open-collector bus transceiver with
nine receiver/drivers. Two modes are used to support a
Talker/Listener environment (see Figure 1), and to support a Talker/Listener/Controller environment (see
Figure 2). Mode 1 is the general purpose mode.
INPUT ONLY
REN
INPUT ONLY
ATN
OPEN COL
OUTPUT ONLY
SRO
THREE
STATE ONLY
EOI
IFC"
REN"
ATN"
SRO"
EOI"
TIR2
GPIB
NRFD
OPTA
12
OPTB
8293
NDAC
Tlih
MODE 1
TO
PROCESSOR
BUS
14
8291
18
3
TIC
1 =THREE STATE
0= OPEN COLLECTOR
SIR
1 = SEND TO GPIB
=OV
0= RECEIVE FROM GPIB
" = IEEE·488 BUS NON·INVERTING DRIVERIRECEIVER
=+5V
-&
Figure 3. Talker/Listener Control Configuration
OPTA
OPTB
8293
MODE 0 PIN DESCRIPTION
MODEO
Symbol
GPIB
I/O
Pin No.
T/R1
Transmit receive 1; direction
control for NOAC and NRFO. If
T/R1 is high, then NOAC* and
NRFO* are receiving. Input is
TTL compatible.
Figure 1_ Talker/Listener Configuration
GPIB
I/O
10
Not Oata Accepted; processor
GPIB bus handshake control
line; used to indicate the condition of acceptance of data
by device(s). It is TTL compatible.
I/O
18
Not Oata Accepted; IEEE
GPIB bus handshake control
line. When an input, it is a TTL
compatible Schmitt-trigger.
When an output, it is an opencollector driver with 48 mA
sinking capability.
I/O
9
Not Ready For Oata; processor GPIB handshake control
line; used to indicate the condition of readiness of device(s) to accept data. This pin
is TIL compatible.
TO
PROCESSOR
BUS
NOAC*
TO
PROCESSOR
BUS
GPIB
Figure 2. Talker/Listener/Controller Configuration
7-177
Function
8293
Symbol
I/O
Pin No.
NRFO"
110
17
T/R2
1/0
EOI"
1/0
Transmit receive 2; direction
control for EOL If T/R2 is high,
EOI* is sending. Input is TTL
compatible.
3
End or Identify; processor
GPIB bus control line; is used
by a talker by indicate the end
of a multiple byte transfer.
This pin is TTL compatible.
15
End or Identify; IEEE GPIB bus
control line; is used by a talker
to indicate the end of a multiple byte transfer. This pin is a
three-state (push-pull) driver
capable of sinking 48 mA and
a TTL compatible receiver
with hysteresiS.
16
Service Request; IEEE GPIB
bus control line; it is an op~n
collector driver capable of
sinking 48 mAo
o
6
Remote Enable; processor
GPIB bus control line; used by
a controller (in conjunction
with other messages) to
select between two alternate
sources of device programming data (remote ·or local
control). This output is TTL
compatible.
13
Remote Enable; IEEE GPfB
bus control line. This input is
a TTL compatible Schmitttrigger.
4
Attention; processor GPIB
bus control line; used by the
8291 to determine how data
on the 010 signal lines are to
be interpreted. This is a TTL
compatible output.
o
19
Symbol
Attention; IEEE GPIB bus control line; this input is a TTL
compatible Schmitt-trigger.
I/O
o
Pin No.
5
Function
Interface
Clear;
processor
GPIB bus contiolline; used by
a controller to place the interface system into a known
quiescent state. It is a TTL
compatible output.
IFC*
12
Interface Clear; IEEE GPIB
bus control line. This input is
a TTL compatible Schmitttrigger.
T/RI01
T/RI02
11
23
Transmit receive General 10;
direction control for the two
spare transceivers. Input is
TTL compatible.
G101*
G102*
Service Request; processor
GPIB bus control line; used by
a device to indicate the need
for service and to request an
interruption of the current sequence of events on the GPIB.
It is a TTL compatible input
o
REN*
ATN*
Not Ready For Data; IEEE
GPIB bus handshake control
line, When an input, it is a TTL
compatible Schmitt·trigger.
When an output, it is an opencollector driver with a 48 mA
current sinking capability.
2
8
SRQ*
Function
110
110
24
25
General 10; this is the TTL
side of the two spare transceivers. These pins are TTL
compatible.
110
110
21
22
General 10; these are spare
three-state (push-pull) driversl
Schmitt-trigger receivers. The
drivers can sink 48 mAo
MODEl
OPTA
OPTB
DTOa t - - - - - - - + - t
ATN
EOi
Figure 4. Talker/Listener Data Configuration
7·178
8293
MODE 1 PIN DESCRIPTION
MOOE2
OPTA
Symbol
I/O
Pin No.
Function
OPTB
Transmit receive 1; controls
the direction for DAV and the
DIO lines. If T/R1 is high, then
all these lines are sending information to the IEEE GPIB
lines. This input is TTL compatible.
T/R1
NOAC
NOAC"
NImi
NRFO"
TlR1
~
IFC"
SYC
3
4
1/0
DAV*
1/0
1/0
24
21
End of Sequence and Attention; processor GPIB control
lines. These two control
signals are ANDed together to
determine whether all the
transceivers in the 8293 are
three-state (push-pull) or
open-collector. When both
signals are low (true), then the
controller is performing a
parallel poll and the transceivers are all opencollector. These inputs are
TTL compatible.
Data Valid; processor GPIB
bus handshake control line;
used to indicate the condition
(availability and validity) of information on the DIO signals.
It is TTL compatible.
Data Valid; IEEE GPIB bus
handshake control line. When
an input, it is a TTL compatible Schmitt-trigger. When
DAV* is an output, it can sink
48 mA.
25,23,
10,9,
8,7,
6,5
Data InputlOutput; processor
GPIB bus data lines; used to
carry message and data bytes
in a bit-parallel byte-serial
form controlled by the three
handshake signals. These
lines are TTL compatible.
22, 19,
18,17,
16, 15,
13, 12
Data Input/Output; IEEE GPIB
bus data lines. They are TTL
compatible Schmitt-triggers
when used for input and can
sink 48 mA when used for output. See ATN and EOI description for output mode.
RE"R
REN"
SRO
SRO"
A'i'Ni
Ern2
1/0
7-179
EOI"
A'ftm
EOi
T/R2
IFCL J--................
CLTH
CIC
r----..._
r - - - -........- '
Figure 5. Talker/Listener/Controller Control
Configuration
MODE 2 PIN DESCRIPTION
Symbol
I/O
Pin No.
Function
Transmit receive 1; direction
control for NDAC and NRFD.
If T/R1 is high, then NDAC and
NRFD are receiving. Input is
TTL compatible.
T/R1
NDAC*
D101*
D108*
ATN"
AfR
1/0
10
Not Data Accepted; processor
GPIB bus handshake control
line; used to indicate the condition of acceptance of data
by device(s). This pin is TTL
compatible.
1/0
18
Not Data Accepted; IEEE
GPIB bus handshake control
line. It is a TTL compatible
Schmitt·trigger when used for
input and an open-collector
driver with a 48 mA current
sink capability when used for
output.
8293
Symbol
1/0 Pin No.
NRFO
I/O
NRFO*
1/0
SYC
REN
1/0
9
17
Not Ready For Data; IEEE
GPIB bus handshake control
line. It is a TTL compatible
Schmitt·trigger when used for
input and an open-collector
driver with a 48 mA current
sink capability when used for
output.
22
System Controller; used to
monitor the system controller
switch and control the direction for IFC and REN. This pin
is a TTL compatible input.
6
Remote Enable; processor
GPIB control line; used by the
active controller (in conjunction with other messages) to
select between two alternate
sources of device programming data (remote or local control). This pin is TTL compatible.
1/0
13
Remote Enable; IEEE GPIB
bus control line. When used as
an input, this is a TTL compatible Schmitt-trigger. When an
output, it is a three-state driver
with a 48 mA current sinking
capability.
IFC
1/0
5
Interface Clear; processor
GPIB bus control line; used by
the active controller to place
the interface system into a
known quiescent state. This
pin is TTL compatible.
CLTH
1/0
12
o
Controller in Charge; used to
control the direction of the
SRO and to indicate that the
8292 is in charge of the bus.
CiC is a TTL compatible input.
21
Clear Latch; used to clear the
IFC Received latch after it has
been recognized by the 8292.
Normally low (except after
a hardware reset), it will be
pulsed low when IFC Received
Pin No.
Function
25
IFC Received
Latched; the
8292 monitors the IFC line
when it is not the active controller through this pin.
SRO*
1/0
8
Service Request; processor
GPIB control line; indicates
the need for attention and requests the active controller to
interrupt the current sequence
of events on the GPIB bus.
This pin is TTL compatible.
I/O
16
Service Request; IEEE GPIB
bus control line. When used
as an input, this pin is a TTL
compatible Schmitt-trigger.
When used as an output, it is
an open-collector driver with a
48 mA current sinking capability.
Transmit receive 2; controls
the direction for EOL This input is TTL compatible.
T/R2
Interface Clear; IEEEGPIB bus
control line. This is a TTL compatible Schmitt-trigger when
used for input and a threestate driver capable of sinking
48 mA current when used for
output.
24
I/O
is recognized by the 8292.
This input is TTL compatible.
Not Ready For Data; processor
GPI8 bus handshake contiOl
line; used to indicate the con·
dition of readiness of device(s)
to accept data. This pin is TTL
compatible.
REN*
IFC*
Symbol
Function
ATN*
7-180
2
23
Attention Out; processor
GPIB bus control line; used by
the 8292 for ATN control of
the IEEE bus during "take
control synchronously" operations. A low on this input
causes ATN to be asserted if
CIC indicates that this 8292 is
in charge. ATNO is a TTL compatible input.
o
11
Attention In; processor GPIB
bus control line; used by the
8292 to monitor the ATN line.
This output is TTL compatible.
o
4
Attention; processor GPIB
bus control live; used by the
8292 to monitor the ATN line.
This output is TTL compatible.
I/O
19
Attention; IEEE GPIB bus control line; used by a controller
to specify how data on the
010 signal lines are to be interpreted and which devices
must respond to data. When
used as an output, this pin is a
three-state driver capable of
sinking 48 rnA current. As an
input, it is a TTL compatible
Schmitt-trigger.
I/O
7
End or Identify 2; processor
GPIB bus control line; used in
conjunction with ATN by the
active controller (the 8292) to
execute a polling sequence.
This pin is TTL compatible.
8293
Symbol
EOI·
I/O
Pin No.
I/O
3
I/O
15
MODE 3 PIN DESCRIPTION
Function
Symbol
End or Identify; processor
GPIB bus control line; used by
a talker to indicate the end of
a multiple byte transfer se·
quence. This pin is TTL com·
patible.
I/O
Pin No.
TiR1
Transmit receive 1; controls
the direction for DAV and the
010 lines. If T/R1 is high, then
all these lines are sending
information to the IEEE GPIB
lines. This input is TTL compatible.
End or Identify; IEEE GPIB bus
control line; used by a talker
to indicate the end of a multiple byte transfer sequence or,
by a controller in Conjunction
with ATN, to execute a polling
sequence. Whel'l an output,
this pin can sink 48 mA current. When an input, it is a TTL
compatible Schmitt-trigger.
3
4
Attention Out; processor
GPIB control line; used by the
8292 during "take control synchronously" operations. This
pin is TTL compatible.
2
Interface Clean Latched; used
to make DAV received after the
system controller asserts IFC.
This input is TTL compatible.
I/O
24
Data Valid; processor GPIB
handshake control line; used
to indicate the condition
(availability and validity) of information on the 010 signals.
This pin is TTL compatible.
I/O
21
Data Valid; IEEE GPIB handshake control line. When an
input, this pin is a TTL compatible Schmitt-trigger. When
DAV· is an output, it can sink
48 mA.
I/O
25,23,
10,9,
8,7,
6, 5
Data Inp~t/Output; processor
GPIB bus data lines; used to
carry message and data bytes
in a bit-parallel byte-serial
form controlled by the three
handshake signals. These
lines are TTL compatible.
I/O
22,19,
18,17,
16, 15,
13, 12
Data Input/Output; IEEE GPIB
bus data lines. They are TTL
compatible Schmitt-triggers
when used for input and can
sink 48 mA when used for output.
OPTA
OPTS
DAV
TiRl
0102 1 - - - - - - + - 1
0 103 1 - - - - - - + - 1
DAV·
0104 1 - - - - - - + - 1
010 5 1 - - - - - - + - 1
0106 ...------+~
OIOS ~-----+-t
0101·0108·
EOi
ATN
Figure 6. Talker/Listener/Controller Data
Configuration
7-181
End of Sequence and Attention; processor GPIB control
lines. These two control lines
are ANDed together to determine whether all the transceivers in the 8293 are pushpull or open-collector. When
both signals are low (true),
then the controller is performi ng a parallel poll and the
transceivers are all opencollector. These inputs are
TTL compatible.
23
MODE3
010 1 1 - - - - - - + - 1
Function
8293
25
23
10
9
8
- 12
DO
Di01
- 13
01
0102
~ 02
0103
- 1516
03
0104
04
Di05
05
0106
17
-
TO
MICROPROCESSOR
INTERFACE
8291
--.!!. 06
....!! 07
2 cs
2 AD
-
10
--.!.!.
-
3
0107
0108
OAV
T/Rl
WR
ATN
INT
EOI
CLOCK
T/R2
~ RESET
NOAC
2
-2
OREO
NRFO
OACK
SRO
GPIB TRIGGER OUTPUT" -2.. TRIG
REN
IFC
7
~
~
6
30
5
31
24
32
1
33
4
34
3
8293
0101
0101·
0102
0102·
DT03
0103·
0104
0104·
0105
0105·
0106
0106·
0107
0107·
0108
0108·
OAV
OAV·
T/Rl
OPTA
ATN
OPTB
-1922
-17
I-18
16
15
-1312
-21
TO
IEEE·488
BUS
E- Vee
26
GNO
,.---- EOI
35
MODEl
36
1
26
39
3
2
8293
EOI· ~
EOI
~ ATN
38
1
37
2
27
10
25
9
I
24
8
6
5
ATN·
~
NOAC
NOAC·
NRFO
NRFO·
.E...
T/Rl
T/R2
SRO·
REN
REN·
,..!.!..
IFC
Figure 7. 8291 and 8293 System Configuration
7-182
TO
IEEE·488
BUS
r-!!..
SRO
MOOEO
• = GPIB BUS TRANSCEIVER
18
IFC·
r-!!..
OPTA
~
GNO
OPTB
~
GNO
8293
TO MICROPROCESSOR
~
~~
t-~
15
16
17
18
19
21
22
23
9
10
4
TO
MICROPROCESSOR
6
7
8
3
11
DO
-0101
28
25
01
-
29
23
30
10
31
9
32
8
33
7
0102
02
0103
03
0104
04
05
0105
06
0106
07
RSO
0107
8291
0108
RS1
TlR1
RS2
Flo
OAV
WR
EOI
RESET
ATN
OREO
SRO
OACK
IFC
Cs
NOAC
CLOCK
NRFO
INT
TlR2
GPIB
TRIGGER
OUTPUT
5
REN
TRIG
34
6
35
5
1
1
36
24
39
3
26
4
0101"
0102
0102"
0103
0103"
0104
0104"
0105
0105"
rE-
~
~
~
~
~
0107" ~
Dl08'- ~
0106"
0106
0107
8293
0108
TO
IEEE·488
BUS
Tlih
OAV
OAV"
~
EOI
ATN
27
24
38
37
.....--2.!..
2
.-!.
12-1-1-
~ Vee
ATNO
OPTA
IFCL
OPTB ~ Vee
MODE 3
..E..
DO
OAV
,E.
' - I - .-!.. T/R1
~ 01
~ 02
~ 03
16
17
18
19
9
8
10
~
4
6
32
MICROPROCESSOR
TO
0101
I
33
35
36
11
OSCILLATOR
OUTPUT
Vee~
~
~3
15·25 pF
±r
4
10
9
04
2
05
06
SRO
07
REN
AO
RD
WR
RESET
-
8292
IFC
ATNO
COUNT
-EOl2
Cs
ATNI
TCI
21
8
38
6
23
5
29
23
39
3
34
7
22
11
ATN
-NOAC
18
NDAC I - -
NFRO
NRFO
~
T/R2
SRO
SRO"
REN
REN"
8293
IFC
ATNO
TO
IEEE·488
BUS
12
IFC" I - ATN"
EOI"
EOI
~
~
~
~
EOl2
ATNI
SPI
OBFI
IBFI
SYNC
IFCL
X,
X2
CIC
CLTH
SYC
1
25
31
24
27
21
24
22
Lr
SYSTEM
CONTROLLER
0FF
SWITCH
IFCL
CIC
CLTH
OPTA
~ GNO
SYC·
OPTB
~ Vee
MOOE2
ON
1.
Figure 8. 8291,8292, and 8293 System Configuration
7-183
" = GPIB BUS TRANSCEIVER
8293
Absolute Maximum Ratings·
Ambient Temperature Under Bias ......... 0 °C to 70°C
Storage Temperature ............. - 65°C to + 150°C
Voltage on any Pin with
Respect to Ground ................. - 1.0V to + 7V
Power Dissipation .......................... 1 Watt
'COMMENT: Stresses above those listed under "Abso/ute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functlona! operation of the device at these or any orne;
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. and Operating Characteristics
TA=O°C to 70°C; VCC= 5.0V ± 10%; GND= OV
SYMBOL
LIMITS
PARAMETER
MIN.
V IL1
Input Low Voltage (GPIB Bus Pins)
VIL2
Input Low Voltage (Option Pins)
TYP.
-0.1
UNIT
TEST CONDITIONS
MAX.
0.8
V
0.1
V
0.8
V
V IL3
Input Low Voltage (All Others)
V IH1
Input High Voltage (GPIB Bus Pins)
2.0
VIH2
Input High Voltage (Option Pins)
4.5
V IH 3
Input High Voltage (All Others)
2.0
VOL1
Output Low Voltage (GPIB Bus Pins)
0.5
V
VOL2
Output Low Voltage (All Others)
0.5
V
IOL= 16 mA
VOH1
Output High Voltage (GPIB Bus Pi,ns)
2.4
V
IOH= -5.2 mA
VOH2
Output High Voltage (All Others)
2.4
V
IOH= -400 IJA
VIH4
Receiver Input Hysteresis
400
600
VIT
.
High to Low
Receiver Input Threshold Low to High
0.8
1.0
1.6
IU1
Low Input Load Current (GPIB Bus Pins)
-3.2
IU2
V
5.5
V
V
IOL=48 mA
mV
2.0
V
0.0
mA
Low Input Load Current (All Others)
10
IJA
VIL=0.8V
Ipo
Bus Power Down Leakage Current
10
IJA
Vcc= OV
Icc
Power Supply Current
100
mA
MAX.
UNIT
5
10
pF
V IN = Vee
10
20
pF
VouT=Vee
V IL=0.8V
Capacitance
SYMBOL
PARAMETER
CIN
Input Capacitance
C OUT
Output Capacitance
MIN.
7·184
TYP.
TEST CONDITIONS
8293
A.C. Characteristics
TA=O°C to 70°C; Vcc =5.0V ± 10%; GND=OV
SYMBOL
PARAMETER
TYP.*
MAX.
UNITS
tpLH1
Driver Propagation Delay (Low to High)
20
35
ns
t pHL1
Driver Propagation Delay (High to Low)
17
30
ns
tpLH2
Receiver Propagation Delay (Low to High)
22
35
ns
tpH L2
Receiver Propagation Delay (High to Low)
18
30
ns
t PHZ1
Driver Enable Delay (High to 3·State)
20
35
ns
t pZH1
Driver Enable Delay (3·State to High)
15
30
ns
t pLZ1
Driver Enable Delay (Low to 3·State)
20
35
ns
tpZL1
Driver Enable Delay (3·State to Low)
15
30
ns
t PHZ2
Receiver Enable Delay (High to 3·State)
25
40
ns
t pZH2
Receiver Enable Delay (3·State to High)
20
35
ns
tpLZ2
Receiver Enable Delay (Low to 3·State)
25
40
ns
tpZL2
Receiver Enable Delay (3·State to Low)
20
35
ns
"Typical @ TA = 25°C.
6.0
4.0
2.0
I
<"
.§.
I-
z
,.- " .
-2.0
'"a:a:
-4.0
U
-6.0
III
j
I
I
fii 40 r - - - - vcc ~ 5.0 v-+--~r:::::1~~~::::~:::1
g
.
TA=25°C
~
~
w
~
J
~
o
>
~
NON·SHADED AREA
CONFORMS TO
PARAGRAPH 3.5.3 OF
IEEE STANDARD
488 ·1978
Vcc=5.0V
-8.0
-10
-12
-14
-4.0
-2.0
-0
VBUS,
3.0 1 - - - + - - + - - + - - + - - + - - - + - + - - + - - - /
!:i
I
:;)
II)
:;)
~
--
5.0 , . - - - - , - - - , - - - , - - - , - - - , - - - " T " " " - - r - - - - .
I
2.0
4.0
2.0 r--+--+--+--f--+--~f---+----I
Q.
I-
:;)
~ 1.01---+--+--+--+--+----+-+--+---/
~
6.0
U
BUS VOLTAGE (VOLTS)
1~
1~
2.0
VI, INPUT VOLTAGE (VOLTS)
Figure 10. Typical Receiver Hysteresis Characteristics
Figure 9. Typical Bus Load Line
7·185
8293
OUTPUT LOADING TEST CIRCUITS
I
TO SCOPE
(OUTPUT)
TO SCOPE
(OUTPUT)
+2.3V
+s.OV
240Q
38.3Q
DATA
BUS
C,
IN916
OR EQUIV.
fOp,
CL INCLUDES JIG AND PROBE CAPACITANCE
Figure 11. Data Input to Bus Output (Driver)
TO SCOPE
(OUTPUT)
CL INCLUDES JIG AND PROBE CAPACITANCE
Figure 12. Bus Input to Data Output (Receiver)
TO SCOPE
(OUTPUT)
1.1V
s.OV
280Q
BUS
DATA
(tPHZ1. tPZH1)
(tpHZ2. IpZH2)
f
f
3 KQ
480Q
CL INCLUDES JIG AND PROBE CAPACITANCE
Figure 13. Send/Receive Input to Bus Output (Driver)
(tpLZ2· tPZL2)
CL INCLUDES JIG AND PROBE CAPACITANCE
Figure 14. Send/Receive Input to Data Output (Receiver)
7~186
8293
8293 WAVEFORMS
tRISE = tFALL '" 5 ns
DUTY CYCLE 50%
=
3.0V
1.5V
INPUT
1.5V
OV
tpLHl
OUTPUT
(DRIVER PROP. DELAY)
FIGURE 11 LOAD
2.0V
tpLH2
OUTPUT
(RECEIVER PROP. DELAY)
FIGURE 12 LOAD
1.5V
tPZH1
OUTPUT
(DRIVER ENABLE DELAY
WITH INPUT HIGH)
FIGURE 13 LOAD
I----------voH------+_----~
2.0V
VZ== 1.0V
tPZL1
OUTPUT
(DRIVER ENABLE DELAY
WITH INPUT LOW)
FIGURE 13 LOAD
OUTPUT
(RECEIVER ENABLE DELAY
WITH INPUT HIGH)
FIGURE 14 LOAD
OUTPUT
(RECEIVER ENABLE DELAY
WITH INPUT LOW)
FIGURE 14 LOAD
VZ== 1.13V
--
O.SV
I~---------VOL------+---~~
tPZH2
~--------VOH------+---~~
Inur
1.5V
I""
t:-
1.5V
'-------VOL------------.;;lIj.10%
7·187
OV
5V
8294
DATA ENCRYPTION UNIT
• Certified by National Bureau of
Standards
• 7·Bit User Output Port
• Single 5V ± 100/0 Power Supply
• SO Byte/Sec Data Conversion Rate
• Peripheral to MCS·S6™, MCS·S5™,
MCS·SOTM and MCS·48™ Processors
• 64·Bit Data Encryption Using 56·Bit
Key
• Implements Federal Information
Processing Data Encryption Standard
• DMA Interface
• 3 Interrupt Outputs to Aid in Loading
and Unloading Data
• Encrypt and Decrypt Modes Available
DESCRIPTION
The Intel@ 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt
64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard.
The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit cipher words. The operation
is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the 8294; however, the 56-bit key is user-defined and may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294 in 8-bit bytes by way of the system data
bus. A DMA interface and three interrupt outputs are available to minimize software overhead associated with data
transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel to achieve effective system
conversion rates which are virtually any multiple of 80 bytes/second. The 8294 also has a 7-bit TTL compatible output
port for user-specified functions.
Because the 8294 implements the NBS encrypti'on algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.
PIN
CONFIGURATION
Xl
X2
RESET
NC
cs
AD
AO
WR
02
03
VCC
NC
BLOCK DIAGRAM
DATA
BUS
ORQ
SRQ
OAV
NC
P6
P5
P4
P3
VOO
NC
NC
NC
Ao
SRO
OAY
CCMP
Po'Ps
"m~
SYNC
X,
X2
+5Y-POWER-GNO--
7-188
TIMING
INTERNAL
BUS
002308
inter
8295
DOT MATRIX PRINTER CONTROLLER
• Programmable Print Intensity
• Interfaces Dot Matrix Printers to
MCS-4S™, MCS-SOISS™, MCS-S6™
Systems
• Single or Double Width Printing
• 40 Character Buffer On Chip
• Serial or Parallel Communication with
Host
• Programmable Multiple Line Feeds
• DMA Transfer Capability
• 3 Tabulations
• Programmable Character Density (10 or
12 Chararcters/lnch)
• 2 General Purpose Outputs
The Intel@ 8295 Dot Matrix Printer Controller provides an interface for microprocessors to the LRC 7040 Series dot
matrix impact printers. It may also be used as an interface to other similar printers.
The chip may be used in a serial or parallel communication mode with the host processor. In parallel mode, data
transfers are based on polling, interrupts, or DMA. Furthermore, it provides internal buffering of up to 40 characters
and contains a 7 x 7 matrix character generator accommodating 64 ASCII characters.
PIN
CONFIGURATION
BLOCK DIAGRAM
INTERNAL
BUS
7-189
002318
8295
PIN DESCRIPTION
Name
110 Pin#
iiO Pin;;
Descripiion
Paper feed input switch.
HOME
39
2
3
Inputs for a crystal to set internal
oscillator frequency. For proper
operation use 6 MHz crystal.
Home input switch, used by the
8295 to detect that the print head
is in the home position.
DACK/SIN
38
4
Reset input, active low. After
reset the 8295 will be set for 12
characters/inch single width
printing, solenoid strobe at 320
msec.
In the parallel mode used as DMA
acknowledgement; in the serial
mode, used as input for data.
PFEED
XTAL1
XTAL2
Name
Description
NC
5
No connection or tied high.
CS
6
Chip select input used to enable
the RD and WR inputs except during DMA.
GND
7
This pin must be tied to ground.
RD
8
Read input which enables the
master CPU to read data and
status. In the serial mode this pin
must be tied to Vee.
DRQ/CTS
0
37
In the parallel mode used as DMA
request output pin to indicate to
the 8257 that a DMA transfer is requested; in the serial mode used
as clear-to-send signal.
IRQ/SER
o
36
In parallel mode it is an interrupt
request input to the master CPU;
in serial mode it should be
strapped to Vss.
MOT
o
o
35
Main motor drive, active low.
34
Solenoid strobe output. Used to
determine duration of solenoids
activation.
o
STB
Vee
9
+ 5 volt power input: + 5V ± 10%.
WR
10
Write input which enables
master CPU to write data
commands to the 8295. In
serial mode this pin must be
to Vss.
the
and
the
tied
33
32
31
30
29
28
27
Solenoid drive outputs; active
low.
26
+ 5V power input (+ 5V ± 10%).
Low power standby pin.
25
No connection.
24
23
General purpose output pins.
22
Top of form input, used to sense
top of form signal for type T
printer.
21
Paper feed motor drive, active
low.
SYNC
o
11
2.5 '"'s clock output. Can be used
as a strobe for external circuitry.
Do
D1
D2
I/O
Three-state bidirectional data bus
buffer lines used to interface the
8295 to the host processor in the
parallel mode. In the serial mode
Do- D2 sets up the baud rate.
GND
12
13
14
15
16
17
18
19
20
Vee
40
+ 5 volt power input: + 5V ± 10%.
D3
D4
D5
D6
D7
NC
GP1
GP2
o
o
TOF
This pin must be tied to ground.
o
7-190
002316
8295
FUNCTIONAL DESCRIPTION
The 8295 interfaces microcomputers to the LRC 7040
Series dot matrix impact printers, and to other similar
printers. It provides internal buffering of up to 40 characters. Printing begins automatically when the buffer is
full or when a carriage return character is received. It
provides a modified 7x7 matrix character generator. The
character set includes 64 ASCII characters.
Communication between the 8295 and the host processor can be implemented in either a serial or parallel
mode. The parallel mode allows for character transfers
into the buffer via DMA cycles. The serial mode features
selectable data rates from 110 to 4800 baud.
The 8295 also offers two general purpose output pins
which can be set or cleared by the host processor. They
can be used with various printers to implement such
functions as ribbon color selection, enabling form
release solenoid, and reverse document feed.
COMMAND SUMMARY
Hex Code
Description
00
Set GP1. This command brings the GP1 pin
to a logic high state. After power on it is
automatically set high.
Hex Code
09
Description
Tab character.
OA
Line feed.
Multiple Line Feed; must be followed by a
byte specifying the number of line feeds.
01
Set GP2. Same as the above but for GP2.
OB
02
Clear GP1. Sets GP1 pin to logic low state,
inverse of command 00.
OC
03
Clear GP2. Same as above but for GP2. Inverse command 01.
Top of Form. Enables the line feed output
until the Top of Form input is activated.
00
04
Software Reset. This is a pacify command.
This command is not effective immediately
after commands requiring a parameter, as
the Reset command will be interpreted as a
parameter.
Carriage Return. Signifies end of a line and
enables the printer to start printing.
OE
Set Tab #1, followed by tab position byte.
OF
Set Tab #2, followed by tab position byte.
Should be greater than Tab #1.
10
Set Tab #3, followed by tab position byte.
Should be greater than Tab #2.
05
Print 10 characterslin. density.
06
Print 12 characterslin. density.
07
Print double width characters. This command prints characters at twice the normal
width, that is, at either 17 or 20 characters
per line.
11
Print Head Home on Right. On some
printers the print head home position is on
the right. This command would enable normal left to right printing with such printers.
08
Enable DMA mode; must be followed by
two bytes specifying the number of data
characters to be fetched. Least significant
byte accepted first.
12
Set Strobe Width; must be followed by
strobe width selection byte. This command
adjusts the duration of the strobe activation.
PROGRAMMABLE PRINTING OPTIONS
07-03
02
01
DO
Solenoid On
(mlcrosec)
x
x
x
x
x
x
x
x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
200
240
280
320
360
400
440
480
CHARACTER DENSITY
The character density is programmable at 10 or 12 characterslinch (32 or 40 characterslline). The 8295 is automatically set to 12 characterslinch at power-up. Invoking
the Print Double-Width command halves the character
density (5 or 6 characterslinch). The 10 charlin or 12
char/in command must be re-issued to cancel the
Double-Width mode. Different character density modes
may not be mixed within a single line of printing.
PRINT INTENSITY
The intensity of the printed characters is determined by
the amount of time during which the solenoid is on. This
on-time is programmable via the Set Strobe-Width command. A byte following' this command sets the solenoid
on-time according to Table 1. Note that only the three
least significant bits of this byte are important.
1
0
1
0
1
0
1
Table 1.
TABULATIONS
Up to three tabulation positions may be specified with
the 8295. The column position of 'each tabulation is
selected by issuing the Set Tab commands, each fol-
7-191
002318
8295
the 8257 DMA controller without further CPU intervention. Figure 2 shows a block diagram of the 8295 in DMA
mode.
lowed by a byte specifying the column. The tab positions will then remain valid until new Set Tab commands
are issued.
Sending a tab character (09H) wiii automaticaiiy fiii the
character buffer with blanks up to the next tab position.
The character sent immediately after the tab character
will thus be stored and printed at that position.
CPU TO 8295 INTERFACE
Communication between the CPU and the 8295 may
take place in either a serial or parallel mode. However,
the selection of modes is inherent in the system hardware; it is not software programmable. Thus, the two
modes cannot be mixed in a single 8295 application.
PARALLEL INTERFACE
Two internal registers on the 8295 are addressable by
the CPU: one for input, one for output. The following
table describes how these registers are accessed.
DONE
RD
WR CS
100
010
Register
Figure 1. Host to 8295 Protocol Flowchart
Input Data Register
Output Status Register
8257
Input Data Register-Data written to this register is
interpreted in one of two ways, depending on how the
data is coded.
DMA
' - - - - -.. '1 CONTROLLER
DACKx
DROx
1. A command to be executed (OXH or lXH).
2. A character to be stored in the character buffer for
printing (2XH, 3XH, 4XH, or 5XH). See the character
set, Table 2.
OPTIONAL
Output Status Register-8295 status is available in this
register at all times.
I/)
::;,
ID
::IE
....w
I/)
>
I/)
STATUS BIT:
FUNCTION:
PA
DE
X,
X2
cs
DRO
AD
DACK
WR
REID
MOT
IBF
PFM
8295
PA-Parameter Required; PA = 1 indicates that a command requiring a parameter has been received. After the
necessary parameters have been received by the 8295,
the PA flag is cleared.
D7
DO
57
PRINTER
IRO
DE-DMA Enabled; DE = 1 whenever the 8295 is in DMA
mode. Upon completion of the required DMA transfers,
the DE flag is cleared.
PFEED
HOME
ISF-Input Buffer Full; IBF = 1 whenever data is written
to the Input Data Register. No data should be written to
the 8295 when I BF = 1.
Figure 2. Parallel System Interface
Data transferred in the DMA mode may be either commands or characters or a mixture of both. The procedure
is as follows:
A flow chart describing communication with the 8295 is
shown in Figure 1.
The interrupt request output (IRQ, Pin 36) is available on
the 8295 for interrupt driven systems. This output is
asserted true whenever the 8295 is ready to receive data.
To improve bus efficiency and CPU overhead, data may
be transferred from main memory to the 8295 via DMA
cycles. Sending the Enable DMA command (08H) activates the DMA channel of the 8295. This command must
be followed by two bytes specifying the length of the
data string to be transferred (least significant byte first).
The 8295 will then assert the required DMA requests to
1. Set up the 8257 DMA controller channel by sending a
starting address and a block length.
2. Set up the 8295 by issuing the "Enable DMA" command (08H) followed by two bytes specifying the
block length (least significant byte first).
The DMA enabled flag (DE) will be true until the
assigned data transfer is completed. Upon completion
of the transfer, the flag is cleared and the interrupt request (IRQ) signal is asserted. The 8295 then returns to
the non-DMA mode of operation.
7-192
oo231B
8295
SERIAL INTERFACE
+5
The 8295 may be hardware programmed to operate in
a serial mode of communication. By connecting the
IRQ/SER pin (pin 36) to logic zero, the serial mode is
enabled immediately upon power-up. The serial Baud
rate is also hardware programmable; by strapping pins,
14, 13, and 12 according to Table 2, the rate is selected.
CS, RD, and WR must be strapped as shown in Figure 3.
STB
Sf
58
Pin 14
Pin 13
Pin 12
Baud Rate
55
a
a
a
a
a
a
a
110
150
300
600
1200
2400
4800
4800
54
1
a
1
1
1
a
a
1
1
a
1
a
8295
TO
SOLENOID
DRIVERS
53
52
51
I
MOT
TO MOTOR
DRIVERS
PFM
Table 2.
The serial data format is shown in Figure 3. The CPU
should wait for a clear to send signal (CTS) from the
8295 before sending data.
Figure 4. 8295 To Printer Solenoid Interface
OSCILLATOR AND TIMING CIRCUITS
The 8295's internal timing generation is controlled by a
self-contained oscillator and timing circuit. A 6 MHz
crystal is used to derive the basic oscillator frequency.
The resident timing circuit consists of an oscillator, a
state counter and a cycle counter as illustrated in Figure
5. The recommended crystal connection is shown in
Figure 6.
+5
PRINTER
PFEED 1 - - - - - - - ;
HOME I------~
8251A TXD
USART CTS
-1
t----
SIN
CTS
SER
SYNC
OUTPUT
(2.5 "lee)
SERIAL
INPUT
STOP
BIT
INTERNAL TIMING
Figure 5. Oscillator Configuration
Figure 3. Serial Interface to UART (8251A)
2 XTAL1
8295 TO PRINTER INTERFACE
The strobe output signal of the 8295 determines the
duration of the solenoid outputs, which hold the data to
the printer. These solenoid outputs cannot drive the
printer solenoids directly. They should be buffered
through solenoid drivers as shown in Figure 4. Recommended solenoid and motor driver circuits may be found
in the printer manufacturer's interface guide.
1-8 MHz
~
8295
.--_~~3 XTAL2
2OPF~
Figure 6. Recommended Crystal Connection
7-193
OO231e
8295
8295 CHARACTER SET
Hex Code
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
Print Char.
space
#
$
%
&
+
Hex Code
Print Char.
Hex Code
Print Char.
Hex Code
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
a
40
41
42
43
44
45
46
47
48
49
5A
4B
4C
4D
4E
4F
@
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
1
2
3
4
5
6
7
8
9
<
>
?
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
Print Char.
P
Q
R
S
T
U
V
W
X
y
Z
[
\
1
t
ABSOLUTE MAXIMUM RATINGS·
a
Ambient Temperature Under Bias ......... °C to 70 °C
Storage Temperature ............... - 65 ° to + 150 °C
Voltage on Any Pin With
Respect to Ground ................... 0.5V to + 7V
Power Dissipation ......................... 1.5 Watt
'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
T A = O°C to 70°C, Vee = Voo= +5V ± 10%, Vss= OV
Symbol
Parameter
Limits
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage (All
Except X1, X2, RESEl)
-0.5
0.8
V
VIL1
Input Low Voltage (X h X2,
RESEl)
-0.5
0.6
V
VIH
Input High Voltage (All
Except X1, X2, RESEl)
Input High Voltage (X 1, X2,
RESEl)
2.2
Vee
V
3.8
Vee
V
VIH1
Test Conditions
VOL
Output Low Voltage (Do- D 7)
0.45
V
IOL=2.0mA
VOl1
Output Low Voltage (All
Other Outputs)
0.45
V
10L= 1.6mA
VOH
Output High Voltage (00- 0 7)
2.4
V
10H= -400",A
VOH1
Output High Voltage (All
Other Outputs)
2.4
V
10H= -50",A
IlL
Input Leakage Current
(RD, WR, CS, A~
±10
!lA
Vss ~ VIN ~ Vee
loz
Output Leakage Current
(Do-D7' High Z State)
±10
!lA
Vss+O.45~ VIN~ Vee
mA
100
Voo Supply Current
5
15
100+ lee
Total Supply Current
60
125
mA
lu
Low Input Load Current
(Pins 24, 27-38)
0.5
mA
VIL=0.8V
IU1
Low Input Load Current
(RESET)
0.2
mA
VIL= 0.8V
7-194
002318
8295
A.C. CHARACTERISTICS
TA=O°C to 70°C, Vcc=Voo= +5V± 10%, VSS=OV
DBB READ
Symbol
Parameter
Min.
+
Max.
Unit
0
ns
0
ns
Test Conditions
tAR
CS, Ao Setup to RD
tRA
CS, Ao Hold After RD
tRR
RD Pulse Width
tAD
CS, Ao to Data Out Delay
225
ns
C L = 150 pF
tRO
RD
225
ns
C L = 150 pF
tOF
+to Data Out Delay
RD t to Data Float Delay
tCY
Cycle Time
t
ns
250
100
ns
2.5
15
",s
Min.
Max.
Unit
DBB WRITE
Symbol
tAW
Parameter
CS,
Ao Setup to WR +
0
ns
tWA
CS, Ao Hold After WR t
0
ns
tww
WR Pulse Width
250
ns
tow
Data Setup to WR t
150
ns
two
Data Hold to WR t
0
ns
Test Conditions
DMA AND INTERRUPT TIMING
Symbol
tAcc
Parameter
Min.
DACK Setup to Control
0
0
Max.
Unit
ns
tCAC
DACK Hold After Control
tCRQ
WR to ORO Cleared
200
ns
tACO
DACK to Data Val id
225
ns
7-195
Test Conditions
ns
002318
8295
WAVEFORMS
1. READ
CS OR
OPERATIC~J
-
OUTPUT BUFFER REGISTER.
).
Ao
K
-'AR,
-
'RR
· /- 'RA--
~
'-'OF1
\
--'RO--
'AD
DATA OUs
(OUTPUT)
-=j
(READ CONTROL)
J)
-------------(j--DATAVALD---=v--------------
2. WRITE OPERATION -
CS OR
(SYSTEM'S
ADDRESS BUS)
AO
-
INPUT BUFFER REGISTER.
~
~--"'11---'ww-------O.~-_'WA-+"-----
(SYSTEM'S
ADDRESS BUS)
- _- _- _
WR
'{
(WRITE CONTROL)
~------------'-Ow-------- - - 'WO
) _ - DATA VALID
DATA BUS _ _ _ _ _ _ DATA
_ _ _ _ _ _- - J
(INPUn
MAY CHANGE
--K
DATA
~_ _ _ _ _ _ _ MAY
_ _CHANGE
_ _ _ _ _ _ _ _ __ _
DMA AND INTERRUPT TIMING
,
1\
IcAC-
f--'ACC-
~
II
~
J
}
ORO
'CRO
D:~:
-'ACO
_________________
-
~---- --------V_AL_ID--------------J)(~-------------__
7-196
002318
8295
PRINTER INTERFACE TIMING AND WAVEFORMS
MOTOR DRIVE
\
V
)
,
I
HOME
....
\
J
SOLENOID DATA
)
K
SOLENOID STROBE
-SDS
J
I-- PDH--
Symbol
r--'~~U
Parameter
.(\.
-
MHH
~
Typical
POH
Print delay from
home inactive
Sos
Solenoid data
setup time before
strobe active
25,..s
SHS
Solenoid data
hold after strobe
inactive
>1 ms
MHA
Motor hold time
after home active
PSP
PFEED setup time
after PFM active
58 ms
PHP
PFM hold time
after PFEED active
9.75 ms
--
7·197
1.8 ms
3.2 ms
002318
inter
2ii4A
1024 X 4 BIT STATIC RAM
2114AL-1
2114AL-2
2114AL-3
2114AL-4
2114A-4
2114A-5
100
120
150
200
200
250
40
40
40
40
70
70
Max. Access Time (ns)
Max. Current (mA)
•
•
Low Power, High Speed
•
•
•
Static Memory - No Clock
• orCompletely
Timing Strobe Required
HMOS Technology
•
Identical Cycle and Access Times
•
Single +5V Supply ±10%
•
High Density 18 Pin Package
Directly TTL Compatible: All Inputs
and Outputs
Common Data Input and Output Using
Three-State Outputs
2114 Upgrade
The Intel@! 2114A is a 409~bit static Random Access Memory organized as 1024 words by 4-bits using HMOS, a high performance MOS technology. It uses fully DC stable (static) circuitry throughout, in both the array and the decoding, therefore it
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114A is designed for memory applications where the high performance and high reliability of HMOS, low cost, large bit
storage, and simple interfacing are important design objectives. The 2114A is placed in an 18-pin package for the highest
possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.
PIN CONFIGURATION
~
vee
LOGIC SYMBOL
BLOCK DIAGRAM
A3
Ao
A4
As
A7
A,
A4
As
A2
A3
Ag
110,
As
Ao
A
~
1/°2
A4
110,
A,
I/~
~
1/°3
CS
GND
@
--=-vee
--ill-GND
®
'1)
.-
6@
ROW
SELECT
MEMORY ARRAY
64 ROWS
64COLUMNS
A7
As
As
~
0)
@
1/°3
A6
IIO,@
A7
1/°4
As
WE
Ag
1/°4
WE
CS
PIN NAMES
ADDRESS INPUTS
Vee POWER (+5V)
wr
WRITE ENABLE
GND GROUND
CS
CHIP SELECT
AO-A9
o
=
PIN NUMBERS
I/O, -1/04 DATA INPUT/OUTPUT
INTEL CORPORA TlON ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
c INTEL CORPORATION_ 1977. 1979
7-198
DECEMBER. 1979
2114A FAMILY
ABSOLUTE MAXIMUM RATINGS*
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation ofthe device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure is not implied. Exposure to absolute maximum rating
conditions for extended' periods may affect device reliability.
Temperature Under Bias .................. -10°C to BO°C
Storage Temperature .......... , ......... -65°C to 150°C
Voltage on any Pin
With Respect to Ground ..... , ............ -3.5V to +7V
Power Dissipation ................................ , 1.0W
D.C. Output Current ................................ 5mA
D.C. AND OPERATING CHARACTERISTICS
TA = O°C to 70°C,
SYMBOL
Vee
= 5V
± 10%, unless otherwise noted.
PARAMETER
2114AL-1/L-2/L-3/L-4
Min. Typ.lll Max.
2114A-4/-5
Min.
Typ.lll
Max.
UNIT
CONDITIONS
III
Input Load Current
(All Input Pins)
10
10
J1A
VIN = 0 to 5.5V
llLOI
I/O Leakage Current
10
10
J1A
CS = V 1H
Icc
Power Supply Current
70
mA
VI/O
50
40
25
VIL
Input Low Voltage
-3.0
0.8
-3.0
0.8
V
VIH
Input High Voltage
2.0
6.0
2.0
6.0
V
10L
Output Low Current
2.1
9.0
10H
Output High Current
-1.0
-2.5
105[21
Output Short Circu it
Current
2.1
9.0
-1.0
-2.5
40
40
mA
VOL = O.4V
mA
VOH = 2.4V
mA
NOTE: 1. Typical values are for T A = 25° C and Vee = 5.0V.
2. Duration not to exceed 30 seconds.
CAPACITANCE
TA
= 25°C, f = 1.0 MHz
SYMBOL
CONDITIONS
MAX
UNIT
ClIO
Input/Output Capacitance
5
pF
Vila = OV
CIN
Input Capacitance
5
pF
VIN = OV
NOTE:
TEST
This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST
Input Pulse Levels ................................................... O.B Volt to 2.0 Volt
Input Rise and Fall Times ...................................................... 10 nsec
Input and Output Timing Levels ................................................ 1.5 Volts
Output Load ............................................... 1 TTL Gate and C L = 100 pF
7-199
= GND
to VCC
Vee = max, 11/0 = 0 mA,
T A = O°C
2114A FAMILY
A.C. CHARACTERISTICS
READ CYCLE
TA
=O°C to 70°C, Vee =5V ± 10%, unless otherwise noted,
[1]
2114AL-1
PARAMETER
SYMBOL
tRe
Read Cycle Time
tA
Access Time
teo
Chip Selection to Output Valid
tex
Chip Selection to Output Active
toTO
Output 3-state from Deselection
tOHA
Output Hold from
Address Change
WRITE CYCLE
Min.
Max.
Min.
Min.
Max.
120
100
100
10
Max.
10
35
ns
250
ns
70
85
ns
ns
10
10
50
ns
60
ns
15
15
15
UNIT
Max.
200
40
15
Min.
250
200
70
10
15
Min.
150
70
30
Max.
150
120
70
2114A-4/L-4 2114A-5
2114AL-3
2114AL-2
[2]
2114AL-1
SYMBOL
PARAMETER
Min.
2114AL-2
Max.
Min.
2114AL-3
Max.
Min.
2114A-4/L-4 2114A-5
Max.
Min.
Max.
Min.
Max.
UNIT
Write Cycle Time
100
120
150
200
250
ns
tw
Write Time
75
75
90
120
135
ns
tWR
Write Release Time
0
0
0
0
0
tOTW
Output 3-state from Write
tow
Data to Write Time Overlap
70
70
90
tOH
Data Hold from Write Time
0
0
0
twe
30
40
35
ns
50
ns
60
120
135
ns
0
0
ns
NOTES:
1. A Read occurs during the overlap of a low CS and a high WE.
2. A Write occurs during the overlap of a low CS and a low WE. tw is measured from the latter of CS or WE going low to the earlier of CS or WE going high.
WAVEFORMS
READ CYCLE@
WRITE CYCLE
twc
1-------tRc------+I
1------tA-------i
ADDRESS
ADDRE~
__
~----------------------~--'I~------
i--twA-
,\\' l\\\2
l// / / / / / / / / / / /,
tw
® ~\\
-tOT~
NOTES:
DOUT
3. WE is high for a Read Cycle.
4. If the CS low transition occurs simultaneously with the WE low
transition, the output buffers remain in a high impedance state.
5. "WE must be high during all address transitions.
,tow
D,N
7-200
~
I
tOH
'V
V'
2114A FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
1.2
1.2
1.1
1.1
--
1.0
:f.
Cl
0.9
«
0.8
w
N
::;
~
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
1.0
:f.
fil
N
0.9
«
0.8
~
II:
oZ
0
0.7
0.5
4.50
5.00
o
5.50
5.25
1.3
«
~
II:
1.0
//
60
80
1. 1
/"
1.2
u
S?
V
:f.
1.1
40
1.2
!
w
20
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
1.4
N
0.7
0.5
4.75
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
:::;
~f-""
0.6
0.6
Cl
~
::;
II:
Z
---
r--
//
fil
N
./"
::;
----r----- ----
1.0
0.9
«
~
II:
o
0.8
Z
0
z
I
r---
0.7
0.9
0.8
0.6
0.7
0.5
100
150
200
250
300
350
o
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
80
30
60
20
40
10
~
60
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
40
~
40
20
20
~
o
o
o
7·201
//
/
o
/
V
/
80
1024 X 4 BIT STATIC RAM
I
2142-2
200
525
Max. Access Time (ns)
I
Max. Power Dissipation (mw)
2142-3
300
525
High Density 20 Pin Package
• Access
Selections From 200-450ns
• I dentlcalTime
Cycle and Access Times
• Low Operating
• .1mW/Blt TypicalPower Dissipation
• Single +5V Supply
2142
450
525
2142L3
300
370
2142L2
200
370
2142L
450
370
Clock or Timing Strobe Required
• No
Completely Static Memory
• Directly
TTL Compatible: All Inputs
• and Outputs
Common Data Input and Output Using
• Three-State
Outputs
The Intel@ 2142 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The 2142 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing
are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
The 2142 is placed in a 2o-pin package. Two Chip Selects (CS1 and CS2) are provided for easy and flexible selection of
individual packages when outputs are OR-tied. An Output Disable is included for direct control of the output buffers.
The 2142 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection
against contamination permitting the use of low cost plastic packaging.
PIN CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
A3
As
Vcc
AO
A5
A7
A,
A4
As
A2
Ag
A3
Ao
A7
I/O,
A5
AS
1/0 2
A6
1/03
A7
1/04
AS
MEMORY ARRAY
64 ROWS
64 COLUMNS
@)
A4
A,
ROW
SELECT
G)
00
A2
-----0
®
A6
1/02
CS2
@
A4
I/O,
A5
A3
®
@
@)
1/03
1/0,
cs,
1/04
1/02
WE
GNO
1/0 3
1/0 4
PIN NAMES
DO
OUTPUT DISABLE
WE
WRITE ENABLE
Vcc
POWER (+5V)
CSi, CS2
AO-A9
CHIP SELECT
ADDRESS INPUTS
GND
GROUND
1/01-1104
DATA INPUT/OUTPUT
o
7-202
= PIN NUMBERS
@
Vcc
0 GND
2142 FAMILY
ABSOLUTE MAXIMUM RATINGS*
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias . . . . . . . . . . . . _10°C to a
WE is high for a Read Cycle.
tow- f.tOH
® WE must be high during all address transitions.
7-204
2142 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
1.2
1.2
-- ---
1. 1
1.0
I'--..
1.1
0.9
0.8
:!
fa
N
:::;
O.9
<{
~
0.8
~
0.7
0.7
0.6
0.6
0.5
0.5
4.50
5.25
5.00
4.75
--------
1.0
r---
5.50
o
~
60
20
80
Vee (V)
NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
1.2
1.1
1.0
l..--
~
~
-
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
-
1.2
1.1
1.0
~
:!
fa
faN
0.9
N
:::;
<{
::0;
a:
0
z
0.9
~
:::;
<(
0.8
::0;
a:
0
z
0.7
0.6
0.8
~ "'-.
0.7
- --
0.6
0.5
100
200
300
400
500
20
600
60
CL (pF)
OUTPUT SOURCE CURRENT
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
VS. OUTPUT VOLTAGE
40
40
30
30
20
10
""
o
o
\
1...
~
20
.E
10
'"~
o
/
/
V
./
/
o
VOH (V)
VOL IV)
7-205
80
2148
1024 x 4 BIT STATIC RAM
2148·3 2148 2148·6
Max. Access Time (ns)
Max. Active Current (rnA)
Max. Standby Current (rnA)
• HMOS Technology
Static Memory
• Completely
- No Clock or Timing Strobe
55
125
125
85
125
30
30
30
70
• Automatic Power· Down
• High Density 18·Pin Package
•
Required
• Equal Access and Cycle Times
• Single + 5 V Supply
Directly TTL Compatible
- All Inputs and Outputs
• Common Data Input and Output
• Three·State Output
The Intel® 2148 is a 4096·bit static Random Access Memory organized as 1024 words by 4 bits using HMOS, a high·
performance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high - disabling the 2148 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as CS remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are
disabled.
The 2148 is assembled in an 18-pin package configured with the industry standard 1K x 4 pinout. It is directly TIL
compatible in all respects: inputs, outputs, and a single +5V supply. The data is read out nondestructively and has the
same polarity as the input data.
PIN CONFIGURATION
~VCC
AO
Vcc
A6
BLOCK DIAGRAM
LOGIC SYMBOL
~GND
A1
AS
A7
A4
AS
1/01
A2
A6
A3
Ag
A3
Ao
1/01
A1
1/02
ROW
SELECT
1/02
A7
A4
AS
AS
1/03
A6
A2
1/03
cs
1/04
GND
MEMORY ARRAY
64 ROWS
64 COLUMNS
o
Ag
A7
1104
AS
1101
WE
1102
= PIN NUMBERS
@
@
@
1103
PIN NAMES
Ao-Ag
WE
cs
1/0 1 -1104
Vcc
GND
ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUTIOUTPUT
POWER (+sV)
GROUND
1104
TRUTH TABLE
CS
WE
H
L
L
X
L
H
MODE
1/0
NOT SELECTED HIGH·Z
WRITE
DIN
READ
DOUT
POWER
STANDBY
ACTIVE
ACTIVE
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTel PRODUCT NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
(f
INTEL CORPORATION 1979
7-206
June 1979
2148
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............ -10°Cto +85°C
Storage Temperature .............. - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground ................. -3.5V to + 7V
D.C. Output Current ......................... 20 mA
Power Dissipation ........................... 1.2W
D.C. AND OPERATING CHARACTERISTICS!1)
T A = O°C to + 70 °C, Vee = + 5 V ± 10% unless otherwise noted.
2148, 2148-3, 2148-6
Symbol
III
Min.
Parameter
Input Load Current (All Input Pins)
IILOI
Output Leakage Current
Icc
Operating Current
Typ.!2)
Max.
Unit
0.01
10
iJ. A
Vee = max, V 1N = GND to Vee
0.1
50
iJ. A
CS = V 1H , Vee = max,
VOUT = GND to 4.5V
75
115
mA
TA = 25°C
125
mA
TA = O°C
mA
Vee = min to max, CS = V 1H
Vee = GND to Veemin,
CS = Lower of Vee or V 1H min
ISB
Standby Current
12
30
Ipo!3)
Peak Power-On Current
25
50
mA
V 1L
Input Low Voltage
-3.0
0.8
V
V 1H
Input High Voltage
2.0
6.0
V
VOL
Output Low Voltage
VOH
Output High Voltage
los
Output Short Circuit Current
Test Conditions
0.4
2.4
V
V
TBD
TBD
mA
-
Vee = max, CS = V 1L ,
Outputs Open
10L =8mA
10H = -2.0mA
VOUT = GND to Vee
Notes:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. Typical limits are at Vee = 5V, TA = +25°C, and Load A.
3. A pull·up resistor to Vee on the CS input is required to keep the device deselected; otherwise, power·on current approaches Icc
active.
+5V
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
10 nsec
Input and Output Timing
Reference Levels
1.5 Volts
Output Load
DOUT - - - . . . . - - -..
+5V
30 pF
(INCLUDING
SCOPE AND
JIG)
330n
See Load A.
CAPACITANCE
5100
DOUT - - - . . . . - - -..
3300
(4)
LoadA.
TA = 25 °C, f = 1.0 MHz
Symbol
510n
GND to 3.0 Volts
Parameter
Max.
Unit
Conditions
C IN
Input Capacitance
5
pF
V 1N =OV
COUT
Output Capacitance
7
pF
VOUT=OV
Load B.
Note 4. This parameter is sampled and not 100% tested.
7-207
5pF
2148
A.C. CHARACTERISTICS
=
T A O°C to + 70°C, Vcc
= +5V ± 10% unless otherwise noted.
READ CYCLE
2148·3
Symbol
Min.
Parameter
Max.
tRC
Read Cycle Time
tAA
Address Access Time
t ACS1
Chip Select Access Time
55
t ACS2
Chip Select Access Time
65
tOH
Output Hold from Address Change
5
t
55
2148·6
Max.
70
Chip Selection Output in Low Z
10
0
tpu
Chip Selection to Power Up Time
0
tpD
Chip Deselectio,n to Power Down Time
0
Unit
Test
Conditions
85
ns
70
85
ns
Note 1
80
95
ns
Note 2
5
ns
10
40
0
30
Max.
ns
70
10
40
Min.
85
5
Chip Deselection to Output in High Z
Ll
Min.
55
t Hz[8[
[8[
2148
40
0
0
ns
Note 7
ns
Note 7
ns
30
30
ns
WAVEFORMS
READ CYCLE NO.1 [3
4)
~1 -l
*
'00,," =::r-----~-
f--
_"_1"_"
PREVIOUS DATA VALID
READ CYCLE NO.
'Re
---~~-- ----~--~1--
X X *=======================================
2[3 S)
1--------
tRC
--------
~-------.I
I
~-----
DATA VALID
Notes:
1. Chip deselected for greater than 55 ns prior to CS transition low.
2. Chip deselected for a finite time that is less than 55 ns prior to CS transition low. (If the deselect time is 0 ns, the chip is by
definition selected and access occurs according to Read Cycle No.1.)
3. WE is high for Read Cycles.
4. Device is continuously selected, CS
=V1L.
5. Addresses valid prior to or coincident with CS transition low.
6. At any given temperature and voltage condition, tHZ max. is less than tLl min. both for a given device and from device to device.
7. Transition is measured ± 500mV from high impedance voltage with Load B. This parameter is sampled and not 100% tested.
7-208
2148
A.C. CHARACTERISTICS (continued)
WRITE CYCLE
2148
2148·3
Symbol
Parameter
Min.
Max.
Min.
Max.
2148·6
Min.
Max.
Unit
twe
Write Cycle Time
55
70
85
ns
tew
Chip Selection to End of Write
50
65
80
ns
tAW
Address Valid to End of Write
50
65
80
ns
0
0
0
ns
40
50
60
ns
5
5
5
ns
25
25
30
ns
tAS
Address Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End of Write
tOH
Data Hold Time
5
twz
Write Enabled to Output in High Z
0
tow
Output Active from End of Write
0
5
15
5
0
25
0
0
0
Test
Conditions
ns
30
ns
Note 2
ns
Note 2
WAVEFORMS
WRITE CYCLE #1 (WE CONTROLLED)
-----twc
'ew
CSllI
'AW
--~
~--
twP
\\1
WE
1
---t [.~:~."" -+'."-~
J)
_____________D_AT_A_U_ND_EF_'N_ED__________
"X,,~.~-~.--
WRITE CYCLE #2 (CS CONTROLLED)
~------
_
'we
----------1
____________________________
~~L----H-'GH-'-MP-ED-A-NC-E------------DATA UNDEFINED
,.,-
Notes: 1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. Transition is measured ± 500 mV from high impedance voltage with Load B. This parameter is sampled and not 100% tested.
2148H
1024 x 4·81T STATIC RAM
2148H-3
55
180
30
Maximum Access Time (ns)
Maximum Active Current (mA)
Maximum Standby Current (mA)
•
Automatic Power· Down
•
Industry Standard 2114A and 2148
Pinout
•
•
HMOS II Technology
•
Completely Static Memory--No Clock
or Timing Strobe Required
•
•
•
•
•
•
Functionally Compatible to the 2148
2148HL
70
125
20
2148HL-3
55
125
20
2148H
70
180
30
Equal Access and Cycle Times
High Density 18·Pin Package
Common Data Input and Output
Three·State Output
Single + 5V Supply
Fast Chip Select Access 2149H
Available
The Intel® 2148H is a 4096-bit static Random Access Memory organized as 1024 words by 4 bits using HMOS
II, a high performance MOS technology. It uses a uniquely innovative design approach which provides .the
ease-of-use features associated with non-clocked static memories and the reduced standby power
dissipation associated with clocked static memories. To the user this means low standby power dissipation
without the need for clocks, address setup and hold times, or reduced data rates due to cycle times that are
longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high-disabling the 2148H-the
part automatically reduces its power requirements and remains in this low power standby mode as long as
CS remains high. This device feature results in system power savings as great as 85% in larger systems,
where the majority of devices are disabled. A non-power-down companion, the 2149H, is available to provide
a fast chip select access time for speed critical applications.
The 2148H is assembled in an 18-pin package configured with the industry standard 1K x 4 pinout. It is
directly TTL compatible in all respects: inputs, outputs, and a single + 5V supply. The data is read out nondestructively and has the same polarity as the input data.
-
AO
.- A,
101 -
A,
A,
-
@
--Vee
~GNO
ROW
SELECT
-
A,
-
A,
-
Ab
10) -
MEMORY ARRAY
- A,
64 ROWS
64 COLUMNS
- A,
WE
o=
?
P'N NUMBERS
PIN NAMES
Ao-A,
WE
Ci
UO,-U04
Vee
GND
ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT/OUTPUT
POWER (+SV)
GROUND
TRUTH TABLE
Figure 1_
2148H Block Diagram
CS
WE
H
L
L
X
L
H
MODE
110
NOT SELECTED HIGH·Z
WRITE
DIN
READ
DOUT
Figure 2.
POWER
STANDBY
ACTIVE
ACTIVE
2148H Pin Diagram
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied
'INTEL CORPORATION, 1980
7-210
AFN2148H/PDS/0980
2148H FAMILY
• COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............ - 10°C to + 85°C
Storage Temperature ............. - 65°C to + 150°C
Voltage on Any Pin with
Respect to Ground ................. - 3.5V to + 7V
D.C. Continuous Output Current ............. 20 mA
Power Dissipation ............................ 1.2W
D.C. AN D OPERATING CHARACTERISTICS"I
TA = 0 °C to + 70°C, Vee = +5V ± 10% unless otherwise noted.
2148HL/HL-3
2148H/H-3
Parameter
Max.
Unit
III
Input Load Current (All Input Pins)
0.01
10
0.01
10
f.1A
Vee
Output Leakage Current
0.1
50
0.1
50
f.1A
CS = VIH, Vee = max,
VOUT = GND to 4.5V
lee
Operating Current
120
180
90
125
mA
Vee = max, CS
Outputs Open
ISB
Standby Current
15
30
10
20
mA
Vee
30
mA
Vec = GND to Vcc min,
CS = Lower of Vcc or VIH min
0.8
V
Ipo
(31
Peak Power-On Current
-3.0
VIH
Input High Voltage
2.1
VOL
Output Low Voltage
VOH
Output High Voltage
los
Output Short Circuit Current
Max.
25
Input Low Voltage
VIL
Typ
(21
Symbol
IILol
Min.
(21
Min.
50
Typ
15
0.8
-3.0
6.0
2.1
0.4
2.4
±200
±150
= max,
=
6.0
V
V
10L
=8
V
10H
=
±200
mA
VOUT
VIN
= GND to Vee
= VIL,
min to max, CS
0.4
2.4
±150
Test Conditions
= VIH
mA
-4.0 mA
=
GND to Vcc
Notes:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute. Typical
thermal resistance values of the package at maximum temperatures are:
8JA (@ 400 fPM air flow) = 40° C/W
8JA (still air) = 70° C/W
8JC = 25° C/W
2. Typical limits are at Vcc = 5V, TA = +25°C, and Load A.
3. A pull-up resistor to Vcc on the CS input is required to keep the deviee deselected during power-on. Otherwise, power-on current
approaches Icc active.
+5V
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
5 nsec
Input and Output Timing
Reference Levels
Output Load
+5V
DOUT - - - - . - - -..
30 pF
(INCLUDING
SCOPE AND
JIG)
2550
1.5 Volts
See Load A.
CAPACITANCE
TA
4800
GND to 3.0 Volts
4800
D O U T - - -.......- -....
2550
(4)
Load A.
=25°C, f =1.0 MHz
Symbol
Parameter
Max.
Unit
CIN
Address/Control Capacitance
5
pF
VIN
CIO
Input/Output Capacitance
7
pF
VOUT
Note 4. This parameter Is sampled and not 100% tested.
Conditions
=
OV
=
OV
Load B.
5pF
2148H FAMILY
A.C. CHARACTERISTICS
TA
=O°C to
+ 70°C, Vcc
= +5V ± 10%
unless otherwise noted.
READ CYCLE
2148H-3/HL-3
Parameter
Symbol
Min.
Max.
2148H/HL
Min.
Max.
Read Cycle Time
55
tAA
Address Access Time
55
Test
Conditions
ns
70
tAC
Unit
70
ns
tACS1
Chip Select Access Time
55
70
ns
Note 1
tACS2
Chip Select Access Time
65
80
ns
Note 2
tOH
Output Hold from Address Change
5
tLZ
Chip Selection Output in Low Z
20
tHZ
Chip Deselection to Output in High Z
0
tpu
Chip Selection to Power Up Time
0
tPD
Chip Deselection to Power Down Time
ns
5
20
20
0
20
ns
Note 6
ns
Note 6
ns
0
30
30
ns
WAVEFORMS
READ CYCLE NO. 113.• 1
~ ~~~~~~~C--~----~~~~
• •, • •
~~
DATA OUT
'O"~ "I
PREVIOUS DATA vAlID! XX*=============DA=T=A=VA=L-I_D================
READ CYCLE NO. 213&1
tRc--------------------~l
--_l-
cs - (
14-----t.cs - - - - - - - - - 1
tLz------..i
DATA OUT --+.....;.;.;,,;;;;,.;.;.;;.;...;=..;;.;;..._--(
t
DATA VALID
HIGH
+-_--J IMPEDANCE
1,,-,u....LJi.J ' - - - - - - -_ _ _ _
pur
-J""---------------------
Icc---- Is.------J
Notes:
1. Chip deselected for greater than 55 ns prior to CS transition low.
2. Chip deselected for a finite time that is less than 55 ns prior to CS transition low. (If the deselect time is 0 ns, the chip is
by definition selected and access occurs according to Read Cycle No 1.)
3. WE is high for Read Cycles.
4. Device is continuously selected,
CS
= V 1L .
5. Addresses valid prior to or coincident with CS transition low.
6. Transition is measured ±500mV from high impedance voltage with Load B. This parameter is sampled and not 100%
tested.
2148H FAMILY
A.C. CHARACTERISTICS (continued)
WRITE CYCLE
2148H-3/HL-3
Parameter
Symbol
Min.
Max.
2148H/HL
Min.
Max.
Unit
twe
Write Cycle Time
55
70
ns
tew
Chip Selection to End of Write
50
65
ns
tAW
Address Valid to End of Write
50
65
ns
a
a
ns
40
50
ns
Write Recovery Time
5
5
ns
tow
Data Valid to End of Write
20
25
ns
tOH
Data Hold Time
Write Enabled to Output in High Z
tow
Output Active from End of Write
a
a
a
ns
twz
a
a
a
tAS
Address Setup Time
twp
Write Pulse Width
tWR
20
25
Test
Conditions
ns
Note 2
ns
Note 2
WAVEFORMS
WRITE CYCLE No. 1 (WE CONTROLLED)
1---------ADDRESS
twc---------1·1
____~-----------------------------------JI~--------
CS[1]
DATA IN
DATAOUT ______~~~~~~__~~=-------_t---rl-----------
WRITE CYCLE No. 2 (CS CONTROLLED)
Iwe
ADDRESS
-
IASI
~.
lew
lAW
,\\ \\\ \\\\\\\\'\
-IWR-
Iwp
tlillIiiiiI III I I III!
, t::.IDW-_IDW~1
DATA IN
I
DATA IN VALID )(
f---Iwz
DATA OUT ------DA-T-A-U-N-DE-F-IN-E-O-..,;:.:..::=1...___H_IG_H_I_M_P_ED_A_N_C_E_____________
Notes:
1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. Transition is measured ±500mV from high impedance voltage with Load B. This parameter is sampled and not
100% tested.
inter
2ii8 FAMilY
16,384 x 1 BIT DYNAMIC RAM
Maximum Access Time (ns)
Read, Write Cycle (ns)
Read-Modify-Write Cycle (ns)
• Single +5V Supply, ±10% Tolerance
• HMOS Technology
• Low Power: 150 mW Max. Operating
11 mW Max. Standby
• Low Voo Current Transients
All Inputs, Including Clocks,
• TTL
Compatible
2118-3
100
235
285
2118-4
120
270
320
2118-7
150
320
410
CAS Controlled Output is
• Three-State,
TTL Compatible
RAS
Only
Refresh
• Refresh Cycles Required
• 128
Every 2ms
Page Mode and Hidden
• Refresh
Capability
Allows
Negative
• VIL min = -2V Overshoot
The Intel® 2118 is a 16,384 word by 1-bit Dynamic MOS RAM designed to operate from a single +5V power supply. The
2118 is fabricated using HMOS - a production proven process for high performance, high reliability, and high storage
density.
The 2118 uses a single transistor dynamic storage cell and advanced dynamic circuitry to achieve high speed with low
power dissipation. The circuit design minimizes the current transients typical of dynamic RAM operation. These low
current transients contribute to the high noise immunity of the 2118 in a system environment.
Multiplexing the 14 addreas bits into the 7 address input pins allows the 2118 to be packaged in the industry standard
16-pin DIP. The two 7-bit address words are latched into the 2118 by the two TTL clocks, Row Address Strobe (RAS) and
Column Address Strobe (CAS). Non-critical timing requirements for RAS and CAS allow use of the address multiplexing
technique while maintaining high performance.
The 2118 three-state output is controlled by CAS, independent of RAS. After a valid read or read-modify-write cycle, data
is latched on the output by holding CAS low. The data out pin is returned to the high impedance state by returning CAS to
a high state. The 2118 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to
execute RAS-only refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing RASonly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of Ao through
A6 during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is
addressed.
PIN
CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
_Voo
64 x 128 CELL
MEMORY ARRAY
_Vss
OUTPUT
BUFFER
AO·A6
ADDRESS INPUTS
CAS
COLUMN ADDRESS STROBE
D,N
DATA IN
OOUT
DATA OUT
WE
WRITE ENABLE
~
RAS
ROW ADDRESS STROBE
WE
Voo
POWER "5Vl
~N
Vss
GROUND
DOUT
2118 FAMILY
ABSOLUTE MAXIMUM RATINGS·
'COMMENT:
AmbientTemperatureUnderBias ... -10°Cto+80°C
Storage Temperature ............. -65°Cto+150°C
Voltage on Any Pin Relative to Vss ............ 7.5V
Data Out Current ............................ 50mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. EXPQsure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS[1]
TA
= O°C to
70°C, Voo
Symbol
= 5V ±10%,
VSS
= OV,
unless otherwise noted.
Limits
Min. Typ,!2] Max. Unit Test Conditions
Parameter
Notes
IILlI
Input Load Current (any input)
0.1
10
J.l.A VIN=VSS to Voo
IILOI
Output Leakage Current for
High Impedance State
0.1
10
Chip Deselected: CAS at VIH,
J.l.A Your = a to 5.5V
1001
Voo Supply Current, Standby
1.2
2
mA CAS and RAS at VIH
1002
Voo Supply Current, Operating
23
27
mA 2118-3, tRC = tRCMIN
3
21
25
mA 2118-4, tRC = tRCMIN
3
19
23
mA 2118-7, tRC = tRCMIN
3
16
18
mA 2118-3, tRC = tRCMIN
3
14
16
mA 2118-4, tRC = tRCMIN
3
12
14
mA 2118-7, tRC = tRCMIN
3
2
4
mA CAS at VIL. RAS at VIH
3
1003
Voo Supply Current; RAS-Only
Cycle
1005
Voo Supply Current, Standby,
Output Enabled
VIL
Input Low Voltage (all inputs)
-2.0
0.8
V
VIH
Input High Voltage (all inputs)
2.4
7.0
V
VOL
Output Low Voltage
0.4
V
IOL
VOH
Output High Voltage
V
IOH
2.4
NOTES:
1. All voltages referenced to V55·
2. Typical values are for TA = 25°C and nominal supply voltages.
3. 100 is dependent on output loading when the device output is selected. Specified
= 4.2mA
= -5mA
100 MAX
is measured with the output open.
CAPACITANCE!1)
TA
= 25°C,
Symbol
Voo
= 5V ±10%,
VSS
= OV,
unless otherwise noted.
Parameter
Typ.
Max.
Unit
CI1
Address, Data In
3
5
pF
CI2
RAS, CAS, WE, Data Out
4
7
pF
NOTES:
I. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation:
C = Iolt with J.V equal to 3 volts and power supplies at nominal levels.
J.V
2118 FAMILY
A.C. CHARACTERISTICS[1,2,3)
TA
= O°C to
70°C, VDD = 5V ±10%, VSS = OV, unless otherwise noted,
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
2118-3
Symbol
Min,
2118-7
2118-4
Max,
Unit
tAAC
Access Time From RAS
100
120
150
ns
4,5
tCAC
Access Time From CAS
55
65
80
ns
4,5,6
tAEF
Time Between Refresh
2
ms
tAP
RAS Precharge Time
tCPN
tCRP
CAS Precharge Time I non·page cycles l
Parameter
Mu,
Min,
2
Mu.
Min,
2
110
120
135
ns
50
55
70
CAS to RAS Precharge Time
0
0
0
ns
ns
tRCO
RAS to CAS Delay Time
25
tASH
RAS Hold Time
70
85
105
ns
25
45
25
55
70
ns
tCSH
CAS Hold Time
100
120
165
ns
tASA
Row Address Set-Up Time
0
0
0
ns
tAAH
Row Address Hold Time
15
15
15
ns
tASC
Column Address Set-Up Time
0
0
0
ns
tCAH
Column Address Hold Time
15
15
20
ns
60
70
90
tAR
Column Address Hold Time, to RAS
IT
Transition Time (Rise and Fall!
3
50
3
50
3
50
ns
tOFF
Output euffer Turn Off Delay
0
45
0
50
0
60
ns
Notel
7
ns
8
READ AND REFRESH CYCLES
tAC
Random Read Cycle Time
235
tAAS
RAS Pulse Width
115
10000
140
10000
175
10000
ns
tCAS
CAS Pulse Width
55
10000
65
10000
95
10000
ns
tACS
Read Command Set-Up Time
0
0
0
ns
tRCH
Read Command Hold Time
0
0
0
ns
270
ns
320
WRITE CYCLE
tAC
Random Write Cycle Time
235
tAAS
RAS Pulse Width
115
10000
140
10000
175
10000
ns
tCAS
CAS Pulse Width
55
10000
65
10000
95
10000
ns
twcs
Write Command Set-Up Time
tWCH
270
ns
320
0
0
0
ns
Write Command Hold Time
25
30
45
ns
tWCR
Write Command Hold Time, to RAS
70
85
115
ns
twp
Write Command Pulse Width
25
30
50
ns
tAWL
Write Command to RAS Lead Time
60
65
110
ns
tCWL
Write Command to CAS Lead Time
45
50
100
ns
tos
Data-In Set-Up Time
0
0
0
ns
tOH
Data-In Hold Time
25
30
45
ns
tOHA
Data-In Hold Time, to RAS
70
85
115'
ns
9
READ-MODIFY-WRITE CYCLE
410
tAWC
Read-Modify-Write Cycle Time
285
tAAW
RMW Cycle RAS Pulse Width
165
10000
320
190
10000
265
10000
ns
tCRW
RMW Cycle CAS Pulse Width
105
10000
120
10000
185
10000
ns
tAwO
RAS to WE Delay
100
120
150
ns
9
tcwo
CAS to WE Delay
55
65
80
ns
9
ns
NOTES
7 tACO Imax liS specified as a reference pOint only. "tACO IS less
All voltages referenced to Vss
Eight cycles are required after power-up or prolonged periods
Igreater than 2msl of AAS inactivity before proper device
operation IS achieved Any 8 cycles which perform refresh are
adequate for thiS purpose
A C Characteristics assume tT' = 5ns
Assume that tACO'" tACO Imax I. If tACO IS greater than tACO
Imax I then tAAC will Increase by the amount that tACO exceeds
tRCO
Load
(max I
= 2 TTL
than tRCD Imax ! access time IS tRAC. If tRCO IS greater than tRCO
Imax ) access time IS tRCD ~ tCAG
IT
IS
measured between
,>
loads and 100pF
Assumes tRCD ? tRCD (max)
7
VIH IMln I
and
VtL Imax I
twcs. tcwD and tAwD are specified as reference POints only If
twcs c twcs Imln I the cycle IS an early write cycle and the data
out pin Will remain high Impedance throughout the entire
cycle If tCW') tcwD Imln.1 and tAwD ~ tAwD Imln I. the cycle IS
a read-modlfy-wrlte cycle and the data out will contain the data
read from the selected address If neither of the above
conditions IS satisfied. the condition of the data out IS
') ~ c:. indeterminate
2118 FAMILY
WAVEFORMS
-
READ CY CLE
V,H
RAS
l-tAP~
031\10
V ,L
V ,H
~
tACO
I
V ,L
- tcP
NI
tCSH
e.f--
®tcAP-1
CAS
I
tAC
t AAS
tASH
CD
1\\\\l0
tCAS
.11
tAA
f----o-
tASA
"iH
ADDRESSES
V ,L
I--
-tAAH-1
~
ROW
ADDRESS
'2
K
tAse
~
I--tCAH-
K
COLUMN
ADDRESS
H
1--. t ACS
V ,H
WE
t ACH
\
d!I
V ,L
0
tCAC
tAAC
HIGH
VOL
IMPEDANCE
DOUT
!--tOFF-
CD
VO H
o
WRITE CY CLE
VALID
~D_A_T.....
A_O_U_T_ _ _ _..Jf
t AC
tAAS
l - t AP -
8 l\@
®tCAP
-1
tASA
,H
ADDRESSES
V ,L
---t--
){tJ)0
l-tCPN-1
tRCO
(i)
- t RAH
L
VI
tCSH
\+t--
J
V
®
---1
ROW
ADDRESS
t RSH - - - - tCAS
K\,\l\~
)t
tAR
t--
tASC-
XX
--tCAH-
K
COLUMN
ADDRESS
t AWL
V,H
WE
V,L
i
'cWl
_ t WCH -
-twcs-
twp
tWCA
e.-@t os -
V ,H
D'N
V'L
}
CD
_ t OH @ -
JK
CD
tOHR
~~~--------------~I~M~~~~~:~N~C~E-------------------------------------------------------------------NOTES:
1,2. V ,H MIN AND V ,l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND Val MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF D oUT '
5. tOFF IS MEASURED TO lOUT'; lila I·
6. tos AND tOH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
7. tACH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST
8. tCAP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE Il.e., FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RASI.
7-217
2118 FAMILY
WAVEFORMS
READ·MODIFY·WRITE CYCLE
J
tRwe
tRRW
(1,
'==-'RP_:I
f.~'RCo-:---
(8)ICRP-j
'~
il)
I---'CPN-i
'cRW
~\\\ (2)
f----IAR
H'RAH
tAS~tw"
tASR-t--V ,H
ADDRESSES Vil
)( (1)
"\
'7
1\2)
AD~~~SS
}(
- - t RWl -
1-
X ;g~~~~
(2)
---t
teAH
K
,,-,wp-k
tRWD
'cWO
IRcsrl
r;;'~
,3)
'I
®'OS
t-~loH-=®
XI})
tCAC-t
tRAe
H
DATA IN
VALID
CD
K
-
I
fiJI
HIGH
IMPEDANCE
l
CWl- - -
0~
VALID
DATA OUT
tOFF
"l;®
-¥
RAS·ONL Y REFRESH CYCLE
.J
IRC
tRAS
V,H
RAS
(i)
Vil
V,H
CAS
Vil
I
_II=='RP-:I
~
I"l 1)
---'
IASRt-
V,H
ADDRESSES
Vil
X~
"'"
-'RAH!
ROW
ADDRESS
](
VOH
HIGH
Val
IMPEDANCE
DOUT
1\
f--'CRP®
HIDDEN REFRESH CYCLE
(For Hidden Refresh Operation order 2118-3 56445,2118-456446 or 2118-7 56447)
ADDRESSES
V,H
Vil
V,H
WE
Vil
VOH
"",Jr.."i"...C----------V-A-lI~~i-tD-AT-A-------------:!I~.,.0;..·0_"
_ _ __
DOUl
VOL
NOTES:
1,2. V ,H MIN AND V ,l MAX ARE REFERENCE LEVELS FOR MEASURING T1MING OF INPUT SIGNALS.
3,4. V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOllT '
5. IOFF IS MEASURED TO lOUT" IllO I·
6. 'DS AND IDH ARE REFERENCED TO CAS OR WE, WHICHEVER OCCURS LAST.
7.IRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST.
S.ICRP REOUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDEDBY A CASONLY CYCLE Ii .•. , FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS).
7·218
2118 FAMILY
D.C.
AND
A.C.
CHARACTERISTICS, PAGE
MODE[7.8.11j
TA = O°C to 70°C, VDD = 5V ±10%, Vss = OV, unless otherwise noted.
For Page Mode Operation order 2118-3 56329, 2118-4 56330, or 2118-7 56331.
2118-3
S6329
Symbol
tpc
Parameter
Min.
125
175
60
115
55
Page Mode Read or Write Cycle
tpCM
Page Mode Read Modify Write Cycle
tcp
CAS Precharge Time, Page Cycle
tRPM
RAS Pulse Width, Page Mode
tCAS
CAS Pulse Width
1004
Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS
Max.
2118-4
S6330
Min.
Max.
145
200
70
10000 140 10000
10000 65 10000
20
17
2118-7
S6331
Min.
Max.
190
280
85
175 10000
95 10000
15
Unit
Notes
ns
ns
ns
ns
ns
mA
WAVEFORMS
PAGE MODE READ CYCLE
~------------------------------IR~--------------------------------~I~
__ V'HC
RAS
WE
V 1HC
~~--------~------------------------------~~--~,-.~---~~~::-tR-5-H--------~tR'~
+-_J
V'l _ _ _
VOH
DOUT VOl-----------------------~~
NOTES:
1.2. V'H MIN AND V'l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS.
3,4. V OH MIN AND Val MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF D oUT '
5. IOFF IS MEASURED TO lOUT
IILO I.
6.IReH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST
7. ALL VOL TAGES REFERENCED TO Vss
8. AC CHARACTERISTIC ASSUME IT = 5n •.
9. SEE THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER AL TERNATE CONDITIONS.
10. tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE (i.e" FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RASI.
" ALL PREVIOUSLY SPECIFIED A.C. AND D.C. CHARACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (j.e" 2118·3, 56329 WILL OPERATE AS A 2118·31.
7-219
2118 FAMILY
PAGE MODE
WRITE CYCLE
ADDRESSES V
~---------------------------------tRPM--------------------------------~·1
,H
V'L--~~T-~~~~~~~------~---£~~--~~----~------~~--~~~--~~------+r------------
V ,HC
WE
V,L ______
~----~~~--_+----------~~------_+----------~~--_H~------~------~------------
V ,H
D'N
VIL ______
~~~~--------~~----~~----------~~--------,~~~----------~~----------------
PAGE MODE READ-MODIFY-WRITE CYCLE
r-------------------
(j)tCRP
CAS
-------------------
tRPM - - - - - - - - - - - -
1-------------t pcM ------------.-!
t---- 45nsec
Note that if 25nsec ~ tACO ~ 45nsec device access time is
determined by equation 3 and is equal to tAAC. If tRCO >
45nsec access time is determined by equation 4. This
20nsec interval (shown in the tACO inequality in equation
3) in which the falling edge of CAS can occur without
affecting access time is provided to allow for system
timing skew in the generation of CAS.
REFRESH CYCLES
Each of the 128 rows of the 2118 must be refreshed every 2
milliseconds to maintain data. Any memory cycle:
1. Read Cycle
2. Write Cycle (Early Write, Delayed Write or ReadModify-Write)
3. RAS-only Cycle
refreshes the selected row as defined by the low order
(RAS) addresses. Any Write cycle, of course, may change
the state of the selected cell. Using a Read, Write, or ReadModify-Write cycle for refresh is not recommended for
systems which utilize "wire-OR" outputs since output bus
contention will occur.
A RAS-only refresh cycle is the recommended technique
for most applications to provide for data retention. A RASonly refresh cycle maintains the Dour in the high
2118 FAMILY
impedance state with a typical power reduction of 30%
over a Read or Write cycle.
This feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability.
RAS/CAS TIMING
RAS and CAS have minimum pulse widths as defined by
tRAS and teAs respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle, once begun by bringing RAS and/or
CAS low must not be ended or aborted prior to fulfilling
the minimum clock signal pulse widthls I. A new cycle can
not begin until the minimum prechargetime, tRP, has been
met.
DATA OUTPUT OPERATION
The 211'8 Data Output I DOUT I, which has three-state
capability, is controlled by CAS. During CAS high state
I CAS at VIH 1 the output is in the high impedance state. The
following table summarizes the DOUT state for various
types of cycles.
Intel 2118 Data Output Operation
for Various Types of Cycles
Type of Cycle
DOUT State
Read Cycle
Data From Addressed
Memory Cell
HI-Z
HI-Z
HI-Z
Data From Addressed
Memory Cell
Indeterminate
Early Write Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read/Modify/Write Cycle
Delayed Write Cycle
POWER ON
After the application of the Voo supply, or after extended
periods of bias (greater than 2ms) without clocks, the
device must perform a minimum of eight (8) initialization
cycles (any combination of cycles containing a RAS clock
such as RAS-only refresh) prior to normal operation.
The Voo current (100) requirement of the 2118 during
power on is, however, dependent upon the input levels of
RAS and~. If the input levels of these clocks are at VIH
or V oo , whichever is lower, the 100 requirement per device
is 1001 (100 standby). If the input levels for these clocks
are lower than V 1H or Voo the 100 requirement will be
greater than 1001, as shown in Figure 2.
~
E
To
o
HIDDEN REFRESH
An optional feature of the 2118 is that refresh cycles may
be performed while maintaining valid data at the output
pin. This feature is referred to as Hidden Refresh. Hidden Refresh is performed by holding CAS at VIL and
taking RAS high and after a specified precharge period
(tRP)' executing a "RAS-Only" refresh cycle, but with CAS
held low (see Figure 1.)
Voo (VOLTS)
Figure 2. Typical 100 VS Voo during power up.
CAS
. ; . . - - - ((
Dour - - . . .HIGHZ
DATA
>--
~-------'
Figure 1. Hidden Refresh Cycle.
7-224
For large systems, this current requirement for 100 could
be substantially more than that for which the system has
been designed: A system which has been designed,
assuming the majority of devices to be operating in the
refresh/standby mode, may produce sufficient 100
loading such that the power supply may current limit. To
assure that the system will not experience such loading
during power on, a pullup resistor for each clock input to .
Voo to maintain the non-selected current level (1001) for
the power supply is recommended.
inter
2147H
HIGH SPEED 4096 x 1 BIT STATIC RAM.
2147H·2
2147H·3
2147HL·3
2147H
2147HL
35
45
55
55
70
70
Max. Active Current (rnA)
180
180
160
30
30
180
30
125
Max. Standby Current (rnA)
15
20
140
10
2147H·1
Max. Access Time (ns)
•
•
•
•
•
•
•
•
Pinout, Function, and Power Com·
patible to Industry Standard 2147
HMOS II Technology
Completely Static Memory-No Clock
or Timing Strobe Required
Equal Access and Cycle Times
Single + 5V Supply
O.8-2.0V Output Timing Reference
Levels
•
•
•
•
Direct Performance Upgrade for 2147
Automatic Power·Down
High Density 18·Pin Package
Directly TTL Compatible-All Inputs
and Output
Separate Data Input and Output
Three·State Output
The Intel® 2147H is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using
HMOS-II, Intel's next generation high-performance MOS technology. It uses a uniquely innovative design
approach which provides the ease-of-use features associated with non-clocked static memories .and the
reduced stanqby power dissipation associated with clocked static memories. To the user this means low
standby power dissipation without the need for clocks, address setup and hold times,nor reduced data
rates due to cycle times that are longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high-deselecting the 2147H
-the part automatically reduces its power requirements and remains in this low power standby mode as
long as CS remains high. This device feature results in system power savings as great as 85% in larger
systems, where the majority of devices are deselected.
The 2147H is placed in an 18-pin package configured with the industry standard 2147 pinout. It is directly
TTL compatible in all· respects: inputs, output, and a single + 5V supply. The data is read out nondestructively and has the same polarity as the input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
A,
A6
A2
A7
AJ
Aa
A4
Ag
As
~GND
A2
AJ
A4
As
A6 DOUT
A7
As
Ag
A,o
A"
DIN
WE
-Vee
A,
A,o
DOUT
@
Ao
Vee
Ao
BLOCK DIAGRAM
LOG IC SYMBO L
MEMORY ARRAY
64 ROWS
64 COLUMNS
A"
DIN WE CS
@
DIN------f
DOUT
PIN NAMES
AO-A"
WE
CS
D,N
DoUT
ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT
DATA OUTPUT
Vee POWER (+5V)
GND GROUND
TRUTH TABLE
B Wl
H
L
L
X
L
H
MODE
NOT SELECTED
WRITE
READ
OUTPUT
POWER
HIGHZ
HIGHZ
DOUT
STANDBY
ACTIVE
ACTIVE
Intel. Corporation assumes no responsibility for the use of any circuitry other than cirCUitry embodied In an Intel product. No other CIrCUIt patent licenses are Implied
Intel Corporation. 1979. 1980
April. 1980
7-225
2147H
ABSOLUTE MAXIMUM RATINGS*
*COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Temperature Under Bias . . . . . . . . . . . .. - 10 °C to 85°C
Storage Temperature. . . . . . . . . . . .. - 65°C to + 150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . .. - 3.5V to + 7V
Power Dissipation ........................... 1.2W
D.C. Output Current ......................... 20 mA
D.C. AND OPERATING CHARACTERISTICS[1]
(T A = O°C to 70°C, Vee = + 5V ± 10%, unless otherwise noted.)
Symbol
2147H·1, 2, 3
Min. Typ. Max.
Parameter
III
Input Load Current
(All Input Pins)
0.01
Min.
2147HL·3
Typ. Max.
10
0.01
0.1
10
0.1
50
0.1
50
150
100
135
125
mA
15
mA
12
20
7
10
50
mA
25
50
15
30
-3.0
0.8
V
-3.0
0.8
-3.0
2.0
6.0
V
2.0
6.0
2.0
0.4
V
ISB
I po l3]
Standby Current
18
30
6
Peak Power-On Current
35
70
25
V1L
Input Low Voltage
-3.0
0.8
V1H
Input High Voltage
2.0
6.0
VOL
Output Low Voltage
180
0.4
2.4
0.01
100
170
-150
10
/l- A
50
120
Output High Voltage
0.01
2147HL
Typ,l21 Max.
mA
0.1
Operating Current
Output Short Circuit
Current
/l- A
Min.
50
Outut Leakage Current
los
2147H
Typ,l21 Max.
Min.
115
ILO
Icc
VOH
10
Unit
2.4
+ 150 -150
V
+ 150 mA
140
160
0.8
6.0
0.4
0.4
2.4
2.4
-150
+ 150
-150
+ 150
NOTES:
1. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
2. Typical limits are at Vcc =5V, TA = + 25°C, and specified loading.
3. A pull·up resistor to Vcc on the CS input is required to keep the device deselected; otherwise, power·on current approaches Icc
active.
Vee
A.C. TEST CONDITIONS
510U
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Level (2147H-1)
Output Timing Reference Levels
(2147H, H-2, H-3, HL, HL-3)
Output Load
GND to 3.0V
5 ns
1.5V
1.5V
DOUT - - -.......- -...
30 pF
(INCLUDING
SCOPE AND
JIG)
300~~
0.8-2.0V
See Figure 1
Figure 1. Output Load
Vee
CAPACITANCE[4]
Symbol
5101!
(TA=25°C, f= 1.0 MHz)
Parameter
DOUT - - -.......- -....
Max. Unit Conditions
C IN
Input Capacitance
5
pF
VIN = OV
COUT
Output Capacitance
6
pF
VOUT=OV
5 pF
NOTE:
4. This parameter is sampled and not 100% tested.
Figure 2. Output Load for tHZ. tLZ. twz. tow
7-226
2147H
A.C. CHARACTERISTICS
Read Cycle
Symbol
t
RC
(TA
=O°C to 70°C, Vcc = + 5V
2147H·3,
2147H,
2147HL
HL·3
2147H·1
2147H·2
Min. Max. Min. Max. Min. Max. Min. Max.
Parameter
[1]
± 10%, unless otherwise noted.)
Read Cycle Time
35
45
Unit
70
55
ns
tAA
Address Access Time
35
45
55
70
ns
tACS1[8]
Chip Select Access Time
35
45
55
70
ns
tACS2[9]
Chip Select Access Time
35
tOH
Output Hold from Address Change
5
td2,3,7]
Chip Selection to Output in Low Z
5
tHZ[2,3,7]
Chip Deselection to Output in High Z
0
tpu
Chip Selection to Power Up Time
0
t pD
Chip Deselection to Power Down Time
45
0
30
0
20
0
ns
10
30
0
ns
40
ns
0
0
20
ns
80
5
10
5
30
65
5
5
20
ns
30
ns
WAVEFORMS
Read Cycle No.
1[4,5]
tRe
ADDRESS
~(':
----./1\
)\
.
tAA
tOH
XX X ~
PREVIOUS DATA VALID
DATA OUT
Read Cycle No.
DATA VALID
2[4,6]
tRe
~r
l
I\.
.
tACS
-tHZ-
tlZ
DATA OUT
Vee
SUPPL Y
CURRENT
HIGH IMPEDANCE
~XX~
Ice_-~p~1-~
DATA VALID
,
HIGH
J
IMPEDANCE
_ _ _ _r-_tP0==L
50%
50%
158 - - - - -
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage condition, tHZ max. is less than tLZ min. both for a given device and from device to device.
3. Transition is measured ± 500 mV from steady state voltage with specified loading in Figure 2.
4. WE is high for Read Cycles.
5~ Device is continuously selected, CS = V1L .
6. Addresses valid prior to or coincident with CS transition low.
7. This parameter is sampled and not 100% tested.
8. Chip deselected for greater than 55 ns prior to selection.
9. Chip deselected for a finite time that is less than 55 ns prior to selection. If the deselect time is 0 ns, the chip is by definition
selected and access occurs according to Read Cycle NO.1. Applies to 2147H, 2147HL, 2147H-3, and 2147HL·3.
7·227
Intel
2147H
A.C. CHARACTERISTICS (Continued)
Write Cycle
I
I
2147H,
2147H·3,
2147HL
2147H·1
2147H·2
HL·3
Min. Max. Min. Max. Min. Max. Min. Max.
Parameter
Symbol
twe[2]
Write Cycle Time
tew
Chip Selection to End of Write
tAW
Address Valid to El'ld of Write
tAS
Address Setup Time
twp
Write Pulse Width
tWR
Write Recovery Time
tow
Data Valid to End of Write
tOH
twZ[3]
Data Hold Time
Write Enabled to Output in High Z
tow[3]
Output Active from End of Write
WAVEFORMS
Write Cycle No. 1
35
35
35
0
20
0
20
10
0
0
45
45
45
0
25
0
25
10
0
0
20
55
45
45
0
25
10
25
10
0
0
25
25
70
55
55
0
40
15
30
10
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
ns
----------'we
ADDRESS
L
(WE CONTROLLED)[4)
CSI'
I~
tew
~
II
IIII
t AW - -
tAS----j
_twp~
\\
t
I
DATA IN
---tDW-~
~
DATA O U T - - - - - - - D - A - T A - U - N D - E F - I N - E D - - - - -.....
(CS CONTROLLED)[4)
~tOHj
.l
DATA IN VALID
I--- twz ----I
Write Cycle No.2
I----'wo-
Ii
" " ,~,,.~,1-----'<>w
~--------twe---------~
ADDRESS
~-------~w-------~
~+-----'<>w - - - - - - - . . j -
DATA IN
DATA IN VALID
- - - " ' J:J. .-----------HIGH IMPEDANCE
DATA
our
DATA UNDEFINED
NOTES:
1. If CS goes high simultaneously with WE high, the output remains in a high impedance state.
2. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
3. Transition is measured ± 500 mV from steady state voltage with specified loading in Figure 2.
4. CS or WE must be high during address transitions.
7·228
inter
2716
16K (2K x 8) UV ERASABLE PROM
• Fast Access Time
- 350 ns Max. 2716·1
- 390 ns Max. 2716·2
- 450 ns Max. 2716
490 ns Max. 2716·5
- 650 ns Max. 2716·6
• Pin Compatible to Intel@ 2732 EPROM
• Single + 5V Power Supply
• Inputs and Outputs TTL Compatible
during Read and Program
• Simple Programming Requirements
Single Location Programming
- Programs with One 50 ms Pulse
• Low Power Dissipation
525 mW Max. Active Power
- 132 mW Max. Standby Power
• Completely Static
The Intel® 2716 is a 16,384·bit ultraviolet erasable and electric;:ally programmable read·only memory (EPROM). The 2716
operates from a single 5·volt power supply, has a static standby mode, and features fast single address location program·
mingo It makes designing with EPROMs faster, easier and more economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
+5V microprocessors such as Intel's 8085 and 8086. A selected 2716-5 and 2716-6 is available for slower speed applications.
The 2716 is also the first EPROM with a static standby mode which reduces the power dissipation without increasing access
time. The maximum active power dissipation is 525 mW while the maximum standby power dissipation is only 132 mW, a
75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level programming.
No need for high voltage pulsing because all programming controls are handled by TTL signals. Program any location at any
time-either individually, sequentially or at random, with the 2716's single address location programming. Total prog ramming
time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION
MODE SELECTION
2716
~
Ce/PGM
Oe
Vpp
Vec
OUTPUTS
(181
(201
(211
(241
(9·11,13·171
MODE
Read
VIL
VIL
+5
+5
DOUT
Standby
VIH
Don't Care
+5
+5
High Z
Program
Pulsed VIL to VIH
VIH
+25
+5
DIN
Program Verify
VIL
VIL
+25
+5
DOUT
Program Inhibit
VIL
VIH
+25
+5
High Z
BLOCK DIAGRAM
t Refer to 2732
Vcc~
data sheet for
specifications
UATAOUTPUTS
00 01
----
PIN NAMES
ADDRESSES
CHIP ENABLE/PROGRAM
AO-A,O
OUTPUT ENABLE
ADDRESS
INPUTS
OUTPUTS
7·229
AFN-00811A-Ol
2716
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section. ;
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . . . . . -10°C to +80°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +125°C
All Input or Output Voltages with
Respect to Ground . . . . . . . . . . . . . . . +6V to -0.3V
Vpp Supply Voltage with Respect
*COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
rei iabi Iity.
to Ground During Program . . . . . . . . +26.5V to -0.3V
DC and AC Operating Conditions During Read
Temperature Range
2716
2716-1
2716-2
2716-5
2716-6
O°C _ 70°C
O°C _ 70°C
O°C _ 70°C
O°C _ 70°C
O°C _ 70°C
5V ±5%
5V ±10%
5V ±5%
5V±5%
5V±5%
VCC
VCC
VCC
VCC
VCC
VCC Power Supply[1,2)
Vpp Power Supply [2)
READ OPERATION
D.C. and Operating Characteristics
Limits
Parameter
Symbol
Conditions
Unit
Typ.[31
Min.
Max.
III
Input Load Current
10
J1A
VIN = 5.25V
ILO
Output Leakage Current
10
J1A
VOUT = 5.25V
IpP1 [2)
Vpp Current
5
mA
Vpp = 5.25V
'CC1[2)
Vcc Current (Standby)
10
25
mA
CE = VIH, OE = VIL
ICC2[21
V CC Current (Active)
57
100
mA
OE =cr= VIL
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
V c c+l
V
VOL
Output Low Voltage
0.45
V
IOL = 2.1 mA
VO H
Output High Voltage
V
IOH = -400 J1A
2.4
NOTES: 1. VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IpP1.
3. Typical values are for T A = 25°C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
Typical Characteristics
ICC CURRENT
ACCESS TIME
VS.
VS.
TEMPERATURE
CAPACITANCE
70
60 ~
-r--- r--
50
r--- r--~
ICC2 ACTIVE CURRENT
~=Vll
VCC=5V -r---
< 40
!
700
700
600
600
500
500
400
----
Vee = 5V
~ 400
'-'
'-'
~
'-'
!:? 30
300
20
200
ICCI STANDBY CURRENT
~=VIH
VCC=5V~
10
o
ACCESS TIME
vs.
TEMPERATURE
10
20
f.--
200
100
30
40
50
TEMPERATURE I C)
60
o
70
80
-
~
-
f---
-
!----
100
1
I
o
;: 300
100
200
300
400
CllpF)
7-230
500
600
700
800
o
10
20
30
40
50
60
70
80
TEMPERATURE I'C)
AFN-OOB11 A-02
2716
A.C. Characteristics
Limits (ns)
2716
Symbol
Parameter
Min.
2716-1
Max.
Min.
2716-2
Max.
Min.
Max.
2716-5
Min.
Max.
2716-6
Min.
Max.
Test
Conditions
tACC
Address to Output Delay
450
350
390
450
450
CE = OE = VI L
tCE
CE to Output Delay
450
350
390
490
650
QE=VIL
200
CE = V IL
tOE
Output Enable to Output Delay
tOF
Output Enable High to Output Float
0
tOH
Output Hold from Addresses, CE or
OE Whichever Occurred First
0
Capacitance
Symbol
120
100
120
0
120
100
0
0
0
Typ.
160
0
100
0
0
0
100
CE=VIL
CE=OE=V IL
A.C. Test Conditions:
[4] TA= 25°C, f= 1 MHz
Parameter
100
Max.
Unit
Conditions
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: ~20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs 0.8V and 2V
= OV
CIN
Input Capacitance
4
6
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
= OV
A. C. Waveforms [11
ADDRESSES
VALID
ADDRESSES
CE-----------------+--~
teE
6E----------------~~--------~
'-------+-- . . . . . . . . . .
[6J
tDF
-~""""I"""'II"""'I~-
HIGH Z
----........
OUTPUT-------------------------------+-+-. . . .~~
~-
NOTE:
•••••••
HIGH Z
...... .
1. Vce must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to VCC except during programming. The supply current would then be the sum of ICC and IpP1.
3.
4.
5.
6.
Typical values are for TA = 25° C and nominal supply voltages.
This parameter is only sampled and is not 100% tested.
OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC.
tDF is specified from OE or CE, whichever occurs first.
7-231
AFN-OOB11 A-03
2716
TYPICAL 16K EPROM SYSTEM
A8-15 ....... - - -...- - - - - - - - - - - . . . . . . . ,
ADO-7
t-t--......- . .I
8212
ADDRESS
ALE ~"-_ _ _ _""I LATCH
8085
VCC
RD r-r--------------------~
512 X 8
O_C_
PROM
3S04A
CE5
.... N
(1)(1)
101M
CES
(J(J
eE7
• This scheme accomplished by using CE (PD) as the primary decode_ OE (CS) is now controlled by previously unused
signal. RD now controls data on and off the bus by way of OE_
• A selected 2716 is available for systems which require CE access of less than 450 ns for decode network operation_
• The use of a PROM as a decoder allows for:
a) Compatibility with upward (and downward) memory expansion.
b) Easy assignment of ROM memory modules, compatible with PUM modular software concepts.
SK, 16K, 32K, 64K 5V EPROM/ROM FAMILY
PRINTED CIRCUIT BOARD LAYOUT
,
D
D
D
a
D
co . _
_._
_
A'2 0
A B
A11 00--4IOI-4l, • . . . . . - . - . . . _ _ _ _
A,o 0
0.~
.-
..-
A9~.
~~
..:..:... ..
o
...
:..
~------~
~
~
~
"'--
~
'-
~"'--
....
"'--
~....
~
A3 00- - ' "
A2 00- - A, 0 0 - - -...
........
~
Ao ••-------...
..
~
~~
~
~
- ....
........
~
~
'......
:
.................a
GNDOD-••- -. . . .~. . . . . . . . . .-~.~.··~c.'Wi
+50D--.........:~. . . .---~. . . . . . . . . . . . . . .- ...
+
•
COMPONENT SlOE
0 ••••
00 0,0203 CEl
7-232
0 •• 0.
04 0 5 0 6 0 7 eE2
2716
ERASURE CHARACTERISTICS
OUTPUT OR-TIEING
The erasure characteristics of the 2716 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2716 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
Intel which should be placed over the 2716 window to
prevent unintentional erasure.
Because 2716's are usually used in larger memory arrays,
Intel has provided a 2 line control function that accomodates this use of multiple memory connections. The two
line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will
not occur.
To most efficiently use these two control lines, it is recommended that CE (pin 18) be decoded and used as the
primary device selecting function, while OE (pin 20) be
made a common connection to all devices in the array and
connected to the READ Iine from the system control bus.
This assures that all deselected memory devices are in their
low power standby mode and that the output pins are only
active when data is desired from a particular memory
device.
PROGRAMMING
The recommended erasure procedure (see Data Catalog
PROM/ROM Programming Instruction Section) for the
2716 is exposure to shortwave ultraviolet light which has
a wavelength of 2537 Angstroms (A). The integrated dose
(i.e., UV intensity X exposure time) for erasure should be
a minimum of 15 W-sec/cm 2 . The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 f.1W/cm 2 power rating. The 2716
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.
Initially, and after each erasure, all bits of the 2716 are in
the "1" state. Data is introduced by selectively programming "a's" into the desired bit locations. Although only·
"a's" will be programmed, both "1 's" and "a's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
DEVICE OPERATION
The 2716
supply is
grammed
pins. The
TTL.
The five modes of operation of the 2716 are Iisted in Table
I. It should be noted that all inputs for the five modes are at
TTL ievels. The power supplies required are a +5V V CC and
a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
two modes.
When the address and data are stable, a 50 msec, active
high, TTL program pulse is applied to the CE/PGM input.
A program pulse must be applied at each address location
to be programmed. You can program any location at any
time - either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
2716 must not be programmed with a DC signal applied to
the CE/PGM input.
TABLE I. MODE SELECTION
~
CE/PGM
(18)
DE
(20)
VPP
(21)
Vee
(24)
OUTPUTS
(9·11.13·17)
MODE
Read
VIL
VIL
+5
+5
DOUT
Standby
VIH
Don't Care
+5
+5
High Z
Program
Pulsed VIL to VIH
VIH
+25
+5
VIL
VIL
+25
+5
DOUT
VIH
+25
+5
High Z
Program Verify
Program Inhibit
VIL
DIN
Programming of multiple 2716s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the paralleled 2716s may be connected together when they are programmed with the same data. A high level TTL pulse
applied to the CE/PGM input programs the paralleled
2716s.
PROGRAM INHIBIT
READ MODE
The 2716 has two control functions, both of which must be
logically satisfied in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output
pins, independent of device selection. Assuming that
addresses are stable, address access time hACC) is equal to
the delay from CE to output (tCE). Data is available at
the outputs 120 ns (tOE) after the falling edge of OE,
assuming that CE has been low and addresses have been
stable for at least tACC - tOE.
is in the programming mode when the Vpp power
at 25V and OE is at VIH. The data to be prois applied 8 bits in parallel to the data output
levels required for the address and data inputs are
STANDBY MODE
Programming of mUltiple 2716s in parallel with different
data is also easily accomplished. Except for CE/PGM, all
like inputs (including OE) of the parallel 2716s may be
common. A TTL level program pulse applied to a 2716's
CE/PGM input with Vpp at 25V will program that 2716.
A low level CE/PGM input inhibits the other 2716 from
being programmed.
The 2716 has a standby mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW. The
2716 is placed in the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the outputs
are in a high impedence state, independent of the OE input.
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed wth Vpp at 25V. Except during programming and program verify, Vpp must be at 5V.
PROGRAM VERIFY
7-233
AFN-00911 A-05
32K (4K
x
2732
8) UV ERASABLE PROPJI
• Pin Compatible to Intel® 2716 EPROM
• Fast Access Time:
- 450 ns Max. 2732
- 550 ns Max. 2732·6
• Completely Static
• Single +5V ± 5% Power Supply
• Output Enable for MCS-85™ and
MCS-86™ Compatibility
• Low Power Dissipation:
150mA Max. Active Current
30mA Max. Standby Current
• Simple Programming Requirements
Single Location Programming
- Programs with One 50ms Pulse
• Three-State Output for Direct Bus
Interface
The Intel® 2732 is a 32,768-bit ultraviolet erasable and electrically programmable read-only memory (EPROM I. The 2732
operates from a single 5-volt power supply, has a standby mode, and features an output enable control. The total programming time for all bits is three and a half minutes. All these features make designing with the 2732 in microcomputer systems
faster, easier, and more economical.
An important 2732 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The
OE control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-72
describes the microprocessor system implementation of the OE and CE controls on Intel's 2716 and 2732 EPROMs.
AP-72 is available from Intel's Literature Department.
The 2732 has a standby mode which reduces the power dissipation without increasing access time. The maximum active
current is 150mA, while the maximum standby current is only 30mA, an 80% savings. The standby mode is achieved by
applying a TTL-high signal to the CE input.
PIN CONFIGURATION
MODE SELECTION
~
vee
A7
A6
As
Ar,
Ag
A4
All
MODE
CE
(18)
OE/Vpp
Vcc
OUTPUTS
(20)
(24)
(9·11,13-17)
Read
VIL
V IL
+5
DOUT
Standby
VIH
Don't Care
+5
High Z
A3
OENpp
Program
V IL
Vpp
+5
DIN
A2
A 10
Program Verify
CE
V IL
+5
Al
V IL
DOUT
Program Inhibit
VIH
Vpp
+5
High Z
Ao
~
00
06
°1
Os
BLOCK DIAGRAM
°2
03
GNO
DATA OUTPUTS
VCCO---
00-07
GNDO---
PIN NAMES
Ao-A"
Y·GATING
ADDRESSES
CE
CHIP ENABLE
OE
OUTPUT ENABLE
°0-°7
OUTPUTS
AO-All
ADDRE$S
INPUTS
32.768·BIT
CEll MATRIX
INTel CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
INTEL CORPORATION. 1980
FEBRUARY 1980
7-234
2732
PROGRAMMING
The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section.
'COMMENT
ABSOLUTE MAXIMUM RATINGS·
Stresses above those listed under ··Absolute Maximum Ratings·· may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability
Temperature Under Bias ............ -10°C to +80°C
Storage Temperature .............. -65°C to +125°C
All Input or Output Voltages with
Respect to Ground ................... +6V to -0.3V
D.C. AND OPERATING CHARACTERISTICS
= O°C to 70°C, VCC = +5V ± 5%
TA
READ OPERATION
Limits
Symbol
Parameter
Typ.i 1
Min.
1
Max.
Unit
Conditions
= 5.25V
= 5.25V
ILl1
Input Load Current (except OE/Vpp)
10
J.l.A
1L12
OE/Vpp Input Load Current
10
J.l.A
VIN
ILO
Output Leakage Current
10
J.l.A
VOUT
ICC1
Vcc Current (StandbYI
15
30
mA
CE
ICC2
Vce Current (Activel
85
150
mA
OE = CE =- VIL
VIL
Input Low Voltage
-0.1
0.8
V
2.0
Vec+1
V
0.45
V
IOL=2.1mA
V
IOH
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VIN
= 5.25V
= VIH, OE = VIL
= -400J.l.A
Note: 1. Typical values are for TA = 25°C and nominal supply voltages.
TYPICAL CHARACTERISTICS
Icc CURRENT
VS.TEMPERATURE
CE TO OUTPUT DELAY (t CE )
VS. CAPACITANCE
CE TO OUTPUT DELAY (t CE )
VS. TEMPERATURE
500
500
90
80
400
70
~
E
u
u
I--I--
60
50
~
-I--
--
400
-
-;:;, 300
300
~ f.-
...-...-
--
~
....
u
;:t
40
200
30 I---+--f-- ~~ ~I:ANDBY CURRENT)
20 I---+--f-- Vce
200
= 5V
100
10
0
0
TA
10
20
30
40
50
TEMPERATURE ( C)
60
70
80
100
o
100
200
300 400
CL (pFI
7-235
500
=
1
600
Vce = 5V
25 C
L
700
800
00
10
20
30
40
50
TEMPERATURE ( C)
I
I
60
70
80
2732
A.C. CHARACTERISTICS
± 5%
TA = O°C to 70°C, Vee = +5V
2732 Limits
Symbol
Parameter
Min.
Max.
2732·6 Limits
Min.
Max.
Test
Conditions
Unit
t Ace
Address to Output Delay
450
550
ns
CE=OE=V 1L
tCE
CE to Output Delay
450
550
ns
0E=V 1L
tOE
Output Enable to Output Delay
120
ns
tOF
Output Enable High to Output Float
0
100
ns
CE= V 1L
CE=V 1L
tOH
Output Hold from Addresses, CE or
OE, Whichever Occurred First
0
ns
CE=OE=V 1L
CAPACITANCE [1]
Symbol
100
Parameter
Input Capacitance
Except OE/Vpp
CIN2
OE/Vpp Input
Capacitance
COUT
Output Capacitance
A.C. WAVEFORMS
0
0
A.C. TEST CONDITIONS
TA=25°C, f=1MHz
CIN1
ADDRESSES
120
Typ.
Max.
4
6
pF
VIN
= OV
20
pF
VIN
12
pF
VOUT
= OV
= OV
Unit Conditions
Output Load: 1 TTL gate and CL = 100pF
Input Rise and Fall Times: ::; 20ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs O.8V and 2V
[2]
ADDRESSES
VALID
tDF
[4)
HIGH Z
OUTPUT --------.:;......;;.-----+.f-H~_<
NOTES:
1. THIS PARAMETER IS ONL Y SAMPLED AND IS NOT 100% TESTED.
•
2. ALL TIMES SHOWN IN PARENTHESES ARE MINIMUM TIMES AND ARE NSEC UNLESS OTHERWISE SPECI FlED.
3. DE MAY BE DELAYED U~O 33~ AFTER THE FALLING EDGE OF CEWITHOUT IMPACT ON tACC.
4. tDF IS SPECI FlED FROM OE OR CEo WHICHEVER OCCURS FIRST.
7·236
HIGH Z
2732
puts are in a high impedance state, independent of the
OE input.
ERASURE CHARACTERISTICS
The erasure characteristics of the 2732 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 2732 in
approximately 3 years, while it would take approximately 1
week to cause erasure when exposed to direct sunlight. If
the 2732 is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels are
available from Intel which should be placed over the 2732
window to prevent unintentional erasure.
The recommended erasure procedure (see Data Catalog)
for the 2732 is exposure to shortwave ultraviolet light
which has a wavelength of 2537 Angstroms (9)' The integrated dose (i.e., UV intensity X exposure time) for
erasure should be a minimum of 15 W-sec/cm 2. The
erasure time with this dosage is approximately 15 to 20
minutes using an ultraviolet lamp with a 12000 I1W/cm2
power rating. The 2732 should be placed within 1 inch of
the lamp tubes during erasure. Some lamps have a filter
on their tubes which should be removed before erasure.
When the address and data are stable, a 50msec, active
low, TTL program pulse is applied to the CE input. A
program pulse must be applied at each address location to
be programmed. You can program any location at any
time - either individually, sequentially, or at random. The
program pulse has a maximum width of 55msec. The 2732
must not be programmed with a DC signal applied to the
CE input.
OUTPUTS
(9·11,13·17)
vee
MODE
(20)
(24)
Read
V IL
V IL
+5
DOUT
Standby
V IH
Don't Care
+5
High Z
Program
V IL
Vpp
+5
Program Verify
V IL
V IL
+5
DOUT
Program Inhibit
V IH
Vpp
+5
High Z
To most efficiently use these two control lines, it is
recommended that CE (pin 18) be decoded and used as
the primary device selecting function, while TIE (pin 20)
be made a common connection to all devices in the array and connected to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low power standby mode and that
the output pins are only active when data is desired
from a particular memory device.
The 2732 is in the programming mode when the OE/Vpp
input is at 25V. It is required that a 0.1 J.lF capacitor be
placed across OE/Vpp and ground to suppress spurious
voltage transients which may damage the device. The data
to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data
inputs are TTL.
TABLE 1. Mode Selection
~
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will
not occur.
Programming
DEVICE OPERATION
OENpp
Because EPROMs are usually used in larger memory arrays, Intel has provided a 2 line control function that accommodates this use of multiple memory connections.
The two line control function allows for:
Initially, and after each erasure, all bits of the 2732 are in
the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1's" and "O's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
The five modes of operation of the 2732 are listed in
Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElV pp during
programming. In the program mode the OElV pp input is
pulsed from a TTL level to 25V.
CE
(18)
Output OR·Tieing
DIN
- -
Read Mode
The 2732 has two control functions, both of which must
be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the
output control and should be used to gate data to the
output pins, independent of device selection. Assuming
that addresses are stable, address access time (tAcc) is
equal to the delay from CE to output (tCE)' Data is
available at theoutputs 120ns (tOE) after the falling edge
of OE, assuming that CE has been low and addresses
have been stable for at least tAcc -. tOE,
Programming of multiple 2732s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the
paralleled 2732s may be connected together when they
are programmed with the same data. A low level TTL pulse
applied to the CE input programs the paralleled 2732s.
Program Inhibit
Programming of multiple 2732s in parallel with different
data is also easily accomplished. Except for CE, all like
inputs (including OE I of the parallel 2732s may be
common. A TTL level program pulse applied to a 2732's
CE input with OE/Vpp at 25V will program that 2732. A
high level CE input inhibits the other 2732s from being
programmed.
Standby Mode
Program Verify
The 2732 has a standby mode which reduces the active
power current by 80%, from 150mA to 30mA. The 2732 is
placed i~ the standby mode by applying a TTL high
signal to the CE input. When in standby mode, the out-
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify is accomplished with OElVpp and CE at VIL. Data
should be verified tDv after the falling edge of CEo
7-237
2732A
32K (4K x 8) UV ERASABLE PROM
• 200 ns (2732A·2) Maximum Access
Time ... HMOS*·E Technology
• Pin Compatible to 2764 EPROM
• Compatible to High Speed 8mHz
8086·2 M PU ... Zero WAIT State
• Industry Standard Pinout ... JEDEC
Approved
• Two Line Control
• Low Standby Current ... 35 mA Max.
The Intel 2732A is a 5V only, 32,384 bit ultraviolet erasable and electrically programmable read-only memory (EPROM). It
is pin compatible to Intel's 450ns 2732. The standard 2732A's access time is 250ns with speed selection (2732A-2)
available at 200ns. The access time is compatible to high performance microprocessors, such as the 8mHz 8086-2. In
these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.
An important 2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OE
control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-72 describes the
microprocessor system implementation of the OE and CE controls on Intel's EPROMs. AP-72 is available from Intel's
Literature Department.
The 2732A has a standby mode which reduces the power dissipation without increasing access time. The maximum
active current is 150mA, while the maximum standby current is only 35mA, a 75% saving. The standby mode is achieved
by applying a TIL-high signal to the CE input.
The 2732A is fabricated with HMOS*-E technology, Intel's high speed N-channel MOS Silicon Gate Technology.
MODE SELECTION
2764
PIN CONFIGURATION
2732A
PIN CONFIGURATION
Vpp
VCC
A'2
PGM
A7
N.C.l 11
A6
AS
~
MODE
CE
(18)
OE/Vpp
Vcc
(20)
(24)
OUTPUTS
(9-11.13·17)
Read
V IL
VIL
+5
DOUT
Standby
V IH
Don't Care
+5
High Z
AS
Ag
Program
+5
An
V IL
Vpp
A4
DIN
A3
DE
Program Verify
VIL
VIL
+5
DOUT
A2
A,a
Program Inhibit
V IH
Vpp
+5
High Z
Al
CE
AO
00
06
0,
05
02
04
GND
03
BLOCK DIAGRAM
DATA OUTPUTS
VCC~
111For total compatibility from
2732A provide a trace to pin 26
00-07
GNO~
PIN NAMES
Ao-A'l
ADDRESSES
CE
CHIP ENABLE
OE
OUTPUT ENABLE
0 0 -07
OUTPUTS
y·GATING
AO-All
ADDRESS
INPUTS
32.763·8IT
CELL MATRIX
'HMOS is a patented process of Intel Corporation.
7_,)~A
inter
2758
8K (1 K x 8) UV ERASABLE LOW POWER PROM
•
•
Single
•
Low Power Dissipation
525 mW Max. Active Power
132 mW Max. Standby Power
+ 5V Power Supply
Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse
•
Fast Access Time: 450 ns Max. in
Active and Standby Power Mode.
•
Inputs and Outputs TTL Compatible
during Read aoo Pr....m
•
Completely Static
•
Three·State Outputs for OR· Ties
The Intel@ 2758 is a 8192-bit ultraviolet erasable and electrically programmable read-only memOfy (~PAOM). The 2758
operates from a single 5-volt power supply, has a static standby mode, and features fast slAgle address location programming. It makes designing with EPROMs faster, easier and more economical. The total pr.amming Hme fOf all
8192 bits is 50 seconds.
The 2758 has a static standby mode which reduces the power dissipation without increa·sj.nQ) aeoess time. TM maximum active power dissipation is 525mW, while the maximum standby power dissipati.fII is 04'My 132mW, a 75%
savings. Powerd
COHVRT
TABLE lIST JHG
TYPE
VALUE AHI> REFERENCES
H ()SEC
l eSEC
L CSEC
l CSEC
IBFBH
IIIGH
IIIBH
1124
131
12221
BIBBH
lBl
Sample ASM51 Listing
8-12
AFN·01739A
8051 SOFTWARE DEVELOPMENT PACKAGE
CONV51
8048 TO 8051 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
• Enables software written for the
MCS-48™ family to be upgraded to
run on the 8051
• Preserves comments; translates 8048
macro definitions and calls
• Provides diagnostic information and
warning messages embedded in the
output listing
• Maps each 8048 instruction to a
corresponding 8051 instruction
The 8048 to 8051 Assembly Language Converter is a utility to help users of the MCS-48 family of microcomputers
upgrade their designs with the high performance 8051 architecture. By converting 8048 source code to 8051 source
code, the software investment developed for the 8048 is maintained when the system is upgraded.
The goal of the converter (CONV51) is to attain functional equivalence with the 8048 code by mapping each 8048
instruction to a corresponding 8051 instruction. In some cases a different instruction is produced because of the
enhanced instruction set (e.g., bit CLR instead of ANL).
Although CONV51 tries to attain functional equivalence with each instruction, certain 8048 code sequences cannot be
automatically converted. For example, a delay routine which depends on 8048 execution speed would require manual
adjustment. A few instructions, in fact. have no 8051 equivalent (such as those involving P4-P7). Finally, there are a few
areas of possible intervention such as PSW manipulation and interrupt processing, which at least require the user to
confirm proper translation. The converter always warns the user when it cannot guarantee complete conversion.
CONV51 produces two files. The output file contains the ASM51 source program produced from the 8048 instructions.
The listing file produces correlated listings of the input and output files, with warning messages in the output file to
point out areas that may require users' intervention in the conversion.
SPECIFICATIONS
Optional Hardware:
Universal PROM Programmer
Line Printer
ICE-51 In-Circuit Emulator
OPERATING ENVIRONMENT
Required Hardware:
Required Software:
ISIS-II Diskette Operating System (V3.4 or later)
Intellec Microcomputer Development System with
Documentation Package:
64K Bytes of RAM
MCS-51 Macro Assembler User's Guide
Flexible Disk Drive(s)
MCS-51 Macro Assembly Language Pocket Reference
System Console
MCS-51 8048-to-8051 Assembly Language Converter
Operating Instructions for ISIS-II Users
-CRT or hard copy device
ORDERING INFORMATION
Part Number
Description
MCI-51-ASM
8051 Software Development
Package
8-13
AFN·01739A
inter
ICE·51™
8051 IN·CIRCUIT EMULATOR
• Precise, full-speed, real-time emulation
- Load, drive, timing characteristics
- Full-speed program RAM
- Serial and parallel ports
• Full symbolic debugging
• User-specified breakpoints
• Macro commands and conditional
blo~k constructs for automated
debugging sessions
• Single-line assembly and disassembly
for program instruction changes
• Execution trace
- User-specified qualifier registers
- Conditional trigger
- Symbolic groupings and display
- Instruction and frame modes
• HELP facility: ICE-51 command syntax
reference at the console
• User confidence test of ICE-51
hardware
• Emulation timer
The ICE-51 module resides in the Intellec® Microcomputer Development System and interfaces to any
. user-designed 8051 system through a cable terminating in an 8051 emulator microprocessor and a pincompatible plug. The emulator processor, together with 8K bytes of user program RAM located in the
ICE-51 buffer box, replaces the 8051 device in the user system while maintaining the 8051 electrical and
timing characteristics. Powerful Intellec debugging functions are thus extended into the user system.
Using the ICE-51 module, the designer can emulate the system's 8051 in real-time or single-step mode.
Breakpoints allow the user to stop emulation on user-specified conditions, and a trace qualifier feature
allows the conditional collection of 1000 frames of trace data. Using the single-line 8051 assembler the
user may alter program memory using ASM51 mnemonics and symbolic references, without leaving the
emulator environment. Frequently used command sequences can be combined into compound commands and identified as macros with user-defined names.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: Intel, Intellec, MCS and ICE, and the combination of MCS or ICE and a
numerical suffix. Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are
implied.
c
INTEL CORPORATION, 1980
8-14
October 1980
ICE·51™
Symbolic Debugging
FUNCTIONAL DESCRIPTION
The ICE-51 emulator permits the user to define
and use symbolic, rather than absolute, references to program and data memory addresses; additional symbols are predefined by the ICE-51 software for referencing registers, flags, and input!
output ports. Thus, the user need not recall or look
up the addresses of key locations in his program
as they change with each assembly, or become
involved with machine code.
Integrated Hardware and Software
Development
The . ICE-51 emulator allows hardware and software development to proceed interactively. This
approach is more effective than the traditional
method of independent hardware and software
development followed by system integration. With
the ICE-51 module, prototype hardware can be
added to the system as it is designed. Software
and hardware integration occurs while the product is being developed.
It can be operated without being connected to the
user's system before any of the user's hardware is
available. In this stage ICE-51 debugging capabilities can be used in conjunction with the Intellec
text editor and 8051 macroassembler to facilitate
program development.
When a symbol is used for memory reference in an
ICE-51 emulator command, the emulator supplies
the corresponding location as stored in the ICE-51
emulator symbol table. This table can be loaded
with the symbol table produced by the assembler
during application program assembly. The user
can obtain the symbol table during software preparation simply by using the "DEBUG" switch in
the ASM51 macroassembler. Furthermore, the
user can interactively modify the emulator symbol
table by adding new symbols or changing or deleting old ones. This feature provides great flexibility
in debugging and minimizes the need to work with
hexadecimal values.
HARDWARE DEVELOPMENT
Through symbolic references in combination with
other features of the emulator, the user can easily:
The ICE-51 emulator assists four stages of development:
SOFTWARE DEBUGGING
The ICE-51 module's precise emulation characteristics and full-speed program RAM make it a valuable tool for debugging hardware, including timecritical serial port, parallel port, and timer interfaces.
• Interpret the results of emulation activity collected during trace.
• Disassemble program memory to mnemonics,
or assemble mnemonic instructions to executable code.
• Examine or modify 8051 internal registers, data
memory, or port contents.
• Reference labels or addresses defined in a user
program.
SYSTEM INTEGRATION
Integration of software and hardware can begin
when any functional element of the user system
hardware is connected to the 8051 socket. As
each section of the user's hardware is completed,
it is added to the prototype. Thus, each section of
the hardware and software is "system" tested in
real-time operation as it becomes available.
Automated Debugging and Testing
MACRO COMMAND
SYSTEM TEST
When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-51 module is then used for real-time emulation of the 8051 to debug the system as a completed unit.
A macro is a set of commands which is given a
name. A group of commands which is executed
frequently can be defined as a macro. The user
can execute the group of commands by typing a
colon followed by the macro name. Up to ten
parameters may be passed to the macro.
The final product verification test may be performed using the 8751 EPROM version of the 8051
microcomputer. Thus, the ICE-51 module provides
the user with the ability to debug a prototype or
production system at any stage in its development without introducing extraneous hardware or
software test tools.
Macro commands can be defined at the beginning
of a debug session and then used throughout the
whole session. The user can save one or more
macro definitions on diskette for later use. The
Intellec text editor may be used to edit the macro
file. The macro definitions are easy to include in
any later emulation session.
8·15
AFN.n17Q1A
ICE·51™
tinuously compares the values stored in the breakpoint registers with the status of specified address, opcode, operand, or port values, and halts
emulation when this comparison is satisfied.
When an instruction initiates a break, that instruction is executed completely before the break
takes place. The ICE-51 emulator then regains
control of the console and enters the Interrogation Mode. With the breakpoint feature, the user
can request an emulation break when his program:
The power of the development system can be applied to manufacturing testing as well as development by writing test sequences as macros. The
macros are stored on diskettes for use during
system test.
COMPOUND COMMAND
Compound commands provide conditional execution of commands (IF command) and execution of
commands repeatedly until certain conditions are
met (COUNT, REPEAT commands).
Compound commands may be nested any number
of times, and may be used in macro commands.
• Executes an instruction at a specific address or
within a range of addresses.
• Executes a particular opcode.
• Receives a specific Signal on a port pin.
• Fetches a particular operand from the user program memory.
• Fetches an operand from a specific address in
program memory.
Example:
* DEFINE .1 = a
*COUNT 100H
; Define symbol .1 to a
; Repeat the following
commands 100H times.
.*IF.I AND 1 THEN ; Check if .1 is odd
,,*BYTE .1=.1
; Fill the memory at location .1
to value .1
,,*END
; Increment .1 by 1.
. *.1 =.1+ 1
.*END
; Command executes upon
carriage-return after END
Table 1. Major Emulation Commands
Description
Command
(The characters *, . *, and" * shown in this example are system prompts which include an indication of the nesting level of compound commands.)
GO
BRO, BR1, BR
Operating Modes
STEP
QRO, QR1
The ICE-51 software is an Intellec RAM-based program that provides the user with easy-to-use commands for initiating emulation, defining breakpoints, controlling trace data collection, and displaying and controlling system parameters.
ICE-51 commands are configured with a broad
range of modifiers which provide the user with
maximum flexibility in describing the operation to
be performed.
TR
Synchronization Line
Commands
EMULATION
The ICE-51 module can emulate the operation of a
prototype 8051 system, at real-time speed (1.2 to
12 MHz) or in Single steps. Emulation commands
to the ICE-51 module control the process of setting up, running, and halting an emulation of the
user's 8051-based system. Breakpoints and tracepoints enable the ICE-51 emulator to halt emulation and provide a detailed trace of execution in
any part of the user's program. A summary of the
emulation commands is shown in Table 1.
Begins real-time emulation and optionally specifies break conditions.
Sets or displays either or both
Breakpoint Registers used for stopping real-time emulation.
Performs Single-step emulation.
Specifies match conditions for qualified trace.
Specifies or displays trace-data collection conditions and optionally
sets Qualifier Register (ORO, OR1).
Set and display status of synchronization line outputs or latched inputs. Used to allow real-time emulation or trace to start and stop synchronously with external events.
Trace and Tracepoints
Tracing is used with both real-time and singlestep emulation to record diagnostic information in
the trace buffer as a program is executed. The information collected includes opcodes executed,
port values, and memory addresses. The ICE-51
emulator collects 1000 frames of trace data.
This information can be displayed as assembler
instruction mnemonics, if desired, for analysis
during interrogation or single-step mode. The
trace-collection facility may be set to run conditionally or unconditionally. Two unique trace qualifier registers, specified in the same way as break-
Breakpoints
The ICE-51 hardware includes two breakpoint registers that allow the user to halt emulation when
specified conditions are met. The emulator con8-16
A~N.n17Q1l1..
ICE·51™
point registers, govern conditional trace activity.
The qualifiers can be used to condition trace data
collection to take place as follows:
Changes can be made in memory and in the 8051
registers, flags, and port values. Commands are
also provided for various utility operations such
as loading and saving program files, defining symbols, displaying trace data, controlling system
synchronization and returning control to ISIS-II. A
summary of the basic interrogation and utility
commands is shown in Table 3. Two time-saving
emulator features are discussed below.
• Under all conditions (forever).
• Only while the trace qualifier is satisfied.
• For the frames or instructions preceding the
time when a trace qualifier is first satisfied (pretrigger trace).
• For the frames or instructions after a trace qualifier is first satisfied (post-triggered trace).
SINGLE-LINE ASSEMBLER/DISASSEMBLER -
The single-line assembler/disassembler (ASM and
DASM commands) permits the designer to examine and alter program memory using assembly
language mnemonics, without leaving the emulator environment or requiring time-consuming
program reassembly. When assembling new
mnemonic instructions into program memory, previously defined symbolic references (from the
original program assembly, or subsequently defined during the emulation session) may be used
in the instruction operand field. The emulator will
supply the absolute address or data values as
stored in the emulator symbol table. These features eliminate user time spent translating to and
from machine code and searching for absolute ad~
dresses, with a corresponding reduction in transcription errors.
Table 2 shows an example of a trace display.
Table 2. Trace Display (Instruction Mode)
*r
P[
l
I rc
FF~n
rrrr: rrrn;
r rr": rrrJII
PrJ I: rrr7P
rrj': rrr31
rrJ c: rrrtp
P r 77: rr r7P
rr'1: rrrn'
1
rr? r::.: rrrq:
('('1":
r('rl-!
rr'J: rn'n
ep.l
Fe
H
r-'rv
pr, r
Ft
eFl
PlC
"
"'r::('C'""
r'
co
rrrr
..., r ") /' ('
rJ
J~'~Trt'rT I('~'
,...('vy
~
('11:f"-
r-"(,V
rrp
prrTF, f
F7
Fr
F'Pf-1
IFf'
fFf
fFf
FFf'
FFI'
F FI'
FF I'
FF I
HI
III
rr~
r'lPp
~
rpp
f-
rrl'
Pfl
PPII
prf 1
rPfl
.r], ' . . n'
prrl
~
erp
r
reI'
~l'" f
l,Fr
t'1'}1
f'pp
I'/P
ttf'
f'!'"Jf.'
?,Pfl
" t~·
prl'
POF
rrl'
~rv
?t P,
f,'~r
(,(·rrfl
:/I.
f T,.~~
Trl'F
r
INTERROGATION AND UTILITY
Interrogation and utility commands give the user
convenient access to detailed information about
the user program and the state of the 8051 that is
useful in debugging hardware and software.
Table 3. Major Interrogation and Utility Commands
Description
Command
HELP
Displays help messages for ICE-51 emulator command-entry assistance.
LOAD
Loads user object program (8051 code) into user program memory, and user symbols into
ICE-51 emulator symbol table.
SAVE
Saves ICE-51 emulator symbol table andlor user object program in ISIS-II hexadecimal file.
LIST
Copies all emulator console input and output to ISIS-II file.
EXIT
Terminates ICE-51 emulator operation.
DEFINE
Defines ICE-51 emulator symbol or macro.
REMOVE
Removes ICE-51 emulator symbol or macro.
ASM
Assembles mnemonic instructions into user program memory.
DASM
Disassembles and displays user program memory contents.
ChangelDisplay
Commands
Change or display value of symbolic reference in ICE-51 emulator symbol table, contents of
key-word references (including registers, 1/0 ports, and status flags), or memory references.
EVALUATE
Evaluates expression and displays resulting value.
MACRO
Displays ICE-51 macro or macros.
INTERRUPT
Displays serial, external, or timer interrupt register settings.
SECONDS
Displays contents of emulation timer, in microseconds.
Trace Commands
Position trace buffer pointer and select format for trace display.
PRINT
Displays trace data pointed to by trace buffer pointer.
8-17
AI=I\.I_n17Q111
ICE·51™
Emulation Accuiacy
HELP - The HELP fiie aiiows the user to dispiay
ICE-51 command syntax information at the Intellee console. By typing "HELP", a listing of all
items for which help messages are available is
displayed; typing "HELP < Item>" then displays
relevant information about the item requested, including typical usage examples. Table 4 shows
some sample HELP messages.
The speed and interface demands of a highperformance single-chip microcomputer require
extremely accurate emulation, including fullspeed, real-time operation with the full function of
the microcomputer. The ICE-51 emulator achieves
accurate emulation with an 8051 bond-out chip, a
special configuration of the 8051 microcomputer
family, as its emulation processor.
Each of the 40 pins on the user plug is connected
directly to the corresponding 8051 pin on the
bond-out chip. Thus the user system sees the
emulator as an 8051 microcomputer at the 8051
socket. The resulting characteristics provide extremely accurate emulation of the 8051, including
speed, timing characteristics, load and drive
values, and crystal operation. The emulator may
draw more power from the user system than a
standard 8051 family device.
Additional bond-out pins provide signals such as
internal address, data, clock, and control lines to
the emulator buffer box. These signals let static
RAM in the buffer box substitute for on-Chip program ROM or EPROM or external program memory. The 8K bytes of full-speed RAM in the buffer
box can be mapped in 4K blocks to anywhere within the 64K program memory space of the 8051. The
bond-out chip also gives the emulator "backdoor" access to internal chip operation, so that
the emulator can break and trace execution without interfering with the values on the user-system
pins.
Figure 1. A Typical 8051 Development Configuration. The host system is an Intellec
Model 225, plus 1 megabyte dual doubledensity flexible disk storage. The ICE-51
module is connected to an SDK-51 system design kit.
Table 4. HELP Command
-HELP IF
IF - The .:onditiorlCll COrnfTIa!l~-t .allows ...:onditio!lel ex(>.:'ut i 0.""1 of onE:"
or more C'ommClnds t-ased on the vi'lues of I:')oolean ..:onditiorlSa
IF (E"XDr> fTHF.f..'l
: :=r<.:omlflond> lfl
lP
rOPIF <.:r>
<.:ommand>: :=/lrl ICF-~l .... omlT'a~ld.
-HELP
Helo is aVC'lilf'ble for trf> follov.!rlo itE'l"1s. TyOfl Pflf' follo\o,'f'\."i ny
the itelTl rl?mt>. Tt"lE" t'elo items =Cl~I~lot te flb["lrE"vi('ltp ..i . (For fT'Iorf'
i~tformCltio:l, tyoe t:F.lP PF[P or l'fLF rNFC".)
Fl'lulc-tion:
Trr':E' ('ollf>.:t!o~l:
r-"is..:-:
ss'>
syr
TR C'P C'pr (,P1 ~YJ
RPf-F
<(,PU~kf>y"ord>
CO en
BR BRr PRJ
f'lfPPLf
~ltifif>r'>
OLrF~T' NEWEf;T
FVAL.tt/'.1F
Ch."ge/fli solay/[.e f i
RFN'VF
SY~B(,L
RECISTER
RFSE'T
SFCCNDS
Id~":O~lstMlt>
JNFC'
<1"('It.:t-~=o~hi'
CPYTF PPIT
f'~YTE
SYl"fCLI('
(system~ sYlflhols>
< traceS re fe!" en..:e>
r".E~
PEYTE PE'"
PPYTE ~A~
XBYTF. EY
fli'acro:
VEF JNE
DlR
['ISABLE FNAPLE
INCLUDE PUT
<~ACRC"~DISPLP y>
<"PCRCf! "'VOC" TIC~'>
C"omoouud
CommC"rlds:
CrUl'IT
IF
RFPEPT
(truetlist>l
r
r!'LSE 1
ENV
The s ere pVcluated in o:-der as Jr.-hit u'lsianed integprs.
If one is rf'acr.ed \o,'hos€' vf'lue hi'S lO\o."-or.:Jer nit J (TRUE), all
commands in tt·E' follo .... i:lo that s arid in thf'
~l!st> arc skiDoed.
rf all S ;'('"\'e value wit.h lo\..order hit r (FJ'LSE), thE'fI elll coml1'C'~his irl ('"II s arp
skipeed cHid, if FLSF is rrpSE'~lt, <,,11 commands i~1 t.hp
are exe.:utE'd.
(EX:
rs$symnols,>
IF. I00P=<
STEP
EL!=F
G0
ENro)
T~f~'
-
8-18
AFN·Q1791A
ICE·51™
SPECIFICATIONS
Physical Characteristics
ICE·51 Operating Requirements
Printed Circuit Boards
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Buffer Box
Width: 8.00 in. (20.32 cm)
Length: 12.00 in. (30.48 cm)
Depth: 1.75 in. (4.44 cm)
Weight: 4.0 Ib (1.81 kg)
Intellec® Microcomputer Development System
(64K RAM required)
System console
Intellec® Diskette Operating System (single or
double density) ISIS-II v. 3.4 or later
Equipment Supplied
• Printed circuit boards (2)
• Emulation buffer box, Intellec interface cables,
and user-interface cable with 8051 emulation
processor
• Crystal power accessory
• Operating instructions manual
• Diskette-based ICE-51 software (single and double density)
Electrical Characteristics
DC Power Requirements (from Intellec system)
Vee= + 5V, + 5%, -1%
lee = 13.2A max; 11.0A typical
Voo= + 12V, ± 5%
100 = 0.1A max; 0.05A typical
VaB = - 10V, ± 5%
IBB = 0.05A max; 0.01A typical
Emulation Clock
User's system clock (1.2 to 12 MHz) or ICE-51
crystal power accessory (12 MHz)
User plug characteristics at 8051 socket
Same as 8031, 8051, or 8751, except that the user
system will see an added load of 25 pF capacitance and 50/LA leakage from the ICE-51 emulator
user plug at ports 0, 1, and 2.
Environmental Characteristics
Operating Temperature: 0° to 40°C
Operating Humidity: Up to 95% relative humidity
without condensation.
ORDERING INFORMATION
Part Number
Description
MCI-51-ICE
8051 Microcontroller In-Circuit
Emulator, cable assembly and
interactive diskette software
8-19
AFN-01791A
UPP-103*
UNIVERSAL PROM PROGRAMMER
*Replaces UPP·101, UPP·102 Universal PROM Programmers
Intellec development system peripheral
for PROM programming and verification
Provides personality cards for program·
ming all Intel PROM families
Provides zero insertion force sockets for
both 16·pin and 24·pin PROMs
Universal PROM mapper software pro·
vides powerful data manipulation and
programming commands
Provides flexible power source for
system logic and programming pulse
generation
Holds two personality cards to facilitate
programming operations using several
PROM types
The UPP·103 Universal PROM Programmer is an Intellec system peripheral capable of programming and verifying all of
the Intel programmable ROMs (PROMs). In addition, the UPP-103 programs the PROM memory portions of the 8748
microcomputer,8741 UPI, the 8755 PROM and 1/0 chip and the 2920 signal processor. Programming and verification
operations are initiated from the Intellec development system console and are controlled by the universal PROM mapper (UPM) program.
8-20
UPP·103
FUNCTIONAL DESCRIPTION
Universal PROM Programmer
The basic Universal PROM Programmer (UPP) consists
of a controller module, two personality card sockets, a
front panel, power supplies, a chassis, and an Intellec
development system intert;onnection cable. An Intel
4040-based intelligent controller monitors the commands from the Intellec System and controls the data
transfer interface between the selected PROM personality card and the Intellec memory. A unique personality
card contains the appropriate pulse generation functions for each Intel PROM family. Programming and verifying any Intel PROM may be accomplished by selecting
and plugging in the appropriate personality card. The
front panel contains a power-on switch and indicator, a
reset switch, and two zero-force insertion sockets (one
16-pin and one 24-pin or two 24-pin). A central power
supply provides power for system logic and for PROM
programming pulse generation. The Universal PROM
Programmer may be used as a table top unit or mounted
in a standard 19-inch RETMA cabinet.
Universal PROM Mapper
The Universal PROM Mapper (UPM) is the software program used to control data transfer between paper tape
or diskette files and a PROM plugged into the Universal
PROM Programmer. It uses Intellec system memory for
intermediate storage. The UPM transfers data in 8-bit
HEX, BNPF, or binary object format between paper tape
or diskette files and the Intellec system memory. While
the data is in Intellec system memory, it can be displayed and changed. In addition, word length, bit position, and data sense can be adjusted as required for the
PROM to be programmed. PROMs may also be duplicated or altered by copying the PROM contents into the
Intellec system memory. Easy to use program and compare commands give the user complete control over programming and verification operations. The UPM eliminates the need for a variety of personalized PROM programming routines because it contains the programming algorithms for all Intel PROM families. The UPM
(diskette based version) is included with the Universal
PROM Programmer.
SPECIFICATIONS
Hardware Interface
Data - Two 8-bit unidirectional buses
Commands - 3 write commands, 2 read commands,
one initiate command
Physical Characteristics
Width -
6 in. (14.7 cm)
Height - 7 in. (17.2 cm)
Depth - 17 in. (41.7 cm)
Weight -
18 Ib (8.2 kg)
UPP-955: 8755A personality card with 40-pin adaptor
socket
PROM Programming Sockets
UPP-501: 16-pin/24-pin socket pair
UPP-502: 24-pin/24-pin socket pair
UPP-562: Socket adaptor for 3621, 3602, 3622, 3602A,
3622A
UPP-555: Socket adaptor for 3604AL, 36046-6, 3608,
3628, 3636
UPP-566: Socket adaptor for 3605, 3625, 3605A, 3625A
Electrical Characteristics
AC Power Requirements -
50-60 Hz; 115/230V AC: 80W
Environmental Characteristics
Operating Temperature -
O°C to 55°C
Optional Equipment
Personality Cards
UPP-816: 2716 personality card
UPP-832: 2732 personality card
UPP-848: 8748,8741 personality card with 40-pin adaptor
socket
UPP-865: 3602, 3622, 3602A, 3622A, 3621, 3604, 3624,
3604A, 3624A, 3604AL, 36046-6, 3605, 3605A, 3625,
3625A, 3608, 3628, 3636
UPP-872: 8702A/1702A personality card
UPP-878: 8708/8704/2708/2704 personality card
Equipment Supplied
Cabinet
Power supplies
4040 intelligent controller module
Specified zero insertion force socket pair
Intellec development system interface cable
Universal PROM Mapper program (diskette-based version)
Reference Manuals
9800819 - Universal PROM Programmer User's Manual
(SUPPLIED)
ORDERING INFORMATION
Part Number
Description
UPP-103
Universal PROM programmer with
16-pin/24-pin socket pair and
24-pin/24-pin socket pair.
8-21
SDK-51
MeS-51 SYSTEM DESIGN KIT
• Complete single·board microcomputer
kit:
-
Intel 8031 CPU
-
ASCII keyboard and 24·character
alpha·numeric display
-
Wire·wrap area for custom
circuitry
-User·configurable RAM
-
• Extensive system software in ROM:
- Single·line assembler and
disassembler
- System debugging commands
Go
Step
Breakpoints
• Interface software:
- Serial port
- Audio cassette
- Intellec® system
• User's guide, assembly manual, and
MCS·51 design manuals
Serial and parallel interfaces
The SDK-51 MCS-51 System Design Kit contains all of the components required to assemble a complete
single-board microcomputer based on Intel's high-performance 8051 single-chip microcomputer. SDK-51
uses the external ROM version of the 8051 (8031). Once you have assembled the kit and supplied + 5V
power, you can enter programs in MCS-51 assembly language mnemonics, translate them into MCS-51 object code, and run them under control of the system monitor. The kit supports optional memory and interface configurations, including a serial terminal link, audio cassette storage, EPROM program memory,
and Intellec® development system upload and download capability.
The following are trademarks of Intel Corporation and may be used only to describe Intel products: intel, Intellec, MCS and ICE, and the combination of MCS or ICE and a
numerical suffix, Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are
implied.
, INTEL CORPORATION, 1980
AFN·01792A
8-22
November 1980
162549
SDK-51
FUNCTIONAL DESCRIPTION
The 8031, 8051, and 8751 CPUS
The SDK-51 is a kit which includes hardware and
software components to assemble a complete
MCS-51 family single-board microcomputer. Only
common laboratory tools and test equipment are
required to assemble the kit. Assembly generally
requires 5 to 10 hours, depending on the experience of the user.
The 8031, 8051, and 8751 CPUs each combine, on
a single chip, a 128 x 8 data RAM; 32 input/output
lines; two 16-bit timer/event counters; a fivesource, two-level nested interrupt structure; a
serial 110 port; and on-chip oscillator and clock circuits. An 8051 block diagram is shown in Figure 1.
The 8031, the SDK-51's CPU, is a CPU without onchip program memory. The 8031 can address 64K
bytes of external program memory in addition to
64K bytes of external data memory. For systems
requiring extra capability, each member of the
8051 family can be expanded using standard memories and the byte-oriented MCS-80 and MCS-85
peripherals. The 8051 is an 8031 with the lower 4K
bytes of program memory filled with on-chip
mask-programmable ROM while the 8751 has 4K
bytes of ultraviolet light-erasable, electrically programmable ROM (EPROM).
The MCS-51 Microcomputer Series
MCS-51 is a series of high-performance singlechip microcomputers for use in sophisticated
real-time applications such as instrumentation,
industrial control and intelligent computer peripherals. The 8031, 8051, and 8751 microcomputers
belong to the 8051 family, which is the first family
in the MCS-51 series.
The 8031 CPU operates at a 12 MHz clock rate,
resulting in 4 Ils multiply and divide and other instructions of 1 Ils and 2 Ils.
In addition to their advanced features for control
applications, MCS-51 family devices have a microprocessor bus and arithmetic capability such as
hardware multipy and divide instructions, which
make the SDK-51 a versatile stand-alone microcomputer board.
For additional information on the 8051 family, see
the 8051 User's Manual or MCS-51 Macroassembier User's Guide.
REFERENCE
-t------------------
II
I
I
OSCILLATOR
&
TIMING
I
I
I
I
I
I
I
COUNTERS
4096 BYTES
PROGRAM
MEMORY
(8051 & 8751)
128 BYTES
DATA MEMORY
--l
I
I
TWO 16·BIT
TIMER/EVENT
I
COUNTERS
I
I
I
8051
CPU
I
I
1
I
I
I
64K·BYTE BUS
EXPANSION
f_____
PROGRAMMABLE
I/O
CON'""'
L
INTERRUPTS
CONTROL
PROGRAMMABLE
SERIAL PORT
• FULL DUPLEX
USART
• SYNCHRONOUS
SHIFTER
I
I
I
I
__ ~ ____ J
PARALLEL PORTS,
ADDRESS/DATA BUS,
& I/O PINS
SERIAL
IN
SERIAL
OUT
Figure 1. 8051 Block Diagram
8-23
AFN·01792A
SDK·51
Table 1. SDK-51 Commands
System Softwaie
A compact but powerful system monitor is contained in 8K bytes of pre-programmed ROM. The
monitor includes system utilities such as command interpretation, user program debugging,
and interface controls. Table 1 summarizes the
SDK-51 monitor commands.
Command
The ROM devices also include a single-line assembler and disassembler. The assembler lets
you enter programs in MCS-51 assembly language
mnemonics directly from the ASCII keyboard. The
disassembler supports debugging by letting you
look at MCS-51 instructions in mnemonic form
during system interrogation.
Define addresses for breaking
execution.
Display cause
Ask the system why execution
stopped.
Upload, download
Transfer files to and from Intellec@ development system.
Save, load
Transfer files to and from optional cassette interface.
Set top of
program memory
Define partition between program memory and data memory.
Set baud
Define baud rate value of serial
port.
Display memory
Examine and change program
memory or data locations.
Assemble
Translate an MCS-51 assembly
mnemonic into object code.
Disassemble
Translate program memory into
MCS-51 assembly language
mnemonics.
Go
Start execution between a selected pair of addresses.
Step
Execute a specified number of
instructions.
Memory
The two 64K external memo'ry spaces are combined into a single memory space which you can
configure between program memory and data
memory. The kit includes 1K-byte of static RAM.
The board has space and printed circuitry for an
additional 15K bytes of RAM and 8K bytes of
ROM.
User Interface
The kit includes a typewriter-format, ASCII-subset
keyboard and a 24-character, alpha-numeric LED
Operation
Set breakpoint
USER·
CONFIGURABLE
MEMORY
ADDRESS
& DATA BUSES
UPI
BUS
Figure 2_ Block Diagram of SDK-51 System Design Kit
8-24
AFN·01792A
SDK-51
display. The standard keyboard and display provide full access to all of the SDK-51's capabilities.
All of the SDK-51 interfaces are controlled by a
pre-programmed Intel 8041 Universal Peripheral
Interface.
A 3 x 4 matrix keyboard can be jumpered to port 1
of the 8031.
Optional Interfaces
TERMINAL
An RS-232-compatible CRT or printing terminal or
a current-loop-interface terminal may be used as a
listing device by connecting it to the board's
serial interface connector and supplying + 12 and
- 12 volts to the board.
Debugging
Hardware breakpoint logic in the SDK-51 checks
the address of a program or external data-memory
access against values defined by the user and
stops execution when it sees a "break" condition.
After a breakpoint, you can examine and modify
registers, memory locations, and other points in
the system. A step command lets you execute instructions in a single-step mode.
Assembly and Test
The SDK-51 assembly manual describes hardware
assembly in a step-by-step process that includes
checking each hardware subsystem as it is installed. Building the system requires only a few
common tools and standard laboratory instruments.
AUDIO CASSETTE
The kit includes hardware, software, and user's
guide instructions to connect and operate an
audio cassette tape recorder for low-cost program
and data storage.
INTELLEC SYTSTEM
An SDK-51 and an Intellec Model 800 or Series II
development system with ISIS-II can upload and
download files through the serial interface without adding any software to the Intellec system.
Parallel 1/0
The kit includes an Intel 8155 parallel 1/0 device
which expands the 8031 1/0 capability by providing 22 dedicated parallel lines. Three 40-pin headers between the 8031 and 8155 devices and the
wire-wrap area facilitate interconnections with the
user's custom circuitry.
Figure 3. SDK-51 Assembled with Additional RAM
and ROM Devices Installed
SPECIFICATIONS
Control Processor
Interfaces
Intel 8031 microcomputer
12 MHz clock rate
Keyboard - 51-key, ASCII subset, typewriter format, 12-key (3 x 4) matrix
Memory
Display -
RAM - 1K-byte static, expandable in 1K segments to 16K-byte with 2114 RAM devices; userconfigurable as program or data memory.
ROM - Printed circuitry for 8K bytes of program
memory in 4K segments using 2732A EPROM devices.
Serial - RS-232 with user-selectable baud rate.
Printed circuitry for 110 baud 20 rnA current loop
interface. 8031 serial port.
Parallel -
24-character, alpha-numeric
22 lines, TTL compatible
Cassette - Audio cassette tape storage interface
8-25
"1=1\1.n17Q?,,
SDK·51
Eieciricai Characterisiics
System monitor preprogrammed in on-board ROM
MCS-51 assembler and disassembler preprogrammed in on-board ROM
Interface control software preprogrammed in
8041's on-chip ROM
DC Power Requirement (supplied by user, cable
included with kit)
Voltage
+ 5V ±5%
+ 12V ± 5% *
-12V ± 5% *
Assembly and Test Equipment Required
Current
3A
100 mA
100 mA
• ± 12 volts required only for operation with serial interface.
Needle-nose pliers
Small Phillips screwdriver
Small diagonal wire cutters
Soldering pencil, :::;30 watts, 1116" diameter tip
Rosin-core, 60-40 solder, 0.05" diameter
Volt-Ohm-Milliammeter, 1 meg-ohm input impedance
Oscilloscope, 1 volt/division vertical sensitivity,
200 p.s/division sweep rate, single trace, internal
and external triggering
Environmental Characteristics
Operating Temperature - 0 to 40°C
Relative Humidity - 10% to 90%, non-condensing
Reference Manuals
SDK-51
SDK-51
SDK-51
MCS-51
MCS-51
ence
Physical Characteristics
Length - 13.5 in. (34.29 cm)
Width - 12 in. (30.48 cm)
Height - 4 in. (10.16 cm)
Weight - 3 Ib (1.36 kg)
User's Manual
Assembly Manual
Monitor Listing
Macro Assembler User's Guide
Macro Assembly Language Pocket Refer-
ORDERING INFORMATION
Part Number
Description
MCI-51-SDK
MCS-51 System Design Kit
8-26
AFN·01792A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
ISIS-II PL/M-80 VJ. 1 COMPILA1ION OF MODULE SIM51
OBJECT MODULE PLACED IN SIM31. ODJ
.F1 PLM80 SIM51. PLM PRINT(:Fl:SIM51 LST) XREF DATE(302)
COMPILER INVOKED BY:
$TITLE( '8051 INSTRUCTION SET SIMULATOR / )
1*
THE FOLLOWING IS A PLM-80 PROGRAM TO SIMULATE THE
OPERATION OF THE INTEL BOSl INSTRUCTION SET
1\10 ATTEMPT HAS BEEI'~ I"IADE TO ~; It1UL.ATE THE IIO PORTE; OR
SPECIAL FUNCTION REGISTEHS, THOUGH THERE ARE 'HOOv..S' TO
ACCESS EXTERNALLY-DEFINED PROCEDURES WHENEVER PO-P3 OR
SaUF ARE READ OR WRITTEN.
RELEVANT ENTRY POINTS:
'INITIALIZE' - SIMULATE HARDWARE RESET;
SUBROUTINE WITH NO INPUT PARAMETERS.
'STEP' - SIMULATE EXECUTION OF ONE INSTRUCTION
INPUT PARAMETER = STARTING ADDRESS;
VALUE RE"l UHNED .:: UPDATED PC.
'FETCH$SIM' - FETCH DATA FROM VARIOUS ADDRESS SPACES
(SEE ROUTINE DEFINITION FOR PARAMETER DEFINITION).
'STORE$SIM ' - STORE DATA INTO VARIOUS ADDRESS SPACES
(SEE ROUTINE DEFINITION FOR PARAMETER DEFINITION).
ALL PARAMETERS PASSED TO AND FROM ALL ROU1INES ARE SIXTEEN-BIT.
A·1
AFN·01739A
8051 INSTRUCTION SET SIMULATOR
PL/M-80 COMPILER
SIM5i;
i
DO;
1*
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DECLARE
DECLARE
DECL.ARE
DECLARE
DECLARE
ROM$SIZE LITERALLY '4096 ~;
1* 4K ROf\l SUPPORTED
INT$RAM(128) BYTE;
HARD$REG(128) BYTE;
USER$CODE(ROM$SIZE) BYTE PUBLICi
EXTERN$RAM(256) BYTEi
1
1
1
1
DECLARE
DECLARE
DECL.ARE
DECLARE
DECL.ARE
DECLARE
DECLARE
REG$ADDR BYTEi
DIR$ADDR BYTE;
SOURCE$ADDR BYTE;
DEST$ADDR BYTEi
BIT$ADDR BYTE;
CODE$ADDR ADDRESS;
PAGED$EXTERNAL$ADDR BYTEi
DECL/\RE
DECL.ARE
DECL.ARE
DECLARE
DECL.ARE
DECLARE
REG$DATA BYTE;
DIR$DATA BYTEi
IND$DATA BYTEj
IMM$DATA BYTE;
BIT$DATA BYTE;
STACK$DATA BYTE;
1
1
1
1
1
18
19
20
21
22
1
1
24
1
1
1.
1
DECLARE
DECLARE
DECLARE
DECL.ARE
LINK$BIT BYTEi
L.OW$NIB BYTE;
HIGH$NIB BYTE;
L.OW$SOURCE$NIB BYTE;
ADD$TEMP
SUB$TEMP
MUL$TEMP
DIV$TEMP
1
27
28
1
29
1
30
1
DECLARE
DECL.ARE
DECLARE
DECLARE
31
1
1
1
DECLARE PC ADDRESS;
DECL.AHE OPCODE BYTE;
DECLARE i'1f\CH$CYC ADDRESS PUBLICi
1
1
1.
DECL.ARE BIT$REG$ADDR BYTE;
DECLARE BIT$PATTERN BYTE;
DECLARE BIT$MASK BYTE;
33
34
35
36
*/
DECL.ARE PAGE$CODE BYTE;
DECLARE PAGE$OFFSET BYTE;
DECL.ARE DISPLACEMENT BYTE;
25
26
32
*1
1
1
1
1
1
1
1
1
1
23
DEFINITIONS OF GLOBAL VARIABLES USED BY INDIVIDUAL
INSTRUCTION SIMULATION PROCEDURES;
ADDRESS;
BYTE;
ADDRESS;
BYTE;
A-2
AFN·01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1*
37
38
39
40
41
42
43
44
45
46
47
·48
49
50
51
52
53
54
55
56
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECL.ARE
DECL.ARE
DECLARE
DECLARE
1*
57
1
PO
SP
DPL
DPH
TCON
TMOD
TLO
TLl
THO
THl
P1
SCON
SBUF
P2
IE
P3
IP
PSW
ACC
B
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
L I TER,6,LL Y
LITERALLY
LITERALLY
LITERAL.LY
LITERALLY
LITERALLY
LITERALLY
LITERAL.LY
'HARD$REG (OOH) 'i
'HARD$REG(OlH)' ;
'HARD$REG (02H) ';
'HARD$REG (03H) ';
'HARD$REG (08H) 'i
'HARD$REG (09H) 'i
'HARD$REG ( OAH) , i
'HARD$REG (OBH) 'i
'HARD$REG (OCH) j
'HARD$REG (ODH) 'i
'HARD$REG( 10H)' i
'HARD$REG ( 18H) 'i
'HARD$REG ( 19H) ' j
'HARD$REG ( 20H) , i
HARDSREG ( 28H) , i
'HARD$REG ( 30H) , i
'HARD$REG (38H) , ;
'HARDSREG (SOH) 'i
'HARD$REG (60H) , ;
'HARD$REG(70H) ' i
I
I
HARDWARE REGISTER TYPE CODES ARE ASSIGNED AS FOL.L.OWS:
o - REGISTER UNDEFINED OR BEYOND SCOPE OF SIMULATOR;
1
REGISTER WRITTEN OR READ SIMPLY BY DIRECT ADDRESSING;
2
110 PORTi
3
(RESERVED FOR EXPANSION)
*1
DECLARE HARD$REG$ATTRIB(128)
0.0,0,0,
(2, L L L
2,0,0,0,
0,0,0,0,
2,0,0,0,
0.0,0,0,
2,0,0,0,
0,0 . 0, 0,
0,0,0,0,
0,0,0,0 .
0, 0, 0, 0,
1,0,0,0.
1,0,0.0,
0,0,0 . 0,
1,0,0,0.
0.0,0,0,
BYTE DATA
1, L 1, L
1,2,0,0,
1,0,0,0,
1, 0, 0, 0,
0,0,0,0,
0,0,0,0,
0,0,0,0 .
0,0,0,0,
L L 0,0,
0,0, (L 0,
0,0,0,01
0,0 .. 0,01
0,0,0,0,
0,0,010,
0,·0,010,
0,0,0,0)
i
DECL.ARE BITSREGSMAP(32) BYTE DATA
( 20H.. 21H, 22H, 23H.
24H, 25H, 26H, 27H.
28H.. 29H, 2AH, 2BH.
2CH, 2DH, 2EHI 2FH.
BOH, B8H. 90H. 98H,
OAOHIOA8H,OBOH,OB8H,
OCOH,OC8H,ODOH,OD8H,
OEOH,OE8H.OFOH.OF8H);
58
59
PREDEFINED SPECIAL SYMBOLS FOR HARDWARE REGISTERS
( NOTE: VALUES OFFSET BY 80H TO CORRESPOND TO INDEX INTO
-H. I
HARD$REG ARRAY(0-127).
1
DECLARE MASK$TABLE(S) BYTE DATA
(OOOOOOOlB.
00000010B,
00000100D.
0001 OOOOH,
00 1 OOOOOB,
01 OOOOOOD,
00001000B,
10000000D ) i
AFN-01739A
A-3
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1*
HOOKS FOR EXTERNAL 110 PORT AND ERROR
HANDLING ROUTINES:
*1
60
61
62
1
2
2
PORT$OUTPUT:
PROCEDURE(PORT$NOIPORT$DATA) EXTERNAL;
DECLARE (PORT$NOIPORT$DATA) BYTE;
END PORT$OUTPUT;
63
64
65
1
2
PORT$INPUT:
PROCEDURE(PORT$NO) BYTE EXTERNAL;
DECLARE PORT$NO BYT~;
END PORT$INPUT;
2
66
67
68
2
2
DIR$ADDR$ERR:
PROCEDURE(HARD$REG$CODE) EXTERNAL;
DECLARE HARD$REG$CODE BYTE;
END DIR$ADDR$ERR;
69
70
71
1
2
2
IND$ADDR$ERR:
PROCEDURE(ILLEGAL$IND$ADDR) EXTERNAL;
DECLARE ILLEGAL$IND$ADDR BYTE;
END IND$ADDR$ERR;
72
73
74
2
STACK$ERR:
PROCEDURE(ILLEGAL$STACK$ADDR) EXTERNAL;
DECLARE ILLEGAL$STACK$ADDR BYTE;
END ST,.,\CK$ERR;
75
76
77
1
2
1
2
2
FETCH$PROG$ERR:
PROCEDURE(ILLEGAL$CODE$ADDR) EXTERNAL;
DECLARE ILLEGALSCODE$ADDR ADDRESS;
END FETCH$PROG$ERR;
A-4
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EdECT
1*
78
79
80
2
2
82
2
83
84
3
3
85
3
86
:2
87
1
2
88
89
90
91
..,
t::._
2
2
92
93
94
2
2
95
2
96
2
97
98
99
100
101
102
103
104
105
106
107
lOB
109
110
1J 1
11.2
11 :3
114
115
116
117
11.8
2
2
2
.)
c.
3
3
:~
VARIOUS MEMORY SPACE ACCESS ROUTINES:
FETCHSPROGRAM:
PROCEDURE (CODESADDR) BYTE;
DECLARE (CODE$ADDR) ADDRESS;
IF CODESADDR ( ROM$SIZE
THEN RETURN USERSCODE(CODESADDR);
EL.SE DO;
CALL FETCH$PROGSERR(CODESADDR);
RETURN OOHi
END;
END FETCHSPROGRAM;
FETCHSREG:
PROCEDURE (REGSNO) BYTE;
DECLARE (REGSNO,REGSADDR) BYTE;
REGSADDR=(PSW AND 00011000B) + REGSNO;
RETURN INT$RAM(REGSADDR);
END FETCHSREG;
PROCEDURE (REGSNO,DATA$VALUE);
STORESREG:
DECLARE (REGSNO,REGSADDR,DATASVALUE) BYTE;
REGSADDR=(PSW AND 00011000B) + REG$NO;
INTSRAMCREGSADDR)=DATA$VALUE;
END STORESREG;
FETCHSDIRPROCEDURECDIRSADDR$NO) BYTE;
DECLARE(DIRSADDRSNO,HARD$REGSINDEX,HARD$REGSTYPE) BYTE;
IF DIR$ADDRSNO (= 7FH THEN
RETURN INTSRAM(DIRSADDRSNO);
EL.SE DOi
HARDSREGSINDEX=DIR$ADDRSNO - 80H;
HARDSREG$TYPE=HARDSREG$ATTRIB(HARDSREGSINDEXl;
DO CASE HARD$REGSTYPE;
DO;
4
5
:5
CALL DIR$ADDRSERR(DIR$ADDRSNO);
RETUHN OOHi
END;
~.1
RETURN HARD$REG(HARD$REG$INDEX);
RETURN PORT$INPUTCDIRSADDRSNO);
4
4
4
3
*1
END;
END;
2
END FFfCI-!$D I I~.;
1
FETCH$DIR$INT:
PROCEDURECDIR$AODRSNO> ByrE;
DECLARE(DIRSADDRSNO,HARDSREGSINDEX,HARDSREGSTVPE) By-rEi
I~ DIRSADDRSNO (= 7FH THEN
RETURN INT$RAM
110
171
112
114
115
176
1ll
178
179
1
2
2
2
2
2
2
2
1
2
2
...
)
r-
180
r-
Ul1
2
'")
18:3
2
HJ4
2
185
186
187
2
2
188
189
190
2
192
193
2
2
2
194
2
2
195
1
196
1 (.77
198
2
2
2
200
201
2
2
;;~O2
1
203
;')
~:O4
~2
c.
206
;;~
;207
:3
3
3
208
209
21.0
21.1
21.2
2
2
2
8051 INSTRUCTION SET SIMULATOR
PROCEDURE(BIT$ADDR) BYTE;
DECLARE BITSADDR BYTE;
BIT$REG$ADDR=BITSREGSMAPCBIT$ADDR / 8);
BITSPAtTERN=FETCHSDIR(BITSREG$ADDR)i
BIT$MASK=MASKSTABLE(BITSADDR AND 000001118);
IF (BIT$PA1TERN AND BIT$MASK) = 0
THEN RETURN OOH;
EL SE RETURN L
END FETCHSBIT;
FETCH$BIT~
FETCH$Bll$INT:
PROCEDURECBIT$ADDR) BYTE;
DECLARE BIT$ADDR BYTE;
BIT$REGSADDR=BIT$REG$MAPCBITSADDR ! 8);
BIT$PATTERN=FETCH$DIR$INTC8IT$REG$ADDR);
BIT$MASK=MASK$TABLE(BIT$ADDR AND 00000111B);
IF (BITSPATTERN AND BIT$MASK) = 0
THEN RETURN OOH;
ELSE RETURN 1;
END FETCHSBIT$INT;
STORE$BIT:
PROCEDURE(BIT$ADDR,BIT$DATA);
DECLARE (BITSADDR,BIT$DATA) BYTE;
BITSREGSADDR=BIT$REGSMAPC8ITSADDR / 8);
BIT$PATTERN=FETCHSDIR$INT(BITSREGSADDR);
BITSMASK=MASK$TABLE(BITSADDR AND 000001110);
IF BITSDATA = 0
THEN BITSPATTERN=BITSPATTERN AND (NOT BIT$MASK);
ELSE BIT$PATTERN~(BIT$PATTERN OR BIT$MASK);
CALL STORE$DIRCBIT$REG$ADDR,BIT$PATTERN);
END STORE$B IT;
PUSH$STACK:
PROCEDURE CDATASVALUE);
DECLARE (DATASVALUE) BYTE;
SP";:SP+l
j
IF SP (::: '7FH
THEN INT$RAM(SP)=DATA$VAlUE;
ELSE CALL STACK$ERR(SP);
END PUSHSSTACK;
POP$STACK:
PROCEDURE BYTE;
DECLARE (DATA$VALUE) BYTE;
IF SP
(=
'7FH
THEN DATA$VALUE=INT$RAM(SP);
ELSE DO;
CALL STACK$ERR(SP);
DATA$VALUE=OOHi
END;
SP=SP-'l ;
RETURN DATASVALUE;
END POP$STAC!I,j
A-7
AFN·01739A
PL/M-80 COMPILER
213
214
215
2
2
216
2
217
218
219
220
221
1
2
2
2
2
222
223
224
2
2
225
2
226
227
228
229
2:'"'.)0
2
231
232
233
,
1::..
235
236
2
2
1
2
2
2
1
...,
2
237
238
239
240
2
2
242
2
244
2
246
c.
248
2
250
2
1
'")
1:_
...,
8051 INSTRUCTION SET SIMULATOR
FETCHSPAGEDSEXTERNAL:
PROCEDURE (PAGEDSEXTERN$ADDR) BYTE;
DECLARE (PAGEDSEXTERNSADDR) BYTE;
RETURN EXTERNSRAM(PAGEDSEXTERN$ADDR);
END FETCHSPAGEDSEXTERNAL;
STORESPAGEDSEXTERNAL:
PROCEDURE (PAGEDSEXTERN$ADDR,DATASBYTE);
DECLARE (PAGED.EXTERNSADDR) BYTE;
DECLARE DATA$BYTE BYTE;
EXTERNSRAM(PAGED$EXTERNSADDR) = DATA$BYTE;
END STORESPAGEDSEXTERNAL;
FETCH$LONG$EXTERNAL:
PROCEDURE (LONG$EXTERN$ADDR) BYTE;
DECLARE (LONG$EXTERN$ADDR) ADDRESS;
RETURN EXTERN$RAM(LONGSEXTERN.ADDR);
END FETCH$LONG$EXTERNAL;
STORE$LONGSEXTERNAL:
PROCEDURE (LONGSEXTERN$ADDR,DATASBYTE"
DECLARE (LONGSEXTERN.ADDR) ADDRESS;
DECLARE DATA$BYTE BYTE;
EXTERN$RAMCLONGSEXTERN$AbDR) = DATA$BYTE;
END STORESLONGSEXTERNAL;
SIGN.EXTENDED:
PROCEDURE (SIGNED$BYTE) ADDRESS;
DECLARE SIGNEDSBYTE BYTE;
IF (SIGNED$BYTE AND 10000000B) = 0
THEN RETURN SIGNEDSBYTE;
ELSE RETURN (SIGNED$BYTE + OFFOOH);
END SIGNSEXTENDED;
PARITY$STATE:
PROCEDURE (DATA$BYTE) BYTE;
DECLARE (DATASBYTE,PARITY$BIT) BYTE;
PARITYSBIT=O;
IF (DATA$BYTE AND 00000001B) (> 0
THEN PARITY$BIT=PARITY$BIT XOR 000000018;
IF (DATA$BYTE AND 000000108) <> 0
THEN PARITY$BIT=PARITY$BIT XOR Ob000001D;
IF (DATA$BYTE AND 00000100B) <> 0
THEN PARITYSBIT=PARITYSBIT XOR 0000000lB;
IF (DATA$BYTE AND 00001000B) <) 0
THEN PARITYSBIT=PARITYSBIT XOR 00000001D;
IF (DATA$BYTE AND 00010000B) () 0
THEN PARITYSBIT=PARITY$BIT XOR 00000001B;
IF (DATA$BYTE AND 00100000B) () 0
THEN PARITY$BIT=PARITYSBIT XOR 000000018;
A-a
AFN·01739A
PL/M-80 COMPILER
252
;2
254
2
8051 INSTRUCTION SET SIMULATOR
(;
IF (DATA$BYTE (.>.ND 01000000B)
THEN PARI1YSBIT=PARITY$BIT XOR 00000001 B.;
...
IF (DATA$BYTE !<\ND 10000000B) .-.... . 0
'
;
THEN PARITY$BIT=PARITY$BIT lOR OOOOOOOlD;
256
~2
2~·7
2
RETURN PARITY$I3ITi
END PAR I TY1iE) rATE;
A-9
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1* THE FOLLOWING CODE PROVIDES A SINGLE ENTRY POINT FOR
AN EXTERNAL ROUTINE TO READ DATA FROM ALL SIMULATOR ADDRESS SF
THE FIRST CALLING PARAMETER GIVES UP TO 16 BITS OF ADDRESS;
THE SECOND SPECIFIES WHICH LOGICAL ADDRESS SPACE TO
READ, USING THE SCHEME:
0 = PROGRAM MEMORY
1 = WORKING REGISTER
2 = DIRECT ADDRESS (INPUTS FOR PORTS)
3
INDIRECT THROUGH REGISTER SPECIFIED
4 = DIRECT BIT ADDRESS (DATA RIGHT-JUSTIFIED)
5 = PAGED EXTERNAL MEMORY
6 = 64K EXTERNAL MEMORY (ALL WRITES CURRENTLY TO PAGE 0)
7 = TOP-OF-STACK (SP UPDATED)
THE FUNCTION CALL RETURNS THE BYTE SO ADDRESSED.
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
2
2
2
2
3
3
3
3
3
3
3
3
3
2
2
FETCH$SIM:
PROCEDURE (DATA$ADDR,DATA$TYPE) ADDRESS PUBLIC;
DECLARE (RETURN$DATA,DATA$ADDR,DATA$TYPE) ADDRESS;
DECLARE DATA$ADDR$BYTE BYTE;
DATA$ADDR$BYTE=DATA$ADDRi
DO CASE DATA$TYPE;
RETURN$DATA=FETCH$PROGRAM(DATA$ADDR);
RETURN$DATA=FETCH$REG(DATA$ADDR$BYTE);
RETURN$DATA=FETCH$DIR$INT(DATA$ADDR$BYTE);
RETURN$DATA=FETCH$IND(DATA$ADDR$BYTE);
RETURN$DATA=FETCH$BIT$INT(DATA$ADDR$BYTE);
RETURN$DATA=FETCH$PAGED$EXTERNAL(DATA$ADDR$BYTE);
RETURN$DATA=FETCH$LONG$EXTERNAL(DATA$ADDR);
RETURN$DATA=POP$STACK;
END;
RETURN RETURN$DATA;
END FETCH$S I M;
1*
THE FOLLOWING CODE PROVIDES A SINGLE ENTRY
AN EXTERNAL ROUTINE TO WRITE DATA INTO ALL
THE FIRST CALLING PARAMETER GIVES UP TO 16
THE SECOND SPECIFIES WHICH LOGICAL ADDRESa
READ, USING THE SCHEME:
o
1
2
3
4
5
6
7
POINT FOR
SIMULATOR ADDRESS
BITS OF ADDRESS;
SPACE TO
PROGRAM MEMORY
- WORKING REGISTER
- DIRECT ADDRESS (OUTPUT LATCHES FOR PORTS)
INDIRECT THROUGH REGISTER SPECIFIED
= DIRECT BIT ADDRESS (DATA RIGHT-JUSTIFIED)
- PAGED EXTERNAL MEMORY
64K EXTERNAL MEMORY CALL WRITTEN CURRENTLY TO PAGE 0)
TOP-OF-STACK (SP UPDATED)
THE THIRD PARAMETER HOLDS THE BYTE VALUE TO BE WRITTEN.
274
275
276
2
2
STORE$SIM:
PROCEDURE (DATA$ADDR,DATA$TYPE,DATA$VALUE) PUBLIC;
DECLARE (DATA$ADDR,DATA$TYPE,DATASVALUE) ADDRESS;
DECLARE (DATA$ADDR$BYTE,DATA$VALUE$BYTE) BYTE;
A·10
AFN·01739A
*1
PL/M-80 COMPILER
277
278
279
280
281
282
283
284
285
286
287
288
289
2
2
2
3
3
3
3
3
3
3
3
3
2
8051 INSTRUCTION SET SIMULATOR
DATA$ADDR$BYTE=DATA$ADDRl
DATA$VALUE$BYTE=DATA$VALUEi
DO CASE DATA$TYPEi
USER$CODECDATA$ADDR MOD ROM$SIZE)=DATA$VALUE$BYTEi
CALL STORE$REG(DATA$ADDR$BYTE,DATA$VALUE$BYTE)l
CALL STORE$DIR(DATA$ADDR$BYTE,DATA$VALUE$BYTE)i
CALL STORE$IND(DATA$ADDR$BYTE,DATA$VALUE$BYTE);
CALL STORE$BIT(DATA$ADDR$BYTE,DATA$VALUE$BYTE);
CALL STORE$PAGED$EXTERNALCDATA$ADDR$BYTE,DATA$VALUE$BYTE);
CALL STORE$LONG$EXTERNALCDATA$ADDR,DATA$VALUE$BYTE)i
CALL PUSH$STACKCDATA$VALUE$BYTE);
END;
END STORE$SIM;
A-11
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJE:CT
$INCLUDE
1
2
2
2
2
2
2
2
298
299
300
1
2
2
302
303
2
2
305
306
307
308
2
2
2
INDIVIDUAL INSTRUCTION PROCEDURES:
=
=
1*
"ACALL
310
311
2
2
2
=
=
=
==
;::
=
-
2
-
=
==
==
==
:::
312
-
=
-31.3
314
315
316
31.7
318
2
1
2
==
2
2
2
*1
INSTRUCT ION:
1*
"ADD
A, (src-byte)·11
FUNCTION:
*1
ADD$A:
PROCEDURE(DATAtBYTE);
DECLARE DATA$BYTE BYTE;
IF ( (ACC AND OFH)+(DATA$BYTE AND OFH) ) ). OFH
THEN PSW=PSW OR 01000000Bi
ELSE PSW=PSW AND 10111111Bi
IF ( (ACC AND 7FH)+(DATA$BYTE AND 7FH) ) :> 7FH
THEN PSW=PSW OR 0OOOO100B;
ELSE PSW=PSW AND 11111011Bi
ADD$TEMP = (ACC) j
ADD$TEMP = (ADD$TEMP+DATA$BYTE);
IF ADD$TEMP :> OFFH
THEN PSW==(PSW OR 10000000B) XOR 000OO100Bi
ELSE PSW=(PSW AND 01111111B);
ACC=LOW(ADD$TEMP);
END ADDtAi
1*
"ADD
A/Rn"
INSTRUCTION:
*1
ADD$A$REG:
PROCEDUREi
REG$ADDR=OPCODE AND 00000111Bi
REG$DATA==FETCH$REG(REGtADDR)i
CALL ADD$A (REG$DATA);
PC::::PC+1;
END ADD$A$REG;
2
2
2
2
2
ad dr 16"
*1
ACALLtADDR11:
PROCEDURE;
PAGEtCODE==(OPCODE AND 11100000B) I 32;
PAGEtOFFSET=FETCHtPROGRAM(PC+1);
PC=PC+2i
CALL PUSHtSTACK(LOW(PC»;
CALL PUSHtSTACK(HIGH(PC»;
PC=(PC AND OF800H) + (PAGE$CODE * 100H) + PAGE$OFFSET;
END ACALL$ADDR11;
/*
319
320
321
322
3;'23
324
PLM)
1*
.290
291
292
293
294
295
296
297
(ISET~51.
=
==
--
"ADD
A, direc"t;1I
INSTRUCTION:
*/
ADD$A$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
DIR$DATA=FETCH$DIR(DIR$ADDR);
CALL ADD$A (OIR$DATA);
PC=PC+2i
END ADD$A$DIR;
1*
"ADD
A,@Ri"
INSTRUCTION:
A-12
*/
AFN·01739A
PL/M-80 COMPILER
325
326
327
328
:3;'29
330
1
2
2
2
2
2
==
-
ADD$A$IND:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001Bi
IND$DATA=FETCH$INDCREG$ADDR)i
CALL ADD$A ( IND$DATA) i
PC=PC+1 i
END ADD$A$IND;
1*
331
332
333
3~34
1
2
2
2
335
2
1
2
2
2
341
342
2
344
345
346
347
348
2
2
2
2
2
350
351
352
2
2
2
2
3~j6
:J~7
358
1
':1
e.
2
2
2
'".,
t:..
359
1
2
2
2
2
2
361
362
363
:361.1-
INSTRUCTION:
*1
"ADDC
A, (src-byte)"
FUNCTION:
"ADDC
A, Rn"
INSTRUCTION:
·1f·1
128;
OFH)+LINK$BIT)
>
7FH)+LINKSBJT)
> 7FH
XOR
OFH
000001000;
·tt/
ADDC$A$REG:
PROCEDURE;
REGSADDR=OPCODE AND 00000111H;
REGSDATA=FETCH$REGCREG$ADDR);
CALL ADDC$A(REG$DAfA);
PC::::PC-I'l ;
END I~DDC$A$REG.;
1*
360
A, #data"
ADDC$A:
PROCEDURECDATA$BYTE)i
DECLARE DATA$BYTE BYTE;
LINK$BIT = (PSW AND 10000000B) I
IF (CACC AND OFH)+(OATA$BYTE AND
THEN PSW=PSW OR 01000000B;
ELSE PSW=PSW AND 10111111Bi
IF (CACC AND 7FH)+(DATA$BYTE AND
THEN PSW=PSW OR 00000100B;
ELSE PSW=PSW AND 11111011B;
ADD$TEMP
(ACC);
ADD$TEMP :::: (ADD$TEMP+DATA$BYTE);
ADD$TEMP :::: (ADDSTEMP+LINK$BIT)i
IF ADDS TEMP > OFFH
THEN PSW=(PSW OR 10000000B)
ELSE PSW=(PSW AND 01111111B);
ACC=LOW(ADD$TEMP);
END ADDCS,...,,;
I'I!-
353
354
355
"ADD
ADD$A$IMM:
PROCEDUREi
IMMSDATA=FETCHSPROGRAM(PC+1);
CALL ADD$A(IMMSDATA);
PC=PC+2;
END ADD$A$IMM;
1*
336
337
338
339
8051 INSTRUCTION SET SIMULATOR
"f.\DDC
A,direct"
INSTRUC'TION:
.I(.!,
ADDC$A$DIR:
PROCEDURE;
DIR$ADDR=FETCHSPROGRAMCPC+l);
DIRSDATA=FETCH$DIR(DIRSADDR);
CALL ADDC$A(DIRSDATA);
PC~:=PC-t"2i
END ADDC$ASDIR;
A-13
AFN·01739A
PL/M-80 COMPILER
365
1
.._.
366
367
368
369
2
2
2
2
.-
370
2
..•
l·lf·
l*
371
1
2
373
374
2
375
2
2
:376
378
379
380
381
382
383
384
3f:35
:3B6
387
388
389
390
391
392
393
1
2
'')
1:..
2
2
2
.-
:::::
-
=
2
...,
1:"_
-
397
2
INSTRUCTION:
it·!
-
-_.
=
"AJMP
addT'11"
IN::lTRUCTION·ll·j
AJMP$ADDR11:
PROCEDURE;
PAGE$CODE=(OPCODE AND 11100000B) I J2;
PAGE$OFFSET=FETCH$PROGRAM(PC+l);
PC:=PG+2;
PC=(PC AND OF800H) + (PAGE$CODE * IOOH)
E.ND AJMP $f'\DDR 11 i
/*
"ANL.
A,Rn"
INSTHUCTIDN:
+
PAGE.OFFSET;
.1$-/
ANL$A$REG:
PROCEDURE;
REG$ADDR=OPCODE AND 00OOO111B .
REG$DATA=FETCH$REG(REG$ADDR);
ACC=ACC AND REG$DA"r Ai
PC:::::PC+l ;
END ANL.$A$REGi
1*
"ANL
A, direct"
INSTRUCTION:
.y,./
ANL.$A$DIR:
PROCEDlIREi
DIR$ADDR=FETCH$PROGRAM(PC+l);
DIR$DATA=FETCH$DIR(DIR$ADDR);
ACC::.~ACC AND DIR$DATAi
PC:;::PC+2;
END ANL$A$DIR;
1·1t-
1
11-/
PC::.::PC+;'~;
2
2
2
2
A,#data"
END ADDC$A$JI'1M;
-.
395
3 C)6
"ADDe
=
2
394
INSTRUCT ION:
ADDC$A$II'1M:
PROCEDURE;
IMM$DATA=FETCH$PROGRAM(PC+l),
CALL ADDC$A(IMMSDATA);
--
1
2
2
2
2
2
A,·@Ri."
.-
/*
377
"ADDC
ADDC$A$IND:
PROCEDURE;
REG$ADDR=OPCODE AND OOOOOOOlBi
IND$DATA=FETCH$IND(REG$ADDR);
CALL ADDC$A(IND$DATA)i
PC""PC+1 ;
END ADDC$A$IND;
'-
3"72
8051 INSTRUCTION SET SIMULATOR
",~NL
A,@Ri"
II\ISTr~IJCT
ION:
*1
ANL$A$IND:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001 Ii.:
IND$DATA=FETCH$IND(REGSADDR);
ACC=ACC AND IND$DATAi
A·14
AFN·01739A
PL/M-80 COMPILER
PC::;:PC-f'l ;
END ANL$ASIND;
398
399
1·1t-
400
401
402
403
404
1
2
2
2
:::::
2
405
406
407
408
409
410
8051 INSTRUCTION SET SIMULATOR
1
2
2
2
=
2
2
::;:
_.
"ANL
AI #de·ta"
INSTRUCTION:
*1
ANL$A$IMM:
PROCEDURE;
IMM$DATA=FETCH$PROGRAM(PC+1);
ACC=ACC AND IMM$DATA;
PC=PC+2;
END ANL$A$IMMi
lit·
"ANL
direct,AJI
I NSTRUCT I ON:
i1:1
ANL$DIR$A:
PROCEDUI~Ei
DIRSADDR=FETCH$PROGRAMCPC+1);
DIR$DATA=FETCH$DIR$INT(DIR$ADDR),
CALL STORE$DIR(DIR$ADDR,ACC AND DIR$J)ATA)
PC;:-.:;PC+2;
END ANL$DIR$Ai
j
:::::
,,411
412
413
414
415
416
417
1
2
2
...,
2
/:.
:::::
2
2
1*
419
420
421
4;23
424
2
2
2
2
::::
2
2
2
2
::::
2
-
2
-
INSTRUCTION:
"ANL
C, bit"
.;;./
DIR~iDATA).;
INSTRUCTION:
ANL$C$BIT:
PROCEDURE;
BIT$ADDR=FETCHSPROGRAM(PC+l);
BIT$DATA=FETCH$BIT(BIT$ADDR);
IF BIT$DATA -. 0 THEN PSW=PSW AND 01111111D;
PC=PC+2;
END ANLSC$BIT;
1*
425
426
427
428
4::10
431
direct . #data"
ANL$DIR$IMM:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
IMM$DATA=FETCH$PROGRAM(PC+2);
DIR$DATA=FETCH$DIR$INTCDIR$ADDR);
CALL STORE$DIR(DIRSADDR,IMMSDATA AND
PC:::::PC+3;
END ANL$D I R$ I MM;
1*
418
"ANL
"ANL
C. Ibit"
INSTRUCTION:
*1
ANL$C$COMPSB IT:
PROCEDURE;
BIT$ADDR=FETCHSPROGRAM(PC+l);
BITSDATA=FETCH$BIT(BITSADDR);
IF BIT$DATA -. 1 THEN PSW=PSW AND 01111111B;
PC=PC+2;
END ANL$C$COl"IP$B IT;
..
lit·
432
"CJNE
A, direct,
CJNE$A$DIR$REL:
T'ElI"
INSTRUCTION:
'1:-/
PROCEDURE;
A-15
AFN-01739A
PL/M·-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
433
2
DIR$ADDR=FETCHSPROGRAMCPC+l);
434
435
436
2
2
DIRSDATA=FETCH$DIR(DIR$ADDR);
4~J8
4:39
4·40
442
-
DISPLACEMENT=FETCHSPROGRAMCPC+2);
IF Ace < DIR$DATA
THEN PSW=(PSW OR 100000000);
ELSE PSW=(PSW AND 01111111B);
'"'
1':-
2
2
...'"-'
_.
'"I
t::.
PC::::PC+3;
IF ACC () DIRSDATA
THEN PC=PC+SIGN$EXTENDEDCDISPLACEMENT);
END C,)NE$ASD I R$REL;
1*
44~5
2
2
":~46
r...
448
44<;>
2
;2
450
;,;2
4~}2
2
'"'
1*
453
454
455
1
,..,
c:.
456
2
2
457
458
I"-
460
461
2
462
'"I
r.;.
464
2
2
':J
2
--
-
::
2
2
'"'
470
1"-
,::>
472
r.:.
473
474
r-_
2
476
2
~.,
"CJNE
RTlI #data, reI"
INSTRUCTION:
*1
"CJNE
@RL #data, rel"
INSTRUCTION:
·n-I
CJNE$IND$IMM$REL:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001Bi
1
2
2
INSTRUCTION:It-!
CJNESREGSIMMSREL:
PROCEDURE;
REG$ADDR=OPCOOE AND 00000111B;
REGSDATA=FETCHSREGCREG$ADDR);
IMM$DATA=FETCHSPROGRAM(PC+l);
DISPLACEMENT=FETCHSPROGRAMCPC+2);
IF REGSDATA < IMM$DATA
THEN PSW=(PSW OR 100000000);
ELSE PSW=(PSW AND 011111110);
PC::;PC+3i
IF REG$DATA () IMM$DATA
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END CJNE$REGSIMM$REL;
1*
465
466
467
468
469
A, #data, re I"
CJNESA$!MM$REL:
PROCEDURE;
IMM$DATA=FETCHSPROQRAM(PC+l);
DISPLACEMENT=FETCH$PROGRAMCPC+2);
IF Ace < IMMSOATA
THEN PSW=(PSW OR 100000000);
ELSE PSW=CPSW AND 01111111B);
PC::::PC+3;
IF Ace <> IMMSDATA
THEN PC=PC+SIGNSEXTENDEDCDISPLACEMENT);
END CJNE$A$IMM$REL;
443
44-4
"CJNE
.-.
IND$DATA~FETCH$IND(REG$ADDR)i
IMM$DATA=FETCH$PROGRAMCPC+l);
DISPLACEMENT=FETCH$PROGRAMCPC+2);
IF INDSDATA < IMMSDATA
THEN PSW=(PSW OR 10000000D);
ELSE PSW=(PSW AND 01111111B);
P(>::PC+3;
IF IND$DATA <> IMM$DATA
THEN PC=PC+SIGN$EXTENDEDCDISPLACEMENT);
END CJNE$IND$IMMSREL;
A·16
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
".
:::
-
477
478
2
47q
2
480
2
-
1*
"CLR
A"
INSTRUCTION:
*1
CLR$A:
PROCEDURE;
ACC=O;
PC=PC+l ;
END CLR$A;
'.
-/.*
"CLR
C"
INSTRUCTION:
'11-/
-.
481
482
483
484
..,
2
c..
:;::
2
CLR$C:
PROCEDURE;
PSW=PSW AND 01111111B;
PC=PC+1 i
END CLR$Ci
/.1$,.
485
486
487
488
489
1
2
2
2
2
:;::
..-
490
491
492
493
1
2
2
2
:=:
:=:
bit"
INSTRUCTION:
I'CPL
A"
INSTRUCTION:
/.*
"CPL
C"
INSTRUCTION:
502
2
503
504
1
2
2
2
2
2
2
:=
1*
1
2
"CPL
bit"
INSTRUCTION:
*1
CPL$B IT:
PROCEDURE;
BIT$ADDR=FETCH$PROGRAM(PC+l);
BIT$DATA=FETCH$BIT$INT(BIT$ADDR);
BIT$DATA=BIT$DATA XOR 00000001Bi
CALL STORE$BIT~BIT$ADDR/BIT$DATA);
PC=PC+2i
END CPL$BIT;
1*
505
506
*1
CPL.$C:
PROCEDUREi
PSW=PSW XOR 10000000B;
PC=PC+1 ;
END CPL$C;
1
2
2
:;::
498
499
500
501
*.1
CPL$A:
PROCEDURE;
ACC=ACC XOR 11111111B;
PC::::PC+l j
END CPL$A;
-494
41.75
4(.76
497
*1
CL.R$B IT:
PROCEDURE;
BIT$ADDR=FETCH$PROGRAM(PC+l);
CALL STORE$BIT(BIT$ADDR,O);
PC::::PC+2;
END CLR$BITi
1*
'-
"CLR
"DA
A"
INSTRUCTION:
*1
DA$A:
PROCEDUREi
IF ( (ACe AND OFH) :> 09H) OR ( (PSW AND 01000000B) <::::. 0)
A·17
AFN·01739A
PL/M-80 COMPILER
=
508
511
512
513
2
515
3
518
519
520
3
2
2
3
3
3
==
==
8051 INSTRUCTION SET SIMULATOR
THEN DO;
IF ACC >= OFAH THEN PSW=PSW OR 10000000B;
ACC=AeC+6;
END;
IF «ACC AND OFOH) > 90H) OR «PSW AND 100000008)
THEN DO)
IF ACC >= OAOH THEN PSW=PSW OR 10000000B;
ACC=ACC+60H)
END;
PC=PC+l;
END DASA;
1*
"DEC
A"
INSTRUCTION:
<> 0)
*1
::::
521
522
523
524
2
2
2
==
DEC$A:
PROCEDURE;
ACC=ACC-1;
PC=PC+1 )
END DECSAi
1*
525
526
527
528
529
1
5:~0
2
2
2
2
2
531
2
==
2
5:~7
2
538
2
1
2
2
2
::::
541
542
543
5 /+4
545
INSTRUCTION;
*1
"DEC
direct"
INSTRUCTION:
*1
DECSDIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
DIR$DATA=FETCH$DIR$INTCDIRSADDR);
DIRSDATA=DIRSDATA-1i
CALL STORESDIR(DIR$ADDR,DIRSDATA);
P(>::PC+2i
END DECSDIR;
1-1l-
539
540
Rn"
DECSREG:
PROCEDURE;
REGSADDR==OPCODE AND 000001118;
REG$DATA=FETCHSREG(REGSADDR);
REGSDATA==REG$DATA-1;
CALL STORE$REG(REGSADDR,REGSDATA);
PC==PC+li
END DECSREG;
1*
532
533
534
535
536
"DEC
"DEC
@Ri"
INSTRUCTION:
*1
PROCEDURE;
REGSADDR=OPCODE AND 000000018;
INDSDATA=FETCH$INDCREGSADDR);
INDSDATA=INDSDATA-1;
CALL STORESIND(REG$ADDR, INDSDATA);
PC::"PC+l ;
DEC$IND~
2
2
2
2
2
2
END DECSIND;
l*
"DIV
AB"
INSTRUCTION:
A-18
*1
AFN-01739A
PL/M-80 COMPILER
546
547
549
1
2
=
=
2
=
550
3
3
3
3
3
2
::::
2
2
=
551
552
553
554
555
556
557
=
=
=
8051 INSTRUCTION SET SIMULATOR
DIV$AB: PROCEDURE;
IF B = 0 THEN PSW=PSW OR 00000100B;
ELSE DO;
PSW=PSW AND 11111011B;
DIVSTEMP=ACC I B;
B=ACC MOD B;
ACC=DIV$TEMP;
END;
PSW=PSW AND 01111111B;
PC=PC+1;
END DIVSABi
::::
=
1*
"DJNZ
Rn,rel"
INSTRUCTION:
*1
=
558
1
559
560
2
561
562
563
2
2
=
=
=
=
565
2
2
2
2
567
2
=
=
=
=
=
568
1
=
=
569
570
571
575
2
2
2
2
2
2
2
577
2
564
DJNZSREG$REL: PROCEDUREi
REG$ADDR=OPCODE AND 00000111B;
DISPLACEMENT=FETCH$PROGRAM(PC+1);
REG$DATA=FETCHSREG(REG$ADDR);
REG$DATA=REG$DATA-1;
CALL STORE$REG(REG$ADDR,REG$DATA);
PC=PC+2;
IF REGSDATA <> 0
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END DJNZ$REGSREL;
1*
572
573
5'74
=
=
=
=
=
=
=
=
"DJNZ
direct,rel"
INSTRUCTION:
*1
DJNZSDIR$REL: PROCEDURE;
DIR$ADDR=FETCHSPROGRAM(PC+l);
DISPLACEMENT=FETCH$PROGRAM(PC+2);
DIRSDATA=FETCHSDIRSINT(DIRSADDR);
DIR$DATA=DIRSDATA-1i
CALL STORESDIR(DIR$ADDR,DIR$DATA);
PC=PC+3i
IF DIR$DATA <> 0
THEN PC=PC+SIGN$EXTENDEDCDISPLACEMENT);
END DJNZ$DIRSREL;
::::
578
5'79
580
581
A"
INSTRUCTION:
1*
1
2
=
2
2
=
=
INC$A: PROCEDURE;
ACC=ACC+l;
PC::::PC+l ;
END INGSAi
"INC
Rn"
INSTRUCTION:
*1
*1
::::
1*
INC$REG: PROCEDURE;
REG$ADDR=OPCODE AND 00000111B;
REGSDATA=FETCH$REG(REG$ADDR);
REG$DATA=REG$DATA+1i
CALL STORESREG(REGSADDR,REG$DATA);
PC::::PC+l ;
582
1
::::
583
2
2
=
=
2
2
2
=
584
585
586
587
"INC
::::
=
=
A·19
AFN,01739A
PL/M-80 COMPILER
588
589
590
591
592
593
594
595
END INCSREG;
2
1
=
=
=
2
=
2
2
2
2
2
8051 INSTRUCTION SET SIMULATOR
1*
"INC
direct"
*1
INSTRUCTION:
=
INCSDIR:
PROCEDURE;
DIRSADDR=FETCHSPROGRAM(PC+l);
DIRSDATA=FETCHSDIRSINT(DIRSADDR);
DIR$DATA=DIR$DATA+1;
CALL STORESDIR(DIRSADDR,DIRSDATA);
PC=PC+2;
END INCSDIR;
=
1*
=
"INC
@Ri"
INSTRUCTION:
*1
:=
596
597
598
599
600
601
602
1
2
2
2
=
=
=
=
2
2
2
=
=
INC$IND:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001B;
INDSDATA=FETCHSIND(REGSADDR);
INDSDATA=INDSDATA+l;
CALL STORESIND(REGSADDR, INDSDATA);
PC=PC+1;
END INCSIND;
1*
603
604
605
607
608
1
2
2
2
2
:=
=
614
1
2
2
2
2
2
616
2
61.:3
=
1
618
6;23
2
2
2
2
2
2
625
2
61.9
620
621
622
II
INSTRUCTION:
*1
",)B
b i t, re 111
INSTRUCTION:
*1
JB$BITSREL:
PROCEDURE;
BITSADDR=FETCH$PROGRAM(PC+l);
BITSDATA=FETCH$BITCBITSADDR);
DISPLACEMENT=FETCHSPROGRAM(PC+2};
PC~::PC+3;
IF BITSDATA=1
THEN PC=PC+SIGNSEXTENDEDCDISPLACEMENT);
END JB$BIT$REl;
1*
617
DPTR
INC$DPTR:
PROCEDURE;
DPL=DPL+i;
IF DPL=O THEN DPH=DPH+i;
PC=PC+1;
END INCSDPTR;
1*
609
610
611
612
"INC
=
=
"JBC
b i t, re 111
INSTRUCTION:
*1
JBC$BITSREL:
PROCEDURE;
BIT$ADDR=FETCH$PROGRAMCPC+l);
BITSDATA=FETCH$BITSINT(BITSADDR);
DISPLACEMENT=FETCH$PROGRAM(PC+2);
PC=PC+3;
CALL STORESBIT(BITSADDR,O);
IF BIT$DATA=i
THEN PC=PC+SIGNSEXTENDED(DISPLACEMENT);
END JBC$BIT$REL;
A-20
AFN-01739A
PL/M-80 COMPILER
1*
626
627
628
629
2
2
2
631
2
1
=
=
=
==
632
633
6:34
635
643
2
1
=
2
l*
1
645
646
647
2
.,r.:..
649
2
=
::::
2
1
6~)3
2
2
2
655
2
*1
"J/"lP
@A+DPTR"
INSTRUCTION:
*1
::::
2::::
6~;8
2
bit, re 1"
INSTRUCTION:
*1
"JNC
reI"
INSTRUCTION:
*1
"JNZ
reI"
INSTRUCTION:
*1
JNZSREL:
PROCEDURE;
DISPLACEMENT=FETCH$PROGRAM(PC+l);
PC:::;PC+2;
IF ACC <> 0
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END JNZ$REL;
1*
656
657
"JNB
JNC$REL:
PROCEDURE;
DISPLACEMENT=FETCH$PROGRAM(PC+l);
PC"=PC+2;
IF (PSW AND 10000000B) - 0
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END ,JNC$REL;
1*
650
651
652
INSTRUCTION:
JNB$BIT$REL:
PROCEDURE;
BIT$ADDR=FETCH$PROGRAMCPC+l);
DISPLACEMENT=FETCH$PROGRAM(PC+2);
BIT$DATA=FETCH$BIT(BIT$ADDR);
PC=PC+3;
IF BIT$DATA=O
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END JNB$B IT$REL;
l*
64-4
reI"
JC$REL:
PROCEDURE;
DISPLACEMENT=FETCH$PROGRAM(PC+l);
PC::::PC+2;
IF (PSW AND 10000000B) <> 0
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END JC$REL;
1*
2
2
2
2
IIJC
JMP$ADPTR:
PROCEDURE;
CODE$ADDR=(DPH*256)+DPL+ACC;
PC=CODE$ADDR;
END JMP$ADPTR;
1
2
2
2
636
637
638
639
640
641
8051 INSTRUCTION SET SIMULATOR
",)l
reI"
INSTRUCTION:
*1
. JZ$REL:
PROCEDURE;
DISPLACEMENT==FETCH$PROGRAM(PC+l);
PC:::::PC+2;
A·21
AFN·01739A
PL/M-80 COMPILER
6!59
2
661
2
IF Ace _. 0
THEN PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END JZ$REl.i
1*
662
663
664
665
666
667
668
669
1*
1
2
2
2
681
682
6B3
684
2
2
...,
t::..
2
2
1
2
2
2
2
=
I
2
INSTRUCTION:
*1
"MCJV
A,Rn"
INSTRUCTION:
*1
"MOV
A, direct"
INSTRUCTION:
*1
=
"MOV
A,@Ri"
INSTRUCTION:
*1
MOV'A$IND:
PROCEDUREi
REGSADDR=OPCODE AND 0000000lBi
ACC=FETCHSIND(REG$ADDR)i
PC::::PC+li
END MOVSA$lNDi
1*
6'-70
691
addr16"
MOV$A$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l)i
ACC=FETCHSDIRCDIRSADDR)i
PC:::::PC+2i
END MOV$ASDIR;
I
2
1*
685
686
687
688
689
"LJMP
MOV$ASREG:
PROCEDUREi
REGSADDR=OPCODE AND OOOOOl11D;
ACC=FETCH$REG(REG$ADDR);
PC:==PC+li
END MOV$ASREG;
1
2
2
1*
680
*1
LJMP$ADDR16:
PROCEDURE;
PAGE$CODE=FETCH$PROGRAM(PC+l);
PAGESOFFSET=FETCH$PROGRAM(PC+2);
PC=(PAGE$CODE * lOOH) + PAGE$OFFSET;
END LJMPSADDR16i
1*
675
676
677
678
679
INSTRUCTION:
CALL PUSH$STACK(LOW(PC»;
CALL PUSH$STACK(HIGHCPC»;
PC=(PAGE$CODE * IOOH) + PAGESOFFSET;
END LCALL$ADDR16;
2
2
2
addr16"
PC~-::PC+3;
2
671
672
673
674
"LCALL
LCALL$ADDR16:
PROCEDURE;
PAGE$CODE=FETCH$PROGRAM(PC+l)i
PAGE$OFFSET=FETCH$PROGRAM(PC+2);
1
2
2
2
2
670
8051 INSTRUCTION SET SIMULATOR
"I"IOV
A, #data"
INSTRUCTION:
'~I
MOV$ASIMM:
PROCEDUREi
ACC=FETCH$PROGRAM(PC+l);
A-22
AFN-01739A
8051 INSTRUCTION SET SIMULATOR
PL/M-80 COMPILER
692
693
2
2
=
PC~.::PC+2;
END MOV$A$IMM;
1*
694
695
696
697
698
701
702
703
704
705
:::
1*
2
2
2
=
=
7:1.0
711
2
=
709
712
1
2
2
2
2
715
716
=
7:1.7
1
2
2
2
2
2
2
719
720
721
'7;:12
723
INSTRUCTION:
'11.-1
II
1"10 V
Rn,:>.ta"
INSTRUCTION:
"MOV
,direct, All
INSTRUCTION:
"MOV
d i rec t, Rn
INSTRUCTION:
II
=
MOV$DIR$REG:
PROCEDURE;
REG$ADDR=OPCODE AND 00000111Bi
REG$DATA=FETCH$REGCREG$ADDR);
DIR$ADDR=FETCH$PROGRAMCPC+l);
CALL STORE$DIR(OIR$ADOR,REG$DATA);
PC=PC+2;
END' 1'10V$DIR$REG;
=
1*
:;
=
=
*1
*1
MOV$DIR$A:
PROCEDUREi
DIR$ADDR=FETCH$PROGRAM(PC+l);
CALL STORE$DIR(DIR$ADDR,ACC);
PC;::PC+2;
END MOV$DIR$A;
1*
718
Rn, direct"
MOV$REG$IMM:
PROCEDUREi
REG$ADDR=OPCODE AND 00000111Bi
IMM$DATA=FETCH$PROGRAM(PC+1);
CALL STORE$REG(REG$ADDR, IMM$DATA);
PC=PC+2i
END MOV$REG$IMM;
1*
713
714
"MOV
*1
MOV$REG$DIR:
PROCEDURE;
REG$ADDR=OPCODE AND 00000111B;
DIR$ADDR=FETCH$PROGRAMCPC+l);
DIR$DATA=FETCH$DIR(DIR$ADDR);
CALL STORE$REG(REG$ADDR,DIR$DATA);
PC;:.PC+2,.
END MOV$REG$DIR;
2
2
2
2
2
2
2
2
2
2
708
INSTRUCTION:
MOV$REG$A:
PROCEDURE;
REG$ADDR=OPCODE AND 00000111Bi
CALL STORE$REG(REG$ADDR,ACC);
PC::::PC+1 i
END MOV$REG$Ai
1*
706
707
RTl, A"
=
"")
c.
699
700
"JVIOV
"MOV
d ire c t, d ire c t
II
*1
I NSTR UC T I ON :
*I
:::
724
1
=
MOV$DIR$DIR:
PROCEDURE;
A-23
AFN·01739A
PL/M-80 COMPILER
725
726
727
728
729
730
2
2
2
2
2
2
=
=
=
=
=
=
SOURCE$ADDR=FETCH$PROGRAM(PC+l)i
DEST$ADDR=FETCH$PROGRAM(PC+2);
DIR$DATA=FETCH$DIR(SOURCE$ADDR);
CALL STORE$DIR(DEST$ADDR,DIR$DATA);
PC::::PC+3;
END MOV$DIR$DIR;
1*
731
732
7~36
1
2
2
2
2
2
73'7
2
733
734
735
738
739
740
741
742
743
1
2
2
2
2
2
8051 INSTRUCTION SET SIMULATOR
IIMOV
d i rec t, @Ri
INSTRUCTION:
/I
::
PROCEDURE;
AND 0000000lB;
IND$DATA=FETCH$IND(REG$ADDR);
DIR$ADDR=FETCH$PROGRAM(PC+1);
CALL STORE$DIR(DIR$ADDR, IND$DATA);
PC::::PC+2i
END MOV$DIR$INDi
=:
I
=
MOV$DIR$IMM:
PROCEDUREi
DIR$ADDR=FETCH$PROGRAM(PC+1);
IMM$DATA=FETCH$PROGRAM(PC+2)i
CALL STORE$DIR(DIR$ADDRI IMM$DATA);
PC==PC+3i
END MOV$DIR$IMM;
*1
MOV$DIR$IND:
=
=
REG$ADDR~OPCODE
,If
1*
"MOV
"MOV
direct, #data"
@Ril All
INSTRUCTION:
INSTRUCTION:
*1
*1
=
744
1
745
2
2
2
2
74,6
747
748
::
MOV$IND$A:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001Bi
CALL STORE$IND(REG$ADDR,ACC);
PC=PC+1 i
END MOV$IND$A;
=
l*
MOV$IND$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
DIR$OATA=FETCH$OIR(DIR$ADDR);
REG$ADDR=OPCODE AND 00000001B;
CALL STORE$IND(REG$ADDR,DIR$DATA);
PC=PC+2;
END MOV$IND$DIR;
=
749
1
::
750
2
751
752
2
2
2
2
2
=
=
753
7~i4
755
=
=
1*
756
1
::
757
2
=
758
2
759
2
2
2
760
761
=
"MOV
"1¥lOV
@Ri,
d i rec t
INSTRUCTION:
/I
@Ril#data ll
INSTRUCTION:
*1
*1
MOV$IND$IMM:
PROCEDURE;
IMM$DATA=FETCH$PROGRAM(PC+l);
REG$ADDR=OPCODE AND 00000001Bi
CALL STORE$IND(REG$ADDR, IMM$DATA);
PCr.::PC+2i
END MOV$IND$IMM;
A-24
AFN·01739A
PL/M-80 COMPILER
1*
762
763
764
765
767
768
769
2
2
2
1*
c:..
2
2
2
2
'-I
1*
776
7'77
7'78
7'79
780
78~3
7B4
785
'"1
r._
2
1*
786
2
788
789
790
2
"1
c:..
"c:..
794
2
2
2
"MOV
b i t, C"
INSTRUCTION:
-j!-/
"I"IOV
DPTR, #data16"
INSTr~UCTION:
i!;'/
"1"lOVe
A,
@A+DPTR"
INSTRUCTION:
.!t. .!
=
"Move
A, @A·t,PC"
INSTRUCTION:
·It-I
MOVC$A$APC:
PROCEDURE;
PC::=pC+l i
CODESADDR=(PC+ACC);
ACC=FETCH$PROGRAMCCODESADDR);
END MOVCSA$APC;
1*
791
792
793
'~I
MOVC$ASADPTR:
PROCEDURE;
CODESADDR=(DPH*256)+DPL+ACC;
ACC=FETCH$PROGRAM(CODE$ADDR);
PC:=PC+:L ;
END MOVC$ASADPTR;
2
2
2
2
7U7
INSTRUCTION:
MOVSDPTR$IMM16.
PROCEDURE;
DPH=FETCHSPROGRAM(PC+l);
DPL=FETCH$PROGRAM(PC+2);
PC:::::PC+3;
END MOV$DPTRSIMM16;
1
2
2
/*
781
782
C, bit"
MOVSBITSC:
PROCEDURE;
BITSADDR=FETCHSPROGRAM(PC+l);
BITSDATA=«PSW AND 10000000B) I 128);
CALL STORESBIT(BIT$ADDR.BIT$DATA);
PC;;::;PC -1-2;
END MOV$BIT'flC;
Tl0
773
7'/4
7'15
"rHJV
MOVSCSBIT:
PROCEDURE;
BIT$ADDR=FETCH$PROGRAMCPC+l);
BITSDATA=FETCHSBITCBIT$ADDR);
IF BIT$DATA=O
THEN PSW=(PSW AND 01111111B);
ELSE PSW=(PSW OR 10000000B);
PC::::PC+2i
END MOVSCSB IT j
1
2
2
2
771
772
8051 INSTRUCTION SET SIMULATOR
"I"IOVX
A, @Ri
II
INSTRUCTION:
*1
MOVX$ASIND:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001B;
PAGEDSEXTERNALSADDR=FETCH$REG(REG$ADDR)I
ACC=FETCH$PAGED$EXTERNAL(PAGED$EXTERNALSADDR);
A-25
AFN·01739A
PL/M-BO COMPILER
795
796
791
798
799
800
801
802
2
2
2
2
2
2
2
e03
1
804
2
805
806
2
2
8051 INSTRUCTION SET SIMULATOR
=
=
PC=PC+i;
END MOVX$A$IND;
=
1*
=
=
=
=
=
=
MOVX$IND$A:
PROCEDUREj
REG$ADDR=OPCODE AND 0000000lBi
PAGED$EXTERNAL$ADDR==FETCH$REG(REG$ADDR);
CALL STORE$PAGED$EXTERNALCPAGED$EXTERNAL$ADDR,ACC);
PC=PC+li
END MOVX$IND$Ai
=
1*
:::::
MOVX$A$DPTR:
PROCEDURE;
ACC=FETCH$LONG$EXTERNAL(CDPH*256)+DPL)i
PC=PC+li
END MOVX$A$DPTRi
=
=
=
"MOVX
"MOVX
@Ri. A"
INSTRUCTION:
A,@DPTR"
*1
INSTRUCTION:
*1
:::
=
1*
"MOVX
@DPTR,A"
INSTRUCTION:
*1
:::
907
808
1
=
2
=
809
2
:::
810
2
==
MOVX$DPTR$A:
PROCEDUREi
CALL STORE$LONG$EXTERNAL(CDPH*256)+DPL,ACC)j
PC::::PC+li
END MOVX$DPTR$Ai
:=
:=
1*
"MUL
AB"
INSTRUCTION:
*1
:::
811
812
913
1
2
=
2
=
814
2
2
=
815
816
==
2
:::
818
8:1.9
8~~O
821
2
2
2
:::
:::
=
--
1
2
:::
8~12
823
2
:;::
.. -
MUL$AB:
PROCEDUREi
MUL$TEMP=ACC * Bi
B=HIGHCMUL$TEMP);
ACC=LOW(MUL$TEMP)i
PSW=PSW AND 01111111B;
IF B :co:: 0
THEN PSW==PSW AND 11111011B;
ELSE PSW=PSW OR 00000I00B;
PC:;::PC+li
END MUL$ABi
1*
IINOP "
INSTRUCTION:
'Ifol
PROCEDUREi
Pco:::pC+:I. i
END NOP;
NOP:
"ORL
A,Rn"
INSTRUCTION:
:::::
1*
ORL$A$REG:
PROCEDUREi
REG$ADDR=OPCODE AND 000OO111Bi
REG$DATA=FETCH$REGCREG$ADDR);
ACC=ACC OR REG$DATA,
824
1
:::
825
2
:::
826
2
=
827
2
==
A-26
'Ifol
AFN-01739A
PL/M-80 COMPILER
828
829
2
2
8051 INSTRUCTION SET SIMULATOR
=
PC=PC+1i
END ORL$A$REGi
=
=
1*
::::
"ORL
A,direct"
INSTRUCTION:
*1
::::
830
831
1
2
832
2
833
834
2
835
2
::::
=
2
::::
ORL$A$DIR:
PROCEDUREi
DIR$ADDR==FETCH$PROGRAM(PC+1)i
DIR$DATA=FETCH$DIR(DIR$ADDR)i
ACC=ACC OR DIR$DATAi
PC=PC+2;
END ORL$A$DIRi
1*
836
837
838
839
840
841
1
2
2
2
2
2
=
=
"ORL
A,@Ri"
INSTRUCTION:
::::
ORL$A$IND:
PROCEDUREi
REG$ADDR=OPCODE AND 0000000lB;
IND$DATA=FETCH$IND(REG$ADDR);
ACC=ACC OR IND$DATAi
PC=PC+1;
END ORL$A$INDi
==
1*
=
"ORL
A,#data"
*1
INSTRUCTION:
*1
=
842
843
844
845
846
::::
2
2
2
2
::::
::::
==
847
1
848
2
2
2
2
2
849
850
851
852
=
=
=
==
=
853
1
854
2
2
2
855
856
857
858
859
2
2
2
=
=
=
==
==
ORL$A$IMM:
PROCEDURE;
IMM$DATA=FETCH$PROGRAM(PC+1);
ACC=ACC OR IMM$DATAi
PC=PC+2i
END ORL$A$IMMi
1*
1
d i rec t, A"
INSTRUCTION:
*1
ORL$DIR$A:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+1)i
DIR$DATA=FETCH$DIR$INT(DIR$ADDR);
CALL STORE$DIRCDIR$ADDR,ACC OR DIR$DATA)i
PC:::,pC+2i
END ORL$DIR$l\;
1*
1I0RL
direct, #data"
INSTRUCTION:
·*1
ORL$DIR$IMM:
PROCEDUREi
DIR$ADDR=FETCH$PROGRAM(PC+l);
IMM$DATA=FETCH$PROGRAM(PC+2);
DIR$DATA=FETCH$DIR$INT(DIR$ADDR)i
CALL STORE$DIR(DIR$ADDR, IMM$DATA OR DIR$DATA)i
PC=PC+3i
END ORL$DIR$IMMi
1*
860
"ORL
"ORL
ORL$C$BIT:
C, bit"
INSTRUCTION:
*1
PROCEDURE;
A-27
AFN·01739A
PL/M-80 COMPILER
861
862
863
865
866
2
2
2
2
2
=
=
=
=
8051 INSTRUCTION SET SIMULATOR
BIT$ADDR=FETCH$PROGRAM(PC+1);
BIT$DATA=FETCH$BIT(BIT$ADDR)i
IF BIT$DATA = 1 THEN PSW=PSW OR 10000000B;
PC=PC+2i
END ORL$C$BITi
:::
=
:::
867
868
869
870
872
873
874
875
876
877
1
2
2
2
2
2
1
2
2
=
=
1*
IIORL
C,/bit
ll
INSTRUCTION:
*1
=
=
=
=
ORL$C$COMP$BIT: PROCEDUREi
BIT$ADDR=FETCH$PROGRAM(PC+l);
BIT$DATA=FETCH$BIT(BIT$ADDR)i
IF BIT$DATA = 0 THEN PSW=PSW OR lOOOOOOOBi
PC=PC+2i
END ORL$C$COMP$BITi
=
1*
==
POP$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
STACK$DATA=POP$STACKi
CALL STORE$DIR(DIR$ADDR,STACK$DATA);
PC=PC+2;
END POP$DIR;
=
=
=
878
2
2
879
2
=
IIPOP
d i -rec
t II
INSTRUCTION:
*1
:::
1*
IIPUSH
d i -rec t
II
INSTRUCTION:
*1
=
880
881
882
883
884
885
1
2
2
2
2
2
:::
=
=
PUSH$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
DIR$DATA=FETCH$DIR(DIR$ADDR)i
CALL PUSH$STACK(DIR$DATA)i
PC=PC+2i
END PUSH$DIRi
:::
=
886
887
888
889
890
2
"RET II
INSTRUCTION:
*1
RET:
1
2
2
2
1*
=
=
=
PROCEDURE;
PAGE$CODE=POP$STACKi
PAGE$OFFSET=POP$STACK;
PC=(PAGE$CODE * lOOH) + PAGE$OFFSETi
END RETi
:::
1*
891
892
893
8(74
:::
2
2
2
=
895
2
:::
INSTRUCTION:
*1
RETI:
PROCEDURE;
PAGE$CODE=POP$STACK;
PAGE$OFFSET=POP$STACKi
PC=(PAGE$CODE * lOOH) + PAGE$OFFSETi
1*
:::
"RETIII
RESTORE INTERRUPT SYSTEM TO LEVEL IN EFFECT
BEFORE LAST INTERRUPT RECEIVED *1
END RETIi
A-28
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
::::
1*
896
897
898
899
900
1
==
=
2
2
2
2
=
==
"RL
A"
INSTRUCTION:
*1
RL$A:
PROCEDUREi
LINK$BIT=(ACC AND 10000000B) 1 128i
ACC==(ACC * 2) + LINK$BITi
PC==PC+1i
END RL$Ai
::::
1*
901
902
903
904
905
906
1
2
=
2
2
=
2
2
=
"RLC
All
INSTRUCTION:
*1
RLC$A:
PROCEDUREi
LINK$BIT=(ACC AND 10000000B) 1 128;
ACC=(ACC * 2) + «PSW AND 10000000B) 1 128);
PSW=(PSW AND 01111111B) + (LINK$BIT * 128)i
PC=PC+1 i
END RLC$Ai
::::
1*
907
908
909
910
911
1
2
2
2
==
==
==
2
1
2
2
2
2
2
==
==
1
2
=
2
2
1
9~25
2
2
2
926
2
==
::::
::::
::::
*1
"RRC
All
INSTRUCTION:
*1
IISETB
C"
INSTRUCTION:
*1
SETB$C:
PROCEDURE;
PSW=PSW OR 10000000B;
PC:.::PC+l ;
END SETB$Ci
1*
922
923
924
INSTRUCTION:
RRC$A:
PROCEDURE;
LINK$BIT=ACC AND 00000001B;
ACC=(ACC I 2) + (PSW AND 10000000B)i
PSW=(PSW AND 01111111B)+(LINK$BIT * 128)i
PC=PC+1i
END RRC$Ai
1*
918
919
920
921
A"
RR$A:
PROCEDURE;
LINK$BIT=ACC AND 00000001Bi
ACC=(ACC 1 2) + (LINK$BIT * 128)i
PC=PC+1i
END RR$Ai
1*
912
913
'914
915
916
917
"RR
"SETB
bit"
INSTRUCTION:
*1
SETB$BIT:
PROCEDURE;
BIT$ADDR=FETCH$PROGRAM(PC+1);
CALL STORE$BIT(BIT$ADDR, 1);
PC!.::PC+2;
END SETB$B IT;
A·29
AFN-01739A
PL/M-80 COMPILER
92'7
928
929
930
931
2
==
SJMP$REL:
PROCEDURE;
DISPLACEMENT=FETCH$PROGRAM(PC+1);
PC=PC+2;
PC=PC+SIGN$EXTENDED(DISPLACEMENT);
END SJMP$RELi
=
2
2
2
;2
2
=
2
=
2
2
942
943
2
2
945
<7'46
947
2
2
2
2
9~J2
2
2
953
2
958
959
2
2
2
2
2
A, (sT'c-byte:>"
*1
FUNCTION:
-lI.·1
END SUBB$A;
==
::::
.-
"SUBB
A, Rn"
INSTRUCTION:
*1
SUBB$A$REG:
PROCEDURE;
REG$ADDR=OPCODE AND 00000111B;
REG$DATA=FETCH$REG(REG$ADDR);
CALL SUBB$A(REG$DATA);
PC::::PC+l ;
END SU13B$A$REG;
1*
954
955
956
9'57
Ii
ACC~ACC-SUB$TEMP;
=
=
2
2
"SUBD
reI
SUBB$A:
PROCEDURE(DATA$BYTE)i
DECLARE DATA$BYTE BYTE;
LINK$BIT=(PSW AND 100000000) 1 128;
SUB$TEMP=DATA$BYTE;
SUB$TEMP=SUB$TEMP+LINK$BIT;
IF (ACC AND OFH) ~ (SUB$TEMP AND OFH)
THEN PSW=PSW OR 01000000B;
ELSE PSW=PSW AND 101111110;
IF (ACC AND 7FH) ~ (SUB$TEMP AND 7FH)
THEN PSW=PSW OR 00000100B;
ELSE PSW=PSW AND 11111011B;
IF Ace < SUB$TEMP
THEN PSW=(PSW OR 10000000B) XOR 00000100B;
ELSE PSW=(PSW AND 01111111B);
1*
948
949
950
951
INSTRUCTION:
l*
2
939
940
IIS,)MP
=
1*
932
9:33
934
935
936
937
8051 INSTRUCTION SET SIMULATOR
"SUBB
A, direct"
INSTRUCTION:
-lI.·1
SUBB$A$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+l);
DIR$DATA=FETCH$DIR(DIR$ADDR);
Cf'\LL SUBB$A.( DIR$DATA);
PC::::PC+2;
END SUBB$A$DIRi
::::
=
..960
961
962
963
964
965
2
2
2
2
2
=
1*
"SUBB
A,@Ri"
INSTRUCTION:
*1
SUBB$A$IND:
PROCEDURE;
REG$ADDR=OPCODE AND 000000010;
IND$DATA=FETCH$IND(REG$ADDR);
CALL SUBB$A(IND$DATA);
PC:::::PC+l ;
END SUBB$A$INDi
A-30
AFN·01739A
PL/M-80 COMPILER
:::
966
967
968
969
9-'0
971
972
973
974
975
976
1*
"SUBB
Al#data"
INSTRUCTION:
*1
2
:::
2
==
SUBB$A$IMM:
PROCEDURE;
IMM$DATA==FETCH$PROGRAM(PC+1);
CALL SUBB$A(IMM$DATA);
PC;::PC+2;
END SUBB$f\$IMMi
==
1*
1
==
2
2
2
2
2
:::
SWAP$A:
PROCEDURE;
LOW$NIB=ACC AND 000011118;
HIGH$NIB==ACC AND 11110000B;
ACC==(LOW$NIB * 16) + (HIGH$NIB I 16);
PC==PC+1;
END SWAP$A;
2
2
==
==
1*
977
978
979
980
981
8051 INSTRUCTION SET SIMULATOR
1
982
2
2
2
2
2
983
2
1
984
985
986
987
2
2
988
2
989
990
2
2
2
==
=
"SWAP
"XCH
A"
INSTRUCTION:
A,Rn"
*1
INSTRUCTION:
XCH$A$REG:
PROCEDURE;
REG$ADDR=OPCODE AND 00000111B;
REG$DATA=FETCH$REG(REG$ADDR};
CALL STORE$REG(REG$ADDR,ACC);
ACC=REG$DATA;
PC:.::PC+l ;
END XCH$A$REG;
"XCH
A, direct"
INSTRUCTION:
==
==
1*
:::
XCH$A$DIR:
PROCEDURE;
DIR$ADDR=FETCH$PROGRAM(PC+1);
DIR$DATA=FETCH$DIR(DIR$ADDR);
CALL STORE$DIR(DIR$ADDR,ACC);
ACC=DIR$DATA;
PC=PC+2;
END XCH$A$DIR;
:::
::::
*1
*1
:::
1*
991
992
993
994
995
996
997
INSTRUCTION:
==
==
==
1*
=
2
2
2
2
Al @Ri"
XCH$A$IND:
PROCEDURE;
REG$ADDR=OPCODEAND 00000001B;
IND$DATA=FETCH$IND(REG$ADDR);
CALL STORE$IND(REG$ADDRlACC);
ACC=IND$DATA;
PC=PC+l;
END XCH$A$IND;
:::
2
2
"XCH
=
"XCHD
Al@Ri"
INSTRUCTION:
·ltl
*1
:::::
998
1
XCHD$A$IND:
PROCEDURE;
A-31
AFN·01739A
PL/M-80 COMPILER
999
1000
1001
t002
1003
1004
1005
1006
2
2
2
2
2
=
=
::;;:
::;;:
2
::;;:
2
2
::;;:
=
REG$ADDR=OPCODE AND 00000001Bi
IND$DATA=FETCH$INDCREG$ADDR)i
LOW$SOURCE$NIB=IND$DATA AND 000011110i
IND$DATA=(IND$DATA AND 111100000) + CACC AND 000011110)i
CALL STORE$INDCREG$ADDR, IND$DATA)i
ACC=CACC AND 111100000) + LOW$SOURCE$NIBi
PC=PC+1;
END XCHD$A$INDi
1*
1007
1008
1009
1010
1011
1012
1
2
2
2
2
2
=
=
:=
::;;:
2
2
=
2
2
2
=
::;;:
2
2
2
2
2
=
=
=
2
=
2
:=
2
2
=
=
1030
1031
1032
1033
1034
1035
2
2
2
2
2
::;;:
=
=
INSTRUCTION:
*1
"XRL
A, direct"
INSTRUCTION:
*1
IIXRL
A,@Ri ll
INSTRUCTION:
*1
XRL$A$IND:
PROCEDURE;
REG$ADDR=OPCODE AND 00000001Bi
IND$DATA=FETCH$INDCREG$ADDR»)
ACC=ACC XOR IND$DATAi
PC=PC+l i
END XRL$A$INDi
1*
1025
1026
1027
1028
1029
A, Rn"
XRL$A$DIR:
PROCEDUREi
DIR$ADDR=FETCH$PROGRAMCPC+1);
DIR$DATA=FETCH$DIRCDIR$ADDR)i
ACC=ACC XOR DIR$DATAi
PC==PC-f'·2i
END XRL.$A$DIRi
1*
1019
1020
1021
1022
1023
1024
"XRL
XRL$A$REG:
PROCEDUREi
REG$ADDR=OPCODE AND 000001110i
REG$DATA=FETCH$REGCREG$ADDR)i
ACC=ACC XOR REG$DATAi
PC=PC+1i
END XRL$A$REGi
1*
1013
1014
1015
1016
1017
1018
8051 INSTRUCTION SET SIMULATOR
"XRL
A,#data"
INSTRUCTION:
*1
XRL$A$IMM:
PROCEDURE)
IMM$DATA=FETCH$PROGRAM(PC+l)i
ACC=ACC XOR IMM$DATAi
PC=PC+2i
END XRL$A$IMM;
1*
"XRL
diT'ect,A II
INSTRUCTION:
*1
XRL$DIR$A:
PROCEDUREi
DIR$ADDR=FETCH$PROGRAMCPC+1»)
DIR$DATA=FETCH$DIR$INTCDIR$ADDR)i
CALL STORE$DIRCDIR$ADDR,ACC XOR DIR$DATA);
PC=PC+2i
END XRL$DIR$Ai
A-32
AFN·01739A
PL/M-80 COMPILER
1·1t-
1036
1037
1038
1039
1040
1041
1042
1
2
_.
.-
2
2
2
2
2
:=
-
8051 INSTRUCTION SET SIMULATOR
"XRL
direct, #data"
INSTRUCTION:
*1
PROCEDURE;
XRLSDIR$IMM:
DIR$ADDR=FETCHSPROGRAM(PC+l);
IMMSDATA=FETCH$PROGRAM(PC+2};
DIRSDATA=FETCHSDIRSINT(DIRSADDR);
CALL STORESDIRCDIRSADDR.IMMSDATA XDR DIR$DATA) ;
PC::::;PC+3;
END XRLSDIRSIMMi
A-33
AFN·01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$E,,}ECT
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
INITIALIZE: PROCEDURE PUBLICi
PC=OOOOHi
PO=OFFHi
Pl::::0FFHi
P2=OFFHi
P3=OFFHi
PSW=OOHi
SP=07Hi
DPL=OOHi
DPH=OOHi
ACC=OOHi
B=OOHi
TLO=OOHi
THO=OOHi
TL1=OOHi
TH1=OOHi
TCON=OOHi
TMOD=OOHi
SCON=OOHi
IE==OOHi
IP=OOHi
MACH$CYC=OOOOHi
1* SIMULATION ELAPSED TIME REGISTER.
END INITIALIZEi
1066
1
DECLARE EXECUTION$TIME(256) BYTE DATA
2
(1,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
1,
L
1,
2,
2,
1,
1,
1,
1,
1,
1,
1,
I,
1,
1,
2,
2,
2,
2,
2,
I,
L
1,
1,
4,
2,
2"
2,
2,
2,
2,
1,
1,
I,
1,
1,
1,
1,
1,
1,
1,
1,
1,
I,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
I,
1,
1,
1,
1,
1,
1,
I,
L
L
1,
L
1,
L
1,
1,
L
1,
1,
L
1,
1,
1,
1,
1,
1,
1,
1,
2,
1,
1,
2,
L
1,
1,
1,
2, 2,
2, 2,
2,
2,
2,
2,
L
1,
1,
2,
2,
2,
1,
2,
2,
1,
2,
2,
2,
1,
2,
2,
1,
2,
1,
L
2,
2,
1,
1;
2,
2,
I.
2,
1,
L
2,
2,
1,
1,
2,
L
2,
2,
1,
1,
1,
1,
1,
1,
1,
I,
L
I,
1,
L
2,
2,
1,
2,
L
1,
2,
1,
1,
1,
1,
2,
2,
1,
2,
2,
1,
1,
4,
1,
L
1,
1,
2,
1,
1,
1,
1,
1,
1,
I,
1,
1,
L
L
1,
2,
2,
L
1,
2,
1,
2,
1,
1,
2,
2,
2,
2,
2,
2,
1,
1,
1,
2,
2,
L
2,
1,
1,
2,
1,
1,
*1
1)i
AFN·01739A
A·34
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1067
J,068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1
2
2
2
2
STEP:
PROCEDURE (NEXT$INSTRUCTION) ADDRESS PUBLIC;
DECLARE NEXT$INSTRUCTION ADDRESSi
PC=NEXT$INSTRUCTION;
OPCODE=USER$CODE(PC);
DO CASE OPCODEi
1*
INSTRUCTIONS CORRESPONDING TO ROW 0 OF OrCaDE MAP
(FORM OXH):
*1
CALL NOPi
CALL AJMP$ADDR 11 ;
CALL LJMP$ADDR 16i
CALL RR$Ai
CALL INC$A;
CALL INC$DIRi
CALL INC$INDi
CALL INC$INDi
CALL INC$REGi
CALL INC$REGi
CALL INC$REGi
CALL INC$REGi
CALL INC$REGi
CALL INC$REGi
CALL INC$REGi
CALL INC$REGi
1*
INSTRUCTIONS CORRESPONDING TO ROW 1 OF OrCaDE MAP
(FORM lXH):
*1
CALL JBC$BIT$RELi
CALL ACALL$ADDR11i
CALL LCALL$ADDR16i
CALL RRC$Ai
CALL DEC$Ai
CALL DEC$DIRi
CALL DEC$INDi
CALL DEC$INDi
CALl. DEC$REGi
CALL DEC$REGi
CALL DEC$REGi
CALL DEC$REGi
CALL DEC$REGi
CALL DEC$REG;
C,t\LL DEC$REGi
CI\LL DEC$REG;
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
.lL ':1 I=;
AFN·01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1*
INSTRUCTIONS CORRESPONDING TO ROW 2 OF OPCODE MAP
(FORM 2XH): *1
CALL JB$BIT$REL;
CALL AJMP$ADDR11;
CALL RET;
CALL RL$A;
CALL ADD$A$IMMi
CALL ADD$A$DIR;
CALL ADD$A$IND;
CALL ADD$A$IND;
CALL ADD$A$REG;
CALL ADD$A$REG;
CALL ADD$A$REG;
CALL ADD$A$REG;
CALL ADD$A$REG;
CALL ADD$A$REG;
CALL ADD$A$REG;
CALL ADD$A$REGi
1*
INSTRUCTIONS CORRESPONDING TO ROW 3 OF OPCODE MAP
(FORM 3XH): *1
CALL JNB$BIT$REL;
CALL ACALL$ADDRlli
CALL RETI;
CALL RLC$Ai
CALL ADDC$A$ I MMi
CALL ADDC$A$D I R;
CALL ADDC$A$IND;
CALL ADDC$A$IND;
CALL ADDC$A$REG;
CALL ADDC$A$REGi
CALL ADDC$A$REGi
CALL ADDC$A$REGi
CALL ADDC$A$REGi
CALL ADDC$A$REG;
CALL ADDC$A$REGi
CALL ADDC$A$REGi
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A·36
AFN·01739A
8051
PL/M-80 COMPILER
INSTRUCTION SET SIMULATOR
$EJECT
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1.155
1156
1157
1158
1139
1160
1161
1162
1163
1164
1165
1166
1167
1*
INSTRUCTIONS CORRESPONDING TO ROW 4 OF OPCODE MAP
(FORM 4XH):
*1
CALL JC$REL;
CALL AJMP$ADDR11i
CALL ORL$DIR$A;
CALL ORL$DIR$IMM;
CALL ORL$A$ I MM;
CALL ORL$A$DIRi
CALL ORL$A$IND;
CALL ORL$A$IND;
CALL ORL$A$REGi
CALL ORL$A$REGi
CALL ORL$A$REG;
CALL ORL$A$REGi
CALL ORL$A$REGi
CALL ORL$A$REG;
CALL ORL$A$REG;
CALL ORL$A$REG;
1*
INSTRUCTIONS CORRESPONDING TO ROW 5 OF OPCODE MAP
(FORM 5XH):
*1
CALL JNC$REL;
CALL ACALL$ADDR 11 .•
CALL ANL$DIR$A;
CALL ANL$DIR$IMM;
CALL ANL$A$IMM;
CALL ANL$A$DIRi
C,\LL ANL$A$IND;
CALL ANL$A$IND;
CALL. ANL$A$REG;
CALL ANL$A$REG;
C~LL ANL$A$REG;
C,\LL ANL$A$REG;
CALL ANL$A$REGi
CALL ANL$A$REG;
CALL ANL$A$REGi
CALL ANL$A$REG;
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
:3
3
3
3
3
3
A-37
AFN·01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1*
1168
1169
1170
1171
1172
1173
1114
1175
1176
I1T7
1178
1179
1180
1181
1182
1183
3
3
3
3
3
3
3
3
3
:3
3
3
3
3
3
3
1*
INSTRUCTIONS CORRESPONDING TO ROW 6 OF OPCODE MAP
(FORM 6XH):
*1
CALL JZ$RELi
CALL AJMP$ADDRlli
CALL XRL$DIR$Ai
CALL XRL$DIR$IMM;
CALL XRL$A$IMM;
ClltLL XRL$A$DIR;
CALL XRL$A$ I ND;
Cf~LL XRL$A$INDi
CALL XRL$A$REGi
C/~LL XRL$A$REG;
CALL XRL$A$REG;
Cf\LL XRL$A$REGi
CALL XRL$A$REG;
CALL XRL$A$REG;
CALL XRL$A$REG;
CALL XRL$A$REG;
INSTRUCTIONS CORRESPONDING TO ROW 7 OF OPCODE MAP
(FORM 7XH):
1184
1185
1186
t 187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
*1
JNZ$REli
ACALL$ADDRlli
ClRL$C$B I T;
JMP$ADPTRi
MOV$A$IMM;
MOV$DIR$IMM;
MOV$IND$IMM;
MOV$IND$IMMi
MOV$REG$IMM;
MOV$REG$IMMi
MOV$REG$IMMi
MOV$REG$IMMi
MOV$REG$IMM;
MOV$REG$IMM;
MOV$REG$IMM;
MOV$REG$IMM;
A-38
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1200
1201
1202
1203
1204
1205
1206
1207
INSTRUCTIONS CORRESPONDING TO ROW 8 OF OPCODE MAP
(FDRM BXH):
*1
CALL S.JMP$RELi
CALL AJMP$ADDR 11 i
CALL ANL$C$BITi
CALL MOVC$A$APC;
CALL DIV$AB;
CALL MOV$DIR$DIRi
CALL MOV$DIR$INDi
CALL MOV$DIR$INDi
CALL MOV$DIR$REGi
CALL MOV$DIR$REGi
CALL MOV$DIR$REGi
CALL MOV$DIR$REGi
CALL MOV$DIR$REGi
CALL MOV$D I R$REGi
CALL MOV$DIR$REGi
CALL MOV$DIR$REGi
1*
INSTRUCTIONS CORRESPONDING TO ROW 9 OF OPCODE MAP
(FORM 9XH):
*1
CALL MOV$DPTR$IMM16;
CALL ACALL$ADDR11;
CALL MOV$BIT$C;
CALL MOVC$A$ADPTRi
CALL SUBB$A$IMMi
CALL SUBB$A$DIR;
CALL SUBB$A$IND;
CALL SUBB$A$INDi
CALL SUBB$A$REGi
CALL SUBB$A$REG;
CALL SUBB$A$REG;
CALL SUBB$A$REG;
CALL SUBB$A$REG;
CALL SUBB$A$REGi
CALL SUBB$A$REGi
CALL SUBB$A$REG;
3
3
3
3
3
3
3
3
1208
3
1209
1210
1211
1212
1213
1214
1215
3
1216
1217
1;;!18
·'.219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1*
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A-39
AFN·01739A
8051 INSTRUCTION SET SIMULATOR
PL/M-80 COMPILER
$EdECT
1232
1233
1234
1235
12~J6
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
124'7
1248
1249
12~iO
1251
1252
1253
1254
12~j5
1256
1257
1258
1259
1260
1261
1262
1263
lit-
INSTRUCTIONS CORRESPONDING TO ROW A OF OPCODE MAP
(FORM AXH):
*1
CALL ORL$C$COMP$BIT;
CALL AJMP$ADDR11;
CALL MOV$C$BITi
CALL INC$DPTRi
CALL MUL$AB;
C/\LL NOP;
CALL MOV$IND$DIRi
CAL.L MOV$IND$DIRi
CALL MOV$REG$DIR;
CALL MOV$REG$DIRi
CALL MOV$REG$DIRi
CALL MOV$REG$DIR;
CALL MOV$REG$DIR;
CALL MOV$REG$DIRi
CAL.L MOV$REG$DIRi
CALL MOV$REG$D I R;
1*
INSTRUCTIONS CORRESPONDING TO ROW D OF OPCODE MAP
(FORM BXH):
*1
CALL ANL$C$COMP$BIT;
CALL ACALL$ADDR11;
CALL CPL$BIT;
CALL CPL$C;
CALL CJNE$A$IMM$REL;
CALL CJNE$A$DIR$REL;
CALL CJNE$IND$IMM$RELj
CALL CJNE$IND$IMM$REL;
CALL CJNE$REG$IMM$REL;
Cf~LL CJNE$REG$IMM$REL;
CALL CJNE$REG$IMM$REL;
CALL CJNE$REG$IMM$REL;
CALL CJNE$REG$IMM$RELi
CALL CJNE$REG$IMM$RELi
CALL CJNE$REG$IMM$REL;
CALL. CJNE$REG$IMM$RELi
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A·40
AFN·01739A
8051 INSTRUCTION SET SIMULATOR
PL/M-80 COMPILER
$EdECT
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1.283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1*
INSTRUCTIONS CORRESPONDING TO ROW C OF OPCODE MAP
(FORM CXH):
*1
CALL PUSH$DIRi
CALL AJMP$ADDR 11 i
CALL CLR$BITi
Cf\LL CLR$Ci
CALL SWAP$A;
CALL XCH$A$DIR;
Cf\LL XCH$A$INDi
CALL XCH$A$IND;
CALL XCH$A$REG;
CALL XCH$A$REGi
CALL XCH$A$REG;
CALL XCH$A$REG;
CALL XCH$A$REG;
CALL XCH$A$REG;
CALL XCH$A$REG;
CALL XCH$A$REG;
1'11:
INSTRUCTIONS CORRESPONDING TO ROW D OF OPCODE MAP
(FORM DXH):
*1
CALL POP$DIR;
CALL ACALL$ADDR11;
CALL SETB$B IT;
CALL SETB$C;
CALL DA$A;
CALL DJNZ$D I R$REL
CALL XCHD$A$INDi
CALL XCHD$A$IND;
CALL DJNZ$REG$REL;
CALL DJNZ$REG$REL;
CALL DJNZ$REG$REL;
CALL DJNZ$REG$REL;
CALL DJNZ$REG$REL
CALL DJNZ$REG$REL;
CALL DJNZ$REG$REL;
CALL DJNZ$REG$REL;
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A-41
AFN-01739A
PL/M-80 COMPILER
8051 INSTRUCTION SET SIMULATOR
$EJECT
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1*
INSTRUCTIONS CORRESPONDING TO ROW E OF OPCODE MAP
(FORM EXH): *1
CALL MOVX$A$DPTR;
CALL AJMP$ADDR11;
CALL MOVX$A$IND;
CALL MOVX$A$ I NO;
CALL CLR$A;
CALL MOV$A$DIR;
CALL MOV$A$IND;
CALL MOV$A$INDi
CALL MOV$A$REG;
CALL MOV$A$REGi
CALL MOV$A$REG;
CALL MOV$A$REG;
CALL MOV$A$REG;
CALL MOV$A$REG;
CALL MOV$A$REG;
CALL MOV$A$REG;
1*
INSTRUCTIONS CORRESPONDING TO ROW F OF OPCODE MAP
(FORM FXH): *1
CALL MOVX$DPTR$Ai
CALL ACALL$ADDR11;
CALL MOVX$IND$Ai
CALL MOVX$IND$Ai
CALL CPL$Ai
CALL MOV$DIR$A;
CALL MOV$IND$Ai
CALL MOV$IND$A;
CALL MOV$REG$Ai
CALL. MOV$REG$A;
CALL MOV$REG$A;
CALL MOV$REG$A;
CALL MOV$REG$Ai.
CALL MOV$REG$Ai
CALL MOV$REG$A;
CALL MOV$REG$A;
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1328
3
1329
1330
1331
1332
2
2
2
PSW=(PSW AND 11111110B) + PARITY$STATE(ACC);
MACH$CYC=MACH$CYC + EXECUTION$TIMECOPCODE)i
RETURN PCi
END STEP;
1333
1
END SIMS1;
?
END;
A·42
AFN·01739A
I
APPLICATIONS
vss
P1.0
vee
P1.1
P1.2
PO.1
P1.3
PO.2
P1.4
PO.3
P1.S
P1.&
PO.4
PO.S
P1.7
PO.&
PO.7
VPD/RST
VDD/EA
P3.1/TXD
PROG/ALE
PSEN
P3.3.1NT1
P2.7
P3.4/TO
P3.S/T1
P2.6
P3.6/WR
P2.4
P2.3
P3.7/RD
XTAL2
RSTIVPD
po.o
P3.0/RXD
P3.2/INTO
vee
RXD
I
TXD
P2.S
INTO
001
PORT 3
P2.2
XTAL1
P2.1
VSS
P2.0
TO
T1
WR
Ro
Figure 1a. 8051 Microcomputer Pinout Diagram
Figure 1b. 8051 Microcomputer Logic Symbol
some microprocessor (preferably Intel's, of course) or
have a background in computer programming and digital
logic.
1. INTRODUCTION
In 1976 Intel introduced/the' MCS-48™ family, consisting
of the 8048, 8748, and 8035 microcomputers. These parts
marked the first time a complete microcomputer system,
including an eight-bit CPU, 1024 8-bit words of ROM
or EPROM program memory, 64 words of data memory,
I/O ports and an eight-bit timer/counter could be integrated onto a single silicon chip. Depending only on the
program memory contents, one chip could control a
limitless variety of products, ranging from appliances or
automobile engines to text or data processing equipment.
Follow-on products stretched the MCS-48™ architecture
in several directions: the 8049 and 8039 doubled the
amount of on-chip memory and ran 83% faster; the 8021
reduced costs by executing a subset of the 8048 instructions with a somewhat slower clock; and the 8022 put a
unique two-channel 8-bit analog-to-digital converter on
the same NMOS chip as the computer, letting the chip
interface directly with analog transducers.
Family Overview
Pinout diagrams for the 8051, 8751, and 8031 are shown
in Figure I. The devices include the following features:
• Single-supply 5 volt operation using HMOS technology.
• 4096 bytes program memory on-chip (not on 8031).
• 128 bytes data memory on-chip.
• Four register banks.
• 128 User-defined software flags.
• 64 Kilobytes each program and external RAM
addressability.
• One microsecond instruction cycle with 12 MHz
crystal.
• 32 bidirectional I/O lines organized as four 8-bit
ports (16 lines on 8031).
• Multiple mode, high-speed programmable Serial
Port.
• Two mUltiple mode, 16-bit Timer/Counters.
• Two-level prioritized interrupt structure.
• Full depth stack for subroutine return linkage and
data storage.
• Augmented MCS-48™ instruction set.
• Direct Byte and Bit addressability.
• Binary or Decimal arithmetic.
• Signed-overflow detection and parity computation.
• Hardware Multiple and Divide in 4 usec.
• Integrated Boolean Processor for control applications.
• Upwardly compatible with existing 8048 software.
Now three new high-performance single-chip microcomputers-the Intel® 8051, 8751, and 8031-extend the
advantages of Integrated Electronics to whole new product areas. Thanks to Intel's new HMOS technology, the
MCS-5ITM family provides four times the program
memory and twice the data memory as the 8048 on a
single chip. New I/O and peripheral capabilities both
increase the range of applicability and reduce total system
cost. Depending on the use, processing throughput
increases by two and one-half to ten times.
This Application Note is intended to introduce the reader
to the M CS-51 ™architecture and features. While it does
not assume intimacy with the MCS-48™ product line on
the part of the reader, he/she should be familiar with
AFN-01502A
B-1
APPLICATIONS
All three devices come in a standard 40-pin Dual InLine Package, vlith the same pin-out, the same timing,
and the same electrical characteristics. The primary
difference between the three is the on-chip program
memory-different types are offered to satisfy differing
user requirements.
ware application examples illustrate many of the concepts.
Several, isolated tasks (rather than one complete system
design example) are presented in the hope that some of
them will apply to the reader's experiences or needs.
A document this short cannot detail all of a computer
system's capabilities. By no means will all the 8051 instructions be demonstrated; the intent is to stress new or
unique MCS_5ITM operations and instructions generally
used in conjunction with each other. For additional hardware information refer to the Intel MCS-5rM Family
User's Manual, publication number 121517. The assembly
language and use of ASM51, the MCS_5ITM assembler,
are further described in the MCS-5J™ Macro Assembler
User's Guide, publication number 9800937.
The 8751 provides 4K bytes of ultraviolet-Erasable,
Programmable Read Only Memory (EPROM) for
program development, prototyping, and limited production runs. (By convention, 1K means 210 = 1024.
lk-with a lower case "k"-equals 103 = 1000.) This part
may be individually programmed for a specific application using Intel's Universal PROM Programmer (UPP).
If software bugs are detected or design specifications
change the same part may be "erased" in a matter of
minutes by exposure to ultraviolet light and reprogrammed with the modified code. This cycle may be
repeated indefinitely during the design and development
phase.
The next section reviews some of the basic concepts
of microcomputer design and use. Readers familiar
with the 8048 may wish to skim through this section
or skip directly to the next, "ARCHITECTURE AND
ORGANIZATION."
The final version of the software must be programmed
into a large number of production parts. The 8051 has
4K bytes of ROM which are mask-programmed with the
customer's order when the chip is built. This part is considerably less expensive, but cannot be erased or altered
after fabrication.
Microcomputer Background Concepts
Most digital computers use the binary (base 2) number
system internally. All variables. constants, alphanumeric
characters, program statements, etc., are represented by
groups of binary digits ("bits"), each of which has the
value 0 or I. Computers are classified by how many bits
they can move or process at a time.
The 8031 does not have any program memory on-chip,
but may be used with up to 64K bytes of external standard
or multiplexed ROMs, PROMs, or EPROMs. The 8031
fits well in applications requiring significantly larger or
smaller amounts of memory than the 4K bytes provided
by its two siblings.
The MCS-5ITM microcomputers contain an eight-bit
central processing unit (CPU). Most operations process
variables eight bits wide. All internal RAM and ROM,
and· virtually all other registers are also eight bits wide.
An eight-bit ("byte") variable (shown in Figure 2) may
assume one of 28 = 256 distinct values, which usually
represent integers between 0 and 255. Other types of
numbers, instructions, and so forth are represented by
one or more bytes using certain conventions.
(The 8051 and 8751 automatically access external program memory for all addresses greater than the 4096 bytes
on-chip. The External Access input is an override for
all internal program memory-the 8051 and 8751 will
each emulate an 8031 when pin 31 is low.)
Throughout this Note, "8051" is used as a generic term.
Unless specifically stated otherwise, the point applies
equally to all three components. Table 1 summarizes the
quantitative differences between the members of the
MCS-48™ and MCS-51TM families.
For example, to represent positive and negative values,
the most significant bit (07) indicates the sign of the other
seven bits-O if positive, I if negative-allowing integer
variables between -128 and +127. For integers with
extremely large magnitudes, several bytes are manipulated together as "multiple precision" signed or unsigned
integers-16, 24, or more bits wide.
The remaind~r of this Note discusses the various M CS-51 ™
features and how they can be used. Software and/or hard-
Table 1. Features of Intel's Single-Chip Microcomputers
EPROM
Program
Memory
-
8748
-
8751
ROM
Program
Memory
8021
8022
8048
8049
8051
External
Program
Memory
-
8035
8039
8031
Program
Memory
(Int!Max)
Data
Memory
(Bytes)
Instr.
Cycle
Time
Input!
Output
Pins
Interrupt
Sources
Reg.
Banks
IK/IK
2K/2K
.IK/4K
2K/4K
4K/64K
64
64
64
128
128
8.4pSec
8.4fiSec
2.5 pSec
1.36 fiSec
1. 0 IJ Sec
21
28
27
27
32
0
2
2
2
5
I
I
2
2
4
AFN-01502A
B·2
APPLICATIONS
a single character, and a word or sequence of letters may
be represented by a series (or "string") of bytes. Since the
ASCII code only uses 128 characters, the most significant
bit of the byte is not needed to distinguish between characters. Often D7 is set to 0 for all characters. In some
coding schemes, D7 is used to indicate the "parity" of the
other seven bits-set or cleared as necessary to ensure
that the total number of "I" bits in the eight-bit code is
even ("even parity") or odd ("odd parity"). The 8051
includes hardware to compute parity when it is needed.
The letters "MCS" have traditionally indicated
a system or family of compatible Intel® microcomputer components, including CPUs, memories, clock generators, I/O expanders, and so
forth. The numerical suffix indicates the microprocessor or microcomputer which serves as
the cornerstone of the family. Microcomputers
in the MCS-48T11 family currently include the
8048-series (8035, 8048, & 8748), the 8049-series
(8039 & 8049), and the 8021 and 8022; the
family also includes the 8243, an I/O expander
compatible with each of the microcomputers.
Each computer's CPU is derived from the 8048,
with essentially the same architecture, addressing modes, and instruction set, and a single
assembler (ASM48) serves each.
A computer program consists of an ordered sequence of
specific, simple steps to be executed by the CPU one-ata-time. The method or sequence of steps used collectively
to solve the user's application is called an "algorithm."
The program is stored inside the computer as a sequence
of binary numbers, where each number corresponds to
one of the basic operations ("opcodes") which the CPU
is capable of executing. In the 8051, each program
memory location is one byte. A complete instruction
consists of a sequence of one or more bytes, where the
first defines rhe operation to be executed and additional
bytes (if needed) hold additional information, such as
data values or variable addresses. No instruction is longer
than three bytes.
The first members of the MCS-51T11 family are
the 8051, 8751, and 8031. The architecture of
the 8051-series, while derived from the 8048,
is not strictly compatible; there are more
addressing modes, more instructions, larger
address spaces, and a few other hardware differences. In this Application Note the letters
"MCS-51" are used when referring to architectural features of the 8051-'series-features
which would be included on possible future
microcomputers based on the 8051 CPU. Such
products could have different amounts of
memory (as in the 8048/8049) or different
peripheral functions (as in the 8021 and 8022)
while leaving the CPU and instruction set
intact. ASM51 is the assembler used by all
microcomputers in the 8051 family.
The way in which binary opcodes and modifier bytes are
assigned to the CPU's operations is called the computer's
"machine language." Writing a program directly in
machine language is time-consuming and tedious. Human
beings think in words and concepts rather than encoded
numbers, so each CPU operation and resource is given a
name and standard abbreviation ("mnemonic"). Programs
are more easily discussed using these standard mnemonics,
or "assembly language," and may be typed into an Intel®
Intellec® 800 or Series II® microcomputer development
system in this form. The development system can mechanically translate the program from assembly language
"source" form to machine language "object" code using a
program called an "assembler." The MCS_5ITM assembler
is called AS M51.
Two digit decimal numbers may be "packed" in an eightbit value, using four bits for the binary code of each digit.
This is called Binary-Coded Decimal (BCD) representation, and is often used internally in programs which
interact heavily with human beings.
There are several important differences between a computer's machine language and the assembly language used
as a tool to represent it. The machine language or instruction set is the set of operations which the CPU can
perform while a program is executing ("at run-time"), and
is strictly determined by the microcomputer hardware
design.
Alphanumeric characters (letters, numbers, punctuation
marks, etc.) are often represented using the American
Standard Code for Information Interchange (ASCII)
convention. Each character is associated with a unique
seven-bit binary number. Thus one byte may represent
07
06
05
04
03
02
01
The assembly language is a standard (though more-orless arbitrary) set of symbols including the instruction set
mnemonics, but· with additional features which further
simplify the program design process. For example,
ASM51 has controls for creating and formatting a program listing, and a number of directives for allocating
variable storage and inserting arbitrary bytes of data into
the object code for creating tables of constants.
DO
Figure 2. Representation of Bits Within an Eight-Bit
"Byte" (Value shown = 01010001 Binary =
81 decimal).
AFN-01S02A
B·3
APPLICATIONS
assembly language by a series of ones and zeros
(naiuraiiy), foHowed by the ietter "B" (for Binary); octal
numbers as a series of octal digits (0-7) followed by the
letter "0" (for Octal) or "Q" (which doesn't stand for anything, but looks sort of like an "0" and is less likely
to be confused with a zero).
In addition, ASM51 can perform sophisticated mathematical operations, computing addresses or evaluating
arithmetic expressions to relieve the programmer from
this drudgery. However, these calculations can only use
information known at "assembly time."
For example, the 8051 performs arithmetic calculations
at run-time, eight bits at a time. ASM51 can do similar
operations 16 bits at a time. The 8051 can only do one
simple step per instruction, while ASM51 can perform
complex calculations in each line of source code. However, the operations performed by the assembler may only
use parameter values fixed at assembly-time, not variables
whose values are unknown until program execution
begins.
Hexadecimal numbers are represented by a series of hexadecimal digits (0-9,A-F), followed by (you guessed it) the
letter "H." A "hex" number must begin with a decimal
digit; otherwise it would look like a user-defined symbol
(to be discussed later). A "dummy" leading zero may be
inserted before the first digit to meet this constraint. The
character string "BACH" could be a legal label for a
Baroque music synthesis routine; the string "OBACH" is
the hexadecimal constant BAC I6 • This is a case where
adding 0 makes a big difference.
For example, when the assembly language source line,
ADD
A,#(LOOP_COUNT + I)
*3
Decimal numbers are represented by a sequence of decimal
digits, optionally followed by a "D." If a number has no
suffix, it is assumed to be decimal-so it had better not
contain any non-decimal digits. "OBAC" is not a legal
representation for anything.
is assembled, AS M51 will find the value of the previously-defined constant "LOOP_COUNT" in an internal
symbol table, increment the value, multiply the sum by
three, and (assuming it is between -256 and 255 inclusive)
truncate the product to eight bits. When this instruction
is executed, the 8051 ALU will just add that resulting
constant to the accumulator.
When an ASCII code is needed in a program, enclose the
desired character between two apostrophes (as in '#') and
the assembler will convert it to the appropriate code (in
this case 23H). A string of characters between apostrophes is translated into a series of constants; 'BACH'
becomes 42H, 41 H, 43H, 48H.
Some similar differences exist to distinguish number
system ("radix") specifications. The 8051 does all computations in binary (though there are provisions for then
converting the result to decimal form). In the course of
writing a program, though, it may be more convenient
to specify constants using some other radix, such as base
Hr. On other occasions, it is desirable to specify the ASCII
code for some character or string of characters without
refering to tables. ASM51 allows several representations
for constants, which are converted to binary as each
instruction is assembled.
These same conventions are used throughout the associated Intel documentation. Table 2 illustrates some of the
different number formats.
2. ARCHITECTURE AND ORGANIZATION
Figure 3 blocks out the MCS_5ITM internal organization.
Each microcomputer combines a Central Processing
Unit, two kinds of memory (data RAM plus program
ROM or EPROM), Input/ Output ports, and the mode,
For example, binary numbers are represented in the
Table 2. Notations Used to Represent Numbers
Bit Pattern
Binary
HexaDecimal
Decimal
Signed
Decimal
OQ
IQ
OOH
OIH
IIIB
1000B
lOOIB
10 lOB
07H
08H
09H
OAH
...............
..
7Q
IOQ
llQ
12Q
0
I
.,
7
8
9
10
0 1 1 1 1
00010000
I11IB
lOOOOB
17Q
20Q
OFH
IOH
15
16
..
. ...
+15
+16
. ...
IIIIIIIB
10000000B
1000000lB
177Q
200Q
20lQ
7FH
80H
81H
127
128
129
+127
-128
-127
OFEH
OFFH
254
255
00000000
0 000 1
o0 0
...............
00000111
0 0 0 1 000
000 100 1
0 0 0 1 0 1 0
o
o
o
o0 0
........ ......
o1111111
~
10000000
10000001
OB
IB
Octal
..
..
. ..
. ..
. ..
...............
........
...
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
1IIIll1OB
IIIIIIIIB
376Q
377Q
. ..
...
...
. ..
..
.. ,
0
+1
....
+7
+8
+9
+10
'0' •
-2
-I
AFN·01502A
8-4
APPLICATIONS
TL1
TH1
TIMER
CONTROL
Figure 3. Block Diagram of 8051 Internal Structure
status, and data registers and random logic needed for
a variety of peripheral functions. These elements communicate through an eight-bit data bus which runs
throughout the chip, somewhat akin to indoor plumbing.
This bus is buffered to the outside world through an I/O
port when memory or I/O expansion is desired.
Let's summarize what each block does; later chapters dig
into the CPU's instruction set and the peripheral registers
in much greater detail.
Central Processing Unit
The CPU is the "brains" of the microcomputer, reading
the user's program and executing the instructions stored
therein. Its primary elements are an eight-bit Arithmetic/
Logic Unit with associated registers A, B, PSW, and SP,
and the sixteen-bit Program Counter and "Data Pointer"
registers.
AFN-01502A
8-5
APPLICATIONS
Arithmetic Logic Unit
•
•
•
•
•
The ALU can perform (as the name implies) arithmetic
and logic functions on eight-bit variables. The former
include basic addition, subtraction, multiplication, and
division; the latter include the logical operations AND,
OR, and Exclusive-OR, as well as rotate, clear, complement, and so forth. The ALU also makes conditional
branching decisions, and provides data paths and temporary registers used for data transfers within the system.
Other instructions are built up from these primitive functions: the addition capability can increment registers or
automatically compute program destination addresses;
subtraction is also used in decrementing or comparing the
magnitude of two variables.
Arithmetic Operations
Logical Oper~tions for Byte Variables
Data Transfer Instructions
Boolean Variable Manipulation
Program Branching and Machine Control
MCS:''48™ programmers perusing Table 4 will notice the
absence of special categories for Input/Output, Timer/
Counter, or Control instructions. These functions are all
still provided (and indeed many new functions are added),
but as special cases of more generalized operations in
other categories. To explicitly list all the useful instructions involving I/O and peripheral registers would require
a table approximately four times as long.
Observant readers will also notice that all of the 8048's
page-oriented instructions (conditional jumps, JMPP,
MOVP, MOVP3) have been replaced with corresponding
but non-paged instructions. The 8051 instruction set is
entirely non-page-oriented. The MCS-48™ "MOVP"
instruction replacement and all conditional jump instructions operate relative to the program counter, with the
actual jump address computed by the CPU during instruction execution. The "MOVP3" and "JMPP" replacements
are now made relative to another sixteen-bit register,
which allows the effective destination to be anywhere in
the program memory space, regardless of where the
instruction itself is located. There are even three-byte
jump and call instructions allowing the destination to be
anywhere in the 64K program address space.
These primitive operations are automatically cascaded
and combined with dedicated logic to build complex
instructions such as incrementing a sixteen-bit register
pair. To execute one form of the compare instruction, for
example, the 8051 increments the program counter three
times, reads three bytes of program memory, computes a
register address with logical operations, reads internal
data memory twice, makes an arithmetic comparison of
two variables, computes a sixteen-bit destination address,
and decides whether or not to make a branch-all in two
microseconds!
An important and unique feature of the MCS-51 architecture is that the ALU can also manipulate one-bit as
well as eight-bit data types. Individual bits may be set,
cleared, or complemented, moved, tested, and used in
logic computations. While support for a more primitive
data type may initially seem a step backwards in an era
of increasing word length, it makes the 8051 especially
well suited for controller-type applications. Such algorithms inherently involve Boolean (true/false) input
and output variables, which were heretofore difficult to
implement with standard microprocessors. These features
are collectively referred to as the MCS-51 ™ "Boolean
Processor," and are described in the so-named chapter
to come.
The instruction set is designed to make programs efficient
both in terms of code size and execution speed. No
instruction requires more than three bytes of program
memory, with the majority requiring only one or two
bytes. Virtually all instructions execute in either one or
two instruction cycles-one or two microseconds. with
a 12-MHz crystal-with the sole exceptions (multiply
and divide) completing in four cycles.
Many instructions such as arithmetic and logical functions or program control, provide both a short and a long
form for the same operation, allowing the programmer
to optimize the code produced for a specific application.
The 8051 usually fetches two instruction bytes per instruction cycle, so using a shorter form can lead to faster
execution as well.
Thanks to this powerful ALU, the 8051 instruction set
fares well at both real-time control and data intensive
algorithms. A total of 51 separate operations move and
manipulate three data types: Boolean (I-bit), byte (8-bit),
and address (l6-bit). All told, there are eleven addressing
modes-seven for data, four for program -;equence control (though only eight are used by more than just a few
specialized instructions). Most operations allow several
addressing modes, bringing the total number of instructions (operation/addressing mode combinations) to Ill,
encompassing 255 of the 256 possible eight-bit instruction opcodes.
For example, any byte of RAM may be loaded with a
constant with a three-byte, two-cycle instruction, but the
commonly used "working registers" in RAM may be
initialized in one cycle with fl two-byte form. Any bit
anywhere on the chip may be set, cleared, or complemented by a single three-byte logical instruction using
two cycles. But critical control bits, I/O pins, and software flags may be controlled by two-byte, single cycle
instructions. While three-byte jumps and calls can "go
anywhere" in program memory, nearby sections of code
may be reached by shorter relative or absolute versions.
Instruction Set Overview
Table 4 lists these III instructions classified into five
groups:
AFN-01S02A
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APPLICATIONS
(MSB)
I I
CY
(LSB)
AC
FO
Symbol Position
CY
PSW.7
RS1
RSO
OV
Symbol Position
OV
PSW.2
I I
p
Name and Significance
Carry flag.
Set/cleared by hardware or software
during certain arithmetic and logical
instructions.
P
AC
PSW.6
Auxiliary Carry flag.
Set/cleared by hardware during addition
or subtraction instructions to indicate
carry or borrow out of bit 3.
FO
PSW.5
Flag 0
Set / cleared / tested by software as a
user-defined status flag.
RSI
PSW.4
RS
PSW.3
Register bank Select control bits I & O.
Set/cleared by software to determine
working register bank (see Note).
Name and Significance
Overflow flag.
Set/cleared by hardware during arithmetic instructions to indicate overflow
conditions.
PSW.I
(reserved)
PSW.O
Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e., even parity.
Note-
the contents of (RSI, RSO) enable the
working register banks as follows:
(O,O)-Bank 0
(O,I)-Bank I
(I ,D)-Bank 2
(I,I)-Bank 3
(DOH-07H)
(OSH-OFH)
(IOH-I7H)
(ISH-IFH)
Figure 4. PSW-Program Status Word' Organization
A significant side benefit of an instruction set more
powerful than those of previous single-chip microcomputers is that it is easier to generate applications-oriented
software. Generalized addressing modes for byte and bit
instructions reduce the number of source code lines
written and debugged for a given application. This leads
in turn to proportionately lower software costs, greater
reliability, and faster design cycles.
and rotates. The carry also serves as a "Boolean accumulator" for one-bit logical operations anp bit manipulation
instructions. The overflow flag (OV) detects when arithmetic overflow occurs on signed integer operands, making
two's complement arithmetic possible. The parity flag
(P) is updated after every instruction cycle with the evenparity ()f the accumulator contents.
The CPU does not control the two register-bank select
bits, RS I and RSO. Rather, they are manipulated by
software to enable one of the four register banks. The
usage of the PS W flags is demonstrated in the Instruction Set chapter of this Note.
Accumulator and PSW
The 8051, like its 8048 predecessor, is primarily an
accumulator-based architecture: an eight-bit register
called the accumulator ("A") holds a source operand and
receives the result of the arithmetic instructions (addition,
subtraction, multiplication, and division). The accumulator can be the source or destination for logical operations
and a number of special data movement instructions,
including table look-ups and external RAM expansion.
Several functions apply exclusively to the accumulator:
rotates, parity computation, testing for zero, and so on.
Even though the architecture is accumulator-based, provisions have been made to bypass the accumulator in
common instruction situations. Data may be moved from
any location on-chip to any register, address, or indirect
address (and vice versa), any register may be loaded with
a constant, etc., all without affecting the accumulator.
Logical operations may be performed against registers or
variables to alter fields of bits-without using or affecting
the accumulator. Variables may be incremented, decremented, or tested without using the accumulator. Flags
and control bits may be manipulated and tested without
affecting anything else.
Many instructions implicitly or explicitly affect (or are
affected by) several status flags, which are grouped
together to form the Program Status Word shown in
FIgure 4.
(The period within entries under the Position column is
called the "dot operator," and indicates a particular bit
position within an eight-bit byte. "PSW.5" specifies bit 5
of the PSW. Both the documentation and ASM51 use
this notation.)
Other CPU Registers
A special eight-bit register ("B")'serves in the execution of
the multiply and divide instructions. This register is used
in conjunction with the accumulator as the second input
operand and to return eight-bits of the result.
The most "active" status bit is called the carry flag (abbreviated "C"). This bit makes possible multiple precision
arithmetic operations including addition, subtraction,
The MCS-51 family processors include a hardware stack
within internal RAM, useful' for subroutine linkage,
AFN-01502A
8-7
APPLICATIONS
are addressed using the Program Counter or instructions
which generate a sixit:t::n-bit address.
passing parameters between routines, temporary variable
storage, or saving status during interrupt service routines.
The Stack Pointer (SP) is an eight-bit pointer register
which indicates the address of the last byte pushed onto
the stack. The stack pointer is automatically incremented
or decremented on all push or pop instructions and all
subroutine calls and returns. In theory, the stack in the
8051 may be up to a full 128 bytes deep. (In practice, even
simple programs would use a handful of RAM locations
for pointers, variables, and so forth-reducing the stack
depth by that number.) The stack pointer defaults to 7 on
reset, so that the stack will start growing up from location
8, just like in the 8048. By altering the pointer contents the
stack may be relocated anywhere within internal RAM.
To stretch our analogy just a bit, data memory is like a
mouse: it is smaller and therefore quicker than program
memory, and it goes into a random state when electrical
power is applied. On-chip data RAM is used for variables
which are determined or may change while the program
is running.
A computer spends most of its time manipulating variables, not constants, and a relatively small number of
variables at that. Since eight-bits is more than sufficient
to uniquely address 128 RAM locations, the on-chip
RAM address register is only one byte wide. In contrast
to the program memory, data memory accesses need a
single eight-bit value-a constant or another variableto specify a unique location. Since this is the basic width
of the ALU and the different memory types, those
resources can be used by the addressing mechanisms,
contributing greatly to the computer's operating efficiency.
Finally, a 16-bit register called the data pointer (DPTR)
serves as a base register in indirect jumps, table look-up
instructions, and external data transfers. The high- and
low-order halves of the data pointer may be manipulated
as separate registers (DPH and DPL, respectively) or
together using special instructions to load or increment
all sixteen bits. Unlike the 8048, look-up tables can therefore start anywhere in program memory and be of
arbitrary length.
The partitioning of program and data memory is extended
to off-chip memory expansion. Each may be added
independently, and each uses the same address and data
busses, but with different control signals. External program memory is gated onto the external data bus by the
PSEN (Program Store Enable) control output, pin 29.
External data memory is read onto the bus by the RD
output, pin 17, and written with data supplied from the
microcomputer by the WR output, pin 16. (There is no
control pin to write external program ROM, which is by
definition Read Only.) While both types may be expanded
to up to 64K bytes, the external data memory may
optionally be expanded in 256 byte "pages" to preserve
the use of P2 as an I/O port. This is useful with a relatively
small expansion RAM (such as the Intel® 8155) or for
addressing external peripherals.
Single-chip controller programs are finalized during the
project design cycle, and are not modified after production. Intel's single-chip microcomputers are not "von
Neumann" architectures common among main-frame
and mini-computer systems: the MCS-5ITM processor
data memory-on-chip and external-may not be used
for program code. Just as there is no write-control signal
for program memory, there is no way for the CPU to
execute instructions out of RAM. In return, this concession allows an architecture optimized for efficient
controller applications: a large, fixed program located in
ROM, a hundred or so variables in RAM, and different
methods for efficiently addressing each.
Memory Spaces
Program memory is separate and distinct from data
memory. Each memory type has a different addressing
mechanism, different control signals, and a different
function.
The program memory array (ROM or EPROM), like an
elephant, is extremely large and never forgets information, even when power is removed. Program memory is
used for information needed each time power is applied:
initialization values, calibration constants, keyboard
layout tables, etc., as well as the program itself. The program memory has a sixteen-bit address bus; its elements
(Von Neumann machines are helpful for software development and debug. An 8051 system could be modified to
have a single off-chip memory space by gating together
the two memory-read controls (PSEN and RD) with a
two-input AND gate (Figure 5). The CPU could then
write data into the common memory array using WR and
AFN-01S02A
8-8
APPLICATIONS
8051
WI!
~ J.fE'MWR}
L..-_ _ _I5"§'EliI_Im......
MEM RD
TO
MEMORY
ARRAY
Figure 5. Combining External Program and Data
Memory Arrays
external data transfer instructions, and read instructions
or data with the AND gate output and data transfer or
program memory look-up instructions.)
In addition to the memory arrays, there is (yet) another
(albeit sparsely populated) physical address space. Connected to the internal data bus are a score of specialpurpose eight-bit registers scattered throughout the chip.
Some of these-B, SP, PSW, DPH, and DPL-have
been discussed above. Others-I/O ports and peripheral
function registers-will be introduced in the following
sections. Collectively, these registers are designated as the
"special-function register" address space. Even the accumulator is assigned a spot in the special-function register
address space for additional flexibility and uniformity.
Input/Output Ports
The MCS-51'M I/O port structure is extremely versatile.
The 8051 and 8751 each have 32 I/O pins configured as
four eight-bit parallel ports (PO, PI, P2, and P3). Each pin
will input or output data (or both) under software control, and each may be referenced by a wide repertoire of
byte and bit operations.
Thus, the MCS-5I™ architecture supports several distinct
"physical" address spaces, functionally separated at the
hardware level by different addressing mechanisms, read
and write control signals, or both:
•
•
•
•
•
On-chip program memory;
On-chip data memory;
Off-chip program memory;
Off-chip data memory;
On-chip special-function registers.
In various operating or expansion modes, some of these
I/O pins are also used for special input or output functions. Instructions which access external memory use
Port 0 as a multiplexed address/data bus: at the beginning
of an external memory cycle eight bits of the address are
output on PO; later data is transferred on the same eight
pins.· External data transfer instructions which supply
a sixteen-bit address, and any instruction accessing
external program memory, output the high-order eight
bits on P2 during the access cycle. (The 8031 always uses
the pins of PO and P2 for external addressing, but PI and
P3 are available for standard I/O.)
What the programmer sees, though, are "logical" address
spaces. For example, as far as the programmer is
concerned, there is only one type of program memory,
64K bytes in length. The fact that it is formed by combining on- and off-chip arrays (split 4K/60K on the 8051
and 8751) is "invisible" to the programmer; the CPU
automatically fetches each byte from the appropriate
array, based on its address.
(Presumably, future microcomputers based on the
MCS_5ITM architecture may have a different physical split,
with more or less of the 64K total implemented on-chip.
Using the MCS-48™ family as a precedent, the 8048's 4K
potential program address space was split I K/ 3K between
on- and off-chip arrays; the 8049's was split 2K/2K.)
The eight pins of Port 3 (P3) each have a special function.
Two external interrupts, two counter inputs, two serial
data lines, and two timing control strobes use pins of P3
as described in Figure 6. Port 3 pins corresponding to
functions not used are available for conventional I/O.
Even within a single port, I/O functions may be combined
in many ways: input and output may be performed using
different pins at the same time, or the same pins at different
times; in parallel in some cases, and in serial in others; as
test pins, or (in the case of Port 3) as additional special
functio"ns.
Why go into such tedious details about address spaces?
The logical addressing modes are described in the Instruction Set chapter in terms of physical address spaces.
Understanding their differences now will payoff in understanding and using the chips later.
AFN-01502A
B-9
APPLICATIONS
(MSB)
I
(LSB)
RD I WR
T1
TO
IINT1 I INTO I TXD I RXD
I
Symbol Position Name and Significance
RD
P3.7
Read data control output. Active low
pulse generated by hardware when
external data memory is read.
WR
P3.6
Write data control output. Active low
pulse generated by hardware when
external data memory is written.
Tl
P3.5
Timer/counter I external input or test
pin.
TO
P3.4
Timer/counter 0 external input or test
pin.
Symbol Position
INTI
P3.3
Name and Significance
Interrupt I input pin. Low-level or
falling-edge triggered.
INTO
P3.2
Interrupt 0 input pin. Low-level or
faUing-edge triggered.
TXD
P3.1
Transmit Data pin for serial port in
UART mode. Clock output in shift
register mode.
RXD
P3.0
Receive Data pin for serial port in
UART mode. Data I/O pin in shift
register mode.
.
Figure 6. P3-Alternate Special Functions of Port 3
software-accessible). These registers are called, naturally
enough, THO, TLO, THI, and TLl. Each pair may be
independently software programmed to any of a dozen
modes with a mode register designated TMOD (Figure
7), and controlled with register TCON (Figure 8).
The timer modes can be used to measure time intervals,
determine pulse widths, or initiate events, with one-microsecond resolution, up to a maximum interval of 65,536
instruction cycles (over 65 milliseconds). Longer delays
may easily be accumulated through software. Configured
as a counter, the same hardware will accumulate external
events at frequencies from D.C. to 500 KHz, with up to
sixteen bits of precision.
Serial Port Interface
Each microcomputer contains a high-speed, full-duplex,
serial port which is software programmable to function
in four basic modes: shift-register I/O expander, 8-bit
UART, 9-bit UART, or interprocessor communications
link. The UART modes will interface with standard I/O
devices (e.g. CRTs, teletypewriters, or modems) at data
rates from 122 baud to 31 kilobaud. Replacing the
standard 12 MHz crystal with a 10.7 MHz crystal allows
110 baud. Even or odd parity (if desired) can be included
with simple bit-handling software routines. Inter-processor
communications in distributed systems takes place at 187
kilobaud with hardware for automatic address/data
message recognition. Simple TTL or CMOS shift registers
provide low-cost I/O expansion at a super-fast I Megabaud. The serial port operating modes are controlled by
the contents of register SCON (Figure 9).
Special Peripheral Functions
There are a few special needs common among controloriented computer systems:
• keeping track of elapsed real-time;
• maintaining a count of signal transitions;
• measuring the precise width of input pulses;
• communicating with other systems or people;
• closely monitoring asynchronous external events.
Until now, microprocessor systems needed peripheral
chips such as timer/counters, USARTs, or interrupt controllers to meet these needs. The 8051 integrates all of
these capabilities on-chip!
Timer/Counters
Interrupt Capability and Control
There are two sixteen-bit multiple-mode Timer/Counters
on the 8051, each consisting of a "High" byte (corresponding to the 8048 "T" register) and a low byte (similar to the
8048 prescaler, with the additional flexibility of being
'(Interrupt capability is generally considered a CPU
function. It is being introduced here since, from an applications point of view, interrupts relate more closely to
peripheral and system interfacing.)
AFN-01502A
8-10
APPLICATIONS
I I I
GATE
CIT
M1
MO
I I I
GATE
CIT
M1
MO
I
M1
MO
o
o
\~------., ~----"I\~---.. ~_ _----")
TIMER 1
TIMER 0
o
16-bit timer/counter. "THx" and "TLx"
are cascaded; there is no prescaler.
o
GATE
Gating control. When set, Timer/counter
"x" is enabled only while "INTx" pin is
high and "TRx" control bit is set. When
cleared, timer/counter is enabled
whenever "TRx" control bit is set.
CiT
Operating Mode
MCS-48 Timer. "TLx" serves as fivebit prescaler.
8-bit auto-reload timer/counter. "THx"
holds a value which is to be reloaded
into "TLx" each time it overflows.
(Timer 0)
TLO is an eight-bit timer/
counter controlled by the
standard Timer 0 control
bits.
THO is an eight-bit timer
only controlled by Timer I
control bits.
(Timer I)
Timer/counter I stopped.
Timer or Counter Selector. Cleared for
Timer operation (input from internal
system clock). Set for Counter operation (input from "Tx" input pin).
Figure 7. TMOD-Timer/Counter Mode Register
(MSB)
I
TF1
I
TR1
I
(lSB)
TFO
TRO
IE1
IT1
lEO
I
ITO
Symbol Position Name and Significance
lEI
TCON.3 Interrupt I Edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.
Symbol Position Name and Significance
TFI
TCON.7 Timer I overflow Flag. Set by hardware
on timer/counter overflow. Cleared
when interrupt processed.
TRI
TCON.6
Timer I Run control bit. Set/cleared
by software to turn timer/counter
on/off.
TFO
TCON.5
Timer 0 overflow Flag. Set by hardware
on timer/counter overflow. Cleared
when interrupt processed.
TRO
TCON.4
Timer 0 Run control bit. Set/cleared by
software to turn timer/counter on/off.
ITI
TCON.2
Interrupt I Type control bit. Set/cleared
by software to specify falling edge/low
level triggered external interrupts.
lEO
TCON.I
Interrupt 0 Edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.
ITO
TCON.O
Interrupt 0 Type control bit. Set/cleared
by software to specify falling edge/low
level triggered external interrupts.
Figure 8. TCON-Timer/Counter Control/Status Register
AFN·01502A
8-11
APflLlCATIONS
(MSB)
(LSB)
I I I I I I I I I
SMO
SM1
SM2
REN
TBB
RBB
TI
RI
Symbol Position
SMO
SCON.7
Name and Significance
Serial port Mode control bit O.
Set/cleared by software (see note).
SMI
Serial port Mode control bit I.
Set/cleared by software (see note).
TI
SCON.I
Serial poft Mode control bit 2. Set by
software to disable reception of frames
for which bit 8 is zero.
Transmit Interrupt flag. Set by hardware when byte transmitted. Cleared
by software after servicing.
RI
SCON.O
Received Interrupt flag. Set by hardware when byte received. Cleared by
software after servicing.
Note-
the state of (SMO,SM I) selects:
(O,O)-Shift register I/O expansion.
(0,1)-8 bit VART, variable data rate.
(1,0)-9 bit VART, fixed data rate.
(1,1)-9 bit VART, variable data rate.
SM2
REN
TB8
SCON.6
SCON.S
SCON.4
SCON.3
Symbol Position
RB8
SCON.2
Receiver Enable control bit. Set/cleared
by software to enable/disable serial
data reception.
Transmit Bit 8. Set/cleared by hardware to determine state of ninth data
bit transmitted in 9-bit UART mode.
Figure 9.
SCON-~erial
Name and Significance
Receive Bit 8. Set/cleared by hardware
to indicate state of ninth data bit
received.
Port Control/Status Register
background task long enough to handle the appropriate
device, then return to the point where it left off.
These peripheral functions allow special hardware to
monitor real-time signal interfacing without bothering
the CPU. For example, imagine serial data is arriying from
one CRT while being transmitted to another, and one
timer/counter is tallying high-speed input transitions
while the other measures input pulse widths. During all
of this the CPU is thinking about something else.
This is the basis of the third and generally optimal solution, hardware interrupts. The 8051 has five interrupt
sources: one from the serial port when a transmission or
reception is complete, two from the timers when overflows occur, and two from input pins INTO and INTI.
Each source may be independently enabled or disabled
to allow polling on some sources or at some times, and
each may be. classified as high or low priority. A high
priority source can interrupt a low priority service
routine; the manager's boss can interrupt conferences
with subordinates. These options are selected by the interrupt enable and priority control registers, IE and IP
(Figures 10 and II).
But how does the CPU know when a reception, transmission, count, or pulse is finished? The 8051 programmer
can choose from three approaches.
TCON and SCON contain status bits set by the hardware
when a timer overflows or a serial port operation is completed. The first technique reads the control register into
the accumulator, tests the appropriate bit, and does a
conditional branch based on the result. This "polling"
scheme (typically a three-instruction sequence though
additional instructions to save and restore the accumulator may sometimes be needed) will surely be
familiar to programmers used to multi-chip microcomputer systems and peripheral controller chips. This
process is rather cumbersome, especially when monitoring
multiple peripherals.
a
As a second approach, the 8051 can perform conditional
branch based on the state of any control or status bit or
input pin in a single instruction; a four instruction
sequence could poll the four simultaneous happenings
mentioned above in just eight microseconds.
Each source has a particular program memory address
associated with it (Table 3), starting at 0003H (as in the
8048) and continuing at eight-byte intervals. When an
event enabled for interrupts occurs the CPU automatically
executes an internal subroutine call to the corresponding
address. A user 'subroutine starting at this location (or
jumped to from this location) then performs the instructions to service that particular source. After completing
the interrupt service routine, execution returns to the
background program.
Table 3. 8051 Interrupt Sources and Service Vectors
Unfortunately, the CPU must still drop what it's doing
to test these bits. A manager cannot do his own work
well if he is continuously monitoring his subordinates;
they should interrupt him (or her) only when they need
attention or guidance. So it is with machines: ideally, the
CPU would not have to worry about the peripherals until
they require servicing. At that time, it would postpone the
Interrupt
Source
Service Routine
Starting Address
(Reset)
External 0
Timer/ Counter 0
External I
Timer/ Counter I
Serial Port
OOOOH
0OO3H
OOOBH
OOl3H
OOIBH
0023H
AFN·01502A
8-12
APPLICATIONS
(MSB)
I
EA
(LSB)
I
ES
ET1
EX1
ETO
I I
EXO
Symbol Position Name and Significance
IE.7
Enable All control bit. Cleared by
EA
software to disable all interrupts,
independent of the state of IEA-IE.O.
ES
ETI
IE.6
IE.5
(reserved)
(reserved)
lEA
Enable Serial port control bit.
Set/cleared by software to enable/
disable interrupts from TI or RI flags.
IE.3
Symbol Position Name and Significance
EXI
IE.2
Enable External interrupt I control bit.
Set/cleared by software to enable/
disable interrupts from INTI.
ETO
lE.I
Enable Timer 0 control bit. Set/cleared
by software to enable/disable interrupts
from timer/counter 0
EXO
IE.O
Enable External interrupt 0 control bit.
Set/cleared by software to enable/
disable interrupts from INTO.
Enable Timer I control bit. Set/cleared
by software to enable/disable interrupts
from timer/counter I.
Figure 10. IE-Interrupt Enable Register
(MSB)
(LSB)
I- I
PS
PT1
PX1
PTO
I I
PXO
Symbol Position
IP.7
IP.6
IP.5
Name and Significance
(reserved)
(reserved)
(reserved)
Symbol Position Name and Significance
PX I
IP.2
External interrupt I Priority control
bit. Set/cleared by software to specify
high/ low priority interrupts for INTI.
PS
IPA
Serial port Priority control bit.
Set/cleared by software to specify
high/ low priority interrupts for Serial
port.
PTO
IP.I
Timer 0 Priority control bit.
Set/cleared by software to specify
high/low priority interrupts for
timer/counter O.
PTI
IP.3
Timer I Priority control bit.
Set/cleared by software to specify
highjlow priority interrupts for
timer/counter I.
PXO
IP.O
External interrupt 0 Priority control
bit. Set/cleared by software to specify
highjlow priority interrupts for INTO.
Figure 11. IP-Interrupt Priority Control Register
AFN-01502A
B-13
APPLICATIONS
Table 4. MCS-S1TM Instruction Set Description
DATA TRANSFER (cont.)
ARITHMETIC OPERATIONS
Mnemonic
ADD
A.Rn
ADD
A.direct
ADD
A.@Ri
ADD
A.#data
ADDC A.Rn
ADDC A.direct
ADDC A.@Ri
ADDC A.#data
SUBB
A.Rn
SUBB
A.direct
A.@Ri
SUBB
SUBB
A.#data
A
INC
Rn
INC
INC
direct
@Ri
INC
DEC
A
DEC
Rn
direct
DEC
@Ri
DEC
INC
DPTR
AB
MUL
DIV
AB
A
DA
Byte Cyc
Description
Add register to Accumulator
I
I
Add direct byte to Accumulator
2
I
Add indirect RAM to Accumulator
I
I
Add immediate data to Accumulator
2
I
Add register to Accumulator with Carry
I
I
Add direct byte to A with Carry flag
2
I
Add indirect RAM to A with Carry flag
I
I
Add immediate data to A with Carry flag
I
2
Subtract register from A with Borrow
I
I
Subtract direct byte from A with Borrow
2
I
I
Subtract indirect RAM from A w/Borrow
I
2
Subtract immed. data from A w/ Borrow
I
Increment Accumulator
I
I
Increment register
I
I
I ncrement direct byte
2
I
Increment indirect RAM
I
I
Decrement Accumulator
I
I
Decrement register
I
I
Decrement direct byte
2
I
Decrement indirect RAM
I
I
Increment Data Pointer
I
2
Multiply A & B
I
4
Divide A by B
I
4
Decimal Adjust Accumulator
I
I
LOGICAL OPERATIONS
Mnemonic
ANL
A.Rn
ANL
A.direct
ANL
A.@Ri
ANL
A.#data
ANL
direct.A
ANL
direct.#data
ORL
A.Rn
ORL
A.direct
A.@Ri
ORL
ORL
A.#data
ORL
direct.A
ORL
direct.#data
XRL
A.Rn
XRL
A.direct
A.@Ri
XRL
XRL
A.#data
XRL
direct.A
XRL
direct.#data
CLR
A
CPL
A
A
RL
RLC
A
RR
A
RRC
A
SWAP A
Destination
AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exclusive-OR register to Accumulator
Exclusive-OR direct byte to Accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR Accumulator to direct byte
Exclusive-OR immediate data to direct
Clear Accumulator
Complement Accumulator
Rotate Accumulator Left
Rotate A Left through the Carry flag
Rotate Accumulator Right
Rotate A Right through Carry flag
Swap nibbles within the Accumulator
Byte Cyc
I
I
2
I
I
I
2
I
2
I
Mnemonic
Description
MOV
A.Rn
Move register to Accumulator
MOV
Move direct byte to Accumulator
A.direct
MOV
A.@Ri
Move indirect RAM to Accumulator
MOV
A.#data
Move immediate data to Accumulator
MOV
Rn.A
Move Accumulator to register
MOV
Rn.direct
Move direct byte to register
MOV
Rn.#data
Move immediate data to register
MOV
direct.A
Move Accumulator to direct byte
MOV
direct.Rn
Move register to direct byte
MOV
direct.direct
Move direct byte to direct
direct.@Ri
MOV
Move indirect RAM to direct byte
MOV
direct.#data
Move immediate data to direct byte
MOV
@Ri.A
Move Accumulator to indirect RAM
@Ri.direct
MOV
Move direct byte to indirect RAM
MOV
@Ri.#data
Move immediate data to indirect RAM
MOV
DPTR.#data 16 Load Data Pointer with a 16-bit constant
Byte Cyc
I
I
2
I
I
I
2
I
I
I
3
2
I
2
I
I
I
I
I
I
2
2
3
I
2
I
2
2
3
I
I
I
I
I
I
I
2
I
I
I
I
I
2
I
I
I
I
I
I
I
DATA TRANSFER
2
2
2
2
3
2
3
Mnemonic
MOVC A.@A+DPTR
MOVC A.@A+PC
MOVX A.@Ri
MOVX A.@DPTR
MOVX @Ri.A
MOVX @DPTR.A
PUSH direct
POP
direct
XCH
A.Rn
XCH
A.direct
XCH
A.@Ri
XCHD A.@Ri
Description
Byte Cyc
Move Code byte relative to DPTR to A
I
2
Move Code byte relative to PC to A
I
2
Move External RAM (8-bit addr) to A
I
2
Move External RAM (16-bit addr) to A
I
2
Move A to External RAM (8-bit addr)
I
2
Move A to External RAM (16-bit addr)
I
2
Push direct byte onto stack
2
2
Pop direct byte from stack
2
2
Exchange register with Accumulator
I
I
Exchange direct byte with Accumulator
2
I
Exchange indirect RAM with A
I
I
Exchange low-order Digit indo RAM w/ A
I
I
BOOLEAN VARIABLE MANIPULATION
Mnemonic
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL
bit
ANL
C.bit
ANL
C./bit
ORL
C.bit
ORL
C./bit
MOV
C.bit
MOV
bit.C
Description
Clear Carry flag
Clear direct bit
Set Carry flag
Set direct Bit
Complement Carry flag
Complement direct bit
AND direct bit to Carry flag
AND complement of direct bit to Carry
OR direct bit to Carry flag
OR complement of direct bit to Carry
Move direct bit to Carry flag
Move Carry flag to direct bit
Byte Cyc
I
I
2
I
I
I
2
I
2
2
2
2
I
I
I
2
2
2
2
2
2
I
2
2
PROGRAM AND MACHINE CONTROL
Mnemonic
ACALL addrll
LCALL addrl6
RET
RET!
AJMP addrll
LJMP addrl6
rei
SJMP
@A+DPTR
JMP
JZ
rei
JNZ
rei
rei
JC
rei
JNC
bit.rel
JB
JNB
bit.rel
JBC
bit.rel
CJNE
A.direct.rel
A.#data.rel
CJNE
CJNE
Rn.#data.rel
@Ri.#data.rel
CJNE
DJNZ
Rn.rel
DJNZ
direct.rel
NOP
Description
Byte Cyc
Absolute Subroutine Call
2
2
Long Subroutine Call
3
2
Return from subroutine
I
2
Return from interrupt
I
2
Absolute Jump
2
2
Long Jump
3
2
Short Jump (relative addr)
2
2
Jump indirect relative to the DPTR
I
2
Jump if Accumulator is Zero
2
2
Jump if Accumulator is Not Zero
2
2
Jump if Carry flag is set
2
2
Jump if No Carry flag
2
2
Jump if direct Bit set
3
2
Jump if direct Bit Not set
3
2
Jump if direct Bit is set & Clear bit
3
2
Compare direct to A & Jump if Not I;:qual
3
2
Compo immed. to A & Jump if Not Equal
3
2
Compo immed. to reg. & Jump if Not Equal 3
2
Compo immed. to indo & Jump if Not Equal 3
2
Decrement register & Jump if Not Zero
2
2
Decrement direct & Jump if Not Zero
3
2
No operation
I
I
Notes on data addressing modes:
-Working register RO-R7
Rn
direct -128 internal RAM locations. any I/O port. control or status register
@Ri
--Indirect internal RAM location addressed by register RO or RI
#data -8-bit constant included in instruction
#data 16 -16-bit constant included as bytes 2 & 3 of instruction
bit
-128 software flags. any I/O pin. control or status bit
2
I
I
2
2
2
2
I
I
2
2
3
2
Notes on program addressing modes:
addrl6 -Destination address for LCALL & LJMP may be anywhere within
the 64-Kilobyte program memory address space.
addrll -Destination address for ACALL & AJMP will be within the same
2-Kilobyte page of program memory as the first byte of the following
instruction.
rei
-SJ M P and all conditional jumps include an 8-bit offset byte. Range is
+127 / -128 bytes relative to first byte of the following instruction.
I
2
3. INSTRUCTION SET AND ADDRESSING MODES
All mnemonics copyrighted © Intel Corporation 1979
group, this chapter starts with the addressing mode
classes and builds to include the related instructions.
The 805 I instruction set is extremely regular, in the sense
that most instructions can operate with variables from
several different physical or logical address spaces. Before
getting deeply enmeshed in the instruction set proper, it
is important to understand the details of the most
common data addressing modes. Whereas Table 4 summarizes the instructions set broken down by functional
Data Addressing Modes
MCS-51 assembly language instructions consist of an
operation mnemonic and zero to three operands separated
by commas. In two operand instructions the destination
is. specified first, then the source. Many byte-wide data
AFN-01502A
8-14
APPLICATIONS
operations (such as ADD or MOY) inherently use the
accumulator as a source operand and/or to receive the
result. For the sake of clarity the letter "A" is specified in
the source or destination field in all such instructions.
For example, the instruction,
ADD
hardware reset enables register bank 0; to select a
different bank the programmer modifies PSW bits 4 and
3 accordingly.
Example 2 - Selecting Alternate Memory Banks
MOV
A,
will add the variableto the accumulator, leaving
the sum in the accumulator.
• Register-one of the working registers in the currently enabled bank.
• Direct-an internal RAM location, I/O port, or
special-function register.
• Register-indirect-an internal RAM location,
pointed to by a working register.
• Immediate data-an eight-bit constant incorporated
into the instruction.
Direct Byte Addressing
Direct addressing can access anyon-chip variable or
hardware register. An additional byte appended to the
opcode specifies the location to be used (Figure 12.b).
Depending on the highest order bit of the direct address
byte, one of two physical memory spaces is selected.
When the direct address is between 0 and 127 (00H-7FH)
one of the 128 low-order on-chip RAM locations is used.
(Future microcomputers based on the MCS_5ITM architecture may incorporate more than 128 bytes of on-chip
RAM. Even if this is the case, only the low-order 128
bytes will be directly addressable. The remainder would
be accessed indirectly or via the stack pointer.)
The first three modes provide access to the internal RAM
and Hardware Register address spaces, and may therefore
be used as source or destination operands; the last mode
accesses program memory and may be a source operand
only.
(It is hard to show a "typical application" of any instruction without involving instructions not yet described. The
following descriptions use only the self-explanatory ADD
and MOY instructions to demonstrate how the four
addressing modes are specified and used. Subsequent
examples will become increasingly complex.)
Example 3 -Adding RAM Location Contents
; DIRADR ADD CONTENTS OF RAM LOCATION 41H
TO CONTENTS OF RAM LOCATION 40H
DIRADR
MOV
ADD
MOV
A,40H
A,41H
40H, A
All I/O ports and special function, control, or status
registers are assigned addresses between 128 and 255
(80H-OFFH). When the direct address byte is between
these limits the corresponding hardware register is
accessed. For example, Ports 0 and I are assigned direct
addresses 80H and 90H, respectively. A complete list is
presented in Table 5. Don't waste your time trying to
memorize the addresses in Table 5. Since programs using
absolute addresses for function registers would be difficult
to write or understand, ASM51 allows and understands
the abbreviations listed instead.
Register Addressing
The 8051 programmer has access to eight "working registers," numbered RO-R7. The least-significant three-bits of
the instruction opcode indicate one register within this
logical address space. Thus, a function code and operand
address can be combined to form a short (one byte)
instruction (Figure 12.a).
The 8051 assembly language indicates register addressing
with the symbol Rn (where n is from 0 to 7) or with a
symbolic name previously defined as a register by the
EQUate or SET directives. (For more information on
assembler directives see the Macro Assembler Reference
Manual.)
Example
4-Adding Input Port Data to Output Port
Data
; PRTADR ADD DATA INPUT ON PORT 1
TO DATA PREVIOUSLY OUTPUT
ON PORT 0
Example I-Adding Two Registers Together
PRTADR
; REGADR ADD CONTENTS OF REG I STER 1
TO CONTENTS OF REGISTER 0
MOV
ADD
MOV
SELECT BANK 2
Register addressing in the 8051 is the same as in the 8048
family, with two enhancements: there are four banks
rather than one or two, and 16 instructions (rather than
12) can access them.
The operand designated '~source>" above may use any
of four common logical addressing modes:
REGADR
PSW.II00010000B
MOV
ADD
MOV
A, PO'
A, PI
PO, A
Direct addressing allows all special-function registers in
the 8051 to be read, written, or used as instruction
operands. In general, this is the only method used for
accessing I/O ports and special-function registers. If direct
addressing is used with special-function register addresses
other than those listed, the result of the instruction is
undefined.
A, RO
A, Rl
RO. A
There are four such banks of working registers, only one
of which is active at a time. Physically, they occupy the
first 32 bytes of on-chip data RAM (addresses O-IFH).
PSW bits 4 and 3 determine which bank is active. A
AFN·01502A
8-15
APPLICATIONS
The 8048 does not have or need any generalized direct
addressing mode, since there are only five special registers
(BUS, PI, P2, PSW, & T) rather than twenty. Instead, 16
special 8048 opcodes control output bits or read or write
each register to the accumulator. These functions are all
subsumed by four of the 27 direct addressing instructions
of the 8051.
Indirect addressing on the 8051 is the same as in the
8048 family, except that all eight bits of the pointer register
contents are significant; if the contents point to a nonexistent memory location (i.e., an address greater than
7FH on the 8051) the result of the instruction is undefined.
(Future microcomputers based on the MCS-5I™ architecture could implement additional memory in the
on-chip RAM logical address space at locations above
7FH.) The 8051 uses register-indirect addressing for five
new instructions plus the 13 on the 8048.
Table 5. 8051 Hardware Register Direct Addresses
Register
Address
PO
SP
DPL
DPH
TCON
TMOD
TLO
TLI
THO
THI
PI
SCON
SBUF
P2
IE
P3
IP
PSW
ACe
B
• = bit
80H*
81H
82H
83H
88H*
89H
8AH
8BH
8CH
8DH
90H*
98H*
99H
OAOH*
OA8H*
OBOH*
OB8H*
ODOH*
OEOH*
OFOH*
Function
Port 0
Stack Pointer
Data Pointer (Low)
Data Pointer (High)
Timer register
Timer Mode register
Timer 0 Low byte
Timer I Low byte
Timer 0 High byte
Timer I High byte
Port I
Serial Port Control register
Serial Port data Buffer
Port 2
Interrupt Enable register
Port 3
Interrupt Priority register
Program Status Word
Accumulator (direct address)
B register
Immediate AddreSSing
When a source operand is a constant rather than a variable (i.e.-the instruction uses a value known at assembly
time), then the constant can be incorporated into the
instruction. An additional instruction byte specifies the
value used (Figure l2.d).
The value used is fixed at the time of ROM manufacture
or EPROM programming and may not be altered during
program execution. In the assembly language immediate
operands are preceded by a number sign ("#"). The
operand may be either a numeric string, a symbolic
variable, or an arithmetic expression using constants.
Example
6-Adding Constants Using Immediate
Addressing
i
addressable register.
IMMADR ADD THE CONSTANT 12 (DECIMAL)
TO THE CONSTANT 34 (DECIMAL)
LEAVE SUM IN ACCUMULATOR
IMMADR
How can you handle variables whose locations in RAM
are determined, computed, or modified while the program
is running? This situation arises when manipulating
sequential memory locations, indexed entries within tables
in RAM, and multiple precision or string operations.
Register or Direct addressing cannot be used, since their
operand addresses are fixed at assembly time.
Example
7 -Adding Constants Using ASM51
Capabilities
i
ASMSUM LOAD ACC WITH THE SUM OF
THE CONSTANT 12 (DEC IMAL)
THE CONSTANT 34
; RETURN
Decimal addition is possible by using the DA instruction
in conjunction with ADD and/or ADDC. The eight-bit
binary value in the accumulator resulting from an earlier
addition of two variables (each a packed BCD digit-pair)
is adjusted to form two BCD digits of four bits each. If the
contents of accumulator bits 3-0 are greater than nine
(xxxx 10 IO-xxxx 1111), or ifthe AC flag had been set, six
is added to the accumulator producing the proper BCD
digit in the low-order nibble. (This addition might itself
set - but would not clear - the carry flag.) Ifthe carry
flag is set, or if the four high-order bits now exceed nine
(10 IOxxxx-IIII xxxx), these bits are incremented by six.
The carry flag is left set if originally set or if either
addition of six produces a carry out of the highest-order
bit, indicating the sum of the original two BCD variables
is greater than or equal to decimal 100.
When performing signed binary arithmetic, certain
combinations of input variables can produce results
which seem to violate the Laws of Mathematics. For
example, adding 7FH (127) to itself produces a sum of
OFEH, which is the two's complement representation of
-2 (refer back to Table 2)! In "normal" arithmetic, two
.positive values can't have a negative sum. Similarly, it js
normally impossible to subtract a positive value from a
negative value and leave a positive result - but in two's
complement there are instances where this too may
happen. Fundamentally, such anomolies occur when the
magnitude of the resulting value is too great to "fit" into
the seven bits allowed for it; there is no one-byte two's
complement representation for 254, the true sum of 127
and 127.
AFN-01S02A
R.1A
APPLICATIONS
digits in the accumulator and returns the product of the
two individual digits in packed BCD format in the
accumulator.
Example II - Two Byte Decimal Add with Registers
and Constants
; BCDADD ADD THE CONSTANT 1.234 (DECIMAl) TO THE
CONTENTS OF REGISTER PAIR ':R3>
(ALREADY A 4 BCD-DIGIT VARIABLE)
BCDADD
MOV
ADD
DA
MOV
MOV
ADDC
DA
MOV
RET
Example 13 -Implementing a BCD Multiply Using
MPYand DIV
A. R2
A.4I34H
A
R2. A
A. R3
A.4I12H
A
R3. A
; MULBCD UNPACK TWO BCD DIGITS RECEIVED IN ACC.
FIND THEIR PRODUCT. AND RETURN PRODUCT
IN PACKED BCD FORMAT IN ACC
MULBCD'
MOV
DIV
B.III0H;
AB
;
;
;
;
B.III0;
AB
;
A
A. B
;
MUL
MOV
DIV
SWAP
ORL
RET
Multiplication and Division
The instruction "MUL AB" multiplies the unsigned
eight-bit integer values held in the accumulator and Bregisters. The low-order byte of the sixteen-bit product is
left in the accumulator, the higher-order byte in B. If the
high-order eight-bits of the product are all zero the
overflow flag is cleared; otherwise it is set. The
programmer can poll OV to determine when the B
register is non-zero and must be processed.
These operations may use all the same addressing modes
as the arithmetics (ADD, etc.) but unlike the arithmetics,
they are not restricted to operating on the accumulator.
Directly addressed bytes may be used as the destination
with either the accumulator or a constant as the source.
These instructions are useful for clearing (ANL), setting
(ORL), or complementing (XRL) one or more bits in a
RAM, output ports, or control registers. The pattern of
bits to be affected is indicated by a suitable mask byte.
Use immediate addressing when the pattern to be affected
is known at assembly time (Figure 14); use the
accumulator versions when the pattern is computed at
run-time.
I! 0 ports are often used for parallel data in formats other
than simple eight-bit bytes. For example, the low-order
five bits of port I may output an alphabetic character
code (hopefully) without disturbing bits 7-5. This can be a
simple two-step process. First, clear the low-order five
pins with an ANL instruction; then set those pins corresponding to ones in the accumulator. (This example
assumes the three high-order bits of the accumulator are
originally zero.)
Example 12- Use of DIV Instruction for Radix
Conversion
; BINBCD CONVERT 8-BIT BINARY VARIABLE IN ACC
TO 3-DIGIT PACKED BCD FORMAT
HUNDREDS' PLACE LEFT IN VARIABLE ·HUND'.
TENS' AND ONES' PLACES IN 'TENONE'
21H
22H
BINBCD
MOV
DIV
MOV
MOV
XCH
DIV
B.II100
AB
HUND. A
A,4IIO
SWAP
ADD
MOV
RET
A
A. B
AB
; DIVIDE BY 100 TO
; DETERM I NE NUMBER OF HUNDREDS
;
;
;
;
DIVIDE REMAINDER BY 10 TO
DETERMINE II OF TENS LEFT
TENS DIGIT IN ACC. REMAINDER
DIGIT
ANL, ORl, XRl
The instructions ANL, ORL, and XRL perform the
logical functions AND, OR, and! or Exclusive-OR on the
two byte variables indicated, leaving the results in the
first. No flags are affected. (A word to the wise - do not
vocalize the first two mnemonics in mixed company.)
The divide instruction is also useful for purposes such as
radix conversion or separating bit fields of the
accumulator. A short subroutine can convert an eight-bit
unsigned binary integer in the accumulator (between 0 &
255) to a three-digit (two byte) BCD representation. The
hundred's digit is returned in one register (HUND) and
the ten's and one's digits returned as packed BCD in
another (TENONE).
E, , , ,
, orvalue,
OOH, and processed with the printing characters.
Interrupt service routines must not change any variable
or hardware registers modified by the main program, or
else the program may not resume correctly. (Such a
change might look like a spontaneous random error.)
Resources used or altered by the service routine
(Accumulator, PSW, etc.) must be saved and restored to
their previous value before returning from the service
routine. PUSH and POP provide an efficient and
convenient way to save register states on the stack.
Example 16-Case Statements Using CJNE
Example 18 - Use of the Stack for Status Saving on
Interrupts
CHAR
E-1---r--....}--t-_ _ _---t-i
R. TURN --~-+----r-""
1--__+ - - - -
L. REAR
R. DASH
R. FRNT
R. REAR
PARK
Applying the brake pedal turns the taillight filaments on
constantly ... unless a turn is in progress, in which case the
blinking taillight is not affected. (Of course, the front turn
signals and dashboard indicators are not affected by the
brake pedal.) Table 6 summarizes these operating modes.
---------t---f---..,
LO.
FREQ.
OSCILLATOR
HI.
FREQ.
OSCILLATOR
Figure 15. TTL logic implementation of
automotive turn signals.
Table 6. Truth table for turn-signal operation.
BRAKE
SWITCH
0
0
0
0
0
0
I
I
I
I
I
I
INPUT SIGNALS
EMERG.
LEFT
RIGHT
SWITCH
TURN
TURN
SWITCH SWITCH
0
0
0
0
0
I
0
I
I
I
0
0
0
I
I
I
I
0
0
I
0
0
I
0
0
I
0
0
I
0
0
I
0
0
I
0
LEFT
FRONT
& DASH
OUTPUT SIGNALS
RIGHT
RIGHT
LEFT
FRONT
REAR
REAR
& DASH
OFF
OFF
BLINK
BLINK
BLINK
BLINK
OFF
OFF
BLINK
BLINK
BLINK
BLINK
OFF
BLINK
OFF
BLINK
BLINK
BLINK
OFF
BLINK
OFF
BLINK
BLINK
BLINK
OFF
OFF
BLINK
BLINK
BLINK
BLINK
ON
ON
BLINK
ON
ON
BLINK
OFF
BLINK
OFF
BLINK
BLINK
BLINK
ON
BLINK
ON
ON
BLINK
ON
01489A
C·18
APPLICATIONS
In most cars, the switching logic to generate these functions requires a number of multiple-throw contacts. As
many as 18 conductors thread the steering column of some
automobiles solely for turn-signal and emergency blinker
functions. (The author discovered this recently to his
astonishment and dismay when replacing the whole
assembly because of one burned contact.)
Design Example #3 demonstrated that symbolic addressing with user-defined bit names makes code and documentation easier to write and maintain. Accordingly, we'll
assign these 110 pins names for use throughout the program. (The format of this example will differ somewhat
from the others. Segments of the overall program will be
presented in sequence as each is described.)
A multiple-conductor wiring harness runs to each corner
of the car, behind the dash, up the steering column, and
down to the blinker relay below. Connectors at each termination for each filament lead to extra cost and labor
during construction, lower reliability and safety, and more
costly repairs. And considering the system's present complexity, increasing its reliability or detecting failures
would be quite difficult.
INPUT PIN DECLARATIONS:
(ALL INPUTS ARE POSITIVE-TRUE LOGIC)
BIT PI.D
BIT PI. I
~
PARK
BIT PI.2
L_TURN BIT PI.3
R_TURN BIT PI.4
~
BRAKE
EMERG
There are two reasons for going into such painful detail
describing this example. First, to show that the messiest
part of many system designs is determining what the
controller should do. Writing the software to solve these
functions will be comparatively easy. Secondly, to show
the many potential failure points in the system. Later we'll
see how the peripheral functions and intelligence built into
a microcomputer (with a little creativity) can greatly
reduce external interconnections and mechanical part
count.
~
~
~
BRAKE PEDAL DEPRESSED
EMERGENCY BLINKER
ACTIVATED
PARKING LIGHTS ON
TURN LEVER DOWN
TURN LEVER UP
OUTPUT PIN DECLARATIONS:
L_FRNT BIT PI.5
~
R_FRNT BIT PI.6
~
L_DASH BIT PI.7
~
R_DASH BIT P2.D
~
The Single-chip Solution
LREAR BIT P2.1
~
The circuit shown in Figure 16 indicates five input pins to
the five input variables-left-turn select, right-turn select,
brake pedal down, emergency switch on, and parking
lights on. Six output pins turn on the front, rear, and
dashboard indicators for each side. The microcomputer
implements all logical functions through software, which
periodically updates the output signals as time elapses and
input conditions change.
R_REAR BIT P2.2
~
FRONT LEFT-TURN
INDICATOR
FRONT RIGHT-TURN
INDICATOR
DASHBOARD LEFT-TURN
INDICATOR
DASHBOARD RIGHT-TURN
INDICATOR
REAR LEFT-TURN
INDICATOR
REAR RIGHT-TURN
INDICATOR
Another key advantage of symbolic addressing will
appear further on in the design cycle. The locations of
cable connectors, signal conditioning circuitry, voltage
regulators, heat sinks, and the like all affect P.c. board
layout. It's quite likely that the somewhat arbitrary pin
assignment defined early in the software design cycle will
prove to be less than optimum; rearranging the I 10 pin
assignment could well allow a more compact module, or
eliminate costly jumpers on a single-sided board. (These
considerations apply especially to automotive and other
cost-sensitive applications needing single-chip controllers.) Since other architectures mask bytes or use
"clever" algorithms to isolate bits by rotating them into
the carry, re-routing an input signal (from bit I of port I,
for example, to bit 4 of port 3) could require extensive
modifications throughout the software.
Figure 16. Microcomputer Turn-signal Connections.
8051
LEFT
.----.::,.......... DASHBOARD
LEFT
REAR
The Boolean Processor's direct bit addressing makes such
changes absolutely trivial. The number of the port containing the pin is irrelevent, and masks and complex program
structures are not needed. Only the initial Boolean varia-
RIGHT
REAR
MODE
SENSORS
SIGNAL
CONDmoNINQ
OUTPUT
BUFFERS
SIGNAL
BULBS
01489A
C-19
1
APPLICATIONS
; INTERRUPT RATE SUBDIVIDER
SUB_DIY
D.A.TA
20H
; HIGH-FREQUENCY OSCILLATOR BIT
HLFREQ
BIT
SUB_DIV.O
; LOW-FREQUENCY OSCILLATOR BIT
LOJ'REQ
BIT
SUB_DIV.7
JMP
ORG
INIT
OOOOH
ORG
100H
; PUT TIMER 0 IN MODE 1
INIT:
MOV
TMOD,#OOOOOOOI B
; INITIALIZE TIMER REGISTERS
MOV
TLO.#O
MOV
THO,#-16
; SUBDIVIDE INTERRUPT RATE BY 244
MOV
SUB_DIV,#244
; ENABLE TIMER INTERRUPTS
SETB
ETO
; GLOBALLY ENABLE ALL INTERRUPTS
SETB
EA
; START TIMER
SETB
TRO
; (CONTINUE WITH BACKGROUND PROGRAM)
; PUT TIMER 0 IN MODE 1
; INITIALIZE TIMER REGISTERS
fast to modulate the parking lights; bit 7 will be "tuned" to
approximately I Hz for the turn- and emergencyindicator blinking rate.
Loading THO with -16 will cause an interruptafter 4.096
msec. The interrupt service routine reloads the high-order
byte of timer 0 for the next interval, saves the CPU registers likely to be affected on the stack, and then decrements
SUB_DIV. Loading SUB_DIV. with 244 initially and
each time it decrements to zero will produce a 0.999
second period for the highest-order bit.
ORG
MOV
PUSH
PUSH
PUSH
DJNZ
MOV
The code to sample inputs, perform calculations, and
update outputs-the real "meat" of the signal controller
algorithm-may be performed either as part of the interrupt service routine or as part of a background program
loop. The only concern is that it must be executed at least
several dozen times per second to prevent parking light
flickering. We wiIJ assume the former case, and insert the
code into the timer 0 service routine.
First. notice from the logic diagram (Figure IS) that the
subterm (PARK, H_FREQ), asserted when the parking
lights areto be on dimly, figures into four of the six output
functions. Accordingly, we will first compute that term
and save it in a temporary location named "DIM". The
PSWcontains two general purpose flags: FO, which corresponds to the 8048 flag of the same name. and PSW.I.
Since The PSW has been saved and will be restored to its
previous state after servicing the interrupt, we can use
either bit for temporary storage.
; SUBDIVIDE INTERRUPT RATE BY 244
; ENABLE TIMER INTERRUPTS
; GLOBALLY ENABLE ALL INTERRUPTS
; START TIMER
ble declarations need to be changed; ASMSI automatically adjusts all addresses and symbolic references to the
reassigned variables. The user is assured that no additional debugging or software verification will be required.
Timer 0 (one of the two on-chip timer/counters) replaces
the thermo-mechanical blinker relay in the dashboard
controller. During system initialization it is configured as
a timer in mode 1 by setting the least significant bit of the
timer mode register (TMOD). In this configuration the
low-order byte (TLO) is incremented every machine cycle,
overflowing and incrementing the high-order byte (THO)
every 2S6 J.lSec. Timer interrupt 0 is enabled so that a
hardware interrupt will occur each time THO overflows.
(For details of the numerous timer operating modes see
the MCS-SITM User's Manual.)
An eight-bit variable in the bit-addressable RAM array
will be needed to further subdivide the interrupts via
software. The lowest-order bit of this counter toggles very
; TIMER 0 SERVICE VECTOR
OOOBH
THO.#-16
PSW
ACC
B
SUB_DIV.TOSERV
SUB_DIV.#244
DIM
BIT
MOV CPARK
ANL
HLFREQ
MOV DIM.C
PSW.I ; DECLARE TEMP.
STORAGE FLAG
; GATE PARKING
LIGHT SWITCH
; WITH HIGH
FREQUENCY
SIGNAL
; AND SAVE IN
TEMP. VARIABLE.
This simple three-line section of code illustrates a remarkable point. The software indicates in very abstract terms
exactly what function is being performed, independent of
01489A-22
C-20
APPLICATIONS
the hardware configuration. The fact that these three bits
include an input pin, a bit within a program variable, and
a software flag in the PSW is totally invisible to the
programmer.
MOV R_DASH,C
MOV FO,C
ORL C,DIM
Now generate and output the dashboard left turn signal.
MOV R_FRNT,C
ORL C,EMERG
; SET CARRY IF
TURN
; OR EMERGENCY
SELECTED.
; GATE IN I HZ
SIGNAL
; AND OUTPUT TO
DASHBOARD.
MOV C,BRAKE
ANL C,jR_TURN
ORL C,FO
ORL C,DIM
To generate the left front turn signal we only need to add
the parking light function in FO. But notice that the function in the carry will also be needed for the rear signal. We
can save effort later by saving its current state in FO.
MOV FO,C
ORL C,DIM
MOV R_REAR,C
(The perceptive reader may notice that simply rearranging
the steps could eliminate one instruction from each
sequence.)
; SAVE FUNCTION
SO FAR.
; ADD IN PARKING
LIGHT FUNCTION
; AND OUTPUT TO
TURN SIGNAL.
Now that all six bulbs are in the proper states, we can
return from the interrupt routine, and the program is
finished. This code essentially needs to reverse the status
saving steps at the beginning of the interrupt.
Finally, the rear left turn signal should also be on when the
brake pedal is depressed, provided a left turn is not in
progress.
MOV C,BRAKE
ORL C,FO
ORL C,DIM
POP
B
; RESTORE CPU
REGISTERS.
POP ACC
POP PSW
RET!
; GATE BRAKE
PEDAL SWITCH
; WITH TURN
LEVER.
; INCLUDE TEMP.
VARIABLE FROM
DASH
; AND PARKING
LIGHT FUNCTION
; AND OUTPUT TO
TURN SIGNAL.
Program Refinements. The luminescence of an incandescent light bulb filament is generally non-linear; the 50%
duty cycle of HLFREQ may not produce the desired
intensity. If the application requires, duty cycles of 25%,
75%, etc. are easily achieved by ANDing and ORing in
additional low-order bits ofSUB_DIV. For example, 30
Hz signals of seven different duty cycles could be produced by considering bits 2~0 as shown in Table 7. The
only software change required would be to the code which
sets-up variable DIM:
Now we have to go through a similar sequence for the
right-hand equivalents to all the left-turn lights. This also
gives us a chance to see how the code segments above look
when combined.
ORL C,EMERG
; AND OUTPUT TO
DASHBOARD.
; SAVE FUNCTION
SO FAR.
; ADD IN PARKING
LIG HT FUNCTION
; AND OUTPUT TO
TURN SIGNAL.
; GATE BRAKE
PEDAL SWITCH
; WITH TURN
LEVER.
; INCLUDE TEMP.
V ARIABLE FROM
DASH
; AND PARKING
LIGHT FUNCTION
; AND OUTPUT TO
TURN SIGNAL.
MOV C,SUB_DIV.I
; SET CARRY IF
TURN
; OR EMERGENCY
SELECTED.
; IF SO, GATE IN I
HZ SIGNAL
ANL C,SUB_DIV.O
ORL C,SUB_DIV.2
MOV DIM,C
; START WITH 50
PERCENT
; MASK DOWN TO 25
PERCENT
; AND BUILD BACK TO
62 PERCENT
; DUTY CYCLE FOR
PARKING LIGHTS.
01489A
C-21
r,,- r
... 1"1"'\
1
IVI"~
Table 7. Non-trivial Duty Cycles.
nllTV
f"'Vf"'1
.... . . . , .
I
. . . . . . . . . . . _ i:C!
_ .....
C!IID
nnl
..,,,,
... _"'1
• DITC!
.., •• ..,
7
X
X
X
X
X
X
X
X
6
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
X
X
X
X
X
X
X
X
3
2
X
X
X
X
X
X
X
X
0
0
0
0
I
I
I
I
1
0
0
I
I
0
0
I
I
0
0
I
0
I
0
I
0
I
12.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
25.0%
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
Interconnections increase cost and decrease reliability.
The simple buffered pin-per-function circuit in Figure 16
is insufficient when many outputs require higher-thanTTL drive levels. A lower-cost solution uses the 8051
serial port in the shift-register mode to augment I/O. In
mode O. writing a byte to the serial· port data buffer
(SBUF) causes the data to be output sequentially through
the "RXD" pin while a burst of eight clock pulses is
generated on the "TXD" pin. A shift register connected to
these pins (Figure 17) will load the data byte as it is shifted
out. A number of special peripheral driver circuits combining shift-register inputs with high drive level outputs
have been introduced recently.
L_DASH BIT 8.2
R_DASH BIT 8.3
75.0%
OFF
OFF
ON
ON
ON
ON
ON
ON
87.5%
OFF
ON
ON
ON
ON
ON
ON
ON
Figure 17. Output expansion using serial port.
L_REAR BIT 8.4
R_REAR BIT B.5
:
:
:
:
REAR LEFT-TURN
INDICATOR
REAR RIGHT-TURN
INDICATOR
The original program to compute the functions need not
change. After computing the output variables, the control
map is transmitted to the buffered shift register through
the serial port:
MOY
SBUF.B
: LOAD BUFFER ANDTRANSMIT
The Boolean Processor solution holds a number of advantages over older methods. Fewer switches are required.
Each is simpler, requiring fewer poles and lower current
contacts. The flasher relay is eliminated entirely. Only six
filaments are driven, rather than 10. The wiring harness is
therefore simpler and less expensive-one conductor for
each of the six lamps and each of the five sensor switches.
The fewer cond uctors use far fewer connectors. The whole
system is more reliable.
This is where the earlier decision to address bits symbolically throughout the program is going to payoff. This
major I/O restructuring is nearly as simple to implement
as rearranging the input pins. Again, only the bit declarations need to be changed.
R_FRNT BIT B.I
62.5%
OFF
OFF
OFF
ON
ON
ON
ON
ON
8051
The software for this technique uses the B register as a
"map" corresponding to the different output functions.
The program manipulates these bits instead of the output
pins. After all functions have been calculated the B register
is shifted by the serial port to the shift-register/ driver.
(While some outputs may glitch as data is shifted through
them, at I Megabaud most people wouldn't notice. Some
shift registers provide an "enable" bit to hold the output
states while new data is being shifted in.)
BIT B.O
50.0%
OFF
OFF
OFF
OFF
ON
ON
ON
ON
+12V
Cascading multiple shift registers end-to-end will expand
the number of outputs even further. The data rate in the
I/O expansion mode is one megabaud, or 8 usec. per byte.
This is the mode which the serial port defaults to following
a reset. so no initializatiQn is required.
L_FRNT
37.5%
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
: FRONT LEFT-TURN
INDICATOR
: FRONT RIGHT-TURN
INDICATOR
: DASHBOARD LEFT-TURN
INDICATOR
: DASHBOARD RIGHT-TURN
INDICATOR
And since the system is much simpler it would be feasible
to implement redundancy and/ or fault detection on the
four main turn indicators. Each could still be a standard
double filament bulb, but with the filaments driven in
parallel to tolerate single-element failures.
Even with redundancy, the lights will eventually fail. To
handle this inescapable fact current or voltage sensing
01489A
C-22
At't'LI\.;A I IUN:::»
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
circuits on each main drive wire can verify that each bulb
and its high-current driver is functioning properly. Figure
18 shows one such circuit.
WIRING
HARNESS
+12V
I
P1.7
P2.0
L_DASH
TO,FAULT
L_DASH
L_REAR
TO.FAULT
L_REAR
R_FRNT
TO.FAULT
R_FRNT
R_DASH
TO.FAULT
R_DASH
R_REAR
TO.FAULT
R.~REAR
P2.1
: WITH ALL COLLECTORS GROUNDED. TO
SHOULD BE HIGH
: IF SO. CONTINUE WITH INTERRUPT ROUTINE.
JB
TO.TOSERV
FAUL T:
: ELECTRICAL FAILURE
:PROCESSING ROUTINE
: (LEFT TO READER'S
: IMAGINATION)
TOSERV:
: CONTINUE WITH
:INTERRUPT PROCESSING
P2.2
Figure 18.
Assume all of the lights are turned on except one; i.e., all
but one of the collectors are grounded. For the bulb which
is turned off. if there is continuity from + 12 V through the
bulb base and filament, the control wire, all connectors,
and the P.e. board traces, and if the transistor is indeed
not shorted to ground, then the collector will be pulled to
+ 12 V. This turns on the base of Q8 through the corresponding resistor, and grounds the input pin, verifying that
the bulb circuit is operational. The continuity of each
circuit can be checked by software in this way.
The complete assembled program listing is printed in
Appendix A. The resulting code consists of 67 program
statements, not counting declarations and comments,
which assemble into 150 bytes of object code. Each pass
through the service routine requires (coincidently) 67 usec,
plus 32 usec once per second for the electrical test. If
executed every 4 msec as suggested this software would
typically reduce the throughput of the background program by less than 2%.
N ow turn all the bulbs on, grounding all the collectors. Q7
should be turned off. and the Test pin should be high.
However, a control wire shorted to + 12 V or an opencircuited drive transistor would leave one ofthe collectors
at the higher voltage even now. This too would turn on Q7,
indicating a different type of failure. Software could perform these checks once per second by executing the routine every time the software counter SUB_DIVis reloaded
by the interrupt routine.
DJNZ SUB_DIV.TOSERV
MOV SUB_DIV.#244
ORL PI.#IIIOOOOOB
ORL
CLR
P2.#00000111 B
L_FRNT
JB
TO.FAULT
SETB L_FRNT
Once a microcomputer has been designed into a system,
new features suddenly become virtually free. Software
could make the emergency blinkers flash alternately or at
a rate faster than the turn signals. Turn signals could
override the emergency blinkers. Adding more bulbs
would allow mUltiple taillight sequencing and
syncopation - true flash factor. so to speak.
Design Example #5 - Complex Control
Functions
: RELOAD COUNTER
: SET CONTROL
OUTPUTS HIGH
Finally, we'll mix byte and bit operations to extend the use
of 8051 into extremely complex applications.
Programmers can arbitrarily assign 110 pins to input and
output functions only if the total does not exceed 32,
which is insufficient for applications with a very large
number of input variables. One way to expand the number
of inputs is with a technique similar to multiplexedkeyboard scanning.
: FLOAT DRIVE
COLLECTOR
: TO SHOULD BE
PULLED LOW
: PULL COLLECTOR
BACK DOWN
01489A
C-23
Figure 19 shows a block diagram for a moderately complex programmable industrial controller with the following characteristics:
The 8051 serial port can be configured to detect bytes with
the address bit set, automatically ignoring all others. Pins
INTO and INT! are interrupts configured respectively as
high-priority, falling-edge triggered and low-priority, lowlevel triggered. The remaining 12 I/O pins output TTLlevel control signals to 12 actuators.
•
•
•
•
64 input variable sensors;
12 output signals;
Combinational and sequential logic computations;
Remote operation with communications to a host
processor via a high-speed full-duplex serial link;
• Two prioritized external interrupts;
• Internal real-time and time-of-day clocks.
There are several ways to implement the sensor matrix
circuitry, all logically similar. Figure 20.a shows one possibility. Each of the 64 sensors consists of a pair of simple
switch contacts in series with a diode to permit multiple
contact closures throughout the matrix.
While many microprocessors could be programmed to
provide these capabilities with assorted peripheral support chips, an 8051 microcomputer needs no other integrated circuits!
The scan lines from Port I provide eight un-encoded
active-high scan signals for enabling columns of the
matrix. The return lines on rows where a contact is closed
are pulled high and read as logic ones. Open return lines
are pulled to ground by one of the 40 kohm resistors and
are read as zeroes. (The resistor values must be chosen to
ensure all return lines are pulled above the 2.0 V logic
threshold, even in the worst-case, where all contacts in an
enabled column are closed.) Since PO is provided opencollector outputs and high-impedance MOS inputs its
input loading may be considered negligible.
The 64 input sensors are logically arranged as an 8x8
matrix. The pins of Port 1 sequentially enable each
column of the sensor matrix; as each is enabled Port 0
reads in the state of each sensor in that column. An
eight-byte block in bit-addressable RAM remembers the
data as it is read in so that after each complete scan cycle
there is an internal map of the current state of all sensors.
Logic functions can then directly address the elements of
the bit map.
The computer's serial port is configured as a nine-bit
U ART, transferring data at 17,000 bytes-per-second. The
ninth bit may distinguish between address and data bytes.
12MHZ
The circuits in Figures 20.b-20.d are variations on this
theme. When input signals must be electrically isolated
from the computer circuitry as in noisy industrial environments, phototransistors can replace the switch/ diode
pairs and provide optical isolation as in Figure 20.b. Additional opto-isolators could also be used on the control
output and special signal lines.
=
XTAL2
SERIAL
LINK
1
iNTo 1 - - - - - I.
iNT1 1--_ _ _ j
RXO
The other circuits assume that input signals are already at
TTL levels. Figure 20.c uses octal three-state buffers
enabled by active-low scan signals to gate eight signals
onto Port O. Port 0 is available for memory expansion or
peripheral chip interfacing between sensor matrix scans.
Eight-to-one multiplexers in Figure 20.d select one of
eight inputs for each return line as determined by encoded
address bits output on three pins of Port I. (Five more
output pins are thus freed for more control functions.)
Each output can drive at least one standard TTL or up to
10 low-power TTL loads without additional buffering.
ASYNCHRONANS
INTERRUPTS
8051
PO.l
PO.2
PO.5
MACHINE
ACTUATORS
PO.S
P2.2
P2.6
P2.7
/
VSS
ALE
N.C.
PSEN
N.C.
Going back to the original matrix circuit, Figure 21 shows
the method used to scan the sensor matrix. Two complete
bit maps are maintained in the bit-addressable region of
the RAM: one for the current state and one for the previous state read for each sensor. If the need arises, the
program could then sense input transitions and/ or
debounce contact closures by comparing each bit with its
earlier value.
EA
SCAN
LINES
Figure 19. Block diagram of 64-input machine
controller.
01489A
C-24
APPLIGA IIUN~
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'------++------1 P1.0
'------++---....., P1.1
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'----------++--------1 P1.3
'----------++------"1 P1.'
' - - - - - - - - - - - 1 1 + - - - - - - 1 P1.5
L - - - - - - - - - - + + - - - - - - " 1 P1 .•
L - - - - - - - - - - - - - - H - - - - - 1 P1.7
L--_ _ _ _
L - - - - - - - - H - - - - - i P 1 .•
L - - - - - - - t t - - - - - 1 P1 .5
L - - - - - - - - - - - t - 1 f - - - - - - - I P1 .•
L-------------+t-------jP1.7
SCAN
LINES
b.) Using optically-coupled isolators.
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IL++
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1'-+-+++-H---<10--++-t-+---t---I-----41-+--t-+-H,---.., PO.2
"--+-++-+-I---~+-+-+-I---+----+-f_t_+-+--! PO.3
l'---------+-+-+---4--_ PO.1
L.t
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L.1~==1~=':==_:=====:; :~:
L+-I--------+--I---+------<>-+----I po.•
4------......-+-----4----i PO.7
I
++-._ _ _- j Pl.2
L-_ _ _ _-++--_ _--jP1.3
a.) Using switch contact/diode matrix.
lfr7~lSt;
PO.7
=
L------++-------"1P1.0
LINES
rrrrlrrl
t
'----_ _ _-1-1---_ _--1 P1.1
SCAN'
rl~ ~ ~ ~ ~ ~ ~1 ~ ~ ~
RETURN
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I I I I
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1
1
Pl.3
I
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Pl.D
Pl.1
Pl.2
P1.4
Pl.S
Pl.7
L--
'----
C.) Using TTL three-state buffers.
d.) Using TTL data selectors.
Figure 20. Sensor Matrix Implementation Methods.
Example 3.
INPUT_SCAN:
: SUBROUTINE TO READ
CURRENT STATE
; OF 64 SENSORS AND
SAVE IN RAM 20H-27H.
MOY RO,#20H
: INITIALIZE
; POINTERS
MOY R L#28H
: FOR BIT MAP
; BASES.
The code in Example 3 implements the scanning algorithm for the circuits in Figure 20.a. Each column is
enabled by setting a single bit in a field of zeroes. The bit
maps are positive logic; ones represent contacts that are
closed or isolators turned on.
01489A
C-25
MOV A,#80H
SCAN: MOV PI.A
RR
A
MOV R2,A
MOV A,PO
XCH A,@RO
MOV @RI,A
INC RO
INC RI
MOV A,R2
JNB
; SET FIRST BIT IN
ACe.
. OUTPUT TO SCAN
LINES.
; SHIFT TO ENABLE
NEXT COLUMN
NEXT.
; REMEMBER CURRENT SCAN
POSITION.
; READ RETURN
LINES.
; SWITCH WITH
PREVIOUS MAP
BITS.
; SAVE PREVIOUS
STATE AS WELL.
; BUMP POINTERS.
What happens after the sensors have been scanned
depends on the individual application. Rather than
inventing some artificial design problem, softVv'are corresponding to commonplace logic elements will be discussed.
Combinatorial Output Variables. An output variable
which is a simple (or not so simple) combinational function of several input variables is computed in the spirit of
Design Example 3. All 64 inputs are represented in the bit
maps; in fact, the sensor numbers in Figure 20 correspond
to the absolute bit addresses in RA M! The code in Example 4 activates an actuator connected to P2.2 when sensors
12, 23, and 34 are closed and sensors 45 and 56 are open.
Example 4.
Simple Combinatorial Output Variables.
; SET P2.2 = (12) (23) (34) (j 45) (j 56)
MOV C,12
ANL C,23
ANL C,34
ANL C,/45
ANL C,/56
MOV P2.2,C
; RELOAD SCAN LINE
MASK
ACe.7,SCAN; LOOP UNTIL ALL
EIGHT COLUMNS
READ.
RET
Intermediate Variables. The examination of a typical
relay-logic ladder diagram will show that many of the
rungs control not outputs but rather relays whose contacts figure into the computation of other functions. In
effect, these relays indicate the state of intermediate variables of a computation.
The M CS-5 I'M solution can use any directly addressable
bit for the storage of such intermediate variables. Even
when all 128 bits of the RAM array are dedicated (to input
bit maps in this example), the accumulator, PSW, and B
register provide 18 additional flags for intermediate
variables.
For example, suppose switches 0 through 3 control a
safety interlock system. Closing any of them should deactivate certain outputs. Figure 22 is a ladder diagram for
this situation. The interlock function could be recomputed
for every output affected, or it may be computed once and
saved (as implied by the diagram). As the program proceeds this bit can qualify each output.
Example 5. Incorporating Override signal into actuator
outputs.
CALL INPUT-SCAN
MOV C,O
ORL C,I
ORL C,2
ORL C,3
MOV FO,C
Figure 21. Flowchart for reading in sensor matrix.
01489A-28
C-26
At't'LI\"A
COMPUTE FUNCTION 0
IIUI~i)
Example 6. Simulating a latching relay.
ANL C,/FO
MOY PI.O,C
;L.-SET
L.-SET:
SET FLAG 0 IF C=I
ORL C,FO
MOY FO,C
COMPUTE FUNCTION I
ANL C,/FO
MOY PI.I,C
;L_RSET RESET FLAG 0 IF C=I
L_RSET: CPS C
ANL C,FO
MOY FO,C
COMPUTE FUNCTION 2
ANL C,/FO
MOY PI.2,C
Time Delay Relays. A time delay relay does not respond
to an input signal until it has been present (or absent) for
some predefined time. For example, a ballast or load
resistor may be switched in series with a D.C. motor when
it is first turned on, and shunted from the circuit after one
second. This sort of time delay may be simulated by an
interrupt routine driven by one of the two 8051 timer I
counters. The procedure followed by the routine depends
heavily on the details of the exact function needed; timeouts or time delays with resettable or non-resettable inputs
are possible. If the interrupt routine is executed every IO
milliseconds the code in Example 7 will clear an intermediate variable set by the background program after it
has been active for two seconds.
"2"
"3"
Example 7. Code to clear USRFLG after a fixed time delay.
JNB
DJNZ
CLR
MOY
USR_FLG,NXTTST
DLA Y_COUNT,NXTTST
USR_FLG
DLA Y_COUNT,#200
NXTTST:
Serial Interface to Remote Processor. When it detects
emergency conditions represented by certain input combinations (such as the earlier Emergency Override), the
controller could shut down the machine immediately
andl or alert the host processor via the serial port. Code
bytes indicating the nature of the problem could be transmitted to a central computer. In fact, at 17,000 bytes-persecond, the entire contents of both bit maps could be sent
to the host processor for further analysis in less than a
millisecond! If the host decides that conditions warrant, it
could alert other remote processors in the system that a
problem exists and specify which shut-down sequence
each should initiate. For more information on using the
serial port, consult the MCS-5ITM User's Manual.
Figure 22. Ladder diagram for output override
circuitry.
Latching Relays. A latching relay can be forced into either
the ON or OFF state by two corresponding input signals,
where it will remain until forced onto the opposite stateanalogous to a TTL Setl Reset flip-flop. The relay is used
as an intermediate variable for other calculations. In the
previous example, the emergency condition could be
remembered and remain active until an "emergency
cleared" button is pressed.
Response Timing.
One difference between relay and programmed industrial
controllers (when each is considered as a "black box") is
their respective reaction times to input changes. As
reflected by a ladder diagram, relay systems contain a
Any flag or addressable bit may represent a latching relay
with a few lines of code (see Example 6).
01489A
C-2?
At"t"LI~A
HUN:>
~
large number of "rungs" operating in parallel. A change in
input conditions will begin propagating through the system immediately, possibly affecting the output state
within milliseconds.
EXCLUSIVE-OR FUNCTION IMPOSEDON CARRY
USING FO IS INPUT VARIABLE.
XO!LFO: JNB FO.XORCNT ; ("J8" FOR X-NOR)
CPL C
XORCNT: ...
~
Software, on the other hand, operates sequentially. A
change in input states will not be detected until the next
time an input scan is performed, and will not affect the
outputs until that section of the program is reached. For
that reason the raw speed of computing the logical functions is of extreme importance.
XCH. The contents of the carry and some other bit may be
exchanged (switched) by using the accumulator as temporary storage. Bits can be moved into and out of the accumulator simultaneously using the Rotate-through-carry
instructions. though this would alter the accumulator
data.
Here the Boolean processor pays off. Every instruction
mentioned in this Note completes in one or two microseconds-the minimum instruction execution time for
many other microcontrollers! A ladder diagram containing a hundred rungs, with an average of four contacts per
rung can be replaced by approximately five hundred lines
of software. A complete pass through the entire matrix
scanning routine and all computations would require
about a millisecond~ less than the time it takes for most
relays to change state.
; EXCHANGE CARRY WITH USRFLG
XCHBIT: RLC
A
MOV
c'USR_FLG
RRC
A
MOV
USR_FLG.C
RLC
A
Extended Bit Addressing. The 8051 can directly address
144 general-purpose bits for all instructions in Figure 3.b.
Similar operations may be extended to any bit anywhere
on the chip with some loss of efficiency.
A programmed controller which simulates each Boolean
function with a subroutine would be less efficient by at
least an order of magnitude. Extra software is needed for
the simulation routines, and each step takes longer to
execute for three reasons: several byte-wide logical
instructions are executed per user program step (rather
than one Boolean operation)~ most of those instructions
take longer to execute with microprocessors performing
multiple off-chip accesses~ and calling and returning from
the various subroutines requires overhead for stack
operations.
The logical operations AND, OR. and Exclusive-OR are
performed on byte variables using six different addressing
modes. one of which lets the source be an immediate
mask. and the destination any directly addressable byte.
Any bit may thus be set, cleared, or complemented with a
three-byte. two-cycle instruction if the mask has all bits
but one set or cleared.
Byte variables, registers. and indirectly addressed RAM
may be moved to a bit addressable register (usually the
accumulator) in one instruction. Once transferred, the bits
may be tested with a conditional jump, allowing any bit to
be polled in 3 microseconds-still much faster than most
architectures,-or used for logical calculations. (This
technique can also simulate additional bit addressing
modes with byte operations.)
In fact. the speed of the Boolean Processor solution is
likely to be much faster than the system requires. The
CPU might use the time left over to compute feedback
parameters, collect and analyze execution statistics, perform system diagnostics, and so forth.
Additional functions and uses.
Parity of bytes or bits. The parity of the current accumulator contents is always available in the PSW, from
whence it may be moved to the carry and further processed. Error-correcting Hamming codes and similar
applications require computing parity on groups of isolated bits. This can be dO,ne by conditionally complementing the carry flag based on those bits or by gathering the
bits into the accumulator (as shown in the DES example)
and then testing the parallel parity flag.
With the building-block basics mentioned above many
more operations may be synthesized by short instruction
sequences.
Exclusive-OR. There are no common mechanical devices
or relays analogous to the Exclusive-OR operation, so this
instruction was omitted from the Boolean Processor.
However. the Exclusive-OR or Exclusive-NOR operation
may be performed in two instructions by conditionally
complementing the carry or a Boolean variable based on
the state of any other testable bit.
Multiple byte sh((t and C RC codes.
Though the 8051 serial port can accommodate eight- or
nine-bit data transmissions, some protocols involve much
01489A-30
C-28
APPLICATIONS
longer bit streams. The algorithms presented in Design
Example 2 can be extended quite readily to 16 or more bits
by using multi-byte input and output buffers.
Many mass data storage peripherals and serial communications protocols include Cyclic Redundancy (CRC)
codes to verify data integrity. The function is generally
computed serially by hardware using shift registers and
Exclusive-OR gates, but it can be done with software. As
each bit is received into the carry, appropriate bits in the
multi-byte data buffer are conditionally complemented
based on the incoming data bit. When finished, the CRC
register contents may be checked for zero by ORing the
two bytes in the accumulator.
This Application Note has detailed the information
needed by a microcomputer system designer to make full
use of these capabilities. Five design examples were used
to contrast the solutions allowed by the 8051 and those
required by previous architectures. Depending on the
individual application, the 8051 solution will be easier to
design, more reliable to implement, debug, and verify, use
less program memory, and run up to an order of magnitude faster than the same function implemented on previous digital computer architectures.
Combining byte- and bit-handling capabilities in a single
microcomputer has a strong synergistic effect: the power
of the result exceeds the power of byte- and bit-processors
laboring individually. Virtually all user applications will
benefit in some ways from this duality. Data intensive
applications will use bit addressing for test pin monitoring
or program control flags; control applications will use
byte manipulation for parallel I I 0 expansion or arithmetic calculations.
4. SUMMARY
A truly unique facet of the Intel MCS-5 I'M microcomputer
family design is the collection of features optimized for the
one-bit operations so often desired in real-world, real-time
control applications. Included are 17 special instructions,
a Boolean accumulator, implicit and direct addressing
modes, program and mass data storage, and many 1/0
options. These are the world's first single-chip microcomputers able to efficiently manipulate, operate on, and
transfer either bytes or individual bits as data.
It is hoped that these design examples give the reader an
appreciation of these unique features and suggest ways to
exploit them in his or her own application.
01489A
r..?Q
l'~
ISIS-II MCS-51 MACRO ASSEMBLER Vl.O
MODULE PLACED IN :FO:AP70.HEX
ASSEMBLER INVOKED BY:
: fl:asm51 ap70. src date(328)
LOC OB~
LINE
SOURCE
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$XREF TITLE(AP-70 APPENDIX)
2
3
i***************************************************** ***
4
5
6
7
8
9
10
THE FOLLOWING PROGRAM USES THE BOOLEAN INSTRUCTION SET
OF THE INTEL 8051 MICROCOMPUTER TO PERFORM A NUMBER OF
AUTOMOTIVE DASHBOARD CONTROL FUNCTIONS RELATING TO
TURN SIGNAL CONTROL, EMERGENCY BLINKERS, BRAKE LIGHT
CONTROL, AND PARKING LIGHT OPERATION.
THE ALGORITHMS AND HARDWARE ARE DESCRIBED IN DESJGN
EXAMPLE #4 OF INTEL APPLICATION NOTE AP-70,
"USING THE INTEL MCS-51
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0000 020040
OOOB
OOOB 758CFO
OOOE CODO
0010 0154
0040
0040 758AOO
0043 758CFO
0046 758961
0049
004C
004E
0050
0052
7520F4
D2A9
D2AF
D28C
80FE
0054 D52038
0057 7520F4
005A
005D
0060
0062
0065
0067
0069
006C
006E
0070
0073
0075
0077
007A
007C
007E
0081
0083
0085
0088
0
~
0
'"'":.-
4390EO
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C295
20B428
D295
C297
20B421
D297
C2Al
20B41A
D2Al
C296
20B413
D296
C2AO
20B40C
D2AO
C2A2
20B405
D2A2
008A 20B402
008D B2A3
LINE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99 +1
SOURCE
INIT:
UPDATE:
ORG
LJMP
OOOOH
INIT
RESET VECTOR
ORG
MOV
PUSH
AJMP
OOOBH
THO. #-16
PSW
UPDATE
TIMER 0 SERVICE VECTOR
HIGH TIMER BYTE ADJUSTED TO CONTROL INT. RATE
EXECUTE CODE TO SAVE ANY REGISTERS USED BELOW
(CONTINUE WITH REST OF ROUTINE)
ORG
MOV
MOV
MOV
0040H
TLO.#O
THO. #-16
TMOD.#OllOOOOlB
MOV
SETB
SETB
SETB
SJMP
SUB_DIV.#244
ETO
EA
TRO
$
DJNZ
MOV
SUB_DIV.TOSERV
SUB_DIV, #244
ORL
ORL
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
CLR
Pi. #111000008
P2,#000001118
L_FRNT
TO. FAULT
L_FRNT
L DASH
TO, FAULT
L_DASH
L_REAR
TO. FAULT
L_REAR
R_FRNT
TO,FAULT
R_FRNT
R_DASH
TO. FAULT
R DASH
R:=REAR
TO, FAULT
R_REAR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
;
ZERO LOADED INTO LOW-ORDER BYTE AND
-16 IN HIGH-ORDER BYTE GIVES 4 MSEC PERIOD
8-BIT AUTO RELOAD COUNTER MODE FOR TIMER 1.
16-BIT TIMER MODE FOR TIMER 0 SELECTED
SUBDIVIDE INTERRUPT RATE BY 244 FOR 1 HZ
USE TIMER 0 OVERFLOWS TO INTERRUPT PROGRAM
CONFIGURE IE TO GLOBALLY ENABLE INTERRUPTS
KEEP INSTRUCTION CYCLE COUNT UNTIL OVERFLOW
START BACKGROUND PROGRAM EXECUTION
EXECUTE SYSTEM TEST ONLY ONCE PER SECOND
GET VALUE FOR NEXT ONE SECOND DELAY AND
GO THROUGH ELECTRICAL SYSTEM TEST CODE:
SET CONTROL OUTPUTS HIGH
;
FLOAT DRIVE COLLECTOR
TO SHOULD BE PULLED LOW
PULL COLLECTOR BACK DOWN
REPEAT SEQUENCE FOR L_DASH.
L REAR.
R_FRNT.
R_DASH,
AND R__REAR.
WITH ALL COLLECTORS GROUNDED, TO SHOULD BE HIGH
IF SO, CONTINUE WITH INTERRUPT ROUTINE.
JB
FAULT:
CPL
TO. TOSERV
S_FAIL
;
$EJECT
ELECTRICAL FAILURE PROCESSING ROUTINE
(TOGGLE INDICATOR ONCE PER SECOND)
»
"0
"0
r-
0
»
-I
0
Z
(Jl
LoC
oBJ
LINE
SOURCE
100
101
102
CONTINUE WITH INTERRUPT PROCESSING:
1)
COMPUTE LOW BULB INTENSITY WHEN PARKING LIGHTS ARE ON.
103
008F
0091
0093
0095
0097
A201
8200
7202
8292
9201
104
TOSERV:
105
106
107
108
MOV
ANL
ORL
ANL
MOV
C, SUB_DIV. 1
C,SUB_DIV.O
C,SUB_DIV.2
C,PARK
DIM,C
;
;
;
;
START WITH 50 PERCENT,
MASK DOWN TO 25 PERCENT,
BUILD BACK TO 62. 5 PERCENT,
GATE WITH PARKING LIGHT SWITCH,
AND SAVE IN TEMP. VARIABLE.
109
0099
009B
0090
009F
A293
7291
8207
9297
OOAI 92D5
00A3 7201
00A5 9295
110
111
112
113
114
115
116
117
118
2)
COMPUTE AND OUTPUT LEFT-HAND DASHBOARD INDICATOR.
MOV
ORL
ANL
MOV
3)
120
121
; SET CARRY IF TURN
OR EMERGENCY SELECTED.
IF SO, GATE IN 1 HZ SIGNAL
AND OUTPUT TO DASHBOARD.
;
COMPUTE AND OUTPUT LEFT-HAND FRONT TURN SIGNAL.
MoV
oRL
MoV
119
C,L_TURN
C,EMERG
C,LO_FREG
L_DASH,C
FO,C
C,DIM
L_FRNT, C
; SAVE FUNCTION SO FAR.
; ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
122
123
124
o
W
00A7
00A9
OOAB
OOAD
I\.)
OO.~F
A290
B093
7205
7201
92Al
4)
COMPUTE AND OUTPUT LEFT-HAND REAR TURN SIGNAL.
MoV
ANL
oRL
oRL
MOV
125
126
127
128
129
C,BRAKE
C, IL_TURN
C,FO
C. DIM
L_REAR, C
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER.
; INCLUDE TEMP. VARIABLE FROM DASH
; AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
130
131
OOBI
00B3
00B5
00B7
00B9
OOBB
OOBD
OOBF
OOCI
00C3
00C5
00C7
o
'"»
A294
7291
8207
92AO
9205
7201
9296
A290
B094
7205
7201
92A2
00C9 DODO
OOCB 32
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
! 51
5)
REPEAT ALL OF ABOVE FOR RIGHT-HAND COUNTERPARTS.
MoV
oRL
ANL
MoV
MoV
oRL
MoV
MoV
ANL
oRL
oRL
MoV
C,R_TURN
C,EMERG
C. LO_FREG
R_DASH,C
FO,C
C,DIM
R_FRNT, C
C,BRAKE
C,/R_TURN
C,FO
C. DIM
R_REAR, C
SET CARRY IF TURN
; OR EMERGENCY SELECTED.
IF SO, GATE IN 1 HZ SIGNAL
; AND OUTPUT TO DASHBOARD.
i
SAVE FUNCTION SO FAR.
; ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER.
; INCLUDE TEMP. VARIABLE FROM DASH
; AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
RESTORE STATUS REGISTER AND RETURN.
POP
RETI
END
PSW
RESTORE PSW
AND RETURN FROM INTERRUPT ROUTINE
»
."
."
!:
o
»
o
:::!
z
en
XREF SYMBOL TABLE LISTING
-------
(')
W
(0)
NAME
TYPE
VALUE AND REFERENCES
BRAKE
DIM
EA.
EMERG
ETa
FO.
FAULT
HI_FREQ
INIT.
L_DASH.
L_FRNT.
L_REAR.
L_TURN.
LO_FREQ
PI.
P2.
PARK.
PSW
R_DASH.
R_FRNT.
R_:REAR.
R_TURN.
S_FAIL.
SUB_DIV
TO.
TOSERV.
THO
TLO
TI'Oli).
N
N
N
N
N
N
L
N
L
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
L
BSEG
BSEG
BSEG
BSEG
BSEG
BSEG
CSEG
BSEG
CSEG
BSEG
BSEG
BSEG
BSEG
BSEG
DSEG
DSEG
BSEG
DSEG
BSEG
BSEG
BSEG
BSEG
BSEG
DSEG
BSEG
CSEG
0090H
OODIH
OOAFH
0091H
00A9H
00D5H
008DH
OOOOH
0040H
0097H
0095H
OOAIH
0093H
0007H
0090H
OOAOH
0092H
OODOH
OOAOH
0096H
00A2H
0094H
00A3H
0020H
OOB4H
OOeFH
N.DSEG
N DSIEG
N D'S:E~
(}()I!ilCH
()()t)I.A;H
OO~
5/0
6rO
TfIIIO
\'III B1ilEG
008CH
.::11
UF"J.l-ATE.
L C':G
005At+l
55
A!S!lEMGL Y CDf"If'LETE,
~
20# 125 140
45# 108 120 128 138 143
64
21# 113 134
63
119 127 137 142
75 78 81 84 87 90 97#
42#
50 58#
32# 77 79 115
30# 74 76 121
34# 80 82 129
23# 112 126
43# 114 135
20 21 22 23 24 30 31 32 72
33 34 35 37 73
22# 107
45 54 148
33# 86 88 136
31# 83 85 139
35# 89 91 144
24# 133 141
37# 97
41# 42 43 62 69 70 104 105 106
75 79 81 84 87 90 96
69 9" 104#
53 ~
6.~#
NO Elltfit~$"'~
»""C
""C
r-
(')
»
-t
0
Z
(J)
u.s. AND CANADIAN SALES OFFICES
3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8080
TWX: 910·338·0026
TELEX: 34-6372
ALABAMA
CONNECTICUT
MICHIGAN
OHIO
Intel Corp.
303 Williams Avenue. S.W.
Suite 1422
Huntsville 35801
Tel: (205) 533·9353
Intel Corp.
Peacock Alley
1 Padanaram Road, Suite 146
Danbury 06610
Tel: (203) 792-l1366
TWX: 710-456·1199
Intel Corp.'
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313) 353'()920
TWX: 810-244·4915
Intel Corp."
6500 Poe Avenue
Dayton 45415
Tel: (513) 890-5350
TWX: 810·450·2528
Pen-Tech Associates, Inc.
Holiday Office Center
3322 Memorial Pkwy., S.w.
Huntsville 35801
Tel: (205) 881·9298
ARIZONA
Intel Corp.
10210 N. 25th Avenue, Suite 11
Phoenix 85021
Tel: (602) 997·9695
BFA
4426 North Saddle Bag Trail
Scottsdale 85251
Tel: (602) 994·5400
FLORIDA
Intel Corp.
1001 N.w. 62nd Street, Suite 406
Ft. Lauderdale 33309
Tel: (305) 771·0600
TWX: 510-956·9407
Intel Corp.
5151 Adanson Street, Suite 203
Orlando 32804
Tel: (305) 628-2393
TWX: 810-853·9219
CALIFORNIA
Pen·Tech ASSOciates, Inc.
201 S.E. 15th Terrace, Suite K
Deerfield Beach 33441
Tel: (305) 421·4989
Intel Corp.
7670 Opportunity Rd
Suite 135
San Diego 92111
Tel: (714) 266·3563
Pen·Tech ASSOciates, Inc.
111 So. Maitland Ave., Suite 202
P.O. Box 1475
Maitland 32751
Tel: (305) 645·3444
Intel Corp.'
2000 East 4th Street
Suite 100
Santa Ana 92705
Tel: (714) 835·9642
TWX: 910-595·1114
Intel Corp.'
15335 Morrison
Suite 345
Sherman Oaks 91403
Tel: (213) 966·9510
TWX: 910-495·2045
Intel Corp.'
3375 Scott Illvd.
Santa Clara 95051
Tel: (408) 987·6086
TWX: 910·339·9279
910·338·0255
Earle Associates, Inc.
4617 Ruffner Street
Suite 202
San Diego 92111
Tel: (714) 278·5441
Mac·1
2576 Shattuck Ave.
Suite 4B
Berkeley 94704
Tel: (415) 843·7625
Mac·1
P.O. Box 1420
Cupertino 95014
Tel: (408) 257·9660
Mac·'
558 Valley Way
Calaveras Business Park
Milpitas 95035
Tel: (408) 946·8665
Mac·1
P.O. Box 8763
Fountain Valley 92708
Tel: (714) 839·3341
Mac·'
1321 Centinela Avenue
Suite 1
Santa Monica 90404
Tel: (213) 829·4797
Mac·1
20121 Ventura Blvd., Suite 240E
Woodland HillS 91364
Tel: (213) 347·5900
COLORADO
Intel Corp.'
650 S. Cherry Street
Suite 720
Denver 80222
Tel: (303) 321·8066
TWX: 910·931·2289
Westek Data Products. Inc.
25921 Fern Gulch
P.O. Box 1355
Evergreen 80439
Tel: (303) 674·5255
Westek Data Products, Inc
1322 Arapahoe
Boulder 80302
Tel: (303) 449·2620
Westek Data Products, Inc.
1228 W. Hinsdale Dr.
Littleton 80120
Tel: (303) 797·0482
GEORGIA
Pen Tech Associates, Inc
Cherokee Center, Suite 21
627 Cherokee Street
Marietta 30060
Tel: (404) 424·1931
Lowry & Associates, Inc.
135 W. North Street
Suite 4
Brighton 48116
Tel: (313) 227·7067
Lowry & Associates, Inc.
3902 Costa NE
Grand Rapids 49505
Tel: (616) 363-9839
MINNESOTA
Intel Corp.
7401 Metro Blvd.
Suite 355
Edina 55435
Tel: (612) 835-6722
TWX: 910-576-2887
MISSOURI
Intel Corp.
502 Earth City Plaza
Suite 121
Earth City 63045
Tel: (314) 291·1990
Technical Representatives, Inc.
320 Brookes Drive, Suite 104
Hazelwood 63042
Tel: (314) 731·5200
TWX: 910·762'()618
ILLINOtS
Intel Corp.'
2550 Golf Road, Suite 815
Rolling Meadows 60008
Tel: (312) 981·7200
TWX: 910-651·5661
Technical Representatlv'·.'2
1502 North Lee Street
Bloomington 61701
Tel: (309) 829·8080
INDIANA
Intel Corp.
9101 Wesleyan Road
Suite 204
Indianapolis 46268
Tel: (317) 299·0623
IOWA
Technical Representatives, Inc.
St. Andrews Building
1930 St. Andrews Drive N.E.
Cedar Rapids 52405
Tel: (319) 393·5510
KANSAS
Intel Corp.
9393 W. 110th St., Ste. 265
Overland Park 66210
Tel: (913) 642·8080
Technical Representatives, Inc.
8245 Nieman Road, Suite 100
Lenexa 66214
Tel: (913) 888·0212, 3, & 4
TWX: 910·749·6412
Technical Representatives, Inc.
360 N. Rock Road
Suite 4
Wichita 67206
Tel: (316) 68Hl242
MARYLAND
Intel Corp.'
7257 Parkway Drive
Hanover 21076
Tel: (301) 796·7500
TWX: 710·862·1944
Mesa Inc.
11900 Park lawn Drive
Rockville 20852
Tel: Washington (301) 661·8430
Baltimore (301) 792'()021
MASSACHUSETIS
Intel Corp.'
27 Industrial Ave.
Chelmsford 01824
Tel: (617) 667·8126
TWX: 710·343-6333
EMC Corp.
381 Elliot Street
Newton 02164
Tel: (617) 244·4740
TWX: 922531
NEW JERSEY
Intel Corp.·
Raritan Plaza
2nd Floor
Raritan Center
Edison 06617
Tel: (201) 225·3000
TWX: 710·480-6238
NEW MEXICO
BFA Corporation
P.O. Box 1237
Las Cruces 88001
Tel: (505) 523-0601
TWX: 910·983'()543
BFA Corporation
3705 Westerfield, N.E.
Albuquerque 87111
Tel: (505) 292·1212
TWX: 910·989·1157
Intel Corp."
Chagrin·Brainard Bldg., No. 210
28001 Chagrin Blvd
Cleveland 44122
Tel: (216) 464·2736
TWX: 810-427·9298
OREGON
Intel Corp.
t0700 S.w. Beaverton
Hiltsdale Highway
Suite 324
Beaverton 97005
Tel: (503) 641-8086
TWX: 910-467-8741
PENNSYLVANIA
Intel Corp."
275 Commerce Dr.
200 Office Center
Suite 300
Fort Washington 19Q3.4
Tel: (215) 542·9444
TWX: 510-661·2077
Q.E.D. Electronics
300 N. York Road
Hatboro 19040
Tel: (215) 674·9600
TEXAS
Intel Corp."
2925 L. B.J. Freeway
Suite 175
Daltas 75234
Tel: (214) 241·9521
TWX: 910-860·5617
Intel Corp."
6420 Richmond Ave.
Suite 280
Houston 77057
Tel: (713) 784·3400
TWX: 910-881·2490
Industrial Digital Systems Corp.
5925 Sovereign
Suite 101
Houston 77036
Tel: (713) 966·9421
Intel Corp.
313 E. Anderson Lane
Suite 314
Austin 78752
Tel: (512) 454·3628
NEW YORK
Intel Corp.'
350 Vanderbilt Motor Pkwy.
Suite 402
Hauppauge 11787
Tel: (516) 231-3300
TWX: 510·227·6236
Intel Corp.
80 WaShington 51.
Poughkeepsie 12601
Tel: (914) 473-2303
TWX: 510·248'()060
Intel Corp.'
2255 Lyell Avenue
Lower Floor East Suite
Rochester 14606
Tel: (716) 254-6120
TWX: 510·253·7391
Measurement Technology, Inc.
159 Northern Boulevard
Great Neck 11021
Tel: (516) 482·3500
T·Squared
4054 Newcourt Avenue
Syracuse 13206
Tel: (315) 463-8592
TWX: 710·541'()554
T·Squared
2 E. Main
Victor 14564
Tel: (716) 924·9101
TWX: 510·254·8542
NORTH CAROLINA
Intel Corp.
154 Huffman Mill Rd.
Burlington 27215
Tel: (919) 564·3631
Pen·Tech ASSOCiates, Inc.
1202 Eastchester Dr.
Highpoint 27280
Tel: (919) 883·9125
WASHINGTON
Intel Corp.
Suite 114, Bldg. 3
1803 116th Ave. N.e.
Bellevue 98005
Tel: (206) 453-8066
TWX: 910·443·3002
WISCONSIN
Intel Corp.
150 S. Sunny slope Rd.
Brookfield 53005
Tel: 1414) 784·9080
CANADA
Intel Semiconductor Corp.·
Suite 233, Bell Mews
39 Highway 7, 8ells Corners
Ottawa, OntariO K2H 8R2
Tel: (613) 829·9714
TELEX: 053·4115
Intel Semiconductor Corp.
50 Galaxy Blvd.
Unit 12
Rexdale, Ontario
M9W4Y5
Tel: (416) 675·2105
TELEX: 06983574
Multilek, Inc."
15 Grenfell Crescent
Ottawa, Ontario K2G OG3
Tel: (613) 226·2365
TELEX: 053·4585
Multilek, Inc
Toronto
Tel: (416) 245·4622
Multilek, Inc.
Montreal
Tel: (514) 481-1350
• Field Application Location
u.s. AND CANADIAN
DISTRIBUTORS
ALABAMA
COLORADO
ILLINOIS
MINNESOTA
tHamilton/Avnet Electronics
4812 Commercial Drive N.w.
Huntsville 35805
Tel: (205) 837·7210
Arrow Electronics, Inc.
Electronics Distribution Division
2121 South Hudson Street
Denver 80222
Tel: (303) 758·2100
Arrow Electronics
492 Lunt Avenue
P.O. Box 94248
Schaumburg 60193
Tel: (312) 893·9420
TWX: 910·222·1807
tlndustrial Components
5229 Edina Industrial Blvd.
Minneapolis 55435
Tel: (612) 831·2666
TWX: 910·576·3153
tPloneer/Huntsvilie
1207 Putman Drive NW
Huntsville 35805
Tel: (205) 837·9033
TWX: 810·726·2197
ARIZONA
tHamliton/Avnet Electronics
505 S. Madison Drive
Tempe 85281
Tel: (602) 275·7851
tWyle Distribution Group
8155 N. 24th Avenue
Phoenix 85021
Tel: (602) 249·2232
TWX: 910·951-4282
CALIFORNIA
tWyle Distribution Group
6777 E. 50th Avenue
Commerce City 80022
Tel: (303) 287·9611
TWX: 910·931'()510
t Hamilton/Avnet Electronics
8765 E. Orchard Road
Suite 708
Englewood 80111
Tel: (303) 740·1000
TWX: 910·931·0510
tPioneerlindiana
6408 Castleplace Drive
Indianapolis 46250
Tel: (317) 849·7300
TWX: 810·260·1794
Arrow Electronics, Inc.
Electronics Distribution Division
720 Palomar Avenue
Sunnyvale, California 94086
Tel: (408) 739·3011
tHarvey Electronics
112 Main Street
Norwalk 06851
Tel: (203) 853·1515
TWX: 710·468·3373
tHamiiton/Avnet Electronics
4545 Viewridge Ave.
San Diego 92123
Tel: (714) 571·7510
TWX: 910·335·1216
tHamilton/Avnet Electronics
10950 W. Washington Blvd.
Culver City 90230
Tel: (213) 558·2609
TWX: 910·340-6364 or 7073
tHamilton Electro Sales
3170 Pullman Street
Costa Mesa 92626
Tel: (714) 641·4100
t Avnet Electronics
4942 Rosecrans Ave.
Hawthorne 90250
Tel: (213) 970·0956
tWyle Distribution Group
124 Maryland Street
EI Segundo 90245
Tel: (213) 322·3826
TWX: 910·348·7140 or 7111
tWyle Distribution Group
9525 Chesapeake Dr.
San Diego 92123
Tel: (714) 565·9171
TWX: 910·335·1590
tWyle Distribution Group
3000 Bowers Avenue
Santa Clara 95052
Tel: (408) 727·2500
TWX: 910·338'()451 or 0296
Hamilton/Avnet Electronics
3170 Pullman
Costa Mesa 92626
Tel: (714) 641·1850
tArrow Electronics
5230 W. 73rd Street
Edina 55435
Tel: (612) 830·1800
TWX: 910·576·2726
tHamilton/Avnet Electronics
7449 Cahill Road
Edina 55435
Tel: (612) 941·3801
TWX: 910·576·2720
MISSOURI
INDIANA
tArrow Electronics
12 Beaumont Road
Wallingford 06492
Tel: (203) 265·7741
TWX: 710·476'()162
tHamiiton/Avnet Electronics
643 Danbury Road
Georgetown 06829
Tel: (203) 762·0361
Hamilton/Avnet Electronics
1175 Bordeaux' Dr.
Sunnyvale 94086
Tel: (408) 743·3355
TWX: 910·339·9332
Pioneer/Chicago
1551 Carmen Drive
Elk Grove 60007
Tel: (312) 437·9680
TWX: 910·222·1834
CONNECTICUT
Arrow Electronics, Inc.
Electronics Distribution Division
9511 Ridge Haven Court
San Diego 92123
Tel: (714) 565·4800
t Avnet Electronics
350 McCormick Avenue
Costa Mesa 92626
Tel: (714) 754·6111
TWX: 910·595·1928
tHamilton/Avnet Electronics
3901 No. 25th Avenue
Schiller Park 60176
Tel: (312) 678·6310
TWX: 910·227'()060
tHamillon/Avnet Electronics
396 Brookes Lane
Hazelwood 63042
Tel: (314) 731·1144
TWX: 910·762'()606
NEW HAMPSHIRE
KANSAS
tHamiitonlAvnet Electronics
9219 Quivira Road
Overland Park 66215
Tel: (913) 888·8900
tComponent Specialties, Inc.
8369 Nieman Road
Lenexa 66214
Tel: (913) 492·3555
FLORIDA
tArrow Electronics
1001 N.w. 62nd Street
Suite 108
Flo Lauderdale 33309
Tel: (305) 776·7790
tArrow Electronics
115 Palm Bay Road, NW
Suite 10, Bldg. 200
Palm Bay 32905
Tel: (305) 725·1480
TWX: 510·959·6337
tHamilton/Avnet Electronics
6800 Northwest 20th Ave.
Flo Lauderdale 33309
Tel: (305) 971·2900
TWX: 510·955·3097
tPioneer/Orlando
6220 S. Orange Blossom Trail
Suite 412
Orlando 32609
Tel: (305) 859·3600
TWX: 810·850·0177
Hamilton/Avnet Electronics
3197 Tech. Drive North
SI. Petersburg 33702
Tel: (813) 576·3930
TWX: 810-863'()374
GEORGIA
Arrow Electronics
2979 Pacific Drive
Norcross 30071
Tel: (404) 449·8252
TWX: 810·757·4213 .
tHamiltonlAvnet Electronics
6700 1·85 Access Road, No. 11
Suite IE
Norcross 30071
Tel: (404) 448'()800
MARYLAND
Arrow Electronics, Inc.
Electronics Distribution Division
4801 Benson Avenue
Baltimore 21227
Tel: (301) 247·5200
(202) 737·1700
tHamiltonlAvnet Electronics
7235 Standard Drive
Hanover 21076
Tel: (301) 796·5684
TWX: 710·862·1861
tPioneer/Washington
9100 Gaither Road
Gaithersburg 20760
Tel: (301) 948·0710
TWX: 710·828·0545
MASSACHUSETTS
tHamiltonlAvnet Electronics
50 Tower Office Park
Woburn 01801
Tel: (617) 273·7500
tArrow Electronics
1 Perimeter Road
Manchester 03103
Tel: (603) 668·6968
NEW JERSEY
tArrow Electronics
Pleasant Valley Avenue
Moorestowll 08057
Tel: (609) 235·1900
TWX: 710·897'()829
tArrow Electronics
285 Midland Avenue
Saddle Brook 07662
Tel: (201) 797·5800
TWX: 710·988·2206
Hamilton/Avnet Electronics
10 Industrial Road
Fairfield 07006
Tel: (201) 575·3390
TWX: 710·734·4338
t Harvey Electronics
45 Route 46
Pinebrook 07058
Tel: (201) 575·3510
TWX: 710·734·4382
tHamilton/Avnet Electronics
1 Keystone Ave.
Bldg. 36
Cherry Hill 08034
Tel: (609) 424'()100
TWX: 710·897·1405
NEW MEXICO
tArrow Electronics
960 Commerce Way
Woburn 01801
Tel: (617) 933·8130
tAliiance Electronics Inc.
11721 Central Ave. N.E.
Albuquerque 87123
Tel: (505) 292·3360
TWX: 910·989·1151
Harvey/Boston
44 Hartwell Ave.
Lexington 02173
Tel: (617) 861·9200
Arrow Electronics, Inc.
Electronics Distribution Division
2460 Alamo Avenue, Southeast
Albuquerque 87106
Tel: (505) 243·4566
MICHIGAN
tArrow Electronics
3810 Varsity Drive
Ann Arbor 48104
Tel: (313) 971·8220
TWX: 810·223-6020
tHamiiton/Avnet Electronics
2524 Baylor Drive, S.E.
Albuquerque 87106
Tel: (505) 765·1500
tPioneer/Michigan
13485 Stamford
Livonia 48150
Tel: (313) 525·1800
TWX: 810·242·3271
tHamiitonlAvnet Electronics
32487 Schoolcraft Road
Livonia 48150
Tel: (313) 522·4700
TWX: 810·242·8775
tMicrocomputer System Technical Demonstrator Centers
u.s. AND CANADIAN
DISTRIBUTORS
NEW YORK
OHIO
TEXAS
CANADA
Harvey Electronics
P.O. Box 1208
Blnghampton 13902
Tel: (607) 748·8211
TWX: 510·252'()893
Arrow Electronics
7620 McEwen Road
Centerville 45459
Tel: (513) 435·5563
TWX: 810·459·1611
Arrow Electronics
13715 Gamma Road
Dallas 75234
Tel: (214) 386·7500
TWX: 910-861·5495
Zentronics
9224 27th Avenue
Edmonton T6N 1 B2
Arrow Electronics
900 Broad Hollow Road
Farmingdale 11735
Tel: (516) 694-6800
TWX: 510·224-6494
Arrow Electronics
6238 Cochran Rd.
Solon 44139
Tel: (216) 248·3990
Arrow Electronics, Inc.
Electronics Distribution Division
10700 Corporate Drive, Suite 100
Stafford 77477
Tel: (713) 491-4100
tL.A. Varah Ltd.
4742 14th Street N.E.
Calgary T2E 6L7
Tel: (403) 230·1235
TWX: 018·258·97
Component Specialties Inc.
8222 Jamestown Drive
Suite 115
Austin 78757
Tel: (512) 837-8922
TWX: 910·874·1320
Zentronics
3651 21st N.E.
Calgary T2E 6T5
Tel: (403) 230·1422
Hamilton/Avnet Electronics
10508A Boyer Blvd.
Austin 78757
Tel: (512) 837·8911
tL.A. Varah Ltd.
2077 Alberta Street
Vancouver V5Y lC4
Tel: (604) 873·3211
TWX: 610·929·1068
tArrow Electronics
3000 South Winton Road
Rochester 14623
Tel: (716) 275·0300
TWX: 910·338'()026
t Hamllton/Avnet Electronics
167 Clay Road
Rochester 14623
Tel: (716) 475·9130
TWX: 910·340-6364
tArrow ElectroniCS
7705 Maltlage Drive
Liverpool 13088
Tel: (315) 652·1000
TWX: 710·545'()230
Arrow ElectroniCS
20 Oser Avenue
Hauppauge 11787
Tel: (516) 231-1000
TWX: 510·224-6494
t Hamilton/Avnet Electronics
16 Corporate Circle
E. Syracuse 13057
Tel: (315) 437·2641
tHamiiton/Avnet Electronics
5 Hub Drive
Melville, Long Island 11746
Tel: (516) 454·6000
TWX: 510·252'()893
t Harvey ElectroniCS
60 Crossways Park West
Woodbury 11797
Tel: (516) 921·8700
TWX: 510·221·2184
Harvey/Rochester
840 Airport Park
Fairport 14450
Tel: (716) 381·7070
NORTH CAROLINA
Pioneer/Carolina
106 Industrial Ave.
Greensboro 27406
Tel: (919) 273·4441
TWX: 510·925·111:4
t Hamilton/Avnet Electronics
2803 Industrial Drive
Raleigh 27609
Tel: (919) 829·8030
Arrow Electronics
938 Burke Street
Winston·Salem 27102
Tel: (919) 725·8711
TWX: 510·922·4765
tHamilton/Avnet Electronics
954 Senate Drive
Dayton 45459
Tel: (513) 433·0610
TWX: 910·340·2531
tPioneerlDayton
1900 Troy Street
Dayton 45404
Tel: (513) 236·9900
TWX: 81()"459·1622
Arrow Electronics
10 Knollcrest Dr.
Cincinnati 45237
Tel: (513) 761·5432
TWX: 810·461·2670
t Pioneer/Cleveland
4800 E. 131st Street
Cleveland 44105
Tel: (216) 587·3600
TWX: 810-422·2210
ALBERTA
tHamiiton/Avnet ElectroniCS
4445 Sigma Road
Dallas 75240
Tel: (214) 661·8661
TWX: 910-860·5371
tHamilton/Avnet Electronics
3939 Ann Arbor Drive
Houston 77063
Tel: (713) 780·1771
t Hamllton/Avnet Electronics
4588 Emery Industrial Parkway
Warrensville Heights 44128
Tel: (216) 831·3500
tComponent Specialties, Inc.
10907 Shady Trail, Suite 101
Dallas 75220
Tel: (214) 357·6511
TWX: 910-861·4999
OKLAHOMA
tComponent Specialties, Inc.
8585 Commerce Park Drive, Suite 590
Houston 77036
Tel: (713) 771·7237
TWX: 910-881·2422
tComponents Specialties, Inc.
7920 E. 40th Street
Tulsa 74145
Tel: (918) 664·2820
TWX: 910-845·2215
UTAH
OREGON
t Hamilton/Avnet Electronics
6024 SW Jean Rd.
Bldg. C, Suite 10
Lake Oswego 97034
Tel: (503) 635-8157
tAlmac/Stroum Electronics
8022 S.W. Nimbus, Bldg. 7
Beaverton 97005
Tel: (503) 641·9070
PENNSYLVANIA
Pioneer/Pittsburgh
560 Alpha Drive
Pittsburgh 15238
Tel: (412) 782·2300
TWX: 710·795·3122
Pioneer/Delaware Valley
141 Gibraltar Road
Horsham 19044
Tel: (215) 674·4000
TWX: 510-665-6778
tArrow/ ElectroniCS
4297 Greensburg Pike
Suite 3114
Pittsburgh 15221
Tel: (412) 351·4000
TENNESSEE
tArrow Electronics
P.O. Box 129
W. Andrew Johnson Hwy.
Talbott 37677
Tel: (615) 587·2137
tHamilton/Avnet Electronics
1585 West 2110 South
Salt Lake City 84119
Tel: (801) 972·2800
WASHINGTON
Arrow Electronics, Inc.
Electronics Distribution Division
1059 Andover Park East
Tukwila 98188
Tel: (206) 575'()907
tHamilton/Avnet Electronics
14212 N.E. 21st Street
Bellevue 98005
Tel: (206) 746·8750
tAlmac/Stroum Electronics
5811 Sixth Ave. South
Seattle 98108
Tel: (206) 763·2300
TWX: 910·444·2067
tWyle Distribution Group
1750 132nd Avenue NE
Bellevue 98005
Tel: (206) 453·8300
TWX: 910·443·2526
WISCONSIN
tArrow ElectroniCS
430 W. Rawson Avenue
Oak Creek 53154
Tel: (414) 764-6600
TWX: 910·338'()026
t Hamilton/Avnet Electronics
2975 Moorland Road
New Berlin 53151
Tel: (414) 784·4510
TWX: 910·262·1182
BRITISH COLUMBIA
Zentronlcs
550 Cambie SI.
Vancouver V6B 2N7
Tel: (604) 688·2533
TWX: 04·5077-89
MANITOBA
L.A. Varah
1·1832 King Edward Street
Winnipeg R2R ONl
Tel: (204) 633-6190
TWX: 07·55·365
Zentronics
590 Berry SI.
Winnipeg R3H OSl
Tel: (204) 775·8661
ONTARIO
tL.A. Varah, Ltd.
505 Kenora Avenue
Hamilton L8E 3P2
Tel: (416) 561·9311
TWX: 061-8349
tHamiiton/Avnet ElectroniCS
3688 Nashua Drive, Units G & H
M isslssauga L4V 1 M5
Tel: (416) 677·7432
TWX: 610·492·8660
tHamliton/Avnet Electronics
1735 Courtwood Crescent
Ottawa K2C 3J2
Tel: (613) 226·1700
tZentronics
141 Catherine Street
Ottawa K2P 1C3
Tel: (613) 238-6411
TWX: 053·3636
tZentronics
1355 Meyerside Drive
Mississauga, Ontario L5T lC9
Tel: (416) 676·9000
Telex: 06·983-657
QUEBEC
tHamilton/Avnet Electronics
2670 Sabourin Street
SI. Laurent H4S 1M2
Tel: (514) 331·6443
TWX: 610·421·3731
Zentronics
5010 Pare Street
Montreal H4P 1 P3
Tel: (514) 735·5361
TWX: 05·827·535
tMicrocomputer System Technical Demonstrator Centers
INTERNATIONAL SALES AND MARKETING OFFICES
....... ~" ... A
or. "' ...
A I
" " Il:;nl""II\,II""L.
ft ....... "' ................ " , , , . . . . "' ... , , . . . . . . . . . . . ,, .... """
UI~lnIDUIVn~'nl:;,.nl:;~I:; ... I"llyC~
ARGENTINA
FINLAND
ITALY
SOUTH AFRICA
Micro Sistemas S.A.
9 De Julio 561
Cordoba
Tel: 54-51-32-880
TELEX: 51837 BICCO
Oy Fintronic AB
Melkonkatu 24 A
SF-00210
Helsinki 21
Tel: 0-6926022
TELEX: 124224 Ftron SF
Eledra 3S S.P.A.·
Viale Elvezia, 18
I 20154 Milan
Tel: (02) 34.93.041-31.85.441
TELEX: 332332
Electronic Building Elements
Pine Square
18th Street
Hazelwood, Pretoria 0001
Tel: 789221
TELEX: 30181SA
AUSTRALIA
A_J_F. Systems & Components Pty. Ltd.
310 Queen Street
Melbourne
Victoria 3000
Tel:
TELEX:
Warburton Franki
Corporate Headquarters
372 Eastern Valley Way
Chats wood, New South Wales 2067
Tel: 407-3261
TELEX: AA 21299
AUSTRIA
Bacher Elektronische Geraete GmbH
Rotenmulgasse 26
A 1120 Vienna
Tel: (0222) 83 63 96
TELEX: (01) 1532
Rekirsch Elektronik Geraete GmbH
Lichtensteinstrasse 97
A 1000 Vienna
Tel: (222) 347646
TELEX: 74759
JAPAN
FRANCE
Celdis S.A.'
53, Rue Charles Frerot
F-94250 Genti IIy
Tel: (1) 581 00 20
TELEX: 200 485
Asahi Electronics Co. Ltd.
KMM Bldg. Room 407
2-14-1 Asano, Kokura
Kita-Ku, Kitokyushu City 802
Tel: (093) 511-6471
TELEX: AECKY 7126-16
Feutrier
Rue des Trois Glorieuses
F-42270 SI. Priest-en-Jarez
Tel: (77) 74 67 33
TELEX: 300 0 21
Hamilton-Avnet Electronics Japan Ltd.
YU and YOU Bldg. 1-4 Horidome-Cho
Nihonbashi
Tel: (03) 662-9911
TELEX: 2523774
Metrologie'
La Tour d' Asnieres
4, Avenue Laurent Cely
92606-Asnieres
Tel: 791 44 44
TELEX: 611 448
Nippon Micro Computer Co. Ltd.
Mutsumi Bldg. 4-5-21 Kojimachi
Chlyoda-ku, Tokyo 102
Tel: (03) 230-0041
Tekelec Airtronic'
Cite des Bruyeres
Rue Carle Vernet
F-92310 Sevres
Tel: (1) 534 7535
TELEX: 204552
GERMANY
BELGIUM
Inelco Belgium S.A.
Ave. des Croix de Guerre 94
B1120 Brussels
Tel: (02) 216 01 60
TELEX: 25441
BRAZIL
Icotron S.A.
0511-Av. Mutinga 3650
6 Andar
Pirituba-Sao Paulo
Tel: 261-0211
TELEX: (011) 222 ICO BR
CHILE
DIN
Av. Vic. Mc kenna 204
Casilla 6055
Santiago
Tel: 227564
TELEX: 3520003
CHINA
C.M. Technologies
525 University Avenue
Suite A-40
Palo Alto, CA 94301
COLOMBIA
International Computer Machines
Adpo. Aereo 19403
Bogota 1
Tel: 232-6635
TELEX: 43439
CYPRUS
Cyprus Eltrom Electronics
P.O. Box 5393
Nicosia
Tel: 21-27982
DENMARK
STL-Lyngso Komponent A/S
Ostmarken 4
OK-2860 Soborg
Tel: (01) 67 00 77
TELEX: 22990
Scandinavian Semiconductor
Supply AlS
Nannasgade 18
OK-2200 Copenhagen
Tel: (01) 83 5090
TELEX: 19037
Electronic 2000 Vertriebs GmbH
Neumarkter Strasse 75
0-8000 Munich 80
Tel: (089) 434061
TELEX: 522561
Jermyn GmbH
Postfach 1180
0-6077 Cam berg
Tel: (06434) 231
TELEX: 484426
Kontron Elektronik GmbH
Breslauerstrasse 2
8057 Eching B
0-8000.Munich
Tel: (89) 319.011
TELEX: 522122
Neye Enatechnik GmbH
Schillerstrasse 14
0-2085 Quickborn-Hamburg
Tel: (04106) 6121
TELEX: 02-13590
GREECE
. American Technical Enterprises
P.O. Box 156
Athens
Tel: 30-1-8811271
30-1-8219470
HONG KONG
Schmidt & Co.
28/F Wing on Center
Connaught Road
Hong Kong
Tel: 5-455-644
TELEX: 74766 Schmc Hx
INDIA
Micronic Devices
104/109C, Nirmal Industrial Estate
Sion (E)
Bombay 400022, India
Tel: 486-170
TELEX: 011-5947 MOEV IN
ISRAEL
Eastronics Ltd.'
11 Rozanis Street
P.O. Box 39300
Tel Aviv 61390'
Tel: 475151
TELEX: 33638
Ryoyo Electric Corp.
Konwa Bldg.
1-12-22, Tsukiji, l-Chome
Chuo-Ku, Tokyo 104
Tel: (03) 543-7711
Tokyo Electron Ltd.
No.1 Higashikata-Machi
Midori-Ku, Yokohama 226
Tel: (045) 471-8811
TELEX: 781-4473
KOREA
Koram Digital
Room 411 Ahil Bldg.
49-4 2-GA Hoehyun-Oong
Chung-Ku Seoul
Tel: 23-8123
TELEX: K23542 HANSINT
Leewood International, Inc.
C.P.O. Box 4046
112-25, Sokong-Oong
Chung-Ku, Seoul 100
Tel: 28-5927
CABLE: ''LEEWOO~'' Seoul
NETHERLANDS
Inelco Nether. Compo Sys. BV
Turfstekerstraat 63
Aalsmeer 1431 0
Tel: (2977) 28855
TELEX: 14693
Koning & Hartman
Koperwerf 30
2544 EN Den Haag
Tel: (70) 210.101
TELEX: 31528
NEW ZEALAND
W. K. McLean Ltd.
P.O. Box 18-065
Glenn Innes, Auckland, 6
Tel: 587-037
TELEX: NZ2763 KOSFY
NORWAY
Nordisk Elektronik (Norge) A/S
Postoffice Box 122
Smedsvingen 4
1364 Hvalstad
Tel: 02786210
TELEX: 17546
PORTUGAL
Oitram
Componentes E Electronica LOA
Av. Miguel Bombarda, 133
Lisboa 1
Tel: (19) 545313
TELEX: 14347 GESPIC
SPAIN
Interface
Av. Generalisimo 51 9'
E-Madrid 16
Tel: 4563151
ITT SESA
Miguel Angel 16
Madrid 10
Tel: (1) 4190957
TELEX: 27707/27461
SWEDEN
AB Gosta Backstrom
Box 12009
10221 Stockholm
Tel: (08) 541 080
TELEX: 10135
Nordisk Electronik AB
Box 27301
S-10254 Stockholm
Tel: (08) 635040
TELEX: 10547
SWITZERLAND
Industrade AG
Gemsenstrasse 2
Postcheck 80 - 21190
CH-8021 Zurich
Tel: (01) 60 22 30
TELEX: 56788
TAIWAN
Taiwan Automation Co.'
3d Floor #15, Section 4
Nanking East Road
Taipei
Tel: 771-0940
TELEX: 11942 TAIAUTO
TURKEY
Turkelek Electronics
Apapurk Boulevard 169
Ankara
Tel: 189483
UNITED KINGDOM
Com way Microsystems Ltd.
Market Street
68-Bracknell, Berkshire
Tel: (344) 51654
TELEX: 847201
G.E.C. Semiconductors Ltd.
East Lane
North Wembley
Middlesex HA9 7PP
Tel: (01) 904-9303/908-4111
TELEX: 28817
Jermyn Industries
Vestry Estate
Sevenoaks, Kent
Tel: (0732) 501.44
TELEX: 95142
Rapid Recall, Ltd.
6 Soho Mills Ind. Park
Wooburn Green
Bucks, Eng land
Tel: (6285) 24961
TELEX: 849439
Sintrom Electronics Ltd.'
Arkwright Road 2
Reading, Berkshire RG2 OLS
Tel: (0734) 85464
TELEX: 847395
VENEZUELA
SINGAPORE
General Engineers Associates
Blk 3, 1003-1008, 10th Floor
P.S.A. Multi-Storey Complex
Telok Blangah/Pasir Panjang
Singapore 5
Tel: 271-3163
TELEX: RS23987 GENERCO
Componentes y Circuitos
Electronicos TTLCA C.A.
Apartado 3223
Caracas 101
Tel: 718-100
TELEX: 21795 TELETIPOS
• Field Application Location
INTERNATIONAL SALES AND MARKETING OFFICES
INTEL@ MARKETING OFFICES
AUSTRALIA
GERMANY
ITALY
SWEDEN
Intel Australia
Suite 2, Level 15, North Point
100 Miller Street
North Sydney, NSW, 2060
Tel: 450-847
TELEX: AA 20097
Intel Semiconductor GmbH·
Seidlstrasse 27
8000 Muenchen 2
Tel: (089) 53 891
TELEX: 523 177
Intel Corporation Italia, S.p.A.
Corso Sempione 39
1·20145 Milano
Tel: 2/34.93287
TELEX: 311271
Intel Sweden A.B.·
Box 20092
Alpvagen 17
S·16120 Bromma
Tel: (08) 9853 90
TELEX: 12261
BELGIUM
Intel Corporation S.A.
Rue du Moulin a Papier 51
Boite 1
B·1160 Brussels
Tel: (02) 660 30 10
TELEX: 24814
Intel Semiconductor GmbH
Mainzer Strasse 75
6200 Wiesbaden 1
Tel: (06121) 700874
TELEX: 04186183
DENMARK
Intel Semiconductor GmbH
Wernerstrasse 67
P.O. Box 1460
7012 Fellbach
Tel: (0711) 580082
TELEX: 7254826
Intel Denmark A/S·
Lyngbyvej 32 2nd Floor
DK·2100 Copenhagen East
Tel: (01) 182000
TELEX: 19567
Intel Semiconductor GmbH
Hindenburgstrasse 28/29
3000 Hannover 1
Tel: (0511) 852051
TELEX: 923625
FINLAND
HONG KONG
Intel Scandinavia
Sentnerikuja 3
SF . 00400 Helsinki 40
Tel: (0) 558531
TELEX: 123 332
FRANCE
Intel Corporation, S.A.R.L.·
5 Place de la Balance
Silic 223
94528 Rungis Cedex
Tel: (01) 687 22 21
TELEX: 270475
Intel Trading Corporation
99·105 Des Voeux Rd., Central
18F, Unit B
Hong Kong
Tel: 5·450·847
TELEX: 63869
ISRAEL
Intel Semiconductor Ltd.·
P.O. Box 2404
Haifa
Tel: 972/4524261
TELEX: 92246511
JAPAN
SWITZERLAND
Intel Japan K.K.·
Flower Hill·Shinmachi East Bldg.
1·23·9, Shinmachi, Setagaya·ku
Tokyo 154
Tel: (03) 426·9261
TELEX: 781·28426
Intel Semiconductor A.G.
Forchstrasse 95
CH 8032 Zurich
Tel: 1·554502
TELEX: 557 89 ich ch
NETHERLANDS
UNITED KINGDOM
Intel Semiconductor B.V.
Cometongebouw
Westblaak 106
3012 Km Rotterdam
Tel: (10) 149122
TELEX: 22283
Intel Corporation (U.K.) Ltd.
Broadfield House
4 Between Towns Road
Cowley, Oxford OX4 3NB
Tel: (0865) 77 1431
TELEX: 837203
NORWAY
Intel Norway AlS
P.O. Box 92
Hvamveien 4
N·2013
Skjetten
Tel: (2) 742 420
TELEX: 18018
Intel Corporation (U.K.) Ltd.·
5 Hospital Street
Nantwich, Cheshire CW5 5RE
Tel: (0270) 62 65 60
TELEX: 38620
Intel Corporation (U.K.) Ltd.
Dorcan House
Eldine Drive
Swindon, Wiltshire SN3 3TU
Tel: (0793) 26101
TELEX: 444447 INT SWN
• Field Application Location
Intel
u.s. AND CANADIAN SERVICE OFFICES
CALIFORNIA
MARYLAND
PENNSYLVANIA
Intel Corp.
1601 Old Bayshore Hwy.
Suite 345
Burlingame 94010
Till: (415) 692-4762
TWX: 910-375-3310
Intel Corp.
7257 Parkway Drive
Hanover 21076
Tel: (301) 796-7500
TWX: 710-862-1944
Intel Corp.
275 Commerce Drive
200 Office Center
Suite 300
Fort Washington 19034
Tel: (215) 542-9444
TWX: 51D-651-2077
Intel Corp.
2000 E. 4th Street
Suite 100
Santa Ana 92705
Tel: (714) 835-9642
TWX: 910-595-1114
Intel Corp.
7670 Opportunity Road
San Diego 92111
Tel: (714) 268-3563
Intel Corp.
3375 Scott Blvd.
Santa Clara 95051
Tel: (406) 987-8086
Intel Corp.
15335 Morrison
Sherman Oaks 91403
Tel: (213) 986-9510
COLORADO
Intel Corp.
650 South Cherry
Suite 720
Denver, 80222
Tel: (303) 321-8086
TWX: 910-931-2289
FLORIDA
Intel Corp.
1001 N.W. 62nd Street
Suite 406
Ft. Lauderdale 33309
Tel: (305) 771-0600
TWX: 510-956-9407
ILLINOIS
Intel Corp.
2550 Golf Road
Suite 815
Rolling Meadows 60008
Tel: (312) 981-7230
TWX: 910-253-1825
KANSAS
Intel Corp.
9393 W. 110th Street
Suite 265
Overland Park 66210
Tel: (913) 642-8080
MASSACHUSETTS
Intel Corp.
27 Industrial Avenue
Chelmsford 01824
Tel: (617) 667-8126
TWX: 710-343-8333
MICHIGAN
Intel Corp.
26500 Northwestern Hwy.
Suite 401
Southfield 48075
Tel: (313) 353-0920
TWX: 810-244-4915
MINNESOTA
Intel Corp.
7401 Metro Blvd.
Suite 355
Edina 55435
Tel: (612) 835-8722
TWX: 910-576-2867
TEXAS
Intel Corp.
313 E. Anderson Lane
Suite 314
Austin 78752
Tel: (512) 454-3628
TWX: 910-874·1347
Intel Corp.
2925 L.B.J. Freeway
Suite 175
Dallas 75234
Tel: (214) 241-2820
TWX: 910-860-5617
Intel Corp.
6420 Richmond Avenue
Suite 280
Houston 77057
Tel: (713) 784-~3OO
TWX: 910-881-2490
VIRGINIA
MISSOURI
Intel Corp.
502 Earth City Plaza
Suite 121
Earth City 63045
Tel: (314) 291-1990
Intel Corp.
7700 Leesburg Pike
Suite 412
Falls Church 22043
Tel: (703) 734-9707
TWX: 710-931-0625
NEW JERSEY
WASHINGTON
Intel Corp.
2450 Lemoine Avenue
Ft. Lee 07024
Tel: (201) 947-6267
TWX: 710-991-8593
Intel Corp.
1603 116th Ave. N.E.
Suite 114
Bellevue 98005
Tel: (206) 232-7823
TWX: 910-443-3002
OHIO
Intel Corp.
Chagrin-Brainard Bldg. 11210
28001 Chagrin Blvd.
Cleveland 44122
Tel: (216) 464-2736
TWX: 810-427-9298
Intel Corp.
6500 Poe Avenue
Dayton 45414
Te I: (513) 890-5350
TWX: 810-450-2528
OREGON
Intel Corp.
10700 S.W. Beaverton-Hillsdale Hwy.
Bldg. 2, Suite 324
Beaverton 97005
Tel: (503) 641-8086
TWX: 910-467-8741
WISCONSIN
Intel Corp.
150 S. Sunnyslope Road
Suite 148
Brookfield 53005
Tel: (414) 784-9060
CANADA
Intel Corp.
50 Galaxy Blvd.
Unit 12
Rexdale, OntariO
M9W4Y5
Tel: (416) 675-2105
Telex: 069-83574
Intel Corp.
39 Hwy. 7, Bells Corners
Ottawa, Ontario
K2H 8R2
Tel: (613) 829-9714
Telex: 053-4115
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