MCS 8 Assembly Language Programming Manual Preliminary Edition Nov73

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INTEL CORP. 3065 Bowers Avenue, Santa Clara, California 95051 • (408) 246-7501

Assembly
Language Programming
Manual
MCST~8

PRELIMINARY EDITION

November 1973
©

Intel Corporation 1973

-- TABLE

OF CONTENTS --

8008 PROGRAMMING MANUAL

Page No.
1.0

INTRODUCTION

1-1

2.0

COMPUTER ORGANIZATION

2-1

2.1

THE CENTRAL PROCESSING UNIT

2-3

2.1.1 WORKING REGISTERS
2. 1 .2 THE STACK
2.1.3 ARITHMETIC AND LOGIC UNIT

2-3
2-5
2-7

MEMORY
COMPUTER PROGRAM REPRESENTATION IN MEMORY
MEMORY ADDRESSING

2-8
2-8
2-10

2.4.1
2 .4 .2
2.4.3
2.4.4
2.4.5

2-11
2-13
2-13
2-14

2.2
2.3
2.4

2.5

3.{)

DIRECT ADDRESSING
INDEXED ADDRESSING
INDIRECT ADDRESSING
IMMEDIATE ADDRESSING
SUBROUTINES AND USE OF THE STACK FOR
ADDRESSING

2-15

CONDITION BITS

2-18

2.5.1
2 .5 • 2
2 .5 . 3
2 •5 . 4

2-18
2-19
2-19
2-20

CARRY BIT
SIGN BIT
ZERO BIT
PARITY BIT

THE 8008 INSTRUCTION SET

3-1

3.1

ASSEMBLY LANG UAGE

3-1

3.1.1
3.1.2
3 • 1. 3
3.1.4
3 • 1 .5
3.1.6

3-1
3-4
3-5

HOW ASSEMBLY LANGUAGE IS USED
STATEMENT MNEMONICS
LABEL FIELD
CODE FIELD
OPERAND FIELD
COMMENT FIELD
i

3-7
3-7
3-15

Page No.

3.2

3.3

3.4
3.5

DATA STATEMENTS

3-15

3.2.1 TWO'S COMPLEMENT
3.2.2 DB DEFINE BYTE(S) OF DATA
3.2.3 DW DEFINE WORD (TWO BYTES) OF DATA
3.2.4 DS DEFINE STORAGE (BYTES)

3-16
3-20
3-21
3-22

SINGLE REGISTER INSTRUCTIONS

3-23

3.3.1
3.3.2

3-24
3-24

MOV INSTRUCTION
REGISTER OR MEMORY TO ACCUMULATOR INSTRUCTIONS

3-25
3-28

3.5.1 ADD ADD REGISTER OR MEMORY TO ACCUMULATOR
3.5.2 ADC ADD REGISTI:R OR MEMORY TO ACCUMULATOR

3-29

3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.6

INR INCREMENT REGISTER
DCR DECREMENT REGISTER

WITH CARRY
SUB SUBTRACT REGISTER OR MEMORY FROM
ACCUMULATOR
SBB SUBTRACT REGISTER OR MEMORY FROM
ACCUMULATOR WITH BORROW
ANA LOGICAL" AND" REGISTER OR MEMORY
WITH ACCUMULATOR
XRA EXCLUSIVE - OR REGISTER OR MEMORY WITH
ACCUMULATOR (ZERO ACCUMULATOR)
ORA LOGICAL" OR" REGISTER OR MEMORY WITH
ACCUMULATOR
CMP COMPARE REGISTER OR MEMORY WITH
ACCUMULATOR

3-31
3-32
3-34
3-36
3-37
3-40
3-41

ROTATE ACCUMULATOR INSTRUCTIONS

3-43

3.6.1
3.6.2
3.6.3
3.6.4

3-44
3-45
3-46
3-47

RLC
RRC
RAL
RAR

ROTATE ACCUMULATOR LEFT
ROTATE ACCUMULATOR RIGHT
ROTATE ACCUMULATOR LEFT THROUGH CARRY
ROTATE ACCUMULATOR RIGHT THROUGH CARRY

Page No.

3.7

IMMEDIATE INSTRUCTIONS

3-49

3.7.1 MVI MOVE IMMEDIATE DATA
3.7.2 ADI ADD IMMEDIATE TO ACCUMULATOR
3.7.3 ACI ADD IMMEDIATE TO ACCUMULATOR WITH CARRY
3.7.4 SUI SUBTRACT IMMEDIATE FROM ACCUMULATOR
3.7.5 SBI SUBTRACT IMMEDIATE FROM ACCUMULATOR

3-50
3-51
3-53
3-54

3.7.6
3.7.7
3.7.8
3.7.9
3.8

3.9

WITH BORROW
ANI AND IMMEDIATE WITH ACCUMULATOR
XRI EXCLUSIVE - OR IMMEDIATE WITH ACCUMULATOR
o RI OR IMMEDIATE WITH ACCUMULATOR
CPI COMPARE IMMEDIATE WITH ACCUMULATOR

3-55
3-57
3-58
3-59
3-60

JUMP INSTRUCTIONS

3-61

3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
3.8.8
3.8.9

CARRY
NO CARRY
ZERO
NOT ZERO
MINUS
POSITIVE
PARITY EVEN
PARITY ODD

3-62
3-64
3-65
3-65
3-66
3-66
3-67
3-67
3-68

CALL SUBROUTINE INSTRUCTIONS

3-70

3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9

3-71
3-72
3-72
3-73
3-74
3- 7

JMP
JC
INC
JZ
INZ
JM
JP
JPE
IPO

JUMP
JUMP
JUMP
JUMP
JUMP
JUMP
JUMP
JUMP
JUMP

IF
IF
IF
IF
IF
IF
IF
IF

CALL
CC CALL IF CARRY
CNC CALL IF NO CARRY
CZ CALL IF ZERO
CNZ CALL IF NOT ZERO
CM CALL IF MINUS
CP CALL IF PLUS
CPE CALL IF PARITY EVEN
CPO CALL IF PARITY ODD

iii

Page No.

3.10 RETURN FROM SUBROUTINE INSTRUCTIONS
3. 10. 1
3. 10. 2
3.10.3
3.10.4
3.10.5
3.10. 6
3.10.7
3.10.8
3.10.9

RET RETURN
RC RETURN IF CARRY
RNC RETURN IF NO CARRY
RZ RETURN IF ZERO
RNZ RETURN IF NOT ZERO
RM RETURN IF MINUS
RP RETURN IF PLUS
RPE RETURN IF PARITY EVEN
RPO RETURN IF PARITY ODD

3.11 RST INSTRUCTION
3.12 INPUT/OUTPUT INSTRUCTIONS

3-84
3-85

3-88
3-89

3.13 HLT HALT INSTRUCTION
3.14 PSEUDO - INSTRUCTIONS

4.0

,3;:::79
3-79
3-80
3-80
3-81
3-81
3-82
3-83
3-83

3-86
3-87

3 • 1 2. 1 IN INPUT
3.12.2 OUT OUTPUT

3.14.1
3.14.2
3.14.3
3.14.4
3.14.5
3.14.6

3-78

ORG ORIGIN
EQU EQUATE
SET
END END OF ASSEMBLY
IF AND ENDIF CONDITIONAL ASSEMBLY
MACRO AND ENDM MACRO DEFINITION

3-90
3-91
3-93
3-94
3-95 .
3-96

PROGRAMMING WITH MACROS

4-1

4.1
4.2

WHAT ARE MAC ROS?
MACRO TERMS AND USE

4-1
4-5

4.2.1
4.2.2
4.2.3
4.2.4

4-5
4-7
4-8
4-9

4.3

MACRO DEFINITION
MACRO REFERENCE OR CALL
MACRO EXPANSION
PARAMETER SUBSTITUTION

REASONS FOR USING MACROS

4-14

Page No.

4.4

USEFUL MACROS

4-15

4.4.1
4.4.2
4.4.3

4-15
4-16·

4.4.4
4.4.5

5.0

4-17
4-20
4-20

PROGRAMMING TECHNIQUES

5-1

5.1
5.2
5.3
5.4

5-1
5-4

5.5

6.0

LOAD ADDRESS MACRO
LOAD INDIRECT MACRO (WITHOUT SUBROUTINES)
MEMORY INCREMENT SUBROUTINE AND LOAD
INDIRECT MACRO (WITH SUBROUTINE)
OTHER INDIRECT ADDRESSING MACROS
CREATE INDEXED ADDRESS MACRO

BRANCH TABLES PSEUDOSUBROUTINE
SOFTWARE MULTIPLY AND DIVIDE
MULTIBYTE ADDITION AND SUBTRACTION
SUBROUTINES
TRANSFERRING DATA TO SUBROUTINES

"A"
"B"
"C"
"D"
"E"

5-13
5-15

6-1

INTERRUPTS

APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX

5-9

INSTRUCTION SUMMARY
INSTRUCTION MACHINE CODES
INSTRUCTION EXECUTION TIMES
ASCII TABLE
BINARY-DECIMAL-HEXADECIMAL CONVERSION
TABLES

A-I
B-1
C-l

D-l

E-l

-- TERMS --

DESCRIPTION

TERMS
Address

A 14 bit number assigned to a memory location corresponding to its sequent~al position.

Bit

The smallest unit of information which can be repres ented. (A bit may be in one of two states, o· or I).

Byte

A group of 8 contiguous bits occupying a single memory

location.
Console

The INTELLEC 8 front panel, containing switches and
indicators that allow a user to operate the computer
and monitor program execution.

Instruction

The smallest single operation that the computer can
be directed to execute.

Obj ect Program

A program which can be loaded directly into the computer's
memory and which requires no alteration before execution.
An object program is usually on paper tape, and is produced by assembling (or compiling) a source program.
Instructions are represented by binary machine code in
an object program.

Program

A sequence of instructions which, taken as a group,
allow the computer to accomplish a desired task.

Source Program

A program which is readable by a programmer but which
must be transformed into object program format before it
can be loaded into the computer and executed. Instructions in an assembly language source program are represented by their assembly language mnemonic.

System Program

A program written to help in the process of creating
user programs.

User Program

A program written by the user to make the computer
perform any desired task.

TERMS

Word

A group of 16 contiguous bits occupying two
successive memory locations. (2 bytes).

nnnnB

nnnn represents a number in binary format.

nnnnD

nnnn represents a number in decimal format.

nnnnO

nnnn represents a number in octal format.

nnnnQ

nnnn represents a number in octal format.

ijklH

ijkl represents a number in hexadecimal format.

1 •a

INTRODUCTION

This manual has been written to help a design engineer program the INTEL
8008 microcomputer in assembly language, and to show why it is both economical and practical to do so. Accordingly this manual assumes that the
reader has a good understanding of logic, but is completely unfamiliar with
programming concepts.
For those readers who do understand programming concepts, several features of
the INTEL 8008 microcomputer are described below. They include:

•

8-Bit parallel CPU on a single chip.

•

48 instructions, including extensive memory reference
and jump on condition capability.

•

Direct addres sing for 16,384 bytes of memory •

•

Seven 8-bit registers, and a seven 14-bit re;ister stack.

INTEL 8008 microcomputer users will have widely differing programming needs.
Some users may wish to write a few short programs, while other users may have
extensive programming requirements.
For the user with limited programming needs, three system programs resident
on the INTELLEC 8 are provided; they are an Editor, an Assembler, and a System
Monitor. Use of the INTELLEC 8 and its three system programs is described
in the INTELLEC 8 Operator's Manual.
For the user with extensive programming needs, cross assemblers are available
which allow programs to be generated on any computer having a FORTRAN compiler whose word size is 32 bits or greater, limiting INTELLEC 8 use to final
checkout of programs only.
Whether a user's programming needs are limited or extensive, this manual
describes how to wtite efficient assembly language programs that may be
assembled either on the INTELLEC 8, or using a cross assembler.
The experienced programmer should note that the assembly language has a
macro capability which allows users to tailor the assembly language to
individual needs I yet still generate object programs which are compatible.
with any 8008 system. The value of this feature will qu1ckly become apparent
to the inexperienced programmer.

1-1

2. a

COMPUTER ORGANIZATION

This section provides the programmer with a functional overview of the
INTELLEC 8 computer. Information is presented in this section at a level
that provides a programmer with necessary background in order to write
efficient programs.
Functionally the computer can be divided into the following three blocks,
a s ill u stra ted in Figure 2 -1 :
•
•
•

Central Processing Unit
Memory
Input/Output and Output Modules

To the programmer, the computer is better represented a s consisting of the
following parts:
( 1) Seven working registers in which all data operations actually occur,
and which may therefore be visualized as a conduit through which
all data must flow. The seven working registers form part of the
Central Processing Unit.
(2) A stack, which is a device used to facilitate execution of subroutines I
as described later in this section. The stack forms part of the Central
Processing Unit.
(3) An arithmetic and logic unit which executes instructions and forms part
of the Central Processing Unit.
( 4) Memory, which is a pa ssive depository of data and instructions, and
must be addressed, byte by byte, in order to access stored information.
(5) Input/Output, which is the interface between a program and the real,
outside world.
The rest of Section 2 explains how the functional blocks of the 8008 computer
as illustrated in Figure 2-1 support its programming capabilities.

2-1

f'''-oH

r-- . - --I
I

8 Re~: 5 rl!!'''-$
l~

b~
.. ~
DI -

sto..c K
~,..; ~11V\<.L. t-i ~
4-l"'\d
a.A

I t!)~
~

to.

r .. l:-e,.",,,.

• ~

ll ...

te::

QI6 ,~

t--r
,

1
h~.~~e ..

,:.

~
'-___ -1

J:tl PUT /0 VtYvT
...,ot:lvL.~ S

Pe'l .. ; ~f'
; S t r -r_:,,__
. l\~ "ish;;.,. E;
~.C> .<;:~,
\e~, IS·t.Ql' L
'.e~

...,....

n.~ k.,.....u. ~ ~v...lI ~~~~
A ~

<" ..

-I

fJ r

~ ~J--- ~A-''*' ~

~w (Nrl'~,)~ ~-IV~~~_~~~'

2.1

THE CENTRAL PROCESSING UNIT

The entire 8008 Central Processing Unit is constructed on one LSI chip.
It consists of seven working registers, a seven register stack, and logic
to enable the INTELLEC 8 instruction set.
Conceptually, the 8008 is a multi-bus machine. Data transfers within the
CPU take place via an internal data bus. Data transfers between CPU and
memory occur via separate data-from-memory and data-to-memory buses.
Separate data input and output buses provide for communication between
CPU and peripheral devices.

2.1.1

WORKING REGISTERS

The 8008 provides the programmer with an accumulator and six additional "scratchpad" registers. The special significance of the accumulator is
that it is accessed by nearly all arithmetic and logical instructions, wherea s
only a limited number of data operations can involve the scratchpad registers.
The seven working registers are numbered and referenced via the integers
0, 1, 2, 3, 4, 5, 6; by convention working registers may also be accessed
via the letters A {for the accumulator}, B, C, D, E, Hand L. The Hand L
registers have special significance in that they are used to store memory
addresses, as described in Section 2.4. ] .
While in theory working registers could be used by the programmer in any way,
certain types of use either lend themselves to efficient programming, or are
forced on the programmer by the design of the computer. The following working
register assignments are recommended:

2-3

Most mathematical or logical operations act on,
and change the contents of this register. Use
register A as the destination for data operations,
never to save or store data.

Registers B, C, D, and E

Use these registers to transfer data between
program modules, and to store intermediate answers
during extended computations.

Registers Hand L

Use only for addres sing.

For the novice programmer, the above working register assignments will not yet
be meaningful, but the rationale for having such assignments will become clear
after examining the programming examples of Sections 3 and 4.

2-4

2.1. 2

THE STACK

The stack consists of seven 14 -bit registers used to hold memory addresses.
The concept of memory addresses is described in Section 2.2, but briefly stated,
memory can be visualized as a sequence of bytes (8 bit data units) numbered
sequentially from a to the highest memory byte present. The address of a memory
byte is the same a s its sequential number in memory. Having 14 bits, a stack
register can address up to 16,384 bytes of memory. (Addresses run from a to
11111111111111 B = 3FFFH = 16,383D, providing 16,384 memory addresses),
Stack operations consist of writing an address to the stack, and reading an
address from the stack. In order to understand these operations, it may be
helpful to visualalize the stack as seven registers on the surface of a cylinder,
as shown below:
...--- pOinter

a and b represent any
two memory addresses.
There is no top or bottom to the stack. Every stack register is adjacent to
two other stack registers. The 8008 keeps a pointer to the next stack register
available.
Writing an Address to the Stack:
To perform a stack write operation;
( 1)

The address is written into the register indicated by the pointer.

( 2)

The pointer is advanced to the next sequential register.

Any register may be used to hold the first address written to the stack. More
than seven addresses may be written to the stack; however, this will cause a
corresponding number of previously stored addresses to be overwritten und lost.
This is illustrated in Figure 2-2.

2-5

After 7 writes

After 6 writes

After 8. writes

die

fig

....

h represent any 8 memory addresses.
represents the stack pointer.

FIGURE 2-2.

Stack Write Operations.

Storing the 8th addres s (h) overwrites the first address stored (a).
Reading an address from the stack:
To perform a stack read operation;
(1 )

The pOinter is backed up one register.

(2)

The memory address indicated by the pointer is read.

The address read remains in the stack undisturbed. Thus if 8 addresses are
written to the stack and then three reads are performed, the stack wi!! appear
as in Figure 2-3.
I

2-6

First Read:
Address h is read

Second Read:
Address g is read

Third Read:
Address f is read

d,e

f,g

...

h represent any 7 memory addresses.
represent the stack pointer.

FIGURE 2-3.
Stack Read Operations.

The stack is zeroed when power is first applied to the 8008 or after a RESET
operation has occurred; thus if a stack read is performed from a stack register
which has not been written, a memory address of 0 will be read.
Section 2.4.5 describes how the stack is used by programs.

2 • 1 .3

ARITHMETIC AND LOGIC UNIT

The arithmetic and logic unit ALU of the 8008 computer provides the logic
for executing instructions. The representation of the ALU in Figure 2-115
sufficient for the programmer, who need know nothing about the ALU in order
to program the 8008.

2-7

2.2

MEMORY

The 8008 can be used with read only memory, programmable read only memory
and read/write memory. A program can cuase data to be read from any type of
memory ,but can only cause data to be written into read/write memory.
The programmer visualizes memory as a sequence of bytes, each of which may
store 8 bits (two hexadecimal digits). Up to 16,384 bytes of memory may be
present, and an individual memory byte is addressed by its sequential number,
between 0 and 16,383. The hexadecimal degits stored in a memory byte may
represent the encoded form of an instruction, or it may be data, as described
in Section 3.2.
2.3

COMPUTER PROGRAM REPRESENTATION IN MEMORY

A computer program consists of a sequence of instructions. Each instruction
enables an elementary operation such a s the movement of a data byte, an
arithmetic or logical operation on a data byte, or a change in instruction
execution sequence. Instructions are described individually in Section 3.
A program will be stored in memory as a sequence of hexadecimal digits which
represent the instructions of the program. The memory address of the next
instruction to be executed is recorded in a 14-bit register called the Program
Counter and thus it is possible to track a program as it is, being executed. Just
before each instruction is executed, the program counter is advunced to the address
of the next sequential instruction. Program execution proceeds sequentially
unless a transfer-of-control instruction (jump or call) is executed, which causes
the program counter to be set to a specified address. Execution then continues
sequentially from this new address in memory.
Upon examining the contents of a memory byte, there is no way of telling
whether- the byte contains an encoded instruction or data. For example, the
hexadecimal code lAR has been arbitrarily selected to encode the instruction
RAR ( rotate the contents of the accumulator right through carry); thus, the
value lAR stored in a memory byte could either represent the instruction RAR
.
'
. or It could represent the data value lAR. It is up to the logic of a program to
insure that data is not misinterpreted as a instruction code, but this is simply
done as follows:

2-8

Every program has a starting memory address, which is the memory address of
the byte holding the first instruction to be executed. Before the first instruction
is executed, the program counter will automatically be advanced to address the
next instruction to be executed, and this procedure will be repeated for every
instruction in the program. 8008 instructions may require I, 2, or 3 bytes to
encode an instruction; in each case the program counter is automatically advanced
to the start of the next instruction, as illustrated in Figure 2-4.
Memory
Address
0212
0213
0214
0215
0216
0217
0218
0219
021A
021B
021C
021D
021E
021F
0220
0221

Instruction
Number

}

I
I}
l

Program Counter
Contents

0213
0215

2
3

0216
0219

4
5

021B

021C
021F

8
9
10

Figure 2-4

0220
0221
0222

Automatic Advance of the Program Counter
as Instructions are Executed

In order to avoid errors, the programmer must be sure that a data byte does not
follow an instruction when another instnlctian is expected. Referring to
Figure 2-4, an instruction is expected in byte 021FH, since instruction 8 is
to be executed after instruction 7. If byte 021 FH held data, the program would
not execute correctly. Therefore, when writing a program, do not store data
in between adjacent instructions that are to be executed consecutively.
NOTE: Ita program stores data into a location, that location should not
normally appear among any program instructions. This is because user programs are normally executed from read-only memory, into which data cannot
be stored.

2-9

A class of instructions (referred to as transfer of control instructions) cause
program execution to branch to an instruction that may be anywhere in memory.
The memory address specified by the transfer of control instruction must be the
address of another instruction; if it is the address of a memory byte holding
data, the program will not execute correctly. For example, referring to Figure 2-4,
say instruction 4 specifies a jump to memory byte 021FH, and say instructions
5, 6 and 7 are replaced by data; then following execution of instruction 4, the
program would execute correctly. Buf if, in error, instruction 4 specifies
a jump to memory byte 021 EH, an error would result, since this byte now holds
data. Even if instructions 5, 6 and 7 were not replaced by data, a jump to
memory byte 02IEH would cause an error, since this is not the first byte of the
instruction.
Upon reading Section 3, you will see that it is easy to avoid writing an assembly
language program with jump instructions that have erroneous memory addresses.
Information on this subj ect is given rather to help the programmer who is debugging
programs by entering hexadecimal codes directly into memory.

2.4

MEMORY ADDRESSING

Each byte in memory has an address which is a 14 bit number corresponding to its
sequential location. Thus the range of addresses is 0 to 16,383 (the highest number
which can be represented in 14 bits). The address of a memory location can Oe
held in memory in two consecutive 8 bit bytes; normally the least significant
8 bits of the address are held in one byte, and the most significant 6 bits of the
address are held in the next byte.
By now it will have become apparent that addressing specific memory bytes
constitutes an important part of any computer program; there are a number of
ways in which this can be done, as described in the following subsections.

2-10

2.4.1

DIRECT ADDRESSING

With direct addressing, as the name implies, an instruction provides an
exact memory address. The following instruction provides an example of
direct addressing:
"Load the contents of memory byte I F2AH into the accumulator ( Register A )"
1 F2AH is a direct address. Direct addressing is the principal means used by
the INTELLEC 8 to address memory, and the Hand L registers are used to
hold the direct memory address. For example, the direct addressing instruction
described above might be illustrated as follows:

Arbitrary
Memory
Address
any

IF29
IF2A
IF2B

Memory

Reoisters

A
B

instruction being
executed

D
E
H

2 A

The instruction encoded by the digits C7H is being executed, and is, in fact,
interpreted to mean:
Load register A ( the accumulator) with the contents of the memory byte whose
address is provided by the Hand L registers.
~

and call instructions on the 8008 provide a special case of direct addressing where the direct address is stored in the two consecutive memory bytes
following the instruction code byte. The low order eight bits of the address are
stored in the first (lower addressed) byte I while the high order six bits of the
address are stored in the second (higher addressed) byte.
I

Thus the instruction:
"Jump to memory location IF22"
would appear in memory as follows:

2-11

Arbitrary Memory
Address
any

any + 1
any + 2

Memory

IF,
44

~----I

IF20
IF21
IF22
IF23

2-12

------- Jump

instruction code

-Address to which jump is

directed

2.4.2

INDEXED ADDRESSING

An indexed address is computed as the sum of two numbers, a base address
and an index. For example, a table may be one hundred bytes long, in which
case the address of any byte is computed as the address of the table origin
( base address), plus the displacement of the byte from the table origin
( index). On the 8008 the Hand L registers will commonly be used
to hold the base address, while either one or two of the registers B,C,D
and E ( but not A ) will hold the index. If one index register is used, tables
cannot be longer than 256 bytes. If two registers are used to store the index
portion of the address, tables can be as large as memory. Figure 2-5 illustrates
the concept of indexed addressing.

Arbitrary
Memory
Address
2130
2131
2132
2133
2134

Req:i sters

A
B

2220
2221
2222
2223

Figure 2-5

D Index
E

21
30

~} Base

Address

Addressed Byte

Indexed Address, Formed by Hand L Register
(Base) Plus D Register ( Arbitrarily Selected as
Index Register)

Indexed addressing can easily be accomplished on the 8008 by writing a sequence
of instructions referred to as a Macro. (See Section 4.4).
2.4.3

INDIRECT ADDRESSING

An indirect address specifies where in memory a direct address is to be
found. The concept of indirect addressing as applied to the 8008 is
illustrated in Figure 2-6.
I

2-13

Arbitrary
Memory
Address
Memory
any

lCll
lC12
lC13
lC14

13
lC
,
,

Reqisters

OF02
OF03
OF04
OFOS

Instruction being executed

I
I
I

!~l

~I--

OF
03

C
D
E
H
L

This memory byte being referenced

Figure 2-6 Indirect Addressing
In Figure 2-6, the instruction being executed specifies that the address of the
memory byte to be referenced is stored in two memory bytes pOinted to by the
Hand L registers. The Hand L registers contain the memory address OF03H;
therefore the address of the memory byte to be referenced is to be found in
memory bytes OF03H and OF04H. These two memory bytes hold the address
lCI3H, which becomes the referenced memory location. Note that the address
is stored with the least significant 8 bits in the lower addressed memory location
(OF03H) ,while the most significant 6 bits are stored in the higher addressed
location (OF04H). This is the usual method for storing addresses in the 8008.
Indirect addressing on the 8008 can also be accomplished by writing a macro
a s described in Section 4.4.
2.4.4

IMMEDIATE ADDRESSING

An immediate instruction is one that provides its own data. The following is an
example of immediate addressing:
Load register A (the accumulator) with the value 2 EH.
The above instruction would be coded in memory as follows:

2-14

Memory

.......

Load accumulator immediate
Value to be loaded into accumulator

Immediate instructions do not reference memory; rather they store data in the
memory byte directly following the instruction code byte.

2.4.5

SUBROUTINES AND USE OF THE STACK FOR ADDRESSING

Before understanding the purpose or effectiveness of the stack
to understand the concept of a subroutine.

it is necessary

Consider a frequently used operation such as addition. The INTELLEC 8 provides instructions to add one byte of data to another byte of data, but what
if you wish to add numbers outside the range of 0 to 255 (the range of one
data byte)? Such addition will require a number of instructions to be executed in sequence. It is quite possible that this addition routine may be
required many times within one program; to repeat the identical code every
time it is needed is possible, but very wasteful of memory:

,.
I

I Program
'I

-&!Qition
j

•

I Program

Addition

1 Program

AddItion
I

etc

2-15

A more efficient means of accessing the addition routine would be to store
it once, and find a way of accessing it when needed:

Program
Program

I
I~

I
-.,............

... 'Mdition

Program

I
I

A frequently accessed routine such a s the addition above is called a subroutine, and the 8008 provides instructions that call subroutines and return
from subroutines.
When a subroutine is executed, the sequence of events may be depicted
as follows:
Main Pro ram

Call instruction __________
~Subroutine

~~------

The arrows indicate the execution s.equence.
When the "Call" instruction Is executed, the address of the "next" instruction is written to the stack. (See Section 2.1.2), and the subroutine is executed. The last executed instruction of a subroutine will always be a special
"Return Instruction", which reads an address from the stack into the program
counter, and thus causes program execution to continue at the" Next" instruc-:tion as illustrated on the next page.

2-16

Memory
Address
OC02
OC03
OC04
OCOS
OC06

Write address of next instruction OC06H to the stack.
Instruction

CALL SUBROUTINE
02

Branch to
subroutines
starting at
OF02H

NEXT INSTRUCTION

oroo
OrOl
Or02
OF03

OF4E
OF4F

FIRST SUBROUTINE INSTRUCTION _...----4-.....1
Return to
next instruction
Body of subroutine

RETURN

2-]7

READ return address

( OC06H ) from stack

Since the stack provides seven registers, subroutines may be nested up to
seven deep; for example, the addition subroutine could itself call some other
subroutine, and so one. An examination of the sequence of write and read
stack operations will show that the return path will always be identical to the
call path, even if the same subroutine is called at more than one level; however, an attempt to nest subroutines to a depth of more than 7 will cause the
program to fail, since some addresses will have been overwritten.

2.5

CONDITION BITS

To make programming ea sier, four condition ( or statu s) bits are provided by
the 8008 to reflect the results of data operations. The descriptions
of individual instructions in Section 3 specify which condition bits are
affected by the execution of the instruction, and whether the execution of the
instruction is dependent in any way on prior status of condition bits.
In the following discussion of condition bits, a bit is "set" to I, and
reset" to O.
II

2 . 5. 1

CARRY BIT

Certain data operations can cause un overflow out of the high order 7 - bit.
For example addition of two numbers euch of which occupies one byte can
give rise to an answer that does not fit in one byte:
I

76543210
10101110
01110100

+ AE

74
122

Bit No.

00100010

Carry == 1
An operation that results in a carry out of bit 7 will set the carry bit.
An operation that could have resulted in a carry out of bit 7 but did not will

2-18

reset the carry bit.
NOTE: The 8008 subtract and compare operations (SUB, SBB SUI, SBI, CMP,
CMI)" are exceptions to the above rules. See the appropriate sections for details.
I

2.5.2

SIGN BIT

As described in Section 3.2.1, it is possible to treat a byte of data as having
the numerical range -128 10 to +127 10 , In this case by convention the 7 bit
will always represent the sign of the number; that is, if the 7 bit is 1, the
number is in the range -12810 to -1. If bit 7 is 0, the number is in the range
o to +127 10 ,
At the conclusion of certain instructions (as specified in the instruction description sections of Section 3), the sign bit will be set to the condition of the answer
7 bit in order to reflect the sign of the answer.

2.5.3

ZERO BIT

This condition bit is set if the answer generated by the execution of certain instructions leaves a zero result in a register. The zero bit is reset if the result
is not zero.
A result that has an overflow but a zero answer byte, as illustrated below, will
alos set the zero bit:

Overflow out
of bit 7.

76543210
10100111 +
01011001
00000000

Zero Answer
Zero bit set to 1.

2-19

Bit Number

2.5.4

PARITY BIT

In order to check that a data transfer operation occurred accurately, byte
"parity" is checked. The number of I bits in a byte are counted, and if the
total is odd, "odd" parity is flagged; if the total is even, "even" parity
is flagged.
The parity bit is set to I for even parity, and is set to 0 for odd parity.

2-20

3.0

THE 8008 INSTRUCTION SET

This section describes the 8008 assembly language instruction set.
For the reader who understands assembly language programming, Appendix
"A" provides a complete summary of the 8008 instructions.
For the reader who is not completely familiar with assembly language, Section
3 describes individual instructions with examples and machine code equivalents.

3.1

ASSEMBLY LANGUAGE

3.1. 1

HOW ASSEMBLY LANGUAGE IS USED

Upon examining the contents of computer memory a program would appear as
a sequence of hexadecimal digits which are interpreted by the CPU as
instruction codes, addresses or data. It is possible to write a program as
a sequence of digits ( just as they appear in memory), but that is slow and
expensive. For example, many instructions reference memory to address
either a data byte or another instruction:
I

Memory Addres s
1432
1433
1434
1435
1436

11
2

14C3
14C4
14CS
l4C6

36
F8

3-1

Assuming the registers Hand L contain 14H and C3H respectively, the program
operates as foHows:
Byte 1432 specifies that the accumulator is to be loaded with the contents of
byte 14C 3.
Bytes 1433 through 1435 specify that execution is to continue with the instruction starting at byte l4C4.
Bytes 14C4 and 14C5 specify that the L register is to be loaded with the
number "36" H.
Byte 14C6 specifies that the contents of the accumulator are to be stored in
byte 1436.
Now suppose that an error discovered in the program logic necessitates
placing an extra instruction after byte 1432. Program code would have to
change as follows:

Memory Address

Old Code

1432
1433
1434
1435
1436
1437
14"C3
l4C4
14C5
14C6
14C7

C7
44
C4
14

E2
36
36
F8

New Code
C7
New Instruction
44
C5
14

E2
36
37
F8

Most instructions have been moved and as a result many must be changed to
reflect the new memory addresses of instructions or data. The potential
for making mistakes is very high and is aggravated by the complete unreadabilHy of the program.

3-2

Writing programs in assembly language is the first and most significant step
towards economical programming; it provides a readable notation for instructions, and separates the programmer from a need to know or specify absolute
memory addresses.
Assembly language programs are written as a sequence of instructions which
are converted to executable hexadecimal code by a special program called
an ASSEMBLER. Use of the INTELLEC 8 assembler is described in the
INTELLEC 8 Operator's Manual.

Assembly language
program written by
programmer

ASSEMBLER
PROGRAM

SOURCE PROGRAM

Executable hexadecimal machine
code

OBJECT PROGRAM

Figure 3-1
Assembler Program Converts Assembly Language Source Program
to Hexadecimal Object Program

As illustrated in Figure 3-1, the assembly language program generated by a
programmer is called a SOURCE PROGRAM. The assembler converts the
SOURCE PROGRAM into an equivalent OBJECT PROGRAM, which consists of a
sequence of hexadecimal codes that can be loaded into memory and executed.

3-3

For example:

Source Program

is converted by the
As sembler to

One Possible Version of
the Objectjrogram

NOW:

MOV
CPI
JZ

A,B
'C'
LER

Cl
3C43
687C3D

LER:

MOV

M,A

Now if a new instruction must be added, only one change is required. Even
the reader who is not yet familiar with assembly language will see how simple
the addition is:

NOW:

LER

A,B
MOV
(New instruction inserted here)
CPI
'C'
JZ
LER
MOV

M ,A

The assembler takes care of the fact that a new instruction will shift the rest of
the program in memory.

3.1. 2

STATEMENT MNEMONICS

Assembly language instructions must adhere to a fixed set of rules as described
in this section. An instruction has four separate and distinct parts or FIELDS.
Field 1 is the LABEL field. It is the instruction's label or name
to reference the instruction.

3-4

and it is used

Field 2 is the CODE field,
the instruction,

It defines the operation that is to be performed by

Field 3 is· the OPERAND field,
needed by the CODE field,

It provides either any addres s or data information

Field 4 is the COMMENT field, It is present for the programmer's convenience
and is ignored by the assembler ,. The programmer uses comment fields to
describe the operation and thus make the program more readable,
The assembler uses free fields; that is, any number of blanks may separate
fields,
Before describing each field in detail, here are some general examples:

Label

Code

Operand

Comment

HERE:

MVI

C,O

Load the C register with zero

THERE:

3AR

Create a one-byte data constant

LOOP:

ADD

Add contents of E register
to the accumulator
Rotate the accumulator left

RLC

3.1.3

LABEL FIELD

This is an optional field, which, if present, may be from I to 5 characters long,
The first character of. the label must be a letter of the alphabet or one of the
special characters @ (at sign) or? (question mark). A colon (:) must follow
the last character, (The operation codes, pseudo - instruction names, and
register names are specially defined within the assembler and may not be used
as labels. Operation codes are given in sections 3.2 - 3,13 and Appendix
A; pseudo - instructions are described in section 3,14.)

3-5

Here are some examples of valid label fields:
LABEL:

F14F:
@HERE:
?ZERO:
Here are some invalid labels:
123:

begins with a decimal digit

LABeL

does not cnd with a colon

ADD:

is an operation code

END:

is a pseudo - instruction

The following label has more than five characters; only the first five will be
recogniz ed:
INSTRUCTION:

will be read as INSTR:

Since labels serve a s instruction addresses, they cannot be duplicated.
example, the sequence:
HERE:

IMP

For

THERE

THERE:

MOV

C,D

THERE:

CALL

SUB

is ambiguous; the assembler cannot determine which THERE: address is to be
referenced by the IMP instruction.
One instruction may have more than one label, however.

3-6

The following sequence

is valid:
LOOPI:
LOOP2:

First label
MOV

C,D

JMP

LOOPI

JMP

LOOP2

Second label

Each IMP instruction will cause program control to be transferred to the same
MOV instruction.
3.1. 4

CODE FIELD

This field contains a code which identifies the machine operation (add, subtract,
jump, etc.) to be performed: hence the term operation code or op-code. The
instructions described in sections 3.2 - 3.13 are each Identift·3d by a mnemonic
label which must appear in the code field. For example, since the "jump" instruction is identified by the letters "JMP", these letters must appear in the
code field to identify the instruction as "jump".
There must be at least one space following the code field.
HERE:

JMP

Thus:

THERE

is legal, but:
HERE:

IMPTHERE

is illegal.
3.1. 5

OPERAND FIELD

This field contains information used in conjunction with the code field to define
precisely the operation to be performed by the instruction. Depending upon the
code field, the operand field may be absent or may consist of one item or two
items separated by a comma.
There are four types of information [(a) through (d) below] that may be requested
as items of an operand field, and the information may be specified in nine ways
[(1) through (9) below].

3-7

The nine ways of specifying information are as follows:
( I)

Hexad.ecimal data. Each hexadecimal number must be fonowed by the
letter 'H' and must begin with a numeric digit ( 0 - 9 ).
Example:

Operand

Label
MVI

HERE:

C,OBAH

Comment
Load register C with the
hexadecimal number BA

( 2)

Decimal data. Each decimal number may optionally be followed by the
letter 'D', or may stand alone.
Example:

Comment

Label

( 3)

E, 105

MVI

ABC:

Load register C with 105

Octal data. ,Each octal number must be followed by one of the letters
'0' or 'Q'.
Example:

Label
LABEL:

Operand
A, 720

MVI

3-8

Comment
Load the accumulator with
the octal number 72

( 4)

Binary data.

Each binary number must be followed by the letter 'B'.

Example:
Label

Code

Operand

NOW:

MVI

lOB

JUMP:

JMP

0010111011111010B

( 5)

Comment

11ll01l0B

Load register two ( the C
register) with OF6H
Jump to memory address
2EFA

The current program counter. This is specified as the character $' and
is equal to the address of the current instruction.
I

Example:

Label

Operand

GO:

JMP

$ + 6

The instruction above causes program control to be transferred to the
address 6 bytes beyond where the JMP instruction is loaded.
( 6) An ASCII constant. This is one or more ASCII characters enclosed in
Single quotes. Two successive single quotes must be used to represent
one single quote within an ASCII constant. Appendix D contains a list of
legal ASCII characters and their hexadecimal representations.
Example:

Label
CHAR:

Operand
MVI

E, '*'

3-9

Comment
Load the E r8Jister with the
eight bit ASCII representation
of an a steri sk

( 7) Labels that have been assigned a numeric value by the assembler. (See
section 3.16.2 for the equate procedure). The following equates are built
into the assembler and are therefore always active:
A
B

C
D

E
H
L
M

equated to 0 representing the accumulator
register B
" I
"
2
C
"
"
"
3
D
"
"
"
"
"
E
"
"
" 4
H
"
"
" 5
"
" 6
L
"
"
"
"
a memory reference
"
" 7
fI

Exam21e:
Suppose VALUE has been equated to the hexadecimal number
9FH. Then the following instructions all load the D register
with 9FH:
Label

°2erand

AI:

MVI
MVI
MVI

A2:

A3:

( 8)

D, VALUE
3,9FH
3, VALUE

Labels that appear in the label field of another instruction.
Exam2le:

Label

Code

°2erand

HERE:

JMP

THERE

THERE:

MVI

D,9FH

3-10

Comment
Jump to instruction at THERE:

(9)

Arithmetic and logical expressions involving data types (1) to (8)
above connected by the arithmetic operators + (addition), - (unary
minus and subtraction), * (multiplication), / (division), MOD
(modulo), the logical operators NOT, AND, OR, XOR, SHR, (shift
right), SHL (shift left), and left and right parentheses.

All operators treat their arguments as 16 bit quantities, and generate 16 bit quantities as their result. The programmer must insure that the result generated fits
the reqUirements of the operation being coded. . For example, the second operand
of an MVI instruction must be an 8 bit value.
Therefore the instruction:
MVI

H,NOT

is invalid, since NOT 0 produces the 16 bit hexadecimal number FFFF.
the instruction:
MVI

H, NOT

AND

However,

OFFH

is valid, since the most significant 8 bits of the result are insured to be 0,
and the result can therefore be represented in 8 bits.
The SHR and SHL operators are linear shifts which cause zeroes to be shifted
into the high order and low order bits, respectively, of their arguments.
NOTE: An instruction in parenthesis isa legal expression in an optional field.
Its value is the encoding of the instruction.
Examples:

Operand

Label
HERE:

MVI

H, HERE SHR 8

Arbitrary Memory Addres s
2EIA

The above instruction loads the hexadecimal number 2EH (l4-blt address of HERE
shifted right 8 bits) into the H register.

3-11

Operand
NEXT:

MVI

34 + 40H/2

The above instruction will load the value 34 + (64/2) = 34 + 32 = 66 into the D
register.

Operand
INS:

(ADD

The above instruction defines a byte of value 82H (the encoding. of ADD C instruction) at location INS:.
.

Operand

MVI

D, 34 + 40H/2

The above instruction will load the value 34 + (64/2) = 34 + 32 ~ 66 into the D
register.
Operators within an expression are evaluated in the following order:

1.
2.
3.
4.

Left and right parentheses
*,/, MOD, SHL, SHR
+, - (unary and binary)
NOT
5. AND
6. OR
XOR
Thus the instruction:
MVI

D, (34 + 40H) /2

will load the value
(34 + 64 ) /2 = 49 into the D register.
The operators MOD, SHL, SHR, NOT, AND, OR, and XOR must be separated
from their operands by at least one blank. Thus the instruction:
MVI

C, VALUE ANDOPH

is invalid.
Using some or all of the above nine data specifications, the following four types
of information may be requested:
(a) A register ( or code indicating memory reference) to serve as the source or
destination in a data operation - Methods I, 2, 3, 4, 7, or 9 may be used
to specify the register or memory reference, but the specification must
finally evaluate to one of the numbers 0 - 7 as follows:

B
C

3
4
5
6
7

H
L
Memory Reference

3-12

Example:
Label
INS1:
INS:Z:
INS3:

Code

Operand

MVI
MVI
.MVI

REG4, 2EH
4H, 2EH
8/2, 2EH

Assuming REG4 has been equated to 4, all the above instructions will load
the value 2EH into register 4.
(b) Immediate data, to be used directly as a data item.
Example:

Label

Code

HERE:

MVI

Operand
H, DATA

Oomment
Load the H register with
the value of DATA

Here are some examples of the form DATA could t(lke:
ADDR AND OFFH (where ADDR is a 14-bit address)
127

'.'
VALUE (where
VALUE has been equated
to a number)
.
.
3EH + 10 / ( 2 AND 2 )
(c) A 14 -bit address, or the label of another instruction in memory.

3-13

Example:

Operand

Label

JMP
JMP

HERE:

THERE
2EADH

Comment
rump to the instruction at THERE
Jump to addres s 2 EAD

(d) A number in a specific range, required by certain instructions.
The RST and IN instructions require a number in the range 0 - 7 •
Example:

Label

,Code
-

GOOD:

RST

lUB

Value of 7, valid

OK:

15 - OAH

Value of 5, valid

BAD:

RST

Operand

Comment

Value of 10, invalid instruction

The OUT instruction requires a number in the range 8 - 31 decimal.
Example:
Label

, Operand

GOOD:

OUT

20 + 11

Value 31 decimal, valid

BAD:

OUT

20 + 11 H

Value 37 decimal, invalid

3-14,

Comment

The INR and DCR instructions require a number in the range 1 - 6, specifying
one of registers B, C, D, E, H, or L.
Example:
Label

Operand

OK:

3.1. 6

Comment

INR

Increment register E

INR

110B

Decrement register L

COMMENT FIELD

The only rule governing this field is that it must being with a semi colon
(;)

HERE:

MVI

C, 0 ADH

; This Is a comment

A comment field may appear alone on a line:

Begin loop here

3.2

DATA STATEMENTS

This section describes ways in which data can be specified in and interpreted by a program. Any 8 bit byte contains one of the 256 possible combinations of zeros and ones. MY particular combination may be interpreted
in various ways. As previously mentioned, the code IAH may be interPreted
as a machine instruction ( Rotate Accumulator Right through Carry), as a
hexidecimal value lAH = 26D, or merely as the bit pattern 00011010

Arithmetic instructions assume that the data bytes upon which they operate are
in a special format called "two's complement", and the operations performed
on these bytes are called "two's complement arithmetic. "

3-15

3.2.1

TWO'S COMPLEMENT

When a byte is interpreted as a signed two's complement number, the low
order 7 bits supply the magnitude of the number, while the high order bit is
interpreted as the sign of the number ( 0 for positive numbers, 1 for negative) .
The range of positive numbers that can be represented in signed two's complement notation is, therefore, from 0 to 127:

00000000 B

00000001 B

126D ==

011111110 B

7EH

127D =

011111111

:::-

7FH

To change the sign of a number represented in two's complement, the following
rules are applied:
(a) Invert each bit of the number ( producing the so-called one's
complement) .
(b) Add one to the reSUlt, ignoring any carry out of the high order
bit position.
Example: Produce the two's complement representation of - lOD.
the rules above,

Following

+ laD = 0 a a 0 1 0 1 0
Invert each bit
Add one

1 1 1 1 01 0 I
1 1 1 1 aI 1 0

Therefore the two's complement representation of - IOD is F6H.
the sign bit is set indicating a negative number.)
I

(Note that

Example: What is the value of 86 H interpreted as a signed two'S complement
number? The high order bit is set, indicating that this is a negative
number. To obtain its value again invert each bit and add one.
I

3-16

86H
Invert each bit
Add one

1 0 0 0 0 110

011110018
011110108

Thus, the value of 86 H is - 7A H

= - 122

The range of negative numbers that ean be represented in
plement notation is from -I to -128.

- 2 =

1 III 111 1 8
111111108

=
=

FFH
FEH

=
=

10000001B
10000000B

81H
80H

-I

-127D
-128D

~gned

two's com-

To perform the subtraction IAH - OCH, the following operations are performed:
Take the two's complement of OCH

= F4H

Add the result to the minuend:
lAH = 0 0 0 1 1 0 1 0
F4H = 1 1 1 1 0 1 0 0
o0 0 0 1 1 1 0

+ (-OCH) -

= OEH

the correct answer

When a byte is interpreted as an unsigned two's complement number, its value
is considered positive and in the range 0 to 255 10 :

o0
o0

000 000 8
000 001 8

01111111 B
1 000 0 0 0 0 8

7FH
80H

111111 1 1 B

FFH

0
1

127D
128D

255D

OH
IH

Twois complement arithmetic is still valid. When performing an addition operation,
the earlY bit is set when the result is greater than 255D. When performing subtraction, the cafIY bit is reset when the result is positive. If the carry bit is
set, the result is negative and present in its two's complement form.

3-17

Example: Subtract 98D from 197D using unsigned two's complement arithmetic.

Overflow

197D =
-98D =
"1

1 1 0 0 0 1 0 1 = C5 H
1 0 0 1 1 1 1 0 = 9 EH
o 1 1 0 0 0 1 1 = 63H = 99D

Since the overflow out of bit 7=1, indicating that the answer is correct and
positive, the subtract operation will reset the carry bit.
Example:

Subtract 15D from 12 D using unsigned two's complement arithmetic.

l2D =
-lSD =
Overflow
.. 0

0 0 1 1 0 0 = OCH
1 1 1 1 0 0 0 1 = OFlH
1 1 1 1 1 1 0 1 = -3D

Since the overflow out of bit 7=0, indicating that the answer is negative and in
its two's complement form, the subtract operation will set the carry bit. (This
also indicates that a "borrow" occurred while subtracting multibyte numbers.
See Section S. 3) •
NOTE: The 8008 instructions which perform the subtraction operation are SUB,
SUI, SBB, SBI, CMP, and CM!. Although the same result will be obtained by
addition of a complemented number or subtraction of an un complemented
number, the resulting carry bit will be different.
Example:

If the result -3 is produced by performing an "ADD" operation on the
numbers +12D and -lSD, the carry bit will be reset; if the same
result is produced by performing a "SUB" operation on the numbers
+12D and +15D, the carry bit will be set. Both operations indicate
that the result is negative; the programmer must be aware which
operations set or reset the carry bit.

"ADD" +12D and -15D

"SUB" +lSD from +12D

+12D = o 0 001 100
+(-lSD) = 1 1 1 1 000 1
0] 1 1 1 1 1 1 0 1 = -3D
L.-causes carry to be reset

+12D = 0 0 0 0 1 1 0 0
- (+15 D) = 1 1 1 1 0 0 a 1
0]
1 1 1 1 1 1 0 1 = -3D
~auses carry to be set

WIN TWO'S COMPLEMENT?
Using two's complement notation for negative numbers, any subtraction problem
becomes a sequence of bit inversions and additions. Therefore, fewer circuits
need to be built to perform subtraction.
3-19

3.2.2

DB DEFINE BYTE (S) OF DATA

Format:
Label

Operand

HERE:

LIST

LIST is a Ust of either:
1) Arithmetic and logical expressions involving any of the arithmetic
and logical operators, which evaluate to eight-bit data quantities
2) Strings of ASCII characters enclosed in quotes
Description: The eight bit value of each expression, or the eight bit ASCII
representation of each character is stored in the next available byt(~ of memory
starting with the byte addressed by HERE:

Examples:

Instruction
HERE:
WORD I :
WORD 2
SIR:
MINUS:

Assembled Data (hex)
DB
DB
DB
DB
DB

OA3H
5 * 2, 2 FH - OAH
5ABCH SHR 8
lSTRINGSp1 1
- 03H

A3
OA25
5A
53545 2494E4 72 031
FD

Note: In the first example above, the hexadecimal value A3 must be written as
OA3 since hexadecimal numbers must start with a decimal digit. (See
Section 3. 1 .5) .

3-20

3.2.3

DW DEFINE WORD (TWO BYTES) OF DATA

Format:
Label

Operand
DW

HERE:

LIST

LIST is a list of expressions which evaluate to 16 bit data quantities.
Description: The least significant 8 bits of the expression are stored in the
lower addres s memory byte (HERE:), and the most significant 8" bits are stored
in the next higher addressed byte (HERE:+l). This reverse order of the high and
low address bytes is normally the case when storing addresses in memory. This
statement is usually used to create address constants for the transfer-of-control
instructions: thus LIST is usually a list of one or more statement labels appearing
elsewhere in the program.
Examples:
Assume CaMP addresses memory location 3BICH and FILL addresses memory
location 3EB4.

Instruction
ADDl:
ADD2:
ADD3:

Assembled Data (hex)
DW
DW
DW

CaMP
FILL
3COIH

3CAEH

IC3B
B43E
Ol3CAE3C

Note that in each case, the data are stored with the least significant 8 bits first.

3-21

3.2.4

QEFINE .§TORAGE ( BYTES)

Format:
Label

Code

HERE:

Operand
EXP

EXP is a single arithmetic or logica 1 expression.
Description: The value of EXP specifies the number of memory bytes to be
reserved for data storage. N:> data values are assembled into these bytes:
in particular the programmer should not assume that they will be zero, or any
other value. The next instruction will be assembled at memory location
HERE: + EXP ( HERE: + 10 or HERE: + 16 in the example below).

Examples:

HERE:

DS
DS

lOH

3-22

Reserve the next 10 bytes
Reserve the next 16 bytes

3.3

SINGLE REGISTER INSTRUCTIONS

This section describes the two instructions which involve a single register.
Instructions in this class occupy one byte as follows:

E ,G

4. . .___---JJO for IN R
1 for DCR

Loot
010

all

100
101
110

Note: REG

F 000

for
for
for
for
for
for

C
D
E
H

or 111

The general assembly language instruction format is:

Operand

Label
LABEL:

REG
I....-_ _ _ _ _ _~B/C/D/E/H/L

---:INR or DCR

I....-_ _ _ _ _ _ _ _

L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

3-23

Optional instruction label

3.3.1

INR

INCREMENT REGISTER

Format:
Label

Code

Operand

Description: The register specified by REG is incremented by one. REG
cannot evaluate to 000 or 111, implying that neither the accumulator nor any
memory location can be incremented by this instruction.
Condition bits affected: Zero, sign, parity
Example:

If register C contains 99H, the instruction:

INR

will cause register C to contain 9AR.

3.3.2

DCR

DECREMENT REGISTER

Format:
Label

Code
DCR

Operand
Rr:G

Description: The register specified by REGis decremented by one. REG
cannot evaluate to 000 or Ill, implying that neither the accumulator nor
any memory location can be deqremented by this instruction.

3-24

Condition bits affected: Zero
Example:

sign

parity

If register L contains zero, the instruction:

DCR

will cause register L to contain OFFH
(minus one in two's complement form)

3.4

MOV INSTRUCTION

This section describes the MOV instruction, which transfers data between registers or between memory and registers. This instruction occupies one byte.
Format:
Label

Code

Operand

MOV

-f
Tis

000
001
010
011
100
101
110
III

Note: DDD and SSS cannot both

for register A
for register B
for register C
for register D
for register E
for register H
for rp.qister L
for memory reference

III B.

Description: One byte of data is moved from the register specified by SRC ( the
source register) to the register specified by DST ( the destination register).
The data replaces the contents of the destination register; the source re-

3-25

gister remains unchanged. If a memory reference is specified ( SRC or DS'F
= IllB ) the data is fetched from or stored into the memory address contained in the Hand L registers. Register L contains the low-order eight
bits of the address and register H contains the high-order six bits of the
address.
I

Condition bits affected: none
Example 1:

Label

Operand
MOV

A,r:

Comment
Move contents of the E register
to the A register

MOV

D, D

Move contents of the D register
to the D register Ii. e. I this is
a null operation

Note: Any of the null operation instructions MOV X, X can also be specified as N
( no-operation) .
Example 2:
The following set of instruction will store the contents of the accumulator
at memory location 2BE9H.

Label

Code

Operand

START:

MVI
MVI
MOV

H, 2BH
L, OE9H
M,A

3-26

Comment
H = high order address byte
L = low order address byte
Move accumulator to memory

Example 3:
The following set of instructions will store the D register at memory location
FINAL:, wherever that location happens to be in memory.

Operand

Label
START:

MVI
MVI
MOV

H FINAL SHR 8
L, FINAL AND OFFH
M,D
I

Comment
H = high order byte
L = low order byte
Move D to memory
addressed by Hand L

The first two instructions in the example above are so commonly used that
they may be specified by the single macro instruction:
START:

LXI

H,FINAL

as described in Section 4.2.1.

3-27

3.5

This section describes the instructions which operate on the accumulator
u sing a byte fetched from another regi ster or memory. In struction s in this
class occupy one byte as follows:

I
000
001
010
011
100
101
110
111

for
for
for
for
for
for
for
for

ADD
ADC

1I 0

I~ I
t 1
P
I

SUB
SBB

ANA
XRA
ORA

CMP

000
001
010
011
100
101
110
111

for
for
for
for
for
for
for
for

When a memory reference is specified, the byte of data is fetched from the
memory location addressed by registers Hand L.
The general assembly language instruction format is:

3-28

A
B

C
D
l~

H
L

Operand

Label

REG

LABEL:

tL..___A, B, C, 0, E, H, L, or M
ADC; SUB, SBB, ANA, XRA, ORA, or CMP
'--_ _ _ _ _ _ _ _ _ _O.ptionalinstruction label

3.5.1

ADD

ADD REGISTER OR !v1EMORY TO ACCUMULATOR

Format:
Operand

Code

REG

Description: The byte in the register specified by REG, or the memory location addressed by Hand L ( if REG=111B) is added to the contents of
the accumulator using two's complement arithmetic. The result is kept
in the accumulator; the byte in REG is unchanged.
I

If there is a carry out of the high-order bit position, the carry bit is set.

The zero bit is set if the result is zero.
The parity bit is set if the result contains an even number of ones ( even
parity) .
The sign bit is set to the most significant bit of the result.
Condition bits affected: Carry, sign, zero, parity

3-29

Example 1:

Label

Operand

Assembled Data

ADl:

MVI

D, 2FR

IE2F

AD2:

MVI

A, 6CR

066C

ADD

The instructions at ADI: and AD2:
load the D register with 2FR a.td the
accumulator with 6CR, respectively. The ADD instruction performs the
addition as follows:
2ER
6CH
9AR

=
=
=

0 0 1 0 1 I 1 0
OIl 0 1 1 0 0
1 0 0 1 1 0 1 0

The zero and carry bits are reset; the parity and sign bits are set. The
accumulator now contains 9AR.

Example 2:

The instruction:
ADD

will double the accumulator.

3-30

3.5.2

ADC

,
ADD REGISTER OR MEMORY TO ACCUMULATOR WITH CARRY

Fonnat:
Operand

Label

0, I

RI E

Description: The byte in the register specified by REG, or the memory location, addressed by Hand L (if REG = 1118) plus the contents of the
carry bit is added to the contents of the accumulator. The result is kept
in the accumulator; the byte in REG is unchanged.
The carry bit is set if there is a carry out of the high-Qrder bit position.
The zero bit is set if the result is zero.
The parity bit is set if the result ha s even parity.
The sign bit is set to the most significant bit of the result.
Condition bits affected: Carry, Sign, zero, parity
Example:

Label

Code

Operand

Assomled

ADI:
AD2:

MVI
MVI
ADC

C,3DH
A, 42H
C

163D
0642
8A

Assume that the carry bit = o. The instructions at ADl: and AD2: load the
C register and the accumulator with 3D and 42 respectively but do not affect
I

3-31

the condition bits. The ADC instmction performs the addition as follows:
3DH
42 H
CARRY

=
=
=

0 0 1 1 1 1 0 1
0 1 0 0 0 0 10
0

RESULT

0 1 1 1 1 1 II=- 7FH

The results can be summarized as follows:

=
=
=

Accumulator
Carry
Sign
Zero
Parity

7FH
0
0
0
0

:::'

:::

If the carry bit had been one at the beginning of the example

the following

would have occurred:
3DH
42H
CARRY
RESULT

= 00111 101
= o 1 000 0 1 0
1
=
= lOOOOO{)O = 80H

Accumulator
Carry
Sign
Zero
Parity
3.5.3

SUB

=
=
=
=

80H
0
1
0
0

SUBTRACT REGISTER OR MEMORY FROM ACCUMULATOR

Format:
Label

OEerand

Code

SUB

(

01 0 • 1

-.°1

/
R1E.G

3-32

Description: The byte in the register specified by REG or the memory: location
addressed by Hand L (if REG=I11B), is subtracted from the accumulator using
two's complement arithmetic. The result is kept in the accumulator; the byte
in REG is unchanged.
I

If there is no overflow out of the high-order bit position, indicating that a borrow

occurred, the carry bit is set. (Note that this differs from an add operation, which
sets the carry if an overflow occurs.)
The zero bit is set if the result is zero.
The parity bit is set if the result has even parity.
The sign bit is set to the most significant bit of the result.
Condition bits affected: Carry sign, zero parity
I

Example:
Assume that the accumulator contains 3EH. Then the instruction:
SUB A
will subtract the accumulator from itself producing a result of zero as follows:
3 EH = a a 1 1 I 1 1 a
+ (-3EH) = 1 1 a a 0 a a 1 Negate and add one
+_____---:=--_ _ _ _ _--=-1 To produce two's complement
Overflow
... 1] 0 0 0 0 0 0 0 0 Result = 0

Since there was an overflow out of the high-order bit position and this is a
subtraction operation, the carry bit will be reset.
I

The parity and zero bits will also be set, and the sign bit will be reset.
Thus the SUB A instruction can be used to reset the carry bit (and zero the
accumulator) .

3-33

SBB

3.5.4

SUBTRACT REGISTER OR MEMORY FROM ACCUMULATOR
WITH BORROW

Format:
~

Label

Operand

S~..

Description: The carry bit is internally added to the contents of the register
specified by REG, or the memory location addressed by HAnd L (if REG=lllB).
This value is then subtracted from the accumulator using two'S complement
arithmetic. The result is stored in the accumulator; the byte in REG remains
unchanged.
This instruction is most useful when performing multfbyte subtractions. It
adjusts the result of subtracting two bytes when a previous subtraction has
produced a negative result (a borrow). For an example of this I see Section
5.3.
Condition bits affected: Carry I sign, zmo I parity (See Section 3.5.3 for details)
Example:
Label
SB1
SB2

Code

Operand
L, 2 H
A, 4H

MVI

MVI
SBB

Assume that the carry bit

= 1.

Assembled Data
3602
0604

Then the SBB instruction will act as follows:

02H + Carry = 03H
Two's Complement of 03H

= 11111101

Adding this to the accumulator produces:
Accumulator == 04H = 000 0 0 10 0
11111101
l~ 0 0 o.n () 0 0 1

~verflOW
3-34

= .() 1 H

.~ R~:;u It

1 causing carry to be reset.

The final result stored in the accumulator is one, causing the zero bit to be
reset. The carry bit is reset since this is a subtract operation and there was
an overflow out of the high-order bit position. The parity and the sign bits are
reset.

3-35

3.5.5

ANA

LOGICAL" AND" REGISTER OR MEMORY WITH ACCUMULATOR

Format:

Label

Code

Operand

ANA

REG

j
1

R I E,G

Description: The byte in the register specified by REG, or the memory location addressed by Hand L ( if REG = lllB ), is logically ANDed bit by
bit with the contents of the accumulator.
The result is stored in the accumulator; the byte in REG remains unchanged.
The carry bit is set to zero, while the zero, sign and parity bits are set
according to the result.
The logical AND function is given by the following truth table:

o
o

Logical AND
Condition bits affected: Carry, zero, sign, parity
Example:
Since any bit ANDed with a zero produces a zero and any bit ANDed with a one
remains unchanged, the AND function is often used to zero groups of bits.

3-36

Operand
A, OrCH
C/OrH
C

Code
MVI
MVI
ANA

Label
ANI
AN2 :

Assembled Data
06rC
160r
A2

The ANA instruction acts as follows:

Accumulator
C Register

=
=

1 1 1 1 1 1 0 0
0 0 11 1 1

OrCH
OrH

Result in Accumulator

OCH

0 0 1 1 0 0

This particular example guarantees that the high-order four bits of the
accumulator are zero and the low-order four bits are unchanged.
I

3.5.6

XRA EXCLUSIVE - OR REGISTER OR MEMORY WITH ACCUMULATOR
( ZERO ACCUMULATOR)

Fonnat:
Label

Operand
REG

Code
XRA

IR ,

Description: The byte in the register specified by REG or the memory location
addressed by Hand L ( if REG =- I11B ) is exclusive - ORed bit by bit with
the contents of the accumulator. The result is stored in the accumulator; the
byte in REG remains unchanged. The carry bit is set to zero, sign and parity
bits are set according to the result.
I

3-37

The Exclusive - OR function is given by the following truth table:

Condition bits affected: Carry, zero, sign, parity
Example 1:
Since any bit exclusive - ORed with itself produces zero the exclusive - OR
can be used to quickly zero the accumulator. (The instruction SUB A could
also be used.)
I

Label

Code

Operand

XRA
MOV
MOV

B,A
C,A

These instructions quickly zero the A, B, and C register.
Example 2:
The exclusive - OR can be used to test two data bytes for equality.

Label

Code

Operand

XRA

If the contents of the C register and the accumulator are equal, the result will

3-38

be zero and the zero bit will be set. If the two quantities differ in any bit
position a one bit will be produced in the result, and the zero bit will not
be set.
Example 3:

Operand

Code

Label

MVI
XRA

A, OFFH
C

Any bit Exclusive - ORed with a one is complemented ( 0 XORI = I, 1 XORI
0 ). The XRA instruction above will therefore store the one's complement
of the C register into the accumulator.

Example 4j
Testing for change of status.
Many times a byte is used to hold the status of several ( up to eight) conditions within a program; each bit signifying whether a condition is true
or false, enabled or disabled, etc.
The exclusive - OR function provides a quick means of determing whioh bits
of a word have changed from one time to another.

CHNG:
STAT:

Code
MVI
MVI
MOV
INR
MOV
XRA
ANA

STAT2:
STATI:

DS
DS

Label

LA:
LB:

Operand
H, STAT@ SHR 8
L, STAT@ AND OFFH
A,M
L
B,M
B
B

Load address of status
into Hand L registers
STAT2 to accumulator
Address next location
STATl to B register
Exclusive-OR STAT! and STAT2
AND result with STATl

1
I

'---------..;.-.--..;.-.--------------------------:~.-.....

.)-39

Assume that logic elsewhere in the program has read the status of eight
conditions and stored the corresponding string of eight zeros and ones at
STAT 1 and at some later time has read the same conditions and stored
the new status at STAT2. The Exclusive - OR at CHNG: produces a one
bit in the accumulator wherever a condition has changed between STAT!
and STAT2.
For example:
Bit Number

STATl
STAT2

76543210
01011100
01111000

= 5CB =
= 78B =

Exclusive-OR

:::;

00100 1 0 0

This shows that the conditions associated with bits 2 and 5 have changed
between STATI and STAT2. Knowing this the program can tell whether
these bits were set or reset by ANDing the result with STAT1 .
I

Result =
STAT I =

00100 1 0 0
o1 0 1 1 1 0 0

0 0 0 0 0 1 0 0

AND

Since bit 2 is now one, it was set between STATl and STAT2 ; since bit 5
1s zero it was reset.

3.5.7

ORA LOGICAL "OR" REGISTER OR MEMORY WITH ACCUMULATOR

Fonnat:
Label

Code
ORA

°Eerand
REG

I ,°1 " .°1
1

•

I
R

Description: The byte in the register specified by REG, or the memory location addres sed by Hand L ( if REG = I11B ), is logically ORed bit by bit
with the contents of the accumulator.

3-40

The result is stored in the accumulator; the byte in REG remains unchanged.
The carry bit is set to zero, while the zero, sign, and IBrity bits are set
according to the result.
The logical OR function is given by the following truth table:
o
1

Condition bits affected: Carry, zero, sign, parity
Example:
Since any bit ORed with a one produces a one, and any bit ORed with a zero
remains unchanged, the OR function is often used to set groups of b1ts to
one.

Code
MVI
MVI
ORA

Label
OR I :
OR 2 :

Operand

Assembled Data

A, 33H

0633
160r
B2

C,OFH
C

The ORA instruction acts as follows:
Accumulator
C register
Result= Accumulator

=
=
=

= 33H

00110011
00001111
00111111

= OFR

= 3FH

This particular exampl'e quarantees that the low-order four bits of the
accumulator are one and the high-order four bits are unchanged.
I

3.5.8

CMP

COMPARE REGISTER OR MEMORY WITH ACCUMULATOR

Format:
Label

Code

Operand
REG

---.

1
_,1 I 11_ REG
I
1 011
_ 1\

3-41

Description: The byte in the register specified by REG, or the memory location
addressed by Hand L ( if REG 111B ), is compared to the contents of the
accumulator. The comparison is performed by internally subtracting the contents of REG from the accumulator ( leaving both unchanged) and setting the
condition bits according to the result. In particular, the zero bit is set if
the quantities are equal, andreset if they are unequal. Since a subtract operation
is perfonned, the carry bit will be set if there is no overflow out of bit 7, indicating that the contents of REG are greater than the contents of the accumulator,
and reset otherwise.
Note: If the two quantities to be compared differ in sign, the sense of the
carry bit is reversed.
=0

Condition bits affected: Carry, zero, sign, parity
Example 1:

Operand

Assembled Data

MVI

E S

2605

CMP

Assume that the accumulator contaips the number OAH.
tion performs the following internal subtractions:

Accumulator
( - E register)

.DAH

= a0 aa1a1a

-SH

1 1 1 1 1

The compare instruc-

1 1

1 a 0 0 0 a 1 0 1 = result
L.-overflow =1, causing carry to be reset
The accumulator still contains OAR and the E register still contains aSH;
however the carry bit is reset and the zero bit reset, indicating r. less than A.
Example 2:
If the accumulator had contained the number 2H, the internal subtraction would

have produced the following:

3-42

Accumulator
( - E register)

=
=

02H
-SH

0 0 0 0 0 0 1 0
1 1 I 1 1 0 1 1

I 1 1 1 1 1 0 1 = result
1 overflow=O causing carry to be set
The zero bit would be reset and the carry bit set, indicating E greater than A.
Example 3:
Assume that the accumulator contains -ISH. The internal subtraction now
produces the following:

Accumulator
( - E register)

=
=

-ISH
-5H

=
=

1 1 1 0 0 1 0 1
1 1 1 1 1 0 1 1

11100000
overflow: 1 causing carry to be reset

Since the two numbers to be compared differed in sign, the resetting of the
carry bit now indicates E greater than A.

3. 6

ROTATE ACCUMULATOR INSTRUCTIONS

This section describes the instructions which rotate the contents of the
accumulator. No memory locations or other registers are referenced.
Instructions in this class occupy one byte as follows:

(0 ,

o1 o I P
---""!I

00 for RtC
01 foc RRC
10 for RAt
11 foc RAR

The general assembly language instruction format 1s:

3-43

Label

Code

LABEL:

Operand

LAlways Blank

RLC

L..-.._ _ _ _ _

RRC

RAL or RAR
I

' - - - - - - - - - - - - - - - - - - - O p t i o n a l instruction label

3.6.1

RLC

ROTATE ACCUMULATOR LEFT

Fonnat:
Label

Code

Operand

RLC

,01°1°1

Description: The carry bit is set equal to the high order bit of the accumulator.
The contents of the accumulator are rotated one bit position to the left with
the high-order bit being transferred to the low-order bit position of the
accumulator.
I

Condition bits affected: Carry
Example:

Label

Code
MVI
RLC

Operand
A, OF2 H

Assembled Data
061'2

3-44

Before RLC is

Carry

ex~cuted:

Accumulator

0---..--r-l ld11110101110 IJ
l

I 11 ddol old 011

[!]

After RLC is executed:

. A = OESH

Carry = 1

3.6.2

RRC

ROTATE ACCUMULATOR RIGHT

Format:
Operand

Label
RRC

I------I
_

Description: The carry bit is set equal to the low-order bit of the accumulator.
The contents of the accumulator are rotated one bIt position to the right with.
the low-order bit being transferred to the high-order bit position of the
accumulator.
I

Condition bits affected: Carry
Example:

Code

Operand

MVI

A, OP2H

RRC

3-45

Assembled Data

06F2
OA

Before RRC is executed:

Accumulator

Carry

[ 1111 11 11 10 10 III 0 I--r-------- 0

After RRC is executed:

[0111111111010111
A = 79H

3.6.3

RAL

Carry = 0

ROTATE ACCUMULATOR LEIT THROUGH CARRY

Format:
Operand

Label

0 0 0 I 1 0 I0 1 0
1
_ " . ' . It
Description: The contents of the accumulator are rotated one bit position to
the left.
The high-order bit of the accumulator replaces the carry bit, while the carry
bit replaces the low-order bit of the accumulator.
Condition bits affected: Carry
Example:

Operand

Label
MVI

A, OBSH

RAL

3-46

As sembled Data

06BS
12

Before RAL is executed:

Carry

After RAL is executed:

Accumulator

(0 1 1 0 1 0 1 0

Carry == I

3.6.4

RAR

A= 6AH

ROTATE ACCUMULATOR RIGHT THROUGH CARRY

Format:
Operand

Label
RAR

....---.-...

0 11 11 0 I 0 I
1_ 0101
_'_ 11_
Description: The contents of the accumulator are rotated one bit position to
the right.
The low-order bit of the accumulator replaces the carry bit, while the carry
bit replaces the high-order bit of the accumulator.
Condition bits affected: Carry
Example:

Operand
A, 6AH

MVI
RAR

3-47

As sembled Data
066A
IA

Accumulator

After RAR is executed:

A=OB5H

3-48

Carry

3.7

IMMEDIATE INSTRUCTIONS

This section describes instructions which perform operations using a byte
of data which is part of the instruction itself.
Instructions in this class occupy two bytes as follows:

( a)

For the MVI instruction:

I ° °I
I

Gil L I , °I D

000
001
000
I
10O
I 0 I
I 1 0
III

°]

for
for
for
for
for
for
for
for

( b ) For the remaining instructions:

°lolo,pliloro Iv

T
I

, A,

--.--

000
001
010
I I
100
101
I 1 0
I 1 1

for
for
for
for
for
for
for
for

ADI
ACI
SUI
SBI
ANI
XRI
ORI

CPI

When a memory reference is specified in the MVI instruction, the addressed
location is specified by too Hand L registers. The L register holds the low-order

3-49

8 bits of the address; the H register holds the high-order 6 bits of the
address.
The general assembly language instruction format is:
Operand

Label

----

L•

MVI

LABEL:

REG, DATA

--....--

8 - bit data quantity

A, B, C, D, E, H, L, or M

- - - - - - - - - - - - O p t i o n a l instruction label
- orOperand

Label

----

LABEL:

DATA
,1:...,.....- - -

8 - bit data quantity

ACI, SUI, SBI, ANI, XRI, ORI, or CPI
~------

3.7.1

MVI

Optional instruction label

MOVE IMMEDIATE DATA

Format:
Label

Operand

------- -----

MVI

REG, DATA

Description: The byte of immediate data is stored in the register specified
by REG, or in the memory location addressed by registers H andL ( if REG =
IllB ) •
Condition bits affected: None
Example:
Label

Operand

Ml:
M2:
M3:

MVI
MVI
MVI

Assembled Data
2E3C
36F4
3EFF

H,3CH
L, OF4H
M, OFFH

The instruction at MI: loads the H register with the byte of data at MI: + I,
1. e., 3CH.
Likewise, the instruction at M2: loads the L register with OF4H. The instruction at M3: causes the data at M3: + I ( OFFH ) to be stored at memory
location 3CF4H. The memory location is obtained by concatenating the
contents of the Hand L registers into a 14 bit address.

3.7.2

AD!

ADD IMMEDIATE TO ACCUMULATOR

Format:
Label

[

Code

Operand

ADI

DATA

1
10 1 0

~...
D
A
I I I

T
A
I I I

Description: The byte of immediate data is added to the contents of the
accumulator using two's complement arithmetic. The result is kept in the
accumulator.

3-51

If there is an overflow out of the high-order bit position, the carry bit is set.

sign, zero, parity

Example:
Label
AD1:
AD2:
AD3:

MVI

ADI
ADI

Operand

Assembled Data

A, 20
66
-66

0614
0442
04BE

The instruction at AD1: loads the accumulator with 14H. The instruction at
AD2: performs the following addition:

=
=

Accumulator
AD2 Immediate Data

The parity bit is set.

14H = 00010100
42H
= 01000010
Result = 01010110

= 56H = New

accumulator

Other status bits are reset.

The instruction at AD3: restores the original contents of the accumulator by
performing the following addition:
Accumulator
AD3 Immediate Data

=
=

56H = 01010110
OBEH = 10111110
Result
= 00010100 = 14H

The carry and parity bits are set.

The zero and sign bits are reset.

3-52

3.7.3

ACI

ADD IMMEDIATE TO ACCUMULATOR WITH CARRY

Format:
Code
ACI

Label

I ,o I
0

/
oI

OEerand
DATA

/
D

A T
I I I I

A
I

Description: The byte of immediate data is added to the contents of the
accumulator plus the contents of the carry bit. The result is kept in the
accumulator.
The carry bit is set if there is an overflow out of the high-order bit position.
The zero bit is set if the result is zero.
The parity bit is set if the result has even parity.
The sign bit is set to the most significant bit of the result.
Condition bits affected: Carry, sign, zero, parity
ExamEle:

Assembled
Data

Label
CI:

Code
MVI

C2:

ACI

-66

OCBE

C3:

ACI

OC42

°Eerand
A,

56B

0656

Assuming that the carry bit = 0 just before the instruction at C2: is executed
this instruction will produce the same result as instruction AD3: in the example of Section 3.7.2.

That is:

Accumu lator
Carry

=
=

14H
1

The instruction at C3: then perrorms the following addition:

= 14H = 0 0 0 1 0 1 0 0
Accumulator
Immediate Data = 42H =; 0 1 0 0 0 0 1 0
Carry bit
=I
=
1

Result

3.7.4

SUI

1 0 1 0 1 II=- 57H

SUBTRACT IMM EDIATE FROM ACCUMULATOR

Format:
Label

Code
SUI

OEerand
DATA

o
I

010.

I
I

j
I

011 I 0 I 0

D
I

T
I

A
I I

Description: The byte of immediate data is subtracted from tne contents
of the accumulator using two's complement arithmetic. The result is stored
in the accumulator.
Since this Is a subtraction operation, the carry bit is set if there is no overrlow
out of the hlg' -order bit position, and roset if there is an overflow.
The zero bit is set if the result is zero.
The parity bit is set if the result has even parity.
The sign bit is set to the most significant bit of the result.
Condition bits affected: Carry, sign, zero, parity

3"54

Example:
This instruction can be used as the equivalent of the DCR instruction applied
to the accumulator. This is handy since the instruction DCR A is illegal.
I

Label
Sl:

Code

Operand

MVI

A, 0

0600

SUI

1401

Assembled Data

The MVI instruction loads the accumulator with zero.
forms the following subtraction:
Accumulator = OH _. 0 0 0 0 0 0 0 0
-S1 Immediate data = -IH = 1 1 1 1 1 1 1 1
Result

The SUI instruction per-

two's complement

1 1 1 1 1 1 1 1

-IH

Since there was no overflow, and this is a subtract operation, the carry bit is set.
The zero bit is also reset

3.7.5

SBI

while the sign and parity bJts are set.

SUBTRACT IMMEDIATE FROM ACCUMULATOR WITH BORROW

Format:
Label

Code
SBI

I I
oI

Operand
DATA

, 1 ,1

0
L

D
I

Description: The carry bit is internally added to the byte of immediate data.
This value is then subtracted from the accumulator using two's complement
arithmetic. The result is stored in the accumulator; the byte of immedIate data
Is unchanged.
This instruction and the SBB instruction are most useful when performing multibyte
subtract1ons. For_an example of this, see Section 5.3.

Since this is a subtraction operation, the carry bit is set if there is no overflow out of the high-order position, and reset if there is an overflow.
The zero bit is set if the result is zero.
The parity bit is set if the result has even parity.
The sign bit is set to the most significant bit of the result.
Condition bits affected: Carry, sign, zero, parity
Example:
Code
XRA
SBI

Operand
A

Assembled Data
AS
ICOI

The XRA instruction will zero the accumulator ( see example in Section
3.5.6 ). If the carry bit is zero the SBI instruction will produce exactly
the same results as the example of Section 3.7.4.
I

If the carry bit is one

the SBI instruction will perform the following op-

eration:
Immediate Data + Carry = 02 H
Two's Complement of 02H == 1111111 0
Adding this to the accumulator produces:
Accumulator = OR= 0 0 0 0 0 0 0 0
111 111 1 0
1 1 1 1 1 1 1 0 = -2H

1 overflow

= 0 causing

= ReSUlt
carry to be set

This time the carry and sign bits are set, while the zero and parity bits are reset.·

3-56

3.7.6

ANI

AND IMMEDIATE WITH ACCUMULATOR

Format:
Code
ANI

Label

°eerand
DATA

I I 01
0

I I I

I0 I

Description: The byte of immediate data is logically ANDed with the contents
of the accumulator.
The resu It is stored in the accumula tor. The ca rry bit is set to zero whit e the
zero sign and parity bits are set according to the result.
I

Condition bits affected: Carry

zero

sign

parity

Examele:

Label

Code

AI:

ANI

Q,pernnd
A/C

MOV

OrH

Assembled Data
C2
240r

The contents of the C register are moved to the accumulator. The ANI instruction then zeroes the high-order four bits leaving the low-order four
bits unchanged. The zero bit will be set if and only if the low-order four
bits were originally zero.
I

If the C register contained 3AB, the ANI would perform the following:

3-57

Accumulator
AND (AI Immediate
data}

3.7.7

XRI

=
=

3AH
OFH

=0
=0

0 1 1 1 0 1 0
000 1 1 1 1

Result

0 0 0 1 0 1 0

= OAH

EXCLUSIVE - OR IMMEDIATE WITH ACCUMULATOR

Format:
Label

Code
XRI

10 1

Operand

DA~

-\
0

III I 0 I olD I

Description: The byte of immediate data is exclusive - ORed with the contents of the accumulator. The result is stored in the accumulator. The
carry bit is set to zero, .while the zero, sign and parity bits are set
according to the result.
Condition bits affected: Carry, zero, sign, parity
Example:
The following instructions cause the two's complement of the C register to
be produced in the accumulator. (See Section 3.5.6 ).

Label

Code

Operand

MOV
XRI
AD!

A,e
OFFH
1

3-58

Comment
C register to accumulator
Produce one's complement
+1 = two's complement

3.7.8

ORI

OR IMMEDIATE WITH ACCUMULATOR

Fonnat:
Code

Label

ORI

Operand
DATA

~...

/
1_ 0

0ll

1_ I

olD

10 10
l. I I.'

A
I

Description: The byte of immediate data is logically ORed with the contents
of the accumulator.
The result is stored in the accumulator. The carry bit is set to zero, while the
zero, sign, and parity bits are set according to the result.
Condition bits affected: Carry, zero, sign, parity
Example:

Label
OR1:

Code
MOV
ORI

Operand.
A,C
OFH

Assembled Data
C2
340F

The contents of the C register are moved to the accumulator. The OR! instruction then sets the low-order four bits to on'e, leaving the high-order
four bits unchanged. .
.
If the C register contained OBSH, the ORI would perfonn the following:

Accumulator = OBSH -= orH
OR(ORI Immp.dlate
=
data)
-.
Result

10110101
001 I I I

1 0 1 1 1 111

3--59

:- OBr:H

3.7.9

CPI

COMPARE IMMEDIATE WITH ACCUMULATOR

Format:
Label

Code

OEerand
DATA

CP\

I0 I0

~...

I I

I I I

Description: The byte of immediate data is compared to the contents of the
accumulator.
The comparison is perfonned by internally subtracting the data from the
accumulator using two's complement arithmetic, leaving the accumulator
unchanged but setting the condition bits by the result.
In particular, the zero bit is set if the quantities are equal
they are unequal.

and reset if

Since a subtract operation is perfonned, the carry bit will be set if there is
no overflow out of bit 7, indicating that the immediate data is greater than the
contents of the accumulator, and reset otherwise.
Note: If the two quantities to be compared differ in sign the sense of the
carry bit is reversed.
I

Condition bits affected: Carry zero, sign parity
I

Example:
Label

Code
MVI

cpr

OEerand
A, 4AH
40H

The cpr instruction performs the following operation:

3-60

Assembled Data
064A
3C40

Accumulator == 4AH = 0 1 0 0 1 '0 1 '0
+ (-Immediate data ) =-40H= 11 000000
1 0 0 0 0 1 0 1 (j
Result
Overflow = 1 causing carry to be reset
The accumulator st111 contains 4AH, but the zero bit is reset indicating that
the quantities were unequal, and the carry bit is reset indicating
DATA
Accumulator.

3.8

JUMP INSTRUCTIONS

This section describes instructions which alter the normal execution sequence
of instructions.
Instructions in this class occupy three bytes as follows:

I- 0 I- 11-

X X
I

Xxi
0 01 LOW
I
_ , .' , ,

ADD

I".

X X
I

H I ADD

.""

I
_

Lhi9h order 6 bits of
a memory address

"don't care" bits ( 0 or 1 )

low -order 8 bits of a memory address

000
o0 0
o0 1
o1 0
o1 1
10 0
10 1
,1 1 0
1 1 1

1
0
0
0
0
0
0
0
0

for
for
for
for
for
for
for
for
for

IMP
JNC
JNZ
JP

JPO
Je
JZ

1M
JPE

Note that, just as i.lddresses are normally stored in memory with the low order

byte first, so are the addresses reprosented in the Jump Instructions.

3-61

The general assembly language instruction format is:
Label
LABEL:

Code
OP

Operand
EXP

L ______

a 14 - bit address

'-------IMP, JC, JNC, JZ, JNZ, 1M, JP, JPE, JPO
1 - - - - - - - - - - - - - - v p t i o n a l instruction label

3.8.1

JMP

JUMP

Format:
Label

/
(

Code
IMP

Operand
ADR

;--------~

.....,..

~ I 1 100
0I
_ I
I

alLOW
ADD
I I
I
I' ,

Description: Program execution continues at the memory address ADR, formed
by concatenating the 6 bits of HI ADD with the 8 bits of LOW ADD.
Condition bits affected: None
Example:

Arbitrary Memory
Address
3COO
3C03

Label

Code

Operand
CLR

AD:

JMP
ADI

Assembled
Data
44003E
0402

3DOO
3D02

LOAD:

MVI
1MP

A, 3
3C03H

0603
44033C

3EOO
3EOI

CLR:

XRA
IMP

A8
44003D

3-62

~-101H

Normally, program instructions are executed sequentially. Al4 bit register
called the program counter holds the address of the next instruction to be
executed. When an instruction is fetched from memory ( but before it is
executed), the program counter is incremented by the length of the instruction.
Thus, if a two byte instruction at address 3COOH is fetched, the next instruction will be fetched from address 3C02H. The IMP instructfon replaces
the program counter contents with a new address, causing program execution
to continue at that address.
Thus the execution sequence of this example is as follows:
The IMP instruction at 3COO replaces the contents of the program counter
with 3EOO. The next instruction executed is the XRA at CLR: , clearing the
accumulator. The IMP at 3EOI is then executed.
The" $" is a special character which the assembler interprets as the address
of the instruction being assembled.
The program counter is set to 3DOO, and the MVI at this address loads the
accumulator with 3. The IMP at 3D02 sets the program counter to 3C03,
causing the ADI instruction to be executed.
From here, normal program execution continues with the instruction 3COS.

3-6:~

3.8.2

JUMP IF CARRY

Format:
Code

Label

I I

-/
1

I I,
0

LOW
, ADD,
I

X X

H
, I, ADD
,,

Description:
If the carry bit is one, program execution continues at the memory
address ADR. If the carry bit is zero, execution continues with the next
sequential instruction.
Condition bits affected: None
For a programming example, see Section 3.8.9.

3-64

JUMP IF NO CARRY

INC

3.8.3

Format:
Code
JNC

Label

I I
0

°eerand

r------____
ADR

...

001 0
I

, 0 ILOW ADD
,,,
I

X X

H I

A D D
I

Description: If the carry bit is zero, program execution continues at the
memory address ADR. If the carry bit is one, execution continues with the
next sequentia I instruction.
Condition bits affected: None
For a programming example, see Section 3.8.9.

3.8.4

JUMP IF ZERO

Format:
Label

Code
JZ

°eerand
ADR

./
011101
'.'

/ ------------~

°IOloILOWADDI~xIHIADDl
. . . II'll".
1 .""1_

Description: If the zero bit is one, program execution continues at the memory
address ADR. If the zero bit is zero, execution continues with the next
sequential instruction.
Condition bits affected: None
For a programming example, see Section 3.8.9.

3-65

3.8.5

JUMP IF NOT ZERO

JNZ

Format:
Label

Code
JNZ

//
...

I ° I ° ° °I° ° r'i'¥.1I?1f1
I 1

I 1 I

X X

H I ADD,
"

Description: If the zero bit is zero, program execution continues at the memory
address ADR. If the zero bit is one, execution continues with the next
sequential instruction.
Condition bits affected: None
For a programming example, see Section 3.8.9.

3.8.6

JUMP IF MINUS

Format:
Label

Code
JM

Operand

...

IO.lll.ltO.oIOlorLOW
_ .. "II'"
~.

ADDI X XJHI ADDI

""'1

Description: If the sign bit is one ( indicating a minus result), program execution continues at the memory address ADR. If the sign bit is zero, execution
continues with the next sequential instruction.
Condition bit affected: None

3-66

For a programming example

3.8.7

see Section 3.8.9.

JUMP IF POSITIVE

Format:
Label

Operand
ADR

Code
JP

--/

11~IIIOIOIOIOILOW

-~
ADDI X XJHI ADD

I . . . . . . . '1""'.

'."111

Description: If the sign bit is zero (indicating a positive result), program
execution continues at the memory address ADR. If the sign bit is one
execution continues with the next sequential instruction.
I

Condition bits affected: None
For a programming example

3.8.8

JPE

see Section 3.8.9.

JUMP IF PARITY EVEN

Format:
Code
JPE

Labe!

Operand
ADR

--;------

( 0 II

--_________

'i'II , 0 I 0 I 0 It? 'i ~ ~ ? ? I

...
XXIHI ADD
I

Description: If the parity bit is one ( indicating a result with even parity) ,
program execution continues at the memory address ADR. If the parity bit is
zero, execution continues with the next sequential instruction.

3-67

Condition bits affected: None

3.8.9

JPO

JUMP IF PARITY ODD

Fonnat: .
Label

Code

Operand
ADR

r---------_

JPO

...

r I
_

LOW A
I

DDI
~ I xl_ ~I !i
1_

III I

AD D
I I

1
_

Description: If the parity bit is zero (indicating a result with odd parity) ,
program execution continues at the memory address ADR. If the parity bit
is one, execution continues with the next sequential instruction.
Condition bits affected: None
Examples of jump instruction:
Example:
This example shows three different but equivalent methods for jumping to one
of two points in a program based upon whether or not the sign bit of a number
is set. Assume that the byte to be tested is in the C register.

3-6U

Label

Code

Operand

ONE:

MOV
ANI

A,C
80H
PLUS
MINUS

JZ
JNZ
TWO:

MOV
RLC

A,C

INC

PLUS
MINUS

JMP

PLUS:

A,C
0
MINUS
SIGN BIT RESET

MINUS:

SIGN BIT SET

THREE:

MOV
ADI
JM

Assembled
Data
C2
2480
68XXXX

48XXXX
C2
02
40XXXX
44XXXX
C2
0400
70XXXX

The AND - Immediate instruction in block ONE: zeroes all bits of the data
byte except the sign bit, which remains unchanged. If the sign bit was zero,
the zero condition bit will be set, and the J2 instruction will cause program
control to be transferred to the instruction at PLUS:. Otherwise, the J2
instruction will merely update the program counter by three, and the JN2
instruction will be executed, causing control to be transferred to the instruction at MINUS:. (The zero bit is unaffected by any jump instructions) .
The RLC instruction in block TWO: causes the carry bit to be set equal to
the sign bit of the data byte. If the sign bit wa s reset, the INC instruction
causes a jump to PLUS:. Otherwise the IMP instruction is executed, unconditionally transferring control to MINUS: . (Note that, in this instance,
a Ie instruction could be substitutec! for the unconditional jump with identical
results) .
The add-immediate instruction in block THREE: causes the condition bits to
be set. If the sign bit was set, t!1e JM instruction causes program control to
be transferred to MINUS:. Otherwise, program control flows automatically
into the PLUS: routine.

3-69

3.9

CALL SUBROUTINE INSTRUCTIONS

This section describes the instructions which call subroutines. These instructions operate like the jump instructions causing a transfer of program
control. In addition a return address is saved on the address stack ( see,
Section 2.4 ) for use by the RETURN instructions ( Section 3.10 ). A discussion ·of the techniques and reasons for writing and using subroutines
appears in Section 5. 3
I

Instructions in this class occupy three bytes as follows:

I I
.

xiI I 0

LOW ADD

I xl

. . . ' , .11' ' .

---...
X

H I ADD]
I 1'1

,_
\

thigh-Order 6 bits of a
memory address

"don't care" bits ( 0 or 1 )

1----

o0 0 1
o0 0 0
o0 1 0
o 10 0
o1 1 0
1
1
1
1

000
0 10
1 00
1 10

for
for
for
for
for
for
for
for
for

Low-order 8 bits of a memory addres s

CALL
CNC
CNZ
CP
CPO
CC
CZ
CM
CPE

Note that, just as addresses are normally stored in memory with the low
order byte first, so are the addresses represented the call instructions.

3-70

Thegenel"alassembly languageinslructl-on fonnat is:
Label

Operand

=tAllE!.:

:t:XP

.............

L a 14 - bit memory addres,;
Io....--CALL"

ee, CNC-. cz"

CNZ. CM,GP~ CPE, -CPO

l------------:Optlon81 instruction label

.:Format:
~
CALL

-LaDel

:Operand

SUB

.~
...
~ I .:0. I·'{)l
i 1 . () )LOWA D0l: X xl:
I._(}1
) ..1
1 .J J ~ 1 ., -J. 1 I 1 _ . ) .~
..,

Des.crtpUo~

The

;"-;

D.1.

H I AD
II ,., 1 _

contents of the program counter, which equals the addres s
of the instnrcUon immediately folloWlnq the CALL lnstl'uet!on·~ Is placed on
theaadrcess stal::k for1ater use.:by a Retumlnstnactlon . Program ex~cut1on
cortUnuescat tnememory ca:ddressSl1B.. obtained hY-'OO1l:eat en ating the 6 bits
.oflUADDwttb~e~:btts of LDWcADD.
Coodltioncbitsaft'ectea-:Nbne

3.9.2

CALL IF CARRY

Format:
Label

Code
______ CC

Operand
SUB

~~~

Description: If the carry bit is one a CALL is performed to subroutine SUB.
The program counter is saved on the address stack and execution continues
with the first instruction of SUB.
I

If the carry bit is zero
instruction.

Condition bits affected:

program execution continues with the next sequential

None

For programming examples using subroutines

3.9.3

CNC

see Section 5.3.

CALL IF NO CARRY

Format:
Label

Operand
_______ SUB

o , 0 11 , 0

-------

,L ,0,

~ ~ I? 9

~
X

....

H , I , ADD
«
,

Description: If the carry bit is zero a CALL is performed to subroutine SUB.
The program counter is saved on the address stack and execution continues
with the first instruction of SUB.
I

3-72

If the carry bit 1s one, program execution continues with the next sequenUal

instruction.
Condition bits affected: None
For programming examples using subroutines, see Section 5.3.

3.9.4

CALL IF ZERO

Format:
Operand
SUB

Label

[ 0

~~
--

Description: If the zero bit is one, a CALL is performed to subroutine SUB.
The program counter is saved on the address stack, and execution continues
with the first instruction of SUB.
If the zero bit is zero,

program execution continues with the next sequential

instruction.
Condition bits affected: None
For programming examples using subroutines, see Section 5.3.

3-73

3.9.5

CNZ

CALL IF NOT ZERO

Fonnat:
Label

Code

Operand

_ _ _ _ _ _ _CNZ _ _ _ _ _ _ _~
,

Description: If the zero bit is zero, a CALL is performed to subroutine SUB.
The program counter is saved on the address stack and execution continues
with the first instruction of SUB.
I

If the zero bit is one, program execution continues with the next sequential

instruction.
Condition bits affected: None
For programming examples using subroutines
CM

3.9.6

see Section 5.3.

CALL IF MINUS

Format:
Label

Code
CM

111,1,0,0 11,0

Operand
SUB

I.L,O,W, Ap,D,1 X, X I,H,I ,Ap,DI

Description: If the sign bit is one ( indicating a minus result), a CALL Is
performed to subroutine SUB. The program counter is saved on the address
stack, and execution continues with the first instruction of SUB.

3-74

If the sign bit is zero

program execution continues with the next sequential

instruction.
Condition bits affected: None
For programming examples using subroutines

CALL IF PLUS

3.9.7

see Section 5.3.

Format:
Code
CP

Label

°Eerand
SUB

~
i

a Ia

I aI
1

LOW
I I

~~
ADD
I x x I ~ ~ 91
H I

Description: If the sign bit is zero (indicating a positive resu It ) a CALL
is performed to subroutine SUB. The program counter is saved on the address
stack and execution continues with the first instruction of SUB.
I

If the sign bit is one program execution continues with the next sequential
in stru ction .
I

Condition bits affected: None
For programming examples using subroutines

3.9.8

CPE

CALL IF PARITY EVEN

3-75

see Section 5.3.

Description: If the parity bit is one ( indicating even parity) a CALL is performed to subroutine SUB. The program counter is saved on the address stack
and execution continues with the first instruction of SUB.
I

If the parity bit is zero

program execution continues with the next sequential

instruction.
Condition bits affected: None
For programming examples using subroutines

CPO

3.9.9

see Section 5.3.

CALL IF PARITY ODD

Fonnat:
Code
CPO

Label

G I 0:' ~l
t 1

J 1 , 0 [ 1 1.

Operand
SUB

01 t : V{
0,

lA, DID

X1 X

liB ~ ~ 9 ~ ]

Description: If the parity bit is zero (indicating odd parity) a CALL is
performed to subroutine SUB. The program counter is saved on the address
stack and execution continues with the first instruction of SUB.
I

If the parity bit is one program execution continues with the next sequential
instruction.
I

Condition bits affected: None
For programming examples using subroutines

3-77

see Section 5.3.

3.10

RETURN FROM SUBROUTINE INSTRUCTIONS

This section describes the instructions used to return from subroutines.
These instructions transfer program control to the last address saved on the
address stack, and remove that address from the stack. A discussion of the
techniques and reasons for writing and using subroutines appears in Section
5.3.
Instructions in this class occupy one byte as follows:

10 oJx

xiI

tl--___

for
for
for
for
for
for
1 0 1 0 for
1 1 0 0 for
1 1 1 0 for
O0
o0
o0
o1
o1
1 0

0
0
1
0
1
0

I
0
0
0
0
0

RET
RNC
RNZ
RP
RPO
RC
RZ

RM
RPE

The general assembly language instruction format is:
Label
LABEL:

Code
OP

Operand

+. . _,_____ blank
RC, RNC, RZ, RNZ, RM, RP, RPE, RPO
'--_ _ _ _ _ _ _ _ _ _ Optional statement label

~-7R

3.10.1

RET

RETURN

Operand

Description: The last address saved on the address stack ( by a call
instruction) is removed from the stack and placed in the program counter.
Thus, execution proceeds with the instruction immediately following the
last call instruction.
Condition bits affected: None
For programming examples see Section 5.3.

3.10.2

RETURN IF CARRY

Format:
Label

Code
RC

Operand

Description: If the carry bit is one a return operation is performed. Otherwise, program execution continuec:: with the next sequential instruction.
I

3-79

Condition bits affected:

None

For programming examples, see Section 5.3.

3.10.3

RNC

RETURN IF NO CARRY

Format:
Code

Label

Operand

RN\

Description: If the carry bit is zero a return operation is performed. Otherwise program execution continues with the next sequential instruction.
I

Condition bits affected: None
For programming examples

3.10.4

see Section 5.3.

RETURN IF ZERO

Format:
Operand

Label

III

DeSCription: If the zero bit is one a return operation is performed.
program execution continues with the next sequential instruction.
I

3-80

Otherwise,

:Condltion bltsaffected: None

£..orPf09r-amminq examples, see Section 5.3.

Rn'URNIf' NOT ZERO

Oper-and

Label

Descrlption!ff the -ZerO bit ls z-ero, a return operation Is performed.
Otherwls-e.. proqram 'execution contlooeswith the next -sequential instructioft.
Condlt1onblts

affected~Nonc

For programmittgexamples, see Section 5.3.
3 .16 •.~

-:RM

RETURN iF MIN-US·

F-Cmnat;

Oserand

Description: If the sign bit is one ( indicating a minus result)
operation is performed.

a return

Otherwise program execution continues with the next sequential instruction.
I

Condition bits affected: None
For programming examples see Section 5.3.

3.10.7

RETURN IF PLUS

Format:
Label

Code

Operand

\
10 01 0

Description: If the sign bit is zero
operation is performed.

0)1

indicating a positive result)

a return

Otherwise program execution continues with the next sequential instruction.
I

Condition bits affected: None
For programming examples see Section 5.3.

3-82

3.10.8

RPE

RETURN IF PARITY EVEN

Fonnat:
Label

Code
RPE

Operand

\
Description: If the parity bit is one ( indicating even parity), a return
operation is perfonned.
Otherwise, program execution continues with the next sequential instruction.
Condition bits affected: None
For programming examples see Section 5. 3.

3.10.9

RPO

RETURN IF PARITY ODD

Format:
Label

Code

Operand

HPO

\
Description: If the parity bit is zero, ( indicating odd parity), a return
operation is perfDnned.

3-H:3

Otherwise program execution continues with the next sequential instruction.
I

Condition bits affected: None
For programming examples see Section 5.3.
3. 11

RST INSTRUCTION

This section describes the RST ( restart) instruction, which is a special
pUrPose subroutine jump. This instruction occupies one byte.
Format:
Label

Code
RST

E, X

Operand
EXP

11, 0

Note: EXP must evaluate to a number in the range OOOB to lllB.
Description: The contents of the program counter are placed on the address
stack, providing a return address for later use by a RETURN instruction.
Program execution continues at memory address:

000 0 0 0 0 0 E X P 0 0 0 B

Normally, this instruction is used in conjunction with
to eight eight-byte routines in the lower 64 words of memory in order to service interrupts to the processor. The interrupting device causes a particular RST instruction to be
executed, transferring control to a subroutine which deals with the situation,
as descdbed in Section 6.
A RETURN instruction then causes the program which was originally running to
resume execution at the instruction where the interrupt occurred.
Condition bits affected: None
3-84

Example:

Code
RST

Label

Operand
10 - 7

RST

D SHL 1

RST
RST

Comment
Call the subroutine at
address 24 (011 OOOB )
Call the subroutine at address
48 (11 OOOOB ). D is equated
to lIB.
Invalid instruction
Call the subroutine at
address 24 (OllOOOB)

For detailed example s of interrupt handling see Section 6.

3.12

INPUT/OUTPUT INSTRUCTIONS

This section describes the instructions which cause data to be input to or
output from the 8008.
Instructions in this class occupy one byte as
follows:

4_____ 0 a E x P
x X EX

for IN

P for OUT (X X -I 0 0 )

XXEXP is an input or output device number which is a hardware characteristic
of the device not under the programmer's control.
I

3-85

The general assembly language format is:
~
OP

Label
LABEL:

Operand
EXP
"-v-'

bit value from 0 - 7 decimal for IN

5 bit value from 8 - 31 decimal for OUT
' - - - - - - - - - - I N or OUT
'-----------------Optionalinstruction label

3.12.1

INPUT

Format:
Label

Code
IN

0 10

Operand
EXP

~
XI

pi I I

Description: An eight bit data byte is read from input device number EXP
( 0 - 7 ) and replaces the contents of the accumulator.
Condition bits affected: None

3-86

Example:

Label

3.12.2

Code
IN

OUT

Operand
0

10/2

Comment
Read one byte from input
device #0 into the accumulator
Read one byte from input
device #5 into the accumulator
Invalid instruction

OUTPUT

Format:
Label

Code
OUT

Operand
EXP

E X
I

Description: The contents of the accumulator are written to output device
number EXP ( 8 - 31 ).
Condition bits affected: None

3-87

Example:

Label

3.13

Code
OUT

HLT

Operand
10

OUT

IFH

OUT

Comment
Write the contents of the
accumulator to output device #10
Write the contents of the
accumulator to output device #31
Invalid instruction

HALT INSTRUCTION

This section describes the HLT instruction.
This instruction occupies one byte.

Format:
Label

Operand

Code
HLT

J0,0,0,0,0,0,0,0

3-88

blank

Description: The program counter is incremented to the address of the next
sequential instruction. The CPU then enters the STOPPED state and no further
activity takes place until an interrupt occurs.

3. 14

PSEUDO - INSTRUCTIONS

This section describes pseudo instructions recognized by the assembler.
A pseudo instruction is written in the same fashion as the machine instructions
described in Sections 3.3 - 3.13, but does not cause any object code to be
generated. It acts merely to pt;ovide the assembler with information to be
used subsequently while generatipg object code.
The general assembly language format of a pseudo - instruction is:
Label
NAMI:

Code
OP

Operand
OPND

Comment

-----

Loperand, may be optional
EQU, SET, END, IF, ENDIF, MAC, ENDM

NAME

May be required, optional, or illegal

Note: Names on pseudo instructions do not end in colons, as do
labels on machine operations.

3-89

3.14.1

ORG

ORIGIN

Fonnat:
Code
ORG

Label

Operand
EXP

---

14 - bit address

I-------Always blank
Description: The assembler's location counter I identified by the special
character $, is set to the value of EXP, which must be a valid 14 bit memory
address. The next machine instruction or data byte (s) generated will be
assembled at address EXP, EXP + 1, etc.
If no ORG appears before the first machine instruction or dara byte In th0
program I assembly will begin at location O.

Example 1:

Memory
Address

Label

1000
1001
1003
1050

Code
ORG
MOV
ADI
IMP
ORG
XRA
=

Assembled
Data

Operand
lOOOH
A,C

C2
0402
445010

NEXT
lO50H
A

The first ORG pseudo instruction informs the assembler that the object program will begin at memory address lOOOH. The second ORG tells the assembler to set its location counter to 1050H and continue assembling machine
instructions or data bytes from that point. Note that the range of memory
from 1006H to l04F is still included in the object program but does not
contain assembled data. In particular the programmer should not assume
I

3-90

that these locations will contain zero, or any other value.
Example 2:
The ORG pseudo instruction can perform a function equivalent to the DS
( define storage) instruction ( see Section 3.2.4 ). The following two
sections of code are exactly equivalent:

Memory
Address
2COO
2C01
2C04
ZCI0

3.14.2

Label

EQU

Code
MOV
IMP
DS
XRA

°Eerand
A,C
NEXT
12
A

Label

Code
MOV
IMP
ORG
XRA

°Eerand
A,C
NEXT
$+12
A

Assembled
Data
C2
44102C
AS

EQUATE

Format:

--Label
NAME

Code
EOU

°Eerand
EXP
'-v-"

An expres sion

Required name
Description: The symbol NAME is assigned the value of EXP by the assembler.
Whenever the symbol NAME is
In~

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.
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© 1973/PrintecJ in U.S.A'/MCS 329-1074-11

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2015:01:14 17:31:57-08:00
Modify Date                     : 2015:01:14 16:53:42-08:00
Metadata Date                   : 2015:01:14 16:53:42-08:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:c5a0c0ff-fed6-9844-9a83-6bd147ac5121
Instance ID                     : uuid:e5f3743f-7c31-c544-a7f4-8b8ad0d7ea13
Page Layout                     : SinglePage
Page Mode                       : UseOutlines
Page Count                      : 204

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