MCUG 3 72_Proceedings_of_the_Fourth_Meeting_of_the_Minuteman_Computer_Users_Group_Jun72 72 Proceedings Of The Fourth Meeting Minuteman Computer Users Group Jun72

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PROCEEDINGS
OF THE
FOURTH MEETING
OF THE
MINUTEMAN COMPUTER
USERS GROUP

* * *

REPORT MCUG-3-72

Meeting held
June
5-6, 1972
,.,
Silver Spring, Maryland

PROCEEDINGS*
OF THE

FOURTH MEETING
OF THE

MINUTEMAN COMPUTER
USERS GROUP

EDITED
by
CHARLES H. BECK

Meeting held
June 5-6, 1972
Silver Spring, Maryland

Report MCUG-3-72

* SPONSOR:
Systems Laboratory
Department of Electrical Engineering
School of Engineering
TULANE UNIVERSITY

PREFACE

Of the nearly 1,000 reliable computers, originally costing $234,000 each,
from the LGM 30 Minuteman ICBM Weapons System, approximately 400 have been
declared excess by the USAF.

These Minuteman D17B Computers can be classed

as extremely flexible general-purpose minicomputers.

Government activities,

industrial contractors, universities, and other organizations have acquired
these excess Dl7B computers for development and use in many fields of research,
education, and other applications.
The Minuteman Computer Users Group (MCUG) was formed to provide for an
effective information interchange and the various forms of assistance needed
by the users.

Those who are members of this cooperative, voluntary group

assist each other by sharing results, programs, applications, interfacing
techniques, maintenance procedures, and spare parts.

The MCUG membership is

in excess of 145 Government activities, industrial contractors, colleges,
universities, and other organizations.
The fourth meeting of the MCUG was held at the Sheraton-Silver Spring
Hotel in Silver Spring, Maryland on June 5-6, 1972.
included in the Appendix.

The registration list is

The persons who attended this meeting numbered 67

and represented 46 organizations.

Previous meetings have been held in Miami

Beach on July 19-20, 1971, Houston on November 16, 1970, and Anaheim on
June 11-12, 1970.
These

PRO~EDINGS

are a permanent record of the material presented at

the meeting on June 5, 1972.

This publication of the MCUG describes such

topics as procurement, simulation, state description, design of a hardware
divider, design of a binary display, and use of the Dl7B in a hybrid computer
system and an automated data acquisition and waveform analysis system.

The

agenda also included a successful demonstration of the D17B/AutoAnalyzer
if

Analysis System developed in the Systems Laboratory at Tulane University under
a research contract supported by the Army Medical R&D Command.

This cost-

effective development included an ASR35 Teletypewriter as the peripheral I/O
device which provided for full alphanumeric communication with the D17B in a
conversational interactive mode.

The D17B/AutoAnalyzer Analysis System was

delivered to the Division of Biochemistry

the Walter Reed Army Institute of

Research where it is used for automated blood serum analysis.

In addition to

the technical sessions there was considerable exchange of information during
the workshop sessions on June 60
The assistance and encouragement of Mr. Richard F. Babler and Mr. John
Po Bartell of the Defense Supply Agency are gratefully acknowledged.

We also

thank Mr. Billy G. Bass of WRAIR for the time and effort required to plan for
demonstration of the D17B/AutoAnalyzer Analysis System at Walter Reed.
Methods of Joining the MCUG
10 Send a check or purchase order in the amount of $100 to the MCUG Chairman

at the address given below. Specify MCUG membership and/or documentation
for checkout, operation, and progrannning of the Minuteman D17B Computer.
2. Request an invoice for $100 to cover the items listed above.

Drc Charles Ho Beck
Professor of Electrical Engineering
Tulane University
New Orleans, Louisiana 10118
These PROCEEDINGS can be obtained by sending a check or purchase order
for $20 to the MCUG Chairman at the a.ddress given above.

MCUG members may

rot' $6c

The following documentation is included in the MCUGmembership:
MCUG-1-71, Dl7B Computer Wire List and Logic Equations
MCUG-2-11 t DI7B Electronic Module Schematics ,
MCUG-3-71, Proceedings of the Third Meeting of the MCUG
MCUG-4-n~ Minuteman D17B Computer Programming Manual
MCUG-l-12~ Dl7B Power Supply Schematics
.'
MCUG-2-72, Minuteman Dl1B Computer Programming Manual Supplement
MCUG-3-72, Proceedings of the Fourth Meeting of 'the MCUG
Charles H

Beck

Chairman t MCUG
iii

MINUTEMAN COMPUTER USERS GROUP MEMBERSHIP
Harvard University, Physics
Haskell Indian Jr. ColI., Voc-Tech.
Heidelberg College, Physics
Hughes Aircraft Corp., Culver City
Indiana University of Pennsylvania,
Physics
Johns Hopkins University, Chemistry
Kansas State College, Pittsburg,
Industrial Technology
Knox College, Physics
Kutztown State College, Physical Sci.
LSU School of Medicine, Neurology
LSUNO, New Orleans, Science
Lowell Technical Inst., Lowell, Mass.
Linfield College, Research Institute
Mankato Area Voc-Tech. School,
Computer Maintenance
Mass. General Hospital, Boston
McDonnell Douglas Corp., St. Louis
Medical University of South Carolina,
Neurosurgery
Merchant Marine Academy,
Computer Science
Merrimack College, Electrical Engr.
Michigan State University,
Cyclotron Laboratory
Michigan Technological University,
Electrical Engineering
Milwaukee Area Technical College,
Electronics
MIT, Charles Stark Draper Laboratory
MIT, Educational Research Center
NASA, MSFC, Huntsville
Nat'l Bureau of Standards, Wash., DC
Nat'l Center for Health Statistics
Nat'l Library of Medicine, DHEW, PHS
Naval Ordnance Station, Indian Head
New Mexico State University,
Electrical Engineering
New York Institute of Technology,
Electronic Technology
Newark College of Engineering,
Mechanical Engineering
Northwestern University,
Material Science
Occidental College, Physics
Ocean Systems, Inc., Reston, Virginia
Oklahoma State University,
Biochemistry

Aerospace Corporation, Los Angeles
AFCRL (LGW), Hanscom Field, Mass.
Air Force Institute of Technology,
Engineering
Arizona State University,
Electrical Engineering
Armstrong State College, Savannah, GA
Arnold Research Organization,
ArnoldAFB, TN
Augustana College, Physics, SD
Austin College, Computer Center
Ball State University, Physics
Beaver College, Psychology
Bluefield State College, Technology
Bowling Green State University,
Psychology
Brigham Young University,
Electrical Engineering
Buena Vista College, Electronics
Bureau of Mines, Laramie
Bureau of Mines, Pittsburgh
California Institute of Technology,
Geological & Planetary Science
Center for Diseas~Control, DHEW
Cleveland State University, Physics
Christian Brothers College,
Computer Science
Colorado State University,
Atmospheric Science
Delaware River Basin Comm., Trenton
Department of State, Nassau
Des Moines Area Community College,
Electronics
Dillard Univ., Mathematics & Physics
Drexel University, Electrical Engr.
Duke University, Electrical Engr.
Eastern Michigan Univ., Ypsilanti
East:e,rn Washington State University,
Ppysics
Einstein College of Medicine,
Radiology
Fighton, Inc., Rochester, NY
Florida State University, CAl Center
Fredericksburg Geomag. Ctr., Corbin
Ft. Belvoir, Electronics
Glastonbury High School, Physics
Goddard Institute for Space Studies
Hahnemann Medical School, Radiation

MINUTEMAN COMPUTER USERS GROUP MEMBERSHIP (Continued)
University of Florida, Ophthalmology
Univ. of Houston, Electrical Engr.
Univ. of Illinois, State Water Survey
Univ. of Iowa, Neurobiology
University of Kentucky,
Mechanical Engineering
University of Miami, Physics
Univ. of Michigan, Aeorspace Engro
Univo of MississippI, Chemistry
University of Missouri-St. Louis,
Chemistry
Univo of Nebraska, Electrical Engr.
Univo of Nevada, Reno, Electr. Engr.
Univo of Nevada, Las Vegas, Physics
Univo of New Hampshire, Electr. Engr.
Univ. of Oklahoma, Mathematics
Univ. of Pennsylvania, Geology
Univ. of Penn
Johnson Foundation
Univ. ef Pittsburgh, Pharmacology
Univo of So~th Florida, Physics
Univ. of Texas i Applied Research Lab.
Univ. of Trieste, Italy, Geodesy
Univo of Virginia, Psychology
Univo of Washington, Psychology
Univo of Wisconsin, Computer Science
Univ o of Wisconsin, Electrical Engr.
Univ. of Wyoming, Electrical Engro
USAFSAM, Medical Systems Division
V. Ao Hospital, Lexington
Vo Ao Research Hospital, Chicago,
Theraputic Radiology
Vo Ao Research Hospital, Gainesville,
Nuclear Medicine
Virginia Institute of Marine Science,
Gloucester Point, Virginia
Washington University, Psychology
Washington & Lee University, Physics
West Virginia University,
Electrical Engineering
Wisconsin State University,
Engineering Mechanics
Worcester Foundation for Experimental
Biology, Shrewsbury, Mass.
Wright State University, Computer
Center

Oklahoma State University, Physics
Pennsylvania State University,
Chemistry
Polytechnic Institute of Brooklyn,
Electrical Engineering
Princeton University, Computer Center
Purdue University, Aeronautics,
Astronautics & Engineering Science
Raytheon Corporation, Bristol, Tenn.
St. John Fisher College, Physics
San Diego State College, Biology
Singer-Kearfott, New Jersey
Sloan-Kettering Institute, Biophysics
SMU, Computing Laboratory
Southwest Minnesota State Cellege,
Electronics
Space Rad. Effects Lab., Newport News
Stanford University, Linear
Accelerator Center
State University College, Breckport,
Data Precessing Services
State University of NY, Mat. Science
Stephen F. Austin State Univ., Physics
Stevens Institute of Technology,
Electrical Engineering
.
Technitrol, Inco, Philadelphia
Tektronix, Inc., Atlanta
Teledyne-Ryan Aeronautical, San Diego
Tennessee Technological University,
Mechanical Engineering
Texas A & M University, Physics
Tulane University, Electrical Engr.
Union Carbide (Nuclear), OakRidge
USDA, ARS, Ames
USDA, Research Service, Beltsville
University Computing Coo, Dallas
Univ. of Akron, Electronic Tech.
University of California, Berkeley,
Fl~ctrical Engineering
Univ. of Colorado. Electrical Engr.
Univ. of Arizona, Optical S.ciences
.
Univ. of Dallas, Chemistry
Univ. of Delaware, Electrical Engr.
University of Florida,
Metallurgical & Materials Engr.

0 ,

TABLE OF CONTENTS
Page

·....... ·..
• · · . ·
MINUTEMAN COMPUTER USERS GROUP MEMBERSHIP · · · · ·
MINUTEMAN D17B COMPUTER PROCUREMENT
·······• ·······
MINUTEMAN D17B COMPUTER DESCRIPTION . . · · · · · • · • · · · · · · ·
MINUTEMAN D17B COMPUTER SPECIFICATIONS • · · · · · · ·
····•
• · ·
SOFTWARE SIMULATION OF THE MINUTEMAN D17B COMPUTER
PREFACE • • • • • • • • • • • • • • • • • •

ii
iv
1
2

4
5

Bruce Chatterton and Gary B. Lamont
AFIT/ENE
Wright-Patterson AFB
APL SIMULATION OF THE D17B

• • • • • • • • • • • • • • • • • • • • • 17

Harry S. Warford
USAFSAM, Medical Systems Division
Brooks AFB
A HARDWARE DIVIDER FOR THE D17B GUIDANCE COMPUTER • • • • • • • • • • 27
Alfred M. Williams, Boeing Co.
and
James D. Bargainer, University of Houston
STATE DESCRIPTION OF THE D17B COMPUTER

•••••••••••••••

Douglas J. Allen and Gary B. Lamont
AFIT/ENE
Wright-Patterson AFB
USE OF THE D17B IN A HYBRID COMPUTER SYSTEM • • • • • • • • • • • • • 66
Lansing B. Evans and Charles H. Beck
Systems Laboratory, Electrical Engineering
Tulane University
DESIGN OF A BINARY DISPLAY FOR THE Dl7B COMPUTER

• • • • • • • • • • 76

Harry S. Warford and D. S. MOran,
USAFSAM, Medical Systems Division
Brooks AFB
AUTOMATED DATA ACQUISITION AND WAVEFORM ANALYSIS
USING THE Dl7B COMPUTER • • • • • • • • • • • • • • • • • • • • 83
Charles H. Beck and Yih-Young Chen
Systems Laboratory, Electrical Engineering
Tulane University
• • • • • • • • .. • • • • • • 93

APPENDIX - REGISTRATION LIST' •••
vi

MINUTEMAN D17B COMPUTER PROCUREMENT
Approximately 800 Minuteman D17B Computers are expected to be declared
excess by the USAF through 1974.
was approximately $234,000.

The original acquisition cost per system

These computers can be acquired by qualified

agencies, contractors, and grantees as the systems become available through
appropriate ADPE reuti1ization agencies on an "as is" non-reimbursable basis
as follows:

DoD Agenci es
Contact respective service Rqs. for ADPE Acquisition for approval and
for forwarding of Requisition Form 1419 to DARO.

DoD Agency Contractors and Grantees
Contact respective contracting officers for approval and for forwarding
of Form 1419 to Defense Supply Agency, DSAH-DARO, Cameron Station, Alexandria,
Virginia 22314.

Civil (Non-DoD) Agencies of the Federal Government
Contact respective Office for ADPE Acquisition for approval and for
forwarding of Transfer Order Form 122 to GSA Excess Equipment Utilization
Branch, Crystal Mall Bldg. 4, Washington, DC 20406.

Civil Agency Contractors and Grantees
Contact respective contracting officers for approval and for forwarding
of Form 122 to GSA as listed previously.

Authorized Donees
Contact respective state surplus property offices for acquisition through
DREW Office of Surplus Property Utilization, 4452 DREW North Bldg.,
Washington, DC 20201.

MINUTEMAN D17B COMPUTER DESCRIPTION

Functional Capabilities and I/O
The D17B is a small
and has the

capab~lities

general~purpose

of:

computer.

It is totally programmable

receiving and sampling analog signals, digital

data, or pulse-type input signals; logical decision-making and performance
of arithmetic operations using an instruction set of 39 machine language
instructions; and transmission of output data in the form of analog, digital
and pulse type signals under program control.

Because of the extremely flex-

ible I/O capability of the D17B, it can be quite useful in a wide variety of
applications.

Central Processing Unit and Control
Since the D17B is a serial-binary computer,.simultaneous access to all
the bits of a memory location is not needed either for instructions or data.
Hence, the arithmetic registers need not be constructed entirely o.f flipflops.

Instead, they are in the form of circulating loops in memory.

The

Dl7B has four double-rank arithmetic registers which are Accumulator (A),
Lower Accumulator (L), Instruction

Regist~r

(I), and Number Register (N).

Because the L-register is addressable, it can be used as rapid-access storage
in addition to performing normal arithmetic functions.

There are two non-

addressable arithmetic registers, the 1- and N-registers, which are used
without programmer control and one 3-bit pseudo-index (phase) register.
The central processing unit (CPU) has I/O access to four rapid-access
memory loops of 1, 4, 8, and 16 words in addition to the main memory which is
arranged in 21 ·channelsof 12.8 words each.

Two input buffer loops of four

words each provide additional input capability to memory in the form of
direct data entry.

These are the V- and R-loops which can also be used as

general-purpose rapid-access memory loops.

Programmed data channels cause data transfers into the arithmetic registers.

All machine functions are processed and interpreted in the CPU.

The

memory channel address from which the next instruction is to be taken is
determined by the location counter.

When the CPU is ready to accept another

instruction from memory, the address is specified by the channel address
stored in the location counter and the sector address specified in the
previous instruction.
The phase register can modify the operand address of one of the multiply
instructions.

This register also serves as a selector switch for choosing one

of two pairs of inputs to one of the incremental pulse-type input loops and
for selecting one of four external positions for each of the three D-A analog
voltage outputs.
The Accumulator holds the results of all arithmetic operations and serves
as an output register for parallel digital data, pulse-type signals, D-A
analog voltage outputs, and telemetry data.

The Lower Accumulator is involved

in certain arithmetic, input, and logical operations.

A real-time clock is

provided by internal timing signals derived from the clock channel of the disc
memory.

Specifications
The D17B is basically composed of two semi-circular sections.

One half

contains the power supply circuit cards which generate the various dc voltages
required in the computer and a 400 Hz
motor in the 6000 rpm disc memory.

signal for providing power to the

The other semi-circular section contains

the discrete DRL and DTL logic components of the computer itself.

Some of

the detailed specifications for the D17B Computer are given in the following
table.

The high degree of reliability and ruggedness of the computer are

evidenced by the strict requirements of the Minuteman ICBM Weapons System.

MINUTEMAN D17B COMPUTER SPECIFICATIONS
Manufacturer: Autonetics, a division of North American Rockwell
Model: D17B
Year:
1962
Type:
Serial, synchronous
Number System: Binary, fixed point, 2's complement

Logic Levels: ·0 or False,
Volts; lor True, -10 Volts
Data Word Length.(bits): 11 or 24 (double-precision)
Instruction Word Length (bits): 24
Maximum I/O (words/s): 25,600
Number of Instructions: 39 types from a 4-bit op code by using five bits
of the operand address field for instructions
which do not access memory.
Execution Times:
Add (ps): 78 1/8
Multiply (ps): 546 7/8 or 1,015 5/8 (double precision)
Divide: (Software)
(Note: Parallel processing such as two simultaneous single precision
operations is permitted without additional execution time.)
Clock Channel: 345.6 KHz
Addressing: Direct addressing of entire memory
Two-address (unf1agged) and three-address (flagged) instructions
Memory:
Word Length (bits): 24 plus 3 timing
Type: Ferrous-oxide-coated NDRO disc
Cycle Time (ps): 78 1/8 (minimal)
Capacity (words): 5,454 or 2,727 (double precision)
Input/Output:
Input Lines:
Output Lines:

48 digital
28 digital
12 Aria10g
3 Pulse
Program:
800 5-bit characters/s
Physical Characteristics:
Dimensions: 20" high, 29" diameter
Power:
28 V dc ± 1 V at 19'A
Circuits:
DRL and DTL. DoUble copper clad, gold plated, glass fiber
laminate, flexible polyurethane coated circuit boards.
Software: .Minimal. delay. coding using machine language modular
special-purpose subroutines.·
.
Reliability: 5.5 years MTBF

SOFTWARE SIMULATION OF THE MINUTEMAN
D17B COMPUTER
Capt Bruce Chatterton

Gary B. Lamont

Electrical Engineering Dept
Air Force Institute of Technology
wright-Patterson Air Force Base, Ohio 45433
ABSTRACT
A software program has been developed which simulates the functions of
the Minuteman D17B Computer at the register transfer level.

The simulation

program is written in the FORTRAN Extended Language to be used on the Intercom
System (teletype) of a CDC 6600 Computer System.

The simulation program was

developed at the Air Force Institute of Technology as an aid to research in
the D17B Computer utilization program. The simulation program can be used
as a teaching aid, for executing D17B programs, and for debugging program
tapes to be run on the D17B Computer. The simulation program consists of
a main program and eight subroutines. A programming language was developed
for the D17B Computer Simulation Program which contains numbers and load
codes, switches, and miscellaneous commands.
I.

Introduction
A software simulation of the Minuteman D17B Computer has been developed

at the Air Force Institute of Technology (AFIT) (Ref 2). The general
1.e;Telopment objectives and results of this simulation are presented in this
paper.
The purpose for developing the D17B Computer Simulation Program was to
create an aid that would be useful to the research effort of the D17B
Computer utilization program. This research effort is concerned with getting
a D17B Computer operational in a laboratory environment and finding useful
applications.

The simulation program has shown itself to be useful in many areas. The
simulation program can be used in learning the basic operations of the D17B
Computer. It can also be used as backup capability for running D17B programs
when the actual computer is not available. Its most important use, however,
is that the simulation program can provip,e error checks for the D17B programs
which it executes. The hardware version of the D17B Computer has no executiontime error checking capabil~ty.
The capability for entering D17B programs from punched tape has been
incorporated in the D17B Computer at AFIT~ Provisions were also made in the
simulation program for reading and executing the data from these same punched
tapes. Therefore, the simulation program can be extremely helpful in the
preparation of the program tapes which are to be read into the D17B Computer.
The simulation program helps in tlle preparation of the program tapes by
detecting and locating invalid symbols punched on the tape, by decoding the
program instructions, and by detecting addressed locations in memory that
are out of range of the program being executed.
Problem statement and Objectives. The prime objective of the D17B Computer
simulation program was to simulate the functions of the D17B Computer. To
pursue this objective;l the following criteria were established~
1. The simulation program was to simulate the D17B Computer at the
register transfer level. A register transfer approach was used because
it allowed the D17B to be simulated at the information and data transfer
level. Thus, it was not necessary to simulate the logicr equations required
to clear and set each flipflop_ The register transfer approach also
allowed for easability in tracing the information flow in the simulated
computer as data is loaded and programs executed.
2 •. The FORTRAN Extended Language was the computer simulation language
chosen for writing the simulation program. This language was chosen because
of access to a computer system which contained the FORTRAN Extended Compiler.
The Computer Design Language (CDL) described in reference 3 was used in

writing portions of the simulation program, but because of the nonavailability of a CDL compiler, a transformation to the FORTRAN Extended Language
was made (Ref 3, Chaps 1-5). CDLis much more descriptive of computer
operations than FORTRAN.
3. The simulation program was to simulate the actual computer as
closely as possible. The same algorithm implemented on the D17B Computer
was used in the simulation program for most functions. This close correlation between the actual computer and the simulation program makes it
possible for a user to use both the computer and simulation program using
only one set of programming techniques. In the areas where a close simulation could not be realized, a quasi-simulation was used. The quasisimulation uses the same register inputs and generates the same results,
but the method of obtaining the results differ.
4~ The real-time control functions (Fine Countdown and Incremental
Inputs) of the D17B were not to be included in the simulation program.
The Fine Countdown function involves the V-loop and the U-loop forming
a digital integrator which operates without program control. The Incremental inputs are inputs to the D17B which are incrementally supplied
to the V-loop and R-loop without program control. The instructions
associated with these functions could be added by a user who is
r~searching the area of real-time control applications for the D17B.
The remainder of this paper will be devoted to a description of the
organization and structure of the D17B Simulation Program and the D17B
Computer Simulation Language.
II.

D17B Computer Simulation Program

The organization and structure of th~ D17B Computer Simulation Program
will be described in this section. The simulation program simulates the
D17B Computer at the register transfer level and is written in the FORTRAN
Extended Language to be run on the Intercom System (teletype) of a Control
Data Corporation (CDC) 6600 Computer System.

The concept used in, writing the simv.1ation program was, to have the person
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using ,it. provide the same ,data to the progI'aIJ:), as h,e. would ,if ,he were using the
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actual

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compute~

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in the Jaborato:ry.

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J'he sw:itches, ;must be ,set to the proper

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position to accomplish loading and computing.

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,. . '

~stbe

The data

error free 'to

successfully execute a p~ogram., ,The type of di 13Pll3,Y (register or memory) is
specifiec;l by. the ~us:er. ,
. ;., •

subroutines.

Simula1;i~oA ,Progr~

The D17B. qomputer,.
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consists, of. a, main program ande.ight

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The main program .i¥l",a .qompilation. of
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thr~e

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distinct sections each
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of which.. performs , a major
.function.
TheSe.
thre.e, sections
are:
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.

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:,.,'..

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Eeadingand
TI'ansla tiop
Section
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Noncomp~te

Compute Mode Section

Mode Section

Fig. 1 shows the program flow between trese.

~eotiolls

of the main program and

the subroutines •.
The Reading
and,
TraJl.Slation. Section
is.,
..
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portion of the simulation program.

thet~ansla ter
..

and
inte:r:preter
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All input data., is read, interpreted, and
;

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".....

translated in this . portion. 9f the main program., Input data is read as alpha,;..

betic and nUlI1eric characters.

~his

,....

data is then iniierpreted. as octal qr

binary data, a D17B load code, a switch
designation (setting), or a miscel'.
.

laneous connnand.

The miscellaneous commands, are responsible for a variety.

of functions which include tbe, following:
•

. ' ,

•

discrete data storing, incremental data, storing, and mode tracing.
fer of operation to the noncompute mode or9neof the

sub~outines

A transis made to

utilize this data.
The Noncompute Mode Section of the simulation program simulates the noncompute mode of the D17B computer.

The noncompute modeis'responsible for

synchronizing, idling','preparing1to, load,preparing to compute, 'loading data
into memory, and verifying "the contents' ,of, memory.
The Compute Mode Section of the simulation program simulates' the compute
mode of 'the D17B Computer.

The compute mode is'responsible for searching,

reading, and writing memory and instruction' exec.ut1:on. '

abnormal program termination

S.ubroutine
DISPLAY

.,
ST ART

READING

o
o

c:T

NONCOMPUTE

STOP<

..,fle{ld 8. Interpret
more Data

SECTION

..o

L.....t>-

SECTION

Subroutine
fJlEMORY

Subroutine
-

Subroutine
STORE

Subroutine < _ . -

Subroutilio
FLAGSTO

Subrotlt inc
DISCHET

_._-.'.,.
1-'

COMPUTE

MODE

TRANSLATION

s::!

Load Data

:>-

Subrout ilw
INCHEr}:;:

UNLO!':D

The subroutines

as~ociated

with the D17B Computer Simulation Program were

made for three purposes:
1. Those functions which were needed several times through the program
were created as subroutines. Subroutines falling into this category are
Subroutine LDA.D, Subroutine. UNLOAD, aha. Subroutine DISPLAY ~ Subroutine LOAD
provides the functio:p. .of.l,oad~ng, the .,contents of the accumulator into addressed
memory locations. Subroutine UNLOAD performs the funQt~o~ ~~ unloading an
addressed word of memory. The information
unlo~ded is. then used either as an
.
instruction or an operand. Subroutine ,DISPI,.A~ prov~q.es the simulation program
,"

'-""-.

(

j ' . , '

with the capability of displaying the binary contents Qf all registers and
loops which are specifi~d by. the user. The contents of a register or loop is
provided as output only when the contents of that register or loop cha:Oges.
2.

Those ,functions which are only called from one place in the main

program, but which are of -such importance that a. separate location is beneficial to the organization of the simulation program., are also subroutines.
Subroutines in this . category are Subroutine STORE, Subroutine FLAGSTO, and
Subroutine MEMORY. Subroutine STORE implements the D17B store (STO)
instruction, which stores the contents of the accumulator in the memory
,
,

location specified by the instruction register. Subroutine F,LA,GSTO
performs the function of deciphering the flag store locations bits of the
..
instruction register. The contents of the accumulator are then stored in
the deciphered channel at the sector address associated with the first
wordtime of execution of the present instruction. Subroutine· MEMORY
provides the capability of displaYing th~ contents of memory (channels 00
thru 50) whenever a memory command is us~d. Only those portions of memory
that have . been wri.tten. into since·· mem?I7.was" .last.··initialized will be shown
in the output listing •.
..

0/- • ," "

;

••

3. Those f~ctiol'ls which Will not be. used ,very f;requently and could be
removed from the simulation program. if it' w.s determined that they were not
really neededarea:lso subro~tihes. However,' to be abl'e' to utilize all the
instruction set or the"-D17B' Computer' and all the channel designations, these
,

..,~

functions had to remain as a part of the simulation program. Subroutines
in this category are Subroutine DISCRET and Subroutine INCREME. Subroutine
TIISCRET provides the capability of entering discrete data and storing it
for use in a prograrrlsing the discrete input instructions (DIA or DIB).
Subroutine INCREME provides the capability for entering quasi-incremental
data into the four words of the V-loop or the four words of the R-loop.
The D17B Computer Simulation Program requires approximately J5K of
core memory to execute on the CDC 6600 C9mputer. The majority of programs
require between two and five seconds of central processor time. In five
seconds, approximately 1000 D17B instructions can be executed by the
simulation program.
III.

D17B Computer Simulation Language
The D17B Computer Simulation Language is the programming language which

was developed as the input data for the D17B Computer Simulation Program.
For purposes of describing this language, it has been divided into the
following categories:
1. Numbers and Load Codes
2.

Switches
J. Miscellaneous Inputs and Commands
The number systems and load codes accepted by the

Numbers and Load Codes.
simulation program are:
Octal Numbers - 0, 1, 2,
Binary Numbers - 0, 1

3, 4, 5, 6 7

Load Codes - HALT, LOCATION, FILL, VERIFY, COMPUTE, ENTER, CLEAR, DELETE
'l'h"'~e jifferent representations of the numbers and load can be specified
and will be accepted by the simulation program as valid data. These three
representations are Octal, Binary, and ASCII. The Octal representation represents the type of input that would be supplied from a teletype keyboard or
switches on a control console. The Binary representation represents the type
of input which appears on the character'input lines going into the D17B

Vomputer. The ASDII representation represents the type of input data on a
punched tape which can be entered into the D17B Computer by a tape reader.
The numbers and load codes in the three representations are as follows:
ASCII
Binary
Octal
Numbers -

Re12r esentation
a
1
2

J
4
5
6

Load Dodes -

7
HALT
LOCATION
FILL
VERIFY

RsU2r~sflnta tion

10000
00001
00010
10011
00100
10101
lalla
00111
01000
11001

Re12rflsflntation
a
1
2

J
4
5
6

7
8
9

110~0

01011

;

11100
<
01101
CLEAR
01110
?
DELETE
11111
Switchese With the simulation language in this category, it is possible to
specify switches and designate a setting or mode. The simulation program
COMPUTE
ENTER

accepts these switch designations and provides this information to program
variables associated with the switches. The form for specifying switches
is as follows:
Switch(Arg)
where Switch is theq.esignated switch mnemonic name, and Arg is the switch
setting or mode position of the switch. The switches and allowed settings

are as follows:
Switch Name

Switch Mogmonic & Settings

Timing Signal
Power On/Off Switch
Initiate Loading Switch
Master Reset Switch

T(ON)
PR(ON), PR(OFF)
FS(ON)
MR(ON)

Cold-Storage ~ite Switch
Discrete Switch
Mechanical Input Switch
Compute Mode Switch

EW( ON), EW( OFF)
Db(ON), DD(OFF)
IM(ON)
K(HALT), K(SINGLE), K(RUN)

Miscellaneous Inputs and Commands. The simulation language iI.1 this category
provides many functions. The functions that will be described are listed as
follows:
Register and Memory Display
Mode Tracing
Execution Specification
Register and Memory Display. The binary contents of any of the registers
(A, I, L, N~ or loops (U, F, E, H, V, R) can be displayed by use of the register
command. The register command has the following form:
REGISTER(Arg)
where Arg is a list of the registers. and/or loops to be displayed.
To. display the Gontents of memory (channels 00 thru 50), a memory command
is used. The memory command has the following form:
MEMORY(Arg)
where Arg is the type of display requested, either BINARY or OCTAL.
Mode Tracing. MOde tracing is used in deciphering the contents of a
program. In the noncompute mode, the modes of operation are listed as output.
In the compute mode, the instruction being executed is listed as outpUt and a
flag store is indicated if it was programmed. The mode tracing capability is

14
requested by a signal command with the following form:
SIGNAL
Execution Specification.

There are numerous occasions when a programmer

will inadvertently write a program which loops on itself resulting in eXecution
going on to infinitum.

To prevent this from happening in the simu1~tedcomputer,

provisions were made for counting

~he 'number of execution cycles in' the 60mpute

mode and terminating the program run when the number exceed~aspecified ~ount.
'The programmer can specify th,e number' of executions allowed' by an eXecute; command.

"
The form of the execute
command is as follows:

EXEGU'~(Arg)

where Arg is any four digit deci~l n~ber from 0000 to 9999.
Other misce11aneo'us inputs and'command'providethecapability of settin.g

and clearing f1ipflops~ initialization of the" contents of memory and certain
specified variables, storing of discrete input data, and storing of quasi...
incremental input data.
PrOgramming Methods. D17B programs are executed on the simUlated computer
,

by arranging the simulation language in a program form.

D17B programming

techniques are described, in the Minutemab. Computer Use,r'S Group Programming
Manual (Ref 1). The simu1ation program allows data to be input without a
format, so a programmer can write a continuous program With each simulation
language word separated by a blank.
The approach' for arranging' the input 1a'nguage.. in program form found
most advantageous by the author is to visualize a hardware control console
with switches for each element of thesf.mulation language'.

To"write a program

then requires that the programmer write' down the simulation language word for
each switch that he would push on theco1'l.sole.

This approach works because of

the similarity between the simulation program and the'hardware ver'sion of the
Computer.
An example program which wa:s:' run on the simulated cOmputer has been
included in this paper as Appendix A.

IV • Cgppl,uion
The lott'lfare simulation program ot the D17B Computerprelented in this
paper hal been operational linoe November 1m. The simulation program was
de",eloped to simulate thetunot1ons of the D17B Oomputer. One of the objeotives
,ot this limulation wal to have the ,Iimulation pro,rd. lillUlate the aotual oomputer al ololel,. al pollible. This objeotive wal lDet beoause the _jorit,. of
the In.7! tunotiol1l have been i1101uded in the ,simulation prOll'''. The loading
aDd interaotion funotionl ot the nonoompute mode have been used. In the
88apute mode, the learohing, readiDlh and. writil1l.lIIID017 and inltruo't;ion exeoution are all part of the siJlulation proc.raa. Wherever po••ible, the lame
allOrithm illplelDented. on the Dl7B' WILl Uled in'the· .imulat1on program. Thi.
a~roach re8Ulted in lome i08£fioie11Oiel in the simulation program, but a
by-produot ot usi. the .... al,orithm i. that the liDIulation proaram OaD be
used a. a teaohiDl aid tor learrd.ni the operatiollot the »1'18 Oomputer. .uIO
, enol" deteotion va. bui1t into the .imulation 'proar" aJ2d hal been "'e1"1 helpful
in creatiDl proar" tape. to be run on the D17B Ooqmter.

IiliJi ARf.Pht
Bttot, O. H. WI 0SJllWderf:£Mt.'M MeMl. "port ICt1O-4-71.
." Orlean., Louisiana. Tulane Unt"'eraityS,. . . LaboratOl7, Department
or .1ectrioallltllineeriDl, September 1ml.
.

I' POltiQA

Q& the. MilQ1itan IlJ.'lI Q'8PPtv.
Malter The.i.. Wri,ht-Patteraon AlB, Ohio, Air 'oroe lnstitutn ot
Technolol7, Department ot Il.•ctrioalll'lli!1lerin~b Maroh 1972.

Ohatterton, B. §gnarl

3. Olm, I.
Je1"878

.IPtrgd'lQi;1on tOOC81?1rl;ef OrI'P1Milg.

Prentioe-Hall, Ino., 1970.

_l.wood 01itt., lew

,if,

'I IOlU':D1SPOSEDTOPJUNTER. tyPE "I''' AHI) "yotfRNArU:"C OTHEJt""
WISE TYPER • H
'

l ' OUTPUT

****.****.***********************************"'**********
**
**
**
D178 COPlPUlER
**

*."'*

"'*

SIMULATION PROGRAM

**
"
,**
***.*********~************************.********** •• *••••
*.*

OATE=

TIME:

03/07/12

•• "UNrOUT OF INPUT

(ENTER PROGRAM'

'~OGRAPJ

J4.28.'8

S ADDI Tl OH It 1"L£ PROGRAM
pltC ON) MRlotU FlU O,N) twUltU 'ILL
4It010002IHTE1t640l0008EHlER CLEAR 1 ENTER
i'lEf'10RY( OCTAL) PUt( ON) EXEcutE'OOD.) SIGNAL R[GIITlRC A)
'p IU

0''''

"'*

MEMORY

RESULTS 0' IlI'IU&'ATION

J( CRUN)

'DUM' *.

CHAH . SECt

00000

440aooos

77777777

00000001

•• gHD O,.M".CRYDUMP.. ", (PORTlONS OF "tMORY, NOT LlstED CONTAIN NO
INFORMATION PAODUCED BY THE 'RISEln 'ROGa,," RUtH
H(j. 0' El(ECUr'Cltf• .,EC1'IEO i
,.81 GHAL ON" MOllIIWILL. 8£ TRACED

0(4) I'O(2)'Utl 1I>LI IUI-MOO£ 0' HA.HUAL. HA'-t
PRIPARE rOCOMPUtE lua·MOOI 0' MAHUAL. HALT
COl1PUTE PlOOI
TMA.'ER lHlT'UIC'UOH- (TRA)

'I'"'

CLiA. ,. AID 1HI'ltU<:,"lO' -(Ct.A),'
A(14·1):000 000
000000 000 001
AUD t HI TRUC tl 0;., til , (M)'J
A(24-.) : 000 000000 lot 000 000 010010

NO. 0' EX£CUTIOtfS KA\I£EXCEEDiO Hp. SPEct"Er) .. 'JOGRA, TERMINATED
au. AtfOTHERPROGRAt'S TyP' RUtl, TO ITOP tyPE HALT .. HALT

Elf0 OF '''OOOAM

14.3.1 .14 .stOP

EXECUTION TIM!:

.777

SEC

APL SIMULATION OF THE Dl7B
HARRY S. WARFORD, CAPT, USAF, BSC*

Introduction
A simulation of the Dl7B serves a broad spectrum of applications.
It allows a rapid development of software by not only emulating the basic
machine, but by providing an inexpensive and rapid means of providing a
large array of outputs. All manner of I/O devices can be simulated for
development when the actual application may be dedicated and require few,
if any, I/O devices. Additionally, the simulation is useful where no
Dl7B exists. Students can receive hands-on experience with many types
of machines by merely calling on a simulation such as the one under
development here. Program debugging likewise proceeds at an accelerated
rate since all the powers of a large system are available with built-in
tracing routines.

Program Development
This simulation is by no means complete at present but has been
developed in strict accord with actual machine procedure so as to render
it easily expandable to a full simulation. The serial nature of the
D17B has been preserved at the word level by controlling the simulation
with a sector counter advancing one sector at a time as in the rotation
of the disc memory. Figure I is a simplified flow chart for the machine
and illustrates how each phase is controlled by tests performed on the
sector count.
Development from this flow chart proceeded with APL on an IBM 360
series system and later on an IBM 370 series system.** APL has proven
to be an ideal language for this simulation due to its inherent capability
to handle vector quantities. This was the author's first encounter with
APL, hence many of the expressions are not as efficient as they could be.
However, the development proceeded with few difficulties to the wide choice
of APL operators.
The main program illustr.ated in Figure 2 was first developed with
dummy instructions in place of the execution routines. Those routines not
yet implemented are left in as dummy statements providing only a printed
indication of proper decoding. As development continues, some of these
will be deleted entirely as they produce outputs that cannot effectively
be simulated or have no apparent use in a general purpose system.
*To be presented by Major M.A. Jenkin, USAF, MC
**This simulation was started during a course taken by the author at
Trinity University, San Antonio, Texas.

Along with the basic program, several short routines are provided
to simulate necessary panel switches to allow program loading and
execution start. These are given in Figure 8 and will be discussed in
greater detail following the discussion of the main routine and execution
routines.
At present, twenty-two instructions have been successfully simulated.
Most of these were straight-forward but for clarity all are listed here
with comments as to considerations given for simulation.
CLA: Clear and Add. Present operand, now in
N-register, replaces contents of A-register
ADD: Add. Contents of A-register and N-register
added modulo 16777216.
SUB: Subtract. Contents of A-register and complement
of N-register added modulo 16777216.
MPY: Multiply. Sign of product predetermined; contents
of A-register saved in L-register; rounded product of
magnitudes formed then corrected for proper sign.
Sector counter advanced 12 additional counts.
SAD: Split Add. Contents of N-register and A-register
decoded into split format and center bits of A-register
saved. Split words added independently but simultaneously
modulo 2048. A-register reassembled.
SSU: Split Subtract. Contents of N-register split and
complemented. Jump to SADI to complete as normal spii.t
add.
SMP: Split Multiply. Middle of L-register saved; contents
of A-register encoded into split word format and saved
criss-cross fashion in L-register. N-register encoded into
split word format and signs independently but simultaneously
predetermined. Products of magnitudes formed then corrected
according to each predetermined sign. During process, products
are rounded. Sector counter incremented 12 additional counts.
COM: Complement.
subtraction.

Contents of A-register complemented by

MIM: Minus Magnitude. If contents of A-register are not
negative they are forced negative by jumping to COM.
ANA: And to A. Contents of L-register and A-register are
encoded into 24-bit vectors and logically anded bit by bit.
REsults are decoded into 24 place binary number and left
in A.

ARS: Accumulator Right Shift. Contents of A-register
shifted right by division with simulated loss of rightmost bits by floor value if original A-register not negative.
For negative A-register, complement of A-register is first
shifted then complemented to provide for extension of sign
bit. In either case, sector counter is incremented
appropriate number of counts as determined by number of
places shifted.
ALS: Accumulator Left Shift. Contents of A-register shifted
left by multiplication and limited to 24 bits by residue
modulo 16777216. Sector counter incremented appropriate
number of counts as determined by number of places shifted.
SAR: Split Accumulator Right Shift. Contents of A-register
encoded into split word format and middle bits saved. Each
half word shifted right by scheme similar to ARS. Arregister
put back together and sector counter incremented appropriate
number of counts.
SAL: Split Accumulator Left Shift. Contents of A-register
encoded into split word format and middle bits saved. Left
shift of each half word proceeds as in ALS. A-register
reassembled and sector counter incremented appropriately.
SLR: Split Left Word, Right Shift. Contents of A~register
encoded into split word format and middle bits and right word
protected while left word shifted right. A-register reassembled and sector counter appropriately incremented.
SRR: Split Right Word, Right Shift. Contents of A-register
encoded into split word format and middle bits and left word
protected while right word shifted right. A-register reassembled and sector counter appropriately incremented.
SLL: Split Left Word, Left Shift. A-register encoded into
split word format and middle bits saved. Left half word
shifted left; jump to SALI to reassemble A-register and adjust
sector counter.
SRL: Split Right Word, Left Shift. A-register encoded into
split word format and middle bits saved. Right half word
shifted left; jump to SALI to reassemble A-register and adjust
sector counter.
TRA: Transfer. Fetch instruction specified by transfer
ins-truction. Change active channel register.

TMI: Transfer on Minus. If contents of A-register positive
continue to next instruction. If negative execute TRA.
STO: Store. Correct operand address to allow for physical
placement of write head and store contents of A-register
at the corrected address.
HPR: Halt and Proceed. Type out PROGRAMMED HALT and proceed
only after GO has been typed into terminal.

Results of Execution Routine
Example of instructions were prepared as three-line programs with a
simulated binary display providing the output. Additionally, a longer
program was prepared and the accumulator monitored by a simulated octal
display. The results are too lengthy to present here but have proven to
be faithful copies of the machine results.

Utility Routines
As mentioned earlier the main program is supported by short simulations
of pertinent panel functions. The three programs in use to date are listed
in Figure 3. These programs treat the instructions and data as though they
were eight place, octal, whole numbers whereas the D17B number range is
approximately! 1.
MRC simulates the master reset function and presets· the I-register
to TRA to channel 0, sector O. The FILL Routine accepts the octally coded
instructions and data with the exact coding used in the actual D17B system
at the School of Aerospace Medicine. RUN places the computer into operation.
No equivalent to halting the comput~r by moving the switch out of RUN has
been implemented. Instead, the attention button is being used.

Conclusions and Projections
An effective simulation with considerable attention to detail has
been started for the D17B.
Three tasks remain to complete the task: 1) simulate the remainder
of the instructions, 2) include the flag store feature, and 3) include
the rapid access loops.
Following completion of the D17B simulation, a logical next step
might include an assembler to run on the D17B but designed on the simulation.

SET
SECTOR
COUNTER

FETCH & DECODE
INSTRUCTION
INCREMENT
SECTOR
COUNTER

FIG. l.a.

FLOWCHART FOR D17B

INCREMENT
SECTOR
COUNTER
NO

READ

OPERAND

YES
FLAG
STORE

EXECUTB
INSTRUCTION

FIG. 1. b.

FLOWCHART FOR D17B, CONT.

''>'4

.(...0

[2]
[3J

MACHINE
OP'l,X+-25pOPEHR
OPFX+-32pOPERR
OPC+-ZERO,SCL,TMI,OPERR,SMP,MPY,SMM,MPM,FORTY,CLA,TRA,

[4J

SECT+-l?127

[lJ

S~O,SAD,ADD,SSU,SUB

[5j
[6 J

IS:+(DI[2J=SEC~)/UECOUE

+IS ,SEC'l'+-128 I (S8Cl'+1)
lBCODE:DI+-, 16 2 128 32 128 TM[C;SE.'C:l'J
[8j
U+-DTO AR
[ 9]
SEC '1'+-12 8 I (S ECl' + 1 )
[luJ +(DI[O]€ 0 2 8 10 11)/NOOP
[11J CPER:S8CT+-128ISECT+l
[7J

[lLJ

+(DI[4J~SEC1')/OPER

[13J
lffl+M[DI[3];DI[4J]
[14J NOOP:+(DI[lJ=O)/UNPLG
[15J +UNFLG,pU+-'A SPORED'

[16] UNPLG:+OPC[DI[OJJ
[17J ZERO:OPZX[8,9,10,11,12,13,14,15,24]+SAL,ALS,SLL,SRL.

SAR,ANS,SLR,SRR,COA
[18J -t]PZX[DI[3]]
[19J SAL:ARSP+, 2048 4 2048 TAR
[20J MID+-ARSP[l]
[21J
ARSP+,2048IARSP x 2*DI[4]

[22] SAL1:AR+(8192xARSP[OJ)+(2048xMID)+ARSP[2]
[23] +IS,pSECT+128IsECT+1rDI[4]
[24J ALS:AR+16777216IAR x 2*DI[4]
[25] +IS,pSECT+128IsECT+1rDI[4]
[26J SLL:ARSP+, 2048 4 2048 TAR
[27J MID+-ARSP[lJ
[28J +SAL1,pARSP[OJ+2048IARSP[OJ x2*DI[4J
[29] SRL:ARSP+, 2048 4 2048 TAR
[30J MID+ARSP[lJ
[31J +SAL1,pARSP[2J+2048IARSP[2J x 2*DI[4J
[32J SAR:ARSP+, 2 1024 4 2 1024 TAR
[33] SAVE+ARSP[ 0] ,ARSP[ 2],ARSP[ 3 J
[34J ARSP+LARSPt2*DI[4]
[35J
AR+-ARSP[4J+(8192xARSP[lJ)+(2048xSAVE[lJ)+(SAVE[OJx«
2~(DI[4J+l)pl)x2*(23-DI[4J»)+(SAVE[2Jx«2~(DI[

4J+l)p1)x2*(10-DI[4J»)

Figure 2 . a.

Main Program

[36j+IS.pSECT+128ISECT+1fDI[4J
ARS:+(AR>8388607)/ARSl
+ARS2.pAR+LARt2*DI[4J
ARS1:AR+16777216-f(16777216-AR)t2*DI[4]
ARS2:+IS,pSECT+128ISECP+lfDI[4]
SLR:ARSP+, 2 1024 8192 TAR
SAVE+ARSP[0J,ARSP[2]
ARSP+LARSPt2*DI[4J

[37J
[38J
[39J
[40J
[41J
[42J
[43J
[44J

AR+SAVE[lJ+(U192xAHSP[lJ)+(SAVE[O]x«2~(DI[4]+1)p1)x

2*(23-DI[4]»)
[45J
+IS.pSECT+120IsECT+1rDI[4]
[46] SRR: ARSP+. 8192 2 1024 TAR
[47 J SA VE'+ARSP[ 0 J,ARSP[ 1]
[48J
ARSP+LARSPt2*DI[4J
[49J
AR+ARSP[2J+(2048xSAVE[0])+(SAVE[1]x«2~(DI[4]+1)pl)x

[50J
[51J

[52J
[53J
[54J
[55J
[56J
[ 57J

[58J
[59J
[60J

[61]
[62J
[63J
[64J

[65J
[66J
[67J

[68]
[69J
[70J

2*(10-DI[4]»)
+IS.pSECT+128IsECP+1rDI[4J
COA:+IS.pO+'COA'
SCL:+IS,pO+'SCL'
TMI:+(AR>8388607)/TRA
+IS
OPE'RR:+O,pD+'OPERR'
SMP:LSP+ 4 2048 TLR
AR S P+ 2 04 8 4 2 04 8 TAR
MID+ARSP[lJ
LR+ARSP[OJ+(2048xLSP[OJ)+(8192xARSP[2])
NRSP+ 20484 2048 TNR
SIGN+(ARSP>1023);.e(NRSP>1023)
PROD+(ARSPL2048-ARSP)x(NRSPL2048-NRSP)
LPROD+LPRODfSIGN[0]x2048-LPROD+(+/ 1024 2 512 TPROD[O
J)-512TPROD[0]
RPROD+RPBOVrSIGN[2Jx2048-RPROD+(+/ 1024 2 512 TPROD[
2J)-512TPROD[2]
AR+(8192xLPROD)+(2048 x MID)+RPROD
+IS,pSECT+128ISECT+6
NPY:SIGN+(AR>8388607);.e(NR>8388607}
LR+AR
PROD+ 8388608 2 4194304 T(ARL167.77216-AR)x(NRL
16777216-NR)
AR+PROD[ O]+PROD[ 1J

Figure 2 .b .

Main Program, Cant.

[71] AR+ARrSIGNx1G777216-AR
[72] +IS,pSECT+120ISECT+12
[73] SMM:+IS,pO+'SMM'
[74] MPM:+IS,pO+'MPM'
[75J FOHTY:OPFX[l,4,5,8,9,11,12,13,14,17,lB,19,20,
21 ]+BOC, BOA, BOB ,RSD, HPR, DOA, VOA, VOB, VOC ,ANA ,MIM. COM,
DIB,DIA
[76] OPFX[24,25,28,29,30,31]+HFC,EFC,LPR,LPR,LPR,LPR
[77] +OPFX[DI[3]]
[78] BOC:+IS,pU+'BOC'
[79J BOB:+IS,pO+'BOB'
[80J BOA:+IS,pO+'BOA'
[81J RSD:+IS,pU+'RSD'
[82J liPR: 'PROGRAMMED HAL'i"
[83J WAIT:START+~
[84J +«2tSTART)='GO')/IS
[85J +WAI'l'
[86J DOA:+IS,pU+'DOA'
[87J VOA:+IS,pO+'VOA'
[88] VOB:+IS,pO+'VOB'
[89] VOC:+IS,pO+'VOC'
[90J ANA:+IS,pAR+2~«24p2)TAR)A«24p2)TLR)
[91] MIM:+(AR>16777215)/IS
[92J COM:+IS,pAR+1G777216-AR
[93J DIB:+IS,pD+'DIB'
[94J DIA:+IS,pO+'DIA'
[95J HFC:+IS,pO+'HFC'
[96J EFC:+IS,pO+'EFC'
[97J LPR:+IS,pO+'LPR'
[98J CLA:+IS,pAR+ml
[99J TRA:+IS,p(pC+DI[3J),(pDI[2J+DI[4J)
[100JSTO:SECT+12BlsECT+l
[101J +(DI[4J~SECT)/STO

[102J +IS,pM[DI[3];(12BISECT-2)J+AR
[103JSAD:NRS+, 2048 4 2048 TNR
[ 1 0 4 JSAD 1 : AR S P+ , 2 04 8 4 2 04 8 TAR
[105 J i4ID+ARSP[ 1]
[106] ARSP+204B I ARSP+NRS
[107] +IS.pAR+(8192 xARSP[O])+(2048xMID)+ARSP[2J
[108JADD:+IS,pAR+16777216IAR+NR
[109JSSU:+SAD1.pNRS+2048-(, 2048 4 2048 TNR)
[l10JSUB:+IS,pAR+16777216IAR+16777216-NR

Figure 2.c.

Main Program, Cont.

VFILL[UJv
V PILL
[lJ
'PROCEED'
READ:L+I!]
en
[3J

~ox\A/(3pL)='END'

[4J
[5J

~«(-ltL)='/').«-ltL)='V'»/LOC.ENT

LR+OO TV ( 8 t - 9 t L)

[6J

~REAV

[7]
[8]
[9]

LOC:~READ,pIR+LR

ENT;ADR+ 32 128 TIR
M[ADR[O];ADR[l]]+AR+LR
[10J
IRS+ 131072 128 TIR

[llJ

~READ.pIR+(IRS[0]x131072)+128IIRS[1]+i

(a)

[1]

VMRC[ OJ V
MRC
IR+l0485760

(b)

VRUN[O]V
V RUN

[1]
[2J
[3]

DI+ 16 2 128 32 128 TIR
C+DI[3J
MACHINE
V
(c)

:fig!.lX"e 3. aJFill Routine, b) Master Reset, cl Run Routine

A Hardware Divider for the Dl7B Guidance Computer
by
Alfred M. Williams
The Boeing Company
Houston, Texas
and
J. D. Bargainer
University of Houston
Houston, Texas 77004

The Dl7B Guidance Computer for the Minuteman I, ICMB is capable of performing addition, subtraction and multiplication through
hardware algorithms.

However, division must be performed through

a software routine.

A hardware division c.apability can be acquired

by modifying the Dl7B operation codes and by incorporating additional hardware.
DI7B.

This paper outlines such a modification to the

The division algorithm is presented along with a description

of the hardware operation.

The divider is designed to perform

full-word and split-word division and determine a fractional quo~

tient and "remainder.

Both the quotient and remainder are' accessi-

ble to the programmer through the computer registers once the
operation is complete.
The Division Algorithm
A non-restoring division algorithm was desired that was capable of performing division. with either positive or negative num-'
bers in either the dividendi or divisor.

It was also desired that

the algorithm be easy to implement on the DI7B.

28
A divider; algori thm which

~ee:l:s

these r,equ;irements
is the
.
..

following fractional divide algorithm.
1.

Let ro

Let
q

=x
=

= q l oq2 ••• qn

To find x/y

ero is the first partial remainder)

1 if'ro and y have the same sign

otherwise

Iteratively

= 2r. 1+(1-2q.)y

r.~

lifr±_l and y ha,ve the same sign
q. =
:.
~O otherwise
:
"
~

The partial remainder r. isthere,fore found by, left
~

shiftingr i-1' ,and th,en ad;¢ling,,'yifr q'i is 0 and s:ubtracting y if qiis 1.
4.

;".,'

Repeat the ,i tera,tionn ,tJ.mes , or, Ul1,til ,the pal;"t.::.ial,
remainder is z'ero.'
000.~1

Add L

When r.~

When r f - 0 then correct the quotient by: 'addinSJ

to correct the quot,ier:t.

0 then q.

::::.

,1, and qj

1.000 ••• 0.

j.> i.

The divider algorithm implemented on the:D17B closely fol.,..
lows this outline; however, the last step in ,the process, correctionof the pse:udo q:uotient",is
correction

.factor~..

no~

perfo:r'med,by adding a

I,nstead., the sign digi,tis pomplemented and

a "1" is forced ,into the ,leas-.t ,sig:nifi,cant.::. dig.it.::. if the remainder
is non-zero.

The end resu .lt of this ,technique;is the same as

that acquired by adding the correction factor to the pseudo quotient.
The division operation designed for the Dl7B assumes that
the dividend is stored in the accumulator.

The division instruc-

tion is interpreted by the instruct.ion processor and a divisor is
loaded into the number (N) register from the specified memory
address.

At the end of the division operation, the quotient is

stored in the accumulator and the remainder is stored in the
lower accumulator.

This arrangement was chosen because the quo-

tient was desired after most division bperations.

In the case

where the remainder is desired, it is possible to transfer it
from the lower accumulator to the accumulator by loading alII's
into the accumulator and executing the ANA instruction.
It was necessary to add a delay flip· flop to the accumulator
to perform the left shift required by the division algorithm.

delay flip flop was aisoadded to the lower accumulator so that
the quotient digits could be stored in the proper order.
logic was designed to do each of the following tasks:

Control

(1) force

the least significant bit of the partial remainder to "0" prior
to each add cycle, (2) determine whether addition or subtraction
was performed _during the next add cycle, (3) determine the quo;...
tient digit and store it in the lower accumulator, (4) monitor the
accumulator for a zero remainder,
tient,

-(5)

correct the pseudo quo-

(6) count the number of shifts performed to determine when

the operation was completed.
The design took into account one more characteristic of the
DI7B.

The D17B operates on two types of numbers, full-word and

split-word numbers.

A full-word number is composed of 24 bits,

of which one bit is a sign bit • . A split-word number is composed
of two ll...,.digit numbers.

As a result, two different division

operation code.s were required, one that would perform
division and one that would

p~rform

fl1~l-word

split-word division.

Divider Design
The D17B has 16 .basic operation codes.
used.

All 16 codes are

Each operation code is determined by the state of

flip flops, 04, 03, 02, and 01.

th~

four

Four of the operation .codes are

used for multiplication, two are used for split-word and fullword "normal" multiplication and two are used for split- and fullword "modified" multiplication.

The mqdified multiplication op-

eration was redundant to.the normal multiplication operation and
was replaced by the division operation.
To delete the IImodified" multiplication operations, it was
necessary to modify the multiplication enable signals, OMO, OMF,
and OM.

Each of these signals enabled a period in the multipli-

cation operation and was modified by ANDing the 02 signal with
them.

During multiplication the 02 flip flop is.. used as the

addition/subtraction indicator to the carry/borrow flip flop, Ak.
The Ak flip flop was enabled for addition if 02 was true and for
subtraction if 02 was false.

This function could no longer be

performed by the 02 flip flop and a' spare flipflop replaced
it.

After these modifications were completed, two operation

codes were available for
04 03 02 01,

0'4

(34)

division'~

The operation code',

was us'ed'for' full-word division and,

03 02 01 (30), was used for split-word: division.

The 01

flip flop was used to distingu'ish"be'tween:"full-word and
split-word division.
The operation codes chosen'for division" maintained two of
the "modified" multiplication operation' characteristic's.

First,

the number located at the specified memory address wasautomatically loaded into the N register during the first cycle of division.

Second", the Q flip flop was one set at the end of the

first word time of division.' A spare flip flop in the computer,
labeled the DIV flip flop, was used'to designate .the division
operation.

The first word time of division was indicated by the

signal (DIV

Q).

signal (DIV Q).

All

remainin(~r

word times' were indicated by the

The D flipflop was' u'sed to 'separate the middle

word times from the last word time.
A word time counter is initialized during'thefirst word time
of 'division.

The counter is composedofthe'CB,5--CBlflip flops.

These flip f lops" are des igrted' to coun tdowna t Tptime.' , They are
initialized to (24) or (11000) 2 for full-word, division and (11)10
or (01011)2 for split-w6rd division.

At Tp time of the first word

time the, accumulator recirculation 'control flip. flop, Ac, is set.
This disables normal recdrculation o£ the accumulator flip flops
and makes it possible for the, accumulator to be extended by one

32
bit.

The one bit extension creates. the one bit shift required by

the divide algorithm.

Also, at Tp time of the first word time, the

lower accumulator recirculatioI) control flip fJ.op, Lc, is set.
This disables normal recirculation Of tl1.e lower accu;m,ulator flip
flops and makes it possible for the lower accumulator. to be extended by one bit.

The lower accumulator is used to store the pseudo

quotient and the one bit delay is required so that the quotient
bits will be stored in the proper order.

During the first word

time of division, the divisor is loaded into the N
memory_

regis~er

from

A spare flip flop designated the N2 flip flop CopiE:sthe

sign of the divisor loaded into the N register.

The sign of the

divisor is compared with the sign of the. number in the accumulator.
If both signs are the same the

differ, the N2 flip flop is reset.

flip flop is set.

the signs

After the N2 flip flop has com-

pleted this operation, it indicates whether addition or subtraction
is performed during the next add cycle.

It also indicates the proper

pseudo quotient digit.

This logic isoperatipnal only if a non-

zero remainder exists.

If a zero remainder does exist, then the N2

flip flop logic is modified so that the flip flop is set at the next
compare time and reset for all remaining modify times.

The C5 flip

flop performs a delay so that the detected addition/subtraction
operation information will be available during the add cycle.

copies the N2 flip flop at TI time during full-word, division and
at Tp and Tl2 time during split-word division.
During the middle word times the dividend, located in the
accumulator, is shifted to the lei't and the divisor, locC'l.ted in

the N register, is subtracted from or added to it.
The shift of the dividend is performed by adding a delay
flip flop to the accumulator.

The C4 flip flop was used to

provide the required one bit delay.

Extended Accumulator

Logic for the C4 flip flop is designed so that it will
copy the Ax flip flop.
The Ap flip flop is designed to copy the C4 flip flop.
A23 flip flop copies the A24 flip flop.

The

The A24 flip flop is

designed to function as the adder/subtractor flip flop during
division and theAk flip flop is used to determine the carry or
borrow.

Addition/Subtraction time is determined by the Nl flip

flop (a spare flip flop).

The add cycle is initiated at T2 time

and continues through Tp time for full-word division.
word division the cycle occurs from T2
time.

For split-

T13 time and TIS - Tp

If a zero remainder exists, the add cycle will not be

initiated.
The SB3 flipflop is used to copy the adder flip flop and
determine if a zero remainder exists.

It is reset prior to each

add cycle and set whenever the A24 flip flop is true.
The J and C2 flip flops are used to store the remainder
status.

Both flip flops are initially reset during the first

word time.

The J flip flop determines if a zero remainder exists

in the least significant split word during split-word division.
It. copies the SB3 flip flop at T13 time," during spli t-woiddivision and the C2 flip flop during full-word division.
The C2 flip flop determines if a zero remainder exists
during full-word division or in the most significant split word
during split-word division.
time.

It copies the SB3 flip flop at Tx

The lower accumulator stOres the pseudo quotient 'gener-

ated during the middle word times of division.

It is extended by

one bit through the addition of the C3 flip flop.

Extended Lower Accumulator
The one bit delay is required if the pseudo quotient digits
are to be stored in the proper order.

The loop re.circulation

control flip flop for the lower accumulator, the Lc flip flop,
has previously been set during the first word time of division,
so that the C3 flip flop can copy the Lx flip flop at the beginning of the second word time.

The C3 flip flop is also de-

signed to function as the quotient flip flop, that is, the C3
flip flop is responsible for decoding and injecting into the lower
accumulator the pseudo quotient digit.
place at To time for full-word division.

This detection takes
It is accomplished by

requiring the C3 flip flop to copy the N2 flip flop.
During split-word division, the pseudo quotient is detected
at TO and T13 time.

At these times, the quotient digit 1.S stored

in the C5 flip flop and it is necessary for the C3 flip flop to
copy the C5 flip flop.

When the C3 flip flop is not detecting a

quotient digit, it copies the Lx flip flop, as previously stated.
The Lp flip flop is designed to copy the C3 flip flop during
division.

The L24 flip flop copies th Lp flip flop during divi-

sian.
The operations just discussed are performed recursively during the middle word times of divisiono

At the end of this period,

the pseudo quotient digits are stored in the lower accumulator
The remainder is stored in the accumulator

During the last word

time of division, the pseudo quotient is corrected and transferred to the accumulator and the remainder is transferred to the
lower accumulator.
The remainder is transferred from the accumulator to the lower accumulator by having the Lp flip flop copy the Ax flip flop.
Correction of the pseudo quotient is performed by the A24 flip
flop and the C3 flip flopo

The A24 flip flop is responsible for

complementing the sign digit of the pseudo quotient.

It comple-

ments the Ap flip flop at Tp time during full-word division and
at Tp and T12 time during split-word division.
The least significant digit of the pseudo quotient is forced
to "1" by the C3 flip flop if the remainder is non-zero.

During

the last word time of division, the C3 flip flop is set or reset
at TO time for full-word division and at TO and Tl3 time for splitword division, depending on the remainder being non-zero or zero
respectively.

The transfer of the pseudo quotient from the lower

36
accumulator to the accumulator is performed by the Ap flip flop.
It copies the C3 flip flop during the last word time of division.
At the end of the last word time of division, it is necessary
to reset the recirculation control flip flops for the accumulator,
Ac, and lower accumulator, Lc and to reset the DIV flip flop.
The logic to implement the division algorithm was constructed
on three cards with the same size and shape as the logic cards of
the D17B.

All flip-flops used in the modification were spare

flip flops already in the computer and only gating logic was added.

Approximately 350 diodes were used on the three cards.
Complete documentation of this modification including, wir-

ing lists, circuit diagrams and negatives for etching the boards
is available and we would be happy to send this documentation to
anyone requesting it.
Bibliography
Yaohan

Chu, Digital Computer Design Fundamentals, McGraw Hill

Book Company Inc., 1962
Autonetics, Minuteman Computer Logical Description Engineering
Manual 2065

14 January 1960

Air Force, General Purpose Digital Computer
llG2-10-5-3-5

Technical Order

December 1960

Air Force, Digital Computer Electronic Modules
llG2-10-5-3-l0

15 October 1962

Technical Order

STATE DESCRIPTION OF Dl7B COMPUTER
Gary B. Lamont
Capt DouglasJ. Allen
Electrica.l Engineering Department
Air Force Institute of Technology
Wright-Patterson Air Force Base, Ohio

45433

ABSTRACT
This report presents a state description of the D17B Computer. A set
of control flipflops were chosen and from this choice the states of the

computer Were defined. The discussion of each state includes a set
register transfer equations that enumerate the information transfer during
that state.
This approach was taken to present a compromise between a simple veitch
diagram of the computer modes and a complete listing of the logic equations
for the computer. Hopefully, this description will not only be a graphic
study plan of the machine, but also an aid for maintenance and trouble
shooting.
Introduction
A state description of the D17B Computer is a method of portraying the
functional operations of the computer using the configuration of the control
flipflops •. A given configuration of the control flipflops is defined as a
state of the computer and the paths between the states represent the functional
operations. A set of register transfer equations that outline the information
transfer between registers may be added to complete this description.
This approach is used for computer synthesis by Chu (Ref 2: 396-429) and
is one basic method of. modern computer design. As an analysis technique this
method places the burden of defining which.flipflops are to be considered as
control flipflops on the analY~er~ After this decision is made, the process

is straightforward.

In this presentation two primary considerations were used

to choose the control flipflops. First, an effort was made to define the
states so that the state description would parallel previous descriptions of
the machine. Secondly, the control flipflops were chosen to make the descriptionlas simple and concise as possible.
A state description offers three advantages: (1) it presents a systematic
way to study the machine, (2) the description presents a definite path to follow for maintenance checks, (3)
veitch diagram presentation.

this method presents more detail than the

State Description of the D17B
Operation of the D17B may be described by considering the various configurations that the control flipflops enter when the machine is executing a
program. Thus, a state of the machine is defined by a particular configuration
of the control flipflops. States may be represented on a diagram which depicts
the various paths that the machine may cycle through during program execution.
This state diagram may be used in conjunction with a description of the information exchange between registers to completely describe the machine operation.
State descriptions have the advantages of being a visual description, thus
easily understood and capable of displaying large amounts of information in a
concise form. Even more important, the state diagram provides a systematic
approach for describing how the computer functions.
Register Transfer Notation. In order to conVeniently describe how information is transferred between registers during each state, it is necessary to
adopt a type of shorthand convention to condense the description. The symbols
usually used in this notation are an adaptati~ of the system used by Chu,
Ref 2: 378.
State Diagram. In this report the states of the computer have been broken
into two major classes or modes, Compute (K) and Non-compute (K'). The states
in these classes are represented by nodes (circles) and are numbered with an

identifying number. Configurations of the major control flipflope which cause
transition between states are listed beside the transition path on the diagram.
Associated with each state diagram is a table which lists the state by number
and name and 'the information transfer which oocurs durinc that statee The
Non-oompute states are displa7ed in fils. 1 and 2 aDd Oompute states are shown
in Figs. " 4, and 5. The associated rapster tranafer notation. for these
state diagrams can be found in Ref 6. Thlllreferenoe oan be obtained from the
Defense Documentation Center.

Ion-P2!Quta Sktta. RafOl ,6)

(4, 1.1 - 2.15)
Power On :Random State. lIten powel' is applied to the D17B, the oontrolling
and

flipflops Will beoome aotivated in a raDdOll state. Depr••aine the "MA.8'l1R
RESET" swi toh oauses the computer to enter a Prepare To aperatestate where
in! tialization 18 begun. a.en, 1.
PtOPW to Qp'tAii (nl). In this state the pba.e register 18 b11 tls.lized
to an 1dle mode.. '0 1a turDed ott to prevent the oOllpUter trOll ante:ri:QI a
speoial state called fine oountdOWi1. The m.orete output oo.trol reei.ter i.
1m tiallzed to prevent randoa diacrete output. and variou. other tl1,f'lopa are
in! tlalized to start the 81f1ChrordlaUon of the b1 t oounter wi tit the .eotor
traok. 00ntro1 flipflop. 02 and J are Olle let to allow traas1 tion to the
S7fto Bit Oounter 1 state.

sue Bl~goWl'" 1 (n2).

Thi. state i8 the ••cond I!l'tate duri. whiob 8711ohronisation to the Bit. Oounter and the Seotor Traok i. aooolllpl1sb.ed. AI
shown on the state 41&12'_,. traa.leut .11I.ter rea.t .11Dal (1... tban ona
memory revolution in duration) v.11l caUSe tbe_cbine to reOJ'Cle throurh
tbe hepare To Oompute Stat.. The 01 flipflOP i. ft ana" .et allowinc entr,r
into the next .tate, S;Jr1O Bit Oounter 2.
§Do Btt Couphr , (n3)~ In this state the inatruotlonr.,iater i. loaded
v.l. th an unoohdi tional jump itu.truotion to ohannel 0, I.otor O. Thi. instruction
v.l.ll be the first 1nstt,totiQlt lflteouW unlel. a nttV instructiotl ia loaded prior

random state at power on

'--.

Fi,-.4. D·118 NOllcompute States

to the computer entering the compute mode.
After complete synchronization of the bit counter and the sector track~
the Rc and 01 flipflops are VI zero" . set allowing transition to the Manual
Halt-Idle state.
Manual Halt-Idle 1 (n4). This state acts as a decision point for
state transition. Three separate situations will cause the computer to
enter the Manual Halt-Interlock state. If the previous state were n3 or n7,
then state n4 was entered at a bit time corresponding to T of sector number
x
0; thus~ the 04 flipflop will be "one" set prior to the occurrence of any
other state determining transition.
A third situation which could ~ause transition from n4 to n5 arises
when the computer control awi tch is placed into "Hal til or "Single Step"
during a compute operation. State n4 will be entered from Program Halt
and transition will occur to state n5 or n7 depending on the 01 flipflop.
This state transition is not predictable since the 01 flipflop state will
be determined by the instruction that was being executed when the compute
switch was placed in the Halt or Single Step. State n7 maybe the next
state entered if the previous state was n5. In this case n4 Was entered
at a bit time corresponding to T1 of sector 177 thus allowing the 01
flipflop to be "one" set.
State nB, Prepare To Compute, will be entered if the IICompute ll
switch is not in a "Halt" position and Sb2 is zero set. Sb2 is a flipflop
that is one set as the result of a verify or parity error.
Manual Halt-Interlock (n5). If there is no Mechanical Reader Input
il
Signal (1*1)
m present or if a "Halt command is present from the IICompute
Switch or if a Sprocket timing interlock signal (T*!) is present with no
Fill Signal, the computer will cycle between states n6 and n5. Similarly,
a cycle will exist throughn7~ n4, and nS if a Mechanical Reader Input
signal is present with no Fill signal (F*). "Wait" state, n9, will be
s
entered if a Fill signal is present. Thus, Manual Halt-Interlock, nS,
acts as an interlock for the state transition prOCeSS of the computer.

Manual Halt - ~epare to toad (n6). ~epare to Load state is entered
if a device such as a photo reader is used for loading. From this state,
transition will be back to n5 if a Sprocket Timing Interlock signal (T*')
is present or to the Wait state, n9, if no T*r signal is present.
ManuaJ. Halt - Idle 2 (n?). The Manual Halt-Idle 2 state serves as a
timing delay. From this stat~ the computer will enter n4 if the compute
swi tch is in the "Halt" posi tion and/or a Parity Error has occurred e If
,no parity or verity errors have occurred, the next state will be nB, the
Prepare to Compute State. In the event that a Fill signal (~) occUrs,
the next state will be n9.
Prepare to Compute (nS). In the Prepare to Compute state initialization of several flipflops is accomplished in preparation for entry in
the Number Search State of Compute. J must be "one" set allowing the D
flipflop to be "one" set. Then when agreement is reached between sector
track and the Number Register, K is "one" set.
"Wait (n9). Flipflops are initialized to receive the Input Load code
in the ~it State. The computer will cycle between this state, n9, and
nlO,Prepare to Sample, until the Sprocket Timing Interlock signal, T*',
has reached steady state. If a verify error occurs, the Idle 2 state will
be reentered.
Prepare to Sample (nlO). The primary purpose of the Prepare to Sample
state, nlO, is to allow the Sprocket Timing Interlock signal to reach steady
state as described above. When this occurs, the computer will remain in the
Prepare to Sample state until bit time T23 occurs and will then transition
to the Sample state, nll.
Sample (nll). During the Sample state, the computer will load the
information on Input Lines Il* through I 5*. Note that flipflops C I
.
P
through Cp4 were ·!'-zeDoH-,"set in state n9 and will be "one" set only bY,an
I* input. At bit timeT13 the computer will enter the Parity Check state.
Parity Check (n12). Flipflop Sb3 will toggle on Cpl as Cpl through
Cp4 complete a circular shift. This circulation will occur on each bit time

when the 04 flipflop is "one". set. In order to insure circulation for only
five bit times the 04 flipflop is. "one" set on bit time T;;Wand "zero" set
on bit T24" "One" setting the CpS flipflop will allow a change to one of
the Process Code states depending upon the contents of the Input Lines.
Process Code-Clear (nl). The clear load code C.Ruaes the Lower
Accumulator, L, to be filled with zeroes •. "One" setting the L flipflop
c
allows new information to be. read into L st~rting with bit time TO. Then.
the CpI flipflop is flipflop is "zero" set preventing new information from
being read into the L-Ioop.lfa parity error is indicated by a Sb3 at bit
time Tp the next modewill.be n9;however, if no parity error occurs, the
computer will bo to state n7, the Wait state.
Delete (n14).
by the computer ~

When the input lines are all "ones" no action is taken
Th7.s command can be used as a space in input tape.

All

"zeroes" is not used as a Delete command because the Sb3 flipflop would
indicate a parity error.
Prepare to Fill State (nlS). The Prepare t.o Fill state is a preparation state for filling the memory. After the Fill command is processed,
the succeeding Load codes will be loaded into memory until "Halt" or "Start
Compute" commands are processed. In the event a parity error occurs, the
next state will be n7; if no parity error occurs, n9 will be next.
Prepare to Verify (nl6). The Prepare to Verify State is analogous to
the Prepare to Fill State. Once the computer cycles through this state
(caused by processing a l?ad code IS' 14 13' 12 II) the succeeding load
codes will be compared with the contents of memory as specified by the
Instruction Register.. This actual operation will be executed as the
result of an Enter command will therefore be described as part of the
Enter state. Exit from this Prepare to Verity is similar to that of the
Prepare to Fill state.
Octal Numbers (nl7).In this stat~ the oct~l numbers received from
the input lines will be .!3tored in the L register. Any number of octal

44
codes may be loaded but only eight sets of octal digits may be stored in
the Lower Accumulator at one time. Octal Numbers that are shifted out of
L are lost. Exit from this state is similar to those of the other Process
Code states.
Location (nlB). In this state, nlB, the contents of the L register
is transferred to the instruction register. This information will contain
the memory location, channel and sector number, that will be used to start
Fill and Verify operations.
The Ic flipflop is "one" set at bit time TO allowing new information
to be written in the I register, then it is "zero" set at bit time T24
after L is transferred to I.
Enter (nl9). In this state, nl.7, the contents of Lower Accumulator
will be loaded first into the accumulator, then into memory if a Prepare
to Fill state had initiated a fill operation or the contents of the
Accumulator and Memory will be compared if a verify operation had been
initiated by the machine cycling through the Prepare to Verify state. The
location of memory involved in the above operation is specified by the
Instruction Register. If a parity error is detected, transition will be
from nl9 to n7, otherwise an error-free operation will allow the computer
to go from the Enter state to the Wait state.
At this point it is necessary to define a set of four states that the
computer cycles through during a Fill or Verify operation. (A Fill or
Verify operation results after the computer has successfully cycled through
the Prepare to Fill or Prepare to Verify states and will continue until the
Halt or Start compute state is reached). These four states are called
Fill-Verify Idle, fvl; Fill-Verify Number Search, fv2; Fill-Verify wait 2
Word Times, fv3 and Fill-Verify Execute, fv4 and the computer cycles through
them simultaneously as it passes through the Enter state. A state diagram
of this four-state operation is depictedfffi~g. These states will be
discussed in conjunction with the Enter state since they occur simultaneously

GE/ EE/7 2S·2

Fig.

'i.

Non compute FiII-Verify States

beginning in the Enter

state~

The action taken by the computer will vary

with the part of memory that is to be filled or verified, thus it is necessary to consider not only the Enter state and the four-state cycle described
above, but also the part of the memory involved in this operation must be
considered.
Fill-Verify Idle (fvl).

During the Fill-Verify Idle state the Lower

Accumulator is copied into the accumulator. "Zero" setting the D flipflop
causes transition to rv2, the Number Search State. This transition occurs
simultaneously with a transition from nl9 to n9 states.
Fill-Verify Number Search (rv2).

During this state agreement is

established between the Sector Track and the operand sector part of the I
register. This comparison is made by the 0b2 flipflop during bit times
T2 through T7" . The operand channel part of the I register is copied into
the C register and channel agreement is established. The D and E flipflops
p
are "one" set to caUSe transition to the Wait 2 Word Times state.
Fill-Verify Wait Two Word Times (rv3). During the Wait Two Word Times
state, the Channel Buffer is copied into the Channel Register. The Number
Register copies the contents of memory as specified by the Channel Register.
"Zero" setting the D flipflop causes transition to the Fill-Verify Execute
state.
Fill-Verify Execute (fv4) •. Fo:r both Fill Verify operations, the operand sector part of the I register will be augmented by one in this state.
For Fill operations the contents of the Accumulator will be transferred to
a memory location as specified by the Operand Address part of the I register. After the Fill operation, transition is made to the Fill-Verify
Idle state. Verify operations are different in two ways. First, the
contents of the Accumulator and the Number Register are compared. If
agreement occurs Sb2 flipflop will remain" zero" set and the next state will
be fvl. Disagreement is indicated by Sb2 "one" setting and the next state
will be a Manual Halt state.

Halt (n20)o When the "Halt" code is processed, the Halt state will be
entered and the V flipflop will be'''zero'' set causing a transition to the
c
Pcrogram Halt state.
Start Compute (n2l). The Start Compute command when entered on the
Input Lines will cause the computer to enter the Manual Halt Idel 1 state
before transitioning to the Prepare to Compute and Compute states. ' If a
parity error occurred while processing the code, the computer will not
transition from the Manual Halt states.
Program Halt (n22). Four separate conditions may cause the computer
to enter n22, the Program Halt state. If a "Halt" load code is successfully
, processed in, the computer will enter n7 before returning ,to Manual Halt
Idle, states.
Secondly, a halt instruction may be executed in the Compute mode or if
the Compute Switch is not in the "Run" posi tionwhen a new instruction is
found the computer will return to Program Halt state from the "Last Word
Time State" of Compute.

Also, if during the Number Search state of compute

, the "Compute Switch" is not in "Run" and an, instruction search is required '
to locate a new instruction, the computer will enter n22. In all cases the
computer prepares to enter' one of the Manual Halt Idle stat"es during the
Program Halt state. The actual Idle state entered depends upon the state
of the 01 flipflop which was set by the instruction being executed when
state n22 was entered.
If state n22 were entered as the result of processing a Halt command,
during a Fill or Verify operation, the D and E' flipflops will be set to
caUSe the computer to simultaneously enter the Idle state of the FillVerify operation.
Compute StatesG Ref (3: 25)
The Compute mode of the
flops. Th~ K flip:f,'lop~ when
one of, the "Compute" states.

and (4: 5~i - 6.13)
D17B is controlled by seVen major control flip"one" set, indicates that the computer is in
The various states of Compute are then!

GE/EEI72S·;!

From Prepare to Compute

Fig.S ' O.17B Compute States

controlled by the D and E flipflops. When the E flipflop is "one" set
an instruction is being executed. The D flipflop, when "one" set, indicates that an instruction search is in progress and when" zero" set
indicates instruction read and/or operand search is in progress. The

four flipflops of the Operand Storage Register, 0 through 01' determine
the instruction that will be executed.
Instruction Search State (cl). The Instruction Search State as
defined in this report will be the state indicated by the flipflop
settings K D E'. It is not necessary for this state to occur with the
execution of every instruction.
If a program is optimally coded, a new instruction can be read into
the I register during the execution of the present instruction. In this
(.

case, the instruction search operation was performed as a result of forethought of the programmer. Similarly, the Instruction Read-Number Search
state may also be avoided by astute programming. In this case the computer
would cycle between the two states of Execute without actually performing
an instruction or operand search.
Instruction agreement occurs when the memory location addressed by
"next instruction" part of I is in a position to be read by the computer.
Monitoring for this condition is performed by the buffer flipflops ObI
and 0b2. These two flipflops a:re monitored by the Id flipflop which
controls the D flipflop. When the D flipflop becomes "zero" set, transition to state c2 occurs.
Instruction Read-Number Search State (c2). Instruction Read-Number
Search state, c2, is a dual function state defined by DE' flipflop conditions. Like the Instruction Search State, this state may not necessarily
be realized with the execution of every instruction. One-half of the dual
function of the state may be exercised. For example, the next instruction
may be found and read during the Execution state and the computer. may cycle
to state c3 for the Number Search function alone.

For number agreement the information in Ip at bit times T2 through
T must agree with the Sector track, S. Since the loops are effectively
g
separate channels of' 4, 8, and 16 word length, more than one f'lipflop is
needed to check agreement for all channel elngths.

Flipflop 0b2 monitors

for agreement for the 4 word loops, ObI monitors for 8 word loops, Sbl
for 16 word loops and 0b.3 monitors for the full channel length, 128 words.
TheNd flipflop is the primary number agreement monitor and is changed by
the above number agreement flipflops at bit time Tl.3"
Instruction Read is accomplished by setting the desired memory channel into the Cp5 through Cpl flipflops. When flipflop Id indicates
Instruction agreement, the I f1ipf'lop is "one" set allowing the new
c
instruction to be read into the I register. Bits I24 through 121 are read
into the Operand Buffer Register, and 112 through I8 are read into the
channel buffer register. If the instruction is a flag-store instruction
(I 20::o1) the flag channel information, I 19 , I 18 , and I17 is read into the
Flag Dade Buffer Register. If the instruction is not a flage-store instruction, the Flag Code Buffer Register is loaded with "zeroes".
From this state, c2, transition will be to one of the instruction
execution states or to 01 in the case of the transfer on minus instruction
with a positive accumulator (see state c4 description). If the Compute
Switch is not in the "Run" position when the I flipflop is "one" set to
c
read a new instruction, the computer will go to Non Compute Program Halt,
n22.
Last Word Time of Execute (0.3). The Last Word Time of Execution, c.3,
will be discussed in conjunction with the execution of each of the instruction states since during this state the operation started in each of the
instruction states is completed. For all one-word-time instructions (04=1),
the instruction defining state is entered for the first bit time of execution
and then the computer transitions to c.3 to complete the operation.
This state acts as a decision point for the computer to exit the Oompute

Mode. If the Compute Switch is· not in the· "Run" position and a new instruction is fOUnd,the computer will go to state n22, Non Compute Program Halt.
Unconditional Transfer (c4}. The word format of the D17B makes no
provision for specifying the channel of the next instruction. Thus, there
must be a command to change· channels of operation. The Unconditional
Transfer is a "jump" instruction that is used for this purpose. In this
"jump" instruction the sector of next instruction field is ignored and the
complete operand address Serves as the address of the next instruction.
The new channel address is contained in the Operand channel portion of the
transfer instruction. This information was shifted to the program channel
tfurfer register during the instruction search operation. At bit time TO
:t:Q.e
program Channel Buffer Register is parallel loaded into the Program
.".'
Channel Register.
-,

'.:

,,""

Instruction agreement is controlled by the nUmber agreement flipflop
which determines the sector of the new instruction from bits 17 through II
of the present instruction.
'Conditional Transfer (c5).The decision for the Conditional Transfer
operation is made in state c2. If bit A24 lszero, the accumulator is
positive and the computer returns to state c1 to search for the instruction
as indicated by 5p [IJ. A "I" ·lli!::bit position A24 indicates that the accumulator contains a negative number and the computer goes to state c3 and
selects the new instruction as indicated by 0[1].
Store Accumulator (c6). The Store state must be considered for four
different situations; storing in channel 50, storing in channels 00 thru
46, storing in the loops, and flag storing.
Storing in charinel'O or "Hot storage writing" is initiated by setting
the S{ flipflop to the channel 50 store code, then the Accumulator is copied
directly intochB.nnel
and in a sector two octal-numbers less than the
sector of SCI]. This two sector difference is accO'unted for by the fact
that the write heads are separated i'rom theread·heads by two sectors.

In order to store information in channels 00 thru46 an EWC signal must
be present, enable write switch must be on.
46 the computer utilizes a separate selector
selection is accomplished using the contents
The Accumulator is then stored in the memory

for selecting channels 00 thru
switch for each channel. This
of Channel Storage Register.
address specified by the OP[I]

minus two sector positions.
Storing in the E, F,H loops is similar to storing in channel 50
except the S.1. flipflops are set by the contents of the channel buffer regisStoring in the V and R loops may be accomplished if the computer is
not in Fine Countdown mode (F =1) (See state 017). In this case, the
o
contents of A is added to the incremental input at the time of execution.
A special case results when the T20 bit of any instruction is "l".
This "flag", "lI' in T20 is used to execute two operations with one instruction. The contents of the Accumulator will be stored in the channel indicated by the contents of bits 119 thru 117 This means that the sector of
next instruction field of the instruction being executed is limited to the
four bits 116 thru 11 .3 and the next instruction must be wi thin the next 16
sectors. Flag storing is accomplished in the following steps: The Flag
0

store buffer register Sb is loaded with :the contents of 119 thru 117 during
state c2.During the execution of the instruction the Flag Store Buffer
register is parallel-loaded into the flag store register. This information
is used to select the proper write heads for writing the Accumulator
contents into memory.
Clear and Add ((7). State c7 initiates the clear and add operation,
in which the contents of memory as specified by the operand address is
transferred to the ACCUlllulator. In state 07 the N flioflop is "one" set
c
allowing the selected contents of memory to be read. into the Number register. In state 0.3 the operation is completed, the selected contents of
memory is read into the Accumulator.

Add (c8). State 08 initiates the add operation in which the memory
contents as specified by operand address is added to the Accumulator.
The sum is then stored in the Accumulator.
Subtract (c9). Subtraction is accomplished by the hardware as
addition in the D17B; however, the carry operation of addition is converted to a borrow operation by a "one" in the 02 flipflop.
Split Add (cl0). During the split add operation the split word
contents of the Accumulator is added to the corresponding parts of memory
and the sum is stored in the split word portions of the Accumulator. At
bit times T12 and Tl.3 the Ac flipflop is "zero" set allowing the contents
of A12 and Al.3 to remain unchanged.
Split Subtract (ell). The split subtract operation is similar to the
split add operation, except that the split word contents of memory location
specified by O[IJ is subtracted from the contents of the Accumulator.
X Special State (c12). No action is performed in the X special state.
It serves only as a decision point for the computer to enter a special set
of states that require one word time to complete and do not require access
to the computer memory. The Channel Storage Register contents are used to
select the X special state that will be entered from c12. In this special
operation the channel storage register serves as an auxiliary operationcode storage register. Since all the X special operations are one word
time instructions, the specific X special state serVes to define the operation and much of the actual operation is performed in state 0.3.
'Complement (013). The complement operation causes the 2's complement
of the Accumulator to be read into the Accumulator. The Accumulator is
circulated and the Ac flipflop is "one" set by the first "one" in the
Accumulator. All succeeding bits of the Accumulator are complemented.
Minus Magnitude (c14). When the computer enters the Minus Magnitude
state, 014, the sign of the Accumulator is tested. If the Accumulator is

GEiIiEI7CS.~

Fig.

X-Special Compute. States

negative no' action is taken; if the Accumulator is positive the Cbl flipflop,
is "one!! set and copied into ,the Cl flipflop, thus generating a complement
instruction.
Logical And to Accumulator (c15). Entering state c15 causes the
correspondig bits of the Accumulator and Lower Accumulator to be logically
"anded".
Enter Fine Countdown (c16). Entering the Fine Countdown causeS the
Fc flipflop to be "one" set. This places the computer into a parailel operation called Fine Countdown. During Fine Countd:own the V and U loops fomi a
digital integrator.

This operation will continue until the Halt Fine Count-

down state fs entered.
Halt Fine Countdown (c17) • Entering the HB.lt Fine Countdown state, 617,
causes the Fine Countdown flipflOp, Fc , to be "zero" set.
Reset Detector (c18).

When the Reset Detector state is entered, the

Dr flipflop is "zero" set. . The Dr flipflop is '" one" set by I~.
Halt and Proceed (c19). Entering state c19, Hand and Proceed causes
the computer to enter state cJ and then state n22, Program Halt.
Load Phase Register (620). The Load Phase Register special instruction
causes C2 to be loaded intp P2 and Cl is copied into P20 P3 copies the I~
flipflop at bit times Tl through T5 • State c20 is defined by three of the C
flipflops, C5; C4 , and C3, the rema1ning two C flipflops may be either "one"
or "zero" set. The actual purpose in setting the Phase Register will be
discussed in conjunction with state c~7.
;,
Binary-Output (c2l, 022,02J). Binary Incremental Output states may
be discussed simultaneously. These states differ only in the sense that
state 021 involves output flipflop Gl , c22involves G2 , and c2J involves
GJo Only the first'state, c21, will be discussed because the discussion
is directly applicable to all three states b.Y substituting the proper G.~
flipflop in state c2i, where 1=1, 2; or 3.
In state c21 the state of the Gl flipflop is checked. If Gl equals
.'

"1" the first eight bits of A are treated:as' a word and +1 is added ,to that
word. If Gl equals "on a liS subtracted from the word formed by the first
eight, bits of A. After one of the above operations is accomplished, the
Gl flipflop copies the sign bit of A.
Discrete Inputs (c24, c25).In both discrete input operations 'a set
of twenty-four discrete input lines and flipflops are sampled and read into
the A register.

For a Discrete Input A,.DIA, operation the discrete input

lines Xl through X19 and flipflops Dr' Fc' P3, PI' P2 , replace bits Al
through A24 respectively.
During the operation initiated by state c25, DIB, the discrete lines
Yl through Y24 replace bits Al through A24 respectively. The actual information transfer described in. th.ese states ~kes place in state c3; however,
the states c24 and 025 serve to,define the operation to be performed in
state c3.
Discrete Outputs (026). Theoperati.n initiated by state c2, Discrete
Output A, causes the bits II through I5 to be loaded into the Discrete Output Register, Dl through D5"
Voltage Output (c27, c28, c29). The Voltage Output states are identical in concept. The function of these states varies only in the phrsical
location of the.output voltage.
Three Voltage Output Registers are loaded with the split word contents
of A. If I4 is "1", ,the right half of A is loaded and if I4 is "0", the left
half of A is loaded.
The states c27, c28, and c29 determine which set of Voltage-Output flipflops, ViI through Vi8 , (i=l, 2, or 3) will be loaded from A. If c27, VOA,
is entered VII through V18 will be loaded; c28, VOB, causes V21 through V28
to be loaded; and c29, VaG, causes v31 through V38 to be loaded with the
proper half-word of A.
The Phase Register also affects the output location of each voltage
line.

57
y Special Stat~ (030). The YSpecialstate~ 030, Serves only as a
decision point for entering specific states 031 through 038. Operations

initiated by the Y Special state do not require a.ccess to Memory; howeVer,
they do require more than one word time to complete.
Accumulator I,eft Shift (031) •. A left shift operation is accomplished
in the D17B by a.dding an extra flipflop, Ak , to the A loop for the num1;>er
of word times equal to the number of i3hifts required. The number of shifts
.. is specified by II through c15" This number is loaded into the Channel
Buffer Register aDd counted down at each word time.
Accumulator Right Shift (c32). State c32 ini tla,tes a right shift of
the Accumulator. To accomplish this operation, the A flipflop is reIDOIted
p
from the reci.rculation loop of the Accumulator. The number of ri.ght sifts
required is indicated by II through 15 and-the A flipflop remains out of
P
_ _
the A loo:p for that number of word times. If the Acc:umula tor is posi ti ve,
zeroes are filled into the vacated bits; however,if the AccuniUlator
contain:;l a negative number, liS replace the bit positions vacated by the
right .shift.
Split Accumulator Left and Split Accumulator Bight Shift (c3.3, 034).
The discussion of states c.3land c.32 are directly applicable to the states
033 and 034 respectively. In the split~shift states the left and right
half words of the Accumulator are shifted the same nu."lJ.ber of bit positions
but are treated as separate words.
•

Spli t Left 1r.Tord Left Shift (0.35) ~ State c35 ini tia tea an operation
which caUSes the l.eft half-word of the Accumulator to be shifted left by
+~IP "'um.ber of bit positionS specified in 'II tb+ough I," The discussion of
state 031 is applicable t.o this state except that bits A14 through A24
only are affected.
Spl! t Right Word Left Shift rC,~6). Bits Al through Ala only are
affected by the Split Right Word Left Shift operation. As implied by the
state

name~

the rihgt half-word of the A register is shifted left.

58 GEIEE/72S·2

Fig.

5, v' Special Compute States

Split Left Word Ri.ght Shift (c:37). State 0:37 initiates a right shift
of the left half-word of the Accumulator. As in all right shift operations,
if the half -word W'Cire posi ti ve., the bits vacated by the shif·ting are filled
with zeroes and if the half-word were negative, liS are filled into the
vacated bit positions.
Split Right Word Right Shift (038). State c38 initiates a right shift
of the right half-word of the Accumulator. The discussion of c37 is directly
applicable to this state except the right half-word is shifted.
Single Character Output (c39)0 The operation initiated by state 039
shifts the four most significant bits out of the Accumulator and presents
them to the four character output lines. A fifth character output line is
used as a parity linea This information is presented on the character output lines for the number of word times specified in s[I].
The Single Character Output operation isaccomplisbed in the following
manner. The sector portion of the instruction operand is shifted into the
Operand Channel Buffer Register.

Each word time this register is decreased

by one, thus it is used to terminate the operation after the end of (s[I])+l
word times.
During the first word time of the Single Charaoter Output operation,
the circulation loop of the Accumulator is extended to include four flipflops of the Operand Channel Buffer Register: C1' C2 , C3 , and C4 " This
causes the four most significant bits of the Accumulator to be left shifted
into these C flipflops
Pari ty is indicated by the J flipflop by "zero"
setting it at the beginning of the operati{!Jn 9.:.nci allowing it to toggle as
each "1" is shifted into the flipflop.
The parity (J) and output (C4, C3 , C2 , and Cl ) is presented on the
0

output lines Sc5 through ScI' respectively, with the occurrence of each
ScT timing pulse.
Split Compare and Limit (c4O). State 040 initiates the Split Compare
and Limit Operation in which the split-word contents of the Accumulator is

compared with the corresponding bits of a word in memory. The memory is
specified in the operand of the SCL instruction.
If the contents of the memory word is greater than:that of A, no
changes are made. If the split word portion of A is positive and greater
than the corresponding part of the memory word, the split memory word
replaces the split-word of A.
If the quantity in :memory is less than the corresponding part of A
and that half-word of A is negative, the two's complement of the memory
half-word replaces the Accumulator half word •
. Mul tiply (c41). The Multiply operation is ini tia ted by state c41.
The operation causes the contents of the Accumulator to be moved to the
Lower Accumulator and the product of the Accumulator and memory contents
specified by the MPY operand is placed in the Accumulator.
Split Multiply (C42)0 State c42 initiates the Split MUltiply
operation. This operation is similar to the Multiply operation except
the left half-word of A goes into the right half-word of L and the right
half-word of A goes into the left half-word of L. The split words of the
Accumulator and the memory word specified by 0 I are multiplied and stored
in the respective split words of the Accumulator.
Split Multiply Modified (c43). Split Multiply Modified is an operation
which causes the three least significant bits of the Channel Buffer Register
to be replaced by the "exclusive or" of those bits and the contents of the
Phase register. The operation then proceeds as a Split Multiply operation.
Split MUltiply Modified commands allow the computer programmer to vary the
effective operand channel address depending upon the Phase register contents.
Multiply Modified (c44). State c44 initiates the Multiply Modified
operation which caUSeS the three least significant bits of the Channel Buffer
Register to be changed by an "(3Xclusive or" operation with the Phase Register.
After the above modification, a multiply operation is accomplished as described

in state 041. It is noteworthy that this operation dOes not change 'the
original multiply instruction in memory.
State Description Summary
In the above jrescription of the D17B the various configurations of
control flipflops were used to define states of the computer. These
state definitions are not unique and many other sets of flipflop combinations may be used to describe the machine operation. The states
described were chosen because they could be given names that correlate
with other published ini'ormation about the D17B. Hopefully, this type
of description will be an aid not only in understanding the operations
of the machine~ but also in maintaining it. For exampleJ the II state"
of an inoperable machine may be determined by checking the status of the
control flipflops. Once the state is identified~ the malfunctioning
circuit may become apparent by considering which flipflop is preventing
normal state transition.
Bibliography
1.

4.
5.
6.

Autonetics 0 Part 1 Preliminary Maintenance Manual of the Minuteman
D17B Computer and Associated Test Eguipment~ P.O. Memo 710 Anaheim,
California: Autonetics, Division of North American Rock'..rell, Inco,
January 1960.
'Chu, Yaohan. Digital Computer Design Fundamentals, New 'll:ork; Me GrawHill Inc., 1962.
Hansen, Do Do and Watkins~ KG R. A Rigorous Logical Study - with Lab of the D17B Digital Computero ACC-31170P-33. Anaheim, California:
Computer and Data Systems Dept of Autonetics ;lvision of North American
Rockwell, Inc.~ 30 April 19620
Shoryer, Lo o. D17B Computer Manual. Anaheim, California: Autonetics
Division of North American Rockwell, Inc., 1 July 19600
USAF Technical Order. Technical Manual Overhaul and Repair General
Purpose Computer (Model D17B), T~O. IlG2-l0-5-3-5. Los Angeles,
California: Air. ForceKier Lithographic~ 24 November 1964.
Allen, Douglas J. Laboratory Conversion and State Description of t~
D17B Computer, Thesis,Air Force Institute of Technology, Wright.
Patterson AFB, Ohio, 1972.

Appendix A
List of Terms and Abbreviations
Ak :

Carry, borrow and misc. flipflop.

"A" register extra delay flipflop.
A: irA" register read flipflop.
x
A24 : "A" register delay flipflop.
A23w: "A" register write flipflop_
B6, B5 , B4 , B3 , B2 , Bl : Bit time counter flipflops.
Cb5 , Cb4 , Cb3 , Cb2 , Cbl : Operand channel buffer register and word time
counter flipflops.
p

Cpl : Program channel register.
Operand channel storage register and auxiliary
operation-code storage register.
DI7B: Designation dfl the computer used for guidance in the Minuteman I
missile.
Shift control for "Discrete Output" register.
Discrete disable signal from a control panel to control the discrete
outputs.
D : Gyro malfunction indicator flipflop.
r
D5, D4 , D3 , D2 , Dl : "Discrete Output" register.
D: Control flipflop.
E: Control flipflop.
Emx: : "E"·loop intermediate read flipflop.
E : "E" loop end read flipflop.
x
Ep : "E" loop write flipflop •.
Enable write signal - from a control panel - enables IIcold storage"
Ewc
write heads in memory.
Fine-countdown-mode indicator flipflop.
"F" loop write flipflop_
F:
Also Fse in some writings - signal from a. control panel that directs
s
the computer to enter the Prepare to Fill state.
F:
!IF" loop read flipflop.
x

G3, G2, Gl : Binary outputs flipflopso
H: "HI' loop write flipflop.
p
H : "H" loop intermediate read flipflop.
mx:
H : "H" loop end read flipflop.
x
I : "I" register interrupt control flipflop.
c
Id: "Instruc:tionSearGh" sector disagreement indicator flipflop.
I.o Also Iic~ the ith signal input to the computer from an external
source for character input, i=l, ••• , 5.
I
Symbol fora mechanical input signal to the computer, command to
mc
enter the Wait state.
"I" register extra delay flipflop.
"I" registe~ read flipflop.
"I" register write flipflop.
Jo, Control flipflop.
K:
Control flipflop.
Halt not or run signal from a control console - directs the computer
to enter the compute states.
K'
kr° Run not or halt. signal from a control console - directs the computer
to enter the non-compute stateso
"L" register interrupt control flipflops.
"L" register delay flipflop.
L : "L" register extra delay flipflop.
p
L : "L" register read flipflop.
x
L24w: "L" register write flipflop.
M : Memory output buffer flipflop.
px
M : Also M - master reset sigDal from a control console, initiates the
rc
r
c0ID.puter to the Prepare to" Operate state.
"N" register interrupt control flipflop.
"Number Search"sector disagreement flipflop.
N : "N" register extra delay flipflop.
p
, N : liN" register, read flipflop •
x
~o

,',

N24w!

"WI register write flipflop.

0b3' 0b2' ObI: Operation-Code-Buffer register.
04' 03' 02' 01: Operation-Code-Stora.ge register.
P3 , P2 , PI: Phase register.
Q: Special timing flipflop.
R: "R" loop interrupt control and mode control flipflop.
c
R:
"R" loop write flipflop.
p
R: "R" loop read flipflop.
x
S: Information read from the sector track of the D17B computer memory.
Sb3' Sb2' Sbl: UFlag-Code" buffer register.
S3' S2' Sl: "Flag-Code" storage register.
T: Sprocket timing signal; used to direct the computer to accept
c
character inputs.
T.: Bit times of the computer, i=l, ••• , 24.
~

TO:
T :

"To Time" indicator flipflop.
"T Time" indicator flipflop.

T :
x
U:
p
Ux :

"T Time" indicator flipflop.
x
"U" loop write flipflop.

"U"

loop read flipflop •.
loop interrupt control and state control flipflop ••

V:
"V"
c
Vp : "V" loop write flipflop.
Vx : "V" loop read flipflop.
V 38 , V37 ,
V31 : Voltage output register number 3.
V28 , V27 , a
V21 : Voltage output register number 2.
e _ • ,

•

V18 , V17 ,
VII: Voltage output register number 1.
OAl : Symbolizes that the flipflop named Al is set to a logical "zero"
condi tion or "zero set".
.
Symbolizes that the flipflop named Al is set to a logical "one"
condition or "one set".
A*·
l' The star or asterisk indicates an external signal to the computer that
has been changed in voltage level but has the same logical meaning as
t!I

a ,

AI:

the symbol with no asterisk.
Prime is used to indicate a logical "not" when A is a logical 1,
AI is a logical O.

Flipflop names and some definitions in this list were taken from
Ref (1: 110-114).

USE OF THE 017B IN A HYBR~D COMPUTER SYSTEM
Lansing'B. Evans and Charles H. Beck
Tulane University
Department of Electrical Engineering
New Orleans=t LA 701rS

ABSTRACT
Now that the USAF has reZeased a Zarge number of ~nuteman DZ7B Computers
whiah were originaZZy designed for missiZe guidanae~ other appZiaations for
these e:xaess generaZ-purpose aomputers have been undergoing a rapid evoZution
in many fieZds. This paper desaribes a new hybrid aomputing appZiaation for
the ~nuteman DZ7B Computer whiah makes use of a Zarge number of the fZe:xibZe
capabiZities of these computers. Hybrid aomputing system design aan take fuZZ
advantage of the aapabiZities of both anaZog and digitaZ aomputers as weZZ as
those of speciaZ hardWare that is possibZe to deveZop beaause of the avaiZabiZity of info~ation in both continuous and discrete fo~. Motivation for
this type of appZiaation for the DZ7B stems primariZy from the versatiZe I/O
aapabiZity of these maahines. The purpose of this paper is to present some of
the design aonsiderations and typiaaZ appZiaations for a DZ7B-TR48 hybrid
aomputing system~ to desaribe the present system aonfiguration~ and to outZine
a speaifia hybrid optimization mode Zing probZem that is being soZved using
this system aonfiguration. The DZ7B has been found to be aompZeteZy satisfaatory for this automated design appZiaation.

BASIC DEFINITION OF A HYBRID SYSTEM
In a broad sense the field of hybrid computation includes all computing
techniques which combine some of the features of digital computation with
some of the features of analog computation.

The combination of digital and

analog devices brings together many of the characteristic advantages of both
types of hardware and software.

In many cases a disadvantage of one part of

the system is more than compensated for by an attribute of another part of
the system.

The idea of interacting advantages will become more evident by

citing some of the capabilities of the two major components of the hybrid
system, the analog and digital computers.

There will be additional entries

to the list of general capabilities which follows depending on the specific
computers being used in a particular hybrid system.

67
Some capabilities of the analog computer include:
1. Dependent variables within the machine are treated in continuous form.
2. High-speed or real-time computation is available with computing speeds
limited primarily by the bandwidth of the computing elements.
3. There exists the ability to perform efficiently such operations as addition,
multiplication, integration and non-linear function generation; on the other
hand, there is very limited ability to make logical decisions or store data.
4. Programming techniques involve patching together the various computing
elements.
On the other side, some of the capabilities of the digital computer
include the following:
1. All data within the computer is in discrete or quantized form.
2. In general only one operation can be performed at a time and many computing
units must be time shared.
3. The facility exists for storing alphanumeric data indefinitely.
4. The ability exists to perform logical decisions and operations using either
numerical or non-numerical data.
5. There exists the ability to modify the program extensively on the basis of
any calculation.
Almost any computing system is a subset of a complete hybrid system.
Whether a system is almost purely digital with only minimal analog capability,
nearly all analog with a small amount of digital ability, or anywhere in
between, it qualifies as a hybrid system and the principles of hybrid computing
may be applied to it.

HYBRID COMPUTER APPLICATIONS
Because of the inherent flexibility of the hybrid computer, there are
numerous applications for this type of system.

One of the most important is

modeling and parameter optimization involving dynamic systems.
~ar

This particu-

application makes use of a true hybrid system involving an analog computer,

digital computer, and appropriate interface components.

As the name implies,

modeling requires the use of known experimental input and output data to obtain
an. accurate mathematical or topological model of the system involved.

With a

complete hybrid system, relatively complicated and multi-variate models may be
consider,ed.

68
The block diagram of a' typical hybri9 modeling technique is, shown "in
Figure L

During a run the actual, system, or ;function. gent;!rat()r representing

the actual systemds operated' in"parallel with the assumed model.

The index

of performance (IP), which measures the quality of 'the model, is formed on
th~ analog comput~r'by
int~grciting
the square 'of the'error
function
over the
.
. ". .
. ;
... , .
.
"

time of the run.

,",

Using, this technique the digital computj!r adjusts the model

parameters after sampling the IP, from the previous run and performing needed
optimization calculations.

The digital computer makes its decisions on the

new parameter settings using an optimization method such as the Tulane Automated Hybrid Optimization (TARO) technique.
The TARO technique has been applied to circuits and various physical
systems.

Currently the TAHO technique is being used for a multi-variate model

of the head and neck of a pilot in a crash situation.
by monitoring human subjects who

ri~e

The data are obtained

an acceleration sled along a track.

simulation of these data is used as the actual. system portion of Figure 1.
Other typical applications of the hybrid computersystetninclude:
Aerospace Simulation
Simulation of ,Process Con.tro1
Simulation of Man-Machine S~stems
Random Process Simulation

USE OF THE MINUTEMAN D17B COMPUTER IN HYBRID APPLICATIONS
In most hybrid systems the digital computer provides control functions
as well as the digital computa'tio~'for the entire system.

Therefore, the

digital computer must have the ability to communicate not only with the usual
digital peripheral equipment but also with the remainder of the hybrid system.
The Minuteman Dl7B Co~uter has the need~d input/output versatility and the
flexibility required for ~ hybrid system.

For it~ size, the Dl7B has a large

number of' digital input and output lines, pulse output lines, and analog type
output lines.
The programmability of the' D17B i8also a significant advantage for a
hybrid system.

The D17B has a complete "set of a:rithme'i:ic, control, and input/

output instructiori~.

It is' also capable of instruction'modification which is

an important factor in efficient software for a hybrid system.

Because many

of the operations required to control the hybrid interface and the analog

INPUT

X(t)

ACTUAL
SYSTEM

ASSUMED
SYSTEM

MODEL
FUNCTION
GENERATOR
T (t)
m

DESIRED
or
ACTUAL
OUTPUT

MODEL
RESPONSE

A-D
CONVERTER

D17B
DIGITAL
COMPUTER

** **

PARAMETER
ADJUSTMENT

Fig. 1. Tulane Hybrid Optimization Modeling Technique.

computer are of a

relatively.basi~

bit-level nature, the machine language

programming of the Dl7B can be far more efficient than the use of a compiler
language.

In addition, as will be seen in the next section, the D17B input!

output instructions are very well suited for hybrid operation.
Perhaps one of the greatest advantages of the D17B hybrid system is the
comple,te flexibility of the configuration.

By the nature of the definition

of a hybrid system, it may be anywhere from pure digital to pure analog.

The

D17B will fill the digital computer requirements for any of these systems if
the memory size and speed are suitable.

The D17B hybrid system described in

the following section is a complete hybrid system with full analog and digital
capabilities.

A full system such as this allows for any operation from merely

using the D17B to control the mode of the analog computer to the sampling of
analog signals with the A-D converter and performing all processing digitally.
This means that practically any computing application can be realized as a
subset of a complete hybrid system.

MINUTEMAN D17B/TR-48 HYBRID SYSTEM CONFIGURATION
In designing the configuration of the D17B/TR-48 hybrid computer system,
a careful effort was made for full and efficient use of the D17B input/output
capabilities.

A block diagram of the basic D17B/TR-48 hybrid computer system

is shown in Figure 2.

It can be seen by inspection of the diagram that this

system is a complete, digitally-controlled hybrid system.
The two major paths of information flow in Figure 2 are those from the
digital to the analog computer and those from the analog to the digital machine.
Since many applications require multi-variate analysis, it is necessary that
the major paths in both directions be multi-channel.

Within reasonable limits,

this presents no problem to the ability of the D17B to control the interface.
The major components of the analog-to-digital information path include a
l6-channel multiplexer and an

analog~to-digital

(A-D) converter.

plexer allows 16 analog signals to time share one A-D converter.

The multiThe D17B

controls the operation of both the multiplexer and the A-D converter as shown
in Figure 3.

In order to permit one of the inputs of the multiplexer to be

switched to the input of the A-D converter, a four-bit binary address, between

and 15 decimal, is transmitted to the multiplexer address register.

The COA

INTERACTIVE
INPUT

'"
/

......

'"
......
;,-

'il
DIA

......

VOB

OOA

DOA

TEN
D-A
CONVERTERS

....
I

NONLINEAR
FUNCTION
GENERATOR

TR-48
"-.,

VOC

....

BUFFER

MINUTEMAN
D17B
DIGITAL
COMPUTER

DOA
VOA

......

'"....
.."

ANALOG
COMPUTER
PATCHING/MODE
CONTROL
RELAYS

8-BIT
PRINTER
DIGITAL

....
"

DOA
DOA

\1,

PARAMETER

,..

COA

DIB
Ij\

A-D
CONVERTER

...

-;;.r

TEN
DPUs

.....
~

MULTIPLEXER

......

Fig. 2. Tulane D17B/TR-48 Hybrid Computer System.

UNIT
INPUT/OUTPUT

l.t
I'

,..
' ......

....,

FROM
COA

BUFFER
REGISTER

4-BIT
ADDRESS

COA
TIMING

··

SIXTEEN

SIXTEEN
ANALOG
INPUTS.

CHANNEL
"

' .

MULTIPLEXER
1/
'"

OOA

-.II

A-D

I"
I'

CONVERTER

ANALOG
OUTPUT

8-BITS
,~

INTERFACE
8-BITS
.I

TO DIB INPUTS
I

Fig. 3. Hybrid System
VOB
8-BITS

A~D

and Multiplexer.

10 DOA
\

. INTERFACE
,....

•

. . ..

CLOCK 1

~I\

•

r ~t\

•
•
•

"<;,

D-A

~ ANALOG
OUTPUT
"

....,

NO'. 1

NO. 1

CLOCK 10

•

• ...

D-A
NO. 10

Fig. 4. Hybrid SYstem D-A Converters.

~ ANALOG

OUTPUT
NO. ;to

73
(character output) instruction is used for this purpose because it sends out
a clock pulse along with a four-bit parallel pulse type word which can easily
and conveniently be interfaced to the multiplexer address register.

The use

of the COA instruction in this case also means that only one machine language
instruction will be needed to control the multiplexer.

Once the proper analog

signal has been applied to the A-D converter, two discrete output (DOA)
instructions are executed to cause the A-D converter to digitize the analog
input.

Two DOAs are used to generate a pulse as required by the A-D converter.

The ten digital-to-analog (D-A) converters shown in Figure 2 are the most
important links in the flow of information from the digital computer to the
analog

co~uter.

The D-A converters are also under complete control of the

D17B.

Figure 4 shows how the D17B loads and controls the D-As.

in the Tulane hybrid system accept an 8-bit digital input.

The D-As used

This 8-bit input

is loaded into one of the internal D-A buffer registers and converted to a
proportional analog value when a clock pulse is applied to that D-A.

Since no

input is loaded into a D-A until a clock pulse is applied, the digital inputs
of all D-As may be connected together and tied to an8....bit digital bus.
The D17B has a voltage output (VOB) instruction which may be used for an
8-bit parallel digital output.

Eight bits from the accumulator are transferred

to the VOB register when a VOB instruction is executed.

Once the VOB .has been

executed, the desired8-bit word is applied to all D-A inputs.

A pair of DOAs

are then used to load the digital word into the proper one of the ten D-As.
Only a few machine language instructions are needed for D-A control.
In addition to the basic A-D and D.;...A units, the interface contains two
somewhat more sophisticated components.

These are the digital parameter units

(DPU) and the digitally controlled nonlinear function generator (DCNFG).

These

devices involve interactions between digital and analog signals rather than a
conversion from one form to the other.
The DPUs provide for the digital control of the parameters in the analog
computer patching.
the D17B.

This control is performed electronically at high speed by

With this ability the parameters of the model may be changed at high

speed under program control.

Basically the DPU is a hybrid multiplier.

multiplies the 8-bit digital word transferred from the VOA lines by the corresponding analog signal from the TR-48 as shown in Figure 5.
The interface between the D17B and the DPUs is quite similar to.the one
for the D-As shown in Figure 4.

The 8-bit VOA lines are fed to the inputs of

VOA
'IIS ....BITS

..}O OOA \1

INTERFACE

•

•• ,
Wr\

CLOCK 1

....

.:::::

ANALOG
~ OUTPUT
NO. 1

--""'"

...

CLOCK 10

"•

-:::,.

ANALOG

DPU
NO. 10

•

ANALOG
~ INPUT
NO. 1

NO. 1

III

...

DPU

~ INPUT

NO. 10
ANALOG
~ OUTPUT
NO. 10

Fig. 5. Digital Parameter Units.

...."-

BUFFER
REGISTER

,;'

DIGITALLY
CONTROLLED
NONLINEAR
FUNCTION
GENERATOR

t- x(t)

VOC
DIGITAL
LINES

INTERFACE

......

VARIABLE
BREAKPOINT
AND
SLOPE
~ y(~)

OOA
Fig. 6. Digitally Controlled Nonlinear Function Generator.

75
all DPUs.

The digital word is then loaded using two DOA instructions as in

the case of the D-A converters.

The analog inputs and outputs for the DPUs

are patched on the TR-48 patch board.

These extremely powerful hybrid comput-

ing elements are also convenient to use with D17B computer machine languageo
The nonlinear function generator is a digitally controlled variable
breakpoint function generator.

The function may have up to ten segments of

any desired slope, and the slopes and breakpoints can be programmed into the
generator under D17B program control.

The slopes and breakpoints are loaded

into the generator using the 8-bit VOC lines and DOA pulses.

After the loading

of the desired function, the output, y(t), takes on the function output for
the corresponding analog input, x(t), as shown in Figure 6.

The setup time for

the function generator is fast and versatile as is the case for the DPUs.
The mode control on the TR-48 Analog Computer is operated from external
relays controlled by the D17B Computer as shown in Figure 2.

The outputs from

the VOC digital lines are loaded into a buffer which drives the relays on the
external patch board.

The relays that are not used for mode control may be

used for high-speed patching changes ih the analog computer program.

CONCLUSIONS
While the D17B is a small general-purpose digital computer, the versatile
input/output capability of this machine has allowed for the development of a
compact, efficient hybrid computer system when used in conjunction with a TR-48
Analog Computer.

The most important benefit of a computer system such as the

Minuteman D17B/TR-48 hybrid system described in this paper is that it may be
used in a wide spectrum of computing applications.

REFERENCES
M. H. Kuo, Automated Modeling of Dynamic Systems Using Hybrid Computer 0ptimimbation Techniques, l)oct.ora1. DiSSertation, Tulane University, New Orleans,
Louisiana, 1971.
C. H. Beck, et at, "Direct modeling of nonlinear systems using hybrid computer
optimization techniques," Conference Proceedings, Seventh Annual Allerton
Conference on Circuit and System Theory, C-4, 6, Urbana, Illinois, 1969.
G. Ao Bekey and W. J. Karplus, Hybrid Computation, John Wiley & Sons, Inco,
New York, 1968.

DESIGN OF A BINARY DISPLAY FOR THE D17B COMPUTER
by
.HARRY S • WARFORD ) Capt, USAF, BSC;';
DEWIDS .. MJRAN, GS-9

INTRODUCTION
Hardware development for the D17B computing system has proceeded rather
slowly as a spare time interest at the USAF School of Aerospace Medicine.
As a result, the binary display teclmique described by this paper has .
not been optimized for future growth of the total system. However, it
has evolved into compact arid relatively inexpensive design through
effective use of machine inh~rent characteristics. The overall design
calls for the capability to monitor any register or memory track with
random access to any particUlar sector. At present, the hardware for
monitoring the me-word registers is complete and the design is complete
for the remaining circuitry to randomly address memory location.
'IEaINIQUE
The D17B utilizes the 24-bit full word for programming but actual word
length m the disc :rremory is 27 bits. "The 3-bit "dead tine" has been .
used in our design to facilitate display without the need for additional
holding registers while maintaining the capability to update the display
each word tine. DUring the 24-bit times representing the computer word
a 24-bit serial entry shift register is filled from the D17B while the
light emitting diode display is blanked. Then during the 3-bit dead time
the shift register is halted and the parallel outputs drive the display.
At the end of the 3-bit times, the display is blanked and the irifornation
is changed or reloaded into the register ..
For randan access the sector channel is to be monitored as shown in
Figure 1. Sector number infornation will be captured in an external .
register and compared with the numbers selected m a set of octally coded
thumbwheel switches. When the information agrees, the. proper shift pulses
are gated to the aforementioned 2~-bit register to capture the next word
of the chosen channel. Channel choice is by a second set of thurnbwheel
switches and the decoding internal to the D17B.

.
;'~o

be presented by Michael Jenkin, M3.jor, USAF, MC, USAF School of
Aerospace Medicine, Brooks AFB T~xas 78235

CIRCUITRY
Figures 2 and 3 show the circuits used to irrplement the basic display.
The derived control signals are shown in Figure 4. It must be noted
here that the logic signals were considered to be of positive sense
for ease of design with cOlTO'rercial DTL logic. Additionally, the levels
were not translated but the signals were merely attenuated to produce
a five volt swing and the integrated circuits were operated with "vcc"
at 0 VOC and "ground" at minus 5 VDC. Figure 5 shows the proposed
control signals to accorrplish random access and Figures 6 and 7 show
the present design being constructed for this purpose. At present,
all logic has been broken into IIDdules representing a byte of data and
irrplemented with commercial plug-in cards and racks.

OTHER DEVELOPMENTS
Little effort has been expended on hard-copy output thus far since the
surplus Flexowriters obtained for this project rapidly deteriorated and
failed early in the project. However, an extremely sirrple and inexpensive technique was used to provide input only by mounting a second
set of leaf switches in tandem with those used to operate the punch
select magnets of our remaining operable .Flexcwri ter. This provides
corrplete electrical isolation thus alleviating the need to IIDdify the
Flexowriter power supply and requires a single capacitor to shape the
timing pulses.
Additionally, an extra tape reader has been converted to stand-alone
use as depicted in Figure 8. A manual I/O panel similar to those
described at earlier user's meetings provides for miscellaneous control.

SECTOR
SELECT
SWITCH

0178

\,"~
SECTOR ..
~

TRACK

TIMING

..")
...

SECTOR
SEARCH
LOGIC

DISPLAY
LOGIC

..
•

.......

CHANNEL
SELECT
MPX

CHANNEL
SELECT
SWITCH

FIG. 1

24 BIT GATED
DISPLAY
(LED)

~
4

DATA

,.,.

BINARY DISPLAY SYSTEM

24 BIT
SHIFT REGISTER

MV-5022
Q
r-----I C

(949)
SP

FIG. 2

*¢
(D17B
CLOCK)

ONE BIT OF DISPLAY REGISTER

9G.Z

47bpf T
-S"Oc: 0
O-----------~------__4932

*
*

INPUT

(LEVELS HALVED BY RESISTOR NET.)

FIG. 3

DISl?LAY CONTROL

I
WG

FIG. 4

TIMING FOR BASIC DISPLAY

SP
8 4 '8G.

I II 1 1 I I I 1 I III I II

111111111111111111111111

11111111

IIIIII1 1

sSP

1111111

C><1

C>roceeqingsof ,the Third Meeting of the Minuteman Computer
Users Group, Minuteman Computer Users Group, Tulane University,
New Orleans, 1971.
3. W. L. White, M. M. Erickson and S. C. Stevens, Practical Automation for
the Clinical Laboratory, C. :V. Mosby Co., St. Louis, 1968.
4. Laboratory Organization and Data Handling Familiarization, T & T
Technology, Inc., 1971.
5. R. H. Laessig and P. P. Tong, "Digital Concentration Analyzer for the
Single Channel AutoAnalyzer," American Laboratory, 67, September 1970.
6. L. G. Whitby and D. Simpson, "Experience with on-line computing in
clinical chemistry, "J. Clin. Path., vol. 22, suppl. no. 3, 107-124, 1969.
7. Po Gray and J. A. owen, "Experience with on-line computer processing of
data from an AutoAnalyzer complex," Clin. Chim. Acta,vol. 24, 389-399,
1969.
8. N. P. Wilburn and 1. D. Coffin, "Combination of on-line analysis with
collection of multi component spectra in an on-line computer," IBM J. R&D,
vol. 13, no. 1, 46, Jan~ary 1969.
9. M. A. Evenson, et., al., "Application of an on-line data acquisition system
using the LINC computer in the clinical chemistry lab," Automation in
Anal. Chem., vol. 1, 137, 1968.
10. M. A. Blaivas and A. H. Mencz, "Progress report on the use of a computer
in the automated clinical chemistry laboratory,". Automation in Anal. Chem.,
vol. 1,368-372, 1967.

. ACKNOWLEDGEMENTS

This project haa been supported in part by the U. S. Army Medical Research
and Development Command under Contract No. DADAl7-71-C-1019.

The authors are

particularly indebted to Capt. Timothy C. Doyle, Computer Systems Branch of the
USAMRDC, and to Mr. Billy G. Bass, Division of Biochemistry at WRAIR, for their
valuable assistance and contributions to the success of this project. Although
the success of this development is due to the efforts of the entire staff of
the Systems Laboratory, special credit is due to Mr. Lansing B. Evans for his
supervision of the installation and demonstration of the system at WRAIR.

E.f.§'l~TE.ATIQ!!

Fourth Meeting of the Minuteman Computer Users Group
Shepaton-SiZver spring
June 5-6, 1972
Capt. Douglas J. Allen
Air Force Institute of Technology
AFIT-SE
Wright Patterson AFB, OH 45433
Mr. Richard F. Babler, Chief
Defense ADPE Reuti1ization Office
Cameron Station
Alexandria, VA 22314
Mr. Ned G. Barber
Psychology
City College of New York
138th St. & Convent Avenue
New York, NY 10031

Mr. Robert A. Beken
Programmer
Air-Medic Micronesia
Box 3
Glenn Dale, MD 20769
Prof. Philip J. Best
Associate Professor, Psychology
University of Virginia
Gilmer Hall
Charlottesville, VA 22901

Maj. Robert C. Brady
USAF HQ/xOOFC .
5916 Minuteman Road
Springfield, VA 22152

Dr. James D. Bargainer
Associate Professor
Electrical Engineering .
University of Houston
Houston, tx 77004

Dr. Sam J. Cipolla
Assistant Professor, Physics
Creighton University
Omaha, NE 68131

Mr. David W. Barrett
Chemistry
Johns Hopkins University
Charles & 34th Street
Baltimore, MD 21218

Mr. Richard S. Cook, Director
ADP Resource Management Div.
General Services Administration
18th & E Street
Washington, DC 20406

Mr. John P. Bartell
Computer Equipment Analyst
Defense Supply Agency
DSAH-LS (nARO)
Cameron Station
Alexandria, VA 22314

Mr. Charles R. Cunnnings
Computer Equipment Analyst
National Library of Medicine
Lister Hill Center
8600 Rockville Pike
Bethesda, MD 20014

Dr. Char1~s H. Beck
Professor of Electrical Engineering
Tulane University
New Orleans, LA 70118

Dr. Frederic M. Davidson
Assistant Professor
Electrical Engineering
Johns HopkinsUniver~ity
Charles & 34th Street
Baltimore, MD 21218

94
Mr. Preston G. Davis
Systems Engineering
Tennessee Technological University
Route 3
Mt. Juliet, Tennessee 37122

Prof." William Fishbein
Psychology
City College of New York
]38th & Amsterdam Avenue
New York, NY 10031

Mr. Edward Dowgirth
(Address not furnished)

Mr. Charles S. Fly
Electrical Engineering
Tennessee Technological University
Rt 7, Box 238A
Clarksville, TN 37040

Mr. Antonio Duque
Design Engineer
Fighton, Inc.
65 Sullivan Street
Rochester,NY 14605

Mr. David'S. Frager
Syst~ms Administrator
BUMED, NNMC
14300, Cantrell Road
Silver Spring, MD 20904

Mr., John W. Dyer
Electrical Engineering
Brigham Young University
B-34
Provo, UT 84601

Mr. William A. Garrison
Chemistry, BH462
University of Missouri - St. Louis
8001 Natural Bridge Road
St. Louis,MO 63121

Mr. John W. Ecklin
Computer Equipment Analyst
DSA
Cameron Station
Alexandria, VA 22314

Robert M. Goldberg
Radiology
Albert Einstein College
1300 Morris Park Avenue
Bronx, NY 10461

1>1r. Ca~los J. Escude
LowelliTechnical Institute
450 Aiken St;reet
Lowell, MA 02173

Mr. Charles E. Greene
Spec. Assistant to Director
Division Data Processing
HSMHA, PHS, DHEW - NCHS
Rm. 10A56 , 5600 Fishers Lane
Rockville, MD 20852

Mr. Lansing B. EVans
Electrical Engineering
Tulane University
New Orleans, LA 70]]8
Dr. Joseph F. Fennell
Space Physics Lab. 120/1813
Aerospace Corporation
P.O. Box 95085
Los Angeles, CA 90045
Mr. Wayne R. Fenn.er
Plasma Research Labs 120/1405
Aerospace Corporation
P.O. Box 95085
Los Angeles, CA 90045

Dr. Robert W. Gruebel
Associate Professor of Physics
Stephen F. Austin State University
Box 3044 SFA Station
Nacogdoches, TX 75961
Mr. William W. Hart, Jr.
Property Utilization Specialist
Excess Equipment Branch
General Services Administration
Washington, DC 20406
Mr. M.A. Henry
Chemistry Department
42 Whitmore Laboratory
Penn State University
University Park, PA 16802

95
Mr. ToA. Holden
Chief, ADP Reutilization Branch
General Services ADM, OADMS
Washington, DC 20406

Mr. William A. Lee
Division of Neurosugery
Medical University of South Carolina
Charleston, SC 29401

Mr. W. Lee Hunter
Systems Analystt E-291
DHEW, PHS - Ctro for Disease Control
1600 Clifton Road
Atlanta, GA 30333

Dr. John R. Lehmann
Program Director
Computer Systems Design
National Science Foundation
Washington, DC 20550

Mro Paul S. Jean
Tennessee Technological University
Electrical Engineering
511 N. Peachtree Ave.
Cookeville, TN 38501

Mr. Fred Lichtenberger
CED, B65
Picatinny Arsenal
Dover, NJ 07801

Maj. Michael A. Jenkin
Dir. of Plans and Hospiti1ization
Ole Automation Planning Group
USAF Office of Surgeon General
HQ Usaf/S6HM Forresta1 Building
Washington, DC 20013
Colo Robert L. Jones
Deputy Comptroller (Data Automation)
OASD (C) OSD
1126 Buchanan Street
McLean, VA 22101
Mr. Jay M. Kaplan
Theraputic Radiology
V.A. Research Hospital
333 Eo Huron
Chicago~ IL 60611

Mr. David A. McB1ain
Director of Computing Services
Austin College
Box 1265
Sherman, TX 75090
Mr. Leonard D. McGann
Director
Division of Data Processing
NCHS, PHS
P.O. Box 12214
Raleigh, NC 27612
Mr. William M. McGhee
President
Fightori, Inc.
65 Sullivan Street
Rochester, NY 14605

Prof. Walter So Koski
Professor of Chemistry
Johns Hopkins University
Charles & 34th Street
Baltimore, MD 21218

Mr • Thomas F McInnis
.Automatic Test Systems Dept.
Advanced Projects Lab.
Hughes Aircraft Company
Building 6 MS E165
Culver City, CA 90230

Mr. Richard Wo Kuberry
Supervisory Geophysicist
NOAA-ERL
Fredericksburg Geomagnitic Center
Corbin, VA 22446

Dr. W. Gordon Monahan
Biophysics
Sloan-Kettering lnst.
425 E. 68th Street
New York, NY 10021

Dr. Gary B. Lamont
Associate Professor
Electrical Engineering
Air Force Institute of Technology
Wright Patterson AFB, OR 45433

Mr. Cesar A. Sepulveda-Nunez
Optical Sciences Center
University of Arizona
Tucson, AZ 85721

96
Mr. RichardOhran
Electrical Engineering
Brighan Young University
173 FELB
Provo, UT 84601
Mr. George E. Pidick
Physics Department
University of South Florida
4202 Fowler Avenue
Tampa, FL 33620
Professor Icarus E. Pyros
Head, Office of Computer Science
US Merchant Marine Academy
Kings Point, L.I., NY 10024
Mr. JohnG. Romanski
Electrical Engineering
Johns Hopkins University
205 Barton Hall
Baltimore, MD 21218
Mr. Harvey S. Schultz
Biophysics
Sloan Kettering Institute
425 E. 68th Street
New York, NY 10021
Dr. Leo H. Soderholm
Investigations Leader
USDA ARS
Rm 213 Ag. Eng.
Iowa State University
Ames, IA 50010
Mr. Edward J. Taborek
Chemical Engineer, SMEFB-EE
US Army MERDC
Fort Belvoir, VA 22060
Dr. Theodore M. Thorson
Physicist, Theraputic Radiology
V.A. Research Hospital
333 Eo Huron
Chicago,IL 60611
Mr. Donald T. Torres
Bureau of Industerial Hygiene
Baltimore City Health Department
602 American Building
Baltimore & South Streets
Baltimore, MD 21202

Prof. Jack C. Towne
Chemistry
University of Dallas
Irving, TX 75060
Mr. Alfred E. Traver
Mechanical Engineering
Tennessee Technological University
Cookeville, TN 38501
Dr. Edward F. Turner, Jr.
Chairman, Physics Department
Washington and Lee University
Lexington, VA 24450
Mr. Michael W. VannieI'
Mechanical Engineering
University of Kentucky
Lexington, KY 40506
Mr. John R. Van Roekel
Gas Dynamics Labs
University of Michigan
Ann Arbor, MI 48105
Dr. James J. Whalen
Assistant Professor
Electrical Engineering
State University of New York at Buffalo
Rm 2B 4232 Ridge Lea Road
Amherst, NY 14226
Mr. Edward M. Wysocki
Electrical Engineering
Johns Hopkins University
Barton Hall
Charles & 34th Streets
Baltimore, MP 21218
Mr. Samuel P. Zieske
Director of Instrumentation
Austin College
Sherman, TX 75090

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