MICRO ONE_Users_Manual_Oct75 ONE Users Manual Oct75

MICRO-ONE_Users_Manual_Oct75 manual pdf -FilePursuit

MICRO-ONE_Users_Manual_Oct75 MICRO-ONE_Users_Manual_Oct75

User Manual: MICRO-ONE_Users_Manual_Oct75

Open the PDF directly: View PDF .
Page Count: 196

Download
Open PDF In Browser	View PDF

Microdata
Microdata MICRO·ONE
USER'S MANUAL

;

I_

Microdata

,

MICRO-ONE

I

®

MICRO·ONE

USER'S MANUAL

UM 20001506
OCTOBER, 1975

PROPRIETARY INFORMATION
The information contained herein is proprietary to and
considered a trade secret of Microdata Corporation
and shall not be reproduced in whole or part without
the written authorization of Microdata Corporation.

98820751011A
© 1975 Microdata Corporation
TM Trademark of Mlcrodata Corporation
Printed in U.S.A.

III'"
D6(714)

I~

Microdam
Microdata Corporation
17481 Red Hill Avenue
Irvine, California 92714

540-6730 TWX, 910-595-1764

MICRO ONE USER'S W\NUAL .
TABLE OF CONTENTS
Page
SECTION 1
1.0
1.1
1.2
1.2.1
1.2.2
1. 2. 3
1. 2.4
1. 2. 5
1. 2 •. 6

1.2.7
1. 2. 8
1..2.9

1.3
1..3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.4
1.4.1
1.4.2
1.5
1. 5.1
1.6
1.7
1.8
1.9

SECTION 2
2.0
2.1
2.1.1
2.1. 2
2 •. 1. 3

2.1. 4
2.1.5
2.1. 6
2.1. 7
2.2
2 •. 2.,1

2.2.2
2.2.3
2.2.4

2.2.5

ARCHITECTURE
SYSTEM ORGANIZATION
General Characteristics
Registers and File
T Register
M Register
N Register
L Register
U Register
R Register
LINK Register
I/O Control Register
File Registers
Memory Descriptions
Core Memory
MOS Memory
Control Memory
Memory Busy Delays
Memory Data Delays
Read-Only Memory Delays
Status and Condition Flags
Internal Status
Condition Flags
Byte I/O Interface
Byte I/O Bus
External Priority Interrupts
Real-Time Clock
Power-Fail/Automatic Restart
Arithmetic Functions
MICROCOMMAND REPERTOIRE
GENERAL
Connnand Formats
Litera1,Commands
Operate Commands
Execute Conunand
Formats for Execute Commands
Literal Commands
Operate Commands
Terms and Symbols Used in the command Descriptions
Microcommands - Formats, Descriptions, and Examples
LT Load T
LM Load M
LN Load N
LU Load U
LZ Load Zero Control

i

1-1
1-1
1-6
1-6
1-7
1-7
1-7
1-7
1-7
1-7
1-7
1-8
1-8
1-8
1-9
1-9
1-9
1-9
1-9
1-10
1-10
1-10
1-11
1-11
1-13
1-13
1-13
1-14

2-1
2-1
2-1
2-1
2-2
2-2

2-3
2-3
2-4
2-4
2-4
2-5
2-5
2-6
2-6

Page
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
2.2.16
2.2.17
2.2.18
2.2.19
2.2.20
2.2.21
2.2.22
2 •. 2 .. 23
2.2 .. 24
2.2.25

L Register Organization
LF Load File
AF Add to File
TZ Test If Zero
TN Test If Not Zero
CP Compare
K Control
Standard Output Functions
Standard Input Functions
A Add
S Subtract
R Read Memory W Write Memory
C Copy
o Or
X Exclusive Or
NAnd
H Shift
E Execute

2-7
2-8
2-8
2-10
2-10
2-11
2-13
2-14
2-15
2-17
2-17
2-23
2-26
2-28
2-33
2-33
2-37
2-39
2-41
2-42

SECTION 3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4

MICRO-ONE I/O AND MEMORY INTERFACE
General Discussion
1/0 Organization
Serial 1/0 Interface
Byte I/O Interface
Program-Controlled 1/0
Concurrent I/O
External Priority Interrupts
Direct Memory Access Port

3-1
3-1
3-1
3-1
3-3
3-3
3-3
3-4

SECTION 4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.4.5
4 •. 2.4 •. 6

BYTE 1/0 INTERFACE
Introduction
Byte I/O Bus
Input Data Lines
Output Data Lines
Input Control Lines
Output Control Lines
Control Lines IOlX/ through I03X/
Lines CPH1 and CPH2/.
Control Line MRSTI
Control Line PROT/, PRIN/
Spare Lines
Control Line SELO/, SELI/.
·Byte I/O Fundamentals
Device Addresses
Device Orders
Status Bytes
Function Bytes
Byte I/O Operations and Timing

4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-4
4-4
4-5
4-5
4-5
4-6
4-6
4-7
4-9
4-9
4-10

4 .. 3
4.3.1
4.3.2
4.3.3
4.3.4

4.4

L8 Load Seven Control
JP Jump

ii

Page

4.6
4.6.1
4.6.2
4.6.3

Program Controlled I/O Operations
Address/Order Phase
Transfer Phase
Data Output Operations
Function Output Operations
Data Input Operations
Concurrent I/O Operation
Concurrent I/O Timing
External Interrupt Operation
Priority Determination
External Interrupt Requests
Interrupt Sequence and Timing

SECTION 5
5.1
5.1.1
5.1. 2
5.1.3
5.1.4
5.2

MICRO-ONE CPU READ/WRITE MEMORY INTERFACE
Processor and Memory Interface
Control Section
Memory Read Data Selection Logic
Memory Write Data Gating Logic
M and N Register Address Gating Logic
Memory Control Interface

5-1
5-1
5-3
5-3
5-3
5-3

SECTION 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
6.3.1
6.3 •. 2
6.3 •. 2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.2.5
6.3.2.6

DIRECT MEMORY ACCESS PORT
Introduction
Functional Description
DMA Interface
DMA Memory Control Logic
DMA Memory Read Data Receivers
DMA Memory Write Gating Logic
DMA Memory Address Gating Logic
DMA Port/Memory Control Interface Timing
Clock Signals
DMA Port Signals
DMA Request (DMAR/)
DMA Write (DMAW/)
Memory Busy (MBSY)
Memory Addresses
Write Data
Read Data

6-1
6-1
6-3
6-3
6-4
6-4
6-4
6-4
6-5
6-5
6-5
6-5
6-6
6-6
6-6
6-8

SECTION 7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4

SERIAL I/O INTERFACE
Introduction
Use as Teletype Controller
General Operation
Character Assembly and Disassembly
Serial I/O Instructions
Teletype Interface Connection

7-1
7-1
7-1
7-1
7-4
7-4

SECTION 8
8.1
8.2
8.3

MICRO-ONE BACKPLANE CONNECTOR SIGNAL LIST
I/O Controllers and DMA Interface Signal List
Serial TTY (J2)
Front Panel (Cable) Connector (J3)

8-1
8-1
8-1

4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.1.5
4.5
4~5.1

iii

4-10
4-11

4-12
4-12
4-12
4-13
4-14
4-14
4-16
4-17
4-18
4-18

Page
SECTION 9

I/O INTERFACE SIGNAL GLOSSARY

SECTION 10
10.1
10.1.1
10.1. 2
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7

OPERATOR CONTROLS
Consoles
System Console (Standard 1600 System Console)
Basic Console
Displays on System Console
Data Display
Run
Halt
Lock
Scan
Panel
Address Stop
Switches and Syst~ Console
Display Selector
Connnand Switches
Pa,nel. Switch
Sense Switches
Run
Step
Interrupt
Clock
Reset
On 'Off-Lock
Address Sync
Register Display and Entry
Display
Enter
Operating Procedures -- System Console

10.3

10.3.1
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10 •.4.5
10.4.6
10.4.7
10.4.8
10.5
10.6
10.6.1
10.6.2
10.7
SECTION 11
11.1
11.1.1
11.1. 2
11. 2
11.3
11.4
11.5
11.5.1
11.,6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.15
11.16

MICRO ONE CPU OPERATIONAL DESCRIPTtON
General
Arithmetic Logic Unit and Multiplexer
Carry In
T. Register
File Registers
Rand U Registers
L Register
L or K Destination in an Operate Command
Condition and Link Logic
Memory Address Registers (M and N)
Destination Register Clock Logic
Command Decode ROMs
Programmed Input/Output
Interrupts
Memory Sequencer (Core Memory Version)
Computer. Clock and Run Control .
Run/Ha1t·Control
.
Computer Start Logic
Automatic Power Fail and Power on Detection Function

SECTION 12

SCHEMATICS

11~14

'iv

10-1
10-1
10-1
10-1
10-3
10-3
10-3
10-3
10-3
10-3
10-3
10-3
··10-3
10-4
10-4
10-4
10-4
10-4
10-4
10-4
10-5
10-5
10-5
10-5
10-5
10-5
10-6
11-1
11-1
11-3
11...,7
11-9
11-9
11-:-9
11-12
11-;14
11-14
11-14
.1~-18

11-19
11-19
i1-22
11-26
11-26
11-29
1i-29

LIST OF ILLUSTRATIONS
Figure No.
1-1
1-2
3-1
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
6-1
6-2
7.... 1
7-2
10-'1
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16

Title
Micro-One Block Diagram
Backplane Interconnections
Typical Micro-One Series I/O Configuration
Micro-One I/O Bus Lines
Relationship of Control Signals CPHI q.nd CPH2/
Data or Function Output Timing
Data or Status Input Timing
Concurrent I/O Timing
Typical Priority Scheme
Typical Selection Acknowledgment Scheme
External Interrupt Timing
Interrupt Sequencer States
CPU and DMA Memory Interface
Half Cycle Read
DMA/Processor Core Memory Interface
DMA Port/Memory Control Timing
Serial I/O Interface Circuit
Serial I/O Timing
MICRO 1600 System Control
Arithmetic/Logic unit Block Diagram
2-Register Block Diagram
Fill Registers Block Diagram
Rand U Register Block Diagram
L Register Block Diagram
Condition & Link Register
M and N Address Registers
Destination Register Clock Logic
Command Decode ROM's Block Diagram
Programmed I/O Block Diagram
Interrupts
Memory Controller Block Diagram
Clock Generation Logic, Block Diagram
Run/Halt Control Block Diagram
Computer Star.t Logic, Block Diagram
Power Fail Detect Block Diagram

v

. 'Page
1-2
1-12
3-2
4-2
4-4
4-12
4-14
4-15
4-17
4~18

4-19
4-20
5-2
5-5
6-2
6 .... 7

7-2
7-3
10-2
11-2
11-8
11-10
11-11
11-13
11-15
11-16
11-l7
11-18
11-20
11-21
11-23
11--27
11-28
11-30
11-31

LIST OF TABLES
Title

Table No.

. Page

1-1

Microcommand Set

1-3

1-2

File Register 0 Flags

l""~

1-3'

Inter,nal Status Bits

1-10

2-1

Register Designation for op~rate Co~ands

2-2

2-2

Standard I/O Control Codes

2-2.0

2-3

2-24

2..... 4

2-25

2-5

2-26

2-6

2-26

4-1

I/O Control States

4-4

4-2

Standard I/O Device Addresses

4-7

4-3

Standard Device Order

4-9

4-4

Typical Status Byte Definition

4""10

4-5

Interrupt Sequence States

4-2Q

8-1

Micro-One Backplane Connector Signal List

8-2

8-2

MOS Memory Interface Connector. List

8-4

9-1

I/O Interface Signal Glossary

9:",,1

11-1

ALU MUX Addresses, ALUModes, and Carry In

11... 4

vi

SECTION 1
ARCHITECTURE

SECTION 1
ARCHITECTURE
1.0

SYSTEM ORGANIZATION

The Micro-One Computer is a bus-organized system~ constructed around a file
of 15 programmable registers, which feature microprogrammed control. The
basic elements of the system are shown in the block diagram of Figure I-I.
The system executes 15 basic microcommands with many variations, plus a
code-variable execute command shown in Table 1-1. All microcommands are
l6-bits long and are in one of three standard formats. Micro-One microprograms are established in a Read-Only~Memory (ROM) and thereafter become
an integral part of the system's hardware. The microprogram can be changed
by replacing the ROM devices. Commands read out of the ROM control all
aspects of Micro-One's operation and are executed in a single 200 nanosecond
machine clock cycle.
Micro-One's 8-bit Arithmetic/Logic Unit (ALU) performs all data manipulation,
including: addition, subtraction, logical AND, logical OR, logical Exclusive
OR, and I-bit left and right shifts. The output of the logic network is the
A-bus which is the input to the files and other system registers; all data
byte movement occurs on this bus. The A-bus extends to the backplane and
can be used for special I/O functions. The output of the register file is
one of the inputs to the ALU, the other input is the B-,bus. B-bus inputs are
determined by the type of command, its options, and the I/O mode. B~bus
inputs are the true and the complement outputs of the T register, the input
bus, and the 8-bit literal contained in certain commands, and four external
sense lines.
The memory data and address buses communicate between the core memory
modules, the processor, and the Direct Memory Access (DMA) port. Either the
processor or the DMA port may operate with the memory, with DMA having
operational priority.
1.1

GENERAL CHARACTERISTICS

The heart of the Micro-One system is mounted on a single 8-1/2 x l2-inch
printed circuit board which contains the basic CPU and the lK ROM. There is
a connection and interface control for a piggyback MOS memory of up to 8K
bytes in lK increments. Additional characteristics include:
•

Core memory addressing to 64Kbytes, or strap selectable to 32K bytes
for operation with Micro-One/2l firmware.

•

1.0 Microsecond memory speed (full cycle)

•

8-Bit memory bytes

•

Up to 1024 words of read only storage

•

Two versions of control consoles

1-1

JUMPERED FOR
32K OR 64K BYTES

~~--~--~--~~-DATA,
STATUS,
REQUESTS,
CONTROL

DIRECT
MEMORY
ACCESS
CORE MEMORY
0-32K BYTES
MEMORY OAT
BUS

CoNTRoL.r---------~

101X}
102X
103X

3UNES

I/O CONTROL .....~_ SET BY COMMAND
REGISTER
DECODE AND CONTROL

INPUT BUS (8 BITS)

FILE
REGISTERS
(15 x 8)

CONDITIONS
(ZERO
POSITIVE,
OVERFLOW)

CONSOLE
DATA
SWITCHES
8 BITS

READ ONLY
STORAGE
256-1024
WORDS (16)
R BUS (16 BITS)

"-_ _ _8~B"-'IT;....;:.L;...;IT...;;E"_R"_A.;.;;L;,;;S;..;F...;R.:..;O:;.;M~R.;..;O:o.;.M"___

___I

COMMAND
DECODE AND ....- CONSOLE CONTROL
CONTROL
SWITCHES

TO ALL FUNCTIONS

Figure 1-1.

R REG ISTER
(16) BITS

Micro-One Block Diagram
1-2

Table 1-1.
No.
0

1

Name
Execute

Literal
to
Register

Microcommand Set

Class Instruction

Code

Mnemonic

Execute

OXXX

E

NA

LZ
LT

Literal
Class
Commands

10XX
11XX
12XX
13 XX
14XX
1SXX
1CXX
1DXX
16xx
17XX

JP
JP
JP
JP
LU
LS

Load
Load
Load
Load
Jump
Jump
Jump
Jump
Load
Load

2fXX

LF

N/A

f

=

3fXX

AF

N/A

f

= file

Literal to Register
Subfunctions

LM
LN

2

Load File

3

Add to File

4

Test If Zero

I

4fXX

TZ

5

Test Not Zero

I

Sf XX

TN

N/A

6

Compare

I 6fXX

CP

N/A

Operations
OX is ORed with U Register
No operation
XX replace contents of T
XX-replace contents of M
XX replace N & M is cleared.
to page O.
to page 1.
to page 2.
to page 3.
XX replaces contents of U.
Internal Controls

Zero
T
M
N

U
Seven

I-'

I

w

I

Operate
Class
Commands
C fie
7

7fc*r

IdJ

L

K

I

N/A

!

estination register
r ,M,N,L, U
N/A

Control

--

I
I

I

i

I

file number
number

Skip
f of
Skip
f of

on no bits match, i f file
the ones in the XX.
on any bits match in file I
the ones in X.
I

Skip
c
0000
0001
0010
0100
0111
1000
1001
1010
1011

on f + XX>28 -1
Field (Binary)
No operation
Enter Sense Switches
Shift Right Four Bits
Enter Internal Status
Enter Console Switches
Clear I/O Mode
Control Output
Data Output
Space Serial TTY

I

Table 1-1.
Name

No.

7

Control

Class Instruction
Operate
Class
Commands

Code

Microcommand Set (Continued)
Mnemonic

7fc*r

Literal to Register
Subfunctions
N/A

---8fc*r
8

10

A

S

N/A

Subtract

Copy

12

OR

0001
0010
0100
1000

Modify Flags
File + T
Sum + 1
Sum + Link Bit

0001
0010
0100
1000

Modify Flags
File + T Complement
Inhibit Increment
Difference + Line

R/S

N/A

OOXX
01XX
10XX
11XX
XXlX
XXX1

Transfer
Decrement
Add Link
Increment
Half Cycle
Write (Not Read)

Bfc*r

C

N/A

XXX1
XXlX
XlXX
1XXX

Modify
Select
Select
Select

Flags
T
+1
Link

Cfc*r

0

N/A

XXX1
XXlX
XlXX
1XXX

Modify
Select
Select
Linked

Flags
T
T Complement
Zero Test

I

11

Concurrent Acknowledge
Interrupt Acknowledge
Data Input
Spare

Afc*r
Read/Write
Memory

I

1100
1101
1110
1111
I

N/A

Add

9fc*r
9

C field (binary)

_~

_ _ . ___ l---.-.-._._ _ _ _ _ _ _ _ _

j

I
1

I
I

I

I
I

1

Table 1-1.
No.

Name

Literal to Register
Subfunctions

C field (binary)

I

I

Dfc*r

X

14

AND

Efc*r I

N

Same as OR

15

Shift

Ffc*r

I

H

XXXl
XXlX
XlXX
lXXX

®
G)
@

If* = 0, result of operation
is placed in file (f) •

=
c =
* =
r =
f

file address
sub op code field
inhibit file write
destination field

I

I

Same as OR

Exclusive OR

(!)
Vt

Mnemonic

13

NOTE:

I-'
I

Code

Microcommand Set (Continued)

I

Modify Flags
Shift Right
Insert ONE
Insert Link

1.2

•

TTL integrated circuitry

•

Operating temperature 0 to 500 C; relative humidity 90%

•

Compatibility with Micro 1600 interface controllers

•

Power:

•

Power fail detect and auto restart standard ,(requires full wave
rectified 8V peak signal supplied from power supply)

•

120 Hz real-time-clock standard

•

Serial TTY interface standard

•

Single channel external interrupt

•

Concurrent I/O using the programmed I/O bus

•

Bidirectional memory data bus

•

Separate 8-bit output and input data buses

•

ROM memory sequencer which can be programmed for CORE OR MOS
memory timing

+5V, 3A with lK ROM

REGISTERS AND FILE

There are eight CPU registers and 15 file registers. Each,of the eight CPU
registers has a specific use in the processor, while the files are used for
general storage and flags.
1.2.1

T Register

The 8-bit T register serves as the operand register for moSt of the operate
class commands, and as a buffer register for output and memory operations.
Both the true and complement output of the T register can be gated to the
B-bus as an operand. When 'both the contents of T and its complement are
selected as operands, the effective operand is all l-bits; if neither is
selected the operand is all O-bits.
The T register can be loaded directly from ROM 'using a Load T instruction,
from core memory on a Read instructioI1~ or it may, be loaded from a file '
register from the input bus, or fro~ itself (such as when incrementing T) by
designating T as the destination register of an, operate class command. All
programmed outputs, including contro1ancJ data bytes, go out via the T register.

1.2.2 M Register
The eight-bit M register contains the eight high-order bits of the processor
memory address. This register is gated onto the Memory Address bus at all
times except during
DMA op~ration. The M register can be loaded directly
from ROM using a Load M command, or can be loaded by designating M as the
destination register of an operate class command. The M register is cleared
on a Load N command.

a

1.2.3

N Register

The eight-bit N register contain the eight 10~order bits of the processor
memory address. This register is gated onto the Memory Address bus at all
times except during a DMA memory operation. The N register can be loaded
directly from ROM using a Load N command, or by being designated as the
destination register of an operate class command.
1.2.4

L Register

The 10-bit L register is the program counter and contains the read-only
storage address of the next command to be executed, unless it is altered
by a Jump command. The eight low-order bits of the L register serve as a
counter which is incremented by one at each clock time when the processor
is running unless a command execution delay is imposed. L is loaded by
a Load L command, or as a destination register of an operate class command.
1.2.5

U Register

The eight-bit U register is used to modify the output of the read-only storage.
For commands with Op Code 0 or non1itera1 instructions with destination of 7,
the contents of the U register are Inc1usive-ORed with the eight high order
bits of the ROM output as it is gated into the R register. This allows for
dynamic modification and changing of operation codes and file register
designators. U is loaded by a Load U command or as a destination register
of an operate class command.
1.2.6

R Register

The 16-bit R register holds the present microcommand being executed. Its
output is decoded and controls the operation of the processor at each clock
time.
1.2.7

LINK Register

The one-bit LINK register holds the ALU'S high order carry from Add, Subtract,
and Compare commands and the shifted off end bit from the Shift command.
1.2.8

I/O Control Register

This three-bit register generates the control signals for the I/O bus,
Seven separate control signals can be developed by decoding the register
outputs. It is loaded and cleared by a control command, placing the timing

1-7

of I/O control signals under command control. There are three output modes
and four input modes. The high-order bit of the register is the input flag.
When this bit is aI-bit, the input bus is esupstituted for the T regi,~ter
when it is selected, and is the source of data when executing an'external
I/O control command.
1.2.9. File Registers
Files consist of 15 eight-bit operational registers plus one File Zero
register. All commands, except Load Register with Literal (Op-l), specify
the file which will provide one input to the ALU. All file registers are
functionally identical except for file register 0 which contains eight
flags, and cannot be used for g,eneral storage. The flags of file register
o are given in Table 1-2.

Table 1-2.

File Register 0 Flags

Bit

Flag

r-----~--------------~--~--~----------------------------------------~

o

Overflow Result Condition

1

Negative Result Condition

2

. Zero Result Cond! ton

3

Concurrent I/O Request Line

4

Internal Interrupt

5

I/O Reply Line

6

Serial Teletype

7

External Interrupt Line

r-----------.-------------~------------------------------------~--------~

1.3 MEMORY DESCRIPTIONS
A brief functional description of the Micro-One·s memories, memory busy, and
memory data delays is provided in paragraphs 1.3.1 through 1.3.6.
1.3.1

Core Memory

The magnetic core memory of the Micro-One is organized into pluggable modules
of 8K or 16K bytes. Addressed at the byte level, the memory is operated in
read or write, and full or half-cycle operations. The full-cycle memory
timing is five 200 ns clock cycles (1.0 microsecond); the half.,..cYcle timing
in the system is three clock cycles (600 ns). For a read operation, the
acce.ssed data is placed in the T register two clock cyclesa:fter the start
of the memory operation. Full cycle regeneration of the data in the memory
does not require the use of the T register and'! may be modified'by the
microprogram before completion of the restore part of the cycle.

1-8

1.3.2

MOS Memory

The MOS memory of the Micro-One is organized into modules of lK bytes with
up to 8K bytes available. The memory is mounted piggyback on the Micro~One
circuit board so that additional connectors are not required.
1.3.3

Control Memory

The read-only memory provides storage for commands and constants of the
microprogram. Its output is gated into the R register where it controls
system operation at the next clock time.
The ROM is always accessed for the next command while the current command
is being executed. This look-ahead ability achieves faster command execution
time. When the sequence of command execution is altered by a jump or skip,
and additional cycle must be taken to perform an access before the next
command is executed. When the unit is halted. theL register contains the
address of the first command to be executed when operation is resumed.
Each command is executed in a single clock cycle time although execution
may be delayed because of core memory or read-only memory operations. The
system clock rate is 20 MHz, and the clock cycle is 200 nanoseconds.
1.3.4 Memory Busy Delays
When the memory is busy due to processor or D}~ operations and a read/write
command or a command to modify M or N registers awaits execution, a delay
will occur until the memory operation is completed. These commands are
executed on the last clock of the memory half or full cycle. If a DMA
request is pending at the time a read or write memory command is to be
executed, execution is delayed to give the DMA memory priority.
1.3.5

Memory Data Delays

Operate class commands which select the contents of either the T register
or its complement during the first two cycles of a processor memory read
operation are executed during the third cycle of the read operation. This
allows time for the accessed byte to be placed in the T register.
1.3.6

Read-Only Memory Delays

An extra cycle is required for command execution for the following conditions
because of the look-ahead nature of the read-only memory:
a.

Jump command.

b.

Test if Zero command when a skip occurs.

c.

Test if not Zero command when a skip occurs.

d.

Compare command when a skip occurs.

e.

Operate class commands which have the L register designated
as a destination.

1-9

1.4

STATUS AND CONDITION FLAGS

Status and Condition flags are described in the following paragraphs.
1.4.1

Internal Status

Eight internal status bits are provided in Micro-One to designate a
particular internal interrupt condition. When any of the internal status bits
is a I-bit, the internal interrupt flag (bit-4) in file register 0 is also a
I-bit. This flag is tested by the microprogram to detect the presence of
the internal interrupt condition. The internal status bits are entered
via the B-bus into the selected file register by a control command, at which
time the status bits are cleared. The assignments for the eight internal
status bits are given in Table 1-3.
Table 1-3.

Internal Status Bits

Bit

~

Interrupt Status

o

Console Interrupt

1

DMA termination

2

Real-Time Clock Interrupt

3

(Spare 0)

4

(Spare 1)

5

(Spare 2)

6

Console Step Switch

7

Power Fail/Restart Interrupt

_____________________- L______________________________________________

1.4.2

~

__

~

Condition Flags

The Overflow, Negative and Zero conditions resulting from an operation
involving the ALU can be stored in File Register 0, (See Table 1-2,)
condition flags are updated for command 7 and for commands 8, 9, B-F if
bit 4 is a I-bit. These condition flags can be tested by the microprogram
for implementing various conditional operations. Definitions of the
condition flags follows:
a.

Overflow - The Overflow Condition Flag stores the arithmetic
overflow condition during an add, subtract or copy command. It
stores the shifted off end bit during a shift command. Arithmetic
overflow occurs when the result exceeds the range of the computer's
8-bit registers.

1~0

b.

Negative - The Negative Condition Flag stores the high-order bit
of the result on the A-bus since the 2's complement number system
uses the most significant bit as the sign bit.

c.

Zero - The Zero Condition flag stores the zero condition of the
result. The zero test can be linked over multiple byte operations
under control of the LINK modifier (bit 7) of operate instructions,
When this bit is 1, the Zero Condition flag may not be set to indicate
the zero condition of the current byte, but may only be reset to
indicate a non-zero result. For this flag to indicate zero over
multiple bytes it must be set by a zero result on the first
operation which will have the LINK modifier zero, and not be reset
by non-zero conditions on succeeding bytes which will have the
LINK modifier a one.

1.5

BYTE I/O INTERFACE

The Micro-One provides an extremely fast elementary I/O capability. (The
basic interconnections are shown in Figure 1-2.) The data paths and control
functions are simple elements, sequenced from the control memory with
flexible disciplines. With the fast (200 ns/step) control memory, firmware
microprograms in control memory can react with a high degree of versatility
in timing, data paths and I/O capabilities. This inc1ude~ priority interrupts,
fully-buffered data channels, macroprogrammab1e transfers, and special
purpose communication multiplexer channels.
The byte I/O interface provides the facility for transferring bytes over a
party line I/O bus under microprogram control. Standard Micro~One firmwave
provides both programmed I/O and concurrent I/O transfer capability, along
with a priority interrupt system. The basic I/O element is the Byte I/O
bus.
1.5.1

Byte I/O Bus

Data transfers through the byte I/O interface are basically two'"'phase
operations. During the first phase, a control byte is placed on the Byte
I/O bus before the actual transfer of data. The control byte contains a
device address specifying the address of one of the I/O controllers on the
bus, and a device order code signifying the type of operation. to. be
performed during the transfer (data, status, or function transfer. etc).
All controllers on the bus examine the device number, but only the addressed
controller accepts the control byte and logically connects itself' to" the bus
for the subsequent data byte transfer. During the second phase of the
byte I/O operation, a single byte is transferred to or from the controller.
After each byte transfer the controller disconnects itself from the bus.

CPH , & CPH 2
-- BYTE OUT
10XX
MEM ADDR

DMA
INTERFACE

MEM OAT
..- DMA CTL
BYTE IN

~ CPH, & CPH 2

BYTE I/O
INTERFACE

THE 1600 SYSTEM
PANEL CAN BE
USED WITH THE
STANDARD'
MICRO ONE

BYTE OUT
BYTE INPUT
10XX

R
EXTERNAL
ROM

L

.ACKPLAN~~
s::

SYSTEM
PANEL

-

L

-

A
Mj:MADDR

~

(;
:II
0
0

-10-PIN
lDlD
0 l> r :II
CONNECTOR
m m ~~ -<-< 0X ." 'CD lD lD
S::l> -1-1
ON MICRO ONE
I-J:
e e
X
(I) (I)
0 0 00 mm
BACKPLANE
Q!I ~
0:II

s:: s::
s:: s::

.-

10LEAD~
CABLE

PIGGYBACK
MOS
MEMORY

PANEL
CONTROL

:II 0

Z

0 0 -IS
r

e

J4

Lt.
+5
+12
POWER -16.75
GND

..
..
.

PWR FAIL& :
RTC
REFERENCE

~

l-+

J3
J10

r

~HtJI~
I
I
I

i!

:Il

m
e ~
(I)

G) lD
"'0

BASIC
PANEL f0-

--

Ci)
e Z ~
-< -< -'5F'
FLOWCHART
CHART

L

MACHINE
CODE

MNEMONIC

'014'

'61AO'

CP 1 X'AO'

N NO
SKIP

AFFECTED REGISTER STATES:
REGISTER

BEFORE

AFTER

CASE 1

L
F1

'014'
'52'

'016'
'52'

NOSKIP

CASE 2

L
F1

'014'
'66'

'015'
'66"

SKIP

COMMAND EXECUTION TIME - 200 NANOSECONDS - NO SI5IP
400 NANOSECONDS - SKIP

2.2.14

K Control

7

f

c

1.1

r

1

1514131211109876543210

This command is used to control special data flow operations, and I/O
functions. The prime usage is:
•

Enter sense switches from panel to selected file register

•

Shift selected file right 4 bit places

•

Enter internal status to selected file register

•

Set and clear the 3 I/O control flip flops (IOXX)

2-15

The prime functions of this command are determined by the value of the c field
as follows:
Explanation

Operation

c

o

No operation

1

Enter Sense Switches

Status of the 4 console sense
switches are placed in the 4 high
order bits of the file file
register designated by f. The 4
low order bits are set to 1 bits.
The status can also be placed in
the designated destination register.

2

Shift File Right 4

The 4 high order bits of the file
register designated by f are placed
in 4 low order bits of the file
register. The 4 high bits are set
to 1 bits. The result can also be
transferred to the designated
destination register.

3

Unused

4

Enter Internal Status

5

Unused

6

Unused

7

Enter Console Switches

The 8 internal status bits are placed
in the file register designated by f,
and the designated destination
register. The internal interrupt
flag in file 0 is reset by this
command, along with the console
interrupt, real-time clock, memory
parity, and power fail/restart.
Console step is reset upon release
of the console switch and spare bits
are controlled according to their
individual implementation in h
hardware.

2-16

The contents of the 8 low or.der console command switches are ANDed with
8 low order bits of the next command.
File register 0 and the destination
register 0 must be selected to prevent any modification of the file or
register during execution of the control command. The command physically
preceding this operation must not
cause a read-only memory delay.

~peration
__________________________.___
Ex_p~l_a_n_a_t_i_o__
n

c
8

Clear I/O Mode

The I/O control register is cleared.
Data from the designated file or input
bus ANDed with the designated file can
be transferred to the designated file
register and register (r).

9-F

Set I/O Modes

The I/O control register is set to
equal the 3 low order bits of the c
field. Data from the designated file
or input bus ANDed with the designated
file can be transferred to a designated
file register and register (r). For
all values of c, except 0,3,5,6,7,
source data is placed in the designated
files if bit 3=0 and also in the designated register. Destination r=7 is
undefined for this command. In other
words, the U register is not used.

2.2.15

Examples of Control Commands

C = 1 Enter sense switches into file 1
L

'005'

Machine
Code

Mnemonic

, 7110'

K 1,1

Flow Chart
Notation

Affected Register Status:

Case 1

Case 2

Register

Before

After

L

'005'

file 1
Sense SW (Binary)
File 0 (Bits 2-0)

1001

'006'
'9F'
1001
010

L

'005 '

file 1
Sense SW (Binary)
File 0 (Bits 2-0)

0010

'006' .
'2F'
0010
000

C = 2 Shift file 1 right 4
L

'012'

Machine
Code

Mnemonic

'7120'

K 1,2

2-17

Flow Chart
Notation

Affected Register States:
Register

Before

After

L

'012'

file 1
file 0 (Bits 2-0)

'EO'

'013'
'FE'
010

C = 4 Enter internal status to file 1
L

'lE3'

Machine
Code

Mnemonic

, 7140'

K 1,4

Flow Chart
Notation

Affected Register Status:

Note:

C

Register

Before

After

L

'lE3'

file 1
Status
file 0 (Bits 2-0)

'45'

'lE4'
'45'
'40'
000

Sense switch 4 can be tested by testing negative condition flag
after entering SSW to file O.

=7

Enter console switches into file 5
Flow Chart
Notation

L

Machine
Code

Mnemonic

'112'
, 113'

'7070'
'25FF'

K 0,7
LF 5,X'FF'

fSI\CSW-. f5

Register

Before

After

L

'112'

file S
Console SW
file 0 (Bit 2-0)

, AS'

'114'
'AS'
'AS'
010

Affected Register Status:

This command cannot be executed via the front panel because it requires a
dynamic situation, and two separate functions entered on the front panel.

2-18

2.2.16

Standard Output Functions

The two output codes COXX and DOXX represent a two byte output sequence,
where the first byte is for control, and the second byte is for data. A
device select control byte is first placed in the T register (which is
also the output bus) and then COXX is set and reset. Following this, a
data value is placed in T and DOXX is set and reset.

COXX and DIXX control codes are used for data input routines. A device
select control byte is first placed in T, and COXX is set and reset.
Following this, DIXX is set, data is input while DIXX is set and then DIXX
is reset.
While DIXX is set, data can be entered in two ways:
1.

Operate commands involving T get the input bus instead of T as
long as I03X is set. These commands are ADD, OR, COPY, EXCLUSIVE
OR, and AND. Any of these can be used to input data while DIXX
is set as long as T complement is not selected.

2.

The control command with the c field = 8-F causes the input bus to
be ANDed with the selected file register as long as I03X is set.
This method allows inputting on the same command that resets DIXX
(providing the selected file has first been set to 'FF').

C = 8-F Input/Output Control
When c equals 8-F, the operations are associated with external I/O, and
the 3 low order bits of c are placed in the I/O control register. On the
same operation, data can be moved from the designated file register or the
input bus ANDed with the designated file register as determined by the
current contents of the I/O control register, to the designated file or
destination register. The data source is specified as follows:
I/O Control

Regi~ter

MOde

Source

0-3

Designated file register

4-7

Input bus ANDed with designated
file register

The values 4-7 correspond to the I03X control flip-flop. This flip-flop
must be set in order to transfer data from the input bit to the computer's
internal registers. Other than this restriction, the three I/O control
register bits can be used in any manner desired at the microprogramming
level of the Micro One and as long as standard I/O interface modules are
not used.

2-19

For purposes of standardization of common interface modules, and implementation of standard I/O software instructions, a convention for I/O codes
have been adopted as shown in Table 2-2.
Table 2-2.
cField
(Hex)

I/O
Mode

8

0
1
2
3
4

9

A
B

C
D
E

F

5
6
7

IOXX
3 2 1

Standard I/O Control Codes

Control Activity

000 None
o 0 1 Control Output (COXX/)
{output
o 1 0 Data Output (DOXX/)
Codes
o 1 1 Space Serial Teletype
1 0 0 Concurrent Acknowledge (CACK/)
1 0 1 I/O Acknowledge (IACK/)
{Input
1 1 0 Data Input (DIXX/)
Codes
1 1 1 Spare

2-20

Note that the
I/O mode is
directly
represented
as the 3
LSB's of
c field

I/O Examples:
1.

Generate following output waveform:

OUTPUT
BUS

COXX

----1

U DATA

DEVICE SELECT

_ _~, COXX

1'--_____________
DOXX

DOXX
CLOCK

2

3

4

5

6

7

8

9

10

11

I/O CONTROL
MACHINE
CODES

FLOW CHART:

DEVICE SELECT CODE-T

---'7090'
'1000'

'7080'
JUMP CAUSES 2
CLOCK DELAY

OUTPUT DATA BYTE-T

- - -'70AO'

'1000'
'7080'

2-21

2.

Input data according to following waveform:

OUTPUT
BUS .

---1

DEVICE SELECT
COXX

COXX

DATA READY

INPUT
BUS

DIXX

DIXX
INPUT
DATA
SAMPLE

L

L

------------------~~

CLOCK
I/O CONTROL
MACHINE
CODES

FLOW CHART:
DEVICE SELECT CODE- T

--

'7090'

'1000'
'7080'

Jump to next
inst. 2 clock delay
'70EO'

Jump to next
inst. 2 clock delay
Operate class
command
'7080'

For a very simple interface having only 3 data registers to set,
a single byte sequence will suffice for outputtting data.

2-22

3.

Output a byte to interface Latch No.2, where only 3 interfaces
latches exist in the system, using the simple interface technique
mentioned above.
I/O CONTROL
MACHINE CODES

FLOW CHART:

OUTPUT DATA BYTE-T

SET I/O MODE = 2

'70AO'

RESET I/O MODE

'7080'

On an input cycle it is necessary to wait at least one clock cycle after
generating DIXX to input data. The I/O controls a~e set in time at the completion of the control command. An input on the next clock would attempt to
transfer data before the interface unit has the correct response data ready
for input.
c field = B which is I/O mode 3 is used to set the serial teletype mode to
SPACE, which ties up the I/O channel.
c fielp

=

2.2.17

A

D which is I/O mode 5 is used to acknowledge interrupts.
Add

' - - - - Inhibit File Write

The selected operand is added to the contents of the file register designated
by f. The sum is placed in the file register (f), if * is an 0 bit, and in the
register designated by r.
The state of the carry out of the high order bit of the adder is placed in
Link. File 0 may not be selected by this command. The c field controls
selection of the operand, incrementing the result and modification of the
condition flags is as follows:

2-23

c-bits
765 4
1 x x x

Link Control: The content of LINK is added to the sum. The zero
condition flag can be reset but cannot be set, providing a
linked zero test over multiple bytes. A linked zero over mu1tip1ebytes functions as follows: Assume a 2-byte add is to be
performed. Two file registers contain a 16-bit number to be
added to another 16-bit number in core memory. The add is performed one byte at a time with the LINK used for carry into the
second add. On the first byte addition the condition flags are
modified. If the result of the first byte addition is not zero,
then of course the entire addition results in a non-zero condition, so that the zero condition flag should not be set on the
second byte add even if its result is zero. On the other hand,
if the first add produces a zero condition, the second may not,
therefore the zero condition flag should be reset table on the
second byte add.
The add function can be used to move data from a file to
another register by not selecting any input in the c field.

x 1 x x

Add One: One is added to the sum.

x x 1 x

Select T: The contents of the T register or the input bus are
selected as the operand. If the T register is not selected,
the operand is zero.

x

x x 1

Modifying Condition Flags: The condition flags are updated
according to the result.

Eight different examples have been selected to illustrate various c
states, data values, and destination registers. Since the L register
advances 1 unless it is the destination, its state will not be shown in
the affected register state chart. File 1 will be used in all examples.
The various functions selected for each example are shown in Tables 2-3, 2-4,
and 2-5.
Table 2-3.
The general form of the examples is
Add the contents of file 1 to one or more of the following:
Link, 1, T
Destination register choices are

T, F1 , or N
Link is always updated.
Condition flags are updated
on selected examples.
------------------------

------------.--~---~~--~,

-------------

2-24

Add command uses file 1 for all examples
Table of functions selected for each example.
Table 2-4.
c Field

Add
Link

Add
1

1. Add (file 1) to (T), put result
in T and f1' and update
condi tion flags.

0

0

2. Add (file 1) to (T), put result
in T, update condition flags.

0

0

Example

N

I

3. Add (file 1) to T, put result

0

0

in N, update condition flags.

N
VI

Modify
Condo
Flags

1

1

1

1

Select
T

I

Destination
Hexadecimal
Code for
c Field

1

1

I

I

Selected
Register
Symbol

Binary
Code

Hexadecimal
Code

3

T, fl

0001

1

3

T

1001

9

I
3

N

1011

B

6

N, f1

0011

3

8

fl

0000

0

5

fl

0000

0

A

fl

0000

0

6

T, fl

0001

II
I

4. Add (file 1) to T, +1, put

0

1

1

0

result in fl and N.
0

i
I

1

I

I

I

5. Add (file 1) to (LINK) , put
result in fl'

1

6. Add one to fl and put result

0

0

0
II

1

0

in f1' update C.

7. Add (f l ) to T and (LINK).
Put result in fl'
8. Add (file 1) to (T) plus 1.
Put result in T, fl'

l

I

I

Ii

I

I

I
I

1

0

1

I

0

I
I

0

I

I

II

I

1

0

I

I

I

I

1

I

\

I

II

I

I
I

I

I

I

I

1

I

Table 2-5.
The coding for the 8 Addition examples is shown below.

Example

Machine
Code
(Hex)

1

8131

AT

1, T, C

(f1) +

(T)~T,

f1, C

2

8139

AT*

1, T, C

(f1) +

(T)~T,

C

3

813B

AN*

1, T,

4

8163

AN

1, I, T

5

8180

A

1, L

(f1) + (T) +l~N, f1
(fl) + (L)-.f1

6

8150

A

1, I, C

(f1) + 1--...f1

7

81AO

A

1, L, T

(£1) + T +

8

8161

AT

1, L, T

(f1) + (T) +

Assembly
Language
Mnemonics

Flow Chart
Notation

c

(f1) + (T)---N, C

(L)~fl
l~T,

f1

NOT E
If both Link and 1 are selected as inputs, they are ORed instead of
added, thus the effective input is 1 regardless of the value of L.
Table 2-6.

Effected Register State Chart
Conditions

Example

File

T

Link

N

Before
After

'65'
00

'9B'
00

·...
1

2

Before
After

'65'
'65'

'15'
'7A'

·...
a

3

Before
After

'65'
'65'

'65'
'65'

·...
a

·...
·...
··...
...
·'CAY
...

4

,

Before
After

'65'
'66'

'00'
'00'

·...
a

·'66'
...

5

Before
After

'00'
'01'

··...
...

1

6

Before
After

' FF'
'00'

·...
·...

·...
1

Before
After

'00'
'01'

'00'
'00'

Before
After

'01'
'03'

'01'
'03'

1

7
8

a

1

a

I

I

I

·...
a

·...
·...
·...
·...
·...
·...
·...
·...

Zero

Neg

Ovf1ow

1

·...
a

a

a

·...
a

a

a

·...
1

1

1

··...
...
··...
...
·...
a

a

Table 2-6 shows the results for the eight ADDITION EXAMPLES:

2-26

...
··...
··...
...

Command execution time - 200 nsecs
2.2.18

S

SUBTRACT

The complement of the selected operand plus one is added to the contents of
the file register designated by' f. The difference is placed in the file
register (f) if * is a 0 bit, and in the register designated by r. The result
is a 2's complement subtraction. The state of the carry out of the high
order bit of the adder is placed in Link. File 0 may not be, selected by this
command. The c field controls selection of the operand, incrementing the
result, and modification of the condition flags as follows:
c-bits

7 6 5 4

Operation

1 x x x

Link control: The content of LINK is added to the sum. Selection of the LINK inhibits the automatic addition of one. The
zero condition flag cannot be set, providing a linked zero test
over multiple bytes. Refer to the add description for details
on linked zero test.

x 1 x x

Inhibit add one: If link control is not selected, one is automatically added to the result to produce a 2's complement subtraction. This control bit inhibits this addition, providing a
l's complement subtraction.
'

x x 1 x

Select T: This complement of the contents of the T register are
selected as the operand to the adder. If not selected, the
operand consists of a I-bit in each bit position.

x x x 1 Modify Condition Flags: The condition flags are updated
according to the result.
Affected:

F, LINK, Condition Flags, r.

If the input bus is enabled (I03X), this command will yield an unpredictable result because the complement of the input bus is not available.

2-27

Examples:
1.

Subtract zero from file 1.

Mnemonic

Machine Code

S 1

9100
Effected register states:
Register

Before

After

'00'

1
'00'

Link
file 1

Even though 0 is subtracted from 0, since 2's complement
adding is used there is a carry of 1 all through the adder
to the Link.
2.

Subtract T, 1 from file 1
Destination T Update condition flags
Machine
Code

Mnemonic

'9179'

ST* 1,D,T,C

Flow Chart
Notation

Effected register states:
~egister

Before
'31'
'31'

After
. '31'
'FF'.-2's complement for -1

o

010

! t \

Zero Neg Overflow
Command execution time -- 200 nanoseconds.
2.2.19

W WRITE MEMORY

R READ MEMORY

A

f

c

1*1

151413121110 9 8 7 6 5 4 3 2

r

I

1 0

The primary function of this command is to initiate a core memory cycle in
which one byte is transferred between the T register and core memory. The
address in core is determined by the contents of the M and N registers. File
o may not be selected by this command.
2-28

The lower two bits of the c field determine whether the memory operation is
read or write and whether the operation is a full or half cycle.
The c-bits control the type of memory operation as follows:
c-bits
765 4

Memory Access Operation

x x I x

Half Cycle: If this bit is a I-bit, a half cycle memory
operation is performed; otherwise a full cycle operation is
selected.

x x x I

Write: If this bit is a l-bit, a write memory operation is performed; otherwise a read operation is selected.

A full cycle takes 5 clock times.
A half cycle takes 3 clock times.
A full cycle read leaves the data in core unchanged.
A full cycle write causes the old data to be cleared so the new value is
unaffected by the old.
A half cycle read leaves all ones in the core location.
A half cycle write ANDS the data to be written with the data already in core.
If a half cycle write into a particular memory cell was preceded by a half
cycle read, the data value gets stored without modification since it is
ANDed with l's, left from the previous half cycle read.
A secondary function of this command is to simultaneously move data between
registers while initiating the memory cycle.
The contents of the file register designated by f is unaltered, incremented,
or decremented as controlled by the c field. The result is placed in the file
register (f) if * is a O-bit, and in the register designated by r. At the
same time, a read (R) or write (W) memory operation is initiated as controlled
by bit 4. If the operation is a memory read, the T register is cleared and
the accessed data is set into the T register after two clock cycle times.
Data to be written into memory must be placed in the T register during or
before the write memory conunand, if the operation is a half cycle write, and
by the first clock cycle time after the write memory command on a full cycle
write. The condition flags and LINK are not affected. Execution of the
memory command is delayed if the memory is in a busy condition from a previous
R or W command or DMA operation.
The bits of the c field control the transfer of data from the file register
as follows:

2-29

c-bits
7 6 5 4

Operation

o0

x x

Transfer: The contents of the file register are transferred
unaltered.

o1

x x

Decrement: The contents of the file register minus one are
routed as specified. If the M register is selected as the
destination and the content of LINK is a I-bit, the contents of
the file register are transferred without being decremented.
This provides a decrement with link control when M is the
destination.

lOx x

Add Link: The content of LINK is added to the contents of the
file register, and the sum is transferred as specified.

1 1 x x

Increment: The contents of the file register plus one are
transferred as specified.

This data transfer feature permits setting up one of the registers directly
involved with the memory access eM, N, or T) at the same time the memory
cycle is initiated. There are some timing restrictions pertaining to modification of M, N, or T registers during a m~ory cycle. Some of the functions
have logic interlocks to prevent errors, and some do not. These restrictions
must be carefully considered with respect to data errors, and unexpected program time delays. The restrictions must be carefully considered with respect
to data errors, and unexpected program time delays. The restrictions are as
follows:
1.

Attempting to change M or N while a memory cycle is in progress
stops the computer clock until the memory cycle is over. No data
errors result. Either M or N can be changed by the command initiating
the memory cycle without causing delay.

2.

Accessing T during a read cycle causes the clock to stop until the
new data value from core is correctly in T. This causes delay but
no data error.

3.

Changing T during a write cycle will cause a delay i f it occurs
during WTXX/ and it may cause a data error if it occurs on the
clock immediately preceeding WTXX/.

The memory access restrictions are specifically defined in the following chart:

2-30

Full Cycle
Read

Full Cycle
Write

Half Cycle
Read

---

Delay from changing
M and N

Up to 4
clocks

Up to 4
clocks

Delay due to T
access

Up to 2
clocks

o clocks

Data in T available
(on Read)

3rd clock
after
memory
connnand

-

I

T must be loaded by

Half Cycle
Write

Up to 2
clocks

Up to 2
clocks

Up to 2
clocks

o

2nd clock
after
memory
command
1st clock
after
memory
cycle
connnand

(on Write)

T must stay loaded

Memory
Cycle
Connnand

i

2 clocks
after

until (on Write)

I
I

I me=ry

connnand

----

----

--~---~

clocks

------

I

----~--

Timing Diagram for Memory Accesses:

I

t

MEMORY
COMMAND
CLOCK
M & N MUST
BE SET ON
OR BEFORE
THIS CLOCK
T MUST BE
SET ON OR
BEFORE
THIS CLOCK
ON A WRITE
HALF CYCLE
COMMAND

I

1ST
CLOCK
AFTER
MEMORY
INST.

I

I
I
I

I
I
I
I
I T MUST BE I
I SET ON OR I

I
I

BEFORE
THIS CLOCK
ON A WRITE
FULL CYCLE
COMMAND

I
I

t

t
2ND
CLOCK
AFTER
MEMORY
INST.

3RD
CLOCK
AFTER
MEMORY
INST.

I T CAN BE
I CHANGED

I ON OR AFTER

THIS CLOCK
TMUST
ON A WRITE
NOT BE
COMMAND
CHANGED
ON THIS
DATA IS
CLOCK ON
AVAILABLE
A WRITE
liN TON
COMMAND THIS CLOCK
AFTER A
READ
COMMAND

I
I

I

2-31

t

I

I

I
4TH
CLOCK
AFTER
5TH
MEMORY \ CLOCK
INST.
\
M, NAND T
CAN BE
CHANGED ON
THIS CLOCK
WITHOUT
DELAY OR
ERROR

I
I

I
I

I
I
I

Examples:
Machine
Code

Example
1)

2)

Full cycle write
(file 1) + l---'N, fl

Half cycle read
(file 2)
~ M, f2

f
i
o 1
p e c

c

d
e
s
t

A 1 D3

A 2 2 2

Mnemonics
WN

RM

1, I

2, H

c Field Binary
Functions and Codes for
Memory Commands
Increment

Full cycle
write

1

o

Transfer
0

3)

Half cycle write
(file 2) + (Link)-.M, f2

A 2 B 2

WM

I

w

4)

N

5)

6)

7)

Full cycle write
~ T, f3
(file 3)
Half cycle read
(fl) - l----'N
followed
(f3) + (T)------+T, f3
Half cycle write followed
by loading T
(f3)------.T, f3

A3ll

WT

3

Inhibit file write
A 1 6 B RN'~
8 3 2 1 AT

0

Transfer
0

~

0

2, L, H Add Link
1

N

1

0

Decrement

1, D, H 0
3, T

1
-

Transfer
A 0 3 0
8 301

Full cycle read, decrement
(file 1) and transfer to M
(J 1) - 1 ----. M, f 1
A 1 4 2

W
AT

0, H
3

0
-

0

Decrement
RM

1, D

o

1

General Description

D

Full cycle write memory is initiated
and N register is updated as well as
fl'

Half cycle
read
1
0

2

Half cycle read memory is initiated
while M register is updated directly
from f 2 •

Half cycle
write
1
1

B

Half cycle write memory is initiated
while file 2 and M are updated by
adding (LINK).

Full cycle
write
1
0

1

Full cycle write memory is initiated,
T is updated from f3 on the same
command.

1

Half cycle
read
0
1
Half cycle
write
1
1
-

-

Field
Hex.
Code

6

-

3
-

Full cycle
read

o

o

4

Half cycle read memory is initiated,
followed by T register access on the
next instruction. This will cause a
program delay until the third clock.
Half cycle write memory is initiated,
followed by loading T on next
instruction. No time delay occurs,
but data written into memory may
be incorrect.
A full cycle read is initiated (fl)
is decremented and transferred to M.
If (LINK) = 1 the contents of the
file are transferred without being
decremented.

2.2.20

COpy

C

f

B

C

1*1

r

1

1514131211109876543210

The selected operand is placed in the file register designated by f, if * is
a O-bit, and in the register designated by r. The LINK is not affected. The
c filed controls selection of the operand, incrementing the operand, and
modification of condition flags as follows:
c-bits
765 4

Operation

1 x x x

Link Control: The content of LINK is added to the sum. The
zero condition flag can be reset but cannot be set, providing
a linked zero test over multiple bytes.

x 1 x x

Add One: One is added to the sum.

x x 1 x

Select T: The contents of the T register or input bus are
selected as the operand. If the T register is not selected,
the operand is zero.

x x x 1

Modify condition flags: The condition flags are updated
according to the result.

Affected:

F, Condition Flags, r.

This command is used to transfer T to a selected file register, with the option
of incrementing or adding LINK while transferring. It is also used for
inputting data, because when the input control flip flop (I03X) is set during
an input mode. operate commands selecting T get the input bus instead.
The command can be used to test the condition of T by selecting fO as the file
register (which is unaffected) and setting the modify condition flag in the c
field.
The command can also be used to clear one file and another selected register
by not selecting any input in the c field.
Command Execution Time -- 200 nanoseconds.
File register 1 is used for all examples except setting condition flag example.
Examples of Copy Command:
2.2.21

o

OR

c

f

15141312111098 7 6 5 4 3 2 1 0

2-33

Machine
Code
f
d
e
i
o 1
s
p e c t

(T)--. f1

Destination for
Copy Corrunands

c field for Copy Corrunands

Link

Add
1

Select
T

Mod.
Condo
Flags

Hex.
Code

B1 2 0

0

0

1

0

2

(T) + 1 - - . f1' N

B1 6 3

0

1

1

0

(T) +

B1 A0

1

0

1

0~f1' N

B1 0 3

0

0

(T)----. fO' C
Set Condition Flags

B1 3 0

0

0

Set DIXX

7 0 E 0

K

0, X'E'

Delay

1 0 0 0

LZ

X'OO'

(T)~f1' T

B

CT

1, T

Reset DIXX

708 0

K

0, 8

Examples

(LINK)~f1

Binary
Code

Hex.
Code

f1

0000

0

C

I, T

(T) is transferred, unaltered
to file 1.

6

f1, N

0011

3

CN

I, I, T

(T) is incremented and transferred to file I, and to the
N register.

0

A

f1

0000

0

C

1, T, L

(T) is added to (LINK) and
transferred to fl.

0

0

0

f1, N

0011

3

CN

1

File 1 and N registers are
cleared because no input is
selected.

1

1

3

fO

0000

0

C

0, T, C Condition flags are set
according to the state of (T) •
File 0 can't be loaded by this
instruction so is unchanged.

Selected
Registers

Mnemonics

N

General Discussion

I

w
.p..

1 2 1

0

0

1

0

2

f1, T

0001

1

The input flip flop is set by
the DIXX command, so the copy
T command transfers the Input
bus to file 1 and to T.

The selected operand is logically inclusive-ORed on a bit-for-bit basis with
the contents of the file register designated by f and the result is placed
in the file register, if * is a O-bit, and in the register designated by r.
The LINK is not affected. The c field controls selection of the operand and
modification of the condition flags as shown below:
c-bits
7 6 5 4

Operation

1 x x x

Link control: The zero condition flag can be reset but cannot be set, providing a linked zero test over multiple bytes.
See the description of the add command for a detailed description of linked zero test.

x 1 x x

Select complement T: The complement of the contents of the T
register is selected as the operand. If the T register is also
selected, the effective operand contains a 1-bit in each bit
position.

x x 1 x

Select T: The contents of the T register or Input bus are
selected as the operand. If neither the T register nor the
complement of the T register is selected, the operand is zero.

x x x 1

Modify Condition Flags: The condition flags are updated
according to the result.

Affected:

F, Condition Flags, r.

If both complement T and T are selected, the operand is alII's.
input bit is enabled (I03X), complement T must not be selected.

If the

This command is used for the general function of logical ORing as needed in a
microprogram. It also has the following specific applications: Setting flag
bits without disturbing other bits (with the OR function it doesn't matter if
the flag is already set since there is no carry); moving data from a file to
another register by not selecting any operand; setting alII's in a file
register and/or one other selected register by selecting both T and T complement as operands; combining two numbers into one byte, such as for assembling
hexadecimal digits into multiple digit numbers after the digits have been input
to the computer as a string.
Bit pattern example of OR function:

file 1
T
Result

Binary

Hexadecimal

01101000
00110100
01111100

'68'

Command Execution Time -- 200 nanoseconds.

2-35

'34'
'7C'

File register I is used for all examples.
Examples of OR command:

Machine
Code
f
d
e
i
s
o 1
p e c t

Link

Select
Compo
T

C1 2 9

a

a

(f 1 ) V O---..N, f1

CIa 3

a

(f 1 ) V

C1 2 a

(f 1 ) V (T), (T)---.N

(f 1 ) V (T) (T)-+f 1

Destination for
OR command results

c field for OR commands
Mod.
Condo
Flags

Hex.
Code

1

a

2

a

a

a

a

a

1

C1 6 B

0

1

C1 6 0

0

(f 1 ) V (T)--.Link, C C 1 B 8

1

Flow Chart Notation
(f 1 ) V

(T)~T

(T)~f1

Select
T

Selected
Registers

Binary
Code

Hex.
Code

Mnemonics

General Discussion

1

1001

9

OT* 1, T

OR (file 1) with
(T), inhibit file
write put result
in T.

a

N, f1

0011

3

ON

1

Move (file 1) to N
by ORing with a
and putting result
in N.

a

2

f1

0000

a

0

1, T

OR (file 1) with
(T) and put result
in file 1.

1

a

6

N

1011

B

ON* 1,T,F

Set N = FF (all
ones) by ORin£
(f1) with T, T and
putting result
in N.

1

1

0

6

f1

0000

a

0

Set f1 = FF by
ORing f1 with T, T
and putting result
in fl.

a

1

1

B

none

1000

8

0* 1, T,L,C

N

I

w

0'\

--

~-.-.--

._--.-------

--~.-~~~-".--

-

--

1,T,F

Perform conditional
test on (f1) V (T)
without changing f1
or T Select L to
perform linked zero
test with a previous command.

2.2.22

x

EXCLUSIVE OR

Inhibit File Write

The selected operand is logically exc1usive-ORed on a bit for bit basis with
the contents of the file register designated by f and the result is placed in
the file register, if * is aD-bit, an& in the register designated by r. The
LINK is not affected. The c field controls selection of the operand and the
modification of the condition flags as shown below:
c-bits
Operation

7 6 5 4

1 x x x

Link Control: The zero condition flags can be reset but cannot
be set, providing a linked zero test over multiple bytes. See
the description of the Add command for a detailed description
of linked zero test.

x 1 x x

Select Com1ement T: The complement of the contents of the T
register is selected as the operand. If the T register is also
selected, the effective operand contains a l-bit in each bit
position.

x x 1 x

Select T: The contents of the T register or input bus are
selected as the operand. If neither the T register nor the
complement of the T register is selected, the operand is zero.

x x x 1

Modify Condition Flags: The condition flags are updated
according to the result.

Affected:

F, Condition Flags, r.

If both complement T and T are selected, this command produces the one's
complement of the value in the file register. If the input bus is enabled
(I03X), complement T must not be selected.
This command is used for the following functions: general purpose exclusive
OR; data comparison, ones complementing; and flipping selected bits such as
controls and status flags.
Bit pattern example of exclusive OR.

file 1
T

Result

Binary

Hexadecimal

01101100
00011010
01110110

'6C'
'lA'

Command execution time -- 200 nanoseconds.

2-37

'76'

File register I is used for all examples.
Examples of Exclusive OR command:

Example
Flow Chart Notation

Machine
Code
f
d
i
e
o 1
s
p e c t

(£1) ¥ (T)---..T

D1 2 9

Destination for Exclusive
OR command results

c field for OR commands

Link

Select
Compo
T

Select
T

Mod.
Condo
Flags

Hex.
Code

0

0

1

0

2

Binary
Code

Hex.
Code

T

1001

9

XT* 1,T

Selected
Registers

Mnemonics

-

N

I

w

General Discussion
Exclusive OR (file
1) with (T)
inhibit file
write, put result
in T.

(£1) ¥ O-.+N, Fl

D1 0 3

0

0

0

0

0

N, fl

0011

3

XN

1

Move (file 1) to N
by exclusive
ORing with 0
(same result as
OR), put resul t
in N.

(f l ) ¥ (T)---.f l

D1 2 0

0

0

1

0

2

fl

0000

0

X

1,T

Exclusive OR (file
1) with (T) and
put result in
file 1.

(f l ) ¥ (T), (T)-+T

D1 6 B

0

1

1

0

6

N

1001

9

XT* 1,T,F

Produce ones complement of (f l )
and place result
in T.

fl ¥ (T), (T)-+f l

D1 6 0

0

1

1

0

6

fl

0000

0

X

1,T,F

Produce ones complement of (£1)
and put it back
into fl'

C D1 B 8

1

0

1

1

B

none

1000

8

x*

1,T,L,C

Perform conditional
test and linked
zero test on (f l )
It (T) without
changing (f 1) or

00

(f 1 ) V

(T)~Link,

..

(T) •

2.2.23

N

AND

File Write

The selected operand is logically ANDed on a bit-for-bit basis with the contents
of the file register designated by f and the result is placed in the file
register, if * is a O-bit, and in the register designated by r. The LINK is
not affected. The c field controls selection of the operand and modification
of the condition flags as shown below:
c-bits
7 6 5 4

Operation

1 x x x

Link control: The zero condition flag can be reset but cannot
be set, providing a linked zero test over multiple bytes. See
the description of the add command for a detailed description
of a linked zero test.

x 1 x x

Select complement T: The complement of the contents of the T
register is selected as the operand. If the T register is also
selected, the effective operand contains a I-bit in each bit
position.

x x 1 x

Select T: The contents of the T register or input bus are
selected as the operand. If neither the T register nor the
complement of the T register is selected, the operand is zero.

x x x 1

Modify condition flags: The condition flags are modified by
execution of the command. Updated according to the result.

Affected:

F, Condition Flags, r.

If both complement T and T are selected and AND command moves the data, unchanged
from the selected file register to the designated destination register. I f the
input bus is enabled (I03X), complement T must not be selected.
The AND command is used for the following functions: General purpose ANDing
of files and T; resetting selected flag or status bits, without disturbing
other flags; and marking out parts of a byte.
Bit pattern examples of the AND function.

file 1
T
Result

Binary

Hexadecimal

01101011
10101101
00101001

'6B'
'AD'
'29'

Command execution time - 200 nanoseconds.
2-39

File register 1 is used for all examples.
Examples of AND Command:

Machine
Code
f
d
i
e
o 1
s
p e c t

(f l ) /\ (T)---+f l

Destination for
And command results

c field for And connnands

Link

Select
Compo
T

Select
T

Mod.
Condo
Flags

Hex.
Code

E 1 2 0

0

0

1

0

2

(f l ) /\ O--.N, fl

E1 0 3

0

0

0

0

(f l ) /\ (T)-+T

E 1 2 9

0

0

1

(f l ) /\ (T), (T)-.. N

E 1 6 B

0

1

1

(f l ) /\ (T)-+-f l

E 1 4 0

0

1

0

0

4

fl

0000

0

N

1,F

is anded wi th
(T • The result
is put into fl.

(f l ) /\ (T)-+- Link, C E 1 B 8

1

0

1

1

B

none

1000

8

N

1,T,L,C

(f l ) is anded with
(T) • The result
is not put in any
register. Only
the condi t ion
flags are set. Use
of link results in
multi byte zero
test.

Example
Flow Chart Notation

Selected
Registers

Binary
Code

Hex.
Code

fl

0000

0

N

1,T

(fl) is anded with
(T) • The result
is put into fl'

0

N, fl

OOll

3

NN

1

(f l ) is anded with
O. The result
(which is 0) is
put into N, and fl'

0

2

T

1001

9

NT* 1,T

(fl) is anded with
(T) • The result
is put in T and
inhibited from fl'

0

6

N

lOll

B

NN* 1,T,F

(!1) is anded with

Mnemonics

N

!.
o

-

General Discussion

(T) which is same
as anding with FF
(all ones). Result
is put in Nand
inhibited from fl'

------~--

--.--------------~.------.- ..

-

(f})

file 1
T

Result

Binary

He:xadec:lma1

01000010
10111111
00000010

'42'
'BF'
'02'

\set
file 1
T

(Select T complement)
Result
file 1
T, T complement
Result

10100101
11010011
(00101100)
00100100
10100101
11111111
10100101

a flag

'AS'
'D3'

(' 2C')
'24'

'AS'
'FF'

'AS'

Command Execution Time -- 200 nanoseconds.
2.2.24

H

SHIFT

Inhibit File Write

The contents of the file register designated by f is shifted left or right one
bit position and placed in the file register, if * is a O-bit, and in the
register designated by r. The high order or low order bit which is shifted
off is placed in LINK and in the overflow flag if the modify condition flag is
selected. The c field controls the direction of shift, entry of an end bit,
and modification of the condition flags as follows:
c-bit
7 6 5 4

Operation

1 x x x

Link control: The content of the LINK is inserted into the
vacated low order or high order bit position. The zero
condition flag can be reset but cannot be set, providing a
linked zero test over multiple bytes. See the description of
the add command for a detailed description of the linked zero
test.

x 1 x x

Insert 1: A 1-bit is unconditionally inserted into the vacated
low order or high order bit position; otherwise a O-bit is
inserted unless the contents of LINK is selected.

x x 1 x

Shift right: if bit 5 is a 1-bit, the operation is a right
shift; otherwise a left shift is performed.

2-41

c-bit
7 6 5 4
x x x 1

Affected:

Operation
Modify condition flags: The zero and negative flags are
updated according to the result. The content of the bit
shifted out is placed in the overflow flag.
F, LINK, Condition Flags, r.

This command provides great flexibility for various shifting functions mechanized by microprogramming. These are as follows:
•

Left or right shifting;

•

End around carry or no end around carry;

•

Arithmetic or logical shifts;

•

Multiple byte shift register implementations in either file registers
or core memory;

•

Pattern rotations by successive shifting of 8 files, one bit at a
time, and assembling into a 9th file;

•

Set or reset link bit by shifting with no destination register.
Bit pattern examples of shift command.
All examples are for shift (f1) and put result back in fl.

Instruction

I
I

Sequence
Number

File 1
Binary

Link

File 1
Hexadecimal

Condition
Flags

Shift Right

before
after

01101001
00110100

0
1

'69'
'34'

-------

Shift Left

before
after

01101001
11010010

1
0

'69'

----

Shift
Right
Enter
Link

before
after

00111000
10011100

1
0

'ge'

Shift
Left
Enter 1

before
after

10001010
00010101

0
1

'8A'
'15'

Shift Left
Modify
Condition
Flag

before
after

11001011
10010110

0
1

'CB'
'96'

011

Shift Right
Modify
Condition
Flag

before
after

00000001
00000000

0
1

'01'
'00'

101

2-42

'D2'

----

'38'

-------

-~-

...

'

---

2.2.25

EXECUTE

E

o

I

1514131211109876543210

The 8-bit contents of the U register are ORed with the 8 high order bits of
the execute command to form an effective command. This provides a means of
partially modifying the contents of a read only storage location. The ~Ring
is performed before the output of the read only storage is gated into the R
register. The meaning of bits present in positions 0-11 is dependent upon the
desired effective operation code after the modification. Due to the lookahead feature of the read-only memory, the new contents of the U register are
not available until after one machine cycle following the transfer of data to
it.
The execute command provides a means for program modification of a command.
This capability is used for many different functions, three of which are as
follows:
•

Indexing of file registers in a program loop.

•

Having a general purpose instruction which may take on different
specific functions, such as load a register, add to the register,
AND with the register, etc., depending on program variables.

•

Selection of alternate file registers depending on program variables.

Sometimes a combination of two of the above is used.
The U register can be set with the load U command, or by being designated as
the destination register of an operate class command, such as Add, Copy, etc.
For the file register indexing, a separate file register is designated as an
index register. It is loaded with an initial value, then incremented, with
the result being put in U each time through the loop, until the loop is
exited.
Examples of execute commands:
U register
EXecute Command
Effective Command

'84'
'0021'~------ This command is stored in

ROM

'8421'

ET

0, 2
~f4 T

4, T'

2-43

Lnstruction codes for bit pattern examples of shift command
These examples are the same except for additional Destination Registers

Flow Chart Notation

Machine
Code
f
d
i
e
o 1
s
p e c t

Insert
Link

Insert
1

Shift
Right

Mod.
Condo
Flags

Hex.
Code

Selected
Registers

Binary
Code

Hex.
Code

Shift right
result to
f l , T.

(fl)@R ----- f l , T

F 1 2 1

0

0

1

0

Z

fl , T

0001

1

HT

1,R

(file 1) is shifted right
one bit, link, or 1 are
not inserted. The result
is put in T and fl.

Shift left
result to
fl·

(fl)@L--.. Fl

FlO 0

0

0

0

0

0

fl

0000

0

R

1

(file 1) is shifted left
one bit, link or 1 are
not inserted. The result
is put in fl.

Shift right
insert link
result to
f l , N.

(fl)@R+LK--.fl' N F 1 A 3

1

0

1

0

A

fl , N

0011

3

HN

1,R,1

(file 1) is shifted right
one bit, (Link) is
inserted in vacated left
hand bit. Result is put
in fl and N.

Shift left
insert 1
result to
f l , M.

(f 1 ) @L+l ---+ f 1 ' M

F 1 4 2

0

1

0

0

4

fl , M

0010

2

HM

1, I

(file 1) is shifted left
1 is inserted into the
vacated right hand bit.
Result is put in fl and
M.

Shift left
modify condo
flag. Result
to fl.

(fl)@L ~fl' C

F 1 1 0

0

0

0

1

1

fl

0000

0

H

1,C

(file 1) is shifted left.
The result is put into
file l. Condition flags
are modified.

Shift right
Modify condo
flag. Result
to fl·

(fl)@R--.F'l' C

F 1 3 0

0

0

1

1

3

fl

0000

0

H

1,R,C

(file 1) is shifted right.
The result is put into
file l. Condition flags
are modified.

Example

Destination for
Shift Command results

c field

Mnemonics

General Discussion

Incrementing the U register value leaves the command the same, but changes the
file register number to 5. If this continued to file F, the next increment
would· change the command to a subtract.
U Register

'Fl"

Executive
Command

This command is stored in ROM
0,2
'0020'/ E
{ ~hift Right file 1
l,R

'Fl20'

Effective
command

The meaning of the cfield of the lower two hexadecimal digits in the
execute command changes with the OP code value in the U register. Therefore
the c field is left as a digit in the MNEMONIC for the execute command.
Commands can also be modified by the U register by using the operate commands
with a 7 in the destination register. This method is advantageous if there
are two variable functions to be done in one loop, with one U register
setting. For example, a program may be indexing through a set of files
where it is necessary to add to a file, and shift the same file in the same
program loop. This could be mechanized as follows:
(f F )

+

l---..~

U, fF

--- Nap
(fo)

+

(T)----1~
.. fO,

(F 0)

@

R

7 (OR U with command)

Destination

• F0' Destination

=7

The coding for this is:
Machine
Code

Mnemonic

'8F46'

AU F, 1

'8027'

AS 0, T Add to file 0

'F027'

HS 0, R

another command

Shift file 0

Assume U = '04' after the first command.
The effective commands following are:
'8427'

Add to file 4

'F427'

Shift file 4 right

2-45

This method of command modification has the limitation of no destination
register since the destination register code position is tied up selecting U
as a modifier to the command. The execute connnand does not have this
restriction.

COMMAND REFERENCE TABLE
Mnemonic
Command
Load T

Comments

Operation Code

11/19

LT

I

Literal

151413121110987 6 5 4 3 2

Load M

LM

12

Literal

15141312111098 7 6 5 4 3 2

Load N

LN

I,

13

Literal

15141312111098 7 6 5 4 3 2

Load U

LU

16

Literal

15141312111098 7 6 5 4 3 2

Load Zero

LZ

10

Literal

I

1 0

I

1 0

I

1 0

I

1 0

I

151413121110987 6 5 4 3 2 1 0

Load Seven

LS

Literal

17

151413121110 9 8 7 6 5 4 3 2

7
7
7

7
7

0
0
0
0
0
0
1
2
4

7

S

F

7
7
7

2-46

0

I

1 0

NoOp
Enable Serial TTY

2
2
4
S

0
0
0
0

Reset T 8
Set TS
Disable} External
Enable
Interrupts
Disable} Real Time
Enable
Clock
Load Protect Bit
Halt

Mnemonic
Operation Code

Command
JUMP

Literal

14

JP

Comments

I
I
I

ODD-OFF

15 14 1312 11 10 9 8 7 6 5 4 3 2 1 0

15

Literal

100-1 FF

15141312111098 7 6 5 4 3 2 1 0

Literal

1C

200-2FF

1514131211109 8 7 6 5 4 3 2 1 0

10

Literal

300-3FF

1514131211109 8 7 6 5 4 3 2 1 0

Load File

LF

2

f

Literal

151413121110 9 8 7 6 5 4 3 2 1 0

Add To File

AF

Test Zero

TZ

Test Not Zero

TN

Compare

3

f

Literal

I
I

151413121110987 6 5 4 3 2 1 0

4

Literal

f

151413121110 9 8 7 6 5 4 3 2

CP

5

f

Literal

151413121110 9 8 7 6 5 4 3 2

6

f

1 0

Literal

1514131211109 8 7 6 5 4 3 2

2-47

1 0

1 0

Mnemonic

Control

Add

Comments

Operation Code

Command

K

Ar

7

1

f

1

c

1*1

8

0

No Op

1

Enter Sense SW

2

Shift Right 4

4

Enter I nternal Status

7

Enter Console SW

8
9

Clear I/O

A

8

Set DOXX (in MICRO ONE/20)
Space Serial TTY

C

Set CACK (in MICRO ONE/20)

Set COXX (in MICRO ONE/20)

D

Set lACK (in MICRO)

E

Set DIXX (in MICRO)

F

Spare

f

c
X X x
x 1 x x
x x 1 x
x x x

Sr*

I

15141312111098 7 6 5 4 3 2 1 0

1*1

15141312111098 7 6 5 4 3 2

Subtract

r

Operand
Field

9

c

f

I

r

1 0

Link

L

Add 1

I

Select T

T

Modify Condition Flags C

1*1

151413121110987 654 3 2

r

I

1 0

x
Link
x 1 x x
Decrement
x x 1 x
Select T
x x x
Modify Condition Flags
X X

2-48

L
D
T
C

Mnemonic
Operati on Code

Command
Memory

Wr
Rr

I

A

c

f

Comments

Operand
Field

1

1*1

1514131211109 8 7 6 5 4 3 2 1 0

Link

L

x 1 x x

Decrement

D

x x

Increment

I

x x 1 x

Half Cycle Operation

H

x x x

Write Operation (supplied by OP Codel

X X x

Copy

Cr

I

B

f

c

1514131211109 8 7 6 5

C

Or*

f

r

I

1 0

x 1 x x

Add 1

,

x x 1 x

Select T

T

x x x

Modify Condition Flags

C

X X x

OR

1*1
4 3 2

1

c

L

Link

1*1

r

I

1514131211109 8 7 6 5 4 3 2 1 0

X X x

x 1 x x
x x 1 x
x x x
Exclusive
OR

Xr

I

D

c

f

15 14 1 3 12 11 1.0 9 8 7 6 5

X X x

x 1 x x
x x 1 x
x x x

Link

L

T

F

T
Modify Condition Flags

C

1*1
4 3 2

r

T

I

1 0

Link
T

L
F

T
Modify Condition Flags

C

T

Mnemonic
Operation Code

Command

AND

E

Nr*

f

c

Comments

1*1

X X x
x 1 x x
x x 1 x
x x x

Shift

Hr*

I

F

f

c

Link

L

T

Modify Condition Flags

C

1*1

x
x 1 x x
x x 1 x
x x x

2-50

1 0

T
T

1514131211109 8 7 654 3 2

X X

]

r

1514131211109 8 7 654 3 2

Operand
Field

F

r

I

1 0

Link

L

Insert

I

Shift R

R

Modify Condition Flags

C

SECTION 3
I/O AND MEMORY INTERFACE

SECTION 3
MICRO-ONE I/O AND MEMORY INTERFACE
3.1

GENERAL DISCUSSION

There are three primary input/output interfaces on the Micro-One computers for
connecting external equipment to the interfaces: Byte I/O, Direct Memory
Access and Serial I/O. In the Micro-One, I/O and memory operations are
performed under control of microcommands. A standard set of I/O macroinstructions is used for performing program-controlled and concurrent I/O
operations.
Information in Sections 3 through 8 discuss I/O and memory, and are arranged
as follows: Section 3 provides general information on the various Micro-One
I/O interface systems; Section 4 provides a detailed description of the programmed Byte I/O interface system, including programmed transfers, block automatic (concurrent) transfers, and external interrupts. Section 5 describes
the CPU Memory interface; Section 6 contains a detailed description of the DMA
port; Section 7 describes the Serial I/O interface, and Section 8 is an I/O
connector signal list. Section 9 is an I/O and memory term glossary.
3.2

I/O ORGANIZATION

Figure 3-1 is a block diagram of a typical Micro-One serial computer system
showing the three primary I/O interfaces: Serial I/O channel, Parallel Byte
I/O channel, and DMA port. These three interfaces provide the system designer
with the flexibility to structure efficient I/O systems for a wide range of
applications. The serial I/O interface, although most commonly used with a
teletype, can be used for other bit-serial devices as well. The byte I/O
interface can be used by controller circuit boards that. plug into the mainframe ch~ssis. The DMA interface provides the method for external I/O devices
to communicate directly with core memory. The user can design his own interface controller for the DMA port, or use standard Microdata DMA interfaces.
3.3

SERIAL I/O INTERFACE

The serial I/O interface is designed primarily for communicating with a fullduplex teletype. Character assembly and disassembly, with all timing and
synchronization, are performed at the microprogram level. Two macro instructions, Input Byte Serially (IBS) and Output Byte Serially (OBS), are used for
communicating with the serial channel device.
Note that the Micro-One firmware (-13) for these instructions was designed to
operate with a 110-baud teletype. The designer can alter the timing of the
serial channel for teletype (or other serial device) compatibility by performing a simple change in firmware.
3.4

BYTE I/O INTERFACE

The byte I/O interface provides for transfer of bytes over a party line I/O
bus under microprogram control. The standard Micro-One computer firmware
provides both programmed and concurrent I/O transfer capability, along with
a priority interrupt system.
3-1

r-; -

~

PERIPHERAL DEVICE/CONTROLLER

- - - -,- - - - --

CORE MEMORY
(8K BYTES)

-;-]
DIRECT
MEMORY
ACCESS
PORT

CORE MEMORY
(8K BYTES)

MEMORY BUS

MEMORY
CONTROL LOGIC
TO
DEVICE - - - - I

SERIAL
I/O
CHANNEL

DMA
CONTROL
LINES

CENTRAL
PROCESSOR
UNIT (CPU)

BYTE I/O BUS

r

I

I/O LINE DRIVER

AND RECEIVER
I OPTION
.
L __

DEVICE
CONTROLLER

DEVICE
CONTROLLER

DEVICE
CONTROLLER

_-.J

PERIPHERAL DEVICE

PERIPHERAL DEVICE PERIPHERAL DEVICE

fEXtERNALDM:ES-- -

-

-

-

-

-

I ~'____~____~______________-W~_BY_T_E I/_O_B_U_S_(_E_X_T_E_N_D_E_D~)~
I
II
__

-

-

-

-

__________________

-

-

-,

~~____~

UP TO

8 UNITS

L
,

~I~~

__

_.-..- _ _

~

-...lI

I
UP TO 64 INTERRUPT LINES

Figure 3-1,

PERIPHERAL DEVICE

PERIPHERAL DEVICE

Typical Micro One Series I/O Configuration
3-2

I
I
II

Data transfers through the byte I/O interface are basically two-phase
operations. First, a control byte is placed on the byte I/O bus before the
actual transfer of data. The control byte contains an I/O controller device
address and a device order code for the type of operation to be performed
during the transfer (data transfer, status/function transfer, etc.)
All controllers on the bus examine the device number, but only the addressed
controller accepts the control byte and logically connects itself to the bus
for the subsequent data byte transfer. During the second phase of the byte
I/O operation a single byte is transferred to or from the I/O controller.
After each byte transfer, the controller disconnects itself from the bus.
3.4.1

Program-Controlled I/O

In standard firmware sets, such as the Micro-One/21, two basic instructions
(one for input and one for output) are used for transferring information to
and from controllers on the byte I/O bus under programmed control. These
instructions permit transfers between the device controller and the A Register,
B Register, or Memory. Up to eight types of input and eight types of output
instructions may be defined for a particular controller. Generally these
include function output, data output, status input, and data input, and are
determined by a 3-bit device order in the control byte of the I/O instruction.
3.4.2

Concurrent I/O

The concurrent I/O feature provides the capability for automatic block
transfers between core memory and I/O controllers connected to the byte I/O
interface. The concurrent mode transfer rate is a function of the firmware
set used in the computer. As an example, standard Micro-One/21 firmware
performs concurrent transfers at rates up to 20,000 bytes per second.
Once started, the transfers are fully automatic and proceed without program
intervention. Concurrent I/O operations take priority over instruction
execution, and force a break in the execution of long instructions such as
multiply, divide, and shifts to ensure that concurrent I/O servicing delays
are not excessive. Concurrent I/O operations make use of pairs of two-byte
address control words stored in dedicated core memory locations. One pair of
address words is used by each controller. The control words, which contain
the address of the current byte being transferred and the address of the last
byte in the block, are initially set by the software program and thereafter
are manipulated automatically by firmware for each byte transferred.
3.4.3

External Priority Interrupts

The external interrupt system of Micro-One series computers operates through
the byte I/O interface in both the computer mainframe and expansion chassis.
Interrupts can originate from device controllers or from the optional Priority
Interrupt interface board connected to the byte I/O bus. The Priority Interrupt interface board provides control of eight external interrupt signals.
The byte I/O interface contains a single external interrupt request line,
common to all I/O controllers on the byte I/O bus, and a priority line that
is carried sequentially through all controllers on the bus. Each I/O
controller receives priority from the preceding controller in the priority

3-3

chain. Priority is passed a long to the next controller in line only if the
previous controller is not ready to request an interrupt. When a controller
receives priority and is ready to request an interrupt, it stops the progression
of the priority signal and activates the interrupt request signal.
After receiving acknowledgment of the interrupt request, the interrupting
controller places an address byte on the I/O bus that the processor uses to
transfer program control to the proper interrupt servicing routine.
3.4.4

Direct Memory Access DMA Port

All Micro-One series computers contain a DMA Port through which data can be
transferred between core memory and I/O devices at rates up to one million
bytes per second. The DMA Port provides this high transfer rate and low
access latency time, for use with high-speed, demand-type devices such as
rotating memories.
The DMA Port consists of the memory bus and various DMA memory control lines
which are available in the computer mainframe. It is up to an external DMA
controller to Eanipulate the control lines and place data and addresses on the
memory bus at the proper times when DMA transfers take place. The DMA
controller may be designed and constructed by the user, or a standard Microdata DMA controller can be used.
The standard programmed I/O instructions are used to set up the DMA Controller
and, if so designed, I/O device controller(s) attached to the DMA Controller
with the parameters of the transfer. Program communication with these device
controllers takes place over the byte I/O bus. Once the transfer is initiated,
the DMA Controller and attached device controller supervise the transfer, and
only minimum attention from the microprogram is required. Standard Microdata
DMA Controllers can accommodate several external device controllers.

3-4

SECTION 4
BYTE I/O INTERFACE

SEC!LON 4
aYTE L/O LN!ERFACE
4.1

IN!RODUC!LON

The Byte I/O interface, to which the parallel-byte device controllers are
connected, contains input control lines, input data lines, output control
lines, output data lines and spare lines. The points of origin or destination in the CPU of the byte I/O interface lines are shown in Figure 4-1.
4.2

BYTE I/O BUS

The following paragraphs describe the I/O data and control lines of the byte
I/O bus. Unless noted, descriptions apply to both internal and external buses.
4.2.1

Input Data Lines

Input data lines
by lK pullups to
equivalent, with
switches on, the
1 on the B bus.
input data lines
in the mainframe
4.2.2

lDOO/through ID07/ are terminated on the CPU input bus
+SV. The lines are driven by 7438 TTL power gates, or
uncommitted collectors on each controller. When a gate
connected line swings to ground potential and places a logical
When the gate is switched off, the line swings to +SV. The
are handled the same whether the device controller is located
or in an external chassis.

Output Data Lines

Output data lines ODOO/through OD07/ originate at the processor Output Data
Register. Data or address information to be transferred over the output data
lines is transferred from the A Register, the B Register, or Memory, into the
Output Data Register and onto the lines. Lines ODOO/through OD07/ are present
at all CPU I/O backplane connectors.
To preserve the expansion capability 6f the byte I/O bus, each device controller on the bus is restricted to a single unit load (one TTL gate, 1.6 ma
maximum) on each of the output data lines. Two loads are allowed if one load
is a low power TTL gate such as a 74L04.
Output Data Register

4.2.3

ODOX/

Binary 1

OV

Binary 0

+4V nominal

Input Control Lines

The input control lines on the byte I/O bus are:
•

ECIO/ - Concurrent I/O request

•

IRPY/ - I/O Reply (spare)

•

EINT/ - External interrupt

4-1

r-J\~v-----~--~+5V

DEVICE CONTROLLER

~....
N__________+-+--1.0 J.lS
<20.8J.1S
CONCURRENT I/O
ACKNOWLEDGE
CACK/

I

r-

--1

---~--il

_1.6J.1S

I

--l 1-1..

400 NS MAX

2.8J.1S

DATA INPUT BUS

1000/'-1007/

ADDRESS AND STATUS
TRANSFER

I---

DATA INPUT
DIXX/

DATA OUTPUT
DOXX/

3.4 J.lS

--~.-!

' - - 800 NS

I

U

200NS~
DATA OUTPUT BUS

I

1000/-1007/

,

!--1.0J.lS

I

OUTPUT DATA
TRANSFER

Figure 4-5.

Concurrent I/O Timing

concurrent I/O request with CACK/, the controller places a byte on data input
lines IDOO/ through ID07/. This byte contains the device address times 2
(shifted left 1 bit) in the lower 6 bits with bit 7 set or reset to specify
the direction of transfer.
This byte is shown in the following diagram.

DEVICE ADORES X2
(SHIFTED
LEFT
ONE
BIT)
...._ _ _
A __
_
,
~

765432
DEVICE
ADDRESS

1/0

(ALWAYS ZERO)
DIRECTION OF TRANSFER:

o:
1

INPUT

= OUTPUT

4-15

0

When the computer receives this byte, it obtains the actual dedicated memory
address (4 X device address) by shifting the 2X address (supplied by the
controller) left 1 more bit position. The direction bit (7) is shifted out
and used by the computer to specify an input or output operation. Examples
of device addresses, addresses supplied by the controller, and dedicated
memory addresses are as follows:
Actual Device
Address (Hex)

Address Supplied
By Controller (Hex)

Dedicated Memory
Address (Hex)

00
01
02

00
02
04

00 thru 03
04 thru 07
08 thru OB

IF

3E

7C thru 7F

The firmware uses the address byte to initiate a normal input or output
operation to or from memory. If an input is specified, the firmware asserts
DIXX/ and the controller responds by placing a data byte on IDOO/ through
ID07/. The addresses of the block of memory locations to or from which the
transfer takes place is specified by software. Prior to starting the block
transfer, the program loads the 4 dedicated memory locations with a l6-bit
starting (current) address and a l6-bit ending address. After each byte is
transferred, the starting (current) address is incremented by the firmware.
Thus, each byte is transferred to or from the next sequential location. After
each transfer (but before the current address is incremented) firmware compares the current address with the final address. If the two are equal, the
firmware tells the controller that the transfer is complete by essentially
executing an output instruction with a device order of 4. Upon receipt of the
second byte of this instruction (strobed by DOXX/) , the controller issues an
external interrupt to indicate to the CPU that the operation is complete.
4.6

EXTERNAL INTERRUPT OPERATION

Interface lines PROT/, PRIN/, SELO/, SELI/, EINT/, lACK/, and IDOO/ through
ID07/ are used by device controllers or the optional Priority Interrupt board
on the byte I/O bus for external interrupt operations. Lines PROT/ and PRIN/
(paragraph 4.2.4.4) make up the hard-wired priority chain that determines the
relative priority of each controller and Priority Interrupt board on the byte
I/O bus. These lines determine priority for interrupt requests. Line EINT/
(paragraph 4.2.3) carries the interrupt request from the controller to the
processor. I/O control register state 5 is decoded in the controller as
interrupt acknowledge IACK/. Input data lines IDOO/ through ID07/ carry an
interrupt address byte from the interrupting controller to the processor in
response to the interrupt acknowledge signal on line IACK/. The interrupt
address byte is used by the processor to locate the entry address of the
interrupt servicing subroutine.

4-16

4.6.1

Priority Determination

Interface units on the byte I/O bus are assigned priority for control of
external interrupts and concurrent I/O request operations. The priority is
achieved by the manner in which lines PRIN/, PROT/, SELI/, and SELO/ are used
to link the interface units together. A typical example of priority wiring
is shown in Figures 4-6 and 4-7. In these examples, three device controllers
in the mainframe chassis are connected in the priority chain. The figures
show that the priority of an interface unit is the same as the physical location of that interface on the byte I/O bus. With special priority wiring,
however, the relative priorities can be independent of backplane positioning.
A device may make a concurrent I/O request at any time. However, to make an
external interrupt request, the device must have priority in (PRIN/). Signal
IS02 of Figure 4-6 on each interface unit inhibits propogation of PRIN/ if the
interrupt servicing routine is not complete. This establishes a true-level
priority among all interface units for generating an external interrupt. A
controller never passes a low signal on line PROT/ if it is making a request
or until the interrupt servicing routing is complete.

PRINX/

PROTX/

PRINX/

CONTROLLER
HIGHEST PRIORITY

PROTX/

CONTROLLER
SECOND HIGHEST PRIORITY

Figure 4-6.

CONTROLLER
THIRD HIGHEST PRIORITY

Typical Priority Scheme

4-17

SELOX/

SELIX/

SELOX/

SELIX/

r---------------~

HIGHEST PRIORITY

Figure 4-7.
4.6.2

SELOX/

SELIX/

~--------------~

SECOND HIGHEST PRIORITY THIRD HIGHEST PRIORITY

Typical Selection Acknowledgment Scheme

External Interrupt Requests

External interrupt requests from interface units are carried on line EINT/ to
the processor. The internal microprogram recognizes the presence of an external interrupt request and responds as dictated by interrupt handling firmware.
External interrupt line EINT/ can be used both by device controllers and by
the optional Priority Interrupt interface board. The Priority Interrupt
option provides the proper interface to the I/O bus, contains priority logic
for each interrupt level, and permits processor control over the handling of
interrupts. This standard option provides, on one circuit board, convenient
hardware for 8 levels of system interrupts. Because the basic interrupt
facility makes use of the byte I/O bus, all device controllers have access to
the interrupt request line and can react to the firmware interrupt handling
sequences in the processor (provided they operate according to the design
guidelines given in paragraph 4.6.3.
Note:

Requesting an interrupt removes priority for interrupt operations
from all controllers lower on the priority chain

4.6.3

Interrupt Sequence and Timing

Figure 4-8 shows the timing for a typical external interrupt sequence.
sequential firmware, processor and I/O device operation is:

The

a.

The I/O device controller lowers line EINT/ to signal a request
for microprogram attention. The controller must receive priority
signal PRIN/ from the higher priority controllers. The requesting controller does not pass the priority signal to lower
controllers.

b.

At the end of the macro instruction currently being executed
(if not a privileged instruction like I/O or jump), the microprogram senses the interrupt request and jumps to a firmware
subroutine to handle it.

4-18

r----------------------------1

EXTERNAL INTERRUPT ------~
REQUEST EINT/
~----(SS

TIME DEPENDENT ON
-.j
CURRENT INSTRUCTION

I

~1.6I1S~

{f-;

INTERRUPT
ACKNOWLEDGE
lACK/

I

300 NS MAX
INPUT DATA LINES
IDOO/-ID07/

~
IS

INTERRUPT ADDRESS
PLACED ON INPUT
DATA LINES

Figure 4-8.

I

~

I

;.1-------------j.- -...j
j.- 400 NS MAX

I

1].-------------,

INTERRUPT ADDRESS
REMOVED FROM LINES

External Interrupt Timing

c.

The microprogram causes line LACK/ to go true to acknowledge
the request. All controllers in the priority chain decode LACK/
and each requesting controller passes SELO/ down the chain to
the lower priority controllers (SELO/ becomes SELI/ at the input
to each controller).

d.

The controller that issued the interrupt request does not pass
SELO/ to the next controller. This prevents any lower priority
controller that may have simultaneously requested an interrupt
from responding to signal LACK/.

e.

In response to the acknowledgement and receipt of SELI/, the
requesting controller places a 6-bit interrupt address on input
data lines (IDOl/ through ID06/. The interrupt address specifies the location (in core memory page 1) of the 2-byte entry
address for the interrupt servicing subroutine.

f.

The processor accepts the 6-bit interrupt address and causes
line IACK/ to go high.

g.

The processor fetches the 2-byte interrupt subroutine entry
address from the first 256-word page of memory using the interrupt address supplied by the controller as the lower 6-bits,
and 01 as the upper two bits.

h.

Using the 2-byte entry address, the microprogram executes a
pseudo return jump or call instruction to the interrupt
servicing subroutine at that address.

i.

The interrupt servicing subroutine then proceeds to service
the interrupt according to the macroprogram.

j.

At the end of the servicing routine, priority is released by
any of the 3 actions listed oelow. Any of these will cause

4-19

the requesting controller to pass signal PROT/ to the lower
priority controllers.
1.
2.

3.

Rearmi~g (if another request is expected)
A concurrent I/O request
Disarming (if no further requests are desired)

The interrupt sequencer in the controller contains two J-K flip-flops (and
associated circuits) which generate the interrupt request (EINT/) and control
the priority line PROT/ to the next controller. The 4 states of the flip-flops
determine the priority interrupt status of the controller. These 4 states are
illustrated in Figure 4-9 and described in Table 4-5.

DISARMED

ARM+
CCIX+
CCOX ..

0

ARMED

~

DEVICE
ACTION

WAIT

lACK

I~

ARM + CCIX + CCOX

DSM

State

ACTIVE

3

2

1

yigure 4-9.

Interrupt Sequencer States

Table 4-5.

Interrupt Sequencer States

Flip-Flop
States
IS02
ISOl

I

Function

o

o

o

Disarmed state. Disregards any received
interrupt and does not move to requesting
state.

1

0

1

Armed state. Allows system to move to
requesting state when peripheral conditions
are met.

2

1

1

Wait state. Generates an external interrupt
to the processor when priority in is received.

3

1

0

Active state. Inhibits propagation of
priority to lower level priority controllers.

4-20

When the controller is initialized, the sequencer is set to state zero
(disarmed). When disarmed, the controller cannot generate an interrupt
request and always passes PROTI to the next controller.
In order to allow an interrupt, the program must execute an instruction to
arm the controller interrupt, setting the sequencer to state one (armed).
In this state, the controller can generate EINTI providing it has priority
from the preceding controller on the priority chain.
When the controller is ready to interrupt the CPU, the sequencer advances to
state two (wait), the priority line (PROT/) is removed from the next controller, and interrupt request EINT/ is generated. The firmware responds to the
interrupt with the acknowledgment (LACK/). The first interrupting controller
in the string that has SELl places its address on the input data lines. Its
sequencer then advances to state three (active) and removes EINT/.
While the sequencer is in the active state, PROTI is not passed to the next
controller. This prevents a lower priority controller from generating an
interrupt while the interrupt handling subroutine is in process. One of the
functions of the interrupt subroutine is to execute an instruction to rearm
the controller if another interrupt is expected, or to disarm the controller
if no further interrupts are desired. The rearming or disarming normally
takes place near the end of the subroutine and restores priority (PROT/) to
the lower priority controllers.
Concurrent 1/0 operations are normally terminated with an end-of-operating
interrupt to inform the CPU that the block of data has been transferred. The
concurrent I/O request automatically arms the controller interrupt.

4-21

SECTION 5
MICRO-ONE CPU READ/WRITE MEMORY INTERFACE

SECTION 5
MICRO-ONE CPU
READ/WRITE MEMORY INTERFACE
5.1

PROCESSOR AND MEMORY INTERFACE

Figure 5-1 illustrates a portion of the processor and memory interface
consisting of the following elements:
•

Control Section

•

Memory Read Data Selection Logic

•

Memory Write Data Gating Logic

•

M and N Register Address Gating Logic

The remainder of this section discusses each element in turn.
5.1.1

Control Section

The Control Section is the main control element of the Micro-One CPU. However,
only that part of the Control Section pertaining to memory is discussed.
One function of the Control Section is to decode the CPU memory micro command
OPAl. OPAl requests memory service for the CPU, and eventually results in a
Memory Busy (MBSY) condition while the memory services the CPU. While
MBSY is high, due to memory use by the CPU, the DMA is prevented from
issuing a request for memory service. While memory is being used by the
DMA channel, the Control Section is inhibited from executing OPAl.
The Control Section also generates Timing Hold signal THLD/. In a DMA
operation, THLD/ is used to stop the main CPU clocks while a DMA memory
cycle is occurring. This essentially freezes execution of microcommands
and prevents CPU me1llory_request while meIl1o~y:i.s servicing the DMA channel.
Signal THLD/ is generated by either of two sets aT-conditions relative to
DMA operations:
1.

Simultaneous OPAl and DMAR/

2.

OPAl while MBSY/ is active

The third function of the Control Section which relates to memory operations
is generation of Transfer Memory Clock signal LT2/. LT2/ clocks the memory
read data through the Memory Read Data Selection Logic to the CPU T Register.
When the DMA interface is using memory, LT2/ is inhibited. Inhibiting LT2/
prevents the data being transferred from memory to the. controller from
entering the CPU T Register.

5-1

.

I

FROM M&N

FROM MD

REG~STERS

REG~STER

I
~

1-"
IN
~

I'i
(t)

V1

I
t:11-'

r-(t)

•

rt

III

1-"

n

(t)

c:::

TOT
REtSTER

LOAD T

I
I
L .- - -

MEMORY
READ DATA
SELECTION

MEMORY
WRITE DATA
GATING

M&N ADDRESS
GATING

...>

r-- - - -

I

N

..

:>;"'~

t:1
1-"

:s:

III (t)
IN S
I'i 0
III I'i

~

'-"

I
I
I

S'<:
H
::;I

rt

(t)

I'i

"'"

III

n

(t)

-

-

III

1-'0..
0
n t:1

-

MA
NTERFACE

- - - .- - -

•

DMA MEMORY
ADDRESS
GATING

LFROM
CURRENT
ADDRESS
COUNTER

- -

DMA MEMORY
WRITE DATA
GATING

BIDIRECTIONAL
MEMORY DATA
BUS (8·BIT)

----

DMA MEMORY
CONTROL

j

FROM
CONTROLLER
WRITE DATA
BUFFER

-

-

TO
CONTROLLER
READ'OATA
BUFFER

-

- - r-

DMA
REQUESTS
FROM
CONTROLLER

MEMORY
CONTROL
INTERFACE
ON MICRO
ONE
PROCESSOR

I
WTXX/
I

..
r

MRST/
I
READ

____ J

r

READ/
WRITE
FROM
MEMORY

-

MEMORY ADDRESS
BUS (16·BIT)

DMA MEMORY
READ DATA
RECEIVERS

--

MBSY

- - - ----

I

~--

MRST/THOUl.

CONTROL
SECTION

I

RTXX/
r

0:;::;1
V1

1~

CPU MEM
REQUEST
CLOCK

1-'l-tI
0..

----,

I

+

~

DMAS/

--""

I

I
I
... I
I
J

CONTROL
SIGNALS
TO
CONTROLLER

DMAR/
DMAW/

MBSY
DMAS/

5.1.2

Memory Read Data Selection Logic

During CPU memory accesses (read mode), this element gates data read from
memory into the CPU T Register. As explained in the preceding paragraph
the Transfer Memory Clock LT2/ signal from the Control Section intiates
the gating operation. To prevent read data gating to the CPU during DMA
operations, DMAS/ inhibits generation of LT2/.
5.1.3

Memory Write Data Gating Logic

During C?U memory write operations this element gates the write data from
the MD Register onto the Memory Data bus. Gating signal WRIT, originating
in the Memory Control Interface, is inhibited during DMA operations.
5.1.4

M and

_~

Register Address Gating Logic

During CPU memory accesses (read~Qr write), this element gates the l6-bit
memory address onto the Memory Address bus from the M and N Registers.
During DMA operations, when the memory address is applied by the DMA
interface, this function is inhibited.
5.2

MEMORY CONTROL INTERFACE

The Memory Control Interface is the principal memory controlling element
of the system. Its primary functions are:
•

Generating memory status and control signals,

•

Monitoring requests ,for memory service from the DMA and CPU,

•

When memory is not busy, determining which requesting device
(CPU or DMA) is to receive access. Determination is based on
DMA having highest priority and the CPU having second priority,

•

Initiating memory read or write operations and timing out the
memory cycles.

The Memory Control Interface generates the Memory Busy (MBSY) signal to
the CPU and to the DMA interface. When memory is available, this signal
goes low and either or both DMA and CPU can request service. If both
elements request simultaneously, the DMA has priority and will receive
memory service. The DMA memory request signal is DMAR/; CPU memory request
signal is OPAl.

5-3

When the DMA or CPU request sequence occurs~ the Memory Control Inter~ace
generates the appropriate memory control signals (listed below) and times
out the memory cycles, as ShOWll inF1gure 5-2.
•

RTXX/ - Start read portion of cycle,

•

WTXX/ - Start write portion of cycle,

•

READ

•

MBSY/ - Active low during all memory sequences. Used internally
by the CPU and externally to control DMA interface devices.

- Low level = clear/write or half-cycle write;
High level = read/restore or half-cycle read.

5-4

I

I

1'-200 NSEC-l

I
I

I
I

wtfJ

UI

TT4/

u

u

u

u

RTXXy/

~~70o-~}••-------400NSEC~~

r

NSEC

WTxx7/-r----------------------~I~·::=___4_0_0_N_SE_C________.J~
READ

L_____ ____

READ

W..B ILE _ _ _ _ _ _ _ _ _

J' .....

r

MBSY/

FULL CYCLE READ/WRITE

TT~
RTXX/

2 CON
SEC

lfJ

u

u

u

r-

__-+ __________

WTXX/

READ

MBSY/

f

__--+-_________

HALF CYCLE READ

Figure 5-2.

Half Cycle Read (Sheet 1 of 2)
5-5

u

TT4/

f"lj

RTXX/

~

~

U

U

U

U

F~ONSEC1

1-"

CJQ

C
~

CD
\J1
N

WTXX/

~

\J1
I
~

I

I

~

0

r

~

'

MICRO ONE
PROCESSOR AN D
CONTROL SECTION
(8-BIT) ~

(16-BITl

,......
CI.l

I
f-'

.

f-'. t:I

.§ ~

f-'
f-'. -1-0

I

PROCESSOR
CONTROL SIGNALS
DMA
CONTROL SIGNALS

f-'·O
ct> n
o..ct>
I

N

06-BIT)

(fJ
t;;d(fJ

f-'O
0 Ii

(8-BIT)

DMA PORT

n

:>;"'(')

0

t:l1i
f-'. ct>

III

OQ

Ii

~

~

BIDIRECTIONAL MEMORY DATA BUS (8-BIT)
BYTE
I/O
BUS

I-hli

0\

..

MEMORY ADDRESS BUS (16-BIT)

0\

16-BIT ADDRESS

~

DATA

ct>

+

MEMORY
CONTROL
INTERFACE

MEMORY
CONTROL

..

CORE
MEMORY
8K TO 64K
BYTES

I

DMA
CONTROL

S

0
'-'Ii

'-<

r----'

H
:;l
rt

~

ct>
Ii

I-h
III

n

ct>

DMA
INTERFACE

1
~-.

r

DEVICE
CONTROLLER(S)

TO PERIPHERAL
DEVICE(S)

An end-of-b1ock interrupt should be generated in the DMA inter~ace or device
controller. This may be either an external "interrupt via the I/O bus or
an internal DMA interrupt which sets bit 1 of the CPU's internal status
register.
The following paragraphs describe the various elements in the DMA system
and their functions in DMA operations. (See Figure 5-1.)
6.2.1

DMA Interface

The DMA interface provides interface and controls required for use of the
Micro-One DMA capability. A standard Microdata DMA interface or an individually
designed interface may be used.
The elements of the DMA interface are:

•
•

DMA Memory Control Logic

•
•

DMA Memory Write Gating Logic

6.2.2

DMA Memory Read Data Receivers

DMA Memory Address Gating Logic
DMA Memory Control Logic

When the DMA interface has been readied for DMA operation this element
monitors contoller requests for DMA transfers. After receiving a controller
request, the DMA Memory Control Logic intitiates a DMA memory cycle
sequence as soon as the CPU memory cycle is completed (MBSY = low level).
The DMA memory cycle sequence consists of a DMA request (DMAR/) , DMA selection
(DMAS/), and read or write mode selection (DMAW or DMAW/, respectively).
These signals originate in the DMA Memory Control section and are sent to the
Memory Control Interface in the Micro-One.
Signal DMAS/ performs the following functions in both the DMA interface and
the Memory Control Interface:
•

Gates memory address from current address counter of DMA controller
onto memory address bus.

•

For memory write operations, gates write data from
onto bidirectional memory data bus.

DMA controller

Signal DMAW is set low (DMAW/) by the DMA Memory Control if a clear/write
cycle is being requested. It is set high (DMAW) if a read cycle is requested.

6-3

6.2.3

DMA Memory Read Data Receivers

Data read from memory during a DMA transfer is buffered from the bidirectional
data bus by eight receivers in the DMA interface. The outputs of the
receivers are applied to the controller.
6.2.4.

DMA Memory Write Gating Logic

This element gates the 8-bit data byte from the controller onto the
bidirectional· data bus and is written into memory during memory write
operations. The data byte is gated onto the bus by DMA Selection signal
DMAS/.
6.2.5

DMA Memory Address Gating Logic

This element gates the l6-bit address stored in the current address register
(contained in either the DMA interface or the controller) onto the memory
address bus. Address gating occurs at DMASI time.
6.3

DMA PORT/MEMORY CONTROL INTERFACE TIMING

To simplify the timing of essential DMA Port/Memory Control Interface
signals, Figure 6-2 illustrates a DMA clear/write memory cycle, followed
immediately by a DMA read/restore cycle, followed by a Micro-One
processor read/restore memory cycle. The sequences shown are not necessarily
typical, but serve to define all DMA signal and timing requirements.
At the start of the timing sequence, the memory is not busy and theDMA
request (DMAR/) and CPU request for memory service OPA occur during the same
clock period (to to ti). Since the DMA channel has priority over the CPU
for memory service, the DMA is granted service before the CPU in cases of
simultaneous requests. The DMA receives memory service on the TT4/ computer
clock pulse tl, provided the timing requirements of paragraphs 6.3.1 and
6.3.2 are met.
.
TT4/ clock pulses occur every 200 nsecs, and 5 pulses (1 microsecond total)
occur during each complete read/restore or clear/write memory cycle. Therefore, the DMA is granted service for the second memory cycle (read/restore) on
clock pulse t6, which occurs 1 microsecond after tl (start of the first memory
cycle). The processor memory service request is not answered until the e~d
of the second DMA cycle (tll). The CPU has been locked out of memory service
for 2 consecutive memory cycles by the DMA. Since the DMA is not requesting
memory service for the third memory cycle starting at time t11' the
processor is allowed to perform its read/restore operation at this time.
During the two DMA cycles, the processor operation freezes. Clock Stop
signal THLD/ stops or inhibits certain computer clocks so that the memory
type microcommand OPA is not executed. OPA remains true until THLD/ is
removed at time tlO to t11' allowing DMA use of memory during THLD/. It is
assumed that. a non-memory type microcommand will be decoded and executed
during clock period tl1 to t 12 •

6-4

6.3.1

Clock Signals

The clock signals TT4/, CPH1, and CPH2/ are used by the Micro-One processor,
Memory Control interface, and the DMA interface to time and synchronize all
memory operations. These clocks are generated by a single crystal oscillator
clock generator located on the CPU control board. TT4/ is the main reference
clock signal for all ciming requirements and is used to generate CPH1 and
CHP2/. CPH1 and CPH2/ are phased clock signals, available to the DMA
interface at any backplane connector at which the DMA interface board is
installed. Combining CPH1 and CPH2/ produces a clock pulse similar to, and
almost in phase with, TT4/. The clock developed from CPH1 and CPH2/ is used
in the DMA interface to time the channel's control functions in synchronism
with the processor and Memory Control interface.
6.3.2.

DMA Port Signals

The following paragraphs describe the DMA Port signals generated in the DMA
interface, along with their timing requirements. Figure 6-2 is referenced
as an aid in conveying the timing relationships.
6.3.2.1

DMA Request (DMAR/).

DMAR/ directly generates THLD/ during clock pulse t1 if OPA is present.
CSTP/ in turn, inhibits processor execution of OPA and fetching of another
microcommand. DMAR/ also enables setting of the Memory Sequencer on clock
periods t1 and t6 to begin each DMA memory cycle. The MBSY and THLD/
signals are held true during the DMA cycles by the Memory Sequencer.
DMAR/ must go low not later than 60 nsec before the leading edge (low-tohigh) of TT4/ pulse tl, and remain true until 20 nsecs after the trailing
edge of t6 in order to initiate a DMA cycle of time tl' It must return
to the false (high) state before the leading edge of time t2' Once DMAR/
goes high after initiating a DMA memory cycle, it must remain high until
after memory becomes not busy (MBSY = low level) at the end of the current
DMA cycle.
The DMAR/ line must be driven by a power gate (SN7438 or equivalent) with
an uncommitted collector. The terminating resistor is located in the
processor, allowing the line to swing between +5V and virtually OV.
6.3.2.2

DMA Write (DMAW/)

When DMAW/ is true (low level), it is applied to the Memory Control
sequencer to enable a clear/write memory cycle. (See Figure 6-2, time to')
A false (high level) state of DMAW/ enables a read /restore DMA memory
cycle as shown at time t6'
DMAW/ must be stable in the desired state no later than 55 nsecs before the
trailing edge of TTY/ clock pulse t1' It must remain true until the memory
goes not busy (MBSY = low level) after the trailing edge of clock pulse t5'

6-5

The DMAW/ line must be driven by a power gate (SN7438 or equivalent) with an
uncommitted collector. The terminating resistor is located in the processor
which allows the line to swing between +5V and virtually OV.
6.3.2.3

Memory Busy (MBSY)

MBSY is generated by the Memory Control interface to inform the DMA interface
when memory is not busy so a DMA request can be issued. MBSY is used in
the DMA interface to inhibit DMAR/ and DMAS/ until MBSY goes false (low level).
MBSY will go true (high) at the DMA interface about 40 nsecs after the
trailing edge of the TT4/ clock pulse on which the memory cycle begins
(tl, t6, and tIl of Figure 6-2) for A CPU memory cycle, and is 80 nanoseconds
for DMA cycles. It remains true for four clock periods during a full memory cycle and goes false no later than 80 nsec after the trailing edge of the
fifth clock pulse. During half memory cycles (initiated and controlled by the
processor only), MBSY remains true for two elock periods, going false not
more than 70 nsecs after the third clock pulse.
MBSY line must be terminated in a single unit lo~d (one TTL gate input)
which is equivalent to a maximum load of 2 mao
6.3.2.4

Memory Addresses

The DMA interface must have the current address on the Memory Address bus
at least 15 nsecs before the leading edge of TT4/ pulse on which the DMA
memory cycle begins (tl and t6). The address must remain stable on the bus
until MBSY goes false (low)
Memory address lines M07A/ through MOOA/ and N07A/ through NOOA/ are
terminated on the computer backplane. The lines must be driven by power gates
(type SN7438 or equivalent) with uncommitted collectors. B~cause of the
termination network, the lines are allowed to swing between virtually OV
and +3.6V.
6.3.2.5

Write Data

During clear/write operations the DMA interface must place the desired
write data on the bidirectional memory data bus no later than the leading
edge of the t3 clock pulse (Figure 6-2). The data must remain stable
until MBSY goes false (low).
Bidirectional memory data lines MD07 through MDOO are terminated on the
computer backplane. The memory write data must be driven to the memory
data bus by power gates (type SN7438 or equivalent) ·with uncommitted
collectors. Because of the termination network the lines are allowed to
swing between virtually OV and +3.6V.

6-6

I--- 200 NS ----1

~

TT4/

tjr------~~r------~~

12:l---

£1

OPA
MBSY

DMAR/

W/I

DMAS/

DMAW/

THLD/

0'>

I.

I

RTXX/

I

--.J
~~~ORY ADDRESS

---..j I-- 15 NS MIN

2Z/@a;/Mr-----------------------------------------.:t(;,..,/,'7~"77"">2X
_ u

WTXX/

400NS----·~1

400NS:------·~1

r--

14

rl---------------------1
--11--15

NS MIN

X'-______________________

_U

,
/ ' WRITE DATA MUST BE TRUE

MEMORY DATA

~~~----------~----

BUS

READ

i-----------------------------~

~A

1---------------- V///////A
I _________________________________ U

CPH1

CHP2/

U

DMACLOCK

1---------

DMA CLEAR/WRITE MEMORY CYCLE --~-------+l-------- DMA READ/RESTORE MEMORY CYCLE - - - - - -.....+-/
..

PROCESSOR READ/
RESTORE MEMORY CYCLE

NOTE'
THE SHADED AREAS SHOW
WHERE THE SIGNALS ARE
NOT REQUIRED TO BE

""CPU MEMORY REQUEST NOT ACTED ON UNTI L THE
TWO BACK TO BACK OMA REQUESTS HAVE BEEN
SERVICED.

DEFINED.

Figure 6-2.

DMA Port/Memory Control Timing

6.3.2.6

Read Data

The data read from memory during a read/restore cycle will be available
on the bidirectional memory data bus 445 osee after the trailing edge of the
TT4/ clock pulse on which the cycle started (t6 of Figure 6-2). The data
will remain stable for gating into the DMA interface until the trailing edge
of the DMA clock pulse corresponding to TT41 clock pulse t lO '
Read data, received from the bidirectional memory data bus, must be buffered
by gates whose inputs load each line with only one unit load (one TTL gate
input) that is equivalent to a maximum load of 2 mao

6-8

SECTION 7
SERIAL I/O INTERFACE

SECTION 7
SERIAL I/O INTERFACE
7.1

INTRODUCTION

The Serial I/O interface is an optional feature of M-l series computers.
It is a hardware/firmware option using microprogramming to control a serial
device such as a teletype or modem.
7.2

USE AS TELETYPE CONTROLLER

The following paragraphs describe operation of the serial I/O channel with
a 4-wire, full-duplex, 20 ma teletype. A cable is provided with the serial
channel to connect directly to the teletype.
7.2.1

General Operation

The 4-wire I/O interface circuit is shown in Figure 7-1. The transmit
portion of the circuit contains a 20-ma current source that can be turned on
or off depending on the state of the I/O control register. When the I/O
control register is in any state other than state 3, output of gate 9E is
high, emitter follower Q3 conducts, and approximately 20 rna of current flows
through resistor R24. This current holds the teletype iIi the mark condition.
When the I/O control register is set to state 3 by a microcommand, the output of gate 9E is low, emitter follower Q3 cuts off, and no current flows to
the teletype.
The receive portion of the interface circuit contains a low-pass filter
network connecting the teletype distributor to bit 6 of File Register 0
where it may be sensed by microcommands. One side of the teletype distributor
is connected to -16.75 volts through resistor R23. The other side of the distributor is connected to 3M, which forms bit 6 of File Register O. When the
teletype sends a mark signal, the output of 3M is held low and a 0 bit appears
in bit 6 of File Register O. When the teletype sends a space signal a 1 bit
appears in bit 6 of File Register O.
7.2.2

Character Assembly and .Disassembly

Teletype character assembly, disassembly, synchronization, and timing is
accomplished by a firmware routine initiated by the macro instructions for
the serial I/O interface. Figure 7-2 illustrates the timiIig for transmission or reception of IIO-band teletype characters.
Note:

The Micro One/13 is the only standard firmware set which has
these serial I/O macro instructions.

During an input operation the firmware program searches for the leading
edge of the start bit by continuously testing bit 6 of File Register O.

7-1

,-----SERIAL INTERFACE CIRCUIT

~
+5V

I
I

I
I

I

I
101X/

101X
102X
103X/

I
I

9E
7410

I
I/O CONTROL
REGISTER
STATES
FROM 7475
LATCH 90

I

102X/
----------------------~

:~-+--I

TTY 0

TO
TELETYPE
103X/

TTY G

+5V

+12
R38
1.3K

P11J2

R37
5.6K

1 1

TTY X1

C25
0.1,uF

CR11
FOH600
TTYI

7403
3M

CR10
FOH600

FILE 0
ENABLE

2

I
I

R23
150

I
I

I
-16.75V

_____ J

L

Figure 7-1.

I

I

2

I

I
I

FROM
TELETYPE

TTY B Hrl--I

TO FILE
U - -.....;...;.;...:.:;..-REGISTER 0
BIT6

Serial I/O Interface Circuit (For ASR 33 TTY)

7-2

START BIT

MARK
SPACE

STOP BITS

2

\1

~

4

3

5

U

7

6

~

8

EIGHT DATA BITS
TEST FOR SPACE
-

14.51
MS

9.09
MS

1 9MS.09

I

9.09

9.09

MS

MS

I

9. 09 1 9.09

9.09 19.09
MS

MS

MS

9.09

MS

MS

SAMPLE POINTS
(A) INPUT TIMING

START

STOP

2

MARK

4

3

5

7

6

8

U

SPACE

9.09

1 MS

SETI/OCONTRO~L~~
REGISTER

-

____

~ ~
__

____

~ ~
__

____

~ ~
__

____

~ ~

(B) OUTPUT TIMING

Figure 7-2.

Serial I/O Timing
]-3

__

____

~ ~'I____~
__

Once a s~ace level is detected the firmware ~rogram delays 4.5 milliseconds
and samples the input every 9.09 milliseconds, shifting each bit into the
least significant byte of the A Register (File Register 4). The initial delay
of 4.5 milliseconds, after detecting the leading edge of the start bit,
causes sampling to occur in the middle of each bit. The firmware routine
exists after eight bits have been assembled.
During a~ output operation the firmware program sets the I/O control
register to the appropriate mark or space condition every 9.09 milliseconds
according to the start and stop bits and the data to be serially transmitted.
Before the first information bit is transferred, the I/O control register is
set to mode 3 to ~ransmit the start bit. The firmware program for transmitting
a teletype character remains active for 11 intervals (100 milliseconds) to
assure the proper stop interval before the next character is transmitted.
7.2.3

Serial I/O Instructions

Two macro instructions affect the operation of the serial I/O interface:
In~ut

Byte Serially (IBS). and Output Byte Serially (OBS).

The Input Byte Serially instruction transfers an 8-bit character from
the teletype into the eight low-order bits of the A Register. The execution of this instruction terminates when a complete teletype character
has been received for proper operation, execution of the instruction must
be started before the start of the teletype character. Once the
instruction is started, the computer becomes tied up until a teletype
character is received. The execution time of the instruction extends
approximately 84 milliseconds after the leading edge of the teletype
character start bit. When the program echoes input characters back to
the teletype the effective input rate cannot exceed five characters per
second (no input can be handled during the 100 milliseconds required fGr
output).
The Output Byte Serially macro instruction disassembles the eight low-order
bits of the A Register and transfers them serially, as a teletype character,
through the serial I/O interface. During the execution of this instruction
the eight low-order bits of the A Register are set to l's, the eight highorder bits remain unchanged.
7.2.4

Teletype Interface Connection

The standard Teletype Model ASR-33TY with 20 rna loop interface is directly
compatible with all Microdata TTY controllers.

7-4

SECTION 8
MICRO-ONE BACKPLANE CONNECTOR SIGNAL LIST

SECTION 8
MICRO-ONE BACKPLANE CONNECTOR SIGNAL LIST
8.1

I/O CONTROLLERS AND DMA INTERFACE SIGNAL LIST

This section contains a signal list of the Micro-One backplane connectors
which can be used for I/O controllers and the DMA interface. (See Table 8.1.)
8.2

SERIAL TTY (J2)
1.

TTYXI

2.

TTY B

3.

TTY 0

4.

8.3

5.

TTY G

6

TTY G

FRONT PANEL (CABLE) CONNECTOR (J3)
1.

2.

ES07/

3.

ES04/

4.

ES05/

5.

HLTL/

6.

INTF/

7.

ES06/

8.

RUNF/

9.

STPF/

10.

CLKF/

8-1

Table 8-1.
PIN
Al
A2
A3
A4
AS
A6
A7
A8
A9
AIO
All
Al2
Al3
Al4
Al5
Al6
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A3l
A32
A33
A34
A3S
A36
A37
A38
A39
A40
A4I
A42
A43
A44
A45
A46
A47
A48
A49
ASO

SIGNAL
NAME
GND
GND
SPARE
-16.7SVDC
+1 2VDC
I CHPI
SPARE
-16.7SVDC
N07A/
ODOS/
MOIA
M02A/
AOOL/
AOIL/
N06A/
LOOX
LllX (GND)
L04X
RSOI
LOIX
WTXX/
L05X
RS02
L02X
L06X
OD02/
RS03
L03X
A02L/
L07X
I02X/
ID04/
I CPEN/
!
A03L/
MDOI
MD04
RS09
EINT/
SPARE
AENP
RUNX
RSIO
RSll
DMAR/
DMAS/
SP2
RS13
RSl4
CONT (GND)
N03A!

Micro-One Backplane Connector Signal List
SIGNAL
SIGNAL
SIGNAL
TYPE
NAME
TYPE
PIN

--

Bl
B2
B3
B4
BS
B6
B7
B8
B9
BIO
Bll
B12
B13
B14
Bl5
B16
Bl7
Bl8
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B3l
B32
B33
B34
B35
B36
B37
B38
B39
B40
B4I
B42
B43
B44
B45
B46
B47
B48
B49
BSO

---

l.
l.

2.

-1.

5.
4.-4700
5.
5.
2.
2.
5-.
2.
2.
2.
3.-4700
2.
4.-4700
2
3.-4700

I

2.
2.
4.-470n
3.-470n
2.
2.

2.
4.-470n
3.-lKO
3.-lKO
2.
6.-4700
6.-470n
3.-4700
3.-470n
2.
3.-4700
3.-4700
3.-lKn
3.-lKO
SPARE
3.-470n
3.-470n
GND
5.
-

8-2

i

I
I

+SVDC
+SVDC
-16.7SVDC
SPARE
SPARE
SPARE
M04A/
SPIll
M06A/
ODOlf
A04L/
MSI
M03A/
MOOA/
RSOO
MS2
RS04
M05A/
LIOX
RTXX/
RS05
CPH2/
READ
CGLO/
RS06
OD06/
MD07
MD03
RS07
MD05
IOlX/
IDOO/
L08X
MDOO
L09X
RS08
OD04
AOSL/
ODOO/
MD06
A06L/
ECIO/
MD02
MRST/
MS3
RTCI
M07A/
A07L/
DMAT/
IRPY/

1.

1.
l.

--

----

5.
3.lKO
5.
4.-4700
2.
7.
5.
5.
3.-4700
7.
3.-4700
5.

4.-470n
3.-4700
4.-4700
4.-4700
2
3.-4700
4.-4700
6.-4700
6.-4700
3.-4700
6.-470n
4.-4700
3.-lKO
2.
60-470n
2.
3.-4700
4.-470n
2.
4.-4700
6 .... 4700
2.
3.-IKO
6.-4700
6.-lKO
7.
5.
2.
SPARE
3.-lKO

Table 8-1.

Micro-One Backplane Connector Signal List (continued)

PIN

SIGNAL
NAME

A5l
A52
A53
A54
ASS
A56
A57
A58
A59
A60
A6l
A62
A63
A64
A65

RS12
SELO/
N04A/
N05A/
PROT/
DMAW/
MBSY
OD07/
RS15
IDOI/
ID06/
ID03/
-16.75 VDC
GND
GND

I
I
I
I

i
I

I

i
I
I
i

I
I

I

I

SIGNAL
TYPE

I

3.-470n
8.
5.
5.
8.
3. -lKn
2.
4.-470n
3.-470n
3.-lKn
3.-lKn
i.-lKn
1.

L

--

I

I

-----

-

PIN

SIGNAL
NAME

B5l
B52
B53
B54
B55
B56
B57
B58
B59
B60
B6l
B62
B63
B64
B65

NOOA/
SELI/
NOIA/
PRIN/
N02A/
SPI2/
SPIO/
OD03/
ID05/
ID07/
I03X/
ID02/
-16.75 VDC
+5 VDC
+5 VDC

SIGNAL
NAME
5.
8.
5.
8.
5.
3.- NO PLP.
3.- NO PLP.
4.-470n
3.-lKn
3.-1Kn
4.-470n
3.-lKn
1.
1.
1.

------------------'-------------------'-

Signal Types:
1.

POWER

2.

TTL OUT

3.

OPEN COLLECTOR INTO TTL (Pull Up)

4.

TTL OPEN COLLECTOR OUT (Pull Up)

5.

TRI STATE OUT

6.

BIDIRECTIONAL TTL OPEN COLLECTOR

7.

JUMPER

8.

THROUGHPUT

8-3

Table 8-2.

MOS Memory Interface Connector List

J3
1
2
3
4
S
6
7
8
9
10
11
12
13
14
IS
16
17
18
19
20
21
22
23
24
2S
26
27
28
29
30
31
32
33
34

J4
M06A/
MDOO
RTXI/
M03A/
M04A/
RFSH
READ/
MBSY/
WTXI/
GND
GND

1
2
3
4
S
6
7
8
9
10
11
12
13
14
IS
16
17
18
19
20

CPH2/
-16.7SV
MDOS
MD03
N07A/
M01A/
M02A/
MSEX/
MOOA/
N06A/
GND
MOSAI

GND
RTXX/
WTXX/
-16.7SV
-16.7SV
READ
+5V
+SV
MD07

8-4

MD04
MD02
MD01
MD06
GND
GND
GND
GND
GND
N03A/

NOOA/
N01A/
N04A/
N02A/
NOSA/
+SV
+SV

SECTION 9
I/O INTERFACE SIGNAL GLOSSARY

SECTION 9
I/O INTERFACE SIGNAL GLOSSARY
This section contains a glossary of the signals used to interface byte I/O
controllers and DMA Port interfaces to the Micro-One computer. The list is
arranged alphabetically by signal mnemonic. The origin for each signal
(computer or controller), the connector pin number, and its f~nction, are
provided in Table 9-1.
NOTE: A slash (/) at the end of a signal or line mnemonic denotes that the
line is low when the function specified by the mnemonic is occurring.
Table 9-1.

I/O Interface Signal Glossary

SIGNAL
MNEMONIC

PIN
NO.

CPRl

A6

Processor Clock.
wave.

CPR2/

B22

Processor Clock. Inverted version
of CPR1, delayed 33 nsec.

DMAR/

A44

DMA Request. DMAR/initiates a
memory cycle for DMA.

DMAS/

A45

DMA Select. DMAS/ selects memory
for a DMA operation by enabling
DMA controller access to memory.

DMAW/

A56

DMA Write. Causes the data byte
on memory data lines MDOO through
MD07 to be written into memory.

ECIO/

B42

Concurrent I/O Request. Low
signal from I/O device request~ng
a concurrent I/O transfer. ECIO/
appears in CPU as bit 3 of File
Register 0 where it acts as an
interrupt to the macroprogram and
initiates a firmware routine for
handling a concurrent transfer.

x

EINT/

A38

External interrupt. Low Signal
from I/O device requesting interruption of the macroprogram.
EINT/ appears in CPU as bit 7 of
File Register 0 where it initiates
a firmware routine for transferring
control to a macroprogram interrupt
handling routine.

x

FUNCTION
--------------------

9-1

5.0 MHz square

Table 9-1.

ORIGIN
CONT
CPU

PIN
NO.

FUNCTION

IDOO/

B32

Data Input Bit O. Connects to
CPU via B Bus gating.

X

IDOI/

A60

Data Input Bit 1. Connects to
CPU via B Bus gating.

X

ID02/

B62

Data Input Bit 2. Connects to
CPU via B Bus gating.

X

ID03/

A62

Data Input Bit 3. Connects to
CPU via B Bus gating.

X

A32

Data Input Bit 4. Connects to
CPU via B Bus gating.

X

BS9

Data Input Bit 5. Connects to
CPU via B Bus gating.

X

Data Input Bit 6. Connects to
CPU via B Bus gating.

X

B60

Data Input Bit 7. Connects to
CPU via B Bus gating.

X

B31

Bit 1 of I/O Control Register

X

A31

Bit 2 of I/O Control Register

X

I03X/

B6l

Bit 3 of I/O Control Register

X

MBSY

AS7

Memory Busy. MBSY is a status
signal from memory indicating that
memory is busy.

X

MDOO

B34

Bidirectional data line (bit 0) to
memory for DMA operation.

MDOI

A3S

Bidirectional data line (bit 1) to
memory for DMA operation.

MD02

B43

MD03
MD04

I

!
IDOS/

I
r

A6l

ID06/
I

I

I

Interface Signal Glossary (continued)

SIGNAL
MNEMONIC

ID04/

I
I
II

tlo

I

I
ID07/
IOIX/

i

I02X/

I
I
I
I

I

X

X

X

X

Bidirectional data line (bit 2) to
memory for DMA operation.

X

X

B28

Bidirectional data line (bit 3) to
memory for DMA operation.

X

X

A36

Bidirectional data line (bit 4) to
memory for DMA operation.

X

X

9-2

I
I

Table 9-1.

~I~~~~

-~

I

-

PIN
NO.

MNEMONIC
--

-

~-------

---

--

- -

I/O Interface Signal Glossary (continued)

------------.--~--

ORIGIN
CONT
CPU

FUNCTION
-----

_.---_._----------_._------_._----------_.

MOOS

B30

Bidirectional data line (bit 5) to
memory for DMA operation.

X

X

M006

B40

Bidirectional data line (bit 6) to
memory for DMA operation.

X

X

MOO7

B27

Bidirectional data line (bit 7) to
memory for DMA operation.

X

X

MOOA/

B14

Bit 0 of upper half of memory
address (used by DMA)

X

X

MOlA/

All

Bit 1 of upper half of memory
address (used by DMA)

X

X

X

X

X

X

X

X

X

X

I

I
i

I
I
II

I
I
i

!

A12

M02A/

Bit 2 of upper half of memory
address (used by DMA)

i
I

I

i
I

B13

M03A/

B7

M04A/

Bit 3 of upper half of memory
address (used by DMA)

I

I
I

i

Bit 4 of upper half of memory
address (used by DMA)

I

Bit 5 of upper half of memory
address (used by DMA)

I

I

i

B18

MOSA/

I

M06A/

B9

Bit 6 of upper half of memory
address (used by DMA)

X

X

M07AI

B47

Bit 7 of upper half of memory
address (used by DMA)

X

X

NOOA

BSI

Bit 0 of lower half of memory
address (used by DMA)

X

X

X

X

X

X

X

X

X

X

NOIA/

BS3

Bit 1 of lower half of memory
address (used by DMA)

N02A/

BSS

Bit 2 of lower half of memory

N03A/

ASO

:::r:s:f (::::rb:a:~:f memory
address (used by DMA)

N04A/
l - -_ _ _ _

I

AS3 L;B;it 4 of lower half of memory
address (used by DMA)

~J_____

_~

9-3

I

II

I

.1

________.

11

___--'-~____

Table 9-1.

I/O Interface Signal Glossary (continued)
ORIGIN
CPU
CaNT

SIGNAL
MNEMONIC

PIN
NO.

FUNCTION

N05A/

A54

Bit 5 of lower half of memory
address (used by DMA)

x

x

N06A/

A15

Bit 6 of lower half of memory
address (used by DMA)

X

X

N07A/

A9

Bit 7 of lower half of memory
address (used by DMA)

X

X

MRST/

B44

Master Reset. Signal used to clear
X
all control flip-flops in controllers.

ODOO/

B39

Output Data Bit

a

x

ODOlf

BIO

Output Data Bit 1

X

OD02/

A26

Output Data Bit 2

X

OD03/

B58

Output Data Bit 3

X

OD04/

B37

Output Data Bit 4

X

OD05/

Ala

Output Data Bit 5

X

OD06/

B26

Output Data Bit 6

X

OD07/

A58

Output Data Bit 7

X

PRIN/

B54

Priority In. Low signal from preceding controller indicating I/O
controller has priority to request
interrupt operation. PRIN/ is
passed serially from CPU to controller to controller, etc.

X

X

PROT/

A55

Priority Out. 'Low signal originating in CPU and passed from
controller to controller carrying
interrupt request priority.
PROT/ becomes PRIN/ on input to
each controller.

X

X

RTCl

B46

Real-Time Clock input, for user
supplied RTC frequencies other than
the standard power line freq (120 Hz)

SELI/

B52

Select in. A low signal from preceding controller .which occurs after
an interrupt or concurrent I/O
request during acknowledge time.

'----------<-------- ----.-

9-4

X

X

X

Table 9-1.
SIGNAL
MNEMONIC

PIN
NO.

I/O Interface Signal Glossary (continued)
ORIGIN
CPU
CONT

FUNCTION
SELl/ indicates controller has
priority to place its address on
data lines for an interrupt or
concurrent I/O operation. SELI/
is passed serially from CPU to
controller to controller, etc.

SELO/

SPARE/

A52

B49

Select Out. Low signal originating
in CPU and passed from controller
to controller which passes select
priority from controller to controller. SELO/ becomes SELI/ at
input to each controller.
Spare. Available for use by DMA
'controller or other customerdesigned option as an internal CPU
interrupt. Enters CPU at internal
status register bit I where it is
OR'ed with other internal status
bits, and ultimately sets bit 4 of
file register O.

X

X

i
!
i
I

I
i

I
I
I

X

I
I

I

-

'----------_.

PANEL TERMS:
CLKF/, STPF/, RUNF/ INTF/
ES04/-ES07/
ANEP/
RUN/

Panel CPU Control Switches
Panel Sense Switches
Enable Console Switches
CPU in RUN MODE

TTY TERMS:
TTYXI
TTY B
TTY 0
TTY G

Serial
Serial
Serial
Serial

9-5

TTY
TTY
TTY
TTY

Input
Reference Voltage
Output
Ground

SECTION 10
OPERATOR CONTROLS

SECTION 10
OPERATOR CONTROLS
10.1

CONSOLES

Two control console options are available: system console and basic console.
These consoles differ in their number of displays and controls. This range of
consoles permits the user to tailor the cost to meet the control and display
capability required for a particular application. The system console is
shown in Figure 10-1, and the basic console in Figure 10-2.
10.1.1

System Console (Standard 1600 System Console)

When using a standard Micro One backplane, the 1600 system panel can be used
providing complete control and display facilities. It is primarily used for
maintenance, system and firmware checkout. The console provides for display
of the micro-one registers in addition to the functions of the basic console.
The features include:
•

Run and halt indicators

•

Display of A bus

•

Display of M, N, and L registers

•

Display of read-only-memory output

•

Four sense switches

•

Six control switches, including run, step, interrupt, clock and
reset

•

Manual command execution

10.1.2

Basic Console

The basic console provides minimal control capability and is designed for
dedicated system application where operator control is not required. The
features include:

10.2

•

Run and halt indicators

•

Four sense switches

•

Five control switches including run, step, interrupt, clock and
reset
DISPLAYS ON SYSTEM CONSOLE

The following paragraphs define the usage of the displays on the system
console.

10-1

II
I I

I

c:::J c::J

REGISTER DISPLAY

I

I I I I

I

.--

I I

I

I

I I

I

I

I

I

@]

I

D

DODD DODD DDDD DDDD

~

'COMMAND SWITCHES
STEP CLOCK
RUN
RESET
INT

1000001

PANEL

[Q

4

3

2

IDDD

1

01

LOCK
RESET
PANELLOCK
HALT
I

I

I

I

I

ION(@)
OFF

MICRODATA

Figure 10-1.

Figure 10-2.

~
II]
[9

MICRO 1600 System Console

Micro One Basic Console

10-2

I

1600

I

10.2.1

Data Display

The l6-bit data indicators (16 lamps on console) display the 8-bit A bus,
Memory Address, 16-bit Control Memory output, or 12-bit control Memory
Address as selected by the Display Selector switches.
10.2.2

RUN

The RUN indicator is on when the processor is running.
10.2.3

HALT

The HALT indicator is on when the power is applied and the processor is not
running.
10.2.4

LOCK

The LOCK indicator is on when the panel is disabled.
10.2.5

PANEL

The PANEL indicator is on when the command switches are enabled and substituting for the control memory.
10.3

SWITCHES ON SYSTEM CONSOLE

System console switches are defined as follows:
10.3.1

Display Selector

The 4 interlocked switched located in the upper right corner select 1 of the 4
displays as follows:
D - Data:

This 8-bit display is the processor's A bus. The data on
the A bus when the processor is halted and in the panel enable
mode depends on the setting of the command switches.

M - Memory Address: This l6-bit display is of the memory address lines.
This is normally the contents of the M and N registers.
L - Control Memory Address:
L register.

This la-bit display is the contents of the

10-3

C - Control Memory: This l6-bit display is of the output of the control
memory. When the processor is halted the R register contains
the same data.
10.4

COMMAND SWITCHES

These 16 locking switches are substituted for the control memory when the
PANEL switch is in the down position. When the processor is halted, the
switch setting is constantly clocked into the R register and depressing the
CLOCK switch causes the command set in the switches to be executed. The
command may also be executed repeatedly by depressing the RUN switch. These
switches are used to gate registers onto the A bus for display and for entering data into register.
10.4.1

Panel Switch

This locking switch selects the source of commands. When in the normal up
position the control memory is used and when in the down position the 16 command switches on the panel are substituted for the control memory.
10.4.2

Sense Switches

The four locking sense switches are available on the control panel.
switches may be read by an Enter Sense Switch command.
10.4.3

These

Run

This momentary contact switch places the processor in the run mode causing it
to execute microcommands.
10.4.4

Step

This momentary contact switch places the processor in the run mode and as long
as the switch is depressed causes an internal interrupt. The halt internal
interrupt is bit 7 of the internal status. This switch is normally microprogrammed to cause a processor halt. Since the processor is forced to run
when the switch is depressed, the computer can be microprogrammed to cause a
single macro instruction to be executed.
10.4.5

Interrupt

This momentary contact switch places the processor in the run mode and causes
an internal interrupt. The_console interrupt is bit 0 of the internal status.
This switch is normally microprogrammed to cause a console interrupt.
10.4.6

Clock

This momentary contact switch causes the processor to execute a single microcommand. If the processor is running at the time the switch is depressed,
the processor will come to a forced halt following the current microcommand
execution.

10-4

10.4.7

Reset

This momentary contact switch halts the processor and clears the L register,
I/O control register and other control flip-flops. The reset is made available
to I/O devices. Since the current microcommand execution will not be completed,
the computer should not be stopped by this switch.
10.4.B

On-Off-Lock

A 3-position key lock switch enables and disables the panel. The key can be
removed in any position. In the OFF position, the panel is inactive. In the
ON position, the panel is active. In the LOCK position, power remains on, but
the panel switches are not active except for the sense switches.
10.5

ADDRESS SYNC

A sync jack is mounted on the rear of the front panel for maintenance purposes.
A positive pulse of 200 nsec duration is obtained when the contents of the
L register are the same as the address set into command switches 14-0.
10.6

REGISTER DISPLAY AND ENTRY

Use of the register Display and Entry is discussed in the following paragraphs.
10.6.1

Display

The processor registers can be displayed directly be selecting the proper
display selector or indirectly by use of commands set into the command switches
to cause the register to be gated to the A bus where i t can he displayed by
selecting 'D'.
The R, U, MD and aD registers cannot be displayed, but the R register will hold
the same information as on the R bus when the processor is halted. The M, N
and L registers can be displayed by selecting them with the display selector.
The file registers, T register and LINK can be displayed indirectly by setting
the commands shown below into the command switches and selecting the data
display (A bus). Panel switch must be on.
Register

Command Setting

Selected File Register X

CXOO

T Register

B020

LINK (AL)

BOBO

LINK (ML)

BOB2

10.6.2 . Enter
Information can be entered into a register by executing a command from the
panel. This requires turning on the PANEL switch, setting the command into

10-5

the command switches and pressing the CLOCK switch. In addition, control
functions such as interrupt enable or the file select can be performed by
executing the appropriate command. The commands for placing the literal 'ZZ,
in a register are shown as follows:
Register

Command

T

11ZZ

M

l2ZZ

N

l3ZZ

U

l6ZZ

File Register X

2XZZ

L

10.7

(Page
(Page
(Page
(Page

0)
1)
2)
3)

l4ZZ
l5ZZ
lCZZ
lDZZ

OPERATING PROCEDURES - SYSTEM CONSOLE

The following list of commands is a minimum that should be tried out when first
becoming acquainted with the Micro-One.
1.

Loading and stepping the L register
a.

Load L
1)

Set CLOCK, RESET

2)

Set PANEL on

3)

Select L display

4)

Set the following commands into the command switches and
press the CLOCK switch one for eacho On the Micro-One
manual loading of L causes L + 1 to be loaded into L.

Settings Switches

Display

l4A9

OAA

1454

055

l5FE

IFF

lClO

211

lDED

3EE

10-6

b.

2.

Step L
1)

Set PANEL off

2)

Set RESET

3)

Select L display

4)

Each time the CLOCK switch is pressed, the L count should
increment, skip, or jump. If no ROM board is plugged in,
the L count will step.

Test M and N
1)

Set PANEL on

2)

Display to M or N

3)

Set the following command into the command switches and press
the clock switch once for each.
1255

Load M

M

55

13AA

Load N

N

AA, M

a

Try other values and repeat
3.

Test ROM and L register (with Micro One/10 firmware)
1)

Set PANEL off

2)

Set RESET

3)

Select L, C

4)

L

C
000

BF02

001

2BOO

002

2AOO

003

4010

Repeatedly press the
CLOCK

After this, the L value depends on computer register
because of conditional skips and jumps.
4.

Test the T register
1)

Set PANEL on

2)

Set DISPLAY to D (A bus)

10-7

states,

3)

Set the following sequences into the command switches and press
the CLOCK switch.
11AA

CLOCK

Load T
Display T = AA with copy T

B020

CLOCK

1155

Load T
Display T = 55 with copy T

B020

Try other values and repeat
5.

Test the File Registers
a.

Load and Read each File.
1)

Set PANEL on

2)

Set DISPLAY to D (A bus)

3)

To load file f, set the following command into the
command switches and press the clock switch once:

xx

2fXX
4)

data value

To read file f, set the following command into the
command switches:
cfOO

Load file f
Read file f

2fXX
cfOO

clock
Do not clock

10-8

SECTION 11
MICRO-ONE CPU OPERATIONAL DESCRIPTION

SECTION 11
MICRO ONE CPU OPERATIONAL DESCRIPTION
11.1

GENERAL

This section describes, separately, each major function of the Micro-One
processor. The individual descriptions include a verbal portion and a block
diagram. The block diagrams contain references to the accompanying annotated
logic schematics. The references identify integrated circuit chips by logic
page number and chip number.
The breakdown of the operational description is as follows:
1.

Arithmetic Logic Unit and Multiplexer

2.

T Register

3.

File Register

4.

Rand U Registers

5.

L Register

6.

Condition and Link Logic

7.

l1emory Address Registers (M and N)

8.

Destination Register Clock Logic

9.

Command Decode ROMs

10.

Programmed Input/Output

11.

Interrupts

12.

Memory Sequencer

13.

Computer Clock and Run Control

14.

Computer Start Logic

15.

Automatic Power Fail and Power On Detection Function

11.1.1

Arithmetic Logic Unit and Multiplexer

The Arithmetic Logic Unit (ALU) shown in figure 11-1 consists of an 8-bit,
2-input, programmable arithmetic logic function generator; an 8-bit latch to
provide A bus and A bus outputs as well as to prevent logical racing. It
further consists of logic to determine carry-in; and an 8-bit, 8-channel
multiplexer to select 1 of 8 possible inputs to one port '(B) of the ALU
function generator. The function generator consists of 2 74181 chips, which

11-1

LITERAL FROM REG - - - - _ _ .
BITS 0-7

~~~----~~O

ALU
MODE

SHIFT R4 AND
SENSE SWITCH

INTERNAL STATUS

2

FILE REG
BUS
(ALAX/

FILE BUS
.:,;R;,,;.T..;S::..:.H,;.;I,;..F.;,.T...;,1____. . 3
A BUS
(PORT A)
(S)
ALU
S·BIT
LATCH
(S)
ALU MUX
PROGRAMMABLE
MUX
~~,:....;..;.;..:;..;...;,....-_... ARITHMETIC
L--r-~ A BUS/
S
BUS
LOGIC
ALU
,;..I.;;,B.;;,U.;;,S_______- t... 5 CHANNELS
(ALBX/l (S)
FUNCTION
CARRY OUT
GENERATOR
.;;,B.;;,U.::;S/:...-______- t... 4 ALU

,;..1

..:.T...;,R.:.,:E:..:G=---______--t... 6

LATCH ENABLE CLOCK
(TT2 + TT3)

...;T....;R.;,.E;;;..G;:.:/________~ 7
CARRY·IN
LOGIC

CARRY TERM FROM
DECODE ROM

MUX ADDRESS 3

OP A' R7/

MUX ENABLE 2
L -_ _ _ _

R REG, BITS 0,1,2,6

' - - - - - - - LINK

Figure 11-1.

Arithmetic/Logic Unit Block Diagram
11-2

have 16 arithmetic and 16 logic functions, selectable by 5 ALU mode input
lines (ALSl, ALS2, ALS3, ALS4, ALM). One input channel, A, consists of the
file register bus and the other, B, is from the ALU }IDX.
The ALU MUX channels are as follows:
Channel 0 - 8-Bit literal from R register, used for all literal class
commands such as literal-to-register, literal-to-file,
add-literal-to-file, and skip commands. '
Chennel 1 - Shift file right 4 to lower 4 bits, and 4 sense switches to
upper 4 bits. For each of these, the alternate 4 bits are
equal to l's, which value is achieved by disabling either
the upper or lower 4 bits of the ALU MUX (with EALBL or
EALBU).
Channel 2 - Internal status consisting of console interrupt, DY~
termination, real-time clock, step switch input, power
fail interrupt and 3 spare inputs.
'
Channel 3 - Shift right input. Since the ALU function generator has
the capability of left shifts only, the 8 lines from the
file register are entered into the MUX and displaced one
bit position to the right to generate right shifts.
Channel 4 - Input bust.
Channel 5 - Input bus. Whenever T register is designated as a data
source by a firmware command and I/O control bit I03X is
set, the input bus is actually selected by the ALU MUX
instead of T. When T/ is designated, input bust is selected.
Channel 6 - T Register.
Channel 7 - T Register/. T or T/ may be designated by firmware commands
as data sources.

The

~rux addresses, and ALU modes for implementation of the firmware commands
are shown in Table 11-1.

11.1.2

Carry In

Carry In (CIN) to the ALU is determined by the firmware operation as follows:
Firmware Operation

Carry In

1.

Literal to register

Not applicable

2.

Add to file

o

3.

Test zero and test NOT zero

Not applicable

11-3

Table 11-1.
Mode

~~U

MUX Addresses, ALU Modes, and Carry In

ALU ML~ Address (3 lines)
Address
MUX Channel

Firmware Conunand
Function

ALU Mode (5 lines)
Mode (HEX)
Function

Carry In

1rxx

Literal to register

0

Literal

'lA'

B

N/A

2fxx

Literal to file

0

Literal

'1A '

B

N/A

3fxx

Add literal to file

0

Literal

'09'

A+B+C

4fxx

Test if Zero

0

Literal

'lE'

AI\B

N/A

5fxx

Test if not Zero

0

I Literal

'lE'

AI\B

N/A

6fxx

Compare

0

Literal

'09 '

A+B+C

7f1r

Enter Sense Switches

1

Enter Sense Switches

'15'

B/

7f2r

Shift Right 4

1

Shift Right 4

'15'

B/

7f4r

Enter Internal Status

2

Internal Status

'15'

7f70

Enter Console Switches

7

T/

'lF'

=0
=1

Clear I/O, I03x

7f8r

Clear I/O, I03x

7F9r)

Set I/O} I03x = 0
States
I03x = 1

to )
7fFr
8fOr

File + 0 -+ r

8f2r

7
5

7/5

Ti
Input bus

Ti/Input

'lE'
bus

'IF'/'lE'

I

A

I

i

N/A
N/A

I
I
I

I

AjA

1\

B

I

N/A

I
I

NA

'OF'

File + T-+r

6/5

T/lnput bus

8f4r

File + l-+r

7

8f6r

File + T +

8f8r

File + Link ~ r

r

N/A

j
7

1~

I

AAB
I

0

N/A

A

'IF'/

I

i

I

7f8r

I

N/A

B/
I

0

I

A+C

0

'09'

A+.B+ C

0

NA

'OF'

A+C

1

6/5

T/lnput bus

'09'

A+B+C

1

7

NA

'OF'

A+C

A = FILE BUS INPUT
B = ALU MUX INPUT

C = CARRY
/\ = AND

+ = ADD
- = SUBTRACT

¥=

V

= OR
EXCLUSIVE OR

A/
A NOT
T = T REGISTER

Link

Table 11-1.

ALD MUX Addresses, ALD Modes. and Carry In (continued)
----------

-----~-~--

Fi rmware Command

C~~::FFi~e-~F::::n-

f-'
f-'
I
Ln

Address

T~r

}lUX

~o_d~ __ ~EX)

Channel

7

NA

'00'

6/5

T/lnput bus

7

1

'06'

I

A- B - C/

1

NA

'00'

I

A - C/

0

9f4r

I

File -

9f6r

I

File - T - l - . . r

6/5

T/lnput bus

'06'

9f8r

File - Link ---. r

7

T/

'00'

AfOr

read.
mem •

l~r

l~r

read
f - 1
mem •

Af8r

read
f + L----+r
mem '

BfOr

read

m_(~_m_=_'_l_:

Bf2r
Bf4r

I

7

'FF'

T/

'00'

~

A - B - C/
A - C/

I
I

0
Link/

I
I

I

A

I

N/A

7

L_

1---. r

(T)

0

A - C/

Link/

(L)---. r

'------------------------ -

I

I

A+ C

Link

I

A+ C

1

-------1

A + C*

0

'09'

A+B+ C*
A + C*

a
a

'09'

A+B + C*

1

'09'

A+B

T/

'OF'

7

NA

6/5

l/Inp ut bus

7

Bf8r

'OF'

T/

. 7 __

(T)-.. r

(T) + 1----+ r

I,

I

I

Bf6r

'00'

T/

7

I

0 -----.. r

!

I A - C/
•

__n__
:_)_l_---.
___r___

+

T/

I

I

Af4m

I - -_ _ _+__

Carry In

Func tion
A - C/

File -

AfCr

--

I
I

I

read
f mem •

--

----~-~---

9f2r

I Af4r

.-.--~----------

AID Mode (5 lines)

ALU MUX Address (3 lines)

..-

,

'OF'

I

NA

6/5

T or Input bus

6/5

T or Input bus

I
I

'OF'

I

.L

-----------------

I

+ C*

*FILE OUTPUT DISABLED

Link

Table 11-1.

ALU MUX Addresses, ALU Modes, and Carry In (continued)
ALU MUX Address (3 lines)
Address
MUX Channel

Firmware Command
Function
Mode

'lB'

T/ or Input bus/

'lB'

AvB

N/A

NA

'03'

'FF'

N/A

(f) OR (TI)-. r

7/4

'FF'--.. r

7

Cf2r

(f) OR

Cf4r
Cf6r

7

(T)~r

Carry In

Function

N/A

6/5

(f)--.r

Mode (HEX)

A
AVB

NA
T or Input bus

CfOr

ALU Mode (5 lines)

'IF'

N/A

"

DfOr
Df2r
Df4r
I-'
I-'

I
0\

(f) EXOR O~r
(f) EXOR (T)~r
(f) EXOR (TI)-..r

T or Input bus

'19'

A~B

7/4

T/ or Input bus

A'r:/B

NA

'19 '
'10'

NA

'IC'

T or Input bus

'IE'

(f) EXOR l-+r

7

EfOr

(f) AND O-.r

7

Ef2r

(f) AND (T)-.r

6/5
7/4

(f) AND (TI) ---+ r

I

I T/ or Input bus/
I NA

N/A

A

NA

Df6r

Ef4r

'IF'

7
6/5

AI

I

I
I
I

I

0

'IE'

N/A
N/A
N/A

i

I

I

N/A

AAB

I

AAB

I

i

N/A

I

N/A

I

I

N/A

I

Ef6r

(f) AND

7

l~r
---+------

FfOr
Ff4r
Ff8r

3

Ff6r
FfAr

..

t

3

Enter Link

Enter 1
Enter Link

A

I

Shift Rl

;_J;ift

Enter 1
-

Ff7r

'IF'

II

Shift File Left
Enter 0

Shift File Right
Enter 0

i
--'--,-

i

A+A+C i

'oc'

I

3
3
3

I
I

!

I
r

!

R1

'OC'

A+A+C I

1

Shift R1

'OC'

A+A+C :

Link

I

I
i

Shift R1

'15'

Shift R1

'15'

Shift R1

'IS'

i

I

B
B
B

!
I

II

i
I

I

r
--I

~----

I

0

N/A
N/A
N/A

Firmware Operation

Carry In

4.

Op Code 7

Not applicable

~.

Op Code 8, 9, B, F

Determined by Carry In
(CIN/) ROM which decodes
the Op Code (bits 15-12)
and the C field (bits 5,
6, 7) to result in CIN/
of LINK/, 0, or 1 as shown
in Table 11-1

6.

Op Codes C, D, E

Not applicable

7.

Op Code A

When Op Code A (Memory) is
processed, CARRY IN is
determined by the CIN/
ROM for all C field conditions, except for C = 10XX
in which case a special
CIN source is selected when
the M register is designated

The special Carry In for Memory command with decrement, and M destination,
1,s as follows:

13

14

15

OPA
.......

'V

7

12

~

MEMORY
COMMAND

I

0

11.2

4

x

x

~

Rl" RO " -OPA
v-'
Memory
Destination
Command

'--

5

R7/R6
DECREMENT

For this condition the Carry In term (CIN/)
" R2/

6

1\

-~
M

= LINK

3

I

x

0

2

0

0

----

M
DESTINATION

" ~
R7/ " R6
DECREMENT

T. REGISTER

The T register is the hub of data flow through the Micro-One. It is a
primary input to the ALU via the ALU MUX. It drives the Memory Data bus on
Memory Write functions, and it drives the Output Data bus. T is loaded from
either the CPU A bus on firmware operations, or the Memory Data bus on Memory
Read functions. The T register is illustrated in Figure 11-2.

11-7

WRITE DATA ENABLE

I"lj

1-"

OQ

~

Ii
(D

I-'
I-'

J

.
N

t-3
I

J;>j

I-'
I-'
I
00

(D
OQ

1-"

T/(S)

MEMORY DATA
BUS (MDX) (S)

A BUS

(8)

T REGISTER
INPUT MUX

(8)

(D

Ii

to

C"l
~
t:;j

1-'.
Pl

LOAD T FROM
MEMORY DATA BUS
(LT2)
LOAD T FROM
A BUS (L Tll

MEMORY DATA
BUS (MDX) (S)

OUTPUT
DATA
BUS
DRIVERS

OUTPUT DATA
BUS (OTBX/) (8)

T REGISTER
T(8)

C/l

rt

I-'
0

MEMORY
DATA
BUS
DRIVERS

T-LOAD
ENABLE

OQ

Ii

Pl

S

TI

T

TOALU
MUX

Gated drives, activated by Memory Write (WRIT), drive the Memory Data bus
while non-gated drivers drive the Output Data bus. T and T complement go
directly to the ALU MUX.
The input to T is selected by a 2-channel MUX. Loading of T is strobed by
either the firmware generated T destination strobe (LTl), or by a Load T
strobe derived from the Memory Read strobe (LT2). The T register is a D type
latch in which the output follows the input as long as the strobe is present.
11.3

FILE REGISTERS

There are 16 8-bit registers designated as File Registers in the Micro-One.
See Figure 11-3. Of the 16, 15 are general purpose random-access and the
remaining one (File 0) is for condition flags, interrupts and I/O flags. Two
16 X 4-bit chips are used for the general purpose files (address 0 being
nonaccessible). An array of 2-input gates is used for File O. When File
Address 0 is selected, a File 0 Enable is generated by the File Control logic,
otherwise a File Chip Enable is generated. The general purpose files and
File 0 are tied together, open collecter, to form the File Register bus.
11.4

R AND U REGISTERS

The R register contains the l6-bit firmware command being executed. It is
loaded at the beginning of each cycle by the TT4 phase clock. The R register
is always loaded, even if the CPU is halted, except when Thold is active.
The Rand U registers are shown in Figure 11-4.
Thold temporarily prevents execution of a command; therefore, the command
must be saved in R until Thold goes inactive and then is executed.
If the firmware command from· the Control ROM has either a 0 Op Code (Execute)
or is an operate command with 8 or higher op code and has a 7 destination, the
contents of the U register are ORed with the upper 8 bits of the command prior
to loading the R register. This is done by use of a 2-channel multiplexing
latch for the upper 8 bits of R, which selects either the ROM output directly
or the ROM output ORed with U.
The U register is loaded by a firmware command from the A bus.
11.5

L REGISTER

The L register, shown in Figure 11-5, is the Control ROM Address Register
containing 10 bits, thus it can address lK words of ROM or 4 pages. The
lower 8 bits of the L register consist of a counter which can be clocked,
parallel loaded, or reset. The upper two bits are latches which can be
individually loaded, or reset. The lower 8 bits address a page size of ROM
and cycle independently of the upper two bits when in the L count mode.
Unless L is loaded, L is incremented 1 count for each firmware instruction.
Counting is suspended when in Halt or Thold. During idle periods, the
counting continues.

11-9

+5V

PULL UPS

A BUS (8)
- - - - - -.......... FILECHIPS
FILE REGISTER BUS (ALAX/)
(OPEN COLLECTOR)
READ
WRITE
MEMORY

FILE ADDRESS
R8-Rl0 (4)

FCW/
FILE CHIP
WRITE Few/
FILE CHIP
ENABLE FCE/

FCE/

FILE ZERO
ENABLE FOE

FOE

CONDITION FLAGS

INTERNAL & EXTERNAL
INTERRUPTS

FILE 0
GATES

SERIAL TTY INPUT

Figure 11-3.

File Registers Block Diagram

11-10

UPPER R BUS (RB8-RB15)

~----,~

UPPER R
REGISTER
MUx/LATCH

UPPER R
REGISTER
(R8-R15)
UPPER R CLOCK

A BUS (8)

- - - -__.t U REGISTER 1 - - - - - - I I w
'--_ _-..I

U SELECT
LOGIC

U LOAD CLOCK

PULL
UPS
LOWER R BUS (ABO-RB7)

LOWER R
REGISTER
LATCH

LOWER R
REGISTER
(RO-R7)
LOWER R CLOCK

L is parallel loaded by the following commands:

Literal to L firmware command
1

4

X

X

1

5

X

X

1

C X

X

1

D X

X

The literal is loaded into the lower 8 bits via the A bus.
of L are loaded by 4, 5, C, or D as follows:

11

I/O
L BIT9
(R11)

11.5.1

10

The upper 2 bits

8

9

[ ~JJ
LOAD L
DESTINATION
(RS1/RS2)

I/O
L BIT8
(RSO)

L or K Destination in an Operate Command

2

1

0

II

OP CODE

----

4 = L DESTINATION
5 = K DESTINATION

The lower 8 bits of L are loaded directly from the A bus. Bit 8 is loaded from
bit 0 of the destination via RSO, providing odd or even page selection. Bit 9
is not affected by this operation, therefore the effective jump is confined to
the half of the ROM at which the previous address was located.
When L is loaded, or a skip operation occurs, the instruction immediately
after the load or skip is inhibited by the IDLE function. This is necessary
because of the "look ahead" feature of the CPU during execution of a microcommand, the next microcommand is being fetched from the ROM.
When L is loaded from the system panel using the load L instruction, setting
of IDLE causes clocking of L one count higher than the value set on the
front panel.

11':"'12

Rll
OP CODE 1

L BIT9
LATCH

L BIT9

L BIT 8
LATCH

L BIT8

L REGISTER
OUTPUT

LO TO L7

MICROCOMMAND
ADDRESS

RSO

LOAD L ENABLE

A BUS (8)
L CLOCK

LCOUNTER
BITS 0-7

(COUNT AND
LOAD)

Figure 11-5.

L Register Block Diagram

11-13

11.6. CONDITION AND LINK LOGIC
The Micro-One condition and link logic is shown in Figure 11-6. There are
three ALU operational conditions maintained and utilized in the Micro-One:
overflow, negative, and zero. The negative condition is simply bit 7 of the
A bus and zero condition is simply the eight input AND of A bust. Overflow
is divided into two categories, arithmetic and shift. For shift overflow,
overflow is the same as Link; namely, the bit shifted out of the file (ALA7
for left shift and ALAO for right shift). For arithmetic operations, overflow
is defined as when the carry in to the most significant bit does not equal
carry out. Expressed logically:
OVFL

=

(ALA7/\ AB7 /\ A7/) v (ALA7/ /\ ALB 7/ /\ A7)

In the Micro-One, a combination ROM and 8-channel multiplexer are used to
generate both the arithmetic and shift type overflows. The ROM selects one of
four overflow sources, based on the firmware command Op code and ALU mode. The
four sources are A7, A7/, Shift out bit, or O.
Zero, Overflow, and Negative condition terms are stored in latches which are
updated on command from the firmware. Zero and overflow conditions are also
used directly for the firmware skip tests. The zero condition latch has
separate update logic because.of the requirement for "reset but not set" on
linked zero tests over mUltiple bytes.
Link is determined from either ALU carry out or the shifted out bit from the
selected File depending on whether an arithmetic or shift operation is taking
place. Link is unconditionally updated on both arithmetic and shift operations
except for the Op Code 3 Add to File command for which neither Link or Condition
flags are affected.
11.7

MEMORY ADDRESS REGISTERS (M AND N)

The M and N registers, shown in Figure 11-7, are each 8-bit tristate registers
which contain the read/write memory addresses while a memory cycle is taking
place. M and N are loaded from the A bus by firmware command. Whenever the
N register is loaded by a l3XX command the M register is cleared to O. This
is accomplished in the Micro-One by disabling the M register output on a load
N command without actually~ clearing M.
11.8

DESTINATION REGISTER CLOCK LOGIC

The Destination Register Clock Logic, shown in Figure 11-8, generates the load
register strobes for M, N, U, T, L, and interrupt enable registers. Also, a
Load 0 strobe is generated for external use.
Destination addresses are located in two places in the firmware command.

11-14

A BUS BIT 7
FILE BUS CARRY OUT

R REG

.....

FILE BUS BIT 7
-..;;....----

OVERFLOW
DETECT
ROM

OVERFLOW
ISOFIl

OVERFLOW
CONDITION
LATCH

CLOCK

QFLO

1-":::';"=-.

MUX BUS BIT7

A BUS (8)

ZERO
CONDITION
LATCH

ZERO
CONDITION
DETECT
ZERO
DETECT

UPDATE
CONDITION
FLAG COMMANDS
CLOCK

ZERO CONDITION
UPDATE LOGIC
UPDATE
CONDITION
FLAG
LOGIC

CLOCK

A7

NEGATIVE
CONDITION
LATCH

LINK SELECT
FILE BUS CARRY OUT
TO OVERFLOW DETECT
MUX

ALH CARRY OUT
FILE BUS BIT 0
FILE BUS BIT 7

LINK UPDATE

LINK
LATCH

CLOCK

Figure 11-6.

Condition & Link Register

11-15

DMA MEMORY
CYCLE

ABUS----~----------~

1----+-------.

N ADDRESS
LINES

1---+------..

M ADDRESS
LINES

N
REGISTER

M
REGISTER

~ADN

M
RESET
LATCH

COMMAND

Figure 11-7.

M and N Address Registers

11-16

CLOCK

LOADL

LOAD L
LOGIC

LDO/
R REG

LT1/

BITS 0-3

DESTINATION
REGISTER
CODE
SELECT
MUX

DESTINATION
REGISTER
DECODER
AND
CLOCK LOGIC

LM/
LN/

R REG

LU/

BITS 8-10

LD7/

OPI tUPPER/LOWER SELECT

CLOCK (GT4)

MI,IX AND DECODER ENABLE OPOP/

UN DECODED
DESTINATION
REGISTER
TERMS

Figure 11-8.

Destination Register Clock Logic
11-17

11

LITERAL COMMANDS
WITH OP CODE 1

OPCODE

o

10 9 8 7

I L:J

LITERAL

DESTINATION
ADDRESS

320
OPERATE COMMANDS

OPCODE

CONTROL

ADDRESS

A 2-channel multiplexer is used to select the correct destination address
according to the op code. Most of the destination register strobes are
generated by a decoder having one of its inputs a GT4 clock. In some places,
non-clocked or differently clocked destination register terms are needed.
These terms, identified as RSO to RS3, are provided for generation of Load L
clock, file write clock, and indication of M, N, and T destination terms to
generate T hold.
11.9

COMMAND DECODE ROMS

Firmware commands in the R register are decoded by read only memory chips to
generate control terms. The ALU mode and MUX addresses are generated directly
by the ROM's. Other terms are generated, such as 10 decoded OP code terms,
which are used as inputs to discrete MSI and SSI logic functions to generate
all of the register update control terms. In addition, the command decode
ROM's are used to generate a carry-in and link, skip, and idle updates.

5

ALU MODE

R REGISTER
3
31 K
ROMS
PLUS 2
256 BIT
ROMS

LINK

103X

10

ALU MUX ADDRESS

DECODED OP CODE TERMS

CARRY IN TERM
IDLE

4

Figure 11-9.

LINK, SKIP, AND
IDLE UPDATE

Command Decode ROM's Block Diagram

11.10

PROGRAMMED INPUT/OUTPUT

The programmed I/O, shown in Figure 11-10, consists of separate 8-bit input
and output data buses. The output bus is driven from the T register through
inverter drivers. Zero true logic is used. The input bus goes directly to
the ALU input MUX. Both input and input/ go to the MUX. Input/output control
is accomplished with three lines, identified as I01X/, I02X/, and I03X/.
These lines are set or reset by the firmware command:

8

12 11

15
7

o

76543

FILE

II03XII02X II01XI

DESTINATION

Clock time for setting the registers is GT4. The IOXX/ register is a D type
latch where the outputs follow the inputs as long as the clock is present. '
The Serial Teletype output is driven by I01X, I02X, and I03X/, and TTY0
from transistor driver.
11.11

INTERRUPTS

The Micro-One features two types of interrupts: internal and external. A
block diagram of the Micro-One interrupt structure is shown in Figure 11-11.
The internal interrupts consist of: console interrupt, power fail/restart,
stepswitch interrupt, real-time clock, and four spares. The internal
interrupts are input to the Micro-One individually via the internal status
channel of the ALU MUX, and collectively via the eight input OR gate to bit 4
of File O.
Internal interrupt latches are reset by either Master reset or the firmware
command, enter internal status. The console interrupt consists of a clocked
latch which is always enabled, and thus always responds when the console
interrupt switch is depressed.
The power fail/restart interrupt consists of an RS latch which is set by
power fail and held in a clamped-on state during power-on with release of
clamping taking place immediately after releasing Master reset.
Real-time clock consists of an interrupt latch which is set each time a realtime clock pulse occurs, if the real-time clock enable latch is set. Realtime clock pulses are generated by a level sensor which has a full wave
rectified power line signal as an input (120 Hz) or (100 Hz). The Step switch
interrupt contains no latch and is tied directly to internal status input and
to the internal interrupt input gate.
11-19

INPUT B
ALU
MUX

8

A BUS
ALU

8

ALU
LATCH

8

FILES

ALU MUX ADDRESS

M. N. l. U
REGISTERS

OUTPUT
BUS

T REG MUX
AND

TREGISTER
DRIVERS

T REGISTER

tOXX 3 INPUT/OUTPUT
3
INPUT/OUTPUT
3 R4 ,5,6
~-..... CONTROL
......I----t CONTROL
I·~~----------------------~~
DRIVERS
LATCHES

SERIAL
TTY
OUTPUT

SERIAL
TTY
OUTPUT
LOGIC

Figure 11-10.

I/O CONTROL
DETECT
LOGIC

Programmed I/O Block Diagram
11-20

I/O CONTROL
CODES

EXTERNAL INTERRUPT
EXTERNAL
INTERRUPT
GATE

EXTERNAL
INTERRUPT
ENABLE
LATCH

FROM
REGISTER

INTERRUPT
ENABLE
COMMAND
lOGIC

FROM POWER
SUPPLY

FULL-WAVE
RECTIFIED
POWER
SIGNAL

1 - - - . - TO FILE 0

REAL-TIME
ENABLE
LATCH

TO
ALU MUX

REAL-TIME
CLOCK
INTERRUPT
LATCH

REAL-TIME
CLOCK
DETECTION

RTC!

INTERAL
INTERRUPT
TO FILE 0

INTERNAL
INTERRUPT 1-_ _. DETECT
LOGIC

CLEAR
SPARES
STOP
SWITCH
CONSOLE
INTERRUPT

CINT/
RC
NETWORK

CLOCK

CLEAR

L-+-_ _ _ _....~ TO ALU MUX

L--!:::~~_ _..
SET INPUT
FROM POWER FAIL
DETECT CIRCUITS

FROM
REGISTERS

POWER FAIL
INTERRUPT
LATCH

CLEAR

ENTER INTERNAL
STATUS
COMMAND
DETECT
LOGIC

Figure 11-11.

Interrupts

11-21

TO ALU MUX

11.12

MEMORY SEQUENCER (CORE MEMORY VERSION)

Memory timing pulses are generated by a state sequencer (shown in Figure 11-12)
which is organized around a ROM, a command latch, and a sequence counter. The
six primary outputs from the sequencer consist of Memory Read Strobe (RTXX/),
Memory Write Strobe (WTXX/), Memory Ready Command (READ), Memory Write (WRIT),
Load T Strobe (LT2), and Memory Busy State (MBSY).
The inputs to the sequencer consist of: DMA Request (DMAR), DMA Write (DMAW),
CPU Memory.Request (OPA) , CPU Write (R4), and CPU 1/2 cycle (RS). Commands
are loaded any time Memory Busy is inactive. If there is no active command
at load time the sequencer goes through one idle step and immediately loads
again. There are five command input lines; therefore 32 different sequences
are possible. When a command is loaded, memory busy becomes active, so the
command remains loaded, and the sequence counter advances until memory busy
becomes inactive. There are a maximum of eight 200 nanosecond steps possible
for each command sequence. For Core Memory Control, the 32 command sequences
are organized as follows in the ROM:
-

DMA

CPU

I
CPU
memory
active
I

I

WRITE

CPU
full cycle
read

CPU
full cycle
read

DMA
read

DMA
write

CPU
1/2 cycle
read

CPU
1/2 cycle
read

DMA
read

DMA
write

CPU
full cycle
write

CPU
full cycle
write

DMA
read

DMA
write

CPU
1/2 cycle
write
_ _ '. __ o

CPU
memory
idle

READ

CPU
1/2 cycle
write

I
I
I

DMA
read

DMA
write

_ _ _ _ ••

idle

idle

DMA
read

DMA
write

idle

idle

DMA
read

DMA
write

idle

idle

DMA
read

DMA
write

idle

idle

DMA
read

DMA
write

All DMA memory operations are full cycle.
The outputs from the ROM consist of RTXX/, WTXX/, READ/ and MBSY/
The 8-step sequence patterns for memory control are as follows:
11-22

DMA
REQUEsT------__~
DMA
WRITE ------__~
CPU MEM
MEMORY
REQUEST------__~ SEQUENCE
COMMAND
LATCH
CPU
WRITE------........

4

~~~R~T~X~X~/------------~READSTROBE

LOAD
WTXX/

~-+-~.;,.;,.;,.:.;.,;;------------.

WRITE
STROBE

MEMORY
SEQUENCE
ROM
~~__~R~E~A~D~--. . READ

COMMAND

CPU 1/2
CYCLE ----If-_-I
CLOCK ----Ir-.......

MEMORY
SEQUENCE
COUNTER

~4---------~~M~B~S~Y~/--__.MEMORY

4

BUSY

DEGLITCH
INDOW
LOAD

WRITE
DATA
ENABLE

CLOCK ---+--.....~
~

SEQUENCER
__-ILOAD
LOGIC

~~~------~

NOTDM

MBSY --------41~

LOADT
STROBE
LOGIC

MBSY/
CPU MEM
REQUEST------.....~

EARLY
MBSY
LATCH

Figure 11-12.

Memory Controller Block Diagram
11-23

Table 11-1.1.

8 Step 200 Nanosecond per Step Sequence Patterns
for Memory Control
11.1.1

DMA or CPU Full Cycle Write

RTXX/

wrxx/

READ/

MBSY/

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

1.

1

1

1

1

1

1

1

11.1.2

DMA and CPU Full Cycle Read

RTXX/

WTXX/

READ/

MBSY/

0

1

0

0

0

1

0

0

1

0

0

0

1

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

11-24

11.1.3

CPU 1/2 Cycle Write

RTXX/

WTXX/

READ/

MBSY/

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

i

1

1

1

1

II

1

1

1

1

1

1

1

1

1

1

1

1

II
I

i

II
I

I
11.1.4

RTXX/

CPU 1/2 Cycle Read

WTXX/

READ/

MBSY/

0

1

0

0

0

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

'I

1

- - --

I

I,
I

-

Priority
Priority is established by the following methods:
1.

When any memory sequence is in process, MBSY prevents loading a new
command (either CPU or DMA).

2.

On simultaneous DMA and CPU requests, the CPU request is held off by
the T hold logic until the memory becomes unbusy, and another DMAR
request is not present.

11-25

11.13

COMPUTER CLOCK AND RUN CONTROL

The clock generation logic (as shown in Figure 11-13) consists of a 20 MHz
oscillator with a 4-bit shift register to generate a 4-phase 200 nanosecond
clock. Each of the phases is approximately 50 nsec wide. The phases are
identified as TT1/, TT2/, TT3/, and TT4/. The repeating cycle is maintained
by reloading a binary 0111 pattern each time TT4/ = O. Starting of the clock
is achieved by entering a 0 into the serial input any time all phases are
simultaneously high, which state will occur whenever the clock goes into
improper operation.
Control of the CPU is established by enabling the clock phases under various
operating conditions. The enabled clocks are as follows:
GT3
GT4

RUNX A TT3

Used to set Halt on Firmware Command and panel clock.

= RUNX A TT4 Used for register update, Condition flag update, file
update, I/O control register update, interrupt clocks.

Load L Clock
LOAD R

=

=

(RUNX/) A (TTl + TT2) /

TT4/ A THOLD/

L COUNT CLOCK

= TT4/ A THLD/ A HLT/

ALU LATCH UPDATE

=

LOAD MEMORY SEQUENCER
11.14

TT2 + TT3
=

TT4/ AMBUSY/

RUN/HALT CONTROL

RUNX (see Figure 11-14) is made up of three terms as follows: RUNX = Halt/A
ATHOLD/ A Id1e/. Ha1t/ is the main run enable term of the CPU and is manually
set by panel control, or automatically by the power fail/power on function.
The Halt state can be caused by Firmware command, Panel Clock, or by Master
Reset.
Tho1d (see Figure 11-14) is a temporary run disable which is caused by
simultaneous occurrence of memory activity requests. There are four functions
which cause Thold:
1.

Attempting to alter M or N during a memory cycle.

2.

Requesting a Memory cycle while one is in process.

3.

Selecting T as a source before a read is complete.

4.

DMA and CPU simultaneously requesting a memory access.

5.

Changing T during a write strobe.

Tho1d stops all CPU firmware functions, including R register update and M, N,
L, U, and File update and Input/Output register update.

11-26

o

PRELOAD
INPUTS

LOAD

20 MC
20 MC
OSCI LLATOR ~C~LHO~C~K~-""''''

REGISTER
RESET

4 PHASE
CLOCK GENERATOR

SHIFT
REGISTER

TTl/

TT2/

I----II~

TT4

TT3/

CLOCK
START
LOGIC

GATED CLOCKS
TT3/
RUN

TTl/--....

XI

TT4/--....

TT2/

TT4/

TTl + TT2

Figure 11-13.

Clock Generation Logic, Block Diagram.
11-27

M OR N DESTI NA TI ON
WITH CPU MEMORY
CYCLE IN PROCESS
CPU MEMORY REQUEST
WHILE MEMORY CYCLE
IN PROCESS
SELECTION OF T
SOURCE DURING
MEMORY READ

T HOLD
LOGIC

--,---,~

SIMUL TANEOUS
CPU AND DMA
MEMORY REQUEST

GO/
RUN X GATE

RESET
CLKF/---~

FIRMWARE
HALT
CODE

RUN X

HALT
DET
LOGIC

..

CLOCK

HALT
LATCH

IDLE
SECONDARY IDLE,
FIRST
COMMAND

:§

AFTER RUN
GO/
BYPASS
_ _ _ _ _ _ _ _ _ _ _ _ _ _~~_L~A-T-C-H--------~~
CLEAR

SH~~T1

PRESET

TT1/

MRST/
IDLE/
SKIP
LOAD---"

SKIP
COND
MUX
PRIMARY
IDLE
LATCH

UPDATE IDLE
CLOCK
LOAD L
HALT

IDLE
UPDATE
CLOCK

TT1/

Figure 11-14.

Run/Halt Control Block Diagram.
11-28

Idle (see Figure 11-14) is a temporary run-disab1e which occurs for one
firmware clock cycle and is caused by a skip or load L action. During idle,
the R register is still updated so that the next firmware command can be
fetched, but all other functions are disabled. Idle disables Tho1d to prevent false Tholds on non-executed memory-related functions immediately
following a jump command.
11.15

COMPUTER START LOGIC

There are five different inputs for starting the Micro One as shown in
Figure 11-15.
1-

Panel Interrupt

2.

Panel Step Mode

3.

Panel Run

4.

Panel Clock

5.

Power Fail/Restart Interrupt

All of these inputs share a common computer start latch and computer start
pulse logic. The computer start latch is set asynchronously to the computer
clock and re1l1ains active until reset by halt, or released by the power fail
interrupt input. The computer start pulse is synchroniZed by clock phase
TT3/, at which time GO/ is generated. GO/ is input to the clear side of the
Halt latch. Halt/ is input to the computer start pulse logic to inhibit
subsequent GO/ pulses.
Four of the computer start inputs are for panel control. These utilize a
common RC pulse network, and separate diode isolators. The CPU differentiates
between the four as follows:
Panel Interrupt and Panel Step mode are also input to the internal interrupt
portion of the CPU, where they are recognized by the firmware. Panel clock
is also input to the Halt Detect logic to generate halt after one Firmware
Command has been executed, and to the First Command by-pass logic to prevent
bypass when Panel Clock is activated as opposed to either of the other three
panel start modes.
The Power Fail/Restart Interrupt generates the rema1n1ng start term. For
~ither Power Failor Restart, it is necessary to generate a GO/pulse.
The
Power Fail Interrupt will always be activated during these times, and will
force the computer start latch to an active state where it will remain until
released by acknowledging the Power Fail Interrupt. Multiple GO/ pulses are
inhibited by the Halt/ input to the computer start pulse logic.
11.16

AUTOMATIC POWER FAIL AND POWER ON DETECTION FUNCTION

The Power Fail Detect logic (shown in Figure 11-16) consists of an RC filter
and an analog level detector. The input is a full-wave rectified signal from
the power supply. The level sensor has a feedback resistor to generate
hysteresis. This hysteresis prevents fluttering of the power fail circuitry
11-29

~--------------~. . TO INTERNAL INTERRUPT

PANEL
INTERRUPT

DIODE
ISOL

PANEL
STEP
MODE

DIODE
ISOL

PANEL---1 DIODE
ISOL
RUN

PANEL
CLOCK

HALT

~

RC
PULSE
NETWORK

SET

HALT/

COMPUTER
START
LATCH

DIODE
ISOL

TO HALT DETECT
LOGIC

Figure 11-15.

Computer Start Logic, Block Diagram

11-30

TT3/

GOI

l-rj

/-'.

+12V

OQ
(:!

l'i

ZEN EO
REGULATED
REFERENCE
VOLTAGE

(\)
~
~

I

~

.'"

SUPPLY

RC
FILTER

1ST
LEVEL
SENSOR

""d
0

°1

~

(\)

RC
TIME
DELAY

I'i

~
~

'"':I
Pl
1-"

MASTER
RESET
TRANSISTOR

MRST/

~

I

I;:j
(\)

~

rt

VJ

2ND
LEVEL
SENSOR

°2

(\)

RC
PULSE
NETWORK

("l

rt

t""

POWER ON
INTERRUPT
CLAMP
TRANSISTOR

0

OQ

1-"
("l

td

~

0

("l

i'"
I;:j

1-"
Pl

RESET INTERRUPT
FROM FIRMWARE
OR MRST/

POWER FAIL/
POWER ON
INTERRUPT
LATCH

PFINT/
TO CPU

OQ

I'i

Pl

a

---.

INPUTTO
COMPUTER
START
LOGIC

at the power fail threshold levels. The input RC time constant is set so
that the first missing power line pulse will be detected. When power fail is
detected, two things occur: the power fail interrupt is immediately set, and
after approximately a 2 msec delay, Master Reset is activated and remains
activated while the power supply voltages decay. The function of setting of
the CPU for power fail, such as saving the registers in core and coming to
halt, is accomplished by software and firmware during the time between Power
Fail Interrupt and Master Reset. During the initial part of power on, the
Power Fail Interrupt is clamped to an active state. When power reaches a
correct level (plus a delay) the level sensor switches output levels and
starts a delay of approximately 100 milliseconds, at which time Master Reset
is released, leaving Power Fail Interrupt in an active state, to be
acknowledged by the firmware/software.
For manual operations, the Power Fail Interrupt can be made momentarily
inactive by depressing the Master Reset switch.

11-32

SECTION 12
SCHEMATICS

COMPONeNTS
USfiD

0

ReSISTOR

1<~2

RES MOOUL.

ZZO

CAPACITOR

CZ7

DIOOE:

CRI4

TRANSISTOR

Q3

CHOKE

LI

CRYSTAL

YI

E:. POINT

fil'

-

I

17

17

I

17

15
17

18

17

B

05C

C

I

18

J 18

I

I

I

E

II<>

lIP

74/0

I

10

18

J

B

I

110

i 10

4

4

15 110
9

I!O 1/0

74109

M

7400

7475

41 15 113

B

1514 14

8

74H04

I
I

8 18

4
7442

8

[i]

7417

74H22

9312

9

10

I~

I

13

-i

4)

I-.E

j;''II7>
cQ7S

10,'5f:I )S

81B

liP

7475

7417

8

.3
5303-3

5303-4

4

.3

12

9322

5.503-2

7475

8

71711<>

74H04

7

10

14

14

IP240

1<>240

13

13

741~1

741G.1

A

0

13

.. _,.

0

E:
121/0

12
74175

3

12

5302-1

7475

12

74298

5PA12E

J

'"

1/

II

74173

74173

II.>

9

'3

'3

9

9

7

I<>

10

9309

7474

7474

10

10
9312

310lA

7

10

10

9

r::

12

7432
12112

74298

7132

H

II

II

74173

74173

.5

5

7475

7475

B

5302-2

9312

9312

I 12

I

12 t 12

4

l-

74H04

12
f.I

Ii:

10

121

,

7

10

74175

12

~312

C

IS

HH74

7436

1.>11.>1"'
74H04

~240

13

5

71717

~240

C

I~

.3

71717

14

8

BIB

5303-1

I
B I

14

SPARE

9312

B

B

t--

I

C

93/2

I&>

4,:

1;1{

2

B

4

9

9

~

-i

7420

1410

7430

9

\\).

-:J.P.

c21.' Ftr)

E.O.

3

7474

I

J.N.

M.F.

4T.

12
9

7402

10

J

I<

L10
I 10

I<

L

7403
10
10

I

10

I 10

7451

SPARE

7430

7425

9312

9312

310lA

7403

10

9

8

7

'"

5

4

3

5

5

74161

74/81

M

Z

-

L

I

CURf2E:NT REV IGlolololololololGlolololOlolGlolO FI
SHE£T NO.
1'lzI314Isl"'17IsI9110IullzI/31/41ISII"I" 16 1

,OR -21 FI~MWA~o SeT ~UT fiTCH
fil
E2 (COMPONENT SIDE)

<'

ALL CAPACITORS

A Rfi
AlD

I. ALL RESISTORS

,.OIllM ._ . . . _,

5EE

5

9

@]>J.C AT LOCATION 78 TO Bfi SELeCTeD
~CCOIi!DING TO NEE.D FOR MOS ME:MORY
(-2~ OR CO!eE. Mr=MORY C-I).

z.

4 lie.

I

9322

I8

(I< OF)

A

G

7425

SPA12E

4

PI IV I

o

SEE E.O.

SPA12E
15

8 1151/~

9
II;

I

8

7438

7410

18

40';'e.

A

74H04

8

74H04

I

PILOT RELeASE
REY/SED AND
NeW I?EL54SeD

I~

B

9322

I 15
I8

I
I

10

-

741(,,1

9 14 19

9

OWN CHKD APPD DATE

DESCRIPTION

ZONE

F

151151 4

B

10

74HOO

10

7417

liP

74fW4

'3

0

5

7408

I Iq

7427

L

I

-'1<.6>2-

I

151

151/51 4

110

110
t1~.
liP
- - _ .51
12

I 4
I 12

4

181 18 1

7402

I<

I

7474

74504
13

530 4

15

74HOO

7402

1402

H

I

4

18

I 18

7402

15

74195

I",

I 15
I 15

15 1 5 1 15

15

7475

8

,

7475

4

7~OZ

-

15

15

7420

I",

I 18

17

15

15

74H74

7404

E

4

5

'"

15

15

151 /8118

D

I /I
I 17

7474

15 1/8118

C

7

15

74HOO

~bl2.

D

15

17

sl

D

1

r",

GND
GIJO

"

TTYX I
TTYB
TTY!jJ

NO.

J4

1("

I

1("

2
3

1("

4

MOOI

a

MOO"

8

/0
/I
12

NO

N03AI

/I

14
/5

NOOA I

/I

NOlA /

/I

MOOD

/I
8

4

PTX/ /
M03A/

15
II

5

M04AI

II

/"
/7

IJ04A I
N02A /

1/

'"

"PSI<
kTAD/

15
1.5

18

NCJ5A I

/1

8

UBSY I
15
)1'/,(// 15

/9

+5V
+5V

10
II

GND
GND

13

20

12
13

CPH2 I

/4

-/G.Z5"V

1/

SI-_+_--+___ +__t-_+_-+..-'C0Pl+ 01'.1. \8"g~D3E 2

A1

R7

0~ :,

(~no 4
A2
04

,

AI

E

~.,\.I=-O=- 1.,1

i! 10

NOTE 1: ALU INPUT ADDRESS
IS DETERMINED BY
-OPCODE
-I03X (INPUT SELECT)
.SUB QPCODE (BITS 4-7)

~~-

1'2. _ _ _ _ _ _ _ _ _ _ _
01 P-'~

7

-

AlU
CONTROL
TERM

AL'O.O '5

AI

S f>.O

GND

9

04

CTo,
AS -e,

R7

R12

B

4F

.. 1

SHEET

a

OF

1

1<5

I

REV

+5V

r - - - -Z8- - - - - - -

-1

I Zh

1
USED TO SELECTLiNK UPDATE FROM
SHIFT DIRECTION

/

QPCDDE DECODE

~1,~R~5~~~________________________
RO_M
__N_O_._2____~__~
10

D

~

PR. 20005'l02.-2

l'l.~R~IZ~ ______________________~~
II

3J

I

01

IK

IK

Z

3

IK

>IK

-- ---5

~

IK

'"

A.D CTG.-E
02 2.

TERMS

~~~~

1'Z~R~14~____________________________________~~
I'>

14

1'l. R ,<;

1~

~~~'~~~~?P~~~;: ~~g~~;~~~SUI

IDLE

.2

r)6

t.

A.~

A.4-

IS"

18 RUNX / '

5

/5 TT/ -I- TTZ



0P7·RI/

I!S

/8

/0

~pESTlNATION

E

70
,400

S

4::r2-

I

'-

t

3

I

I
I

-'I

"1442.

1

'14

121

U

A

4A.

4B

OPCODE

RSO

::~,~~:;::"" <~
741104

GATED T4 18

2.Y

3A

4

5

DESTINATION REGISTER
DECODER

ZA.

13

RO

lY

11. UPDATE
iDLE

RSZ/

'"
7F

" 'n'l.2.
, 'l.B
iB

D

1/

~

2. lA 5"

i1f12 ~~
Rq
11

q UPDATE;

RUNX·TTI·TT2

LOAD L CLOCK

DESTINATION
REGISTER
MUX

'-----"'

UL

0PA/RIS

EXCEPT MEMORY

9 7H
----------------------"-1
74/ 0

"00. ""."0

9,1<0

'25P7/

5
4

q.l
"'EET

4

_ _ _~4_ _ _---1._ _ _---'~ _ _._--l.._ _ _ _ ~!!.--_ _ _...l-.-_ _ _ j

OF

/8

0
REV

4

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- . ___

INPUTS

10

ALF\O/

FROM
FILE

10

ALAI/

10

ALAe!

10

AL A 3!

REG
BUS

o
INPUTS

~~3M

~~~E

LOWER4BITS

2.3 AI
/

I

FO 9

:t

SELECT 3
3

ALse

ID

ALS3

I~

. .!A~O!L_

I

PI'AI3 I

IQ

4Q f-"'8_ _ _ _ _ _ _ _ _ _ _ _ _...cA

FI t:}'10"--_ _ _ _ _ _ _ _7'd4D 7475

BilL

IK

Fe \I

:

G

F3 13

3

e

13
.-=

8,10, Ii'., 13

D

r-~9---------~I>_--_{~PII~AII4D

3QN.;"-_ _ _ _ _ _ _ _ _ _ _ _.,;A=<:_ 8,10,1<:,13
3Q

3D

='-

AD!L / '1,11

~

i'.G 14

3

\

40

8,IO,Ii'.,13

MOLl '1,11

A 3 74181

-'-'~-c:c------__-+__"\+--+--='i'03

ALM

ABUSO-3

Ai'.

5 SI
4 'Oco

\

I-'-______________

19

=A=A=~~:~::/===============~:=====::='8~-'----~·~2---~-'--~~"-'----

74/7

1

PR200053D3-4

r--_--"5"-1 A7

,,'- "R-'-'-'4'---+_ _ _ _ _ _ _ _ _+--__--'-1A£TG.:FQ4~

-+__-"'-1E'. AS (",eoo)

Ii'- ",;R,,;,I"'3'--+_ _ _ _ _ _ _ _

13 -R-''''---IH---------+----''-1F\3
13 -'-'R..:':>=--_+========+-_ _--'-j7 Ae

MSBAL:U~IO-A-=L~A~7~!--~6~~~s~~~~NA~:~~~E~~~E:~DM~AS~T~~~HGL'C_H_+------''''~AI
I OF CONDITION FLAG
INPUTS*7

"

ALB7/

L

3E
Q2. II

5 AO

e-~

13 EI

~_--,14.0E2.

J

OVERFLOW CONDITION
DECODE ROM

A

+5V

Q3~ I

12. -'-.:R""2.=----f+_ _ _ _ _ _ _ _+-_ _-"-I:l M

-

I
I

L-f--+--'-1' DO
~DI

- - - '1 L---"''''ID2.

t--<'9

: r---~-'-jD3

_'~_:J
"'
5

w

OVERFLOW CONDITION

14

9312.

~D4
I---

~D~

-.lOb
~D7
__--c:'3::j:,c

L--+__-"I2.:::;SB
L---+--..:I~"'OA
IOE

A

OVERFLOW CONDITION
SELECT MUX

9

*

INDICATE'S

4

TI1IICE'ON THIS PAGE

_____1 ._.________ ~ ____________'________2

__ T

1

LITERAL BIT 0

12. RO

'" to

Ito C [N T /CONSOLE
10

1 /SHIFT

ALA

r P/-B32

o

DO
2. Dl

ALII4 /SHIFT RIGHT • INPUT

'8 TO

8

INTERRUPT STATUS

4 D3 'BIZ

RIGHT 1 INPUT

04

W

~H>~4,--__________-=~

D5

r

'Y~

Dt.

1000/ INPUT BUSO

TREGO

5M

3 DZ
.,

h4f\04

,

14

ALU INPUT MUX
BIT 0

ALBO/

;;

__

D

"I D7

TO/ TREGO/

+SV

,---------...:'-'-1' SO
, -____---"=-j2. S 1

i! /4

, -__-'-'3=-, 5 2.

IK

~

E

DMA.T / II.

-

12. R 1

LITERAL BIT 1

DO

10 _A~L'2Ac''5.c/:....:cSH~I''_F.:.T:_R..:.T:.:
.•:.:':::N:..PU:.T~_ __+-+_j-t-_+-...=.21 D 1 S L

~._-*_++-+_t-_3,,-10 A LA'Z. / SHIFT RT. 1 INPUT
1001/INPUTBUS1

c

8

I

03 '1312

S

04

7

DiD

'"

07

w

~
I 5 H>--=-'2-J--I--.f---+--=-{,-~ 05

P/-AI.O
8 Tl

D2

4

74HD4

TREG 1

TI/TREG1/

'-+-1--+-~I_',

50

+-++-,-,12.'-1

S1

14

ALU INPUT MUX
BIT 1

I
I

A\..BV

;;

y~

- -

- --,1
I

c
I

.--+---"13",, S2

I

~E

1

,
1

1

LITERAL BIT 2

12 R2.

-

DO

10

ALAe.

lID

RTC. / REAL·TIME CLOCK STATUS

10

ALA":> / SHIFT RT. 1 INPUT

I SHIFT RT.' INPUT

I

3 D2
..,. 03 'BIZ

I[P~/i::-]8~"'E;z[.}JI~D2.<0~z?.!./1'~N"'.P':!.UT~BU~S~2~--_:_+_1--+__t-~'S D 4

W

8

B4H04

TREG2

B

ALU INPUT MUX
BIT 2

1

AlB2/

I

'5 - - - __ I

I

I

'l

Dc;.

"l

D7

I

.--+-J--I,-,-,II'-1 SO

I

T2/TREG2/

+5V

14

Y~

+-__-"-9.q5H'>-'8'--+--+-+-j_~t._, DS
8 T2.

TOALU
INPUT
CHANNEL B

2. 01 SK

I
1

B

._+-+---,I,-,'2.~, S 1

+-+--,-,\'3'-1 S2

~E
LITERAL BIT 3

12 R"-

to

--

SPARE

* to

ALP-.7 /SHIFT RT.' INPUT

2

!
g

A

ALU MUX
ADDRESS
SELECT

3

II.

ALB;?,/

S

Dl 5,)

cepil-~8[5[7[}~~~?~IUO~/~~~-t~~---r-l~t--t--~~ O~
403

ALA4/SHIFTRT.1INPUT

!-+-i__t-~Sl

__
[E~~¥I!?0~0'.:3~/~IN~P~U~T.!:BrU~S~3~::--:PI-A!.Z

8

SPIO /

DO

To

0

4

~,>",0'--.f---+--+---l_-"iD'-1 OS

T REG 3

V74H04

"7 0"

T3/TREG3/

q

931 '2.
W

y

U4

ALU INPUT MUX
BIT 3

r!L

0,

__t-~I~' '30
1~"':2..!.1__________________________--t-_+-,-1-=-j2. ~ I
B

JB~S~O~_ _ _ _ _ _ _ _ _ _ _ _~-+-1

~ ~

~

~ B'52

1:1

'32.

4

10

E

EALBL / ENABLE MUX LOWER

ALU INPUT MUX BITS

A

a-

3

Ie ISC2000150<:a 10

7f INDICA TES TWICE ON TNI$. PAGE

I ~I~ I
~
18
I
____________',_'_1_ _ _._--"'2,_ _ _ _ _1'___._.__1___
SHEET

___ ._____4 ____.__J.'-_____

.~

OF

REV

1,

ALASI
PI-A32.

':::'1'-

I

13 ~

12

IoH

1

SENSE SW ,

:,

SHIFT RT. 1 INPUT

4

I D04 /

S

INPUT BUS BIT 4

D

IIJS/r 10

8

+sv

ffi
r4

-

Ro;

"

E'505'

I PI-85~

"PIZI

ALr..b I

10

1005/

C

-1-

--

5H

-

(,

12

,

IK

ALA, /

10

3~

4
V74H04

Tu.

8

IK S

LITERAL BIT 7

17

09-2
PFl NI I

ESD,

8/00

I

liB

Tr

r.
3
3

Ti

I

D4-

14

ALU INPUT MUX
BIT 5

ALB5'1

5'-----

'(~

OS

I
I

SO

I

51

I
I

52

I

I

t-K

IK

IK

7

5

,
I

03

''1312.
W

DS

y

I

0",

I'>

~

I

I

111>,.2
.,H

SENSE SW 4

Z

14

r--!2-

ALV INPUT MUX
BIT 6

ALBl./ 5 _ _ _ _

CHANNEL B

•
I

I
I
I
I
I

3

4
S

~~

{"

74li04

I TREG71

I

'51

I

I
I

E

I
I
I
I

r.J

1

Dl

I

0203
04

q'!>IZ

1
1
W

14

'( f-'2-

OS

ALU INPUT MUX

ALB,I

BIT 7

01

SO

BSt

12.

BS2

13

EALl'>1l1 ENABLE MUX UPPER

10

0,1

A

'.

E

I c ISC2000lS0G ID
I I
OWG
SIZE

.

-~

,

5-----.-.!

52-

ALU INPUT MUX BITS 4 - 7

--~.---~~

I-

Dt.

11

1 _ _.~_~_

B

I

0,2

ElSO

4-

TO ALU
INPUT

'50

DO

I-

I
I

D4-

1'2

C

I
I
I
I
I

02

9

...... ' , I I ...

- II
I

DI

ZI8

1007/ INPUT BUS BIT 7

T REG 7

1

'1312W

DO

II

+Sy

I--

I
I
I
I

in

74H04V'"

,

I
I

D3

Z.

S

8

3 ---"l.N.LsHIFT RT. 1 INPUT

LPI-

I
I

It.

-.-~ D,

v

Rr

z. I

DO

I

4

T1'4l-\04-

ur
13

IoH

REG 61

B

I

E

-.--~

I
I

T REG 6

IT

1
1

~ E

3

SHIFT RT. 1 INPUT

9

Tlo

0,1

I
I

SENSE SW 3

~IDO!.i/

8

Dl

Ol

1'1

IK

3

D

1
I
I
I
I
I
I
I

9
II

I
I

1

,,

OiO

ZIB

I

--I

I

12.

STPF/

1"

ALU
MUX
ADDRESS
SELECT

S

+SV

~ E50io

A

4

r

._-----

2

-

-~ D2

,~

V,4H04

LITERAL BIT 6

ALB41 ' 5 - - - -

2. 01 H

SENSE SW 2

,

1'3 Rin

8

DGo

I

~H04

T REG 5

I

8

r

ALU INPUT MUX
BIT 4

':.PI

INPUT BUS BIT 5

TS/TREG51

"

-

'( ...!..'L

----S:

4

13

TS

8

14

W

13 '0.2

SHIFTRT 1 INPUT

~'

931Z.

OS

1'2-

II~/O
C,H

1

02.

0"

in

LITERAL BIT 5

[J9~

ll.

II SO

ZI8
IK

IK

l.ll

~M

04

q

T4/TREG41

8

,

1/l4K04

T REG 4

T4

DO

2 01

1

[.::/'74 H 0 4

~.
10

, 5v

'C

IK

1

ES04

J9 -"

i.

"r

LITERAL BIT 4

R"T

I

2

I

SHEET

.7

OF

1

Id

~-.--.-----

I

flEV

--

+SV

15·

T REGISTER INPUT
MUX BITS 0 - 3

o
/8
MEMORY

~C~A

:.

I

INPUTS~8

TO

MDOO

'L

AO

0-

MDOI

ILl 21<

AI

)- MDOZ

~~UTS/
T REG

4

Z

\2

,

lY
9322

2-;

2B

1(11

tel

2Q

(.

8 MD03

II

A~

3Y

7

t. 3D

9

1

4Q

rJt

4B

'1Y

S

It-

E

/

I

MUX

,.J2

E 1·2

~

E~-4

74,5

I

7411

I

....:L-

74~5

/2

I
I
I

II 3

/0

~c:%411

3

TO

¢qQ~[£!.[J

_.-<

:

I
I
I
1

1
I

!~3D

12

l/';4-17

I

'~
9 7438

I
I
I
1
I

51E

~PI-A35!

I
I

¢OOI/

1
I

T2

~
1
I
I

tPDOZ~A4IiJ

I

A

I

t.c

t.O

I

MD04

Z.

A4

3

18

MDOS

14

'LA

~.~

13

MDOG,

5"

Aro

G.

10 48

LOADT
FROM A 4
BUS

LT'2. /

5

LTII

4

'En

ZV

3Y

TO.

~J3-17

8

12

7

(, 3D

4Q.

5
E

,al

'I

1
I

MUX

70
7400

.,

4D

4G/

I
I

:

10

2
I
vi/-]411 1

T3/

r

9

8

I
I
1

I

+15 V

i!1/P

Zl7

fI - - -r.: - - - ---,
470 1'
I'

1470
I

I
I
(;- -L"
5 'i-

S- 'rT

..J

T4

4

~J4-1

I t.f! 2.
V7411

MOOI/

¢D04/

1

1'S"

/3 ~F

/2

~l/7411

II",

10

~V1411

10
9 -7438

I

tPD05"1

LATCH
T LOAD ENABLE

1''51

I
I

T6

r~1iiJ~~
T

I
I

T'x'

T REGISTER

T'x'!

T REGISTER!

OTB'x'! OUTPUT DATA BUS!
MO'x'

MEMORY DATA BUS

5

!/JDOt.1

I
1
1

7
B

P!~.?f.I
r-(p/

1'1

....-----f J3 - 34
MOO?

13

1

P!-B40

I
I

")

7

R

P1-f3Z7l
!/JDD?I jPI-A5BI
T")/

Ie

1

SC2000150 W D
CJ

DEFINITION.OFTEAMS

1

PI-AIO

I

I
I
I
I
1
~MEMORY BUS &
OUTPUT DATA
.B.US DRIVERS

B
7

~

I
.,IE

,)3-1 ..
MOO')

I

/I
I

8

PI-B3f!

1'41

I
",IE

1

l

~'PI-A3G,1

1
I
I

.----~--

;~B
74\1

~ E. \·2
~ E,A

8

¢DO.3/~

I 3D

I

II

J

MOOB

I

I~~'
1 4 7438

IIlI p!2& \'5
7415
3
'LQI W4
2D

4A
4Y

~

2 lD

3Gi

3B

A1

I

IV

4

3A

II

7
~
MEMDRY D ATABUS,
15

28

MOO?

LOAD T FR OM

10-

lA

c

T'L/

I
1
I

'~'
/2 7438

:

8

PI-B43l

l~

I
I

TREG
BITS 4 - 7

PI-810-1

~-!
MOO2

1

I

T REG INPUT
MUX BITS 4-7

8

T1I

1

I
I

l

rV4-3
MODI

I

~r
:
~c
3
'~
I
I 1438

B

tD

Tl

I

I
I
I
I
I

I
I

J91

TO!_

I

'~
I
4 14'38

c

8

4PI'B34!

LATCH

I
I

!

:

5E
II
'~I

I
I

o

-l

~J3-2
M OC

~1
~
h- ~~4

4-QI p§-

4D

.-

4
~

I

30.
3Q/ 1\

4A

10

4

'470
1

•

I

.-l: 5
7

I

I
IS

\0

3B

3

I

•

I

2QI lH·

'LO

I

It.

7'115

5 3A

Ai:.

"""5

lQ

<

I

I

5"0

ZI3

•
<
I
L_ -

T REG BITS 0 - 3

5C

lB

13

TREG??Stj5
A BUS

11>.

Z7

----,------,

r:
470

_.

WRITE ,DATA ENABLE

WRIT

OF

/8

REV

A

HALT IS SET BY FIRMWARE COMMAND 1780 AND BY PANEL CLOCK SWITCH INPUT

~
9K

z

FIRMWARE
HALT

74HOO

3

;;LTL!

18

HALT LATCH

COMMAND
CODES

o

~: ~~:F

SWITCH INPUT

17 581

'~TI!KL'L~



C'L

1

B

B

~

!5

A7

NEGATIVE

/0,
CONDITION
12 D PR Q . 9 LATCH

BIT 7 OF A BUS

NEG.

10

6L
7474

lICF

/8

GT4

~

9K
10
4~

UPDATE CONDITION
FLAG

5 74H(x)

CK Olp;!.

~~
/3

SHIFT OUT TERM

TO OVERFLOW

~---+--'-F;:O:.;R.:O:.:V.:E::.R::.F.:L;:O:.;W'---_+----------..:5:.l0"- ~ DETECT MUX
ARITHMETIC &
SHIFT CARRY
OUT TERMS

A

4
S

ALA7

t- IC?

P
10

CARAY OUT &
SKIP CONDITION
DETECT LOGIC MUX
ADDRESS SELECT

C0UT

ALAO

{:

g30g

..2

F50

I~

FSI

':I

4

lCO

let

J'N

.5
UNKI
Qt>==-------+---~='--

2. ,.--'pT

"h"'+--=-d
D

f-l-

4
LINK LATCH

8K:

A

7474

9L

LINK

SA

a

*INDICATES TWICE ON THIS PAGE

S8
MUX

4

4

UL

UPDATE LINK

81'
3
I~

2 7~08

LINK & SHIFT OVERFLOW SELECT MUX
(REST OF MUX ON PAGE 16)

__ .__ ~ __ _______ 3 ... ____ . _-'---_ _

2

S-C20001.50r;, D
S"EET

9

OF

1

fCJ

REV

~-

1

I

AO

~~ ____________________~4D04L

A BUS
BITS

0-3

{l

AI
--'-'-'-____________________
:gl----l--l-------"d

RCj

9 8

4 1742.5

RIO

5,(",7

. .:R.:.:. :II_______+-________-'-ql-----'.

81=
10 7408

8

9

~f04

r ~1D.:.1=2--,~.=-,,-_
15

B

5,"',7

ALA7

~H04 F0E
~'--"'FI'""L"'E'""Z"ER"'O""E'"'NA""B"'L"'E'----~'-- 10
9

8

1:\

1 10M
3~0~P~B~/_0~p~C~O~D~E~B~______________________~--------------------------~--~1 7451
.,

9
18

3

4
~

l.!l

6T4 ______

~~

GATED T4 CLOCK

~~~~~~~

_____________

0Pe.+ QlP3

LOAD FILE OR ADD TO FILE OP CODES

R53/
R5

FILE WRITE ENABLE

~

________________________

10M

74~1

",,8

FeE/
10

FILE CHIP ENABLE

~~~074~1

~
IOM

4

74,1

3

R4/

10M

10M

7451

Few!

""Go

10

FILECHIPWRITE

'--____-'e.""I 74 S I

~

INTERRUPT ENABLE
CODES

14 74109

.; LD7/

~

/2 R.3/

K

ap:

~
'1/-"

17 MRST/
<) PLUPX

REAL-TiME CLOCK ENABLE

RTce

~~i5~NAL

INTERRUPT

*

INOIC'ATi:$

TWIC'E' ON THIS' PA6£

I C ISC20001S0C;
SHEET

4

3

A

/'"

1-.. i-~EAL-TIME CLQCK &

/0

1

OF

la

0
.EV

,15

r.5" "coLI

o

5"

AOa!

114D

o
R
Y

A
BUS

A
D
D
R

s

A04L./

c

...

4Q.'"

fiB

~

0EZp1-

10.2

I

<.14 -17

IJO,A/ PI-A50

17TRI

STATE
LATCH

r-+-------'

<.14-10
LOWER EIGHT
BITS OF

lis
I, ZJ417

lQ

4

~ Et

LOAD N

(2)E\P-'---+-~

~ EZ
' -_ _ _ _ _--'

~~~~1ATE

....l9c

o

R
A

4Cl.

r

MOOA /

c

~PI-BI4

J

~

'--f <.18 - 2 Z

II MOIA /

&,

P 1_ 1\ III
<.I!i- 19

lJE 10-:.--..

M02A/ PI- A 12

(;lEl::rL
CLK
17TRI STATE

i::'2.

.--+-____...J

I

1.13.,8

3 r?41"3G 5
40)

I

N07A/ PI-A91

\Q:'

~ E\

M
E
M

<.14 - 18

<.1!i-23

-=

'-----+-+-1'-'"'''1 2D 2<.1 'Ul r-=4'-_+_ _ _ _ _,

II

I

I

IJOr.A/ PI-AISI

t~

-

"-___-+--1--'1;..4'-\ ID

--

P 1_ AS"

G!l:2.;L...

CJ~

'--_____+-+--'-1Z"-i

1 IJ OSA /

ADDRESS

I

4J4-1",

~'-+--+---1f-+--+--+_ ~
I Z 3 D 3 K 361. S
~N.+--+--+--,I,-,I-l4D 4Q /-"''''--+_1--_-,

LN/

-

MEMORY

~ -+--+--l__C-14- 'j \ D CLRtQ f-:'=--+---1~ _____--,N.::O..",-,A':':/1 PI - A 5 3

Y

o

I
I

NOlA/, PI-B55

elK

k

"OSL/

'5 A07LI

L-...j <.14-/4

1 NOIA/ _~
1
J4-15

~ EI

i

I-I

-,A-,-O=cIO=cL::.t-/_ _

4

1Cl 4

12 '3D 1.1 361 S
M
E
M

~.~

IG.I-~=------------'-l-~
~

10. ZD741l

5 AO'3L/

--

IJOOA/--'"

CLR

14 10

5 AOILI

I

,)3-20

M03A/PI_BI31

'--------QELJ

LATCH

o

D
R

~
S

B

I ~ P 1- B 7
~~-t-t------------~M~Of4~A~/~~~2

' - - - - - - - ~ -+_+-+--,1,-,4'-1 lD ClRH i : '
4C-.+-+_ _ _ _ _,
1 -_ _ _____
13 2. D"K '2G r-=

?

'---------1

4 Ltv\/
LOAD M

\'2

3D7417~6l

S"

'-----------~M-::..+--+-t-I:..:I-f4D 4G. t.
~ E 1 (lEl P-'--!--'
f--!2c 102CLI(0 ..'2 p-L-

-

UPPER EIGHT
BITS OF
MEMORY
ADDRESS

liS

17TRI STATE
' - - - - - - - - ' LATCH

B

L-...j J 3 - 5

1 M05A/

PI-BIB

T MOr.A/

.)p31_-B295
<.13-1

E2 E I

[±]

M07A/

~6 ~4

PI-B:::

~

--

IK

4

eM /'

THIS JUMPER USED TO DISABLE
UPPER BIT OF MEMORY ADDRESS
WHEN RUNNING 821 FIRMWARE

III

IL.:.~=-ZI,---Cj} 8 A

A

A

I
I
1101

SA

I C 18C2000150~ ID

/5 DMA¢N
DISABLE M 8< N DURING OMA CYCLE

_____~4 __ .______JL _______

3~

I~ I

SHEET

________~I______~2 ________~I_____ _

1/

1

OF

lei

J

REV

+ Y
14
14

RSOtJ

lPI-A,?

A
BU

IIPI-A4Z
I[PI-A43
RSII
14
RSIO
14

{

5

5
5

:>
~

j

RSIQ

RSII

T
U REGISTER

BITSO-3

AO

e

tJ

Ae

"'3D

A':>

74D

I

G

z

IE

•

r

--- I
2

I

/

IF

I
I

10 3F IQ
':> ,
15
CD 7475eQ

AI

LLV

OR

15 TT4/

3Qtl

4Q~

5

THlll

4

IF

12

I

13 h43a

IF

I

E3·4

9

I

10 h4:la

'u' WITH

I

10K,,,

I

/1

IF

5CZ

I

g CI

4,10:-1

4,10,9

RII

QDle.

10,1:'

701

U REGISTER
'OR'LOGIC

5

CLK

10 1"

r.{I.ICROCOMMAND

1

c

CLOCK UPPER A REGISTER

74 c.7

1

PI-M8

L

1

'- .<

'i!3
1470

",-

-.l

3- 's-

2

R513

RSI4
RSI5

R REGISTER MUX LATCH

T

R'OI4

A4

e 10

AS

:0

U
A"

3H /0

"'3D

A7

7 4D

~

£1-2

~

£'.3-4

lID

470

L,--

r:..

I

12

I

13 h43c.

I

470

11-1

Qe 14
I Be
74aQa
~ Ell

RI:'

13

RI'!

QD'e

RI5

1/

I

"l CI

8

I
I

___ --..JI

7 DI

9

11-1

lo174:1e

QA

",,4,5

ZI-I

5 Cc.

"'DC.

QC

~_IZ

r

U REGISTER
'OR'LOGIC

-f-470

I

L._

L

+5V

I

4 743c.

I

J
470

Rle.

Ae

~ AI

I

(,

I

I~

4Q~

,t--- -

15

.<;

I

sat-l

?D7475 ZQ

B.(;S12-15

r~~1
I 74:3e.
I 5 IH
I

W

U REGISTER

BITS4-7

BUS

--8"-_ _ _ _ _
~
L IS CLOCKED
AT ALL TIMES
EXCEPT DURING
HALT & T HOLD

c

18 THLD/

~Z~LOCK

15

741-174

: 48
<0
5~

Q/P:!"

_ j -....__.'-/~I C

74H04

qH~

{

L CLOCK

Cy~

I

~

i
/

" -!:

.!!-'--':.: 5___________________+-+__

~
--- -::.:c

V

QA I--CCI- l0

2C

CK

2.

L05X 1"t-

14

PI·Azzl

10
L REGISTER

~BITSO-3

CO Q,A II

L03X 14

T

CK

PI.A15

I

p_I-=-\=-O.:.:~:

.1.:!.2.-j _ _ _ _ _ _ _ _""T>--___
1\4
QC ,23
LOI X

C

~=______________________-4_____'3~D
~

c

C lI2.
ET

..:.::.:.::~=-------------f----':"-! ~ 7:~~B,
g

B

LO - L9

14
QD~IJ4~~------------1'_BZI
\4 RS05
MICROCOMMAND

I PI'B25

FROM
CONTROL ROM

14

14
Ie RCK/

I
470

\-/p

470

5

RS05

4"

J

10
4

T
12

T
RS07

13

T

A

10

ID

10.1

S

RSOr.

..-

470 I

T

RSOC:;

rPI BZ9
RS07

~o~

RS04

+5Y

ZI

,---

9

74115

za

2D

ZGlI

3D
4D
eLI(

3&
)GIl

4(1

4QI

~~REGISTER
BITS 4 - 7

Z

R4

3

R41

7

RS

3,S,7, '1,IS,l£"

t.

RSI

10

RIP

15

R7

14

R7/

II

10

I-

3,4,5,7,'1,0,15, I"

4,1l.
3,5,l~,\1.o

RIO!

4
3,7
q

A

LATCH

'(I

1 C ISC2000!500

_:":::,_
... __ A _______l_-___ 3

I ~~ I

SHEET

/8

_ _ _-'-I_ _~ ___~_ _ _ _ _ _ _T.L _______

J

OF

/6

ID
I

REV

lA

4K FIRMWARE ROMS (4 PAGES TOTAL)

~

1l
23
08
1 AE! (t.24 01
? ~~
01

,

~5

D

I.
7

A'S
A4

"r.

A~

o2lS

A?.

At
8 AO

I')

18

04

0'3

E3
E4-

02

rEV

~. Ell

-

1271

UPPER HALF WORD OF
PAGES 0 AND 1

.;rtS'/5

~

12,IGo

P.5'14

I£:', It.

15

,12.5'1.3

14-

RSI2

t~

PSII

1\

R810

lZ, II.

10

PS09

Cf

RSOrfi

D

lZ, Ie.

lZ
1'2
1"-

1'2

IB
23

.oK 11AI:I(r.Z40)
Al
,,,

1
Z At.

" A5

010

4
A4S A3

RfC;

t. AZ
7 AI
8 AO

C

~
15

Ii

E3
E4
Ell

01

E2/

i

Z At.

3 A"l
4
A4

7
8

B

1'1
i8

A:'
AZ

C

Al

AD

'I

LOWER HALF WORD OF
~PAGESOANDl

RSO?

IG.

R80<»

0& 1S

R80S

13
13

RSQ4.

£)4 13

Rsoa

03 II

RS02

E3

-

13

14

85

E4
~ Ell

~

UPPER HALF WORD OF
PAGES 2 AND 3

02 10

il8

'5

14-

03 11

Z3
Z40
1 A5((.
Al
0

t.

..

04 13

'LA

-

It.

15

IiJZ

10

PSOI

1iJ1

9

.1:'.5'00

13

I£:.
I£:., It.

B

12,1""

IZ,I"

E2I

'2B
LOCiX
13
L07X

23
1
2
3

13
.:..CC;X
13
LOSX
13
L04X
I'>

-

13

13
13
B

1'3

A

4

LO.3X
L02X
LO.lX
LDDX

5

'7"
8

LD9X

I PI-A3~

I')

CPEN/

18

+5.

~

Z9

7

ZQ

IK.

05

.lI-

A8(~24R) 11.
fJ,7
u7

AfA5

1ZJt.

A4

A'3

AZ
Al

134

AO
E3
E4

I

5

I I I I

LOWER HA LF WORD OF
PAGES 2 AND 3

05 14

I:'

03 II
1ZJ2 10

Ell

£11

A

'i

EV

4K FIRMWARE ROMS (4 PAGES TOTAL)

Ie ISC20001.50w /D
I ~:-I

4

3

I

2

1

SHEET

/~

____ J

OF

/<'1

I

REV

MEMORY
SEQUENCER

I

-

-,

-

--

I

LATCH

I
I

I

~
PI
.3

0

1/3

la

,

I ZI9
1"170

1

1

,

.-

I
I

J

1

.

-/-5 V

I 215
I ~70

I
3

-

-

~

DMAR/ 18

-'

2

RTXX/
15
(j),tJAO
18

A5~

¢PA /

o

RUNX/
R4

I/3 ~D---

2

~
5

8e

7420

" ___

S-\:~~~

'-~~-+~II~~.:~I
~

LOGIC

,---".

4

RUNX·TTI·

HZ

r1z"r---Bc\
Be

MBSY/

~ 17420/

~s
0..£.
D

~

/

I'?, 17,

r r4/ 12,15,18

B

L*:
I

Ie:.

r

18

BB
7474-

MEMORY SEQUENCER
DEGLITCHER

Q

1L-_______

9

QJ.,..:.

CLE

7474

~c

pe

D

PI-A~71

MaSY

~Q~

01-=-

88

A

TT I

CLOCK PHASE 4

MEMORY BUSY

.-

*

_ _ _ _ _ _ _ _ _~r_TL3~/_/~,IB,8

l~=~~~~~t~~~~~[~~~~d-----+-+----;;_:~;_;;;:;;~;_--------~T~r~4~1;,:.13
13

15

CLOCK PHASE 1

-i_-+____~C~L~O~C~K~P~H~A~S~E~3

1_t-t-_ _ _ _

A

~

12>

CLi:

15

~~EARLY MEMORY
BUSY LATCH

TT3/

*UNGATED CPU CLOCKS
EACH 50 NANOSECONDS OUR I NG
ONE 200 NANOSECOND PERIOD

SC20001S0r;-, E
SHEET

4

3

.-L_ _ _ _ _ _2_____ _

/5

1

OF

/~

REV

9 PLUPX
II1R<;'TI

j f l l/'l1RSTI

4

o

SKIP
CONDITIONS

5q
{
9

COUT

COMPARE

12.

A'lR0

SKIP ZERO

11

A ~ R0 / SKIP ZERO NOT
F50

I

F<5'/

LL

r

2CO 9L lY
ZC{30Q

~
f12-

15

\

EXECUTE
COMMANDS
SELECT U

1:

10 2C2.

I
2C3
1 ~ fop.,

II

C

DESTINATION
CODE 7
SELECTS U

ENTER

~~l~~~AL

HLT

2..:!3.2
~
L

I

14

R514

:!2.c

R51S

19

14

* 13

1<500
R501

13A\8

I
I

742'>

I
I 13
I

3B

10.l(

......

Ie.

~~~TE
CLOCK

c!R/!i

FDIIC,OO

I
I

z~T
.S'
D
QF-

1

9H

I
I
I

I

110

REAL-TIME
CLOCK
INTERRUPT
LATCH

7474

+5V

4

RIO

2~
~ 74H2Z

~
9H

R 39

CRI2

~~

,---------,

7474

2.2K

FJ)/-I(.OO

C 2"
300 PI'

GT4

I PII PI-

-r

II C

R41
g.31<

-:f

1C40

IK

~ D PI?QI-''"

r----<

Q/~

a c

12

f-SV

4

I

\3

>-

~~T~S~~L

C

T

LATCH

Q

CI

CINT/

13 .
RllNTI

INTF/

AS

T

+5V

R4Z

S.G,K

TT"B J2-2

SERIAL TELETYPE

If(.

+5V

CRII
FOH("OO

R37

TTYX1

I

R23
IfiO,2W

1

E/

REFERENCE VOLTAGE

T,,,1

SERIAL TELETYPE INPUT LINE

J 2-1

1

R,CI

CONSOLE INTERRUPT CLOCK

83

14

~

I2!RU

I

112 74'2.0

IJ9-t, I I NT F /
LPI- A 4 -1(".15V

o

I

/I

3,4,IB

IDLE"/

t!I

Q

(!

U DETECT
LOGIC

0P7·R7/

13 RS/

*18

~Ir-'OR'

~

14 RSoe
RTCCK
17

{3

CODE

\

:13

IDLE

LATCH

e. ~

~

I

9

Q

PRIMARY
IDLE

I

I

1<51'2.

D

!'LIZ

IOJ

13
~

--

~
PR

SKIP

CONDITION
SELECT
(REF 56 MUX

RTCE

14

14

IZ

8A::
7474

TTl!

RSl?~

14

~8
10 7~H

14

~E~~i.r'~NEA~
10

PI- 6<14

9

UPDATE IDLE

Ul

to

+SV
DATA I/O CONTROL
REGISTER-IQXX

I

B

{
B

"",,"

OUTPUT
CGDE
FROM R
REGISTER

.I ...f

R4

9D

wl L~_

'2. 107415IQI

a~v

2<1

3

13 R'i

2QI

2D

*

3G
(,

1'3 Rw

27

~5

2/7

~70

470

470

7

3

'"

30
741l

IS

5

14

3D

...

B
101 X I

102X /

13

* 16

103X I

3D

*17 MR5T/

fT'''C;

EI·e.
R2S
410

E'3'~

GT4

+5V

220

CONSOLE'
INTERRUPT

U.

POWER FAIL
INTERRUPT

17

f~~r~NAL

G,

A

G,

DMI';T I

L_

.12-(,

SERIAL
TELETYPE
OUTPUT

.12- 3

LINE

I0'3X
3
5TI'1=/

7,17

G.

A

PFINTI

~Pll/

__4-~____2Q

8M ~B~____~I~N~T£ER~'N~A~L~IN~T~E~R~R~U~P~T_______________

lIN\"

JO

74'301

+-__--'!£<1

7 _S"-'-P.:.l.=2o.;1'--____________________....__

:~i~~~~~T---.[~~~J--~S~T~P~FL/-----~---------J~---U~
J9-'j
~~~~;IME

:.12-5

IK

~SP~IO~/____________~-4

{ 7
INTERRUPTS

STEP SWITCH

ClNTI

J

PI- 8",1

I/O
CONTROL
LINES

.,,,TY"-

;,----IK

PI-A31

7411

10

+SV

ggDSEE~"3 0P7-R1

PI-B31

'* INDICA TES TWICE: ON THIS PAGE.

D

1(,_R~T-=C~/~_____________________________~~
SkEET

INTERRUPT

4

3

I~

1

OF

/d

REV

1'5

TT3/
~~--------------------------------------------------~2qIOD

I",

INTF/

PANEL INTERRUPT

~TPF/

STEP MODE INPUT

GO CLOCK

3 q 7402
.--__-::.

CR0
I~

FDHGOO
1<0

0

'I

q

CR7

o

FDHtDOO

HLT/
HLT

+5V

+5V

+'5V

R35

R34

IK

CR9

IK

CRI
FDH
IDOO

Jq _a
PANEl RUN INPUT
__-l~~~~~~~~~t__,-~~~CI1-5__~~~____~~~q
[~~~]-~R~':!.!::!.EL-

I

FOHGOO

300PF

+5V

~COMPUTER

L __7::!2"-- -.J

-=(,80

START

COMMAND LATCH

START COMMAND
PULSE GENERATION

CRB
CLKF

J"I- 10

8A

;)

RG NETWORK

+5V

+IZV

c

1213

eez

DELAYED

30K

/N4001

/214
10

r-----~.

1

CI~

22 U.P

C23

15 V

.... _ _ _ _ _ _ _ _ _ _ _ _ _ _"'M..:-R"'SocT.LI_ q ,IO.13,'5.11O

IK

;0 A>'2.'----e~-----*----+--____1>--_t_I
LMf339/V

+/iV

+

RI9

MASTER
RESET
3 DRIVER

c

R22
IK

+5V

R30

R20

IMEG

200

Tl"2u.f
...Le.5V,!5%

CR3

POWER FAIL
MASTER RESET

-=

GENERATOR

POWER OFF
& ON DELAY
RC NETWORK

Q2.
2N;)72.5

FDHGOO
+SV

R21

a (H~~~R~S~-fI-2~'1

R3

I NE1WORK

IK

I

q

14

B

I

RI5

I
I

~ 1

-=-

1<32

22K.

opTi6i\iii.L.- - l

I

I

I

I

PI-B"!"

RTCI

A

h
I

01.uf'

Z5V
RESET POWER
FAIL INTERRUPT

"'3
£12 " "

PFlNT/ 1,110

POWER FAIL &

POWER ON

+5V

INTERRUPT
LATCH

Ret:.

I

8

I

L: ________ J

3.3K

SENSOR

I

lOB

129

POWER FAIL
DETECT LEVEL

C 2~

ADJUSTABLE
POWER LEVEL
DETECTION
REFERENCE

I.

lose

B

300PF

e5K

FDHfi,OO

CRI4

2.2K FDH
(,00

CI9

Ral

;)K

CR5

RIO

R29
.12K

R21

I 3K

t5V

i.8K I

.-. ___ J

(o..,..

I

IK

IK.

+5V

RS

10K

A

R7
ZZK.

I",

REAL·TlME CLOCK
POWER LINE FREQ
120 Hz OR 100Hz

RU.NT

S'C20001.50G
SHEET

3

_____2 _ _

17

1

OF

/a

0
REV

4~~------------------~

o

I'" IDL~

__________________~/~/-r-

4~R.~~~2~/

/5

c

INHIBITS T HOLD DURING IDLE

PAC CPU MEMORY OPERATION 12

/oH

CHANGE M OR N WHILE
CPU MEMORY CYCLE
IS I PROGR ESS

13
TIMING HOLD
GENERATION
FOR MEMORY
OPERATIONS

15 UBSY

3
.3
.3
15

(iJPA/

9

0'

rHLD

~-------------t----------~~~-12

eSI
LT2

SELECTING T AS A
SOURCE DUR ING A

MEMORY READ
BEFORE T IS LOADED
FRQM MEMORY

DMAR/

CPU MEMORY REQUEST
SIMULTANEOUS WITH
DMA REQUEST

15 DMA REQUEST

c
9

15

rHLD/ IZ ,t,;1

7404

eS2

HLT/

c
HALT

2

9E
7410

Iii

Gr.:J

4

GT4

9

TT.3/

UNGATED
15

/0

TT4/

4,9.10.

COMPUTER CLOCKS

A:;

IDLE/
~________-,Rc:.U=N.:.;Xc.:/_ 4,9,15

17 CLKF/

17 Gtj/

2

PANEL CLOCK INPUT

COMPUTER
START PULSE

II
CONTROL LATCH
WHICH INHIBITS

B

DOUBLE EXECUTION OF

15 TTl /CLDCK PHASE 1

1ST FIRMWARE COMMAND
AFTER RUN IS ACTIVATED

B

A

A

SC 2000 /50 G
SHEET

4

3

2

1&

OF

1&

D
REV



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2011:12:09 10:51:16-08:00
Modify Date                     : 2011:12:09 11:10:39-08:00
Metadata Date                   : 2011:12:09 11:10:39-08:00
Producer                        : Adobe Acrobat 9.46 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:21769f21-f407-4027-9d70-9ec1beaa9c8a
Instance ID                     : uuid:716136de-92d2-41e1-a326-33752be2e637
Page Layout                     : SinglePage
Page Mode                       : UseOutlines
Page Count                      : 196