MPC106UM MPC106 PCI Bridge Memory Controller Users Manual Jan97
MPC106UM_MPC106_PCI_Bridge_Memory_Controller_Users_Manual_Jan97 MPC106UM_MPC106_PCI_Bridge_Memory_Controller_Users_Manual_Jan97
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Overview
Signal Descriptions
Device Programming
Processor Bus Interface
Secondary Cache Interface
Memory Interface
PCI Bus Interface
Internal Control
Error Handling
Power Management
Bit and Byte Ordering
JTAGlTesting Support
Initialization Example
Glossary of Terms and Abbreviations
Index
-..
-.e.•
Overview
Signal Descriptions
Device Programming
Processor Bus Interface
Secondary Cache Interface
Memory Interface
PCI Bus Interface
Internal Control
Error Handling
--
Ell
Power Management
Bit and Byte Ordering
JTAGfTesting Support
Initialization Example
Glossary of Terms and Abbreviations
Index
MPC106UM/AD
1/97
MPCI06
PCI Bridge/Memory Controller
User's Manual
PlJwe,PC
®
MOTOROLA
e Motorola Inc. 1997. All rights reserved.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or
implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this
document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out olthe application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical' parameters can and do
vary in different applications. All operating parameters, including "Typicals' must be validated lor each customer application by customef. technical
experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim 01 personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part.
Motorola and
® are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
IBM is a registered trademark of International Business Machines Corporation. The PowerPC name, PowerPC logotype, Pow.rPC 601, PowerPC 602,
PowerPC 603, PowerPC 603e, and PowerPC 604 are trademarks 01 International Business Machines Corporation used by Motorola under license from
International Business Machines Corporation.
CHRP is a trademark of Apple Computer, Inc., International Business Machines Corporation, and Motorola, Inc. Power Macintosh is a trademark of
Apple Computer, Inc.
CONTENTS
Paragraph
Number
Title
Page
Number
About This Book
Audience .............................................................................................................. xxv
Organization ....................................................................................................... xxvi
Additional Reading ........................................................................................... xxvii
Conventions ..................................................................................................... xxviii
Acronyms and Abbreviations .......................................................................... xxviii
Chapter 1
Overview
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
MPCI06 PCIB/MC Features ............................................................................... 1-1
MPC106 Major Functional Units ......................................................................... 1-4
60x Processor Interface .................................................................................... 1-4
Secondary (L2) Cache/Multiple Processor Interface ....................................... 1-4
Memory Interface ............................................................................................ 1-5
PCI Interface .................................................................................................... 1-6
Power Management ............................................................................................. 1-6
Full-On Mode .................................................................................................. 1-6
Doze Mode ....................................................................................................... 1-6
Nap Mode ........................................................................................................ 1-7
Sleep Mode ...................................................................................................... 1-7
Suspend Mode .................................................................................................. 1-7
Chapter 2
Signal Descriptions
2.1
2.2
2.2.1
2.2.2
2.2.2.1
2.2.2.1.1
2.2.2.1.2
2.2.2.2
MOTOROLA
Signal Configuration ............................................................................................ 2-1
Signal Descriptions .............................................................................................. 2-3
Signal States at Reset ....................................................................................... 2-7
60x Processor Interface Signals ....................................................................... 2-8
Address Bus (A[0-31D ................................................................................ 2-8
Address Bus (A[O-31])-Output ............................................................. 2-9
Address Bus (A[0-31])-Input ............................................................... 2-9
Address Acknowledge (AACK) .................................................................. 2-9
Contents
iii
CONTENTS
Paragraph
Number
2.2.2.2.1
2.2.2.2.2
2.2.2.3
2.2.2.3.1
2.2.2.3.2
2.2.2.4
2.2.2.5
2.2.2.6
2.2.2.7
2.2.2.8
2.2.2.9
2.2.2.9.1
2.2.2.9.2
2.2.2.10
2.2.2.11
2.2.2.12
2.2.2.13
2.2.2.13.1
2.2.2.13.2
2.2.2.14
2.2.2.14.1
2.2.2.14.2
2.2.2.15
2.2.2.16
2.2.2.16.1
2.2.2.16.2
2.2.2.17
2.2.2.17.1
2.2.2.17.2
2.2.2.18
2.2.2.18.1
2.2.2.18.2
2.2.2.19
2.2.2.20
2.2.3
2.2.3.1
2.2.3.1.1
2.2.3.1.2
2.2.3.1.3
2.2.3.1.4
2.2.3.1.5
2.2.3.1.6
2.2.3.1.7
iv
Title
Page
Number
Address Acknowledge (AACK)-Output ............................................... 2-9
Address Acknowledge (AACK)-Input... ............................................. 2-10
Address Retry (ARTRY) ........................................................................... 2-10
Address Retry (ARTRY)-Output ........................................................ 2-10
Address Retry (ARTRY)-Input... ........................................................ 2-10
Bus Grant 0 (BGO)-Output.. .................................................................... 2-11
Bus Request 0 (BRO)-Input... .................................................................. 2-11
Caching-Inhibited (CI)-Input/Output ........ ;............................................. 2-12
Data Bus Grant 0 (DBGO)-Output .......................................................... 2-12
Data Bus Grant Local Bus Slave (DBGLB)-Output ............................... 2-12
Data Bus (DH[0-31], DL[0-31]) .............................................................. 2-13
Data Bus (DH[0-31], DL[0-31])-Output ........................................... 2-13
Data Bus (DH[0-31], DL[0-31])-Input .............................................. 2-14
Global (GBL)-Input/Output .................................................................... 2-14 .
Local Bus Slave Claim (LBCLAIM)-Input ............................................ 2-14
Machine Check (MCP)-Output ............................................................... 2-14
Transfer Acknowledge (TA) ...................................................................... 2-15
Transfer Acknowledge (TA)-Output .................................................. 2-15
Transfer Acknowledge (TA)-Input ..................................................... 2-15
Transfer Burst (TBST) ............................................................................... 2-16
Transfer Burst (TBST)-Output.. .......................................................... 2-16
Transfer Burst (TBST)-Input ...................... ;....................................... 2-16
Transfer Error Acknowledge (TEA)-Output... ........................................ 2-16
Transfer Start (TS) ..................................................................................... 2-17
Transfer Start (TS)-Output.. ................................................................ 2-17
Transfer Start (TS)-Input .................................................................... 2-17
Transfer Size (TSIZ[0-2]) ......................................................................... 2-17
Transfer Size (TSIZ[0-2])-Output ...................................................... 2-17
Transfer Size (TSIZ[0-2])-Input.. ....................................................... 2-18
Transfer Type (TT[O-4]) ........................................................................... 2-18
Transfer Type (TT[0-4])-Output ........................................................ 2-18
Transfer Type (TT[O-4])-Input. .......................................................... 2-18
Write-Through (WT)-Input/Output.. ....................................................... 2-18
Extended Address Transfer Start (XATS)-Input .................................... 2-19
L2 Cache/Multiple Processor Interface Signals ............................................. 2-19
Internal L2 Controller Signals ................................................................... 2-19
Address Strobe (ADS)-Output ............................................................ 2-20
Burst Address 0 (BAO)-Output ........................................................... 2-20
Burst Address 1 (BA1)-Output ........................................................... 2-20
Bus Address Advance (BAA)-Output.. ............................................... 2-20
Data Address Latch Enable (DALE)-Output.. .................................... 2-21
Data RAM Chip Select (DCS)-Output ............................................... 2-21
Dirty In (DIRTY_IN)-Input ................................................................ 2-21
MPC106 PCIB/MC User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
2.2.3.1.8
2.2.3.1.9
2.2.3.1.10
2.2.3.1.11
2.2.3.1.12
2.2.3.1.13
2.2.3.1.14
2.2.3.2
2.2.3.2.1
2.2.3.2.2
2.2.3.2.3
2.2.3.2.4
2.2.3.3
2.2.3.3.1
2.2.3.3.2
2.2.3.3.3
2.2.4
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
2.2.4.5
2.2.4.6
2.2.4.7
2.2.4.8
2.2.4.9
2.2.4.10
2.2.4.11
2.2.4.12
2.2.4.12.1
2.2.4.12.2
2.2.4.13
2.2.4.14
2.2.4.15
2.2.4.16
2.2.4.17
2.2.4.18
2.2.4.19
2.2.4.20
2.2.4.21
2.2.4.22
2.2.5
2.2.5.1
MOTOROLA
Title
Page
Number
Dirty Out (DIRTY_OUT)-Output... .................................................... 2-22
Data RAM Output Enable (DOE)-Output .......................................... 2-22
Data RAM Write Enable (DWE[0-2])-Output. .................................. 2-22
Hit (HIT)-Input ................................................................................... 2-22
Tag Output Enable (TOE)-Output ...................................................... 2-23
Tag Valid (TV)-Output ....................................................................... 2-23
Tag Write Enable (TWE)-Output ....................................................... 2-23
External L2 Controller Signals .................................................................. 2-24
External L2 Bus Grant (BGL2)-Output .............................................. 2-24
External L2 Bus Request (BRL2)-lnput ............................................. 2-24
External L2 Data Bus Grant (DBGL2)-Output... ................................ 2-24
Hit (HIT)-Input ................................................................................... 2-25
Multiple Processor Interface Signals ......................................................... 2-25
Bus Grant 1-3 (BG[1-3])-Output ....................................................... 2-25
Bus Request 1-3 (BR[1-3])-lnput ...................................................... 2-26
Data Bus Grant 1-3 (DBG[1-3])-Output.. .......................................... 2-26
Memory Interface Signals .............................................................................. 2-26
ROM Address 0 (ARO)-Output... ............................................................ 2-27
ROM Address 1-8 (AR[I-8])-Output .................................................... 2-27
ROM Address 9-20 (AR[9-20D-Output ................................................ 2-27
Buffer Control (BCTL[O-I ])-Output ...................................................... 2-27
Column Address Strobe (CAS[0-7])-Output... ....................................... 2-28
SDRAM Clock Enable (CKE)-Output. ................................................... 2-28
SDRAM Command Select (CS[0-7D~Output ........................................ 2-28
SDRAM Data Qualifier (DQM[0-7])-Output ........................................ 2-29
Flash Output Enable (FOE)-Output ........................................................ 2-29
Memory Address (MA[0-12])-Output. ................................................... 2-29
Memory Data Latch Enable (MDLE)-Output.. ....................................... 2-29
Data ParitylECC (PAR[0-7D .................................................................... 2-30
Data Parity (PAR[0-7D-Output .......................................................... 2-30
Data Parity (PAR[0-7D-Input ............................................................. 2-30
Parity Path Read Enable (PPEN)-Output... ............................................. 2-30
Row Address Strobe (RAS[0-7D-Output ............................................... 2-31
ROM Bank 0 Select (RCSO)-Output... .................................................... 2-31
ROM Bank 1 Select (RCS1)-Output... .................................................... 2-31
Real Time Clock (RTC)-Input ................................................................ 2-31
SDRAM Internal Bank Select (SDBAO)-Output .................................... 2-32
SDRAM Column Address Strobe (SDCAS)-Output .............................. 2-32
SDRAM Address (SDMA[I-II])-Output .............................................. 2-32
SDRAM Row Address Strobe (SDRAS)-Output ................................... 2-32
Write Enable (WE)-Output ..................................................................... 2-33
PCI Interface Signals ..................................................................................... 2-33
PCI AddressIData Bus (AD[31-O]) ........................................................... 2-33
Contents
v
CONTENTS
Paragraph
Number
2.2.5.1.1
2.2.5.1.2
2.2.5.2
2.2.5.2.1
2.2.5.2.2
2.2.5.3
2.2.5.3.1
2.2.5.3.2
2.2.5.4
2.2.5.4.1
2.2.5.4.2
2.2.5.5
2.2.5.6
2.2.5.6.1
2.2.5.6.2
2.2.5.7
2.2.5.8
2.2.5.8.1
2.2.5.8.2
2.2.5.9
2.2.5.9.1
2.2.5.9.2
2.2.5.10
2.2.5.11
2.2.5.11.1
2.2.5.11.2
2.2.5.12
2.2.5.12.1
2.2.5.12.2
2.2.5.13
2.2.5.13.1
2.2.5.13.2
2.2.5.14
2.2.5.14.1
2.2.5.14.2
2.2.5.14.3
2.2.5.l4.4
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
2.2.6.5
vi
Title
Page
Number
AddresslData (AD[31-O])-Output ...................................................... 2-33
AddresslData (AD[31-O])-Input ......................................................... 2-33
CommandlByte Enable (CIBE[3-O]) ......................................................... 2-33
CommandlByte Enable (CIBE[3-O])-Output ,.................................... 2-34
CommandlByte Enable (CIBE[3-O])-Input ........................................ 2-34
Device Select (DEVSEL) .......................................................................... 2-35
Device Select (DEVSEL)-Output ....................................................... 2-35
Device Select (DEVSEL)-Input .......................................................... 2-35
Frame (FRAME) ........................................................................................ 2-35
Frame (FRAME)-Output .................................................................... 2-35
Frame (FRAME)-Input ....................................................................... 2-35
PCI Bus Grant (GNT)-Input ................................................................... 2-35
Initiator Ready (IRDY) .............................................................................. 2-36
Initiator Ready (IRDY)-Output. .......................................................... 2-36
Initiator Ready (IRDY)-Input ............................................................. 2-36
Lock (LOCK)-Input ................................................................................ 2-36
Parity (PAR) .............................................................................................. 2-36
Parity (PAR)-Output ........................................................................... 2-37
Parity (PAR)-Input .............................................................................. 2-37
Parity Error (PERR) ........................................................... :....................... 2-37
Parity Error (PERR)-Output ............................................................... 2-37
Parity Error (PERR)-Input .................................................................. 2-37
PCI Bus Request (REQ)-Output ............................................................. 2-37
System Error (SERR) ................................................................................ 2-38
System Error (SERR)-Output ............................................................. 2-38
System Error (SERR)-Input ................................................................ 2-38
Stop (STOP) ............................................................................................... 2-38
Stop (STOP)-Output ........................................................................... 2-38
Stop (STOP)-Input .............................................................................. 2-38
Target Ready (TRDY) ............................................................................... 2-38
Target Ready (TRDY)-Output ............................................................ 2-38
Target Ready (TRDY)-Input. .............................................................. 2-39
PCI Sideband Signals ................................................................................ 2-39
Flush Request (FLSHREQ)-Input ....................................................... 2-39
ISA Master (ISA_MASTER)-Input .................................................... 2-39
Memory Acknowledge (MEMACK)-Output.. .................................... 2-40
Modified Memory Interrupt Request (PIRQ)-Output.. ....................... 2-40
Interrupt, Clock, and Power Management Signals ..................... ;.................. 2-40
Test Clock (CKO)-Output. ....................................................................... 2-40
Hard Reset (HRST)--Input ....................................................................... 2-40
Nonmaskable Interrupt (NMI)-Input ...................................................... 2-41
Quiesce Acknowledge (QACK)-Output ................................................. 2-41
Quiesce Request (QREQ)-Input .............................................................. 2-41
MPC106 PCIB/MC User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
2.2.6.6
2.2.6.7
2.2.7
2.2.7.1
2.2.7.2
2.2.7.3
2.2.7.4
2.2.7.5
2.2.8
2.2.8.1
2.2.8.2
2.2.8.3
2.2.8.4
2.3
Title
Page
Number
Suspend (SUSPEND)-Input .................................................................... 2-42
System Clock (SYSCLK)-Input.. ............................................................ 2-42
IEEE 1149.1 Interface Signals ....................................................................... 2-42
ITAG Test Clock (TCK)-Input ............................................................... 2-42
JTAG Test Data Output (TDO)-Output .................................................. 2-42
ITAG Test Data Input (TDI)-Input ......................................................... 2-43
ITAG Test Mode Select (TMS)-Input .................................................... 2-43
ITAG Test Reset (TRST)-Input .............................................................. 2-43
Configuration Signals .................................................................................... 2-43
Address Map (DBGO)-Input ................................................................... 2-43
ROM Bank 0 Data Path Width (FOE)-Input .......................................... 2-44
Clock Mode (PLL[0-3])-Input. ............................................................... 2-44
ROM Location (RCSO)-Input ................................................................. 2-44
Clocking ............................................................................................................. 2-44
Chapter 3
Device Programming
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.4
3.2.5
3.2.5.1
3.2.5.2
3.2.5.3
3.2.5.4
3.2.6
3.2.6.1
3.2.6.2
3.2.6.3
3.2.6.4
3.2.7
MOTOROLA
Address Maps ....................................................................................................... 3-1
Address Map A ................................................................................................ 3-1
Address Map B ................................................................................................ 3-7
Emulation Mode Address Map ...................................................................... 3-11
Configuration Registers ..................................................................................... 3-15
Configuration Register Access ...................................................................... 3-15
Configuration Register Access in Little-Endian Mode ............................. 3-15
Configuration Register Access in Big-Endian Mode ................................ 3-17
Configuration Register Summary .................................................................. 3-19
PCI Registers ................................................................................................. 3-22
PCI Command Register ............................................................................. 3-23
PCI Status Register .................................................................................... 3-24
Power Management Configuration Registers (PMCRs) ................................ 3-26
Error Handling Registers ............................................................................... 3-29
ECC Single-Bit Error Registers ................................................................. 3-29
Error Enabling Registers ............................................................................ 3-30
Error Detection Registers .......................................................................... 3-32
Error Status Registers ................................................................................ 3-34
Memory Interface Configuration Registers ................................................... 3-36
Memory Boundary Registers ..................................................................... 3-36
Memory Bank Enable Register .................................................................. 3-40
Memory Page Mode Register .................................................................... 3-41
Memory Control Configuration Registers ................................................. 3-42
Processor Interface Configuration Registers ................................................. 3-51
Contents
vii
CONTENTS
Paragraph
Number
3.2.8
3.2.9
3.2.9.1
3.2.10
Title
Page
Number
Alternate OS-Visible Parameters Registers ................................................... 3-63
Emulation Support Configuration Registers .................................................. 3-64
Modified Memory Status Register. ............................................................ 3-66
External Configuration Registers ................................................................... 3-67
Chapter 4
Processor Bus Interface
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.3
4.3.3.1
4.3.3.2
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.5.1
MPC 106 Processor Bus Configuration ................................................................ 4-1
Single-Processor System Configuration .......................................................... 4-1
Multiprocessor System Configuration ............................................................. 4-3
Multiprocessor System Configuration with External L2 Cache ...................... 4-4
Processor Bus Interface Configuration Registers ............................................ 4-5
Processor Bus Protocol Overview ....................................................................... 4-6
MPC 106 Arbitration ........................................................................................ 4-7
Address Pipelining and Split-Bus Transactions ............................................... 4-7
Address Tenure Operations .................................................................................. 4-8
Address Arbitration .......................................................................................... 4-8
Address Transfer Attribute Signals ................................................................ 4-10
Transfer Type Signal Encodings ............................................................... 4-10
TBST and TSIZ[0-2] Signals and Size of Transfer ................................. .4-13
Burst Ordering During Data Transfers ...................................................... 4-14
Effect of Alignment on Data Transfers ..................................................... 4-14
Address Transfer Termination ....................................................................... 4-16
MPC 106 Snoop Response ......................................................................... 4-17
Address Tenure Timing Configuration ...................................................... 4-18
Data Tenure Operations ..................................................................................... 4-18
Data B us Arbitration ...................................................................................... 4-18
Data B us Transfers and Normal Termination ................................................ 4-19
Data Tenure Timing Configurations .............................................................. 4-19
Data Bus Termination by TEA ...................................................................... 4-19
60x Local Bus Slave Support ......................................................................... 4-21
60x Local Bus Slave Timing ..................................................................... 4-21
Chapter 5
Secondary Cache Interface
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
viii
L2 Cache Configurations ..................................................................................... 5-2
Write-Back Cache Operation ........................................................................... 5-2
Write-Through Cache Operation ..................................................................... 5-2
Synchronous Burst SRAMs ............................................................................. 5-3
Pipelined Burst SRAMs ................................................................................... 5-4
Asynchronous SRAMs .................................................................................... 5-6
MPC106 PCIBIMC User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.4.2.4
5.4.2.4.1
5.4.2.4.2
5.4.2.4.3
5.4.2.4.4
5.5
5.5.1
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.1.5
5.5.1.6
5.5.1.7
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.6
5.6.1
5.6.2
MOTOROLA
Title
Page
Number
Two-Bank Support ........................................................................................... 5-7
Internal L2 Cache Controller Operation .............................................................. 5-9
L2 Cache Addressing ....................................................................................... 5-9
L2 Cache Line Status ..................................................................................... 5-10
L2 Cache Tag Lookup ................................................................................... 5-10
L2 Cache Cast-Out Operations ...................................................................... 5-11
L2 Cache Parity ............................................................................................. 5-11
L2 Cache Interface and Interrupt Vector Relocation ..................................... 5-12
L2 Cache Response to Bus Operations .............................................................. 5-12
Write-Back L2 Cache Response .................................................................... 5-12
Write-Through L2 Cache Response .............................................................. 5-20
L2 Cache Interface Parameters .......................................................................... 5-23
L2 Cache Interface Control Parameters ......................................................... 5-23
L2 Cache Interface Initialization Parameters ................................................. 5-24
CF_L2_illT_DELA Y ................................................................................ 5-25
CF_DOE ................................................................................... :................ 5-26
CF_ WDATA .............................................................................................. 5-26
CF_WMODE ............................................................................................. 5-27
Normal Write Timing without Partial Update (CF_WMODE =0) ....... 5-27
Normal Write Timing (CF_WMODE = 1) ............................................ 5-27
Delayed Write Timing (CF_WMODE = 2) ........................................... 5-28
Early Write Timing (CF_WMODE =3) ............................................... 5-29
L2 Cache Interface Timing Examples ............................................................... 5-30
Synchronous Burst SRAM L2 Cache Timing ............................................... 5-30
L2 Cache Read Hit Timing ........................................................................ 5-30
L2 Cache Write Hit Timing ....................................................................... 5-32
L2 Cache Line Update Timing .................................................................. 5-33
L2 Cache Line Cast-Out Timing ............................................................... 5-34
L2 Cache Hit Timing Following PCI Read Snoop .................................... 5-36
L2 Cache Line Push Timing Following PCI Write Snoop ........................ 5-37
L2 Cache Line Invalidate Timing Following PCI Write-with-Invalidate
Snoop ..................................................................................................... 5-38
Asynchronous SRAM L2 Cache Timing ....................................................... 5-39
Burst Read Timing ..................................................................................... 5-39
L2 Cache Burst Read Line Update Timing ............................................... 5-40
Burst Write Timing .................................................................................... 5-41
External L2 Cache Controller Operation ........................................................... 5-42
External L2 Cache Operation ........................................................................ 5-43
External L2 Cache Controller Interface Parameters ...................................... 5-43
Contents
ix
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 6
Memory Interface
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.3.1
6.3.2
6.3.3
6.3.3.1
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.8.1
6.3.9
6.3.9.1
6.3.10
6.3.10.1
6.3.10.2
6.3.10.2.1
6.3.10.2.2
6.3.11
6.3.12
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.7.1
6.4.8
6.4.8.1
6.4.9
6.4.9.1
6.4.9.2
x
Overview .............................................................................................................. 6-1
Memory Interface Signal Buffering ..................................................................... 6-2
Flow-Through Buffers ..................................................................................... 6-3
Transparent Latch Buffers ............................................................................... 6-3
Registered Buffers ........................................................................................... 6-4
ParitylECC Path Read Control ........................................................................ 6-5
DRAMIEDO Interface Operation ........................................................................ 6-6
Supported DRAMIEDO Organizations ........................................................... 6-7
DRAMIEDO Address Multiplexing ................................................................ 6-8
DRAMIEDO Power-On Initialization ............................................................. 6-9
Supported Memory Interface Configurations ............................................ 6-10
DRAMIEDO Interface Timing ...................................................................... 6-11
DRAMIEDO Burst W rap ............................................................................... 6-18
DRAMIEDO Latency .................................................................................... 6-18
DRAMIEDO Page Mode Retention .............................................................. 6-19
DRAMIEDO Parity and RMW Parity ........................................................... 6-20
RMW Parity Latency Considerations ........................................................ 6-20
ECC ................................................................................................................ 6-21
DRAMIEDO Interface Timing with ECC ................................................. 6-21
DRAMIEDO Refresh ..................................................................................... 6-25
DRAMIEDO Refresh Timing .................................................................... 6-25
DRAMIEDO Refresh and Power Saving Modes ....................................... 6-27
Self-Refresh in Sleep and Suspend Modes ............................................ 6-27
RTC Refresh in Suspend Mode ............................................................. 6-28
Processor-to-System-Memory Transaction Examples ................................... 6-28
PCI-to-System-Memory Transaction Examples ............................................ 6-32
SDRAM Interface Operation ............................................................................. 6-39
Supported SDRAM Organizations ................................................................ 6-41
SDRAM Address Multiplexing ..................................................................... 6-41
SDRAM Burst and Single-Beat Transactions ............................................... 6-42
SDRAM Page Mode Retention ...................................................................... 6-42
SDRAM Power-On Initialization .................................................................. 6-43
JEDEC Standard SDRAM Interface Commands ........................................... 6-44
SDRAM Interface Timing ............................................................................. 6-46
SDRAM Mode-Set Command Timing ...................................................... 6-51
SDRAM Parity and RMW Parity .................................................................. 6-52
RMW Parity Latency Considerations ........................................................ 6-53
SDRAM Refresh ............................................................................................ 6-53
SDRAM Refresh Timing ........................................................................... 6-54
SDRAM Refresh and Power Saving Modes .............................................. 6-54
MPC106 PCIB/MC User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.4.1
Title
Page
Number
ROMIFlash Interface Operation ........................................................................ 6-56
ROMlFlash Cacheability ............................................................................... 6-59
64-Bit ROMIFlash Interface Timing ............................................................. 6-59
8-Bit ROMIFlash Interface Timing ............................................................... 6-61
ROMlFlash Interface Write Operations ......................................................... 6-63
ROMIFlash Interface Write Timing .......................................................... 6-63
Chapter 7
PCI Bus Interface
7.1
7.1.1
7.1.2
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.3.4
7.3.5
7.3.6
7.4
7.4.1
7.4.2
7.4.3
7.4.3.1
7.4.3.2
7.4.4
7.4.5
7.4.5.1
7.4.5.2
7.4.6
7.4.6.1
7.4.6.2
7.5
7.5.1
7.5.2
7.5.3
7.5.4
MOTOROLA
PCI Interface Overview ....................................................................................... 7-1
The MPCI06 as a PCI Master ......................................................................... 7-2
The MPCI06 as a PCI Target .......................................................................... 7-2
PCI Bus Arbitration ............................................................................................. 7-3
PCI Bus ProtocoL ................................................................................................ 7-3
Basic Transfer Control ..................................................................................... 7-3
PCI Bus Commands ......................................................................................... 7-4
Addressing ..................................................................................................... ',' 7-6
Memory Space Addressing .......................................................................... 7-6
110 Space Addressing .................................................................................. 7-7
Configuration Space Addressing ................................................................. 7-7
Device Selection .............................................................................................. 7-7
Byte Alignment ................................................................................................ 7-8
Bus Driving and Turnaround ........................................................................... 7-8
PCI Bus Transactions ........................................................................................... 7-8
Read Transactions ............................................................................................ 7-9
Write Transactions ......................................................................................... 7-10
Transaction Termination ................................................................................ 7-11
Master-Initiated Termination ..................................................................... 7-11
Target-Initiated Termination ..................................................................... 7-12
Fast Back-to-Back Transactions .................................................................... 7-14
Configuration Cycles ..................................................................................... 7-15
The PCI Configuration Space Header ....................................................... 7-15
Accessing the PCI Configuration Space .................................................... 7-16
Other Bus Transactions .................................................................................. 7-21
Interrupt Acknowledge Transactions ......................................................... 7-21
Special-Cycle Transactions ....................................................................... 7-22
Exclusive Access ............................................................................................... 7-23
Starting an Exclusive Access ......................................................................... 7-23
Continuing an Exclusive Access .................................................................... 7-24
Completing an Exclusive Access ................................................................... 7-24
Attempting to Access a Locked Target... ....................................................... 7-24
Contents
xi
CONTENTS
Paragraph
Number
7.5.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.9
Title
Page
Number
Exclusive Access and the MPC106 ............................................................... 7-24
PCI Error Functions ...................................................................................... :.... 7-25
PCI Parity ....................................................................................................... 7-25
Error Reporting .............................................................................................. 7-26
MPC106-lmplemented PCI Sideband Signals ................................................... 7-26
ISA_MASTER ............................................................................................... 7-26
FLSHREQ and MEMACK ............................................................................ 7-27
Emulation Support ............................................................................................. 7-27
PCI Address Decoding ................................................................................... 7-27
Interrupt Vector Relocation ........................................................................... 7-28
Modified Memory Status Register ................................................................. 7-28
Curious Code Protection ................................................................................ 7-31
Processor-to-PCI Transaction Examples ........................................................... 7-31
Chapter 8
Internal Control
8.1
8.1.1
8.1.2
8.1.2.1
8.1.2.2
8.1.3
8.1.3.1
8.1.3.1.1
8.l.3.2
8.2
Internal Buffers .................................................................................................... 8-1
60x Processor/System Memory Buffers .......................................................... 8-2
60x ProcessorlPCl Buffers ............................................................................... 8-3
Processor-to-PCI-Read Buffer (PRPRB) ..................................................... 8-4
Processor-to-PCI-Write Buffers (PRPWBs) ................................................ 8-5
PCI/System Memory Buffers ........................................................................... 8-5
PCI-to-System-Memory-Read Buffer (PCMRB) ........................................ 8-7
Speculative PCI Reads from System Memory ........................................ 8-7
PCI-to-System-Memory-Write Buffers (PCMWBs) ................................... 8-8
Internal Arbitration .............................................................................................. 8-9
Chapter 9
Error Handling
9.l
9.2
9.2.1
9.2.2
9.2.2.l
9.2.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.3
9.3.l
xii
Priority of Externally-Generated Interrupts ......................................................... 9-2
Interrupt and Error Signals ................................................................................... 9-3
System Reset .................................................................................................... 9-3
60x Processor Bus Error Signals ..................................................................... 9-3
Machine Check (MCP) ................................................................................ 9-3
Transfer Error Acknowledge (TEA) ............................................................ 9-4
PCI Bus Error Signals ...................................................................................... 9-5
System Error (SERR) .................................................................................. 9-5
Parity Error (PERR) ..................................................................................... 9-5
Nonmaskable Interrupt (NMI) ..................................................................... 9-5
Error Reporting .................................................................................................... 9-6
60x Processor Interface .................................................................................... 9-6
MPC106 PCIB/MC User's Manual
MOTOROLA
CONTENTS
Paragraph
Number
9.3.1.1
9.3.1.2
9.3.1.3
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.3.2.4
9.3.2.5
9.3.3
9.3.3.1
9.3.3.2
9.3.3.3
9.3.3.4
9.3.3.5
9.4
9.5
Title
Page
Number
Unsupported 60x Bus Transaction Error ..................................................... 9-6
Illegal L2 Copy-Back Error ......................................................................... 9-6
Flash Write Error ......................................................................................... 9-6
Memory Interface ............................................................................................ 9-7
System Memory Read Data Parity Error ..................................................... 9-7
L2 Cache Read Data Parity Error ................................................................ 9-7
System Memory ECC Error......................................................................... 9-8
System Memory Select Error ........................................................................ 9-8
System Memory Refresh Overflow Error .................................................... 9-8
PCI Interface .................................................................................................... 9-8
Address Parity Error .................................................................................... 9-8
Data Parity Error .......................................................................................... 9-9
Master-Abort Transaction Termination ....................................................... 9-9
Received Target-Abort Error ..................................................................... 9-10
NMI (Nonmaskable Interrupt) ................................................................... 9-10
Interrupt Latencies ............................................................................................. 9-10
Example Signal Connections ............................................................................. 9-10
Appendix A
Power Management
A.l
A.l.l
A.l.2
A.l.3
A.l.4
A.l.5
A.l.6
A.2
A.2.l
A.2.2
A.2.3
A.2.4
A.2.5
A.2.6
A.2.7
MOTOROLA
MPCl06PowerModes ....................................................................................... A-l
MPCl06 Power Mode Transition ................................................................... A-I
Full-OnMode ................................................................................................. A-3
Doze Mode ...................................................................................................... A-3
Nap Mode ....................................................................................................... A-3
Sleep Mode ..................................................................................................... A-4
Suspend Mode ................................................................................................. A-5
MPC106 Power Management Support ............................................................... A-6
Power Management Configuration Registers ................................................. A-6
Clock Configuration ....................................................................................... A-6
PCI Address Bus Decoding ............................................................................ A-7
PCI Bus Special-Cycle Operations ................................................................. A-7
Processor Bus Request Monitoring ................................................................. A-7
Memory Refresh Operations in Sleep/Suspend Mode .................................... A-7
Device Drivers ................................................................................................ A-8
Contents
xiii
CONTENTS
Paragraph
Number
Title
Page
Number
Appendix B
Bit and Byte Ordering
B.l
B.2
Big-Endian Mode .................................................................................................B-2
Little-Endian Mode ..............................................................................................B-5
Appendix C
JTAGlTesting Support
C.l
C.l.l
C.1.2
C.1.2.1
C.1.2.2
C.1.2.3
C.1.3
ITAG Interface Description .................................................................................C-l
ITAG Signals ...................................................................................................C-2
ITAG Registers and Scan Chains .................................................................... C-2
Bypass Register ................................................................................................ C-2
Boundary-Scan Registers .................................................................................C-2
Instruction Register ..........................................................................................C-3
TAP Controller ................................................................................................ C-3
Appendix D
Initialization Example
Glossary of Terms and Abbreviations
Index
xiv
MPC106 PCIBIMC User's Manual
MOTOROLA
ILLUSTRATIONS
Figure
Number
1-1
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
Title
Page
Number
MPCI06 Block Diagram ............................................................................................... 1-2
MPCI06 Signal Groupings ........................................................................................... 2-2
SYSCLK Input with Internal Multiples ...................................................................... 2-45
Address Map A (Contiguous Map) ............................................................................... 3-4
Address Map A (Discontiguous Map) .......................................................................... 3-5
PCI Memory Map (Address Map A) ...................................................................•........ 3-6
PCI liD Map (Address Map A) ..................................................................................... 3-7
Address Map B ........................................................................................................... 3-10
Emulation Mode Address Map ................................................................................... 3-14
MPCI06 Configuration Space .................................................................................... 3-21
PCI Command Register .............................................................................................. 3-23
PCI Status Register ..................................................................................................... 3-25
Power Management Configuration Register 1 (PMCR1) ........................................... 3-26
Power Management Configuration Register 2 (PMCR2) ........................................... 3-28
ECC Single-Bit Error Counter Register-OxB8 ......................................................... 3-29
ECC Single-Bit Error Trigger Register-OxB9 .......................................................... 3-29
Error Enabling Register 1 (ErrEnRl) ......................................................................... 3-30
Error Enabling Register 2 (ErrEnR2) ......................................................................... 3-31
Error Detection Register 1 (ErrDRl)-OxCI ............................................................. 3-32
Error Detection register 2 (ErrDR2)-OxC5 ............................................................... 3-33
60x Bus Error Status Register-OxC3 ........................................................................ 3-34
PCI Bus Error Status Register-OxC7 ........................................................................ 3-35
60xIPCI Error Address Register-OxC8 ..................................................................... 3-35
Memory Starting Address Register l-Ox80 .............................................................. 3-36
Memory Starting Address Register 2-Ox84 .............................................................. 3-37
Extended Memory Starting Address Register l-Ox88 .............................................. 3-37
Extended Memory Starting Address Register 2-Ox8C ............................................. 3-37
Memory Ending Address Register l-Ox90 ............................................................... 3-38
Memory Ending Address Register 2-Ox94 ............................................................... 3-38
Extended Memory Ending Address Register l-Ox98 ............................................... 3-39
Extended Memory Ending Address Register 2-Ox9C .............................................. 3-39
Memory Bank Enable Register--OxAO ...................................................................... 3-40
Memory Page Mode Register-OxA3 ........................................................................ 3-41
Memory Control Configuration Register 1 (MCCRl)-OxFO ................................... 3-42
Memory Control Configuration Register 2 (MCCR2)-OxF4 ................................... 3-45
Memory Control Configuration Register 3 (MCCR3}-OxF8 ................................... 3-46
MOTOROLA
Illustrations
xv
ILLUSTRATIONS
Figure
Number
3-34
3-35
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
xvi
Title
Page
Number
Memory Control Configuration Register 4 (MCCR4)-OxFC ................................... 3-49
Processor Interface Configuration Register 1 (PICRl)-OxA8 .................................. 3-52
Processor Interface Configuration Register 2 (PICR2)-OxAC ................................. 3-57
Alternate OS-Visible Parameters Register l-OxBA ................................................. 3-63
Alternate OS-Visible Parameters Register 2-OxBB ................................................. 3-64
Emulation Support Configuration Register 1 (ESCRl)-OxEO ................................. 3-64
Emulation Support Configuration Register 2 (ESCR2)-OxE8 ................................. 3-66
Modified Memory Status Register-OxE4/0xEC ....................................................... 3-67
External Configuration Register I-Port Ox092 ......................................................... 3-68
External Configuration Register 2-Port Ox81 C ........................................................ 3-68
External Configuration Register 3-Port Ox850 ......................................................... 3-69
Single-Processor Configuration with Optional L2 Cache ............................................ 4-2
Multiprocessor Configuration ....................................................................................... 4-3
Multiprocessor Configuration with External L2 Cache ................................................ 4-4
Overlapping Tenures on the 60x Bus for a Single-Beat Transfer ................................. 4-6
Address Bus Arbitration with Dual Processors ............................................................ 4-9
Address Pipelining ...................................................................................................... 4-10
Snooped Address Transaction with ARTRY and L1 Cache Copy-Back .................... 4-17
Single-Beat and Burst Data Transfers ......................................................................... 4-19
Data Tenure Terminated by Assertion of TEA ........................................................... 4-20
Local Bus Slave Transaction ...................................................................................... 4-22
60x Bus State Diagram ............................................................................................... 4-23
Typical L2 Cache Using Burst SRAM (Write-Back) ................................................... 5-3
Typical L2 Cache Using Pipelined Burst SRAM (Write-Back, ADSC Only) ............. 5-4
Alternate L2 Cache Using Pipelined Burst SRAM (Write-Back Using ADSP) ........... 5-5
Typical L2 Cache Using Asynchronous SRAM (Write-Back) ..................................... 5-6
512-Kbyte, Two-Bank, L2 Cache Using Synchronous Burst SRAM
(Write-Back) .............................................................................................................. 5-8
I-Mbyte, Two-Bank, L2 Cache Using Pipelined Burst SRAM (Write-Back,
ADSC Only) .............................................................................................................. 5-9
HIT and DIRTY_IN Delay Configuration .................................................................. 5-26
External Byte Decode Logic Requiring CF_WMODE = 1 ........................................ 5-27
Normal Write Timing (CF_WMODE = Oor 1) .......................................................... 5-28
External Byte Decode Logic Requiring CF_WMODE = 2 ........................................ 5-28
Delayed Write Timing (CF_WMODE = 2) ................................................................ 5-29
External Byte Decode Logic Requiring CF_WMODE = 3 ........................................ 5-29
Early Write Timing (CF_WMODE = 3) ..................................................................... 5-30
Timing Diagram Legend ............................................................................................. 5-30
L2 Cache Read Hit Timing with CF_DOE = 0 ........................................................... 5-31
L2 Cache Read Hit Timing with CF_DOE = 1........................................................... 5-31
L2 Cache Write Hit Timing ........................................................................................ 5-32
L2 Cache Line Update Timing ................................................................................... 5-33
L2 Cache Line Cast-Out Timing ................................................................................. 5-34
MPC106 PCIBIMC User's Manual
MOTOROLA
ILLUSTRATIONS
Figure
Number
Title
Page
Number
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
L2 Cache Line Cast-Out Timing with No ARTRY ..................................................... 5-35
L2 Cache Hit Timing Following PCI Read Snoop ..................................................... 5-36
Modified L2 Cache Line Push Timing Following PCI Write Snoop ......................... 5-37
L2 Cache Line Invalidate Timing Following PCI Write-with-Invalidate Snoop ....... 5-38
L2 Cache Burst Read Timing with CF_DOE = 0 ....................................................... 5-39
L2 Cache Burst Read Timing with CF_DOE = 1 ....................................................... 5-40
L2 Cache Burst Read Line Update Timing with CF_WDATA =0 ........................... 5-40
L2 Cache Burst Read Line Update Timing with CF_WDATA = 1 ........................... 5-41
L2 Cache Burst Write Timing with CF_WDATA = 0 or 1 ........................................ 5-41
Typical External L2 Cache Configuration .................................................................. 5-42
Flow-Through Buffer .................................................................................................... 6-3
Transparent Latch-Type Buffer .................................................................................... 6-4
Registered Buffer .......................................................................................................... 6-5
16-Mbyte DRAM System with Parity .......................................................................... 6-7
DRAMIEDO Address Multiplexing-64-Bit Data Bus Mode ..................................... 6-9
DRAM Single-Beat Read Timing-No ECC ............................................................. 6-14
DRAM Burst Read Timing-No ECC ....................................................................... 6-15
EDO Burst Read Timing-No ECC ........................................................................... 6-16
DRAM Single-Beat Write Timing-No ECC ............................................................ 6-17
DRAMIEDO Burst Write Timing-No ECC, CPX = 1 ............................................. 6-18
DRAM Burst Read with ECC ..................................................................................... 6-23
EDO Burst Read Timing with ECC ............................................................................ 6-24
DRAM Single-Beat Write Timing with RMW or ECC Enabled ............................... 6-24
DRAMIEDO Bank Staggered CBR Refresh Timing .................................................. 6-26
DRAMIEDO Self-Refresh Timing in Sleep and Suspend Modes .............................. 6-28
Suspend Mode-Real Time Clock Refresh ................................................................ 6-28
Processor Burst Reads from Memory-60-ns DRAM with Flow-Through
Buffers ..................................................................................................................... 6-29
6-17 (Continued) Processor Burst Reads from Memory-60-ns DRAM with
Flow-Through Buffers ............................................................................................. 6-30
6-18
Processor Burst Write to Memory-60-ns DRAM with Flow-Through Buffers ....... 6-31
6-19
PCI Reads from Memory-Speculative Reads Enabled-60-ns DRAM with
Flow-Through Buffers ............................................................................................. 6-33
6-19 (Continued) PCI Reads from Memory-Speculative Reads Enabled-60-ns
DRAM with Flow-Through Buffers ........................................................................ 6-34
6-20
PCI Reads from Memory-Speculative Reads Disabled-60-ns DRAM with
Flow-Through Buffers ............................................................................................. 6-35
6-20 (Continued) PCI Reads from Memory-Speculative Reads Disabled-60-ns
DRAM with Flow-Through Buffers ........................................................................ 6-36
6-21
PCI Writes to Memory-60-ns DRAM with Flow-Through Buffers ........................ 6-37
6-21 (Continued) PCI Writes to Memory-60-ns DRAM with Flow-Through ........................ 6-38
6-22
128-Mbyte SDRAM System with Parity .................................................................... 6-40
6-23
SDRAM Address Multiplexing ................ ;................................................................. 6-41
MOTOROLA
Illustrations
xvii
ILLUSTRATIONS
Figure
Number
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
8-1
8-2
8-3
8-4
9-1
9-2
9-3
A-l
B-1
B-2
B-3
xviii
Title
Page
Number
PGMAX Parameter Setting for SDRAM Interface .................................................... 6-43
SDRAM Burst Read Timing ....................................................................................... 6-47
SDRAM Burst Write Timing ............................................................................... ,...... 6-48
SDRAM Burst Read Followed By Burst Write Timing ............................................. 6-49
SDRAM Single-Beat Read Timing ............................................................................ 6-50
SDRAM Single-Beat Write Timing ............................................................................ 6-51
SDRAM Mode-Set Command Timing ....................................................................... 6-52
SDRAM Bank-Staggered CBR Refresh Timing ........................................................ 6-54
SDRAM Self-Refresh Entry Timing .......................................................................... 6-55
SDRAM Self-Refresh Exit Timing ............................................................................. 6-56
16-Mbyte ROM System .............................................................................................. 6-57
I-Mbyte Flash System ................................................................................................ 6-58
64-Bit ROMIFlash Interface-Nonburst Read Timing .............................................. 6-60
64-Bit ROMIFlash Interface-Burst Read Timing ..................................................... 6-61
8-Bit ROMIFlash Interface-Single-Byte Read Timing ............................................ 6-62
8-Bit ROMIFlash Interface-HaIf-Word Read Timing .............................................. 6-62
8-Bit ROMIFlash Interface-Burst Read Timing ....................................................... 6-62
Flash Memory Write Timing ...................................................................................... 6-64
PCI Single-Beat Read Transaction ............................................................................... 7-9
PCI Burst Read Transaction ........................................................................................ 7-10
PCI Single-Beat Write Transaction ............................................................................ 7-10
PCI Burst Write Transaction ....................................................................................... 7-11
PCI Target-Initiated Terminations .............................................................................. 7-14
Standard PCI Configuration Header ........................................................................... 7-15
Layout of CONFIG_ADDR Register ......................................................................... 7-17
Type 0 Configuration Translation ............................................................................... 7-19
Direct-Access PCI Configuration Transaction ........................................................... 7-21
PCI Parity Operation ................................................................................................... 7-26
Modified Memory Tracking States ............................................................................. 7-29
Processor Burst Read to Device on PCI Bus .............................................................. 7-32
Processor Burst Write to Device on PCI Bus ............................................................. 7-33
Processor Read from PCI with Master-Abort ............................................................. 7-34
MPC106 Internal Buffer Organization ............................................................ :............ 8-2
60x Processor/System Memory Buffers ....................................................................... 8-2
60x ProcessorlPCl Buffers ............................................................................................ 8-3
PCI/System Memory Buffers ........................................................................................ 8-6
Internal Interrupt Management Block Diagram ............................................................ 9-2
Example Interrupt Signal Configuration-603-/604-Based System .......................... 9-11
Example Interrupt Signal Configuration-601-Based System ................................... 9-11
MPCI06PowerModes ................................................................................................ A-2
Four-Byte Transfer to PCI Memory Space-Big-Endian Mode ..................................B-3
Big-Endian Memory Image in System Memory ...........................................................B-4
Big-Endian Memory Image in Big-Endian PCI Memory Space ..................................B-5
MPC106 PCIBIMC User's Manual
MOTOROLA
ILLUSTRATIONS
Figure
Number
B-4
B-5
B-6
B-7
B-8
B-9
B-lO
B-11
C-1
Title
Page
Number
Munged Memory Image in System Memory ................................................................B-7
Little-Endian Memory Image in Little-Endian PCI Memory Space ............................B-8
One-Byte Transfer to PCI Memory Space-Little-Endian Mode ................................B-9
Two-Byte Transfer to PCI Memory Space-Little-Endian Mode .............................B-10
Four-Byte Transfer to PCI Memory Space-Little-Endian Mode .............................B-11
One-Byte Transfer to PCI 110 Space-Little-Endian Mode .......................................B-12
Two-Byte Transfer to PCI 110 Space-Little-Endian Mode ......................................B-13
Four-Byte Transfer to PCI 110 Space-Little-Endian Mode ......................................B-14
JTAG Interface Block Diagram ....................................................................................C-1
MOTOROLA
Illustrations
xix
ILLUSTRATIONS
Figure
Number
xx
Title
MPC106 PCIBIMC User's Manual
Page Number
MOTOROLA
TABLES
Table
Number
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
Title
Page
Number
Acronyms and Abbreviated Terms ........................................................................... xxviii
MPC 106 Signal Cross Reference ................................................................................. 2-3
Output Signal States during System Reset ................................................................... 2-8
Data Bus Byte Lane Assignments .............................................................................. 2-13
PCI Command Encodings ........................................................................................... 2-34
Address Map A-Processor View ................................................................................ 3-2
Address Map A-PCI Memory Master View .............................................................. 3-2
Address Map A-PC! I/O Master View ....................................................................... 3-3
Address Map B-Processor View ................................................................................ 3-8
Address Map B-PCI Memory Master View ............................................................... 3-8
Address Map B-PCI I/O Master View ....................................................................... 3-9
Emulation Mode Address Map-Processor View ...................................................... 3-11
Emulation Mode Address Map-PCI Memory Master View .................................... 3-12
Emulation Mode Address Map-PCI I/O Master View ............................................. 3-12
MPCI06 Configuration Registers ............................................................................... 3-19
PCI Configuration Space Header Summary ............................................................... 3-22
Bit Settings for PCI Command Register-Ox04 ......................................................... 3-23
Bit Settings for PCI Status Register-Ox06 ................................................................ 3-25
Bit Settings for Power Management Configuration Register l-Ox70 ...................... 3-26
Bit Settings for Power Management Configuration Register 2-Ox72 ...................... 3-28
Bit Settings for ECC Single-Bit Error Counter Register-OxB8 ............................... 3-29
Bit Settings for ECC Single-Bit Error Trigger Register-OxB9 ................................ 3-29
Bit Settings for Error Enabling Register 1 (ErrEnRl)-OxCO ................................... 3-30
Bit Settings for Error Enabling Register 2 (ErrEnR2)-OxC4 ................................... 3-31
Bit Settings for Error Detection Register 1 (ErrDR1)-OxCl .................................... 3-33
Bit Settings for Error Detection Register 2 (ErrDR2)-OxC5 .................................... 3-34
Bit Settings for 60x Bus Error Status Register-OxC3 ............................................... 3-35
Bit Settings for PCI Bus Error Status Register-OxC7 .............................................. 3-35
Bit Settings for 60xIPCI Error Address Register-OxC8 ........................................... 3-36
Bit Settings for Memory Starting Address Registers 1 and 2 ..................................... 3-37
Bit Settings for Extended Memory Starting Address Registers 1 and 2 ..................... 3-38
Bit Settings for Memory Ending Address Registers 1 and 2 ...................................... 3-39
Bit Settings for Extended Memory Ending Address Registers 1 and 2 ...................... 3-40
Bit Settings for Memory Bank Enable Register-OxAO ............................................ 3-41
Bit Settings for Memory Page Mode Register-OxA3 ............................................... 3-42
Bit Settings for MCCRI-OxFO ................................................................................. 3-43
Bit Settings for MCCR2-OxF4 ................................................................................. 3-45
Bit Settings for MCCR3-OxF8 ................................................................................. 3-47
MOTOROLA
Tables
xxi
TABLES
Table
Number
3-34
3.35
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
3-45
4-1
4-2
4-3
4-4
4-5
4-6
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
8-1
8-2
9-1
B-1
xxii
Title
Page
Number
Bit Settings for MCCR~xFC ................................................................................. 3-49
Bit Settings for PICRI--OxA8 ................................................................................... 3-52
ProcessorIL2 Configurations ....................................................................................... 3-56
Bit Settings for PICR2--OxAC ................................. ;....................................•............ 3-58
Bit Settings for Alternate OS-Visible Parameters Register l--OxBA ..•.................... 3-63
Bit Settings for Alternate OS-Visible Parameters Register 2--OxBB ........................ 3-64
Bit Settings for ESCRI--OxEO .... ~ ............................................................................. 3-65
Bit Settings for ESCR2--OxE8 ................................................................................... 3-66
Bit Settings for Modified Memory Status Register--OxE4/0xEC .............................. 3-67
Bit Settings for External Configuration Register I-Port Ox092 ............................... 3-68
Bit Settings for External Configuration Register 2-Port Ox81 C .............................. 3-69
Bit Settings for External Configuration Register 3-Port Ox850 ............................... 3-70
MPCI06 Responses to 60x Transfer Type Signals .................................................... 4-10
Transfer Type Encodings Generated by the MPCl 06 ................................................ 4-13
MPCI06 Transfer Size Encodings .............................................................................. 4-13
MPCI06 Burst Ordering ............................................................................................. 4-14
Aligned Data Transfers ................................................................................................ 4-14
Misaligned Data Transfers (4-Byte Examples) ......................................................... .4-16
60x to Tag and Data RAM Addressing for 4-Gbyte Cacheable Address Space ........ 5-10
Write-Back L2 Cache Response ................................................................................. 5-13
Write-Through L2 Cache Response ........................................................................... 5-20
Buffer Configurations ................................................................................................... 6-2
Supported Memory Device Configurations .................................................................. 6-8
Supported Memory Interface Configurations ............................................................. 6-11
Suggested DRAM Timing Configurations ................................................................. 6-12
DRAMIEDO Timing Parameters ...................... ~ ......................................................... 6-12
Estimated DRAM Latency .......................................................................................... 6-19
Estimated EDO Latency ............................................................................................. 6-19
Suggested DRAM Refresh Timing Configurations .................................................... 6-26
DRAMIEDO Power Saving Modes Refresh Configuration ....................................... 6-27
Memory Device Configurations Supported ................................................................ 6-41
SDRAM Command Encodings ................................................................................... 6-46
SDRAM Power Saving Modes Refresh Configuration .............................................. 6-55
PCI Bus Commands ....................................................................................................... 7-4
PCI Configuration Space Header Summary .... \.......................................................... 7-16
CONFlG_ADDR Register Fields ............................................................................... 7-18
Type 0 Configuration-Device Number to IDSEL Translation ................................. 7-19
Special-Cycle Message Encodings ............................................................................. 7-23
Snooping Behavior Caused by a Hit in an Internal Buffer ........................................... 8-6
Internal Arbitration Priorities ........................................................................................ 8-9
Externally-Generated Interrupt Priorities ..................................................................... 9-2
Byte Lane Translation in Big-Endian Mode .................................................................B-2
MPC106 PCIBIMC User's Manual
MOTOROLA
TABLES
Table
Number
B-2
B-3
B-4
Title
Page
Number
Processor Address Modification for Individual Aligned Scalars .................................B-5
MPCI06 Address Modification for Individual Aligned Scalars ..................................B-6
Byte Lane Translation in Little-Endian Mode ..............................................................B-6
MOTOROLA
Tables
xxiii
TABLES
Table
Number
xxiv
Title
Page
Number
MPC106 PCIBIMC User's Manual
MOTOROLA
About This Book
The primary objective of this user's manual is to describe the functionality of the MPC106
PCI bridge/memory controller (PCIBIMC) for use by systems designers and software
developers. The MPC106 is one device in a family of products that provides system-level
support for industry-standard interfaces to be used with PowerPCTM microprocessors.
In this document, the term '60x' is used to denote a 32-bit microprocessor from the
PowerPC architecture family that conforms to the bus interface of the PowerPC 601™,
PowerPC 603™, or PowerPC 604TM microprocessors. Note that this does not include the
PowerPC 602™ microprocessor which has a multiplexed address/data bus. 60x processors
implement the PowerPC architecture as it is specified for 32-bit addressing, which provides
32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and
floating-point data types of 32 and 64 bits (single-precision and double-precision).
It must be kept in mind that each PowerPC processor is a unique PowerPC implementation.
It is beyond the scope of the manual to provide a thorough description of the PowerPC
architecture; refer to PowerPC Microprocessor Family: The Programming Environments
for more information about the architecture. It is also beyond the scope of the manual to
provide a thorough description of the PCI local bus; refer to PCl Local Bus Specification
and PCl System Design Guide for more information about the PCI bus.
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/powerpc/.
Audience
This manual is intended for system software and hardware developers who want to develop
products incorporating PowerPC microprocessors and the PCI bus. It is assumed that the
reader understands operating systems, microprocessor system design, and the basic
principles of reduced instruction set computing (RISC) processing.
MOTOROLA
AboutThls Book
xxv
·Organization
Following is a summary and a brief description of the major sections of this manual:
•
Chapter 1, "Overview," is useful for readers who want a general understanding of
the features and functions of the MPC106.
•
Chapter 2, "Signal Descriptions," provides descriptions of individual signals of the
MPC106.
•
Chapter 3, "Device Programming," is useful for software engineers who need to
understand the address space and functionality of the registers implemented in the
MPC106.
•
Chapter 4, "Processor Bus Interface," describes the interaction between the
MPC106 and the 60x processor or multiple 60x processors.
•
Chapter 5, "Secondary Cache Interface," describes the operation of the secondary or
level 2 (L2) cache interface.
•
Chapter 6, "Memory Interface," provides details for interfacing the MPC 106 to
DRAM, EDO, SDRAM, ROM, and Flash ROM devices.
•
Chapter 7, "PCI Bus Interface,"describes the MPC106 as a bridge from the 60x
processor bus to the PCI bus and the MPC 106 as a PCI agent.
•
Chapter 8, "Internal Control," describes the internal buffers between the interfaces
of the MPC 106.
•
Chapter 9, "Error Handling," describes how the MPC106 handles error detection
and reporting on the three primary interfaces-processor interface, memory
interface, and PCI interface.
•
Appendix A, "Power Management,"provides information about power saving
modes for the MPC 106.
•
Appendix B, "Bit and Byte Ordering," describes big- and little-endian byte ordering
arid the implications on systems using the MPC 106.
•
Appendix C, "ITAGrresting Support," describes the IEEE 1149.1 functiQns used for
facilitating board testing and chip debug.
•. Appendix D, "Initialization Example," provides sample initialization code in
PowerPC assembly language.
•
This manual also includes a glossary and an index.
In this document, the terms '601', '603', and '604' are used as abbreviations for 'PowerPC
601 microprocessor', 'PowerPC 603 microprocessor', and 'PowerPC 604 microprocessor',
respectively.
xxvi
MPC106 PCIBIMC User's Manual
MOTOROLA
Additional Reading
This section provides a brief list of additional reading that supplements the information in
this manual.
The following materials are available from the Motorola Literature Distribution Centers
listed on the back cover of this manual; the document order numbers are included in
parentheses for ease in ordering:
•
MPCI06 PCI Bridge/Memory Controller Technical Summary, Rev 1 (MPC1061D)
•
PowerPC 601 RISC Microprocessor User's Manual, Rev 1 (MPC601 UMlAD)
•
PowerPC 603e RISC Microprocessor User's Manual with Supplementfor PowerPC
603 Microprocessor (MPC603EUMlAD)
•
Addendum to PowerPC 603e RISC Microprocessor User's Manual: PowerPC 603e
Microprocessor Supplement and User's Manual Errata (MPC603EUMAD/AD)
•
PowerPC 604 RISC Microprocessor User's Manual (MPC604UM1AD)
•
Addendum to PowerPC 604 RISC Microprocessor User's Manual: PowerPC 604e
Microprocessor Supplement and User's Manual Errata (MPC604UMAD/AD)
•
PowerPC Microprocessor Family: The Programming Environments
(MPCFPElAD)
•
PowerPC Microprocessor Family: The Programming Environmentsfor 32-Bit
Microprocessors (MPCFPE32B/AD)
The following books are available from the PCI Special Interest Group, P.O. Box 14070,
Portland, OR 97214; Tel. (800) 433-5177 (U.S.A.), (503) 797-4207 (International).
•
•
PCI Local Bus Specification, Rev 2.1
PCI System Design Guide, Rev 1.0
The following books are available from the Morgan-Kaufmann Publishers, 340 Pine Street,
Sixth Floor, San Francisco, CA 94104; Tel. (800) 745-7323 (U.S.A.), (415) 392-2665
(International).
•
PowerPC Microprocessor Common Hardware Reference Platform: A System
Architecture, by Apple Computer, Inc., International Business Machines, Inc., and
Motorola, Inc.
•
Macintosh Technology in the Common Hardware Reference Platform, by Apple
Computer, Inc.
•
PowerPC Architecture: A Specification for a New Family of RISC Processors, by
International Business Machines, Inc.
•
Computer Architecture: A Quantitative Approach, Second Edition, by John L.
Hennessy and David A. Patterson
MOTOROLA
AboutThis Book
xxvii
Conventions
This document uses the following notational conventions:
Names for signals that are active high are shown in uppercase text
without an overbar. Active-high signals are referred to as asserted
when they are high and negated when they are low.
A bar over a signal name indicates that the signal is active low.
Active-low signals are referred to as asserted (active) when they are
low and negated when they are high.
Hexadecimal numbers
Binary numbers
Abbreviations or acronyms for registers are shown in uppercase text.
.
Specific bit fields or ranges are shown in brackets.
OxOF
ObOOll
REG [FIELD]
In certain contexts, such as a signal encoding, this indicates a don't
care. For example, ifIT[0-3] are binary encoded ObnOOl, the state
of ITO is a don't care.
n
Acronyms and Abbreviations
Table i contains acronyms and abbreviations that are used in this document.
Table i. Acronyms and Abbreviated Terms
Meaning
Term
xxViii
BGA
Ball grid array package
BIST
Built-in self test
BIU
Bus interface unit
CAS
Column address strobe
CBR
CAS before RAS
DIMM
Dual in-line memory module
DRAM
Dynamic random access memory
ECC
Error checkhig and correction
EDO
Extended data out DRAM
ErrOR
Error detection register
ErrEnR
Error enabling register
ESCR
Emulation support configuration register
IEEE
Institute of Electrical and Electronics Engineers
IntAck
Interrupt acknowledge
ISA
Industry standard architecture
MPC106 PCIBIMC User's Manual
MOTOROLA
Table I. Acronyms and Abbreviated Terms (Continued)
Term
Meaning
JTAG
Joint test action group interface
L2
Secondary cache
MICR
Memory interface configuration register
MCCR
Memory control configuration register
Mux
Multiplex
PCI
Peripheral component interconnect
PCIBIMC
PCI bridge/memory controller
PICR
Processor interface configuration register
PLL
Phase-locked loop
PMC
Power management controller
PMCR
Power management configuration register
RAS
Row address strobe
ROM
Read-only memory
RTC
Real-time clock
SDRAM
Synchronous dynamic random access memory
SIMM
Single in-line memory module
VCO
Voltage-controlled oscillator
MOTOROLA
AboutThis Book
xxix
Chapter 1
Overview
The MPC 106 provides a PowerPCTM microprocessor common hardware reference platform
(CHRPTM) compliant bridge between the PowerPC microprocessor family and the
Peripheral Component Interconnect (PCI) bus. CHRP is a set of specifications that defines
a unified personal computer architecture and brings the combined advantages of the Power
Macintosh™ platform and the standard PC environment to both system vendors and users.
PCI support allows system designers to rapidly design systems using peripherals already
designed for PCI and the other standard interfaces available in the personal computer
hardware environment. These open specifications make it easier for system vendors to
design computers capable of running multiple operating systems. The MPCI06 integrates
secondary cache control and a high-performance memory controller. The MPCI06 uses an
advanced, 3.3-V CMOS process technology and is fully compatible with TIL devices.
This ~ocument describes the MPCI06, its interfaces, and its signals.
1.1 MPC106 PCIB/MC Features
The MPCI06 provides an integrated high-bandwidth, high-performance, TIL-compatible
interface between a 60x processor, a secondary (L2) cache or additional (up to four total)
60x processors, the PCI bus, and main memory. This section summarizes the features of the
MPCI06.
Figure 1-1 shows the major functional units within the MPCI06. Note that this is a
conceptual block diagram intended to show the basic features rather than an attempt to
show how these features are physically implemented on the device.
MOTOROLA
Chapter 1. Overview
1-1
L2 Cache
Interface
Memory
Memory
60x Processor
Interface
Interface
L2
60xBus
Configuration
Registers
PCI Bus
Figure 1-1. MPC106 Block Diagram
Major features of the MPC 106 are as follows:
•
•
1-2
60x processor interface
-
Supports up to four 60x processors
-
Supports various operating frequencies and bus divider ratios
-
32-bit address bus, 64-bit data bus
-
Supports full memory coherency
-
Supports optional 60x local bus slave
-
Decoupled address and data buses for pipelining of 60x accesses
-
Store gathering on 60x-to-PCI writes
Secondary (L2) cache control
-
Configurable for write-through or write-back operation
-
Supports cache sizes of 256 Kbytes, 512 Kbytes, and 1 Mbyte
-
Up to 4 Gbytes of cacheable space
-
Direct-mapped
-
Supports byte parity
.-
Supports partial update with external byte decode for write enables
-
Programmable interface timing
MPC106 PCIB/MC User's Manual
MOTOROLA
•
•
-
Supports pipelined burst, synchronous burst, or asynchronous SRAMs
-
Alternately supports an external L2 cache controller or integrated L2 cache
module
Memory interface
-
1 Gbyte of RAM space, 16 Mbytes of ROM space
-
High-bandwidth, 64-bit data bus (72 bits including parity or ECC)
-
Supports fast page mode DRAMs, extended data out (EDO) DRAMs, or
synchronous DRAMs (SDRAMs)
-
Supports 1 to 8 banks ofDRAMlEDO/SDRAM with sizes ranging from 2 Mbyte
to 128 Mbytes per bank
-
Supports page mode SDRAMs-2 open pages simultaneously
-
DRAMIEDO configurations support parity or error checking and correction
(ECC); SDRAM configurations support parity
-
ROM space may be split between the PCI bus and the 6Oxlmemory bus
(8 Mbytes each)
-
Supports 8-bit asynchronous ROM or 64-bit burst-mode ROM
-
Supports writing to Flash ROM
-
Configurable external buffer controllogic
-
Pro~ammable
interface timing
PCI interface
-
Compliant with PCl Local Bus Specification, Revision 2.1
-
Supports PCI interlocked accesses to memory using LOCK signal and protocol
-
Supports accesses to all PCI address spaces
-
Selectable big- or little-endian operation
-
Store gathering on PCI writes to memory
-
Selectable memory prefetching of PCI read accesses
-
Only one external load presented by the MPC 106 to the PCI bus
-
Interface operates at 20-33 MHz
-
Word parity supported
-
3.3 V/5.0 V-compatible
•
Concurrent transactions on 60x and PCI buses supported
•
Power management
-
Fully-static 3.3-V CMOS design
-
Supports 60x nap, doze, and sleep power management modes, and suspend mode
MOTOROLA
Chapter 1. Overview
1-3
•
IEEE 1149.1-compliant, JTAG boundary-scan interface
•
304-pin ball grid array (BGA) package
1.2 MPC106 Major Functional Units
The MPC 106 consists of the following major functional units:
•
•
•
•
60x processor interface
Secondary (L2) cache/multiple processor interface
Memory interface
PCI interface
This section describes each of these functional units.
1.2.1 60x Processor Interface
The MPC 106 supports a programmable interface to a variety of PowerPC microprocessors
operating at select bus speeds. The 60x address bus is 32 bits wide and the data bus is 64
bits wide. The 60x processor interface of the MPC 106 uses a subset of the 60x bus protocol,
supporting single-beat and burst data transfers. The address and data buses are decoupled
to support pipelined transactions.
Two signals on the MPC106, LBCLAIM (local bus slave claim) and DBGLB (data bus
grant local bus slave), are provided for an optional local bus slave. However, the local bus
slave must be capable of generating the TA (transfer acknowledge) signal to interact with
the 60x processor(s).
Depending on the system implementation, the processor bus may operate at the PCI bus
clock rate, or at two or three times the PCI bus clock rate. The 60x processor bus is
synchronous, with all timing relative to the rising edge of the 60x bus clock.
1.2.2 Secondary (L2) Cache/Multiple Processor Interface
The MPC106 provides support for the following configurations of 60x processors and L2
cache:
•
Up to four 60x processors with no L2 cache
•
A single 60x processor plus a direct-mapped, lookaside, L2 cache using the internal
L2 cache controller of the MPC 106
•
Up to four 60x processors plus an externally controlled L2 cache (such as the
Motorola MPC2604GA integrated L2100kaside cache)
The internal L2 cache controller generates the arbitration and support signals necessary to
maintain a write-through or write-back L2 cache. The internal L2 cache controller supports
either asynchronous SRAMs, pipelined burst SRAMs, or synchronous burst SRAMs, using
byte parity for data error detection.
1-4
MPC106 PCIB/MC User's Manual
MOTOROLA
When more than one 60x processor is used, nine signals of the L2 interface change their
functions (to BR[1-3], BG[1-3], and DBG[1-3]) to allow for arbitration between the 60x
processors. The 60x processors share all 60x interface signals of the MPC106, except the
bus request, bus grant, and data bus grant signals.
When an external L2 controller (or integrated L2 cache module) is used, three signals of the
L2 interface change their functions (to BRL2, BGL2, and DBGL2) to allow the MPC106
to arbitrate between the external cache and the 60x processor(s).
1.2.3 Memory Interface
The memory interface controls processor and PCI interactions to main memory and is
capable of supporting a variety of DRAM, extended data-out (EDO) DRAM, or
synchronous DRAM (SDRAM) and ROM or Flash ROM configurations as main memory.
The maximum supported memory size is 1 Gbyte of DRAMIEDO/SDRAM, with 16
Mbytes of ROMIFlash. The MPCI06 configures its memory controller to support the
various memory sizes through software initialization of on-chip configuration registers.
Parity (DRAMIEDO/SDRAM) or ECC (DRAMIEDO-only) is provided for error
detection.
The MPC 106 controls the 64-bit data path to main memory (72 bits with parity or ECC).
To reduce loading on the data bus, system designers may need to add buffers between the
60x bus and memory. The MPC106 features configurable data/parity buffer control logic to
accommodate several buffer types.
The MPC106 supports a variety of DRAMIEDO/SDRAM configurations. DRAMIEDO/
SDRAM banks can be built using dual in-line memory modules (DIMMs), single in-line
memory modules (SIMMs), or directly-attached memory devices. Thirteen multiplexed
address signals provide for device densities up to 16 M. Eight row address strobe/command
select (RAS/CS[0-7]) signals support up to eight banks of memory. The MPC106 supports
bank sizes from 2 Mbytes to 128 Mbytes. Eight column address strobe/data qualifier (CASI
DQM[0-7]) signals are used to provide byte selection for memory bank accesses.
The MPC106 supports parity checking and generation in two forms-normal parity and
read-modify-write (RMW) parity. As an alternative to simple parity, the MPC106 supports
error checking and correction (ECC) for DRAMIEDO configurations. Using ECC, the
MPC 106 detects and corrects all single-bit errors and detects all double-bit errors and all
errors within a nibble.
For ROMIFlash support, the MPC106 provides 20 address bits (21 address bits for the 8-bit
wide ROM interface), two bank selects, one output enable, and one Flash write enable. The
16-Mbyte system ROM space is subdivided into two 8"Mbyte banks. Bank 0 (selected by
RCSO) is addressed from OxFF80_0000 to OxFFFF_FFFF. Bank 1 (sel~ted by RCS1) is
addressed from OxFFOO_OOOO to OxFF7F_FFFF. A configuration signal (FOE) sampled at
reset, determines the bus width of the ROM or Flash device (8-bit or 64-bit) in bank O. The
data bus width for ROM bank 1 is always 64 bits. For systems using the 8-bit interface to
MOTOROLA
Chapter 1. Overview
1-5
bank 0, the ROMIFlash device must be connected to the most-significant byte lane of the
data bus (DH[0-7]).
The MPCI06 also supports a mixed ROM system configuration. That is, the system can
have the upperS Mbytes (bank 0) of ROM space located on the PCI bus and the lower
8 Mbytes (bank 1) of ROM space located on the 6Oxlmemory bus.
1.2.4 PCI Interface
The MPCI06's PCI interface complies with the PCI Local Bus Specification, Revision 2.1,
and follows the guidelines in the PCI System Design Guide, Revision 1.0 for host bridge
architecture. The PCI interface connects the processor and memory buses to the PCI·bus,
to which 110 components are connected. The PCI bus uses a 32..bit multiplexed address/
data bus, plus various control and error signals.
The PCI interface of the MPC 106 functions as both a master and target device. As a master,
the MPCI06 supports read and write operations to the PCI memory space, the PCI 110
space, and the PCI configuration space. The MPCI06 also supports PCI special-cycle and
interrupt-acknowledge commands. As a target, the MPC106 supports read and write
operations to system memory. Mode selectable big-endian to little-endian conversion is
supplied at the PCI interface.
Buffers are provided for 110 operations between the PCI bus and the 60x processor or
memory. Processor read and write operations each have a 32~byte buffer, and memory
operations have one 32-byte read buffer and two 32-byte write buffers.
1.3 Power Management
The MPC 106 provides hardware support for four levels of power reduction; the doze, nap,
and sleep modes are invoked by register programming, and the suspend mode is invoked by
assertion of an external signal. The design of the MPC 106 is fully static, allowing internal
logic states to be preserved during all power saving modes. The following sections describe
the programmable power modes provided by the MPC 106.
1.3.1 Full-On Mode
This is the default power state of the MPC 106 following a hard reset, with all internal
functional units fully powered and operating at full clock speed.
1.3.2 Doze Mode
In this power saving mode, all the MPC 106 functional units are disabled except for PCI
address decoding, system RAM refreshing, and 60x bus request monitoring (through BRx).
Once the doze mode is entered, a hard reset, a PCI transaction referenced to system
memory, or a 60x bus request can bring the MPC 106 out of the doze mode and into the fullon state. If the MPCI06 is awakened for a processor or PCI bus access, the access is
completed and the MPCI06 returns to the doze mode. The MPC106's doze mode is totally
independent of the power saving mode of the processor.
1-6
MPC106 PCIBIMC User's Manual
MOTOROLA
1.3.3 Nap Mode
Nap mode provides further power savings compared to doze mode. The greater power
savings can be achieved by placing both the processor and the MPC 106 in a power
reduction mode. In this mode, only the PCI address decoding, system RAM refresh, and the
processor bus request monitoring are still operating. A hard reset, a PCI bus transaction
referenced to system memory, or a 60x bus request can bring the MPC106 out of the nap
mode. If the MPC 106 is awakened by a PCI access, the access is completed, and the
MPC 106 returns to the nap mode. If the MPC 106 is awakened by a processor access, the
access is completed, but the MPC106 remains in the full-on state. When in the nap mode,
the PLL is required to be running and locked to the system clock (SYSCLK).
1.3.4 Sleep Mode
Sleep mode provides further power savings compared to the nap mode. As in nap mode,
both the processor and the MPC106 are placed in a reduced power mode concurrently. In
sleep mode, no functional units are operating except the system RAM refresh logic, which
can continue (optionally) to perform the refresh cycles. A hard reset or a bus request wakes
the MPC106 from the sleep mode. The PLL and SYSCLK inputs may be disabled by an
external power management controller (PMC). For additional power savings, the PLL can
be disabled by configuring the PLL[O-3] signals into the PLL-bypass mode. The external
PMC must enable the PLL, turn on SYSCLK, and allow the PLL time to lock before
waking the system from sleep mode.
1.3.5 Suspend Mode
Suspend mode is activated by asserting the SUSPEND signal. In suspend mode, the
MPC 106 may have its clock input and PLL shut down for additional power savings.
Memory refresh can be accomplished in two ways--either by using self-refresh mode
DRAMs or by using the RTC input. To exit the suspend mode, the system clock must be
turned on in sufficient time to restart the PLL. After this time, SUSPEND may be negated.
In suspend mode, all outputs (except memory refresh) are released to a high-impedance
state and all inputs (including HRST) are ignored.
MOTOROLA
Chapter 1. Overview
1-7
Chapter 2
Signal Descriptions
This chapter provides descriptions of the MPC106's external signals. It describes each
signal's behavior when the signal is asserted and negated and when the signal is an input or
an output.
NOTE
A bar over a signal name indicates that the signal is active
low-for example, ARTRY (address retry) and TS (transfer
start). Active-low signals are referred to as asserted (active)
when they are low and negated when they are high. Signals that
are not active low, such as TV (tag valid) and NMI
(nonmaskable interrupt), are referred to as asserted when they
are high and negated when they are low.
For multiple function signals, outlined signal names refer to the
alternate function(s) of the signal being described. For
example, the L2 controller signal TOE (tag output enable) has
the alternate function DBG1 (data bus grant 1) when the
MPC 106 is configured for a second 60x processor.
2.1 Signal Configuration
The MPC106's signals are grouped as follows:
•
•
•
•
•
•
•
60x processor interface signals
L2 cache/multiple processor interface signals
Memory interface signals
PCI interface signals
Interrupt, clock, and power management signals
IEEE 1149.1 interface signals
Configuration signals
Figure 2-1 illustrates the signals of the MPC 106, showing how the signals are grouped. A
pinout diagram showing actual pin numbers is included in the MPC106 hardware
specifications.
MOTOROLA
Chapter 2. Signal Descriptions
2-1
r-_ ADl31-Ql
-
1
TROY
1
1 .. XATS
1
1
1
FRAME
"STOP
LOCK
DEVSE[
1
1
2
SERR PERR
REO
GNT
F[SRREO
MEMACi(
ISA MASTER
PIRO/SDRAS
'-~
r-
1 .. i3FiO
4
BGO
1 .. 1'8
rnrw
PCI
Interface
32
PAR
C/BEI3-Ql
1
1
1
1
1
1
Memory
Interface
8
8
WE:
1
MAO/ARO
1
MA[1-12VAR[9-20]
12
PARIQ-7VARI1-81
8
FeEt
1
MDLEISDCAS PPEN 2
RCST
1
RCS(jt
1
BCT[O BCT[f
2
RTC
1
'-
r-
Interrupt, Clock,
and Power
Management
Signals
32
5
3
1
3
1
.. A[Q-31]
.. TT[D-4]
.. TSIZ[Q-2]
.. TBST
.. WT, CT, GB[
.. AACK
1 .. ARTRY
DBGot
1
64 .. DH[Q-31], DL[Q-31]
1 .. TA
LBCLAIM
1
DBGLB/CKE
1
fV{CP;
TEA
2
..
~
~
~
~
60x
Processor
Interface
~
~
~
~
~
~
~
~
RAS[O-7J/CS[Q-7]
"CASIO-71/DQMIO-71
..
1
SYSCLK CKOt
HR"ST
2
1
NMI
1
QREQ
1
OACR
1
SUSPEf\lD
1
1
ADS/DALElBRL2
1
BAA/BA 1/BGL2
DOE/DBGL2
1
3
DWE[O-2j/DBG2 DBG3.C.Ko
1
HIT
1
1
1
1
OCStIm3
1
1
1
L2 Cachel
Multiple
Processor
Interface
BAO/BR3
TWElBG2
TV!BR2
DIRTY' 1f\l/BRl
DIRTY_OUT/BG1
~
1
1
TOO
1
1
1
TCK
TDI
TMS
]
IEEE 1149.1
JTAG
Interface
TRST
'-
Configuration
~
OBGOt
mEt
RCSOt
PLL[Q-31
1
1
1
4
t Some signals have duaI functions and are
shown more than once in this figure.
Figure 2-1. MPC106 Signal Groupings
2-2
MPC106 PCIBIMC User's Manual
MOTOROLA
2.2 Signal Descriptions
This section describes individual MPC106 signals, grouped according to Figure 2-1. The
following sections a.re intended to provide a quick summary of signal functions. Table 2-1
provides an alphabetical cross-reference to the signals of the MPC106. It details the signal
name, interface, alternate functions, number of signals, whether the signal is an input,
output, or bidirectional, and finally a pointer to the section in this chapter where the signal
is described.
Table 2-1. MPC106 Signal Cross Reference
Signal
Signal Name
Alternate
Function(s)
Interface
Number
of Pins
110
Section #
.32
1/0
2.2.2.1
60x processor
-
1
1/0
2.2.2.2
Address/data
PCI
-
32
1/0
2.2.5.1
AD'S
Address strobe
Internal L2
controller
KJA8.E
18R8.2
1
0
2.2.3.1.1
ARO
ROM address 0
Memory
MAti
1
0
2.2.4.1
8
0
2.2.4.2
12
0
2.2.4.3
A[0--31]
Address bus
60x processor
AACK
Address
acknowledge
AD[31-Q]
AR[1-8]
ROM address 1-8
Memory
PAR[()-'1]
AR[9-20]
ROM address 9-20
Memory
MA[1-72]
SD18A(),
SDMA{7-11]
ARTRY
Address retry
60x processor
-
1
1/0
2.2.2.3
BAO
Burst address 0
Internal L2
controller
H'JR3
1
0
2.2.3.1.2
BA1
Burst address 1
Internal L2
controller
BAA
BG8.2
1
0
2.2.3.1.3
'BAA
Bus address
advance
Internal L2
controller
~A1
1
0
2.2.3.1.4
BG8.2
-
2
0
2.2.4.4
1
0
2.2.2.4
BCTL[0-1]
Buffer control 0-1
Memory
BGO
Bus grant 0
60x processor
BG1
Bus grant 1
Multiple
Processor
DffRT'l3}UT
1
0
2.2.3.3.1
~
Bl,!s grant 2
Multiple
Processor
TW/e
1
0
2.2.3.3.1
~
Bus grant 3
Multiple
Processor
DCS
1
0
2.2.3.3.1
BGL2
External L2 bus
grant
External L2
controller
~A1
1
0
2.2.3.2.1
'Ii».
Bus request 0
60x processor
-
1
I
2.2.2.5
BRO
MOTOROLA
Chapter 2. Signal Descriptions
2-3
Table 2-1. MPC106 Signal Cross Reference (Continued)
Signal
Signal Name
Alternate
Functlon(a)
Interface
Number
110
of Pine
Section #
BFff
Bus request 1
Multiple
Processor
bmTY_1N
1
I
2.2.3.3.2
BF!2
Bus request 2
Multiple
Processor
TV
1
I
2.2.3.3.2
1m3
Bus request 3
Multiple
Processor
!BAG
1
I
2.2.3.3.2
BR[2
External L2 bus
request
External L2
controller
"'Aim
DAl:E
1
I
2.2.3.2.2
CAS[o-7]
Column address
strobe 0-7
Memory
DQM[O-7]
8
0
2.2.4.5
"C7BE[3-0]
Commandlbyte
enable
PCI
-
4
1/0
2.2.5.2
"Cr
Caching-inhibit
60x processor
-
1
110
2.2.2.6
CKE
SDRAMclock
enable
Memory
~
1
0
2.2.4.6
CKO
Test clock
Clock
~
1
0
2.2.6.1
"CS[0-7)
SDRAM command
select
Memory
~(O-7]
8
0
2.2.4.7
DALE
Data address latch
enable
Internal L2
controller
~
1
0
2.2.3.1.5
1ml:2
DBGO
Data bus grant 0
60x processor
1
0
2.2.2.7
DB"G01
Address map
Configuration
-
~
I
2.2.8.1
1
0
2.2.3.3.3
DBG1
Data bus grant 1
Multiple
Processor
ilfE
DBG2
Data bus grant 2
Multiple
Processor
7JWEO
1
0
2.2.3.3.3
DBG3
Data bus grant 3
Multiple
Processor
DWE1
1
0
2.2.3.3.3
15BG[2
External L2 data
bus grant
External L2
controller
1RJE
1
0
2.2.3.2.3
"DBG[B
Data bus grant
local bus slave
60x processor
eKE
1
0
2.2.2.8
DeS"
Data RAM chip
select
Internal L2
controller
!BGS
1
0
2.2.3.1.6
D"EVSE[
Device select
PCI
-
1
110
2.2.5.3
DH[0-31).
OL[0-31)
Data bus
60x processor
-
64
110
2.2.2.9
OIRtYJN
Dirty in
IntemalL2
controller
1iIff
1
I
2.2.3.1.7
2-4
MPC106 PCIBIMCUser's Manual
MOTOROLA
Table 2-1. MPC106 Signal Cross Reference (Continued)
Signal Name
Signal
Alternate
Function(s)
Interface
Number
of Pins
I/O
Section #
mn
1
0
2.2.3.1.8
Internal L2
controller
lHilJ[2
1
0
2.2.3.1.9
SDRAMdata
qualifier
Memory
7JM[rJ-7}
8
0
2.2.4.8
Data RAM write
enable 0-2
Internal L2
controller
1Jll«l2
3
0
2.2.3.1.10
FlSHREO
Flush request
PCI (sideband)
1
I
2.2.5.14.1
mE
Flash output
enable
Memory
-
1
0
2.2.4.9
"FOE 1
ROM bank 0
data path width
Configuration
-
1
I
2.2.8.2
"FRAME
Frame
PCI
1
I/O
2.2.5.4
GBl
Global
60x processor
-
1
I/O
2.2.2.10
DIRTY_OUT
Dirty out
Internal L2
controller
r>O£
Data RAM output
enable
DOM[0-7]
OWE"[0-2]
DIBG3
CKO
"GNT
PCI bus grant
PCI
1
I
2.2.5.5
R1T
Hit
Internal l2
controller
-
1
I
2.2.3.1.11
HIT
External l2 hit
External l2
controller
-
1
I
2.2.3.2.4
HAST
Hard reset
Interrupt
-
1
I
2.2.6.2
IRDY
Initiator ready
PCI
1
1/0
2.2.5.6
ISA_MASTER
ISAmaster
PCI (sideband)
-
1
I
2.2.5.14.2
LBeLAIM
local bus slave
claim
60x processor
1
I
2.2.2.11
a>cK
lock
PCI
-
1
I
2.2.5.7
MAO,
MA[1-12]
Memory address
0-12
Memory
ARrJ,
AR[9-2(}}
SDIBA(},
SDMA{1-11}
13
0
2.2.4.10
MCP
Machine check
60x processor
-
1
0
2.2.2.12
mLE
Memory data latch
enable
Memory
~
1
0
2.2.4.11
MEMAcK
Flush acknowledge
PCI (sideband)
1
0
2.2.5.14.3
NMI
Nonmaskable
interrupt
Interrupt
-
1
I
2.2.6.3
PAR
Parity
PCI
-
1
I/O
2.2.5.8
MOTOROLA
Chapter 2. Signal Descriptions
2-5
Table 2-1. MPC106 Signal Cross Reference (ContInued)
-
Signal
Alternate
Functlon(s)
Interface
Signal Name
Number
of Pins
110
Section.
~
PAR[o-7]
Data parity 0-7
Memory
AR[1-81
8
1/0
2.2.4.12
PEFfF{
Parity error
PCI
-
1
110
2.2.5.9
15I"RO
Modified memory
interrupt request
PCI (sideband)
SDRAS
1
0
2.2.5.14.4
PLL[Q-3]
Clock mode
Configuration
-
4
I
2.2.8.3
J5I5EN
Parity path read
enable
Memory
-
1
0
2.2.4.13
'OACK
Quiesce
acknowledge
PoWer
Management
-
1
0
2.2.6.4
OREQ"
Quiesce request
Power
Management
-
1
I
2.2.6.5
"RAS[0-7]
Row address
strobe 0-7
Memory
08[0-7J
8
0
2.2.4.14
RCSO
ROMlbank 0 select
Memory
0
2.2.4.15
ROM location
Configuration
1
I
2.2.8.4
RCS1
ROMlbank 1 select
Memory
1
0
2.2.4.16
Am
PCI bus request
PCI
1
0
2.2.5.10
ATC
Real time clock
Memory
-
1
RCSl)1
1
I
2.2.4.17
SDBAO
SDRAMbank
select
Memory
MAt
AflG
1
0
2.2.4.18
SDOAS"
SDRAM column
address strobe
Memory
MDLE
1
0
2.2.4.19
SDMA[1-11]
SDRAM address
1-11
Memory
AR[10-20]
13
0
2.2.4.20
~
SDRAM row
address strobe
Memory
"PllUJ
1
0
2.2.4.21
SERR
System error
PCI
-
1
1/0
2.2.5.11
STOP"
Stop
PCI
-
1
110
2.2.5.12
SUSPEND
Suspend
Power
Management
1
I
2.2.6.6
SYSCLK
System clock
Clock
-
1
I
2.2.6.7
'fA
Transfer
acknowledge
SOx processor
-
1
110
2.2.2.13
'i'BS'i'
Transfer burst
SOx processor
1
110
2.2.2.14
TCK
JTAG test clock
IEEE 1149.1
JTAG
-
1
I
2.2.7.1
2-6
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 2-1. MPC106 Signal Cross Reference (Continued)
Signal
Signal Name
Alternate
Function(s)
Interface
Number
of Pins
I/O
Section #
TOO
JTAG test data
output
IEEE 1149.1
JTAG
-
1
0
2.2.7.2
TOI
JTAG test data
Input
IEEE 1149.1
JTAG
-
1
I
2.2.7.3
TEA
Transfer error
acknowledge
SOx processor
-
1
0
2.2.2.15
Tag output enable
Internal L2
controller
D/861
1
0
2.2.3.1.12
TMS
JTAG test mode
select
IEEE 1149.1
JTAG
-
1
I
2.2.7.4
TRO'7
Target ready
PCI
1
110
2.2.5.13
TRST
JTAG test reset
IEEE 1149.1
JTAG
-
1
I
2.2.7.5
TS
Transfer start
SOx processor
-
1
I/O
2.2.2.1S
TSIZ[D-2)
Transfer size
SOx processor
3
I/O
2.2.2.17
TT[D-4)
Transfer type
SOx processor
-
5
I/O
2.2.2.18
TV
Tag valid
Internal L2
controller
BfB2
1
110
2.2.3.1.13
TWE
Tag write enable
Internal L2
controller
1ffJ2
1
0
2.2.3.1.14
-
1
0
2.2.4.22
1
110
2.2.2.19
1
I
2.2.2.20
roe-
WE
Write enable
Memory
Wf
Write-through
SOx processor
XATS
Extended address
transfer start
SOx processor
1 The MPC10S samples these signals at power-on reset or hard reset to determine the configuration. After they
are sampled, they assume their normal functions. See Section 2.2.8, "Configuration Signals," for more
information.
2.2.1 Signal States at Reset
When a system reset request is recognized (HRST or power-on reset), the MPC106 aborts
all current internal and external transactions; releases all bidirectional 110 signals to a highimpedance state; ignores the input signals (except for SYSCLK, and the configuration
signals DBGO, FOE, RCSO, and PLL[0-3]), and drives most of the output signals to an
inactive state. (Table 2-2 shows the states of the output-only signals during system reset.)
MOTOROLA
Chapter 2. Signal Descriptions
2-7
Table 2-2. Output Signal States during System Reset
60x processor
State during System Reset
Signal
Interface
BOO
Negated
JE15
TEA
L2
mmt:B/CKE
Driven, but with indeterminate state
DEmO
Configuration input during system reset
~.
Negated
DBGL2IOOE
'DCS
DIRTY_oot
DWE[G-2]
TOE
Memory
BAMro"JBGI:2
TWE
Driven, but with indeterminate state
MA[G-12Y
SDBAO,SDMA[1-11]
High-impedance
~G-1]
Negated
~M[G-7]
~
'PPEN
RAS/CS[G-7]
RCSf
WE
fOE
COnfiguration input during system reset
RCSO
PCI
MEMACK
High-impedance
REO
PIROJS'DRAS
Clock
CKO
Internal (core) clock
Power management
~
High-impedance
IEEE 1149.1 JTAG
TOO
High-Impedance
2.2.2 60x Processor Interface Signals
This section provides descriptions of the 60x processor interface signals on the MPC 106.
Note that with the exception of BGn, BRn, DBGn, DBGLB, and LBCLAIM, all of the 60x
processor interface signals are connected to all processors in a multiprocessor system. See
Section 4.1.2, "Multiprocessor System Configuration," for more information.
2.2.2.1 Address Bus (A[0-31])
The address bus (A[0-31]) consists of 32 signals that are both input and output signals.
2-8
MPC106 PCIBIMC User's Manual
MOTOROLA
2.2.2.1.1 Address Bus (A[O-31 ])-Output
Following are the state meaning and timing comments for A[0--31] as output signals.
State Meaning
Asserted/Negated-Specifies the physical address for 60x bus
snooping.
Timing Comments AssertionlNegation-Driven valid in the same clock cycle as the
assertion ofTS. Once driven, these signals remain valid for the entire
address tenure.
High-impedance-Occurs one clock cycle after the assertion of
AACK.
2.2.2.1.2 Address Bus (A[O-31 ])-Input
Following are the state meaning and timing comments for A[0--31] as input signals.
State Meaning
Asserted/Negated-Specifies the physical address of the bus
transaction. For burst reads, the address is aligned to the critical
double-word address that missed in the instruction or data cache. For
burst writes, the address is aligned to the double-word address of the
cache line being pushed from the data cache.
Timing Comments AssertionlNegation-Must occur in the same clock cycle as the
assertion ofTS. Once driven, these signals must remain stable for the
entire address tenure.
High-impedance-Occurs one clock cycle after the assertion of
AACK.
2.2.2.2 Address Acknowledge (AACK)
The address acknowledge (AACK) signal is an input and output signal on the MPC 106.
2.2.2.2.1 Address Acknowledge (AACK)-Output
Following are the state meaning and timing comments for AACK as an output signal.
State Meaning
Asserted-Indicates that the address tenure of a transaction is
terminated. On the clock cycle following the assertion of AACK, the
bus master releases the address-tenure-related signals to the highimpedance state and samples ARTRY.
Negated-Indicates that the address tenure must remain active, and
all address-tenure-related signals must remain valid.
Timing Comments Assertion-Occurs a programmable number of clock cycles after TS
and whenever ARTRY conditions are resolved. For pipelined
transactions, AACK is asserted in the same clock cycle or after the
last TA of the previous data tenure. When using the internal L2
controller, the assertion of AACK is delayed to hold the address valid
for the tag update.
Negation-Occurs one clock cycle after assertion.
High-impedance-Occurs one clock cycle after negation.
MOTOROLA
Chapter 2. Signal Descriptions
2-9
2.2.2.2.2 Address Acknowledge (AACK)-Input
Following are the state meaning and timing comments for AACK as an input signal.
State Meaning
Asserted-Indicates that the externally-controlled L2 cache is
terminating the address tenure. On the cycle following the assertion
of AACK, the bus master releases the address tenure related signals
to the high-impedance state and samples ARTRY.
Negated-Indicates that the address tenure must remain active, and
all address-tenure-related signals must remain valid.
Timing Comments Assertion-Occurs anytime after the assertion of TS when ARTRY
is valid (or expected to be valid in the next clock cycle). For pipelined
transactions, the assertion of AACK should not occur before the last
TA of the previous data tenure.
Negation-Occurs one clock cycle after assertion.
High-impedance-Occurs one clock cycle after negation.
2.2.2.3 Address Retry (ARTRY)
The address retry (ARTRY) signal is both an input and output signal on the MPC106.
2.2.2.3.1 Address Retry (ARTRY}-Output
Following are the state meaning and timing comments for ARTRY as an output signal.
State Meaning
Asserted-Indicates that the initiating 60x bus master must retry the
current address tenure.
NegatedlHigh-impedance-Indicates that the MPC106 does not
require the address tenure to be retried.
Timing Comments Assertion-For processor to system memory accesses, occurs two
clock cycles after TS. For processor to PCI accesses, the MPC106
withholds ARTRY and AACKuntil the ARTRY condition for the
PCI access is resolved. See Section 4.3.3.1, "MPC106 Snoop
Response," for more information. Once asserted, occurs one clock
after the assertion of AACK.
NegationIHigh-impedance-ARTRY is released to high-impedance
for the first half of the second clock cycle after the assertion of
AACK, then it is negated for one clock, and then it is released to
high-impedance.
2.2.2.3.2 Address Retry (ARTRY)-Input
Following are the state meaning and timing comments for ARTRY as an input signal.
State Meaning
Asserted-During a snoop operation, indicates that the 60x either
requires the current address tenure to be retried due to a pipeline
collision or needs to perform a snoop copy-back operation.
During normal 60x bus cycles in a multiprocessor system, indicates
that the other 60x requires the address tenure to be retried.
2-10
MPC106 PCIS/MC User's Manual
MOTOROLA
NegatedlHigh-impedance-lndicates that the address tenure is not
required to be retried.
Timing Comments Assertion-Occurs one clock after the assertion of AACK. Note that
ARTRY may be asserted early, but it is sampled one clock after the
assertion of AACK.
NegationlHigh-impedance-ARTRY is released to high-impedance
for the first half of the second clock cycle after the assertion of
AACK, then it is negated for one clock, and then it is released to
high-impedance.
2.2.2.4 Bus Grant 0 (BGO)-Output
The bus grant 0 (BGO) signal is an output on the MPC106. Following are the state meaning
and timing comments for the BGO signal.
State Meaning
Asserted-Indicates that the primary 60x processor may, with the
proper qualification, begin a bus transaction and assume mastership
of the address bus.
Negated-Indicates that the primary 60x processor is not granted
mastership of the next address bus tenure.
Timing Comments Assertion-Occurs when BRO is the highest priority request that is
asserted. Also occurs if the 60x bus is parked on the primary 60x
processor and no other request is pending.
Negation-Occurs when other higher priority transactions are
pending.
2.2.2.5 Bus Request 0 (BRO)-Input
The bus request 0 (BRO) signal is an input on the MPC 106. Following are the state meaning
and timing comments for the BRO signal.
State Meaning
Asserted-Indicates that the primary 60x processor requires
mastership of the 60x bus for a transaction.
Negated-Indicates that the primary 60x processor does not require
mastership of the 60x bus.
Timing Comments Assertion-May occur when bus grant 0 (BGO) is negated and a bus
transaction is needed by the 60x processor. This may occur even if
the two possible pipeline accesses have already occurred.
Negation-Occurs for at least one clock cycle after an accepted,
qualified bus grant, even if another transaction is pending on the 60x
processor. It is also negated for at least one clock cycle when the
assertion of ARTRY is detected on the 60x bus (except for assertions
due to primary 60x snoop copy-back operations).
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2.2.2.6 Caching-Inhibited (CI)-Input/Output
The caching-inhibited (CI) signal is both an input and output signal on the MPC106.
Following are the state meaning and timing comments for the CI signal.
State Meaning
Asserted-Indicates that an access is caching-inhibited.
Negated-Indicates that an access is caching-allowed. Note that CI
is always negated for snoop cycles initiated by the MPCI06.
Timing Comments AssertionlNegation-The same asA[O-31].
High-impedance-The same as A[0-31].
2.2.2.7 Data Bus Grant 0 (DBGO)-Output
The data bus grant 0 (DBGO) signal is an output on the MPC106. Following are the state
meaning and timing comments for the DBGO signal. Note that DBGO also serves as a
configuration input at power-on reset (POR). See Section 2.2.8, "Configuration Signals,"
for more information.
State Meaning
Asserted-Indicates that the primary 60x may, with the proper
qualification, assume mastership of the data bus. A qualified data bus
grant is defined as the assertion of BGO and negation of ARTRY. The
requirement for the ARTRY signal is only for the address bus tenure
associated with the data bus tenure about to be granted (that is, not
for another address tenure available because of address pipelining).
Negated-Indicates that the primary 60x processor is not granted
mastership of the data bus.
Timing Comments Assertion-Occurs on the first clock cycle in which the data bus is
not busy and the primary 60x processor has the highest priority
outstanding data transaction. If the data bus is parked on the primary
60x processor, DBGO is asserted one clock cycle after BGO. In fastL2 mode, DBGO may be asserted as early as the same clock cycle as
the last TA of the previous data tenure.
Negation-Occurs one clock cycle after assertion.
2.2.2.8 Data Bus Grant Local Bus Slave (DBGLB)-Output
The data bus grant local bus slave (DBGLB) signal is an output on the MPC106. Following
are the state meaning and timing comments for the DBGLB signal.
State Meaning
Asserted-Indicates, to the local bus slave, that the MPC106 has
granted a60x processor the data bus. Ifthe cycle is a local bus slave
cycle, the local bus slave can use the data bus to transfer data to the
60x processor.
Negated-Indicates that a 60x processor has not been granted
mastership of the data bus.
Timing Comments Assertion-The same as DBGn except if the previous transaction is
an external L2 cache operation and the externally-controlled L2
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asserted AACK before DBGn. In that case, DBGLB is not asserted
for the external L2 cache transaction (so as not to confuse the local
bus slave). See Section 4.4.5, "60x Local Bus Slave Support," for
more information.
Negation-Occurs one clock cycle after assertion.
2.2.2.9 Data Bus (DH[O-31], DL[O-31])
The data bus (DH[0--31], DL[0--31]) consists of 64 signals that are both input and output
signals on the MPC106. The data bus is comprised of two halves-data bus high (DH[O-31]) and data bus low (DL[0--31]). Table 2-3 specifies the byte lane assignments for the data
bus.
Table 2-3. Data Bus Byte Lane Assignments
Byte Lane
Data Bus Signals
DH[Q-7]
o (MSB)
DH[8-15]
1
DH[16-23]
2
DH[24-31]
3
DL[Q-7]
4
DL[8-15]
5
DL[16-23]
6
DL[24-31]
7 (LSB)
2.2.2.9.1 Data Bus (DH[O-31], DL[O-31 ]}-Output
Following are the state meaning and timing comments for the data bus as output signals.
State Meaning
AssertedlNegated-Represents the value of data being driven by the
MPC106.
Timing Comments AssertionlNegation-For a 60x processor read transaction, the data
bus signals are valid one clock cycle after the DBGn signal is
asserted. For PCI-to-memory or internal buffer flush transactions,
the data bus signals are valid at least one clock cycle after the data
bus becomes idle.
High-impedance-For 60x processor read transactions, the data bus
signals are released to high-impedance one clock cycle after the last
assertion ofTA or one clock cycle after detecting a qualified ARTRY.
For PCI-to-memory or internal buffer flush transactions, the data bus
signals are released to high-impedance when the transaction is
complete.
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2.2.2.9.2 Data Bus (DH[O-31], Dl[O-31 ])-Input
Following are the state meaning and timing comments for the data bus as input signals.
State Meaning
AssertedlNegated-Represents the state of data being driven by a
60x processor, the L2 cache, or the memory subsystem.
Timing Comments AssertionlNegation-For a 60x processor write transaction, the data
bus signals are valid one clock cycle after the assertion of DBGn. For
an L2 copy-back transaction, the data bus signals are valid when data
RAM output enable (DOE) is asserted. For a memory read
transaction, the data bus signals are valid at a time dependent on the
memory interface configuration. Refer to Chapter 6, "Memory
Interface," for more information.
High-impedance-the data bus signals are released to highimpedance one clock cycle after the last assertion of TA. If the
address tenure is ARTRY d, the data bus signals go to a highimpedance state one clock cycle after the qualified ARTRY.
2.2.2.10 Global (GBl)-lnput/Output
The global (GBL) signal is both an input and output signal on the MPC106. Following are
the state meaning and timing comments for the GBL signal.
State Meaning
Asserted-Indicates that an access is global. Coherency needs to be
enforced by hardware. Note that GBL is always asserted for snoop
cycles initiated by the MPC106.
Negated-Indicates that an access is not global. Hardware-enforced
coherency is not required.
Timing Comments AssertionlNegation-The same as A[0-31].
High-impedance-The same asA[0-31].
2.2.2.11 local Bus Slave Claim (lBClAIM)-lnput
The local bus slave claim (LBCLAIM) signal is an input on the MPC 106. Following are the
state meaning and timing comments for the LBCLAIM signal.
State Meaning
Asserted-Indicates that the local bus slave claims the transaction
and is responsible for driving TA during the data tenure.
Negated-Indicates that the transaction is not claimed by the local
bus slave.
Timing Comments Assertion-The MPC 106 samples the LBCLAIM signal when
PICR2[CF_L2_HIT_DELAY] expires.
Negation-Occurs one clock cycle after assertion.
2.2.2.12 Machine Check (MCP)-Output
The machine check (MCP) signal is an output on the MPC 106. Following are the state
meaning and timing comments for the MCP output signal.
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State Meaning
Asserted-Indicates that the MPC106 detected an illegal
transaction, a memory select error, or a parity error on a memory
read cycle. Assertion of SERR, PERR, or NMI may also trigger
MCP.
Negated-Indicates that normal operation should proceed.
Timing Comments Assertion-Occurs synchronous to the 60x bus clock.
Negationlhigh-impedance-Occurs after all error flags have been
cleared by software and the machine check exception vector has
been accessed. The configuration parameter, SHARED_MCP, in
power management configuration register 2 (PMCR2) controls
whether the MPC 106 negates MCP or releases MCP to highimpedance.
2.2.2.13 Transfer Acknowledge (TA)
The transfer acknowledge (TA) signal is both an input and output signal on the MPC106.
2.2.2.13.1 Transfer Acknowledge (TA)-Output
Following are the state meaning and timing comments for TA as an output signal.
State Meaning
Asserted-Indicates that the data has been latched for a write
operation, or that the data is valid for a read operation, thus
terminating the current data beat. If it is the last (or only) data beat,
this also terminates the data tenure.
Negated-Indicates that the 60x must extend the current data beat
(insert wait states) until data can be provided or accepted by the
MPC106.
Timing Comments Assertion-Occurs when the current data beat can be completed.
Negation-Occurs after the clock cycle of the final (or only) data
beat of the transfer. For a burst transfer, TA may be negated between
beats to insert one or more wait states before the completion of the
next beat.
High-impedance-Occurs one-half clock cycle after negation.
2.2.2.13.2 Transfer Acknowledge (TA)-Input
Following are the state meaning and timing comments for TA as an input signal.
State Meaning
Asserted-Indicates that the external L2 cache or local bus slave has
latched data for a write operation, or is indicating the data is valid for
a read operation, thus terminating the current data beat. If it is the last
(or only) data beat, the data tenure is terminated.
Negated-Indicates that the 60x bus master must extend the current
data beat (insert wait states) until data can be provided or accepted
by the external L2 cache or local bus slave.
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Timing Comments Assertion-Occurs when the current data beat can be completed.
Negation-Occurs after the clock cycle of the final (or only) data
beat of the transfer. For a burst transfer, TA may be negated between
beats to insert one or more wait states before the completion of the
next beat.
High-impedance-Occurs one-half clock cycle after negation.
2.2.2.14 Transfer Burst (TBST)
The transfer burst (TBST) signal is an input and output signal on the MPC 106.
2.2.2.14.1 Transfer Burst (TBST)-Output
Following are the state meaning and timing comments for TBST as an output signal. Note
that all MPC106-generated snoop operations are 8-word bursts; therefore, TBST is always
asserted for snoop operations.
State Meaning
Asserted-Indicates that a burst transfer is in progress.
Negated-Indicates that a burst transfer is not in progress.
Timing Comments AssertionlNegation-The same as A[O-31].
High-impedance-The same as A[0-31].
2.2.2.14.2 Transfer Burst (TBST)-Input
Following are the state meaning and timing comments for TBST as an input signal.
State Meaning
Asserted-Indicates that a burst transfer is in progress.
Negated-Indicates that a burst transfer is not in progress.
Timing Comments AssertionlNegation-The same as A[O-31].
High-impedance-The same asA[0-31].
2.2.2.15 Transfer Error Acknowledge (TEA)-Output
The transfer error acknowledge (TEA) signal is an output on the MPCI06. Note that the
TEA signal can be disabled by clearing the TEA_EN bit in processor interface
configuration register 1 (PICRI). Following are the state meaning and timing comments for
the TEA signal.
State Meaning
Asserted-Indicates that a bus error has occurred. Assertion of TEA
terminates the data transaction in progress; that is, it is not necessary
to assert TA because it is ignored by the target processor. An
unsupported transaction will cause the assertion of TEA (provided
TEA is enabled). Unsupported transactions include the following:
• A direct-store access
• A graphics read or write (eciwx or ecowx)
• A write to the PCI interrupt acknowledge space
• A write to Flash space, when Flash writes are disabled
• An aborted processor-to-PCI transaction
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Negated-Indicates that no bus error has been detected.
Timing Comments Assertion-Occurs during the data tenure in which the bus error is
detected.
Negation-Occurs one clock after assertion.
2.2.2.16 Transfer Start (TS)
The transfer start (TS) signal is both an input and an output signal on the MPC 106.
2.2.2.16.1 Transfer Start (TS)-Output
Following are the state meaning and timing comments for the TS output signal.
State Meaning
Asserted-Indicates that the MPCI06 has started a bus transaction,
and that the address and transfer attribute signals are valid. Note that
the MPC 106 only initiates a transaction to broadcast the address of a
PCI access to memory for snooping purposes.
Negated-Has no special·meaning.
Timing Comments Assertion-Occurs two clock cycles after BGn is negated and the
address bus is idle.
Negation-Occurs one clock cycle after assertion.
High-impedance-Occurs one clock cycle after the assertion of
AACK.
2.2.2.16.2 Transfer Start (TS)-Input
Following are the state meaning and timing comments for the TS input signal.
State Meaning
Asserted-Indicates that a 60x bus master has begun a bus
transaction, and that the address and transfer attribute signals are
valid.
Negated-Has no special meaning.
Timing Comments Assertion-May occur one clock cycle after BGn is asserted.
Negation- Occurs one clock cycle after assertion.
2.2.2.17 Transfer Size (TSIZ[O-2])
The transfer size (TSIZ[0-2]) signals consist of three input and output signals on the
MPCI06.
2.2.2.17.1 Transfer Size (TSIZ[O-2])-Output
Following are the state meaning and timing comments for TSIZ[0-2] as output signals.
Note that all MPC106-generated snoop operations are eight-word bursts; therefore
TSIZ[0-2] are always ObOlO for snoop operations.
State Meaning
MOTOROLA
AssertedlNegated-In conjunction with the transfer burst (TBST)
signal, TSIZ[0-2] specify the data transfer size for the 60x bus
Chapter 2. Signal Descriptions
2-17
transaction. Refer to Section 4.3.2.2, "TBST and TSIZ[0--2] Signals
and Size of Transfer," for transfer size encodings.
Timing Comments AssertionlNegation-The same as A[0-31J.
High-impedance-The same asA[0--31].
2.2.2.17.2 Transfer Size (TSIZ[O-2])-lnput
Following are the state meaning and timing comments for TSIZ[0--2] as input signals.
State Meaning
AssertedlNegated-In conjunction with the transfer burst (TBST)
signal, TSIZ[0--2] specify the data transfer size for the 60x bus
transaction. Refer to Section 4.3.2.2, "TBST and TSIZ[0--2] Signals
and Size of Transfer," for transfer size encodings.
Timing Comments AssertionlNegation-The same as A[0-31].
High-impedance-The same as A[0--31].
2.2.2.18 Transfer Type (TT[O-4])
The transfer type (TT[O-4]) signals consist of five input and output signals on the MPC 106.
2.2.2.18.1 Transfer Type {TT[O-4])-Output
Following are the state meaning and timing comments for TT[0--4] as output signals.
State Meaning
AssertedlNegated-Specifies the type of 60x bus transfer in progress
for snooping. Refer to Section 4.3.2.1, "Transfer Type Signal
Encodings," for transfer type encodings.
Timing Comments AssertionlNegation-The same asA[0-31].
High-impedance-The same as A[0--31].
2.2.2.18.2 Transfer Type (TT[O-4])-lnput
Following are the state meaning and timing comments for TT[0--4] as input signals.
State Meaning
AssertedlNegated-Specifies the type of 60x bus transfer in
progress. Refer to Section 4.3.2.1, "Transfer Type Signal
Encodings," for transfer type encodings.
Timing Comments AssertionlNegation-The same as A[0-31].
High-impedance-The same as A[0--31].
2.2.2.19 Write-Through (WT)-lnputlOutput
The write-through (WT) signal is both an input and output signal on the MPC106.
Following are the state meaning and timing comments for the WT signal.
State Meaning
Asserted-Indicates that an access is write-through.
Negated-Indicates that an access is write-back. Note that WT is
always negated for snoop cycles initiated by the MPC106.
Timing Comments AssertionlNegation-The same as A[0--31].
High-impedance-The same as A[0--31].
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MOTOROLA
2.2.2.20 Extended Address Transfer Start (XATS)-Input
The XATS signal is an input on the MPC 106. Following are the state meaning and timing
comments for the XATS signal.
State Meaning
Asserted-Indicates that the 60x has started a direct-store access
(using the extended transfer protocol). Since direct-store accesses
are not supported by the MPCI06, the MPC106 automatically
asserts the TEA signal when XATS is asserted (provided TEA is
enabled). If TEA is disabled, the MPC 106 terminates the direct-store
access by asserting TA; however, no data is ,altered for write
operations, and invalid data is returned on read operations.
Negated-Has no special meaning.
Timing Comments Assertion-May occur one clock cycle after BGn is asserted. The
XATS signal can only be asserted by a processor (that is, the
MPC106 cannot assert XATS).
Negation-Occurs one clock cycle after assertion.
2.2.3 L2 Cache/Multiple Processor Interface Signals
The MPCI06 provides support for either an internal L2 controller or an external L2
controller and/or multiple 60x processors.
The signals ADSIDALElBRL2, BAIIBAAlBGL2, DOEIDBGL2, and HIT function
differently depending on whether the MPC106 is in the internal L2 controller or external
L2 controller mode.
The signals BAOIBR3, DCSIBG3, DIRTY_INIBR1, DIRTY_OUTIBG1, DWEOIDBG2,
DWEIIDBG3, TOEIDBG1, TVIBR2, and TWElBG2 function differently depending on
whether the MPC106 is in the internal L2 controller or multiple 60x processor mode.
Section 2.2.3.1, "Internal L2 Controller Signals," describes the internal L2 controller
configuration for these signals; Section 2.2.3.2, "External L2 Controller Signals," describes
the external L2 controller configuration for these signals; and Section 2.2.3.3, "Multiple
Processor Interface Signals," describes the multiple processor configuration for these
signals.
2.2.3.1 Internal L2 Controller Signals
This section provides a brief description of the interface signals for the internal L2
controller. The internal L2 controller supports synchronous burst SRAMs, pipelined burst
SRAMs, and asynchronous SRAMs. Some of the signals perform different functions
depending on the SRAM configuration.
MOTOROLA
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2-19
2.2.3.1.1 Address Strobe (ADS)-Output
The address strobe (ADS) signal is an output on the MPC106. It is used for burst SRAM
configurations only. Asynchronous SRAM configurations use the alternate function DALE.
Following are the state meaning and timing comments for the ADS signal. Note that this
signal has an on-chip pull-up resistor.
State Meaning
Asserted-Indicates that the address is valid to be latched by the
burst SRAMs.
Negated-Indicates that the burst SRAMs should use addresses from
their internal counters.
Timing Comments Assertion-The MPC l06 asserts ADS during the 60x bus address
phase. The MPC 106 also asserts ADS when a write cycle needs to be
aborted.
Negation-The MPC 106 negates ADS until the data access is
completed.
2.2.3.1.2 Burst Address 0 (BAO}-Output
The burst address 0 (BAO) signal is an output on the MPC 106. It is used for asynchronous
SRAM configurations only. Following are the state meaning and timing comments for the
BAO signal.
State Meaning
AssertedlNegated-Indicates the most-significant bit of the burst
counter address.
Timing Comments AssertionlNegation-Valid when DALE is negated, after each TA
assertion.
2.2.3.1.3 Burst Address 1 (BA1)-Output
The burst address 1 (BAl) signal is an output on the MPC106. It is used for asynchronous
SRAM configurations only. Burst SRAM configurations use the alternate function BAA.
Following are the state meaning and timing comments for the BAt signal.
State Meaning
AssertedlNegated-Indicates the least-significant bit (Isb) of the
burst counter address.
Timing Comments AssertionlNegation-Valid when DALE is negated, after each TA
assertion.
2.2.3.1.4 Bus Address Advance (BAA)-Output
The bus address advance (BAA) signal is an output on the MPCl06. It is used for burst
SRAM configurations only. Asynchronous SRAM configurations use the alternate function
BAl. Following are the state meaning and timing comments for the BAA signal.
State Meaning
Asserted-Indicates that the burst SRAMs should increment their
internal addresses.
Negated-Indicates no change to the addresses.
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Timing Comments AssertionlNegation-The MPCI06 asserts BAA together with TA
during a read access and one clock cycle after TA during write
accesses (to advance the burst address).
2.2.3.1.5 Data Address Latch Enable (DALE)-Output
The data address latch enable (DALE) signal is an output on the MPC106. Following are
the state meaning and timing comments for the DALE signal.
State Meaning
Asserted-Indicates the external address latch should latch the
current 60x bus address.
Negated-Indicates the external address latch should be transparent.
Timing Comments Assertion-Occurs when the data SRAM access starts and the
address is valid.
Negation-Occurs when the data access is completed.
2.2.3.1.6 Data RAM Chip Select (DCS)-Output
The data RAM chip select (DCS) signal is an output on the MPC106. Following are the
state meaning and timing comments for the DCS signal.
State Meaning
Asserted-Enables the L2 data RAMs for read or write operations.
Negated-Disables the L2 data RAMs.
Timing Comments AssertionlNegation-For a burst SRAM configuration, DCS is valid
when ADS is asserted.
-Dr-
For a pipelined burst SRAM configuration, DCS is valid when ADS
or TS is asserted.
-Dr-
For an asynchronous SRAM configuration, DCS is asserted when a
data read or write is in progress. DCS is negated when the L2 cache
is idle.
2.2.3.1.7 Dirty In (DIRTY_IN)-Input
The dirty in (DIRTY_IN) signal is an input on the MPC 106. The polarity of the DIRTY_IN
signal is programmable by using the PICR2[CF_MOD_HIGH] parameter; see
Section 3.2.7, "Processor Interface Configuration Registers," for more information.
Following are the state meaning and timing comments for the DIRTY_IN signal.
State Meaning
Asserted-Indicates that the selected L2 cache line is modified.
Negated-Indicates that the selected L2 cache line is unmodified.
Timing Comments AssertionlNegation-The DIRTY_IN signal is valid when the L2 hit
delay after TS expires. The DIRTY_IN signal is held valid until the
end of the address phase.
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Chapter 2. Signal Descriptions
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2.2.3.1.8 Dirty Out (DIRTY_OUT)-Output
The dirty out (DIRTY_OUT) signal is an output on the MPC 106. The polarity of the
DIRTY_OUT signal is programmable by using the PICR2[CF_MOD_HIGH] parameter;
see Section 3.2.7, "Processor Interface Configuration Registers," for more information.
Following are the state meaning and timing comments for the DIRTY_OUT signal.
State Meaning
Asserted-Indicates that the L2 cache line should be marked
modified.
Negated-Indicates that the L2 cache line should be marked
unmodified.
Timing Comments AssertionlNegation-TheDIRTY_OUT signal is valid when the tag
write enable (fWE) signal is asserted to indicate a new line status.
The DIRTY_OUT signal is held valid for one clock cycle after TWE
is negated.
2.2.3.1.9 Data RAM Output Enable (DOE)-Output
The data RAM output enable (DOE) signal is an output on the MPC106. Following are the
state meaning and timing comments for the DOE signal.
State Meaning
Asserted-Indicates that the L2 data RAMs should drive the data
bus.
Negated-Indicates that the L2 data RAM outputs should be
released to the high-impedance state.
Timing Comments AssertionlNegation-See Chapter 5, "Secondary Cache Interface,"
for more detailed timing information.
2.2.3.1.10 Data RAM Write Enable (DWE[O-2])-Output
The data RAM write enable (DWE[0-2]) signals are outputs on the MPC106. Following
are the state meaning and timing comments for the DWEn signals.
State Meaning
Asserted-Indicates that a write to the L2 data,RAMs is in progress.
Negated-Indicates that no writes to the L2 data RAMs are in
progress.
Timing Comments AssertionlNegation-See Chapter 5, "Secondary Cache Interface,"
for more detailed timing information. Note that all the DWE signals
have the same timing. They are not gated by byte enables. Multiple
DWEs are used to reduce loading.
2.2.3.1.11 Hit (HIT)-Input
The hit (HIT) signal is an input on the MPC106. The polarity of the HIT signal is
programmable by using the PICR2[CF_HIT_HIGH] parameter; see Section 3.2.7,
"Processor Interface Configuration Registers," for more information. Following are the
state meaning and timing comments for the HIT signal.
State Meaning
Asserted-Indicates that the L2 cache has detected a hit.
Negated-Indicates that the L2 cache has not detected a hit.
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Timing Comments AssertionlNegation-The HIT signal is valid when the L2 hit delay
after TS expires, and held valid until the end of the address phase.
The L2 hit delay is programmable by using the
PICR2[CF_L2_HIT_DELAY] parameter.
2.2.3.1.12 Tag Output Enable (TOE)-Output
The tag output enable (TOE) signal is an output on the MPC106. Following are the state
meaning and timing comments for the TOE signal.
State Meaning
Asserted-Indicates that the tag RAM should drive its indexed
content onto the 60x address bus.
Negated-Indicates that the tag RAM output should be released to
the high-impedance state.
Timing Comments AssertionlNegation-Asserted for two or three clock cycles for tag
read operations during L2 copy-back cycles (depending on
PICR2[CF_TOE_WIDTH]); see Chapter 5, "Secondary Cache
Interface," for more detailed timing information.
2.2.3.1.13 Tag Valid (TV)-Output
The tag valid (TV) signal is an output on the MPC 106. The polarity of the TV signal is
programmable by using the PICR2[CF_MOD_HIGH] parameter; see Section 3.2.7,
"Processor Interface Configuration Registers," for more information. Also, note that this
signal has an on-chip pull-up resistor. Following are the state meaning and timing
comments for the TV signal.
State Meaning
Asserted-Indicates that the current L2 cache line should be marked
valid.
Negated-Indicates that the current L2 cache line should be marked
invalid.
Timing Comments AssertionlNegation-The TV signal is valid when tag write enable
(TWE) is asserted to update the tag status. TV is held valid for one
clock cycle after TWE is negated. Otherwise, TV is normally driven
for tag lookup operations.
High-impedance-The TV signal is either released to a highimpedance state during tag read operations or always driven
depending upon the parameters PICR2[CF_FAST_CASTOUT] and
PICR2[CF_HOLD]; see Section 3.2.7, "Processor Interface
Configuration Registers," for more information.
2.2.3.1.14 Tag Write Enable (TWE)-Output
The tag write enable (TWE) signal is an output on the MPC106. Following are the state
meaning and timing comments for the TWE signal.
State Meaning
MOTOROLA
Asserted-Indicates that the tag addresS, valid, and dirty bits should
be updated.
Chapter 2. Signal Descriptions
2-23
Negated-Indicates that updating the tag address, valid, and dirty
bits is not currently necessary.
Timing Comments Assertion/Negation-The TWE signal is asserted for one clock cycle
during tag write operations.
2.2.3.2 External L2 Controller Signals
When an external L2 cache controller is used instead of the internal L2 controller, four
signals change their functions. This section provides a brief description of the signals used
by the MPC 106 to interface with the external L2 cache controller.
2.2.3.2.1 External L2 Bus Grant (BGL2)-Output
The external L2 bus grant (BGL2) signal is an output on the MPC 106. Following are the
state meaning and timing comments for the BGL2 signal.
State Meaning
Asserted-Indicates that the external L2 controller may assume
mastership of the 60x address bus.
Negated-Indicates that the external L2 controller is not granted
mastership of the next 60x address bus tenure.
Timing Comments Assertion-May occur at any time when the external L2 bus request
(BRL2) signal is asserted and the 60x address bus is available.
Negation-May occur at any time after assertion, or after BRL2 is
negated.
2.2.3.2.2 External L2 Bus Request (BRL2)-lnput
The external L2 bus request (BRL2) signal is an input on the MPC106. Following are the
state meaning and timing comments for the BRL2 signal. Note that this signal has an onchip pull-up resistor.
State Meaning
Asserted-Indicates that the external L2 controller requires
mastership of the 60x bus for a transaction.
Negated-Indicates that the external L2 controller does not require
mastership of the 60x bus.
Timing Comments Assertion-May occur at any time.
Negation-May occur at any time. However, BRL2 must be negated
for at least one clock cycle after an accepted, qualified external L2
bus grant.
2.2.3.2.3 External L2 Data Bus Grant (DBGL2)-Output
The external L2 data bus grant (DBGL2) signal is an output on the MPC 106. Following are
the state meaning and timing comments for the DBGL2 signal.
State Meaning
Asserted-Indicates that the external L2 controller may assume
mastership of the 60x data bus.
Negated-Indicates that the external L2 controller is not granted
mastership of the data bus.
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Timing Comments Assertion-Occurs on the first clock cycle in which the data bus is
not busy and the external L2 controller has the highest priority
outstanding data transaction.
Negation-Occurs one clock cycle after assertion.
2.2.3.2.4 Hit (HIT)-Input
The hit (HIT) signal is an input on the MPC 106. For the external L2 controller, the polarity
of the HIT signal is always active low. That is, it is not affected by the
PICR2[CF_HIT_HIGH] parameter. Following are the state meaning and timing comments
for the HIT signal.
State Meaning
Asserted-Indicates that the current transaction is claimed by the
external L2 controller. The external L2 controller will assert AACK
and TA for the transaction.
Negated-Indicates that the current transaction is not claimed by the
external L2 controller. The MPC 106 should handle the transaction
and control AACK and TA as appropriate.
Timing Comments Assertion/Negation-The HIT signal is valid when the L2 hit delay
after TS expires, and is held valid until the end of the address phase.
The L2 hit delay is programmable by using the
PICR2[CF_L2_HIT_DELAY] parameter.
2.2.3.3 Multiple Processor Interface Signals
When a system implementation uses more than one 60x processor, nine of the internal L2
controller signals change their functions. This section provides a brief description of the
multiple processor interface signals. Note that in a multiprocessor system, with the
exception of bus request (BRn), bus grant (BGn), and data bus grant (DBGn), all of the 60x
processor interface signals are connected to each processor. See Section 4.1.2,
"Multiprocessor System Configuration," for more information.
2.2.3.3.1 Bus Grant 1-3 (BG[1-3])-Output
The bus grant (BG[1-3]) signals are outputs on the MPC106. Following are the state
meaning and timing comments for the BGn signals.
State Meaning
Asserted-Indicates that processor n (where n is 1, 2, or 3) may, with
the proper qualification, begin a bus transaction and assume
mastership of the address bus.
Negated-Indicates that processor n is not granted mastership of the
next address bus tenure.
Timing Comments Assertion-Occurs when BRn is the highest-priority request that is
asserted.
Negation-Occurs when other higher-priority transactions are
pending.
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Chapter 2. Signal Descriptions
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2.2.3.3.2 Bus Request 1-3 (BR[1-3])-lnput
The bus request (BR[1-3]) signals are inputs on the MPCI06. Following are the state
meaning and timing comments for the BRn signals.
State Meaning
Asserted-Indicates that processor n (where n is 1,2, or 3) requires
mastership of the 60x bus fora transaction.
Negated-Indicates that processor n does not require mastership of
the bus.
Timing Comments Assertion-May occur when BGn is negated and a bus transaction is
needed by processor n. This may occur even if the two possible
pipeline accesses have already occurred.
Negation-Occurs for at least one bus cycle after an accepted,
qualified bus grant, even if another transaction is pending on
processor n. It is also negated for at least one bus cycle when the
assertion of ARTRY is detected on the 60x bus (except for assertions
due to 60x snoop copy-back operations).
2.2.3.3.3 Data Bus Grant 1-3 (DBG[1-3])-Output
The data bus grant (DBG[1-3]) signals are outputs on the MPC106. Following are the state
meaning and timing comments for the DBGn signals.
State Meaning
Asserted-Indicates that processor n (where n is 1.2, or 3) may, with
the proper qualification, assume mastership of the data bus. A
qualified data bus grant is defined as the assertion of DBGn, negation
ofDBB, and negation of ARTRY. The ARTRY signal requirement is
only for the addressbus tenure associated with the data bus tenure
about to be granted (that is, not for another address tenure available
because of address pipelining).
Negated-Indicates that processor n is not granted, mastership of the
data bus.
Timing Comments Assertion-Occurs one bus clock cycle before data bus is available,
and when processor n has the highest priority for an outstanding data
transaction.
Negation-Occurs one clock after assertion.
2.2.4 Memory Interface Signals
The memory interface supports either standard DRAMs, extended data out DRAMs (EDO
DRAMs), or synchronous DRAMs (SDRAMs) and either standard ROM or Flash devices.
Some of the memory interface signals perform different functions depending on the RAM
and ROM configurations. This section provides a brief description of the memory interface
signals on the MPC 106.
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2.2.4.1 ROM Address 0 (ARO)-Output
The ROM address 0 (ARO) signal is an output signal on the MPC106.
Note that the ARO signal is only supported for ROM bank 0 when configured for an 8-bit
ROM data bus width.
Following are the state meaning and timing cominents for the ARO output signal.
State Meaning
AssertedlNegated-Represents address bit 0 (the most-significant
bit) of the 8-bit ROMIFlash. Bits 1-20 of the ROM address are
provided by AR[1-8] andAR[9-20].
Timing Comments Assertion/Negation-The ROM address is valid on assertion of
RCSO or RCS 1.
2.2.4.2 ROM Address 1-8 (AR[1-8])-Output
The ROM address 1-8 (AR[1-8]) signals are output signals only for the ROM address
function. Note that these signals are both input and output signals for the memory parity
function (PAR[0-7]). Following are the state meaning and timing comments for AR[1-8]
as output signals.
State Meaning
AssertedlNegated-Represents bits 1-8 of the ROMIFlash address.
The other ROM address bits are provided by ARO and AR[9-20].
Timing Comments Assertion/Negation-The ROM address is valid on assertion of
RCSO or RCS 1.
2.2.4.3 ROM Address 9-20 (AR[9-20])-Output
The ROM address (AR[9-20]) signals consist of 12 output signals on the MPC106.
Following are the state meaning and timing comments for the AR[9-20] output signals.
State Meaning
AssertedlNegated-Represents bits 9-20 of the ROMIFlash address
(the 12 lowest-order bits, withAR20 as the lsb). Bits 0-8 of the ROM
address are provided by ARO and AR[1-8].
Timing Comments Assertion/Negation-The ROM address is valid on assertion of
RCSO or RCS I.
2.2.4.4 Buffer Control (BCTL[o-1])-Output
The two buffer control (BCTL[O-I]) signals are outputs on the MPC106. Following are the
state meaning and timing comments for the BCTL[O-I] output signals.
State Meaning
AssertedlNegated-Used to control external data bus buffers
(directional control and high-impedance state) between the 60x bus
and memory. See Section 6.2, "Memory Interface Signal Buffering,"
for more information.
Note that data buffers may be optional for lightly loaded data buses,
but buffers are required whenever an L2 cache and ROMlFlash (on
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Chapter 2. Signal Descriptions
2-27
the 60x processor/memory bus) are both in the system or if ECC is
enabled.
Timing Comments AssertionlNegation-Valid during data transfers (write or read) to or
from memory.
2.2.4.5 'Column Address Strobe (CAS[o-7]}-Output
The eight column address strobe (CAS[0-7]) signals are outputs on the MPC106. CASO
connects to the most-significant byte select. CAS7 connects to the least-significant byte
select. Following are the state meaning and timing comments for the CASn output signals.
State Meaning
Asserted-Indicates that the DRAM (or EDO) column address is
valid and selects one of the columns in the row.
Negated-For DRAMs, indicates CAS precharge; the current
DRAM data transfer has completed.
-orFor EDO DRAMs, indicates CAS precharge; the current data
transfer completes in the first clock cycle of CAS precharge.
Timing Comments Assertion-The MPC 106 asserts CASn two to eight clock cycles
after the assertion of RASn (depending on the setting of the
MCCR3[RCD 2] parameter). See Section 6.3.4, "DRAMIEDO
Interface Timing," for more information.
2.2.4.6SDRAM Clock Enable (CKE)-Output
The SDRAM clock enable (CKE) signal is an ou~ut on the MPC106. Following are the
state meaning and timing comments for the CKE output signal.
State Meaning
Asserted-Enables the internal clock circuit of the SDRAM memory
device. Also, CKE is part of the SDRAM command encoding.
Negated-Disables the internal clock circuit of the SDRAM
memory device. Also, CKE is part of the SDRAM command
encoding. Note that the MPC 106 negates CKE during certain system
power-down situations.
Timing Comments Assertion-CKE is valid on the rising edge of the 60x bus clock. See
Section 6.4, "SDRAM Interface Operation," for more information.
2.2.4.7 SDRAM Command Select (CS[O-7])-Output
The eight SDRAM command select (CS[0--7]) signals are output on the MPC106.
Following are the state meaning and timing comments for the CSn output signals.
State Meaning
Asserted-Selects an SDRAM bank to perform a memory operation.
Negated-Indicates no SDRAM action during the current cycle.
Timing Comments Assertion-The MPC 106 asserts the CSn signal to begin a memory
.cycle. For SDRAM, CSn must be valid on the rising edge of the 60x
bus clock.
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2.2.4.8 SDRAM Data Qualifier (DQM[O-7])-Output
The eight SDRAM data qualifier (DQM[0-7]) signals are outputs on the MPC 106.
Following are the state meaning and timing comments for the DQMn output signals.
State Meaning
Asserted-Prevents writing to SDRAM. (Note that the DQMn
signals are active high for SDRAM.)
Negated-Allows a read or write operation to SDRAM.
DQMO connects to the most significant byte select.
DQM7 connects to the least significant byte select.
Timing Comments Assertion-For SDRAM, DQMn must be valid on the rising edge of
the 60x bus clock during read or write cycles.
2.2.4.9 Flash Output Enable (FOE)-Output
The Flash output enable (FOE) signal is an output on the MPCI06. Following are the state
meaning and timing comments for the FOE output signal.
State Meaning
Asserted-Enables Flash output for the current read access.
Negated-Indicates that there is currently no read access to Flash.
Note that the FOE signal provides no indication of any write
operation(s) to Flash.
Timing Comments Assertion-The MPC 106 asserts FOE at the start of the Flash read
cycle.
2.2.4.10 Memory Address (MA[O-12])-Output
The memory address (MA[0-12]) signals consist of 13 output signals on the MPC106.
Following are the state meaning and timing comments for the MA[0-12] output signals.
State Meaning
AssertedlNegated-Represents the row/column multiplexed
physical address for DRAMs or EDOs (MAO is the most-significant
address bit; MA12 is the least-significant address bit).
Timing Comments Assertion-The row address is valid on assertion of RASn, and the
column address is valid on assertion of CASn.
2.2.4.11 Memory Data Latch Enable (MDLE)-Output
The memory data latch enable (MDLE) signal is an outp\,!t on the MPCI06. Following are
the state meaning and timing comments for the MDLE output signal.
State Meaning
Asserted-MDLE enables an external latched data buffer for read
operations, if such a buffer is used in the system.
Negated-MDLE disables the external latched data buffer, if such a
buffer is used in the system.
Timing Comments Assertion- For systems that use an external data buffer, MDLE
follows CAS timing for DRAM read operations, follows CAS
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Chapter 2. Signal Descriptions
2-29
precharge timing for EDO read operations, and follows RCS[O-l]
timing for ROMIFlash read operations.
2.2.4.12 Data Parity/ECC (PAR[O-7])
The eight data paritylECC (PAR[0-7]) signals are both input and output signals on the
MPC106.
2.2.4.12.1 Data Parity (PAR[O-7])-Output
Following are the state meaning and timing comments for PAR[0-7] as output signals.
State Meaning
AssertedlNegated-Represents the byte parity or ECC being written
to memory (PARO is the most-significant parity bit and corresponds
to byte lane 0 which is selected by CASIDQM[O]). The data parity
signals are asserted or negated as appropriate to provide odd parity
(including the parity bit) or ECC.
Timing Comments AssertionlNegation-PAR[0-7] are valid concurrent with DH[0-31]
and DL[0-31].
2.2.4.12.2 Data Parity (PAR[O-7])-lnput
Following are the state meaning and timing comments for PAR[0-7] as input signals.
State Meaning
AssertedlNegated-Represents the byte parity or ECC being read
from memory (PARO is the most-significant parity bit and
corresponds to byte lane 0 which is selected by CASIDQMO).
TIming Comments AssertionlNegation-PAR[0-7] are valid concurrent with DH[0-31]
and DL[0-31].
2.2.4.13 Parity Path Read Enable (PPEN)-Output
The parity path read enable (PPEN) signal is an output on the MPCI06. Following are the
state meaning and timing comments for the PPEN output signal.
State Meaning
AssertedlNegated-Used to control external parity path buffers
between the 60x bus and memory. See Section 6.2.4, "ParitylECC
Path Read Control," for more information.
Asserted-PPEN enables the parity bus buffer (for flow-through
type buffering) in the memory read path, or acts as the output enable
for the parity bus latch (for latched-type buffering) in the memory
read path.
Negated-PPEN disables the parity bus buffer.
Timing Comments AssertionlNegation-For normal parity or no parity, PPEN is
asserted with the first read CASIDQMn and held valid throughout
the read burst. For ECC, PPEN is asserted with the first read CASn
and negated during the bus turnaround cycle.
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2.2.4.14 Row Address Strobe (RAS[O-7])-Output
The eight row address strobe (RAS[0-7]) signals are outputs on the MPC106. Following
are the state meaning and timing comments for the RASn output signals.
State Meaning
Asserted-Indicates that the memory row address is valid and selects
one of the rows in the selected bank.
Negated-Indicates DRAM precharge period.
Timing Comments Assertion-The MPC 106 asserts the RASn signal to begin a
memory cycle. All other memory interface signal timings are
referenced to RASn.
2.2.4.15 ROM Bank 0 Select (RCSO)-Output
The ROM bank 0 select (RCSO) signal is an output on the MPC 106. Following are the state
meaning and timing comments for the RCSO output signal.
State Meaning
Asserted-Selects ROM bank 0 for a read access or Flash bank 0 for
a read or write access.
Negated-Deselects bank 0, indicating no pending memory access
to ROMIFlash.
Timing Comments Assertion-The MPC 106 asserts RCSO at the start of a ROMIFlash
access cycle.
2.2.4.16 ROM Bank 1 Select (RCS1)-Output
The ROM bank 1 select (RCS 1) signal is an output on the MPC 106. Following are the state
meaning and timing comments for the RCS 1 output signal.
State Meaning
Asserted-Selects ROM bank 1 for a read access or Flash bank 1 for
a read or write access.
Negated-Deselects bank 1, indicating no pending memory access
to ROMIFlash.
Timing Comments Assertion-The MPC 106 asserts RCS 1 at the start of a ROMIFlash
access cycle.
2.2.4.17 Real Time Clock (RTC)-Input
The real time clock (RTC) signal is an input on the MPC 106. Following are the state
meaning and timing comments for the RTC input signal.
State Meaning
AssertedlNegated-RTC is an external clock source for the memory
refresh logic when the MPC106 is in the suspend power-saving
mode.
Timing Comments Assertion-The maximum period of RTC is 114 of the refresh
interval of the DRAM. For example. the minimum frequency for
RTC when using DRAMs with a 125 Ils refresh interval would be
32kHz.
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Chapter 2. Signal Descriptions
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2.2.4.18 SDRAM Internal Bank Select (SDBAO)-Output
The SDRAM internal bank: select (SDBAO) signal is an output signal on the MPCl06.
Following are the state meaning and timing comments for the SDBAO output signal.'
State Meaning
AssertedlNegated-Selects the SDRAM internal bank:
(Low = bank: A, High = bank: B) to be activated during the row
address phase and selects the SDRAM internal bank for the read or
write operation during the column address phase of the memory
access.
Timing Comments Assertion/Negation-The same as SDMA[1-11].
2.2.4.19 SDRAM Column Address Strobe (SDCAS)-Output
The SDRAM column address strobe (SDCAS) signal is an output on the MPC106.
Following are the state meaning and timing comments for the SDCAS output signal.
State Meaning
Asserted-SDCAS is part of the SDRAM command encoding and is
used for SDRAM column selection during read or write operations.
See Section 6.4, "SDRAM Interface Operation," for more
information.
Negated-SDCAS is part of SDRAM command encoding used for
SDRAM column selection during read or write operations.
Timing Comments Assertion-For SDRAM, SDCAS is valid on the rising edge of the
60x bus clock when a CSn signal is asserted.
2.2.4.20 SDRAM Address (SDMA[1-11])-Output
The SDRAM address (SDMA[l-ll]) signals consist of 11 output signals on the MPCl06.
Following are the state meaning and timing comments for the SDMA[1-ll] output signals. '
State Meaning
AssertedlNegated-Represents the row/column multiplexed
physical address for SDRAMs (SDMAI is the most-significant'
address bit; SDMAII is the least-significant address bit).
TIming Comments AssertionlNegation-For SDRAM, the row address is valid on the
rising edge of the 60x bus clock when SDRAS is asserted, and the
column address is valid on the rising edge of the 60x bus clock when
SDCAS is asserted.
2.2.4.21 SDRAM Row Address Strobe (SDRAS)-Output
The SDRAM row address strobe (SDRAS) signal is an output on the MPG106. Following .
are the state meaning and timing comments for the SDRAS output signal.
State Meaning
2-32
AssertedlNegated-SDRAS is part of the SDRAM command
enCOding and is used for SDRAM bank selection during read or write
operations. See Section 6.4, "SDRAM Interface Operation," for
more information.
MPC106 PCIBIMC User's Manual
MOTOROLA
Timing Comments Assertion-SDRAS is valid on the rising edge of the 60x bus clock
when a CSn signal is asserted.
2.2.4.22 Write Enable (WE)-Output
The write enable (WE) signal is an output on the MPC 106. Following are the state meaning
and timing comments for the WE output signal.
State Meaning
Asserted-Enables writing to DRAM, EDO, or Flash.
-or-
For SDRAM, WE is part of the SDRAM command encoding. See
Section 6.4, "SDRAM Interface Operation," for more information.
Negated-No DRAM, EDO, or Flash write operation is pending.
Timing Comments Assertion-For DRAM, the MPCI06 asserts WE concurrent with
the column address and prior to CASn. For SDRAM, the MPC 106
asserts WE concurrent with SDCAS for write operations.
2.2.5 PCI Interface Signals
This section provides descriptions of the PCI interface signals on the MPC106. Note that
throughout this manual, signals and bits of the PCI interface are referenced in little-endian
format.
2.2.5.1 PCI Address/Data Bus (AD[31-O])
Th~
PCI address/data bus (AD[31-O]) consists of 32 signals that are both input and output
signals on the MPCI06.
2.2.5.1.1 Address/Data (AD[31-0])-Output
Following is the state meaning for AD[31-O] as output signals.
State Meaning
AssertedlNegated-Represents the physical address during the
address phase of a PCI transaction. During the data phase(s) of a PCI
transaction, AD[31-O] contain data being written.
The AD [7-0] signals define the least-significant byte and AD [3 1-24]
the most-significant byte.
2.2.5.1.2 Address/Data (AD[31-0])-lnput
Following is the state meaning for AD [3 1-0] as input signals.
State Meaning
AssertedlNegated-Represents the address to be decoded as a check
for device select during the address phase of a PCI transaction or data
being received during the data phase(s) of a PCltransaction.
2.2.5.2 Command/Byte Enable (C/BE[3-0])
The four commandlbyte enable (CIBE[3-O]) signals are both input and output signals on
theMPCI06.
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Chapter 2. Signal Descriptions
2-33
2.2.5.2.1 Command/Byte Enable (C/BE[3-0])-Output
Following is the state meaning for C/BE[3-0] as output signals.
State Meaning
AssertedlNegated-During the address phase, CIBE[3-O] define the
bus command. Table 2-4 specifies the PCI bus command encodings.
See Section 7.3.2, "PCI Bus Commands," for more information.
During the data phase, CIBE[3-O] are used as byte enables. Byte
enables determine which byte lanes carry meaningful data. The
CIBEO signal applies to the least-significant byte.
Table 2-4. PCI Command Encodings
~[3-0)
PCICommand
0000
Interrupt acknowledge
0001
Special cycle
0010
VO read
0011
110 write
0100
Reserved
0101
Reserved
0110
Memory read
0111
Memory write
1000
Reserved
1001
Reserved
1010
Configuration read 1
1011
Configuration write1
1100
Memory read multiple
1101
Dual access cycle 1
1110
Memory read line
1111
Memory write and invalidate
1 The MPC106 does not respond to this command.
2.2.5.2.2 Command/Byte Enable (C/BE[3-0])-lnput
Following is the state meaning for CIBE[3-O] as input signals.
State Meaning
2-34
AssertedlNegated-During the address phase, CIBE[3-O] indicate
the command that another master is sending. Table 2-4 specifies the
PCI bus command encodings. See Section 7.3.2, "PCI Bus
Commands," for more information. During the data phase,
C/BE[3-O] indicate which byte lanes are valid.
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MOTOROLA
2.2.5.3 Device Select (DEVSEL)
The device select (DEVSEL) signal is both an input and output signal on the MPC106.
2.2.5.3.1 Device Select (DEVSEL)-Output
Following is the state meaning for DEVSEL as an output signal.
State Meaning
Asserted-Indicates that the MPC 106 has decoded the address and
is the target of the current access.
Negated-Indicates that the MPC 106 has decoded the address and is
not the target of the current access.
2.2.5.3.2 Device Select (DEVSEL)-Input
Following is the state meaning for DEVSEL as an input signal.
State Meaning
Asserted-Indicates that some PCI agent (other than the MPC 106)
has decoded its address as the target of the current access.
Negated-Indicates that no PCI agent has been selected.
2.2.5.4 Frame (FRAME)
The frame (FRAME) signal is both an input and output signal on the MPCI06.
2.2.5.4.1 Frame (FRAME)-Output
Following is the state meaning for FRAME as an output signal.
State Meaning
Asserted-Indicates that the MPC 106, acting as a PCI master, is
initiating a bus transaction. While FRAME is asserted, data transfers
may continue.
Negated-If IRDY is asserted, indicates that the PCI transaction is
in the final data phase; if IRDY is negated, indicates that the PCI bus
.is idle.
2.2.5.4.2 Frame (FRAME)-Input
Following is the state meaning for FRAME as an input signal.
State Meaning
Asserted-Indicates that another PCI master is initiating a bus
transaction.
Negated-Indicates that the transaction is in the final data phase or
that the bus is idle.
2.2.5.5 PCI Bus Grant (GNT)-Input
The PCI bus grant (GNT) signal is an input signal on the MPC106. Note that GNT is a
point-to-point signal. Every master has its own GNT signal. Following is the state meaning
for the GNT input signal.
State Meaning
MOTOROLA
Asserted-Indicates that the MPCI06 has been granted control of
the PCI bus. If GNT is asserted before the MPC 106 has a transaction
to perform (that is, the MPC106 is parked), the MPC106 drives
Chapter 2. Signal Descriptions
2-35
AD[31-O], CIBE[3-O], and PAR to stable (but meaningless) states
until they are needed for a legitimate transaction.
Negated-Indicates that the MPC 106 has not been granted control of
the PCI bus, and cannot initiate a PCI transaction.
2.2.5.6 Initiator Ready (IROY)
The initiator ready (IRDY) signal is both an input and output signal on the MPC106.
2.2".5.6.1 Initiator Ready (IRDY)-Output
Following is the state meaning for IRDY as an output signal.
State Meaning
Asserted-Indicates that the MPC106, acting as a PCI master, can
complete the current data phase of a PCI transaction. During a write,
the MPC106 asserts IRDY to indicate that valid data is present on
AD[31-O]. During a read, the MPC 106 asserts IRDY to indicate that
it is prepared to accept data.
Negated-Indicates that the PCI target needs to wait before the
MPC 106, acting as a PCI master, can complete the current data
phase. During a write, the MPC106 negates IRDY to insert a wait
cycle when it cannot provide valid data to the target. During a read,
the MPC106 negates IRDY to insert a wait cycle when it cannot
accept data from the target.
2.2.5.6.2 Initiator Ready (IRDY)-Input
Following is the state meaning for IRDY as an input signal.
State Meaning
Asserted-Indicates another PCI master is able to complete the
current data phase of a transaction.
Negated-If FRAME is asserted, indicates a wait cycle from another
master. If FRAME is negated, indicates the PCI bus is idle.
2.2.5.7 Lock (LOCK)-Input
The lock (LOCK) signal is an input on the MPC 106. See Section 7.5, "Exclusive Access,"
for more information. Following is the state meaning for the LOCK input signal.
State Meaning
Asserted-Indicates that a master is requesting exclusive access to
memory, which may require multiple transactions to complete.
Negated-Indicates that a normal operation is occurring on the bus
or an access to a locked target is occurring.
2.2.5.8 Parity (PAR)
The PCI parity (PAR) signal is both an input and output signal on the MPC 106. See
.
Section 7.6.1, "PCI Parity;' for more information.
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MOTOROLA
2.2.5.8.1 Parity (PAR)-Output
Following is the state meaning for PAR as an output signal.
State Meaning
Asserted-Indicates odd parity across the AD[31-O] and
CIBE[3-O] signals during address and data phases.
Negated-Indicates even parity across the AD[31-O] and
CIBE[3-O] signals during address and data phases.
2.2.5.8.2 Parity (PAR)-Input
Following is the state meaning for PAR as an input signal.
State Meaning
Asserted-Indicates odd parity driven by another PCI master or the
PCI target during read data phases.
Negated-Indicates even parity driven by another PCI master or the
PCI target during read data phases.
2.2.5.9 Parity Error (PERR)
The PCI parity error (PERR) signal is both an input and output signal on the MPC106.
2.2.5.9.1 Parity Error (PERR)-Output
Following is the state meaning for PERR as an output signal.
State Meaning
Asserted-Indicates that the MPC 106, acting as a PCI agent,
detected a data parity error. (The PCI initiator drives PERR on read
operations; the PCI target drives PERR on write operations.)
Negated-Indicates no error.
2.2.5.9.2 Parity Error (PERR)-Input
Following is the state meaning for PERR as an input signal.
State Meaning
Asserted-Indicates that another PCI agent detected a data parity
error while the MPC106 was sourcing data (the MPC106 was acting
as the PCI initiator during a write, or was acting as the PCI target
during a read).
Negated-Indicates no error.
2.2.5.10 PCI Bus Request (REQ)-Output
The PCI bus request (REQ) signal is an output signal on the MPC106. Note that REQ is a
point-to-point signal. Every master has its own REQ signal. Following is the state meaning
for the REQ output signal.
State Meaning
Asserted-Indicates that the MPCI06 is requesting control of the
PCI bus to perform"a transaction. If the PCI bus grant (GNT) signal
is asserted before the MPC106 has a transaction to perform (that is,
the MPC106 is parked), then REQ is not asserted.
Negated-Indicates that the MPC 106 does not require use of the PCI
bus.
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Chapter 2. Signal Descriptions
2-37
2.2.5.11 System Error (SERR)
The PCI system error (SERR) signal is bDth an input and output signal on the MPCI06.
2.2.5.11.1 System Error (SERR)-Output
Following is the state meaning for SERR as an output signal.
State Meaning
Asserted-Indicates that an address parity error, a target-abort (when
the MPCI06 is acting as the initiator), or some other system error
(where the result is a catastrophic ertor) was detected.
Negated-Indicates no error.
2.2.5.11.2 System Error (SERR)-Input
Following is the state meaning for SERR as an input signal.
State Meaning
Asserted-Indicates that a target (other than the MPCI06) has
detected a catastrophic error.
Negated-Indicates no error.
2.2.5.12 Stop (STOP)
The stop (STOP) signal is both an input and output signal on the MPCI06.
2.2.5.12.1 Stop (STOP)-Output
Following is the state meaning for STOP as an output signal.
State Meaning
Asserted-Indicates that the MPC 106, acting as a PCI target, is
requesting that the initiator stop the current transaction.
Negated-Indicates that the current transaction can continue.
2.2.5.12.2 Stop (STOP)-Input
Following is the state meaning for STOP as an input signal.
State Meaning
Asserted-Indicates that a target is requesting that the PCI initiator
stop the current transaction.
Negated-Indicates that the current transaction can continue.
2.2.5.13 Target Ready (TROY)
The target ready (TRDY) signal is both an input and output signal on the MPC 106.
2.2.5.13.1 Target Ready (TROV)-Output
Following is the state meaning for TRDY as an output signal.
State Meaning
2-38
Asserted-Indicates that the MPC 106, acting as a PCI target, can
complete the current data phase of a PCI transaction. During a read,
the MPC106 asserts TRDY to indicate that valid data is present on
AD[31-0]. During a write, the MPCI06 asserts TRDY to indicate
that it is prepared to accept data.
MPC106 PCIBIMC User's Manual
MOTOROLA
Negated-Indicates that the PCI initiator needs to wait before the
MPC 106, acting as a PCI target, can complete the current data phase.
During a read, the MPCI06 negates TROY to insert a wait cycle
when it cannot provide valid data to the initiator. During a write, the
MPC106 negates TROY to insert a wait cycle when it cannot accept
data from the initiator.
2.2.5.13.2 Target Ready (TRDY)-Input
Following is the state meaning for TROY as an input signal.
State Meaning
Asserted-Indicates another PCI target is able to complete the
current data phase of a transaction.
Negated-Indicates a wait cycle from another target.
2.2.5.14 PCI Sideband Signals
The PCI specification loosely defines a sideband signal as any signal not part of the PCI
specification that connects two or more PCI-compliant agents, and has meaning only to
those agents. The MPC 106 implements four PCI sideband signals-FLSHREQ,
ISA_MASTER, MEMACK, and PIRQ.
2.2.5.14.1 Flush Request (FLSHREQ)-Input
The flush request (FLSHREQ) signal is an input signal on the MPC106. Following is the
state meaning for the FLSHREQ input signal.
State Meaning
Asserted-Indicates that a device needs to have the MPC106 flush
all of its current operations. FLSHREQ should be asserted when
MEMACK is negated and before FRAME is asserted.
Negated-Indicates normal operation for the MPCI06. FLSHREQ
should be deasserted after FRAME is deasserted.
2.2.5.14.2 ISA Master (ISA_MASTER)-Input
The ISA master (ISA_MASTER) signal is an input signal on the MPC106. This signal is
only valid for address map A; it has no meaning for address map B or for the emulation
mode address map. Following is the state meaning for the ISA_MASTER input signal.
State Meaning
Asserted-Indicates that an ISA master is requesting system
memory. The ISA_MASTER signal is an implied address bit 31 for
ISA devices that cannot drive a full 32-bit address. Accordingly,
when the MPC106 detects ISA_MASTER asserted, it automatically
asserts DEVSEL. Note that due to the automatic assertion of
DEVSEL when ISA_MASTER is asserted, possible bus contention
can occur if the current transaction is not truly intended for the
MPC106 (or system memory behind it).
Negated-Indicates that no ISA master requires system memory.
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Chapter 2. Signal Descriptions
2-39
2.2.5.14.3 Memory Acknowledge (MEMACK)-Output
The memory acknowledge (MEMACK) signal is an output signal on the MPCI06.
Following is the state meaning for the MEMACK output signal.
State Meaning
Asserted-Indicates that the MPC106 has flushed all of its current
operations and has blocked a1l60x transfers except snoop copy-back
operations. The MPCI06 asserts MEMACK in response to the
assertion of FLSHREQ, after the flush is complete.
Negated-Indicates the MPCI06 may still have operations in its
queues. The MPCI06 negates MEMACK two cycles after
FLSHREQ is deasserted.
2.2.5.14.4 Modified Memory Interrupt Request (PIRQ)-Output
The modified memory interrupt request (PIRQ) signal is an output signal on the MPC 106.
The polarity of the PIRQ signal is programmable by using the
ESCRl[PIRQ_ACTIVE_HIGH] parameter; see Section 3.2.9, "Emulation Support
Configuration Registers," for more information. Note that the PIRQ signal is only
meaningful in the emulation mode address map. See Section 7.8, "Emulation Support," for
more information. Following is the state meaning for the PIRQ output signal.
State Meaning
Asserted-Indicates that software has not recorded a PCI to system
. memory write operation.
Negated-Indicates either that software has recorded all PCI to
system memory writes or that no writes have occurred.
2.2.6 Interrupt, Clock, and Power Management Signals
The MPC 106 coordinates interrupt, clocking, and power management signals across the
memory bus, the PCI bus, and the 60x processor bus. This section provides a brief
description of these signals.
2.2.6.1 Test Clock (CKO)-Output
The test clock (CKO) signal is an output on the MPCI06. This signal provides a means to
test or monitor the internal PLL output or the bus clock frequency. The CKO clock should
be used for testing purposes only. It is not intended as a reference clock signal.
2.2.6.2 Hard Reset (HRST)-Input
The hard reset (HRST) signal is an input on the MPC106. Following are the state meaning
and timing comments for the HRST input signal.
State Meaning
Asserted-Initiates a complete hard reset of the MPC 106. During
assertion, all bidirectional signals are released to the high-impedance
state and all output signals are either in a high-impedance or inactive
state.
Negated-Indicates that normal operation should proceed.
Timing Comments Assertion-May occur at any
2-40
ti~e,
asynchronous to SYSCLK.
MPC106 PCIS/MC User's Manual
MOTOROLA
Negation-May occur at any time after the minimum hard reset
pulse width has been met.
2.2.6.3 Nonmaskable Interrupt (NMI)-Input
The nonmaskable interrupt (NMI) signal is an input on the MPC 106. Following are the state
meaning and timing comments for the NMI input signal.
State Meaning
Asserted-Indicates that the MPCI06 should signal a machine
check interrupt to the 60x processor.
Negated-No special meaning.
Timing Comments Assertion-NMI may occur at any time, asynchronous to SYSCLK.
Negation-Should not occur until after the interrupt is taken.
2.2.6.4 Quiesce Acknowledge (QACK)-Output
The quiesce acknowledge (QACK) signal is an output on the MPC106. See Section A.I.I,
"MPC106 Power Mode Transition," for more information about the power management
signals. Following are the state meaning and timing comments for the QACK output signal.
State Meaning
Asserted-Indicates that the MPC106 is in a low-power state. All
bus activity that requires snooping has terminated, and the 60x
processor may enter a low-power state.
Negated-Indicates that the 60x processor should not enter a lowpower state. The MPCI06 is in full-on state with normal bus activity.
Timing Comments Assertion-The MPC I 06 can assert QACK at any time,
synchronous to the 60x bus clock when QREQ is asserted.
Negation-The MPC106 can negate QACK any time, synchronous
to the 60x bus clock.
2.2.6.5 Quiesce Request (QREQ)-Input
The quiesce request (QREQ) signal is an input on the MPC106. See SectionA.l.1,
"MPC106 Power Mode Transition," for more information about the power management
signals. Following are the state meaning and timing comments for the QREQ input signal.
State Meaning
Asserted-Indicates that a 60x processor is requesting that all bus
activity involving snoop operations pause or terminate so that the
60x processor may enter a low-power state.
Negated-Indicates that a 60x processor is in the full-on state.
Timing Comments AssertionlNegation-A 60x processor can assert QREQ at any time,
asynchronous to the 60x bus clock. The MPC 106 synchronizes
QREQ internally.
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Chapter 2. Signal Descriptions
2-41
2.2.6.6 Suspend (SUSPENO)-Input
-
The suspend (SUSPEND) signal is an input on the MPC106. Following are the state
meaning and timing comments for the SUSPEND input signal.
State Meaning
Asserted-Activates the suspend power-saving mode.
Negated-Deactivates the suspend power-saving mode.
Timing Comments Assertion-The SUSPEND signal can be asserted at any time,
asynchronous to the 60x bus clock. The MPC106 synchronizes
SUSPEND internally.
Negation-The .",.,.."""'=..,.,.
SUSPEND signal can be negated at any time,
asynchronous to the 60x bus clock, as long as it meets the timing
requirements for turning the PLL and external clock on and off when
entering and exiting suspend mode.
2.2.6.7 System Clock (SYSCLK)-Input
The system clock (SYSCLK) signal is an input on the MPCI06. The SYSCLK signal sets
the frequency of operation for the PCI bus, and provides a reference clock for the phaselocked loops in the MPC106. SYSCLK is used to synchronize bus operations. See
Section 2.3, "Clocking," for more information.
2.2.7 IEEE 1149.1 Interface Signals
To facilitate system testing, the MPC 106 provides a JTAG test access port (TAP) that
complies with the IEEE 1149.1 boundary-scan specification. This section describes the
JTAG test access port signals.
2.2.7.1 JTAG Test Clock (TCK)-Input
The JTAG test clock (TCK) signal is an input on the MPC 106. Following is the state
meaning for the TCK input signal.
.
State Meaning
AssertedlNegated-This input should be driven by a free-running
clock signal with a 50% duty cycle. Input signals to the test access
port are clocked in on the rising edge of TCK. .Changes to the test
access port output signals occur on the falling edge of TCK. The test
logic allows TCK to be stopped.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
2.2.7.2 JTAG Test Data Output (TOO)-Output
Following is the state meaning for the TDO output signal.
State Meaning
2-42
AssertedlNegated-The contents of the selected internal instruction
or data register are shifted out onto this signal on the falling edge of
TCK. The IDO signal will remain in a high-impedance state except
when scanning of data is in progress.
MPC106 PCIBIMC User's Manual
MOTOROLA
2.2.7.3 JTAG Test Data Input (TOI)-Input
Following is the state meaning for the TDI input signal.
State Meaning
AssertedlNegated-The value presented on this signal on the rising
edge of TCK is clocked into the selected JTAG test instruction or
data register.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
2.2.7.4 JTAG Test Mode Select (TMS)-Input
The test mode select (TMS) signal is an input on the MPC106. Following is the state
meaning for the TMS input signal.
State Meaning
AssertedlNegated-This signal is decoded by the internal JTAG TAP
controller to distinguish the primary operation of the test support
circuitry.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
2.2.7.5 JTAG Test Reset (TRST)-Input
The test reset (TRST) signal is an input on the MPC 106. Following is the state meaning for
the TRST input signal.
State Meaning
Asserted-This input causes asynchronous initialization of the
internal JTAG test access port controller. During power-on reset, the
system should assert TRST to reset the JTAG control logic.
Negated-Indicates normal operation.
Note that this input contains an internal pull-up resistor to ensure that
an unterminated input appears as a high signal level to the test logic.
2.2.8 Configuration Signals
The MPCI06 has several signals that are sampled during power-on reset to determine the
configuration of the ROM, Flash, and dynamic memory, and the phase-locked loop clock
mode. This section describes the signals sampled during power-on reset, and how they are
configured. Weak pull-up or pull-down resistors should be used to avoid interference with
normal signal operations.
2.2.8.1 Address Map (OBGO)-Input
The address map configuration signal uses DBGO as a configuration input. Following is the
state meaning for the DBGO configuration signal.
State Meaning
High-Configures the MPC106 for address map A.
Low-Configures the MPCI06 for address map B.
See Section 3.1, ''Address Maps," for more information.
MOTOROLA
Chapter 2. Signal Descriptions
2-43
2.2.8.2 ROM Bank 0 Data Path Width (FOE)-Input
The ROM bank 0 data path width configuration signal uses FOE as a configuration input.
Following is the state meaning for the FOE configuration signal.
State Meaning
High~onfigures
ROM bank 0 for an 8-bit data path.
Low~onfigures
ROM bank 0 for a 64-bit data path.
2.2.8.3 Clock Mode (PLL[O-3])-lnput
The clock mode (PLL[~3]) configuration signals are dedicated inputs on the MPC106.
Following is the state meaning for the PLL[~3] configuration signals.
State Meaning
HighILow~onfigures
the operation of the PLL and the internal
clock (core) frequency. Settings are based on the desired PCI bus and
core frequency of operation. See Section 2.3, "Clocking," for more
information.
2.2.8.4 ROM Location (RCSO)-Input
The ROM location configuration signal uses RCSO as a configuration input. Following is
the state meaning for the RCSO configuration signal.
State Meaning
High-Indicates that ROM is located on the 60x processor/memory
bus.
Low-Indicates that ROM is located on the PCI bus. Note that the
parameter, PICR2[CF_FFO_LOCAL], may be used to remap the
lower half of ROM space (OxFFOO_000--OxFF7F_FFFF) back to the
60x processor/memory bus. 'See Section 6.5, "ROM/Flash Interface
Operation," for more information.
2.3 Clocking
The MPC106 requires a single system clock input, SYSCLK. The SYSCLK frequency
dictates the frequency of operation for the PCI bus. An internal PLL on the MPC 106
generates a master clock that is used for all of the internal (core) logic. The master clock
provides the core frequency reference and is phase-locked to the SYSCLK input. The 60x
processor, L2 cache, and memory interfaces operate at the core frequency.
The internal PLL on the MPC106 generates a core frequency either equal to the SYSCLK
frequency (xl), twice (x2), or three times (x3) the frequency of SYSCLK (see Figure 2-2)
depending on the clock mode configuration signals (PLL[0-3]). The core frequency is
phase-locked to the rising edge of SYSCLK. Note that SYSCLK is not required to have a
50% duty cycle.
2-44
MPC106 PCIBIMC User's Manual
MOTOROLA
SYSCLK
'----_I
~
,-----,rI
(xl)
~
I
I
(x2)
(x3)
Figure 2-2. SYSCLK Input with Internal Multiples
The PLL is configured by the PLL[0-3] signals. For a given SYSCLK (PCI bus) frequency,
the clock mode configuration signals (PLL[O-3]) set the core frequency (and the frequency
of the VCO controlling the PLL lock). The supported core and VCO frequencies and the
corresponding PLL[0-3] settings are provided in the MPCI06 hardware specifications.
MOTOROLA
Chapter 2. Signal Descriptions
2-45
Chapter 3
Device Programming
The programmable aspects of the MPC 106 are primarily for use by initialization and error
handling software. This chapter describes the selectable address maps and the configuration
registers on the MPC106.
3.1 Address Maps
The MPC106 supports three address mapping configurations designated address map A,
address map B, and emulation mode map. Address map A conforms to the PowerPC
reference platform specification. Address map B conforms to the PowerPC microprocessor
common hardware reference platform (CHRP). The emulation mode map is provided to
support software emulation of x86 hardware.
The configuration signal DBGO, sampled during power-on reset, selects between address
map A and address map B. Map A is selected by using a pull-up resistor (DBGO = 1); map
B is selected by using a pull-down resistor (DBGO = 0). After reset, the address map can be
changed by programming PICR1[ADDRESS_MAP].
Emulation mode map can only be selected by software after reset by programming
ESCR1[EMULATION_MODE_EN].
3.1.1 Address Map A
Address map A complies with the PowerPC reference platform specification. The address
space of map A is divided into four areas-system memory, PCI 110, PCI memory, and
system ROM space. Table 3-1, Table 3-2, and Table 3-3 show separate views of address
map A for the 60x processor, a PCI memory device, and a PCI 110 device, respectively.
When configured for map A, the MPC 106 translates addresses across the 60x and PCI buses
as shown in Figure 3-1 through Figure 3-4.
Map A can be configured as contiguous or discontiguous by PICR1[XIO_MODE]. The
discontiguous map reserves a 4-Kbyte page for each 32-byte block addressed on the PCI
bus allowing each 32-byte block from 0 to 64KB - 1 in PCI 110 space to have distinct page
protection attributes. This can help when accessing PC-compatible 110 devices in the
ISAlPCIIIO space address 0 to 64KB - 1. The contiguous map as seen from the processor
is shown in Figure 3-1. The discontiguous map as seen from the processor is shown in
Figure 3-2.
MOTOROLA
Chapter 3. Device Programming
3-1
Table 3-1. Address Map A-Processor View
&Ox Processor Address Range
PCI Address Range
Definition
Decimal
Hex
00000000
3FFFFFFF
0
1G-1
NoPClcycle
System memory space
40000000
7FFFFFFF
1G
2G-1
No PCI cycle
Reserved 1
80000000
S07FFFFF
2G
2G+8M-1
0~7FFFFF
PCI/ISA 110 space
(64 Kbytes or
8 Mbytes)2.3
8080000O
SOFFFFFF
2G+8M
2G + 16M-1
O~FFFFFF
PCI configuration
direct access4
81000000
BF7FFFFF
2G+16M
3G-8M-1
01000000-3F7FFFFF
PCI 1/0 space
BF800000
BFFFFFEF
3G-8M
3G-16-1
3F800000-3FFFFFEF
Reserved
BFFFFFFO
BFFFFFFF
3G-16
3G-1
3FFFFFF0-3FFFFFFF
PCIIISA interrupt
acknowledgeS
COOOOOOO
FEFFFFFF
3G
4G-16M-1
OOOOOOOQ-3EFFFFFF
PCI memory space
FFoooooO
FFFFFFFF
4G-16M
4G-1
No PCI cycleS
ROM spaces
Table 3-2. Address Map A-PCI Memory Master View
PCI Memory Transactions Address Range
60x Address Range
Definition
Decimal
Hex
00000000
OOFFFFFF
0
16M-1
No system memory cycle7
PCIIISA memory space
01000000
7EFFFFFF
16M
2G-16M-1
No system memory cycle7
PCI memory space
Reserved
System memory space
7Foooooo
7FFFFFFF
2G-16M
2G-1
No system memory cycle7
800000OO
FFFFFFFF
2G
4G-1
0000000Q-7FFFFFFF
3-2
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-3. Address Map A-PCIIIO Master View
peltlo Transactions Address Range
60x Address Range
00000000
ooOOFFFF
Definition
Decimal
Hex
0
64K-1
No system memory cycle
ISAlPCIIIO space
No system memory cycle
Reserved
00010000
007FFFFF
64K
8M-1
00800000
3F7FFFFF
8M
1G-8M-1
No system memory cycle
PCI 1/0 space
3F800ooo
3FFFFFFF
1G-8M
1G-1
No system memory cycle
Reserved
40000000
FFFFFFF
1G
4G-1
No system memory cycle
Reserved
Notes:
1. The MPC106 generates a memory select error (if enabled) for transactions in the address range
400oooQO-7FFFFFFF.lf memory select errors are disabled. the MPC106 returns all1s for read
operations and no update for write operations.
2. PCI configuration accesses to CF8 and CFC-CFF are handled as specified in the PCI Local Bus
Specification. See Section 7.4.5. "Configuration Cycles," for more information.
3. Processor addresses are translated to PCI addresses as follows:
In contiguous mode:
PCI address (AD[31-O]) = ObO II A[1-31J. PCI configuration accesses use processor addresses
80000CF8and8oo00cFc-80000CFF.
In discontiguous mode:
PCI address (AD[31-O]) = OXOOOO II A[9-19JII A[27-31J. PCI configuration accesses use
processor addresses 80067018 and 8006701 c-8006701 F.
4. IDSEL for direct-access method: 11 =Ox808008xx. 12=Ox808010xx•...• 18=Ox808400xx.
5. Reads to this address generate PCI interrupt-acknowledge cycles; writes to this address generate TEA
(if enabled).
6. If the ROM is located on the PCI bus. these addresses are not reserved and PCI cycles will be
generated.
7. If the "IS"A'_"i"Mi"iA"'S""T'"'E""R signal is asserted. the PCI memory cycle is forwarded to system memory and the
60x bus address becomes ObOO II AD[29-0J.
MOTOROLA
Chapter 3. Device Programming
3-3
MPC106
SOx Processor
Not forwarded
to PCI bus
System
memory
Reserved
Memory controller
performs system
memory access
-------
1GB
Memory select error
PCI I/O Space
0
PCI I/O addresses
in 0 to 64KB - 1 range
------
64KB
Unaddressable
byPCI I/O
------
+ 8MB
8MB
PCI configuration
8MB to 16MB-1
16MB
8MB
Clear A31 (msb) and
change 60x bus
cycle to PCI I/O cycle
1GB-8MB
lGB-l
PCI Memory Space
Clear A31 and A30
and change 60x
bus cycle to
PCI memory cycle
PCI memory space
------
16MB
-------
-- ....
PClmemory
cycIo
1GB-16MB
Decodes ROM/Flash
space and performs
ROMlFlash ROM access
or register access
System ROM space
(ROM or Flash)
-1
0
PClmemory
space in range
o to 1GB -16MB-1
------
1GB-16MB
Unaddressable
as PCI memory
lGB-l
lGB-l
Figure 3-1. Address Map A (Contiguous Map)
3-4
MPC106 PCIB/MC User's Manual
MOTOROLA
MPC106
0
Not forwarded
to PCI bus
....
System
memory
Reserved
Memory controller
performs system
memory access
-------
1GB
Memory select error
2GB -1
PCI 1/0 Space
0
PCIIISA bus port
(discontiguous
8 Mbytes)
.....
Modify address
xOOOO II A[9-19~1I A[27-3
and chanBe Ox bus
cycle to P I 1/0 cycle
-------
2GB + 8MB
PCI configuration
direct access
-
-
-
-
-
-
-
2GB+16M B
PCI I/O space
IPClIIOcydo
PCIIISA 1/0 addresses
in 0 to 64KB - 1 range
------
641<8
Unaddressable
byPClllO
8 MB
------
8MB
PCI configuration
8MB to 16MB-1
Clear A31 (msb) and
change 60x bus
cycle to PCI 1/0 cycle
8MB
1GB-l
0
...
PCI memory space
-------
4GB-16M B
System ROM space
(ROM or Flash)
L-_ _ _ _ _ _- - ' 4GB-l
Clear A31 and A30
and change 60x
bus cycle to
PCI memory cycle
.....
---
PClmomory
cydo
PCI Memory Space
.-------~~~--'o
PClmemory
space in range
Oto 1 GB-16MB-1
1GB-I8MB
Decodes ROMIFlash
space and performs
ROM/Flash access
or register access
1GB-18MB
Unaddressable
as PCI memory
1GB-l
L---------------....I1GB-l
Figure 3-2. Address Map A (Oiscontiguous Map)
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Chapter 3. Device Programming
3-5
PCI Master
Ia
PCiJlSA memory space
in Oto 2GB-16MB-1
-------
16MB
PClmemory
PCI memory space in
16MB to 2GB -16MB-1
Reserved
cycles
Ignored.
Not forwarded
to system memory
or the SOx bus
2GB-16MB
System memory space
in range 2GB to 3GB - 1
SySan
memory
cydeo
3GB
2GB
0
3GB
1GB
System memory
addresses in 2GB to
3GB - 1 range.
Forwarded with AD31
complemented so
logic can decide
to snoop. Memory
controller performs
system memory access.
------Memory select error
4GB-l
L-_ _ _- ' -_ _ _---J 4GB-l
Figure 3-3. PCI Memory Map (Address Map A)
3-6
MPC106 PCIBIMC User's Manual
MOTOROLA
Reserved
PCI
I/O
MPC106
Not forwarded to
system memory
PCI/ISA flO sface in
range
oto 64 KB -
64KB
64KB
Unaddressable by
system I/O
Unaddressable by
system I/O
-------
8MB
I/O configuration
8 MB to 16 MB - 1
-
______
8MB
Nol forwarded to
system memory
16MB
PCI I/O space in
8 MB to 1 GB - 8MB - 1
range
PCII/O cycles
1GB-8MB
1GB
4GB-l
1GB-8MB
1GB
4GB-l
Figure 3-4. PCI 1/0 Map (Address Map A)
3.1.2 Address Map B
Address map B complies with the PowerPC microprocessor common hardware reference
platform (CHRP). As with address map A, the address space of map B is divided into four
areas-system memory, PCI memory, PCI I/O, and system ROM space. When configured
for map B, the MPC106 translates addresses across the 60x and PCI buses as shown in
Figure 3-5. Table 3-4, Table 3-5, and Table 3-6 show separate views of address map B for
the 60x processor, a PCI memory device, and a PCI I/O device, respectively.
MOTOROLA
Chapter 3. Device Programming
3-7
Table 3-4. Address Map B-Processor View
60x Processor Address Range
PCI Address Range
Definition
Decimal
Hex
00000000
0009FFFF
0
640K-1
No PCI cycle
System memory space
ooOAOOOO
OOOBFFFF
640K
768K-1
OOOAOOOO-OOOBFFFF
Compatibility hole 1
OOOCOOOO
3FFFFFFF
768K
1G -1
No PCI cycle
System memory space
40000000
7FFFFFFF
1G
2G-1
No PCI cycle
Reserved 2
80000000
FCFFFFFF
2G
4G-48M-1
8000oo0Q-FCFFFFFF
PCI memory space
FDooOOOO
FDFFFFFF
4G-48M
4G-32M-1
OOOOooOO-OOFFFFFF
PCI/ISA memory space3
FEOOooOO
FE7FFFFF
4G -32M
4G -24M-1
OOOOOooO-OOOOFFFF
PCIIISA 1/0 space
(64 Kbytes or 8 Mbytes)4
FE800000
FEBFFFFF
4G -24M
4G-20M-1
00800oo0-00BFFFFF
PCI 1/0 space5
FECOoooo
FEDFFFFF
4G-20M
4G-18M-1
CONFIG_ADDR
PCI configuration
address registerEI
FEEOOOOO
FEEFFFFF
4G -18M
4G -17M-1
CON FIG_DATA
PCI configuration data
register7
FEFOOOOO
FEFFFFFF
4G -17M
4G -16M-1
FEFOOOOQ-FEFFFFFF
PCI interru pt
acknowledge8
FFooOOOO
FF7FFFFF
4G -16M
4G-8M-1
FFOOOooQ-FF7FFFFF
64-bit system ROM
space9
FF80oo00
FFFFFFFF
4G-8M
4G-1
FF8oo00Q-FFFFFFFF
8- or 64-bit system ROM
space 9
Table 3-5. Address Map B-PCI Memory Master View
PCI Memory Transaction Address Range
60x Address Range
Definition
Decimal
Hex
00000000
0009FFFF
0
640K-1
0000000O-OO09FFFF
System memory space
OooAOOOO
OOOFFFFF
640K
1M-1
OOOAOOOo-oooFFFFF
Compatibility hole1
00100000
3FFFFFFF
1M
1G -1
001000OQ-3FFFFFFF
System memory space
40000000
7FFFFFFF
1G
2G-1
4000oo0Q-7FFFFFFF
Reserved2
80000000
FCFFFFFF
2G
4G-48M-1
No system memory cycle
PCI memory space
FDooOOOO
FDFFFFFF
4G-48M
4G-32M-1
OooOOOOO-OOFFFFFF
System memory space10
FEOooOOO
FEFFFFFF
4G-32M
4G-16M-1
No system memory cycle
Reserved
FFOOOOOO
FF7FFFFF
4G -16M
4G-8M-1
FFOooOOQ-FF7FFFFF
64-bit system ROM
space9
3-8
MPC106 PCIBIMCUser's Manual
MOTOROLA
Table 3-5. Address Map B-PCI Memory Master View (Continued)
PCI Memory Transaction Address Range
60x Address Range
FFSOOooO
Definition
Decimal
Hex
1 FFFFFFFF
4G-SM
14G-1
FF8oo00o-FFFFFFFF
8- or S4-bit system ROM
space9
Table 3-6. Address Map B-PCI VO Master View
PCIIIO Transaction Address Range
60x Address Range
Hex
Definition
Decimal
00000000
ooOOFFFF
0
S4K-1
No system memory cycle
PCI/ISA I/O space
00010000
oo7FFFFF
64K
SM-1
No system memory cycle
Reserved
00800000
ooBFFFFF
8M
12M-1
No system memory cycle
PCII/Ospace
ooCOooOO
FFFFFFFF
12M
4G-1
No system memory cycle
Reserved
Notes:
1. Transactions in the compatibility hole address range are controlled by the PCLCOMPATIBILITY_HOLE
and PROC...:COMPATIBILITY_HOLE parameters in emulation support configuration register 1 (ESCR1).
The MPC10S directs the transaction to system memory or PCI memory, depending on these parameters.
See Section 3.2.9, "Emulation Support Configuration Registers," for more information.
2. The MPC10S generates a memory select error (if enabled) for transactions in the address range
40000000-7FFFFFFF.lf memory select errors are disabled, the MPC10S returns all1s for read
operations and no update for write operations.
3. The MPC10S forwards SOx transactions in this range to the PCI memory space with the S
most-significant bits cleared (that is, AD[31-o] =OxOO II A[8-31]).
4. Processor addresses are translated to PCI addresses as follows:
In contiguous mode:
PCI address (AD[31-o]) =OxOO II A[8-31]. Note that in contiguous mode, the processor
range FE01000o-FE7FFFFF is reserved.
In discontiguous mode:
PCI address (AD[31-o]) =OxOooo II A[9-19]II A[27-31].
5. The MPC10S forwards SOx transactions in this range to the PCII/O space with the 8 most-significant bits
cleared (that is, AD[31-o] =Oxoo II A[8-31]).
S. Each word in this address range is aliased to the PCI CONFIG_ADDR register. See Section 7.4.5.2,
"Accessing the PCI Configuration Space," for more information.
7. Each word in this address range is aliased to the PCI CONFIG_DATA register. See Section 7.4.5.2,
"Accessing the PCI Configuration Space," for more information.
S. Reads from this address generate PCI interrupt-acknowledge cycles; writes to this address generate
TEA (if enabled).
9. The ROMIFlash space may be located on the SOx/memory bus, on the PCI bus, or on both. See
Section S.5, "ROMIFlash Interface Operation:' for more information.
10.lf ESCR1[FD_ALlAS_EN] =1, the MPC10S forwards PCI memory transactions in this range to system
memory with the S most-Significant bits cleared (that is, OXOO II AD[23-0]).
MOTOROLA
Chapter 3. Device Programming
3-9
Processor View
System memory
640K
System memory
---------
1M
System memory
16M
0,---_ _ _ _--,
640K
---------Compatibility hole
768K
PCI Master 110 View
PCI Master Memory View
0.-----_ _ _ _-,
0
Compatibility hole
________ _
System memory
----------
16M
System memory
System memory
PClmemory
PClmemory
lG
2G
4~
4G-48M
48M
System memory1
(o-16M)
4G-32M
4G-17M
4G-16M
PCllntAck
4G-16M
System ROM space
(ROM
Flash)
4G '--_
_or_
_--'
Note: This view can be disabled.
•
Reserved
Figure 3-5. Address Map B
3-10
MPC106 PCIB/MC User's Manual
MOTOROLA
3.1.3 Emulation Mode Address Map
The emulation mode address map is actually a subset of address map B that has a
programmable boundary, as seen by the PCI bus, between the system memory space and
the PCI memory space. The emulation mode address map is fully compliant with the PC
emulation option described in the CHRP specification.
When configured for the emulation mode address map, the MPC 106 translates addresses
across the 60x and PCI buses as shown in Figure 3-6. Table 3-7, Table 3-8, and Table 3-9
show separate views of the emulation mode address map for the 60x processor, a PCI
memory device, and a PCI 110 device, respectively. See Section 7.8, "Emulation Support,"
for more information about emulation mode.
Table 3-7. Emulation Mode Address Map-Processor View
60x Processor Address Range
PCI Address Range
Hex
Definition
Decimal
00000000
oo09FFFF
0
640K-1
No PCI cycle
System memory space
oooAoooO
OOOBFFFF
640K
768K-1
ooOAOOOO-OOOBFFFF
Compatibility hole1
OOOCOOOO
3FFFFFFF
768K
1G -1
No PCI cycle
System memory space
40000000
7FFFFFFF
1G
2G-1
No PCI cycle
Reserved2
80000000
FCFFFFFF
2G
4G-48M-1
8oo0oo0Q-FCFFFFFF
PCI memory space
FDooOooo
FDFFFFFF
4G-48M
4G-32M-1
OOOOOOOO-OOFFFFFF
PCI/ISA memory space3
FEOooOoo
FE7FFFFF
4G-32M
4G-24M-1
OOOOooOO-OOOOFFFF
PCI/ISA 1/0 space
(64 Kbytes or 8 Mbytes)4
FE8oo000
FEBFFFFF
4G-24M
4G-20M-1
00800000-00BFFFFF
PCI 1/0 spaceS
FECooOoo
FEDFFFFF
4G-20M
4G-18M-1
CONFIG_ADDR
PCI configuration
address registerS
FEEOOOOO
FEEFFFFF
4G-18M
4G-17M-1
CONFIG_DATA
PCI configuration data
register7
FEFOOooo
FEFFFFFF
4G-17M
4G -16M-1
FEFOOOOQ-FEFFFFFF
PCI interrupt
acknowledgeS
FFOOOOOO
FF7FFFFF
4G -16M
4G-8M-1
FFOOOOOQ-FF7FFFFF
64-bit system ROM
space9
FF800000
FFFFFFFF
4G-8M
4G-1
FF8000OQ-FFFFFFFF
8- or 64-bit system ROM
space 9
MOTOROLA
Chapter 3. Device Programming
3-11
Table 3-8. Emulation Mode Address Map-PCI Memory Master View
PCI MemoryTransaction Address Range
SOx Address Range
Definition
Decimal
Hex
00000000
0009FFFF
0
640K-1
00000000-Q009FFFF
System memory space
OOOAOOOO
OOOFFFFF
640K
1M-1
OOOAOOOO-QOOFFFFF
Compatibility hole 1
00100000
Programmable10
1M
Programmable 10
0010000o-Programmable 10
System memory space 10
Programmable 10
FFFFFFFF
Programmable 10
4G-l
No system memory cycle
PCI memory space 10
Table 3-9. Emulation Mode Address Map-PCIIIO Master View
PCI VO Transaction Address Range
60x Address Range
00000000
OOOOFFFF
Definition
Decimal
Hex
0
64K-l
No system memory cycle
PCI/ISA 1/0 space
00010000
007FFFFF
64K
8M-l
No system memory cycle
Reserved
00800000
OOBFFFFF
8M
12M-1
No system memory cycle
PCllIOspace
OOCOOOOO
FFFFFFFF
12M
4G-1
No system memory cycle
Reserved
Notes:
1. Transactions in the compatibility hole address range are controlled by the PC,-COMPATIBILITY_HOLE
and PROC_COMPATIBILlTY_HOLE parameters in emulation support configuration register 1 (ESCR1).
The MPC106 directs the transaction to system memory or PCI memory, depending on these parameters.
See Section 3.2.9, "Emulation Support Configuration Registers;' for more information.
2. The MPC106 generates a memory select error (if enabled) for transactions in the address range
400000OD-7FFFFFFF." memory select errors are disabled, the MPC106 returns allIs for read
operations and no update for write operations.
3. The MPC106 forwards 60x transactions in this range to the PCI memory space with the 8
most-significanlbits cleared (that is, AD[31-Q] = OxOO II AIB-31]).
4. Processor addresses are translated to PCI addresses as follows:
In contiguous mode:
PCI address (AD[31-0]) = OxOO II A[8-31]. Note that in contiguous mod.e, the processor
range FE01000o-FE7FFFFF is reserved.
In discontiguous mode:
PCI address (AD[31-Q]) = OxOOOO II A[9-19] II A[27-31].
5. The MPCl 06 forwards 60x transactions in this range to the PCI I/O space with the a most-significant bits
cleared (that is, AD[31-Q] OxOO II A[a-31]).
=
6. Each word in this address range is aliased to the PCI CONFIG_ADDR register. See Section 7.4.5.2,
"Accessing the PCI Configuration Space; for more information.
7
3-12
Each word in this address range is aliased to the PCI CONFIG_DATA register. See Section 7.4.5.2,
"Accessing the PCI Configuration Space;' for more information.
MPC106 PCIB/MC User's Manual
MOTOROLA
8. Reads from this address generate PCI interrupt-acknowledge cycles; writes to this address generate
TEA (if enabled).
9. The ROMIFlash space may be located on the SOx/memory bus, on the PCI bus, or on both. See
Section 6.5, "ROM/Flash Interface Operation," for more information.
10. The emulation mode allows system software to configure the PCI memory address space by
programming the parameter ESCR1[TOP_OF_MEM). The MPC106 claims PCI memory transactions
addressed from 00100000 to oxe II TOP_OF_MEM II FFFFF and forwards the transactions to system
memory. The MPC1 06 does not claim PCI memory transactions addressed from OxO II TOP_OF_MEM +
1 II 00000 to FFFFFFFF; other PCI memory targets claim transactions in this range. 60x
processor-ta-PCI transactions are unaffected by the value in TOP_OF_MEM.
MOTOROLA
Chapter 3. Device Programming
3-13
Processor View
0,--_.,.--_ _---,
PCI Master Memory View
0,--_-,----_ _---,
System memory
PCI Master 110 View
0.--_ _ _ _ _--,
System memory
640K
640K
Compatibility hole
Compatibility hole
1M _________ _
768K
-
-'- --
System memory
System memory
16M
System memory
TM1
1G
2G
PClmemory
PClmemory.
4G-48M
4G-32M
PCIIISA memory
(D-16M)
TPM&BIO
4G-20M
4G-18M
4G-17M
4G-16M
ROM space
or Flash)
4G '--_ _ _ _--'
Note: Top of memory is programmable in emulation mode.
•
Reserved
Figure 3-6. Emulation Mode Address Map
3·14
MPC106 PCIBIMC User's Manual
MOTOROLA
3.2 Configuration Registers
This section describes the programmable configuration registers of the MPCI06. These
registers are generally set up by initialization software following a power-on reset or hard
reset, or by error handling routines. All the internal registers of the MPCI06 are
intrinsically little-endian. In the following register descriptions, bit 0 is the least-significant
bit of the register.
Any reserved bits in the following register descriptions are not guaranteed to have
predictable values. Software must preserve the values of reserved bits when writing to a
configuration register. Also, when reading from a configuration register, software should
not rely on the value of any reserved bit remaining consistent.
3.2.1 Configuration Register Access
When using address map A, the MPC 106 configuration registers are accessed by an indirect
method similar to accessing PCI device configuration registers. The 32-bit register address
(Ox8000_00nn, where nn is the address offset of the desired configuration register-see
Table 3-10 and Figure 3-7) is written to CONFIG_ADDR at Ox8000_0CF8 (Ox8006_7018
in discontiguous mode). Then, the data is accessed at CONFIG_DAT at addresses
Ox8000_OCFC-Ox8000_OCFF (Ox8006_701C-Ox8006_701F in discontiguous mode).
When using address map A, certain configuration bits for the MPC 106 can also be accessed
at the addresses Ox8000_0092, Ox8000_081C, and Ox8000_0850. These are compatible
with the example system described by the PowerPC reference platform specification. See
Section 3.2.10, "External Configuration Registers," for more information.
When using address map B or emulation mode address map, the MPC 106 uses a similar
indirect method to access the internal configuration registers-the exception is that
CONFIG_ADDR and CONFIG_DATA are found at different addresses. The 32-bit register
address (Ox8000_00nn, where nn is the address offset of the desired configuration
register-see Table 3-10 and Figure 3-7) is written to CONFIG_ADDR at any
word-aligned address in the range OxFECO_OOOO--OxFEDF_FFFF. Every word within this
range is aliased to the same location. Then, the data is accessed at CONFIG_DAT at any
address in the range OxFEEO_OOOO--OxFEEF_FFFF. Every word within this range is aliased
to the same location.
3.2.1.1 Configuration Register Access in Little-Endian Mode
In little-endian mode (both processor and the MPCI06), the program should access the
configuration registers using the methods described in Section 3.2.1, "Configuration
Register Access." The data appears in the 60x processor register in descending significance
byte order (MSB to LSB) at the time it is stored to the MPCI06. For the indirect-access
method, the configuration register address in the processor register should appear (as data
appears) in descending significance byte order (MSB to LSB) at the time it is stored to the
MPCI06.
MOTOROLA
Chapter 3. Device Programming
3-15
Example: Map A configuration sequence, 4-byte data write to register at. address offset
OxA8
Initial values:rO contains Ox8000_00A8
rl contains Ox8000- OCF8
r2 contains OxAABB_CCDD
Register at OxA8 contains OxFFFF_FFFF (AB to A8)
Code sequence: stw rO,O(rl)
stw r2,4(rl)
Address Ox8000_0CF8 contains Ox8000_00A8 (MSB to LSB)
Results:
Register at OxA8 contains OxAABB_CCDD (AB to A8)
Example: Map A configuration sequence, 2-byte data write to register at address offset
OxAA
Initial values:rO contains Ox8000_00A8
rl contains Ox8000_0CF8
r2 contains OxAABB_CCDD
Register at OxA8 contains OxFFFF_FFFF (AB to A8)
Code sequence: stw rO,O(rl)
sth
r2,6(rl)
Results:
Address Ox8000_0CF8 contains Ox8000_00A8 (MSB to LSB)
Register at OxA8 contains OxCCDD_FFFF (AB to A8)
Note that in this example, the value Ox8000_00A8 is the configuration address register, not
Ox8000_00AA. The address offset OxAA is generated by using Ox8000_OCFE for the data
access.
Example: Map A configuration sequence, I-byte data read from register at address offset
OxA9
Initial values:rO contains Ox8000_00A8
rl contains Ox8000_0CF8
Register at OxA8 contains OxAABB_CCDD (AB to A8)
Code sequence: stw
rO,O(rl)
Ibz
r2, 5 (rl)
Results:
Address Ox8000_0CF8 contains Ox8000_00A8 (MSB to LSB)
r2 contains Oxoooo_oecc
3-16
MPC106 PCIBIMC User's Manual
MOTOROLA
Example: Map B or emulation mode address map configuration sequence, 4-byte data
write to register at address offset OxA8
Initial values:rO contains Ox8000_00A8
rl contains OxFECO_OOOO
r2 contains OxFEEO_OOOO
r3 contains OxAABB_CCDD
Register at OxA8 contains OxFFFF_FFFF (AB to A8)
Code sequence: stw rO,O(rl)
stw r3,O(r2)
Address OxFECO_OOOO contains Ox8000_00A8 (MSB to LSB)
Results:
Register at OxA8 contains OxAABB_CCDD (AB to A8)
Example: Map B or emulation mode address map configuration sequence, I-byte data
write to register at address offset OxAA
Initial values:rO contains Ox8000_00A8
rl contains OxFECO_OOOO
r2 contains OxFEEO_OOOO
r3 contains OxAABB_CCDD
Register at OxA8 contains OxFFFF_FFFF (AB to A8)
Code sequence: s tw - rO, 0 (rl )
sth
r3,O(r2)
Address OxFECO_OOOO contains Ox8000_00A8 (MSB to LSB)
Results:
Register at OxA8 contains OxFFDD_FFFF (AB to A8)
3.2.1.2 Configuration Register Access in Big-Endian Mode
In big-endian mode (both the processor and the MPC106), software must byte-swap the
data of the configuration register before performing an access. That is, the data appears in
the processor register in ascending significance byte order (LSB to MSB). When using
either address map (A, B, or emulation mode), software-loads the configuration register
address and the configuration register data into the processor register in ascending
significance byte order (LSB to MSB).
Note that in the following examples, the data in the configuration register (at OxA8) is
shown in little-endian order. This is because all the internal registers are intrinsically
little-endian.
MOTOROLA
Chapter 3. Device Programming
3-17
Example: Map A configuration sequence, 4-byte data write to register at address offset
OxA8
Initial values:rO contains OxA800- 0080
rl contains Ox8000 - OCF8
r2 contains OxODCC_BBAA
Register at OxA8 contains OxFFFF_FFFF (AB to A8)
Code sequence: stw rO,O(rl)
stw r2, 4 (rl)
Address Ox8000_0CF8 contains Ox8000_00A8 (MSB to LSB)
Results:
Register at OxA8 contains OxAABB_CCDD (AB to A8)
Example: Map B or emulation mode address map configuration sequence, 2-byte data
.
write to register at address offset OxAA
Initial values:rO contains OxA800_0080
rl contains OxFECO_OOOO
r2 contains OxFEEO_OOOO
r3 contains OxDDCC_BBAA
Register at OxA8 contains OxFFFF_FFFF (AB to A8)
Code sequence: stw rO,O(rl)
sth r3,2(r2)
Address OxFECO_OOOO contains Ox8000_00A8 (MSB to LSB)
Results:
Register at OxA8 contains OxAABB_FFFF (AB to A8)
3·18
MPC106 PCIBIMC User's Manual
MOTOROLA
3.2.2 Configuration Register Summary
Table 3-10 describes the configuration registers provided by the MPC106. Note that any
configuration addresses not defined in Table 3-10 are reserved.
Table 3-10. MPC106 Configuration Registers
Program·
Accessible
Size
Address
Offset
(in Hex)
Register
Size
00
2 bytes
2 bytes
Vendor ID =1057h
Read
Ox1057
02
2 bytes
2 bytes
Device ID = 0002h
Read
OxOOO2
04
2 bytes
2 bytes
PCI command
Read/write
OxOOO6
06
2 bytes
2 bytes
PCI status
Read/bit-reset
Ox0080
08
1 byte
1 byte
Revision ID
Read
Oxnn
09
1 byte
1 byte
Standard programming interface
Read
OxOO
OA
1 byte
1 byte
Subclass code
Read
OxOO
OB
1 byte
1 byte
Class code
Read
Ox06
OC
1 byte
1 byte
Cache line size
Read
Ox08
OD
1 byte
1 byte
Latency timer
Read
OxOO
OE
1 byte
1 byte
Header type
Read
OxOO
OF
1 byte
1 byte
BIST control
Read
OXOO
3C
1 byte
1 byte
Interrupt line
Read
OxOO
3D
1 byte
1 byte
Interrupt pin
Read
OXOO
3E
1 byte
1 byte
MINGNT
Read
OxOO
3F
1 byte
1 byte
MAXGNT
Read
OXOO
40
1 byte
1 byte
Bus number
Read
OxOO
41
1 byte
1 byte
Subordinate bus number
Read/write
OxOO
Register
Register
Access
Default Value
42
1 byte
1 byte
Disconnect counter
Read
oxOO
44
2 bytes
2 bytes
Special cycle address
Read
OxOOOO
70
2 bytes
1 or 2 bytes
Power management configuration 1
Readlwrite
OxOOOO
72
1 byte
1 byte
Power management configuration 2
Read/write
OxOO
73
1 byte
1 byte
Reserved
Read/write
OxCD
8Q-87
8 bytes
1, 2, or 4 bytes
Memory starting address
Read/write
OxOOOO_OOOO
88-8F
8 bytes
1, 2, or 4 bytes
Extended memory starting address
Read/write
OxOOOO_OOOO
90-97
8 bytes
4 bytes
Memory ending address
Readlwrite
OxOOOO_OOOO
98-9F
8 bytes
1, 2, or 4 bytes
Extended memory ending address
Read/write
OXOOOO_OOOO
AO
1 byte
1 byte
Memory bank enable
Read/write
OxOO
MOTOROLA
Chapter 3. Device Programming
3·19
Table 3-10. MPC106 Configuration Registers (Continued)
Program·
Accessible
Size
Address
Offset
(hi Hex)
Register
Size
A3
1 byte
1 byte
Memory page mode
Read/write
OxOO·
A8
4 bytes
1, 2, or 4 bytes
Processor interface configuration 1
Read/write
OxFFOO_0010
AC
4 bytes
1, 2, or 4 bytes
Processor interface configuration 2
Read/write
OXOOOC_060C
B8
1 byte
1 byte
ECC single-bit error counter
Readlwrite
OxOO
B9
1 byte
1 byte
ECC single-bit error trigger
Readlwrite
OxOO
BA
1 byte
1 byte
Alternate
Read/write
Ox04
BB
1 byte
1 byte
Alternate
Read/write
OxOO
CO
1 byte
1 byte
Error enabling 1
Read/write
Ox01
C1
1 byte
1 byte
Error detection 1
Readlbit-reset
OxOO
C3
1 byte
1 byte
60x bus error status
Read/bit-reset
OxOO
C4
1 byte
1 byte
Error enabling 2
Read/write
OxOO
C5
1 byte
1 byte
Error detection 2
Readlbit-reset
OxOO
C7
1 byte
1 byte
PCI bus error status
Readlbit-reset
OxOO
C8-CB
4 byte
4 bytes
60X/PCI error address
Read
OxOOOO_OOOO
EO
4 bytes
1, 2, or 4 bytes
Emulation support configuration 1
Read/write
OxOFFF_0042
E4
4 bytes
1, 2, or 4 bytes
Modified memory status
Read (no clear)
OxOOOO_OOOO
E8
4 bytes
1, 2, or 4 bytes
Emulation support configuration 2
Read/write
OxOOOO_0020
EC
4 bytes
1,2, or 4 bytes
Modified memory status
Read (clear)
OxOOOO_OOOO
FO
4 bytes
1,2, or 4 bytes
Memory control configuration 1
Read/write
OxFFn2_0000
F4
4 bytes
1,2, or4 bytes
Memory control configuration 2
Read/write
OxOOOO_0003
F8
4 bytes
1,2, or4 bytes
Memory control configuration 3
Read/write
OxOOOO_OOOO
FC
.4 bytes
1, 2, or 4 bytes
Memory control configuration 4
Read/write
Ox0010_0000
Register
as visible parameters 1
as visible parameters 2
Register
Access
Default Value
Figure 3-7 shows the MPCI06 configuration space.
3-20
MPC106 PCIB/MC User's Manual
MOTOROLA
Address
Offset (Hex)
Illi!] Reserved
~----------------------------.---------------------------~
~------------~--~-------+------------~--~--------~
~----------~-------------+-------------.------------~
~----------~-------------+------~--~-+------------~
--------------~------------~------------~
--------------~------------~
00
04
08
DC
3C
40
44
80
~--------------------------------------------------------~
~----------------------------------------------------~
r-----------------------------------------------------~
r-----------------------------------------------------~
r-----------------------------------------------------~
r-----------------------------------------------------~
--------------1
84
88
8C
90
94
98
9C
AD
A4
r-----------------------------------------------------~
A8
AC
B8
BC
-------------+--------~--__i
--------------~------------~
r-----------------------------------------------------~
r-----------------------------------------------------~
~--------------------------------------------------------~
~------------------------~~--~~------------------4
~--------------------~------~----------------------4
~--------------------~------~----------------~----4
CO
C4
C8
EO
E4
E8
EC
FO
F4
~--------------~~~~~~~~----------------~F8
L-______________~~~~~~~~______________~FC
Figure 3-7. MPC106 Configuration Space
MOTOROLA
Chapter 3. Device Programming
3-21
3.2.3 PCI Registers
The PCI Local Bus Specification defines the configuration registers from OxOO through
Ox3F. Additionally, the host bridge architecture section of the PCI System Design Guide
defines the bus number register (Ox40), the subordinate bus number register (Ox41), and the
disconnect counter register (Ox42).
With the exception of the PCI command, PCI status, and subordinate bus number registers,
all of thePCI registers are read-only on the MPC106. Table 3-11 summarizes the PCI
configuration registers of the MPC 106. Detailed descriptions of these registers are provided
in the PCI Local Bus Specification.
Table 3-11. PCI Configuration Space Header Summary
Address
Offset
Description
Register Name
=Motorola)
00
Vendor 10
Identifies the manufacturer of the device (Ox1057
02
Device ID
Identifies the particular device (OxOO02
04
PCI command
Provides coarse control over a device's ability to generate and respond
to PCI bus cycles (see Section 3.2.3.1, "PCI Command Register:' for
more information)
06
PCI status
Records status information for PCI bus-related events (see
Section 3.2.3.2, "PC I Status Register:' for more information)
08
Revision ID
Specifies a device-specific revision code (assigned by Motorola)
09
Standard programming
interface
Identifies the register-level programming interface
of the MPC106 (OxOO)
OA
Subclass code
Identifies more specifically the function of the MPC106
(OxOO host bridge)
OB
Base class code
Broadly classifies the type of function the MPC106 performs
(Ox06 bridge device)
OC
Cache line size
Specifies the system cache line size
00
Latency timer
Specifies the value of the latency timer for this bus master in PCI bus
clock units
OE
Header type
Bits Q-6 identify the layout of bytes 10-3F; bit 7 indicates a multifunction
device. The MPC106 uses the most common header type (OxOO)
OF
BIST control
Optional register for control and status of built-in self test (BIST)
10-33
Reserved on the MPC106
34-3B
-
3C
Interrupt line
Contains interrupt line routing information
3D
Interrupt pi n
Indicates which interrupt pin the device (or function) uses
(OxOO no interrupt pin)
3E
MINGNT
Specifies the length of the device's burst period
(OxOO indicates that the MPC106 has no major requirements for the
settings of latency timers)
3-22
=MPC106)
=
=
Reserved for future use by PCI
=
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 3-11. PCI Configuration Space Header Summary (Continued)
Address
Offset
Description
Register Name
3F
MAXLAT
Specifies how often the device needs to gain access to the PCI bus
(OXOO indicates that the MPC106 has no major requirements for the
settings of latency timers)
40
Bus number
Identifies the assigned bus number of the MPC106
(OXOO = host bridge)
41
Subordinate bus
number
Identifies the bus number beneath the MPC106 bridge
42
Disconnect counter
Specifies the timer for target-disconnect timeout
(OXOO = the timer is disabled)
43
-
Reserved on the MPC106
3.2.3.1 PCI Command Register
The 2-byte PCI command register, shown in Figure 3-8, provides control over the ability to
generate and respond to PCI cycles. Table 3-12 describes the bits of the PCI command
register.
III Reserved
Memory-Write-and-Invalidate - - - - - - - - ,
r - - - - - Special-Cycles
,...---- Bus Master
Memory Space
I/O Space
Parity Error Response - - - - - ,
SERR
Fast Back-to-Back
10 9
15
8
7
6
5
4
3
2
1
0
Figure 3-8. PCI Command Register
Table 3-12. Bit Settings for PCI Command Register-Ox04
Name
Bit
Reset.
Value
Description
15-10
-
AliOs
These bits are reserved.
9
Fast back-to-back
0
This bit is hardwired. to 0, indicating that the MPC106 (as a master)
does not run fast back-ta-back transactions.
8
SERR
0
This bit controls the SERR driver of the MPC1 06. This bit (and bit 6)
must be set to report address parity errors.
0 Disables the 'SE'RR driver
1 Enables the SERR driver
7
-
0
This bit is reserved.
MOTOROLA
Chapter 3. Device Programming
3-23
Table 3-12. Bit Settings for PCI Command Register-Ox04 (Continued)
BH
Name
Reset
Value
Description
6
Parity error
response
0
This bit controls whether the MPC106 responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Action is taken on a parity error. See Chapter 9, "Error
Handling," for more information.
S
-
0
This bit is reserved.
4
Memory-write-andinvalidate
0
This bit is hardwired to 0, indicating that the MPC106, acting as a
master does not generate the memory-write-and-invalidate
command. The MPC106 generates a memory-write command
instead.
3
Special-cycles
0
This bit is hardwired to 0, indicating that the MPC106 (as a target)
ignores all special-cycle commands.
2
Bus master
1
This bit controls whether the MPC106 can act as a master on the
PCI bus. Note that if this bit is cleared, 60x to PCI writes will cause
the data to be lost and SOx to PCI reads will assert TEA (provided
the TEA....EN bit in PICR1 is set).
0 Disables the ability to generate PCI accesses
1 Enables the MPC106 to behave as a PCI bus master
1
Memory space
1
This bit controls whether the MPC106 (as a target) responds to
memory accesses.
0 The MPC106 does not respond to PCI memory space
accesses.
1 The MPC106 responds to PCI memory space accesses.
0
1/0 space
0
This bit is hardwired to 0, indicating that the MPC106 (as a target)
does not respond to PCI va space accesses.
3.2.3.2 pel Status Register
The 2-byte PCI status register, shown in Figure 3-9, is used to record status information for
PCI bus-related events. The definition of each bit is given in Table 3-13. Only 2-byte
accesses to address offset Ox06 are allowed.
Reads to this register behave normally. Writes are slightly different in that bits can be
cleared, but not set. A bit is cleared whenever the register is written, and the data in the
corresponding bit location is a 1. For example, to clear bit 14 and not affect any other bits
in the register, write the value ObOI00_0000_0000_0000 to the register.
3-24
MPC106 PCIBIMC User's Manual
MOTOROLA
III
Received Target-Abort - - - - - ,
Received Master-Abort - - - - ,
Signaled System Error
Detected Parity Error
Reserved
, . . . - - - - - - - - Signaled Target-Abort
, - - - - - - - DEVSEL Timing
, - - - - - - Data Parity Detected
, - - - - - Fast Back-to-Back Capable
66-MHz Capable
15 14 13 12 11 10 9
8
7
6
5
4
o
Figure 3-9. PCI Status Register
Table 3-13. Bit Settings for PCI Status Register-Ox06
Bit
·Name
Reset
Value
Description
15
Detected parity
error
0
This bit is set whenever the MPC1 06 detects a parity error, even if
parity error handling is disabled (as controlled by bit 6 in the PCI
command register).
14
Signaled system
error
0
This bit is set whenever the MPC106 asserts SEAR.
13
Received
master-abort
0
This bit is set whenever the MPC106, acting as the PCI master,
terminates a transaction (except for a special-cycle) using
master-abort.
12
Received
target-abort
0
This bit is set whenever an MPC1 06-initiated transaction (excluding a
special-cycle) is terminated by a target-abort.
11
Signaled
target-abort
0
This bit is set whenever the MPC106, acting as the PCI target, issues
a target-abort to a PCI master.
10-9
DEVSEL timing
00
These bits are hardwired to ObOO, indicating that the MPC106 uses
fast device select timing.
S
Data parity
detected
0
This bit is set upon detecting a data parity error. Three conditions
must be met for this bit to be set:
• The MPC106 detected a parity error.
• MPC106 was acting as the bus master for the operation in which
the error occurred.
• Bit 6 in the PCI command register was set.
7
Fast back-to-back
capable
1
This bit is hardwired to 1, indicating that the MPC106 (as a target) is
capable of accepting fast back-to-back transactions.
6
-
0
This bit is reserved.
5
66-MHz capable
0
This bit is read-only and indicates that the MPC106 is not capable of
66-MHz PCI bus operation.
4-0
-
00000
These bits are reserved.
MOTOROLA
Chapter 3. Device Programming
3-25
3.2.4 Power Management Configuration Registers (PMCRs)
The power management configuration registers (PMCRs) control the power management
functions of the MPC 106.
Power management configuration register 1 (PMCR1), shown in Figure 3-10, is a 2-byte
register located at offset Ox70. Some of the bits in PMCRI configure the MPCI06 to use
the distinct power management features of different 60x processors. Table 3-14 describes
the bits ofPMCRl.
III Reserved
SUSP_QACK
60CNEED_QREQ
NO_604_RUN
LP_REF_EN
SLEEP_MSG_TYPE
NO_SLEEP_MSG
NO_NAP_MSG
---------,
------,
------,
-----,
--..,
r--------PM
r - - - - - - DOZE
.....-----NAP
r - - - - SL.EEP
CKO~MODE
BR1_WAKE
15 14 13 12 11 10 9 8
7 6 5 4 3
2 1 0
Figure 3-10. Power Management Configuration Register 1 (PMCR1)
Table 3-14. Bit Settings for Power Management Configuration
Register 1-ox70
Bit
Name
Reset
Value
Description
15
NO_NAP_MSG
0
HALT command broadcast
0 Indicates that the MPC1 06 broadcasts a HALT command onto
the PCI bus prior to entering the nap mode
1 Indicates that the MPC106 does not broadcast a HALT
command on the PCI bus prior to entering the nap mode
14
NO_SLEEP_MSG
0
Sleep message broadcast
0 Indicates that the MPC106 broadcasts a sleep message
command on the PCI bus prior to entering the sleep mode
1 . Indicates that the MPC106 does not broadcast a sleep
message command on the PCI bus prior to entering the sleep
mode
The sleep message will be either a SHUTDOWN or HALT
command as determined by PMCR1 [SLEEP_MSG_TYPE).
13
SLEEP_MSG_TYPE
0
Sleep message type
0 Indicates that the MPC106 broadcasts a HALT command onto
the PCI bus prior to entering the sleep mode
1 Indicates that the MPC106 broadcasts a SHUTDOWN
command onto the PCI bus prior to entering the sleep mode
Note that the sleep message will be broadcast only if
PMCR1 [NO_SLEEP_MSG) = O.
3-26
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-14. Bit Settings for Power Management Configuration
Register 1-Ox70 {Continued}
Name
Bit
Reset
Value
Description
12
LP_REF_EN
0
Low-power refresh
0 Indicates that the MPC106 does not perform memory refresh
cycles when it is in sleep or suspend mode
1 Indicates that the MPC106 continues to perform memory
refresh cycles when in sleep or suspend mode
11
NO_604_RUN
0
When both a PowerPC 6O4™ microprocessor and the MPC106
are in nap mode and the MPC106 is woken up by a PCI
transaction that accesses system memory, this bit controls
whether the MPC106 asserts the OACK signal so the 604 can
respond to the snoop (QACK is connected to the RUN signal on
the 604). Note that the MPC106 ignores NO_604_RUN unless
PICR1 [PROC_TYPE] =Ob11, indicating a 604.
0 Indicates that the MPC106 asserts the OACK signal
1 Indicates that the MPC106 does not assert the OACK signal
10
601_NEED_QREQ
0
Indicates whether the MPC106 should use the
signal as
one of the conditions for entering the nap/sleep state when a
PowerPC 601 ™ microprocessor is used in the system. Note that
the MPC106 ignores 601_NEED_QREQ unless
PICR1 [PROCJYPE] =ObOO, indicating a 601.
0 Indicates that the QREQ signal is not required
1 Indicates that the QREQ signal is required
9
SUSP_QACK
0
Indicates whether the MPC106 asserts the QACK signal when
entering the suspend power saving mode.
0 Indicates that the MPC106 does not assert the OACK signal
when entering the suspend power saving mode
1 Indicates that the MPC106 asserts OACK when entering the
suspend power saving mode
8
-
0
This bit is reserved.
7
PM
0
Power management enable
0 Disables the power management logic within the MPC106
1 Enables the power management logic within the MPC106
6
-
0
This bit is reserved.
5
DOZE
0
Enables/disables the doze mode capability of the MPC106. Note
that this bit is only valid if MPC106 power management is enabled
(PMCR1[PM] =1).
0 Disables the doze mode
1 Enables the doze mode
4
NAP
0
Enables/disables the nap mode capability of the MPC106. Note
that this bit is only valid if MPC106 power management is enabled
(PMCR1[PM] =1).
0 Disables the nap mode
1 Enables the nap mode
MOTOROLA
om:o
Chapter 3. Device Programming
3-27
Table 3-14. Bit Settings for Power Management Configuration
Register 1-Ox70 (Continued)
Bit
Name
Reset
Value
SLEEP
3
0
Description
Enables/disables the sleep mode capability of the MPC106. Note
that this bit is only valid if MPC106 power management is enabled
(PMCR1[PM] 1).
0 Disables the sleep mode
1 Enables the sleep mode
=
2-1
CKO_MODE
00
Selects the clock source for the test clock output.
00 Disables the test clock output driver
01 Selects the internal (core) clock as the test clock output
source
10 Selects one-half of the internal (core) dock as the test clock
output source
11 Selects SYSCLK as the test dock output source
0
BR1_WAKE
0
Enables/disables awareness of a second, third, or fourth
processor for nap and sleep modes.
0 Indicates the MPC106 will not awaken from nap or sleep
mode when BAT, 1m2, or BFI3 is asserted
1 Indicates the MPC106wili awaken from nap or sleep mode
when mIT, m:i2, or BR3 is asserted in a multiprocessor
configuration
Power management configuration register 2 (PMCR2), shown in Figure 3-11, is a I-byte
register located at offset Ox72. Table 3-15 describes the bits ofPMCR2.
III Reserved
765
4
321
0
Figure 3-11. Power Management Configuration Register 2 (PMCR2)
Table 3-15. Bit Settings for Power Management Configuration Register 2-Ox72
Bit
Name
Reset
Value
Description
7-1
-
AliOs
These bits 'are reserved.
0
SHARED_MCP
0
This bit allows the MPC106 to share the MCP Signal with another
device that might drive J.ifCP.
0 The MPC106 always drives the JVlCJ5 signal.
1 The MPC106 drives the MCP signal when there is an error to
report. Otherwise, the MCP signal.is released to a
high-impedance state.
3-28
MPC106PCIBIMC User's Manual
MOTOROLA
3.2.5 Error Handling Registers
Chapter 9, "Error Handling," describes specific error conditions and how the MPC106
responds to them. The registers at offsets OxB8, OxB9, and OxCO through OxCB control the
error handling and reporting for the MPC106. The following sections provide descriptions
of these registers.
3.2.5.1 ECC Single-Bit Error Registers
The ECC single-bit error registers are two 8-bit registers used to control the reporting of
ECC single-bit errors. See Chapter 9, "Error Handling," for more information. The ECC
single-bit error counter, shown in Figure 3-12, maintains a count of the number of single-bit
errors that have been detected. Table 3-16 describes the bits of the ECC single-bit error
counter.
ECC Single-Bit Error Counter
o
7
Figure 3-12. ECC Single-Bit Error Counter Register-OxB8
Table 3-16. Bit Settings for ECC Single-Bit Error Counter Register-OxB8
Bit
7-4)
Name
EGG single-bit error
counter
Reset
Value
Description
AliOs
These bits maintain a count of the number of EGG single-bit errors
that have been detected and corrected. If this value equals the value
contained in the EGG single-bit error trigger register, then an error
will be reported (provided ErrEnR1[2] = 1).
The ECC single-bit error trigger, shown in Figure 3-13, provides a threshold value, that,
when equal to the single-bit error count, triggers the MPC106 error reporting logic.
Table 3-17 describes the bits of the ECC single-bit error trigger.
I
7
ECC Single-Bit Error Trigger
I
0
Figure 3-13. ECC Single-Bit Error Trigger Register-OxB9
Table 3-17. Bit Settings for ECC Single-Bit Error Trigger Register-OxB9
Bit
7-4)
Name
EGG single-bit error
trigger
MOTOROLA
Reset
Value
AliOs
Description
These bits provide the threshold value for the number of EGG
single-bit errors that are detected before reporting an error condition.
Chapter 3. Device Programming
3-29
3.2.5.2 Error Enabling Registers
Error enabling registers 1 and 2 (ErrEnR1 and ErrEnR2), shown in Figure 3-14 and
Figure 3-15, control whether the¥PC106 recognizes and reports specific error conditions.
Table 3-18 describes the bits of ErrEnR1 and Table 3-19 describes the bits of ErrEnR2.
Memory Refresh Overflow Enable - - - - - - ,
Memory Select Error Enable - - - - - - ,
PCI Target PERR Enable
PCI Received Target-Abort Enable
765
4
r-----r-----
PCI Master PERR Enable
Memory Parity/ECC Enable
. - - - - PCI Master-Abort Error Enable
60x Bus Error Enable
321
0
Figure 3-14. Error Enabling Register 1 (ErrEnR1)
Table 3-18. Bit Settings for Error Enabling Register 1 (ErrEnR1)-OxCO
Reset
Value
Bit
Name
7
PCI received
target-abort enable
0
This bit enables the reporting of target-abort errors that occur on the
PCI bus for transactions involving the MPC106 as a master.
0 Received PCI target-abort error disabled
1 Received PCI target-abort error enabled
6
PCI target PERR
enable
0
This bit enables the reporting of data parity errors on the PCI bus for
transactions involving the MPC106 as a target.
0 Target ~ disabled
1 Target ~ enabled
5
Memory select error
enable
0
This bit enables the reporting of memory select errors that occur on
(attempted) accesses to system memory.
0 Memory select error disabled
1 Memory select error enabled
4
Memory refresh
overflow enable
0
This bit enables the reporting of memory refresh overflow errors.
0 Memory refresh overflow disabled
1 Memory refresh overflow enabled
3
PCI master PERR
enable
0
This bit enables the reporting of data parity errors on the PCI bus for
transactions involving the MPC106 as a master.
0 Master J5ERR disabled
1 Master PERR enabled
2
Memory
parity/ECC enable
0
Thi" bit enables the reporting of system memory read parity errors
that occur on accesses to system memory or exceeding the ECC
single-bit error threshold.
0 Memory read paritylECC single-bit threshold disabled
1 Memory read paritylECC single-bit threshold enabled
3-30
Description
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-18. Bit Settings for Error Enabling Register 1 (ErrEnR1)-OxCO (Continued)
Bit
Name
Reset
Value
Description
1
PCI master-abort
error enable
0
This bit enables the reporting of master-abort errors that occurred on
the PCI bus for transactions involving the MPC106 as a master.
0 PCI master-abort error disabled
1 PCI master-abort error enabled
0
60x bus error
enable
1
This bit enables the reporting of 60x bus errors.
0 60x bus error disabled
1 60x bus error enabled
[I]
L2 Parity Error Enable
Illegal L2 Copy-back Error Enable
PCI Address Parity Error Enable
Reserved
, . . . - - - - - - ECC Multibit Error Enable
Flash ROM Write Error Enable
765
4
321
0
Figure 3-15. Error Enabling Register 2 (ErrEnR2)
Table 3-19. Bit Settings for Error Enabling Register 2 (ErrEnR2}-OxC4
Bit
Name
Reset
Value
Description
7
PCI address parity
error enable.
0
This bit controls whether the MPC106 asserts MCP (provided MCP
is enabled) if an address parity error is detected by the MPC106
when acting as a target.
0 PCI address parity errors disabled
1 PCI address parity errors enabled
6
-
0
This bit is reserved.
5
Illegal L2 copy-back
error enable
0
This bit controls whether an error is reported when the L2 cache
attempts a copy-back to PCI memory space or ROM/Flash space.
0 Disabled
1 Enabled
4
L2 parity error enable
0
This bit enables parity generation and parity error detection for the
internally-controlled L2 cache. Note that parity checking must be
enabled (MICR1[PCKEN) = 1) to detect L2 parity errors.
0 L2 parity disabled
1 L2 parity enabled
3
ECC multibit error
enable
0
This bit enables the detection of ECC mullibit errors.
0 ECC multi bit error detection disabled
1 ECC multibit error detection enabled
MOTOROLA
Chapter 3. Device Programming
3-31
Table 3-19. Bit Settings for Error Enabling Register 2 (ErrEnR2)-OxC4 (Continued)
Name
Bit
Reset
Value
Description
2-1
-
00
These bits are reserved.
0
Flash ROM write error
enable
0
This bit controls whether the MPC106 detects attempts to write to
Flash when either PICR1[FLASH_WR_EN] 0 or
PICR2[FLASH_WR_LOCKOUT] = o.
0 Disabled
1 Enabled
=
..
3.2.5.3 Error Detection Registers
Error detection registers 1 and 2 (ErrDRI and ErrDR2), shown in Figure 3-16 and
Figure 3-17, contain error flags that report when the MPC 106 detects a specific error
condition.
The error detection registers are bit-reset type registers. That is, reading from these registers
occurs normally; however, write operations are different in that bits (error flags) can be
cleared, but not set. A bit is cleared whenever the register is written, and the data in the
corresponding bit location is a 1. For example, to clear bit 6 and not affect any other bits in
the register, write the value ObOIOO_OOOO to the register. When the MPCI06 detects an
error, the appropriate error flag is set. Subsequent errors will set the appropriate error flags
in the error detection registers, but the bus error status and error address are not recorded
until the previous error flags are cleared.
Table 3-20 describes the bits of error detection register 1 and Table 3-21 describes the bits
of error detection register 2.
Memory Refresh Overflow Error - - - - - ,
Memory Select Error - - - - - .
PCI target PERR - - - ,
PCISERR
765
4
, - - - - - - 60X/PCI Cycle
. - - - - - Memory Read Parity Errorl
ECC Single-Bit Error Exceeded
Unsupported 60x Bus Cycle
321
0
Figure 3-16. Error Detection Register 1 (ErrDR1)-OxC1
3-32
MPC106 PCIS/MC User's Manual
MOTOROLA
Table 3-20. Bit Settings for Error Detection Register 1 (ErrDR1 r-oxC1
Bit
Name
Reset
Value
Description
7
PCISERR
0
Note that for the MPC106 to recognize the assertion of SERR by
another PCI agent, bit 5 (RX_SERR_EN) of the alternate OS-visible
parameters register 1 must be set. See Table 3-43 for a description
of the RX_SERR_EN bit.
0 No error signaled
1 Error signaled
6
PCI target PERR
0
PCI target J5"rnR
0 The MPC106, as a PCI target, has not detected a data parity
error
1 The MPC106, as a PCI target, detected a data parity error
5
Memory select error
0
Memory select error
0 No error detected
1 Memory select error detected
4
Memory refresh
overflow error
0
Memory refresh overflow error
0 No error detected
1 Memory refresh overflow has occurred
3
60X/PCI cycle
0
60X/PCI cycle
0 Error occurred on a 60x-initiated cycle
1 Error occurred on a PCI-initialed cycle
2
Memory read parity
error/ECC single-bit
error trigger exceeded
0
Memory read parity error/ECC single-bit error trigger exceeded
0 No error detected
1 Parity error detected or ECC single-bit error trigger exceeded
1- 0
Unsupported 60x bus
cycle
00
Unsupported 60x bus cycle
00 No error detected
01 Unsupported transfer attributes
10 XATS detected
11 Reserved
iII
Reserved
, . - - - - - ECC Multibit Error
L2 Parity Error
Illegal L2 Copy-Back Error
Invalid Error Address
Flash ROM Write Error
765
4
3
2
t
0
Figure 3·17. Error Detection register 2 {ErrDR2r-oxC5
MOTOROLA
Chapter 3. Device Programming
3-33
Table 3-21. Bit Settings for Error Detection Register 2 (ErrDR2}-OxC5
Bit
Name
Reset
Value
Description
7
Invalid error address
0
This bit indicates whether the address stored in the 60X/PCI error
address register is valid.
0 The address in the SOX/PCI error address register is valid.
1 The address in the SOX/PCI error address register is not valid.
6
-
0
This bit is reserved.
5
Illegal L2 copy-back
error
0
Illegal L2 copy-back error
0 No error detected
1 Illegal L2 copy-back (L2 copy-back to PCI or ROM/Flash space)
error detected
4
L2 parity error
0
L2 parity error
0 No error detected
1 L2 parity error detected
3
ECC multi bit error
0
ECC multi bit error
0 No error detected
1 ECC multi bit error detected
2-1
0
-
00
Flash ROM write error
These bits are reserved.
Flash ROM write error
0 No error detected
1 The MPC106 detected a write to Flash ROM when writes to
Flash ROM are disabled.
0
3.2.5.4 Error Status Registers
The error status registers latch the state of the 60x or PCI address bus when an error is
detected; see Figure 3-18, Figure 3-19, and Figure 3-20. These registers provide system
status for error handling software.
Table 3-22 describes the bits of the 60x bus error status register, Table 3-23 describes the
bits of the PCI bus error status register, and Table 3-24 describes the bits of 60xIPCI error
address register.
.------....---f.G--,
:=J
TT[0-4)
7
3 2
TSIZO[0-2]
o
Figure 3-18. 60x Bus Error Status Register-OxC3
3-34
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-22. Bit Settings for 60x Bus Error Status Register-OxC3
Name
Bit
Reset
Value
Description
7-3
TT[0-4)
00000
These bits maintain a copy of TT[0-4). When a 60x bus error is
detected, these bits are latched until all error flags are cleared.
2~
TSIZ[o-2)
000
These bits maintain a copy of TSIZ[o-2). When a 60x bus error is
detected, these bits are latched until all error flags are cleared.
III Reserved
. MPC106 Master/Target Status - - - - - - - ,
7
r - - - - C7BE[3-0]
o
543
Figure 3-19. PCI Bus Error Status Register-OxC7
Table 3-23. Bit Settings for PCI Bus Error Status Register-OxC7
Bit
Name
Reset
Value
Description
7-5
-
000
These bits are reserved.
4
MPC106
masterltarget status
0
MPC106 masterltarget status
0 MPC106 is the PCI master
1 MPC106 is.the PCI target
3-0
~[3-0]
0000
These bits maintain a copy of ~[3-0]. When a PCI bus error is
detected, these bits are latched until all error flags are cleared.
60X/PCI Error Address
o
31
Figure 3-20. 60xIPCI Error Address Register-OxC8
MOTOROLA
Chapter 3. Device Programming
3-35
Table 3-24. Bit Settings for 60xIPCI Error Address Register-oxC8
Bit
Reset
Value
Name
Description
OXOO
A[24-31) or AD[7-o) (dependent upon whether the error is a SOx bus
error or a PCI bus error). When an error is detected, these bits are
latched until all error flags are cleared.
23-16
OxOO
A[16-23) or AD[15-8) (dependent upon whether the error is a 60x
bus error or a PCI bus error). When an error is detected, these bits
are latched until all error flags are cleared.
15-8
OXOO
A[8-15) or AD[23-16) (dependent upon whether the error is a 60x
bus error or a PCI bus error). When an error is detected, these bits
are latched until all error flags are cleared.
7-0
OXOO
A[o-7) or AD[31-24) (dependent upon whether the error is a 60x bus
error or a PCI bus error). When an error is detected, these bits are
latched until all error flags are cleared.
31-24
Error address
3.2.6 Memory Interface Configuration Registers
The memory interface configuration registers (MICRs) control memory boundaries
(starting and ending addresses), memory bank enables, memory timing, and external
memory buffers. Initialization software must program the MICRs at power-on reset and
then enable the memory interface on the MPC106 by setting the MEMGO bit in memory
control configuration register 1 (MCCR1).
3.2.6.1 Memory Boundary Registers
The extended starting address and the starting address registers are used to define the lower
address boundary for each memory bank. The lower boundary is determined by the
following formula:
Lower boundary for bank n = ObOO II II II OxOOOOO.
The extended ending address and the ending address registers are used to define the upper
address boundary for each memory bank. The upper boundary is determined by the
following formula:
Upper boundary for bank n = ObOO II II II OxFFFFF.
See Figure 3-21, Figure 3-22, and Table 3-25 for memory starting address register 1 and 2
bit settings.
Starting Address Bank 3 Starting Address Bank 2 Starting Address Bank 1 Starting Address Bank 0
31
24 23
16 15
8
7
o
Figure 3-21. Memory Starting Address Register 1-ox80
3-36
MPC106 PCIBIMC User's Manual
MOTOROLA
Starting Address Bank 7 Starting Address Bank 6 Starting Address Bank 5 Starting Address Bank 4
31
24 23
o
8 7
16 15
Figure 3-22. Memory Starting Address Register 2-Ox84
Table 3-25. Bit Settings for Memory Starting Address Registers 1 and 2
Bit
Name
ReaetYalue
Description
Word Address
31-24
Starting address bank 3
OXOO
Starting address for bank 3
Ox80
23-16
Starting address bank 2
OXOO
Starting address for bank 2
15-8
Starting address bank 1
OXOO
Starting address for bank 1
7-0
Starting address bank 0
OXOO
Starting address for bank 0
31-24
Starting address bank 7
OxOO
Starting address for bank 7
23-16
Starting address bank 6
OXOO
Starting address for bank 6
15-8
Starting address bank 5
OXOO
Starting address for bank 5
7-0
Starting address bank 4
OXOO
Starting address for bank 4
Ox84
See Figure 3-23, Figure 3-24, and Table 3-26 for extended memory starting address
register 1 and 2 bit settings.
III Reserved
Starting Address 1
Extended Starting Address 0
Extended Starting Address < ! - - - - - - ,
Extended Starting Address 3
31
2625 24 23
18 17 16 15
_FvtAlnrl~,rI
10 9
8
2 10
7
Figure 3-23. Extended Memory Starting Address Register 1--Ox88
III Reserved
Starting Address 5
Extended Starting Address 4
_FrlAlnrl~,rI
Extended Starting Address 6 - - - - - - - ,
Extended Starting Address 7
31
2625 24 23
18 17 16 15
10 9
8
7
210
Figure 3-24. Extended Memory Starting Address Register 2--Ox8C
MOTOROLA
Chapter 3. Device Programming
3-37
Table 3-26. Bit Settings for Extended Memory Starting Address Registers 1 and 2
Bit
Reset Value
Name
Description
Byte Address
31-26
-
AliOs
These bits are reserved.
25-24
Extended starting address 3
ObOO
Extended starting address for bank 3
23-18
-
AliOs
These bits are reserved.
17-16
Extended starting address 2
ObOO
Extended starting address for bank 2
15-10
-
AliOs
These bits are reserved.
Ox88
9-8
Extended starting address 1
ObOO
Extended starting address for bank 1
7-2
-
AliOs
These bits are reserved.
1-0
Extended starting address 0
ObOO
Extended starting address for bank 0
31-26
-
All Os
These bits are reserved.
25-24
Extended starting address 7
ObOO
Extended starting address for bank 7
23-18
-
AliOs
These bits are reserved.
Ox8C
17-16
Extended starting address 6
ObOO
Extended starting address for bank 6
15-10
-
AliOs
These bits are reserved.
9-8
Extended starting address 5
ObOO
Extended starting address lor bank 5
7-2
-
AliOs
These bits are reserved.
1-0
Extended starting address 4
ObOO
Extended starting address for bank 4
See Figure 3-25, Figure 3-26, and Table 3-27 for memory ending address register 1 and 2
bit settings.
Ending Address Bank 3
31
Ending Address Bank 2
24 23
Ending Address Bank 1
16 15
8
Ending Address Bank 0
7
o
Figure 3-25. Memory Ending Address Register 1-Ox90
Ending Address Bank 7
31
Ending Address Bank 6
24 23
Ending Address Bank 5
16 15
8
Ending Address Bank 4
7
o
Figure 3-26. Memory Ending Address Register 2-Ox94
3-38
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 3-27. Bit Settings for Memory Ending Address Registers 1 and 2
Name
Bit
Reset Value
Description
Byte Address
Ox90
31-24
Ending address bank 3
OXOO
Ending address for bank 3
23-16
Ending address bank 2
OXOO
Ending address for bank 2
15-8
Ending address bank 1
OXOO
Ending address for bank 1
7-{J
Ending address bank 0
OXOO
Ending address for bank 0
31-24
Ending address bank 7
OXOO
Ending address for bank 7
23-16
Ending address bank 6
OXOO
Ending address for bank 6
15-8
Ending address bank 5
OXOO
Ending address for bank 5
7-{J
Ending address bank 4
OXOO
Ending address for bank 4
Ox94
See Figure 3-27, Figure 3-28, and Table 3-28 for extended memory ending address register
1 and 2 bit settings.
III Reserved
Extended Ending Address 1
Extended Ending Address 0
Extended Ending Address 2 - - - - - - . . . ,
Extended Ending Address 3
31
2625 24 23
18 17 16 15
10 9
8
7
210
Figure 3-27. Extended Memory Ending Address Register 1-ox98
III Reserved
Extended Ending Address 5
Extended Ending Address 4
Extended Ending Address 6 - - - - - - - ,
Extended Ending Address 7
2625 24 23
31
18 17 16 15
10 9
8
7
210
Figure 3-28. Extended Memory Ending Address Register 2-ox9C
MOTOROLA
Chapter 3. Device Programming
3-39
Table 3-28. Bit Settings for Extended Memory Ending Address Registers 1 and 2
Bit
Name
Reset Value
Description
31-26
-
AliOs
These bits are reserved.
25-24
Extended ending address 3
ObOO
Extended ending address for bank 3
23-18
-
AliOs
These bits are reserved.
17-16
Extended ending address 2
ObOO
Extended ending address for bank 2
15-10
-
All Os
These bits are reserved.
9--8
Extended ending address 1
ObOO
Extended ending address for bank 1
7-2
-
All Os
These bits are reserved.
1-0
Extended ending address 0
ObOO
Extended ending address for bank 0
31-26
-
AliOs
These bits are reserved.
25-24
Extended ending address 7
ObOO
Extended ending address for bank 7
23-18
-
AliOs
These bits are reserved.
17-16
Extended ending address 6
ObOO
Extended ending address for bank 6
15-10
-
AliOs
These bits are reserved.
9--8
Extended ending address 5
ObOO
Extended ending address for bank 5
7-2
-
AliOs
These bits are reserved.
1-0
Extended ending address 4
ObOO
Extended ending address for bank 4
Byte Address
Ox98
Ox9C
3.2.6.2 Memory Bank Enable Register
Individual banks are enabled or disabled by using the I-byte memory bank enable register,
shown in Figure 3-29 and Table 3-29. If a bank is enabled, the ending address of that bank
must be greater than or equal to its starting address. If a bank is disabled, no memory
transactions will access that bank, regardless of its starting and ending addresses.
Bank 4 - - - - - - ,
Bank 5 ~----,
Bank 6 - - - . ,
Bank 7
7 6
5
4
. . . - - - - - - Bank 3
.----Bank2
. - - - - Bank 1
BankO
3
2
1 0
Figure 3-29. Memory Bank Enable Register-OxAO
3-40
MPC106 PCIS/MC User's Manual
MOTOROLA
Table 3-29. Bit Settings for Memory Bank Enable Register-QxAO
Bit
Name
Reset
Value
7
Bank 7
0
6
Bank 6
0
5
Bank 5
0
Description
Bank 7
o Disabled
1 Enabled
Bank 6
o Disabled
1 Enabled
Bank 5
o Disabled
1 Enabled
4
Bank 4
0
Bank 4
o Disabled
1 Enabled
3
Bank 3
0
2
Bank 2
0
1
Bank 1
0
Bank 3
o Disabled
1 Enabled
Bank 2
o Disabled
1 Enabled
Bank 1
o Disabled
1 Enabled
0
BankO
0
BankO
o Disabled
1 Enabled
3.2.6.3 Memory Page Mode Register
The I-byte memory page mode register, shown in Figure 3-30 and Table 3-30, contains the
PGMAX parameter which controls how long the MPC106 retains the currently accessed
page (row) in memory. See Section 6.3.7, "DRAMIEDO Page Mode Retention:' or
Section 6.4.4, "SDRAM Page Mode Retention," for more information.
PGMAX
7
o
Figure 3-30. Memory Page Mode Reglster-QxA3
MOTOROLA
Chapter 3. Device Programming
3-41
Table 3-30. Bit Settings for Memory Page Mode Register-OxA3
Bit
7-0
Reset
Value
Name
AliOs
PGMAX
Description
For DRAMIEDO configurations, the value of PGMAX, multiplied by
64, determines the maximum RAS assertion interval for retained
page mode. When programmed to OxOO, page mode is disabled.
For SDRAM configurations, the value of PGMAX, multiplied by 64,
determines the activate to precharge interval (sometimes called row
active time or tRAS) for retained page mode. When programmed to
OxOO, page mode is disabled.
3.2.6.4 Memory Control Configuration Registers
The four 32-bit memory control configuration registers (MCCRs) set all RAM and ROM
parameters. These registers are programmed by initialization software to adapt the
MPC106 to the specific memory organization used in the system. After all the memory
configuration parameters have been properly configured, the initialization software turns on
·the memory interface using the MEMGO bit in MCCRI. See Figure 3-31 and Table 3-31
for memory control configuration register 1 bit settings.
III
Reserved
. - - - - - - - - - - - Bank 6 Row
Bank 7 Row - - - - - - - - - ,
PCKEN - - - - - - . . . . ,
RAM_TYPE - - - - - - ,
r------r----r---
SREN - - - - - ,
Bank 5 Row
Bank 4 Row
Bank 3 Row
Bank 2 Row
MEMGO----,
Bank 1 Row
BURST - - - ,
8N64
ROMFAL
27
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Figure 3-31. Memory Control Configuration Register 1 (MCCR1 )-OxFO
3-42
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-31. Bit Settings for MCCR1-oxFO
Name
Bit
Reset
Value
Oescrlptlon
31-28
ROMNAL
AII1s
For burst-mode ROM and Flash reads, ROMNAL controls the next
nibble access time. The maximum value is Ob1111 (15). The
actual cycle count will be two cycles more than the binary
value of ROMNAL.
For Flash writes, ROMNAL measures the write pulse recovery
(high) time. The maximum value is Ob1111 (15).The actual
cycle count will be four cycles more than the binary value of
ROMNAL.
27-23
ROMFAL
AII1s
For nonburst ROM and Flash reads, ROMFAL controls the access
time. For burst-mode ROMs, ROMFAL controls the first
access time. The maximum value is Ob11111 (31). For the
64-bit configuration, the actual cycle countwill be three cycles
more than the binary value of ROMFAL. For the 8-bit
configuration, the actual cycle count will be two cycles more
than the binary value of ROMFAL.
For Flash writes, ROMFAL measures the write pulse low time. The
maximum value is Ob11111 (31). The actual cycle count will
be two cycles more than the binary value of ROMFAL.
22
-
0
This bit is reserved.
21
8N64
x
Read only. This bit indicates the state of the ROM bank 0 data
path width configuration signal (FOE) at power-on reset.
0 Indicates that the MPC106 has been configured for a 64-blt
data path for ROM bank 0
1 Indicates that the MPC106 has been configured for an 8-bit
data path for ROM bank 0
20
BURST
0
Burst mode ROM timing enable.
0 Indicates standard (nonburst) ROM access timing
1 Indicates burst-mode ROM access timing
19
MEMGO
0
RAM interface logic enable. Note that this bit must not be set until
all other memory configuration parameters have been
appropriately configured by boot code.
0 MPC106 RAM interface logic disabled
1 MPC106 RAM interface logic enabled
18
SREN
0
Self-refresh enable. Note that if self refresh is disabled, the
system is responsible for preserving the integrity of
DRAMIEDO/SDRAM during sleep or suspend mode.
0 Disables the DRAMIEDO/SDRAM self refresh during sleep or
suspend mode
1 Enables the DRAMIEDO/SDRAM self refresh during sleep or
suspend mode
17
RAM_TYPE
1
RAM type
0 Indicates synchronous DRAM (SDRAM)
1 Indicates DRAM or EDO DRAM (depending on the setting for
MCCR2[EDO))
MOTOROLA
Chapter 3. Device Programming
3-43
Table 3-31. Bit Settings for MCCR1-OxFO (Continued)
Name
Bit
Reset
Value
Description
16
PCKEN
0
Memory interface parity checking/generation enable
0 .Disables parity checking and parity generation for
transactions to DRAMIEDO/SDRAM memory. If ECC is
enabled. disables L2 parity checking.
1 Enables parity checking and generation for all memory
transactions to DRAMIEDO/SDRAM. If ECC is enabled.
enables L2 parity checking.
15-14
Bank 7 row
00
RAM bank 7 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 7.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
13-12
Bank 6 row
00
RAM bank 6 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 6.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
11-10
BankS row
00
RAM bank 5 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 5.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
9-8
Bank 4 row
00
RAM bank 4 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 4.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
7-6
Bank 3 row
00
RAM bank 3 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 3.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
5-4
Bank 2 row
00
RAM bank 2 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 2.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
3-44
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-31. Bit Settings for MCCR1-OxFO (Continued)
Name
Bit
Reset
Value
Description
3-2
Bank 1 row
00
RAM bank 1 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 1.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
1--0
BankO row
00
RAM bank 0 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank O.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
See Figure 3-32 and Table 3-32 for memory control configuration register 2 (MCCR2) bit
settings.
•
Reserved
RMW_PAR - - - - ,
BUF_MODE
REFINT
18 17 16 15
31
210
Figure 3-32. Memory Control Configuration Register 2 (MCCR2)-OxF4
Table 3-32. Bit Settings for MCCR2-OxF4
Bit
Name
Reset
Value
Description
31-18
-
AliOs
These bits are reserved.
17
EGG_EN
0
EGG enable. This bit controls whether the MPG106 uses EGG for
transactions to system memory. Note that the EGG_EN parameter
overrides the PGKEN parameter. Also note that this bit and
RMW_PAR cannot both be set to 1. See Section 6.3, "DRAM/EDO
Interface Operation; for more information.
0
EGG disabled
1
EGG enabled
16
EDO
0
EDO enable. This bit indicates the type of DRAMs for the MPG1 06
memory interface. See Section 6.3, "DRAMIEDO Interface
Operation; for more information.
0
Indicates standard DRAMs
Indicates EDO DRAMs
1
MOTOROLA
Chapter 3. Device Programming
3-45
Table 3-32. Bit Settings for MCCR2-OxF4 (Continued)
Bit
Name
Reset
Value
Description
15-2
REFINT
AliOs
Refresh interval. These bits directly represent the number of clock
cycles between CBR refresh cycles. One row is refreshed in each
RAM bank during each CBR refresh cycle. The value forREFINT
depends on the specific RAMs used and the operating frequency
of the MPC106. See Section 6.3.10, "DRAM/EDO Refresh; or
Section 6.4.9, "SDRAM Refresh; for more information. Note that
the period of the refresh interval must be greater than the
readlwrite access time to insure that readlwrite operations
complete successfully.
1
BUF_MODE
1
Buffer mode. This bit controls how BCTlO and BCTl1 operate.
See Section 6.2, "Memory Interface Signal Buffering," for more
information.
0 BCf[Q enables the buffer for write operations; SCTCf
enables the buffer for read operations,
1 BCTlO controls the buffer direction (W/R); BCTl1 acts as
buffer enable.
0
RMW_PAR
0
Read-modify-write (RMW) parity enable. This bit controls how the
MPC106 writes parity bits to DRAMIEDO/SDRAM. Note that this
bit does not enable parity checking and generation. PCKEN must
be set to enable parity checking. Also note that this bit and
ECC_EN cannot both be set to 1. See Section 6.3.8, "DRAMIEDO
Parity and RMW Parity:' or Section 6.4.8, "SDRAM Parity and
RMW Parity; for more information.
RMW parity disabled
0
1
RMW parity enabled
See Figure 3-33 and Table 3-33 for memory control configuration register 3 (MCCR3) bit
settings.
•
31
28 27
24 23
20 19 18
15 14
12 11
9
8
6
5
Reserved
3 2
o
Figure 3-33. Memory Control Configuration Register 3 (MCCR3)-OxF8
3-46
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 3-33. Bit Settings for MCCR3-oxF8
Name
Bit
Reset
Value
Description
31-28
BSTOPRE_U
0000
Burst to precharge-upper nibble. For SDRAM only. These bits,
together with MCCR4[BSTOPRE_L), control the open page
interval. The page open duration counter is reloaded with
BSTOPRE_U II BSTOPRE_L every time the page is accessed
(inciuding page hits). When the counter expires, the open page is
closed with an SDRAM-precharge bank command. See
Section 6.4.4, "SDRAM Page Mode Retention," for more
information.
27-24
REFREC
0000
Refresh to activate interval. For SDRAM only. These bits control
the number of clock cycles frqm an SDRAM-refresh command until
an SO RAM-activate command is allowed. See Section 6.4.9,
"SDRAM Refresh;' for more information.
0001
1 ciock
0010
2 clocks
3 clocks
0011
23-20
19
RDLAT
CPX
0000
0
...
...
1111
0000
15 clocks
16 clocks
Data latency from read command. For SDRAM only. These bits
control the number of clock cycles from an SDRAM-read command
until the first data beat is available on the 60x data bus. RDLAT
values greater than 4 clocks are not supported. See Section 6.4.5,
"SDRAM Power-On Initialization," for more information.
0000
Reserved
0001
1 clock
2 clocks
0010
3 clocks
0011
4 ciocks
0100
0101
Reserved (not supported)
...
...
1111
Reserved (not supported)
CAS write timing modifier. For DRAMIEDO only. This bit, when set,
adds one clock cycle to the CAS precharge interval (CP4 + 1) and
subtracts one clock cycle from the "CAS assertion interval (CASs 1) for write operations to DRAMIEDO. Read operations are
unmodified. See Section 6.3.4, "DRAMIEDO Interface Timing," for
more information.
0
CAS write timing is unmodified
CAS write timing is modified as described above
1
18-15
RAS6P
MOTOROLA
0000
RAS assertion interval for CBR refresh. For DRAM/EDO only.
These bits control the number of clock cycles RAS is held asserted
during CBR refresh. The value for RAS 6P depends on the specific
DRAMs used and the 60x bus frequency. See Section 6.3.10,
"DRAMIEDO RefreSh," for more information.
0001
1 clock
2 clockS
0010
3 clocks
0011
...
...
1111
0000
15 clocks
16 clocks
Chapter 3. Device Programming
3-47
Table 3-33. Bit Settings for MCCR3-0xF8 (Continued)
Bit
14-12
Name
CASs
Reset
Value
000
Description
CAS assertion interval for page mode access. For DRAMIEDO
only. These bits control the number of clock cycles CAS is held
asserted during page mode accesses. The value for CASs
depends on the specific DRAMs used and the 60x bus frequency.
Note that when ECC is enabled, CASs + CP4 must equal four clock
cycles. See Section 6.3.4, "DRAMIEDO Interface Timing," for more
Information.
001
1 clock
010
2 clocks
011
3 clocks
11-9
CP4
000
...
...
111
000
7 clocks
8 clocks
CAS precharge interval. For DRAMIEDO only. These bits control
the number of clock cycles that CAS must be held negated in page
mode (to allow for column precharge) before the next assertion of
CAS. Note that when ECC is enabled, CASs + CP4 must equal four
clock cycles. See Section 6.3.4, "DRAMIEDO Interface Timing," for
more information.
001
1 clock
010
2 clocks
011
3 clocks
8-6
CAS 3
000
...
...
11.1
000
7 clocks
8 clocks
CAS assertion interval for the first access. For DRAMIEDO only.
These bits control the number of clock cycles CAS is held asserted
during a single beat or during the first access in a burst. The value
for CAS3 depends on the specific DRAMs used and the 60x bus
frequency. See Section 6.3.4, "DRAMIEDO Interface Timing," for
more information.
001
1 clock
010
2 clocks
011
3 clocks
5-3
RCD2
000
...
...
111
000
7 clocks
8 clocks
RAS to CAS delay interval. For DRAMIEDO only. These bits
control the number of clock cycles between the assertion of RAS
and the first assertion of CAS. The value for RCD2 depends on the
specific DRAMs used and the.60x bus frequency. However, RCD2
must be at least two clock cycles. See Section 6.3.4, "DRAMIEDO
Interface Timing," for more information.
001
Reserved
010
2 clocks
011
3 clocks
3-48
...
...
111
000
7 clocks
8 clocks
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-33. Bit Settings for MCCR3-0xF8 (Continued)
Name
Bit
2-0
Reset
Value
000
RP1
Description
RAS precharge interval. For DRAMIEDO only. These bits control
the number of clock cycles that RAS must be held negated (to
allow for row precharge) before the next assertion of RAS. Note
that RP 1 must be at least two clock cycles. See Section 6.3.4,
"DRAMIEDO Interface Timing," for more information.
001
Reserved
010
2 clocks
011
3 clocks
...
...
111
000
7 clocks
8 clocks
See Figure 3-34 and Table 3-34 for memory control configuration register 4 (MCCR4) bit
settings.
•
Reserved
,..---- WCBUF
RCBUF
SDMODE
28 27
31
24 23 22 21 20 19
8
7
4
3
o
Figure 3~34. Memory Control Configuration Register 4 (MCCR4)-OxFC
Table 3-34. Bit Settings for MCCR4-0xFC
Bit
31-28
27-24
Name
PRETOACT
ACTOPRE
MOTOROLA
Reset
Value
0000
0000
Description
Precharge to activate interval. For SDRAM only. These bits control
the number of clock cycles from an SDRAM-precharge command
until an SDRAM-activate command is allowed. See Section 6.4.5,
·SDRAM Power-On Initialization," for more information.
0001
1 clock
0010
2 clocks
0011
3 clocks
...
...
1111
0000
15 clocks
16 clocks
Activate to precharge interval. For SDRAM only. These bits control
the number of clock cycles from an SDRAM-activate command until
an SDRAM-precharge command is allowed. See Section 6.4.5,
"SDRAM Power-On Initialization," for more information.
0001
1 clock
0010
2 clocks
0011
3 clocks
...
...
1111
0000
15 clocks
16 clocks
Chapter 3. Device Programming
3-49
Table 3-34. Bit Settings for MCCR4-0xFC (Continued)
Bit
Name
Reset
Value
Description
23-22
-
00
Reserved
21
WCBUF
0
Memory write buffer type. This bit configures the MPCl 06 for one of
two buffer types, and controls the timing and operation of the buffer
control signals (BCTlO and BCTll ). See Section 6.2, "Memory
Interface Signal Buffering," for more information.
0
Flow through or transparent latch type buffer
1
Registered type buffer
20
RCBUF
1
Memory.read buffer type. This bit configures the MPC106 for one of
two buffer types, and controls the timing and operation of the buffer
control signals (BeTlO and BCTll ). See Section 6.2, "Memory
Interface Signal Buffering," for more information.
Flow-through type buffer
0
1
Transparent latch or registered type buffer
19-8
SDMODE
AliOs
SDRAM mode register. For SDRAM only. These bits specify the
SDRAM mode register data to be written to the SDRAM array
during power-up configuration.
Bit
Description
19-15 Opcode. For compliance with the JEDEC standard, these
bits are set to ObOOOOO for normal mode of operation and
to ObOOOOl for the JEDEC reserved test mode. All other
modes of operation are vendor-specific.
14-12 CAS latency
000 Reserved
001 1
010 2
011 3
100 4
101 Reserved
110 Reserved
111 Reserved
11
Wrap type
0
Sequential (Note that the sequential wrap type is
required for 60x processor-based systems)
1
Interleaved
10-8
Wrap length
000 Reserved
001 Reserved
010 4
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Reserved
3-50
MPC106 PCIBIMC User's Manual
MOTOROLA"
Table 3-34. Bit Settings for MCCR4-0xFC (Continued)
Name
Bit
7-4
3-0
ACTORW
BSTOPRE_L
Reset
Value
0000
0000
Description
Activate to readlwrite interval. For SDRAM only. These bits control
the number of clock cycles from an SDRAM-activate command until
an SDRAM-read or SDRAM-write command is allowed. See
Section 6.4.5, ·SDRAM Power-On Initialization," for more
information.
0001
Reserved
0010
2 clocks
0011
3 clocks
...
...
1111
0000
15 clocks
16 clocks
Burst to precharge-Iower nibble. For SDRAM only. These bits,
together with MCCR3[BSTOPRE_U), control the open page
interval. The page open duration counter is reloaded with
BSTOPRE_U II BSTOPRE_L every time the page is accessed
(including page hits). When the counter expires, the open page is
closed with an SDRAM-precharge bank command. See
Section 6.4.4, ·SDRAM Page Mode Retention:' for more
information.
3.2.7 Processor Interface Configuration Registers
The processor interface configuration registers (PICRs) control the programmable
parameters of the 60x bus interface and the L2 cache interface. There are two 32-bit
PICRs-PICRI and PICR2. See Figure 3-35 and Table 3-35 for PICRI bit settings.
MOTOROLA
Chapter 3. Device Programming
3-51
III Reserved
CF_L2_MP
Speculative PCI Reads
CF_APARK
CF_LOOP_SNOOP
LE_MODE
ST_GATH_EN
NO_PORT_REGS
CF_EXTERNAL_L2
CF_DPARK
TEA_EN
MCP_EN
FLASH_WR_EN
CF_LB~EN
CF_MP_ID
ADDRESS_MAP
PROC_TYPE
XIO_MODE
RCSO
CF_CACHE_1G
CF_BREAD_WS ~..
I
1
CF_CBA_MASK
!I J I I
II
IIIIIII IIIIII
24 23 22 21 20 19 18 ·17 16 15 14 13 12 11 10 9
31
8
7
6
5
4
3
2
I
1
0
Figure 3-35. Processor Interface Configuration Register 1 (PICR1)-OxA8
Table 3-35. Bit Settings for PICR1-OxA8
Bit
Name
Reset
Value
Description
31-24
CF_CBA_MASK
AII1s
L2 copy-back address mask. The MPC106 uses CF_CBA_MASK to
mask off address bits that are not driven by the tag RAM during tag
RAM read cycles. If a bit in CF_CBA_MASK is cleared (ObO). the
corresponding address bit read from the tag RAM will be treated as
ObO by the MPC106 (it is masked internally). regardless of its actual
state. If a bit in CF_CB~MASK is set (Ob1). the corresponding
address bit read from the tag RAM will be the actual state of the
address bit.
23-22
CF_BREAD_WS
00
Burst read wait states. These bits control the minimum number of
wait states from TS to the first TA for burst reads.
00 o wait states (601. 603 with 2:1 or greater clock ratiO. and 604)
01 1 wait state (603 with 1:1 clock ratio in DFifRY mode)
10 2 wait states (603 with 1:1 clock ratio in no-DRTRY mode)
11 3 wait states (not recommended)
3-52
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-35. Bit Settings for PICR1-OxA8 (Continued)
Name
Bit
Reset
Value
Description
21
CF_CACHE_1G
0
L2 cache 0-1 Gbyte only. This bit controls whether the L2 cache
caches addresses from 0 to 1 Gbyte or from 0 to 2 Gbytes and the
ROM address space.
0 The L2 may cache addresses from 0 to 2 Gbytes and ROM
addresses.
1 The L2 may only cache addresses from 0 to 1 Gbyte. No check
for hit or miss is performed for addresses from
1 to 2 Gbytes or for ROM addresses.
20
RCSO
x
ROM Location. Read only. This bit indicates the state of the ROM
location (RCSO) configuration signal at power-on reset.
ROM is located on PCI bus
0
1 ROM is located on 60x/memory data bus
19
XIO_MODE
0
Address map A contiguousldiscontiguous mode. This bit controls
whether address map A uses the contiguous or discontiguous 110
mode. Note that this bit is also accessible from the external
configuration register at Ox850. See Section 3.1.1. "Address Map A,"
for more information.
0 Contiguous mode
1 Discontiguous mode
18--17
PROC_TYPE
00
Processor type. These bits identify the type of processor used in the
system. The MPC106 uses PROC_TYPE to control ARTRY timing
(due to differences between the 601 and the 6031604). and the
power saving modes (for the 603 or 604).
00 601
01 Reserved
10 603
11 604
16
ADDRESS_MAP
x
Address map. This bit controls which address map is used by the
MPC106. The initial state is determined by the state of the address
map (DBGO) configuration signal at power-on reset. Note that
software that dynamically changes this bit must ensure that there
are no pending PCI transactions and that there is a sync instruction
following the address map change to allow the update to take effect.
See Section 3.1. "Address Maps," for more information.
0 The MPC106 is configured for address map B.
1 The MPC106 is configured for address map A.
15-14
CF_MP_ID
00
Multiprocessor identifier. Read only. This bit indicates which
processor (in a multiprocessor system) is performing the current
transaction. CF_MP_10 provides a means for software to identify
the processors.
00 Processor 0 is reading PICRl [CF_MP_10].
01 Processor 1 is reading PICRl [CF_MP_10].
10 Processor 2 is reading PICRl [CF_MP_10].
11 Processor 3 is reading PICRl [CF_MP_10).
MOTOROLA
Chapter 3. Device Programming
3-53
Table 3-35. BitSettings for PICR1-OxA8 (Continued)
Bit
Name
Reset
Value
Description
13
CF_LBA_EN
0
Local bus slave access enable. This bit controls whether the
MPC106 allows a local bus slave in the 60x bus address range from
1 Gbyte to 2 Gbytes. When this bit is cleared, the MPC106 ignores
the LBCLAIM signal. See Section 4.4.5, "60x Local Bus Slave
Support;' for more information.
Local bus slave access is disabled.
0
1
Local bus slave access is enabled.
12
FLASH_WR_EN
0
Flash write enable. This bit controls whether the MPC106 allows
write operations to Flash ROM.
Flash write is disabled.
0
Flash write is enabled.
1
11
MCP_EN
0
Machine check enable. This bit controls whether the MPC106
asserts MCP upon detecting an error. See Chapter 9, "Error
Handling:' for more information.
Machine check is disabled
0
1
Machine check is enabled
10
TEA_EN
0
Transfer error enable. This bit controls whether the MPC106 asserts
TEA upon detecting an error. See Chapter 9, "Error Handling," for
more information.
Transfer error is disabled
0
Transfer error is enabled
1
9
CF_DPARK
0
Data bus park. This bit indicates whether the 60x processor is
parked on the data bus.
60x processor is not parked on the data bus.
0
1
60x processor is parked on the data bus.
8
CF_EXTERNAL_L2
0
External L2 cache enable. This bit, in conjunction with CF_L2_MP,
indicate the processor and L2 configuration of the system. See
Table 3-36 for the specific bit encodings. See Section 5.6.2,
"External L2 Cache Controller Interface Parameters; for more
information.
External L2 disabled.
0
External L2 enabled.
1
7
NO_PORT_REGS
0
When configured for address map A, this bit indicates the presence
or absence of the external configuration registers. See
Section 3.2.10, "External Configuration Registers," for more
information.
The system implements the external configuration registers.
0
The MPC106 treats accesses to the external registers as PCI
1/0 cycles.
1
There are no physical registers for the external configuration
registers. The MPC106 services read accesses to the external
registers.
Note that writes to these registers are always shadowed regardless
of the state of this bit.
6
ST_GATH_EN
0
This bit enables/disables store gathering of writes from the
processor to PCI memory space. See Chapter 8, "Internal Control,"
for more information.
0
Store gathering is disabled
1
Store gathering is enabled
3-54
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 3-35. Bit Settings for PICR1-OxA8 (Continued)
Bit
Name
Reset
Value
Description
5
LE_MODE
0
This bit controls the endian mode of the MPC10S. Note that this bit
is also accessible from the external configuration register at Ox092.
See Appendix B, "Bit and Byte Ordering; for more information.
0 Big-endian mode
1 Little-endian mode
4
CF_LOOP_SNOOP
1
This bit causes the MPC10S to repeat a snoop operation (due to a
PCI-to-memory transaction) until it is not retried (AFi"i'RY input
asserted) by the processor(s) or the L2 cache. Generally, this bit
indicates whether the system implements snoop looping using the
high-priority snoop request (HP_SNP_REO) signal on the S01. See
PowerPC 601 RISC Microprocessor User's Manualfor more
information.
Snoop looping is disabled
0
1 Snoop looping is enabled
3
CF_APARK
0
This bit indicates whether the SOx address bus is parked. See
Section 4.3.1, "Address Arbitration," for more information.
0
Indicates that no processor is parked on the SOx address bus
1 Indicates that the last processor that used the 60x address bus
is parked on the SOx address bus
2
Speculative PCI
Reads
0
This bit controls speculative PCI reads from memory. Note that the
MPC10S performs a speculative read in response to a PCI
read-multiple command, even if this bit is cleared.
See Chapter 8, "Internal Control; for more information.
0
Indicates that speculative reads are disabled.
1 Indicates that speculative reads are enabled.
1-{)
CF_L2_MP
00
L2/multiprocessor configuration. These bits in conjunction with
CF_EXTERNAL_L2, indicate the processor and L2 configuration of
the system. See Table 3-36 for the specific bit encodings. See
Section 5.4, "L2 Cache Interface Parameters; for more information.
MOTOROLA
Chapter 3. Device Programming
3-55
Table 3-36 shows the processorIL2 configuration encodings for the CF_EXTERNAL_L2
and CF_L2_MP parameters in PICRI.
Table 3-36. ProcessorIL2 Configurations
Configuration
CF_EXTERNAL_L2
CF_L2_MP
0
00
Uniprocessor without L2 cache
0
01
Uniprocessor with internally-controlled, write-through L2 cache
0
10
Uniprocessor with internally-controlled, write-back L2 cache
0
11
Multiprocessor (2-4 60x processors on the 60x bus) without L2 cache
1
00
Uniprocessor with externally-controlled L2 cache
1
01
Reserved
1
10
Reserved
1
11
Multiprocessor with externally-controlled L2 cache
See Figure 3-36 and Table 3-37 for processor interface configuration register 2 (PICR2) bit
settings.
3-56
MPC106 PCIB/MC User's Manual
MOTOROLA
II] Reserved
L2_UPDATE_EN
L2_EN
NO_SERIAL_CFG
CF_FLUSH_L2
NO_SNOOP_EN
CF_FFO_LOCAL
FLASH_WR_LOCKOUT
CF_FAST_L2_MODE
CF_DATA_RAM_TYPE
CF_WMODE
CF_SNOOP_WS
CF_MOD_HIGH
CF_HIT_HIGH
CF_AD DR_ONLY_DISABLE
CF_HOLD
CF_INVMODE
CF_RWITM_FILL
-
CF_L2_HIT_DELAY
------CF_TWO_BANKS
,--CF_FAST_CASTOUT
CF30E_WIDTH
,
CF_L2_SIZE
CF_APHASE_WS
CF_WDAT.A
ICF-rE
IIIIIIIII
I
I
II
IIII
31 30 29 28 27 26 25 2423 22 21 2019 18 17 16 15 14 13 12 11 10
IIII
9
8
7
6 5
I
4 3
III
2
1
0
Figure 3-36. Processor Interface Configuration Register 2 (PICR2)-OxAC
MOTOROLA
Chapter 3. Device Programming
3-57
Table 3-37. Bit Settings for PICR2-OxAC
Name
Bit
-
Reset
Value
Description
31
L2_UPDATE_EN
0
L2 update enable. This bit controls whether the
internally-controlled L2 cache can be Updated with new data.
Note that this bit has no effect on the external L2 cache
controller operation. Also, note that L2_UPDATE_EN is
accessible at port Ox81C.
The L2 cache can only be read or invalidated. The L2
0
cache cannot be updated. Snoops are serviced to
maintain coherency.
1
The L2 cache can be updated with new data.
30
L2_EN
0
This bit enables/disables the internally-controlled L2 cache.
The L2 cache is only enabled if both this bit and CF_L2_MP
signify that there is an internally-controlled L2 cache in the
system. Note that this bit has no effect on the external L2
cache controller operation. Also, note that L2_EN is
accessible at port Ox81 C.
The L2 cache is disabled. However, the tags are not
0
invalidated. No L2 snoop operations or data updates are
performed while this bit is cleared.
The L2 cache is enabled.
1
29
NO_SERIAL_CFG
0
This bit controls whether the MPC106 serializes configuration
writes to PCI devices from the 60x bus.
Configuration writes to PCI devices from the 60x bus
0
cause the MPC106 to serialize and flush the internal
buffers.
1
Configuration writes to PCI devices from the SOx bus do
not cause serialization. The internal buffers are not
flushed.
28
CF_FLUSH_L2
0
L2 cache flush. The transition on this bit from 0 to 1 initiates
an internally-controlled L2 cache flush and invalidate
operation, provided L2_EN = ObO. Note that this bit has no
effect on the external L2 cache controller operation. Also,
note that L2_EN is accessible at port Ox81C.
Normal cache operation.
0
1
The transition from 0 to 1 indicates that the L2 cache
should write all modified lines to memory and mark all
lines as invalid.
27
NO_SNOOP_EN
0
This bit controls whether the MPC106 generates snoop
transactions on the 60x bus for PCI-te-system memory
transactions. This is provided as a performance enhancement
for systems that do not need to maintain coherency on
system memory accesses by PCI.
0
Snooping is enabled.
1
Snooping is disabled.
3-58
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-37. Bit Settings for PICR2-oxAC (Continued)
Bit
26
Name
CF_FFO_LOCAL
Reset
Value
°
Description
ROM remapping enable. This bit allows the lower 8 Mbytes of
the ROMIFlash address range to be remapped from the PCI
bus to the 6Ox/memory bus. Note that this bit is meaningful
only if the ROM location parameter indicates that ROM is
located on PCI bus (PICR1[RCSO) =0).
ROMIFlash remapping disabled. The lower 8 Mbytes of
the ROMIFIash address space are not remapped. All
ROM/Flash accesses are directed to the PCI bus.
1 . ROM/Flash remapping enabled. The lower 8 Mbytes of
the ROMIFlash address space are remapped to the
60x/memory bus. ROMIFlash accesses in the range
OxFFOO_OOOO-OxFo:F7F_FFFF are directed to the
60x/memory bus. ROM/Flash accesses in the range
OxFF80_0000-0xFFFF_FFFF are directed to the PCI
bus.
°
25
24
FLASH_WR_LOCKOUT
CF_FAST_L2_MODE
°
°
Flash write lock-out. This bit, once set, prevents writing to
Aash. Once set, this bit can only be cleared by a hard reset.
Write operations to Flash are enabled, provided
FLASH_WR_EN =1.
1 Write operations to Flash are disabled until the MPC106
is reset.
°
Fast L2 mode enable. This bit enables/disables fast L2 mode
timing. Fast L2 mode timing allows for no dead cycles
between consecutive burst reads that hit in the L2 cache.
Note that the 601 and 603 are not capable of using fast L2
mode timing.
Disable fast L2 mode timing
1 Enable fast L2 mode timing
°
23-22
CF_DATA_RAM_TYPE
MOTOROLA
00
L2 data RAM type. These bits indicate the type of data RAM
used for the L2 cache.
00 Synchronous burst SRAM
01 Pipelined burst SRAM
10 Asynchronous SRAM
11 Reserved
Chapter 3. Device Programming
3-59
Table 3-37. Bit Settings for PICR2-OxAC (Continued)
Bit
Reset
Value
Name
Description
21-20
CF_WMODE
00
SRAM write timing and partial update disable. These bits
control L2 data RAM write timing. For an asynchronous
SRAM cache configuration, only mode 00 is valid. See
Section 5.4.2.4, "CF_WMODE," for more information.
00 Normal write timing without partial update.
01 Normal write timing with partial update using external
byte write decoding. Not valid for asynchronous SRAMs.
10 Delayed write timing with partial update using external
byte write decoding. When performing an L2 cache write,
the MPC106 issues the L2 cache control signals, but
delays the assertion ofTA by one cycle to allow for
external byte write decoding. Not valid for asynchronous
SRAMs.
11 Early write timing with partial update using external byte
write decoding. The MPC1 06 speculatively asserts DWE
one cycle earlier than the other L2 data RAM control
signals for better write performance. Not valid for
asynchronous SRAMs.
19-18
CF_SNOOP _WS
11
Snoop wait states. These bits control the minimum number of
wait states for the address phase in a snoop cycle. See
Section 4.3.3.2, "Address Tenure Timing Configuration:' for
more information.
wait states (2-clock address phase)
00
01 1 wait state (3-clock address phase)
10 2 wait states (4-clock address phase)
11 3 wait states (5-clock address phase)
o
17
CF_MOD_HIGH
0
Cache-modified signal polarity. This bit controls the active
state of the DIRTY_IN, DIRTY_OUT, and TV L2 cache
signals.
0
The input signals TV and DIRTY_IN are active low and
the output signals TV and DIRTY_OUT are active low.
1 The input signals TV and DIRTY_IN are active high and
the output signals TV and DIRTY_OUT are active high.
16
CF_HIT_HIGH
0
L2 cache HIT signal polarity. This bit controls the active state
01 the HIT signal for the internally-controlled L2 cache. Note
that this bit has no effect on the external L2 cache controller
operation. RTT is always active low for the external L2 cache
controller interface.
HIT is active low.
0
1
HIT is active high.
15
-
0
This bit is reserved.
14
CF_ADDR_ONLY_DISABLE
0
This bit specifies whether the internally-controlled L2 cache
responds to address-only transactions (clean, flush, and kill).
This bit is set when the L2 is enabled for normal L2 operation.
Note that this bit has no effect on the external L2 cache
controller operation.
The internally-controlled L2 cache responds to clean,
0
flush, and kill transactions.
1
The internally-controlled L2 cache ignores clean, flush,
and kill transactions.
3-60
MPC106 PCIS/MC User's Manual
MOTOROLA
Table 3-37. Bit Settings for PICR2-OxAC (Continued)
Name
Bit
Reset
Value
Description
13
CF_HOLD
0
L2 tag address hold. This bit controls the hold time of the
address, TV, and DIRTY_OUT signals with respect to the
rising edge (negation) of mE.
0 Synchronous tag RAM configurations. No hold time (0
clock cycles). TV is always driven during tag reads.
1 Asynchronous tag RAM configurations. Tag address, TV,
and DIRTY_OUT are held valid for one clock cycle after
mE is negated. TV is released to high-impedance
during tag reads.
12
CF_INV_MODE
0
L2 invalidate mode enable. When L2 invalidate mode is
enabled, any SOx transaction on the 60x bus causes the L2 to
invalidate the tag entry indexed by the SOx address. Invalidate
mode is used to initialize the tag contents. Note that this bit
has no effect on the external L2 cache controller operation.
See Section 5.2.2, "L2 Cache Line Status," for more
information.
0 L2 invalidate mode is disabled.
1 L2 invalidate mode is enabled.
11
CF_RWITM_FILL
0
L2 read-with-intent-to-modify line-fill disable. This bit controls
the response of the internally-controlled L2 cache to
read-with-intent-to-modify (RWITM) misses. Note that this bit
has no effect on the external L2 cache controller operation.
See Section 5.3, "L2 Cache Response to Bus Operations," for
more information.
0 The internally-controlled L2 cache performs a line-fill
when a RWITM miss occurs.
1 The internally-controlled L2 cache does not perform a
line-fill when a RWITM miss occurs.
10-9
CF_L2_HIT_DELAY
11
L2 cache hit delay. These bits control the number of clock
cycles from the assertion of TS until HIT is valid. See
Section 5.4.2.1, "CF_L2_HIT_DELAY," for more information.
00 Reserved
01 1 clock cycle
10 2 clock cycles
11 3 clock cycles
8
CF_TWO_BANKS
0
L2 cache banks. This bit specifies the number of banks of L2
data RAM. See Section 5.1.6, "Two-Bank Support," for more
information.
0 1 SRAMbank
1 2SRAMbanks
7
CF_FAST_CASTOUT
0
Fast L2 castout timing
0 Normal L2 castout timing. TV is released to
high-impedance during tag reads.
1 Fast L2 castout timing for improved performance when
using synchronous write tag RAMs. TV is always driven
during tag reads.
MOTOROLA
Chapter 3. Device Programming
3-61
Table 3-37. Bit Settings for PICR2-OxAC (Continued)
Name
Bit
Reset
Value
6
CF30E_WIDTH
0
5-4
CF_L2_SIZE
00
Description
TOE active pulse width. This bit controls the number of clock
cycles that WE is held asserted during L2 tag
cast-outlcopy-back operations.
2 clock cycles
0
3 clock cycles
1
L2 cache size. These bits indicate the size of the L2 cache.
00
01
10
11
3-2
CF_APHASE_WS
11
256 Kbytes
512 Kbytes
1 Mbyte
Reserved
Address phase wait states. These bits control the minimum
number of address phase wait states (in clock cycles) for
processor-initiated operations.
wait states
00
01 1 wait state
10 2 wait states
11 3 wait states
o
1
CF_DOE
0
L2 first data read access timing. For synchronous burst
SRAM configurations, this bit controls the number 01 clock
cycles from DOE assertion to valid data on the first read
access. Note that this bit has no effect on the external L2
cache controller operation. See Section 5.4.2.2, "CF_DOE,"
for more information.
1 clock cycle
0
2 clock cycles
1
For asynchronous SRAM configurations, this bit controls the
first data access timing of pipelined read cycles.
3-2-2-212-2-2-2 timing (2 clocks)
0
3-2-2-213-2-2-2 timing (3 clocks)
1
0
CF_WDATA
0
This bit has different functions depending on the L2 data RAM
configuration. See Section 5.4.2.3, "CF_WDATA:' for more
information.
For synchronous burst SRAM configurations, this bit is
reserved and must be cleared to O.
For pipelined burst SRAMs, this bit indicates ADSC-only or
ADSP mode. See Section 5.1.4, "Pipelined Burst SRAMs," for
more information.
ADSC-only mode
0
1
ADSP mode
is connected to ADSP on the L2 data
RAM)
For asynchronous SRAMs, this bit indicates the DWEn timing:
OWEn is negated on the falling clock edge of the cycle
0
when TA is asserted.
1
DWEn is negated on the rising clock edge when TA is
negated.
ern
3-62
MPC106 PCIB/MC User's Manual
MOTOROLA
3.2.8 Alternate OS-Visible Parameters Registers
The alternate OS-visible parameters registers 1 and 2 provide operating systems an
alternate means to access some of the bits in PIeRI. These registers are 1 byte each. See
Figure 3-37 and Table 3-38 for alternate OS-visible parameters register 1 bit settings.
IliI
Reserved
XIO_MODE - - - - - , .....---TEA_EN
RX_SERR_EN
MCP_EN
765
4
3
2
1
0
Figure 3-37. Alternate OS-Visible Parameters Register 1-OxBA
Table 3-38. Bit Settings for Alternate OS-Visible Parameters Register 1-OxBA
Name
Bit
Reset
Value
7-6
-
00
5
RX_SERR_EN
0
Description
Reserved
This bit controls whether the MPC106 recognizes the assertion of
"SERA by another PCI device.
0
1
The MPC106 ignores the assertion of "SEAR by another PCI
device.
The MPC106 recognizes the assertion of "SERA by another
PCI device.
4-3
-
00
These bits are reserved.
2
XIO_MODE
1
Address map A discontiguous/contiguous mode. This bit controls
whether address map A uses the discontiguous or contiguous 1/0
mode. See Section 3.1.1, "Address Map A," for more information.
Note that this bit is the inverse of bit 19 of PICR1.
0 Discontiguous mode
1 Contiguous mode
1
TEA_EN
0
Transfer error acknowledge enable. This bit controls whether the
MPC106 asserts TEA upon detecting an error. Note that this bit is
the same as bit 10 of PICR1.
0 Transfer error acknowledge is disabled.
1 Transfer error acknowledge is enabled.
0
MCP_EN
0
Machine check enable. This bit controls whether the MPC106
asserts QCP upon detecting an error. Note that this bit is the
same as bit 11 of PICR1.
0 Machine check is disabled.
1 Machine check is enabled.
MOTOROLA
Chapter 3. Device Programming
3-63
See Figure 3-38 and Table 3-39 for alternate OS-visible parameters register 2 bit settings .
•
765
4
321
Reserved
0
Figure 3-38. Alternate OS-Visible Parameters Register 2-OxBB
Table 3-39. Bit Settings for Alternate OS-Visible Parameters Register 2-OxBB
Name
Bit
Reset
Value
Description
7-1
-
00
These bits are reserved.
0
FLASH_WR_EN
0
Flash write enable. This bit controls whether the MPC106 allows
write operations to Flash ROM. Note that this bit is the same as bit
1201 PICR1.
0 Flash writes are disabled.
1 Flash writes are enabled.
3.2.9 Emulation Support Configuration Registers
The 32-bit emulation support configuration registers (ESCRs) control the behavior of the
MPC 106 when operating in emulation mode. The emulation mode is fully compliant with
the PC emulation option described in the PowerPC Microprocessor Common Hardware
Reference Platform: A System Architecture. See Section 7.8, "Emulation Support," for
more information about emulation mode.
See Figure 3-39 and Table 3-40 for emulation support configuration register 1 (ESCRl) bit
settings.
•
EMULATION_MODE_EN
EMULATION_MODE_HW
PROC_COMPATIBILlTY_HOLE
PCLCOMPATIBILlTY_HOLE
PIRQ_ACTIVE_HIGH
PIRQ_EN
FD_ALlAS_EN
31
28 27
Reserved
-----------------,
----------------,
--------------...,
-----------------,
-------------,
-----------...,
------------,
16 15
876543210
Figure 3-39. Emulation Support Configuration Register 1 (ESCR1)-OxEO
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MPC106 PCIBIMC User's Manual
MOTOROLA
Table 3-40. Bit Settings for ESCR1-OxEO
Bit
Name
Reset
Value
Description
31-28
-
AliOs
These bits are reserved.
27-16
INT_VECTOR_RELOCATE
AII1s
These bits represent the 1-Mbyte block of system memory that is
accessed when emulation mode is enabled
(EMULATION_MODE_EN =1) and a 60x transaction to the address
range OxFFFO_OOOO-OxFFFF]FFF occurs. The 12
most-significant bits of the address (OxFFF) are replaced by these
bits, and the 20 least-significant bits are left unchanged. These bits
have no effect if emulation mode is disabled
(EMULATION_MODE_EN =0).
15-8
TOP_OF_MEM
AliOs
These bits represent the block address of a 1-Mbyte block that is the
upper address boundary to which the MPC106, as a PCI target, will
respond. These bits have no effect if emulation mode is disabled
(EMULATION_MODE_EN =0).
7
-
This bit is reserved.
6
FD_ALlAS_EN
°
1
This bit is used in address map B only; it is not used for map A or the
emulation mode map.
No response
1 The MPC106, as a PCI target, responds to addresses in the
range OxFDOO_OOOO-
Error
-
Illegal operation; Signals error. Address only
operation. AACK is asserted.
00011
Error
-
Illegal operation; signals error. Address only
operation. AACK is asserted.
00101
Error
-
Illegal operation; Signals error. Address only
operation. AACK is asserted.
00111
Error
-
Illegal operation; signals error. Address only
operation. AACK is asserted.
01111
Error
-
Illegal operation; Signals error. Address only
operation. AACK is asserted.
1xxx 1
Error
-
Illegal operation; signals error. Address only
operation. AACK is asserted.
MOTOROLA
Chapter 4. Processor Bus Interface
4-11
Table 4-1. MPC106 Responses to 60x Transfer Type Signals (Continued)
TT[Q-4]
Bus Operation
Class of
Operation
MPC106 Response
TEA
Direct-store load
request
Error
-
Illegal operation; signals error. Address only
operation. AACK is asserted.
Graphic write (ecowx)
Error
TEA
asserted
Illegal operation; signals error. AACK is
asserted; TEA will be asserted if enabled. If
TEA is not enabled, data tenure is terminated
byTA.
11100
Graphic read (eciwx)
Error
TEA
asserted
Illegal operation; signals error. AACK is
asserted; TEA will be asserted if enabled. If
TEA is not enabled, data tenure is terminated
by fA.
0101x
Direct-store load
immediate
Error
TEA
asserted
Illegal operation; signals error. AACK is
asserted; TEA will be asserted if enabled. If
TEA is nol enabled, data tenure is terminated
byTA.
0111x
Direct-store load last
Error
TEA
Illegal operation; signals error. AACK is
asserted; TEA will be asserted if enabled. If
TEA is not enabled, data tenure is terminated
byTA.
0100x
. 10100
asserted
0001 x
0011x
Direct-store store
immediate
Error
Direct-store store last
Error
TEA
asserted
TEA
asserted
Illegal operation; Signals error. AACK is
asserted; TEA will be asserted if enabled. If
TEA is not enabled, data tenure is terminated
by 'fA.
Illegal operation; signals error. AACK is
asserted; TEA will be asserted if enabled. If
TEA is not enabled, data tenure is terminated
byTA.
The MPC 106 propagates snoop broadcast operations to the 60x bus in response to PCI businitiated memory accesses. All snoop broadcasts generated by the MPC106 are caused by
PCI bus operations and are identified as burst, cacheable, write-back, and global accesses.
The transaction types driven by the MPC106 for snoop operations are not encoded as
address-only; however, all MPC106-initiated snoop operations should be treated as
address-only transactions, and no DBGn or TA signal assertions should be expected
following the address tenure. Table 4-2 describes the transfer type encodings generated by
the MPC106.
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MPC106 PCIBIMC User's Manual
MOTOROLA
Table 4-2. Transfer Type Encodings Generated by the MPC106
TT[D-4J
60x Bus Operation
(Driven by MPC106)
Condition
00010
Burst-write-with-Ilush
Generated in response to non locked PCI writes to
memory
10010
Burst-write-with-Ilush-atomic
Generated in response to locked PCI writes to memory
00110
Burst-write-with-kill
Generated in response to nonlockedllocked PCI writes
with invalidate to memory
11110
Burst-RWITM-atomic
Read-with-intent-to-modily-generated lor locked PCI
reads
01010
Burst-read
Generated in response to non locked PCI reads to
memory
4.3.2.2 TBST and TSIZ[O-2] Signals and Size of Transfer
The transfer size (TSIZ[0-2]) signals, in conjunction with the transfer burst (TBST) signal,
indicate the size of the requested data transfer, as shown in Table 4-3. These signals may be
used along with address bits A[29-31] to determine which portion of the data bus contains
valid data for a write transaction or which portion of the bus should contain valid data for
a read transaction. The 60x processors use the eight-word burst transactions for the transfer
of cache blocks. For these transactions, the TSIZ[0-2] signals are encoded as ObOlO, and
address bits A[27-28] determine which double-word transfer should occur first.
The MPC106 supports critical-word-first burst transactions (double-word-aligned) from
the 60x processor. The MPC 106 transfers this double word of data first, followed by double
words from increasing addresses, wrapping back to the beginning of the eight-word block
as required.
Table 4-3. MPC106 Transfer Size Encodings
MOTOROLA
TBST
TSIZO
Asserted
Negated
TSIZ1
TSIZ2
Transfer Size
0
1
0
Eight-word burst
0
0
0
Eight bytes
Negated
0
0
1
One byte
Negated
0
1
0
Two bytes
Negated
0
1
1
Three bytes
Negated
1
0
0
Four bytes
Negated
1
0
1
Five bytes
Negated
1
1
0
Six bytes
Negated
1
1
1
Seven bytes
Chapter 4. Processor Bus Interface
4-13
4.3.2.3 Burst Ordering During Data Transfers
During burst data transfer operations, 32,bytes of data (one cache block) are transferred to
or from the cache in order. Burst write transfers are always performed
zero-double-word-first.
However,
since
burst
reads
are
performed
critical-double-word-first, a burst-read transfer may not start with the first double word of
the cache block, and the cache-block-fill operation may wrap around the end of the cache
block. Table 4-4 describes MPC106 burst ordering.
Table 4-4. MPC106 Burst Ordering
For Starting Address:
Data Transfer
A[27-28]
=00
A[27-28]
= 01
A[27-28]
= 10
A[27-28]
First data beat
DWO
DW1
DW2
DW3
Second data beat
DW1
DW2
DW3
DWO
Third data beat
DW2
DW3
DWO
DW1
Fourth data beat
DW3
DWO
DW1
DW2
=11
Note: The A[29-31] signals are always ObOOO for burst transfers Initiated by the MPC106.
4.3.2.4 Effect of Alignment on Data Transfers
Table 4-5 lists the aligned transfers that can occur to and from the MPC106. These are
transfers in which the data is aligned to .an address that is an integer multiple of the size of
the data. For example, Table 4-5 shows that I-byte data is always aligned; however, for a
4-byte word to be aligned, it must be oriented on an address that is a multiple of 4.
Table 4-5. Aligned Data Transfers
Data Bus By1e Lane(s)
Transfer Size
Byte
4-14
TSIZO
TSIZ1
TSIZ2
A[29-31]
0
1
2
3
4
5
6
7
..J
-
-
-
-
..J
-
-
-
-
-
-
-
-
-
..J
-
0
0
1
000
0
0
1
001
0
0
1
010
-
0
0
1
011
-
0
0
1
100
0
0
1
101
0
0
1
110
-
0
0
1
111
-
-
-
MPC106 PCIBlMCUser's Manual
..J
-
..J
-
..J
-
-
..J
-
-
..J
MOTOROLA
Table 4-5. Aligned Data Transfers (Continued)
Data Bus Byte Lane(s)
Transfer Size
TSIZO
TSIZ1
TSIZ2
A[29-31]
0
1
" "
0
1
0
000
0
1
0
010
-
-
0
1
0
100
-
-
0
1
0
110
-
-
Word
1
0
0
000
1
0
0
100
Double word
0
0
0
000
Half word
Notes:
2
3
4
5
6
7
-
-
-
-
-
-
-
-" -"
-
-
-" -"
-
" -"
-" -" " "
" " " "
" " " " " " " "
-
-
-
-
-
" These entries indicate the byte portions of the requested operand that are read or written during that
bus transaction.
- These entries are not required and are ignored during read transactions; they are driven with undefined data during all write transactions.
Data bus byte lane 0 corresponds to DH[D-7J. byte lane 7 corresponds to DL[24-31J.
The MPC106 supports misaligned memory operations, although their use may
substantially degrade performance. Misaligned memory transfers address memory that is
not aligned to the size of the data being transferred (such as, a word read from an odd byte
address). The MPCI06's processor bus interface supports misaligned transfers within a
word (32-bit aligned) boundary, as shown in Table 4-6. Note that the 4-byte transfer in
Table 4-6 is only one example of misalignment. As long as the attempted transfer does not
cross a word boundary, the MPC 106 can transfer the data to the misaligned address within
a single bus transfer (for example, a half-word read from an odd byte-aligned address). An
attempt to address data that crosses a word boundary requires two bus transfers to access
the data.
Due to the performance degradations associated with misaligned memory operations, they
should be avoided. In addition to the double-word straddle boundary condition, the
processor's address translation logic can generate substantial exception overhead when the
load/store multiple and load/store string instructions access misaligned data. It is strongly
recommended that software attempt to align code and data where possible.
MOTOROLA
Chapter 4. Processor Bus Interface
4-15
Table 4-6. Misaligned Data Transfers (4-Byte Examples)
Transfer Size
(Four Bytes)
Data Bus Byte Lanes
TSIZ[D-2]
A[29-31]
0
1
2
3
4
5
6
7
-
-
-
Aligned
100
000
A
A
A
A
Misaligned-first access
011
001
A
A
A
001
100
-
-
-
-
A
-
010
010
-
-
A
A
-
-
011
100
-
-
-
A
A
001
011
-
A
-
-
-
011
100
-
A
A
A
-
Aligned
100
100
-
-
-
-
-
A
A
A
A,
Misaligned-first access
011
101
-
-
-
-
A
A
000
A
-
-
-
110
-
-
A
A
010
000
A
A
-
-
-
-
001
111
-
-
-
-
-
010
-
-
A
001
-
-
A'
011
000
A
A
A
-
-
-
-
second access
Misaligned-first access
second access
Misaligned-first access
second access
second access
Misaligned-first access
second access
Misaligned-first access
second access
-
-
-
-
-
Notes:
A:
Byte lane used
- : Byte lane not used
4.3.3 Address Transfer Termination
Address transfer termination occurs with the assertion of the address acknowledge (AACK)
signaL A snoop response is indicated by the assertion of the ARTRY signal until one clock
after AACK; the bus clock cycle after AACK is referred to as the ARTRY window. The
MPC 106 controls assertion of AACK unless the cycle is claimed by the external L2 cache
controller (as indicated by the assertion of the lllT signal by the L2 cache controller).
Following assertion of mT, the L2 cache controller is responsible for assertion of AACK.
When AACK is asserted by the L2 cache controller, it should be asserted for one clock
cycle, and then negated for one clock cycle prior to entering a high-impedance state. The
MPC 106 holds the AACK signal in a high-impedance state until assertion of AACK by the
Mpc 106 is required for the termination of the address cycle. For address bus transactions
initiated by a processor, the snoop response originates from either the MPC 106 or an
alternate bus master (the other processors or an external L2 cache controller). For
transactions initiated by the MPC 106, the snoop response originates from an alternate bus
master.
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MPC106 PCIBIMC User'. Manual
.MOTOROLA
The following sections describe how the MPC 106 can be configured through its register
settings to accommodate a variety of snoop responses and snoop timing requirements.
4.3.3.1 MPC106 Snoop Response
Processors may assert ARTRY because of pipeline collisions or because an address snoop
hits a modified block in the processor's L1 cache. When a processor detects a snoop hit due
to a modified block in the cache, it will assert its bus request in the window of opportunity
(the clock after theARTRY window) to obtain mastership of the bus for its L1 copy-back
cycle.
The MPCI06 can be configured to repeat the snoop for a PCI-to-memory transaction that
has been terminated by the assertion of ARTRY by a processor or by the L2 cache through
the use of the PICRI [CF_LOOP_SNOOP] bit. If PICRI [CF_LOOP_SNOOP] is set, the
MPCI06 repeats snooping until ARTRY is not asserted. If PICRI [CF_LOOP_SNOOP] is
cleared, the MPC106 repeats the snoop until either ARTRY is not asserted, or a snoop push
occurs.
The MPC106 may assertARTRY because of an L2 cast-out operation (when the MPCI06's
internal L2 cache controller is being used), an address collision with an MPCI06 internal
buffer, or because the PCI bus is occupied by another PCI bus master in a transaction that
requires snooping before the 60x-to-PCI address bus transaction is completed. This can
occur, for example, when a 60x processor performs a read operation to a PCI target while
the PCI bus is occupied by another PCI bus master, or when a 60x processor performs a
write operation to the PCI bus, but the MPCI06's 6Ox-to-PCI write buffer is full and
another PCI bus master accesses the system RAM requiring a snoop while the 60x
processor is waiting. Note that the MPCI06 may assertARTRY on any clock cycle after the
assertion of TS and the clock cycle following AACK.
Figure 4-7 illustrates the sequence of bus actions in the case of a snoop. When a 60x
processor detects a snoop hit with the L1 cache in write-back mode, the 60x asserts ARTRY
and BR. This causes the MPC I 06 to grant the bus to the 60x processor which then proceeds
with a copy-back to main memory of the modified cache block.
&Ox Bus Clock
• •~~
!JFW" • •~~IXll
D":::::
I
I~
-----<""""""""",.
i
AI'W)
I
~rr-:- r - - - r - - - r -
Figure 4-9. Data Tenure Terminated by Assertion of TEA
The bus transactions interpreted by the MPCI06 as bus errors are as follows:
•
Direct-store transactions, as indicated by the assertion of XATS and TT[O-4]
•
Any graphics read/write transactions (caused by eciwx or ecowx instructions)
•
Write operations into INTA space, OxBFFF_FFFO in address map A, or
OxFEFX_XXXX in address map B.
•
Write operations into ROM or write to Flash ROM if Flash ROM is not enabled, or
if the transfer bus width does not match the Flash ROM data width, or transaction is
not caching-inhibited or write-through. Caching-inhibited or write-through writes to
Flash ROM are the only transactions allowed.
•
Processor read operation from PCI transaction which is target-aborted by the PCI
target, or if the target asserts PERR.
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MPC106 PCIBIMC User's Manual
MOTOROLA
4.4.5 60x Local Bus Slave Support
The MPC 106 provides support for a local bus slave that can handle 60x transactions by
generating its own TA responses. Following the assertion of the local bus claim
(LBCLAIM) signal, the MPC 106 will assert AACK for local bus slave address tenures. The
local bus slave should monitor the ARTRY and TEA signals, and abort the associated data
tenure if required, but should never assert ARTRY. In addition, the local bus slave should
only respond to bus transactions originated by processors, and not respond to L2 cache
cast-out operations, or Ll snoop transactions. System designers should ensure that the local
bus slave does not respond to any bus transaction by the MPC106's internal L2 controller,
or an external L2 cache controller, as the L2 controllers have no logic to sense the assertion
of the LBCLAIM signal by the local bus slave.
The local bus slave can claim any address in the 4-Gbyte address space. To prevent conflicts
with the L2 cache, the local bus slave should use an address range that is not cacheable in
the L2. When configured to use the MPC106's integrated L2 cache controller, cachinginhibited accesses and accesses in the PCI address space (Ox8000_0000 through
OxFEFF_FFFF, OxFFOO_OOOO through OxFFFF_FFFF when configured for ROM access on
PCI, and OxA_OOOO through OxB_FFFF if the compatibility hole range is enabled) are not
cached. If the local bus slave's address range is in the PCI memory space, the data from the
local bus slave may be cached in the L1 cache, but data from the PCI memory space will
not be cached (or coherency maintained) by the MPC106's internal L2 cache controller.
4.4.5.1 60x Local Bus Slave Timing
The MPC106's response to a local bus slave is controlled through the configuration of the
PICRl[CF_LBA_EN] bit. If the PICRl[CF_LBA_EN] bit is cleared, the MPC106 ignores
the LBCLAIM signal. If the PICRI [CF_LBA_EN] bit is set, the MPC 106 samples the
LBCLAIM signal when the wait-state value set in PICR2[CF_L2_HIT_DELAY] expires,
and ifLBCLAIM is asserted, drives DBGLB, and thereby allows the local bus slave to drive
the TA signal. The local bus slave can drive TA the clock after the assertion of LBCLAIM,
but not earlier, thereby providing a fastest local bus slave access of 3-1-1-1 bus cycles. A
local bus slave should not assert TA before the ARTRY window' when the system is
configured for no-DRTRY mode operation, and should not assert TA more than one clock
before the ARTRY window when operating in DRTRY mode.
The MPCI06 will not assertARTRY for any bus operation claimed by the local bus slave.
External L2 cache controllers should not assert ARTRY for any local bus slave operation,
as data from the local bus slave should be treated as noncacheable. If the MPC 106 is
configured for multiprocessor operation, another processor can assert ARTRY to retry the
bus operation in the clock cycle after PICR2[CF_SNOOP_WS] expires.
Note that the local bus slave should only drive the TA signal when a data tenure is in
progress. The local bus slave is responsible for ·precharging the TA signal following
negation by driving TA high for one half clock cycle prior to entering a high-impedance
state following the last TA assertion. If the system is running in fast-L2 mode, DBGLB may
be asserted at the same time as the last assertion of TA in an L2 cache operation. If the
MOTOROLA
Chapter 4. Processor Bus Interface
4-21
following data bus tenure is a local bus slave transaction, the local bus slave should delay
driving data and asserting TA to allow ti~e for TA negation and precharging between the
L2 bus operation and the subsequent locai bus slave bus operation.
Figure 4-10 shows an example of a fast local bus slave transaction.
~I2H1TDELAY =1, CF"APHAtrws =1
¥M~'M
Dala ~--':-':"--C:X::)CX::J
.... [J~u @ I L@%.~
f',
11\
I
)I
I
By Local Bus Slave
"----'-<:-~~ .
,
"
By MPC106
Figure 4-10. Local Bus Slave Transaction
When tracking 60x bus status, note that the MPC 106 internal L2 cache controller does not
use standard 60x bus signaling during L2 cache cast-out operations (including L2 flush
operations generated by the L2 flush command.) The TS, AACK, or DBGn will not be
asserted on the 60x bus for L2 cache cast-out operations; under some conditions TA may
be asserted. Since the MPC 106 tracks the L2 cache cast-out cycle as a normal bus operation
internally, a following bus operation will be treated as a pipelined operation by the
MPC 106. The assertion of AACK for the following pipelined bus operation will be delayed
until the end of the L2 cache cast-out data tenure.
The encoding of the TT[0-4] bits of the MPCI06 do not reflect address-only transactions
during MPCI06-initiated snoop operations; however, all snoop operations initiated by the
MPCI06 should be considered as address-only operations. There will be no DBGn or TA
signal assertions by the MPCI06 for snoop operations initiated by the MPC106.
The 60x bus state diagram shown in Figure 4-11 is provided to facilitate the design of local
bus slave devices.
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MPC106 PCIBIMC User's Manual
MOTOROLA
~eod&~dbg&~ts
Legend:
• ..., --COndition shown is false
o
Ti-Idle
• aack-Address acknowledge
o
• dbr-Data bus r~uest as indicated by
TT[0-4) that the cycle is not
address only.
T1-Address phase in progress, data
phase not started yet.
o
T1a-Address phase in progress, data
phase completed. '
o
T1 b-Address phase and data phase in
progress.
• dbg-Data bus grant
o eod-End of data phase
• ts-Transfer start
• T1o-Address phase completed, data
phase not started yet.
o
T1 i-Address phase completed, data
phase in progress.
• T2a-Address pipelined, data phase
not started yet.
o
T2p-Address pipelined, data phase in
progress.
Figure 4-11. 60x Bus State Diagram
MOTOROLA
Chapter 4. Processor Bus Interface
4·23
Chapter 5
Secondary Cache Interface
A secondary (L2) cache provides the processor with faster access to instructions and data
by maintaining a subset of system memory in high-speed static RAM devices (SRAMs).
The MPC106 provides support for two L2 cache options'-an internally-controlled L2
cache and an external L2 cache controller (or integrated L2 cache module).
The internal L2 cache controller allows the system designer to implement a direct-mapped,
lookaside L2 cache in a write-back or write-through configuration with a cacheable address
space of up to 4 Gbytes. The MPC 106 supports L2 cache sizes of 256 Kbytes, 512 Kbytes,
and 1 Mbyte made up of either synchronous burst, pipelined burst, or asynchronous
SRAMs. The data path to the L2 cache is 64 bits wide. The L2 cache line size and coherence
granularity is 32 bytes.
The MPC 106 can perform fast nonpipelined bursts of 3-1-1-1 bus cycles and pipelined
bursts of 2-1-1-1 bus cycles to the internally-controlled L2 cache. When used with the
PowerPC 604 microprocessor in fast L2 mode, the MPCI06 can perform pipelined bursts
of 1-1-1-1 bus cycles to the internally-controlled L2 cache.
This chapter describes the L2 cache interface of the MPC 106--the various configurations,
operation, programmable parameters, and response to bus operations. Design and timing
examples are provided for several configurations.
Throughout this chapter, the following details should also be considered:
•
The MPC106 does not support caching PCI space with the internally-controlled L2.
•
L2 write-back operations to PCI space are illegal.
•
When configured for an externally-controlled L2, PCI space may be cached if no
write-back operations to PCI space occur.
•
L2 write-back operations to the system ROM space are illegal.
•
In emulation mode, L2 write-back operations to the interrupt vector relocation space
are illegal.
MOTOROLA
Chapter 5. Secondary Cache Interface
5-1
Chapter 2, "Signal Descriptions;' contains the signal definitions for the L2 cache interface
and Chapter 3, "Device Programming," details the configurable parameters that are used to
initialize the L2 cache interface. In addition, Chapter 8, "Internal Control," provides
information about the internal buffers that permit the MPC106 to coordinate memory
accesses between the L2 cache, the 60x processor(s), and devices on the PCI bus.
5.1 L2 Cache Configurations
The following sections describe the various L2 cache configurations that the MPC 106
supports.
5.1.1 Write-Back Cache Operation
The use of a write-back L2 cache offers several advantages over direct access to the
memory system. Since every Ll write operation does not go to main memory but to the L2
cache which can be accessed more quickly, write operation latency is reduced along with
contention for the memory system. Subsequent read accesses from the processor that hit in
the L2 cache are also expedited in comparison to the memory system. Write-back L2 cache
blocks implement a dirty bit in their tag RAM, which indicates whether the contents of the
L2 cache block have been modified from that in the memory system. L2 cache blocks that
have been modified (dirty bit set) will be written back to memory on L2 cache line
replacement, while unmodified L2 cache blocks will be invalidated and overwritten without
being cast out to memory.
5.1.2 Write-Through Cache Operation
Write-through L2 caches reduce read latency in the same way write-back L2 caches do, but
write operations from the primary (Ll) cache are written to both the L2 cache and the
memory system, thereby exhibiting the same latency as an ordinary memory write. A writethrough L2 cache keeps memory coherent with the contents of the L2 cache, and removes
the need for maintenance of a dirty bit in the tag RAM.
5-2
MPC106 PCIB/MC User's Manual
MOTOROLA
5.1.3 Synchronous Burst SRAMs
The internal L2 cache controller of the MPC 106 supports using synchronous burst SRAMs
as the L2 data RAMs. A typical implementation is shown in Figure 5-1.
MPC106
TAG RAM
A[(}-31)
L.CCR
r_----------r_----~A
~----------~----~D
~r_--~
r-----------r------~~
TWE
TV
WE
r_--~
r-------------.------~
""DIR""'TI"-_O"'U;';-T
TVI
DIRTY I
TVO -NC
DIRTY 0 1-------,
I
HIT~--~ ~----------------------------~I
MATCH
DIRTIJN~--~
~------------------------------~
BURSTSRAMs
BUFFER
I
L2A
I
(OPTIONAL)
?
r'-I_~
r_--+--~A
DCSr_--~
ADS
BAA
DOE
OWEn
~ADSP
r------------~~
ADSC
BAA
OE
WE
O[HS)
Figure 5-1. Typical L2 Cache Using Burst SRAM (Write-Back)
The MPCI06 provides five signals for interfacing to synchronous burst SRAMs. Burst
transactions consist of four beats, with 64 bits of data per beat. The data RAM latches the
address and DCS (data RAM chip select) inputs at the beginning of the access when ADS
(address strobe) is asserted. The DOE (data RAM output enable) signal is an asynchronous
signal that enables the driving of data onto the 60x data bus during read accesses. The BAA
signal, when asserted, advances the internal beat counter of the burst RAM. The DWEn
signals, when asserted, indicate that a write operation to the burst RAM is required. If the
MPCI06 is configured for partial update write timing (CF_WMODE = Ob01, ObIO, or
Ob 11), then external logic is required to decode which bytes of the double word should be
MOTOROLA
Chapter 5. Secondary Cache Interface
5-3
selected for the write to the L2 data RAM. The byte write enables can be decoded from the
DWEn, A[29-31], TBST, and TSIZ[0-2] signals.
5.1.4 Pipelined Burst SRAMs
The internal L2 cache controller of the MPC 106 supports using pipelined burst SRAMs as
the L2 data RAMs. Timing for pipelined burst SRAMs is very similar to burst SRAMs,
except BAA and TA are delayed to account for the extra pipeline delay for the pipelined
burst SRAM read accesses.
Typical applications only use the SRAM's ADSC input as shown in Figure 5-2. The fastest
possible cycle times are 4-1-1-1 for nonpipelined accesses and 1-1-1-1 for pipelined
accesses.
MPC106
-
TAG RAM
A(O-31]
D(H3]
L.mA
D
~
mE"
WE"
'!WE"
~
<
TV
DIRTY_OUT
TVI
DIRTY I
1
TVO r--NC
DIRTY 0
MATCH
R1T
tmm'Jff
PIPEUNED
BURSTSRAM
BUFFER
(OPTIONAL)
HA
I
L2A
B~
r-
I
I
A
~ ADSJS"
~
DeS"
' - - - CS2
.---- CS2
~
AIlS"
BAA
DOE"
DWE"n
BAA
~
WE"
~
D(<>----
L2A
A13
I
I
,-J~L-----'
I
I
r'--~---,
L....~
L.... ~
~C"S"
h.F-+---+l C"S"
ADSe"
1---------~~ADSe"
I-----l~
I-----l~m
I-----l~
1-----l~WE"
I---------~~m
OE"
I---------~~OE"
I--------~~WE"
D[G-63)
I
D[G-63)~
Figure 5-5. 512-Kbyte, Two-Bank, L2 Cache Using Synchronous Burst SRAM
(Write-Back)
5-8
MPC106 PCIB/MC User's Manual
MOTOROLA
MPC106
TAG RAM
A[(}-31]
-
0[0-63]
~Wi
c;
r-
~--------------4-------~A
~--------------4-------~D
TOE" 1----_
TWE"
TV 1----_1
""DIRB'I'TYv_"""OU;";'T
I-------------------I---------.t OE"
WE"
f---------------_f------~
TVI
DIRTY I
1
TVO t-NC
DIRTY 0 f - - - - - ,
MATCH
ffif~--_I
~~---I
I---------------------------------~
f-----------------------------------~
BUFFER
(OPTIONAL)
L2A
rBANKO
(
PIPELINED
BURSTSRAM
f
I
pA]=13---=2=<-S]-+--.t A
f---------J
f-----+~~
I---~~
,--~
A12
CS2
f'-=-----.t ~
ADS" ~--___i
"BAA
neE"
1---+~CS2
I---------=-------~ADSC
1---+-+1 ADSC
I---+~"BAA
BAA
OE"
WE"
DWrn
.-'-~---'
L.:.... ADSP"
.-- ADSP"
~I-----I
BANK 1
I---+~OE"
I---+~WE"
D[D-ro]
L
D[D-ro]~
Figure 5-6. 1-Mbyte, Two-Bank, L2 Cache Using Pipelined Burst SRAM (Write-Back,
ADSC Only)
5.2 Internal L2 Cache Controller Operation
This section describes the operation of the internal L2 cache controller. Section 5.6,
"External L2 Cache Controller Operation," describes the external L2 controller operation.
5.2.1 L2 Cache Addressing
The low-order address bits of the 60x address bus are connected to the address signals of
the tag RAM as the tag entry index. The high-order address bits are connected to the tag
RAM data signals. Depending on the cache size and size of the cacheable address space,
different bits from the 60x address bus should be connected to the tag RAM and data RAM.
Table 5-1 shows the address signals used by three L2 cache sizes in a 4-Gbyte cacheable
space. For smaller cacheable space, the tag RAM data width can be reduced by setting the
proper cast-out address mask (CF_CBA_MASK). For example, with a cache size of
MOTOROLA
Chapter 5. Secondary Cache Interface
5-9
512 Kbytes, an 8-bit tag RAM (plus the TV bit) can be used by masking off the five highorder address bits to provide a cacheable space of 128 Mbytes. See Section 3.2.7,
"Processor Interface Configuration Registers," for additional information about tag
configuration.
Table 5-1. 60x to Tag and Data RAM Addressing for 4-Gbyte Cacheable
Address Space
Tag Address
Tag Data
Data RAM Address
A[14-26] (13 bits)
A[Q-13] (14 bits)
A[14-28] (15 bits)
512 Kbytes
A[13-26] (14 bits)
A[Q-12](13 bits)
A[13-28] (16 bits)
1 Mbyte
A[12-26] (15 bits)
A[D-l1](12 bits)
A[12-28] (17 bits)
Cache Size
256 Kbytes
5.2.2 L2 Cache Line Status
The high-order address bits, TV, and DIRTY_OUT signals are used to update the tag RAM
and dirty RAM with new line status. The tag RAM and dirty RAM are updated at the
assertion of TWE.
The RESET signal to the tag RAM should initialize the L2 line status to the invalid and
unmodified state. If hardware initialization is not available, software can perform tag
initialization using the invalidate mode function prior to enabling the L2 interface. When
invalidate mode is enabled, any 60x transaction causes the L2 controller to invalidate the
tag entry indexed by the 60x address. Note that invalidate occurs regardless of the state of
the CF_L2_MP and CF_L2_EN parameters, as well as the state of the fiT and DIRTY_IN
signals. However, the L2 cache interface parameters, CF_L2_SIZE, CF_fiT_fiGH,
CF_MOD_HIGH, CF_L2_HIT_DELAY, and CF_HOLD, must be programmed for proper
tag write timings and proper valid and dirty bit polarity before using the invalidate mode.
5.2.3 L2 Cache Tag Lookup
When both the TWE and TOE signals are negated, the tag RAM is in tag lookup mode.
During 60x bus operations, L1 copy-back operations, and MPClO6-initiated snoop
operations, the MPCI06 uses the status of the HIT and DIRTY_IN signals to determine the
current L2 line status and responds accordingly. The polarity of the fiT and DIRTY_IN
signals is programmable.
The TV signal can be used with tag RAMs with separate 110 valid bits or one bidirectional
valid bit. Note that the TV signal is either released to a high-impedance state or always
driven during tag read operations depending on the parameters CF_HOLD and
CF_FAST_CASTOUT in PICR2. For tag RAMs with separate 110 valid bits, the TV signal
from the MPC106 is connected to the valid input of the tag RAM. The MPC106 does not
sample the TV signal as an input, so the valid output of the tag RAM can be left
unconnected. The TV signal is always asserted during the tag lookup, allowing the
MPC 106 to work with tag RAMs that use the TV signal input for the lookup comparison.
5-10
MPC106 PCIBIMC User's Manual
MOTOROLA
The TV signal is in a high-impedance state when the MPC106 is configured for a
uniprocessor system without an L2 cache, or a multiprocessor system.
5.2.4 L2 Cache Cast-Out Operations
For L2 cast-outs, the MPC106 normally drives ARTRY to retry the 60x processor
transaction that caused the L2 cast-out and performs a tag RAM and data RAM read to
retrieve the dirty address and data. After the tag RAM read completes, the processor restarts
the memory transaction that caused the cast-out. Since the tag RAM read takes a
considerable number of clock cycles, it delays the memory access. In the case of a
processor burst read that causes a cast-out, the MPC106 does not retry the processor read
transaction. Instead, the MPC 106 asserts AACK for the processor transaction, and starts the
L2 cast-out (tag RAM and data RAM read) and the memory read access in parallel. The
memory read output enable (CASn) signals are delayed until the L2 cast-out is completed.
This effectively overlaps the RASn access of the memory transaction with the L2 cast-out,
so the processor read data is ready as soon as the L2 cast-out is completed.
To get the address for L2 cast-outs, the MPC106 drives the low-order bits and asserts TOE.
The MPC 106 latches only the address bits from the tag data signals during tag read
transactions. The L2 cache line status is not used. Once the address is known for the line
being written to memory, the line status in the L2 tag must be updated. When configured
for normal cast-out timing (CF_FAST_CASTOUT = 0), the MPCI06 drives all the address
bits, TV, and DIRTY_OUT, and asserts TWE to perform the tag update. When configured
for fast cast-out timing (CF_FAST_CASTOUT = 1), the MPC106 performs the tag update
during the last clock of the tag read. In the fast cast-out mode, the TV and DIRTY_OUT
signals are driven when TOE is asserted, and TWE is asserted during the last clock cycle of
TOE to update the tag RAM status.
5.2.5 L2 Cache Parity
The MPCI06 internal L2 cache controller supports parity generation and checking for data
in the L2 cache. The parity signals from the L2 data RAMs connect to the 60xlmemory
parity signals. Parity generation and checking is controlled through the
L2_PARITY_ERROR_ENABLE parameter in error enabling register 2. Note that memory
parity checking/generation (MCCRl[PCKEND must also be enabled.
The parity signals are valid with the data on writes to the L2 data RAMs. When reading
from the L2 data RAMs, the MPC106 checks parity at the assertion ofTA.
Since the MPC106 uses the parity signals for ROM address bits during ROM accesses, L2
cache line fills from ROM cannot reflect correct parity. Therefore, the MPC 106 does not
perform parity checking during L2 cache read operations within the ROM address space.
Processor parity checking should be disabled when accessing the ROM address space to
avoid machine check exceptions or a checkstop state. Accesses to ROM in the PCI memory
space are not cached by the MPC 106.
MOTOROLA
Chapter 5. Secondary Cache Interface
5-11
5.2.6 L2 Cache Interface and Interrupt Vector Relocation
When the MPC106 is configured for interrupt vector relocation, all memory accesses from
OxFFFO_OOOO to OxFFFF_FFFF are translated to a I-Mbyte memory block lower in the
memory address space. The 12 most-significant bits of the address (OxFFF) of the 60x
memory access are replaced by the contents of ESCR 1[INT_ VECTOR_RELOCATE], and
the remaining 20 address bits are unchanged. Interrupt vector relocation presents special
problems with respect to the L2 cache and snooping. The L2 tag RAM sees only the
untranslated address (OxFFFx_xxxx) and uses the 60x bus address (prior to translation by
the MPCI06) for lookups and tag updates. Software must handle any coherency issues
regarding accesses to the original vector addresses and their translated locations.
Snooping always uses the original 60x interrupt vector address rather than the translated
(relocated) address. Software must maintain cache coherency if PCI devices access the
memory region used for vector relocation. Because the L2 cache uses the original vector
address, it treats the access as a normal system ROM space access with respect to
determining whether the data should be cached. If the system ROM space is located on the
PCI bus, the RAM region is not cached.
5.3 L2 Cache Response to Bus Operations
The MPC106 samples the WT, CI, GBL, ARTRY, HIT, and DIRTY_IN signals and
responds with the activity required by the bus operation. The internal L2 cache controller
only supports operations mapped in the system memory address space, and ignores
memory operations mapped in the PCI space. The internal L2 cache controller supports the
following four types of bus operations:
•
•
•
•
Norma160x bus operations (any 60x-initiated operations, with the exception of L1
copy-back operations)
60x L1 copy-back operations
L2 cast-out operations (when configured as a write-back cache)
Snoop operations due to PCI-to-system memory transactions, provided snooping is
enabled (PICR2[NO_SNOOP_EN] = 0)
The following sections describe the internal L2 cache controller responses to bus operations
in both write-back and write-through configurations.
5.3.1 Write-Back L2 Cache Response
When the MPC 106 is configured to support a write-back L2 cache, the L2 cache supplies
data on 60x single-beat or burst read hits, read snoop hits, and write snoop hits to modified
lines. L2 cache lines are updated on burst read misses, single-beat write hits (depending on
partial update configuration), or burst write hits, and burst write misses. Table 5-2 describes
5-12
MPC106 PCIBIMC User's Manual
MOTOROLA
the internal L2 cache controller response to normal 60x bus operations, L1 copy-back
operations, L2 copy-back operations, and PCI bus snoop operations.
Table 5-2. Write-Back L2 Cache Response
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2Hit
L2
Line
Status
NewL2
Line
Status
Hit
-
-
L2->CPU
Stop MEM access.
Miss
inv/um
um
MEM->L2->
um
MEM-> CPU
L2 Controller
Response
MPC106
Operation
Normal 60x Bus Operations
-,RlRWITM
xOx
B,RlRWITM
xOx
-
xOx
-
Miss
inv/um
-
-
MEM-> CPU
xOx
A
Miss
mod
-
If copy-back buffer
is available, L2->
CBB, MEM -> L2
If copy-back buffer
is not available, set
next state as
invalid.
Wait for L2 copyback mode.
If copy-back buffer
is available, L2 >CBB, MEM->
CPU/L2
If copy-back buffer
is not available,
stop MEM access.
Save low-order bit
address. ARTRY
the 60x read
transaction.
Goes to L2 copyback mode.
B,RlRWITM with
L2_UPDATE_EN
=0
B,RlRWITM
(106)
xOx
-
Miss
mod
-
-
MEM-> CPU
B,RWITM with
CF_RWITM_FILL =1
xOx
-
Miss
-
-
-
MEM-> CPU
SB,RlRWITM
xOx
Miss
-
-
-
MEM-> CPU
-,RlRWITM
x1x
-
Hit
um
inv
->invalid
MEMlPCI -> CPU
-,RlRWITM
x1x
A
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode.
Stop MEM access.
Save low-order bit
address. ARiRY
the 60x read
transaction.
Goes to L2 copyback mode.
Miss
-
-
MEMlPCI -> CPU
Hit
-
mod
CPU->L2->
mod
Stop MEM access.
B,RlRWITM with
L2_UPDATE_EN
=0
(106)
-,RlRWITM
x1x
B,W
OOx
-
OOx
-
Hit
-
inv
->invalid
CPU->MEM
10x
-
Hit
-
um
CPU->L2->
um
CPU->MEM
B,Wwith
L2_UPDATE_EN
B,W
MOTOROLA
=0
Chapter 5. Secondary Cache Interface
5-13
Table 5-2. Write-Back L2 Cache Response (Continued)
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2 Hit
L2
Line
Status
NewL2
Line
Status
B,Wwith
L2_UPDATE_EN = 0
10x
-
Hit
-
inv
-> invalid
CPU->MEM
B,W
OOx
-
Miss
inv/um
mod
CPU->L2->
mod
Slop MEM access.
OOx
-
Miss
inv/um
-
-
CPU->MEM
10x
-
Miss
Inv/um
um
CPU->L2->
um·
CPU->MEM
10x
-
Miss
inv/um
-
-
CPU->MEM
xOx
A
(106)
Miss
mod
-
Set next state as
invalid.
Wait for L2 copyback mode.
Stop MEM access.
Save low-order bit
address. ARTRY
the 60x write
transaction.
Goes to L2 copyback mode.
xOx
-
Miss
mod
-
-
CPU->MEM
SB, W with partial
update
OOx
-
Hit
-
mod
CPU->L2->
mod
Stop MEM access.
SB, W with partial
update and
L2_UPDATE_EN = 0
OOx
-
Hit
um
inv
->invalid
CPU->MEM
SB, W with partial
update and
L2_UPDATE_EN = 0
OOx
A
(106)
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode.
Stop MEM access.
Save low-order bit
address. ARTRY
the 60x write
transaction.
Goes to L2 copyback mode
SB, W with partial
update
10x
-
Hit
um
-
CPU->L2
CPU->MEM
SB, W with partial
update and
L2_UPDATE_EN = 0
10x
-
Hit
um
inv
->invalid
CPU->MEM
SB, W with partial
update
10x
A
(106)
Hit
mod
-
Set next state as
um.
Wait for L2 copyback mode.
Stop MEM access.
Save low-order bit
address. ARTRY
the 60x write
transaction.
Goes to L2 copyback mode.
B,Wwith
L2_UPDATE_EN
=0
B,W
B,Wwith
L2_UPDATE_EN
5-14
MPC106
Operation
=0
B,W
B,Wwith
L2_UPDATE_EN
L2 Controller
Response
=0
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 5-2. Write-Back L2 Cache Response (Continued)
Bus Operation
(Slngle.Beat or
Burst, Read or
Write)
WIM
ARTRY
L2Hit
L2
Line
Status
NewL2
Line
Status
SB, W with partial
update
xOx
-
Miss
-
-
-
CPU->MEM
SB, W without partial
update
xOx
-
Hit
um
inv
-> invalid
CPU->MEM
SB, W without partial
update
xOx
A
(106)
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode.
Stop MEM access.
Save low-order bit
address. ARTRY
the 60x write
transaction.
Goes to L2 copyback mode
-,W
x1x
-
Hit
um
inv
-> invalid
CPU -> MEM/PCI
B,W
x1x
-
Hit
mod
inv
-> invalid
CPU -> MEMlPCI
SB,W
x1x
A
(106)
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode
Stop MEM access.
Save low-order bit
address. ARTRY
the 60x write
transaction.
Goes to L2 copyback mode.
-,W
x1x
Miss
-
-
-
CPU -> MEMlPCI
-,Clean
xOx
-
Hit
um
-
-
-
-,Clean
xOx
A
(106)
Hit
mod
-
Set next state as
um.
Wait for L2 copyback mode.
Save low-order bit
address. End the
Clean address
phase. ARTRY
any pending 60x
address phase.
Goes to L2 copyback mode.
-,Clean with
CF_ADDR_ONLY_
DISABLE 1
xOx
-
Hit
mod
-
-
-
-,Clean
XOx
-
Miss
-
-
-
-,Clean
x1x
-
Hit
um
inv
-,Clean with
CF_ADDR_ONLY_
DISABLE 1
x1x
-
Hit
um
-
-
-
L2 Controller
Response
MPC106
Operation
=
=
MOTOROLA
Chapter 5. Secondary Cache Interface
5-15
Table 5-2. Write-Back L2 Cache Response (Continued)
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2 Hit
L2
Line
Status
NewL2
Line
Status
-,Clean
x1x
A
(106)
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode
Save low-order bit
address. ARiFiY
the 60x
transaction.
Goes to L2 copyback mode
-,Clean with
CF_ADDR_ONLY_
DISABLE = 1
x1x
-
Hit
mod
-
-
-
-,Clean
x1x
-
-
-
-
xOx
-
Miss
-,Flush
Hit
um
inv
-> invalid
-,Flush with
CF_ADDR_ONLY_
DISABLE =1
xOx
-
Hit
um
-
-
-
-,Flush
xOx
A
(106)
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode.
Save low-order bit
address. ARTRY
the 60x
transaction.
Goes to L2 copyback mode.
-,Flush with
CF_AD DR_ONLY_
DISABLE =1
xOx
-
Hit
mod
-
-
-
-,Flush
xOx
-
Miss
-
-
-
-,Flush
x1x
-
Hit
um
inv
->invalid
-,Flush with
CF_ADDR_ONLY_
DISABLE =r
x1x
-
Hit
um
-
-
-
-,Flush
x1x
A
(106)
Hit
mod
-
Set next state as
invalid.
Wait for L2 copyback mode
Save low-order bit
address. ARTRY
the 60x
transaction.
Goes to L2 copyback mode
-,Flush with
CF_ADDR_ONLY_
DISABLE =1
x1x
-
Hit
mod
-
-
-
-,Flush
x1x
Miss
-
-
-
-
-,KiIl/ICBI
xOx
-
Hit
-
inv
->invalid
Invali.date internal
buffers if hit.
5-16
L2 Controller
Response
MPC106 PCIB/MC User's Manual
MPC106
Operation
MOTOROLA
Table 5-2. Write-Back L2 Cache Response (Continued)
Bus Operation
(Slngle-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2Hlt
L2
Line
Status
NewL2
Line
Status
-,KiIIl ICBI with
CF_ADDR_ONLY_
DISABLE 1
xOx
-
Hit
-
-
-
Invalidate internal
buffers if hit.
-,KiII/ICBI
xOx
-
Miss
-
-
-
Invalidate internal
buffers if hit.
-,KiII/ICBI
x1x
-
Hit
-
inv
-> invalid
Invalidate internal
buffers if hit.
-,KiII/ICBI with
CF_ADDR_ONLY_
DISABLE 1
xOx
-
Hit
-
-
-
Invalidate internal
buffers if hit.
-,KiII/ICBI
x1x
-
Miss
-
-
-
Invalidate internal
buffers if hit.
-
Hit
-
PCI
read
snoop:
um
I! PCI read snoop,
replace line with
CPU copy-back
data.
->um
MPC106 detects a
60x snoop-push to
the snooped
address and does
not assert ARTRY.
I! PCI read or PCI
read w/lock, run
60x transaction
and send data to
memory and PCI.I!
PCI write, run 60x
transaction and
merge 60x data
with PCI write data
and write to
memory. Exit L 1
copy-back mode.
I! in loop-snoop
mode, repeat
snoop.
L2 Controller
Response
=
=
MPC106
Operation
L 1 Copy-Back Operations
-
xxx
PCI
read wI
lock or
PCI
write
snoop:
inv
MOTOROLA
I! PCI read wI lock
or write snoop: L2
->invalid
Chapter 5. Secondary Cache Interface
5-17
Table 5-2. Write-Back L2 Cache Response (Continued)
Bus Operation
(Single-Beat or
Burat, Read or
Write)
WlM
AR'i'RY
L2Hlt
L2
Line
Status
NewL2
Line
Status
xxx
-
Hit
-
PCI
read,
PCI
read wI
lock,
PCI
write:
inv
-> invalid
MPC106 detects a
SOx snoop-push to
the snooped
address and does
not assert Am'RY.
If PCI read or PCI
read wI lock, run
60x transaction
and send data to
memory and PCI.lf
PCI write, run 60x
transaction and
merge 60x data
with PCI write data
and write to
memory. Exit L 1
copy-back mode.
If in loop-snoop
mode, repeat
snoop.
-
xxx
-
Miss
-
-
-
MPC106 detects a
60x snoop-push to
the snooped
address and does
not assert ARTRY.
Run 60x
transaction. If PCI
read or PCI read wI
lock snoop, send
data to memory
and PCI. If PCI
write, send PCI
data to memory.
Exit L 1 copy-back
mode.
If in loop-snoop
mode, repeat
snoop.
-
xxx
A
(106)
-
-
-
-
MPC106 detects a
60x snoop-push
that does not
match the snooped
address. MPC106
asserts ARTRY to
retry 60x
transaction. Exit
L 1 copy-back
mode. If in loopsnoop mode,
repeat snoop.
-with
L2_UPDATE_EN
5-18
=0
L2 Controller
Response
MPC106 PCIBIMC User's Manual
MPC106
Operation
MOTOROLA
Table 5-2. Write-Back L2 Cache Response {Continued}
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2Hit
L2
Line
Status
NewL2
Line
Status
-
-
-
L2 Controller
Response
MPC106
Operation
um/inv
Send dirty address
onto address bus.
Burst data onto
data bus. -> next
state.
Grant address bus
to L2. Capture
copy-back
address. Grant
data bus to L2.
Send L2 data to
memory.
Enter normal
mode.
L2 Copy·Back Operations
-
-
PCI Bus Snoop Operations
-,-
xx1
A
(SOx)
-
-
-
-
If 60x asserts SR
in the window of
opportunity, then
save snoop type
(PCI read, read wI
lock, or write).
Enter L 1 copy-back
mode. Grant bus to
6Ox.
Else if no BR
assertion, repeat
snoop.
-,R
xx1
N
(SOx)
Hit
-
-
L2->MPC10S
L2-> PCI.
-,R
xx1
N
(SOx)
Miss
-
-
-
MEM->PCI.
-,W
xx1
N
(SOx)
Hit
um
inv
->invalid
PCI->MEM.
-,WNK
xx1
N
(SOx)
Hit
mod
inv
L2 -> MPC10S,
->invalid
L2 data merge with
PCI data -> MEM.
-,WK
xx1
N
(SOx)
Hit
mod
inv
->invalid
PCI->MEM.
-,W
xx1
N
(SOx)
Miss
-
-
-
PCI->MEM.
Key:
A
N
RWNITC
W
WK
inv
um
MOTOROLA
Asserted
Negated
Read-with-no-intent-to-cache
Write-with-flush, write-with-flush-atomic,
write-with-kill
Write-with-kill
Invalid
Unmodified
B
R
RWITM
WNK
-,x
mod
SB
Burst
Read, Read-atomic, RWNITC
Read-with-intent-to-modify, RWITM atomic
Write-with-flush, write-with-flush-atomic
Input don't care
Modified
Single-beat
Chapter 5. Secondary Cache Interface
5-19
5.3.2 Write-Through L2 Cache Response
When the MPC106 is configured to support a write-through L2 cache, the L2 cache
supplies data on 60x single-beat or burst read hits, and read snoop hits. L2 cache lines are
updated on burst read misses, single-beat write hits (depending on partial update
configuration), or burst write hits, and burst write misses. Table 5-3 describes the internal
L2 cache controller response to normal60x bus operations, Ll copy-back operations, and
PCl bus snoop operations.
Table 5-3. Write-Through L2 Cache Response
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2 Hit
NewL2
Status
L2 Controller
Response
MPC106
Operation
Normal 60x Bus Operations
-,RlRWITM
xOx
-
Hit
-
L2->CPU.
5top MEM access.
B, RlRWITM
xOx
-
Miss
urn
MEM->L2->
urn
MEM-> CPU
B, RlRWITM with
L2_UPDATE_EN =0
xOx
-
Miss
-
-
MEM-> CPU
B, RWITM with
CF_RWITM_FILL =1
xOx
-
Miss
-
-
MEM-> CPU
5B, RlRWITM
xOx
-
Miss
-
MEM-> CPU
-,RlRWITM
01x
-
Hit
inv
-,RlRWITM
01x
-
Miss
B,W
xOx
-
Hit
-
CPU-> L2
CPU->MEM
xOx
-
Hit
inv
->invalid
CPU->MEM
xOx
-
Miss
urn
CPU-> L2
CPU->MEM
xOx
-
Miss
-
-
CPU->MEM
5B, W with partial
update
xOx
-
Hit
-
CPU-> L2
CPU->MEM
5B, W with partial
update and
L2_UPDATE_EN =0
xOx
-
Hit
inv
->invalid
CPU->MEM
5B, W without partial
update
xOx
-
Hit
inv
->invalid
CPU->MEM
SB,W
xOx
-
Miss
-
-
CPU->MEM
-,W
x1x
-
Hit
inv
CPU -> MEMlPCI
-,W
x1x
-
Miss
-,Clean
xOx
-
-
-
-
B, Wwith
L2_UPDATE_EN
=0
B,W
B, Wwith
L2_UPDATE_EN
5-20
=0
MPC106 PCIBIMC User's Manual
MEM/PCI -> CPU
MEM/PCI -> CPU
CPU -> MEMlPCI
-
MOTOROLA
Table 5-3. Write-Through L2 Cache Response (Continued)
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
-, Clean
x1x
-, Clean with
CF_ADDR_ONLY_
DISABLE = 1
x1x
-,Clean
x1x
-, Flush
xOx
-, Flush with
CF_ADDR_ONLY_
DISABLE = 1
xOx
-, Flush
xOx
-, Flush
x1x
-, Flush with
CF_ADDR_ONLY_
DISABLE = 1
x1x
-, Flush
x1x
-,KilVICBI
xOx
-, KilVICBI with
CF_ADDR_ONLY_
DISABLE = 1
xOx
-, KilVlCBI
xOx
-, KilVICBI
x1x
-, KilVICBI with
CF_ADDR_ONLY_
DISABLE = 1
-,KilVICBI
NewL2
Status
L2 Controller
Response
MPC106
Operation
ARTRY
L2Hlt
-
Hit
inv
->invalid
Hit
-
-
-
Miss
-
-
Hit
inv
->invalid
Hit
-
-
-
Miss
-
-
Hit
inv
->invalid
Hit
-
-
-
-
Miss
-
-
-
Hit
inv
->invalid
(Invalidate buffer)
Hit
-
-
(Invalidate buffer)
-
Miss
-
-
(Invalidate buffer)
Hit
inv
->invalid
(Invalidate buffer)
x1x
-
Hit
-
-
(Invalidate buffer)
x1x
-
Miss
-
-
(Invalidate buffer)
-
Hit
PCI read
snoop:
um
If PCI read snoop,
CPU->L2
MPC106 detects a SOx
snoop-push to the
snooped address. If
PCI read, or PCI read
wI lock, send CPU data
to memory and PCI. If
PCI write, merge CPU
data with PCI data and
send merged data to
memory. Exit L 1 copyback mode. If loopsnoop mode, repeat
snoop.
L 1 Copy-Back Bus Operations
-,-
xxx
PCI read
wI lock, or
PClwrite
snoop:
inv
MOTOROLA
If PCI read wI
lock, or PCI write
snoop:
L2 -> invalid
Chapter 5, Secondary Cache Interface
5-21
Table 5-3. Write-Through L2 Cache Response (Continued)
Bus Operation
(Single-Beat or
Burst, Read or
Write)
NewL2
Status
L2 Controller
Reaponse
MPC106
Operation
ARTRY
L2Hlt
xxx
-
Hit
PCI read,
PCI read
wI lock, or
PClwrite
snoop:
inv.
->invalid
MPC106 detects a 60x
snoop-push to the
snooPed address. If
PCI read, or PCI read
wI lock, send CPU data
to memory and PCI. If
PCI write, merge CPU
data with PCI data and
send merged data to
memory. Exit L1 copyback mode. If loopsnoop mode, repeat
snoop.
,
xxx
-
Miss
-
-
MPC106 detects a 60x
snoop-push to the
snooped address. If
PCI read, or PCI read
wI lock, send CPU data
to memory and PCI. If
PCI write, merge CPU
data with PCI data and
send merged data to
memory. Exit L1 copyback mode. If loopsnoop mode, repeat
snoop.
,
xxx
A
(106)
-
-
-
MPC106 detects a 60x
snoop-push that does
not match the snooped
address. MPC106
asserts ARTRY to retry
the 60x transaction.
Exit L1 copy-back
mode. If loop-snoop
mode, repeat snoop.
-,-with
L2_UPDATE_EN
=0
WIM
PC! Bus Snoop Operations
,
xx1
A
(60x)
-
-
-
If the 60x asserts SA" in
the window of
opportunity, then save
snoop-type (PCI read,
PCI read wI lock, or PCI
write); Enter L1 copyback mode; grant bus to
60x. Else repeat snoop.
-,R
xx1
N
(6Ox)
Hit
-
L2-> MPC106
L2->PCI
-,R
xx1
N
(6Ox)
Miss
-
-
MEM->PCI
5-22
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 5-3. Write-Through L2 Cache Response (Continued)
Bus Operation
(Single-Beat or
Burst, Read or
Write)
WIM
ARTRY
L2 Hit
NewL2
Status
L2 Controller
Response
MPC106
Operation
-,W
xx1
N
(60x)
Hit
inv
-> invalid
PCI->MEM
-,W
xx1
N
(60x)
Miss
-
-
PCI->MEM
Key:
A
N
RWNITC
W
WK
inv
um
Asserted
Negated
Read-with-no-intent-to-cache
Write-with-flush, write-with-flush-atomic,
write-with-kill
Write-with-kill
Invalid
Unmodified
B
R
RWITM
Burst
Read, read-atomic, RWNITC
Read-with-intent-to-modify, RWITM atomic
WNK
Write-with-flush, write-with-flush-atomic
Input don't care
Modified
Single-beat
-,X
mod
SB
5.4 L2 Cache Interface Parameters
The L2 cache interface parameters, located in PICRI and PICR2, allow the MPC106 to
support a variety ofL2 cache configurations and timings. The MPC106's default power-up
configuration holds the L2 cache disabled so that system software can program all the L2
cache interface parameters prior to enabling the L2 interface. Some of the parameters only
affect the internal L2 cache controller interface, while others affect both the internal L2
cache controller interface and external L2 cache controller interface.
The following sections describe the L2 cache interface parameters. Refer to Chapter 3,
"Device Programming," for additional information about the specific programming of the
L2 cache interface parameters.
5.4.1 L2 Cache Interface Control Parameters
The L2 cache interface control parameters control specific operations of the L2 cache
interface, and can be modified whether the internal L2 cache interface is enabled or
disabled. The L2 cache interface control parameters are:
•
CF_EXTERNAL_L2-Specifies if the external L2 cache interface is enabled.
•
CF_L2_MP-Specifies single or multiprocessor configuration, and write-through or
write-back L2 cache interface configuration.
•
L2_UPDATE_EN-Specifies if the internally-controlled L2 cache can be updated.
This L2 parameter can also be set through port Ox81 C.
•
L2_EN-Specifies if the internal L2 cache interface is enabled. Can also be
configured through port Ox81 C. Note that the CF_L2_MP parameter must also
indicate a single processor with write-back or write-through L2 cache configuration
to enable the internal L2 cache controller.
MOTOROLA
Chapter 5. Secondary Cache Interface
5-23
•
CF_FLUSH_L2--'-Setting this configuration parameter causes the internal L2 cache
controller to flush all modified lines to memory, and to invalidate all L2 cache lines.
This configuration parameter can also be accessed through port Ox81 C. Note that an
L2 flush can only occur if the internal L2 cache controller is enabled.
Note that L2_UPDATE_EN, CF_FLUSH_L2, and L2_EN have no effect on the external
L2 cache controller operation. However, it is possible for the external L2 cache controller
to monitor these parameters at port Ox81C and use them to perform similar functions.
5.4.2 L2 Cache Interface Initialization Parameters
The L2 cache interface initialization parameters control the configuration and operational
behavior of the L2 cache interface, and can only be changed when the L2 cache interface
is disabled. These parameters must be set properly before the L2 cache is enabled and the
L2 cache interface must be disabled before modifying these parameters.
The L2 cache interface initialization parameters are as follows:
•
CF_CBA_MASK-Specifies which bits of the dirty address read from the tag RAM
are valid. For systems requiring less than 4 Gbytes of cacheable space, this
parameter allows the tag RAM width to be reduced. See Section 5.2.1, "L2 Cache
Addressing," for more information on this parameter. Note that this parameter also
affects the external L2 cache controller interface.
•
CF_CACHE_IG-Specifies the memory space cached by L2 cache. Note that this
parameter also affects the external L2 cache controller interface.
•
CF_FAST_L2_MODE-Specifies if fast L2 mode timing is enabled. The use of fast
L2 mode is supported only by the 604. Note that this parameter also affects the
external L2 cache controller interface.
•
CF_DATA_RAM_TYPE-Specifies the type of SRAM used by the L2 cache.
•
CF_WMODE-Specifies L2 data RAM write timing and partial update mode. See
Section 5.4.2.4, "CF_ WMODE," for more information on this parameter.
•
CF_MOD_HlGH-Specifies the polarity of the DIRTY_IN, DIRTY_OUT, and TV
signals.
.
•
CF_HIT_HIGH-Specifies the polarity of the HIT signal for the internal L2 cache
controller interface only. Note that the HIT signal is always active low for the
external L2 cache controller interface, regardless of the state of CF_HIT_HIGH.
•
CF_ADDR_ONLY_DISABLE-Specifies whether the internal L2 controller
responds to address-only transactions (Clean, Flush, and Kill).
•
CF_HOLD-Specifies the hold time of the address, TV, and DIRTY_OUT signals
with respect to the rising edge of the TWE signal.
5-24
MPC106 PCIB/MC User's Manual
MOTOROLA
•
CF_INV_MODE-The L2 cache invalidate enable mode is used to initialize the tag
contents before enabling the L2 cache in cases where hardware initialization of the
tag and dirty RAM is not available. To flush the L2 cache, the CF_FLUSH_L2 (or
port Ox81 C[CF_FLUSH_L2]) configuration parameter can be set. See
Section 5.2.2, "L2 Cache Line· Status," for more information on this parameter.
•
CF_RWITM_FILL-Controls whether the internally-controlled L2 cache performs
a line-fill when an RWITM miss occurs. See Section 5.3, "L2 Cache Response to
Bus Operations," for more information.
•
CF L2 HIT_DELAY-Specifies the earliest valid sampling point for the HIT and
DIRTY_IN signals. Note that this parameter also affects the external L2 cache
controller interface. See Section 5.4.2.1, "CF_L2_HIT_DELAY," for more
information on this parameter.
•
CF_TWO_BANKS-Specifies the number of banks of L2 data RAM. See
Section 5. 1.6, ''Two-Bank Support," for more information on using two banks ofL2
data RAM.
•
CF_FAST_CASTOUT-'-Specifies timing of L2 cast-out operation. See
Section 5.2.4, "L2 Cache Cast-Out Operations," for more information on fast castout timing.
•
CF_TOE_WIDTH-Specifies the width of the active TOE pulse during L2 cast-out
tag read operations. Note that this parameter also affects the external L2 cache
controller interface.
• , CF_L2_SIZE-Specifies L2 cache size.
•
CF_DOE-Specifies the timing relation between the assertion of DOE and valid L2
data. See Section 5.4.2.2, "CF_DOE," for more information on this parameter.
•
CF_ WDATA-Specifies ADSC-only or ADSP mode for pipelined burst SRAM
configurations or the write pulse timing for asynchronous SRAM configurations.
See Section 5.4.2.3, "CF_WDATA," for more information on this parameter.
5.4.2.1 CF_L2_HIT_DELAY
CF_L2_HIT_DELAY specifies the earliest valid sampling point of the HIT and DIRTY_IN
signals from the assertion ofTS. CF_L2_HIT_DELAY can be configured for a one, two, or
three' clock delay. For best performance, (3-1-1-1 nonpipelined, and 2-1-1-111-1-1-1
pipelined), CF_L2_HIT_DELAY should be configured for a delay of one clock cycle. Note
that the MPC106 may not sample the HIT and DIRTY_IN signals at the earliest sampling
point, so these signals should be held valid as long as the address is valid. Note that
CF_L2_HIT_DELAY controls the sampling point of the HIT signal for external L2 cache
configurations. Figure 5-7 shows the earliest sampling points selected by the configuration
of CF_L2_HIT_DELAY.
MOTOROLA
Chapter 5. Secondary Cache Interface
5-25
60xBus Clock
JULrL.rlI1JL
IIII
TS" ~
I
I
I
I
I
I
I
I
I
I
I
R1TmlIiTYJI'f ~
Figure 5-7. HIT and DIRTY_IN Delay Configuration
5.4.2.2 CF_DOE
CF_DOE specifies the time from DOE assertion to the data valid access time of the L2 data
RAM for the first data beat. If CF_DOE is cleared to 0, one clock cycle is selected. If
CF_DOE is set to 1, two clock cycles are selected. If CF_DOE is set to 1, then the MPC 106
will try to assert DOE speculatively at the end of the assertion of TS as long as DBGn is
asserted in order to mininuze the effect of the extra clock delay on read hits. Figure 5-15
and Figure 5-16 in Section 5.5, "L2 Cache Interface Timing Examples," show synchronous
burst SRAM read timing with CF_DOE = 0 and 1, respectively.
When using asynchronous SRAM, CF_DOE controls the first data beat access time of
pipelined read transactions. Clearing CF_DOE to 0 provides 3-2-2-2/2-2-2-2 burst read
timing, and setting CF_DOE to 1 provides 3-2-2-2/3-2-2-2 burst read timing. Figure 5-24
and Figure 5-25 in Section 5.5, "L2 Cache Interface Timing Examples," show
asynchronous SRAM read timing with CF_DOE =0 and 1, respectively.
5.4.2.3 CF_ WDATA
When using synchronous burst SRAMs, the CF_WDATA parameter is reserved and must
be cleared to O.
When using pipelined burst SRAMs, the CF_ WDATA parameter configures the internal L2
cache controller for ADSC-only or ADSP mode. See Section 5.1.4, "Pipelined Burst
SRAMs," for more information on the two pipelined burst SRAM configurations.
When using asynchronous SRAMs, CF_WDATA controls the write pulse timing. If
CF_WDATA is cleared to 0, DWEn is negated on the falling edge of the clock cycle in
which TA is asserted. If CF_WDATA is set to 1, DWEn and TA are negated on the same
rising edge of the clock during cache line fills from memory. If CF_ WDATA is set to 1, and
the transaction is not a cache line fill from memory, the DWEn signals are negated on the
falling edge of the clock in which TA is asserted (that is, the same timing as when
CF--'WDATA is cleared to 0).
Figure 5-26 and Figure 5-27 in Section 5.5, "L2 Cache Interface Timing Examples," show
asynchronous SRAM write data set-up timing with CF_WDATA = 0 and 1, respectively.
Note that when using asynchronous SRAMs, there must be sufficient data hold time when
CF_ WDATA is set to 1. It is recommended that the memory system employ a latChed
memory buffer that holds data valid for one clock after TA when CF_WDATA = 1. Also,
5-26
MPC106 PCIBIMC User's Manual
MOTOROLA
the fastest cache line fill from memory is 3-3-3-3 when CF_WDATA =1. Memory timing
must be programmed accordingly.
5.4.2.4 CF_ WMODE
CF_WMODE selects one of three L2 data RAM write timings or normal write timing
without partial update. The following sections describe each of these settings.
5.4.2.4.1 Normal Write Timing without Partial Update (CF_WMODE =0)
When CF_ WMODE is set to 0 (ObOO), normal write timing without partial update is
selected. In this mode, the MPCl06 can only update an entire double word at a time; it
cannot issue single-byte writes to the L2 cache because there is no external byte decode
logic present. Figure 5-9 shows normal write mode timing for pipelined and nonpipelined
bus transactions with CF_ WMODE set to 0, and CF_L2_HIT_DELAY set to 1.
Note that asynchronous SRAM configurations must use CF_WMODE =O.
5.4.2.4.2 Normal Write Timing (CF_ WMODE =1)
When CF_WMODE is set to 1 (ObOl), normal write timing with partial update is selected.
The MPC106 assumes external byte decode logic is implemented with no external delays
on the DWEn signals.
Figure 5-8 shows the logic required for external byte decode that requires
CF_WMODE =1.
REGISTERED PAL
-
A[2~31],
TSIZ[()-2],
COMBINATION DECODE
Latched A[2~,
TSIZ[()-2],
TllSf,ADS
DATA RAM
r---
WE"]()-1]
WE"]()-1]
sox Bus Clock
~n
'---
Figure 5-8. External Byte Decode Logic Requiring CF_WMODE = 1
Figure 5-9 shows the normal write mode timing associated with Figure 5-8 for pipelined
and nonpipelined bus transactions with CF_ WMODE set to 0 or 1, and
CF_L2_HIT_DELAY set to 1.
MOTOROLA
Chapter 5. Secondary Cache Interface
5-27
60x Bus Clock
1
1
60xAddress
~
1
1
1
u:
1
1
~:,
}
60x Data (MPC106)
TA
ADS"
1
1
1
\:
1
I
1
\:
\:
WE" (L2 Data RAM)
I
0:
ft"\:
I
1
1
~
I'
1
\1
1
1
1
I
1
1
1
I
I
I
~I
I
1
~
I
\LJI
1
1
\LJI
1
1
tlWE"n
1
ft"\:
1
~
~
1
1
~
1
1
rlCS"
NONPIPElINED
PIPELINED
Figure 5·9. Normal Write Timing (CF_WMODE
=0 or 1)
=
5.4.2.4.3 Delayed Write Timing (CF_ WMODE 2)
When CF_ WMODE is set to 2 (OblO), one clock cycle of delayed write timing is provided,
allowing for one level of external logic for byte selection. Figure 5-10 shows the logic
required for external byte decode that requires CF_ WMODE to be set to 2.
REGISTERED PAL
r--
DATA RAM
REGISTERED PAL
r---
Latched A(2~
TSIZ[o-2],
WE"[o-7]
WE"[o-7]
60x Bus Clock
'---
Figure 5-10. External Byte Decode Logic Requiring CF_WMODE
=2
Figure 5-11 shows the write mode timing associated with Figure 5-10 for pipelined and
nonpipelined bus transactions with CF_ WMODE set to 2, and CF_L2_HIT_DELAY
set to 1.
5-28
MPC106 PCIB/MC User's Manual
MOTOROLA
60x Bus Clock
TS"
I
I
I
I
AACK -r--r--r~~~:--~~--'-~~~:--~~--~~-
60xAddress
60x Dam (MPC106)
~,-'______---,
-;--7-{~~=:::X:::JC=X:::J
TA
ADS"
-L...---"-",\ I
BAA"
I
I
\I.l.:_-I------'_...J. ---I01.l.:_--'---'_...J'---J~
,:
rl---'-----'---'---'---;
\:......../1
I
r'_--'---'_-1----11_
\:......../1
' """'\\..,.:OWE n --'--'--ir-
WE" (l2 Dam RAM)
C~=~=~>-):..'--~~--~~-
I
:-..,.---t---l0::
....
I
IT
\I.l.:_...J.i_--'-----L'---I!t\I.l.:_...J.i_-I----I'---Jr
-I---I----I----JI...........
~--~~~~~'-"'\'
I
I
I
I
\L'
__.----,...J(II\L,_..,.--r---lfl,
T
I
I
T
~....
: __'----'-...J1:
DeS"
NONPIPELINED
PIPELINED
Figure 5-11. Delayed Write Timing (CF_WMODE
=2)
5.4.2.4.4 Early Write Timing (CF_WMODE = 3)
When CF_WMODE is set to 3 (Ob 11), early write timing is provided, and DWE is asserted
speculatively one clock cycle early to provide better write performance. Note that early
write timing is not supported for synchronous pipelined SRAMs when ADSP is used.
Figu~ 5-12 shows the logic required for external byte decode that requires CF_WMODE
to be set to 3.
DATA RAM
REGISTERED PAL
r-A[2~11. TSIZ[G-21.
TBSi,AD!. ~n
WE"[O -7J
WE[G-7J
60x Bus Clock
'---
C!
Figure 5-12. External Byte Decode Logic Requiring CF_WMODE
=3
Figure 5-13 shows the early write mode timing associated with Figure 5-12 for pipelined
and nonpipelined bus transactions with CF_WMODE set to 3, and CF_L2_HIT_DELAY
setto 1.
MOTOROLA
Chapter 5. Secondary Cache Interface
5-29
60x Bus Clock
1
1
1
1
1
1
1
-'--r--r,~~:-~-r~~~:~~-r--r--r--~~
60x Address ~,-LI_-'---'-,}-~_(
60x Data (MPC106)
'fA
_;--;--<=~
1
1
<'
') I
1
1
1
1
1
1
~
1
,...:.1_-'----'-_
I
'.,..,
(~
''r--''r-''r--'
i
_
:
':
'--'--, 1
II
I
-,-I_-'----'----''--, I
ADS
'\lJi
1
1
OWE"n -,---,,---.. 1
'r--''r--''r--''r--'
'~:
1
I:
-.,...--r-
1
.L1_-'-----'-__.1...---'---" 1
1
,J--
' 1\ l1J I \ . ! - - ! -11 11
1
\;---r-T---r--'
WE(L2Data RAM)
1
,:,
1
1
hu..:__-'-----'-__J........J~
1
1
"BAA -+--:-----+-~,,.......\"_!-'---r~fII\
T
~
1
1
II
I,
1
1
NONPIPELINED
1
,
1
1
1
PIPELINED
Figure 5-13. Early Write Timing (CF_WMODE
1
1
ABORTED
=3)
5.5 L2 Cache Interface Timing Examples
The figures in the following sections provide examples of the internal L2 cache controller
interface signal timing in the course of cache read hits, cache write hits, cache line updates,
L2 cache cast-out operations, and snoop operations. L2 cache timing examples are provided
for a cache implemented with synchronous burst SRAMs and asynchronous SRAMs.
The symbols shown in Figure 5-14 are applicable to all the figures in the following sections.
_
Invalid, don't care, or unknown
o
Valid
~
Address driven by MPC106
e2J
Address driven by tag RAM
Figure 5-14. Timing Diagram Legend
5.5.1 Synchronous Burst SRAM L2 Cache Timing
The following sections provide timing examples for L2 cache operations in systems
implemented using synchronous burst SRAM.
5.5.1.1 L2 Cache Read Hit Timing
Figure 5-15 shows the L2 interface timing for a read hit in the L2 cache. The L2 cache
configuration parameters CF_APHASB_WS, CF_L2_HIT_DELAY, and CF_DPARK are
set to 1, and CF_DOE is cleared to O.
5-30
MPC106 PCIBIMC User's Manual
MOTOROLA
BOx Bus Clock
I
\.lJ
AACK
A[(}-31]
--<. . .
I
1
:
:
Rii • •
llBGn
I
:
I
IYI
I
I
\.lJ I
I
I
I
I
I
r-<=::=:=~~I
.
)~I~I~I~I~I~I
I
. 1
I
I
1
I
1
1
1
I \ Ij I
I II
I
I
I
I
I
I
I
I
I
I
CIJj!iU~I~!lI~C._ • • • • •
I I I
I
I
I
I
\1
I
I
Data
fA
y:
ADS"
y:
~n
I
BAA
I
I
I
I
;-t"\ I
\1
I
\1
DOE
rr-r
(T\I
~~
I
II
I
I
I
~
Figure 5-15. L2 Cache Read Hit Timing with CF_DOE = 0
Figure 5-16 shows the L2 interface timing for a read hit with configuration parameters,
CF_APHASE_WS, CF_L2_HIT_DELAY, CF_DPARK, and CF_DOE set to 1.
60x Bus Clock
AACK
A[(}-31]
HIT
llBGn
I
I
I
I IYI
I\.JJI
I I\.JJI
I
1
--<
:
:
:
I
I
I
I
I
I
_.e._.c._.____
I
I
I
I
I
I
I
>--C~:)~=::X:~~C~~=>C~X~=:x:::::~=X=::=
BAD,BAI
A(G-31]
(Latched)
14I~~~~~~~::~~~~~~::~~~~~~~~
WI
Figure 5-25. L2 Cache Burst Read Timing with CF_DOE
=1
5.5.2.2 L2 Cache Burst Read Line Update Timing
Figure 5-26 shows the L2 interface timing for an L2 cache line update during a burst read
operation. The L2 cache configuration parameter CF_WDATA is cleared to O.
60x Bus Clock
TS"I
mK I-+---r--~
A(G-31] :
..~__
ml . . . .~~-"Br,-~~~~r-II~~~
Dam
I-~~.~C;::~
TA II_+-...l---L.----l__~
r-'-~
mE" I
Figure 5-26. L2 Cache Burst Read Line Update Timing with CF_WDATA
5-40
MPC106 PCIBIMC User's Manual
=0
MOTOROLA
Figure 5-27 shows the L2 interface timing for an L2 cache line update during a burst read
operation. The L2 cache configuration parameter CF_ WDATA is set to 1.
60x Bus Clock
A[0-31]
m"~~~MB~~Ii~~~~-tIG"~~
Data
-';-~.~-C::=:::;
Figure 5-27. L2 Cache Burst Read Line Update Timing with CF_WDATA = 1
5.5.2.3 Burst Write Timing
Figure 5-28 shows the L2 interface timing for an L2 cache line update during a burst write
operation. Note that the timing is the same for CF_ WDATA 0 or CF_WJ;>ATA 1.
=
"
=
60x Bus Clock
TS'
"IJlJK
A[0-31]
m
Data
BAO,BAI
A[0-31]
(\.a1ched)
Figure 5-28. L2 Cache Burst Write Timing with CF_WDATA
MOTOROLA
Chapter 5. Secondary Cache Interface
=0 or 1
5-41
5.6 External L2 Cache Controller Operation
The MPCI06 can support an external L2 cache controller in uniprocessor as well as multi·
processor configurations. Figure 5·29 shows a typical system configuration with an
external L2 cache. Note that the signal connections to the external L2 cache controller may
vary depending on the external L2 cache implementation.
MPC106
BRO
BR
!!GO
!l(j
])000
DBG
SMT
r-
-
~
TS". A[Q-31J.~,
~
T-mQ-M T
Q.ffi. BL,AA K,TA
60xO
INT
is, A[Q-31~0-4J.
TSI~~
Q. WT. BL,-mK.TA
I-
:=
I-
DH[Q-31J. DL[Q-31J.
PAR[Q-7]
~
I--
DH[Q-31J, DL[Q-31J.
PAR[Q-7]
IDi,MCP
I--
~
TEA.MCP
XA'fS
ARTRY
NMI
Il
XA'fS
~
I--
~
SHl)
-
NMf
SMiT
llRf
BGf
I-I-I--
DBGf
a.----
~
~O-k.1J.m.
PEtCSEro-m~
ciWp .6OT.
iIBB" Dlil3 NlW6.
e~A~~~R~
I
E
,K P.N
I--
BR
I-
!l(j
DBG
SMT
I--
60x 1
INT
Bffi2
BGIT
I-
BR
l-
f-
!l(j
I--
I-
~
I-
DBG
TS". A[Q-31~0-41.
~
I-
~
SHl)
~
f-
DH[Q-31J. DL[Q-31J.
PAR[Q-7]
l-
f-
l:2WJM
I--
DBGl2
TSI~~
• BL,AACK,TA
Q,
XA'fS
f-
ARTRY
TEA
HRESEI
HIT
a.---- iIBB", DBB
DRTRY •TAGCiJf,
l----
FiJJSH 12 EN.
L2 UPDATE. EN
ETC.
I
L2
CONTROLS
If.lTO0
~
HRESEI
EXTERNALL2
o Tied to Voo through a resistor individually.
All bidirectional signals should have a pull-up resistor.
Figure 5-29. Typical External l2 Cache Configuration
5-42
MPC106 PCIB/MC User's Manual
MOTOROLA
5.6.1 External L2 Cache Operation
When an externally-controlled L2 cache is used, the MPC106 samples the HIT input signal
when CF_L2_IDT_DELAY expires. For 60x cycles, if HIT is asserted, the external L2
cache drives AACK and TA to complete the transaction without the MPC106 initiating a
system memory transfer. The external L2 cache can assert ARTRY to retry 60x cycles, and
requests the bus through BRL2 to perform L2 cast-out operations. The MPC106 grants the
address and data bus to the external L2 cache by asserting BGL2 and DBGL2, respectively.
The external L2 cache must qualify the BGL2 by ARTRY and take care not to take the bus
in the ARTRY window or the window of opportunity. If the external L2 cache asserts
ARTRY, it should not assert HIT. If the external L2 cache asserts ARTRY, it should assert
ARTRY on or before the clock cycle when HIT is valid and hold ARTRY asserted until one
clock after AACK.
If the external L2 cache asserts ARTRY for a snoop push, it should assert BRL2 in the
ARTRY window as well as in the window of opportunity. If a processor also asserts bus
request in the window of opportunity, the MPCI06 will grant the bus to the processor (an
L1 snoop push has the highest priority and always takes precedence over an L2 snoop
push). If a processor does not request the bus in the window of opportunity, the bus will be
granted to the external L2 cache. Since a processor can assertARTRY without asserting bus
request (even though it has dirty data), the snoop has to be repeated after the external L2
cache snoop push until ARTRY is not asserted. A system using an external L2 cache
controller must operate with snoop looping enabled (PICR1[CF_LOOP_SNOOP] =1).
For a PCI read snoop, the external L2 cache snoop push data will be forwarded to PCI as
well as to memory. For a normal PCI write (not write-with-invalidate) snoop, the external
L2 cache push data will be merged with the PCI data. Then, the result will be written to
memory. For a PCI write-with-invalidate snoop, the external L2 cache should invalidate the
cache line without a snoop push.
5.6.2 External L2 Cache Controller Interface Parameters
The CF_EXTERNAL_L2 and CF_L2_MP parameters are used to enable and disable the
MPC106's external L2 cache controller interface. The following L2 cache interface
parameters, described in Section 5.4, "L2 Cache Interface Parameters," should be set
properly before the external L2 cache controller interface is enabled:
•
•
•
•
•
CF_L2_HIT_DELAY
CF_TOE_WIDTH
CF_CBA_MASK
CF_FAST_L2_MODE
CF_CACHE_IG
Note that the external L2 cache modes are selected by the CF_EXTERNAL_L2 and
CF_L2_MP parameters only. The external L2 cache controller interface is enabled
whenever the external L2 cache modes are selected and disabled whenever the external L2
MOTOROLA
Chapter 5. Secondary Cache Interface
5-43
cache modes are not selected-the L2_EN parameter has no effect on the external L2 cache
controller interface. Care should be exercised when enabling or disabling the external L2
cache controller interface on the MPC106. The external L2 cache must not claim any
transaction (by asserting HIT) when the MPC106's external L2 cache controller interface
is disabled.1)rpically, the external L2 cache controller interface on the MPC106 is enabled
before the external L2 cache is enabled and the external L2 cache is disabled before the
external L2 cache controller interface on the MPC 106 is disabled.
5-44
MPC106 PCIB/MC User's Manual
MOTOROLA
Chapter 6
Memory Interface
The memory interface of the MPC 106 controls processor and PCI interactions with system
memory. It is capable of supporting a variety of DRAM, EDO, or SDRAM, and ROM or
Flash configurations as main memory. Note that only one of the RAM interfaces (DRAM,
EDO, or SDRAM) can be used in a system; that is, a system cannot mix DRAM and EDO
devices.
This chapter describes the memory interface on the MPCI06--its features and limitations,
buffering requirements, supported device organizations, initialization, and timing. Design
examples are provided for the DRAM, EDO, SDRAM, ROM, and Flash interfaces.
Chapter 2, "Signal Descriptions," contains the signal definitions for the memory interface,
and Chapter 3, "Device Programming;' details the configurable parameters that are used to
initialize the memory interface. In addition, Chapter 8, "Internal Control," provides
information about the internal buffers that permit the MPC 106 to coordinate memory
accesses between the L2 cache, the 60x processor(s), and devices on the PCI bus.
6.1 Overview
The DRAMIEDO/SDRAM interface supports up to eight banks of 64-bit memory. Bank
sizes up to 128 Mbytes provide for a maximum memory size of 1 Gbyte. Programmable
parameters allow for a variety of DRAMIEDO/SDRAM organizations and timings. Note
that if SDRAM is used, it must comply with the JEDEC specification for SDRAM. Two
types of parity as well as ECC protection are provided for the DRAMIEDO.
The MPC 106 handles parity checking and generation, with eight parity bits checked or
generated for the 64-bit data path. Read-modify-write (RMW) parity is also provided for
write transactions less than the full 8-byte data path. As an alternative to parity, the MPC 106
supports ECC for the data path to DRAMIEDO system memory. Note that the MPC106
does not support ECC for SDRAM memory configurations. Using ECC, the MPC106
detects and corrects all single-bit errors, and detects all double-bit errors and all errors
within a nibble.
The DRAMIEDO/SDRAM interface provides for doze, nap, sleep, and suspend power
saving modes, defined in Appendix A, "Power Management."
MOTOROLA
Chapter 6. Memory Interface
6-1
The ROMlFlash interface supports one or two banks of ROMlFlash memory on the
60x/memory bus. Bank sizes up to 8 Mbytes provide for a maximum ROMlFlash memory
size of 16 Mbytes. The ROM space may also be mapped to the PCI bus or split between the
60x/memory bus and the PCI bus.
6.2 Memory Interface Signal Buffering
To reduce loading on the data bus, most system designs will require buffering between the
60x data bus and the memory data bus. The MPC 106 features configurable data buffer
control logic to accommodate flow-through, transparent latch, or registered data buffers.
This section describes the different buffer control configurations of the MPC 106. Note that
in addition to the data and parity signals, certain other memory interface signals may also
require buffering. The AC characteristics of the MPCI06, memory operating frequency,
capacitive loading, and transmission line effects of the board layout dictate which signals
require buffering, and which buffer devices are appropriate. The example design in
Figure 6-4 uses bidirectionaVtri-state drivers on the data and parity signals.
The BCTLO and BCTLl signals control the data bus buffers (directional control and
high-impedance state). The buffer mode parameter (MCCR2[BUF_MODE]) controls how
the buffer control signals, BCTLO and BCTLl, operate. The memory buffer type
parameters (MCCR4[WCBUF] and MCCR4[RCBUF]) determines the type of buffer used
and the data synchronization for that buffer type. Table 6-1 shows the parameter settings for
the different configurations and gives examples of typical buffer devices that might be used
in those configurations.
Table 6-1. Buffer Configurations
BCTU
RCBUF
BUF_MODE
0
0
0
Flow-through
WE
"RE
5417416863
0
0
1
Flow-through
DIR
(WIR)
OE
54n416245,
54n4162245,
54n4163245
0
1
0
Transparent latch
WI:
"RE
54n416543,
54n4162543
0
1
1
-
DIR
(WiR)
OE
-
1
0
0
WE
"RE
1
0
1
-
DIR
(wIR)
OE
-
1
1
0
Registered
WE
RE
54n416952,
54n4162952
54n416601
1
1
1
-
DIR
(WIR)
OE
-
6-2
Buffer Type
BCTI])
WCBUF
MPC106 PCIBIMC User's Manual
Typical Buffer Device
MOTOROLA
6.2.1 Flow-Through Buffers
Both the WCBUF and RCBUF parameters should be cleared to indicate a flow-through
buffer configuration. The MPC 106 supports two protocols for the buffer control signals,
BCTLO and BCTLl. The buffer mode parameter, BUF_MODE, determines which protocol
the buffer control signals use.
The default protocol (BUF_MODE = 1) uses BCTLO as a direction control signal (writes
active high/reads active low), and BCTLl as a buffer output enable signal (active low).
Buffers that are compatible with this protocol include the 5417416245, 54174162245, and
54174163245. These buffers are available from several manufacturers. Connections to this
buffer device should be made as shown in Figure 6-1.
~-------------------------,
5417416245
DIR
60xdata ~~~--'---I >--H---------,
A'
I
I
I
I-----*-----;'~ Memory
I
IB
data
Figure 6-1. Flow-Through Buffer
The alternate protocol (BUF_MODE = 0) uses BCTLO as a buffer write enable signal
(active low), and BCTLl as a read enable signal (active low). The 5417416863, available
from several manufacturers, is compatible with this protocol.
6.2.2 Transparent Latch Buffers
The WCBUF parameter should be cleared and the RCBUF parameter should be set to
indicate the transparent latch configuration. The BCTLO, BCTLl and MOLE signals
control the buffer. The BCTLO signal acts as a buffer write enable signal, and BCTLl acts
as a read enable signal. MDLE is used to latch the buffer to provide additional data hold
time, as might be required by an asynchronous L2 cache (refer to the MDLE waveform
shown in Figure 6-7). Note that SDRAM memory systems cannot use latched buffers
because the SDCAS signal is multiplexed with the MDLE signal.
Buffers that are compatible with the transparent latch configuration include the 5417416543
and 54174162543. These buffers are available from several manufacturers. Connections to
the buffer device are shown in Figure 6-2.
MOTOROLA
Chapter 6. Memory Interface
6-3
I
I
0EliA
I
"CEllA
0CT[f-----;-1='-'---0
5417416543
MDLE"_+-----lI....:UBA=BA'----C1
BCTLO _+-----lI....:O::.::E::.::AB=---C1
I~
I
LEAB
C
GND
D
60x data ...f-----------4~~O
~l,_--'__::":":":':_=,-'-----\,-~--'---'-__::~--'----'---'---\,_--'I
JRCBUF = 1
1
-AA--AA--AA--AA_
U
1
I
I
1
r--+ RAC
I
I
I""
I
Note: ~ is driven only if RCBUF
1
1
1
: ICAC ~ICAC
I
I
I
1
1
I
I
CAC
1
1
~ICAC
I
I
=1.
Figure 6-7. DRAM Burst Read Timing-No ECC
MOTOROLA
Chapter 6. Memory Interface
6-15
60x Bus Clock
J
I
~
I
I
I
I
I
I
I;AS!I CP4 I CASsl CP4 I CASsl CP4 I CASSI
_CRP _ _ RCD 2-'
------
I
:
Ie
I
MemAddress
I
I
---,----:-::~X
I
;
,
Ir-"\
Ir-"\
Ir-"\
1,'--+---+--1
~ I"---{
I~ ---J '----(
~RSH
~ CSH ~I
I
r
I
R~~-:::::r
dp·
I
ROW
X
r:::-
COL
X
COL
X
COL
ASR~.,.A~~---.rCAH I_ICAH
Data
~
I
I
~RAD
I
I
I
DATAO
I
I
I
I
X,.....:..::..:=-...::..-.....,C,..,..OL---I
DATA1
I
I}
I
I
D~~
DATA2
I
,
I
I
RCBUF=O
DISABLED
READ
X --....,.-----....,.-----....,.-.:-...:-=c-=--~-c---::~~~:::~~X~_..,.-.....,
~'--"":;='==;=----""'f\"""I
I
I
I
I
I
I
I
I
I
I
I
Data
"""BCTL"""'O,""""BCfr.rL1
=D.
DAT~
I
I
I
;~
; X'----T-"'FISAB=.:;LEr-jD-1~'----r;
I
I
I
I
I
I
I
I
I
I
I
I
L~A_I
,
I}
I
i
__r--'---r;R~EAD;,-;---,-----r--;~h
~RAC.--!Je
I
I
CAC'
Lk_1
Me
---tI
, CAC'
I
I
RCBUF = 1
I
I
I
I
I
~ Me---tI
, CAC '
, CAC
I
Note: liIDCE is driven only if RCBU F = 1.
Figure 6-8. EDO Burst Read Timing-No ECC
6-16
MPC106 PCIBIMC User's Manual
MOTOROLA
60x Bus Clock
_RP 1 - - R A S
I
I RC I
I...
m-
--l-----JV
I
~
I
I
_CRP_...
I
--t---1C1 cP:
I
MemAddress
-'---'--...,X
I
RCD2
I
I
I CAS31
~" ....
~
: ~Wr--SH-+--i
r---r~~
ROW
X'--'=:"'-C-OL---
ASR ~-i+--JCAH
Data
-.--,----r:._RAH--tR;~~j_:~r----'--...J
I
I
~
I
I
I
DISABLED
I
: ?
I
I
I
I
X
I
I
WRITE
X,----
I
I
I
I
I
I
I
I
__
I
====~~~~V--,-~~~~ ~~v-l
I
I--t WP +--I
I
I
I ... WCS ~IWCHI
Note: M[)[E' remains negated during wrHes to DRAM.
Figure 6-9. DRAM Single-Beat Write Timing-No ECC
MOTOROLA
Chapter 6. Memory Interface
6·17
SOx Bus Clock
J--, RP 1, ]101'" I
I
I ]101
1\ I I
I
I V,--'--,--,
I I I I RCD2 I I I I CP4+1 I CASS-II CP4+11 CASS-II CP4+1 I CASS-II
_CRP_~ ..... CAS3~----------~
I
I
I
I
I I
I I
I Ir+-t--i
-Li
I
I
I
I
I
I
I
I
MemAddress
I
Data
:
:
l3C'f[Q, Brn1
XX
I
MDIT"
WE
U
~~V
I
I
I
I
I
I
I
I
~~~~~~~~~~~~~~~~~I~VIII
I!J",
WCS
WCH
]10 1---1-J--1--- WP .-I---+---+-+-+--+--!-I-.!]IoI
IWCSIWCHI I
I
I
Nole thai if CPX = I, CP4 and CAS s are automatically adjusted by one cycle during write bursts to allow greater
data propagation lime. Also, note that MDLE remains negated during writes to DRAMIEDO.
Figure 6-10. DRAM/EDO Burst Write Timing-No ECC, CPX = 1
6.3.5 DRAM/EDO Burst Wrap
The MPCI06 supports burst-of-four, double-word data beats for accesses to system
memory. The burst is always sequential, and the critical double word is always supplied
first. For example, if the 60x requests the third double word of a cache line, the MPC 106
reads double words from memory in the order 2-3-0-1.
6.3.6 DRAM/EDO latency
Table 6-6 summarizes the estimated DRAM latency (in processor cycles) for a burst read
operation. The first number is the number of processor clock cycles from the assertion of
TS by the 60x processor to the time the first data is returned; the next three numbers are the
number of clock cycles for the subsequent three data beats. The latency calculations assume
ECC has been disabled, RAS has been precharged, the MPC 106 is idle, and the 60x
processor and the MPC 106 are operating at the same frequency.
6-18
MPC106 PCIB/Me User's Manual
MOTOROLA
Table 6-6. Estimated DRAM Latency
DRAM
Access
Time
60 ns
70ns
System
Timing
Processor Bus Frequency
25 MHz
33 MHz
SO MHz
66MHz
Aggressive
(lightly loaded)
5-2-2-2
5-2-2-2
6-3-3-3
7-3-3-3
Conservative
(heavily loaded)
6-2-2-2
6-2-2-2
7-3-3-3
8-4-4-4
Aggressive
(lightly loaded)
5-2-2-2
5-3-3-3
7-3-3-3
8-4-4-4
Conservative
(heavily loaded)
6-2-2-2
6-3-3-3
8-3-3-3
9-4-4-4
Table 6-7 summarizes the estimated EDO latency (in processor cycles) for a burst read
operation. The first number is the number of processor clock cycles from the assertion of
TS by the 60x processor to the time the first data is returned; the next three numbers are the
number of clock cycles for the subsequent three data beats. The latency calculations assume
ECC has been disabled, RAS has been precharged, the MPC106 is idle, and the 60x
processor and the MPC106 are operating at the same frequency.
Table 6-7. Estimated EDO Latency
EDO
Access
Time
60 ns
System
Timing
Processor Bus Frequency
25 MHz
33 MHz
SO MHz
66MHz
Aggressive
(lightly loaded)
5-2-2-2
5-2-2-2
6-2-2-2
7-2-2-2
Conservative
(heavily loaded)
6-2-2-2
6-2-2-2
7-2-2-2
8-3-3-3
6.3.7 DRAM/EDO Page Mode Retention
Under certain conditions, the MPC106 retains the currently active DRAMIEDO page by
holding RAS asserted for pipelined burst accesses. These conditions are:
•
A pending transaction (read or write) hits the currently active DRAMIEDO page.
•
There are no pending refreshes.
•
The maximum RAS assertion interval (controlled by PGMAX) has not been
exceeded.
Page mode can dramatically reduce access latencies for page hits. Depending on the
memory system design and timing parameters, using page mode can save three to four
clock cycles from subsequent burst accesses that hit in an active page. Page mode is
disabled by clearing the PGMAX parameter (that is, PGMAX = OxOO).
MOTOROLA
Chapter 6. Memory Interface
6-19
6.3.8 DRAM/EDO Parity and RMW Parity
When configured for DRAM or EDO, the MPC 106 supports two forms of parity checking
and generation-normal parity and read-modify-write (RMW) parity. Normal parity
assumes that each of the eight parity bits is controlled by a separate CAS signal. Thus, for
a single-beat write from PCI to system memory, the MPC 106 generates a parity bit for each
byte written to memory.
RMW parity assumes that all eight parity bits are controlled by a single CAS signal and
therefore must be written as a single 8-bit quantity (that is, a byte). Therefore, for any write
operation to system memory that is less than a double word, the MPC 106 must latch the
write data, read an entire 64-bit double word from memory, check the parity of the double
word read from memory, merge the write data with the double word read from memory,
regenerate parity for the new double word, and finally write the new double word back to
memory.
The MPCI06 checks parity on all memory reads, provided parity checking is enabled
(PC KEN = 1). The MPC106 generates parity for the following operations:
•
•
•
•
PCI to memory write operations
L1 and L2 copy-back operations
L2 cast-out operations
60x single-beat write operations with RMW parity enabled (RMW_PAR
=1)
The 60x processor is expected to generate parity for all other 60x to memory write
operations as the data goes directly to memory and does not pass through the MPCI06.
6.3.8.1 RMW Parity latency Considerations
When RMW parity is enabled, the time required to read, modify, and write increases
latency for some transactions.
For 60x processor single-beat writes to system memory, the MPC 106 latches the data,
performs a double-word read from system memory (checking parity), and then merges the
write data from the processor with the data read from memory. The MPC 106 then generates
new parity bits for the merged double word and writes the data and parity to memory. The
read-modify-write process adds six clock cycles to a single-beat write operation. If page
mode retention is enabled (PGMAX;f:. 0), then the MPC106 will keep the memory in page
mode for the read-modify-write sequence. Figure 6-13 shows DRAMIEDO timing for a
60x single-beat write operation with RMW parity enabled.
For PCI writes to system memory with RMW parity enabled, the MPC106 latches the data
in the internal PCI-to-system-memory-write buffer (PCMWB). If the PCI master writes
complete double words to system memory, the MPC106 generates the parity bits when the
PCMWB is flushed to memory. However, if the PCI master writes 32-, 16-, or 8-bit data
that cannot be gathered into a complete double word in the PCMWB, a read-modify-write
operation is required. The MPC106 performs a double-word read from system memory
(checking parity), and then merges the write data from the PCI master with the data read
6-20
MPC106 PCIB/MC User's Manual
MOTOROLA
from memory. The MPC106 then generates new parity for the merged double word and
writes the data and parity to memory. If page mode retention is enabled (PGMAX '" 0), the
MPC106 keeps the memory in page mode for the read-modify-write sequence.
Since the processor drives all eight parity bits during 60x burst writes to system memory,
these transactions go directly to the DRAMs with no performance penalty. All other
transactions are unaffected and operate as in normal parity mode.
6.3.9 ECC
As an alternative to simple parity, the MPC 106 supports ECC for the data path between the
MPC106 and system memory. ECC not only allows the MPC106 to detect errors in the
memory data path, but also allows the MPC 106 to correct single-bit errors in the 64-bit data
path. The ECC logic in theMPC 106 detects and corrects all single-bit errors and detects all
double-bit errors and all errors within a nibble. Other errors may be detected, but are not
guaranteed to be corrected. Multibit errors are always reported. However, when a single-bit
error occurs, the single-bit error counter register is incremented and its value compared to
the single-bit error trigger register. If the values are not equal, no error is reported; if the
values are equal, then an error is reported. Thus, the single-bit error registers may be
programmed such that minor faults with memory are corrected and ignored, but a
catastrophic memory failure generates an interrupt.
The MPC106 supports concurrent ECC for the DRAMJEDO data path and parity for the
60x processorIL2 cache data path. ECC and parity may be independently enabled or
disabled. The eight signals used for ECC (PAR[0-7]) are also used for 60x processorIL2
cache parity. The MPC106 checks ECC on all memory reads (provided ECC_EN = 1), and
generates parity on all 60x processor reads that are latched by the L2 cache (provided
PC KEN = 1). The parity path and data path buffers effectively isolate the ECC (106 to/from
memory) transactions from the parity (106 to/from 60xIL2) transactions.
6.3.9.1 DRAM/EDO Interface Timing with ECC
When ECC is enabled, the time required to check/generate the ECC codes increases access
latency. Figure 6-11 through Figure 6-13 illustrate DRAMJEDO timing for various types of
accesses with ECC enabled; see Figure 6-11 for a DRAM burst read operation, Figure 6-12
for an EDO burst read operation, and Figure 6-13 for a single-beat write operation.
For processor burst reads from system memory, checking the ECC codes for errors requires
an additional two clock cycles for the first data returned, and at least four clock cycles for
subsequent beats. If an asynchronous L2 cache is used in the system, then the subsequent
beats require a minimum of five clock cycles. These requirements do not depend on the
buffer type or whether DRAM or EDO is used for system memory.
MOTOROLA
Chapter 6. Memory Interface
6-21
For 60x processor single beat writes to system memory, the MPC 106 latches the data,
performs a double-word read from system memory (checking and correcting any ECC
errors), and merges the write data from the processor with the data read from memory. The
MPC106 then generates a new ECC code for the merged double word and writes the data
and ECC code to memory. This read-modify-write process adds six clock cycles to a
single-beat write operation. If page mode retention is enabled (PGMAX "# 0), the MPC 106
keeps the memory in page mode for the read-modify-write sequence.
For 60x processor burst writes to system memory, the MPC106 latches the data in the
internal copy-back buffer and flushes the buffer to memory at the earliest opportunity. The
MPC106 generates the ECC codes when the flush occurs. Note that the MPC106 does not
check the data being overwritten in memory.
For PCI writes to system memory with ECC enabled, the MPC 106 latches the data in the
internal PCI to memory write buffer (PCMWB). If the PCI master writes complete double
words to system memory, the MPC 106 generates the ECC codes when the PCMWB is
flushed to memory. However, if the PCI master writes 32-, ·16-, or 8-bit data that cannot be
gathered into a complete double word in the PCMWB, a read-modify-write operation is
required. The MPC106 performs a double word read from system memory (checking and
correcting any ECC errors), and then merges the write data from the PCI master with the
data read from memory. The MPC106 then generates a new ECC code for the merged
double word and writes the data and ECC code to memory. If page mode retention is
enabled (PGMAX"# 0), the MPC106 keeps the memory in page mode for the
read-modify-write sequence.
6-22
MPC106 PCIS/MC User's Manual
MOTOROLA
~
60x Bus Clock
mJfl\
I
~..J
Mem Address
DRAM Data
I
I
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I DATAO DATAO I DATAl I DATAl I DATA2 IDATA2 DATA3 DATA3
I
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,
,
,
I
I
I
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Device driving SOx data bus =
I
I
'0
I
,
I
+: ~ + ~ +: ~ +
I
60x Data Bus
I
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X
DISABLED (HI-Z)
TA
,
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U
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RCBUF=O
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DATAO DATAl
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I DATA2 DATA3
I DATA3 I
MPC106 DRAM
MPC106 DRAM
MPC106 DRAM
MPC106 I
I
I
I
I
60x Data Bus
DRAM
Device driving SOX data bus =
I
I
I
I
I
I
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I
I
I
I
I
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I
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RCBUF=l
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TA
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~~
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n
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Figure 6-11. DRAM Burst Read with ECC
MOTOROLA
Chapter 6. Memory Interface
6-23
BOx Bus Clock
Mem Address
DRAM Data
I DATAO I
I DATA1
I DATA2 I
I DATA3 I
1 I
1
1 I
1 I
1
1 I
1
1 DATAO 1DATAO 1DATA1 1DATA1 1 DATA2 1DATA2 1DATA3 1DATA3
BOx Data Bus
Device driving BOx data bus =
1DRAM
MPC106 1DRAM MPC106 1 DRAM MPC106 1DRAM MPC106 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
~ ~I~~~~~~~~__~~~~~~~~~~~~~~~~
(inactive)
1
~~j~4-~~~~~~~4-~~+-~~~~
Notes:
RCBUF must be programmed to zero for systems with EDO and ECC.
t;;;[5[E will be inactive for this configuration.
Figure 6-12. EDO Burst Read Timing with ECC
BOx Bus Clock
m
I
m
Mem Address
DRAM Data
I
1
1
1\
1
~
C?L
cpL
J'
1
BOx Data Bus
1
1
1
1
;CEq
1
1
1
1
1
1
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:)
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1
--t=:
Device driving ~ data b~S =
1
~
X
DISABLED (HI·Z)
1
1
1
TA
1
1
1
~
~
7
I
1
1
(
1
~
1
tR
~
~
1
1
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)
MPC106
1 DRAM,
, BOX 1
1
W[O,BCTL1
(
1
:
1
1
READ
)[8ED(
1
1
1
1
1
1
1
1
1
1
1
I
I
~
I
I
I
WRITE
X
I
r,
Figure 6-13. DRAM Single-Beat Write Timing with RMW or ECC Enabled
6-24
MPC106 PCIB/MC User's Manual
MOTOROLA
6.3.10 DRAM/EDO Refresh
The memory interface supplies CAS before RAS (CBR) refreshes to DRAMIEDO
according to the refresh interval, MCCR2[REFINT]. The value stored in REFINT
represents the number of 60x bus clock cycles required between CBR refreshes. The value
for REFINT depends on the specific DRAMlEDOs used and the operating frequency of the
MPC 106. The value should allow for any potential collisions between DRAMIEDO
accesses and refresh cycles. The period of the refresh interval must be greater than the
access time to insure that read and write operations complete successfully.
If a burst read is in progress at the time a refresh operation is to be performed, the refresh
waits for the read to complete. In the worst case, the refresh must wait the number of clock
cycles required by the longest programmed access time. The value stored to REFINT
should be the number of clock cycles between row refreshes reduced by the number of
clock cycles required by the longest access time (to allow for potential collisions).
For example, given a DRAM with 4096 rows and a cell refresh time of 64 ms, the number
of clocks between row refreshes would be 64 ms + 4096 rows = 15.6I!s.lfthe 60x bus clock
is running at 66 MHz, the number of clock cycles per row refresh is 15.6 I!s x 66 MHz =
1030 clock cycles. If the number of clock cycles for the longest burst access time is 24
clocks, then the value stored in REFINT would be ObOO_OOll_lllO_111O (in decimal,
1030 - 24 = 1006).
6.3.10.1 DRAM/EDO Refresh Timing
The refresh timing for DRAMIEDO is controlled by the programmable timing parameter
MCCR3[RAS 6P]' RAS 6P determines the number of 60x bus clock cycles that RAS is held
asserted during a CBR refresh. The MPC106 implements bank staggering for CBR
refreshes, as shown in Figure 6-14; see Table 6-5 for the acronyms used in Figure 6-14. The
acronyms with subscripted numbers represent the programmable timing parameters of the
MPCI06.
MOTOROLA
Chapter 6. Memory Interface
6-25
60x Bus Clock
riAS"[O,7]
"FlA$[I, S]
riAS"[2,5]
riAS"[3, 4]
.
;
\1,
/:I
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/:
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=1-8 cycles
=As configured for readiwrite timing
RASSp
RPI
Figure 6-14. DRAMIEDO Bank Staggered CBR Refresh Timing
System software is responsible for optimal configuration of RAS 6P at reset. The
configuration process must be completed before any accesses to DRAMIEDO are
attempted. Table 6-8 represents suggested refresh timing configurations for Motorola
DRAM technology. The actual values used by initialization software depend upon the
specific memory technology used in the system.
Table 6-8. Suggested DRAM Refresh Timing Configurations
RAS6P
Processor Frequency
6-26
70 ns
60ns
25 MHz
2
2
33 MHz
3
2
50 MHz
4
3
66 MHz
5
4
MPC106 PCIB/MC User's Manual
MOTOROLA
6.3.10.2 DRAM/EDO Refresh and Power Saving Modes
The MPC 106 memory interface provides for doze, nap, sleep, and suspend power saving
modes defined in Appendix A, "Power Management."
In doze and nap power saving modes and in full-on mode, the MPC106 supplies the normal
CBR refresh to DRAMIEDO. In sleep mode, the MPC106 can be configured to take
advantage of self-refreshing DRAMIEDOs, provide normal refresh to DRAMlEDO, or
provide no refresh support. In suspend mode, the MPC 106 can be configured to take
advantage of self-refreshing DRAMIEDOs, provide CBR refreshes based on the RTC input
signal, or provide no refresh support. Normal refresh is not available for DRAMIEDO in
suspend mode. Table 6-9 summarizes the refresh types available in each of the power
saving modes and the relevant configuration parameters.
Table 6-9. DRAMIEDO Power Saving Modes Refresh Configuration
Power
Saving
Mode
Refresh
Type
SUSPEND
Signal
Doze
Normal
Nap
Sleep
Suspend
Power Management Control Register (PMCR)
[LP_REF_EN)
MCCR1
[SREN)
[PM)
[DOZE)
[NAP)
[SLEEP)
Negated
(High)
1
1
0
0
-
-
Normal
Negated
(High)
1
-
1
0
-
-
Self
Negated
(High)
1
-
-
1
1
1
Normal
Negated
(High)
1
-
-
1
1
0
None
Negated
(High)
1
-
-
1
0
-
Self
Asserted
(Low)
1
-
-
0
1
1
RTC
Asserted
(Low)
1
-
-
0
1
0
None
Asserted
(Low)
1
-
-
0
0
-
Note: Normal refresh is not available in suspend mode.
Note that in the absence of refresh support, system software must preserve DRAMIEDO
data (such as by copying the data to disk) before entering the power saving state.
6.3.10.2.1 Self-Refresh in Sleep and Suspend Modes
The setup timing for self-refreshing DRAMIEDOs is shown in Figure 6-15; see Table 6-5
for acronyms used in Figure 6-15.
MOTOROLA
Chapter 6. Memory Interface
6-27
1
m[O, 7]
RAS"[I,6)
1
1
\:
I:
I:
1
I
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1
~'I
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CSR~I
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1
1
1
1
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1
1
1
1
RAS"[2,5)
.'
nsL.rl.JL
60x Bus Clock
I
: HI-Z :
X
//
RASS = Self-refresh interval (must be greater than
oo~)
Figure 6-15. DRAMIEDO Self-Refresh Timing in Sleep and Suspend Modes
6.3.10.2.2 RTC Refresh in Suspend Mode
If the MPC 106 is configured to provide refresh cycles based on the RTC signal in suspend
mode, RAS and CAS are driven as shown in Figure 6-16. The DRAMlEDOs used in this
mode of operation must have a distributed refresh interval no less than 4 times the period
of the RTC input signal. For example, if the frequency of RTC is 32.768 KHz, the
DRAMlEDOs must have a low-power refresh interval greater than 122 Ils to allow use of
the RTC refresh feature.
RTC~
m
I
1'""\'
/1
I
RAS"[O, 2, 4, 6 ) :
I
RAS"[I,3,5,7]
I:
I
I
1'""\'
~I
'-LI
I
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I
LIn--:- - i - - - i - I
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Figure 6-16. Suspend Mode-Real Time Clock Refresh
6.3.11 Processor-to-System-Memory Transaction Examples
The figures in this section provide examples of signal timing for 60x processor-to
system-memory transactions. Figure 6-17 shows a series of processor burst reads from
system memory. Figure 6-18 shows a processor burst write to system memory.
6-28
MPC106 PCIS/MC User's Manual
MOTOROLA
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6.4 SCRAM Interface Operation
The MPCI06 provides the necessary control functions and signals for JEDEC-compliant
SDRAM devices. The MPC106 provides 1 Gbyte of addressable memory.
The eleven row/column multiplexed address signals (SDMA[I-II]) and one internal bank
select (SDBAO) provide for SDRAM densities from 1M to 16M in depth. Eight SDRAM
command select (CS) signals support up to eight banks of memory. Eight SDRAM data
qualifier (DQM) signals are used to provide byte selection for 64-bit accesses.
In addition to DQM[0-7], CS[0-7], SDBAO, and SDMA[I-11], there are 64 data signals
(DH[0-31] and DL[0-31]), a write enable (WE) signal, a column address strobe (SDCAS)
signal, a row address strobe (SDRAS), a memory clock enable (CKE) signal, and eight
parity bits (PAR[0-7]).
Note that when configured for SDRAM, the following MPC106 features are not supported:
•
•
•
ECC
Asynchronous L2 cache
Partial L2 update with external byte write decode (that is, CF_ WMODE must be
cleared to ObOO)
•
Modified memory tracking in PC emulation mode (SDRAS is multiplexed with
PIRQ)
•
Latched data buffers (SDCAS is multiplexed with MDLE)
•
Local bus slave (CKE is multiplexed with DBGLB)
Figure 6-22 shows an example of an eight-bank, 128-Mbyte system, comprised of
2M bit x 9 SDRAMs. Note that the SDRAM memory clock must operate at the same
frequency as, and phase aligned with, the 60x processor bus clock.
MOTOROLA
Chapter 6. Memory Interface
6-39
OHG-DH31
OL<>-Dl31
Oa1a path 1o/Irom BOx
~
@_IVOr
BClI3
Da1a path from boot memory
Write parity from BOx
@
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8
MPC106
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Add..... palh 10 boot memory
Bullers
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bus.-
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g g
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A(II-o]
OQM
A(IHI]
DQ{B-O]
I
DA:rA[G-7] + PARO
DQ{B-O]
DATAlS6-63] +
PARj
Figure 6-22. 128-Mbyte SDRAM System with Parity
6-40
MPC106 PCIBIMC User's Manual
MOTOROLA
6.4.1 Supported SDRAM Organizations
It is not necessary to use identical memory devices in each memory bank; individual
memory banks may be of differing size. Although the MPC 106 multiplexes the row and
column address bits onto 12 memory address signals, individual SDRAM banks may be
implemented with memory devices requiring fewer than 24 address bits. Note that the
MPCI06 only supports devices that conform to the 16M JEDEC standard. It does not
support the 4M JEDEC standard.
Table 6-10 summarizes some of the memory configurations supported by the MPCI06.
Table 6-10. Memory Device Configurations Supported
Number of
Devices Ina
Bank
Device
Configuration
Row Bits x
Column Bits
Bank Size
Maximum
Memory (Using
All 8 Banks)
16
4Mx4
12x 12
32Mbytes
256Mbytes
8
2Mx8,9
12x 12
16Mbytes
128 Mbytes
4
1M x 16, 18
12x 12
8Mbytes
64 Mbytes
By using a memory polling algorithm at power-on reset, system firmware configures the
MPC 106 to correctly map the size of each bank in memory (the memory boundary
registers). The MPCI06 uses its bank map to assert the appropriate CSn signal for memory
accesses according to the provided bank depths.
6.4.2 SDRAM Address Multiplexing
System software must configure the MPCI06 at power-on reset to appropriately multiplex
the row and column address bits for each bank. All 16M SDRAM devices use 12 row bits,
so the appropriate row bit parameters in MCCRI should be set to ObIt. Address
multiplexing will then occur according to the configura~on settings, as shown in
Figure 6-5.
Figure 6-23. SDRAM Address Multiplexing
During the row address phase, SDBAO contains A9 and SDMA[1-11] contain A[10-20].
During the column address phase, SDBAO contains AS, SDMA[1-3] contain A[t)..;.8] , and
SDMA[4-11] contain A[21-28].
MOTOROLA
Chapter 6. Memory Interface
6-41
6.4.3 SDRAM Burst and Single-Beat Transactions
The MPC106 runs a burst-of-four for every transaction (burst and single-beat). For
single-beat read transactions, the MPC 106 masks the extraneous data in the burst by driving
the DQMn signal high on the irrelevant cycles of the burst. For single-beat write
transactions, the MPC 106 protects nontargeted addresses by driving the DQMn signal high
on the irrelevant cycles of the burst.
For. single-beat transactions, the bursts cannot be terminated early. That is, if the relevant
data is in the first data phase, the subsequent data phases of the burst must run to completion
even though the data is irrelevant.
The MPC106 supports burst-of-four, double-word data beats for accesses to system
memory. The burst is always sequential, and the critical double word is always supplied
first. For example, if the 60x requests the third double word of a cache line, the MPC 106
reads double words from memory in the order 2-3-0-1.
6.4.4 SDRAM Page Mode Retention
Under certain conditions, the MPC I 06 retains two active SDRAM pages for burst or single
beat accesses. These conditions are:
•
A pending transaction (read or write) hits one ofthe currently active internal pages.
•
There are no pending refreshes.
•
The burst to precharge interval (controlled by BSTOPRE_U and BSTOPRE_L) has
not been exceeded.
•
The maximum activate to precharge interval (controlled by PGMAX) has not been
exceeded.
Page mode can dramatically reduce access latencies for page hits. Depending on the
memory system design and timing parameters, using page mode can save clock cycles from
subsequent burst accesses that hit in an active page. SDRAM page mode is controlled by
the BSTOPRE_U, BSTOPRE_L, and PGMAX parameters. Page mode is disabled by
clearing either BSTOPRE_U and BSTOPRE_L, or the PGMAX parameter.
The page open duration counter is loaded with BSTOPRE_U II BSTOPRE_L every time
the page is accessed (including page hits). When the counter expires (or when PGMAX
expires) the open page is closed with a precharge bank command. Page hits can occur at
any time in the interval specified by BSTOPRE.
The PGMAX parameter specifies the activate to precharge interval (sometimes called row
active time or tRAS)' When the interval specified by PGMAX expires, the MPC106 must
close the active page by issuing a precharge bank command. The value in PGMAX is
multiplied by 64 to generate the actual number of clock cycles for the interval.
The value for PGMAX depends on the specific SDRAM devices used, the ROM system,
and the operating frequency of the MPCI06. If a ROM access is in progress at the time
6-42
MPC106 PCIB/MC User's Manual
MOTOROLA
PGMAX expires, the MPCI06 must wait for the ROM access to complete before issuing
the precharge command to the SDRAM. In the worst case, the MPCI06 initiates a ROM
access one clock cycle before PGMAX expires. Therefore, the activate to precharge interval
must be sufficiently less than the maximum row active time for the SDRAM device to
insure that the issuing of a precharge command is not stalled by a ROM access.
The maximum value stored to PGMAX should be the maximum row active time for the
SDRAM device (tRAS(MAX») reduced by the number of clock cycles required by the longest
ROM access time (controlled by the ROMFAL and ROMNAL parameters), as shown in
Figure 6-24.
~AX)
lor SDRAM device
PGMAX (in number of clock cyIlles) x 64
"
I
Worst case ROM access time
Figure 6-24. PGMAX Parameter Setting for SDRAM Interface
For example, consider a system with a 60x bus clock frequency of 66 MHz using SDRAMs
with a maximum row active time (tRAS(MAX») of 200 ~s. The maximum number of clock
cycles between activate bank and precharge bank commands is 66 MHz x 200 ~s = 13200
clock cycles. If the system uses 8-bit ROMs, the MPC 106 byte gathers the ROM accesses
into 64-bit double words, requiring 8 ROM accesses for a 60x read from ROM. If ROMFAL
is programmed to all ones, each ROM access will take 33 clock cycles. Therefore, the worst
case interval for a 60x read from ROM would be 33 clock cycles x 8 accesses 264 clock
cycles. The value stored in PGMAX would be (13200 - 264) + 64 = 202 (orObll00_1010).
=
6.4.5 SDRAM Power-On Initialization
At system reset, initialization software must set up the programmable parameters in the
memory interface configuration registers (MICRs). These include the memory boundary
registers, the memory banks enable register, the memory page mode register, and the
memory control configuration registers (MCCRs). See Section 3.2.6, "Memory Interface
Configuration Registers," for more detailed descriptions of the MICRs and MCCRs.
NOTE
The MPCI06 can only support certain configurations of
parityIRMWIECC, DRAMIEDOISDRAM, and buffer types.
Section 6.3.3.1, "Supported Memory Interface Configurations
describes the supported memory interface configurations.
The programmable parameters relevant to the SDRAM interface are:
•
•
•
Memory bank starting and ending addresses (memory boundary registers)
Memory bank enables (memory bank enable register)
PGMAX-maximum activate to precharge interval (also called row active time
ortRAS)
MOTOROLA
Chapter 6. Memory Interface
6-43
• SREN-self-refresh enable
• RAMTYP-RAM type
• PCKEN-memory interface parity checking/generation enable
• Row address bit count for each bank
• BUF_MODE-buffer mode
• RMW_PAR-read-modify-write parity enable
• BSTOPRE_U-burst to precharge interval-upper nibble
• BSTOPRE_L--burst to precharge interval-lower nibble"
• REFREC-refresh recovery interval
• RDLAT-data latency from read command
• PRETOACT-precharge-to-activate interval
• ACTOPRE-activate-to-precharge interval
• WCBUF-memory write buffer type
• RCBUF-memory read buffer type
·SDMODE-SDRAM mode register
• ACTORW-activate-to-readlwrite interval
Once all the memory parameters are configured, then system software should set the
MEMGO bit (MCCRl, bit 19) to enable the memory interface. (Note that 100 Ils must
elapse after the negation of HRST before the MEMGO bit can be set, so a delay loop in the
initialization code may be necessary.)
The MPCI06 then proceeds with the following initialization sequence:
1. Issues a precharge-all-banks command
2. Issues eight refresh commands
3. Issues a mode-set command to initialize the mode register
See Section 6.4.6, "JEDEC Standard SDRAM Interface Commands," for detailed
information about the SDRAM commands in the above sequence. When the sequence
completes, the SDRAM array is ready for access.
6.4.6 JEDEC Standard SDRAM Interface Commands
The MPC106 performs all accesses to SDRAM by using JEDEC standard SDRAM
interface commands. The SDRAM device samples the command and data inputs on the
rising edge of the 60x bus clock. Data at the output of the SDRAM device must be sampled
on the rising edge of the 60x bus clock.
The MPC106 provides the following SDRAM interface commands:
•
6-44
Activate-bank-Latches the row address and initiates a memory read of that row.
Row data is latched in SDRAM sense amplifiers and must be restored by issuing a
precharge command before another bank-activate is issued.
MPC106 PCIB/MC User's Manual
MOTOROLA
•
Precharge-bank-Restores data from the sense amplifiers to the appropriate row.
Also initializes the sense amplifiers in preparation for reading another row in the
SDRAM internal bank. A precharge command must be issued after a read or write,
if the row address changes on the next access. Note that the MPC106 uses SDMA1
to distinguish between the precharge-bank and precharge-all-banks commands. The
SDRAMs must be compatible with this format.
•
Precharge-all-banks-Initializes the sense amplifiers of all SDRAM internal banks.
Note that the MPC106 uses SDMA1 to distinguish between the precharge-all-banks
and precharge-bank commands. The SDRAMs must be compatible with this format.
•
Read-Latches the column address and transfers data from the selected sense
amplifier to the output buffer as determined by the column address. During each
succeeding clock, additional data is output without additional read commands. The
amount of data transferred is determined by the burst size.
•
Write-Latches the column address and transfers data from the data signals to the
selected sense amplifier as determined by the column address. During each
succeeding clock, additional data is transferred to the sense amplifiers from the data
signals without additional write commands. The amount of data transferred is
determined by the burst size.
•
Refresh-Causes a row to be read in both memory banks (JEDEC SDRAM) as
determined by the refresh row address counter (similar to CBR). The refresh row
address counter is internal to the SDRAM device. After being read, a row is
automatically rewritten into the memory array. Before execution of refresh, both
memory banks must be in a precharged state.
•
Mode-set-Allows setting of SDRAM options. The options are CAS latency, burst
type, and burst length.
CAS latency depends upon the SDRAM device used (some SDRAMs provide CAS
latency of 1, 2, or 3, some provide CAS latency of 1, 2, 3, or 4, etc.).
Burst type must be chosen according to the 60x cache wrap (sequential).
Although some SDRAMs provide burst lengths of 1, 2,4,8, or a page, the MPC106
only supports a burst of four. Burst lengths of 1, 2, 8, and a page for SDRAMs are
not supported by the MPC106.
The mode register data (CAS latency, burst length, and burst type) is programmed
into MCCR4[SDMODE] by initialization software at reset. After
MCCR1[MEMGO] is set, the MPC106 then transfers the information in
MCCR4[SDMODE] to the SDRAM array by issuing the mode-set command. See
Section 6.4.7.1, "SDRAM Mode-Set Command Timing," for timing information.
•
Self-refresh-Used when the SDRAM device is in standby for very long periods of
time (corresponding with sleep or suspend mode on the MPC106). Internal refresh
cycles are automatically generated by the SDRAM to keep the data in both memory
banks refreshed. Before execution of this command, both memory banks must be in
a precharged state.
MOTOROLA
Chapter 6. Memory Interface
6-45
The MPCI06 automatically issues a precharge command to the SDRAM when the
BSTOPRE or PGMAX intervals have expired, regardless of pending memory transactions
from the PC! bus or 6Ox. The MPC 106 can perform precharge cycles concurrent with snoop
broadcasts for PC! transactions.
The SDRAM interface command encodings are summarized in Table 6-11.
Table 6-11. SDRAM Command Encodings
Command
Refresh
(CBR)
Mode
Set
Activate
Bank
Precharge
All Banks"
Precharge
Bank
Previous CKE
High
High
High
High
High
High
High
High
CurrentCKE
x
x
x
x
x
High
x
Low
~
Low
Low
Low
Low
Low
Low
Low
Low
SDRAS
Low
Low
Low
High
High
Low
Low
Low
'SI5CAS
High
High
High
Low
Low
Low
Low
Low
WE
High
Low
Low
High
Low
High
Low
High
DQMn
x
x
x
I,.ow
Low
x
x
x
SDBAO
Bank
select
x
Bank
select
Bank
select
Bank
select
x
Opcode
x
SDMA1
Row
High
Low
Low
Low
x
Opcode
x
SDMA[2-11)
Row
x
x
Column
Column
x
Opcode
and
mode
x
Write
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• Note that the MPC106 only issues the precharge all banks command at initialization when the MCCR1 [MEMGO)
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6.4.7 SCRAM Interface Timing
System software is responsible for optimal configuration of the SDRAM programmable
timing parameters (RDLAT, BSTOPRE, PRETOACT, ACTOPRE, andACTORW) at reset.
The actual values used by initialization software depend upon the specific SDRAM devices
used in the system design.
Note that data latency is programmable for read operations (RDLAT). For write operations,
the first beat of write data is supplied concurrent with the write command.
The following figures illustrate SDRAM timing for various types of accesses; Figure 6-25
shows several burst read operations, Figure 6-26 shows a burst write operation, Figure 6-27
shows burst read followed by burst write operations, Figure 6-28 shows a single-beat read
operation, and Figure 6-29 shows a single-beat write operation.
6-46
MPC106 PCIBIMC User's Manual
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6-48
MPC106 PCIBIMC User's Manual
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6·50
MPC106 PCIBIMC User's Manual
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I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
M
I
I
~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
3
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
:
I
:
I
I
I
I
I
I
I
I
I
I
~
~
I
I
I
I
:::
I
M
00
BCTL[0-1]
I
I
I
I
I
I
M'
I::
I I I
DQM[O-7]
I
I
~:::::::M
WE"::
I
I
I
I
I
I
3
I
I
I
Data Bus L~...J.......L-.L-J......J~'--l{~O)-...L~......L.~- - ' - - - ' - - ' - - ' - " - '
Figure 6-29. SDRAM Single-Beat Write Timing
6.4.7.1 SCRAM Mode-Set Command Timing
The MPC106 transfers the mode register data, (CAS latency, burst length, and burst type)
stored in MCCR4[SDMODE] to the SDRAM array by issuing the mode-set command. The
timing of the mode-set command is shown in Figure 6-30.
MOTOROLA
Chapter 6. Memory Interface
6-51
SOx bus clock
CKE
,'\---1--
RASfCSn
~--:---;------;"-~,
SDCAS/ELE
'
---'---; ,...---'---'--"'-----'--.....:"
MAo-MA11
MCCR4[SDMODE] Data
,
XRow
1'--'1-1
,
,, ,'L
, ,
CAS/DQMn
Data
(three-stated)
,..
,
1
1
.. I
Mode-set to any command
I
(for example, refresh or bank-activate)
fixed at five clock cycles
Figure 6-30. SDRAM Mode-Set Command Timing
6.4.8 SCRAM Parity and RMW Parity
When configured for SDRAM, the MPCI06 supports two forms of parity cheCking and
generation-normal parity and read-modify-write (RMW) parity. Normal parity assumes
that each of the eight parity bits is controlled by a separate DQM signal. Thus, for a
single-beat write to system memory, the MPC 106 generates a parity bit for each byte
written to-memory.
RMW parity assumes that all eight parity bits are controlled by a single DQM signal and
therefore must be written as a single 8-bit quantity (that is, a byte). Therefore, for any write
operation to system memory that is less than a double word, the MPC106 must latch the
write data, read an entire 64-bit double word from memory, check the parity of the double
word read from memory, merge the write data with the double word read from memory,
regenerate parity for the new double word, and finally write the new double word back to
memory.
The MPCI06 checks parity on all memory reads, provided parity checking is enabled
(PCKEN = 1). The MPC106 generates parity for the following operations:
•
•
•
•
PCI to memory write operations
L1 and L2 copy-back operations
L2 cast-out operations
60x single-beat write operations with RMW parity enabled (RMW_PAR = 1)
The 60x processor is expected to generate parity for all other 60x to memory write
operations as the data goes directly to memory and does not pass through the MPC 106.
6-52
MPC106 PCIBIMC User's Manual
MOTOROLA
6.4.8.1 RMW Parity Latency Considerations
When RMW parity is enabled, the time required to read, modify, and write increases
latency for processor single-beat writes to system memory and PCI writes to system
memory. All other transactions are unaffected and operate as in normal parity mode.
For 60x processor single-beat writes to system memory, the MPC106 latches the data,
performs a double-word read from system memory (checking parity), and then merges the
write data from the processor with the data read from memory. The MPC 106 then generates
new parity bits for the merged double word and writes the data and parity to memory. The
read-modify-write process adds six clock cycles to a single-beat write operation. If page
mode retention is enabled (BSTOPRE *- 0 and PGMAX *- 0), then the MPC106 will keep
the memory in page mode for the read-modify-write sequence. Since the processor drives
all eight parity bits during 60x burst writes to system memory, these transactions go directly
to the SDRAMs with no performance penalty.
For PCI writes to system memory with RMW parity enabled, the MPC106 latches the data
in the internal PCI-to-system-memory-write buffer (PCMWB). If the PCI master writes
complete double words to system memory, the MPC106 generates the parity bits when the
PCMWB is flushed to memory. However, if the PCI master writes 32-, 16-, or 8-bit data
that cannot be gathered into a complete double word in the PCMWB, a read-modify-write
operation is required. The MPC 106 performs a double-word read from system memory
(checking parity), and then merges the write data from the PCI master with the data read
from memory. The MPCI06 then generates new parity for the merged double word and
writes the data and parity to memory. If page mode retention is enabled (BSTOPRE *- 0 and
PGMAX *- 0), the MPCI06 keeps the memory in page mode for the read-modify-write
sequence.
6.4.9 SDRAM Refresh
The memory interface supplies CBR refreshes to SDRAM according to the interval
specified in MCCR2[REFINT]. The value stored in REFINT represents the number of 60x
bus clock cycles required between CBR refreshes. The value for REFINT depends on the
specific SDRAM devices used and the operating frequency of the MPC106. This value
should allow for a potential collision between memory accesses and refresh cycles. The
period of the refresh interval must be greater than the access time to insure that read and
write operations complete successfully.
If a burst read is in progress at the time a refresh operation is to be performed, the refresh
waits for the read to complete. In the worst case, the refresh must wait the number of clock
cycles required by the longest access time. The value stored to REFINT should be the
number of clock cycles per row refresh reduced by the number of clock cycles required by
the longest access time (to allow for potential collisions).
For example, given an SDRAM with 4096 rows and a cell refresh time of 64 ms, the per
row refresh interval would be 64 ms + 4096 rows = 15.6I1s. If the 60x bus clock is running
at 66 MHz, the number of clock cycles per row refresh is 15.611s x 66 MHz = 1030 clock
MOTOROLA
Chapter 6. Memory Interface
6-53
cycles. If the number of clock cycles for the longest access time is 24 clocks, value stored
in REFINT would be ObOO_00ll_ll1O_111O (in decimal, 1030 - 24 = 1006).
6.4.9.1 SDRAM Refresh Timing
The CBR refresh timing for SDRAM is controlled by the programmable timing parameter
MCCR3[REFREC]. REFREC represents the number of clock cycles from the refresh
command until a bank-activate command is allowed. TheAC specifications of the specific
SDRAM device will provide a minimum refresh to activate interval.
The MPCI06 implements bank staggering for CBR refreshes, as shown in Figure 6-31.
This reduces instantaneous current consumption for memory refresh operations.
60x Bus Clock
CKE
C'S(O,1)
I
D
I
I
I
I
~_-I----+----II:'
:i=
,I I,
I
:;:::; --I---+-P---iU---r-1 -...,.I-.,.....---r-----r--r---r----r----.t
C'S(6,7)
I
~
1'--t-+--+:--i~r--+--+-~I---4--+-+--IW
~~
I
V
SDRAS
I
I
SDBAO,
SDMA[1-11)
I REFREC I
I"
Row Address
I
X
WE-01---.--r--'--·I--'I---Ir--.--.--.--,---T1
I
:
I~
I ACTORW I
-I"
-I
Column Address
I
I
I
I
I
I
I
I
I
DaMn J""---'-~---''--~I-~I--:-1--:----'---:---'--...:.1-"""1\
II
I
I
Figure 6-31. SDRAM Bank-Staggered CBR Refresh Timing
6.4.9.2 SDRAM Refresh and Power Saving Modes
The MPC 106 memory interface provides for doze, nap, sleep, and suspend power saving
modes defined in Appendix A, "Power Management."
In doze and nap power saving modes and in full-on mode, the MPC106 supplies the normal
CBR refresh to SDRAM. In sleep mode, the MPCI06 can be configured to take advantage
of self-refreshing SDRAMs or provide normal refresh to the SDRAMs. In suspend mode,
the MPCI06 can be configured to take advantage of self-refreshing SDRAMs. Normal and
real-time clock (RTC) refresh are not available for SDRAM in suspend mode-all
JEDEC-compliant SDRAMs allow self-refresh which consumes less power than normal or
RTC refresh. Table 6-12 summarizes the refresh types available in each of the power saving
modes and the relevant configuration parameters.
6·54
MPC106 PCIBIMC User's Manual
MOTOROLA
Table 6-12. SDRAM Power Saving Modes Refresh Configuration
Power
Saving
Mode
Refresh
Type
SUSPEND
Signal
Doze
Normal
Nap
Sleep
Suspend 1
Power Management Control Register (PMCR)
MCCR1
[SREN]
[PM]
[DOZE]
[NAP]
[SLEEP]
[LP_REF_EN]
Negated
(High)
1
1
0
0
-
-
Normal
Negated
(High)
1
-
1
0
-
-
Self
Negated
(High)
1
-
-
1
1
1
Normal
Negated
(High)
1
-
-
1
1
0
Self
Asserted
(Low)
1
-
-
0
1
1
Note: Normal and RTC refresh are not available in suspend mode.
The entry timing for self-refreshing SDRAMs is shown in Figure 6-32. The exit timing for
self-refreshing SDRAMs is shown in Figure 6-33.
60x Bus Clock ~
CKEUI
.
I
I
I
DQMn
Data
(three-stated)
Figure 6-32. SDRAM Self-Refresh Entry Timing
MOTOROLA
Chapter 6. Memory Interface
6-55
6OxBusCI~~
CKE
-1
'C'Sii
1\
'SDRAS
:
S'DCAS
I ~
I
I
SDBAO,
SDMA[1-11J
WE
DQMn
Data
(three-stated)
:
I
xxx
I
I
+-r
I
.--
LILfUL.J
~
Ay
~
I
I
I
I
I
1/
:~
I'---.J.J
•
~
SDMA1=1
~
~
•
12 Cycles
~
I
I
I
.
Figure 6-33. SDRAM Self-Refresh Exit Timing
6.5 ROM/Flash Interface Operation
For the ROM/Flash interface, the MPC106 provides 21 address bits, two bank selects, one
Flash output enable, and one Flash write enable. Figure 6-34 shows an example of a
16-Mbyte ROM system.
6-56
MPC106 PCIBIMC User's Manual
MOTOROLA
OH[(}...31],
0L[(}...31]
Data path kYfrom 60x
I!eT[lf
lIC'f[f
.1
£::,.\l ITransceiver
MPC106
Data path ta/from ORAMIEDO array
Write parity from 60x
I
~ Transceiver
J5I5Eff
Parity path to/Irom ORAMIEDOarray
Address path to/Irom ORAMIEDO array
AR[&-20]
r- ~
Buffers
AR[1-8]
f-l-{)
Buffers
I
I
L
L
A(G-18], A·1
A(G-18], A-1
1Mx8
ROM
r--
eE"
[~
BHE
"FiCSO
~
K
K
--
0[8-15] r--NC
0[G-7]
0[G-7]
Buffers
GNO
1Mx8
ROM
·'E··x!!..••
(Bank 0 select\
r--
CE"
[~
BHE
0[8-15] f-NC
0[G-7]
r--
0[55-«3]
GNO
D[()-63
Bank 1 select
Buffers
GNO
t
L......-
D[G-7]
r--
0[G-7]
0[8-15] r--NC
;E
eE"
r
·'E··x!!..••
A(G-18], A·1
r--
D[G-7]
0[8-15] r--NC
t;E
L..--
1Mx8
ROM
D{55-«3]
GNO
CE"
r
1Mx8
ROM
A(G-18], A-1
Figure 6-34. 16-Mbyte ROM System
Figure 6-35 shows an example of a I-Mbyte Flash system. Note that because of the 8-bit
data path, external decode logic is necessary to select between the two devices.
MOTOROLA
Chapter 6. Memory Interface
6-57
DH[0-3ll.
Dl.[0-3l1
Data path toIIrom 60x
BCTLO
~\1
BCTLl
MPC106
Transceiver
Data path toIIrom DRAM/EOO array
Write parity from 60x
I
J ~\11 Transceiver
J5PEff
AR{9-201
r- -{::;Buflers
AR[l-8)
_ --I> BufferS
Parity path toIIrom DRAMIEDO array
Address path to DRAMIEDO array
I
Programming voltaga
power supply
I
Sys1em Flash
write detect
andVpp mux
conIroi
ARl
~
J:f
Bank
decode
h
I
----+
A[0-18]
i
Bank A
f - - - J5WIr
f - - - Vpp
-
mE"
WE
BankB
r-~
5l2Kx8
FlASH
e'E"
WE"
~
0[0-7]
~
0[0-7]
WE"
e'E"
Vpp
J5WIr
5l2KxS
FlASH
A[0-1S1
Figure 6-35. 1-Mbyte Flash System
The MPCI06 supports an 8- or 64-bit data path to bank O. A configuration signal (FOE)
sampled at reset, determines the bus width of the ROM or Flash device (8-bit or 64-bit) in
.
bank O. The data bus width for ROM bank 1 is always 64 bits.
The most-significant ROMlFlash address bit (ARO) is only supported for bank 0 when
using the 8-bit data path. The extra address bit allows for up to 2 Mbytes of ROMlFlash
space in bank 0 for the 8-bit data path configuration. For the 64-bit data path, 20 address
bits (AR[ 1-20]) allows for up to 8 Mbytes per bank.
For systems using the 8-bit interface to bank 0, the ROM/Flash device must be connected
to the most-significant byte lane of the data bus (DH[o-7]). The MPC106 performs byte
lane alignment for single-byte reads from ROMIFlash memory. The MPCI06 can also
perform byte gathering (up to eight bytes) for ROMlFlash read operations. The data bytes
are gathered and aligned within the MPC 106, then forwarded to the 60x processor.
6-58
MPC106 PCIBIMC User's Manual
MOTOROLA
°
The 16-Mbyte ROMIFlash space is subdivided into two 8-Mbyte banks. Bank (selected
by RCSO) is addressed from OxFF80_0000 to OxFFFF_FFFF. Bank 1 (selected by RCS 1)
is addressed from OxFFOO_OOOO to OxFF7F_FFFF. Implementations that require less than
16 Mbytes may allocate the required ROMIFlash to one or both banks.
For example, an implementation that requires only 4 Mbytes of ROM/Flash could locate
at addresses OxFFCO_OOOO-OxFFFF_FFFF.
the ROMIFlash entirely within bank
Alternately, the ROM/Flash could be split across both banks with 2 Mbytes in bank at
OxFFEO_OOOO-OxFFFF_FFFF, and 2 Mbytes in bank 1 at OxFF60_0000-0xFF7F_FFFF.
Any system ROM space that is not physically implemented within a bank will be aliased to
the physical device(s) within that bank.
°
°
The MPC 106 can be configured to support ROM/Flash devices located on the 6Oxlmemory
bus or on the PCI bus. The RCSO signal is sampled at reset to determine the location of
ROM/Flash. See Section 2.2.8, "Configuration Signals," for more information. If the
system ROM space is mapped to the PCI bus, the MPC106 directs all system ROM accesses
to the PCI bus.
The MPC106 also supports splitting the system ROM space between PCI and the
60xlmemory bus. The entire ROM space is mapped to the PCI space, and then, by setting
the configuration parameter PICR2[CF_FFO_LOCAL], the lower half of the ROM space
(FFOO_OOOO-FF7F_FFFF) is remapped onto the 60xlmemory bus. This allows the system
to have the upper half of ROM space on the PCI bus for boot firmware and the lower half
of the ROM space on the 60xlmemory bus for performance critical firmware. The
ROMIFlash on the 60xlmemory bus is selected by RCS 1 and the data path must be 64 bits
wide.
6.5.1 ROM/Flash Cacheability
Data in ROM/Flash memory is cacheable with certain restrictions-the L2 cache must use
synchronous burst SRAMs, and the ROM data in the cache must not be modified. Flash data
in the L2 cache can be modified, but the L2 cache must operate in write-through mode.
The MPC106 does not generate parity for transactions in the system ROM space, so
incorrect parity is stored with ROMIFlash data in the L2 cache. However, this does not
cause a parity error because the MPC 106 does not check paritylECC for any transaction in
the system ROM address space.
6.5.2 64-Bit ROM/Flash Interface Timing
The ROMlFlash interface of the MPC106 supports burst and nonburst devices. The
MPC 106 provides programmable access timing for the ROMIFlash interface. The
programmable timing parameters for the ROM/Flash interface are MCCR1[ROMNAL],
MCCR1[ROMFAL], and MCCR1[BURST]. See Section 3.2.6.4, "Memory Control
Configuration Registers," for more information.
MOTOROLA
Chapter 6. Memory Interface
6-59
When configured for a 64-bit data path, MCCRl[ROMFAL] controls the latency for
nonburst devices. For burst devices, ROMFAL controls the latency for the first data beat
only. The actual latency cycle count for the 64-bit interface is three clock cycles more than
the value specified in ROMFAL. For example, when ROMFAL = ObO_OOOO, the latency is
three clock cycles; when ROMFAL ObO_ODOI, the latency is four clock cycles; when
ROMFAL = ObO_OOlO, the latency is five clock cycles; and so on.
=
MCCRI [ROMNAL] controls the latency for burst devices for the burst data beats following
the first data beat. The actual latency cycle count is two cycles more than the value specified·
in ROMNAL. For example, when ROMNAL = ObOOOO, the latency is two clock cycles;
when ROMNAL = ObOOOI, the latency is three clock cycles; when ROMNAL = ObOOIO,
the latency is four clock cycles; and so on. MCCRI [BURST] controls whether the MPC 106
uses burst (BURST I) or nonburst (BURST 0) access timing.
=
=
ROMFAL and ROMNAL are set to their maximum value at reset in order to accommodate
initial boot code fetches. BURST is cleared at reset to indicate nonburst device timing.
Figure 6-36 and Figure 6-37 illustrate the 64-bit ROMlFlash interface timing for nonburst
and burst device configurations.
AR[l-18[ )(\--_ _-
_ _-
I
_ _-
_ _ _-
I
_ _ _-_~-_ __
_ _I
I
I
~n \'l-II_\__~~-~_+I-~~~\__~~-.I-+_~-I\__~~-~I-+__
,
I
I
I
I
I
I
I
I
I
60x Data ....:.---,:.--=---.:...~'--,Xi---,:.-....:........,D,..."AT::-:-A.,....O....:.---,:.---.Xi---,:.-"'"'----::D-::AT~A1~'--...:......-,~
Data sampled
f
~
f
Notes:
ROMFAL (ROM first access latency) =0-15 clock cycles
MCCR1 [BURST] 0 (default value at reset)
=
Figure 6-36. 64-Bit ROMIFlash Interface-Non burst Read Timing
6-60
MPC106 PCIBIMC
user's Manual
MOTOROLA
SOx Bus Clock
AR[19-20)
:
AR[HB)
.'
y_--:-__--:-----:-~x
:
ROMFAL :...:.r-:------J~ 1
X
ROMNAL~'
.
1
1
X
ROMNAL~'
.
1
1
X
ROMNAL~'
.
1
1
y.,-----'--'-----'--'-----'--'----'--------'
1
ROMFAL :..
1
X
•
1
~n ~~'~-4_-4-+-~-~~_4--+__+--~~~~~_4--+_~--~
1
X
60x Data
Data sampled
DATAO
f
X
DATA1
f
X
DATA2
f
X
1
DATA3
f
Ct
Notes:
ROMFAL (ROM first access latency) = 0-15 clock cycles
ROMNAL (ROM next access latency) = 0-9 clock cycles
Figure 6-37. 64-Bit ROM/Flash Interface-Burst Read Timing
6.5.3 8-Bit ROM/Flash Interface Timing
The MPC 106 provides programmable latency for accessing ROMIFlash memory so that
systems of various clock frequencies may properly interface to the ROMIFlash devices. The
programmable timing parameter MCCRl[ROMFAL] controls the access latency to
ROMIFlash memory. The actual latency cycle count is two cycles more than the value
specified in ROMFAL. For example, when ROMFAL = ObOOOO, the latency is two clock
cycles; when ROMFAL = ObDOOl, the latency is three clock cycles; when ROMFAL =
ObOOlO, the latency is four clock cycles; and so on. ROMFAL is set to its maximum value
at reset in order to accommodate initial boot code fetches from a slow device. To improve
access latency, it is recommended that initialization software program a more appropriate
value for the actual device being used. The 8-bit interface only provides nonburst access
timing, so the parameter MCCRl[BURST] is ignored for the 8-bit interface.
The following figures illustrate the 8-bit ROM/Flash interface timing for various read
accesses. Figure 6-38 shows a single-byte read access. Figure 6-39 shows a half-word read
access. Word and double-word accesses require using the burst access timing shown in
Figure 6-40.
MOTOROLA
Chapter 6. Memory Interface
6-61
60x Bus Clock
1
~
/:'
\:
\:I
1
mE'
AR[G-20]
60x Data
I~
1
1
1
\:I
/:
;
X;
:
X DA~AO
:
)o~ROMFAL
101(
2 cycles ,
(constant)
Data sampled
1
1
/:
1
;
: X;
:
1
1
X
5cycies
(constant)
)0,01(
t
1
X
)0,01(
-+1111(
, 2cyc1es
,
DATAl:
X
ROMFAL~
t
(constanQ
Figure 6-38. 8-Bit ROM/Flash Interface-Slngle-Byte Read Timing
60x Bus Clock
~
1
mE'
AR[o-20]
1
/:
\:
1
X;
;
;
X;
1
60x Data
:
101(
)0
X
:i"C-' ROMFAL
:
DATA
:
X
DAtA
X
)o~ROMFAL~
)0,01(
t
, 2cycles '
(constant)
:
, 2 cycles '
(constant)
t
Data sampled
Figure 6-39. 8-Bit ROM/Flash Interface-Half-Word Read Timing
60x Bus Clock
1
\::
~,
~:
AR[G-20]
60x Data
1
1
~:
101(
)0101(
, (2 + ROMFAL)'
x8 cycles
I
\::
C~r-i-i-....L......J
1
: Ii
:X~;~::~'~;~~~~:
I~:--r--'-",",\:
~':;
1
~ ':
'i-,-....L......I~ 1
':
)0,
3 cycles
(constant)
.;J~:---L.-.,--.1---,--.,~
__
:::=x==
:j:
,01(
1
1
)0101()0
5 cycles beIween accesses
(constant)
'
New felch
b91s
,
Repeated four times for complete burst
Figure 6-40. 8-Bit ROM/Flash Interface-Burst Read Timing
6-62
MPC106 PCIBIMC User's Manual
MOTOROLA
6.5.4 ROM/Flash Interface Write Operations
The MPC106 accommodates only single-beat, data path sized (8- or 64-bit), writes to Flash
memory. Software must partition larger data into individual data path sized (8- or 64-bit)
write operations. If an attempt is made to write to Flash with a data size other than the full
data path size, the MPC106 will assert TEA (transfer error acknowledge), provided TEA is
enabled in PICR!.
The MPC106 latches processor writes to system ROM space before initiating the actual
write operation to Flash. This is necessary to avoid contention on the multiplexed
paritylROM address signals. The 60x initiates the write to system ROM space and drives
parity during the data tenure, the MPC 106 latches the data, and then MPC 106 drives the
ROM address and data for the write to Flash. System logic (external to the MPC106) is
responsible for multiplexing high voltage to the Flash memory as required for write
operations.
PICRI [FLASH_WR_EN] must be set when performing write operations to Flash memory.
FLASH_WR_EN controls whether write operations to Flash memory are allowed.
FLASH_WR_EN is cleared at reset to disable write operations to Flash memory.
Writing to Flash can be locked out by setting PICR2[FLASH_WR_LOCKOUT]. When
this bit is set, the MPC106 disables writing to Flash memory, even if FLASH_WR_EN is
set. Once set, the FLASH_WR_LOCKOUT parameter can only be cleared by a hard reset. .
If the system attempts to write to read-only devices in a bank, then bus contention may
occur. This is because the write data is driven onto the data bus when the read-only device
is also trying to drive its data onto the data bus. This situation can be avoided by disabling
writes to the system ROM space using FLASH_WR_EN or FLASH_WR_LOCKOUT or
by connecting the Flash output enable (FOE) signal to the output enable on the read-only
device.
6.5.4.1 ROM/Flash Interface Write Timing
The parameter MCCRI [ROMNAL] controls the Flash memory write recovery time (that
is, the number of cycles between write pulse assertions). The actual recovery cycle count is
four cycles more than the value specified in ROMNAL. For example, when ROMNAL =
ObOOOO, the write recovery time is four clock cycles; when ROMNAL = ObOOOl, the write
recovery time is five clock cycles; when ROMNAL = ObOOlO, the write recovery time is six
clock cycles; and so on. ROMNAL is set to the maximum value at reset. To improve
performance, it is recommended that initialization software program a more appropriate
value for the actual device being used.
Figure 6-41 illustrates the write access timing of the Flash interface.
MOTOROLA
Chapter 6. Memory Interface
6-63
60x Bus Clock
AR[G-2O]
1
1
:,
:~
1
:/
1
1
:,
1
1
Ies
2
1
I(~)I
I ...
1
60x Data
1
Vpp
:/
5V'
X
'
1
:/
I
1
.1 ...
1
DATAO
I
I
1
ROMFAL
:,-4~1es
1
(coristant)
.1""
1
1
1
1
IROMNAL
.1""
1
•
X
1
1
113V 1
Note: Vpp multiplexed by system logic with appropriate setup time to write cycle.
Figure 6-41. Flash Memory Write Timing
6-64
MPC106 PCIBIMC User's Manual
MOTOROLA
Chapter 7
PCI Bus Interface
One of the primary functions of the MPC106 is to serve as a bridge between the 60x
processor bus (the host bus) and the PCI bus. The MPC106's PCI interface complies with
the PCI Local Bus Specification, Revision 2.1 and follows the guidelines in the PCI System
Design Guide, Revision 1.0, for host bridge architecture.
It is well beyond the scope of this manual to document the intricacies of the PCI bus. This
chapter provides a rudimentary description of PCI bus operations. The specific emphasis is
directed at how the MPC106 implements the PCI bus. It is strongly advised that anyone
designing a system incorporating PCI devices should refer to the PCI Local Bus
Specification, Revision 2.1 and the PCI System Design Guide, Revision 1.0, for a thorough
description of the PCI local bus.
NOTE
Much of the available PCI literature refers to a 16-bit quantity
as a word and a 32-bit quantity as a double word. Since this is
inconsistent with the terminology in this manual, the terms
'word' and 'double word' are not used in this chapter. Instead,
the number of bits or bytes indicates the exact quantity.
7.1 PCllnterface Overview
The PCI interface connects the processor and memory buses to the PCI bus, to which 110
components are connected. The PCI bus uses a 32-bit multiplexed, address/data bus, plus
various control and error signals. The PCI interface supports address and data parity with
error checking and reporting.
The PCI interface of the MPC 106 functions as both a master (initiator) and target device.
Internally, the PCI interface of the MPC106 is controlled by two state machines (one for
master and one for target) running independently of each other. This allows the MPCI06 to
run two separate transactions simultaneously. For example, if the MPC 106, as a master, is
trying to run a burst-write to a PCI device, it may get disconnected before finishing the
transaction. If another PCI device is granted the PCI bus and requests a burst-read from
system memory, the MPC106, as a target, can accept the burst-read transfer. When the
MPC 106 is granted mastership of the PCI bus, the burst-write transaction continues.
MOTOROLA
Chapter 7. PCI Bus Interface
7-1
As a master, the MPC 106 supports read and write operations to the PCI memory space, the
PCI 110 space, and the PCI 256-byte configuration space. As a master, the MPC 106 also
supports generating PCI special-cycle and interrupt-acknowledge transactions. As a target,
the MPC 106 supports read and write operations to system memory.
Internal buffers are provided for operations between the PCI bus and the 60x processor or
system memory. Processor read and write operations each have a 32-byte buffer, and
memory operations have one 32-byte read buffer and two 32-byte write buffers. See
Section 8.1, "Internal Buffers," for more information.
The interface can be programmed for either little-endian or big-endian formatted data, and
provides data swapping, byte enable swapping, and address translation in hardware. See
Appendix B, "Bit and Byte Ordering," for more information on the bi-endian features of
the MPC106.
7.1.1 The MPC106 as a PCI Master
Upon detecting a 60x-to-PCI transaction, the MPC106 requests the use ofthe PCI bus. For
60x -to-PCI bus write operations, the MPC 106 requests mastership of the PCI bus when the
60x completes the write operation on the 60x processor bus. For 60x-to-PCI read
operations, the MPC106 requests mastership ofthe PCI bus when it decodes that the access
is for PCI address space.
Once granted, the MPC 106 drives the 32-bit PCI address (AD[31-O]) and the bus command
(CIBE[3-0]) signals. The master interface supports reads and writes of up to 32 bytes
without inserting master-initiated wait states.
The master part of the interface can initiate master-abort cycles, recognizes target-abort,
target-retry, and target-disconnect cycles, and supports various device selection timings.
The master interface does not run fast back-to-back or interlocked accesses.
7.1.2 The M PC1 06 as a PCI Target
As a target, upon detection of a PCI address phase the MPC 106 decodes the address and
bus command to determine if the transaction is for system memory. If the transaction is
destined for system memory, the target interface latches the address, decodes the PCI bus
command, and forwards them to an internal control unit. On writes to system memory, data
is forwarded along with the byte enables to the internal control unit. On reads, four bytes
of data are provided to the PCI bus and the byte enables determine which byte lanes contain
meaningful data.
The target interface of the MPC106 can issue target-abort, target-retry, and targetdisconnect cycles. The target interface supports fast back-to-back transactions and
interlocked accesses using the PCI lock protocol.
7-2
MPC106 PCIB/MC User's Manual
MOTOROLA
The target interface uses the fastest device selection timing and can accept burst writes to
system memory of up to 32 bytes with no wait states. Burst reads from system memory are
also accepted with wait states inserted depending upon the timing of system memory
devices. The target interface disconnects when a transaction reaches the end of a cache line
(32 bytes).
7.2 PCI Bus Arbitration
The PCI arbitration approach is access-based. Bus masters must arbitrate for each access
performed on the bus. PCI uses a central arbitration scheme where each master has its own
unique request (REQ) output and grant (GNT) input signal. A simple request-grant
handshake is used to gain access to the bus. Arbitration for the bus occurs during the
previous access so that no PCI bus cycles are consumed due to arbitration (except when the
bus is idle).
The MPC106 does not function as the central PCI bus arbiter. It is the responsibility of the
system designer to provide for PCI bus arbitration. Regardless of the implementation, the
arbitration algorithm must be defined to establish a basis for a worst-case latency guarantee.
Latency guidelines are provided in the PCI Local Bus Specification. There are devices
available that integrate the central arbiter, interrupt controller, and PCI-to-ISA bridge
functions into a single device.
7.3 PCI Bus Protocol
This section provides a general description of the PCI bus protocol. Specific PCI bus
transactions are described in Section 7.4, "PCI Bus Transactions." Refer to Figure 7-1,
Figure 7-2, Figure 7-3, and Figure 7-4 for examples of the transfer-control mechanisms
described in this section.
All signals are sampled on the rising edge of the PCI bus clock (SYSCLK). Each signal has
a setup and hold aperture with respect to the rising clock edge, in which transitions are not
allowed. Outside this aperture, signal values or transitions have no significance.
7.3.1 Basic Transfer Control
The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase
followed by one or more data phases. Fundamentally, all PCI data transfers are controlled
by three signals-FRAME (frame), IRDY (initiator ready), and TRDY (target ready). A
master asserts FRAME to indicate the beginning of a PCI bus transaction and negates
FRAME to indicate the end of a PCI bus transaction. A master negates IRDY to force wait
cycles. A target negates TRDY to force wait cycles.
The PCI bus is considered idle when both FRAME and IRDY are negated. The first clock
cycle in which FRAME is asserted indicates the beginning of the address phase. The
address and bus command code are transferred in that first cycle. The next cycle begins the
first of one or more data phases. Data is transferred between master and target in each cycle
MOTOROLA
Chapter 7. PCI Bus Interface
7-3
that both IRDY and TRDY are asserted. Wait cycles may be inserted in a data phase by the
master (by negating IRDY) or by the target (by negating TROY).
Once a master has asserted IRDY, it cannot change IRDY or FRAME until the current data
phase completes regardless of the state of TRDY. Once a target has asserted TRDY or
STOP, it cannot change DEVSEL, TRDY, or STOP until the current data phase completes.
In simpler terms, once a master or target has committed to the data transfer, it cannot change
its mind.
When the master intends to complete only one more data transfer (which could be
immediately after the address phase), FRAME is negated and IRDY is asserted (or kept
asserted) indicating the master is ready. After the target indicates the final data transfer (by
asserting TRDY), the PCI bus may return to the idle state (both FRAME and IRDY are
negated) unless a fast back-to-back transaction is in progress. In the ca~e of a fast back-toback transaction, an address phase immediately follows the last data phase.
7.3.2 PCI Bus Commands
A PCI bus command is encoded in the CIBE[3-O] signals during the address phase of a PCI
transaction. The bus command indicates to the target the type of transaction the master is
requesting. Table 7-1 describes the PCI bus commands as implemented by the MPCI06.
Table 7-1. PCI Bus Commands
~[3-(JJ
7-4
PCI Bus Command
MPC106
Supports
asa Master
MPC106
Supports
as a Target
Definition
0000
Interruptacknowledge
Ves
No
The interrupt-acknowledge command is a
read (implicitly addressing the system
interrupt controller). Only one device on the
PCI bus should respond to the interruptacknowledge command. Other devices
ignore the interrupt-acknowledge
command. See Section 7.4.6.1, "Interrupt
Acknowledge Transactions," for more
information.
0001
Special-cycle
Ves
No
The special-cycle command provides a
mechanism to broadcast select messages
to all devices on the PCI bus. See
Section 7.4.6.2, "Special-Cycle
Transactions," for more information.
0010
liD-read
Ves
No
The .I/O-read command accesses agents
mapped into the PCI 110 space.
0011
liD-write
Ves
No
The I/O-write command accesses agents
mapped into the PCIIIO space.
0100
Reserved'
No
No
-
0101
Reserved'
No
No
-
MPC106 PCIB/MC User's Manual
MOTOROLA
Table 7-1. PCI Bus Commands (Continued)
C7BE[:HI]
PCI Bus Command
MPC106
Supports
as a Master
MPC106
Supports
as a Target
Definition
0110
Memory-read
Yes
Yes
The memory-read command accesses
either system memory, or agents mapped
into PCI memory space, depending on the
address. When a PCI master issues a
memory-read command to system memory,
the MPC106 (the target) fetches data lrom
the requested address to the end 01 the
cache line (32 bytes) from system memory,
even though all of the data may not be
requested by (or sent to) the master.
0111
Memory-write
Yes
Yes
The memory-write command accesses
either system memory, or agents mapped
into PCI memory space, depending on the
address.
1000
Reserved·
No
No
1001
Reserved·
No
No
-
1010
Configuration-read
Yes
No
The configuration-read command
accesses the 256-byte configuration space
of a PCI agent. A specific agent is selected
when its IDSEL signal is asserted during
the address phase. See Section 7.4.5,
"Configuration Cycles," for more detail of
PCI configuration cycles.
1011
Configuration-write
Yes
No
The configuration-write command accesses
the 256-byte configuration space of a PCI
agent. A specific agent is selected when its
IDSEL Signal is asserted during the address
phase. See Section 7.4.5.2, "Accessing the
PCI Configuration Space," for more detail of
PCI configuration accesses.
1100
Memory-read-multiple
No
Yes
The memory-read-multiple command
functions similar to the memory-read
command, but it also causes a prefetch of
the next cache line (32 bytes);
Note that for PCI reads from system
memory, prefetching for all reads may be
forced by setting bit 2 (PCI speculative read
enable) of PICR1. See Section 8.1.3.1.1,
·Speculative PCI Reads from System
Memory," for more information.
1101
MOTOROLA
Dual-address-cycle
No
No
The dual-address-cycle command is used
to transfer a 54-bit address (in two 32-bit
address cycles) to 54-bit addressable
devices. The MPC106 does not respond to
this command.
Chapter 7. PCI Bus Interface
7-5
Table 7-1. PCI Bus Commands (Continued)
cmE[3-0]
PCI Bus Command
MPC106
Supports
asa Master
MPC106
Supports
as aTarget
Definition
1110
Memory-read-line
Yes
Yes
The memory-read-line command indicates
that a master is requesting the transfer of
an entire cache line (32 bytes).
1111
Memory-write-andinvalidate
No
Yes
The memory-write-and-invalidate
command indicates that a master is
transferring an entire cache line (32 bytes).
and. if this data is in any cacheable
memory. that cache line needs to be
invalidated .
• Reserved command encodings are reserved for future use. the MPC106 does not respond to these commands.
7.3.3 Addressing
PCI defines three physical address spaces-PCI memory space, PCI 110 space, and PCI
configuration space. Access to the PCI memory and 110 space is straightforward, although
one must take into account the MPCI06 address map (A, B, or emulation mode map) being
used. The address maps are described in Section 3.1, "Address Maps." Access to the PCI
configuration space is described in Section 7.4.5, "Configuration Cycles."
Address decoding on the PCI bus is performed by every device for every PCI transaction.
Each agent is responsible for decoding its own address. PCI supports two types of address
decoding-positive decoding and subtractive decoding. For positive decoding, each device
is looking for accesses in the address range that the device has been assigned. For
subtractive decoding, one device on the bus is looking for accesses that no other device has
claimed. See Section 7.3.4, "Device Selection," for information about claiming
transactions.
The information contained in the two low-order address bits (AD[l-On varies by the
address space (memory, 110, or configuration). Regardless of the encoding scheme, the two
low-order address bits are always included in parity calculations.
7.3.3.1 Memory Space Addressing
For memory accesses, PCI defines two types of burst ordering controlled by the two loworder bits of the address-linear incrementing (AD[l-O] = ObOO) and cache wrap mode
(AD[l-O] = ObIO). The other two AD[1-O] possibilities (ObOI and Obi 1) are reserved. As
a target, the MPCI06 executes a target disconnect after the first data phase completes if
AD[l-O] = ObOI or AD[l-O] = Obll during the address phase of a system memory access.
As a master, theMPC 106 always encodes AD[I-O] = ObOO for PCI memory space accesses.
For linear incrementing mode, the memory address is encoded/decoded using AD[31-2].
Thereafter, the address is incremented by 4 bytes after each data phase completes until the
transaction is terminated or completed (a 4-byte data width per data phase is implied). Note
that the two low-order bits of the address bus are still included in all parity calculations.
7-6
MPC106 PCIB/MC User's Manual
MOTOROLA
For cache wrap mode (AD[1-0] = Ob 10) reads, the critical memory address is decoded
using AD[3I-2]. The address is incremented by 4 bytes after each data phase completes
until the end of the cache line is reached. Thereafter, the address wraps to the beginning of
the current cache line and continues incrementing until the entire cache line (32 bytes) is
read. The MPC 106 does not support cache wrap mode write operations and executes a
target disconnect after the first data phase completes for writes with AD[I-O] =ObIO.
Again, note that the two low-order bits of the address bus are still included in all parity
calculations.
7.3.3.2 1/0 Space Addressing
For PCI 110 accesses, all 32 address signals (AD[31-0]) are used to provide an address with
granularity of a single byte. If the target is addressable by more than one byte, the AD[10] signals indicate the least-significant valid byte involved in the transfer.
Once a target has claimed an 110 access, it must determine if it can complete the entire
access as indicated by the byte enable signals. If all the selected bytes are not in the address
range of the target, the entire access cannot complete. In this case, the target does not
transfer any data, and terminates the transaction with a target-abort.
7.3.3.3 Configuration Space Addressing
PCI supports two types of configuration access, which use different formats for the AD[310] signals during the address phase. The two low-order bits of the address indicate the
format used for the configuration address phase-type 0 (AD[1-O] = ObOO) or type I
(AD[1-O] =ObOI). Both address formats identify a specific device and a specific
configuration register for that device. See Section 7.4.5, "Configuration Cycles," for
descriptions of the two formats.
7.3.4 Device Selection
The DEVSEL signal is driven by the target of the current transaction. DEVSEL indicates
to the other devices on the PCI bus that the target has decoded the address and claimed the
transaction. DEVSEL may be driven one, two, or three clocks (fast, medium, or slow device
select timing) following the address phase. Device select timing is encoded into the device's
configuration space status register. If no agent asserts DEVSEL within three clocks of
FRAME, the agent responsible for subtractive decoding may claim the transaction by
asserting DEVSEL.
A target must assert DEVSEL (claim the transaction) before or coincident with any other
target response (assert its TROY, STOP, or data signals). In all cases except target-abort,
once a target asserts DEVSEL, it must not negate DEVSEL until FRAME is negated (with
IRDY asserted) and the last data phase has completed. For normal termination, negation of
DEVSEL coincides with the negation of TRDY or STOP.
If the first access maps into a target's address range, that target asserts DEVSEL to claim
the access. But, if the master attempts to continue the burst access across the resource
boundary, then the target must issue a target disconnect.
MOTOROLA
Chapter 7. PCI Bus Interface
7-7
The MPCI06 is hardwired for fast device select timing (PCI status register[10-9] = ObOO).
Therefore, when the MPCI06 is the target of a transaction (system memory access), it
asserts DEVSEL one clock cycle following the address phase.
As a master, ifthe MPC106 does not see the assertion of DEVSEL within four clocks after
the address phase (five clocks after it asserts FRAME), it terminates the transaction with a
master-abort.
7.3.5 Byte Alignment
The byte enable (CIBE[3-O], during a data phase) signals are used to determine which byte
lanes carry meaningful data. The byte enable signals may enable different bytes for each of
the data phases. The byte enables are valid on the edge of the clock that starts each data
phase and stay valid for the entire data phase. Note that parity is calculated on all bytes
regardless of the byte enables. See Section 7.6.1, "PCI Parity," for more information.
If the MPC 106, as a target, sees no byte enables asserted, it completes the current data phase
with no permanent change. This implies that on a. read transaction, the MPC106 expects
that the data is not changed, and on a write transaction, the data is not stored.
7.3.6 Bus Driving and Turnaround
A turnaround cycle is required, to avoid contention, on all signals that may be driven by
more than one agent. The turnaround cycle occurs at different times for different signals.
The IRDY, TROY, DEVSEL, and STOP signals use the address phase as their turnaround
cycle. FRAME, CIBE[3-O], and AD[31-O] signals use the idle cycle between transactions
(when both FRAME and IRDY are negated) as their turnaround cycle. The PERR signal
has a turnaround cycle on the fourth clock after the last data phase.
The address!data signals, AD[31-O], are driven to a stable condition during every address!
data phase. Even when the byte enables indicate that byte lanes carry meaningless data, the
signals carry stable values. Parity is calculated on all bytes regardless of the byte enables.
See Section 7.6.1, "PCI Parity," for more information.
7.4 pel Bus Transactions
This section provides descriptions of the PCI bus transactions. All bus transactions follow
the protocol as described in Section 7.3, "PCI Bus Protocol." Read and write transactions
are similar for the memory and I/O spaces, so they are treated as a generic "read
transaction" or a generic "write transaction."
The timing diagrams show the relationship of significant signals involved in bus
transactions.When a signal is drawn as a solid line, it is actively being driven by the current
master or target. When a signal is drawn as a dashed line, no agent is actively driving it.
High-impedance signals are indicated to have indeterminate values when the dashed line is
between the two rails.
7-8
MPC106 PCIBIMC User's Manual
MOTOROLA
The terms 'edge' and 'clock edge' always refer to the rising edge of the clock. The terms
'asserted' and 'negated' always refer to the globally visible state of the signal on the clock
edge, and not to signal transitions. '(:lc' represents a turnaround cycle in the timing
ILl
eli agrams.
7.4.1 Read Transactions
Figure 7-1 illustrates a PCI single-beat read transaction. Figure 7-2 illustrates a PCI burst
read transaction. The transaction starts with the address phase, occurring when a master
asserts FRAME. During the address phase, AD[31-O] contain a valid address and
CIBE[3-0] contain a valid bus command.
The first data phase of a read transaction requires a turnaround cycle. This allows the
transition from the master driving AD[31-O] as address signals to the target driving AD[310] as data signals. The turnaround cycle is enforced by the target using the TRDY signal.
The earliest the target can provide valid data is one cycle after the turnaround cycle. The
target must drive the address/data signals when DEVSEL is asserted.
During the data phase, the commandlbyte enable signals indicate which byte lanes are
involved in the current data phase. A data phase may consist of a data transfer and wait
cycles. The CIBE[3-O] signals remain actively driven for both reads and writes from the
first clock of the data phase through the end of the transaction.
A data phase completes when data is transferred, which occurs when both IRDY and TRDY
are asserted on the same clock edge. When either IRDY or TRDY is negated, a wait cycle
is inserted and no data is transferred. The master indicates the last data phase by negating
FRAME when IRDY is asserted. The transaction is considered complete when data is
transferred in the last data phase.
SYSCLK
AO[31-O]
I
~(3-0]
e
--@®
I
~
l'RAME
~I
I
I
IROY
\1
~
I
I
I
mv
B~E ENA~LES
I
I
I
\1
I
I
I
I
I
I
I
I
/1
I
I
/1
\J~
Figure 7-1. PCI Single-Beat Read Transaction
MOTOROLA
Chapter 7. PCI Bus Interface
7-9
SYSCLK
AD[31-Q]
~[3-0]
FImlE"
DATAl
~
I
I
I
I ENABLES
I 1~
---:-@D( BYTE
~:
I
I
I
I
I
\1
lImY
I
I
\1
DEVSEL
I
I
I
I
BYTE ENABLES 2
;II
I
I
I
I
I
/1
I
I
I
1
1
0~
TFil5V
0
/1
1
-I
Figure 7-2. PCI Burst Read Transaction
7.4.2 Write Transactions
Figure 7-3 illustrates a PCI single-beat write transaction. Figure 7-4 illustrates a PCI burst
write transaction. The transaction starts with the address phase, occurring when a master
asserts FRAME. A write transaction is similar to a read transaction except no turnaround
cycle is needed following the address phase because the master provides both address and
data. The data phases are the same for both read and write transactions. Although not shown
in the figures, the master must drive the byte enable signals, even if the master is not ready
to provide valid data (IRDY negated).
SYSCLK
AD[31-Q]
--@®(
I
~[3-0]
FIWJE"
lImY
l5EVSE[
TFil5V
I
~
DATA
I
I
BYTE
~I
I
I
\1
I
I
I
I
I
I
I
I
I
I
I
~NABLE~
I
I
I
I
I
I
I
I
\1
I
1
/1
I
/1
0:
Figure 7-3. PCI Single-Beat Write Transaction
7-10
MPC106 PCIBIMC User's Manual
MOTOROLA
SYSCLK
AD[3l-O]
~ DATAl
I
CiBE[3-{)]
I
~
~I
I
I
I
BEsl
I
~I--~--~~---r--+-~~
Figure 7-4. PCI Burst Write Transaction
7.4.3 Transaction Termination
Termination of a PCI transaction may be initiated by either the master or the target. The
master is ultimately responsible for bringing all transactions to conclusion, regardless of the
cause of the termination. All transactions are concluded when FRAME and IRDY are both
negated, indicating the bus is idle.
7.4.3.1 Master-Initiated Termination
Normally, a master initiates termination by negating FRAME and asserting IRDY. This
indicates to the target that the final data phase is in progress. The final data transfer occurs
when both TRDY and IRDY are asserted. The transaction is considered complete when data
is transferred in the last data phase. After the final data phase, both FRAME and IRDY are
negated (the bus becomes idle).
There are three types of master-initiated termination:
•
Completion Completion refers to termination when the master has concluded its
intended transaction. This is the most common reason for termination.
•
Timeout
•
Master-abort Master-abort is an abnormal case of master-initiated termination. If no
device (including the subtractive decoding agent) asserts DEVSEL to
claim a transaction, the master terminates the transaction with a
master-abort. For a master-abort termination, the master negates
FRAME and then negates IRDY on the next clock. If a transaction is
terminated by master-abort (except for a special-cycle command), the
received master-abort bit (bit 13) of the PCI status register is set.
MOTOROLA
Timeout refers to termination when the master loses its bus grant
(GNT is negated) and its internal latency timer has expired. The
intended transaction is not necessarily concluded. Note that the
MPC 106 does not have a latency timer. Latency for the MPC 106
acting as a master is determined by the target.
Chapter 7. PCI Bus Interface
7-11
As a master, if the MPC106 does not detect the assertion of DEVSEL within four clocks
following the address phase (five clocks after asserting FRAME), it terminates the
transaction with a master-abort. On reads that are aborted, the MPC106 returns all Is
(OxFFFF_FFFF). On writes that are aborted, the data is lost.
7.4.3.2 Target-Initiated Termination
By asserting the STOP signal, a target may request that the master terminate the current
transaction. Once asserted, the target holds STOP asserted until the master negates
FRAME. Data mayor may not be transferred during the request for termination. If TRDY
and IRDY are asserted during the assertion of STOP, data is transferred. However, ifTRDY
is negated when STOP is asserted, it indicates that the target will not transfer any more data,
and the master therefore does not wait for a final data transfer as it would in a completion
termination.
When a transaction is terminated by STOP, the master must negate its REQ signal for a
minimum of two PCI clocks, one being when the bus goes to the idle state (FRAME and
IRDY negated). If the master intends to complete the transaction, it must reassert its REQ
immediately following the two clocks or potential starvation may occur. If the master does
not intend to complete the transaction, it can assert REQ whenever it needs to use the PCI
bus again.
There are three types of target-initiated termination:
•
Disconnect
Disconnect refers to termination requested because the target is
temporarily unable to continue bursting. Disconnect implies that some
data has been transferred. The master may restart the transaction at a
later time starting with the address of the next untransferred data.
(That is, data transfer may resume where it left off.)
•
Retry
Retry refers to termination requested because the target is currently-in
a state where it is unable to process the transaction. Retry implies that
no data was transferred. The master may start the entire transaction
over again at a later time. Note that the PCI Local Bus Specification,
Revision 2.1 requires that all retried transactions must be completed.
•
Target-abort Target-abort is an abnormal case of target-initiated termination.
Target-abort is used when a fatal error has occurred, or when a target
will never be able to respond. Target-abort is indicated by asserting
STOP and negating DEVSEL. This indicates that the target requires
termination of the transaction and does not want the transaction
retried. If a transaction is terminated by target-abort, the received
target-abort bit (bit 12) of the master's status register and the signaled
target-abort bit (bit 11) of the target's status register is set. Note that
any data transferred in a target-aborted transaction may be corrupt.
7-12
MPC106 PCIBIMC User's Manual
MOTOROLA
As a target, the MPCI06 terminates a transaction with a target disconnect due to the
following:
•
It is unable to respond within eight PCI clocks (not including the first data phase).
•
A cache line (32 bytes) of data was transferred. (See the discussion of cache wrap
mode in Section 7.3.3.1, "Memory Space Addressing," for more information.)
•
The last four bytes of a cache line was transferred in linear-incrementing address
mode. (See the discussion oflinear-incrementing mode in Section 7.3.3.1, "Memory
Space Addressing," for more information.)
•
If AD[1-O] = ObOI or AD[l-O] = Obll during the address phase of asystem
memory access. (See Section 7.3.3.1, "Memory Space Addressing," for more
information. )
As a target, the MPC106 responds to a transaction with a retry due to the following:
•
A 60x bus copy-back operation is in progress.
•
A PCI write to system memory was attempted when the internal PCI-to-systemmemory-write buffers (PCMWBs) are full.
•
A nonexclusive access was attempted to system memory while the MPC106 is
locked.
•
A configuration write to a PCI device is underway and
PICR2[NO_SERIAL_CFG] = o.
•
An access to one of the MPCI06 internal configuration registers is underway.
•
The 32-clock latency timer has expired and the first data phase was not begun.
As a target, the MPC106 responds with a target-abort if a PCI master attempts to write to
the ROMlFlash ROM space in address map B. On PCI writes to system memory, if an
address parity error or data parity error occurs, the MPC106 aborts the transaction
internally, but continues the transaction on the PCI bus.
Figure 7-5 shows several target-initiated terminations. The three disconnect terminations
are unique in the data transferred at the end of the transaction. For disconnect A, the master
is negating IRDY when the target asserts STOP and data is transferred only at the end of
the current data phase. For disconnect B, the target negates TRDY one clock after it asserts
STOP, indicating that the target can accept the current data, but no more data can be
transferred. For the disconnect without data, the target asserts STOP when TRDY is
negated indicating that the target cannot accept any more data.
MOTOROLA
Chapter 7. PCI Bus Interface
7-13
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7-34
MPC106 PCIS/MC User's Manual
MOTOROLA
Chapter 8
Internal Control
The MPC106 uses internal buffering to store addresses and data moving through it, and to
maximize opportunities for concurrent operations. An internal control unit directs the flow
of transactions through the MPC 106, performing internal arbitration and coordinating the
internal and external snooping. This chapter describes the internal buffering and arbitration
logic of the MPC 106.
8.1 Internal Buffers
For most operations, the data is latched internally in one of seven data buffers. The
exception is processor accesses to system memory. Data transfers between the 60x
processor and system memory, with the exception of snoop copy-backs and burst writes
when ECC is enabled, occur directly on the shared data bus, so no internal data buffering
is required for those transactions.
Each of the seven data buffers has a corresponding address buffer. An additional buffer
stores the address of any 60x processor accesses to system memory. All transactions
entering the MPC106 have their addresses stored in the internal address buffers. The
address buffers allow the addresses to be snooped as other transactions attempt to go
through the MPC 106. This is especially important for write transactions that enter the
MPCI06 because memory can be updated out-of-order with respect to other transactions.
The MPC 106 performs 60x bus snoop transactions (provided snooping is enabled) for each
PCI access to system memory to enforce coherency between the PCI-initiated access and
the L1 and L2 caches. All addresses are snooped in the order that they are received from the
PCI bus. For systems that do not require hardware-enforced coherency, snooping can be
disabled by setting the CF_NO_SNOOP parameter in PICR2. Note that if snooping is
disabled, the PC;I exclusive access mechanism (the LOCK signal) does not affect the
transaction. That is, the transaction will complete, but the 60x processor will not be
prohibited from accessing the cache line.
Figure 8-1 depicts the organization of the internal buffers.
MOTOROLA
Chapter 8. Internal Control
8-1
60x Processor/L2 Interface Control Block
60x Processor/System Memory
Buffers
60x Processor/PCI
Buffers
Memory Interface
Control Block
PCI/System Memory
Buffers
PCI Interface Control Block
Figure 8-1. MPC1061nternai Buffer Organization
8.1.1 60x Processor/System Memory Buffers
Because systems using the MPCI06 have.a shared data bus between the processor, L2
cache, and system memory, for most cases it is unnecessary to buffer data transfers between
these devices. However, there is a 32-byte copy-back buffer which is used for temporary
storage ofL! copy-back or external L2 copy-back operations due to snooping PCI-initiated
reads from memory, L2 cast-outs, and processor burst writes when ECC is enabled. The
copy-back buffer can only be in one of two states-invalid or modified with respect to
system memory. Since the buffer is only used for burst write data, the entire cache line in
the buffer is always valid if any part of the cache line is valid.
Figure 8-2 shows the address and data buffers between the 60x processor bus and the
system memory bus.
Processor Address/Control
Processor/Memory Oata
Memory
"
=,/
,T
Transaction
Address Buffer
!!
Copy-Back 1 A 1001011021031
Buffer
!I
Memory Row/Column Address
Figure 8-2. 60x Processor/System Memory Buffers
8-2
MPC106 PCIB/MC User's Manual
MOTOROLA
In the case of a snoop for a PCI read from system memory that causes an Ll or external L2
copy-back, the copy-back data is simultaneously latched in the copy-back buffer and the
PCI-read-from-system-memory buffer (PCMRB). Once the L1 or external L2 copy-back is
complete, the data is forwarded to the PCI agent from the PCMRB. The MPC106 flushes
the data in the copy-back buffer to system memory at the earliest available opportunity.
L2 cast-outs are caused by a 60x processor transaction that misses in the L2 cache, and the
cache line in the L2 that will be replaced currently holds modified data. The MPC 106
latches the modified data from the L2 to minimize the latency of the original 60x processor/
system memory transaction. The MPC106 flushes the data in the copy-back buffer to
system memory at the earliest available opportunity. Note that the copy-back buffer is also
used for L2 cache flush operations.
For processor burst writes to memory with ECC enabled, the MPC106 uses the copy-back
buffer .as a temporary holding area while it generates the appropriate ECC codes to send to
memory.
Once the copy-back buffer has been filled, the data remains in the buffer until the system
memory bus is available to flush the copy-back buffer contents to system memory. During
the time that modified data waits in the copy-back buffer, all transactions to system memory
space are snooped against the copy-back buffer. If a 60x processor burst write to system
memory hits in the copy-back buffer, the copy-back buffer is invalidated. Also, since the L1
cache in the 60x processor can contain a more recently modified version of a cache line than
that in the copy-back buffer, all PCI-initiated transactions that hit in the copy-back buffer
cause a snoop broadcast on the 60x processor bus (provided snooping is enabled).
8.1.2 60x Processor/PCI Buffers
There are three data buffers for processor accesses to PCI--one 32-byte processor-to-PCIread buffer (PRPRB) for processor reads from PCI, and two 16-byte processor-to-PCIwrite buffers (PRPWBs) for processor writes to PCI. Figure 8-3 shows the address and data
buffers between the 60x processor bus and the PCI bus.
Processor Address/Control
ProcessorlMemory Oata
I
+
1 1001 011
1 11021 031
Processor/PCI AO
Write Buffers
A
(PRPWBs)
+
!
1 100 101 02 103 1
+
Processor/PC I A
Read Buffer
(PRPRB)
PCI Address/Oata
Figure 8-3. 60x ProcessorlPCI Buffers
MOTOROLA
Chapter 8. Internal Control
8-3
8.1.2.1 Processor-to-PCI-Read Buffer (PRPRB)
60x processor reads from PCI require buffering for two primary reasons. First, the
processor bus uses a critical-word-first protocol, while the PCI bus uses a zero-word-first
protocol. The MPC106 requests the data zero-word-first, latches the requested data, and
then delivers the data to the 60x processor critical-word-first.
The second reason is that if the target for a processor read from PCI disconnects part way
through the data transfer, the MPCI06 may have to handle a system memory access from
an alternate PCI master before the disconnected transfer can continue.
When the processor requests data from the PCI space, the data received from PCI is stored
in the PRPRB until all requested data has been latched. The MPC 106 does not terminate
the address tenure of the 60x transaction until all requested data is latched in the PRPRB.
If the PCI target disconnects in the middle of the data transfer and an alternate PCI master
acquires the bus and initiates a system memory access, the MPC106 retries the 60x
processor so that the incoming PCI transaction can be snooped. A PCI-initiated access to
system memory may require a snoop transaction on the 60x processor bus, and a copy-back
may be necessary. The MPC106 does not provide the data to the 60x bus (for the processor
to PCI read transaction) until all outstanding snoops for PCI writes to system memory have
completed. Note that if a processor read from PCI transaction is waiting for a PCWMB
snoop to complete, all subsequent requests for PCI writes to system memory will be retried
on the PCI bus.
The PCI interface of the MPC106 continues to request the PCI bus until the processor's
original request is completed. When the next processor transaction starts, the address is
snooped against the address of the previous transaction (in the internal address buffer) to
verify that the same data is being requested. Once all the requested data is latched, and all
PCI write to system memory snoops have completed, the MPC106 asserts AACK and
DBGn (as soon as the 60x data bus is available) and completes the data transfer to the
processor. If a second processor starts a new transaction, the address cannot match the
disconnected transaction address. If the new transaction is not a read from PCI, it proceeds
normally; if the transaction is a read from PCI, it must wait until the disconnected
transaction completes before proceeding.
For example, if the processor initiates a critical-word-first burst read, starting with the
second double word of the cache line, the read on the PCI bus begins with the cache-linealigned address. If the PCI target disconnects after transferring the first half of the cache
line, the MPC106 re-arbitrates for the PCI bus, and when granted, initiates a new
transaction with the address of the third double word of the line. If an alternate PCI master
requests data from system memory while the MPC106 is waiting for the PCI bus grant, the
MPC106 retries the processor transaction to allow the PCI-initiated transaction to snoop the
processor bus. When the processor snoop is complete, the subsequent processor transaction
is compared to the latched address and attributes of the PRPRB to ensure that the processor
is requesting the same data. Once all data requested by the processor is latched in the
PRPRB, the data is transferred to the processor, completing the transaction.
8·4
MPC106 PCIB/MC User's Manual
MOTOROLA
8.1.2.2 Processor-to-PCI-Write Buffers (PRPWBs)
There are two 16-byte buffers for processor writes to PCI. These buffers can be used
together as one 32-byte buffer for processor burst writes to PCI, or separately for singlebeat writes to PCI. This allows the MPC 106 to support both burst transactions and streams
of single-beat transactions. The MPC 106 performs store gathering (if enabled) of
sequential accesses within the 16-byte range that makes up either the first or second half of
the cache line. All transfer sizes are gathered if enabled (PICR1[ST_GATH_EN] = 1).
The internal buffering minimizes the effect of the slower PCI bus on the higher-speed 60x
processor bus. Once the processor write data is latched internally, the 60x processor bus is
available for subsequent transactions without having to wait for the write to the PCI target
to complete. Note that both PCI memory and 110 accesses are buffered. Device drivers must
take into account that writes to 110 devices on the PCI bus are posted. The processor may
believe that the write has completed while the MPC 106 is still trying to acquire mastership
of the PCI bus.
If the processor initiates a burst write to PCI, the 60x data transfer is delayed until all
previous writes to PCI are completed, and then the burst data from the 60x processor fills
the two PRPWBs. The address and transfer attributes are stored in the first address buffer.
For a stream of single-beat writes, the data for the first transaction is latched in the first
buffer and the MPC106 initiates the transaction on the PCI bus. The second single-beat
write is then stored in the second buffer. For subsequent single-beat writes, store gathering
is possible if the incoming write is to sequential bytes in the same half cache line as the
previously latched data. Store gathering is only used for writes to PCI memory space, not
for writes to PCI 110 space. The store gathering continues until the buffer is scheduled to
be flushed or until the processor issues a synchronizing transaction.
For example, if both PRPWBs are empty and the 60x processor issues a single-beat write
to PCI, the data is latched in the first buffer and the PCI interface of the MPC106 attempts
to acquire the PCI bus for the transfer. The data for the next 60x-to-PCI write transaction is
latched in the second buffer, even if the second transaction's address falls within the same
half cache line as the first transaction. While the PCI interface is busy with the first transfer,
any sequential processor single-beat writes within the same half cache line as the second
transfer are gathered in the second buffer until the PCI bus becomes available.
8.1.3 PCI/System Memory Buffers
There are three data buffers for PCI accesses to system memory--one 32-byte PCI-tosystem memory read buffer (PCMRB) for PCI reads from system memory and two 32-byte
PCI-to-system memory write buffers (PCMWBs) for PCI writes to system memory.
Figure 8-4 shows the address and data buffers between the PCI bus and the system memory.
MOTOROLA
Chapter 8. Internal Control
8-5
Memory Row/Column Address
Processor Address/Control
PC,I/Memory
Wnte Buffers
(PCMWBs)
Processor/Memory Data
t
1A 1001011021031
1A 1001011021031
PCI/Memory
Read Buffer A
(PCMRB)
I 1001011021031
f
PCI Address/Oata
Figure 8-4. PCVSystem Memory Buffers
Note that many PCI accesses to system memory are snooped on the 60x processor bus to
ensure coherency between the PCI bus, system memory, the L1 cache of the 60x processor,
and the L2 cache (if present). All snoops for PCI accesses to system memory are performed
strictly in-order. Table 8-1 summarizes the snooping behavior of PCI accesses to system
memory that hit in one of the internal buffers.
Table 8-1. Snooping Behavior Caused by a Hit in an Internal Buffer
PCI Transaction
Hit In Internal Buffer
Snoop Required
Read
Copy-back
Yes
Read (not locked)
PCMRB
No
Read (first access of a locked
transfer)"
PCMRB
Yes
Read (not locked)
PCMWB
No
Read (first access of a locked
transfer)"
PCMWB
Yes
Write
Copy-back
Yes
Write
PCMRB
Yes
Write
PCMWB
No
* Only reads can start an exclusive access (locked transfer), The first locked transfer
must be snooped so that the cache line in the L1 is invalidated,
8-6
MPC106 PCIB/MC User's Manual
MOTOROLA
8.1.3.1 PCI-to-System-Memory-Read Buffer (PCMRB)
When a PCI device initiates a read from system memory, the address is snooped on the 60x
processor bus (provided snooping is enabled). If the memory interface is available, the
memory access is started simultaneously with the snoop. If the snoop results in a hit in
either the L 1 or L2 cache, the MPC 106 cancels the system memory access.
Depending on the outcome of the snoop, the requested data is latched into either the 32byte PCI-to-system-memory-read buffer (PCMRB), or into both the copy-back buffer and
the PCMRB (as described in Section 8.1.1, "60x Processor/System Memory Buffers").
•
If the snoop hits in the L1 or externally-controlled L2, the copy-back data is written
to both the copy-back buffer and to the PCMRB. The data is forwarded to the PCI
bus from the PCMRB, and to system memory from the copy-back buffer.
•
If the snoop hits in the internally-controlled L2, the data is written to the PCMRB
. and sent to PCI without changing the internal state of the data in the L2. Note that a
copy-back to system memory is unnecessary because the state of the data in the L2
remains unchanged.
•
If the snoop does not hit in either the L1 or L2, the PCMRB is filled from system
memory starting at the requested address to the end of the cache line. If the PCI
agent requested a cache wrap mode transfer, the beginning of the cache line is then
loaded into the PCMRB.
The data is forwarded to the PCI bus as soon as it is received, not when the complete cache
line 1;tas been written into the PCMRB. The addresses for subsequent PCI reads are
compared to the existing address, so if the new access falls within the same cache line and
the requested data is already latched in the buffer, the data can be forwarded to PCI without
requiring a snoop or another memory transaction.
If a PCI write to system memory hits in the PCMRB, the PCMRB is invalidated and the
address is snooped on the processor bus. If the 60x processor accesses the address in the
PCMRB, the PCMRB is invalidated.
8.1.3.1.1 Speculative PCI Reads from System Memory
To minimize the latency for large block transfers, the MPC106 provides the ability to
perform speculative PCI reads from system memory. When speculative reading is enabled,
the MPC 106 starts the snoop of the next sequential cache line address when the current PCI
read is accessing the third double word (the second half) of the cache line in the PCMRB.
Once the speculative snoop response is known and the MPC 106 has completed the current
PCI read, the data at the speculative address is fetched from system memory and loaded into
the PCMRB in anticipation of the next PCI request.
Note that the assertion of CASn for the speculative operation is delayed until PCI is finished
reading the data currently latched in the PCMRB. If a different address is requested, the
speculative operation is halted and any data latched in the PCMRB is invalidated.
Speculative PCI reads are enabled on a per access basis by using the PCI memory-read-
MOTOROLA
Chapter 8. Internal Control
8-7
multiple command. Speculative PCI reads can be enabled for all PCI memory read
commands (memory-read, memory-read-multiple, and memory-read-line) by setting bit 2
in PICRI.
The MPCI06 starts the speculative read operation only under the following conditions:
•
PICRl[2] = 1 or the current PCI read access is from a memory read-multiple
command.
•
The current PCI read access started at the beginning of the cache line.
•
The MPC 106 is accessing the third double word of the cache line in the PCMRB for
the current PCI read.
•
No internal buffer flushes are pending.
•
The access is to system memory space. (The MPC106 does not perform speculative
reads on system ROM space.)
8.1.3.2 PCI-to-System-Memory-Write Buffers (PCMWBs)
For PCI write transactions to system memory, the MPCI06 employs two PCMWBs. The
PCMWBs hold up to one cache line (32 bytes) each. Before PCI data is transferred to
system memory, the address must be snooped on the 60x processor bus (if snooping is
enabled). The buffers allow for the data to be latched while waiting for a snoop response.
The write data can be accepted without inserting wait states on the PCI bus. Also, two
buffers allow a PCI master to write to one buffer, while the other buffer is flushing its
contents to system memory. Both PCMWBs are capable of gathering for writes to the same
cache line.
If the snoop on the 60x processor bus hits modified data in either the L1 or L2 cache, the
snoop copy-back data is merged with the data in the PCMWB, and the full cache line is sent
to memory. For the PCI memory-write-and-invalidate command, a snoop hit in either the
L1 or L2 cache invalidates any modified cache line without requiring a copy-back.
Note that a PCI transaction that hits in either of the PCMWBs does not require a snoop on
the 60x processor bus. However, if a PCI write address hits in the PCI-read-from-systemmemory buffer (PCMRB), the MPC106 invalidates the PCMRB and snoops the address on
the 60x processor bus.
When the PCI write is complete and the snooping is resolved, the data is flushed to memory
at the first available opportunity.
For a stream of single-beat writes, the data for the first transaction is latched in the first
buffer and the MPC106 initiates the snoop transaction on the 60x processor bus. For
subsequent single-beat writes, gathering is possible if the incoming write is to the same
cache line as the previously latched data. Gathering to the first buffer can continue until the
buffer is scheduled to be flushed, or until a write occurs to a different address. If there is
valid data in both buffers, further gathering is not supported until one of the buffers has been
flushed.
8-8
MPC106 PCIB/MC User's Manual
MOTOROLA
8.2 Internal Arbitration
The arbitration for the PCI bus is performed externally. All processor to PCI transactions
are performed strictly in-order. Also, all snoops for PCI accesses to system memory are
performed in order (if snooping is enabled). However, the MPC106 performs arbitration
internally for the shared processor/memory data bus. The arbitration for the processor/
memory data bus employs the priority scheme shown in Table 8-2.
Table 8-2. Internal Arbitration Priorities
Operation
Priority
A high-priority copy-back buffer flush due to one of the following:
A PCI access to system memory hits in the copy-back buffer.
An l2 cast-out occurs simultaneously with a PCI access to system memory and both the cast-out
and the PCI access are to the same address in system memory.
An L2 cast-out hits a nonsnooped address in the PCMWB.
A 60x processor burst write to system memory with ECC enabled hits a nonsnooped address in
thePCMWB.
A 60x processor burst write to system memory with ECC enabled hits a nonsnooped address in
the PCMRB.
1
··
··
·
2
A PCI read from system memory (with snoop complete)
3
··
··
··•
4
5
6
Priority 60x processor or L2 cache transfers including the following:
An L2 cache copy-back (or PCMRB data transfer) due to a PCI read snoop hit
A 60x processor read from system memory
A SOx processor to L2 cache transfer
A fast L2 cache cast-out
A high priority PCMWB flush due to one of the following:
A PCI read hits in the PCMWB
The PCMWB is full and another PCI write to system memory starts
A 60x processor to system memory read hits in the PCMWB
• A 60x processor to system memory single-beat write hits in the PCMWB
A medium priority copy-back buffer flush due to one of the following:
A 60x processor read hits in the copy-back buffer.
A 60x processor single-beat write hits in the copy-back buffer.
The copy-back buffer is full and new data needs to be written to it.
··
·
··
···
Normal 60x processor or L2 cache transfers including the following:
A SOx processor write to system memory
A snoop copy-back due to a PCI write snoop
A 60x processor read from PCI
A SOx processor write to PCI
A copy-back buffer fill
7
A PCI read from system memory (with snoop not complete)
8
A low-priority copy-back buffer flush
9
A low-priority PCMWB flush
10
A PCMRB prefetch from system memory due to a speculative PCI read operation
MOTOROLA
Chapter 8. Internal Control
8-9
Chapter 9
Error Handling
The MPCI06 provides error detection and reporting on the three primary interfaces (60x
processor interface, memory interface, and PCI interface). This chapter describes how the
MPC106 handles different error (or interrupt) conditions.
Errors detected by the MPC 106 are reported to the 60x processor by asserting the machine
check (MCP) or transfer error acknowledge (TEA) signal. The system error (SERR) and
parity error (PERR) signals are used to report errors on and to the PCI bus. The MPCI06
provides the NMI signal for ISA bridges to report errors on the ISA bus. The MPC106
internally synchronizes any asynchronous error signals.
The PCI command and status registers, and the error handling registers enable or disable
the reporting and detection of specific errors. These registers are described in Chapter 3,
"Device Programming."
The MPC106 detects illegal transfer types from the 60x processor, illegal L2 copy-back
errors, illegal Flash write transactions, PCI address and data parity errors, accesses to
memory addresses out of the range of physical memory, memory parity errors, memory
refresh overflow errors, L2 cache parity errors, ECC errors, PCI master-abort cycles, and
PCI received target-abort errors.
The MPC 106 latches the address and type of transaction that caused the error in the error
status registers to assist diagnostic and error handling software. See Section 3.2.5.4, "Error
Status Registers," for more information. Chapter 2, "Signal Descriptions," contains the
signal definitions for the interrupt signals.
Figure 9-1 provides the internal interrupt management block diagram.
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Chapter 9. Error Handling
9-1
Figure 9-1. Internal Interrupt Management Block Diagram
9.1 Priority of Externally-Generated Interrupts
Table 9-1 describes the relative priorities and recoverability of externally-generated
interrupts.
Table 9-1. Externally-Generated Interrupt Priorities
exception
cause
Proce88or
Recoverability
0
System reset
RRST or power-on reset (POR)
Nonrecoverable In all
cases
1
Machine check
(MCPorTEjl;)
Unsupported SOX bus transaction, Illegal L2 copy-back
operation, or Rash write error
Nonrecoverable In most
cases
2
Machine check
(MCP)
PCI address parity error (SEAR) or PCI data parity
error (FSERR) when the MPC106 is acting as the PCI
target
Nonrecoverable in most
cases
3
Machine check
(MCPorTEjl;)
Memory select error, memory data read parity error,
memory refresh overflow, L2 parity error, or ECC error
Nonrecoverable In most
cases
4
Machine check
(MCPorTEjl;)
PCI address parity error (SEAR) or PCI data parity
error (15EIm) when the MPC106 is acting as the PCI
master, PCI master-abort, or received PCI target-abort
Nonrecoverable in most
cases
5
Machine check
NMI (nonmaskable interrupt)
Nonrecoverable In most
cases
Priority
(MCP)
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Note that for priority 1 through 5, the exception is the same. The machine check exception
and the priority are related to additional error information provided by the MPC106 (for
example, the address provided in the 60xIPCI error address register).
9.2 Interrupt and Error Signals
Although Chapter 2, "Signal Descriptions," contains the signal definitions for the interrupt
and error signals, this section describes the interactions between system components when
an interrupt or error signal is asserted.
9.2.1 System Reset
The system reset interrupt is an asynchronous. nonmaskable interrupt that occurs at poweron reset (POR) or when the hard reset (HRST) input signal is asserted.
When a system reset request is recognized (HRST or POR), the MPC106 aborts all current
internal and external transactions, releases all bidirectional 110 signals to a high-impedance
state, ignores the input signals (except for SYSCLK, and the configuration signals DB GO,
FOE, RCSO, and PLL[0-3]), and drives most of the output signals to an inactive state.
(Table 2-2 shows the states of the output-only signals during system reset.) The MPCI06
then initializes its internal logic.
For proper initialization, the assertion of HRST must satisfy the minimum active pulse
width. The minimum active pulse width and other timing requirements for the MPC 106 are
given in the MPC106 hardware specifications.
During system reset, the latches dedicated to JTAG functions are not initialized. The IEEE
1149.1 standard prohibits the device reset from resetting the JTAG logic. The JTAG reset
(TRST) signal is used to reset the dedicated JTAG logic during POR.
9.2.2 60x Processor Bus Error Signals
The MPC106 provides two signals to the 60x processor bus for error reporting-MCP and
TEA.
9.2.2.1 Machine Check (MCP)
The MPC106 asserts MCP to signal to the 60x processor that a nonrecoverable error has
occurred during system operation. The assertion of MCP depends upon whether the error
handling registers of the MPC 106 are set to report the specific error.
Assertion of MCP causes the 60x processor to conditionally take a machine check
exception or enter the checkstop state based on the setting of the MSR[ME] bit in the 60x
processor. The programmable parameter PICRI [MCP_EN] is used to enable or disable the
assertion of MCP by the MPC 106.
The MCP signal may be asserted on any cycle. The current transaction mayor may not be
aborted depending upon the software configuration.
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Chapter 9. Error Handling
9-3
The MPCI06 holds MCP asserted until the 60x processor has taken the exception. The
MPCI06 decodes an interrupt acknowledge cycle by detecting 60x processor reads from
the two possible machine check exception addresses at OXOOOO_0200--0XOOOO_0207 and
0~0_0200-0x~0_0207.
The MCP signal can be configured, by programming PMCR2[SHARED_MCP], as an
output-only or as an open drain output signal. When configured for output-only, the
MPCI06 always drives the MCP signal. When configured for open drain output, the
MPCI06 drives the MCP signal only when signalling a detected error. Otherwise, the
MPCI06 releases MCP to a high-impedance state. The open drain configuration allows
other devices to signal MCP to the 60x processor without contention.
9.2.2.2 Transfer Error Acknowledge (TEA)
The MPCI06 asserts TEA to signal to the 60x processor that a nonrecoverable error has
occurred during data transfer on the 60x processor data bus. The assertion of TEA depends
upon whether the error handling registers of the MPCl 06 are set to report the specific error.
Assertion of TEA terminates the data transaction in progress; that is, it is not necessary to
assert TA because it will be ignored by the target processor. An unsupported transaction
causes the assertion of TEA (provided TEA is enabled). Unsupported transactions include:
•
A direct-store access
•
A graphics read or write (eciwx or ecowx)
•
A write to the PCI interrupt-acknowledge space (map A or map B)
•
A write to system ROM space, when Flash writes are disabled
•
An aborted processor-to-PCI transaction
The assertion of TEA causes the 60x processor to conditionally take a machine check
exception or enter the checkstop state based on the setting of the MSR[ME] bit in the 60x
processor.
The TEA signal may be asserted on any cycle that DBB is asserted. The assertion of TEA
terminates the data tenure immediately, even if in the middle of a burst. The MPC106
asserts TEA for only one clock. Note that the assertion of TEA does not prevent compt
data from being written into the cache or GPRs of the 60x processor.
The programmable parameter PICRl[TEA_EN] is used to enable or disable the assertion
of TEA by the MPCI06. If PICRl[TEA_EN] is programmed to disable the assertion of
TEA, and a 60x processor data transfer error occurs, then the MPC 106 asserts TA the
appropriate number of times to complete the transaction, but the data is unpredictable.
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9.2.3 PCI Bus Error Signals
The MPC106 uses three error signals to interact with the PCI bus-SERR, PERR, and
NMI.
9.2.3.1 System Error (SERR)
The SERR signal is used to report PCI address parity errors, PCI data parity errors on a
special-cycle command, target-abort, or any other errors where the result is potentially
catastrophic. The SERR signal is also asserted for master-abort, except if it happens for a
PCI configuration access or special-cycle transaction.
The agent responsible for driving AD[31-O] on a given PCI bus phase is responsible for
driving even parity one PCI clock later on the PAR signal. That is, the number of Is on
AD[31-O], CIBE[3-O], and PAR equals an even number.
The SERR signal is driven for a single PCI clock cycle by the agent that is reporting the
error. The target agent is not allowed to terminate with retry or disconnect if SERR is
activated due to an address parity error.
Bits 8 and 6 of the PCI command register control whether the MPC 106 asserts SERR upon
detecting one of the error conditions. Bit 14 of the PCI status register reports when the
MPC 106 has asserted the SERR signal.
9.2.3.2 Parity Error (PERR)
The PERR signal is used to report PCI data parity errors during all PCI transactions, except
for a PCI special-cycle command. The agent responsible for driving AD[31-O] on a given
PCI bus phase is responsible for driving even parity one PCI clock later orrthe PAR signal.
That is, the number of Is on AD[31-O], CIBE[3-O], and PAR equals an even number.
The PERR signal must be asserted by the agent receiving data two PCI clocks following
the data phase for which a data parity error was detected. Only the master may report a read
data parity error and only the selected target may report a write data parity error.
Bit 6 of the PCI command register controls whether the MPCI06 ignores PERR. Bit 15 and
bit 8 of the PCI status register are used to report when the MPC 106 has detected or reported
a data parity error.
9.2.3.3 Nonmaskable Interrupt (NMI)
The NMI signal is, effectively, a PCI sideband signal between the PCI-to-ISA bridge and
the MPC106. The NMI signal is driven by the PCI-to-ISA bridge to report any
nonrecoverable error detected on the ISA bus (normally, through the IOCRCK signal on
the ISA bus). The name nonmaskable interrupt is misleading due to its history in ISA bus
designs. The NMI signal should be connected to GND if it is not used. If PICR 1[MCP_EN]
is set, the MPC106 reports the NMI error to the 60x processor by asserting MCP.
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Chapter 9. Error Handling
9-5
9.3 Error Reporting
Error detection registers 1 and 2 (ErrDRI and ErrDR2) indicate which specific error has
been detected. Associated with these two registers, error enabling registers 1 and 2
(ErrEnRl and ErrEnR2) are used to enable the latching of the error flags and the
corresponding error information which results in the assertion of MCP or TEA, provided
they are enabled.
ErrDRI[3] (60xlPCI cycle) and ErrDR2[7] (invalid error address) together with the 60xl
PCI error address register, the 60x bus error status register, and the PCI bus error status
register are used to provide additional information about the detected error. When an error
is detected, the associated information is latched inside these registers until all the error
flags are cleared. Subsequent errors will set the appropriate error flags in the error detection
registers, but the bus error status and error address registers retain the information for the
initial error until all error flags are cleared.
9.3.1 60x Processor Interface
The 60x processor interface of the MPC 106 detects unsupported 60x bus transaction errors,
illegal L2 copy-back errors, and Flash write errors. In these cases, both ErrDRl[3] and
ErrDR2[7] are cleared, indicating that the error is due to a 60x bus transaction and the
address in the 60xIPCI error address register is valid. The MPCI06 asserts either TEA or
TA (depending on the value ofPICRl[TEA_END to terminate the data tenure.
9.3.1.1 Unsupported 60x Bus Transaction Error
When an unsupported 60x bus transaction error occurs, ErrDRl[1~] is set to reflect the
error type. Unsupported 60x bus transactions include XATS-initiated transactions, writes
to the PCI interrupt-acknowledge space (OxBFFF_FFFn using address map A or
OxFEFn_nnnn using address map B), and transactions with unsupported transfer attributes.
Unsupported transfer attributes include the illegal and reserved transfer types defined in
Section 4.3.2.1, ''Transfer Type Signal Encodings."
9.3.1.2 Illegal L2 Copy-Back Error
The MPC 106 does not support L2 cache copy-back operations to the PCI address space or
to the system ROM space. If the L2 attempts a copy-back operation to one of these address
spaces, ErrDR2[5] is set.
9.3.1.3 Flash Write Error
The MPC I 06 allows data bus width writes to the system ROM space when
PICRI [FLASH_WR_EN] is set and PICR2[FLASH_WR_LOCKOUT] is cleared.
Otherwise, any 60x processor write transaction to the system ROM space results in a Flash
write error. When a Flash write error occurs, ErrDR2[0] is set.
The MPCI06 accommodates only single-beat, data path sized (8- or 64-bit depending on
the configuration) writes to Flash memory. Software must partition larger data into
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individual data path sized (8- or 64-bit) write operations. Attempts to write to Flash with a
data size other than the full data path size will cause a Flash write error.
9.3.2 Memory Interface
The memory interface of the MPC 106 detects read parity, ECC, memory select, and refresh
overflow errors. The MPC106 detects parity errors on the data bus during DRAMIEDO
read cycles or during L2 cache read cycles. When ECC is enabled, the memory controller
can detect single-bit and multibit errors for system memory read transactions. Since the
ECC logic corrects single-bit errors, they are reported only when the number of errors in
the ECC single-bit error counter register equals the threshold value in the ECC single-bit
error trigger register. A memory select error occurs when the address for a system memory
transaction falls outside of the physical memory boundaries. A refresh overflow error
occurs when there is no refresh transaction within a period that is equivalent to 16 refresh
cycles.
In all cases, if the memory transaction was initiated by a PCI master, ErrDRl[3] i.s set; if
the memory transaction was initiated by the 60x processor, ErrDRl[3] is cleared.
ErrDR2[7] is cleared to indicate that the error address in the 60xlPCI error address register
is valid. If the ECC single-bit error trigger threshold is reached, then the error address will
indicate the address of the most recent ECC single-bit error. When a parity or ECC error
occurs on the last beat of a transaction and another transaction to the same page has started,
ErrDR2[7] is set to indicate that the error address in the 60xIPCI error address register is
not valid. Note that for L2 data parity errors and refresh overflow errors, the MPCI06
cannot provide the error address and the corresponding bus status. In these cases,
ErrDR2[7] is set to indicate that the error address in the 60xlPCI error address register is
not valid.
If the transaction is initiated by the 60x processor, or by a PCI master with bit 6 of the PCI
command register cleared, then the error status information is latched, but the transaction
continues and terminates normally.
9.3.2.1 System Memory Read Data Parity Error
When MCCRl[PCKEN] is set, the MPCI06 checks memory parity on every memory read
cycle and generates the parity on every memory write cycle that emanates from the
MPCI06. When a read parity error occurs, ErrDRl[2] is set.
The MPC 106 does not check parity for transactions in the system ROM address space. Note
that the processor should not check parity for system ROM space transactions as the parity
data will be incorrect for these accesses.
9.3.2.2 L2 Cache Read Data Parity Error
When ErrEnR2[4] and MCCRl[PCKEN] are set, the MPC106 checks L2 cache parity on
every L2 cache read cycle that is not in the system ROM address space. This allows ROMI
Flash data to be cached in the L2. See Section 6.5.1, "ROMlFlash Cacheability," for more
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Chapter 9. Error Handling
9-7
information. When an L2 cache read parity error occurs, ErrDR2[4] is set. Note that the
processor should not check parity for system ROM space transactions as the parity data will
be incorrect for these accesses.
9.3.2.3 System Memory ECC Error
When MCCR2[ECC_EN] is set, the MPCI06 performs an ECC check on every memory
read cycle and generates the ECC check data on every memory write cycle. When a singlebit ECC error occurs, the ECC single-bit error counter register is incremented by 1 and its
value is compared to the value in the ECC single-bit error trigger register. If the values are
equal, ErrDRl [2] is set. In addition to single-bit errors, the MPC106 detects all2-bit errors,
all errors within a nibble (one-half byte), and any other multibit error that does not alias to
either a single-bit error or no error. When a multibit ECC error occurs, ErrDR2[3] is set.
9.3.2.4 System Memory Select Error
A memory select error occurs when a system memory transaction address falls outside of
the physical memory boundaries. When a memory select error occurs, ErrDRl[5] is set.
If a write transaction causes the memory select error, the write data is simply ignored. If a
read transaction causes the memory select error, the MPC 106 returns OxFFFF_FFFF (all
Is). No RAS signals are asserted in either case.
9.3.2.5 System Memory Refresh Overflow Error
When there are no refresh transactions for a period equal to 16 refresh cycles, the MPC106
reports the error as a refresh overflow. When the MPC106 detects a refresh overflow,
ErrDRl[3] is set.
9.3.3 PCI Interface
The MPC 106 supports the error detection and reporting mechanism as specified in the pel
Local Bus Specification, Revision 2.1. The MPC106 keeps error information and sets the
appropriate error flags when a PCI error occurs (provided the corresponding enable bit is
set), independent of whether the PCI command register is programmed to respond to or
detect the specific error.
In cases of PCI errors, ErrDRl [3] is set to indicate that the error is due to a PCI transaction.
In most cases, ErrDR2[7] is cleared to indicate that the error address in the 6Ox/PCI error
address register is valid. In these cases, the error address is the address as seen by the PCI
bus, not the 60x bus address.
If NMI is asserted, the MPC 106 cannot provide the error address and the corresponding bus
error status. In such cases, ErrDR2[7] is set to indicate that the error address in the 6Ox/PCI
error address register is not valid.
9.3.3.1 Address Parity Error
If the MPC 106 is acting as a PCI master, and the target detects and reports (by asserting
SERR) a PCI address parity error, then the MPCI06 sets ErrDRl[7] and sets the detected
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MPC106 PCIBIMC User's Manual
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parity error bit (bit 15) in the PCI status register. This is independent of the settings in the
PCI command register. Note that for the MPC106 to recognize the assertion of SERR by
another PCI agent, bit 5 (RX_SERR_EN) of the alternate OS-visible parameter register 1
must be set.
If the MPC 106 is acting as a PCI target and detects a PCI address parity error, the PCI
interface of the MPC106 sets the status bit in the PCI status register (bit 15). If bits 8 and 6
of the PCI command register are set, the MPC106 reports the address parity error by
asserting SERR to the master (two clocks after the address phase) and sets bit 14 of the PCI
status register. Also, if PICRl[MCP_EN] is set, the MPC106 reports the error to the 60x
processor by asserting MCP.
9.3.3.2 Data Parity Error
If the MPC 106 is acting as a PCI master and a data parity error occurs, the MPC 106 sets
bit 15 of the PCI status register. This is independent of the settings in the PCI command
register.
If the PCI command register of the MPC 106 is programmed to respond to parity errors (bit
6 of the PCI command register is set) and a data parity error is detected or signaled during
a PCI bus transaction, the MPC106 sets the appropriate bits in the PCI status register (bit
15 is set, and possibly bit 8 is set, as described in the following paragraphs).
If a data parity error is detected by the MPC106 acting as the master (for example, during
a 60x processor-read-from-PCI transaction), and if bit 6 of the PCI command register is set,
the MPCI06 reports the error to the PCI target by asserting PERR and by setting bit 8 of
the status register and tries to complete the transaction, if possible. Also, if
PICRl[MCP_EN] is set, the MPC106 asserts MCP to report the error to the 60x processor.
These actions also occur if the MPC 106 is the master and detects the assertion of PERR by
the target (for a write).
If the MPC 106 is acting as a PCI target when the data parity error occurs (on a write), the
MPC106 asserts PERR, and sets ErrDRl[6] (PCI target PERR). If the data had been
transferred, the MPCI06 completes the operation but discards the data. Also, if
PICRl[MCP_EN] is set, the MPCI06 asserts MCP to report the error to the 60x processor.
In the case that PERR is asserted by the master during a memory read, the address of the
transfer will be logged in the error address register and MCP is optionally asserted.
9.3.3.3 Master-Abort Transaction Termination
lithe MPC106, acting as a master, initiates a PCI bus transaction (excluding special-cycle
and configuration transactions), but there is no response from any PCI agent (DEVSEL has
not been asserted within five PCI bus clocks from the start of the address phase), the
MPCI06 terminates the transaction with a master-abort and sets the master-abort flag
(bit 13) in the PCI status register.
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Chapter 9. Error Handling
9-9
If ErrEnRI [1] and PICRl[MCP_EN] are both set and the MPC106 terminates a transaction
with a master-abort, the MPC106 reports the error to the 60x processor by asserting MCP
and TEA.
9.3.3.4 Received Target-Abort Error
If a PCI transaction initiated by the MPC106 is terminated by target-abort, the received
target-abort flag (bit 12) of the PCI status register is set. If ErrEnRl[7] and
PICRl[MCP_EN] are both set and the MPC106 receives a target-abort, the MPC106
reports the error to the 60x processor by asserting MCP and TEA.
Note that any data transferred in a target-aborted transaction may be corrupt.
9.3.3.5 NMI (Nonmaskable Interrupt)
If PICRI [MCP_EN] is set and a PCI agent (typically the system interrupt controller) asserts
the NMI signal to the MPC 106, the MPC 106 reports the error to the 60x processor by
asserting MCP.
When the NMI signal is asserted, no error flags are set in the status registers of the MPC 106.
The agent that drives NMI should provide the error flag for the system and the mechanism
to reset that error flag. The NMI signal should then remain asserted until the error flag is
cleared.
9.4 Interrupt Latencies
Latencies for taking various interrupts are variable based on the state of the MPC 106 when
the conditions to produce an interrupt occur. The minimum latency is one cycle. In this
case, the interrupt is signaled in the cycle following the appearance of the interruptproducing conditions.
9.5 Example Signal Connections
This section provides two examples of connecting the interrupt signals between the 60x
processor, the MPC 106, and an interrupt controller on the PCI bus. TYpically the interrupt
controller is integrated into the PCI-to-ISA bridge. Figure 9-2 shows a PowerPC 603
microprocessor- or PowerPC 604 microprocessor-based system design. Figure 9-3 shows a
PowerPC 601 microprocessor-based system design.
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MPC106 PCIB/MC User's Manual
MOTOROLA
603/604
Power-{)n
reset
I
I
rnT
TEA
~
TEA
MCP
HAST
NMI
1"'-
WlI1 PERF! NMI
r---
MPC106
WlI1 PERF!
t t
Interrupt
controller
rnT
Figure 9-2. Example Interrupt Signal Configuration-603-1604-Based System
~JN
~_00i
601
i'EA
Power-{)n
reset
r--
rnT ~
HR"SI
MPC106
WiI1"Pmf
~
Interrupt
controller
NMI
~
~
~
NMI -
rnT -
~JN
~00i
~
Figure 9-3. Example Interrupt Signal Configuration-601-Based System
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Chapter 9. Error Handling
9-11
Appendix A
Power Management
The MPC 106 provides the system designer hardware resources to flexibly reduce system
power consumption through the use of software and system hardware power control
mechanisms. This appendix describes the hardware sUpPQrt provided by the MPC 106 for
power management.
A.1 MPC106 Power Modes
The MPC 106 implements four levels of power reduction-doze, nap, sleep, and suspend,
with power consumption reduced with each step from doze to suspend. The doze, nap, and
sleep modes are entered through software setting the required configuration register bit in
the power management configuration register (PMCR). For more information about this
register, see Section 3.2.4, "Power Management Configuration Registers (PMCRs)." The
suspend mode is entered by the assertion of the SUSPEND signal, as described in
Section 2.2.6.6, "Suspend (SUSPEND)-Input." All of the power management modes are
enabled by the configuration of the global power management bit, PMCR[PM].
A.1.1 MPC106 Power Mode Transition
While the doze, nap, and sleep modes are enabled by setting the corresponding bits in the
PMCR, in the case of the nap and sleep modes the power management mode is entered upon
the assertion of the QREQ signal. The MPCI06 responds by entering the power
management mode selected, and asserts QACK to signal to the processor that the power
management mode has been entered. The doze mode is entered directly by configuring the
doze bit in the PMCR, and does not require the assertion of QREQ.
The configuration of the MPCI06 and the processor signals asserted differ depending on
which processor (PowerPC 60 I microprocessor, PowerPC 603 microprocessor, or
PowerPC 604 microprocessor) the MPC 106 is connected to. The response of the MPC 106
is configured through the setting of the processor type bits in PICRl[PROC_TYPE].
MOTOROLA
Appendix A. Power Management
A-1
In a system designed using the 601, the MPCI06 can be configured to ignore the state of
the QREQ signal, and enters the nap or sleep mode directly upon the setting of the required
PMCR bits. This is controlled through PMCR[6OCNEED_QREQ1, which when cleared to
o allows the immediate invocation of the nap or sleep mode without assertion of QREQ,
and when set to 1 requires the assertion of QREQ by system power control logic to enter
the desired power management mode.
In systems designed using the 603, the power control signals QREQ and QACK are
connected to the corresponding signals on the MPC 106, and the doze, nap, or sleep mode
is entered following the configuration of the required bit in the PMCR, and the assertion of
QREQ (in nap and sleep modes) to the MPCI06 by the 603.
In systems designed using the 604, the MPC106's QREQ signal is connected to the 604's
HALT signal, and the MPCI06's QACK signal is connected to the 604's RUN signal, and
the doze, nap, or sleep mode is entered following the configuration of the required bit in the
PMCR, and the assertion of QREQ (in nap and sleep modes) to the MPC106 by the 604.
Configuring the processor type bits in PICRl[PROC_TYPE] for the 604 causes the signal
levels sampled and driven by the MPC106's QREQ and QACK signals to correspond to the
levels required by the 604's RUN and HALT signals.
FigureA-l shows the five power modes of the MPCI06, and the conditions required for
entering and exiting those modes .
••T1: PMCR[DOZE)) = 1 & PMCR[PM] =1
T2: hard reset, BRx = 0, PCI address hit, NMI
T3: PMCR[NAP]=1 & PMCR[PM] =1 &OREQ = 0 (or HALT = 1 in 604 system)
T4: hard reset, BRx = 0, PCI address hit, NMI
T5: PMCR[SLEEP] = 1 & PMCR[PM] = 1 & QREQ = 0 (or HALT = 1 in 604 system)
T6: hard reset,
= 0, NMI
T7: suspend = 0 & PMCR[PM] =1
Ta: suspend = 1
mrx
Figure A-1. MPC106 Power Modes
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MPC106 PCIBIMC User's Manual
MOTOROLA
The following sections provide a detailed description of the power modes of the MPC 106.
A.1.2 Full-On Mode
This is the default power mode of the MPC 106. In this mode, the MPC 106 is fully powered
and the internal functional units are operating at full clock speed.
A.1.3 Doze Mode
In this power management mode, all of the MPC106's functional units are disabled except
for PCI address decoding, system RAM refresh logic, processor bus request monitoring
(through BRO and BRl), and NMI signal monitoring. Once the doze power management
mode is entered, a hard reset, a PCI transaction referenced to the system memory, a bus
request from BRO or BRl, or assertion ofNMI (with PICRl[MCP_EN] set to 1) brings the
MPC106 out of the doze mode and into the full-on mode.
After the system request has been serviced, the system returns to the doze mode if neither
PMCR[DOZE] nor the PMCR[PM] has been cleared and there are no further pending
service requests.
In doze mode, the PLL is required to be running and locked to SYSCLK. The transition to
the full-on mode will take no more than a few processor cycles. The MPCI06's doze mode
is totally independent of the power saving mode of the CPU.
A.1.4 Nap Mode
Additional power savings can be achieved through the nap mode. When invoking the
MPC 106's nap mode, both the MPC 106 and the processor should be programmed to enable
the nap mode. The processor may also be programmed to enter sleep mode while the
MPC 106 enters nap mode.
As in doze mode, all the MPC 106's functional units are disabled except for the PCI address
decoding, system RAM refresh logic, processor bus request monitoring (through BRO and
BRl), and NMI signal monitoring. Once the nap mode is entered, a hard reset, a PCI
transaction referenced to the system memory, a bus request from BRO, a bus request from
BRI (in a multiprocessor system with PMCR[BRCWAKE] set to 1), or an asserted NMI
(PICRl[MCP_EN] set to 1) will bring the MPCI06 out of the nap mode.
In nap mode, the PLL is required to be running and locked to SYSCLK. The transition to
the full-on mode will take no more than a few processor cycles.
When the MPC106 is awakened by an access other than a PCI bus-initiated transaction, the
transaction will be serviced and PMCR[PM] will be cleared. This means that the MPC106
will not automatically re-enter the nap mode. For PCI bus-initiated transactions,
PMCR[PM] will not be cleared, and the MPC106 will return to nap mode after the
transaction has been serviced.
MOTOROLA
Appendix A. Power Management
A-3
While the MPC106 is servicing a PCI bus transaction in systems using a 603, if the 603 is
still in a power management mode the 603 will not respond to any snoop cycles. Software
should therefore flush the 603's L1 cache before allowing the system to enter the nap mode
if the system allows a PCI bus access to wake up the MPC 106. However, in systems using
the 604, the 604 can be forced to respond to a snoop cycle if the RUN signal (connected to
the QACK signal from the MPC106) is asserted. This response by the 604 is enabled by
clearing PMCR[NO_604_RUN] to O. If the MPCI06 is configured to allow snoop
responses by the 604, there is no need to flush the L1 cache before the 604 enters the nap
mode.
Before entering the nap mode, QREQ from 603 or HALT from 604 will be sampled active
by the MPC106, which will then respond with a QACK signal when it is ready to nap,
thereby allowing the processor to enter either the nap or sleep mode.
A.1.S Sleep Mode
Sleep mode provides additional power savings when compared to nap mode. As in nap
mode, both MPCI06 and the processor should be configured to enable the sleep mode
(although the processor may optionally be configured for nap mode while the MPC106 is
in sleep mode). While the MPC106 is in sleep mode, no functional units are operating
except the system RAM refresh logic (optional), processor bus request monitoring (through
BRO or BRI), and NMI signal monitoring. A hard reset, a bus request from BRO, a bus
request from BRI (in a multiprocessor system with PMCR[BRCWAKE] set to I),or
assertion ofNMI (with PICRI[MCP_EN] set to 1) will wake the MPCI06 from the sleep
mode. The PMCR[PM] bit will always be cleared after the MPC106 is awakened from the
sleep mode.
-
The PLL and SYSCLK input may be disabled by an external power management controller
(PMC) for additional power savings. The PLL can be disabled by setting the
PLL_CFG[0-3] signals in the PLL bypass mode. When recovering from sleep mode, the
external PMC has to re-enable the PLL and SYSCLK first, and then wake up the system
after 100 microseconds of PLL relock time.
In sleep mode, the system can retain the system memory content through the use of three
different methods. The first method is the normal CBR refresh which is supported by every
system. The second method is to enable the self-refresh mode of the system memory. This
can be supported only if the system memory is capable of supporting the self-refresh mode.
The third method is supported by the operating system by copying allthesystem memory
data to a hard disk. In this case, there is no need to continue the memory refresh operation.
The programming options for the three memory retention methods are defined by the
configuration of PMCR[LP_REF_EN] and MCCR8[SREN]. If the LP_REF_EN bit is
cleared to 0, there will be no memory refresh operation when the MPCI06 is in the sleep
or suspend mode. If PMCR[LP_REF_EN] is set to 1, memory refresh will be carried out
even when the MPCI06 is in a low-power mode. In this case, MCCR8[SREN] is used to
A-4
MPC106 PCIBIMC User's Manual
MOTOROLA
determine whether the refresh is a self refresh (MCCR8[SREN] set to 1) or a CBR refresh
(MCCR8[SREN] cleared to 0).
When the MPC106 is in the sleep mode using CBR refresh and keeping the PLL in locked
operation, the wake up latency should be comparable to nap mode. However, additional
wake up latency will be needed if the system uses the self-refresh mode and/or turns off the
PLL during sleep mode operation.
Before entering the sleep mode, QREQ from 603 or HALT from 604 should be sampled
active. The MPC 106 will then respond with a QACK signal when it is ready to enter the
sleep mode, thereby allowing the processor to enter into either the nap or sleep mode.
Turning off the PLL and/or external clock during sleep mode requires waiting until the
assertion of the QACK signal. The external PMC chip should trap all the wake up events so
that it can tum on the PLL (observing the recommended PLL relock time) and/or the
external clock source before forwarding the wake up event to the MPC106.
A.1.6 Suspend Mode
Suspend mode provides the greatest reduction of power consumption. It is activated
through the assertion of the SUSPEND signal, which is driven by an external 110 device (in
most cases an external (system level) power management controller). In suspend mode, no
functional units are operating except the system RAM refresh logic (optional) and the
internal logic monitoring the SUSPEND signal. The MPC106 will remain in the suspend
mode until the SUSPEND signal is negated.
The PLL and SYSCLK input may be disabled by an external power management controller
(PMC) for additional power savings. The PLL can be disabled by setting the
PLL_CFG[0-3] pins into the PLL bypass mode. When recovering from suspend mode, the
external PMC has to re-enable the PLL and SYSCLK first, and then wake up the system
after the PLL has had time to relock (100 Jls).
In suspend mode, the system can retain the contents of system memory through the use of
three different methods. The first method is the low-frequency refresh (RTC refresh) which
can be supplied very easily by most systems. A low-frequency clock signal is supplied by
the system to the real time clock (RTC) input of the MPCI06. Note that RTC refresh is not
supported for SDRAM configurations. However, JEDEC-compliant SDRAM devices
allow self-refresh, which consumes less power than RTC refresh. The second method is to
enable the self-refresh mode of the system memory. This can be supported only if the
system memory is capable of supporting the self-refresh mode. The third method is
supported by the operating system by copying all the system memory data to the hard disk.
In this case, there is no need to continue the memory refresh operation.
The programming options for the three memory retention methods is defined by the
configuration of PMCR[LP_REF_EN] and MCCR8[SREN]. If PMCR[LP_REF_EN] is
cleared to 0, there will be no memory refresh operation when the MPC 106 is in suspend
MOTOROLA
Appendix A. Power Management
A-5
mode. If PMCR[LP_REF_EN] is set to 1, memory refresh will be carried out even when
the MPC 106 is in suspend mode.
In this case, MCCR8[SREN] will be used to determine whether the refresh is a self refresh
(MCCR8[SREN] set to 1) or a low-frequency refresh (MCCR8[SREN] cleared to 0). Note
that if the memory system is configured for EDO, it will be treated as no refresh required,
and no low-frequency refresh is supported.
In suspend mode, all bidirectional and output signals (except the memory refresh-related
signals if RTC refresh is being used) will be at high impedance and all input signals, with
the exception of HRST and the PLL configuration signals, will be ignored.
After the assertion of the SUSPEND signal, the system should not tum off the PLL and/or
the external clock source for at least 60 microseconds (two RTC clock periods). Before the
de-assertion of the SUSPEND signal, the system should allow sufficient time for the PLL
to stabilize.
A.2 MPC106 Power Management Support
The MPCI06 provides hardware for the support of power management activities that is
accessible to software and external system-level power management controllers. The fully
static design allows internal logic states to be preserved during all power saving operations.
System software is expected to handle the majority of power management tasks through
access to the PMCR. The following sections provide a description of the power
management features and capabilities provided by the MPCI06.
A.2.1 Power Management Configuration Registers
-
The PMCRs provide software access to the power management modes, enables, and
configurations for different processors. Refer to Section 3.2.4, "Power Management
Configuration Registers (PMCRs)," for a detailed description of the PMCR.
A.2.2 Clock Configuration
In doze and nap modes, the PLL must be running ~d locked to SYSCLK in order to
provide clocks to the internal logic units that need to be awake, and to minimize the
transition time required in coming out of a power saving mode to the full-on mode. The
power mode transition occurs with the assumption that the PLL is locked with SYSCLK.
The electrical characteristics of the SYSCLK signal and the PLL configuration should
remain the same whether the MPC106 is in the full-on mode, or in doze or nap mode. In
sleep or suspend mode, the external PMC (if it exists) may disable the PLL and the
SYSCLK input for further power savings. However, it is the external PMC's responsibility
to guarantee that there is sufficient relock time for the PLL of the MPC 106 before MPC 106
is awakened by any event. Doze and nap modes are intended to be used dynamically due to
their fast recovery time; sleep and suspend modes are intended for longer periods of power
savings with the PLL and SYSCLK off.
A-6
MPC106 PCIBIMC User's Manual
MOTOROLA
A.2.3 PCI Address Bus Decoding
PCI address bus decoding is enabled while the MPC 106 is in the doze or nap mode. A PCI
transaction to system memory awakens the MPC 106 from the doze or nap power saving
mode.
After servicing the PCI transaction, the MPC 106 returns to the previous power saving mode
(doze or nap) if there are no additional PCI bus service requests. In systems using a 603,
the L1 cache should be flushed prior to entering the nap mode. Systems designed using the
601 or 604 are not required to flush their Ll caches prior to entering the nap mode.
A.2.4 PCI Bus Special-Cycle Operations
Before the MPC106 enters the nap or sleep mode, it will broadcast the halt or shutdown
message over the PCI bus by means of special bus' cycle. See Section 7.4.6.2,
"Special-Cycle Transactions," for a description of PCI special-cycle operations.
In nap mode, if PMCR[NO_NAP_MSG] is cleared to 0, the MPC106 broadcasts the halt
message over the PCI bus. If PMCR[NO_NAP_MSG] is set to 1, the MPC106 does not
broadcast any message to the PCI bus.
In sleep mode, if PMCR[NO_SLEEP_MSG] is cleared to 0, the MPC 106 broadcasts either
the halt or shutdown message over the PCI bus depending on whether
PMCR[SLEEP_MSG_TYPE] is cleared or set. If PMCR[NO_SLEEP_MSG] is set to 1,
the MPC 106 does not broadcast any message to the PCI bus and the configuration of
PMCR[SLEEP_MSG_TYPE] is ignored.
A.2.5 Processor Bus Request Monitoring
In doze, nap, and sleep modes, the MPC 106 monitors the BRO signal. When BRO is
asserted, (for example, due to the processor's time base interrupt service routine), the
MPC106 exits its power saving mode and returns to the full-on mode to service the request.
Additionally, in a multiprocessor system, BR[1-3] can be used to awaken the MPC106. In
nap or sleep mode, the assertion of BR1, BR2, or BR3 is treated as a wake up event if
PMCR[BR1_WAKE] is set to 1. In doze mode, it is unconditional, and does not depend
upon the condition of the bit in PMCR[BRCWAKE].
A.2.6 Memory Refresh Operations in Sleep/Suspend Mode
In sleep or suspend mode, all functional units, including the system memory refresh logic,
will not be operating. The system memory contents can be maintained either by enabling
the memory's self-refresh mode or by having the system software copy all the memory
contents to a hard disk before the MPC106 enters the sleep or suspend mode. However, if
the memory does not have self-refresh capability or the system software has not copied the
memory contents to the hard disk, the refresh logic of the MPC 106 can continue to operate
even if in sleep or suspend mode. This is configured through PMCR[LP_REF_EN], which
when set to 1 allows the refresh logic to continue to perform refresh cycles for system
MOTOROLA
Appendix A. Power Management
A-7
memory when the MPC106 is in the sleep or suspend mode. If PMCR[LP_REF_EN] is
cleared to 0, memory refresh operations will cease when the MPC106 enters the sleep or
suspend mode. For additional detail on memory refresh operations, refer to
Section 6.3.10.2, "DRAMIEDO Refresh and Power Saving Modes."
A.2.7 Device Drivers
Since operating systems service I/O requests by system calls to the device drivers, the
device drivers must be modified for power management. When a device driver is called to
reduce the power of a device, it needs to be able to check the power mode of the device,
save the device configuration parameters, and put the device into a power saving mode.
Furthermore, every time the device driver is called it needs to check the power status of the
device, and if the device is in a power saving mode, restore the device to the full-on mode.
A-8
MPC106 PCIBIMC User's Manual
MOTOROLA
Appendix B
Bit and Byte Ordering
The MPC106 supports both big-endian and little-endian formatted data on the PCI bus.
This appendix provides examples of the big- and little-endian modes of operation.
PICR1[LE_MODE] controls the endian mode of the MPC106. LE_MODE is also
accessible from the external configuration register at port Ox092. Note that the 60x
processor and the MPC 106 should be set for the same endian mode before accessing the
devices on PCI bus.
When designing little-endian or big-endian systems using the MPC106, system designers
and programmers must consider the following:
•
The PCI bus uses a little-:-endian bit format (the most-significant bit (msb) is 31),
while the 60x bus uses a big-endian bit format (the most-significant bit is 0). Thus,
PCI address bit AD31 equates to the 60x address bit AO, while PCI address bit ADO
equates to the 60x address bit A31.
•
For data comprised of more than 1 byte, the endian mode affects the byte ordering.
For little-endian data, the least-significant byte (LSB) is stored at the lowest (or
starting) address while the most-significant byte is stored at the highest (or ending)
address. For big-endian data, the most-significant byte is stored at the lowest (or
starting) address while the least-significant byte is stored at the highest (or ending)
address.
•
For 60x processors, the conversion to little-endian mode does not occur on the data
bus. The bus interface unit (BIU) of the 60x processor uses a technique called
munging to reverse the address order of every 8 bytes stored to memory. See Chapter
3, "Operand Conventions" in PowerPC Microprocessor Family: The Programming
Environments, for more information. External to the processor, all the byte lanes
must be reversed (MSB to LSB, etc.) and the addresses must be unmunged. The
unmungiQglbyte lane reversing mechanism can either be between the processor and
system memory or between the PCI bus and system memory. The MPC 106
unmunges the address and reverses the byte lanes between the PCI bus and system
memory.
MOTOROLA
Appendix B. Bit and Byte Ordering
B-1
-
B.1 Big-Endian Mode
When the 60x processor is operating in big-endian mode, no address modification is
performed by the processor. In big-endian mode, the MPC106 maintains the big-endian
byte ordering on the PC! bus during the data phase(s) of PC! transactions. The byte lane
translation for big-endian mode is shown in Table B-1. Note that the bit ordering on the PC!
bus remains little-endian.
Table B-1. Byte Lane Translation in Big-Endian Mode
&Ox Byte Lane
60x Data Bus Signals
PCI Byte Lane
PCI AddresalData Bus
Signals During PCI Data
Phase
0
DH[Q-7]
0
AD[7-o)
1
DH[8-15)
1
AD[15-8)
2
DH[16-23)
2
AD[23-16)
3
DH[24-31)
3
AD[31-24)
4
DL[Q-7]
0
AD[7-o)
5
DL[8-15)
1
AD[15-8)
6
DL[16-23)
2
AD[23-16)
7
DL[24-31)
3
AD[31-24)
8·2
MPC106 PCIBIMC User's Manual
MOTOROLA
Figure B-1 shows a 4-byte write to PCI memory space in big-endian mode.
60x
j
°
1
2
3
A[28-31]
°°°°
, - - - - - - , I
4
1 00 1 01 1 02 1 03 1 xx
5
6
7
Byte lanes
xx
xx
xx 1 60x data bus
!
MPC106
Runs PCI memory transaction
AO[3--31]
Munge Address
XORwith 100
~
I
~
I
0
0000
2
I
A[28-31]
3
4
5
6
7
Byte lanes
r-I0-00-10-1"-,-02""T'"1-03-'-,-xx---rlxx---'lrxx---'--1xx--'I 60x data bus
~
MPC106
Unmunges address
Swaps byte lanes
Runs PCI 1/0 transaction
AO[3--0]
Ouring Address Phase
0100
3
2
o
PCI byte lanes ('C7SE[3--0] asserted)
1 00 1 01 1 02 1 031 PCI data bus (AO[31-O] during data phase)
~
M:M
PCI 110 Space
Figure B-11. Four-Byte Transfer to PCI VO Space-Little-End ian Mode
8-14
MPC106 PCIB/MC User's Manual
MOTOROLA
Appendix C
JTAGITesting Support
The MPCl 06 provides a joint test action group (JTAG) interface to facilitate boundary-scan
testing. The JTAG interface implements the five test port signals required to be fully
compliant with the IEEE 1149.1 specification. For additional information about JTAG
operations, refer to the IEEE 1149.1 boundary-scan specification.
C.1 JTAG Interface Description
The JTAG interface consists of a set of five signals, three JTAG registers, and a test access
port (TAP) controller, described in the following sections. A block diagram of the JTAG
interface is shown in Figure C-l.
~I
..
Figure C-1. JTAG Interface Block Diagram
MOTOROLA
Appendix C. JTAGlTesting Support
C-1
C.1.1 JTAG Signals
The MPC 106 provides five dedicated JTAG signals-test data input (IDI), test mode select
(TMS), test reset (TRST), test clock (TCK), and test data output (IDO). The TDI and IDO
signals are used to input and output instructions and data to the JTAG scan registers. The
boundary-scan operations are controlled by the TAP controller through commands received
by means of the TMS signal. Boundary-scan data is latched by the TAP controller on the
rising edge of the TCK signal. The TRST signal is specified as optional by the IEEE 1149.1
specification, and is used to reset the TAP controller asynchronously. The assertion of the
TRST signal at power-on reset assures that the ITAG logic does not interfere with the
normal operation of the MPC 106.
Section 2.2.7, "IEEE 1149.1 Interface Signals," provides additional detail about the
operation of these signals.
C.1.2 JTAG Registers and Scan Chains
The bypass, boundary-scan, and instruction ITAG registers and their associated scan chains
are implemented by the MPCI06. These registers are mandatory for compliance with the
IEEE 1149.1 specification.
C.1.2.1 Bypass Register
The bypass register is a single-stage register used to bypass the boundary-scan latches of
the MPC106 during board-level boundary-scan operations involving components other
than the MPC106. The use of the bypass register reduces the total scan string size of the
boundary-scan test.
C.1.2.2 Boundary-Scan Registers
The ITAG interface provides a chain of registers dedicated to boundary-scan operations. To
be ITAG-compliant, these registers cannot be shared with any functional registers of the
MPC106. The boundary-scan register chain includes registers controlling the direction of
the input/output drivers, in addition to the registers reflecting the signal value received or
driven.
-
The boundary-scan registers capture the input or output state of the MPC106's signals
during a Capture_DR TAP controller state. When a data scan is initiated following the
Capture_DR state, the sampled values are shifted out through the IDO output while new
boundary-scan register values are shifted in through the IDI input. At the end of the data
scan operation, the boundary-scan registers are updated with the new values during an
Update_DR TAP controller state.
Note that the LSSD_MODE signal (used for factory testing) is not included in the
boundary-scan register chain.
C-2
MPC106 PCIB/MC User's Manual
MOTOROLA
C.1.2.3 Instruction Register
The 8-bit JTAG instruction register serves as an instruction and status register. As TAP
controller instructions are scanned in through the TOI input, the TAP controller status bits
are scanned out through the TDO output.
C.1.3 TAP Controller
The MPC 106 provides a standard JTAG TAP controller that controls instruction and data
scan operations. The TMS signal controls the state transitions of the TAP controller.
MOTOROLA
Appendix C. JTAGfTesting Support
C-3
Appendix D
Initialization Example
This appendix contains an example PowerPC assembly language initialization routine for
an MPC 106-based system using address map A.
i#*****************
Contains MPC106 initialization
***********************
#include "./asmPowerPC.h"
#include ". /asmppc .h"
.toc
T .. main:
.tc
.. main[tcj, main [dsj
.globl main [dsj
.csect main[dsj
.main[prj, TOC[tcOj, 0
. long
.globl . main [prj
.csect . main [prj
. align 4
;#=====================================================================================
;#
;#
;# Register usage:
;#
;#
;#
;#
;#
;#
rO is continually loaded with masking patterns
rl
Ox 8000 Ocf8 CONFIG_ADDR
r2 = Ox 8000 Ocfc CONFIG_DATA
r3 is used to define which register number is to be stored at CONFIG_ADDR
r4 is used for loading and storing data to/from CONFIG_DATA
;#
..
;#=====================================================================================
i#********************************CYFS****************** *******************************
#define WHICHDRAM initmdc2pdram
;#define WHICHDRAM initmdc2edo
i'********************************END CYFS*********************************************
.main:
lis
ori
ori
rO, MPC106_REG
rl, rO, OxOcf8
r2, rO, OxOcfc
# rO = Ox 8000 0000 BASE_ADDRESS
# rl
Ox 8000 Ocf8 CONFIG_ADDR
# r2 = Ox 8000 Ocfc CONFIG_DATA
;#
MOTOROLA
Appendix
o. Initialization Example
0-1
i#
-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
;1I
;1I
;1I
This small section of code speeds up accesses to the Boot ROM, but
is written SPECIFICALLY FOR VERY FAST ROM or SRAM.
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MCCR1
r3, 0, r1
1I start building new register number
1I write this value to CONFIG_ADDR
lwbrx
lis
ori
and
or
stwbrx
r4,
rO,
rO,
r4,
r4,
r4,
1I
1I
II
1I
1I
1I
1I register number OxfO
;1I
0, r2
OxOO16
rO, Ox5555
r4, rO
r4, rO
0, r2
load r4 from CONFIG_DATA
REDUCE WAIT STATES FOR ROM ACCESSES
(contains no reserved bits)
clears the desired bits
sets the desired bits
write the modified data to CONFIG_DATA
;1I
;1I
End of Boot ROM speed-up.
i#
-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
;#
;# This section of code initializes the MPC106's PCI Interface Registers
;#
initpci:
;1I
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, PCI_CMD
r3, 0, r1
# register number OxOO04
lhbrx
lis
ori
or
sthbrx
r4,
rO,
rO,
r4,
r4,
1I load r4 from CONFIG_DATA
1I
1I
1I sets the desired bits
II write the modified data to CONFIG_DATA
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, PCI_STAT
r3, 0, r1
# start building new register number
II register number OxOO06
1I write this value to CONFIG_ADDR
li
lhbrx
ori
sthbrx
r3,
r4,
r4,
r4,
# load r4 from CONFIG_DATA
1I Writing all ones will clear all bits in PCI_STAT
1I write the modified data to CONFIG_DATA
# start building new register number
II write this value to CONFIG_ADDR
0, r2
OxOOOO
rO, Ox0106
r4, rO
0, r2
;1I
-
OxOO02
r3, r2
r4, Oxffff
r3, r2
;#
;1I=====================================================================================
;1I
;1I This section of code initializes the MPC106's Processor Interface Registers
;# for use with the PDC4 (single 603/604 and 512 kB of pipeline
;# or flowthrough L2) at 60 - 66 MHz.
;#
initproc:
0-2
MPC106 PCIB/MC User's Manual
MOTOROLA
;#
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, PICR2
r3, 0, r1
# start building new register number
# register number Oxac
# write this value to CONFIG_ADDR
lwbrx
r4, 0, r2
# load r4 from CONFIG_DATA
lis
ori
and
rO, Ox2800
rO, rO, Ox0800
r4, r4, rO
# Reserved bits are 29, 27, and 11
# bit 31 is MSb, bit
is LSb
# clears all Oxac reg except reserved bits
;#
;#
lis
lis
lis
rO, Ox800f
rO, Ox814f
rO, Ox804f
#flow through type
#pipelined type, fast 12 mode
jlpipelined type, slow 12 mode
;#
;#
;#
ori
ori
ori
°
rO, rO, Ox068e
rO, rO, Ox068f
rO, rO, Ox06ge
ori
rO, rO, Ox0296
or
stwbrx
r4, r4, rO
r4, 0, r2
U bank 256 k
#1 bank 256 k with adsp mode on
#2 banks 512 k, fast castout, aphase
3 wait
#hit delay =3
#2 banks 512 k, fast castout, aphase
1 wait
#hit delay=l
# sets the desired bits
# write value to CONFIG_DATA
;# These next five lines may not be necessary if the above OR pattern = Ox c2ge 650e
lwbrx
r4, 0, r2
lis
rO, Ox4000
# Now that we've written to the Ox ac register,
ori
rO, rO, Ox4000
# keep pattern the same, but set the L2_EN bit (see next reg)
r4, r4, rO
# by setting bit 30 to a 1
or
r4, 0, r2
# write value to CONFIG_DATA
stwbrx
;#
r3, MPC106_REG
# start building new register number
lis
r3, r3, PICR1
# register number Oxa8
ori
r3, 0, r1
stwbrx
# write this value to CONFIG_ADDR
r4, 0, r2
# load r4 from CONFIG_DATA
lwbrx
;#
;#
lis
ori
and
lis
lis
ori
ori
or
stwbrx
MOTOROLA
rO, OxOOOO
rO, rO, Ox4000
r4, r4, rO
rO, Ox3f75
rO, 0x3f37
rO, rO, Ox0498
rO, rO, Ox0698
r4, r4, rO
r4, 0, r2
# bit 14 is reserved bit
# bit 31 is MSb
# clears all Oxa8 reg bits except reserved bits
#603 in drtry mode
#604 type processor
# LEAVE THE L2 CACHE OFF
# LEAVE THE L2 CACHE OFF but turn on dpark
# sets the desired bits
# write value to CONFIG_DATA
Appendix D. Initialization Example
0-3
..
i#
lis
ori
stwbrx
r3, MPC106_ROO
r3, r3, ALT_OSV_l
r3, 0, rl
lbz
lis
or
stb
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPC106_ROO
r3, r3, ALT_OSV_2
r3, 0, rl
# start building new register number
# register number Oxbb
# write this value to CONFIG_ADDR
lbz
lis
ori
or
stb
r4,
rO,
rO,
r4,
r4,
# load r4 from CONFIG_DATA
#
#
# sets the desired bits
# write the modified data to CONFIG_DATA
ori
2(r2)
OxOOOO
rO, Ox0026
r4, rO
2(r2)
# start building new register number
# register number Oxba
# write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
#
#
# sets the desired bits
# write the modified data to CONFIG_DATA
i#
3 (r2)
OxOOOO
rO, OxOOOO
r4, rO
3(r2)
i#==================================================== =================================
i#
i# This section of code initializes the MPC106's memory configuration registers
i# for use with the MDC2 (64 MB PDRAM/EDO and 2 MB SRAM BootROM) at 60 - 66 MHz.
ill
i#
i#
This will branch to either initmdc2pdram for page mode type dram or
it will branch to initmdc2edo for edo dram
WHICHDRAM
b
i#
i#************************Normal page mode DRAM initialization****************
initmdc2pdram:
i#
..
lis
ori
stwbrx
r3, MPC106_ROO
r3, r3, MCCRl
r3, 0, rl
# start building new register number
# register number OxfO
# write this value to CONFIG_ADDR
lwbrx
lis
ori
and
or
stwbrx
r4,
rO,
rO,
r4,
r4,
r4,
#
#
#
#
#
#
lis
r3, MPC106_ROO
i#
0, r2
OxOO16
rO, Ox5555
r4, rO
r4, rO
0, r2
load r4 from CONFIG_DATA
REDUCE WAIT STATES FOR ROM ACCESSES
(contains no reserved bits)
clears the desired bits
sets the desired bits
write the modified data to CONFIG_DATA
i#
0-4
# start building new register number
MPC106 PCIB/MC User's Manual
MOTOROLA
ori
stwbrx
r3, r3, MCCR2
r3, 0, r1
lwbrx
lis
ori
r4, 0, r2
rO, OxOOOO
rO, rO, OxOc34
and
or
stwbrx
r4, r4, rO
r4, r4, rO
r4, 0, r2
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MCCR3
r3, 0, r1
lwbrx
lis
ori
and
or
stwbrx
r4,
rO,
rO,
r4,
r4,
r4,
0, r2
Ox0002
rO, Oxa294
r4, rO
r4, rO
0, r2
lis
ori
stwbrx
lwbrx
r3,
r3,
r3,
r4,
MPC106_REG
r3, MCCR4
0, r1
0, r2
lis
ori
and
lis
lis
ori
or
stwbrx
rO, Oxffef
rO, rO, Oxffff
r4, r4, rO
rO, OxOOOO
rO, Ox0010
rO, rO, OxOOOO
r4, r4, rO
r4, 0, r2
# register number Oxf4
# write this value to CONFIG_ADDR
#
#
#
;#
#
#
#
load r4 from CONFIG_DATA
Self-Refresh value (not used for MDC2 or MDC3)
Ox30d (decimal 781) clocks between refresh, BUF=E/E
781 clocks for 50 MHz, 1041 for 66.6 MHz
clears the desired bits
sets the desired bits
write the modified data to CONFIG_DATA
;#
;#
;#
;#
;#
;#
;#
lis
ori
and
or
stwbrx
rO,
rO,
r4,
r4,
r4,
# start building new register number
# register number Oxf8
# write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
# RAS6P=0101, CAS5=010, CP4=001,
# CAS3= 010, RCD2=010, RP1=100
# clears the desired bits
# sets the desired bits
# write the modified data to CONFIG_DATA
# start building new register number
# register number Oxfc
# write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
# all BUT bit 20 are reserved!!!
# bit 31 is MSb
# clears all Oxfc reg bits except reserved bits
# set RCBUF=O for flow thru data buffers
# set RCBUF=l for clocked/latched data buffers
#
# sets the desired bits
# write value to CONFIG_DATA
OxOOOO
rO, OxOOOO
r4, rO
r4, rO
0, r2
# set RCBUF=O for flow thru data buffers
#
# clears the desired bits
..
# sets the desired bits
# write the modified data to CONFIG_DATA
;#
;#
;# For MDC2, 64MB total of PAGE MODE DRAM
;#
;# BankO
;# Bankl
;# Bank2
Ox 0000 0000 - Ox 007f ffff
Ox 0080 0000 - Ox DOff ffff
Ox 0100 0000 - Ox 017f ffff
MOTOROLA
Appendix O. Initialization Example
0-5
;# Bank3
;lI Bank4
;# BankS
;# Bank6
;# Bank7
Ox
Ox
Ox
Ox
Ox
0180
0200
0280
0300
0380
0000
0000
0000
0000
0000
-
Ox
Ox
Ox
Ox
Ox
01£f
027f
02££
037f
03ff
ffff
ffff
ffff
ffff
ffff
;11
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MEl'CSTA_03
r3, 0, r1
# start building new register number
# register number Ox80
# write this value to CONFIG_ADDR
lis
ori
stwbrx
r4, Ox1810
r4, r4, Ox0800
r4, 0, r2
# Each bank on MIX:2 is 8MB
# (no reserved bits)
# write the modified data to CONFIG_DATA
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MEl-CSTA_47
r3, 0, r1
# register number Ox84
# write this value to CONFIG_ADDR
lis
ori
stwbrx
r4, Ox3830
r4, r4, 0x2820
r4, 0, r2
II Each bank on MIX:2 is 8MB
# (no reserved bits)
# write the modified data to CONFIGJ)ATA
lis
ori
stwbrx
r3, MPC106_REG
# start building new register number
r3, r3, EXT_MEM3TA_03 # register number Ox88
# write this value to CONFIG_ADDR
r3, 0, r1
lwbrx
lis
ori
and
stwbrx
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPC106_REG
II start building new register number
r3, r3, EXT_MEM_STA_47 II register number Ox8c
r3, 0, r1
# write this value to CONFIG_ADDR
lwbrx
lis
ori
and
stwbrx
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MEM_END_03
r3, 0, r1
# register number Ox90
# write this value to CONFIG_ADDR
lis
r4, Ox1f17
# Each bank on MIX:2 is 8MB
;#
II start building new register number
;lI
0, r2
Oxfcfc
rO, Oxfcfc
r4, rO
0, r2
#
#
#
#
#
load r4 from CONFIGJ)ATA
Each bank on MIX:2 is 8MB
clears all non-reserved bits
write the modified data to CONFIG_DATA
;#
-
0, r2
Oxfcfc
rO, Oxfcfc
r4, rO
0, r2
# load r4 from CONFIG_DATA
# Each bank on MIX:2 is 8MB
II
# clears all non-reserved bits
II write the modified data to CONFIG_DATA
;#
0-6
II start building new register number
MPC106 PCIB/MC User's Manual
MOTOROLA
ori
stwbrx
r4, r4, OxOf07
r4, 0, r2
lis
ori
stwbrx
r3, MPClO6_Rm
r3, r3, MEICEND_47
r3, 0, rl
lis
ori
stwbrx
r4, Ox3f37
r4, r4, Ox2f27
r4, 0, r2
lis
ori
stwbrx
r3, MPClO6_Rm
It start building new register number
r3, r3, EXT_MElCEND_03 It register number Ox9B
r3, 0, rl
It write this value to CONFIG_ADDR
lwbrx
lis
ori
and
stwbrx
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPClO6JlEl3
It start building new register number
r3, r3, EXT_MElCEND_47 It register number Ox9c
r3, 0, rl
It write this value to CONFIG_ADDR
lwbrx
lis
ori
and
stwbrx
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPClO6JlEl3
r3, r3, MElCBANICEN
r3, 0, rl
(no reserved bits)
write the modified data to
It
It
CONFIG_DATA
;It
start building new register number
register number Ox94
It write this value to CONFIG_ADDR
It
It
on MOC2 is BMB
(no reserved bits)
It write the modified data to
It Each bank
It
CONFIG_DATA
;It
0, r2
Oxfcfc
rO, Oxfcfc
r4, rO
0, r2
load r4 from CONFIGJ'ATA
on MOC2 is BMB
It
It Each bank
It
clears all non-reserved bits
write the modified data to CONFIGJ'ATA
It
It
;It
0, r2
Oxfcfc
rO, Oxfcfc
r4, rO
0, r2
load r4 from CONFIG_DATA
Each bank on MOC2 is BMB
It
It
It
clears all non-reserved bits
write the modified data to CONFIG_DATA
It
It
;1
I
start building new register number
register number OxaO
write this value to CONFIG..JIDDR
It
I
r4, OxOOOO
It ENABLE ALL B BANKS OF DRAM
r4, r4, OxOOff
I (no reserved bits)
r4, O(r2)
I write the modified data to CONFIG_DATA
endnrlc2init
IIjump to enable memories
;#**********************edo initialization**···*··*···****···*·*··**·****··*··
ini tm:ic2edo:
lis
ori
stb
b
1.+
;1
lis
ori
stwbrx
r3, MPClO6_Rm
r3, r3, MCCRl
r3, 0, rl
I start building new register number
I register number OxfO
I
write this value to
CONFIG_ADDR
;1
MOTOROLA
Appendix D. Initialization Example
0-7
and
or
stwbrx
r4,
rO,
rO,
r4,
r4,
r4,
lis
ori
stwbrx
r3, MPCI06_REG
r3, r3, MCCR2
r3, 0, rl
lwbrx
lis
ori
II load r4 from CONFIG_DATA
0, r2
Ox0016
rO, 0x5555
r4, rO
r4, rO
0, r2
# REDUCE WAIT STATES FOR ROM ACCESSES
II (contains no reserved bits)
# clears the desired bits
sets the desired bits
/I
# write the modified data to CONFIG_DATA
;#
lwbrx
lis
;lI lis
ori
and
or
stwbrx
II start building new register number
# register number Oxf4
# write this value to CONFIG_ADDR
r4, 0, r2
# load r4 from CONFIG_DATA
rO, OxOOOl
II Self-Refresh value (not used for MDC2 or MDC3) EDO mode set
# Self-Refresh value (not used for MDC2 or MDC3) EDO mode NOT set
rO, OxOOOO
# Ox30d (decimal 781) clocks between refresh, BUF=E/E
rO, rO, OxOc34
;# 781 clocks for 50 MHz, 1041 for 66.6 MHz
r4, r4, rO
# clears the desired bits
r4, r4, rO
# sets the desired bits
# write the modified data to CONFIG_DATA
r4, 0, r2
;#
-
;11
;11
;11
;11
0-8
lis
ori
stwbrx
r3, MPCI06JU;:G
r3, r3, MCCR3
r3, 0, rl
lwbrx
lis
ori
and
or
stwbrx
r4,
rO,
rO,
r4,
r4,
r4,
0, r2
Ox0002
rO, Oxa294
r4, rO
r4, rO
0, r2
II
II
II
II
II
lis
ori
stwbrx
lwbrx
r3,
r3,
r3,
r4,
MPC1 06_REG
r3, MCCR4
0, rl
0, r2
II start building new register number
II register number Oxfc
II write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
lis
ori
and
lis
lis
ori
or
stwbrx
rO, Oxffef
rO, rO, Oxffff
r4, r4, rO
rO, OxOOOO
rO, Ox0010
rO, rO, OxOOOO
r4, r4, rO
r4, 0, r2
lis
ori
and
# start building new register number
# register number Oxf8
# write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
RAS6P=0101, CAS5=010, CP4=001,
CAS3= 010, RCD2=010, RP1=100
clears the desired bits
sets the desired bits
write the modified data to CONFIG_DATA
II all BUT bit 20 are reserved!!!
II bit 31 is MSb
II clears all Oxfc reg bits except reserved bits
II set RCBUF=O for flow thru data buffers
II set RCBUF=l for clocked/latched data buffers
II
# sets the desired bits
II write value to CONFIG_DATA
rO, OxOOOO
rO, rO, OxOOOO
r4, r4, rO
II set RCBUF=O for flow thru data buffers
II
II clears the desired bits
MPC106 PCIBIMC User's Manual
MOTOROLA
;#
;#
or
stwbrx
r4, r4, rO
r4, 0, r2
# sets the desired bits
# write the modified data to CONFIG-PATA
;#
;#
;# For MDC2, 32MB total of EDO DRAM
;#
;# BankO
;# Bank1
;# Bank2
;# Bank3 =
;# Bank4 =
;# BankS =
;# Bank6
;# Bank7 =
Ox 0000 0000 - Ox
not ilnplemented
Ox 0080 0000 - Ox
not ilnplemented
Ox 0100 0000 - Ox
not ilnplemented
Ox 0180 0000 - Ox
not ilnplemented
007f ffff start=OO ext=OO end=07 extend=OO
OOff ffff start=08 ext=OO end=Of extend=OO
017f ffff start=10 ext=OO end=17 extend=OO
01ff ffff start=18 ext=OO end=lf extend=OO
;#
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MElLSTA_03
r3, 0, r1
# start building new register number
lis
ori
stwbrx
r4, Oxed08
r4, r4, OxedOO
r4, 0, r2
lis
ori
stwbrx
r3, MPC1 06_REG
r3, r3, ME!CSTA_47
r3, 0, r1
lis
ori
stwbrx
r4, Oxed18
r4, r4, Oxed10
r4, 0, r2
lis
ori
stwbrx
r3, MPC1Q.6_REG
# start building new register number
r3, r3, EXT_MEM_ST~03 # register number Ox88
r3, 0, r1
# write this value to CONFIG_ADDR
lwbrx
lis
ori
and
stwbrx
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPC106 REG
# start building new register number
r3, r3, EXT_MEM_ST~47 # register number Ox8c
r3, 0, r1
# write this value to CONFIG..J\DDR
lwbrx
lis
r4, 0, r2
rO, Oxfcfc
# register number Ox80
# write this value to CONFIG.,J\DDR
# Each bank on MDC2 is 8MB
#
(no reserved bits)
# write the modified data to CONFIG_DATA
;#
# start building new register number
# register number Ox84
# write this value to CONFIG-fiDDR
# Each bank on MDC2 is 8MB
#
(no reserved bits)
# write the modified data to CONFIG-PATA
;#
0, r2
Oxfcfc
rO, Oxfcfc
r4, rO
0, r2
# load r4 from CONFIG-PATA
# Each bank on MDC2 is 8MB
#
# clears all non-reserved bits
-
# write the modified data to CONFIG_DATA
;#
MOTOROLA
# load r4 from CONFIG_DATA
# Each bank on MDC2 is 8MB
Appendix D. Initialization Example
0-9
ori
and
stwbrx
rO, rO, Oxfcfc
r4, r4, rO
r4, 0, r2
#
# clears all non-reserved bits
# write the modified data to CONFIG-PATA
lis
ori
stwbrx
r3, MPCl06_REG
r3, r3, MEMJ:ND_03
r.3, 0, rl
# start building new register number
# register number Ox90
# write this value to CONFIG_ADDR
lis
ori
stwbrx
r4, OxedOf
r4, r4, Oxed07
r4, 0, r2
# Each bank on MDC2 is 8MB
# (no reserved bits)
# write the modified data to CONFIG_DATA
lis
ori
stwbrx
r3, MPCl06_REG
r3, r3, MEM_END_47
r3, 0, rl
# start building new register number
# register number Ox94
# write this value to CONFIG_ADDR
lis
ori
stwbrx
r4, Oxedlf
r4, r4, Oxed17
r4, O. r2
# Each bank on MDC2 is 8MB
# (no reserved bits)
# write the modified data to CONFIG-PATA
lis
ori
stwbrx
r3, MPCl06_REG
# start building new register number
r3, r3, EXT_MEM_END_03 # register number Ox98
r3, 0, rl
/I write this value to CONFIG_ADDR
lwbrx
lis
ori
and
stwbrx
r4,
rO.
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPCl06_REG
# start building new register number
r3, r3, EXT_ME!CEND_47 # register number Ox9c
r3, 0, rl
# write this value to CONFIG_ADDR
lwbrx
lis
ori
and
stwbrx
r4,
rO,
rO,
r4,
r4,
lis
ori
stwbrx
r3, MPCl06_REG
# start building new register number
r3, r3, MEM_BANK_EN # register number OxaO
r3, 0, rl
# write this value to CONFIG..J\DDR
lis
ori
r4, OxOOOO
r4, r4, Ox0055
;#
;#
;#
0, r2
Oxfcfc
rO, Oxfcfc
r4, rO
0, r2
#
#
#
#
#
load r4 from CONFIG_DATA
Each bank on MDC2 is 8MB
clears all non-reserved bits
write the modified data to CONFIG-PATA
;#
-
0, r2
Oxfcfc
rOo Oxfcfc
r4. rO
0, r2
# load r4 from CONFIG_DATA
# Each bank on MDC2 is 8MB
#
# clears all non-reserved bits
/I write the modified data to CONFIG-PATA
;#
0-10
# ~LE 0,2,4,6 banks of edo 8 rob each
# (no reserved bits)
MPC106 PCIBIMC User's Manual
MOTOROLA
stb
r4, 0(r2)
# write the modified data to CONFIG_DATA
endmdc2init:
;#
;#
lis
ori
stwbrx
r3, MPC106_REG
r3, r3, MEICPGMAX
r3, 0, rl
lbz
lis
ori
ori
or
stb
1hz
r4, 3 (r2)
rO, OxOOOO
rO, rO, Ox0020
rO, rO, OxOOOO
r4, r4, rO
r4, 3 (r2)
r4, 3 (r2)
it********************* end
# start building new register number
# register number Oxa3
# write this value to CONFIG_ADDR
# load r4 from CONFIG_DATA
#
# this byte numberX64
# this byte numberX64
# sets the desired bits
# write the modified data to CONFIG_DATA
# load r4 from CONFIGJ)ATA look at contents
of edo or pdram initialization********************
;#
; # DRAM SHOULD NOW BE CONFIGURED AND ENABLED - MUST WAIT 200 us BEFORE ACCESSING
;#
li
mtctr
wait200us:
rO, 0x3800
rO
bdnz
wait200us
lis
ori
stwbrx
r3, MPC106Jm:;
r3, r3, MCCRl
r3, 0, rl
lwbrx
lis
ori
or
stwbrx
r4,
rO,
rO,
r4,
r4,
#
;#
0, r2
OxOO08·
rO, OxOOOO
r4, rD
0, r2
# start building new register number
# register number OxfO
# write this value to CONFIG.j\DDR
# load r4 fram CONFIGJ)ATA
# MEIf3O=l
# set the MEIf30 bit
# write the modified data to CONFIGJ)ATA
;#
li
mtctr
wait8ref:
bdnz
rD, 0x2000
# approx decimal 8000
rO
wait8ref
;#
; # DRAM ON MDC2 IS NOW AVAILABLE FOR USE - ASSERT DRAMINIT FLAG IN TCSRO REGISTER
;#
lis
ori
stwbrx
r3, TCPCI_REGS
r3, r3, ~
r3, 0, rl
#
# r3 = Ox 8000 505c for PortHole
# write this value to CONFIG.j\DDR
li
sthbrx
r3, OxOOO2
r4, r3, r2
# 2-byte write to ~2
# write the CONFIGJ)ATA
to assert DRAMINIT
;#
;#=====================================================================================
MOTOROLA
Appendix o. Initialization Example
0·11
;#
;#
Now let's turn on the L2 cache
uncornment the desired mode below
;#
;#
;#
;#
;#
lis
ori
stwbrx
r3, MPC106J!E(3
r3, r3, PICRl
r3, 0, rl
lwbrx
ori
stwbrx
ori
stwbrx
r4, 0, r2
r4, r4, OxOOOl
r4, 0, r2
r4, r4, OxOOO2
r4, 0, r2
# start building new register number
# register number Oxa8
# write this value to
CONFIG~ADDR
# load r4 from CONFIGJ)ATA
# set bit 0 for write-through L2
# write Ox ff75 0699 to CONFIG_DATA
# set bit 1 for write-back L2
# write Ox £f75 069a to CONFIG_DATA
0-12
MPC106 PCIBIMC User's Manual
MOTOROLA
Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this
book. Some of the terms and definitions included in the glossary are reprinted from IEEE
Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©I985 by
the Institute of Electrical and Electronics Engineers, Inc. with the permission of the IEEE.
Note that some terms are defined in the context of how they are used in this book.
A
Architecture. A detailed specification of requirements for a processor or
computer system. It does not specify details of how the processor or
computer system must be implemented; instead it provides a
template for a family of compatible implementations.
Atomic. A bus access that attempts to be part of a read-write operation to the
same address uninterrupted by any other access to that address (the
term refers to the fact that the transactions are indivisible). The 60x
processor initiates the read and write separately, but signals the
memory system that it is attempting an atomic operation. If the
operation fails, status is kept so that the 60x can try again. The 60x
implements atomic accesses through the lwarxlstwcx. instruction
pair, which asserts the TIO signal.
B
Beat. A single state on the 60x interface that may extend across multiple bus
cycles. A 60x transaction can be composed of multiple address or
data beats.
Big-endian. A byte-ordering method in memory where the address n of a
word corresponds to the most-significant byte. In an addressed
memory word, the bytes are ordered (left to right) 0, 1,2,3, with 0
being the most-significant byte. See Little-endian.
Block. An area of memory that ranges from 128 Kbyte to 256 Mbyte, whose
size, translation, and protection attributes are controlled by the block
address translation (BAT) mechanism.
Buffer. A temporary storage mechanism for queuing data.
MOTOROLA
Glossary of Terms and Abbreviations
Glossary-1
Burst. A multiple beat data transfer whose total size is typically equal to a
cache line (32-bytes).
Bus clock. Clock that synchronizes the bus state transitions.
Bus master. The owner of the address or data bus; the device that initiates or
requests the transaction.
C
Cache. High-speed memory containing recently accessed data and/or
instructions (subset of main memory).
Cache flush. An operation that removes from a cache any data from a
specified address range. This operation ensures that any modified
data within the specified address range is written back to main
memory. This operation is generated typically by a Data Cache
Block Flush (dcbf) instruction.
Caching-inhibited. A memory update policy in which the cache is bypassed
and the load or store is performed to or from main memory.
Cache line. A small region of contiguous memory that is copied from
memory into a cache. The size of a cache line may vary among
processors; the maximum block size is one page. Note that the term
'cache line' is often used interchangeably with 'cache block'.
Cast-outs. Cache line that must be· written to memory when a snoop miss
causes the least recently used cache line with modified data to be
replaced.
Clear. To cause a bit or bit field to register a value of zero, See also Set.
Copy-back operation. A cache operation in which a cache line is copied
back to memory. Copy-back operations consist of snoop push-out
operations and cache cast-out operations.
D
Direct-store. Interface available on PowerPC processors only to support
direct-store devices from the POWER architecture.
Disconnect. The termination of a PCI cycle initiated by the target because it
is unable to respond within eight PCI clock cycles. Note that the term
'disconnect' is often used interchangeably with 'target-disconnect'.
E
Glossary-2
Exception. An unusual or error condition encountered by the processor that
results in special processing.
MPC106 PCIBIMC User's Manual
MOTOROLA
F
Fetch. Retrieving instructions from either the cache or main memory and
placing them into the instruction queue.
Flush. An operation that causes a modified cache line to be invalidated and
the data to be written to memory.
I
Implementation. A particular processor that conforms to the PowerPC
architecture, but may differ from other architecture-compliant
implementations for example in design, feature set, and
implementation of optional features. The PowerPC architecture has
many different implementations.
In-order. An aspect of an operation that adheres to a sequential model. An
operation is said to be performed in-order if, at the time that it is
performed, it is known to be required by the sequential execution
model. See Out-of-order.
Interrupt. An external signal that causes the 60x to suspend current
execution and take a predefined exception.
K
Kill. An operation that causes a cache line to be invalidated.
L
Ll cache. See Primary cache.
L2 cache. See Secondary cache.
Latency. The number of clock cycles necessary to execute an instruction and
make ready the results of that instruction.
Least-sigilificant byte (LSB). The byte of least value in an address, register,
data element, or instruction encoding.
Little-endian. A byte-ordering method in memory where the address n of a
word corresponds to the least-significant byte. In an addressed
memory word, the bytes are ordered (left to right) 3, 2, 1,0, with 3
being the most-significant byte. See Big-endian.
M
Most-significant bit (msb). The highest-order bit in an address, registers,
data element, or instruction encoding.
Most-significant byte (MSB). The highest-order byte in an address,
registers, data element, or instruction encoding.
MOTOROLA
Glossary of Terms and Abbreviations
Glossary-3
Multiplex. To combine two or more signals into a single physical pin. The
pin may alternate between the multiple signal functions (such as the
PCI CIBE[3-O] signals), or may provide only one function based on
the configuration (such as the BAOIBR3 signal).
Munging. A technique used to alter the byte-ordering of data by modifying
its address; commonly used when translating between big-endian
and little-endian data formats.
N
o
Nibble. A sequence of four bits. In the context of ECC, a nibble is either the
high-order four bits (bit 0-3) or the low-order four bits (bits 4-7) in
a byte.
Optional. A feature, such as an instruction, a register, or an exception, that is
defined by the PowerPC architecture but not required to be
implemented.
Out-of-order. An aspect of an operation that allows it to be performed ahead
of one that may have preceded it in the sequential model, for
example, speculative operations. An operation is said to be
performed out-of-order if, at the time that it is performed, it is not
known to be required by the sequential execution model. See
In-order.
Overflow. An error condition that occurs during arithmetic operations when
the result cannot be stored accurately in the destination register(s).
For example, if two 32-bit numbers are multiplied, the result may not
be representable in 32 bits.
P
Page. A 4-Kbyte area of memory, aligned on a 4-Kbyte boundary.
Park. The act of allowing a bus master to maintain mastership of the bus
without having to arbitrate.
PCI (peripheral component interconnect).A computer bus standard,
managed by an industry consortium called the PCI SIG (Special
Interest Group), that uses a 32- or 64-bit multiplexed address/data
bus and provides the interconnect mechanism between peripheral
components.
Physical memory. The actual memory that can be accessed through the
system's memory bus.
Pipelining. A technique that breaks operations, such as instruction
processing or bus transactions, into smaller distinct stages or tenures
Glossary-4
MPC106 PCIB/MC User's Manual
MOTOROLA
(respectively) so that a subsequent operation can begin before the
previous· one has completed.
Primary (Ll) cache. The cache resource that is most readily available to a
processor (for example, the internal cache of a 60x processor). See
also Secondary (L2) cache.
R
Retry. Resending the current address or data beat until it can be accepted.
Refresh. Periodic charging a device that cannot hold its content. Dynamic
RAM (DRAM) devices require refresh cycles every few
milliseconds to preserve their charged bit patterns.
Reservation. The processor establishes a reservation on a cache line of
memory space when it executes an Iwarxlstwcx. instruction to read
a memory semaphore into a GPR.
Reserved. In a register, a reserved field is one that is not assigned a function.
A reserved field may be a single bit. The handling of reserved bits is
implementation-dependent. Software is permitted to write any value
to such a bit. A subsequent reading of the bit returns 0 if the value
last written to the bit was 0 and returns an undefined value (0 or 1)
otherwise.
RIse (reduced instruction set computing). An architecture characterized
by fixed-length instructions with nonoverlapping functionality and
by a separate set of load and store instructions that perform memory
accesses.
S
Scan interface. The 60x's test interface.
Secondary (L2) cache.The cache resource that is next-to-the-most readily
available to a processor, the primary (Ll) cache being the most
readily available. This cache is typically larger, offers slower access
time than a primary cache, and may be accessed by multiple devices.
The use of a secondary cache improves performance by reducing the
number of bus accesses to external main memory.
Set (v). To write a nonzero value to a bit or bit field, the opposite of clear. The
term 'set' may also be used to generally describe the updating of a
bit or bit field.
Set (n). A subdivision of a cache. Cacheable data can be stored in a given
location in anyone of the sets, typically corresponding to its lowerorder address bits. Because several memory locations can map to the
MOTOROLA
Glossary of Terms and Abbreviations
Glossary-5
same location, cached data is typically placed in the set whose cache
line corresponding to that address was used least recently.
Slave. The device addressed by a master device. The slave is identified in the
address tenure/phase and is responsible for supplying or latching the
requested data for the master during the data tenure/phase.
Snooping. Monitoring addresses driven by a bus master to detect the need for
coherency actions.
Snoop push. Write-backs due to a snoop hit. The cache line will transition to
an invalid or exclusive state.
Synchronization. A process to ensure that operations occur strictly in order.
System memory. The physical memory available to a processor.
T
Target-disconnect. The termination of a PCI cycle initiated by the target
because it is unable to respond within eight PCI clock cycles. Note
that the term 'target-disconnect' is often used interchangeably with
'disconnect' .
Tenure. The period of bus mastership. For the 60x, there can be separate
address bus tenures and data bus tenures. A tenure consists of three
phases-arbitration, transfer, termination.
Throughput. The measure of the number of instructions that are processed
per clock cycle.
Timeout. A transaction termination due to exceeding a latency limit. A
transaction is not necessarily concluded when a timeout occurs.
Transaction. A complete exchange between two bus devices. A transaction
is minimally comprised of an address tenure/phase; one or more data
tenures/phases may be involved in the exchange. There are two kinds
of transactions-address/data and address-only.
Transfer termination. Signal that refers to both signals that acknowledge the
transfer of individual beats (of both single-beat transfer and
individual beats of a burst transfer) and to signals that mark the end
of the tenure/phase.
W
Word. A 32-bit data element.
Write-back.A memory update policy in which processor write cycles are
only required to be written to the cache. The data in the cache does
Glossary-6
MPC106 PCIB/MC User's Manual
MOTOROLA
not necessarily stay consistent with that same location's data in
memory. The data in the cache is copied to memory when a copyback operation is required.
Write-through. A memory update policy in which all processor write cycles
are written to both the cache and memory.
IMC-'
MOTOROLA
Glossary of Terms and Abbreviations
Glossary-7
INDEX
Note: Italics are used throughout the index to indicate words that are found in the glossary (with the exception of
document references, which are also italicized).
dual processor arbitration, 4-9
signals, 4-7
L2 cache address operations, 5-9
snoop operation, 4-17
transfer attribute signals, 4-10
transfer termination, 4-16
Address maps
address map A
contiguous map, 3-4
discontiguous map, 3-5
overview, 3-1
PCI 110 map, 3-7
PCI memory map, 3-6
address map B, overview, 3-7, 3-11
addressing on PCI bus, 7-6
DBGO signal, 3-1
description, 3-1
emulation mode address map, 3-1, 3-11, 3-64, 7-27
ESCRI register, 3-1, 3-64, 7-27
examples, configuration sequences, 3-16
Addressing
L2 cache addressing, 5-9
memory addressing, 6-8, 6-41
PClbus
configuration space, 7-7
110 space, 7-7
memory space, 7-6
ADn (PCI address/data bus) signals, 2-33, 7-6
ADS (address strobe) signal, 2-20, 5-39
Alignment
aligned data transfers, 4-14
byte alignment, 6-58,7-8, B-1
Alternate bus master, usage, 4-1
Alternate OS-visible parameters registers, 3-63
An (60x address bus) signals, 2-9
Arbitration
60x bus
address bus arbitration, 4-8
address tenure, 4-6
arbitration signals, 4-7
data bus, 4-18
data tenure, 4-6
dual processor arbitration, 4-9
internal arbitration, 8-9
PCI bus arbitration, 7-3
Architecture, PowerPC, xxv
Numerics
60x address bus, see Address bus, 60x
60x data bus, see Data bus, 60x
60x processor interface
60x local bus slave timing, 4-21
address retry, 2-10, 4-8
address tenure operations, 4-8
alternate bus master, 4-1
burst ordering and data transfers, 4-14
bus accesses, 4-6
bus configuration, 4-1
bus error signals, 9-3
bus error status register, 3-29, 3-34, 3-41, 9-6
bus interface support, 4-1
bus interface unit (BIU), B-1
bus protocol, 4-6
bus request monitoring, power management, A-7
byte ordering, B-1
configuration registers, 3-51, 4-5
configuring power management, 3-26
data tenure operations, 4-18
error detection, 9-6
multiprocessor configuration, 4-3
overview, 1-4,4-1
PCI buffers, 8-3
PCI bus operations, 4-12
prograrurnable parameters
parking, 3-51, 4-5
PICRlIPICR2 registers, 3-51, 4-5
signals, 2-8
single-processor configuration, 4-1
slave support, 4-21
system memory buffer, 8-2
unsupported bus transactions error, 4-20, 9-6
A
AACK (address acknowledge) signal, 2-9, 4-16
Acronyms and Abbreviations, xxviii
Address bus, 60x
address tenure
bus protocol overview, 4-6
operations, 4-8
timing configuration, 4-18
arbitration
bus arbitration, 4-8
MOTOROLA
Index
Index-1
INDEX
ARn (ROM address) signals, 2-27, 6-58
ARTRY (address retry) signal, 2-10, 4-17
Asynchronous SRAMs
CF_DOE bit, 3-62, 5-26
CF_WDATA bit, 3-62, 5-26
CF_WMODE bit, 3-60, 5-27
description, 5-6
L2 cache timing examples, 5-39
B
BAO (burst address 0) signal, 2-20
BAA (bus address advance) signal, 2-20
Bank-activate command, SDRAM, 6-44
BCTLn (buffer control) signals, 2-27, 6-2
BOL2 (external L2 bus grant) signal, 2-24, 5-43
BOn (bus grant) signals, 2-11, 2-25,4-7
Bibliography of additional reading, xxvii
Big-endian mode
accessing configuration registers, 3-17
byte lane translation, B-2
byte ordering, B-2
LE_MODE bit, 3-55, B-1
PCI memory space, B-3, B-5
BIST (built-in self test) control register, 3-22
Boundary-scan registers, C-2
BRL2 (external L2 bus request) signals, 2-24, 5-43
BRn (bus request) signals, 2~11, 2-26, 4-7
Buffers
internal buffers
copy-back buffer, 8-2
PCI-to-system memory read buffer
(PCMRB),8-5
PCI-to-system memory write buffers
(PCMWBs),8-5
processor-to-PCI-read buffer (PRPRB), 8-4
processor-to-PCI-write buffers (PRPWBs), 8-5
memory buffers
configurations, parameter settings, 6-2
flow-through buffers, 6-3
latch-type buffers, 6-3
mode/control signals, 6-2
registered buffers, 6-4
Burst operations
60x data bus transfers
description, 4-14
normal termination, 4-19
64-bit data path, 6-18
burst ordering
60x data transfers, 4-14
PCI cache wrap mode, 7~
PCI linear incrementing, 7~
PCI bus transfer, 7-3
SDRAM-based systems, 6-42
Bus error status registers, 60x, 3-29, 3-34, 3-41, 9~
Index-2
Bus interface unit (BIU), 60x, B-1
Bus operations
60x processor interface
address tenure operations, 4-8
bus protocol, 4~
data tenure operations, 4-18
L2 cache response, 5-12
PCI bus transactions, 7-8
Bypass register, C-2
Byte
alignment, 6-58, 7-8, B-1
byte enable signals, 2-33, 7-8, 7-25
ordering
60x bus, B-1
big~ndian mode, B-2
least-significant byte (LSB), B-1
littIe-endian mode, B-5
nwst-significant byteJbit (MSBlmsb), B-1
PCI bus, 7-2, B-1
PCI alignment, 7-8, B-2
C
C/BEn (commandlbyte enable) signals, 2-33, 7-8,
7-25
Cache wrap mode, PCI, 7~
CASn (column address strobe) signals, 2-28, 6-8, 6-28
CHRP (common hardware reference platform), I-I,
3-1
CI (caching-inhibited) signal, 2-12
CKO (test clock) signal, 2-40
CKE (SDRAM clock enable) signal, 2-28
Clock configuration
PLLn (clock mode) signals, 2-44
power management support, A~
Clock signals, 2-40
Commands
PCI commands
C/BEn signals, 2-33, 7-4
interrupt-acknowledge transaction, 7-21
PCI command register, 3-23, 7-16
special-cycle command, 7-22
SDRAM commands
command encodings, 6-46
JEDEC standard commands, 6-44
mode-set command, 6-52
mode-set commands, 6-45
Common hardware reference platform
(CHRP), I-I, 3-1
Completion, PCI transaction, 7-11
Configuration
configuration registers
60x bus error status registers, 3-29, 3-34, 3-41,
9-6
60xlPCI error address register, 3-36, 9~
MPC106 PCIB/MC User's Manual
MOTOROLA
INDEX
DBGn (data bus grant) signals, 2-12, 2-26, 3-1, 4-7
DCS (data RAM chip select) signal, 2-21, 5-3-5-6
Device drivers
modifying for power management, A-8
posted writes, 8-5
DEVSEL (device select) signal, 2-35, 7-7
DHnlDLn (data bus) signals, 2-13, 6-6
Direct-store access, 4-20
DIRTY_IN signal, 2-21, 5-10
DIRTY_OUT signal, 2-22, 5-10
Disconnect, 7-2, 7-12, 8-4
DOE (data RAM output enable) signal, 2-22, 3-62,
5-26
Doze mode, 1-6, 6-27, A-3
DQMn (SDRAM data qualifier) signals, 2-29
DRAMIEDO interface
burst wrap, 6-18
CASn for byte lane selection, 6-8
DRAM system with parity, 16 Mbyte, 6-7
ECC single-bit error description, 6-21
interface operation, 6-6
interface timing, 6-11
latency, 6-18
memory configurations supported, 6-8
organizations supported, 6-7
page mode retention, 6-19
parity support, 6-20, 6-52
power-on initialization, 6-9
programmable parameters, 3-36, 6-9
refresh, 6-25
RMW parity, 6-20, 6-52
SDRAM page mode retention, 6-42
suggested DRAM timing configurations, 6-12
timing parameters, 6-12
use in MPC106, 6-1
see also Memory interface
DWEn (data RAM write enable) signals, 2-22, 5-3
accessing registers, 3-15-3-18
alternate OS-visible parameters registers, 3-63
ECC single-bit error registers, 3-29, 9-7
emulation support, 3-1, 3-64, 7-27
error detection registers, 3-32, 9-6
error enabling registers, 3-30, 9-6
error status registers, 3-34, 7-25
external configuration registers, 3-67
memory bank enable register, 3-40, 6-9
memory boundary registers, 3-36-3-40, 6-9
memory control configuration registers, 3-42, 6-2
memory interface configuration registers, 3-36
memory page mode register, 3-41
modified memory status register, 3-66
PCI command register, 3-23, 7-16
PCI status register, 3-24, 7-16
power management registers, 3-26-3-28, A-I
processor interface configuration registers, 3-51
register access, 3-15-3-18
reserved bits, 3-15
summary of registers, list, 3-19
configuration signals, 2-43
configuration space
MPC106 configuration space, 3-21
PCI addressing, 7-7
PCI configuration
configuration cycles
CONFIG_ADDR register, 3-8, 3-15, 7-17
CONFIG_DATA register, 3-8, 3-15, 7-18
configuration space header, 7-15
type 0 and 1 accesses, 7-16
configuration header summary, 3-22,7-16
Conventions, xxviii
CSn (SDRAM command select) signals, 2-28
D
Data bus, 60x
address tenure timing configuration, 4-19
arbitration signals, 4-7
bus arbitration, 4-18
bus transaction errors, 4-20, 9-6
data tenure
bus protocol overview, 4-6
operations, 4-18
data transfer, 4-14, 4-19
shared data bus, 8-2
termination by TEA, 4-19, 9-10
Data transfers, 60x
alignment, 4-14
burst ordering, 4-14
normal termination, 4-19
DBGL2 (external L2 data bus grant) signal, 2-24, 5-43
DBGLB (data bus grant local bus slave)
signal, 2-12, 4-21
MOTOROLA
E
ECC single-bit error
additional errors, 6-21
description, 6-21
registers, 3-29, 9-7
Emulation mode
address map overview, 3-11
emulation support, 7-27
ESCRllESCR2 registers, 3-1, 3-64,7-27
L2 cache and vector relocation, 5-12
ErrDRllErrDR2 (error detection) registers, 3-32,
7-25,9-6
ErrEnRllErrEnR2 (error enabling) registers, 3-30, 9-6
Errors
error detection registers, 3-32, 7-25,9-6
error enabling registers, 3-30, 9-6
Index
Index-3
INDEX
error handling
overview, 9-1
registers, 3-29, 7-25, 9-3-9-4
error reporting
60x processor interface, 9-6
address/data error, 7-13, 9-8
error detection registers, 3-32, 7-25, 9-6
errors within a nibble, 6-21, 9-8
Flash write error, 9-6
illegal L2 copy-back error, 9-6
L2 cache read data parity error, 9-7
master-abort transaction tennination, 7-11, 9-9
nonmaskable interrupt, 2-41, 9-10
PCI bus, 7-25, 9-5
PERR and SERR signals, 7-26, 9-5
system memory errors, 6-1, 9-7
TEA and MCP signals, 2-14, 2-16, 4-19, 9-1
unsupported bus transaction error, 4-20, 9-6
error Status registers, 3-34, 7-25, 9-6
interrupt and error signals, 2-14, 2-40, 9-3
overflow condition, 3-30, 9-8
ESCRIIESCR2 (emulation support configuration)
registers, 3-1, 3-64, 7-27
Exceptions
bus errors, 9-4
interrupt and error signals, 2-40, 9-3
interrupt latencies, 9-10
interrupt priorities, 9-2
system reset interrupt, 9-3
Exclusive access, PCI, 7-23
External configuration registers, 3-67
F
FLSHREQ (flush request) signal, 2-39, 7-27
FNR (ROM bank 0 data path width) signal, 2-44
FOE (flash output enable) signal, 2-29, 6-63
FRAME signal, 2-35, 7-3
Full-on mode, 1-6,6-27, A-3
G
G8L (global) signal, 2-14
GNT (PCI bus grant) signal, 2-35, 7-3
Initialization
DRAM power-on initialization, 6-9
initialization code example, D-l
SDRAM power-on initialization, 6-43
Interface
60x processor interface
60x local bus slave timing, 4-21
address retry, 2-10, 4-8
address tenure operations, 4-8
alternate bus master, 4-1
burst ordering and data transfers, 4-14
bus accesses, 4-6
bus configuration, 4-1
bus error signals, 9-3
bus error status register, 3-29, 3-34, 3-41, 9-6
bus interface support, 4-1
bus interface unit (81U), B-1
bus protocol, 4-6
bus request monitoring, power management, A-7
byte ordering, 60x bus, B-1
configuration registers, 3-51, 4-5
configuring power management, 3-26
data tenure operations, 4-18
error detection, 9-6
multiprocessor configuration, 4-3
overview, 1-4, 4-1
PCI buffers, 8-3
PCI bus operations, -4-12
signals, 2-8
single-processor configuration, 4-1
slave support, 4-21
system memory buffer, 8-2
unsupported bus transactions error, 4-20, 9-6
JTAG interface
block diagram, C-l
description, C-l
registers, C-2
signals, 2-42, C-2
see also JTAG interface
L2 interface
60x address bus, 5-9
cache configurations, 5-2
cache control parameters, 5-23, 5-43
cache flush, 3-58
H
HIT signal, 2-22, 2-25, 5-10
HRST (hard reset) signal, 2-40, 9-3, A-2
cache initialization parameters, 5-24
cache line status, 2-22, 5-10
cache operation, 5-43
cache tag lookup, 2-21, 5-10
cast-outs, 5-11
IEEE 1149.1 specifications
signals, 2-42, C-2
specification compliance, C-2
Implementation of the PowerPC architecture, 1-4
Index-4
CF_L2_HILDELAY timing
configuration, 3-61, 4-5, 4-21, 5-26
configuration registers, 3-56
copy-back operation, 5-10
data RAM write enable
MPC106 PCIBIMC User's Manual
MOTOROLA
INDEX
signals, 2-22
timings, 5-27
dirty bit, 5-2
external cache controller operation, 5-42
features list, 1-2
illegal L2 copy-back error, 9-6
internal cache controller operation, 5-9
overview, 1-4,5-1
parity support, 5-11
read data parity error, 9-7
response to bus operations, 5-12
signals, 2-19
SRAMs, 5-3-5-7, 5-30-5-41
tag RAM and data RAM addressing, 5-10
timing examples, 5-30
vector relocation, 5-12
write-back, 5-2, 5-12
write-through, 5-2, 5-20
memory interface
buffer mode parameters, 6-2
configuration registers, 3-36
DRAMIEDO
address mUltiplexing, 6-8
interface operation, 6-6
SDRAM address multiplexing, 6-41
see also DRAMIEDO interface
ECC error, 9-8
error detection, 9-7
errors within a nibble, 9-8
features list, 1-3
fetch,6-60
Flash interface
I-Mbyte Flash system, 6-58
cacheability restrictions, 6-59
description, 6-56
interface timing, 6-61
memory write timing, 6-64
paritylECC signals, 6-5
single-byte read timing, 6-62
write operations, 6-63
Flash write error, 9-6
MICR (memory interface configuration)
registers, 6-9
overview, 1-5, 6-1
page, 6-9
physical memory, 9-7
power management support, 6-27
read data parity error, 9-7
refresh overflow error, 9-8
registers, 3-36-3-42, 6-9
ROM interface
l6-Mbyte ROM system, 6-57
burst read timing, 6-61
cacheability restrictions, 6-59
description, 6-56
MOTOROLA
interface timing, 6-59
SDRAM interface operation
configurations supported, 6-41
overview, 6-39
see also SDRAM interface operation
select error, 9-8
signal buffering, 6-2
signals, 2-26
system memory, 6-1, 9-8
pel interface
address bus decoding, 7-6, A-7
address/data parity error, 7-13, 9-8
big-endian mode, B-3
burst operation, 7-3
bus arbitration, 7-3
bus commands, 7-4
bus error signals, 9-5
bus protocol, 7-3
bus transactions, 7-8, 7-21
byte alignment, 7-8, B-2
byte ordering, 7-2, B-1
ClBEn signals, 7-25
cache wrap mode, 7-6
command encodings, 7-4
configuration cycles, 7-15
configuration header, 7-15
configuration space addressing, 7-7
data transfers, 7-3, 7-8
error detection and reporting, 7-25, 9-5, 9-8
error transactions, 7-25
exclusive access, 7-23
fast back-to-back transactions, 7-14
features list, 1-3
110 space addressing, 7-7
linear incrementing, 7-6
master-abort transaction termination, 7-11,9-9
memory space addressing, 7-6
MPCI06 as PCI bus master, 7-2
MPCI06 as PCI target, 7-2
nonmaskable interrupt, 2-41, 9-10
overview, 1-6, 7-1, 7-1
pel Local Bus Specification, xxvii, 3-22
PCI special-cycle operations, 7-23, A-7
pel System Design Guide, xxvii, 3-22
PCI-to-ISA bridge, 7-27
PCI-to-system memory read buffer
(PCMRB),8-5
PCI-to-system memory write buffers
(PCMWBs),8-5
processor-to-PCI read buffer (PRPRB), 8-4
processor-to-PCI-write buffers (PRPWBs), 8-5
read transactions, 7-9
registers, 3-22, 7-16, 9-9
retry PCI transactions, 7-12
signals, 2-33, 7-3-7-8
Index
Index-5
INDEX
target-abort error, 7-12, 9-10
target-disconnect, 7-2, 7-12, 8-4
target-initiated termination, 7-12
transaction termination, 7-11
turnaround cycle, 7-8
write transactions, 7-10
Internal control
arbitration
in-order execution, 8-9
out-oj-order execution, 8-1
buffers, 8-1
Interrupts, see Exceptions
IRf5Y (initiator ready) signal, 2-36, 7-3
ISA_MASTER signal, 2-39,7-26
J
JTAG interface
block.diagram of JTAG interface, C-1
boundary-scan registers, C-2
bypass register, C-2
description, C-1
instruction register, C-3
JTAG registers, C-2
JTAG signals, 2-42, C-2
scan interface, 1-4
status register, C-3
TAP controller, C-3
K
Kill operation, 3-60
L
L2 (secondary) cache, see L2 interface
L2 interface
60x address bus, 5-9
cache configurations, 5-2
cache control parameters, 5-23, 5-43
cache flush, 3-58
cache initialization parameters, 5-24
cache line status, 2-22, 5-10
cache operation, 5-43
cache tag lookup, 2-21, 5-10
cast-outs, 5-11
CF_L2_HIT_DELAY timing
configuration, 3-61, 4-5, 4-21, 5-26
configuration registers, 3-56
copy-back operation, 5-10
data RAM write enable
signals, 2-22
timings, 5-27
dirty bit, 5-2
external cache controller operation, 5-42
Index-6
features list, 1-2
illegal L2 copy-back error, 9-6
internal cache controller operation, 5-9
overview, 1-4, 5-1
parity support, 5-11
read data parity error, 9-7
response to bus operations, 5-12
signals, 2-19
SRAMs
asynchronous SRAMs, 5-6, 5-39
pipelined burst SRAMs, 5-4
synchronous burst SRAMs, 5-3, 5-30
two-bank support, 5-7
tag RAM and data RAM addressing, 5-10
timing diagrams
burst read, 5-39
burst read line update, 5-40
burst write, 5-41
castout timing, 5-34
castout timing with no ARTRY, 5-35
hit following PCI read snoop, 5-36
invalidate following PCI read snoop, 5-38
legend for timing diagrams, 5-30
push following PCI write snoop, 5-37
read hit timing, 5-31
update timing, 5-33
write hit timing, 5-32
vector relocation, 5-12
write-back, 5-2, 5-12
write-through, 5-2, 5-20
Latency, DRAMlEDO, 6-18
LBCLAIM (local bus slave claim) signal, 2-14, 4-21
Little-endian mode
accessing configuration registers, 3-15
aligned scalars, address modification, B-5
byte lane translation, B-6
byte ordering, B-5
LE_MODE bit, 3-55, B-5
PCI bus, 7-2, B-1
PCI I/O space, 8-12
PCI memory space, B-9
Local bus slave timing, 60x, 4-21
LOCK signal, 2-36, 7-23
M
MAn (memory address) signals, 2-29, 6-9
Master-abort, PCI, 7-11, 9-9
MCCRn (memory control configuration)
registers, 3-42-3-49
MCP (machine check) signal, 2-14, 4-19, 9-3
Mi5LE (memory data latch enable) signal, 2-29, 6-3
MEMACK (memory acknowledge) signal, 2-40,7-27
MPC106 PCIB/MC User's Manual
MOTOROLA
INDEX
Memory interface
buffer mode parameters, 6-2
configuration registers, 3-36
DRAMIEDO
address multiplexing, 6-8
interface operation, 6-6
SDRAM address multiplexing, 6-41
see also DRAMIEDO interface
ECC error, 9-8
error detection, 9-7
errors within a nibble, 9-8
features list, 1-3
fetch,6-60
Hash interface
I-Mbyte Hash system, 6-58
cacheability restrictions, 6-59
description, 6-56
interface timing, 6-61
memory write timing, 6-64
paritylECC signals, 6-5
single-byte read timing, 6-62
write operations, 6-63
Hash write error, 9-6
memory configurations, 6-10, 6-11
overview, 1-5, 6-1
page, 6-9
physical memory, 9-7
power management support, 6-27,6-55
read data parity error, 9-7
refresh overflow error, 9-8
registers
memory bank enable register, 3-40, 6-9
memory boundary registers, 3-36-3-40, 6-9
memory control configuration registers, 3-42
memory page mode register, 3-41
ROM interface
16-Mbyte ~OM system, 6-57
burst read timing, 6-61
cacheability restrictions, 6-59
description, 6-56
interface timing, 6-59
select error, 9-8
signal buffering, 6-2
signals, 2-26
system memory, 6-1, 9-8
Memory page mode register, 3-41
MICR (memory interface configuration)
registers, 6-9, 6-43
Misaligned 60x data transfer, 4-16
Mode-set command, SDRAM, 6-45,6-52
MPCI06
aligned scalars, address modification, B-6
block diagram, 1-2
default mode, A-3
device programming, 3-1
MOTOROLA
DRAMIEDO interface use, 6-1
major functional units, 1-4
PCI bus master, 7-2
PCI bus/memory controller features, 1-1
PCI sideband signals, 7-26
PCI target, 7-2
Multiprocessor implementations
address pipelininglsplit-bus capability, 4-7
multiprocessor configuration, 4-3
Munging
for 60x processors, B-1
munged memory image, LE mode, B-7
N
Nap mode
description, 1-6, A-3
memory refresh, 6-27
PMCR bit settings, 3-26
QREQ signal, A-I
special cycle, PCI, 7-22
Nibble, see Errors
NMI (nonmaskable interrupt) signal, 2-41, 9-5, 9-10
P
PAR (PCI parity) signal, 2-37, 7-25
PARn (data paritylECC) signals, 2-30
PCI interface
address bus decoding, 7-6, A-7
address/data parity error, 7-13, 9-8
big-endian mode, four-byte transfer, B-3
burst operation, 7-3
bus arbitration, 7-3
bus commands, 7-4
bus error signals, 9-5
bus protocol, 7-3
bus transactions
fast back-to-back transactions, 7-14
interrupt-acknowledge transaction, 7-21
legend for timing diagrams, 7-8
read transactions, 7-9
special-cycle transaction, 7-22
transaction termination, 7-11
write transactions, 7-10
byte alignment, 7-8, B-2
byte ordering, 7-2, B-1
cache wrap mode, 7-6
configuration cycles, 7-15
configuration header, 7-15
configuration space addressing, 7-7
data transfers, 7-3
error detection and reporting, 7-25, 9-5, 9-8
error transactions, 7-25
exclusive access, 7-23
Index
Index-7
INDEX
features list, 1-3
I/O space addressing, 7-7
linear incrementing, 7-6
little-endian mode transfers to I/O space, B-12
little-endian mode transfers to memory space, B-9
master-abort transaction termination, 7-11, 9-9
memory space addressing, 7-6
MPCI06 as PCI bus master, 7-2
MPCI06 as PCI target, 7-2
nonmaskable interrupt, 2-41, 9-10
overview, 1-6, 7-1
PCI command encodings, 7-4
PCI commands
interrupt-acknowledge transaction, 7-21
special-cycle command, 7-22
PCI Local Bus Specification, xxvii, 3-22
PCI special-cycle operations, 7-23, A-7
PCI System Design Guide, xxvii, 3-22
PCI-to-ISA bridge, 7-27, 9-5
PCI-to-system memory read buffer (PCMRB), 8-5
PCI-to-system memory write buffers
(PCMWBs), 8-5
processor-to-PCI read buffer (PRPRB), 8-4
processor-to-PCI-write buffers (PRPWBs), 8-5
registers
bus error status register, 3-35, 9-9
CONFIG_ADDR register, 3-8, 3-15, 7-17
CONFIG_DATA register, 3-8, 3-15,7-18
configuration header summary, 3-22, 7-16
PCI commands register, 3-23, 7-16
status register, 3-24, 7-16
retry PCI transactions, 7-12
signals
DEVSEL, 2-35, 7-7
error reporting signals, 9-5
FLSHREQ, 2-39, 7-27
FRAME, 2-35, 7-3
GNT, 2-35, 7-3
IROY, 2-36, 7-3
IS A_MASTER, 2-39, 7-26
I.OCK, 2-36, 7-23
MEMACK, 2-40, 7-27
PERR, 2-37, 7-26, 9-5
REQ, 2-37, 7-3
SERR, 2-38, 7-26, 9-5
TRDY, 2-38, 7-3
target-abort error, 7-12, 9-10
target-disconnect, 7-2, 7-12, 8-4
target-initiated termination, 7-12
turnaround cycle, 7-8
PERR (PCI parity error) signal, 2-37, 7-26, 9-5
PICRs (processor interface configuration registers)
PICR 1 register
address map A contiguity, 3-1, 3-53
Index-B
bit settings/overview, 3-52, 4-5
CF_BREAD_WS bit, 3-52, 4-5, 4-19
FLASH_WR_EN bit, 3-54, 9-6
LE_MODE (endian mode) bit, 3-55, 3-68, B-5
MCP_EN bit, 4-20, 9-3
speculative PCI reads bit, 3-55
ST_GATH_EN bit, 3-54
TEA_EN bit, 2-16, 3-54, 4-19, 9-4
XIO_MODE bit, 3-1, 3-53
PICR2 register
bit settings/overview, 3-58,4-5
CF_AP ARK bit, 3-55, 4-5
CF_APHASE_WS bit, 3-62, 4-5
CF_DOE bit, 3-62, 5-26
CF_FAST_CASTOUT bit, 3-61, 5-25
CF_HOLD bit, 3-61, 5-24
CF_L2_HIT_DELAY bit, 3-61,4-21,5-25
CF_SNOOP_WS bit, 3-60, 4-5
CF_TWO_BANKS bit, 3-61, 5-7
CF_WDATA bit, 3-62, 5-26
CF_WMODE bit, 3-60, 5-27
FLASH_WR_LOCKOUT bit, 3-59, 9-6
L2_EN bit, 3-58, 3-69, 5-23
TEA_EN bit, 3-69
Pipelined burst SRAMs
CF_WDATA bit, 3-62, 5-26
description, 5-4
Pipe lining
address pipelining, 4-7, 4-10
memory latency, 4-7
split-bus transactions, 4-7
throughput, 4-7
PLLn (clock mode) signals, 2-44
PMCR registers
refresh during power saving modes, 6-55
PMCR registers, see Power management
Power management
clock configuration, A-6
doze mode, 6-27, A-3
DRAM refresh, 6-27
full-on mode, 6-27, A-3
memory interface, support, 6-27, 6-55
memory refresh operation, 6-25
memory refresh operations, A-7
modifying device drivers, A-8
MPCI06 default mode, A-3
MPCI06 support, A-6
nap mode, 6-27, 7-23, A-3, A-7
overview, 1-6
PCI address bus decoding, A-7
PCI special-cycle operations, 7-22
PMCR registers
DRAMIEDO refresh configuration, 6-27
LP_REF_EN bit, A-7
MPC106 PCIBIMC User's Manual
MOTOROLA
INDEX
Read-with-autoprecharge command, SDRAM, 6-45
Real-time clock signal, 2-31, 6-28, A-5
Refresh
DRAMIEDO refresh, 6-25
power management, refresh operations, 6-27,
6-55, A-7
SDRAM refresh
command, 6-45
overview, 6-53
timing diagram, 6-54
Registers
60x bus error status registers, 3-29, 3-34, 3-41, 9-6
60x/PCI error address register, 3-36, 9-6
alternate OScvisible parameters registers, 3-63
clearing bits, 3-24
configuration registers, 3-15
ECC single-bit error registers, 3-29, 9-7
error detection registers, 3-32, 9-6
error enabling registers, 3-30, 9-6
error handling registers, 3-29, 7-25, 9-3-9-4
error status registers, 3-34, 7-25
ESCRs (emulation support configuration)
registers, 3-1, 3-64
external configuration registers, 3-67
JTAG
boundary-scan registers, C-2
bypass register, C-2
instruction register, C-3
status register, C-3
MCCRn (memory control configuration)
registers, 3-42--3-49
memory bank enable register, 3-40, 6-9
memory boundary registers, 3-36-3-40, 6-9
memory page mode register, 3-41
MICRn (memory interface configuration)
registers, 3-36
optional register, BIST control, 3-22
PCI command register, 3-23, 7-16
PCI registers, 3-22
PCI status register, 3-24, 7-16
PICRn (processor interface configuration)
registers, 3-51, 4-5
power management registers, 3-26-3-28
setting bits, 3-24
REQ (PCI bus request) signal, 2-37, 7-3
Reservation set, lwarxlstwcx., 4-11
ROMlFlash interface
cacheability restrictions, 6-59
description, 6-56
Flash interface
I-Mbyte Flash system, 6-58
interface timing, 6-61
memory write timing, 6-64
paritylECC signals, 6-5
single-byte read timing, 6-62
overview, 3-26-3-28
PMbit,A-l
PMCRI
bit settings, 3-26
PM bit, 3-27
PMCR2 bit settings, 3-28
power management support, A-6
power modes, A-I
refresh and power saving modes, 6-27
power mode transition, A-I
processor bus request monitoring, A-7
QREQ signal, A-I
SDRAM power saving modes, 6-55
signals, 2-40
sleep mode, 3-26, 6-27,7-23, A-4
suspend mode, 2-31, 6-28, A-5
systems using 601, 3-27, A-2
systems using 603, 3-53, A-2
systems using 604, 3-27, A-2
Power mode transition with the PICRI,
PROC_TYPE bit, A-I
Power-on initialization
power-on reset (PaR), 3-36, 6-8, 9-3
SDRAM power-on initialization
overview, 6-43
programmable parameters, 6-43
setting up MICR parameters, 6-9
PowerPC
common hardware reference platform
(CHRP), I-I, 3-1
PowerPC 601 microprocessor, 3-27, A-2
PowerPC 603 microprocessor, 3-53, A-2
PowerPC 604 microprocessor
fast L2 mode, 5-1
power management, 3-27, A-2
PowerPC Reference Plaiform Specification, 3-1
programming the MPCI06, 3-1
PPEN (parity path read enable) signal, 2-30, 6-5
Precharge-all-banks command, SDRAM, 6-45
Precharge-bank command, SDRAM, 6-45
Processor interface, see 60x processor interface
Programming the MPC106, 3-1
Q
QACK (quiesce acknowledge) signal, 2-41, 3-27, A-I
QREQ (quiesce request) signal, 2-41, 3-27, A-I
R
RAM access time, 3-45
RASn (row address strobe) signals, 2-31, 6-6, 6-28
RCSO (ROM location configuration) signal, 2-44,
6-59
RCSn (ROM bank select) signals, 2-31
MOTOROLA
Index
Index-9
INDEX
write operations, 6-63
ROM interface
16-Mbyte ROM system, 6-57
burst read timing, 6-61
interface timing, 6-59
ROM address signals, 2-27
see also Memory interface
RTC signal, 2-31, 6-28, A-5
S
SDBAO (SDRAM internal bank select) signal, 2-32
SDCAS (SDRAM column address strobe) signal, 2-32
SDMAn (SDRAM address) signals, 2-32
SDRAM interface operation
128-Mbyte SDRAM system, 6-40
bank-activate command, 6-44
burst operations, 6-42
command encodings, 6-46
configurations supported, 6-41
JEDEC interface commands, 6-44
mode-set command, 6-45, 6-52
overview, 6-39
power saving modes, 6-55
power-on initialization, 6-43
precharge-all-banks command, 6-45
precharge-bank command, 6-45
prograrurnable parameters, 6-43
read-with-autoprecharge command, 6-45
refresh
command, 6-45
description, 6-53
self-refresh command, 6-45
timing diagrams
burst-of-four read timing, 6-47
burst-of-four write timing, 6-48
self-refresh entry timing, 6-55
self-refresh exit timing, 6-56
single-beat read timing, 6-50
single-beat write timing, 6-51
write-with-autoprecharge command, 6-45
SDRAM power-on initialization, 6-43
SDRAS (SDRAM row address strobe) signal, 2-32
Secondary (L2) cache, see L2 interface
Self-refresh command, SDRAM, 6-45
SERR (system error) signal, 2-38, 7-26, 9-5
Signal buffering
flow-through buffers, 6-3
memory interface buffer configurations, 6-2
parity/ECC path read control, 6-5
registered buffers, 6-4
transparent latch buffers, 6-3
Signals
60x address/data bus arbitration, 4-7
AACK, 2-9, 4-16
Index-10
ADn, 2-33, 7-6
ADS, 2-20, 5-39
alternate functions, list, 2-3
An, 2-9
ARn, 2-27, 6-58
ARTR'r, 2-10, 4-17
BAO, 2-20
BAA,2-20
BCTLn,2-27,6-2
BGL2, 2-24, 5-43
BGn, 2-11, 2-25, 4-7
BRL2, 2-24, 5-43
BRn, 2-11,2-26,4-7
C/BEn, 2-33, 7-8, 7-25
CASn,2-28,6-8,6-28
CI,2-12
CKO,2-40
CKE,2-28
configuration signals, 2-43
CSn, 2-28
DBGL2,2-24,5-43
DBGLB, 2-12, 4-21
DBGn,2-12,2-26,3-1,4-7
rx:s,2-21,5-3-5-6
DEVSEL, 2-35, 7-7
DHnIDLn, 2-13, 6-6
DIRT'r_IN, 2-21, 5-10
DIRT'r_OUT, 2-22, 5-10
DOE, 2-22, 3-62, 5-26
DQMn, 2-29
DWEn, 2-22, 5-3
error siguals, 2-40, 9-3
FLSHREQ, 2-39, 7-27
FNR,2-44
FOE,2-29, 6-63
FRAME, 2-35, 7-3
GBL, 2~14
GNT, 2-35, 7-3
HIT, 2-22, 2-25, 5-10
HRST, 2-40, 9-3, A-2
IEEE 1149.1 interface, 2-42, C-2
interrupt and error signals, 2-40, 9-3
interrupt signal connections, examples, 9-10
interrupt signals, 2-40, 9-3
interrupt, clock, and power management, 2-40
IRDY, 2-36, 7-3
ISA_MASTER, 2-39, 7-26
JTAG signals, 2-42, C-2
L2 cache interface signals, 2-19
LBCLAIM, 2-14, 4-21
LOCK, 2-36, 7-23
MAn, 2-29, 6-9
MCP, 2-14, 4-19, 9-3
MOLE, 2-29, 6-3
MPC106 PCIB/MC User's Manual
MOTOROLA
INDEX
MEMACK, 2-40, 7-27
memory interface, 2-26
NMI, 2-41, 9-5, 9-10
PAR (PCI parity), 2-37, 7-25
PARn (data parity/ECC), 2-30
PCI interface signals, 2-33
PCI sideband signals, 2-39, 7-26
PERR, 2-37, 7-26, 9-5
PLLn,2-44
PPEN, 2-30, 6-5
QACK, 2-41, 3-27, A-I
QREQ, 2-41, 3-27, A-I
RASn, 2-31, 6-6, 6-28
RCSO (ROM location configuration), 2-44, 6-59
RCSn (ROM bank select), 2-31
REQ, 2-37, 7-3
RTC, 2-31, 6-28, A-5
SDBAO,2-32
SDCAS,2-32
SDMAn,2-32
SDRAS,2-32
SERR, 2-38, 7-26, 9-5
signal connections, examples, 9-10
signal groupings, 2-2
STOP, 2-38, 7-8
SUSPEND, 2-42
SYSCLK, 2-42, 2-44
TA,2-15
TBST, 2-16, 4-13
TCK (JTAG test clock), 2-42, C-2
TOI (JrAG test data input), 2-43, C-2
TOO (JrAG test data output), 2-42, C-2
TEA, 2-16,4-19, 9-4
TMS (JrAG test mode select), 2-43, C-2
TOE, 2-23
TRDY, 2-38, 7-4
TRST (JrAG test reset), 2-43, C-2
TS,2-17
TSIZn, 2-17, 4-13
TIn, 2-18, 4-10
TV, 2-23, 5-10
TWE, 2-23, 5-24
WE, 2-33
WT, 2-18, 5-12
XATS, 2-19, 3-33, 4-20
Single-beat operations, 4-19
Single-beat transactions
SDRAM-based systems, 6-42, 6-50, 6-51
Single-beat transfer, see Transfer
Sleep mode
description, 1-6, A-4
memory refresh, 6-27
PCI interface support, 7-23
PMCR bit settings, 3-26
QREQ signal, 2-41, 3-27, A-I
MOTOROLA
Snooping
snoop push, 4-17
snoop response, 4-12, 4-17, 8-8
Split-bus transactions, 4-7
SRAMs
asynchronous SRAMs, 5-6, 5-39
pipelined burst SRAMs, 5-4
synchronous burst SRAMs, 5-3, 5-30
timing examples, 5-24-5-41
two-bank support, 5-7
Status register, PCI, 3-24, 7-16
STOP signal, 2-38, 7-8
Suspend mode
description, A-5
refresh, 2-31, 6-28, A-5
RTC signal, 2-31, 6-28, A-5
SUSPEND signal, 2-42
Synchronous burst SRAMs
CF_DOE bit, 3-62, 5-26
CF_WDATA bit, 3-62, 5-26
description, 5-3
L2 cache timing examples, 5-30
two-bank support, 5-7
SYSCLK (system clock) signal, 2-42, 2-44
System reset
HRST signal, 2-40, 9-3, A-2
initialization sequence, 6-44
system reset interrupt, 9-3
T
TA (transfer acknowledge) signal, 2-15
Target-abort error, 7-12, 9-10
Target-disconnect, see PCI interface
Target-initiated termination
description, 7-2, 7-12, 8-4
PCI status register, 7-12
TBST (transfer burst) signal, 2-16, 4-13
TCK (JTAG test clock) signal, 2-42, C-2
TOI (JrAG test data input) signal, 2-43, C-2
TOO (JTAG test data output) signal, 2-42, C-2
TEA (transfer error acknowledge) signal, 2-16,
4-19,9-4
Termination
60x address tenure, 4-6
60x data tenure, 4-6
completion, PCI transaction, 7-11
master-abort, PCI, 7-11, 9-9
normal termination, 4-19
target-disconnect, PCI, 7-2, 7-12, 8-4
target-initiated tennination, 7-12
termination by TEA, 4-19, 9-10
termination of PCI transaction, 7-11
timeout, PCI transaction, 7-11
transfer termination, 4-16
Index
Index-11
INDEX
Timeout, PCI transaction, 7-11
Timing diagrams
60x single-beatlburst data transfers, 4-19
acronyms in DRAM timing diagrams, 6-12
CBR refresh timing, SDRAM, 6-54
CF_L2_HlT_DELAY, 3-61, 4-5, 4-21,5-26
CF_WMODE, 5-27
DRAM RTC refresh in suspend mode, 6-28
DRAMIEDO
interface timing, 6-11
interface timing with ECC, 6-21
refresh, 6-25
self-refresh in sleep and suspend modes, 6-28
L2cache
burst read, 5-39
burst read line update, 5-40
burst write, 5-41
castout timing, 5-34
castout timing with no ARTRY, 5-35
hit following PCI read snoop, 5-36
invalidate following PCI read snoop, 5-38
push following PCI write snoop, 5-37
read hit timing, 5-31
update timing, 5-33
write hit timing, 5-32
legend for L2 interface timing, 5-30
ROM/Flash
burst read timing, 6-61
Flash memory write, 6-64
interface timing, 6-61
single-byte read, 6-62
SDRAM
burst-of-four read, 6-47
burst-of-four write, 6-48
mode-set command timing, 6-52
self-refresh entry, 6-55
self-refresh exit, 6-56
single-beat read, 6-50
single-beat write, 6-51
TMS (JTAG test modeselect) signal, 2-43, C-2
TOE (tag output enable) signal, 2-23
Turnaround cycle and PCI bus, 7-8
TV (tag valid) signal, 2-23, 5-10
TWE (tag write enable) signal, 2-23, 5-24
w
WE (write enable) signal, 2-33
Write-back
L2 cache response, 5-12
support for L2 cache operation, 5-2
write-back cache with MPCI06, 5-2
Write-through
L2 cache response, 5-20
support for L2 cache operation, 5-2
write-through cache with MPCI06, 5-2
Write-with-autoprecharge command, SDRAM, 6-45
WT (write-through) signal, 2-18, 5-12
X
XATS (extended address transfer) signal, 2-19,
3-33,4-20
Transactions
fast back-to-back transactions, PCI bus, 7-14
PCI bus transactions, 7-8
PCI transaction termination, 7-11
Transfer
60x address/data tenure, 4-6
aligned data transfer, 60x, 4-14
transfer termination, 4-16
TRDY (target ready) signal, 2-38, 7-3, 7-4, 7-11
TRST (JTAG test reset) signal, 2-43, C-2
TS (transfer start) signal, 2-17
TSIZn (transfer size) signals, 2-17, 4-13
TIn (transfer type) signals, 2-18, 4-10
Index-12
MPC106 PCIB/MC User's Manual
MOTOROLA
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Huntsville
Santa Clara
Wyle Electronics ............. (408)727-2500
Santa Fe Springs
Arrow/Schweber Electronics ... (205)837-£955
FAI .......................•. (205)837-9209
Future Electronics ............ (205)830-2322
Hamilton/Hallmark ........... (205)837-8700
Newark ............. " ...... (205)837-9091
Time Electronics ........... 1-£00-789-TIME
Wyle Electronics ............. (205)830-1119
ARIZONA
Phoenix
Newark ..................... (310)929-9722
Sierra Madre
PENSTOCK ................. (818)355-£775
Sunnyvale
Hamilton/Hallmark ........... (408)435-3500
PENSTOCK ................. (408)730-0300
Time Electronics ........... 1-800-789-TIME
Thousand Oaks
Newark ...........•......... (805)449-1480
FAI ...•..................... (602)731-4661
Future Electronics ............ (602)968-7140
Hamilton/Hallmark ..........•. (602)414-3000
Wyle Electronics .•........... (602)804-7000
Scottsdale
Alliance Electronics .......... (602)483-9400
Tempe
Arrow/Schweber Electronics ... (602)431-0030
Newark .... . . . . . . • . . . . . . . . .• (602)966-£340
PENSTOCK ........•........ (602)967-1620
Time Electronics ........... 1-£00-789-TIME
CALIFORNIA
Agoura Hills
Torrance
Time Electronics ........... 1-800-789-TIME
Tustin
Time Electronics ........... 1-800-789-TIME
Woodland Hills
Hamilton/Hallmark ........... (818)594-0404
COLORADO
Lakewood
FAI ......................... (303)237-1400
Future Electronics ............ (303)232-2008
Danver
Newark ..................... (303)373-4540
Englewood
Future Electronics ............ (818)865-0040
Time Electronics Corporale .. 1-800-789-TIME
Calabassas
Arrow/Schweber Electronics ..• (818)880-9686
Wyle ElectroniCS ............. (818)880-9000
Chatsworth
Time Electronics ..•........ 1-£00-789-TIME
Arrow/Schweber Electronics ... (303)799-0258
Hamilton/Hallmark ........... (303)790-1662
PENSTOCK ................. (303)799-7845
Time Electronics ........... 1-800-789-TIME
Thornton
Wyle Electronics ............. (303)457-9953
CONNECTICUT
Bloomfield
Newark ..................... (203)243-1731
Costa Mesa
Hamilton/Hallmark ........•.. (714)789-4100
CulverCltv
Hamilton/Hallmark ..••....... (310)558-2000
Garden Grove
Newark ..................... (714)893-4909
Irvine
Cheshire
FAI ......................... (203)250-1319
Future Electronics ............ (203)250-0083
Hamilton/Hallmark ........... (203)271-2844
Southbury
Time Electronics ........... 1-800-789-TIME
Arrow/Schweber Electronics •..
FAI ......•......•.........•.
Future Electronics .........•..
Wyle Laboratories Corporale ..
Wyle Electronics .•...........
(714)587-0404
(714)753-4778
(714)453-1515
(714)753-9953
(714)863-9953
Wallingfort
ArrowTSchweber Electronics ... (203)265-7741
FLORIDA
Altamonte Springs
Future Electronics ............ (407)865-7900
Clearwater
Los Angeles
FAI ....................•..•. (818)879-1234
Wyle Electronics ........•... , (818)880-9000
Manhattan Beach
FAI ......................... (813)530-1665
Future Electronics ............ (813)530-1222
Deerfield Beach
PENSTOCK ................. (310)546-£953
Newberry Park
PENSTOCK ........•...•..•. (805)375-£680
Palo Alto
Newark ...............•..... (415)812-£300
Riverside
Newark ..................... (909)980-2105
Rocklin
Hamilton/Hallmark ........... (916)632-4500
Sacramento
FAI .......... , ........•..•.. (916)782-7882
Newark ..•.................. (916)565-1760
Wyle Electronics •............ (916)638-5282
San Diego
Arrow/Schweber Electronics ...
FAI .........................
Future Electronics .......•.••.
Hamilton/Hallmark ...•.......
Newark ..•........•.....•..•
PENSTOCK .......•.........
Wyle Electronics .............
(619)565-4800
(619)623-2868
(619)625-2800
(619)571-7540
(619)453-8211
(619)623-9100
(619)565-9171
San Jose
Arrow/Schweber Electronics ...
Arrow/Schweber Electronics ...
FAI .........................
Fulure Electronics ....•...•...
(408)441-9700
(408)426-£400
(408)434-0369
(408)434-1122
Arrow/Schweber Electronics ... (305)429-8200
Wyle Electronics ............. (305)420-0500
Ft. Lauderdale
FAI ......................... (305)428-9494
Future Electronics . . . . . . . . . . .. (305)436-4043
Hamilton/Hallmark ........... (305)484-5482
Newark .•................... (305)488-1151
Time Electronics .......•... 1-800-789-TIME
Lake Mary
Arrow/Schweber Electronics ... (407)333-9300
Largo/Tampa/St. Petersburg
Hamilton/Hallmark ........... (813)547-5000
Newark ..................... (813)287-1578
Wyle Electronics ............. (813)576-3004
Time Electronics ........... 1-800-789-TIME
Orlando
FAI ....................•.... (407)865-9555
Newark ..................... (407)896-8350
Tallahassee
FAI .. . .. . .. .. .. . . .. . ... .. .. (904)668-7772
Tampa
Newark ..................... (813)287-1578
PENSTOCK ................. (813)247-7556
Winter Park
Hamilton/Hallmark ........... (407)657-3300
PENSTOCK .........•....... (407)672-1114
GEORGIA
Atlanta
FAI ............•............ (404)447-4767
Time Electronics ........ , .. 1-800-789-TIME
Wyle Electronics ............. (404)441-9045
Duluth
Arrow/Schweber Electronics ... (404)497-1300
Hamilton/Hallmark ........... (404)623-4400
Norcross
Future Electronics ............
Newark .....................
PENSTOCK .................
Wyle Electronics .•........•..
(770)441-7676
(770)448-1300
(770)734-9990
(770)441-9045
IDAHO
Boise
FAI ......................... (208)376-8080
Newark ..................... (208)342-4311
ILLINOIS
Addison
Wyle Laboratories . . . . . . . . . . .. (708)620-0969
Bensenville
Hamilton/Hallmark ..•........ (708)797-7322
Chicago
FAI ......................... (708)843-0034
Newark Electronics Corp... 1-800-4NEWARK
Hoffman Estates
Future Electronics ............ (708)682-1255
Itasca
Arrow/Schweber Electronics ... (708)250-0500
Palatine
PENSTOCK ...............•. (708)934-3700
Schaumburg
Newark .........•.•...•..... (708)310-8980
Time Electronics ........... 1-800-789-TIME
INDIANA
IndianapoliS
Arrow/Schweber Electronics . .. (317)299-2071
Bailey's Electronics .......•... (317)848-9958
Hamilton/Hallmark ........... (317)575-3500
FAI ......................... (317)469-0441
Future Electronics. . . . . . . . . . .. (317)469-0447
Newark ..................... (317)259-0085
Time Electronics ........... 1-800-789-TIME
Ft. Wayne
Newark ..................... (219)484-0766
PENSTOCK ................. (219)432-1277
IOWA
Cedar Rapids
Newark ..................... (319)393-3800
Time Electronics ..........• 1-800-789-TIME
KANSAS
Kansas City
FAI ......................... (913)381-£800
Lenexa
Arrow/Schweber Electronics .... (913)541-9542
Hamilton/Hallmark ........... (913)663-7900
Olathe
PENSTOCK ................. (913)829-9330
Overland Park
Future Electronics ............ (913)649-1531
Newark ...................•. (913)677-0727 .
Time Electronics ........... 1-800-789-TIME
MARYLAND
Baltimore
FAI ......................... (410)312-0833
Columbia
Arrow/Schweber Electronics ... (301 )596-7800
Future Electronics ............ (410)290-0600
Hamilton/Hallmark ......•.... (410)720-3400
Time Electronics ..•........ 1-800-789-TIME
PENSTOCK •................ (410)290-3746
Wyle Electronics ............. (410)312-4844
Hanover
Newark ..•.•..•............. (410)712-£922
For changes to this Information contact Technical Publications at FAX (602) 244-6560
1211196
AUTHORIZED DISTRIBUTORS- continued
UNITED STATES - continued
MASSACHUSETIS
Boston
Arrow/Schweber Electronics ... (508)658-0900
FAI ......................... (508)779-3111
Newark .................. 1-800-4NEWARK
Bolton
Future Corporate ............. (508)779-3000
Burlington
PENS'OCK ................. (617)229-9100
Wyle Electronics ............. (617)271-9953
Peabody
Time Electronics ........... 1-800-789-TIME
Hamilton/Hallmark ........... (508)532-9893
Woburn
Newark ..................... (617)935-8350
MICHIGAN
Detroit
FAI ......................... (313)513-0015
Future Electronics .....•...... (616)698-6800
Grand Rapids
Newark ..................... (616)954-6700
Livonia
Arrow/Schweber Electronics ... (810)455-0850
Future Electronics ............ (313)261-5270
Hamilton/Hallmark ........... (313)416-5800
Time Electronics ........... 1-800-789-TIME
Troy
Newark ..................... (810)583-2899
MINNESOTA
Bloomington
Hauppauge
Ft. Washington
Arrow/ScFiweber Electronics ... (516}231-1000
Future Electronics ............ (516}234-4000
Hamilton/Hallmark ..........• (516}434-7400
Newark .. '" ............. 1-800-4NEWARK
PENSTOCK ................. (516}724-9580
Konkoma
Hamilton/Hallmark ........... (516)737-0600
Long Island
FAI .......................•. (516}348-3700
Melville
Wyle Laboratories . . . . . . . . . . .• (516}293-8446
Pittsford
Newark .............. " ..... (716)381-4244
Wyle Electronics .............. (612)853-2280
PENSTOCK .................. (612)882-7630
Eden Prairie
Arrow/Schweber Electronics ... (612)941-5280
FAI .......... " '" .......... (612)947-0909
Future Electronics ... " .... '" (612)944-2200
HamiitonlHalimark ........... (612)881-2600
Time Electronics ........... 1-800-789-TIME
Minneapolis
Newark .•. . . . . . . . • . . . . . . . . .. (612)331-6350
Earth City
Hamilton/Hallmark ........... (314)291-5350
MISSOURI
St. Louis
Arrow/Schweber Electronics ... (314)567-6888
Future Electronics ..•......... (314)469-6805
FAI ......................... (314)542-9922
Newark ..................... (314}453-9400
Time Electronics ..•.... '" . 1-800-789-TIME
NEW JERSEY
Bridgewater
PEIiJSTOCK ................. (908}575-9490
Cherry Hill
Hamilton/Hallmark ........... (609}424-o110
East Brunswick
Newark . . . . . . . . . . . . . . . . . . . .. (908}937-6600
Fairfield
FAI ......................... (201}331-1133
Marlton
Arrow/Schweber Electronics. .. (609}598-6000
FAI ......................... (609}988-1500
Future Electronics ............ (609}596-4080
Plnebrook
Arrow/Schweber Electronics ... (201)227-7880
Wyle Electronics ............. (201 }882-8358
Parsippany
Future Electronics. . . • . . . . . • .. (201 }299-0400
Hamilton/Hallmark ........... (201)515-1641
Wayne
Time Electronics ........... 1-800-789-TIME
NEW MEXICO
Albuquerque
Hamilton/Hallmark ........... (505}828-1058
Newark ..................... (505)828-1878
NEW YORK
Bohemia
Philadelphia
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (609)439-9110
Pittsburgh
Arrow/Schweber Electronics ..• (412)963-6807
Newark ..................... (412}788-4790
Time Electronics ........... 1-800-789-TIME
TENNESSEE
Knoxville
Newark .....•.. . . . . . . . . . . . .. (615)588-6493
TEXAS
Arrow/Schwebe, Electronics ... (716}427-o300
Austin
Future Electronics ............ (716)387-9550
FAI ......................... (716)387-9600
Hamilton/Hallmark ........... (716}272-2740
Time Electronics ........ '" 1-800-789-TIME
Syracuse
FAI ......................... (315)451-4405
Future Electronics ............ (315}451-2371
Newark ..................... (315}457-4873
Time Electronics ........... 1-800-789-TIME
NORTH CAROLINA
Charlotte
Arrow/Schweber Electronics ... (919)876-3132
FAI ......................... (919)876-0088
Future Electronics .. '" .. '" .. (919)790-7111
Hamilton/Hallmark ........... (919)872-0712
Newark ....•.•........... 1-800-4NEWARK
Time Electronics ........... 1-800-789-TIME
OHIO
Centerville
Benbrook
Carollton
Arrow/Schweber Electronics ... (214)380-6464
Dallas
FAI ....................•.. " (214}231-7195
Future Electronics ............ (214)437-2437
Hamilton/Hallmark ........... (214}553-4300
Newark ..................... (214}458-2528
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (214)235-9953
EIPaso
FAI ......................... (915}577-9531
Newark ...............•..... (915}772-6367
Ft. Worth
Arrow/Schweber Electronics . .. (513}435-5563
Cleveland
FAI ......................... (216}446-o061
Newark ..................... (216}391-9330
Time Electronics ........... 1-800-789-TIME
Columbus
Newark ..................... (614)326-0352
Time Electronics ........... 1-800-789-TIME
Dayton
FAI ......................... (513)427-6090
Future Electronics ........... , (513)426-0090
HamiitonlHalimark ........... (513)439-6735
Newark ..................... (513)294-8980
Time Electronics ........... 1-800-789-TIME
Mayfield Heights
Future Electronics ............ (216)449-6996
Solon
Arrow/Schweber Electronics ... (216}248-3990
Hamilton/Hallmark ........... (216)498-1100
Worthington
Hamilton/Hallmark ........... (614)888-3313
OKLAHOMA
Tulsa
FAI ......................... (918}492-1500
Hamilton/Hallmark ........... (918}459-6000
Newark ..................... (918}252-5070
OREGON
Beaverton
Arrow/Almac Electronics Corp. .
Future Electronics ............
Hamilton/Hallmark ...........
Wyle Electronics .............
Arrow/Schweber Electronics ... (512)835-4180
Future Electronics ............ (512)502-0991
FAI •........................ (512}346-8426
Hamilton/Hallmark ........... (512}219-3700
Newark ... .. . . . . . . . .. . . . . . .. (972)458-2528
PENSTOCK ................. (512)348-9762
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (512}833-9953
PENSTOCK ................. (817)249-0442
FAI ......................... (704)548-9503
Future Electronics ............ (704)547-1107
Newark . . . . . . . . . . . . . . . . . . . .. (704)535-5650
(503}629-8090
(503)645-9454
(503}526-8200
(503)643-7900
Portland
FAI ......................... (503)297-5020
Newark ..................... (503)297-1984
PENSTOCK ................. (503)646-1670
Time Electronics ........... 1-800-789-TIME
PENNSYLVANIA
Coatesville
Newark ..................... (516}567-4200
Wyle Electronics ............. (609)439-9110
Rochester
Raleigh
Burnsville
Newark ..................... (215}654-1434
Mt. Laurel
PENSTOCK ................. (610)383-9536
Allied Electronics ............. (817)338-5401
Houston
Arrow/Schweber Electronics ... (713)647-6868
FAI ....•.........•.......... (713}952-7088
Future Electronics ............ (713)785-1155
Hamilton/Hallmark ........... (713)781-6100
Newark ................... " (713)894-9334
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (713}879-9953
Richardson
PENSTOCK ................. (214}479-9215
San Antonio
FAI ......................... (210}738-3330
Newark ........•...•........ (210}734-7960
UTAH
Salt Lake City
Arrow/Schweber Electronics ...
FAI ......•..................
Future Electronics ...•....•. "
Hamilton/Hallmark ...........
Newark .....................
Wyle Electronics .............
(801 )973-6913
(801 }467-9696
(801 }467-4448
(801}266-2022
(801}261-5660
(801}974-9953
West Valley City
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (801)974-9953
WASHINGTON
Bellevue
Almac Electronics Corp. . ..... (206)643-9992
PENSTOCK ................. (206)454-2371
Bothell
Future Electronics ............ (206)489-3400
Kirkland
Newark ... . .. .. .. . . .. . . . . . .. (206}814-6230
Redmond
Hamilton/Hallmark ........•.. (206)882-7000
Time Electronics ........... 1-800-789-TIME
Wyle Electronics ............. (206}881-1150
Seattle
FAI ..................•.....• (206}486-8616
Wyle Electronics ............. (206}881-1150
For changes to this Information contact Technical Publications at FAX (602) 244-6560
1211/96
AUTHORIZED DISTRIBUTORS - continued
UNITED STATES -continued
WISCONSIN
Brookfield
Saskatchewan
Arrow/Schweber Electronics ... (414)792-0150
Future Electronics ............ (414)879-0244
Wyle Electronics ............. (414)521-9333
Madison
Newark ..................... (608)278-0177
Milwaukee
FAI ......................... (414)792-9778
Time Electronics ........... 1-800-789-TIME
New Berlin
Hamilton/Hallmark ........ '"
Ottawa
Hamilton/Hallmark ........... (800)663-5500
(414)780-7200
Wauwatosa
Newark ..................... (414)453-9100
CANADA
ALBERTA
Calgary
Arrow Electronics ............
Electro Sonic Inc.............
FAI .........................
Future Electronics ............
Hamilton/Hallmark ...........
BRITISH COLUMBIA
Vancouver
Arrow Electronics ............
Electro Sonic Inc.............
FAI .........................
Future Electronics ............
Hamilton/Hallmark
(604)421-2333
(604)273-2911
(604)654-1050
(604)294-1166
(604)420-4101
Toronto
Arrow Electronics ............
Electro SoniC Inc.............
FAI .........................
Future Electronics ............
Hamilton/Hallmark ...........
Newark .....................
MANITOBA
Winnipeg
Electro S"onic Inc. ...........
FAI .... , ... , .. , ... , .........
Future Electronics ............
Hamilton/Hallmark ...........
(204)783-3105
(204)786-3075
(204)944-1446
(800)663-5500
PENSTOCK ... , ............. (613)592-8088
(403)255-9550
(403)291-5333
(403)250-5550
(800)663-5500
Edmonton
(905)670-7769
(416)494-1666
(905)612-9888
(905)612-9200
(905)564-6060
(905)670-2888
QUEBEC
Montreal
ONTARIO
Kanata
Electro Sonic Inc. ...........
FAI .........................
Future Electronics ............
Hamilton/Hallmark ...........
(613)226-5903
(613)728-8333
(613)820-8244
(613)727-1800
(613)226-1700
London
Newark ..................... (519)685-4280
Arrow Electronics ............
FAI .........................
Future Electronics ............
Hamilton/Hallmark ...........
(514)421-7411
(514)694-8157
(514)694-7710
(514)335-1000
Mt. Royal
Newark ..................... (514)738-4488
Mississauga
PENSTOCK ... , ...... , .... " (905)403-0724
Newark ..................... (905)670-2888
FAI ......................... (403)438-5888
Future Electronics ............ (403)438-2858
Hamilton/Hallmark ........... (800)663-5500
Quebec City
Arrow Electronics ............ (418)687-4231
FAI ......................... (418)682-5775
Future Electronics ............ (418)877-6666
INTERNATIONAL DISTRIBUTORS
AUSTRALIA
POLAND
GERMANY - continued
AVNET VSI Electronics (Aust.) .... (61)29878-1299
Veltek Australia Pty Ltd ..... (61)39574-9300
Sasco Semiconductor ......... (49) 89-46110
Spoerle Electronic .......... (49) 6103-304-0
GREECE
AUSTRIA
EBV Elektronik .............. (43) 1 8941774
SEI/Elbatex GmbH ............ (43) 1 866420
Spoerle Electronic ........... (43) 1 31872700
BELGIUM
Spoerle Electronic. . . . . . . . . .. (32) 2 725 4660
EBV Elektronik ............. (32) 2 716 0010
SEI/Rodelco B.V. ....•...... (32) 2 460 0560
BULGARIA
Macro Group ................. (359) 2708140
EBV Elektronik ............... (30) 13414300
HOLLAND
Spoerle Electronic .............. (42) 2731355
SEI/Elbatex .................. (42) 24763707
Macro Group ................. (42)23412182
CHINA
Advanced Electronics Ltd. . .. (852)2305-3633
AVNET WKK Components Ltd .... (852)2357-8888
China EI. App. Corp. XiaMan Co .. (86)106818-9750
Nance Electronics Supply Ltd .. (852) 2 765-3025
........................ or (852) 2 333-5121
Qing Cheng Enterprises Ltd ... (852) 2 493-4202
DENMARK
Arrow Exatec ............... (45) 44 927000
Avnet Nortec AlS ............ (45) 44 880800
EBV Elektronik ............... (45) 39690511
ESTONIA
Arrow Field Eesti .............. (372) 6503288
Avnet Baltronic ............... (372) 6397000
FINLAND
Arrow Field OY ............. (35) 89777571
Avnet NortecOY .......... '" (35) 89613181
FRANCE
Arrow Electronique .. . . . . .• (33) 1 49 78 49 78
Avnet Components. . . . . . .. (33) 1 49 65 25 00
EBV Elektronik ........... (33) 1 64 68 86 00
Future Electronics ............ (33)169821111
Newark .................... (33)1-30954060
SEI/Scaib .. . . . . . . . . . . . . .. (33) 1 69 19 89 00
GERMANY
Avnet E2000 ...............
EBV ElektronikGmbH .......
Future Electronics GmbH ....
SEI/Jermyn GmbH ..........
Newark ....................
(49) 89 4511001
(49) 89 99114-0
(49) 89-957270
(49) 6431-5080
(49)2154-70011
ROMANIA
Macro Group ................. (401) 6343129
RUSSIA
MacroGroup ................ (781)25311476
HONG KONG
AVNET WKK Components Ltd.... (852)2357-8888
Nanshing Clr. & Chern. Co. Ltd ... (852)2333-5121
SCOTLAND
EBV Elektronik ............ (44) 161 4993434
SINGAPORE
INDIA
INDONESIA
P.T.Ometraco ............. (62) 21 619-6166
IRELAND
Future Electronics ............. (65) 479-1300
Strong Pte. Ltd ............... (65) 276-3996
Uraco Technologies Pte Ltd..... (65) 545-7811
SLOVAKIA
Arrow ..................... (353) 14595540
Future Electronics ............. (353) 6541330
Macro Group ............... (353) 16766904
Macro Group ................. (42) 89634181
SLOVENIA
SEI/Elbatex ................ (48) 22 6254877
SPAIN
ITALY
AVNET EMG SRL ............ , (39) 2 381901
EBV Elektronik ............... (39) 2 660961
Future Electronics ............. (39) 2 660941
Silverstar Ltd. SpA ........... (39) 2 661251
JAPAN
AMSC Co., Ltd.............
Fuji Electronics Co., Ltd.....
Marubun Corporation .......
Nippon Motorola Micro Elec..
OM RON Corporation .......
Tokyo Electron Ltd. . . . . . . . ..
PORTUGAL
Amitron Arrow ............... (35) 114714806
EBV Elektronik ............ (31) 3465 623 53
Spoerle Electronic ..... , ...... (31) 4054 5430
SEI/Rodelco B.V. .......... (31) 7657 227 00
Canyon Products Ltd ....... (91) 80 558-7758
CZECH REPUBLIC
Macro Group ................ (48) 22 224337
SEI/Elbatex ................ (48) 22 6254877
Spoerle Electronic ........... (48) 22 6060447
81-422-54-8800
81-3-3814-1411
81-3-3639-8951
81-3-3280-7300
81-3-3779-9053
81-3-5561-7254
KOREA
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Avnet ........................ (371) 8821118
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Macro Group ................. (370) 7751487
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AVNET VSI (NZ) Ltd . . . .. .... (64)9635-7801
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Arrow Tahonic A/S ............ (47)22378440
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MPC106UMAD/AD
(Motorola Order Number)
9197
REV 1
Addendum to
MPC106 PCI Bridge/Memory Controller User's Manual:
MPC106 Revision 4.0 Supplement and User's
Manual Errata
This addendum to the MPCI06 PCI BridgelMemory Controller User's
Manual provides information on an enhanced revision of the MPC106 as
well as corrections to the user's manual.
This document is divided into two parts:
•
Part 1: The MPC106 PCI Bridge/Memory Controller Supplement
provides an overview of the MPC106 Rev. 4.0, with detailed
information about features that differ from those of the MPC106
described in the user's manual. This information is presented in the
same order as in the user's manual.
•
Part 2: Errata to MPC106 PCI BridgelMemory Controller User's
Manual contains corrections to the user's manual.
This document is designed to be used in conjunction with the user's manual.
In this document, the term '106' is used as an abbreviation for 'MPC106', the
term 'PCIB/MC' is used as an abbreviation for 'PCI bridge/memory
controller' , and the term '60x' is used to denote a 32-bit microprocessor
from the PowerPC® architecture family.
The PowerPC name is a registered trademark and the PowerPC logotype is a trademark of International Business Machines Corporation. used by
Motorola under license from International Business Machines Corporation.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or
discontinue this product without notice.
© Motorola Inc.•
1997. All rights reserved.
®
MOTOROLA
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.comlSPSlPowerPC/.
Part 1: The MPC106 Revision 4.0 Supplement
This section describes the details of the MPC106 Rev. 4.0. Any differences between the
Rev. 4.0 and previous revisions are noted.
1.1 Overview
Revision 4.0 adds new functionality to the MPC106 PCI Bridge/Memory Controller. This
document provides pertinent information regarding the new functionality and signal
changes brought about by the added features .
. 1.1.1 New Features
The primary features added to Rev. 4.0 of the MPC106 is support for 5:2 clock mode, 64Mbit JEDEC-compliant SDRAM devices, 16501 memory interface buffers, and an external
error checking module.
The following are new features, changes, and additions to the MPCI06 Rev. 4.0:
2
•
Supports 64-Mbit, 4- and 2-bank SDRAMs with 2 open pages simultaneously
•
Supports 16501-type memory interface buffers
•
Built-in performance monitor facility
•
Supports an external, in-line, error checking module (ECM)lbuffer for use with
SDRAM, including enhancements to the SDRAM error logging hardware for this
mode. This mode uses one additional pin-an error indicator signal from the ECM
is connected to the ISA_MASTERIBERR input signal. Note that the address that is
logged is the original requested address (the "critical word first" address), not the
exact doubleword.
•
Now supports 5:2 60xIPCI bus clock ratio
•
Two bits have been added to the BSTOPRE field so a page open value can be setthat
allows the MPC106 to operate in maximum open page mode.
•
Programmable 60x, memory, and PCI bus drivers
•
A timer (MCCR2[TS_WAIT_TIMER]) has been added to prevent contention
between ROM devices and other components in higher frequency systems
Addendum to MPC106 PCIBIMC User's Manual
1.2 Signals
With the addition of functionality, the MPC106 Rev. 4.0 has several changes to its signal
functions. Specifically, the external ECM, SDRAM interface, and configuration signals
have been added or changed on Rev. 4.0. This section describes the new/changed signals.
1.2.1 New Signal-External ECM Error Detect (BERR)-Input
The external ECM error detect (BERR) signal is an input on the MPC106 Rev. 4.0.
Following are the state meaning and timing comments for the BERR signal.
State Meaning
Asserted-Indicates that the external ECM has detected a parity or
ECC error.
Negated-Indicates that the external ECM has not detected any errors.
Timing Comments AssertionlNegation-Valid in the same clock cycle as data on the
destination bus (that is, the memory bus for writes, and the 60x bus for
reads).
Note that the 'i3'E'RR signal is multiplexed with the ISA_MASTER signal. Systems that use
the ISA_MASTER signal cannot use an external ECM. Also, the signal functions as BERR
only if external ECM mode is enabled. See the bit descriptions for
MCCR4[EXT_ECM_EN] in Table 10 for more information.
1.2.2 SDRAM Interface Signal Changes
With the addition of support for 64-Mbit SDRAM devices, the MPC106 Rev. 4.0 adds two
new SDRAM address signals, SDBAl/SDMAO and SDMAl. Table 1 shows the MPC106
Rev. 4.0 SDRAM interface signals as well as the suggested hook-up for a JEDEC standard
168-pin DIMM. Also shown in Table 1 are the memory signal assignments from previous
revisions of the MPC106.
Table 1. MPC106 Rev. 4.0 SDRAM Interface Signal Changes
MPC106 Pin
Number
MPC106 Rev. 4.0
SDRAM Interface
Function
MPC106 Rev. 3.0
SDRAM Interface
Function
MPC106 Rev.2.x
Function
168-Pin JEDEC
DIMMPin
J15
DQMO
DQMO
CASO
28
H15
DQM1
DQM1
CASf
29
G16
DQM2
DQM2
CAS2
46
E16
DQM3
DQM3
CAS3
4?
G14
DQM4
DQM4
CAS4
112
G13
DQM5
DQM5
CAS5
113
F14
DQM6
DQM6
CAS6
130
E14
DQM?
DQM?
CAS?
131
Addendum to MPC106 PCIB/MC User's Manual
3
Table 1. MPC106 Rev. 4.0 SDRAM Interface Signal Changes (Continued)
4
MPC106 Pin
Number
MPC106 Rev. 4.0
SDRAM Interface
Function
MPC106 Rev. 3.0
SDRAM Interface
Function
MPC106 Rev. 2.x
Function
168·Pin JEDEC
DIMM Pin
M14
CSO
CSO
RASO
30&45
of 1st socket
(BankO)
L13
CSf
CST
RAS1
114&129
of 1st socket
(Bank 1)
K13
CS2
CS2
RAS2
30&45
of 2nd socket
(Bank 2)
K14
CS3
CS3
RAS3
114&129
of 2nd socket
(Bank 3)
K12
CS4
CS4
RAS4
30 &45
of 3rd socket
(Bank 4)
L10
CS5
CS5
RAS5
114&129
of 3rd socket
(Bank 5)
J12
CS6
CS6
RAS6
30&45
of 4th socket
(Bank 6)
K11
CS7
CS7
RAS7
114& 129
of 4th socket
(Bank 7)
T15
WE
WE
WE
27
E13
Sl)CJ\$
SDCAS
MDLE
111
H10
SDRAS
SDRAS
PIRQ
115
J14
PPEN
PPEN
PPEN
-
J10
CKE
CKE
DBGLB
63& 128
N15
SDBA1/SDMAO
(depends on
4·bankor
2·bank operation)
(not used)
MAO
39 & 126
U16
SDBAO
SDBAO (bank
select)
MA1
122
P1
SDMA1
(not used)
XATS
123
T16
SDMA2
SDMA1
MA2
38
R16
SDMA3
SDMA2
MA3
121
Addendum to MPC1 06 PCIB/MC User's Manual
Table 1. MPC106 Rev. 4.0 SDRAM Interface Signal Changes (Continued)
MPC106 Pin
Number
MPC106 Rev. 4.0
SDRAM Interface
Function
MPC106 Rev. 3.0
SDRAM Interface
Function
MPC106 Rev. 2.x
Function
168-Pin JEDEC
DIMM Pin
P15
SDMA4
SDMA3
MA4
3?
P16
SDMA5
SDMA4
MA5
120
N16
SDMA6
SDMA5
MA6
36
M15
SDMA?
SDMA6
MA?
119
M16
SDMA8
SDMA?
MA8
35
L15
SDMA9
SDMA8
MA9
118
K15
SDMA10
SDMA9
MA10
34
11?
33
K16
SDMA11
SDMA10
MA11
J16
SDMA12
SDMA11
MA12
1.2.3 New Configuration Signals
MPC106 Rev. 4.0 has two new signals that are sampled during power-on reset to determine
the buffer configuration and clock phasing (for 5:2 clock mode). This section describes the
new signals sampled during power-on reset, and how they are configured. Weak pull-up or
pull-down resistors should be used to avoid interference with normal signal operations.
1.2.3.1 501-mode (8CTlO)-lnput
The SOl-mode configuration signal uses BCTLO as a configuration input. See Section 1.4.1,
"501 Buffer Mode," for more information. Following is the state meaning for the BCTLO
configuration signal.
State Meaning
High-Configures the MPC106 Rev. 4.0 to support backward
compatibility with MPCl06 Rev. 3.0 memory interface buffer
configurations.
Low-Configures the MPC106 Rev. 4.0 to support 16501-type
universal bus transceivers between the 60x/memory data bus.
Note that this input has an internal pull-up resistor to ensure backward compatibility as the
default configuration.
Addendum to MPC106 PCIB/MC User's Manual
5
1.2.3.2 60x Clock Phase (LBCLAIM)-Input
The 60x clock phase configuration signal uses LBCLAIM as a configuration input. Note
that if a system implements a local bus slave, the 60x clock phase input must be gated off
this signal during normal system operation. The 60x clock phase is only sampled during
power-on reset, hard reset, and when coming out of the sleep and suspend power saving
modes. Following is the state meaning for the LBCLAIM configuration signal.
State Meaning
High/Low-60x bus clock input to resolve clock phasing with the PCI
bus clock (SYSCLK) in 5:2 clock mode.
Note that this signal is only necessary when the PLL is configured for 5:2 clock mode.
1.2.4 Clocking
The MPC106 Rev. 4.0 requires a single system clock input, SYSCLK. The SYSCLK
frequency dictates the frequency of operation for the PCI bus. An internal PLL on the
MPC106 Rev. 4.0 generates a master clock that is used for all of the internal (core) logic.
The master clock provides the core frequency reference and is phase-locked to the
SYSCLK input. The 60x processor, L2 cache, and memory interfaces operate at the core
frequency.
The internal PLL on the MPCI06 Rev. 4.0 generates a core frequency either xl, x2, x2.5,
or x3 of the SYSCLK frequency (see Figure 1) depending on the clock mode configuration
signals (PLL[0-3]). New to Rev. 4.0 is the 2.5 multiplier (5:2 mode). The core frequency is
phase-locked to the rising edge of SYSCLK. Note that SYSCLK is not required to have a
50% duty cycle.
SYSCLK
(xi)
~
I
r
--.J
I
(x2)
(x3)
Figure 1. SYSCLK Input with Internal Multiples
The PLL is configured by the PLL[0-3] signals. For a given SYSCLK (PCI bus) frequency,
the clock mode configuration signals (PLL[0-3]) set the core frequency (and the frequency
of the VCO controlling the PLL lock). In the new 5:2 clock mode, the MPC106 Rev. 4.0
6
Addendum to MPC106 PCIB/MC User's Manual
needs to sample the 60x bus clock (on the LBCLAIM configuration input) to resolve clock
phasing with the PCI bus clock (SYSCLK).
The supported core and VCO frequencies and the corresponding PLL[0-3] settings are
provided in the MPCI06 PCI Bridge/Memory Controller Hardware Specifications.
1.3 Registers
Several configuration registers have changed as a result of the new functionality in the
MPC106 Rev. 4.0. This section describes those changes. Note that this section only
documents the new or changed programmable parameters. For bit descriptions of the
unchanged parameters, refer to Chapter 3, "Device Programming," of the MPCI06 PCI
BridgelMemory Controller User's Manual. Note that all internal registers are shown in
little-endian bit order.
1.3.1 PCI Command Register
The 16-bit PCI command register, shown in Figure 2, provides control over the ability to
generate and respond to PCI cycles.
[£l
Memory-Write·and-Invalidate - - - - - . . . ,
. - - - - - Special-Cycles
Parity Error Response - - - . . . ,
. . - - - Bus Master
Memory Space
SERR
Fast Back·to-Back
15 14 13
10 9
Reserved
I/O Space
8
7
6
5
4
3
2
1 0
Figure 2. PCI Command Register
Addendum to MPC106 PCIBIMC User's Manual
7
Table 2 describes the new Read_Lock bit of the PCl command register.
Table 2. Bit Settings for PCI Command Register-Ox04
Bit
14
Reset
Value
Name
Read_Lock
0
Description
PCI force read lock. This bit controls how the MPC1 06 Rev.4.0, as
a PCI target, treats PCI read transactions (memory-read,
memory-read-multiple, and memory-read-line) to system memory.
It is used to force a lock on PCI reads from system memory.
0 All PCI reads to system memory behave as on the MPC106
Rev. 3.0.
1 All PCI reads to system memory are treated internally as if the
PCI master had requested an exclusive access (that is, as if
the LOCK signal had been asserted). The MPC1 06 serializes
all PCI read transactions to system memory, and all snoops
are performed on the 60x bus as RWITM transfer types.
This bit should only be set in cases where address collisions are
known to cause erroneous transactions. Note that the Read_Lock
parameter is not defined in the PCI Local Bus Specification.
1.3.2 Performance Monitor Registers
The MPC106 Rev. 4.0 adds facilities to monitor selected system behavioral characteristics.
See Section 1.5, "Performance Monitor," for more information. This section describes the
registers implemented to support the performance monitor facilities. Table 3 shows the new
performance monitor registers.
Table 3. Performance Monitor Registers
Address
Offset
(in Hex)
Register
Size
ProgramAccessible
Size
48
4 bytes
2 or 4 bytes
Command register
Write-only
OxOOOO
4C
2 bytes
1 or 2 bytes
Mode control register
Read/write
OxOO
Performance Monitor Register
Register
Access
Default Value
50
4 bytes
4 bytes
Performance monitor counter 0
Read/write
OxOOOO
54
4 bytes
4 bytes
Performance monitor counter 1
Read/write
OxOOOO
58
4 bytes
4 bytes
Performance monitor counter 2
Read/write
OxOOOO
5C
4 bytes
4 bytes
Performance monitor counter 3
Read/write
OxOOOO
1.3.2.1 Performance Monitor Command Register (CMDR)-Ox48
The performance monitor command register (CMDR) is used to select the counter and the
events to be counted. The CMDR can be accessed as a two byte register at address offset
Ox48 or as a four byte register at address offset Ox48. It cannot be accessed as a 2-byte
register at address offset Ox4A. See Figure 3 and Table 4 for performance monitor
command register (CMDR) bit settings.
8
Addendum to MPC1 06 PCIBIMC User's Manual
o
Reserved
EVENT_L
31
2423
1615
13 12
8 7
6
5 4
a
Figure 3. Performance Monitor Command Register (CMDR)-Ox48
Table 4. Bit Settings for CMDR-Ox48
Bit
Name
Reset
Value
Description
31-24
THRESHOLD_L
OxOO
Threshold-lower byte. THRESHOLD_U II THRESHOLD_L define
the threshold value for PMCO and PMC1. See Section 1.5.2.3,
''Threshold Events;' for more information.
23-16
THRESHOLD_U
OxOO
Threshold-upper byte. THRESHOLD_U II THRESHOLD_L define
the threshold value for PMCO and PMC1. See Section 1.5.2.3,
"Threshold Events;' for more information.
15-13
EVENT_L
000
Event-low order bits. EVENT_U II EVENT_L determines which
events to count. See Section 1.5.2, "Performance Monitor Events;'
for more information.
12-8
-
00000
These bits are reserved
7-6
COUNTER
00
Counter select. These bits determine the counter to be
programmed.
00 PMCO
01 PMC1
10 PMC2
11 PMC3
5
CMD_TYPE
a
Command type. This bit determines the encoding for EVENT_U
and EVENT_L.
a Command type O. Events to count are selected according to
Table 12. See Section 1.5.2.1, "Command Type a Events;' for
more information.
1 Command type 1. Events to count are selected according to
Table 13. See Section 1.5.2.2, "Command Type 1 Events;' for
more information.
4-0
EVENT_U
00000
Event-high order bits. EVENT_U II EVENT_L determines which
events to count. See Section 1.5.2, "Performance Monitor Events;'
for more information.
Addendum to MPC106 PCIB/MC User's Manual
9
1.3.2.2 Performance Monitor Mode Control Register (MMCR)-Ox4C
The performance monitor mode control register (MMCR) is used to control performance
monitor operation. See Figure 4 and Table 5 for performance monitor mode control register
(MMCR) bit settings.
Reserved
OVFLOW 2-3
~~--,
DISCOUNT
~~-,
OVFLOWO-1
15 14 13
876 5
1 0
Figure 4. Performance Monitor Mode Control Register (MMCR)-Ox4C
Table 5. Bit Settings for MMCR-Ox4C
Bit
Name
Reset
Value
Description
15
OVFLOWO-1
0
Overflow PMCO into PMC1. Setting this bit allows PMCO and
PMC1 to be linked to become a 64·bit counter. See Section
1.5.2.5, "Counter Overflow," for more information.
0 Disable overflow from PM CO into PMC1.
1 Enable overflow from PMCO into PMC1.
Note that using counter overflow requires DISCOUNT = 0 and
PMCTRG =0.
14
OVFLOW2-3
0
Overflow PMC2 into PMC3. Setting this bit allows PMC2 and
PMC3 to be linked to become a 64·bit counter. See Section
1.5.2.5, "Counter Overflow," for more information.
0 Disable overflow from PMC2 into PMC3.
1 Enable overflow from PMC2 into PMC3.
Note that using counter overflow requires DISCOUNT = 0 and
PMCTRG =0.
13-8
-
All Os
These bits are reserved
7
ENABLE
0
Count enable. This bit enables the performance monitor facility.
0 Disable performance monitor event counting.
1 Enable performance monitor event counting.
6
DISCOUNT
0
Disable counter for msb set. This bit controls the behavior of the
counters when their msb (bit 7) changes from 0 to 1.
0 Counters continue to increment after their msb changes from 0
to 1.
1 PM CO stops when its msb changes from 0 to 1.
If PMCTRG = 0, PMC1, PMC2, and PMC3 stop when their
msb changes from 0 to 1.
If PMCTRG = 1, PMC1, PMC2, and PMC3 continue to
increment after their msb changes from 0 to 1.
5-1
-
All Os
These bits are reserved
10
Addendum to MPC106 PCIB/MC User's Manual
Table 5. Bit Settings for MMCR-ox4C (Continued)
Bit
0
Reset
Value
Name
PMCTRG
0
Description
Performance monitor counter trigger. This bit determines the
behavior of PMC1, PMC2, and PMC3 when the msb (bit 7) of
PMCO changes from 0 to 1.
0 Enable PMC1, PMC2, and PMC3 counting regardless of the
state of the msb of PMCO.
1 Disable PMC1, PMC2, and PMC3 counting until the msb of
PMCO changes from 0 to 1.
PMCTRG provides a triggering mechanism to allow counting after
a certain condition occurs or after a period of time has elapsed.
1.3.2.3 Performance Monitor Counters (PMCO, PMC1, PMC2,
PMC3)-Ox50, Ox54, Ox58, Ox5C
There are four performance monitor counter registers (PMCO, PMCl, PMC2, and PMC3)
that can be used to count events selected by the CMDR. Figure 5 shows an example of one
performance monitor counter (all four are similar with the exception of their respective
addresses).
D
MSB
LSB
31
Reserved
2423
16 15
8 7
o
Figure 5. Performance Monitor Counter (PMCn)
Note that although the counters use little-endian bit-ordering, the byte ordering is actually
big-endian (that is, the most-significant byte is located in bits 7-0, the next most-significant
byte is located in bits 15-8, the third most-significant byte is located in bits 23-16, and the
least-significant byte is in bits 31-24).
1.3.3 Output Driver Control Register (ODCR)-Ox73
Although not a new register, the output driver control register (ODCR) has not been
documented in the MPC106 PCl Bridge/Memory Controller User's Manual. The ODCR is
an 8-bit register located at address offset Ox73. See Figure 6 and Table 6 for output driver
control register bit settings.
Addendum to MPC106 PCIB/MC User's Manual
11
B
MEM_CTRL1
Reserved
PROC_A
DH_DL
PROC_CTRL1
PCI_CTRL
PROC_CTRL2
PCI_AD
~
I
MEM_CTRL2
~
I
I
I
I
I
I
7654321
I
I
o
Figure 6. Output Driver Control Register (ODCR)-Ox73
Table 6. Bit Settings for ODCR-Ox73
Bit
Name
Reset
Value
Description
7
PCLAD
1
PCI address/data signal driver control. This bit controls the drivers
for the PCI bus signals AD[31-O), C/BE[3-0), and PAR.
0 Indicates that the MPC1 06 has been configured for 40 Q PCI
AD signal drivers.
1 Indicates that the MPC106 has been configured for 20 Q PCI
signal drivers.
6
PCI_CTRL
1
PCI control signal driver control. This bit controls the drivers for
the PCI bus signals FRAME, IRDY, TRDY, DEVSEL, STOP, SERR,
PERR,REQ, and MEMACK.
0 Indicates that the MPC1 06 has been configured for 40 Q PCI
control signal drivers.
1 Indicates that the MPC1 06 has been configured for 20 Q PCI
control signal drivers.
5
DH_DL
0
Data bus signal driver control. This bit controls the drivers for the
processor/memory data bus signals DH[0-31) and DL[0-31).
0 Indicates that the MPC1 06 has been configured for 40 n data
bus signal drivers.
1 Indicates that the MPC1 06 has been configured for 20 Q data
bus signal drivers.
4
MEM_CTRL2
1
Memory signal driver control 2. This bit, along with MEM_CTRL 1,
controls the drivers for the memory control and address signals
MAlSDMA[0-12), PAR/AR[0-7], RAS/CS[Q-7), CAS/DQM[0-7),
WE, PPEN, FOE, RCS[0-1), DBGLB/CKE, PIRQ/SDRAS,
MDLE/SDCAS, and BCTL[0-1).
---MEM_CTRL
2
1
0
0
1
1
12
0
1
0
1
Memory
Bus Driver
Reserved
200
130
ao
Addendum to MPC106 PCIS/MC User's Manual
Table 6. Bit Settings for ODCR-Ox73 (Continued)
Bit
Name
Reset
Value
Description
3
PROC_A
1
Processor address bus signal driver control. This bit controls the
drivers for the processor address bus Signals A[0-31].
0 Indicates that the MPC106 has been configured for 40 0
processor address bus signal drivers.
1 Indicates that the MPC106 has been configured for 20 0
processor address bus signal drivers.
2
PROC_CTRL1
1
Processor/L2 control signal 1 driver control. This bit controls the
drivers for the processor/L2 control signals CKO, TS, AACK,
ARTRY, TA, TEA, BGn, DBGn, ADS, DOE, BAA, DCS, BAO,
OWEn, LBCLAIM, QACK, and MCP.
0 Indicates that the MPC106 has been configured for 40 0
processor/L2 control signal 1 drivers.
1 Indicates that the MPC106 has been configured for 20 0
processor/L2 control signal 1 drivers.
1
PROC_CTRL2
0
Processor/L2 control signal 2 driver control. This bit controls the
drivers for the processor/L2 control signals CT, WT, GBL, TBST,
TSIZ[0-2], TT[O-4], TWE, and TV.
0 Indicates that the MPC1 06 has been configured for 40 0
processor/L2 control signal 2 drivers.
1 Indicates that the MPC106 has been configured for 20 0
processor/L2 control signal 2 drivers.
0
MEM_CTRL1
1
Memory signal driver control 1. This bit, along with MEM_CTRL2,
controls the drivers for the memory control and address Signals
MAlSDMA[0--12], PAR/AR[0-7J, RAS/CS[0-7], CAS/DQM[0--7],
WE, PPEN, FOE, RCS[O-lJ, DBGLB/CKE, PIRQ/SDRAS,
MDLE/SDCAS, and BCTL[O-l].
----MEM_CTRL
1
2
0
0
1
1
Addendum to MPC106 PCIBIMC User's Manual
0
1
0
1
Memory
Bus Driver
Reserved
200
130
80
13
1.3.4 Memory Control Configuration Registers
The four 32-bit memory control configuration registers (MCCRs) set all RAM and ROM
parameters. These registers are programmed by initialization software to adapt the
MPC106 to the specific memory organization used in the system.
See Figure 7 and Table 7 for memory control configuration register 1 bit settings.
EIJ
Bank 7 Row
Bank 6 Row
PCKEN
Bank 5 Row
RAM_TYPE
Bank 4 Row
SREN
Bank 3 Row
MEMGO
BURST
8N64
501_MODE
I
ROMNAL
31
I
Reserved
ROMFAL
r-
11
1
Bank 1 Row
BankO
Row
~
IIIIIIII I I I I I I I I
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
28 27
Bank 2 Row
8
7
6
5
4
3
2
1
0
Figure 7. Memory Control Configuration Register 1 (MCCR1)-OxFO
Table 7. New Bit Settings for MCCR1-0xFO
Bit
22
14
Name
501 - MODE
Reset
Value
0
Description
Read only. This bit indicates the state of the 501-mode
configuration Signal (BCTLO) at power-on reset. See Section
1.2.3.1, "501-mode (BCTLO)-Input;' for a description of the 501mode configuration signal.
0 Indicates that the MPC1 06 has been configured for 16501type buffers
1 Indicates that the MPC106 has been configured for backward
compatibility
Note that the setting of 501_MODE and BUF_MODE (bit 1 of
MCCR2) determine the behavior of the buffer control signals
BCTL[0-1]. See Section 1.4.1, "501 Buffer Mode;' for more
information.
Addendum to MPC1 06 PCIS/MC User's Manual
Table 7. New Bit Settings for MCCR1-oxFO (Continued)
Bit
Name
Reset
Value
Description
15-14
Bank 7 row
00
RAM bank 7 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 7.
For DRAM/EDO configurations (RAM_TYPE = 1). the encoding is
as follows:
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
For SDRAM configurations (RAM_TYPE = 0). the encoding is as
follows:
00 14 row bits-64 Mbit 4 internal bank devices
01 14 row bits-64 Mbit 2 internal bank devices
10 Reserved
11 12 row bits-16 Mbit 2 internal bank devices
13-12
Bank 6 row
00
RAM bank 6 row address bit count. See the description for bits
15-14
11-10
Bank 5 row
00
RAM bank 5 row address bit count. See the description for bits
15-14
9-8
Bank 4 row
00
RAM bank 4 row address bit count. See the description for bits
15-14
7-6
Bank 3 row
00
RAM bank 3 row address bit count. See the description for bits
15-14
5-4
Bank 2 row
00
RAM bank 2 row address bit count. See the description for bits
15-14
3-2
Bank 1 row
00
RAM bank 1 row address bit count. See the description for bits
15-14
1-0
BankO row
00
RAM bank 0 row address bit count. See the description for bits
15-14
Addendum to MPC106 PCIBIMC User's Manual
15
See Figure 8 and Table 8 for memory control configuration register 2 (MCCR2) bit settings.
!:m
TS_WAIT_TIMER
Reserved
EEXT_ECM_ECC_EN - - - . . . ,
RMW_PAR - - - - ,
EXT_ECM_PAR_EN
BUF_MODE
BSTOPRE[0-1]
REFINT
31
22 21 20 19 18 17 16 15
29 28
2
1
0
Figure 8. Memory Control Configuration Register 2 (MCCR2)-oxF4
Table 8. New Bit Settings for MCCR2-oxF4
Bit
31-29
Name
TS_WAIT_TIMER
Reset
Value
000
Description
TS_WAIT_TIMER[0-2] controls the ROM output disable timing.
The minimum time allowed for ROM devices to enter high
impedance is 2 clocks. TS_WAIT_TIMER adds (n-1) clocks to the
minimum disable time. It has no effect on configurations that do
not use buffers so putting a slow ROM directly on the 60x bus at
higher clock frequencies is not recommended. Negative
additions (that is, setting TS_WAIT_TIMER[0-2] 1) do not
reduce the minimum enforced disable times. This delay is
enforced after all ROM and Flash accesses preventing any other
memory access from starting (for example DRAM after ROM
access, SDRAM after Flash access, ROM after Flash access,
etc.)
=
28--22
16
-
All Os
TS_WAIT
_TIMER
[0-2]
minimum
disable
time
@
@
66 MHz
83 MHz
000
001
010
011
100
101
110
111
2 clocks
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
8 clocks
30ns
30ns
45ns
60ns
75ns
90ns
105ns
120ns
24ns
24ns
36ns
48ns
60ns
72ns
84ns
96ns
These bits are reserved.
Addendum to MPC1 06 PCIBIMC User's Manual
Table S. New Bit Settings for MCCR2-0xF4 (Continued)
Bit
Name
Reset
Value
Description
21-20
BSTOPRE[0-1]
00
Burst to precharge-bits 0-1. For SDRAM only. These bits,
together with BSTOPRE[2-5] (bits 31-28 of MGGR3), and
BSTOPRE[6-9] (bits 3-0 of MGGR4), control the open page
interval. The page open duration counter is reloaded with
BSTOPRE[0-9] every time the page is accessed (including page
hits). When the counter expires, the open page is closed with an
SDRAM-precharge bank command. See Section 6.4.4, "SDRAM
Page Mode Retention," in the MGP106 User's Manual for more
information.
19
EXT_EGM_PAR_EN
0
External error checking module parity enable. This bit controls
whether the MPC106 uses an external error checking module to
generate, check, and report parity errors. Note that
EXT_EGM_EN (bits 23-22 of MGGR4) must be set to Ob11 to
enable the ex1ernal error checking module.
Ex1ernal module parity checking disabled
0
External module parity checking enabled
1
18
EXT_ECM_EGG_EN
0
External error checking module EGC enable. This bit controls
whether the MPG106 uses an external error checking module to
generate, check, correct, and report EGG. Note that
EXT_ECM_EN (bits 23-22 of MGGR4) must be set to Ob11 to
enable the ex1ernal error checking module.
External module EGG disabled
0
1
External module ECC enabled
I
See Figure 9 and Table 9 for memory control configuration register 3 (MCCR3) bit settings.
[J
31
28 27
24 23
20 19 1B
15 14
12 11
9
B
6
5
Reserved
3
2
o
Figure 9. Memory Control Configuration Register 3 (MCCR3)-OxFS
Addendum to MPC106 PCIB/MC User's Manual
17
Table 9. New Bit Settings for MCCR3-0xF8
Bit
31-28
Name
BSTOPRE[2-5]
Reset
Value
0000
Description
Burst to precharge-bits 2-5. For SDRAM only. These bits,
together with BSTOPRE[0-1] (bits 21-20 of MCCR2), and
BSTOPRE[6-9] (bits 3-0 of MCCR4), control the open page
interval. The page open duration counter is reloaded with
BSTOPRE[0-9] every time the page is accessed (including page
hits). When the counter expires, the open page is closed with an
SDRAM-precharge bank command. See Section 6.4.4, "SDRAM
Page Mode Retention;' in the MCP106 User's Manual for more
information.
See Figure 10 and Table 10 for memory control configuration register 4 (MCCR4) bit
settings.
EJ
Reserved
...----WCBUF
BSTOPRE[6-9]
RCBUF
SDMODE
31
28 27
24 23 22 21 20 19
8
7
4
3
o
Figure 10. Memory Control Configuration Register 4 (MCCR4)-OxFC
Table 10. New Bit Settings for MCCR4-0xFC
Bit
Name
23-22
EXT_ECM_EN
--
18
Reset
Value
00
Description
External error checking module enable. These bits enable the
external error checking module interface of the MPC106.
00 External error checking module disabled
01 Reserved
10 Reserved
11 External error checking module enabled
Note that both WCBUF and RCBUF must also be set to 1s to
enable the external error checking module. Note also that
EXT_ECM_PAR_EN (bit 19 of MCCR2) and EXT_ECM_ECC_EN
(bit 18 of MCCR2) should be used to enable parity and ECC
checking respectively when using an external ECM. PCKEN and
ECC_EN should be cleared to 0 when using an external ECM.
Addendum to MPC106 PCIB/MC User's Manual
Table 10. New Bit Settings for MCCR4-0xFC (Continued)
Bit
Name
Reset
Value
Description
19-8
SDMODE
All as
SDRAM mode register. For SDRAM only. These bits specify the
SDRAM mode register data to be written to the SDRAM array
during power-up configuration. Note that for 64-Mbit SDRAMs, the
SDMODE is actually a 14-bit field. The 2 most significant bits are
forced to a and concatenated to the SDMODE bits in this register.
Bit
Description
19-15 Opcode. For compliance with the JEDEC standard, these
bits are set to ObOOOOO for normal mode of operation and
to ObOOOOl for the JEDEC reserved test mode. All other
modes of operation are vendor-specific.
14-12 CAS latency
000 Reserved
001 1
010 2
all 3
100 4
101 Reserved
110 Reserved
111 Reserved
11
Wrap type
a
Sequential (Note that the sequential wrap type is
required for 60x processor-based systems)
1
Interleaved
10-8
Wrap length
000 Reserved
001 Reserved
010 4
all Reserved
100 Reserved
101 Reserved
110 Reserved
111 Reserved
3-0
BSTOPRE[6-9]
0000
Burst to precharge-bits 6-9. For SDRAM only. These bits,
together with BSTOPRE[O-I] (bits 21-20 of MCCR2), and
BSTOPRE[2-5] (bits 31-28 of MCCR3), control the open page
interval. The page open duration counter is reloaded with
BSTOPRE[0-9] every time the page is accessed (including page
hits). When the counter expires, the open page is closed with an
SDRAM-precharge bank command. See Section 6.4.4, "SDRAM
Page Mode Retention," in the MCP106 User's Manual for more
information.
Addendum to MPC106 PCIB/MC User's Manual
19
1.4 Memory Interface
With the addition of functionality, the MPC106 Rev. 4.0 has several changes to its memory
interface. Specifically, support for l6S0l-type bus transceivers has been added, and the
SDRAM interface operation has been improved. This section describes these new/changed
features.
1.4.1 501 Buffer Mode
The MPC106 Rev. 4.0 now supports l6S01-type universal bus transceivers. These devices
use different polarity on their control signals. The 106 uses a new SOl-mode configuration
signal (BCTLO) that alters the polarity of the buffer control signals to accommodate 16501type devices. Refer to Section 1.2.3.1, "50 I-mode (BCTLO)-Input," for more information.
The state of the SOl-mode configuration signal (BCTLO) at power-on reset can be read at
MCCRl[SOCMODE]. Note that MCCRl[SOCMODE] is a read-only bit. The setting of
the SOl_MODE and MCCR2[BUF_MODE] determine the behavior of the buffer control
signals BCTL[O-l] as shown in Table 11.
Table 11. 50CMODE Buffer Configuration
501_MODE
BUF_MODE
BCTLO
BCTL1
0
0
WE
RE
0
1
W/R
OE
1
0
WE
RE
1
1
RIW
OE
Note the polarity of the buffer control signals as indicated by an
overbar (that is, no overbar = active high, overbar = active low).
20
Addendum to MPC106 PCIB/MC User's Manual
Connections to 16501-type buffers should be made as shown in Figure 11.
~----------------------------------------~
~~,
:
1
1 OEAB ~
BCTLO -'---V~---
--
1
1
CI~B~_
60x Bus Clk ~ --
V-- -
: ~EAB
Gnd - -----------,
1
1
Gnd
60x Bus Clk
1
LEBA
[>>-___
l
ClkBA
--'--'----'----1
1
BCTL t _,--'~OE=BAcc.a
~-r:--+------+--+-----t-+--1
D
I
60x Data Bus A
•
1
>--~t---'
C
1
1
~~
",:
1-_,~~-+---C--lk
r---;
Memory
Data Bus
-+----<
1
1
L ________________________________________
1
~
Figure 11. 501-Type Buffer
1.4.2 SDRAM Interface Operation
The SDRAM interface of the MPClO6 Rev. 4.0 has been upgraded to support 64-Mbit, 4and 2-bank SDRAM devices with two open pages simultaneously. To support these
devices, another bank select (SDBAlISDMAO) and another address bit (SDMA1) have
been added to the SDRAM interface. Note that the big-endian memory address bits have
been relabeled to accommodate these changes. See Table 1 for the SDRAM interface signal
name changes.
1.4.2.1 SDRAM Initialization Changes
The encoding for the row bits for each bank (MCCR1, bits 15-0) has been modified to
allow configuring the MPClO6 for 64-Mbit, 4 internal bank devices, 64-Mbit, 2 internal
bank devices, and 16-Mbit, 2 internal bank devices.
Two bits have been added to the BSTOPRE field (MCCR2, bits 21-20) so a page open
value can be set that allows the MPC lO6 to operate in maximum open page mode. This
Addendum to MPC106 PCIBIMC User's Manual
21
means that a page can remain open until forced closed either by another access, refresh, or
by the expiration of PGMAX.
1.4.2.2 SDRAM Mode-Set Command Execution
For 64-Mbit SDRAMs, the mode-set command uses a 14-bit mode register data field
(SDMODE). On the MPC106 Rev. 4.0, the 2 most significant bits are forced to and
concatenated to the 12-bit MCCR4[SDMODE] parameter during mode-set command
execution.
°
1.5 Performance Monitor
The MPC106 includes a performance monitor facility that allows it to record/monitor
selected system behaviors. Four 32-bit performance monitor counters (PMCO, PMC!,
PMC2, and PMC3) in the MPC106 count the occurrence of software-selectable events. The
benefits of an on-board performance monitor are numerous, and include the following:
•
Since some systems or software environments are not easily characterized by signal
traces or benchmarks, the performance monitor can be used to understand the
MPC106's behavior in any system or software environment.
•
The performance monitor facility can be used to aid system developers when
bringing up and debugging systems.
•
In multiple processor (MP) systems, system performance can be increased by
monitoring memory hierarchy behavior. This can help to optimize algorithms used
to schedule or partition tasks and to refine the data structures and distribution used
by each task.
The performance monitor command register (CMDR) and the performance monitor mode
control register (MMCR) control the operation of all four counters. See Section 1.3.2,
"Performance Monitor Registers," for more information.
1.5.1 Performance Monitor Operation
Using the configuration registers discussed in Section 1.3.2, "Performance Monitor
Registers," the four performance monitor counters can be used to count the occurrences of
specific events. Up to four different events can be counted simultaneously using the four
different counters. The CMDR is used to select a specific counter and the events to be
counted. The MMCR is used to control the behavior of the counters.
There is only one CMDR to setup all four counters. The CMDR needs to be programmed
once for each counter. The CMDR[COUNTER] parameter specifies which counter is being
configured. If all four counters need to start at the same time, each counter is configured by
writing to the CMDR, and then counting is enabled by setting MMCR[ENABLE].
22
Addendum to MPC1 06 PCIBIMC User's Manual
CMDR[THRESHOLD_U] and CMDR[THRESHOLD_L] are used to specify the
threshold value for PMCO and PMCI threshold events. PMC2 and PMC3 do not support
threshold events, so a threshold value is meaningless for these counters. See Section 1.5.2.3,
"Threshold Events," for more information.
MMCR[OVFLOW 0_1] can be used to link PMCO to PMC1 effectively turning these two
32-bit counters into one 64-bit counter. Similarly, MMCR[OVFLOW 2_3] can be used to
link PMC2 to PMC3. See Section 1.5.2.5, "Counter Overflow," for more information.
1.5.2 Performance Monitor Events
There are two types of events that can be counted-command type 0 and command type 1.
The command type is selected by the CMDR[CMD_TYPE] parameter. The eight bit event
parameter, composed of CMDR[EVENT_U] II CMDR[EVENT_L], specifies which events
are counted. Depending on the command type selected, the meaning of the event parameter
varies.
Before describing performance monitor events, it is important to note how some terms are
defined. The following terms are used throughout this section:
End-of- data (EOD) EOD is the clock cycle of the last data transfer for a transaction. For
burst transactions, EOD occurs on the fourth assertion of TA. For
single-beat transactions EOD occurs on the first (and only) assertion
ofTA. Figure 12 shows example ofEOD for both burst and single-beat
transactions.
Pipelined
For processor transactions, pipelining occurs when TS is asserted
before the previous transaction's EOD. Figure 12 shows an example of
a pipelined processor transaction.
For memory transactions, pipe1ining occurs when the MPCI06
internally starts a system memory transaction before the previous
memory transaction has completed.
Addendum to MPC106 PCIB/MC User's Manual
23
Cycle
0
2
3
4
5
7
6
8
9
5
W
i
10
11
12
13
14
60x bus clock
I
I
I
I
rs:W
I
I
W
I
fA
I
EOD
I
I
I
I
I
\ 1
I 2
I 3
4
I
6
v
Pipelined for 6 Cycles
Transaction A is a burst transaction, therefore the EOO occurs on the fourth fA.
Transaction B is a single beat transaction, so the EOO occurs at the first and only fA.
Note that transaction B is a pipelined transaction, because the TS of transaction B comes
before the EOO of the previous transaction, A.)
Figure 12. Pipelined Processor Transaction and End-of-Data (EOD)
Processor latency
Processor latency is the number of clock cycles between, and
including, the assertion of TS and the first assertion of TA. For
pipelined transactions, latency is the number of clock cycles between,
and including, the clock cycle following the previous transaction's
EOD and the first assertion ofTA; refer to Figure 13.
o
Cycle
2
4
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SOx bus clock
TS
I
I
I
I
I
~~:--7-'\JLJ~:--~--7---~~---T--~--~~---7--~--7---~~--~
I
I
1
I
I
2
I 3
I
I
~
Latency = 3
I
~
Latency = 3
Transaction A shows a non-pipelined transaction. Transaction B shows a pipelined transaction.
Figure 13. Processor Latency
PCI latency
24
PCI latency is the number of PCI clock cycles between and including,
the assertion of FRAME and the first PCI clock cycle that data is valid
(IRDY and TRDY asserted); refer to Figure 14.
Addendum to MPC106 PCIBIMC User's Manual
60x bus clock
PCI clock
I
I
FRAME~
I
AID
1/
I
~------r-----'------r
~ AddreS~
C:
X
X'----'''--T--'
Wait:
X
Datal:
X Data~
\
IRDY
~
;-:
;-:
I
\
I
2
I
3
I
4
I
~------~---~
Latency=4
Latency is counted starting with the cycle FRAME is asserted and
counted until the first data is valid.
Figure 14. PCI Latency
1.5.2.1 Command Type 0 Events
Command type 0 events are specified with CMDR[CMD_TYPE] = O. Command type 0
events can only be counted in PMCO and PMC 1. (PMC2 and PMC3 cannot be used because
all command type 0 events are threshold events--see Section 1.5.2.3, "Threshold Events,"
for more information.) All command type 0 events are processor transactions.
There are 135 valid command type 0 events. Each of these events is defined by the
transaction type, destination, and transaction size bits shown in Table 12. There are three
possible transaction types (read, write, and read/write), fifteen possible destinations (L2,
system memory, PCI, and/or ROM), and three possible transaction sizes (burst, single-beat,
and burst/single-beat). Every command type 0 event must have at least one transaction type,
one destination, and one transaction size defined. Note that processor snoop copy-backs
and retried processor transactions are not counted.
Addendum to MPC106 PCIB/MC User's Manual
25
Table 12. Command Type o-Processor Transactions
CMDR Bit
EVENT_U
4
Name
READ
Description
Read transaction type bit. Enables counting of read transactions.
Disable counting of read transactions
1
Enable counting of read transactions
0
3
WRITE
Write transaction type bit. Enables counting of write transactions.
0
Disable counting of write transactions
1
Enable counting of write transactions
2
L2
L2 destination bit. Enables counting of transactions with the L2 as the
target.
Disable counting events targeted at the L2
0
1
Enable counting events targeted at the L2
Note that writes to the L2, in write-through cache mode, will only be
counted as transactions to memory.
1
MEMORY
Memory destination bit. Enables counting of transactions with system
memory as the target.
0
Disable counting events targeted at system memory
1
Enable counting events targeted at system memory
0
PCI
PCI destination bit. Enables counting of transactions with PCI as the target.
Disable counting events targeted at PCI
1
Enable counting events targeted at PCI
0
EVENT_L
15
ROM
14
BURST
ROM destination bit. Enables counting of transactions with ROM as the
target.
Disable counting events targeted at ROM
0
1
Enable counting events targeted at ROM
Burst transaction size bit. Enables counting of burst transactions.
Disable counting of burst transactions
1
Enable counting of burst transactions
0
13
SINGLE_BT
Single-beat transaction size bit. Enables counting of single beat
transactions.
0
Disable counting of single beat transactions
1
Enable counting of single beat transactions
1.5.2.2 Command Type 1 Events
Command type 1 events are specified with CMDR[CMD_TYPE] = 1. Command type 1
events are defined in Table 13. Most command type 1 events can be counted by all four
counters. However, as specified in Table 13, some events can only be counted in PMCO and
PMCl, and others are only countable in PMC2 and PMC3. Note that all events are counted
in 60x bus cycles, except PCI events which are counted in PCI cycles.
26
Addendum to MPC106 PCIB/MC User's Manual
Table 13. Command Type 1-Event Encodings
Event
(deCimal)
Event
(hex)
Counter
PMCn
Description
Processor Transactions
0
00
0,1,2,or3
Counter holds current value
1
01
0,1,2,or3
Number of 60x cycles
2
02
o or 1
TA overlap. Number of cycles from the TS to the last TA of the
previous transaction in pipelined situations. This is the period of time
marked 'Pipelined for 6 cycles' in Figure 12.
Note that the counter will increment only if the number of TA overlap
cycles is greater than the threshold value.
3
03
0,1,2,or3
Cache-inhibited transactions that are not retried
4
04
-
Reserved
5
05
0,1,2,or3
L2 castouts with no retry
6
06
0,1,2, or 3
Total L2 castouts
7
07
0,1,2,or3
sync and eieio instructions that are not retried
8
08
0,1,2,or3
Address-only transactions (sync, eieio, Kill, icbi, Clean, Flush, tlbi,
Iwarx, stwcx, tlbsync) that are not retried
9
09
o or 1
Number of cycles between BRO and BGO (qualified).
Note that the counter will increment only if the number of cycles from
a bus request until a bus grant is qualified, including the cycles the
signals are asserted, is greater than the threshold value.
10
OA
o or 1
Number of cycles between BR1 and BG1 (qualified).
Note that the counter will increment only if the number of cycles from
a bus request until a bus grant is qualified, including the cycles the
signals are asserted, is greater than the threshold value.
11
OB
0,1,2, or 3
Number of cycles that the 60x address bus is busy (includes all
address phases)
12
OC
0,1,2, or 3
Number of cycles that the 60x data bus is busy (includes all data
transfers)
13
00
0,1,2, or 3
Number of retries issued by the MPC106 on the 60x bus
14
OE
0,1,2, or 3
Number of retries issued by an alternate master (not including the L2)
on the 60x bus
15
OF
0,1,2, or 3
Number of retries issued to the MPC106 on the 60x bus
16
10
0,1,2,or3
Number of cycles that the memory interface is busy reading from
ROM
17
11
0,1,2, or 3
Number of cycles that the memory interface is busy reading from
system memory
18
12
0,1,2, or 3
Number of cycles that the memory interface is busy performing reads
and writes (from both system memory and ROM)
Addendum to MPC106 PCIBIMC User's Manual
27
Table 13. Command Type 1-Event Encodings (Continued)
Event
(decimal)
Event
(hex)
Counter
PMCn
19
13
°
20
14
°
21
15
°
or 1
or 1
or 1
Description
Number of cycles that an L2 castout or a processor burst write with
ECC enabled has to wait for the L2 castout buffer
Note that the counter will increment only if the number of cycles an L2
castout or a processor burst write with ECC enabled has to wait for
the L2 castout buffer is greater than the threshold value.
Number of cycles that the processor waits while a PCI transaction is
occurring
Note that the counter will increment if the number of cycles the
processor waits while a PCI transaction is occurring is greater than
the threshold value.
Burstiness for processor transactions. PMCO will count the number of
times there are X transactions in a row with an acceptable latency of Y
cycles.
Note that this event involves PMCO and PMC1. See Section 1.5.2.4,
"Burstiness," for more information.
PCI Transactions
28
32
20
0,1,2,or3
33
21
°
34
22
0,1,2,or3
Number of PCI read and write to memory commands (memory-read,
memory-read-line, and memory-read-multiple, memory-write and
memory-write-invalidate)
35
23
0,1,2,or3
Number of data beats read by external PCI master
36
24
0,1,2,or3
Number of data beats read and written by external PCI master
37
25
0,1,2, or 3
Number of PCI memory-read-line commands
38
26
0,1,2, or 3
Number of PCI memory-read-multiple commands
39
27
0,1,2,or3
Number of PCI reads from ROM space
40
28
0,1,2,or3
Number of PCI memory-write-and-invalidate commands
41
29
0,1,2,or3
Number of speculative PCI read snoops
42
2A
0,1,2,or3
Number of PCI read and speculative PCI read snoops
43
2B
0,1,2,or3
Number of PCI write, PCI read, and speculative PCI read snoops
or 1
Number of PCI cycles
Number of PCI read from memory commands (memory-read,
memory-read-line, and memory-read-multiple)
Note that the counter will increment if the number of cycles from the
start of the transaction until the first data is greater than the threshold
value.
Addendum to MPC106 PCIBIMC User's Manual
Table 13. Command Type 1-Event Encodings (Continued)
Event
(decimal)
Event
(hex)
Counter
PMCn
44
2C
0,1,2, or 3
Number of PCI reads that hit in the PC I-to system-memory-readbuffer (PCMRB) while the MPC1 06 is still trying to fill it after a
disconnect.
When a PCI read is attempted but the latency exceeds 32 PCI cycles,
the MPC106 must disconnect as required by the PCI specification.
The MPC1 06 assumes that the PCI master will return with a request
to the same address and continues the line fill from system memory.
Event 44 occurs if the PCI master issues a read command to the
same cache line, while the line fill is still in progress
45
2D
0, 1,2, or 3
Number of PCI reads that hit in the PCMRB while the MPC1 06 is still
busy performing a speculative fetch of that line
46
2E
O,1,2,or3
Number of PCI reads that hit in the PCMRB
47
2F
0,1,2, or 3
Number of PCI reads that hit modified cache lines in a processor's L1
cache
48
30
O,1,2,or3
Number of PCI reads and PCI writes that hit modified cache lines in a
processor's L 1 cache
49
31
0,1,2, or 3
Number of PCI transactions that disconnected at the end of a cache
line
50-59
32-3B
-
Reserved
60
3C
0,1,2, or 3
Number of cycles that FRAME is asserted
61
3D
O,1,2,or3
Number of cycles that IRDY is asserted
62
3E
O,1,2,or3
Number of cycles that TRDY is asserted
Description
System Memory Transactions
80
50
20r3
Number of pipelined read misses to page 0
81
51
2or3
Number of pipelined read and write misses to page 0
82
52
20r3
Number of non-pipelined read misses to page 0
Number of non-pipelined read and write misses to page 0
83
53
20r3
84
54
20r3
Number of pipelined read hits to page 1-SDRAM only
85
55
2or3
Number of pipelined read and write misses to page 1-8DRAM only
86
56
2or3
Number of non-pipelined read misses to page 1-8DRAM only
87
57
2or3
Number of non-pipelined read and write misses to page 1-SDRAM
only
88
58
20r3
Number of pipelined read hits to page 0
89
59
2or3
Number of pipelined read and write hits to page 0
90
5A
20r3
Number of non-pipelined read hits to page 0
91
5B
2or3
Number of non-pipelined read and write hits to page 0
Addendum to MPC106 PCIBIMC User's Manual
29
Table 13. Command Type 1-Event Encodings (Continued)
Event
(decimal)
Event
(hex)
Counter
PMCn
92
5C
20r3
Number of pipelined read hits to page 1-50RAM only
93
50
20r3
Number of pipelined read and write hits to page 1-S0RAM only
94
5E
20r3
Number of non-pipelined read hits to page 1-50RAM only
95
5F
2or3
Number of non-pipelined read and write hits to page 1-S0RAM only
96
60
20r3
Number of forced closings for page 0 (excluding refreshes)
97
61
20r3
Number of forced closings for page 1 (excluding refreshes)-50RAM
only
98
62
20r3
Total number of misses to page 0 and page 1, pipelined and nonpipelined
99
63
20r3
Total number of hits to page 0 and page 1, pipelined and nonpipelined
100
64
20r3
Total number of forced closings for page 0 and page 1
Description
1.5.2.3 Threshold Events
The intent of threshold support is to be able to characterize events that can take a variable
number of cycles to occur. Threshold events are only counted if the latency is greater than
the threshold value (CMDR[THRESHOLD_U] II CMDR[THRESHOLD_LD. Figure 15
shows an example of a command type 0 event with threshold.
Note that PMCO and PMCI are the only counters that support counting threshold events.
PMC2 and PMC3 do not support threshold events
Cycle
o
2
3
4
o
2 I 3
0
5
6
7
8
9
10 I 11
I
I
12 I 13
I
14 I
I
Clock
x
I
These two transactions (a non-pipelined transaction 'A' and a pipelined transaction '6')
both have a latency of 3. Therefore they will both be counted as events if the
threshold value is 0, 1, or 2 (that is, X> CMDR[THRESHOLD_Ulll CMDR[THRESHOLD_L]).
Figure 15. Command Type 0 Threshold Example
There are seven command type 1 threshold events (events 2, 9, 10, 19,20,21 and 33). The
event descriptions in Table 13 describe how threshold is used for those events.
30
Addendum to MPC1 06 PCIBIMC User's Manual
1.5.2.4 Burstiness
Burstiness is a special command type 1 event that involves both PMCO and PMC}. When
configured correctly, it enables PMCO to count the number of times there are at least X
transactions in a row with an acceptable latency of Y clock cycles between any two
transactions. For example, burstiness can count the number of times there are 1,000 writes
to PCI in a row, each with less than or equal to 9 cycles of latency between them.
To count burstiness, PMCO is configured to count the command type 0 processor
transaction(s) of interest (see Table 12). The threshold of PMCO is set to be the minimum
number of consecutive transactions desired (referred to as X above). PMC} is configured
to count command type 1 event 21 (see Table 13). The threshold of PMCI is set to the
acceptable latency desired (referred to as Y above). Note that the latency to the first
transaction is not considered.
Figure 16 shows a simple example that counts the number of times at least three processor
transactions are in a row with an acceptable latency of five between them. In this example,
X is 3 and Y is 5 (that is the acceptable latency is s; 5 cycles). For this example, X is the
threshold of PMCO and Y is the threshold of PMC 1. Since burstiness does not actually use
PMC1, it may be useful to set MMCR[OVFLOW 0_1] to allow overflow counting into
PMC1. PMCO operates as a normal command type 0 event until PMCI is configured for
command type 1 event 21.
Addendum to MPC106 PCIB/MC User's Manual
31
Clock
EOD
PMCO
Event
Threshold
CountPMCO
Ae'
Be'
Ce'
' , , , , , , , , , '-,--'---'--'--'--'---'---'-~'--'-~-i--'-
~..:..o__________
PMC1
Event
Threshold -'----'--'----'7\i-"i_:_'r.:_,r.:_,r-:;i-:"i_:_\r.:_,r.-,;.:-li-:~/_:;I/_;_,;7\i_::1i_:_'/_;_,r.:_,r::;i_:_,i_::_\i_'---'-_'_::~f_:_,Ir.:_,;--'--'--_'_:,/_;_,r::;;---'---'---'::,1-711::
CountPMC1 ,-,-,,~~~~J~~~~~/~~~~JP'~~~~~f~~/~"-T~I~-''-~~~~-''-~~
PMCO_O_____________J"r_________________- .____________________~~_
3 Transactions Each with
Latency < 5, so Count
Start Counting Again,
Acceptable Latency was not Met
PMCO Threshold = 3
(X, Minimum Number of Transactions)
PMCO:
Command Type = 0, Event = OxFF, Threshold = Ox0003
PMC1 Threshold = 5
(Y, Acceptable Latency)
PMC1 :
Command Type = 1, Event = Ox21, Threshold = Ox0005
NOTE: Since X is the minimum number of transactions, even if 2,000 transactions occur each with an
acceptable latency of 5, then the value in PMCO will still only be 1. The acceptable latency has to be
violated before the counter can be eligible to increment again.
Figure 16. Processor Burstiness Example
1.5.2.5 Counter Overflow
The counters can be configured as 64-bit counters by setting MMCR[OVFLOW 0_1] for
PMCO and PMCI or MMCR[OVFLOW 2_3] for PMC2 and PMC3. Figure 17 shows a
diagram of PMCO and PMCI configured to utilize overflow. Note that using counter
overflow requires MMCR[DISCOUNT] = 0 and MMCR[PMCTRG] = o.
Carry-out
G-I~
PMC1
7
o 15
8 23
16 31
24
7
PMCO
o 15
8 23
16 31
24
Figure 17. Overflow Example
32
Addendum to MPC106 peIB/MC User's Manual
Part 2: Errata to MPC106 PCI Bridge/Memory Controller
User's Manual
This section describes corrections to the MPCI06 PCI Bridge/Memory Controller User's
Manual. For convenience, the section number and page number of the errata item in the
user's manual are provided.
Errata 1
The manual incorrectly describes the address range for local bus slave accesses as restricted
to the space from 1 Gbyte to 2 Gbytes. In fact, the local bus slave can claim any address in
the 4-Gbyte address space.
Changes
Section/Page
3.2.7,3-54
Replace the description for PICR1 [CF_LBA_EN] (bit 13) in
Table 3-35 with the following:
Table 3-35. Bit Settings for PICR1-0xA8
Bit
13
Name
CF_LBA_EN
Reset
Value
0
Description
Local bus slave access enable. This bit controls whether the
MPC106 responds to the LBCLAIM signal (and therefore local bus
slave accesses). When this bit is cleared, the MPC1 06 ignores the
LBCLAIM signal. See Section 4.4.5, "60x Local Bus Slave Support,"
for more information.
Local bus slave access is disabled.
0
1
Local bus slave access is enabled.
Errata 2
The manual incorrectly documents the memory interface signal buffering, including the
polarity of the BCTLO signal when the BUF_MODE parameter is set to 1, and the
registered buffer configuration for DRAMIEDO systems. The error affects Table 6-1,
"Buffer Configurations," and Section 6.2.1, "Flow-Through Buffers" (specifically the
manner in which 5417416245,54174162245, and 54174163245, flow-through type buffers
are connected to the 60x and memory data buses).
Addendum to MPC106 PCIB/MC User's Manual
33
Section/Page
Changes
6.2,6-2
Replace Table 6-1 with the following:
Table 6-1. Buffer Configurations
WCBUF
RCBUF
BUF_MODE
0
0
0
0
0
0
1
6.2.1,6-3
Typical
Buffer
Device
BeTlO
BCTl1
Flow-through
WE
RE
5417416863
1
Flow-through
DIR
(R/W)
OE
54/7416245
54/74162245
54174163245
0
Transparent latch
(DRAM/EDO)
WE
RE
5417416543
54174162543
Registered
(DRAM/EDO)
WE
RE
5417416952
54174162952
5417416601
Buffer Type
0
1
1
-
DIR
(R/W)
OE
-
1
0
0
-
WE
RE
-
1
0
1
-
DIR
(R/W)
OE
-
1
1
0
Registered
(SDRAM)
WE
RE
5417416952
54174162952
5417416601
1
1
1
-
DIR
(R/W)
OE
-
Replace the first sentence of the second paragraph with the following:
The default protocol (BUF_MODE = 1) uses BCTLO as a direction
control signal (reads active high/writes active low), and BCTLl as a
buffer output enable signal (active low).
34
Addendum to MPC1 06 PCIB/MC User's Manual
Section/Page
Changes
Replace Figure 6-1 with the following:
6.2.1,6-3
BCTLO--'
,
DIR
,
,
Memory data
~__~L_"""
__
-i
~-
A:
,
,
---,
I
«
II
,
,
L ________________________
'
•
60xdata
B
~
Figure 6-1. Flow-Through Buffer
Errata 3
The manual neglected to include a connection example for 16601-type registered
transceivers.
Section/Page
6.2.3,6-5
Changes
Replace the figure title for Figure 6-3 with '16952-Type Registered
Buffer'.
Addendum to MPC106 PCIBIMC User's Manual
35
Section/Page
Changes
6.2.3,6-5
Add the following after Figure 6-3:
~-----------------------------------------~
:
BCTlO -;--
5417416601
OEAB_c{:>_
I
I
Gnd_~~lla~- - - - - - - - - - 60x Bus Clk
:
ClkAB
[>>--
I
Gnd
-~~B.{>-
--=]
I
Gnd-+-~-I
ICI~
60x Bus Clk ---~-Gnd
BCTl1
_~ ClkEna~
I
_+_i>i.l3~
I
60x Data Bus
V-
---f
A,
I I---J
~
:4
I
---<
----
I
I
L
~
CE
D
C
.----
I--
~{1
B
Memory
Data Bus
>-1-- I> Clk
CE ----<
L-
D
C
--mISPSiPeweFP{;/
http://www.mot.com/SPSIRISC/netcomml
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