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MPRH01TSU-02_603_604_Reference_Design_2.1_Aug95 MPRH01TSU-02_603_604_Reference_Design_2.1_Aug95

User Manual: MPRH01TSU-02_603_604_Reference_Design_2.1_Aug95

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PowerPC 603/604 Reference

Design Technical Specification

This document provides a detailed

technical description of the PowerPC

603/604 Reference Design. It is in-

tended as a first source of information

for both hardware and software de-

signers. Where appropriate, other

documents are referenced.

Document Number:

MPRH01TSU-02

August, 9 1995

Release 2.1

2MPRH08TSU-02

 International Business Machines Corporation, 1995. Printed in the United States of America 8/95. All Rights

reserved.

IBM Microelectronics, PowerPC, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, RISCWatch,

and AIX are trademarks of the IBM corporation. IBM and the IBM logo are registered trademarks of the IBM

corporation. Other company names and product identifiers are trademarks of the respective companies.

This document contains information which is subject to change by IBM without notice. IBM assumes no re-

sponsibility or liability for any use of the information contained herein. Nothing in this document shall operate

as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The

products described in this document are not intended for use in implantation or other direct life-support ap-

plications where malfunction may result in physical harm or injury to persons. NO WARRANTIES OF ANY

KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR

FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.

Contacts

USA and Canada:

IBM Microelectronics Division

1580 Route 52, Bldg. 504

Hopewell Junction, NY 12533-6531

Tel: (800) PowerPC

Fax: (800) PowerFax

Japan:

IBM

800, Ichimiyake

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Shiga–ken, Japan 520–23

Tel: (81) 775–87–4745

Fax: (81) 775–87–4735

Europe:

IBM

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( from Paris add 16)

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Laatzener Str. 1

30539 Hannover, Germany

Tel: (49) 511–516–3444 (English)

(49) 511–516–3555 (Deutsche)

Fax: (49) 511–516–3888

ESD Warning

The motherboard and memory cards contain CMOS devices which are very susceptible

to ElectroStatic Discharge (ESD). DO NOT remove them from the antistatic bags until you

have connected yourself to an acceptable ESD grounding strap. Work in a static free envi-

ronment and be sure any person or equipment coming into contact with the cards do not

have a static charge. The cards are particularly susceptible until they are placed in a prop-

erly designed enclosure. Bench work should be done by persons connected to ESD

grounding straps.

MPRH08TSU-02

IBM POWERPCTM 603/604 REFERENCE DESIGN AGREEMENT

BEFORE READING THE REST OF THE DOCUMENT, YOU SHOULD CAREFULLY READ THE FOLLOWING TERMS

AND CONDITIONS. OPENING THE PACKAGE INDICATES YOUR ACCEPTANCE OF THESE TERMS AND CONDI-

TIONS. IF YOU DO NOT AGREE WITH THEM, YOU SHOULD PROMPTLY RETURN THE PACKAGE UNOPENED TO

YOUR IBM SALES OFFICE.

International Business Machines Corporation (”IBM”) agrees to provide you a PowerPC 603/604 Reference Design (Reference Design)

in return for your promise to use reasonable efforts to develop a system based on the technology in the Reference Design. The Reference

Design contains documentation and software listed below:

Documentation

PowerPC 603e RISC Microprocessor Hardware Specification

PowerPC 603e RISC Microprocessor Technical Summary

PowerPC 603/604 RISC Microprocessor Hardware Specification

PowerPC 603/604 Reference Design Technical Specification

IBM PowerPC 603/604 Reference Board Design Files (on 8mm tape)

IBM PowerPC 604 Reference Board Mfg. Data Files (in Gerber format)

IBM14N1372 Data Sheet

IBM11D4360B Data Sheet

Motorola MPC970 Data Sheet

Altera 5130 Data Sheet

Integrated Device Technology IDT71216 Data Sheet

LICENSE TO SOFTWARE

The software is licensed not sold. IBM, or the applicable IBM country organization, grants you a license for the software only in the country

where you received the software. Title to the physical software and documentation (not the information contained in such documentation)

transfers to you upon your acceptance of these terms and conditions. The term ”software” means the original and all whole or partial copies

of it, including modified copies or portions merged into other programs. IBM retains title to the software. IBM owns, or has licensed from

the owner, copyrights to the software provided under this agreement. The terms of this Agreement apply to all of the hardware, software

and documentation provided to you as part of the Reference Design.

With regard to the software provided hereunder, it is understood and agreed that you intend to use the software solely for the purpose of

designing PowerPC compatible products, testing your designs, and making your own independent determination of whether you wish to

eventually manufacture PowerPC compatible products commercially. In accordance with this understanding, IBM hereby grants you the

rights to: a) use, run, and copy the software, but only make such number of copies and run on such number of machines as are reasonably

necessary for the purpose of designing PowerPC compatible products and testing such designs; and b) copy the software for the purpose

of making one archival or backup copy.

With regard to any copy made in accordance with the foregoing license, you must reproduce any copyright notice appearing thereon. With

regard to the software provided hereunder, you may not: a) use, copy, modify or merge the software, except as provided in this license;

b) reverse assemble or reverse compile it; or c) sell, sublicense, rent. lease, assign or otherwise transfer it. In the event that you no longer

wish to use the software, you will return it to IBM.

LICENSE TO DESIGN DOCUMENTATION

With regard to the design documentation provided hereunder, it is understood that you intend to use such documentation solely for the pur-

pose of designing your own PowerPC compatible products, testing your designs, and making your own independent determination of wheth-

er you wish to eventually manufacture PowerPC compatible products commercially. In accordance with this understanding, IBM hereby

grants you the right to: a) use the design documentation for the purpose of designing PowerPC compatible products and testing such de-

signs; b) make derivative works of the design documentation for the purpose of designing PowerPC compatible products, and testing such

designs; and c) make copies of the design documentation and any such derivative works, but only such numbers as are reasonably neces-

sary for designing PowerPC compatible products and testing such designs.

With regard to any copy made in accordance with the forgoing license, you must reproduce any copyright notice appearing thereon. With

regard to the design documentation provided hereunder, you may not: a) use, copy, modify, or merge the design documentation as provided

in this license; or b) sell, sublicense, rent, lease, assign, or otherwise transfer it.

In the event you no longer wish to use the design documentation or any derivative versions thereof, you must return them to IBM.

DISCLAIMER OF WARRANTY

IBM does not represent or warrant that the Reference Design (which may contain prototype items): a) meets any particular requirements;

b) operates uninterrupted; c) is error free; or d) is non–infringing of any patent, copyright, or other intellectual property right of any third party.

IBM makes no representation or warranty regarding the performance or compatibility that may be obtained from the use of the Reference

Design or that the Reference Design is adequate for any use. The Reference Design may contain errors and may not provide the level

of completeness, functionality, support, performance, reliability, or ease of use available with other products, whether or not similar to the

Reference Design. IBM does not represent or warrant that errors or other defects will be identified or corrected.

THE REFERENCE DESIGN IS PROVIDED ”AS IS” WITH ALL FAULTS, WITHOUT WARRANTY OF ANY KIND, EX-

PRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND

FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE

REFERENCE DESIGN IS WITH YOU.

Some jurisdictions do not allow exclusion of implied warranties, so the above exclusions may not apply to you.

4MPRH08TSU-02

LIMITATION OF REMEDIES

IBM’s entire cumulative liability and your exclusive remedy for damages for all causes, claims or actions wherever and whenever asserted

relating in any way to the subject matter of this agreement including the contents of the Reference Design and any components thereof,

is limited to twenty five thousand dollars ($25,000.00) or its equivalent in your local currency and is without regard to the number of items

in the Reference Design that caused the damage. This limitation will apply, except as otherwise stated in this Section, regardless of the

form of the action, including negligence. This limitation will not apply to claims by you for bodily injury or damages to real property or tangible

personal property. In no event will IBM be liable for any lost profits, lost savings, or any incidental damages or economic consequential dam-

ages, even if IBM has been advised of the possibility of such damages, or for any damages caused by your failure to perform your responsibi-

lities. In addition, IBM will not be liable for any damages claimed by you based on any third party claim. Some jurisdictions do not allow these

limitations or exclusions, so they may not apply to you.

RISK OF LOSS

You are responsible for all risk of loss or damage to the Reference Design upon its delivery to you.

IBM TRADEMARKS AND TRADE NAMES

This Agreement does not give you any rights to use any of IBM’s trade names or trademarks. You agree that should IBM determine that

any of your advertising, promotional, or other materials are inaccurate or misleading with respect to IBM trademarks or trade names, that

you will, upon written notice from IBM, change or correct such materials at your expense.

NO IMPLIED LICENSE TO IBM INTELLECTUAL PROPERTY

Notwithstanding the fact that IBM is hereby providing design information for your convenience, you expressly understand and agree that,

except for the rights granted under sections 1 and 2 above, no right or license of any type is granted, expressly or impliedly, under any pat-

ents, copyrights, trade secrets, trademarks, or other intellectual property rights of IBM. Moreover, you understand and agree that in the

event you wish to be granted any license beyond the scope of the expressly stated herein, you will contact IBM’s Intellectual Property Licens-

ing and Services Office (currently located at 500 Columbus Avenue, Thornwood, N.Y.), or such other IBM offices responsible for the licens-

ing of IBM intellectual property, when you seek the license.

YOUR ASSUMPTION OF RISK

You shall be solely responsible for your success in designing, developing, manufacturing, distributing, and marketing any product(s), or

portion(s), where use of all or any part of the Reference Design is involved. You are solely responsible for any claims, warranties, represen-

tations, indemnities and liabilities you undertake with your customers, distributors, resellers or others, concerning any product(s) or por-

tion(s) of product(s) where use of all or any part of the Reference Design is involved. You assume the risk that IBM may introduce other

Reference Design that are somehow better than the Reference Design which is the subject of this Agreement. Furthermore, you accept

sole responsibility for your decision to select and use the Reference Design; for attainment or non-attainment of any schedule, performance,

cost, reliability, maintainability, quality, manufacturability or the like, requirements, or goals, self–imposed by you or accepted by you from

others, concerning any product(s) or portion(s) of product(s), or for any delays, costs, penalties, charges, damages, expenses, claims or

the like, resulting from such non-attainment, where use of all or any part of the Reference Design is involved.

GENERAL

In the event there is a conflict between the terms of this Agreement and the terms printed or stamped on any item or any ambiguities with

respect thereto, including documentation, contained in the Reference Design, the terms of this Agreement control to the extent IBM is af-

forded greater protection thereby. IBM may terminate this Agreement if you fail to comply with the terms and conditions of this Agreement.

Upon termination of this Agreement, you must destroy all copies of the software and documentation. You are responsible for payment of

any taxes, including personal property taxes, resulting from this Agreement. Neither party may bring an action hereunder, regardless of form,

more than one (1) year after the cause of the action arose. If you acquired the Reference Design in the United States, this Agreement is

governed by the laws of the State of New York. In the event of litigations, trial shall be in New York without a jury. If you acquired the Refer-

ence Design in Canada, this Agreement is governed by the laws of the Province of Ontario; otherwise, this Agreement is governed by the

laws of the country in which you acquired the Reference Design. All obligations and duties which, by their nature, survive termination or

expiration of this Agreement, shall remain in effect beyond termination or expiration of this Agreement, and shall bind IBM, you and your

successors and assigns. If any section or paragraph of this Agreement is found by competent authority to be invalid, illegal or unenforceable

in any respect for any reason, the validity, legality, and enforceability of any such section or paragraph in every other respect, and the remain-

der of this Agreement, shall continue in effect so long as it still expresses the intent of the parties. If the intent of the parties cannot be pre-

served, the parties will attempt to renegotiate this Agreement and failing renegotiation, this Agreement will then be terminated. The headings

in this Agreement shall not affect the meaning or interpretation of this Agreement in any way. No failure by IBM in exercising any right, power

or remedy under this Agreement shall serve as a waiver of any such right, power or remedy. Neither this Agreement nor any activities here-

under will impair any right of IBM to develop, manufacture, use or market, directly or indirectly, alone or with others, any products or services

competitive with those offered or to be offered by you; nor will this Agreement or any activities hereunder require IBM to disclose any busi-

ness planning information to you. You agree to comply with all applicable government laws and regulations. Any changes to this Agreement

must be in writing and signed by the parties.

MPRH08TSU-02

Table of Contents

Section 1 Introduction 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 IBM Reference Products 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 Reference Design 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Reference Board 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.3 Reference Firmware 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.4 Reference System 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Purpose 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Reference Design Overview 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 The CPU 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2 IBM27-82660 Bridge 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.3 L2 Cache 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.4 System Memory 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.5 PCI Bus 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.6 Flash ROM 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.7 ISA Bus 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.8 Time of Day Clock 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.9 PS/2t Compatible Keyboard/Mouse Controller 21. . . . . . . . . . . . . . . . .

1.3.10 System Clocks 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.11 System I/O EPLD 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Quickstart Peripheral List 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Reference Design Level 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2 CPU and CPU Bus 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 CPU Bus Masters 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 603e CPU 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 604 CPU 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 System Response by CPU Bus Transfer Type 26. . . . . . . . . . . . . . . . . . . . .

2.3 System Response by CPU Bus Address Range 28. . . . . . . . . . . . . . . . . . . .

2.3.1 Address Mapping for Non-Contiguous I/O 28. . . . . . . . . . . . . . . . . . . . . .

2.3.2 Address Mapping for Contiguous I/O 30. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 PCI Final Address Formation 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 CPU to Memory Transfers 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 LE Mode 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 CPU to PCI Transactions 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 CPU to PCI Read 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 CPU to PCI Write 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2.1 Eight-Byte Writes to the PCI (Memory and I/O) 31. . . . . . . . . . . . . . . . .

2.5.3 CPU to PCI Memory Transactions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 CPU to PCI I/O Transactions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.5 CPU to PCI Configuration Transactions 32. . . . . . . . . . . . . . . . . . . . . . . .

2.5.5.1 Preferred Method of Generating PCI Configuration Transactions 32.

6MPRH08TSU-02

2.5.5.2 650 Bridge compatible method 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.6 CPU to PCI Interrupt Acknowledge Transaction 33. . . . . . . . . . . . . . . . .

2.5.7 PCI Lock 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 CPU to ROM Transfers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 CPU to ROM Read 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 CPU to ROM Write 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2.1 ROM Write Protection 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 CPU to BCR Transfers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3 PCI Bus 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 PCI Transaction Decoding 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 PCI Transaction Decoding By Bus Command 36. . . . . . . . . . . . . . . . . . .

3.1.2 PCI Memory Transaction Decoding By Address Range 36. . . . . . . . . . .

3.1.3 PCI I/O Transaction Decoding 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 ISA Master Considerations 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 PCI Transaction Details 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Bus Snooping on PCI to Memory Cycles 39. . . . . . . . . . . . . . . . . . . . . . .

3.2.2 PCI to PCI Peer Transactions 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 PCI to System Memory Transactions 39. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Bus Arbitration Logic 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Other PCI Considerations 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 4 ISA Bus 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 The ISA Bridge 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Address Ranges 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 ISA Bus Concurrency 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 ISA Bus Masters and IGN_PCI_AD31 44. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 DMA 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1 Supported DMA Paths 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 DMA Timing 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3 Scatter-Gather 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 X-Bus 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.1 Control Signal Decodes 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.2 Keyboard/Mouse Controller 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.3 Real Time Clock (RTC) 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.4 PCI Adapter Card Presence Detect Register 47. . . . . . . . . . . . . . . . . . . .

4.6.5 L2 SRAM Identification Register 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.6 Planar ID Detection Register 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.7 DRAM Presence Detection 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.7.1 DRAM SIMM 1-2 Memory ID Register 49. . . . . . . . . . . . . . . . . . . . . . . . .

4.6.7.2 DRAM SIMM 3-4 Memory ID Register 49. . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Miscellaneous 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7.1 Speaker Support 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 5 System I/O EPLD 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 System Register Support 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPRH08TSU-02

5.1.1 External Register Support 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2 Internal Registers 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2.1 Storage Light Register 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2.2 Power Management Control Register 1 52. . . . . . . . . . . . . . . . . . . . . . .

5.1.2.3 Power Management Control Register 2 53. . . . . . . . . . . . . . . . . . . . . . .

5.1.2.4 Freeze Clock Register (FCR) Low 53. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2.5 Freeze Clock Register (FCR) High 53. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Signal Descriptions 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 EPLD Design Equations 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.1 Fit File 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.2 TDF File 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 6 Memory Systems 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 DRAM 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 Refresh 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 DRAM Presence Detection 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.3 Organization 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 L2 Cache 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 SRAM 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2 TagRAM 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.3 L2 Cache Configuration 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 ROM 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 CPU to ROM Transfers 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.1 CPU to ROM Read 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.2 CPU to ROM Write 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.2.1 ROM Write Protection 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 7 Endian Mode Considerations 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 What the 603/604 CPU Does 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 What the 660 Bridge Does 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Bit Ordering Within Bytes 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Byte Swap Instructions 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 603/604 CPU Alignment Exceptions In LE Mode 80. . . . . . . . . . . . . . . . . . .

7.6 Single–Byte Transfers 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Two–Byte Transfers 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 Four–Byte Transfers 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 Three byte Transfers 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.10 Instruction Fetches and Endian Modes 89. . . . . . . . . . . . . . . . . . . . . . . . . . .

7.11 Changing BE/LE Mode 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.12 Summary of Bi–Endian Operation and Notes 92. . . . . . . . . . . . . . . . . . . . . .

Section 8 Exceptions 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Interrupts 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.1 System Interrupt Handler 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.2 Interrupt Handling 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8MPRH08TSU-02

8.1.3 Interrupt Assignments 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1.4 Scatter-Gather Interrupts 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Error Handling 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1 Data Error Checking 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1.1 CPU to Memory Writes 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1.2 CPU to Memory Reads 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1.3 PCI to Memory Parity Errors 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1.4 CPU to PCI Transaction Data Parity Errors 97. . . . . . . . . . . . . . . . . . . .

8.2.2 Illegal CPU cycles 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.3 SERR, I/O Channel Check, and NMI Logic 97. . . . . . . . . . . . . . . . . . . . . .

8.2.4 Out of Bounds PCI Memory Accesses 97. . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.5 No Response on CPU to PCI Cycles – Master Abort 98. . . . . . . . . . . . .

8.2.6 CPU to PCI Cycles That Are Target Aborted 98. . . . . . . . . . . . . . . . . . . .

8.2.7 Error Status Registers 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.8 Reporting Error Addresses 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.9 Errant Masters 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.10 Special Events Not Reported as Errors 99. . . . . . . . . . . . . . . . . . . . . . . . .

Section 9 System Setup and Initialization 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 CPU Initialization 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 660 Bridge Initialization 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 ISA Bridge (SIO) Initialization 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.1 Summary of SIO Configuration Registers 106. . . . . . . . . . . . . . . . . . . . . . .

9.4 PCI Configuration Scan 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.1 Multi-function Adaptors 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4.2 PCI to PCI Bridges 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5 Reference Design Combined Register Listing 108. . . . . . . . . . . . . . . . . . . . . .

9.5.1 Direct Access Registers 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5.2 Indexed BCR Summary 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6 ISA Bus Register Suggestions 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 10 System Firmware 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 Introduction 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 Power On System Test 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2.1 Hardware Requirements 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Boot Record Format 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1 Boot Record 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1.1 PC Partition Table Entry 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1.2 Extended DOS Partition 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1.3 PowerPC Reference Platform Partition Table Entry 122. . . . . . . . . . . . .

10.3.2 Loading the Load Image 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 System Configuration 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.1 System Console 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.2 System Initialization 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.3 Main Menu 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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10.4.3.1 System Configuration Menu 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.3.2 Run a Program 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.3.3 Reprogram Flash Memory 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.3.4 Exit Options 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.4 Default Configuration Values 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 11 Electromechanical 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Electrical 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.1 Power Requirements 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.2 Onboard 3.3V Regulator 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.3 Onboard 2.5V Regulator 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 Thermal 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1 Thermal Requirements for the 603/604 Processor 139. . . . . . . . . . . . . . .

11.2.1.1 604 Fan-Sink Installation 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1.2 604 Fan-Sink Experimentation 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1.3 Thermal Requirements for the 3.3V Regulator 140. . . . . . . . . . . . . . . . .

11.3 Mechanical 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.1 Reference Design Board Mechanical 141. . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.2 Connector Locations 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.3 Connector Locator Diagram 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.4 Keyboard Connector J14 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.5 Mouse Connector J15 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.6 Speaker Connector J13 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.7 Power Good LED/KEYLOCK# Connector J12 145. . . . . . . . . . . . . . . . . . .

11.3.8 HDD LED Connector J11 (1 x 2 Berg) 145. . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.9 Reset Switch Connector J10 (1 x 2 Berg) 146. . . . . . . . . . . . . . . . . . . . . . .

11.3.10 Fan Connector J9 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.11 3.3V Power Connector J5 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.12 Power Connector J4 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.13 AUX5/ON-OFF Connector J6 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.14 PCI Connectors J25, J26, and J27 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.15 ISA Connectors J29, J30, J31, J32, and J33 150. . . . . . . . . . . . . . . . . . . .

11.3.16 SIMM Connectors J21, J22, J23, and J24 152. . . . . . . . . . . . . . . . . . . . . .

11.3.17 Power Switch Connector J8 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.18 Power Up Configuration Connector J7 154. . . . . . . . . . . . . . . . . . . . . . . . .

11.3.19 L2 Cache Data SIMM Connector J3 155. . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.20 RISCWatch Connector J19 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.21 Battery Connector BT2 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3.22 Reference Design Board Connector Footprint #1 158. . . . . . . . . . . . . . . .

11.3.23 Reference Design Board Connector Footprint #2 159. . . . . . . . . . . . . . . .

11.4 Enclosure 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 12 Physical Design Guidelines 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 General Considerations 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.1 Construction 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 MPRH08TSU-02

12.1.2 General Wiring Guidelines 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Clock Nets 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 CPU Bus Nets 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4 Timing Critical Nets 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.5 PCI Bus Nets 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.6 Group 2A: Noise Sensitive Wires 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.7 8mm Tape Contents and Extract Instructions 168. . . . . . . . . . . . . . . . . . . . . .

12.7.1 Download Instructions 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.7.2 Cadence Version 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.7.3 Tape Contents 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 13 Errata for Reference Design Release 2.1 169. . . . . . . . . . . . . . . . . . . . .

13.1 PowerPC 603/604 Reference Design Roadmap 169. . . . . . . . . . . . . . . . . . . .

13.2 Release 2.1 Board Level Errata 171. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.1 Driving 32MB 72-pin DRAM SIMMs 171. . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.2 CPU Data Bus 33 Ohm Series Resistors 171. . . . . . . . . . . . . . . . . . . . . . .

13.3 Reference Design Errata for Revision 1.1 of the 660 Bridge 172. . . . . . . . .

13.3.1 Workaround Implementation 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3.2 HPP1 Reference Design Workaround PAL 172. . . . . . . . . . . . . . . . . . . . . .

13.3.3 HCn Reference Design Workaround PAL 173. . . . . . . . . . . . . . . . . . . . . . .

13.3.4 HBROOM Reference Design Workaround PAL 175. . . . . . . . . . . . . . . . . .

13.4 660 Bridge Revision 1.1 Errata, 8/9/95 Release 177. . . . . . . . . . . . . . . . . . . .

13.4.1 Individual 66 Bridge Errata 177. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.2 IPAL Design Files 182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.2.1 HPP1 Design File 182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.2.2 C3 PAL Design File 184. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.2.3 Broom PAL Design File 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.3 Workaround PAL Installation 188. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 14 Bill of Materials 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1 603e/604 Reference Design Bill of Materials 189. . . . . . . . . . . . . . . . . . . . . . .

14.1.1 603e Bill of Materials 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.1.2 604 Bill of Materials 194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 15 Schematics 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.1 Reference Board Component Placement 200. . . . . . . . . . . . . . . . . . . . . . . . . .

Section 16 Selected Component Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPRH08TSU-02

Figures

Figure 1. 603/604 Reference Design Block Diagram 20. . . . . . . . . . . . . . . . . . .

Figure 2. Non-Contiguous PCI I/O Address Transformation 29. . . . . . . . . . . . .

Figure 3. Non-Contiguous PCI I/O Address Translation 29. . . . . . . . . . . . . . . . .

Figure 4. Contiguous PCI I/O Address Translation 30. . . . . . . . . . . . . . . . . . . . .

Figure 5. Typical External Register 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 6. DRAM Bank Organization 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 7. Synchronous SRAM, 256K L2 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 8. Synchronous SRAM, 512K L2 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 9. Synchronous SRAM, 1M L2 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 10. Asynchronous SRAM, 256K L2 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 11. Asynchronous SRAM, 512K L2 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 12. Asynchronous SRAM, 1M L2 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 13. Synchronous TagRAM, 512K L2 72. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 14. Synchronous TagRAM, 1M L2 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 15. Endian Mode Block Diagram 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 16. Example at Address XXXX XXX0 80. . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 17. Example at Address XXXX XXX2 81. . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 18. Double Byte Write Data ab at Address XXXX XXX0 84. . . . . . . . . . .

Figure 19. Word (4-Byte) Write of 0a0b0c0dh at Address XXXX XXX4 84. . . . .

Figure 20. Instruction Alignment Example 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 21. Wrong Instruction Read When Unmunger is used 90. . . . . . . . . . . . .

Figure 22. Instruction Stream to Switch Endian Modes 91. . . . . . . . . . . . . . . . . . .

Figure 23. Interrupt Handling 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 24. PCI Interrupt Connections 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 25. Boot Record 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 26. Partition Table Entry 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 27. Partition Table Entry Format for an Extended Partition 122. . . . . . . . .

Figure 28. Partition Table Entry for PowerPC Reference Platform 122. . . . . . . . .

Figure 29. PowerPC Reference Platform Partition 123. . . . . . . . . . . . . . . . . . . . . . .

Figure 30. System Initialization Screen 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 31.Configuration Utility Main Menu 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 32. System Configuration Menu 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 33. System Information Screen 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 34. Device Configuration Screen 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 35. SCSI Devices Screen 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 36. Boot Devices Screen 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 37. Set Date and Time Screen 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 38. Run a Program Screen 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 39. Reprogram the Flash Memory Screen 134. . . . . . . . . . . . . . . . . . . . . . .

Figure 40. 604 Heat Sink Assembly 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 41. Connector Location Diagram 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 MPRH08TSU-02

Figure 42. The Keyboard Connector 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 43. The Mouse Connector 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 44. 1x4 Speaker Connector 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 45. 1x5 Power Good LED Connector 145. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 46. 1x2 HDD LED Connector 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 47. 1x2 Reset Switch Connector 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 48. 1x2 Fan Connector 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 49. 1x6 3.3V Power Connector J5 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 50. 1x12 Power Connector 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 51. AUX5/ON-OFF Connector 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 52. PCI Connector 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 53. ISA Connector 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 54. SIMM Connector 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 55. 1x2 Power Switch Connector 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 56. 1x2 Power Up Configuration Connector 154. . . . . . . . . . . . . . . . . . . . . .

Figure 57. L2 SRAM Module Connector 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 58. 2x8 RISCWatch Connector 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 59. Signal and Power Layers 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 60. Typical Wiring Channel Top View 162. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 61. PowerPC 603/604 Board Fabrication 163. . . . . . . . . . . . . . . . . . . . . . . .

Figure 62. Power Plane Split 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 63. PCI Interrupt Slot 0 Connections 171. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 64. Generic Implementation PAL Installation 188. . . . . . . . . . . . . . . . . . . . .

MPRH08TSU-02

Tables

Table 1. Quickstart Peripheral List 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2. Example Clock Generator Frequencies 26. . . . . . . . . . . . . . . . . . . . . . . .

Table 3. TT[0:3] (Transfer Type) Decoding by 660 Bridge 27. . . . . . . . . . . . . . . .

Table 4. 660 Bridge Address Mapping of CPU Bus Transactions 28. . . . . . . . . .

Table 5. 660 Bridge Address Mapping of CPU Bus Transactions 33. . . . . . . . . .

Table 6. Reference Design Responses to PCI_C[3:0] Bus Commands 36. . . . .

Table 7. Mapping of PCI Memory Space, Part 1 36. . . . . . . . . . . . . . . . . . . . . . . . .

Table 8. Mapping of PCI Memory Space, Part 2 37. . . . . . . . . . . . . . . . . . . . . . . . .

Table 9. Mapping of PCI Master I/O Transactions 38. . . . . . . . . . . . . . . . . . . . . . .

Table 10. Active CAS# Lines – PCI to Memory Writes, BE or LE Mode 40. . . . .

Table 11. DMA Assignments 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 12. DRAM Module Presence Detect Bit Encoding 48. . . . . . . . . . . . . . . . . .

Table 13. Planar ID Encoding 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 14. DRAM Module Presence Detect Bit Encoding 49. . . . . . . . . . . . . . . . . .

Table 15. External Register Support 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 16. Signal Descriptions 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 17. Supported DRAM Modules 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 18. L2 Configuration Implementation 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 19. Endian Mode Byte Lane Steering 78. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 20. Endian Mode 6–3/604 Address Translation 78. . . . . . . . . . . . . . . . . . . .

Table 21. Memory in BE Mode 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 22. Memory in LE Mode 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 23. PCI in BE Mode 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 24. PCI in LE Mode 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 25. Two Byte Transfer Information 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 26. Rearranged 2-Byte Transfer Information 85. . . . . . . . . . . . . . . . . . . . . .

Table 27. 4-Byte Transfer Information 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 28. Rearranged 4–Byte Transfer Information 88. . . . . . . . . . . . . . . . . . . . . .

Table 29. Mapping of PCI Memory Space, Part 1 95. . . . . . . . . . . . . . . . . . . . . . .

Table 30. Summary of SIO Register Setup

(Configuration Address = 8080 08xx) 104. . . . . . . . . . . . . . . . . . . . . . . .

Table 31. Summary of SIO Configuration Registers 106. . . . . . . . . . . . . . . . . . . . .

Table 32. Configuration Address Assignments 107. . . . . . . . . . . . . . . . . . . . . . . . . .

Table 33. Combined Register Listing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 34. 660 Bridge Indexed BCR Listing 114. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 35. Compatible ISA Ports (Not on Reference Board) 116. . . . . . . . . . . . . .

Table 36. Power Supply Specification 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 37. Approximate Power Consumption 137. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 38. Specifications for 3.3V Regulator on the Motherboard 138. . . . . . . . . . .

Table 39. Specifications for 2.5V Regulator on the Motherboard 138. . . . . . . . . . .

Table 40. Keyboard Connector Pin Assignments 144. . . . . . . . . . . . . . . . . . . . . . . .

Table 41. Mouse Connector Pin Assignments 144. . . . . . . . . . . . . . . . . . . . . . . . . .

14 MPRH08TSU-02

Table 42. Speaker Connector Pin Assignments 145. . . . . . . . . . . . . . . . . . . . . . . . .

Table 43. Power Good LED Connector 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 44. HDD LED Connector 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 45. Reset Switch Connector 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 46. Fan Connector Pin Assignments 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 47. 3.3V Power Connector J5 Pin Assignments 147. . . . . . . . . . . . . . . . . . .

Table 48. Power Connector J4 Pin Assignments 147. . . . . . . . . . . . . . . . . . . . . . . .

Table 49. AUX5/ON-OFF Connector Pin Assignments 148. . . . . . . . . . . . . . . . . . .

Table 50. PCI Connector Pin Assignments 148. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 51. ISA Connector Pin Assignments 150. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 52. SIMM Connector Pin Assignments 152. . . . . . . . . . . . . . . . . . . . . . . . . .

Table 53. Power Switch Connector Pin Assignments 154. . . . . . . . . . . . . . . . . . . .

Table 54. Power Up Configuration Connector Pin Assignments 154. . . . . . . . . . .

Table 55. L2 SRAM Module Connector Pin Assignments 155. . . . . . . . . . . . . . . .

Table 56. RISCWatch Connector Pin Assignments 157. . . . . . . . . . . . . . . . . . . . . .

Table 57. Height Considerations 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 58. Clock Net Lengths ( 7  a  10 ) 165. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 59. CPU Bus Nets 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 60. Timing Critical Nets 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 61. PCI Bus Nets 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 62. Noise Sensitive Nets 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 63. PowerPC 603/604 Reference Design Roadmap 170. . . . . . . . . . . . . . . .

Table 64. 603e Bill of Materials 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 65. 604 Bill of Materials 194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPRH08TSU-02

About This Book

Notice:

The 603 version of the PowerPC 603/604 Reference Design is no longer supported. It is replaced by the 603e

version of the 603/604 PowerPC Reference Design. In this document, the term 603 also refers to the Pow-

erPC 603e RISC microprocessor unless otherwise specified.

Power management is beyond the scope of this document.

Audience:

This reference design is designed for engineers and system designers who are interested in implementing

PowerPC systems that are compliant with the PowerPC Reference Platform Specification. The material re-

quires a detailed understanding of computer systems at the hardware and software level.

Reference Material:

Understanding of the relevant areas of the following documents is required for a good understanding of the

reference design:

SPowerPC 604 User’s Manual, IBM document MPR604UMU-01

SPowerPC 604 Hardware Specification, IBM document MPR604HSU-01

SPowerPC 603 User’s Manual, IBM document MPR603UMU-01

SPowerPC 603e Hardware Specification, IBM document MPR603EHS-01

SPowerPC 603e Technical Summary, IBM document MPR603TSU-04

SIBM27-82660 PowerPC to PCI Bridge User’s Manual, IBM document number MPR660UMU–01

SPCI Local Bus Specification, Revision 2.1, available from the PCI SIG

SPowerPC Reference Platform Specification, Version 1.1, IBM document MPRPRPPKG

SThe Power PC Architecture, second edition, Morgan Kaufmann Publishers

(800) 745–7323, IBM document MPRPPCARC–02

SIntel 82378ZB System I/O (SIO) Data Book, Intel order number 290473-004.

The following documents are useful as sources of tutorial and supplementary information about the reference

design.

SPowerPC System Architecture, Tom Shanley, Mindshare Press (800) 420-2677.

SIBM27-82650 PowerPC to PCI Bridge User’s Manual, IBM document number MPR650UMU–01

Document Conventions:

Kilobytes, megabytes, and gigabytes are indicated by a single capital letter after the numeric value. For exam-

ple, 4K means 4 kilobytes, 8M means 8 megabytes, and 4G means 4 gigabytes.

The terms DIMM and SIMM are often used to mean DRAM module.

Hexadecimal values are identified (where not clear from context) with a lower-case letter h at the end of the

value. Binary values are identified (where not clear from context) with a lower-case letter b at the end of the

value.

In identifying ranges of values from and to are used whenever possible. The range statement from 0 to 2M

means from and including zero up to (but not including) two megabytes. The hexadecimal value for the range

from 0 to 64K is: 0000h to FFFFh.

The terms asserted and negated are used extensively. The term asserted indicates that a signal is active

(logically true), regardless of whether that level is represented by a high or low voltage. The term negated

means that a signal is not asserted. The # symbol at the end of a signal name indicates that the active state

of the signal occurs with a low voltage level.

16 MPRH08TSU-02

Introduction

MPRH01TSU-02

Section 1

Introduction

This document provides a detailed technical description of the PowerPCt 603/604 Refer-

ence Design, and is intended to be used by hardware, software, test, simulation, and other

engineers as a first source of information. Software developers should read through the

entire document because pertinent facts may be located in hardware sections.

The focus of this document is mainly the motherboard electronics and firmware. Where ap-

propriate this document references detailed information in other documents. Consult other

documents for information on specific I/O devices such as hard drives, CD–ROMs, L2

cache cards, video cards, etc. that comprise a total system.

Recommendations for memory mappings, software implementations, and the like are only

recommendations and may or may not represent the algorithms implemented in boot code

or operating systems.

Note: This document contains several references to the 603/604 Reference Design Power

Management Specification; however, the specification was not yet available at the date of

printing.

1.1 IBM Reference Products

IBM offers several different PowerPC reference products for a given PowerPC system.

1.1.1 Reference Design

The PowerPC 603/604 Reference Design (reference design) is composed of both the in-

tangible design and the documentation describing that design. The reference design docu-

mentation addresses the motherboard electronics, firmware, and various system related

issues. The reference design contains this reference design Technical Specification, Gerb-

er format physical design files on an 8mm tape, electrical device model files in Cadencet

format, system firmware guidelines, schematics, contact information for commented boot

ROM source code, and such other device and system information as is deemed helpful.

1.1.2 Reference Board

The PowerPC 603/604 Reference Board (reference board) is the physical implementation

of the motherboard part of the reference design. It includes the reference design, the popu-

lated motherboard, the boot ROM, and other components as appropriate.

1.1.3 Reference Firmware

The PowerPC 603/604 Reference Firmware (reference firmware) is described in the refer-

ence design, and consists of the commented source code of the software contained in the

boot ROM. This is available from IBM as discussed in section 10.1.

Introduction

18 MPRH01TSU-02

1.1.4 Reference System

The PowerPC 603/604 Reference System (reference system) consists of a complete

603/604 PowerPC computer system, including the motherboard, enclosure, power supply,

cooling devices, and such other adaptors and peripherals as are described in the detailed

product offering.

1.2 Purpose

The reference design is aimed at the market for low cost desk top PowerPC personal com-

puters. The motherboard is sized to fit within a BabyAT form factor enclosure, although the

enclosure may need to be modified to provide additional cooling and/or additional space

for I/O cards.

The reference design is intended to help companies develop their own products using the

PowerPC architecture. The reference design may be used:

SAs a baseline system in order to gauge the effects of changes on the design

STo test new boot code

STo test operating systems and/or applications

SFor performance measuring.

The reference design is:

SA compliant implementation of the PowerPC Hardware Reference Platform Specifi-

cation, version 1.1

STested for functionality to the level of software available at the time of shipping

SA prototype of a system under development which may have prototype ASICs, erra-

ta, and/or wiring changes.

The reference design is not:

SA complete market ready design

STested for compliance to FCC and other regulatory requirements.

Introduction

MPRH01TSU-02

1.3 Reference Design Overview

This section contains an overview of the reference design. The block diagram of the refer-

ence design is shown in Figure 1.

The reference design is compliant with the PowerPC Reference Platform Specification Ver-

sion 1.1.

The core of the system is the PowerPC 603et or PowerPC 604t RISC microprocessor.

The IBM27-82660 Bridge chipset (660 Bridge) interfaces the CPU to the DRAM memory,

and provides L2 cache control for the tagRAM and SRAM components that are located on

the CPU bus.

The 660 Bridge also interfaces the CPU to the PCI bus. On the motherboard, the ISA bus

bridge is located on the PCI bus. The boot ROM is also physically located on the PCI bus,

but is accessed using a special protocol. PCI devices are unable to activate the ROM, and

ROM operations do not interfere with the PCI bus protocol.

The reference design also provides three PCI slots, by which major I/O subsystems, such

as SCSI and video adaptors, can be connected to the system. The reference design also

provides five ISA slots.

The motherboard is designed to an industry standard BabyAT (8.6 in. by 13 in.) form factor.

It requires +5V to power most of the components. The motherboard also requires 12 V

to support some of the peripheral features. Components that require +3.3V (such as the

PCI bus agents) are supported using a regulator mounted on the motherboard to convert

+5V to +3.3V.

1.3.1 The CPU

The reference board can be configured with either the 603e, or the 604 implementation of

the PowerPC architecture. Only one CPU may be installed at a time.

These CPUs use a CPU bus clock, and are in general capable of running their internal clock

at several different multiples of the bus clock frequency. The reference design runs the PCI

bus clock at a fixed frequency multiple of one half of the CPU bus clock frequency. The CPU

bus clock frequency is adjustable, and is nominally 66MHz.

The reference design supports bi-endian operation, and is equipped with an ESP connec-

tor to support RISCWatch debugging and monitor systems.

Consult your IBM representative for currently available choices of CPU type and operating

frequency.

1.3.2 IBM27-82660 Bridge

The IBM27-82660 Bridge (660 Bridge) chipset supplies many of the functions of the refer-

ence design. The 660 Bridge interfaces the CPU to the L2, system memory, the PCI bus,

the ROM, and other reference design components.

1.3.3 L2 Cache

The reference design supplies an L2 cache controller, located inside the 660 Bridge chip-

set. The motherboard provides a socket for an SRAM module, and the L2 tag RAM (16K

x 15, synchronous) is supplied installed on the board. The L2 is a unified, write-thru, direct-

Introduction

20 MPRH01TSU-02

mapped, look-aside cache that supports 1M of SRAM to cache the low 1G of CPU memory

space. The L2 supplies data to the CPU bus on write hits and snarfs the data (updates the

SRAM data while the memory controller is accessing DRAM memory) on read/write mis-

ses. It snoops PCI to memory transactions. Typical read performance with 9ms SRAM is

3-1-1-1, followed by -2-1-1-1 on pipelined reads for sync.

Regulator 29F040

KYBD

Mouse

8042

Mouse

DC1385

RTC

IBM27-82663

Buffer

ESP Connector

X-Bus

ISA Bus

Data

Address

Control

ISA Expansion

Slots (5)

System I/O

EPLD

X-Buffers

Data

Addr/Cntrl

MPC970

Clock Gen X-Bus

Strobes

ISA Bus

Bridge

SIO

Keyboard

Speaker

Control

PCI_AD

Address/Data

PCI Expansion

Slots (3)

Flash ROM

IBM27-82664

Controller

DRAM Module

604

603

TagRAM

L2 SRAM

Module

Address

Data

5v to 3.3v

PCI Bus

60X Bus

Power

Mgt Cntrlr

87C750

Figure 1. 603/604 Reference Design Block Diagram

EPM5130C

1.3.4 System Memory

The reference design memory subsystem can support up to 128M of 70ns DRAM memory

on four 72 pin modules via sockets. Each SIMM socket can support an 8M or 32M 72 pin

SIMM. The DRAM subsystem is 72 bits wide: 64 data bits and eight parity bits. One parity

bit is generated for each byte of data written. The 660 Bridge can also be configured to per-

Introduction

MPRH01TSU-02

form ECC memory data checking and correction using standard parity DRAM modules. Or

it can be configured to disable DRAM parity checking for systems using non-parity DRAM.

The 660 Bridge also provides DRAM refresh and supports EDO hyper-page mode DRAM.

Memory access performance from the CPU bus at 66MHz with 70ns DRAM is typically:

SPipelined burst read: 4-4-4-4 CPU bus clocks—16 CPU clocks for 32 bytes of data

SPipelined burst write: 5-4-4-4 CPU bus clocks—17 CPU clocks for 32 bytes of data

Memory access performance from the PCI bus at 33MHz with 70ns DRAM is typically:

SRead bursts 5-1-1-1 -1-1-1-1 6-1-1-1 -1-1-1-1 6-1-1-1 -1-1-1-1 ... 6-1-1-1 -1-1-1-1,

SWrite bursts 5-1-1-1 -1-1-1-1 3-1-1-1 -1-1-1-1 3-1-1-1 -1-1-1-1 ... 3-1-1-1 -1-1-1-1.

1.3.5 PCI Bus

The 660 Bridge includes the interface between the PCI bus and the rest of the system. The

reference design allows CPU to PCI access and PCI bus master to memory access (with

snooping), and handles all PCI related system memory cache coherency issues. Three PCI

expansion slots are provided.

The reference design also supports memory block locking, types 0 and 1 configuration

cycles, and ISA master access to system memory thru the ISA bridge.

1.3.6 Flash ROM

The reference design uses an AMD AM29F040-120 Flasht ROM to contain the POST and

boot code. It is recommended that Vital Product Data (VPD) such as the motherboard

speed and native I/O complement be programmed into in this device. It is possible to pro-

gram the Flash before or during the manufacturing process.

After power on, the initial code fetched is supplied from this device. The 660 Bridge man-

ages ROM access and control. The reference design supports a 512K Flash.

1.3.7 ISA Bus

The ISA bridge function is provided by an Intel 82378ZB chip (SIO). It provides a PCI to

ISA bus bridge where the native I/O and the ISA slots reside, and it provides system ser-

vices such as ISA bus DMA, PCI bus arbitration, and interrupt control.

1.3.8 Time of Day Clock

The reference design uses a Dallas Semiconductort DS1385S to provide the real time

clock (TOD or RTC) function. This device is PC compatible and resides on the X-bus. It fea-

tures an additional 4K of NVRAM and a replaceable battery.

1.3.9 PS/2t Compatible Keyboard/Mouse Controller

The reference design uses an Intel 8042AH as a keyboard and mouse controller.

The code used is the same version as used in IBM Personal System/2 machines. This mi-

crocode may differ from other 8042 type keyboard controllers.

1.3.10 System Clocks

The primary clock generation is accomplished with a Motorolat MPC970 PLL clock gener-

ator, which uses a seed oscillator to generate the CPU and PCI clocks needed by the sys-

tem.

Introduction

22 MPRH01TSU-02

1.3.11 System I/O EPLD

The system I/O EPLD is a programmable logic device that uses the X-bus signals and the

partial decode signals from the SIO to decode chip selects for various components.

1.3.12 Power Management

Power management hardware is included on the board; however, power managenent ca-

pability will be implemented at a later date and will be described in a separate document.

1.4 Quickstart Peripheral List

The reference design is intended for typical PC peripherals. Products from a large number

of manufacturers should work satisfactorily (see Table 1 for a list of peripherals and materi-

als). Reference boards do not come with the all of the required peripherals, cables, speak-

er, indicator LEDs, switches, and such that are needed to configure a properly working sys-

tem.

Table 1 outlines the generic requirements for peripherals and gives examples of some de-

vices that have been used for testing. It is not a recommendation of any particular vendor.

The purpose of this table is to outline at least one set of peripherals that may be used to

begin testing.

Table 1 does not include cables for a parallel port, indicators, a switch, or a speaker.

An IBM 3101 asynchronous terminal or equivalent is required for testing with the bring up

driver (BUD) code. Settings are 8-bit, no parity, one stop bit, and 9600 baud. VT100 or VT52

emulator terminals may be acceptable. It is desirable to also have a video monitor for BUD

tests. The boot code will boot with either an async console, a video on motherboard, or

both.

1.5 Reference Design Level

This documentation supports the release 2.1 version of the 603/604 reference design and

reference board. Except as noted, the information herein is believed to be correct for the

release 3.0 version of the reference design, once all of the errata are cured (see section

13, Errata for the reference design roadmap).

The reference board schematics are of the release 2.0 reference board, and correctly show

the workarounds that are installed on that board in order to work around certain errata.

Introduction

MPRH01TSU-02

Table 1. Quickstart Peripheral List

Generic Description Example Device

L2 SRAM card, 256KB Alliance Semiconductor AS7M64P3256–15C

Loctite 384 adhesive, 300ml cartridge Loctite Corp. 17041

Loctite 384 activator, 10 liter can Loctite Corp. 17101

Video adapter card, PCI S3 Diamond Stealth (S3) 864

SCSI adaptor card, PCI NCR 8100S with 609–039–1635 controller

Super I/O adaptor ( IDE, floppy, serial

ports, parallel ports, etc.) Acculogic sIDE–4/HP (110–00139–00E00)

Audio adaptor card Creative Labs Soundblaster 16

Floppy disk drive, 3.5”x1.44MB Alps DFR723F, IBM 73G4514, Mitsubishi MF355F–258UG

Hard disk drive, SCSI–2, 8 bit Quantum LPS270/5405, Maxtor MXT–540SL, IBM WDS–3200 (79F4042)

Hard disk drive, SCSI 1GB IBM 94G3187

Hard disk drive, IDE 1GB Maxtor HDMC71260AC

CD_ROM drive, internal SCSI Toshiba XM–4101BMY

CD_ROM drive, internal SCSI, 4x Toshiba 5301–4x

CD_ROM drive, internal IDE, 4x Chinnon CDS5451

Chassis, Baby AT Olsen Metal Products CC300249–17

Power supply, 200W Energy Star API-3186S, IBM 06H2968

Box fan Panaflow FBA08T12M

Box fan shock mounts IBM 81F7977

Internal cables, floppy, SCSI, and CD–

ROM Standard cables

Speaker, internal 8W .5W 2pin

LED, 2.5 ma drive

Asynchronous terminal IBM 3101

Super VGA monitor IBM 6324, 6325, 6327, 9524, 9525, 9527, 9521

Keyboard, PS/2 compatible

Mouse, PS/2 compatible

Introduction

24 MPRH01TSU-02

CPU

MPRH01TSU-02

Section 2

CPU and CPU Bus

This section discusses topics that are directly related to the CPU, including how the 660

bridge decodes CPU initiated transfers as a function of the transfer type and address range.

For more information, refer to the 660 Bridge User’s Manual.

The reference design supports CPU bus speeds up to 66MHz, and PCI bus speeds up to

33MHz. The reference design is initially configured with a CPU:PCI bus speed ratio of 2:1.

The CPU:PCI clock ratio can be changed to 1:1 or 3:1 by reconfiguring the clock generator

and the 660 bridge, as long as other system considerations are handled correctly.

2.1 CPU Bus Masters

The reference design uses a single CPU, of either the PowerPC 603e or PowerPC 604 fam-

ily, and an external L2 cache is not allowed. Thus there are only two bus masters on the

CPU bus, the CPU and the 660 bridge. CPU bus arbitration is greatly simplified, and the

multi-processor capabilities of the 660 bridge are not used. The remaining arbitration on

the CPU bus is between the CPU and the snoop broadcasting logic in the 660 bridge. Since

the 660 bridge parks the CPU bus on CPU1 whenever the bus is idle, CPU latency is mini-

mized.

One level of address bus pipelining is supported, and most data writes are posted. Precise

exceptions are reported via TEA#, and imprecise exceptions are reported via MCP#. PIO,

or programmed I/O transactions (XATS# type) are not supported.

2.1.1 603e CPU

The 603e version of the reference design operates the 603e in 64 bit data bus mode.

The reference design is initially configured for DRTRY# mode, and can be reconfigured to

no-DRTRY# mode by populating R440 = 0 ohm. In DRTRY# mode, data is assumed to

have been speculatively presented to the CPU, and so is held for one clock in an internal

CPU latch before being presented to the CPU data consumers. In no-DRTRY# mode, the

data is assumed to be good when TA# is sampled active, so it is immediately forwarded

without the delay cycle. Use of this mode mainly speeds up reads from the L2.

The 603e version of the reference design runs at 3:2 603e internal clock to bus clock ratio

at 99MHz:66MHz. CPU PLL_CFG[0:3] is set to 1100.

On the 603e version of the reference board, the following are populated: R425 and R426

with 1k ohm resistors, and R423 and R424 with with 10k ohm resistors. The following are

not populated: R421, R422, R427, and R428, R377.

CPU

26 MPRH01TSU-02

2.1.2 604 CPU

The reference design is initially configured for DRTRY# mode, and can be reconfigured to

no-DRTRY# mode by populating R440 = 0 ohm.

The 604 version of the reference design is initially configured to run at 2:1 604 internal clock

to bus clock ratio at 132MHz:66MHz. CPU PLL_CFG[0:3] is set to 0100. The 604 can be

configured to run with different internal to bus clock ratios as described in the 604 User’s

Manual.

The clock generator can be configured to produce different frequencies. Some examples

are shown in Table 2.

Table 2. Example Clock Generator Frequencies

CPU Internal Clock (MHz) CPU Bus Clock (MHz) PCI Bus Clock (MHz) Crystal Y2A (MHz)

100

50 25 12.5

66 33 16.5

120 60 30 15

132 66 33 16.5

On the 604 version of the reference board, the following are populated: R423 (10k) and

R425, R426, and R428 with with 1k ohm resistors, and R377 with 0 ohm. The following are

not populated: R421, R422, R424, and R427.

2.2 System Response by CPU Bus Transfer Type

All access to the rest of the system is provided to the CPU by the 660 Bridge. Table 3 shows

the 660 Bridge decoding of CPU bus transfer types. Based on TT[0:3], the 660 Bridge re-

sponds to CPU bus master cycles by generating a read transaction, a write transaction, or

an address-only response. The 660 Bridge ignores TT[4] when it evaluates the transfer

type.

The bridge decodes the target of the transaction based on the address range of the transfer

as shown in Table 4. The transfer type decoding shown in Table 3 combines with the target

decoding to produce the following:

SSystem memory reads and writes

SPCI I/O reads and writes

SPCI configuration reads and writes

SPCI interrupt acknowledge reads

SPCI memory reads and writes

SSystem ROM reads and writes

SVarious bridge control register (BCR) reads and writes.

CPU

MPRH01TSU-02

Table 3. TT[0:3] (Transfer Type) Decoding by 660 Bridge

TT[0:3] 60X Operation 60X Bus

Transaction 660 Bridge Operation For CPU to

Memory Transfers 660 Bridge Operation For CPU to

PCI Transactions

0000 Clean block or lwarx Address only Asserts AACK#. No other response. No PCI transaction.

0001 Write with flush SBW(1)

or burst Memory write operation. PCI write transaction.

0010 Flush block or stwcx Address only Asserts AACK#. No other response. No PCI transaction.

0011 Write with kill SBW or burst Memory write operation. L2 invalidates

addressed block. PCI write transaction.

0100 sync or tlbsync Address only Asserts AACK#. No other response. No PCI transaction.

0101 Read or read with no

intent to cache SBR(1)

or burst Memory read operation. PCI read transaction.

0110 Kill block or icbi Address only Asserts AACK#. L2 invalidates

addressed block. Asserts AACK#. No other response.

0111 Read with intent to

modify Burst Memory read operation. PCI read transaction.

1000 eieio Address only Asserts AACK#. No other response. No PCI transaction.

1001 Write with flush atomic,

stwcx SBW Memory write operation. PCI write transaction.

1010 ecowx SBW Asserts AACK# and TA# if the transaction is not claimed by another 60X bus

device. No PCI transaction. No other response.

1011 Reserved Asserts AACK#. No other response. No PCI transaction.

1100 TLB invalidate Address only Asserts AACK#. No other response. No PCI transaction.

1101 Read atomic, lwarx SBR or burst Memory read operation. PCI read transaction.

1110 External control in,

eciwx Address only 660 asserts all ones on the CPU data bus. Asserts AACK# and TA# if the

transaction is not claimed by another 60X bus device. No PCI transaction. No other

response.

1111 Read with intent to

modify atomic, stwcx Burst Memory read operation. PCI read transaction.

Note:

(1)As used in this table, SBR means Single-Beat Read, and SBW means Single-Beat

Write.

Transfer types in Table 3 that have the same response are handled identically by the

bridge. For example, if the address is the same, the bridge generates the same memory

read transaction for transfer types 0101, 0111, 1101, and 1111.

The 660 Bridge does not generate PCI or system memory transactions in response to ad-

dress only transfers. The bridge does drive all-ones onto the CPU bus and signals TA# dur-

ing an eciwx if no other CPU bus agent claims the transfer.

References in the remainder of this document to a CPU read, assume one of the transfer

types in Table 3 that produce the read response from the 660 bridge. Likewise, references

to a CPU write refer to those transfer type that produce the write response.

CPU

28 MPRH01TSU-02

2.3 System Response by CPU Bus Address Range

The 660 Bridge determines the target of a CPU bus master transaction based on the CPU

bus address range as shown in Table 4. The acronym BCR means bridge control register.

Table 4. 660 Bridge Address Mapping of CPU Bus Transactions

CPU Bus Address Other

Conditions Target Transaction Target Bus Address Notes

0 to 2G

0000 0000h to 7FFF FFFFh System Memory 0 to 2G

0000 0000h to 7FFF FFFFh (1)(2)

2G to 2G + 8M

8000 0000h to 807F FFFFh

Contiguous

Mode

PCI I/O Transaction, BCR Transaction,

PCI Configuration

0 to 8M

0000 0000h to 007F FFFFh (3)

Non-Contigu-

ous

Mode

PCI Configuration

(Type 1) Transaction

0 to 64K

0000 0000h to 0000 FFFFh (4)

2G + 8M to 2G + 16M

8080 0000h to 80FF FFFFh PCI Configuration

(Type 0) Transaction PCI Configuration Space

0080 0000h to 00FF FFFFh

2G + 16M to 3G – 8M

8100 0000h to BF7F FFFFh PCI I/O Transaction 16M to 1G – 8M

0100 0000h to 3F7F FFFFh

3G – 8M to 3G

BF80 0000h to BFFF FFFFh BCR Transactions

and PCI Interrupt

Ack. Transactions

1G – 8M to 1G

3F80 0000h – 3FFF FFFFh (3)(6)

3G to 4G – 2M

C000 0000h to FFDF FFFFh PCI Memory

Transaction 0 to 1G – 2M

0000 0000h to 3FDF FFFFh

4G – 2M to 4G

FFE0 0000h to FFFF FFFFh

Direct Attach

ROM Read,

Write, or Write

Lockout

BCR Transaction 0 to 2M

0000 0000h to 001F FFFFh

(ROM Address Space)

(2)

Remote ROM PCI Memory Transaction to I/O Bus

Bridge 1G – 2M to 1G

3FE0 0000h to 3FFF FFFFh (2)

Notes for Table 4:

1. System memory can be cached. Addresses from 2G to 4G are not cacheable.

2. Memory does not occupy the entire address space.

3. Registers do not occupy the entire address space.

4. Each 4K page in the 8M CPU bus address range maps to 32 bytes in PCI I/O

space.

5. Registers and memory do not occupy the entire address space. Accesses to un-

occupied addresses result in all one-bits on reads and no-ops on writes.

6. A memory read of BFFF FFF0h generates an interrupt acknowledge transaction

on the PCI bus.

2.3.1 Address Mapping for Non-Contiguous I/O

Figure 2 shows the address mapping that the 660 Bridge performs in non-contiguous

mode. The I/O map type register (address 8000 0850h) and the bridge chip set options 1

contiguous mode, the 8M address space of the 60X bus is compressed into 64K of PCI ad-

dress space, and the 60X CPU cannot create PCI I/O addresses from 64K to 8M.

In non-contiguous I/O mode, the 660 Bridge partitions the address space so that each 4K

page is remapped into a 32-byte section of the 0 to 64K ISA port address space, so that

60X CPU protection attributes can be assigned to any of the 4K pages. This provides a flex-

CPU

MPRH01TSU-02

ible mechanism to lock the I/O address space from change by user-state code. This parti-

tioning spreads the ISA I/O address locations over 8M of CPU address space.

In non-contiguous mode, the first 32 bytes of a 4K page are mapped to a 32-byte space

in the PCI address space. The remainder of the addresses in the 4K page are mirrors into

the the same 32-byte PCI space. Each of the 32 contiguous port addresses in each 4K page

has the same protection attributes in the CPU.

Figure 2. Non-Contiguous PCI I/O Address Transformation

Discarded

Forced to zero

The three least-significant address bits are unmunged during the transformation if little-endian mode is

selected.

LSB

MSB

LSB

MSB

For example in Figure 3, 60X CPU addresses 8000 0000h to 8000 001Fh are converted

to PCI I/O port 0000h through 001Fh. PCI I/O port 0020h starts in the next 4K page at 60X

CPU address 8000 1000h.

ISA I/O 60X Address

0000 8000 0000

0001 8000 0001

0002

8000 0002

4K Page .

001E 8000 001E

001F 8000 001F 60X Addresses

8000 0020 to 8000 0FFF

Are Wrapped and Should

0020 8000 1000 Not Be Used.

0021

8000 1001

4K Page .

Figure 3. Non-Contiguous PCI I/O Address Translation

CPU

30 MPRH01TSU-02

2.3.2 Address Mapping for Contiguous I/O

In contiguous I/O mode, CPU addresses from 2G to 2G + 8M generate a PCI I/O cycle on

the PCI bus with PCI_AD[29:00] unchanged. The low 64K of PCI I/O addresses are for-

warded to the ISA bus unless claimed by a PCI agent.

Memory page protection attributes may only be assigned by 4K groups of ports, rather than

by 32-port groups as in the non-contiguous mode. This is the power-on default mode.

Figure 4 gives an example of contiguous I/O partitioning.

ISA I/O 60X Address

0000 8000 0000

0001 8000 0001

0002 8000 0002

. .

001E 8000 001E

001F 8000 001F Contiguous 603/604

addresses (No gaps)

0020 8000 0020

0021 8000 0021

. .

FFFE 8000 FFFE

FFFF 8000 FFFF

Figure 4. Contiguous PCI I/O Address Translation

2.3.3 PCI Final Address Formation

The 660 Bridge maps 60X CPU bus addresses from 2G to 4G as PCI transactions, error

address register reads, or ROM reads and writes. The 660 Bridge manipulates 60X bus

addresses from 2G to 4G to generate PCI addresses as follows:

SPCI_AD[31:30] are set to zero.

SPCI_AD[2:0] are unmunged if little-endian mode is selected.

SAfter unmunging, PCI_AD[1:0] are set to 00b except for PCI I/O cycles.

2.4 CPU to Memory Transfers

The system memory address space is from 0 to 2G. Physical memory does not occupy the

entire address space. When the CPU reads an unpopulated location, the 660 Bridge re-

turns all-ones and completes the transfer normally. When the CPU writes to an unpopulat-

ed location, the Bridge signals normal transfer completion to the CPU but does not write

the data to memory. The memory select error bit in the error status 1 register (bit 5 in index

C1h) is set in both cases.

All CPU to memory writes are posted and can be pipelined.

The 660 Bridge supports all CPU to memory bursts, and all single-beat transfer sizes and

alignments that do not cross an 8-byte boundary, which includes all memory transfers initi-

ated by the 603/604 CPU.

CPU

MPRH01TSU-02

2.4.1 LE Mode

The bridge supports all transfer sizes and alignments that the CPU can create in LE mode;

however, all loads or stores must be at natural alignments in LE mode (or the CPU will take

an alignment exception). Also, load/store multiple word and load/store string word instruc-

tions are not supported in the CPU in LE mode.

2.5 CPU to PCI Transactions

Since all CPU to PCI transactions are CPU memory mapped, software must in general uti-

lize the EIEIO instruction which enforces in-order execution, particularly on PCI I/O and

configuration transactions. Some PCI memory operations can be sensitive to order of ac-

cess also. See the 660 Bridge User’s Manual.

All addresses from 2G to 4G (including ROM space) must be marked non-cacheable. See

the PowerPC Reference Platform Specification. The reference design supports all PCI bus

protocols during CPU to PCI transactions.

The reference design supports all CPU to PCI transfer sizes that do not cross a 4-byte

boundary, and, to support the 604 store multiple instruction, the reference design supports

8-byte CPU to PCI writes that are aligned on an 8-byte boundary. The bridge does not sup-

port CPU bursts to the PCI bus.

When the 660 bridge decodes a CPU access as targeted for the PCI, the 660 bridge re-

quests the PCI bus. Once the SIO grants the PCI bus to the 660 bridge, the bridge initiates

the PCI cycle and releases the bus.

CPU to PCI transactions that the PCI target retries, cause the 660 Bridge to deassert its

PCI_REQ# (the Bridge follows the PCI retry protocol). The Bridge stays off of the PCI bus

for two PCI clocks before reasserting PCI_REQ# (or FRAME#, if the PCI bus is idle and

the PCI_GNT# to the Bridge is active).

2.5.1 CPU to PCI Read

If the CPU to PCI cycle is a read, a PCI read cycle is run. If the PCI read cycle completes,

the data is passed to the CPU and the CPU cycle is ended. If the PCI cycle is retried, the

CPU cycle is retried. If a PCI master access to system memory is detected before the PCI

read cycle is run then the CPU cycle is retried (and no PCI cycle is generated).

2.5.2 CPU to PCI Write

If the CPU to PCI cycle is a write, a PCI write cycle is run. CPU to PCI I/O writes are not

posted, as per the PCI Local Bus Specification version 2.1. If the PCI transaction is retried,

the Bridge retries the CPU.

CPU to PCI memory writes are posted, so the CPU write cycle is ended as soon as the data

is latched. If the PCI cycle is retried, the Bridge retries the cycle until it completes.

2.5.2.1 Eight-Byte Writes to the PCI (Memory and I/O)

The 660 Bridge supports 1-byte, 2-byte, 3-byte, and 4-byte transfers to and from the PCI.

The 660 Bridge also supports 8-byte memory and I/O writes (writes only, not reads) to the

PCI bus. This enables the use of the 604 store multiple instruction to PCI devices.When

an 8-byte write to the PCI is detected, it is not posted initially. Instead the CPU waits until

the first 4-byte write occurs, then the second 4-byte write is posted. If the PCI retries on

CPU

32 MPRH01TSU-02

the first four byte transfer or a PCI master access to system memory is detected before the

first 4-byte transfer then the CPU is retried. If the PCI retries on the second 4-byte transfer

then the 660 Bridge retries the PCI write.

2.5.3 CPU to PCI Memory Transactions

CPU transfers from 3G to 4G–2M are mapped to the PCI bus as memory transactions.

2.5.4 CPU to PCI I/O Transactions

CPU transfers from 2G+16M to 3G–8M are mapped to the PCI bus as I/O transactions. In

compliance with the PCI specification, the 660 Bridge master aborts all I/O transactions that

are not claimed by a PCI agent.

2.5.5 CPU to PCI Configuration Transactions

The reference design allows the CPU to generate type 0 and type 1 PCI configuration

cycles. The CPU initiates a transfer to the appropriate address, the 660 bridge decodes the

cycle and generates a request to the PCI arbiter in the SIO. When the PCI bus is acquired,

the 660 bridge enables its PCI_AD drivers and drives the address onto the PCI_AD lines

for one PCI clock before it asserts PCI_FRAME#. Predriving the PCI_AD lines for one clock

before asserting PCI_FRAME# allows the IDSELs to be resistively connected to the

PCI_AD[31:0] bus at the system level.

The transfer size must match the capabilities of the target PCI device for configuration

cycles. The reference design supports 1-, 2-, 3-, and 4-byte transfers that do not cross a

4-byte boundary.

Address unmunging and data byte swapping follows the same rules as for system memory

with respect to BE and LE modes of operation. Address unmunging has no effect on the

CPU address lines which correspond to the IDSEL inputs of the PCI devices.

2.5.5.1 Preferred Method of Generating PCI Configuration Transactions

The preferred method for generating PCI configuration cycles is via the 660 Bridge indexed

Bridge Control Registers (BCR). This configuration method is described in section 4 of the

660 User’s Manual. The IDSEL assignment and their respective PCI_AD lines are shown

in Table 5. The addresses used for configuration are assigned as shown in Table 5.

2.5.5.2 650 Bridge compatible method

If it is not possible to use indexed BCRs to generate PCI configuration cycles, they can be

generated by an alternate method known as the 650 bridge compatible method. CPU ac-

cesses to the address range 2G+8M to 2G+16M cause the bridge to arbitrate for the PCI

bus and then to execute a type 0 PCI configuration transaction as described in the Pow-

erPC Reference Platform Specification and implemented by the IBM27–82650 PowerPC

to PCI Bridge. This is referred to as the 650 compatible configuration method. This method

of accessing PCI configuration space does not allow access to the PCI configuration regis-

ters in the bridge chip, and it should not be used unless required to maintain 650

compatibility.

When using the 650 bridge compatible configuration method, use only the specified ad-

dress. Using certain other addresses could cause bus contention because multiple PCI

slots could be selected. For example, using any CPU address in the range 8080 0000 to

80FF FFFF with both AD11 = 1 and AD12 = 1 causes selection of both the SIO and any

device in slot 1, possibly resulting in damage.

CPU

MPRH01TSU-02

Table 5. 660 Bridge Address Mapping of CPU Bus Transactions

Device IDSEL Line 60X Address* PCI Address

Intel SIO 82378ZB A/D 11 8080 08XXh 080 08XX

PCI slot 1 A/D 12 8080 10XXh 080 10XX

PCI slot 2 A/D 13 8080 20XXh 080 20XX

PCI slot 3 A/D 14 8080 40XXh 080 40XX

Reserved config scan A/D 18 8084 00XXh 084 00XX

Note: *This address is independent of contiguous I/O mode.

2.5.6 CPU to PCI Interrupt Acknowledge Transaction

Reading the interrupt acknowledge address (BFFF FFF0h) causes the bridge to arbitrate

for the PCI bus and then to execute a standard PCI interrupt acknowledge transaction. The

system interrupt controller in the ISA bridge claims the transaction and supplies the 1-byte

interrupt vector. There is no physical interrupt vector BCR in the bridge. Other PCI bus mas-

ters can initiate interrupt acknowledge transactions, but this may have unpredictable ef-

fects.

2.5.7 PCI Lock

The 660 Bridge does not set PCI locks when acting as the PCI master. The PCI_LOCK#

signal in the 660 Bridge supports resource locking of one 32-byte cache sector (block) of

system memory. Once a PCI lock is established, the block address is saved. Subsequent

accesses to that block from other PCI bus masters or from the CPU bus are retried until

the lock is released.

The bridge generates a flush-sector snoop cycle on the CPU bus when a PCI bus master

sets the PCI lock. The flush-sector snoop cycle causes the L1 and L2 caches to invalidate

the locked block, which prevents cache hits on accesses to locked blocks. If the L1 contains

modified data, the PCI cycle is retried and the modified data is pushed out to memory.

Note: The 60X processors do not have bus-locking functions. Instead, they use the load

reserve and store conditional instructions (lwarx and stwcx) to implement exclusive access.

To work with the lwarx and stwcx instructions, the 660 Bridge generates a flush-sector op-

eration to the CPU in response to the PCI read that begins a PCI lock.

2.6 CPU to ROM Transfers

The PowerPC Reference Platform Specification allocates the upper 8M of the 4G CPU ad-

dress space as ROM space. The reference design implements a 2M ROM space from

4G–2M to 4G. The actual ROM is a 512K device located at 4G–2M. The ROM is attached

to the 660 bridge via the PCI_AD lines. This mode is required when using the Intel SIO.

ROM device writes and write-protect commands are supported. See the 660 Bridge User’s

Manual for more information.

The ROM device attaches to the 660 bridge by means of control lines and the PCI_AD[31:0]

lines. When a CPU bus master reads from the ROM, the bridge masters a BCR transaction,

during which it reads the ROM and returns the data to the CPU. CPU writes to the ROM

and ROM write-protection operations are also forwarded to the ROM device.

Although connected to the PCI_AD lines, the ROM is not a PCI agent. The ROM and the

PCI agents do not interfere with each other because the ROM is under bridge control, and

CPU

34 MPRH01TSU-02

the bridge does not enable the ROM except during ROM cycles. The bridge accesses the

ROM by means of BCR transactions. Other PCI devices cannot read or write the ROM be-

cause they cannot generate BCR transactions.

2.6.1 CPU to ROM Read

At power-on, the 603/604 CPU comes up in BE Mode with the L1 cache disabled, and be-

gins fetching instructions (using 8-byte single beat reads) at address FFF0 0100 (4G – 1M

+ 100h). The reference design logic also resets to BE mode.

The system ROM address space is from 4G – 2M to 4G. Since the size of the installed ROM

is less than 2M (512K), it is mirrored every 512K throughout the ROM space. Location 0

of the 512K ROM is mapped to CPU bus addresses 4G–2M, 4G–1.5M, 4G–1M, and

4G–.5M.

The Flash is located on the PCI bus physically but not logically, and is 8 bits wide. This re-

quires the 660 Bridge to decode Flash address, run 8 cycles to PCI bus without activating

FRAME, accumulate the 8 single bytes of read data into an 8-byte group and generate a

TA# and an AACK# to complete the cycle. The CPU can also read the ROM using bursts,

but it receives the same 2 instructions from the ROM on each beat of the burst. For more

information, see the 660 Bridge User’s Manual.

Software can lock out the ROM using a 660 bridge BCR. When the CPU writes to any ROM

location while the ROM is locked out, the bridge signals normal transfer completion to the

CPU but does not write the data to the ROM. The CPU bus write to the locked flash bit in

the 660 bridge error status 2 register (bit 0 in index C5h) is set.

2.6.2 CPU to ROM Write

Writing to Flash is another very specialized cycle. Only one address (FFFF FFF0) is used

for writing data to Flash. The Flash address and data are both encoded into four bytes and

written using a 4-byte write transfer. Eight byte and burst transfers to the ROM are not sup-

ported. See the 660 Bridge User’s Manual.

Writes to Flash may be performed in either BE or LE mode. The data byte swapper in the

660 Bridge is gated according to endian mode. Writes in BE mode occur in natural se-

quence. However, address unmunging in LE mode has no effect on the cycle because the

addresses are ignored. Therefore, software must reverse the byte significance of the data

and address encoded into the store instructions for LE mode writes to the ROM.

2.6.2.1 ROM Write Protection

Flash write protection must be implemented within software. Port FFFF FFF1 can be used

to lock out all Flash writes. Writing any data to this port address locks out all Flash writes

until the 660 Bridge is hardware reset. In addition, the Flash itself has means to permanent-

ly lock out changing certain sectors by writing control sequences. Consult the Flash Specifi-

cation for details.

2.6.3 CPU to BCR Transfers

The 660 Bridge can be extensively programmed by means of the Bridge Control Registers

(BCR). See the 660 Bridge User’s Manual for a description of the operation and program-

ming of the 660 bridge BCRs.

PCI Bus

MPRH01TSU-02

Section 3

PCI Bus

The reference design includes a 32-bit PCI bus at frequencies up to 33MHz. The PCI bus

is compatible with the PCI Specification, revisions 2.0 and 2.1. The power supply voltage

is 3.3v, and the reference design components have 5v tolerant I/O. Up to three PCI cards

may be added to the system, which provides full hardware and software support for PCI

2.0 and 2.1 compliant PCI agents.

The PCI bus can be run an one-third, one-half, or the same frequency as the 60X CPU bus,

and is initially configured to run at one half of the CPU bus speed.

PCI bus activity initiated by the CPU is discussed in section 2. This section describes PCI

bus transactions initiated by a (non-660-bridge) PCI bus master.

3.1 PCI Transaction Decoding

When a PCI bus master initiates a transaction on the PCI bus, the transaction either misses

and is master aborted, or it is claimed by a PCI target. The target can be either the 660

bridge or another PCI target.

PCI Bus

36 MPRH01TSU-02

3.1.1 PCI Transaction Decoding By Bus Command

Table 6 shows the responses of the 660 bridge and other agents to various PCI bus trans-

actions initiated by a PCI bus master other than the 660 bridge. As shown in Table 6, the

660 bridge ignores (No response) all PCI bus transactions except PCI memory read and

write transactions, which it decodes as possible system memory accesses.

Table 6. Reference Design Responses to PCI_C[3:0] Bus Commands

C[3:0] PCI Bus Command Can a PCI Bus Master

Initiate this Transaction? 660 Bridge Response to

the Transaction Can Another PCI Target

Claim the Transaction?

0000 Interrupt Acknowledge No. Only the 660 Bridge is

allowed to initiate. None Yes. The ISA bridge is

intended to be the target.

0001 Special Cycle Yes None Yes

0010 I/O Read Yes None Yes

0011 I/O Write Yes None Yes

0100 Reserved No. Reserved None n/a

0101 Reserved No. Reserved None n/a

0110 Memory Read Yes System memory read Yes, if no address conflict.

0111 Memory Write Yes System memory write. Yes, if no address conflict.

1000 Reserved No. Reserved None n/a

1001 Reserved No. Reserved None n/a

1010 Configuration Read No. Only 660 Bridge. None Yes

1011 Configuration Write No. Only 660 Bridge. None Yes

1100 Memory Read Multiple Yes System memory read Yes, if no address conflict.

1101 Dual Address Cycle Yes None Yes

1110 Memory Read Line Yes System memory read Yes, if no address conflict.

1111 Memory Write and Invalidate Yes System memory write Yes, if no address conflict.

3.1.2 PCI Memory Transaction Decoding By Address Range

When a PCI bus master transaction is decoded by bus command as a system memory read

or write, the 660 bridge checks the address range. Table 7 shows the mapping of PCI bus

master memory accesses to system memory. This is the mapping that the 660 bridge uses

when it decodes the bus command to indicate a system memory access.

Table 7. Mapping of PCI Memory Space, Part 1

PCI Bus Address Other Conditions Target Cycle Decoded Target Address Notes

0 to 2G

IGN_PCI_AD31

Deasserted Not Decoded N/A No Response.

IGN_PCI_AD31

Asserted System Memory * 0 to 2G Snooped by caches.

2G to 4G System Memory * 0 to 2G Snooped by caches.

Note:

*Memory does not occupy this entire address space. Accesses to unoccupied space

are not decoded.

Unless the IGN_PCI_AD31 signal is asserted, PCI memory accesses in the 0 to 2G ad-

dress range are ignored by the 660 Bridge. There is no system memory access, no snoop

PCI Bus

MPRH01TSU-02

cycle, and the 660 bridge does not claim the transaction. When the IGN_PCI_AD31 signal

is asserted, the 660 Bridge maps PCI memory accesses from 0 to 2G directly to system

memory at 0 to 2G. PCI memory accesses from 2G to 4G are mapped to system memory

from 0 to 2G.

PCI memory access that are mapped to system memory cause the 660 bridge to claim the

transaction, access system memory, and arbitrate for the CPU bus and broadcast a snoop

operation on the CPU bus. A detailed description of the snoop process is presented in the

660 Bridge User’s Manual.

Table 8 gives a more detailed breakdown of the reference design response to PCI memory

transactions in the 0 to 2G range. Note that the preferred mapping of PCI memory, so that

it can be accessed both by the CPU and by PCI bus masters, is from 16M to 1G–2M.

Table 8. Mapping of PCI Memory Space, Part 2

PCI Bus Address Target Resource System Memory Address Snoop Address

2G to 4G System memory (1) 0 to 2G 0 to 2G

1G–2M to 2G Reserved (2)

No system memory access.

The 660 bridge ignores PCI

No snoop.

16M to 1G–2M PCI Memory

The 660 bridge ignores PCI

memory transactions in this

0 to 16M PCI/ISA Memory (3)

memory transactions in this

range.

Notes:

1) The 660 bridge maps PCI bus master memory transactions in the 2G to 4G range to sys-

tem memory, and the CPU is unable to initiate PCI memory transactions to this address

range, so do not map devices to this PCI memory address range.

2) The CPU (thru the 660 bridge) can not access the 1G–2M to 2G address range, so do

not map PCI devices herein unless the CPU will not access them.

3) Transactions initiated on the PCI bus by the ISA bridge on behalf of an ISA bus master

only (IGN_PCI_AD31 asserted for an SIO), are forwarded to system memory and broad-

cast snooped to the CPU bus from 0 to 16M. If this is not an ISA bus master transaction,

then the 660 bridge ignores it. Note that the 660 bridge will also forward PCI transactions

from 16M to 2G if IGN_PCI_AD31 is asserted during an ISA-bridge-mastered transac-

tion, and that this capability is not normally used.

PCI Bus

38 MPRH01TSU-02

3.1.3 PCI I/O Transaction Decoding

The 660 Bridge initiates PCI I/O transactions on behalf of the CPU. Other PCI bus masters

are also allowed to initiate PCI I/O transactions. Table 9 shows the reference design map-

ping of PCI I/O transactions. The 660 bridge ignores PCI I/O transactions.

PCI/ISA I/O is mapped to PCI I/O space from 0 to 64K. The ISA bridge subtractively de-

codes these transactions (and also PCI memory transactions from 0 to 16M). Other devices

may actively decode and claim these transactions without contention.

PCI I/O is assigned from 16M to 1G–8M.

Table 9. Mapping of PCI Master I/O Transactions

PCI Bus Address Target Resource Other System Activity

1G–8M to 4G Reserved (1)

The 660 Bridge ignores I/O transactions initiated by PCI

bus masters.

16M to 1G–8M PCI I/O devices

bus masters.

8M to 16M Reserved (1)

64K to 8M Reserved (2)

0 to 64K PCI/ISA I/O

Notes:

1) The CPU (thru the 660 bridge) can not access this address range, so do not map PCI

devices herein unless the CPU will not access them.

2) In contiguous mode, the CPU (thru the 660 bridge) can create PCI I/O addresses in the

64K to 8M range. In non–contiguous mode, the CPU can only access PCI addresses

from 0 to 64K.

3.1.4 ISA Master Considerations

Since the reference design implements IGN_PCI_AD31 and uses an Intel SIO, memory

transactions produced on the PCI bus by the ISA bridge on behalf of an ISA master, are

forwarded to system memory at the corresponding address (0 —16M).

If ISA masters are utilized and the SIO is programmed to forward their cycles to the PCI

bus, then no other PCI device (e.g. video) is allowed to be mapped at the same addresses

because contention would result.

The SIO chip contains registers to control which ranges of ISA addresses are forwarded

to the PCI bus.

ISA masters cannot access any PCI memory.

For more information on the handling of ISA bus master operations, see the 660 Bridge

User’s Manual and the SIO data book.

3.2 PCI Transaction Details

Details of the reference design implementation of various PCI transactions, including se-

quencing, timing, and interactions with the CPU bus, are found in the 660 Bridge User’s

Manual.

PCI Bus

MPRH01TSU-02

PCI bus masters are not able to access the boot ROM, the BCRs in the 660 bridge, or the

CPU bus.

3.2.1 Bus Snooping on PCI to Memory Cycles

Each time a PCI (or ISA) bus master accesses memory, (and once again for each time a

PCI burst crosses a cache block boundary) the 660 bridge broadcasts a snoop operation

on the CPU bus. If the CPU signals an L1 snoop hit by asserting ARTRY#, the 660 bridge

retries the PCI transaction. The ISA bridge then removes the grant from the PCI agent, who

(according to PCI protocol) releases the bus for at least one cycle and then arbitrates again.

Meanwhile, the 660 bridge grants the CPU bus to the CPU, allowing it to do a snoop push.

Then the PCI agent again initiates the original transaction.

During the transaction, the 660 bridge L2 cache is monitoring the memory addresses. The

L2 takes no action on L2 misses and read hits. If there is an L2 write hit, the L2 marks that

block as invalid, does not update the block in SRAM, and does not affect the PCI transac-

tion. L2 operations have no effect on PCI to memory bursts.

3.2.2 PCI to PCI Peer Transactions

Peer to peer PCI transactions are supported consistent with the memory maps of Table 6,

Table 7, Table 8, and Table 9, which together show the ranges of different bus command

transactions that are supported.

3.2.3 PCI to System Memory Transactions

PCI to system memory transactions are described in detail in the 660 Bridge User’s Manu-

al.

Single and burst transfers are supported. Bursts are supported without special software

restrictions. That is, bursts can start at any byte address and end on any byte address and

can be of arbitrary length. Also, the arbitration logic insures that the PCI does not monopo-

lize the PCI bus.

As per the PCI specification, the byte enables are allowed to change on each data phase.

This has no practical effect on reads, but is supported on writes. The memory addresses

linearly increment by 4 on each beat of the PCI burst. All PCI devices must use only linear

burst incrementing.

Table 10 shows which CAS# lines are activated when a PCI master writes memory. Note

that CAS[0]# refers to byte addresses 0 mod 8, CAS[1]# refers to byte addresses 1 mod

8, etc.. For read cycles, eight bytes of memory data are read on each access, but the master

receives only the desired 4 bytes. The bytes are read or written to memory independently

of BE or LE mode (the endian mode byte swappers are situated between the CPU and the

rest of the system, not between the PCI and the rest of the system).

In ECC mode, PCI to memory transactions that result in less than 8-byte writes, cause the

memory controller in the 660 bridge to execute a read-modify-write operation, during which

8 bytes of memory data are read, the appropriate bytes are modified, the ECC byte is modi-

fied, and then the resulting 8 bytes are written to memory.

PCI Bus

40 MPRH01TSU-02

Table 10. Active CAS# Lines – PCI to Memory Writes, BE or LE Mode

PCI_

AD[2]

Byte Enables BE[ ]# Column Address Selects CAS[ ]#

AD[2]

3 2 1 0 0 1 2 3 4 5 6 7

0 1 1 1 1

0 1 1 1 0 X

0 1 1 0 1 X

0 1 1 0 0 X X

0 1 0 1 1 X

0 1 0 1 0 X X

0 1 0 0 1 X X

0 1 0 0 0 X X X

0 0 1 1 1 X

0 0 1 1 0 X X

0 0 1 0 1 X X

0 0 1 0 0 X X X

0 0 0 1 1 X X

0 0 0 1 0 X X X

0 0 0 0 1 X X X

0 0 0 0 0 X X X X

1 1 1 1 1

1 1 1 1 0 X

1 1 1 0 1 X

1 1 1 0 0 X X

1 1 0 1 1 X

1 1 0 1 0 X X

1 1 0 0 1 X X

1 1 0 0 0 X X X

1 0 1 1 1 X

1 0 1 1 0 X X

1 0 1 0 1 X X

1 0 1 0 0 X X X

1 0 0 1 1 X X

1 0 0 1 0 X X X

1 0 0 0 1 X X X

1 0 0 0 0 X X X X

Note:

X = active. Blank = inactive. Byte enables would normally represent contiguous ad-

dresses. This table shows what would happen for all cases.

PCI Bus

MPRH01TSU-02

3.3 Bus Arbitration Logic

The reference design uses the Intel SIO as the PCI bus arbiter. The PCI arbiter sees the

660 bridge as one of several PCI agents. The order of priority for PCI arbitration is program-

mable, and is initially set to be:

1. 660 bridge (the SIO normally parks the bus on the 660 bridge)

2. PCI slot 1

3. PCI slot 2

4. PCI slot 3

For more information on arbitration, see section 9 on reference design initialization, and

see the PCI Arbitration Controller section of the SIO data book. See the reference design

schematics for the connection of the various PCI requests and grants.

There may be concurrency of cycles on the ISA bus (caused by DMA or ISA masters) with

PCI or CPU transactions as long as the ISA bus operations are not forwarded to the PCI

bus. Forwarding of ISA bus operations must wait for the ISA bridge to grant the PCI bus

to its ISA interface.

3.4 Other PCI Considerations

The reference design motherboard presents from 7 to 10 PCI loads to the bus, and at least

three additional PCI compliant agents/loads can be added to the PCI bus without exceed-

ing the loading parameters.

PCI Bus

42 MPRH01TSU-02

ISA Bus

MPRH01TSU-02

Section 4

ISA Bus

The reference design includes an ISA bus that is interfaced to the PCI bus by the ISA bus

bridge. Five ISA expansion slots are provided by the reference design. The reference de-

sign uses a buffered subset of the ISA bus, called the X-bus, to host onboard native I/O,

such as the real time clock and the keyboard and mouse controller.

4.1 The ISA Bridge

The ISA bridge function is provided by an Intel 82378ZB chip (SIO). It provides a PCI to

ISA bus bridge, with the following major functions:

SBridge between PCI and ISA

S8/16 bit ISA devices

S24 bit addressing on ISA

SPartially decodes native I/O addresses

SUnclaimed PCI memory address below 16MB forwarded to the ISA bus

SUnclaimed PCI I/O address below 64K forwarded to the ISA bus

SPowers up to an open condition (i.e., cycles may be passed to the ISA bus)

SGenerates ISA clock, with a programmable divide ratio of three or four

SAllows ISA mastering and has programmable decodes that map ISA memory

cycles to the PCI bus

S32–bit posted memory write data buffer (no I/O buffering)

SSeven channel ISA DMA controller

SFunction of two 83C37s with 32–bit extensions

SSupports 8– bit or 16–bit devices on the ISA bus

SSupports 32–bit addressing for ISA to PCI memory transfers

S8–byte bidirectional buffer for DMA data

STimer block (function of 82C54)

SInterrupt Controller (function of two 8259s)

SPCI bus arbiter.

SFunctions as PCI target during programming and ISA target cycles, and as bus mas-

ter during DMA or ISA master cycles

SGenerates ISA_REFRESH# signal to refresh ISA bus DRAM.

ISA Bus

44 MPRH01TSU-02

4.2 Address Ranges

The ISA bus address ranges which may be separately enabled in the ISA bus bridge for

forwarding to the PCI bus are:

S0 - 512K

S512K - 640K

S640K - 768K

S768K - 896K ( in 8 ranges of 16 K each)

S896K - 960K

S1M - xM (where x < or = 16) with the hole (see the SIO data book). The hole may

be 64K or 8M.

If an ISA DMA produces an address in the 0-16M range and this address is enabled in the

ISA bridge for forwarding to the PCI, the ISA bridge will initiate a PCI transaction which the

660 bridge will forward to system memory.

The 660 bridge uses medium timing when claiming ISA master originated cycles on the

PCI. It does not use subtractive decoding. Hence, ISA masters can only communicate with

other ISA devices or system memory. They may not communicate with PCI devices.

Warning: The software should not map any PCI memory at PCI addresses which ISA mas-

ters can create (those addresses between 0-16M which are programmed for forwarding

from ISA to PCI). This is because contention would result between the device mapped at

that address and the 660 bridge. Alternatively stated, ISA masters should not be allowed

to create accesses to system memory using any address between 0 and 16M that is

mapped to a PCI device, such as video.

4.3 ISA Bus Concurrency

ISA bus cycles which are not enabled for forwarding, including the hole, remain on the ISA

bus. That is, DMA or ISA bus master cycles on the ISA bus can run concurrently with PCI

or CPU cycles.

4.4 ISA Bus Masters and IGN_PCI_AD31

The ISA bridge supports ISA bus masters. System memory accesses from an ISA bus mas-

ter are designed to be mapped to the 0 to 16M range, and the ISA bridge forwards them

to the PCI bus at the same range, which is not compliant to the PowerPC Reference Plat-

form specification. Other PCI to system memory accesses however, are correctly mapped

to the 2G to 4G range (for system memory address range from 0 to 2G). In some architec-

tures this problem is handled by using the ISA_MASTER# signal, which is active during the

ISA bus master operation.

However, the ISA bridge allows ISA masters to run posted writes to system memory, with-

out latching in the accompanying ISA_MASTER# signal. In this situation, the ISA_MAS-

TER# signal is no longer synchronized to the ISA bus master operation.

To overcome this challenge, the reference design detects PCI memory transactions that

are initiated by the SIO. The reference design ANDs together GNT0#, GNT1#, and GNT2#,

ISA Bus

MPRH01TSU-02

to generate IGN_PCI_AD31, which is active high during the address phase of any PCI

transaction that is not initiated by one of the three possible PCI agents (besides the 660

bridge and the SIO). If the PCI transaction was not initiated by the 660 bridge, and if it is

a memory transaction, then the 660 bridge assumes that it is a system memory transaction

initiated on the PCI bus by the SIO on behalf of an ISA bus master, and so forwards it to

the correct system memory address in the 0 to 16M range.

As a consequence of this design, the ISA bridge must be programmed to map ISA DMA

(that is bound for system memory) to a PCI memory transaction using the 0 to 2G address

range, rather than the apparently correct 2G to 4G range. Since the DMA sourced PCI

transaction also causes IGN_PCI_AD31 to be asserted during the address phase of a PCI

transaction initiated by the ISA bridge, the 660 bridge will not do the usual inversion of the

highest order address bit, but will forward the transaction to system memory in the 0 to 2G

range.

Another consequence of the design is that the ISA bridge can not initiate peer to peer PCI

memory transactions, because no matter what the PCI address is, it will be claimed by the

660 bridge (if the address is that of a populated memory location) and mapped to system

memory, possibly causing various inappropriate results.

These are the only limitations on the normal operation of the ISA bridge that are caused

by the IGN_PCI_AD31 design, and there are no implications for other PCI or ISA agents,

which are totally unaffected by the situation.

ISA Bus

46 MPRH01TSU-02

4.5 DMA

The DMA controller in the ISA bridge consists of the functionality of two 82C37A DMA con-

trollers with 32-bit addressability extensions and enhanced functionality. The DMA request/

grant lines are connected on the reference design as shown in Table 11.

Table 11. DMA Assignments

DMA Channel Assignment or Connection

0ISA connectors

1ISA connectors

2ISA connectors

3ISA connectors

4Cascade in

5ISA connectors

6ISA connectors

7ISA connectors

4.5.1 Supported DMA Paths

DMA operations can be performed only:

SFrom ISA I/O mapped devices to ISA memory mapped devices, and

SFrom ISA I/O mapped devices to system memory (via the PCI bus). In these trans-

fers, the system memory address must be mapped to the PCI address range 0 to

2G (see section 4.4).

The DMA source device can be located on the X-bus. If the DMA target is ISA memory

mapped, it can also reside on the X-bus.

SISA DMA to PCI I/O devices is not allowed.

SISA DMA to PCI memory devices is not allowed.

SISA DMA from ISA memory mapped devices is not allowed.

4.5.2 DMA Timing

The DMA controller runs compatible cycles for all ISA to ISA DMA transfers. Type A, type

B and type F timing is available only for ISA I/O to system memory (via the PCI) DMA trans-

fers.

4.5.3 Scatter-Gather

The reference design permits the use of independent scatter-gather (SG) operations on

DMA channels 0-3 and 5-7. This operation chains together a number of DMA transfers to

different memory locations so that they appear as one DMA transfer. The SG command,

descriptor table, and status registers are relocatable via a configuration register in the ISA

bridge. The termination of an operation may be signaled to the software by configuring any

(or all) of the SG channels to use IRQ13 or by configuring the channel to signal end of pro-

cess (aka Terminal Count) to the DMA device. See the SIO data book for details.

ISA Bus

MPRH01TSU-02

4.6 X-Bus

The X-bus is a utility bus, an 8 bit buffered version of the ISA bus, implemented on the refer-

ence board to support the native I/O devices that are located on the reference board. X-bus

data transceiver U12 is controlled by the ISA bridge via XDIR (UBUSTR) and XDEN#

(UBUSOE#). Various devices are located on the X–bus.

4.6.1 Control Signal Decodes

The System I/O EPLD (Chandra) is a programmable logic device that uses the X-bus sig-

nals and the partial decode signals from the ISA bridge to decode chip selects for various

components. For more information on the System I/O EPLD, see that data sheet.

4.6.2 Keyboard/Mouse Controller

The reference design uses an Intel 8042AH as a keyboard and mouse controller, which

resides on the X-bus. The code used is the same version as used in IBM Personal System/2

machines. This microcode may differ from other 8042 type keyboard controllers. These dif-

ferences are usually only significant when porting AIX to the system (for more information

contact your IBM representative. This device contains several registers. See the data sheet

for more information.

4.6.3 Real Time Clock (RTC)

The reference design uses a Dallas Semiconductort DS1385S to provide the real time

clock (TOD or RTC) function. This device is PC compatible and resides on the X-bus. It fea-

tures an additional 4K of NVRAM and a replaceable battery. This device contains several

registers. See the data sheet for more information.

4.6.4 PCI Adapter Card Presence Detect Register

The reference design uses U20 to buffer the PCI adaptor card presence detection bits onto

the X-bus under control of the system I/O EPLD. These bits report in pairs, and do not con-

tain any information about the identity of the card. They merely report on its presence.

ISA Port 080C Read Only Reset n/a

D0D1D2D3D4D5D6D7

MSB LSB

Reserved

PCI Slot 0 Presence Detect

PCI Slot 1 Presence Detect

PCI Slot 2 Presence Detect

Bits 7:6 Reserved

Bits 5:4 PCI Slot 2 Presence Detect Bits. 00 = Present, 11 = No PCI card installed.

Bits 3:2 PCI Slot 2 Presence Detect Bits. 00 = Present, 11 = No PCI card installed.

Bits 1:0 PCI Slot 2 Presence Detect Bits. 00 = Present, 11 = No PCI card installed.

ISA Bus

48 MPRH01TSU-02

4.6.5 L2 SRAM Identification Register

The reference design uses U19 to buffer the SRAM identification/presence detect bits from

the SRAM socket onto the X-bus under control of the system I/O EPLD.

ISA Port 080D Read Only Reset n/a

D0D1D2D3D4D5D6D7

MSB LSB

Reserved

SRAM ID[2:0]

Table 12. DRAM Module Presence Detect Bit Encoding

SRAM ID [2:0]

SRAM Module Identification

ID3 ID2 ID1

0 0 0 512K Synchronous

0 0 1 256K Synchronous

0 1 0 Reserved

0 1 1 Reserved

1 0 0 512K Asynchronous

1 0 1 256K Asynchronous

1 1 0 1M Asynchronous

1 1 1 L2 SRAM module not present

4.6.6 Planar ID Detection Register

Revision information on the planar (motherboard) is buffered onto the X-bus by U18, under

control of the system I/O EPLD.

ISA Port 0852 Read Only Reset n/a

D0D1D2D3D4D5D6D7

MSB LSB

ID Bits[7:0]

Table 13. Planar ID Encoding

Planar

ID[7:0] CPU CPU Internal Clock/

CPU Bus Clock/

PCI Bus Clock

Schematic

0C 603 66/66/33 MPRH02SCU–01

0D 603e 99/66/33 MPRH02SCU–01

0E 604 132/66/33 MPRH02SCU–01

other — — Reserved

ISA Bus

MPRH01TSU-02

4.6.7 DRAM Presence Detection

DRAM module presence and identification data is hard coded into the pinout of the SIMM

(or DIMM) by shorting particular pins to ground or no-connecting them on the SIMM itself.

The reference design uses U17 and U40 to buffer the presence detect bits from the DRAM

sockets onto the X-bus under control of signals from the system I/O EPLD. This information

appears as the DRAM SIMM 1-2 Memory ID Register and the DRAM SIMM 3-4 Memory

ID Register.

4.6.7.1 DRAM SIMM 1-2 Memory ID Register

ISA Port 0880 Read Only Reset n/a

This register indicates the ID bits associated with SIMMs 1 and 2.

D0D1D2D3D4D5D6D7

MSB LSB

ID Bits[7:0]

Bits 7:4 SIMM 2 ID bits. See Table 14.

Bits 3:0 SIMM 1 ID bits. See Table 14.

4.6.7.2 DRAM SIMM 3-4 Memory ID Register

ISA Port 0881 Read Only Reset n/a

This register indicates the ID bits associated with SIMMs 3 and 4.

D0D1D2D3D4D5D6D7

MSB LSB

ID Bits[7:0]

Bits 7:4 SIMM 4 ID bits. See Table 14.

Bits 3:0 SIMM 3 ID bits. See Table 14.

Table 14. DRAM Module Presence Detect Bit Encoding

Presence Detect Bits

DRAM Module Identification

PD4 PD3 PD2 PD1

1 0 0 0 4 MB (1M x 36b) 70ns

1 0 1 1 8 MB (2M x 36b) 70ns

1 0 1 0 16 MB (4M x 36b) 70ns

1 1 0 1 32 MB (8M x 36b) 70ns

1 1 1 1 No DRAM module installed.

Other encodings Not currently defined.

ISA Bus

50 MPRH01TSU-02

4.7 Miscellaneous

4.7.1 Speaker Support

The reference design has a connector for a small speaker. The speaker output is driven

by the timer 2 signal from the ISA bridge. The intended speaker is a typical PC type, 8 ohms

and .5W.

EPLD

MPRH01TSU-02

Section 5

System I/O EPLD

Note:

The System I/O EPLD generates system control register access signals from X-bus I/O

port transactions, supports power management, and provides various other system func-

tions.

In this section, the system I/O EPLD is referred to as the EPLD.

The EPLD is a programmed Alterat EPM5130QC100 electrically programmable logic de-

vice. For timing and electrical specifications, see that data sheet.

5.1 System Register Support

The EPLD supports both internal and external registers.

5.1.1 External Register Support

The EPLD supports a group of external registers, which are latches or other devices that

are physically located in a device other than the EPLD. As shown in Figure 5, the EPLD

supplies control signals to the external registers, based on a decode of the address and

control lines of the X-bus (or ISA bus). In response to the signals from the EPLD, the exter-

nal register either reads or writes data to the X-bus.

Figure 5. Typical External Register

C DA EPLD

Address

Control Strobes

External Register

or Device

Possible

Other

Circuitry

X-bus or ISA

EPLD

52 MPRH01TSU-02

For the external registers that the EPLD supports, Table 15 shows the external register,

the ISA I/O port address, and the supplied control signal(s).

Table 15. External Register Support

ISA Port

Address Register Read/

Write Register

Location Signal Strobe or

Function

0060 or

0062 or

0064 or

0066

Keyboard Controller

Registers R/W Keyboard

Controller KBD_CS# (as-

serted for an ac-

cess to any of

these addresses)

Address Decode

0070 RTC Address Latch Enable W/O RTC RTC_ALE Write strobe

0071

RTC Data

Write

RTC

RTCWR# Write strobe

Read RTCDS# Read strobe

0074 NVRAM Address Low Byte W/O NVRAM AS0# Address Decode

0075 NVRAM Address High Byte W/O NVRAM AS1# Address Decode

0077

NVRAM Data

Write

NVRAM

NVRAMWE# Write Strobe

Read NVRAMOE# Read Strobe

080C Equipment Present R/O Board PRSNT_RD# Read Strobe

080D L2 Cache Status Register R/O Board L2_STATUS_RD# Read Strobe

0852 Planar ID R/O Board PLANAR_ID_RD# Read Strobe

0880 DRAM Presence Detect 1/2 R/O Board DRAM_PD_RD1# Read Strobe

0881 DRAM Presence Detect 3/4 R/O Board DRAM_PD_RD2# Read Strobe

5.1.2 Internal Registers

The EPLD contains a group of internal registers, which are accessed via the ISA bus I/O

port address shown for each register.

5.1.2.1 Storage Light Register

ISA Port 0808 Read/Write Reset to xxxx xxx0

This register controls the HDD_LED# output of the EPLD. This signal normally controls the

hard disc drive activity LED.

D0D1D2D3D4D5D6D7

Reserved

Hard Disk Activity Light

MSB LSB

Bit 0 Hard Disk Activity Light:. . . 0 = Turn light off (negate HDD_LED#).

1 = Turn light on (assert HDD_LED#).

EPLD

MPRH01TSU-02

5.1.2.2 Power Management Control Register 1

ISA Port 082A Read/Write Reset to xxxx xxxx

D0D1D2D3D4D5D6D7

MSB LSB

Serial Data Bit

Command to 87C750

I/O Strobe Key

Reserved

This register is part of the power management system. For a detailed functional description

of the operation of this register, see the 603/604 Reference Design Power Management

Specification.

5.1.2.3 Power Management Control Register 2

ISA Port 082B Read/Write Reset to 0xxx 0xx0

D0D1D2D3D4D5D6D7

MSB LSB

Reserved

Reset PM Controller/Status

Reserved

IRQ12 Mask

CPU1 ROM Completed

Reserved

This register is part of the power management system. For a detailed functional description

of the operation of this register, see The 603/604 Reference Design Power Management

Specification.

5.1.2.4 Freeze Clock Register (FCR) Low

ISA Port 0860 Read/Write Reset to 0000 0000

D0D1D2D3D4D5D6D7

MSB LSB

Freeze Clock Register[7:0]

See section 5.1.2.5.

5.1.2.5 Freeze Clock Register (FCR) High

ISA Port 0862 Read/Write Reset to xxx0 0000

D0D1D2D3D4D5D6D7

MSB LSB

Freeze Clock Register [12:8]

Reserved

EPLD

54 MPRH01TSU-02

The freeze clock register (FCR) is a 13 bit register that is accessed by the system via the

X-bus as two 8-bit registers, as shown in this and the previous sections. Once triggered,

the FCR data is shifted out as serial data on FRZ_DATA_OUT.

This function is intended for use with the MPC970 clock chip, as is done in the reference

design. The MPC970 contains an input shift register, the input of which (Frz_Data) is con-

nected to FRZ_DATA_OUT. ISA_CLK is used to clock the data from the EPLD to the

MPC970.

EPLD will shift the freeze clock data out of the FCR in response to either one of two triggers:

1. A write to ISA I/O port 862, or

2. A low to high transition on the UNFREEZE input iff bit 0 and bit 1 of the FCR are

high.

After triggering the data transfer, wait at least 2.3us for the transfer to complete before

accessing the FCR or retriggering the data transfer.

This is a one way serial data transfer between the two devices. Reading the FCR returns

the contents of the FCR, and does not cause a read of the data in the MPC970 register.

A 1 in a bit position freezes the corresponding clock output of the MPC970. For details of

the data transfer operation and the meaning of the data, see the MPC970 data sheet.

5.2 Signal Descriptions

Table 16 shows the active signals of the EPLD. Pins not shown should not be connected.

Table 16. Signal Descriptions

Signal Name Pin I/O Description

X-bus Interface Signals

ECS[2:0] 21, 22, 59 IEncoded Chip Select [2:0]. Encoded chip selects for pe-

ripheral devices supported by the ISA I/O Bridge. Used by

EPLD X-bus I/O port address decoders. From SIO.

ECSEN# 60 I Encoded Chip Select Enable. Asserted to enable the base

decoder. Negated to select the option decoder. Used by

EPLD X-bus I/O port address decoders. From SIO.

XA[7:0] 61 ,64, 65,

66, 67, 70,

71, 72.

IX–address bus [7:0]. Used by EPLD X-bus I/O port ad-

dress decoders.

XD[7:0] 31, 32, 33,

92, 73, 74,

34, 95.

I/O

24mA X-data bus [7:0]. Used by EPLD to transfer data.

XIOW# 16 I X-bus I/O Write. This signal indicates that the system is

writing to an X-bus I/O device. Used by EPLD X-bus I/O

port address decoders.

XIOR# 9 I X-bus I/O Read. This signal indicates that the system is

reading from an X-bus I/O device. Used by EPLD X-bus

I/O port address decoders.

External Register Support Signals

AS0# 50 O

6mA NVRAM address register low byte write strobe. EPLD as-

serts this signal to write to X–bus port 0074.

AS1# 49 O

6mA NVRAM address register high byte write strobe. EPLD

asserts this signal to write to X–bus port 0075.

EPLD

MPRH01TSU-02

Table 16. Signal Descriptions (Continued)

Signal Name DescriptionI/OPin

External Register Support Signals

DRAM_PD_RD1# 57 O

6mA DRAM SIMM presence detect read enable 1. EPLD as-

serts this signal to read X-bus port 0880.

DRAM_PD_RD2# 56 O

6mA DRAM SIMM presence detect read enable 2. EPLD as-

serts this signal to read X-bus port 0881.

KYBD_CS# 98 O

6mA Keyboard chip select. EPLD asserts this signal to read

X-bus ports 0060, 0062, 0064, and 0066.

L2_STATUS_RD# 54 O

6mA L2 cache status register read strobe. EPLD asserts this

signal to read X-bus port 080D.

NVRAMOE# 1 O

6mA NVRAM output enable (read strobe). EPLD asserts this

signal to read X–bus port 0076. This normally causes a

read of the NVRAM data stored at the location contained

in the NVRAM address register.

NVRAMWE# 53 O

6mA NVRAM data write strobe. EPLD asserts this signal to

write to X–bus port 0076. This normally causes the data

associated with this write to be written into the NVRAM

location contained in the NVRAM address register.

PLANAR_ID_RD# 52 O

6mA Planar ID read. EPLD asserts this signal to read X-bus

port 0852.

PRSNT_RD# 41 O

6mA Equipment present register read. EPLD asserts this signal

to read X-bus port 080C.

RTC_ALE 48 O

6mA Real time clock address latch enable. EPLD asserts this

signal to write X-bus port 0070.

RTCDS# 51 O

6mA Real time clock read strobe. EPLD asserts this signal to

read X–bus port 0071.

RTCWR# 35 O

6mA Real time clock write strobe. EPLD asserts this signal to

write to X–bus port 0071.

Interrupt Signals

IRQ1 86 O Interrupt request 1. Latched active when IRQ1_IN is as-

serted. Negated when KYBD_CS# is asserted.

IRQ1_IN 89 I Keyboard interrupt. EPLD is designed to intercept the

keyboard interrupt between the keyboard and the ISA bus

bridge. Either connect IRQ1 and IRQ1_IN as shown in the

reference design, or disconnect both signals from the sys-

tem (routing the keyboard interrupt to the ISA bus bridge),

or see the 603/604 Reference Design Power Manage-

ment Guide.

IRQ12 36 I Interrupt request 12 input. Connect to system IRQ12, the

mouse interrupt. Also see the 603/604 Reference Design

Power Management Guide.

System Clock Interface Signals

FRZ_DATA_OUT 90 O

6mA Freeze data out. Serial data stream to MPC970 clock

chip. See the MPC970 data sheet.

ISA_CLK 20 I ISA clock. Used to clock the freeze serial data stream to

the MPC970 clock chip. See the MPC970 data sheet.

Also see the 603/604 Reference Design Power Manage-

ment Guide.

Power Management Signals (not used in release 2.0 or 2.1)

EPLD

56 MPRH01TSU-02

Table 16. Signal Descriptions (Continued)

Signal Name DescriptionI/OPin

Power Management Signals (not used in release 2.0 or 2.1)

83CX_RESET 91 O

6mA Power management controller reset. No-connect or con-

nect as shown in the 603/604 Reference Design Power

Management Guide.

ACTIVITY# 58 O

6mA Activity. No-connect or connect as shown in the 603/604

Reference Design Power Management Guide.

CMD_STATE# 8 I Power manangement controller command state. No-con-

nect or connect as shown in the 603/604 Reference De-

sign Power Management Guide.

EXT_ACTVTY# 3 I External activity. No-connect or pull low or connect as

shown in the 603/604 Reference Design Power Manage-

ment Guide.

IO_STROBE# 99 O

6mA I/O strobe. No-connect or connect as shown in the

603/604 Reference Design Power Management Guide.

PROC_RDY 83 I Power management controller ready. No-connect or con-

nect as shown in the 603/604 Reference Design Power

Management Guide.

RWD0 96 I/O

24mA Power management controller serial read/write data bit.

No-connect or connect as shown in the 603/604 Refer-

ence Design Power Management Guide.

UNFREEZE 82 I Unfreeze. No-connect or connect as shown in the

603/604 Reference Design Power Management Guide.

Other Signals

HDD_LED# 100 O

6mA Hard disk drive activity light. EPLD asserts this signal

while bit 0 of the storage light register (port 0808) is 1.

This signal normally indicates hard disk drive activity.

RESET# 10 I System reset. Used by EPLD to reset internal state ma-

chines and internal registers.

VCC 18, 19, 43,

44, 68, 69,

93, 94

I +5V:

GND 12, 13, 37,

38, 62, 63,

87, 88

I GROUND:

EPLD

MPRH01TSU-02

5.3 EPLD Design Equations

5.3.1 Fit File

–– MAX+plus II Compiler Fit File

–– Version 5.0 8/5/94

–– Compiled: 05/05/95 14:44:22

BEGIN

DEVICE = ”EPM5130WC–1”;

”A0” : INPUT_PIN = 72 ;

”A1” : INPUT_PIN = 71 ;

”A2” : INPUT_PIN = 70 ;

”A3” : INPUT_PIN = 67 ;

”A4” : INPUT_PIN = 66 ;

”A5” : INPUT_PIN = 65 ;

”A6” : INPUT_PIN = 64 ;

”A7” : INPUT_PIN = 61 ;

”/CMD_STATE” : INPUT_PIN = 8 ; –– LC8

”/ECSEN” : INPUT_PIN = 60 ;

”ECS0” : INPUT_PIN = 59 ;

”ECS1” : INPUT_PIN = 22 ;

”ECS2” : INPUT_PIN = 21 ;

”/EXT_ACTVTY” : INPUT_PIN = 3 ; –– LC3

”IRQ1” : INPUT_PIN = 89 ; –– LC103

”IRQ12” : INPUT_PIN = 36 ; –– LC38

”ISA_CLK” : INPUT_PIN = 20 ;

”PROC_RDY” : INPUT_PIN = 83 ; –– LC99

”/RESET” : INPUT_PIN = 10 ;

”UNFREEZE” : INPUT_PIN = 82 ; –– LC98

”/XIOR” : INPUT_PIN = 9 ;

”/XIOW” : INPUT_PIN = 16 ;

”/ACTIVITY” : OUTPUT_PIN = 58 ; –– LC72

”/AS0” : OUTPUT_PIN = 50 ; –– LC56

”/AS1” : OUTPUT_PIN = 49 ; –– LC55

”/DRAM_PD_RD1” : OUTPUT_PIN = 57 ; –– LC71

”/DRAM_PD_RD2” : OUTPUT_PIN = 56 ; –– LC70

”FRZ_DATA_OUT” : OUTPUT_PIN = 90 ; –– LC104

”/HDD_LED” : OUTPUT_PIN = 100 ; –– LC120

”/IO_STROBE” : OUTPUT_PIN = 99 ; –– LC119

”IRQ1_OUT” : OUTPUT_PIN = 86 ; –– LC102

”/KYBD_CS” : OUTPUT_PIN = 98 ; –– LC118

”/L2_STATUS_RD” : OUTPUT_PIN = 54 ; –– LC68

”/NVRAMOE” : OUTPUT_PIN = 1 ; –– LC1

”/NVRAMWE” : OUTPUT_PIN = 53 ; –– LC67

”/PLANAR_ID_RD” : OUTPUT_PIN = 52 ; –– LC66

”/PRSNT_RD” : OUTPUT_PIN = 41 ; –– LC49

EPLD

58 MPRH01TSU-02

”RTC_ALE” : OUTPUT_PIN = 48 ; –– LC54

”/RTCDS” : OUTPUT_PIN = 51 ; –– LC65

”/RTCWR” : OUTPUT_PIN = 35 ; –– LC37

”83CX_RESET” : OUTPUT_PIN = 91 ; –– LC113

”RWD0” : BIDIR_PIN = 96 ; –– LC116

”XD0” : BIDIR_PIN = 95 ; –– LC115

”XD1” : BIDIR_PIN = 34 ; –– LC36

”XD2” : BIDIR_PIN = 74 ; –– LC82

”XD3” : BIDIR_PIN = 73 ; –– LC81

”XD4” : BIDIR_PIN = 92 ; –– LC114

”XD5” : BIDIR_PIN = 33 ; –– LC35

”XD6” : BIDIR_PIN = 32 ; –– LC34

”XD7” : BIDIR_PIN = 31 ; –– LC33

”CLKFF0” : LOCATION = LC48 ;

”CLKFF1” : LOCATION = LC96 ;

”CLKFF2” : LOCATION = LC95 ;

”CLKFF3” : LOCATION = LC94 ;

”CLKFF4” : LOCATION = LC47 ;

”CLKFF5” : LOCATION = LC46 ;

”CLKFF6” : LOCATION = LC45 ;

”CLKFF7” : LOCATION = LC44 ;

”CLKFF8” : LOCATION = LC43 ;

”CLKFF9” : LOCATION = LC93 ;

”CLKFF10” : LOCATION = LC92 ;

”CLKFF11” : LOCATION = LC91 ;

”CLKFF12” : LOCATION = LC112 ;

”CNTR0” : LOCATION = LC111 ;

”CNTR1” : LOCATION = LC110 ;

”CNTR2” : LOCATION = LC109 ;

”CNTR3” : LOCATION = LC108 ;

”DOUBLE_FRZ” : LOCATION = LC90 ;

”DOUBLE_SNC” : LOCATION = LC107 ;

”FREEZEFF” : LOCATION = LC106 ;

”GEN_STOP_BITFF” : LOCATION = LC105 ;

”GPCS0” : LOCATION = LC89 ;

”PWR_REG21” : LOCATION = LC80; ––IRQ12_MASK

”PWR_REG22” : LOCATION = LC79 ;

”SHIFT_ENFF” : LOCATION = LC103 ; –– PIN 89

”SNC_FREEZE” : LOCATION = LC99 ; –– PIN 83

”SNC_SHIFT_ENFF” : LOCATION = LC98 ; –– PIN 82

”SNC_UNFREEZE” : LOCATION = LC101 ; –– PIN 85

”START_SHIFTFF” : LOCATION = LC100 ; –– PIN 84

”UNFREEZEFF” : LOCATION = LC97 ; –– PIN 81

END;

EPLD

MPRH01TSU-02

5.3.2 TDF File

%***************************************************************************%

%****** AHDL SOURCE CODE FOR: SIO/XBUS INTERFACE CONTROL *****************%

%***************************************************************************%

SUBDESIGN chandra(

% DEFINE PRIMARY INPUTS AND OUTPUTS %

A[7..0] :INPUT; % A7 is MSB and A0 is LSB %

ECS[2..0] :INPUT; % ECS2 is MSB and ECS0 is LSB %

/ECSEN :INPUT;

/XIOR :INPUT;

/XIOW :INPUT;

/RESET :INPUT;

/CMD_STATE :INPUT;

PROC_RDY :INPUT;

/EXT_ACTVTY :INPUT;

IRQ1 :INPUT;

IRQ12 :INPUT;% Freeze Clock %

ISA_CLK :INPUT;

UNFREEZE :INPUT;

/PLANAR_ID_RD :OUTPUT;

/PRSNT_RD :OUTPUT;

/L2_STATUS_RD :OUTPUT;

/DRAM_PD_RD1 :OUTPUT;

/DRAM_PD_RD2 :OUTPUT;

/KYBD_CS :OUTPUT;

IRQ1_OUT :OUTPUT;

RTC_ALE :OUTPUT;

/RTCDS :OUTPUT;

/RTCWR :OUTPUT;

/AS0 :OUTPUT;

/AS1 :OUTPUT;

/NVRAMWE :OUTPUT;

/NVRAMOE :OUTPUT;

/HDD_LED :OUTPUT;

83CX_RESET :OUTPUT;

/ACTIVITY :OUTPUT;

/IO_STROBE :OUTPUT;

FRZ_DATA_OUT :OUTPUT;

XD[7..0] :BIDIR; % XD7 is MSB and XD0 is LSB %

RWD0 :BIDIR;

)

VARIABLE % Misc. Variables%

GPCS0 :NODE;

HDD_LEDFF :SRFF;

D[7..0] :NODE;

XD_TRI_OE :NODE;

LIGHT_STRB :NODE;

INT1FF :DFF; % Keyboard interput latch %

CLRINT1 :NODE; % Power Management Variables%

EPLD

60 MPRH01TSU-02

PWR_REG1_STRB :NODE;

PWR_REG2_STRB :NODE;

PWR_REG2[2..0] :SRFF;

83CX_CS :NODE;

RWD0_STRB :NODE;

IRQ12_MASK :NODE; % Freeze Clock Variables %

CLKFF[12..0] :DFFE;

SHIFT_ENFF :SRFF;

CNTR[3..0] :DFF;

SNC_SHIFT_ENFF :DFFE;

START_SHIFTFF :SRFF;

CLKFF_WR :NODE;

CLKFF_STRB :NODE;

CLKFF_SELL :NODE;

CLKFF_SELH :NODE;

GEN_START_BIT :NODE;

GEN_STOP_BITFF :DFF;

STOP_SHIFT :NODE;

UNFREEZEFF :DFFE; % Unsynchronized UNFREEZE %

SNC_UNFREEZE :DFF; % Synchronized UNFREEZE %

DOUBLE_SNC :DFF; % Double Synchronized UNFREEZE %

FREEZEFF :DFFE; % Unsynchronized FREEZE %

SNC_FREEZE :DFF; % Synchronized FREEZE %

DOUBLE_FRZ :DFF; % Double Synchronized FREEZE %

BEGIN%*****%

% CHANDRA uses SIO’s General Purpose Register Decode 0 –– Software sets %

% to 800–8FF to enable the following decoded signals. %

GPCS0 = LCELL (!ECS[2] & ECS[1] & !ECS[0] & /ECSEN);

% Hard Disk Light I/O address range : 0808 %

LIGHT_STRB = !A[7] & !A[6] & !A[5] & !A[4] & A[3] & !A[2]

& !A[1] & !A[0] & GPCS0; HDD_LEDFF.s = XD[0] & LIGHT_STRB;

HDD_LEDFF.r = !XD[0] & LIGHT_STRB;

HDD_LEDFF.clk= GLOBAL(/XIOW);

HDD_LEDFF.clrn= (/RESET);

/HDD_LED = !HDD_LEDFF.q;

% Equipment present Read Command 1 (I/O address range: 080C) %

/PRSNT_RD = ! (!A[7] & !A[6] & !A[5] & !A[4] & A[3] & A[2]

& !A[1] & !A[0] & GPCS0 & !/XIOR);

% Equipment present Read Command 2 (I/O address range: 080D) %

/L2_STATUS_RD = !(!A[7] & !A[6] & !A[5] & !A[4] & A[3] & A[2]

& !A[1] & A[0] & GPCS0 & !/XIOR);

% External/Internal Planar ID I/O address range: 0852 %

/PLANAR_ID_RD = !(!A[7] & A[6] & !A[5] & A[4] & !A[3] & !A[2]

& A[1] & !A[0] & GPCS0 & !/XIOR);

EPLD

MPRH01TSU-02

% Keyboard Chip Select I/O address range = 0060, 0062, 0064, 0066– %

/KYBD_CS = !(!ECS[2] & ECS[1] & !ECS[0] & !/ECSEN);

% Keyboard interupt (INT1) Clear = KBD_CS qualified with XIOR %

CLRINT1 =!ECS[2] & ECS[1] & !ECS[0] & !/ECSEN & !/XIOR; INT1FF.d=VCC;

INT1FF.clk = IRQ1; % Set Keyboard INT1 latch on rising edge of IN1 %

INT1FF.clrn = /RESET & !CLRINT1;

IRQ1_OUT = INT1FF.q;

% RTC_ALE I/O address 0070 %

RTC_ALE = (!A[2] & !A[1] & !A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOW) ;

% RTCWR I/O address 0071 %

/RTCWR = !(!A[2] & !A[1] & A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOW);

% RTCDS I/O address 0071 %

/RTCDS = !(!A[2] & !A[1] & A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOR);

% Nvram AS0 I/O address 0074 %

/AS0 = !(A[2] & !A[1] & !A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOW);

% Nvram AS1 I/O address range: 0075 %

/AS1 = !(A[2] & !A[1] & A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOW);

% Nvram RTC WER I/O address 0077 %

/NVRAMWE = !(A[2] & A[1] & A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOW);

% Nvram RTC OER I/O address range: 0077 %

/NVRAMOE = !(A[2] & A[1] & A[0] & !ECS[2] & !ECS[1] & !/ECSEN & !/XIOR)

; %%

% DRAM_PD_RD1 enables Present Detect I/O address range: 0880 %

/DRAM_PD_RD1 = !(A[7] & !A[6] & !A[5] & !A[4] & !A[3] & !A[2] & !A[1]

& !A[0] & GPCS0 & !/XIOR);

EPLD

62 MPRH01TSU-02

% DRAM_PD_RD2 enables Present Detect I/O address range: 0881 %

/DRAM_PD_RD2 = !(A[7] & !A[6] & !A[5] & !A[4] & !A[3] & !A[2] & !A[1]

& A[0] & GPCS0 & !/XIOR);

%*************************************************************************%

% POWER MANAGEMENT %

% %

%*************************************************************************%

% Write Power Control Register 1 I/O address: 082A %

% %

% (MSB) Bits 7–5 Reserved %

% Bit 4 I/O Strobe Key (W/O) %

% Bits 3–1 Data/Command B[3..1] to 83C750 (W/O) %

% (LSB) Bit 0 83C750 D0 (R/W) %

%*************************************************************************%

83CX_CS = (!A[7] & !A[6] & A[5] & !A[4] & A[3] & !A[2] & A[1] & GPCS0);

PWR_REG1_STRB = 83CX_CS & !A0;

% –Write ZERO to 83C750 %

RWD0_STRB = (PWR_REG1_STRB & !/XIOW & !XD[0]);

RWD0 = TRI (GND, RWD0_STRB);

% 83C750 I/O Strobe Key %

/IO_STROBE = !(XD[4] & PWR_REG1_STRB & !/XIOW & PROC_RDY

& !83CX_RESET);

%IO_CHRDY = TRI (GND, IO_STRB);%

%*************************************************************************%

% Write Power Control Register 2 I/O address: 082B %

% %

% (MSB) Bit 7 CPU1 ROM Completed (Reset by /RESET, W/R) %

% Bit 6 Reserved %

% Bit 5 Reserved %

% Bit 4 Reserved %

% Bit 3 IRQ12 Mask (Reset by /RESET) (W/R) %

% Bits 2–1 Reserved %

% (LSB) Bit 0 Reset 83C750 (W/O) %

%*************************************************************************%

PWR_REG2_STRB = 83CX_CS & A0;

PWR_REG2[1].s = XD[3] & PWR_REG2_STRB;

PWR_REG2[1].r = !XD[3] & PWR_REG2_STRB;

PWR_REG2[1].clrn = (/RESET);

PWR_REG2[2].s = XD[7] & PWR_REG2_STRB;

PWR_REG2[2].r = !XD[7] & PWR_REG2_STRB;

PWR_REG2[2].clrn = (/RESET);

PWR_REG2[0].s = XD[0] & PWR_REG2_STRB;

PWR_REG2[0].r = !XD[0] & PWR_REG2_STRB;

EPLD

MPRH01TSU-02

PWR_REG2[0].clrn = VCC;

PWR_REG2[].clk = GLOBAL(/XIOW);

83CX_RESET = PWR_REG2[0].q;

IRQ12_MASK = PWR_REG2[1].q;

%*************************************************************************%

% This output should be NORed with IRQ1 and EXTACTIV signals externally to%

% provide a real Activity Alert to the 87C350 (because of restriction of %

% CHANDRA’s IO pins.) %

%********************%

/ACTIVITY = !(IRQ1 # !IRQ12_MASK & IRQ12 # !/EXT_ACTVTY);

%*************************************************************************%

% Freeze Clock Logic – Refer to the Motorola MC88LV970 PLL Clock Driver %

% Specification for information on Freeze Data protocol. %

% %

% Freeze Clock Logic contains a 12 Bit serial shift register %

% Decode the low order CLKFF[7..0] on addresses: 0860 –0861 %

% Decode the high order CLKFF[12..8] on addresses: 0862 –0863 %

%*************************************************************************%CLK

FF_STRB = (!A[7] & A[6] & A[5] & !A[4] & !A[3] & !A[2] & GPCS0);

CLKFF_WR = CLKFF_STRB & !/XIOW;

CLKFF_SELL = CLKFF_STRB & !A[1];

CLKFF_SELH = CLKFF_STRB & A[1];

CLKFF[12..0].prn = VCC;

CLKFF[12..0].clrn = /RESET;

CLKFF[12..0].ena = START_SHIFTFF.q # CLKFF_WR;

CLKFF[12..0].clk = ISA_CLK;

if START_SHIFTFF.q then % Shift with wraparound %

CLKFF[11..0].d = CLKFF[12..1].q;

CLKFF[12].d = CLKFF[0].q;

else if CLKFF_SELL then % Write to CLKFF[7..0] %

CLKFF[7..0].d = XD[7..0];

CLKFF[12..8].d = CLKFF[12..8].q;

else if CLKFF_SELH then

CLKFF[7..0].d = CLKFF[7..0].q; % Write to CLKFF[12..8] %

CLKFF[12..8].d = XD[4..0];

else

CLKFF[12..0].d = CLKFF[12..0].q; % Do nothing %

end if;

%*************************************************************************%

% UNFREEZE Flip Flop is cleared asynchronously when the UNFREEZE signal %

% makes a low to high transition. It is set once shifting has been enabled%

% The CHANDRA ignores the UNFREEZE signal if the 601 PCLK clocks are not %

% frozen. %

%*************************************************************************%UN-

FREEZEFF.prn = !SNC_SHIFT_ENFF.q & /RESET;

UNFREEZEFF.clrn = VCC;

UNFREEZEFF.ena = !SHIFT_ENFF.q ;

UNFREEZEFF.d = !(CLKFF[0].q # CLKFF[1].q);

UNFREEZEFF.clk = UNFREEZE ;

EPLD

64 MPRH01TSU-02

%*************************************************************************%

% This signal is the UNFREEZE Flip Flop synchronized to the ISA clock. %

%*************************************************************************%

SNC_UNFREEZE.prn = /RESET;

SNC_UNFREEZE.clrn = VCC;

SNC_UNFREEZE.d = UNFREEZEFF.q;

SNC_UNFREEZE.clk = ISA_CLK;

%****************************************************************************%

% This signal is the UNFREEZE Flip Flop double synchronized to the ISA clock.%

%****************************************************************************%

DOUBLE_SNC.prn = /RESET;

DOUBLE_SNC.clrn = VCC;

DOUBLE_SNC.d = SNC_UNFREEZE.q;

DOUBLE_SNC.clk = ISA_CLK;

%*************************************************************************%

% FREEZE Flip Flop is cleared asynchronously when the UNFREEZE signal %

% makes a high to low transition. It is set once shifting has been enabled%

% The CHANDRA ignores the UNFREEZE signal if the 601 PCLK clocks are %

% already frozen. %

%*************************************************************************%

FREEZEFF.prn = !SNC_SHIFT_ENFF.q & /RESET;

FREEZEFF.clrn = VCC;

FREEZEFF.ena = !SHIFT_ENFF.q ;

FREEZEFF.d = CLKFF[0].q & CLKFF[1].q;

FREEZEFF.clk = !UNFREEZE ;

%*************************************************************************%

% This signal is the FREEZE Flip Flop synchronized to the ISA clock. %

%*************************************************************************%

SNC_FREEZE.prn = /RESET;

SNC_FREEZE.clrn = VCC;

SNC_FREEZE.d = FREEZEFF.q;

SNC_FREEZE.clk = ISA_CLK;

%****************************************************************************%

% This signal is the FREEZE Flip Flop double synchronized to the ISA clock.%

%****************************************************************************%

DOUBLE_FRZ.prn = /RESET;

DOUBLE_FRZ.clrn = VCC;

DOUBLE_FRZ.d = SNC_FREEZE.q;

DOUBLE_FRZ.clk = ISA_CLK;

SHIFT_ENFF.s = CLKFF_SELH; % Start shifting upon write to 862 %

SHIFT_ENFF.r = GND;

SHIFT_ENFF.prn = DOUBLE_SNC.q & DOUBLE_FRZ;

SHIFT_ENFF.clrn = !GEN_STOP_BITFF.q & /RESET; %Clr when it reaches 15 & rst%

SHIFT_ENFF.clk = /XIOW;SNC_SHIFT_ENFF.d = SHIFT_ENFF.q;

% One clock after SHIFT_ENFF%

SNC_SHIFT_ENFF.ena = /RESET;

SNC_SHIFT_ENFF.clrn = /RESET;

SNC_SHIFT_ENFF.clk = ISA_CLK;

CNTR[].clk = ISA_CLK;

CNTR[].clrn = /RESET; % Counter resets to zero %

EPLD

MPRH01TSU-02

If SNC_SHIFT_ENFF.q Then % Count while SNC_SHIFT_ENFF is 1 %

CNTR[].d = CNTR[].q + 1;

Else

CNTR[].d = CNTR[].q;

End If;

GEN_START_BIT = !CNTR[3].q & !CNTR[2].q & !CNTR[1].q & CNTR[0].q; % 1 %

STOP_SHIFT = CNTR[3].q & CNTR[2].q & CNTR[1].q & !CNTR[0].q; % 14 %

GEN_STOP_BITFF.d = STOP_SHIFT; %Generate Stop Bit when counter is 15 %

GEN_STOP_BITFF.prn = VCC;

GEN_STOP_BITFF.clrn = /RESET;

GEN_STOP_BITFF.clk = ISA_CLK;

START_SHIFTFF.s = GEN_START_BIT;

START_SHIFTFF.r = STOP_SHIFT;

START_SHIFTFF.clrn = /RESET;

START_SHIFTFF.clk = ISA_CLK;

%*************************************************************************%

% FRZ_DATA_OUT is a 1 when the counter = 0. It is also a 1 whenever %

% START_SHIFTFF is 1 and CLKFF[0] is a 1 and then when the counter is %

% Fifteen to leave it in the high state. %

%*************************************************************************%

FRZ_DATA_OUT = !CNTR[3].q & !CNTR[2].q & !CNTR[1].q & !CNTR[0].q

# GEN_STOP_BITFF.q

# START_SHIFTFF.q & !CLKFF[0].q;

%*************************************************************************%

% Read Storage Light Status Register I/O address: 0808 %

% (MSB) Bits 7–1 Reserved %

% (LSB) Bit 0 Hard Disk Active Light (W/R) %

% %

% Read Power Control Register 1 I/O address: 082A %

% (MSB) Bits 7–1 Reserved %

% (LSB) Bit 0 83C750 D0 (W/R) %

% %

% Read Power Control Register 2 I/O address: 082B %

% (MSB) Bit 7 CPU1 ROM Completed (Reset by /RESET, R/W) %

% Bit 6 Reserved %

% Bit 5 Reserved %

% Bit 4 Reserved %

% Bit 3 IRQ12 Mask (Reset by /RESET, W/R) %

% Bits 2–1 Reserved %

% (LSB) Bit 0 83C750 Status (R/O) %

% %

%*************************************************************************%

XD_TRI_OE = ((LIGHT_STRB

# PWR_REG1_STRB # PWR_REG2_STRB

# CLKFF_STRB) & !/XIOR);

XD[0] = TRI (D[0], XD_TRI_OE);

D[0] = HDD_LEDFF & LIGHT_STRB

# RWD0 & PWR_REG1_STRB

# PROC_RDY & /CMD_STATE & PWR_REG2_STRB

# CLKFF[0].q & CLKFF_SELL

# CLKFF[8].q & CLKFF_SELH;

EPLD

66 MPRH01TSU-02

XD[1] = TRI (D[1], XD_TRI_OE);

D[1] = CLKFF[1].q & CLKFF_SELL

# CLKFF[9].q & CLKFF_SELH;

XD[2] = TRI (D[2], XD_TRI_OE);

D[2] = CLKFF[2].q & CLKFF_SELL

# CLKFF[10].q & CLKFF_SELH;

XD[3] = TRI (D[3], XD_TRI_OE);

D[3] = PWR_REG2[1].q & PWR_REG2_STRB

# CLKFF[3].q & CLKFF_SELL

# CLKFF[11].q & CLKFF_SELH;

XD[4] = TRI (D[4], XD_TRI_OE);

D[4] = CLKFF[4].q & CLKFF_SELL

# CLKFF[12].q & CLKFF_SELH;

XD[5] = TRI (D[5], XD_TRI_OE);

D[5] = CLKFF[5].q & CLKFF_SELL;

XD[6] = TRI (D[6], XD_TRI_OE);

D[6] = CLKFF[6].q & CLKFF_SELL;

XD[7] = TRI (D[7], XD_TRI_OE);

D[7] = PWR_REG2[2].q & PWR_REG2_STRB

# CLKFF[7].q & CLKFF_SELL;

END;

Memory

MPRH01TSU-02

Section 6

Memory Systems

The reference design contains four distinct memory systems: system memory (DRAM), L2

cache memory (SRAM and tagRAM), ROM for boot and POST code, and NVRAM.

6.1 DRAM

The reference design has slots for up to 128M of system memory (DRAM), arranged as

four industry standard 72-pin SIMMs (see Table 17). When using more than one pair of

32MB SIMMs however, it is necessary to insert a buffer on the WE[1:0] and MA[11:0] lines

between the SIMMs and the 664, in order to drive the increased capacitive load presented

by the 32MB SIMMs. The reference design does not buffer these signals, and does not pro-

vide circuit board patterns for such buffers.

S70ns

S4 data bytes plus 1 parity bit per byte, 72 pin SIMM

Spresence detect bits.

Table 17. Supported DRAM Modules

Size Organization IBM Part Number DRAM Data Sheet

4MB 1M x 36b IBM11E1360BA MMDS14DSU–00

8MB 2M x 36b IBM11E2360BA MMDS22DSU–00

16MB 4M x 36b IBM11E4360B MMDS26DSU–00

32MB 8M x 36b IBM11E8360B MMDS27DSU–00

6.1.1 Refresh

The memory controller in the 660 bridge provides a flexible refresh capability for the refer-

ence design.

The ISA bus bridge provides the ISA_REFRESH# signal to refresh ISA bus memory. Refer

to the SIO data book for more information.

6.1.2 DRAM Presence Detection

The reference design includes a method for software to detect and identify installed DRAM

modules using the presence detect bits, PD[15:0]. See section 4.6.7.

Memory

68 MPRH01TSU-02

Figure 6. DRAM Bank Organization

CAS0

CAS1

CAS2

CAS3

CASP

MCE0#

MCE1#

MCE2#

MCE3#

MCE5#

MCE6#

MCE7#

PD1

PD2

PD3

PD4

MRE0#

MRE1#

MRE2#

MRE3#

MWE0#

MWE1#

RAS0

RAS1

RAS2

RAS3

GND

CAS0

CAS1

CAS2

CAS3

CASP

PD1

PD2

PD3

PD4

RAS0

RAS1

RAS2

RAS3

MCE4#

CAS0

CAS1

CAS2

CAS3

CASP

PD1

PD2

PD3

PD4

RAS0

RAS1

RAS2

RAS3

GND

CAS0

CAS1

CAS2

CAS3

CASP

PD1

PD2

PD3

PD4

RAS0

RAS1

RAS2

RAS3

MPD8

MPD7

MPD6

MPD9

MPD10

MPD11

MPD12

MPD13

MPD14

MPD15

MPD5

MPD4

MPD3

MPD2

MPD1

MPD0

D[0:31]

D[32:64]Data & Par Data & Par

Data & Par Data & Par

Presence

Detect Bits

SIMM 1

SIMM 2

SIMM 3

SIMM 4

Bank 0 Bank 1

MemoryMemory

6.1.3 Organization

The 4-byte DRAM modules (SIMMs) are arranged in pairs to form 8-byte memory banks,

as shown in Figure 6. Each socket supports a 32-bit (non-parity) or a 36-bit (4 data bytes

plus 4 parity bits) DRAM SIMM. Bank 0 is composed of SIMM 1 and SIMM 2. Bank 1 is com-

posed of SIMM 3 and SIMM 4. The 2 SIMMs in each bank must be the same size.

Combining the internal organization of the SIMMs (found in the respective data sheets) with

the bank organization of Figure 6 shows that each parity bit is accessed with the associated

data byte. The 660 bridge uses this standard organization for either parity or ECC mode

operation.

Memory

MPRH01TSU-02

6.2 L2 Cache

The reference design supplies an L2 cache controller, located inside the 660 Bridge chip-

set. The motherboard provides a socket for an SRAM module, and the L2 tag RAM (two

16K x 15 synchronous devices) is supplied installed on the board. The L2 is a unified, write-

thru, direct-mapped, look-aside level 2 cache that caches the low 1G of CPU memory

space.

The reference design is initially configured to use a 512K synchronous SRAM module, but

can be configured to use 256K, 512K, or 1M module populated with either synchronous or

asynchronous SRAM.

The L2 supplies data to the CPU bus on write hits and snarfs the data (updates the SRAM

data while the memory controller is accessing DRAM memory) on read/write misses. It

snoops PCI to memory transactions. Typical synchronous SRAM read performance with

9ns SRAM is 3-1-1-1, followed by -2-1-1-1 on pipelined reads. Typical asynchronous

SRAM read performance with 15ns SRAM is 3-2-2-2, followed by -3-2-2-2 on pipelined

reads. For more information on the operation and capabilities of the L2, see the 660 Bridge

User’s Manual.

6.2.1 SRAM

As initially configured (Figure 8), the reference design features a 512K synchronous SRAM

SIMM. A synchronous 256K SRAM module is shown in Figure 7. A synchronous 1M SRAM

module is shown in Figure 9.

It is also possible to use asynchronous SRAM modules with the reference design.

Figure 10 shows a 256K asynchronous SRAM module. Figure 11 shows a 512K asynchro-

nous SRAM module. Figure 12 shows a 1M asynchronous SRAM module.

Figure 7. Synchronous SRAM, 256K L2

CPU_ADDR[14:28]

CPU_DATA[0:63]

CPU_DPAR[0:7]

Data

Address

32k x 18

SRAM

Data

Memory

70 MPRH01TSU-02

Figure 8. Synchronous SRAM, 512K L2

CPU_DATA[0:63]

CPU_DPAR[0:7]

Data

Address

SRAM

Data

64k x 18

CPU_ADDR[13:28]

Figure 9. Synchronous SRAM, 1M L2

CPU_DATA[0:63]

CPU_DPAR[0:7]

Data

Address

SRAM

Data

CPU_ADDR[13:28]

Data

Address

SRAM

Data

64k x 18 64k x 18

CPU_ADDR[12]

Memory

MPRH01TSU-02

Figure 10. Asynchronous SRAM, 256K L2

CPU_ADDR[14:28]

CPU_DATA[0:63]

CPU_DPAR[0:7]

Data

Address

SRAM

Data

32k x 9

Figure 11. Asynchronous SRAM, 512K L2

CPU_DATA[0:63]

CPU_DPAR[0:7]

Data

Address

SRAM

Data

CPU_ADDR[13:28]

64k x 18

Memory

72 MPRH01TSU-02

Figure 12. Asynchronous SRAM, 1M L2

CPU_DATA[0:63]

CPU_DPAR[0:7]

Data

Address

SRAM

Data

CPU_ADDR[12:28]

128k x 9

6.2.2 TagRAM

The tagRAM, a pair of IDT71216S10 devices, is installed on the reference board. The ta-

gRAM configuration for a 512K L2 (initially supplied on the reference design) is shown in

Figure 13. The tagRAM configuration for a 1M L2 is shown in Figure 14.

Figure 13. Synchronous TagRAM, 512K L2

Data

Address

TAG_VALID Valid Match TAG_MATCH

16k x 15

TagRAM

CPU_ADDR[13:26]

CPU_ADDR[2:12]

VDD

Figure 14. Synchronous TagRAM, 1M L2

Data

Address

TAG_VALID Valid

Match TAG_MATCH

16k x 15

TagRAM

CPU_ADDR[13:26]

CPU_ADDR[12]

CPU_ADDR[2:11]

Match

VDD

Memory

MPRH01TSU-02

6.2.3 L2 Cache Configuration

To implement the desired L2 configuration on the reference design, refer to Table 18.

Table 18. L2 Configuration Implementation

Configuration Component Values

Cache Size SRAM Type

256K 512K 1M Burst Asynch

R 463 0 W0 Wno-pop

R 465 0 Wno-pop no-pop

R 466 no-pop 10k 10k

R 467 no-pop 0 W0 W

R 475 10k no-pop no-pop

R 477 no-pop no-pop 10k

R 478 no-pop no-pop 0 W

R 479 1k 1k no-pop

U 37 populate populate populate

U 38 nopop nopop populate

R 168 0 Wno-pop

R 169 no-pop 0 W

R 170 no-pop 0 W

R 171 0 Wno-pop

R 172 0 Wno-pop

R 474 no-pop 0 W

R 476 no-pop 0 W

Memory

74 MPRH01TSU-02

6.3 ROM

The reference design uses an AMD AM29F040-120 Flasht ROM to contain the POST and

boot code. It is recommended that Vital Product Data (VPD) such as the motherboard

speed and native I/O complement be programmed into in this device. It is possible to pro-

gram the Flash before or during the manufacturing process.

6.4 CPU to ROM Transfers