MS_37269B_Litton_L 304H_Functional_Description_Jul74 MS 37269B Litton L 304H Functional Description Jul74

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MS 37269B

FUNCTIONAL DESCRIPTION OF THE
LITTON L-304H
MICROELECTRONIC COMPUTER

July 1974

THIS DOCUMENT HAS BEEN APPROVED FOR PUBLIC DISSEMINATION.

Prepared by:
Data Systems Division
Litton Systems, Inc.
8000 Woodley Avenue
Van Nuys, California 91409

TABLE OF CONTENTS

Section

INTRODUCTION
L-304H Offers High-Speed Processing for Tactical Applications
System Organization of the L-304H Computer
MULTIPROGRAMMING CAPABILITY
Priority Demand Operation Enhanced by Multiprogramming
Response to Priority Interrupts
Program Level Change Shown as a Function of Interrupt
Program Levels Linked by Instructions
Protection Provided Against Power Loss
Multiprogramming Capability Enhanced by Four Real-Time
Clocks
Multiprogram Capability Facilitates Program Load
Protection Provided Against Interprogram Interference
EXTENDED MEMORY ADDRESSING
Extended Memory Addressing Option Provides Powerful Tool
in MultiprogramAddressing
Memory Parity Generation and Check Provided
REGISTER ORGANIZATION
General Purpose Process Registers Provide Multipurpose Use
Status Register
Preassigned Locations in Base Memory
INSTRUCTION REPERTOIRE
Instruction Repertoire Tailored to Tactical Real-Time
Applications
Flexibility of Data Word Formats
Instruction Word Format
Addressing Modes Enhance Programming
Instruction Options Provided by Multimode Addressing
Litton Computer Characterized by Powerful Instruction Repertoire
Special Instructions Facilitate Programming
Program Sequencing
Memory Control of the Instruction's Address Field
Series of Operations Implemented via Each Instruction Execution
Factors Affecting Instruction Execution Time

iii

2
2

3
8
8
9
11
12
12

12
13
13
14
14
14
16
16
17
17
20
20
21
22
24
24
25
44
46
47
48
49

TABLE OF CONTENTS (Continued)

Page

Section
6

8
9

INPUTiOUTPUT SYSTEM

Modular Features of Input/Output Unit
IOU Addresses Up to 56 Peripheral Devices
Input/Output Multiplexing Occurs on a Priority Basis
Seven Modes of Automatic Input/Output Operations Provided
IOU System Provides Both a Burst and Block Mode of Data
Transfer
Real Time System Programs Called by I/O Interrupt Have
Programmable Priority
Program Loading Provided by Hardware Bootstrap Control
The IOU System is Power Fail Safe
SPECIAL PROCESSING UNITS
Pr.ogram Skip Capability Provided for all SPUs
Extended Performance Arithmetic Option

L-304H SOFTWARE
SYSTEM PACKAGING, POWER, AND CONTROLS

70
78

53
53
56
58
59
61
61
62
63
64

LIST OF ILLUSTRATIONS

Figure

Page

1-1

Comparison of Sample System Configurations

2-1
3-1

Program Level Change
PCA Byte Format
Base Memory Map
Process Register Pair
Operand Selected from Memory Output when W = 1
Operand Selected from Memory Output when W = 0
Full Word Format
Instruction Word Format
Queue Table Instruction
Move and Insert
Move and Zero
Instruction Access Process
Page Control and Address
Instruction Execution Sequence
OFR Instruction Word
ITR Instruction Word

4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
6-1
6-2
6-3
6-4
6-5
6-6

DEC Instruction Word
I/O Key Word
I/O Termination Word
Character Positions, Least Significant First

6-7
7-1
8-1
8-2
8-3
8-4
9-1
9-2
9-3

Character Positions, Most Signficant First
SPU Interconnection Diagram
L-304 OS Resident Supervisor
L-304 Operating System
Resident Supervisor Structure
L-304 OS Support Programs
L-304H Processor Packaging
L-304H Memory Packaging
L-304H System Control Panel

7
11
15
19
21
21
22
22
23
-44
45
45
47
48
49

53
54
54
55
56
57
57
.62
71
72
73
74
81
81
82

LIST OF TABLES

Page

Table
i-I
II-I
111-1
V-I
V-2
V-3
V-4
V-5
V-6
V-7
V-8
V-9
VI-l
VII-1

Key Features of the L-304H Computer (2 Sheets)
Program Level Condition Due to Program Activity Register
Interpretation of Access Control Bits
Data Operand and Transfer Instruction Address
Class: Arithmetic Instructions (2 Sheets)
Class: Data Manipulation Instructions (3 Sheets)
Class: Data Handling Instructions (3 Sheets)
Class: Jump Instructions (3 Sheets)
Class: Transfer Instructions (2 Sheets)
Class: Input/Output Instructions
Class: Mis<;ellaneous Instructions
Add Instruction Times in Microseconds
Data Rates for 1/0 Operations

8
15
28
29
31
34
37
40
42
43
51
59

Summary of Instructions for Extended Performance
Arithmetic Option

Litton L-304H Computer System

SECTION 1 INTRODUCTION

L-304H OFFERS HIGH-SPEED PROCESSING FOR TACTICAL APPLICATIONS

The Litton L-304H Computer provides significantly_ il1cre~sed s~ed and perfQrmance capabiJities over previous L-304 models.

~_ _ _ _ __

determine the source of the interrupt and whether
its _. priority is hjgher or lower __ thaJl the program
curren-tly under execution. This function is performed concurrently and without interference to
the currently executing program. Sixty-four levels
of priority are provided, with complete control afforded the programmer for masking and enabling
each of the interrupts independently.

The L-304H is a successor to the basic Litton
L-304 series of computers that have found widespread application among all branches of the military for a variety of real-time data processing
applications.
The L-304H retains the general
characteristics of this basic computer family while
offering a performance improvement of approximately four times that of the currently deployed
L-304F.

Hardware implementation of the. multiprogramming function is also provided to minimize the
time required for data exchanging in the multiprogramming environment. Since the functions
performed in program exchanging are repetitive,
hardware implementation of this feature is quite
straightforward. As with the handling of interrupts, full software override control is provided
to the program.

The computer architecture of the L-304 computer
systems is specifically designed for real-time application as evidenced by the inclusion of features
such as a hardware interrupt handler, hardware
multiprogramming control, special instructions, a
hardware real-time clock, and provisions for special processing units (SPUs). These and additional
features of the L-304H are described in more detail in Table I-I.

In design of the L-304 computer family, special
instructions were included for real-time processing.
As an example, the Gated Compare instruction
provides the ability to determine whether a quantity is within or without specified limits. Such a
function, of course, is particularly useful in the
correlation of incoming sensor data with an existing data file. Hardware mechanization of real-time
clocks provides the programmer with the capability
to set timing intervals for four different real-time
clocks, each with resolution of one millisecond.

Experience with real-time systems throughout the
industry has shown that attempts to handle a
large number of interrupts on a real-time basis
with an executive-type software interrupt handler
results in large overhead which decreases the efficiency of the machine directly proportional to
the number of interrupts that must be serviced.
Separate hardware is provided in the L-304H to

The L-304H is fully I/O compatible and upward

software compatible with the L-304F. This feature was provided by having the instruction set of
the L-304H contain, as a subset, the entire repertoire of the L-304F. Since software compatibility
has been maintained with previous versions of the
computer, fully developed support. software is
available. Enhancements to the already powerful
L-304 repertoire are provided by new instructions
and optional macro capability. The new instruc-

tions provide double precision (32-bit) arithmetic;
direct "flag" testing of a single bit in memory; and
enqueue, dequeue instructions for file control.
i Special processing units will "custom" functions as
required by particular applications.
Implementation of the computer utilizes MSI
Schottky circuitry which increases the packaging
density and permits an increase in the CPU clock
rate.

SYSTEM ORGANIZATION OF THE L-304H COMPUTER

The' L-304H computer system achieves maximum
flexibility and growth potential in storage, computation, and input/output capability by use of modular design techniques.
The modular design of the L-304H computer permits a variety of system configurations, ranging·
from those with limited processing, memory, and
I/O requirements to systems requiring multiple
processors, independent input/output operations,
and masses of random access storage. This growth
is achieved by adding central processing units,
memory units, independent input/output units,
and special processing units (SPUs) without changing the basic system implementation.

Figure 1-1, A.) The other port is available for
I/O direct memory access.
If additional processing capability is required, a
second L-304H processing unit (CPU, IOU, SPU)
may be added. (See Figure 1-1, B.)

The L-304H memories are designed with two or
four ports; i.e., they contain data lines, control
lines, and priority iogic which will permit either
two or four processors (or processor-like devices)
tu access the memories independently.

Maximum memory expansion is achieved with the
use of word addressable mass memories and an
optional extended memory card. (See Figure
1-1, C.) While the memory bus capacity limits
the number of memory units to eight, the numbyr
of words directly addressable by L-304H instructions with an expanded EMA is two million. Therefore, mass core memory units each containing
131 K words or more may be used. The asynchro'nous timing relationship between the CPU and the
memories permits the access time of the mass memory .to be considerably slower from that of the
main memory (without creating synchronization
problems).

A basic processing system requires the use of a
.single memory port with the IOUs and SPUs cycle
stealing on a common bus with the CPU. (See

An optional input/output processor (lOP) requiring an independent bus memory would use the
four port memory(s), as shown in Figure 1-1, D.

3/4

Table I-I. Key Features of the

L~304H

Computer (Sheet I of 2)
Features

Category

Computer Type

General-purpose; modular, with single or multiple central processing
units.

Logic

Synchronous; silicon integrated circuits, TTL SSI, TTL MSI, and
Schottky SSI, MSI.

Arithmetic Mode

Parallel; binary; fixed point.

Floating Point Option

Five basic instructions: Compare, Add, Subtract, Multiply, Divide.
32-bit format: sign bit 8-bit exponent, 23-bit function.

Word Length

Memory word - 32 bits plus 4 parity bits; (parity optional) instruction word - 32 bits; data word - 32 bits, 16 bits, 8 bits, 1 bit.

Core Memory

16,384-word assemblies, modular expansion to two million words;
overlapping memory cycles; one to four independent access ports;
changeable bank address; memory protect by 2048-word block
(optional); 450 nanosecond access; less ~han 750 nanoseconds full
cycle; wide temperature cores; power transient protection.

Instructions

89 Basic Instructions: 18 Arithmetic, 36 Data Manipulation and
Handling, 26 Jump and Transfer, 4 Input/Output and 5 Miscellaneous.
39 Macro Instructions may be specified.

Addressing

Single and double word addresses; modifiable; full randon addressing
capability up to two million words; memory bus limited by line drive
capability to maximum of 8 memory banks.

Addressing Range

Without EMA Options:
With Standard EMA Option:
With Expanded EMA Option:

Address Modification·

Eight modes: literal, direct, indirect, relative, with selectable indexing;
plus register-to-register mode.

Arithmetic

Eight accumulators for each level; eight index registers for each level, .
overlapped with accumulators; fixed-point binary arithmetic; numbers are signed integers, negative numbers are two's complement.

32,768 words
131,072 words
2,097,152 words

Table I-I. Key Features of the L-304H Computer (Sheet 2 of 2)

r----------------------.---------------------------------______________________
Category

Feature

Programming

Sixty-four independent program levels with externally and internally
activated priority-level switching and software override capability;
dynamic priority hierarchy; eight process registers for each level to be
used as accumulators, index registers, mask registers; 16 memory page
control and address registers for each program level (optional); program
activity register containing one status and one enable bit for each program level; multilevel priority interrupts; dynamic program relocatability
using page/base address registers; special memory test instructions; macro
instruction capability.

Data Handling

Logical operations; field, insert, shift, and comparison
instruction.

Input/Output

Single word transfers; block transfers by bytes or words (asynchronous, independent of program execution); burst block transfers
(synchronous with device); interleaved transfers from several devices;
simultaneous I/O and instruction execution, independent I/O c-ontroller; seaparate normal and error termination for each device; alarm
clock mode (for real-time clock); bootstrap program load.

Maintenance

Central system self-test using hang-up detectors for memory, central
processing unit, I/O, real-time clock; automatic detection to gross
function or module; modular construction; vast compatibility.
Optional self-test logic.

Growth Capability

Special processing units (SPUs) implement classes of individual instructions using any operation code not required for the basic L-304H instruction set (macro). Specialized design for macro instructions allows greater
throughput. Six SPUs and one IOU may be associated with each CPU on
each Direct Memory Access channel.

EMA

Extended memory address up to 131 K words
Memory Protection
Parity generation and error detection for both the CPU memory and
IOU memory interfaces.

(Standard Option)

•••

• L304H CENTRAL PROCESSING UNIT
• UP TO 131,072 WORDS OF MEMORY
• INPUT/OUTPUT UNIT
.SPECIAL PROCESSING UNIT

16 K

B
.DUAL L304H CENTRAL PROCESSING
UNITS
.UP TO 131,072 WORDS OF MEMORY
.INPUT/OUTPUT UNITS
• SPECIAL PROCESSING UNITS

16 K

131K

C
.DUAL L304H CENTRAL PROCESSING
UNITS
.MIX OF 16K AND 131K WORD MEMORIES
• INPUT/OUTPUT UNITS
• SPECIAL PROCESSING UNITS

16K

_ 16K

• DUAL L304H CENTRAL PROCESSING
UNITS
.UP TO 131,072 WORDS OF MEMORY
.1 NPUT/OUTPUT PROCESSORS
• SPECIAL PROCESSING UNITS

Figure 1-1. Comparison of Sample System Configurations

16K

SECTION 2. MULTIPROGRAMMING CAPABILITY

PRIORITY DEMAND OPERATION ENHANCED BY MULTIPROGRAMMING _ _ _ _ _ _ __

Featuring a multiprogramming capability that
enables it to execute 64 different programs on a
priority demand basis, the computer is uniquely
tailored to tactical command and control
applications.

program activity register (PAR). The most significant (highest numbered) one bit of the program
status register which has a corresponding one bit in

One of the most important and unique features of
the computer is a hardware implemented system
for control of program switching in a multiprogramming environment. Its function and its tactical
data system advantages have been proven in operational systems.

Table II-I. Program Level Condition Due to
Program Activity Register
Situation

The computer's built-in multiprogramming feature
allows the processor to execute up to 64 different
programs (00 through 778 in octal representation),
one at a time, on a priority demand basis. Real-time
clocks and interval timers under software control
are also provided to implement time-sliced multiprogramming if required. The principal feature of
the design is that the control for switching from
one program to another is built into the hardware
wi th a software override provision.
Each of up to 64 programs is assigned a program
level number that corresponds to a bit position
within a 64-bit program status register. Bits are set
or reset in this register by program or by the I/O
unit (Table 11-1). A second 64-bit register (the,
program enable register) provides logical masking on the program status register. Bits in this
register are set or reset by programmed instructions.
Together, these two 64-bit registers are called the

PE Bit

Inactive

Program level is disabled
and idle

Waiting,

Program is enabled and is
waiting for a response
from an external equipment
or another program level

Stimulated

Equipment responded or
program was stimulated
but the program has not
been enabled

Suspended

Program suspended because
program of higher priority
is currently being executed
or program level change
lock has been set

Operating

Program level is operating

PS: Program Status Bit
PE: Program Enable Bit

Description

PS Bit

3307-6

tern ally forced interrupt levels and may be entered
directly via a hard-wired interrupt signal from an
external device. The utilization of these levels for
forced interrupts does not preclude their use
within the normal priority auction configuration.

the program enable register determines the currently active program, as shown in Table II-I. The
PAR is held in eight half-word locations in the
base memory bank, and is accessible by any program. (The base memory bank contains the PAR
along with dedicated addresses for inactive process
registers and I/O control words.)

Program level 74 is entered automatically for a detected memory access violation, a memory parity
error, a memory timeout, a program timeout, a
device timeout, or an illegal operation code. Status
bits are set preserving the source of the error such
that the program can sample status and determine
both the cause of the problem and the necessary
corrective action. Information available to the program includes the error type, the device address,
and the memory bank address.

A six-bit number that represents the active program level is logically generated and held in a register called the active program level register. The
contents of this register are available to programs by execution of the Load Register Special
instruction.
Nine program levels are used for special program
functions. These are program levels 70-77 and 00.
Program level 77 is reserved for power shutdown.
When this condition is detected, program level 77
is automatically entered. Approximately 100 microseconds remain for program clean-up before
power is lost.

Program level 74 can also be entered directly via a
hard-wired interrupt signal from an external device._
This permits level 74 to be used as either an additional externally forced interrupt level or as an
error level entered either by an internally or externally detected error.

Program level 76 is reserved for start-up of the
computer when power- is applied. Under this condition, computer control causes the CPU to enter
and execute program level 76 if the system is in the
automatic mode.

Program level 75 is used for a program trace
routine when under control of the programmers'
console.
I

Program level 00 is used for initial program execution following bootstrap program load by the IOU.

Program levels 70-73 have been designated as exRESPONSE TO PRIORITY INTERRUPTS

the computer enables many external interrupts
to be quickly serviced. This means that external
device interrupts occur for data transfer completion and for interrupts initialed by the device itself. These operations typically require a minimum
of program time. The program processing of I/O
interrupts is executed on a variable priority basis.

The computer will respond rapidly to program interrupts in full accord with a preset ranking of program priorities.
The computer has a number of design features that
facilitate the capability to respond to program
interrupts on a" priority basis without the use of
complex executive decision operations. Sixty-four
program interrupt levels are available, each having its own process registers and page control and address (PCA) registers. This enables 64 independent
programs to be simultaneously available for computer operation. Each level has an assigned priority
but only operates if that level is the highest priority demanding activation.

Low-priority function~ are interrupted in favor of
higher-priority functions. After completion of the
higher-priority function, the computer returns to
the interrupted lower-priority function without
delay and without program duplications. The
computer provides the additional feature of a programmable priority level lock-out. This feature
guarantees, if so desired, the execution of a sequence of instructions of a low-priority function
without being interrupted by a higher-priority
function. Normally, the lock-out is set only for

An interrupt level can be stimulated either by
instruction, by interrupts from the I/O, or by an
internally generated alarm. The I/O capability of
9

the sequence of a few instructions. During lockout, all external interrupts are accepted but not
executed. Low-priority functions will inv~rl~hly
receive quick attention -since the computer's capability to process data exceeds the requirements of
typical workloads by a comfortable margin.
Control over the programs which are operating or
suspended is maintained in the status and enable
registers. - The status register contains 64 bits,
where each position represents a program level.
The enable register acts as a mask. It is also
64 bits in length and can be used to inhibit a program from operating. Thus, the program operating at any given time is the highest priority program having a coincident one bit in both the status
and enable registers unless a program level lock is
set. When a program is operating, the set of process registers accessed - is that set which corresponds to the operating program level
Each time that the contents of the status or
enable register are accessed during the execution
-ot--specific in-structions, the- logic of the computer
will test the program priority levels to determine
_, whether or not a change of level is to occur. If a,
switch in programs is required, the hardware will
preserve the state of the interrupted program and
initiate the new program.
Completion of an I/O transfer, as well as device
initiated action, may also cause an interruption of
a current program. Under these circumstances, the
termination word associated with each I/O channel
will be accessed, the specified program level will
set the corresponding bit in the status register, and
a one will be placed in the proper position to indicate the reason for termination of the I/O transfer.
The computer logic determines whether or not an
interruption is to take place. If an interrupt is to
occur, the procedure followed is the same as that
described.

In multiprocessor configurations, the capability
of interprocessor interrupts exists. If, during the
execution of specific instructions~ one processor
accesses the base memory of another processor,
the latter is forced into a program level change normally to the level enabled by the calling processor. This interrupt is automatically initiated by
the calling processor but may be locked out by the
called processor.
Externally forced interrupt levels (70-73 and 74)
are entered directly upon receipt of a hard-wired
interrupt signal from an external device. The priority auction (PAR word search) that normally
occurs in response to an external interrupt from
the IOU or an internally generated interrupt is bypassed for the forced level interrupt and the program level, as specified by the received signal, is
entered directly.
Forced interrupts can be inhibited by the program
level lockout. However, an interrupt received during lockout will be saved and will initiate a level
change when the lockout is reset.
A level entered in response to a forced interrupt
can be interrupted by a higher priority interrupt
without the loss of the lower level interrupt.
When several forced interrupts are received together, a priority selection will be made by the
CPU such that the higher priority interrupts are
processed first.
The priority interrupts may be caused by sources
either external or internal to the computer. These
interrupts are:
a.

External interrupts (from each peripheral device via the IOU)
True interrupts (externally initiated)
(2) Normal I/O termination
(3) Error I/O termination
(1)

Internal interrupts

Externally forced interrupt

( 1)
(2)
(3)
(4)
(5)

Interprocessor interrupt

Program termination
Memory access violation
Memory parity error
Power interrupt
Timeouts

PROGRAM LEVEL CHANGE SHOWN AS A FUNCTION OF INTERRUPT _ _ _ _ _ _ _ __

is shown by a one in the enable register, and
(3) the program level change lock is reset. . At the
end of the currently executed instruction, a level
change is initiated. The active general registers are
preserved in the general register area in the base
memory bank. The assigned fixed area is determined by the program level which corresponds to
the bit position in the program activity register as
shown in steps 2 and 3 (Figure 2-1).

The computer's multiprogramming feature enables
the central processing unit to execute 64 different
programs on a priority demand basis.
Program level switching with software control is
built into the hardware. Its functional advantages
in tactical data systems have been proven in operational systems.
The sequence of a program level change is shown
step by step in Figure 2-1. An operating program
level is indicated by the most significant bit pair in
the program activity register which contains a one
in both the status and enable registers.

The new program level to be activated addresses
the base memory bank, as shown in step 4. The set
of general registers is transferred by step 5 into the
active general registers. In addition, the p~ge control and address information is moved by step 6
from the core memory to the active registers.
Both active registers provide for faster access during instruction execution.

Assume that: (1) an interrupt changes the status
bit for a program of higher priority from a zero to
a one, (2) this program level is not masked, which

OPERATING

'ROGRl LEVEL

1NTE10'

~I_~_ _ _ _ _-----JI~r:STUS

PROGRAM
ACTIVITY
REGISTER

ENABLE
BITS

(BASE) MEMORY BANK
GENERAL REGISTERS

ACTIVE
GENERAL
REGISTERS

I...

...

lit.

PAGE CONTROL AND ADDRESS

PROCESS REGISTERS

"- .....

PAGE CONTR AND ADDRESS

......
r

ACTIVE
PAGE
CONTROL
AND ADDRESS

2344B-17A

Figure 2-1. Program Level Change
11

PROGRAM LEVELS LINKED BY INSTRUCTIONS

any program. If so desired, the execution of a sequence of instructions of a low-priority function
can be completed without being interrupted by a
higher priority function. Normally, the lock is set
only for the sequence of a few instructions.

The hardware/software interface provides a six-fold
exit from a program level. Program levels can be
linked by using the "call" instructions.
A program level change is initiated by: (1) external interrupt, (2) input/output termination,
(3) program termination, (4) memory access violation or parity error, (5) functional time-outs, and
(6) power interrupts. A level change occurs nor.,.
mally if· the initiated program level is of higher
priority, the program level has been enabled, and .
the program level change lock has been reset.

Any program is allowed to access the program
activity register, which governs the program level
change. Thus, any program can call any other
program by setting the appropriate bits in the PAR
and terminating itself. Specific instructions are
available for this purpose. If the called program is'
the highest priority, it is called immediately; if not,
it must wait.

The program level lock can be set only by
specific instructions, and can be set (or reset) by

PROTECTION PROVIDED AGAINST POWER LOSS

The on-off sequencer provides for orderly shutdQWll and startup procedures during power transients as well as application or removal of primary
power.

. When a power failure has been detected, the on-off
sequencer notifies the CPU, which,.in turn

When primary power is initially applied or when
power is recovering from a transient, the on-off
sequencer provides a System Reset which initializes the CPU and inhibits memory operation while
the logic voltage is coming up. When the logic voltage reaches its nominal level, the on-off sequencer
removes the System Reset and Memory Inhibit and,
provides a signal to the CPU that:
a.

Sets the location register to 1610

Sets the CPU to the run condition

Completes the instruction being executed

Stores the registers associated with the curren t program level

Initiates a program level change to level 77

Approximately 100 microseconds are then left for
the necessary clean-up or bookkeeping operations
as specified by the programmer. After this 100microsecond period, the Memory Inhibit is activated since voltage tolerances can no longer be
guaran teed.

Sets up a program level change to program
level 76

Once the shutdown sequence has begun, "start-up"
will not be initiated until System Reset has
been activated, regardless of the duration of the
transient.

MULTIPROGRAMMING CAPABILITY ENHANCED BY FOUR REAL-TIME CLOCKS

cessed via an I/O channel which is serviced by the
IOU in the alarm mode. The associated key and
termination words provide the agency for interval
counting and program interrupts after the specified
time has elapsed. These program interrupts can be
selectively disabled and temporarily locked out.

Real-time clocks provide prescribed time-base for
calling programs involved in peripheral service,
system monitors, or fault detection.
The L-304H provides four independent programmable real-time clocks (RTC). Each RTC is ac-

Each RTC has a period of 1 millisecond, and each
channel has a capacity of 4.1 seconds. Each RTC
channel is staggered by 250 microseconds in requesting IOU service.

IOU operation: if one RTC channel has not been
serviced by the time the next clock is due (a period
of 250 microseconds), the IOU timeout bit is
posted in the status register, a System Reset is effected, and the CPU is forced to the error program
level, 74.

In addition, the RTC logic provides. a monitor for

MULTIPROGRAM CAPABILITY FACILITATES PROGRAM LOAD _ _ _ _ _ _ _ _ _ __

program load switch and inhibited during the load
operation, is started by the IOU. The CPU will obtain the program's starting location from the PLR
associated with level 00 where the IOU has stored
it during the bootstrap operation. The CPU will
then automatically enter level 00 and execute the
bootstrap program stored at that level.

Program level 00 is reserved for program loading after the IOU completes load of bootstrap
program.
After the initial bootstrap program has been
loaded by the IOU, the CPU, deactivated by the

PROTECTION PROVIDED AGAINST INTERPROGRAM INTERFERENCE

A technique utilizing memory protection mini-

A violation of the privilege feature will automatically cause a program level interruption to a specific program level. Control can then be returned
to the executive program. The memory protect
code is:

mizes the possibility of interprogram interference.
The multiprogram use of a computer provides
opportunity for interprogram interference by accident or without authorization. To minimize this
possibility, memory-protect capabilities are provided in the L-304H Computer.

00
01

. The memory-protect feature implemented by the
PCA registers controls the memory access for instructions and operands as well as a write protection. The mechanization of the computer provides
the detailed features in hardware with appropriate
software control by program.

10
11

Instruction Fetch, Operand Read and
Write permitted
Only Instruction Fetch and Operand
Read permitted
Only Operand Read permitted
No Access permitted

SECTION 3.

EXTENDED MEMORY ADDRESSING

EXTENDED MEMORY ADDRESSING OPTION PROVIDES
POWERFUL TOOL IN ~ MUL TIPROGRAM ADDRESSING-_ _ _ _ _ _ _ _ _ _ _ __

The EMA option adds memory protection and parity as well as extended addressing for each program
level of the L-304H.

by any program level. Each PCA byte consists of
a 6-bit page field and a 2-bit access control field
(Figure 3-1). Whenever the computer generates a
IS-bit address, the four most significant bits of the
address select one of the 16 PCA bytes from the
scratch pad memory. The page field, whiCh includes the memory bank and page addresses, is appended to the most significant end of the remaining 11 bits, forming the 17-bit word address.
Since the IOU is independent of program levels,
the EMA is not active during IOU memory cycles.

The standard memory addressing capability of the
computer is 32,768 words. The EMA (extended
memory addressing) option expands this capability
to 131,072 words while segmenting all memory
into pages of 2048 words. In addition, each page
is subject to programmable access control.
This extended addressing and access control is provided by a set of 16 8-bit bytes associated with
each of the 64 program levels. These sets, caned
page control and address (PCA) registers, are
stored in reserved locations in the computer base
memory while the associated program level is not
active. PCA registers for the active program level
are held in a fast access "scratch pad" memory
within the CPU. During each program level change,
the required PCA registers are transferred from the
base memory to the scratch pad by the processor
hardware.

At the same time, the access control field is compared with the memory tnode lines and if the pending operation is not allowed, the memory request
is inhibited, the CPU is notified, and a level change
(to error level 74) is initiated. The memory is not
accessed. Table 111-1 shows the interpretation of
the excess control bits.
An expanded EMA option provides the computer
with the addressing capability of 2,097, IS2 words.

There is no program access to the scratch pad, but
all PCA registers in the base memory are accessible
MEMORY PARITY GENERATION AND CHECK PROVIDED _ _ _ _ _ _ _ _ _ _ _ __

Parity on a byte basis is checked or generated for
every memory cycle.

the error program level, 74. If the check fails during a Read-Modify-Write memory cycle, the data,
along with the incorrect parity bit is restored to
the memory before the transfer is initiated.

If faulty parity is detected, the CPU inhibits execu-

tion of the instruction and initiates a transfer to .
14

Table III-I.

Interpretation of Access Control Bits

PAGE
ACCESS
CONTROL BITS

NAME

READ-WRITE
ACCESS

FETCH
INSTRUCTION

READ
OPERAND

WRITE
OPERAND

READ
ACCESS

FETCH
INSTRUCTION

READ
OPERAND

WRITE

READ
DATA
ACCESS

READ
OPERAND

FETCH

WRITE

NO
ACCESS

FETCH

READ

WRITE

ACTION PERMITTED

ACTION INHIBITED

2344B-1

M)B

LSB

ACqESS CONTROL

MEMORY BANK ADDRESS

Figure 3-1. PCA Byte Format

PAGE ADDRESS

SECTION 4. REGISTER ORGANIZATION

GENERAL PURPOSE PROCESS REGISTERS PROVIDE MULTIPURPOSE USE _ _ _ _ _ __

and accumulators eliminates the requirements for a
number of load and store instructions from a program. Often, index quantities are derived from
arithmetic operations. Thus, the result is directly
available as an index in subsequent instructions.

A set of eight process registers is provided for
each of 64 program levels. These registers may be
used as index registers, accumulators, and other
programming functions.
The computer provides a multiprogram capability
that is program-controlled with a priority demand
technique. Each of 64 program levels is assigned
its own set of process registers. These registers are
held in the computer's base memory bank for all
temporarily inactive program levels; and in highspeed, scratch-pad memories for currently active
program levels. Whenever a program level change
occurs, the currently active registers are written,
automatically, back into their reserved and dedicated locations within the base memory bank and
the new set of registers is loaded into the highspeed memories.

The use of the process registers as multiple accumulators provides the opportunity to leave partial
results in the accumulator without having to preserve them in memory. Partial results can be combined with instructions using the special address
feature, which allows register-ta-register operations
without time consuming memory access.
The process registers of any program level rna y be
addressed by any other program by addressing the
base memory bank. The process registers of the
active program may be addressed by the instruction's S field for indexing operations, by the instruction's H field for use as an accumulator, and
by the instruction's operand address. Special addresses (00-07 8 ) are recognized as process register
addresses instead of memory locations.

The high-speed memories are constructed from MSI
random access memory chips. An array of these
elements provides a small memory of 16 half words.
Access to this memory is less than 40 nanoseconds.
Use of the process registers as both index registers
16

STATUS REGISTER

The status register contains information pertaining
to error/fault conditions existing within the system.
The register is organized as two 8-bit bytes, and
may be interrogated by a program via the Load

The format of the two bytes is shown below

MSB

1ST BYTE

LSB

I I I I I ICM I I I
I CrANN,L
I : MBA:
sp

LSB

MSB

2ND BYTE

IT
CM
1M
IE
PE
AE
SP

MBA
Channel

Program Time Out
IOU Time-Out
CPU/Memory Time-Out
IOU/Memory Time-Out
IOU Memory Parity Error
CPU Memory Parity Error
Access Violation
Spare
Current Memory Bank Address
or Error Memory Bank Address
Active IOU Channel or Error
IOU Channel

PREASSIGNED LOCATIONS IN BASE MEMORY _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Program Location Registers. One half-word for
each program level indicating the current entry
point into that program.

Each base memory has several pre-assigned locations used as temporary storage for registers control words, etc., while that program level, channel,
or function is not active.

Program Activity Registers. Four words indicating
the enable and status conditions for each program
level.

Figure 4-1 shows the organization of the locations
in the base memory. Each location is defined as
follows:
General Purpose Process Registers. Eight half
words to be used by each program level for accumulators, index registers, etc.

Page Control and Address Words. Sixteen 8-bit
bytes for each program level controlling the memory access and paging for that level.

I/O Control Words. Eight key and termination
words for each I/O channel. (See section on IOU).
17/18

Note that although locations 01610-01777 are
unassigned, the processor, on automatic startup, is forced to run starting at location 01610.

HALF-WORD
OCTAL LOCATIONS
, PROGRAM LEVEL

RHO

RH1

RH2

RH4

RH3

RH5

RH6

RH7

00000-00007
000 10-00017

GENERAL PURPOSE
PROCESS REGISTERS

•
••

••

•
••

•

76
77

1/0 CHANNEL

RHO

00,01

RH1

RH2

RH3

RH4

TERMINATE

KEY

RH5

KEY

RH7

00770-00777

TERMINATE

01000-10007

RH6

01010-10017

02,03
04,05

1/0 CONTROL
WORDS

06,07

•

••
•

••

•

01360-01367

74,75
76,77

01370-01377

0-3

01400-01407

PROGRAM LEVELS

PLR

01410-01417

4-7
PROGRAM LOCATION
REGISTERS

•••
74-77

PROGRAM ACTIVITY REGISTERS

PLR
PE

••
•
PLR

PLR
PE

PLR

01570-01577

01600-01607

01610-01617

UNASSIGNED

AUTO START./
LOCATION

••
•

01770-01777
~

PROGRAM LEVEL

PAGE CONTROL
AND ADDRESS WORDS

PO P1 P2 P3 .

T T

P13 P14 P15

02010-02017

•
••
02770-02777

03000-03007

UNASSIGNED

_ _ _ _""-i_ _ _ _ _ _ _ _

02000-02007

_ _ _ _L...__ _ _.........I...__ _ ____L_ _ _ _

Figure 4-1. Base Memory Map

__I1

0377:77777

SECTION 5. INSTRUCTION REPERTOIRE

INSTRUCTION REPERTOIRE TAILORED TO TACTICAL REAL-TIME APPLICATIONS - - - - -

The computer instruction repertoire provides a
number of special instructions to specifically reduce the reaction time of tactical command and
control systems.

The Store all Zero instruction is used to clear
memory or register cells.
The Transfer and Jump instructions include a wide
range of control instructions to assist the programmer in organizing and controlling his program
sequence and provide a capability to respond to
external stimuli. General purpose (GP) register
test instructions are used to test and modify registers and provide program looping. Instructions are
provided to test a single bit for its status. A Load
Special Instruction provides internal/external status to the programmer to facilitate fault diagnosis.
The Enque/Deque instruction provides a simplified
method for handling common data files.

The computer has been designed to satisfy the
requirements of tactical real-time· command and
control systems. Toward this end, an instruction
repertoire has been prepared which provides a
numbe~_?f special instructions to decrease reaction
time. The combination of this type of instruction
list and the flexibility of programming offers a
powerful tool for performing real-time missions.
The selection of each instruction was made after
intensive trade-off analysis and discussions which
reflected Litton's extensive experience in tactical
data processing requirements. The instructions
may be grouped in seven classes: arithmetic, data
manipuiation, data handling, jump, transfer, inputi
output, and miscellaneous instructions. The arithmetic instructions encompass a comprehensive
computational capability and include Add, Add
Double Precision, Subtract, Subtract Double Precision, Multiply, and Divide with a number of variations to simplify the programming operation.
The jump group includes compare instructions
which allow algebraic, logical, and gated (within
limits) comparisons.

Input/output instructions initiate and enable communication to be set up with peripheral devices for
automatic independent data transfers. Two instructions allow single transfers between a device
and a GP register.
The L-304H was designed to accommodate the addition of a special processing unit tailored to a
customer's specific application. These SPUs offer
the capability to perform macro instructions and
allow execution of complex algorithms efficiently
under software control. The SPU has direct access
to both the memories and the hardware process
registers. Thirty-nine operation codes have been reserved for the macro operations.

Data manipulation instructions include logical
operations which enable data to be matched and
merged, and act as an adjunct to the data handling
capability. The Move and Insert and the Move and
Zero instructions give an excellent capability to
move groups of bits of arbitrary length about the
process registers. A full complement of shift instructions, including a reflect operation is also
provided.
Four instructions are incorporated
which facilitate set and reset of individual bits
within a data word.

An example of an SPU is the extended perform-

ance arithmetic unit which provides double precision multiply and divide operations and floating
point multiply, divide, add, subtract, and compare
instructions.
A summary of the 128 instructions, by type,
includes:

Arithmetic: 18 fixed point
Data Manipulation:
reset bit

Transfer (Branch): 4 GP register test, 3 control transfer, 4 GP register modify

6 logic, 6 shift, 8 set/
Jump:
match

Data Handling: 7 load (registers), 2 store
(registers), 4 move, 2 exchange, 1 store zero

7 compare, 8 test bit and skip on

Miscellaneous: 5 miscellaneous
Macro:

39 codes available

FLEXIBILITY OF DATA WORD FORMATS

The data word size in the Litton computer is
determined at the programmer's option.

called the W field). This bit will select either the
left-most 16 bits of a selected word if it is zero
(W = 0), or it will select the right-most 16 bits of a
selected word if it is one(W = 1). On word operations, the W bit of the instruction is ignored, and
the address is treated as an even number. Therefore, all word addresses are even numbers.

The programmer may select data words of a single
bit, a "byte" of eight bits, a half-word of 16 bits,
and a full word of 32 bits. The data word size is a
function of the programmer's option on the
instruction to be executed. On arithmetic and
logical instructions, either half-word or word
operations are allowed. Special instructions are
provided for test and modification of single bits
within a half-word. Special byte handling instructions are also provided. Full-word products are
generated on multiply instructions; full-word dividends are used in divide instructions; full-word
register pairs are allowed in shift instructions, and
addition and subtraction can be performed on
full-word operands.

Bytes of eight bits are selected on half-word instructions as either the "upper byte" or "lower
byte" by the instruction's operation code. Single
bit positions of a byte are selected by use of the
instruction word's H field.
Bytes of a variable length and position are selected
and controlled during the move instructions by a
mask contained in the instruction's CA field.
The storage of partial words and full words within'
the process registers and memory is shown in
Figures 5-1 through 5-4.

Memory addresses are considered as half-word
addresses because the instruction's operand address field contains a single bit (in bit position O~

I
31

16 15

Figure 5-1. Process Register Pair

16~ BYTE

I-

......--1

UPPER - - - - 4

BYTE LOWER

Figure 5-2. Operand Selected from Memory Output when W = 1
21

----1-

·1

~ BYTE UPPER.

•

7
..

BYTE LOWER

Figure 5-3. Operand Selected from Memory Output when W =
15

MSH

LSH

Figure 5-4. Full Word Format
A data word may contain a numerical or logical
quantity.
Numerical quantities are treated as
signed integers. Logical quantities include unsigned numbers (e.g., addresses) or collections of
individual bits and fields.

word operand is required.

In numerical words, the most significant bit is
treated as the algebraic sign. If this bit is a zero,
the sign is positive. If this bit is a one, the sign is
negative. The sign bit of a numerical half-word is
automatically sign extended (value repeated) to
the left 16-bit positions when a numerical full-',

Negative numbers are represented in two's complement form. Two's complement representation
has advantages in arithmetic compatibility with unsigned numbers and in elimination: of a negative
zero value.
A 32-bit algebraic operand is provided with two
sign bits (S 1 and S2) which are always equal
(Figure 5-4).

M = 0, Direct Address
M = 1, Direct Address with Indexing
M = 2, Literal
M = 3, Literal with Indexing
M = 4, Indirect
M = 5, Indexed, Indirect
M = 6, Indirect, Indexed
M = 7, Relative with Indexing Option

The Litton computer operates with a 32-bit instruction word containing five fields.
The normal use and definition of each instruction
word field is as follows (Figure 5-5):
a.

F Field - This 7-bit field is the instruction
operation code. The operation code is represented by a 3-digit octal number.

H Field - The H field is a 3-bit binary number that selects one of eight process registers
to be used as the accumulator by the instruction. Process registers are addressed by
H = 0, 1, 2, . . " 7 on all program levels.

These options are described in more detail in
a subsequent discussion of addressing modes.
d.

M Field - The M field is a 3-bit code that
provides up to eight instruction address options as follows:

S Field - The S field is a 3-bit field that
selects one of the eight process registers to be
used as an index register on modes M= 1, 3,
5, 6, and 7. The S field addresses the same
set of process registers as the H field on a
program level. A different set of eight process registers is provided for each of 64 program levels.

CA Field - The operand address field, CA, is
a 16-bit field that may either be an address of
a word in memory or may be a 16-bit operand itself. The CA field is used as an operand
in the literal address modes, M = 2 or 3.
When the CA field is used as an address, it is
considered to consist of three subfields:
D, A, and W. These three subfields provide
memory address extension of up to 18 bits
for addressing 16-bit words or 17 bits for
addressing 32-bit words.

A Sub field - The A subfield is an II-bit
binary address.
The II-bit address will
select one of 2048 32-bit words within a
memory module. The particular memory
module is selected by the three MSBs of the
6-bit page control and address register (described previously).

W Subfield - During an operand fetch, the
I-bit W subfield specifies left or right half of
the 32-bit memory output to be used as a
16-bit operand. If W is a zero, the left half
of the word is used. If W is a one, the right
half is used. The W sub field is ignored during
an instruction fetch.

D Subfield - The D subfield is a 4-bit binary
number that selects one of 16 page control
and address registers. The selected register
contains six bits which are "appended to the
most significant end of the A subfield to
yield .a 17-bit operand address. Although an
overflow out of the D subfield may occur
during indexing, a carry is not allowed to
propagate from the D sub field to the S field.
LEGEND:
F:

OPERATION CODE

ADDRESSING MODE SELECTOR

ACCUMULATOR DESIGNATOR

INDEX DESIGNATOR

CA :

OPERAND ADDRESS FIELD

PAGE CONTROL
AND ADDRESS REG

PAGE DESIGNATOR

WORD ADDRESS DESIGNATOR

HALFWORD ADDRESS DESIGNATOR

MEMORY ADDRESS

.......

10F 8
ACCUMULATORS

~
MEMORY
PROTECTION

1 OF 8
INDEX
REGISTERS
19 18

2524122 21

....~

1 OF 16

16 15

12 11

-""'r-

...

HALF-WORD
SELECTION

CPU
CONTROL
AND TIMING

2344B-16A

Figure 5-5. Instruction Word Format
23

ADDRESSING MODES ENHANCE PROGRAMMING

The availability of eight addressing modes in the
Litton computer provides the programmer with a
powerful tool.

The relative mode provides an addressing capability which allows referencing to the location of
the current instruction. A relocation of a program will not disturb the relationship between the
instruction and the referenced operand. It is
recommended that the operand be located close to
the instruction since an insertion or deletion of
instructions in a program requires modification of
the relative address.

The eight addressing modes may be grouped into
four major classes: literal, direct, relative, and
indirect. Indexing is applied appropriately to each
of the modes.
The literal mode uses information contained within
the instruction format as an operand. Therefore,
a memory access is eliminated which results in a
saving in storage space as well as in execution
time.

The indirect addressing mode with indexing is
applicable to reentrant subroutines because the
index is added after accessing of the indirect
address.

The direct mode is the most. commonly used
addressing mode. In this mode, the operand address is contained within the instruction.

Double indexing is provided through use of the
indirect options when CA = 0-7. Under those conditions, CA will specify a second index register.

INSTRUCTION OPTIONS PROVIDED BY MULTIMODE ADDRESSING

Eight simply structured addressing modes provJded by the instruction's M field allows flexibility
in operand selection.
The eight address modes combined with the 128
instruction codes give the computer several hundred useful instruction options. The M field is
used to select the address option. These options
are provided in almost all instructions. Table V-I
summarizes the possible operand addresses that
can be generated with the eight modes.

M = 2, .Literal - The CA Treid represents a
16-bit half-word.
This word may be an
operand, mask, instruction address, or shift
number.

M = 3, Literal with Indexing - The CA field
represents a 16-bit half-word as in mode 2.
The CA field is added to the contents of the
process register selected by the S field before
the instruction operation takes place. This
provides a useful double operation on many
instructions. Overflow is detected on this addition for those instructions which could
cause arithmetic overflow (F = Xl 0 through
X17, X30, X3l). If it does not occur for
instructions FIIO-FI17, F130, and F131,
the next instruction in sequence is skipped.
The sum replaces the CA field within. the instruction word register, and is used as the new
instruction operand, as in M = 2.

M = 4, Indirect - The contents of the memory word that are addressed by the 16-bit address. This "indirect" address replaces the CA
field within the instruction word register and
is used as in M = O.

M = 5, Indexed, Indirect - The 16-bit CA
field of the instruction word is added to the
contents of the process register selected by
the S field. Overflow on this addition is not

The addressing modes are defined as follows:
a.

M = 0, Direct Address - The CA field of the
instruction word is not modified. The D subfield directly or indirectly selects the specific
memory module. The A and W subfields
specify a half-word operand address in the
specified memory module. On transfer instructions or full 32-bit operands, W is not
used.

M = 1, Direct Address with Indexing - The
CA field of the instruction word is added to
the contents of the index register selected by
the S field. Overflow on this addition is not
detected. The sum replaces the CA field
within the instruction word register, and is
used as the new operand address field as in

M = O.

the D and A subfields of the instruction. The
W bit is not modified. No overflow is detected on this addition. The sum replaces
the D and A subfields of the instruction
within the instruction word register. This
operation yields an address that is relative
to the address on the next instruction in
sequence.

detected. The sum is used to address a 16-bit
word in memory that replaces the CA field
of the instruction in the instruction word register, and is used as the new operand address
field as in M = o.
g.

M = 6, Indirect, Indexed - The 16-bit CA
field of the instruction selects a 16-bit word
in memory which is added to the process register selected by the S field. No overflow
detection occurs. The sum replaces the CA
field of the instruction in the instruction
word register, and is used as the new operand
address field, as in M = o.

If the S field of the instruction is not zero, the

16-bit CA field of the instruction word is added to the contents of the LL register. The
sum is then added to the contents of the process register selected by the S field. This operation yields an indexed address that is relative
to the address of the next instruction in
sequence.

M = 1, Relative - This address option mode
operates in two ways, depending upon the
S field of the instruction word.

The modified CA field is then used to specify
the operand address as in M = 0, unless it is a
transfer type instruction (F = 34 through 36,
40 through 43), in which case the CA field is
used as the operand as in M = 2.

If the S field is all zeros, the contents of the
instruction location register, LL, are added to

•

LITTON COMPUTER CHARACTERIZED BY POWERFUL INSTRUCTION REPERTOIRE

The computer instructions include general-purpose
as well as special instructions useful in real-time
tactical applications.

listed in Tables V-I through V-So Instruction execution times are based on address modes 0 or I:
direct with or without indexing.

The instructions, grouped into seven classes, are

The following symbols and notations are used frequently in the definition of the instructions.

25/26

Letter
CA

Definition
The instruction word's CA field. It is a
16-bit number that is used to address a
location in memory or, in modes 2 and 3
(Literal), CA is used as a 16-bit operand.

Represents a full-word (32 bits) as in
(H)d or (Y)d.

The F field of the instruction word defining the operation code.

H
Hd

(H)

The H field of the instruction word
specifying the accumulator.
Hd or (H)d refers to a processor register
pair. The LSB of the H field is ignored
for instructions requiring the use of a
processor register pair.
The contents of the process register that
is selected by the H field of the instruction word.

Represents the contents of the instruction location register (15 bits). This
number is the address of the next instruction in normal sequence.

The M field of the instruction word
specifying the address mode.

m-n

Denotes the bit positions of a word.
(Y)4-0 denotes the five LSBs of the
operand.

The S field of the instruction word
specifying the index register.

(S)

The contents of the process register that
is selected by the S field of the instruction word. A 16-bit word that is generally used for address indexing.

Transfer address.

SWJ

The set of three conditional jump
switches.

SWH

The set
switches.

Operand address.

(Y)

Operand - (Y) = Y for the literal mode.

(Y)B

A single bit of the operand.

(Y)BL

A single bit of the lower byte of the

The odd numbered register of a process
register pair (1, 3, 5, 7) which contains
the least significant half of a full word.

Program level register.

(Y)BU

The even numbered register of a process
register pair (0, 2, 4, 6) which contains
the most significant half of a full-word.

Definition

of three conditional halt

operand.

Process register 6.

Letter

The number of bit positions shifted on
shift type instructions.

A single bit of the upper byte of the
operand.

One's complement
noted.

unless otherwise

()

Parentheses represent the contents of the
memory location that is addressed by
the word within the parentheses.

Not equal to.

I I

Absolute value.

A'B

Logical AND function.

AlB

Logical inclusive OR function.

A E9 B

Logical exclusive OR function.

A +B

Addition.

A - B

Subtraction.

A x B

Multiplication.

A:B

Division.

Table V-t. Data Operand and Transfer Instruction Address
Action
Mode

Transfer and Execute
Instruction
Address

M-Field

S-Field

0-7

Direct

Y = CA

Z = (Y)

T = (Y)

0-7

Direct with
Indexing

Y = CA + (sj

Z = (Y)

T = (Y)

0-7

Uteral

Z = CA

= CA

0-7

Uteral with
Indexing

Z = CA + (S)

= CA + (S)

0-7

Indirect

Y = (CA)

Z = (Y)

T = (Y)

0-7

Indirect with
Indexing

= (Y)

T = (Y)

0-7

Indirect with
Second Address
Indexing

Y = (CA) + (S)

Z = (Y)

T = (Y)

Relative

Y = CA+LL

Z = (Y)

1-7

Relative with
Indexing

y= CA+ LL+(S)

Z = (Y)

T = CA + LL + (S)

Name

Operand Address

N
00

= CA+ LL

NOTES:

= (CA+ (S))

Operand

CA:
LL:
M:
S:

Contents of the Instruction Address Field
Contents of the Location Register
Mode Designator
Index Designator

y: Value of the Operand Address
Z: Value for the Operand
T: Value for the Transfer Address
( ): Contents of

Table V-2.- Class: Arithmetic Instructions (Sheet 1 of 2)
Subclass
Arith

Arith
and
Skip

Mnemonic

Function Code

Name

Description

Execution Time
(psec) m =0/1

Add

1.60

Subtract

1.60

Replace Add

1.95

Replace Subtract

1.95

Add Absolute

1.60

Subtract Absolute

1.60

(H E+1) X (Y)-+ Hd

Multiply

3.36

031

(H)d 7 cY) -+ H E+1
Remainder -+ HE

Divide

7.20

ADD

110

(H) + cY)~H
Skip next location if!lQ overflow

Add

1.60

SUB

111

(H)-cY)~

H
Skip next location if!!.Q overflow

Subtract

1.60

RAD'"

112

(Y)+H~Y

Replace Add

1.95

cY)~H

ADD

010

(H) +

SUB

011

(H) -

RAD'"

012

(Y)+(H)~Y

RUB'"

013

(Y) - (H)

ADA

014

(H) + I(Y)I

SBA

015

(H) - I(Y)I

MPY

030

DIV

cY)~H

Y
~

Skip next location if!!Q overflow
RUB'"

113

(Y)-(H)~

Y
Skip next location if!lQ overflow

Replace Subtract

1.95

ADA

114

(H) + IcY)1 ~ H
Skip next location if !ill overflow

Add Absolute

1.60

"'Literal modes 2 and 3 will cause the instruction to act as a NOP.

Table V-2. Class: Arithmetic Instructions (Sheet 2 of 2)
Subclass
Arith
and
Skip

Mnemonic

Function Code

Description

Name

Execution Time
(}lsec) m = 0/1

SBA

115

(H) - IcY)1 ~ H
Skip next location if.!!.Q overflow

Subtract Absolute

1.60

ADP

120

(H)d + (Y)d ~ Hd
Skip next location if!!Q overflow

Add Double
Precision

1.92

SDP

121

(H)d -- (Y)d ~ Hd
Skip next location if.!!.2 overflow

Subtract Double
Precision

1.92

MPY

130

(HE+I) X (Y)~Hd
Skip next location if ~ overflow

Multiply

3.36

Div

131

Remainder
(H)d 7 Y -~ HE+l
Skip next location if!!Q overflow

Divide

7.20

Vol

Table V-3. Class: Data Manipulation Instructions (Sheet 1 of 3)
Subclass
Logic

Shift

Mnemonic

. Description

Function Code

Name

Execution Time
(psec) m = 0/ I

EOR

020

(H) Ef> (Y) ~ H

Exclusive Or

1.60

lOR

021

(H)j(Y) ~H

Inclusive Or

1.60

AND

022

(H)'(Y)~H

Logical And

1.60

RER'"

024

(Y) Ef> (H) ~ Y

Replace
Exclusive Or

1.95

RIR'"

025

(Y)j(H)~Y

Replace Inclusive Or

1.95

RAN'"

026

(y). (H)

Replace Logical And

1.95

SLL

044

(H)d shifted logically, left, circularly n places as specified by
(Y)4-0'
HIS ~ H I6
H31 ~ HO

Shift Long Left

2.72
8 Shifts

NLL

045

(H)d shifted algebraically, left, open n places as specified by
(Y)4-0 or until H31 =f H 30 . Count residue ~ S.

Normalize Long Left

2.88
8 Shifts

Shift Long Righ t

2.72
8 Shifts

Shift Algebraically
Right

2.72
8 Shifts

H31 ~ H3I
H14 ~ H I6
SLR

056

(Y)4-0'

057

H15~ HIS
O~HO

(H)d shifted logically, right, circularly n places as specifed by
HO~ H3I

SAR

H16~ H I5

(H)d shifted algebraically, right, open n places as specified by
(Y)4-0'
H31 ~ H31
H 16 ~ H14

"'Literal modes 2 or 3 will cause the instruction to act as a NOP.

HIS ~ HIS
H31 ~H30

Table V-3. Class: Data Manipulation Instructions (Sheet 2 of 3)
Subclass
Shift

Set/Reset
Bit

Mnemonic

Function Code

Name

Description

Execution Time
(jlsecl m = 0/ I

SNC

046

(H E+1)shifted logically, left, circularly n places as specified
by (Y)4-0·
HIS ~HO
(HE) + number of ones shifted ~ HE

Shift And Count

2.72
8 Shifts

RFT

047

(HE) shifted logically left and (H E+)) shifted logically right
n places as specified by (Y)4-0.
HO~ H 16
H31 ~ HIS

Reflect

2.72
8 Shifts

SBL*

060

a)
b)

1 --l- (Y)BL as specified by H.
An interprocessor interrupt is set if other PAR
address is accessed.

Set Lower Bit

1.95

SBU*

061

a)
b)

1 -~ (Y)BU as specified by H.
An interprocessor interrupt is set if other PAR
address is accessed.

Set Upper Bit

1.95

RBL*

062

o~ (Y)BL as specified by H

Reset Lower Bit

1.95

RBU*

063

o~ (Y)BU as specified by H

Reset Upper Bi t

1.95

SBL*

160

a)
b)
c)
d)

1 -+ (Y)BL as speCified by H.
External interrupt lockout is reset
An internal interrupt is set if PAR address is accessed.
An interprocessor interrupt is set if other PAR address
is accessed

Set Lower Bit

1.95

SBU*

161

a)
b)
c)
d)

1 -+ (Y)BU as specified by H
External interrupt lockout is reset
An internal interrupt is set if PAR address is accessed
An interprocessor interrupt is setif other PAR address
is accessed

Set Upper Bit

1.95

--r---

----_.-

*Literal modes 2 or 3 will cause the instruction to act as a NOP.

Table V-3. Class: Data Manipulation Instructions (Sheet 3 of 3)
Subclass

Mnemonic

Function Code

Set/Reset
Bit

RBL*

162

RBU*

163

Description
a)
b)
c)

o~ (Y)BL as specified by H

a)
b)
c)

o~ (Y)BU as specified by H
External interrupt lockout is reset
An internal interrupt is set if PAR address is accessed.

Name

Execution Time
(/JSec) m =0/1

Reset Lower Bit

1.95

Reset Upper Bit

1.95

External interrupt lockout is reset
An internal interrupt is set if PAR address is accessed

*Literal modes 2 or 3 will cause the instruction to act as a NOP.

Table V-4. Class: Data Handling Instructions (Sheet I of 3)

Subclass
Load
Register

Mnemonic

Description

Function Code

LOR

004

(Y) -+ H

LOO

006

(Y)d-+ Hd

Name

Execution Time
(J1Sec) m =~~

Load Register

1.60

Load Double

1.76

Load Absolute

1.60

LOA

016

I(Y)I-+ H

LOA

116

I(Y)I-+ H
Skip next location if!!2 overflow: (Y)

LOC

017

(Y) -+ H

LOC

117

LRS

Store
Zeros
Store
Register

._-------

-,---- --"--

Load Absolute

1.60

Load Complement

1.60

(Y) -+ H
NOTE: 2's complement
Skip next location if!!2 overflow: (y) =1= -1.

Load Complement

1.60

104

LL/LP/base memory address/status -+H as specified by the
S field. The M and CA fields are not used by this instruction.

Load Register
Special

1.00

STZ

072

0-+ (Y)

Store all Zeros

1.95

STR*

005

(H) -+ Y

Store Register

1.95

STO*

007

(H)d -+ Yd

Store Double

1.95

EXC*

002

(Y) -+ H

Exchange

1.95

;=-1.

-NOTE: 2's complement

Exchange

(H) -+ Y

.EXD*

003

(Y)d -+ Hd

*Literal modes 2 or 3 will cause the instruction to act as a NOP.

(H)d -+ Yd

Exchange Double

2.27

Table V-4. Class: Data Handling Instructions (Sheet 2 of 3)
Subclass
Move

Mnemonic
MVI

MVI

Description

Function Code
071

171

(H) shifted logica!ly right, circularly n places as specified
by M field. HO ~ HIS

[(H) shifted • ,C A] / [(S) • CA] ~ S

(H) ~ H unless H = S
NOTES: 1. Address options do not exist for this
instruction .
. 2. CA = mask

M=O
(H) shifted logically left, circularly 8 places. HIS -+ HO

Name

Execution Time
(usee) m = 0/1

Move and Insert

1.92
4 Shifts

Move and Insert

2.24
8 Shifts

Move and Zero

1.60
4 Shifts

M::;i::O
(H) shifted logically left, circularly n places as specified
by the M field. HIS ~ HO
b)

[(H)shifted • C A] / [(S) • CAl -+ S

(H) ~ H unless H = S
NOTES: 1. Address options do not exist for this
instruction.
2. CA = mask

MVZ

070

(H) shifted logically right, circularly n places as specified
by the M field. HO -+ H 15

(H) shifted • CA -+ S

(H)

H unless H = S

NOTES: 1. Address options do not exist for this
instruction.
2. CA = mask

Table V-4. Class: Data Handling Instructions (Sheet 3 of 3)
Subclass
Move

Mnemonic
MVZ

--------------------------------------,,--------------------r-----"-------Execution Time

Function Code

170

Description

M :: 0
(H) shifted logically left, circularly 8 places. H15 -l> HO

Name

Move and Zero

(J,lSe HO
b)

(H) shifted· CA

(H) -l> H unless H

NOTES: 1. Address options do not exist for this
instruction
2. CA = mask
-------------------------------------~------------------~----"----------

Table V-So Class: Jump Instructions (Sheet 1 of 3)
.-

Subclass
Algebraic
Compare

Mnemonic
JTW

- ----.--..

~--

... --

---

Description

Function Code
037

(Y) < (H) : LL + 2 -+ LL (next loc)

Name
Jump Three Ways

(Y) = (H) : LL + 4 -+ LL

Execution Time
(/JSec) m =0/1
1.60 Y~ H
1.76 Y > H

(Y) > (H) : LL + 6 -+ LL
CJL

050

(Y) ~ (H) : LL + 2 -+ LL (next loc)

Compare, Jump if Less

1.60

Compare, Jump if
Equal

1.60

Compare, Jump if
not Equal

1.60

Compare, Jump if
Greater

1.60

Gated Comparison,
Jump if Inside

1.76

Gated Comparison,
Jump if Outside

1.76

Test Lower Bit,
Jump if Zero

1.60

(Y) < (H) : LL + 4 -+ LL
CJE

051

(Y) =F (H) : LL + 2 -+ LL (next loc)
(Y) = (H) : LL + 4 -+ LL

052

(Y)

= (H) : LL + 2 -+ LL (next loc)

(Y) =F (H) : LL + 4 -+ LL
CJG

053

(Y) ~ (H) : LL + 2 -+ LL (next loc)
(Y) > (H) : LL + 4 -+ LL

Gated
Compare

GCI

GCO

054

055

I(Y) - (H)I

> (H 6) : LL + 2 -+ LL (next loc)

I(Y) - (H)I

TLZ

064*

< (H6) : LL + 2 -+ LL
(H)I > (H6): LL + 4 -+ LL

I(Y) - (H)I
I(Y) -

Test Bit

(H 6): LL + 4

(next loc)

(Y)BL =F 0 : LL + 2 -+ LL (next loc)
(Y)BL
BL

= 0 : LL + 4 -+ LL

= Lower bit as specified by H

*Literal modes 2 or 3 will cause the instruction to act like a NOP

Table V-So Class: Jump Instructions (Sheet 2 of 3)

Subclass
Test Bit

Mnemonic
TUZ

Description

Function Code
065*

-.---------------

(Y)BU =F 0 : LL + 2 ~ LL (next loc)
(Y)BU = 0 : LL + 4

Name

Execu tion Time
(~ec
~:JU.L

Test Upper Bit,
Jump if Zero

1.60

Test Lower Bit,
Jump if One

1. 60

Test Upper Bit,
Jump if One

1.60

Test Lower Bit,
Jump if Zero

1. 60

Test Upper Bit,
Jump if Zero

1.60

BU = Upper bit as specified by H

TLF

066*

(Y)BL =F 1 : LL + 2 ~ LL (next loc)
(Y)BL = 1 : LL + 4 ~ LL
BL = Lower bit as specified by H
-

TUF

067*

(Y)BU =F 1 : LL + 2 ~ LL (next loc)
(Y)BU = 1 : LL + 4

BU = Upper bit as specified by H

TLZ

164*

(Y)BL =F 0 : LL + 2 ~ LL (next loc)
(Y)BL=O:

LL+4~LL

BL = Lower bit as specified by H

TUZ

165*

Set external interrupt lockout

(Y)BU =F 0 : LL + 2 ~ LL (next loc)
(y)BU=O:

LL+4~LL

BU = Upper bit as specified by H
b. Set external interrupt lockout
*Literal modes 2 or 3 will cause the instruction to act like a NOP.

Table V-So Class: Jump Instructions (Sheet 3 of 3)
Subclass
Test Bit

Mnemonic
TLF

Description

Function Code
166*

a. (Y)BL

* 1 : LL + 2

LL (next loc)

= 1 : LL + 4 -+ LL
BL = Lower bit as specified by H

(Y)BL

Name

Execution Time
(psec) m = 0/1

Test Lower Bit,
Jumper if One

1.60

Test Upper Bit,
Jump if One

1.60

b. Set external interrupt lockout

TUF

167*

a. (Y)BU

* 1 : LL + 2

LL (next loc)

= 1 : LL + 4 -+ LL
BU = Upper bit as specified by H.

(Y)BU

b. Set external interrupt lockout

*Li teral modes 2 or 3 will cause the instruction to act like a NOP.

Table V-6. Class: Transfer Instructions (Sheet 1 of 2)
Subclass

Mnemonic

Description

Function Code

Name

DTX

032

(H) - 2 ~ H : 0 ~ H on wrap around

L1. + 2 -~ LL ifH
033

(H) + 1 ~H:

040

(H)

Increment by One
and Transfer

1.60

= 0 (next loc)

O~H

LlL + 2 ~ LL ifH
XEZ

1.60

on wrap around

T~LLifH=I=O

Increment by Two
and Transfer

T ~ LL if H :#: 0
LL + 2 ~ LL ifH

133

1.60

= 0 (next loc)

(H) + 2 ~ H : 0 ~ H on wrap around

a)
b)

lOX

Decrement by One
and Transfer

T ~ LL if H :#: 0
LL + 2 ~ LL ifH

132

1.60

= 0 (next loe)

(H) - 1 ~ H : 0 ~ H on wrap around

a)
b)

ITX

Decrement by Two
and Transfer

T ~ LL if H :#: 0

DOX

Execution Time
(psec) m:= 0/1

= 0 (next loc)

= 0: T~LL

1.60

Transfer if H =1= 0

1.60

Transfer if
H is Negative

1.60

Transfer if H

(H) =1= 0: LL + 2 ~ LL (next loc)
XNZ

041

(H) =1=0 :
(H)

XNG

042

T~LL

= 0 : LL + 2 ~ LL (next loc)

(H) 15 :: 1 : T ~ LL
(H)15

7= 1 : LL + 2 ~ LL (next loe)

Table V-6. Class: Transfer Instructions (Sheet 2 of 2)
..... -

Subclass

Mnemonic

Description

Function Code

XPS

043

Control
Transfer

XFR

034

XLK

03S

{Hhs =0: T-+LL
{Hhs =1= 0: LL + 2 -+ LL (next loc)
T-+LL

T-+LL
LL

XSW

036

+ 2 -+ H (next loc)

Hb = SWJb : T -+ LL

Hb =1= SWJb : LL + 2 -+ LL (next loc)
Comparison is by bit match

Name

Execution Time
(/JSec) m = 0/1

Transfer if
H is positive

1.60

Transfer
Uncondi tional

1.60

Transfer
Unconditional and
Store Link

1.60

Transfer on
Console Transfer
Switch

1.60

Table V-7. Class: Input/Output Instructions
Subclass
I/O

Mnemonic

Function Code

DEC

074

DES

174

Description
(yhS-8

I/O data lines 15-8

(Y)s-o

I/O data lines 5-0

(Y) 15-8 ~ I/O data lines 15-8

(Y)5-0
b.

OFR

076

I/O address lines 5-0

Name

Execution Time
~ec) I1)

External Device
Command

4.16

External Device
Command and
Suicide

5.31

Output from Register

4.32

Input to Register

4.48

= ~~

Res et e,xternal interrupt lockout.
Set internal interrupt.
Res et J)AR status bit associated with existing level.

(H)d

~I /0

data lines 31-0

(Y)S-O ~I/0 address lines 5-0

.ITR

075

I/O dat a iiIles 31-0 ~ Hd
(Y)5-O ~ I/O address lines 5-0

Table V-S. Class: Miscellaneous Instructions
Subclass

Mnemonic

Function Code

Misc

EXE

001

Description
a.

LL~LL

Name

Execution Time
(usec)m=O/1

Execute

1.60

Halt

1.60

b. The next instruction is accessed from address T.

= SWHb·

Comparison is by bit match.

HLT

000

Halt if Hb

MBA

027

(Y) ~ memory module addressed by (Y)14-15

Memory status -- Hd if H =F 0

(Y) ffi (H) ~ Y

Set YO if [(Y)

LL + 4

QED

124*

Memory Bank
Assignment

2.16 H = 0
2.56 H 1 0

Queue Table
Enque and Deque

1.95

No operation

0.80

a. Macro is activated upon access of instruction from
memory.
b. CPU halts and waits for Function End signal from SPU.
c. CPU accesses next instruction from memory upon receipt
of the Function End signal.

TBD

(H)] =#= 0

LL if the following equation is true

[(Y) ffi (H)]

= 0 • YO = 1

or
[(Y) ffi (H)] =#= 0 • YO

LL + 2 ~ LL (next loc) if the above equation is false
d.

Macro

Nap

077

TBD

Any Unused
Code

Set external interrupt lockout

NOTE: The SPU can generate the Function End signal immediately upon recognition of its instruction when it is
advantageous to execute the macro instruction concurrently with subsequent CPU instructions.
"'Modes 2 or 3 will cause the instruction to act as a Nap.

SPECIAL INSTRUCTIONS FACILITATE PROGRAMMING _ _ _ _ _ _ _ _ _ _ _ __

A number of special instructions are provided to
simplify programming and reduce program execution time.
Special instructions that will simplify programming
include:
Queue Table Enque and Deque
This special instruction provides a more convenient
method for handling common data files between
multiple processor and program level, as well as
providing a suitable method of handling multiple
I/O termination to a common program level (Figure 5-6).

will be set in the control word but the next location will be skipped in memory. The processor
must then wait to be called before u~ing the
table.
When a processor has finished using the table, it
must again execute the Queue Table instruction.
The processor queue bit and the "in use" bit will
be reset if no other queue bits are set in the instruction. The next location will be accessed by
the processor to return it to its next routine.
If other queue bits are still set when the dequeing

This is accomplished by using a designated control
word for each data file. The control word is composed of an "in use" bit (bit 0) and 14 priority bits
(14-1). Bit 15 must always be zero.

instruction is executed, the "in use" bit will not be
reset and the next location in memory will be
skipped. The processor will then determine the
next highest priority (relative bit position) and
issue a call to that processor by setting a bit in its
PAR word and generating an interprocessor interrupt (SBL and SBU instructions).

The same instruction is used for both enqueing and
dequeing. A processor may use the file without
being called only when the control word contains
all zeros. If the file is in use when initially accessed by a processor, the appropriate queue bit

The interrupt lock-out is set during this instruction
to prevent a program level change from occurring
before the processor completes the routines necessary for assuring an orderly transition in the usage
of the table.

0 I

USE BIT

PRIORITY BITS

FILE NOT
IN USE

liN
I

CONTROL WORD

(Y) INITIAL

(Y) FINAL

SKIP

(HI

0000008

002001 8

0400018

042001 8

YES

002001 8

0000008

002001 8

042001 8

040001 8

YES

002001 8

ENOUE

LAST USER

DEOUE

Figure 5-6. Queue Table Instruction
44

Move Instruction
The Move and Zero instruction (Figure 5-8) permits the storage of the bits into the designated area
of the register but sets the remaining bits to zero.

The two Move instructions allow any number of
bits in one register to be addressed by means of a
mask and moved to any position in another
register.

This capability greatly facilitates the handling of
"packed" data which in tum minimizes memory
requirements by allowing several short words to be
stored into a single memory word.

The Move and Insert instruction (Figure 5 -7)
allows the bits to be stored into the designated
area of the register without disturbing the remaining contents of that register.

EQUATION:

En SHIFTED . C~

ES).c~s

CA MASK

INITIAL

o E01 10~ 000

(H)
SHIFTED

1 010 000 [201 10iJ 000

(H)S'CA

o 000 000 ~01 1O~

o 000

101 000

000

11 11

~ 000

o 101

100

~01

o 101

100

~OO OOOJ 111

OO Hd.

The three instructions used in perforlning the comparisons are as follows:
1.

2.
3.

FCL: The next instruction in memory is skipped if Yd < Hd.
FCE: The next instruction i~ memory is skIpped if Yd = Hd.
FCG: The next instruction in memory is skipped if Yd > Hd.
,"

L9n9 Multiply (LMY) Instruction

prior to executing the compare instructions. If the.,
numbers are not pre-normalized, an error bit is set
and the next instruction in memory is executed.

The process register pair (H)d is multiplied by the
operand (Y)d and the 64-bit product is stored in
Hd and Hd + 1. The multiplicand is restricted to
H(O,1) or H( 4 ~. The product will be stored in
H(O,I,2,3) or H(4,5,6,7)'

Double Precision Multiply (DMY) Instruction

A (+ 1) product will result in an error condition.
The process registers are left unaltered and the next
instruction in memory is executed. Use of the trap
instruction will cause the next location in memory
to be shipped if no error condition exists.

It is assumed that all numbers are pre-normalized

The DMY instruction performs a multiplication of
the double length operand (Y)d and a process register pair (H)d. The 32-bit truncated product is stored
in the process register pair (H)d.
Multiplication of a (-1) multiplier by a (-1) multiplicand will resul t in an error condition. The process
register pair is left unaltered and the next instruc. tion in memory is executed. Use of the trap instruction will cause the next location in memory to be
skipped if an error does not exist.

Long Divide (LDV) Instruction

The 64-bit dividend (H)d, d + 1 is divided by the
divisor (Y)d. The remainder is stored in Hd and
the 32-bit quotient is stored in (H)d + 1.
The 64-bit dividend will be fetched from either
H(O,I,2,3) or H(4,5,6,7)'
An illegal divide will occur if the dividend is greater

Double Precision Divide (DDV) Instruction

The dividend (H)d is divided by the divisor (Y)d.
The quotient is placed in Hd and the remainder is
discarded. An illegal divide will occur if the dividend is greater than the divisor or the dividend is
equal to the divisor and has the same sign. An illegal
divide will cause an error bit to be set and the process register pair will ,be left unaltered.
A trap instruction will cause the next instruction in
memory to be skipped if no error condition exists.

than the divisor or the dividend is equal to the divisor and has like sign. An illegal divide will cause an
error bit to be set and the process registers will be
left unaltered.
A trap instruction will cause the next instruction in
memory to be skipped if no error condition exists.
Packaging and Power

The extended performance arithmetic unit is packaged on four logic cards which are inserted directly
into the processor unit ATR case.
No additional power is required other than that
already provided by the processor power supply.
67/68

Table VII-I. Summary of Instructions For Extended Performance
Arithmetic Option
Execution
Times
(,usee)

Mnemonic

Code

Operation

FAD

140*

Hd + Yd .... Hd

Floating Point Add

5.24

FSB

141*

Hd - Yd .... Hd

Floating Point Subtract

5.24

FMP

142*

Hd x Yd .... Hd

Floating Point Multiply

6.24

FDV

143*

Hd
Yd .... Hd

Floating Point Divide

FAD

150*

Hd + Yd .... Hdt

Floating Point Add-Trap

5.24

FSB

151*

Hd - Yd .... Hdt

Floating Point Subtract-Trap

5.24

FMP

152*

Hd x Yd .... Hdt

Floating Point Multiply-Trap

6.24

FDV

153*

Hd
Yd .... Hd

Floating Point Divide-Trap

FCL

101 *

Skip Next Location
If Y < H

Floating Point Compare,
Jump is Less

2.44

FCE

102*

Skip Next Location
If Y = H

Floating Point Compare,
Jump if Greater

2.44

FCG

103*

Skip Next Location
If Y > H

Floating Point Compare,
Jump if Greater

2.44

DMY

144

Hd x Yd .... Hd

Double Precision Multiply

7.24

DDV

145

Hd .... Hd
Yd

Double· Precision Divide

DMY

154

Hd x Yd .... Hdt

Double Precision Multiply-Trap

DDV

155

Double Precision Divide-Trap

DCL

105

Skip Next Location
If Y < H

Double Precision Compare,
Jump if Less

2.44

DCE

106

Skip Next Location
If Y = H

Double Precision Compare,
Jump if Less

2.44

DCG

107

Skip Next Location
If Y > H

Double Precision Compare,
Jump if Less

2.44

LMY

146

(H)d x (Y)d'"
Hd, d + I

Long Multiply

7.64

LDV

147

(Hd,d+l)
HI+
1
(Y)d
.... (
Remainder . . Hd

LMY

156

LDV

157

(H)d x (Y)U"Hd, d + It
(H)d, d + I
. . Hd + I
(Y)d
Remainder ... Hdt

Name

.... Hut

Long Divide

Long Multiply-Trap

Long Divide-Trap

*Literal Modes 2 or 3 will cause the instruction to act as an NOP.
tSkip Next Location If No Error

12.64

15.64
7.24
15.64

16.04

7.64

16.04

SECTION 8. L-304H SOFTWARE

The programs in the Resident Supervisor category
can be further considered as three groups designated as Control Programs, Service Programs, and
I/O Programs. The Control Programs are those
which determine the course of action to be taken
by the L-304 operating system. The Service Programs are those routines which perform specific
non-I/O functions, such as the Octal Conversion
Routine. Most of these routines are open; i.e., they
may be called directly by the User Program, perform their function, and return to the User Program. The I/O Programs handle the L-304 peripherals in the manner best suited for the L-304
operating system. These routines are also open for
use by the User Program, providing that the
method of peripheral handling is suitable to the
user's problem.

The L-304H Computer incorporates a software
package which includes a comprehensive set of
operator-controlled utility/facility programs and a
computer test program for use in detecting and
isolating computer failures.
Operating System
The L-304H utilizes the standard operating system
provided for all the Litton family of L-304 computers. This system has been developed to provide
effective communication between the user and the
computer system, and to aid in efficient use of the
system.
The operating system is a group of programs that
controls the loading and execution of object programs with provisions for relocatability and for
card, tape. (magnetic or paper), and printer handling. Troubleshooting aids are also provided in the
form of memory dumps and program trace performed at operator-selected points. In addition the
L-304 operating system provides the required flexibility to allow use of the computer in varying memory configurations with no less than 16K words as
a minimum.

A block diagram of the L-304 operating system and
related software is shown in Figure 8-1 and 8-2.
The Resident Supervisor structure is illustrated in
Figure 8-3. The programs in this group also fall
into three categories: (1) the System Loading Control Programs, (2) the Functional Input Programs,
and (3) the Modification Programs. This structure
is illustrated in Figure 8-4. The L-304 operating
system Loading Control Programs consist of all programs other than the Resident Supervisor which
may be used by L-304 during a load operation.

The L-304 operating system is categorized in three
major groups: (1) the Resident Supervisor, (2) the
Loading Control Programs, and (3) the Support
Programs. Of these, only those programs in the
Resident Supervisor category must be in core storage at all times.

L3040S
RESIDENT
SUPERVISOR

CONTROL
ROUTINES

BOOTSTRAP
LOADER

OPERATOR
INITIATED
LOAD
ROUTINE

OPERATOR
COMMUNICATIONS
ROUTINES

SUPERVISOR
CONTROL

ERROR
DIAGNOSTIC
ROUTINE
(OSERRORI

1/0
ROUTINES

SERVICE
ROUTINES

DUMP

OPERATOR
INTERRUPT

SYSTEM
LOADER

MASTER
RESET
RECOVERY

BINARY
TO OCTAL
CONVERSION
ROUTINE

KEYWORD
GENERATION
ROUTINE

MULTIPLEX
I/O
ROUTINE

DURA
I/O
ROUTINE
37269

Figure 8 -1.

L-304 OS Resident Supervisor

RESIDENT
SUPERVISOR

PATCH

MAP
ROUTINE

INSERT

FETCH
IRELOCATING
LOADERS)

JOB
CONTROL

CARD
CONVERSION
ROUTINE

RELOCATOR

PREPROCESSOR

TRACE

POSTPROCESSOR
SAVE

POSTPROCESSOR

START
ROUTINE

LIBRARIAN

COM POOL
ASSEMBLER

PRINT
FORMAT
ROUTINE

UNIVERSAL
LOAD
ROUTINE

SORT
ROUTINE

SLANG
SETUP
AND
EXECUTIVE

INSTRUCTION
TRAIL

37269-

Figure 8-2.

L-304 Operating System

RESIDENT SUPERVISOR
--

NON-RESIDENT L304 OS ROUTINES
BOOTSTRAP LOADER

SUPERVISOR CONTROL
60
SYSTEM LOADER
FETCH
INITIALIZATION
ROUTINE

INSERT

PATCH

OPERATOR INITIATED
LOAD (OSSAVE)

180

110

MASTER RESET RECOVERY
START
ROUTINE

LINKAGE
EDITOR

FETCH LOADER

OPERATOR INTERRUPT
250

180

150
ERROR ROUTINE

MAP ROUTINE
200

BINARY-TO-OCTAL
CONVERSATION ROUTINE

JOB CONTROL
670

KEYWORD GENERATION ROUTINE

CARD CONVERSION ROUTINE
1070

DUMP ROUTINE

RELOCATOR
1010

SLANG COMPI LER
1900

DURA 1/0 ROUTINE (98)

PRE-PROCESSOR
390

TRACE INPUT ROUTINE
300
RESTART

SAVE

110

MULTIPLEX
1/0
ROUTINE
(460)

LIBRARIAN
750
L304 0s::8440
GRAND TOTAL::::19,780

Figure 8-3. Resident Supervisor Structure

37269

PROGRAMS THAT ARE
LOADED BY AND USE THE
SERV!CES OF THE L304 OS

PROGRAMS DEPENDENT
UPON L3040S

L304 ASSEMBLER
SLAt~G

SETUP Af"JO

EXECUTIVE
600

COMPOOL ASSEMBLER

POST-PROCESSOR
SAVE ROUTINE

TRACE PROGRAM

400
+1000 DATA BASE

1500

UNIVERSAL LOAD ROUTINE

POST-PROCESSOR
DATA EDITOR

500

840
+1220 DATA BASE
PRINT FORMAT ROUTINE
500

SORT
700

DUPLICATION ROUTINES
300

TOTAL:::: 1840

TOTAL:::: 9500

Figure 8-4. L-304

Support Programs

Assembly Program
I

The L-304 Assembly Program is available for use
on a Litton L-304, or IBM 360 or IBM 370
computer.
The assembly language is relatively standard, i.e.,
each instruction (statement), excluding the label
and comments field, consists of an operator and
variable field. The operator (op code) identifies the
operation (add, subtract, etc.); the variable field
generally represents such things as storage locations, general registers, immediate data, or constant
values. The variable field in assembly language can
contain from I to 4 subfields, depending on
the instruction class.

Symbolic instruction statements are one-for-one
representations of L-304 machine instructions
The assembler language provides for the symbolic
representation of any addresses, machine components (such as registers), and actual values needed
in source statements. Also provided is a variety of
forms of data representations: decinial, octal, hexadecimal, or character representation of binary
machine values. (The programmer selects the representation best suited to express a given piece of
data.)

The assembly program translates or processes
assembler-language programs into machine language
for execution by the computer. The program
written in the assembler language (used as input
to the Assembler) is called the source program; the
machine-language program produced as output from
the Assembler is called the object program. The
translation or processing procedure performed by
the Assembler to produce the object program is
called assembling. The object program produced
is also referred to as an assembly. Program statements (source statements) written in assembler lan-

LABEL

LABL

The following example illustrates the use of the
label (name), operation, variable field (operand),
and comments entries as they appear on the coding form. An "Add" instruction has been labeled
by the symbol LABL; the operation entry (ADD)
is the mnemonic operation code for an add operation; and the variable field 5, 6 designates the two
general registers whose contents are to be added.

OPERATION

ADD

guage may consist of: a label to identify the statement; a symbolic operation code (mnemonic) to
identify the function the statement represents; and
a variable field, consisting of one to four sub fields
to designate the data or storage locations used in
the operation, and space for comments.

VARIABLE FIELD COMMENTS

5,6

ADD REGISTER 5
TO 6. STORE SUM
IN6.

IDENTIFICATION

100

field entry, if used, may be numeric or symbolic or
a combination of numeric and symbolic. The variable field entry may consist of from zero to four
sub fields, depending upon the type of operation
code specified.

The basic structure of the assembler language is a
source statement consisting of a label entry, an
operation entry, and a variable field entry. The
label entry (optional) is a symbol. The operation
entry (mandatory) is a mnemonic operation code
representing an assembler instruction. A variable

360. The simulator is written in IBM 360 Basic
Assembly Language and can be run on any model
of the IBM 360 computer which is operating under
the S6360 Operating System. The resuits of a simulator run will, with the specific exceptions, be
identical to the results that would be obtained if
the same program were to be executed on an L-304
computer.

Service Routines

The L-304 Service Routines listed below constitute
functions which are used by most program systems.
The routines may be loaded by the Operating
System Program and entered from external programs or they may be entered directly by operator
control.
Mathematical Routines

This group is divided into the foilowing five subsections:

The simulator is designed to accept as input the
output of the L-304 Assembler Program. This input
-~ consists of a machine language representation of
the programmed instructions. The user of the simulator indicates, via control cards:

a. Trigonometric Functions
•
•
•
•

a. The trace or dump features that he wishes to
use.
b. The peripheral device(s) he wishes to simulate.
c. The modification he wishes to make to the assembled program(s) ..
d. The address and program level at which the execution of the L-304 program is to start.
e. The maximum number of lines of output or the
maximum number of L-304 instructions he
wishes to execute in this run.

Sine/Cosine
Tangent
Arc Tangent
Arc Sine/Arc Cosine

b. Square Root
c. Double Precision Arithmetic Functions
• Add/Subtract
• Multiply
• Divide

The seven modules of the simulator have specific
functions.

d. Logarithmic Functions (Base 2, e, or 10)

The Input Module has four major functions:

e. Exponential Function (XY)

1. To read in the control cards
2. To read in the binary deck(s)
3. To resolve any external linkages in the L-304
programs
4. To relocate, if necessary, the data in the binary
deck(s).

Conversion Routines

The routines within this group will:
a. Format 16-bit data words into EBCDIC characters for binary, octal, hex, or BCD output
b. Pack binary, octal, hex, or BCD EBCDIC character inputs into 16-bit words
c. Convert binary to BCD or BCD to binary. The
Edit will convert a signed binary fraction to a
signed BCD fraction and format in EBCDIC
(with leading zeros suppressed and inserted decimal point).

The Universal Load Routine deformats the control
cards read by the Input Module and stores the data
from the various fields in the 360 core.
The Instruction Interpreter Module performs the
execution of all L-304 instructions except the three
I/O instructions and maintains the L-304 real time
clock.

Interceptor/Simulator Program

The Peripheral Simulator simulates the peripheral
devices that normally interface with the L-304.

The L-304 Interpreter/Simulator is a group of seven
modules (separate assemblies) designed to simulate
the execution of any L-304 program on the IBM
76

The Debugging Module is responsible for generating
program traces, and dump output.

a. Instruction Test - all instructions (except I/O)
and addressing modes are tested.
b. Internal Interrupt Test - all logic related to program level call is tested except for I/O stimulators.
c. Real Time Clock Test - the L-304 program
controlled clock is tested along with I/O stimulated program level call.
d. Computer Time-Out Logic Test - central processor, memory, and I/O control timeout logic
tested.
e. Watchdog Timer Test - the programmed controlled times is tested.
f. Data Entry and Display Test - the operator
communication functions are tested
g. Extended Memory Addressing - all logic associated with memory access by program is tested
h. Memory Test - one or more memories are tested
and the test is directed to locating failures in
the data lines, addressing lines, and memory controllogic.

The I/O Control Simulator simulates both the
L-304 IOC and the I/O devices defined by the
customer that are to be present on the L-304. This
module also maintains the L-304 real time clock.
General Machine Test Program (GMT)

The GMT program consists of a set of program
modules which exercise and test the functions of
the central processor unit, memory unit(s) and I/O
control unit. The program is constructed to facilitate computer troubleshooting by providing an
error halt option at each test point and an option
to loop on a given test.
The program is loaded into memory from card
decks using the bootstrap load feature of the
L-304.
The program modules of the GMT have specific
functions described as follows:

SECTION 9. SYSTEM PACKAGING, POWER, AND CONTROLS

Design and packaging of the L~304H Computer
makes it suitable for use in a wide variety of rugged
tactical environments.

Standard electronic circuits, consisting of highspeed Schottky SSI and MSI elements are used
throughout the processor and memory units. Eight
types of SSI and 14 types of MSI circuits are used,
with components mounted on four- to six-layer
printed circuit cards constructed by standard
plated-through hole technique, with ground and
power layers provided.

Each module of the airborne version of the L-304H
Computer is packaged in a three-quarter long ATR
case, which measures 7.5 inches by 7.5 inches by
19.5 inches and weighs approximately 30 pounds.
One ATR case contains the processor unit, including the control, arithmetic, and input/output circuits. Another case, containing the memory unit,
includes a 16,384 word core stack and associated
memory circuitry (Figures 9-1 and 9-2).

Heat generated on the cards is conducted through
integral bar-type heat sinks to the sides of the ATR
case where spring pressure is applied to maintain
positive contact to cold plates on the side of the
structure. With the use of cold plates, components
are isolated from air flow contaminants.

Provision for growth is afforded by the modular
construction technique used throughout both units.
Memory size can be increased by simply adding
16K memory units in a plug-in arrangement.
Multiple processor capability is likewise achieved
by the modular addition of processor units.

The processor and memory units are powered by
integral power supplies. Input power is 115 volts,
400 Hertz. Processor power consumption is 220

Access to the functional cards and power supply
assemblies is gained. by removing the top shear
cover of the unit case. Removal of the bottom
shear cover provides access to the wiring side of the
wire-wrap plate. All covers are fitted with EMI
gaskets.

watts; memory power consumption is 260 watts
under nominal operating conditions. Automatic,
orderly shutdown is provided by power sequencing
circuitry, and power loss protection is provided·
by power fault interrupt to the CPU. Operation
in both steady-state and transient conditions is
as specified in MIL-STD-704A for category B
equipment.

The power supply furnishes a regulated +5 volt,
40 ampere output to the processor unit. Distributed
power is routed through the VAST connector to
accommodate VAST testing requirements. A terminating cap (mating connector) is provided to return
direct power during operation, and each card is supplied power through a separate power cable. The
power supply has been packaged with four separate, removable units. In addition to providing thermal advantages, this packaging of elements accommodates testing, fault isolation, and replacement of
elements. The four units are: (1) switch assembly,
(2) rectifier assembly" (3) auxiliary regulator card
assembly, and (4) main regulator control card assembly. These four units plug in directly to the
single processor unit wire wrap plate.

External interface connectors are mounted either
on the front faces of the ATR cases or on the rear
depending upon specific customer applications.
VAST test connectors are provided on the sides of
the cases and on the edges of the printed circuit
cards.
The ATR structures are dip-brazed assemblies which'
give extremely high strength-to-weight ratios and
incorporate two side cold plates of finned aluminum. As a result of the dip-brazing process, the
fins become an integral part of the primary structure and provide a direct, unimpaired thermal path
for all internal components. Cooled air is not
required, and the computer uses only forced ambient air for heat dissipation.

The switch and rectifier assemblies are modular subassemblies using a one-piece heat sink which mounts
discrete components directly to its surface. The
heat sink is then mounted directly to the system
cold plates, providing a direct thermal path to system cooling.

The L-304H Computer is designed for installation
in a variety of ground, shipboard, and airborne environments, and meets the following military specifications:
MIL-E-5400N
MIL-E-16400
MIL-I-461A
MIL-E-4158
MIL-STD-704A

Class 2X
Classes 3 and 4
Notice 3

The two card assemblies are two-sided printed circuit cards with discrete components mounted on a
bar type heat sink similar to the logic cards. Thermal conduction is achieved through spring clips to
primary structure which is attached to the cold
plates. Electrical connections are made through 30
and 90-pin fork and blade type connectors.

Category B

Processor Unit

The processor unit ATR case includes the central
processing unit (CPU), input/output unit (IOU),
and associated power supply. Twenty logic card
connectors are provided. The CPU uses 11 printed
circuit cards, the IOU uses 3 cards, and 6 card slots
are provided as spares for expansion. Each card is
6 inches x 7 inches and contains a mix of SSI and
MSI components up to a maximum of 80 microcircuits. A single wire-wrap plate is used to interconnect the cards with 180-pin fork and b lade connectors used to connect the cards to the plate. Functional partitioning and byte slicing maximize fault
isolation techniques.

Sense circui try has been added to protect the
power supply and to automatically shut down
power under the following conditions:
a.
b.
c.
d.
e.

Overv olt age
Overcurrent
Overtemperature
Loss of phase
Over/under voltage input

Automatic restart will occur under the following
condi tions:

The temperature decreases to the operating
level.

The input voltage reaches the level required
by specification.

Heat is removed from the power supply via the
thermal conduction from the main chassis to the
cold plates. The power supply provides a single
132-pin output connector which contains both
the output voltages and test points internal to the
power supply. The test points were selected to
providecompatibiiity with VAST testing requirements. In addition, the power supply provides a
fault signal to the memory to indicate a power
supply malfunction; it also contains the same
startup, shutdown, and protective circuitry features as the processor power suppiy.

Fuses have been added within the power supply to
protect the unit from an internal short-circuit
condition.
Memory Unit

The memory unit ATR case contains six types of
17 printed circuit cards, a 16K core stack, and
the memory power supply. The circuit cards are
4 inches x 7 inches and are interconnected by a
single wire-wrap plate with fork and blade connectors used to connect the cards to the plate. The
16K by 36-bit core stack is a single plug-in unit,
and contains in tegral sense am plifier circuits. Four
rails on the corners of the core stack provide physical support and location fixing. In addition, the
rails provide thermal conductive cooling paths for
conducting heat to the cold wall side plates. The
core stack uses 14 mil cores, selected for optimum
performance and reliability.

System Control Panel

The system control panel (SCP) for the L-304H,
shown in Figure 9-3, is a self-contained subunit
which can be mounted on the front of the processor case or located remotely.
The panel indicators and switches are grouped as
follows:

The 16K memory power supply provides regulated
direct current voltages to the 16K core memory
unit. The power supply accepts 3-phase, 115-vac,
400-Hz power input and furnishes the memory
with the following voltages:
+5v ±10 percent
+5v ±5 percent
-5v ±5 percent

+23v ±7 percent
+32v ±10 percent

Data & Base
Select Switches

OVER TEMP: Illuminates when processor
case temperature reaches the warning level;
if temperature increases to the upper limit,
system power is shut down.
PWR FAULT PROC: Illuminates when the
processor power supply fails.

0.5 amp
@

Functional
Switches

RUN: Illuminates when CPU is running.

1.0 amp

Data
Display

INDICATORS

11.5 amps

Indicators

0.5 amp

PWR FAULT MEM: Illuminates when a memory power supply fails.

0.7 amp

IOU MEM TIME OUT: Illuminates on a detected failure for the IOU-memory interface.

+ 12v variable (8.5 to 12 amps) matched to
stack characteristics
The power supply consists of six major assemblies:

IOU TIME OUT: Illuminates on a detected
failure for the IOU-external device interface.

Main Chassis. Contains the high power components and serves as the housing assembly
for the power supply.

CPU MEMORY TIME OUT: Illuminates on a
detected failure for the CPU-memory
interface.

Component Chassis. Contains the output rectifier filters.

PROGRAM TIME OUT: Illuminates on failures such as an internal CPU failure, an illegal
operation code, or a time out of the CPUSPU interface.

Four Circuit Cards. Auxiliary converter, ±5v
regulator, +5v regulator, and logic card.
80

SYSlfMCOIIT'ROl

1.62

1.50

Lll'Il MODUlAR PRQC£SSOR
AND SYSlfM COIIlRO\. CQIISClI

Figure 9-1. L-304H Processor Packaging

~------------~-._

.3TYP-

7.6

3.0

-"'Z

6.5

L·304H 16K X 36 BIT
4 PORT HIGH SPEED CORE MEMORY

Figure 9-2. L-304H Memory Packaging

FUNCTIONAL SWITCHES

POWER: Actuation turns on the processor
power supply.

LAMP TEST: Actuation causes all switch caps
and indicators to illuminate ~Tld forces zeroes
into the data display.

SYS RESET: ~A?Lctuation causes a simulated
power failure and resets the processor and
memory to their initial conditions; release of
the switch simulates restoration of power,
i.e., the processor is forced to program level
76 8 and started.

Switchcap illuminates
PARITY ERROR:
when memory parity error is detected; actu-,
ation of switch resets display.
DATA ENTER: Actuation interrupts the
processor and indicates to the program that
the operator has entered a code into the
DATA SELECT switches.

t::r:':\

\:::/

POWER FAULT
PRO

MEM·

PROG LOAD: Actuation initially causes a
system reset; upon recovery, the CPU remains inactive and the Bootstrap signal is sent
to the IOU.

--,-1

OVER
TEMP

I I

L.J..

-~
TIME OUTS

FAULT
CODE

100

DATA SELECT

"""\

BASE
SEl

ffi~~~~
~~~~~I
L-304H

Figure 9-3. L-304H System Control Panel

DATA DISPLAY: Three-digit decimal LED
readout under program control which provides program communication with operator;
the FAULT CODE indicator calls attention to
the fact that a fault code is present.
DATA SELECT: Three decimal switches used
by operator to insert data into processor; the
switches can be interrogated at any time by
the program, but the DATA ENTER switch
must be actuated to interrupt the running
program.

BASE SEL: Eight position switch by which
the operator designates which of the memories is to serve as the base memory.

In addition to the controls and indicators on the
system control console, each 16K memory has a
prime power on/off switch and indicator, a memory bank address switch, and a power fault
indicator.

Litton

DATA SYSTEMS

NT S

PUlER

AN/USQ~20
Right SHift. Q ............... Shift (0) Right by Y
Right SH itt. A ................ Shift (Al Right by Y
03 Right SHift. AQ ...... ;. .......... Shift (AO) Right by Y,
04* COMpare • A,ea, ~ AQ • ........ Sense Oh (Ali =(A)f
05 Left SH ift • Q _ "._ ................ Shift (Q) Left by Y
06 Left SH ift • A ................... Shift (Al Left by Y
07 Left SHift. AQ ................... Shift (AO) Left by Y
10 ENTer. Q .. Y. k=OtQ'~Q
15
SToRe It A .......................... {A),......,.,. Y. k =4, A'-fJoA
16 SToRe. an ............ ' ............. (B)l~ Y
ri"!'I. SToRe'. cf! .......... 8 '. . . . . . . . ! • (Clj-.... y
20 ADD 0 A ... '" .................... (A) + Y .....;~ A
21 SUBtract 41 A ........ it ............ (A) - Y --l'/J:- A
22 MUltiply ............................. {Ql Y -fJJ- AQ
23* DIVide ............................ (AO) / Y -+- Q. R -(l:!.Af
24 RePlace 1& A +Y ......... " ..... (A) +(Y) ~ ya A
25 RePlace 41 A -Yo ••••••••• (A) -(Y)~ ya A
26* ADD • Q . . . . . . . . . . . . . . . . . . {Q}+- Y ...... O.(A)i=(A)flj interpretation
27'* 5U a tract • Q • • .. • • .. • • • • .. (a) - Y ..:...flo. Q, (A) i :: (A)f reversed for AS Q
30 ENTer 0 y + Q 0 C • • • • • .. • • • y +(0) -fit- A
31 ENTer ~ y .... Q ............ Y-(Q)-I>·A
32 SToRe t
k=I, (Y)L-'(oOIOO+nLj
k =0, Y ~(OOIOO+nl.

mono inter, at 00040+j

76'" OUiputeC'Cwith-MoNrron mode). Buffer OUT on CJ with mono
.

k=3,{Y) ....{00120+j);

k:o It (Y)L -!J.!.{OOI20 + j)l'
k :;0, Y -in--{OOI2o+1\.
mono inter. at 00060 + j

...... NO - OPeration •
- Com Premont A or. Q .............. _}
It

•

.......

L(A)(Q) -fta> Yi (Ali:: (A}f
SET (A\, FOR Yni:l
COM PLEM ENT (Al n FOR Y n =I
CLEAR (Aln FOR Y n =1
SU** • • • • • ... Y n ..... (A}n FOR {O}n:ttl

*""l.P'" L.o(jica I Product

.....,. Clear-A,·O,D an,ot Y...... •• ..........

SToRe \I L.P •• '.• : •••••••
50 S£Lective • SET •• ;......
!Sl SElective • CP*'" • • • • .. ••
5, SElective .. CL** ........

53 SELective

..........

RePlace • A -LP•••••••••

54 fteplace. SElective • SET.. • .. • • SET (Aln FOR ('()n ::I I r -II> Y a A
55 Replace SElective •. CPo ....... COMPLEMENT (A)nFOR (Y)n=l,-+-V SA
56 Replace SElective • Ct........... CLEAR (Aln FOR (Y)n zit ~ Y A
51 Replace SElective • SUo ... : ... (Y)n ~(A>n FOR ('Q)n =Ilt -f>Y
60 Jum P (arithmetic 1 •••••••• }Jum p to Y if j -c?ndIt iO.n is satisfied.
61 Jum P {manua I} ... " • • • • • •• (see JP
RJP. J - Designators)
Jump to Vif Ctinput }
62"'" JumP {Ifoen has ACTIVE
IN put buffer) .......... buffer active....
{see JP
RJ P
A
63 Ju~P (If 1& en has ACTIVE
Jump to Y if Ci output
j - Designators)
OUTput buffer) ........ buffer active
64 Return JumP (arithmetic) •• ~ • }Jum p. to Y+I and P+I ~YL if j condition is
65 Return JumP (manual). ••••. ; satisfied (see JP a. RJP 1 - Designators)
66..... TERMinate e en" !NPUT•••••• Terminate input buffer on chClnnel j
6~ TERMinate •
OUTPUT •••• Terminate output buffer on channel j
70* RePeaT................... Ex~cute N I Y times
"
71' BSKip 0- an•••.••...••••• (Sll =Y) skip NI and clear {S)ll {B)l ~ Y,
Advance si and read N I
7~ 8JumP" a~ •.•.•.••..•.• (Bli =0, read NI i (B)j ¢: 0, (S)j-L and
.
. .
jump to address Y

CS-I Mono-codes

Remove Interrupt Lockout . . . . . . . . . . . . .
Remove Interrupt L.ockout and JumP.Y .. .

..... TeSt-CO or-CI ....................... .

tL. -Cleor

'!} ~5peciol

Designators <.see opponite

~ldQ of card)

Y - The operand, Y or (y)

NTDS UNIT

PUTER

AN/USQ·20

NORMAL

k-DESIGNATORS

j .. DESIG.
r----"

(Not applicable on
or A)
Skip Cod.

(nolklp)

:3
4

s"
t-----

Code

OriQin

Code

Dest.

Cc1de

'blank'

'not uled'

U
W

MiJ

L
U
VI
X

XUl
.XML

XMu

SKIP
Q POS
Q NEG
A ZERO
A NOT Zero
A POS

A NEG

(4 bits)

REPLACE

STORE

READ

~
J-DE SIGNATORS

L
U
'II
'notuMd'

A
CPL . Cpl ML
LX
CPU Cpl Mu UX
CPW Cpl M not UMd'
A

OrlQin

D~sf,

Ml
Mu

XMu

A-A· re~ister

Mu- Upper half memory word
X •• Sign bit extended

o - O-reQister

JP &
j

JP
60

RJP

( No Jump)·

(Uncond. Jume)*

2
3
4
5
6
7

==?:
-':'

KEY I
KEY 2
KEY "3
STOP
STOP 5
STOP 6

P~S

Q NEG

A ZERO
A NOT Zero

A POS

Wncond. Jump 1

A NEG
---_.-

STOP 1

63, _ _

*60 eleorsi.nt~rrupt

ACTIVE OUT

bootstrop modes..

-2412~-

leli

7 -

20}19

::iJ

15 114 -

(2 bits)
EX- FCT
13

,
,

STRoC"

not used'

,
I

not used'

IN ed'tOUT.Cn

JP
62 63
, blank'

not used'

nof used'

73 75 74 76
I

L
U

not used'

'II

blank'

not used'

U~reQister

U-

* j -DESIGNATORS
04

(no skip)

t
2

(uncond itional skip)

:3
4
~

6
7

SKIP

Y LESS : y s to)
Y MORE: Y > (0)
:(Q)~ Y and Y >(A)
Y IN
:(Q)
< Y or Y :s (A 1
Y OUT
Y LESS : Y s (A)
Y MORE: Y > (A)

./ 0 6 Increm4lnt If HI is

HE -

Next execution

ADO-Q ,SU aeQ

DIV

COM - A • • Qt. A Q

'=;-~---~

62 j
ACTIVE IN

"-""

RJP

§":-

-DESIGNATORS

[

Cpl- Complement

ML- Low t!' half memory word

and represents Cn where n may be 0 -15

k-DESIGNATORS

XML

pO~ltions

The Instruction word assumes the formot:

LEGEND
M - Memory word (30 bits 1

<\ bit

OCCUPIt:S

RPL

NO Over Flow
Over r:low

A ZERO
A NOT Zero

A POS
A NEG
..

eloS!}

ENTeLP t RPLe LP

( no skip)

(no skip)

SKIP
A POS

SKIP

A NEG
Q ZERO
Q t40T Zero
Q POS
Q

NEG

RPT

EVEN parity

,-------1

{no mOd.lJV 0 f NE r:Y
0 ~~E s'(i-l
AOV
1.BACK
1'( 0 fNE"Y-1

:y
:y'

000 pOrlty
A ZERO
A NOT Zero

Rpl. Inc. : Yo
-'-._---_.
AOVR

A POS

BACK R : Yo

A NEG

ADD B R

ADO B

:'(0

Increments '( addrcu for the store portion of the replace.

fy-

NE "y .. Bb

Table IV -6.

Index of Instructions by Function Code

, PAGE

MNEMONIC
CODE

FUNCTION
CODE

l'i

NUMoER
IN TEXT

:r--;,fRUCfIO"-l

MtT

2-54

EXE

2-5C

EXECUTE '

EXC

2-1-

EXCHA.NGE

EXD

2-17

EXCHANGE DOUBLE

LOR

2-12

LOAD ill-!

03
(}.l

rlAU

STR

2-12

LDD

2-]3

)rD

2-13

AJD

2-18

ADD

SUB

2-19

SUBTRACT

RAO

2-19

REPLACE ADD

RU8

2-19

~EPLACE

AOA

2-2C

AOD ABSOLUTE

S8A

2-20

SUfi'" ... .:! ASSOLUTE

LDA

2-14

LOAD A8S0LUTE

lDC

2-14

LOAD COMPLEMENT

EOR

2-22

EXCLUSUE OR

lOR

2-23

INCLUSIVE OR

AND

2-23

LOGICAL AND

MBD

2-51

MEMORY SANK DESIGNATOR

REI!

2-24

REPLACE EXCLUSive OR

Rill

2-25

REPLACE INClUSIVE OR

/IAN

2-26

REPLACE lOGICAL AND

MBA

2-51

MEMORY BANK ASSIGNMENT

MPY

2-21

MULTIPLY

DIV

2-21

DIVIDE

DTX

2-31

DECREMeNT RH BY 2,
TRANSFER IF RH .. 0

32
If" l)

ITX

2-32

TRANSFER AND INCitEMENT
RH &Y 2

cox

2-32

DECREMENT RH BY I,
TRANSFER IF lIH ,. 0

lOX

2-33

-l

FUN(7jON
(::.,o~

I
4!

MNEMONIC
CODE

I
I

PAGE
NUMBER
IN TEXT

INSTRUCTION

XEZ

2-34

TRANSFER IF RH = 0

XNZ

2-35

TRANSFER If RH .. 0

t"\ -i

XNG

2-35

TRANSFER IF lIH IS NEGATIVE

t-', -; :... .

l-.____.~~3~ ~
__

t~-2--~----r_-T-RA-N-'--F-E-Il-'f--RH--1s__~__SI_Tl_V_E__~

____
X_ps_____

2-7:7

SHIFT LONG LEFT

Nll

2-28

NORMAL! ZE lONG LEFT

SNC

2-30

SHIFT AND COUNT

11FT

2-30

REFLECT

CJl

2-36

COMPARE, JUMP IF lESS

Sll

STORE DOuSlE
I

L____

5_1____+-___C_J_E____+-_2_-_3_7__

i i
53

~I--CO\~ARE.JU~iFfQUAL

CJU

2-37

COMPARE, JUMP IF UNEQUAL

CJG

2-38

COMPARE, JUMP IF GREATER

~'----'----_+----------+_------+_----------------------_1

2-38

Gel

GATED COMPARISON,
JUMP IF INSIDf

GeO

~-'

2-38

GATED COM~AJUSON.
JUMP IF OUTSIDE

2-~

SHIFT LONG RIGHT

2-19

SHIFT AlGEBU.lCAll Y RIGHT

SlR
57

60
(Oi! 01)

SET

2-52

SET alT

152

Cll!

2-53

CLEAR alT

SKZ

2-39

SKIP IF 81T IS ZERO

SKN

2-40

SKIP IF alT IS ONE

MVZ

2-16

MOve AND ZEitO

MVI

2-14

MOVE AND INS9T

STZ

2-~

STORE All Zf~OS

(Ol! 63;

(OR 65;

•

(OR 67)0

t-,";

TRANSFER AND INCREMENT
IIrl BY 1

(E " 1)

J.I

XFR

2-33

TRANSfER UNCONDITIONAL

xu:

2-33

TRANSFER UNCONDITIONAL
AND STORE LINK

)(SW

JTW

.. , _

!--------~---------+------~------------------~~

LOAD DOUBLE

SUaTRAG

-----~~~.'~\--~----------~--~---~-----------------------4

STORE RH

DEV

SPECIAL D£V1Cf COMMAND

TRANSFE~

2-3.4

ON CONSOLE
TRANSFER SWITCH

OFR

2-36

JUMP THREE-WAY

NO?

2--45

INPUT TO REGISTeR

2-45

OUTPUT fROM REGISTER

2-49

NO OPERATION

2502-8

·INDICATES DUAL FUNCT!ON CODE fOR IDENTICAL INSUUCTIOr-.,

4-30

\" ,-

Table IV-5.

L-304F Instruction Index
TRANSFER IN.STRUCTIONS

ARITHMETIC INSTRUCTIONS
FUNCTION
CODE

INSTRUCTION

MNEMONIC
CODE

PAGE
NUMBER

2-20

ADA

ADD

2-J8

OI'I.D1:

DIV

MUlTlPl Y

MPY

REPlACE ADD

RAO

REPLACE suarRACT

RUB

\LJBTRACT

S8A

2-21
2-21
2-19
2-19
2-20

SUB

2-19

A.8~OlUH

ADD
f--

.. uaTRACT

MNEMONIC
CODE
EXC

EXCHANGE

,XO

2-17
2-17

l.OA

2-14

lDC

LOAD
II AaSOLUTE .....- ~

r- ----

--'

LOAD COMPLEMENT

LOAD DOUBLE

lDD

2-14
2-13
2-~M

2-14
2-16
2-13
2-12

LOAD RH
-.-------..

LOR

MOVE AND !N)E!!T

MVI

MOVE A.ND ZERO

MVZ

STOilE DOUBLE

STD

ST()llE RH

S II!

f---- .

2-34

TRANSFER
"UNCONOIT 10NA l

XfR

2-33

TRANSFER
UNCONDITIONAL
AND STORE LINK

xu::

2-33

TRANSFER IF RH
IS NEGATIVE

XNG

2-35

XNZ

2-35

TRANSFER If RH "
IS POSITIvE
'

XI'S

2-35

TRANSfER ON
CONSOLE TRANSFER
SWITCH

xsw

2-3-4

MNEMONIC
CODE

PAGE
NUMBU

2-:11

COMPARE, JUMP
IF leSS

CJL

2-30

2-26

COMPARE, JUMP
If UNEQUAL

CJU

2-37

RE~

2-24

GCI

2-:?s

RIR

2-25

GATtD COMPAalSON, JUMP If
INSIDE
GATED COMPAIl!SON, JUMP If
OUTSIDE

GCO

2-38

JUMP THREE WAY

JTW

2-36

bO
lei 67}

SKN

2--40

SKZ

-2-39

fOR
lOR

2-23

RAN

24
25

NUMBER

2-23
2-22

LOGICAL AND
O~

INCLUSIVE OR

SHIFT INSTRUCTIONS
PAGE

FUNCTION
CODe

MNEMONIC
CODE

NUMBER

NLl

2-28

SHIfT AlGfBRAICAll Y RIGHT

SAR

2-29

SHIfT lONG lEFT

SLl

SHIFT lONG RIGHT
Sr',fT AND COUNT

SlR

SNC

HFLECT

P.fT

2-'0
2-29
2-30
2-30

Sit:; IP If alT IS
ONI:
SKIP IF II!T IS

zuo

fUNCTION
CODE

MNEMONIC
CODE

SPecIAL DEVICE
COMMAND

Of V

INI'UT fO
RfGIS Tf~

IT II

_._-

0.-

10165)

*
*

MISCELLANEOUS INSTRUCTIONS
INSTRUCTION
CLEAR alT

INPUT /OUTPUT INSTRUCTIONS

FUNCTION
COOf

CJG

OUTPU';' FROM
REGiS TEll

XEZ

-.---

COMPARE, JUMP
If GREATER

1:"eLUSIVE OR
f-----.

INSTIluCrlON

2-32

2-37

EXCLUS IVE OR

NORMALIZE
LON(; LEfT

ITX

CJE

AND

INSTRUCTION

32
IE.: I}

~EPLACE

2-33

COMPARE, JUMi'
IF EQUAL

LOGICAL AND

REPLACE
EXCLUSIVE

lOX

33
IE

JUMP INSTRUCTIONS

PAGE

MNEMCNIC
CODE

R~?LACE

2-31

IN:'fI!UCTION

FUNCTiON
CODE

OTX

TRANSFEilIF
RH 10

lOGIC INSTRUCTIONS
!NS TRUCT ION

TRANSFER IF
RH = 0

DOUIILE

1---

2-32

TRANSFER AND
INCilt:MENT
RH 8Y 2

PAGE

DOX

TRANSFER AND
INCREMENT
RH BY 1

NUMBER

EXCHANGE

3:!

RH/O

DATA TRANSMISSION INSTRUCTIONS
FUNCTION
CODE

NUMBER

DECREMENT RH L\Y
2, TRANSfER IF

INSTRUCTION

MNEMONIC
CODE

DECREMENT RH 8Y
I. TRANSFER IF
RH/o

~.'B~OlUTE
~

PAGE

FUNCTION
CODc

INSTRUCTION

PAGE

NUMBER

2-404

FUNCTION
CODE
62

MNEMONIC
CODf
Clit

2-53

10163)

~~
'\HAlT

-2-50

EXE

HU4

MEMOIY!ANI(
ASSIGNMENT

2-54
2-51

MEMOIfY BANK
DESIGNATOR

Mao

2-51

NO OPERA TION

NOP

2--49

2-.45

SET BIT

SET

2-52

2-45

S rO~f ALL ZEROS

STZ

2-54

1Of/ 61)

Ofll

PAGE
NUMBER

4-29

Source Exif Data:
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