MSP430FR4xx And MSP430FR2xx Family (Rev. D) User Guide

User Manual:

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Table of Contents
Preface
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
- 1.1 System Control Module (SYS) Introduction
- 1.2 System Reset and Initialization
  - 1.2.1 Device Initial Conditions After System Reset
- 1.3 Interrupts
- 1.4 Operating Modes
- 1.5 Principles for Low-Power Applications
- 1.6 Connection of Unused Pins
- 1.7 Reset Pin (RST/NMI) Configuration
- 1.8 Configuring JTAG Pins
- 1.9 Memory Map – Uses and Abilities
- 1.10 JTAG Mailbox (JMB) System
- 1.11 Device Security
  - 1.11.1 JTAG and SBW Lock Mechanism (Electronic Fuse)
  - 1.11.2 BSL Security Mechanism
- 1.12 Device-Specific Configurations
  - 1.12.1 MSP430FR413x and MSP430FR203x Configurations
  - 1.12.2 MSP430FR2433 Configurations
- 1.13 Device Descriptor Table
- 1.14 SFR Registers
- 1.15 SYS Registers
- 1.16 System Configuration Registers
2 Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
- 2.1 Power Management Module (PMM) Introduction
- 2.2 PMM Operation
- 2.3 PMM Registers
3 Clock System (CS)
- 3.1 CS Introduction
- 3.2 CS Operation
- 3.3 CS Registers
4 CPUX
- 4.1 MSP430X CPU (CPUX) Introduction
- 4.2 Interrupts
- 4.3 CPU Registers
- 4.4 Addressing Modes
- 4.5 MSP430 and MSP430X Instructions
  - 4.5.1 MSP430 Instructions
  - 4.5.2 MSP430X Extended Instructions
- 4.6 Instruction Set Description
5 FRAM Controller (FRCTL)
- 5.1 FRAM Introduction
- 5.2 FRAM Organization
- 5.3 FRCTL Module Operation
- 5.4 Programming FRAM Devices
- 5.5 Wait State Control
  - 5.5.1 Wait State and Cache Hit
- 5.6 FRAM ECC
- 5.7 FRAM Write Back
- 5.8 FRAM Power Control
- 5.9 FRAM Cache
- 5.10 FRCTL Registers
6 Backup Memory (BKMEM)
- 6.1 Backup Memory Introduction
- 6.2 BKMEM Registers
7 Digital I/O
- 7.1 Digital I/O Introduction
- 7.2 Digital I/O Operation
- 7.3 I/O Configuration
- 7.4 Digital I/O Registers
8 Capacitive Touch I/O
- 8.1 Capacitive Touch I/O Introduction
- 8.2 Capacitive Touch I/O Operation
- 8.3 CapTouch Registers
  - 8.3.1 CAPTIOxCTL Register (offset = 0Eh) [reset = 0000h]
9 CapTIvate Module
- 9.1 CapTIvate Introduction
- 9.2 CapTIvate Overview
- 9.3 CapTIvate Registers
10 CRC Module
- 10.1 Cyclic Redundancy Check (CRC) Module Introduction
- 10.2 CRC Standard and Bit Order
- 10.3 CRC Checksum Generation
  - 10.3.1 CRC Implementation
  - 10.3.2 Assembler Examples
- 10.4 CRC Registers
11 Watchdog Timer (WDT_A)
- 11.1 WDT_A Introduction
- 11.2 WDT_A Operation
- 11.3 WDT_A Registers
  - 11.3.1 WDTCTL Register
12 Timer_A
- 12.1 Timer_A Introduction
- 12.2 Timer_A Operation
- 12.3 Timer_A Registers
13 Real-Time Clock (RTC) Counter
- 13.1 RTC Counter Introduction
- 13.2 RTC Counter Operation
- 13.3 RTC Counter Registers
14 32-Bit Hardware Multiplier (MPY32)
- 14.1 32-Bit Hardware Multiplier (MPY32) Introduction
- 14.2 MPY32 Operation
- 14.3 MPY32 Registers
  - 14.3.1 MPY32CTL0 Register
15 LCD_E Controller
- 15.1 LCD_E Introduction
- 15.2 LCD_E Operation
- 15.3 LCD_E Registers
16 ADC Module
- 16.1 ADC Introduction
- 16.2 ADC Operation
- 16.3 ADC Registers
17 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode
- 17.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview
- 17.2 eUSCI_A Introduction – UART Mode
- 17.3 eUSCI_A Operation – UART Mode
- 17.4 eUSCI_A UART Registers
18 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode
- 18.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview
- 18.2 eUSCI Introduction – SPI Mode
- 18.3 eUSCI Operation – SPI Mode
- 18.4 eUSCI_A SPI Registers
- 18.5 eUSCI_B SPI Registers
19 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode
- 19.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview
- 19.2 eUSCI_B Introduction – I2C Mode
- 19.3 eUSCI_B Operation – I2C Mode
- 19.4 eUSCI_B I2C Registers
20 Embedded Emulation Module (EEM)
- 20.1 Embedded Emulation Module (EEM) Introduction
- 20.2 EEM Building Blocks
- 20.3 EEM Configurations
Revision History
Important Notice

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