MSP430FR4xx And MSP430FR2xx Family User's Guide (Rev. H) Users
Users_guide
User's%20Guide%20-%20slau445h
User Manual:
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- Table of Contents
- Preface
- 1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)
- 1.1 System Control Module (SYS) Introduction
- 1.2 System Reset and Initialization
- 1.3 Interrupts
- 1.4 Operating Modes
- 1.5 Principles for Low-Power Applications
- 1.6 Connection of Unused Pins
- 1.7 Reset Pin (RST/NMI) Configuration
- 1.8 Configuring JTAG Pins
- 1.9 Memory Map – Uses and Abilities
- 1.10 JTAG Mailbox (JMB) System
- 1.11 Device Security
- 1.12 Device-Specific Configurations
- 1.13 Device Descriptor Table
- 1.14 SFR Registers
- 1.15 SYS Registers
- 1.15.1 SYSCTL Register (offset = 00h) [reset = 0000h]
- 1.15.2 SYSBSLC Register (offset = 02h) [reset = 0000h]
- 1.15.3 SYSJMBC Register (offset = 06h) [reset = 000Ch]
- 1.15.4 SYSJMBI0 Register (offset = 08h) [reset = 0000h]
- 1.15.5 SYSJMBI1 Register (offset = 0Ah) [reset = 0000h]
- 1.15.6 SYSJMBO0 Register (offset = 0Ch) [reset = 0000h]
- 1.15.7 SYSJMBO1 Register (offset = 0Eh) [reset = 0000h]
- 1.15.8 SYSUNIV Register (offset = 1Ah) [reset = 0000h]
- 1.15.9 SYSSNIV Register (offset = 1Ch) [reset = 0000h]
- 1.15.10 SYSRSTIV Register (offset = 1Eh) [reset = 0002h]
- 1.16 System Configuration Registers
- 1.16.1 Smart Analog Combo Subfamily System Configuration Registers
- 1.16.1.1 Smart Analog Combo Subfamily SYSCFG0 Register (offset = 00h) [reset = 9601h]
- 1.16.1.2 Smart Analog Combo Subfamily SYSCFG1 Register (offset = 02h) [reset = 0000h]
- 1.16.1.3 Smart Analog Combo Subfamily SYSCFG2 Register (offset = 04h) [reset = 0000h]
- 1.16.1.4 Smart Analog Combo Subfamily SYSCFG3 Register (offset = 06h) [reset = 0000h]
- 1.16.2 System Configuration Registers for Devices Without Smart Analog Combo (SAC)
- 1.16.2.1 Devices Without Smart Analog Combo SYSCFG0 Register (offset = 00h) [reset = 9603h]
- 1.16.2.2 Devices Without Smart Analog Combo SYSCFG1 Register (offset = 02h) [reset = 0000h]
- 1.16.2.3 Devices Without Smart Analog Combo SYSCFG2 Register (offset = 04h) [reset = 0000h]
- 1.16.2.4 Devices Without Smart Analog Combo SYSCFG3 Register (offset = 06h) [reset = 0000h]
- 1.16.1 Smart Analog Combo Subfamily System Configuration Registers
- 2 Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
- 2.1 Power Management Module (PMM) Introduction
- 2.2 PMM Operation
- 2.2.1 VCORE and the Regulator
- 2.2.2 Supply Voltage Supervisor
- 2.2.3 Supply Voltage Supervisor During Power-Up
- 2.2.4 LPM3.5 and LPM4.5 (LPMx.5)
- 2.2.5 Low-Power Reset
- 2.2.6 Brownout Reset (BOR)
- 2.2.7 LPM3.5 Switch
- 2.2.8 Shared Reference Generation and Distribution
- 2.2.9 Temperature Sensor
- 2.2.10 RST/NMI
- 2.2.11 PMM Interrupts
- 2.2.12 Port I/O Control
- 2.3 PMM Registers
- 2.3.1 PMMCTL0 Register (offset = 00h) [reset = 9640h]
- 2.3.2 PMMCTL1 Register (offset = 02h) [reset = 0000h]
- 2.3.3 PMMCTL2 Register (offset = 04h) [reset = 0000h]
- 2.3.4 PMMIE Register (offset = 0Eh) [reset = 0000h] (External)
- 2.3.5 PMMIFG Register (offset = 0Ah) [reset = 0000h] (External)
- 2.3.6 PM5CTL0 Register (offset = 10h) [reset = 0011h]
- 3 Clock System (CS)
- 3.1 CS Introduction
- 3.2 CS Operation
- 3.2.1 CS Module Features for Low-Power Applications
- 3.2.2 Internal Very Low-Power Low-Frequency Oscillator (VLO)
- 3.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO)
- 3.2.4 XT1 Oscillator
- 3.2.5 Digitally Controlled Oscillator (DCO)
- 3.2.6 Frequency Locked Loop (FLL)
- 3.2.7 DCO Modulator
- 3.2.8 Disabling FLL Hardware and Modulator
- 3.2.9 FLL Unlock Detection
- 3.2.10 FLL Operation From Low-Power Modes
- 3.2.11 DCO Factory Trim and Software Trim
- 3.2.12 Operation From Low-Power Modes, Requested by Peripheral Modules
- 3.2.13 Fail-Safe Operation
- 3.2.14 Synchronization of Clock Signals
- 3.2.15 Module Oscillator (MODOSC)
- 3.3 CS Registers
- 4 CPUX
- 4.1 MSP430X CPU (CPUX) Introduction
- 4.2 Interrupts
- 4.3 CPU Registers
- 4.4 Addressing Modes
- 4.5 MSP430 and MSP430X Instructions
- 4.5.1 MSP430 Instructions
- 4.5.2 MSP430X Extended Instructions
- 4.6 Instruction Set Description
- 4.6.1 Extended Instruction Binary Descriptions
- 4.6.2 MSP430 Instructions
- 4.6.2.1 ADC
- 4.6.2.2 ADD
- 4.6.2.3 ADDC
- 4.6.2.4 AND
- 4.6.2.5 BIC
- 4.6.2.6 BIS
- 4.6.2.7 BIT
- 4.6.2.8 BR, BRANCH
- 4.6.2.9 CALL
- 4.6.2.10 CLR
- 4.6.2.11 CLRC
- 4.6.2.12 CLRN
- 4.6.2.13 CLRZ
- 4.6.2.14 CMP
- 4.6.2.15 DADC
- 4.6.2.16 DADD
- 4.6.2.17 DEC
- 4.6.2.18 DECD
- 4.6.2.19 DINT
- 4.6.2.20 EINT
- 4.6.2.21 INC
- 4.6.2.22 INCD
- 4.6.2.23 INV
- 4.6.2.24 JC, JHS
- 4.6.2.25 JEQ, JZ
- 4.6.2.26 JGE
- 4.6.2.27 JL
- 4.6.2.28 JMP
- 4.6.2.29 JN
- 4.6.2.30 JNC, JLO
- 4.6.2.31 JNZ, JNE
- 4.6.2.32 MOV
- 4.6.2.33 NOP
- 4.6.2.34 POP
- 4.6.2.35 PUSH
- 4.6.2.36 RET
- 4.6.2.37 RETI
- 4.6.2.38 RLA
- 4.6.2.39 RLC
- 4.6.2.40 RRA
- 4.6.2.41 RRC
- 4.6.2.42 SBC
- 4.6.2.43 SETC
- 4.6.2.44 SETN
- 4.6.2.45 SETZ
- 4.6.2.46 SUB
- 4.6.2.47 SUBC
- 4.6.2.48 SWPB
- 4.6.2.49 SXT
- 4.6.2.50 TST
- 4.6.2.51 XOR
- 4.6.3 Extended Instructions
- 4.6.3.1 ADCX
- 4.6.3.2 ADDX
- 4.6.3.3 ADDCX
- 4.6.3.4 ANDX
- 4.6.3.5 BICX
- 4.6.3.6 BISX
- 4.6.3.7 BITX
- 4.6.3.8 CLRX
- 4.6.3.9 CMPX
- 4.6.3.10 DADCX
- 4.6.3.11 DADDX
- 4.6.3.12 DECX
- 4.6.3.13 DECDX
- 4.6.3.14 INCX
- 4.6.3.15 INCDX
- 4.6.3.16 INVX
- 4.6.3.17 MOVX
- 4.6.3.18 POPM
- 4.6.3.19 PUSHM
- 4.6.3.20 POPX
- 4.6.3.21 PUSHX
- 4.6.3.22 RLAM
- 4.6.3.23 RLAX
- 4.6.3.24 RLCX
- 4.6.3.25 RRAM
- 4.6.3.26 RRAX
- 4.6.3.27 RRCM
- 4.6.3.28 RRCX
- 4.6.3.29 RRUM
- 4.6.3.30 RRUX
- 4.6.3.31 SBCX
- 4.6.3.32 SUBX
- 4.6.3.33 SUBCX
- 4.6.3.34 SWPBX
- 4.6.3.35 SXTX
- 4.6.3.36 TSTX
- 4.6.3.37 XORX
- 4.6.4 Address Instructions
- 5 Interrupt Compare Controller (ICC)
- 5.1 Interrupt Compare Controller (ICC) Introduction
- 5.2 ICC Operation
- 5.3 ICC Registers
- 5.3.1 ICCSC Register (offset = 00h) [reset = 0023h]
- 5.3.2 ICCMVS Register (offset = 02h) [reset = 00FFh]
- 5.3.3 ICCILSR0 Register (offset = 04h) [reset = FFFFh]
- 5.3.4 ICCILSR1 Register (offset = 06h) [reset = FFFFh]
- 5.3.5 ICCILSR2 Register (offset = 08h) [reset = FFFFh]
- 5.3.6 ICCILSR3 Register (offset = 0Ah) [reset = FFFFh]
- 5.3.7 ICCILSR4 Register (offset = 0Ch) [reset = FFFFh]
- 5.3.8 ICCILSR5 Register (offset = 0Eh) [reset = FFFFh]
- 5.3.9 ICCILSR6 Register (offset = 10h) [reset = FFFFh]
- 5.3.10 ICCILSR7 Register (offset = 12h) [reset = FFFFh]
- 6 FRAM Controller (FRCTL)
- 7 Backup Memory (BAKMEM)
- 8 Digital I/O
- 8.1 Digital I/O Introduction
- 8.2 Digital I/O Operation
- 8.3 I/O Configuration
- 8.4 Digital I/O Registers
- 9 Capacitive Touch I/O
- 10 CapTIvate Module
- 11 CRC Module
- 12 Watchdog Timer (WDT_A)
- 13 Timer_A
- 14 Timer_B
- 15 Real-Time Clock (RTC) Counter
- 16 32-Bit Hardware Multiplier (MPY32)
- 16.1 32-Bit Hardware Multiplier (MPY32) Introduction
- 16.2 MPY32 Operation
- 16.3 MPY32 Registers
- 17 LCD_E Controller
- 17.1 LCD_E Introduction
- 17.2 LCD_E Operation
- 17.2.1 LCD Memory
- 17.2.2 Configuration of Port Pin as LCD Output
- 17.2.3 Configuration of LCD Pin as COM or SEG
- 17.2.4 LCD Timing Generation
- 17.2.5 Blanking the LCD
- 17.2.6 LCD Blinking
- 17.2.7 LCD Voltage and Bias Generation
- 17.2.8 LCD Operation Modes
- 17.2.9 LCD Interrupts
- 17.2.10 Static Mode
- 17.2.11 2-Mux Mode
- 17.2.12 3-Mux Mode
- 17.2.13 4-Mux Mode
- 17.2.14 6-Mux Mode
- 17.2.15 8-Mux Mode
- 17.3 LCD_E Registers
- 17.3.1 LCDCTL0 Register
- 17.3.2 LCDCTL1 Register
- 17.3.3 LCDBLKCTL Register
- 17.3.4 LCDMEMCTL Register
- 17.3.5 LCDVCTL Register
- 17.3.6 LCDPCTL0 Register
- 17.3.7 LCDPCTL1 Register
- 17.3.8 LCDPCTL2 Register
- 17.3.9 LCDPCTL3 Register
- 17.3.10 LCDCSSEL0 Register
- 17.3.11 LCDCSSEL1 Register
- 17.3.12 LCDCSSEL2 Register
- 17.3.13 LCDCSSEL3 Register
- 17.3.14 LCDM[index] Register – Static, 2-Mux, 3-Mux, 4-Mux Mode
- 17.3.15 LCDM[index] Register – 5-Mux, 6-Mux, 7-Mux, 8-Mux Mode
- 17.3.16 LCDIV Register
- 18 Enhanced Comparator (eCOMP)
- 18.1 eCOMP Introduction
- 18.2 eCOMP Operation
- 18.3 eCOMP Interrupts
- 18.4 eCOMP Registers
- 18.4.1 CPxCTL0 Register (offset = 00h) [reset = 0100h]
- 18.4.2 CPxCTL1 Register (offset = 02h) [reset = 0000h]
- 18.4.3 CPxINT Register (offset = 06h) [reset = 0000h]
- 18.4.4 CPxIV Register (offset = 08h) [reset = 0000h]
- 18.4.5 CPxDACCTL Register (offset = 10h) [reset = 0002h]
- 18.4.6 CPxDACDATA Register (offset = 12h) [reset = 0100h]
- 19 Transimpedance Amplifier (TIA)
- 20 Smart Analog Combo (SAC)
- 20.1 SAC Introduction
- 20.2 SAC Operation
- 20.3 SAC Configuration
- 20.4 SAC Registers
- 20.4.1 SACxOA Register (offset = 00h) [reset = 0000h]
- 20.4.2 SACxPGA Register (offset = 02h) [reset = 0001h]
- 20.4.3 SACxDAC Register (offset = 04h) [reset = 0000h]
- 20.4.4 SACxDAT Register (offset = 06h) [reset = 0000h]
- 20.4.5 SACxDACSTS Register (offset = 08h) [reset = 0000h]
- 20.4.6 SACxIV Register (offset = 0Ah) [reset = 0000h]
- 21 ADC Module
- 21.1 ADC Introduction
- 21.2 ADC Operation
- 21.2.1 ADC Core
- 21.2.2 ADC Inputs and Multiplexer
- 21.2.3 Voltage Reference Generator
- 21.2.4 Automatic Power Down
- 21.2.5 Sample and Conversion Timing
- 21.2.6 Conversion Result
- 21.2.7 ADC Conversion Modes
- 21.2.7.1 Single-Channel Single-Conversion Mode
- 21.2.7.2 Sequence-of-Channels Mode
- 21.2.7.3 Repeat-Single-Channel Mode
- 21.2.7.4 Repeat-Sequence-of-Channels Mode
- 21.2.7.5 Using the Multiple Sample and Convert (ADCMSC) Bit
- 21.2.7.6 Stopping Conversions
- 21.2.7.7 Window Comparator
- 21.2.7.8 Using the Integrated Temperature Sensor
- 21.2.7.9 ADC Grounding and Noise Considerations
- 21.2.7.10 ADC Interrupts
- 21.3 ADC Registers
- 21.3.1 ADCCTL0 Register
- 21.3.2 ADCCTL1 Register
- 21.3.3 ADCCTL2 Register
- 21.3.4 ADCMEM0 Register
- 21.3.5 ADCMEM0 Register, 2s-Complement Format
- 21.3.6 ADCMCTL0 Register
- 21.3.7 ADCHI Register
- 21.3.8 ADCHI Register, 2s-Complement Format
- 21.3.9 ADCLO Register
- 21.3.10 ADCLO Register, 2s-Complement Format
- 21.3.11 ADCIE Register
- 21.3.12 ADCIFG Register
- 21.3.13 ADCIV Register
- 21.3.14 MSP430FR413x SYSCFG2 Register (absolute address = 0164h) [reset = 0000h]
- 22 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode
- 22.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview
- 22.2 eUSCI_A Introduction – UART Mode
- 22.3 eUSCI_A Operation – UART Mode
- 22.3.1 eUSCI_A Initialization and Reset
- 22.3.2 Character Format
- 22.3.3 Asynchronous Communication Format
- 22.3.4 Automatic Baud-Rate Detection
- 22.3.5 IrDA Encoding and Decoding
- 22.3.6 Automatic Error Detection
- 22.3.7 eUSCI_A Receive Enable
- 22.3.8 eUSCI_A Transmit Enable
- 22.3.9 UART Baud-Rate Generation
- 22.3.10 Setting a Baud Rate
- 22.3.11 Transmit Bit Timing - Error calculation
- 22.3.12 Receive Bit Timing – Error Calculation
- 22.3.13 Typical Baud Rates and Errors
- 22.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes
- 22.3.15 eUSCI_A Interrupts
- 22.4 eUSCI_A UART Registers
- 23 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode
- 23.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview
- 23.2 eUSCI Introduction – SPI Mode
- 23.3 eUSCI Operation – SPI Mode
- 23.4 eUSCI_A SPI Registers
- 23.5 eUSCI_B SPI Registers
- 24 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode
- 24.1 Enhanced Universal Serial Communication Interface B (eUSCI_B) Overview
- 24.2 eUSCI_B Introduction – I2C Mode
- 24.3 eUSCI_B Operation – I2C Mode
- 24.3.1 eUSCI_B Initialization and Reset
- 24.3.2 I2C Serial Data
- 24.3.3 I2C Addressing Modes
- 24.3.4 I2C Quick Setup
- 24.3.5 I2C Module Operating Modes
- 24.3.6 Glitch Filtering
- 24.3.7 I2C Clock Generation and Synchronization
- 24.3.8 Byte Counter
- 24.3.9 Multiple Slave Addresses
- 24.3.10 Using the eUSCI_B Module in I2C Mode With Low-Power Modes
- 24.3.11 eUSCI_B Interrupts in I2C Mode
- 24.4 eUSCI_B I2C Registers
- 24.4.1 UCBxCTLW0 Register
- 24.4.2 UCBxCTLW1 Register
- 24.4.3 UCBxBRW Register
- 24.4.4 UCBxSTATW
- 24.4.5 UCBxTBCNT Register
- 24.4.6 UCBxRXBUF Register
- 24.4.7 UCBxTXBUF
- 24.4.8 UCBxI2COA0 Register
- 24.4.9 UCBxI2COA1 Register
- 24.4.10 UCBxI2COA2 Register
- 24.4.11 UCBxI2COA3 Register
- 24.4.12 UCBxADDRX Register
- 24.4.13 UCBxADDMASK Register
- 24.4.14 UCBxI2CSA Register
- 24.4.15 UCBxIE Register
- 24.4.16 UCBxIFG Register
- 24.4.17 UCBxIV Register
- 25 Manchester Function Module (MFM)
- 26 Embedded Emulation Module (EEM)
- Revision History
- Important Notice