MT76x7_Reference_Manual MT76x7 Reference Manual

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MT76x7_Reference_Manual Reference

Manual

Version: 1.09

Release date: 31 August 2017

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Document Revision History

Revision

Date

Description

0.77 6 October 2016 Initial draft

0.80 23 June 2016 • 1. Add detail description to CLOCK, GPT, RTC, PWM and SPI

Master module.

• 2. Add register table to section 6.11, 6.12 and 6.13

0.81 2 September 2016 Move register descriptions to individual sections.

0.82 30 September 2016 Add RTC max value and illustrate pinmux don’t care values.

1.00 4 Novermber 2016 • Correct the address of mpu_channel_en.

• Add description of way_replace_policy

• Add SPI Slave interface datasheet of 2.5.9

• Update Auxilliary ADC specifications of Table 4-6

• Correct Xtal frequency supporting values(26/40/52MHz) and

descriptions

1.01 26 December 2016 Remove BT EDR related information

1.02 1 March 2017 Add MT7697F to 1.1 general description and table 1.1

1.03 5 April 2017 Update GPIO description

1.05 5 April 2017 • 1. Updated Clock Generation Block Diagram

• 2. Modify RTC Block Diagram

1.04 20 April 2017 Removed SPI-M DMA & USB description

1.06 23 May 2017 • Removed XTAL note in Boot Strap Test Mode of Chip Mode

• Updated Power States for CM4 Subsystem Wake-up time table

• Updated I2S for Stereo & 44.1KHz/48KHz

1.07 2 Aug 2017 Replaced “full duplex” description with “both directional data” in

section 1.2.5.1, “Introduction” to SPI Master.

1.08 21 Aug 2017 • Updated Pinmux table, section 5.3, “Pin multiplexing”

• Updated PMU electrical characteristics, section 4.5, “PMU

characteristics”

1.09 31 August 2017 • Fixed SPI master transfer data buffer size description, see Figure

2-54

• Updated PMU LDO and BUCK description

• Updated Bootstrap options

• Updated XTAL requirements

• Added 32k XTAL functional specification

• Added PMU UVLO and PMU_EN_WF characteristics

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Table of Contents

Document Revision History ............................................................................................................................... 2

List of Tables and Figures .................................................................................................................................. 7

1. System Overview .................................................................................................................................. 12

1.1. Introduction ..................................................................................................................................... 12

1.2. Features ............................................................................................................................................ 12

1.2.1. Technology and packaging ............................................................................................. 12

1.2.2. Power management and clock source ........................................................................... 12

1.2.3. Platform .......................................................................................................................... 13

1.2.4. WLAN .............................................................................................................................. 13

1.2.5. Bluetooth ........................................................................................................................ 14

1.2.6. Miscellaneous ................................................................................................................. 14

1.3. Applications ...................................................................................................................................... 14

1.4. Block diagram ................................................................................................................................... 15

2. Functional Description .......................................................................................................................... 16

2.1. Overview .......................................................................................................................................... 16

2.2. Power Management Unit (PMU) ...................................................................................................... 16

2.2.1. PMU architecture ........................................................................................................... 16

2.2.1.1. PMU sleep mode ........................................................................................................... 16

2.2.2. Chip power plan ............................................................................................................. 17

2.2.3. Digital power domain and power states ........................................................................ 17

2.3. Clock and reset generation .............................................................................................................. 20

2.3.1. Clock ............................................................................................................................... 20

2.3.1.1. Cortex-M4 MCU clock Settings ...................................................................................... 23

2.3.1.2. Cortex-M4 serial flash clock setting .............................................................................. 25

2.3.1.3. Cortex-M4 SPI master clock setting .............................................................................. 27

2.3.1.4. I2S master clock setting for external CODEC ................................................................. 31

2.3.1.5. Audio CODEC clock setting ............................................................................................ 31

2.3.1.6. PWM clock setting ........................................................................................................ 31

2.3.1.7. AUXADC clock setting .................................................................................................... 32

2.3.1.8. Cortex-M4 I2C master clock setting .............................................................................. 32

2.3.1.9. Cortex-M4 UART clock setting ....................................................................................... 34

2.3.2. Reset ............................................................................................................................... 34

2.4. Application processor subsystem ..................................................................................................... 35

2.4.1. CPU ................................................................................................................................. 35

2.4.2. Cache and tightly coupled memory (TCM) ..................................................................... 35

2.4.2.1. General Description ....................................................................................................... 35

2.4.2.2. Programming guide of cache size configuration ........................................................... 38

2.4.2.3. Organization of cache .................................................................................................... 38

2.4.2.4. Theory of operations ..................................................................................................... 40

2.4.2.5. MPU ............................................................................................................................... 42

2.4.2.6. Remapping .................................................................................................................... 44

2.4.2.7. Register definitions ....................................................................................................... 45

2.4.3. Bus fabric ........................................................................................................................ 56

2.4.4. Serial flash controller ..................................................................................................... 57

2.4.4.1. General Description ....................................................................................................... 57

2.4.4.2. Block diagram ................................................................................................................ 58

2.4.4.3. Serial Flash related waveform ....................................................................................... 59

2.4.4.4. Programming guide ....................................................................................................... 64

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2.4.4.5. Register definitions ....................................................................................................... 65

2.4.5. DMA................................................................................................................................ 83

2.4.5.1. General description ....................................................................................................... 83

2.4.5.2. Full-Size and Half-Size DMA channels ........................................................................... 84

2.4.5.3. Ring buffer and double buffer memory data movement .............................................. 85

2.4.5.4. Unaligned word access .................................................................................................. 85

2.4.5.5. Virtual FIFO DMA ........................................................................................................... 86

2.4.5.6. DMA channels and priority control ............................................................................... 87

2.4.5.7. Register definitions ....................................................................................................... 88

2.4.6. General Purpose Timer................................................................................................. 352

2.4.6.1. Register definitions ..................................................................................................... 353

2.4.7. Watchdog timer ........................................................................................................... 360

2.4.7.1. Register definitions ..................................................................................................... 361

2.4.8. eFuse ............................................................................................................................ 365

2.4.9. Interrupt Controller ...................................................................................................... 365

2.4.9.1. Interrupt Sources......................................................................................................... 366

2.4.9.2. External interrupt ........................................................................................................ 368

2.4.10. Power-on sequence ...................................................................................................... 368

2.4.10.1. Power-on reset (Cold Reset) ....................................................................................... 369

2.4.10.2. Watchdog reset ........................................................................................................... 369

2.4.10.3. Reset scenarios ............................................................................................................ 370

2.4.10.4. Sleep and wakeup sequence ....................................................................................... 370

2.4.11. Memory map ................................................................................................................ 371

2.4.12. SYSRAM_CM4 ............................................................................................................... 376

2.4.13. Crypto engine ............................................................................................................... 376

2.4.13.1. Features ....................................................................................................................... 376

2.4.13.2. Functional description ................................................................................................. 376

2.4.13.3. Programming sequence .............................................................................................. 378

2.4.13.4. Register definitions ..................................................................................................... 383

2.5. Peripherals ..................................................................................................................................... 419

2.5.1. GPIO interface .............................................................................................................. 419

2.5.1.1. GPIO function .............................................................................................................. 419

2.5.1.2. Register definitions ..................................................................................................... 422

2.5.2. UART interface ............................................................................................................. 486

2.5.2.1. General description ..................................................................................................... 486

2.5.2.2. Programming guide ..................................................................................................... 487

2.5.2.3. Register map ............................................................................................................... 488

2.5.2.4. Register definitions ..................................................................................................... 489

2.5.3. I2C serial interface ........................................................................................................ 541

2.5.3.1. General description ..................................................................................................... 541

2.5.3.2. Functions ..................................................................................................................... 541

2.5.3.3. I2C programming sequence ........................................................................................ 542

2.5.3.4. Initialization ................................................................................................................. 542

2.5.3.5. TX/RX Sequence .......................................................................................................... 543

2.5.3.6. Registers definitions .................................................................................................... 549

2.5.4. Auxiliary ADC ................................................................................................................ 570

2.5.4.1. General description ..................................................................................................... 570

2.5.4.2. Function ....................................................................................................................... 570

2.5.4.3. Auxiliary ADC features: ................................................................................................ 572

2.5.4.4. Auxiliary ADC digital averaging FSM ............................................................................ 572

2.5.4.5. ADC FIFO access .......................................................................................................... 574

2.5.4.6. Programming sequence .............................................................................................. 575

2.5.4.7. Auxiliary ADC clock source .......................................................................................... 575

2.5.4.8. Register definitions ..................................................................................................... 576

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2.5.5. SPI master interface ..................................................................................................... 596

2.5.5.1. Introduction................................................................................................................. 596

2.5.5.2. SPI timing diagram....................................................................................................... 597

2.5.5.3. Programming guide .................................................................................................... 598

2.5.5.4. Registers definitions .................................................................................................... 599

2.5.6. SPI slave interface ........................................................................................................ 611

2.5.6.1. General description ..................................................................................................... 611

2.5.6.2. Block diagram .............................................................................................................. 611

2.5.6.3. SPI Slave CR Read/Write protocol ............................................................................... 612

2.5.6.4. Programming sequence .............................................................................................. 613

2.5.6.5. SPI slave protocol timing ............................................................................................. 616

2.5.6.6. Interrupt ...................................................................................................................... 619

2.5.6.7. SPI driver domain registers ......................................................................................... 619

2.5.6.8. SPI MCU domain registers ........................................................................................... 622

2.5.6.9. SPI pinmux configuration ............................................................................................ 628

2.5.7. I2S interface ................................................................................................................. 629

2.5.7.1. Registers definitions .................................................................................................... 630

2.5.8. Pulse Width Modulation (PWM) .................................................................................. 636

2.5.8.1. General description ..................................................................................................... 636

2.5.8.2. PWM block diagram .................................................................................................... 637

2.5.8.3. PWM function ............................................................................................................. 637

2.5.8.4. Programming examples ............................................................................................... 639

2.5.8.5. Notice .......................................................................................................................... 641

2.5.8.6. Register definitions (PWM_NUM = 0~39) ................................................................... 641

2.5.8.7. Application Notes ........................................................................................................ 644

2.5.9. IrDA............................................................................................................................... 644

2.5.9.1. General description ..................................................................................................... 644

2.5.9.2. Block Diagram .............................................................................................................. 644

2.5.9.3. IRTX functions .............................................................................................................. 645

2.5.9.4. Register definitions ..................................................................................................... 648

2.6. Radio MCU Subsystem ................................................................................................................... 664

2.6.1. CPU ............................................................................................................................... 664

2.6.2. RAM/ROM .................................................................................................................... 665

2.6.3. Memory map ................................................................................................................ 665

2.6.4. N9 bus fabric ................................................................................................................ 667

2.6.5. CIRQ .............................................................................................................................. 668

2.6.5.1. General description ..................................................................................................... 668

2.6.5.2. Functions ..................................................................................................................... 668

2.6.5.3. Interrupt sources ......................................................................................................... 669

2.6.5.4. Interrupt Source Masking ............................................................................................ 671

2.6.5.5. External Interrupt ........................................................................................................ 671

2.6.5.6. Programming guide ..................................................................................................... 672

2.6.5.7. Register definitions ..................................................................................................... 673

2.7. Wi-Fi subsystem ............................................................................................................................. 724

2.7.1. Wi-Fi MAC ..................................................................................................................... 724

2.7.2. WLAN baseband ........................................................................................................... 724

2.7.3. WLAN RF ....................................................................................................................... 725

2.8. Bluetooth subsystem...................................................................................................................... 725

2.9. RTC ................................................................................................................................................. 726

2.9.1. Main functions: ............................................................................................................ 726

2.9.2. Power Up/Down Flow .................................................................................................. 726

2.9.3. Register definitions ...................................................................................................... 727

3. Radio Characteristics .......................................................................................................................... 773

3.1. Wi-Fi radio characteristics .............................................................................................................. 773

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3.1.1. Wi-Fi RF block diagram ................................................................................................. 773

3.1.2. Wi-Fi 2.4GHz band RF receiver specifications .............................................................. 773

3.1.3. Wi-Fi 2.4GHz band RF transmitter specifications ......................................................... 775

3.1.4. Wi-Fi 5GHz band RF receiver specifications ................................................................. 775

3.1.5. Wi-Fi 5GHz band RF transmitter specifications ............................................................ 778

3.2. Bluetooth radio characteristics ...................................................................................................... 778

3.2.1. Bluetooth RF block diagram ......................................................................................... 778

3.2.2. Basic Rate receiver specifications ................................................................................ 779

3.2.3. Basic Rate transmitter specifications ........................................................................... 780

3.2.4. Bluetooth LE receiver specifications ............................................................................ 780

3.2.5. Bluetooth LE transmitter specifications ....................................................................... 781

4. Electrical Characteristics ..................................................................................................................... 782

4.1. Absolute Maximum Rating ............................................................................................................. 782

4.2. Recommended operating range .................................................................................................... 782

4.3. DC characteristics ........................................................................................................................... 782

4.4. XTAL oscillator ................................................................................................................................ 783

4.5. PMU characteristics ....................................................................................................................... 783

4.6. Auxiliary ADC characteristics .......................................................................................................... 785

4.7. Thermal characteristics .................................................................................................................. 786

5. Package Specifications ........................................................................................................................ 787

5.1. Pin layout........................................................................................................................................ 787

5.2. Pin description................................................................................................................................ 787

5.3. Pin multiplexing .............................................................................................................................. 790

5.4. Bootstrap ........................................................................................................................................ 796

5.5. Package information ...................................................................................................................... 797

5.6. Ordering information ..................................................................................................................... 797

5.7. Top marking ................................................................................................................................... 798

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List of Tables and Figures

Table 1-1 Differences between MT7697D, MT7697, MT7697F and MT7687F .................................................... 12

Table 2-1. MTCMOS power domain ..................................................................................................................... 17

Table 2-2. Power states for Cortex-M4 subsystem ............................................................................................... 19

Table 2-3. Power states for N9 Subsystem ........................................................................................................... 19

Table 2-4. Power state transition scenarios for N9 .............................................................................................. 20

Table 2-5. Power state transition scenarios for Cortex-M4 .................................................................................. 20

Table 2-6. Cortex-M4 clock rate ........................................................................................................................... 21

Table 2-7. N9 Clock Rate ....................................................................................................................................... 21

Table 2-8. Peripheral clock rate ............................................................................................................................ 22

Table 2-9. Cortex-M4 Clock GEN0 ........................................................................................................................ 25

Table 2-10. CM4 HCLK 2M Clock GEN ................................................................................................................... 27

Table 2-11. SPI master mode register................................................................................................................... 30

Table 2-12. PWM global control ........................................................................................................................... 32

Table 2-13. I2C Master Counting Value Phase ...................................................................................................... 34

Table 2-14. TCM and cache configuration ............................................................................................................ 35

Table 2-15. TCM Address Spaces of Different Cache Size Settings ....................................................................... 37

Table 2-16. Write-back Mode Cache R/W Action Summary ................................................................................. 41

Table 2-17. Write-through Mode Cache R/W Action Summary ........................................................................... 42

Table 2-18. Test patterns for whole chip simulation ............................................................................................ 44

Table 2-19. Flash controller support read mode .................................................................................................. 57

Table 2-20. Available DMA channels .................................................................................................................... 84

Table 2-21. Virtual FIFO Access Port ..................................................................................................................... 86

Table 2-22. DMA use for hardware functions....................................................................................................... 87

Table 2-23. General Purpose Timer Types .......................................................................................................... 352

Table 2-24. Cortex-M4 NVIC interrupt source .................................................................................................... 366

Table 2-25. Cortex-M4 external interrupt de-bounce period ............................................................................. 368

Table 2-26. Cortex-M4 memory map ................................................................................................................. 372

Table 2-27. AES hardware specification ............................................................................................................. 377

Table 2-28. DES hardware specification ............................................................................................................. 377

Table 2-29. AES128 programming sequence ...................................................................................................... 378

Table 2-30. AES192 programming sequence ...................................................................................................... 378

Table 2-31. AES256 programming sequence ...................................................................................................... 379

Table 2-32. DES programming sequence ............................................................................................................ 379

Table 2-33. Triple-DES programming sequence ................................................................................................. 380

Table 2-34. SHA256 programming sequence ..................................................................................................... 380

Table 2-35. SHA224 programming sequence ..................................................................................................... 380

Table 2-36. SHA1 programming sequence ......................................................................................................... 381

Table 2-37. MD5 programming sequence .......................................................................................................... 381

Table 2-38. SHA512 programming sequence ..................................................................................................... 382

Table 2-39. SHA384 programming sequence ..................................................................................................... 382

Table 2-40. Functional description of AGPIO ...................................................................................................... 422

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Table 2-41. Register map with conditional CR (LCR) .......................................................................................... 488

Table 2-42 The initialization of I2C ..................................................................................................................... 542

Table 2-43 The TX sequence of I2C Direct Normal Mode ................................................................................... 543

Table 2-44 The RX sequence of I2C Direct Normal Mode................................................................................... 543

Table 2-45 The TX sequence of I2C Direct General Mode .................................................................................. 544

Table 2-46 The RX sequence of I2C Direct General Mode .................................................................................. 545

Table 2-47 The TX sequence of I2C DMA Normal Mode .................................................................................... 545

Table 2-48 The RX sequence of I2C DMA Normal Mode .................................................................................... 546

Table 2-49 The TX sequence of I2C DMA General Mode .................................................................................... 547

Table 2-50 The RX sequence of I2C DMA General Mode ................................................................................... 548

Table 2-51. SPI pin description ........................................................................................................................... 596

Table 2-52. SPI Interface Pinmux Configuration ................................................................................................. 628

Table 2-53. SPI CPOL/CPHA configuration .......................................................................................................... 628

Table 2-54. I2S pin description ........................................................................................................................... 629

Table 2-55. I2S Slave Mode................................................................................................................................. 629

Table 2-56. I2S Data Format ............................................................................................................................... 629

Table 2-57. PWM Modes .................................................................................................................................... 636

Table 2-58. PWM parameters ............................................................................................................................. 638

Table 2-59. N9 memory map .............................................................................................................................. 665

Table 2-60. Internal interrupt source ................................................................................................................. 672

Table 2-61. External interrupt source ................................................................................................................. 673

Table 3-1. 2.4GHz RF Receiver Specification ...................................................................................................... 774

Table 3-2. 2.4GHz RF Transmitter Specifications ................................................................................................ 775

Table 3-3. 5GHz RF receiver specifications ......................................................................................................... 776

Table 3-4. 5GHz RF Transmitter Specifications ................................................................................................... 778

Table 3-5. Basic Rate transmitter specifications ................................................................................................. 780

Table 3-6. Bluetooth LE receiver specifications .................................................................................................. 780

Table 3-7. Bluetooth LE transmitter specifications............................................................................................. 781

Table 4-1 Absolute maximum rating .................................................................................................................. 782

Table 4-2. Recommended operating range ........................................................................................................ 782

Table 4-3. DC characteristics .............................................................................................................................. 782

Table 4-4. XTAL Oscillator requirements and performance ............................................................................... 783

Table 4-5. 32k XTAL Oscillator functional specifications .................................................................................... 783

Table 4-6. Recommended parameters of 32k XTAL Crystal ............................................................................... 783

Table 4-7. PMU electrical characteristics ........................................................................................................... 783

Table 4-8. PMU UVLO & PMU_EN_WF characteristics ....................................................................................... 784

Table 4-9. Auxiliary ADC specifications .............................................................................................................. 785

Table 4-10. Thermal characteristics .................................................................................................................... 786

Table 5-1. Pin Map .............................................................................................................................................. 787

Table 5-2. Pin descriptions.................................................................................................................................. 788

Table 5-3. Pin multiplexing ................................................................................................................................. 791

Table 5-4. Bootstrap Option– Flash Access Mode .............................................................................................. 796

Table 5-5. Bootstrap Option – XTAL Clock Mode ............................................................................................... 796

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Table 5-6. Bootstrap Option – 32KHz Clock Mode ............................................................................................. 796

Table 5-7. Bootstrap Option — Chip Mode ........................................................................................................ 796

Table 5-8. Ordering Information ......................................................................................................................... 797

Figure 1-1. System-on-chip block diagram ........................................................................................................... 15

Figure 2-1. Chip Power Block Diagram ................................................................................................................. 16

Figure 2-2 PMU sleep and wakeup sequence ....................................................................................................... 17

Figure 2-3. MT76x7 power state ........................................................................................................................... 19

Figure 2-4. Clock generation block diagram ......................................................................................................... 21

Figure 2-5. Clock domains in N9 and Cortex-M4 peripherals ............................................................................... 22

Figure 2-6. Cortex-M4 MCU clock switch ............................................................................................................. 23

Figure 2-7. Cortex-M4 flash clock switch .............................................................................................................. 25

Figure 2-8. Cortex-M4 SPI master clock switch .................................................................................................... 28

Figure 2-9. PWM tick clock switch ....................................................................................................................... 31

Figure 2-10. I2C counting VAL diagram ................................................................................................................ 32

Figure 2-11. Reset structure ................................................................................................................................. 34

Figure 2-12. MCU, cache, TCM and AHB bus connectivity ................................................................................... 36

Figure 2-13. Cache size and TCM settings ............................................................................................................ 37

Figure 2-14. Cache Lookup ................................................................................................................................... 39

Figure 2-15. Cache miss/refill criterion................................................................................................................. 41

Figure 2-16: MPU protection setting example ..................................................................................................... 43

Figure 2-17: Example Settings of Cache Remapping ............................................................................................ 44

Figure 2-18. Cortex-M4 subsystem – bus fabric ................................................................................................... 57

Figure 2-19. Serial flash controller block diagram ................................................................................................ 58

Figure 2-20. The red line block is the SF_TOP in MCUSYS_CM4. .......................................................................... 59

Figure 2-21. Example for direct read for SPI mode............................................................................................... 59

Figure 2-22. Example for quad I/O read in SPI mode ........................................................................................... 60

Figure 2-23. Example for quad I/O read in QPI mode .......................................................................................... 60

Figure 2-24. Direct read waveform for SPI mode ................................................................................................. 61

Figure 2-25. Direct read waveform for QPI mode ................................................................................................ 64

Figure 2-26. Generic DMA controller block diagram ............................................................................................ 84

Figure 2-27. Ring Buffer and Double Buffer Memory Data Movement ................................................................ 85

Figure 2-28. Unaligned Word Accesses ................................................................................................................ 86

Figure 2-29. Virtual FIFO DMA .............................................................................................................................. 86

Figure 2-30. Virtual FIFO Concept ......................................................................................................................... 87

Figure 2-31. The system diagram of the GPT_CM4 ............................................................................................ 353

Figure 2-32. PMU Power-on Sequence ............................................................................................................... 369

Figure 2-33. WDT structure ................................................................................................................................ 370

Figure 2-34. Sleep and wakeup sequence ......................................................................................................... 371

Figure 2-35. Crypto engine system ..................................................................................................................... 377

Figure 2-36. Crypto Engine block diagram .......................................................................................................... 377

Figure 2-37. AGPIO/GPIO Block Diagram (Left: AGPIO; Right: GPIO) ................................................................. 420

Figure 2-38. AGPIO configured as output multiplexing ..................................................................................... 421

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Figure 2-39. AGPIO configured as input multiplexing......................................................................................... 421

Figure 2-40. AGPIO configured as Input, Output or Analog mode ..................................................................... 422

Figure 2-41. UART block diagram ....................................................................................................................... 487

Figure 2-42 The block diagram of I2C module. ................................................................................................... 542

Figure 2-43 SCL clock phases .............................................................................................................................. 543

Figure 2-44. Auxiliary ADC block diagram (Analog Part) ..................................................................................... 571

Figure 2-45. Auxiliary ADC block diagram ........................................................................................................... 571

Figure 2-46. Auxiliary ADC Clock Timing Diagram .............................................................................................. 571

Figure 2-47. Auxiliary ADC digital averaging FSM .............................................................................................. 572

Figure 2-48. Auxiliary ADC FIFO access block diagram ...................................................................................... 574

Figure 2-49. Auxiliary ADC clock source diagram .............................................................................................. 576

Figure 2-50. SPI TX transaction, more_buf_mode=0 .......................................................................................... 597

Figure 2-51. SPI RX transaction, more_buf_mode=0 .......................................................................................... 597

Figure 2-52. SPI TX transaction, more_buf_mode=1 and both_directional_data_mode=0 ............................... 598

Figure 2-53. SPI RX transaction, more_buf_mode=1 and both_directional_data_mode=0 ............................. 598

Figure 2-54. SPI TX/RX transaction, more_buf_mode=1 and both_directional_data_mode=1 ........................ 598

Figure 2-55. SPI Slave block diagram .................................................................................................................. 611

Figure 2-56. SPI Slave CR Read/Write Protocol .................................................................................................. 612

Figure 2-57. SPI Slave otorola protocol .............................................................................................................. 616

Figure 2-58. I2S signal waveform ........................................................................................................................ 630

Figure 2-59. PWM block diagram ....................................................................................................................... 637

Figure 2-60. PWM Cycle...................................................................................................................................... 637

Figure 2-61. PWM Normal Function ................................................................................................................... 639

Figure 2-62. 2-State PWM .................................................................................................................................. 639

Figure 2-63. 2-State Replay Mode PWM ............................................................................................................ 639

Figure 2-64. IRDA block diagram ........................................................................................................................ 645

Figure 2-65. The Logic representation for NEC protocol .................................................................................... 645

Figure 2-66. The Pulse Train in Transmission of NEC Protocol ........................................................................... 646

Figure 2-67. Message is Started by a 9ms AGC Burst ......................................................................................... 646

Figure 2-68. A Repeat Code is Transmitted Every 110ms ................................................................................... 646

Figure 2-69. Coding Method for RC5 Protocol .................................................................................................... 647

Figure 2-70. The Lead Pulse in RC6 Protocol ...................................................................................................... 647

Figure 2-71. Coding Method for RC6 Protocol .................................................................................................... 648

Figure 2-72. The Trailer Pulse in RC6 Protocol ................................................................................................... 648

Figure 2-73. N9 bus fabric ................................................................................................................................... 667

Figure 2-74. N9 interrupt controller ................................................................................................................... 668

Figure 2-75 Interrupt Controller Block Diagram ................................................................................................. 669

Figure 2-76. External Interrupt Controller Block Diagram .................................................................................. 671

Figure 3-1. 2.4/5GHz RF block diagram ............................................................................................................. 773

Figure 3-2. Wi-Fi/Bluetooth RF block diagram ................................................................................................... 779

Figure 3-3. Basic Rate receiver specifications ..................................................................................................... 779

Figure 5-1. Package Outline Drawing.................................................................................................................. 797

Figure 5-2. Top marking ...................................................................................................................................... 798

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1. System Overview

1.1. Introduction

MT76x7 series chipsets, including MT7697D, MT7697 and MT87F, are highly integrated single chip solutions

featuring an application processor, a low power 1x1 11n Wi-Fi subsystem and a Power Management Unit

(PMU). The application processor subsystem contains an ARM® Cortex-M4 with floating point MCU and

peripherals, including UART, I2C, SPI, I2S, PWM, IrDA and auxiliary ADC. The chipset also contains a 32-bit RISC

CPU that could fully offload the application processor.

MT7697D includes a Wi-Fi dual-band subsystem with the 802.11a/b/g/n radio, baseband and MAC that are

designed to meet both the low power and high throughput application requirements. It also includes

embedded SRAM/ROM. The Bluetooth subsystem contains the Bluetooth radio, baseband and link controller

and uses the same 32-bit RISC CPU for Bluetooth protocols.

MT7697 includes a Wi-Fi dual-band subsystem with the 802.11b/g/n radio, baseband and MAC that are

designed to meet both the low power and high throughput application requirements. It also includes an

embedded SRAM/ROM. The Bluetooth subsystem contains the Bluetooth radio, baseband and link controller

and uses the same 32-bit RISC CPU for Bluetooth protocols.

MT7687F includes a Wi-Fi single-band subsystem with the 802.11b/g/n radio, baseband and MAC that are

designed to meet both the low power and high throughput application requirements. It also includes an

embedded SRAM/ROM and a 2MB serial flash in the package.

For the differences between MT7697D, MT7697, MT7697F and MT7687F family ICs, please refer to the Table

1-1, as shown below.

Table 1-1 Differences between MT7697D, MT7697, MT7697F and MT7687F

MT7697D

MT7697

MT7697F

MT7687F

Flash External SPI Flash External SPI Flash Embedded 2MB Flash Embedded 2MB Flash

Wi-Fi and

Bluetooth

Wi-Fi 1x1n 2G/5G

band

802.11a/b/g/n

Wi-Fi 1x1n 2G band

802.11b/g/n

Wi-Fi 1x1n 2G band

802.11b/g/n

Wi-Fi 1x1n 2G band

802.11b/g/n

Bluetooth Bluetooth LE Bluetooth LE Bluetooth LE None

1.2. Features

1.2.1. Technology and packaging

• Highly integrated 40nm RFCMOS technology

• 8mm x 8mm 68-pin QFN package

1.2.2. Power management and clock source

• Integrate high efficiency power management unit with single 3.3V power supply input

• 40, 26 and 52MHz source crystal clock support with low power operation in idle mode

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1.2.3. Platform

• ARM Cortex-M4 MCU with FPU with up to 192MHz clock speed

• Embedded 352KB SRAM and 64KB boot ROM

• Supports external serial flash with Quad Peripheral Interface (QPI) mode

• Supports eXecute In Place (XIP) on flash

• 32KB cache in XIP mode

• Hardware crypto engines including AES, DES/3DES, SHA2 for network security

• 28 General Purpose IOs multiplexed with other interfaces

• Two UART interfaces with hardware flow control and one UART for debug, all multiplexed with GPIO

• One SPI master interface multiplexed with GPIO

• One SPI slave interface multiplexed with GPIO

• Two I2C master interface multiplexed with GPIO

• One I2S interface multiplexed with GPIO

• Four channel 12-bit ADC multiplexed with GPIO

• 28 PWM multiplexed with GPIO

• 25 channels DMA

• Low power RTC mode with 32KHz crystal support

1.2.4. WLAN

• Dedicated high-performance 32-bit RISC CPU N9 with up to 160MHz clock speed

• IEEE 802.11 a/b/g/n compliant

• Supports 20MHz, 40MHz bandwidth in 2.4GHz and 5GHz bands

• Dual-band 1T1R mode with data rate up to 150Mbps

• Supports STBC, LDPC

• Greenfield, mixed mode, legacy modes support

• IEEE 802.11 d/e/h/i/k/r/w support

• Security support for WFA WPA/WPA2 personal, WPS2.0, WAPI

• Supports 802.11w protected managed frames

• QoS support of WFA WMM, WMM PS

• Integrated LNA, PA, and T/R switch

• Optional external LNA and PA support.

• RX diversity support with additional RX input

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1.2.5. Bluetooth

Bluetooth supports the following features on MT7697 and MT7697D:

• Bluetooth specification 2.1

• Bluetooth 4.2 Low Energy (LE)

• Integrated BALUN and PA

• Scatternet support: up to 7 piconets simultaneously with background inquiry, page scan

• Up to seven simultaneous active ACL links

• Support SCO and eSCO link with re-transmission

• Support wide-band speech and hardware accelerated SBC codec for A2DP streaming

• Packet loss concealment

• Channel quality driven data rate adaptation

• Channel assessment for AFH

1.2.6. Miscellaneous

• Integrates 4kbit eFuse to store device specific information and RF calibration data.

• Advanced Wi-Fi and Bluetooth coexistence scheme

1.3. Applications

MT76x7 is designed for Internet-of-Things applications based on Mediatek’s low power technology, Wi-Fi and

Bluetooth designs.

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1.4. Block diagram

UART x 2

Clock

generation 40/26/52MHz XTAL

PMU

UART x 2

I2C x 2

4 channel

Auxiliary ADC

SPI

SPI Flash

controller

25 channel

Generic DMA

TCM / Cache

(96KB)

ARM Cortex M4

with FPU

SPI flash

UART x 1

EFUSE

(4Kb)

N9 CPU

ILM/DLM

SRAM/ROM

Debug

UART x 2

GPIO/PWM x 28

Crypto Engine

Watch Dog

Timer

Bluetooth RF

Bluetooth

baseband

Bluetooth link

controller

Bluetooth

audio CODEC

Bluetooth RF

Wi-Fi dual-band

RF

Wi-Fi baseband

Wi-Fi MAC

Wi-Fi PSE

Wi-Fi RF

Cortex-M4

SYSRAM

(256KB)

SYSRAM

N9 subsystem Cortex-M4

subsystem

I2S

IrDA

General

Purpose Timer

RTC

32kHz XTAL

Figure 1-1. System-on-chip block diagram

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2. Functional Description

2.1. Overview

2.2. Power Management Unit (PMU)

A single regulated 3.3V power supply is required for the MT76x7. It could be from DC-DC converter to convert

higher voltage supply to 3.3V or boost from a lower voltage supply to 3.3V.

The PMU contains Under-Voltage Lockout (UVLO) circuit, several low drop-out regulators (LDOs), a highly

efficient buck converter and a reference band-gap circuit. The circuits are optimized for low quiescent current,

low drop-out voltage, efficient line/load regulation, high ripple rejection, and low output noise.

BUCK

(3.3V to 1.7V) CLDO

(1.7V to 1.15)

AVDD45_BUCK

AVDD12_VCORE

DVDD11

AVDD16_CLDO

LXBK

DVDDIO

AVDD16_WF0_AFE

AVDD16_XO

AVDD16_BT

RF LDO/RF

core (1.6V)

IO (3.3V)

AVDD33_WF0_A_TX

AVDD33_WF0_A_PA

AVDD33_WF0_G_TX

AVDD33_WF0_G_PA

AVDD33_BT

RF(3.3V)

LXBK

1.7V

3.3V

Digital core

(1.15V)

AVSS45_BUCK

VSS

AVDD25_ALDO_OUT

ALDO

(3.3V to 2.5V)

ADC

(2.5V)

AVDD25_AUXADC

ELDO

(3.3V to 2.5V)

AVSS25_AUXADC

VSS

2.5V

PMU_DIO33_OUT

3.3V

AVDD45_MISC

PWR_SW

(3.3V)

Figure 2-1. Chip Power Block Diagram

2.2.1. PMU architecture

The PMU integrates 3 LDOs and one buck converter.

The buck converter converts 1.55~1.86V output to other subsystems in MT76x7. It can be operated in PFM

mode or PWM mode. Through an external on-board LC filter (2.2µH inductor and 10µF cap), it outputs a low

ripple 1.55~1.86V to Wi-Fi RF system, Bluetooth RF system and CLDO. CLDO is under BUCK domain and then it

outputs 1.15V for all digital logic used on the chip. ALDO is also from the 3.3V chip supply input and generates

2.5V for the auxiliary ADC.

Once MT76x7 goes into deep sleep mode, ALDO shuts down, and BUCK and CLDO are configured into low-

power mode with low Iq.

PMU has an integrated ELDO (eFuse LDO). It provides 2.5V output voltage to the internal eFuse macro in

programming mode.

2.2.1.1. PMU sleep mode

When both TOP_OFF (N9) and CM4_OFF power domains enter into sleep mode, the PMU enters the sleep

mode automatically. BUCK and CLDO are turned-off in the PMU sleep mode. SLDOH and SLDOL are turned-on

to provide 1.6V and 1.15V power. By setting the SLDOL parameters, SLDOL can lower its output voltage to save

power consumption in PMU sleep mode.

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TOP_OFF or CM4_OFF leaving sleep mode also wakes up the PMU. In normal mode, BUCK/ CLDO are turned-

on to provide large power for the whole chip and SLDOH/SLDOL are turned-off.

Please refer to Figure 2-2 for PMU sleep and wakeup sequence. The SLDOL TEMP1 and STABLE value setting is

in RG_PMU_08 (0x81021420).

BUCK

ENABLE

SLDOH

ENABLE

SLDOL

ENABLE

CLDO

ENABLE

SLDOL

Voltage 1.15V 1.0V

(VSEL_TEMP1) 0.85 V

(VSEL_STABLE) 1.15V

Figure 2-2 PMU sleep and wakeup sequence

2.2.2. Chip power plan

The 3.3V power source is directly supplied to the switching regulator, digital I/Os, and RF-related circuit. It is

converted to 2.5V by the LDO for ADC analog circuit. It is converted to 1.6V by the buck converter for low

voltage circuits. The built-in digital LDOs and RF LDOs converts 1.6V to 1.15V for digital, RF, and BBPLL core

circuits.

2.2.3. Digital power domain and power states

The digital circuit is separated into five power domains.

• TOP_AON

• TOP_OFF(N9)

• WF_OFF

• BT_OFF

• CM4_SYS.

Except for TOP_AON, each power domain can be turned on and off individually.

Table 2-1. MTCMOS power domain

Domain

Description

Circuit Included

OFF Condition

TOP_AON Always-on power domain,

which keeps the minimum

circuit powered to wake up

from the sleep mode upon

receiving a wake-up event.

It includes:

• Chip level configuration

register.

• Sleep mode controller;

N/A

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Domain

Description

Circuit Included

OFF Condition

•

External interrupt

controller;

• Part of the Wi-Fi MAC

that handles the beacon

filtering.

• Sustain and backup

memory that stores the

RAM code and the

register values that

need to be kept during

sleep mode.

TOP_OFF(N9) The power domain can be

power gated in Wi-Fi power

save mode and Bluetooth

power save mode.

The N9 subsystem with its

peripherals and part of the

Wi-Fi MAC circuit are

included.

N9 is in sleep mode

and no DMA functions

are enabled.

WF_OFF The power domain can be

power gated when Wi-Fi is

not used and in Wi-Fi power

save mode.

The Wi-Fi baseband and part

of the MAC subsystem are

included.

• Wi-Fi is disabled.

• N9 is in standby

mode or in sleep

mode.

BT_OFF The power domain can be

power gated when

Bluetooth is not used and in

Bluetooth power save

mode.

The Bluetooth subsystem is

included.

• Bluetooth is

disabled.

• N9 is in standby

mode or in sleep

mode.

CM4_OFF The power domain is not

powered gated when Cortex

M4 is used.

Cortex-M4 subsystem with

its peripherals is included.

N/A

The MT76x7 power state diagram is shown in Figure 2-3. There are two sleep mode controllers, controlled by

N9 and Cortex-M4, respectively.

The N9 power state and Cortex-M4 power state operate independently. When both enter the sleep mode, the

XTAL and PMU can be changed to the low power mode to further lower the current consumption.

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N9 active

Wi-Fi ON

PLL clock

N9 standby

XTAL 26MHz

N9 sleep

XTAL 32KHz

MCU idle

Wi-Fi ON

PLL clock

PMU sleep

XTAL/PMU in low

power mode

Cortex-M4 sleep

XTAL 32KHz

Cortex-M4

standby

XTAL 26MHz

Cortex-M4 active

PLL Clock

PMU sleep

XTAL/PMU in low

power mode

When both Cortex-M4 and N9

are in sleep mode, XTAL

and PMU is changed

to low power mode.

Enter sleep mode

Wake-up from sleep timer expired or interrupt

Enter sleep mode

Figure 2-3. MT76x7 power state

Table 2-2. Power states for Cortex-M4 subsystem

MCU mode

Description

Wake-up time

Power

CM4 active MCU executing code at PLL clock n/a

CM4

standby

MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. PLL is off.

100 ns

(HCLK comes

from XTAL)

CM4 sleep MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. Only 32KHz clock from XTAL is active. MCU

is configured to wake up on the expiry of the internal timer and

external wake-up events.

850 us 1mA

PMU sleep CM4_OFF is power gated. XTAL and PMU operate in low power

mode. MCU is configured to wake up on the expiry of the internal

timer and external wake-up events.

5.2 ms 0.3mA

Table 2-3. Power states for N9 Subsystem

MCU mode

Description

Wake-up time

Power

N9 active MCU executing code at PLL clock. n/a

MCU idle MCU clock is gated off, while MCU subsystem clocks are on to

maintain the operation of Wi-Fi function, like listening to beacon.

PLL is on.

800 ns

N9 standby MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. PLL is off.

100 ns

(HCLK comes

from XTAL)

N9 sleep • MCU subsystem clocks are gated off and the state of the

entire subsystem is retained.

• Only 32KHz clock from XTAL is active.

• MCU is configured to wake up on the expiry of the internal

1.2 ms 1mA

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MCU mode

Description

Wake-up time

Power

timer, external wake-up events, or the wake-up events from

Wi-Fi radio or Bluetooth ratio.

PMU sleep • TOP_OFF (N9) and WF_OFF are power gated. XTAL and PMU

operate in low power mode.

• The state information is retained in back-up buffer (sleep-

mode memory) and can be restored when wake-up.

• MCU is configured to wake up on the expiry of the internal

timer, external wake-up events, or the wake-up events from

Wi-Fi radio or Bluetooth ratio.

5.2 ms 0.3mA

*XTAL: 40 MHz

The typical scenarios which N9 operates in and the power state transition are summarized in Table 2-4.

Table 2-4. Power state transition scenarios for N9

Scenario

Description

State transition

1 All functions are idle and the N9 firmware triggers to enter the

sleep mode.

Active à Standby à Sleep

2 Wi-Fi DTIM timer is expired and the hardware wakes up to listen

to beacon and then goes to sleep again when It is not necessary

to wake up N9 to process the data.

Sleep à MCU idle (Wi-Fi ON) à

sleep

3 Wi-Fi DTIM timer is expired and the hardware wakes up to listen

to beacon and then wake up N9 to process the data.

Sleep à MCU idle (Wi-Fi ON) à

Active

The typical scenarios which CM4 operates in and the power state transition are summarized in the following

table.

Table 2-5. Power state transition scenarios for Cortex-M4

Scenario

Description

State transition

1 All functions are idle and the CM4 firmware triggers to enter the

sleep mode.

Active à Standby à Sleep

2 The wake-up event (wake-up event from N9 or other sources)

triggers Cortex-M4 to wake up.

Sleep à Standby à Active

2.3. Clock and reset generation

2.3.1. Clock

MT76x7 is connected to the XTAL or external clock source as the single clock source of the whole system. The

XTAL oscillator can support the XTAL frequencies from among 40, 26 and 52MHz.

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XTAL

oscillator

f = 40/

26/52MHz

PLL1

DIV

PLL2

DIV 1

DIV 3

DIV 12 WF_RXADC_CLK

80MHz

WF_TXDAC_CLK

960MHz

WF_DIG_CLK

320MHz

32MHz 960MHz

DIV 5

SPI CLOCK

FLASH CLOCK

I2C CLOCK

UART CLOCK

XPLL (Audio Frac-N)

±1% (0.01% granularity)

I2S_MCLK

16MHz

AUXADC CLOCK

PWM CLOCK

DIV 13

2-32 step 0.5

1-160MHz

1-192MHz

832MHz

640MHz

RF PLL

WF RF

DIV 5

2-32 step 0.5

XTAL CLOCK

DIV

PMU

BGCLK

(25KHz)

F32K CLOCK

2MHz

0

1

DIV

DIV options:

480, 240, 120, 60,

30, 20, 15, 12, 10

9.6, 19.2, 38.4, 115.2KHz

DIV

DIV options: 2708,1354,677,226

DIV

50, 100, 200, 400KHz

DIV options: 520,260,130,65

N9 CLOCK

160MHz

DIV 8

DIV 794

CM4 CLOCK

192MHz

120MHz

250, 500KHz

1, 2, 4, 6, 8, 10, 12MHz

DIV 64MHz

DIV 16MHz

RF power domain

AON power domain

CM4 power domain

DIV 2

PMU power domain

830081B4[14:13]

0

1

2

80021114[21:20]

81021170[12:8]

830081B0[2:0]

1

4

1

3

830081B0[15:14]

830081B0[9:4]

81021100[2:0] 1

4

81021100[9:4]

830081B4[7:3]

1-32 step 1

0

1

3

81021100[15:14]

81021100[17:16]

81021100[31:21]

2

830081B4[17]

830081B4[23:19]

24000028[27:16]

830B0000[27:24]

2

830081B4[12:8]

8300A600[2:1]

2

0

83090244[15:0] 83090248[15:0]

830A0244[15:0]830A0248[15:0]

1

XTAL

oscillator

f = 32KHz

RTC

RTC power domain

Figure 2-4. Clock generation block diagram

• PLL1 is used to generate the clock sources for Bluetooth and PLL2.

• PLL2 is used to generate the clock sources for Wi-Fi, N9 core, Cortex-M4 core and bus fabric.

• XPLL is used to generate the clock sources for I2S (for external audio CODEC).

The options of clock rate for MCU are listed below.

Table 2-6. Cortex-M4 clock rate

Reference Clock

(MHz)

MCU Clock

(MHz, XTAL mode)

MCU Clock (MHz, PLL mode)

40 40 30, 32, 40, 48, 60, 80, 96, 120, 160, 192

26 26

52 52

Table 2-7. N9 Clock Rate

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Reference Clock (MHz)

MCU Clock

(MHz, XTAL mode)

MCU Clock (MHz, PLL mode)

40 40 30, 32, 40, 48, 60, 80, 96, 120, 160, 192

26 26

52 52

Table 2-8. Peripheral clock rate

Peripheral Clock Rate

Supported specifications

PWM

XTAL clock with DIV13 (Default)

200Hz at minimum.

XTAL clock

F32K clock

UART

XTAL clock with DIV

9.6kbps, 19.2kbps, 38.4kbps, 115.2kbps,

3Mbps

I2C

XTAL clock with DIV

50, 100, 200, 400kHz

SPI

XTAL clock with DIV (Default)

0.25, 0.5, 1, 2, 4, 6, 8, 10, 12MHz

Flash XTAL clock with DIV (Default)

64MHz.

BT_DIG_CLK (64MHz) with DIV

Cortex-M4 clock with DIV

I2S

Cortex-M4

TCM

Cache

INT

WDT

GPT SYSRAM GDMA MTK

Security

PWM

x40

UART

x2

I2C

x2

SPI

Flash

CTRL

ADC

HIF SYS

WF/BT

AHB

ASYNC

Bridge

x2

Cortex-M4 Clock

N9 CLOCK

ADC

CLOCK

FLASH

CLOCK

SPI

CLOCK

I2C

CLOCK

UART

CLOCK

PWM

CLOCK

Figure 2-5. Clock domains in N9 and Cortex-M4 peripherals

MT76x7 clock setting is configured by CRs that control some clock dividers and MUXs.

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Note : all the clock sources must be enabled and stable when the software applies a switch.

2.3.1.1. Cortex-M4 MCU clock Settings

Cortex-M4 MCU Clock supports 32kHz, 40MHz(XTAL) and maximum 192MHz (divided from PLL). Cortex-M4

MCU clock is Cortex-M4 CPU and AHB BUS clock.

Figure 2-6. Cortex-M4 MCU clock switch

The configure CRs are

cm4_wbtac_mcu_ck_sel[1:0] : 0x830081B0[15:14]

cm4_mcu_div_sel[5:0] : 0x830081B0[9:4]

cm4_hclk_sel[2:0] : 0x830081B0[2:0]

***reference Table 2-9

830081B0

CM4_CKGEN0

CM4 CLOCK CONTROL REGISTER 0

00040180

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Na

me AAAA AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

CM4

_

MPD

_

DUT

Y

CM4

_

MPD

_

DLY

AAA

A CM4_PLL_DIV

_E N

Typ

e

RW RW RW

Res

et

0 0 1 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Na

me

CM4_WBT

AC

_MCU_CK

_S EL

CM4_MPD_CG

_BY PASS

AAA

A CM4_MCU_DIV_SEL AAA

A CM4_HCLK_S

EL

Typ

e

RW RW RW RW

Res

et

0 0 0 0 0 0 1 1 0 0 0 0 0 0

Bit(s)

Name

Description

mcu_p ll_d iv

(1 .5 :0 .5 :32.0 )

cm4 _ wbtac_mcu_ck_sel[1 :0 ]

0

1

2

3

1 'b 0

0

1

2

3

4

5

6

7

sys_64m _ clk

÷ 2 or 4

cm4 _ h clk_sel[2 :0 ]

cm4 _ mcu_d iv_sel[5 :0 ]

Value 1 ~ 62

f32k _ clk

XTAL

ext_clk for testing

XTAL

960MHz (PLL2 )

320MHz (PLL2 )

832MHz (PLL1 )

CM4 MCU Clock

1 'b 0

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Bit(s)

Name

Description

21

CM4_MPD_DUTY

Duty of mcu_pll_div clock out

20

CM4_MPD_DLY

Delay for change signal in mcu_pll_div (in case of too

large CDC delay)

0 : 4T

1 : 5T

18:16

CM4_PLL_DIV_EN

[2] pll_div_en

[1] pll_div2_en

[0] pll_div4_en

15:14

CM4_WBTAC_MCU_CK_SEL

CM4 MCU clock

frequency selection.

2'b000 : XTAL freq

2'b001 : WIFI PLL 960MHz

2'b010 : WIFI PLL 320MHz

2'b011 : BBPLL1 832MHz (26/52 MHz XTAL) or 640MHz (40

MHz XTAL)

13:11

CM4_MPD_CG_BYPASS

Bypass clock gated function in MCU_PLL_DIV module

9:4

CM4_MCU_DIV_SEL

6'd0

: INVAILD, clock will stop when this field is

cleared to 6'h0

6'd1 : div factor=1.5

6'd2 : div factor=2.0

....

6'd61 : div factor=31.5

6'd62 : div factor=32.0

2:0

CM4_HCLK_SEL

MCUSYS_CM4 root clock source selection

000 : OSC clock 20/26/40/52 MHz

001 :

32K clock out, selected by 32K_SEL[1:0]

010 : SYS 64MHz clock

011 : N/A

100 : PLL after divider :

divider source = CM4_WF/BT PLL

(CM4_WBTAC_MCU_CK_SEL)

divider factor = CM4_MCU_DIV_SEL [5:0]

101 : RBIST clock from PAD

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Table 2-9. Cortex-M4 Clock GEN0

• Set Cortex-M4 MCU clock to 192MHz (divided from PLL2)

o Enable PLL1+PLL2 and polling to ready

o Set cm4_wbtac_mcu_ck_sel[1:0]=2’h1 to switch source clock of CM4 PLL divider to PLL2

(960MHz)

o Set cm4_mcu_div_sel[5:0]=5’h8 to set divider clock output to 192MHz. (divided 960MHz by 5 (1 +

8/2)).

o Set cm4_hclk_sel[2:0]=3’h4 to switch CM4 MCU clock to the output of PLL divider

• Set CM4 MCU clock to 160MHz (divided from PLL2)

o Enable PLL1+PLL2 and polling to ready

o Set cm4_wbtac_mcu_ck_sel[1:0]=2’h2 to switch source clock of CM4 PLL divider to PLL2

(320MHz)

o Set cm4_mcu_div_sel[5:0]=5’h2 to set divider clock output to 160MHz. (divided 320MHz by 2 (1 +

2/2)).

o Set cm4_hclk_sel[2:0]=3’h4 to switch CM4 MCU clock to the output of PLL divider

• Set CM4 MCU clock to 64MHz (divided from PLL1)

o Enable PLL1 and polling to ready

o Set cm4_wbtac_mcu_ck_sel[1:0]=2’h0 to switch source clock of CM4 PLL divider to XTAL

o Set cm4_hclk_sel[2:0]=3’h2 to switch CM4 MCU clock to the sys_64m_clk

• Set CM4 MCU clock to XTAL clock

o Set cm4_wbtac_mcu_ck_sel[1:0]=2’h0 to switch source clock of CM4 PLL divider to XTAL

o Set cm4_hclk_sel[2:0]=3’h0 to switch CM4 MCU clock to the XTAL

2.3.1.2. Cortex-M4 serial flash clock setting

Cortex-M4 Serial Flash clock supports maximum frequency of 83.2MHz. It can be switched to XTAL clock,

64MHz (divided from PLL) and cm4_hclk (the maximum of 83.2MHz).

Figure 2-7. Cortex-M4 flash clock switch

The configure CRs are

sf_top_clk_sel[1:0] : 0x830081B4[14:13]

sf_top_clk_sel[1 :0 ]

0

1

2

3

XTAL

sys_64m _ clk

cm4 _ h clk

f32k _ clk

cm4 _ flash_clk

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***reference Table 2-10

830081B4

HCLK_2M_CKEGN

HCLK_2M_CK CONTROL REGISTER

00390C61

Bit 31 30 29 28 27 26 25 24

2

3

2

1

2

0

1

9

18 17 16

Nam

e

AAA

A AAAA AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A SPIM_120M_DIV

_SEL AAAA

SPIM

_CK

_

SEL

SPIM

_120

M_C

K

_EN

Type

RW

Rese

t

0 0 1 1 1 0 1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

AAA

A SF_TOP_C

L K_SEL HCLK_2M_SW_DIV_SEL HCLK_2M_DIV_SE

L

HCL

K

_2M

_

SRC_

CK_S

EL

HCL

K

_2M

_

DIV_

SEL_

SW

HCL

K

_2M

_

CK_E

N

Type

RW

RO

RW

Rese

t

0 0 0 1 1 0 0 0 1 1 0 0 0 0 1

Bit(s)

Name

Description

23:19

SPIM_120M_DIV_SEL

SPIM_120M_DIV_SEL[4:0]

Freq. divider factor

5'd0 : x1 (bypass)

5'd1 : x(1/2)

5'd2 : x(1/3)

....

5'd31: x(1/32)

17

SPIM_CK_SEL

SPIM_CK Select

1'b0 : SPIM_120M_CK

1'b1 : XTAL Clock

16

SPIM_120M_CK_EN

SPIM_120M_CK Output Enable

1'b0

: disable SPIM_120M_CK output

1'b1 : enable SPIM_120M_CK output

14:13

SF_TOP_CLK_SEL

SF_TOP Clock Select

2'b00 : XTAL Clock

2'b01 :SYS 64M Clock

2'b10 :CM4_HCLK_CK

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Bit(s)

Name

Description

2'b11 :AON_F32K_CK

12:8

HCLK_2M_SW_DIV_SEL

HCLK_2M_CK SW DIV SEL

7:3

HCLK_2M_DIV_SEL

HCLK_2M_DIV_SEL[4:0]

Freq. divider factor

5'd0 : x1 (bypass)

5'd1 : x(1/2)

5'd2 : x(1/3)

....

5'd31: x(1/32)

2

HCLK_2M_SRC_CK_SEL

HCLK_2M_CK Source Clock Slect

1'b0 : select XTAL clock

1'b1 : select F32K clock

1

HCLK_2M_DIV_SEL_SW

HCLK_2M_CK SW Mode

1'b0

: HW control

1'b1 : SW control

0

HCLK_2M_CK_EN

HCLK_2M_CK enable

1'b0 : disable HCLK_2M_CK

1'b1 : enable HCLK_2M_CK

Table 2-10. CM4 HCLK 2M Clock GEN

• Set Cortex-M4 serial flash clock to XTAL clock

o Set cm4_sf_top_clk_sel[1:0]=2’h0 to switch Cortex-M4 serial flash clock to XTAL

• Set Cortex-M4 serial flash clock to 64MHz (divided from PLL1)

o If PLL1 is enabled, goes to next step. Otherwise, enable PLL1 and polling to ready

o Set cm4_sf_top_clk_sel[1:0]=2’h1 to switch Cortex-M4 Serial Flash clock to 64MHz (sys_64m_clk)

• Set Cortex-M4 serial flash clock to cm4_hclk (max. frequency is 83.2MHz)

o Set cm4_sf_top_clk_sel[1:0]=2’h2 to switch Cortex-M4 serial flash clock to cm4_hclk.

2.3.1.3. Cortex-M4 SPI master clock setting

Cortex-M4 SPI master clock supports 4, 6, 8, 10 and 12 MHz (divided from 120MHz clock).

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Figure 2-8. Cortex-M4 SPI master clock switch

The configure CRs are

spim_clk_sel : 0x830081B4[17]

rs_clk_sel[11:0] : 0x24000028[27:16]

***reference Table 2-10 and Table 2-11

24000028

SMMR

SPI master mode register

00018880

Bit 31 30 29 28

2

7

26 25 24 23 22 21 20 19 18

1

7

1

6

Nam

e rs_slave_se

l

clk_

mod

e

rs_clk_sel

Type

RW

Reset

0

1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e cs_dsel_cnt full

_du

p lex

int

_

en

spi

_

star

t_se

l

pfet

ch_

e n - CPH

A CPO

L

lsb

_

firs

t

more

_buf

_mo

d e

-

Type RW RW RW RW RW

R

O

RW RW RW RW RO

Reset

1

0

1

0

1

0

Bit(s)

Name

Description

31:29

rs_slave_sel

rs_slave_sel.

3'h0: select SPI device #0. (default is flash)

3'h1: select SPI device #1.

~

3'h7: select SPI

device #7.

28

clk_mode

This register is used to specify that period of SCLK HIGH

is longer or period of SCLK LOW is longer when clock

divisor(rs_clk_sel) is odd.

1'b0: period of SCLK LOW is longer.

sp im _ck_sel

0

1

XTAL

sys_120m _ clk

spim _clk

D IV

rs_clk_sel[11:0 ]

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Bit(s)

Name

Description

1'b1: period of SCLK HIGH is longer.

27:16

rs_clk_sel

Register Space SPI clock frequency select.

12'h0: SPI clock frequency is hclk/2. (50% duty cycle, duty cycle is

the ratio of the output high time to the total cycle time)

12'h1: SPI clock frequency is hclk/3. (33.33% or 66.67% duty cycle)

12'h2: SPI clock

frequency is hclk/4. (50% duty cycle)

12'h3: SPI clock frequency is hclk/5. (40% or 60% duty cycle)

~

12'h4095: SPI clock frequency is hclk/4097.

15:11

cs_dsel_cnt

Internal delay the de

-select time of SPI chip select is

configured to occupy the number of

cycles of spim_clk

clock.

10

b

oth-directional data

Both directional data or half duplex mode.

1'b0: half duplex mode.

1'b1:

both-directional data mode.

Note: The

both-directional data is valid only when more_buf_mode

= 1. The transmission is always as hal

f duplex when

more_buf_mode = 0;

9

int_en

Interrupt enable.

1'b0: disable SPI interrupt.

1'b1: enable SPI interrupt.

8

spi_start_sel

The interval between spi_cs_n and spi_sclk.

1'b0: 3 spim_clk

1'b1: 6 spim_clk

7

pfetch_en

SPI pre

-fetch buffer enable

1'b0: disable pre

-fetch buffer.

1'b1: enable pre

-fetch buffer.

6

-

Reserved.

5

CPHA

Initial SPI clock phase for SPI transaction.

There are four SPI modes used to latch data. These SPI modes latch

data in one of four ways, and are defined by the logic

state

combinations of the CLK Polarity (CPOL) in relation to the CLK

Phase (CPHA). The valid logic combinations identify and determine

the SPI modes supported by the SPI device.

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Bit(s)

Name

Description

At CPOL=0 the base value of the clock is zero

For CPHA=0 (mode 0), data is rea

d on the clock's rising edge and

data is changed on a falling edge.

For CPHA=1 (mode 1), data is read on the clock's falling edge and

data is changed on a rising edge.

At CPOL=1 the base value of the clock is one (inversion of CPOL=0)

For CPHA=0 (mode 2),

data is read on clock's falling edge and data

is changed on a rising edge.

For CPHA=1 (mode 3), data is read on clock's rising edge and data is

changed on a falling edge.

4

CPOL

Initial SPI clock polarity for SPI transaction.

3

lsb_first

lsb_first.

1'b0:

MSB(most significant bit) is transferred first for SPI

transaction.

1'b1: LSB(least significant bit) is transferred first for SPI

transaction.

2

more_buf_mode

Select 2 words buffer or 8 words buffer for SPI

transaction.

1'b0: SPI transfer data buffer siz

e is only 2 words. In this mode, SPI

DI/DO data #0 register and SPI opcode/address register are the

data buffer for SPI transaction. And, SPI master follows

mosi_byte_cnt and miso_byte_cnt to complete the transmission

and reception, respectively. This

type

of transaction must operate in

half duplex mode.

1'b1: SPI transfer data buffer size is 8 words. In this mode, SPI

opcode/address register are the data buffer for SPI transaction and

follows cmd_bit_cnt to complete the transaction. SPI DI/DO data

#0~#7 register are the data buffer for SPI transaction an

d follows

do_bit_cnt and di_bit_cnt to complete the transmission and

reception, respectively. In half duplex mode, transmitted data are

loaded from SPI opcode/address register and SPI DI/DO data

#0~#7 registers. And, the received data will overwrite the SP

I

DI/DO data #0~#7 registers. In

both-directional data mode, SPI

DI/DO data #0~#3 registers are used for transmission and SPI

DI/DO #4~#7 registers are used for receipt.

1:0

-

Reserved.

Table 2-11. SPI master mode register

• Set Cortex-M4 SPI Master clock to 120MHz (divided from PLL2)

o If PLL2 is not enabled, enable PLL2 and polling to ready.

o Set spim_clk_sel to 1’b0

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o Set rs_clk_sel[11:0] to 12’h8/12’hA/12’hD/12’h12/12’h1E, SPI Master clock is 12/10/8/6/4MHz.

(120MHz / (2+n))

• Set Cortex-M4 SPI Master clock to XTAL Clock

o Set spim_clk_sel to 1’b1

o Set rs_clk_sel[11:0] to n, SPI Master clock is (26/(2+n))MHz.

2.3.1.4. I2S master clock setting for external CODEC

I2S Master Clock supports 16MHz (divided from XPLL). Hardware controls the divider and clock MUX. No need

to configure it through software.

2.3.1.5. Audio CODEC clock setting

Audio CODE Clock supports 6.5 MHz (divided from XPLL).

Hardware controls the divider and clock MUX. No need to configure it through software.

2.3.1.6. PWM clock setting

PWM Clock supports 32 kHz, 2 MHz (divided from XTAL and shared with AUXADC) and XTAL.

Figure 2-9. PWM tick clock switch

The configure CRs are

pwm_tick_clock_sel[1:0] : 0x830081B4[14:13]

***reference Table 2-12

8300A600

PWM_GLO_CTRL

PWM global control

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

-

Type

RO

Reset

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name -

pwm_

glob

al_r

eset

pwm_tick_

clock_sel

glob

al_k

ick

Type

RO

RW

WO

Reset

0

pwm_tick_clock_sel[1 :0 ]

0

1

2

3

XTAL

sys_ 2 m _ clk

f32k _ clk

pwm_tick_clk

1 'b 0

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Bit(s)

Name

Description

31:4

-

Reserved

3

pwm_global_reset

Write 1 and then write 0 to reset all PWM modules and its

parameters

(PWM_CTRL/PWM_PARAM_S0/PWM_PARAM_S1).

2:1

pwm_tick_clock_sel

PWM tick clock select.

2'h0: 32KHz

2'h1: 2MHz

2'h2: XTAL clock

0

global_kick

All PWM modules with "pwm_global_kick_enable" would be

kicked by this bit at the same time

Table 2-12. PWM global control

• Set PWM tick clock to 32kHz

o Set pwm_tick_clock_sel[1:0]=2’h0 to switch PWM Tick Clock to 32KHz (f32k_clk)

• Set PWM tick clock to 2MHz (divided from XTAL)

o Set pwm_tick_clock_sel[1:0]=2’h1 to switch PWM Tick Clock to 2MHz (sys_2m_clk)

• Set PWM tick clock to XTAL clock

o Set pwm_tick_clock_sel[1:0]=2’h2 to switch PWM Tick Clock to XTAL Clock

2.3.1.7. AUXADC clock setting

AUXADC clock only supports 2MHz (divided from XTAL and shared with PWM).

This is the default hardware setting. No need to configure it through software.

2.3.1.8. Cortex-M4 I2C master clock setting

Cortex-M4 I2C Master clock supports 50, 100, 200, 400 kHz. The digital logic clock of I2C Master Controller is

the XTAL clock. I2C Master Interface clock (SCL) is controlled by a state machine configured by 4 VAL registers.

These 4 VAL registers can tune the I2C interface frequency and the phase of SCL and SDA.

Figure 2-10. I2C counting VAL diagram

The configuration CRs are

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MM_CNT_PHASE_VAL0[7:0] : x83090244[7:0]

MM_CNT_PHASE_VAL1[7:0] : x83090244[15:8]

MM_CNT_PHASE_VAL2[7:0] : x83090248[7:0]

MM_CNT_PHASE_VAL3[7:0] : x83090248[15:8]

***reference Table 2-12

83090244

MM_CNT_VAL_PHL

Counting Value Phase Low

0000FFFF

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

MM_CNT_PHASE_VAL1 MM_CNT_PHASE_VAL0

Type

RW

Rese

t

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit(s)

Name

Description

15:8

MM_CNT_PHASE_VAL1

Phase 1 counting value. SCL rising edge to SDA timing.

The STOP condition period.

7:0

MM_CNT_PHASE_VAL0

Phase 0 counting value. SDA to SCL rising edge timing.

The data setup time.

83090248

MM_CNT_VAL_PHH

Counting Value Phase High

0000FFFF

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

AAA

A

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

MM_CNT_PHASE_VAL3 MM_CNT_PHASE_VAL2

Type

RW

Rese

t

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit(s)

Name

Description

15:8

MM_CNT_PHASE_VAL3

Phase 3 counting value. SCL falling edge to SDA timing.

The data hold time.

7:0

MM_CNT_PHASE_VAL2

Phase 2 counting value. SDA to SCL falling edge timing.

The START condition period.

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Bit(s)

Name

Description

Table 2-13. I2C Master Counting Value Phase

• Set I2C Master clock (SCL)

o Set MM_CNT_PHASE_VAL0/1/2/3=w/x/y/z to set the SCL frequency to (26000 / (1+w+x+y+z)) kHz

2.3.1.9. Cortex-M4 UART clock setting

Cortex-M4 UART Clock (baud rate) supports 9.6, 19.2, 38.4, 115.2 kHz (divided from XTAL). And the baud rate

is a complex calculation. It’s recommended to use MediaTek API to configure UART to switch the baud rate.

2.3.2. Reset

MT76x7 has three global resets: XRESETN, CM4_RESETN and N9_RESETN. Figure 2-11 shows the module that

the reset signals are applied to.

Figure 2-11. Reset structure

XRESETN Reset Tree

(1) Cortex-M4 WDT and GPT module

(2) Cortex-M4 WIC module

(3) N9 WDT and GPT module

(4) N9 interrupt module

(5) AON module (top MISC logic always on during sleep)

Cortex-M4 and N9 Reset Tree Architecture

CM4_RESETN Reset Tree

Cortex-M4 MCU and all modules on Cortex-M4 bus other than

XRESETN reset tree

N9_RESETN Reset Tree

N9 MCU and all modules on Cortex-M4 bus other than XRESETN

reset tree

Chip Cold Reset Event

Or

Cortex-M4 Host Reset Event

Chip Cold Reset Event

Or

N9 Host Reset Event

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2.4. Application processor subsystem

The MCU subsystem consists of a 32-bit MCU, the AHB/APB bus matrix, internal RAM/ROM with ROM patch

function, the flash controller, and the system peripherals including Direct Memory Access (DMA) engine and

the General Purpose Timer (GPT).

2.4.1. CPU

MT76x7 features an ARM Cortex-M4 processor - the most energy efficient ARM processor available that

supports clock rates from 1MHz to 192MHz.

The MCU executes the Thumb-2 instruction set for optimal performance and code size, including hardware

division, single cycle multiplication and bit-field manipulation.

MT76x7 includes the memory protection unit (MPU) in Cortex-M4 MCU that provides memory protection

features. It can be used to detect unexpected memory access.

MT76x7 also includes floating point unit (FPU) in Cortex-M4 processor to support DSP related functionality.

2.4.2. Cache and tightly coupled memory (TCM)

2.4.2.1. General Description

MT76x7 has a cache for Cortex-M4 to improve the efficiency of the code and data fetch from the external

flash. The only cacheable memory region is the external flash.

MT76X7 also has a Tightly-Coupled-Memory (TCM), a zero-wait-state memory which is dedicated for Cortex-

M4 and can be accessed by Cortex-M4 exclusively. It is a memory space for a critical code such as interrupt

service routine that requires minimum latency execution. The DMA engines on AHB bus cannot access TCM.

The total size of cache memory and the TCM is 96KB. Four software-configurable options of differerent cache

size, TCM size and the cache associativity are offered. The user can select whichever option maximizes their

application performance.

The cache system has the following features:

• Configurable 1/2/4-way set associative (8KB/16KB/32KB)

• Each way has 256 cache lines with 8-word link size

• 20-bit tag memory: 19-bit high address and 1-bit valid bit

• 2-bit dirty memory: each dirty bit identifies the dirtiness of half cache line

The size of SRAM is 96KB. It can be configured to the following configuration

• 96KB TCM, no cache

• 88KB TCM, 8KB cache (1 way, direct mapped)

• 80KB TCM, 16KB cache (2 way set-associative)

• 64KB TCM, 32KB cache (4 way set-associative)

The configuration setting and the memory configuration are shown in Table 2-14.

Table 2-14. TCM and cache configuration

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0x0153_0000[9:8]

Functional Description

Start Address

End Address

00b 96KB TCM, no cache 0x0010_0000 0x0011_7FFF

01b 88KB TCM, 8KB cache, direct mapped 0x0010_0000 0x0011_5FFF

10b 80KB TCM, 16KB cache, 2-way set-associative 0x0010_0000 0x0011_3FFF

11b 64KB TCM, 32KB cache, 4-way set associative 0x0010_0000 0x0010_FFFF

The cache controller provides ways to perform cache operations including invalidate single/all cache lines and

flush one/all cache lines.

To improve the system performance, the cache controller can record the statistics of the cache hit count and

the number of cacheable memory access. Cache hit rate can be obtained by dividing the cache hit count by the

number of memory access.

MT76x7 core processor has been implemented with a TCM subsystem which consists of Core Cache and TCM

(tightly coupled memory). This TCM subsystem is placed between the MCU core and AHB bus interface, as

shown in Figure 2-12.

ARM Cortex-M4 Cache Controller

and MPU

AHB Bus

Interface

Serial Flash

Controller

TCM Cache

Way 1

Cache

Way 2

Cache

Way 2

Cache

Way 3

Figure 2-12. MCU, cache, TCM and AHB bus connectivity

TCM is a high-speed (zero wait state) dedicated memory accessed exclusively by MCU. Due to the latency

penalty when MCU accesses memory or peripherals through the on-chip bus, by moving timing critical code

and data into TCM, the performance of MCU can be enhanced, and the response to particular events can be

guaranteed.

Another method to enhance the MCU performance is the implementation of cache. In this case, the core

cache is a small block of memory containing a copy of small portion of cacheable data in the external memory.

If MCU reads a cacheable datum, the datum will be copied into the core cache. Once MCU requests the same

datum again, it can be obtained directly from the core cache (called cache hit) instead of fetching it again from

the external memory.

Consider the fact that accessing cache is much faster than accessing external memory through the bus TCM

sub-system. A faster instruction fetching can be obtained, and that leads to a higher IPC (Instruction Per Cycle),

which is a major factor in the evaluation of core performance. Since a large external memory maps to a small

cache, the cache can hold only a small portion of external memory. If MCU accesses a datum not found in the

cache (called cache miss), one cache line must be dropped (flushed), the required datum and its neighboring

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data are transferred from the external memory to cache (called cache line fill). Before cache line fill, an

important step to maintain data consistency between cache and external memory needs to be performed. This

important step is called “cache write back” (see later sections for details). In this design, a cache line consists

of eight words (8x32 bits) (will be introduced later). The best way to utilize TCM is maintaining the critical

instruction or data in TCM due to the advantage of TCM described above. After power-on reset, the boot

loader copies TCM contents from the external storage (e.g. flash) to the internal TCM. If necessary, MCU can

replace TCM contents with other data in the external storage during the runtime to implement a mechanism

such as “overlay”. TCM is also an ideal place to place stack data.

The sizes of TCM and cache can be set to one of the following 4 configurations:

• 64KB TCM, 32KB cache (4-way)

• 80KB TCM, 16KB cache (2-way)

• 88KB TCM, 8KB cache (1-way)

• 96KB TCM, 0KB cache (no cache)

Figure 2-13. Cache size and TCM settings

These different configurations provide flexibility for software to adjust and reach optimum TCM sub-system

performance.

The address mapping of these memories is shown here:

Table 2-15. TCM Address Spaces of Different Cache Size Settings

Cache size setting

TCM RAM identity

Used as

2’b00

(Total TCM = 96K, cache =

TCM RAM4(8K)

TCM4 (0x0011_6000 ~ 0x0011_7fff)

TCM RAM3(8K)

TCM3(0x0011_4000 ~ 0x0011_5fff)

64KB

8KB

TCM

cache

TCM

cache

TCM

cache

8KB

64KB

8KB

64KB

8KB

64KB

8KB

TCM

4-way cache

2-way cache

1-way cache

No cache

8KB

TCM

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Cache size setting

TCM RAM identity

Used as

0)

TCM RAM2(8K)

TCM2 (0x0011_2000 ~ 0x0011_3fff)

TCM RAM1(8K)

TCM1 (0x0011_0000 ~ 0x0011_1fff)

TCM RAM0(64K)

TCM0 (0x0010_0000 ~ 0x0010_ffff)

2’b01

(Total TCM =

88K, cache =

8K/1way)

TCM RAM4(8K)

Cache way 3

TCM RAM3(8K)

TCM3 (0x0011_4000 ~ 0x0011_5fff)

TCM RAM2(8K)

TCM2 (0x0011_2000 ~ 0x0011_3fff)

TCM RAM1(8K)

TCM1 (0x0011_0000 ~ 0x0011_1fff)

TCM RAM0(64K)

TCM0 (0x0010_0000 ~ 0x0010_ffff)

2’b10

(Total TCM =

80K, cache =

32K/2way)

TCM RAM4(8K)

Cache way 3

TCM RAM3(8K)

Cache way 2

TCM RAM2(8K)

TCM2 (0x0011_2000 ~ 0x0011_3fff)

TCM RAM1(8K)

TCM1 (0x0011_0000 ~ 0x0011_1fff)

TCM RAM0(64K)

TCM0 (0x0010_0000 ~ 0x0010_ffff)

2’b11

(Total TCM =

64K, cache =

32K/4way)

TCM RAM4(8K)

Cache way 3

TCM RAM3(8K)

Cache way 2

TCM RAM2(8K)

Cache way 1

TCM SRAM1(8K)

Cache way 0

TCM RAM0(64K)

TCM0 (0x0010_0000 ~ 0x0010_ffff)

2.4.2.2. Programming guide of cache size configuration

Change cache size must follow the steps listed below, to prevent the cache data from loss in the configuration

of cache size. At initialize, the cache size is set to 0.

1) Flush all cache lines

2) Invalidate all cache lines

3) Configure the tcm and cache size

The example code is as follows:

*(CACHE_OP) = 0x13;//flush all cache lines

*(CACHE_OP) = 0x3;//invalidate all cache lines

int org_cfg = *(CACHE_CON) //read original configuration

*(CACHE_CON)=(org_cfg & 0xffff_fcff) | (cache_size<<8) | 1; //update

cache size

2.4.2.3. Organization of cache

The cache TCM sub-system has the following features:

• Configurable 1/2/4-way set associative (8KB/16KB/32KB)

• Each way has 256 cache lines with 8-word line size (256*8*4 = 8KB)

• 20-bit tag memory: 19-bit high address and 1-bit valid bit

• 2-bit dirty memory (each dirty bit records the dirtiness of half cache line – 4 words)

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Each way of cache comprises two memories: tag memory and data memory. The tag memory stores each

line’s valid bit and tag (upper 19 bits of the address). The data memory stores line data. When MCU accesses

the memory, the address is compared to the contents of the tag memory. First, the line index (address bit

[12:5]) is used to locate a line in the tag memory. When a particular line is found in the tag memory, the upper

19 bits (address bit [31:13]), called tag, of the desired memory address are compared with the content of the

found tag line. If an match is found in both line address and tag address plus valid bit is 1, it is said a cache hit,

and the data from that particular cache way is returned to MCU. This process is illustrated here..

Figure 2-14. Cache Lookup

If most memory accesses are cache hit, MCU is able to acquire data immediately without wait states, and the

overall TCM sub-system performance will be higher. There are several factors that may affect the cache hit

rate:

• Cache size and the organization

The larger the cache size, the higher the hit rate. However, the hit rate will start to saturate when the cache

size is larger than a threshold size. Normally the size of 16KB and above and two or four way can achieve a

good hit rate.

• Program behavior

A

d

r

e

s

19

8

V

T

a

g

I

n

d

e

x

0

1

2

253

254

255

D

a

t

a

V

T

a

g

D

a

t

a

V

T

a

g

D

a

t

a

V

T

a

g

D

a

t

a

3

2

1

9

4

-

t

o

-

1

m

u

l

t

i

p

l

e

x

o

r

H

i

t

D

a

t

a

4

5

12

1

3

1

0

D

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If the TCM sub-system performs several tasks and switches frequently between tasks, the cache contents may

have to be flushed out frequently. This is due to the fact that each time a new task runs, the cache will hold its

data for a period of time for the opportunity of likely-be-used-again. However, the stored data might get

flushed out before being used again if the following task requires the data occupying the same cache entries.

Interrupts can cause program flow to change dynamically and reduce the benefit of cache. The interrupt

handler code and the data it processes may cause cache to flush out data used by the current task. Thus, after

returning from the interrupt handler to current task, the flushed data may need to be filled into the cache

again if it is required by the program routine. This will cause performance degradation.

To assist the software engineer to tune the TCM sub-system performance, the cache controller records the

cache hit count and number of cacheable memory accesses. The cache hit rate can be obtained from dividing

these two numbers.

The cache TCM sub-system also comprises a module called MPU (Memory Protection Unit). MPU prevents

illegal memory access and specifies which memory regions are cacheable or non-cacheable. Two fields in the

CACHE_CON register control the enabling of MPU functions. MPU has its own registers to define the memory

region and associated regions. These settings only take effect after the enabling bit in CACHE_CON is set to 1.

For more details on the settings, please refer to the MPU section of this design specification.

2.4.2.4. Theory of operations

1) Write-back/Write-through Configurable Cache

There are two different types of cache designs to maintain the data consistency: cache write-through and

cache write-back.

The write-back cache improves the performance especially when processors generate writes as fast as or

faster than the writes can be handled by the external memory. However, the implementation of write-back is

much harder than that of write-through. When a cache line is dirty, four or eight words will be written back to

the external memory at once, and this will certainly occupy significant bus bandwidth and therefore decrease

the overall efficiency. To solve this problem, a write buffer is necessary in the write-back implementation.

Once the writes get written into the write buffer, the processor can continue the execution.

For TCM sub-systems with large memory write latency, it is possible that the burst write of cache write-back

operation may cause large impact on the TCM sub-system performance. To deal with it, the software can

change the cache to write-through mode if necessary.

2) Write Back Implementation

When a cache hit happens on the write request, only the cache content will be modified, and the dirty bit will

be set (in contrast to write-through, write-through modifies both the contents of cache and the external

memory). Now the content of the cache location which is just modified is inconsistent with that in the external

memory. When the cache misses the read request, line fill will be performed, and a randomly selected cache

line will be replaced, but before that, the dirty bits of that selected cache line have to be checked for the

necessity of write-back. If the dirty bits are not set, line fill can proceed right away, and the selected cache line

can be simply flushed and replaced by a newly fetched line from the external memory which consists of the

requested data. On the other hand, if one of or both the dirty bits are set, write-back has to be performed

before line fill. In that case, half or the entire cache line are written into the write buffer. See the following

figure for summary:

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Figure 2-15. Cache miss/refill criterion

3) Write Buffer

The write buffer consists of address buffer, data buffer, HTRANS buffer, HSIZE buffer, HLOCK buffer, and

HBURST buffer. The write buffer is first-in-first-out (FIFO) design, and the depth of write buffer is eight words.

Since the outputs from code cache meet the AMBA format, the address buffer and data buffer are

independent, and the outputs of write buffer also meet AMBA format and are designed for pipelining.

4) Cache Operation

Upon power-on, the cache memory contains random values, and these numbers are useless for MCU. MCU

needs to flush out the cache content in each cache line before being utilized. The cache controller provides a

register which, when written, can operate on the cache memory to fulfill the necessary prerequisite

mentioned above (called cache operation). The operation involves:

• Invalidate one cache line

The user must give a memory address. If it is found within cache, that particular cache line containing the given

address will be invalidated. The invalidation is done by writing a 0 to the valid bit at the corresponding tag line.

Alternatively, the user can invalidate a cache line by specifying a set/way mapped to that cache line.

• Invalidate all cache lines

The user does not need to specify an address. The cache controller clears valid bits in all tag lines when this

operation is requested.

• Flush one cache line

The user must give a memory address. If it is found within cache and the dirty bit or bits are set, that particular

cache line containing the given address will be flushed into the write buffer. Alternatively, the user can

invalidate a cache line by specifying a set/way mapped to that cache line. This operation is not supported if the

cache is operating in the write-through mode.

• Flush all cache lines

The user needs not to specify an address. The cache controller flushes all the cache lines with the dirty bit or

bits set. This operation is not supported if the cache is operating in the write-through mode.

5) Cache Activity Summary

Table 2-16. Write-back Mode Cache R/W Action Summary

Op

Cacheable

Hit

Dirty

Action

Write Request

Write into

cache only

and set the

dirty bit

Write into

external

memory

Cache Hit

Cache Miss

Read Request

Read From

Cache

Check Dirty

Bits

Line Fill Cache Write

Back

CacheHit

Cache Miss

Dirty

Clean

Write back done

and write buffer contents

ONLY the last set of

write back words

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Op

Cacheable

Hit

Dirty

Action

W0~W3

W4~W7

Rd

N

d

D

d

Single read

Y

d

Return data, no stall

N

Line refill from bus using AHB WRAP8 burst

N

Y

• Evict half line to WBuf.

• Line refill from bus using AHB WRAP8 burst.

• Write back half line from WBuf using AHB INCR4 burst

write.

Y

N

Y

• Evict whole line to WBuf.

• Line refill from bus using AHB WRAP8 burst.

• Write back whole line from WBuf using AHB INCR8 burst

write.

Wr

N

d d

d

• Wait for WBuf space.

• Place write data into write WBuf and let ARM proceed

(CLKEN = 1). Stall ARM by one cycle.

Y

d

• Write to data SRAM; meanwhile set up corresponding dirty

bit

• Stall ARM by one cycle to avoid struct hazard.

N

d

• Wait for WBuf space.

• Place write data into write WBuf and let ARM proceed

(CLKEN=1). Stall ARM by one cycle.

Legend Y: yes, N: no, d: don’t care

Table 2-17. Write-through Mode Cache R/W Action Summary

Op

Cacheable

Hit

Action

Rd

N

d

Single read

Y

Return data, no stall

N

Line read from bus using AHB WRAP8 burst

Wr

N

d

Wait for WBuf space.

Place write data into write WBuf and let ARM proceed (CLKEN = 1).

Stall ARM by one cycle.

Y

N

Y

Write to data SRAM.

Wait for WBuf space.

Place write data into write WBuf and let ARM proceed (CLKEN = 1).

Stall ARM by one cycle.

Legend Y: yes, N: no, d: don’t care

2.4.2.5. MPU

MPU provides a protection mechanism and cacheable indication of memory, which features:

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• Protection settings

Determine if MCU can read/write a memory region. If the setting does not allow MCU’s particular access to a

memory address, MPU will stop the memory access and issue the “ABORT” signal to MCU, making it entering

the “abort” mode. The exception handler must then process the situation.

• Cacheable settings

Determine a memory region is cacheable or not. If cacheable, MCU will keep a small copy in its cache after

read accesses. If MCU requires the same data later, it can acquire it from the high-speed local copy, instead of

from the low-speed external memory.

The 4GB memory space is divided into 16 memory blocks with 256MB size each, i.e. MB0 ~ MB15. EMI takes

MB0 ~ MB3, TCM RAM takes MB4, TCM uses MB5, APB peripherals MB8. The characteristics of these memory

blocks are listed below:

• Read/write protection setting

• All MBs are determined by MPU.

• Cacheable setting

All MBs are determined by MPU. Note that the software should avoid making cache line access to the MB that

does not support burst read/write. Usually only MB0 ~ MB3, mapped to EMI, are set as cacheable regions.

APB Peripherals

MB3

~

MB0

MB4

MB5

Region 0

Region 1

Region 2

Region 3

Region 0 base address

Region 1 base address

Region 2 base address

Region 3 base address

non -

readable/writeable

readable/non

- writeable

no

n

-

readable/non

- writeable

readable/writeable

MB8

MB6 AHB Peripherals

TCM

TCM RAM

EMI

Figure 2-16: MPU protection setting example

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For example, the figure above illustrates the protection setting in each memory block. Five regions are defined

in the figure. Note that each region can be continuous or non-continuous to each other, and those address

ranges not covered by any region are set to be readable/writeable automatically. There is one restriction:

Different regions must not overlap.

The user can define maximum 16 regions in MB0 ~ MB4 and MB10. Each region has its own setting defined in a

32-bit register:

In chip simulation, three patterns are used to verify L1 cache, as shown in Table 2-18.

Table 2-18. Test patterns for whole chip simulation

Testlist

Testname

Description

mcu_cm4.list Cache_test Test l1cache function

mcu_cm4.list Cache_ram Test tcm ram read/write access

mcu_cm4.list Cm4_xip_flash • Cortex-M4 boot from rom, enable cache controller

• Jump to serial flash to execute XIP

2.4.2.6. Remapping

MT76x7 cache provides two register sets for thesoftware programmer to make the actual memory address

same as different CPU load/store target address. The following figure shows the scenario: The software sets

0x10xxxxxx to cacheable but 0x1Fxxxxxx to non–cacheable, but they are mapped to the same physical address.

Bank 0

Bank 1

vBank 0

vBank 1

0X1000000

0X11000000

0X1

E

00000

0x1

F

00000

0x1

F

0000000 à 0X10XXXXXXX

Memory Map Remap:

0x1

E

0000000 à 0X11XXXXXXX

ARM

Cache/MPU

Controller

Address Remap

Figure 2-17: Example Settings of Cache Remapping

To achieve this:

1) Set region begin with 0x1000_0000 to cacheable using MPU.

2) Set region begin with 0x1F00_0000 to non-cacheable using MPU.

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3) Set BASEADDR field in Remap EntryHi to 0x1F00_0000.

4) Set BASEADDR filed in Remap EntryLo to 0x1000_0000.

2.4.2.7. Register definitions

Module name: l1cache Base address: (+1530000h)

Address

Name

Width

Register Function

01530000

Cache_con

32

Cache general control register

01530004

CACHE_OP

32

Cache operation

01530008

cache_hcnt0L

32

Cache hit count 0 lower part

0153000C

cache_hcnt0U

32

Cache hit count 0 upper part

01530010

cache_Ccnt0L

32

Cacheable access count 0 lower part

01530014

cache_Ccnt0U

32

Cacheable access count 0 upper part

01530018

cache_hcnt1L

32

Cache hit count 1 lower

part

0153001C

cache_hcnt1U

32

Cache hit count 1 upper part

01530020

cache_Ccnt1L

32

Cacheable access count 1 lower part

01530024

cache_Ccnt1U

32

Cacheable

access count 1 upper part

01530028

way_replace_policy

32

Replace policy

0153002C

mpu_channel_en

32

MPU channel enable

01531000

NCREMAP_HI0

32

Remap Entry_HI0

01531004

NCREMAP_LO0

32

Remap Entry_LO0

01531008

NCREMAP_HI1

32

Remap Entry_HI1

0153100C

NCREMAP_LO1

32

Remap Entry_LO1

01540000~

0154003c

mpu_entry [n]

(n=0~15)

32

MPU N

-th channel control

01540040~

0154007c

mpu_End_entry [n]

(n=0~15)

32

MPU N

-th channel control

01530000

Cache_con

Cache general control register

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e CACHESI

ZE MD

RF

CN

TE

N1

CN

TE

N0

MP

DE

Fen

Mp

en MC

EN

Type

RW

Rese

t

0 0 0 0 0 0 0 0

Bit(s)

Name

Description

9:8

CACHESIZE

Selects cache size

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Bit(s)

Name

Description

00 No cache

01 8KB, 1

-way cache

10 16KB, 2

-way cache

11 32KB, 4

-way cache

7

MDRF

Enables early restart function

0

Disable

1 Enable

4

CNTEN1

Enables cache hit counter 1

If enabled, the cache controller will increment a 48

-bit counter by

one when a cache hit is detected. This number can provide a

reference in performance evaluation for tuning application

programs. This

counter increments only when the data are obtained

from MPU cacheable region 8 ~ 15.

0 Disable

1 Enable

3

CNTEN0

Enables cache hit counter 0

If enabled, the cache controller will increment a 48

-bit counter by

one when a cache hit is detected. This number

can provide a

reference in performance evaluation for tuning application

programs. This counter increments only when the data are obtained

from MPU cacheable region 0 ~ 7.

0 Disable

1 Enable

2

MPDEFen

Enables MPU default protection attribute

If enabled,

the default protection will be in privilege mode

read/write. The user mode is not accessible.

0 Disable

1 Enable

1

Mpen

Enables MPU comparison of read/write permission

setting

If disabled, MCU can access any memory without restriction. If

enabled, MPU will compare the address of MCU to MPU protection

setting. If the MCU accessed address falls into the restricted region,

MPU will stop this memory access and send an "ABORT" signal to

MCU. For details, please refer to the MPU part of this specification.

0 Dis

able

1 Enable

0

MCEN

Enables MPU comparison of cacheable/non-cacheable

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Bit(s)

Name

Description

setting

If disabled, MCU memory accesses are all non

-cacheable, i.e. they

will go through the AHB bus (except for TCM access). If enabled,

the setting in MPU will take effect. If MCU

accesses a cacheable

memory region, the cache controller will return the data in cache if

it is found in cache and will get the data through the AHB bus only

if a cache miss occurs. For details, please refer to the MPU part of

this specification.

0 Disable

1 Enable

01530004

CACHE_OP

Cache operation

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

TADDR[31:5]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

TADDR[31:5] OP[3:0] EN

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:5

TADDR[31:5]

Target address

This field contains the address of invalidation operation. If OP[3:0]

= 0010, TADDR[31:5] will be the address[31:5] of a

memory whose

line will be invalidated if it exists in the cache. If OP[3:0] = 0100,

TADDR[12:5] will indicate the set, while TADDR[19:16] indicate

which way to clear:

0001 way #0

0010 way #1

0100 way #2

1000 way #3

4:1

OP[3:0]

Operation

This field

determines which cache operations will be performed.

0001 invalidate all cache lines

0010 invalidate one cache line using address

0100 invalidate one cache line using set/way

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Bit(s)

Name

Description

1001 flush all cache lines

1010 flush one cache line using address

1100 flush one

cache line using set/way

0

EN

Enables command

This enabling bit must be written 1 to enable the command.

0 Does not enable

1 Enable

01530008

cache_hcnt0L

Cache hit count 0 lower part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Chit_cnt0[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

Chit_cnt0[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

Chit_cnt0[31:0]

Cache hit count 0

WRITE Write any value to CACHE_HCNT0L or CACHE_HCNT0U

clears CHIT_CNT0 to all 0.

READ Current counter value

0153000C

cache_hcnt0U

Cache hit count 0 upper part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

Chit_cnt0[47:32]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit(s)

Name

Description

15:0

Chit_cnt0[47:32]

Cache hit count 0

WRITE Write any value to CACHE_HCNT0L or CACHE_HCNT0U

clears CHIT_CNT0 to all 0.

READ Current counter value

01530010

cache_Ccnt0L

Cacheable access count 0 lower part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

CACC_cnt0[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CACC_cnt0[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

CACC_cnt0[31:0]

Cache access count 0

WRITE Write any value to CACHE_CCNT0L or CACHE_CCNT0U

clears CACC_CNT0 to all 0.

READ Current counter value

01530014

cache_Ccnt0U

Cacheable access count 0 upper part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CACC_cnt0[47:32]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

CACC_cnt0[47:32]

Cache access count 0

WRITE Write any value to CACHE_CCNT0L or CACHE_CCNT0U

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Bit(s)

Name

Description

clears CACC_CNT0 to all 0.

READ Current counter value

The best way to use CACHE_HCNT0 and CACHE_CCNT0 is to set

the initial value to 0 for both registers, enable both counters (set

CNTEN0 to 1),

run a portion of program to be benchmarked, stop

the counters and get their values. Therefore, during this period,

The cache hit rate value may help tune the performance of the

application program. Note that CHIT_CNT0 and CACC_CNT0 only

increment if the

cacheable attribute is defined in MPU cacheable

region lower half channels (i.e. channel 0 ~ 7 of the total 16

channels).

01530018

cache_hcnt1L

Cache hit count 1 lower part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Chit_cnt1[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

Chit_cnt1[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

Chit_cnt1[31:0]

Cache hit count

WRITE Write any value to CACHE_HCNT1L or CACHE_HCNT1U

clears CHIT_CNT1 to all 0.

READ Current counter value

0153001C

cache_hcnt1U

Cache hit count 1 upper part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

Chit_cnt1[47:32]

Type

RW

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Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

15:0

Chit_cnt1[47:32]

Cache hit count

WRITE

Write any value to CACHE_HCNT1L or CACHE_HCNT1U

clears CHIT_CNT1 to all 0.

READ Current counter value

01530020

cache_Ccnt1L

Cacheable access count 1 lower part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

CACC_CNT1[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CACC_CNT1[31:0]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

CACC_CNT1[31:0]

Cache access count 1

WRITE

Write any value to CACHE_CCNT1L or CACHE_CCNT1U

clears CACC_CNT1 to all 0.

READ Current counter value

01530024

cache_Ccnt1U

Cacheable access count 1 upper part

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CACC_CNT1[47:32]

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

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Bit(s)

Name

Description

15:0

CACC_CNT1[47:32]

Cache access count 1

WRITE

Write any value to CACHE_CCNT1L or CACHE_CCNT1U

clears CACC_CNT1 to all 0.

READ Current counter value

01530028

way_replace_policy

Replace policy

00000001

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

Re

pla

ce

pol

icy

Type

RW

Rese

t

1

Bit(s)

Name

Description

0

Replace policy

0

Using way_counter which counts in every cycle to make it more

like random.

1

Replace the lower way first if that way is not valid. If all ways are

valid, replace

policy is random.

0153002C

mpu_channel_en

MPU channel enable

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CH15~CH0

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

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Bit(s)

Name

Description

15:0

CH15~CH0

Enables/Disables the associated region

0 Disable the region setting

1 Enable the region setting

01531000

NCREMAP_HI0

Remap Entry_HI0

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

BASEADDR size EN

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:9

BASEADDR

Base address of this region

5:1

size

Size of this region. Actual size = 2^(size +9) Bytes, max

size is 256MB.

0

EN

Enables this region

0 Disable

1 Enable

01531004

NCREMAP_LO0

Remap Entry_LO0

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0

Bit(s)

Name

Description

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Bit(s)

Name

Description

31:9

BASEADDR

This register sets up the mapped address base of CPU

access which hits NC

-Remap Entry0_HI.

01531008

NCREMAP_HI1

Remap Entry_HI1

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

BASEADDR size EN

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:9

BASEADDR

Base address of this region

5:1

size

Size of this region. Actual size = 2^(size +9) Bytes, max

size is 256MB.

0

EN

Enables this region

0 Disable

1 Enable

0153100C

NCREMAP_LO1

Remap Entry_LO1

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0

Bit(s)

Name

Description

31:9

BASEADDR

This register sets up the mapped address base of CPU

access which hits NC

-Remap Entry1_HI. Note that the

base and size settings in 2 EntryHi cannot be overlapped.

Otherwise, the resultant mapped address will be

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Bit(s)

Name

Description

undefined.

01540000~

0154003C

mpu_entry

[n](n=0~15)

MPU N-th channel control

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

BASEADDR C ATTR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:9

BASEADDR

start addr of MPU

8

C

Cacheable Attribute, Cacheable setting and non-cacheable

setting are similar to cache protection settings .

0: non

-cacheable

1: cacheable

Note that each region can be continuous or non

-continuous to each

other. For those address ranges not covered by any region in the

MPU cacheable settings are set to be uncacheable automatically.

There is one restriction: Different regions must

not overlap.

7:5

ATTR

Protection modes

3'd0: no protection

3'd1:Only R/W for privilege mode access

3'd2: Only R/W for privilege mode access; read access to user mode

3'd3:Only R/W for privilege mode access; write access to user mode

3'd4:Only read for p

rivilege/user mode

3'd5:Both R/W are forbidden

3'd6: Privilege mode read only; no access to user mode

01540040~

0154007C

mpu_End_entry

[n](n=0~15)

MPU N-th channel control

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

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Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

BASEADDR

Type

RW

Rese

t

0 0 0 0

Bit(s)

Name

Description

31:12

BASEADDR

END addr of MPU

2.4.3. Bus fabric

MT76x7 implements AHB/APB bus fabric to connect the MCU, memory, IO peripherals and the radio

subsystem.

• ILM/DLM: Instruction Local Memory / Data Local Memory, the zero-wait-state local memory for Radio

MCU.

• Wi-Fi HIF: The data interface to Wi-Fi Packet switch engine.

• Bluetooth FIFO I/F: The control/data interface to Bluetooth subsystem.

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ARM Cortex M4

Cache

Controller TCM/Cache

(96KB)

Cortex-M4 AHB bus

Generic DMA

SPI flash

APB

bridge

APB2 bus

Wi-Fi HIF

UART1 UART2 I2C-1 I2C-2 SPI-M

I2S

Bluetooth

FIFO I/F AUX

ADC

TOP &

CM4

CONFIG

GPT WDT

N9

Interface to radio subsystem

Peripherals

APB

bridge

SYSRAM_

CM4

(256KB)

APB1 bus

ILM/DLM

PWM

XIP

AHB mux

ICODEDCODESYSTEM

Asyncrhrous AHB-2-

AHB bridge

(N9 bus to CM4 bus)

Asyncrhrous AHB-2-

AHB bridge

(CM4 bus to N9 bus)

APB

bridge

APB0 bus

TCM ROM

N9 AHB bus

GDMA

CONFIG

Crypto

Engine

Figure 2-18. Cortex-M4 subsystem – bus fabric

The AHB bus arbitration adopts round-robin scheme.

The N9 subsystem and Cortex M4 subsystem are in different clock domains, so the asynchronous bridges are

inserted in the bus fabric. N9 has the ability to (but would be rarely used) all the Cortex-M4 peripherals.

2.4.4. Serial flash controller

2.4.4.1. General Description

MT76X7 features a serial flash controller that can support the serial flash with the read mode of (JEDEC)

standard SPI mode, SPI-Quad mode, QPI (Quad Peripheral Interface) mode, Dual IO mode, and Dual-Output

mode.

The frequency of the serial clock rate is up to 64MHz. That provides 256Mbps equivalent throughput on flash

when SPI-quad mode or QPI mode is used.

Table 2-19. Flash controller support read mode

Read Mode Description

SPI 1xIO for receiving command and address, 1xIO for output data

SPI-Quad 1xIO for receiving command, 4xIO for address, 4xIO for output data

QPI 4xIO for receiving command/address and output data

Dual-IO 1xIO for command, 2xIO for address and output data

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Read Mode Description

Dual-Output 1xIO for receiving command, 2xIO for address and output data

The Serial Flash Controller Supports Two Operation Modes:

 Direct read mode, which supports a high-throughput direct-access through AHB bus

 Macro access mode, which supports flash access with arbitrary command and is through APB bus.

2.4.4.2. Block diagram

Direct Read

Serial

Flash

MAC R/W

GPRAM

APB

SF+0000h AHB

0000_0000

SCK

SCS#

SI

SO

WP

HOLD

Bridge

Figure 2-19. Serial flash controller block diagram

See Figure 2-19 for the block diagram of MT7697 serial flash controller. There are two exclusive control paths,

“Direct Read” and “Macro R/W”, and each path can only be enabled to access a device once at a time. Direct

Read supports convenient high-speed serial nor-flash code fetching through AHB and can be used for boot-up

without any register setting. Macro R/W supports flexible command sequence GPRAM (general-purpose

SRAM) through APB.

In Figure 2-20, the SF_TOP in the system block diagram is shown with red line block. The SF_TOP have 2 AHB

interfaces and 1 APB interface. These interfaces are listed as follows:

• AHB interface (direct read): base address = 0x3000_0000, which is connected to AHB layer 5 and used

for dma_cm4.

• AHB interface (direct read): base address = 0x1000_0000, which is connected to cache controller and

used for cm4 only.

• APB interface (mac mode): base address = 0x8307_0000, which is connected to APB layer 2 and

programmed for cm4.

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Figure 2-20. The red line block is the SF_TOP in MCUSYS_CM4.

2.4.4.3. Serial Flash related waveform

1) Direct Read for SPI

Figure 2-21. Example for direct read for SPI mode

2) Quad I/O Read

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Figure 2-22. Example for quad I/O read in SPI mode

Figure 2-23. Example for quad I/O read in QPI mode

SIO [3:0] = {pad_hold, pad_wp, pad_sin0, pad_so0}

H0 = MSB of output data 0

L0 = LSB of output data 0

A5 includes address bit 23 to bit 20. A4 includes address bit 19 to bit 16.

A3 includes address bit 15 to bit 12. A2 includes address bit 11 to bit 8.

A1 includes address bit 7 to bit 4. A0 includes address bit 3 to bit 0.

3) Direct Read Behavior Waveform

• Direct Read Mode (SPI)

Quad I/O Read --- E7H (not QPI)

sf_clk

sf_cs

sck

sf_hold

sf_wp

sf_so/sio1

sf_si/sio0

E7h

bit 23

bit 22

bit 21

bit 20

bit 19

bit 18

bit 17

bit 16

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 3

bit 2

bit 1

bit 0

bit 7

bit 6

bit 5

bit 4

command

24 bit Address

Dummy

Cycles

Data Out

bit 3

bit 2

bit 1

bit 0

bit 3

bit 2

bit 1

bit 0

bit 7

bit 6

bit 5

bit 4

bit 7

bit 6

bit 5

bit 4

Quad I/O Read command --- command = EBH (QPI)

sf_clk

sf_cs

sck

SIO(3:0)

e

b

A5

A4

A3

A2

A0

A1

H0

L0

H1

L1

command

24 bit Address

Dummy

Cycles

Data Out

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hclk_ck

sf_clk

sr_req

hready

srack

flash_dle

sf_cs

sck

pad_sin0

pad_so0

SF CS EXT CYC

6 bit command

24 bit address

dummy

cycles

0B

hclk_ck

sf_clk

sr_req

hready

srack

flash_dle

sf_cs

sck

pad_sin0

pad_so0

32 cycles

data 1 ~ data 4

data 5 ~ data 8

data 9 ~ data 12

sync clock

Figure 2-24. Direct read waveform for SPI mode

• Direct Read Mode (QPI)

Overhead transaction cycles (from AHB sending request to AHB finishing reading data)

= (1 request cycle + SF_CS_EXT_CYC) + (2 command cycles) + (6 address cycles) + (dummy cycles ) +

6*(fSFC/fAHB) synchronizing overhead + 2 latency cycles + (8*number of transfers) + AHB_REQ_1TLH_EN +

DEL_LATCH_LATENCY+FIFO_RD_LTC

= SF_CS_EXT_CYC + AHB_REQ_1TLH_EN + DEL_LATCH_LATENCY + FIFO_RD_LTC + (8*number of transfers) +

dummy cycles + 11 cycles + 6*(fSFC/fAHB) synchronizing overhead,

(cycle period = sfc cycle period)

hclk_ck

sf_clk

sr_req

hready

srack

flash_dle

sf_cs

sck

pad_sin0

pad_so0

32 cycles

Last 4 data

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 







+

=otherwise , 1 4 / Byte Data ReadFlash Serial

4by divided becan Bytes Data ReadFlash Serial if , 4 / Byte Data ReadFlash Serial

Transfer ofNumber

For example, SF_CS_EXT_CYcd C is 2 cycles, AHB_REQ_1TLH_EN = 0, DEL_LATCH_LATENCY = 1, FIFO_RD_LTC =

2, dummy cycle = 6 cycles, serial flash read data byte is 32, serial flash frequency is 78MHz, and AHB frequency

is 52MHz.Therefore, the transaction cycles is 2 + 0 + 1 + 2 + 8*8 + 6 + 11 + 6*(78/52) = 95 cycles

• Direct Read Mode (SPI-Quad with serial flash device not supporting wrap)

Overhead transaction cycles (from AHB sending request to AHB finishing reading data)

= (1 request cycle + SF_CS_EXT_CYC) + (2 command cycles) + (6 address cycles) + (dummy cycles ) +

6*(fSFC/fAHB) synchronizing overhead + 2 latency cycles + (8*number of transfers) + AHB_REQ_1TLH_EN +

DEL_LATCH_LATENCY + FIFO_RD_LTC + 2*(number of transfers data read from pre-fetch buffer)*(fSFC/fAHB)

synchronizing overhead

= SF_CS_EXT_CYC + AHB_REQ_1TLH_EN + DEL_LATCH_LATENCY + FIFO_RD_LTC + (8*number of transfers) +

dummy cycles + 11 cycles + 6*(fSFC/fAHB) + 2*(number of transfers data read from pre-fetch

buffer)*(fSFC/fAHB) synchronizing overhead,

(cycle period = sfc cycle period)









+

=otherwise , 1 4 / Byte DataRead Flash Serial

4by divided becan Bytes DataRead Flash Serial if , 4 / Byte DataRead Flash Serial

Transfer ofNumber

For example, SF_CS_EXT_CYC is 4 cycles, AHB_REQ_1TLH_EN = 1, DEL_LATCH_LATENCY = 1, FIFO_RD_LTC = 2,

dummy cycle = 6 cycles, serial flash read data byte is 32, serial device not supporting wrap, the first access data

from bus is the last 4 bytes of the 32-byte data, serial flash frequency is 78MHz, and AHB frequency is 52MHz.

Therefore, the transaction cycles is 2 + 1 + 1 + 2 + 8*8 + 6 + 11 + 6*(78/52) + 2*[(32-4)/4] = 110 cycles

• Macro Mode (QPI)

Overhead transaction cycles (from AHB sending request to Serial flash controller finishing reading data from

serial flash device)

= 6 cycles (from AHB sending request through APB to Serial Flash controller) + (Serial Flash Macro input data

length + Serial Flash Macro Output data length)*2 * (fAPB/fSFC) + DEL_LATCH_LATENCY * (fAPB/fSFC) + 2

latency cycles

(cycle period = APB cycle period)

For example: Serial flash macro input data length = 3, output data length = 2, DEL_LATCH_LATENCY =1, serial

flash frequency is 78MHz, and APB frequency is 52MHz. Therefore, the transaction cycle is

6+(3+2)*2*(52/78)+1*(52/78)+ 2 = 6 + 7 + 1 + 2 = 16 cycles

Signal explanation:

hclk: AHB clock SIO[3:0]={HOLD, WP, SO, SI}

sf_clk: serial flash controller clk flash_dle: Indicates the serial flash buffer is full

srreq: AHB slave read request sfbuf_count: Serial flash buffer counter

ahb_hsel: AHB hsel signal A5: Address bit 23 to bit 20

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Signal explanation:

ahb_hready: AHB hready signal A4: Address bit 19 to bit 16

srack: AHB slave read ack signal A3: Address bit 15 to bit 12

haddr: AHB HADDR A2: Address bit 11 to bit 8

hrdata: AHB HRDATA A1: Address bit 7 to bit 4

sf_req: Serial flash request A0: Address bit 3 to bit 0

sf_cs: Serial flash chip select H0: MSB of output data 0

sck: Serial flash clock L0 = LSB of output data 0

SIO[3:0]: Serial flash quad io

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Figure 2-25. Direct read waveform for QPI mode

2.4.4.4. Programming guide

1) Read Back Register after Value Change

Due to the bridge latency when setting up APB registers (see Figure 2-19), registers affecting AHB such as

SF_DIRECT_CTL may be unstable if AHB is accessed immediately. Therefore, it is suggested that after changing

AHB related registers, e.g. SF_DIRECT_CTL, the registers should be read back again before accessing AHB.

2) Serial Flash Command Sequence Control Example

SF indicates the APB interface base address = 0x8307_0000.

Address Register name R/W Value Loop Flash

command

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA W 0x00000006 WE

(Write Enable)

SF + 0004h SF_MAC_OUTL W 0x00000001

SF + 0008h SF_MAC_INL W 0x00000000

SF + 0000h SF_MAC_CTL W 0x0000000C

SF + 0000h SF_MAC_CTL R [1] = 1, [0] = 0 loop

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA W 0x452301D8 BE

(Block Erase)

SF + 0004h SF_MAC_OUTL W 0x00000004

SF + 0008h SF_MAC_INL W 0x00000000

SF + 0000h SF_MAC_CTL W 0x0000000C

SF + 0000h SF_MAC_CTL R [1] = 1, [0] = 0 loop

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA W 0x00000005 RDSR

(Read Status

Register)

SF + 0004h SF_MAC_OUTL W 0x00000001

SF + 0008h SF_MAC_INL W 0x00000001

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Address Register name R/W Value Loop Flash

command

SF + 0000h SF_MAC_CTL W 0x0000000C loop

SF + 0000h SF_MAC_CTL R [1] = 1, [0] = 0 loop

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA R [8] = 0 (flash WIP)

SF + 0800h SF_GPRAM_DATA W 0x00000006 WE

(Write Enable)

SF + 0004h SF_MAC_OUTL W 0x00000001

SF + 0008h SF_MAC_INL W 0x00000000

SF + 0000h SF_MAC_CTL W 0x0000000C

SF + 0000h SF_MAC_CTL R [1] = 1, [0] = 0 loop

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA W 0x45230102 PP

(Page Program)

SF + 0804h SF_GPRAM_DATA W 0x78563412

SF + 0808h SF_GPRAM_DATA W 0xddccbbaa

SF + 0004h SF_MAC_OUTL W 0x0000000C

SF + 0008h SF_MAC_INL W 0x00000000

SF + 0000h SF_MAC_CTL W 0x0000000C

SF + 0000h SF_MAC_CTL R [1] = 1, [0] = 0 loop

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA W 0x00000005 RDSR

(Read Status

Register)

SF + 0004h SF_MAC_OUTL W 0x00000001

SF + 0008h SF_MAC_INL W 0x00000001

SF + 0000h SF_MAC_CTL W 0x0000000C loop

SF + 0000h SF_MAC_CTL R [1] = 1, [0] = 0 loop

SF + 0000h SF_MAC_CTL W 0x00000008

SF + 0800h SF_GPRAM_DATA R [8] = 0 (flash WIP)

2.4.4.5. Register definitions

Module name: sf_top Base address: (+83070000h)

Address

Name

Width

Register Function

83070000

SF_MAC_CTL

32

Serial flash macro R/W control

83070004

SF_DIRECT_CTL

32

Serial flash direct read setting

83070008

SF_MISC_CTL1

32

Serial flash clock MISC controller setting 1

83070010

SF_MAC_OUTL

32

Serial flash

macro output data length

83070014

SF_MAC_INL

32

Serial flash macro input data length

8307001C

SF_STA2_CTL

32

Serial flash static control setting 2

83070020

SF_DLY_CTL1

32

Serial flash delay controller setting 1

83070024

SF_DLY_CTL2

32

Serial flash delay controller setting 2

83070028

SF_DLY_CTL3

32

Serial flash delay controller setting 3

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Address

Name

Width

Register Function

83070044

SF_MISC_CTL3

32

Serial flash MISC control setting 3

83070080

SF_PERF_MON1

32

Serial flash performance monitor 1

83070084

SF_PERF_MON2

32

Serial flash

performance monitor 2

83070088

SF_PERF_MON3

32

Serial flash performance monitor 3

8307008C

SF_PERF_MON4

32

Serial flash performance monitor 4

83070090

SF_PERF_MON5

32

Serial flash performance monitor 5

83070094

SF_PERF_MON6

32

Serial flash performance monitor 6

83070098

SF_PERF_MON7

32

Serial flash performance monitor 7

8307009C

SF_PERF_MON8

32

Serial flash performance monitor 8

830700A0

SF_PERF_MON9

32

Serial flash performance monitor 9

830700A4

SF_PERF_MON10

32

Serial flash performance monitor 10

83070800~

8307089c

SF_GPRAM_DATA [n]

(n=0~39)

32

Serial flash macro R/W memory data (160

bytes)

83070000

SF_MAC_CTL

Serial flash macro R/W control

00010000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

RE

LE

AS

E_

MA

C

Type

RW

Rese

t

1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

AB

OR

T_

CL

R

SF

_A

BO

RT

SF_ABOT

_REQ_SR

C

SF

_IR

Q_

EN

SF

_IR

Q_

AC

K

H

W_

QPI

MA

C_

MA

SK

_O

P

MA

C_

MA

SK

MA

C_

XI

O_

SE

L

SF

_M

AC

_E

N

SF

_T

RI

G

WI

P_

RE

AD

Y

WI

P

Type

RU

RW

RU

RW

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

16

RELEASE_MAC

Prevents hanging the AHB bus. As the serial flash enters

the MAC mode, it will raises

SF_ABORT to "high" for the

MCU to interrupt the current transaction and check if the

AHB bus is hanged. If Release_MAC is set to 1, SF_ABORT

will not be raised to 1. In the DEBUG develop segment, set

this bit to 1 when the serial flash enters the macro mod

e,

and SF_ABORT will not be raised to 1. The serial flash will

continue the next operation event though the data read

are wrong.

0 Disable

1 Enable

15

ABORT_CLR

Clears serial flash abortion. As we would like to exit the

serial flash abortion status, ABORT_CLR must be set to 1

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Bit(s)

Name

Description

to clear the SF_ABORT status and then set ABORT_CLR

back to 0 to detect another serial flash abortion.

0 Disable

1 Enable

14

SF_ABORT

Serial flash abortion status register. As the AHB bus

raises request in the MAC mode, it will cause the abortion

of the serial flash controller.

0 Does not abort

1 Abort

13:12

SF_ABOT_REQ_SRC

Request source of serial flash abortion

00 Does not abort

01 Abortio

n is caused by MCU.

10 Abortion is caused by ALICE.

9

SF_IRQ_EN

Serial flash interrupt enable during serial flash abortion

0 Disable

1 Enable

8

SF_IRQ_ACK

Serial flash interrupt acknowledged signal

0 Non

-acknowledged

1 Acknowledged

7

HW_QPI

AHB mode for QPI/SPI setting

0 SPI

1 QPI

6

MAC_MASK_OP

Serial flash hardware DIRECT/MAC mode auto switch

setting. If setting MAC_MASK_OP=1 then trigger

SF_TRIG=1, hardware module will auto switch to MAC

mode until MAC mode operation finished.

0 Disable

1 Enable

5

MAC_MASK

Serial flash software DIRECT/MAC mode switch setting. If

MAC_MASK is set to 1, the hardware will switch to the

MAC mode manually and will not permit any DIRECT

mode access until MAC_MASK=0. It is suggested to run

MAC mode in internal sysram code

if MAC_MASK = 1 by

software setting.

0 Disable

1 Enable

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Bit(s)

Name

Description

4

MAC_XIO_SEL

MAC mode for QPI/SPI setting

0 SPI

1 QPI

3

SF_MAC_EN

Switches the serial flash control to update the macro.

Please set up this bit before triggering the update macro

(It is suggested

to run MAC mode in internal sysram code

due to DIRECT/MAC cannot run at the same time.

Another way to switch to hardware auto switch mode by

setting up MAC_MASK_OP)

0 Disable

1 Enable (Direct read is forbidden when SF_MAC_EN = 1)

2

SF_TRIG

Serial flash write macro trigger

0 Disable

1 Enable (Fill command sequence I/O length before SF_TRIG)

1

WIP_READY

WIP register status ready for access. WIP_READY exits

due to asynchronous latency delay before flash responds

to WIP

0 WIP not ready for read

1 WIP ready fo

r read (Check if WIP_READY = 1 before the next

command sequence)

0

WIP

Serial flash command write in process

0 Flash update finished (Check if WIP = 0 before the next

command sequence)

1 Not finished

83070004

SF_DIRECT_CTL

Serial flash direct read setting

0B0B7710

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

SF_CTRL_CMD1 SF_CTRL_CMD2

Type

RW

Rese

t

0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e CMD1_DUMMY_CYC CMD2_DUMMY_CYC SF_READ_MOD

E

CM

D2

_E

XT

_A

DD

R_

EN

SF

_C

MD

2_

EN

CM

D1

_E

XT

_A

DD

R_

EN

SF

_Q

PI_

EN

Type

RW

Rese

t

0 1 1 1 0 1 1 1 0 0 1 0 0 0 0

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Bit(s)

Name

Description

31:24

SF_CTRL_CMD1

Serial flash DIRECT read mode command 1 register

setting for DUAL/QIO/QPI

mode.

*value = efuse{0x102[7:0]}

23:16

SF_CTRL_CMD2

Serial flash DIRECT read mode command 2 register

setting for DUAL/QIO/QPI mode.

*value = efuse{0x103[7:0]}

15:12

CMD1_DUMMY_CYC

Serial flash read mode dummy cycles for SF_CTRL_CMD1

setting

4'b0000 1T

4'b0001 2T

4'b 0010 3T

4'b 0011 4T

4'b 0100 5T

4'b 0101 6T

4'b 0110 7T

4'b 0111 8T

4'b 1000 9T

4'b 1001 10T

4'b 1010 11T

4'b 1011 12T

4'b 1100 13T

4'b 1101 14T

4'b 1110 15T

4'b 1111 16T

*value = efuse{0x104[7:4]}

11:8

CMD2_DUMMY_CYC

Serial flash read mode dummy cycles for SF_CTRL_CMD2

setting

4'b 0000 1T

4'b 0001 2T

4'b 0010 3T

4'b 0011 4T

4'b 0100 5T

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Bit(s)

Name

Description

4'b 0101 6T

4'b 0110 7T

4'b 0111 8T

4'b 1000 9T

4'b 1001 10T

4'b 1010 11T

4'b 1011 12T

4'b 1100 13T

4'b 1101 14T

4'b 1110 15T

4'b 1111 16T

*value =

efuse{0x104[3:0]}

6:4

SF_READ_MODE

Selects serial flash read mode

3'b000 Normal read mode

3'b 001 Fast read mode

3'b 010 Dual output mode

3'b 011 Dual I/O mode

3'b 111 Quad I/O mode

3

CMD2_EXT_ADDR_EN

Enabled to send 4-byte address as using SF_CTRL_CMD2

0 Disable

1 Enable

2

SF_CMD2_EN

Enables SF_CTRL_CMD2 command. When SF_CMD2_EN

is set to 1, the serial flash controller will use the

SF_CTRL_CMD2 command to read data as accessing

address exceeds 24 bits.

0 Disable

1 Enable

1

CMD1_EXT_ADDR_EN

Enabled extend address mode for SF_CTRL_CMD1.

0 Disable

1 Enable

0

SF_QPI_EN

Serial flash QPI enable in QIO mode. Set up this bit with

QIO = 1 (SF_READ_MODE = 3'b111)

0 Disable

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Bit(s)

Name

Description

1 Enable

83070008

SF_MISC_CTL1

Serial flash clock MISC controller

setting 1

B2C00000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e SF_CS_EXT_CYC fifo_rd_lt

c

NO

_R

EL

OA

D

FIF

O_

MA

CR

O_

RS

T

CS

_E

XT

_C

YC

_O

PT

_E

N

fou

rta

p_f

ifo

_en

ahb

_R

EQ

_1T

Lh

_E

N

SF

_D

OU

BL

E_

SY

NC

SF

_S

YN

C_

EN

RE

G_

AD

DR

_S

YN

C_

SE

L

Type

RW

Rese

t

1 0 1 1 1 0 1 1 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SFI

O_

EN

_S

EL

CS_SETU

P_LTC

SF

_R

EQ

_I

DL

E

CH

2_

B2

S

SF

_F

BC

LK

_S

EL

SM

PC

K_I

NV

OU

TC

K_I

NV

DEL_LAT

CH_LATE

Ncy

Type

RW

RU

RW

Rese

t

0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:28

SF_CS_EXT_CYC

CS pin pulled from high to low extension cycles. Default:

12 cycles

4'b0000 1 cycle

4'b0001 2 cycles

4'b0010 3 cycles

4'b0011 4 cycles

4'b0100 5 cycles

4'b0101 6 cycles

4'b0110 7 cycles

4'b0111 8 cycles

4'b1000 9 cycles

4'b1001 10 cycles

4'b1010 11 cycles

4'b1011 12 cycles

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Bit(s)

Name

Description

4'b1100 13 cycles

4'b1101 14 cycles

*value = efuse{0x105[7:4]}

25:24

fifo_rd_ltc

4 Tap FIFO read latency

*value = efuse{0x105[1:0]}

23

NO_RELOAD

NO_RELOAD setting: RELOAD function is that the serial

flash controller keeps the CS pin low, and the CLK pin

keeps pending after the pre

-fetch buffer is full. If the next

access address continues, the previous address will then

start generating CLK to access the next data with

out any

command/address overhead time suffer to gain better

bandwidth usage.

0 CMD/ADDR will not be issued if the next access address

continues the previous address.

1 CMD/ADDR will be re

-issued.

*value = efuse{0x106[7]}

22

FIFO_MACRO_RST

Serial flash IO module reset control

0 Disable reset

1 Enable reset

21

CS_EXT_CYC_OPT_EN

Enables CS extension cycle optimization. In the DIRECT

READ mode, the CS extension cycle will be added before

each transaction. However, before receiving a new

request, CS might have

been pulled up. If

CS_EXT_CYC_OPT_EN is set to 1, serial flash controller

will base on the CS pulling up cycle before the new request

to reduce the CS extension cycle time .

0 Disable

1 Enable

*value = efuse{0x106[5]}

20

fourtap_fifo_en

Enables 4 Tap FIFO

0 Disable

1 Enable

*value = efuse{0x106[4]}

19

ahb_REQ_1TLh_EN

Enables serial flash controller delay 1T to latch AHB

request

0 No delay

1 Delay 1T to latch AHB request

*value = efuse{0x106[3]}

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Bit(s)

Name

Description

18

SF_DOUBLE_SYNC

Enables serial flash double sync. If the frequency of serial

flash is at the twice of BUS frequency, and we would like

the serial flash controller to work in the synchronous

mode, set SF_SYNC_EN to 1 and SF_DOUBLE_SYNC to 1

0 Disable

1 Enable

*value = efuse{0x106[2]}

17

SF_SYNC_EN

Enables serial flash synchronous mode

0 Asynchronous mode

1 Synchronous mode

*value = efuse{0x106[1]}

16

REG_ADDR_SYNC_SEL

SF address select

0 Synchronous mode

1 Asynchronous mode

14

SFIO_EN_SEL

Serial flash IO PAD Enable signal align with clock positive

edge

select

0 Disable

1 Enable

*value = efuse{0x107[6]}

13:12

CS_SETUP_LTC

Serial flash/CS setup time latency. Set up CS_SETUP_LTC

to increase the /CS setup time. Default /CS setup time for

both MAC and DIRECT READ mode is 1.5 serial flash clock

period.

2'b00

Does not increase serial flash /CS setup time

2'b01 Increase 1T for /CS setup time

2'b10 Increase 2T for /CS setup time

2'b11 Increase 3T for /CS setup time

*value = efuse{0x107[5:4]}

8

SF_REQ_IDLE

Serial flash controller processing transaction status

reg

ister

0 Transaction is being processed.

1 Idle

6

CH2_B2S

Channel 2 of serial flash access switch to single data

access mode for priority arbitration behavior setting. In

MT7637, CPU can access the serial flash through channel

2. If CH2_B2S = 1, the

arbitration will switch to another

agent (MCU) access after every CH2 single access.

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Bit(s)

Name

Description

0 Disable

1 Enable

*value = efuse{0x108[6]}

5

SF_FBCLK_SEL

Serial flash feedback clock selection setting

0 Use non

-feedback clock

1 Use feedback clock for serial flash

*v

alue = efuse{0x108[5]}

4

SMPCK_INV

Sample clock inverse for read data input

0 No inverse

1 Inverse

*value = efuse{0x108[4]}

3

OUTCK_INV

Output clock inverse bit

0 No inverse

1 Inverse

*value = efuse{0x108[3]}

1:0

DEL_LATCH_LATENcy

Selects serial flash latch delay latency

2'b00 Not delay

2'b01 Delay 1T to latch serial flash data

2'b10 Delay 2T to latch serial flash data

2'b11 Delay 3T to latch serial flash data

*value = efuse{0x108[1:0]}

83070010

SF_MAC_OUTL

Serial flash macro output data length

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

MAC_OUT_LENGTH

Type

RW

Rese

t

0 0 0 0 0 0 0 0

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Bit(s)

Name

Description

7:0

MAC_OUT_LENGTH

Serial flash write data length, 1 ~ 160 bytes

83070014

SF_MAC_INL

Serial flash macro input data length

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

MAC_IN_LENGTH

Type

RW

Rese

t

0 0 0 0 0 0 0 0

Bit(s)

Name

Description

7:0

MAC_IN_LENGTH

Serial flash read data length, 1 ~ 160 bytes

8307001C

SF_STA2_CTL

Serial flash static control setting 2

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

KE

EP

_R

EA

D_

SE

TTI

NG

Type

RW

Rese

t

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

Type

Rese

t

Bit(s)

Name

Description

31

KEEP_READ_SETTING

Keep Direct Read mode setting after watch-dog reset

If KEEP_READ_SETTING is set to 1,

the content of

SF_DIRECT_CTL and SF_MISC_CTL2 can only be reset by power

-

on reset and will not be cleared after the watch

-dog reset.

0 Disable

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Bit(s)

Name

Description

1 Enable

83070020

SF_DLY_CTL1

Serial flash delay controller setting 1

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

SFIO3_OUT_DLY SFIO2_OUT_DLY

Type

RW

Rese

t

0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SFIO1_OUT_DLY SFIO0_OUT_DLY

Type

RW

Rese

t

0 0 0 0 0 0 0 0

Bit(s)

Name

Description

27:24

SFIO3_OUT_DLY

Serial flash SFIO3 pin IO output delay setting

*value = efuse{0x109[7:4]}

19:16

SFIO2_OUT_DLY

Serial flash SFIO2 pin IO output delay setting

*value = efuse{0x109[3:0]}

11:8

SFIO1_OUT_DLY

Serial flash SFIO1 pin IO output delay setting

*value = efuse{0x10A[7:4]}

3:0

SFIO0_OUT_DLY

Serial flash SFIO0 pin IO output delay setting

*value = efuse{0x10A[3:0]}

83070024

SF_DLY_CTL2

Serial flash delay controller setting 2

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

SFIO3_IN_DLY SFIO2_IN_DLY

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SFIO1_IN_DLY SFIO0_IN_DLY

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

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Bit(s)

Name

Description

29:24

SFIO3_IN_DLY

Serial flash SFIO3 pin IO input delay setting

*value[3:0] = efuse{0x10B[7:4]}

21:16

SFIO2_IN_DLY

Serial flash SFIO2 pin IO input delay setting

*value[3:0] =

efuse{0x10B[3:0]}

13:8

SFIO1_IN_DLY

Serial flash SFIO1 pin IO input delay setting

*value[3:0] = efuse{0x10C[7:4]}

5:0

SFIO0_IN_DLY

Serial flash SFIO0 pin IO input delay setting

*value[3:0] = efuse{0x10C[3:0]}

83070028

SF_DLY_CTL3

Serial flash delay controller setting 3

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

sfifo_wr_en_dly_sel SFCS_DLY

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SFCK_OUT_DLY SFCK_SAM_DLY

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

29:24

sfifo_wr_en_dly_sel

Serial flash FIFO write enable delay select setting

*value = efuse{0x10D[5:0]}

19:16

SFCS_DLY

Serial flash SFCS pin IO output delay setting

*value = efuse{0x10E[7:4]}

11:8

SFCK_OUT_DLY

Serial flash CK pin IO output delay setting

*value = efuse{0x10E[3:0]}

5:0

SFCK_SAM_DLY

Serial flash sample clock delay setting

*value = efuse{0x10F[5:0]}

83070044

SF_MISC_CTL3

Serial flash MISC control setting 3

00003000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

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Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CH

2_

TR

AN

S_I

DL

E

CH

1_T

RA

NS

_I

DL

E

CH

2_

TR

AN

S_

MA

SK

CH

1_T

RA

NS

_M

AS

K

Type

RU

RW

Rese

t

1 1 0 0

Bit(s)

Name

Description

13

CH2_TRANS_IDLE

Idle status of CH2 after setting up CH2_TRANS_MASK

0 Busy

1 Idle

12

CH1_TRANS_IDLE

Idle status of CH1 after setting up CH1_TRANS_MASK

0 Busy

1 Idle

9

CH2_TRANS_MASK

Masks the AHB request for the CH2 of serial flash from

platform bus

0 Disable

1 Enable

8

CH1_TRANS_MASK

Masks the AHB request for the CH1 of serial flash from

platform bus

( CPU cannot access SFC after enable )

0 Disable

1 Enable

83070080

SF_PERF_MON1

Serial flash performance monitor 1

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

Type

Rese

t

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

PE

Rf_

mo

n_c

lr

per

f_

MO

N_

EN

Type

RW

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Rese

t

0 0

Bit(s)

Name

Description

1

PERf_mon_clr

Clears information of performance monitor. If

PERF_MON_CLR is set to 1, all data in the performance

monitor will be set to 0. Set PERF_MON_CLR to 0 to clear

the information in the performance monitor before re

-

starting the performance monitor.

0 Disable

1 Enable

0

perf_MON_EN

Performance monitor enable bit.

0 Disable

1 Enable

83070084

SF_PERF_MON2

Serial flash performance monitor 2

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

PERf_mon_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

PERf_mon_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

PERf_mon_CYC

Cycle counts after enable performance monitor

83070088

SF_PERF_MON3

Serial flash performance monitor 3

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

SF_BUSY_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SF_BUSY_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit(s)

Name

Description

31:0

SF_BUSY_CYC

Serial Flash Busy Cycle counts after enabling performance

monitor. SF_BUSY_CYC is the summation of MAC mode

and 3 AHB channels busy cycle.

8307008C

SF_PERF_MON4

Serial flash performance monitor 4

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

SF_MAC_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

SF_MAC_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

SF_MAC_CYC

Serial Flash MAC Mode Cycle counts after enabling

performance monitor

83070090

SF_PERF_MON5

Serial flash performance monitor 5

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

CH1_BUSY_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CH1_BUSY_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

CH1_BUSY_CYC

Serial Flash channel 1 busy cycle (access serial flash

device) counts after enabling performance monitor

83070094

SF_PERF_MON6

Serial flash performance monitor 6

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

CH1_REQ_COUNT

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Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CH1_REQ_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

CH1_REQ_COUNT

The number of AHB bus requests channel 1 of the serial

flash controller receives after enabling performance

monitor

83070098

SF_PERF_MON7

Serial flash performance monitor 7

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

ch1_DATA_BYTE_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

ch1_DATA_BYTE_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

ch1_DATA_BYTE_COUNT

The number of data bytes AHB bus transferred through

channel 1 of the serial flash controller after enabling

performance monitor

8307009C

SF_PERF_MON8

Serial flash performance monitor 8

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

ch2_BUSY_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

ch2_BUSY_CYC

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit(s)

Name

Description

31:0

ch2_BUSY_CYC

Serial Flash channel 2 busy cycle (access serial flash

device) counts after enabling performance monitor

830700A0

SF_PERF_MON9

Serial flash performance monitor 9

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

CH2_REQ_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CH2_REQ_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

CH2_REQ_COUNT

The number of AHB bus requests channel 2 of the serial

flash controller receives after enabling performance

monitor

830700A4

SF_PERF_MON10

Serial flash performance monitor 10

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

CH2_DATA_BYTE_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

CH2_DATA_BYTE_COUNT

Type

RU

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

CH2_DATA_BYTE_COUNT

The number of data bytes AHB bus transferred through

channel 2 of the serial flash controller after enabling

performance monitor

83070800~

8307089C

SF_GPRAM_DATA

[n](n=0~39)

Serial flash macro R/W memory data

(160 bytes)

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

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Nam

e

GPRAM_DATA

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

GPRAM_DATA

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31:0

GPRAM_DATA

R/W SRAM data by register address (0x800 ~ 0x89f).

SRAM data are composed of MAC_OUT_LENGTH +

MAC_IN_LENGTH bytes. Please read "twice" to access the

data when the address is changed. ( APB_CON[1] have to

set 1'b1 to read APB using 2T pclk )

2.4.5. DMA

2.4.5.1. General description

A generic DMA Controller is placed on AHB Bus to support fast data transfers and to off-load the processor.

With this controller, specific devices on AHB or APB buses can benefit greatly from quick completion of data

movement from or to memory modules such as Internal System RAM or External SRAM. Such Generic DMA

Controller can also be used to connect any two devices other than memory module as long as they can be

addressed in memory space.

Each channel has a similar set of registers to be configured to different scheme as desired. Once the service

candidate is decided, the responsible device driver should configure the Generic DMA Controller properly in

order to conduct DMA transfers. Both Interrupt- and Polling-based schemes in handling the completion event

are supported.

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Figure 2-26. Generic DMA controller block diagram

The table below presents the available DMA Channels:

Table 2-20. Available DMA channels

DMA number Type Ring Buffer Two Buffer Burst Mode Unaligned Word

Access

DMA1 Full Size ● ● ●

DMA2 Full Size ● ● ●

DMA3 Half Size ● ● ● ●

DMA4 Half Size ● ● ● ●

DMA5 Half Size ● ● ● ●

DMA6 Half Size ● ● ● ●

DMA7 Half Size ● ● ● ●

DMA8 Half Size ● ● ● ●

DMA9 Half Size ● ● ● ●

DMA10 Half Size ● ● ● ●

DMA11 Half Size ● ● ● ●

DMA12 Virtual FIFO ●

DMA13 Virtual FIFO ●

DMA14 Virtual FIFO ●

DMA15 Virtual FIFO ●

DMA16 Virtual FIFO ●

DMA17 Virtual FIFO ●

DMA18 Virtual FIFO ●

DMA19 Virtual FIFO ●

DMA20 Virtual FIFO ●

DMA21 Virtual FIFO ●

DMA22 Virtual FIFO ●

DMA23 Virtual FIFO ●

DMA24 Virtual FIFO ●

DMA25 Virtual FIFO ●

2.4.5.2. Full-Size and Half-Size DMA channels

There are three types of DMA channels supported in MT76X7.

• Full-size DMA: Both the source address and the destination address are programmable. It is normally

used for memory copy.

• Half-size DMA: Either the source address or the destination address is programmable. It is normally

used for data movement between memory and peripherals.

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• Virtual FIFO DMA (VFF DMA): It is a half-size DMA with an additional FIFO control engine. It is used to

provide the buffering capacity for peripherals including UART.

• Full-size DMA channel—channels 1 and 2

• Half-size DMA channel—Channels 3-11

• Virtual FIFO DMA—Channels 12-25

The difference between the first two types of DMA channels is that both source and destination address are

programmable in full-size DMA channels, but only the address of one side can be programmed in half-size

DMA channel. In half-size channels, only either the source or destination address can be programmed, while

the addresses of the other side are preset. Which preset address is used depends on the setting of MAS in

DMA Channel Control Register. Refer to the Register Definition section for more detail.

2.4.5.3. Ring buffer and double buffer memory data movement

DMA channels 1 through 11 support ring-buffer and double-buffer memory data movement. This can be

achieved by programming DMA_WPPT and DMA_WPTO, as well as setting WPEN in DMA_CON register to

enable. The following figure illustrates how this function works. Once the transfer counter reaches the value

of WPPT, the next address jumps to the WPTO address after completing the WPPT data transfer. Note that

only one side can be configured as ring-buffer or double-buffer memory, and this is controlled by WPSD in

DMA_CON register.

Figure 2-27. Ring Buffer and Double Buffer Memory Data Movement

2.4.5.4. Unaligned word access

The word access address on AHB bus must be aligned to word boundary, or the 2 LSB is truncated to 00b. If

programmers do not notice this, it may cause an incorrect data fetch. In the case where data is to be moved

from unaligned addresses to aligned addresses, the word is usually first split into four bytes and then moved

byte by byte. This action results in four read and four write transfers on the bus.

To improve bus efficiency, unaligned-word access is provided in DMA3~11. While this function is enabled,

DMAs move data from unaligned address to aligned address by executing four continuous byte-read access

and one word-write access, reducing the number of transfers on the bus by three.

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Figure 2-28. Unaligned Word Accesses

2.4.5.5. Virtual FIFO DMA

Virtual FIFO DMA is used to ease UART control. The difference between the Virtual FIFO DMAs and the

ordinary DMAs is that Virtual FIFO DMA contains an additional FIFO controller. The read and write pointers

are kept in the Virtual FIFO DMA. During a read from the FIFO, the read pointer points to the address of the

next data. During a write to the FIFO, the write pointer moves to the next address. If the FIFO is empty, a FIFO

read is not allowed. Similarly, data is not written into the FIFO if the FIFO is full. Due to UART flow control

requirements, an alert length is programmed. Once the FIFO Space is less than this value, an alert signal is

issued to enable UART flow control. The type of flow control performed depends on the setting in UART.

Each Virtual FIFO DMA can be programmed as RX or TX FIFO. This depends on the setting of DIR in DMA_CON

register. If DIR is “0”(READ), it means TX FIFO. On the other hand, if DIR is “1”(WRITE), the Virtual FIFO DMA is

specified as a RX FIFO.

Virtual FIFO DMA provides an interrupt to MCU. This interrupt informs MCU that there is data in the FIFO, and

the amount of data is over or under the value defined in DMA_COUNT register. With this, MCU does not need

to poll DMA to know when data must be removed from or put into the FIFO.

Note that Virtual FIFO DMAs cannot be used as generic DMAs.

Figure 2-29. Virtual FIFO DMA

Table 2-21. Virtual FIFO Access Port

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DMA number Address of Virtual FIFO Access Port

DMA12 7900_0000h

DMA13 7900_0100h

DMA14 7900_0200h

DMA15 7900_0300h

DMA16 7900_0400h

DMA17 7900_0500h

DMA18 7900_0600h

DMA19 7900_0700h

DMA20 7900_0800h

DMA21 7900_0900h

DMA22 7900_0A00h

DMA23 7900_0B00h

DMA24 7900_0C00h

DMA25 7900_0D00h

The figure below illustrates the operations of virtual FIFO DMA used for UART RX.

• READ: DMA controller reads data from UART and increments the WRITE pointer of the FIFO

controller.

• WRITE; DMA controller writes data that was area from UART to SRAM in the area defined before

enabling the virtual FIFO.

• READ: MCU reads data when FIFO is not empty and the amount of data is over a pre-defined

threshold. The read transaction will be finished only when DMA controller reads back the data from

SRAM.

• READ: DMA controller reads data from SRAM and increments the READ pointer of the FIFO controller.

Figure 2-30. Virtual FIFO Concept

2.4.5.6. DMA channels and priority control

There are two full-size DMA channels, 8 half- size DMA channels, and 13 virtual FIFO DMA channels in MT76x7.

Table 2-22. DMA use for hardware functions

DMA

UART

SRAM

MCU

(1) READ

(2) WRITE

(3) READ (4) READ

memory

FIFO size

Destination Address

READ pointer

(MCU)

WRITE pointer

(UART RX)

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Hardware Function DMA Type

Radio (Bluetooth) Virtual FIFO DMA x 2

Radio (Wi-Fi) Half size DMA x 1

UART (x2) Virtual FIFO DMA x 4

I2S Virtual FIFO DMA x 2

ADC Virtual FIFO DMA x 1

I2C (x2) Half size DMA x 4

Security boot Full size DMA x 1

Reserved Full size DMA x 1, half size DMA x 5 and virtual FIFO DMA x 4.

The DMA provides two levels of scheduling scheme among all channels.

1) The first level scheduling follows the strict-priority scheme. All channels can be grouped into four

priority groups. Group one gets the highest priority, then group two, and so on.

2) The second level scheduling follows the round-robin scheme. Every channel in the same priority group

has equal opportunity to use the bandwidth and was served sequentially.

The arbitration is done per AHB transaction. When one AHB transaction is finished, the scheduler will follow

the above mechanism to select the next DMA channel to serve.

2.4.5.7. Register definitions

Register programming tips:

• Start registers shall be cleared, when associated channels are being programmed.

• PGMADDR, i.e. programmable address, only exists in half-size DMA channels. If DIR in Control

Register is high, PGMADDR represents Destination Address. Conversely, If DIR in Control Register is

low, PGMADDR represents Source Address.

• Functions of ring-buffer and double-buffer memory data movement can be activated on either source

side or destination side by programming DMA_WPPT & and DMA_WPTO, as well as setting WPEN in

DMA_CON register high. WPSD in DMA_CON register determines the activated side.

Module name: dma_cm4 Base address: (+83010000h)

Address

Name

Width

Register Function

83010000

DMA_CM4_GLBSTA0

32

DMA CR4 Global Status Register 0. This

register helps software program keep

track of the global status of DMA channels.

83010004

DMA_CM4_GLBSTA1

32

DMA CR4 Global Status Register 1. This

register helps

software program keep

track of the global status of DMA channels.

83010010

DMA_CM4_GROUP0

32

DMA CR4 Group Setting Register 0

83010014

DMA_CM4_GROUP1

32

DMA CR4 Group Setting Register 1

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Address

Name

Width

Register Function

83010028

DMA_CM4_GLBLIMIT

ER

32

DMA CR4 Global Bandwidth Limiter

Register

83010100

DMA1_SRC

32

DMA CR4 Channel 1 Source Address

Register

83010104

DMA1_DST

32

DMA CR4 Channel 1 Destination Address

Register

83010108

DMA1_WPPT

32

DMA CR4 Channel 1 Wrap Point Address

Register

8301010C

DMA1_WPTO

32

DMA CR4 Channel 1 Wrap To Address

Register

83010110

DMA1_COUNT

32

DMA CR4 Channel 1 Transfer Count

Register

83010114

DMA1_CON

32

DMA CR4 Channel 1 Control Register

83010118

DMA1_START

32

DMA CR4 Channel 1 Start Register

8301011C

DMA1_INTSTA

32

DMA CR4 Channel 1 Interrupt Status

Register

83010120

DMA1_ACKINT

32

DMA CR4 Channel 1 Interrupt

Acknowledge Register

83010124

DMA1_RLCT

32

DMA CR4 Channel 1 Remaining Length of

Current Transfer

83010128

DMA1_LIMITER

32

DMA CR4 Channel 1 Bandwidth Limiter

Register

83010200

DMA2_SRC

32

DMA CR4 Channel 2 Source Address

Register

83010204

DMA2_DST

32

DMA CR4 Channel 2 Destination Address

Register

83010208

DMA2_WPPT

32

DMA CR4 Channel 2 Wrap Point Address

Register

8301020C

DMA2_WPTO

32

DMA CR4 Channel 2 Wrap To Address

Register

83010210

DMA2_COUNT

32

DMA CR4 Channel 2 Transfer Count

Register

83010214

DMA2_CON

32

DMA CR4 Channel 2 Control Register

83010218

DMA2_START

32

DMA CR4 Channel 2 Start Register

8301021C

DMA2_INTSTA

32

DMA CR4 Channel 2 Interrupt Status

Register

83010220

DMA2_ACKINT

32

DMA CR4 Channel 2 Interrupt

Acknowledge Register

83010224

DMA2_RLCT

32

DMA CR4 Channel 2 Remaining Length of

Current Transfer

83010228

DMA2_LIMITER

32

DMA CR4 Channel 2 Bandwidth Limiter

Register

83010308

DMA3_WPPT

32

DMA CR4 Channel 3 Wrap Point Address

Register

8301030C

DMA3_WPTO

32

DMA CR4 Channel 3 Wrap To Address

Register

83010310

DMA3_COUNT

32

DMA CR4 Channel 3 Transfer Count

Register

83010314

DMA3_CON

32

DMA CR4 Channel 3 Control Register

83010318

DMA3_START

32

DMA CR4 Channel 3 Start

Register

8301031C

DMA3_INTSTA

32

DMA CR4 Channel 3 Interrupt Status

Register

83010320

DMA3_ACKINT

32

DMA CR4 Channel 3 Interrupt

Acknowledge Register

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Address

Name

Width

Register Function

83010324

DMA3_RLCT

32

DMA CR4 Channel 3 Remaining Length of

Current Transfer

83010328

DMA3_LIMITER

32

DMA CR4 Channel 3 Bandwidth Limiter

Register

8301032C

DMA3_PGMADDR

32

DMA CR4 Channel 3 Programmable

Address Register

83010408

DMA4_WPPT

32

DMA CR4 Channel 4 Wrap Point Address

Register

8301040C

DMA4_WPTO

32

DMA CR4 Channel 4 Wrap To Address

Register

83010410

DMA4_COUNT

32

DMA CR4 Channel 4 Transfer Count

Register

83010414

DMA4_CON

32

DMA CR4 Channel 4 Control Register

83010418

DMA4_START

32

DMA CR4 Channel 4 Start Register

8301041C

DMA4_INTSTA

32

DMA CR4 Channel 4 Interrupt Status

Register

83010420

DMA4_ACKINT

32

DMA CR4 Channel 4 Interrupt

Acknowledge Register

83010424

DMA4_RLCT

32

DMA CR4 Channel 4 Remaining Length of

Current Transfer

83010428

DMA4_LIMITER

32

DMA CR4 Channel 4 Bandwidth Limiter

Register

8301042C

DMA4_PGMADDR

32

DMA CR4 Channel 4 Programmable

Address Register

83010508

DMA5_WPPT

32

DMA CR4 Channel 5 Wrap Point Address

Register

8301050C

DMA5_WPTO

32

DMA CR4 Channel 5 Wrap To Address

Register

83010510

DMA5_COUNT

32

DMA CR4 Channel 5 Transfer Count

Register

83010514

DMA5_CON

32

DMA CR4 Channel 5 Control Register

83010518

DMA5_START

32

DMA CR4 Channel 5 Start

Register

8301051C

DMA5_INTSTA

32

DMA CR4 Channel 5 Interrupt Status

Register

83010520

DMA5_ACKINT

32

DMA CR4 Channel 5 Interrupt

Acknowledge Register

83010524

DMA5_RLCT

32

DMA CR4 Channel 5 Remaining Length of

Current Transfer

83010528

DMA5_LIMITER

32

DMA CR4 Channel 5 Bandwidth Limiter

Register

8301052C

DMA5_PGMADDR

32

DMA CR4 Channel 5 Programmable

Address Register

83010608

DMA6_WPPT

32

DMA CR4 Channel 6 Wrap Point Address

Register

8301060C

DMA6_WPTO

32

DMA CR4 Channel 6 Wrap To Address

Register

83010610

DMA6_COUNT

32

DMA CR4 Channel 6 Transfer Count

Register

83010614

DMA6_CON

32

DMA CR4 Channel 6 Control Register

83010618

DMA6_START

32

DMA CR4 Channel 6 Start

Register

8301061C

DMA6_INTSTA

32

DMA CR4 Channel 6 Interrupt Status

Register

83010620

DMA6_ACKINT

32

DMA CR4 Channel 6 Interrupt

Acknowledge Register

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Address

Name

Width

Register Function

83010624

DMA6_RLCT

32

DMA CR4 Channel 6 Remaining Length of

Current Transfer

83010628

DMA6_LIMITER

32

DMA CR4 Channel 6 Bandwidth Limiter

Register

8301062C

DMA6_PGMADDR

32

DMA CR4 Channel 6 Programmable

Address Register

83010708

DMA7_WPPT

32

DMA CR4 Channel 7 Wrap Point Address

Register

8301070C

DMA7_WPTO

32

DMA CR4 Channel 7 Wrap To Address

Register

83010710

DMA7_COUNT

32

DMA CR4 Channel 7 Transfer Count

Register

83010714

DMA7_CON

32

DMA CR4 Channel 7 Control Register

83010718

DMA7_START

32

DMA CR4 Channel 7 Start Register

8301071C

DMA7_INTSTA

32

DMA CR4 Channel 7 Interrupt Status

Register

83010720

DMA7_ACKINT

32

DMA CR4 Channel 7 Interrupt

Acknowledge Register

83010724

DMA7_RLCT

32

DMA CR4 Channel 7 Remaining Length of

Current Transfer

83010728

DMA7_LIMITER

32

DMA CR4 Channel 7 Bandwidth Limiter

Register

8301072C

DMA7_PGMADDR

32

DMA CR4 Channel 7 Programmable

Address Register

83010808

DMA8_WPPT

32

DMA CR4 Channel 8 Wrap Point Address

Register

8301080C

DMA8_WPTO

32

DMA CR4 Channel 8 Wrap To Address

Register

83010810

DMA8_COUNT

32

DMA CR4 Channel 8 Transfer Count

Register

83010814

DMA8_CON

32

DMA CR4 Channel 8 Control Register

83010818

DMA8_START

32

DMA CR4 Channel 8 Start

Register

8301081C

DMA8_INTSTA

32

DMA CR4 Channel 8 Interrupt Status

Register

83010820

DMA8_ACKINT

32

DMA CR4 Channel 8 Interrupt

Acknowledge Register

83010824

DMA8_RLCT

32

DMA CR4 Channel 8 Remaining Length of

Current Transfer

83010828

DMA8_LIMITER

32

DMA CR4 Channel 8 Bandwidth Limiter

Register

8301082C

DMA8_PGMADDR

32

DMA CR4 Channel 8 Programmable

Address Register

83010908

DMA9_WPPT

32

DMA CR4 Channel 9 Wrap Point Address

Register

8301090C

DMA9_WPTO

32

DMA CR4 Channel 9 Wrap To Address

Register

83010910

DMA9_COUNT

32

DMA CR4 Channel 9 Transfer Count

Register

83010914

DMA9_CON

32

DMA CR4 Channel 9 Control Register

83010918

DMA9_START

32

DMA CR4 Channel 9 Start

Register

8301091C

DMA9_INTSTA

32

DMA CR4 Channel 9 Interrupt Status

Register

83010920

DMA9_ACKINT

32

DMA CR4 Channel 9 Interrupt

Acknowledge Register

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Address

Name

Width

Register Function

83010924

DMA9_RLCT

32

DMA CR4 Channel 9 Remaining Length of

Current Transfer

83010928

DMA9_LIMITER

32

DMA CR4 Channel 9 Bandwidth Limiter

Register

8301092C

DMA9_PGMADDR

32

DMA CR4 Channel 9 Programmable

Address Register

83010A08

DMA10_WPPT

32

DMA CR4 Channel 10 Wrap Point Address

Register

83010A0C

DMA10_WPTO

32

DMA CR4 Channel 10 Wrap To Address

Register

83010A10

DMA10_COUNT

32

DMA CR4 Channel 10 Transfer Count

Register

83010A14

DMA10_CON

32

DMA CR4 Channel 10 Control Register

83010A18

DMA10_START

32

DMA CR4 Channel 10 Start Register

83010A1C

DMA10_INTSTA

32

DMA CR4 Channel 10 Interrupt Status

Register

83010A20

DMA10_ACKINT

32

DMA CR4 Channel 10 Interrupt

Acknowledge Register

83010A24

DMA10_RLCT

32

DMA CR4 Channel 10 Remaining Length of

Current Transfer

83010A28

DMA10_LIMITER

32

DMA CR4 Channel 10 Bandwidth Limiter

Register

83010A2C

DMA10_PGMADDR

32

DMA CR4 Channel 10 Programmable

Address Register

83010B08

DMA11_WPPT

32

DMA CR4 Channel 11 Wrap Point Address

Register

83010B0C

DMA11_WPTO

32

DMA CR4 Channel 11 Wrap To Address

Register

83010B10

DMA11_COUNT

32

DMA CR4 Channel 11 Transfer Count

Register

83010B14

DMA11_CON

32

DMA CR4 Channel 11 Control Register

83010B18

DMA11_START

32

DMA CR4 Channel 11 Start Register

83010B1C

DMA11_INTSTA

32

DMA CR4 Channel 11 Interrupt Status

Register

83010B20

DMA11_ACKINT

32

DMA CR4 Channel 11 Interrupt

Acknowledge

Register

83010B24

DMA11_RLCT

32

DMA CR4 Channel 11 Remaining Length of

Current Transfer

83010B28

DMA11_LIMITER

32

DMA CR4 Channel 11 Bandwidth Limiter

Register

83010B2C

DMA11_PGMADDR

32

DMA CR4 Channel 11 Programmable

Address Register

83010C10

DMA12_COUNT

32

DMA CR4 Channel 12 Transfer Count

Register

83010C14

DMA12_CON

32

DMA

CR4 Channel 12 Control Register

83010C18

DMA12_START

32

DMA CR4 Channel 12 Start Register

83010C1C

DMA12_INTSTA

32

DMA CR4 Channel 12 Interrupt Status

Register

83010C20

DMA12_ACKINT

32

DMA CR4 Channel 12 Interrupt

Acknowledge Register

83010C28

DMA12_LIMITER

32

DMA CR4 Channel 12 Bandwidth Limiter

Register

83010C2C

DMA12_PGMADDR

32

DMA CR4 Channel 12 Programmable

Address Register

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Address

Name

Width

Register Function

83010C30

DMA12_WRPTR

32

DMA CR4 Channel 12 Write Pointer

83010C34

DMA12_RDPTR

32

DMA CR4 Channel 12 Read Pointer

83010C38

DMA12_FFCNT

32

DMA CR4 Channel 12 FIFO Count

83010C3C

DMA12_FFSTA

32

DMA CR4 Channel 12 FIFO Status

83010C40

DMA12_ALTLEN

32

DMA CR4 Channel 12 Alert Length

Register

83010C44

DMA12_FFSIZE

32

DMA CR4 Channel 12 Virtual FIFO Size

Register

83010C48

DMA12_CVFF

32

DMA CR4 Channel 12 Cascade Virtual

FIFO Control Register

83010C50

DMA12_TO

32

DMA CR4 Channel 12 Timeout Value

Register

83010D10

DMA13_COUNT

32

DMA CR4 Channel 13 Transfer Count

Register

83010D14

DMA13_CON

32

DMA CR4 Channel 13

Control Register

83010D18

DMA13_START

32

DMA CR4 Channel 13 Start Register

83010D1C

DMA13_INTSTA

32

DMA CR4 Channel 13 Interrupt Status

Register

83010D20

DMA13_ACKINT

32

DMA CR4 Channel 13 Interrupt

Acknowledge Register

83010D28

DMA13_LIMITER

32

DMA CR4 Channel 13 Bandwidth Limiter

Register

83010D2C

DMA13_PGMADDR

32

DMA CR4 Channel 13 Programmable

Address Register

83010D30

DMA13_WRPTR

32

DMA CR4 Channel 13 Write Pointer

83010D34

DMA13_RDPTR

32

DMA CR4 Channel 13 Read Pointer

83010D38

DMA13_FFCNT

32

DMA CR4 Channel 13 FIFO Count

83010D3C

DMA13_FFSTA

32

DMA CR4 Channel 13 FIFO Status

83010D40

DMA13_ALTLEN

32

DMA CR4 Channel 13 Alert Length

Register

83010D44

DMA13_FFSIZE

32

DMA CR4 Channel 13 Virtual FIFO Size

Register

83010D48

DMA13_CVFF

32

DMA CR4 Channel 13 Cascade Virtual

FIFO Control Register

83010D50

DMA13_TO

32

DMA CR4 Channel 13 Timeout Value

Register

83010E10

DMA14_COUNT

32

DMA CR4 Channel 14 Transfer Count

Register

83010E14

DMA14_CON

32

DMA CR4 Channel 14 Control Register

83010E18

DMA14_START

32

DMA CR4 Channel 14 Start Register

83010E1C

DMA14_INTSTA

32

DMA CR4 Channel 14 Interrupt Status

Register

83010E20

DMA14_ACKINT

32

DMA CR4 Channel 14 Interrupt

Acknowledge Register

83010E28

DMA14_LIMITER

32

DMA CR4 Channel 14 Bandwidth Limiter

Register

83010E2C

DMA14_PGMADDR

32

DMA CR4 Channel 14 Programmable

Address Register

83010E30

DMA14_WRPTR

32

DMA CR4 Channel 14 Write Pointer

83010E34

DMA14_RDPTR

32

DMA CR4 Channel 14 Read Pointer

83010E38

DMA14_FFCNT

32

DMA CR4 Channel 14 FIFO Count

83010E3C

DMA14_FFSTA

32

DMA CR4 Channel 14 FIFO Status

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Address

Name

Width

Register Function

83010E40

DMA14_ALTLEN

32

DMA CR4 Channel 14 Alert Length

Register

83010E44

DMA14_FFSIZE

32

DMA CR4 Channel 14 Virtual FIFO Size

Register

83010E48

DMA14_CVFF

32

DMA CR4 Channel 14 Cascade Virtual

FIFO Control Register

83010E50

DMA14_TO

32

DMA CR4 Channel 14 Timeout Value

Register

83010F10

DMA15_COUNT

32

DMA CR4 Channel 15 Transfer Count

Register

83010F14

DMA15_CON

32

DMA CR4 Channel 15 Control Register

83010F18

DMA15_START

32

DMA CR4 Channel 15 Start Register

83010F1C

DMA15_INTSTA

32

DMA CR4 Channel 15 Interrupt Status

Register

83010F20

DMA15_ACKINT

32

DMA CR4 Channel 15 Interrupt

Acknowledge Register

83010F28

DMA15_LIMITER

32

DMA CR4 Channel 15 Bandwidth Limiter

Register

83010F2C

DMA15_PGMADDR

32

DMA CR4 Channel 15 Programmable

Address Register

83010F30

DMA15_WRPTR

32

DMA CR4 Channel 15 Write Pointer

83010F34

DMA15_RDPTR

32

DMA CR4 Channel 15 Read Pointer

83010F38

DMA15_FFCNT

32

DMA CR4 Channel 15 FIFO Count

83010F3C

DMA15_FFSTA

32

DMA CR4 Channel 15 FIFO Status

83010F40

DMA15_ALTLEN

32

DMA CR4 Channel 15 Alert Length

Register

83010F44

DMA15_FFSIZE

32

DMA CR4 Channel 15 Virtual FIFO Size

Register

83010F48

DMA15_CVFF

32

DMA CR4 Channel 15 Cascade Virtual

FIFO Control Register

83010F50

DMA15_TO

32

DMA CR4 Channel 15 Timeout Value

Register

83011010

DMA16_COUNT

32

DMA CR4 Channel 16 Transfer Count

Register

83011014

DMA16_CON

32

DMA CR4 Channel 16 Control Register

83011018

DMA16_START

32

DMA CR4 Channel 16 Start Register

8301101C

DMA16_INTSTA

32

DMA CR4 Channel 16 Interrupt Status

Register

83011020

DMA16_ACKINT

32

DMA CR4 Channel 16 Interrupt

Acknowledge Register

83011028

DMA16_LIMITER

32

DMA CR4 Channel 16 Bandwidth Limiter

Register

8301102C

DMA16_PGMADDR

32

DMA CR4 Channel 16 Programmable

Address Register

83011030

DMA16_WRPTR

32

DMA CR4 Channel 16 Write Pointer

83011034

DMA16_RDPTR

32

DMA CR4 Channel 16 Read Pointer

83011038

DMA16_FFCNT

32

DMA CR4 Channel 16 FIFO Count

8301103C

DMA16_FFSTA

32

DMA CR4 Channel 16 FIFO Status

83011040

DMA16_ALTLEN

32

DMA CR4 Channel 16 Alert Length

Register

83011044

DMA16_FFSIZE

32

DMA CR4 Channel 16 Virtual FIFO Size

Register

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Address

Name

Width

Register Function

83011048

DMA16_CVFF

32

DMA CR4 Channel 16 Cascade Virtual

FIFO Control Register

83011050

DMA16_TO

32

DMA CR4 Channel 16 Timeout Value

Register

83011110

DMA17_COUNT

32

DMA CR4 Channel 17 Transfer Count

Register

83011114

DMA17_CON

32

DMA CR4 Channel 17 Control Register

83011118

DMA17_START

32

DMA CR4 Channel 17 Start Register

8301111C

DMA17_INTSTA

32

DMA CR4 Channel 17 Interrupt Status

Register

83011120

DMA17_ACKINT

32

DMA CR4 Channel 17 Interrupt

Acknowledge Register

83011128

DMA17_LIMITER

32

DMA CR4 Channel 17 Bandwidth Limiter

Register

8301112C

DMA17_PGMADDR

32

DMA CR4 Channel 17 Programmable

Address Register

83011130

DMA17_WRPTR

32

DMA CR4 Channel 17 Write Pointer

83011134

DMA17_RDPTR

32

DMA CR4 Channel 17 Read Pointer

83011138

DMA17_FFCNT

32

DMA CR4 Channel 17 FIFO Count

8301113C

DMA17_FFSTA

32

DMA CR4 Channel 17 FIFO Status

83011140

DMA17_ALTLEN

32

DMA CR4 Channel 17 Alert Length

Register

83011144

DMA17_FFSIZE

32

DMA CR4 Channel 17 Virtual FIFO Size

Register

83011148

DMA17_CVFF

32

DMA CR4 Channel 17 Cascade Virtual

FIFO Control Register

83011150

DMA17_TO

32

DMA CR4 Channel 17 Timeout Value

Register

83011210

DMA18_COUNT

32

DMA CR4 Channel 18 Transfer Count

Register

83011214

DMA18_CON

32

DMA CR4 Channel 18 Control Register

83011218

DMA18_START

32

DMA CR4 Channel 18 Start Register

8301121C

DMA18_INTSTA

32

DMA CR4 Channel 18 Interrupt Status

Register

83011220

DMA18_ACKINT

32

DMA CR4 Channel 18 Interrupt

Acknowledge Register

83011228

DMA18_LIMITER

32

DMA CR4 Channel 18 Bandwidth Limiter

Register

8301122C

DMA18_PGMADDR

32

DMA CR4 Channel 18 Programmable

Address Register

83011230

DMA18_WRPTR

32

DMA CR4 Channel 18 Write Pointer

83011234

DMA18_RDPTR

32

DMA CR4 Channel 18 Read Pointer

83011238

DMA18_FFCNT

32

DMA CR4 Channel 18 FIFO Count

8301123C

DMA18_FFSTA

32

DMA CR4 Channel 18 FIFO Status

83011240

DMA18_ALTLEN

32

DMA CR4 Channel 18 Alert Length

Register

83011244

DMA18_FFSIZE

32

DMA CR4 Channel 18 Virtual FIFO Size

Register

83011248

DMA18_CVFF

32

DMA CR4 Channel 18 Cascade Virtual

FIFO Control Register

83011250

DMA18_TO

32

DMA CR4 Channel 18 Timeout Value

Register

MT76x7

Internet-of-Things Wireless Connectivity

Reference Manual

Page 96 of 798

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Address

Name

Width

Register Function

83011310

DMA19_COUNT

32

DMA CR4 Channel 19 Transfer Count

Register

83011314

DMA19_CON

32

DMA CR4 Channel 19

Control Register

83011318

DMA19_START

32

DMA CR4 Channel 19 Start Register

8301131C

DMA19_INTSTA

32

DMA CR4 Channel 19 Interrupt Status

Register

83011320

DMA19_ACKINT

32

DMA CR4 Channel 19 Interrupt

Acknowledge Register

83011328

DMA19_LIMITER

32

DMA CR4 Channel 19 Bandwidth Limiter

Register

8301132C

DMA19_PGMADDR

32

DMA CR4 Channel 19 Programmable

Address Register

83011330

DMA19_WRPTR

32

DMA CR4 Channel 19 Write Pointer

83011334

DMA19_RDPTR

32

DMA CR4 Channel 19 Read Pointer

83011338

DMA19_FFCNT

32

DMA CR4 Channel 19 FIFO Count

8301133C

DMA19_FFSTA

32

DMA CR4 Channel 19 FIFO Status

83011340

DMA19_ALTLEN

32

DMA CR4 Channel 19 Alert Length

Register

83011344

DMA19_FFSIZE

32

DMA CR4 Channel 19 Virtual FIFO Size

Register

83011348

DMA19_CVFF

32

DMA CR4 Channel 19 Cascade Virtual

FIFO Control Register

83011350

DMA19_TO

32

DMA CR4 Channel 19 Timeout Value

Register

83011410

DMA20_COUNT

32

DMA CR4 Channel 20 Transfer Count

Register

83011414

DMA20_CON

32

DMA CR4 Channel 20 Control Register

83011418

DMA20_START

32

DMA CR4 Channel 20 Start Register

8301141C

DMA20_INTSTA

32

DMA CR4 Channel 20 Interrupt Status

Register

83011420

DMA20_ACKINT

32

DMA CR4 Channel 20 Interrupt

Acknowledge Register

83011428

DMA20_LIMITER

32

DMA CR4 Channel 20 Bandwidth Limiter

Register

8301142C

DMA20_PGMADDR

32

DMA CR4 Channel 20 Programmable

Address Register

83011430

DMA20_WRPTR

32

DMA CR4 Channel 20 Write Pointer

83011434

DMA20_RDPTR

32

DMA CR4 Channel 20 Read Pointer

83011438

DMA20_FFCNT

32

DMA CR4 Channel 20 FIFO Count

8301143C

DMA20_FFSTA

32

DMA CR4 Channel 20 FIFO Status

83011440

DMA20_ALTLEN

32

DMA CR4 Channel 20 Alert Length

Register

83011444

DMA20_FFSIZE

32

DMA CR4 Channel 20 Virtual FIFO Size

Register

83011448

DMA20_CVFF

32

DMA CR4 Channel 20 Cascade Virtual

FIFO Control Register

83011450

DMA20_TO

32

DMA CR4 Channel 20 Timeout Value

Register

83011510

DMA21_COUNT

32

DMA CR4 Channel 21 Transfer Count

Register

83011514

DMA21_CON

32

DMA CR4 Channel 21 Control Register

83011518

DMA21_START

32

DMA CR4 Channel

21 Start Register

MT76x7

Internet-of-Things Wireless Connectivity

Reference Manual

Page 97 of 798

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Address

Name

Width

Register Function

8301151C

DMA21_INTSTA

32

DMA CR4 Channel 21 Interrupt Status

Register

83011520

DMA21_ACKINT

32

DMA CR4 Channel 21 Interrupt

Acknowledge Register

83011528

DMA21_LIMITER

32

DMA CR4 Channel 21 Bandwidth Limiter

Register

8301152C

DMA21_PGMADDR

32

DMA CR4 Channel 21 Programmable

Address Register

83011530

DMA21_WRPTR

32

DMA CR4 Channel 21 Write Pointer

83011534

DMA21_RDPTR

32

DMA CR4 Channel 21 Read Pointer

83011538

DMA21_FFCNT

32

DMA CR4 Channel 21 FIFO Count

8301153C

DMA21_FFSTA

32

DMA CR4 Channel 21 FIFO Status

83011540

DMA21_ALTLEN

32

DMA CR4 Channel 21 Alert Length

Register

83011544

DMA21_FFSIZE

32

DMA CR4 Channel 21 Virtual FIFO Size

Register

83011548

DMA21_CVFF

32

DMA CR4 Channel 21 Cascade Virtual

FIFO Control Register

83011550

DMA21_TO

32

DMA CR4 Channel 21 Timeout Value

Register

83011610

DMA22_COUNT

32

DMA CR4 Channel 22 Transfer Count

Register

83011614

DMA22_CON

32

DMA CR4 Channel 22 Control Register

83011618

DMA22_START

32

DMA CR4 Channel 22 Start Register

8301161C

DMA22_INTSTA

32

DMA CR4 Channel 22 Interrupt Status

Register

83011620

DMA22_ACKINT

32

DMA CR4 Channel 22 Interrupt

Acknowledge Register

83011628

DMA22_LIMITER

32

DMA CR4 Channel 22 Bandwidth Limiter

Register

8301162C

DMA22_PGMADDR

32

DMA CR4 Channel 22 Programmable

Address Register

83011630

DMA22_WRPTR

32

DMA CR4 Channel 22 Write Pointer

83011634

DMA22_RDPTR

32

DMA CR4 Channel 22 Read Pointer

83011638

DMA22_FFCNT

32

DMA CR4 Channel 22 FIFO Count

8301163C

DMA22_FFSTA

32

DMA CR4 Channel 22 FIFO Status

83011640

DMA22_ALTLEN

32

DMA CR4 Channel 22 Alert Length

Register

83011644

DMA22_FFSIZE

32

DMA CR4 Channel 22 Virtual FIFO Size

Register

83011648

DMA22_CVFF

32

DMA CR4 Channel 22 Cascade Virtual

FIFO Control Register

83011650

DMA22_TO

32

DMA CR4 Channel 22 Timeout Value

Register

83011710

DMA23_COUNT

32

DMA CR4 Channel 23 Transfer Count

Register

83011714

DMA23_CON

32

DMA CR4 Channel 23 Control Register

83011718

DMA23_START

32

DMA CR4 Channel 23 Start Register

8301171C

DMA23_INTSTA

32

DMA CR4 Channel 23 Interrupt Status

Register

83011720

DMA23_ACKINT

32

DMA CR4 Channel 23 Interrupt

Acknowledge Register

MT76x7

Internet-of-Things Wireless Connectivity

Reference Manual

Page 98 of 798

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Address

Name

Width

Register Function

83011728

DMA23_LIMITER

32

DMA CR4 Channel 23 Bandwidth Limiter

Register

8301172C

DMA23_PGMADDR

32

DMA CR4 Channel 23 Programmable

Address Register

83011730

DMA23_WRPTR

32

DMA CR4 Channel 23 Write Pointer

83011734

DMA23_RDPTR

32

DMA CR4

Channel 23 Read Pointer

83011738

DMA23_FFCNT

32

DMA CR4 Channel 23 FIFO Count

8301173C

DMA23_FFSTA

32

DMA CR4 Channel 23 FIFO Status

83011740

DMA23_ALTLEN

32

DMA CR4 Channel 23 Alert Length

Register

83011744

DMA23_FFSIZE

32

DMA CR4 Channel 23 Virtual FIFO Size

Register

83011748

DMA23_CVFF

32

DMA CR4 Channel 23 Cascade Virtual

FIFO Control Register

83011750

DMA23_TO

32

DMA CR4 Channel 23 Timeout Value

Register

83011810

DMA24_COUNT

32

DMA CR4 Channel 24 Transfer Count

Register

83011814

DMA24_CON

32

DMA CR4 Channel 24 Control Register

83011818

DMA24_START

32

DMA CR4 Channel 24 Start Register

8301181C

DMA24_INTSTA

32

DMA CR4 Channel 24 Interrupt Status

Register

83011820

DMA24_ACKINT

32

DMA CR4 Channel 24 Interrupt

Acknowledge Register

83011828

DMA24_LIMITER

32

DMA CR4 Channel 24 Bandwidth Limiter

Register

8301182C

DMA24_PGMADDR

32

DMA CR4 Channel 24 Programmable

Address Register

83011830

DMA24_WRPTR

32

DMA CR4 Channel 24 Write Pointer

83011834

DMA24_RDPTR

32

DMA CR4 Channel 24 Read Pointer

83011838

DMA24_FFCNT

32

DMA CR4 Channel 24 FIFO Count

8301183C

DMA24_FFSTA

32

DMA CR4 Channel 24 FIFO Status

83011840

DMA24_ALTLEN

32

DMA CR4 Channel 24 Alert Length

Register

83011844

DMA24_FFSIZE

32

DMA CR4 Channel 24 Virtual FIFO Size

Register

83011848

DMA24_CVFF

32

DMA CR4 Channel 24 Cascade Virtual

FIFO Control Register

83011850

DMA24_TO

32

DMA CR4 Channel 24 Timeout Value

Register

83011910

DMA25_COUNT

32

DMA CR4 Channel 25 Transfer Count

Register

83011914

DMA25_CON

32

DMA CR4 Channel 25

Control Register

83011918

DMA25_START

32

DMA CR4 Channel 25 Start Register

8301191C

DMA25_INTSTA

32

DMA CR4 Channel 25 Interrupt Status

Register

83011920

DMA25_ACKINT

32

DMA CR4 Channel 25 Interrupt

Acknowledge Register

83011928

DMA25_LIMITER

32

DMA CR4 Channel 25 Bandwidth Limiter

Register

8301192C

DMA25_PGMADDR

32

DMA CR4 Channel 25 Programmable

Address Register

MT76x7

Internet-of-Things Wireless Connectivity

Reference Manual

Page 99 of 798

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Address

Name

Width

Register Function

83011930

DMA25_WRPTR

32

DMA CR4 Channel 25 Write Pointer

83011934

DMA25_RDPTR

32

DMA CR4 Channel 25 Read Pointer

83011938

DMA25_FFCNT

32

DMA CR4 Channel 25 FIFO Count

8301193C

DMA25_FFSTA

32

DMA CR4 Channel 25 FIFO Status

83011940

DMA25_ALTLEN

32

DMA CR4 Channel 25 Alert Length

Register

83011944

DMA25_FFSIZE

32

DMA CR4 Channel 25 Virtual FIFO Size

Register

83011948

DMA25_CVFF

32

DMA CR4 Channel 25 Cascade Virtual

FIFO Control Register

83011950

DMA25_TO

32

DMA CR4 Channel 25 Timeout Value

Register

83010000

DMA_CM4_GLBSTA0

DMA CR4 Global Status Register 0.

This register helps software program

keep track of the global status of DMA

channels.

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e IT1

6

RU

N1

6

IT1

5 RU

N15 IT1

4

RU

N1

4

IT1

3 RU

N13 IT1

2 RU

N12 IT1

1 RU

N11 IT1

0

RU

N1

0

IT9 RU

N9

Type

RO

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

IT8 RU

N8

IT7 RU

N7

IT6 RU

N6

IT5 RU

N5

IT4 RU

N4

IT3 RU

N3

IT2 RU

N2

IT1 RU

N1

Type

RO

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

31

IT16

ITN Interrupt status for channel 16

0 : No

interrupt is generated.

1 : An interrupt is pending and waiting for service.

30

RUN16

RUNN DMA channel 16 status

0 Channel 16 is stopped or has completed the transfer already.

1 Channel 16 is currently running

29

IT15

ITN Interrupt status for channel 15

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

28

RUN15

RUNN DMA channel 15 status

0 Channel 15 is stopped or has completed the transfer already.

MT76x7

Internet-of-Things Wireless Connectivity

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This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Bit(s)

Name

Description

1 Channel 15 is currently running

27

IT14

ITN Interrupt status for channel 14

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

26

RUN14

RUNN DMA channel 14 status

0 Channel 14 is stopped or has completed the transfer already.

1 Channel 14 is currently running

25

IT13

ITN Interrupt status for channel 13

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

24

RUN13

RUNN DMA channel 13 status

0 Channel 13 is stopped or has completed the transfer already.

1 Channel 13 is currently running

23

IT12

ITN Interrupt status for channel 12

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

22

RUN12

RUNN DMA channel 12 status

0 Channel 12 is stopped or has completed the transfer already.

1 Channel 12 is currently running

21

IT11

ITN Interrupt status for channel 11

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

20

RUN11

RUNN DMA channel 11 status

0 Channel 11 is stopped or has completed the transfer already.

1 Channel 11 is currently running

19

IT10

ITN Interrupt status for channel 10

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

18

RUN10

RUNN DMA channel 10 status

0 Channel 10 is stopped or has completed the transfer already.

1 Channel 10 is currently running

MT76x7

Internet-of-Things Wireless Connectivity

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Bit(s)

Name

Description

17

IT9

ITN Interrupt status for channel 9

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

16

RUN9

RUNN DMA channel 9 status

0 Channel 9 is stopped or has completed the transfer already.

1 Channel 9 is currently running

15

IT8

ITN Interrupt status for channel 8

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

14

RUN8

RUNN DMA channel 8 status

0 Channel 8 is stopped or has completed the transfer already.

1 Channel 8 is currently running

13

IT7

ITN Interrupt status for channel 7

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

12

RUN7

RUNN DMA channel 7 status

0 Channel 7 is stopped or has completed the transfer already.

1 Channel 7 is currently

running

11

IT6

ITN Interrupt status for channel 6

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

10

RUN6

RUNN DMA channel 6 status

0 Channel 6 is stopped or has completed the transfer already.

1 Channel 6 is currently

running

9

IT5

ITN Interrupt status for channel 5

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

8

RUN5

RUNN DMA channel 5 status

0 Channel 5 is stopped or has completed the transfer already.

1 Channel 5 is currently

running

7

IT4

ITN Interrupt status for channel 4

MT76x7

Internet-of-Things Wireless Connectivity

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Bit(s)

Name

Description

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

6

RUN4

RUNN DMA channel 4 status

0 Channel 4 is stopped or has completed the transfer already.

1 Channel 4 is currently

running

5

IT3

ITN Interrupt status for channel 3

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

4

RUN3

RUNN DMA channel 3 status

0 Channel 3 is stopped or has completed the transfer already.

1 Channel 3 is currently r

unning

3

IT2

ITN Interrupt status for channel 2

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

2

RUN2

RUNN DMA channel 2 status

0 Channel 2 is stopped or has completed the transfer already.

1 Channel 2 is currently

running

1

IT1

ITN Interrupt status for channel 1

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

0

RUN1

RUNN DMA channel 1 status

0 Channel 1 is stopped or has completed the transfer already.

1 Channel 1 is currently

running

83010004

DMA_CM4_GLBSTA1

DMA CR4 Global Status Register 1. This

register helps software program keep

track of the global status of DMA

channels.

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e IT2

5

RU

N2

5

Type

RO

Rese

t

0 0

MT76x7

Internet-of-Things Wireless Connectivity

Reference Manual

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e IT2

4

RU

N2

4

IT2

3

RU

N2

3

IT2

2

RU

N2

2

IT2

1 RU

N21 IT2

0

RU

N2

0

IT1

9

RU

N1

9

IT1

8

RU

N1

8

IT1

7 RU

N17

Type

RO

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description

17

IT25

ITN Interrupt status for channel 25

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

16

RUN25

RUNN DMA channel 25 status

0 Channel 25 is

stopped or has completed the transfer already.

1 Channel 25 is currently running

15

IT24

ITN Interrupt status for channel 24

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

14

RUN24

RUNN DMA channel 24 status

0 Channel

24 is stopped or has completed the transfer already.

1 Channel 24 is currently running

13

IT23

ITN Interrupt status for channel 23

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

12

RUN23

RUNN DMA channel 23 status

0

Channel 23 is stopped or has completed the transfer already.

1 Channel 23 is currently running

11

IT22

ITN Interrupt status for channel 22

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

10

RUN22

RUNN DMA channel 22 status

0 Channel 22 is stopped or has completed the transfer already.

1 Channel 22 is currently running

9

IT21

ITN Interrupt status for channel 21

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

MT76x7

Internet-of-Things Wireless Connectivity

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

Bit(s)

Name

Description

8

RUN21

RUNN DMA channel 21 status

0 Channel 21 is stopped or has completed the transfer already.

1 Channel 21 is currently running

7

IT20

ITN Interrupt status for channel 20

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

6

RUN20

RUNN DMA channel 20 status

0 Channel 20 is stopped or has completed the transfer already.

1 Channel 20 is currently running

5

IT19

ITN Interrupt status for channel 19

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

4

RUN19

RUNN DMA channel 19 status

0 Channel 19 is stopped or has completed the transfer already.

1 Channel 19 is currently running

3

IT18

ITN Interrupt status for channel 18

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

2

RUN18

RUNN DMA channel 18 status

0 Channel 18 is stopped or has completed the transfer already.

1 Channel 18 is currently running

1

IT17

ITN Interrupt status for channel 17

0 : No interrupt is generated.

1 : An interrupt is pending and waiting for service.

0

RUN17

RUNN DMA channel 17 status

0 Channel 17 is stopped or has completed the transfer already.

1 Channel 17 is currently running

83010010

DMA_CM4_GROUP0

DMA CR4 Group Setting Register 0

00000000

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Nam

e

GROUP_

CH16

GROUP_

CH15

GROUP_

CH14

GROUP_

CH13

GROUP_

CH12

GROUP_

CH11

GROUP_

CH10

GROUP_

CH9

MT76x7

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Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Nam

e

GROUP_

CH8

GROUP_

CH7

GROUP_

CH6

GROUP_

CH5

GROUP_

CH4

GROUP_

CH3

GROUP_

CH2

GROUP_

CH1

Type

RW

Rese

t

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit(s)

Name

Description