MU5_Basic_Programming_Manual_Jul75 MU5 Basic Programming Manual Jul75
MU5_Basic_Programming_Manual_Jul75 MU5_Basic_Programming_Manual_Jul75
User Manual: MU5_Basic_Programming_Manual_Jul75
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m;rVEl\SI'".['Y
CHi' ~1.Al~CI-mSTEH.
DEPART11EN-T OF CQSrpU'I'ER SCIENCE
'I
MUS BASIC PROGRJ.].'iMING MAl-mAL
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CC:;TENTS
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C'"dAF'I'ER
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.l.
Introduction
CH.4..L'">l'ER 2
CHAl":l-l'ER 3
CHAPTER
-.-A
T119
B-l~ri thrnetic
Accumulato:;.~
Arithmetic
CIIAP1'ER j'"
CHAPTER 6
CEi\. P'l'ER
7
?ne Interrupt System
CHAFfER
8
Tho V Sto:te
CHAPTER
9
CI{AFfER 10
LJ
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"
Tho Basic
progr~~~ing
Language - XPL
II
L .!
II
LI
II
,c
'
I
n
LJ
II
LJ
n
,
j
~
I
il
LJ
LJ
L
j
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'--I
:
;
- l
cc:rll:)u-:':sticnal oz'de:.:s
~l
l.-)
111
f
4
I
9
'~
Th0 c:!.' bi ts def::!.;'''.!0 on0 of four types of ari tt:mEltic; ...
sigl".lod fh:od-point
docimul
float:tng-point
-
,
i7h1.10 "tho unsig;ned
ii:i:od-poi:nt~
d0fino tho opol'a'1:io1'l. to be peri'o!:med s. no N defines the opera:i.'ld
Co~npuJ.;~t:i.ono.l orders al~O of the single address type (eog O ?
A :::.: op0:;''':::','ld p A + opol"a."ld) 0
- l
0
The B-orders operate on t110 modifier register Eo
Tl1ey have
the i'ormat:-
f
1001!
4rrhe functions pl'cvidecl
9
cO:i:.~r0spond
,
J
to those 'I.'7hich operate on X but
the division ordo:\.·s are not implel'.:ented in MUS 0
is convenient to think of the instruction as being divided in the
L )
sarile way:-
II
10111 d I
f
'I
9
4
'- J
Howove:;."': the
tVJO
values of d give a
tot~l
of 32 possible functions;
some of theso ere used ior'mm1ipulating registers in tho s0cond&ry
operand unit,'which is closely associated vith all store-to-stOI'e
operations.
In
th:i.l~;:
orgro~isational
tho
orders, the instruction is divided
..
L i
000
6
3
The
Cl'"
bi tn
:;,·eg;is'~o:c.·
~l~!()
arG
7
zeTo, and tho 6 f ~ bits define both the orgo.l1isations.l
and the opel'atiml
r>l;!:'.inly cOl1.comod with
'\;0
be performed 0
cont~'ol
Tne organisation2.1 orders
transfers and
th~
manipulation of
llJ'I. 0pGrz1.d is spocifi0d by N (or N'), ~.nd is independent of
!'I.lr!ction.
:l
'n::-;.l"r.n 9) 9
f~"J. opol1~nd
01'
the
L !
mo.y be c. l:i:t~n.·alg a 'na.'11ed operand? (more siraply:
a sOCOndE'!.l'Y
operQx~d;
the various intel'nal :t'sgistel's (X,
. I
L
J
S1..1iiWuary of th.e (b?der Code
This section SUlilills,:rizes the oV0rall patt0Z'u of ·;::1'1e oras:>:>
L.J
co~eo
The detail is given in Inter sections
func·cions in MUS differ fl'om general
fOJ.."1l1.
~l
u
Chapter
registGJ..~
3
4
5
6
Accillilul::>.. tors
st;;;-ucture
Accessing an.d Store to
S-CO:;"S
Ol'c\ers
Grganisational Orders
:2
!
Literals
203
Variables
204
Internal Register
Gp0r~lds
205
2,,6
·1
Pr:l. vileged Opert;'!lds
207
Secondary Operands
2 a8
Descriptor Types 0 -
2011 - 20 1 4
3
3
i3, BOD
..
.d.
'
XD, DOD, DT,
EN
-,
X~f
Some
overleaf 0 which should
ReIerences
B
shcvn bslowo
03
Cor:lptltc.. i:icnal
.~
n
L
In
V32
vS.::!.,
S[l1]
S[B]
S[O]
n is G-bi t Si~!1.0c1 int0gel'"
n defines internal re3:istor, P /T' 1)0. ->
Gper8,nc1 is accessed c1il"'ectly at
(W3) + ul1signec1 11.; n is sca.led for V32
Gperand is accessed 'via ~i.
descriptor at (NS) + 11, using
B or 0 o.s a."'l index
Ie (Extended Operand) P.T.O. ->
!
I:
L \
11
l J
,\
L
J
l _I
()l"'(1e:r s
--
1311. 'l
l
Nl v
r
1
L{DOnot0 test r08tllt by T (= 0 for :t·rC), := 1 for ygG)
rfl10 OP01"a,.'>"}.(1 specifies the way in which mr is 30 t.
0
--------_.-----_._-----------_
... _--mr == 0
1 rm ;:\ T
1 TIN / ':\'1'
! SN = '1'
D•() .'7, tl./2
.
L
J
L !
10
r ~s i iT:3
! :t.
i
:::IT.\~
'--:--------~---I?
I SIT I F~5
!,lJ
i L!.
t
I
I
M
!~
!
------Si?
SIT
I31,[
---
,-------
i61'
--:-------lZ-J
_____________.____________
1 ~.() I
D
---------~~
i :1~! i
}~J)
11RI
fT.:----~~--------~-----------! 1.9~1___________7-------:C-T-)1-'----.
i 2.oi
Df_;i)
121i
12~~ I
<---------GL~.--------->
i 11~ l-~'
t.J.~~~
!
! Q/.~ I
TIel)
,J_ _ _ _ _ _ _ _ __
I
-:--.-,-,
~:?:
1' ... _,.:./
• ","",-<....:'' - - - ' - - -
,-J
il'?L____.
1-:>.11 _ _ _ __
1• ,),1.
,:,~ 1
L
:-~'....o.
1:::-;·..,.'---_·
. ,j.i;
__
~
IjlL____
_ __
)71
1·';-",,--:-.----------.
10
-', l
..:.,::.:..----------------
i !tl!______ _
!
.~~-----------------------
!?0i
21 -----------------_.
i5
l ~i3_·1___ .___.____
! .5 :-!
---------------------L
____________
j5~l
--OJ
j 3..J_l.. I
Ik' In 7 I
l.-l
1
,-_J
I
-1
i..J
I
~
/
1- 1
." == 0
le' == 1
r
I1
== 0
[ n, =
1
I n' == 2
r ,
LI'l'lI!RP.. L
Q
!-
11
I
r
n'
I
1, v :::: "
:J
,.-
l
r!..
==
-.J
= / .-
If,-bit
siZt:.Gc:
3~;~bit
oS :i.En8~l
,.. - t)J.
' >G
u!:.
0Ll,...·bit
lS-iJi \:
1l:13 i~1·3(~
3::~-bi t
un::3 i2::'.. e(~.
11'
=: \)
6L1_-bit
l
,...
o-
=:
7
0.5.-021:
c' , - .
j
rrhe
11'3::-::t
scale(~
8..n~~.
:lO 1)i t.J
(if
to "'cho
t"!..('(10<~
8)"0
P.0C9:3:3E:..;'-':I)
~Jf~.::;Q
un3 tac1\:s op,8r:a,.,.""1("i
'~SGS
Cl.~~..~re:!:::.t
ctoSC:;:-ipt01.' in D':
instead of
U
rl0\Y
fa ·'
l02~in~
on. o - vali(:
~- 1
.1.:''\,
,ope:L~X!.Ct
-
.-
I
!,'0'9
c'
..)')
r:::
U
fro!l1 (172)
opel'and :i).:'o!:'!. (::7'::3)
I O:~1 ---l
~,- , i -:----.
:.... f ..1 i Si .. 4
}
.:.: -::.':. (::: t~..~
i . 10 ;
i,; ~ o~i
~:: ~
.
1
I
O~ !~
~
~
1
_~
•
0
. -I
~==.
j
~Iol
1H~Gl
•
0
1. .
•
:>:5
'1
i2'Ti;"E4J.!.51·
=-'" .:::'!"=,{ :'-"'I-~
'~I
0f7J
o r-r?]
f
i7.;:.Cll;::
I
1
I
.';DC
t
~
1.Ft
1
l
"
ID.::=,
'"lr:
. 1/
!'
I SLGC.
:!:.__
~I
J
SM'J'!El .1l8&·SVB
t -S~:l~
f.
.
r--~--J--;'--l=- 1--===[~==~=-~=I7~
f 0
t
'1
I 0
1 'i
I
r;
t:,~~"~"~;=~:~"~~r~"~~x:i~;7:"':~~'-"~'~'~~1:i:"i:;:'j r·'·~~~·~.~1·1~~~:;~'~:··-~r.·
i
V.
SMVF
CD >lei
Q)
j
DUMMyl sse",
sc
".F I
•
SUBi
A
i=
&
,.
i
f>Ct..,· .
A~'
·loUni'.-W
AB·
Ic~gp-i-, e'
I
BITS
OJ
XC4.
I .xc 5
XNB'~'
.SF =
NO
~
I-
= '. I
..
X N B -]-
'.'-
NB::::SF-l--
I
. SET LI N l(
I'
X N B=>
~
.
•
.
Bn_2.X ._. ---~~-~~-.~
~X
.
~n_
X_._.
I
Bn v
:x
11l~1i;X
.
.a.~
).
~::~:
x .:.
'--.
Bn v
.
x.·.
_~_~':'_'_
j
s ••
note 3
f" BlTS
·B
~"¢l;.~~~n"':.~~~-:::-~~~o..7.:mz.~~:
x
Snv
1.' .' .
.'
. J Bn·&~~t
aX
ACC
:E,..·..~.:.~.::::.z;;::~r....s=.:.t~~'!:c."",..i] .... ~":'..~..'::;~~r=-..
AEX
B
BOD
t·ll~
•
I
I;A & X
.
DR
I·
I ,~ 11t1
STACK_:!
SF +
.,
>tOR
fiN
SN:=.
. -t-See M U5 :l3asic 'Programmlng t-,,1anUClI
[=~-,....:~- ~~_?!~~,,==-,=>_~J
t . ~C 6
M S : : : · : . Dl=_..
B.
AEX
.~ ·SUB2., .~ CD lD'uMtJl~:t~urvH'w~Y
,-. ){Ci---r-XC2-- ~C3--'
0
ICOMp'!'.
C~P=
_
;.
4U;V~}AY
I DU1/lMY
tD
(
. JI
I RETUi1N
xco
~o
_ o
~o
{\:.~ JA'i'CfRC .I,
td'.-
Sf~ r~
I
A
.JU~.-iP
t .:., .::: u
.....:1
DUM1-.IY! A V
'i' LO~
I SN J N B
-
~ ~
',:1
;:;"'Z~~DUN'''l' IUllPAC".1 CQ.N~_A
XNB
'1
DUMMY! A
v.
COMp . ACOM?
A'E.X ••. v
Ms-~~o~JI..
ITI
.
1
i
DUM:MY. DUM}JYt"
.'·&tAm::f}i" A
~ ifA~~DUMM¥1 -e
COM!"·I
DUM1..,~'" t~
A X.
'1'·* . JA ~
BlLGC
,~.... i~.·:;"n'l ~~\'~V£;·
°l~
f'~I-Q
I
;
AU
.J~~.i=l
lI'j'l!l; :.~ .~" .\" 1i)1Ln~;rJ""I~~~E;;:=' ~ =i:,~~~:
. ' If
1
:10
. : !
I,SUOD.I ~~~~D.
'1 :\!~.'jOl!) , IP.l~!!-oD , .. 1.
;~
.
~ k l ' GJ
t
il
~ iO~!
m_
~:[il
':t J0
1DO
-}-
~I
i
Slrs.f/Jj
~
.}:>::=.-.1 jl.OD~=1 k£~~=' ~ ~~
I
i :::;> . r~~fi}l:::::;>.·· ~~ ~::~ I ';"OD=?:'"t ;-:.1:;:1::-"> 1 -> i .'
~ ~[lJ:£I;:::: t [;;R -:-' ',-::1- l.fo. -!- I· tm;...J}.§Y ~ +1
I
J ;:Ci-3X- ~ .i.'~':llf_H! ,'1. "~ A - '. DUM}':':)" I. - J '.
1
·.·IIFW~
., '1
0H
I~~'~~:"~="~~l-;~;;~~~f~~;;';~~-:~"~~~"-"~~j'~:\'OD=~'rr:~;?~~;~~~ f "'"~~1~~1
J ={--:l1J iJ:D = II1I ID ==
~..
0 }-...~
10 ~
2 l~·-~
%
~
IS
~
OJQ
BOD
=
DT
XDT
~--·DOD
I--
•
I
z
NOTE:
I. -;:.,-. If TEST
E>nif TEST
(to given by operand)
3. S e:t Sn
'.
( X I.s. bi to'; ope.rand)
2. Set
\-_._------
-r-"-"I
=
Iiti.m
,
4.1.7,~
R.N.!.
_ . J.. ,'-MUS
..
>~
d··
INSTRUCTION SFT- FUNCTIOI\!'~ Af'''-lD -'NTEHNAL REGISTEHS
-.,-~'--'
.
,:r~~c
J-~~,
j~'~!
....... -
.
,i'-'~~~' ',r-·~~r~'
....
x·,~-c· "r~~~
.,
'.r~~~I=""'·::r-··-·C'·~·-r·~·-~·'·
J
1
,.J
,.
L
1
..J
~
o
C--c;
~
2
3
4
5
6
7
9
[J
10
r---f-----r-.--',--.~--]
13
~ of
;l-UN
4---
r----·-~·;_:--.;(~T----I(;--~~·;;)"-··~;~{;. .s~F--._....._-
..··'.. ··· ....i·6·bi·t·'!:.i~,:~; ...... - -,
___ LI - _ · - : - .. · .. · .. ·--- .. -· .. · ....· __ .... ·· .. ·1
~Gbhi·lo".(:
.~ __. . . _.J____.__. . . ._
.._......... , , . . . . . _.. ,,_.,. . . .1
. .i' r
~ J.'.".I'~t_'!'''': .. __ .. 1
JO~
.
D
.j
°l ___ ___ .
1-':1-'
~ '1---- x;~~ --.+~:~'.I ~'::::·::.-;,I
" 0 ill-----o--···--'r-\:;:--C.:l·· . ··«;:;·,:.U·. '. "'1
" -;tor---~-~-=I~~=~---_._·j
L....J.-Jl.!.NL:~_._...Jw_!2.~_:?__ ... ~: ..... "..
lf~-'--'--<----
.----_. ",. _......-.....................,... ".' .
»
--\
j
.......
c","
j
- .....
" - - .•','.- ' • • ' .
''''.0
"
. . . . . . . .'
-o··T~·II~~I~~~i;-;i:~;:i- -,
•
'.
1
: •• ;' '"
.1
•
I
~.--- .-_._1_. -_.....- . -_........ --.-. ,... , 'I
J_~J(b .~_I~i.~-_:~~i~~.~ ......... -... '" .1
"I 0 I~.! ~~_~!.:_ ~I~_~,.i_~:,,:~ d ................ ,
!
.,.,".
__
1',132
I "
bit lIi\:.i'::I:·.,~
!
L~ ,~~=j-¢·r6~~.~~-t·.·;;I;:;-i:~;\':_~:.,o '" __ ......
..
•
,;
',4
, "j- "
~ J
f~
I
, " ~~ .... .i
~ '-l'---I--·'I-'--:-';:.-::-:-;--·--· -:'.:;';~;;-""" .....
"'<>H3 14 15 L1 fc,,/'\L
I ,"~
"
15
C·\11-(-n
A r 11-', ., •
! .... .........
"
,.1 '.' I'\~ \ '''',
_i ...... : .. .-- I \ .-,. . '.
.--.
C·j !', ...
"_ ... t ..-
'i/~
•
o
__._._. '__".".'.
9 '10 1')12 13
.1"
,
'·j-t~rol--·-·~.··-·-~;-(i;l;··~{if-·-·-·--l
I-~\-'~
I Ace LOGiCAL
__ .~J__.__._________t
2
•
t.
0
l '.
.0
.
1
E
_ _.. ___ • __ • _ _ _
;,,;;
c
=-"··;t:~·=i;·~;;·· .'-. :.
·11
.____..__._ _ _ _ _1
o
U'.;
........_ . _ . - . - - - - - _ .-
Vo-r
1'--1
L
r:) gc '---'--1
.l
.
.
c~OI(~lliL::rul
I
;'
!......-."-..... <-... -".~
0"-- ';-1"
32 ..-.---- "'( I:; .~'1~:'- [;~, y.-... 1-',
1
' -;--v ;~ h;:;-:;--;,;,-,;.)-----I
l ' : -.
'
I
L
r:-·-FZ.T~1:·"-;2 r--~! D
____ '_H....
B
.
L_i0 _J
f
1.~
.
.~~L~,.Ir.·~:j,:;=~;;;,~~~:::~~~~=,~·1·
.
,', 1:;
~
1-
t.
fj'. :'--1--"--'-'"
r.r-;f;~;---I
.. : (,
if
--j
'-L -- --:j._-- ~-.-.-
. --------..-~
,
i:::
~2
L
.-.~--------------_-.<.I
t
.. ,.J
.~~.--
., Ir
~l
f!
. .1 . ..:)
.O .I
1_
'-
l\! I
n
Descl.·iptor Formats
--------
T' SF) must not bo accessed
this \'lr:,y J into:.':'!'upt :t'outL'l:;)S use the area in front of SF as working
The stack is designed both to provide temporary 'working spaco
'i-'n';
,."
\ '!-\
.-'-v
-",.
p.,.oc"'du...·
'"
GO
...
'"
1b
Q
(
~, Q: o.•
.....
"' __
fu-·.... ".0va_'U:~;c:tne:
1
. •
• • '!... " .
. ):
arl,'c.u"l1Gi:J,C
G:>:prGssJ.ons
a':l:'::.d
, ....
6 L,fJ c
e1so the space required for procedu:ra calls (se0 Section
Certain
Q
I
orders II e og. 0 S'fACK B, Cause an operand to be staal.ad - SF is advanced
by Z (3:z'-bit) words and thG opera:t,d is stored at the 64-bit wm,'c} specified
by the new value of SFo
'1'heso operands may be ul'lstackaa by specifying the
S'l'ACK as the operand part of an order,
A = STACK - the 64-bit
Gog'",
word at SF is loaded on to the highvh'l.Y ~ end SF is docreased by 20
that all unstacked opol'a.1.cis al~G :;l,t1cumed
be
-;';0
64
0
2 and
6
0
Not0
bits long ..
Ordors which alter SF ere described in Sections
6
L
4Q4p
3~2v
30
6.1-bit
'(;'ord 2.ddross !ol
,
15
1
'1'he Extra Neme Be,se Register }1ffi
The 0xtra name base ;r-sg:1.s ter ~ XNB i is
,
32
hi ts lcmg 0
Bits 2 - 30
hold the address of e 64-bit ,vora 2.L"lywhel"e in the virtual stol~e; bits 0$
""'ay aG NB s;nd SF p except that th2> operand is in the segment defined by
tha 'cop half of XNB (instead of SN)
must not oV0:rflow out of this
J~13
Q
Note thet the addi tiOJl of tho ne,llle
segme:!1t~
or there will be an. interrupt.
is designed to be a base register for non-local
n~ue8
used
C.
ir!
to:.
m~1.n:y
p:C'oc0dul'e, and will often cna..'1.ge its value in e
procedul~e
pzoogl"ams, the top half of
)a~B
vrill be zero (like SN).
which alter XJ."\ffi
~r~
describod in Section
0:;-d01'6
6
0
0
I
In
20
,',
1001
2
s e R;··n;':;,r.~ t
!
6.!\t~-oi t
\"'!ord
rl . ,
14
J..;)
').'11e data descriptor l'egist01'~ D~ is
the
deScl~iptors
64 bits
l'equil'ed for accessing data
an ordor which accesses a ds::ta
stl~uctul'$,
address 101
:1.
lone~ a..'lld is uS0d to hold
structm.'es
0
The operand part of
e-p;:;;cifies a descriptor and a modifier"
'rho deSCl'iptor is loaded into D £u1d then. combined with the rnodifier 'co define
'~ho
siza bnd address of the particular structm:'e"',element Z'equired"
D'atails of the descriptor types and the mechanism for accessing
~J0condary operands are given in Section,s 2
0
8 and 2,,11 - 2Q14G
D also plcys a major part in the ope:z.'ation of tho store-to-s-coZ'e
ol'dol'S
0
1)
in Che..pter
nllllAipulation orders
5.
t".:i.'0
1"',
d,escribed, with the store-to-store orders,
I'"
A literal
opor~,d
appears directly as part of the ordor; if e
I i tal.~al is specified as the operl",.nd part of a e;tore order ~ there \'lill
-l
be
~.h
interrupt 4
There are several alternativ0s:6-hit
(a)
si~1ed
(b)
16-bit unsig;nsd
(c)
16-bit
sig-ned
(d)
3~-bit
unsig.,.ed
(e)
32 - bit
signed
(f)
64-bit
The li tora-Is are copied to ti10 laast 3i§:,'7l.iiica.:;'lt end of the highway"
Tho
rsmaining bits of the higl1way a:;."o$ set to zeres fer unsigned Ii -Corals a.'1.d
to copies of the sign bit fo:.' signed l i tel.'als "
The precise fm,'mat of
Let L1 denote
:wt 1.2 denote
L3
wt 14
L9t
denote
bits to be loaded to highway bits
Ol'dGl'B
__ J
-,
0
16
to high<7ay bits 32
bits to be loaded to highw&..y bits
bits to be loaded
appear as follow8:-
Icr!f lk I
32-bit litel'als
6.6.-bit
literals
,
containing Ii torals is unehpected
denote 16 hits to 03 loaded to highway bits
Then the
16-bi t I i to!'als
16
16
16
Ol'cioI'S
lerl:!: lk I
0
40
150
31
0
4-7 •
630
1)
Variable Operands
v64;
There are two kinds of variable, V32 anel
bi ts &"1(1
64
bits respectively.
The operand part of the order spec:i.fies
the kin,
NB ;,:;>, SF ;;:;>, SETLINK.
Nota that the organisational cOIll1nands, input/output and CTL use
W01~c1S,
hi t
in the nama segment.
Thus when running under the operating system 32-
\'IOl'ds:-
o
15
should not be used when writing in XPL
o
96
Should not be used when using the Autocode machine o
"
In terTIal Regis ter
LJ
G'Per~. Xlds
.d"."1Y internal :;:,'egister may be specified as ths operand for a fetch
order; a stol'e order i:1ay v/rite to most internal registers» except '.:hose
LJ
within the primary opel'and unit, i.e o , MS g HB, C0 9 }GrB, SN, SFp
BH~
A table listing all the :t'egistel's or combinations of registers that
c~m
OS accessod in this way is given in section 102; note that only co,l1plete
u
lines may be accessed s for example, SF cannot be read by itself but
only in combination with SNo
Internal register
oper~~ds m~y
only be used with computational
end s tore to s tore orders, not with ol'ga.'"'lisa tional ord.ers.
L.J
The Internal Register Z is a dummy opere.nd. which is
'l;v.l.~itten
to as a means of suppressing overlap until the order is comp1etee
-1
L
J
LJ
L~
'-,
1
L~
L ..J'
"
,.
.'
'_ I
'I
L
2.6
,Stackad Oparands
When the operand part of the order speoifies
I
r,
STACK,th~
64...bit
word' at SF is loaded on to the highway and thEm SF is deorea.sed by 20
I,
Note that all operands c()ming from STACK are 64 bits lOl'a&;; this doas
l )
not mean tha.t only 64-bit opora.nds may be sant to the stack - shorter
operands will be extended by zeros on the way.
L J
[A store order specj.fying STAC!;': will store the, operand at SF
and then decrease SF by 2.
allowed] •
This is 'not a sensible order, but is
"
L
I
n
n
lJ
L
j
L
!
l
)
L )
,
'
1- )
L ,
l
)
-
Privileged
--
-----------------------
Op0re~ds
privileged operands are used by executiV0 to hold system control
informatiollo
c..J
They can only be s.ccosssd in 0:tscutiv0 mode and are of no
interest to the ordinary programmer.
Access can be made in
~vo
wayso
In the first case, a bass rogister
a.."ld a nalne aloe specified as for a. variable operand; the size is always 64
bits, and the address is calculated exactly as for a v64 variable.
However?
access is made not to tho virtual store of the program but to the local
v-store (i 6 e. U the addr0ss is interpreted as a local V-store address)o
In the second ca.6e 9 the Opel'2Jld part of th0 order is srrACK v the actiOl'l is
exactly the
-,
S8~e
as for other stacked
as a 64-bit word address in th3 local
opere~de,
but SF is now interpreted
V~st9reo
(The local v-store is
described in Chapter 8)0
~,
-'
.'
'-'I
.,
LJ
-~,
LJ
L .J
Lj
~l
L.J
L-)
2 .. 8 .. 1
2.8
Secondary Operands
~-
For a secondary opsr,e.nd, the ops:t'and part of the order specifies
a 64-bit descriptor and a modifier..
)
I:
Normally, the descriptor specifies
Lj'
the type and origin (i.s o , starting address) of the data structure
containing the secondary
operand~
particular operand is required o
and the modifier defines which
For example, if A is a descriptor
specifying a vector of 32-bit elements p then the orders
X
= ACS]
t
fS
= 25;
I:
would load the 25th element (counting from zel o) of A
'-
I
L
j
4
into the fixed-point accumulatoro
Descriptors can define vectors or strings of elenlents of va:l.'ious
sizes; miscellaneous special types are also provided o
The different types
I:
of descriptor are defined in sections 2 .. 1i - 2.140
L
}
i~
;
A descriptor may be specified in the same way as a variable or
"d!ta~ked
operand; it is a.lways 64 bits long, and is loaded into the D
register. Alternatively, the operand part of tho order may specify tha.t
II
the descriptor is already in D; this avoids unnecessary loading of D
if the same descriptor is
u~Gd
for consecutive aecondary oparro.ds o
The modifiel" used is normally I3 or 0 (1.0 4 , no mOdifier) 0
there are special functions (see Chapter
5)
HClwevm.',
{ 1
which allow any opera.nd to be
used as a modifier and also cause a special type of modification o
I
J
l
J
l
)
All
modifiers are interpreted as signed 32-bit fixed-point integers o
When access is made via certain types of descriptor (eog., vectors)
it is possible to check automatically that the modifier (if any) lias in the
range 0 ~ modifier < bound. The bound is held in bits 8-31 of the descl"iptol"Q
A
seconda~y
operand may not be used in conjinctton with the
following functions, D
=>~
XD
=>, nqs =>, NB =>, SF =>, SET LINK
0
rl
l
I
"
i I
"
{
J
.T.r:l11gth of .tho Ol'dOl'S
M ordOl' may bo 16, 32,
O~· 80 b:i,'O;G; lOl'1g.
48
Xi: \'till bo 16 bi ts
long whon: 80 bits
-
~
s~oond~y; b~so ~G~ista~
lo~g~
So
Ii\ g~ ..b:l.t
64...bJ. t U tG:r~l
j
l:i.torai e,."1.d will
In Q.ll other casas,
2.10,,1
r--;I
L i
'ripe 0 - VectOl' D88criptm.'s
Type 0 descriptors are used for vectors of elements of size Ip
4, 8, 16~ 32 or 64 bits.. The descriptor defines the origin of the vector,
the' element size, and
upper bound fm.' the modifier (ioe", the 11umber
aT!
of elements in the vector)..
IT/SIZE!
23
1
The format is:-
lustBC!
1 1
BOU1''ID
L
J
ORIGIN' IN BYTES
32
I'
T = 0
Defines type 0 ..
SIZE
Defines the element
(Coded as follows:011 ::.::
11 0
us
8 bitr;;
S:i.ze
as 111 4~
000::.:: 1 bit;
100 ::.:: 16 bits;
8:>
16~ ;'32 or
010 = 4-
64 hits.
hits~
101 ::.:: 32 bits;
= 6£1_. hi ts ) ~
L)
r,
l _,
rL~
e10~ents
... US =
-;o!::
~
BC
If Be
p~~
::.::
..
up
J..,
3
bits.
ti::0n
mo(::if1G:it~
:-LZ 1'l()"C
....
sco,J...co 0
1, then thOl'G is :no bcu:::-.d
ch.ec!;:()
IJ
upp0r bound for the modifior Q
to
0 f.Xld Be
=0
fJ
othO:;;"";'fise tho2.?e "ill be an in'i:or::.'<.::pt.,
I'
LJ
1_ I
ffiUSt
start on
&"
byte bounna.:cy"
to SIZE and US) o.nd c:,clded to the origin to give the address of the
Type 1 desCl'iptors are uS3d for strings of 8 hit elements"
The format; ia:-
descriptor defines tho o:;;:>;tgin. O-l"ld l.angth of the string..
ITlSIZE!
IE~GTH
1
T =1
SIZE
"',
32
Doiines type 1u
Must define the;') ele:nent size as
\vill occur
"
ORIGTN' IN BYTES
1
1
'rhe
8
bits (011), elsa an interrupt
i)
lENGTH
LSNGTH defines the numbe~' of elements in the addressed st:dng ..
ORIGIN
Defines a base
Action:
G.cldr0ss~
as in type 0 0
The r"odiiier (if any) is added to the ol'igin to gi V0 the address
of the f1tt'.rt of tho string
0
LENGTH defines the length of tho
!"J.O bour.:d ch.6clcing 4:
,
'l'he f~.nD.l op3!'and is
<:f.
string of 8-bi t elements
0
In store to
sto:;;:>e o::,aerG the '\7hole s'c:;"ing \7il1 be used as t:!'le operand (see Chapter
In computatio.'lnl orders, the opera..."1.d can. be at mcst
the strh1g is le3s -ens
64 bits, then it is zero
64
5)
0
bits long; if
filled for fetch? tl'unc~Lted
\1i th zGrO-Cb3cki:1.g :[0:;:" GtO!'0; if th:;; st:;;"ing is longer than
64
hits $ just
the first 6.q. bits ':::I th0 zt::;:'ing 8,re loaded on to or stored from the highwayo
-,
- l
~pe
2 - Descriptor Descriptors
Type 2 descriptors are identical with type 0 descriptors
(except that T = 2· instead of 0).
\TISIZEI
IUS!BCI
2.3
1 1 1
BOUND
ORIGIN IN BYTES
24
It is conventiQnal to use type 2 descriptors
32
to
address vectors
containing descriptors; type 0 is used for vectors containing data.
-.-~--
-.
10.8.72
,
r~
,
L j
u
Typa
~
- '\iisc'311::U""1.90US
Descriptor~
u
Typo 300 Ree.l Addr0ss
- - - UNIT NillImER
I
i
I
I
I
I
U
"I
!
LJ
I
J
,Tp T?
=
3v
0
T
T'
BOUND
2
6
24
SPARE
- : - - V-STORE
I
- - - REAL ADDRESS IN BYTES
I
I
1 I I
4 12 11 i
32
D0fine type 3 0 0.
BG"uND
Upper bound for modifier a.s in Type 0 0
ORIGIN
Co.":~e.ins
the real
stor~
address (the physical address ~ not the
"I
vi:-..~tuS1.1 store
LJ
significant bits are ignored
address) of a 64-bi t operand 0
The three least
0'
Actiot~: The op0raud is E),ccossed in th0
same' way as a type 0 64-bit element.
Tho lUo(liiiel' is always scaled, and bound checked if bit BeH! in DOD
U
is set to
I
0
Type 3,,0 descriptors may only be used in Executive mode o
0
"I
U
J
J
l
J
"
.,
\.'
,I
T
2
BOUND
Upp01.' hound
6
32
3:or modifier M in type
ORIGIN, Dofinas a 64-bit word address.
bitz are
ORIGIN IN BYTES
i~"l10red
00
The three least significant
0
Action.: ACGos::J is made in o:r:a.ctly the sama way as
£01"
a. type 0
elemont (nssuming US = Be = 0, so that tho modifier is
e.nd hound-chocI<;sd if bit BcrU in DOD is set to O.
~o~d
64-bi t
scs.led~
Note that the
lios on ~ 64-bit ~ord boundaryo
'11110 Gloccossing mechanism for this descriptor bypasses ell opel'and
bu~fel's, and
always accosses the real store corresponding to the
definod virtual address.
e;.:ocutivo procedures 0
This type of e?cess is needed in some
,
I
"
T
BOUN'D
ORIGIN IN BYTES I
6
T, Tt
= 3,
'I
32
:-,
Z definG type 302
BOlllilJ
Upper bound toJ:.· modifier as in type 0
ORIGIN
Defines a 64-bit word address; the three least significant bits
~J
,l
LJ
Action: Acc0ss is made
~n
exactly the same way as for type 301
descript02.·s, bypassing the operand bufiel"S 0
"-I
In addition, for
a fetch o:rdor, the value of the 64-bit word in the store is
finally set to zero o
I'
11
LJ
x
T
2
ORIGIN IN BYTES I
6
11
32
Li
x
Unused
ORIGIN
Defines a 32-bit word address; the two least significant bits
l
a!.'s ig;lored ..
Actio:;).: rrhe
J
II
LJ
64-bi t elomont at the ol"igin address is loaded into D a...""ld
L
then in terp:;;'€lted according to i t9 type
be indirect,
iT!
t1hich case the
whol~
0
process is repeated o
a modifier is specified, the modification
final (not indireot) stage c
J
The new descriptor may
trutOS
",.
If
place at the
il
I
J
il
'f
lJ
l J
11
L I
Ii
~_
1
11
~
J
J
Types 304 - 3.31
Procedure Call
'1' t
T
2
6
x
ORIGIN IN BYTES
32
Tp T' = 3, 4 - 31 Define the procedure call type.
X
(32 - 63 are illegal)G
Not usen.
ORIGIN Contains the address of the 'procedure call vector'.
u
The two
least significant bits of the origin field are ignored.
Action: iVhen an attempt is made to access an operands the hardware forces
a procedure call to the address held in the first 32-bit 'Word of
the vector, with the return link pointing to the instruction
attempting to make the access o
The origin is not modified (even
i f a modifier i3 specified by the
J
1
part of the order) 0
The type bits in D are reset to a type 0 32-bit vector with
-,
J
opel~and
US = BC
=0
0
The X and ORIGIN fields are unaltered o
Oi'l.e example of the use of the procedure ;~p.ll descriptor is an
If the
implementation of an Algol formal parameter called by name.
cOl.-rosponding e.ctuo.l parameter is a simple variable, then the parametel'
descriptor can be a normal type '0 desoriptor 0
But if the actual pararr;eter
is an e:{pression i then the descriptor will be a procedul'a call to code
which eva.luates the expression.
The value will be stored in some suitable
store location end D replaced by a type 0 descriptor pointing to it;
finally, the
tn set' bit in the stored link
and an EXIT obeyed"
(cfo~
Section
6
0
2) is set,
The order ca.using the procedure call will be re-obeyed -
th0 tD set t bit pl'events reloading of D and defines that the current value
of D describes the required operand c
(The 'D set? bit is automa.tically reset.
to 0)0
Note that a procedure call descriptor may be modified; the modification
'Will take place when the olOder is re-obeyed after exi t
fl~om
the procedure"
L
j
l J
fi
ri
l
j
I'
l )
[,
I J
11
Ii
l
J
Ii
I J
Ii
n
I J
--,
,
I
II
L I
!
J
3.1.1
!
J
Chapter 3 The B-Arithmetic
~1
i
I
LJ
There is a separate 32-bit B-arithmatic unit which operates on
the modifier register Bo
Although B is used mainly for modification
it is also used for some of the simpler integer arithmetic, for e,crumple,
i = i + 1.
The bits of B are numbered from 0 on the left hand (most
I
I
LJ
si~1ificant
end).
dO
l
dl
d2
d30 d31
1____________________________ 1
LJ
The operand connect:,on to the B-ari thmetic unit is from the least
significant 32 bits of the highway (bits 32 - 63) •
. The B-ari thmetic unit performs sig;ned 2' s complement arithmetic.
Thus B may take values in the range -2 ~". 31 to 2 l' 31 - 1.
If p after
any arithmetic operation, the true result is outside this range, the
overflow bit is set"
The overflow bit and a bit \.,hich is used to inhibit
the interrupt resulting from overflow are digits
5
and 0 of BOD (see 1.1 0 2)0
Thus digit 5 of BOD is set to a one if overflow occurs and the interrupt
will be inhibi'ced if digit 0 is also set to a one o
BOD are not
All othel.' digits of
signific~lt.
l
~--.---
..
"
II
~rhe
3Q2
B-Instruction.s
The order code p~ovid0a for 16 B-iunctions.
Gnly 14 of these
ase implemented on iViU5 snd the rest are dUlTh"11y instructions 0
rl
The
instructions nro:-
rl
LOAD (=)
Load B from the least significant 32 bits of the highway"
'I .
c
I
L
J
L
J
h11W & DECREAiENT (::::')
Load B from the lea.st significant 32 bits of the highway
then subtract 10
If
~~
overflow occurs digit 5 of BOD
is set"
ST ACre & ill.iID (*=)
'I'he stack front regis tel' (S17) is first a.dvanced by 20
The contents of B are pI,aced on the highway as for a
order (see below)&
This is then sent to the 64-bit \'lord
whose fLddress specified by the new vs..lue of SF"
",
8t01'0
Finally 1
the: 'operand
is loa.ded into B as in the load order (see ' ..
·~r,
LJ
.~,t
above)"
LJ
sri'Of'CE (=»
rrhe content of B is pla.ced on the least sig;nificant
bits (bits 32 -
63) of the highway and
32
L
J
zeros aTe placed
II
0:. tho most significa.T'!t 32 hits (0 - 31)0
The operan.d
L J
specifies the destination of this information o
L
,1I..1)D (-:-)
Tho operand is added to B, leaving the result in Eo
If
J
ri
an overflow occurs, then digit 5 of BOD is set Q
L
J
,i
SUBTHACT ( ... )
L!
The opera.nd is subtracted from B leaving the result in
!f ru"l ove;t.4flow occurs ~ then digit
MUJJrrJ?LY (*)
5 of
B~
BOD is set 0
ri
,.
B is multiplied by the operai1.d to produce a 32-bi t result
in B Which is the least
si~~ific~~t
bits of the true
a.~swer
and digit
L i
32 bits of the true
64 bits igned a."l.6Wer.. If the true product has more thru~
32 signific~~t bits, then B contains the least significp~t
32
I,
5 of
BOD is seto
10 8
0
0
72
L I
LJ
, i
--'
~I
DIVIDE (;)
A dummy instruction.
NON-EQUIVALENCE
(z.>
B ~~d the operand are non-equivalenced to produce a
result in B ..
-~
,
,
OR (V)
B
~d
the operand are ored to produce a result in B.
AND (&)
~l
B and the operand are anded to produce a result in
'l
Bo
SHIFT (1'1.)
B ''.'!ill be shifted arithmetically (left) by the
number of places specified by the signed iriteger in
u
digi ts
57-63
of the operand.
If overflow occm's digi t
.5 of BOD is seto
cmIPARE (CC}lP)
The
oper~.nd
is subtl'acted fl.'om Eo
Bits '1'1 GI.nd '1'2 of
the test register are then set iTom the result of the
subtraction (see section
6 4).
0
A true Tesult is
:?.lways generated and no overflow may occur.
The
overflow hit in BOD is copied to bit TO of 'che tost
LJ
register",
'fhe contents of B are not altered.
RE~lERSE SUBTRACT (e)
B
Bo
is subtracted from the opera.."1d leaving the result in
If an overflow occurs, then digit 5 of BOD is seto
CC:1PARE 8;; INCREM1;:NT (Cn-rc)
..4. compare opsi:,ation is performed (see above) then B is
incremented by 1.
LJ
Ii B overflows as a result of being
incremented then digit
5
of BOD ·is set after the compal'e
operation has been completed o
u
A dunur.y instruction.,
Ii
I J
,
)
I,
L
I
II
LI
,)
I J
il
~___ J
!
,J
Ci12.pter 4LJ
4.1 The
!~ccumulator
/tri thmotic
Accu:;';1ulator fU.).d i"1:8 Associated Registers
16
The function code contains a set of
functions for each of the
followinr; kinds of aritlunetic:-
fixed point signed
fixed point unsigned
floating point
decimal
In 1;1U5 there arc two associated registers:-
X which is used by the sig.ned fixed point m'ders
A which is used by the unsigned fixed point, floating point
~~d
decimal o1"'d01"'8 0
,-J
Each accumulator register is conceptually 64 bits long but digits
o -
u
I
J
31 of X will no'c exist on IliUS.
Thera are
t,,\'10
other visible 64-oit
rOGisters in the arithmetic unit, namely AOD a.'1.d AEX..
The hits of
AOD aro conce:rned mainly with interrupts whereas P.EX (the accumulator
o::tcns::'on .regist0:i.') serves to hold the least signiiica:.'1t pal'j: of double
lCl1.[1;th l'08ul"tn
8"(;0::"0
:::";ld
0
Because the accumulator
~ jl/
is shered p the load an.d
functions wouid bo the same in the fixed point unsigned, decimal
ilo..:>..ti:;'1g poil1.t instruction se-;;s.
Therefore the load and store
functioJ:1.s :i.11. the ibwd point unsigned set are made to ope:rate on AOD
:it is convEll1ien-i; to oonsider the operand for each function to 'be
tho 64-bit s.ccuxnulator input buffer AlB.
,
~.1.cc\.imulc.tol~
fUl1.ctions will be described by
Thus the ope:;.~ation of -;;h6
rafe:l.~ence
to the registe:rs:-
il
: J
402
i !
Allocation of Digits in ADD
f,
J
l
[,
digit
51
52
53
Operand size (O/! memling 32/64 bits)
L !
Inhibit floating point overflow interrupt
Inhibi t floating point undad'lo,'! interrupt
J
L
Inhibi t fixed point overflow interrupt·
55
Inhibit decimal overflow interrupt
56
Inhibit zero divide interrupt
57
58
59
60
61
62
Floating point overflo·v! indicator
63
Floating point underflow indicator
L J
Fixed point overflow indicator
rl
r~cimal overflow ind~cator
L I
Zero divide indicator
Inhibit rounding
rl
l.,
Double length.:!:
"
LJ
I:
L
L
j
j
L j
1-'
L :
~_ J
u
l.J
r;rul-::::i.plication 2..nd diviGion, the binary point is at the least
dO
q2·~·;::J:.
t
ell
d31
~----~.-------------,"""'-
I
i
.l...;-_ __
t_
binary point
si£~~
--- .....,,........, ..
I
l~
:r!'
~--
I
I
b:i.ns.ry point
d?d
-......-
I
q::-~.·-,b:.t
.:.~
...
I
A
I
binary point
.~
J
:5 0
6,.;, . ·~Qi t
r1:1.
_ d6;3
'~----------------------~'I
I
I
-.l
binary point
(0) Decimal
Dat~
15
is stored in si2;11-modulu6 form o
or
1.;_
b:l ts at the least siwdficant end ~
binaxy (0 .:: 0000, 1
means
-ve~
=.
000:1.9
0
"
D
Each decimal digit is coded in
=.
9
1901); the, sig;n code is 1101
8.11 other combinations mean +ve (1111
i''s
preferred) ~
multiplication and division:> the decimal point is at the least
significant end,
i.0~~
, J
4- bits each; and the sig,-n occupies
~l
decimal digits occupying
The modulus consists c.f
For
II
data is interpreted as an intagaT.
II
,
* -.;-~.:2-1ji t
d2.j.~·27 dz8-?1 .
00-::1 d/r-;-I
I DO 1 Dl 1
I
$'
,,00
i D6
i S
A ~\
1 I
!
"1
I
sig:.1.
decimal point
I'
d1·-7....,...__'--______--:_d..",;.t-i6-:--..,,'1"".q..l...;o_cl_6-::o:--_6-:.,..;;:\
dO-J
~?4:bi t
I
DO
I
Dl I
! s
!
ll. l~
i I
I
decimal point
I Dl4-
11
(d) Floating-poil!t
u
2;''1d
is
Q,S
SU1.
unsig:G.ou 11-bi t· ii7.tager
00000000000
->
-102t;_
00000000001
->
-1023
",rn.i~'1't!s
',.
o
10000000000
->
11111i~i11:1.i
->
o
u
1023
-,
J
1
-:~:_>"A~;~~_ .~
.:..
..- - - -
dO
dl
dl0 d11 d12
d6q
----~------.----------~--~----~--~--------------------------~--~
1
I
I
m~?}tissa
The Sign.od Fi::i.ed Po~.nt Accll\ntll~to:L' O;,.~do:i.'G
•
J
•
J
The;; a:d thmotio functions in this z:ot a.ssumo X and tho oporb;nd
to be s ignod
i~1. teg0l~s
0
Copy digits 32 - 63 from
LOAD (::::)
ArB to
c J
LOAD DOUBLE (=')
Dumnty instruotion.
J
L
sr.l'ACK AND LOAD
<~~=)
63 of the ne:;~t £1'00 6t:j.··bi t
word on tho staal.. making digi tG 0 ... 31 in this "(!lo:t'd
Sto.01, X in digi to 32 ..
Than 0p0l'a:to
zero o
STORE (=»
for
aD
ri
,'.
)
'
wAD.
Copy X to digi tEl 32 - 63 of the Highway and
to
2:0:1;'00
digits 0 - 31 of the Highway.
.i-lDD (+)
Digi 1:3 32 r0tul~l10d;
ADD is
63 of AID
to Xo
SQt
a:i:'O addod to
X al'l.d the a:'oaul t :l.s
!f -the addiUon oV€ll'flo'lld, d:1.gi t
59
O:i~
In this case the result in X 'will bo the
0
J
I
II
leo.st 13ignifioa!lt 32 bits of a 3Z·. . bi t o;nS'i'IO:r.
SUB'I'RAC'r (-)
Digi ts 32 -
63 of
A:£B are subtl.'E).cted from X and the
:i'Gault is l'etu:rned to 21::0
digit
iJULT (*)
59
If tho
:;.~asul·l;
ovol'flo,\'is,
of AOD is set.
X is multiplied by digito 32, ...
63
of AlB
·to fo=-:',n a
signod sil.gle length re81.11 t in
ovel'flows, digit 59 of ADD is set ~ and the result is
the least siguifica..'1.t 32 bits
DIVIDE (j>
X is divided by digits 32 - 63 of AlB, to :fm.'m a
C!uotient in X, v/hich will be rounded down"
divisor is zero, than digit
61
1f the
of ADD is set~ ~~~nd
X will be unal tared ..
N02{ EQUIVALENCE
OR (OR.)
DUiTImy
instructions"
- l
J
11
Digits
59 - 63 of
AYB are interpreted as a signed binc.:::.'Y
intGgsr 'which sp3cifies the number of decimo.l pl:;:;,co3 by
which A is to be shifted (left).
over digits 0 to
59.
Digits 60
,-
a left shift overflows digit 60 of AOD is set ..
:Dtl~1uny
COMPARE ADD
Digits
AOD o
,- -
The shift is logical
i:nstruction oK
51 - 63
of ArB are anded with digits
51 - 63
of
The overflow digit of the test register will be
set to Ojl depending upon the result being non-::::;erojze:.:'oo
:1
L
J
cmlPARE (CG:flP)
p'. is interpl~0ted us a decima,l number according to the
63) of Ao
is set as the sign (bits 60
&
The logical
of A a.."1d AlB is formed, and bi tTl of the
register is set according as the result is
to zero o
Bit T
o
-eElS t
= or
1
of the test register is set to bit
60 of AOD (decimal overflow)o
U}iPACK
This instruction 3e-::s AEX (32 - 59) = ArB (32 - 59)
~Ld
.A.EX
0
-
AEX (60 - 63) = AlB (60 - 63) v A (0 - 3)Q
(0 - 31) are unaltered • It also shifts digits
59 of
A
four places lefto
are set zero and digits 60
REVERSE DIVIDE (¢)
Li
L~
u
Duml~Y
instructicn·o
l""
Digits 56
63 unaltered
- 59
0
of A
'I
4,,7
~lon.ti!lg-Pc>int
Tho ACC
Acculr,ula'.::o:e OJ.'dors
For soma of the floating-point a:l'i thn1eti~'f instl~uc-::ions ~ A ;::'''ld
AEX aro regarded as a doublo-length result rogistor, A holdil''l.g tho
11,OSt
significant half ~ a..'1d AEX tho least significant
~uli
Both wilL
0
i
I
have tho format of page 403D3Q
In ull instructiono AlB will
51 of AOD is one.
fOl~ tho
64-bit operand if digit
If ADD is zero digit3 32 - 63 of AIB will form tho
.
most signiiicant part of tha 6.d.-bit opora:..d· of '\;ihich tho other half
instj.~uctiCl1S
The operation of tho floating point
upon the setting of digits
62
al1.d
63 of AOD o
sp0cial doub10 length vorsio.1s of c.dd ",nd
~I.d
is ignored by' all other
subtl~act
I
,
are dep0:ldent
62 is tho il..hibit
into digit 63 of
Digit
Rounding:13 p0rformod by fOl'cing 1
rounding digit.
1 j
and roverso subtract
opel~a tions ~
'-,
LOAD SINGLE (=)
51 of AOD is set to ze" o, then digits
32 - 63 of AIB a .... e copied to digits 0 - 31 of A.
Digits 32 - 63 of A a .... e cloared~
Fi .... st, digit
4
L
,
"
W.A..D DOUBLE (= t
)
Fi .... st, digit
51
of ADD is sot to a one, then AIB
is copied to AI>
A (or digits 0 - 31 of A) is s tackod then A
is loaood as in = / =V if digit
Digit
s'rORE (=»
51
51
of AOD is 0/1 0
of AOD is unaltered Q
A (0 .... digits 0 - 31 of A, az for X) i~ stored
depending on whether digit
51
of AOD is i
(or 0)0
,--
P-.DD (+)
The oper2.."'1d f:-0111· AlB is addod to JJio
l1'irDt the
GxpO;i1en ts of A llil.d AIB al'-'e ccmpo...:i.~0d ~"1cl the e:-:pOl'1011 t
field of A is :i,'eplaced by the larger
0
The ma.""1tissa
associated with the srr'.a,ller eXpOn8l1.t is then shifted
right by the :.lumneA' of hexadecimal pluces given by
the exponent difference o
Also tho digits which are
shifted out are placed in tho ma\'1tissa field of AEX
the res'c of AEX being clea:o..':;d.
of A is set to the sum of the
The IM.ntissa field
mantiss~.
fields of A
B..'1d AlB (ana of which may have be:e,n shifted).
nOl'J:m.,liss.tion shifts 'l.'lhich follow apply
shift of
13
he:~8.decimc,1
places.
<:~crOS8
The
the
If both ma.."1.tissa
fields are zero a stD..Tldard flo<:.ting point zero is
geneZ'ated (403.3)0
The. exponents of A and AEX 8,1'e
both set to the exponent of .the double length result
- 1
and rounding is porformed as described above o
When digit 63 of ADD is set and A e..."1.d AEX contain a
double length number smallsr t11.o..."1. AlB a correct tmroundod
double length result will be formed o
If either of the above C:luse exponent overflmv/tmderflow
digit
57/58
of AOD will be seto
- 1
SUBTRACT (-)
The operand from the highwcy is subtracted from Ao
~J
The operation proceeds in the same general
j:lJJD 0
tho
1fULTIPLY
However, if tho numbe:1' to be subtrl:,c ted is
it is nogated and thon tho add operation
smal1er~
(~<)
A is mul tipliEld by the oper2.:.""1d to give a double length
result in A rolci
ft~X.
This result is standardisedp
and AEX exponent BElt as above o
if digit
62
of AOD is not set..
(0Z' underflow) digit
- 1
u
as
is performed Q
--1
LJ
w~y
57
Rounding will occur
On exponent overflm:.r
~/58) of ADD is
seta
DIVIDS (j)
A is divided by the
to gi va a single lengtl1
0p0:;"f!.l."1d
stendo.rdisad (possibly :i:o:.mded) result in ,P!..o
divisor io
2001'0
digit
61 of J.,.OD
is
overflow or undiElrflow occurs digit
s~t
or if
. If
t;'ho
o:q;O~:"&:'lt
. j
57 (158) of AGD
is set ..
NON EQUIVPJENCE (E)
, J
Tn0 J..·c8u1 t of combining A and AlB with logical
.E
L j
is l'etuTned to Ao
OR (V)
The result of combining f. an.d AlB with the logical V
is retu:l."J:lod to A"
SHIFT (a)
A is shifted circularly (left) by the number of places
specified by digits 58 ~ 63 of AlB"
pJ{D (&)
J.·esult of combiIl.ing. A :::;':l1d AlB "lith a logical
. The
&; :tS
returned to AG
REVERSE SUBTRACT (e)
'1'his is the
Sallle
as SUBTRACT g
subtracted from the op0ra..."'ld
cm~p J.lRE (CGvl?)
A is compa.red wi th the
registor is setQ
CONVERT (CGN-V)
h';
J_",
""'- L:.:>
that A is
Q
ope:;,~~~.d
in AlB and the tes t
Both are assuMed to be floatingTO of the test :;,~egister is set if any
point numbers o
of
e~:cept
J"'7 , J"0° ,
il
61
are set"
L
j
Tho only conversion function provided in the
floating-point set is one which converts the integer
part of A to a signed
fi::;~ed
!
L
j
point number leaving the
If the result is too big digit
result in PiliX o
L
59 of
ADD is set,.
REVERSE DIVIDE (0)
This is the
is divided by
s~~e
as DIVIDE except that the
op0r~ld
A~
il
~.
I
i
U
!
LJ
I
This chapt0:i.' defines the registGrs Dp XD a,'ld DOD (Sectio:::.
5
0
2) s..,.d dsscribos the ordors
(c) S'l:01'0 to Store
(Section 505)
The
:i.'I~giste::·
mCl1ip'l11ation.
ol~ders
are concerned with loading
are co:wo:rnod ,lith modifyil1g descriptors a>"1.d accessing elements
u
Cl'10 stl"i11g to. E..lLoths!"', C:t-
CClnpE~il1.g
"(:\70 strings
G
Tl1G registers
D a:-.d XD aro used to hold the r'loscrip'col's of the stl'ings.
",
7ho STACK ordo= is described in Section 503, chiefly
because it isn't described anywhere Gls0 0
'rhis cha.pter
diff(n~ont
eSSUfilOS
tOed; the reader is familiar with tho
types of. d~scriptor defined in s0ctions Z~11
",
_-1
I
_1
-,
j
~
.J
--,
J
-,
J
I
J
10 0 8.7"2
Intornal
:) 02
i~ef;istors
in the Secondary Operand
Ul~i t
(SEOP)
7110 two main registers in the SEOP are D and XD.
64 bits long and are used to hold
are both
I
d63
TYP}~
BOUND (DB)
24
ORIGIN (DO)
32
TYPE
BOUND (XDB)
ORIGIi.'l' (XDO)
24-
32
-8
()
0
fol1owin~
The
notation is used for various parts of D, XD:-
(d3Z-63)
the orip;in field of XD
(d3Z-63)
D''''''
0
tll0 bound
field of
(d8-3 1 )
XDB
the bound
field of XD
XDO
tllt~
lYf
XDT
J
I
the origin lield of D
t"I'....,
l-'U
L
rleseriptors~ so they
dO
XD
J
ann origin fields as shovm below:-
havo typo, bound
D
~
They
])
top half of D
the top half. of XD
(d8-31)
(dO-3 1 )
(dO-31 )
The only 0'[:h01" 1".:,.gistoX' in SEOP which can be used by the p::,,'ograGlmer
:t~:;
DDD;
DO:D~
Sto~e
DB ;;:::
Lead the bmllld of D (bits
D in bits
of the oporai1.d.
XDO
XD
::
,;\.!;B
-
Note:
stOl'O
D at new SF)"
of the ope:t'a.nd 0
of the operand g
8-31) fl'om
bits
40-63
The rest of D is unal t0red 0
)
As for DO
::
XD =>
of the op~rand 0
of D are unaltered.
Load D from bits
LJ
32·-63
=,
D
=,
D =>p DB = but operate
on XD instead of Do
r
J
So:ne of tIl'';>S0 m.'dors may blS used wi th secondary opcrands;,
Pcr 8[3] u.:l.d S[O]
DO == J
D-..::~
op0r"1..1·1ds~
the effect is as follows:-
DB=:
D 1.7ill fi::.rst be loeded with the S operand descriptor; then
tho socondary operand will be acceslJed and will replace
the \'.'1':.ole 'or pert of the new value of Do
(b)
D *==
The
~):dginel
contents of D will be stacked before the
,S descript.or is lqaded into Do
(c)
X.DO
=,
AD
=$
XDB
=
I'lork as G:i:pectad 0
The ol'de:cs D =>
opel'and (S[B] ~
<1J,..d
S(oJ,
XD => ma.y not be combined with uny secondary
D[B] or nEo]);,
"
UYono of those o:rders mo.y be u::.;ed vIi tl1 socondary opel'andsJ,
"
L
Uscs bits
:::0:.'
32-63
t:.1e descriptor in D"
(~ftor
origin field
d0S0;.~iptor8) ~
The modifier is added to ·tho
scaling if US = 0 in type 0 or Z
aD.a subtracted f:l.'om tho bound field
A
Q
l :
bomld check in:i::errupt will occur unless 0 < mociiiiel' <
b01..l:r:.d (2.ssuraing bound checking is not inhibited) (';
The
bo"1ci
ol'dcl'S
p
copy) ~
C~l~ists
of tb0 specified byte rapestad as often as
n0cassa~1.
~l
.J
The table look-up
orci0X' SC2.rtS
',\
:::'~:,~,
--,.~
....
:,:/,S~~
------
, i
~
p:.~ocessed
by the
O:!~d01~,
bi ts C01'x'espena i:ng
u
u
,~
LJ
lo~2~72
~~€(-Str.~ng
Orders
For 2.11
strin~-string
orders, XD contains the source st:!'"l.::2:
desc::"iptor a,n.d D tito destination string descriptor
lUU3':;
htrl/0 type
o~ 1
;\
or :2 and elemellt size 8 bits, othe!'v!ise ths!'e
,\7ill be an I'l'S interrupt.,
~1d
The descripto::s
0
J
I
The operand defines the MASK (see abovo)
The FILLER is not in fact used for 2.11 the orde!'zo
a FILLER.,
lJ
OPERA.I'JD
\ J
l )
If the sourco
nlove one byte from source to destinationo
string is thfj null st:ring, ;nove FILLEn to dastination
If DB ::: 0 there vlill be a BCI{ in terl.·upt 0
Updates
l)O~
Q
DB~
XDO p YJ)Bc
,,--,,
[if DB ::: 0 then ByH interrupt
L J
if XDB :::: 0 1:h0::1 (FILlER :::> DrO]; MOD 1)
r~
,
19180
(YJ)[O]:::>
I
D[O]; MOD 1; ki'iOD 1)]
L _,
c1'3stination there 'will be an SSG interrupt; but note that;
this will simply' i:sl'minate the operation if the inh:l.bi t
bit SSS! is seto
Updates
DO~
DB, XDO, XDB ..
[Li:
g
eJ.~
(KDLO] :::> D[O]; UOD 1; XlViOD 1); -> L1)]
DB
P
0 then ( i f XDB ::: 0 than SSS
L ,
interl~upt
l J
r- ,
,
Moves source to destina.tion o
'
If source runs out, then uses
~- ,
XDBo
'l
[L1: if DB l' 0 then (SMVB OPE Rf:1w ; -> Ll) j
L:
, !
i
j
-,
J
SQ,lP
Compal'~S
in
'Ci70
I
LJ
corresponding bytes 0
If source
out ~ FILillrt :i.e:;
l't.!nS
'l'he tost rogister is set = 0 if no iboqunlity
used 0
I
source c.nd destination strings loo1dng for inGCluaJj:t;y
iou.\'ld ~ > 0 if sourco byte > des tination byte p < 0 if
J.S
50U::CO
byte < destination byte; foX' comparison ptlrpOSef; 3 the bytos
I
J
D.~ce
tre8,ted as ullsign(;)d integers.
DO p DB, XDO p XDB are
updated 0
[Ll:
if DB
-
=0
i f XD3
=.:
then (T
= v=~.
-> T4)'
-·!'of 9
,
0 then (if FILLER
~
D[O] then -> L2 else
(1Il0D 1; ->, Ll
~lsG i f XD[o] ~
»
D[O] then -> L3 elso (MOD 1;
X?l!OD 1; -> L1);
"-~1
I
L3: if XD[O]
I
-'--
els0
T
= '>i
;
J
80U1"C0
and d0stination are logicl?lly combined and the :cosult,
stoZ'0cl in destination 0
fm~
g D[O]; MOD 1; ::S]{:OD 1; -> Ll)]
r,
I
,
•.
J
'.~\
,--,,
string
'wiIl be
:;);:1
ITS' interrupt; XD is not used
doscr~pto~
i J
0
(J
d6'.)
..)
OPER;\ITv
!tlASK
BYTE
I J
-------~--------
l
a:re-
ltpd~.tGd
.J
Q
r-
]
L ;
c)
"
L.I
u
---,
I
~J
D 'i18.Y cOiltain
C.ii)'
d08C:i.':1.ptor
0
The opel'al1.d conto.:1.wJ no
o';;11c:: tnc,l;. the L[ASK~ speci:Eied as usual in bits
i(L;:Or-"~CI,~', :~'.:
48-550'
!
'c
J
.J
~
I
I
contain. a byte V'<:ic\:or doscriptor 0
[Ll:
:J.I
1mB? 0 thZln (D(XD[O]] :::> XD[O]; XXiOD 1~ .,.> i,:C)]
If tll0
\.J
lo~. s·;;
If no 1 ).s :fo:.r::'=-~
.,
D "'lill
.!.."
of D(XD[O]] :;:: 0 thS
u
else BN = 0)]
'. ..J
._J
~,
;unspecified manner 0
_J
j
(~G.ICD
C'
:.:
.) Q.J
This ordex" enables a fast 80 [:.n. to be mad0 fOl. .
equal to the operand.
6
tXt.1. 01cn~::~:;;t
D contains a descr5,ptor which
the 'caol0 - origin in DO, lengt;h in DB.
in byte 1.mits.
Q
d8J:'Ln·:):~
71'.0 long'j;:l is
oxP:::'c:,;;:;e,~
'1'110 descriptor must have typo 0 or :? :::'::VI
hi ts corr0Gponning to 11 s
in the MASK are
with each ,31eTJ1ent of the table in
i~no:;;'0(;
tm.'l'l. :f.Ol'
e}i3EKn,·;;
r
1
,
j
0
eCiClali ty
,-
(U:.1('[8.['
,
I
If no equality is found, then 'Chl11sl'!t
found, with the bound field updated.
[Ll: if 1)13 := 0 tl10n T
~
'1
> t else
r
'LUi] truces operands directly Leorn stor,2>"
L
J
,~
:;
I J
l. !
---_.:;;-..,
eJ.:""
0
I
I~J
~I
(ci)
(e) Spsoial
LJ
J
__ I
LJ
o~dsrG.
_~
J.
6
9
N'
7
l
'-1
In the following ol'deX'8, it !JhC(l:lci to
remembered that the least significant hit of each
is pOl'manOi1'l;ly
so that the least sign.ifica'·'lt bit of the operal.1.d nill have
201'O D
N13
-
:Coarl
}ID f 1--' orC!
SF
:::
Lead
SI:~
--
Xl'fB
registoj,~
bits j<~8
fY'ol1l bits lt8
,
ll,ad }J-lB f.l"om bits
32
63 of
63 of
:;10
effect"
th0 opel'and o
the operand 0
63 of the
op01'and o
NB+
r 1
is
8J'?
-
Nt:{ +-
1:'0t
allowed)
Add liB to
in t(:n'X'upt
XB
-
S:B -r
1
0';'1-
Add SF to
0
("J=.)e1:Oj~d
bits 4.8
f;': €'i.;:r20n t
oV0j.~i'low
opeJ..~a:n.d
bits
48
- 6Q
..... 9
:'11'.d sto):'s
tho
.~ ~,..,
rt=;sl:}:2;
..~ l;!,
~~6su.l t
i~"'l ~;!~J ;~
Sl? 3
0
-
63?
f:;md
store t110
interrupt on DElgment overflow"
l
b'ut th(-;l opor::::nd is
2.
signed 16-bi t ird.:eger
I
r
0
NB =>
The opel"?.nd may l:.ct bo
opsl-"tU1.d
.( .,
{:I
SF ::=>
As for rYE =>1 but 8to:;.'e SN
Xl([B =>
ft.J3
f():l:'
NB
=>,
~J1d
SF'o
but store (all 32 bits of) X"NB"
SN :::::
l
:
L_
i
I
LJ
I
6 7
r.'
1
(;
J
U
L.
Ir!11ibi t Program Fattl ts ,
J
This
(lIS -
o~d9r
various bits of hlS to 0 or 1
S0~S
d0~8n~~~~ ~p~~
oi'cs
o < i
~J
,
i, n.)
if
!'·:6
c:] s :::-::~1. cl '..... ~" .,-<- (, .J
;.
if
OPS:':'f);'ld
;:) )
.:...;~
'Di ,.~
( c)
j
l j
I
U
( .~~8
(56
-;-
i
\
/
= 0.
1\;8(8 .....
\
~ /
== 1 , 1\18(8 + i
'.
)
i)
(c
)
if
Of.; aI' ~1.I.~i..d
bit
C::.o +
i)
-
O~
(d
)
if
01~3::"2.).1.d
;):Lt
<40 +
i)
::::
1 • 1\18(i)
MS(i )
(cl) ftb~)v.3 app ly ~
set ~s8
u
l
D...nc~
bit
+ i )
= ~sg = hlS12 = 0,
hlS13
= MS14
~LS
\:~·l~1-~Cl""0d
is
Z:'0'C
.~.:)
::':1:: 0 :.' f::::, ,~~
·J
'-1
I
MS
~6
NB
CO
j.o
32
7----:.--~--
CO is
'Ch& 16-b:i.t word :iddross of the order currently being obeyed; the most
co
sig,'71ifican-c bit of
is .always zero ~
'. J
->
2 'l S cOluplemo:lt intcg0:t..
~~"i'1d &l"e added
1-,
to COl)
till 2:c':;empt to
l )
•
J
Symbolicdly :-
Sy:m~Jolical1;7:
[MS
-
NS. CO] - [SF]
(~Tote
t11t};t: if tl18 Oper8.Ild specifios
Symbolic 2,11y :[CPER/um] == [IliS 0 lXB, CO]
I"
1
11
{ !
------- - -
J
l
----
-----
-
----
"rill be:-
LJ
SF
The call '\7:£::'1 lock like:. J
ST ACK LINK L1
S'I' ACX ;-",2
. J
L1:
I
'~--'
th.0 s
·~a.c!<
loo~(s
lil~e:-a
'_.J
SF
The procGdu:l:"e i tS01f 'will con "cain orders:-
PRCCEDUR3 P
3
SF +
'1'118 orcie:r-
~ffi
to sa";; NB for use
for -ehe n local
11
== SF - 3 sets NE -->
LII~r{ 211.
9.. S
:rl.l:"'.1i:0S
a
b~:.S0
or the
ths staclc p :;:l1.d SF ..:-
..1
.J
I LE~3:1 Ail
A21
;-\3 I
',''
1\
'/
SF
i:n, the prccedure
Pl"OC0Clure
:11. ~dv8..J.i.ces
SF 0
"
6.4
Conditional Control Transfers
. The tes t bits TO, T1, T2 are hi ts 4- g 5 a.'1d 6 of the machine
status register MS (see Section 6.2).
They are set by the computational
orders Cu,MP a;.i.d CINC (see Chapters 3 and 4) and by some of the s tore to
store orders.
The signifioance of these bits is generally as follows:-
TO
set to 1 if overflow
T1
set to 0 if result
T2
set to 0 if result> 0, 1 if result < 0
= 0,
1 if result f 0
A set of seven orders is provided which causes a relative jump if
MS is suitably set.
If the test succeeds then the jump is carried. out in
exactly the same way as for ->.
r
IF
= 0,
->
jump if Tl
IF
...t.
r- 0,
->
jump i f Tl == 1
IF > Og ->
-
0
jump i f T1 == 0 or T2 == 0
jump i f '1'2 = 1
IF < 0, ->
=0
="
IF -< 0, ->
jump i f Tl
I}'
> 0, ->
jump if Tl
IF
OVERFLOW, ->
jump if TO == 1
'1'11.01'0 is an
1
.1.
or T2 = 1
and T2 = 0
r -\
eighth conditional jump order which may be used to
test the Boolea.i." BN, desoribed in the n0:;t s0ction
Q
II
IF
-"~...,-----
.....-.-
BN~
->
jump if EN = 1
\
.\
r
,
---------
',!
7
The BooleaJ.1., BN, is bit
L
J
Thel~e
are two kinds of orders which set EN.
with the result of a test p
J
i
mac~,i~Le
of the
~d
status register 1{S.
The first kind combines BN
uses tho operand to define '\'lhat logical
operation to perform; ·the second kind comhin0s EN" directly with the
opera;.J.d.
The iir3t kind of o:;.~dGr tosts MS in one of
I.
8
'Ways to produce
a result R equal to 0 or 10
=0
R ::.: 1
p
R
if Tl :::
. 0 othsl"l'fise
O~
~l
--
0
> 0
=1
R ::: 1
o
if T1 ::: 1,
if 'I'1 ::: 0
or T2 ::: 0, 0 othe:rvlise
o
< 0
- ,,
Bits
" .J
'i
1•. .1
=
otherwise
1, a other,vise
< 0
R ::.: 1
if Cl'l ::: 0
> 0
R ::: 1
if T:i.·::: 1 a.i''l.d T2 ::: 0, 0 othorwise
OVFLOW
R::.: 1
i f '1'0 ::: O.
o
EN
R ::: 1
if BN ::.: 1,
o otherl"fis0
or T2·
otherwise
59 - 63 of the operand define the way in which th:i.s result R is
mr
as follows:-
BN ::: 0
set
to be combined with
- 1
otherwise
0000
0001
i3:.:r ::.:
0
and BN vii th R
0010
EN/go
invert EN, then and wi th R
C011
EN :::
load BN wi th R
0100
BN &/
at"ld with inVG1'Se of R
0101
t
not equivalence with R
0110
BN
0111
EN V
01'
1000
BN/&/
inveTt EN, then a.:.d with inverse of R
1001
EN ==
equivalence 'with R
lel0
Bli/
invert EN"
1011
BN/V (implies)
invert Br-T, then
1100
EN
1101
EN V/
or with inverse 01 R
1110
BN/V/
invert TIN,
1111
EN = 1
set EN ::: 1
,vi th R
:.J
-I
L.J
'.
j
,.J
=/
01'
with R
load EN with inverse of R
The second kind of order use
4 of
th0l1.
or \vith in,lsrse of R
the f1 bits to specify the function
as above? ai1.d takes the oper8.1J.d R from the least significant bit of the highv!2.Y.
u
I'
Special Dreier:s
xco-6
Stack the oporz,l1d p m'l.a jump to zc:.::,L:::mt
locations 0 -
g193, 32-bi t y!o:rd
6 X'ospectively.
DL=
The Display
SPM
This function
is
L~~ps
may also
for US0 'vli til the System l'orfOr:ffi2.l1c0 Moni tOl"'
.,
rl
7. 1 • 1
Chanter
Z
The Interrupt System
.. J
There f!re eight -eyp'.::>s of interrupt divided into tyro grou.ps of four,
"'t:he System interT*upts and Process l')8,.sed 'inte:i.I'trllp"t:s
0
"rhe syste!!1 in.terrtlpts
are concerned with activities external to -ehe current process (e.gog
control).
The process based inte:.'rup-cs
th~00
as n. result of specific 'actions
The interrupts are sno'ilTI bolow ~ each associated with
in the cu:crent pxocess.
2
OCCU1~
p8:..~iphe?:8.1
bit interrupt number.
\.J
( 000
Sys "caIn ErrOl"
i ~O'
CPR Not-Equivalence
I
'1
U
J...
010
lOl1
periphoral Wind a"'!
("100
Instruction count Zero
PH.GCESS BA.SED
r\ '101-
Illegal OrdEll'S
DJTERRUPTS
'-1110
P?~ogram
11
'I "
\..-'--'<'
I
Faul t8
Software Interrupt
:.J
interrupts occur sirt1ulta:neotlsly? tha first to be clG2.1t with
When an in.te:crupt occurs ~ the h8.1'(1\'7&,1'8 stops Y:hat it is eloin;:; a.."1ci enters
an intsl.'l'upt seqUG:les o
SG't
During this entry sequ0nce the 'Interrupt Entry Bit' is
This atlovlS tl10 soq:'lence to run in a sp0ci~i,.1 non-interruptible
(.l
ln009
of
operation c1esc:dhGd by t:'1G tao1e in 702.
'The fi:::st [..ction of this sGquenc0_ is to
Y:Ol~(:<)
1._)
T118 fc~~"r;1at of this linl\: is the
SaTI16
l~'0tain
th0 state of the machin.e
(?wS the control registel'" consisting
of i,lachine State J.'G[;iste:c (16 bits)? Na..1l8 Base 1'0[;i81:0:;:' (16 bits) and the 32-
bi t
cO:"1 t1'ol
a(l<~l'ess.
In addition ·co reta,inirlg a lil1k, t116
ill';~err'L1pt
sGC!1.1once also
trUJ,lsf81"'S
I
co:ntrol to tl1B aPiJrop:ciate interrupt pl'ocedure ~
acl1ievecl by resetting the
,701'(1
u
bits (r.IS, i\lBp CO) fl~om the second half of the
of this entry is used to hold the link
lor~g 2.11d starts
L~
64
2,1:
vio:::-d
7'!'lis control transfer :.8
0
16 of the first of the
This table is
16 x 64 bits
COm111011 segme:i1.ts (S0:-cme~1t SIC) ~
Y!hen a Cl)l1
t
int0r~:--upt
occurs t}-;,e linl:: 'vlil1 :point to tIl0
\
I
be cornplets G
Ot1'16::' interrupt s11tries all in.structiol1s up to t118 0110 addressed by
tho link vdll be cO!l(plete.
r
Unservicec1 intorl'llpts r.1ay be read in Prop V line 26.
Before discussing the intorrupts in detail it is nocessary to
~escrihe
the
~achine
State Rogister.
,
\
i
)
r \
I "
r
)
{
, I
'I
,
}
r
I
t
J
,",
bits
4
to
7
are test :'."'0gisters o
Til-is bit
is set by interrupt entry or by t1:.e fllit.ctiol".I.S
o
Q
XC 6
6.6)0
BIT
Force LRL ] insteaD of S[ J
o
.-.-1
1
z
Sy3 tem Perfo:;;yna.:.1.ce
i~Ioni tor
3
OV8rflo~
4
5
6
7
0
ve
7
_I
8
9
J
10
11
iL1.
12
J
l
J
For desc:ciptiorJ. of hi-;;;:; (0
~
7)
see
o
7.2.2
"
" I
Effects of System Mode Bits
J
I,
'-I
I CFr\. by-
Cause
!pass
!
1N8.l11e store I Ins tr 0 1 B or D I ACC • undel'IExElC lI~oc1el L1IFl LOIFI Interrupt
I flip-flop I
I
I (2Intry bit
I by-pass
I counter I under I Exec
I
I off
1Exec
,control
1
1
I
I
o
I
Q
10
I
p'Y-Pi:1SS CPR 1 s1
.j
----~----~--------~-----bY-P0_58 Name I·
stcro .
I
Effect
~··:::3truction
I
lcontroll
()
11
I
12._ _-;-_ _1....:''''''2_--;-_1-'4-;1_1_,~'-;-;-_ _ _ __
1
1
Counter off I
Allow V-access
V
: _J
('I
J
.;
J
V
j
\/
Allow system
TI10de bits of
(-"(
I )
£,IS to be
Inhibit Ll
Inhihit LO
J
'/
j
.,
Inhibit SysteTit
Z"orce
j
'/
1
Erj.'"'or
r-;
./
. I
l'e 1 ElV2..n
pro~rs.rJ1
t
V
-I
faulti
to be systern
I
I .j
!
I
errOl'"
Use LD nl?J',le
store o:iJ.ly
'1~(6"f
.:..t:
...:c. b~~. 1-v
1'; 1"' 0'"
_
B
...
-I
o;:Jo
,j
I
I
,
)
D intel'l'Upts will be forced as system errm.'s if D11 is set and a.1'l ACe
01'
interrupt vlill be forced as a system error if D12 is set.
All oth0l' program faults
l I
7,'ill be fOl'ced as system errOl'S if D13, D142 Di5 or the Interrupt bit is set.
(N .B.
The Na.'lle store is by-passed when the interrupt entry bit is set since
r,
a~cess
r \
to common segm8nts cannot be made via the naIne store).
If:)
Ii 1".)1'.8 Store
:1
15 set) the 8 32-bi t lines of naT.l0 store are used as fast
The hardwaro interprets only the bottom 3 bits of a VnarilO typo' operand
In La mode (bit
rGgisters.
address and maps it into this name store.
.
b
' as 0
0
reg~ste:r's may
e usea.
x
:No store accesses occur.
?-....
3--01
.... nar.1es or
4-
'X
L
These fast
0"..-011: nal.\1es.
f'"A'"
r '
1
The System (L,.:lVeJ. 0) Interrupts
The procedures which service t},'J.es0 interrupts must be written
as to not ceuse &l'1Y othol' Level 0 8y.;:;te!l1 inter:fupts ~ foZ'
00
ex~.lnp10 p tn.::>
Peripheral 'Window Interl'upt procedure should not cause a CPR Not Equivalence
Intel'rupt o
L)
This requil'es that a. fow CPR's are permaJl.ently allocated to
covel' the program and world.l'lg store used by these Ir.;.vel 0 Intel'l....<.lpt prOCOd1.11'eS"
If a CPR
t
interrupt occurs while the Level Zero Interrupt flip-flop is
then a System Error interrupt is caused o
set~
This also occurs if an illegal
hardware function is executed while the Level Zero Intel'Tupt flip-flop
In this scmS0 the SysteLl Error Interl-upt difZel"S from the other
is 'set 0
System Interrupts o
does occur it cannot recur until
However, once
the System EZ'X'ol" Status regis tel" (see below) is reset, or unless th.e
Engineel"s 'Interrupt' is pressed o
",
The System E:;"Z'Ol' Interrupt is caused by :1S,.rd-rlare or Executive
failur080
The System Error
exact cause 0
St~tus
register
shc~~ bel~l
can pinpoint tho
The soft,lare aetiO!1 on this intorrupt is to perform erTOl' diagnosis)
a.>."'ld res~.::art nO!"ll1a,l
system operations if possible"
error indication
L.J
Engineers Interrupt (Console)
(fel'ces CPR
bYPV,8S)
l ..J
'~I
49
50
SAC Po.r:1·cy
51
52
NQlne Store T,rul tiple cqui valEmco
53
54
55
CPR Multiple equivalence
aES Multiple Equivalenc0
Spare
IEV i\iul tip10 Etiui v&.lonc0
B or D error & OiSll)
...J
57
& (1)1S12)
!11ogcl function & (LoIF + L1IF
Ace error
59
60
61
CPR exoc Illegal
CPR
t
Spa.re
& (LoIF)
~
3XEC)
,
!
CPR Not-Equivalence Interrupt
This interrupt can be
Mode procedure.
procluc~d
by a user program or by
alL
executive
, .'
It oocurs when an attempt is made to acoess an,address
which does not lie within the addl'ess ;fiolc1 defined by the contents
:.
of the CPR'so
)
If the required address lies in local store, the procedure
il
will free a CPR and allocate it to the page containing the address o
Control is then returned to the interrupted process.
If the page containing the required address is not in local
organise its transfer
, J
In this case control is not returned to the interrupted
r-l
store, then the procedure will locate the page
to local store.
~"d
process (which is hal ted awaiting the termination of the tra>."1sfer) and
, J
a process change may occur.
Exchange Interrupt
This interrupt is set by the Block Transfer Unit on completion
r -:
t
(or termination) of a Core to Core Transfer.
)
Peripheral Window Interrupt
This Interrupt is caused by an external device (eog., peripheral
processor, drum) writing to the Peripheral Window V-line or by an il'l.to:;:'rupt
from the console (e.g., TTY, CLOCK)o
61 and 60 in V-line
%011A,
The two are distinguished 'by bits
the first l1ndicating peripheral window
0
r -,
The
information sent to this 32-bit V-line consists of the sending unit
number and a message.
The Peripheral Window procedure must queue up
this message for subsequent processing o
.. 1
,
)
r
1
"
J
'Writing to the peripheral Window V-line sets it not busy in
'readiness for another message.
The Peripheral Window procedure runs with
interrupts inhibited, so a subsequent message won't be acknowledged until
the procedure is e:d ted
0
This interrupt is also entered for console interrupts (Teletype
and Clock).
Prop V-line 26 contains the cause of interrupt.
,- 1
L J
t
!
7.4
Process Based
I~~errupt~
The Instruction Counter
~e~
Interrupt
This interrupt is set when the instruction counter becomes zero,.
It may be inhibited by tho 'instruction counter inhibit' bit being sot
in the Ma.ohine Sta.te Register.
~ .p~egal ~
In!errupt
This interrupt is caused by program fault conditions detected by
the hardware; these conditions set bits
status V-line.
48 - 53 in the program fault
(See next section).
The Program Fault Interrupt
--,
LJ
This interrupt is caused also by program fault conditions detected
58 in the program fault status V-linGo
by the hardware which sets bits 56 -
The following table relates the assignments of bits in the Program
Fault Interrupt status V-line to specific fault conditions:V-line bit
condition
.:18
.
Illegal function & (LOIF + LlIF + EM)
49
Name Adder overflow & (LOIF + LlIF + EM)
50
51
Control Adder overflow & (LOIF + LlIF + EM)
52
CPR EXEC illegal (illegal access via the CPR's
Illegal V store access
\
when not in the exec mode)
LJ
u
'~I
u
53
Parity
54
Sys tern Pelof ormance Monitor
55
Spare
56
B fault & MS1
57
D fault & MSl
58
Acc fault
&
MS1
IJ
When a program fault occurs, the hardware may not wait until the
arithmetic and control units have finished their current operation(s)g
so that multiple fault conditions may not be completely recorded in the
Program Fault Status register.
The
~tware
Interrup~
This interrupt occurs in user mode only When the software interrupt
bit is set.
u
(See
8.3.3).
10.9.73/2
.
\
)
r
~\
C11p.p~~-:o:r;)
Tne v-StorG
Irr troduc t:LO:.1
ThB V-storo contains hardware registers used to control
2,:n.d/m.' diaG;J.1.ose parts of tho
rllUS
processor 0
not include tho IntoJ."nal Registers ~ which aro ",ddrossod by u
diffsl"ent Tl1Gchrulism o
a
J
I
'-1
use:..~
Tho v-store is not genexally
prOgra..'11 but is accessible fl.'om within
diaS;llostic progra;aS
lIm5
f~ccessible
to
to
Exocutive~
0
The figuro in 1"Z.3 shows the instruction format required to
obtain e. V-store Op0!'w"1.d G
The V-storo is dividod into
1z8
blocks of :256 linos oacho
:i.'.:c:ch line is n.ormally a 64 bit quantity but many of the 1:i.n03 will
contain less then
64. bits, in which cs-sethe bits 'will app0ar right
justified in a 6L~. bit 'Wo:·d.
they ""lould appeax' O~'1 a
64-oi';; wide highway.,
gives tho :.::.110ca-<::1.on of block numbers to sections of
V-StO::"0
J
i
o
1
Ll
"
3
CCG>Isom V-STOIB
S!:..C V --S'T05!S
5
6
L_
--,
L.J
",,
in the
System V-storo (S81q2)
~
k
256 V-line addresses are mapped into the first 512 x 32
bit wozods in segment 8192, the fil"st of the comnl0n segments. by the
These
PROP before using them to access store.
This gives the executive a
simple moans of communicating between processes and approximates the
Atlas working stOJ."e.
Starting at the 32nd 32-bit word of segment 8192 are
8 pairs
of new amI old links used by the interrupt entry sequence"
V-line
(Decimal)
64- bit
boundaries
16
20
22
26
Virtual Address (88192)
Name
size
\
J
l
}
~
I
. Hex specifying
32-bit boundaries
20
System Error Old Link
22
System Error.Entry Link
2426
28
CPR
~Achange
2A
Exchange Entry Link
2C
Periphera.l Window Old Link
2E
peripheral VlindO\'1 En try LinIe
30
Instruction Count Old Link
32
Instruction Count
34
Illega.l Order Old Link
t
CPR t
Old Link
En try Link
..
r'-·
Old Link
Illegal Order
28
I
,~-
Ent~J
~~try
r '
-
~,
Link
Link
Program Fault Old Link
Program Fault Entry Link
!
I
30
Software Old Link
Software Entry Link
L i
,1
L
)
--~~------------~
Addrass (Dacimcl)
~;8J110
81.20
j~ccess
specifying
.
6L -bi t ooundaries
o
(hi ts
4.8 -> 53)
and the System Po:-dormanco l\!on i t 01'
~,
.'
-1
~
.1.
1'5
2
t..
~
_1
,
-~
-.!
R/Vl
°l
L )
I)
o
'._.!
i-i
\ oj
12
Vi
9
SEARCH MASK
12
''-1
.J
The mask operates on the search (block) address,
specifies that bit to be ignored
Q
.R,
16FL7
NS LIl'f."8 COpy
('Yo.) 10/ %11 )
These lines contain a bit significant indicator sho'wing
'
.'
C
!
.
whic.h namo store entry received the last valid name store
aCCGSG
G
V stm:e 'without disturbing NS LINE COPY.
Resetting sets tIle p0inte:c to
t~10
l
,
l
I
:
)
line 17 causes all entries in the na,ne store to be
10.,:;.,,73/1
IJ
25
l'0Iel'enCes
I.J
-,
,.J
U:r.:.s0:;:-viced sof>t';:'!2. . :L'G i~~l to::"1'11P .;;
Uns0l."'vic r.s.d.
'_I
-_.
,1
I
I
__._---
p::C)g:r'~':J:r!
fE.;21 t
TJ"nserviC0ct psZ'ipj Jt;j,.... ?l
Unservicc(: e:::cl-:.t:;:lgc
Unsor"v"iC0cl CP£~
UllS0J..~viced
t
i:::1·:·~;}::·1~U.::lt
~ai:,i(~O\:l
vi::::::.dG,(.~.;r
i~'i ~~el.. ::..... :.!p·;:
~~T;, t~.~.l~~t:.:?':t:
:11'1 to::'::"'~i~)'~~
syst0zn ·S-r70:"'"' i~~v:~·:'~:''''~'iJ.~)t
27
\
I
\
I
1
,~
\
l
I
II
l
I
11
r-
~I
()
()
Tl:o OT3S v-Stol'e (Blocl{ 2)
TI1G followi.nG sho:.'t ctescription
system will
1
cl~'ify
points in ons V-sto:ce control.
The OBS contRins
3..s."'1.
0
,_"
operand store similar t'J tli0 PIZGP 1'12,2TlC store
bu'\: 'vlhic11 is not :-c'ost:ric-cerl to doaling "I..vit11
0111y
:.n.Zj::e 80g,'illO:n..'t; opGl---a;1.ds
All operu.."1ds which ,:;,,1'0 not nmaes and all opo:r&<'1c\s in accumulator
o1'(103:'s (names included) are buffered in the OBS opel't..nd
stol~e.
(This means
part
~:
-
-,
'__ J
'--1
LJ
--I
Ro4Q2
Name
Ac1rlress
S:t~~e
l
Access
(Decimal)
I~
aBS.ClEAR
OBSoPURGE
0
'Writing a
to bit
VOl
Vi
1
63
Causes th0 nBS to 'be CL'8AHED e
a.ll tal te:;:oed Y operands in the aBS oper8J1.d sto:ce
to :ma.in store
a1'0
This means
written back
'i'hey are also retained in the> operand store and
Q
vunalteL"ed~",
reset to
Wri ting a
vl'
to bit
63 causes th(;] GBS to be PURGED"
all 'a1 tared v opel'ands
8.1'0
This
lnaa;.1.S
writta]!'J. back 8,3 in the CLEAR but in
addi tion a.ll lines in the ope!'e.nd s tO~.'0 :;.o);e set El!r.pty. i ge .. t
the aBS ope!'$'ld store is left :111 a ?:ES3T ::-;t2.t0 o
~
1
(Unassigned)
:2
DES "MASK
l"
I
w
r)
".,
1~
-----.~,----
.--------....
,52
63
~-
'l~his is used
A
!
to
mask the X field of
1 7 in tl:.e lllask
to be
~.grlOred
caUSOS
the
\:;3,:'8
CBS .FIND line (see below) ..
COJi.'1"0SPO::,.<:H11g
bit in the Find operation
0
3
30
L '
~I
I
\
l - ,'
I'
is set non-zej.. . o
othe~vis0
t110
test :.. . G:;i8t::;l~ is set: equal to zero
0-
-----------
LJ
(JBS o DultIP
L!-
vr
29
u
1
U
vrri tins to this line C2,uses tho £1.111c-::;io"5 on the Ace queue and
J
their opel"8.J.i.ds to be ~~..rritten to the sPGc:tf1.ed
All useful information in the oper.and
8tOl'O
t116 lines are rLo""C all RT~SErr) but the ,Ace'
16
i.s
Crt1.,f.t:..1G
x
64 bit block o
l'et8-i:t8cl
(i.e.,
is l~etu1"ned to
the 'eBpty' state.
Each dumpod entry consists of 2 x
-l
-\Vords.
.?:..o______?~~ ___ .1._____....1.::1_·______-:..;1_2:I TIE I p i S
X
I
._---------._------------_
..----..;.....------",-o
63
~'<,.,,---,___ ~ _ _ _ _
Word 0
1..J
'rhis contains
u
64 bit
FUNC 1
DOP
A.cc func·~iol1 (?Dl'JC)
t116
al)'<"l
the time of access is i:1 E (e:,:-cec1.l·i:i V0) "
SOlTtO
harc1v/are information
Tile T bi ts specify the
type of opora,11.d:L_J
o
u
Inva:!..icl· (Empty entry)
1
u
If the opoI'a:n.(l is a Ii ·ter2:..1 t119
and tl10 litera,l is 11Gld i11
~tlle
virt~-1al
2,i:L"lro3s field is irreleva11t"
secol1.cl V10=CC; of tho
on~~1"'y"
u
- 1
V[O l' tl 1
L~
I
I.zITE~1A.L
-o----"-------·~-·---63
!
-1
Note th9.. t when the
il'1'eleva,nt.
LJ
-,
u
-
u
1
oper[~d
is not
8.
li teral type 9 \'IO:i.'d 1 is
,-1
Vf
nBS. mrDlJ1'.;p
5
<, •
1
.L J.
s
p
1'\1
-------'~r;"
3-4
\..-..)
,-
above aci.clress 8pacifies
bit blod: from rl 11.00
::::
::::
not empty
not full
I
I
J
I
I
, I
I
!
!
1
I
i
J
~1
i
I
iunctioTIo"
DBS o liTIS3''i'
'~rri ting
to tl1.is V-line
C~UfJOS
a resot of
tn~
C3S Buffel Store
ll
I
'!
I
I
I
, I
6 8,,73/2
0
I
'/
-!
--------
Q
control Console V-Store (Block
~)
--~--.---------""--
,
rrhe console V-linos 8,::'e as follows:-
!~c1dr0SS
Access
(Decimal)
Specifying
c
•• '. ,oouncar~es
l'
04-03.1,
o
CONSOLE INTEmmPT
Each. of t118se is '1
R/I'!:
IJ
''.vl1en set
tj
is tho fast clock intex':cupt u
(Currently 1/100 sec).
is the teletype character interrupt.
(Currently 1 sec).
(S0e line
Y/ri ti:ng to tl'!.is
to be l'esel"l::
li!:~e
J).
ca.nnot
caU.SG
tIl.e
'1":
oE 0 I" I
0
bi t
This can only be achieved by resetting
0
.
li!l€)
Yij.~i tine; a "1
2
T!11E
--------
70
TJPPl~I~
c;r
to bit 62 resets bi t 62,"
13
V!ri ting a
,f
1
t
to
I
~
I
3
15
TUlB Wi'iER
R
~
I
I ~\\l\~\~~~\~\~SW' W\l~L
,-I
4
j"
T
U
£'
---4 ---,.-
I
u !
T !
FRAcrnON
OF SECS
s~cs
32
63
"
Seconds and fractions of seconds '/ in b.cod o as
~
shown 0
4
This line is staticisod by reading TIMEQUPPER o
DJ.l{fE IGiER
11
R
LJ
J.
it
.'----'
10:i,~W0l~®\\\WI
32
U!
4'
-:----'-
UI
'1'
MONTH
DAY
~
Months and days appeal' in bi:i'1ary coded decimal in
8
5
R
4-
:-\~i\\In\' \\'\\\\\"'''\''
I
I --..:.-1'"
--\ \ I' \ \ '.;...'\\\\'\\\'\\\"\'\\,\\\
\
, \ \"
\1'\\ltI"\\1
.}j
32
u :1
YEAR
63-
!
L..J
f\.ltl:.cugl1 this li:c.e l!.2"s :r9ad o:nly access,
bit
6
to
63 at -erda add:;"08S 'will operata the hooter.
rrELETYPE DP:rA.
8
R/W
8
I ~\\\\\\W\ \;~.\\\\~~,\I\W\\.f'W§\\'!
32
To output a
DAT A
56
charnct0l~,
.
1.8
LJ
TELETY?E CONTaOL
63
TELETYPE CmITROL must be in
output mode? thEm Ylri ting -;';0 this line
7
'wl~i ting
8
.
,ene
st2l~ts
the
character parity.
R/i'f
8
L..J
LJ
Each hi';:; has indiv::dual significance 8.l1d is '1 9 when
-I
set active.
LJ
Dig~}:.!
=
56
57
PRn~r
58
59
Input/Output Toletype (Vi: for input)
60
VAccept V
61
'Cancel Mesoage V
62
Teletype start
ON/OFF (OF},
t
n
1' )
L
~
I
Input H.equ0st 9
L 1
Teletype online
When tho TTY is onlino, bits
59,
60~ 61 will cause ;;.n interrupt.
ON LHT.E (Pe:dphe:raJ.)
~
j
•
j
OFF LUT.E (Ins true tion Source)
! lI;U S'l' ·l:SI~ I
I:
I :
10
1'10Di~
SVTI'TCl-IES
R
Tho 1eaGt s~.2:nific:~lt
of t!1is lirlG
8 bits
and tiLl;) rr:.ost significant
Sp~~c~i..:fy" vZ'l.,ri0t18·
rrrHDsa
4 bits
lilodes of oPGration when set to
are used
fOA~ s'~!itc11il1g
\:>f th8 Loc9,,1 oF.L'fid
!~1a,ss
t~·
the stacks
stores off-line.
1.,9".<";:;1 0
:112hi.oit Clock Into!"rupt 1
No overlapping of instructions o
60
Bypass
61
62
Inhibit Clock Interrupt 0 0
N:.ll110
H.eset parity
Store
0
l J
Q
28.6,,74/2
n
11
16
R
10
R
,/ /5.S-6-::;
)
,
~,
i
LJ
Z...
~Auto?
::.:.11
LJ
55
:i·r--:.·~
-~ ...........
LJ
0-
r-
oo
b:..
~
u
"
'~1
L..J
,....,..'\·t '}
-:'-'.'.
$'
,;.;.nd 12
II
_ _ _ _ _ _(}3Ioc~;:
_ _ _ _ •_ _
.1_
S,AC V•_. -store
~t)
SAC unit.
11
. 4.rldress
.
n
(Decim:;!..1)
LJ
o
30
...... _
L
VI
lA
is
... ..l _ _ _ _ _ _ _ _ _ .'_~ _ _ _ _ _• _ _ _• _ _ _ _ _
1
P
1
i::~
}
t
).~
-.:.:-";-.-.---.-.-----.---------~-;~
jL:.
Tha
U30
of
L
V.j
~hio
line ia'doscribed later under line
"
5
•
I
L_J
1
(0
L
2
C?ii, V:\
J
R/".'i
....
__.:.2:.'A__J._..___ ~'"l:~~~_____ . ___~;____
___~;~L____,_3.____. . . .__·
,
I
;~
....,
R/Vl
3
S iZ'38
6Li..I~
, -
~f'he
AC
16 \vords
bi is are
(S11oYt.n. bslo'w)
0;
o
Q
p:C~(jgrD.Jil
o
o
1
1.
bit
35 -
0
u
Dnta
n
8.6.2
32
CPR registers o
Each of the30 i:J G0::.1'::;ep'cu2.11y divided into Virtual
Address part a,'ld RGnl Address
p~,t
0::: '2;110 :i:or;r.at illustr.r:.ted in CPR VA
!?!'ld CPP. RA.
operation to the VA half oJ! )=:'A heJ.f of the CPR
:registe:;.~
specified
by the con ten ts of CPR }nJMBER.
must be written to irrunediately
4
b8~:0l"(;;
t~'lC
V:i,z"cuul AddreSS part.
'Ynis
CPR IGNOI{E
T11is vector
5
CPR FIND
..
-
"I;l::"~''t.:U~
ho.If of
...J
.--)
U
i
~
6
CPR
.llj.rlS~1J
32
r~/\V
7
CP!\.
REFE~U.~l~CD
32
R/V!
"
'. .J ,
_J
i
...J
Ll
00 o
<)
16
CPR FIND MASK
1
hO ~.)
....
14
11
,-J
1
I Pf---,-s----C\W\\W\\';\\m\~!
37
63
The use of this line is
The Find
mech~ism
d05C~:ib0d
opec:>ate,s
ovel~
unde:;:"
lillS
.5
CPR FIrTD
,'I
0
each hit of the segment
field whereas tl18 P r.i.nd. X fields both merely have a
'--'
,
,
Ii
,,---}
CPR X FIELD
11
<%
B)
l
p~:rpoGes
~1d
is fully
R,A'l:::Reset
17
R
CPlt lq(IT EQUIVAIEliCE i.3
(fa 11)
Line
17
holds the sEliE,."ment
L J
J
U
The ac tion of
'\J:'.,':i. ti;;lg
their norlja,l state
~-l
LJ
during the CPR
t
as system e1'1'01'3
,..J
has been
.4J::.y CPR.z:
il1"i::er;,.~upts
which occur
in-carl'upt p:1."OCedUl'0 \'Jill be nonitored
0
If thesa ceCti::'" before th", PSX lino
reset, thoI'G will bo no information in PSX
about the address
---,
0
to ';;h:::: PSX line rctUl"nS both to
c~uGing
the system error CPR
tG
~
20
SAC PA..l.\ITY
8
R/W=Reset Bit
57
---]
<0/1>14)
:~
._.•_1___1___,__
-I
1!
~
-=03 !
i
I
EJ(EC rJODE
P:{OP (NG:i.' 013S) OPERAtm
IKS'I'RDCTlmr (Ncri' OP~Rj.ll\TD)
B::T 1 '~,
B T.T 0
j"
L..'1CAL STOR'S STACK NO u
3}:CI{,'::.i~Cs;3
DA.T/l (iJC".c IDC.B. .L STOP.:s)
LI1-rg V..4..T.JID: .:1. D.P-/F:,l.t Pi\.RI1rY 11. 4..S
.
OCCUR}1En
'IE-lEKS I-ij~G Ef8:2I~' A. p!Ll!r~.,y F ll~L IlT E~{EC 1l10DE
P[JS S I BI·Y S I~GB J3Ir-i' 5~1 BECl:.1iE SEi'E D
u
,
l:iB.I'I'HTG TO BLCCK
LJ
7
LTNE i
~i
U
U
21
SAC I'.'iODE
<%15)
L.J
:;:I',TJ:r}J:A~f:: ~-'lt.l.~I:r·~"
Il'rrERRUPT FOR OPERft.1IDS
FOR OPER.Lll'iDS &,
::1\r.H1i~r'T l:)i0.~r~r·'[ I}?"f~RRupr
Ii'JST~~uCT 1 O~t1S
II~tr{713~~'I' ~~:'~Cl::ltl'H~~E I.)/0~7..'l'1"-'l
PQ:2,CE :£ P .t:.i?.j.:rl~Y
FORCE p~.Jrfl!'iy (j>TG? :~'O?:lli'tL ?itR}:r:..~y)
II'J"'TErtl~UPT
.22
ACCESS VIOLlt?IGN
60
I
62
R;v{=Reset
61
Bits
&
63
, J
()q
-------_.-""
Ii!
I
!~CC1!:SS VIOL·A.TIG~
Il~Sl;itUC:'T':tC12'r ()'~iJT GPT~RP..N1))
S":lSTErr'1 ERn,OR Pl.CCESS
Bit
Il\[ OBS
CAUSED ACCESS VIOI.ATION'
~
'VIOj:"AT~m,r
I
[,
61
and refers to
progr~ti
faults only.
n
vrri ting
'- J
to this line.
,'l
23
R/W=Reset (see below)
I';
/
'l
PARITY FAIL 0:;,.
n~cc::,~Il\:G
FROi',~
I~}(G~1AJ,!CE
IIJ.':l\J--J
.
rmquES'l'S
EXCHANGE
PA:"(I'1'"tl Il,r'TB11HUF'}'
sr-r !1.CI{)
s"rjJ::~~~ :!:.I.?~.I L (Y1I(O~\SG
"
,~
W:t'iting to block
7
line 1. clo9.rs tho bottom
4
bits¢
R
UNIT ST A.'ruS
1
r- "
02;
2
~--l
w
25
I'lr'iting' to this line
to be sent to
tll(~l
19051~
CP':'US8S
S~
interrupt signal
¢
~_J
LJ
8&7 The !BU v-store (Block 5)
The instruction buffer unit ma.intains a record of the eight
LJ
most recent control transfers in.
-
wi th a
~,
f
jump to t address.
th(~
form of a 'jump from' address
This tabla is Imo'Wn as the JUMP TRACE
and software communicates "lith it by'means of the :lEU V-lines.
The
u
J~clP
TRACE is not maintained in any interrupt mode c
Since V
store access can only be obtained in these modes this ensures that
IBU V store is used sensibly when Jmjp TRACE ia static o
u
-Address
Name
Size
Access'
FILL-POINTER
4-
R/W
64-bit
boundaries
o
1
lvl-,\\ " \,
32
The line points to the entry in JUMP TRACE Which is
the next to be filled 0
When the hardware fills an
antry the FILL-POINTER is incremented by 1 (modulo 8).
Reading this line
~ives
the format
sh~m
above.
The
Valid bit (bit 32) indicates whetheT that entry has
been filled by tho hardware since the last process
u
change (see PROP V store 8 3)0
0
Vllien writing to this lihe the format is as follows:-
61
Bit
bit
off 0
59
60
causes the FILL-PO}ITER to be written to when
(Trace on) is zero, i 6 e o9 the Trace is switched
To switch tho Trace on the line must be w:d ttan to
again Vii th bit 60 set to a one 9
- l
u
63.,
I LiNE NOI
"
0:1.'
a. general reset gi van.
L
1
J
R
, J
'i
n
This line contains the
of the last
9
J"{JMP FRG},l' address (the address
16 hi t section of tho
the ent:!'y in J-m1P T?l.AC'i pointed
N oBc
The
~ JliMP
~t
JtJMP
instruction) in.
,',
by the FILL-POINTER.
'i'O' addrosses in JUMP 'l~RA.CE
as V store
,. !
Call1''lot
be read
G
It ca."Ulot be l'oad unless bit
60 in line 0 has been set
to zero"
.1
__ .I
~. J
n
t
j
'.
I
rl
,-,
,
,
:-1
L
J
c_J
P0::'iphoral Window V-Store (Loc;?l Block
6)
- l
'.J
ltddrGss
Namo'
Size
Access
o
r.!ESSAGB WINDON
32
R/W=Reset
- 1
'fhis 11egistol" belongs to lliU5 v-stOJ.'O but i;l addition
m~y hQ,V0
infol~mution
in th.o system o
T110
wri tten to it f:-com othe:c units
'\-r.ci-cing of tl1is il1IormatiorL
caUS0S
attempt to \'iri. te to the line from within MUS will mel'ely
:...J
cs-use tho line to be set not busyo
u
,
-~
u
~J
-,
j
_.1
14 8.72
0
u
n
Parity V-store (Block 7)
L:
Address
Name
Size
./J.·ccess
(Decimal)
64-bit
bOlli"1dary
L'
o
i
MUS RIPF
This provides a
me~"1S
R(\'l
of inhibiting further requests from
9 2 1)0
lIDS to exchange (see also
0
0
General reset resets this to zero o
L)
1
EXCHANGE REQUEST Pft.RITY
60
R/W=Reset (see below)
4
6;:s
1--,-....:-..,.-;:-,.-:...-:--· I
I .I
I
,_ DATA (V VlRITE
1_ j.\.DDRESS
-
Crnri':i\oL & UNIT NO
J'
requests from
excha~ga
c.
J
~_
J
1- EXCHANGE OVERDUE
Writing to this Irme resets all bits and resets the
4 bits
of block
4
line
,-----.
20~
L
This line is resat by:-
.:
Writing to this line
4
Writing to Block
line 230
,i
This line
i~
duplicated in block
4
line 20
0
" !
l
;
'-1
c
J
Vx-store consists of registers which control and/or
d~.Qgnoso
~o.d
- 1
zyst0m ha.rd~;;tare ::md which aloe com!ll.ul'l.ica.ted with from MUS
other units in the
rIms
bet,70en
syst~:nno
It defines the means of communication
and the other uni 1:8 of' -;::h0 system
Q
MUS may only access
ViC-store whon in executive mode or 8.n.y interrupt mode.
-,
Access is
achieved by a. real 2.ddress in a rea.l a.ddress mode descriptor or by
CPR bYP2.SEl 0
a. list of tha syst0m Vx-stores:-
E01mv is
MUS Vx
'-~
9v3
Disc (Drum) Vx
Block Transfer Unit Vx
~J
-,
905
19o5E Vx
96
Loca.l Store V-x.
907
008
Mass
0
'. J
Store Vx
System Pel'i'ormance Monitor Vx
LJ
A pl'obl$m 0xists when writing to the Vx-store and ".:hen cha.nging
NcB"
,-I
the status of the ruachine..
As fuz- e.s MUS is ccmcer:ll.ed p a. write order
is ccmplate whoD. it is accepted by the st01"e access cord::rol and it is
'--I
£01"
or(~or
uctually
:LS
a
lal"g~3
possible
number of iz:atl"uctions to be obeyed before the
executed~
A soft'\va:re interlock muat be applied in
C9.ses wna;,.~e this could cause t:;:-ouble, 19 "g 0 ~ 'W!'i ting to. :reset a BTu 5.nter:rupt
~_J
L"_nd t:':1ea relea~dng tha intel'rupt flip flops in Machine Status may Teeul t
i:1.
2.
second BTU il'1torrupt II which ....lill apparently va.."'1ish and may look like
p,,~::'i-:;y
"
intor:;:-up'cs p a::.'1.d local store fail soft 0
There are many ways of providing such an interlock
~~d
two such
are illustrated:,_ .J
=> Vx-Sto!'e
En ::
'.~
S(;Jlle
Vx-store
(destroys Bn)
b)
=> Vx-Sto:ra
B ¢ saine V;::-stOl.'e
B j2} 0
( imlOcuous )
.'\. und X ardEll'S etO not provide a satisfactory interlock o
.
~--.,
u
n
L
rrho normal iVIU5 Vx-store consists of the following:-
r.rh(~
P81'ipheral Window (Block
6,
Line 0)
This line falls into the Vx category because it is the
ll1ea:n,s by which other units in the system commun.icate 'With MUS 0
These have 'Write only at::cess and use this to put informatiml
into ';;11e 32 bit line 0
This causes an interrupt in MUS Which
al10',::8 the information to be read 0
'1'110 Parity V-Store (Block
7)
L J
63 of line 0 of MU5 V-store block 70 I t has
ro:?d/w:d te access from all units in the system including lroS.
Wh0n C-'1Y bit in the exchange Vx line UPF becomes set (see 9.4) ~
MUS RIPF is bit
exchange sends a sig;:nal to every unit in the system.
This ia
ig,"110red if the unit has the mar.rual
g
ignore parity 9 switch set 0
If not ~ and the !UPII' bit is set to
t
1 v then no further accesses
, !
are permitted iro,n r:IUS to e:;:cha..ge until appropriate action is
In normal circumst2.1"1ces this is a complete description
fIowover ~ i f the HEi\iOTE switch is set in MUS
of HU5 Vx.-a tore.
Console V store (Line 12 bit
54 see 8c5> then blOCl{S (2
->
5)
ci I\ms V S'l::ore becomes available as Vx-stOl.'e in addition to the
t,70 lines just described
in chaptel' !3 e
lO~
"1'110 MUS V-stm:'e is completely described
<.8
access as 0>$ f
S;?)ilEl
0 ;))
01'0 "
3
a".~d
5
55
r-1
become treated as
However, bleck
does hav0 scme changes on access.
11 a:r;,d 12 as V store have only READ access.
accesc
a.'1d
:
All V lines in blocks 2,
Vx lines vrith th0
Console V--store
Q
3 the
Lines
The per,missible
",8 Vx linos is REJU)/WRITE with the eJec0ption of bits 5J(
of line 12 'which
8
tay READ only 0
Access to the Peripheral Window and 1JUS RIPF is unal tared
(
)
rl
~l
~
__ J
L1
'i'he Disc Vx lines exist in ono block (Block 0) which COllsistn
:~
of :)2 liaas of 6~~ bits
0
- l
. J
16(1
\ -r -b';-
o
Name
Size
Accesr;
DISC ADDRESS
2:2
R/Vl
t word)
'_J
'" .J
p
is ths internal rea.d request
bi:~
and
if,~
set (ioe o , = '1') override~ bit 330
U
('1'hereiol'e normally a zero) ..
-1
'__J
R/Vl
specifies ·whether reading from or Tlriting
D
specifies th0 disc number 0 ->
-~1
L_J
30
Each
has 64 bands containing 37 blocks of 256
'l
words (32 bi t8 + 4. parity bits)
,-.J
specifies the
SIZE
for tr8.J."1.sier
numbel~
0
of blocks rElquested
Q
VIri ting to this line initiates a disc tral1sier;o
Note
"
1
'rna
block and size digits are updated dm.'ing-
29
S'i'DRE ADDRESS
The
28
transfer
R/N
tl.
24
I ~r\\~l U~M\.SS /LiJCAL P..EA.L
4
J
So
ADDRESS I
bits specify the real address in what is the
receiving or sending unito
Hardware ignores the
l~Go
eight hits of the address; it is a!3sumed to point to
L..J
at least
size)
L.J
-,
l~
0
8.
256 wm.'d block boundary (minimuw tra'i.sier
'l'his line is altered during a tr8..nDier
0
0
DISC STATUS
(see bolow) _
The description bolo",. is of the status bits
W:"011
sot :::
r
?., 1
.l.
•
Decorie the rost of the st.1.tt!S line.
,
Tilis is 0xalninecl by software on
c
"
L
I
L
)
completion of 0&.ch transfer. _ If set,
set~
come further action is requiroct.
re~,Gt
This digit is
by writing a '1 v
to it.
Dgeod 0
33
v,~
1 ine
7.
1',
This ind:i.(;&.tes an operators request to go
onto SELt" TEST.
Fur-chol' information about
7.
tho request is held in line
34 -. 41
same sig11iiicance as bits
+'7,
->
"-1.9.
Disc 1 absent.
Set
mG.!'1uall~1
L
to indicato the disc is off
'
ri
line i.e., cannot be read from or written to
l
J
by a CPU.
43
- 44
Spare
...At:::
r .....1
Disc 1 on SQlf Test.
,-/16
Disc 0 ahsent.·
47
- 40"
Spare
49
Disc 0 on Self Tost.
50
Illegal roquost to the disco
51
-- 52
WIlen input" p2.1'i t:;' error occurs th030 hits
define whether it pc cured in data, address or
con trol inf orm2,tion ~
Input parity error.
53
This callses a bit
l
i
l
J
to be set in th0 exchange Vx. l-ine UPF .-Resetting of both bits is achieved by
writing a '1' to this bit.
Bound locked out (see line
55
Data
18.1:;0
5).
(Hardwa:re el'l~or).
il
10.4073/1
rl
_
J
~r
u
~isc).
)0
Column. parity error (internal to
->-
How parity e1'ro1' (internal to disc)
';)1
~n
:J< )
Ignol'0 P'i"':o. ty fault - applies to
59
60
End
')'{
'oJ
tra.nsf0:'~.
i
0
J.' :::: ENDED.
Di::;c unit number (:::: 0).
-l
/~ccess
1
C. )
All bits of S'i'):J.'US
ca.n
,_J
be read.
C2.n
too
32, 50, 53, 53
Cnly bits
Eaci1 is 1'0Se',:; by wri ting a
to its bit positiono
.,
LJ
3
CTJHH.Ei?r
:2-4
P03I:-LI(Ji~S
R
·-l
.-
1---1
t..)
---·1--
6
6
6
j -WI\\' \.'1' \ 1
Dl
DO
'_"_;_'_'~i~~,____~~__~__1)2
~____~__
~~__
~
D3
32
6-=<
II
j 1
I
,}
DISC 0 PACKING DENSITY
DISC 1 PACKING DENSITY
rrhis line gives the curl'ent positions of e:;>.ch,
of tho discs, and also recol'cls which packing
density is current (VOi - HAIF P.D., t1 f
-
FULL
PoI)Q)o
L_J
R;t'l
28
1" \\\\\\'\1
''o,' \ '.
'">0
I(EAL ADDil.ESS
------------------------~-
i
63
,)"
This line holds thE? a4d~ess to be 'written to on
disc transfer corr.plet0.
is the STATUS line 2..
Tile ,'information written
Thi~" address must not oe a
disc address;;:
I!JCKGUrr 01
16 lockout switches for
This con".::ains
discs 0 al1d 1
bit locks out
~
oach of
rl'has0 are set mfulually.
4
bands o
Each
II
6
IDCKOUT
23
ji..fj
fOl' line
5
I
R
32
,-,,
appli(3d to discs 2 and 30
L
7
REqUEST SEL-:''' TES'r
59
->
60
5
Reservod for Request Self Test
on dices
61
62
,
2,
r-l
3 ..
a..11.d
inOtlU0st
solf test' on disc 10
~Request
self test' on disc 0
fl~equest
self
test~
0
is set manul?lly
0
'CPU permission to self test 1 ..
ACCG8S
All hi ts can be READ 0
Only hi t
63 can be vll'i tten
to"
8
7
R/Vl
1 1
I I I
57 - 59
60
61
!
:2
I
Margh1.s
L
A/D Required
,1
_~
Self Test
Disc number
•
j
L
j
I
'
.,
I
'
,_J
--,
26
,."
,.J
~-
'j
"I
.~
.,
1_
J
.
,
6
6
R
6 _
6
3
AID holds the AID conversion value •
Ct.:I':"Emt Bf'lm,
-(
59
..J
60
--,
LJ
--1
,-_J
-,
L.-J
--,
l.J
--,
L.J
~I
LJ
---,
L.J
-:
,~
.,
L_J
--,
L_!
--,
L.J
,
~,
,
L.J
Print fVD
Surface Error
--1
62
The
BIJJCK and TRACK is maintained"
l_J
LJ
111 1 1
l-jVDI-;W-@0,\\'IBAlmiB:LDCKjTRACKllll!1
32
63
Address Error
Self Phasing Error
The Block T:r8.Usfor Unit is desifs'Tl.ed to perform autonomous
bloc~..
transfer:::: between six possible stores in the system (2 mass
5"1:;Ol'03
and
4- local stores).
Up to
4
block
tl~t'.nsfero
may be specified
n
cO!1currcl"l.tly rnd these are cD.rried out on an equa.l priority, timeSh2XGcl b~s:ts
0
A blo0k
out one
tr~l.nsfeX" :f:r-~
i~'ord $;''; 8.
masS to local for instance is carried
timo th:;:ough tho 0)Ccnal1.ge..
. I
'rhe 'Word to be transferred
is buff',n'od ill tIl€! BTU boiore being sent on to the local store..
'rhus
t
j
I.
J
the t:l.'X1si'e!' mn,S8 -> local actually consists of "boIlO transfers:-
Ma.ss -> BTU followed by
3TH
A block
.v> Local
tl'B:.nsfe::..~
4
has
controlling V-lines associated with
4 sets of those V lines allowing; 4- COl1.curren t tra..""l.sfers
22.;:;:1 set is sitt"io;ted in c~e of the 4 block addresses 0 -:> 3 of this
it c
'1')::.61'0 iU'0
Po. blcek
of 64 bits"
of B'1'"(j V;;:-store consists of 32 lines
Wit!:.:!.!! blocks 0 -> 3 the VX lines havo the following
BIJJCI{S
o
3
~>
l
.1
,.
}
l
}
(Tra1"l.sier control V lines)
c! r
-----/,.."~
0
Access
SiZe
~:) fJ :-;
'--1
Sps'cify"i:ng
G~tI . . . bi"'~ bcu~-'lcQ.ri0s
'!
o
SOUF~CE
PJ)DI~
E/l'l
32
4
28
i ~\.0\~.m~\\~!----~----~-R~A~~Q~b~~:--~I----1
\. \1" I
oource '. "OJ: 1..0C \:
L )
to a botL"1.dary that is a multiple of the block
size obtained by l'ounding the txs"ilsfel' size up
to the nearest power of 2.
In addition the
10:?st si@;nificG4l.t o.dd;;:·ess bits are alw2.ys
4
intGZ'p~·\)ted
I'
\ __I
by the hardware as zero (16
'.11Ol'd
minimum boumlary) <>
A tranSf0l"' of all zeroes (null tr~"1.sfer) is achieved
wh0n bit
41
of the source RoA. is set to 1
unit no (bits 36
~~d t~e
.,
'1
DESTINATION ADDR
3Z
j
l.
1~~\'Tl)estinati0l1
32
J
R/W
z8
R.Ao of block
63
I
This address is interproted by hardware in
the same way as the source address
SIZE
"1
0
R/VI
20
",
At the start of a block tra.;."'1zfGr N spocifies tho
LJ
trg.,"').sier size as 2 less thun the number of 32 bit
words due for· transfer
0
(NIZ will al'7l:::tys be odd).
The ma::cimum tr:?.nsfer size is 64K and the minimum
theoretical size is :2 words
0
the block backwards to the fir'ot
l.J
Each time
0
V/ord is b.'aJ,lsferred N is decremented by :2.
:?
64-bi t
on
= -2.
completion of the trans for N will be
Ul is the number of the unit which is to be
interrupted on complotion of the transfero
3
L
TRANSFER STATUS
J
R/VI
4
28
1 1 1 1
I ! I
I ~\\' \0lli-w\\\Wi,"".\\\T"M\\\"T>'\\\,",",\\\\\\\W'i\.\W\\\\\\\\\\ 1 I
3Z
I 63
.I!
",
1 I
I
'I
I
1
,
,_
SPP.J~E
PDT
I ,_ TC
1- TIP
",
Bi t
60 is the 'rransfer in Progress bit
this bit initiates a block rrra:nsfer 0
0
Setting
It may be
=teset by software to terminate the t:caTlsfer midway
HS.l·dviare resets this bit on transfer complete
(successful or not).
28.6 74/1
0
0
r~
.
I
I 1
Bit 61 is the TrD.:nsfer Complete bit
rtardWal'0
0
sets this bit on completion (successful or not)
of the block transfer.
This is what cause:;; the
Block Transfer Cor::plote in te:L rupt in Ui
1
r-.
'1'he
0
I
interrupt may be turned off by resetting this bit.
Bit 62 is the Parity du;ing Tra.i1.sfe!' bit
0
I
When
set this bit indicates that the current tra:.'lsfer
has been terminated by hardware because of a parity
fault (sge BoT.U 0 Block 4 - Parity V lines) ~.-Bit
63
L _'
is a spare fault bito
L
o
PFO
R=Reset
1
.10'....L
;.J .....
oc. ::..)
r~
of this line is sot if parity is detected
on address or control bits sent to the B.T.U.
f:l'om 0:1:chal'1ge.
e;cchange and
'l'his signal is pass€)cl back to
S'ZltS'
EY-change V:g:-sto!'e
line 2).
a hit in the UPF line in the
(S00
BTU
Vx-sto:.~e
Block
l
•
l
I
l
j
5
Both of these bits are reset by
reading the PFI bit only.
R/yr
(
1
1
Bi t
63 of this 11:.'161 is a means of inhibi ting
fU"Hthel'
_ J
from the BoT ~ U to excha:n.ge 0
Z'e,~ue8 ts
When :a:l1y hit i:a the UPF Vx 1 ine (S00 block
5
line 2) becomes set as a result of some parity
fsult eXCh!:1ng0 s(mds
tl1G systerrt o
:l
_
J
signal to 0;;:.ch unit in
1V1:,J3Xl this sig'nal appears in trla
B., '1' • U O? p!'ovided pari ty in terl'upts are
r1
unhinhibited, the RIPF line if set will stop
fUJ:'th6:;'~
2
TH.ANSFER
to 0xcha.1'lge
1~6ques ts
CG:/iPLE'fE
4
,
J
\
J
0
R
56 - 59 conta.in the trunsfel' complete bits
for chBnnels 0 -> 3 respectivolyo
Bits
rl
NoBo Early morning reset sets these bits to zero o
1---
]
l
j
'_J
o
SUPF
13
?his line indicates scndine; lli"1.it parity faila
f'.cidr8SS
~1.d
control information. is ChElCK;3d forIf tho check fails a bit is set
:1.11 St]PF COl"'rGS pond ing to the uni"i: \Yh.ic h 8011. t
"C:1G
-,
,-1
12
---,
~._J
~~
1
,j
-[
__I
-1
TIe:..=..dirJ.g' this 1ir1e causes it to be 'clea.x·ud {}
.J
Lit
!f
cont:L'cl
[
0;'"
8.dd:!.'0SS
S&t~
indic::;/cos a
pari 1:y <>
-.J
"
13
UPI'
J
1
"
J
-l
.J
-,
J
~~on
units 0 -> 11 rospectivoly.
R
r --,
This VX-store consists of four lines in block 0 0
Accoss
(Dacimal)
O<.-bi t
boundaries
o
VXINT
VI
1
W:2.'i ting to this line interrupts the 1905E at the
n0~ct-occurril!.g
Normal-Mode instruction-fetch time
(The value of bit 63 is irrelevant)"
0
Writing to
this line also sets bit 220 in the 1905E~8 internal
V-line 129, (knovm as SR129) 0
1
VI
1
5ERIPF
W:d ti'ag a 0 to bit
flip~ilop 9
~et8 the 5ERIPF
63 of this line
(thus allovling requests through Exci12..>.'7.go
:tn tho SV9n t of a pari ty f ai 1)
W1"i ting a 1 to
0
bit 63 ~et~ 5ERIPF ~ (thUG inhibi ting 1"e~u0sts in tho
even 'C.
0
f
.1 )
a par:!.. ..... . y f al._.
·""R-P'r.'O
5J:;;:\.i
r
.. ",21
appears as •OJ.·C
.:.,
in the 1905E t s internal V-line 1290
2
RPS
w
1
to
V-lino resets
(Tho value of bit 63 during' wri ting is i1"1"01ev2.1:1 t) 0
Pi'O) \7h.ich indicates a parity f8.il detected by the
1905E on info1"m::l..tion received via
appears as bit
( Spare)
2 18
1
E~l:Change,
also
in the 1905E9s internal V-line 129.
w
(Writing to this line causes no action).
28.6 74/1
I
,
\
i
0
-
\
<....,/
iJ)
~J
'i.'fie following
a list of
:loS
l'01(,nrG:,;i-:.t
bits
~l
,!!108.11i11g
Adv1;1.\").ce W8.l'Tt.i:n.g of Power 17'ailu:t'e
~J
'-,
{s:truilar to bit 49 in s.lD.) System
Sl·::"C:r'
V-lin·3)
I\~U5 ~ c
Remote switch on/off
0
0
.. .J
lillo\~t/In:nibi t
.
-,
KiDS co:mrllul1icatio:1
IJtlit fail - (sirililal' to t110
OvIO;::,'dU0
signo,1 at bit
60,
EXCflC?.11g0
MUS V-line
i_I
23 in block 4)"
this is
25
Z0t
in bloele
by w:r:i ting; to 1m5 V-line
4.
L.J
.. J
-,
,' () '7-2
1 J"ooJ
L.J
~Cl1.e
~cr~1.
L.
---,,--
Store V:n:-·S tors
.......-----~------
'l'his Vx-store consists of
llt~d:r-eSf:3
-----
5
lines in Block 0
0
Size
Access
6L~:"~bi t
bO~.l.J.~da.:r-ies
a
()n incoD1in.g a.ddrE:sses or cOZ'ltrol bi ts fronl
r.rh.is l"'asul ts in a bit be::":n.g set
by vl:i.'iting to PFO o
8
F A,IIrSO]TT
R/Vl
I~~~\i\~\\l\~m\\s\\)\\\\~\§l\Wrt1..t. . .-;--4'-·1
32
!
63
I
I
I_- OFF
i
56
-,>
59
Ti1.eS6 bi:.ts CB:n. be Get to sp0ci::y'
a failsoft m::JGe.
(See bele/H)
Q
;
has no effect.
!
,-I
rrhGR0 r!1a~i
'co
C!.
bo
Get
:i1 n108.l1.i:rlsful
";:0
11l1il1be:rs
r,xldo of op~ration of tho Local Stol~0,
Q
Each ntllnbol' corrosponds
as below:-
i .. J
o
o
Norm~l
- nIl
4
stacks interleaved in
1011
I
I
L',,
l'~on-iTl·cerJ.0f'1.."io(1
<.Ie
,,-
of S0('!t1C'1'..tiaJ.
I:~~?Cll
s tacl< con tains
:.;v1dr03SGS:)
liOrl-i1l tG:._ll'.:~~:l..\t("lIi .::.pC 0::: Go,:uon t~~::~l
~CaCll
ill
o!,(1.0r
s t:;:.C!I,= corl t8. ins
il1. O!,r1ox·
8/\(:1""03808,
1
:2
3
I, -::;--Q'l
t . oJ
I 1
I I
I
I
-r,-
1,':- I 11:2-·!
,
! tj.K , ![iF: I 112KI ! 161(1
1 I
I
I
10-
t -r
11-
1.'1~-!
\ j,~:;Z!
1
1"1:2:1 ! 0- - i -;-':-1
i4J{ I i ;11c I
1
1
1 I
''"j'
10:"-
1!i.- -
11-;;-:'\
I
..... ~
I
I
I Dr< I ! L~K 1
1
! 1
1
-~I
I
11GKI
1
.-'! ,-.. ~ ". :
1 J, .:.1,-'
,--J
ITo:!.-:L11.~:8r18;::.V0rl
!~(
of
-
se~uentinl
:2ach. stucl.::
add~ea8081
C011tairlS
in order
!:l.2:':1
!~r.:.-!
1"()..:'-
116K!
11STCt
I LGC I
I
Into~10avod
t1..I'!.'::
1
E~, :~,
')
in
~airG,stecks
F~(:d~"c:n:;sfJd
i11
0
&3
Ol"(~ or
I
L__
10 11
1 ()-
I
.r=:--"=I,.
! 0 11 I:?'::'!
! [i- 1 18- i
1..-----·----··-;
__ _.c:----=:l
. 1
L,xo:c'lO:'l.vor' in l,ail's ~ s ta<:ks 1 g.,
a11(~
0
2:.
3,
Il1 t0~["le~\ro::
~-V~~
1 2·,
3,
?,
adCi l"0ssrad in o~rc1er
in. pai.1"13 , fccncl-::s 0 2~ 2
a6/;rGsse,~1
in order
10 11
101!
_I.
1231 12 31
18- I 10- ! 10- : 18- !
11()~1 InK I 12 rc 1 1J:]~i
[--10 :l.1
10- 1
l'iI£.J
__,..----L-,.-L.. ____:. . __I.
10 1\ 12 31 12 3;
l~- I 10- I l~- I
I. j ,0,.'.,
,... T-I
L_J
6)5.74/1
1,:,,:,~,
n., 1 I"
c: y-'
• ,c\;.cl
J).ltS:i.'loavocl in p:::d.rs p stnckG 1 &.
s;'i.d 0 &. 2, e.dd1'0:::;God on
3
ol~dol"
•______ or1
12
Irrtol'l10f':;ved
/:4:.d
3
i11
pairs p stucks 0 & 1
& 2, Qdd:,;"'ossod in order
1
J.~'-""l
\0 11 12 31 i2 v-::!
10- I 10- I 18- I
/=.171
18K 1 18K I l'~t
In.t0~~10eIoVDd
:121 pfLi3:~;-!';
1>
stncl~s
QllC: 0 ['..; 1» ;:;.ddl'0:!:sed in ordor
3
F~
2
(ell
18~
,!
119El
,._.- ......".... !
,
,
1
13
I~
!
-'-31 ,:;-;t.'J 1'0
(011 12
11
18·· I 18- I 10- I 10- !
I 16Kl 1:t6Kl 18?~ I 18IC I•
J:..I
'-l
..
8ui-c~~bJ.o prG(~4utionrs mud~ DS t(;),k'?JTl to ensure that the setting o.f this line
-1
"
l?.j\'T
:i.1.
tl10se bits specify throE!
53 -
states as fol10,,!s:-
"
00
Normal
01
Normal
10
Il~~.rel'se
11
Ohoy console switches
Ene1 Action -
of console s'.vi tcr"!.8s
'1
.
Continuous self test
'0 i
t
~l
00
O",l}r
the oc1.cJ
6.~:.-rJ:!. t
'rlO:!... ·.:1S
C~'l11~r
t110 evon r);! -bj {.
.o;;tO:'"'{(D
~,
10
c ......
• l,t
.Jt-"
" • I
._'
:.}:t
I."IU11C
t ion
",
'.~~
TIea':.l H.Gstore
12
1
~ ••'"
.>
12 b:V<:s
6.6.74/1
9. 6 .5
PST
See Bolow
5
Digits
59 - 62
REft.n ONLY Fault bits - one per stack
Rji'l - this bit initiates and term:L11a.tes
s01£ test when set
= OG
':
--1
l
J
Size
JI.Jl;i~~"(:ls
------:3
~
A.ccess
~ \:1~ -"iJ~~.:;
".1
!
b~1Jl":.dc:~~i'
l
o
PG~·tER S'rAC~I
b
8
1.
PG~'lEi~
srr !~C!~
1
0
0
R/W
R/I'l
'I
:"i
":' .... r ... -:·r;t---~
;;''''L.:I~.6.:\.
S:l'/~CI{
:2
8
R/W
P0~;\T}.?:?t.
STAC:f. J'-,
()
0
RjiN
o
,
~
o
I::\\\\\W\\i:\\\\W\\\\'~:\WS\\\\,I,\\\,\
\ W~~~Stj t::
..-..;..;.I--..
---~
50
3:(.;
i
J
Eif.~~~. t~1
-,r.:..
.:JiJ ->
-::;'1,
...;.
PCflJ.Yel~
Bupply 0
58
60
~>
"""
v'"
\..~
PO'7J01'"
SUlJply i
->
·51
T'O\78:t~
Supply 2
,.
>.:;2
_.>
63
POW02'
SUPJ)ly
p1_
3
'lalue
u
00
Roduced ID2.rgin
11
LJ
u
Irlcrof1.sod margin
II
l_
OFF LDm STACKS
R
Ii
L.
28
1 1 1 1
I ~'1\S\\\\W\~\\I,S\\\\\I\\Vj\,N\\\\'0\@W:\W I !
[!
2
3
I I ! I
i-
I I
I
3
I I 1_-STACK
Srjlo\no,o7 ~
A.h.·..... .!.:.. :4
I 1_ STACK 1
~-
I
1_ STACK 0
r,
~ d0f ine
'rheas hi to when set to v1
m'i..7 LUTZ..
a s tack to be
This is achieved mal'l.t:l::?11y 0
r~
,
5
WORKING ST ACES
I
Rji'i
This line has tho same format as line 40
L '
Each bit wb,m set specifies 0.. stack to be vlm:,king
n02'mally.
RGset to put a stack on -Cos';; 0
6
RjW
2
Bits
62 and 63 of this line
stacks 0 to
define which of
3 is on self test.
~!
Rfi'l
7
Sottins: bit 63 in.itiB.tes self test
spGcified in line 6"
8
To
6
SELF TEST Crn-rERGL
tho stack
reset testing a,fto2"
I,'
'I
,
,C - '
011
I
<''l.
RjW
.J
!
L
Before putting any stack
(58 -> 60)
Wj,'i tten
al'l.d
all
self test, patt01'ns
operating modes (61 ->
63)
08.11 bG
to thi;:; line ..
I
-
'
I
:. 1
n
l
J
LJ
R/W
3
Sit
61 is SEQ
~d specifies only ono cyclc of
all addresses of 'che stack on toot (' 1 V) or
continuous cycling (V O')"
Bit
62 is ST a.."lu for the stack on test specifies
?stop at end of current
stOl'O
cycle V (t1')0
Bit 63 is CON' c",.nd specifics (for the stack on
tos t)
'1
s top on
,,-~J
1./;,
13:;:'1'01'
th:ts hi t
('
0~)
CM
0
To continue aftel"
be reset to
t
1? then
17
10
u
stop on erTOl" 'l
• ')
h
rl'i.lis lLto holds the address at which 8,..'1.
03.'1'01'
---,
1
"I
I
LJ
"
12
6
H=Reoet
26
,
1111:1.1
I ~\SW\\,&\\\0\\WlWW0\\\"";\ ·.\C\'15\""\~"'\"'\\\, I I ! I I
I I
I I I I 63
32
1 I
I I
I
I I
.
PFAC
I
I I
\ i 1 - PF3
I I
i 1_ PFZ
I
1__ pi<'1
I 1_ '0"'0-I 1_ PJJ;V-1_ INVALID P.J)DRBSS
\\T1\
~J
]):.~~i t
Sg--(PFV)
Pnri tios
V store liP date.
59
(PFO)
Stack 0 riP or OIP data
60
(PF:~)
Stacl~
1 liP
01'
DIP dZ;Ct"
61
(PF.2)
Stack 2 liP
0:;:-
DIP data
62
(PF3)
Stack 3 liP
OJ:'
alP data
63
(PFAC)
Address or Control bits
[l
~l
f:t'·or~1.
E::!:changc
57
(INVAL)
INVALID ADDRESS SOl'l.t
i.,0 q
to
int0rf~C0
to high fo:;;, numbol' of si::ac1c.s
working
If
~!1.y
of tl1GSe bits is set a sigl1al is sent to
eJrohan.go end to the Engineers Door 3.l"1d Consolo"
ST ACI{ 0 S'I'.A.'rUS
3
serACK 1 STATUS
3
ST _/!.Cli :2 fIf ATUS
3
R
3
R
•
R
J
,_ J
1
>_
15
~l
<% 1";
ST ACK
<70
to)
3
S~f'/lTUS
'['he formats of theso
Ri;~(i
6:1.
62
4-
~_
J
.
J
lines are the s::,.me.,
t
Power Supply on margin
Stack or. self test
Error during self test
RfVl
2·
~1
Tnis specifies 'which section of the data or
address word is to be reo.d 'whsn reading '!,'DO
or 'fA lines 24 and 26
0
._ i
~o~
:'ofers to the most
'23"
:cof e~s to the leas t s ignif ican t: sec tion.
significant section,
(i
'__ I
9 aE~
Tr.~e Sys tom Po}:f :.J:l'ma:ac:o Uoni tor Vx-s tore
follGwi~"1g:-
The SystmTI PerfOrri1.a,·lce Monitor Vx store consists of the
This line is accBssed by using a real moele
spGcified in the
origir~o,
de5c:ciptor~
with
V·-::;'t:e2·'~
The real address part specified is irrelevant"
Tile top 32 bi t:J 0':: 'che V-linG are '\'!:d te only (if :read, they retu:"n 0).
o
nesats
J.
~~d
icitiates
histogr~n
logic
2
RCV/iL
CV03:,:;,·idcs validation lines for hi3tograi11 input
3
~li'TOI~F
Tu:cns off interrupt
4
E:~ablo bits
u
5, 6, 7
Initiates fast counters
~i
6
H,t)sets
7
3I rf
f~st
counters
()
0
9
l~A.!O
:i.0
1:1.
L.J
BIT
R/~J:l
Used as RAIO
12
13
Rn,!:l_ i
:i..:t
~nr.IS.J
15
t.t'
CCl1tl'ol the input mode on
'~he
histogrz-.l·I\ input cha.""1nels
Allows DV!G1.1
Histogr::~,m
logic to cOT.tinuo
upon overflew of Y-Counter
2IT·
'.,
16
17
1G
,/
Set the scale factor
18
19
two
P:rsscalar
P1..~:'.:;:3:"
BIT
20
Enable bits 23g 2L!.p 251
21
Not usod
:22
Not used
HSAC
7,0, 27 ~ 28, 29; 30
Allows CPU to ·wri te to or road
tho :real star0 via ExchangG
RSlV)
Initiates the display of the store
contents on the VDU
25
iiSAIE
26
RSAID!1
J:ncl'Erment/Decremont Histogram 1.10de
27
RSAECF!
Clears 'l'i tle store
nO
Dwell
..t,()
H:i.8togr~.rn
2()
RS[;.DAD
Direct Addressing rno(1e
30
'27
RSARD
Clears Data store
be
zn
&:;
30
29
NOTE =
,, ,,
mode
CIoal's ti tIe store and data
,
st01:'O
~,
E::-::.8.Elpt for those pairs notecl t only one bit in tho
abov0 group should be set at a timoo
BIT
Turn off parity fail indicator
BITS
32
BIT
60
Not used
61
}:ioni tor is in Ma."lual Mode
->
59
Not used
J
c
~\
BIT
BIT
6~
..J
in one of the i'ollowing
:·;106 c:;
:
i
~-. ~!
111 ANUAL, DISPLAY ~ CLEAl1.-STORE
. ,
r~
l J
'l
~l'hi8
cor:.~~is·t.s
of
3
bloci:::s of store addressed as follcN1S:-
~J
Size
----'
o
R/W
8
.
tore bi ts LtS
16 :;;: 32
To z"Gad thas3
cou~t0rs
bits
- 63
bits
- 63 of the highway
u
256 x 7 bits
i
U
,J
L-J
LJ
u
--1
L~
-
1
'I
~-
u
I
of the highway
I!
_J
I,
.
)
_
)
'l
,
J
Chapter 10
The
Basic~~rogramming
Language - XPL
XPL compilers e:dst for MUS and the 1900.
bOtt:C01l
unG..voidcblo
diif'3:;~e:nc0a
Sin.ce tbOi
1900
vers:.1.on~
difforences
b$en a.imed for, however, there are
h~,6
the compilers
Cornpatibili ty
0
compiler will be used rnore extensively than tho
~m5
th:to doscription applies to the MUS version, any
be~7e0n
the compilers will be mentioned.
':
o
--,,
Prog:i:'am & Statemonts
"
0
LJ
Blocks "
Declarative:,;
l
u
G
"
10 0 5
•
0
"
" " 10
"
0
"
..
•
0
$
000
' ..
o
0
•
o •
o
o
"
"
c
Q
e
•
000
(1)
Var:!.s.bJ.e Declarations
(2)
Literal Declarations
0
•
•
0
0
•
"
0
•
....
o
0
..
0
"
. .
o
The T0S~i; Bits in v.lS
. 1
u
u
'J
"
..
"
0
o
•
•
•
0
•
•
0
"
0
•
"
0
6
1007
"
" .
"
P.lto:l"n.-a"Cive Punching Conventions for the VDU's
Special DirectivG Stutements
"
. .. "
..
. . ..
o
o
0000880
0
"
0
(I:
•
0
0
o
0
o
•
•
"
10 0 i!.
II)
a
Procedure C811'Facilitias
o
•
.. "
Conditional
0
0
"
(4.)
•
o
"
D~~ga:rdsational
0
•
"
(3)
10.,3
•
o
Store to store
0
•
" "
(2)
..
o
"
Comput8:i:ior~al
o
•
"
(1 )
" 10,,1
•
Q
"
..
o
" .. . .. • • •
"
LJ
-,
.
" "
" " "
G
..
"
"
"
0
G
10 a:i.:l.
10,,1,,1
Modified BNF (Backus l'faur FOl'm) is used to define any
The mOdifica.tions to the BNF are as follows.
(1)
'.
)
~-
.'
Xn the order of alternatives and of elements within alternatives:=
eo
Any
no
If one
alte~native
which is a stem of another comes after
~~lte:t'i.'l.ative
it~
is a special case of anotherp it must
comG firsta
CoO
In recursiv0 d'afillitiol1.s g thel'e must be at least one
Several
alt0rn~tiv0S
s..l1.otha:..~
by ene'losing them in square brackets II
may be specified as an element of
-1
'-
.
)
J
. J
~
!
.'
',.
::=
*SEGMENT
BEGIN
L.J
END
*END OF SEGMENT
The
COi."Lsists of So nltmb~r of sta.tements g EJ.nd hene,,,, Ii
Ll
~::.-: <81'ATEMENT> [
I ]
L1
"
::= I
<1'ABLB> I
<'I'EX'I'>- I
I
t
I
':::SE;P>
::~
!
and ':7110:;;'0 com."1l0nt comm(ll1ces wi t11
.-.-l
:i1.0\11i~e
0
t\'lO
colons and terminates 't7i th a
1"01' 1:1.;:';'0 cOTI.tinuat~"C:Il1, purposes 11' is ignored It
Th.) ooven tYP0S of XPL stataments ara explained in the
" J
u
fol1cw:l::.i.g s0otion3
Q
10.3 l
Q
Name~.Litera18 &
Since the busic
lit~rals,
(1)
Labels
oper~,ds
in the language are names and
it is convenient to define them first.
Names & Literals
::= I
%!
~ - .'
!~ !
I
::= [+1-1 ] [ • I ]
::= [!]
::=
::= ~!11213141516171819!AIBICIDIEIF
[I«I~~EGER»][I]
::
= [ I ][ I
]
!:=
::== a ve:c'tical bar
::= 1
::=
r 1 I .][ I
]
::= D I[ I ]
I[.[.I]I
]
(2)
::= 0111213
::= 0!1121314151 61 7
Labels
A label talces the form of a nama followed by a colon, i.e og