EB68 MachXO2 Breakout Board Evaluation Kit User’s Guide Mach XO2Breakout Users 952920

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
MachXO2 Breakout Board Evaluation Kit
User’s Guide

January 2014
Revision: EB68_02.2



MachXO2 Breakout Board
Evaluation Kit User’s Guide

Introduction
Thank you for choosing the Lattice Semiconductor MachXO2™ Breakout Board Evaluation Kit!
This user’s guide describes how to start using the MachXO2 Breakout Board, an easy-to-use platform for evaluating and designing with the MachXO2 ultra-low density FPGA. Along with the board and accessories, this kit
includes a pre-loaded demonstration design. You may also reprogram the on-board MachXO2 device to review
your own custom designs.
The MachXO2 Breakout Board currently features the MachXO2-7000HE device. A previous version of this board
featured the MachXO2-1200ZE. The board design and features have not changed, and consequently, this document can be used as a guide for either version of the board. If you require a board featuring the MachXO2-1200ZE,
Lattice recommends the MachXO2 Pico Development Kit.
See “Ordering Information” on page 16 for more information.
Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling
section of this document for handling and storage tips.

Features
The MachXO2 Breakout Board Evaluation Kit includes:
• MachXO2 Breakout Board – The board is a 3” x 3” form factor that features the following on-board components
and circuits:
– MachXO2 FPGA – Current board version: LCMXO2-7000HE-4TG144C 
(Previous board version no longer available: LCMXO2-1200ZE-1TG144C)
– USB mini-B connector for power and programming
– Eight LEDs
– 60-hole prototype area
– Four 2x20 expansion header landings for general I/O, JTAG, and external power
– 1x8 expansion header landing for JTAG
– 3.3V and 1.2V supply rails
• Pre-loaded Demo – The kit includes a pre-loaded counter design that highlights use of the embedded MachXO2
oscillator and programmable I/Os configured for LED drive.
• USB Connector Cable – The board is powered from the USB mini-B socket when connected to a host PC. The
USB channel also provides a programming interface to the MachXO2 JTAG port.
• Lattice Breakout Board Evaluation Kits Web Page – Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.
The content of this user’s guide includes demo operation, programming instructions, top-level functional descriptions of the Breakout Board, descriptions of the on-board connectors, and a complete set of schematics.

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Figure 1. MachXO2 Breakout Board, Top Side
LED Array (J4)

4x15 60-Hole
Prototype Array (J6)

MachXO2
PLD (U3)

Two 2x20
Header Landings
(J2, J4)

Two 2x20
Header Landings
(J3, J5)

FTDI
USB to UART/FIFO
IC (U1)

JTAG Header
Landing (J1)

USB Mini-B
Socket (J7)

Power/GND
Power LED
Test Points
(PWR_ON)
(TP1, TP2, TP3)

Storage and Handling
Static electricity can shorten the lifespan of electronic components. Please observe these tips to prevent damage
that could occur from electro-static discharge:
• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
• Store the evaluation board in the packaging provided.
• Touch a metal USB housing to equalize voltage potential between you and the board.

Software Requirements
You should install the following software before you begin developing new designs for the Breakout board:
• Lattice Diamond® design software
• FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)

MachXO2 Device
This board currently features the MachXO2-7000HE FPGA which offers embedded Flash technology for instanton, non-volatile operation in a single chip. Numerous system functions are included, such as two PLLs and 256
Kbits of embedded RAM plus hardened implementations of I2C, SPI, timer/counter, and user Flash memory. Flexible, high performance I/Os support numerous single-ended and differential standards including LVDS, and also
source synchronous interfaces to DDR/DDR2/LPDDR DRAM memory. The 144-pin TQFP package provides up to

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
114 user I/Os in a 20mm x 20mm form factor. Previous versions of this board featured the MachXO2-1200ZE PLD
in the same package. This version of the board is no longer available. A complete description of this device can be
found in the MachXO2 Family Data Sheet.

Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO2 device. The design
integrates an up-counter with the on-chip oscillator.
Note: You may obtain your Breakout Board after it has been reprogrammed. To restore the factory default demo
and program it with other Lattice-supplied examples see the Download Demo Designs section of this document.

Run the Demonstration Design
Upon power-up, the preprogrammed demonstration design automatically loads and drives the LED array in an
alternating pattern. The program shows a clock generator based on the MachXO2 on-chip oscillator. The counter
module is clocked at the oscillator default frequency of 2.08MHz to illustrate how low speed timer functions can be
implemented with a FPGA. The 22-bit up-counter further divides the clock to advance the LED display approximately every 500ms. The resulting light pattern will appear as an alternating pair of lit LEDs per row.
Figure 2. Demonstration Design Block Diagram
MachXO2
c_delay[20]
(~2 Hz)

22-bit
Up-Counter
Clock
Generator

1x8 LED
Array

c_delay[21:0]

2.08 MHz

WARNING: Do not connect the Breakout Board to your PC before you follow the driver installation procedure of this
section.
Communication with the Breakout Board with a PC via the USB connection cable requires installation of the FTDI
chip USB hardware drivers. Loading these drivers enables the computer to recognize and program the Breakout
Board. Drivers can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a stand-alone package.
To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:
1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.
2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.
3. Click Finish to install the USB driver.
4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a green Power LED (D9) will light indicating the board is powered on.
5. The demonstration design will automatically load and drive the LED array in an alternating pattern.

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
To load the FTDI chip USB hardware drivers via the stand-alone package on a Windows system:
1. Browse to www.latticesemi.com/breakoutboards and download the FTDI Chip USB Hardware Drivers package.
2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.
3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J7). After the connection is made, a green Power LED (D9) will light indicating the board is powered on.
4. If you are prompted, “Windows may connect to Windows Update” select No, not this time from available
options and click Next to proceed with the installation. Choose the Install from specific location (Advanced)
option and click Next.
5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder
created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified
folder and click OK.
6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.
7. Click Finish to install the USB driver.
8. The demonstration design will automatically load and drive the LED array in an alternating pattern.
See the Troubleshooting section of this guide if the board does not function as expected.

Download Demo Designs
The counter demo is preprogrammed into the Breakout Board, however over time it is likely your board will be modified. Lattice distributes source and programming files for demonstration designs compatible with the Breakout
Board. The demo design for the 1200ZE version of the board is available on the web. Use the same design files for
MachXO2-7000HE. Change the device in the Diamond Software tool and re-run the process flow to generate the
JEDEC for MachXO2-7000HE. The description below references the 7000HE version.
To download demo designs:
1. Browse to the Lattice Breakout Board Evaluation Kits web page (www.latticesemi.com/breakoutboards) of the
Lattice web site. Select MachXO2 Breakout Board Demo Source and save the file.
2. Extract the contents of MachXO21200ZEBreakoutBoardDemoDesignSource.zip to an accessible location
on your hard drive.
3. Open the Project in the Diamond Design Software and change the device to MachXO2-7000HE-4TG144C.
4. Run the Process Flow and regenerate the JEDEC file.
Continue to Programming a Demo Design with Lattice Diamond Design Software.

Programming a Demo Design with the Lattice Diamond Programmer
The demonstration design is pre-programmed into the MachXO2 Breakout Board by Lattice. If you have changed
the design but now want to restore the Breakout Board to factory settings, use the procedure described below.
To program the MachXO2 device:
1. Install, license and run Lattice Diamond software. See www.latticesemi.com/latticediamond for download and
licensing information.
2. Connect the USB cable to the host PC and the MachXO2 Breakout Board.

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
3. From Diamond, open the Default_pattern_w_standby.ldf project file.
4. Click the Programmer icon.
5. Click Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0). If the cable is not
detected, see the Troubleshooting section.
6. Click the Program icon. When complete, PASS is displayed in the Status column.

MachXO2 Breakout Board
This section describes the features of the MachXO2 Breakout Board in detail.

Overview
The Breakout Board is a complete development platform for the MachXO2 FPGA. The board includes a prototyping
area, a USB program/power port, an LED array, and header landings with electrical connections to most of the
FPGA’s programmable I/O, power, and JTAG pins. The board is powered by the PC’s USB port or optionally with
external power. You may create or modify the program files and reprogram the board using Lattice Diamond software.
Figure 3. MachXO2 Breakout Board Block Diagram
Bank 0

GPIO

USB Mini B
Socket

USB
Controller

2x20 Header
Landing (J2)

JTAG
Programming

1x8 Header
Landing (J1,
Optional JTAG
Interface)

A/Mini-B
USB Cable

Bank 1
GPIO

Bank 3 (-1200ZE)
Bank 3,4 & 5 (-7000HE)
2x20 Header
Landing (J4)

GPIO

2x20 Header
Landing (J3)

MachXO2-7000HE or
1200ZE device
8

GPIO

2x20 Header
Landing (J5)
Bank 2

6

LED
Array

MachXO2 Breakout Board
Evaluation Kit User’s Guide
Table 1 describes the components on the board and the interfaces it supports.
Table 1. Breakout Board Components and Interfaces
Component/Interface

Schematic
Reference

Type

Description

Circuits
USB Controller
USB Mini-B Socket

Circuit

U2: FT2232H

USB-to-JTAG interface and dual USB UART/FIFO IC

J7:USB_MINI_B

Programming and debug interface

FPGA

U3: LCMXO27000HE-4TG144C

7000-LUT device packaged in a 20 x 20mm, 144-pin TQFP

Output

D8-D1

Red LEDs
User-definable I/O
Optional JTAG interface

I/O

Components
LCMXO2
Interfaces
LED Array
Four 2x20 Header
Landings

I/O

J2: header_2x20
J3: header_2x20
J4: header_2x20
J5: header_2x20

1x8 Header Landing

I/O

J1: header_1x8

4x15 60-Hole Prototype
Area
Test Points

Prototype area 100mil centered holes.
Power

TP1: +3.3V
TP2: +1.2V
TP3: GND

Power and ground reference points

Subsystems
This section describes the principle sub systems for the Breakout Board in alphabetical order.
Clock Sources
All clocks for the counter demonstration designs originate from the MachXO2 on-chip oscillator. You may use an
expansion header landing to drive a FPGA input with an external clock source.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the
MachXO2. The remaining pins serve as power supplies for external connections. Each landing is configured as
one 2x20 100 mil.
Table 2. Expansion Connector Reference
Item

Description

Reference Designators

J2, J3, J4, J5

Part Number

header_2x20

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Table 3. Expansion Header Pin Information (J2)
Header Pin Number

-1200ZE Function

-7000HE Function

MachXO2 Pin

1

NC

NC

-

2

VCCIO0

VCCIO0

118, 123, 135

3

PT17D / DONE

PT36D / DONE

109

4

PT17C / INITn

PT36C / INITn

110

5

PT17B

PT36B

111

6

PT17A

PT36A

112

7

GND

GND

-

8

GND

GND

-

9

PT16D

PT33B

113

10

PT16C

PT33A

114

11

PT16B

PT28B

115

12

PT16A

PT28A

117

13

PT15D / PROGn

PT27D / PROGn

119

14

PT15C / JTAGen

PT27C / JTAGen

120

15

GND

GND

-

16

GND

GND

-

17

PT15B

PT25B

121

18

PT15A

PT25A

122

19

PT12D / SDA / PCLKC0_0 PT22D / SDA / PCLKC0_0

125

20

PT12C / SCL / PCLKT0_0

PT22C / SCL / PCLKT0_0

126

21

PT12B / PCLKC0_1

PT18B / PCLKC0_1

127

22

PT12A / PCLKT0_1

PT18A / PCLKT0_1

128

23

GND

GND

-

24

GND

GND

-

25

PT11D / TMS

PT17D / TMS

130

26

PT11C / TCK

PT17C / TCK

131

27

PT11B

PT15B

132

28

PT11A

PT15A

133

29

PT10D / TDI

PT14D / TDI

136

30

PT10C / TDO

PT14C / TDO

137

31

GND

GND

-

32

GND

GND

-

33

PT10B

PT11B

138

34

PT10A

PT11A

139

35

PT9D

PT10B

140

36

PT9C

PT10A

141

37

PT9B

PT9B

142

38

PT9A

PT9A

143

39

GND

GND

-

40

GND

GND

-

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Table 4. Expansion Header Pin Information (J3)
Header Pin Number

-1200ZE Function

-7000HE Function

MachXO2 Pin

1

VCC_1.2V

VCC_1.2V

36, 72, 108, 144

2

VCCIO1

VCCIO1

79, 88, 102

3

VCC_1.2V

VCC_1.2V

36, 72, 108, 144

4

NC

NC

-

5

PR10C

PR24A

74

6

PR10D

PR24B

73

7

PR10A

PR23A

76

8

PR10B

PR23B

75

9

GND

GND

-

10

GND

GND

-

11

PR9C

PR21A

78

12

PR9D

PR21B

77

13

PR9A

PR18A

82

14

PR9B

PR18B

81

15

GND

GND

-

16

GND

GND

-

17

PR8C

PR17A

84

18

PR8D

PR17B

83

19

PR8A

PR16A

86

20

PR8B

PR16B

85

21

GND

GND

-

22

GND

GND

-

23

PR5C / PCLKT1_0

PR12A / PCLKT1_0

92

24

PR5D / PCLKC1_0

PR12B / PCLKC1_0

91

25

PR5A

PR11A

94

26

PR5B

PR11B

93

27

GND

GND

-

28

GND

GND

-

29

PR4C

PR9A

96

30

PR4D

PR9B

95

31

PR4A

PR7A

98

32

PR4B

PR7B

97

33

GND

GND

-

34

GND

GND

-

35

PR3A

PR5A

100

36

PR3B

PR5B

99

37

PR2C

PR3A

105

38

PR2D

PR3B

104

39

PR2A

PR2A

107

40

PR2B

PR2B

106

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Table 5. Expansion Header Pin Information (J4)
Header Pin Number

-1200ZE Function

-7000HE Function

MachXO2 Pin

1

VCC_3.3V

VCC_3.3V

-

2

VCCIO3

VCCIO3/4/5

30, 16, 7

3

VCC_3.3V

VCC_3.3V

-

4

NC

NC

-

5

PL2A / L_GPLLT_FB

PL3A / L_GPLLT_FB

1

6

PL2B / L_GPPLC_FB

PL3B / L_GPPLC_FB

2

7

PL2C / L_GPLLT_IN

PL4A / L_GPLLT_IN

3

8

PL2D / L_GPLLC_IN

PL4B / L_GPLLC_IN

4

9

PL3A / PCLKT3_2

PL6A / PCLKT5_0

5

10

PL3B / PCLKC3_2

PL6B / PCLKC5_0

6

11

PL3C

PL8A

9

12

PL3D

PL8B

10

13

GND

GND

-

14

GND

GND

-

15

PL4A

PL9A

11

16

PL4B

PL9B

12

17

PL4C

PL10A

13

18

PL4D

PL10B

14

19

GND

GND

-

20

GND

GND

-

21

PL5A / PCLKT3_1

PL12A / PCLKT4_0

19

22

PL5B / PCLKC3_1

PL12B / PCLKC4_0

20

23

PL5C

PL15A

21

24

PL5D

PL15B

22

25

GND

GND

-

26

GND

GND

-

27

PL8A

PL17A

23

28

PL8B

PL17B

24

29

PL8C

PL19A

25

30

PL8D

PL19B

26

31

GND

GND

-

32

GND

GND

-

33

PL9A / PCLKT3_0

PL22A / PCLKT3_0

27

34

PL9B / PCLKC3_0

PL22B / PCLKC3_0

28

35

GND

GND

-

36

GND

GND

-

37

PL10A

PL24A

32

38

PL10B

PL24B

33

39

PL10C

PL25A

34

40

PL10D

PL25B

35

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Table 6. Expansion Header Pin Information (J5)
Header Pin Number

-1200ZE Function

-7000HE Function

MachXO2 Pin

1

NC

NC

-

2

VCCIO2

VCCIO2

37, 51, 66

3

PB20D / SI / SISPI

PB38B / SI / SISPI

71

4

PB20B

PB37B

69

5

PB20C / SN

PB38A / SN

70

6

PB20A

PB37A

68

7

PB18D

PB35B

67

8

PB18B

PB31B

62

9

PB18C

PB35A

65

10

PB18A

PB31A

61

11

GND

GND

-

12

GND

GND

-

13

PB15D

PB29B

60

14

PB15B

PB26B

58

15

PB15C

PB29A

59

16

PB15A

PB26A

57

17

GND

GND

-

18

GND

GND

-

19

PB11B / PCLKC2_1

PB23B / PCLKC2_1

56

20

PB11D

PB18B

54

21

PB11A / PCLKT2_1

PB23A / PCLKT2_1

55

22

PB11C

PB18A

52

23

GND

GND

-

24

GND

GND

-

25

PB9B / PCLKC2_0

PB16B / PCLKC2_0

50

26

PB9D

PB13B

48

27

PB9A / PCLKT2_0

PB16A / PCLKT2_0

49

28

PB9C

PB13A

47

29

GND

GND

-

30

GND

GND

-

31

PB6D / S0 / SPISO

PB12B / S0 / SPISO

45

32

PB6B

PB9B

43

33

PB6C / MCLK / CCLK

PB12A / MCLK / CCLK

44

34

PB6A

PB9A

42

35

GND

GND

-

36

GND

GND

-

37

PB4D

PB6B

41

38

PB4B

PB4B

39

39

PB4C / CSSPIN

PB6A / CSSPIN

40

40

PB4A

PB4A

38

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Figure 4. J2/J4 Header Landing Callout
J4

1

2

1

2

NC
109
111
GND
113
115
119
GND
121
125
127
GND
130
132
136
GND
138
140
142
GND

IO0
110
112
GND
114
117
120
GND
122
126
128
GND
131
133
137
GND
139
141
143
GND

3.3
3.3
1
3
5
9
GND
11
13
GND
19
21
GND
23
25
GND
27
GND
32
34

IO3
NC
2
4
6
10
GND
12
14
GND
20
22
GND
24
26
GND
28
GND
33
35

Top Side

LCMXO2-7000HE
4TG144C

J2

J2

J4

Figure 5. J3/J5 Header Landing Callout
J3

J3

J5

LCMXO2-7000HE
4TG144C

Top Side

12

J5

1

2

1

2

1.2
1.2
74
76
GND
78
82
GND
84
86
GND
92
94
GND
96
98
GND
100
105
107

IO1
NC
73
75
GND
77
81
GND
83
85
GND
91
93
GND
95
97
GND
99
104
106

NC
71
70
67
65
GND
60
59
GND
56
55
GND
50
49
GND
45
44
GND
41
40

IO2
69
68
62
61
GND
58
57
GND
54
52
GND
48
47
GND
43
42
GND
39
38

MachXO2 Breakout Board
Evaluation Kit User’s Guide
Figure 6. J1 Header Landing and LED Array Callout
LED Array
J1
1
3.3
TDO
TDI
NC
NC
TMS
GND
TCK

J1

LED

Function

MachXO2
Pin

D8
D7
D6
D5
D4
D3
D2
D1

LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0

107
106
105
104
100
99
98
97

D8

D1

8
Top Side

LCMXO2-7000HE
4TG144C

MachXO2 FPGA
The MachXO2-7000HE-4TG144C is a 144-pin TQFP package FPGA device which provides up to 114 usable I/Os
in a 20 x 20mm package. 108 I/Os are accessible from the breakout board headers.
Table 7. MachXO FPGA Interface Reference
Item

Description

Reference Designators

U3

Part Number

LCMXO2-7000HE-4TG144C

Manufacturer

Lattice Semiconductor

Web Site

www.latticesemi.com

JTAG Interface Circuits
For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a
PC host and the JTAG programming chain of the Breakout Board. The USB 5V supply is also used as a source for
the 3.3V supply rail. A USB mini-B socket is provided for the USB connector cable.
Table 8. JTAG Interface Reference
Item

Description

Reference Designators

U1

Part Number

FT2232HL

Manufacturer

Future Technology Devices International (FTDI)

Web Site

www.ftdichip.com

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Table 9. JTAG Programming Pin Information
Description

MachXO2 Pin

Test Data Output

137:TDO

Test Data Input

136:TDI

Test Mode Select

130:TMS

Test Clock

131:TCK

LEDs
A green LED (D9) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO2 device.
Table 10. Power and User LEDs Reference
Item

Description

Reference Designators

Red LEDs (D1, D2, D3, D4, D5, D6, D7, D8)
Green LEDs (D9)

Part Number

LTST-C190KRKT (D1-D8)
LTST-C190KGKT (D9)

Manufacturer

Lite-On It Corporation

Web Site

www.liteonit.com

Power Supply
3.3V and 1.2V power supply rails are converted from the USB 5V interface when the board is connected to a host
PC.
Test Points
In order to check the various voltage levels used, test points are provided:
• TP1: +3.3V
• TP2: +1.2V
• TP3: GND
USB Programming and Debug Interface
The USB mini-B socket of the Breakout Board serves as the programming and debug interface.
JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the
Breakout Board to serve as the programming interface to the MachXO2 FPGA.
Programming requires the Lattice Diamond or ispVM System software.
Table 11. USB Interface Reference
Item

Description

Reference Designators

U1

Part Number

FT2232HL

Manufacturer

Future Technology Devices International (FTDI)

Web Site

www.ftdichip.com

14

MachXO2 Breakout Board
Evaluation Kit User’s Guide
Board Modifications
This section describes modifications to the board to change or add functionality.
Bypassing the USB Programming Interface
The USB programming interface circuit (USB Programming and Debug Interface section) may be optionally
bypassed by removing the 0 ohm resistors: R5, R6, R7, R8 (See Appendix A. Schematics, Sheet 2 of 5). Header
landing J1 provides JTAG signal access for jumper wires or a 1x8 pin header.
Applying External Power
The Breakout Board is powered by the circuit of Schematic Sheet 5 of 5 based on the 5V USB power source. You
may disconnect this power source by removing the 0 ohm resistors: R42 (VCC_1.2V) and R44 (VCC_3.3V). Power
connections are available from the expansion header landings, J3 (+1.2V, pins 1 and 3, schematic sheet 3 of 5) and
J4 (+3.3V, pins 1 and 3, schematic sheet 4 of 5).
Measuring Bank and Core Power
In addition to the expansion headers, test points (TP1, TP2) provide access to power supplies of the MachXO2
FPGA. Inline 1 ohm resistors: R24 (VCCIO0, +3.3V, Bank 0), R25 (VCCIO1, +3.3V, Bank 1), R26 (VCCIO2, +3.3V,
Bank 2), R27 (VCCIO3, +3.3V, Bank 3), R56 (VCC core, +1.2V) can be used to measure current for the power supplies.

Mechanical Specifications
Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]

Environmental Requirements
The evaluation board must be stored between -40° C and 100° C. The recommended operating temperature is
between 0° C and 90° C.
The board can be damaged without proper anti-static handling.

Glossary
FPGA: Field Programmable Gate Array
DIP: Dual in-line package
LED: Light Emitting Diode.
LUT: Look Up Table
PCB: Printed Circuit Board
RoHS: Restriction of Hazardous Substances Directive
USB: Universal Serial Bus
WDT: Watchdog Timer

Troubleshooting
Use the tips in this section to diagnose problems with the Breakout Board.
LEDs Do Not Flash
If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is
likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design section to restore the factory default.

15

MachXO2 Breakout Board
Evaluation Kit User’s Guide
USB Cable Not Detected
If Lattice Diamond Programmer or ispVM System does not recognize the USB cable after installing the Lattice USB
port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the
board to your PC prior to installing the Lattice-supplied USB driver.
To access the Troubleshooting the USB Driver Installation Guide:
For Diamond software and standalone Diamond Programmer:
1. Start Diamond or Diamond Programmer and choose Help.
2. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic.
3. Follow the directions to install the Lattice USB driver.
For ispVM:
1. Start ispVM System and choose Options > Cable and I/O Port Setup.
The Cable and I/O Port Setup Dialog appears.
2. Click the Troubleshooting the USB Driver Installation Guide link.
The Troubleshooting the USB Driver Installation Guide document appears in your system’s PDF file reader.
3. Follow the directions to install the Lattice USB driver.
Determine the Source of a Pre-Programmed Device
If the Breakout Board has been reprogrammed, the original demo design can be restored. To restore the board to
the factory default, see the Download Demo Designs section for details on downloading and reprogramming the
device.

Ordering Information
Description

Ordering Part Number

MachXO2-7000HE Breakout Board Evaluation Kit

LCMXO2-7000HE-B-EVN

MachXO2 Breakout Board Evaluation Kit

LCMXO2-1200ZE-B-EVN1

1.For reference only. This version of the board is no longer available for sale.

Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com

16

China RoHS Environment-Friendly
Use Period (EFUP)

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Revision History
Date

Version

December 2011

01.0

Initial release.

Change Summary

January 2012

01.1

Figure “MachXO2-1200ZE Breakout Board, Top Side” updated with revision B board photo.

December 2012

01.2

Updated document to describe new version of the board featuring the
MachXO2-7000HE. Indicated that the MachXO2-1200ZE version of the
board is no longer available.

February 2013

02.0

Updated Tables 3-6 to include -7000HE information. Added -7000HE
notes to Figure 3 and Appendix A.

September 2013

02.1

Updated procedure in Programming a Demo Design with the Lattice
Diamond Programmer section.
Added information to the procedure on loading the FTDI chip USB hardware drivers via the standalone package:
Updated description of Reference Designators in the Power and User
LEDs Reference table.

January 2014

02.2

Updated description and procedure for downloading demo designs in
Download Demo Designs section.
Updated project file name in Programming a Demo Design with the Lattice Diamond Programmer section.

© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

17

18

A

B

C

D

5

USB
CONNECTOR

5

USB to
JTAG / RS232

4

4

Power from USB 5V

3

I/Os

3

HEADER

FPGA

BANK 0

JTAG
HEADER

2

I/Os

BANK 2

LCMXO2-7000HE-4TG144C or
LCMXO2-1200ZE-1TG144C

I/Os + I2C

2

HEADER
Thursday, April 21, 2011

1

Sheet

1

of

5

LCMXO2-7000HE-B-EVN or LCMXO2-1200ZE-B-EVN

Document Number

Rev
A

Lattice MachXO2 1200ZE Breakout Board - Block Diagram

Date:

Size
B

Title

AXELSYS

RS232

I/Os + SPI

LEDS(1-8)

1

A

B

C

D

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Appendix A. Schematics

Note: The schematics are drawn using the MachXO2-1200ZE device. Please consult Tables 3 through 6 for -1200
and -7000HE pin name and bank synonyms. Pin numbers are correct for either device.

Figure 7. Block Diagram

BANK 3
BANK 1

HEADER

A

B

C

0.1uF

C12

+3.3V

8
7
6
5

CS
CLK
DI
DO

5

93LC56-SO8

VCC
NU
ORG
VSS

U2

1
2
3
4

0.1uF

0.1uF

0.1uF

R11
10k

+3.3V

C6

C8

C5

+3.3V

R12
10k

0.1uF

C9

R19

R13
10k

2k2

0.1uF

C7

4

L2

1
2
600ohm 500mA

C13
18pF

0.1uF

10uF

2

1

C11

C10

VCC1_8FT

+3.3V

L1
2
1
600ohm 500mA

3

12MHZ

4

3

+3.3V

C3
4u7

C1
4u7

G1 G2

1

X1

1
2
1
2

+3.3V

5
5

12k 1%

R9

C14
18pF

3

FT_EECS
FT_EECLK
FT_EEDATA

R10

2k2

0.1uF

C4

0.1uF

C2

3

DM
DP

13

3

2

63
62
61

6

14

7
8

49

50

VCC1_8FT

FT2232H

+3.3V

PWREN#

BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7

BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7

ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7

ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7

SUSPEND#

FTDI High-Speed USB

TEST

OSCO

OSCI

EECS
EECLK
EEDATA

REF

RESET#

DM
DP

VREGOUT

VREGIN

U1
FT2232HL

AGND
10

D

4

4
9
VPHY
VPLL

12
37
64
VCORE
VCORE
VCORE

20
31
42
56
VCCIO
VCCIO
VCCIO
VCCIO

GND
GND
GND
GND
GND
GND
GND
GND

19
1
5
11
15
25
35
47
51

5

36

60

48
52
53
54
55
57
58
59

38
39
40
41
43
44
45
46

26
27
28
29
30
32
33
34

16
17
18
19
21
22
23
24

TDO

TDI

TMS

2

2

0
0
0
0

0
0
0
0
0
0
0

1
2
3
4
5
6
7
8

AXELSYS

RS232_Rx_TTL
RS232_Tx_TTL
RTSn
3
CTSn
3
DTRn
3
DSRn
3
DCDn
3

+3.3V

TCK

3
3

TCK
TDI
TDO
TMS

3
3
3
3

2k2

R4

FOR FUTURE RS232 FUNCTION

TCK

TMS

TDO
TDI

1

Date:

Size
B

Thursday, April 21, 2011

LCMXO2-1200ZE-B-EVN

Document Number

1

Sheet

2

of

5

Rev
A

Lattice MachXO2 1200ZE Breakout Board -USB to JTAG

Title

DNI
DNI
DNI
DNI
DNI
DNI
DNI

1
2
3
4
5
6
7
8

J1

header_1x8
DNI

5k1

5k1

5k1

R5
R6
R7
R8

R3

R2

R1

R14
R15
R16
R17
R18
R20
R21

+3.3V

A

B

C

D

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Figure 8. USB Interface to JTAG

20

A

B

C

D

PT10A
PT9C
PT9A

PT11C_TCK_TESTCLK
PT11A
PT10C_TDO

PT15A
PT12C_SCL_PCLT0_0
PT12A_PCLKT0_1

PT16C
PT16A
PT15C_JTAGen

PT17C_INITn
PT17A

5

VCCIO0

5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Header2x20
DNI

J2

MAKE PWR TRACES
CAPABLE OF 1A

PT10B
PT9D
PT9B

PT11D_TMS
PT11B
PT10D_TDI

PT15B
PT12D_SDA_PCLKC0_0
PT12B_PCLKC0_1

PT16D
PT16B
PT15D_PROGn

PT17D_DONE
PT17B

2
2

2
2

2k2

R22

4

TDI
TDO

TMS
TCK

2k2

R23

+3.3V

4

C17
0.01uF

R24

0.1uF

C20

1

VCCIO0

0.1uF

+3.3V

C19

0.1uF

PT9D
PT9C
PT9B
PT9A

PT10B
PT10A

PT11D_TMS
PT11C_TCK_TESTCLK
PT11B
PT11A

C18

VCCIO0

PT10D_TDI
PT10C_TDO

119
120
121
122

PT15D_PROGn
PT15C_JTAGen
PT15B
PT15A

BANK 0

BANK 1

PR8D
PR8C
PR8B
PR8A

PR9D
PR9C
PR9B
PR9A

PR10D
PR10C
PR10B
PR10A

VCCIO0
VCCIO0
VCCIO0

VCCIO1
VCCIO1
VCCIO1

NC4
PT12D/SDA/PCLKC0_0
PT12C/SCL/PCLKT0_0
NC5
PT12B/PCLKC0_1
PT12A/PCLKT0_1
PCLKC1_0/PR5D
PCLKT1_0/PR5C
PT11D/TMS
PR5B
PT11C/TCK/TEST_CLK
PR5A
PT11B
PR4D
PT11A
PR4C
PT10D/TDI
PR4B
PT10C/TDO
PR4A
PT10B
PT10A
PR3B
PR3A
PT9D
NC6
PT9C
PT9B
PT9A
PR2D
PR2C
PR2B
PR2A

PT15D/PROGRAMn
PT15C/JTAGENB
PT15B
PT15A

PT16D
PT16C
PT16B
PT16A

PT17D/DONE
PT17C/INITn
PT17B
PT17A

79
88
102

104
105
106
107

103

99
100

95
96
97
98

91
92
93
94

87
89

83
84
85
86

77
78
81
82

73
74
75
76

3

LCMXO2-7000HE-4TG144C or LCMXO2-1200ZE-1TG144C

118
123
135

140
141
142
143

136
137
138
139

130
131
132
133

125
126
127
128

113
114
115
117

PT16D
PT16C
PT16B
PT16A

PT12D_SDA_PCLKC0_0
PT12C_SCL_PCLT0_0
PT12B_PCLKC0_1
PT12A_PCLKT0_1

109
110
111
112

PT17D_DONE
PT17C_INITn
PT17B
PT17A

U3-2

3

PR2D
PR2C
PR2B
PR2A

PR3B
PR3A

PR4D
PR4C
PR4B
PR4A

0.01uF

C21

PCLKC1_PR5D
PCLKT1_PR5C
PR5B
PR5A

PR8D
PR8C
PR8B
PR8A

PR9D
PR9C
PR9B
PR9A

PR10D
PR10C
PR10B
PR10A

2

0.1uF

C22

LED4
LED5
LED6
LED7

LED2
LED3

LED0
LED1

DSRn
DCDn
DTRn

0.1uF

C23

5
5
5
5

5
5

5
5

R25

+3.3V

2
2
2

RS232_Rx_TTL
RS232_Tx_TTL
RTSn
2
CTSn
2

2

2
2

AXELSYS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Header2x20
DNI

J3

MAKE PWR TRACES
CAPABLE OF 1A

0.1uF

C15

PR3A
PR2C
PR2A

PR4C
PR4A

PCLKT1_PR5C
PR5A

PR8C
PR8A

PR9C
PR9A

PR10C
PR10A

VCC_1.2V

Thursday, April 21, 2011

LCMXO2-1200ZE-B-EVN

Document Number

1

Sheet

3

of

Lattice MachXO2 1200ZE Breakout Board - FPGA

Date:

Size
B

Title

1

VCCIO1

0.1uF

C24

VCCIO1

PR3B
PR2D
PR2B

PR4D
PR4B

PCLKC1_PR5D
PR5B

PR8D
PR8B

PR9D
PR9B

PR10D
PR10B

VCCIO1

1

5

Rev
A

0.1uF

C16

A

B

C

D

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Figure 9. FPGA

21

A

B

C

D

VCCIO3

5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

X2

Output

Vcc
3

4

R27

+3.3V

CB3LV-3C-50M0000

GND

EN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Header2x20
DNI

J4

C26
0.1uF

0.1uF

VCCIO3
C27
0.01uF

PL9A_PCLKT3_0

0.1uF

C53

PL10A
PL10C

PL9A_PCLKT3_0

PL8A
PL8C

PL5A_PCLKT3_1
PL5C

PL4A
PL4C

4

C25

4

0.1uF

C28

VCCIO3

PL2A_L_GPLLT_FB
PL2C_L_GPLLT_IN
PL3A_PCLKT3_2
PL3C

VCC_3.3V

+3.3V

1

MAKE PWR TRACES
CAPABLE OF 1A

50MHz OSC

2

1

DNI

This is optional
R54 to enable or
disable the
crystal.
0

PL10A

PL10B
PL10D

PL9B_PCLKC3_0

PL8B
PL8D

PL5B_PCLKC3_1
PL5D

PL4B
PL4D

PL2B_L_GPPLC_FB
PL2D_L_GPLLC_IN
PL3B_PCLKC3_2
PL3D

5

C29
0.1uF

0.1uF

C30

32
33
34
35

PL10A
PL10B
PL10C
PL10D

VCCIO3
VCCIO3
VCCIO3

PL10A
PL10B
PL10C
PL10D

PL9A/PCLKT3_0
PL9B/PCLKC3_0
NC2

PL8A
PL8B
PL8C
PL8D

PL5A/PCLKT3_1
PL5B/PCLKC3_1
PL5C
PL5D

PL4A
PL4B
PL4C
PL4D
NC0
NC1

PL3A/PCLKT3_2
PL3B/PCLKC3_2
PL3C
PL3D

PL2A/L_GPLLT_FB
PL2B/L_GPPLC_FB
PL2C/L_GPLLT_IN
PL2D/L_GPLLC_IN

BANK 3

VCCIO2
VCCIO2
VCCIO2

PB20A
PB20B
SN/PB20C
SI/SISPI/PB20D

PB18A
PB18B
NC3
PB18C
PB18D

PB15A
PB15B
PB15C
PB15D

PB11C
PB11D
PCLKT2_1/PB11A
PCLKC2_1/PB11B

PB9C
PB9D
PCLKT2_0/PB9A
PCLKC2_0/PB9B

PB6A
PB6B
MCLK/CCLK/PB6C
SO/SPISO/PB6D

PB4A
PB4B
CSSPIN/PB4C
PB4D

BANK 2

PB18A
PB18B

61
62
63
65
67

37
51
66

68
69
70
71

PB15A
PB15B
PB15C
PB15D

57
58
59
60

R28 DNI

R32 DNI

100
100

R40 DNI
PB11C
PB11D

PCLKT2_PB11A R41 DNI
PCLKC2_PB11B

3

100

100
R38 DNI

R36 DNI

100

100

100

100

PCLKT2_0_PB9A
PCLKC2_0_PB9B

PB9C
PB9D

MCLK_CCLK_PB6C R34 DNI
S0_SPISO_PB6D

PB6A
PB6B

CSSPIN_PB4C R30 DNI
PB4D

PB4A
PB4B

NOTE
PLACE ALL 100 OHM
DIFF TERM RESISTORS
ON BOTTOM OF BOARD

0.1uF

C32

R37 DNI

R35 DNI

R33 DNI

R31 DNI

R29 DNI

0.1uF

C33

SN_PB20C
R39 DNI
SI_SISPI_PB20D

PB20A
PB20B

PB18C
PB18D

PB18A
PB18B

PB15C
PB15D

PB15A
PB15B

0.01uF

C31

PB20A
PB20B
SN_PB20C
SI_SISPI_PB20D

PB18C
PB18D

PB11C
PB11D
PCLKT2_PB11A
PCLKC2_PB11B

PB9C
PB9D
PCLKT2_0_PB9A
PCLKC2_0_PB9B

PB6A
PB6B
MCLK_CCLK_PB6C
S0_SPISO_PB6D

PB4A
PB4B
CSSPIN_PB4C
PB4D

52
54
55
56

47
48
49
50

42
43
44
45

38
39
40
41

LCMXO2-7000HE-4TG144C or LCMXO2-1200ZE-1TG144C

7
16
30

27
28
31

23
24
25
26

PL9A_PCLKT3_0
PL9B_PCLKC3_0

PL8A
PL8B
PL8C
PL8D

19
20
21
22

11
12
13
14
15
17

PL4A
PL4B
PL4C
PL4D

PL5A_PCLKT3_1
PL5B_PCLKC3_1
PL5C
PL5D

5
6
9
10

1
2
3
4

PL3A_PCLKT3_2
PL3B_PCLKC3_2
PL3C
PL3D

PL2A_L_GPLLT_FB
PL2B_L_GPPLC_FB
PL2C_L_GPLLT_IN
PL2D_L_GPLLC_IN

U3-3

3

100

100

100

100

100

100

2

0.1uF

C34

VCCIO2

2

Date:

Size
B

Title

R26

+3.3V

AXELSYS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Header2x20
DNI

J5

PB4D
CSSPIN_PB4C

S0_SPISO_PB6D
MCLK_CCLK_PB6C

PCLKC2_0_PB9B
PCLKT2_0_PB9A

PCLKC2_PB11B
PCLKT2_PB11A

PB15D
PB15C

SI_SISPI_PB20D
SN_PB20C
PB18D
PB18C

Thursday, April 21, 2011

LCMXO2-1200ZE-B-EVN

Document Number

1

Sheet

4

of

5

Lattice MachXO2 1200ZE Breakout Board - FPGA

1

VCCIO2

PB4B
PB4A

PB6B
PB6A

PB9D
PB9C

PB11D
PB11C

PB15B
PB15A

PB20B
PB20A
PB18B
PB18A

MAKE PWR TRACES
CAPABLE OF 1A

VCCIO2

1

Rev
A

A

B

C

D

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Figure 10. FPGA

A

B

C

J7

1K

VCC
DD+
ID
GND

5

Input

3
IN

U5

Tab

Output

1

R53
C52

0
0.1uF

2
4

100

R55

0.1uF

C51

NCP1117

OUT
TAB
GND

4

2

600ohm 500mA

L5

VBUS_5V

10uF

C48

1
2
3
4
5

VBUS_5V

SKT_MINIUSB_B_RA

D9
Green

R43

10uF

3

GND
1

R42

R44

0

0

4

2
2

22uF

C49

VCC_3.3V

DM
DP

L3
1

+3.3V

+1.2V

J6

Proto Type Area

4X15 PROTOTYPE AREA

3

3
3
3
3
3
3
3
3

LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0

LAYOUT LEDs IN A SINGLE ROW

DNI
TP3

D8
Red

1K

R45

+3.3V

0.01uF

0.1uF

DNI

C41

C40

TP2

0.1uF

C39

DNI

0.1uF

C38

TP1
+1.2V

0.1uF

1uF

10uF

+3.3V

C37

C36

C35

Proto Type Area, Holes on 0.1 inch Centers

1

L4
1
2
600ohm 500mA

R56

0.1uF

C50

2
1
600ohm 500mA

22uF

C47

VCC_1.2V

1

D

1

2

1

C46

1

2

1

FAN1112

1
STATUS_LED7 2

U4

D7
Red

1K

R46

2

LEDs

1
STATUS_LED6 2

VBUS_5V

1
STATUS_LED5 2

2

D6
Red

1K

R47

1

1uF

10uF

36
72
108
144

AXELSYS

D4
Red

1K

R49

U3-1

D3
Red

1K

R50

1

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LCMXO2-1200ZE-1TG144C

VCC
VCC
VCC
VCC

VCCP

0.01uF

0.1uF

129

C45

C44

+3.3V

D2
Red

1K

R51

8
18
29
46
53
64
80
90
101
116
124
134

1
D1
Red

1K

R52

Thursday, April 21, 2011

LCMXO2-1200ZE-B-EVN

Document Number

1

Sheet

5

of

5

Rev
A

Lattice MachXO2 1200ZE Breakout Board - Power, LEDs

D5
Red

1K

+1.2V

C43

C42

R48

Date:

Size
B

Title

STATUS_LED4 2

3

1
STATUS_LED3 2

+1.2V

1
STATUS_LED2 2

4

1
STATUS_LED1 2

22
STATUS_LED0 2

5

A

B

C

D

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Figure 11. Power LEDs

MachXO2 Breakout Board
Evaluation Kit User’s Guide

Appendix B. Bill of Materials
Table 12. MachXO2 Breakout Board Bill of Materials
Item Quantity

Reference

Manufacturer

1

2

C1, C3

2

34

C2, C4, C5, C6, C7, C8, C9, C11, C12, C15, C16, C18,
C19, C20, C22, C23, C24, C25, C26, C28, C29, C30, C32,
C33, C34, C37, C38, C39, C40, C44, C50, C51, C52, C53

Part Number

Panasonic

ECJ-1VB0J475K

Kemet

C0402C104K4RACTU

3

5

C10, C35, C42, C46, C48

Taiyo Yuden

LMK107BJ106MALTD

4

2

C13, C14

Kemet

C0402C180K3GACTU

5

6

C17, C21, C27, C31, C41, C45

Kemet

C0402C103J4RACTU

6

2

C36, C43

Kemet

C0402C105K9PACTU

7

2

C47, C49

Taiyo Yuden

LMK212BJ226MG-T

8

8

D1, D2, D3, D4, D5, D6, D7, D8

LITE-On, Inc.

LTST-C190KRKT

9

1

D9

LITE-On, Inc.

LTST-C190KGKT

10

1

J1

Molex

22-28-4081

11

4

J2, J3, J4, J5

12

1

J6

Samtec

13

1

J7

Neltron

5075BMR-05-SM-CR

14

5

L1, L2, L3, L4, L5

Murata

BLM18AG601SN1D

15

3

R1, R2, R3

Yageo

RC0402FR-075K1L

16

5

R4, R9, R19, R22, R23

Yageo

RC0402FR-072K2L

17

8

R5, R6, R7, R8, R42, R44, R53, R54

Yageo

RC0603JR-070RL

18

1

R10

Yageo

RC0402FR-0712KL

Yageo

RC0402FR-0710KL

19

3

R11, R12, R13

20

7

R14, R15, R16, R17, R18, R20, R21

21

5

R24, R25, R26, R27, R56

22

14

23

9

Yageo

RC0603JR-070RL

Vishay/Dale

CRCW06031R00JNEAHP

R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38,
R39, R40, R41

Yageo

RC0603FR-07100RL

R43, R45, R46, R47, R48, R49, R50, R51, R52

Yageo

RC0402FR-071KL

Yageo

RC0603FR-07100RL
FT2232HL

24

1

R55

25

3

TP1, TP2, TP3

26

1

U1

FTDI

27

1

U2

Microchip

93LC56C-I/SN

28

1

U3

Lattice

LCMXO2-7000HE-4TG144C or
LCMXO2-1200ZE-1TG144C

29

1

U4

Fairchild Semi

FAN1112SX

30

1

U5

On Semi

NCP1117ST33T3G

31

1

X1

TXC

7M-12.000MAAJ-T

32

1

X2

CTS

CB3LV-3C-50M0000

23

Mouser Electronics
Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Lattice:
LCMXO2-1200ZE-B-EVN LCMXO2-7000HE-B-EVN



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : No
Page Count                      : 24
Page Mode                       : UseOutlines
XMP Toolkit                     : Adobe XMP Core 5.2-c001 63.139439, 2010/09/27-13:37:26
Creator Tool                    : FrameMaker 10.0.2
Modify Date                     : 2014:01:02 10:56:26+08:00
Create Date                     : 2000:11:21 10:30:03Z
Metadata Date                   : 2014:01:02 10:56:26+08:00
Format                          : application/pdf
Title                           : EB68 - MachXO2 Breakout Board Evaluation Kit User’s Guide
Creator                         : Lattice Semiconductor
Description                     :  MachXO2 Breakout Board Evaluation Kit User’s Guide
Producer                        : Acrobat Distiller 10.1.8 (Windows)
Document ID                     : uuid:9b182082-6d5f-409c-a1e1-bcef86426974
Instance ID                     : uuid:d305917c-a191-4954-ac98-a8b2b1ebad3d
Author                          : Lattice Semiconductor
Keywords                        : EB68, MachXO2, XO2, MachXO2 Breakout Board Evaluation Kit, LCMXO2-1200ZE-B-EVN, MachXO2-7000HE
Subject                         :  MachXO2 Breakout Board Evaluation Kit User’s Guide

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