TN1199 MachXO2 SysCLOCK PLL Design And Usage Guide Mach XO2sys CLOCKPLLDesignand

• MachXO2 sysCLOCK PLL Design and Usage Guide
  • Introduction
  • Clock/Control Distribution Network
  • MachXO2 Top Level View
  • Primary Clocks
  • Dynamic Clock Mux (DCMA)
    • DCMA Primitive Definition
    • DCMA Declaration in VHDL Source Code
    • DCMA Usage with Verilog Source Code
  • Dynamic Clock Control (DCCA)
    • DCCA Primitive Definition
    • DCCA Declaration in VHDL Source Code
    • DCCA Usage with Verilog Source Code
  • Edge Clocks
    • Edge Clock Bridge
  • ECLKBRIDGECS Primitive Definition
    • ECLKBRIDGECS Declaration in VHDL Source Code
    • ECLKBRIDGECS Usage with Verilog Source Code
  • Edge Clock Synchronization (ECLKSYNCA)
    • ECLKSYNCA Primitive Definition
    • ECLKSYNCA Declaration in VHDL Source Code
    • ECLKSYNCA Usage with Verilog Source Code
  • Secondary High Fan-out Nets
  • Clock Dividers (CLKDIVC)
    • CLKDIVC Primitive Definition
    • CLKDIVC Declaration in VHDL Source Code
    • CLKDIVC Usage with Verilog Source Code
    • CLKDIVC Instantiation
  • sysCLOCK PLL
    • Functional Description
    • PLL Features
    • PLL Inputs and Outputs
    • PLL Attributes
  • MachXO2 PLL Primitive Definition
  • Dynamic Phase Adjustment
  • Frequency Calculation
  • Fractional-N Synthesis Operation
  • Low Power Features
    • Dynamic Clock Enable
    • Standby Mode
  • Configuring the PLL Using IPexpress
    • Configuration Tab
    • Configuration Modes
    • IPexpress Output
    • Use of the Pre-MAP Preference Editor
  • PLL Reference Clock Switch (PLLREFCS)
  • Internal Oscillator (OSCH)
    • OSCH Primitive Definition
    • OSCH Declaration in VHDL Source Code
  • Technical Support Assistance
  • Revision History
  • Appendix A. Primary Clock Sources and Distribution
  • Appendix B. Edge Clock Sources and Connectivity
  • Appendix C. Clock Preferences
  • Appendix D. PLL WISHBONE Bus Operation
    • PLL Architecture
  • Appendix E. MachXO2 Device Usage with Lattice Diamond Design Software