_950_Terminal_Theory_of_Operation_26Jan1981 950 Terminal Theory Of Operation 26Jan1981
_950_Terminal_Theory_of_Operation_26Jan1981 _950_Terminal_Theory_of_Operation_26Jan1981
User Manual: _950_Terminal_Theory_of_Operation_26Jan1981
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950 Theory of Operation CPU, Timing and Control (Refer to Figure 1) The 23.814 Mhz oscillator (Osc 1) is used to generate all timing for the terminal. It is used directly as the dot clock (Shift Clock), divided by 13 to drive the UARTs, and divided by 14 (1.701 Mhz) to.drive the CRT controller (CCLK) and the CPU (via the clock stretch circuit). The clock stretch circuit is capable, upon command, of generating clock periods twice the normal length (588 ns versus 1175 ns) for accessing slow memory or peripheral devices. Its output drives the 10 input of the 6502 CPU. The CPU then outputs 12, which controls the timing of the CPU bus. 12 is a slightly delayed ver.sion of 1 0 • The result of these circuits are 12 and CCLK, two signals of identical frequency but opposite phase, (except during clock stretched cycles). The importance of this will be made clear later in our discussion of the display controller. The CPU fetches its program from the ROMs (Read Only Memory) A41-43. It uses the 6522 (A54) to sense switches Sl and S2 and to generate control signals for the test of the terminal. Display Controller (Refer to Figure 2) Timer T2, part of the 6522, and the 6545 (A55) are used to generate the memory address, in Display RAM, of each character as it is about to be displayed, and the horizontal and vertical synchronization pulses necessary to control the deflection circuits of the monitor. Timer T2 is used to count horizontal scan lines and interrupt the processor (via NMI) when a specified number of scans has occurred. The processor then loads the memory address of the next data row into the CRT Controller and "sets" this address by generating a carefully-timed reset to the 6545. At this same time the processor loads a 4 bit value into latch, A61. At the time of the CRT reset this value is transferred to counter A60 and becomes the Row Address of the next data row. This value is then incremented by each horizontal sync pulse until the start of the next data row when it is again preset to a value determined by the CPU. The CPU and the display controller share access to the System and Display RAM (Random Access Memory). This is done during alternate phases of the 12 clock. During the positive portion of 12 the CPU address may be gated onto the RAM address bus by Multiplexers A43-46, and bidirectional transceiver A14 is enabled to pass data between the CPU data bus and the RAM data bus. During the negative portion of 12 the 6545 address bus is gated onto the RAM address bus allowing the video data to be latched by A24 and held for the display generator. This alternating access or "interleaved" access allows the processor to operate at normal-speed, without wai't_s of any kind, yet prevents degradation of the display quality that could be caused by inadvertant appropriation of the display bus by the processor to access data. The only penalty for this scheme is the necessity for fast RAM (150 ns or faster). Video Generation (Refer to Figure 3) This Display Data and the Row Address (or scan address) are used to obtain the dots for the next character to be displayed from the character generator ROMs A32 and A33. These dots are then fed in parallel to shift registers A22 and A23 and emerge serially as raw video. Additionally, bits 0-3 of Display data and bit 7 of A33 are combined to generate the attribute signals Underline, Blink, Blank, and Reverse. ICs A19, 20, 21 and 30 latdhand delay the decoded attributes from the previous data row for carry-over into the next. Bit 6 of A33 controls the intensity of the character to be displayed. ~ Gates AI, 2, 10 and 11 are used to modify the raw video to the proper intensity and polarity, and gate it on or off in response to the attribute signals and control signals BOW (used to reverse the entire display), cursor, BLI-RATE (used to blink the video) and FORCE BLANK (used to blank the entire screen). Transistor Ql is used to dr.ive the video to the proper voltage and current levels to drive the video module and/or an external mon.itor (using the composite video jumpers) . I/O Circuits (Refer to Figure 4) UART A49 is used to receive (and optionally transmit) serial data from (and to) the keyboard. The transmit path to the keyboard is normally used to conduct the bell tone from the 6522 (via driver Q4) to the speaker in the keybo~rd. UARTs A50 (Main Port, P3) and A5l (Printer Port, P4) are used to send and receive ser ial data from P·3 and P4 via the dr ivers, receivers and switching circuits A39, 40, 47, 48, 56, 57, 58 and 59. The UARTs A49, 50 and A5l (655ls) are connected to the CPU Bus and generate IRQ interrrupts when commanded by the CPU to send or receive data. Additionally these parts contain internal baud rate generators that must be programmed by the CPU to control the baud rates. (". General Debugging Guidelines The following procedures are usually 90ne when there is no initial beep at turn on. To debug any microprocessor without an emulator, remove as mahy devices as possible from the bus •. This includes the CPU, CRT controller, VIA, UARTs, and Program, User, and Character Generator ROMs. The address and data lines can then be checked for proper operation. Field component failures will generally be the most complicated integrated circuits. In case of a failure of this type, first replace any of the socketed components associated with the failure symptoms. Should the problem persist, check the RAM, RS232 components, bus transceiver, and multiplexers. This failure group is the most difficult to troubleshoot. An effective way to check the RAM is to use a test wire with two clips. Connect one end to the R4/Dl junction in the video section of the logic and the other end touching the outputs of the RAM. This, in essence, uses the monitor as a scope. Compare the response on the screen with a good terminal, and using this method, a faulty terminal can be debugged quickly. Should the problem not be found in the second f~jlure group, a simple hard failure in any area could be the cause of the problem. . 1/26/81 ( PART NUMBER DOCUMENT NO. 29000 039 REV. 3, FEBRUARY 1979 '1' Rockwell R650X and R651X R6500 Microcomputer System DATA SHEET R6500 MICROPROCESSORS (CPU's) SYSTEM ABSTRACT FEATURES The S-bit R6500 microcomputer system is produced with NChannel, Silicon Gate technology. Its performance speeds are This innovative enhanced by advanced system architecture. architecture results in smaller chips - the semiconductor threshold to cost-effectivity. System cost-effectivity is further enhanced by providing a family of 10 software-compatible microprocessor (CPU) devices, described in this document. Rockwell also provides memory and microcomputer system ... as well as low-cost design aids and documentation. • • • • • • • • • • • • • • • • • • • • R6500 MICROPROCESSOR (CPU) CONCEPT Ten CPU devices are available. All are software-compatible. They provide options of addressable memory, interrupt input, on-chip clock oscillators and drivers. All are -b'us-compatible with earlier generation microprocessors like the M6S00 devices. The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by external clocks. The on-chip clock versions are aimed at high performance, low cost applications where single phase inputs, crystal or RC inputs provide the time base. The external clock versions are geared for multiprocessor system applications where maximum timing control is mandatory. All R6500 microprocessors are also available in a variety of packaging (ceramic and plastic), operating frequency (1 MHz and 2 MHz) and temperature (commercial, industrial and military) versions. MEMBERS OF THE R6500 MICROPROCESSOR (CPU) FAMILY • • Single +5V supply N channel, silicon gate, depletion load technology Eight bit parallel processing 56 InstrUctions Decimal and binary arithmetic Thirteen addressing modes True indexing capability Programmable stack pointer Variable length stack Interrupt capabil ity Non-maskable interrupt Use with any type of speed memory S-bit Bidirectional Data Bus Addressable memory range of up to 65K bytes "Ready" input Direct Memory Access capability Bus compatible with M6S00 1 MHz and 2 MHz operation Choice of external or on-chip clocks On·the-chip clock options External single clock input - RC time base input - Crystal time base input Commercial, industrial and military temperature versions Pi'peline architecture Ordering Information Order Number: R65XX __ _ Microprocessors with On-Chip Clock Oscillator Model R6502 R6503 R6504 R6505 R6506 R6507 Addressable Memory 65K 41< SK 4K 4K SK Bytes Bytes Bytes Bytes Bytes Bytes lTemperature Range: No suffix = OOC to +700 C E = -40 oC to +S50 C (I ndustriall MT = -550 C to +1250 C (Military) M = MIL.sTD~3, Class B Package: Microprocessors with External Two Phase Clock Output Model R6512 R6513 R6514 R6515 Addressable Memory 65K 4K SK 4K Bytes Bytes Bytes Bytes C = Ceramic; P = Pla~ (Not AVaible for M 'or MT suffix) Ff'8t/uency Range: No suffix = 1 MHz A = 2 MHz Model Designator: XX = 02,03,04, ... 15 NOTE: Contact your local Rockwell Representative concerning availability. SpeclflCiition. tubJect to @ Rockwell International Corporation 1979 All Rights Reserved Printed in U.S.A. change without notice R6600 Signal Description Clocks (41 1 , 41 2 ) Non-Maskable Interrupt (liI1l1l. The R651X requires a two phase non-overhipping clock that runs at the V CC voltage level. A negative going edge on this input requests that a non-rnaskable interrupt sequence be generated within the microprocessor. The R650X clocks are suPPlied with ali internal clock generator. The frequency of these clocks is externally controlled. IiiMi is an unconditional interrupt. Following completion of the current instruction, the sequence of operations defined for i'fiQ . will be performed, regardless of the state interrupt mask flag. The vector address loaded into the progrlilm counter, low and high, are locations fFFA and FFFB respectively, thereby transferring pro· gram·.control to the memory vector located at these addresses. The instructions loaded at these locetions cause the microproc· essor to branch to a non-rnaskable interrupt routine in memory. Add,.. BUI (AO...A15) These outputs are TTL compatible. capable of driving one standard TTL load and 130 pF. Data BUI (00·1)7) Eight pins are used for the data bus. This is a bidirectional bus. transferring data to and from the device end peripherals. The out· puts are trioState buffers capable of driving one standard TTL load and 130pF. Data BUI Enable (DBEt This TTL compatible input allows external control of the trioState data output buffers and will enable the microprocessor bus driver when in the high state. In normal operation DBE would be driven by the phase ~ (41 2 ) clock. thus allowing data output from microprocessor only during 41 • During the read cycle. the data bus drivers are internally disa~ed. becoming .essentially an. open circuit. To disable data bus drivers externally.DBE should be held low. Ready (ROY) This input signal allows the user to halt or single cycle the microprocessor on all cycles except write cycles. A negative transition •to the low state during or coincident with phase one (41,) will halt the microprocessor with the output address lines reflecting the current address being fetChed. If Ready is low during a write cycle, it is ignored until the foUowing read operation. This condition will remain through a subsequent phase two (412) in which the Ready signal is low. This feature allows microprocessor inter· facing with the low speed PROMs as well as fast (max. 2 cycle) Direct Memory Access (DMA). Interrupt Request IIRQ) This TTL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor will complete the current instruction being executed before recognizing the request. At that time, the interrupt mask bit in the Status Code Register will be examined. If the interrupt mask flag is not set, the microprocessor will begin an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The micro· processor will then set the interrupt mask flag high so that no fur· ther interrupts may occur. At the end of this cycle, the program counter low will be loaded from address FFFE, and program counter high from location FFFF. therefore transferring program control to the memory vector located at these addresses. The RDY signal must be in the high state for any interrupt to be rec· ognized. A 3KO external resistor should be used for proper wire-OR operation. NMI 'also requires an external 3K wire·OR operations. n regis.ter tc:> (, V CC for proper Inputs iRO and NMI are hardware interrupts,lines that are sam. pled during 412 (phase 2) and will begin the eppropriate interrupt routine on the 41, (phase ,) following the completion of the cur· rent instruction. Set 0vrrflow Flag (5.0.) A neg~tive going edge on this input sets the overflow bit in the Status Code Register. This Signal is sampled on the trailing edge of 411 and must be externally synchronized. SYNC This output line is provided to identify those cycles in which the microprocessor is doing an OPCODE fetch. The SYNC line goes high during 41, of an OP CODE fetch and stays high for the remainder of that cycle. If the RDY line is pulled low during the 41, clock pulse in which SYNC went high, the processor will stop in its current state and will remain. in the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause Single instruction execution. ( Reset This input is used to reset or start the microprocessor from a power down condition. During the time that this line is held low, writing to or from the microprocessor is inhibited. When a posi· tive edge is detected on the input. the microprocessor will imme· diately begin the reset sequence. After a system initialization time of six clock'cycles, the mask interrupt flag will be set and the microprocessor will load the pro· gram counter from the memory vector locations FFFC and FFFD. This is the start location for program control. After VCC reaches 4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the R/W and (SYNC) signal will become valid., When the reset signal goes high following these two clock cycles. the microprocessor will proceed with the normal reset procedure detailed above. ( ADDRESSING MODES ACCUMULATOR ADDRESSING - This fonn of addressing is represented with a one byte instruction, implying an operation on the accumulator. IMPLIED ADDRESSING - In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction. IMMEDIATE ADDRESSING - In immediate addressing, the operand is contained in the second byte of the inStruction, with no further memory addressing required. RELATIVE ADDRESSING - Relative addressing is used only with branch instructions and establishes a destination for the conditional branch. ABSOLUTE ADDRESSING - In absolute addressing, ~econd byte of the instruction specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 65K bytes of addressable memory. The second byte of the instruction becomes the operand which is an "Offset"added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is -128 to +127 bytes from tha next instruction. ZERO PAGE ADDRESSING - The zero page instructions allow for shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. Careful use of the zero page can result in significant increase in code efficiency. INDEXED ZERO PAGE ADDRESSING - (X, V indexing) - This form of addressing is used in conjunction with the index register and is referred to as "Zero Page, X" or "Zero Page, V". The effective address is calculated by adding the second byte to the contents of the index register. Since this is a fonn of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally due to the "Zero Page" addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur. INDEXED ABSOLUTE ADDRESSING - (X, V indexing) - This form of addressing is used in conjunction with X and V index register and is referred to as "Absolute, X", and "Absolute, V". The effective address is formed by adding the contents of X or V to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time. INDEXED INDIRECT ADDRESSING - In indexed indirect addressing (referred to as (Indirect, Xl), the second byte of the instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory location on page zero whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero. INDIRECT INDEXED ADDRESSING - In indirect .indexed addressing (referred to as (Indirect!, V), the second byte of the instruction points to a memory location in page zero. The contents of this memory location is added to the contents of the V index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents. of the next page zero memory location, the result being the high order eight bits of the effective address. ABSOLUTE INDIRECT - The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location is contained in tha third byte of the instruction. The contents of tha fully specified memory location is the low order byte of the effective address. The next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program counter. INSTRUCTION SET - ALPHABETIC SEQUENCE ADC Add Memory to Accumulator with Carry AND "AND" Memory with Accumulator ASl Shift left One Bit (Memory or Accumulator) BCC BCS BEQ BIT BMI BNE BPl BRK BVC BVS Branch on Carry Clear Branch on Carry Set Branch on Result Zero Test Bits in Memory with Accumulator Branch on Result Minus Branch on Result not Zero Branch on Result Plus Force Break Branch on Overflow Clear Branch on Overflow Set ClC ClD Cli ClV CMP CPX CPV Clear Carry Flag Clear Decimal Mode Clear Interrupt Disable Bit Clear Overflow Flag Compare Memory and Accumulator Compare Memory and Index X Compare Memory and Index V DEC Decrement Memory by One DEX Decrement Index X by One DEV Decrement Index V by One EOR "Exclusive-or" Memory with Accumulator INC INX INV Increment Memory by One Increment Index X by One Increment Index V by One JMP JSR Jump to New location Jump to New location Saving Return Address lOA lOX lDV lSR load Accumulator with Memory load Index X with Memory load Index V with Memory Shift One Bit Right (Memory or Accumulator! NOP No Operation ORA "OR" Memory with Accumulator PHA Push Accumulator on Stack PHP Push Processor Status on Stack PlA Pull Accumulator from Stack PlP Pull Processor Status from Stack ROL ROR RTI RTS Rotate One Bit Left (Memory or Accumulator) Rotate One Bit Right (Memory or Accumulator) Return from Interrupt Return from Subroutine SBC SEC SED SEI STA STX STY Subtract Memory from Accumulator with Borrow Set Carry Flag Set Decimal Mode Set Interrupt Disable Status Store Accumulator in Memory Store Index X in Memory Store Index V in Memory TAX TAV TSX TXA TXS TVA Transfer Accumulator to Index X Transfer Accumulator to Index V Transfer Stack Pointer to Index X Transfer Index X to Accumulator Transfer Index X to Stack Register Transfer Index V to Accumulator VSS ROYO O.4V j~-PW-H-.-:---:'-:'-:':'~+-~ OL Rm ----t=~:.I~---------..J/ ~f O.4V CREF O'4V~1 "A" 1.5V . L ADDRESS FROM CPU I--PWHI/I 2 - 1 , . +-__ DATAFROM __- i_ _ _ MEMORY REF "B" -r_~~ ROY, 5.0. SYNC Timing for Writing Data to Memory or Peripherals Clock Timing - R6512, 13, 14, 15 ,REF "A" ~l·~------TCYC------~~ Rm ( ADDRESS FROM CPU DATAFROM __~-------r--c~ CPU REF "B" Note: "REF," means Reference Points on clocks. PROGRAMMING MODEL o 7 ....1ACCUMULATOR A I'--______ o 7 15 1~_ _.y...;..._ _ _~IINDEX REGISTER o 7 ....1INDEX REGISTER X 1,--_______ o PCH__-=-~__~;.;;;... PCl __~I PROGRAM COUNTER ,--_~...;;.;.. I Y X 7 I 7 11 I 8 I NIVI IB lOll I ZIClpROCESSOR STATUS REG ~ "PC" CARRY ZERO "s" 1 = RESULT ZERO IRQ DISABLE 1 = DISABLE 1 =TRUE '-----DECiMAL MODE ' - - - - - - B R K COMMAND. L--------OVERFlOW L.--_ _ _ _ _ _ _ NEGATIVE 'P" 1 = TRUE o -'1 STACK POINTER 1...-'--_ _ _ S_ _ _ _ o 7 A 1= BRK 1 =TRUE 1 =NEG. ( +- - .-r--- AD ....- Al A2 .... A3 CONTROL SECTION ---t.~ REGISTER SECTION +t~ rINDEX REGISTER Y ~ INDEX REGISTER X ~ STACK POINT REGISTER IS) t? INTERRUPT LOGIC '-RDY ABL .- A4 ..J r- .... A5 ~~ ..J « z a: w INSTRUCTION DECODE I- Z .- A6 .... A7 -~ ~ ALU ~ ~ ADDRESS BUS .-r--- AB :I: 0 « ..J « z I+I+I+- ~ Ii. a: +- A9 ....-- ACCUMULATOR .-- w l- TIMING CONTROL ~ ·A1D +- All +- A12 A13 ' ... ... ~ PCL ~ ~ PCH ABH ~ INPUT DATA LATCH IDLI I+- A14 A15 '- - LEGEND: 11' : L-< '" ~ ..... - q,2 DATA BUS BUFFER H PROCESSOR STATUS REGISTER P I CLOCK GENERATOR ,I t Note: .m--2 -I m '"T1 l> nm l> C VSS PAO PAl PA2 PA3 PA4 PA5 PA6 PA7 PBO PBl PB2 PB3 PB4 PB5 PB6 PB7 CB1 CB2 VCC CAl CA2 RSO RSl RS2 RS3 REs DO Dl D2 D3 D4 D5 D6 D7 ¢2 CSl Cs2 R/W iRQ Pin Configuration ,=.-~~~,-~ .. =-"~.",-~~.,".,-."------------,,, CD Rockwell International Corporation 1978 < m :rJ Temperature Range +70 0 C +70 0 C +70 0 C +70 0 C +85 0 C +85 0 C +85 0 C N N -I Ordering Information Order Number :rJ 0) (J1 Specifications subject to change without notice l> "m-I --< l> :rJ - OPERATION SUMMARY Register Select Lines I RSO, RS1, RS2, RS31 The four Register select lines are nCfmally connected to the processor address bus lines to allow the processor to select the internal R6522 register which is to be accessed. The sixteen possible combinations access the registers as follows: RS1 L L L L ORB L L L H ORA L L H L DDRB L L H H DORA L H L L T1L-L T1C-L Write Latch Read Counter T1C-H Trigger T1 L·UT1 Col Transfer H L RSO Remarks RS2 RS3 L Register H RS3 RS2 RS1 RSO Register H L L L T2L-L T2C-L Write Latch Read Counter H L L H T2C-H Triggers T2L-L/T2C-L Transfer Controls Handshake L H H L T1L-L L H H H T1 L-H H L H H L H H ACR H H L L PCR H H L H IFR H H H L IER H H H H ORA ( Remarks SR No Effect on Handshake Note: L = O.4V DC, H = 2.4V DC. Timer 2 Control R/W= L RS3 RS2 RS1 RSO H L L L Write T2L-L Read T2C-L Clear I nterrupt flag H L L H Write T2C-H Transfer T2L-L to T2C-L Clear I nterrupt flag Read T2C-H R/W=H ( Writing the Timer 1 Register The operations which take place when writing to each of the four T1 addresses are as follows: RS3 RS2 RS1 RSO Operation IR/W = LI L H L L Write into low order latch L H L H Write into high order latch Write into high order counter Transfer low order latch into low order counter Reset T1 interrupt flag L H H l Write low order latch X H H H Write high order latch Reset T1 interrupt flag Reading the Timer 1 Registers For reading the Timer 1 registers, the four addresses relate directly to the four registers as follows: RS3 RS2 RS1 RSO Operation IR/W = HI l H L l Read T1 low order counter Reset T1 interrupt flag L H l H Read T1 high order counter L H H l Read T1 low order latch L H H H Read T1 high order latch ( TIMING CHARACTERISTICS Read Timing Characteristics (loading 130 pF and one TTL load) Parameter Symbol Min Delay time, address valid to clock positive transition T ACR 180 Delay time, clock positive transition to data valid on bus TCDR - Peripheral data setup time TpCR Data bus hold time THR Rise and fall time for clock input T RC Typ 300 10 - Max Unit - - nS - 395 nS - - - - - 25 nS , nS nS TRF PHASE TWO CLOCK Jr-t---t---t---=:..::..-------- 2.4V ADDRESS -----,-:! . , , - - - - + - - t - - + - - - - - - - - - - - O . 4 V PERIPHERAL DATA Jr-..:..;::=---.:.--t--+----------2.4V T 1.-_ _,,1_ - _H.!I_ - - - - - - O.4V -2.4V DATA BUS r--"""';1f-- -- - - --O.4V Read Timing Characteristics Write Timing Characteristics Parameter Symbol Min Enable pulse width TC 0.47 - 25 liS Delay time, address valid to clock positive transition T ACW 180 - - nS Delay time, data valid to clock negative transition T DCW 300 - - nS Delay time, read/write negative transition to clock positive transition TWCW 180 - - nS Data bus hold time T HW 10 - - nS Delay time, Enable negative transition to peripheral data valid TCpW - - 1.0 J.l.S T CMOS - Delay time, clock negative transition to peripheral data valid CMOS (VCC - 30%) Typ Unit 1 - PHASE TWO CLOCK ,.--------2.4V ADDRESS --::;:o-J Max ~==::r---1::::"'..4:r,:;;~----O.4V rt-......::C::.:M~O::.:S'--_ _ _ _ 2.4V T DCW -1----1 READ/WRITE -O.4V DATA BUS - - - - - - - - - O.4V - - - - - - - - - VCC ...Jro-------2.4V PERIPHERAL DATA Write Timing Characteristics 2.0 liS I/O Timing Characteristics Characteristic Symbol Min Typ Max Unit Rise and fall time for CA 1, CB 1, CA2 and CB2 input signals TRF - - 1.0 j.ts Delay time, clock negative transition to CA2 negative transition (read handshake or pulse mode) TCA2 - - 1.0 j.ts Delay time, clock negative transition to CA2 positive transition (pulse mode) T RS1 - - 1.0 j.ts Delay time, CA 1 active transition to CA2 positive transition (handshake mode) T RS2 - - 2.0 j.ts Delay time, clock positive transition to CA2 or CB2 negative transition (write handshake) T WHS - - 1.0 j.tS Delay time, peripheral data val id to CB2 negative transition T DC 0 - 1.5 j.ts Delay time, clock positive transition to CA2 or CB2 positive transition (pulse mode) T RS3 - - 1.0 j.tS Delay time, CB1 active transition to CA2 or CB2 positive transition (handshake mode) T RS4 - - 2.0 j.ts Delay time, peripheral data valid to CA 1 or CB 1 active transition (input latching) TIL 300 - - ns Delay time CB1 negative transition to CB2 data valid (internal SR clock, shift out) TSR1 - - 300 ns Delay time, ne9ative transition of CB1 input clock to CB2 data valid (external clock, shift out) TSR2 - - 300 ns Delay time,CB2 data valid to positive transition of CB1 clock (shift in, internal or external clock) T SR3 - - 300 ns Pulse Width - PB6 Input Pulse T IPW 2 - - j.ts Pulse Width - CB 1 In'put Clock T ICW 2 - - j.ts liPS 2 - - j.ts IICS 2 - - j.tS . \ Pulse Spacing - PB6 I nput Pulse Pulse Spacing - CB1 Input Pulse PB6 INPUT PULSE COUNTING MODE C T 1PW =:\{"'"_-_-_-_-_-_-_:::: ~ r---2.4V CB2 SERIAL DATA IN T ICW CB1CLOCK ( \ O.4V ~TS R3 V-- -- ~ TSR1 2.4V O.4V TSR2 CB2 SERIAL DATA OUT ~ I/O Timing Characteristics 2.4V O.4V ( Timer 1 Operating Modes Two bits are provided in the Auxiliary Control Register to allow selection of the Tl operating modes. These bits and the four possible modes are as follows: ACR7 Output Enable ACR6 "Free-Run" Enable 0 0 Generate a single time·out interrupt each time Tl is loaded 0 1 Generate) continuous interrupts 1 0 Generate a single interrupt and an output pulse on PB7 for each Tl load operation 1 1 Generate continuous interrupts and a square wave output on PB7 Mode FUNCTION CONTROL Control of the various functions and operating modes within the R6522 is accomplished primarily through two registers, the Peripheral Con· trol Register (PCR), and the Auxiliary Control Register (ACR). The PCR is used primarily to select the operating mode for the four peripheral control pins. The Auxiliary Control Hegister selects the operating mode for the Interval Timers (Tl, T2), and the Serial Port (SRI. Peripheral Control Register The Peripheral Control Register is organized as follows: Bit # I 7 I 6 CB2 Control Function 5 4 CBl Control 3 I 2 I CA2 Control 1 0 CAl Control Typical functions are shown below: PCR3 PCR2 PCR1 Mode 0 0 0 Input mode - Set CA2 interrupt flag (IFRO) on a negative transition of the input signal. Clear I FRO on a read or write of the Peripheral A Output Register. 0 0 1 Independent interrupt input mode - Set IFRO on a negative transition of the CA2 input sig· nal. Reading or writing ORA does not clear the CA2 interrupt flag. 0 1 0 Input mode - Set CA2 interrupt flag on a positive transition of the CA2 input signal. Clear I FRO with a read or write of the Peripheral A Output Register. 0 1 1 I ndependent interrupt input mode - Set I FRO on a positive transition of the CA2 input signal. Reading or writing ORA does not clear the CA2 interrupt flag. 1 0 0 Handshake output mode - Set CA2 output low on a read or write of the Peripheral A Output Register. Reset CA2 high with an active transition on CAl. 1 0 1 Pulse output mode - CA2 goes low for one cycle following a read or write of the Peripheral A Output Register. 1 1 0 Manual output mode - The CA2 output is held low in this mode. 1 1 1 Manual output mode - The CA2 output is held high in this mode. , Auxiliary Control Register Many of the functions in the Auxiliary Control Register have been discussed previously. However, a summary of this register is presented here as a convenient reference for the R6522 user. The Auxiliary Control Register is organized as'follows: Bit fI 7 Function I 6 Tl Control 4 5 T2 Control I 3 I 2 Shift Register Control 1 0 PB latch Enable PA latch Enable ( Shift Register Control The Shift Register operating mode is selected as follows: ACR4 ACR3 ACR2 Mode 0 0 0 Shift Register Disabled. 0 0 1 Shift in under control of Timer 2 . 0 1 0 Shift in under control of system clock. 0 1 1 Shift in'under control of external clock pulses. 1 0 0 Free-running output at rate determined by Timer 2. 1 0 1 Shift out under control of Timer 2. 1 1 0 Shift out under control of the system clock .. 1 1 1 Shift out under control of external clock pulses. ( T2 Control Timer 2 operates In two modes. If ACR5 = 0, T2 acts as an interval timer in the one-shot mode. If ACR5 = 1, Timer 2 acts to count a pre: determined number of pulses on pin PB6, ( ROCKWEll INTERNATIONAL-MICROelECTRONIC DEVICES ~~~Y~O~U~R~L~O~C~A~L~R~EP~R~E~S~E~N~T~A~T~IV7.E~----' REGIONAL SALES OFFICES HOME OFFICE' Rockwell International Corp. Microelectronic Devices P.O. Box 3669 Anaheim, Ca. 92803 U.S.A. Phone: (,114) 632-0950 1WX: 910-591-1698 , Also Applications Centers CENTRAL REGION, U.S.A. Contact Robert 0 Whitesell & Associates 6691 East Washington Street Indianapolis. Indiana 46219 (317) 359-9283 Attn. Milt Gamble. Mgr. EASTERN REGION, U.S.A.' Carolier Office Building 850-870 U.S. Route 1 North BrunswiCk, New Jersey 08902 Phone: (201) 246-3630 EUROPE Rockwell International GmbH Microelectronic Devices Fraunhoferstrasse 11 0-8033 Munchen-Martinsried Germany Phone: (089) 859-9575 Tp.IA~: 0521/2650 MIDWEST REGION, U.S.A. 1011 E. Touhy Avenue, Suite 245 Des Plaines, IL 60018 . Phone: (312) 297-8RI WESTERN REGION, U.S.A. 3310 Miraloma Avenue P.O. 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Ichiban-cho Central Building 22-1 Ichiban-cho, Chiyoda-ku Toyko 102, Japan Phone: 265-8808 Telex: J22198 808 ( ( PART NUMBER A6545-1 '1' .R6500 Microcomputer System Rockwell DATA SHEET CRT CONTROLLER (CRTC) DESCRIPTION FEATURES The R6545-1 CRT Controller (CRTC) is designed to interface an 8-bit microprocessor to CRT raster scan video displays, and adds an advanced CRT controller to the established and expanding line of R6500 products. • Compatible with 8-blt microprocessors • Up to 2.5 MHz character clock operation • Refresh RAM may be configured in row/column or straight binary addressing • Alphanumeric and limited graphics capability • Up and down scrolling by page, line, or character • Programmable Vertical Sync Width • Fully programmable display (rows, columns, character matrix) The R6545-1 provides refresh memory addresses and character generator row addresses which allow up to 16K char_ acters with 32 scan lines per character to be addressed. A major advantage of the R6545-1 is that the refresh memory may be addressed in either straight binary or by row/column. Other functions in the R6545-1 include an intemal cursor regIster which generates a cursor output when its contents are equal to the current refresh address. Programmable cursor start and end registers allow a cursor of up to the full character scan in height to be placed on any scan lines of the character. Variable cursor display blink rates are provided. A light pen strobe input allows capture of the current refresh address in an internal light pen register. The refresh address lines are configured to provide direct dynamic memory refresh. All timing for the video refresh memory signals is derived from the character clock input. Shift register, latch, and multiplex control Signals (when needed) are provided by external high-speed timing. The mode control register allows noninterlaced video display modes at 50 or 60 Hz refresh rate. The internal status register may be used to monitor the R6545-1 operation. The RES input allows the CRTC-generated fi~d rate to be dynamically-synchronized with line frequency jitter. ORDERING INFORMATION Part Number R6545-1P R6545-1AP R6545-1C R6545-1AC Package Type Plastic Plastic Ce.ramic Ceramic o RockwelllntamaIIonaI Corporation 1980 All Rights RaHrved PrInted In U.S.A. Frequency 1 MHz 2 MHz 1 MHz 2 MHz Temperature Range O°C to O°C to O°C to O°C to +70°C +700C +70°C +70°C • N9n-interlaced scan • 50/60 Hz operation • Fully programmable cursor • • • • • • • Light pen register Addresses refresh RAM to 16K characters No external DMA required Internal status register 4Q-Pin ceramic or plastic DIP Pin-compatible with MC6845 Single +5 ±5% Volt Power Supply VSS m LPEN CCO/MAO CC1/MA1 CC2/MA2 CC3/MA3 CC4IMA4 CC5/MA5 CC8/MA8 CC7/MA7 CRO/MAS CR1/MA9 CR2/MA10 CR3/MA11 CR4IMA12 CREI/MA13 DISPLAY ENABLE CURSOR VCC VSYNC HSYNC RAO RA1 RA2 'RA3 RA4, 00 01 02 03 04 DEI 08 07 Ci RS ,2 Rlii CCLK R6545-1 Pin Configuration SpecltlcaIIona subject to change without notice Document No. 21000 DI7 Decemblr1_ INTERFACE SIGNAL DESCRIPTION CPU INTERFACE !62 (Phase 2 Clock) The input clock is the system Phase 2 (_2) clock and is used to trigger all data transfers between the system processor (CPU) and the R6545-1. Since there is no maximum limit to the allowable clock time, it is not· necessary for it to be a continuous clock. This capability permits the R6545-1 to be easily interfaced to non-6500 compatible microprocessors. _2 R/W (Read/Write) The R/W input signal generated by the processor is useri to control the direction. of data transfers. A high on the R/W pin allows the processor to read the data supplied by the R6545-1, a low on the R/W pin allows data on data lines 00-07 to be written into the R6545-1. CI (Chip Select) The Chip Select input is normally connected to the processor address bus either directly or through a decoder. The R6545-1 is selected when CS is low. CURSOR (Cursor Coincidence) The CURSOR signal is an active-high output used to indicate ( when the scan coincides with the programmed cursor position. The cursor position may be programmect to be any character in the address field. Furthermore, within the character, the·oursor may be programmed to be any block of scan lines, since the start scan line and the end scan line are both programmable. The cursor position may be delayed by one character time by setting Bit 5 of RS to A "1". LPEN (Light Pen Strobe) The LPEN signal is an· edge-sensitive input used to load the internal Light Pen Register with the contents of the Refresh . Scan Counter at the time the active edge. occurs. The active edge of LPEN is the low-to-high transition. CCLK (Clock) The CCLK signal is the character timing clock input and is used as the time base for all internal count/control functions. FmI The Register Select input is used to access intemal registers. A low on this pin permits writes (R/W = low) into the Address Register and reads (R/W = high) from the Status Register. The contents of the Address Register is the identity of the register accessed when RS is high. The R'ESsignal is an active-low input used to initialize all internal scan counter circuits. When ~ is low, all intemal counters are stopped and cleared, all scan and video outputs must stay are low, and control registers are unaffected. low for at least one CCLK period. All scan timing is initiated can be used to synwhen RES goes high. In this way, chronize display frame timing with line frequency. RES may also be used to synchronize multiple CRTC's in horizontal· and/or ( . vertical split screen operation. 00-07 (Data Bus) REFRESH RAM AND CHARACTER ROM INTERFACE 00-07 are the eight data lines used to transfer data between the processor and the R6545-1. These lines are bidirectional and are normally high-impedance except during read cycles when the chip is selected (~ = low). MAo-MA13 (Refresh RAM Address Lines) RS (Register Select) VIDEO INTERFACE HSYNC (Horizontal Sync) The HSYNC signal is an active-high output used to determine the· horizontal position of displayed text. It may drive a CRT monitor directly or may be used for composite video generation. HSYNC time position and width are fully programmable. VSYNC (Vertical Sync) The VSYNC signal is an active high output used to determine the vertical position of displayed text. Like HSYNC, VSYNC may be used to drive a CRT monitor or composite video generation circuits. VSYNC time position and width are both programmable. QISPLAYENABLE (Display Enable) The OISPLAY ENABLE signal is an active-high output used to indicate when the R6545-1 is generating active display information. The number of horizontal display characters per row and the number of vertical display rows are both fully programmable and together are used to generate the OISPLAY ENABLE signal. DISPLAY ENABLE can be delayed one character time by setting bit 4 of RB equal to 1. m m These 14 signals are active-high outputs used to address the Refresh RAM for character storage and display operations. The starting scan address is fully programmable and the ending scan address is determined by the total number of characters displayed, which is also programmable, in terms of characters/ line and lines/frame. There are two selectable address modes for MAO~MA 13: In the straight binary. mode (RB, Mode Control, bit 2 = "0"), characters are stored in successive memory locations. Thus, the software must be designed such that row and column character coordinates are translated into sequentially-numbered addresses. In the row/column mode (RB, Mode Control, bit 2 = "1 "), MAO-MA7 become column addresses CCO-CC7 and MASMA13 become row addresses CRO-CR5. In this case, the software can manipulate characters in terms of row and column locations, but additional address compression circuits are needed to convert the CCO-CC7 and CRO-CR5 addresses into a memory-efficient binary address scheme. RAo-RA4 (Raster Address Lines) These 5 signals are active-high outputs used to select each ras- ( ter scan within an individual character row. The number of raster scan lines is programmable and determines the character height, including spaces between character rows. J INTERNAL REGISTER ORGANIZATION Addr_ Register CS RS 4 3 2 1 0 Reg. No. 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 X X X X X X X X X X X X X X· X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RO Rl R2 R3 R4 R5 A6 R1 RS R9 R10 Rll R12 R13 R14 R15 R16 R17 Register Name Address Register Status Register Horizontal Total Char Horizontal Displayed Char Horizontal Sync Position YSYNC, HSYNC Widths Vertical Total Rows Vertical Total Adjust Lines Vert.ical Displayed Rows Vertical Sync Position Mode Control Scan Line Cursor Start Line Cursor End Line Display Start Address (HI Display Start Address (L1 Cursor Position Address (HI Cursor Position Address (L1 Light Pen Register IHI Light Pen Register (LI Read IR/WHighl Register Units Register No. Write IR/WLowl V V V - V 4 3 6 5V V 7 6 5 4 3 7 6 5 4 3 7 6 5 4 3 7 6 5 4 3 /' 6 5 4 3 / ' / ' ./ 4 3 V 6 5 4 3 V 6 5 4 3 7 6 5 4 3 / ' V ./ 4 3 V 8 5 4 3 / ' V ./ 4 3 /' V 5 4 3 7 6 5 4 3 ./'V 5 4 3 7 6 5 4 3 ./' V 5 4 3 7 6 5 4 3 V V V V V V V V V V V No. of Scan Lines Scan Line No. Scan Line No. - - V - V V V V - 6 5 4 3 2 1 0 V / V V No. of Characters/Row No. of Characters/Row Character Position No. of Scan Lines, Characters No. of Character Rows No. of Scan Lines No. of Character Rows No. of Character Rows 7 1/ I V V V / / V _.. Register Bit V 2 1 0 / ' ./ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 1. Overall Register Structure and Addressing GND CPU IIF STATUS REGISTER (SR) VIDEO IIF ~D7~~~~--------~--"HSYNC cb2---4~ R/W ---II" cs---II" RS - This 8-bit register contains the status of the CATC. Only two bits are assigned, as follows: ..........~VSYNC DISPLAY ENABLE . CURSOR LPEN CCLK RES 1.,..r----.,.,J ...... '----__..v___- - . J ' - - - - N O T USED L.I MAO-MA13 RAO·RA4 REFRESH RAM AND CHARACTER ROM Vertical R. Tree (VRT) o • Scan Is not currently in its vertical . .t..- time. 1 - Scan il currently in its vertiCil .... time. Not. the! this bit octulily g_ to I HI H when verti..1 re-trece stlrts, but goes to • "0" five char.etar clock tim.. before vertiCal ... In., 10 that critical timings for refresh RAM _rations Ire lvoided. t,_ R6545·1 Interface Diagram ·t..... ' - - - - - LPEN Register Full (LRF) o - Register R16 Dr R17 h. bUn reod by the CPU. INTERNAL REGISTER DESCRIPTION ADDRESS REGISTER This 5-bit write-only register is used as a "pointer" to direct CATC/CPU data transfers within the CATC. Its contents is the number of the desired register (0-17). When CS and AS are low, then this register may be loaded; when CS is low and AS is high, then the register selected is the one whose identity is . stored in this address register. 1 - LPEN strobe h.. bUn .....ived. ' - - - - - - Not Used NOTE: The Statu. Register tak.. the State, I-I 0 l' 1-1-1-1-1-1 immediately after pOWer (V CCI turn..,n. Ro-HORIZONTAL TOTAL CHARACTERS R7-VERnCAL SYNC POSmON This 8-blt write-only register contains the total of displayed and non-displayed characters, minus one, per horizontal line. The frequency of HSYNC Is thus determined by this register. This 7-bit write-only register is used to select the character row time at which the vertical SYNC pulse is desired to occur and, thus, is used to position the displayed text in the vertical direction. R1-HORIZONTAL DISPLAYED CHARACTERS "RI-MODE CONTROL (MC) This 8-bit write-only register contains the number of displayed characters per horizontal line. This 8-bit write-only register selects the operating modes of the R6545-1 , as follows: R2-HORIZONTALSYNC POSITION 78543210 MC7 MC8 This 8-bit write-only register contains the position of the horizontal SYNC on the horizontal line, In terms of the character location number on the line. The position of the HSYNC determines the left to right location of the displayed text on the video screen. In this way, the side margins are adjusted. (- - - MC& MC4 CSK DES MC3 MC2 MC. MC& 0 "AD _ 0 L:= R3-HORIZONTAL AND VERTICAL SYNC WIDTHS .. This B-bit write-only register contains the widths of both HSYNC and VSYNC, as follows: M.... Program to "0" NoIUoed '---R".'_RAM Add .....ing Mode fRADI o• L...--- Mult , f or streight binary or Row/Column Protr.mtDUO'" D ...... E...ble Skew IDESt for no ....ay. o• • • to ct.1.., DilpllV EMbie OM ch.rlcter .tIme• CUrsor Sk. w (CSKI 0- for no delay. , .. to ctet.v CursoI' on. ehllrNtH' tim•. HSYNC Pulse Width }~ The width of the horizontal sync pulse IHSYNC) in the number of character clock times ICCLK). ' - - - - - - - - - VSYNC Pulse Width The width of the vertical sync pulse IVSYNC) in the number of scan lines. When bits 4·7 are all "0", VSYNC will be 16 scan lines wide. Control of thes~ parameters allows the R6545-1 to be interfaced to a variety of CRT monitors, since the HSYNC and VSYNC timing signals may be accommodated without the use of external one shot timing. R4-VERTICAL TOTAL ROWS The Vertical Total Register is a 7-bit register containing the total number of character rows in a frame, minus one. This register, along with R5, determines the overall frame rate, which should be close to the line frequency to ensure flicker-free appearance. If the frame time is adjusted to be longer than the period of the line frequency, then RES may be used to provide absolute synchronism. RS-VERTICAL TOTAL LINE ADJUST The Vertical Total Line Adjust Register (R5) is a 5-bit write-only register containing the number of additional scan lines needed to complete an entire frame scan and is intended as a fine adjustment for the video frame time. R6-VERTICAL DISPLAYED ROWS This 7-bit write-only register contains the number of displayed character rows in each frame: R9-ROW SCAN LINES " This 5-bit write~only register contains the number of scan lines, minus one, per character row, including spacing. R10-CURSOR START LINE R11-CURSOR END LINE These 5-bit" write-only registers selept the starting and ending scan lines for the cursor. In addition, bits 5 and 6 of R10 are used to select the cursor blink mode, as follows: Bit Bit ~ ...L Cursor Blink Mode o o Display Cursor Continuously Blank Cursor Continuously Blink Cursor at 1/16 Field Rate Blink Cursor at 1/32 Field Rate o 1 1 o 1 R12-DISPLAY START ADDRESS HIGH R13-DISPLAY START ADDRESS LOW These registers form a 14-bit register whose contents is the memory address of the first character of the displayed scan (the character on the top left of the video display, as in Figure 1). Subsequent memory addresses are generated by the R6545-1 as a result of CCLK input pulses, Scrolling of the display is accomplished by changing R12 and R13 to the memory address associated with the first character of the desired line of text to be displayed first. Entire pages of text may be scrolled or changed as well via R12 and R13. ( . ~~ NUMBER OF HORIZONTAL TOTAL CHARACTERS CROI ____________________ ____________________ -JA~ ~, NUMBER OF HORIZONTAL DISPLAVED CHARACTERS CRt! r~--------------~A~------------~, Lg::~~ START ADDRESS HIGH CR121* START ADDRESS LOW CR13I* ~ l SCAN NUMBER 0 F LIN ES CRtl ~ ~CURSO," START LINE CR1'1 I"""CURSOR END LINE CR111 1\ NUMBER OF VERTICAL TOTAL ROWS CR41 NUMBER OF VERTICAL' OISPLAV ROWS CRill • \""D..nD POSITION AODRESS HIGH CR141 CURSOR POSITION ADDRESS LOW CR1111 HORIZONTAL RETRACE PERIOD CNON.oISPLA VI . DISPLAV PERIOD VERTICAL RETRACE PERIOO CNON.oISPLAVI VERTICAl. TOTAL { ADJUST CRSI Figure 1. Video Display Format R14-CURSOR POsmolt.i HIGH R15-CURSOR PosmON LOW DESCRIPTION OF·OPERATION These registers form a 14-bit register whose contents is the memory address of the current cursor position. When the video display scan counter (MA lines) matches the contents of this register, and when the scan line counter (RA lines) falls within the bounds set by R10 and R11, then the CURSOR output becomes active. Bit 5 of the Mode Control Register (RS) may be used to delay the CURSOR output by a full CCLK time to accommodate slow access memories. VIDEO DISPLAY R16-LlGHT PEN HIGH R17..;..LlGHT PEN LOW These registers form a 14-bit register whose contents is the light pen strobe position, in terms of the video display address at which the strobe occurred. When the LPEN input changes from low to high, then, on the next negative-going edge of CCLK, the contents of the internal scan counter is stored in registers R16 and R17. REGISTER FORMATS Register pairs R12/R13, R14/R15, and R16/R17 are formatted in one of two ways: (1) Straight binary, if register RS, bit 2 = "0". (2) Row/Column, if register RS, bit 2 = "1". In this case the· low byte is the Character Column and the high byte is the Character Row. Figure 1 indicates the relationship of the various pr09ram registers in the R6545-1 and the resultant video display. Non-displayed areas of the Video Display are used for horizontal and vertical retrace functions of the CRT monitor. The horizontal and vertical sync signals, HSYNC and VSYNC, are programmed to occur during these intervals and are used to trigger the retrace in the CRT monitor. The pulse widths are eonstrained by the monitor requirements. The time position of the pulses may be adjusted to vary the display margins (left, right, top, and bottom) .. REFRESH RAM ADDRESSINO Shared Memory Mode (RB, bit 3 = "0") In this mode, the Refresh RAM address lines (MAO-MA13) directly reflect the Contents of the internal refresh scan character counter. Multiplex control, to permit addressing and selection of the RAM by both the CPU and the CRTC, must be provided external to the CRTC. In the Row/Column address mode, lines MAO-MA7 become character column addresses (CCO-CC7) and MAS-MA13 become character row addresses (CRO-CR5). ADDRESSING MODES Bits 5 and 6 in the Cursor Start Line High Register (R10) control the cursor display and blink rate as follows: (- Row/Column In this mode, the CRTC address lines (MAO-MA 13) are ganeratadas 8 column (MAo-MA7) and 6 row (MAS-MA 13) addresses. Extra hardware is needed to compress this addressing into a straight binary sequence in order to conserve memory in the refresh RAM. BitS Bit 5 Cursor C)ptInting Mode 0 0 0 1 0 Display Cursor Continuously. Blank Cursor Continuously Blink Cursor at 1/16 Field Rate Blink Cursor at"1/32 Field Rate 1 1 1 Binary In this mode, the CRTC address lines are straight binary and no compression circuits are needed. However, software complexity is increased since the CRT characters cannot be stored in terms of their row and column locations, but must be sequential. USE OF DYNAMIC RAM FOR REFRESH MEMORY The R6545-1 permits the use of dynamic RAMS as storage devices for the Refresh RAM by continuing to increment memory addresses in the non-display intervals of the scan. This is a viable technique, since the Display Enable Signal controls the actual video display blanking. Figure 2 illustrates Refresh RAM addressing for the case of binary addressing for 80 columns and 24 rows with 10 non-displayed columns and 10 non-displayed rows. . DISPLAY·80 0 1 2 3 76 83 156 71 78 The cursor is positioned on the screen by loading the Cursor Position Addtess High (R14) and Cursor Position Address Low (R15) registers with the desired refresh RAM address. The cursor can be positioned in any of the 16K character positions. Hardware paging and data scrolling is thus allowed without loss of cursor position. Figure 3 is an example of the display cursor scan line. UNDERLINE CURSOR o 79 80 81 161 89 80 81 82 157 158 159 160 160 161 162 237 2.38 239 240 249 169 240 241 242 317 318 319 320 329 1680 1681 1682 1757 1758 175.9 1760 1769 1760 1761 1762 1837 1838 1839 1840 1849 1840 1841 1842 1917 1918 1919 1920 1929 1920 1921 1922 1997 1998 1999 2000 2009 2000 2001 2002 2077 2078 2079 2080 2089 2640 2641 2642 2717 2718 2720 2729 OVERLINE CURSOR O~~++~- 2 3 4 3 4 3 4 5 6 56 8 9 10 11 8 9 10 11 1 7 BOX CURSOR 0 2 1 TOTAL-go , The cursor of up to 32 characters in height can be displayed on and between the scan lines as loaded into the Cursor Start Line (R10) and Cursor End Line (R11) Registers. 7 1~""~~ 23ElI!~~ 5~~:t~ 6~ 73EliliaaE 8 9 10~~++-H- 11-++++t-t-if-- CURSOR START LINE = 9 CURSOR START LINE = 1 CURSOR START LINE = 1 CURSOR END LlNE=9 CURSOR END LINE = 1 CURSOR END LINE =9 Figure 3. ( Cursor Display Scan Line Control Examples Figura 2. Memory Addressing Example (80 x 24) CURSOR OPERATION A one character wide cursor can be controlled by storing values into the Cursor Start Line (R10) and Cursor End Une (R11) registers and into the Cursor Position Address High (R14) and Cursor Position .Low (R15) registers. ( MPU WRITE TIMING CHARACTERISTICS (V cc '" 5.0V ±5%. T A = 0 to 70 o C. unless otherwise noted) 1 MHz Symbol 2MHz Min Max TCYC 1.0 TC T ACW 440 Address Hold Time TCAH 0 - RtW Set-Up Time Riiii Hold Time TWCW 180 Data Bus Set-Up Time TCWH T DCW 0 Data Bus Hold Time T HW · ClwlCteriitic Cycle Time 02 Pulse Width Address Set-Up Time 180 Min Max 0.5 - In 200 - ns 90 - ns 0 ns - 90 - 0 - ns 265 - 100 - ns 10 - 10 - ns (tr and t f • 10 to 30 111) WRITE CYCLE ~----------TCYC------------~ 2.0V 2.0V O.BV ...----_I-TACW r-------J .,..,..,..,~ 2.0V Ci, RS O.BV ____ ...----....-TWCW O.BV TOCW DO-07 Unit THW ns ( MPU READ TIMING CHARACTERISTICS (V cc = 5.0V ±5%. T A = 0 to 70 0 C. unless otherwise noted), 1 MHz 2 MHz Symbol Min Max Cycle Time TCYC 1.0 02 Pulse Width TC Address Set-Up Time T ACR Address Hold Time Characteristic Min Max Unit - 0.5 440 - 200 ns 180 - 90 - - ",5 ns TCAR 0 - 0 ~ ns RtWSet-Up Time TWCR 180 - 90 - ns Read Access Time TCDR - 340 - 150 ns Read Hold Time THR 10 - 10 - ns Data Bus Active'Time (Invalid Data) TCDA 40 - 40 - ns Itr and tf = 10 to 30 ns) - - - , - .. --~-------~-. MEMORY AND VIDEO INTERFACE CHARACTERISTICS (V cc '" 5.0V ±.5%, T A" 0 to 70 De. unless otherwise noted) 1 MHz Min Mo. Min Mo. Units TCCY 0.' 40 0.' 40 .s TCCH 200 - 200 - ns MAO·MA 13 Propagation Delay TMAD - 300 - 300 ns RAO-RA4 Propagation Delav TRAD - 300 - 300 ns DISPLAY ENABLE Prop. Delay - 450 - 450 ns HVSNC Propagation Delay TDTD T HSD 450 450 ns VSYNC Propagation TVSD - 450 450 ns Cursor Propagation Delay T CDO - 450 - 450 ns LPEN Strobe Width T LPH ISO - ISO ns LPEN to CCLK Delay T LPI 20 - 20 - CCLK to. LPEN Delay T LP2 0 - 0 - ns Symbol Characterittics fr. 2MHz Char.. Clock CVcle Time Char. Clock Pulse Width ns tf ., 20 ns (max) SYSTEM TIMING DEFINITIONS ~------------TCCY--------------~ 2.0V \"---- CCLK SIGNAL- ISee Belowl * SIGNAL SIGNAL SYMBOL IX) MAO·MA13 TMAD RAO·RA4 TRAD DISPLAY ENABLE TDTD HSYNC T HSD VSYNC TVSD CURSOR TCDD LIGHT PEN STROBE TIMING DEFINITIONS CCLK O.BV 1------' LPEN SEE NOTE MAO.MA13 _ _ _ _ _ ~~\.. _ _ _n_+l_ _ _ NOTE: SLASH AREA DEFINES THE "WINDOW" IN WHICH AN LPEN POSITIVE EDGE WILL CAUSE ADDRESS N+2 TO LOAD INTO LIGHT PEN REGISTER. TRANSITIONS ON EITHER SIDE OF THIS "WINDOW" WILL RESULT IN UNPREDICTABLE VALUES BEING LOADED INTO THE LIGHT PEN REGISTER. ___l~\.. ______ n+_2_ _ _ _ _ _[ SPECIFICATIONS ( Maximum Ratings Symbol Rating Supply Voltage VCC V IN Input Voltage Operating Temperature Range TOp T STG Storage Temperature Value Unit -0.3 to +7.0 Vdc -0.3 to +7.0 Vdc o to +70 °c °c ·55 to 150 All inputs contain protection circuitry to prevent damage due to high static discharges., Care should be taken to prevent unnecessary application of voltages in excess of the allowable limits. Electrical Characteristics (V CC = 5.0V ±5%, T A = 0·70 o C, unless otherwise noted) Symbol Characteristic Min Max Unit\ Input High Voltage V IH 2.0 Input Low Voltage V IL 0.3 VCC 0.8 Input Leakage (02, RfiiJ, RES,~, RS, LPEN, CCLK) liN - 2.5 "Adc ITSI - 10.0 "Adc VOH 2.4 - Vdc Vdc Vdc Three-State Input Leakage (00-07) (V IN = 0.4 to 2.4V) Output High Voltage I LOAO = 205 "Adc (00-07) ( I LOAO = 100 "Adc (all others) Output Low Voltage I LOAO = 1.6 mAdc Power Oissipation VOL - 0.4 Vdc Po - 1000 mW - 10.0 pF 12.5 pF 10.0 pF Input Capacitance 02,RAN,RES,CS,RS, LPEN,CCLK C IN 00-07 Output Capacitance COUT .. TEST LOAD 2.4Kfl R854S-1 PIN 130pF I R ( R=11KO FOR 00-07 =24KO FOR ALL OTHER OUTPUTS PART NUMBER R6551 R6500 Microcomputer System DATA SHEET Asynchronous Communication Interface Adapter (ACIA) The R6551 Asynchronous Communication Interface Adapter (ACIA) provides a program-controlled interface between 8-bit microprocessor-based systems and serial communication data sets and modems. With its on-chip baud rate generator, the R6551 is capable of transmitting at 15 different program-selectable rates between 50 baud and 19,200 baud, and receiving at either the transmit rate or at 16 times an external clock rate. The R6551 has programmable word lengths of 5, 6, 7, or 8 bits; even, odd or no FEATURES • • • Compatible with 8-bit microprocessors Full duplex or half duplex operation with buffered receiver and transmitter 15 programmable Baud Rates (50 to 19,200) Receiver data rate may be identical to baud rate or may be 16 times the external clock input Data set/modem control functions Programmable word lengths, number of stop bits, and parity bit generation and detection Programmable interrupt control • • • • • • • Software reset Program-selectable serial echo mode Two chip selects 2 MHz or 1 MHz clock rate Single +5V ±5% power supply 28-pin plastic or ceramic DIP Full TTL compatibility • • • • parity; 1, 1-1/2 or 2 stop bits. With the R6551, a crystal is the only required external support component - eliminating the multiple-component support that is typically needed. In addition, the R6551 is designed for maximum programmed control from the CPU, to simplify hardware implementation. A control register and a separate command register permit the CPU to easily select the R6551 's operating modes and check data, parameters and status. Frequency Temperature Range R6551 P Plastic 1 MHz OOC to +70 0 C R6551AP Plastic 2 MHz OOC to +70 0 C +70 0 R6551C Ceramic 1 MHz OOC to C R6551AC Ceramic 2 MHz OOC to +70 0 C IRQ RTS CTS TxO OTR RxO RSO RS1 11 12 13 14 R6551 Pin Configuration © Rockwell International Corporation 1981 All Rights Reserved Printed in U.S.A. en c:: :s -. ~--CTS '---I~TxD I/O CONTROL CS1 .. BAUD RATE GENERATOR 141--I~ RxC ~--XTLI I--"'XTLO VSS Q) (') » 0. Q) "0 r+ ... » n » CD TIMING & CONTROL LOGIC DTR RTS VCC :s :r+s CD CSO RES o :::.l. RtW JJ2 _. r+ CD .....- - DCD RS1 IRQ 07 06 05 04 03 02 01 DO DSR OCO VCC :s c:: o o 3 3 TRANSMIT DATA & SHIFT REGISTERS RSO VSS CSO CS1 RES RxC XTLI ...o:::T n DATA BUS BUFFERS Ordering Information Package Type -<:s (') (') Q) 00-07<::8 Order Number » en RECEIVE DATA & SHIFT REGISTERS RxD R6551 Interface Diagram Specifications subject to change without notice Document No_ 29000 053 Rev. 1, January 1981 - Control Register INTERNAL ORGANIZATION The Control Register selects the desired baud rate, frequency source, word· length, and the number of stop bits. T.O 00-07 I SBN I I RCS , WLO I seR' , ' - - - - - SELECTED BAVO RATE ISBR) DsR ~tW R.C CSO XTLI CS; XTLQ RSO OTR RS, fiTS I [SBR3ISBR2ISBR'ISBROI Lc--I 6CD IRQ WL I WL' ( ~ ! !.~ o Q 00 00 0 , 00 1 0 00 1 1 o 1 00 o1 0 1 o1 1 0 o 1 ., 1 , 0 00 '001 10 10 10 1 1 1 1 00 11 01 1 1 1 0 1111 .2 R.O Rei 16x b .... M) Clock a.\ld 50 75 '&.Iud 109.92 Baud 134.58 Baud 150 s.ud 300 600 Blud 12()O Blud 1800 Baud 2400 Baud 3600 Blud 4800 S.ud 7200 Baud 9600 s.ud Bo'" 19.200 a.ud ' - - - - - - - - - - RECEIVER. CLOCK SOURCE IRCS) o .. E~t...n.1 Receiver Ctock 1. - B.ud R••e ' - - - - - - - - - - - - - - WORD LENGTH IWL) R6551 BI;)ck Diagram n 00 Transmitter/Receiver 8 Bits 0' 'Bits 10 T1 SBits SSits ' - - - - - - - - - - - - - - - - - SToP BIT NUMBER ISBN) Bits 0-3 of the Control Register .select the divisor used to generate the baud rate for the Transmitter. If the Receiver clock is to use the same baud rate as the Tr·ansmitter, then RxC becomes an output pin and can be used to slave other circuits to the R6551. .....-""""T-- 0-1 Stop Bit 7 6 5 4 3 2 1 O. 10 10 10 I 0 10 10 10 10 I H"d ...," R.... ,IiU) - - - - - - - - Prolr.mRese! T =2StopBits -l%StopBitl IFor WL - 6.nd No Parity) zlStopBit . (For Wl" 8 and Paritvl R6551 Control Register RxD ( ....- - - - - - - - - - - RxC Commllnd Register XTLI The Command Register controls specific modes and functions. Transmitter/Receiver Clock Circuits Transmit and. Receive Data Regist~rs These registers are used as temporary data storage for the 6551 Transmit and Receive circuits. The Transmit Data Register is characterized as follows: • Bit 0 is the leading bit to be transmitted. • Unused data bits are the high-order bits and are "don't care" for transmission. ~ OATATERMINAL READY IOTR) o • Deb T«miNlI Not R_cty (OTA High) , • Datil TermlNlI RNdy li5TlI' Low) INTERRUPT REQUEST DISABLED (lRO) O. IRQ E..bltd , -IAQDilllblfd TRANSMITTER INTERRUPT CONTRDLITlC) ~ ~ iffiI. Hloh, T........ I......upt O_blod 0" RTI- Low, Tnn....1t Im.rupt E_1ed 1 0 m · LoW, Transmit Int.rupt Enlbled 1 1 fITS .. Low. TrlMlnit Interrupt DI_11Id Tr.n....it Bruk on TxO ' - - - - - - - - - - RECEIVER ECHO MODE IREM) 0" Recti. . Nor.... Mode . , .. ANI'_ Echo Mod. The Receive Data Register is characterized in a similar fashion: L--_ _ _ _--'-...;.._ _ _ _ _ PARITY MODE ENABLED IPME) o. .. PII,ity Mod. No Plirity BitDi.b'-' 0 __ • Bit 0 is the leading bit received. • Unused data bits are the high-order bits and are "0" for the receiver. Parity Check D_bled 1 .. Perity Mode El1Iblld ' - - - - - - - - - - - - - - - - PARITY MODE CONTROLIPMC) • Parity bits are not contained in the Receive Data Register, but are stripped-off after being used for external parity checking. Parity and all unused high-order bits are "0". Z Ii o 0 Odd ,.-Ity Tn..wmlttedIRectiwd o 1 E.... PI,ity Tr.ftlmittedlA. .i.... 1 0 Mlrk "'rhy Bit Tr.lIIMiIted PII,ity Check Otab... 1 1 StMce ..... ity Bit T,..nsm'*tecl ...,ityCheclcDillblMl R6551 Command Register ( Status Register cso, The Status Register reports the status of various R6551 functions The two ch ip select inputs are normally connected to the processor address lines either directly or through decoders. The R6551 is selected when CSO is high and CS1 is low. 1 I 0 ~ ~; ; : ; "'. Frammg Error· a '" No Framing Error 1 ,. Framing Error Detected CS, (Chip Selects) RSO, RS' (Register Selects) The two register select lines are normally connected to the processor address lines to allow the processor to select the various R6551 internal registers. The following table indicates the internal register select coding: OverrunD = No Ollerrun 1 = Overrun Hi'15 Occurred L-_ _ _ _ _ _ Receiver Data Register Full o ., Not Full 1 ,. Full RS' RSO Write Read 0 0 Transmit Data Register Receiver Data Register 0 1 Programmed Reset (Data is "Don't Care") Status Register 1 0 Command Register 1 1 Control Register L-_ _ _ _ _ _ _ _ Transmitter Data Register Empty o = Not Empty 1 = Empty L-_ _~_ _ _ _ _ _ _ Data Carrier Detect lOCO) o = OeD low (Detect) 1 = OeD high (Not Detectedl L-_ _ _ _ _ _ _ _ _ _ _ _ Data Set Ready (DSR) o = DSA low (Ready) 1 '" DSA high (Not Ready) L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ Interrupt (tRQ! a '" No Interrupt , '" Interrupt Has Occurred -No interrupt occurs for these conditions R6551 Status Register INTERFACE SIGNAL DESCRIPTION Note that only the Command and Control registers are read/write. The Programmed Reset operation does not cause any data transfer, but is used to clear Bits 0 through 4 in the Command Register and Bit 2 in the Status Register. The Programmed Reset is slightly different from the Hardware Reset (RES); these differences are described in the individual register definitions. RES (Reset) ACIA/Modem Interface Signal Description During system initialization a low on the RES input will cause internal registers to be cleared. 02 (Input Clock) The input clock is the system 02 clock and is used to synchronize all data transfers between the system microprocessor and the R6551. XTLI, XTLO (Crystal Pins) These pins are normally directly connected to the external crystal (1.8432 MHz) used to derive the various baud rates. Alternatively, an externally generated clock may be used to drive the XTLI pin, in which case the XTLO pin must float. XTLI is the input pin for the transmit clock. R/W (Read/Write) TxD (Transmit Data) The R/W is generated by the microprocessor and is used to control the direction of data transfers. A high on the R/W pin allows the proc' essor to read the data supplied by the R6551. A low on the R!W pin allows a write to the R6551. I RQ (Interrupt Request) The TxD output line is used to transfer serial NRZ (non-return-tozero) data to the modem. The LSB (least significant bit) of the Transmit Data Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected, or under control of an external clock (as selected by the Control Register!. RxD (Receive Data) The iRCi pin is an interrupt output from the interrupt control logic. It is an open drain output, permitting several devices to be connected to the common IRQ microprocessor input. Normally a high level, iR5 goes low when an interrupt occurs. The RxD input line is used to transfer serial NRZ data into the ACIA from the modem, LSB first. The receiver data rate is either the programmed baud rate or the rate of an externally generated receiver clock (as selected by the Control Register!. 00-07 (Data Bus) RxC (Receive Clock) The 00-07 pins are the eight data lines used to transfer data between the processor and the R6551. These lines are bi-directional and are normally high-impedance, except during Read cycles when the R6551 is selected. The RxC is a bi-directional pin which serves as either the receiver 16x clock input or the receiver 16x clock output. The latter mode results if the internal baud rate generator is selected for receiver data clocking. ( ",- ',,' (\ ' RTS (Request to Send) DSR (Data Set Ready) The RTS output pin is used to control the modem from the processor. The state of the RTS pin is determined by the contents of the Command Register. The DSR input pin is used to indicate to the R6551 the status of the modem. A low indicates the "ready" state and a high, "not-ready". DSR is a high-impedance input, and must be connected. If .unused, it should be driven high or lOiN, but not switched. CTS (Clear to Send) The CTS inp~t pin is used to control the transmitter operation. The enable state is with CTS low. The transmitter is automatically disabled if CTS is high. DTR (Data Terminal Ready) DCD (Data Carrier Detect) The DCD input pin is used to indicate to the R6551 the status of the carrier-detec~ outpuf of the modem. A low indicates that the modem carrier signal is present and a high, that it is not. Like 5SR, DCD is a high-impedance input, and must be connected. This output pin is used to indicate the status of the R6551 to the modem_ A Iowan DTR indicates the R6551 is enabled and a high indicates it is disabled. The processor controls this pin via bit 0 of the Command Register. READ/WRITE CYCLE CHARACTERISTICS (VCC = 5.0V ±5%, T A = 0 to 70 0 C, unless otherwise noted) 1 MHz Characteristic 2MHz Symbol Min Max Min Max Cycle Time 02 Pulse Width tCYC tc 1.0 400 40 0.5 40 - 200 - Address Set-Up Time Unit J..Is ns tAC 120 - 70 - Address Hold Time tCAH 0 - 0 - ns ns R/W Set-Up Time twc 120 - 70 - ns R/W Hold Time Data Bus Set-Up Time tCWH 0 - 0 - ns tDCW tHW 150 20 - 60 - 20 - 150 ns ns 20 40 - Data Bus Hold Time Read Access Time (Valid Data) Read Hold Time Bus Active Time (Invalid Data) tCDR tHR tCDA 20 40 200 - - ns ns (t r and tf = 10 to 30 ns) ===~VIH CSO, CS1, RSO, RSl ~~~VIL ~------------------VIH V 1L Write Timing Characteristics RtW ~---------------------------------------------------VIH Read Timing Characteristics ns I---------tccv--------~ TRANSMIT/RECEIVE CHARACTERISTICS 2 MHz 1 MHz Symbol Min Max Min Max Unit Transmit/Receive Clock Rate tCCY 400' - 400' - ns Transmit/Receive Clock High Time tCH 175 - 175 - ns - 175 - ns Characteristic XTll (TRANSMIT CLOCK INPUT)_ _.....I ( TxO NOTE: TxO rate is 1/16 TxC rate Transmit/Receive Clock low Time tCl 175 XTLI to TxD Propagation Delay too - 500 - 500 ns RTS Propagation Delay t Dly - 500 - 500 ns I RQ Propagation Delay (Clear) tlRQ - 500 - 500 ns Transmit Timing with External Clock (t r , t f = 10 to 30 ns) 1 'The baud rate with external clocking is: Baud Rate = -16--'--x TCCY IRQ (CLEAR) !- tIRQ _ -----J Interrupt and Output Timing I------tccv------~~I ( Rxe (INPUT) NOTE: RxO rate is 1/16 RxC rate Receive External Clock Timing PACKAGE OUTLINES 28 LEAD PLASTIC 28 LEAD CERAMIC I (.550) (.530) 1.115) '" (1.420) (1.380) • I + 1.080) j~~~A,,,,, : jt= (.055) (.010) (.022) (.015) I "'" --lI 11.090 ) I---:::: ---I ,-, 1.155) 1.065) (.125) (.015) a.,.;,..,.,..,1"'I"T"I"T"I................................................... ~ ~_------_(1.470)----_-. (1.440) (. (.065) 1.065) Intel S04SH/S04SH-1 /S035H LlS035H L-1 HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER • S04SH/S048H-1 Mask Programmable ROM • S03SHL/803SHL-1 CPU Only with Power Down Mode x 8 ROM • 1K 64 x 8 RAM CP.U, ROM, RAM, I/O in Single • 8-BIT Package • High Performance HMOS • Reduced, Power Consumption 1.4 usec and 1.9 usec Cycle Versions • All Instructions 1 or 2 Cycles. • Over 90 Instructions: 70% Single Byte 27 I/O Lines • Interval Timer/Event Counter • Easily Expandable Memory and I/O Compatible with 8080/8085 Series • Peripherals • Two Single Level Interrupts The Intel@ B04BH/B04BH-1/B035HLlB035HL-1 are totally self-sufficient, B-bit parallel computers fabricated on single silicon chips using Intel's advanced N-channel silicon gate HMOS process, The B04BH contains a 1K X B program memory, a 64 X B RAM data memory, 27 I/O lines, and an B-bit timer/counter in addition to on-board oscillator and clock circuits, For systems that require extra capability the B048H can be expanded using standard memories and MCS-80 Tl1/MCS-B5 T11 peripherals, The B035HL is the equivalent of the 8048H without program memory and can be used with external ROM AND RAM, To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally pin compatible version of the B048H with UV-erasable user-programmable EPROM program memory is available. The B74B will. emulate the B04BH up to 6 MHz clock frequency with minor differences. The B04BH is fully compatible with the 8048 when operated at 6 MHz. These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have extensive bit handling capability as well as facilities for' bo(h binary and BCD arithmetic. Efficient use of program memory results from an instruction set consisting mostly of single bit instructions and no instructions over 2 bytes in length. BLOCK DIAGRAM LOGIC SYMBOL PIN CONFIGURATION TO XTAL 1 Tl XTAL 2 P27 IiEsTt P26 ss P2S INT P24 EA P17 RD P16 PSEN WR PIS ALE P13 DBa P12 OB, Pll PORT o 1 PORT '. 2 B048H 80:iSHL B04BH-l 803SHL-l P14 DB2 PIa DB3 DB4 VDD PROG DBs P23 DBS P22 DB7 P21 VSS P20 1024 WORDS PROGRAM MEMORY CLOCK , B BIT CPU > ;:. IY- V B BIT TIMER EVENT COUNTER BUS 64 WORDS DATA MEMORY r- V 27 1/0 LINES PORT EXPANDER STROBE Intel Corporation assumes no responsibility for the use of any circuit.ry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. elntel Corporation 1980' AFN-01491A-01 APPENDIX A 8035/8048/8748/ and 8049 CPU SPECIFICATIONS ( This appendix contains the specifications for the CPU chips that may possibly be used with the system as its hardware design exists. of the 8035 is expected to compose the bulk of the applications. A-I Use intel [?)OO ~ OJfu(]O~~OOW S04SH/S04SH-1 /S035HL/S035H L-1 PIN DESCRIPTION = Designation Pin VSS VDD 20 Circuit GND potential 26 low power standby pin VCC 40 Main power supply; +5V during operation. PROG 25 Output strobe for 8243 1/0 expander. P10-P17 Port 1 P20-27 Port 2 27-34 8-bit quasi-bidirectional port. 8-bit quasi-bidirectional port. P20-P23 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit 1/0 expander bus for 8243. 21-24 35-38 DBO-DB7 BUS 12-19 Function True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR. TO Input pin testable using the conditional transfer instructions JTO and JNTO. TO can be designated as a clock output using ENTO ClK instruction. T1 39 Input pin testable using the JT1, and JNT1 instructions. Can be designated the timer/counter input using the STRT CNT instruction. INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also Designation Pin = Function testable with conditional jump instruction. (Active low) RD 8 Output strobe' activated during a BUS read. Can be used to enable data onto the bus from an external device. Used as a read strobe to external data memory. (Active low) 'RESET WR 4 Input which is used to initialize the processor. (Active low) (Non TTL VI H) 10 Output strobe during a bus write. (Active low) Used as write strobe to external data memory. ALE 11 Address latch enable. This signal occurs once during each cycle and is useful as a clock output. The negative edge of ALE strobes address into external data and program 'memory. PS'E'N 9 Program store enable. This output occurs only during a fetch to external program memory. (Active low) SS 5 Single step input can be used in conjunction with ALE to "single step" the processor through each instruction. (Active low) EA 7 External access input which forces all program memory fetches to reference external memory. Useful for emulation and debug, and essential for testing and program verification. (Active high) XTAl1 2 One side of c"rystal input for internal oscillator. Also input for external source. (Non TTL VIH) XTAl2 3 Other side of crystal input. AFN-01491A-02 S04SH/S04SH-1/S035HL-1/S035HL-1 INSTRUCT~ON SET Mnemonic ADD A, R ADD A, @R ADD A, /I data ADDC A, R ADDC A,@R" ADDC A, /I data ANL A, R ANL A,@R ANL A, # data ORl A, R ORL A@R ORL A, /I data XRL A, R XRL A, @R XRL, A, # data INCA DECA CLR A CPLA DAA SWAP A RL A RLC A RR A RRC A De,crlpllon Add register 10 A Add data memory to A Add immediate to A Add register with carry Add dala memory with carry Add immediale with carry And register to A And dala memory to A And immediale to A Or regisler 10 A Or data memory to A Or immediale to A Exclusive or register to A Exclusive or data memory to A Exclusive or immediate to A Increment A Decrement A Clear A Complement A Decimal adjust A Swap nibbles 01 A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry Byle, Cycle. 1 1 1 1 2 2 1 ;! 1 2 1 2 1 1 2 1 1 2 1 2 1 2 1 2 Descrlpllon Mnemonic Inpul port to A IN A, P Output A to port OUTL P, A And immediate to port ANL p, /I data Or Immediate to pori ORL P, /I data Inpul BUS to A INS A, BUS OUTL BUS, A Output A to BUS ANl BUS, # data And immediate to BUS ORl BUS, /I data Or immediate to BUS Input expander port to A MOVD A,P MOVD P, A Oulput A to expander port And A to expander port ANLD P, A Or A to expander port ORLO P, A 1 1 Bylel Cycle, 2 1 1 2 2 2 2 2 I 1 2 2 2 2 2 2 2 1 1 1 1 2 2 2 Regiliers Descrlpllon Increment register Increment data memory Decrement register Byles Cyclel 1 I I 1 I I Branch Mnemonic JMP addr JMPP@A DJNZ R, addr JC addr JNC addr JZ addr JNZ addr JTO addr JNTO addr JTI addr JNTI addr JFO addr JFl addr JTF addr JNI addr JBb addr Descrlpllon Jump unconditional Jump indirect Decrement register and skip Jump on carry = 1 Jump on carry = 0 Jump on A zero Jump on A not zero Jump on TO" I Jump on TO" 0 Jump on Tl " 1 Jump on TI "0 Jump on FO" I Jump on Fl " I Jump on timer flag Jump on INT " 0 Jump on accumulator bit Mnemonic CALL addr RETR RETR Delcrlpllon Jump to subroutine Return Return and restore status Bytes Cycles Description Clear carry Complement carry CLear flag 0 Complement flag 0 Clear flag I Complement flag 1 Bylel Cycle. 1 1 1 2 2 2 2 Flags Mnemonic ClR C CPL C ClR FO CPL FO ClR FI CPL FI Dala Moves Input/Oulpul Mnemonic INC R INC@R DEeR ( Subroullne Accumulalor Byles Cycles 2 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Mnemonic Delcrlpllon Byle. Cycles MOV A, R Move register to A 1 1 Move data memory to A MOVA,@R 1 I Move immediate to A MOV A, /I data 2 2 Move A to register MOV R, A 1 1 MOV@R,A Move A to data memory 1 1 MOV R, /I data Move immediate to register 2 2 MOV @R, /ldata Move immediate to data memory 2 2 MOVA, PSW Move PSW to A 1 1 Move A toPSW I 1 MOV PSW, A XCH A, R Exchange A and register 1 1 1 1 Exchange A and data memory XCH A, @R XCHD A;@A Exchange nibble of A and 1 register Move exlernal data memory to A MOVXA,@R 1 2 MOVX@R,A 1 2 Move A to external data memory MOVPA,@A Move to A from current page 1 2 MOVP3A, @ 1 2 Move to A from page 3 ( Tlmer/Counler Description Aead timer/counter Load timer/counier Start timer Start counter Stop timer/counter Enable>timer/counter interrupt Disable timer/counter interrupt Byle, Cycles I I 1 1 1 1 1 I 1 1 I I 1 I Mnemonic EN I DIS I SEL RBO SEL RBI SEL MBO SEL MBI ENT 0 ClK Descrlpllon Enable external interrupt Disable external interrupt Select register bank 0 Select register bank I Select memory bank 0 Select memory bank 1 Enable clock output on TO Bytes Cycle. I I 1 I 1 1 1 1 1 I 1 I Mnemonic NOP Description No operation Byles Cycles 1 I Mnemonic MOVA, T MOV T, A STAT T STRT CNT STOP TCNT EN TCNTI DIS TCNTl Control 1 1 ( AFN·01491 A·03 S04SH/S04SH-1 IS035H LlS035H L-1 A~C. CHARACTERISTICS (PORT 2 TIMING) TA = O°Cto 70°C, VCC = 5V±100f0, VSS = OV 8048H·1 8035HL·1 8048H 8035HL Parameter Symbol 6 MHz Min. Max. 8 MHz Min. 11 MHz Max. Min. Unit Max. tcp Port control Setup Before Falling edge of PROG. 110 105 ns tpc Port Control Hold After Falling Edge of PROG. 100 90 ns tpR PROG to Time P2 Input Must Be Valid tpF Input Data Hold Tinie tDP Output Data Setup Time 250 210 200 ns tpD Output Data Hold Time 65 35 20 ns tpp PROG Pulse Width 1200 970 700 ns tpL Port 2 1/0 Data Setup 350 300 250 ns tLP Port 2 I/O Data'Hold 150 65 20 ns 810 0 700 150 0 150 0 650 ns 150 ns PORT 2 TIMING \'--_ _ _~V \'---_ _~I --1' r' CA EXPANDER PORT OUTPUT r'DPi'PDl PCH I PORT CONTROL ,- EXPANDER PORT OUTPUT DATA 'PR I INPUT PCH PORT 20 3 DATA PORT CONTROL 'PC--! ~. PROG 'PP . V I I , BUS TIMING AS A FUNCTION OF TCY * SYMBOL TLL TAL TLA TCC (1) TCC (2) TDW TWD TDR FUNCTION OF 7/30 TCY 1/10 TCY 1/15 TCY 1/2 TCY 2/5 TCY 2/15 TCY 1/15 TCY 0 TCY MIN MIN MIN MIN MIN MIN MIN MIN SYMBOL TCC (1) : RDIWR T CC (2) : PSEN TRD (1) TRD (2) TAW TAD (1) TAD (~) TAFC TCA FUNCTION OF TCY 11/30 3/10 3/10 1/2 1/3 1/30 1/15 TCY TCY TCY TCY TCY TCY TCY MAX MAX MIN MAX MAX MIN MIN TRD (1) : RD TRD (2) : PSEN TAD(1);RD TAD (2) : PSEN • APPROXIMATE VALUES NOT INCLUDING GATE DELAYS. AFN·OI491A·05 ( . (, S04SH/S04SH-1/S035HL/S035HL-1 WAVEFORMS f-oo~-__-_-IL-L-_-I-ALE ICY ------·----i J \'-___-----'I L I ALEJ I- i-- i - I C C - - j - ICA I AD - - - - - - - . \ pst", IAFC - - ; I-- -I L i---IDR Ii FLOATING ~-F-LO-A-TI-NG--- : i FLOATING BUS BUS I___ IAD~~~ Instruction Fetch From External Program Memory ALE J Read From External Data Memory L WR -------,.X ~:: ~ TEST 2.4V O.4SV _ _ _ _....J. -:::~:: X. . .____ - - FLOATING BUS Input and Output for A.C.rests. Write to External Data Memory A.C. CHARACTERISTICS TA = O°C to 70°C VCC = VDD = 5V ± 10%, VSS = OV 8048H 8035HL Symbol POINTS • Parameter 6 MHz 8048H-1 8035HL-1 8 MHz 11 MHz Conditions Min. Max. Min. Max. Min. Max. Unit (Note 1) tLL ALE Pulse Width tAL 400 270 150 ns Address Setup to ALE 75 75 70 ns tLA Address Hold from ALE 65 65 50 ns tcc Control Pulse Width (PSEN, RD, WR) 700 490 300 ns tow Data Setup before WR 370 370 280 ns two Data Hold after WR 80 80 40 ns tCY Cycle Time 2.5 1.875 1.36 f.1s tOR Data Hold tRD PSEN, RD to Data In tAW Address Setup to WR tAD Address Setup to Data In tAFC Address Float to RD, PSEN tCA Control Pulse to ALE NOTE 1: Control outputs BUS outputs 0 CL = 80 pF CL = 150 pF 200 0 500 230 150 0 340 210 950 100 ns 200 ns ns 200 400 650 CL = 20pF (NOTE 2) ns 0 0 -1 ns 10 10 0 ns NOTE 2: BUS High Impedance Load: 20 pF AFN-01491A-06 ( (, ( ( ( ( ( I lIONEl LTRI [ 1811 AI~ REVISIONS DESCRIPTION DATE E.C"-I 54 I APPRovED I ~ 4 f" .00'-- '7"~4'l,' .~ 5H 2- '51-1 Z. ~H ~H t- eo. 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