_950_Terminal_Theory_of_Operation_26Jan1981 950 Terminal Theory Of Operation 26Jan1981
_950_Terminal_Theory_of_Operation_26Jan1981 _950_Terminal_Theory_of_Operation_26Jan1981
User Manual: _950_Terminal_Theory_of_Operation_26Jan1981
Open the PDF directly: View PDF .
Page Count: 88
Download | |
Open PDF In Browser | View PDF |
950 Theory of Operation CPU, Timing and Control (Refer to Figure 1) The 23.814 Mhz oscillator (Osc 1) is used to generate all timing for the terminal. It is used directly as the dot clock (Shift Clock), divided by 13 to drive the UARTs, and divided by 14 (1.701 Mhz) to.drive the CRT controller (CCLK) and the CPU (via the clock stretch circuit). The clock stretch circuit is capable, upon command, of generating clock periods twice the normal length (588 ns versus 1175 ns) for accessing slow memory or peripheral devices. Its output drives the 10 input of the 6502 CPU. The CPU then outputs 12, which controls the timing of the CPU bus. 12 is a slightly delayed ver.sion of 1 0 • The result of these circuits are 12 and CCLK, two signals of identical frequency but opposite phase, (except during clock stretched cycles). The importance of this will be made clear later in our discussion of the display controller. The CPU fetches its program from the ROMs (Read Only Memory) A41-43. It uses the 6522 (A54) to sense switches Sl and S2 and to generate control signals for the test of the terminal. Display Controller (Refer to Figure 2) Timer T2, part of the 6522, and the 6545 (A55) are used to generate the memory address, in Display RAM, of each character as it is about to be displayed, and the horizontal and vertical synchronization pulses necessary to control the deflection circuits of the monitor. Timer T2 is used to count horizontal scan lines and interrupt the processor (via NMI) when a specified number of scans has occurred. The processor then loads the memory address of the next data row into the CRT Controller and "sets" this address by generating a carefully-timed reset to the 6545. At this same time the processor loads a 4 bit value into latch, A61. At the time of the CRT reset this value is transferred to counter A60 and becomes the Row Address of the next data row. This value is then incremented by each horizontal sync pulse until the start of the next data row when it is again preset to a value determined by the CPU. The CPU and the display controller share access to the System and Display RAM (Random Access Memory). This is done during alternate phases of the 12 clock. During the positive portion of 12 the CPU address may be gated onto the RAM address bus by Multiplexers A43-46, and bidirectional transceiver A14 is enabled to pass data between the CPU data bus and the RAM data bus. During the negative portion of 12 the 6545 address bus is gated onto the RAM address bus allowing the video data to be latched by A24 and held for the display generator. This alternating access or "interleaved" access allows the processor to operate at normal-speed, without wai't_s of any kind, yet prevents degradation of the display quality that could be caused by inadvertant appropriation of the display bus by the processor to access data. The only penalty for this scheme is the necessity for fast RAM (150 ns or faster). Video Generation (Refer to Figure 3) This Display Data and the Row Address (or scan address) are used to obtain the dots for the next character to be displayed from the character generator ROMs A32 and A33. These dots are then fed in parallel to shift registers A22 and A23 and emerge serially as raw video. Additionally, bits 0-3 of Display data and bit 7 of A33 are combined to generate the attribute signals Underline, Blink, Blank, and Reverse. ICs A19, 20, 21 and 30 latdhand delay the decoded attributes from the previous data row for carry-over into the next. Bit 6 of A33 controls the intensity of the character to be displayed. ~ Gates AI, 2, 10 and 11 are used to modify the raw video to the proper intensity and polarity, and gate it on or off in response to the attribute signals and control signals BOW (used to reverse the entire display), cursor, BLI-RATE (used to blink the video) and FORCE BLANK (used to blank the entire screen). Transistor Ql is used to dr.ive the video to the proper voltage and current levels to drive the video module and/or an external mon.itor (using the composite video jumpers) . I/O Circuits (Refer to Figure 4) UART A49 is used to receive (and optionally transmit) serial data from (and to) the keyboard. The transmit path to the keyboard is normally used to conduct the bell tone from the 6522 (via driver Q4) to the speaker in the keybo~rd. UARTs A50 (Main Port, P3) and A5l (Printer Port, P4) are used to send and receive ser ial data from P·3 and P4 via the dr ivers, receivers and switching circuits A39, 40, 47, 48, 56, 57, 58 and 59. The UARTs A49, 50 and A5l (655ls) are connected to the CPU Bus and generate IRQ interrrupts when commanded by the CPU to send or receive data. Additionally these parts contain internal baud rate generators that must be programmed by the CPU to control the baud rates. (". General Debugging Guidelines The following procedures are usually 90ne when there is no initial beep at turn on. To debug any microprocessor without an emulator, remove as mahy devices as possible from the bus •. This includes the CPU, CRT controller, VIA, UARTs, and Program, User, and Character Generator ROMs. The address and data lines can then be checked for proper operation. Field component failures will generally be the most complicated integrated circuits. In case of a failure of this type, first replace any of the socketed components associated with the failure symptoms. Should the problem persist, check the RAM, RS232 components, bus transceiver, and multiplexers. This failure group is the most difficult to troubleshoot. An effective way to check the RAM is to use a test wire with two clips. Connect one end to the R4/Dl junction in the video section of the logic and the other end touching the outputs of the RAM. This, in essence, uses the monitor as a scope. Compare the response on the screen with a good terminal, and using this method, a faulty terminal can be debugged quickly. Should the problem not be found in the second f~jlure group, a simple hard failure in any area could be the cause of the problem. . 1/26/81 ( PART NUMBER DOCUMENT NO. 29000 039 REV. 3, FEBRUARY 1979 '1' Rockwell R650X and R651X R6500 Microcomputer System DATA SHEET R6500 MICROPROCESSORS (CPU's) SYSTEM ABSTRACT FEATURES The S-bit R6500 microcomputer system is produced with NChannel, Silicon Gate technology. Its performance speeds are This innovative enhanced by advanced system architecture. architecture results in smaller chips - the semiconductor threshold to cost-effectivity. System cost-effectivity is further enhanced by providing a family of 10 software-compatible microprocessor (CPU) devices, described in this document. Rockwell also provides memory and microcomputer system ... as well as low-cost design aids and documentation. • • • • • • • • • • • • • • • • • • • • R6500 MICROPROCESSOR (CPU) CONCEPT Ten CPU devices are available. All are software-compatible. They provide options of addressable memory, interrupt input, on-chip clock oscillators and drivers. All are -b'us-compatible with earlier generation microprocessors like the M6S00 devices. The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by external clocks. The on-chip clock versions are aimed at high performance, low cost applications where single phase inputs, crystal or RC inputs provide the time base. The external clock versions are geared for multiprocessor system applications where maximum timing control is mandatory. All R6500 microprocessors are also available in a variety of packaging (ceramic and plastic), operating frequency (1 MHz and 2 MHz) and temperature (commercial, industrial and military) versions. MEMBERS OF THE R6500 MICROPROCESSOR (CPU) FAMILY • • Single +5V supply N channel, silicon gate, depletion load technology Eight bit parallel processing 56 InstrUctions Decimal and binary arithmetic Thirteen addressing modes True indexing capability Programmable stack pointer Variable length stack Interrupt capabil ity Non-maskable interrupt Use with any type of speed memory S-bit Bidirectional Data Bus Addressable memory range of up to 65K bytes "Ready" input Direct Memory Access capability Bus compatible with M6S00 1 MHz and 2 MHz operation Choice of external or on-chip clocks On·the-chip clock options External single clock input - RC time base input - Crystal time base input Commercial, industrial and military temperature versions Pi'peline architecture Ordering Information Order Number: R65XX __ _ Microprocessors with On-Chip Clock Oscillator Model R6502 R6503 R6504 R6505 R6506 R6507 Addressable Memory 65K 41< SK 4K 4K SK Bytes Bytes Bytes Bytes Bytes Bytes lTemperature Range: No suffix = OOC to +700 C E = -40 oC to +S50 C (I ndustriall MT = -550 C to +1250 C (Military) M = MIL.sTD~3, Class B Package: Microprocessors with External Two Phase Clock Output Model R6512 R6513 R6514 R6515 Addressable Memory 65K 4K SK 4K Bytes Bytes Bytes Bytes C = Ceramic; P = Pla~ (Not AVaible for M 'or MT suffix) Ff'8t/uency Range: No suffix = 1 MHz A = 2 MHz Model Designator: XX = 02,03,04, ... 15 NOTE: Contact your local Rockwell Representative concerning availability. SpeclflCiition. tubJect to @ Rockwell International Corporation 1979 All Rights Reserved Printed in U.S.A. change without notice R6600 Signal Description Clocks (41 1 , 41 2 ) Non-Maskable Interrupt (liI1l1l. The R651X requires a two phase non-overhipping clock that runs at the V CC voltage level. A negative going edge on this input requests that a non-rnaskable interrupt sequence be generated within the microprocessor. The R650X clocks are suPPlied with ali internal clock generator. The frequency of these clocks is externally controlled. IiiMi is an unconditional interrupt. Following completion of the current instruction, the sequence of operations defined for i'fiQ . will be performed, regardless of the state interrupt mask flag. The vector address loaded into the progrlilm counter, low and high, are locations fFFA and FFFB respectively, thereby transferring pro· gram·.control to the memory vector located at these addresses. The instructions loaded at these locetions cause the microproc· essor to branch to a non-rnaskable interrupt routine in memory. Add,.. BUI (AO...A15) These outputs are TTL compatible. capable of driving one standard TTL load and 130 pF. Data BUI (00·1)7) Eight pins are used for the data bus. This is a bidirectional bus. transferring data to and from the device end peripherals. The out· puts are trioState buffers capable of driving one standard TTL load and 130pF. Data BUI Enable (DBEt This TTL compatible input allows external control of the trioState data output buffers and will enable the microprocessor bus driver when in the high state. In normal operation DBE would be driven by the phase ~ (41 2 ) clock. thus allowing data output from microprocessor only during 41 • During the read cycle. the data bus drivers are internally disa~ed. becoming .essentially an. open circuit. To disable data bus drivers externally.DBE should be held low. Ready (ROY) This input signal allows the user to halt or single cycle the microprocessor on all cycles except write cycles. A negative transition •to the low state during or coincident with phase one (41,) will halt the microprocessor with the output address lines reflecting the current address being fetChed. If Ready is low during a write cycle, it is ignored until the foUowing read operation. This condition will remain through a subsequent phase two (412) in which the Ready signal is low. This feature allows microprocessor inter· facing with the low speed PROMs as well as fast (max. 2 cycle) Direct Memory Access (DMA). Interrupt Request IIRQ) This TTL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor will complete the current instruction being executed before recognizing the request. At that time, the interrupt mask bit in the Status Code Register will be examined. If the interrupt mask flag is not set, the microprocessor will begin an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The micro· processor will then set the interrupt mask flag high so that no fur· ther interrupts may occur. At the end of this cycle, the program counter low will be loaded from address FFFE, and program counter high from location FFFF. therefore transferring program control to the memory vector located at these addresses. The RDY signal must be in the high state for any interrupt to be rec· ognized. A 3KO external resistor should be used for proper wire-OR operation. NMI 'also requires an external 3K wire·OR operations. n regis.ter tc:> (, V CC for proper Inputs iRO and NMI are hardware interrupts,lines that are sam. pled during 412 (phase 2) and will begin the eppropriate interrupt routine on the 41, (phase ,) following the completion of the cur· rent instruction. Set 0vrrflow Flag (5.0.) A neg~tive going edge on this input sets the overflow bit in the Status Code Register. This Signal is sampled on the trailing edge of 411 and must be externally synchronized. SYNC This output line is provided to identify those cycles in which the microprocessor is doing an OPCODE fetch. The SYNC line goes high during 41, of an OP CODE fetch and stays high for the remainder of that cycle. If the RDY line is pulled low during the 41, clock pulse in which SYNC went high, the processor will stop in its current state and will remain. in the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause Single instruction execution. ( Reset This input is used to reset or start the microprocessor from a power down condition. During the time that this line is held low, writing to or from the microprocessor is inhibited. When a posi· tive edge is detected on the input. the microprocessor will imme· diately begin the reset sequence. After a system initialization time of six clock'cycles, the mask interrupt flag will be set and the microprocessor will load the pro· gram counter from the memory vector locations FFFC and FFFD. This is the start location for program control. After VCC reaches 4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the R/W and (SYNC) signal will become valid., When the reset signal goes high following these two clock cycles. the microprocessor will proceed with the normal reset procedure detailed above. ( ADDRESSING MODES ACCUMULATOR ADDRESSING - This fonn of addressing is represented with a one byte instruction, implying an operation on the accumulator. IMPLIED ADDRESSING - In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction. IMMEDIATE ADDRESSING - In immediate addressing, the operand is contained in the second byte of the inStruction, with no further memory addressing required. RELATIVE ADDRESSING - Relative addressing is used only with branch instructions and establishes a destination for the conditional branch. ABSOLUTE ADDRESSING - In absolute addressing, ~econd byte of the instruction specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 65K bytes of addressable memory. The second byte of the instruction becomes the operand which is an "Offset"added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is -128 to +127 bytes from tha next instruction. ZERO PAGE ADDRESSING - The zero page instructions allow for shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. Careful use of the zero page can result in significant increase in code efficiency. INDEXED ZERO PAGE ADDRESSING - (X, V indexing) - This form of addressing is used in conjunction with the index register and is referred to as "Zero Page, X" or "Zero Page, V". The effective address is calculated by adding the second byte to the contents of the index register. Since this is a fonn of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally due to the "Zero Page" addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur. INDEXED ABSOLUTE ADDRESSING - (X, V indexing) - This form of addressing is used in conjunction with X and V index register and is referred to as "Absolute, X", and "Absolute, V". The effective address is formed by adding the contents of X or V to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time. INDEXED INDIRECT ADDRESSING - In indexed indirect addressing (referred to as (Indirect, Xl), the second byte of the instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory location on page zero whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero. INDIRECT INDEXED ADDRESSING - In indirect .indexed addressing (referred to as (Indirect!, V), the second byte of the instruction points to a memory location in page zero. The contents of this memory location is added to the contents of the V index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents. of the next page zero memory location, the result being the high order eight bits of the effective address. ABSOLUTE INDIRECT - The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location is contained in tha third byte of the instruction. The contents of tha fully specified memory location is the low order byte of the effective address. The next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program counter. INSTRUCTION SET - ALPHABETIC SEQUENCE ADC Add Memory to Accumulator with Carry AND "AND" Memory with Accumulator ASl Shift left One Bit (Memory or Accumulator) BCC BCS BEQ BIT BMI BNE BPl BRK BVC BVS Branch on Carry Clear Branch on Carry Set Branch on Result Zero Test Bits in Memory with Accumulator Branch on Result Minus Branch on Result not Zero Branch on Result Plus Force Break Branch on Overflow Clear Branch on Overflow Set ClC ClD Cli ClV CMP CPX CPV Clear Carry Flag Clear Decimal Mode Clear Interrupt Disable Bit Clear Overflow Flag Compare Memory and Accumulator Compare Memory and Index X Compare Memory and Index V DEC Decrement Memory by One DEX Decrement Index X by One DEV Decrement Index V by One EOR "Exclusive-or" Memory with Accumulator INC INX INV Increment Memory by One Increment Index X by One Increment Index V by One JMP JSR Jump to New location Jump to New location Saving Return Address lOA lOX lDV lSR load Accumulator with Memory load Index X with Memory load Index V with Memory Shift One Bit Right (Memory or Accumulator! NOP No Operation ORA "OR" Memory with Accumulator PHA Push Accumulator on Stack PHP Push Processor Status on Stack PlA Pull Accumulator from Stack PlP Pull Processor Status from Stack ROL ROR RTI RTS Rotate One Bit Left (Memory or Accumulator) Rotate One Bit Right (Memory or Accumulator) Return from Interrupt Return from Subroutine SBC SEC SED SEI STA STX STY Subtract Memory from Accumulator with Borrow Set Carry Flag Set Decimal Mode Set Interrupt Disable Status Store Accumulator in Memory Store Index X in Memory Store Index V in Memory TAX TAV TSX TXA TXS TVA Transfer Accumulator to Index X Transfer Accumulator to Index V Transfer Stack Pointer to Index X Transfer Index X to Accumulator Transfer Index X to Stack Register Transfer Index V to Accumulator VSS ROYO O.4V j~-PW-H-.-:---:'-:'-:':'~+-~ OL Rm ----t=~:.I~---------..J/ ~f O.4V CREF O'4V~1 "A" 1.5V . L ADDRESS FROM CPU I--PWHI/I 2 - 1 , . +-__ DATAFROM __- i_ _ _ MEMORY REF "B" -r_~~ ROY, 5.0. SYNC Timing for Writing Data to Memory or Peripherals Clock Timing - R6512, 13, 14, 15 ,REF "A" ~l·~------TCYC------~~ Rm ( ADDRESS FROM CPU DATAFROM __~-------r--c~ CPU REF "B" Note: "REF," means Reference Points on clocks. PROGRAMMING MODEL o 7 ....1ACCUMULATOR A I'--______ o 7 15 1~_ _.y...;..._ _ _~IINDEX REGISTER o 7 ....1INDEX REGISTER X 1,--_______ o PCH__-=-~__~;.;;;... PCl __~I PROGRAM COUNTER ,--_~...;;.;.. I Y X 7 I 7 11 I 8 I NIVI IB lOll I ZIClpROCESSOR STATUS REG ~ "PC" CARRY ZERO "s" 1 = RESULT ZERO IRQ DISABLE 1 = DISABLE 1 =TRUE '-----DECiMAL MODE ' - - - - - - B R K COMMAND. L--------OVERFlOW L.--_ _ _ _ _ _ _ NEGATIVE 'P" 1 = TRUE o -'1 STACK POINTER 1...-'--_ _ _ S_ _ _ _ o 7 A 1= BRK 1 =TRUE 1 =NEG. ( +- - .-r--- AD ....- Al A2 .... A3 CONTROL SECTION ---t.~ REGISTER SECTION +t~ rINDEX REGISTER Y ~ INDEX REGISTER X ~ STACK POINT REGISTER IS) t? INTERRUPT LOGIC '-RDY ABL .- A4 ..J r- .... A5 ~~ ..J « z a: w INSTRUCTION DECODE I- Z .- A6 .... A7 -~ ~ ALU ~ ~ ADDRESS BUS .-r--- AB :I: 0 « ..J « z I+I+I+- ~ Ii. a: +- A9 ....-- ACCUMULATOR .-- w l- TIMING CONTROL ~ ·A1D +- All +- A12 A13 ' ... ... ~ PCL ~ ~ PCH ABH ~ INPUT DATA LATCH IDLI I+- A14 A15 '- - LEGEND: 11' : L-< '" ~ ..... - q,2 DATA BUS BUFFER H PROCESSOR STATUS REGISTER P I CLOCK GENERATOR ,I t Note: .m--2 -I m '"T1 l> nm l> C VSS PAO PAl PA2 PA3 PA4 PA5 PA6 PA7 PBO PBl PB2 PB3 PB4 PB5 PB6 PB7 CB1 CB2 VCC CAl CA2 RSO RSl RS2 RS3 REs DO Dl D2 D3 D4 D5 D6 D7 ¢2 CSl Cs2 R/W iRQ Pin Configuration ,=.-~~~,-~ .. =-"~.",-~~.,".,-."------------,,, CD Rockwell International Corporation 1978 < m :rJ Temperature Range +70 0 C +70 0 C +70 0 C +70 0 C +85 0 C +85 0 C +85 0 C N N -I Ordering Information Order Number :rJ 0) (J1 Specifications subject to change without notice l> "m-I --< l> :rJ - OPERATION SUMMARY Register Select Lines I RSO, RS1, RS2, RS31 The four Register select lines are nCfmally connected to the processor address bus lines to allow the processor to select the internal R6522 register which is to be accessed. The sixteen possible combinations access the registers as follows: RS1 L L L L ORB L L L H ORA L L H L DDRB L L H H DORA L H L L T1L-L T1C-L Write Latch Read Counter T1C-H Trigger T1 L·UT1 Col Transfer H L RSO Remarks RS2 RS3 L Register H RS3 RS2 RS1 RSO Register H L L L T2L-L T2C-L Write Latch Read Counter H L L H T2C-H Triggers T2L-L/T2C-L Transfer Controls Handshake L H H L T1L-L L H H H T1 L-H H L H H L H H ACR H H L L PCR H H L H IFR H H H L IER H H H H ORA ( Remarks SR No Effect on Handshake Note: L = O.4V DC, H = 2.4V DC. Timer 2 Control R/W= L RS3 RS2 RS1 RSO H L L L Write T2L-L Read T2C-L Clear I nterrupt flag H L L H Write T2C-H Transfer T2L-L to T2C-L Clear I nterrupt flag Read T2C-H R/W=H ( Writing the Timer 1 Register The operations which take place when writing to each of the four T1 addresses are as follows: RS3 RS2 RS1 RSO Operation IR/W = LI L H L L Write into low order latch L H L H Write into high order latch Write into high order counter Transfer low order latch into low order counter Reset T1 interrupt flag L H H l Write low order latch X H H H Write high order latch Reset T1 interrupt flag Reading the Timer 1 Registers For reading the Timer 1 registers, the four addresses relate directly to the four registers as follows: RS3 RS2 RS1 RSO Operation IR/W = HI l H L l Read T1 low order counter Reset T1 interrupt flag L H l H Read T1 high order counter L H H l Read T1 low order latch L H H H Read T1 high order latch ( TIMING CHARACTERISTICS Read Timing Characteristics (loading 130 pF and one TTL load) Parameter Symbol Min Delay time, address valid to clock positive transition T ACR 180 Delay time, clock positive transition to data valid on bus TCDR - Peripheral data setup time TpCR Data bus hold time THR Rise and fall time for clock input T RC Typ 300 10 - Max Unit - - nS - 395 nS - - - - - 25 nS , nS nS TRF PHASE TWO CLOCK Jr-t---t---t---=:..::..-------- 2.4V ADDRESS -----,-:! . , , - - - - + - - t - - + - - - - - - - - - - - O . 4 V PERIPHERAL DATA Jr-..:..;::=---.:.--t--+----------2.4V T 1.-_ _,,1_ - _H.!I_ - - - - - - O.4V -2.4V DATA BUS r--"""';1f-- -- - - --O.4V Read Timing Characteristics Write Timing Characteristics Parameter Symbol Min Enable pulse width TC 0.47 - 25 liS Delay time, address valid to clock positive transition T ACW 180 - - nS Delay time, data valid to clock negative transition T DCW 300 - - nS Delay time, read/write negative transition to clock positive transition TWCW 180 - - nS Data bus hold time T HW 10 - - nS Delay time, Enable negative transition to peripheral data valid TCpW - - 1.0 J.l.S T CMOS - Delay time, clock negative transition to peripheral data valid CMOS (VCC - 30%) Typ Unit 1 - PHASE TWO CLOCK ,.--------2.4V ADDRESS --::;:o-J Max ~==::r---1::::"'..4:r,:;;~----O.4V rt-......::C::.:M~O::.:S'--_ _ _ _ 2.4V T DCW -1----1 READ/WRITE -O.4V DATA BUS - - - - - - - - - O.4V - - - - - - - - - VCC ...Jro-------2.4V PERIPHERAL DATA Write Timing Characteristics 2.0 liS I/O Timing Characteristics Characteristic Symbol Min Typ Max Unit Rise and fall time for CA 1, CB 1, CA2 and CB2 input signals TRF - - 1.0 j.ts Delay time, clock negative transition to CA2 negative transition (read handshake or pulse mode) TCA2 - - 1.0 j.ts Delay time, clock negative transition to CA2 positive transition (pulse mode) T RS1 - - 1.0 j.ts Delay time, CA 1 active transition to CA2 positive transition (handshake mode) T RS2 - - 2.0 j.ts Delay time, clock positive transition to CA2 or CB2 negative transition (write handshake) T WHS - - 1.0 j.tS Delay time, peripheral data val id to CB2 negative transition T DC 0 - 1.5 j.ts Delay time, clock positive transition to CA2 or CB2 positive transition (pulse mode) T RS3 - - 1.0 j.tS Delay time, CB1 active transition to CA2 or CB2 positive transition (handshake mode) T RS4 - - 2.0 j.ts Delay time, peripheral data valid to CA 1 or CB 1 active transition (input latching) TIL 300 - - ns Delay time CB1 negative transition to CB2 data valid (internal SR clock, shift out) TSR1 - - 300 ns Delay time, ne9ative transition of CB1 input clock to CB2 data valid (external clock, shift out) TSR2 - - 300 ns Delay time,CB2 data valid to positive transition of CB1 clock (shift in, internal or external clock) T SR3 - - 300 ns Pulse Width - PB6 Input Pulse T IPW 2 - - j.ts Pulse Width - CB 1 In'put Clock T ICW 2 - - j.ts liPS 2 - - j.ts IICS 2 - - j.tS . \ Pulse Spacing - PB6 I nput Pulse Pulse Spacing - CB1 Input Pulse PB6 INPUT PULSE COUNTING MODE C T 1PW =:\{"'"_-_-_-_-_-_-_:::: ~ r---2.4V CB2 SERIAL DATA IN T ICW CB1CLOCK ( \ O.4V ~TS R3 V-- -- ~ TSR1 2.4V O.4V TSR2 CB2 SERIAL DATA OUT ~ I/O Timing Characteristics 2.4V O.4V ( Timer 1 Operating Modes Two bits are provided in the Auxiliary Control Register to allow selection of the Tl operating modes. These bits and the four possible modes are as follows: ACR7 Output Enable ACR6 "Free-Run" Enable 0 0 Generate a single time·out interrupt each time Tl is loaded 0 1 Generate) continuous interrupts 1 0 Generate a single interrupt and an output pulse on PB7 for each Tl load operation 1 1 Generate continuous interrupts and a square wave output on PB7 Mode FUNCTION CONTROL Control of the various functions and operating modes within the R6522 is accomplished primarily through two registers, the Peripheral Con· trol Register (PCR), and the Auxiliary Control Register (ACR). The PCR is used primarily to select the operating mode for the four peripheral control pins. The Auxiliary Control Hegister selects the operating mode for the Interval Timers (Tl, T2), and the Serial Port (SRI. Peripheral Control Register The Peripheral Control Register is organized as follows: Bit # I 7 I 6 CB2 Control Function 5 4 CBl Control 3 I 2 I CA2 Control 1 0 CAl Control Typical functions are shown below: PCR3 PCR2 PCR1 Mode 0 0 0 Input mode - Set CA2 interrupt flag (IFRO) on a negative transition of the input signal. Clear I FRO on a read or write of the Peripheral A Output Register. 0 0 1 Independent interrupt input mode - Set IFRO on a negative transition of the CA2 input sig· nal. Reading or writing ORA does not clear the CA2 interrupt flag. 0 1 0 Input mode - Set CA2 interrupt flag on a positive transition of the CA2 input signal. Clear I FRO with a read or write of the Peripheral A Output Register. 0 1 1 I ndependent interrupt input mode - Set I FRO on a positive transition of the CA2 input signal. Reading or writing ORA does not clear the CA2 interrupt flag. 1 0 0 Handshake output mode - Set CA2 output low on a read or write of the Peripheral A Output Register. Reset CA2 high with an active transition on CAl. 1 0 1 Pulse output mode - CA2 goes low for one cycle following a read or write of the Peripheral A Output Register. 1 1 0 Manual output mode - The CA2 output is held low in this mode. 1 1 1 Manual output mode - The CA2 output is held high in this mode. , Auxiliary Control Register Many of the functions in the Auxiliary Control Register have been discussed previously. However, a summary of this register is presented here as a convenient reference for the R6522 user. The Auxiliary Control Register is organized as'follows: Bit fI 7 Function I 6 Tl Control 4 5 T2 Control I 3 I 2 Shift Register Control 1 0 PB latch Enable PA latch Enable ( Shift Register Control The Shift Register operating mode is selected as follows: ACR4 ACR3 ACR2 Mode 0 0 0 Shift Register Disabled. 0 0 1 Shift in under control of Timer 2 . 0 1 0 Shift in under control of system clock. 0 1 1 Shift in'under control of external clock pulses. 1 0 0 Free-running output at rate determined by Timer 2. 1 0 1 Shift out under control of Timer 2. 1 1 0 Shift out under control of the system clock .. 1 1 1 Shift out under control of external clock pulses. ( T2 Control Timer 2 operates In two modes. If ACR5 = 0, T2 acts as an interval timer in the one-shot mode. If ACR5 = 1, Timer 2 acts to count a pre: determined number of pulses on pin PB6, ( ROCKWEll INTERNATIONAL-MICROelECTRONIC DEVICES ~~~Y~O~U~R~L~O~C~A~L~R~EP~R~E~S~E~N~T~A~T~IV7.E~----' REGIONAL SALES OFFICES HOME OFFICE' Rockwell International Corp. Microelectronic Devices P.O. Box 3669 Anaheim, Ca. 92803 U.S.A. Phone: (,114) 632-0950 1WX: 910-591-1698 , Also Applications Centers CENTRAL REGION, U.S.A. Contact Robert 0 Whitesell & Associates 6691 East Washington Street Indianapolis. Indiana 46219 (317) 359-9283 Attn. Milt Gamble. Mgr. EASTERN REGION, U.S.A.' Carolier Office Building 850-870 U.S. Route 1 North BrunswiCk, New Jersey 08902 Phone: (201) 246-3630 EUROPE Rockwell International GmbH Microelectronic Devices Fraunhoferstrasse 11 0-8033 Munchen-Martinsried Germany Phone: (089) 859-9575 Tp.IA~: 0521/2650 MIDWEST REGION, U.S.A. 1011 E. Touhy Avenue, Suite 245 Des Plaines, IL 60018 . Phone: (312) 297-8RI ;:. IY- V B BIT TIMER EVENT COUNTER BUS 64 WORDS DATA MEMORY r- V 27 1/0 LINES PORT EXPANDER STROBE Intel Corporation assumes no responsibility for the use of any circuit.ry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. elntel Corporation 1980' AFN-01491A-01 APPENDIX A 8035/8048/8748/ and 8049 CPU SPECIFICATIONS ( This appendix contains the specifications for the CPU chips that may possibly be used with the system as its hardware design exists. of the 8035 is expected to compose the bulk of the applications. A-I Use intel [?)OO ~ OJfu(]O~~OOW S04SH/S04SH-1 /S035HL/S035H L-1 PIN DESCRIPTION = Designation Pin VSS VDD 20 Circuit GND potential 26 low power standby pin VCC 40 Main power supply; +5V during operation. PROG 25 Output strobe for 8243 1/0 expander. P10-P17 Port 1 P20-27 Port 2 27-34 8-bit quasi-bidirectional port. 8-bit quasi-bidirectional port. P20-P23 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit 1/0 expander bus for 8243. 21-24 35-38 DBO-DB7 BUS 12-19 Function True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD, and WR. TO Input pin testable using the conditional transfer instructions JTO and JNTO. TO can be designated as a clock output using ENTO ClK instruction. T1 39 Input pin testable using the JT1, and JNT1 instructions. Can be designated the timer/counter input using the STRT CNT instruction. INT 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also Designation Pin = Function testable with conditional jump instruction. (Active low) RD 8 Output strobe' activated during a BUS read. Can be used to enable data onto the bus from an external device. Used as a read strobe to external data memory. (Active low) 'RESET WR 4 Input which is used to initialize the processor. (Active low) (Non TTL VI H) 10 Output strobe during a bus write. (Active low) Used as write strobe to external data memory. ALE 11 Address latch enable. This signal occurs once during each cycle and is useful as a clock output. The negative edge of ALE strobes address into external data and program 'memory. PS'E'N 9 Program store enable. This output occurs only during a fetch to external program memory. (Active low) SS 5 Single step input can be used in conjunction with ALE to "single step" the processor through each instruction. (Active low) EA 7 External access input which forces all program memory fetches to reference external memory. Useful for emulation and debug, and essential for testing and program verification. (Active high) XTAl1 2 One side of c"rystal input for internal oscillator. Also input for external source. (Non TTL VIH) XTAl2 3 Other side of crystal input. AFN-01491A-02 S04SH/S04SH-1/S035HL-1/S035HL-1 INSTRUCT~ON SET Mnemonic ADD A, R ADD A, @R ADD A, /I data ADDC A, R ADDC A,@R" ADDC A, /I data ANL A, R ANL A,@R ANL A, # data ORl A, R ORL A@R ORL A, /I data XRL A, R XRL A, @R XRL, A, # data INCA DECA CLR A CPLA DAA SWAP A RL A RLC A RR A RRC A De,crlpllon Add register 10 A Add data memory to A Add immediate to A Add register with carry Add dala memory with carry Add immediale with carry And register to A And dala memory to A And immediale to A Or regisler 10 A Or data memory to A Or immediale to A Exclusive or register to A Exclusive or data memory to A Exclusive or immediate to A Increment A Decrement A Clear A Complement A Decimal adjust A Swap nibbles 01 A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry Byle, Cycle. 1 1 1 1 2 2 1 ;! 1 2 1 2 1 1 2 1 1 2 1 2 1 2 1 2 Descrlpllon Mnemonic Inpul port to A IN A, P Output A to port OUTL P, A And immediate to port ANL p, /I data Or Immediate to pori ORL P, /I data Inpul BUS to A INS A, BUS OUTL BUS, A Output A to BUS ANl BUS, # data And immediate to BUS ORl BUS, /I data Or immediate to BUS Input expander port to A MOVD A,P MOVD P, A Oulput A to expander port And A to expander port ANLD P, A Or A to expander port ORLO P, A 1 1 Bylel Cycle, 2 1 1 2 2 2 2 2 I 1 2 2 2 2 2 2 2 1 1 1 1 2 2 2 Regiliers Descrlpllon Increment register Increment data memory Decrement register Byles Cyclel 1 I I 1 I I Branch Mnemonic JMP addr JMPP@A DJNZ R, addr JC addr JNC addr JZ addr JNZ addr JTO addr JNTO addr JTI addr JNTI addr JFO addr JFl addr JTF addr JNI addr JBb addr Descrlpllon Jump unconditional Jump indirect Decrement register and skip Jump on carry = 1 Jump on carry = 0 Jump on A zero Jump on A not zero Jump on TO" I Jump on TO" 0 Jump on Tl " 1 Jump on TI "0 Jump on FO" I Jump on Fl " I Jump on timer flag Jump on INT " 0 Jump on accumulator bit Mnemonic CALL addr RETR RETR Delcrlpllon Jump to subroutine Return Return and restore status Bytes Cycles Description Clear carry Complement carry CLear flag 0 Complement flag 0 Clear flag I Complement flag 1 Bylel Cycle. 1 1 1 2 2 2 2 Flags Mnemonic ClR C CPL C ClR FO CPL FO ClR FI CPL FI Dala Moves Input/Oulpul Mnemonic INC R INC@R DEeR ( Subroullne Accumulalor Byles Cycles 2 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Mnemonic Delcrlpllon Byle. Cycles MOV A, R Move register to A 1 1 Move data memory to A MOVA,@R 1 I Move immediate to A MOV A, /I data 2 2 Move A to register MOV R, A 1 1 MOV@R,A Move A to data memory 1 1 MOV R, /I data Move immediate to register 2 2 MOV @R, /ldata Move immediate to data memory 2 2 MOVA, PSW Move PSW to A 1 1 Move A toPSW I 1 MOV PSW, A XCH A, R Exchange A and register 1 1 1 1 Exchange A and data memory XCH A, @R XCHD A;@A Exchange nibble of A and 1 register Move exlernal data memory to A MOVXA,@R 1 2 MOVX@R,A 1 2 Move A to external data memory MOVPA,@A Move to A from current page 1 2 MOVP3A, @ 1 2 Move to A from page 3 ( Tlmer/Counler Description Aead timer/counter Load timer/counier Start timer Start counter Stop timer/counter Enable>timer/counter interrupt Disable timer/counter interrupt Byle, Cycles I I 1 1 1 1 1 I 1 1 I I 1 I Mnemonic EN I DIS I SEL RBO SEL RBI SEL MBO SEL MBI ENT 0 ClK Descrlpllon Enable external interrupt Disable external interrupt Select register bank 0 Select register bank I Select memory bank 0 Select memory bank 1 Enable clock output on TO Bytes Cycle. I I 1 I 1 1 1 1 1 I 1 I Mnemonic NOP Description No operation Byles Cycles 1 I Mnemonic MOVA, T MOV T, A STAT T STRT CNT STOP TCNT EN TCNTI DIS TCNTl Control 1 1 ( AFN·01491 A·03 S04SH/S04SH-1 IS035H LlS035H L-1 A~C. CHARACTERISTICS (PORT 2 TIMING) TA = O°Cto 70°C, VCC = 5V±100f0, VSS = OV 8048H·1 8035HL·1 8048H 8035HL Parameter Symbol 6 MHz Min. Max. 8 MHz Min. 11 MHz Max. Min. Unit Max. tcp Port control Setup Before Falling edge of PROG. 110 105 ns tpc Port Control Hold After Falling Edge of PROG. 100 90 ns tpR PROG to Time P2 Input Must Be Valid tpF Input Data Hold Tinie tDP Output Data Setup Time 250 210 200 ns tpD Output Data Hold Time 65 35 20 ns tpp PROG Pulse Width 1200 970 700 ns tpL Port 2 1/0 Data Setup 350 300 250 ns tLP Port 2 I/O Data'Hold 150 65 20 ns 810 0 700 150 0 150 0 650 ns 150 ns PORT 2 TIMING \'--_ _ _~V \'---_ _~I --1' r' CA EXPANDER PORT OUTPUT r'DPi'PDl PCH I PORT CONTROL ,- EXPANDER PORT OUTPUT DATA 'PR I INPUT PCH PORT 20 3 DATA PORT CONTROL 'PC--! ~. PROG 'PP . V I I , BUS TIMING AS A FUNCTION OF TCY * SYMBOL TLL TAL TLA TCC (1) TCC (2) TDW TWD TDR FUNCTION OF 7/30 TCY 1/10 TCY 1/15 TCY 1/2 TCY 2/5 TCY 2/15 TCY 1/15 TCY 0 TCY MIN MIN MIN MIN MIN MIN MIN MIN SYMBOL TCC (1) : RDIWR T CC (2) : PSEN TRD (1) TRD (2) TAW TAD (1) TAD (~) TAFC TCA FUNCTION OF TCY 11/30 3/10 3/10 1/2 1/3 1/30 1/15 TCY TCY TCY TCY TCY TCY TCY MAX MAX MIN MAX MAX MIN MIN TRD (1) : RD TRD (2) : PSEN TAD(1);RD TAD (2) : PSEN • APPROXIMATE VALUES NOT INCLUDING GATE DELAYS. AFN·OI491A·05 ( . (, S04SH/S04SH-1/S035HL/S035HL-1 WAVEFORMS f-oo~-__-_-IL-L-_-I-ALE ICY ------·----i J \'-___-----'I L I ALEJ I- i-- i - I C C - - j - ICA I AD - - - - - - - . \ pst", IAFC - - ; I-- -I L i---IDR Ii FLOATING ~-F-LO-A-TI-NG--- : i FLOATING BUS BUS I___ IAD~~~ Instruction Fetch From External Program Memory ALE J Read From External Data Memory L WR -------,.X ~:: ~ TEST 2.4V O.4SV _ _ _ _....J. -:::~:: X. . .____ - - FLOATING BUS Input and Output for A.C.rests. Write to External Data Memory A.C. CHARACTERISTICS TA = O°C to 70°C VCC = VDD = 5V ± 10%, VSS = OV 8048H 8035HL Symbol POINTS • Parameter 6 MHz 8048H-1 8035HL-1 8 MHz 11 MHz Conditions Min. Max. Min. Max. Min. Max. Unit (Note 1) tLL ALE Pulse Width tAL 400 270 150 ns Address Setup to ALE 75 75 70 ns tLA Address Hold from ALE 65 65 50 ns tcc Control Pulse Width (PSEN, RD, WR) 700 490 300 ns tow Data Setup before WR 370 370 280 ns two Data Hold after WR 80 80 40 ns tCY Cycle Time 2.5 1.875 1.36 f.1s tOR Data Hold tRD PSEN, RD to Data In tAW Address Setup to WR tAD Address Setup to Data In tAFC Address Float to RD, PSEN tCA Control Pulse to ALE NOTE 1: Control outputs BUS outputs 0 CL = 80 pF CL = 150 pF 200 0 500 230 150 0 340 210 950 100 ns 200 ns ns 200 400 650 CL = 20pF (NOTE 2) ns 0 0 -1 ns 10 10 0 ns NOTE 2: BUS High Impedance Load: 20 pF AFN-01491A-06 ( (, ( ( ( ( ( I lIONEl LTRI [ 1811 AI~ REVISIONS DESCRIPTION DATE E.C"-I 54 I APPRovED I ~ 4 f" .00'-- '7"~4'l,' .~ 5H 2- '51-1 Z. ~H ~H t- eo. AQ.RAM I'!. _ _ _ _ _ _ _ _.;.:13<-1c. -=:::::.:.:...:.:.:....::..::. ~------~------------------------------------------------------------------------------------------------------------------------, AD· RAIJ· II ~~~~ __~----------__--1~5,A AD.RAM·lt I· 14 8 8t~~~------~----------------------------~-----------------------------------------------------------------------------------------------------, I 6b'~I4_4_--------------------------------------------------------------------------------------------------------------, 5 ac.. CoLI(. I.t " ~~~~------------------~O " 14~ 10_ '" ., ) AI'" ':>0'=---""---/ A8 "L~~ l4LS~'Z. }:8~t_--------__r 14LS~t +-_~-S...;.,,-I AI" '" AD·RAM·IO AO.RAM·e AD. RAM.' 5H t.- AD. RAIJ.'5 AD·RAM·" AD·RAM·' AD·RAIJ·'l, AD· RAM· I 0$ ,.. ~ ~ ~ c c < ~ At5 '2.114 .., 8 I... 13 It 8 e 5 G~D \I Ii- I~ +5V 5".,,, 3 Z I ~ 18 ..,""In cO-'" c c c c c Vee. 11 I" 1'5' r >II C 88 14 OB.~ !!1M I DB·! OB·Z DB" DB· I/> '!IH 25101 I OME~.E.~ : R./W " It 1\ 14 e, '," :\AI:(.~ '" e, Al A: B4 U Ie. at IS 8 11 BI 18 A3 A2. AI B~ '6l. mt~ 01 T~I" IS ... 3 t c: 13 ~ p G~O~9 rr s 01t-t-,~1::::.:.:.:.~-, 08 A4 ~ ,&_N'" ~ c c < 8'''5 Lt.' OEL·DI5P\...ENA I 11\ All iSl~j5L.EN ·v .-I RI9 IIC. RA3 ,A l' " ~- 8 1 18 '' " 5 tc~~ All ., AIO fcs . ~ " ~~_+_+_+_+-----4' ~.• " AW /I .::1+5\1 Rn 15 LD CLR , 1 Icn,o. L -__ ,A ~ OH t lot U "MLSOO I.... H. LD +5V ~ II<. 5.11/- S A ~---..f-~8 "10 oz- I-:-:-______________ 01 4 ~-------------'---+--5~ C t 1.1 .... H r---f>CI<. C.K 03 ()4. A8 An I vsr..r __________~~---------..:.:'5~5IR ~~ IQt-3~_+------~--_.~_+_+~------~----------_.----~ A1 233L·_ 05 14 4 ~ .5\1 0(. r--------,,~ 10 AlB 2.Q'1-:5=-+-------t---+-+-+-4-------------~t-----+----::-I Af. 1 .-----,t~ Z.D14L51133Qt-f.--+-...,.---~-.-+~-4--....;,..--.....--------t-----+----.:::..j A5 01 4 11.14 r----~3D 4at---~------t--t-~4---~--_+-----------~--_+----... A4 E5 IK ---2!. 40 Eft I4 1 •• r-__~14L~~_OO ____1~,CLK 510/ '1. IDE /I " I," TC. I Qtt-l~____~, 01 ~D~B~~~_____4~DI , e A" AU. 04 l!a Atl. A8 Z 33'1. . os ~,"------------~I-----..:.:,t' F 14LSIGoGo Al G ~~~+8Qt-'-'~+_~~------_t__t_~~------~4~ OE. '0 E 11 :~ I" 15 If. 11 .A : 14 It 1 f,J ~I>CIC. CIt.I ....... · .Hr'3'--------------~------------ II(. ~~ PR ~____-+~5~~ ..!.o Q 5 DEL CURSOR 511 ~ A11 14L'71 3 ~. I ~~~~------~_+_+_+_+_+----------~_a ~ 5 >'-"t---I~~~--"'--.:....j ~_.~~I~~~ 1___ -, A10 3 141.S08 IV.-.:4::-+-I----1....,:...---...--::1 4' 10 ---.;. 14 II~ l..A ~ 8 A Q<.14\.$n4 CI(. Q' UIJDERLlt-lE ~t=_--~H~~_+---------------::~~.;;:;;.;..=___ REVERSE·YIlJEO , Q'lt-:,=------4~_+-+---------------=~::::::::.;.==- BL't.lK QS~--------.......f-+-----------------.=:..:.:..;:.:..:....---- 1 BLAt.JK. 4V~I~t~_+--_+~_+_+~-~~1 4D Q.~I~O----------~-t---------------__~~~~----DEL.OI5PL·Et-lA1.0 wD AZ' Q5 It HALF·lt-lTEt-l5ITY w . "MoLS"1 1415'1+ Q(oJ~'5~-------------------_----..:.:;:..;;;;....::~~=.;.;.~ 10 t~ r---+-+-+-+"";'''''i' 5D 10 13 18 ,QIQ, II 31) Ajq - TI q 1 2Vt-q::--t-t---i--"'-+~Go 1.D 3Yt-:::-++-+--....f-f-:7-I30 a.-____________________~14 4A ....20=-____________--'--____' :-1 I, 3 ~t---::4:-i II) ~ ~g ell. CLR ..-----....;;...-..:---~3'A o ~) ~ 14L~ r-------------~~~~~"~1_ A12'4 14LS.04 ., ~-r__~~~_q...~A~~ 1--1 . Z~ I-f-+-+-+---~I'I A.. 3 5_ ~~ow.\O~ ~~A~I~~--~ 14L~4 VSVt.lC 311 " RIB SMIFT. CLI(.. O\SPL.EtJA DOT BIAL "17 .j'-",u> ~ ,,. ____~~~~-- +5V I All +5V Z,I At.~ 0 14L"lIf.w II YPP '4L.~ ~I_~ 14L50+ SH f. DATE I 54,', 5 0 /0 03 11 S A5 z.f! [eN CL~ " ot A~ A. 1(, -~CL/(. CRTC.Kt5 ADO J 1Q II 8D - 5H I ~ 11 lD At.4 ClI·AD·' ~II " .'1 RI" o 01 I DESCRIPTION "IIC. \J ~ L i +!5V In r CM.AD.' REVISIONS I ZONE I LlRl % cut 48 STRI .l I' ~SH w ~V _I 14LSoa ROW.' DISPL·EIJ- _ICA'. . .,_, _011 _ _• -......... '........... .- ~o ~--. 5Hw 51014 DW.O.~_ ""'0._ .. - COUTROL 80· "SO '~..: a.-OO1 Ii ---~ - 7 8 6 .I I ~ ~ 'X"TALI D -=A=B~~~ ~ ______~~____________________________~~I' ECIJ I ii: 5+ ILl ~~IRQ ~A~B=I~______~~~__________________________~I~'" : fl. APPIIOVED DESCRIPTION .... , I" ________ ______________________________ u. _ Y1tQ" ~== REVISIONS .,. " I 2 3 4 5 D R~~ R51 P'7-1 ~R~~______~4-~~__________________-+~t~~ R~ A8q .. ~~~~---+-+-r;----------------------r~C5~ ~r~o~.p~.S~E~L~__~~~I-1~~----__--______--__---+~~ CSI ~D~B~~________~~~~~~--------__----~----~~le OB~ 5H I..... OBI ICJ OBI DBl. DB' W DBl. DB4 DBS Z"Z. 0 B4 t3 OBS D~ « DB' .2. 1..5 DB' ~ DB' 10 Q r-:t 1----..1.... ...._-:-- - - 1 10 11 +;' I~ U. ~~~_+~4_+_~~_+~4_+_~~~~ XLI _+--_+-_+H~---~--_~++----~----...:..J OBl. CTS~q~--~~_+_+--4_----------~ t-r-r-~~~~~~4 OB9 t-r-~~~~~~z~t DB4 t-~H_4---+-~~DB5 .-~~__~~Z4~DB~ .....r-r-_r-Z5~DB' " ro 38 ~HHH_+......;,;.jl 3A -::!:I Y-+-++~+-+_+_~I___4_+_+---.!.I!t~ R5¢ , Pf>-Z ~! 1"88 5 ---4---. 'D!R ~I...:..l 3 ~r_~~~r;~~_+_;-----..::~CST ~r_~~~~~~~~--~la~O&o T. ~ t---< C43 330 r l I--< C45 rl--< C55 1'188 PF 330 PF ., II?'CJ e 1 L, L--.... I - ....-____..::Z~ A48 P!-w CTS ,\. P+~'S RT' ~ .J:.15 ," .~ .. 05R C4t 330 PF - P;l-IO ;t I~ SIG. Gt.lD [ 'IG.Gt.lO PROT· GMD ~~~~r---~1.~3 OB5 L...j~~f---~1.4.:..j DB" A51 "551 '-IHf---~~~ DB' '-I~--....::t'.!.I. ~ L-----4:..tR~E,. .J:I AM) E" ..: 140b +SV ........ .... R54 5104 b¥a P3~1 P3-13 A " ......--.. ~~ .... 5 P4-1 P3·Z5 a .cAlI: 6 P3-' , P"-I '------+------------__________________ ~A'8\.~"'~~ ___ 4-~~~ B q 10 "'48 p..;;--......------+---------------~, 2Y~-----r----r_----------~--------------~~----------~~~~.~I~ 1L.....-j1~ C5~ I . 330 PF 20 OTR C43 ~~I~t~r____+------------______--------4_----------------J ~~~~~~~~--~t~O OBt ~~~~~~~--~,~I DB' Y~HHH----.....:U!:.lDB4 PF 330 PF 14aa ~~I~.~r_--_+------~------------------~--~ ~~~r;~~_+_;----~lq~DBI A48 10 Asq tA I 330 P4-3 ....---~ "7 L.....-j,-- P3-t IzIA3q~~II~----------~J~__--+_-3-30--P-F----~R~.~D~" 'Yr~~----+----i------------~--------------~4_-+-q~ &---+~ tIS - rt/W 7 P3-14 P4-B 1A!q 11_. 8 1m r::------+_+--~__=..f I D l Y ... 10 <----t-2=-t I'" TID ~-----'I "D'TR ~ SU. 14 YH-+_+++-+-+_H~___4----..!:!.I R!ll L-jH-+-+--+-+--I-+-hl--l>--_....:Z~8 _A_B_I_O---:-____________---!HHH~HH~_+_+_+-------!!2::.j C50 IOO.a. , oeD", 5 ~~+-----~ 13 It 4 ~48 ASq 4Y~-----;-----r------------~--------------~~------------~~ L~~+_+_~~_+_+~~4_+_+_---!t~~~ttl~~~-~111~5--1 1m XLI 8 8 1'.0 MOO .....~~~~IO~4A 74LS157 v ~MO.At1lM '---t---\ 14LS'2 ~~~~~---r-r-r~~1-1-+-+-+-+-+-+-+-+---+---------~+~5V~------------~~~~~~ "L .-_......- 74L!I32 r--_ _~4..f q ASS '-------i '"55"1 t--I--4~RE,et P3~24 5 c "- 1 . 10 1150 t1 02 A , AS8 PI-'Z PI-4 1\ TltO " A48 rp..:..:--------..--------~~-:..:....::~4 ----./ 1488 L - - C!il ' t PH ';' R~l,SIOA I/?W 1~3t 11--__....:.::12:.{,-1--""""" ~-----+~4_-~-' PO~I ' -A R~O~I~Z~------_+_+--_+--------4----++~----~----------~~ W RIIOI +SV 14L50S OCO rLI-"------~_+_+--_+--------H----++4_----~----------_+--~ ~r_r_r-r-~~~~~~14q OBI " ES to I, OSR t-~H-4-+--+4--I-+---~~OB¢ !lH 1 , RxO --'" RlIC !-=-5____ 18 Bl:-OIR.EI.lA GI.lO TXD~I~O------_+--_+--_r~r-----_1----~~~----~------~------~----------~ t-HH_+_+-+-+-+-+~--+....:3~ CSl 5H' <50=: El PO-l UF =--____ ~-+~~~~~~~--~m~~W B Ct~.OI R'30 510A 'fl,W DTR~I~I------+_----_, 1m 1-8 -+_.., ~A~B~I~I______~~HHH~~~H~_+_+_+_+_+--_+~t eso ZI * '3rO-P~F~--------~ 115 ~~~_;-4-+_+_-+~~4_+_+_--~I~' ~ ~r_~r_r_r-~~~~~~--~~14~RSI SH I Of AlioS 14LS!('" q " C40 (/7 TKO ~ T PF It. RlIO ~~ c l C411 330 ,.. Z1 IU. "I- ... ~ SH(' Pl-Z A~ '"551 4 3 2 ( , " ( I I ( REVISIONS APPIIOIlED D£SCRIPTION 51-1 25H l. EC. RArb. R.A3 BLACK.OIJ·WH.ITE .(a.O·W) '4L904 C9 '5 BLI·RATE IO.OI~t It t 15 BLAIJ'" • AIO '''OG. DOTS. SERIAL "llII UIJ DER LlIJE +511 DEL CURSOR REVERe.E VIDEO OEl DI~PL· , EIJ - -It II . • G....O AIO 5 ~ • AIO II RS 1If. '40'" . I' !o R4 2.10.4. '40'" . l'l • " E.4 --~------ ____________r-__________________ __ ~ 11 ~1I~-+---------4~I~ Iltt~~ . r-:l - ~ A5 SEL,CPU'ADDR SH "" 5H Z 4- SH +5V ~ JVV'v- ?' PR ~J Ae. " QrL '4L'510'l eL.K ... l 1 RII !·31fRli 1M . ., ~ q ,4-UK>0 ~4 )O~A~8~-t---------------------, RESET _8 A8 14L.S04 '4L5~. 1 .I. i MlI,T 11 SHIn-.Cll(. SH 1FT .CLI( 5H 4 5H, occil5COR ~ rt:J8 '" '" 10~'500 q A5 14-LS08 '--__________________.J _1CA'' ' ~..- :;=_=-OII-.c:--.-.. I-.-:-.,":'_~ .. ___ _ I' ""I' ""I ......---4----'-1. • I. - ~ - I:' , •. 'KMM· .~_ c:oooo.c.....Aoe .. II.,. .-..... __ 5H 1 5H .. XTALI '5 5H 1,'5,' C49 .01Ad ifJo 4 , +5V A'S f Pl.-I SH 2. 5H RIOolK AS 0..:.1_ 1__ pl.-' ..HSV ....C. DC.CARRY '1 ~~I~WA~ t-----------__------________~3~ ~4~1 P2. -(g .. "SYNC (",.... ) DC.CARRY .. ... CQI..\P.""TTL IIIDEO c.eLK t Pb-8 pl.-' r------.~_~------------SH 1 .. I P6-10 ~-, AIO ',,"lS04 '4 l!l ,t. p,,-, RI II<. 3 AI'" ~- ~~-----------------~ PAt 3" ~~~--------------------------:jR5Z ~~----------------------__3:~~RS3 PA4 PA I pAl/) CA I CA2 3 1-J---------~S~IY Z. l40 ~______________________________________--, L-:-~_--. , P5-1 PA~ v PSG. 3Y _o BI.DIR.ENA LI~4---I---_--_--------~'___;qoo. I.!I~t~-l-..,...-------------IiIO;o,~~ 5AI.!~ 10 __~~r-________________~IO~ 4A q IA L~Z__LLL+-.-~---------o liND > R40 II<. ~ 10 3 IY LI 115 GT Gt"" , ty 5 C.D~ 3Y q 11"'4- 4Y " 5Y ~ ('Y ("Q~ 5A A"5 4A 14LS3l.o'3A tA IA I.. IZ. .." 'l. GIJD ··.f:8 C·CLK +t A~q ClR HSN r~~~~---------1r-------------------~~7 +-ltV q +I~V Q ~~1-.---------+---------------r_~)-I,V r +SV -11.'1 ~ " . 1___ 1 <.: ..• ~J!TC1t, -r. . C11~ T :' To.I';" T L---:.I~Ic> eLK PR 910 I -v. A _c 2.2:...1 Gt-IO 22 ...f .01..... I : T C,," 1'01 .... z.1....J " Gt.lD -7 q r--- 1\ 10 1+5V "14l504 8 q JV~~ Al0 he '4L500 5 10 I / SW 5 • HSt.J 05 I j 11J~01 PS-3 Gf "" ~ (,,~ GLR PS-4 ___ 5Y 141.5""ZA --q~cU<. , '" ~~~-~~4Y ~~_I-41 A~b ~Lw~--~~+-~----------------~e~~ 1..!...----1-1-1~I--..--.r_----------:,~.,.,. [IT: 40 14L5114 P5'-S Gr ~~~-+ 15~t~ +sv 3D ... 3G ' 5H 5 "A~I~~~________--~~r1r---~~--~4~~ GIJD LJ-I--lH-+--:::-1IY __ &-+-+-+---1 ~ 511 (,. OUT SPEAKER IiLIICK·Ot.I·WIIITe (BOW) SH ?a ti3================-------===-tHttt~JT~I~~15 z ID IQ 4Q~ ~ 4 '50~ 5 tD It rZ ZQ 'Q~ " irI ("Y GND 5H , Gt 3q 5H Z. L.. ~- ~2.4 ~ 8 G~ ___ IALt~------~~+_~r__t_r--~ 9" PB4 15 pes ~~ 2.3 C'll ~~-----------------~ ____________________ CSZ ______________________~B , q 4Y A<..' __________________-:jzt ~W 34 RES ~~----------------~ ~~ ~ LI~4 -_-4-+-+-t--Hr---:3;o,~ ~-------~,12.Y 5AIII~0~__________~+-~rlr_~~~~ l~----------------------------------------_=======:t:t:t~======~3Y 4A~" ,,~ It 3A ~------------'---irl----:';o: P8t 13 " !lY l1L5%'l.A L..!.-.----------------t--t---e8~J,. PS3 14 13 IALZ.~--~--------------~~r-__ ~e ~~~----------------------:3,jR51 38 R':.,p ~~~ tS5" PA5t:t=========================---------------rt---------~JA~'I~~I~ -E~-----------------------:3t1DBI ____________________:j2.5 .. ... ________________________________ ~~________________________:30~DB3 ~~ S --------~~~IY~I ~ ZY PA~~=======----------------------_l---------tlj_------_,~ L" A~. sv 1.,~----J-~~~4__1_+--_.--~~~~~--P8'LI~o~ _t--__----_, '~L5!"12AL ~-----J~~~_f_+--_t~--~z ~ ~ -l~~--------------------------::JD84 ~~ RE'l. I K. Iq CBt [! ____________________________________~ ~~----~-----------------~~' OB~ 2.8 DBS ~~--------------------:2.q~ SW " SH Go 4S'''2.4'=o8153 / , RP!I l ~Ii~. II<. l\P, RE~· IK __________________________________________________________ eRic RESET ~~~~~ ___ SH ~ () ( i i 82 RPI ~ I\I~ ~O'O~ I" ~ R3 Ql El CSr"\ R4 '-" + R5 I ;' ~ ~ Q: ' ~ u ~ o· ~ ,Q:~' G"~ ai' ~ (~ rn" 01 :c E2 '" '" C7 '" ;;; a; R9 OSC 1 A7 E4 E3 Al1~ 0:I2~ ~ CS~ '" '" 0 A 0 g: C;; a RIO Q '" -;.AI~3 00 TELEVIDEO 0 AI4 .... ;;; (.) c::::::J 0 o RS t.) c::::::J c::::::J ~9 ~ O~ A~10 ~ o g: CALIF, USA Cl0 : ~ ~A15~ COI~ A~I6 ~ ~ ~ '... R"i C9;;; co OCI4 A'D7 II C12C::::> R12c::5=l +r"\ C15 ~2 It CI3 A24 A26 A25 0 C19 A27 A28 9~ ~ 0 C20 '" ~ : ~ A C28 A35 0 C29 A38 0 ~ L C30 A37 0 ~ ~ ;;; I ;;; ;;; E28 C40 C41 M ~ 00 _ _ A53 03 A47 DO j ~ .... AM A55 R28 c::::::J n"'~ M8 M9 ASI A50 0452 C52 '" '"'" '"~ ~ I '"'" ~ '" '"'" '" 0 '" ,.'"'" 0 '" ,.'"'"'" '"'" '" A 13 ( ( (. ITEMI FIND NO. ~\L.~ OTY PER ASSY tJ2 C ZOw ::;) 2 f -N > > ~ ~ W ..2 I 3 t,? / 6 ,Rol./p US -()S7 7[3 7~/q. 1800000- 018 . Ie PROORRMED EPROM 7... 7 t,/-{}o/0 - IJ ::l.)t- IC 7~L5 37~ L 7~OO/O - /) :LS I (I 74t L~ 377 7 <9 I 9_ /0 2 2 I / /1 "2- R ,t-/c,tooo -023 If.? 2... 2- ~60oloo - 002- /S I /6 I C> 0,5 RlE-S c/ft Res C/F ~;( , Kn.. U5 U4 U2..~3 UI 74L50$ VOLTAGE REGULATOR RES SIP (PRC\() 10K ..n. R 51"l 000- 103 f?/;/~ooo - 211'-) ,.c 17(,L-o%-DoSR. G:>OOOO 0 - 00 I Ufo UfO PcPo3S ~'k<<:oR I.. 7~oOIO / 2 I .,,... Ie PROGRAMED ROM I74COC)/O -036 7C HICPolPRo / I s- REMARKS TITLE I DESCRIPTION I8COCoO - Op 9 / / PART NUMBERI REFERENCE DOCUMENT W VI RPc...3 ~w R'Z. RI, R3 S-% YStW ~ov C~,8 CJDV CIO 2- '2 PIP N rl' A ::;;..oN C q{) 0 lot) - OD-.S CA'P c/b 3~o\?-P .20% {",tt../ . 50 V C 6'00/00 - 0 0 / cAr R/L .1 3 C c?o 0/00 -t:J02 CAP c/p /0 k.n.. /1- IJ I IrAP Cl el'2. 17 /t/ 10 0,< soy' C"2-S,9,11,13 J 19 NOTES: /J, 0/ AI..f. 0 I o~ 804-&. /11 cRO.PI Al"J~,,,, Cf-~J 80 ENGRtG.. APPDr\.L ,*., J'.. U/1i 9-'">"'>::'0 9/; J ft,t; APPD{?'£)/J-ttl APPD KEY 2: :r T - w I- 02.0/ ~ ~ N >- w PART NUMBERI REFERENCE DOCUMENT REMARKS TITLE I DESCRIPTION ~ -2.0 :J-I 22. / / / I B80DD0.3 - 00 J 'D,c. Bl> A~ D .:13 ..2.~ ..2S- S3bO/OO - 00/ UIO»E' c.Rt ItJ 1/-00/ ~t I :27 ~ IV 2. DO (,?o!..- ()O 2- Cf 'PIN pLUer . P . , '1-:l3 -'Co APPD APPD f.l.. () /i.t ,tI~ 1/:''' t;(:1'%J1,1' 9kJ/o() APPD KEY 2: ENGR CHANGES 1...go DWNO(l",/:!t:".r.. REV CHG NO. DATE APPD TITLE TeleVldeo:'lnc. 1JART LiST ito TVI I /k::Cj eo/4f2f) SIZE SHT ..2 A OF~ BQOCO03-00 I REV BILL OF MAT'L NO. I .0 ( () ~-~-----~--------~----~----~------ - ~-~~ - - .... en -Y.e ZOw ITEMI FIND NO. ~ ::I >- ->- ~ ~ ~ W N W PART NUMBER I REFERENCE DOCUMENT REMARKS TITLE I DESCRIPTION 2. 2.. .2 L ARH. CHA 5$1 S II NOTES: APPLICATION NEXT ASSY I USED ON UNIT OF MEASURE: 01-EACH 02-INCH 03-FEET KEY 1: OWN -CHI{ O.lJ..~f" ... q·2J·El:: 0. ~.z{lfv,.. Ct_, ~..":" OS-AS REQ'D ENGR~:J~~~ '1--:2J-/{O 09-0THER APPD ' ... nol•• ) A-WITH BIM D-WITHOUT BIM R-REFERENCE S- SPECIFICATION O-OTHER( ••• not •• ) ENGR CHANGES AIltV RE. I ... H_G I nATII' I • I ADDn I TF!IF!VlrtF!n~ Inc. - - - - - - - J TITLE CUART rt aft T UI 1 () A.t: '~:3h APPD!2!IIJ1i11 rAJ/iO 4 APPD KEY 2: / t---+--I---+---I I - SIZE A L/~7 kG'! BDA RD / ISHT~IBILL OF IIAT'L NO. OF ..3 BQ00003-00 I REV o ( ( ITEMI FIND NO, OTY PER ASSY / SZ ~u..~ -N zow > ;:) 2 w ~3 ~2. 01 lIIC > W lIIC 5Z 3 3- 3· .2.. ~Z r: qlJPI"tJ ¥ I " .t6 I I 1 I ,1 I &>b I r.. 9~o/()o -00.3 I I I 7 - C 700100·· 00' Vl 1V/.7 IT} 3 PART NUMBER I REFERENCE DOCUMENT ICI·~sJ-lq, ~-33J35-3q,,: " 4 q.1)8~,.~b~-l7.L7-"': J w ~ -> N PART NUMBER I REFERENCE DOCUMENT w 2- .2.. .2. .:L .2- I 7~bOlo 1 7~o% I 7~OC)lo -i!',:J..O :2.3 I I I .4 4, 4 I7~~% ~~ lI- lY! f/- I7~ob10 - ~ .:20 :2.t .:l.2. - t) /jl - 0/9 - 0 2 / Ie 7~~t; /'<3 Ie It! 7~~< /6'6' 7~ L.~ /73 A3.4 A. 22..,Z3 AlB Ie 7~~> 17~ Alq,c.I,G:,IJ~4 0:2.3 Ie. A~5--~ "1 7~LS _~67 .2..t I ~ 2... ..2. 2- L 7~tJolO - O~S If' 7U t-<.. . .~ 7~ 7~/RJl I 7~~o/O - oJ..6 :2..7 ..2... :l. 2- I .:zi / / I I I I :29 I I :30 3/ 4 4 3L / ~S 3£ I ~7 / I I I I L 3<1- 3f I 7~60/l) - 0.2..7 , 7~polD -p~q Ie 7~/tP9 Ie I 71,t~olo -I'JSS It I 7~o% - 059 I 7~&'o// - Poo I~ I Z I I I / 3'· 3 ~ I I I f I 4 2.. /' ·33 A "2..4 A39,48 A40.51 A4"1 Ie 4 / REMARKS TITLE I DESCRIPTION ~ Z Z TIL //7 Ll-N.3J' . ASb .2.11" AL5 -'28} (150 "Sec.) Ie 6//6 PAN .2Y X AI 7~ooll 002- Ze 6S-{).2..A H/"-R/..)tP/ettJ~6S~L)R . 7~~LPII - /) 1/ 3 Ie 6S-~~ cRr I":LJA/T 7~poll - ~Dt,t- "Ie bS-~/ uARr 7~()OII- DD~ Y 6S-22.A I/. I.A A34- 37 A53 A S5 A49-5 \ A54 Al4 .:I 740010-·QbJ-=<.;· -Ie I..}ST'Z4Skj I7f"/-DO/O - ok6 Ie Klllq..A nl< ~~ur CRY~TAL 6S: 2.3·814 Mt-lt A41 5YS ROM ·2.33"2- (':-000 ') T8/)~ooo - ~ () I I lose, I NOTES: APPLICATION NEXT ASSY USED ON UNIT OF MEASURE: DWN 01-EACH 04-BULK CHK 02-INCH 05- AS REQ'D ENGR~ 03-FEET 09-0THER , ... not•• ) APPD KEY 1A-WITH BIM D- WITHOUT BI M R- REFERENCE S- SPECIFICATION 0- OTHER ( ••• not •• ) APPD ENGR CHANGES REV CHG NO. DATE APPD TITLE CCJAJ rROL 711z APPD KEY 2: TeleVldeo; Inc. 7ARTS ~/~T BoAR 0 q.1-o SIZE SHT~ BILL OF MAT'L NO. A OF ~ B~OOOO'2.-00 . REV I B4 (I ---.~ ....- - - . - ITEM/ FIND NO, !::LL~ OTY PER ASSY ~.3 OJ. ,,/ 39 ZOw ::l 2 ->- -N>- lit: lII: W IT ~t1£'tlt? I II I ! / / 0<2_ ~3 I I I I I f ~~ 2 2 2 cr/ ~2- t,.s PART NUMBER / REFERENCE DOCUMENT W /J/)H .:l53~ CUf?P~R 8ViE) A33 CJ()3 Y CHAR tfG-N .RON ..23 3 <. ('.La iu E-R RVTt==) .A'32 - C'/CJ 2.. Ie CHAR GF,rAv II Jot?ot'O r 800000 -00, I I I140010-010 I740010- 0 ,1 I R514000-015 R 514000- 018 Sys . ROM. 2332 Ie. ,4 LS 4'2 Ie.. IJE 555 RES. elF' 7t;O.Q V4W R32 ~w '/4W RI,~3 P~5 ~..Q.. <."'-~ RES 4-;1 I<. .. 50]0 Lf-J I I R !;'/~ooo R~<, 4-'1 2..71) , ~ - 0 () 2- ..a. .5'1 1 L r 2.0 2.0 2.C R~/tU)t)() - 005 £,z;.< ~ S"I t"e. &>1)(,) - bJ CJS- R.~ R s/~t)O() - ()o6 R~5 S2 55 5 1£ S/~OOO - !:J09 p~s ,$'3 s(t l l I I J I II< S/¢,O()O - 017 R~5 RES J-t' 4 4 4 s-t R6J4oo0 - 014 £S/~oo -I"&> 2. 2 !? S:-IUOOO - 12a-5 $-/o.fl... S-7 I RES 22. 50 :2- 2... 2.. I I R~/4000 02.'L - 02.4 _~~n ..(L ~/o.n.. An 5°10 ! J41 ~6 (,J.7 RES. 1142 I (EOoo) 5OJo '/4 W I r 1. Z z. Z. 1 1 -:"1 I REMARKS TITLE I DESCRIPTION s%' '~tU R '2.1,"2.'2. / 2<=1,31.35-37 R4 .~% ~w. ~X V~IJ. R'4l43 R·.34 'lh-:.:f4~-IO,'4 -20,Z3-2S,38 I k..{L ~ Y~tJ. 3·3K.n s% len.. 5% ~t.) ~w. R 11 / 2.8,3'1)45 , R 2~ .5% iL4 W RI2: RPI-4 R '2.1.30 /00 .r I..IJ !(,GS rPAe it: '. It.Q fL 12. \J . 5 '70 . 4" RI 1/4 W NOTES: I APPLICATION NEXT ASSY USED ON UNIT OF MEASURE: 01-EACH 04-BULK CHK 02-INCH 05- AS REO'D ENGR~ 03-FEET 09-0THER 'He not•• ) KEY 1: A-WITH BIM D-WITHOUT BIM R-REFERENCE S- SPECIFICATION O-OTHER( ••• not •• ) ENGR CHANGES DWN REV CHG NO. DATE TeleVldeo~lnc. APPD TITlE APPD APPD C.::?t1J rRtJL. TVZ APPD KEY 2: ?A1<.75 SIZE A SHT_j OF _ _ I i-/5> T BCJAR.D 9.i-o BILL OF MAT'l NO. RfV BqOOOO'2. - 00 I 84 (I (: ITEMI FIND NO. OTY --.-_.....-~_.....-----,I 77 II J I r .R 11!7 1"1 ~ ('II 0 - IL. C ::;) :I ZOW ~ ~ ~ ~ ~ PART NUMBER 1 REFERENCE DOCUMENT Rc -404 73.T . .. I 7{E.\.~ ._ 4.'.J';. Mt0 0 30/- 002.IIG S05:!KET J!L REMARKS TITlE 1 DESCRIPTION ~ W 5 C1J~ 2.4- RIM5 R~'13 ·:1/4 H~2-34 0~ I -.r c ~ocxr;T ;&·2.1tUS.. 37.-4:-6.-4'l..,5Z . .~ ,~1915- 1M :L 0 0 ~o t - cf/ ~1313 H..::LOb~O' <13 <.1"2...1<" a~ 2.12J~ gf- t I rl t CDNNE-~TOR RS:2..~2.. RIA. I P'3,4 H..:loo601-DD~1 PLUIir ~. PINS I PZ.5 tL."J.OO ;?:O'-'Q.t;> II R1 II l1k+.iALe-' K€-Y 8l)ARD CMuN~croR.. S-.:LD ~I ." I) -oosl J:c. Sact<&"T A¥J.-51 A 53 - 55 ~oPJrv~ -~:l- _£6 I I '-1 ~ . h ! H.200:l..01 -DOli 13 13 }../\l.OOf,Ol-OOJ I -PLUGc...PINS· ~'lOO 100 - OOl. I TRA'-JS. -"2 .PI I P9 - ! PAO· LARGE 01.2 .4 ~J tJ:j :b __qL ···4~ q3 111'1.t' NOTES: APPLICATION NEXT ASSY USED ON UNIT OF MEASURE: 01-EACH 04-BUlK 02-INCH 05-AS REO'D?)'tY1. 03-FEET 09-0THER , ... not•• ) KEY1: t-----+---~I t-----+---~ OWN A-WITH 81M 0- WITHOUT BI M R- REFERENCE S-SPECIFICATION O-OTHER{ ••• not •• ) CHK ::: APP.D APPD KEY 2: ENGR CHANGES REV CHG NO. DATE TeleVldeo;lnc. APPD J tf>A£ IS t.-/ ~ 7 .0 CcJt1J r/?IJL !5~AI'\..P n7 ~"lJ ~ Tv I TITLE SIZE A , ISHT~IBlll OF MATl NO. of--LIBQOOODZ-OOI REV ~l~ ( ( - -------------~--- ITEM! FIND NO. I OTY PER A~t: u.. ~I ZOw I J 2 b3~ !': > ~ N > ~ PART NUMBER! REFERENCE DOCUMENT REMARKS TITLE! DESCRIPTION ~ sr 60 61 /2 63 t'~_ (r +1~12. 66 II II I / 1/ 1/ ,.5<~.(-O/O() - DOO I ;;..# :l~/'9 ,s :~..:ffL/,() 0 -00 2. I ::LA.! ~FJ I q 5350100-003 I 2A.J ZCf07A 41414 SJ60/00 ~ 000 IIAI 67 Q T R AAI..s I 5. T/2/? TRAN51<' 1,4 02 03 T{)~ TRAIJ515 TOR :61 6~l 7 IJ Ib 3CO/bO -~t:) I /11/ ~"(J I III111 71 q/¥ D'nb~ / OJ -4 D,S J)/I') 7),t:;. . 72. 1..)..J2..1 ~ 73 H2.ooJPl y ~- 0 0 ~ D>~p...<. r.(? I T~ H u •• 10 P_QSa..,_. 5 \ ,'2. .s I D,;. . 7f 7'- NOTES: APPLICATION NEXT ASSY USED ON UNIT OF MEASURE: DWN 01-EACH Q4-BULK CHK 02-INCH 05-AS REO'D ENGR~ 03-FEET 09-0THER APPD , ... not..) APPD KEY 1: A-WITH B/M APPD - DBI R M ENC KEY R WITHOUT -REFE E2· · S- SPECIFICATION O-OTHER( ••• not••) REV ~eleVldeo®lnc ENGR CHANGES CHG NO. DATE APPD rlJA Rr r'l TITLE _ I . . , . t.-/~ 7 I AO£) CtJN Tf(~ t, & rrl'. 7 l/ I '-9 SO SIZE A I ~JBILL SHT OF __ OF MAT'L NO. B90000Z - 00 I REV 84 (1 ( (i -- --- -.~----------.-- --_._--- - - - - - 8 7 4 5 6 1 2 3 ~l D ~I r---- ---- ---- ---- --- -- ----I I I I I I no ill I I I I S - I I I -oot. I I \ - \ PIO PII T. ~ P'-I pn PI!. II U A • D • ..q TI Pili I CTRL. ! ~1 Po . . . . . . . P"'~ J ~,- . +rtvl v.. Rll v•• AU 1>0 01 ". p,., t.O ~ ...... O~ v •• D4 OS DO. tL.~ 0' 10K ........ LINE liP!. +511 ~ • ~1.+5VI I1P !. RP!.l toK 101. 10K 7 ." ",.. '.* UOT• .,:·UUL,US OT....W . . . . .ClF1£D 1: LlW(. IIU£tt a w l % D P [ :t TAB F G H • .0 " TAlI 7. ,< "! "r .. I. I , , 1lCUE1 ........ ~ foe F. TO •• . .," IIPI U PI. P,-!. ," 10IC ps a•• . SP ., _It .PACE T " I I " " , 58 I I 8 u ........., I I l:"l~~ I- Pl. I I I I I (a<»5~n EA * I I ·c_., I .. ' 1. J Ulo -001 I I XTAU 1:: 10K I' l.\ '.- r flIPS, 1114 10K ruin I c . ~l I D - - - --- --- --------- --.iV -- n '5 1: F. '10 .....T I.tlEAK ill YEII.IOU ·00. A..O '001. [i) VERSION 000!. I!l CIIlCUITRT _LV OPTIO&.IAL II :l C .[] 8 L'Na FUll " c v DEL .. • ~ I~l una F1 '8 I L'__ ~~~ ----, .• B UI 14LSU,' II ALE n. ~ IS .!!.! I. ~ 15 e1 I.. ~~"'1. ~ " I. ~ I.. .!!.!.. WI[ L ____________ - - - ________________________________________________________ _ A , --a ~ ~ '1, ....... =. . A e~ K£YIICMRD ..50 1CiJ::i:[,,_--, I·" 1 7 1 6 I 5 i 4 I 3 I· 2 I 1 .. I :.- L I n ~ I. ,. r I 1 I ,- 9 ~ a i °.. 0,. -1 .... .. . I \ ~ ! g~ \ i ~ ~ 0 ~ f- ..., .... r ::: :: l s 5 I 'Ul .. ; 9l!S2a2~a. ::; , iii J: ;I = 15 ~ • - J ... . i~ /: =.. ~... • t 11: f0o- ~~~5 ~e: 'I~& '" ---------- , !;Ii - - ----- -'------------------ :- • ~ •1 '" 51" .... l- :- I 8 UI :a , !l J iii 51 I g '1 .1J: e&.. -I ~ 9' 1= i ' - - -- - - ---------- - . .. . .. J s"~ i I: .. • ~ ... S UI e !l !l t ~ , ;j L_____ ;:I 2 'n-:,~ ~ ~2~ I- ( , '1 ------- J -- --- ... ... r-1"'- - - • • ..9l I5E ·1 '" I .- I I I i ro- ~ N I I I ---, • 15 ..IlIr .B'" ::I 11 iJ 1 f S t 011 ... .. = .. r • . ~ I . ~ ;I 15 ii .J: I I ~- '" .I " .L.. ~ ~ J ~ R§ ~ '1 011 r ... • I , J I !I = -II .rtln ~ f'. iii" .... ,.- B I! c L. _____________________ J [! -- =lie: 11- !d!-, ;I .. .. .. . O . .. . . 9 II iii 2 S 2~'!.c" ;. . ~ 11 I - - - - - - - ---- - N ~ .- f-- .IJI e je I .... - g - I-i :.- I I I .. _. T n I ~ I- (,~) E\SIEI1E,5 . 9- 74L'3o!~4L.S~t .. oz. Et, R2.4 ~ 1~ E 1"\ I A(.3 "74LSS'l. ~ VO'4t;;, I ~YI'tZ. . , V3 n • • I 20 7s< B~~ ~ . 1.q.L5~'l. - ~ c.s/AII I ~ II I ' 5 r- III goo '9- cr 4: c( III r- ..9 ...... 4: '" A'S t A" , A' Vee 1ft « « '" '" 2. , 4 _ G"'D lie. cs AI At. • : II .... 0 1Jcc.' '7 :~ " (S q 10 II 13 14 15 I'- 11 ., tz 2.3 I ..SV t.4 A42. 0 REVISIONS In II l'If./'Z~3'Z. "" 1"'1 0 0 1'Z.)A5S~'~. IS I ~ E2.1 tol I~I "5V:' l4 "lloO mfES 18 _ Nco'! l. ~ :~5'IJ IEM p- ~ ... A"9 5 ~ --. 1. 'Z 4 ___ I u n E2.0 lONE l 'll I q I/Ot'O A2 TJt;:P." 11 ~ zm : : " t/Of. IS tlOl ". t}oe 11 ~A8 -5V I. l' R30 IiUi SH ~Aq ~AIO -5. II ~ 5Hl,'5,' AS! 5N1.,o:.,1 ~ 5 SH" ABt/J ~ AB5 ...., AS," SH Z ~ ABa AS,., ABI¢> ABH A5~ tio50ZA SHZ,5 5142,,5 ~ AS" s ... ~O ".BoI SfoI , oJW 51< , OAf . 2,4 RA2. RS tt . 1-0 AI.-5' RA., R/w RA4JSTB u.o> A55 CD545 MAl ~../74LS!l'l. ..... 4 5H I 1~ .DB~ . 084 Das DB" 0,," 10 5H I 51< , 11>. vs'" '8 D~PL.eUA ,. GURSOR ~H "." 51< • 5H ... "* ~ ~ f,:- T 5 ~ B ~ " 30 OS2DB. 2.9 OM .....a Z8 085 LU" 2."1 DB" MAil .... MAIO "B 2S '4 ~ '" IA." ~ I" .;,' ~t r • ~/ )A'" " fO:"'P.'S'EL 51< , 40 ....A' 1.6 DEn '4L5'!2. "S'" ...-.. .. ,"". ..... " DS¢ !t 081 0'" ,. ECl.l 64 , . . A. '0• ..... t..\A2. It DB. Lta v" A'" AB. ABO A84 AS'S AB'" A8' ""'AB. A.... ABOO un +5V ;-- ~ ABIl AS" ~ .1L~, •• . . •• , I" ...... I·'······ , I"" .... ~ I.... ·.. ·~ oas 2.15 II a. IO.I!I - "" A4r. '"".... '4LSI~ t~~~ 5H" 5EL..cPU.ADDR. 41' '1" 'K " .... - E~ ..... '5 ~ 5~L _ !.~ g5!i . ~ ~ (01 'It- _ A45 '4L515' _ I - ~ ~ ~ ~ .... 1 q It q It I~a ~~ ., ~ j D 2 .... H iacio " .. . . ... .,I :i .-- "" ,. 15 , ~L " '013 /I 14- 1ft'"EU - "' ... - ..44 '4L$IS' -=- ~ l\, ~ .;: .... l " I " "" - _ - SEL "' .. ~~ ii . ... DO ~i .'" '---,-' Of '" .... - "" 1ft , ...t\in ?:~~~ .. ~ ,-=15 EU sa. 4 ,. ., It .. 1 ell It :I .. I a 5 II 14 15 -"9 j ./ Ha 00 " :I c .. ~ ~ .iii '----y---' I I -----. ......-.-_.. --.• , I, I, I, -- e1ill&Vlclec(K COIJTROL 8D· 't50 "J:::Hi'Goool-aool .. ......... ., ~ 74L54t. SH ~ 5. ~ ~H .. ~H ~ l!t AD·RA ..... II 15 "A 0 ~ •• '• •.~ , AD.RAM·It. .,~ ac..c:.L1<. 0 " - E.C.N 14 ~ .. · c. AQR.AM '''I ;;;;;0;;;;;- Sr-... lUS')! ~ '" AIr. ~ '0 .. AS ~J A,S>8 ""l4L5'!tl '1-LS04 - AD. RAM· 10 5HZ. AD·RAM·" AD.RAU·e AD.RAM.' AO.RAU·c;. AD.RA""·5 AD·RAJ"A·4 AD-RA.... ·' AD·RAU·!' AD-RA ...... ! .i AD.RAU.c6 -t 51" I, WSggg . .5Y I 4 3, '5 t I 11 '" c :: I/:c ~ III ; !II :I ~ Vee. to At5 "§' 2.114 ... It GND " +t ]5 .. I, •• 8 Vc.c. 11 10 18 5""'" n ... " i~:C~;~:!;=~ s At' ~U4 W ~,{ DB." D8-$ DB·. DB·' DB·Z DB./ DB-.,. ~. t OM' DMEN.EN R/W , , - .. 11.81 111 '0 Ala B"'AI4 At. 1 .... B\tto(' .. IS, B4 4 I . as I' 82. !!I All. 3 B d ll I.~t ,. GND 14 D~ oa·' "5"~ I.l g8§ g = "'" 5H .. W 13 1, II '" . It 81, .. 5 • • t , t +5V .. tt ,. t'c~~:t~;I!;(i~clll "'. .,. "B ~ 21 WE. "II'" <5E' 20 ~ i 011, GU ~ § +1 15 "5 Ate. %.114 g r .~ t , " ... ,ei<~~~~~!C:" 2.4 .g~.ag.§~.Qg~ II +5V ct SGt14!.tlnl'-'5 ~O_N!II::!~:I"''''' 18 4: c C C C ~ r"!. ""'t AtS Vee 10 - 2.\14 g g 8 g 14 S N '" IS .. ''tlll GND 1011 "1415''''1 ~ +SV f!. .55 Yo< WIt: CIt CH:AD" eM.AD." eN·AD·! CIol·AD·4 CH·AD·. CH·AD·2. CH.AD·' CM-AD-IP A1C. """ CS "".. .Q. 10 t"" 11 ,~ '4 1'14 15 '" 151~ lC." It I t ., ..... rW{ """ ':' 0 ., 18 c; p: !5E~ .g % % .Q..Q. r-".a~~""''' = 21 Vee. .. WE CI1011 tt ret . <'":;3 ~~g~,§g~~ 8 ' '" 5 4 ,. !. , t5 -~lc~~S:i:l!Ctft 8 P: ,I_ 8' .... , . , ... ~c:.!~~~ I '511t.ln ":" 'tt .. z.4'c:t:l~!Q:I!C~'t 18 V.. "BI>- A" -~~ ~~.Q~.Q~~8" 1" - q -'0 II - .. -'0 I-::r=.. e_~_'1. "E=..... J -"l" ' CWo eot.I1WlL 10 '110 _II 1,." " ! ::_,~ CH· .... _ eM· ~~:~ SH 3 CH· ~ \ CH ~~.~ ~ 14 r -'-'cP ~ 0" BS ~b ~I AbO CP ~ts!'4 q H .. ,:,1=,...... ,H .. 40 4Q '4l'3lqo, 0'5 ~ 02. Q5 15 Q'l. 1 15 00 I 01 4 01 0p Q1 5 GriZ. lOOt 3 ~ ~~8 .~v SWIFT. elK ~ DC CARRY ~- ".... I ,.1 AI> ., : 14L'500 r RC. ~ : E5 :: U 04 ;; :~ 05 15 .; ~ c~ _ f <:. 'it Cf.I·-.. ''!O '.' Ir I A4 f B a~PP ~ JV~~y I 01~ . "l4LSOb 08 ,"" I I I I '--_+__+-=1S~ ~ "T4LSo04 SHIFT. eLK. ::: ~ ,a tit IIIIII LC?k'4lS04 ~~~~V~DEO BLlJJK OISPl.BlA BLAt.JK. .DEL.DISPL-.EN5T". '---, r SH " HALF. tIlTEIl'ITY t3 ... v SH.. vsv"c (Y5~l)1 '5 IIII "15 ROW.CIJ SWOo Dr3PL·BJ- a~ "lIT."" __ .:'":"'__ __ o.~ _ ..c..-.... 5W4 • ~Inc. COLITROL aD. "we> l~ ~ ~ 7 8 5 6 t 'H .. XTALI ~,= ~ R/w -< 5" r. 18 OBI ;, DSt. ~~ OB5 2.2. DB4t3 DBS De~ 2.4 DB' !~ DB' . . " II! 1I11111111111 S '3 ,t. '5V « n ~ Ob'+sv EI1 glE.IZ EIO EI3 ~ Q ;:. ~ .'V .. ,.,,,>< -" ". "07 .5V iii t iii ~or aJ '" ~ D ... !t30.n,. ~ ,~~ fU ~ P1-1 P1-Z SPI 330 C". 330 Pf PF .I f1 r----- 6 T I U·~·D'UF ..0 GilD 14L'53"" 10 ~ po •• .~x=: t17 ."" PO ... l~~PF . • E. El +sv EB '0 PO-, PI-I PI-2 PI-4 R'21,510.n I/'ZW '2. 14lSOS 5+ ,n C4,l 3~~~F 13;~SPF £CIJ r : ~ ,,~ DESCRIPTION ZONEILlJt l. '3'30 PF ~Ir ,. IOJ el ~ V '" ~Dlm OBf<> ~" 1)5 SH , on t- ~~ ~ .'0 y ~~ cr.. ~ c REVISIONS ., : ~ 1 2 3 ., ., .. ~ ;i: s !. " ~ ~A5~~~ _ _ IKe., L _(., I l ~ '" +5V :~~ A4'> G:.551 D~I DB4 is '5V oed> DB" r; a: o ll'fW il ~~ DBz. ~ y y oJ 28 RSI -U.J [O.P.5EL t c ~~~ ASq 5H I y,. XL' ~ ~, .~ .. on 1'5V I" ~ D .4 .. II P .... c R'30 5IOAt/'lW P3-14 " ~-Il ~ PE.-2. P!-Z C., ?~o ~:~ PF ~ ~:~ P4-S 2.2. OB4 """"" "'0 "" A50 &.55"1 23 DBS 24 DB'" P4-3 25 DB' '--~ ~~ B .2 aTR P'3-'2.Q RESET B CTS 5. , P4-~ Rn P3-4 05R P4-r. C4.'t 330 PF 5H , ASIC Pi-IO 1 P3-1Z A P3-Z4 IUDI "0"1. I -r-IE>q CTS r--;'~';::;-i AS! D' I A~4'5 "''1,.1 : .~_~ 0;- _ •.J AIO 74010 E31 ''!is I '5V 'trv ... ~ 3.3K RU. -=- .33,".4 ~ .. .54 SlO~ A~- R31 StK. 4.1" ...12.JA!B~ --"'-8 7 6 5 I,! 4 3 ".., : ,.02:l : _If ...... _011 .... ~ ....III_o. '00 .... P3-1 PROT· Gli. TIDI " . R3t. P4-1 PR01'· GNO ); -'s w~.a,. - P3-' SIG.G~D O ...~_~NE2i1~.tb4"~'4I r _ I SIG. GNO I, ! t·! 2 (TTY) 1- e P3-15 P3-13 A "I8II¥IcIec(1nc. COliTROL BD· qSO ~ '-' ~ REVISIONS 51< 2 S.2 S" , 5" ~ """""""EQJ 81 RA¢> RA3 8l.ACK'.OJ,J·WHITE .(a.C.W) ~. 5H • '4LSOO 4 SLltJl<. 54 BLI.·RATE SIl' BLAlJl. OOTS.SER.lAL I : . .... . : : +llV PEl-I ROW·q UJJDERLINE 5... DEL CURSOR 5, REVERSE VIDEO .. )) Al . t4-LSOO .5V • AIO ,40<. HALF·urrEN!iITV ~VV~ • AIO '40," ~ORCE· AlO ~ SH' .... EI Et1 '40~ VS"-' -5iW-i:iEij 'l.f'~ H'f,J 14L~ec. 01 04 '2.'04 11J~f4. E. 04 . . , - ....-q -ltV ?"'-5 QI 2JJ'Z."Z.ICI! I. C~ R8 PG.-B Pl.-4 GoB .... II< pz-, S. 4 COUP.V+"TL VIDEO ~ PZ·'" •VlYt.lC (vs;;O ~ II< • ...SV ....C. L·crJu·Al561 .sv PG.-' T4.' .. '40"" SH I ~-IO : Gf,JO f ~~ I 150n. II< ~ SLAWK SH' S. ., Un. '4LS8c.. DEL O~PL'EfoJ - POo-I4 ·sv 15 Pt-, ~ Pl-I SH 2 DC.CARRV SH .. c.cu:c s. 2 SH 4 DC,CARRY c.EiJ( 5H ~ 13 51< I .11 I 14l!3!. ltV" I AS"· t-----------------------~3~8 -'4lSC)4. +5V~'-'..-,--"1'~,_, , I "'~ RESE-r C4. SH '.~.' ~.Ol'" o ~. SHIFT·C,LK XTALI ~ ~ 5. I s. ~ •• 4 5.5 5.5 .~ ......... w;;;;;;;;;;-- ., ZONE I LlII E"'" BlI· RATE FORCE' II!SI..AJ.lK •• v .5V 1, ~ .~-f. ." ~ 5 ,. £!!!. ~ ..... OB4 -i 5H I DB' GNP r' DBI/> ~ Z. ~ ,H , I I ~ 5 IilLACK·OW·WH ITII! (BOW) 5H '" IIII GIla,. IV 'tV '3V I: GoA It. !SA 4A I0 I" • o-ll-. : ~ '2. 8 o-!.L "'"S"t a----. I ~ ~ '"A 1't 10 0-- I 10 ~ ~" 10 A"," 3A " ","V74L5".,4A1I II 5Y 2A1 l .5V fiQ 13 r.V ~JA . I .. 2 5 ' Go : : 11. 5 1!I"y .1 ~ :IT: ~ Z ~ I 5 1 '" 2. '4 '" 8 +SV RP" RE5,·I'" , 51312.1 ...... --="SV RE!t· IK Ii'fir ~ ..z.V" PS .. I .. I'Z..V -= W PS·4 .01.....f ~~T-~--~~~~--~----~--~--~ .. GI J,- PR 10 c.., 1.2....1 ~IO GND SH .. I----yCLK ilL +.V Cil t'2...J PS"'3 ~ ; ~~ IA Z. T& "' c:reLK. ~ ~ l:TGtI. ~~ "~ NO. o-!!- , " : :~14~:;":: ;.0 H.'" q SM5 ~ ROO ... p,... o-ll-, ..MI". ct ,SH Z. oJ-!- 4 !II IIIIII .r:JCJ. ~ i~y 5" 5 ~ BI.DIR.E...." -;:a;;u SH • OUT 5PE'AKE'R IA "1"& A81'3 .. , " Is ~ 6' ! .. 1 ...stt ia..,.L s. , Gt ~,-y J3. SN , " J 3Y~ ~ :~~~~~: - ..!
Source Exif Data:File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Modify Date : 2014:01:31 14:59:22-08:00 Create Date : 2014:01:31 14:20:59-08:00 Metadata Date : 2014:01:31 14:59:22-08:00 Format : application/pdf Document ID : uuid:8fe4241c-772b-ec46-ae49-139928695e52 Instance ID : uuid:50ec74c2-94b7-0941-8630-a23cdf154794 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Page Layout : SinglePage Page Count : 88EXIF Metadata provided by EXIF.tools