_950_Terminal_Theory_of_Operation_26Jan1981 950 Terminal Theory Of Operation 26Jan1981
_950_Terminal_Theory_of_Operation_26Jan1981 _950_Terminal_Theory_of_Operation_26Jan1981
User Manual: _950_Terminal_Theory_of_Operation_26Jan1981
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950 Theory of Operation
CPU, Timing and Control
(Refer to Figure 1) The 23.814 Mhz oscillator (Osc 1) is used
to generate all timing for the terminal.
It is used directly
as the dot clock (Shift Clock), divided by 13 to drive the UARTs,
and divided by 14 (1.701 Mhz) to.drive the CRT controller (CCLK)
and the CPU (via the clock stretch circuit).
The clock stretch circuit is capable, upon command, of generating
clock periods twice the normal length (588 ns versus 1175 ns) for
accessing slow memory or peripheral devices.
Its output drives
the 10 input of the 6502 CPU. The CPU then outputs 12, which
controls the timing of the CPU bus.
12 is a slightly delayed
ver.sion of 1 0 •
The result of these circuits are 12 and CCLK, two signals of
identical frequency but opposite phase, (except during clock
stretched cycles). The importance of this will be made clear
later in our discussion of the display controller.
The CPU fetches its program from the ROMs (Read Only Memory)
A41-43.
It uses the 6522 (A54) to sense switches Sl and S2 and
to generate control signals for the test of the terminal.
Display Controller
(Refer to Figure 2)
Timer T2, part of the 6522, and the 6545
(A55) are used to generate the memory address, in Display RAM,
of each character as it is about to be displayed, and the
horizontal and vertical synchronization pulses necessary to control the deflection circuits of the monitor.
Timer T2 is used to count horizontal scan lines and interrupt
the processor (via NMI) when a specified number of scans has
occurred. The processor then loads the memory address of the
next data row into the CRT Controller and "sets" this address by
generating a carefully-timed reset to the 6545.
At this same time the processor loads a 4 bit value into latch,
A61. At the time of the CRT reset this value is transferred to
counter A60 and becomes the Row Address of the next data row.
This value is then incremented by each horizontal sync pulse until
the start of the next data row when it is again preset to a value
determined by the CPU.
The CPU and the display controller share access to the System and
Display RAM (Random Access Memory).
This is done during alternate
phases of the 12 clock. During the positive portion of 12 the CPU
address may be gated onto the RAM address bus by Multiplexers
A43-46, and bidirectional transceiver A14 is enabled to pass data
between the CPU data bus and the RAM data bus.
During the negative portion of 12 the 6545 address bus is gated
onto the RAM address bus allowing the video data to be latched
by A24 and held for the display generator.
This alternating access or "interleaved" access allows the
processor to operate at normal-speed, without wai't_s of any kind,
yet prevents degradation of the display quality that could be
caused by inadvertant appropriation of the display bus by the
processor to access data.
The only penalty for this scheme is the necessity for fast RAM
(150 ns or faster).
Video Generation
(Refer to Figure 3) This Display Data and the Row Address (or
scan address) are used to obtain the dots for the next character
to be displayed from the character generator ROMs A32 and A33.
These dots are then fed in parallel to shift registers A22 and A23
and emerge serially as raw video.
Additionally, bits 0-3 of Display data and bit 7 of A33 are
combined to generate the attribute signals Underline, Blink, Blank,
and Reverse. ICs A19, 20, 21 and 30 latdhand delay the decoded
attributes from the previous data row for carry-over into the next.
Bit 6 of A33 controls the intensity of the character to be displayed.
~
Gates AI, 2, 10 and 11 are used to modify the raw video to the
proper intensity and polarity, and gate it on or off in response
to the attribute signals and control signals BOW (used to reverse
the entire display), cursor, BLI-RATE (used to blink the video)
and FORCE BLANK (used to blank the entire screen).
Transistor Ql is used to dr.ive the video to the proper voltage
and current levels to drive the video module and/or an external
mon.itor (using the composite video jumpers) .
I/O Circuits
(Refer to Figure 4) UART A49 is used to receive (and optionally
transmit) serial data from (and to) the keyboard. The transmit
path to the keyboard is normally used to conduct the bell tone from
the 6522 (via driver Q4) to the speaker in the keybo~rd.
UARTs A50 (Main Port, P3) and A5l (Printer Port, P4) are used to
send and receive ser ial data from P·3 and P4 via the dr ivers,
receivers and switching circuits A39, 40, 47, 48, 56, 57, 58 and 59.
The UARTs A49, 50 and A5l (655ls) are connected to the CPU Bus
and generate IRQ interrrupts when commanded by the CPU to send or
receive data. Additionally these parts contain internal baud
rate generators that must be programmed by the CPU to control the
baud rates.
(".
General Debugging Guidelines
The following procedures are usually 90ne when there is no
initial beep at turn on. To debug any microprocessor without an emulator, remove as mahy devices as possible from the
bus •. This includes the CPU, CRT controller, VIA, UARTs, and
Program, User, and Character Generator ROMs. The address and
data lines can then be checked for proper operation.
Field component failures will generally be the most complicated
integrated circuits. In case of a failure of this type, first
replace any of the socketed components associated with the
failure symptoms. Should the problem persist, check the RAM,
RS232 components, bus transceiver, and multiplexers. This
failure group is the most difficult to troubleshoot. An
effective way to check the RAM is to use a test wire with two
clips. Connect one end to the R4/Dl junction in the video
section of the logic and the other end touching the outputs
of the RAM. This, in essence, uses the monitor as a scope.
Compare the response on the screen with a good terminal, and
using this method, a faulty terminal can be debugged quickly.
Should the problem not be found in the second f~jlure group,
a simple hard failure in any area could be the cause of the
problem.
.
1/26/81
(
PART NUMBER
DOCUMENT NO. 29000 039
REV. 3, FEBRUARY 1979
'1'
Rockwell
R650X and R651X
R6500 Microcomputer System
DATA SHEET
R6500 MICROPROCESSORS (CPU's)
SYSTEM ABSTRACT
FEATURES
The S-bit R6500 microcomputer system is produced with NChannel, Silicon Gate technology. Its performance speeds are
This innovative
enhanced by advanced system architecture.
architecture results in smaller chips - the semiconductor threshold
to cost-effectivity. System cost-effectivity is further enhanced by
providing a family of 10 software-compatible microprocessor
(CPU) devices, described in this document. Rockwell also provides memory and microcomputer system ... as well as low-cost
design aids and documentation.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
R6500 MICROPROCESSOR (CPU) CONCEPT
Ten CPU devices are available.
All are software-compatible.
They provide options of addressable memory, interrupt input,
on-chip clock oscillators and drivers.
All are -b'us-compatible
with earlier generation microprocessors like the M6S00 devices.
The family includes six microprocessors with on-board clock
oscillators and drivers and four microprocessors driven by external
clocks. The on-chip clock versions are aimed at high performance,
low cost applications where single phase inputs, crystal or RC
inputs provide the time base. The external clock versions are
geared for multiprocessor system applications where maximum
timing control is mandatory. All R6500 microprocessors are
also available in a variety of packaging (ceramic and plastic),
operating frequency (1 MHz and 2 MHz) and temperature (commercial, industrial and military) versions.
MEMBERS OF THE R6500 MICROPROCESSOR
(CPU) FAMILY
•
•
Single +5V supply
N channel, silicon gate, depletion load technology
Eight bit parallel processing
56 InstrUctions
Decimal and binary arithmetic
Thirteen addressing modes
True indexing capability
Programmable stack pointer
Variable length stack
Interrupt capabil ity
Non-maskable interrupt
Use with any type of speed memory
S-bit Bidirectional Data Bus
Addressable memory range of up to 65K bytes
"Ready" input
Direct Memory Access capability
Bus compatible with M6S00
1 MHz and 2 MHz operation
Choice of external or on-chip clocks
On·the-chip clock options
External single clock input
- RC time base input
- Crystal time base input
Commercial, industrial and military temperature versions
Pi'peline architecture
Ordering Information
Order Number:
R65XX __ _
Microprocessors with On-Chip Clock Oscillator
Model
R6502
R6503
R6504
R6505
R6506
R6507
Addressable Memory
65K
41<
SK
4K
4K
SK
Bytes
Bytes
Bytes
Bytes
Bytes
Bytes
lTemperature Range:
No suffix = OOC to +700 C
E = -40 oC to +S50 C
(I ndustriall
MT = -550 C to +1250 C
(Military)
M =
MIL.sTD~3,
Class B
Package:
Microprocessors with External Two Phase Clock Output
Model
R6512
R6513
R6514
R6515
Addressable Memory
65K
4K
SK
4K
Bytes
Bytes
Bytes
Bytes
C = Ceramic;
P = Pla~
(Not AVaible for
M 'or MT suffix)
Ff'8t/uency Range:
No suffix = 1 MHz
A = 2 MHz
Model Designator:
XX = 02,03,04, ... 15
NOTE: Contact your local Rockwell Representative
concerning availability.
SpeclflCiition. tubJect to
@
Rockwell International Corporation 1979
All Rights Reserved
Printed in U.S.A.
change without notice
R6600 Signal Description
Clocks (41 1 , 41 2 )
Non-Maskable Interrupt (liI1l1l.
The R651X requires a two phase non-overhipping clock that runs
at the V CC voltage level.
A negative going edge on this input requests that a non-rnaskable
interrupt sequence be generated within the microprocessor.
The R650X clocks are suPPlied with ali internal clock generator.
The frequency of these clocks is externally controlled.
IiiMi is an unconditional interrupt. Following completion of the
current instruction, the sequence of operations defined for i'fiQ .
will be performed, regardless of the state interrupt mask flag. The
vector address loaded into the progrlilm counter, low and high, are
locations fFFA and FFFB respectively, thereby transferring pro·
gram·.control to the memory vector located at these addresses.
The instructions loaded at these locetions cause the microproc·
essor to branch to a non-rnaskable interrupt routine in memory.
Add,.. BUI (AO...A15)
These outputs are TTL compatible. capable of driving one standard
TTL load and 130 pF.
Data BUI (00·1)7)
Eight pins are used for the data bus. This is a bidirectional bus.
transferring data to and from the device end peripherals. The out·
puts are trioState buffers capable of driving one standard TTL load
and 130pF.
Data BUI Enable (DBEt
This TTL compatible input allows external control of the trioState
data output buffers and will enable the microprocessor bus driver
when in the high state. In normal operation DBE would be driven
by the phase ~ (41 2 ) clock. thus allowing data output from
microprocessor only during 41 • During the read cycle. the data
bus drivers are internally disa~ed. becoming .essentially an. open
circuit. To disable data bus drivers externally.DBE should be held
low.
Ready (ROY)
This input signal allows the user to halt or single cycle the microprocessor on all cycles except write cycles. A negative transition
•to the low state during or coincident with phase one (41,) will halt
the microprocessor with the output address lines reflecting the
current address being fetChed. If Ready is low during a write
cycle, it is ignored until the foUowing read operation. This condition will remain through a subsequent phase two (412) in which
the Ready signal is low. This feature allows microprocessor inter·
facing with the low speed PROMs as well as fast (max. 2 cycle)
Direct Memory Access (DMA).
Interrupt Request IIRQ)
This TTL level input requests that an interrupt sequence begin
within the microprocessor. The microprocessor will complete the
current instruction being executed before recognizing the request.
At that time, the interrupt mask bit in the Status Code Register
will be examined. If the interrupt mask flag is not set, the microprocessor will begin an interrupt sequence. The Program Counter
and Processor Status Register are stored in the stack. The micro·
processor will then set the interrupt mask flag high so that no fur·
ther interrupts may occur. At the end of this cycle, the program
counter low will be loaded from address FFFE, and program
counter high from location FFFF. therefore transferring program
control to the memory vector located at these addresses. The
RDY signal must be in the high state for any interrupt to be rec·
ognized. A 3KO external resistor should be used for proper
wire-OR operation.
NMI 'also requires an external 3K
wire·OR operations.
n regis.ter tc:>
(,
V CC for proper
Inputs iRO and NMI are hardware interrupts,lines that are sam.
pled during 412 (phase 2) and will begin the eppropriate interrupt
routine on the 41, (phase ,) following the completion of the cur·
rent instruction.
Set 0vrrflow Flag (5.0.)
A neg~tive going edge on this input sets the overflow bit in the
Status Code Register. This Signal is sampled on the trailing edge of
411 and must be externally synchronized.
SYNC
This output line is provided to identify those cycles in which the
microprocessor is doing an OPCODE fetch. The SYNC line goes
high during 41, of an OP CODE fetch and stays high for the
remainder of that cycle. If the RDY line is pulled low during the
41, clock pulse in which SYNC went high, the processor will stop
in its current state and will remain. in the state until the RDY line
goes high. In this manner, the SYNC signal can be used to control
RDY to cause Single instruction execution.
(
Reset
This input is used to reset or start the microprocessor from a
power down condition. During the time that this line is held low,
writing to or from the microprocessor is inhibited. When a posi·
tive edge is detected on the input. the microprocessor will imme·
diately begin the reset sequence.
After a system initialization time of six clock'cycles, the mask
interrupt flag will be set and the microprocessor will load the pro·
gram counter from the memory vector locations FFFC and FFFD.
This is the start location for program control.
After VCC reaches 4.75 volts in a power up routine, reset must be
held low for at least two clock cycles. At this time the R/W and
(SYNC) signal will become valid.,
When the reset signal goes high following these two clock cycles.
the microprocessor will proceed with the normal reset procedure
detailed above.
(
ADDRESSING MODES
ACCUMULATOR ADDRESSING - This fonn of addressing is
represented with a one byte instruction, implying an operation on
the accumulator.
IMPLIED ADDRESSING - In the implied addressing mode, the
address containing the operand is implicitly stated in the operation
code of the instruction.
IMMEDIATE ADDRESSING - In immediate addressing, the
operand is contained in the second byte of the inStruction, with
no further memory addressing required.
RELATIVE ADDRESSING - Relative addressing is used only
with branch instructions and establishes a destination for the conditional branch.
ABSOLUTE ADDRESSING - In absolute addressing, ~econd
byte of the instruction specifies the eight low order bits of the
effective address while the third byte specifies the eight high
order bits. Thus, the absolute addressing mode allows access to
the entire 65K bytes of addressable memory.
The second byte of the instruction becomes the operand which is
an "Offset"added to the contents of the lower eight bits of the
program counter when the counter is set at the next instruction.
The range of the offset is -128 to +127 bytes from tha next
instruction.
ZERO PAGE ADDRESSING - The zero page instructions allow
for shorter code and execution times by only fetching the second
byte of the instruction and assuming a zero high address byte.
Careful use of the zero page can result in significant increase in
code efficiency.
INDEXED ZERO PAGE ADDRESSING - (X, V indexing) - This
form of addressing is used in conjunction with the index register
and is referred to as "Zero Page, X" or "Zero Page, V". The effective address is calculated by adding the second byte to the contents of the index register. Since this is a fonn of "Zero Page"
addressing, the content of the second byte references a location in
page zero. Additionally due to the "Zero Page" addressing nature
of this mode, no carry is added to the high order 8 bits of memory
and crossing of page boundaries does not occur.
INDEXED ABSOLUTE ADDRESSING - (X, V indexing) - This
form of addressing is used in conjunction with X and V index register and is referred to as "Absolute, X", and "Absolute, V". The
effective address is formed by adding the contents of X or V to
the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or
count value and the instruction to contain the base address. This
type of indexing allows any location referencing and the index to
modify multiple fields resulting in reduced coding and execution
time.
INDEXED INDIRECT ADDRESSING - In indexed indirect
addressing (referred to as (Indirect, Xl), the second byte of the
instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory
location on page zero whose contents is the low order eight bits
of the effective address. The next memory location in page zero
contains the high order eight bits of the effective address. Both
memory locations specifying the high and low order bytes of the
effective address must be in page zero.
INDIRECT INDEXED ADDRESSING - In indirect .indexed
addressing (referred to as (Indirect!, V), the second byte of the
instruction points to a memory location in page zero. The contents of this memory location is added to the contents of the V
index register, the result being the low order eight bits of the
effective address. The carry from this addition is added to the
contents. of the next page zero memory location, the result being
the high order eight bits of the effective address.
ABSOLUTE INDIRECT - The second byte of the instruction
contains the low order eight bits of a memory location. The high
order eight bits of that memory location is contained in tha third
byte of the instruction. The contents of tha fully specified memory location is the low order byte of the effective address. The
next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program
counter.
INSTRUCTION SET - ALPHABETIC SEQUENCE
ADC Add Memory to Accumulator with Carry
AND "AND" Memory with Accumulator
ASl Shift left One Bit (Memory or Accumulator)
BCC
BCS
BEQ
BIT
BMI
BNE
BPl
BRK
BVC
BVS
Branch on Carry Clear
Branch on Carry Set
Branch on Result Zero
Test Bits in Memory with Accumulator
Branch on Result Minus
Branch on Result not Zero
Branch on Result Plus
Force Break
Branch on Overflow Clear
Branch on Overflow Set
ClC
ClD
Cli
ClV
CMP
CPX
CPV
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Compare Memory and Index X
Compare Memory and Index V
DEC Decrement Memory by One
DEX Decrement Index X by One
DEV Decrement Index V by One
EOR "Exclusive-or" Memory with Accumulator
INC
INX
INV
Increment Memory by One
Increment Index X by One
Increment Index V by One
JMP
JSR
Jump to New location
Jump to New location Saving Return Address
lOA
lOX
lDV
lSR
load Accumulator with Memory
load Index X with Memory
load Index V with Memory
Shift One Bit Right (Memory or Accumulator!
NOP
No Operation
ORA "OR" Memory with Accumulator
PHA Push Accumulator on Stack
PHP Push Processor Status on Stack
PlA Pull Accumulator from Stack
PlP Pull Processor Status from Stack
ROL
ROR
RTI
RTS
Rotate One Bit Left (Memory or Accumulator)
Rotate One Bit Right (Memory or Accumulator)
Return from Interrupt
Return from Subroutine
SBC
SEC
SED
SEI
STA
STX
STY
Subtract Memory from Accumulator with Borrow
Set Carry Flag
Set Decimal Mode
Set Interrupt Disable Status
Store Accumulator in Memory
Store Index X in Memory
Store Index V in Memory
TAX
TAV
TSX
TXA
TXS
TVA
Transfer Accumulator to Index X
Transfer Accumulator to Index V
Transfer Stack Pointer to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack Register
Transfer Index V to Accumulator
VSS
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