OTI 610_611_Multimedia_Audio_and_Communications_Accelerators_Technical_Specification_May97 610 611 Multimedia Audio And Communications Accelerators Technical Specification May97
User Manual: OTI-610_611_Multimedia_Audio_and_Communications_Accelerators_Technical_Specification_May97
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OAK TECHNOLOGY~
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OAK TECHNOLOGY~
011-610/011-611
Multimedia
Audio and Communications
Acce Ierators
Technical
Specification
May 1997
Customer Feedback
Oak Technology welcomes your suggestions to improve the quality of our documentation.
Please send your comments to:
Corporate Communications Department
Oak Technology
139 Kifer Court
Sunnyvale, CA 94086
Fax: (408) 737-3838
e-mail: marcom@oaktech.com
Printed in the U.S.A.
\0 1997 Oak Technology, Inc.
All Rights Reserved
v.OO3
Oak Technology and the Oak logo are registered trademarks of Oak Technology, Inc. Audia3D and TeiAudia3D are trademarks of Oak Technology, Inc. All other names, brands, products
and company names are trademarks or registered trademarks of their respective owners.
The information contained in this document is the property of Oak Technology, Inc. The document itself remains the sole property of Oak Technology and is provided for the sole purpose
of incorporating Oak Technology products. No part of this document may be duplicated or stored by electronic means without the express written consent of Oak Technology, Inc. This
document is distributed only in conjunction with a non-disclosure agreement with Oak Technology, Inc. and must be surrendered along with all copies upon request of Oak Technology,
Inc. Any use, other than specified, may result in civil and criminal prosecution. Parties providing information to Oak Technology, Inc. which leads to the conviction of any person for
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The information in this document has been carefully checked and is believed to be reliable. However, Oak Technology Inc. (OTI) makesno guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use, of or reliance upon it. OTI does not guarantee that the use of any
information contained herein will not infringe upon patent, trademark, copyright, or rights of third parties. No patent or license is implied hereby. This document does not in any way
extend the warranty on any product beyond that set forth in OTl's standard terms and conditions of sale. OTI reserves the right to make changes in the product or specifications, or both,
presented in this publication at any time without notice.
Oak Technology
Technical Specification
CONTENTS
CHAPTER 1: OVERVIEW .................................................................................................. 1-1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Features .................................................................................................................................. 1-1
1.1 .1
OTI-61 0 Features ..... '" .............................................................................................. 1-1
1.1 .2
OTI-611 Features ...................................................................................................... 1-2
Product Introduction ............................................................................................................... 1-1
1.2.1
OTI-610 PCI Audio Accelerator ................................................................................ 1-1
1.2.2
OTI-611 PCI Audio and Communications Accelerator ............................................... 1-2
Architecture ............................................................................................................................. 1-3
Block Diagram Descriptions .................................................................................................... 1-4
1.4.1
Digital Signal Processor ......................................................................... '" ................ 1-4
1 .4.2
External Device Interface .......................................................................................... 1-7
MIDI Port .................................................................................................................. 1-7
1.4.3
1.4.4
Game Port ................................................................................................................ 1-8
1.4.5
PS Input Port ............................................................................................................. 1-8
Programmable Input/Output Port ......................... ~ .................................................... 1-8
104.6
ModemNoice and Audio Codec Interfaces .............................................................. ~ 1-8
104.7
104.8
DAA Interface (OTI-611 Only) .................................................................................. 1-9
The OTI-61 0 System ....................................................................................,........................... 1-9
The OTI-611 System .............................................................................................................. 1-1 0
Technical Specifications ........................................................................................................ 1-11
1.7.1
OTI-610 Technical Specifications ........................................................................... 1-11
1.7.2
OTI-611 Technical Specifications ........................................................................... 1-15
Wavetable Synthesizer Technical Specifications .................................................................... 1-19
1.8.1
HSP Wavetable Synthesizer Technical Specifications .............................................. 1-20
1.8.2
Optional DSP Wavetable Synthesizer Technical Specifications ............................... 1-20
1.8.3
HSP Fax/Data Modem Technical Specifications ...................................................... 1-21
CHAPTER 2: PCI BUS INTERFACE .................................................................................... 2-1
2.1
2.2
PCI Bus
PCI Bus
2.2.1
2.2.2
2.2.3
2.204
Interface Description .................................................................................................. 2-1
Function Information .................................................................................................. 2-2
Configuration ReadIWrite Cycle ................................................................................ 2-3
1/0 ReadIWrite Cycle .......................... ~ ..................................................................... 2-4
Game Port Registers .................................................................................................. 2-4
Bus Master Operation and Memory ReadIWrite Burst Cycle ...................................... 2-4
CHAPTER 3: CODEC I NTERFACES ................................................................................... 3-1
3.1
3.2
Oak Technology
Codec Selection ...................................................................................................................... 3-1
Codec Interfaces ..................................................................................................................... 3-2
Technical Specification
OTI-610/0TI-611
3.3
3.4
3.5
3.6
OTI-61 O/OTI-611 to AC '97 Codec Interface ........................................................................... 3-3
3.3.1
AC '97 Codec Types ................................................................................................. 3-4
3.3.2
AC '97 Codec Clocking ............................................................................................ 3-5
3.3.3
Resetting the AC '97 Codec ...................................................................................... 3-6
3.3.4
AC-LinkAudio Output Frame (SDATA_OUTJ ............................................................ 3-6
3.3.5
AC-Link Audio Input Frame (SDATA_INJ ................................................................... 3-7
Dual Codec (Audio and Modem) Interface (OTI-611 to STLC7549) .......................................... 3-9
Audio Codec Interface (OTI-61 0 to STLC7549AC) ................................................................. 3-10
Dual Codec (Audio and Modem) Interface (OTI-611 to AD1843) ........................................... 3-11
CHAPTER 4: PERIPHERAL INTERFACES ...•.••...•.••....••.•....••.•........••••....•......•........•.......•... 4-1
4.1
4.2
4.3
4.4
4.5
Musical Instrument Digital Interface (MIDI) Port ...................................................................... 4-1
Game Port ............................................................................................................................... 4-3
4.2.1
Hardware Polling Digital Mode ................................................................................ 4-3
4.2.2
Analog Mode ............................................................................................................ 4-3
4.2.3
Game Port Interface Description ............................................................................... 4-4
Decoded Audio Input Port (l2S Port) ......................................................................................... 4-5
Programmable Input/Output Port ............................................................................................. 4-9
DAA Interface ....................................................................................................................... 4-10
CHAPTER 5: MEMORY INTERFACE ..•..•.•..•...•••.•.••.....•........•.....•..••••.....•••....•........••..•...•.•• 5-1
5.1
5.2
External Wavetable Sample Set ROM Interface ........................................................................ 5-1
SRAM Memory Interface Timing .............................................................................................. 5-2
CHAPTER 6: PIN DESCRIPTIONS ..•..•...••.••.•.••..•.•...•....•....•.•.....•..•.•.•.•.......•.••.........•.•.....•• 6-1
6.1
6.2
6.3
6.4
OTI-610 Pinout Diagram ......................................................................................................... 6-1
OTI-611 Pinout Diagram ......................................................................................................... 6-2
Pin Grouping by Function ....................................................................................................... 6-3
6.3.1
Pin Names by Pin Number ........................................................................................ 6-3
Pin Descriptions by Interface ................................................................................................... 6-8
6.4.1
PCI Interface ............................................................................................................. 6-8
6.4.2
MPEG and MIDI Interface ....................................................... :................................. 6-9
6.4.3
External Memory Interface ......................................................................................... 6-9
6.4.4
Audio Codec Interface ............................................................................................. 6-10
6.4.5
Clocks and Miscellaneous Interface ........................................................................ 6-11
6.4.6
DAA Interface ......................................................................................................... 6-11
6.4.7
Modem Codec Interface .......................................................................................... 6-12
PIO and Game Port Interface .................................................................................. 6-12
6.4.8
6.4.9
Power ..................................................................................................................... 6-13
CHAPTER. 7: REGISTER DEFI NITIONS ...•..•••..•...•..•.••.•..•.•.••.•.•...•....•..•.•••...•...•..•..•......•.•... 7-1
7.1
Oak Technology
Numerical Listings of Registers ................................................................................................ 7-2
7.1.1
Game Port Function Registers ................................................................................... 7-2
7.1.2
Audio Function Registers .......................................................................................... 7-2
7.1.3
Modem Control Function Registers ........................................................................... 7-4
ii
Technical Specification
Contents
7.2
7.3
7.4
7.5
7.6
7.7
Oak Technology
Alphabetical Listings of Registers ............................................................................................. 7-5
7.2.1
Audio Registers ......................................................................................................... 7-6
7.2.2
Game Port Registers .................................................................................................. 7-8
7.2.3
Modem Registers ...................................................................................................... 7-8
PCI Configuration Registers ..................................................................................................... 7-9
7.3.1
Audio Configuration Registers ................................................................................... 7-9
7.3.2
Game Port Configuration Registers .......................................................................... 7-12
7.3.3
Fax/Modem Configuration Registers ........................................................................ 7-15
General Control Registers ...................................................................................................... 7-18
704.1
OTI-61 010TI-611 Status Register (Read Only) ......................................................... 7-20
704.2
Miscellaneous Modes Control Register .................................................................... 7-21
7.4.3
Codec Control ........................................................................................................ 7-22
704.4
General Purpose 1/0 Control ................................................................................... 7-23
704.5
Interrupt Status Register ........................................................................................... 7-24
704.6
Interrupt Mask Register ........................................................................................... 7-25
704.7
DSP Interface and Codec Sample Rate Control Register ........................................... 7-26
704.8
PS Control and Status .............................................................................................. 7-27
704.9
DSP General Control 1 ........................................................................................... 7-28
704.10 DSP General Control 2 ........................................................................................... 7-29
704.11
Miscellaneous Channel Control .............................................................................. 7-30
704.12 Power Down Control (Write Only) .......................................................................... 7-31
704.13
PS Input Rate Control and Status ............................................................................. 7-31
704.14 Digital Audio Serial Port (l2S) Format Control (Write Only) ...................................... 7-32
704.15 Host Interface Port (HIP) Interface Registers ............................................................. 7-32
704.1 6 MPU-401 Control Registers ..................................................................................... 7-34
7.4.17 Codec Index Register 2 ........................................................................................... 7-36
7.4.18 Codec Index Register 1 ........................................................................................... 7-37
7.4.1 9 Codec Data Register ............................................................................................... 7-37
704.20 STLC7549 GPIO Data Register ................................................................................ 7-38
Channel Registers .................................................................................................................. 7-39
7.5.1
Playback Base Address 0 and 1 - Channel n (where n = 0-7) ................................... 7-42
7.5.2
Playback Segment Length 0 and 1 - Channel n (where n = 0-7) ............................... 7-43
7.5.3
Playback Channel Command - Channel n (where n = 0-7) ...................................... 7-44
7.504
Playback Segment Position - Channel n (where n = 0-7) ........................................... 7-45
7.5.5
Playback Channel 7 Interrupt Count. ....................................................................... 7-46
7.5.6
Capture Base Address - Channel n (where n = 8 or 9) ............•................................. 7-47
7.5.7
Capture Segment Length - Channel n (where n = 8 or 9) .......................................... 7-48
7.5.8
Capture Channel Command - Channel n (where n = 8 or 9) .................................... 7-49
7.5.9
Capture Segment Control- Channel n (where n = 8 or 9) ........................................ 7-50
7.5.10 Capture Interrupt Count - Channel 9 ....................................................................... 7-51
Game Port Registers .............................................................................................................. 7-51
7.6.1
Standard Game Port ................................................................................................ 7-52
7.6.2
Digital Mode Game Port I & II X Position ................................................................ 7-53
7.6.3
Digital Mode Game Port I & II Y Position ................................................................ 7-53
7.6.4
Game Port Control .................................................................................................. 7-54
OTI-611 Fax/Modem I/O Register Definitions ........................................................................ 7-55
7.7.1
Modem Data Registers ............................................................................................ 7-55
Index Address Register ............................................................................................ 7-56
7.7.2
7.7.3
Codec Index Register .............................................................................................. 7-56
iii
Technical Specification
OTI-610/0TI-611
7.7.4
7.7.5
7.7.6
Codec Data Registers .............................................................................................. 7-57
External Outputs Register ........................................................................................ 7-58
Modem I/O Space Register ...................................................................................... 7-58
CHAPTER 8: AC-LINK CHARACTERISTICS ....................................................................... 8-1
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.1 0
8.11
8.12
8.13
8.14
Audio Codec '97 Component Specification Overview ............................................................. 8-1
AC '97 AC-Link Digital Serial Interface Protocol ...................................................................... 8-1
OTI-61 0/OTI-611 in the AC '97 System ................................................................................... 8-4
AC '97 System Implementation ................................................................................................ 8-5
OTI-61 0/OTI-611 Connection to the AC '97 Codec ................................................................. 8-6
Resetting the AC '97 Codec ........................................................................................ '" .......... 8-7
8.6.1
Cold AC '97 Reset ..................................................................................................... 8-7
8.6.2
Warm AC '97 Reset .................................................................................................. 8-8
8.6.3
Register Reset of AC '97 Codec ................................................................................. 8-8
AC-Link Low Power Mode ...................................................................................................... 8-8
8.7.1
Waking up AC-Link .................................................................................................. 8-9
Examples of AC-Link Power Down Operations .......................................................... 8-9
8.7.2
Testability ............................................................................................................................. 8-10
AC-Link DC and AC Characteristics ....................................................................................... 8-11
8.9.1
DC Characteristics .................................................................................................. 8-11
8.9.2
AC Timing Characteristics ........................................................................................ 8-12
8.9.3
Reset ...................................................................................................................... 8-12
Clocks ................................................................................................................................... 8-13
Data Setup and Hold ............................................................................................................. 8-14
Signal Rise and Fall Times ..................................................................................................... 8-15
AC-Link Low-Power Mode Timing ......................................................................................... 8-16
ATE In-Circuit Test Mode Timing ........................................................................................... 8-17
CHAPTER 9: ELECTRICAL CHARACTERISTICS ................................................................. 9-1
9.1
9.2
9.3
9.4
Oak Technology
Absolute Maximum Ratings ..................................................................................................... 9-1
DC Specifications .................................................................................................................... 9-2
AC Specifications .................................................................................................................... 9-4
Reset Timing ............................................................................................................. 9-4
9.3.1
PCI Clock Requirement ............................................................................................. 9-5
9.3.2
9.3.3
PCI Bus Timing (I/O Read Operation) ........................................................................ 9-6
9.3.4
PCI Bus Timing (I/O Write Operation) ....................................................................... 9-7
PCI Bus Master Request Timing ................................................................................. 9-8
9.3.5
9.3.6
PCI Bus Master ReadIWrite Timing ............................................................................ 9-8
9.3.7
ROM Memory Interface Timing .............................................................................. 9-10
9.3.8
SRAM Memory Interface Timing ............................................................................. 9-11
AC-Link Timing Characteristics .............................................................................................. 9-12
AC-Link Reset Timing ............................................................................................. 9-13
9.4.1
9.4.2
Clocks .................................................................................................................... 9-14
9.4.3
Data Setup and Hold .............................................................................................. 9-15
Signal Rise and Fall Times ....................................................................................... 9-16
9.4.4
9.4.5
AC-Link Low Power Mode Timing .......................................................................... 9-17
ATE In-Circuit Test Mode ........................................................................................ 9-17
9.4.6
iv
Technical Specification
Contents
9.5
9.6
9.7
9.8
9.9
Audio/Modem Codec Port Timing (STLC7549) ....................................................................... 9-18
Audio Codec Port Timing (STLC7549AC) ............................................................................... 9-21
Modem Codec Port Timing (ST7546) ..................................................................................... 9-24
TDM Audio/Modem Codec Port Timing (AD1843) ................................................................ 9-26
f2S Port Timing ...................................................................................................................... 9-29
CHAPTER 10: THERMAL SPECIFICATIONS ......•.............•..................•...•..........••....•••.•... 10-1
CHAPTER 11: MECHANICAL SPECIFICATIONS ............................................................ 11-1
APPENDIX A: OTI-611 HSP FAX/DATA MODEM ............................................................ A-1
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.1 a
A.11
HSP Fax/Modem ...... ,............................................................................................................. A-l
A.l .1
Software Environment .............................................................................................. A-l
A.l.2
Hardware Environment ............................................................................................ A-l
Standard Features ................................................................................................................... A-2
Technical Specifications ......................................................................................................... A-2
AT Command Set ................................................................................................................... A-3
AT/Kn Command Set .............................................................................................................. A-7
Results Codes ......................................................................................................................... A-7
5 Registers .......................................................................... '" ................................................. A-9
Fax Class 1 Command Set .................................................................................................... A-13
Call Progress ........................................................................................................................ A-15
AT Voice Command Descriptions ......................................................................................... A-16
cloP - PIT Testing Utilities ..................................................................................................... A-24
APPENDIX B: HOST SIGNAL PROCESSING (HSP) BASED WAVETABLE SYNTHESIZER .. B-1
B.l
B.2
B.3
B.4
B.5
B.6
Oak Technology
HSP Wavetable Synthesizer Specifications ............................................................................. B-1
HSP Wavetable Synthesizer Description ................................................................................. B-2
General MIDI Description ...................................................................................................... B-2
General MIDI Sound Sample Set Description ......................................................................... B-3
CyberSound Keyboard Description ....................................................................................... B-12
Wavetable Synthesizer Key/Note Range ............................................................................... B-12
v
Technical Specification
OTI-610/0TI-611
(This page intentionally left blank)
Oak Technology
vi
Technical Specification
OVERVIEW
CHAPTER 1
1.1
FEATURES
1.2
1.1.1
OTI-610 FEATURES
The OTI-61 0 and OTI-611 controllers are PCI bus based audio and audio/
communications devices designed to support multiple digital audio stream
sample rate conversion, digital mixing, and playback. Both devices
provide full duplex audio operation (simultaneous playback and record in
stereo), and the OTI-611 has fax/data modem capability.
•
•
•
•
•
•
•
Provides high-performance
multiple channel digital audio
to Pentium-class systems
PRODUCT INTRODUCTION
Multiple digital audio channels
with sample rate conversion on
each channel
1.2.1
Digital mixing of all channels
The OTI-61 0, also known as the Audia3DTM, is a highly integrated audio
accelerator that is suitable for motherboard and add-in card applications.
Microsoft 2D DirectSound DSPbased hardware acceleration
Supports mu Iti~e source
DirectSound 3 positional
sound (Head Related Transfer
Function) using DSP hardware
acceleration
Sample rate conversion and
mixing support of an FS input
port for uncomMessed digital
audio, such as PEG-1 audio
Meets the AC '97 (Audio Codec
1997) specification b~ meeting
requirements for AC- ink
•
Programmable DSP core for
easy feature upgrades
•
s~nthesizer with reverb and
General MIDI wavetable music
c orus
MIDI port (IN and
• MPU-401
Oun
32-bit PCI bus master support
• with
scatter/gather
OTI-610 PCIAUDIOACCElERATOR
The OTI-61 0 supports major sound standards such as Microsoft Windows
Sound System (WSS) software, Microsoft DirectSound, Microsoft
Directlnput, and Microsoft's software emulated SoundBlaster Pro
standards.
The OTI-61 0 DSP supports wavetable music synthesis (when used with
external Sample Set ROM) or host signal processing (HSP) wavetable
music synthesis. Both synthesizer types support the Musical Instrument
Digital Interface (MIDI) interfaces. Both synthesizer types support the
General MIDI (GM) compatible instrument set consisting of 128 instruments or sounds, each instrument or sound having its own instrument or
"patch" number. The OTI-61 0 also supports a GM Drum Kit. Two audio
effects, chorus and reverb, are also supported.
For the DSP synthesizer, up to 24 voices at 22.05 KHz are presented
concurrently. Chorus and reverb operations require memory to delay the
sample outputs to generate the effects. The OTI-61 0 implements a delay
line memory by using system memory and the PCI bus. Chorus requires
one delay buffer and reverb requires five.
For the HSP synthesizer, up to 32 voices at 22.05 KHz are presented
concurrently. Chorus and reverb operations are implemented in system
memory.
The OTI-61 0 incorporates direct interfaces to an audio co dec, game and
MIDI ports, external optional Wavetable Sample Set ROM, an FS digital
audio port for MPEG decoded digital audio, and the PCI bus.
Oak Technology
1-1
Technical Specification
011-610/011-611
1.1.2
OTI-611 FEATURES
Provides high-performance
• multiple
channel digital audio,
modem, and fax capabilities to
Pentium-class systems
digital audio channels
• Multiple
wjth sample rate conversion on
each channel
• Digital mixing of all channels
2D DirectSound DSP• Microsoft
based hardware acceleration
source
• Supports
DirectSound 3 positional
multi~e
sound (Head Related Transfer
Function) using DSP hardware
acceleration
rate conversion and
• Sample
mixing support of an PS input
port for uncomMessed digital
audio, such as PEG-1 audio
HSP fax/data
• V.34bis-compliant
modem
Exceeds the AC '97 (Audio
• Codec
1997) specification 'Cmeetin requirements for A Link, p uscferoviding an additional mo em codec interface
R
Programmable DSP core for
• easy
feature upgrades
music
• General MIDIwithwavetable
reverb and
s~nthesizer
1.2.2
OTI-611 PCI AUDIO AND COMMUNICATIONS ACCELERATOR
The OTI-611, also known as the TeiAudia3DTM, is a highly integrated audio
and communications accelerator suitable for motherboard and add-in
card appl ications.
The OTI-611 supports major sound standards, including Microsoft
Windows Sound System (WSS) software, Microsoft DirectSound, Microsoft
Directlnput, and Microsoft's software-emulated SoundBlaster Pro
standards.
'
The OTI-611 DSP supports wavetable music syntheSiS (when used with
external sample set ROM) or host signal processing (HSP) wavetable music
synthesis. Both synthesizer types support the Musical Instrument Digital
Interface (MIDI) interfaces. Both synthesizer types support the General
MIDI (GM) compatible instrument set consisting of 128 instruments or
sounds, each instrument or sound having its own instrument or "patch"
number. The OTI-611 also supports a GM Drum Kit. Two audio effects,
chorus and reverb, are supported.
For the DSP synthesizer, up to 24 voices at 22.05 KHz are presented
concurrently. Chorus and reverb operations require memory to delay the
sample outputs to generate the effects. The OTI-611 implements a delay
line memory by using system memory and the PCI bus. Chorus requires
one delay buffer and reverb requ ires five.
For the HSP synthesizer, up to 32 voices at 22.05 KHz are presented
concurrently. Chorus and reverb operations are implemented in system
memory.
The OTI-611 supports an HSP-based, fully compliantV.34 (28.8 Kbps) and
V.34+ (33.6 Kbps) data, andV.29, Y.17, andV.27terfax modem operation,
inciudingV.42 LAPM & MNP 2-4 error detection and correction and
V.42bis & MNP 5 data compression.
c orus
MIDI port (IN and
• MPU-401
OUT)
32-bit PCI bus master support
• with
scatter/gather
Oak Technology
The OTI-611 incorporates direct interfaces to an audio codec and/or
modem codec, (or combination thereof), game and MIDI ports, external
optional Wavetable Sample Set ROM, an FS digital audio port (for MPEG
decoded digital audio), and the PCI bus.
1-2
Technical Specification
Overview
1.3
ARCHITECTURE
The OTI-61 0 and OTI-611 share a common PCI bus master interfaced, RAM-based DSP architecture for support
of the features listed on pages 1-1 and 1-2. The OTI-61 0 and OTI-611 provide 10 bus master channels. Channels
o through 7 are used for playback of digital audio. Channel 8 is used for recording of digital audio. Channel 9
is reserved for use with the DSP-based wavetable synthesizer.
The OTI-61 0 and OTI-611 also provide support for an HSP-based wavetable synthesizer and General MIDI Sound
Sample Set, which utilizes one digital audio channel playback channel.
The ROM interface provides an interface to an optional external 2MB ROM, which is used for storing a GM
Sound Sample Set if the optional DSP-based GM wavetable synthesizer is used.
The audio codec interface within the OTI-61 0 and OTI-611 provides direct connections to different types of
audio codecs, depending upon external jumper settings, which are read during power up and stored in a status
register.
The OTI-611 offers additional functionality over the OTI-61 0 by providing hardware support for an HSP-based
Y.34 fax/modem in the form of transmit and receive buffers, and modem codec and DAA interfaces. The OTI-611
also provides direct connections to different types of modem codecs, depending upon external jumper settings,
which are read during power up and stored in a Status register.
Simplified block diagrams for the OTI-61 0 and OTI-611 are shown in Figures 1-1 and 1-2. More detailed block
diagrams are shown in Figures 1-3 and 1-4.
DSPCORE
Wavetable Synthesis,
Digital Mixing,
Direct Sound & 3D.
PCI
PCI
MASTER
IIF
DSP
INTERFACE
OS PI
MEMORY
Interface
t
BUS
Bus
Arbiter
Figure 1-1: OTI-610 Simplified Block Diagram
Oak Technology
1-3
Technical Specification
011-610/011-611
DSP CORE
Wavetable Synthesis,
Digital Mixing, .
Direct Sound & 3D.
PCI
BUS
PCI
MASTER
IIF
DSPI
MEMORY
Interface
DSP
INTERFACE
.----------,
14-~ L_c:~:~n_e~ _0_ J
Bus
Arbiter
Figure 1-2: OTI-611 Simplified Block Diagram
1.4
BLOCK DIAGRAM DESCRIPTIONS
Figure 1-3 gives a more detailed block diagram of the OTI-61 0 audio accelerator, and Figure 1-4 gives a more
detailed block diagram of the OTI-611 audio and communications accelerator.
1.4.1
DIGITAL SIGNAL PROCESSOR
The core of the OTI-61 0 and OTI-611 is a dedicated high-speed, RAM-based digital signal processor (DSP)
tailored for audio applications. Its three-bus architecture and logiC design allow program memory, data memory,
and coefficient memory all to be accessed on a single cycle. The DSP of the OTI-61 0 and OTI-611 features all
the instructions commonly used in other DSP chips, plus special instructions to speed up certain audio
operations, such as wavetable synthesis with effects, sample rate conversion, and digital mixing.
The OTI-61 0 and OTI-611 DSPs have the following features:
•
A tightly coupled interface between the DSP and PCI bus master
•
Three sets of internal static random access memory (SRAM): 5Kx24 words, 4Kx16 words, and 2Kx16 words
•
Single-cycle computation for all functions, including multiplier/accumulator (MAC)
•
Single-cycle fetch of one opcode and two operands
•
Single-cycle context switching
•
Zero overhead looping and branching
•
Three clock latency values to handle interrupts
Oak Technology
1-4
Technical Specification
~
A
rot
n
---.--------;::::=============::=:::;----.-.-~===.:::::;-
OTI-610
I HOSTI
::r
DSP
CORE
Supports:
Wavetable
Synthesis
Digital Mixing
DlrectSound &
3D Positional Sound
IF
::3
o
~
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IF
~:~:~~::O]
WDMD[1S : 0]
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.---Bus Master Chan nels
Channel 0: Playback
I Address Logic
Data BUffer
Control & Status'
Channel 1: Playback
P M(SKx24)
XDM(4Kx16)
Channel 2: Playback
Y DM(2Kx 16)
Channel 3: Playback
•
DSP RAMs
AUDIO
CODEC
IF
•
•
Channel7:Playback
-l
AMCLK
ASCLK
AFS
ASDO
ASDI
ARESET#
APWDN#
I
VI
ChannelS: Capture
Channel 9: Capture
I
~ External Device I F
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aa
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Figure 1-3: OTl-61 0 Expanded Block Diagram
~
~.
~
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o
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---_....__.._-----_._._--_.
OTI-611
R
FRAME#
IRDY#
BUS
REQUEST
ARBITER
TRDY#
II Bus
..
H.
LJ §E
DSP CORE
Supports: Wavetable Synthesis
Digital Mixing
DlrectSound &
3D Positional Sound
LJ
RST#
__._----_ _-----
Address Logic
Channel1: Playback
PCIBUS
P M(SKx 24)
Slave' Master
IF
X OM (4Kx 16)
Channel 2: Playback
AD [31: 0]
YDM(2Kx16)
Channel 3: Playback
PAR
AUDIO
CON FIG.
•
REQ#
DSP RAMs
AUDIO
CODEC
IF
•
•
Channel7:Playback
GNT#
INTA#
Channel8: Capture
INTB#
Channel 9: Capture
LCLK
PXTALMI
11 i 1 I
a c aC ~
~
0
)(
c==
~
0
:j
1 l-·l--=f=f·----{--·---f----·--·--l--·-f---f=f·-+--f--;-·-j---"l
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r-
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l:a ~ ~ ~ Ie;') I(/) ~
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m~
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AMCLK
ASCLK
AFS
ASDO
ASDI
ARESET#
APWDN#
MMCLK
MSCLK
MFS
MSDO
MSDI
MRESET#
MPWDN#
MODEM
CONFIG.
~
...4
Q
.......
g
...4
...4
Control & Status
~
)Ii
I
c:T\
c:T\
& AUX BUS
rol
WDMCE2#
Data BUffer
DEVSEU
n
:r
::::J
0'
WDMCE1#
ChannelO:Playback
IDSEL#
PXTALMO
WDMD[1S :0)
g
•
I
'~
WDMA[19 :0]
Bus Master Chan nels
Request
STOP
CBE#[3:0]
WDMOE#
Figure 1-4: OT/-611 Expanded Block Diagram
Overview
•
Extended dynamic range -
•
External ROM memory space support -
•
Parallel host interface port (HIP) for faster and more flexible communications with the host system
•
liming-adjustable external memory interface
•
36 Mips speed performance
•
Special instructions for commonly used audio operations
•
Zero wait states for external memory access, if special coding rules are followed
1.4.2
includes 40-bit accumulator
up to 2MB -
through an internal base address register
EXTERNAL DEVICE INTERFACE
The OTI-61 0 and OTI-611 external device interface (ED!) includes the following sub-blocks:
• MIDI port
• Game port
• Digital, serial FS audio interface
• Programmable input/output port
• Audio codec interface
• Modem codec interface (OTI-611 only)
only)
• DAA interface
(OTI~611
1.4.3
MIDI PORT
MIDI information is passed by using two pins connected to an internal universal asynchronous receiver
transmitter (UART) - one pin for receiving and one for transmitting.
The hardware implementation is MPU-401 compatible when used with a standard MIDI adapter and game cable,
and is capable of full duplex transmission and reception.
The transmission rate is fixed at 31 .25 KHz, per the MIDI Specification.
Two 16x8 FIFOs are used for MIDI data buffering -
one for receiving and one for transmitting.
For more information on the MIDI interface, refer to Chapter 4, Section 4.1.
Oak Technology
1-7
Technical Specification
011-610/011-611
1.4.4
GAME PORT
The game port interface uses an analog timer, which is NE5S8-compatible in operation. The port interfaces with
analog joysticks, which are used for computer game programs.
A typical application constantly polls the game port, up to 90 times per second, when the analog joystick is
selected. To conserve CPU power, the OTI-61 0/OTI-611 has hardware to check the game port for data and
immediately puts the data into a register for the CPU to read. This speeds up the game port operation. Driver
support is required to take advantage of this feature.
For more information on the game port interface, refer to Chapter 4, Section 4.2.
1.4.5
12S INPUT PORT
The OTI-61 0 and OTI-611 provide an interface to the external digital serial audio. The serial audio data, like
decoded MPEG audio output, can be input and then mixed with all sound sources from the host.
For more information on the FS interface, refer to Chapter 4, Section 4.3.
1.4.6
PROGRAMMABLE INPUT/OUTPUT PORT
The OTI-611 provides two software-controlled PIO interface pins, which can be used as general I/O pins to
interface with external devices. Alternatively, these pins may be software programmed to implement a simple FC
serial bus protocol for communication to a Single FC device.
For more information on the programmable I/O interface, refer to Chapter 4, Section 4.4.
1.4.7
MODEMNOICE AND AUDIO CODEC INTERFACES
The modem/voice and audio codec interfaces provide the following functions for both the'OTI-61 0 and OTI-611,
except where noted:
•
Transmit/receiving buffers (FIFO) management, including interrupt generation and modem codec interface for
fax/modem operation (OTI-611 only).
•
The OTI-61 0 provides one interface port for an external audio codec. The codec interface will convert the
audio codec serial data to parallel data for digital audio data capture and will convert digital audio parallel
data to serial data for playback through the audio codec. Chapter 3 provides complete information on codec
support for the OTI-61 O.
•
The OTI-611 provides two interface ports, one for an external audio codec and one for an external modem
codec. Alternatively, by setting a Codec Selection register, these ports can be used in different configurations
to support multiple types of audio and modem codecs. In either case, the codec interfaces receive data
through their serial ports. The codec interface will convert the codec serial data to parallel data for capture/
receiving and parallel data to serial data for playback/transmitting. Chapter 3 provides complete information
on codec support for the OTI-611 .
•
AC-Link interface support (which is required for AC '97 compliant audio codecs, or AC '97 compliant dual
audio and modem codecs): The OTI-61 0 and OTI-611 provide an AC-Link interface. The OTI-61 0 AC-Link
interface will operate correctly only with AC '97 audio codecs. The OTI-611 AC-Link interface will operate
correctly with either AC '97 audio codecs (audio data only to the codec) or an AC '97 audio/modem codec
(audio and modem data to the codec).
For more information on the codec interface, refer to Chapter 4, Section 4.5.
Oak Technology
1-8
Technical Specification
Overview
1.4.8
DAA INTERFACE (OTI-611 ONLy)
The OTI-611 provides multiple signals for direct connection to fax/data modem DAA structures. When used with
the HSPY.34/V.34+ fax/data modem software supplied with the OTI-611 and an appropriate modem codec, a
complete fax/data modem may be built.
In addition, programmable, uncommitted input and output pins are also available for additional flexibility in the
modem system design.
For more information on the DAA interface, refer to Chapter 4, Section 4.5.
1.5
THE OTI-610 SYSTEM
Figure 1-5 presents a simplified block diagram of a PCI audio system based on the OTI-61 o. The audio codec
may be an AC '97 type with the AC-Link interface, or it may be the STLC7549AC Audio Codec from SGS
Thomson.
Reference Design Schematics and a Bill of Materials for an OTI-610 audio system implementation are available.
12 5 Uncompressed
Digital Audio
Optional
Wavetable
Sample
ROM
r - - - - - - Analog
Inputs
AUDIO
CODEC
011-610
SPEAKERS
Joystick
MIDI
port
Figure 1-5: OTI-610 Simplified System Block Diagram
Oak Technology
1-9
Technical Specification
OTI-610/0TI-611
1.6
THE OTI-611 SYSTEM
Figure 1-6 below is a simplified block diagram of a PCI audio and communications system based on the OTI-611.
The audio codec may be an AC '97 type with the AC-Link interface, or it may be the STLC7549AC Audio Codec
from SGS Thomson. The modem codec may be the ST7546 from SGS Thomson. Alternatively, the audio and
modem codec functions may be fulfilled by the Oak Technology OTI-612 AC '97 compliant dual co dec, or any
other AC '97 compliant dual codec. Other alternatives are the STLC7549 Dual Codec from SGS Thomson and
the AD1843 Dual Codec from Analog Devices.
Refer to Chapter 3 for more information on interfacing to codecs.
The OTI-611 provides various interface signals to the DAA. For more details on the DAA interface, refer to
Chapter 4. The DAA must be designed to meet the voltage isolation and connection approval regulations for the
country or countries in which the resultant fax/data modem solution is to be sold. The DAA design may be a
standard transformer and op-amp hybrid configuration, or may be all solid state design.
Reference Design Schematics and a Bill of Materials for various OTI-611 based audio and communications
system implementations are available.
2
Optional
Wavetable
Sample
1 5 Uncompressed
Digital Audio
, - - - - Analog
Inputs
ROM
SPEAKERS
AUDIO
CODEC
II)
:J
=
U
011-611
=-
MODEM
CODEC
Joystick
TIP
RING
MIDI
port
Figure 1-6: OT/-67 7 Simplified System Block Diagram
Oak Technology
1-10
Technical Specification
Overview
1.7
TECHNICAL SPECIFICATIONS
1.7.1 OTI-610TECHNICAL SPECIFICATIONS
Physical Description
•
160-pin Plastic Quad Flat Pack (PQFP)
•
O.5J.l triple-layer metal CMOS
Supported Multimedia Standards
•
Microsoft DirectSound
•
Microsoft DirectSound 3D
•
Microsoft Directlnput
•
Microsoft Windows Sound System
•
SoundBlaster Pro software emulation via Windows 95 (for hardware-level compatibility a separate SB register
compatible device is required).
•
MPU-401 (UART mode)
•
General MIDI synthesizer
DSP Specifications
•
36 Mips speed performance
•
lightly coupled interface between the DSP and PCI bus master
•
Three sets of internal static random access memory (SRAM): 5Kx24 words, 4Kx16 words, and 2Kx16 words
•
Single instruction/single data computation for all functions, including multiplier/accumulator (MAC)
•
Single-cycle fetch of one opcode and two operands
•
Single-cycle context switching
•
Zero overhead looping and branching
•
Three clock latency values for interrupts
•
Extended dynamic range, including 40-bit accumulator
•
External ROM memory space (up to 2MB)
•
Parallel host interface port (HIP) for faster and more flexible communications with the host system
•
liming adjustable, external memory interface
Oak Technology
1-11
Technical Specification
OTI-610/0TI-611
•
Special instructions for common audio operations
•
Zero wait states for external memory access (when special coding ru les are followed)
System Bus Interface
•
32-bit direct connection to PC! bus (33-MHz PCI 2.1 compliant)
•
PCI burst and PCI bus mastering supported
•
Scatter/gather functions supported
•
Multiple interrupts supported
DSP Audio Processing
•
DirectSound HRTF 3D positional audio
•
Wavetable synthesis (optional)
•
Sound buffer playback
•
Sound buffer capture
•
Digital audio mixing
•
Sample rate conversions (8 KHz to 48 KHz)
Digital Mixing Capabilities
•
Up to 8 mono or stereo channels of digital audio playback with sample rate conversion
•
Two mono or stereo channels for audio capture and loopback
MIDI Interface
•
MPU-401 UART mode
•
16-byte FIFOs for MIDI IN and OUT
•
MIDI IN and OUT
Game Port Interface
•
Directlnputsupport
•
Digital mode
•
Analog mode
Oak Technology
1-12
Technical Specification
Overview
Codec Interface Compatibility
•
Any AC '97 audio codec
•
STL7549AC audio-only Codec
•
AD1843 Audio Codec
Microsoft DirectX Technology Accelerator
The OTI-61 a supports the complete range of Microsoft's DirectSound and DirectSound 3D hardware
acceleration functions.
The OTI-61 a supports the complete range of Microsoft's Directlnput acceleration functions in hardware.
HSP Wavetable Synthesizer Specifications
•
Available in Pentium class and Pentium MMX class software versions
•
Up to 32-voice polyphony
•
Full 16 MIDI channel multi-timbral support
•
Complete General MIDI (GM) Sound Set
•
GM Percussion Sound Set
•
4MB sample sets available
•
Supports downloadable samples to system RAM
•
User-defined maximum RAM cache, CPU utilization, and number of allowable voices
•
Intelligent scaling and dynamic buffering to minimize CPU utilization
Optional DSP Wavetable Synthesizer Specifications
•
Professional quality DSP-based wavetable synthesizer with 24-voice polyphony
•
Full 16 MIDI channel multi-timbral support
•
Complete 128-instrument GM Sound Sample Set, with GM Percussion Sound Set stored in external 2MB
Sample ROM
•
Programmable reverb and chorus effects control without additional SRAM
Minimum System Requirements
•
133-MHz Pentium CPU
•
16MB system memory
•
256KB cache
Oak Technology
1-13
Technical Specification
OTI-610/0TI-611
•
PCI bus interface
•
Windows 95 or Windows NT 4.0
Power Management
•
Hardware and software power down and mute
Other Interfaces
•
Programmable pin for peripheral control (software FC implementation)
•
J25 port for digital audio streams,
•
Wavetable sample ROM
AC '97 Codec Interface
•
5-pin digital serial interface -AC-Link
•
Bi-directional, fixed data rate, serial PCM digital stream
•
Supports 16-bit samples and sets the trailing 4 bits to zero (0) within the AC '97 20-bit data slots
•
The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming datastreams, each with
20-bit sample resolution, allowing support of 16-bit, 18-bit, and 20-bit samples within each data slot of the
datastream
Software and Manufacturing Support
Oak Technology offers comprehensive software support packages for Oak multimedia devices. The OTI-61 0
software package comes with drivers for popular operating systems such as Windows 95 and NT. In addition,
Oak supplies complete manufacturing reference deSigns for the OTI-61 0, which facilitates early market entry.
Operating System Drivers
Windows 95
Windows NT 4.0
Windows Sound System
Windows Sound System
DirectSound and DirectSound 3D
MPU-401
Directlnput
Analog and Digital Joystick
Analog and Digital Joystick
HSP Wavetable
MPU-401
Oak Technology
1-14
Technical Specification
Overview
1.7.2
OTI-611 TECHNICAL SPECIFICATIONS
Physical Description
•
Integrated AC '97 compliant digital controller for audio and communications
•
160-pin Plastic Quad Flat Pack (PQFP)
•
O.Sf.! triple-layer metal CMOS
Supported Multimedia Standards
•
Microsoft DirectSound
•
Microsoft DirectSound 3D
•
Microsoft Directlnput
•
Microsoft Windows Sound System
•
SoundBlaster Pro emulation in software via Windows (for hardware-level compatibility a separate SB registercompatible device is required)
•
MPU-401 (UART mode)
•
General MIDI synthesizer
DSP Specifications
•
36 Mips speed performance
•
Tightly coupled interface between the DSP and PCI bus master
•
Three sets of internal static random access memory (SRAM): SKx24 words, 4Kx16 words, and 2Kx16 words
•
Single instruction/single data computation for all functions, including multiplier/accumulator (MAC)
•
Single-cycle fetch of one opcode and two operands
•
Single-cycle context switching
•
Zero overhead looping and branching
•
Three clock latency values for interrupts
•
Extended dynamic range, including 40-bit accumulator
•
External ROM memory space (up to 2MB)
•
Parallel host interface port (HIP) for faster and more flexible communications with the host system
•
Timing adjustable, external memory interface
•
Special instructions for common audio operations
•
Zero wait states for external memory access (when special coding rules are followed)
Oak Technology
1-15
Technical Specification
011-610/0TI-611
System Bus Interface
•
32-bit direct connection to PCI bus (33-MHz PCI 2.1 compliant)
•
PCI burst and PCI bus mastering supported
•
Scatter/gather functions supported
•
Multiple interrupts supported
DSP Audio Processing
•
Multiple digital audio channels
•
DirectSound HRTF 3 D positional audio
•
Wavetable synthesis
•
Sound buffer playback
•
Sound buffer capture
•
Digital audio mixing
•
Sample rate conversions (8 KHz to 48 KHz)
Digital Mixing Capabilities
•
Up to 8 mono or stereo channels of digital audio playback with sample rate conversion
•
Two mono or stereo channels for audio capture and loopback
MIDI Interface
•
MPU-401 UART mode
•
16-byte FIFOs for MIDI IN and OUT
•
MIDI IN and OUT
Game Port Interface
•
Directlnput support
•
Digital mode
•
Analog mode
Codec Interface Compatibility
•
Any AC '97 audio/modem codec
•
OTI-612 AC '97 audio/modem codec
•
STLC7549 audio/modem codec
Oak Technology
1-16
Technical Specification
Ov.erview
•
AC '97 audio codec plus ST7546 modem codec
•
AD1843 as audio/modem codec
•
AD1843 as audio codec plus ST7546 modem codec
HSPIDAA Modem Interface
To support its host-based modem, the OTI-611 has the following. Data Access Arrangement (DAA) functions and
controls:
•
•
•
•
•
•
RING_DET - Ring Detect
LC_SENSE - Line Current Sense
OFF_HOOK - Hook Relay Control
CID_RELAY - Caller ID Relay Control
HDSET_REL - Handset Relay Control
CODEC_MODE - Codec Mode Select
Microsoft DirectXTechnology Accelerator
The OTI-611 supports the complete range of Microsoft's DirectSound and DirectSound 3D hardware acceleration
functions.
The OTI-611 supports the complete range of Microsoft's Directlnput acceleration functions in hardware.
HSP Wavetable Synthesizer Specifications
•
Available in Pentium class and Pentium MMX class software versions
•
Up to 32-voice polyphony
•
Full 16 MIDI channel multi-timbral support
•
Complete General MIDI (GM) Sound Set
•
GM Percussion Sound Set
•
4MB sample sets available
•
Supports downloadable samples to system RAM
•
User-defined maximum RAM cache, CPU utilization, and number of allowable voices
•
Intelligent scaling and dynamic buffering to minimize CPU utilization
Oak Technology
1-17
Technical Specification
011-610/011-611
Optional DSP Wavetable Synthesizer Specifications
•
Professional quality DSP-based wavetable synthesizer with 24-voice polyphony
•
Full 16 MIDI channel multi-timbral support
•
Complete 128-instrument GM Sound Sample Set, with GM Percussion Sound Set stored in external 2MB
sample ROM
•
Programmable reverb and chorus effects control without additional SRAM
HSP Modem Specifications
•
Industry-standard Hayes AT Command Set
•
28.8K/33.6KV34+ modem (56K upgradeable)
•
14.4KV.29, V.17, andV.27ter fax
•
V.42bis and MNP 5 compression
•
V.42 LAPM and MNP 2-4 error detectionlcorrection
Minimum System Requirements
•
133-MHz Pentium CPU (P166 required for simultaneous MIDI/modem operation)
•
16MB system memory (32MB recommended)
•
256KB cache
•
PCI bus interface
•
Windows 95 or Windows NT 4.0
Power Management
•
Hardware and software power down and mute
•
Modem wakeup on Ring Detect
Other Interfaces
•
Programmable pin for peripheral control (software FC implementation)
•
FS port for digital audio streams
•
Wavetable sample ROM
AC '97 Codec Interface
•
5-pin digital serial interface - AC-Link.
•
Bi-directional, fixed data rate, serial PCM digital stream
Oak Technology
1-18
Technical Specification
Overview
•
Supports 16-bit samples and sets the trailing 4 bits to zero (0) within the AC '97 20-bit data slots
•
The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with
20-bit sample resolution, allowing support of 16-bit, 18-bit, and 20-bit samples within each data slot of the
data stream
Software and Manufacturing Support
Oak Technology offers comprehensive software support packages for Oak multimedia devices. The OTI-611
software package comes with drivers for popular operating systems such as Windows 95 and NT. In addition,
Oak supplies complete manufacturing reference designs for the OTI-611, which facilitates early market entry.
Operating System Drivers
Windows 95
Windows NT 4.0
Windows Sound System
Windows Sound System
DirectSound and DirectSound 3 D
MPU-401
Directlnput
Analog and Digital Joystick
Analog and Digital Joystick
HSP Modem
HSP Modem
HSP Wavetable
MPU-401
1.8
WAVETABLE SYNTHESIZER TECHNICAL SPECIFICATIONS
The OTI-61 0 or OTI-611 systems optionally support two types of wavetable synthesizers:
•
Host signal processing (HSP) based
•
Digital signal processor (DSP) based
The HSP type is Pentium class or Pentium MMX class based software only and produces a digital audio data
stream that is sentto the OTI-61 0/OTI-611, similar to data contained in a .WAV file. The OTI-61 0/OTI-611 mixes
this digital audio data along with any other incoming digital audio data streams and sends the resultant digital
mix to the audio codec for playback.
The DSP type is implemented in firmware running on the internal DSP engine within the OTI-61 0/OTI-611. The
DSP wavetable synthesizer engine produces a digital audio data stream that is mixed internally in the DSP along
with other incoming digital audio data streams. The resultant digital audio mix is sent to the audio codec for
playback.
Oak Technology
1-19
Technical Specification
OTI-610/0TI-611
Appendix B contains the following additional information about each type of wavetable synthesizer supported for
OTI-61 0/OTI-611 based systems.
•
General MIDI Sound Sample Set chart
•
GM Percussion Sound Set chart
•
MIDI implementation chart
•
General information on MIDI
1.8.1
HSP WAVETABLE SYNTHESIZER TECHNICAL SPECIFICATIONS
When used with the OTI-61 0 or OTI-611 as the audio playback system with MPU-401 MIDI port support, the
HSP wavetable synthesizer meets the following technical specifications:
•
Professional quality software-based synthesizer with 32-voice polyphony
•
Available in Pentium class and Pentium MMX class software versions
•
Full 16 MIDI channel multi-timbral support
•
Complete 128-instrument GM Sound Sample Set, with extended GM Percussion Sound Set
•
Programmable reverb and chorus effects control using system RAM
•
Supports downloadable samples to system RAM, extending instrument options beyond General MIDI
instrument set
•
User-selectable maximum RAM cache, CPU utilization, and number of allowable voices
•
Intelligent scaling and dynamic buffering to minimize CPU utilization
•
MIDI IN, MIDI OUT hardware MPU-401 interface to external MIDI sequencers, MIDI sound modules, and
MIDI keyboards for recording and playback.
•
Real-time instrument selection when used with CyberSound Keyboard application
•
Works with standard Windows 95 software sequencers (Media Player, Sound Recorder [play mode], Cakewalk
Pro, Voyetra Orchestrator, Netscape Navigator MIDI playback plug-ins, and others) for MIDI file playback and
real-time user control of the synthesizer.
1.8.2
OPTIONAL DSPWAVETABLE SYNTHESIZERTECHNICAL SPECIFICATIONS
The OTI-61 0 or OTI-611 will support an optional DSP-based wavetable synthesizer, which will meet the
following technical specifications:
•
Professional-quality DSP-based wavetable synthesizer with 24-voice polyphony
•
Full 16 MIDI channel multi-timbral support
•
Complete 128-instrl,lment GM Sound Sample Set, with GM Percussion Sound Set stored in external 2MB
sample ROM
•
Programmable reverb and chorus effects control without additional SRAM
Oak Technology
1-20
Technical Specification
Overview
•
MIDI IN, MIDI OUT hardware MPU-401 interface to external MIDI sequencers, MIDI sound modules, and
MIDI keyboards for recording and playback
•
Real-time instrument selection when used with CyberSound Keyboard application
•
Works with standard Windows 95 software sequencers (Media Player, Sound Recorder [play mode], Cakewalk
Pro, Voyetra Orchestrator, Netscape Navigator MIDI playback plug-ins, and others) for MIDI file playback and
real-time user control of the synthesizer
1.8.3
HSP FAX/DATA MODEM TECHNICAL SPECIFICATIONS
The HSPV.34/Y.34+ fax/data modem software supplied with the OTI-611 will, when combined with appropriate
modem codec and approved DAA, result in a fully functional fax/data modem capable of meeting the following
specifications Iisted below.
Appendix A contains the supported AT Command Set, along with other details.
COMMAND SET
DATA STANDARDS
FACSIMILE
STANDARDS
ASYNCHRONOUS
DATA
ERROR CORRECTION
DATA COMPRESSION
COMMUNICATIONS
•
Oak Technology
Industry Standard Hayes AT Command Set
ITU-T V.21
0-300 bps
ITU-T V.22
1,200 bps
ITU-T Y.22bis 2,400 bps
ITU-T Y.23
1,200175 bps
ITU-T Y.32
9,600 bps
ITU-T V.32bis 14,400 bps
ITU-T V.34
28,800 bps
33,600 bps
Y.34+
Bell 103
0-300 bps
Bell 212A
1,200 bps
ITU-T
ITU-T
ITU-T
ITU-T
Y.21
Y.17
Y.27ter
V.29
300 bps Channell
14,400 bps 4,800 bps
9,600 bps
Start Bits
Data Bits
Pari~
1
1
7
7
8
8
odd or even
mark or space
none
none
Bits
Stop Bits
1 or 2
1 or 2
2
1 or 2
ITU-T Y.42 LAPM and MNP 2-4
ITU-T Y.42bis and MNP 5
-43 dBm
-10 dBm (± 1 dBm)
Adj. if allowed by PIT
Receive Sensitivity:
Transmit Level:
1-21
Technical Specification
011-610/011-611
(This page intentionally left blank)
Oak Technology
1-22
Technical Specification
PCI BUS INTERFACE
CHAPTER 2
2.1
PCI BUS INTERFACE DESCRIPTION
The OTI-61 0 and OTI-611 support direct connections to the PCI bus. The PCI interface is compliant with the PCI
Local Bus Specification Revision 2.1.
Each logical device within the OTI-61 0/OTI-611 circuits (audio and game port devices for the OTI-61 0 and
audio, game port, and modem devices for the OTI-611 ) has its own configuration read and write registers to meet
PCI plug and play requirements, as well as I/O base address registers to meet the need for programmable control
registers to control the functions of each device.
To increase the audio data transfer rate, the OTI-61 0 and OTI-611 also perform as bus masters to take memory
read/write burst cycles and directly capture or fill system memory as required.
Refer to Chapter 6 for pin names and descriptions for the PCI bus interface.
Refer to Chapter 7 for register descriptions of the OTI-61 0/OTI-611 .
PCI Bus Interface
•
The 32-bit PCI bus is supported up to 33 MHz.
•
Bus master memory read/write cycles can be programmed to be either 0 or 1 wait state on the OTI-61 0/
OTI-611 side. The default value is 1 wait state. The typical bus master transfer is done as 4 double words in a
burst cycle.
•
The configuration cycle is run at 1 wait state.
•
I/O cycles run at 2-5 wait states.
Oak Technology
2-1
Technical Specification
011-610/011-611
2.2
PCI BUS FUNCTION INFORMATION
The following tables show the PCI bus interface command cycles that the OTI-61 0 and OTI-611 support.
Command
Supported Mode
Description
1/0 Read
Target
No burst cycle, no back-back 1/0, medium DEVSEL#, any
enable bytes combination.
I/O Write
Target
No burst cycle, no back-back 1/0, medium DEVSEL#, any
enable bytes combination.
Interrupt Acknowledge
Not supported
Special Cycle
Not supported
Configuration Read
Target
Any enable bytes combination, medium DEVSEL#. Burst cycle
not supported.
Configuration Write
Target
Any enable bytes combination, medium DEVSEL#. Burst cycle
not supported.
Memory Read
Master
4 DWORD, burst cycle transfer depends on buffer request
Memory Write
Master
4 DWORD, burst cycle transfer depends on buffer request.
Memory Read Multiple
Not supported
Dual Address Cycle
Not supported
Memory Read Line
Not supported
Memory Write and Invalidate
Not supported
Unsupported Special Bus Interface Signals:
PERR#
Not supported
5ERR#
Not supported
lOCK#
Not supported
5BO#
Not supported
5DONE#
Not supported
Oak Technology
2-2
Technical Specification
PCI Bus Interface
Termination and Special Functions in Master Mode:
Fast Back-to-Back Transaction
Not supported
Target Abort
Master mode can handle this
Disconnect
Master mode can handle this
Retry
Master mode can handle this
Master Abort
Wait up to six PC! clocks to detect DEVSEL# in master cycle
Latency Timer
Not supported
Cache Line Size
Not supported
Address/Data Stepping
Does not happen
Termination and Special Functions in Siave/Target Mode:
Delay Transaction
Not supported
Fast Back-to-Back Transaction
Not supported
Target Abort
Supported when illegal address detected
Disconnect
Supported when burst cycle occurs
Retry
Does not happen
Master Abort
Does not happen
Address/Data Steppi ng
Does not happen
Note:
In Slave mode, the OTI-61 0 and OTI-611 do not support burst cycle in order to avoid any errors
occurring in transfer cycle. Slave mode should implement disconnect target termination when burst
cycle occurs. That is, if both FRAME# and IRDY# are detected and asserted at the same rising elK, the
OTI-610 and OTI-611 will assertTRDY#, STOP#, and DEVSEl# until the current data phase transfer
completes.
2.2.1
CONFIGURATION READIWRITE CYCLE
Configuration read/write commands support (decoding cmd = 1010 or 1011).
If IDSEl# is asserted, the configuration commands are latched and AD(1 :0] are 00 (indicating Type 0
configuration header), and then the configuration cycle is started.
When FRAME# is asserted (sampled on the rising elK), the AD bus must be latched and decode the offset
configuration space (if the configuration cycle is on at the same time). Data read/write occurs after the second
elK rising edge (sendsTRDY# out). The second elK means IRDY# has been sampled.
When FRAME# is sampled and the second rising elK also samples both FRAME# and IRDY#, the burst cycle
occurs. Because the OTI-61 0/OTI-611 does not support a burst cycle, the pel interface should assert STOP# and
TRDY# at the same time.
Oak Technology
Technical Specification
OTI-610/0TI-611
2.2.2
I/O READIWRITE CYCLE
The OTI-61 0 and OTI-611 have an internal 32-bit wide data bus. By using 1/0 mapped registers, the device
drivers can directly control internal functions and get information about the OTI-61 0 and OTI-611 peripheral
devices.
At the CLK rising edge, if FRAME# is asserted, the OTI-61 0 and OTI-611 will latch the AD bus and CMD bus
data. After decoding the content, if the address bus value equals the 1/0 base register address, and the command
is I/O read/write (0010 or 0011), then the OTI-61 0/OTI-611 Slave mode is entered and DEVSEL# will be sent out
until the transaction is completed.
At the next rising CLK , the OTI-61 0 and OTI-611 will detect the IRDY# assertion. If it is true, the OTI-61 01
OTI-611 wi II receive the data or send out the data that is associated with the registers' decoded address and byte
enable at the following rising edge CLK. TRDY# will be sent out when the IRDY# is sampled at rising edge CLK.
2.2.3
GAME PORT REGISTERS
PCI Game Port Configuration registers are supported along with Standard Game addresses. Consult Chapter 7,
Section 7.6 for complete details. The default state for the OTI-61 0/OTI-611 is disabled.
2.2.4
BUS MASTER OPERATION AND MEMORY READ/WRITE BURST CYCLE
Bus Master Mode
When operating in the WSS or DirectSound modes, the device drivers enable the bus master cycle and the burst
Iine buffer is empty. The OTI-61 0/OTI-611 wi II request the bus from the system arbiter. The bus request wi II
continue to be asserted when buffer is empty until the disable command is received from OTI-61 010TI-611
device drivers.
Buffer Architecture for the Bus Master
Two 4-DWORD-sized line buffers are dedicated to each capture and playback function in the bus master mode.
This buffer is used for the memory burst command. The physical memory address and counter will increment at
each DWORD transfer. When the counter matches the Data Length register, an interrupt will be generated. The
address must auto-increment one DWORD until2x the data length offset is met, then the Memory address will
reload from the Memory address registers.
Command Select and Memory Burst Cycle
The OTI-61 0 and OTI-611 support bus master operation to issue a memory burst cycle, and the command could
be selected by device drivers. The supported commands include Memory Read, Memory Read Line, Memory
Write, Memory Write, and Invalidate to complete a burst cycle. The memory burst line buffer size is 4 DWORD.
When the OTI-61 0 and OTI-611 bus master is active and the request bus has been granted (GNT# asserted), the
OTI-610 and OTI-611 will continue to detect both FRAME# and IRDY# de-asserted (IDLE state). If IDLE state has
been detected, the bus master starts a bus cycle and sends FRAME#, burst start address, and command out first.
On the following CLK, IRDY# is sent out and the circuitry detects DEVSEL#, if it is asserted. If DEVSEL# is
asserted, the following rising CLK will transfer data as each TRDY# is sampled. Before the next data transfer (the
fourth DWORD), FRAME# is de-asserted and IRDY# continues to be asserted until completion of the last data
transfer. When the last data has been transferred, the line buffer should be full. The OTI-61 0 and OTI-611 will
request the bus when the buffer is empty and bus master is still enabled.
Oak Technology
2-4
Technical Specification
CODEC INTERFACES
CHAPTER 3
3.1
CODEC SELECTION
The OTI-61 0 and OTI-611 require information specifying which type of codec or combinations of codecs will be
used. This information is obtained during the Power Up sequence by reading the state of three signals, according
to the table below. Internally the pins are pulled up to Vdd. The logic state (1) may be set using pull-down
resistors on the appropriate pins. Refer to the OTI-61 0/OTI-611 Reference Schematics for component values.
After the Codec Selection data is read during Power Up, it is also stored in the OTI-61 0/OTI-611 Internal Status
register 40h, where it may be read by the OTI-61 0/OTI-611 software driver and used to set up the codecs for
proper operation.
OTl-610/0Tl-611 Signal Name
Codec Supported
WDMA[7]
(MCODEC bit 2)
WDMA[6]
(MCODEC bit 1)
WDMA[5]
(MCODEC bit 0)
ADl843 as Audio'N1odem Coded
0
0
0
Reserved
0
0
1
ADl843 as Audio Codec plus
ST7546 Modem N1odec'
0
1
0
Reserved Audio Codec plus
ST7546 Modem Codec'
0
1
1
STLC7549 Audio'lvt>dem Coded
1
0
0
OTJ-612 AC 197 Audio'N1odem Codec' or
Any AC 197 Audio'N1odem Codec'
1
0
1
AC 197 Audio Codec plus
ST7546 Modem Codec'
1
1
1
Reserved
1
1
0
Note:
' Modem Codec Selection is used by the OTI-611 only. Modem codec functions cannot be accessed by
the OTI-61 0, and the bit selections used with the OTI-61 0 will only affect audio codec selection.
Oak Technology
3-1
Technical Specification
OTI-610/0TI-611
3.2
CODEC INTERFACES
The OTI-61 0 is designed to support audio functions, while the OTI-611 is designed to support both audio and
communications functions. Both devices will support a variety of codecs, as listed in the table below.
In the sections that follow, details will be provided on interfacing to each type of codec.
Codecs Supported by the OTI-610 and OTI-611:
Codec
Description
Support
Notes
OTI-612
AC '97 Compliant (AC-Link) Dual Audio and Communications
Codec
OTI-611
1,2,3
AC '97 Codec
(AC-Link)
Audio Codec (basic specifications)
Dual Audio and Communications Codec (basic specification +
modem support)
OTI-610
OTI-611
1
1,2,4
Dual Audio and Communications Codec
OTI-611
5
OTI-610 (audio only)
OTI-611 (audio port)
5
OTI-611 (modem port)
5
OTI-610 (audio only)
OTI-611
6
STLC7549
STLC7549AC
Audio Codec
ST7546
Modem Codec (master mode, software mode, or hardware
mode for data transmit
AD1843
Dual Audio and Communications Codec (master mode, 16/32
slots per frame)
Notes (notes from AC '97 Specification in italics):
1. AC '97 controllerlAC '97 pair interoperability can only be guaranteed for non-optional AC '97
audio features.
2. Modem interoperability is not expected between AC '97 controllerlAC '97 pairs that aren't sourced
as a matched set by the same vendor. Given this, each vendor's AC '97 controller implicitly knows
what the Modem DAOADC resolution is in the AC '97 version wi modem support by inspecting the
vendor ID registers.
3. Oak Technology part number
4. Future products from other manufacturers of AC 197 compliant codecs provided modem 16-bit
outgoing and incoming data is in time slot 5. See note on modem interoperability.
5. SGSThomson part number
6. Analog Devices part number
Throughout the discussion of interfacing with the various codecs in this chapter, codec signal names will be given
along with the equivalent OTI-61 0 and OTI-611 Signal names. Codec signal names appearing in descriptive text
will be printed in italics and will be enclosed within parentheses.
Tables containing Signal names will show both the OTI-61 0/OTI-611 and codec signal names in the same way.
Example:
OTI-610/0TI-611 Signal Name
AC-Link Signal Name
ARESET#
(RESET#)
Timing diagrams will be presented with the OTI-61 0 and/or OTI-611 signal name in the illustration.
Oak Technology
3-2
Technical Specification
Codec Interfaces
3.3
OTI-61 0/OTI-611 TO AC '97 CODEC 1NTERFACE
The OTI-61 0 or OTI-611 communicates with the OTI-612 AC '97 compatible dual audio and communications
codec (or any other AC '97 compatible audio or dual audio and communications codec) via a digital serial link
called /lAC-link."
AC-Link is as-pin, bi-directional, fixed data rate, serial PCM digital stream. It handles multiple input and output
audio streams, as well as control register accesses to the AC '97 Codec device employing a time division
multiplexed (TOM) scheme. The AC-Link architecture divides each audio frame into 12 outgoing and 12
incoming datastreams, each with 20-bit sample resolution. Support is also available for 16-bit and 18-bit data
samples within the 20-bit slot. The OTI-61 0 and OTI-611 support 16-bit sample data within an AC '97 data slot.
See Chapter 8 for further information on AC-Link, including DC and AC timing characteristics.
All digital audio streams, optional modem line codec streams, and command/status information are
communicated over the AC-Link point-to-point serial interconnect interface. A breakout of the signals
connecting the two is shown in the table below. The signals listed in the table connect the OTI-61 O/OTI-611 to
an AC '97 compatible codec.
OTI-610/0TI-611
Signal Name
Type
OTI-612 or AC 197
Codec Signal NameAC-Link Signal Name
Type
ARESET#
0
RESET#
I
Master H/W Reset to AC 197 Codec from OTI-61 0 or
OTI-611
AFS
0
SYNC
I
48-KHz fixed rate sample sync from OTI-610 or OTI-611
ASClK
I
BIT_ClK
0
12.288-MHz serial data clock (Fxl2 from AC 197 Codec)
to OTI-610 or OTI-611. Fx=24.576 MHz
ASDO
0
SDATA_OUT
I
Serial, time division multiplexed output stream to AC 197
Codec from OTI-610 or OTI-611
ASDI
I
SDATA_IN
0
Description
Serial, time division multiplexed input stream from AC
197 Codec to OTI-610 or OTI-611
Throughout the discussion of interfacing with AC '97 type codecs in this chapter, AC-Link signal names will be
given along with the equivalent OTI-61 0 and OTI-611 signal names. AC-Link signal names appearing in
descriptive text will be printed in italics and will be enclosed within parentheses.
Tables containing signal names will show both the OTI-61 O/OTI-611 and AC-Link signal names in the same way.
Example:
011-610/011-611 Signal Name
ARESET#
AC-Link Signal Name
(RESET#)
liming diagrams will be presented with the AC-Link signal name in the illustration.
Oak Technology
3-3
Technical Specification
011-610/011-611
3.3.1
AC '97 CODEC TYPES
The AC '97 Codec is specified at minimal functionality as an audio-only codec. Optional support for modem
functions may also be provided, in which case the AC '97 Codec is an audio/communications codec, or a dual
codec.
The OTI-61 0 is an audio accelerator, and when used in an AC '97 system will support audio-only versions of the
AC '97 Codec. The OTI-611 is an audiolcommunications accelerator, and when used in an AC '97 system will
support audio/communications versions of the AC '97 Codec, such as the OTI-612.
The AC '97 Codec is specified in two package types - 48 pins and 64 pins. The audio-only or the audio/
communications version of the AC '97 Codec could be supplied in either a 48-pin or a 64-pin package.
Connections to the various types of AC '97 Codecs and the OTI-61 0 and OTI-611 are shown in the figures below.
OTI-610 Connections toAC'97 Audio Codecs
XTAL 11
ARESET#
~DO~~----~~~----~~
XTAL 10
~DI ~~----~~~-------~~
........"'------------~..;:;:.::.:;:.------------~--t
AFS J--IoOl.---....:.:.:.~---........~
~CLK
XTAl21
XTAl20
36.864
OTI·61 0
MHz
Figure 3-1: OT/-61 oAC-Link Connection toAC '97 Audio Codec, 48-pin Package
-
XTAl11
XTAl10
ARESET#
~DO
~DI
ASClK
AFS
25
RESET#
lS
20
21
22
19
SDATA OUT
SDATA IN
BIT ClK
SYNC
9
12
10
14
RESET:
SDATA.OUT
SDATAJN
BIT.ClK
SYNC
AC-Link
--L
XTAl21
AC'97
AUDIO
CODEC
0
L:..
36 .864
MHz
XTAl20
-:::L
D
~
Fx
24. 576
M Hz
64-Pin Pkg
OTI-610
Figure 3-2: OT/-610AC-Link Connection toAC '97 Audio Codec, 64-pin Package
Oak Technology
3-4
Technical Specification
Codec Interfaces
OTI-611 Connections to AC '97 Audio/Communications Codecs
-
XTAL 11
ARESET#
ASDO
ASDI
ASClK
AFS
XTAl10
2S
RESET:
11
20
21
22
19
SDATA OUT
SDATA IN
BIT ClK
SYNC
S
8
6
10
RESET:
SDATA_OUT
SDATA_IN
BIT_ClK
SYNC
XTAl21
011-612
36 .864
MHz
24. 576
M Hz
or
AC'97
CODEC
CJ
~
D
~
Fx
AC-link
--L
r::L
XTAl20
48·Pin Pkg
011-611
Figure 3-3: OTI-611 AC-Link Connection to AC '97 Audio/Communications Codec, 48-pin Package
XTAL 11
ARESETII
XTAL 10
ASDO
A5DI
ASCLK
AFS
25
RESET#
20
21
22
19
15
14
RESET:
SDATA_OUT
SDATA_IN
BIT_CLK
SYNC
Fx
24.576
AC-link
XTAL21
MHz
AC'97
CO DEC
XTAL20
36.864
MHz
64-Pin Pkg
011-611
Figure 3-4: OTJ-611 AC-Link Connection to AC '97 Audio/Communications Codec, 64-pin Package
3.3.2
AC '97 CODEC CLOCKING
Synchronization of all AC-Link data transactions is signaled by the OTI-61 O/OTI-611. The OTI-612 or other AC
'97 compatible codecs drive the serial bit clock (BIT_CLK) onto AC-Link, which the OTI-61 O/OTI-611 then
qualifies with a synchronization signal AFS (SYNC) to construct audio frames.
The OTI-612 or other AC '97 compatible codecs derive their clocks from an external 24.576-MHz (Fx) crystal
and drive a buffered and divided-by-2 clock (Fxl2) to the OTI-61 O/OTI-611 over AC-link under the AC-link signal
name "BIT_CLK." The use of a crystal is recommended, but an external oscillator may also be input to AC '97.
Clock jitter at the DACs and ADCs is a fundamental impediment to high-quality output, and the internally
generated clock provides a clean clock that is independent of the physical proximity of the OTI-61 0 or OTI-611.
The beginning of all audio sample packets, or "audio frames," transferred over AC-link is synchronized to the
rising edge of the AFS (SYNC) signal. AFS (SYNC) is driven by the OTI-61 0 or OTI-611. The OTI-61 0 or OTI-611
takes ASCLK (BIT_CLK) as an input and generates AFS (SYNC) by dividing ASCLK (BIT_CLK) by 256 and applying
some conditioning to tailor its duty cycle. This yields a 48-KHz AFS (SYNC) signal whose period defines an audio
frame. Data is transitioned on AC-link on every rising edge of ASCLK (BIT_CLK) and subsequently sampled on
the receiving side of AC-link on each immediately following falling edge of ASCLK (BIT_CLK).
Oak Technology
3-5
Technical Specification
011-610/011-611
3.3.3
RESETTINGTHEAC '97 CODEC
There are three types of AC '97 Codec resets:
1. a "cold" reset where all AC '97 Codec logic (registers included) is initialized to its default state
2. a "warm" reset where the contents of the AC '97 Codec register set are left unaltered
3. a "register" reset which only initializes the AC '97 Codec registers to their default states
After signaling a reset to AC '97, the OTI-61 0/OTI-611 will attempt to play or capture audiodata until it has
sampled a "Codec Ready" indication from the AC '97 Codec. (Refer to Chapter 8 for detailed explanations and
timing diagrams.)
.
3.3.4
AC-LlNKAUDIO OUTPUT FRAME (SDATA_OUT)
The audio output frame datastreams correspond to the multiplexed bundles of all digital output data targeting the
OTI-612 or any AC '97 compliant codec DAC inputs and control registers. Each audio output frame supports up
to 12 20-bit outgoing data time slots with either 16-bit, 18-bit, or 20-bit data in each time slot.
In the AC '97 mode, the OTI-61 0/OTI-611 supports only 16-bit data for slot 0 and 16-bit MSB justified data, with
trailing zeroes for 20-bit audio and modem data slots.
Slot 0 is a special reserved time slot containing 16 bits used for AC-Link protocol infrastructure.
Within slot 0 the first bit is a global bit (ASDO (SDATA_OUT) slot 0, bit 15) which flags the validity for the entire
audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one slot
time of valid data. The next 12 bit positions sampled by the AC '97 Codec indicate which of the corresponding
12 time slots contain valid data. In this way, datastreams of differing sample rates can be transmitted across ACLink at its fixed 48-KHz audio frame rate. Control/Status as well as optional extensions of the baseline AC '97
specification, such as the modem line codec, may take advantage of this feature. AC '97 specified audio
functional ity must always sample rate convert to and from a fixed 48 kilo samples/second on the AC '97
controller. This requirement is necessary to ensure that interoperability between AC '97 controller/AC '97 Codec
pairs, among other things, can be guaranteed by definition for baseline specified AC '97 features.
The following diagram illustrates the time slot based AC-Link protocol.
I~
-----Tag Phase
..
-----1---------
Data Phase
----------.j
20.8uS
(48 KHz)
\~----~r-----~'~------~
ASCLK
i
End 01 previous
Audio Frame
("1·
Time Slot ·Valid"
Bits
time slot contains valid PCM data)
=
Figure 3-5: AC-Link Audio Output Frame
A new audio output frame begins with a low to high transition of AFS (SYNC). AFS (SYNC) is synchronous to the
rising edge of ASCLK (BIT_CLK). On the immediately following falling edge of ASCLK (BIT_CLK), the AC '97
Codec samples the assertion of AFS (SYNC). This falling edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising of ASCLK (BIT_CLK), the OTI-61 0 or OTI-611
transitions ASDO (SDATA_OUT) into the first bit position of slot 0 (Valid Frame bit). Each new bit position is
Oak Technology
3-6
Technical Specification
Codec Interfaces
presented to AC-Link on a rising edge of ASCLK (BIT_eLK) and subsequently sampled by the AC '97 Codec on the
following falling edge of ASCLK (BIT_eLK). This sequence ensures that data transitions and subsequent sample
points for both incoming and outgoing datastreams are time aligned.
AC'97 Codec samples SYNC assertion here
~
AFS
C
ASCLK
AC'97 Codec samples first SDATA_OUT bit of frame here
J
.J1JlJlJlI
~~~~Slot(1) ~Slot (2)~
ASDO
!
End of previous
Audio Frame
Figure 3-6: Start of an Audio Output Frame
The ASDO (SDATA_OUT) composite stream is MSB justified (MSB first) with all non-valid slots' bit positions set
with Os by the OTI-61 0 or OTI-611. In the event that there are less than 20 valid bits within an assigned and
valid time slot, the OTI-61 0/OTI-611 always sets all trailing non-valid bit positions of the 20-bit slot with Os.
For example, consider an 8-bit sample stream that is being played out to one of the AC '97 Codec's DACs. The
first 8-bit positions are presented to the DAC (MSB justified), followed by the next 12 bit positions, which are set
with Os by the OTI-61 0 or OTI-611. This ensures that regardless of the resolution of the implemented DAC (16-,
18-, or 20-bit), no DC biasing will be introduced by the least significant bits.
When monophonic audio sample streams are output from the OTI-61 0 or OTI-611, it is necessary that both left
and right sample stream time slots be filled with the same data.
3.3.5
AC-LlNK AUDIO INPUT FRAME (SDATA_INJ
The audio input frame datastreams correspond to the multiplexed bundles of all digital input data targeting the
OTI-61 0/OTI-611. As is the case for audio output frame, each AC-Link audio input frame consists of 12 20-bit
time slots. Slot 0 is a special reserved time slot containing 16 bits used for AC-Link protocol infrastructure.
Within slot 0 the first bit is a global bit (ASDI (SDATA_IN) slot 0, bit 15) that flags whether the AC '97 Codec is in
the "Codec Ready" state or not. If the "Codec Ready" bit is a 0, this indicates that the AC '97 Codec is not ready
for normal operation. This condition is normal, for example, following the de-assertion of Power On Reset, while
the AC '97 Codec's voltage references settle. When the AC-Link "Codec Ready" indicator bit is a 1, it indicates
that the AC-Iink and AC '97 control and status registers are in a fu lIy operational state. The OTI-61 0/OTI-611
must further probe the Power Down Control/Status register of the AC '97 Codec to determine exactly which
subsections, if any, are ready.
Prior to any attempts at putting the AC '97 Codec into operation, the OTI-61 0/OTI-611 should poll the first bit in
the audio input frame (ASDI (SDATA_IN) slot 0, bit 15) for an indication that the AC '97 Codec has gone "Codec
Ready." Once the AC '97 Codec is sampled Codec Ready2, then the next 12 bit positions sampled by the
OTI-610/0TI-611 indicate which of the corresponding 12 time slots are assigned to input data streams, and that
they contain valid data.
There are several subsections within AC '97 Codec that can independently go busy/ready. It is the responsibility
of the OTI-61 0/OTI-611 software drivers to probe more deeply into the AC '97 Codec register fi Ie to determ ine
which AC '97 Codec subsections are actually ready.
Oak Technology
3-7
Technical Specification
011-610/011-611
The following diagram illustrates the time slot based AC-Link protocol.
1 4 - - - - - - Tag Phase
--------
----~.II-'
.
Data Phase
20.8uS
----------0/
,\------,
AFS
ASCLK<
ASDI~ _ _...IUJ.!!2lI:L..J1\ - - - I I . . . . _J '-J
Time Slot 'Valid'
Bits
('1' =time slot contains valid PCM data)
Siol 1
Figure 3-7: AC-Link Audio Input Frame
A new audio input frame begins with a low to high transition of AFS (SYNC). AFS (SYNC) is synchronous to the
rising edge of ASCLK (BIT_CLK). On the immediately following falling edge of ASCLK (BIT_CLK), the AC '97
Codec samples the assertion of AFS (SYNC). This falling edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising of ASCLK (BIT_CLK), the AC '97 Codec transitions
ASDI (SDATA_IN) into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented to
AC-Link on a rising edge of ASCLK (BIT_CLK), and subsequently sampled by the OTI-61 0/OTI-611 on the
following falling edge of ASCLK (BIT_CLK). This sequence ensures that data transitions and subsequent sample
points for both incoming and outgoing datastreams are time-aligned.
AC'97 Codec samples SYNC assertion here
AFS
ASCLK
ASDI
E
OTI·61010TI-611 samples first ASDI (SDATA_IN)
bit of frame here
J
JlSl1lJlI
~
!
End of previous
Audio Frame
Figure 3-8: Start of an Audio Input Frame
The ASDI (SDATA_IN) composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned
and/or unassigned time slots) set with Os by the AC '97 Codec. ASDI (SDATA_IN) data is sampled on the fall ing
edges of ASCLK (8IT_ CLK).
For more complete data and information on AC '97, consult the Audio Codec '97 component specification.
Oak Technology
3-8
Technical Specification
Codec Interfaces
3.4
DUAL CODEC (AUDIO AND MODEM) INTERFACE
(011-611 10 STLC7549)
The STLC7549 is a 16-bit 1:d-type dual audio and communications codec manufactured by SGS Thomson. For
audio functions it supports a variety of analog inputs and various hardware controls, as well as software register
controls.
The AC timing diagram and parameter table for the OTI-611 interface to the STLC7549 are given in Section 9.5
(Chapter 9).
The OTI-611 provides a direct interface to the STLC7549 for both audio and fax/data modem functions.
For audio, the data transfer and clocking interface consists of five signals: AMCLK (MCLKA), AFS (FSYNC 1),
ASCLK (SCLK1), ASDI (SIN1), and ASDO (SOUT1). AMCLK is an audio master clock derived from the OTI-611
internal clock generation circuitry. It is sent to the STLC7549AC master clock - MCLKA - input. No external
crystal on the STLC7549 is required. From the AMCLK (MCLKA) signal, all internal sampling frequencies for the
audio functions of the STLC7549 are generated, as well as the audio serial bit clock - ASCLK (SCLK1) - and the
audio frame sync signal - AFS (FSYNC1).
An audio data frame consists of four time slots in the ASDI (SIN 1) direction and four time slots in the ASDO
(SOUT1) direction. For the outgoing audio frame to the STLC7549, two time slots are assigned for audio Left and
Right data, and two time slots are assigned for STLC7549 register control data (if any) that may be written to
control registers. For the incoming audio frame from the STLC7549, two time slots are assigned for digitized
analog audio Left and Right data, and two time slots are assigned for STLC7549 status information and register
content data.
The fax/data modem register control data and status information is also carried on the audio frame, as
described below.
By placing data into the appropriate outgoing audio frame time slot, the OTI-611 software driver is able to
configure the STLC7549 to the requirements of the audio as well as the fax/data modem subsystem. Conversely,
by reading the data in the appropriate incoming audio frame time slot, the OTI-611 software driver is able to
determine the audio and fax/data modem configuration status of the STLC7549 and modify either accordingly
during the next frame (if necessary).
For fax/data modem functions, the data transfer and clocking interface consists of five signals: MMCLK
(MCLKM), MFS (FSYNC2), MSCLK (SCLK2), MSDI (SIN2), and MSDO (SOUT2).
MMCLK is an modem master clock derived from the OTI-611 internal clock generation circuitry. It is sent to the
STLC7549 modem master clock - MCLKM - input. From the MMCLK (MCLKM) signal, all internal sampling
frequencies for the modem functions of the STLC7549 are generated, as well as the modem serial bit clock MSCLK (SCLK2) - and the modem frame sync signal - MFS (FSYNC2).
A fax/modem data frame consists of four time slots in the MSDI (SIN2) direction and four time slots in the ASDO
(SOUT2) direction. For the outgoing fax/data modem frame to the STLC7549, two time slots are assigned for
modem data and telephony data, and two time slots are reserved. For the incoming fax/data modem frame from
the STLC7549, two time slots are assigned for modem data and telephony data, and two time slots are reserved.
For complete specification and implementation details for the STLC7549, please consult the STLC7549 data
sheet or contact SGS Thomson.
Oak Technology
3-9
Technical Specification
OTI-610/0TI-611
..L
XTAL 11
CJ
--c...
XTAL 10
11.2896
M Hz
L"""
36 .864
M Hz
ASDO
ASDI
ASCLK
AFS
AMCLK
XTAL21
CJ
-c..
APWON#
ARESET#
XTAL20
MSDO
MSDI
MSCLK
MFS
MMCLK
,,q
,,~
25
64
20
21
22
19
24
61
60
59
58
55
q
<;4
11
<;~
~
52
7
6
51
50
OTI-611
PDWN#
RESET#
SIN1
SOUTl
SCLK1
FSYNC1
MClKA
SIN2
SOUT2
SCLK2
FSYNC2
MCLKM
STLC7549
Figure 3-9: Dual Codec (Audio and Modem) Interface (OTJ-611 to STLC7549)
3.5
AUDIO CODEC INTERFACE (011-610 TO STLC7549AC)
The STLC7549AC is a 16-bit SD-type audio co dec manufactured by SGS Thomson. It supports a variety of analog
inputs and various hardware controls, as well as software register controls.
The AC timing diagram and parameter table for the OTI-61 0 interface to the STLC7549AC are given in Chapter 9,
Section 9.6.
The OTI-61 0 provides a direct interface to the STLC7549AC. The data transfer and clocking interface consists of
five signals: AMCLK (MCLKA), AFS (FSYNC1), ASCLK (SCLK1), ASDI (SIN 1), and ASDO (SOUT1). AMCLK is
an audio master clock derived from the OTI-61 0 internal clock generation circuitry. It is sent to the STLC7549AC
master clock - MCLKA - input. No external crystal on the STLC7549AC is required. From the AMCLK
(MCLKA) signal, all internal sampling frequencies for the STLC7549AC are generated, as well as the serial bit
clock - ASCLK (SCLK1) - and the frame sync signal - AFS (FSYNC1).
An audio data frame consists of four time slots in the ASDI (SIN 1) direction and four time slots in the ASDO
(SOUT1) direction. For the outgoing audio frame to the STLC7549AC, two time slots are assigned for audio Left
and Right data, and two time slots are assigned for register control data (if any) that may be written to control
registers. For the incoming audio frame from the STLC7549AC, two time slots are assigned for digitized analog
audio Left and Right data, and two time slots are assigned for status information and register content data.
By placing data into the appropriate outgoing audio frame time slot, the OTI-61 0 software driver is able to
configure the STLC7549AC to the requirements of the audio subsystem. Conversely, by reading the data in the
appropriate incoming audio frame time slot, the OTI-61 0 software driver is able to determine the status of the
STLC7549AC and modify it accordingly during the next frame (if necessary).
For complete specification and implementation details for the STLC7549AC, please consult the STLC7549AC
data sheet or contact SGS Thomson.
Oak Technology
3-10
Technical Specification
Codec Interfaces
--L
XTAl11
APWDN#
ARESET#
CJ
~ XTAL 10
11. 2896
M Hz
....r::-
ASDO
ASDI
ASClK
AFS
AMClK
28
f.':t
25
64
20
21
22
19
24
61
60
59
58
55
PDWN#
RESEll
SIN1
SOUT1
SCLK1
FSYNC1
MClKA
XTAl21
CJ
~ XTAL20
36 .864
M Hz
011-611
STLC7549AC
Figure 3-10: Audio Codec Interface (OTI-61 0 to SG7549AC)
3.6
DUAL CODEC (AUDIO AND MODEM) INTERFACE
(OTI-611 TO AD1843)
The AD1843 Serial Port 16-bit SoundComm Codec from Analog Devices, Inc. is a SO-type dual audio and
modem codec device with a TDM interface similar to AC-Link. It is available in the 80-pin PQFP package or the
1~O-pin TQFP package. For this discussion, it is assumed that the pin numbers used in the illustrations are for the
80-pin PQFP package.
AC timing diagrams and the timing parameter table for the OTI-611 connection to the AD1843 are found in
Section 9.8 (Chapter 9).
The AD1843 can operate in two modes: bus master and bus slave. The mode is controlled by the BM pin. When
tied toVdd (+3.3V or +S.OV), theAD1843 is a bus master. When tied toVss (OV), theAD1843 is a bus slave. If
used in the bus slave mode, two other pins, TSI [time slot in] and TSO [time slot out], may be required.
The BM pin selected mode of the AD1843 also controls the direction of the AD1843 (SCLK) and (SOFS) signals.
In the bus master mode, these signals are outputs to the OTI-611. In the bus slave mode, these signals are inputs
from the OTI-611 .
The 011-611 is designed to work with theAD1843 in the bus master mode only.
The TOM data and clocking interface consists primarily of the signals ARESET# (RESET#), ASCLK (SCLK), AFS
(SDFS), ASDO (500), and ASDI (501). Both audio and modem data are carried on this interface, with particular
time slots assigned to each data type.
The AD1843 also provides three conversion clock outputs which may be individually controlled by register
programming. When used with the AD1843, the OTI-611 software driver configures conversion clocks 1 and 2
to support the generation of the modem master clock (via the ACONVl input pin on the OTI-611 ) and frame sync
(the MFS input pin) requirement of the OTI-611 when performing modem functions. Serial bit clock inputMSCLK - is shared with ASCLK (SCLK). In this fashion, a direct interface between the OTI-61 0 and AD1843 is
achieved with the required sample rates for high-quality audio (up to 48 KHz) and for support ofV.34/V.34+ faxl
data modem communications, which have lower sample rates.
Oak Technology
3-11
Technical Specification
011-610/011-611
For complete specification and implementation details for the AD1843, consult the AD1843 data sheet or
contact Analog Devices, Inc.
XTAL 11
XTAL 10
APWDN# 1 - " . i L - - - - - - u - - t PWROWN#
ARESET# I - " " ' - - - - - - - u . - - t RESET:
ASOO 1----=~_ _ _~:...-tSDI
ASOI
SOO
ASCLK I----=~---~---i SCLK
AFS !---!""---+-----=----i SDFS
AMCLK
ACONV1 ........"'---t----=:---t CONV1
r----'-'---t CONV2
XTAL21
XTAL20
36.864
MHz
MSOO
MSOI
MSCLK
MFS
MMCLK
Vdd
8M
8
011-611
ADl843
Figure 3-11: Dual-Codec (Audio and Modem) Interface -
Oak Technology
3-12
OTl-611 to AD 1843
Technical Specification
PERIPHERAL INTERFACES
CHAPTER 4
4.1
MUSICAL INSTRUMENT DIGITAL INTERFACE (MIDI) PORT
The fundamental function of the MIDI interface is to convert parallel data bytes from the computer data bus into
the serial MIDI datastream (MIDI OUT) and serial MIDI formatted datastream (MIDI IN) into parallel data for use
by the computer (a UART function).
The de facto standard for a PC-based MIDI interface is the Roland MPU-401 interface. The OTI-61 0 and OTI-611
MIDI interface meets the MPU-401 standard requirements for UART mode operation.
The MIDI IN or MIDI OUT datastream is a unidirectional asynchronous serial bitstream at 31.25 Kbits/sec with
10 bits transmitted per byte (1 start bit, 8 data bits, and 1 stop bit). The MIDI data consists of MIDI messages
which control functions of the musical synthesizer such as Note On, Aftertouch, Modulation, and many others.
Typical MIDI messages consist of 3 bytes each, although there are variations.
The MIDI 1.0 Specification published by the International MIDI Association provides detailed information on the
MIDI protocol and a list of MIDI messages, along with the number of bytes for each MIDI message.
Additional information may be obtained from the MIDI Manufacturers Association.
For both the OTI-61 0 and OTI-611, MIDI data is passed without alteration -
that is, without MIDI Filtering.
Not all MIDI messages will affect the synthesizer to which they are directed due to the many different types of
synthesis used on, and the features provided by, music synthesizers on the market. For that reason, a MIDI
. implementation chart is published for each synthesizer detailing its responses to received MIDI messages, and
detailing which MIDI messages it can transmit.
A MIDI implementation chart is published for the OTI-61 0/OTI-611 supported wavetable synthesizer types. For
both the OTI-61 0 and OTI-611, the optional DSP-based wavetable synthesizer or the HSP-based wavetable
synthesizer will respond to MIDI messages according to MIDI implementation charts given for each type. See
Appendix B for details.
The MIDI Specification provides for three different MIDI connections, labeled MIDI IN, MIDI OUT, and the
optional MIDI THRU. The OTI-61 0 and OTI-611 provide support for MIDI OUT and MIDI IN data transfer. The
OTI-610 or OTI-611 do not internally provide support for MIDI THRU functions. External interfaces are
commercially available that can provide MIDI THRU capability, if required.
The OTI-61 0 and OTI~611 MIDI port is implemented with two signals - TXD for MIDI OUT and RXD for MIDI
IN. These pins use TTL logic voltage levels. The DC characteristics for these signals are provided in Chapter 9.
Oak Technology
4-1
Technical Specification
011-610/011-611
IMPORTANT NOTE:
The TXD and RXD signals are intended to be connected to the PC game port connector through a noise
suppression RC network.
For proper operation of the MIDI port it is necessary to use an industry-standard MIDI adapter and game
port cable that plugs into the game port connector and converts the TTL level signal into a current loop
signal for MIDI OUT data. When receiving MIDI IN data, it converts the current loop signal to a TTL
level signa\. The current loop operation is a requirement of the MIDI Specification for physical electrical
connections between MIDI capable devices. The game controller then plugs into the MIDI adapter and
game port cable assembly.
If a game controller is plugged directly into the game port connector, be sure that the game controller
does not make any connections to the MIDI IN and OUT pin assignments on the game port connector.
The OTI-61 0/OTI-611 internal port interface includes a 16-byte FIFO memory buffer for both MIDI IN and MIDI
OUT data. Incoming MIDI data may be read in register 60h. Outgoing MIDI data is written in register 60h. The
MIDI port may be turned on and off by programming register 61 h. See Chapter 7, Register Definitions, for more
details.
A noise suppression RC network is recommended on the TXD and RXD signals as shown in Figure 4-1 below.
Consult the OTI-61 0/OTI-611 Reference Schematics for component values.
TXD
r---:-14=.8_""-'\1
RXD 1+-14_7_-1--,\/
}
ToGarne Port
Connector
OTI-610
OTI-611
Figure 4-1: OT/-61 O/OT/-611 MIDI Interface Simplified Diagram
Oak Technology
4-2
Technical Specification
Peripheral Interfaces
4.2 GAME PORT
The OTI-61 0 and OTI-611 game port interface is designed to work in two modes: 1) hardware polling digital
mode and 2) analog mode. The game port control signals include four button signals and four position signals.
For both modes, the processing of the button Signals are the same. They are not latched, but the switch states are
just passed to the data bus when they are required. The position Signals are handled differently, depending upon
the mode being used.
4.2.1
HARDWARE POLLING DIGITAL MODE
In the hardware polling digital mode, the joystick position information is represented by a time delay value and a
digital counter. In this mode, when the OTI-61 0/OTI-611 Polling Enable bit is set (register OCh [7] = 1), a 12-bit
internal counter starts counting but will be reset after a fixed time period (9c4h=2500d, 2500ms). This period is
the game port sampling frequency.
lime delay signals sent from the NE558-compatible timing circuitry of the OTI-61 0 and OTI-611 are processed
and used to latch the counter value, which is the corresponding joystick position information.
The OTI-61 0 and OTI-611 support two game controllers, each with two buttons, and one group of positional data
containing X andY 12-bit direction information. The two groups of X,Y positional data are latched into four
register addresses: 08h, 09h, OAh, and OBh. When this information is needed, stable and accurate position data
can be read out from these registers.
Button state information may be read from register OCh (bits [3 :0]).
4.2.2
ANALOG MODE
In the analog mode, game control information can be acquired by either reading the PCI-mapped register OOh (or
register 01 h, which presents the same information as OOh), or the fixed game port address 200h and 201 h.
Button Signals and unprocessed position signals are passed to the data bus. Software will keep polling these
registers for information and does the time delay calculation.
Software polling in the analog mode is slower than for the hardware polled digital mode.
Oak Technology
4-3
Technical Specification
OTI-610/0TI-611
4.2.3
GAME PORT INTERFACE DESCRIPTION
BUTAl J--L=f''--BUTAl ~:L--_
BUTBl J--L=f'''---BUTB2 J--L'Z'''---.-..J\j
To Game Port
Connector
GjXl
GjYl
GjX2
GjY2
To Game Port
Connector
011-610
011-611
Figure 4-2: OTI-610/0T/-611 Game Port Interface Simplified Diagram
The GJX and GJY input pins are for analog voltage inputs from the joystick. Interfacing to the joystick requires an
RC timing network at each input. Consult the OTI-61 O/OTI-611 Reference Schematics available from Oak
Technology for component values.
The Joystick Button input pins are internally pulled up to Vdd. A contact de-bounce circuit is recommended on
each button signal. Consult the OTI-61 O/OTI-611 Reference Schematics available from Oak Technology for
component values.
Control of the game port is obtained through the game port registers, as listed below. Further details about these
registers and the degree of control are available in Chapter 7.
The Standard Game Port register implements the standard analog game port functions. It is accessible from either
the Standard Game Port I/O address of 200h/201 h or the PCI Offset address of OOh/01 h.
Game Port Registers:
Host Offset
Size
Description
OOh
B bit
Standard Game Port
O1h
B bit
Standard Game Port
OBh-09h
16 bit
Digital Game Port I & II X Position
OAh-OBh
16 bit
Digital Game Port I & II Y Position
OCh
B bit
Game Port Control
Address
Size
Description
200h
B bit
Standard Game Port
201h
B bit
Standard Game Port
Oak Technology
4-4
Technical Specification
Peripheral Interfaces
Standard Game Port
Host Offset: OOh, 01 h, 200h, and 0201 h
Bit
7
6
5
4
3
2
1
0
RlW
PBB2
PBB1
PAB2
PAB1
PBY
PBX
PAY
PAX
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
PBB2
Port B Button 2
1 - button pressed; 0 - button unpressed
PBB1
Port B Button 1
1 - button pressed; 0 - button unpressed
PAB2
Port A Button 2
1 - button pressed; 0 - button unpressed
PAB1
Port A Button 1
1 - button pressed; 0 - button unpressed
PBY
Port BY-axis
1 - ti mer active; 0 - ti mer inactive
PBX
Port B X-axis
1 - timer active; 0 - timer inactive
PAY
Port A Y-axis
1 - timer active; 0 - timer inactive
PAX
Port A X-axis
1 - timer active; 0 - timer inactive
A write to this port will generate a trigger pulse to the internal 558-like timer. A read from this port will get the
current Game Port Button and position status.
At Power On reset, the game port with no hardware polling enabled is set. To use the hardware polling mode,
the driver needs to write a value of 1/1" into register OCh, bit position 7.
To use port 200h/201 h, register OCh, bit position 6 needs to be set to a value of 1/1." The two modes cannot be
activated at the same time. The Power On default value is "0."
4.3
DECODED AUDIO INPUT PORT (PS PORT)
The FS port is intended for use as an input for digital audio serial data in the FS format. An example of digital
audio data that may be input to this port is decoded MPEG digital audio serial data.
The FS port interface consists of three signals:
BCLK - Digital Audio Bit Clock
LRCLK - Left/Right Channel (UR) Clock
SDATA - Digital Audio Serial Data
These signals may be connected directly the Digital Audio Bit Clock, Left/Right Channel Clock, and Digital Audio
Serial Data pins of an FS bus.
Oak Technology
4-5
Technical Specification
011-610/011-611
BCLK
~9
151
J
5~;~~ ::=~115:0===:=====ii
2
1 50"lg"ltal
Audio Device
I
OTI-610
OTI-611
Figure 4-3: OT/-61 O/OT/-611 J2S Interface Simplified Diagram
BCLK
LRCLK
50ATA
149
iSl
MPEG
1<;0
Decoder
I
OTI-610
OTI-611
Figure 4-4: OTJ-61 O/OT/-611 MPEG Decoder Interface Simplified Diagram
The different modes of operation of the FS port are controlled by five bits in the OTI-61 O/OTI-611 Host Offset
register 004Fh (see Chapter 7 for more details). The format set in this register must match the input source type
for correct operation.
Oak Technology
4-6
Technical Specification
Peripheral Interfaces
Host Offset Register: 004Fh
Bit
7
6
5
4
3
2
1
0
RIW
Reserved
Reserved
Reserved
ORDER
PACK
LRPOL
EDGE
CYCDLY
Initial
0
0
0
1
0
1
1
0
Bit
Description
Comment
ORDER
Bit Order
1 - MSB first on the data stream; 0 - LSB first on the data stream
PACK
Packing Direction
LRPOL
Left/Right Channel Polarity
EDGE
Edge Control
CYCDLY
Clock Cycle Delay
1 - Forward Packing: Collect data from the start point of UR
signal;
o - Backward Packing: Collect data from the end point of UR
signal
1 - HIGH indicates LEFT channel when LRCLK is HIGH;
LEFT channel when LRCLK is LOW
o - LOW indicates
1- Latch on RISI NG edge
on FALLI NG edge
o - Latch
1 - One clock delay relative to UR
o - No delay relative to UR
The example in Figure 4-5 shows the Right Justified mode. Data is valid on the rising edge of the BCLK signal.
The MSB of the data is delayed 16 BCLK cycles from an LRCLK transition. Since there are 64 BCLK cycles per
LRCLK period, the LSB of the data is right justified to the next LRCLK transition. This mode may be set with a
value of 16h in register 4Fh.
The default mode set by the OTI-610/011-611 is 16h in register 4Fh.
LRCLK
-11------------------------------,
BCLK
rLfA
SDATA
~_________R_i9_~_Ch_a_nn_el____________~~~---
i'LIL
~ 15 I 14 I 13 I 12 I " I 10 I 9 I 8 I 7 I 8 I 5 I 4 I 3 I 2 I I I 0 V# X~ 15 I 14 I 13 I 12 I " I 10 I 9 I 8 I 7 I 6 I 5 I 4 I 3 I 2 I I I 0
vI/;-:JJJl
Right JustHied Mode
Figure 4-5: 125 Right Justified Data Input Format
Oak Technology
4-7
Technical Specification
011-610/011-611
The example in Figure 4-6 shows the FS Justified mode. Data is valid on the rising edge of BLCK. LRCLK is high
for the Left Channel. In this mode, the MSB is left justified to an LRCLK transition, but with a single BCLK period
delay. This mode may be set with a value of 1 Bh in register 4Fh .
. /1
Left Channel
-
LRCLK
-1I1'--_______________
.I'jJ'I,
BCLK
lJlr
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ''/
1,-
Right Channel
,2S Justified Mode
Figure 4-6: fl5 Justified Data Input Format
The example in Figure 4-7 shows the Left Justified mode. Data is valid on the rising edge of BCLK. This is similar
to the FS Justified mode, but with no BCLK period delay. Also, LRCLK is high for the Left Channel. This mode
may be set with a value of 1Dh in register 4Fh.
LRCLK
1~
)
-/.
BCLK
SDATA
_____
R_i9h_tC_h_an_ne_I_ _ _ _ _ _ __
lJlr
7L// 115 114 113 112 111 110 I
9
I I I 1 I I 3 I 2 I 1 I 0 VII XI 114 113 112 111 110 I I 1 I I I 13 12 I 1 I 0 VlO X
8
7
6
5
4
IS
9
8
7
6
5
4
Left Justified Mode
Figure 4-7: fl5 Left Justified Data Input Format
Digital audio serial data in the PS format consists of digital audio samples at either a 32-KHz, 44.1-KHz, or 48KHz rate. The OTI-61 0/OTI-611 samples the incoming data in register 4Eh to determine the sample rate, and
writes a sample rate selection into bits[l :0] of register 49h as follows:
11 = 44.1 KHz
10 = 48 KHz
OX = 32 KHz
The OTI-61 O/OTI-611 will perform sample rate conversion on the incoming digital audio serial data stream and
add it to the digital mix of other digital audio channels.
In the case where the OTI-61 0/OTI-611 is operating in an AC '97 system (see table in Chapter 3, Section 3.1), the
output sample rate of the digital mixer would be set at 48 KHz. If the incoming J2S data were 48 KHz, no
conversion would be necessary.
If the OTI-61 0/OTI-611 were not operating in an AC '97 system, the output sample rate of the digital mixer would
be set at 22.05 KHz. Sample rate conversion would be done between the incoming PS sample rate and the
outgoing sample rate.
Oak Technology
4-8
Technical Specification
Peripheral Interfaces
4.4
PROGRAMMABLE INPUT/OUTPUT PORT
The OTI-6l O/OTI-6ll provides two general purpose, TTL-compatible programmable input/output pins and PI01. The pin direction is set by programming register 43h in the OTI-6l O/OTI-6ll.
PlOD
Host Offset: 0043 h
Bit
7
6
5
4
3
2
1
0
RlW
SRESET
SSIDWR
MCLKSR
Reserved
DCl
PIOl
DCO
PIOO
Initial
0
0
0
0
0
X
0
X
Bit
Description
Comment
SRESET
Software Reset
SSIDWR
Subsystem I D
Subsystem Vendor ID
Write Control
MCLKSR
Main Clock (MCLK) source control
PIO[1:0]
General Purpose I/O
ReadlWrite data to/from external PIO pins
DCl
Direction Control 1
o - PIOl
DCO
Direction Control 0
o - PIOO is input
1 - Reset of OTI-61l simi lar to use of PC! Reset Signal RST#
TOGGLE from 0 to 1 and back to 0
1 - Enable Write of Subsystem 10 and Subsystem Vendor ID Registers
o - Disable Write
1- External MCLK Crystal
o - Modem Clock Source (36.864 MHz)
1 - PIOl is output
is input
1 - PIOO is output
FC is an acronym for Inter-IC bus. The FC bus is an inexpensive, 2-wire communications link developed by
Philips Semiconductors as a simple means for connecting a CPU to peripheral chips or as a link between
integrated circuits. The user may program these pins to implement a simple software-controlled FC interface to
one FC compatible peripheral device. FC has a fairly low bandwidth, so it is usually used as a control bus, not a
high-speed data transfer bus.
The bus physically consists of two active wires and a ground connection. The active wires, SDA and SCl, are bidirectional. SDA is the serial data line and SCl is the serial clock line. Every component hooked up to the bus
has its own unique address. Each of these chips can act as a receiver and/or transmitter depending upon its
functional ity.
More information on the FC bus can be obtained by contacting Philips Semiconductor. A useful FAQ on the FC
bus also exists at http://www.ecn.uoknor.edu/-jspatridfaqs/i2c.fac
Either PlOD or PIOl may be software controlled and used to implement either of the SDA and SCl signals of the
FC protocol.
Oak Technology
4-9
Technical Specification
011-610/011-611
PIOO M--'1.....
1 _ _ _ _+
PIOl I+--llI.:%--4_ _ _--+
OTI-610
OTI-611
Figure 4-8: OT/-61 O/OT/-611 PC Interface Simplified Diagram
4.5
DAA INTERFACE
The function of the Data Access Arrangement (DAA) is to interface a fax/data modem and its modem codec to the
analog public switched telephone system (PSTN). In many countries, the DAA is required to be approved by the
government authorities in a process known as "homologation." The approval requirements dictate the
components, and possibly the actual design, that may be used to construct an approved DAA. The OTI-611
provides pre-defined pin functions to support the majority of DAA designs that may be approved throughout the
world.
The pins listed in the following table are intended to support the HSP fax/data modem DAA functions, and as
such are available only on the OTI-611.
In addition to the pre-defined pin function support, there are three spare output pins and one spare input pin that
may be used in support of additional DAA functions or other special system functions.
Oak Technology
4-10
Technical Specification
Peripheral Interfaces
DAA Interface - 10 pins: 3 inputs, 7 outputs:
Pin Name
Pin #
Type
Description
RING_DET
158
I
Ring Detect - OTI-611 only
TTL level pulsed DC signal derived from AC Ringing Signal and equal to it in
frequency
LC_SENSE
160
I
Line Current Sense - OTI-611 only
TTL level (High) when line current is sensed
OFF_HOOK
159
0
Hook Relay Control - OTI-611 only
TTL level (High) to operate OFF HOOK relay
CID_RELAY
1
0
Caller ID Relay Control - OTI-611 only
TTL level (High) to operate CID relay
HDSET_REL
2
0
Handset Relay Control - OTI-611 only
TTL level (High) to operate HANDSET relay
CODEC_MODE
3
0
Codec Mode Select - OTI-611 only
Selects data mode for ST7546 Modem Codec
Spare Input Pin - TTL level input
Modem Wake Up Enable - This pin is internally pulled up (enabled) and may
be tied to Ground to disable the modem wake up feature following a Power
Down operation.
ISPARE
153
I
OSPARE 0
155
0
Spare Output Pin - TTL level output
OSPARE 1
156
0
Spare Output Pin - TTL level output
OSPARE 2
MONIT
157
0
Spare Output Pin - TTL level output
DSP Monitor (Diagnostic only)
The DAA interface output lines may be programmed via the OTI-611 Modem Index 2 register (External Outputs
register 2h) [15:0] bits.
The DAA interface input state is available by reading the appropriate bits in OTI-611 Index Register 7h.
The bit maps for these registers are given on the following page.
Oak Technology
4-11
Technical Specification
011-610/011-611
OFF_HOOK
CID_RELAY
HDSET_REL
COD EC..MODE
RING_DET
LC_SENSE
159
1
2
3
158
160
OSPAREO
OSPARE 1
OSPARE2
ISPARE
155
156
157
153
OTI-611
u
Figure 4-9: OTJ-611 DAA Interface Simplified Diagram
Modem Index 2 Register: (External Outputs Register 2h) [15:0J
Bit
15
14
13
12
11
10
9
8
RIW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPOUT2
SPOUTl
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RIW
SPOUTO
ST7546
HDSTRLY
CODPWR
SPKRMT
CODRST
CID
OHRLY
Initial
0
0
0
0
0
1
1
1
Bit
Description
SPOUT[2:0]
Spare Output Pins
5T7546
ST7546 Mode Select
HDSTRLY
Headset (Voice) Relay Control
CODPWR
Codec Power Down
5PKRMT
Speaker Mute Control
CODRST
Codec Reset
CID
Caller I D Relay Control
Active low
OHRLY
Off-Hook Relay Control
Active low
Comment
Software-controlled outputs
Controls CODEC_PIN on OTI-611. Connects to HCO pin on
ST7546 Modem Codec.
o = Codec Reset
Default value is 0007h.
Oak Technology
4-12
Technical Specification
Peripheral Interfaces
Modem Index Register 7h (Low Byte) Read: (Externailnput Register) [7:0]
Bit
7
6
5
4
3
2
1
0
Read
Reserved
Reserved
Reserved
Reserved
Reserved
ISPARE
LCSNS
RGDET
Initial
0
0
0
0
0
0
0
0
Bit
Description
ISPARE
Spare Input Pin
LCSNS
Line Current Sense
RGDET
Ring Detect
Comment
Reads the state of ISPARE pin of OTI-61010TI-611
DAA design is beyond the scope of this chapter. Consult the OTI-611 Reference Design Schematics for examples
of DAA design suitable for use with the OTI-611.
The defined DAA pin functions on the OTI-611 support the host signal processing based \l.34/V.34+ fax/data
modem software supplied with the OTI-611 , provided appropriate hardware is in the DAA circu it. The DAA and
HSP\l.34I\1.34+ software are used together to build a completely functional and approvable V.34I\1.34+ fax/data
modem, similar to that in Figure 4-10 below.
OFF_HOOK
CID_RELAY
HDSET_REL
CODEC_MODE
RING_DET
LC_SENSE
159
1
2
3
158
160
OSPAREO
OSPARE 1
OSPARE2
ISPARE
155
156
157
153
MPWDN#
MRESETI
5
MSDO
MSDI
MSCLK
MFS
MMCLK
011-611
DAA
~
12
38
HCO
HC1
PWRDWN#
RESEll
9
41
42
3
4
9
DIN
DOUT
SCLK
FS
MCLK
--J416
11
8
7
6
-;:
........
TIP
RING
TX+ I-TX· r--RX+ ~
RX-
SG7546
TQFP44 PKG
Figure 4-10: OTI-611 Fax/Data Modem Hardware Implementation Simplified Example
Oak Technology
4-13
Technical Specification
011-610/011-611
(This page intentionally left blank)
Oak Technology
4-14
Technical Specification
MEMORY INTERFACE
CHAPTER 5
The OTI-61 a and OTI-611 support an external memory interface to either 2MB of ROM or 2MB of SRAM. Data
is transferred to the internal DSP 16 bits at a time (word transfer).
This interface is typically used for the optional DSP-based wavetable synthesizer Sound Sample Set ROM.
5.1
EXTERNAL WAVETABLE SAMPLE SET ROM INTERFACE
The optional DSP wavetable synthesizer uses a 2MB (1 Mx16) ROM (UM23C161 DaM in the example below) to
store samples of the 128 General MIDI (GM) instruments sounds and 47 percussion, or drum kit, sounds. In use,
the DSP wavetable synthesizer generates musical sounds by reading the samples contained in the ROM, processing those samples within the DSP-based synthesizer engine, and then sending the processed samples to the
digital mixer of the OTI-61 a and OTI-611. From there, the digitally mixed data is sent to the audio codec for
playback.
WDMCElI
ROMCE#
ROMOE#
V c c - BYTE#
L~
WDMA[19:0)
ROMA(19:0)
ROMD(15:O)
WDMD[15:0]
ROM
1M x 16
UM23C16100M
Of equivalent
OTI-610
OTI-611
Figure 5-1: OTl-610/0TI-611 ROM Simplified Interface Diagram
Sound Sample Set ROM data to the DSP-based synthesizer is obtained 16 bits at a time. Therefore, the BYTE
mode of the ROM has been disabled by connecting BYTE# to Vcc. Otherwise, interfacing to the ROM is direct.
Oak Technology provides the Sound Sample Set data patterns required for the ROM as part of the OTI-61 a or
OTI-611 software drivers to customers who choose to use the optional DSP-based wavetable synthesizer.
.
Alternatively, the wavetable Sound Sample Set could be stored in SRAM. See Section 5.2 below.
ROM interface timing information is provided in Chapter 1a.
The Sound Sample Set data has been specifically developed for use with the OTI-610 and OTI-611 and is not
suitable for use with any other wavetable synthesizer. .
Oak Technology
5-1
Technical Specification
OTI-610/0TI-611
5.2
SRAM MEMORY INTERFACE TIMING
The SRAM interface capability permits flexibility in the use of the OTI-61 0 and OTI-611 for a variety of future
appl ications that may be offered or developed for the OTI-61 0 and OTI-611 .
Figure 5.2 below show the basic connections. The implementation is shown for two 512Kx16 SRAM devices.
The OTI-61 0/OTI-611 provides two Chip Enables (WDMCE1 # and WDMCE2#) and uses the high-order bit
WDMA[19] as a Write Enable (SRAM WE#) to the SRAM. Data is transferred 16 bits at a time.
SRAM interface timing information is provided in Chapter 10.
cs#
,.--- OE#
WEI
WDMCE2#
WDMCE1#
WDMOE#
WDMA[19)
WDMA[18:0)
-
WDMA[18:0)
WDMD[15:0)
WDMD[15:0) """-
S12x16SRAM
- f - f--- cs#
'--f--- OE#
'--
WEI
WDMA[18:0)
WDMD[15:0)
OTI·610
OTI·611
512""16 SRAM
Figure 5-2: OTI-61 O/OTl-611 SRAM Simplified Interface Diagram
Oak Technology
5-2
Technical Specification
PIN DESCRIPTIONS
CHAPTER 6
6.1
OTI-610 PINOUT DIAGRAM
o
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
NC
NC
VSS
NC
NC
NC
NC
NC
VSS
NC
NC
PIOO
PIOl
VDD
XTAL21
XTAL20
VSS
AFS
ASDO
ASDI
ASCLK
ACONVl
AMCLK
ARESET#
XTAL 11
XTAL 10
APWDN#
PXTALMI
PXTALMO
MUTEOUT
VDD
MUTRQ#
WDMA6
WDMAS
WDMA4
WDMA3
WDMA2
WDMA1
WDMAO
VSS
WDMCE2#
WDMOE#
WDMCE1#
WDMD15
WDMD14
VDD
WDMD13
WDMD12
WDMDll
WDMD10
WDMD9
WDMD8
VSS
WDMD7
WDMD6
WDMD5
WDMD4
WDMD3
WDMD2
WDMDl
WDMDO
ADO
ADl
AD2
AD3
VSS
AD4
VDD
ADS
AD6
011-610
(Top View)
RST#
INTAt
INTB#
LCLK
VSS
GNT#
REQ#
~g~~
~~~~Oa;~~
~2~~~~~
~
~
i~~~~o~
~~~~=
AID
2~~a~
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
OOOO~OOOOO=~OO~OOOOOO~~~~@wQO~~OOOOO~OOO
««>««>U_«>«««U>~_~O~>U~««<>«<
Figure 6-1: OTI-610 Pinout
Oak Technology
6-1
Technical Specification
011-610/011-611
6.2
OTI-611 PINOUT DIAGRAM
·2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CID_RELAY
HDSET_RELAY
CODEC_MODE
VSS
MPWDN#
MMCLK
MFS
MSCLK
MSDO
VSS
MSDI
MRESET#
PIOO
PIOl
VDD
XTAL 21
XTAL20
VSS
AFS
ASDO
ASDI
ASCLK
ACONV1
AMCLK
ARESET#
XTAL 11
XTAL10
APWDN#
PXTALMI
PXTALMO
MUTEOUT
VDD
MUTRQ#
RST#
INTAI
INTB#
LCLK
VSS
GNT#
REQ#
011-611
(Top View)
~g~~
~~~~Oa~~~
~2~~~~~
,..
~
I~~~~o~
~~~~=
WDMA6
WDMAS
WDMA4
WDMA3
WDMA2
WDMAl
WDMAO
VSS
WDMCEU
WDMOE#
WDMCE1#
WDMD15
WDMD14
VDD
WDMD13
WDMD12
WDMDll
WDMD10
WDMD9
WDMD8
VSS
WDMD7
WDMD6
WDMD5
WDM04
WDMD3
WDMD2
WDMDl
WDMDO
ADO
ADl
AD2
AD3
VSS
A04
VDD
ADS
AD6
AD7
g~~O~
120
1 19
1 18
1 17
1 16
1 15
114
113
1 12
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
OOOO~OOOOO=~OO~OOOOOO=~~~~~OeO~~OOOOO~OOO
««>««>u_«>«««u>~_~
~>U~««<>«<
_NM~~~~=~O_NM~~~~=~O-NM~~~~=~O_NM~~~I~=~o
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I~~~=
Figure 6-2: OTI-611 Pinout
Oak Technology
6-2
Technical Specification
Pin Descriptions
6.3
PIN GROUPING BY FUNCTION
6.3.1
PIN NAMES BY PIN NUMBER
Signal Name
Pin #
Type*
CID_RELAY
1
0
Caller 10 Relay control - OTI-611
HDSET_REL
2
0
Handset Relay control - OTI-611
CO DEC_MODE
3
0
Mode select for ST7546 Modem Codec - OTI-611
Vss
4
I
MPWDN#
5
0
Modem Codec Power Down - OTJ-611
MMCLK
6
0
Modem Codec Main Clock - OTI-611
MFS
7
I
Modem Codec Frame Sync - OTI-611
MSCLK
8
I
Modem Codec Serial Clock - OTI-611
MSDO
9
0
Vss
10
I
Ground input
MSDI
11
I
Modem Codec Serial Data In - OTI-611
MRESET#
12
0
Modem Codec Reset - OTI-611
PIOO
13
I/O
PIOO (1 2C clock - programmed output)
PIOl
14
I/O
PIOl (l 2C data - programmed output)
Vdd
15
I
Voltage input
XTAL21
16
I
Crystal 2 In (36.864 MHz) - ModemlDSP
Required - Power on default for DSP clock
XTAL20
17
0
Crystal 2 Out (36.864 MHz) - ModemlDSP
Required - Power on default for DSP clock
Vss
18
I
AFS
19
1/0
Audio Codec Frame Sync
Output for AC 197 Codecs
Input for all other Codecs
ASDO
20
0
Audio Codec Serial Data Out
ASDI
21
I
Audio Codec Serial Data In
ASCLK
22
I
Audio Codec Serial Clock
ACONVl
23
I
Audio Codec Conversion Clock 1
Note:
Function
Ground input
Modem Codec Serial Data Out - OTI-611
I
Ground input
* The pins are classified as Input (I), Output (0), or Input/Output (I/O)
# Indicates an active level low Signal pin
Oak Technology
6-3
Technical Specification
OTI-610/0TI-611
PIN NAMES BY PIN NUMBER (Cont~)
Signal Name
Pin #
Type*
AMCLK
24
0
Audio Codec Main Clock
ARESET#
25
0
Audio Codec Reset
XTAL11
26
I
XTAL10
27
0
Crystal 1 Out (11.2896 MHz) - Audio CodecClock
Not required when using AC 197 Codec
APWDN#
28
0
Audio Codec Power Down
PXTALMI
29
I
Crystal Main In - DSP (optional 33.0 - 40.0 MHz)
If used, SW must change default selection (see XTAL2t)
PXTALMO
30
0
Crystal Main Out - DSP (optional 33.0 - 40.0 MHz)
If used, SW must change default selection (see XTAL20)
MUTEOUT
31
0
Mute Output
Vdd
32
I
Voltage Input
MUTRQ#
33
I
Mute Request
RST#
34
I
Reset Input from PC! Bus
INTA#
35
0
Audio Interrupt
INTB#
36
0
Modem Interrupt - OTI-611 only
LCLK
37
I
PCI Clock
Vss
38
I
Ground input
GNT#
39
I
Bus Grant
REQ#
40
0
Bus Request
AD31-AD28
41-44
I/O
Address/Data bus
Vss
45
I
AD27-AD24
46-49
I/O
Vdd
50
I
CBE3#
51
I/O
IDSEL#
52
I
AD23-AD22
53-54
I/O
Vss
55
I
Note:
Function
Crystal 1 In (11.2896 MHz) - Audio Codec clock
Not required when using AC 197 Codec
Ground input
Address/Data bus
Voltage input
Command/Byte_Enable 3
Initialization Device Select
Address/Data bus
Ground input
* The pins are classified as Input (I), Output (0), or Input/Output (1/0)
# Indicates an active level low signal pin
Oak Technology
6-4
Technical Specification
Pin Descriptions
PIN NAMES BY PIN NUMBER (Cont'd)
Signal Name
Pin #
Type*
AD21-AD16
56-61
1/0
Address/Data bus
CBE2#
62
1/0
Command/Byte_Enable 2
Vss
63
I
FRAME#
64
1/0
Frame, start of cycle
IRDY#
65
1/0
Initiator Ready
TRDY#
66
1/0
Target Ready
DEVSEL#
67
1/0
Device Select
STOP#
68
1/0
Stop the current cycle
Vdd
69
I
CBE1#
70
1/0
Command/Byte_Enable 1
PAR
71
0
Parity Even
AD15-ADll
72-76
1/0
PCI Address/Data bus
Vss
77
I
AD10-AD8
78-80
1/0
PC! Address/Data bus
CSEO#
81
1/0
Command/Byte_Enable 0
AD7-AD5
82-84
1/0
PC! Address/Data bus
Vdd
85
I
AD4
86
1/0
Vss
87
I
AD3-ADO
88-91
1/0
PCI Address/Data bus
WDMDO-WDMD7
VENDIDO-VENDID7
92-99
1/0
I
External SRAMIROM Data
Power Up: Subsystem Vendor 10[0:7]
Vss
100
I
WDMD8-WDM013
VENOID8-VENDID13
101-106
1/0
I
Vdd
107
I
WDMD14-WOMD15 '
108-109
VENDID14-VENOI015
Note:
1/0
I
Function
Ground input
Voltage input
Ground input
Voltage input
PC! Address/Data bus
Ground input
Ground input
External SRAMIROM Data
Power Up: Subsystem Vendor 10[8:13]
Voltage input
External SRAMIROM Oata
Power Up: Subsystem Vendor ID[14:15]
* The pins are classified as Input (I), Output (0), or Input/Output (1/0)
# Indicates an active level low signal pin
Oak Technology
6-5
Technical Specification
OTI-610/0TI-611
PIN NAMES BY PIN NUMBER (Cont'd)
Signal Name
Pin #
Type*
WDMCE1#
110
0
External SRANVROM Chip Enable 1
WDMOE#
111
0
External SRANVROM Output Enable
WDMCE2#
112
0
External SRANVROM' Chip Enable 2
Vss
113
I
WDMAO
BUS_MODE
114
WDMA1
11 S
WDMA2-WDMA4
BODID[0:2]
116-118
WDMAS
MCODEC (0)
119
WDMA6
MCODEC (1)
120
GjX1, GjY1
0
I
0
I
0
I
0
I
0
Function
Ground input
External SRANVROM Address
Power Up: 1 = PCI Bus; 0 = AuxBus
External SRANVROM Address
Power UP: Game Port Enable/Disable Selection
1 = Game Port Enabled (no internal pullup);
o = Game Port, including configuration, Disabled
External SRANVROM Address
Power Up: Board ID[0:2]
External SRANVROM Address
Power Up: Codec Selection bit 0
I
External SRANVROM Address
Power Up: Codec Selection bit 1
121-122
I
joystick 1 location: X, Y
AVss
123
I
Analog Ground input
AVdd
124
I
Analog Voltage input
GjX2, GjY2
12S-126
I
joystick 2 location: X, Y
WDMA7
MCODEC (2)
127
WDMA8-WDMA11
SSYSI DO-SSYSI D3
128-131
Vss
132
WDMA12-WDMA18
SSYSID4-SSYSID10
133-139
WDMA[19]
WEMWE#
140
0
0
Vdd
141
I
Voltage input
BUTA1
142
I
Game Port I Button A
Vss
143
I
Ground input
Note:
0
I
0
External SRANVROM Address
Power Up: Codec Selection bit 2
I
External SRANVROM Address
Power Up: Subsystem ID[0:3]
I
Ground input
0
I
External SRANVROM Address
Power Up: Subsystem 10[4:10]
External ROM Address
External SRAM Write Enable
Diagnostic
* The pins are classified as Input (I), Output (0), or Input/Output (1/0)
# Indicates an active level low signal pin
Oak Technology
6-6
Technical Specification
Pin Descriptions
PIN NAMES BY PIN NUMBER (Cont'd)
Signal Name
Pin #
Type*
BUTB1
144
I
Game Port I Button B
BUTA2
145
I
Game Port II Button A
BUTB2
146
I
Game Port II Button B
RxD
147
I
MIDI Receive data
TxD
148
0
MIDI Transmit data
BCLK
149
I
12 S Bit Clock
SDATA
150
I
12 S Serial data
LRCLK
151
I
12 S
Vss
152
I
Ground input
ISPARE
153
I
Spare Input pin
Enable Modem Wake-Up - via internal Ring Detect
This feature set by external connection to ground
Vdd
154
I
Voltage input
OSPARE [1 :0]
155-156
0
Spare Output pins 0 and 1
MONIT/OSPARE2
157
0
DSP MIPS Monitor (diagnostic only)
Spare Output pin 2
RING_DET
158
I
OFF_HOOK
159
0
Hook Relay control - OTI-611 only
LC_SENSE
160
I
Line Current detect - OTI-611 only
Note:
Function
Left/Right Clock
Ring Detect - OTI-611 only
* The pins are classified as Input (I), Output (0), or Input/Output (I/O)
# Indicates an active level low signal pin
Oak Technology
6-7
Technical Specification
OTI-610/0TI-611
6.4
PIN DESCRIPTIONS BY INTERFACE
6.4.1
PCI INTERFACE
PCllnterface - 49 pins: 4 inputs, 4 outputs, 41 I/O
Pin Name
Pin #
Type
I/O
Description
LCLK
37
TTL
I
PCI CLOCK. Used to provide timing for all transactions on PCI. All
other PC! signals are sampled on the rising edge of LCLK, and all
timing parameters are defined with respect to the rising edge of
LCLK.
RST#
34
TTL
Schmidt
I
RESET. This signal resets all internal state machines and default
registers. Also used to latch-in configuration register values.
FRAME#
64
PCI
I/O
CYCLE FRAME. Used to indicate the beginning and duration of an
access. This signal is an input during Slave mode and an output
during Master mode.
INITIATOR READY. Used to indicate the initiating agent's ability to
complete the current data phase of the transaction. I ROY # is used
in conjunction with TROY#. This signal is an input during Slave
mode and an output during Master mode.
IROY#
65
PC!
I/O
TRDY#
66
PC!
I/O
STOP#
68
PC!
I/O
IOSEL#
52
TTL
I
OEVSEL#
67
PCI
I/O
DEVICE SELECT
PAR
71
PCI
0
PARITY. Active high even parity across AC[31 :0] and CBE#[3:0]
AO[31:0]
Refer to
pin table
PC!
I/O
Address/Data Bus
CBE#[3:0]
Refer to
pin table
PCI
I/O
Command/Byte_Enable
REQ#
40
PCI
0
REQUEST. Output to the PC! bus arbiter to request for the bus.
GNT#
39
TTL Pullup
I
INTA#
35
PCI
0
Audio Interrupt
INTB#
36
PCI
0
Modem Interrupt
TARGET READY. Used to indicate the target agent's ability to
complete the current data phase of the transaction. TROY# is used
in conjunction with IROY#.
STOP. Active low signal used by the current Slave to request the
Oak Technology
current Master to stop the current transaction. This signal is an
output during Slave mode and an input during Master mode.
fNITIALIZATION DEVICE SELECT. Active high chip select in lieu of
the upper 24 address lines during configuration Read and Write
transactions.
GRANT. Input from the bus arbiter to indicate that the bus has
been granted.
6-8
Technical Specification
Pin Descriptions
6.4.2
MPEG AND MIDI INTERFACE
MPEG/MIDllnteriace - 5 pins: 4 inputs, 1 output
Pin Name
Pin #
Type
I/O
BCLK
149
TTL
I
12 5 Digital Audio Bit Clock
LRCLK
151
TTL
I
125 Left/Right Channel (UR) Clock
5DATA
150
TTL
I
125 Digital Audio Serial Data
RxD
147
TTL
Schmidt
I
MIDI Receive Serial Data
TxD
148
18mA
0
MIDI Transmit Serial Data
6.4.3
Description
EXTERNAL MEMORY INTERFACE
Memory Interface (for ROM or RAM) - 39 pins: 23 outputs, 16 lias
Pin Name
Pin #
Type
I/O
WDMCE1#
110
4mA
0
External SRAMIROM Chip Enable 1
WDMCE2#
112
4mA
0
External SRAMIROM Chip Enable 2
WDMOE#
111
4mA
0
External SRAMIROM Output Enable
WDMA[19]
WEMWE#
140
4mA
0
External ROM Address
External SRAM Write Enable
WDMD[15:0]
VENDID[15:0]
Refer to
pin table
4mA
pullup
1/0
I
WDMA[O]
BUS_MODE
114
4mA
0
I
External SRAMIROM Address
1 = PCI, 0 = AuxBus
4mA
0
I
External SRAMIROM Address
Power Up: Game Port Enable/Disable Selection
1 Game Port Enabled (Internal pullup)
= Game Port, and configuration, Disabled
WDMA[1]
11S
0
Description
External SRAMIROM Data
Power Up: Subsystem Vendor 10[15:0]
o
=
WDMA[4:2]
BODID[2:0]
Refer to
pin table
4mA
0
I
External SRAMIROM Address
Power Up: Board 10
WDMA[S]
MCODEC (0)
119
4mA
0
I
External SRAMIROM Address
Refer to Codec Support Table
WDMA[6]
MCODEC (1)
120
4mA
0
I
External SRAMIROM Address
Refer to Codec Support Table
WDMA[7]
MCODEC (2)
127
4mA
0
External SRAMIROM Address
Refer to Codec Support Table
WDMA[18:8]
SSYSID[10:0]
Refer to
pin table
4mA
Oak Technology
I
0
I
External SRAMIROM Address
Power Up: Subsystem 10[10:0]
6-9
Technical Specification
011-610/011-611
The input data on WDMA[7:5] pins is used at Power Up to inform the OTI-61 0/OTI-611 what codec or codec
combination is attached to the codec interface. The data is also placed in the OTI-61 0/OTI-611 Status register
42h. This data is then used by the software driver to configure the attached codec(s).
The table below presents the codec options supported.
011-610/011-611 Signal Name
Codec Supported
6.4.4
WDMA[7]
(MCODEC bit 2)
WDMA[6]
(MCODEC bit 1)
(MCODEC bit 0)
AD1843 as Audio/Modem Codec
0
0
0
Reserved
0
0
1
AD1843 as Audio Codec plus
ST7546 Modem Modec
0
1
0
Reserved Audio Codec plus
ST7546 Modem Codec
0
1
1
STLC7549 Audio/Modem Codec
1
0
0
OTI-612 AC 197 Audio/Modem Codecor
Any AC 197 Audio/Modem Codec
1
0
1
AC 197 Audio Codec plus
ST7546 Modem Codec
1
1
0
Reserved
1
1
1
WDMA[S]
AUDIO CODEC INTERFACE
Audio Codec Interface - 8 pins: 4 inputs, 4 outputs
Pin Name
Pin #
Type
I/O
AMCLK
24
4mA
0
Audio Codec Main Clock
ASCLK
22
TIL
I
Audio Codec Serial Clock
AFS
19
TIL
0
I
Audio Codec Frame Sync
Output for AC '97 Codecs
Input for all other Codecs
Description
ASDI
21
TIL pullup
I
Audio Codec Serial Data In
ACONV1
23
TIL
I
Audio Codec Conversion Clock (for AD1843 Codec)
ASDO
20
4mA
0
Audio Codec Serial Data Out
ARESET#
25
4mA
0
Audio Codec Reset
APWDN#
28
4mA
0
Audio Codec Power Down
Oak Technology
6-10
Technical Specification
Pin Descriptions
6.4.5
CLOCKS AND MISCELLANEOUS INTERFACE
Clock and Miscellaneous Interface - 8 pins: 4 inputs, 4 outputs
Pin Name
Pin #
Type
I/O
PXTALMI
29
TIL
I
PXTALMO
30
2mA
0
Crystal Main Out (33 - 40 MHz) - DSP
Optional
XTAL11
26
TIL
I
Crystallin (11.2896 MHz) - Audio
Not required when using AC 197 Codec
XTAL10
27
2mA
0
Crystal lOut (11.2896 MHz) - Audio
Not required when using AC 197 Codec
XTAL21
16
TIL
I
Crystal 2 In (36.864 MHz) - ModemlDSP
Required - Power on default for DSP clock
XTAL20
17
2mA
0
Crystal 2 Out (36.864 MHz) - ModemlOSP
Required - Power on default for DSP clock
MUTRQ#
33
TIL
Schmidt
I
Mute Request
MUTEOUT
31
4mA
0
Mute Output
6.4.6
Description
Crystal Main In (33 - 40 MHz) - DSP
Optional
DAA INTERFACE
OAA Interface - 8 pins: 3 inputs! 5 outputs
Pin Name
Pin #
Type
I/O
RING_OET
158
TTL
I
Ring Detect - OTI-611
LC_SENSE
160
TTL
I
Line Current Sense - OTI-611
ISPARE
153
TTL
I
Spare Input Pin
Modem Wake Up - via internal Ring Detect
Set to ground to enable this feature
OFF_HOOK
159
4mA
0
Hook Relay Control - OTI-611
ClD_RELAY
1
4mA
0
Caller 10 Relay Control - OTI-611
HDSET_REL
2
4mA
0
Handset Relay Control - OTI-611
OSPARE[l :0]
156,155
4mA
0
Spare Output Pins
MONIT/OSPARE2
157
4mA
0
OSP Monitor (diagnostic only)
Spare Output Pin
Oak Technology
Description
6-11
Technical Specification
OTI-610/0TI-611
6.4.7
MODEM CODEC INTERFACE
Modem Codec Interface - 8 pins: 3 inputs,S outputs
Pin Name
Pin #
Type
1/0
MMCLK
6
4mA
0
MSCLK
8
TIL
I
Modem Codec Serial Clock - OTI-611 only
MFS/ACONV2
7
TIL
I
I
Modem Codec Frame Sync - OTI-611
Modem Codec Conversion Clock II (For AD1843 Codec)
MSDI
11
TIL
I
Modem Codec Serial Data In - OTI-611
MSDO
9
4mA
0
Modem Codec Serial Data Out - OTI-611
MRESET#
12
4mA
0
Modem Codec Reset - OTI-611
MPWDN#
5
4mA
0
Modem Codec Power Down - OTI-611
CODEC_MODE
3
4mA
0
Mode Select for ST7546 Modem Codec
6.4.8
Description
Modem Codec Main Clock - OTI-611
PIO AND GAME PORT INTERFACE
Pia/Game Interface - 10 pins: 8 inputs, 2 I/Os
Pin Name
Pin #
Type
1/0
PIOO
13
TIL Pullup
4mA
0
PIOl
14
TIL Pullup
4mA
0
BUTA1, BUTBl
142,144
TIL Pullup
I
Game Port 1 buttons
GjX1, GjY1
121-122
Analog
I
joystick 1 location: X, Y
BUTA2, BUTB2
145-146
TIL Pullup
I
Game Port 2 buttons
GjX2, GjY2
125-126
Analog
I
joystick 2 location: X, Y
Oak Technology
I
I
Description
PIOO - Input
PIOO - (I2C clock) - Programmed Output
PIOl - Input
PIOl - (I2C clock) - Programmed Output
6-12
Technical Specification
Pin Descriptions
6.4.9
POWER
Power - 24 pins
Type
1/0
Description
Pin Name
Pin #
Avdd
124
I
Analog Voltage input
Avss
123
I
Analog Ground input
Vss[13:0]
Refer to
pin table
I
Ground input
Vdd[7:0]
Refer to
pin table
I
Voltage input
Note:
All input pins, excluding the clock inputs, have pull up resistors
Oak Technology
6-13
Technical Specification
OTI-610/0TI-611
(This page intentionally left blank)
Oak Technology
6-14
Technical Specification
REGISTER DEFINITIONS
CHAPTER 7
The register structure of the OTI-61 0 and OTI-611 consists of a base address within the PCI configuration register
structure to which an offset address is added to obtain the address of the control registers of the OTI-61 0/
OTI-611. There is a default base address upon Power On, but the operating system may change the base address.
Each logical device within the OTI-61 0 and OTI-611 has its own Base Address register within the PCI
configuration space. Thus, each logical device has its own group of offset registers. 'In cases where the Offset
Register Number may be duplicated, it actually belongs to a different logical device unless there is a specific
notation that the register is shared across one or more logical devices. Not all possible register numbers are
used. Only those listed are valid Offset Register Numbers. The remaining possible numbers are either not
implemented or reserved.
The logical devices referred to are: Game Port Device, Audio Device, and Modem Device.
Modem Control Function registers are applicable to the 011-611 only.
Oak Technology
7-1
Technical Specification
OTI-610/0TI-611
7.1
NUMERICAL LISTINGS OF REGISTERS
7.1.1
GAME PORT FUNCTION REGISTERS
Game Port
Register Number
Register Name
Page
Number
OOh
PCI Game Port
7-52
01h
PCI Game Port (Same as OOh)
7-52
08h-09h
Game Port I & II - X position
7-53
OAh-OBh
Game Port I & II - Y position
7-53
OCh
Game Port Control
7-54
200h
Standard Game Port
7-52
201h
Standard Game Port
7-52
Note:
Host Offset relative to Game Port Base Address register
7.1.2
AUDIO FUNCTION REGISTERS
Audio Register
Number
Register Name
Page
Number
30h-33h
Channel 9 Base Address
7-47
38h-39h
Channel 9 Segment Length
7-48
3Ah-3Bh
Channel 9 Interrupt Count
7-51
3Ch-3Dh
Channel 9 Command
7-49
3Eh-3Fh
Channel 9 Segment Position
7-50
40h
61 0/611 Status Register
7-20
41h
Miscellaneous Mode
7-21
42h
Codec Control
7-22
43h
General Purpose I/O & Crystal Source for Main Clock
7-23
44h-45h
Interrupt Status
7-24
46h-47h
Interrupt Mask
7-25
48h
Codec Sample Rate Control
7-26
49h
12S Control and Status
7-27
4Ah
DSP General Control Register 1
7-28
4Bh
DSP General Control Register 2
7-29
4Ch
Miscellaneous Channel Control
7-30
Oak Technology
7-2
Technical Specification
Register Definitions
AUDIO FUNCTION REGISTERS (Cont'd)
Audio Register
Number
Register Name
Page
Number
4Dh
Power Down Control
7-31
4Eh
12S Input Rate Control and Status
7-31
4Fh
J2S Serial Port Format Control
7-32
SOh-51 h
Host Interface Register HDRO
7-32
54h-55h
Host Interface Register HDR1
7-33
5Bh-59h
Host Interface Register HDR2
7-33
5Ch-5Dh
Host Interface Command and Status
7-33
60h
MIDI Data Port
7-34
61h
MIDI Port Command and Status
7-35
62h
MIDI Port Baud Rate Divisor/Loopback
7-35
6Ch
Audio Codec Index Register 2
7-36
6Dh
Audio Codec Index Register 1
Same as 43h in Modem I/O Space
7-37
6Eh-6Fh
Audio Codec Data
Same as 44h-45h in Modem 1/0 Space
7-37
70h-7Fh
Channel 0 Playback Registers
7-42 to 7-45
BOh-BFh
Channel 1 Playback Registers
7-42 to 7-45
90h-9Fh
Channel 2 Playback Registers
7-42 to 7-45
AOh-AFh
Channel 3 Playback Registers
7-42 to 7-45
BOh-BFh
Channel 4 Playback Registers
7-42 to 7-45
COh-CFh
Channel 5 Playback Registers
7-42 to 7-45
DOh-DFh
Channel 6 Playback Registers
7-42 to 7-45
EOh-EFh
Channel 7 Playback Registers
7-42 to 7-45
FOh-F3h
Channel B Base Address
7-47
F4h-F5h
Channel 7 Interrupt Count for Modem
7-46
FBh-F9h
Channel B Segment Length
7-4B
FCh-FDh
Channel B Command
7-49
FEh-FFh
Command B Segment Position
7-50
Note:
Host Offset relative to Audio Function Base Address register
Oak Technology
7-3
Technical Specification
011-610/011-611
7.1.3
MODEM CONTROL FUNCTION REGISTERS
The names provided in the following table are provided for reference only. Some registers may have different
names and functions depending upon whether or not data is written to or read from the register. These registers
are applicable to the OTI-611 only.
Modem Control
Register Nurmer
Register Name
Page
Number
31h
STLC7549 Codec GPIO Data
7-38
40h
Data [7: 0)
7-55
41h
Data[15:8)
7-55
42h
Index[7:0)
7-56
43h
Codec Index[7:0)
Same as 6Dh in Audio 10 space
7-37
7-56
44h
Codec Data[7:0)
Same as 6Eh in Audio 10 space
7-37
7-57
45h
Codec Data[15:8]
Same as 6Fh in Audio 10 space
7-37
7-57
46h
ID
Same as Index 2 Extout[7:0] register
7-58
47h
10 Space Control
7-58
Note:
Host Offset relative to Modem Function Base Address register
Oak Technology
7-4
Technical Specification
Register Definitions
7.2
ALPHABETICAL LISTINGS OF REGISTERS
The register names in sections 7.2.1 through 7.2.3 are listed alphabetically and are provided to help the user find
the page number on which complete register descriptions are provided.
Note:
The register number is relative to the Base Address Register value placed in the Base Address Register
(1 Oh) of the PCI configuration space for each type of device. Thus, audio register names are relative to
the Audio Configuration Base Address Register value, while game port register names are relative to the
Game Port Configuration Base Address Register value. Likewise, modem register names are relative to
the Modem Configuration Base Address Register value.
Logically, the OTI-61 0 is two devices: an audio device and a game port device. Each device has its own
configuration space.
Logically, the OTI-611 is three devices: an audio device, a game port device, and a modem device. Each device
has its own configuration space.
Oak Technology
7-5
Technical Specification
OTI-610/0TI-611
7.2.1
AUDIO REGISTERS
Register Name
Register Number
Device Type
Page Number
610/611 Status Register
40h
A
7-20
Audio Codec Index Register 2
6Ch
A
7-36
6Dh
A
7-37
Same as 43h in
Modem I/O space
M
7-56
6Eh-6Fh
A
7-37
Same as 44h, 45h in
Modem I/O space
M
7-57
Channel 0 Playback Registers
70h-7Fh
A
7-42 to 7-45
Channel 1 Playback Registers
80h-8Fh
A
7-42 to 7-45
Channel 2 Playback Registers
90h-9Fh
A
7-42 to 7-45
Channel 3 Playback Registers
AOh-AFh
A
7-42 to 7-45
Channel 4 Playback Registers
BOh-BFh
A
7-42 to 7-45
Channel 5 Playback Registers
COh-CFh
A
7-42 to 7-45
Channel 6 Playback Registers
DOh-DFh
A
7-42 to 7-45
Channel 7 Playback Registers
EOh-EFh
A
7-42 to 7-45
Channel 7 Interrupt Count
F4h-F5h
A
7-46
Channel 8 Base Address
FOh-F3h
A
7-47
Channel 8 Command
FCh-FOh
A
7-49
Channel 8 Position
FEh-FFh
A
7-50
Channel 8 Segment Length
F8h-F9h
A
7-48
Channel 9 Base Address
30h-33h
A
7-47
Channel 9 Command
3Ch-30h
A
7-49
Channel 9 Interrupt Count
3Ah-3Bh
A
7-51
Channel 9 Segment Length
38h-39h
A
7-48
Channel 9 Position
3Eh-3Fh
A
7-50
Codec Control
42h
A
7-22
DSP Interface
Codec Sample Rate Control
48h
A
7-26
OSP General Control 1
4Ah
A
7-28
Audio Codec Index Register 1
Audio Codec Data
Oak Technology
7-6
Technical Specification
Register Definitions
AUDIO REGISTERS (Cont'd)
Register Name
Register Number
Device Type
Page Number
DSP General Control 2
4Bh
A
7-29
General Purpose 1/0
43h
A
7-23
Host Interface Register HDRO
50h-51h
A
7-32
Host Interface Register HDR1
54h-55h
A
7-33
Host Interface Register HDR2
58h-59h
A
7-33
Host Interface Command and Status
5Ch-5Dh
A
7-33
12S Control and Status
49h
A
7-27
12S I nput Rate Control and Status
4Eh
A
7-31
12S Serial Port Format Control
4Fh
A
7-32
Interrupt Mask
46h-47h
A
7-25
Interrupt Status
44h-45h
A
7-24
MIDI Data Port
60h
A
7-34
MIDI Port Command and Status
61h
A
7-35
MIDI Port Baud Rate
Divisor/Loopback
62h
A
7-35
Miscellaneous Channel Control
4Ch
A
7-36
Miscellaneous Mode
41h
A
7-21
Power Down Control
4Dh
A
7-31
Note:
Host Offset relative to Audio Base Address register
A Audio; GP Game Port; M Modem
=
Oak Technology
=
=
7-7
Technical Specification
OTI-610/0TI-611
7.2.2
GAME PORT REGISTERS
Register Name
Register Number
Device Type
Page Number
Game Port I & II - X position
08h-09h
GP
7-53
Game Port I & II - Y position
OAh-OBh
GP
7-53
Game Port Control
OCh
GP
7-54
PCI Game Port
OOh
GP
7-52
PC! Game Port (Same as OOh)
01h
GP
7-52
Standard Game Port
200h
GP
7-52
Standard Game Port
201h
GP
7-52
Note:
Host Offset relative to Game Port Base Address register
A =Audio; GP = Game Port; M = Modem
7.2.3
MODEM REGISTERS
Register Name
Register Number
Device Type
44h
Page Number
7-57
M
CODEC_DATAI7:0]
Same as 6Eh in Audio 10 space
7-37
45h
7-57
M
CODEC_DATAI15:8]
Same as 6Fh in Audio 10 space
7-37
43h
7-56
M
CODEC_INOEXI7:0]
Same as 60h in Audio 10 space
7-37
Data [7:0]
40h
M
7-55
Data[15:8]
41h
M
7-55
ID
Same as Index 2 10[7:0] register
46h
M
7-58
Index[7:0]
42h
M
7-56
10 Space Control
47h
M
7-58
STLC7549 Codec GPIO Data
31h
M
7-38
Note:
Host Offset relative to Modem Base Address register
A =Audio; GP = Game Port; M = Modem
Oak Technology
7-8
Technical Specification
Register Definitions
7.3
PCI CONFIGURATION REGISTERS
7.3.1
AUDIO CONFIGURATION REGISTERS
The OTI-61 0 and OTI-611 share a common architecture for the audio and game port functions. The PCI
configuration registers for audio and game port functions are identical.
TheOTI-610 and OTI-611 are logical multi-function devices. The OTI-61 0 is an audio and a game port device
and the OTI-611 is an audio, game port, and modem device.
The table below lists the audio configuration registers common to both the OTI-61 0 and OTI-611.
Byte 3
Byte 2
Byte 1
Byte 0
Address
06
11
10
4E
OOOOOOOOh
Status : 0200
Command : 0000
0OOOOO04h
04h
01h
OOh
B2h
00000008h
OOh
80h
Latency Timer
OOh
OOOOOOOCh
01
00000010h
I/O Base Address Registers (Default 000030xx)
OOOOOOOOh
00000014h
OOOOOOOOh
00OOOO18h
OOOOOOOOh
0OOOOO1Ch
OOOOOOOOh
0OOOOO20h
OOOOOOOOh
00000024h
OOOOOOOOh
0OOOO028h
Subsystem 10
OOh
Note:
Subsystem Vendor 10
0OOOOO2Ch
OOOOOOOOh
00000030h
reserved OOOOOOOOh
00000034h
reserved OOOOOOOOh
00000038h
OOh
01h
Interrupt Li ne
00OOOO3Ch
Values in bold are set to zero.
The Power On default value of the 1/0 Base Address register (1 Oh-13h) is 00003001 h. Byte 0 is hardwired to 01 h
to indicate 1/0 Base. The operating system will overwrite bytes 1,2, and 3. All audio function registers are offset
from the final address value written into bytes 1, 2, and 3 (registers 11 h, 12h, 13h) by the operating system.
The configuration space address range is from OOh to 3Fh, but not all addresses are used.
Oak Technology
7-9
Technical Specification
011-610/011-611
Descriptions ofAudio Configuration Registers
Offset = OOh-()1h
Vendor ID
RO
The Oak Technology Vendor ID is 104Eh.
Device ID
Offset = o2h-03h
RO
Device 1D is 0611 h. The OTI-61 0 is derived from the OTI-611 and can be identified by
checking bit 4 of register 40h of the Audio Configuration Register Space. Refer to the description
of register 40h.
=
Command
Bit
15-10
9
8
7
6
5
4
3
2
1
o
13-0
Status
Bit
15
14
13
12
11
10-9
8
7
6
5
4-0
Offset 04h-05h
R/W
Description
Reserved. Hardwired to o.
Fast Back-to-Back Enable. Hardwired to o.
System Error Enable. Hardwired to o.
Address/Data Stepping. Hardwired to o.
Parity Error Response. OTI-610/0TI-611 ignores this bit. Hardwired to O.
ForVGA compatible. Hardwired to o.
Allows OTI-61 0/OTI-611 to use Memory write and invalidate when acting as bus
master. Power on value = o.
For special cycle device. Hardwired to o.
Value of 1 allows OTI-61 0/OTI-611 to behave as a bus master. Power On value O.
Value of 0 disables the device response, value of 1 allows device to respond to memory
space access. OTI-61 0/OTI-611 has no memory space access. Power On value is O.
Value of 0 disables the device response; value of 1 allows device to respond to I/O
space access. Power on value is o.
Device 10 is 0611 h. The OTI-61 0 is derived from the OTI-611 and can be identified by
checking bit 4 of register 40h of the Audio Configuration Register Space. Refer to the
description of register 40h.
Offset = 06h-07h
R/W
Description
Parity Error Status. No matter command register bit 6. Write a '1' to this location will
clear this status. Hardwired to O.
System Error Status. Hardwired to o.
Receive Master Abort. If Master Abort occurs in OTI-61 0/OTI-611 master mode, the
status bit will respond. Writing a 1/1" to this bit location will reset this status.
Receive Target Abort. OTI-610/0TI-611 in Master mode shou Id return the status.
Writing a 1/1" to this bit location will reset the status.
Signaled Target Abort. Hardwired to o.
Medium DEVSEL#. Hardwired to 01 .
Parity Error. Hardwired to O.
Fast Back-to-Back. The OTI-61 0/0TI-611 does not support this function.
Hardwired to o.
UDF (User-Defined Features). Hardwired to o.
33-MHz PCICLK. Hardwired to o.
Reserved. Hardwired to
o.
Revision 1D
OTI-610/0TI-611 revision ID is B2h
Oak Technology
Offset = OSh
7-10
RO
Technical Specification
Register Definitions
Class and Subclass Code Register
Offset = 09h-OBh
RO
OTI-61 0/OTI-611 is Multimedia Class (Address OBh); Audio Subclass (Address OAh); the
interface of audio device (Address 09h)
Class Code = 04h, Subclass Code = 01 h, Interface = OOh.
=ODh
Latency Timer
Offset
Header1ype
Offset =OEh
R/W
RO
Read Only = 80h, multi-function device.
10 Base Registers
Offset
=10h-13h
R/W
OTI-61 0/OTI-611 mC!Pped I/O base address registers. OTI-61 OIOTI-611 1/0 decoding logic will
compare the content of the I/O base registers (11 h, 12h and 13 h) and bit 0 of command
registers.
Bit
Description
OS assigned the I/O base.
31-8
7-1
Hardwired to O.
o
Hardwired to 1 to indicate this range is for I/O Base assignment.
Power On value
= 00003 DOl h
Subsystem Vendor 10
Offset = 2Ch
R/W
Required by PC '97. For system manufacturer of OTI-61 0/011-611 system. Th is register wi II
read external pull-up/pull-down values ofWDMD[15:0] pins as its initial value during power up.
It also can be programmed by BIOS or SW after power up if register 43h, bit 6 (SSIDWR) has
been set.
Subsystem 10
Offset = 2Eh
R/W
Required by PC '97. For system manufacturer of OTI-61 0/011-611 system. Th is register wi II
read external pull-up/pull-down values ofWDMA[18:8] pins as its initial value during power up.
It also can be programmed by BIOS or SW after power up if register 43h, bit 6 (SSIDWR) has
been set.
Offset = 3Ch
Interrupt Line
R/W
This register is assigned by OS after interrupt rerouting algorithm to tell the device driver which
input of the system interrupt controller the device's interrupt pin is connected to.
Offset = 3Dh
Interrupt Pin
R/W
Audio function in OTI-61 010TI-611 uses a single interrupt. The interrupt is internal Wired-Or
and connected to INTA#.
INTA# = 01h.
The other registers of configuration space are reserved and hardwired to OOh.
Oak Technology
7-11
Technical Specification
011-610/011-611
7.3.2
GAME PORT CONFIGURATION REGISTERS
The OTI-61 a and OTI-611 are logical mu Iti-function devices. The OTI-61 0 is an audio and a game port device,
and the OTI-611 is an audio, game port, and modem device.
The table below lists the game port configuration registers common to both the OTI-61 a and OTI-611.
Byte 3
Byte 2
Byte 1
Byte 0
Address
16
11
10
4E
OOOOOOOOh
Status : 0200
Command : 0000
00000004h
09h
04h
10h
B2h
00000008h
OOh
80h
Latency: DOh
OOh
OOOOOOOCh
01
0000001Dh
I/O Base Address Registers (Default 00003 FOx)
OOOOOOOOh
00000014h
OOOOOOOOh
00000018h
OOOOOOOOh
000000lCh
OOOOOOOOh
00000020h
OOOOOOOOh
DOOOO024h
OOOOOOOOh
00000028h
Subsystem Vendor ID
Subsystem I D
DOh
Note:
0000002Ch
OOOOOOOOh
00000030h
reserved OOOOOOOOh
00000034h
reserved OOOOOOOOh
00000038h
OOh
DOh
Interrupt: OOh
0000003Ch
Values in bold are set to zero.
The Power On default value of the 1/0 Base Address register (1 Oh-13h) is 00003FOl h. The high-order Nibble of
byte 0 is part of the 1/0 Base Address. The low-order Nibble of byte 0 is hardwired to 1h. The operating system
will overwrite the high-order Nibble of byte 0, and all of bytes 1, 2, and 3. All audio function registers are offset
from the final address value written into the high-order Nibble of byte 0 and bytes 1,2, and 3 by the operating
system.
Configuration space address range is from OOh to 3 Fh, but not all addresses are used.
Oak Technology
7-12
Technical Specification
Register Definitions
Descriptions of Game Port Configuration Registers
Vendor 10
Offset = OOh-01 h
RO
=02h-03h
RO
The Oak Technology Vendor 10 is 104Eh.
Device 10
Offset
Device 10 is 1611 h. The OTI-61 0 is derived from the OTI-611 and can be identified by
checking bit 4 of register 40h of the audio configuration register space. Refer to the description
of register 40h.
Offset = 04h-05h
R/W
Description
Reserved. Hardwired to o.
Fast Back-to-Back Enable. Hardwired to
System Error Enable. Hardwired to o.
Address/Data Stepping. Hardwired to O.
Parity Error Response. The OTI-61 0/OTI-611 ignores this bit. Hardwired to o.
ForVGA compatibility. Hardwired to O.
Allows OTI-610/0TI-611 to use memory write and invalidate when acting as bus
master. Hardwired to O.
For special cycle device. Hardwired to O.
Value of 1 allows OTI-61 0/OTI-611 to behave as a bus master. Hardwired to o.
Value of 0 disables the device response; value of 1 allows device to respond to memory
space access. The OTI-61 0/OTI-611 has no memory space access. Power On value is
Command Register
Bit
15-10
9
8
7
6
5
4
3
2
1
o
o.
o.
Value of 0 disables the device response; value of 1 allows device to response to I/O
space access. Power On value is o.
Offset = 06h-07h
Status Register
Bit
15
14
13
12
11
10-9
8
7
6
5
4-0
RIW
Description
Parity Error Status. No matter command register bit 6. Writing a 1/1" to this location will
clear this status. Hardwired to O.
System Error Status. Hardwired to o.
Receive Master Abort. Hardwired to O.
Receive Target Abort. Hardwired to O.
Signaled Target Abort. Hardwired to o.
Medium DEVSEL#. Hardwired to 01.
Parity error. Hardwire to O.
Fast back-to-back. OTI-61 0/OTI-611 does not support this function. Hardwired to O.
UDF (user-defined features). Hardwired to O.
33-MHz PCICLK. Hardwired to O.
Reserved. Hardwired to O.
Offset = 08h
Revision 10
RO
OTI-61 0/OTI-611 revision 10 is B2h.
Class and Subclass Code
Offset = 09h-OBh
RO
011-610/011-611 is Input device Class (address OBh); Game Port/Joystick Subclass (address
OAh); interface programming interface defined (address 09h)
Class Code = 09h, Subclass Code = 04h, Interface = 10h.
Oak Technology
7-13
Technical Specification
011-610/011-611
Latency Timer
=OOh
RO
Offset = OEh
RO
Offset = 10h-13h
RIW
Offset
Read On Iy registers = OOh
Header1ype
Read Only = 80h, multi-function device.
10 Base Registers
OTI-61 010TI-611 mapped 1/0 base address registers .. OTI-61010TI-611 1/0 decoding logic will
compare the content of the 10 base registers (h igh-order Nibble of 1Oh, 11 h, 12 h, and 13 h) and
bit 0 of command registers.
Description
Bit
31-4
OS assigned the 1/0 base.
3-1
Hardwired to O.
o
Hardwired to 1 to indicate this range is for 1/0 Base assignment.
Power-on value = 00003F01 h
Subsystem Vendor 10
Offset = 2Ch
RIW
Required by PC '97. For system manufacturer of 011-610/011-611 system. This register will
read external pull-up/pull-down values ofWDMD[15:0] pins as its initial value during power up.
It also can be programmed by BIOS or SW after power up if register 43h, bit 6 (SSIDWR) has
been set (shared with audio configuration).
Subsystem 10
Offset = 2E
RIW
Required by PC '97. For system manufacturer of 011-610/011-611 system. This register will
read external pull-up/pull-down values ofWDMA[18:8] pins as its initial value during power up.
It also can be programmed by BIOS or SW after power up if register 43h, bit 6 (SSIDWR) has
been set (shared with audio configuration).
Interrupt Line
Offset = 3Ch
RO .
Offset = 30h
RO
Read Only registers = OOh
Interrupt Pin
Read Only registers = OOh
The other registers of configuration space are reserved and hardwired to ~Oh.
Oak Technology
7-14
Technical Specification
Register Definitions
7.3.3
FAX/MODEM CONFIGURATION REGISTERS
The OTI-611 is a multi-function device -
an audio, game port, and modem device.
The table below lists the modem configuration registers for the OTI-611.
Byte 3
Byte 2
Byte 1
Byte 0
Address
02
88
10
4E
OOOOOOOOh
Status: 0200
Command : 0000
00000004h
07h
OOh
02h
B2h
00000008h
OOh
80h
OOh
OOh
OOOOOOOCh
01
00000010h
I/O Base Address Registers (Default 00003Exx)
OOOOOOOOh
00000014h
OOOOOOOOh
00000018h
OOOOOOOOh
0000001Ch
OOOOOOOOh
00000020h
OOOOOOOOh
000OO024h
OOOOOOOOh
000OOO28h
Subsystem ID
OOh
Note:
Subsystem Vendor ID
0OOOOO2Ch
OOOOOOOOh
0OOOO030h
reserved OOOOOOOOh
0OOOO034h
reserved OOOOOOOOh
00OOOO38h
OOh
02h
Interrupt Line
0OOOO03Ch
Values in bold are set to zero.
The power on default value of the liD Base Address Register (1 Oh-13h) is 00003E01 h. Byte 0 is hardwired to 01 h
to indicate liD Base. The operating system will overwrite bytes 1,2, and 3. All audio function registers are offset
from the final address value written into bytes 1,2, and 3 (registers 11 h, 12h, and 13h) by the operating system.
Configuration space address range is from OOh to 3Fh, but not all addresses are used.
Oak Technology
7-15
Technical Specification
OTI-610/0TI-611
Descriptions of Fax/Modem Configuration Registers
Vendor ID
Offset = OOh-Ol h
RO
Offset = 02h-03h
RO
The Oak Technology Vendor 10 is 104Eh.
Device 10
Device 10 is 0288h.
Offset = 04h-05
R/W
Description
Reserved. Hardwired to O.
Fast Back-to-Back Enable. Hardwired to O.
System Error Enable. Hardwired to O.
AddresslData Stepping. Hardwired to O.
Parity Error Response. OTI-611 ignores this bit. Hardwired to O.
ForVGA compatible. Hardwired to O.
Allow OTI-611 to use memory write and invalidate when acting as bus master. Power
On value is O.
For special cycle device. Hardwired to O.
Value of 1 allows OTI-611 to behave as a bus master. Power On value is O.
Value of 0 disables the device response; value of 1 allows device to respond to memory
space access. The OTI-611 has no memory space access. Power On value is O.
Value of 0 disable the device response; value of 1 allows device to response to 1/0
space access. Power On value is O.
Command Register
Bit
15-10
9
8
7
6
5
4
3
2
1
o
=
Status Register
Bit
15
14
13
12
11
10-9
8
7
6
5
4-0
Offset 06h-07h
R/W
Description
Parity Error Status. No matter command register bit 6. Writing a "1" to this location will
clear this status. Hardwired to O.
System Error Status. Hardwired to O.
Receive Master Abort. If master abort occurs in OTI-611 master mode, the status bit will
respond. Writing a 1/1" to this bit location will reset this status.
Receive Target Abort. OTI-611 in master mode should respond with status. Writing a
1/1" to this bit location will reset the status.
Signaled Target Abort. Hardwired to O.
Medium DEVSEL#. Hardwired to 01.
Parity error. Hardwired to O.
Fast Back-to-Back. The OTI-611 does not support this function. Hardwired to O.
UDF (user-defined features). Hardwired to O.
33-MHz PCICLK. Hardwired to O.
Reserved. Hardwired to O.
Revision ID
Offset = 08h
RO
OTI-611 revision 10 is B2h
Class and Subclass Code
Offset = 09h-OBh
RO
OTI-611 is Simple Communication device Class (address OBh), 16550-compatible serial
controller.
Class Code = 07h , Subclass Code = OOh , Interface = 02h.
Oak Technology
7-16
Technical Specification
Register Definitions
Latency Timer
Offset = OOh
R/W
Header1ype
Offset = OEh
RO
Read Only = 80h, multi-function device.
=
10 Base Registers
Offset 10h-13h
R/W
OTI-611 mapped I/O base address registers. OTI-611 I/O decoding logic will compare the
content of the 10 base registers (11 h, 12h and 13h) and bit 0 of command registers.
Bit
Description
OS assigned the I/O base.
31-8
7-1
Hardwired to o.
o
Hardwired to 1 to indicate this range is for I/O Base assignment.
Power on value = 00003E01 h
Subsystem Vendor 10
Offset = 2Ch
R/W
Required by PC '97. For system manufacturers of 011-611 systems. This register will read
external pull-up/pull-down values ofWDMD[15:0] pins as its initial value during power up. It
also can be programmed by BIOS or SW after power up if register 43h, bit 6 (SSIDWR) has been
set (shared with audio configuration).
Subsystem 10
Offset = 2Eh
R/W
Required by PC '97. For system manufacturers of 011-611 systems. This register will read
external pull-up/pull-down values ofWDMA[18:8] pins as its initial value during power up. It
also can be programmed by BIOS or SW after power up if register 43h, bit 6 (SSIDWR) has been
set (shared with audio configuration).
Interrupt Line
Offset = 3Ch
R/W
This register is assigned by OS after interrupt rerouting algorithm to tell device driver which
input of the system interrupt controller the device's interrupt pin is connected to.
Offset = 30h
Interrupt Pin
RO
The fax/modem function in the OTI-611 uses a single interrupt. The interrupt is internal Wire-Or
and connected to INTB#.
INTB# = 02h.
The other registers of configuration space are reserved and hardwired to OOh.
Oak Technology
7-17
Technical Specification
OTI-610/0TI-611
7.4
GENERAL CONTROL REGISTERS
The registers' locations are linear and byte addresses are Audio 1/0 Base Address + host offset.
Description of registers are provided by register number and are identified by group in the corresponding section heading.
From the Genera! Control Register Group, certain registers pertain to codec operation. The tables below and on
the next page provide a Iist of those registers.
Oak Technology
Host Offset
Size
040h
8 bit
Status Register
041h
8 bit
Miscellaneous Mode
042h
8 bit
Codec Control
043h
8 bit
General Purpose 1/0 Control
044h-045h
16 bit
Interrupt Status Register
046h-047h
16 bit
Interrupt Mask Register
048h
8 bit
DSP Interface & Codec Sample Rate Control Register
049h
8 bit
MPEG Control and Status
04Ah
8 bit
DSP General Control 1 and DSP Memory Access
04Bh
8 bit
DSP General Control 2
04Ch
8 bit
Miscellaneous Channel Control
04Dh
8 bit
Power Down Control (write only)
04Eh
8 bit
12S Input Rate Control and Status
04Fh
8 bit
Digital Audio Serial Port (J2S) Format Control
50h-51h
16 bit
HDRO [15:0] - Dual Port Data Register I
54h-55h
16 bit
HDR1 [15:0] - Dual Port Data Register II
58h-59h
16 bit
HDR2 [15:0] - Dual Port Data Register III
5Ch-5Dh
16 bit
HCSR [15:0] - HIP Command/Status Register
060h
8 bit
MPU-401 Data Port
061h
8 bit
MPU-401 Command/Status Port
062h
8 bit
MPU-401 Baud Rate Divisor/Loopback
06Ch
8 bit
Audio Codec Index Register 2
06Dh
8 bit
Audio Codec Index Register 1
Same as 43h in Modem 1/0 space
06Eh-06Fh
16 bit
Audio Codec Data Register
Same as 44h, 45h in Modem 1/0 space
Description
7-18
Technical Specification
Register Definitions
Access to the external codecs used by the OTI-61 0 and OTI-611 is via a serial interface. The OTI-61 0 and
OTI-611 translate th is internally to a 16-bit parallel interface.
All OTI-61 O/OTI-611 external codecs use the same index register technique for reading and writing internal
codec registers. The individual codec reference must be consulted for register offsets and configurations. The
following describes typical codec access sequences for reading and writing codec registers.
Write Codec register:
1) Poll Codec Busy (CB) bit until NOT busy. If time out, reset codec.
2) Write the Codec Index register with Codec Read (CRD) bit cleared.
3) Write data to Codec Data register.
Read Codec register:
1) Poll Codec Busy (CB) bit until NOT busy. If time out, reset codec.
2) Write the Codec Index register with Codec Read (CRD) bit set.
3) Poll Codec Data Valid (CDV) bit until set. If time out, reset codec.
4) Read data from Codec Data Register.
Codec Control Register Offsets:
Oak Technology
Host Offset
Size
Description
042h
8 bit
Codec Control
048h
8 bit
Codec I/O Sample Rate Control
06Ch
8 bit
Audio Codec Index Register 2
06Dh
8 bit
Audio Codec Index Register 1
Same as 43h in Modem I/O space
06Eh-06Fh
16 bit
/
Audio Codec Data Register
Same as 44h, 45h in Modem I/O space
7-19
Technical Specification
OTI-610/011-611
7.4.1
OTI-610/0TI-611 STATUS REGISTER (READ ONLy)
Host Offset: 0040h
Bit
,
Read
Initial
7
6
5
4
3
2
1
0
Cf2
CT1
CTO
PCTel
HI
BI02
BIOl
BIOO
X
1
01
01
01
0
1
1
0
0
1
Bit
Description
CT[2:0]
Codec Type
PCTel
PCTel Present
1 = PCTel HM' (OTI-611)
0= No PCTel HM' (OTI-610)
HI
Host Interface
Read from WDMA[O] input pins (BUS_MODE) upon Power Up
1 = PC! Bus; 0= AuxBus. Should always be 11111.
BID[2:0]
Board ID
Note:
Comment
See table below - State is set by pulldown or pullup values on
the following signal pins during Power Up: WDMA[7],
WDMA[6], WOMA[5], CT2, CTl, CTO
Value is board implementation-specific. State is set by pulldown
or pullup values on the following signal pins upon Power Up:
WDMA[4], WDMA[3], WDMA[2], BI0[2], BIO[l], BID[O]
1 Initial value for CT[2:0] bits and 810[2:0] bits is determined by hardware jumpers. If the jumper is
pulled down, the logic level in the register is 0 for those bit positions. If the jumper is pulled up, the
logic level in the register is 1 for those bit positions. The initial value for these bits if no jumper is present
is undetermined.
Codec Type Selection Table:
CT[2:0]
Audio Codec
Modem Codec
0 0 0
A01843
AOl843
0 0 1
Reserved
Reserved
0 1 0
AOl843
ST7546
0 1 1
Reserved
ST7546
1 0 0
ST7549
ST7549
1 0 1
OTI-612 or AC 197 Dual
OTI-612 or AC 197 Dual
1 1 1
AC 197 Audio
ST7546
1 1 0
Reserved
Reserved
This register describes the hardware configuration of the OTI-61 0 or OTI-611 implementation.
The HI, PCTel, CT[2:0], and BI0[2:0] bits are latched into the register upon Hardware Reset or initial Power Up.
Oak Technology
7-20
Technical Specification
Register Definitions
The HI bit is an external pull-down, jumper-selectable, function enable reserved for future use with AuxBus
functions. The default value is 1, indicating PCI bus functions. AuxBus functions are not documented and should
not be chosen.
The PCTel bit is set to 0 on the OTI-61 0 and set to 1 on the OTI-611.
The CT[2:0] and BI0[2:0] bits are board implementation-specific external pull-down or pull-up jumpers available
to the hardware designer to identify a particular board design.
7.4.2
MISCELLANEOUS MODES CONTROL REGISTER
Host Offset: 0041 h
Bit
7
6
5
4
3
2
1
0
RlW
AM
SRC2
SRCl
SRCO
OM
Reset
PSM
TM
Initial
0
0
0
0
0
0
0
0
Bit
Description
AM
Addressing Mode
SRC[2:0]
Observe Mode Signal Source
OM
Observe Mode
RESET
DSP Software Reset Control
PSM
DSP Memory Power Save Mode
TM
Internal Test Mode
Comment
Reserved
View Internal signals for Debug purposes
1 - Enter Observe Mode
o - Exit Observe Mode
1 - Enter Reset Mode
o - Exit Reset Mode
1 - Enter Power Save Mode, turn off DSP SRAM clock
o - Exit Power Save Mode
1 - Enter Test Mode; 0 - Exit Test Mode
Power On default value is ~Oh.
Power Save Mode causes the OTI-611 to stop the DSP SRAM internal clock and disable all internal circuitry
except the host interface to reduce the power consumption of the device for power down mode.
The TM bit will be reset to "0" when the RESET bit is set to "0" in this register.
CAUTION:
Except for the Power Save Mode (PSM) bit, this register is used for chip debug and test purposes only.
Use carefully to avoid abnormal operation of the OTI-611 .
Oak Technology
7-21
Technical Specification
OTI-610/0TI-611
7.4.3
CODEC CONTROL
Host Offset: 0042h
Bit
7
6
5
4
3
2
1
0
R/W
Reserved
Reserved
Reserved
ATE
WRESET
APD
ARESET
AMUTE
Initial
0
0
0
0
0
0
0
Bit
Description
ATE
AC 197 ATE Mode
WRESET
AC 197 Codec Warm Reset
, - Warm Reset
APD
Audio Codec Power Down
, - Audio Codee Power Down
ARESET
Audio Codec Reset
AMUTE
Audio Mute Control
,
Comment
' - Enter AC 197 Codec ATE Mode
o - Exit AC 197 Codec ATE Mode
Audio Codee Reset: TOGGLE this bit from 10 1 to 1,1 and back to 10'
' - Mute Audio Codec
0- Unmute Audio Codec
Power On default value is 01 h.
This register is dedicated to codec control.
Oak Technology
7-22
Technical Specification
Register Definitions
7.4.4
GENERAL PURPOSE I/O CONTROL
Host Offset: 0043h
Bit
7
6
5
4
3
2
1
0
RlW
SRESET
SSIDWR
MCLKSR
Reserved
DCl
GPIOl
DCO
GPIOO
Initial
0
0
0
0
0
X
0
X
Bit
Description
SRESET
Software Reset
SSIDWR
Subsystem 10
Subsystem Vendor 10
Write Control
MCLKSR
Main Clock Crystal Source Control
GPI0[1:0]
General Purpose 1/0
ReadlWrite data to/from external GPIO pins
DCl
Direction Control 1
o - GPIOl
DCO
Direction Control 0
o -GPIOO
Comment
1 - Reset of OTI-61l similar to use of PC! Reset Signal RST#
TOGGLE from 0 to 1 and back to 0
1 - Enable Write of Subsytem 10 and Subsystem Vendor 10 Registers
0- Disable Write of Subsytem 10 and Subsystem Vendor 10 Registers
1 - Use External Crystal on PXTALM pins - (33 MHz to 40 MHz)
0- Use Modem Clock Source (36.864 MHz) on XTAL1 pins only
1 - GPIOl is output
is input
1 - GPIOO is output
is input
This register is dedicated to certain control functions of the OTI-61 0 and OTI-611 .
Power On default value is OOOOOXOX binary.
The General Purpose 1/0 pins (GPIO[l :0], DC[O:l]) can be used to implement an FC interface bus.
MCLKSR permits the OTI-61 010TI-611 to run from a Single crystal source. The default condition is for using a
single crystal- in this case, the crystal used for modem functions. Internally, the modem functions and internal
OSP clocking are derived from this source. For the OTI-611, which contains modem functions, this is the most
desirable mode. For the OTI-61 0, which does not contain modem functions, the clocking mechanism for modem
functions has been removed, but clocking to the internal OSP has been retained so that the default condition for
the OTI-61 0 is the same as for the OTI-611 .
MCLKSR may be set to 1 by software. In this case, the internal OSP clocking is separated from the modem
function clocking. The internal OSP may then be run separately from a 33-MHz to 40-MHz crystal attached to
the XTALl pins. However, for the OTI-611, the modem crystal (36.864 MHz) is still required. It is not required
for the OTI-61 o.
Oak Technology
7-23
Technical Specification
OTI-610/0TI-611
7.4.5
INTERRUPT STATUS REGISTER
Host Offset: 0044h (0044h and 0045h)
Bit
15
14
13
12
11
10
9
8
RIW
Reserved
MUTEI
DSPI
MPU4011
Cll
ClO
Reserved
Reserved
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
PI7
PI6
PIS
PI4
PI3
PI2
PI1
Pia
Initial
0
0
a
0
0
0
0
0
Bit
Description
MUTEI
HIW Mute Interrupt
DSPI
DSP Interrupt
MPU4011
MPU401 Interrupt
1 - MPU401 device caused an interrupt
Cll-CIO
Capture Interrupt
1 - Interrupt occurred on corresponding capture channel
(CI 1 Channell, CIa Channel 0)
P17-P10
Playback Interrupt
1 - Interrupt occurred on corresponding playback channel
(PI7 Channel 7 to PIO Channel 0)
Comment
1 - HIW Mute state change triggered an interrupt
1 - DSP triggered an interrupt
=
=
=
=
Power On default value is OOOOh.
This is the Interrupt Status register for the host and is written by the OTI-61 0/OTI-611 hardware to generate host
interrupts for each channel.
A "1" read from any bit indicates a pending interrupt request from the correspondingOTI-61 0/OTI-611 hardware.
Each bit can be RESET to "0" from the Host by writing "1" to each bit location.
Physical host interrupts are enabled and disabled by the Interrupt Mask register. The status bits in this register
will be active regardless of the state of the corresponding mask bits in the Interrupt Mask register.
Oak Technology
7-24
Technical Specification
Register Definitions
7.4.6
INTERRUPT MASK REGISTER
Host Offset: 0046h (0046h and 0047h)
Bit
15
14
13
12
11
10
9
8
RIW
Reserved
MUTEIM
DSPIM
MPU4011M
CIM1
ClMO
Reserved
Reserved
Initial
0
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
RlW
PIM7
PIM6
PIMS
PIM4
PIM3
PIM2
PIMl
PIMO
Initial
1
1
1
1
1
1
1
1
Comment
Bit
Description
MUTEIM
Hardware MUTE Interrupt Mask
DSPIM
DSP Interrupt Mask
MPU4011M
MPU401 Port Interrupt Mask
ClM1-CIMO
Capture Interrupt Mask
o - Allow interrupt on corresponding capture channel
PIM7-PIMO
Playback Interrupt Mask
o - Allow interrupt on corresponding playback channel
1 - Mask Mute Interrupt
o - Allow Mute Interrupt
1 - Mask DSP triggered interrupt
o - Allow DSP triggered interrupt
1 - Mask MPU401 device interrupt
device interrupt
o - Allow MPU401
1 - Mask interrupt on corresponding capture channel
1 - Mask interrupt on corresponding -playback channel
Power On default value is 7FFFh.
This register is used to inhibit external interrupts from being generated by an OTI-61 0/OTI-611 interrupt source.
Only the physical interrupt is masked. The OTI-61 0/OTI-611 Interrupt Status register may be polled to determine
if an internal interrupt was generated.
Oak Technology
7-25
Technical Specification
011-610/011-611
7.4.7
DSP INTERFACE AND CODEC SAMPLE RATE CONTROL REGISTER
Host Offset: 0048h
Bit
7
6
5
4
3
2
1
0
RIW
CPFMT
CPENA
DSPwr
Reserved
Reserved
Reserved
SRCl
SRCO
Initial
1
0
0
0
0
0
1
0
Bit
Description
CPFMT
Capture Input Format
CPENA
Capture Enable
DSPwr
DSP Memory
Interface Wait State Control
1 - Disable. DSP will wait until current memory access cycle is
finished.
o - Force DSP H/W to execute the next instruction without
waiting for current external memory access to finish.
SRC[1:0]
Codec Sample Rate Control
See table below.
SRC[1:0]
o
Comment
1 - Stereo
0- Mono
1 - Capture data will write to internal capture FIFOs
o - Capture data will be discarded
Sample Rate Control
x
11.025 KHz
1 0
22.05 KHz
1 1
44.1 KHz
Power On default value is 82h.
This register is used to control capture data, set external memory interface wait state control, and set the codec
sample rate control.
Oak Technology
7-26
Technical Specification
Register Definitions
7.4.8
PS CONTROL AND STATUS
Host Offset: 0049h
Bit
7
6
5
4
3
2
1
0
RIW
MPENA
MUTEST
Reserved
Reserved
Reserved
Reserved
MR1
MRO
Initial
0
0
0
0
0
0
1
0
Bit
Description
MPENA
12S Enable
MUTEST
HIW Mute Status
MR[1:0]
FS Sample Rate
MR[1:0]
12S Sample Rate
ox
32.0 KHz
1 0
48.0 KHz
1 1
44.1 KHz
Comment
1 - Mix 12 S audio input with OTI-610/0TI-611 audio output
input mixing
o - Disable 12S audio
1 - On
0- Off
Set by HI\A/ only, TOGGLED by external 'MUTE' button
See table below. Set by H/W only by sampling external (l2S)
audio clock
Power On default value is 02h.
This register is used to enable/disable FS input source and detect the FS data sample rate.
The OTI-61 O/OTI-611 determines the sample rate of the incoming FS audio data and reports it in this register.
Oak Technology
7-27
Technical Specification
OTI-610/0TI-611
7.4.9
DSP GENERAL CONTROL 1
Host Offset: 004Ah
Bit
7
6
5
4
3
2
1
0
IV""
0/"",
DI!NT
DO!NT
DEBUG
PMS
XMS
VMS
WTRAM
WTROM
Initial
0
0
0
0
0
0
0
0
Bit
Description
DIINT
DEBUG_IN Interrupt to DSP
Active high
DOINT
DEBUG_OUT Interrupt to DSP
Active high
DEBUG
Debug Enable
PMS
Program Memory Select
XMS
Register Memory Select
1 - Select DSP data memory eXI data memory) for access
o - DSP IX I data memory access disabled
VMS
Data Memory Select
1 - Select DSP data memory ('yl data memory) for access
o - DSP Iyl data memory access disabled
wrRAM
External SRAM Access
wrROM
Specify Wavetable Memory Type
Comment
1 - OTI-610/0TI-611 DSP is in debug mode
o - OTI-610/0TI-611 DSP is in normal mode
1 - Select DSP program memory for access
o - DSP progra~ memory access disabled.
1 - Select external SRAM for access
o - External SRAM access disabled
1 - Select memory type as ROM
o - Select memory type as SRAM
Power On default value is ~Oh.
The OTI-61 0/OTI-611 supports direct access to the OTI-61 0/OTI-611 DSP memory space. The DSP memory
space includes internal SRAM, as well as external SRAM or ROM.
To access this memory from the host computer, set one of the four memory select bits (PMS, XMS, VMS, or
WTRAM). The memory select bits are mutually exclusive. Operation is undefined if more than one of these bits
are set simultaneously.
Setting any of the memory select bits suspends normal operation of the DSP. When all the memory select bits are
cleared, the DSP continues where it left off. Care must be taken not to modify data or program memory that the
DSP may be utilizing. Failure to do so may result in unstable operation of the OTI-61 0/OTI-611.
Oak Technology
7-28
Technical Specification
Register Definitions
7.4.10
DSP GENERAL CONTROL 2
Host Offset: 004Bh
Bit
7
6
5
4
3
2
1
0
RIW
Reserved
Reserved
Reserved
Reserved
Reserved
MONIT
FIOLE
Reserved
Initial
0
0
0
0
0
0
1
0
Bit
Description
MONIT
Monitor Select
Comment
1 - MONIT/OSPARE3 pin provides OSP monitor ouput
o - MONIT/OSPARE3 pin used as OSPARE3 output for the OM
interface
1 - Force OSP into idle state
FIDLE
Force Idle
o - Allow DSP to run normally
See Programming Note
Power On default is 02h.
PROGRAMMING NOTE:
The FIDLE bit is also set during Power On Reset. Since the OTI-61 0/OTI-611 firmware is RAM-based, the
host must clear this bit after downloading the firmware.
Oak Technology
7-29
Technical Specification
OTI-610/0TI-611
7.4.11
MISCELLANEOUS CHANNEL CONTROL
Host Offset: 004Ch
Bit
7
6
5
4
3
2
1
0
ruw
PClWS
M!D1
MIDO
Reserved
Reserved
Reserved
Reserved
MM
Initial
0
0
0
0
0
0
0
0
Comment
Bit
Description
PClWS
PCI Interface Wait State Select
o - 1 wait state
MID[1~O]
Memory Interface Delay Setting
See table below
MM
MODEM Mode
MID[1:0]
Approximate
Delay Length
0 0
Sns
0 1
6ns
1 0
7ns
1 1
9ns
1 - 0 wait state
1 - channel 7 and channel 9 are assigned to MODEM. Interrupt
will be directed to INTB.
channel 7 and channel 9 are assigned as audio channels.
Interrupt will be directed to INTA.
o-
Power On default value is ~Oh.
The OTI-611 supports bus master communication with the modem codec. In this mode, channel 7 (playback)
and channel 9 (capture) cannot be used as audio channels.
When MM is set (modem mode), channel 7 and 9 interrupts are directed to PCI hardware INTB. When MM is
cleared (audio mode), channel 7 and 9 interrupts are directed to PCI hardware INTA.
Oak Technology
7-30
Technical Specification
Register Definitions
7.4.12 POWER DOWN CONTROL (WRITE ONLy)
Host Offset: 004Dh
Bit
7
6
5
4
3
2
1
0
W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PDWN
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
PDWN
OTI-61 0/OTI-611 Power Down Mode
1 - Turn off internal IMCLKI and channel ILCLK I to reduce steady
state current consumption
0- Return to chip state prior to Power Down
Power On default value is ~Oh.
This register is write only and activates the OTI-61 O/OTI-611 Power Down mode. When active ("1"), the
OTI-61 O/OTI-611 goes into a "sleep" mode and will not function normally. It will only respond to PCI
configuration cycles and the R/W cycle of this register.
7.4.13
PS INPUT RATE CONTROL AND STATUS
Host Offset: 004Eh
Bit
7
6
5
4
3
2
1
0
Write
CNTOF7
CNTOF6
CNTOFS
CNTOF4
CNTOF3
CNTOF2
CNTOFl
CNTOFO
Read
SCNT7
SCNT6
SCNTS
SCNT4
SCNT3
SCNT2
SCNTl
SCNTO
Initial
X
X
X
X
X
X
X
X
Bit
Description
CNTOF[7:0]
Write Only
Offset to LRCLK sampled count in 2 1s complement form
SCNT[7:0]
Read Only
Sampled Count. LRCLK sampled by MCLK
Comment
* 8.
Power On default value is XXh (unknown) and depends upon LRCLK state.
This register is used to determine the incoming PS sample rate. The sum of Count and Offset are used. Offset
value = 2's complement value of ROUND(93.54 - 2.83*MCLK).
MCLK in the table and formula is the main crystal frequency (33 MHz or 36.864 MHz)
Oak Technology
7-31
Technical Specification
OTI-610/0TI-611
7.4.14
DIGITAL AUDIO SERIAL PORT (12S) FORMAT CONTROL (WRITE ONLy)
Host Offset: 004Fh
Bit
7
6
5
4
3
2
1
0
\\/rite
Reserled
Reser-Jed
Reserved
ORDER
PACK
LRPOL
EDGE
CYCDLY
Initial
0
0
0
1
0
1
1
0
Bit
Description
ORDER
Bit Order
PACK
Packing Direction
LRPOL
Left/Right Channel Polarity
EDGE
Edge Control
o - Latch on FALLING edge
CYCOLY
Clock Cycle Delay
o - No delay relative to UR
Comment
1 - MSB first on the data stream
first on the data stream
o - LSB
1 - Forward Packing: Collect data from the start point of UR signal
0- Backward Packing: Collect data from the end point of UR
signal
1 - UR HIGH indicates LEFT channel
o - UR LOW indicates LEFT channel
1 - Latch on RISING edge
1 - One clock delay relative to UR
Power On default value is 16h.
This register is used to set the various possible FS formats which may be used by the FS interface of the OTI-61 0/
OTI-611.
7.4.15
HOST INTERFACE PORT (HIP) INTERFACE REGISTERS
This section lists hardware HIP interface registers. The HIP registers are used to transfer information to and from
the OTI-61 O/OTI-611 DSP.
HDRO - Dual Data Port Register I
Host Offset: OOSOh-OOS1 h
Bit
15
14
13
12
11
10
9
8
RlW
D15
D14
D13
D12
Dl1
Dl0
D9
D8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
07
06
05
04
03
02
01
DO
Initial
0
0
0
0
0
0
0
0
Oak Technology
7-32
Technical Specification
Register Definitions
HDR1- Dual Data Port Register /I
Host Offset: OOS4h-OOSSh
Bit
15
14
13
12
11
10
9
8
RlW
015
014
013
012
011
010
09
08
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
07
06
05
04
03
02
01
DO
Initial
0
0
0
0
0
0
0
0
HDR2 - Dual Data Port Register II/
Host Offset: OOS8h-OOS9h
Bit
15
14
13
12
11
10
9
8
RlW
015
014
013
012
011
010
09
08
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R1W
07
06
05
04
03
02
01
DO
Initial
0
0
0
0
0
0
0
0
HIP Command/Status Register
Host Offset: OOSCh-OOSDh
Bit
15
14
13
12
11
10
9
8
RIW
015
014
013
D12
011
010
09
08
Initial
1
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RIW
07
06
05
04
03
02
Dl
DO
Initial
0
0
0
0
0
0
0
0
Oak Technology
7-33
Technical Specification
OTI-610/0TI-611
7.4.16 MPU-401 CONTROL REGISTERS
The MPU-401 compatible MIDI port is controlled with three registers, as shown below.
Host
Offset
Size
060h
8 bit
MPU-401 Data Port
061h
8 bit
MPU-401 Command/Status Port
062h
8 bit
MPU-401 Baud Rate Oivisor/Loopback
Description
MPU-401 Data Port
Host Offset: 0060h
Bit
7
6
5
4
3
2
1
0
R/W
07
06
05
04
03
02
01
DO
Initial
0
0
0
0
0
0
0
0
Bit
Description
0[7:0]
MPU401 Data
Comment
Read: MIOLIN (MPU-401 port) data
Write: MIOLOUT (MPU-401 port) data
This register implements the standard MPU-401 data port functions. It is not, however, accessible at the standard
MPU-401 port addresses of 3xOh.
Oak Technology
7-34
Technical Specification
Register Definitions
MPU-401 Command/Status Port
Host Offset: 0061 h
Bit
7
6
5
4
3
2
1
0
Read
ORR
DTR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Write
07
06
05
04
03
02
01
00
Initial
1
1
0
0
0
0
0
0
Bit
Description
0[7:0]
MPU401 Command
ORR
Oata Receive Ready (Read)
o - Oata ready
OTR
Oata Transmit Ready (Read)
o - Ready to receive command
Comment
Write:
OFFh - Reset MPU401 UART
03Fh - Enter MPU401 UART mode
1 - No data ready
1 - Transmitter not ready
or transmit data
This register implements the standard MPU-401 command/status port functions. It is not, however, accessible at
the standard MPU-401 port addresses of 3x1 h.
MPU-401 Baud Rate Divisor
Host Offset: 0062 h
Bit
7
6
5
4
3
2
1
0
RlW
LB
06
05
04
03
02
01
00
Initial
0
1
0
0
0
0
1
0
Bit
Description
LB
Loop Back
0[6:0]
Clock ~ivider
Comment
1 - Connect TXO output to RXO internally for testing purposes
0- Normal Operation, RXO connected to external port pin
Hexadecimal number, which when multiplied by 16 and divided
into MCLK will produce MPU-401 baud rate = 31250 Hz +/- 1%
or less
This register sets the internalloopback connections for testing the MPU-401 port.
This register also sets the divisor for the MPU-401 transmit/receive baud rate clock. The Power On default value
is 42h. This value corresponds to the divisor needed when using a 33-MHz crystal applied to the PXTALM pins.
Oak Technology
7-35
Technical Specification
011-610/011-611
PROGRAMMING NOTE:
This register's default value of 42h must be changed by software to the value 49h, which corresponds to
using a 36.864-MHz crystal on the modem crystal inputs, XTAL 1 pins. This is the default crystal setting
for the OTI-61 0/OTI-611. If the user intends to use a 33-MHz crystal on the PXTALM pins and sets the
selection bit 5 in register 43h, then the default value of 42h does not need to be changed.
The baud rate is determined using the following formula applied against the main clock crystal frequency being
used by the OTI-61 0/OTI-611 :
MPU-401 baud rate = MCLK / (16 * divisor) = 31.25 KHz
MCLK = OTI-61 0/OTI-611 Main Clock
divisor = Hexadecimal number to be programmed in register 62h
Register 62h Divisor Value vs. Main Clock Frequency Table:
Main Clock
Divisor
(Decimal)
MPU-401 Baud Rate
Divisor
(Hex)
30.000 MHz
60
31250
3C
33.333 MHz
66
31250
42
36.864 MHz
73
31562 (+.998% error)
49
7.4.17 CODEC INDEX REGISTER 2
Host Offset: 006Ch
Bit
7
6
5
4
3
2
1
0
RIW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INX6
INX5
Initial
X
X
X
X
X
X
0
0
Bit
Description
INX[6:5]
Codec Register Index Value
Comment
MSB[6:5] of Codec Index address. These bits are concatenated
with bits INX[4:0] of register 006Dh, Codec Index Register 1
operation.
Power On default value is XXXXXXOO binary.
This register is used in conjunction with register 006Dh to control CODEC index register addressing.
INX[6:5] supports the extended addressing space requirements of the AC '97 Specification.
Oak Technology
7-36
Technical Specification
Register Definitions
7.4.18 CODEC INDEX REGISTER 1
Host Offset: 006Dh
Bit
7
6
5
4
3
2
1
0
RlW
CB
DV
CRD
INX4
INX3
INX2
INXl
INXO
Initial
0
0
0
X
X
X
X
X
Bit
Description
CB
Command Busy Status
DV
Data Valid Status
CRD
Codec Read
INX[4:0]
Codec Register Index
Power On default value is
Comment
1 - Current Index access not yet complete. Set by HMI only
o - Current Index access complete
1 - Current Index register can be read. Set by HMI only.
o - Current Index register cannot be read
1 - Codec Write access
Read access
o - Codec
Codec Register Indexed Address
OOOXXXXX binary.
This register is used to control co dec operation and codec index address.
7.4.19 CODEC DATA REGISTER
Host Offset: 006Eh-006Fh
Bit
15
14
13
12
11
10
9
8
RIW
CD15
CD14
C013
C012
COll
CD10
CD9
CDB
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RIW
C07
CD6
COS
C04
C03
CO2
COl
COO
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
CD[15:0]
Codec Register Data
Data from/to register specified in previous Codec Index Register 1
Write: Data for output to Codec
Read: Data from Codec
Power On default value is ~Oh.
Oak Technology
7-37
Technical Specification
OTI-610/0TI-611
7.4.20 STLC7549 GPIO DATA REGISTER
Host Offset: 6D = 31 h
Bit
7
6
5
4
3
2
1
0
IlJW
GPI07
GPI06
GPIOS
GPI04
GPI03
GPI02
GPI01
GPIOO
Initial
0
0
0
0
0
0
0
0
Bit
Description
GPIO[7:0]
GPIO Data
Comment
STLC7S49 Dual Codec GPIO port control
This is a special register to support ST7549 GPIO pins. The content of this register will pass to ST7549 through
the serial data stream on a dedicated GPIO slot.
Oak Technology
7-38
Technical Specification
Register Definitions
7.5
CHANNEL REGISTERS
The OTI-61 0/OTI-611 supports eight individual playback channels and two capture channels. All playback
channels operate alike and all capture channels operate alike. The only difference is the host offset. The tables
below list the host offset of each register for all capture channels and all playback channels.
Playback channels can operate in two addressing modes - sequential and random. Sequential mode is used by
host-driven playback and is so named because the OTI-61 0/OTI-611 receives a sequential stream of audio data
without any knowledge of its position in the audio stream. The host can initiate random access of the sequential
stream by stopping playback and restarting from a different buffer location. Playback channel random mode is
used solely by the OTI-61 0/OTI-611 to access Chorus and Reverb delay buffers for the DSP-based wavetable
synthesizer.
Capture Channel Register Offsets
Host Offset
Mode
Size
Name
OFOh-OF3h
Capture
32 bit
Channel 8 Base Address
OF8h-OF9h
16 bit
Channel 8 Segment Length
OFCh-OFDh
16 bit
Channel 8 Command
OFEh-OFFh
16 bit
Channel 8 Position
32 bit
Channel 9 Base Address
038h-039h
16 bit
Channel 9 Segment Length
# of samples to fetch
03Ah-03Bh
16 bit
Channel 9 Interrupt Count
IRQ count: for modem operation as Overrun!
Underrun count
03Ch-03Dh
16 bit
Channel 9 Command
03Eh-03Fh
16 bit
Channel 9 Position
030h-033h
Oak Technology
Effects!
MODEM
7-39
Description
Physical system memory address
# of samples to fetch
Start/stop, reset control, status data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
Physical system mem9ry address
Start/stop, reset control, status data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
Technical Specification
011-610/011-611
Playback Registers
Host Offset
Mode
Size
Name
070h-073h
Playback
32 bit
Channel 0 Base Address 0
Physical system memory address
074h-077h
32 bit
Channel 0 Base Address 1
Physical system memory address
078h-079h
16 bit
Channel 0 Segment Length 0
# of samples to fetch
07Ah-07Bh
16 bit
Channel 0 Segment Length 1
# of samples to fetch
07Ch-07Dh
16 bit
Channel 0 Command
07Eh-07Fh
16 bit
Channel 0 Position
32 bit
Channel 1 Base Address 0
Physical system memory address
084h-087h
32 bit
Channel 1 Base Address 1
Physical system memory address
088h-089h
16 bit
Channell Segment Length 0
# of samples to fetch
08Ah-08Bh
16 bit
Channel 1 Segment Length 1
# of samples to fetch
08Ch-08Dh
16 bit
Channel 1 Command
08Eh-08Fh
16 bit
Channel 1 Position
32 bit
Channel 2 Base Address 0
Physical system memory address
094h-097h
32 bit
Channel 2 Base Address 1
Physical system memory address
098h-099h
16 bit
Channel 2 Segment Length 0
# of samples to fetch
09Ah-09Bh
16 bit
Channel 2 Segment Length 1
# of samples to fetch
09Ch-09Dh
16 bit
Channel 2 Command
09Eh-09Fh
16 bit
Channel 2 Position
32 bit
Channel 3 Base Address 0
Physical system memory address
OA4h-OA7h
32 bit
Channel 3 Base Address 1
Physical system memory address
OA8h-OA9h
16 bit
Channel 3 Segment Length 0
# of samples to fetch
OAAh-OABh
16 bit
Channel 3 Segment Length 1
# of samples to fetch
OACh-OADh
16 bit
Channel 3 Command
OAEh-OAFh
16 bit
Channel 3 Position
080h-083h
090h-093h
OAOh-OA3h
Oak Technology
Playback
Playback
Playback
7-40
Description
Start/stop, reset control, status, data format (8/1 6,
mono/stereo)
Current length counter (buffer pointer)
Start/stop, reset control, status, data format (8/1 6,
mono/stereo)
Current length counter (buffer pointer)
Start/stop, reset control, status, data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
Start/stop, reset control, status, data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
Technical Specification
Register Definitions
Playback Registers (Cont'cl)
Host Offset
Mode
Size
Name
OBOh-OB3h
Pla'yback
32 bit
Channel 4 Base Address 0
Physical system memory address
OB4h-OB7h
32 bit
Channel 4 Base Address 1
Physical system memory address
OB8h-OB9h
16 bit
Channel 4 Segment Length 0
# of samples to fetch
OBAh-OBBh
16 bit
Channel 4 Segment Length 1
# of samples to fetch
OBCh-OBDh
16 bit
Channel 4 Command
OBEh-OBFh
16 bit
Channel 4 Position
32 bit
Channel 5 Base Address 0
Physical system memory address
OC4h-OC7h
32 bit
Channel 5 Base Address 1
Physical system memory address
OC8h-OC9h
16 bit
Channel 5 Segment Length 0
# of samples to fetch
OCAh-OCBh
16 bit
Channel 5 Segment Length 1
# of samples to fetch
OCCh-OCDh
16 bit
Channel 5 Command
OCEh-OCFh
16 bit
ChannelS Position
32 bit
Channel 6 Base Address 0
Physical system memory address
004h-OD7h
32 bit
Channel 6 Base Address 1
Physical system memory address
008h-009h
16 bit
Channel 6 Segment Length 0
# of samples to fetch
ODAh-OOBh
. 16 bit
Channel 6 Segment Length 1
# of samples to fetch
ODCh-OOOh
16 bit
Channel 6 Command
ODEh-OOFh
16 bit
Channel 6 Position
32 bit
Channel 7 Base Address 0
Physical system memory address
OE4h-OE7h
32 bit
Channel 7 Base Address 1
Physical system memory address
OE8h-OE9h
16 bit
Channel 7 Segment Length 0
# of samples to fetch
OEAh-OEBh
16 bit
Channel 7 Segment Length 1
# of samples to fetch
OECh-OEDh
16 bit
Channel 7 Command
OEEh-OEFh
16 bit
Channel 7 Position
OF4h-OFSh
16 bit
Channel 7 Interrupt Count
OCOh-OC3h
OOOh-003h
OEOh-OE3h
Oak Technology
Playback
Playback
Playback
7-41
Description
Start/stop, reset control, status, data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
Start/stop, reset control, status, data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
Start/stop, reset control, status, data format (8/1 6,
mono/stereo)
Current length counter (buffer pointer)
Start/stop, reset control, status, data format (8/16,
mono/stereo)
Current length counter (buffer pointer)
IRQ count: for modem operation as
OverrunlUnderrun count
Technical Specification
OTI-610/0TI-611
PLAYBACK BASE ADDRESS OAND 1 - CHANNEL N (WHERE N= 0-7)
7.5.1
Host Offset: See table below for corresponding entry for n
Bit
31
30
29
28
27
26
RlW
BA31
BA30
BA29
BA28
D~I
nA"''''
OA"l£
D~U
U"".J
Llr~"'T
Initial
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RlW
BA23
BA22
BA2l
BA20
BA19
BA18
BA17
BA16
Initial
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
RlW
BA1S
BA14
BA13
BA12
BAll
BA10
BA9
BA8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
BA7
BA6
BAS
BA4
BA3
BA2
BAl
BAO
Initial
0
0
0
0
0
0
0
0
Bit
Description
BA[31 :0]
Base Address
24
25
OA"l~
DA'lA
Comment
Host physical memory address of the channel buffer
Two 32-bit host physical base address registers. The Base Address 0 register is used in both sequential and
random access modes (See Playback Channel Command Registers). )"he Base Address 0 register is used in
sequential access mode.
PROGRAMMING NOTE:
These registers must be programmed with the physical address of a segment of the host buffer. In
random mode, this address must be aligned on a 128KB boundary. In sequential mode, this address
must be al igned on a DWORD boundary.
.
Oak Technology
7-42
Technical Specification
Register Definitions
PLAYBACK SEGMENT LENGTH 0 AND 1 - CHANNEL N (WHERE N = 0-7)
7.5.2
Host Offset: See table below for corresponding entry for n
Bit
15
14
13
12
11
10
9
8
RIW
SL1S
SL14
SL13
SL12
SL11
SL10
SL9
SL8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
SL7
SL6
SLS
SL4
SL3
SL2
SL1
SLO
Initial
0
0
0
0
0
0
0
0
Bit
Description
SL[lS:0]
Segment Length
Comment
Length in bytes of the associated host buffer segment. Actual
transfer is length +1.
Two 16-bit host buffer segment length registers. These registers specify the length in bytes of the physical memory
segment pointed to by the corresponding Playback Base Address 0 or 1 register.
PROGRAMMING NOTES:
1. Note that the actual number of bytes transferred is the programmed length +1. This allows true 64KB
transfers with a 16-bit register.
2. Since this register allows a maximum of 64KB per segment, it may be necessary to break large host
memory segments into smaller units.
3. In random mode, this register is typically programmed by the OTI-61 0/OTI-611 DSP.
Oak Technology
7-43
Technical Specification
011-610/011-611
PLAYBACK CHANNEL COMMAND - CHANNEL N (WHERE N = 0-7)
7.5.3
Host Offset: See table at beginning of this section for corresponding entry for n
Bit
15
14
13
RiW
START
RFiFO
IV'\I'H.JVIVI
IVIVI'lV
LJV
V"'Lr\LJ I
Initial
0
0
0
0
0
Bit
7
6
5
4
RIW
Segment
Status
Reserved
Reserved
Initial
-
-
-
nA. .... r"""\.I"""\. .......
12
11
10
9
8
~Dr:A~V
1('1
I('n
0
0
0
3
2
1
0
VDC4
VDC3
VDC2
VDC1
VDCO
0
0
0
0
0
a.
~'"' .. IJ""'\
~J""'\
L..JI
L..JV
Bit
Description
START
Enable Channel
RFIFO
Reset FIFO
RANDOM
Random Mode Select
MONO
MONO Enable
DS
Data Size
DREADY
Data Ready
LS1
Last Segment Flag 1
o - Normal operation
LSO
Last Segment Flag 0
o - Normal operation
VDC[1:0]
Valid Data Count
Number of valid samples in the FIFO. Range 0-16 (used by OTI610/0TI-611 DSP only).
Segment
Status
Current Segment
0= Segment 0
1 = Segment 1
Comment
1 - Enable bus master operation starting with base register set
o - Disable bus master operation
o.
1 - Reset Data FIFO R/W pointers, start bit, valid data count
o - Norma I operation
1 - Random addressing mode
o - Sequential addressing mode
1 - Monophonic format data (1-channel)
o - Stereophonic format data (2-channel)
1 - 8-bit samples
o - 16-bit samples
1 - FIFO contains valid data (used by OTI-610/0TI-611 DSP only)
1 - Segment specified by base address 1 is the last segment
1 - Segment specified by base address 0 is the last segment
Setting the START bit will enable the bus master. If the channel FIFO is empty, the bus master will request the bus
and memory transfer will begin. When the START bit is cleared, the bus master will stop after finishing the
current bus cycle.
PROGRAMMING NOTE:
Setting the START bit always resets the hardware to base register o. Pause/Resume and Set Position
programming should take this behavior into account.
Oak Technology
7-44
Technical Specification
Register Definitions
The random addressing mode (RANDOM bit set) uses base and length 0 registers only. In addition, the OTI-61 0/
OTI-611 DSP expects the base register address to be modular 128K, and physically contiguous in memory. These
restrictions force a maximum length of 64K WORDS in random mode.
The sequential addressing mode is designed to allow the host to implement scatter/gather control. The OTI-61 0/
OTI-611 will automatically switch between the base address registers 0 and 1 when it reaches the end of the
current register length. It will then send an interrupt to the host, whereupon the host may reload the used
segment registers. When the last segment of a page table is encountered, the appropriate LSx bit (LSO or LS1 )
must be set to indicate that the OTI-61 0/OTI-611 shou Id stop fetching data at the end of that segment.
PLAYBACK SEGMENT POSITION - CHANNEL N (WHERE N = 0-7)
7.5.4
Host Offset: See table below for corresponding entry for n
Bit
15
14
13
12
11
10
9
8
Read
SP15
SP14
SP13
SP12
SPll
SP10
SP9
SP8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
SP7
SP6
SP5
SP4
SP3
SP2
SPl
SPO
Initial
0
0
0
0
0
0
0
0
Bit
Description
SP[15:0]
Segment Position
Comment
Current byte position in active position
Specifies the offset in bytes of the next datum to be fetched by the OTI-61 0/OTI-611 bus master from the segment
pointed to by the corresponding Playback Base Address 0 or 1 register.
PROGRAMMING NOTE:
Host driver must keep track of active segment, based on the number of segment switch interrupts
, received. Remember that every time the START bit is set (Playback Channel Command), the OTI-61 0/
OTI-611 starts from base address register O.
Oak Technology
7-45
Technical Specification
011-610/011-611
7.5.5
PLAYBACK CHANNEL 7 INTERRUPT COUNT
Host Offset: OOF4h-OOFSh
Bit
15
14
13
12
11
10
9
8
Read
!C15
!C14
!C13
!C12
lel1
IC10
ICg
Ica
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
IC7
IC6
IC5
IC4
IC3
IC2
IC1
ICO
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
IC[15:0]
Interrupt Count
Number of interrupts generated by playback channel 7 since the
last time this register was read.
Counts the number of interrupts generated by the effects/modem playback channel. The register is reset every
time it is read. This register is generally used as an overrun detector when the channel is used for modem
operation~
Note that this register only exists for playback channel 7. Channels 0 through 6 do not support interrupt
counting.
Oak Technology
7-46
Technical Specification
Register Definitions
CAPTURE BASE ADDRESS - CHANNEL N (WHERE N = 8 OR 9)
7.5.6
Host Offset: See table on page 7-39 below for corresponding entry for n
Bit
31
30
29
28
27
26
25
24
RIW
BA3l
BA30
BA29
BA28
BA27
BA26
BA2S
BA24
Initial
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RIW
BA23
BA22
BA2l
BA20
BA19
BA18
BA17
BA16
Initial
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
RlW
BA1S
BA14
BA13
BA12
BAll
BA10
BA9
BA8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RIW
BA7
BA6
BAS
BA4
BA3
BA2
BAl
BAO
Initial
0
0
0
0
0
0
0
0
Bit
Description
BA[3l:0]
Base Address
Comment
Host physical memory address of the channel buffer
The host physical base address register. The register is used in both sequential and random access modes (see
Capture Channel Command).
PROGRAMMING NOTE:
These registers must be programmed with the physical address of a segment of the host buffer. In
random mode, this address must be aligned on a 128KB boundary. In sequential mode, this address
must be aligned on a DWORD boundary.
Oak Technology
7-47
Technical Specification
OTI-610/0TI-611
7.5.7
CAPTURE SEGMENT LENGTH - CHANNEL N (WHERE N = 8 OR 9)
Host Offset: See table on page 7-39 below for corresponding entry for n
Bit
15
14
13
12
11
10
9
8
RIW
SL1S
SL14
SL13
SL12
SL11
SL10
SL9
SL8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
SL7
SL6
SLS
SL4
SL3
SL2
SL1
SLO
Initial
0
0
0
0
0
0
0
0
Bit
Description
SL[lS:0]
Segment Length
Comment
Length in bytes of the associated host buffer segment. Actual
transfer is length +1.
This register specifies the length in bytes of the physical memory segment pointed to by the Capture Base Address
register. For random address mode (See Capture Channel Command), the range is 0 - 16, in WORD increments.
PROGRAMMING NOTES:
1. Note that the actual number of bytes transferred is the programmed length + 1. This allows true 64KB
transfers with a 16-bit register.
2. In random mode, this register is typically programmed by the OTI-61 0/OTI-611 DSP.
Oak Technology
7-48
Technical Specification
Register Definitions
CAPTURE CHANNEL COMMAND - CHANNEL N (WHERE N
3.5.8
= 8 OR 9)
Host Offset: See table on page 7-39 below for corresponding entry for n
Bit
15
14
13
12
11
10
9
8
RIW
START
RFIFO
RANDOM
MONO
DS
FREADY
LS
Reserved
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RlW
Reserved
Reserved
PAUSE
VDC4
VDC3
VDC2
VDCl
VDCO
Vlnitial
0
0
0
0
0
0
0
0
Bit
Description
START
Enable Channel
RFIFO
Reset FIFO
RANDOM
Random Mode Select
MONO
MONO Enable
DS
Data Size
FREADY
FIFO Ready
LS
Last Segment Flag
PAUSE
Pause Flag
VD[4:0]
Valid Data Count
Comment
1 - Enable bus master operation starting with base register set 0
o - Disable bus master operation
1 - Reset Data FIFO RIW pointers, start bit, valid data count
o - Normal operation
1 - Random addressing mode
0- Sequential addressing mode
1 - Monophonic format data (l-channel)
o - Stereophonic format data (2-channel)
1 - 8-bit samples
o - 16-bit samples ready to accept
1 - FIFO has valid data (used by OTI-610/0TI-611 DSP only)
1 - Segment specified by base address is the last segment
0- Normal operation
1 - Pause capture operation
o - Normal operation
Number of valid samples in the FIFO. Range 0-16 (used by OTI610/0TI-611 DSP only).
Setting the START bit will enable the bus master. If the channel FIFO is not empty, the bus master will request
the bus and memory transfer will begin. When the START bit is cleared, the bus master will stop after finishing
the current bus cycle.
PROGRAMMING NOTE:
Setting the START bit always resets the hardware to base register O. Pause/Resume and Set Position
programming should take this behavior into account.
In the random addressing mode (RANDOM bit set), the OTI-61 0/OTI-611 DSP expects the base register address
to be modulo 128K, and physically contiguous in memory. These restrictions force a maximum length of 64K
WORDS in random mode.
Oak Technology
7-49
Technical Specification
011-610/011-611
Unlike the playback channels, the capture channel sequential addressing mode uses a single base register to
implement a ping-pong (double buffer) buffer scheme. The Capture Segment Length register should be set to half
the host buffer size. The first time the segment length is reached, the OTI-61 0/OTI-611 sends an interrupt to the
host, then reloads the length counter only. Host buffer writes continue with the next sequential address. When
the segment length is reached for the second time, the host interrupt is sent, and the OTI-61 0/OTI-611 reloads
both the length counter and the base address from the corresponding registers. This sequence repeats until the
START bit is cleared or the appropriate LSx bit is encountered.
7.5.9
CAPTURE SEGMENT POSITION - CHANNEL N (WHERE N= 8 OR 9)
Host Offset: See table on page 7-39 below for corresponding entry for n
Bit
15
14
13
12
11
10
9
8
Read
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
SP7
SP6
SP5
SP4
SP3
SP2
SPl
SPO
Initial
0
0
0
0
0
0
0
0
Bit
Description
SP[15:0]
Segment Position
Comment
Current byte position in active position
Specifies the offset in bytes of the next datum to be written by the OTI-61 0/01"1-611 bus master to the segment
pointed to by the Capture Base Address register.
Oak Technology
7-50
Technical Specification
Register Definitions
7.5.10 CAPTURE INTERRUPT COUNT - CHANNEL 9
Host Offset: 003Ah-003Bh
Bit
15
14
13
12
11
10
9
8
Read
IC15
IC14
IC13
IC12
IC11
IC10
IC9
IC8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
IC7
IC6
IC5
IC4
IC3
10
ICl
ICO
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
IC[15:0]
Interrupt Count
Number of interrupts generated by channel 9 (capture channell)
since the last time this register was read.
Counts the number of interrupts generated by the effects/modem capture channel. The register is reset every time
it is read. This register is generally used as an overrun detector when the channel is used for modem operation.
Note that this register only exists for capture channell. Capture channel 0 does not support interrupt counting.
7.6
GAME PORT REGISTERS
The registers' locations are linear and byte addresses are Game Port Configuration 110 Base Address + host offset.
Host
Offset
Size
OOh-Olh
8 bit
Standard Game Port
08h-09h
16 bit
Digital Mode Game Port I & II X Position
OAh-OBh
16 bit
Digital Mode Game Port I & II Y Position
OCh
8 bit
Game Port Control
200h
8 bit
Standard Game Port
201h
8 bit
Standard Game Port (duplicate)
Oak Technology
Description
7-51
Technical Specification
OTI-610/0TI-611
7.6.1
STANDARD GAME PORT
Host Offset: OOOOh, 0001 h, and 0200h, 0201 h
Bit
7
6
5
4
3
2
1
0
RlW
PBB2
PBB1
PAB2
PAB1
PBY
PBX
PAY
PAX
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
PBB2
Port B Button 2
o - Button not pressed
PBB1
Port B Button 1
o - Button not pressed
PAB2
Port A Button 2
o - Button not pressed
PAB1
Port A Button 1
o - Button not pressed
PBY
Port BY-axis
o - Timer inactive
PBX
Port B X-axis
o - Timer inactive
PAY
Port A Y-axis
o - Timer inactive
PAX
Port A X-axis
o - Timer inactive
1 - Button pressed
1 - Button pressed
1 - Button pressed
1 - Button pressed
1 - Timer active
1 - Timer active
1 - Timer active
1 - Timer active
This register implements the standard analog game port functions. It is accessible from either the standard game
port 1/0 address of 200h/201 h or the PCI offset address of OOh/Ol h.
A write to this port will generate a trigger pulse to the internal SS8-like timer. A read from this port will get the
current game port button and position status.
PROGRAMMING NOTE:
The standard game port addresses of 200h and 201 h may be disabled using the SPEN bits in register OCh,
Game Port Control. The Power On default condition disables the standard game port addresses.
Oak Technology
7-52
Technical Specification
Register Definitions
7.6.2
DIGITAL MODE GAME PORT I & II X POSITION
Host Offset: OBh-09h
Bit
15
14
13
12
11
10
9
8
Read
Reserved
Reserved
Reserved
XA12
XA11
XA10
XA9
XAB
Initial
-
-
-
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
XA7
XA6
XAS
XA4
XA3
XA2
XA1
XAO
Initial
0
0
0
0
0
0
0
0
Bit
Description
Comment
XA[12:0]
Game Port X-axis Position
This register contains the current X-axis position of Digital Mode Game Port selected by the DGPSEL bit of the
Game Port Control (OCh) register.
Valid only if the POLLEN bit of the Game Port Control register is set.
7.6.3
DIGITAL MODE GAME PORT I & II Y POSITION
Host Offset: OAh-OBh
Bit
15
14
13
12
11
10
9
8
Read
Reserved
Reserved
Reserved
VA12
YA11
VA10
YA9
YAB
Initial
-
-
-
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
VA7
VA6
VAS
YA4
VA3
VA2
YA1
YAO
Initial
0
0
0
0
0
0
0
0
Bit
Description
YA[12:0]
Game Port V-axis Position
Comment
This register contains the currentY-axis position of Digital Mode Game Port selected by the DGPSEL bit of the
Game Port Control (0068h) register.
Valid only if the POLLEN bit of the Game Port Control register is set.
Oak Technology
7-53
Technical Specification
OTI-610/0TI-611
7.6.4
GAME PORT CONTROL
Host Offset: OCh
Bit
7
6
5
4
3
2
1
0
Read
POLLEN
SPEN
Reserved
DGPSEL
PBB2
PBB1
PBA2
PBA1
Write
POLLEN
SPEN
Reserved
DGPSEL
Reserved
Reserved
Reserved
Reserved
Initial
0
0
0
0
0
0
0
0
..
Comment
Bit
Description
POLLEN
Hardware Poll Enable
1 - Enable hardware polling of analog game port
0- Disable hardware polling of analog game port
SPEN
Standard Port Enable
1 - Enable standard game port response at 200h/201 h
1 - Access Digital Mode Game Port II using Game Port Position
registers
0- Access Digital Mode Game Port I using Game Port Position
registers
DGPSEL
Digital Mode Game Port Select
PBB2
Port B Button 2
o - Button
PBB1
Port B Button 1
o - Button
PAB2
Port A Button 2
o - Button
PAB1
Port A Button 1
o - Button
1 Button pressed
not pressed
1 Button pressed
not pressed
1 Button pressed
not pressed
1 Button pressed
not pressed
This register contains miscellaneous game port control functions for both the analog and digital game port
implementations.
The POLLEN bit enables the OTI-611 auto-polling of the analog joystick position. The OTI-61 0/OTI-611 utilizes
hardware counters to measure the trigger time period of each axis of the analog joystick in a manner similar to
the method normally used by software joystick routines. This hardware polling relieves the software of the task of
waiting for the joystick time-out, thus reducing the CPU load.
The DGPSEL bit is used to control which digital game port values are read when the Game Port I & II X Position
and Game Port I & II Y Position registers are read.
Oak Technology
7-54
Technical Specification
Register Definitions
7.7
OTI-611 FAX/MODEM I/O REGISTER DEFINITIONS
The registers' locations are linear and byte addresses are Modem Configuration liD Base Address + host offset.
Host
Offset
Size
40h-41h
16 bit
Modem Data [15:0] Input and Output
42h
8 bit
Index Register Address [7:0J
43h
8 bit
Codec Index Register Address [7:0J
44h-45h
16 bit
Codec Data [15:0] Input and Output
46h
8 bit
ID
47h
8 bit
Modem 1/0 Space Control
7.7.1
Description
MODEM DATA REGISTERS
Host Offset: 40h-41 h
Bit
15
14
13
12
11
10
9
8
Read
IMD15
IMD14
IMD13
IMD12
IMDll
IMD10
IMD9
IMD8
Write
OMD15
OMD14
OMD13
OMD12
OMDll
OMD10
OMD9
OMD8
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
IMD7
IMD6
IMDS
IMD4
IMD3
IMD2
IMDl
IMDO
Write
OMD7
OMD6
OMD5
OMD4
OMD3
OMD2
OMDl
OMDO
Initial
0
0
0
0
0
0
0
0
Bit
Description
IMD[lS:0]
Incoming Modem Data
OMD[1S:0]
Outgoing Modem Data
Oak Technology
Comment
7-55
Technical Specification
011-610/011-611
7.7.2
INDEX ADDRESS REGISTER
Host Offset: 42h
7
Bit
-- ..
fllW
J
6
' •• 1''1_'"
Initial
..... . _11_-
J
I
0
0
I
...... _, ..-
I
0
I
....... _....
0
I
I
..... ,,-,.0
I
I
....... _,0
o
1
2
I
........ _, ...
I
0
I
........ _, ..
I
-
0
Comment
Bit
Description
MINDX[7:0]
Modem Index Register Address
7.7.3
3
4
5
CODEC INDEX REGISTER
Host Offset: 43 h
Bit
7
6
5
4
3
2
1
0
R/W
CMDBSY
DVS
CACC
CINDX4
CINDX3
C1NDX2
C1NDX1
CINDXO
Initial
0
0
0
0
0
0
0
0
Bit
Description
CI NDX [4:0]
Codec Index Register Address
CACC
Codec Access Type
DVS
Data Valid Status
CMDBSY
Command Busy Status
Comment
1 = Write Access
o = Read Access
1 = Current indexed register can be read
1 = Current index address is not yet complete
This register is the same as register 6Ch in the audio function registers. This allows codec access from both
configuration spaces.
Oak Technology
7-56
Technical Specification
Register Definitions
7.7.4
CODEC DATA REGISTERS
Host Offset: 44h-45h
Bit
15
14
Read
IC015
Write
13
12
11
10
9
8
IC014
IC013
IC012
ICOll
IC010
IC09
IC08
OC015
OC014
OC013
OC012
OCOll
OC010
OC09
OC08
Initial
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Read
IC07
IC06
IC05
IC04
IC03
IC02
ICOl
ICOO
Write
OC07
OC06
OC05
OC04
OC03
OC02
OC01
OCOO
Initial
0
0
0
0
0
0
0
0
!
Bit
Description
ICO[15:0]
Incoming Codec Oata
OCO[15:0]
Outgoing Codec Data
Comment
These register is the same as register 6Ch-6Dh in the audio function registers. This allows co dec access from both
configuration spaces.
Oak Technology
7-57
Technical Specification
011-610/011-611
EXTERNAL OUTPUTS REGISTER
7.7.5
Host Offset: 46h
Bit
7
6
5
4
3
2
1
0
RlW
SPOUTO
ST7546
HDSTRLY
CODPWR
SPKRMT
CODRST
ClD
OHRLY
Initial
0
0
0
0
0
1
1
1
Bit
Description
SPOUT[2:0]
Spare Output Pins
ST7546
ST7546 Mode Select
HDSTRLY
Headset (Voice) Relay Control
CODPWR
Codec Power Down
SPKRMT
Speaker Mute Control
CODRST
Codec Reset
CIO
Caller 10 Relay Control
Active low
OHRLY
Off-Hook Relay Control
Active low
Comment
Software-controlled outputs
Controls CODEC_PIN on OTI-611. Connects to HCO pin on
ST7546 Modem Codec.
o = Codec Reset
Default value = 0007
Same as Index 2 Extout[7:0] register.
7.7.6
MODEM 1/0 SPACE CONTROL
Host Offset: 47h
Bit
7
6
5
4
3
2
1
0
RIW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10Cl
lOCO
Initial
0
0
0
0
0
0
0
0
Bit
IOC[1:0]
Oak Technology
Description
1/0 Space Control
Comment
110011 : Use PCI assigned 1/0 space only
111 0": Decode both PC! VO space and COM3 space (3 E8h-3 EFh)
111111: Decode both PC! 1/0 space and COM4 space (2E8h-2EFh)
7-58
Technical Specification
AC-LINK
CHARACTERISTICS
CHAPTER 8
8.1
AUDIO CODEC '97 COMPONENT SPECIFICATION OVERVIEW
The Audio Codec '97 Component Specification was created by Intel Corporation, National Semiconductor
Corporation, Creative Laboratories, Inc., Yamaha Corporation, and Analog Devices, Inc., and was first published
by Intel Corporation on May 17,1996.
Consult the Audio Codec '97 Component Specification for complete details on:
•
AC-Link operation
•
Register control and register bit definition of the AC '97 Codec
•
AC-Link slot definitions
Throughout this chapter, the Audio Codec '97 Component Specification may also be referred to as "AC '97 Codec
Specification," or simply as "AC '97.f! The codec device discussed in the Audio Codec '97 Component
Specification may be referred to as "AC '97 Codec." The term AC-Link referenced in the Audio Codec '97
Component Specification may also be referred to as "AC-Link."
The Audio Codec '97 Component Specification defines the codec component of an audio or audio/
communications system, as well as the communications link between it and its companion digital controller.
The AC '97 digital controller and the AC '97 Codec together comprise the AC '97 System.
8.2
AC '97 AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
A 5-pin digital serial interface called AC-Link connects the OTI-61 0/OTI-611 to any AC '97 Codec.
AC-Link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio
streams, as well as control register accesses employing a time division multiplexed (TOM) scheme.
The AC-Link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20bit sample resolution, allowing support of 16-bit, 18-bit, and 20-bit samples within each data slot of the data
stream.
The 011-610 and 011-611 support 16-bit samples and set the trailing 4 bits set to 0 within the AC '97 20-bit
data slots.
Oak Technology
8-1
Technical Specification
011-610/011-611
Note:
Throughout the rest of this chapter, AC-link signal names will be given along with the equivalent
OTI-610 and OTI-611 signal names. AC-link signal names appearing in descriptive text will be printed
in italics and will be enclosed within parentheses.
Tables containing signal names will show both the OTI-61 0/OTI-611 and AC-link signal names in the
same way.
Example:
OTI-610/011-611 Signal Name
AC-Link Signal Name
(RESET#)
ARESET#
Timing diagrams will be presented with the OTI-61 0/OTI-611 signal name in the illustration.
Synchronization of all AC-link data transactions is signaled by the OTI-61 0 or OTI-611. The AC '97 Codec
functions as a slave to the OTI-61 0 or OTI-611 .
The AC '97 Codec drives a fixed 12.288-MHz serial bit clock, ASCLK (BIT_CLK) [derived from the AC '97 Codec
crystal clock frequency source] onto AC-link, which the OTI-61 0 or OTI-611 controller then qualifies with a
synchronization signal, AFS (SYNC), to construct audio frames.
AFS (SYNC), fixed at 48 KHz, is derived by dividing down ASCLK (BIT_CLK). ASCLK (BIT_CL/() provides the
necessary clocking granularity to support twelve 20-bit outgoing and incoming time slots. AC-link serial data is
transitioned on each rising edge of ASCLK (BIT_CLK).
The receiver of AC-link data (the AC '97 Codec for outgoing data from the OTI-61 0/OTI-611 or the OTI-61 0/
OTI-611 for incoming data from the AC '97 Codec), samples each serial bit on the falling edges of ASCLK
(BIT_CLK).
The AC-Link protocol provides for a special 16-bit (13 bits defined, with 3 reserved trailing bit positions) time slot
(slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A "1/1
in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been
assigned to a data stream and contains valid data. If a slot is "tagged" invalid, it is the responsibility of the source
of the data (the AC '97 Codec for the input stream to the OTI-61 0/OTI-611 or the OTI-61 0 or OTI-611 for the
output stream to the AC '97 Codec), to set all bit positions with Os during that slot's active time.
AFS (SYNC) remains high for a total duration of 16 ASCLKs (BIT_CLKs) at the beginning of each audio frame.
The portion of the audio frame where AFS (SYNC) is high is defined as the "Tag Phase./1 The remainder of the
audio frame where AFS (SYNC) is low is defined as the "Data Phase."
o
Slot It
7
AFS JI~
10
11
12
_______________----II
OUTGOING STREAMS
INCOMING STREAMS
Tag Phase
~
\.
Data Phase
.\
Figure 8-1: AC '97 Standard Bi-directional Audio Frame
Oak Technology
8-2
Technical Specification
AC-Link Characteristics
The table below shows the data streams currently defined by the AC '97 Specification and the support provided
by either the OTI-61 or the OTI-611. Slot directions are given relative to the OTI-61 or OTI-611 and should be
reversed if referenced to the AC '97 Codec.
a
a
Support
AC' 97 Data Stream
Slots/Slot #
011-610
OTI-611
Notes
Control
Control Register Write Port
2 output
Slot! 1,2
Yes
Yes
1
Status
Status Register Read Port
2 input
Slot 1,2
Yes
Yes
1
PCM Playback Data
2-channel composite PCM output stream (UR)
2 output
Slot 3L, 4R
Yes
Yes
1
PCM Record Data
2-channel composite PCM input stream (UR)
2 input
Slot 3L, 4R
Yes
Yes
1
Optional Modem Line Codec Output Stream
Modem line Codec DAC output stream to OTI-612 or
AC '97 Codec
1 output
Slot 5
Fi lied with Os
Yes
2
Optional Modem Line Codec Input Stream
Modem line Codec DAC input stream to OTI-612 or AC
'97 Codec
1 input
Slot 5
Fi lied with Os
Yes
2
Optional Dedicated Microphone Input
Microphone input stream in support of Acoustic Echo
Cancellations and/or other voice applications
1 input
Slot 6
Filled with Os
No
Fi lied with Os
3
RESERVED - Undefined.
Fi lied with Os by OTI-61 0/OTI-611
6 output
Slot 6-12
Fi lied with Os
Fi lied with Os
RESERVED - undefined
Filled with Os by OTI-612 or AC '97 Codec
5 input
Slot 7-12
Filled with Os
Fi lied with Os
Notes (from the AC '97 Specification):
1.
2.
3.
Oak Technology
AC '97 controlier/AC '97 Codec pair interoperability can only be guaranteed for non-optional
AC '97 audio features.
Modem interoperability is not expected between AC '97 controller/AC '97 Codec pairs that
aren't sourced as a matched set by the same vendor. Given this, each vendor's AC '97 controller
implicitly knows what the modem OACIAOC resolution are in the AC '97 Codec version wi
modem support by inspecting the vendor 10 registers.
An audio component vendor who develops an AC '97 Codec with optional dedicated
microphone channel support should also offer an AC '97 controller to fully support this feature
with a matched set solution.
8-3
Technical Specification
011-610/011-611
Software Driver Support and AC '97 Controller/AC '97 Interoperability
The software driver written for the OTI-61 0/OTI-611 is responsible for exposing and managing the AC '97 Codec
analog features. Interoperability requires that every AC '97 controller and AC '97 driver support the basic AC '97
Codec features.
Mono PCM output always translates in the AC '97 controller to two mono channels (L and R) on the AC-Link.
The following optional AC '97 features should also be supported by all AC '97 controller drivers when determined
to be present:
•
Tone control
•
Loudness
•
Simulated stereo
•
3D stereo enhancement
•
Headphone out
Other features may not make sense to support unless there is also support in the AC '97 controller. In these cases,
interoperability may be limited to an AC '97 controller/AC '97 analog pair sourced by the same vendor:
•
Modem ADC and DAC
•
Third ADC input channel
•
Vendor-specific features
8.3
OTI-610/0TI-611 IN THE AC '97 SYSTEM
The OTI-61 0 and OTI-611 support the AC-Link, which is defined in the Audio Codec '97 Component
Specification, as a peer-to-peer communications link between a digital audio controller and an Audio Codec, or
as a digital audio/communications controller and a dual audio/modem codec.
The OTI-61 0 and OTI-611 support multiple codec types, including the AC '97 type. The OTI-61 0 or OTI-611
therefore can function as the "AC '97 Digital Controller" referred to in the Audio Codec '97 Component
Specification.
The OTI-61 0 supports multiple codecs. If the codec type selected isAC '97, then the OTI-61 0 functions as an
audio-only AC '97 digital controller, and would be typically used in an AC '97 system with an audio-only AC '97
C~&.
.
The OTI-611 supports multiple codecs. If the codec type selected is AC '97, then the OTI-611 functions as an
audio and communications AC '97 digital controller and would be typically used in an AC '97 system with the
OTI-612 dual audio and communications AC '97 compliant Codec, or any dual audio and communications AC
'97 Codec supporting modem outgoing and incoming 16-bit data in time slot 5.
See Chapter 3 for more detai Is on codecs supported by the OTI-61 0 and OTI-611 .
Oak Tec~nology
8-4
Technical Specification
AC-Link Characteristics
8_4
AC '97 SYSTEM IMPLEMENTATION
The AC '97 System Diagram in Figure 8-2 and the immediately following text is reproduced directly from the AC
'97 Codec Specification.
Standard system audio i/o
(Audio Codec '97 architecture supports
migration of sources toward digital)
Bus sources ~
-Wave
-DirectX
-soft CD or DVD
-soft AC-3
Digital (12S or equlv) s::J0urces
-cost reduced CD (or DVD)
-HW digital synthesizer
-HW AC-3 decode
1111
I - - - - - - - - - [LII_ - - - - I
II II
I
I multi-function
I
=1
=1
=1
accelerator
:: ::
data pump, ...
II II
I
1
__
Analog mixer sources
-CD: Redbook audio (or DVD)
-VIDEO: TV tuner or video cap
-AUX: int source or upgrade synth
headset
III
=s_~
PC riser
I
modem
I
I I I I--IlWoU.:LW...lI~_
1 I L _ .modBm ..Ex: _ .
AC '97 analog
: '- __ mot:lsrn J:Jx: _
L __ _
fIJot:Iem..!x~_
(tolfrom DAA)
Description:
eFull-duplex, 16-bit stereo, 90 dB SNR, 2-chip motherboard solution
eDigital/analog split for scaleable featureslhigher quality
eDigital: PCI stand-alone or multi-function combined audioltelephony
bus IIF, sample rate conversion, AC-link & control, plus options
vendor specific package: supports a scaleable audio family
eAnalog: high quality, fixed 48K sample rate DAC's and ADC's
industry standard package: standard pinout, mixer, interconnect, & i/o
options: tone, 3D, 18 or 20 bits, addt'l channels, modem ADC & DAC •••
0
eJ
headphones
or headset wI mic
-and/or-
~
I I
2 speakers
wI desktop mic
-and/or-
III
I I
Pro Logic stereo
played thru
Consumer
Equipment
via line out
(or decoded
by the speakers)
Digital audio "outside the box"
is an extension to system audio
,--------------- j -.-1--
digital
audio
USB,
I
I
I
_I
-I
1394
I
1
1
I
-
Digital
Speakers
or
Consumer
Equipment
.::::::::
t::::::::
-
l1li
II
2 6 speakers attached to
L ___________
PC
__
or_Consumer
______
Equipment
____ _
Figure 8-2: AC '97 System Diagram
Figure 8-2 " .. . shows the essential features of an AC '97 audio design. The AC '97 analog component performs
fixed 48K sample rate DAC & ADC conversions, mixing, and analog processing (tone, 3D stereo enhancement,
etc.). It always functions as a slave to an AC '97 digital controller which must be implemented in the digital
portion of any AC '97 audio system."
liThe AC '97 controller, primarily targeted for PCI, can be as simple as a stand-alone design which supports high
quality sample rate conversions to/from 48Kss, Sound Blaster* compatibility, FM and/or wavetable synthesis, with
optional DirectSound* acceleration, AC-3 decode, etc. The AC '97 controller may also be embedded within a
pel multifunction accelerator, offering higher levels of integration by combining audio with telephony or
graphics. However, nothing precludes ISA, USB, or 1394 designs based on the AC '97 architecture."
"The digital link, ''AC-Iink'', connecting the AC '97 controller to the AC '97 analog component is a bi-directional,
5-wire, serial TDM format interface, designed for dedicated point to point interconnect on a circuit board."
"The diagram shows the most common (high attach rate) connections, some digital and some analog. PC audio
today requires that a number of analog sources be supported in the analog mixer. Over time, it will become
attractive from both cost and functionality perspectives to move these sources toward dedicated digital
connections or onto the bus2. The AC '97 architecture facilitates this migration."
Oak Technology
8-5
Technical Specification
OTI-610/0TI-611
liThe AC '97 architecture is designed primarily to support stereo 2-speaker PC audio. However, two multichannel extensions are shown in the system diagram, one utilizing the AC '97 architecture and one independent
of it:/I
•
"Multi-channel encoded stereo (such as Dolby* ProLogic*) can be played out through the 2-channel AC '97
audio subsystem. This type of signal can be played on normal stereo speakers, decoded into 4 channels by
the speakers, or sent to consumer equipment via a stereo analog line out connection. II
•
"True 2/4/6 channel digital audio output (such as 5.1 channel Dolby AC-3*) can bypass the 2-channel AC '97
audio subsystem and be transmitted via a digital link (such as USB or 1394) to digital speakers or digital
ready consumer equipment which drives a multi-speaker arrangement such as the home theateiI . N
Note:
The support for dedicated digital connections requires frequency locking and sample rate conversion
capabilities in the AC '97 controller in order to reconcile independent time bases, the digital source, and
AC '97's fixed 48Kss.
There are many PC audio sources that are not currently bus independent, such as DOS games, HIW
accelerated Windows 95 games, CD Redbook audio, and DVD-ROM movies w/HW AC-3 decode. In
order to hear ALL PC audio sources through one set of digitally connected speakers, backwards
compatibility must be addressed.
8.5
011-610/011-611 CONNECTION TO 1HE AC '97 CODEC
The OTI-61 0 or OTI-611 communicates with the OTI-612 AC '97 co'mpatible dual audio and communications
codec (or any other AC '97 compatible audio codec, or dual audio and communications codec) via a digital
serial link called AC-Link. AC-Link is a 5-pin, bi-directional, fixed data rate, serial PCM digital stream. It
handles multiple input and output audio streams, as well as control register accesses to the AC '97 Codec device
employing a time division multiplexed (TOM) scheme. The AC-Link architecture divides each audio frame into
12 outgoing and 12 incoming data streams, each with 20-bit sample resolution.
All digital audio streams, optional modem line codec streams, and command/status information are
communicated over this point-to-point serial interconnect interface.
See Chapter 3 for specific details on physical connections between the OTI-6TO and OTI-611 and the various
types of AC '97 Codec packages.
A breakout of the signals connecting the OTI-61 O/OTI-611 to an AC '97 Codec is shown in the following table and figure.
OTI-610/0Tl-611
Signal Name
Type
OTI-612 or AC 197
Codec Signal NameAC-Link Signal Name
Type
ARESET#
0
RESET#
I
Master HIW Reset to AC 197 Codec from OTI-610 or
OTI-611
AFS
0
SYNC
I
48-KHz fixed rate sample sync from OTI-610 or OTI-611
ASClK
I
BIT_ClK
0
12.288-MHz serial data clock (Fxl2 from AC 197 Codec)
to OTI-610 or OTI-611. Fx=24.576 MHz
ASDO
0
SDATA_OUT
I
Serial, time division multiplexed output stream to AC 197
Codec from OTI-610 or OTI-611
ASDI
1
SDATA_IN
0
Oak Technology
Description
Serial, time division multiplexed output stream from AC
197 Codec to OTI-610 or OTI-611
8-6
Technical Specification
AC-Link Characteristics
ARESET#
ASDO
ASDI
ASClK
AFS
RESEll
RESEll
SDATA OUT
SDATA IN
BIT ClK
SYNC
SDATA_OUT
SDATA_IN
BIT_ClK
SYNC
-:::L
D
-=r
Fx
24. 576
AC-Link
MHz
OTI-612
OTI-610
or
or
AC'97
CODEC
OTI-611
Figure 8-3: AC-Link Connection to AC '97 Compatible Co dec
8.6
RESETTING THE AC '97 CODEC
The AC '97
1.
2.
3.
Codec Specification provides for three types of AC '97 Codec reset:
a Cold AC '97 Reset where all AC '97 Codec logic (registers included) is initialized to its default state
a Warm AC '97 Reset where the contents of the AC '97 Codec register set are left unaltered
a Register Reset, which only initializes the AC '97 Codec registers to their default states
The current Power Down state would ultimately dictate which form of AC '97 reset is appropriate.
Unless a "cold" or "register" reset (a write to the Reset register) is performed, wherein the AC '97 Codec registers
are initialized to their default values, the AC '97 Codec registers are required to keep state during all Power
Down modes.
After signaling a reset to AC '97 Codec, the OTI-61 O/OTI-611 wi II not attempt to play or capture audio data until
it has sampled a "Co dec Ready" indication from the AC '97 Codec.
8.6.1
COLD AC 197 RESET
A Cold Reset activates AC-Link as well as resets the AC '97 Codec.
A Cold Reset of the AC '97 Codec is achieved by the OTI-61 O/OTI-611 driver asserting ARESET# (RESET#) low
for the minimum specified time, or by the OTI-61 0/OTI-611 asserting ARESET# (RESET#) low for the minimum
specified time during its Power On sequence.
By driving ARESET# (RESET#) low ASCLK (BIT_eLK), and ASDO (SDATA_OUT) will be activated, or re-activated
as the case may be, by the AC '97 Codec. All AC '97 Codec control registers will be initialized to their default
Power On reset values.
ARESET# (RESET#) is an asynchronous input to the AC '97 Codec.
Oak Technology
8-7
Technical Specification
011-610/011-611
8.6.2
WARM AC 197 CODEC RESET
A warm AC '97 Codec reset will re-activate the AC-Link without altering the currentAC '97 Codec register values.
A Warm Reset is signaled by the OTI-61 0/OTI-611 driver setting AFS (SYNC) high for a minimum of 1uS in the
absence of ASCLK (BIT_ CLK).
Within normal audio frames, AFS (SYNC) is a synchronous AC '97 Codec input. However, in the absence of
ASCLK (BIT_CLK), AFS (SYNC) is treated as an asynchronous input used in the generation of a warm reset to the
AC '97 Codec.
The AC '97 Codec will not respond with the activation of ASCLK (BIT_CLK) until AFS (SYNC) has been driven low
by the OTI-61 0/OTI-611 and has been sampled low again by the AC '97 Codec. This prevents the false detection
of a new audio frame.
8.6.3
REGISTER RESET OF AC 197 CODEC
A register reset of the AC '97 Codec is achieved by writing any value to the AC '97 Codec Reset register (Index
OOh), which causes all registers to revert to their default values.
8.7
AC-LINK LOW POWER MODE
The AC-Link signals can be placed in a low-power mode. When the AC '97 Codec General Purpose register
(20h) is programmed to the appropriate value, both AC-Link signals, ASCLK (BIT_CLK) and ASDI (SDATA_IN),
will be brought to and held at a logic low-voltage level.
-----II
AFS
\~---
ASCLK
ASDO
ASDI
NOTE: ASCLK not to scale
Figure 8-4: AC-Link Power Down Operation
ASCLK (BIT_CLK) and ASDI (SDATA_IN) from the AC '97 Codec to the OTI-61 0/OTI-611 are transitioned low
immediately (within the maximum specified time) following the decode of the write to the General Purpose
register (26h) with PR4. When the OTI-61 0/OTI-611 driver is ready to program the AC-Link into its low-power
mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. At this point in time it is
assumed that all sources of audio input have also been neutralized.
The OTI-61 0/OTI-611 driver should also drive the OTI-61 0/OTI-611 AC-Link signals, AFS (SYNC) and ASDO
(SDATA_OUT), low after programming AC '97 to this low-power, "halted" mode.
Oak Technology
8-8
Technical Specification
AC-Link Characteristics
8.7.1
WAKING UP AC-LlNK
Once the AC '97 Codec has been instructed to halt BIT_ClK, a special "wake up" protocol must be used to bring
the AC-Link to the active mode since normal audio output and input frames cannot be communicated in the
absence of BIT_ClK.
There are two methods for bringing the AC-Link out of a low power, halted mode: Cold AC '97 Reset and Warm
AC '97 Reset. The current Power Down state would ultimately dictate which form of AC '97 reset is appropriate.
Regardless of the method used, the OTI-61 0/OTI-611 will perform the wake-up task.
Once powered down, re-activation of the AC-Link via re-assertion of the AFS (SYNC) signal (Warm AC '97 Reset
method) must not occur for a minimum of four audio frame times following the frame in which the Power Down
was triggered. When AC-Link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).
8.7.2
EXAMPLES OF AC-LlNK POWER DOWN OPERATIONS
The following illustrations and text are taken directly from the Audio Codec '97 Component Specification.
PR1=O
PR2=O
DAC=1
ANL=1
&
&
Ready = 1
~
Figure 8-5: One Example of AC '97 Power Down & Power Up Flow
The above figure illustrates one example procedure to do a complete power down ofAC /97. From normal
operation, sequential writes to the General Purpose Register are performed to power down AC /97 a piece at a
time. After everything has been shut off, a final write (of PR4) can be executed to shut down the AC '97's digital
interface (AC-Link). The part will remain in sleep mode with all its registers holding their static values. To wake
up, the AC '97 controller will send pulse on the sync line issuing a warm reset. This will restart AC '97's digital
interface (resetting PR4 to zero). AC '97 can also be woken up with a cold reset. A cold reset will cause a loss of
values of the registers as a cold reset will set them to their default states. When a section is powered back on the
Power Down Control/Status register (index 26h) should be read to verify that the section is ready (i.e., stable)
before attempting any operation that requires it.
Oak Technology
8-9
Technical Specification
OTI-610/0TI-611
. ""'- PRO=O./ . ""'- P R 1=0 . /
&
ADC=1
&
DAC=1
Figure 8-6: AC '97 Power Down & Power Up Flow with Analog Still Alive
The above figure illustrates a state when all the mixers should work with the static volume settings that are
contained in their associated registers. This is used when the user could be playing a CD (or external LINE_IN
source) through AC '97 to the speakers but have most of the system in low power mode. The procedure for this
follows the previous except that the analog mixer is never shut down.
8.8
TESTABILITY
The AC '97 Specification lists two test modes. One is for ATE in-circuit tests and the other is optional for vendor,..
specific tests. Regardless of the test mode, the OTI-61 0/OTI-611 must issue a "cold" reset to resume normal
operation of theAC '97 Codec.
All AC-Link signals are normally low through the trailing edge of ARESET# (RESET#).
When the AC '97 Codec is placed in the ATE in-circuit test mode, its digital AC-Link outputs (i.e., BIT_ClK and
SDATA_IN) are driven to a high-impedance state. This allows ATE in-circuit testing of the OTI-61 0/OTI-611 digital
controller.
The AC '97 Codec enters the ATE in-circuit test mode when the OTI-61 0/OTI-611 drives ASDO (SDATA_OUT)
high at the trailing edge of ARESET# (RESET#) and the AC '97 Codec samples ASDO (SDATA_OUT) as high at the
trailing edge of ARESET# (RESET#).
Oak Technology
8-10
Technical Specification
AC-Link Characteristics
8.9
AC-LINK DC AND AC CHARACTERISTICS
The AC '97 Specification recommends that the digital AC-Link interface portion of the AC '97 Codec component
be capable of operating at either 5V or 3.3Y, depending on which DVdd is supplied to it. The AC '97
Specification lists DVdd for the AC '97 Codec at DVdd = 5V or DVdd = 3.3Y, or alternatively, DVdd=5Vor
DVdd=3V (recommended). Consult the Audio Codec '97 Component Specification for complete details on the
AC '97 Codec DC characteristics.
The AC '97 Specification also states that when designed into an AC '97 system, the AC '97 digital controller and
AC '97 Codec should always run off the same DVdd voltage level.
The OTI-61 0 and OTI-611 digital controllers operate only at Vdd = +5VDC. Therefore, when interfaced to an AC
'97 Codec, the AC '97 Codec DVdd must also operate at +5VDC.
8.9.1
DC CHARACTERISTICS
The table below represents the DC characteristics of the OTI-61 0 and OTI-611 for AC-Link signals ARESET#
(RESET#), AFS (SYNC), ASCLK (BIT_CLK), ASDI (SDATA_IN), and ASDO (SDATA_OUT).
Parameter
Symbol
Min
Type
Max
Units
Input Voltage Range
V.10
-0.30
-
DVdd + 0.30
V
Low Level Input Voltage
Vii
-
-
0.30 x Vdd
V
High Level Input Voltage
V ih
0.40 x Vdd
-
-
V
High Level Output Voltage
V Oh
0.50 x Vdd
-
-
V
Low Level Output Voltage
VOl
-
-
0.20 x Vdd
V
Input leakage Current (RESET#, SYNC, SDATA_OUT, AClink Inputs)
-
-10
-
10
uA
Input leakage Current (BIT_ClK, SDATA_IN, AC-link
Outputs)
-
-10
-
10
uA
Output Buffer Drive Current
-
-
5
-
rnA
Note:
Tamb'lent = 25°C, AVdd =Vdd = 5VDC; AVss =Vss = OV; 50pF external load)
Oak Technology
8-11
Technical Specification
OTI-610/0TI-611
8.9.2
Tambient
8.9.3
ACTIMING CHARACTERISTICS
= 25°C, AVdd =Vdd = 5VDC; AVss =Vss = OV; 50pF external load)
RESET
Cold Reset
TrsClow
Trst2clk
ARESET#
AFS
-
_ _ _flJLfU1J
Figure 8-7: Cold AC '97 Reset Timing
Parameter
Symbol
Min
Type
Max
Units
ARESET (RESET#) active low pulse width
Trst.low
1.0
-
-
uS
ARESET (RESET#) inactive to ASCLK (BIT_CLK) startup delay
Trst2c1k
162.8
-
-
nS
Warm Reset
_----J} T_~~h ~_T_syn_c2_Clk--+~I_ _ __
AFS
ASCLK ________________________~~
Figure 8-8: WarmAC '97 Reset Timing
Parameter
Symbol
Min
Type
Max
Units
AFS (SYNC) active high pulse width
Tsync_high
-
1.3
-
uS
AFS (SYNC) inactive to ASCLK (BIT_CLK) startup delay
Tsync2c1k
162.8
-
-
nS
Oak Technology
8-12
Technical Specification
AC-Link Characteristics
8.10 CLOCKS
(50pF external load)
Parameter
Symbol
ASCLK (BIT_ CLK) frequency
ASCLK (BIT_ CLK) period
Tclk...period
ASCLK (BIT_CLK) output jitter
Min
Type
Max
Units
-
12.288
-
MHz
-
81.4
-
nS
-
-
750
pS
ASCLK (BIT_CLK) high pulse width (note 1)
Tclk_high
32.56
40.7
48.84
nS
ASCLK (BIT_ CLK) low pulse width (note 1)
Tclk...low
32.56
40.7
48.84
nS
-
48.0
-
KHz
AFS (SYNC) frequency
AFS (SYNC) period
T
sync~n
"od
-
20.8
-
uS
AFS (SYNC) high pulse width
Tsync_high
-
1.3
-
uS
AFS (SYNC) low pulse width
TsyncJow
-
19.5
-
uS
SYNC
J
Tsync_high
Figure 8-9: Clock Timing
Oak Technology
8-13
Technical Specification
OTI-610/0TI-611
8.11 DATA SETUP AND HOLD
(50pF external load)
Symbol
Min
Type
Max
Units
Setup to faiiing edge of ASCLK (BiT_eLK)
Tsetup
15.0
-
-
nS
Hold from falling edge of ASCLK (BIT_CLIO
Tho1d
5.0
-
-
nS
Parameter
Tsetup
ASCLK
1 r-
11\~_-J7t
\----
ASDI,
ASDO
AFS
~---II",--
Thold
Figure 8-10: Data Setup and Hold Timing
Oak Technology
8-14
Technical Specification
AC-Link Characteristics
8.12 SIGNAL RISE AND FALL TIMES
(50pF external load)
Parameter
Symbol
Min
Type
Max
Units
ASCLK (BIT_CLK) rise time
Triseclk
2
-
-
nS
ASCLK (BIT_ CLK) fall time
Tfallclk
2
-
-
nS
AFS (SYNC) rise time
Trisesync
2
-
-
nS
AFS (SYNq fall time
Tfallsync
2
-
-
nS
ASDI (SDATA_IN) rise time
Trisedin
2
-
-
nS
ASDI (SDATA_QUT) fall time
Tfall din
2
-
nS
ASDO (SDATA_QUT) rise time
Trisedout
2
-
-
nS
ASDO (SDATA_ QU7) fall time
Tfall dout
2
-
-
nS
ASCLK
~
:I L j I:
T rise""
Tfalldk
~j
:I
~ Tfall
AFS
Trisesync
ASDI
~
:I L j I:
Trise"'n
ASDO
sync
Tfalldin
~
Trisedout
:I L j I:
Tfalldout
Figure 8-11: AC '97 Signals Rise and Fall Times
Oak Technology
8-15
Technical Specification
011-610/011-611
8.13 AC-LINK LOW-POWER MODE TIMING
Parameter
End of Slot 2 to ASCLK (BIT_CLK), ASDI (SDATA_IN) low
AFS
SLOT 1
Symbol
Min
Type
Max
Units
Ts2..Jldown
-
-
1.0
uS
SLOT 2
ASCLK
AS DO
DON'T CARE
WRITE TO 0x26
ASDI
NOTE: ASCLK NOT TO SCALE
Figure 8-12: AC-Link Low-Power Mode Timing
Oak Technology
8-16
Technical Specification
AC-Link Characteristics
8.14 ATE IN-CIRCUIT TEST MODE TIMING
Parameter
Setup to trailing edge of ARESET# (RESET#)
Symbol
Min
Type
Max
Units
Tsetup2rst
15.0
-
-
nS
Toff
-
-
25.0
nS
Rising edge of ARESET# (RESET#) to Hi-Z delay
t
RESET#
SDATA_OUT
d
SDATA_IN, BIT_elK
Hi-Z
TOft
Figure 8-13: ATE In-Circuit Test Mode Timing
Oak Technology
8-17
Technical Specification
011-610/011-611
(This page intentionally left blank)
Oak Technology
8-18
Technical Specification
ELECTRICAL
CHARACTERISTICS
CHAPTER 9
9.1
ABSOLUTE MAXIMUM RATINGS
The values listed below are stress ratings only. Functional operation at the maximum ratings is not recommended
or guaranteed. The device's reliability is affected if the device is operated for extended periods at maximum
ratings.
Electrostatic discharge damage may result from high static voltages or electric fields.
Symbol
Parameter
Min.
Max.
Unit
AVoo
Analog Power Supply
-0.3
7.0
V
DVoo
Digital Power Supply
-0.3
7.0
V
VIA
Analog Input Voltage
-0.3
7.0
V
VIO
Digital Input Voltage
-0.3
7.0
V
Veso
ESD Tolerance (Human Body Model per Method 3015.2 of
MIL-STD-883B)
2
KV
TOPER
Operating Temperature
0
+70
°C
TSTG
Storage Temperature
-65
+150
°C
1800
mW
POMAX
Maximum Power Dissipation at TJ = 125°C
Oak Technology
9-1
Technical Specification
011-610/011-611
9.2
DC SPECIFICATIONS
Unless otherwise noted, electrical characteristics of the OTI-61 0/OTI-611 are specified over the operation range.
Typical values for:
VDD = AVDD = +5VDC ± 5°1o
VSS = AVSS = OVDC
The table below lists the DC specifications of the OTI-61 0 and OTI-611 , except for five signals specifically used
as the AC-Link connection to AC '97 Codecs.
DC Specifications (except AC-Link Signals):
Symbol
Parameter
Min.
Voh
Output High Voltage
2.4
VOl
Output Low Voltage
Vol
Max.
Unit
Condition
Notes
V
loh
= 400 uA
0.4
V
101
= 18 mA
TxD pin
Output Low Voltage
0.4
V
101
= 4 mA
All other output pins
except PC! types
Vol
Output Low Voltage
0.4
V
101
= 2 mA
PC! Interface pins
V ih
Input High Voltage
2.0
DVdd +0.5
V
TTL
Vii
Input Low Voltage
-0.5
0.8
V
TTL
V.IS
Schmidt Input Voltage
2.4
DVdd +0.5
V
Schmidt
V.Ie
CMOS Input Voltage
3.8
DVdd +0.5
V
CMOS
III
Input Leakage Current
-10
10
uA
°u
Output Leakage Current
-10
10
uA
Icc
Operating Supply Current
245
270
mA
mA
Icc-po
Operating Supply Current
Power Down Mode
33
mA
lavdd
AVdd Current
500
uA
C,
Input Capacitance
8
pF
Co
Output Capacitance
8
pF
C,o
I/O Capacitance
8
pF
Note:
DVdd = 5V
DVdd = 5.25V
AVdd = 5V
TA = O°C to 70°C;VDD =AVDD =5V +/1 5°/o;VSS = AVSS = OV
For complete details, consult Chapter 6.
Oak Technology
9-2
Technical Specification
Electrical Characteristics
AC-Link Signal List:
OTI-610/0TI-611
Signal Name
Type
OTI-612 or AC 197
Codec Signal NameAC-Link Signal Name
Type
ARESET#
0
RESET#
I
Master HIW Reset to AC '97 Codec from OTI-610 or
OTI-611
AFS
0
SYNC
I
48-KHz fixed rate sample sync from OTI-610 or OTI-611
ASClK
I
BIT_ClK
0
12.288-MHz serial data clock (Fxl2 from AC '97 Codec)
to OTI-610 or OTI-611. Fx=24.576 MHz
ASDO
0
SDATA_OUT
I
Serial, time division multiplexed output stream to AC '97
Codec from OTI-61 0 or OTI-611
ASDI
I
SDATA_IN
0
Serial, time division multiplexed output stream from AC
'97 Codec to OTI-61 0 or OTI-611
Description
Data from the table below applies to the following OTI-61 010TI-611 Signals when used as an AC-Link
connection to the OTI-612 or an AC '97 compatible codec in an AC '97 system design.
AC-Link Signals DC Characteristics:
Symbol
Parameter
Min.
Max.
Units
VIN
Input Voltage Range
-0.30
5.3
V
Vll
low level Input Voltage
-
0.8
V
VIH
High level Input Voltage
2.0
-
V
VOH
High level Output Voltage
2.4
-
V
VOL
low level Output Voltage
-
0.55
V
-
Input leakage Current
(AC-Link inputs)
-10
10
uA
-
Output leakage Current
(Hi-Z'd AC-Link outputs)
-10
10
uA
Note:
TA = O°C to 70°C;VDD =AVDD
Oak Technology
= 5V +/1
Condition
Notes
IOl = 5.0 mA
Typ
5%;VSS =AVSS = OV
9-3
Technical Specification
011-610/011-611
9.3
AC SPECIFICATIONS
Unless otherwise noted, electrical characteristics are specified over the operation range.
Typical value forVDD = AVDD = +5VDC ± 5%, VSS = AVSS = OVDC
AC specifications for AC-Link signals when used in an AC '97 system are given in Chapter 8 and in Section 9.4.
9.3.1
RESET TIMING
Parameter
Symbol
t RESET# l
twoMV
twoMvH
Min.
RST# Low Time
Typ
Units
32
nS
5
WDM Valid Hold Time
Notes
LCLK
1
WDM Valid Time from RST# Rising Edge
RST#
Max
nS
--------\~----~f-------------------tWDM
~4
tWDMVH :
~14
~;
~DMD~5~1 ~~~~~(~~V_A_U_D~~
~DMA~~~ ~~~~~(~~V_A_U_D~~
Figure 9-1: PCI Reset and Jumper Latch Timing
Oak Technology
9-4
Technical Specification
Electrical Characteristics
9.3.2
PCI CLOCK REQUIREMENT
Min.
Parameter
Symbol
Typ
Max.
Units
\.cKP
PC! Bus Clock Period
30
nS
tPCKl
PCI Bus Clock Low Time
12
nS
\.cKH
PCI Bus Clock High Time
12
nS
Notes
LCLK
Figure 9-2: PCI Clock Timing
Oak Technology
9-5
Technical Specification
OTI-610/0TI-611
9.3.3
PCI BUS TIMING (1/0 READ OPERATION)
Symbol
Min.
Parameter
tSPCI
Input Setup Time to LCLK
7
t HPC1
Input Hold Time to LCLK
0
tpPCI
Output Propagation Delay
Time from LCLK
2
Typ
Max.
Units
Notes
nS
20
nS
11
nS
nS
o pF Load
50 pF Load
LCLK
FRAME#
~4 tSPc~~4 tHPr
:
AD[31:0]
~
hADD~ESS~
j
:4
.
~
tpPCI
_--!~_4--c~\
\ ...
:
I:.:
: tpPCI
DATA 1 )
\
_
r:~.
......_ _
~
_ _ _-:--_ _ _
~
tSPcI1 tHPCI
~:4
~:
~B~~~~~~====:=========B=E=#=~=~=]=:==)~--------~ tHPCI
i+--+
tSPCI :
+--.:
IRDY#
~~\~~~--~~--~~~~
~
tpPCI
:+---+:
TRDY#
.
:
~--------~\~
~
__
~ tpPCI
j+---+.'
~l~~----~--~----~
tpPCI
~
------------,\'--_-!--__~/
DEVSEL#~;
~
tpPCI
VALI~~--~----
PAR
Figure 9-3: PCI Bus Timing (I/O Read Operation)
Oak Technology
9-6
Technical Specification
Electrical Characteristics
9.3.4
PCI BUS TIMING (I/O WRITE OPERATION)
Parameter
Symbol
Min.
Typ
Max.
tSPCI
Input Setup Time to LCLK
7
nS
t
Input Hold Time to LCLK
0
nS
Output Propagation Delay
Time from LCLK
2
HPC1
tPPCI
11
Notes
Units
nS
nS
o pF Load
50 pF Load
LCLK
.
FRAME#
: tSPCI:
~
n\....--!---·---;.,...J/
~4 tSPc~~4 tHPr'. tsp~
AD[31:0]
~~~~1~~-D-~-A-1~:~)~'~~~~~~~~~.
~
CBE#[3:0]
~. tHPr'
.
~
:..
.
tSPCI ~ t HPC1
~:..
~:
~ . .r---+.:ri
C[3'·.:O]
X':.:
1 . . - ._
~--.)}--------------~
BE-#-[3-:0-]--1
_
_
....;..---1.
_
IRDY#
TRDY#
~ t pPC1
~
DEVSEL#;-
---------------;\'----!-----J/
Figure 9-4: PCI Bus Timing (I/O Write Operation)
Oak Technology
9-7
Technical Specification
OTI-610/0TI-611
9.3.5
PCI BUS MASTER REQUESTTIMING
Symbol
Min.
Parameter
Typ
Max.
Units
tSPC1
Input Setup Time to LCLK
7
nS
t HPC1
Input Hold Time to LCLK
0
nS
- ..
-~
Output Propagation Delay
Time from LCLK
tpPCI
Notes
2
11
nS
nS
o pF Load
50 pF Load
LCLK
:,' t pPC1
:.---.:,
,
REQ#
n,---~
_______
, tSPCI
GNT#
'
:
t PPCI:
'
'
~ ~--+------,:-------:
--~-~--,I-
i tHPCI
i
~
M
\'----+-----i-_~----+---'!r-------7---~
Figure 9-5: PCI Bus Master Request
9.3.6
PCI BUS MASTER READIWRITETIMING
Symbol
Min.
Parameter
Typ
Max.
Units
tSPCI
Input Setup Time to lCLK
7
nS
tHPC1
Input Hold Time to LCLK
0
nS
~PCI
Output Propagation Delay
Time from LCLK
2
Oak Technology
9-8
11
nS
nS
Notes
o pF Load
50 pF Load
Technical Specification
Electrical Characteristics
2
4
3
5
7
6
LCLK
1 t ppc, l
1 t pPC1
i4--+i
FRAME#
n'----:-----i------+-----+----:-1----'1-~----!
1 tppc,l
~
AD[31 :0]
i4---+!
1 t pPC1
i4--+.
i I\
i iADD~ESS
'H:
:
1 t ppc, l
~
1 t pPC1
i4--+.
:4
t SPC1
1
1 t HPC1
~:
Vi)
~ DATt 1 _
i+-+.
(READ!)
ADATA;,':'
" '2.X.
v:,:,:
DATA!::' 3 )
.)-.
-.--!
t SPC1
~~~~~~~*~~-----B-~-~-~-]·:-------~}~-~
1 t pPC1
~
IROY#
: t pPC1
~
!""---~~\'__+--__~--.;.._--~--~l--'l---:
t SPC1
;4
TROY#
: t HPC1
~~4
~;
~~--~\~~l~\~~
__~/
: t SPC1
: t HPC1
i+--+.
!+-+.
j , __- - - i
----------i-_\
OEVSEL#""':
1 t pPC1
~
AD[31:0]
~
HADD~ESS~
tp~I'
H
!
i4----+.
CBE#[3:0]
: t pPC1
::
;.
1
WR'TEDATA~l
It
pPC1
!4-+.
C[~:O] ~
t pPC1
1 t pPC1
BE#[3:0] -1
X DAT~3 }~--i
__
1~ B_E#_[3_:_0]_-_2__o__'XBE#[3:~ }~--!
:
.
1
t pPC1
i+--+.
:)
PAR
WRITE DATA 2
i
\
-3
: t pPC1
~
i
~_~~'~~
i
VALI~ ~~ VALI~
X
i
VALID!
Figure 9-6: PCI Bus Master ReadlWrite Timing
Oak Technology
9-9
Technical Specification
011-610/011-611
9.3.7
ROM MEMORY INTERFACETIMING
WDMCE1#
ROMCE:
ROMOE#
L--
BYTE:
Vcc-
WDMA(19:0)
ROMA(19:0)
WDMD[15:0)
ROMD[15:0)
~
~
1M x 16
UM23C16100M
or equivalent
OTI-610
OTI-611
Parameter
Symbol
Min.
Typ
Chip Enable Pulse Width
teEW
Max.
Units
150
nS
Notes
ROM Requirements:
Symbol
Parameter
Min.
Typ
Max.
Units
tACE
Chip Enable Access Time
70
nS
tAOE
Output Enable Access Time
70
nS
tHZ
Data Hold Time to Hi-Z
30
nS
~
WDMCE1# :
(ROMCE#)
WDMCE1# :
(ROMOE#) j
.
tCEW
\'---_ _ _ _----1/
~\
..
'------------'1
X~________V_A_L_ID__A_D_D_R_ES_S___________X~
WDMA[19:0]
:4
:+--
WDMD[15:0]
Notes
:
tACE
--------------+~:
tHZ
______
j
~
!----------~-------------__4( VALID ~TA
-------!
).l-:
Figure 9-7: External CMOS Mask ROM Interface Timing Requirements
Oak Technology
9-10
Technical Specification
Electrical Characteristics
9.3.8
SRAM MEMORY INTERFACE TIMING
WDMCE2#
WDMCE1#
WDMOE#
WDMAI19]
WDMAIl8:0]
WDMDIlS:O)
....:-r--
..
CS#
OE#
WE#
WDMAIl8:0]
WDMD[lS:0)
~
S12x16SRAM
-~ :.....-
CS#
OE#
-- WE#
WDMAIl8:0)
WDMD[lS:0)
OTI-610
OTI-611
512Kx16 SRAM
Parameter
Symbol
Min.
Typ
Chip Enable Pulse Width
tCEW
Max.
Units
150
nS
Max.
Units
Notes
SRAM Requirements (maximum):
Min.
Parameter
Symbol
Typ
tACE
Chip Enable Access Time
70
nS
tAOE
Output Enable Access Ti me
70
nS
tHZ
Data Hold Time to Hi-Z
30
nS
Notes
tCEW
WDMCE1# :
\~--------'/
WDMCE2# ~
l \~ _ _ _ ____l/
WDMCE1#~
WDMA[19:0]
WDMD[15:0]
~i-!
l\~-----JI
t-
_ _ _ _- - - - ;_ _
...IX~_____VA_L_ID_A_D_D_R_E_S_S_...;..._----JX'----.....;;
~
~:
_tAOE
~
~---------------~~------------------------------~(~'-VA-L-ID~d(iA~~---------------~
Figure 9-8: External SRAM Memory Interface Timing Requirements
Oak Technology
9-11
Technical Specification
OTI-610/0TI-611
9.4
AC-LINK TIMING CHARACTERISTICS
A breakout of the signals connecting the OTI-61 O/OTI-611 to an AC '97 Codec is shown in the table and figure
below.
Type
OTI-612 or AC 197
CodecSignai NameAC-Link Signal Name
Type
ARESET#
0
RESET#
I
Master HIW Reset to AC 197 Codec from OTI-610 or
OTI-611
AFS
0
SYNC
I
48-KHz fixed rate sample sync from OTI-610 or OTI-611
ASClK
I
BIT_ClK
0
12.288-MHz serial data clock (Fxl2 from AC 197 Codec)
to OTI-610 or OTI-611. Fx=24.S76 MHz
ASDO
0
SDATA_OUT
I
Serial, time division multiplexed output stream to AC 197
Codec from OTI-61 0 or OTI-611
ASDI
I
SDATA_IN
0
Serial, time division multiplexed output stream from AC
197 Codec to OTI-610 or OTI-611
- .... _.. -.. - ....
_....
Signal Name
Description
Note: Unless otherwise noted, Tambient = 25 0 C, AVdd = DVdd = 5VDC; AVss = DVss = OV; 50pF external load
Throughout the rest of this section on AC-Link timing, AC-Link signal names will be given along with the
equivalent OTI-61 0 and OTI-611 signal names. AC-Link signal names appearing in descriptive text will be
printed in italics and will be enclosed within parentheses.
Tables containing signal names will show both the OTI-61 O/OTI-611 and AC-Link signal names in the same way.
Example:
011-610/011-611 Signal Name
ARESET#
AC-Link Signal Name
(RESET#)
liming diagrams will be presented with the OTI-61 O/OTI-611 signal name in the illustration.
ARESET#
ASDO
ASDI
ASClK
AFS
RESET:
RESET:
SDATA OUT
SDATA IN
BIT ClK
SYNC
SDATA.OUT
SDATA.IN
BIT.ClK
SYNC
r:L
D
Fx
24. 576
AC-Link
M Hz
011-612
or
011-610
or
011-611
AC'97
CODEC
Figure 9-9: OT/·61 O/OTI-611 AC-Link Connection to an AC '97 Compatible Codec
Oak Technology
9-12
Technical Specification
Electrical Characteristics
9.4.1
AC-L1NK RESETTIMING
Cold Reset
Parameter
Symbol
Min
Typ
Max
Units
ARESET (RESETIf) Active Low Pulse Width
Trst.low
1.0
-
-
uS
ASCLK (BIT_eLK) Startup Delay from ARESET# (RESETIf) high
Trst2c1k
162.8
-
-
uS
ARESET# _ _ _{
AFS
T
rnU~
J,--T_rS_t2C_lk_.+I____
_ _ _ _rmJlJ1f
Figure 9-10: AC-Link Cold Reset Timing
Warm Reset
Parameter
Symbol
Min
Typ
Max
Units
AFS (SYNC) active High Pulse Width
Tsync_h"Igh
-
1.3
-
uS
AFS (SYNC) Inactive to ASCLK (BIT_CLK) Startup Delay
Tsync2c1k
162.8
-
-
uS
____J ~~ ~\-T_syn_c2_Clk--fo'I
T
AFS
_ _ __
ASCLK _______________________________~
Figure 9-11: AC-Link Warm Reset Timing
Oak Technology
9-13
Technical Specification
OTI-610/0TI-611
9.4.2
CLOCKS
(50pF external load)
Parameter
Symbol
Min
Typ
Max
Units
-
12.288
-
MHz
-
81.4
-
nS
-
-
750
pS
'ASClK (BIT_eLK) Frequency
ASClK (BIT_eLK) Period
TIck_persod
0
ASClK (BIT_eLK) Output jitter
ASClK (BIT_CLK) High Pulse Width'
Tclk_high
32.56
40.7
48.84
nS
ASClK (BIT_ CLK) low Pulse Width'
TclkJow
32.56
40.7
48.84
nS
-
48.0
-
KHz
-
20.8
-
uS
1.3
-
uS
19.5
-
uS
AFS (SYNC) Frequency
AFS (SYNC) Period
Tsync.J)erl00d
AFS (SYNC) High Pulse Width
Tsync_high
AFS (SYNC) Low Pulse Width
TsyncJow
Note:
lWorst case duty cycle restricted to 40/60.
ASCLK
14-----
T clkJ)eriod - - - - . .
AFS
'-----/1--"
14----- TsyncJ)eriod
Figure 9-12: AC-Link Clock Timing
Oak Technology
9-14
Technical Specification
Electrical Characteristics
9.4.3
DATA SETUP AND HOLD
(50pF external load)
Parameter
Symbol
Min
Typ
Max
Units
Setup to Falling Edge of ASCLK (BIT_CLK)
Tsetup
15.0
-
-
nS
Hold from Falling Edge of ASCLK (BIT_CLK)
Tho1d
5.0
-
-
nS
Tsetup
ASCLK
1 I--
I 1\'--_---'71
\'----
ASDI,
ASDO
AFS
If----I~-
Thold
Figure 9-13: AC-Link Data Setup and Hold Timing
Oak Technology
9-15
Technical Specification
011-610/011-611
9.4.4
SIGNAL RISE AND FALL TIMES
(SOpF external load)
Parameter
Symbol
Min
Typ
Max
Units
ASCLK (BIT_CLK) Rise Time
TriseC:;IK..
2
-
-
nS
ASCLK (BIT_CLK) Fall Time
Tfallclk
2
-
-
nS
AFS (SYNC) Rise Time
Trisesync
2
-
-
nS
AFS (SYNC) Fall Time
Tfallsync
2
-
-
nS
ASDI (SDATA_IN) Rise Time
Trisedin
2
-
-
nS
ASDI (SDATA_IN) Fall Time
Tfall din
2
-
nS
ADSO (SDATA_OUT) Rise Time
Trisedout
2
-
-
ADSO (SDATA_OUT) Tall Time
Tfall dout
2
-
-
nS
ASCLK
nS
~
:I L j 1:. Tfallclk
Triseclk
~j
AFS
Trisesync
ASDI
I: Tfall
sync
~
:I L j I: Tfalld;"
Trisedin
ASDO
:I
~
Trisedout
:I L j I: Tfalldout
Figure 9-14: AC-Link Signal Rise and Fall Timing
Oak Technology
9-16
Technical Specification
Electrical Characteristics
9.4.5
AC-LlNK LOW POWER MODETIMING
Parameter
End of Slot 2 to ASCLK (BIT_CLK), ASDI (SDATA_IN) Low
AFS
SLOT 1
Symbol
Min
Typ
Max
Units
Ts2.,.pdown
-
-
1.0
uS
SLOT 2
ASCLK
ASDO
WRITE TO 0x26
DON'T CARE
TS2.J)down
ASDI
NOTE: ASCLK NOT TO SCALE
Figure 9-15: AC-Link Low Power Mode Trming
9.4.6
ATE IN-CIRCUITTEST MODE
Parameter
Setup to Trailing Edge of ARESET# (RESET#)
Rising Edge of ARESET# (RESETIf) to Hi-Z Delay
Symbol
Min
Typ
Max
Units
Tsetup2rst
15.0
-
-
nS
Toff
-
-
25.0
nS
ARESET#
ASDO
ASDI,
ASCLK
Hi -Z
Figure 9-16: AC-Link ATE Test Mode Trming
Oak Technology
9-17
Technical Specification
OTI-610/0TI-611
9.5
AUDIO/MODEM CODEC PORT TIMING (STLC7549)
Throughout the rest of this section on STLC7549 Audio/Modem Codec timing, STLC7549 signal names will be
given along with the equivalent OTI-611 signal names. STLC7549 signal names appearing in descriptive text will
be printed in italics and will be enclosed within parentheses.
T:::thlp,
n:::tmp,
r71l4q
,i(Jn:::t1 -n:::tmp,
in thp
.-_._- rnnt:::tinin(J
-_··--·····-0 ,ion:::tl
--0- .-...
- ... -- will
... -- ,how
--.- ...hnth
- ---. thp
---- nTI-h11
- - - - - - :::tnrl
---- STI
- . --- -- --0-----.---- --.
-.-- ,:::tmp
--- .. - w:::tv
··-r
Example:
011-611 Signal Name
ARESET#
S1LC7549 Signal Name
(RESET#)
liming diagrams will be presented with the OTI-611 signal name in the illustration.
APWON#
ARESET#
ASOO
ASOI
ASCLK
AFS
AMCLK
MSOO
MSOI
MSCLK
MFS
MMCLK
28
25
63
64
20
21
22
19
24
61
60
59
58
55
~
!'i4
11
8
53
52
51
50
7
6
OTI-611
PDWN#
RESET#
..
SIN1
SOUT1
SCLK1
FSYNC1
MCLKA
SIN2
SOUT2
SCLK2
FSYNC2
MCLKM
STLC7549
Figure 9-17: Simplified Connection Diagram- OTI-611 to STLC7549
Oak Technology
9-18
Technical Specification
Electrical Characteristics
ASCLK
Tpda2 --.:
AFS
:
Tpda2~
--1/'
i+-:
:\
i+- .
:
:.
Tsckla
~:.
~
~:
Tsckha
~ Tsa2 ~ Tha2 ~
==x .
:.
ASOI
ASOO
~:.
~:
X,-----,.X'--__
Tpda3~
X
X
:.-
X---
Tckla Tckha
AMCLK
Tpda1---+i
ASCLK
!4-
______~!X~i----------.
:
Figure 9-18: OTI-611 to STLC75491iming
Oak Technology
9-19
Technical Specification
OTI-610/0TI-611
011-611 to S1LC7549Timing Chart:
Parameter
Symbol
MCLKA
STLC7549 Master Clock Input
Range - Audio Codec
AMCLK
Master Ciock - Audio Codec
MCLKM
STLC7549 Master Clock Input
Range - Modem Codec
MMCLK
Master Clock - Modem Co dec
Min.
Typ
Max.
Units
6.144
11.2896
12.288
MHz
11.2896
1.8432
2.4576
MHz
3.84
MHz
2.4576
MHz
Tpwa
Master Clock Period - Audio
1/AMCLK
-
Tpwm
Master Clock Period - Modem
1/MMCLK
-
Tpda1
ASCLK (SCLK1) Output Delay from AMCLK Rising
Edge
10
nS
Tpda2
AFS (FSYNC1) Delay Time
10
nS
Ts2
ASDI Setup Time to ASCLK (SCLK1) Fa"ing Edge
10
nS
Th2
ASDI Hold Time from ASCLK (SCLK1) Fa"ing Edge
5
nS
Tpda3
ASDO Delay from ASCLK (SCLK1) Rising Edge
Tsckw1
ASCLK (SCLK1) Period
Tsckh1
ASCLK (SCLK1) High Time
142
nS
Tsckl1
ASCLK (SCLK1) Low Time
142
nS
Tsckw1
MSCLK (SCLK2) Period
Tsckh1
MSCLK (SCLK2) High Time
851
nS
Tsckl1
MSCLK (SCLK2) Low Time
851
nS
FSA
Audio Sample Frequency
FSM
Modem Sample Frequency
Note:
15
1/[64xFSA]
1I [64xFSM]
nS
S
S
AMCLKI[4xNx64]
N=l, FSA=44.1
N=2, FSA=22.05
KHz
KHz
MMCLKI[4x64]
Hz
AMCLK and MMCLK depend upon software programming
Oak Technology
9-20
Technical Specification
Electrical Characteristics
9.6
AUDIO CODEC PORT TIMING (STLC7549AC)
Throughout the rest of this section on STLC7549AC Audio Codec timing, STLC7549AC signal names will be given
along with the equivalent OTI-61 0 signal names. STLC7549AC signal names appearing in descriptive text will be
printed in italics and will be enclosed within parentheses.
Tables containing signal names will show both the OTI-61 0 and STLC7549AC signal names in the same way.
Example:
OTI-610 Signal Name
ARESET#
STlC7549AC Signal Name
(RESET#)
Timing diagrams will be presented with the OTI-61 0 signal name in the illustration.
Note:
Consult SGS Thomson STlC7549AC data sheet for complete technical specifications and applications
information.
APWDN#
ARESET#
ASDO
ASDI
ASCLK
AFS
AMCLK
?R
63
25
64
20
21
61
60
59
58
55
22
19
24
r
PDWN#
RESET#
SIN1
soun
SCLK1
FSYNC1
MCLKA
STLC7549AC
TCFP84PKG
OTI-610
~
Figure 9-19: Simplified Connection Diagram- OTl-610 to STLC7549AC
Oak Technology
9-21
Technical Specification
OTI-610/0TI-611
Tsckwa
ASCLK
Tpda2
AFS
:
Tpda2--.1
--L/
1
~ !4- j
1.- j
:..
\
~:..
~:
Tsckla 1 Tsckha
~ TSa2l Tha2 ~
;..
ASDI
~;..
~;
J: .
ASDO
--=!=-x
X.i.:'-------*'---Tpda3~
.x
*,---14-
Tckla Tckha
AMCLK
ASCLK
Tpda1---.1
1+--
!X
----------~: ~:---------------
Figure 9-20: OT/-610 to STLC7549AC Timing
Oak Technology
9-22
Technical Specification
Electrical Characteristics
OTI-610 to STLC7549ACTiming Chart:
Symbol
Parameter
Min.
Typ
Max.
Units
6.144
11.2896
12.288
MHz
MCLKA
STLC7549AC Master Clock Input Range
AMCLK
Master Clock
11.2896
MHz
Tpwa
Master Clock Period
1/AMCLK
-
Tpda1
ASCLK (SCLK1) Output Delay from AMCLK Rising
Edge
10
nS
Tpda2
AFS (FSYNC1) Delay Time
10
nS
Tsa2
ASDI Setup Time to ASCLK (SCLK1) Falling Edge
10
nS
Tha2
ASDI Hold Time from ASCLK (SCLK1) Falling Edge
5
nS
Tpda3
ASDO Delay from ASCLK (SCLK1) Rising Edge
Tsckwa
ASCLK (SCLK1) Period
Tsckha
ASCLK (SCLKl) High Time
142
nS
Tsckla
ASCLK (SCLK1) Low Time
142
nS
FSA
Audio Sample Frequency
Note:
15
1/[64xAFS]
1/[64x(FSYNC1 )]
AMCLKI[4xNx64]
N=1, FSA=44.1
N=2, FSA=22.05
nS
S
KHz
KHz
AMCLK depends upon software programming
Oak Technology
9-23
Technical Specification
011-610/011-611
9.7
MODEM CODEC PORT TIMING (ST7546)
Throughout the rest of this section on ST7546 Modem Codec timing, ST7546 signal names wiH be given along
with the equivalent OTI-611 signal names. ST7546 signal names appearing in descriptive text will be printed in
italics and will be enclosed within parentheses.
names in the same wav.
Tables containing
signal
names will show both the OTI-611 and ST7546 sienal
'-'
"""
v
I
Example:
OTI-611 Signal Name
ST7546 Signal Name
MRESET#
(RESET#)
Timing diagrams will be presented with the OTI-611 signal name in the illustration.
Note:
Consult SGS Thomson ST7546 data sheet for complete technical specifications and applications
information.
MPWDN# I-.>L.----~_.. PWRDWN#
MRESET_
RESET#
MSDO I-.il-----..:.L.._.. DIN
MSDI
DOUT
MSCLK
SCLK
MFS
FS
MMCLK
MCLK
CODEC_MODE
HCO
r---=---1 HC1
OTI-611
ST7546
TQFP44PKG
Figure 9-21: OTJ-611 to ST7546 Simplified Connection Diagram
MSCLK
MFS
;t
~~i
__7_'________~--2-~~i-~-l--~--4--------------------6~ l+-'~
8~--.1~~9
MSDI
MSDO
-+1 ~ 11
HCO,
HC1
)~-------------------------------------------------------Figure 9-22: OTJ-611 to ST7546 Serial Interface TIming Diagram
Oak Technology
9-24
Technical Specification
Electrical Characteristics
011-611 to S17546 Timing Chart:
Symbol
N
Parameter
Min.
Units
MSCLK (SCLK) Period
300
nS
2
MSCLK (SCLK) Width Low
150
nS
3
MSClK (SCLK) Width High
150
nS
4
MSClK (SCLK) Rise Time
10
nS
5
MSClK (SCLK) Fall Time
10
nS
6
MFS (FS) Setup Ti me
20
nS
7
MFS (FS) Hold Time
20
nS
8
MDSI (DIN) Setup Time
20
nS
9
MDSI (DIN) Hold Time
0
nS
10
MSDO (DOUT) Valid Time
11
HCO, HC7 Setup Time
15
nS
20
nS
1.54
0.92
*Modem Master Clock, Derived from OTI-611
MClK (Main Clock)
For MCLK = 36.864 MHz
MMCLK
Max.
1
ST7546 Master Clock Input Range
MCLK
Typ
MHz
2.8
*MClKl32
MHz
1.152
MHz
868
nS
Tpw
Modem Master Clock Cycle
Tph
Pulse Width High
45
55
%
Tpl
Pulse Width low
45
55
%
___{
T mUow
1___
TrSt2Clk
---+--j_
MRESET#
Figure 9-23: OTI-611 to ST7546 Reset Timing
011-611 to S17546 ResetTiming Chart:
Parameter
Symbol
TrsL10w
MRESET# (RESET#) active low pulse width
Oak Technology
9-25
Min.
Typ
Max.
Units
Notes
100
-
-
nS
-
Technical Specification
OTI-610/0TI-611
9.8
TDM AUDIO/MODEM CODEC PORT TIMING (AD1843)
Throughout the rest of this section on AD1843 Modem Codec timing, AD1843 signal names will be given along
with the equivalent OTI-611 signal names. AD1843 signal names appearing in descriptive text will be printed in
italics and will be enclosed within parentheses.
T;:)hlp~ c:ont;:)inim~'
0 -si~nal
-0
--_._._-
__
00
__
._.
names
names in the same wav.
- . will show both the OTI-611 and AD1843 si2:nal
V
I
Example:
OTI-611 Signal Name
ARESET#
AD1843 Signal Name
(RESET#)
Timing diagrams will be presented with the OTI-611 signal name in the illustration.
Note:
Consult Analog Devices AD1843 data sheet for complete technical specifications and applications
information.
28
25
APWDN#
ARESET#
51
'"
80
20
ASDO
21
ASDI
22
ASCLK
19
AFS
AMCLK I ACONV1
23
PWRDWN#
RESET#
1
79
2
501
500
SCLK
SOFS
67
71
CONV1
CONV2
-
MSDO
MSDI
MSCLK - 8
MFS ~
MMCLK ,...-
OTI-611
AD1843
8O-p1l'l
PQFPpkg
Figure 9-24: OT/-611 to AD1843 Simplified Connection Diagram
Oak Technology
9-26
Technical Specification
Electrical Characteristics
~ Tsckwa --+~
ASCLK
,
,
,
,
Tpd1
AFS
--+.
~ Tafs--';
:+-:
:
~
\'-----!-------{I---~---
Th
Ts
:4
~:4
~:
X
ASDI==X
(
ASDO
Bit 15
X
Bit 14
--+. i+Bit 15
X
Bit 14
\~
Bit 0
X'---_~~
x==
-+.:+-
Bit 0
Thz
)>-:- - -
~:
Trpwl
ARESET#
'---_:::x
X
Tdv
________#--~i
,4
~:
Trpwl
\~--------#--~I
Figure 9-25: OTI-611 toAD18431iming Diagram
Oak Technology
9-27
Technical Specification
011-610/011-611
OTI-611 to AD18431iming Chart:
Min.
Typ
Max
Units
AD1843 Master Clock Output
Master Mode Only
12.288
16.384
MHz
ASCLK
Master Clock Input - Audio
12.288
16.384
MHz
MSCLK
Master Clock Input - Modem
12.288
MHz
1/ASCLK
-
Symbol
SCLK
Parameter
Tpwa
Master Clock Period
Tpd1
AFS (SOFS) Delay Time from ASCLK Rising Edge
Tafs
AFS (SOFS) Pulse Width High
15
80
Ts
ASDI Setup Time to ASCLK (SCLI<) Falling Edge
5
Th
ASDI Hold Time from ASCLK (SCLI<) Falling Edge
5
Tpda3
Tdv
Tsckwa
Trpwl
Thz
nS
nS
(SDO) Delay from ASCLK (SCLI<) Rising Edge
10
nS
ASDO Valid Delay from ASCLK (SCLK) Rising Edge
15
nS
1/[64xAFS]
1/[64x(FSYNCl )]
ASCLK (SCLK) Period
ARESET# (RESET#) and APWDN_ (PWROWN#) Low
Pulse Width
(500) Hi-Z State Delay from ASCLK (SCLK)
Oak Technology
S
100
nS
15
9-28
nS
Technical Specification
Electri cal Characteristics
9.9
J2S PORT TIMING
RIGHT
LRCLK
;
;;
~ ;~~
RIGHT
L_~
________
___________
: Tckh :: Tckl :: Twhd :: Twsu
BCLK
~h!
:~:
Tcyc
~Tdsu
HTdhd
~
x=
~~~
SDATA_ _----.JX'--_ _--JX,---LS-S---..X
MSS
Figure 9-26: OTI-611 F5 Port TIming Diagram
OTI-611 PS PortTiming Chart:
Symbol
Min.
Parameter
Typ
Max.
Units
18.4
MHz
Fbck
BCLK Frequency
Tcyc
BCLK Cycle Time
54
nS
Tckh
BCLK HIGH Time
15
nS
Tckl
BCLK LOW Time
15
nS
Tdsu
SDATA Setup Time
12
nS
Tdhd
SDATA Hold Time
2
nS
Twsu
LRCLK Setup Time
12
nS
Twhd
LRCLK Hold Time
2
nS
Oak Technology
9-29
Technical Specification
OTI-610/0TI-611
(This page intentionally left blank)
Oak Technology
9-30
Technical Specification
THERMAL SPECIFICATIONS
CHAPTER 10
The OTI-611 device operates properly when the Case Temperature (Tc) is within the specified temperature range
of O°C to 70°C.
Symbol
Parameter
Min.
Max.
Unit
Condition
25
°CJWatt
No airflow, with internal heat spreader
in the package
0
+70
°C
-65
+150
°C
TJ
Junction Temperature (at ambient
temperature = 25°C)
55.6
6004
°C
°C
DVdd = 5.0V
Po = 1220 mW
DVdd = 5.25V
Po = 1410 mW
TJ
Junction Temperature (at ambient
temperature = 70°C)
107
116
°C
°C
DVdd
DVdd
2200
mW
aJA
Package Junction-to-Ambient
Thermal Resistance
TOPER
Operating Temperature, Case (Te)
TSTG
Storage Temperature
POMAX
Note:
Absolute Maximum Power
Dissipation
TJ =TA + aj/po
Oak Technology specification for TJ
Oak Technology
DVdd
= 5.25V maximum
= 5.0V
= 5.25V
TJ = 125°C
= 12SoC maximum
10-1
Technical Specification
011-610/011-611
(This page intentionally left blank)
Oak Technology
10-2
Technical Specification
MECHANICAL
SPECIFICATIONS
CHAPTER 11
The OTI-61 0 and OTI-611 are packaged in the 160-pin PQFP plastic package.
--r------l___+_
Hd
nnr'nnnnnnnnMnII"'lMnnnr.,n~ne'DOOnDnnDOODDnnnnDnn"
'I
0
011-610
011-611
c
e
Oak Technology
b
11-1
Technical Specification
OTI-610/0TI-611
Inches
Millimeter
Symbol
Min.
Nom.
Max.
Min.
Nom.
Max.
A1
0.05
0.25
0.50
0.002
0.010
0.020
A2
3.17
3.32
3.47
0.125
0.131
0.137
b
0.20
0.30
0.40
0.008
0.012
0.016
c
0.10
0.15
0.20
0.004
0.006
0.008
D
27.90
28.00
28.10
1.098
1.102
1.106
E
27.90
28.00
28.10
1.098
1.102
1.106
e
-
0.65
-
-
0.026
-
Hd
30.95
31.20
31.45
1.218
1.228
1.238
He
30.95
31.20
31.45
1.218
1.228
1.238
L
0.65
0.80
0.95
0.025
0.031
0.037
L1
-
1.60
-
-
0.063
-
Y
-
-
0.08
-
-
0.003
e
0
-
10
0
-
10
Oak Technology
11-2
Technical Specification
OTI-611 HSP FAX/DATA
APPENDIX A
A.l
MODEM
HSP FAX/MODEM
The Host Signal Processing (HSP) based fax/modem software is supplied with and only works with the OTI-611
TeiAudia3D audio/communications accelerator.
The HSP-based fax/modem software supplied with the OTI-611 is fully compliant to International
Telecommunications Union (lTU)V.34 andV.34+ (sometimes known asV.34bis) specifications and well as ITU
Group 3 facsimile standards. It also conforms to the industry-standard AT Command Set for fax/data modems.
The HSP fax/modem currently supportsV.34N.34+, but can be upgraded to support 56 Kbps at the time the ITU
publishes its final 56-Kbps standard specification.
A.l.l
SOFTWARE ENVIRONMENT
All modem data pump and controller functions are performed in software, utilizing the power of the computer
central processing unit (CPU) and system memory (RAM). The HSPY.34 fax/modem is supplied as executable
code, and is part of the OTI-611 installation software.
The executable code is designed to work with the hardware support structures within the OTI-611 to interface
between the HSP software and external hardware modem codec and Data Acquisition Answer (DAA) structure
which connects to the public switched telephone network (PSTN), thus forming a completely functional data and
fax modem.
The HSP V.34 executable code is intended to operate in a Windows 95 software environment and functions as a
legitimate Windows 95 application when used with the OTI-611 in an audio and communications design.
A.l.2
HARDWARE ENVIRONMENT
The HSPV.34 fax/modem code is available for Pentium class and Pentium MMX class based computer systems.
Minimum system recommendations in the OTI-611 environment are:
•
Operating System - Windows 95 and Windows NT 4.0
•
CPU - 1 66-MHz Pentium class or Pentium MMX class
•
Total System RAM - 32MB
•
Free Hard Disk Space - 2MB
Oak Technology
A-l
Technical Specification
011-610/011-611
A.2
STANDARD FEATURES
•
V.34 (28.8 Kbps)/\l.34+ (33.6 Kbps) data modem, capable for upgrading to 56 Kbps
•
Group 3 fax modem to 14,400 bps
•
Industry-standard AT Commands
•
EIA Class 1 Fax Commands
•
VA2 LAPM & MNP 2-4 Error Correction
•
\l.42bis & MNP 5 Data Compression
•
Tone or pulse dial support
A.3. TECHNICAL SPECIFICATIONS
Data Standards:
ITU-T \1.21
ITU-T \1.22
ITU-T \l.22bis
ITU-T \1.23
ITU-T \1.32
ITU-T \l.32bis
ITU-T \1.34
0-300 bps
1,200 bps
2,400 bps
1,200175 bps
9,600 bps
14,400 bps
28,800 bps
33,600 bps
0-300 bps
1,200 bps
ITU-T V.34+
Bell 103
Bell 212A
Facsimile Standards:
ITU-T \1.21
ITU-T \1.17
ITU-T \1.27 ter
ITU-T \1.29
300 bps Channel 1
14,400 bps
4,800 bps
9,600 bps
Asynchronous Data:
Start Bits
1
1
1
1
Data
Bit~
7
7
8
8
Pari~ Bits
odd or even
mark or space
none
none
Stop Bits
1 or 2
1 or 2
2
1 or 2
Error Correction:
ITU-T \1.42 LAPM and MNP 2-4
Data Compression:
ITU-T VA2bis and MNP 5
Oak Technology
A-2
Technical Specification
011-611 HSP Fax/Data Modem
Communications:
Receive Sensitivity:
Transmit Level:
-43 dBm
-10 dBm (± 1 dBm)
Adj. if allowed by PIT
Pulse: Mark
33 or 39 mSec
67 or 61 mSec (decadic)
90 mSec DTMF
90 mSec DTMF
Dialing:
Tone:
A.4
Space
Duration
Spacing
AT COMMAND SET
The HSPV.34 fax/modem supplied with the OTI-611 responds to the AT Commands listed in the table below.
Parameters in bold type are the default values.
Command
Function
AT
Attention - this precedes all commands except N
N
Execute previous command - does not require a
A
Causes the modem to go off hook. If a call is coming in, the modem will try to answer it. The procedure
for answering a call is a short silence and then an answer tone. Sending a character to the modem during
this procedure will abort the answer procedure. The amount of time the modem will wait for a carrier is
programmable by modifying the 57 register.
BO
B1
B2
D
Dmn
L
W
,
,
@
!
5=(0-9)
1\
EO
E1
Select CCITT V.22 (1200 bps)
Select Bell 212A (1200 bps)
Select CCiTT V23
Originate mode will transmit data at 75 bps and receive data at 1200 bps. Answer mode will transmit
data at 1200 bps and receive data at 75 bps. The command NO (Disable Auto Mode) must be selected.
D alone will take the modem off-hook and wait for a dial tone (see X command for exceptions).
length of time to wait for a dial tone before dialing is programmable in register 56.
The
ATDmn will dial a phone number where m is a modifer: L, W, " ;, @, !, or S. It will dial the telephone
number n.
Dial last number.
Wait for dial tone. If you have selected XO or Xl (disable dial tone detection), then you can use this
modifier to override that setting.
Pause during dial. The amount of time to pause is determined in register 58.
Return to command mode after dialing. It doesn't wait for carrier or hang up.
Wait for 5 seconds of silence. This is used to access systems that do not provide a dial tone.
Hook flash. Causes the modem to go on-hook for 0.5 sec,onds. This is used in PBX systems and for voice
features like call waiting.
Dials a stored number. Up to ten numbers can be stored, and the addresses are from 0 to 9. To store a
number into one of these addresses, use the &Z command.
Turns on 1300-Hz calling tone.
Commands issued to the modem are not echoed to the local terminal. This only matters in the command
mode. It does not affect the modem's ability to send response codes.
Commands are echoed to the local terminal.
Oak Technology
A-3
Technical Specification
OTI-610/0TI-611
AT COMMAND SET (Cont'd)
Command
Function
HO
Hl
Force modem on-hook (hang-up)
Force modem off-hook (to answer or dial)
iO
11
12
13
14
Reiurn
Return
Report
Report
Report
numeric product code
hardware variation code
internal code
software revision number
product feature listing
LO
Speaker volume zero
L1
Speaker volume low
L2
L3
Speaker volume low
Speaker volume low (hardware currently limits volume adjustment to on/off)
MO
Speaker always off
M1
Speaker on until carrier detected
M2
M3
Speaker always on
Speaker on during answering only
NO
Disable auto-mode. This forces the modem to connect at the speed specified in register S37.
N1
Enable auto-mode. The modem will answer at the highest available line speed and ignore any ATBn
command.
00
Return to data mode. If you have entered the command mode using the time-independent escape
sequence, this will put you back in data mode without going on-hook.
Retrain the modem. If the line condition has changed since the original connection, retraining the modem
will cause it to reconnect at the most efficient speed for the current line condition.
01
P
QO
Ql
Sn
Sn=m
T
Pulse dialing allows the modem to work on telephone networks where tone is not supported.
Enable response to OTE.
Disable response to DTE. The modem does not respond to the terminal. Issuing a command will not
produce a response (unless the command is something like ATZ, which will restore this setting to default.)
Set default S-register. Any subsequent = or ? commands will modify the default S register.
Set register n to value m
Tone dialing
VO
Result codes will be sent in numeric form. (See the result code table)
V1
Result codes will be sent in word form. (See the result code table)
WO
Report DTE speed only. After connection, there will be no message about what Error .Correction or Data
Compression protocol is in use.
Wl
W2
Report DCE speed, Error Correction/Data Compression protocol, and DTE speed.
Report DCE speed only.
XO
Xl
X2
X3
Send OK, CONNECT, RING, NO CARRIER, ERROR, and NO ANSWER. Busy and Dial Tone Detection
are disabled.
Send XO messages and CONNECT speed.
Send Xl message and NO DIAL TONE.
Send X2 messages except NO DIAL TONE, BUSY, and RING BACK
X4
Send all responses
Oak Technology
A-4
Technical Specification
011-611 HSP Fax/Data Modem
AT COMMAND SET (Cont'd)
Command
Function
YO
Yl
Disable long space disconnect
Enable long space disonnect; with error correction, hang up after sending 1.6-second long space; without
error correction, hang up after 4-second long space.
ZO
Zl
Reset modem to profi Ie 0
Reset modem to profile 1
=n
Sets the value of the default S register
?
Reports the value stored in the default S register
&CO
&Cl
Force DCD on
OeD follows remote carrier
&00
&01
&02
&03
DTR
DTR
DTR
DTR
&F
is assumed on
drop causes modem back to command mode without disconnecting
drop causes modem to hang up
drop causes modem to be initialized; &Y determines which profile is loaded.
Load factory profile
&GO
&Gl
&G2
Disable guard tone
Enable SSO-Hz guard tone
Enable 1800-Hz guard tone on answering modem
&KO
&10
&K4
&KS
&K6
Disable flow control
Enable RTS/CTS flow control
Enable XONIXOFF flow control
Enable transparent software flow control
Enable both RTS/CTS and XONIXOFF flow control
&PO
&Pl
&P2
&P3
Selects
Selects
Selects
Selects
&SO
&Sl
Force DSR on
DSR on at the start of handshaking and off after carrier loss
&TO
&Tl
Terminate test
Start ALB test
&UO
&Ul
Enable trellis coding
Disable trellis coding
&VO
&Vl
&V2
Display active profile
Display stored profiles
Display stored telephone numbers
&WO
&Wl
Save active profile to profile 0
Save active profile to profile 1
&YO
Use profile 0 on power up
Use profile 1 on power up
&Yl
Oak Technology
39%-61 % make/break ratio at 10 pulses per second
33%-67% makelbreak ratio at 10 pulses per second
39%-61% makelbreak ratio at 20 pulses per second
33%-67% makelbreak ratio at 20 pulses per second
A-S
Technical Specification
OTI-610/0TI-611
AT COMMAND SET (Cont'd)
Command
&Zn=m
Function
Save telephone number (up to 36 digits) into memory location n (0-9)
%C1
%C2
Percent Commands
Disabie data compression
Enable MNP5 compression
Enable V.42bis compression
%C3
Enable both V.42bis and MNPS
%EO
%E1
Disable auto-retain
Enable auto-retain
%
vioCO
%E2
Enable auto-retrain and fallback
%E3
Enable autO-retrain and fast hang up
%NO
%N1
%N2
%N3
%N4
%N5
%N6
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
CPU
CPU
CPU
CPU
CPU
CPU
CPU
loading
loading
loading
loading
loading
loading
loading
disabled
not to exceed
not to exceed
not to exceed
not to exceed
not to exceed
not to exceed
10%
20%
30%
40%
50%
60%
%N7
Dynamic CPU loading not to exceed 70%
%N8
%N9
Dynamic CPU loading not to exceed 80%
Dynamic CPU loading not to exceed 90%
%Q
Report line signal quality
\AO
Backslash Commands
64-character max. MNP block size
\A1
128-character max. MNP block size
\A2
\A3
192-character max. MNP block size
256-character max. MNP block size
\Bn
In non-error correction mode, transmit break in lOOms units (1-9 with default 3)
\GO
Disable XONIXOFF flow control (modem to modem)
\G1
Enable XONIXOFF flow control (modem to modem)
\Kn
Define break type
\
\LO
Use stream mode for MNP
\L1
Use interactive block mode for MNP
\NO
\N1
\N2
Normal mode; speed control without error correction
Plain mode; no speed control and no error correction
Reliable mode
\N3
Auto-reliable mode
\N4
\N5
LAPM error correction only
MNP error correction only
*QO
Send the IICONNECT xxxxll result codes to the OlE when an invalid TIES escape sequence is detected
after the IIOK'I response has already been sent
*Q1
Does NOT send the "CONNECT XXXXII result codes to the DTE when an invalid TIES escape sequence is
detected after the 1I0K" response has already been sent.
Oak Technology
A-6
Technical Specification
OTI-611 HSP Fax/Data Modem
A.5
AT/Kn COMMAND SET
\Kn
Local OlE send break during
normal or reliable mode
Local modem sends break during
plain mode
Remote modem sends break
during normal mode
\KO
Enter command state; no break or
remote
Break to remote; and enter
command state
Empty data buffers; and send
break to DTE
\K1
Empty data buffers; break to remote
Same as\KO
Same as\KO
\K2
Same as\KO
Send break to remote
Immediately send break to DTE
\K3
Immediately send break to remote
Same as\KO
Same as\K2
\K4
Same as\KO
Same as\K2
Send break to DTE with buffered
RXD data
\KS
Send break to remote with TXD data
Same as\K2
Same as\K4
A.6
RESULTS CODES
Long Form
Short
Form
OK
0
Modem successfully executed an AT command
CONNECT
1
A connection established
RING
2
Modem detected an incoming call
NO CARRIER
3
Modem lost or could not detect a remote carrier signal within the register S7
time
ERROR
4
Modem detected an error in an AT command
CONNECT 1200
5
Connection at 1200 bps
NO DIALTONE
6
Modem did not detect a dial tone within 5 seconds after off-hook
BUSY
7
Modem detected a busy tone
NO ANSWER
8
Modem did not detect 5 seconds of silence when using the
the dial command
CONNECT 0600
9
Connection at 600 bps
CONNECT 2400
10
Connection at 2400 bps
CONNECT 4800
11
Connection at 4800 bps
CONNECT 9600
12
Connection at 9600 bps
CONNECT 7200
13
Connection at 7200 bps
CONNECT 12000
14
Connection at 12000 bps
CONNECT 14400
15
Connection at 14400 bps
Oak Technology
Description
A-7
@
dial modifier in
Technical Specification
OTI-610/0TI-611
RESULTS CODES (Cont'd)
long Form
Short
Form
CONNECT 19200
16
Connection to 19200 bps
CONNECT 38400
17
Connection to 38400 bps
CONNECT 57600
18
Connection to 57600 bps
CONNECT 115200
19
Connection to 115200 bps
CONNECT 28800
20
Connection to 28800 bps
CONNECT 300
21
Connection to 300 bps
CONNECT 1200TXI75RX
22
Connection to transmit 1200/receive 75 bps
CONNECT 75TXl1200RX
23
Connection to transmit 75/receive 1200 bps
CONNECT 110
24
Connection to 110 bps
RING BACK
25
Ring Back signal detected
+FCERROR
+F4
Error occurred in Class 1 fax operation
FAX
33
Fax modem connection established
DATA
35
Data modem connection established
CARRIER 300
40
Carrier rate or 300 bps
CARRIER 1200175
44
Carrier rate of transmit 1200/receive 75 bps
CARRI ER 75/1200
45
Carrier rate of transmit 75/receive 1200 bps
CARRIER 1200
46
Carrier rate of 1200 bps
CARRIER 2400
47
Carrier rate of 2400 bps
CARRIER 4800
48
Carrier rate of 4800 bps
CARRIER 7200
49
Carrier rate of 7200 bps
CARRIER 9600
50
Carrier rate of 9600 bps
CARRIER 12000
51
Carrier rate of 12000 bps
CARRIER 14400
52
Carrier rate of 14400 bps
CARRIER 16800
53
Carrier rate of 16800 bps
CARRIER 19200
54
Carrier rate of 19200 bps
CARRIER 21600
55
Carrier rate of 21 600 bps
CARRIER 24000
56
Carrier rate of 24000 bps
CARRIER 26400
57
Carrier rate of 26400 bps
COMPRESSION: CLASS 5
58
MNP Class 5 data compression connection established
Oak Technology
Description
A-8
Technical Specification
OTI-611 HSP Fax/Data Modem
RESULTS CODES (Cont'd)
Long Form
Short
Form
CONNECT 16800
59
Connection at 16800 bps
CONNECT 21600
61
Connection at 21600 bps
CONNECT 24000
62
Connection at 24000 bps
CONNECT 26400
63
Connection at 26400 bps
COMPRESSION: CLASS 5
66
MNP Class 5 data compression connection established
COMPRESSION: V.42bis
67
V.42bis data compression connection established
COMPRESSION: NONE
69
Connection established without data compression
PROTOCOL: NONE
76
Connection established without error correction
PROTOCOL: LAPM
77
V.42/LAPM error correction connection established
PROTOCOL: ALT
80
MNP 3-4 error correction connection established
CARRIER 31200
90
Carrier rate of 31200 bps
CARRIER 33600
91
Carrier rate of 33600 bps
CONNECT 31200
95
Connection at 31200 bps
CONNECT 33600
96
Connection at 33600 bps
A.7
S REGISTERS
Register
0
Description
Function
Rings to auto-answer
Set the number of rings required before the modem answers. 0 setting disables auto-answer.
Range: 0 - 255 rings
Default: 0 (auto-answer disabled)
1
Ring counter
Count the number of rings before the modem answers.
Range 0 -255 rings
Default: 0
2
Escape character
Define the character used for the three-characer escape code sequence. 0 setting disables the escape code
character.
Range 0 -127
Default: 43 (+)
3
Carriage return character
Define the character for carriage return
Range 0 - 127
Default: 13 (carriage return)
Oak Technology
A-9
Technical Specification
OTI-610/0TI-611
S REGISTERS (Cont'd)
Register
4
Function
Line feed character
Define the character for line feed.
Range 0 -127
Default: 10 (line feed)
5
Backspace character
Define the character for backspace.
Range 0 -127
Default: 8 (backspace)
6
Wait before dialing
Set the length of time to pause after off hook before dial.
Range 2 - 255 seconds
Default: 2 seconds
7
Wait for carrier after dial
Set the length of time that the modem waits for a carrier from the remote modem before hanging up.
Range 1- 255 seconds.
Default: 50 seconds
8
Pause time for dial delay
Set the length of time to pause for the pause dial modifier
Range 0 - 255 seconds
",n.
Default: 2 seconds
9
Carrier detect response time
Define the length of time a signal is detected and qualified as a carrier.
Range: 1 - 255 tenths of a second
Default: Default 6 (0.6 second)
10
Lost carrier hang up delay
Set the length of time the modem waits before hanging up for a carrier loss.
Range: 1 - 255 tenths of a second
Default: 14 (6 seconds)
11
DTMF speed control
Set the length of tone and the time between tones for the tone dialing.
Range: 50 - 255 milliseconds
Default: 95 milliseconds
12
Escape Prompt Delay (EPD) timer
Set the time from detection of the last character of the three character escape sequence until the "0K" is
returned to the DTE
Range: 0 -255 fiftieths of a second
Default: 50 (1 second)
13
Reserved
14
Reserved
15
Reserved
16
Reserved
17
Reserved
Oak Technology
A-10
Technical Specification
011-611 HSP Fax/Data Modem
S REGISTERS (Cont'd)
Register
18
Function
Test timer
Set the length of loopback test.
Range: 0 - 255 seconds
Default: 0 (disable timer)
19
Reserved
20
Reserved
21
Reserved
22
Reserved
23
Reserved
24
Reserved
25
Delay to DTR
Set the length of time the modem ignores DTRbefore hanging up.
Range: 0 - 255 hundredths of a second
Default: 5 (0.05 second)
26
Reserved
27
Reserved
28
Reserved
30
Disconnect inactivity timer
Set the length of time allowed for inactivity before the connection is hung up.
Range: 0 - 255 in 10 seconds
Default: 0 (disabled)
32
XON character
Set the value of XON character.
Range: 0 - 255
Default: 17
33
XOFF character
Set the value of XOFF character.
Range: 0 - 255
Default: 19
34
V.34 data rate (bit-rate)
Set the maximum bit rate for V.34
Range: 0 - 8 (2400 baud)
1-10 (3000 baud)
1-11 (3200 baud)
1-13 (3429 baud)
bit rate = «534)+1) * 2400 bps
Default: 13 (33600 bps)
Oak Technology
A-l1
Technical Specification
OTI-610/0TI-611
S REGISTERS (Cont'd)
Register
35
Function
V.34 symbol rate (haud-rate)
Set the maximum baud rate for V.34
Range: 0 - 5
0- 2400 baud
1 - 2743 baud (NtA)
2 - 2800 baud (N/A)
3 - 3000 baud
4 - 3200 baud
5 - 3429 baud (N/A until V.34bis)
Default: 0 (2400 baud)
36
37
Reserved
Line connection speed
o - Attempt to connect at the highest speed
3 - Attempt to connect at 300 bps
4 - Attempt to connect at 1200 bps
6 - Attempt to connect at 2400 bps '
7 - Attempt to connect at 4800 bps
8 - Attempt to connect at 7200 bps
9 - Attempt to connect at 9600 bps
10 - Attempt to connect at 12000 bps
11 - Attempt to connect at 14400 bps
12 - Attempt to connect at V.34
Default: 0
38
Delay before forced hang up
Set the delay to hang up after the disconnecting command is received.
Range: 0 - 255 seconds
Default: 20 seconds
39
Reserved
40
Reserved
41
Reserved
42
Reserved
43
Reserved
44
Reserved
45
Reserved
46
Reserved
47
Reserved
48
Reserved
82
Reserved
Oak Technology
A-12
Technical Specification
011-611 HSP Fax/Data Modem
S REGISTERS (Cont'd)
Register
Function
86
Call failure reason code
o - Normal disconnect; no error
4 - Loss of carrier
5 - V.42 negotiation failed to detect an error correction modem at remote end
6 - No response to complete negotation
9 - No common protocol
12 - Remote initiated a normal disconnect
13 - Remote modem did not respond after 10 message retransmissions
14 - Protocol violation
15 - Compression failure
20 - Hang up by inactivity time out
91
Transmit level
Set the transmit level in -dBm.
Range: 0 - 15 (-dBm)
Default: 11 (-11 dBm)
A.8
FAX CLASS 1 COMMAND SET
Fax Class 1 Command Set:
Command
+FCLASS=O
+ FCLASS=1
+FAE?
Function
Select data mode
Select facsimile Class 1 mode
Report active adaptive answer setting: 0 for disabled; 1 for enabled
+FAE=?
Report adaptive answer capability
+FAE=O
+FAE=1
Disable adaptive answer
Enable adaptive answer
+FCLASS=?
Report service classes supported
+FTS=n
Stop transmission and pause, 0-255 in 10 ms
+FRS=n
Wait for silence, 0-255 in 10 ms
+FTM=?
Report Class 1 transmit capabilities
+FRM=?
Report Class 1 receive capabilities
+FTH=n
Transmit data with carrier n, n=3, 24, 48, 72, 73, 74, 96, 97, 98, 121, 122, 145, 146
+FRH=n
Receive data with carrier n, n=3, 24, 48, 72, 73,74,96,97, 98,121, 122, 145, 146
Oak Technology
A-13
Technical Specification
OTI-610/0TI-611
Oak Class 8 (Voice Mode) AT Commands Summary:
Command
Function
ATA
Answering in voice mail
ATD
Dial command in voice mode
ATH
Hang up in voice mode
ATZ
Reset from voice mode
AT#BDR
Select baud rate (turn off autobaud)
AT#C1D
Enable Caller ID detection and select reporting format
AT#CLS
Select data, fax, or voice
AT#MDL?
Identify model
AT#MFR?
Identify manufacturer
AT#TL
Transmit level control
AT#REV?
Identify revision level
AT#RG
Record gain control
AT#SPK
Change the setting of speakerphone
AT#VBS
Bits per sample (ADPCM)
AT#VBT
Beep tone timer
AT#VLS
Voice line select (ADPCM)
AT#VRA
Ringback goes away timer (originate)
AT#VRX
Voice Receive Mode (ADPCM)
AT#VSD
Silence deletion tuner (voice receive, ADPCM)
AT#VSP
Silence detection period (voice receive, ADPCM)
AT#VSS
Silence sensitivity tuner (voice receive)
AT#VTX
Voice Transmit Mode (ADPCM)
AT#VBQ?
Query buffer size
AT#VCI?
Identify compression method (ADPCM)
AT#VRN
Ringback never came timer (originate)
AT#VSK
Buffer skid setting
AT#VSR
Sampling rate selection (ADPCM)
AT#VTD
DTMF/tone reporting capability
AT#VTS
Play tone string (online voice command)
Oak Technology
A-14
Technical Specification
011-611 HSP Fax/Data Modem
A.9
CALL PROGRESS
The table below shows Call Progress codes sent to the Data Terminal Equipment (DTE).
Code Sent to DTE
O to 9,
*, #,
A to D
Meaning
DTMF
Digits 0 through 9, *, #, or A through D detected by the modem.
a
Answer Tone (CClm
Send to the DTE when the V.25/T.30 2100-Hz Answer Tone (Data or Fax) is detected. If the
DTE fails to react to the code, and the modem continues to detect Answer tone, the code is
repeated as often as once every 0.5 seconds.
b
Busy
Send to DTE when the busy cadence is detected. The modem sends the busy b code
every 4 seconds if busy continues to be detected and the DTE does not react. This allows the
DTE the flexibility of ignoring what could be a false busy detection.
c
Calling Tone
Send when the T.30 11 OO-Hz Calling Tone (Fax Modem) is detected. The modem assumes
the calling tone is valid and sends this code only after 4 seconds of proper cadence has been
detected. If the DTE does not react to this code, the code is repeated as often as once every
4 seconds.
d
Dial Tone
Sent in Voice Receive Mode when dial tone is detected after any remaining data in the voice
receive buffer. The modem sends this code every 3 seconds if dial tone continues to be
detected and the DTE does not react. This allows the DTE the flexibility of ignoring what
could be a false dial tone detection.
e
European Data Modem Calling Tone
Send when the V.25 1300-Hz Calling Tone (Data Modem) is detected. The modem assumes
that the calling tone is valid, and sends this code only after 4 seconds or proper cadence has
been detected. If the DTE does not react to the code and the modem continues, the code is
sent again as often as once every 4 seconds.
f
Bell Answer Tone
Sent when Bell 2225-Hz Answer Tone (Data) is detected. If the OTE fails to react to the code
and the modem continues to detect Answer tone, the code is repeated as often as every 0.5
seconds.
h
Hung Up Handset
Sent immediately when the modem detects that the local handset has hung up.
q
Quiet
Sent in Voice Receive Mode after any remaining data in the receive voice buffer when the
silence detection timer (#VSP) expires and the voice data has been passed to the DTE.
s
Silence
Sent in Voice Receive Mode after the silence detection timer (#VSP) expires and if valid voice
has not been detected (#VSS).
t
Handset Off-Hook
Sent one time when the local handset transition goes off-hook.
Oak Technology
End of Stream
This code is sent to denote the end of a voice data stream.
A-15
Technical Specification
OTI-610/0TI-611
The table below shows Call Progress codes sent to the modem.
Code Sent to Modem
Meaning
Terminate
Sent during Voice Transmit Mode to indicate that the DTE has finished transmitting a voice
message. The Modem complete transmission of any remaining data in the voice transmit
buffer before responding with the VCON message and entering Online Voice Command Mode.
Cancel
Sent during Voice Transmit Mode to indicate that the DTE has finished transmitting a voice
message and wants the modem to discard any remaining data in the voice transmit buffer.
The modem immediately purges its buffer, and then responds with the VCON message
entering Online Voice Command Mode.
Pause
p
Send during Voice Transmit Mode to force the modem to suspend sending voice data to the
selected output device. Any data currently in the voice transmit buffer is saved until either a
resume «DLE>r) or cancel «DLE> is received during the paused state, the modem processes it normally, and also
automatically resumes transmission of the data left in the buffer (appended with r
Sent during Voice Transmit Mode to force the modem to resume sending voice data to the
selected output device. Any data currently in the voice transmit buffer is now played.
A.10 AT VOICE COMMAND DESCRIPTIONS
ATA - Answering in Voice
This command works similarly to the way it works in Data and Fax Modes.
Result Code:
VCON
ATD - Dial Command in Voice
This command will perform the dial action in Voice Mode.
Result Codes:
VCON - Issued in Voice Mode when the modem determines that the remote modem or handset has gone
off-hook.
NO ANSWER - Issues in Voice Mode when the modem determines that the remote has not picked up the
line before the S7 timer expires.
ATH - Hang Up in Voice
This command works the same as in Data and Fax modes by hanging up the phone line.
1 . This command forces the #CLS=O, but does not destroy any of the voice parameter settings such as #VBS,
#VSp, etc.
2. The #BDR setting is forced back to O.
ATZ - Reset from Voice Mode
This command works the same as in Data and Fax modes. In addition, it will also reset all voice related parameters to default states, force the #BDR=O condition, and force the telephone line to be selected with the handset
on-hook.
Oak Technology
A-16
Technical Specification
011-611 HSP Fax/Data Modem
#BOR - Select Baud Rate (Turn Off Autobaud)
This command selects a specific DTE/modem baud rate.
Parameters: n = 0 - 48 (Baud Rate = n * 2400 bps)
Default: 0
Result Codes:
OK
ERROR
if n is between
Otherwise
°and 48
Command options:
#BDR?
#BDR=?
#BDR=O
#BDR=n
Return the current setting
Return a message indicating the speeds that are supported
Enable autobaud detection on the DTE interface
Select the baud rate
#CIO - Enable Caller ID Detection and Select Reporting Format
This command enables or disables Caller ID recognition and reporting in any mode.
Parameters: n = 0, 1, or 2
Default: 0
Result Codes:
OK
ERROR
n = 0, 1, or 2
Otherwise
Command Options:
#CID?
#CID=?
#CID=O
#CID=l
#CID=2
Return the current setting (0, 1, or 2)
Return the message,
"0-2"
Disables Caller ID
Enable formatted Caller ID reporting of SDM (single data message) and MDM (multiple
data message) packets.
Enable unformatted Caller ID reporting
#CLS - Select Data, Fax, or Voice
This command selects Data, Fax, orVoice Mode
Parameters: n=O, 1, 2, or 8
°
Default:
Result Codes:
OK
ERROR
if n = 0, 1, 2, or 8
Otherwise
Command options:
#CLS?
#CLS=?
#CLS=O
#CLS=l
#CLS=2
#CLS=8
Return the current setting (0, 1, 2, or 8)
Return the message, "0, 1, 2, 8"
Select Data Mode
Select Class 1 Fax Mode
Select Class 2 Fax Mode
Select Voice Mode
#MOL - Identify Model
This command identifies the model number of the modem.
Command option:
#MDL?
"OAK288DFV"
#MFR? - Identify Manufacturer
This command identifies the modem manufacturer.
Command option:
#MFR?
Oak Technology
"Oak Technology"
A-17
Technical Specification
OTI-610/0TI-611
#REVl - Request Revision Level
This command requests the revision number of Oak driver.
#REV?
"Oak 2.00"
#RG - Record Gain Control
This command sets the record gain.
Parameters: n = 0000 - 7FFF
Default: 7FFF
Result Codes:
OK
if n = 0000 - 7FFF
ERROR
Otherwise
Command options:
#RG?
Return the current setting
Return the message, "0000-7FFF"
#RG=?
#RG=n
Set the record gain to n
#SPK - Change the setting of Speakerphone
This command set the parameters for the speakerphone.
Parameters: #SPK=, ,
microphone mute
1 - microphone on (default)
2 - Room Monitor mode (mic on max. AGC, speaker off)
Speaker Output Level
Range: to 15 (speaker attenuation in 2 dB steps)
Default: 5 (10 dB attenuation)
Speaker mute is achieved by a value of 16
0 - a dB
1 - 6 dB gain (default)
2 - 9.5 dB gain
3-12dBgain
Command options:
It is not necessary to enter all three parameters,
#SPK=,,
#SPK=,,
a-
a
#Tl- Transmit Level Control
This command sets the transmit level.
Parameters: n = 0000 - 7FFF
Default: 3FFF
Resu It Codes:
OK
if n = 0000 - 7FFF
ERROR
Otherwise
Command options:
#TL?
Return the current setting
Return the message, "0000-7FFF"
#TL=?
Set the record gain to n
#TL=n
#VBQl - Query Buffer Size
This command queries the modem's voice transmit and voice receive buffers size.
Parameters: None
Command option:
#VBQ?
Oak Technology
Return the size of buffers.
A-18
Technical Specification
011-611 HSP Fax/Data Modem
#VBS - Bits Per Sample (Compression Factor)
This command selects the degree of ADPCM voice compression to be used.
Parameters: n = 4 (Only 4 bits per sample compression ratio is supported)
Default: 4
Result Codes:
OK
ifn = 4
ERROR
Otherwise
Command options:
Return the current setting
#VBS?
Return "4"
#VBS=?
Selects 4 bits per samples
#VBS=4
#VBT - Beep Tone Timer
This command sets the duration for DTMF tone generation.
Parameters: n = 0 - 40 (duration = n 110 seconds)
Default: 10
Result Codes:
OK
if n = 0 - 40
ERROR
Otherwise
Command options:
Return the current setting
#VBT?
Returns the message, "0-40"
#VBT=?
Disables the tone generation capability
#VBT=O
Sets tone duration
#VBT=n
#vcn - Identify Compression Method
This command identjfjes the compression method used by the modem.
Parameter: None
Command option:
#VCI?
Returns the message, "0ak;ADPCM;32"
#VLS - Voice Device Selection
This command selects which devices is routed through the modem.
Parameter: n = 0, 1, 2, 3, 4, or 6
Default: 0
Result Codes:
if n = 0, 1, 2, 3, 4, or 6
OK
Otherwise
ERROR
Command options:
Return current setting
#VLS?
Return the device types supported by the modem
#VLS=?
Select Device Type
#VLS=n
o
Phone Line with Telephone handset
1
Handset
2
On-Board Speaker
3
Microphone
4
Telephone line with on-board speaker ON and handset
6
SpeakerPhone
Oak Technology
A-19
Technical Specification
011-610/011-611
#VRA - Ringback Goes Away Timer (Originate)
When originating a voice call, this command can set the "Ringback Goes Away" timer value, an amount of time
measured from when the ringback cadence stops once detected. If ringback is not detected within this period,
the modem assumes that the remote has picked up the line and switches to Online Voice Command Mode. Every
time a ringback cadence is detected, this timer is reset.
Parameters: n = 0 - 255 (0 - 2.55 seconds)
Default: 70
Result Codes:
OK
ERROR
if n = 0 - 255
Otherwise
Command options:
#VRA?
#VRA=?
#VRA=O
#VRA=n
Return the current setting
Return the message, "0-255"
Turn off the timer. The dialing modem sends VCON and enters Online Voice Command
Mode after one ringback.
Set the timer (timer = n * 0.01 seconds)
#VRN - Ringback Never Came Timer (Originate)
When originating a voice call, this command sets the "Ringback Never Came" timer value, an amount of time
measured from completion of dialing. If a ringback is not detected within this period, the modem assumes the
remote has picked up the line and switches to Online Voice Command Mode.
Parameters: n = 0 - 255 (0 - 2.55 seconds) "
Result Codes:
OK
ERROR
if n = 0 - 255
Otherwise
Command option:
#VRN?
#VRN=?
#VRN=O
#VRN=n
Return the current setting
Return the message, "0-255"
Turn off the "Ringback Never Came timer." After dial ing, the modem sends VCON and
enters Online Voice Command Mode immediately.
Set the timer (duration = n * 0.01 second)
#VRX - Voice Receive
This command sets the modem in Voice Receive Mode.
Parameters: None
Result Codes:
CONNECT
ERROR
When voice transfer from modem to DTE can begin
if #VLS=O and not connected to any input device
#VSD - Silence Deletion Tuner (Voice Receive)
This command can enable/disable Voice Receive Mode silence detection. Silence Deletion is not supported in
Oak HSP Modem.
Parameters: n = 0
Default: 0
Result Codes:
OK
ERROR
ifn = 0
Otherwise
Command options:
#VSD?
#VSD=?
#VSD=O
Oak Technology
Return current setting
Return the message, "0"
Disable Silence Deletion
A-20
Technical Specification
011-611 HSP Fax/Data Modem
#VSK - Buffer Skid Setting
This command queries and sets the number of bytes of spare space, after the XOFF threshold is reached, in the
modem's buffer duringVoice Transmit Mode. This equates to the "skid" spare buffer space, or the amount of data
the DTE can continue to send after being told to stop sending data by the modem, before the modem voice
transmit buffer overflows.
Parameters: n = 0 - 255
Default: 255
Result Code:
OK
if n = 0 - 255
ERROR
Otherwise
Command options:
Return the current setting
#VSK?
Return the message, "0-255"
#VSK=?
Set the skid buffer size to n bytes
#VSK=n
#VSP - Silence Detection Period (Voice Receive)
This command sets the Voice Receive Mode silence detection period value. If the modem does not receive any
ADPCM data after the timer expired, it wi II cause the modem to send s or q codes.
Parameters: n = 0 - 255 (0 - 25.5 seconds)
Default: 55
Result Code:
OK
if n = 0 - 255
Otherwise
ERROR
Command options:
Return current setting
#VSP?
Return the message, "0-255"
#VSP=?
Disable the silence period detection timer
#VSP=O
timer = n * 0.1 second
#VSP=n
#VSR - Sampling Rate Selection
This command sets the audio codec sampling rate.
Parameters: n = 8000 (8000 Hz sampling rate)
Default: 8000
Result Codes:
OK
if n = 8000
ERROR
Otherwise
Command options:
Return the current setting
#VSR?
Return the message, 1/8000"
#VSR=?
Set the sample rate to 8000
#VSR=8000
Oak Technology
A-21
Technical Specification
OTI-610/0TI-611
#VSS - Silence Sensitivity Tuner (Voice Receive)
This command sets the sensitivity in Voice Receive Mode silence detection.
Parameters: n = 0 - 3
Default: 2
Result Codes:
OK
if n = 0 - 3
Otherwise
ERROR
Command options:
Return current setting
#VSS?
Return
the message, "0-3"
#VSS=?
Disable
silence detection by the modem in Voice Receive Mode
#VSS=O
Least
sensitive
setting
#VSS=l
Medium
sensitive
setting
#VSS=2
Most sensitive setting
#VSS=3
#VTD - Tone Reporting Capability
This command sets which types of tones can be detected and reported to the DTE via shielded codes in Voice
Transmit, Voice Receive, and Online Voice Command Modes.
Parameters: i, j, k
Default: 3F, 3F, 3F
Result Codes:
OK
If settings are supported by the modem
ERROR
Otherwise
Command options:
#VTD?
Return current setting
Returns the tone reporting capabilities of the modem.
#VTD=?
Where i, j, k corresponds to the desired capabilities (see table below), i for Voice
#VTD=i,j,k
Transmit, j forVoice Receive, and k for Online Voice Command Modes.
Bit
Oak Technology
Description
0
0/1 = Disable/Enable DTMF tone capability
1
0/1 = Disable/Enable V.2S 1300-Hz Calling tone capability
2
0/1 = Disable/Enable V.30 11 OO-Hz Facsimile Calling tone capability
3
0/1 = Disable/Enable V.2S/f.30 21 OO-Hz Answer tone capability
4
0/1 = Disable/Enable 222S-Hz Answer tone capability
5
0/1 = Disable/Enable call progress tone and cadence tone capability
A-22
Technical Specification
011-611 HSP Fax/Data Modem
#VTS - Play Tone String (Online Voice Command Mode)
This command can play one or more DTMF or other tones. No key abort is allowed.
Dual or Single Tones:
These are represented by a substring enclosed in square brackets ("[ ]") within
the parameter. Each such sub-string consists of three subelements corresponding to two
frequencies in Hertz (0, or 2000-3000) and a duration (ASCII decimal in units of lOOms).
Varying DTMF Digits: This is represented by a substring enclosed in curly braces ("{ }") within the parameter.
Each such sub-string consists of two subelements corresponding to a OTMF digits (0-9, A-O, *, I), and
alternate duration in units of lOOms.
Parameters: The tone generation consists of elements in a list with each element separated by commas.
Result Codes:
OK
ERROR
Command to play tones on currently selected device is accepted.
Command was not issued in Online Voice Command Mode or string is grammatically
incorrect.
#VTX - Voice Transmit
This command sets the modem in Voice Transmit Mode. The #VLS command should have been previously issued
correctly.
Parameters: None
Result Codes:
CONNECT
ERROR
Oak Technology
When voice transmission by OTE can begin.
If #VLS=O and output device is not connected.
A-23
Technical Specification
011-610/011-611
A.11 %P - PTTTESTING UTILITIES
This facility testing of signal levels provides a continuous signal when the modem is in IDLE mode. This allows
the user to initiate a series of signal that are necessary for PTT approval. These signals are answer tone, carriers,
modulation, and other pertinent signals. A selected test will be terminated when any keyboard character is
entered. The following are command descriptions.
Note:
For DTMF, the transmit level is -1 OdBm for low band and -8dBm for high band; inter-digit delay is fixed
at 70ms. All other transmit level is adjustable according to the setting of register 591 (from -10 to 15dBm). Speaker control initiates by command ATLn.
%POO - O/oP09
%Pl0
O/oPll
O/oP12
O/oP13
O/oP14
O/oP15
%P16
O/oP17
%P18
%P19
O/oP20
%P21
O/oP22
O/oP23
%P24
O/oP25
O/oP26
O/oP27
O/oP28
%P29
O/oP30
O/oP31
%P32
%P33
O/oP34
%P35
O/oP36
O/oP37
O/oP38
O/oP39
O/oP40
O/oP41
%P42
%P43
%P44
O/oP45
O/oP46
O/oP47
O/oP48
O/oP49
O/oP50
Oak Technology
DTMF tone digits from 0 to 9.
DTMF digit A.
DTMF digit B.
DTMF digit C.
DTMF digit D.
DTMF digit *.
DTMF digit #.
V.21 Channel 1 mark 980 Hz.
V.21 Channel 2 mark 1 650 Hz.
V.23 Reversed channel mark 390 Hz.
V.23 Forward channel mark 1300 Hz.
V.22 Originate.
V.22bis originate.
V.22 Answer.
V.22bis Answer.
V.21 Channell space 1180 Hz.
V.21 Channel 2 space 1850 Hz.
V.23 Reversed channel space 450 Hz.
V.23 Forward channel space 2100 Hz.
V.32 at 9600 bps.
V.32bis 14400 bps.
Silence, off-hook.
V.25 Answer tone 21 00 Hz.
Guard tone 1800 Hz.
V.25 Calling tone 1300 Hz.
Fax calling tone 1100 Hz.
V.21 Channel 2 1650 Hz.
V.27ter 2400 bps.
V.27ter 4800 bps.
V.29 7200 bps.
V.29 9600 bps.
V.17 7200 bps long train.
V.17 7200 bps short train.
V.l 7 9600 bps long train ..
V.17 9600 bps short train.
V.17 12000 bps long train.
V.17 12000 bps short train.
V.17 14400 bps long train.
V.17 14400 bps short train.
V.34, 2400 bps modulation.
V.34, 4800 bps modulation.
V.34, 7200 bps modulation.
A-24
Technical Specification
011-611 HSP Fax/Data Modem
%P51
%P52
%P53
%P54
O/oP55
O/oP56
O/oP57
O/oP58
O/oP59
O/oP60
O/oP61
O/oP62
O/oP63
O/oP64
O/oP65
O/oP66
O/oP67
V.34, 9600 bps modulation.
V.34, 12000 bps modulation.
V.34, 14400 bps modulation.
V.34, 16800 bps modulation.
V.34, 19200 bps modulation.
V.34, 21600 bps modulation.
V.34, 24000 bps modulation.
V.34, 26400 bps modulation.
V.34, 28800 bps modulation.
V.32bis 9600 bps modulation.
V.32bis 12000 bps modulation.
Bell 212A originate 1200 bps
Bell 212A answer 1200 bps
Bell 103 originate mark 1270 Hz
Bell 103 originate space 1070 Hz
Bell 103 answer mark 2225 Hz
Bell 103 answer space 2025 Hz
%P99,n
where 0<= n <=23
f(Hz) = n * (150Hz)
n
f(Hz)
o
0
modem goes off hook and reports power level of incoming signal if present
150
1
2
300
3
450
4
600
5
750
6
900
7
1050
8
1200
9
1350
10
1500
11
1650
12
1800
13
1950
14
2100
15
2250
16
2400
17
2550
18
2700
19
2850
20
3000
21
3150
22
3300
23
3450
Oak Technology
A-25
Technical Specification
OTI-610/011-611
% I or % B Country Code Selection and Identification
This command provides the ability of selection the desired country telephony Central Office. When the selection
is correct, a set of the selected country parameters will be loaded for the current operation.
Command format:
Country
USA
France
Germany
Italy
Sweden
UK
Japan
Australia
Spain
Taiwan
Singapore
Korea
Switzerland
Norway
Netherlands
Belgium
Canada
Ireland
Portugal
Poland
Hungary
Finland
Denmark
ATO/oin
n
Comment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Factory defau It
Result Codes:
OK
ERROR
Command format:
Result Codes:
If correct selection.
Otherwise.
AT%H
country name CO
(Central Office)
ERROR
Otherwise.
Oak Technology
A-26
Technical Specification
APPENDIX B
HOST SIGNAL PROCESSING (HSP)
BASED WAVETABLE SYNTHESIZER
The OTI-61 0 and OTI-611 provide the user with two wavetable synthesizer options: 1) DSP-based with external
2MB ROM which contains the General MIDI (GM) sample set, or 2) an HSP-based software wavetable
synthesizer wherein the synthesizer engine and GM sample set are contained in system memory. This appendix
discusses the HSP-based wavetable synthesizer.
B.1
HSP WAVETABlE SYNTHESIZER SPECIFICATIONS
•
Extensible, professional-quality software synthesizer up to 32-voice polyphony
•
Full 16 MIDI channel multi-timbral support
•
Complete GM sample set
•
Programmable reverb and chorus effects control
•
Supports downloadable samples to extend instrument options beyond General MIDI
•
User-selectable maximum RAM c?che, CPU utilization, and number of allowable voices
•
Intelligent scaling and dynamic buffering to minimize CPU utilization
•
Real-time instrument selection changes when used with CyberSound Keyboard application
•
Works with standard Windows 95 software sequencers (Cakewalk, Voyetra, etc.)
Minimum System Recommendations
OTI-611 Environment
OTI-610 Environment
Operating System
Windows 95
Windows 95
CPU
166-MHz Pentium class
166-MHz Pentium I\t1MX class
133-MHz Pentium class
166-MHz Pentium I\t1MX class
Total System RAM
12 Megabytes
12 Megabytes
Free Hard Disk Space
5.0 Megabytes
5.0 Megabytes
Oak Technology
B-1
Technical Specification
OTI-610/0TI-611
B.2
HSP WAVETABLE SYNTHESIZER DESCRIPTION
The OTI-61 0 and OTI-611 use an HSP-based wavetable synthesizer and General MIDI sample set known as
CyberSound GM. CyberSound GM is a programmable General MIDI synthesizer implemented in software for
Windows 95. CyberSound GM for the OTI-61 0 and OTI-611 is available in two code versions supporting either
Pentium class or Pentium MMX class CPUs.
CyberSound GM offers all of the functionality of a stand-alone General MIDI module or wavetable synthesizer on
a PC sound card. CyberSound GM provides programmable effects processing and customizable system
performance settings and monitoring. Coupled with CyberSound Keyboard, the user has a complete, highquality, MIDI controllable, wavetable synthesizer for music playback at significantly lower cost.
CyberSound GM utilizes both traditional and revolutionary music synthesis techniques synthesis, wavetable sounds, and physical model ing.
B.3
digital and analog
GENERAL MIDI DESCRIPTION
The General MIDI Specification, published by the International MIDI Association, defines a set of general
capabilities for GM Instruments. The GM Specification includes the definition of a GM sound set (a patch
number or program number map), a GM percussion map (mapping of percussion sounds to note numbers), and
a set of GM performance capabilities (number of voices, types of MIDI messages recognized, etc.).
A MIDI sequence which has been generated for use on a General MIDI instrument should play correctly on any
General MIDI synthesizer or sound module. The numbers in the table on page 8-4 refer to the program change
number, which is called within a sequence to select a particular instrument or voice. In synthesizers or sound
modules designed to conform to the General MIDI Standard, Program Change Number 1 will always be Acoustic
Grand Piano, while Program Change Number 47 is always the Orchestral Harp, and so on. Any of these
instrument voices can be selected by issuing its appropriate program change number on any of the 16 MIDI
channels, except for channell O. For General MIDI compatibility among GM instruments or sound modules,
MIDI Channell 0 is always reserved for the program change number, which selects the percussion sounds, or
drum kit, of the GM-compliant synthesizer or rack style sound module.
The General MIDI sound set is grouped into "sets" of related sounds. For example, program numbers 1-8 are
piano sounds, 9-16 are chromatic, or tonal, percussion sounds, 17-24 are organ sounds, 25-32 are guitar sounds,
etc. The General MIDI system utilizes MIDI channels 1-9 and 11-16 for chromatic, or tonal, instrument sounds,
while channel number lOis utilized for "key-based" non-tonal, percussion sounds. For the instrument sounds on
channels 1-9 and 11-16, the note number in a MIDI Note On message is used to select the pitch of the sound to
be played. For example, if the vibraphone instrument (program number 12) has been selected on channel 3, then
playing note number 60 on channel 3 would play the middle C note (this would be the default note to pitch
assignment on most instruments), and note number 59 on channel 3 would play 8 below middle C. Both notes
would be played using the vibraphone sound.
The General MIDI percussion map used for channell 0 is given in the table on page B-11. For these "key-based"
non-tonal percussion sounds, the note number data in a MIDI Note On message is used to trigger the percussion
sounds.
There are 47 note numbers in the General MIDI percussion map. However, the HSP wavetable synthesizer
provided with the OTI-61 0/OTI-611 provides 61 percussion sounds, including the 47 required by the General
MIDI Standard.
Oak Technology
B-2
Technical Specification
Host Signal Processing (HSP) Based Wavetable Synthesizer
Note numbers on channell 0 are used to select which drum or percussion sound will be played. For example, a
Note On message on channell 0 with note number 60 will playa hi bongo drum sound. Note number 59 on
channel 10 will play the Ride Cymbal 2 sound.
It should be noted that the General MIDI system specifies sounds using program numbers 1 through 128. The
MIDI Program Change message used to select these sounds uses an 8-bit byte, which corresponds to decimal
numbering from 0 through 127, (or OOH through 7FH hexadecimal) to specify the desired program number.
Thus, to select GM sound number 10, the glockenspiel, the Program Change message will have a data byte with
the decimal value 9.
The GM system specifies which instrument or sound corresponds with each program/patch number, but General
MIDI does not specify how these sounds are produced. Thus, program number 1 should select the acoustic grand
piano sound on any General MIDI instrument. However, the acoustic grand piano sound on two General MIDI
synthesizers that use different synthesis techniques may sound quite different. Thus, the quality of the synthesizer
is based on the quality of the synthesis technique for a particular instrument sound. For some instruments, the
sounds may be rendered better using an FM synthesis technique, while other instruments may be rendered better
using wavetable (recorded instrument samples) playback, or physical modeling synthesis, which not only models
the instrument but the method of playing it.
There are other requirements of General MIDI, such as the synthesizer or sound module being capable of
responding to 16 MIDI channels with voice polyphony (16 pitched sounds and 8 percussion sounds at once),
resulting in 24-voice polyphony.
8.4
GENERAL MIDI SOUND SAMPLE SET DESCRIPTION
The high-quality GM sample set is derived from profeSSional music sample libraries, and is customized for use
with the OTI-61 0 and OTI-611. A complete listing of the GM sample set provided with the OTI-61 0 and OTI-611
is given in the table below. A complete listing of the GM Percussion Map (percussion sounds) provided with the
OTI-610 and OTI-611 is given in the table on page 8-11.
Since CyberSound GM is capable of downloadable samples, the user is not limited to the GM sample set.
Additional sounds, even complete sound libraries, can be used with CyberSound GM.
Oak Technology
B-3
Technical Specification
011-610/011-611
General MIDI Sound Set Sample Set (All Channels Except 10):
Prog #
Instrument
Prog#
Instrument
Prog #
Instrumnet
Prog #
Instrument
1
Acoustic Grand Piano
33
Acoustic Bass
65
Soprano Sax
97
FX 1 (rain)
2
Bright Acoustic Piano
34
Electric Bass (finger)
66
Alto Sax
98
FX 2 (soundtrack)
3
Electric Grand Piano
35
Electric Bass (pick)
67
Tenor Sax
99
FX 3 (crystal)
4
Honky-tonk Piano
36
Fretless Bass
68
Baritone Sax
100
FX 4 (atmosphere)
5
Electric Piano 1
37
Slap Bass 1
69
Oboe
101
FX 5 (brightness)
6
Electric Piano 2
38
Slap Bass 2
70
English Horn
102
FX 6 (goblins)
7
Harpsichord
39
Synth Bass 1
71
Bassoon
103
FX 7 (echoes)
8
Clavi
40
Synth Bass 2
72
Clarinet
104
FX 8 (sci-fi)
9
Celesta
41
Violin
73
Piccolo
105
Sitar
10
Glockenspiel
42
Viola
74
Flute
106
Banjo
11
Music Box
43
Cello
75
Recorder
107
Shamisen
12
Vibraphone
44
Contrabass
76
Pan Flute
108
Koto
13
Marimba
45
Tremolo Strings
77
Blown Bottle
109
Kalimba
14
Xylophone
46
Pizzicato Strings
78
Shakuhachi
110
Bag pipe
15
Tubular Bells
47
Orchestral Harp
79
Whistle
111
Fiddle
16
Dulcimer
48
Timpani
80
Ocarina
112
Shanai
17
Drawbar Organ
49
String Ensemble 1
81
Lead 1 (square)
113
Tinkle Bell
18
Percussive Organ
50
String Ensemble 2
82
Lead 2 (sawtooth)
114
Agogo
19
Rock Organ
51
SynthStrings 1
83
Lead 3 (calliope)
115
Steel Drums
20
Church Organ
52
SynthStrings 2
84
Lead 4 (chiff)
116
Woodblock
21
Reed Organ
53
Choir Aans
85
Lead 5 (charang)
117
Taiko Drum
22
Accordion
54
Voice Oohs
86
Lead 6 (voice)
118
Melodic Tom
23
Harmonica
55
Synth Voice
87
Lead 7 (fifths)
119
Synth Drum
24
Tango Accordion
56
Orchestra Hit
88
Lead 8 (bass + lead)
120
Reverse Cymbal
25
Acoustic Guitar - nylon
57
Trumpet
89
Pad 1 (new age)
121
Guitar Fret Noise
26
Acoustic Guitar - steel
58
Trombone
90
Pad 2 (warm)
122
Breath Noise
27
Electric Guitar (jazz)
59
Tuba
91
Pad 3 (polysynth)
123
Seashore
28
Electric Guitar (clean)
60
Muted Trumpet
92
Pad 4 (choir)
124
Bird Tweet
29
Electric Guitar (muted)
61
French Horn
93
Pad 5 (bowed)
125
Telephone Ring
30
Overdriven Guitar
62
Brass Section
94
Pad 6 (metallic)
126
Helicopter
31
Distortion Guitar
63
SynthBrass 1
95
Pad 6 (halo)
127
Applause
32
Guitar Harmonics
64
SynthBrass 2
96
Pad 7 (sweep)
128
Gunshot
Oak Technology
B-4
Technical Specification
Host Signal Processing (HSP) Based Wavetable Synthesizer
The following charts break down the MIDI sound sample set by type of instrument sound.
Piano:
Prog #
Program Description
0
Acoustic Grand Piano
1
Bright Acoustic Piano
2
Electric Grand Piano
3
Honky-tonk Piano
4
Rhodes Piano
S
Chorused Piano
6
Harpsichord
7
Clavinet Chromatic
Tonal Percussion:
Prog #
Program Description
8
Celesta
9
Glockenspiel
10
Music Box
11
Vibraphone
12
Marimba
13
Xylophone
14
Tubular Bells
1S
Dulcimer
Oak Technology
8-S
Technical Specification
011-610/011-611
Organ:
Prog#
Program Description
16
Hammond Organ
17
Percussive Organ
18
Rock Organ
19
Church Organ
20
Reed Organ
21
Accordion
22
Harmonica
23
Tango Accordion
Guitar:
Prog#
Program Description
24
Acoustic Guitar (nylon)
25
Acoustic Guitar (steel)
26
Electric Guitar (jazz)
27
Electric Guitar (clean)
28
Electric Guitar (muted)
29
Overdriven Guitar
30
Distortion Guitar
31
Guitar Harmonics
Bass:
Prog#
Program Description
32
Acoustic Bass
33
Electric Bass (finger)
34
Electric Bass (pick)
35
Fretless Bass
36
Slap Bass 1
37
Slap Base 2
38
Synth Bass 1
39
Synth Bass 2
Oak Technology
8-6
Technical Specification
Host Signal Processing (HSP) Based Wavetable Synthesizer
Strings:
Prog #
Program Description
40
Violin
41
Viola
42
Cello
43
Contrabass
44
Tremolo Strings
45
Pizzicato Strings
46
Orchestral Harp
47
Timpani
Ensemble:
Prog #
Program Description
48
String Ensemble 1
49
String Ensemble 2
50
SynthStrings 1
51
SynthStrings 2
52
Choir Aahs
53
Voice Oohs
54
Synth Voice
55
Orchestra Hit
Brass:
Prog #
Program Description
56
Trumpet
57
Trombone
58
Tuba
59
Muted Trumpet
60
French Horn
61
Brass Section
62
Synth Brass 1
63
Synth Brass 2
Oak Technology
B-7
Technical Specification
OTI-610/0TI-611
Reed:
Prog #
Program Description
64
Soprano Sax
65
Alto Sax
66
Tenor Sax
67
Baritone Sax
68
Oboe
69
English Horn
70
Bassoon
71
Clarinet
Pipe:
Prog #
Program Description
72
Piccolo
73
Flute
74
Recorder
75
Pan Flute
76
Bottle Blow
77
Shakuhachi
78
Whistle
79
Ocarina
Synthesizer lead:
Prog #
Program Description
80
Synth Lead 1 (Square)
81
Synth Lead 2 (Sawtooth)
82
Synth Lead 3 (Caliope Lead)
83
Synth Lead 4 (Chiff Lead)
84
Synth Lead 5 (Charang)
85
Synth Lead 6 (Voice)
86
Synth Lead 7 (Fifths)
87
Synth Lead 8 (Brass + Lead)
Oak Technology
B-8
Technical Specification
Host Signal Processing (HSP) Based Wavetable Synthesizer
Synthesizer Pad:
Prog #
Program Description
88
Pad 1 (new age)
89
Pad 2 (warm)
90
Pad 3 (polysynth)
91
Pad 4 (choir)
92
Pad 5 (bowed)
93
Pad 6 (metallic)
94
Pad 7 (halo)
95
Pad 8 (sweep)
Synthesizer Effects:
Prog #
Program Description
96
FX 1 (rain)
97
FX 2 (soundtrack)
98·
FX 3 (crystal)
99
FX 4 (atmosphere)
100
FX 5 (brightness)
101
FX 6 (goblins)
102
FX 7 (echoes)
103
FX 8 (sci-fi)
Ethnic:
Prog #
Program Description
104
Sitar
105
Banjo
106
Shamisen
107
Koto
108
Kalimba
109
Bagpipe
110
Fiddle
111
Shanai
Oak Technology
B-9
Technical Specification
011-610/011-611
Non-tonal Percussive:
Prog #
Program Description
112
Tinkle Bell
113
Apogo
114
Steel Drums
115'
Woodblock'
116
Taiko Drum
117
Melodic Tom
118
Synth Drum
119
Reverse Cymbal
Sound Effects:
Prog #
Program Description
120
Guitar Fret Noise
121
Breath Noise
122
Seashore
123
Bird Tweet
124
Telephone
125
Helicopter
126
Applause
127
Gunshot
Oak Technology
8-10
Technical Specification
Host Signal Processing (HSP) Based Wavetable Synthesizer
The following table gives the General MIDI percussion map:
MIDI Note
MIDI Note
Percussion Sound
#
Name
27
0#1
28
Percussion Sound
#
Name
High Q
58
A#3
Vibraslap
El
Slap
59
B3
Ride Cymbal 2
29
Fl
Scratch Push
60
C4
High Bongo
30
F#l
Scratch Pull
61
C#4
Low Bongo
31
Gl
Sticks
62
04
Mute High Conga
32
G#l
Click Square
63
0#4
Open High Conga
33
Al
Metronome Click
64
E4
Low Conga
34
A#l
Metronome Bell
65
F4
High Timbale
35
B1
Acoustic Bass Drum
66
F#4
Low Timbale
36
C2
Bass Drum 1
67
G4
High Agogo
37
C#2
Side Stick
68
G#4
Low Agogo
38
02
Acoustic Snare
69
A4
Cabasa
39
0#2
Hand Clap
70
A#4
Maracas
40
E2
Electric Snare
71
B4
Short Whistle
41
F2
Low Floor Tom
72
C5
High Whistle
42
F#2
Closed High Hat
73
C#5
Short Guiro
43
G2
High Floor Tom
74
05
Long Guiro
44
G#2
Pedal High Hat
75
D#5
Claves
45
A2
Low Tom
76
E5
High Wood Block
46
A#2
Open High Hat
77
F5
Low Wood Block
47
B2
Low-Mid Tom
78
F#5
Mute Cuica
48
C3
High-Mid Tom
79
G5
Open Cuica
49
C#3
Crash Cymbal 1
80
G#5
Mute Triangle
50
03
High Tom
81
AS
Open Triangle
51
0#3
Ride Cymbal 1
82
A#5
Shaker
52
E3
Chinese Cymbal
83
B5
Jingle Bell
53
F3
Ride Bell
84
C6
Belltree
54
F#3
Tambourine
85
C#6
Castanets
55
G3
Splash Cymbal
86
06
Mute Surdo
56
G#3
Cowbell
87
0#6
Open Surdo
57
A3
Crash Cymbal 2
Note:
All percussion sounds listed in bold type are the required General MIDI percussion sounds. Those listed
in ital ics are the extra ones provided with the OTI-61 0/OTI-611 .
Oak Technology
8-11
Technical Specification
011-610/011-611
B.5
CYBERSOUND KEYBOARD DESCRIPTION
CyberSound Keyboard is an interactive software MIDI keyboard application that works in conjunction with the
CyberSound GM wavetable synthesizer. The application permits the user to play musical notes and change
instrument settings in real time.
Basic specifications are:
•
PC QWERTY keyboard input with three-octave range
•
One-finger/mouse-c1ick chord input
•
Mu Itiple style arpeggiator
B.6
WAVETABLE SYNTHESIZER KEY/NOTE RANGE
In the General MIDI Specification, the MIDI note number range is given as 0 through 127, corresponding to Key
Name C-l through G9. Not all synthesizers are able to generate tones over the entire MIDI note range. It is
necessary to consult the MIDI implementation chart for the particular synthesizer to determine the note range
that is covered.
A standard piano keyboard layout consists of 88 keys, from Key Name AD to Key Name C120. Those 88 keys
cover 7 octaves (1 through 8) plus 4 keys (AD, A#O, BO at the low end, and C9 at the high end), and correspond to
MIDI Note Numbers 21 through 120.
An octave consists of 12 notes. For example, the notes within Octave 2 would be:
C2,C2#,D2,D2#,E2,F2,F2#,G2,G2#,A2,A2#,B2
in ascending order, where the pitch of C2 is lower than the pitch of B2.
Key Name C4 is also known as Middle C in a standard 88-key piano keyboard layout.
The table below summarizes the comparison between a standard piano keyboard layout and MIDI note numbers
and note key names.
0
1
2
3
4
5
6
7
8
9
C-1 B-1
CO BO
C1 B1
C2 B2
0-
B3
C4 B4
C5 B5
C6 B6
C7 B7
C8 B7
C9 B9
Key Name
C-1
CO
C1
C2
0
C4
C5
C6
C7
C8
C9
G9
MIDI Note #
0
12
24
36
48
60
72
84
96
108
120
127
Standard 88
Piano Keys
-
AO
C1
C2
C3
C4
MidC
C5
C6
C7
C8
C9
-
MIDI Note #
-
21
24
36
48
60
72
84
96
108
120
-
Octave #
-1
Key Name
Range
9
The CyberSound GM HSP-based synthesizer provided with the 011-610/011-611 responds to MIDI Note
Numbers (Key Name) 12 (CO) through 120 (C9).
Oak Technology
B-12
Technical Specification
Host Signal Processing (HSP) Based Wavetable Synthesizer
OTI-610/0TI-611 HSP-Based Wavetable Synthesizer (CyberSound GM) MIDI Implementation Table:
Function
Transmitted
Received
MIDI Channels
1-16
Basic Channel
1
Mode
Remarks
Multi-polyphonic
Default
Note Number
CO - C9
Velocity
0-127
After Touch
X
X
Keys
Channel
Pitch Bend
0
+/- 1 note +/- 8192
X
X
X
X
0
0
0
0
0
0
Modulation
Volume
Pan
Expression
Sustain
Reset All Controls
Program Change #
X
0-127
System Exclusive
X
X
Control
1,2
7
10
11
64
121
Note:
X
X
0 = Yes; X = No
Oak Technology
B-13
Technical SpeCification
•
•
•
•
•
•
1
II
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II
OAK TECHNOLOGY"
CORPORATE
HEADQUARTERS
Oak Technology
139 Kifer Court
Sunnyva le, Ca liforn ia 94086 U.s.A.
408-737 -0888
Fax 408-737-3838
J A PAN
Oak Technology, K.K.
Musashino Nissay Plaza 5F
1-11-4 Nakamachi, Musashino City
Tokyo, Japan 180
81-422-56-3761
Fax 81-422-56-3778
TAIWAN
Oak Techno logy, Inc. Taiwan
Room B, 7F, No.370
Section 1, Fu Hsing South Road
Taipei , Taiwan R.O .C.
886-2-784-9123
Fax 886-2-706-7641
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