Osborne_An_Introduction_to_Microcomputers_Volume_2_Sep78 Osborne An Introduction To Microcomputers Volume 2 Sep78
Osborne_An_Introduction_to_Microcomputers_Volume_2_Sep78 Osborne_An_Introduction_to_Microcomputers_Volume_2_Sep78
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AN INTRODUCTION
TO MICROCOMPUTERS
VOLUME 2
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SOME REAL MICROPROCESSORS
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By Adam Osborne
With Jerry Kane
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Osborne &. Associates, Inc.
Berkeley, California
Library of Congress Catalogue Card Number" 76-374891
ISBN 0-931988-15-2
Copyright © 1975, 1976, 1977, 1978 by Adam Osborne and Associates, Incorporated
All rights reserved. Printed in the United States of America. No part of this publication may be reproduced,
stored in a retrieval system, or transmitted in any form, or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior written permission of the publishers. Original bound volume of
AN INTRODUCTION TO MICROCOMPUTERS series published in 1975.
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Published By
Adam Osborne & Associates, Inc.
P.O. Box 2036
Berkeley, California, U.S.A. 94702
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DISTRIBUTORS OF OSBORNE & ASSOCIATES, INC. PUBLICATIONS
For information on translations and on book distributors outside of the United States of America,
please call or write:
Osborne & Associates, Inc.
P.O. Box 2036
Berkeley, California 94702
United States of America
(415) 548-2805
TVVX 910-366-7277
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CONTRIBUTING AUTHORS
The following persons have contributed in the writing of sections of this book in addition to its principal
authors:
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Susanna Jacobson
Osborne & Associates, Inc.
Curt Ingraham
Osborne & Associates, Inc.
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vii
viii
TABLE OF CONTENTS
CHAPTER
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PAGE
4-Bit Microprocessors and the TMS1000 Series Microcomputers
1-1
TMS1000 Programmable Registers
TMS1000 Memory Addressing Mode
TMS1000 Status Flags
TMS1000 Input and Output Logic
TMS1000 Series Microcomputer Pins and Signals
TMS 1000 Series Microcomputer Instruction Execution
TMS 1000 Series Microcomputer Instruction Set
The Benchmark Program
Data Sheets
1-3
1-5
1-5
1-5
1-6
1-10
1-10
1-10
1-01
The Mostek 3870 (and Fairchild F8)
2-1
The 3870 One-Chip Microcomputer
3870/F8 Programmable Registers
3870 Memory Addressing Modes
3870/F8 Status Flags
3870 Pins and Signals
3870 Instruction Timing and Execution
3870 I/O Ports
3870 Interrupt Logic
Timer/Counter Logic
The 3870 Control Code
The 3870/F8 Instruction Set
The 3870 Benchmark Program
The 3850 CPU
F8 Programmable Registers and Status Flags
F8 Addressing Modes
F8 Clock Circuits
F8 CPU Pins and Signals
F8 Timing and Instruction Execution
F8 I/O Ports
A Summary of F8 Interrupt Processing
The F8 Instruction Set
The Benchmark Program
The 3851 Program Storage Unit (PSU)
The 3851 PSU Read-Only Memory
3851 PSU Input/Output Logic
3851 PSU Interrupt Logic
3851 PSU Programmable Timer Logic
3851 PSU Data Transfer Timing
Using the 3851 PSU in Non-F8 Configurations
The 3861 and 3871 Parallel I/O (PIO) Devices
The 3856 and 3857 16K Programmable Storage Units (16K PSU)
Additional F8 Support Devices
The 3852 Dynamic Memory Interface (DMil
The 3854 Direct Memory Access (DMA) Device
The 3853 Static Memory Interface (SMil
Data Sheets
2-3
2-5
2-6
2-9
2-9
2-11
2-11
2-13
2-15
2-17
2-19
2-26
2-29
2-31
2-31
2-32
2-34
2-35
2-37
2-37
2-37
2-38
2-39
2-40
2-41
2-42
2-45
2-45
2-45
2-47
2-47
2-49
2-49
2-53
2-54
2-01
3-1
The National Semiconductor SC/MP
SCiMP Programmable Registers
Addressing Modes
SC/MP Status Register
SC/MP CPU Signals and Pin Assignments
ix
3-3
3-4
3-5
3-5
TABLE OF CONTENTS (Continued)
CHAPTER
3 (Cont.)
4
SC/MP Timing and Instruction Execution
SC/MP Bus ..;\ccess Logic
SCiMP Input/Output Operations
The SC/MP Halt State
SC/MP Interrupt Processing
SC/MP DMA and Multiprocessor Operations
The SC/MP Reset Operation
SCiMP Serial Input/Output Operations
The SC/MP Instruction Set
The Benchmark Program
Support Devices for the SC/MP CPU
Using Other Microcomputer Support Devices with the SC/MP CPU
Data Sheets
PAGE
. 3-7
3-8
3-10
3-13
3-14
3-17
3-21
3-21
3-22
3-28
3-29
3-31
3-01
The8080A
4-1
The SOSOA CPU
SOSOA Programmable Registers
SOSOA Addressing Modes
SOSOA Status
8080A CPU Pins and Signals
SOSOA Timing and Instruction Execution
Clock Signals
Instruction Fetch Sequence
A Memory Read or Write Operation
Separate Stack Memory Modules
The Wait State
The Wait. Hold and Halt States
The Hold State
The Halt State and Instruction
The Reset Operation
External Interrupts
External Interrupts During the Halt State
Wait and Hold Conditions Following an Interrupt
The S080A Instruction Set
.
The Benchmark Program
Instruction Execution Times and Codes
Support Devices that may be Used with the SOSOA
The 8224 Clock Generator and Driver
The 8224 Clock Generator Pins and Signals
The 8228 and 8238 System Controller and Bus Driver
Bus Driver Logic
Control Signal Logic
8228 System Controller Pins and Signals
The 8259 Priority Interrupt Control Unit (PICU)
8259 PICU Pins and Signals
The 8259 PICU Interrupt Acknowledge Vector
8259 PICU Priority Arbitration Options
How Interrupt Requests and Priority Status are'Recorded
Programming the 8259 PICU
The TMS 5501 Multifunction Input/Output Controller
TMS 5501 Device Pins and Signals
TMS 5501 Device Access
TMS 5501 Interrupt Handling
TMS 5501 Parallel I/O Operations
TMS 5501 Serial I/O Operation
TMS 5501 Interval Timers
Data Sheets
4-3
4-3
4-4
4-5
4-6
4-7
4-8
4-12
4-12
4-12
4-13
4-16
4-17
4-19
4-19
4-21
4-24
4-24
4-24
4-25
4-33
4-46
4-46
4-46
4-48
4-48
4-49
4-49
4-52
4-52
4-54
4-57
4-60
4-62
4-67
4-67,
4-70'
4-74
4-75
4-75
4-76
4-01
x
TABLE OF CONTENTS (Continued)
CHAPTER
5
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6
PAGE
The 8085
5-1
The 8085A CPU
8085A Programmable Registers
8085A Addressing Modes
8085A Status
8085A CPU Pins and Signals
A Comparison of 8085A and 8080A Signals
8085A Timing and Instruction Execution·
The Clock Signals
Memqry Access Sequences
Bus Idle Machine Cycles
The Wait State
The SID and SOD Signals
The Hold State
The Halt State and Instruction
External Interrupts
The Reset Operation
The 8085A Instruction Set
8085A Microprocessor Support Devices
The 8155/815.6 Static Read/Write Memory with 1/0 Ports and Timer
8155/8156 Device Pins and Signals
8155/8156 ParaliellnputlOutput
8155/8156 Device Addressing
The 8155/8156 CounterlTimer
8155/8156 Control and Status Registers
8155/8156 Device Programming
The 8355 Read-Only Memory with I/O
8355 Device Pins and Signals
8355 Ready Logic
8355110 Logic
The 8755A Erasable Programmable Read-Only Memory with 1/0
Data Sheets
5-2
5-3
5-3
5-3
5-3
5-7
5-7
5-8
5-9
5-18
5-20
5-21
5-24
5-26
5-28
5-32
5-34
5-35
5-35
5-35
5-38
5-39
5-41
5-43
5-43
5-45
5-45
5-49
5-50
5-51
5-D1
The 8048 Microcomputer Devices
6-1
The 8048. 8748. 8049.8749 and 8035 Microcomputers
An 8048 and 8049 Functional Overview
8048. 8748. and 8035 Microcomputer Programmable Registers
8048 Series Addressing Modes
A Program Memory Map
8048 Series Status
8048 Series Microcomputer Operating Modes
8048 Series Microcomputer Pins and Signals
8048 Series Timing and Instruction Execution
Internal Execution Mode
External Memory Access Mode
Debug Mode
Single Stepping
Programming Mode
Verification Mode
InputlOutput Programming
Hold State
CounterlTimer Operations
Internal and External Interrupts
6-2
6-3
6-7
6-8
6-12
6-13
6-14
6-15
6-18
6-18
6-20
6-23
6-23
6-24
6-26
xi
6-26
6-26
6-27
6-27
TABLE OF CONTENTS (Continued)
CHAPTER
6 (Cont.)
7
The 8048 Microcomputer Series Instruction Set
The Benchmark Progra~
The 8041 Slave Microcomputer
An 8041 Functional Overview
8041 Data Bus Logic
8041 I/O Ports One and Two
8041 and 8741 Programmable Registers
8041 and 8741 Addressing Modes
8041 and 8741 Status
8041 and 8741 Slave Microcomputer Operating Modes
8041 and 8741 Pins and Signals .
8041 Series Timing and Instruction Execution
8741 Single Stepping and Programming Mode
8041 Input/Output Programming
8041 CounterlTimer Operations
8041 Interrupt Logic
Programming 8048-8041 Data Transfers
The 8041/8741 Instruction Set
The 8021 Single-Chip Microcomputer
An 8021 Fu nctional Overview
8021 I/O Port Pins
The T1 Pin
The 8021 Reset Input
The 8021 Clock Inputs
The 8021 Timer/Counter
8021 Scratchpad Memory and Programming
The 8243 Input/Output Expander
8243 Input/Output Expander Pins and Signals
8243 Input/Output Expander Operations
Data Sheets
PAGE
6-32
6-32
6-41
6-42
6-43
6-44
6-44
6-44
6-45
6-45
6-45
6-46
6-46
6-46
6-47
6-47
6-47
6-49
6-51
6-51
6-51
6-51
6-52
6-53
6-53
6-53
6-53
6-53
6-55
6-01
ZilogZ80
7-1
The Z80 CPU
A Summary of Z80/8080A Differences
Z80 Programmable Registers
Z80 Addressing Modes
Z80 Status
Z80 CPU Pins and Signals
Z80-8080A Signal Compatibility
Z80 Timing and Instruction Execution
Instruction Fetch Execution Sequences
A Memory Read Operation
Memory Write Operation
The Wait State
Input or Output Generation
Bus Requests
External Interrupts
The Halt Instruction
The Z80 Instruction Set
Input/Output Instructions
Primary Memory Reference Instructions
Block Transfer and Search Instructions
Secondary Memory Reference (Memory Operate) Instructions
Immediate Instructions
Jump Instructions
7-1
7-1
7-5
7-6
7-7
7-7
7-9
7-11
7-12
7-13
7-13
7-14
7-14
7-15
7-16
7-19
7-38
7-38
7-39
7-39
7-41
7-41
7-41
xii
TABLE OF CONTENTS (Continued)
CHAPTER
7 (Cont.)
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Subroutine Call and Return Instructions
Immediate Operate Instructions
Jump-on-Condition Instructions
Register-Register Move Instructions
Register-Register Operate Instructions
Register Operate Instructions
Bit Manipulation Instructions
Stack Instructions
I nterrupt Instructions
Status and Miscellaneous Instructions
The Benchmark Program
Support Devices that may be Used with the Z80
The Z80 Parallel 110 Interface (PIO)
Z80 PIO Pins and Signals
Z80 PIO Operating Modes
Z80 PIO Interrupt Servicing
Programming the Z80 PIO
The Z80 Clock Timer Circuit (CTC)
Z80 CTC Functional Organization
Z80 CTC Pins and Signals
Z80 CTC Operating Modes
Z80 CTC Interrupt Logic
Programming the Z80 CTC
Data Sheets
PAGE
7-41
7-41
7-41
7-42
7-42
7-42
7-42
7-43
7-43
7-44
7-44
7-44
7-45
7-46
7-49
7-51
7-52
7-54
7-54
7-55
7-57
7-60
7-60
7-01
The Motorola MC6800
9-1
The MC6800 CPU
The MC6800 Programmable Registers
MC6800 Memory Addressing Modes
MC6800 Status Flags
MC6800 CPU Pins and Signals
MC6800 Timing and Instruction Execution
The Hold State. the Halt State and Direct Memory Access
Interrupt Processing. Reset and the Wait State
The MC6800 Instruction Set
The Benchmark Program
MC6800 Summary of Cycle by Cycle Operation
Support Devices that may be Used with the MC6800
The MC6802 CPU with Read/Write Memory
The MC6870 Two Phase Clocks
The MC6870A Clock Device
The MC6871A Clock Device
The MC6871 B Clock Device
The MC6875 Clock Device
Some Standard Clock Signal Interface Logic
The MC6820 and MCS6520 Peripheral Interface Adapter (PIA)
The MC6820 PIA Pins and Signals
MC6820 Operations
The MC6850 Asynchronous Communications Interface Adapter (ACIA)
The MC6850 ACIA Pins and Signals
MC6850 Data Transfer and Control Operations
MC6850 ACIA Control Codes and Status Flags
The MC6852 Synchronous Serial Data Adapter (SSDA)
MC6852 SSDA Pins and Signals
MC6852 Data Transfer and Control Operations
MC6852 Status Register
9-3
9-3
9-3
9-5
9-6
9-7
9-10
9-12
9-16
9-17
9-25
9-31
9-33
9-39
9-41
9-41
9-43
9-44
9-44
9-45
9-45
9-48
9-55
9-55
9-57
9-59
9-61
9-61
9-63
9-65
xiii
TABLE OF CONTENTS (Continued)
CHAPTER
9 (Cant.)
10
The MC6852 Control Registers
Programming the MC6852
The MC8507 (or MC6828) Priority Interrupt Controller (PIC)
MC6828 Pins and Signals
The Interrupt Acknowledge Process
Interru pt Priorities
Interrupt Inhibit Logic
The MC6840 Programmable CounterlTimer
The MC6840 CounterlTimer Pins and Signals
MC6840 Addressing
MC6840 CounterfTimer Programmable Options
The MC6844 Direct Memory Access Controller
MC6844 DMA Controller Pins and Signals
MC6844 Addressable Registers
MC6844 DMA Transfer Modes
MC6844 DMAC Three7State Control. Cycle Stealing Mode
MC6844 DMAC Halt Modes
Comparing MC6844 DMAC Modes
Using an MC6844 DMAC with Mixed Modes
The MC6844 Control Registers and Operating Options
Resetting the MC6844 DMAC
Programming the MC6844 DMAC
The MC6846 Multifunction Support Device
MC6846 Multifunction Device Pins and Signals
MC6846 CounterfTimer Logic
MC6846 I/O Port Logic
MC6846 Device Reset
Data Sheets
PAGE
9-66
9-70
9-71
9-72
9-74
9-75
9-77
9-78
9-78
9-82
9-94
9-106
9-107
9-109
9-110
9-111
9-113
9-116
9-116
9-116
9-122
9-122
9-124
9-124
9-127
9-128
9-129
9-D1
The MOS Technology MCS6500
10-1
The MCS6500 Series CPUs
MCS6500 Series CPU Programmable Registers
MCS6500 Memory Addressing Modes
MCS6500 Status Flags
MCS6500 CPU Pins and Signals
MCS6500 Timing and Instruction Execution
Interrupt Processing and System Reset
MCS6500 CPU Clock Logic
MCS6500 CPU Interface Logic
The MCS6500 Instruction Set
The Benchmark Program
Support Devices that may be Used with the MCS6500 Series Microprocessors
The MCS6522 Peripheral Interface Adapter
MCS6522 PIA Pins and Signals
MCS6522 Parallel Data Transfer Operations
MCS6522 Interval Timer Logic
MCS6522 Shifter Logic
MCS6522 Interrupt Logic
The MCS6530 Multifunction Support Logic Device
MCS6530 Multifunction Device Pins and Signals
MCS6530 Parallel Data Transfer Operations
MCS6530 Interval Timer and Interrupt Logic
The MCS6532 Multifunction Support Logic Device
MCS6532 Multifunction Device Pins and Signals
MCS6532 Logic Functions
Data Sheets
10-2
10-3
10-4
10-6
10-7
10-13
10-15
10-15
10-15
10-16
10-16
10-27
10-29
10-30
10-33
10-36
10-42
10-46
10-47
10-47
10-51
10-51
10-53
10-54
10-55
10-D1
xiv
TABLE OF CONTENTS (Continued)
CHAPTER
11
PAGE
. 11-1·
The signetics 2650A
The 2650A CPU Logic
2650A Programmable Registers
The 2650A Memory Addressing Modes
The 2650A Status Flags
The 2650A CPU Pins and Signals
Interfacing Memory to the 2650A MicrocompLiter
Interfacing I/O Devices to the 2650A Microcomputer
The 2650A Microcomputer Instruction Process
2650A Microcomputer Direct Memory Access
The 2650A Microcomputer Instruction Set
The 2650A Benchmark Program
Support Devices that may be Used with the 2650A Microprocessor
Data Sheets
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11-1
11-3
11-4
11-8
11-10
11-12
11-12
11-12
11-14
11-14
11-15
11-23
11-D1
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The RCA COS MAC
12-1
The COSMAC CPU
COS MAC Programmable Registers
COSMAC Memory Addressing Modes
COSMAC Status Flags
COS MAC CPU Pins and Signals
COSMAC Timing and Instruction Execution,
COSMAC Memory Read Timing
COSMAC Memory Write Instruction Timing
COS MAC Data Input Data Output and Direct Memory Access
A Summary of COSMAC Interrupt Processing
The COSMAC Instruction Set
The Benchmark Program
Using COSMAC with Other Microprocessor Support Devices
The CDP1852 Parallel I/O Port
CDP1852 Pins and Signals
CDP 1852 Operations Overview
CDP1852 Input Operations
CDP1852 Output Operations
.
Data Sheets
12-2
12-2
12-4
12-5
12-5
12-8
12-11
12-11
12-12
12-17
12-17
12-23
12-32
12-33
12-33
12-33
12-34
12-37
12-D1
IM6100 Microcomputer Devices
13-1
The IM6100 CPU
IM6100 Programmable Registers
IM6100 Memory Space
IM6100 Memory Addressing Modes
IM61 00 Status Flags
IM6100 CPU Pins and Signals
IM61 00 Timing and Instruction Execution
IM6100 No Operation Machine Cycle
IM6100 Data Input Machine Cycle
IM6100 Data Output Machine Cycle
IM6100 Address Demultiplexing
IM61 00 Memory Read Machine CycleTimirig
IM6100 Memory Write Machine Cycle
IM6100 Input/Output Timing
IM61 00 Wait State
IM6100 Hold and Halt Conditions
IM6100 Direct Memory Access
13-2
13-3
13-3
13-3
13-6
13-6
13-9
13-10
13-10
13-10
13-11
13-13
13-14
13-18
13-22
13-23
13-26
xv.
TABLE OF CONTENTS (Continued)
CHAPTER
13 (Cont.)
14
15
The IM6100 Reset
IM61 00 Interrupt Logic
IM6100 Control Panel Logic
External Control Signal Priorities
IM6100 Instruction Set
The IM6100 Benchmark Program.
Some SpeciallM6100 Hardware Considerations
Implementing a Hardware Stack
Support Devices that may be Used with the IM61 00
The IM6101 Parallel Interface Element (PIE)
IM6101 Parallel Interface Element Pins and Signals
IM6101 Functional Logic
IM6101 Interrupt Handling Logic
The IM6102 MEDIC
IM6102 MEDIC Pins and Signals
The IM6100-IM61021nterface
IM6102 Extended Memory Control
IM61 02 Extended Memory Programming Considerations
IM6102 Extended Memory Interrupt Considerations
IM6102 Dynamic Memory Refresh and Direct Memory Access Logic
IM61 02 Programmable Real-Time Clock Logic
IM61 02 MEDIC Instructions
Data Sheets
PAGE
13-29
13-29
13-33
13-37
13-37
13-38
13-47
13-47
13-51
13-53
13-55
13-56
13-62
13-64
13-65
13-69
13-69
13-77
13-78
13-79
13-83
13-85
13-D1
The 8X300 (or SMS300)
14-1
The 8X300 Microcontroller
8X300 Addressable Registers
8X300 Status Flags
8X300 Memory Addressing
8X300 Pins and Signals
8X300 Instruction Execution and Timing
The 8X300 Instruction Set
The 8X300 Benchmark Program
The 8T32. 8T33. 8T35. and 8T36 Interface Vector Byte (IV Byte)
8T32/3/5/6 IV Byte Pins and Signals
8T32/3/5/6 IV Byte Operation
8T32/3/5/6 IV Byte Addresses
The 8T39 and 8T58 Bus Expanders
Data Sheets
14-1
14-3
14-4
14-4
14-5
14-6
14-9
14-17
14-21
14-21
14-23·
14-24
14-26
14-D1
The National Semiconductor PACE and INS8900
15-1
PACE and INS8900 Microcomputer System Overviews
INS8900 Programmable Registers
INS8900 Stack
INS8900 and PACE Addressing Modes
INS8900 and PACE Status and Control Flags
INS8900 and PACE CPU Pins and Signals
INS8900 and PACE Timing and Instruction Execution
The Initialization Operation
The Halt State and Processor Stall Operations
Direct Memory Access Operations
The INS8900 and PACE Interrupt System
The INS8900 and PACE Instruction Set
The Benchmark Program
The PACE DP8302 System Timing Element (STE)
15-2
15-4
15-5
15-6
15-9
15-10
15-11
15-14
15-14
15-15
15-19
15-24
15-33
15-35
xvi
TABLE OF CONTENTS (Continued)
CHAPTER
15 (Cont.)
0
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The PACE Bidirectional Transceiver Element (BTE)
Using Other Microcomputer Support Devices with the PACE and INS8900
Data Sheets
PAGE
15-36
15-38
15-01
The General Instrument CP1600
16-1
The CP1600 Microcomputer System Overview
CP1600 Programmable Registers
CP1600 Memory Addressing Mode
CP1600 Status and Control Flags
CP1600 CPU Pins and Signals
CP1600 Instruction Timing and Execution
CP1600 Memory Access Timing
The CP 1600 Wait State
The CP1600 Halt State
CP 1600 Initialization Sequence
CP1600 DMA Logic
The CP1600 Interrupt Logic
The CP1600 Instruction Set
The Benchmark Program
Support Devices that may be Used with the CP1600
The CP1680 Input/Output Buffer (lOB)
CP1680 lOB Pins and Signals
CP16BO Addressable Registers
The CP1680 Control Register
CP1680 Data Transfer Operations
The CP1680 Interval Timer
CP1680 Interrupt Logic
Data Sheets
16-1
16-3
16-3
16-6
16-6
16-10
16-10
16-12
16-12
16-13
16-13
16-15
16-16
16-25
16-27
16-30
16-30
16-31
16-32
16-33
16-36
16-37
16-01
The General Instrument 1650 Series Microcomputers
17-1
A 1650 Functional Overview
1650 Series Microcomputer Programmable Registers
1650 Series Microcomputer Memory Addressing Modes
1650 Series Microcomputer Pins and Signals
1650 Series Microcomputer Instruction Set
The 1650 Benchmark Program
Data Sheets
17-1
17-4
17-6
17-6
17-8
17-9
17-01
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17
18
The Texas Instruments TMS 9900. TMS 9980, and TMS 9440 Products
18-1
The TMS 9900 Microprocessor
A TMS 9900 Functional Overview
TMS 9900 Programmable Registers
TMS 9900 Memory Addressing Modes
TMS 9900 I/O Addressing
TMS 9900 CPU Pins and Signals
TMS 9900 Timing and Instruction Execution
Memory Access Operations
Memory Select Logic
TMS 9900 I/O Instruction Timing
The Wait State
The Hold State
The Halt Stelte
TMS 9900 Interrupt Processing Logic
The TMS 9900 Reset
The TMS 9900 Load Operation
18-2
18-2
18-3
18-6
18-8
18-13
18~ 15
18-15
18-19
18-20
18-23
18-25
18-25
18-26
18-34
18-34
xvii
TABLE OF CONTENTS (Continued)
CHAPTER
18 (Cont.)
19
20
The TMS 9900 Instruction Set
The Benchmark Program
The TMS 9980A and the TMS 9981 Microprocessors
TMS 9980 Series Microprocessor Pins and Signals
TMS 9980 Series Microprocessor Timing and Instruction Execution
TMS 9980 Series Interrupt Logic
The TMS 9980 Series Instruction Set
The TMS 9940 Single-Chip Microcomputers
TMS 9940 Registers and Read/Write Memory
TMS 9940 CPU Pins and Signal Assignments
TMS 9940 General Purpose Flags
TMS 9940 Timer/Event Counter Logic
TMS 9940 Interrupt Logic
TMS 9940 Reset
Programming a TMS 9940E Erasable Programmable Read-Only Memory
Loading a Program into TMS 9940 Read/Write Memory
The TMS 9940 Instruction Set
The TIM 9904 Four-Phase Clock Generator/Driver
The TMS 9901 Programmable System Interface (PSI)
TMS 9901 Pins and Signals
TMS 9901 PSI Interrupt Logic
TMS 9901 Data Input and Output
TMS 9901 Real-Time Clock Logic
TMS 9901 Reset Logic
Data Sheets
PAGE
18-35
18-42
18-44
18-45
18-49
18-49
18-52
18-52
18-54
18-56
18-65
18-65
18-65
18-65
18-66
18-66
18-66
18-67
18-70
18-73
18-76
18-78
18-80
18-81
18-D1
Single Chip Nova Minicomputer Central Processing Units
19-1
A Product Overview
Nova Programmable Registers
Nova Memory Addressing Modes
Nova Status Flags
MicroNova and 9440 CPU Pins and Signals
CPU Logic and Instruction Execution.
Arithmetic/Logic Instructions
Memory Reference Instructions
Input/Output Instructions
A Nova Summary
9440 Timing and Instruction Execution
MicroNova and 9440 Interrupt Processing
MicroNova and 9440 Direct Memory Access Logic
The MicroNova and 9440 Instruction Sets
The Benchmark Program
Data Sheets
19-2
19-4
19-5
19-10
19-10
19-17
19-17
19-20
19-20
19-22
19-23
19-27
19-31
19-32
19-32
19-D1
The Intel 8086
20-1
The 8086 CPU
8086 Programmable Registers and Addressing Modes
8086 Status
8086 CPU Pins and Signals
8086 Timing and Instruction Execution
8086 Bus Cycles
8086 Instruction Queue
8086 Memory and I/O Device Read Bus Cycle for Simple Configurations
8086 Memory or I/O Device Write Bus Cycle for Minimum Mode
8086 Read and Write Bus Cycles for Maximum Mode
20-3
20-3
20-17
20-19
20-25
20-26
20-27
20-30
20-31
20-32
xviii
TABLE OF CONTENTS (Continued)
CHAPTER
20 (Cont.)
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22
23
24
The 8086 Wait State
The 8086 Hold State
The 8086 Halt State
The 8086 Lock
The 8086 Processor Wait for Test State
The 8086 Processor Escape
The 8086 Reset Operation
8086 Interrupt Processing
Single Stepping Mode
The 8086 Instruction Set
8086-8080A Instruction Compatibility
The Benchmark Program
Instruction Execution Times and Codes
The Intel 8284 Clock Generator/Driyer
8284 Clock Generator/Driver Pins and Signals
The Intel 8288 Bus Controller
8288 Bus Controller Signals and Pin Assignments
The 8282/8283 8-Bit Input/Output Port
The 8282/8283 Input/Output Port Pins and Signal Assignments
The 8286/8287 8-Bit Bidirectional Bus Transceivers
8286 and 8287 Bidirectional Bus Transceiver Pins and Signal Assignments
Some 8086 Microprocessor Bus Configurations
Data Sheets
2900 Series and 6700 Series Chip Slice Products
22-1
The 2901/6701 Arithmetic and Logic Unit (ALU)
The 2909 Microprogram Sequencer
The 2902 Carry Look Ahead
Data Sheets
22-2
22-5
22-8
22-D1
The MC1 0800 Series Chip Slice Logic
23-1
The MC1 0800 Arithmetic and Logic Unit Slice
The MC 10801 Microprogram Control Unit
The MC1 0802 Timing Device
The MC1 0803 Memory Interface Device
Data Sheets
23-3
23-5
23-6
23-6
23-D1
The Hewlett Packard MC2
24-1
An MC2 System Overview
MC2 Programmable Registers and Status
MC2 Memory Addressing Modes
Hardware Aspects of the MC2
The MC2 Instruction Set
The Benchmark Program
25
PAGE
20-34
20-34
20-36
20-37
20-38
20-38
20-38
20-38
20-41
20-41
20-48
20-48
20-67
20-77
20-77
20-80
20-80
20-83
20-83
20-85
20-85
20-86
20-D1
24-1
24-2
24-4
24-4
24-5
24-6
Selecting a Microcomputer
25-1
Designing Logic with Microcomputers -A Sequence of Events
Microcomputer Development Hardware
Microcomputer System Software
An Economic Example
A Look at the Future
25-2
25-3
25-5
25-9
25-10
xix
xx
LIST OF FIGURES
FIGURE
Q
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a:
0
CJ
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w
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(3
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0
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Q
Logic of the TMS1000 Series Microcomputer
TMS1000 and MC141000 Microcomputer Signals and Pin Assignments
TMS1200 and MC141200 Microcomputer Signals and Pin Assignments
TMS 1070 Microcomputer Signals and Pin Assignments
TMS1270 Microcomputer Signals and Pin Assignments
TMS1100 Microcompu~er Signals and Pin Assignments
TMS1300 Micrqcomputer Signals and Pin Assignments
1-2
1-6
1-7
1-7
1-8
1-8
1-9
2-1
2-2
2-3
2-4
2-5
2-6·
2-7
2-8
2·-9
2-10
2-11
2-12
2-2
2-4
2-9
2-26
2-30
2-34
2-39
2-40
2-46
2-48
2-49
2-13
2-14
2-15
2-16
A Fairchild/Mostek F8 Microcomputer System
Logic of the Fairchild/Mostek 3870 Microcomputer
3870 Microcomputer Signals and Pin Assignments
Instructions That Move Data Between the Scratchpad and Various Registers
Logic of the Fairchild F8 3850 CPU
Fairchild 3850 CPU Signals and Pin Assignments
Logic of the Fairchild F8 3851. 3856. and 3857 Programmable Storage Unit
3851 PSU Signals and Pin Assignments
Conceptual Logic to Include a 3851 P5U in a Non-F8 Microcomputer System
3856 PSU Signals and Pin Assignments
3857 PSU Signals and Pin Assignments
Logic of the Fairchild F8 3852 Dynamic Memory Interface (DM!). and of the 3854
Direct Memory Access (DMA) Devices
3852 DMI Signals and Pin Assignments
3854 DMA Signals and Pin Assignments
Logic of the F8 3853 Static Memory Interface (SM!) Device
3853 SMI Signals and Pin Assignments
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
Logic of the SC/MP Microcomputer
SC/MP CPU Signals and Pin Assignments
SC/MP Bus Access Logic Processing Sequence
Bus Utilization of Each SC/MP Instruction
SC/MP Data Input Cycle
SC/MP Data Output Cycle
NHOLD Signal Used to Lengthen SC/MP I/O Operation
Circuit to Cause Programmed Halt for SC/MP CPU
SC/MP Interrupt Instruction Fetch Process
Using SC/MP in a System with Direct Memory Access
One Method of Initializing an SC/MP Multiprocessor System
Forcing the Halt State in an SC/MP Multiprocessor System
An SC/MP System Showing Typical Support Devices that may be Required
SC/MP Data Lines Buffered Using 8216 Devices
3-2
3-6
3-9
3-11
3-12
3-12
3-13
3-13
3-14
3-17
3-20
3-20
3-29
3-30
4-1
The 8080A CPU. 8224 Clock and 8228 System Controller Forming a
Three-Device Microprocessor
8080A CPU Signals and Pin Assignments
A Machine Cycle Consisting of Five Clock Periods
Status Output During T2 of Every Machine Cycle
8080A Instruction Fetch Sequence
8080A Memory Write Timing
The 8080A CPU Operating With Fast Memory and No Wait State
The 8080A CPU Operating With Slow Memory and a Normal Wait State
Floating of Data and Address Busses at <1>2 in T3. for READ Operation Being
Completed Prior to Onset of Hold State
Floating of Data and Address Busses at <1>2 in T4. for a WRITE. or Any Non-READ
Operation (R/WO=False)
Floating of Data and Address Busses for READ Operation in a Three Clock Period
Machine Cycle
e(
@
PAGE
1-1
1-2
1-3
1-4
1-5
1-6
1-7
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9A
4-9B
4-10A
xxi
2-50
2-52
2-54
2-55
2-56
4-4
4-8
4-8
4-10
4-13
4-14
4-15
4-16
4-17
4-18
4-18
LIST OF FIGURES (Continued)
PAGE
FIGURE
4-10B
4-11
4-12
4-13.
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
4-31 "
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
5-1 .
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10.
5-11
5-12
5-13
5-14.
5-15
5-16
5-17·
5-18
Floating of Data and Address Busses at <1>2 in T 1. for WRITE or Any Non-READ
4-18
Operation Being Completed Prior to Onset of Hold State·
4-20
Interrupt Initiation Sequence
Signal Sequences and Timing for Instructions: STC. CMC. CMA. NOP. RLC. RRC. RAL. RAR.
XCHG. EI. DI: DAA. ADD R. ADC R. SUB A. SBB R. ANA R. XRA R. ORA R. CMP R
4-33
Signal Sequences and Timing for Instructions: INR. DCR. MOV REG REG. SPHL. PCHL.
4-34
DCX.INX
4-34
Signal Sequences and Timing for Instructions: DCR. INA. MVI M
Signal Sequences and Timing for Instructions: LDAX. MOV REG M. 'ADI. ACI. SUI. SBI.
ANI. XRI. ORI. CPI. MVI R. ADD M. ADC M. SUB M. SBB M. ANA M. XRA M.
4-35
ORA M. CMP M
4-35
Signal Sequences and Timing for Instructions:STAX. MOV M REG
4-36
Signal Sequences and Timing for Instructions; LHLD
4-36
Signal Sequences and Timing for Instructions: PUSH. RST
4-37
Signal Sequences and Timing for Instructions: POP. RET
4-38
Signal Sequences and Timing for Instructions: DAD
4-38
. Signal Sequences and Timing for Instructions: XTHL
Signal Sequences and Timing for Instructions: LXI. JMP. JNZ. JZ. JNC. JC. JPO.
4-39
JPE. JP. JM
4-39
Signal Sequences and Timing for Instructions: ST A
4-40
Signal Sequences and Timing for Instructions: LDA
4-40
Signal Sequences and Timing for Instructions:SHLD
Signal Sequences and Timing for Instructions: CALL. CNZ. CZ. CNC. CC. CPO. CPE.
CP.CM
'
4-41
4-42
Signal Sequences and Timing for Instructions: RNZ. RZ. 'RNC.RC. RPO. RPE. RP. RM
4-43
Signal Sequences and Timing for Instructions: IN
4-44
Signal Sequences and Timing for Instructions: OUT
4-45
Signal Sequences and Timing for Instructions: HL T
4-47
8224 Clock Generator Signals and Pin Assignments
4-49
8228 System Controller Signals and Pin Assignments
4-51
A Standard. Three Device 8080A Microcomputer System
4-51,
Timing for Control Signals Output by the 8228 System Controller
4-53
8259 Priority Interrupt Control Unit Signals and Pin Assignments
4-54
A System With One PICU
4-56
A System With Three PICUs -Gne Master and Two Slaves
4-68
Logic of the TMS 5501 Multifunction Input/Output Controller
4-69
TMS 5501 Multifunction Input/Output Controller Signals and Pin Assignments
Logic of the 8085A Microprocessor
8085A CPU Signals and Pin Assignments
A Comparison of 8085A and 8080A/8224/8228 Signal Interface
A Four Clock Period Instruction Fetch Machine Cycle
.
A Six Clock Period Instruction Fetch Machine Cycle
A Memory Read Machine Cycle Following an Instruction Fetch
An I/O Read Machine Cycle Following an Instruction Fetch
A Memory Write Machine Cycle Following an Instruction Fetch
An I/O Write Machine Cycle Following an Instruction Fetch
A Bus Idle Machine Cycle Following an Instruction Fetch During Execution of a
DAD Instruction
Wait States Occurring in a Memory Read Machine Cycle
A RIM Instruction Followed by a SIM Instruction
A Hold State Following a Single Machine Cycle Instruction Execution
A Halt Instruction and a Halt StateTerminated by an Interrupt Request
Hold States Occurring Within a Halt State
An Interrupt Being Acknowledged Using a Single Byte Instruction
A Bus Idle Instruction Fetch Machine Cycle
Power On and RESET IN Timing for the 8085A
xxii
5-2
5-4
5-6
5-9
5-10
5-15
5-16
5-17
5-18
5-19
5-20
5-23
5-23
5-26
5-27
5-28
5-30
5-31
LIST OF FIGURES (Continued)
FIGURE
Q
w
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0
D.
a:
0
u
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g
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~
Q
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5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
7-1
7-2
7-3
7-4
7-5
7-6,
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
'PAGE
Logic of the 8155 and 8156 Multifunction Devices
Logic Functions of the 8155/8156 Device
8155/8156 Multifunction Device Signals and Pin Assignments
An 8155 Device Connected to an 8085A CPU Bus
Logic of the 8355 and 8755 Multifunction Devices
Logic Functions of the 8355 Device
8355 Multifunction Device Signals and Pin Assignments
An 8085A-8155/8156-8355 Microcomputer System
8755A Multifunction Device Signals and Pin Assignments
Logic of the 8048 Series Microcomputers
Functional Logic of the 8048,8049,8748,8749, and 8035 Microcomputers
8048 I/O p,orts '1 and 2 Pin Logic
8048 Series Microcomputers' Memory Addressing
8048,8748 and 8035 Microcomputer Pins and Signals
Execution of 8048 Single Machine Cycle Instructions Without any External Access
An 8048 Series External Instruction Fetch
An 8048 Series External Data Read or Write
An 8048-8355 Configuration
Demultiplexing DBO-DB7 to Create Separate Address and Data Busses
An 8048 Single Step Circuit
8748 EPROM Programming and Verification Timing
An Eight-Device Daisy Chained Interrupt Request/Acknowledge Scheme
A Low Chip Implementation of an Eight-Device Daisy Chained Interrupt
Request/Acknowledge Scheme
A Comparison of 8048 and 8041 Functional Logic
8041 and 8741 Microcomputer Pins and Signals
A Comparison of 8048 and 8021 Functional Logic
8021 Microcomputer Pins and Signals
Logic of the 8243 Input/Output Expander
Input/Output Expander Pins and Signals
Functional Diagram of the 8243 Input/Output Expander
An 8243/8048 Configuration with External Logic Read and Write Strobes
\ Timing for Data Output to an 8243 Port Via an MOVD, ORLD, or ANLD Instruction
Timing for Data Input from an 8243 Port
Logic Functions of the Z80 CPU
The Standard 8080A Three-Chip System and Z80,Signal Equivalents
Z80 Programmable Registers
Z80 CPU Signals and Pin Assignments
Z80 Instruction Fetch Sequence
Z80 Memory Read Timing
Z80 Memory Write Timing
Z80 Wait State Timing
Z80 Input or Output Cycles
Z80 Input or Output Cycles with Wait States
Z80 Bus TiminQ
Z80 Response to a Maskable Interrupt Request
Wait States During ?80 Response to a Maskable Interrupt Request
Z80 Response to a Nonmaskable Interrupt Request
Z80 Halt InstnJction Timing
Logic Functions of the Z80 PIO
Z80 PIO Signals ard Pin ASSignments
Mode 0 (Output) Timing
Mode 1 (lnpyt) Timing
Port A. Mode 2 (Bidirectional) Timing
xxiii
5-36
5-37
5-37
5-38
5-46
5-47
5-48
5-48
5-52
6-3
6-4 '
6-6
6-9
6-16
6-19
6-19
6-20
6-21
6-21
6-24
6-25
6-29
6-31
6-42
6-45
6-50
6-52
6-54
6-55
6-56
6-57
6-58
6-58,
7-2
7-3
7-5
7-8
7-12
7-13
7-13
7-14
7-15
7-15
7-16
7-16
7-18
7-19
7-19
7-46
7-48
7-50
7-51
7-51
LIST OF FIGURES (Continued)
FIGURE
PAGE
7-21
7-22
7-23
Interrupt Acknowledge Timing
Z80-CTC Signals and Pin Assignments
Z80-CTC Control Code Interpretation
7-52
7-56
7-61
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
Logic of the MC6800 CPU Device
MC6800 CPU Signals and Pin Assignments
A Standard MC6800 Read Machine Cycle
A Standard MC6800 Write Machine Cycle
TSC Floating the Address Bus
TSC Floating the Address and Data Busses When DBE is Tied to <1>2
System Bus Floating During the Halt State
MC6800 Interrupt Acknowledge Sequence
The Reset Sequence
MC6800 Wait Instruction Execution Sequence
Use of 8080A Support Devices With MC6800 CPU
Timing for8080A Support Devices Used With an MC6800 CPU
Logic of the MC6802 CPU Device
MC6802 CPU Signals and Pin Assignments
MC6870A Clock Device Pins and Signals
MC6871 A Clock Device Pins and Signals
MC6871 B Clock Device Pins and Signals
MC6875 Clock Device Pins and Signals
Logic of the MC6820 PIA
MC6820 PIA Signals and Pin Assignments
Functional Block Diagram for the MC6820 PIA
I/O Port A Control Register Interpretation
I/O Port B Control Register Interpretation
Logic of the MC6850 ACIA or MC6852 SSDA Devices
MC6850 ACIA Signals and Pin Assignments
MC6852 SSDA Signals and Pin Assignments
Data Flows Within an MC6852 SSDA
Logic of the MC6828 Priority Interrupt Controller
MC6828 Signals and Pin·Assignments
MC6840 CounterfTimer Signals and Pin Assignments
Logic of the MC6844 DMA Controller
MC6844 DrviA Controller Signafs and Pin Assignments
Timing for Three-State Control. Cycle Stealing Direct Memory Access with the MC6844
An MC6844 DMAC Connected for Three-State Control. Cycle Stealing Direct Memory
Access
Timing for Halt. Cycle Stealing Direct Memory Access with the MC6844
An MC6844 DMAC Connected for Halt. Cycle Stealing or Halt Burst Direct Memory
9-4
9-5
9-8
9-8.
9-10
9-11
9-12
9-14
9-15
9-16
9-32
9-33
9-34
9-35
9-39
9-40
9-40
9-41
9-46
9-47
9-48
9-52
9-52
9-56
9-57
9-62
9-64
9-71
9-35
9-36
9-37
Acce~~
9-72
9-79
9-107
9-108
9-111
9-112
9-114
9-115
9-38
9-39
Logic for MC6844 DMAC with Channel 3 Chained to Channel 0 and Data Flowing
into Alternate Memory Buffers
Logic of the MC684p Multifunction Device
MC6846 Multifunction Device Signals and Pi~ Assignments
9-120
9-125
9-126
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
Logic of MCS6500 Series CPU Devices
MCS6502 Signals andPin Assignments
MCSQ503 Signals and Pin Assignments
MCS6504 S!~nalsand Pin Assignments
MCS6505 Signals and Pin Assignments
MCS6506 Signals and pin Assignments
MCS6512 Signals and Pin Assignments
MCS6513 Signals and Pin Assignments
MCS6514 Signals and Pin Assignments
MCS6515 Signals and Pin Assignments
10-3
10-8
10-8
10-9
10-9
10-10
10-10
10-11
10-11
10-12
xxiv
LIST OF FIGURES (Continued)
pAGE
FIGURE
c
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0
Q.
a:
0
tJ
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all
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co
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10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
Time Base Generation for MCS650X CPU Input Clocks
Logic of the MCS6522 PIA
MCS6522 PIA Signals and Pin Assignments
Auxiliary Control Register Bit Assignments
Peripheral Control Register Bit Assignments
Logic of the MCS6530 and MCS6532 Multifunction Support Devices
Logic Provided by the MCS6530 Multifunction Device
MCS6530 Multifunction Device Signals and Pin Assignments
Logic Provided by the MCS6532 Multifunction Device
MCS6532 Multifunction Device Signals and Pin Assignments
10-17
10-29
10-31
10-32
10-34
10-48
10-49
10-50
10-53
10-54
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
Logic of the 2650A MicrocomplHer CPU
2650A CPU Signals and Pin Assignments
How Control Signals Identify Address and Data Bus Use for the 2650A Microcomputer
2650A-8080A Signal Equivalents
2650A-MC6800 Signal Equivalents
An 8251 USART Accessed by ci'2650A as an I/O Device
An 8251 USART Accessed by a 2650A as a Memory Device
An 8255 PPI Accessed by a 2650A as an I/O Device
An 8255 PPI Accessed by a 2650A as a Memory Device
Vectored Interrupt Using the 8214 PICU with a 2650A CPU
Synchronization Circuits in a 2650A-MC68XX Interface
An MC6850 ACIA Connected to a 2 6 5 0 A "
An MC6820 PIA Connected to a 2650A
Important Timing Considerations When Interfacing a 2650A CPU with MC68XX
Series Devices
11-2
11-9
11-13
11-24
11-24
11-25
11-25
11-26
11-26
11-27
11-28
11-29
11-29
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
Logic of the CDP1802 COSMAC CPU and the CDP1852 110 Port
CDP1802 COSMAC CPU Signals and Pin Assignmellts
COSMAC Machine Cycle Timing
COSMAC Memory Read Instruction Timing
COSMAC Memory Write Instruction Timing
COSMAC DMA-IN Machine Cycle
COSMAC DMA-OUT Machine Cycle
COSMAC I/O Data Input Instruction Execution Timing
COSMAC I/O Data Output Instruction Execution Timing
CDP1852 I/O Port Pins and Signals
CDP1852 I/O Port in Input Mode with Programmed Input
CDP1852 I/O Port in Input Mode with DMA Input
COP 1852 I/O Port in Output Mode with Programmed Output
CDP1852 I/O Port in Output Mode with DMA Output
12-3
12-6
12-8
12-10
12-11
12-12
12-13
12-15
12-16
12-32
12-35
12-36
12-38
12-39
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
Logic of the IM61 00 CPU and the IM61 01 Parallel Interface Element
IM61 00 CPU Signals and Pin Assignments
IM6100 Machine Cycles and Clock Periods
IM6100 Data Input Machine Cycle Timing
IM6100 Data Output Machine Cycle Timing
IM61 00 Memory Read Machine Cycle Timing
IM6100 Instruction Fetch Machine Cycle
Machine Cycle Timing for Memory Read from Indirectly Addressed Location
IM61 00 Memory Write Machine Cycle Timing
Machine Cycle Timing for Memory Write to Indirectly Addressed Location
Auto-Increment Machine Cycle for an IM61 00 Memory Reference Instruction that
Specifies Indirect Addressing with Auto-Increment
IM61 00 DCA Instruction Timing with I ndirect Addressing
IM61 00 DCA Instruction Timing with Indirect Addressing and Auto-Increment
13-2
13-7
13-8
13-10
13-11
13-12
13-12
13-13
13-14
13-15
13-12
13-13
xxv
11-30
13-15
13-16
13-17
LIST OF F~GURES (Continued)
PAGE
FIGURE
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-22a
13-23
13-24
13-25
13-26
13-27
13-28
13-29
13-30·
13-31
13-32
13-33
13-34
13-35
13-36
13-37
13-38
13-39
13-40
13-41
13-42
14~1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
IM61 00 I/O Data Input Machine Cycle
IM6100 I/O Data Output Machine Cycle
IM6100 I/O InstructionTiming
Wait States within an IM6100 Data Input Machine Cycle
Wait States within an IM61 00 Data Output Machine Cycle
An IM61 00 Halt State Initiated by Execution of a HL T Instruction
An IM61 00 Halt State Initiated and Terminated by the RUN/HL T Input
IM6100 DMA Initiation Timing
IM61 00 DMA Termination Timing
IM61 00 Interrupt Acknowledge Timing
Logic and Instruction Sequce for an IM61 00 Vectored Interrupt Acknowledge
IM61 00 OSR Instruction Timing
IM6100 DCA Instruction in Control Panel Memory-Timing with Indirect Addressing
IM61 00 Jump-to-Subroutine Instruction Timing with IndirectAddressing
IM6100 Jump-to-Subroutine Instruction Timing with Stack Access Logic
Using an External Stack Memory to Avoid IM6100 JMS ROM Problems,
IM6100 System Bus Converted to an 8080A-Compatible System Bus
IM6101 Parallel Interface Element Signals and Pin Assignments
LogicofthelM6101 PIE' ,
An IM61 01 I/O Read Instruction's Timing
An IM6101 I/O Write Instruction's Timing
Logic of the IM6102 MEDIC
IM61 02 MEDIC Signals and Pin Assignments
An IM61 00 Microcomputer System that Includes an IM61 02 MEDIC and IM61 01
PIE Device
'
Itvi61 02 Extended Memory Addressing Registers and Data Paths
IM61 00 DCA Instruction Timing with Direct Addressing Using Extended Memory
Addressing
IM6100 DCA Instruction Timing with Ind irect Addressing Using Extended Memory
Addressing
IM6100 DCA Instruction Timing with Indirect Addressing and Auto-Increment Using
.
Extended Memory Addressing
IM6102 DMA Read Timing
IM6102 DMA Write Timing
13-18
13-19
13-21
13-22
13-23
13-24
13-25
13-27
13-28
13-30
13~32
13-34
13-36
13-48
13-49
13-50
13-52
13-54
13-55
13-59
13-60
13~65
13-66
13-68
13-71
13-73
13-75
13-76
13-80
13-81
Logic of the 8X300 Microcontroller and 8T32/3/5/6
A Logic Overview of the 8X300 Microcontroller
8X300 Microcontroller Signals and Pin Assignments
An 8X300 Register-to-Register Instruction's Execution
An 8X300 IV Byte-to-Register Instruction's Execution
An 8X300 Register-to-IV Byte Instruction's Execution
An 8X300 IV Byte-to-IV Byte Instruction's Execution
8T32/3/5/6 Interface Vector Byte Signals and Pin Assignments
8T32/3/5/6IV Byte Control Signals and Interfaces .
8T32/3/5/6 IV Byte Address Programming Pulse
8T32/3/5/6 IV Byte Protect Programming Pulse
8T39 and 8T38 Bus Expander Signals and Pin Assignments
14-2
14-3
14-5
14-11
14-12
14-13
14-14
14-21
14-22
14-24
14-25
14-26
A National Semiconductor PACE Microcomputer System
A National Semiconductor INS8900 Microcomputer System
Logic of the INS8900 Microprocessor
INS8900 and PACE CPU Signals and Pin Assignments
INS8900 and PACE Data Input Timing
INS8900 and PACE Data Output Timing
Using the EXTEND Signal'to Lengthen I/O Cycles
INS8900 and PACE Initialization Timing
15-3
15-4
15-5
15-10
15-12
15-13
15-13
15-14
xxvi
LIST OF FIGURES (Continued)
FIGURE
Q
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0:
15-9
15-10
15-11
15-12
15-17
15-18
15-19
15-20
16-1
16-2
16-3
16-4
16-5
16-6
16-7 ,
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
Logic of the CP1600 CPU and CP1680 I/O Buffer
CP1600 CPU Signals and Pin Assignments
CP1600 Machine Cycles and Bus Timing
CP1600 Instruction Fetch Timing
CP1600 Timing for Memory Read Instruction with Implied Memory Addressing
CP1600 Timing for Memory Write Instruction with Implied Memory Addressing
CP1600 Wait State Timing
CP1600 DMA Timing
CP1600 Interrupt Service Routine Initialization
CP1600 Timing forTCllnstruction's Execution
CP1600 to 8080A Bus Conversion
CP1600 lOB Signals and Pin Assignments
A CP1600-CP1680 Microcomputer Configuration
PD1680 Handshaking with Data Input
PD1680 Handshaking for Data Output
16-2
16-7
16-9
16-9
16-10
16-11
16-12
16-14
16-14
16-15
16-26
16-28
16-29
16-34
16-35
17-1
17-2
17-3
17-4
Logic of the 1650 Series Microcomputers
1650 Functional Logic
1650 Series Microcomputer Bidirectional I/O Port Pin Logic
1650 Microcomputer Signals and Pin Assignments
17-2
17-3
17-4
17-7
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
18-17
18-18
18-19
18-20
Logic of the TMS 9900 CPU
TMS 9900 Signals and Pin Assignments
TMS 9900 Clock Periods and Timing Signals as Generated by the TIM 9904
A TMS 9900 Memory Read Machine Cycle
A TMS 9900 Memory Write Machine Cycle
Two TMS 9900 Output-to-CRU Machine Cycles
Two TMS 9900 Input-from-CRU Machine Cycles
TMS 9900 System Bus Utilization During I/O Operations
The TMS 9900 Wait State
TMS 9900 Hold State Timing
TMS 9900 Memory Map
A TMS 9900 Interrupt Acknowledge Pulse Generated Using an SBO Instruction
TMS 9900 Interrupt Acknowledge Generated by Decoding Valid Addresses
Logic of the TMS 9980A and TMS 9981 Microprocessors
TMS 9980A Signals and Pin Assignments
TMS 9981 Signals and Pin Assignments,
TMS 9980 Memory Map
Some TMS 9980A/TMS 9981 Interrupt Interfaces
Logic of the TMS 9940 Single-Chip Microcomputers
TMS 9940 Memory Map
18-2
18-14
18-16
18-16
18-17
18-21
18-22
18-24
18-24
18-25
18-28
18-33
18-33
18-46 '
18-47
18-48
18-51
18-52
18-53
18-54
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Terminating INS8900 or PACE Halt State
Timing Diagram for Processor Stall Using NHALT and CONTIN Si,gnals
Using PACE EXTEND Signal for Cycle-Stealing DMA
Idealized Circuit for Cycle-Stealing DMA During INS8900 and PACE Internal Machine
Cycles
Timing for Cycle-Stealing 'DMA During INS8900 and PACE Internal Machine Cycle
Internal View of INS8900 ,and PACE Interrupt System
Initiating INS8900 and PACE Level 0 Interrupt Using NHALT and CONTIN Signals
Circuit to Prevent ConflictsBetween PACE Level 0 Interrupts and Lower Priority
Interrupts
DP8302 System Timing Element (STE) Pins and Signals
Circuit to Generate Substrate Bias Voltage (VBB) for PACE CPU
BTE Signals and Pin Assignments
Signal Connections to Control BTE in a DMA System
15-13
15-14
15-15
15-16
15-15
15-16
15-17
15-18
15-19
15-20
15-23
15-25
15-35
15-36
15-36
15-37
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xxvii
LIST OF FIGURES (Continued)
FIGURE
18-21
18-22
PAGE
18-23
18-24
18-25
18-26
TMS 9940 Microcomputer Signals and Pin Assignments
Handshaking Logic in a TMS 9940 Multi-Microcomputer Network Communicating
via the TD Data Line
TIM 9904 Signals and Pin Assignments
Logic of the TMS 9.901 Programmable System Interface
TMS 9901 Programmable System Interface Signals and Pin Assignments
TMS 9901 PSI General Data Flows and CRU Bit Assignments
18-62
18-68
18-71
18-72
18-75
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
Logic of the Data General MicroNova and the Fairchild 9440
MicroNova CPU Signals and Pin Assignments
9440 CPU Signals and Pin Assignments
The Nova Arithmetic and Logic Unit
Arithmetic/Logic Instruction Object Code Interpretation
Load and Store Instruction Object Codes
Jump and Modify Memory Instruction Object Codes
General Input/Output Instruction Object Code Interpretation
Input/Output Skip Instruction Object Code Interpretation
CPU Device 3F 16 Input/Output Instruction Object Code Interpretation
CPU Device 1 Input/Output Instruction Object Code Interpretation
9440 Memory Read/Instruction Fetch Timing
,,
9440 Memory Write Timing
9440 I/O Data Input Timing
9440 I/O Data Output Timing
9440 Interrupt Acknowledge"lnstruction Execution Timing
9440 Mask Out Instruction Execution Timing
19-3
19-13
19-14
19-16
19-16
19-19
19-19
19-20
19-21
19-21
19-22
19-23
19-24
19-26
19-26
19-30
19-31
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12 '
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
Logic of the Intel 8086 CPW
8086 Programmable Registers
8086 Pins and Signal Assignments
Two 8086 Bus Cycles
8086 Memory Read Bus Cycle for a Minimum Mode System (MN/MX=+5V)
8086 Memory Write Bus Cycle for a Minimum Mode System (MN/MX=+5V)
8086 Memory or I/O Read Bus Cycle for a Maximum Mode System (MN/MX=OV)
8086 Memory or I/O Write Bus Cycle for a Maximum Mode System (MN/MX=OV)
The 8086 READY Input and Wait States
'
8086 HALT Instruction and Bus Cycle Timing for a Complex Bus Configuration
'
8086 Interrupt Vector
Logic of the 8284 Clock Generator and Driver
8284 Clock Generator and Driver Pins and Signal A.ssignments
Normal 8284 Clock Generator Circuit
Clock Synchronization Logic in a Multi-CPU 8086 Cpnfiguration
8288 Bus Controller Pins and Signal Assignments
8282 and 8283 Input/Output Port Pins and Signal Assignments
8286 and 8287 Bidirectional Bus Transceiver Pins and Signal Assignments
Generating a System Bus for a Simple 8086 Configuration
Generating a System Bus in an 8086 Microcomp~ier System Using an 8288 Bus
Controller
20-4
20-5
20-19
20-26
20-30
20-32
20-33
20-33
20-34
20-36
20-39
20-76
20-76
20-78
20-79
20-80
20-84
20-85
20-86
22-1
22-2
22-3
22-4
The 2901/6701 Arithmetic and Logic Unit
2901 ALU Logic
2909 Microprogram Sequencer Block Diagram
Four 2901 s in a 16-Bit CPU Using the 2902 for CarfY ~ook Ahead
22-2
22-3
22-6
22-9
23-1
23-2
23-3
MC1 0800 Series Devices in a Central Processing Unit Configuration
The MC1 0800 ALU Slice Functional Diagram
MC10803 Memory Interface Device Block Diawam
23-1
23-2
23-6
xxviii
18-58
20-88
LIST OF FIGURES (Continued)
FIGURE
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24-1
24-2
Logic of the Hewlett Packard MC2 Microprocessor
CPU and I/O Device Registers' Organization for the MC2
24-2
24-4
25-1
System Software Modules
25-6
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xxix
xxx
LIST OF TABLES
TABLE
Q
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TMS 1000 Series Microcomputer Summary
TMS 1000 Series Instruction Set Summary
1-1
1-12
2-1
2-2
2-3
2-4
2-5
2-6
3870/F8 Instruction Set Summary
Timing and ROMC States for F8 Instruction Set
3870/F8 Instruction Set Object Codes
ROMC Signals and What They Imply
Relationship Between Programmable Timer Contents and Effective Timer Counts
A Summary of Differences Between 3851. 3856. and 3857 PSUs
2-21
2-27
2-29
2-33
2-44
2-47
3-1
3-2
3-3
3-4
3-5
Status and Address Output via the Data Lines at the Beginning of an I/O Cycle
Statuses Output on the Data Bus for Various Types of Machine Cycles
SC/MP Instruction Execution Times
SC/MP Instruction Set Summary
SC/MP Instruction Set Object Codes and Execution Times
3-8
3-8
3-11
3-24
3-27
4-1
4-2
4-2
4-3
4-4
4-5
4-6
4-7
4-8
Devices of the 8080A Microcomputer Family
Statuses Output via the Data Lines During the Second Clock Cycle of an 8080A
Machine Cycle
Statuses Output on the Data Bus for Various Types of Machine Cycle
A Summary of 8080A/9080A Microcomputer Instruction Set
A S~mmary of Instruction Object Codes and Execution Cycles
A Summary of 8259 PICU Operations
TMS 5501 Address Interpretations
TMS 5501 Interrupt Logic and Priorities
4-11
4-11
4-27
4-32
4-66
4-70
4-74
5-1
5-2
A Summary of 8085A Instruction Object Codes and Execution Cycles
8155/8156 Device Port C Pin Options
5-32
5-38
6-1
6-2
6-3
A Summary of 8048 Series Microcomputers
A Summary of 8048 Microcomputer Instruction Set
8048 Series Instruction Set Object Codes
6-2
6-35
6-41
7-1
7-2
7-3
7-4
7-22
7-4
7-5
7-6
Comparisons of Z80 and 8080A Instruction Execution Cycles
A Summary of the Z80 Instruction Set
A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics
for Identical Instructions
Z80 PIO Interpretation of Control Signals
Z80 PIO Select Logic
Z80 PIO and 8255 Mode Equivalences
7-33
7-45
7-47
7-49
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
A Summary of the MC6800 Instruction Set
Operation Summary
MC6800 Instruction Set Object Codes
MC6820 Operating Modes
Addressing MC6820 Internal Registers
MC6852 Status Register Bit Set/Reset Conditions
MC6852 Interrupt Summary
MC6828 Address Vectors Created for Eight Priority Interrupt Requests
MC6828 Interrupt Masks - Their Creation and Interpretation
MC6840 Addressable Locations
A Summary of MC6840 Options and Control Register Settings
MC6844 DMAC Register Addresses
MC6844 DMAC Modes' Response Times and Transfer Rates
MC6846 I/O Addressable Locations
9-19
9-26
9-30
9-49
9-49
9-67
9-68
9-74
9-78
9-82
9-99
9-110
9-116
9-124
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1-1
1-2
xxxi
LIST OF TABLES (Continued)
TABLE
PAGE
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
A Comparison of MCS6500 Series and the MC6800 CPU Devices
A Summary of the MCS6500 Microcomputer Instruction Set
Summary of MCS6500 Object Codes, with MC6800 Mnemonics
Addressing MCS6522 Internal Registers
Summary of I/O Port A Handshaking Control Signals
A Summary of MCS6522 Interrupt Setting and Resetting
Addressing the MCS6530 Multifunction Support Logic Device
Addressing the MCS6532 Multifunction Support Logic Device
10-2
10-20
10-26
10-33
10-37
10-47
10-52
10-55
11-1
11-2
Summary of Signetics 2650A Instruction Set
Signetics 2650A Instruction Object Codes
11-17
11-22
12-1
12-2
COS MAC Instruction Set Summary
COSMAC Instruction Set Object Codes
12-26
12-31
13-1
13-2
13-3
13-4
13-5
13-37
13-40
13-46
13-57
13-6
IM6100 External Signal Sampling Priorities
IM61 00 Instruction Set Summary
IM61 00 Instruction Set Object Codes
IM61011nterpretation of I/O Instruction Control Bits 3-0
IM6102 MEDIC Pins that should be Tied to Power or Ground when Certain Functions
are Unused
IM6102 MEDIC I/O Instructions
14-1
14-2
14-3
14-4
14-5
14-6
8X300 Source and Destination Object Code Interpretations
8X300 Instruction Set
8X300 Instruction Set Object Codes
Interface Vector Byte Options
Specifications for Signals Illustrated in Figures 14-10 and 14-11
8T39 Bus Expander Addresses and IV Byte Addresses That May Be Connected
14-10
14-18
14-20
14-21
14-24
14-27,
15-1
15-2
15-3
15-4
15-5
INS8900 and PACE Instruction Set Summary
INS8900 and PACE Instruction Set Object Codes
Branch Conditions for INS8900 and PACE BOC Instruction
PACE BTE Truth Table
Comparing INS8900 System Busses to 8080A System Busses
15-27
15-31
15-33
15-37
15-44
16-1
CP1600 Bus Control Signals
CP1600 Instruction Set Summary
CP1600 Branch Conditions and Corresponding Codes
CP1600 Instruction Set Object Codes
16-8
16-18
16-23
16-24
1650 Series One-Chip Microcomputer Options
1650 Series Microcomputer Register Designations
A Summary of the 1650 Series Microcomputer Instruction Set
Mnemonics Recognized by the 1650 Assembler for Special Cases of General
Instru ctions
1650 Instruction Set Object Codes
17-1
17-5
17 -11
High-Order Address Bus Line Used by TMS 9900 I/O Instructions
TMS 9900 Instruction Set Summary
TMS 9900 Instruction Set Object Codes
A Summary of Differences Between the TMS 9900 and TMS 9980 Series
Microprocessors
A Summary of Differences Between the TMS 9980A and TMS 9981 Microprocessors
TMS 9980 Interrupts
TMS 9940 CRU Bit Address Assignments
TMS 9940 CRU Bits Whose Functions are Determined Under Program Control
18-23
18-38
18-43
16~2
16-3
16-4
17-1
17-2
17-3
17-4
17-5
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
xxxii
13-67
13-87
17-14
17-15
18-45
18-50
18-59
18-60
LIST OF TABLES (C~ntinued)
PAGE
TABLE
19-1
19-2
19-3
Nova System Bus Signals
MicroNova and 9440 Instruction Set Summary
MicroNova and 9440 Instruction Set Object Codes
19-11
19-35
19-40
20-1
20-2
20-3
20-10
20-47
20-4
20-5
20-6
20-7
A Summary of Intel 8086 Memory Addressing Options
8086 Branch-on-Condition Instructions
A Summary of Intel 8086 Memory Addressing Options Identified by the EA
Abbreviations in Table 20-3
The 8086 Instruction Set Summary
A Summary of 8086 Instruction Object Codes and Execution Cycles
8080A to 8086 Instruction Mapping
Effect of lOB. CEN. and AEN on Control Signals Output by the 8288 Bus Controller
20-50
20-51
20-68
20-74
20-82
22-1
22-2
22-3
2901 ALU Function Control
ALU Source Operand Control
ALU Destination Control
22-3
22-3
22-7
23-1
23-2
MC 10800 ALU Logical Operations
MC 10800 Arithl'T1etic Operations
23-3
23-4
ce(
e(
24-1
A Summary of the MC21nstruction Set
24-8
@
25-1
25-2
Some Typical Microcomputer Based Product and Development Costs
Unit Prices for Microcomputer Based Products
25-10
25-10
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xxxiv
QUICK INDEX
PAGE
INDEX
A
Address/Data Lines. Demultiplexing in the INS8900
After Sales Service
ALE Differences in 8085 and 8085A
ALE Generation in 8085 and 8085A
AMD 9080A Status Difference
Assembler
Assembler/Editor Combined
15-38
25-1
5-5
5-18
4-6
25-5
25-5
B
Bidirectional Transceiver Element (BTE)
BTE Mode Control Signals
Buffering SC/MP Busses
Bus Interface Unit (BIU). 8086
15-2
15-37
13-29
20-25
C
CALL Instruction. 8080A Interrupt Response Using
Chip Slice Logic. Carry Status and Overflow in
Chip Slice Logic. Sign Status in
Chip Slice Logic. Zero Status in
Context Switch. TMS 9900
Context Switch. TMS 9900 Backward
Context Switch. TMS 9900 Forward
CONTIN and NHALT Signals are Malfunctional
Continuing Engineering Costs
COSMAC Input/Output Programs
COSMAC Instruction Machine Cycle
COSMAC Interrupt Service Routine Programs
COSMAC Negative Set-up Time
COSMAC Nested Subroutine
COSMAC Timing Variations
Cost. Variable Contributing Factors
Costs. Variable
CPU Initiated DMA Block Data Transfers
CP1600 Direct Addressing
CP1600 Implied Addressing
CP1600 I/O Port Pin Characteristics
CP1600 PCIT Signal
CP 1600 Stack Addressing
Cycle-Stealing DMA During INS8900 and PACE Internal Machine Cycles
Cycle-Stealing DMA in PACE and INS8900 Systems
4-54
22-5
25-5
22-5
18-5
18-6
Debug
Demultiplexing the INS8900 Address/Data Lines
Demultiplexing the SC/MP Data Bus
DEND/IRO Signal. MC6844 DMAC
DGRNT. DMAC. TxSTB. TxAKA and TxAKB Signals. MC6844
DGRNT. TxRON. and DORT Signals. MC6844 DMAC
DMA and Multiprocessor Logic of the SC/MP
DMA Block Data Transfers Initiated by CPU
DMA Block Data Transfers Initiated by External Logic in PACE and .INS8900 Systems
DMA Control Sig'nals in IM6102
DMA. Cycle-Stealing. During INS8900 and PACE Internal Machine Cycles
DMA. Cycle-Stealing. in PACE and INS8900 Systems
DMA Modes in IM6102
DMA Priority Arbitration. MC6844 Fixed
DMA Programming in IM6102
DMA Registers in IM6102
DMAC. DGRNT. TxSTB. TxAKA. and TxAKB Signals. MC6844
DORT. DGRNT. and TxRON Signals. MC6844 DMAC
DROH Signal. MC6844 DMAC
25-8
15-38
3-30
9-113
9-114
9-112
3-1
15-16
15-17
13-79
15-18
15-17
13-83
9-11 q
13-83
13-79
9-114
9-112
9-114
Q
w
~
ct
ex:
0
Q.
ex:
0
u
~
enw
~
ct
g
(I)
(I)
ct
0/1
w
Z
ex:
0
CD
(I)
0
~
ct
Q
ct
@
D
xxxv
18~6
15-15
25-1
12-23
12-9
12-23
12-9
12-22
12-8
25-1
25-2
15-16
16-3
16-4
16-30
16-13
16-5
15-18
15-17
QUICK INDEX (Continued)
INDEX
PAGE
E (Cant.)
Editor
Editor/Assembler Combined
Enabling and Disabling INS8900 and PACE Interrupts
Execution Unit (EUl. 8086
Extend Used to Suspend INS8900 and PACE I/O During DMA Operations
Extended Memory. Base Page in IM6100
25-5
25-5
15-21
20-25
15-17
13-70
F
Fairchild F8 Device Set. The
Fixed Cost Contributing Factors
Fixed Costs
Floating INS8900 and PACE System Busses
F8 Device Set. The Fairchild
F8 Direct Memory Access
F8 DMI Memory Refresh
F8/3870 Accu mu lator
F8/3870 Data Counters
F8/3870 Program Counter
F8/3870 Scratchpad
F8/3870 Stack Register
2-1
25-1
25-2
15-15
2-1
2-53
2-52
2-5
2-6
2-6
2-6
2-6
G
Generating the PACE Substrate Bias Voltage
15-35
H
Halt State in 8085 and 8085A
Hold State in 8085 and 8085A
5-24
5-24
IM61 00 Base Page in Extended Memory
IM6100 Bit Numbering
IM6100 Clock Period Assignments
IM6100 Control Panel Switch Register
IM6100 Extended Memory Jump
IM6100 Extended Memory Subroutine Accesses
IM61 00-IM61 02 Interrupt Acknowledge
IM61 00-IM61 02 Reset Bootstrap
IM6100 Indirect Addressing with Auto-Increment Timing
IM6100 Indirectly Addressed Memory Read Cycle
IM61 00 Indirectly Addressed Memory Write Cycle
IM6100 Instruction Fetch Machine Cycle
IM61 00 Interrupt Processing Instructions
IM6100 Memory Fields
1fv1f31 00 Subroutines in Read-Only Memory
IMEl1 00 Vectored Interrupt Acknowledge
IM6101 Control Registers
IM6101 FLAG Instructions
IM6101 FLAG Outputs
IM61b1 Interrupt Acknowledge
IM6101 I/O lristructions
IM6101 Programming
IM61 01 Read Instruction
IM6101 ResetBootstrap
IM61Q1 Select Logic'
IM6101 Sense Inputs
IM6101 Sense Interrupt Priority
IM6101 SKIP Instructions
IM61 01 Write Operation
IM61 02 Data Field Register
IM6102 DMA Control Signals
IM6102 DMA Modes
IM6102 DMA Programming
13-70
13-7 '
13-10
13-33
13-77
13-77
13-70
13-70
13-14
13-13
13-14
13-13
13-31
13-70
13-5
13-32
13-58
13-61
13-58
13-70
13-58
13-56
13-58
13-70
13-56
xxxvi
1~-58
13-63
13-q1
13-5S
13-70
13-79
13-83
13-83
QUICK INDEX (Continued)
PAGE
INDEX
I (Cant.)
IM6102 DMA Registers
IM61 02 Extended Memory Addressing Registers
IM6102 Instruction Buffer Register
IM6102 Instruction Field Register
IM6102 Interrupt Acknowledge
IM61 02 Interrupt Vector Register
IM6102 Jump Across Memory Fields
IM6102 Reset Bootstrap
INS8900 and PACE CPU Registers During Interrupts. Saving
INS8900 and PACE. Cycle-Stealing DMA during Internal Machine Cycles
INS8900 and PACE Data Input Cycle
INS8900 and PACE Data Output Cycle
INS8900 and PACE Direct Addressing Options
INS8900 and PACE Direct Indexed Addressing
INS8900 and PACE Execution Speed
INS8900 and PACE Extend Signal for Slow I/O Operations
INS8900 and PACE. Extend Used to Suspend I/O During DMA Operations
INS8900 and PACE. Floating System Busses
INS8900 and PACE Halt State
INS8900 and PACE Interrupt Acknowledge and Return from Interrupt
iNS8900 and PACE Interrupt Pointers
INS8900 and PACE Interrupt Priorities
INS8900 and PACE Interrupt Response
INS8900 and PACE Interrupts. Enabling and Disabling
INS8900 and PACE Level 0 Interrupt Response
INS8~00 and PACE Logic Level
INS8900 and PACE Machine Cycle
INS8900 and PACE Machine Cycle Types
INS8900 and PACE Non-Maskable (Level 0) Interrupt
INS8900 and PACE Power Supply
INS8900 and PACE Processor Stall
INS8900 and PACE Signal Differences
INS8900 and PACE Split Base Page
INS8900 and PACE Split Base Page to Address I/O
INS8900 and PACE Stack Interrupts
INS8900 and PACE Systems. Cycle-Stealing DMA in
INS8900 and PACE Systems. DMA Block Data Transfers Initiated by External Logic
INS8900 and 8080A System Busses Compared
INS8900 Control Signal Polarity Considerations
INS8900. Demultiplexing the Address/Data Lines
INS8900 System. The 8212 Used as a Simple Input Port in an
INS8900 System. The 8212 Used as an Output Port in an
INS8900 System. 8255 PPI Devices Used in an
INS8900 Systems. The 8251 USART and 8253 Programmable CounterlTimer Used in
INS8900. Two 8255 Devices Used for 16-Bit I/O Ports with
INS8900. 6800 Support Devices Compatible with
INS8900. 8212 Used for Input with Handshaking in
Interrupt Differences in 8085 and 8085A
Interrupts During an MC6800 HALT
IRQ/DEND Signal. MC6844 DMAC
13-79
13-70
13-71
13-70
13-70
13-78
13-72
13-70
15-22
15-18
15-12
15-13
15-24
15-7
15-1
15-13
15-17
15-15
15-14
15-21
15-21
15-21
15-21
15-21
15-22
15-2
15-12
15-12
15-22
15-1
15-15
15-10
15-16
15-7
15-5.22
15-17
15-17
15-43
15-39
15-38
15-39
15-41
15-42
15-43
15-43
15-44
15-40
5-28
9-38
9-113
L
Label Table
Level 0 and Processor Stall Interrupt Similarities
Linking Loader
25-8
15-15
25-8
Q
w
~
o
D.
a:
o
a:
o
~
enw
~
g
en
en
ct
ell
w
Z
a:
o
III
en
o
~
ct
Q
ct
@
xxxvii
QUICK INDEX (Continued)
INDEX
M
PAGE
MCS6500 Slow Memory Interface
MCS6500 Wait State
MCS6522 Addressing
MCS6522 Interval Timer 1
tviCS6522 Interval Timer 1 Free Running Mode
MCS6522 Interval Timer 1 One-Shot Mode
MCS6522 Interval Timer 2
MCS6522 1/0 Port A Data Transfer
MCS6522 1/0 Port B Data Transfer
MCS6530 Addressing Logic
MCS6532 ~9dressing
MC6800 Bus State Controls
MC6800 Clock Signals
MC6800 Enable Signal Generation
MC6800 HALT. Interrupts During an
MC680Q Internal Operations Machine Cycle
MC6800 Interrupt Priorities
MC680d Machine Cycle
MC6800 Machine Cycle Types
MC6800 Non-Maskable Interrupt
MC6800 Normal External Interrupts
MC6800 Read Machine Cycle
MC6800 Reset
MC6800 Reset During Power-up
MC6800 Reset Operation
MC6800 Software Interrupt
MC6800 Stretching Address Timing
MC6800 SWllnstruction
MC6800 Synchronous HALT Generation
MC6800 Use of WAIT for DMA
MC6800 WAllnstruction
MC6800 Wait State
MC6800 Wait State with Slow Memory
MC680ti Write Machine Cycle
MC6820 Automatic Handshaking
MC6820 Control Codes
MCq820 Interrupt Logic
MC6820 Registers Addressing
MC6840 Continuous Mode
MC6840 Continuous Mode with 0 Initial Value
MC6840 Continuous 8-Bit Counting Square Wave Option
MC6840 Control Registers
MC6840 CounterlTimer Initialization
MC6840 Divide-by-Eight Clock
MC6840 Divide-by-Eight Mode
rviC6840 Event Counting
MC6840 External Signal Timing
MC6840 Frequency Comparison and Pulse Width Measurement Mode 5
MC6840 Hardware Initialization
MC6840lnterruptEnabie
MC6840 One-Shot Mode
MC6840 Output Signal Enable
MC6840 Programmed Initialization
MC6840 Status Register
MC6840 8-Bit Counting Mode
MC6840 16-Bit Counting Mode
MC6844 Channel Control Registers
xxxviii
10-15 .
10-14
10-31
10-39
10-41
10-40
10-41
10-33
10-35
10-48
10-54
9-6
9-7
9-44
9-38
9-9
9-13
9-7
9-7
9-13
9-13
9-7
9-13
9-15
9-15
9-13
9-42
9-13
9-45
9-16
9-16
9-16
9-9
9-8
9-53
9-51
9-51
9-49
9-100
9-103
9-103
9-94
9-79
9-95
9-103
9-104
9-80
9-1 b5
9-102
9-96
9-104
9-97
9-94
9-97
9-96
9-95
9-119
QUICK INDEX. (Continued)
INDEX
PAGE
M (Cant.)
MC6844 Data Chaining
MC6844 Data Chaining Control Register
MC6844 DMAC Address 8us
MC6844 DMAC Data 8us
MC6844 DMAC Device Select
MC6844 DMAC. DGRNT. TxST8. TxAKA andTxAK8 Signals
MC6844 DMAC DROH Signal
MC6844 DMAC Four-Channel Mode
MC6844 DMAC IRO/DEND Signal
MC6844 DMAC Two-Channel Mode
MC6844 DMAC TxAKA and TxAKB Signals
MC6844 DMAC. TxRON. DORT. and DGRNT Signals
MC6844 DMAC TxRO-TxR3 Signals
MC6844 DMAC TxSTB Signal
MC6844 DMAC <1>2 DMA Clock
MC6844 Enable/Priority Control Register
MC6844 Fixed DMAPriority Arbitration
MC6844 Interrupt Control Register
MC6844 Rotating Data Priority Arbitration
MC6846 Composite Status Register
MC6850 Control Register
MC6850 Interrupt Logic
MC6850 MODEM Control Signals
MC6850 Serial I/O Control Logic
MC6850 Serial I/O Data and Control Signals·
MC6850 System Reset
MC6852 Interrupt Logic
MC6852 Reset Operation
MC6852 Serialization Sequence
MC6852 Triple Data Buffers
Microcomputer Development Systems. Simple
Microcomputer Development Systems. Simulating
MicroNova I/O Bus
MicroNova Memory Bus
MODEM Control Signals
Monitor:
Motorola A and B Series Parts
Multiple Device Selects and Bus Loading (8085A)
Multi-8086 Clock Signals. Synchronizing
9-119
9-117
9-109
9-109
9-109
9-114
9-114
9-118
9-113
9-117
9-113
9-112
9-114
9-113.115
9-112
9-116
9-116
9-121
9-117
9-129
9-59
9-59 .
9-58
9-59
9-58
9-59
9-70
9-70
9-63
9-65
25-4
25-4
19-12
19-12
9-58
25-5
9-2
5-11
20-79
N
NEC 8080A External Interrupt Differences
NEC 8080A Hold Differences
NEC 8080Alnstruction Execution Time Differences
NEC 8080A Instruction Set Differences
NEC 8080A Interrupt Acknowledge Differences
NHALT and CONTIN Signals are Multifunctional
Nova Direct Memory Addressing
Nova Indirect Indexed Addressing
Nova Indirect Page Zero Addressing
Nova Indirect Program Relative Addressing
Nova I/O Device Address Space
Nova I/O Device Addressing
Nova I/O Device Busy and Done $tatus
Nova I/O Device Registers
Nova Multiple Indirect Addressing· •
4-24
4-17
4~33
4-24.
4-24
15-15
19-6
19-8
19-6
19-7
19-22
19-9
19-20
19-21
19-9
0
Object Programs. Relocatable
Overflow and Carry Status in Chip Slice Logic
25-7·
22-5 ..
cw
I~
a::
0
a.
a::
0
u
!:
en
w
I~
C3
0
en
en
~
clJ
w
za::
0
m
en
0
~
~
c
~
@
xxxix
.
.
QUICK INDEX (Continued)
PAGE
INDEX
P
PACE Address Latches and Decoders '
PACE and INS8900. Cycle-Stealing DMA during Internal Machine Cycles
PACE and INS8900 Data Input Cycle
PACE and INS8900 Data Output Cycle
PACE and INS8900 Direct Addressing Options
P~CE a'ld INS8900 Direct Indexed Addressing
PACE and INS8900 Execution Speed
PACE and INS8900. Extend Used to Suspend I/O During DMA Operations
PACE and INS8900. Floating System Busses
pACE and INS89dO Halt State
.
PACE and INS8900 Internjpt Acknowledge and Return from Interrupt
PACE and INS8900 Interrupt Pointers
PACE and INS8900 Interrupt Priorities
PACE and INS8900 Interrupt Response
PACE and INS8900lnterrupts. Enabling and Disabling
PACE and INS8900 Logic Level
PACE and INS8900 Machine Cycle
PACE and INS8900 Machine Cycle Types
PACE and INS8900 Non-Maskable (Level 0) Interrupt
PACE and INS8900 Power Supply
PACE and INS8900 Processor Stall
PACE and INS8900 Signal Differences
PACE and INS8900 Signal for Slow Operations
PACE and INS8900 Split Base Page
PACE and INS8900 Split Base Page to Address I/O
. PACE and INS8900 Stack Interrupts
PACE and INS8900 Systems Cycle-Stealing DMA
PACE and INS8900 Systems DMA Block Data Transfers Initiated by External Logic
PACE Clock Signals
.
PACE CPU and INS8900 Registers during Interrupts. Saving
PACE DP8302 STE Clock Frequency
PACE Level 0 Interrupt Problems
PACE Level 0 Interrupt. Return from
PACE MILE Used in an SC/MP System. The
PACE Stack Interrupt Problems
Preventing Simultaneous Selection of I/O and Memory on an 8085A
Preventing Transient Selection on an 8085A
Processor Stall and Level 0 Interrupt Similiarities
Program Linking
PSU Address Space
15-2
15-18
15-12
1~.. ~ 13
15"24
15:7
15-1
15-17
15~ 15
15-14
15-21
15-21
i 5-21
15-21
15-21
15-2
15-12
15-12
15-22
15-1
15-15
15-10
15-13
15-16
15-7
15-5.22
15-17
15-17
15-11
15-22
15-35
15-24
15-23
3-31
15-22
5-12
5-12
15-15
25-8
2-40
R
Read-Only Memory. IM6100 Subroutines in
Relocatable Loader
Relocatable Object Programs
Relocating Assembler
Reset. 8048. 8748. and 8035
Return from PACE Level 0 Interrupt
ROMC State
13-5
25-7
25-7
25-7
6-17
15-23
2-35
s
Saving INS8900 and PACE CPU Registers During Interrupts
SC/MP and SC/MP-II
SC/MP and SC/MP-II. Signal Differences Between
SC/MP Bus Access Control Signals
SC/MP Bus-Sharing Control Signals
SC/MP Busses. Buffering
SC/MP Control Techniques in Multiprocessor Applications
SC/MP Data Bus Definition Signals
15-22
3-3
3-5
3-6
3-17
3-29
3-19
3-7
xl
QUICK INDEX (Continued)
PAGE
INDEX
5 (Cant.)
cw
~
a:
oQ.
a:
o
u
~
enw
~
III(
g
(I)
(I)
III(
all
w
a:
Z
oCD
(I)
o
~
III(
c
III(
@
T
Select Problem with 8085
Service, After Sales
Sign Status in Chip Slice Logic
Simple Microcomputer Development Systems
Simulating Microcomputer Development Systems
Standard Memory Devices Connected to an 8048 Series Microcomputer
Subroutine Library
Suspension of an SC/MP 110 Cycle
Synchronizing Multi-8086 Clock Signals
System Timing Element
3-30
3-12
3-12
3-1
3-10
3-3
3-7
3-9
3-10
3-3
3-3
3-18
3-13
3-5
3-15
3-1
3-31
3-33
3-32
3-7
3-5
5-14
25-1
22-5
25-4
25-4
6-22
25-8
3-9
20-79
15-2
TMS 1000 Subroutines
TMS 5501 Nonstandard Features
TMS 5501 Output Signal Inversion
TMS 5501 Reset
TMS 5501 Wait State
TMS 9900 Backward Context Switch
TMS 9900 Context Switch
TMS 9900 Direct Addressing
TMS 9900 Forward Context Switch
TMS 9900 Implied Addressing
TMS 9900 Indexed Addressing
TMS 9900 Instruction Execution Sequences
TMS 9900 Internal Operations Machine Cycle
TMS 9900 Interrupt Vector Map
TMS 9900 Memory Addresses
TMS 9900 Multiple Interrupt Hardware Considerations
TMS 9900 Nested Interrupt Priorities
TMS 9900 Program Memory Addressing
TMS 9940 CRU Bit Utilization
TMS 9940 CRU I/O Expansion Mode
TMS 9940 HOLD Logic
TMS 9940 IDLE Logic
TMS 9940 Multiprocessor System Interface TMS 9940 Simple CRU 1/0 Mode
TMS 9940 Sync Mode
1-4
4-75
4-69
4-73
4-70
18-6
18-5
18-6
18-6
18-7
18-6
18-18
18-15
18-27
18-3
18-30
18-29
18-8
18-59
18-60
18-64
18-64
18-61
18-59
18-64
SC/MP Data Bus, Demultiplexing the
SC/MP Data Input Cycle
SC/MP Data Output Cycle
SC/MP DMA and Multiprocessor Logic
SC/MP ENOUT Signal Used to Establish Access Priorities·
SC/MP Instruction Execution Speed
SC/MP 110 Cycle Status Information
SC/MP 110 Cycle, Suspension of an
SC/MP 110 with Bus Access Logic Continuously Enabled
SC/MP Logic Level
SC/MP Memory Pages
SC/MP in Multiprocessor Systems
SC/MP NHOLD Signal for Slow 1/0 Operations
SC/MP (P-Channell and SC/MP-II (N-Channell, Signal Differences Between
SC/MP Return-from-Interrupt Technique
SC/MP Serial 110
SC/MP System, The PACE MILE Used in an
SC/MP System, The 8212 Used as an Output Port in an
SC/MP Systems, The 8212 I/O Port Used in
SC/MP Timing Control Signals
SC/MP-II (N-Channell and SC/MP (P-Channel), Signal Differences Between
xli
QUICK INDEX (Continued)
INDEX
PAGE
T (Cont.)
TMS 9980 Series Clock Logic
Transient Selection. Preventing on an 8085A
TTL Level PACE Bus
Two 8255 Devices Used for 16-Bit I/O Ports with INS8900
TxAKA and TxAKB Signals. MC6844 DMAC
TxAKA. TxAKB. DMAC. DGRNT. and TxSTB Signals. MC6844
TxAKB and TxAKA Signals. MC6844 DMAC
TxRON. DQRT and DGRNT Signals. MC6844 DMAC
TxRO-TxR3 Signals. MC6844 DMAC
TxR1 Signal. MC6844 DMAC
TxR2 Signal. MC6844 DMAC
TxR3 Signal. MC6844 DMAC
TxSTB Signal. MC6844 D
TxSTB Signal. MC6844 DMAC
TxSTB. TxAKA. TxAKB. DMAC. and DGRNT Signals. MC6844
18-49
5-12
15-2
15-43
9-113
9-114
9-113
9-112
9-114
9-114
9-114
9-114
9-113
9-115
9-114
u
Utilities
25-8
V
Variable Cost Contributing Factors
Variable Costs
25-1
25-2
w
Wait States during 8085 Interrupt Acknowledge
5-29
z-
Zero Status in Chip Slice Logic
Z80 Bus Control Signals
Z80 CPU Control Signals
Z80 Indexed Addressing
Z80 LSI Technology
Z80 System Control Signals
Z80 Wait States During Interrupt Acknowledge
1650 Accumulator
1650 Counter/Timer Logic
1650 I/O Pin Logic
1650 I/O Port Registers
1650 Program Counter
1650 Program Memory
1650 Stack17-6
1650 Status Register
1650 Timing
1650 VXX Power Supply
22-5
7-9
7-9
7-6
7-1
7-7
7-18
17-4
17-7
17-3
17-3
17-4
17-3
2650A Accumulator
2650A Branch Instruction Addressing
2650A Bus Access Control Signals
2650A Bus Contents Identification Signals
2650A CPU Execution Control Signals
2650A Extended Addressing Options
2650A External Device Control Signals
2650A Index Registers
2650A Interrupt Control Signals
2650A Memory Page Selection
2650A Memory Pages
2650A Program Counter
2650A Program Relative Addressing Options
2650A Stack
2901 ALU Operations Specification
2901 ALU Source Specification
11-3
11-7
11-11
11-11
11-11
11-6
11-12
11-3
11-12
11-8
11-3
11-3
11-4
11-4
24-4
22-4
xlii
17-5
17-8
17-8
QUICK INDEX (Continued)
PAGE
INDEX
cw
~
a:
oQ.
a:
o(J
~
en
w
~
g
CI)
CI)
oct
a1:I
w
Z
a:
o
en
2-10
2-7
2-17
2-3
2-7
. 2-13
2-16
2-6
2-16
2-8
2-10
2-6
2-5
2-6
2-6
2-6
2-6
3870 Clock Logic
3870 Direct Scratchpad Addressing
3870 Event Counter Mode
3870 Expansion
3870 Implied Scratchpad Addressing
3870 Interrupt Disable
3870 Interval Timer Mode
3870 Memory Addressing
3870 Pulse Width Measurement Mode
3870 r Scratchpad Addressing
3870 Reset
3870 Scratchpad Memory Addressing
3870/F8 Accumulator
3870/F8 Data Counters
3870/F8 Program Counter
3870/F8 Scratchpad
3870/F8 Stack Register
CI)
o
~
oct
C
oct
@
6800 Support Devices Not Compatible with INS8900
8T32 IV Byte Access Logic
8T32 IV Byte Addressing
8T32 IV Bytes
8T33 IV Byte Access Logic
8T33 IV Byte Addressing
8T33 IV Bytes
8T35 IV Byte Access Logic
8T35 IV Byte Addressing
8T35 IV Bytes
8T36 IV Byte Access Logic
8T36 IV Byte Addressing
8T36 IV Bytes
8X300 Data and I/O Addressing
8X300 Program Memory Addressing
. 8X300 Rotate and Mask Logic
8X300 Shift and Merge Logic
8035.8048. and 8748 Reset
8041 Buffer Status Register
8048 and 8748 Debug Mode
8048 Series External Memory Access Mode
8048 Series Internal Execution Mode
8048 Series 1/0 Port Pin Logic
8048 Series I/O Ports
8048 Series Machine Cycles and Clock Periods
8048 Series Memory Spaces
8048 Series Microcomputer. Standard Memory Devices Connected to an
8048 Series Microcomputer. 8355 or 8755 Connected to an
8048 Series Program Memory Addressing
8048 Series Single Stepping
8048 Series Verify Mode
8048 Wait State
8048.8748. and 8035 Reset
8049 Series Microcomputers
8080A and INS8900 System Busses Compared
8080A and 8086 Registers' Compatibility
8080A Carry Status Borrow Logic
8080A Carry Status Nomenclature
xliii
15-44
14-23
14-4
14-4
14-23
14-4
14-4
14-23
14-4
14-4
14-23
14-4
14-4
14-4
14-4
14-7
14-8
6-17
6-44
6-15
6-14
6-14
6-5
6-5
6-18
6-8
6-22
6-22
6-8
6-15
6-15
6-20
6-17
6-3
15-43
20-3
4-5
4-26
QUICK INDEX (Continued)
INDEX
PAGE
SOSOA Clock Periods
SOSOA Data Bus Definition Signals
SOSOA Direct Addressing
SOSOA Implied Addressing
SOSOA Instruction Status
SOSOA Interrupt Control Signals
S080A Interrupt Response Using CALL Instruction
SOSOA Machine Cycles
S080A Slow Memories
SOSOA Timing Control Signals
SOSOA Wait State Request Logic
SOS5 and SOS5A
SOS5 and SOS5A. ALE Differences in
SOS5 and SOS5A. ALE Generation in
SOS5 and SOS5A. Halt State in
SOS5 and SOS5A. Hold State in
SOS5 and SOS5A. Interrupt Differences in
S085 Interrupt Acknowledge
SOS5 Interrupt Acknowledge. Wait States During'
SOS5 I/O Write Timing
SOS5 Memory Read Timing
S085 Memory Write Timing
SOS5 Multibyte Acknowledge
SOS5. Select Problem with
SOS5A and SOS5
SOS5A and SOS5. Halt State in
S085A and SOS5. Interrupt Differences in
SOS5A Bus Control Signals
SOS5A Bus Idle Machine Cycle
SOS5A Clock Periods
SOS5A Control Signals
SOS5A Data Bus Definition Signals
SOS5A Device Select Logic
SOS5A Hold Within a Halt State
SOS5A Interrupt Acknowledge
SOS5A Interrupt Signals
SOS5A Machine Cycles
SOS5A Multibyte Acknowledge
SOS5A Multiple Device Selects and Bus Loading
SOS5A. Preventing Simultaneous Selection of I/O and Memory onan
SOS5A. Preventing Transient Selection on an
SOS5A Reset Signals
SOS5A RIM after TRAP
SOS5A Serial I/O
SOS5A TRAP Interrupt
SOS6 and SOSOA Registers' Compatibility
SOS6 AX Register
SOS6 Base Relative Indexed Addressing
SOS6 BCD Addition
SOS6 BCD Division
SOS6 BCD Multiplication
SOS6 BCD Subtraction
SOS6 Bus Interface Unit (BIU)
S086 BX Register
SOS6 Code Segment Register and Program Counter
SOS6 Complex Control Signals
SOS6 CX Register
xliv
4-7
4-7
4-5
4-4
4-10
4-7
4-54
4-7
4-13
4-6
4-14
5-1
5-5
5-1S
5-24
5-24
5-2S
5-29
5-29
5-16
5-15
5-16
5-29
5-14
5-1
5-24
5-2S
5-5
5-1S
5-S
5-5
5-5
5-10
5-27
5-29
5-5
5-7
5-29
5-11
5-12
5-12
5-5
. 5-31
5-5
5-31
20-3
20-3
. 20-13
20-43
20-45
20-45
20-43
20-25
20-3
20-7
20-24
20-5
QUICK INDEX (Continued)
PAGE
INDEX
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8086 Data Memory Base Relative Addressing
8086 Data Segment and Stack Segment Registers
8086 Direct Indexed Addressing
8086 Direct Memory Addressing
8086 OX Register
8086 Execution Unit (EU)
8086 External Memory Addressing
8086 Extra Segment. Source Index and Destination Index Registers
80~6 HOLD in Maximum Mode System
8086 HOLD in Minimum Mode System
8086 Implied Memory Addressing
80~6 Indirect Addressing
808p Instruction Queue
8086 Interrupt Return
8Q~6 Interrupt Vector Table
80861/0 Port Addressing
8086 Maskable Interrupt
8086 Non-Maskable Interrupt
8086 Program Relative Addressing
8086 Reset
8086 Segment Registers
8086 Simple Control Sgnals
8086 Single Instruction Time Identified
8086 Software Interrupts
8086 Stack Segment and Stack Pointer Registers
8155 Device Reset
8155/8156 I/O Mode 0
8155/8156 I/O Mode 1
8155/8156 I/O Port Addresses
8155/8156 Timer Mode 0
8156/815p I/O Mode 0
8156/8155 VO Mode 1
8156/81551/0 Port Addresses
8212 I/O Port Used in SC/MP Systems. The
8212 Used as a Simple Input Port in an INS8900 System. The
8212 Used as an Output Port in an INS8900 System. The
8212 Used as an Output Port in an SC/MP System. The
8212 Used in an INS8900 System for Input with Handshaking. The
8224 Clock Signals
8243 Reset
8251 USART and 8253 Programmable CounterlTimer Used in INS8900 Systems. The
8253 Programmable CounterlTimer and 8251 USART Used in INS8900 Systems
8255 Devices Used for 16-Bit I/O Ports with INS8900
8255 PPI Devices Used in an INS8900 System
8259 PICU Interrupt Mask
8259 PICU Interrupt Masking
8259 PICU Interrupt Service Routine Priorities
8259 PICU Polling
8259 PICU Rotating InterruptPriorities
8284 Wait State Logic
8288 Advanced Write Control Signals
8288 Bus Controller Interrupt Signals
8288 Bus Controller Memory Protect
8288 I/O Bus Mode
8355 or 8755 .cQnnected to an 8048 Series Microcomputer
8748 and 8048 Debug Mode
8748 Programming Mode
xlv
20-13
20-9
20-12
20-11
20-5
20-25
20-20
~0-8
20-35
20c35
20-12
20-17
20-25
20-41
20-39"
20-17
20-39.40
20-39.40
20-17
20-23.79
20-6
20-24
20-38
20-38.40
20-8
5-38
5-38
5-38
5-40
5-42
5-38
5-38
5-40
3-32
15-39
15-41
3-33
15-40
4-46
6-53
15-43
15-43
15-43
15-42
4-63
4-59
4-57
4-59
4-58
20-79
20-81
20-82
20-82
20-81
6-22
6-15
6-15
QUICK INDEX (Continued)
INDEX
PAGE
8748.8048. and 8035 Reset
8755 and 8755A
8755 or 8355 Connected to an 8048 Series Microcomputer
8755A and 8755
6-17
5-51
6-22
5-51
9080A AMD Status Difference
9440 Instruction Fetch
9440 Memory Read
9440 System Bus
4-6
19-23
19-23
19-14
xlvi
INTRODUCTION
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This is the first of two volumes that replace An Introduction to Microcomputers: Volume 2 - Some Real Products. This volume describes microprocessors and dedicated support devices. Volume :3 de~cribes general support devices.
We define a "dedicated" support device as one best used with its parent microprocessor. We define a
"general" support device as one which can be used w~th any microprocessor.
Unfortunately, categorizing support devices as "dedicated" or "general" is not always straightforward. Certainiy IM6100 and TMS9900 support devices have' CPU interfaces which ara peculiar to the parent
microprocessor, so using them with other microprocessors makes little sense. Most MC6800 microprocessor
support devices are also considered dedicated because they use the MC6800 clock signal. This clock signal is
automatically generated by an MC6800 microprocessor or its clock device. It can be derived quite inexpensively in other microcomputer systems; nevertheless, we include MC6800 support devices in Volume 2,
because in our opinion the added clock logic is not compensated for by any performance capabilities over and
above those which you would find in a competing device that did not require the added clock logic.
When reading Volumes 2 and 3, therefore, you should bear in mind that we have had to be subjective when
deciding whether some parts should be described in Volume 2 or Volume 3. Dp not automatically use support
parts described in Volume 2 without checking equivalent parts described in Volume 3. Conversely, there may
be instances where your application is better served by a support device described in Volume 2. In general, you
can look upon Volume 3 support devices as CPU-independent, while Volume 2 devices are CPU-dependent.
In order to cope with the rapid evolution of new parts, Volumes 2 and 3 have been printed loose-leaf. Each
volumo will have six updates per year, appearing at bimonthly intervals. For Volume 2, updates will appear in
November, January, March, May, July and September. Each Septembor the entire book will be reprinted, including the past year's updates. If you have inserted your updates, you will not need to buy a new book next
year. For your convenience, an order form may be found at the back of this book.
SIGNAL CONVENTIONS
Signals may be active high, active low or active in two states. An active high signal is one which, in the high
state, causes events to occur, while in the low state has no significance. A signal that is active low causes
events to occur when in the low state, but has no significance in the high state. A signal that has two active
states will cause two different types of events to occur, depending upon whether the signal is high or low; this
signal has no inactive state. Within this book a signal that is active low has a bar placed over the signal name.
For example, WR identifies a "write strobe" signal which is pulsed low when data is ready for external logic to
receive. A signal that is active high or has two active states has no bar over the signal name.
TIMING DIAGRAM CONVENTIONS
Timing diagrams play an important part in the description of any microprocessor or support device. Timing
diagrams are therefore used extensively in this book. All timing diagrams observe the following conventions:
1)
A low signal level is equivalent to no voltage. A high signal level is equivalent to voltage present:
No voltage
I
xlvii
Voltage present
2)
A single signal making a low-to-high transition is illustrated like this:
low
3)
A single signal making a high-to-Iow transition is illustrated like this:
high
4)
high
I
\
low
When two or more parallel signals exist. the notation:
r-
signals change
l
states that one or more of the parallel signals change level. but the transition (high-to-Iow or low-to-high) is
unspecified.
5)
A three-state single signal is shown floating thus:
~-------~
Signal
floating
6)
.
A three-state bus containing two or more signals is shown floating thus:
______~r---~~---i~----floating
7)
J
When one signal condition triggers other signal changes. an arrow indicates the relationship as follows:
co~:~on
Causes
change
here'
Thus a signal making a low-to-high transition would be illustrated triggering another signal making a high-to-Iow
transition as follows:
A signal making a high-to-Iow transition triggering a bus change of state would be illustrated as follows:
~xlviii
8)
When two or more conditions must exist in order to trigger another logic event. the following illustration is used:
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Thus a low-to-high transition of one signal occurring while another signal is low would be illustrated triggering a
third event as follows:
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When a single triggering condition causes two or more events to occur. the following illustration is used:
@
This
con,dition
j'
causes
these
changes
Thus a low-to-high transition of one signal triggering changes in two other signal levels would be illustrated as
follows:
10)
All signal level changes are shown as square waves. Thus rise and fall times are ignored. These times are given in
the data sheets which appear at the end of every chapter.
INSTRUCTION SET CONVENTIONS
Every microcomputer instruction set is described with two tables. One table identifies the operations which occur when the instruction set is executed, while the second table defines object codes and instruction times.
Because of the wide differences that exist between one instruction set and another, we have elected not to
use a single set of codes and symbols to describe the operations for all instructions in all instruction sets. We
believe any type of universal convention is likely to confuse rather than clarify; therefore each instruction set
table is preceded by a list of symbols as used within that table alone.
A short benchmark program is given to illustrate each instruction set. Some comments regarding benchmark
programs in general are, however, in order. We are not attempting to highlight strengths or weaknesses of
different devices, nor does this book make any attempt at comparative analyses, since the criteria which make
one microcQmputer better than another are simply too dependent on the application.
xlix
ATTENTION WRITERS
Osborne & Associates is seeking qualified contributors to future updates of Volumes 2 and 3.
Qualified contributors must have an excellent technical background, they must be able to write clearly,
'and they must be unaffiliated with any manufacturer of semiconductor devices. Faculty at universities
are particularly welcome as contributors.
A contributor, when selected, will be assigned a specific category of parts to keep updated. Keeping parts updated will include describing new parts iIi the category as they appear, and improving the
description of parts that are aiready covered.
If you would like to become a contributor to Volume 2 and/or Volume 3, please write stating your
qualifications and the categories of parts that you believe you could cover competently. If possible, send
us a sample of your work; we suggest two or three pages of a part description following the format presented in these books as closely as possible. Send material to:
OSBORNE &: ASSOCIATES, INC.
P.O. Box 2036
Berkeley, California 94702
Attention: Volume 2/3 Contributors
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Chapter 1
4-BIT MICROPROCESSORS AND THE TMS1000
SERIES MICROCOMPUTERS
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The earliest microprocessors were all 4-bit devices: that is to say. data was operated on in 4-bit units. frequently referred to as "nibbles". Early microprocessors were 4-bit devices simply because the concept of an LSI CPU was ambitious enough; starting with an a-bit CPU would have been foolhardy.
But LSI technology has advanced so rapidly that there is an inconsequential difference between the cost of manufacturing an 8-bit CPU chip as against a 4-bit chip. Manufacturers attempted to maintain an artificial price differential bet. ween their 4-bit and 8-bit CPUs in order to prolong the life of the 4-bit product: but the pressure of competition has all
but extinguished these price differentials - with the result that the 4-bit microprocessor is a dying product. Price is the
only advantage that 4-bit microprocessors offer when compared to the more capable 8-bit microprocessor.
Early 4-bit microcomputers included such devices as the Intel 4004 and 4040 and the National Semiconductor IMP-4.
These early 4-bit microcomputers require package counts that exceed typical 8-bit microcomputers that are now
available: therefore the economics of today dictate that the Intel 4004, the Intel 4040 and the IMP-4 offer less
capability for more money. Only the most unusual application could be more economically implemented using one of
these three 4-bit microcomputers. rather than a simple 8-bit device such as the 3870. COSMAC. 8048. or one of the
38-pin MCS6500 series CPUs. We consider the Intel 4004, the Intel 4040 and the IMP-4 to be obsolete devices;
therefore they are not described.
It is interesting to note that even though these three 4-bit microcomputers are obsolete. they will continue to have a
significant market for many years to come. based on products that were designed around them before they became obsolete. The fact that they are obsolete simply means that. were you to design a new product today. you would be better
off using one of the simple 8-bit microcomputers. That does not mean it would be economical to redesign a product
that already exists. simply to take advantage of more recent microcomputer developments. The cost of re-engineering
around a new microcomputer will likely overwhelm any savings that may accrue.
The TMS1000 series microcomputer devices, initially manufactured by Texas Instruments, are still economically very viable - even though they are 4-bit devices. This is because the TMS 1000 is a one-chip microcomputer. ROM, RAM, CPU. and I/O logic are all provided within a single package. The low cost associated with the
single-chip TMS 1000 microcomputer package makes this the product of choice for a large number of simple applications that can be accommodated within the logical confines of the TMS 1000.
In reality, the TMS 1000 is a family of six 4-bit microcomputers whose differences are summarized in Table 1-1.
The various microcomputers are sufficiently similar for us to describe them together. PMOS and CMOS versions
are now available. Some CMOS versions manufactured by Motorola have the part number MC 141 000.
Table 1-1. TMS1000 Series Microcomputer Summary
·TMS
1000
Package Pin Count
ROM Program Bytes'
RAM Data Nibbles"
28
1024
64
R Signal Outputs
o Data Outputs
Maximum Rated Voltage
Typical Power Dissipation
.
A Byte
IS
eight bits
..
TMS
1200
TMS
1070
TMS
1270
TMS
1100
TMS
1300
TMS
1000C
TMS
1200C
40
1024
28
1024
64
40
1024
64
28
2048
128
40
2048
40
1024
128
28
1024
64
11
13
10
11
16
10
16
8
20
8
20
8
6
15V/
90mW
15V/
90mW
5V/
15mW
8
6
5V/
5mW
11
64
13
8
20
8
20
15V/
90mW
15V/
90mW
A Nibble
IS
8
35
15V/
90mW
35
15V/
90mW
four bits
1-1
64
MC
MC
141000 141200
28
1024 .
40
1024·
64
11
64
16
8
6.5
8
6.5
5V/ .
2.5mW
3V/
0.5mW
5V/
2.5mW
3V/
0.5mW
Figure 1-1 illustrates that part of our .general microcomputer system logic which is implemented by the
TMS1000 series microcomputers. This figure is deceptive, since it would be hard to compare the primitive I/O
capabilities of the TMS1000 with a device such as the 8255 Programmable Peripheral Interface device, which
is described in Volume III. Nevertheless, Figure 1-1 does indicate the logic which is provided by a TMS1000
series microcomputer, albeit in a primitive form.
Logic to Handle
Interrupt Requests
from
External Devices
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I······.
C
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I··
I.·. .·.
1\
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Stack Pointer
d.
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Interrupt Priority
Arbitration
rj
. I.··.•
~.··i
.................
"i.e;
i
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............ · . •···.ii•.•·<
Ii
...•....
I/O Communication
Serial to Parallel
Interface Logic
Direct Memory
Access Control
Logic
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.......
.......
\
.....
•....
L.:. ia
........•
~
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.:.....
.....
.......
Programmable
Timers
,'"
f
Figure 1-1. Logic of the TMS 1000 Series Microcomputer
The fact that the TMS1000 series microcomputers are single-chip devices has a number of secondary, non-obvious implications. Most ifTiportant of all, there are no such things as support devices. The 1024 or 2048 bytes of ROM
represent the exact amount of program memory which will be present; there can be neither more nor less. Similarly,
the 64 or 128 nibbles of RAM cannot be expanded. Direct memory access logic is not present - and its presence
would make very little sense anyway; with the small total ROM and RAM memory available, there simply is not the opportu~ityto transfer blocks of data long enough to warrant bypassing the CPU.
Interrupts, similarly, would be of marginal value to a TMS1000 microcomputer. Given the small amount of program
memory available and the very low cost of the package, it would be hard to justify the complexities of interrupt logic,
simply to have the microcomputer perform more than one task.
All devices of the TMS 1000 microcomputer family are implemented using PMOS technology. Selected CMOS parts are
also available.
.
1-2
A single -15V power supply is required for PMOS parts. CMOS parts use power supplies in the range +3V to +6.5V.
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The fastest clock frequency which can drive a TMS 1000 series microcomputer has a 2.5 microsecond cycle time. All instructions execute in six clock cycles. or 15 microseconds: but beware of making direct execution speed comparisons
between the TMS 1000 and the 8-bit microcomputers which are described next. A TMS 1000 program will usually be
considerably longer than the 8-bit microcomputer equivalent because the TMS 1000 instruction set is more primitive:
but this is not always true. It is possible for the TMS1000 instruction set to equal or surpass many 8-bit
microprocessors. in terms of instruction efficiency. for certain control applications.
The prime manufacturer of the TMS 1000 is:
TEXAS INSTRUMENTS. INC.
P.O. Box 1443
Houston. Texas 77001
A second source for CMOS parts with MC 14xxxx part numbers (see Table 1-1) is:
MOTOROLA INCORPORATED
CMOS Products Division
3501 Ed Bluestein Blvd.
Austin. Texas 78721
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TMS1000 PROGRAMMABLE REGISTERS
TMS 1000 programmable registers may be illustrated as follows:
4-bit Accumulator
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2- or 3-bit X register
}
6- or 7-bit Data Counter
4-bit Y register
6-bit Program Counter
4-bit Page register
1-bit Chapter flag (optional)
6-bit Subroutine Return register
4-bit Page Buffer register
Apart from being only four bits wide. the Accumulator is a typical primary Accumulator. It is the principal source and
destination for data that is being operated on.
1-3
Taken together. the X and Y registers constitute a 6- or 7-bit Data Counter which addresses the 64 or 128 nibbles
of RAM. The X register is two or three bits wide and theY register is four bits wide. Since the Xand Y registers are indeed separate and distinct registers. RAM is effectively divided into four or eight pages. each of which is 16 nibbles
.
long. A four-page RAM may be illustrated as follows:
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10
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The Y register, in addition, serves as a secondary Accumulator'and ari output Address register. We will describe
its use as an output Address register shortly.
Those TMS 1000 series microcomputers that provide 128 nibbles of RAM have a 3-bit X register. RAM is then divided
into eight 16-nibble pages.
The Program Counter and Page Address register, taken together, constitute a 10-bit Program Counter. They are.
in reality. separate and distinct registers. with the result that program memory is divided into sixteen 64-byte pages.
ThoseTMS1000 microcomputers that provide 2048 bytes of program memory have an additional 1-bit flag,
referred to as Chapter Logic, which is used to select one of two alternate 1024-byte ROM chapters.
TMS 1000
The Subroutine Return register is simply a buffer for the Program Counter register. Similarly,
the Page Buffer register is a simple buffer for the Page Address register. These two buffer
SUBROUTINES
registers allow the TMS1 000 a single level of subroutine call logic. When a subroutine is called,
the contents of the Page Address and Page Buffer registers are exchanged. the Program Counter register contents are
moved to the Subroutine Return register. and a new value provided by the subroutine Call instruction is loaded into the
Program Counter. This may be illustrated as follows:
I
,-.-._~I_-'-.....I~~_""--,,,_...
Instruction object code
: :d~: : :g;,: ~ ItY1cc I 1=0
1-4
Subroutine Return register
Page Buffer register
TMS1000 MEMORY ADDRESSING MODE
TMS1000 microcomputers have separate and distinct program and data memories. There are no instructions
capable of writing into program memory. and data memory cannot contain instruction object codes.
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Data memory is accessed using implied addressing. The X and Y registers combine to serve as a Data Counter: we
have just described this Lise of the X and Y registers.
Only subroutine Call instructions and Branch instructions address program memory. These instructions address
program memory using variations of absolute, paged direct addressing. .
We have already
illustrate~
the addressing logic of a subroutine call.
A Branch instruction loads the Program Counter with a new address. which is provided by the instruction. just as a Call
instruction does. If the Branch instruction occurs in a subroutine - that is. in the sequence between a subroutine Call
instruction and a subroutine Return instruction - the Page Address register will not be affected. However. execution
of a Branch instruction outside a subroutine will load the Page Address register from the Page Buffer register. The two
types of program branches may be illustrated as follows:
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Page Buff"'eg;",,
Only if Branch OS;curs
outside a subroutine
TMS1000 STATUS FLAGS
The TMS 1000 series microcomputers have a single status flag which combines to serve as a Carry status and a
simple logic decision stat'us. All Branch and subroutine Call instructions are conditional; the Branch or subroutine
Call occurs only if the status flag is 1.
The unique feature of the status flag as compared to most status logic is that its passive level is high (1). If an instruction causes the status flag to be reset to 0, it will revert to 1 after a single instruction cycle:
R~'~
CLOCK
STATUS
--+---~t:
"_~II-
Instruction
____"'"
I
Instruction
Instruction
I
2
3
Instructions that test the condition of the status flag must directly follow the instruction which modifies the level of the
status flag.
TMS1000 INPUT AND OUTPUT LOGIC
The only data input to a TMS1000 series microcomputer occurs as 4-bit nibbles, referred to in Texas Instruments literature as K inputs. Instructions that access the K inputs simply input whatever signal levels exist at the time
of the access.
TMS 1000 series microcomputers output data referred to as 0 outputs, and control signals referred to as R outputs.
1-5
There are eight data or 0 outputs: but they are created in an unusual way. 0 output logic receives, as inputs, the contents of the Accumulator, plus the status flag. These five data bits create the eight 0 output signals according to a
matrix which you must define when you order the TMS 1000 microcomputer. This may be illustrated as follows:
Accumulator {
Contents
o Output
o outputs
Matrix
Status flag
As the illustration above would imply, the five inputs select 32 of the possible 256 signal combinations which can be
output via the eight 0 outputs.
The control R outputs are treated as 11, 13 or 16 single control signals. Refer to Table 1-1, which identifies the number
of R output signals available with each of the TMS 1000 series microcomputers. You can set or reset R output signals
individually. The Y register is used to identify the individual R signal which is being set or reset.
TMS1000 SERIES MICROCOMPUTER PINS AND SIGNALS
Figures 1-2 through 1-7 illustrate the pins and signals of the TMS1000 series microcomputers. Note that the
TMS 1000 and TMS 1100 microcomputers have identical pins and signals. Since signals are consistent for the entire
family of microcomputers, they will be described together.
The four data inputs are provided by K1, K2, K4 and K8. We would name these signals 010, OIL 012 and 013 to be
consistent with common microcomputer terminology: however. Texas Instruments literature uses the signal names K 1,
K2, K4 and K8 to represent the binary level of each signal.
R8
R9
RlO
(VSS in MC141000) VDD
K1
K2
K4
K8
INIT
07
06
05
04
03
3
4
5
6
7
8
9
10
11
12
13
14
TMS1000
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R7
R6
R5
R4
R3
R2
R1
RO
Vss (VDD in MC141000)
OSC2
OSC1
00
01
02
Pin Name
Description
Type
K1. K2, K4. K8
00- 07
RO - R10 .
OSC1,OSC2
INIT
VDD, VSS
Data input
Data output
Control output
Timing
Power on reset
Power and Ground
Input
Output
Output
Input'
Input
Figure 1-2. TMS1000 and MC141000 Microcomputer Signals and Pin Assignments
1-6
R8
R9
1
2
3
4
5
6
7
RlO
Q
w
!ia:
oD..
a:
o
u
~
en
w
l-
R11
R12
(VSS in MC141200) VDD
K1
K2
K4
K8
INIT
07
e:(
U
oCI)
CI)
e:(
~
w
Z
a:
o
In
06
05
04
03
CI)
o
40
8
9
10
TMS1200
11
12
13
14
15
16
17
18
19
20
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R7
R6
R5
R4
R3
R15 }
R14
in MC141200 only
R13
R2
R1
RO
Vss (VDD in MC141200)
OSC2
OSC1
00
01
02
~
e:(
Q
e:(
@
Pin Name
Description
Type
K1, K2, K4, K8
00- 07
RO - R12,R13- R15
OSC1,OSC2
INIT
Data input
Data output
Control output
Timing
Power on reset
Power and Ground
Input
Output
Output
Input
Input
VDD' VSS
Figure 1-3. TMS 1200 and Me 141200 Microcomputer Signals and Pin Assignments
R8
R9
R10
VDD
K1
5
6
K2
K4
K8
INIT
07
06
05
04
03
28
27
26
25
24
1
2
3
4
TMS1070
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
R7
R6
R5
R4
R3
R2
R1
VSS
RO
OSC2
OSC1
00
01
02
Pin Name
Description
Type
K1, K2, K4, K8
00- 07
RO - R10
OSC1,OSC2
INIT
Data input
Data output
Control output
Timing
Power on reset
Power and Ground
Input
Output
Output
Input
Input
VDD' Vss
Figure 1-4. TMS1070 Microcomputer Signals and Pin Assignments
1-7
A8
A9
Al0
All
A12
1
40
2
3
4
39
5
6
7
8
9
10
11
VDD
Kl
K2
K4
K8
INIT
04
12
13
14
15
16
17
18
03
08
19·
20
07
06
05
. 09
Piri Name
,Kl, K2, K4, K8
00- 09
AO - A12
OSC1. OSC2
INIT
VDD,VSS
38
37
36
35
34
TMS1270
33
32
31
30
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
Al
Vss
AO
OSC2
OSCl
00
01
02
Description
Type
Data input
Data output
Control output
Timing
Power on reset
Power and Ground
Input
Output
Output
Input
Input,
Figure 1-5. TMS1270 Microcomputer Signals and Pin Assignments
A8
A9
Al0
VDD
Kl
K2
K4
K8
INIT
07
06
05
04
03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin' Name
K 1, K2, K4; K8
00-07
RO - R10
OSC1,OSC2
INIT
VDD,VSS
TMSll00
28
27
26
25
24
23
22
21
A7
A6
AS
A4
A3
A2
Al
RO
20
19
18
17
16
15
Vss
OSC2
OSCl
Description
Data input
Data output
, Control output
Timing
Power on reset
Power and Ground
00
01
02
Type
Input
Output
Output
Input
Input
Figure 1-6. TMS 1100 Microcomputer Signals and Pin Assignments
1-8
cw
I-
~.
o0a:
o
u
~
en
w
!(
R11
R12
R13
R14
R15
VDD
K1
K2
K4
K8
INIT
07
g
CI)
CI)
<
olJ
w
Z
a:
o
III
CI)
o
06
05
04
03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
.....i----I 16
.....-----t 17
....i----4I 18
....-----1 19
20
TMS1300
40
39
38
'37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
RO
Vss
OSC2
OSC1
00
01
02
:E
<
c
<
@
Pin Name
Description
Type
K1, K2, K4, K8
00- 07
RO - R15
OSC1,OSC2
INIT
VDD,VSS
Data input
Data output
Control output
Timing
Power on reset
Power and Ground
Input
Output
Output'
Input
Input
Figure 1-7. TMS 1300 Microcomputer Signals and Pin Assignments
The 0 outputs are provided by 00 - 07, or, in the case of the TMS1270, 00 - 09.
The R outputs occur at RO - R15, or some smaller number of R outputs, depending on the microcomputer.
OSC1 and OSC2 are timing inputs and outputs. A number of timing options are provided. All TMS 1000 series
microcomputers contain internal clock logic which you can access in conjunction with an external RC circuit as
follows:
::6=1=~=h :
You can also input an externally created clock signal at OSC1, in which case OSC2 must be connected to ground (VSS).
When you have more than one TMS 1000 series microcomputer in a configuration. it is a good idea to synchronize the
many microcomputers by driving them with a single clock signal.
INIT is a power on reset signal. Following power on. INIT should be input high (VSS) for at least six consecutive clock
cycles. The Reset operation stores binary ones in the Page Address register and the Page'Buffer register. The 0 outputs.
the R outputs and the Program Counter are all zeroed. Thus. the first instruction executed will have the hexadecimal
address 3C016.
Page Address register ~ ~ Program Counter
111 1 0 0 000 0
- - '-v-"'-'v-'"
3
C
0
1-9
TMS1000 SERIES MICROCOMPUTER INSTRUCTION EXECUTION
Noniicrdcomputer described in this book has simpler instruction execution timing than the TMS 1000 series. All instructions generate one byte of object code. There are no two- or three-byte object codes. Similarly. every instruction executes in a single machine cycle, as timed by the system clock.
TMS1000 SERIES MICROCOMPUTER INSTRUCTION SET
There are variations in the instruction sets of the different microcomputers in the TMS 1000 series. However. the
different instruction sets are similar enough for us to describe them all in Table 1-2. As compared to similar tables
for other microcomputers in this book. Table 1-2 has an additional column which identifies the instructions which are
available with each of the TMS 1000 series microcomputers.
.
Within the confines of a single-chip microcomputer. the instruction set defined in Table 1-2 is both powerful and effective. It would be easy to point out instruction set features which. from a programmer's point of view. are undesirable;
however. theTMS1 000 series microcomputers are oriented to digital logic. The TMS 1000 is not a product that gets
programmed; rather. its instruction set is a means of defining an optional portion of the ROM mask. Within this context.
the instruction set is very adequate. Note that, since you are dealing with a singie-chip microcomputer, there is
nothing to prevent you from redefining the Control Unit and thus creating your own instruction set.
THE BENCHMARK PROGRAM
The benchmark program we are using throughout this book in order to exercise the various microcomputer instruction
sets is essentially meaningless in any TMS 1000 application. Given 64. or at most. 128 nibbles of RAM. the whole concept of moving data among tables is meaningless. We therefore simplify the problem and look upon 10BUF as external
logic. Instead of reading from 10BUF. we will input K data. We will assume that each block of K data is preceded by a
nibble which defines the number of data nibbles to follow:
:
K1
K8
n data nibbles
follow
Thus. each block of data that is input must be fifteen nibbles or less in length.
LOOP
LDX
TKA
TAY
TKA
TAM
DYN
BR
TBHI
LOOP
LOAD TABLE PAGE ADDRESS
INPUT FIRST K NIBBLE. IT EQUALS DATA NIBBLE TO FOLLOW
MOVE TO Y. XY NOW ADDRESSES END OF TABLE
INPUT NEXT DATA NIBBLE
SAVE IN MEMORY
DECREMENT Y
IF Y NOT O. RETURN FOR NEXT NIBBLE
Symbols are used in Table 1-2 as follows:
Registers:
A
X.Y
PC
PA
CF
SR
PB
-
Accumulator
Data Counter. Y also serves as an output address.
Program Counter
Page Address register
Chapter Flag (one bit)
Subroutine Return register
Page Buffer
Statuses:
. ST
C
NE
- The Status Flag
- The status flag reflects a Carry. That is. it is set if there is a Carry from the most significant bit
(MSBl. and reset otherwise.
- The status flag reflects "not equal". That is. it is set if the compared bits are not equal. and reset
if they are equal.
1-10
Inputs and Outputs:
K
-
R
-
o
c
bb
...w
-
the four input lines
the five-bit Output register
the control outputs
Two bits in the object code which specify one of the four bits of a RAM location:
o
3
c(
a:
.......--BitNo.
I I I I. 1.-- RAM location
0
a..
a:
0
j~
CJ
~
j
.~
j
u)
w
bb
...
g
-----00
'------10
' - - - - - - - - 01
c(
(I)
(I)
c(
GlJ
w
2
a:
0
III
(I)
0
~
c(
cc(
@
' - - - - - - - - - - - - 11
b
data
label
R([Y]}
x
[ X](MSB}
[[ X.yJ]
Operand which specifies one bit of a RAM location
2. 3. or 4 bits of immediate data
Destination of Branch instruction (6 bits of direct address in the object code)
The control output line specified by the contents of the Y register.
One bit of immediate data or direct address in the object code.
The most significant bit of the X register
The contents of the RAM location addressed by the contents of the Data Counter.
[[ X.Y]](b} The specified bit of the RAM location addressed by the contents of the Data Counter.
[ ]
Contents of location enclosed within brackets. If C3 register designation is enclosed within the brackets.
then the designated register's contents are specified. If K or R is enclosed within the brackets. then the
data at the inputs or control outputs is specified.
Data is transferred in the direction of the arrow.
Data is exchanged between the two locations designated on either side of the arrow.
Where two object codes are given. the first is the code used in the TMS 1000. TMS 1200. TMS 1070. and TMS 1270.
while the second is the object code used in the TMS 11 00 and TMS 1300.
X in one of the rightmost three columns means that th~ instruction is implemented on the designated TMS 1000 device.
1-11
Table 1-2. TMS1000 Series Instruction Set Summary
TYPE
NlNEMONIC
STATUSES
OPERAND I--_-~
C
NE
x
TMS1000
TMS1200
'TMS1070
TMS1270
08
x
SETR
Load Accumulator with data on input lines.
R([Y])-1
00
RSTR
Set R output addressed by contents of Y.
R([Y])-O
TOO
Reset R output addressed by contents of Y.
[0] -([A],STI
Transfer data from Accumulator and status flag to the 0 outputs.
[0] -00,.
09
O.
a Output register.
TMS1100
TMS1300
x
TKA
Clear the
I
OBJECT
CODE
If [K] ,"",0, ST-I
Set status only if data on input lines is not
[K]-[A]
KNEZ
g
OPERATION PERFORMED
OE
x
MC141000
MC141200
x
X
X
x
X
X
DC
x
x
X
OA
x
x
X
OB
x
X
TAM
[A]-[[X,Y))
TMY
03
27
22
x
Store Accumulator to RAM location addressed by contents of XY Data Counter.
[[X,Y))-[Y]
X
X
X
TMA
Load Register Y from RAM.
[[X,Y))-[A]
21
x
X
X
XMA
,Load Accumulator from RAM.
[[X,Y))--[A]
2E
X
X
X
Exchange contents of RAM location addressed by Data Counter XY with those of
Accumulator.
N
Q3
X
x
TAMIY
[A]-[[X,Y)); [y]--'-[y] + 1
20
TAMIYC
x
Store Accumulator to RAM and increment contents of Y register.
[A]-[[X,Y)); [y]-[y] + 1; ST-C
25
X
X
Store Accumulator to RAM and increment contents of Y register. Set status flag
only if there is a carry.
[A]-[[X,Y)); [Y]-[Y]-I: ST-C
24
X
Store Accumulator to RAM and decrement contents of Y register. Set status flag
only if there is no borrow.
tA]-[[X,Y)); [A]-O
04
TAMOYN
TAMZA
Store Accumulator to RAM and then clear Accumulator.
AMAAC
SAMAN
IMAC
X
X
X
[A]-[[X,Y)) + [A]; ST-C
Add contents of RAM location to those of Accumulator. Set status flag only if
there is a carry.
[A]-[[X,Y))-[AI; ST-C
Subtract Accumulator contents from those of RAM location. Set status flag only
if there is no borrow.
[A]-[[X,Y)) + I; ST-C
Load contents of RAM location to Accumulator and increment. Set' status flag
only if there is a carry. RAM contents are unchanged.
X
X
26
25
28
3E
x
x
x
x
06
27
3C
X
X
x
x
X
x
x
x
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 1-2. TMS1000 Series Instruction Set Summary (Continued)
STATUSES
TVPE
MNEMONIC
OPERATION PERFORMED
OPERAND
C
OMAN
W
NE
X
U
Z
W
a::
w_
U.W
wIa::e(>a::C
ww
a::
OO-~
ALEM
X
MNEA
X
MNEZ
X
::E0~
w>1Z
::Ea::
00
~~g
e(::E
CZ
0
U
w
(I)
I
W
SBrr
b
RBIT
b
TBIT1
b
TCV
data
TCMIV
'data
X
[V]-'data
Load Register V immediate.
[[X,V])-data; [V]-[V] + 1
Load RAM location immediate and increment contents of Register V.
[X]-data
Load Register X immediate.
[PB]-data
Load Page Buffer register immediate .
w
l-
e(
E
w
~
~
LOX
data
LOP
data
..
...
w
e(
a::
w
00
w
l-
~
Q
w
::E
~
ALEC
data
VNEC
data
X
X
A2AAC
X
A3AAC
X
A4AAC
X
A5AAC
X
A6AAC
X
A7AAC
[A]-[[X,V))-1; ST-C
Load contents of· RAM location to Accumulator and decrement. Set status flag
only if there is no borrow. RAM contents are unchanged.
If [A] ~ [[X,V)), ST-1
Set status flag only if Accumulator contents are less than or equal to those of
RAM location addressed by Data Counter XV.
If [[X,V)) '" [AJ. ST-1
Set statu~ flag only if contents of RAM location are not equal to those of Accumulator.
·If [[X,V)) .; 0, ST - 1
Set status flag only if contents of ~AM location are hot equal.to zero.
[[X,V]](b) -1
Set specified bit of RAM location addressed by contents of Data Counter XV.
[[ X,V]](b) -0
Reset specified bit of RAM location addressed by contents of Data Counter XV.
ST - [[X,V]](b)
Test specified bit of RAM location and set status flag only if the bit is set.
X
OBJECT
CODE
TMS1000
'TMS1200
TMS1070
TMS1270
2A
X
3F
OO;;OObb
X
X
X
X
00
26
MC141000
MC141200
X
07
29
01
TMS1100
TMS1300
X
X
X
X
X
X
X
001101bb
X
X
X
001110bb
X
X
X
0100xxxx
X
X.
X
0110xxxx
X
X
X
001111xx
00101xxx
0001xxxx
X
X
X
0111xxxx
X
0101xxxx
X
X
X
.
If. [A] ~,data, ST-1
Set status flag only if Accumulator contents are less than or equal to immediate
data.
If [V] ~ ~data, ST-1
Set status flag only if contents of Register V are not equal to immediate data.
[A]-[A]+2; ST-C
Add 2 to Accumulator contents. Set status flag only if there is a carry.
[Ak-[A] + 3; ST-C
Add 3 to Accumulator contents. Set status flag only if there is a carry.
[A]":'[A]+4;ST-C
Add 4 to Accumulator contents. Set status flag only if there is a carry.
[A]-[A]+5;ST-C
Add 5 to Accumulator contents. Set status flag only if there is a carry.
·[A]-[A]+6;ST-C
Add 6 to Accumulator contents. Set status flag only if there is a carry.
[A]-[A]+7; ST-C
Add 7. to Accumulator contents. Set status flag only if there is a 'carry.
X
X
78
X
74
X
7C
X
72
X
06
7A
76
X
X
X
X
X
Table 1-2. . TMS1000 Series Instruction
Set Summary (Continued)
.
STATUSES
TYPE
MNEMONIC
O~ERAND
C
A8AAC
~w
X
Al0AAC
X
~~
AllAAC
X
~-
A12AAC
X
wC
a..w
ST -c·
Add 8 to Accumulator contents. Set status flag only if there is a ·carry.
[A]-[A]+9;ST-C
.Add 9 to Accumulator contents. Set status flag pnly if there is a carry.
[A]-[A] + 10;ST-C
Add 10 to Accumulator contents. Set status flag only if there is a carry.
[A]~[A]+8;
X
A9AAC
~
0:-
0;:)
w~
58
~
A13AAC
IL
[A]-[A]+ 11; ST-C
Add 11 to Accumulator contents.
[A]-[A]+ 12; ST-C
Add 12 to Accum'ulator contents.
[A]-[A]+ 13; ST-C
Add 13 to Accumulator contents.
[A)-[A] + 14; ST-C
Add 14 to Accumulator contents.
X
A14AAC
X
::;)
.'"
I
~
Z
0
:E:
(J
Z
BR
label
CALL
label
i=
i5
Z
c(
,
a:ce
ww
.......... w
>
~~O
~,~
TAY
TVA
::;:
cece
X
05
79
X
MC141000
MC141200
X
X
X
X
75
X
70
X
73
X
7B
X
X
Set status flag only if there is a carry.
Set status flag only if there is a carry.
OF
X
X
X
10xxxxxx
X
X
X
llxxxxxx
X
X
X
[A]-[Y]
Transfer Accumulator contents to Register Y.
[Y]-[A]
Transfer Register Y contents to Accumulator.
24
20
23
X
X
X
X
If [Y]fo[A],ST-l
Set status flag only if contents of Y register are ncit equal to those of Accumulator.
02
X
X
X
[A]-O
Clear Accumulator.
[A]-[A]+l
Increment Accumulator. No status affected.
[A]-[A]+ 1; ST -C.
Increment Accumulator. Set status flag only if there is a carry.
2F
7F
OE
X'
a
0
a: (J
IZI
01
7E
71
TMS1100
TMS1300
Set status flag only if there is a carry.
If ST = 1. then [PC]-Iabel;
outside subroutine. [PA]-[PB]
Branch if status flag is set.
If ST = 1. then [SR]-[PC]+ 1. [PB]-[PAl. [PC]-label
Call subroutine if status flag is set. A subroutine call within subroutine will act as
a branch. and load the Page Buffer from the Page Address register:
[PC]-LABEL
[PB]-[PA]
Z
0
TMS1000
'TMS1200
'TMS1070
TMS1270
Set status flag only if there is a carry.
[PC]-[SRl. [PA]-[PB]
Return from subroutine.
RETN
::;:
OBJECT
CODE
OPERATION PERFORMED'
NE
X
X
I
ffi!ffi~
.......... c(
~ ~ ce
00
w w
YNEA
X
W
IL
a: ce 0
ce w
w
..... ~
CIl ce
5w
w
CLA
IA
IL
ce 0
lAC
X
70
X
X
X
X
X
© AD~M OSBORNE &
ASSOCIATES,INCORPORATED
Table 1-2. TMS 1000 Series Instruction Set Su mmary (Continued)
STATUSES
TYPE
MNEMONIC
OPERAND
OPERATION PERFORMED
C
w
H)
Pulse width, clock low, twld>U
Sum of rise time and pulse width, clock high, tr + tw(dlHI
Sum of fall time and pulse Width, clock low, tf + twld>U
Oscillator frequency, fosc
Operating free-air temperature, T A
NOTES:
1.
2.
3.
4.
-4
K
0
V
V
/.IS
/.IS
/.IS
/.IS
/.IS
/.IS
400
70
kHz
°c
Unless otherwise noted, all voltages are with respect to VSS.
These average values apply for any 100-ms period.
Ripple must not exceed 0.2 volts peak-to.peak in the operating frequency range.
The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this specification for
logic voltage levels only.
VSS
Voo
Jj---.,
~ tf
I-e-
tw(cpL)
~,,--_-_-_-_-_V:,:(~,
Ii
-.f
\4- tr
--.j
~
tc~"I-------- tC(c;'l1
I
tW(c;'lHI
-JI
------t..~1
NOTE: Timing points are 90% (high) and 10% (low),
FIGURE 7 - EXTERNALLY DRIVEN CLOCK INPUT WAVEFORM
Data sheets on pages 1-02 through 1-05 are reproduced by permission of Texas Instruments Incorporated.
1-D2
TMS 1000/1200 AND TMS 1100/1300
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE·AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)
PARAMETER
w
!ia:
VOH
Low·level output current
10L
o(J
IOO(av)
~
g
P(AV)
en
en
ct
ell
w
Z
a:
oen
TMS 1000/1200 (see Note 2)
-0."75
10 = -2mA
300
Average power dissipation
TMS 1000/1200 (see Note 2
Average power dissipation
TMS11 00/1300 (see Note 2)
MAX UNIT
500
j./A
-100
j./A
V
-0·4
All outputs open
-6
-10
rnA
All outputs open
-7
-11
rnA
All outputs open
90
175
mW
All outputs open
1q5
193
mW
300
350
kHz
TMS11 00/1300 (see Note 2)
P(AV)
Typt
-1.1:1: -0.6:1:
10 = -10mA
Average supply current from VOO
IOO(av)
50
VI = OV
VOL = VOO
Average supply current from VOO
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I R outputs
(see Note 1)
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I 0 outputs
High·level output voltage
Q
MIN
TEST CONDITIONS
Input current, K inputs
II
fosc
Internal oscillator frequency
Ci
Small'signal input capacitance, K inputs
Rext = 50 kn,
VI =0,
Cext = 47 pF
f = 1 kHz
Cj(¢)
Input capacitance, clock input
VI = 0,
f=1ookHz
250
10
pF
25
pF
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t All typical values are at VOO = -15 V, TA = 25°C.
:I: Parts with
NOTES:
VOH of -2 V minimum, -1.3 V tvpical, are available if requested.
1. The algebraic convention where the most·positive (least.negative) limit is designated as maximum is used in this
specification for logic voltage levels onlv.
2. Values are given for the open·drain 0 and R output configurations. Pull·down resistors are optionally available on all
outputs and increase I DO (see Section 4,4).
SCHEMATICS OF INPUTS AND OUTPUTS
TYPICAL OF ALL K INPUTS
INPUT
~
TYPICAL OF ALL 0 AND R
OPEN·DRAIN OUTPUTS
VSS
d
R' 50 kn
l
VOD
TYPICAL OF ALL 0 AND R
OUTPUTS WITH OPTIONAL
PULL·DOWN RESISTORS
Vss
VSS
J .
I ....
~OUTPUT
i
d
rOUTPUT
~VOO
The 0 outputs have nominally 60 n on·state impedance; however, upon request a 130·n buffer can be mask program·
med (see note It I section 4.3).
The value of the pull·down resistors is mask alterable and provides the fo!lowing nominal short·circuit output currents
(outputs shorted to VSS):
o outputs: 100,200,300,500, or 900 J.1A
R outpllls: 100, 150, or 200 J.1A.
l-D3
TMS 1000/1200 AND TMS 1100/1300
INTERNAL OR EXTERNAL CLOCK.
If the internal oscillator is used, the OSC1 and OSC2 terminals are shorted together and tied to an external resistor to
VOO and a capacitor to VSS' If an external clock is desired, the clock source may be connected to OSC1 and OSC2
shorted to VSS'
TYPICAL INTERNAL OSCILLATOR FREQUENCY
vs
EXTERNAL RESISTANCE
CONNECTION FOR INTERNAL OSCILLATOR
I lE------o
cext
osc':
Vss
OSC2 '---~-""--'l~VDD
R ext
100L-~~~--~--~~~--~~~~__~~
o
20
40
60
80
100
120 140
160
180
200
Rext.- External Resistance - kn
TYPICAL BUFFER CHARACTERISTICS
o OUTPUTS
R OUTPUTS
HIGH·LEVEL OUTPUT CURRENT
HIGH·LEVEL OUTPUT CURRENT
vs
vs
HIGH·LEVEL OUTPUT VOLTAGE
HIGH·LEVEL OUTPUT VOLTAGE
-30 .....--.--.---.---..,....-..;...,.....---.r--.......-..,....-...,...---.
-~ ~~--~--~~~~~~~~~~-4-~
c(
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c(
-40
E
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:J
CJ
:;
-30
-20~-4--~~~--+---~~~-+--~~4-~
CJ
;
:J.
~
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:J
0
-15
1
i -10 ~-4----t-.;+-,jC---+-
!
...I
...I
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2
2
oL-~
o
__
~
-1
__
~~
__
-2
~
__
~
-3
__
~~~~
-4
__
-5
~
-1
-5
-2
-3'
VOH - High·Lewl Output Volt. - V
VOH - High·Lewl Output Volt8Qtl - V
1-04
-5
TMS 1070/1270
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)*
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• -20V
-20 V to 0.3 V
-35 V to 0.3 V
-20 V to 0.3 V
-2.5 mA
-12 mA
-5mA
-24mA
400mW
600mW
O°C to 70°C
-55°C to 150°C
Voltage applied to any device terminal (see Note 1)
Supply voltage, V DD
Data input and output voltage with VDD applied (see Note 2)
Clock input and IN IT input voltage
Average output current (see Note 3): 0 outputs
R outputs
Peak output current:
0 outputs .
R outputs .
Continuous power dissipation: TMS 1070 NL .
TMS 1270 NL.
Operating free-air temperature range
Storage temperature range.
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·Stresses beyond those listed under "Absolute Maximum Ratings" maY cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions"
section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
oal
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RECOMMENDED OPERATING CONDITIONS
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PARAMETER
Supply voltage. VOO (see Note 41
MAX
UNIT
-15
-17.5
V
-1.3
INIT or Clock
Low-level input voltage, VIL (see Note 51
NOM
-14
0.3
-6
K
High-level input voltage, VIH (see Note 51
MIN
K (See Note 21
-35
INIT or Clock
VDO
2.5
Clock cycle time, tcl¢1
-1
-8
V
-15
-8
3
10
SlS
60
SlS
15
Instruction cycle time, tc
V
0.3
Pulse width, clock high, tw(¢HI
1
SlS
Pulse width, clock low, tw(¢Ll
1
SlS
Sum of rise time and pulse width, clock high, tr + tw(¢HI
1.25
SlS
Sum of fall time and pulse width, clock low, tf t tw(¢Ll
1.25
SlS
Oscillator frequency, fosc
Operating free-air temperature, T A
NOTES:
1.
2.
3.
4.
5.
100
400
0
70
kHz
C
Unless otherwise noted, all volt~ges are with respect to VSS.
VOO must be within the recommended operating conditions specified in ~.4.
These average values apply for any 100-ms period.
Ripple must not exceed 0.2 volts peak-to-peak in the operating frequency range.
The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this specification for
logic voltage levels only.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)
PARAMETER
II
TEST CONDITIONS
Input current, K inputs
I a outputs
High-level output voltage
VOH
I
(see Note 11
R outputs
MIN
Typt
VI=OV
40
100
10 = -1 mA
-1
-0.5
-4.5
-2.25
10 = -10 rnA
Low-level output current
10L
IDO(avl Average supply current from VDD
VOL = VDD
All outputs open
MAX
300
UNIT
SlA
V
-100
SlA
-10
mA
90
175
mW
300
350
kHz
-6
P(AVI
Average power dissipation
All outputs open
fosc
Internal oscillator frequency
Rext
Ci
Small-signal input capacitance, K inputs
V, =OV,
f =
1 kHz
10
pF
Ci(¢1
Input capacitance, clock input
V,-OV,
f - 100 kHz
25
pF
t All typical values are at VOO
= -15
V, T A
= 50 kn,
Cext = 47 pF
250
= 25°C.
NOTE 1: The algebraic convention where the most-positive (least-negative) limit is designated as maximum is used in this specification.
for logic voltage levels only.
1-D5
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Chapter 2
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IX:
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THE MOSTEK 3870
(AND FAIRCHILD F8)
IX:
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The F8 has had a profound Impact on the microcomputer Industry. When it first appeared, the F8 was discussed
as an off-beat product with a strange set of chips and a ridiculous Instruction set. The chip set was strang~
because logic was organized with the goal of minimizing chip counts: In contrast, microprocessors such as the
8080A and 6800 were designed with logic distributed functionally on chips - one traditional CPU logic function
per chip. The F8 instruction set is indeed strange, and in some cases quite limiting, but it reflects the simple
chip design of the F8 CPU.
Many microprocessors are now going into consumer products. In this marketplace, the two-chip F8 system provided by a 3860 CPU and a 3861 PSU gained an early dominant position. Other microprocessors available when
the F8 was introduced required seven or more chips to provide the same capabilities as the two-chip F8. The
economics of consumer product volumes rendered the inefficiencies of the F8 instruction set inconsequential:
as a result, in 1977 the F8 was the world's leading microprocessor in terms of CPU sales.
.
In recognition of the F8 success story, most microprocessor manufacturers have introduced one-chip and twochip microcompu~er systems.
Since the F8 3850 CPU/3851 PSU configuration was the world's first two-chip 8-bit microcomputer system. the F8 was
the easiest 8-bit microprocessor to convert into a one-chip microcomputer. Fairchild, the F8 prime source, and
Mostek, the F8 second source, both designed one-chip microcomputers around the F8. Fairchild des'gned the
3869, which was a simple combination of the 3860 CPU and 3861 PSU on a single chip. Mostek developed a
more ambitious one-chip microcomputer, the 3870. Mostek developed the 3870 ahead of the Fairchild 3859:
therefore, Fairchild dropped the 3869 and became a second source for the 3870. Thus. the original F8 second
source. Mostek. is now the new prime source. while the original prime source. Fairchild. is now a second source.
The majority of F8 customers have small configurations which convert readily to the 3870. This being the case. the
3870 is the F8 product being actively marketed, while the old F8 chip set is now manufactured to meet the needs of
existing customers and to represent a possible expansion for any customer whose application will no longer fit within
the confines of the 3870. In this chapter, therefore, we begin by examining the 3870 in detail. Dl3scriptions of the
F8 CPU and its support devices follow.
.
r-------.....,.
THE FAIRCHILD
These are the F8 devices described:
F8 DEVICE SET
- The 3860 CPU.
- The 3861 Programmable Storage Unit (PSU), which provides read-only memory plus
various additional logic functions.
- The 3862 Dynamic Memory Interface (DM!), which primarily provides interface logic for dynamic or static
read-write mem~ry.
- The 3863 Static Memory Interface (SM!), which primarily provides interface logic for static read/write memory.
- The 3864 Direct Memory Access (DMA), which, in conjunction with the 3862 DMI, implements Direct Memory Access logic.
'
- The 3866 and 3867 16K Programmable Storage Units (PSU 16), which are variations of the 3861 PSU b4t provide more read-only memory.
- The 3861 PIO, which provides the additional logic functions of the 3861 PSU but has no read-only memory.
- The 3871 PIO, which is equivalent to the 3861 PIO but has logic characteristics identical to thp 3870.
Some additional 3870 series products are planned for delivery in late 1978 and early 1979.
2-1
The 3872 is identical to the 3870. except that program memory is doubled from 2048 to 4096 bytes. The 4096 bytes of
program memory are configured as 4032 bytes of read-only memory and 64 bytes of read/write memory. Thus. the
3872 will have 128 bytes of read/write memory. of which 64 are in the scratchpad and an additional 64 are in external
memory.
The 3873. which will probably be available in early 1979. is equivalent to a 3870 with one serial I/O channel added.
The 3876. which will probably be available in late 1978. is equivalent to a 3870 with 64 bytes of additional read/write
memory; that is.to say. in addition to the 2048 bytes of program memory there will be 64 bytes of scratchpad memory
and an additiona>1 64 bytes of external read/write memory. This additional 64 bytes of external read/write memory will
have a low power standby option. allowing you to maintain data in these 64 bytes while power has been removed from
the rest of the device.
.
Figure 2-1 illustrates logic associated with individual F8 devices, and the 3870 one-chip microcomputer.
All devices of the F8 family require +5V and +12V power supplies. The 3870. however, uses a single +5V power supply.
Using a 500 nsdock. instruction cycle time is 2 ,""sec. Instruction execution times ·rangefrom 1'to 6.5 instruction cycles. or 2 to 13 ,""sec.
. .
N-channel isoplanar MOS technology is used for the F8.
N-channel ion injection technology is used for the 3870.
The 3870 Microcomputer
.----------------------------,
:
3850 CPU
3851, 3856 or 3857 Program Storage
I
Unit (PSU)
I
I
I
n
eques
I~~~R
-
-
I
I/O Port I/O ~ort
I/O Port I/O Port
•
,~
,
,
'.
--
~
~
r
II
3853 Static
Memory Interface .
(SMJ)
/
Prog Timer
Prog Timer
64-byte RAM
ALU
and.
CU
Interrupt Request
ROM
,--__
- --
RAM
INTERFACE
LOGIC
__ ...J
'Mem Addr Log
Jt
STATIC
RAM
t
I~
SYSTEM BUS
~
DYNAMIC
or
STATIC
RAM
~
I~
r
'.
r
RAM
INTERFACE
LOGIC
DMA CONTROL
- ..
~
/
/
--
3852 Dynamic Memory Interface
(DMJ)
-
DMA
. CONTROL
LOGIC
'"
A maximum of 65,536 bytes of memory may be present in an F8 microcomputer system.
Figure 2-1. A Fairchild/Mostek F8 Microcomputer System
2-2
3854 Direct
Memory Access
(DMA)
I
The principal manufacturer for the F8 is:
FAIRCHILD SEMICONDUCTOR .
464' Ellis Street
Mountain View. CA 94040
Q
The second source is:
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MOSTEK. INC.
P.O. Box 169
Carrollton. TX 75006
The principal manufacturer for the 3870 is:
MOSTEK. INC.
P.O. Box 169
Carrollton. TX 75006
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Second sources are:
FAIRCHILD SEMICONDUCTOR
464 Ellis Street
Mountain View. CA 94040
MOTOROLA. INC.
Semiconductor Products Division
3501 Ed Bluestein Blvd.
Austin. TX 78721
@
.THE 3870 ONE-CHIP MICROCOMPUTER
Functions implemented on the 3870 microcomputer are illustrated in Figure 2-2.
Some caution must be exercised when looking at Figure 2-2; functions shown as present should not always be
considered equal to larger systems. For example. read/write memory and memory addressing are shown as completely
present: however. only 64 bytes of read/write memory are provided. with no possibility of expansion. I/O ports and interface logic are shown as provided. but the 3870 itself has only four I/O ports. Programmable timers and interrupt handling logic are shown as present. yet only one interrupt request line is available and only one programmable timer is
present -- again with no possibility for expansion.
There is. in fact. a sharp contrast between the expansion philosophy of the 3870 as compared to
the Intel 8048. The 3870 is simply not expandable: if your application overflows the 3870 you
can keep your programs, but you must revert to the F8 chip set. In contrast. the 8048 is expandable. albeit in a somewhat clumsy fashion. Thus. when an application overflows a 3870. you can keep your programs but you must throwaway your 3870 chips. When an- application overflows the 8048. you can keep the 8048
already in hand. using expansion capabilities to support new functions.
2-3
it
",,'.',.....
"'>"",'
i<
/)
......
.( J. ,jJ
.,"
'\ A;ithM~tis~Hd' \
Acc~mulat?r
: ;
~,.,
.)~9gic Unitii
.. ,',.........".,.
.... ::).: ...
R~gistens)
""""",.
,.....
','"
':','.
.:'.
..
""
,
Interrupt Priority
Arbitration
•••••••
Stack Pointer
"""'"
'".
Direct Memory
Access Control
Logic
8~~ I~t~rtace
..
>Logi'9''')'''''''~< "i'.' I' ....,:':'... ............, Program Counter
"/i:,'!/
'
.....
•••••••i
•
i"'::"""
,"',','
"'"
,':..
'i'
......
~.
it
. ,?
"."".,
'}" >t:
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1/ a Communication
ROM Addressi;'~
Serial to Parallel
Interface Logic
t.\'iiiand
•.'. • :Interface~&glc\
RAM>Addressing
IJqf'oris
Interface Logic
- \aod")/<\
.• :,19terfil~eiLogic
xi'
.,"
,.,
",.,
...,
I/Oports ""'.'\
("E~g~ralTIma?,',Ef
Timers,"':',)i}::,
,
.Read/Write
)i<
Figure 2-2. Logic of the Fairchild/Mostek 3870 Microcomputer
2-4
:.-
3870/F8 PROGRAMMABLE REGISTERS
These are the programmable registers of the 3870 and F8:
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Accumulator (A)
8 bits
11 bits in the 3870,116 bits in the F8 Program Counter (PCO)
a:
11 bits in the 3870,16 bits in the F8' Program Counter buffer, or Stack register (PC 1)
lJ
11 bits in the 3870,16 bits in the F81 Data Counter (DCO)
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11 bits in the 3870116 bits in the F8 Data Counter buffer (DC 1)
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5 bits
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DCO or PCO registers ..
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1
2
2
I
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9
11
9
HU
10
12
A
H
.,,{
HL
11
13
B
K
. - { KU
KL
12
14
C
13
15
D
Q
.. {QU
14
16
E
QL
15
17
F
16
20
10
58
72
3A
59
73
3B
60
74
3C
61
75
3D
62
76
3E
63
77
3F
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W register .....
PC 1 (Stack) register ....
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Status register (W)
DCO register :4
§
. ,
Scratch pad Address register (lSAR)
a:
Scratchpad Byte Address
Decimal
Octal
Hexadecimal
Scratchpad
,
H is equivalent to a Data
Counter buffer register
K is equivalent to a Stack
register buffer
Q is equivalent to a Data
Counter or Program Counter
buffer register
I
",
There is one 8-bit Accumulator, which may be likened to the Primary Accumulator (AO) of
our hypothetical microcomputer. Wherever there is a choice, this Accumulator is the usual
source or destination for data operations associated with any instruction's execution.
2-5
3870/F8
ACCUMULATOR
The 64-byte scratchpad may be viewed either as a small read~write memory, or as 64 8bit secondary Accumulators. The first 11 scratchpad bytes may. be accessed directly. as
though they were secondary Accumulators. Remaining RAM bytes can only be accessed using
a form of implied memory addressing. where a 6-bit register (identified as the ISAR register) must provide the address
of the byte being accessed. The ISAR register is in every way identical to a 6-bit Data Counter.
Data Counter DCO is an implied addressing register, as described for our hypothetical
microcomputer.
..
.
3870/F8 DATA
COUNTERS
Data Counter DC1 is simply a buffer for the contents of Data Counter DCO. Implied addressing via Data Counter DC 1 is not allowed. The only instruction that accesses Data Counter DC 1 is an instruction which
will exchange the contents of Data Counters DCO and DC 1.
Program Counter PCO serves the same function in a 3870 or F8 system as it does in
our hypothetical microcomputer.
3870/F8 PROGRAM
COUNTER
3870/F8 STACK
The Stack register (PC1) is, in reality, a buffer for Program Counter PCO; the Stack register
does not address an area in read-write memory. and there arena Push or Pop instructions as
REGISTER
described in Volume I. Chapter 6. Interrupts and Jump-to-Subroutine instructions save the
contents of Program Counter PCO in Stack register pct before loading a new address into Program Counter PCo:
Old Address from
pca
is moved to PC 1
NeWAddr~ss"
.
~
I'-e.. ?J
Program Counter
I~ -",
pea
Old Address in
/ ' PClislost
.
Stack register PCl
The classical Stack can be implemented in a 3870 or F8 system. but a short program needs to be written to do this.
Read-only memory is always addressed using implied addressing, with auto-increment, via
Data Counter DCO. No other memory addressing modes are provided.
MEMORY
ADDRESSING
There are a number of instructions which load immediate data into Data Counter DCO; data may also be transferred
between Data Counter DCO and scratchpad bytes. and it is possible to add the contents of the Accumulator to Data
.
.
Counter DCO.
In order to understand scratchpad addressing, one has to view it as representing neither 64
Accumulators nor 64 bytes of read-write memory, but rather as something between the
two.
SCRATCH PAD
MEMORY
ADDRESSING
3870 MEMORY ADDRESSING MODES
The 3870 microcomputer has two separate and distinct memories:
1)
There is the 64-byte scratchpad. which is the only read/write memory available.
2)
There are 2048 bytes of read-only memory. which must contain all programs. but may also contain constant data.
We will refer to addressing of the 64-byte scratchpad as "scratchpad addressing", while "memory addressing"
refers to the 2048 read-only memory bytes.
It is important to note that the scratchpad and the read-only memory have separate and distinct address spaces.
Scratchpad locations have addresses in the range 0 through 6310. while read-only memory locations have addresses in
the range 0 through 204710. Thus. addresses 0 through 6310 can access both a scratchpad byte and a read-only
memory location; however. this will never cause confusion since separate and distinct instructions access scratchpad
as against read-only memory. Since no one instruction can access both scratchpad and read-only memory. there is no
possibility for confusion.
2-6
Instructions which access scratchpad memory use the four low-order object code bits to identify Scratchpad Addressing mode. as follows:
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...
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Scratchpad access instruction object code
~} Directly address one of Scratch pad bytes 0 through 11
1011
1100·
1101
I-
1110
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S - Implied addressing via ISAR
I - Implied addressing via ISAR
with auto-increment of three
low-order ISAR bits.
D - Implied addressing via ISAR
with auto-decrement of three
low-order ISAR bits.
There are a number of register-register instructions that operate on the Accumulator and on one of the first 12
scratchpad bytes, using object codes as follows:
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65432
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0000
One scratch pad byte from bytes 0 through 11 is specified
1011
An instruction that accesses the Accumulator and one of the
scratchpad bytes is specified
This type of object code treats the first 12 scratch pad bytes as secondary Accumulators.
Any scratchpad byte may be addressed via the ISAR register using implied addressing; that
is to say. the 6-bit number in the ISAR (which can have a value in the range 0 through 63) identifies the one scratchpad byte which will be accessed by the next scratchpad referencing instruction.
The ISAR register provides implied addressing. and implied addressing with auto-increment or
auto-decrement: however. only the low-order three bits of the ISAR register are involved in the
auto-increment or auto-decrement operation:
5
4
o
3
DIRECT
SCRATCHPAD
ADDRESSING
IMPLIED
SCRATCHPAD
ADDRESSING
.....-SitNo.
·TTL--
l...........i-.....I!..-ISAR
l...-""'--'r.........I...........
-
These three bits may be incremented or decremented by ~n implied addressing scratchpad memory reference with auto-increment/decrement.
Specifies an instruction that accesses the Accumulator and one
of the scratch pad bytes
F8 scratch pad bytes may therefore be ·accessed as contiguous 8-byte buffers. with wraparound auto-increment or
auto-decrement within each 8-byte buffer.
2-7
Instructions shown in Table 2-2 use the symbol r in the operand to represent scratchpad addressing. This is what the symbol r represents:
rSCRATCHPAD
ADDRESSING
- If r is a number between a and 11. one of scratchpad bytes a through 11 is addressed directly.
- If r is S. implied addressing via ISAR is specified.
- If r is I. implied addressing via ISAR. with auto-increment of the low-order three implied address bits. is specified.
- If r is O. implied addressing via ISAR. with auto-decrement of the low-order three address bits. is specified.
Given the various ways in which scratchpad memory can be addressed. this is the most effective way of configuring
scratchpad:
o
89 AB C 0 E F 10
1718
2728
1F20
3738
2F 30
3F
11111111111111111111111111111111111111 111111111111111111111111111
Secondary
Accumulators
H
K
Q
tt+
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
Buffer 6
Dot, Co""to, IDCOI 0' Prog"m Cou",,, IPCOI buff"
Stack (PC 1) buffer
Data Counter (OCO) buffer
' - - - - - - - - Status register (J) buffer
Treat scratch pad bytes a through
dreSSing.
8 as nine secondary Accumulators:
access these bytes using direct scratchpad ad-
Wherever possible. use scratchpad bytes 9 through F only as buffers for their associated registers: when accessing
these bytes. use the specific instructions which transfer data between these scratchpad bytes and their associated
registers.
Although you can address scratch pad bytes 9. A. and B by using direct addressing. do not do so when these
scratchpad bytes are being used as buffers for the Status registers (W) and Data Counter (DCa).
While indirect addressing via ISAR can access anyscratchpad byte. you should avoid addressing scratch pad bytes a
through F in this fashion. Wherever possible. use ISAR only to address scratch bytes 1a16 through 3F16: divide this
area into 8-byte buffers as illustrated. Because I addressing auto-increments only the three low-order ISAR bits. this
form of scratchpad byte addressing will wrap around within one 8-byte buffer. as follows:
ISAR
X
X
X
X
X
x
X
x
0
x
0
0
0
1
X
X
X
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0'
X
X
X
X
X
X
X
X
X
X
X
X
X
x
x
x
x
x
0
1
1
1
1
etc.
Similarly. 0 implied addressing via ISAR will wrap around within eight scratchpad byte divisions. as follows:
ISAR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
1
1
0
0
0
0
0
etc.
2-8
0
1
1
0
1
0
1
1
0
0
0
0
1
1
3870/F8 STATUS FLAGS
The Status register, also called the W register, holds five status flags, as follows:
4 3 2
o
.-'1-.................
Bit No .
Status register (WI
Q
w
~
a:
o0.
a:
o
o
~
enw·
l-
e(
' - - - - - - - Interrupt Control Bit
U
o
(I).
(I)
e(
01:1
w
Z
a:
o
III
The O. Z. C and S status flags are identical to the flags with equivalent symbols. as described in Volume I. Chapter 6 for
our hypothetical microcomputer.
The Interrupt Control bit is treated as a fifth status; this status will not be modified by arithmetic or logic operations.
but it will be transferred. as a unit with the other four status flags. to or from Scratchpad byte O.
'
(I)
o
~
3870 PINS AND SIGNALS
Q
3870 pins and
e(
e(
si~nals
are illustrated in Figure 2-3.
@
XTL1
XTL2
Po:O.
PO-1 !
PO-2 '
PO-3
STROBE
P4-0
P4-1
P4-2
P4-3
P4:4
P4-5
P4-6
P4-7
PO-7
PO-6
PO-5
PO-4
GND
..
-
---.-.
...
...
...
...
i.
.
---,- -..
~
-- ........
--.. ....
-- ...--- ..
...
-- ....
~.
...
1
40
2
39
3
38
4
37'
5
36
6
35
7
34
8
33
9
32
3870
10
31
11 Microcomputer 30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22.
20
21
-----... ..-
:...-~
-- -..
~
---
.....
----- -'...~
~
-.- .....
.:
--- ...
~
~
--- .--..
----~
~
Pin Name
Description
Type
PO-O - PO-7
Pl-0 - Pl-7
P4-0 - P4-7'
P5-0 - pg:r
STROBE
EXTINT
RESET
TEST
XTL1. XTL2
VCC. GND'
I/O Port 0
I/O Port 1
I/O Port 4
I/O Port 5
Ready Strobe
External Interrupt
External Reset
Test Line
Time/Clock
Power Supply Lines
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
Input
Input
Input
Input
Input
Figure 2-3. 3870 Microcomputer Signals and Pin Assignments
2-9
32 of the 40 signals implement four 8-bit I/O ports, which are addressed as 1/0 Ports 0, 1, 4 and 5.
Pins POO through P07 implement I/O Port O.
Pins P10 through P17 implement
i/o Port 1 ~
Pins P40 through P47 implement I/O Port 4.
Pins P50 through P57 implement I/O Port 5.
I/O port characteristics are described following signal definitions.
STROBE is a handshaking control signal associated with I/O Port 4. Whenever data is output to I/O Port 4, STR08E
is pulsed low for approximately three ~Iock periods.
External interrupt requests are input via EXT INT.
RESET is a master reset input. When it is grounded, the following events occur:
1)
Program Counter contents (PCO) are pushed onto the Stack register (PC1,).
2)
The ICB bit of the Status register is reset to 0; this di~ables all interrupts.
3)
1/0 Port 4 and 5 pins all output +5V. Reset does not affect I/O Port 0 and 1 pins.
4)
Other internal registers are not affected.
The TEST input is used to test hardware. Normally the TEST pin is connected to ground, or it is left unconnected.
When a voltage between 2V and 2.6V is connected to TEST. 1/0 Ports 4 and 5 become output and input connections to
the internal Data Bus; as follows:
' l:___~__ ._----"'"T":-J
'TI-/l
______.....l"_'_
~
Data Bus
-----------~-----,
I/O
Port false.
5 is a(Port
wire-OR
th,e0)internal Data Bus; it is
logically
pin 1 input
= DatatoBus
--.. I/O Port 4 is, the internal Data Bus output; it is logically true:
(Port pin 1 = Data Bus ,1)
When a voltage level between +6V'and +7V is applied to the TEST pin, I/O Ports 4 and 5 are connected to the internal
Data Bus as illustrated above; but. in addition, internal program memory is disconnected from the Data,Bus. This allows
instruction codes to be entered via I/O Port 5. '
.
The TEST pin should be used for test purposes only. Do not use TESTduring normal 3870 operations. You cannot. for example, use TEST as a means of transferring data between the Data Bus and external logic via I/O Ports 4 and
5. Also, you cannot use TEST to supercede internal program memory, with an external program memory. This is
because timing associated with the test conditions differs markedly from normal instruction execution timing.
XTL 1 and XTL2are clock signal inputs. These two clock signal inputs can be used in one of
four ways.
3870 CLOCK
LOGIC
If XTL 1 and XTL2 are both grounded. then an internal oscillator within the 3870 generates the clock signal. Internal oscillator frequencies ranging between 1.7MHz and 4MHz are allowed.
An external crystal may be connected across XTL 1 and XTL2; in this case the external crystal determines clock frequency. Any frequency in the range 1 MHz to 4 MHz is allowed. There are internal 20 pF capacitors between XTL 1 and
ground and XTL2 and ground; therefore, external capacitors are not required. This may be illustrated as follows:
XTL 1
t------.. .
o
XTL2
t------...J
2-10
1 MHz to 4 MHz
If an external clock signal is used, then it should be applied to pin XTL2, and pin XTL 1 should be left open.
The internal clock signal generated will have a frequency that is half of the external clock signal frequency. For example. in order to generate a 1 MHz internal clock signal. a 2 MHz external clock signal must be applied to pin XTL2.
c
It is also possible to generate the internal 3870 clock signal using resistor capacitor (RC) or inductor capacitor
(LC) circuits. The RC mode may be illustrated as follows:
w
~
a:
o
Q.
R
XTL2
VCC
~-----""-""";~",""--.I
rc:
o(.)
C
~
enw
I-
XTL1
ct
(Capacitor C is optional)
~-----.
C3
o(I)
(I)
ct
R
ell
Capacitance
Minimum frequency
Maximum frequency
w
Z
a:
o
4Kil Minimum
20.5 pF + 2.5 pF + C
1/(1.1 RC + 65 ns)
1/(RC + 15 ~s)
!XI
(I)
o
~
ct
c
ct
The external capacitor C is optional. since there is a 20.5 pF internal capacitor.
The LC mode may be illustrated as follows:
@
Inductor L = 0.1 mH (minimum)
Inductor quality =. (Q) = 40
If the external capacitor (C) is present. it must be 30 pF or less.
Capacitance
10 pF
1.3 pF + C
Frequency = 1/(2 7T J1C)
±
3870 INSTRUCTION TIMING 'AND EXECUTION
All 3870 instructions execute as a sequence of "Iong" and "short" machine cycles. A long machine cycle lasts
six clock periods. A short machine cycle lasts four clock periods. For each 3870 instruction. Table 2-2 identifies the
sequence of long and short machine cycles via which the instruction executes. By referring to this table. you can compute instruction execution times as a function of clock frequency.
Note that Table 2-2 refers to ROMC states. ROMC states have no meaning when you are using a 3870: however. they
constitute five signals output by the 3850 CPU in an F8 configuration. as described later in this chapter. Since Table
2~2 applies to both the 3870 and the F8. ROMC states are identified.
3870 I/O PORTS
The 3870 has four 8-bit I/O ports, which we defined when describing 3870 pins and signals. I/O ports are addressed via port numbers 0, 1, 4, and 5. I/O port addresses 6 and 7 are also reserved by the 3870; I/O Port 6 is
used' to output control codes and to input interrupt status. I/O Port 7 is used to acc~ss interval time~ logic.
O. 1. 4. 5. 6. and 7 are the only I/O port addresses which have any meaning within a 3870. Output instructions that address any other I/O port act as "no operation" instructions. Input instructions that address any other port will clear the
Accumulator. Nevertheless. the 3870 instruction set. as oefined in Table 2-1. includes both long-form and short-form
I/O instructions. allowing any I/O port to be accessed with addresses in the range 0 through 255. This permits the 3870
instruction set to be completely compatible with the full F8 instruction set -- a necessity if 3870 programs are to be
transportable to larger F8 configurations.
.
2-11
Everyone of the 3870 1/0 port pins is truly bidirectional. Logic associated with each pin may be illustrated as
follows:
.
Vee
~
c0
Output
Buffer
..,.
~
::l
o
en
'E0
Q
Port
I/O
Pin
()
a:
0
-C'
~
]
en
:J
al
«
~
0
0
Ia:
0
0
0
l-
a:
0..
0..
~ 0«
a: .....I
The pin logic illustrated above is present in the 3870 microcomputer and the 3871 PIO only; other devices have
the F8 1/0 pin characteristics.
.
If you do not understand digital logic. then you will not understand the illustration above. but that is not particularly important. The above illustration explains exactly how bidirectional 110 port pin logic works. From a programmer's point
of view. this simply translates into the fact that you can freely input and output data without worrying about prior 1/0
port contents. However. all 1/0 port pins have inverted logic. This means that when you write 1 to a!1110 port pin a 0
voltage will be generated. while a +5V voltage will be generated if you output 0 to the pin. Conversely. external logic
will cause your program to input 1 if it grounds a pin. while it will cause your program to input 0 if it applies +5V to the
. .
pin.
The output buffer portion of 1/0 port pin logic determines th,e pin characteristics. Standard TTL logic is provided
by the standard output buffer, which may be illustrated as~ follows:
vee
I
2-12
6K II (typ;""n
You can buy 3870 devices with different output buffers at I/O Port~ 4 and 5. but not at I/O Ports 0 and 1. I/O Ports 0
and 1 pins can only have the standard output buffer illustrated above. There are two optional output buffer designs
available for phls of I/O Ports 4 and 6. A direct drive output is similar to the standard output. but it sources more current. Logic is illustrated as follows:
Vee
c
w
~
a::
oa.
, 1K
n (typical)
a::
o
u
~
en
w
...
g<
(I)
(I)
<
oil
w
Z
a::
--
o
en
(I)
o
~
The other option is an open drain output. which may be illustrated as follows:
c<
1-
@
The open drain output allows you to tie pins together: you can then wire-AND two or more pins when data is output.
Consider the following configurations:
P43
, P44
P45
~
--...-j--
-~----....
-
If all outputs are high. then the wire-AND will be high: however. if anyone of the three outputs goes low. then the wireAND resulti~g from all three outputs will also go low.
3870 INTERRUPT LOGIC
External logic can input an interrupt request to the 3870 via the EXT INT signal.
Interrupt requests may also be generated internally by timer/counter logic.
There are two levels of interrupt enable/disable logic within the 3870; There is a Control
register (described later in this chapter) which has bits 0 and 1 set aside to selectively enable or disable external interrupts and timer/counter interrupts, respectively. If one or both of
these interrupts are enabled. then any interrupt request is still subject to master ena-
2-13
3870
INTERRUPT
DISABLE
ble/disable logic, which is specified by the Interrupt Control bit of the Status register (bit 4 "of the W register).
This may be illustrated as follows:
-----------~~ To CPU
""1
a ...
432
Bit No.
....~--- Status register (W)
Latch
ta=
For all bits:
1 =enable
a = disable
,-"-.
7
6
5
4
"2
3
1
Ix I
1
a ......
._---
~t~
Bit No.
Control
,,.;,ie,
External Interrupt
•
TIme,/Counte, ,Inte"upt
A timer/counter interrupt request is latched. If timer/counter interrupt logic has been disabled via Control
register
bit 1. then an interrupt request will be held until timer/counter interrupts are subsequently enabled; the interrupt request will then occur.
External interrupt requests are not latched. An external interrupt request will only occur if the EXT INT signal makes
an active transition while external interrupts have been enabled by Control register bit O.
Ariy inteh'upt request that reaches Status register logic will be latched, Thus. if Status register bit 4 is 0 when
either an external interrupt request or a. timer/counter interrupt request occurs. then the interrupt request will be held
pending until Status register bit 4 is subsequently set to 1.
.
A reset or power-on operation disables all interrupts: the Status and Control registers are cleared.
Timer/counter interrupt requests have priority over external interrupt requests. Thus. if a timer/counter interrupt
request and external intertupt request occur simultaneously and both are enabled. then the timer/counter interrupt request will be acknowledged.
When any interrupt request is acknowledged, further interrUpts are disabled via the Status register: however. interrupt enable/disable logic associated with the Control register is not affected. Thus. an external interrupt request will
be held pending for the duration of a timer/counter interrupt seivice routine's execution. However. the external interrupt request will be removed if. at any time while it is held pending. external interrupts are specifically disabledvia bit 0
of the Control register. .
. .' ..
.
If a timer/counter interrupt request is generated while an external interrupt service routine is being executed. then
Status register interrupt disable logic will prevent the timer/counter interrupt request from interrupting the external interrupt service routine. However. the timer/counter interrupt request will beheld pending until interrupts" are subsequently enabled at the Status register. If for any reason timer/counter interrupts have been specifically disabled via
Control register bit 1. then any subsequent timer/counter interrupt request will be delayed until timer/counter interrupt
logic is specifically enabled via bit 1 of the Control register.
When an interrupt request is acknowledged. the Program Counter(PCO)"contents a~e s8vedon the Stack register (PC 1).
For a Timer interrupt request. a new value.. 02016.
into the Program
Counter:
'. is loaded
"
I.
a2a16~
I,
~
I
I
~I~'~~
pca
PC1
2-14
When an external interrupt request is acknowledged. Program Counter (PCO) contents are saved in the Stack register
(PCn then the new value OA016 is loaded into the Program Counter (PCO). Thus. interrupt service routines for timer
and external interrupts must originate at memory locations 02016 and OAO 16. respectively.
Since a reset or power-on clears the Program Counter. the beginning of program memory must be allocated thus:
Program
Memory
o
w
~
a:
o0..
a:
o
u
000
...
.:~-·Initialization begins here
020
Timer interrupt service routine
...._...- - begins here
OAO
__
Extemal interrupt service routine
...
-~- begins here
~
ui
w
~
g
fI)
fI)
~
Gl:I
w.
Z
a:
oID
fI)
o
TIMER/COUNTER LOGIC
3870 timer/counter logic represents a significant enhancement over prior F8 logic.
3870 timer/event counter logic consists of an 8-blt binary Counter register together with a Buffer register and
associated logic. The two registers are accessed as I/O Port 7. Data output to I/O Port 7 is written into the Counter
register and the Buffer register. Data input from Port 7 is read from the Counter register only. This may be illustrated
as follows:
::i:
~
Buffer Register
~
@
Out to - - - I/O Port 7
__
_~
In from I/O Port 7
The scheme illustrated above allows timer/counter logic to operate in a "free running" mode. Whenever the contents
of the Counter register decrement to O. the new Counter register contents are taken from the Buffer register. and a
timer interrupt request occurs. This may be illustrated as follows:
Counter
Buffer
Register
Register
. Contents
Contents
02
. xx
01
xx
---.;-------...~ Timer interrupt request
00
xx
xx
xx.
xx-1
xx
xx-2
xx
etc.
etc.
You can read Counter register contents at any time. eVE!n while the timer/counter is operating. by inputting from I/O
Port 7: Counter register contents will be input.
Timer/counter logic can be operated in Interval Timer mode, in Pulse Width Measurement mode, or in Evant
Counter mode. The contents of a Control register (which is accessed as I/O Port 6) determine the mode.in which
timer/counter logic will operate. We will describe the Control register after discussing timer/counter operating
modes.
2-15
In Interval Time~ mode, timer/counter logic is used to compute time intervals. In order to
3870
compute a time interval, the timer/counter register contents are decremented at fixed
INTERVAL
"decrement" intervals. The decrement interval is equal to a number of clock periods. as
TIMER MODE
specified by the control code. The decrement interval may range between a low of two clock
periodsahd a high of 400 clock periods. If. for example. a 500 nanosecond clock is employed and the decrement interval is 100 clock periods. then the Counter register contents will be decremented once every 50 microseconds. If the initial value output to I/O Port 7 is 20010 (C816). then in Interval Timer mode. timer/counter logic will time out once every 10 milliseconds.
Time interval = 0.5 x 100 x 200 microseconds
The time delays which can be generated using timer/counter logic in Interval Timer mode are given by the following
equation:
Time interval = Reset value x Decrement time interval
The reset value is the value written out to I/O Port 7; it may have any value in the range 0 through 255. 0 is in fact
equivalent to a count of 256. since the decrement ends with a Timer interrupt request when Counter register contents
decrement from 1 to O.
In Interval Timer mode, timer/counter logic operates as follows:
1)
An initial value must be output to I/O Port 7. This becomes the reset value.
2)
Using an appropriate control code. you select Interval Timer mode and options. The control code also starts and
stops timer/counter logiC in Interval Timer mode.
3)
Once started by an appropriate control code. the Counter register continuously decrements. reloads. and redecrements.
4)
In order to stop the timer/counter when operating in Interval Timer mode. you must output ari appropriate control
code.
Each time the Counter register decrements to b. a ti~er interrupt request is generated. If timer iniernlp~ requests are
enabled. then the interrupt request will be ackn6wledged; if timer interrupt requests are disabled. the interrupt request
will be latched and will be held pending until timer interrupt requests are subsequently enabled.
If interrupts are enabled when timer/counter logic times out in Interval Timer mode. there will be a small time delay
before the interrupt is acknowledged; no interrupt cah be acknowledged until the conclusion of the currently executing
instruction. plus the next instruction if it is privileged. (Privileged instructions are instructions which cannot be interrupted; they are identified in Table 2-1.) In the worst case. it is possible for 49 clock periods to elapse be.tween the
timer/counter timing out and a timer interrupt being acknowledged; on the average. between 24 and 30 clock periods
will separate these two events. If long delays between a time-out and interrupt acknowledge are not aC<:eptqble. then
you must avoid executing privileged instrLJctions while timer/counter logic is operating in Interval Timer mode.
In P~lse Width Measurement mode, timer/~aunter logic measures the duration of a pulse
which is input on the EXT INT pin. Under program control. you can measure a low pulse:
EXTINT
\
3870'
PULSE ,WIDTH
MEASUREMENT
MODE
I
+
+
START
TIMER
STOP
TIMER
or you can measure a high pulse:
EXTINT
I
\_----
-4
START
TIMER
STOP
TIMER
Stop and start logic represerits the only difference between Pulse Width Measurement mode and Interval Timer mode.
As illustrated above. it is EXT INT signal transitions that start and stop timer/counter logic in Pulse Width mode. In addition. you can use control codes to stop timer/counter logic in Pulse Width mode.
2-16
An external interrupt request occurs at the trailing edge of the EXT INT pulse. This external interrupt request will be
acknowledged only if external interrupts have been enabled. If external interrupts are disabled. no interrupt request occurs. That is to say. if external interrupts are enabled at some point after the end of a pulse. no interrupt request will be
pending.
cw
~
a:
oQ.
a:
o
(J
Within the pulse itself. timer/counter decrement logic works exactly as described for Interval Timer mode. The Counter
register contents are decremented once each decrement interval; the decrement interval is defined in Interval Timer
mode. If the timer/counter does not time-out within the pulse width. then on the trailing edge of the pulse the
timer/counter is stopped. By inputting from I/O Port 7. you read the contents of the Counter register at the trailing edge
of the pulse; the difference between this input value and the initial reset value can be used to compute the pulse duration. as follows:
~
enw
I~
U
oen
Pulse duration = (Initial reset value - final Counter register contents) x decrement time interval
For example. su ppose the initial reset value output to I/O Port 7 is 10010 (6416). while the final value input from I/O
Port 7 is 1610 (1016); if the control code has set timer/counter logic to decrement once every 100 microseconds. then
the pulse width must be 8.4 milliseconds:
en
Pulse width = (100 - 16) x 100 microseconds
~
o!I
w
Z
a:
o
If the Counter register does time-out within a pulse. then a timer interrupt request occurs. the Buffer register contents
are loaded into the Counter register. and decrementing restarts. Program logic must respond to the timer interrupt request by incrementing a scratchpad counter; the total pulse time is computed as follows:
al
en
Pulse duration = (Initial reset value - final Counter register contents)
x decrement time interval
x initial reset value x decrement time interval
x scratchpad counter contents
o
~
~
c
~
@
Suppose. for example. that the initial reset value output to I/O Port 7 is 20010 (C816). and that the Counter register has
timed out three times within the pulse width; the scratchpad counter will now contain 3. If the final value input from
I/O Port 7 is 5310 (3516) and the decrement time interval specified by the control code is 50 microseconds. then the
total pulse timer interval is 37.35 milliseconds:
Pulse interval = (200 - 53) x 50 + 200 x 3 x 50
= 37.350 microseconds
In Event Counter mode, the Counter register contents are decremented on "active" transitions of the EXT INT input. An "active" transition on this signal may be high-to-Iow or low-tohigh. as selected by the control code.
3870
EVENT
COUNTER
MODE
In the Event Counter mode. when the Counter register decrements to 0 a timer interrupt request is
latched. as described for the Interval Timer mode. Thus. if the timer interrupts are enabled. the interrupt request will be acknowledged following execution of the next non-privileged instruction; if timer interrupts are
disabled. the interrupt request will be held until interrupt requests are re-enabled. Active transitions on the EXT INT
signal. while decrementing the Counter register contents. also cause interrupt requests to occur if external interrupts
are enabled. Since it would be pointless to have an external interrupt request occur on every decrement. external interrupts are normally disabled in Event Counter mode.
THE 3870 CONTROL CODE
Operation of 3870 timer/counter logic and interrupt logic is controlled via an 8-bit control code which must bo
output to I/O Port 6. I/O Port 6 is a write-only location. When you input from I/O Port 6, you do not read the contents of the Control register: rather~ the level on the EXT INT pin appoars at bit 7 of the Accumulator. This may
be illustrated as follows:
_~:_g~~~O_elr_~~"':'-';;';;';~$~~~~
I I I I I I I I I
40000000
EXTINT
~}---------------j.' IN
2-17
6
Accumulator
If you need to read the control code after writing it out. then you must keep a copy of it in one of the scratch pad bytes.
Control code bits are assigned as follows:
7
6
5
4
..
3
o
2
",-SitNo.
I I I I I I I I I
I~
I~
~
.~
~.
~
Control code
~
interrupts disabled
~{ o1 Extemal
Extemal interrupts enabled
interrupts disabled
{ o1 Timer/counter
Timer/counter interrupts enabled
INT is active low
{ o1 EXT
EXT INT is active high
Stop timer/counter in any mode
{ o1 Start
timer/counter in Interval Timer or Event Counter modes
~
~
o Interval Timer mode if bits
{
7, 6, 5 are not 000
Event Counter mode if bits 7, 6, 5 are 000
1 Pulse Width Measurement mode. (Do not use 000 for bits 7, 6, 5 in
this mode)
.
+ 2 pre-scalar}
+ 5 pre-scalar
+ 20 p ..-,c,'" ~
+
,---.
7
o
o
o
o
1
6' 5
0
·0
1
1
o
1
o
1
1
1
1
",-SitNo.
o
Event Counter mode
1
0
1
0
1
+ 10 pre_scalar.
+ 20 pre-scalar
+ 40 pre-scalar
'+ 100 pre-scalar
+ 200 pre-scalar
6 . ! ~ ~~:~:~:::~}"
.
.
Pre-scalar x Clock period gives decrement time interval in Interval Timer or Pulse Width Measurement modes
.
.
. '
Bits 0 and 1 are used to selectively enable or disable interrupt requests. External interrupt requests occur via
active transitions on the EXT INT input signal; timer/counter interrupt requests are generated within
timer/counter logic. You have the option of enabling both external interrupts and timer/counter interrupts; you
can enable one but not the other, or you can disable both.
Recall that timer/counter interrupt requests are latched; if timer/counter interrupt logic is disabled (control code bit 1 is
0) whe"n the timerlcounter interrupt request occurs. then the interrupt request will remain pending until timer/counter
interrupts are subsequently enabled (control code bit 1 is 1). or until the 3870 is reset. A reset removes the latched interrupt request. External interrupts are not latched; an external interrupt request will be generated only as EXT INT
makes an active transition while control code bit 0 is 1. A timer/counter interrupt request occurs whenever the
timer/counter register decrements from 1 to O. as previously described.
An external interrupt request occurs whenever an "active" transition is sensed on the EXT INT pin. Bit 2 of the
control code determines what an "active" transition of EXT INT will consist of. If bit 2.is O. then a low level on
EXT INT is considered active. and high-to-Iow transition causes an external interrupt request. If bit 2 of the control code
is 1. then a high level on EXT INT is considered active and a low-to-high signal transition will cause an external interrupt request.
Control code bit 3 is the start/stop bit. This bit must be used to start and stop timer/counter logic when operating in Interval Timer mode or Event Counter mode. When timer/counter logic is operating in Pulse Width Measurement mode.
then leading and trailing edges of an active EXT INT pulse start and stop timer/counter logic; within a pulse. however.
the start/stop bitof the Control code can be used to stop and then restart timer/counter logic.
2-18
In Interval Timer mode or Pulse Width mode. bits 5. 6 and 7 select the decrement time interval. The important point to
note is that bits 5. 6 and 7 are cumulative. Thus. you have seven pre-scalar options shown with the control code.
c
w
~
a:
oQ.
a:
o
o
~
en
w
~
g
C/)
C/)
In Interval Timer mode or in Pulse Width mode. the Counter register contents are decremented once every decrement
time interval. A decrement time interval is equal to the internal clock pulse time multiplied by the pre-scalar. Assuming
a 500 nanosecond internal clock pulse width. 010 in Control register bits 7.6 and 5 would generate a decrement time
interval of 2.5 microseconds. A decrement time interval of 50 microseconds would be generated by 110 in Control
register bits 7. 6 and 5.
THE 38~O/F8 INSTRUCTION SET
Table 2-1 summarizes the 3870/F8 instruction set: instructions are grouped into categories that conform with
our hypothetical microcomputer Instruction set, as described in Volume I, Chapter 7.
.
With reference to Table 2-1. refer to the addressing modes description for an explanation of "r". which occurs in the
operand column to represent some of the scratchpad addressing options.
One of the more confusing aspects of 3870/F8 programming is understanding the ways in which data may be moved
between different registers: this information is therefore summarized in Figure 2-4.
<
a!I
w
Z
a:
o
CD
C/)
o
~.
c<
<
@
The following symbols are used in Table 2-1 :
A
addr
C
data3
data4
data5
DCO
DC1
dpchr
disp
FMASK
The Accumulator
A 16-bit memory address
Carry status
A 3-bit binary data unit
A 4-bit binary data unit
. A 5-bit binary data unit
Data Counter register
Data Counter buffer
Scratchpad Data or Program Counter Half Registers. These are KU (Register 12). KL (Register 13).
(Register 14) and aL (Register 15).
An 8-bit signed binary address displacement
A 4-bit mask composed of a portion of the Status register (W):
3
2
0 ............... Bit No.
I-~--I=FMASK
- - - - - - - - Overflow status
H
ISAR
J
K
o
p4
p8
. PCO
PC1
a
Scratchpad Data Counter Register H (Registers 10 and 11).
The Interrupt Control Bit in the Status register (W).
Indirect Scratchpad Address Register
Scratchpad Register 9
Scratchpad Registers 12 and 13
Overflow status
A 4-bit I/O port number
An 8-bit 1/0 port number
Program Counter
Stack register
Scratchpad Registers 14 and 15
2-19
au
S
sr
TMASK
Any of the following operands and Scratchpad addressing modes:
.
R direct address of bytes 0 through 11
S implied addressing via ISAR
I implied addressing via ISAR. with auto-increment of the low-order
three ISAR bits
D implied addressing via ISAR. with auto-decrement of the low-order
three ISAR bits
Sign status
The register specified by the r argument
A 3-bit mask composed of a portion of the Status register (W):
2
0
~BitNo.
TMASK
~--- Sign status
~----
Carry status
' - - - - - - - Zero status
W
Z
x
[]
[[ ]]
A
V
¥
The CPU Status register
Zero status
Bits y through z of the quantity x. For example. A <3.0> represents the low-order four bits of the Accumulator; addr < 15.8 > represents the high-order eight bits of a 16-bit memory address
Contents of location enclosed within brackets. If a register designation is enclosed within the brackets.
then the designated register's contents are specified. If an I/O port number is enclosed within the brackets.
then the liD port contents are specified. If a memory address is enclosed within the brackets. then the contents of the addressed memory location are specified.
.
Implied memory addressing; the contents of the memory location or register designated by the contents of
a register
Logical AND
Logical OR
Logical Exclusive OR
Data is transferred in the direction of the arrow
Data is exchanged between the two locations designated on either side of the arrow
Under the heading of STATUSES in Table 2-1. an X indicates statuses which are modified in the course of the instructions' execution. If there is no X. it means that the status maintains the value it had before the instruction was executed. A 0 or 1 means the status is cleared or set. respectively.
2-20
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 2-1. 3870/F8 Instruction Set Summary
STATUSESTYPE
-g
MNEMONIC
OPERAND(S)
OPERATION PER-FORMED
BYTES
C
Z
S
0
INS
P4
1
0
X
X
0
(A]-[P4]
IN
PS
2
0
X
X
0
Input to Accumulator from I/O port.
[A]-[PS]
OUTS
P4
1
Input to Accumulator from I/O port.
[P4]-[A]
OUT
PS
2
Output to I/O port from Accumulator.
[PS]-[A]
Output to I/O port from Accumulator.
LM
1
ST
1
LR
A.r
1
LA
A.DPCHR
1
LR
r.A
LR
DPCHR.A
1
LR
DCO.H
1
LR
DCO,o
1
LR
H,DCO
1
LR
o.DCO
1
[O]-[OCO]
IU.
U
Z
IU
a:
IU
~
IU
a:
>a:
0
:E
IU
:E
>a:
ia:
[A]-[[DCO)). [DCO]-[OCO]+ 1
Load the Accumulator via DCO and auto-increment DCO.
[[DCOll-[Al. [OCO]-[OCO+ 11
Store the Accumulator via DCO and auto-increment OCO.
[A]-[SR]
Load the contents of the specified register. SR. into the Accumulator. Increment or decrement
ISAR if specified by r.
[A]-[DPCHR]
Load Accumulator with the conterits of the specified DPCHR.
[SR]-[A]
Load the contents of the Accumulator into the specified register. Increment or decrement ISAR
if specifl8d by r.
[DPCHR]-[A]
Load the contents of the Accumulator into the specifl8d DPCHR.
[DCO]-[H]
Load the contents of Scratchpad registers 10 and 11 into DCO.
[DCO]-[o]
Load the contents of Scratchpad registers 14 and 15 into DCO.
[H]-[DCO]
Load the contents of DCO into Scratchpad registers 10 and 11.
LR
PC1.K
1
. L.oad the contents of DCO lnto Scratchpad registers 14 and 15.
[PCl]-[K]
LR
K,PCl
1
Load the contents of Register K into the Stack register.
[K]-[PCl]
LR
pco,o
1
- Load the contents of the Stack register into Register K.
[pco]-[o]
1
Load the contents of Register
[pCl]-[PCO], (PCO]-[oi
a.
PI<
a into the Program Counter.
Save the f=:ontents of the Program cOunter in the Stack register. then ioad the contents of
Register a into the Program Counter.
Table 2-1. 3870/F8 Instruction Set Summary (Continued)
TYPE
MNEMONIC
OPERANDIS)
STATUSES
BYTES ~---r---T--~~--~--~~
OPERATION PERFORMED
c
z
s
o
AS
x
x
x
x
ASD
x
x
x
x
[Al-:[A]+ [SR]
Add binary the contents of the specified register to the cdntents of the Accumulator. Increment
or decrement ISAR if sPecified by r.
[A]--:-[A]+ [SR]
o
Add decil1)al the contents of the sP ]-oATA3
Load immediate into the upper three bits of the ISAR.
[ISAR<2.0>]-oATA3
Load immediate into the lower three bits of the ISAR.
[DCO]-ADDR
Load immediate data into the DCO.
[A<3.0>]-DATA4
Load immediate data into the lower four bits of the Accumulator ..Clear the high four b!ts of the
Accumulator.
[A]-DATA8
Load immediate data into Accumulator.
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
TYPE
MNEMONIC
OPERAND IS)
OPERATION PERFORMED
BYTES
C
Z
S
0
AI
DATAS
2
X
X
~
x
NI
DATAS
2
0
X
X
0
01
DATAS
2
0
X
X
0
XI
DATAS
2
0
X
X
0
CI
DATAB
2
X
X
X
X
1&1
~
4(
a:
1&1
a.
0
1&1
~
4(
Q
1&1
Exclusive-OR immediate with Accumulator.
::E
~
[A)-[A) + DATAS
Add immediate to Accumulator:
[A)-[A) A DATAS
AND i.r:nmediate with Accumulator.
[A)-[A) VDATAS
OR immediate with Accumulator.
[A)-[A).y.DATAB
DATAB - [A]
Compare immediate: subtract Accumulator contents from immediate data. but only the status
f1,!I;1.~ are affected.
a.
::E
..,
PI
ADDR
3
BR
DISP
2
JMP
AD DR
3
:;)
[pcll-[PCOl. [PCO)-ADDR
Save Program .Counter in Stack register. then load immediate address into Program Cou·nter.
[pcO)-[PCO)+DISP
Add immediate displacement to contents of Program Counter.
[PCO)-ADDR. [A)-ADDR<15.B>
Load irnmediate address into Program Counter.1.oad the high order byte of the address into the
Accumulator,
Z
0
·E
Q
BT
. DATA3.DISP
2
BF
DATA4.DISP
2
BP
DISP
2
Be
DISP
2
BZ
DISP
2
If DATA3 VTMASK4 0 then [PCO)-[PCO) + DISP
OR the 3 bits of immediate data with the current TMASK.lf any resulting bit is a 1. add the displacement· to PCO.
If DATA4 =FMASK. then [PCO)-[PCO)+DISP
If the 4 bits of immediate data are equal to FMASK. add the displacement to PCO.
If[S] = 1 then [PCO)-[PCO)+ DISP
Branch relative if the Sign bit is set.
If [e) = 1 then [PCO)-[PCO)+ DISP
Branch relative if the Carry bit is set.
If [Z) =; 1 then [PCO)-[PCO)+ DISP
8M
DISP
2
If [S) =utnen lrCO]-[PCO)+ DISP
BNC
DISP
2
BNZ
DISP
2
.Branch relative if the Sign bit is reset.
If [C) =0 then [PCO)-[PCO)+ DISP
Branch relative if the Carry bit is reset.
If [Z] =0 then [PCO)-[PCO]+DISP
BNO
DISP
2
Branch relative if the Zero bit is reset.
If (0) =0 then· [PCO]-[PCO)+ DISP
BR7
DISP
2
Branc~ !.ellltive !!'!!J~ Zero bit is set.
Z
0
U
Z
0
:z:.
U
Z
4(
a:
ID
Branch relative if the Overflow bit is reset.
If [ISAR <2.0 » = 7 then [PCO)-[ PCO) + DISP
If the low three bits of the ISAR are not all 1s. branch relative.
Table 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
TYPE
MNEMONIC
OPERAND(S)
OPERATION PERFORMED
BYTES
C
Z
S
0
S
LR
A.IS
1
[DCO]-[DCll
Exchange:the contents of DCO with the contents of DC1.
[A]-[ISAR]
~~
LR
IS. A
1
Load the contents of ISAR into the Accumulator.
[ISAR]-[A]
a:
XDC
'"I-
1
(/)
"''''
~~
Load the contents of the Accumulator into the ISAR.
[PCO]-[PCll
Load the contents of the Stack register, into the Program Counter.
(/)
S
'"a:
a:
a:
'"I"''''
1-1- c(
(/)(/)
pop
1
ADC
1
0
X
1
0
[DCO]-[DCO]+ [A]
Add the contents of DCO to the contents of the Accumulator, which is treated as a signed binary
number. Store the ,result in DCO.
1
0
X
1
0
0--+f7
a:
SS'"
",,,,IL
a: a: 0
i
SR'
1
of.
Shift the contents of the Accumulator right one bit. The most significant bit becomes a O.
SR
4
1
1
1
0
X
1
0
0000
T
17
l
I
i
0'
Shift the contents of the Accumulator right four bits. The most significant four bits become Os.
'"I-
SL
0
X
X
0
a:
'"0
+--17
IL
a:
,
Ot.-O
Shift the contents of the Accumulator left one bit. The least significant bit becomes a O.
c(
SL
4
1
0
X
X
0
'"
P
l-
(/)
S
w
I
~
0' 0000
T
Shift the contents of the Accumulator left four bits. The least significant four bits become Os.
a:
COM
1
0
X
X
0
[A]-[M
LNK
1
X
X
X
X
Complement Accumulator contents.
[A]-[A]+C
INC
1
X
X
X
X
Add the Carry to the contents of the 'Accumulator.
[A]-[A]+1
CLR
1
Increment the contents of the Accumulator.
[Al-O
Clear the Accumulator.
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 2-1. 3870/F8 Instruction Set Summary (Continued)
STATUSES
TYPE
MNEMONIC
OPERAND(S)
OPERATION PERFORMED
BYTES
C
ICL
:I
a:
a:
1&1
I-
DI
1
EI
1
!:
CI.I
:I
I-
I-
S
O.
[1]-0'
Set the interrupt enable- bit in the Status register•. W, to O.
(1)-1
Set the interrupt enable bit in the Status register, W.to·1.
LR
W,J
1
[W]-[J)
LR
J,W
1
Move the contents of Scratchpad register 9 into the Status register. W.
[J]-[W]
c(
CI.I
Z
Move the contents.of the Status register, W. into Sclatchpad register 9.
NOP
1
No operation is performed. This is not a Haft.
THE 3870 BENCHMARK PROGRAM
The fact that the 3870 has just 64 bytes of read/write memory makes the benchmark program used In this book
somewhat meaningless. We will therefore substitute a program similar to the one given in Chapter 1 for the
TMS1000. A block of data is to be input via I/O Port O. The first byte of data identifies'the length of the data block to
follow: this data block must be less than 48 bytes in length so that it will fit into scratchpad memory starting at
scratchpad byte 1016. Here is the necessary program:
LOOP
INS
LR
L1SU
L1SL
INS
LR
LR
INC
LR
DS
BNZ
0
INPUT FIRST BLOCK LENGTH BYTE
SAVE IN SCRATCHPAD BYTE 0
INITIALIZE ISAR·
O,A
1
0
0
S,A
A,IS
IS,A
o
LOOP
Accumulator
7
INPUT DATA BYTE
SAVE IN NEXT SCRATCHPAD BYTE
INCREMENT ALL SIX ISAR BITS
DECREMENT SCRATCHPAD BYTE 0
RETURN IF NOT ZERO
..
0
I....
7
ISAR
0
I
CPU .
General
: Registers
LR r,A
LR A,r
Register
Address
Poiriter
..
PI, Interrupt, Reset
0
. . .____. tI. _____. .
2
0
3
15
4
Program Counter
5
6
LRJ,W
0
Zero
Carry
Sign
:r
PI
9
J
A
H
B
H
C
K
D
K
E
Q
F
10
Q
Interrupt
Reset
_-_...._-_.......
...........
Stack Pointer
··
LR P,K
•
3'RS3
I
o
Data Counter
Memory
Address
Pointer
PK
8
Overflow
15
POP
7
LR
LR
LR
LR
•
DC,H
H,DC
DC,Q
a,DC
Figure 2-4. Instructions That Move Data Between the Scratchpad and Various Registers
2-26
Table 2-2. Timing and ROMe States for Fa Instruction Set
MNEMONIC:
OPERAND IS)
ADC
cw
~
c:
o
D-
OATA8
AI
~
g
fI)
fI)
c:
oCD
fI)
o
~
<
c
<
@
0
{
No
Branch
BR7
No' Branch
Branch
BT
No
Branch
Branch
CI
DATA4,DISP
{
BF
Branch
t
DISP
{
DATA3,DISP
1
CM
COM
DCI
ADDR
r
DS
EI
P8
IN
S
0
LR
DCO,Q
S
S
lC
3
S
S
0
LR
H,DCO
S
0
L
S
1
LR
IS,A
INS
Oor 1
0
A,ClI.
A,QU
A,r
lC
1
3
0
LR
J,W
LR
K,P
S
0
S
lC
1
LR
LR
0
LR
3
L
S
3
L
S
S
2
KLA
KU,A
P,K
0
LR
PCO,Q
LR
Q,DCO
11
L
S
E
S
S
S
0
0
L
L
16
19
S
L
L
S
16
19
S
S
S
S
L
L
S
S
L
L
S
S
S
L
L
S
L
0
0
6
9
0
0
0
7
8
0
0
0
15
18
0
L
0
0
L
S
2
0
0
0
0
0
0
S
lC
0
S
1
.-,
3
0
lC
6
S
9·
LR
LR
LR
QL,A
QU,A
r,A
S
S
S
0
0
0
0
W,J
S
lC
S
0
L
3
O.
0
0
LR
L
S
lC
NI
S
0
L
3
lB
DATA8
S
L
NM
NS'
01
0
0
L
L
r
DATA8
S
S
2
0
0
L
3
S
0
2
0
lC
0
OM
2
L
through
15
L
S
L
lC
18
OUT
P8
S
L
L
3
1A
OUTS
Oorl
S
S
lC
OUTS
2
through
15
ADDR
(INTERRUPTI
ADDR
LI
DATA8
LIS
DATA4
DATA3
uSt.
2
O·
ROMe
STATE
S
S
INS
JMP
0
A,IS
A,KL
A,KU
S
S
L
S
S
INC
S
L
S
DCO,H
S
S
S
DI
DATA3
LR'
L
S
DATA8
LISU
LM
0
L
S
S
r
r
. CYCLE.
lC
AMD
AS
OPERAND IS)
S
S
S
L
2
ASD
MNEMONIC
LNK
LR
LR
LR
LR
LR
LR
0
CI/S
w
'3
A
L
S
<
Z
L
S
L
S·
~
en
w
ROMC
STATE
AM
c:
o
o
CYCLE.
0
lC
L
L
08
S
L
L
0
L
S
L.
S
S
S
L
13
3.
C
14
PI
0
3
0
0
0
S
0
L
lC
lA
L
S
L
S
L
L
S
2-27
0
O·
3
D
C
14
0
Table 2-2. Timing: and ROMC States 'for F8 Instruction Set (Continued)
MNEMONIC
OPERAND!S)
, CYCLE,
L
L
S
PI<
:
pop
S
S
s
!RESET}
SL'
SL
SA
SA
Sf
1
4
1
4
B
0
0
0
0
0
5
0
3
0
2
0
0
S
S
L
L
S
L
S
S
XM
xs
r
0
4
0
1C
L
S
DATAB
12
14
S
S
S
XI
ROMC
STATE
The following symbols are used in Table 2-3:
aaaa
Four bits choosing the register addressing mode:
0000-1011 Registers 0 - B directly addressed .
1100 ISAR addresses the register'
1101 ISAR addresses the register. Increment low three bits of ISAR.
1110 ISAR addresses the register. Decrement low three bits of ISAR.
1111 NOP. No operation is performed if aaaa=F16.
cc
Two bits choosing a Scratchpad register:
OO--KU
Scratchpad Register 12
01--KL
Scratchpad Register 13
10--0U . Scratchpad Register 14
11--0L
Scratchpad Register 15
One bit of immediate data.
d
eeee A 4-bit port number.
qqqq A 16-bit address.
rr
An 8-bit signed d,isplacement.
An 8-bit port number.
ss
yy
One byte (8 bits) of immediate data:.
When two numbers are given in the "Machine Cycles" column (for example. 3/3.5). the first is the execution time if no
branch is taken. and the second is execution time if the branch is taken.'
.
2-28
Table 2-3. 3870/F8 Instruction Set Object Code
ODJECT
INSTRUCTION
Q
ADC
~
a:
o0-
AI DATAB
AM
w
a:
o
AMO
AS r
~
ASO r
Be OISP
BF DATA4.DISP
~
8M DISP
CJ
en
w
gen
BNC DISP
BNO DISP
all
BNZ DISP
BP DISP
BR DISP
BR7 DISP
en
ct
w
Z
a:
oCD
BT DATA3.DISP
o
BZ DISP
en
BYTES
BE
1
2.5
2
1
2.5
2.5
1
1
2.5
24
@
yy
BB
B9
. 11008888
11018888
INSTRUCTION
CYCLES
LNK
LR A.DPCHR
LR A.IS
LR A,r
LR DC,H
1
2
3/3.5
3/3.5
LR DC,a
LR DPCHR,A
LR H,DC
3/3.5
3/3.5
3/3.5
LR
LR
LR
LR
2
2
2
3/3.5
LR PC1,K
3/3.5
3.5
BF RR
l0000ddd
RR
2
2
3/3.5
3/3.5
LR
LR
LR
NI
84
2
B2 RR
l00ldddd
RR
1
2
2
91
92
RR
RR
2
2
9B
RR
RR
2
94
Bl
~R
90
~
ct
Q
ct
MACHINE
CODE
RR
3/3.5
RR
CI DATAB
CLR
25
CM
YY
70
2
1
2.5
1
BD
lB
1
1
3
1
1
2.5
1
6
1
2
1
1
2
4
COM
DCI AD DR
DI
2A
DS r
EI
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2.5
THE 3860 CPU
Beginning with the 3860 CPU. we are going to describe the Individual devices of the Fa microcomputer system.
The 3860 CPU and the 3861 PSU descriptions depend on the preceding 3870 discussion for a frame of
reference. That Is to say. these two F8 devices are described as variations of the 3870. rather than as standalone devices.
Functions Implemented on the 3860 CPU are illustrated In Figure 2-6.
These are the functions which one would expect to find on a CPU chip. and which are on the 3860 CPU:
- The Arithmetic and Logic Unit
- The Control Unit and Instruction register
- Logic needed to interface the System 8us with the 'control Signals which are input and output by the CPU
- Accumulator register
There Is no memory addressing logic. and there are no memory addressing registors on the 3860 CPU. Stack
Pointer. Program Counter and Data Counter reglaters are all maintained on memory chips and memory interface
chips.
With the F8 scheme. memory addressing logic will be duplicated if more than one memory device is present in
an F8 microcomputer system. We will discuss shortly how potential contention problems are resolved under
these circumstances.
.
2-29
Logic to Handle
___ Interrupt Requests
---from
External Devices
Data Countensl
Stack Pointer
,
".
Interrupt Priority
Arbitration
-
:·t
Program Counter
Direct Memory
Access Control
Logic
~
System Bus
~
I/O Communication
Serial to Parallel
Interface Logic
t
:.
ROM Addressing
and
Interface Logic
i,{::.
t
Programmable
Timers
~
Read Only
Memory
/
L
Figure 2-5. Logic of the Fairchild F8 3850 CPU
Two advantages accruo from having no momory address logic on the CPU chip:
1)
No address lines are needed on the System Bus. so neither the CPU nor connecting devices need 16 address pins.
These 16 pins are used instead to implement two 8-bit I/O ports at each device.
2)
The real estate on the CPU chip which would have been used by Address registers and memory addressing logic is
available for other purposes; it is used to implement 64 bytes of read/write memory.
Having I/O ports and read/write memory on the CPU chip paves the. way for some very low-cost small
microcomputer configurations; for example. the 3850 CPU and the 3851 PSU form a two-device microcomputer
system. with all of the necessary prerequisites for reasonable performance. Until the advent of the 3870 single-chip
microcomputer. this two-chip configuration represented the lowest cost 8-bit microcomputer on the market.
The disadvantage of removing memory addressing logic from the CPU chip is that standard memory devices can
no longer connoct directly to the System Bus. This bus has no address lines;therefore. separate logic devices must
create the interface needed by standard memories. In the F8 system this is done by the 3852 OMI and the 3853 SMI
devices.
Clock signal generation logic is also part of the 3850 CPU. This is now standard among microcomputers.
2-30
Fa PROGRAMMABLE REGISTERS AND STATUS FLAGS
F8 programmable registers and status flags are Identical to the 3870. For details. refer to the earlier discussion.
Fa ADDRESSING MODES
3870 and F8 addressing modes are Identical. both for scratchpad memory and for external program memory. But
memory addressing logic Is Implemented on F8 memory devices. not on the 3860 CPU.
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Every 3851 PSU contains its own Program Counter (PCOl. Stack register (PS 11. and Data Counter (DCO). The 3851 PSU
has no Data Counter buffer (DC 1).
The 3852 DMI and 3853 SMI devices contain all four Address registers: PCO. PC1. DCO and DC1.
~
Since Address registers are present on every PSU. OMlor SMI device In an F8 microcomputer system. these
registers will be duplicated In any F8 system that contains more than a minimum amount of memory. So long as
the microcomputer system has been correctly configured. this presents no problem. Every memory device contains
identical connections to the common System Bus. and instructions that modify the contents of any Address register do
so identically for all memory devices. For example. if there are three memory devices. and therefore three Program
Counters in an F8 system. every Program Counter is incremented identically after a byte of object code is fetched. This
being the case. Address registers on different memory devices will always contain identical address information.
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Every F8 device that contains memory addressing logic also contains a memory address mask which you must
define when ordering the device. This mask identifies the device's addressed space. Thus. a memory device will only
respond to memory accesses within its address space. So long as no two devices have overlapping address spaces
(and if they do. that is a logic design error) there Is no chance for memory contentions to arise. In order to illustrate
this point. consider the very simple example of an F8 configuration that contains two 3851 PSUs. Each 3851 PSU contains 1024 bytes of read-only memory. Let us assume that 3851 PSU #1 responds to memory addresses in the range
000016 through 03FF16. while PSU #2 responds to memory addresses in the range 040016 through 07FF16. This may
be illustrated as follows:
These two Program
Counters always
contain the
same information
PSU 1
I
PSU 2
~
DCO or PCO
I
DCO or PCO
I
I
I
I II IIII
0
0
0
0
0
0
MASK
PSU 1 responds only if PCO or DCO bits 10 through
15 are 000000. because
0000 16 = 0000000000000002
03FF16 = 00000011111111112
PSU 2 responds only if PCO or DCO bits 10 through
15 are 00000 1. because
0400 16 = 00000 100000000002
07FF16 =00000111111111112
--....-
"-v-"
MASK
MASK
Any memory reference instruction will identify a memory address as the contents of either the Program Counter (PCO)
or the Data Counter (DCO). When this address is in the range 000016 through 03FF16. PSU #1 will respond but PSU
#2 will not. If this address is in the range 040016 through 07FF16. then PSU #2 will respond but PSU #1 will not. A
memory address of 080016 or more will result in neither PSU responding.
There is one circumstance under which memory addressing contentions can arise. Since the 3851 PSU does not contain a DC 1 register. it does not respond to the XDC instruction which exchanges the contents of the DCO and DC 1
registers. Therefore. in an F8 configuration that contains 3851 PSUs together with 3852 DMI and/or 3853 SMI devices.
execution of an XDC instruction will result in 3851 PSU DCO registers containing different information from 3852 DMI
or 3853 SMI DCO registers. If an external data memory reference instruction is now executed. it is possible for a 3851
PSU and 3852 OMlor 3853 SMI device to simultaneously consider itself selected. For example. consider an F8 configuration which contains a 3851 PSU and 3853 SMI. Suppose the 3851 PSU mask causes it to respond to addresses in
the range 000016 through 03FF16. while the 3853 SMI responds to all other memory addresses. Now. if Data Counter
DCO contains 02A316 while the Data Co·unter buffer (DC 1) contains OA7F16. then. following execution of an XDC in-
2-31
struction, nothing will happen to the contents ofthe 3851 PSU DCO register: however, the 3853 SMI DCO register will
contain OA7F16. Any instruction that accesses data memory via DCO will now cause both the 3851 PSU and the 3853
SMI to consider themselves selected.
In F8 configurations that include the 3851 PSU together with 3852 OMlor 3853 SMI devices, the best way of avoiding
memory addressing problems is to not use the XDC instruction. If you do use the XDC instruction, you must be particularly careful to ensure that DCO is never within a 3851 PSU's address space when the XDC instruction is executed.
F8 CLOCK CIRCUITS
Three ways of generating an F8 system clock have been advertised; these are the RC mode, Crystal mode, and
External mode. Only Crystal mode has worked consistently in practice.
Using the Crystal mode, a crystal In the 1 to 2 MHz range connects across the XTLX and XTLY pins; along with
two capacitors (C1 and C2), which provide a highly precise clock frequency:
Vss
RC
C,
XTLY
3850
CPU
D
XTLX
C2
1
VGG
The external crystal (and capacitors), together with internal circuitry, combine to form a parallel resonant crystal
oscillator. The two capacitors should be approximately 15pF. The crystal should have these characteristics:
Frequency: 1 to 2 MHz
Mode of Oscillation: Fundamental
Operating Temperature Range: 0 to 70°C
Equivalent Resistance: 1 to 1.5 MHz - 4750
1.5 to 2 MHz - 3500
Resonance: Parallel
Drive Level: 10mW
Load Capacity: - 15pF
Frequency Tolerance: Per customer's requirements
Holder (case) Style:
You can use an external clock to synchronize an F8 system with external logic. The clock signal must be input to the
3850 XTL Y pin as follows:
Vss
RC
External
Clock
XTLY
3850
CPU
XTLX
2-32
Table 2-4. ROMe Signals and What They Imply
CYCLE
4
ROMC
3 2 1
0
HEX
LENGTH
0
0
0
0
0
00
S.L
Instructio~ Fetch. The device whose address space includes the contents of the PCO register must place
on the Data Bus the op code addressed by PCO. Then all devices increment the contents of PCO.
0
0
0
0
1
01
L
The device whose address space includes the contents of the PCO register must place on the Data Bus
the contents of the memory location addressed by PCO. Then all devices add the 8-bit value on the Data
Bus. as a signed binary number. to PCO.
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0
0
0
1
0
02
L
0
0
0
1
1
03
L.S
The device whose DCO addresses a memory word within the address space of that device must place
on the Data Bus the contents of the memory location addressed by DCO. Then all devices increment
DCO.
Similar to 00, except that it is used for Immediate Operand fetches (using PCO) instead of instruction
fetches.
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. FUNCTION
0
0
1
0
0
04
S
Copy the contents of PCl into PCO.
0
0
1
0
1
05
L
Store the Data Bus contents or write bus contents into the memory location pointed to by DCO. Increment DCO.
0
0
1
1
0
06
L
Place the high order byte of DCO on the Data Bus.
e(
0
0
1
1
1
07
L
Place the high order byte of PCl on the Data Bus.
c1:I
0
1
0
0
0
08
L
All devices copy the contents of PCO into PC1. The CPU outputs zero on the Data Bus in this ROMC
state. Load the Data Bus into both halves of PCO thus clearing the register.
0
1
0
0
1
09
L
The device whose address space includes the contents of the DCO register must place the low order
byte of DCO onto the Data Bus.
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(3
oCI)
CI)
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CI)
o
0
1
0
1
0
OA
L
All devices add the 8-bit value on the Data Bus. treated as a signed binary number. to the Data Counter.
~
0
1
0
1
1
OB
L
The device whose address space includes the value in PCl must place the low order byte of PCl on the
0
1
1
0
0
OC
L
The device whose address space includes the contents of the PCO register must place the c~ntents of
the memory word addressed by PCO onto the Data Bus. Then all devices move the value which has just
0
1
1
0
1
00
S
All devices store in PCl the current contents of PCO. incremented by 1. PCO is unaltered.
0
1
1
1
0
OE
L
The device whose address space includes the contents of PCO must place the contents of the word addressed by PCO onto the Data Bus. The value on the Data Bus is then moved to the low order byte of
0
1
1
1
1
OF
L
The interrupting device with highest priority must place the low order byte of the interrupt vector on the
e(
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Data Bus.
been placed on the Data Bus into the low order byte of PCO.
DCO by all devices.
Data Bus. All devices must copy the contents of PCO into PC1. All devices must move the contents of
the Data Bus into the low order byte of PCO.
1
0
0
0
0
10
L
Inhibit any modification to the interrupt priority logic.
1
0
0
0
1
11
L
The device whose memory space includes the contents of Pc:O must place the contents of the addressed memory word on the Data Bus. All devices must then move the contents of the Data Bus to the
upper byte of DCO.
1
0
0
1
0
12
L
All devices copy the contents of PCO into PC 1. All devices then move the contents of the Data Bus into
1
0
0
1
1
13
L
The interrupting device with highest priority must move the high order half of the interrupt vector onto
the low order byte of PCO.
the Data Bus. All devices must move the contents of the Data Bus into the high order byte of PCO. The
interrupting device will reset its interrupt circuitry (so that it is no longer requesting CPU servicing and
can respond to another interrupt).
1
0
1
0
0
14
L
1
0
1
0
1
15
L
All devices move the contents of the Data Bus into the high order byte of PC 1.
1
0
1
1
0
16
L
All devices move the contents of the Data Bus into the high order byte of DCO.
1
0
1
1
1
17
L
All devices move the contents of the Data Bus into the low order byte of PCO ..
1
1
0
0
0
18
L
All devices move the contents of the Data Bus into the low order byte of PC 1.
1
1
0
0
1
19
L
All devices move the contents of the Data Bus into the low order byte.of DCO.
1
1
O.
1
0
lA
L
During the prior cycle an I/O port timer orinterrupt control register was addressed. The devic\! contain-
1
1
0
1
1
lB
L
All devices move the contents of the Data Bus into the high order byte of PCO.
ing the a~dressed port must move the current contents of the Data Bus into the addressed port.
During the prior cycle the Data Bus specified the address of an I/O port. The device containing the addressed I/O port must place the contents of the I/O port on the Data Bus. (No~e that the contents of
timer and interrupt control regis'ters 'cannot be read back onto the Data Bus.)
1
1
1
0
0
lC
Lor S
1
1
1
0
1
10
S
Devices with DCO and DCl registers must switch registers. Devices without a DCl register perform no
operation.
1
1
1
1
0
IE
L
The device whose address spac'e includes the contents of PCO must place the low order byte of PCO
1
1
1
1
1
IF
L
The device whose address space includes the contents of PCO must place the high order byte of PCO on
None.
onto the Data Bus.
the Data Bus.
F8 CPU PINS AND SIGNALS
3860 CPU pins and signals are illustrated in Figure 2-6. A description of these signals is useful as a guide to the
way in which the F8 microcomputer system works.
11>
WRITE·
VDD
VGG
I/O 03
DB3
I/O 13
I/O 12
DB2
I/O 02
I/O 01
DBl
I/O 11
I/O 10
DBO
I/O 00
ROMCO
ROMCl
ROMC2
ROMC3
---- ..--.. -...
-- '.-..--- --.....
--- -.
-- -----
- -..
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RC
40
XTLX
39
XTLY
38
37 ~ EXT RES
I/O 04
36
DB4
35
I/O 14
34
I/O 15
33
DB5
32
31 ~ I/O 05
30
... I/O 06
DB6
29
28
I/O 16
27
I/O 17
26
DB7
25
I/O 07
24 i - - - VSS
23
INT REO
22
ICB
21
ROMC4
-.. -..
'
-- --
3850
CPU
- -- ..----,--- ------ ..
----- ----,
--- --
Pin Name
Description
Type
·DBO - DB7
.11>. WRITE
I/O 00 - I/O 07
I/O 10 - I/O 17
·ROMCO - ROMC4
·EXT RES
·INT REO
*ICB
RC
XTLX
XTLY
VSS.VDD.VGG
Data Bus Unes
Clock Lines
I/O Port Zero
I/O Port One
Control Lines
External Reset
Interrupt Request
Interrupt Control Bit
Clock Oscillator
Crystal Clock Line
External Clock Une
Power Unes
Bidirectional
Output
Bidirectional
Bidirectional
Output
Input
Input
Output
Input
Output
Input
·These signals connect to the System Bus.
Figure 2-6. Fairchild 3850 CPU Signals and Pin Assi,gnments
The Data Bus lines (DBO - DB7) and the control lines (ROMCO - ROMC4) provide the heart of all data and control
information flow.
The Data Bus lines are common. bidirectional lines. and are the only conduit for data to be transmitted between devices
of an F8 microcomputer system.
A lack of address lines on the System Bus usually means that data and addresses must be multiplexed on a
single set of eight lines - which slows down all memory reference operations; they must now proceed in three
serial increments, rather than in one parallel increment. In the F8 System Bus, multiplexing is rarely needed,
since addresses originate within memory devices, or memory interface devices" whence they are transmitted
directly to memory. In other words. the only time addresses are ever transmitted on the Data Bus is when they are
being transmitted as data.
Refer to Fig~re 2-1. Suppose a memory reference instruction needs to access a by'te o,f dynamic RAM. ROMC control
signals (described in the next paragraph) specify that the memory byte whose address is implied by the Data Counters
, (DCa) is to be 'referenced. Every memory device receives the ROMC control signals. but only the 3852 DMI finds that its
address space includes the Data Counter implied address; therefore. only the 3852 DMI will respond to the/memory
reference instruction. The 3852 DMI then outputs an address directly to dyna.mic RAM; this address is not transmitted
2-34
via the System Bus. If the memory reference instruction requires data to be input to or output from dynamic RAM. the
data transfer occurs directly between the System Bus and Dynamic RAM. bypassing the 3852 DMI entirely..
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Since the 3851 PSU. the 3852 DMI and the 3853 SMI devices all contain Address registers and
ROMC STATE
address generation logic. they also coritain rudimentary Arithmetic arid Logic Units equivalent to
very primitive CPUs. These primitive CPUs are driven by 5-bit instructions called ROMC states. ROMC states are output by the 3860 CPU via five control lines, ROMCO - ROMC4. Each five-bit combination of ROMC signal states
identifies one 01.32 possible operations which the memory devices may have to perform to accomplish one step of an
instruction's execution. For example. ROMC state 00000 causes the contents of memory bytes addressed by the Program Counter to be transmitted to the CPU: this is the "instruction fetch" ROMC state. Table 2-4 summarizes the interpretation of ROMC states.
and WRITE are two timing signals output by the 3850 CPU to synchronize events within the rest of the
Fa system.
~
The EXT RES line disables Interrupts and loads a 0 address into all Program Counters. causing program execution to
restart with the instruction code stored in external memory byte O.
en
en
INT REQ and ICB are signals used for overall Interrupt control. INT REO is the master lihe on which all interrupt requests are transmitted to the 3850 CPU. ICB is output low by the CPU if interrupts are enabled. and it is output high by
the CPU if interrupts are disabled.
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The two I/O ports which are part of the 3860 CPU device use pins 1/000 -11007 and 1/010 -1/017, respectively.
RC, XTLX and XTL Yare the three pins used for clock inputs.
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Fa TIMING AND INSTRUCTION EXECUTION
All instructions are executed in cycles, which are timed by the trailing edge of WRITE.
There are two types of instruction cycle, the short cycle which is four clock periods long. and the long cycle
which is six clock periods long. The long cycle is sometimes referred to as 1.5 cycles. WRITE high appears only at the
end of an instruction cycle. Timing may be illustrated as follows:
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.
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I
I
I , ·
I
.
I
I
I
WRITE.~~
---1
I
I
\
I
Start of
End of
End of
new
cycle
short
cycle
long
cycle
,.-_ _.....'
WRITE
I
I
I
\___
The simplest instructiohS of the F8 instruction set execute in one short cycle. The most complex instruction (PI) re.
quires two short cycles plus three long cycles.
Table 2-2 summarizes the sequence in which short (5) and long (L) machine cycles are executed for each F8 instruction. ROMC states defining operations performed during each machine cycle are summarized In Table 2-4.
2-35
The trailing edge of the WRITE pulse triggers the next ROMC state to be output on the ROMCO - ROMC4 lines:
I
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.
.
_rrE.~~~~
I
ROMC
.
I
I
I
.
.
I'
I
:,...~
....- - - -
One short machine cyCle ----.~~:
I
I
For any instruction that only accesses the Accumulator or scratchpad memory. no further System Bus activity is .required. since all subsequent operations will occur within the F8 CPU. This inactivity on the System Bus is used to overlap the last (or only) machine cycle of one instruction with the instruction fetch for the next instruction. For instructions
that execute in a single machine cycle. accessing only logic within the 3850 CPU. timing may be illustrated as follows:
I
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I
I
I
WRITE
I
I
I
:
I
I
I
I
.
Instruction 1 execute
Instruction 2 fetch
Short machine
cycle 1
I
I
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I
I
II
I
I
I
I
I
I
I
I
I
.
Instruction 2 execute
Instruction 3 fetch
Short machine
cycle 2
I
Instruction 3 execute
Short machine
cycle 3
Instructions that do access external memory or I/O ports will always terminate with a machine cycle that does not
cause any System Bus activity: the next instruction is fetched during this machine cycle. This may be illustrated as
follows:
I
WRITE
~~
I
:
I
n
I
______~____~r--\~______~.
I
Instruction 1 execute
Long machine cycle 1
I
Instruction 1 execute
Instruction 2 fetch
Short machine cycle 2
_.__
I
:
I
If for any reason data is to be transferred via the Data Bus during a machine cycle. then the data appears on the Data
Bus at some time which depends on the data source or destination. For details. see the data sheets at the end of this
chapter. There are no accompanying control signals since none are needed: the ROMC state identifies events which are
occurring. Tim}ng for any machine cycle that involves data transfer via the Data Bus may be illustrated as follows:
WRITE
ROMC
DATA
2-36
Fa I/O PORTS
Logic associated with each F8 I/O port pin may be illustrated as follows:
+5V
+5V
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(
Output _ _ _ _ _--,
Strobe
FB)
(f)
oCt
all
~ Data Out ---;~
Latch
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(f)
o
~
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The characteristics of F8 I/O port pins differ markedly from the 3870. The only point of similarity is the fact that both
have inve'rse logic; when you output a 1-bit. OV' is output to external logic; when you write a O-bit. a +5V voltage is
output to external logic. Conversely. external logic must input OV for a 1 input bit and +5V for a 0 input bit.
On reset or power up. F8 I/O port pins are indeterminate. You must therefore start every Reset instruction sequence
with instructions that initialize all I/O port pins. In contrast. the 3870 clears I/O Port 4 and 5 pins on reset; this gener.
ates +5V outputs since logic is inverted.
When using 3870 or F8 I/O ports. the following restrictiors apply:
1)
You must write 0 to every I/O port pin that is to receive data input. This is because external logic cannot write a 0
to any I/O port pin that previously had a 1 bit output by the CPU.
2)
The CPU cannot output a 0 bit (+5V output) to an I/O port pin if the pin is connected to external logic that is inputting a' 1 bit (OV input),
A SUMMARY OF Fa INTERRUPT PROCESSING
The interrupt handling capabilities of the F8 system are described with the 3861 PSU and 3863 SMI devices.
Although many different interrupt priority arbitration schemes could be implemented, the simplest scheme
would be to daisy chain 3861 PSUs, terminating the daisy chain with ~ 3863 8MI if present. '
As soon as an interrupt is acknowledged. the contents of Program Counters (PCO) a're saved in Stack registers (PC 1);
then an interrupt vector address is loaded into the Program' Counters. This address is a permanent mask option for
PSUs. with the exception of bit 7. which discriminates between timer interrupts and external interrupts. The interrupt
address vector is completely programmable for the 3853 SMI. again with the exception of bit 7. which discriminates
device interrupts.
.
between timer interrupts and external
,
,
Post-interrupt housekeeping operations must be handled via an appropriate program. Defining just what this program
consists of is not simple; an F8 system has only the Acc~mulator and Status register which must be saved. but at the
'
other extreme. it has the entire scratchpad which could be saved.
THE Fa INSTRUqTION SET
The F8 and 3870
ins~ruction set~
are identical; for details see Table 2-1 and associated text.
2-37
THE BENCHMARK PROGRAM
Now consider our benchmark program: for the
lOOP
DCI
lM
ADC
XDC
DCI
lM
XDC
ST
XDC
DS
BNZ
lR
lR
DCI
ST
Fa it looks like this:
TABLE
lOAD TABLE BASE ADDRESS
lOAD DISPLACEMENT TO FIRST FREE BYTE
ADD TO BASE ADDRESS
SAVE THIS ADDRESS IN DC1
10BUF
lOAD I/O BUFFER BASE ADDRESS
lOAD NEXT BYTE FROM I/O BUFFER
SWITCH ADDRESSES
STORE IN NEXT BYTE OF TABLE
SWITCH ADDRESSES .
0
DECREMENT I/O BUFFER lENGTH
lOOP
RETURN IF NOT END
H.DC
IF END. STORE SECOND BYTE OF CURRENT
A.Hl
TABLE ADDRESS AS DISPLACEMENT TO
TABLE. FIRST FREE BYTE
The benchmark pr!,gram above makes the following assumptions:
1)
The I/O buffer can be located anywhere in read/write memory.
2)
The number of occupied bytes in the I/O buffer is maintained in scratchpad byte O. Thus. decrementing scratchpad
byte 0 to zero provides the I/O buffer length. .
3)
The
permanent
data table beginning memory
address has all Os for the low-order eight bits:
I
. .
, . . . .
..
The table is not more than 256 bytes long. and the displacement to the first free byte is stored in the first byte of the table. Since the table beginning address has Os in the low~order eight bits. the displacement to the first free byte also
becomes the low-order eight bits of the first free byte address:
Table beginning address
Address of first free byte
pq and rs are hexadecimal digits
All of the above assumptions are valid - and. depending upon the application. may also be realistic. Removing any of
the above assumptions will make the FB program longer. by removing one of the inherent strengths of the F8 instruction set.
2-38
THE 3861 PROGRAM STORAGE UNIT (PSU)
The 3861 PSU has been the principal read-only memory program storage device in small F8 microcomputer
systems. In addition to providing 1024 bytes of read-only memory, the 3861 PSU has two 8-bit I/O ports, a programmable timer, and interru~t logic.
'.
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o::
o
(.)
~
en
w
The 3861 PSU can also' be used In non-F8 microcomputer systems. The most important and non-obvious advantage of including a 3851 PSU in a non-F8 microcomputer system is the fact that 3851 PSU memory will lie outside of
the microcomputer address space. This is because the 3851 PSU relies on its own memory addressing logic. which exists independent of and parallel to any other memo,rv addressing logic.
Figure 2-7 illustrates functions provided by the 3851 PSU. Device pins and signals are given in Figure 2-8. Pins and signals which are unique to the 3851 PSU are described as part of the general 3851 PSU discussion.
~
g
(I)
(I)
Clock Logic
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0::
o
a:I
(I)
o
Arithmetic and
Logic Unit
Accumulator
Registerts)
:E
c(
c
c(
@
Figure 2-7. Logic of the.Fairchild F8 3851. 3856 and 3857 Programmable Storage Unit
2-39
I/O B7
I/O A7
1
2
3
4
5
6
7
.8
VGG
~
EXTINT
PRiOUT
WRITE
INT REO
PRIIN.
DBDR
9
10
11
12
13
14
15
16
17
18
19
20
ROMC4
ROMC3
ROMC2
ROMCl
ROMCO
VSS
I/O AO
I/O BO
Pin Name
3851
PSU
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Description
I/O AO - I/O A7
I/O BO - I/O B7
DBO - DB7
ROMCO - ROMC4
<1>. WRITE
EXTINT
PRIIN
PRIOUT
INT REO
DBDR
VSS.VDD.VGG
DB7
DB6
I/O B6
I/O A6
I/O A5
I/O B5
DB5
DB4
I/O B4
I/O A4
I/O A3
. I/O B3
. 39
I/O Port A
I/O Port B
Data Bus
Control Lines
Clock Lines
External Interrupt
Priority In
.,
Priority Out
Interrupt Request
Data Bus Drive
Power Supply Lines
DB3
DB2
I/O B2
I/O A2
I/O Al
I/O Bl
DBl
DBO
Type
Input/Output
Input/Output
Tristate. Bidirectional
Input
Input
Input
Input
Output
Output
Output
Input
Figure 2-8. 3851 PSU Signals and Pin Assignments
THE 3851 PSU READ-ONLY MEMORX
Every 3861 PSU has 1024 bytes of read-only'memory, pIps memory addressing logic. The rea'd-only memory
must be defined when the chip is created.
•
.
3861 PSU memory addressing logic consists of a Program Counter (PCO), a Data Counter (DCO), and a Stack
register (PC1L which is in fact a buffer for the Program Counter.
.
There is also a 6-bit page select mask, which must be specified when the chip is created; the
page select represents the high-order six bits of the memory address for all ROM bytes of the
PSU. As such, the page select defines the PSU's address space.
PSU
ADDRESS
SPACE
When a ROMC state output by the 3850 CPU. and received by the 3851 PSU, identifies a memory
reference operation, the ROMC state also identifies whether the memory address is to be found in PCO or in DCa. In
response to this ROMC state, PSU memory addressing logic will compare its 6-bit page select mask with the high-order
six bits of the specified Address regis.ter's contents:
lS 14 13 12 11 10 9 8 76 S 4 3 2 1 0
Bit No.
{xlxlxlxlxlxf ,II I I I I I I I I PCOorDCO
I
I
I
I
I
I
Iy Iy Iy Iy Iy Iy I
Page Select Mask
2-40
If there is coincidence. the 3851 PSU will respond to the memory reference operation: if there is no coincidence. the
3851 PSU addressing logic modifies the contents of Address registers. as might be required by the ROMC state. but it
does not respond to the actual memory reference instruction.
3861 PSU INPUT/OUTPUT LOGIC
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a:
o
ID
Every 3861 PSU has four I/O port addresses assigned to it. These four I/O ports have addresses which are
specified via a 6-blt I/O port address mask, which you must define when you order a 3851 PSU. This mask is interpreted as the 6 high-order bits of an 8-bit I/O port address. These are the four addressable I/O ports:
I/O port address mask: XXXXXX
XXXXXXOO
XXXXXX01
XXXXXX 10
XXXXXX11
I/O Port A
I/O Port B
Interrupt control port
Programmable Timer register
Suppose the 6-bit I/O port mask is specified as 0000112. I/O Ports OC16. OD16. OE16 and OF16 will then be selected.
An I/O port mask of 000000 is illegal. since I/O port addresses 0 and 1 are reserved for the two 3850 CPU I/O ports.
The two 8-bit I/O ports of a 3861 PSU are identical to the 3860 CPU I/O ports which we have already described.
except for one detail: there are three optional I/O port pin logic configurations available with a 3861 PSU.
The first option is the standard configuration which we described for the 3850 CPU I/O port pins.
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o
The second option is open drain configuration. which maybe illustrated as follows:
:!
0(
c0(
@
-----------...,
I
VOO'
I
I
(a)
-
~--(b)
TTL Input
L_
y
I
I
X
I
I
I
I
I
--~;_----.--
I
I
I
I/O Port
r
rI
I
I
I
I
I------(c)
I
I
_______ _":::: ",::... J
TTL Output
IL- _ _ _ _ _ _ _ _ _
__
This open drain configuration allows you to wire-OR outputs from a number of pins.
2-41
The third option is a driver pull-up configuration designed specifically to drive LED displays. This configuration may be
illustrated as follows:
------------,I
I/O Port
VDD
VDD
I
I
LED
I
I
R
x ----.0---1
__
~
________ --l
3851 PSU INTERRUPT LOGIC
The 3851 PSU can receive external interrupt requests or interrupt requests from its programmable timer. These
two sets of interrupt logic can be selectively enabled or disabled via a control code written to the interrupt controll/O port. This control code is interpreted as follows:
I/O Port No: X X X X X X 1 0
6
4
3
2
o ....--BitNo.
~L
o .
. Control code
. { O. 0 Disable all interrupts
0 1 Enable external interrupt
Disable timer interrupt
.
1 0 Disable all interrupts
1 1 Enable timer interrupt
.
Disable external interrupt
onb~
care
Its
:
.
.
External interrupt request logic may be illustrated as follows:
From
external
logic
From higher
priority device
in daisy chain
EXT tNT
PRIIN
--1
t··
'INT REQ
---~"'I'+----""I"'~· PRI OUT
To thtl CPU
To lower
priority device
in daisy chain
An external interrupt request is generated by external logic pulling EXT INT low. The interrupt request will be passed
on to the CPU by outputting INT REO low. providing these two conditions are met:
1)
External interrupts have been enabled via the interrupt control code (01 in the two low-order bits).
2)
The PRI IN signal is low.
2-42
If EXT INT is low and external interrupts are enabled. an interrupt is~requested:· whether or not it is
acknowledged. PRI OUT is output high. The combination of the PRI IN and PRI OUT signals is designed to implement
daisy chain interrupt priority logic. which may be illustrated as follows:
c
1iN-rREQ~~----~----------------~--------------~&---------------~~-------
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a:
o
Device 1
o
Device 3
Device 2
Device 4
~
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ct
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ct
ct
C
@
When an active interrupt request occurs at one device. outputting PRI OUT high disables external interrupt logic at all
lower priority devices in the daisy chain.
An interval timer interrupt request is generated when the programmablo timer I/O port decrements to zero. This
interrupt request will be acknowledged if programmable timer interrupts have been enabled via the interrupt control
1/0 port (11 in the two low-order bits).
.
There is no priority arbitration between external interrupts and programmable timer interrupts. since one or the other
but not both can be enabled at any time.
When the CPU acknowledges an interrupt request, the 3861 PSU responds by saving Program Counter (PCO)
contents in the Stack register (PC1), then loading an interrupt sorvice routino starting address into the Program
Counter (PCO). This Interrupt service routine starting address is a mask option which you must specify when ordering the 3861 PSU. One bit of the interrupt address vector (it is bit 7) is set aside to identify the interrupt request a8 external or a8 coming from the programmable timer. This may be illustrated as follows:
15
14
13
12
11
10
9
8
6
5
4
3
2
Interrupt address vector
t
V
/ t'-
f
/
!
J 0 '",ert_d fo< ,,,,",,,mmeble tlme< 'ote"",1
1 1 inserted for external interrupt
~------------------••- - - - - - - - - Mask defined address bits
The actual interrupt response sequence consists of five machine cycles. during which ROMC states are output in the
order 1016. 1C16. OF16. 1316.0016. Table 2-4 identifies functions performed in response to each ROMC state.
2-43
Table 2-5. Relationship Between Programmable Timer Contents and Effective Timer Counts
TIMER
CONTENTS
TIMER
COUNTS
TIMER
CONTENTS
TIMER
COUNTS
TIMER
CONTENTS
TIMER
COUNTS
TIMER
CONTENTS
TIMER
COUNTS
TIMER
CONTENTS
TIMER
COUNTS
FE
FO
FB
F7
EE
DC
B8
71
E3
C7
8E
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
F5
EA
04
A9
52
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
BC
79
F2
E4
C9
93
27
4E
9C
38
70
El
C3
86
OC
18
31
63
C6
8C
19
33
67
CE
90
3A
74
E9
02
A5
4B
96
20
5B
B7
6E
DO
BA
75
EB
06
AD
5A
B5
6A
05
AB
56
AC
58
B1
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
62
C4
88
11
22
44
89
13
26
4C
98
30
61
C2
84
08
10
20
40
81
02
05
OB
16
2C
59
B3
66
CC
99
32
65
CA
95
2B
57
AE
5C
B9
73
E7
CF
9F
3E
7C
F8
Fl
E2
C5
8A
15
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2A
55
AA
54
A8
50
AO
41
83
06
00
lA
35
6B
07
AF
5E
BO
7B
F6
EC
08
BO
60
CO
80
00
01
03
07
OF
lE
3D
7A
F4
E8
DO
A1
43
87
OE
lC
39
72
E5
CB
97
2F
5F
BF
7F
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10
3B
76
ED
OA
B4
68
01
A3
47
8F
IF
3F
7E
FC
F9
F3
E6
CD
9B
36
60
DB
B6
6C
09
B2
64
C8
91
23
46
80
lB
37
6F
OF
BE
70
FA
A4
49
92
25
4A
94
29
53
A6
40
9A
34
69
03
A7
4F
9E
3C
78
FO
EO
Cl
82
04
09
12
24
48
90
21
42
85
OA
14
28
51
A2
45
8B
17
2E
50
BB
77
EF
DE
Timer counts are decimal numbers
Timer contents are hexadecimal numbers
2-44
3861 PSU PROGRAMMABLE TIMER LOGIC
The 3861 PSU has a single programmable timer which Is addressed as the fourth I/O port (XXXXXX112). This
"
timer is free running unless it contains the value FF16. The value FF16 stops the timer.
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The Interval timer Is a polynomial shift register. Table 2-6 gives the correlation between timer counts and timer
register contents.
'
,
The programmable timer dec'rementsonce every 31 clock periods. Using a 500rianosecond c!ock. therefore. the timer
'
register will decrement once every 15.5 microseconds.
In order to generate any specific, time interval. you must load an initial value into the programmable timer register by
outputting the appropriate,timer contents to the programmable timer I/O port address. For example. in order to have an
initial value of 10016. you must load the programmable timer I/O port with the value C416. Loading the programmable
timer with the initial value 2816 will generate an initial count of 16410. These correlations can be read off Table 2·5.
Once the programmable timer times out. it reloads the value FE16. representing 25410 counts. and starts to decrement
,,,.
again.
3861 PSU DATA TRANSFER TIMING
When data Is Input to the 3861 PSU from the Data Bus, no control signals are needed since the ROMC state sig·
nals identify the presence of data on the Data Bus. When data Is output by the 3861 PSU, however, the control
output DBDR is low. Timing ~ay be illustrated as follows:
In
CI)
o
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ct
Q
ct
@
WRITE--...I
ROMC----------------------R-------------~~~-----------------------------
DATAOUT--------------------------------------~~-----------------------------
5B5R--------------------------------------~
The purpose of the low DBDR signal is 'to prevent Data Bus contentions from ever'arising. This is also a very useful sig·
nal in non·F8 microcomputer systems that include a 3851 PSU. since it can be used as a data read strobe., '
,
' . '
,
. '
;:,..;~ r"·
,:.J
USING THE 3861 PSU IN NON-F8 CONFIGURATIONS
The 3861 PSU is easily included in non-F8 microcomputer configurations. The trick is to generate ROMC s1ates
as memory addresses. A ROMC state of 1C idles the 3861 PSU. Appropriate logic is illustrated, in Figur~ 2·9.
Let us consider some examples. For simplicity. we will use 8080A assembly language mnemonics and assurl1~ that the
3851 PSU is selected by addresses FFED16 through FFFF16. This is how data input and data output'via 3851 PSU I/O
ports could be implemented. in conjunction with the logic of Figure 2·9:
•
F8 Instructions'
IN
PORT
OUT
PORT
ROMC States
03
1B
00
03
lA
80aOA Instructions
MVI
APORT
STA
OFFE3H
LDA "OFFFBH
MVI
LXI
MVI
STA
MOV
2-45
APORT
OFFFAH
B.DATA
OFFE3H
M.B,
--
··..
··..
---
~
---
.
~
:;;:
~
.
.-
•
n
T
,r
t
,
..
l
~
2 IN
1 OUT
SELECT
-
A4
A5
A15
DO
D7
iN'fR"EQ
CLOCK
SYNC
,. ... ,.
CLOCK
DERIVATIVE
LOGIC
SELECT
LOGIC
··.--..;.
AO
-....
··..-
·-
DBO --- DB7 I/O AO - I/O A7
~
WRITE
ROMC
ROMC4
I/O BO - I/O B7
3851
PSU
+
1'11002 ,
¢::>
4+ .+
--
I~ I~ I~
Figure 2-9. Conceptual Logic to Include a 3851 PSU in a Non-F8 Microcomputer System
Possibly the most useful application for a 3861 PSU in some other microcomputer system would be to implement lookup tables. The 1024 bytes of read-only memory could store data tables of that size. The Program Counter
and Data Counter are active Address registers which can be used to identify ,the location which must be looked up.
By way of illustration. consider a decimal multiplication table look-up program. 100 bytes of read-only memory could
be set aside to store the product of any two single decimal digits. This may be illustrated as follows:
Memory location: 00---0910 11 12-~"'19 20 21 22---293031 etc.
Contents: 00---000001 02---09000204---180003 etc.
Now. in order to compute any decimal multiplication. the two decimal digits are loaded into the eight low-order Data
Counter bits: the contents of the memory location addressed by the Data Counter are then read. Again assuming that
the 3851 PSU is selected by memory addresses FFED16 through FFFF16. and using 8080A assembly language
mnemonics in conjunction with Figure 2-9. appropriate instructions may be illustrated as follows:
ROMC States
19
02
8080A Instructions
MVI
. STA
LDA
46H
OFFF9H
OFFE2H
These instructions seek 4 x 6: 24 will be returned to the Accumulator.
These are just some conceptual examples of how the 3851 PSU can be used in non-F8 configurations. Clearly. the
specific microprocessor being used to drive the 3851 PSU will have a significant influence on the exact interface used
and the 3851 logic capabilities which are or are not accessible.
2-46
THE 3861 AND' 3871 PARALLEL 1/0 (PIO) DEVICES
The 3861 PIO contains the I/O ports, programmable timer, and Interrupt logic of the 3861 PSU. This device contains no memory; It Is otherwise Id!~11~al to the 3861 PSU. Figure 2-8 provldes38~1 PIO signals aod pin assignments.
. .
.
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The 3871 has the I/O ports, timer/counter and Interrupt logic of the 3870 single-chip microcomputer. 3871 PIO
signals and'pln ~sslgnment., are Identical to the 3851 PSU Illustrated In Figure 2-8, with the exception that the
3870 STROBE signal __ gsoclated with 1/9 Port 4 Is output at pl~ 12.
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THE 3866 AI\IP 3867 16K PROGRAMMABLE
\
STORAGE UNITS (16K PSU)
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These two devices .are enhancements
?f and repl~cements for the 3861
PSU which we have just described.
Superficially. Figure 2-7 represents t~e logi~ implemented on all three PSUs-the 3851.3856 and 3857. Table 2-6
summarizes the differences between the devices. These are tho most significant features of the 3866 and 3867
PSUs:'
.!'
c',, .
'
a:
oCD
1)
RESET sets all I/O port pins and address lines to zero. In the 3851. PSU RESET leaves 110 port pins indeterminate ','
.
and this has caused problems in'marw applications.
2)
The interval timers of the 3856 arid 38q7 PSUsare binary decremel'lters rather than polynomial shifters -with the
result that you can read timer contents directly and determine lapsed times. Also. a programmable option allows
you to measure pulse widths being input to the PSu.
.I
. .
3)
The 3857 PSU uses the 16 pins of the two 8-bit I/O ports for 16 address lines. so that additional ROM or RAM can
be interfaced directly to a 3857 PSU "':":'" without requiring a 3852 DMI or 3853 SMI. as was the case with the 3851
PSU.
. '
4)
The 3856 and 3857 PSU~ both provide 2K bytes of ROM for program storage: this is twice the program memory
on the 3851 PSU. This significantly.' increases
the
scope of two-device
Fa microcomputer systems.
available
.
,.
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ct
ct
Q
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Figures 2-10 and 2-11 illustrate the pins anq si9flals of the 3856 anq 3857 16K PSUs respectively.
Table 2-6. A Summary of Differences Bem:een 3851. 3856 and 3857 PSUs
FUNCTION
3851 PSU
ROM
I/O Ports
Address lines
Interrupt
signals
1024 !>ytes
2 x 8 bits
None
Interrupt
options
Timer register
Timer decrement
interval
Timer stop/start
control
Timer readback
Timer read
pulse width?
RESET zero
I/O ports?
3856 PSU
2048 bytes
2 x 8 pits
Non~: .
Priority in and
Priority out
Priority in an~
Priority out
3857 PSU
2048 bytes
None
16
Priority in only.
Must be end of
daisy chain.
Enable timer and/or
external
Enable timer or
external. but not
both
Enabl~ timer and/or
external
~-Dit
No
8-bit Count down
2. 8. 32 or 128
clock cycles
Yes
8-bit Count down
2. 8. 32 or 128
clock cycles
Yes
No
No
Yes
Yes
Yes
Yes
No
Yel>
No I/O ports
Polynomial
31 clock cycl~s
2-47
I/O B7
I/O A7
VGG
VDD
EXfTNf
PRIOUT
, WRITE
<1>
INT REO
PRIIN
DBDR
STROBE
ROMC4
ROMC3
ROMC2
ROMCl
. ROMCO
VSS
. I/O AO
I/O BO
Pin Name
I/O AO- I/O A7
I/O BO - I/O B7
STROBE
DBQ-DB7
ROMCO - ROMC4
<1>, WRiTE
EXTINT
PRIIN
PRIOUT
INT REO
DBDR··
VSS: VDD , VGG
Fig~re
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
3856
16K PSU
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Description·
I/O Port A
I/O Port B
STROBE for I/O Port A
Data Bus
Control Lines
Clock Lines
External Interrupt
Pri9rity In
Priority Out
Interrupt Request
Data Bus Drive
. Power Supply Lines
DB7
DB6
I/O B6
I/O A6
I/O A5
I/O B5
DB5
DB4
I/O B4
I/OA4
I/O A~
170B3
DB3
DB2
I/OB2
I/O A2
I/O A1
I/O B1
DB1
i:>~
Type
Input/Output
Input/Output
Output '
Tristate, Bidirectional
Input
Input'
Input
Input.
Output
Output
Output
2-10. 3856 PSU Signals and Pin Assignments
2-48
c
w
le:(
a:
0
D.
ADDR10
ADDR09
VGG
VDD
EXTINT
ADDR15
WRITE
a:
0
(J
~
u)
w
I-
e:(
U
0
en
en
e:(
~
«1>
INT REO
PRIIN
DBDR
CPU READ
ROMC4
ROMC3
ROMC2
ROMCl
w
~OM~O
a:
en
VSS
RAM vyRITE
ADDR06
Z
0
en
0
:!:
40
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
3857
16K PSU
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
DB7
DB6
ADDR12
ADDR13
ADDR14
ADDRll
DB5
DB4
ADDR07
ADDROO
ADDROl
ADDR03
DB3
DB2
ADDR04
ADDR05
ADDR02
ADDROS
DBl
DBO
,J
e:(
C
e:(
@
Pin Name
Description
ADDROO - ADDR 15
CPU READ
RAMWRITE
DBO - DB7
ROMCO - ROMC4
«1>. WRITE
EXTINT
PRIIN
iNfREQ
DBDR
VSS. VDD.VGG
Address Lines
Memory Read Enable
Memory Write Signal
Data Bus .
Control Cines
Clock Lines
External Interrupt
Priority 'In
Interrupt Request
Data Bus Drive
Power Supply Lines
Type
Output
Output
Output
Tristate. Bidirectional
. Input
Input
Input
Input
Output
. Output
Fig'ure 2-11. 3857 PSU. Signal'S and PiO Assignments
ADDITIONAL F8 SUPPORT DEVICES
There are three additional F8 support devices: the 3862 Dynamic Memory Interface. the 3863 Static Memory
Interface. and the 3864 Direct Memory Access device. We are going to summarize these devices rather than
,. .
give complete descriptions. since th~se devices are infrequently used.
Only F8 configurations with a substantial amount of memory use these devices - and there are very few such F8 configurations: however. in every case there are better alternatives. For example. the 3854 Direct Memory Access device
should not be used to implement direct memorY access logic in·r}on-F8 configurations: the Z80 OMA device is clearly
superior. In fact. signal peculiarities and timing problems associated with the 3852 OMI. 3853 SMI and 3854 OMA
devices make them unattractive components in non-F8 configurations.
If you do need to use the 3852 OMI. the 3853 SMI. or the 3854 OMA d~vices. you will have to refer
since the discussion which follows provides performance summaries only - not product detail.
t~ vendor literature.
THE 3862 DYNAMIC MEMORY INTERFACE (DMI)
Primarily. this device contains the necessary address ge~eratlon and memory refresh logic needed to include
dynamic read/write memory in an F8 system.
Because of the way in which the F8 microcomputer system is organized. however. memory refresh and direct
memory access logic are closely related. That is why. in Figure 2-12. a small part of the direct memory access
control logic is shown as being implemented on the 3862 DMI c~ip.·
.
.
2-49
Clock Log!c
Logic to Handle
Interrupt Requests
from
External Devices
Arithmetic and
, Logic Unit
Accumulator
Registensi
Interrupt Priority
Arbitration '
Syste~
Bus
Interlace Logic
Interlace Logic
Programmable
Timers
Read Only
'Memory
I/O Ports
Figure 2-12. Logic of the Fairchild F8 3852 Dynamic M.emory Interface (OM!). and of the
3854 Direct Memory Acc!3sS (DM~) Devices
2-50
Figure 2-13 illustrates pins and signals of the 3852 OMI.
Conceptually, memory addressing logic of the 3862 OMI is very similar to 3867 PSU memory addressing logic;
there are, however, some differences between the 3862 OMI memory addressing and the 3861 or 3866 PSU:
The 3852 OMI contains two Oata Counters.
and OC 1. The presence of the auxiliary Oata Counter (OC 1) has no
immediate impact on memory addressing logic within the 3852 OMI. However. as we discussed earlier. its presence in an F8 system that also includes a 3851 PSU calls for programming caution.
2)
Oata and address flows surrounding a 3852 OMI are totally unlike the 3851 or 3856 PSU. In the case of these PSUs.
addresses are transmitted entirely within the logic of the PSU; the only communication needed between a PSU and
the CPU is via the eight Oata Bus lines of the System Bus. The OM I. on the other hand. generates a 16-bit address.
which it outputs directly to the read/write memory which it is controlling.
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a:
oca
1)
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0
D.
a:
0
u
~
a
These address pins are equivalent to 3857 PSU address pins -:.. that is. the address pins which CPU would have.
if the CPU contained memory addressing logic for the microcomputer system. In other words. the 3852 OMI creates the address lines and control signals. which. so far as the read/write memory is concerned. are lacking on the
F8 System Bus. The F8 System Bus does. however. contain data lines needed by the read/write memory to actually
transmit data to or from the CPU.
enw
l-
e:(
g
II)
II)
e:(
Oata and address flows around the 3852 OMI may be illustrated as follows:
all
w
Z
a:
0
CD
II)
0
Data lines {
:!
e:(
~
I
Control lines
ce:(
@
Data being
written or read
flows via this
connection
}
D~ta being input to. - - - - - "
or out from address
registers uses this
-P'
Iii.
r
connection
System
Bus
.~
•
r
u
.Dynamic
RAM
K..
Address lines
C,.
Control lines
-
3857 PSU
or
3852DMI
~
I
Address
Space
Master
Enable
3)
Logic
~
.-
Unlike the 3851. 3856 or 3857 PSU. the 3852 OMI has no on-chip logic to determine address space for read/write
memory which the OMI is controlling. Address space determination is made by logic in between the OMI and the
read/write memory. Typically. selected'high-order address lines output by the OMI are gated through elementary
Boolean logic components to create the master enable signal used to strobe attached read/write memory. This is illustrated above.
2-51
VGG
1
40
~
2
3
4
39
38
37
36
VDD
ROMC4
RDMC3
ROMCl
ROMCl
34
33
32
31
ROMCO
CPU READ
REGDR
ADDR15
ADDR14
WRITE
MEMIDLE
CPU SLOT
RAM WRITE
CYCLE REO
ADDR7
ADDR6
ADDR5
ADDR4
,ADDR3
5
6
7
8
9
10
11
DBl
DB2
DB3
12
13
14
15
16
17
18
19
Vss
20
ADDR2
ADDRl
ADDRO
DBO
3852
DMI
30
29
28
27
26
25
24
ADDR13
ADDR12
ADDRll
ADDR10
ADDR9
ADDR8'
DB7
DB6
23
22
2.1
Pin Name
Description
DBO - DB7
ADDRO - AD DR 15
~. WRITE
MEMIDLE
CYCLE REO
CPU SLOT
CPU READ
REGDR
RAM WRITE
ROMCO - ROMC4
VSS. VDD. VGG
Data Bus Lines
Address' Unes
Clock Lines
DMA Timing Une
RAM Timing Line
Timing Line
RAM Timing Line
Register Drive Une
Write Line
Control Lines
Power Lines
DB5
DB4
. Type
Tristate. Bidirectiomil
Tristate, Output
Input
Output
Output
Input/Output
Output
Input/Output'
Tristate. Output
InputInpu~
Figure 2-13. 3852 DMI Signals and Pin Assignments
The process of refreshing dynamic memory and implementing direct memory access are integrally related in an
F8 syste~.
.
'
The presence of a separate DMI interface device means that there can be a limited overlap
between a -memory reference operation which was initiated by the CPU' and a memory
referenc~, operation that Is not Initiated by th~ CPU. '
FaDMI
MEMORY
REFRE:SH
Two types of memory reference operations are not initiated by the CPU: memory refresh
'
and direct .memo~ access.
Let us consfch,r how a direct memory access may follow a CPU-initiated memory read' operation. These are the
events which occur: ,
,.
"
'
,
.
.
,
,
1)
Upon receiving 'an appropriate ROMC state from the CPU. the 3852 DMI, outputs a 16-bit memory address.
together'wJth a read stroQe: these outputs from the 3852 DMI are received by read/write memory.
2)
Read/writ~ m~mory responds by placing data directly on the Data Bus. The data must rema'in stable on the Data
Bu~ until the CPU has had time to read the data.
·2-52
3)
While data is stable on the Data Bus. DMA logic may apply a new memory address to
read/write memory. Following the arrival of address and control signals at read/write memory.
there is a fixed time delay before read/write memory responds by placing data on the Data
Bus. This time delay can overlap with time when prior data must be stable on the Data Bus.
This may be illustrated as follows:
F8 DIRECT
MEMORY
ACCESS
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a:
ono
Add..,. Bu,
a:
o
~ Re,:;m
A, :.."
x...t'__A_~_:_r:_s_s_.JX,",
u
I
~
enw
~
Data Bus
g
CI)
CI)
X
Data stable
to CPU
--..
I
DMA
Data Stable
I
overlap
I
~
n
_ _ __
~
I
cW:I
w
z
a:
o
In
DMI logic outputs control signals which identify the way In which each memory access period is being used;
there are three possibilities:
CI)
1)
Memory is communicating with the F8System Bus.
~
2)
Memory is not communicating with the System Bus. but since it is dynamic memory it is being refreshed.
c
3)
Memory is not Gommunicating with the System Bus and is available for external access.
@
Cases 2 or 3 above may follow case 1 in separate memory access periods of the same instruction cycle.
o
~
~
THE 3864 DIRECT MEMORY ACCESS (DMA) DEVICE
This device receives memory access period Identification signals output by the 3862 DMI. Based on the direct
memory access requirements specified by the currently executing program, the DMA device accesses
read/write memory, during available memory access periods, al defined by the 3862 DMI. Figure 2-14 illustrates 3864 DMA pins and signals.
These are the variables which must be specified for a direct memory access operation:
1)
The beginning address for the memory buffer into which data must be written. or out of which data must be read.
2)
The length of the buffer.
3)
Whether data is to be written or read out of the buffer.
Once a direct memory access operation has been initiated, it proceeds in parallel with other events occurring
within the F8 microcomputer system, using memory access periods which are defined by the 3862 DMI as
available for direct memory access. In other words. direct memory access operations in no way slow down program
execution that may be occurring in parallel.
DMA data transfe~ may be high-speed or low-speed. Low-speed DMA transfer means that each DMA access is
enabled by a signal from the external device. stating that it is ready to transmit or receive data. High-speed access
assumes that the external device will always be ready to transmit or receive data: therefore. every single available
memory access period is utilized.
As a direct memory access operation proceeds. after each access the memory address is incremented and the buffer
length is decremented. Memory address. buffer length and DMA controls are stored in buffers which the CPU accesses
as though they were I/O ports. The contents of these I/O ports may be written into. or read at any time. This means
that the F8 DMA system allows total flexibility for every type of programmable DMA operation; these include
such things as stopping a DMA operation temporarily. or interrogating a DMA operation to determine how far it has
progressed.
Indefinite DMA transfer may also be specified. In this case. no buffer length is given: rather. the DMA operation will
proceed until stopped.
2-53
DIRECTION
1.
ENABLE
XFER
2
XFER'REci
VGG
VDD
ADDR8
. ADDR9
ADDR10
'ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
P1
P2
DB7
DB6
DB5
084
DWS
STROBE
LOAD REG
MEMIDLE
3
4
5
6
7
34
8'
33
9
10
11
12
13
14
15
16
«I>
Vss
3854
DMA
32
ADDRO
ADDR1
ADDR2
ADDR3
ADDR4
29
28
27
17
ADDR5
ADDR6
ADDR7
26 ....t - - READ REG
25
WRITE
24
DBO
18
19
20
23
22
21
DB1
DB2
DB3
Pin Name
Description
Type
Doo - DB7
ADDRO - ADDR 15
«1>. WRITE
LOAD REG/READ REG
P1. P2
MEMIDLE
Data Bus Lines
Address Unes
Clock Lines
Registers Load/Read Line
Port 'Address Select
Memory Idle Une
Transfer Request Line
Control Status Lines
DMA Write Slot. Transfer'
Output Strobe Une
Power Lines
Tristate. Bidirectional
Tristate. Output
Input
Input
Input
Input
Input
Output
Output
Output
XFER'REci
ENABLE. DIRECTION
DWS. XFER
STROBE
VSS,VDD.VGG
Figure 2-14. 3854 DMA Signals and Pin Assignments
THE 3853 STATIC MEMORY INTERFACE (SMI)
,
.
The 3863 SMI provides interface logic for static read/write memory, that is, for memory which does not need to
be refreshed. Logic implemented on this device Is Illustrated in Figure 2-16, and Is a simple combination of functions which have already been described for the 3861 PSU and for the 3862 DMI. Figure 2-16 illustrates 3863
SMI pins and signals.
The description of memory Interface logic which was given for the 3862 DMI applies also for the 3863 SMI. The
3863 SMI, however, does not identify memory access periods, and cannotbe used to Implement direct memory
access.
Becausethe 3853 SMI does not have me'mory refresh or direct memory access supportlogic. there is unused real estate
on the. SMI chip .. The real estate is used to implement a programmable timer and interrupt processing logic. as described for the 3851 PSU. There are. however. two small differences between interrupt logic as implemented on the
PSU ,and the SMI devices: they are:
1)
The 3853 SMI interrupt address vector is not a permanent mask option as it is on the PSU: rather. it is programmable.
2)
The 3853 SMI has no priority output line. which means that in a daisy chain interrupt configuration it must have
lowest priority: that is. it must come at the end of the daisy chain.
2-54
Clock Logic
c
w
~
oa..
ex:
Arithmetic and
Logic Unit
ex:
o
(,J
~
en
w
~
g
CI)
CI)
~
o!I
w
Z
ex:
o
III
CI)
o
~
~
c
System- Bus
ct
@
I/O Ports
Interface Logic
Interface Logic
Read Only
Memory
I/O Ports
Figure 2-15. Logic of the F8 3853 Static Memory Interface (SMJ) Device
2-55
VGG
1
40
«I>
2
3
4
39
38
37
36
35
34
WRITE
INT REO
PRIIN
RAM WRITE
EXfiNT
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDRl
ADDRO
DBO
DBl
DB2
DB3
Vss
5
6
7
8
9
10
"12
3853
SMI
13
14
15
16
17
18
19
20
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
. ROMC4
ROMC3
ROMC2
ROMCl
ROMCO
CPU READ
REGDR
ADDR15
ADDR14
ADDR13
ADDR12
ADDR1l
ADDR10
ADDR9
ADDR8
DB7
DB6
DB5
DB4
Pin Name
Description
Type
000 - DB7
ADDRO - ADDR 15
«1>. WRITE
INT REO
Data Bus Lines
Address Unes
Clock Lines
Interrupt Request
Priority In Line
Write Une
External Interrupt Line
Register Drive Une
CPU Read Line
Control Lines
Power Supply Lines
Bidirectional
Output
Input
Output
Input
Output
Input
Input/Output
Output
Input
PATiN
RAM WRITE
EXTiNT
REGDR
CPU READ
ROMCO - ROMC4
VSS. VDD. VGG
Figure 2-16. 3853 SMI Signals and Pin Assignments
2-56
DATA SHEETS
This section contains specific electrical and timing data for the following devices:
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w
~
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II:
II:
o
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• 3870 One-Chip Microcomputer
.3850 CPU
.3851 PSU
.38520MI
.3853 SMI
.38540MA
·3856 2K P.SU
.3861 PIO
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(j
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CI)
e:(
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II:
o
m
CI)
o
~
e:(
c
e:(
@
2-01
3870
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
0
Temperature Under Bias ....................................................ooe to 70 e
o
Storage Temperature ................................................ ; . -65"e to +150 e
Voltage On Any Pin With Respect To Ground ............................. .- .. -1.0V to + 7V
Power Dissipation .................... _.............. '.' ......................... 1.0W
De CHARACTERISTICS
TA = O°C to 70°C, Vec = 5V ± 10%
SYMBOL
PARAMETER
MIN
MAX
UNIT
TEST CONDITIONS
Outputs Open
Outputs Open
Ice
Power Supply Current
TBD
mA
Po
Power Dissipation
TBD
mW
VIHEX
External Clock
Input High Level
2.4
5 ..
a
V
V,LHEX
External Clock
Inpl.Jt Low Level
-0.3
0.6
V
',HEX
External Clock
Input High Current
100
pA
V'HEX= 2.4V
',LEX
External Clock
Input Low Current
-100
pA
V'LEX= 0.6V
V,H
Input High Level
V,L
Input Low Level
IIH
Input High Current
(except open drain and
direct drive I/O ports)
IlL
Input Low Current
(except open drain and
direct drive ports)
ILOD
Leakage Current
(open drain ports)
10H
Output High Current
(except open drain and
direct drive ports)
-100
IOHDD
Output Drive Current
(direct drive ports)
-1.5
5.8
V
0.8
V
100
pA
V'H= 2AV
internal pull-up
-1.6
mA
V'L=O.4V
10
pA
Pull-down
. device off
2.0
-0.3
-8
pA
VOH=2.4V
mA
VOH= 0.7V
to 1.5V
IOL
Output Low Current
1.8
mA
VOL=O.4V
IOHS
Output High Current
(STROBE Output)
-300
pA
VOH=2.4V
IOLS
Output Low Current
(STROBE Output)
5.0
mA
VOL= O.4V
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Data sheets on pages 2-02 through 2-05 reprinted by permission of Mostek Corporation.
·2-D2
3870
AC CHARACTERISTICS
TA = at to 70t, VCC = +5V ± 10%
SIGNA~
Q
w
~
a:
oa.
SYMBOL
PARAMETER
MIN
MAX
UNIT
to(XTL)
Time Base Period, Crystal Mode
250
1000
ns
4MHz-1MHz
to(LC)
Time Base Period, LC Mode
250
1000
ns
4MHz-1MHz
COMMENTS
a:
XTLl
to(RC)
Time Base Period, RC Mode
250
2000
ns
4MHz-500kHz
u
XTL2
to(INT)
Time Base Period, !nternal Mode
250
590',
ns
4MHz-1.7MHz
to(EX)
Time Base Period, External Mode
250
2500
ns
4MHz-400kHz
tEX(H)
External Clock Pulse Width, High
90
2000
ns
tEX(L)
External Clock Pulse Width, Low
90
2000
ns
t
Internal C!ock Period
2to
typo
ns
0.5 JJS @ 4MHz
ext. time base
STROBE
tl/O-S
Port Output to
3t <1>-1 000 min.
3tcJ>+250 max.
ns
Note 1
1SL
sTROBE
8t -250 min.
12t +250 max.
ns,
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g
CI)
CI)
c(
~
w
2
a:
o
m
CI)
o
:E
c(
Q
c(
@
STROBE
Delay
Pulse Width, Low
RI;SET
tRH
RESET Hold Time, Low
6t + 750 min.
ns
EXT/NT
tEH
EXT INT Hold Time, Active
State
6t + 750 min.
ns
NOTES:
Note 2
1. Load is SOpF plus 1 standard TTL input.
2. Specificatiol"l is applicable when the timer is in the Interval Timer Mode.
See "Timer Characteristics" for EXT INT requirements when in the Pulse Width,
Measure~ent Mode or the Event Counter Mode.
J. The AC Timing Diagrams are given in Figure 5.
CAPACITANCE
TA = 25t:, f=
2MHz
I
SYMBOL
PARAMETER
CIN
IriPlh Capacitance: I/O Ports, RESET, EXT INT '
CXTL
Input Capacitance: XTL 1, XTL 2
MIN
18
2-03
MAX
UNIT
7
pF
23
pF
TEST CONDITION
Unmeasuredcfrins
returned to N D
3870
TIMER CHARACTERISTICS
Definitions:
Error = Indicated tim'e value - actual time value
tpsc
= t x Prescale Value
Interval Timer Mode:
Single interval error, free running (Note 3) .................................... , ±6t
Cumulative interval error, free running (Note 3) ..................................... 0
Error between two Timer reads (Note 2) ............. ; ...... "; ............... ±(tpsc + t to ~(tpsc +t to -(tpsc"+ 7t to ~8t
Load Timer to stop Timer error (Note 1) .. ': ........................ +t to -(tpsc + 2t to -itpsc + 8teil)
Loa~ Timer to interrupt request error (Notes 1,3) ......................... -2t to -9t
Pulse Width Measurement Mode:
Measurement accuracy (Note 4) ..................................+t to -(tpsc +2t <1»
Minimum pulse width of EXT INT pin .............,' .............................2t
Event Counter Mode:
Minimum active time of EXT INT pin ..... ; ......................................2t
Minimum inactive time of Ext I NT pin ........ ~ ..... , ........................... 2t
Notes:
1. All times which entail loading, starting, or stopping the Timer are referenced from the end
of the last machine cycle of the OUT or OUTS instruction.
2. All times which entail reading the Timer are referenced from the end of the .Iast machine
cycle of th~ IN ·or INS in~tructiori.
. . '
.
3. All times which entail the generation of an interrupt request are referenced from the start
of the machine cycle i"n which the appropriate interrupt request latch is set. Additional
time may elapse if the interrupt request occurs during ~ privileged or multicycle instruction:
4. Error may be ~ufl1ulative if operation is rep~tit~"ely perf~rmed.
2-04
3870
External Clock
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w
~
oD.
a:
Internal Clock
a:
o
CJ
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u)
w
...
c(
(3
oCI)
CI)
c(
ail
I/O Port Output
w
Z
f'VO.'
a:
o
a:a
CI)
o
:E
c(
cc(
STROBE
tSL
@
EXTINT
lep BIT
~Ir--------.J'EH
3(~
BITJ
_
Note: All measurements are referenced to VI L max., VIH min., VOL max., or VOH min.
FIGURE 5. AC TIMING DIAGRAMS
2-05
3850 CPU
2.2.2' EI~ctrical Specifications
Absoiuiema;, WRITE
V OH
VOL.
V OH
Output High Voltage
Output Low Voltage
Output High Voltage
XTLY
VIH
VIL
IIH
IlL
Input
Input
Input
I nput
VOH
VOL
c
w
~
a:
oa.
a:
o
o
~
enw
~
ROMCO
CI)
CI)
ROMC4
g
c(
ail
w
Z
.
OB.O
a:
oco
OB7
CI)
o
~
c(
Q
c(
@
1/00
1/0 17
EXT RES
INT REO
reB
TEST CONDITIONS
MIN.
MAX.
UNITS
4.4
VSS
2.9
VOO
0.4
Volts
Volts
Volts
10H = -50 p.A
10L = 1.6 rnA
10H = -100 p.A
4.5
VSS
5
-10
VGG
O.B
50
-120
Volts
Volts
pA
pA
VIN= VOO
VIN = VSS
Output High Voltage
Output Low Voltage
3.9
VSS
VOO
0.4
Volts
Volts
10H = -100 pA
10L = 1.6 rnA
VIH
VIL
VOH
VOL
IIH
IlL
Input High Voltage
Input Low Voltage
Output High Voltage
Outpu~ Low Voltage
Input H igti Current
I nput Low Current
2.9
VSS
3.9
VSS
VOO
O.B
VOO
0.4
3
-3
Volts
Vo'its
Volts
Volts
pA
pA
10H = -100 pA
10L = 1.6 rnA
V IN = 7V 3-State mode
VIN = VSS, 3-State mode
VOH
VOH
VOL
VIH
VIL
IlL
Output High Voltage
Output High Voltage
Output Low Voltage
Input High Voltage (1)
Input Low Voltage
I nput Low Current
3.9
2.9
VSS
2.9
VSS
VOO
VOO
0.4
VOO
O.B
-1.6
Volts
Volts
Volts
Volts
Volts
rnA
10H = -30 p.A
10H = -150pA
10L = 1.6 rnA
Internal pull-up to VOO
VIH
VIL
IlL
Input High Voltage
Input Low Voltage
I nput Low Current
3.5
VSS
-0.1
VOO
O.B
-1.0
Volts
Volts
rnA
Internal pull-up to VOO
VIH
VIL
IlL
Input High Voltage
Input Low Voltage
I nput Low Current
3.5
VSS
-0.1
VOO
O.B
-1.0
Volts
Volts
rnA
VIN = VSS
VOH
VOH
VOL
Output High Voltage
Output High Voltage
Output Low Voltage
3.9
2.9
VSS
VOO
VOO
0.4
Volts
Volts
Voits
IOH = -10 p.A
10H = -100 pA
10L = 100 pA
PARAMETER
High Voltage
Low Voltage
High Current
Low Current
(1)
VIN
= O.4V
(2)
VIN = VSS
Internal pull-up to VOO
Hysteresis input circuit provides additional 0.3V noise immunity while internal pull-up provides TTL
compatability.
.
. (2) Measured while FB port is outputting a high level.
Note:
Positive current is defin~d as conventional current flowing into the pin referenced ..
(3) Guaranteed but ,not tested.
2-D7
3850 CPU
Table 2-4. A Summary of 3850 CPUSignal AC Characteristics
~C Cha:acteristics: VSS = OV, VDD = +5V ± 5%, VGG =+12V ±5910, T A = O°C to +70°C
Symbols in this table are used by all figures in Section 2.
PARAMETER
SYMBOL
Px *
PW ..
x
tXl
MIN.
UNITS
TEST CONDITIONS
External Input Period
0.5
10
pS
200
Px -200
250
nS
tp tf ~30 nS
nS
CL= 100 pf
CL= 100 pf
Ext. to - to - Delay
Ext. to <11+ to + Delay
PtI>
tI> Period
0.5
PWl
td 1
td2
Pulse Width
180
PW2
WRIT!: Pulse Width
PWs
W~!T~
PWL
MAX;
External Pulse Width
txi'
, .td 3
td 4 *
TYP.
250
. 10
nS
pS
P(ll-180
nS'
tI> to WRI~E + Delay
150
250
nS
CL = 100 pf
-'I
td,--I
~
-~I '/,
WRITE
ROMC
~td2
I
~---.---PWS---~==:::;:.~
~~__________~/
~ ___________ _
~PW2~
I
I
:i
- -TRUE
- -ROMC
- -STATE
- - 0- I I
.
X,
I--td 3 - l
I
- I
\1
~tdb3~ll
DATA--------------~------------------~ ~------~----------------BUS _____________
1_____________----J~ OP CODE FOR NEXT INSTRUCTION
I
I
l O N E CYCLE OF A SINGLE CYCLE
I
INSTRUCTION, OR LAST CYCLE OF A
MUL llCYCLEINSTRUCTION
I
NEXT
I INSTRUCTION
Symbols are defined in Table 2-4
Figure 2-1 OA. A Short Cycle Instruction Fetch
ROMC---------------I----~){~________T_R_U_E_R_O_M__
C_S_TA_T_E__
O_______~~--f.-td 3
I
~tdb3-1
-J
:
I
_______________________________________________~~OPCODEFORNEXT
ONE CYCLE OF THE SINGLE, LONG
CYCLE OS INSTRUCTION
(DECREMENTSCRATCHPAD)
I INSTRUCTI0 N
Symbols are defined in Table 2-4
Figure 2-10B.A Long Cycle Instruction Fetch (During DS Only)
2-010
1
NEXT
INSTRUCTION
3850 CPU
cw
PWL
I:
"
(WRITE)J
~
0
tdbl
I
I
STABLE
I
DATA BUS (1)
tdbo~
~
en
w
I
I
I
0
u
I- _____~
I I
0.
a:
'1
I
~
f
I
I
a:
~
PWS
XI
I~
~
c:(
U
I
(HIGH IMPEDANCE)
"I:
DATA BUS (1)
tdb2
STABLE
0
CI)
CI)
c:(
X
DATA BUS
w
2
I~
a:
0
en
X
DATA BUS
CI)
0
~
c:(
STABLE
l~tdb4
ell
tdbS
~
DATA STABLE
X
DATA BUS
~
DATA STABLE
l~tdbs~1
c
c:(
@
1. Timing for CPU outputting data onto the data bus.
Delay tdbl is the delay when data is coming from the accumulator.
Delay tdb2 is the delay when data is comi'ng from the scratch pad (or from a memory device).
Delay tdbO is the delay for the CPU to stop
~riving
the data bus.
2. There are four possible cases when inputting data to the CPU, via the data bus lines: they depend on the data path and the
destination in the CPU, as follows:
tdb3;
tdb4;
tdb5;
tdbS;
Destination
Destination
Destination
Destination
-
IR (instruction Fetch) - See Figure 2-10 for details.
Accumulator (with ALU operation - AM)
Scratch pad (LR K,P etc.)
Accumulator (no ALU operation - LM)
In each case a stable data hold time of 50 nS from the WR ITE refrence point is required.
Symbol~
are defined in Table 2-4
Figure 2-11. Memory Reference Timing
2':'D11
3850 CPU.
11~~-~~~~~-_-_-_-_-_P_WS_-_-_-_-/---~~=~~~~I____________
(WRITE).../
I I
II
---~"~I !..-- th
j.-- tsu
I/O (1)
DATA MAY CHANGE
X
I
I-
to
..
: DATA FROM OLDOUTS
I/O (2)
STABLE
X
:
DATA MAY CHANGE
I
I
I
X---N-E-W-D-A-T-A--+:----------
(1)
This represents the timing for data at the I/O pin during the execution of the INS instruction, i.e., the
CPU is inputting.
(2)
This represents the timing for data being output by the CPU at the I/O pin.
Symbols are defined in Table 2-4
Figure 2-13. Timing for Data Input or Output at I/O Port Pins
~
WRITE
ROMC
~.
PW
s
/
j.- PW2 -.j I
PW L
II
~ -jX
TRUE
INT REO (2)
1
I-
INT REO (2)
EXT RES
I
.. I
1
X
1
\
I
I
:1
.. I
td 5
I
I
I
--~
I
I
~td4~
!::td 5
I
/
:
td 3
ICB (1)
~I
{
tsx
I
1
I
.I
(1)
ICB will go from a 1 to a 0 following the execution of the EI instruction and will go from a 0 to 1
following either the execution of the 01 instruction or the CPU's acknowledgement of an interrupt .
. (2)
This is an input to the CPU chip and is generated by a PSU or 3853 MI chip. The open drain outputs
of these chips are all wire "ANDed" together on this line with the pull-up being located on the CPU
chip. For a 0 to 1 transition the delay is measured to 2.0V.
Symbols are defined in Table 2-4
Figure 2-14. Interrupt Signals Timing
2-012
3851 PSU
3.2.5 . Electrical Specifications
Absolute Maximum Ratings (Above which useful
life may be impaired)
Q
w
~
a:
oQ.
a:
o
CJ
~
enw
t-
c(
U
o
(I)
(I)
c(
c1J
w
2
a:
VGG
VDD
I/O Port Open Drain Option
Exter:nal nHerrupt Input
All other inputs & outputs
Storage Temperature
Operating Temperature
Note: All voltages with r~spectto VSS'
DC Characteristics: VSS = OV, VDD =+5V ± 5%,
VGG ~ +12V ±5%,
T A = O°C to +70°C
o
a:a
SUPPL Y CURRENTS
(I)
o
:!:
c(
Q
c(
@
+ 15V 'to -O.3V
+7Vto -O.3V
+ 15V., to -O.3V
-6ocfjiA to +225 J.l.A
+7V to -O.3V
-55°C to +150°C
O°C to +ib~c
SYMBOL PARAMETER MIN. TYP. MAX. UNITS
IDD
IGG
V
DD
Current
VGG Current
28
60
rnA
TEST·
CONDITIONS
f = 2 MHz.
Outputs
Unloaded
10
30
rnA
f = 2 MHz,
Outputs
Unloaded
'2-013
Table 3-2. A Summary of 3851 PSU Signal Characteristics
3851 PSU
SIGNAL
DATA BUS (D80-D87)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
2.9
VDD
0.8
VDD
0.4
1
-1
Volts
Volts
Volts
Volts
/lA
/lA
10H = -100 /lA ,
10L = 1.6 rnA
VIN = VDD: 3-State mode'
VIN = VSS' 3-State mode
VDD
0.8
3
Volts
Volts
/lA
VIN = VDI:>
VDD'
0.8
3
Volts
Volts
/lA
VIN = VDD
VDD
0.4
Volts
Volts
10H= -100/lA
10L = 100/lA
Open Drain Output (1)
10L": 1 mA
VIN = VDD
VIH
VIL
VOH
VOL
IIH
10L
Input High Voltage
'Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
VIH
VIL
IL
Input High Voltage
Input low Voltage
Leakage Current
4.0
VIH
VIL
IL
Input High Voltage
Input Low Voltage
Leakage Current
3.5
V OH
VOL
Output High Voltage
Output Low Voltage
3.9
INTERRUPT REQUEST
(INT REO)
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
VSS
0.4
3
Volts
Volts
/lA
DATA BUS DRIVE (DBDR)
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
VSS
0.4
3
Volts
/lA
YiN = VDD
VIH
VIL
VIC
IIH
IlL
IlL
Input
Input
Input
Input
Input
Input
0.8
15
10
-225
-500
Volts
Volts
Volts
/lA
/lA
/lA
VIN = VOD
VIN = 2V
VIN = VSS
VOH
VOH
VOL
VIH
VIL
IL
IlL
Output High Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Leakage Current
Input Low Current
VOH
VOL
VIH
VIL
IlL
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Leakage Current
CLOCK LINES (, WRITE)
PRIORITY IN AND CONTROL
LINES (i>'RTTN, ROMCD-ROMC4)
PRIORITY OUT (PRI OUT)
EXTERNAL INTERRUPT
(EXT INT)
I/O PORT OPTION A
(STANDARD PULL-UP)
I/O PORT OPTION B
(OPEN DRAIN)
High Voltage
Low Voltage
Clamp Voltage
High Current
Low Current
Low Current
2-D14
VSS
3.9
VSS
VSS
VSS
VSS
3.5
-150
3.9(5)
2.9
VSS
2.9(3)
VSS
VDD
VDD
0.4
VDD
0.8
1
-1.6
Volts
Volts
Volts
Volts
Volts
/lA
mA
"
External Pull:up
IOL ='2 rnA
IIH = 185'/lA
10H = -30/lA
IOH = .;.150 JlA
10L= 1.6 rnA
Internal Pull-up to VDD [3]
YiN = VDD
VIN =O.4V'(4)
External Pull·up
VSS
2.9(3)
VSS
0.4
\tDD
0.8
2
Volts
Volts
Volts
/lA
10L = 2 ~A
(3)
VIN=+12V
.3861 pSU
A Sumr:riary of 3851 PSU S/gnal Characteristics (Continued)
Table 3-2.
SIGNAL
SYMBOL
PARAMETER
MIN.
VOH
VOL
Output High Voltage
Output Low Voitage
I/O p'ORT OPTION C (DRIVER
PULL·UP)
MAX.
UNITS
3.75
VDO
Vss
0.4
Volts
Volts
TEST CONDITIONS
IOH
IOL
=-1 mA
= 1.6 rnA
c
w
~
oQ.
a:
Notes:
1. Pull·up resistor to VOO on CpU.
2. Positive current is defined conventional current flowing into the pin referenced.
3. Hysteresis input circuit provitJes additionai 0.3V n~ise immunity while internal/external puil-up provides TTL compatibility.
4. Measuted while I/O port is outputting a high level.
5. Guaranteed but not tested.
a:
as
o
u
~
en
w
I-
ct
g
U)
U)
Table 3-3. A Summary of 3851 PSUSignalAC Characteristics'
ct
~
w
Z
a:
om
U)
o
~
ct
c
ct
@
,
AC Characteristics: VSS
;
= OV,
\tOO
= +5V
± 5%, VGG
= +12V
± 5%, TA
= etc
to +70°C
Symbols i~ this table are use8 by aU figures in Section 3.
SYMBOL
PARAMETER
MIN.
Pet>·
PWl
tdl
td2
td4
PW2
PWs
PWL
td3
et> Period
et> Pulse Width
et> to WRITE + De.lay
ct> to WRITE-Delay.
WRITE to bB Input Delay
WRITE Pulse Width
WRITE Period; Short
WRITE Period; Lo'ng
WRITE to ROMCDelay
WRITE to DB Output Delay
WRITE to DB"DR' - Delay
WRITE to i5'BDR -+- Delay
WRITE to INT REO - Delay
WRiTE to ~ + Delay
PRIIN to INT REQ- Delay
PAl IN to PRI OUT -:- Delay
PRIIN to PRi'O'OT + Delax
WRITE to j5§'jQ'O'T + Delay
0.5
180
td7
tds
tn
tf2
tpn
tpdl
tpd2
tpd3
TYP.
MAX.
10
Pet>-180
250
250
2Pet> + 1.0
Pet>
Pet>-100
UNITS
pS
nS
oS
nS
pS
nS
TEST
CONDiTIONS
tr. tl = 50 nS typo
CL = 100 pf
CL = 100 pf
tr. tl = 50 nS typo
4Pet>
SPet>
2Pet> + 100-td2
2Pet> + 200
550
nS
2Pet> + 850 - td2
nS
CL
nS
nS
nS
nS
nS
nS
riS
Open Drain
CL = 100 pf [1]
Cl, = 100 pf [3j
CL = 100 pf [2]
CL = 5ci p~
CL = 50 pf
CL = 50 pf
200
200
430
430
'/
300
= 100 pi
~i:ld~:::}:: ,,;~:~~:to 'PATQij'f ::-:-~~~I:~y : :'i: ::::":.:'::'} ,<' ::) <;: ::;"S( 0 ,,:<:::::;::) 1:<>::Jl ~': ,. tC>:,,~~ ~! ...• '. '.:
. . . i . ? i .iF; . C.••. "'j: •.• •••. ((.... ..;.. •.• . ....."
Ii. •.• '~i'ji~ ."i
~:
II>.:.:.::
•. ::
.•. ; .::: •.
!:. :•. :•. .: •:.••:.•:. :• •. •:.• .•.•:.• . • :•. :.:•.:• \:•.:'
:>.' •..•. .:.:. .:..•
>:::::: -: . : »
.•••
.•
: :••. ).::.:::.:." .:.•:: .••.•.
C:,
>.: ...•..:.c:.'.::
.•:.:.::
I; ·. . •.• iii)
.':.
'"
ili,i{
':::
...
vr' '. ;)( • • i,· .it>
..
[f;11" 1" •.. '.'•
1/'· )j i.·.' , ii.;: 1:(~'i.I .••!
. . •::~., j;i2.;•.sc.•.•.'• . 1·':.,~
. ,'i.· ,. . . . (j,:! •. • ·~l.; :i I i I .·.....ii:] I;i~l '\ li·~i~;.i
~:<.
'>(:.;;~ I'~;
.
.
:.•. : ., .:: .•..
i."
.•.•.
:!..• :.. • • . ::i.
:.i . ·•..•..• :.:.
::.::.: '.'.: ' •.
P.
••.•..••. : •....
Notes:
1. Ass~me Priority In was enabled (PRI IN =0) in previous F8 cycle before interrupt is detected in the PSU.
.
2. PSU has interrupt pending before priority in is enabled.
~.::
3. Assume pin tied to INT REQ input of the 3850 CPU.
4. The parameters which are shaded in the table above represent those which are most frequently of importance when
interfacing to an FB system. Unshaded paramet~rs are typically those that are relevant only between FB chips and not
normally of concern to the user.
5. Input and output capacitance is 3 to 5 pf typical on all pins except VOO, V GG, and VSS'
. 2-015
(.:. '.' ••
3851 PSU.
'I'
,r----- . . . \
LONG CYCLE
ROMC
STABLE
------~-------'
I~----------td7------~--~~
DATA BUS OUTPUT ~_____~I____________________--,~}-______~~S~T~A~B~L_E_____________
I
DBDR
(START OF DATA OUT)
DBDR
(ENDOF DATA
OUT IN SUBSEQUENT
CYCLE)
i
I
j.d8J..,;-.--_ _ _ __
~~I~~·------------~~t-d4::~~~-------~!------------~~--
DATA BUS INPUT __________________________~
STABLE
SYMBOLS ARE DEFINED IN TABLE 3-3
Figure 3-3. 3851 PSU Data Bus Timing
~----~~------------I
WRITE
INPUT (1)
~
I......t----tsu--~..~~~:th
DATA MAY CHANGE
---------------------------'
OUTPUT (2)
_________
(STANDARDPULLUP)
__
DATA STABLE
DATA MAY CHANGE
~I~~-.___ts~p~
------------------~-------------------~~
~2~.9~V~
S~T~A~B~L~E~
~
~
__
______
~~_tOd~
_____________
________
____
___________
OUTPUT (2)
~~
____2_._9V
_______________S_T_A_B_L_E__________________
(OPEN DRAIN) --~------------- -
_----+-_t=--:-"'\td.P~I_
r--
OUTPUT (2)
(DRIVER PULLUP) _______________~
._ _ _ _ _
r--
2.9V
STABLE
SYMBOLS ARE DEFINED IN TABLE 3-3
1. The set-up and hold times specified are with respect to the end ·of the second long cycle during execution of the three·
cycle IN or INS instruction.
2. All delay times are specified with respecUo the end of the second long cycle during execution of the three cycle OUT or
OUTS instruction.
Figure 3-7. Timing at PSU I/O Ports
2-016
3851 PSU
Q
w
~
II:
oa.
~---.....;,-,
I
"
LONG CYCLE
II:
o
CJ
~
en
w
ROMC
t-
ct
g
en
en
INTREQ
ct
ell
w
Z
II:
o
III
STABLE
-------------------'
~~
__
______
~~--t-r-'::i~.____., ______~--------------:I·:======-tr-2----~~
t'pd3j._--+--F-tpd4=i~_
en
o
~
ct
Q
ct
PRIIN ------------------~
~tP't
@
,
i
r_
'\l._
,~tPd,',
PRI OUT
~
EXT INT _________________________________
I
···ft
r
P'2:kv
tPd2
,
....;....---..~ tex~
,~--~----------------
NOTE: TIMING MEASUREMENTS ARE MADE AT VALID LOGIC lEVEL OF THE SIGNALS
REFERENCED UNLESS OTHERWISE NOTED.
SYMBOLS ARE DEFINED IN TABLE 3-3
Figure 3-13. Interrupt Logic Signals' Timing
2-017
Table 4-2. Summary of 3852 DMI Signal Characteristics
3852DMI
SYMBOL
PARAMETER
VIH
VIL
VOH
VOL
IIH
IlL
ADDRESS LINES
(ADDRO-ADDR 15)
AND
RAM WRITE
CLOCK
(til, WRITE)
SIGNAL
MIN. MAX.
UNITS
TEST CONDITIONS
Input High Voltage
I nput Low Voltage
Output Higb Voltage
Output Ldw Voltage
I nput High Current
Input Lbw Current
2.9
Volts
Volts
Volts
Volts
Il A
Il A
IOH = -100 IlA
IOL =1.6 rnA
VIN = VDD, 3-State mode
VIN == VSS, 3-State mode
VOH
VOL
IL
IL
Output High Voltage
Output Low Voltage
Leakage Current
Leakage Current
4.0
VSS
Volts
Volts
Il A
Il A
IOH = -1 rnA
IOL = 3.2 rnA
VIN = VDD, 3-State mode
V IN = V SS' 3-State mode
VIH
VIL
IL
Input High Voltage
Input LolJV Voltage
Leakage Current
4.0
VSS
3
Volts
Volts
Il A
VIN = V DD
MEMIDLE,
CYCLE REQ,
CPU READ
VOH
VOL
Output High Voltage
Output Low Voltage
3.9
VSS
VDD
0.4
Volts
Volts
IOH = -1 rnA
IOL = 2 rnA
CONTROL LINES
(ROMCO-ROMC4)
VIH
VIL
IL
I nput High Voltage
Input LoW Voltage
Leakage Current
3.5
VSS
VDD
0.8
Volts
Volts
3
~A
VIN = 6V
VDD
VDD
0.8
-14.0
Yolts
Volts
Volts
Volts
rnA
IOH = -300 Il A
IOL = 2 rnA
I nternal Pull-up
,3
Il A --
DATA BUS
(DBO-DB7)
..
J
,
REGDR,
CPU SLOT
,
'. ~
VOH
VOL
VIH
ViL
IrL
IL
VSS
3.9
VSS
VDD
0.8
VDD
004
3
-3
VDD
004
3
-3
VDD
0.8
,
Output High Voltage
Output Low Voltage
Input High Vbltage
Input Low Voltage
I nput Low Current
(REGDR)
Leakage Current
3.9
VSS
3.5
VSS
-3.5
O.fl
VIN = OAV & Device
outputting a logic "1"
VIN = 6V
"
2-018
3862DMI
PARAMETER
SYMBOL
pcf)
cw
~
a:
oa..
a:
o
u
~
u)
w
~
g
(/)
(/)
c(
oll
w
2
a:
o
Ul
(/)
o
~
c(
C
c(
@
..
td2
tad1
tad2
• tad3
tad4
tad5
. tad6
tcrl
tcr2
t?Sl
tcs2
tcs3
tml
tm2
tm3
tm4
tCY1
tCY2
tCY3
tCY4
twr1
twr2
twr3
twr4
trgl
trg2
td4
td7
Table 4-3. 3852 OM I Output Signals Timing Summary
MIN.
clock period
to WRITE - Delay
Address delay if PCO
Address delay to high Z (short cycle with DMA on)
Address delay to refresh (short cycle with REF on)
Address delay if DC
Address delay to high Z (long cycle with DMA on)
Address delay to refresh (long cycle with REF on)
CPU READ - Delay
CPU READ + Delay
CPU SLOT + Delay
CPU SLOT - Delay (PCO access)
CPU SLOT - Delay (DC access)
MEMIDLE + Delay (PCO access)
MEMIDLE - Delay (PCO access)
MEMIDLE + Delay (DC access)
MEMIDLE - Delay (DC access)
WRITE to CYCLE REO - Delay
WR ITE to CYCLE REO + Delay
CYCLE REO + to + Edge Delay
CYCLE REO - to - Edge Delay
RAM WRITE - Delay
RAM WRITE + Delay
RAM WRITE Pulse Width
RAM WRITE to High Z Delay
REGDR - Delay
REGDR + Delay
WRITE to Data Bus Input Delay
WR ITE to Data Bus Output Delay
TYP.
MAX.
10
250
50
300 500
tcs2+200
tcs2+50
tcs2+400
tcs2+50
2P+50-td 2
2P+400-td 2
tcs3+50
tcs3+200
tcs3+400
tcs3+50
50.
250 450
2P(I>+50-td 2
2PcI>+400-td 2
80-td 2
320-: td 2
2P+420-td 2
2P+60-td 2
2pcf>+420-td 2
4P+60-td 2
4P(I>+400-td 2
2P+50-td2
4Pc:f>+50-td2
4P+350-td i
4P+50-td 2
4P+400-td 2
6P(I>+50-td 2
6P+350-td2
400-td 2
80- td 2
P+80-td 2
Pcf>+400-td 2
2P(I>
2P(1)
4Pcf>+450-td2
4PeI>+50-td 2
5P(I>+50-td 2
5P(I>+300-td 2
Pel>
350
tcs2+200
tcs2+40
70
300 500
2P(I>+80-td 2
2Pcf>+500-td 2
2P11>+1000
2P(I>+100-td 2
2P(fJ+850-td 2
0.5
UNITS NOTES
",S
nS
nS
nS
nS
nS
hS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Fig. 2-9
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1,4
1,4
1,4
1,4
3
3
3
3
1
1
2
Notes:
1. CL
=
50 pf.
2. CL = 100 pf.
3. CL :: 500 pf.
4. CYCLE REO is a divide-by-2 of (I> for all instructions except the STORE instruction.
5. On a given chip, the timing for all signals will tend to track. For example, if CPU SLOT for a particular chip is fairly slow
and its timing falls out near the MAX aelay value specified, then the timing for all signals on that chip will tend to be out
near the MAX delay values. Likewise for a fast chip whose signals fall near the MIN values. This is a result of the fact that
processing parameters (which affect device speed) are quite uniform over small physical areas on the surface of a wafer.
6. Input and output capacitance is 3 to 5 pf typical on all pins except VDD, VGG' and VSS'
2-019
38520MI
W
I-
a:~
~~
~.
~
d3
~
tad2ta--=--------.t
' '. I
I tad, =1)(~----------~--~><===><---R-E-F-.--~-------><~_R_E_F_.
____
~
~
: 'I:
rnd.
~
rndS
",I:
tadS - - - - - - - - - - - - - - - + 1
.\
" \
~ ~::::g----------- -------~ ~tcs,
'\ - - - - - - - - - ' ,
: I:
~~,
~ I:
g , 'I
" ' 3 ' 1 ·1
,1m,
+
ICY,
•\
I
'
':::J~f--------\
t_m_4~:~:I'-----------------·~1
tCY3 _ _
, \____--J!
\---'--7-_
: --: Icy, I===ICY'~
twr'----------..;....
It:
,-
~
-------------------------------------------------I
:E
~
-\..
·1
~ 1__ "'"-_________-----------------...;...twr4
It:
~-----------------twr2----------------------~
~
~
_ __I _ _ tr_"
-
~I-
t-------------------
1~:~----------tr-g2----------~t-d4-----~~-~-----------~~·~1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...;...________
~£ _~
~!
-
-
~ ~ __I:.:====~~~~~~:::_-_-t_d_7~=============:·~1
~~
~0
~
__
~
_______________~________~______Jx~------------------.
x~--------------
Figure 4-4. Timing Characteristics for 3852 OM I Output Signals
2-020
3852 DMI/3853 SMI
4.2.2
= OV, VOO = +5V ± .5%,
VGG = +12V ± 5%,
T A = O°C to +70°C
OC Electrical Specifications
DC Characteristics: VSS
Absolute Maximum Ratings (Above which useful
life may be impaired).
SUPPL Y CURRENTS
Q
w
!ia::
oa..
a::
o
o
~
iii
+15V to -O.3V·
+7V to -O.3V
+7V to -O.3V
-65°C to +150°C
O°C to +70°C
VGG
VOO
All other inputs & outputs
Storage Temperature
Operating Temperature
TEST
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
100
VOO Current
35
70
rnA
f = 2 MHz,
Outputs
unloaded
IGG
VGG Current
13
30
rnA
f = 2 MHz,
Outputs
unloaded
Note: All voltages with respect to VSS'
w
!i
u
o
(/)
(/)
Table 5-2. 3853 SM I Output Signals Timing Summary
c:(
~
w
Z
a::
oIII
(/)
o
~
c:(
Q
c:(
@
SYMBOL
P
td2
tadl
tad4
tcrl
tcr2
twrl
twr2
t~r3
trgl
trg2
td4
td7
trl .
tpr l .
tex
clock period
to WR ITE - Delay
Address delay if PCO .
Address delay if DCO
CPU READ - Delay
CPU READ + Delay
RAM WRITE - Delay
RAM WRITE + Delay
RAM WRITE Pulse
REGDR - Delay
REGDR + Delay
WRITE to Data Bus
Input Delay
WRITE to Data Bus
Output Delay
WRITE to INT REO - Delay
PRI IN to INT REO - Delay
EXT INT Set·up Time
TYP.
MIN.
PARAMETER
0.5
50
2P+50-td 2
50
2P+50-td 2
4P+50-td 2
5P+50- td 2
350
70
2P+80-td 2
300
250
300
2P+ 100-td2
200
NOTES
MAX.
UNITS
10
250
500
2P+400-td 2
450
2P+400-td 2
4P+450-td 2
5P+300-td 2
P
500
2P+500-td 2
2P+1000
J,lS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
2
3
3
1
1
3
3
3
1
1
2P+850-td 2
nS
2
430
240
nS
nS
nS
2, 6
2, 7
400
Fig. 2-9
Notes:
1. CL = 50 pf.
2. CL
= 100 pf.
3. CL
=500 pf.
4. On a given chip, the timing for all signals will tend to track. For example, if CPU SLOT for a particular chip is fairly slow
and its timing falls out near the MAX delay value specified, then the timing for all signals on that chip will tend to be out
near the MAX delay values. Likewise fora fast chip whose signals fallout near the MIN values. This is a result of the fact
that processing parameters (which affect device speed) are quite uniform.
5. Input and output capacitance is 3 to 5 pf typical on all pins except VDD, VGG, and VSS'
6. Assume Priority In was enabled (PRI IN = 0) in previous F8 cycle before interrupt is detected in the PSU.
7. PSU has interrupt pending before priority in is enabled.
2-021
·3853 SMI
...-w
~
~
~
en
~
~
I'~·
__________________________-L,,---,
______~\________~/______~\~
~tadl --+\_--------_
~----------------x
__________________
I
Xl~
~ ~I1-oI.t-------- tad 4 ------'~~
: E~
"'1
-1\ "'2 -~.I
I
.-..1
"""-1----------- twrl - - - - - - - - -••+0141- twr3,
~ -<--~~~~~~~~~~~~~~~~~~~~~~-t-w-r2--~~~~~~~~~~~~~~\----~.r,.----- ..
I·
td7-~
______________________________
___________________________
~ ~ ---------------------r-------------------------
en ...
~
~
c5
0
--JX~
"2-:1-
I~
I~
I~
I§
2V
ItP)
I
1-- tP'21
~~-------------------~------~I------------~
2V
1__!..___
---~t-~t.
Figure 5-4. 3853 Signal Timing
2-022
3854 DMA
Table 6-3. Summary of 3854 DMA Signal Characteristics
ELECTRICAL SPECIFICA TlONS
Absolute Maximum Ratings (Above which useful life may be impaired)
...
e:(
IX:
o11.
IX:
o
CJ
Note: All voltages with respect to VSS'
en
DC CHARACTERISTICS: VSS = OV, VDD = +5V
~
...w
+15V to -0.3V
+7V to -0.3V
+7V to -0.3V
-55°C to +150 o C
OOC to +70 o C
VGG
VDD
All other Inputs & Outputs
Storage Temperature
Operating Temperature
cw
e:(
± 5%,
VGG = +12V
± 5%, TA = a to +70 o C
SUPPLY CURRENTS
(3
oCI)
CI)
e:(
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
20
15
40
28
mA
mA
.t = 2 MHz, Outputs Unloaded
f = 2 MHz, Outputs Unloaded
o/l
w
Z
IX:
o
VDD Current
VGG Current
IDD
IGG
!Xl
CI)
o
SIGNAL
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
3.5
VDD
0.8
VDD
0.4
1
-1
Volts
Volts
Volts
Volts
pA
pA
IOH = -100pA
IOl = 1.6 mA
V IN = 6V, 3-State mode
VIN = VSS' 3-State mode
VDD
0.4
1
Volts
Volts
pA
IOH=-lmA
IOl = '3.2 mA
VIN = 6V, 3-State mode
VDD
0.4
Volts
Volts
IOH = -100pA
IOL = 2 mA
1
pA
VIN = 6V
~
e:(
c
e:(
DATA BUS (DBO-DB7)
VIH
VIL
VOH
VOL
IIH
III
Input High Voltage
Input low Voltage
Output High Voltage
Output low Voltage
Input High Current
I nput low Current
ADDRESS LINES
(ADDRO-ADDR15)
VOH
VOL
IL
Output High Voltage
Output low Voltage
Leakage Current
4.0
ENABLE, DI RECTION
DWS (DMA WRITE
SLOT), XFER,
STROBE
VOH
VOL
Output High Voltage
Output Low Voltage
3.9
IL
Leakage Current
@
SIGNAL
SYMBOL
PARAMETER
VIH
VIL
IL
LOAD REG, READ
REG, Pl, P2
WRITE,«(l
MEM IDLE, XFER REO
VSS
3.9 '
VSS
VSS
VSS
MIN.
MAX.
UNITS
Input High Voltage
Input Low Voltage
Leakage Current
3.5
VDD
0.8
1
Volts
Volts
pA
VIN = 6Y
VIH
VIL
IL
Input High Voltage
Input Low Voltage
Leakage Current
3.5
VDD
0.8
1
Volts
Volts
pA
VIN = 6V
VIH
VIL
Il
Input High Voltage
Input Low Voltage
Leakage Current
4.0
VDD
0.8
1
Volts
Volts
pA
VIN = 6V
VSS
VSS
0
VSS
a
Note:
Positive current is defined as conventional current flowing into the pin referenced.
2-023
TEST CONDITIONS
Table 6~4. 3854 DMA Device Signals Summary
3854DMA
SYMBOL
P
PW 1
td1
td2
PW2
td3
td4
td6
td7
tdi
td8
tdg
tdg'
td10
td'10
td11
td 11
PARAMETER
Clock Period
Pulse Width
to WRITE + Delay
to WRITE - Delay
WRITE Pulse Width
WRITE to READ/LOAD REG
Delay
DB I nput Set-upTime
XFER REQ to MEM IDLE Set-up
MEM IDLE to ADDR True
MEM IDLE to ADDR 3-State
READ REG to DB Output
WRITE
ENABLE &
01 RECTI ON + Delay
MEM IDLE to ENABLE - Delay
MEM IDLE to, XFER & DWS
+ Delay'
MEM IDLE to XFER & DWS
- Delay
to STROBE + Delay
to STROBE - Delay
to
MIN.
TYP.
0.5
180
60
60
P-100
'
,
200
50
30
40
200
,
30
30
:
MAX.
UNITS
NOTES
10
P-180
300
250
P and W R 'I TE as su ppl ied by the 3850 CPU.
2. Input and output capacitance is 3 to ~ pf typic~·lon all pins except V DD , V GG , and VSS.
, 2-024
Q
w
__________~L~ ____ ~~____~/~---~-~-~~,'~
~
a:
0
D.
a:
0
u
~
----------------------------------------------~)(~-------
en
w
I
l-
e(
g
U)
U)
e(
0
<{
gl!)
CI/S
00:
UJ
a:
0
a:a
U)
0
~
e(
Q
e(
@
r--.,td
-.. UJ
W
Z
<{
0:
(1)-
::>1co::>
<{a..
1-1<{::>
oQ
z
wO
...J-
col<{u
zUJ
.
..
3
-1, X : . . - , - - - - - - - - - - - - -
--------------I-.--------~
I~--------------~--~-------------
1 1 . - tda -1:.,.-;...______~_______
________________________________
~><:~
__________
S_TA_B_L_E____________
1'- td9'-j
~~~~r~-_-_-_--------------+---~~
1
UJ~
0
UJ
...J
e
~
OUJ
UJ~
0:
0:
________________________
~~)f
'. !.- td
6-"
------------------~i
UJ
u..
X
I
I
I
(I)
~~
~~
~...J
,
/
I
~ td7'-1------~--~~--~----~ 'di~
_________________3_.S_TA_T_E______________--J>c~
____A~D~D~R~T~R~U~E~__~I~3~.S~T~A~T~E
I
~ _ _ _ _ _ _---,.--~t----JdlO) .
:_ti~dl
L .'
.. 'd,. ~'t: . . .-._
~ ------------~~----------------------~~~----------------
I-
(I)
Figure 6-5. 3854 DMA Device Signals and Timing
2-025
3856 2K PSU
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage VGG
Supply Voltage Voo
I/O Port Open Drain Option
Other I/O Port Options
All Inputs and Outputs
Storage Temperature
Temperature (Ambient) Under Bias
+15 to -0.3 V
+ito -0.3 V
+15 to -0.3 V
. +7 to -0.3 V
+7 to -0.3 V
-55 to +150°C
to +70°C
o
NOTE 1. Above which useful life may be Impaired. All voltages measured with respect to Vss.
TYPICAL THERMAL RESISTANCE VALUES
SUPPLY CURRENTS
TEST
SYMBOL PARAMETER TYP MAX UNITS
CONDITIONS
100
IGG
Voo Current
VGG Current
75
30
125
45
mA
f = 2 MHz,
mA
Outputs
unloaded
f = 2 MHz,
Outputs
unloaded
PLASTIC:
(}JA (Junction to ambient)
(}JC (Junction to case)
= 60°C/W (Still Air)
= 42°C/W
CERAMIC:
(}JA (Junction to ambient)
(}JC (Junction to case)
= 48°C/W (Still Air)
= 33°C/W
TABLE 1. 3856 PSU SIGNAL DC CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS: Vss = OV, Voo
SYMBOL
PAR~METER
= +5.0V±5%, VGG = +12V ±5%, TA = O·Cto +70·Cunlessotherwisenoted.
SIGNAL
MIN
MAX
UNITS
2.9
Voo
0.8
V
V
V
V
/LA
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input LOW Current
Data Bus (DB o·DB 7 )
Input HIGH Voltage
Input LOW Voltage
Leakage Cumint
Clock Lines (, Write)
. Priority In and Control
3.5
VIL
IL
Input HIGH Voltage
Input LOW Voltage
Leakage Current
Lines (PFiiiN, ROM Co-ROM C4 )
Vss
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Priority Out (PRI OUT)
VOH
VOL
Interrupt Request (INT REO)
I~
Output HIGH Voltage
Output LOW Voltage
Leakage Current
VOH
VOL
IL
Output HIGH Voltage
Output LOW Voltage
Leakage Current
Data Bus Drive (DBDR)
VIH
VIL
VO H
VOL
IIH
10L
V IH
VIL
IL
V IH
Vss
3.9
Vss
4.0
Vss
3.9
Vss·
Vss
Vss
2-D26
TEST CONDITIONS
/LA
10H = -100/LA
10L = 1.6 rnA
VIN = Voo, 3-State Mode
VIN = Vss, 3-State Mode
Voo
0.8
3.0
V
V
/LA
VIN
= Voo
Voo
0.8
3.0
V
VIN
= Voo
Voo
0.4
3.0
-3.0
Voo
0.4
0.4
3.0
0.4
3.0
V
/LA
V
IOH = -100 /LA
= 100 /LA
If
IOL
V
V
Open Drain Output (Note 1)
IOL = 1.0 rnA
/LA
V
/LA
VIN
= Voo
External Pull-up
IOL = 2.0 rnA
VIN = Voo
3866 2K PSU
TABLE 1. 3856 PSU SIGNAL DC CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS: Vss = OV, Vee = +5.0V :5%, VGG = +12V :5%, TA =
SYMBOL
VOL
VIH
VIL
IlL
Input HIGH Voltage
Input LOW Voltage
Input LOW Current
External Interrupt (EXT INT)
VO H
Output HIGH Voltage
VOH
VOL
VIH
VIL
IlL
Output HIGH.Voltage
Output LOW Voltage
Input HIGH VoltagE!
Input LOW Voltage
Input LOW Current
1/0 Port Option A
(Standard Pull-Up)
VOH
VOL
V IH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
VO H
Q
w
~
II:
oD..
II:
o(.)
~
u)
w
~
g
(f)
(f)
ct
o!I
w
VIL
II:
VO H
In
VOL
Z
o
(f)
o
~
ct
Q
«
@
SIGNAL
PARAMETER
Input HiGH Voltage
Output LOW Voltage
Strobe
MIN
MAX
UNITS
3.9
Vee
0.4
V
V
Vee
O.B
-1.6
V
V
mA
Vee
Vee
0.4
V
V
V
V
V
mA
Vss
2.9
Vss
3.9
2.9
Vss
2.9
Vss
Vee
O.B
-1.6
1/0 Port Option B
TEST CONDITIONS
IOH = 1.0 mA
IOL = 2.0 mA
liN = -130 p.A (Internal Pull-up)
VIN = 0.4 V
IOH = -30 p.A, Note 5
IOH = -150 p.A
IOL = 1.6 mA
Internal Pull-up to VOD, Note 3
VIN = 0.4 V, Note 4
External Pull-up
(Open Drain)
Vss
2.9
Vss
Output HIGH Voltage
Output LOW Voltage
o·bto +70·Cunlessotherwisenoted.
I/O Port Option C
(Driver Pull-Up)
4.0
Vss
0.4
IOL = 2.0 mA, Note 3
Vee
O.B
V
V
V
Vee
0.4
V
V
IOH = -1.0 mA
IOL = 2.0 mA
NOTES:
1. Pull-up resistor to VOO on CPU.
2. Positive current is defined as conventional current Ilowing into the pin relerenced.
3. HysteresiS input circuit provides edditional 0.3 V noise immunity while internallexternal pull-up provides TTL compatibility.
4. Measured while 1/0 port is outputting a high level.
5. Guaranteed. but not tested.
.
TABLE 2. 3856 PSU SIGNAL AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS: Vss = 0 V, Voo = +5.0 V :5%, VGG = + 12 V :5%, TA = O·C to + 70·C unless otherwise noted.
SYMBOL
P
PW 1
td 1, td2
td 4
PW2
PWs
PW L
td 3
td7
tda·
tr1
tp r1
PARAMETER
Period
Pulse Width
to Write + Delay
Write to DB Input Delay
Write Pulse Width
Write Period; Short
Write Period; Long
Wr~te
Write
Write
Write
Write
to
to
to
to
to
ROMC Delay
DB Output Delay
DBDA - Delay
DBDR + Delay
INT Req - Delay
MIN
0.5
1BO
P-100
Write to Output Stable
tdp
tsu
th
Write to Output Stable
1/0 Set-up Time
1/0 Hold Time
Ext Int Set-up;Time
Write to Strobe + Delay
Write to Strobe - Delay
tax
tsB1
tsB2
MAX
10
P-1BO
250
UNITS
p's
ns
ns
t r , tl = 50 ns Typ
CL = 100 pF
2P+1.0
p.s
ns
t r , tl = 50 ns Typ
P
TEST CONDITIONS
4P
ns
2P+100-td2
2P+200
550
2P+850-td2
ns
ns
CL = 100 pF
ns
Open Drain
430
CL = 100 pF, Note 1
CL = 100 pF, Note 2
1.0
ns
ns
ns
ns
p's
2.5
p.s
400
ns
p.s
ns
ns
ns
ns
200
PRI In to INT Req - Delay
tpd 1, tpd2 PRI In to PRI Out Delay
tpd 3 • tpd4 Write to PRI Out Delay
Write to Output Stable
tsp
tod
TYP
200
BOO
600
200
1.3
0
400
5P+300
6P+410
CL = 50 pF
CL = 50 pF
CL = 50 pF, Standard Pull-up
Note 3
CL = 50 pF, RL = 12.5 kG
Open Drain, Note 5
CL = 50 pF, Driver Pull-up
CL = 50 pF
CL = 50 pF
NOTES:
1. Assume Priority In was enabled (PRIIN ~ 0) in previous Fa cycle before interrupt is detected in the PSU.
2. PSU has interrupt pending belore priority in is enabled.
3. Assume pin tied to INT REa input 01 the 3850 CPU.
4. The parameters which are shaded in the table above represent those which are most Irequently 01 Importance when interlacing to an Fe system. Unshadad
parameters are typically those that are relevant only between Fe chips and not normaliy 01 concern to the user.
5. Input and output capacitance is 3 to 5 01 typical on all pins except VOO' VCC and VSS'
2-027
3856 2K PSU
WRITE
Id11 _ _
-
Id,
1"
l
r---,
----:-- I-pw,-/ _ld3~1
.
ROMC
.
Id,
LONG CYCLE
STABLE
X
DATA BUS OUTPUT
.\
I
---
STABLE.
-
-.
DBDR
(START OF DATA OUT)
'\..
-Id·-I
DBDR
(END OF DATA OUT
IN SUBEQUENT CYCLE)
.
I
.
Id.
DATA BUS INPUT - - - - - - - - - - - - - - - . . . . ; . . - - - - - - - - * - - - - - - S - T A - B - L - E - - - - -
Fig. 2 DATA BUS TIMING
WRITE
,
'\
,---,
LONG CYCLE
-1"-1
X
ROMC
\
/
STABLE
_I"~
.
I',
• I
2V
~IPd3-1
-"
tpr,
4--tpd,,~
/
-
~tpr2----+-
-'1
.--Ipd,-..
2 V.
4--I Pd2
1-1.,STROBE
"'
.
'ISl
.
'182
Fig. 3 INTERRUPT LOGIC SIGNALS 1/0 STROBE
NOTES:
1. Timing measurements are made at valid logic level to valid logic level
of the signals referenced unless otherwise noted.
2. Symbols are defined in Table 2.
2-D28
.
.
3856 2K PSU/3861 PIO
110 operations that use the two psu 110 ports execute in three instruction cycles. During the first cycle, the port
address is transmitted to the Data Bus. During the second cycle, data is either sent from the Accumulator to the
110 latch or enabled from the 110 pin to the Accumulator depending on whether the instruction is an output or
an input. At the falling edge or Write (marking the end of the second cycle and beginning of the third cycle) the
data is strobed into either the Latch (OUTS) or the Accumulator{ INS) respectively. The third cycle is then used
by the CPU for its next instruction fetch. Figure 4 indicates 110 timing.
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o(.)
~
Data Bus timing associated with execution of 110 instructions does not differ from Data Bus timing associated·
with any other data transfer to, or from the PSU. However, timing at ttie 110 port itself depends on which port
option is being used. Figures 5a, 5b, and 5c illustrate the three ports options. Figure 4 illustrates timing for the
f~ree cases.
WRITE
en
w
~
INPUT III
en
en
ct
OUTPUT (2)
(STANDARD PUllUPI
g
------DA-Tr-A-M-AY-C-H-AN-G-E-~-~X
------r---__Yi'2.9
DATA STABLE
v
STABLE
(OPENO~::~~ (2) ------r---~y~2.9 v
STABLE
.X DATA M~Y CHANGE
a15
w
Z
a:
o
III
en
o
~
OUTPUT (2)
(DR)VER PUllUPI
-----------------~-P--.~)tL----------------------------~--------• F""
2.9V
ct
C
ct
STABLE
Fig. 4 TIMING AT PSU 110 PORTS
@
(1,) The set-up and hold times specified are with respect to the end of the second long cycle during execution of the three cycle IN or INS
instruction.
(2.) All delay times are specified with respect to the end of the second long cycle during execution of the three cycle OUT or OUTS instruction.
:,1
7.2.2
Electrical Specifications
Absolute Maximum Ratings (Above which useful
life may be impaired)
VGG
+15V to -0.3V
VOO
External Interrupt Input
All other Inputs & Outputs
Storage Temperature
Operating Temperature
+7V to -0.3V
-600 p.A to +225 p.A
+7V to -0.3V
-55°e to+150 0 e
oOe to +70o e
SUPPL Y CURRENTS
TEST
SYMBOL PARMJIETER MIN. TYP. MAX. UNITS
CONDITIONS
100
VOo Current
30
70
rnA
f = 2 MHz,
Outputs
Unloaded
IGG
VGG Current
10
18
rnA
f = 2 MHz,
Outputs
Unloaded
Supply Currents measured with VOO = +5V ± 5%,
o
VGG = +12V ± 5%, T A = oOe to +70 e. All other
eleCtric~1 specifications are in Table 7-4. All
voltages ~easured with respect to VSS.
2-D29
3861 PIO·
Table 7-4. A Summary of 3861 PIO Signal Characteristics
MAX.
UNITS
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
3.5
VOO
0.8
VOD
0.4
1
-1
Volts
Volts
Volts
Volts
pA
pA
10H'= -100 pA
10L = 1.6 mA
V IN = 6V, 3-State mode
V IN = V SS' 3-State mode
VIH
VIL
IL
Input High Voltage
Input Low Voltage
Leakage Current
4.0
VDD
0.8
1
Volts
Volts
pA
VIN = 6V
PRIORITY IN AND,
CONTROL LINES
(PRI IN, ROMCOROMC4)
VIH
VIL
IL
Input High Voltage
Input Low Voltage
Leakage Current
3.5
VDO
0.8
1
Volts
Volts
pA
VIN = 6V
PRIORITY OUT
(PRIOUT)
VOH
VOL
Output High Voltage
Output Low Voltage
3.9
VDD
0.4
Volts
Volts
10H = -100 pA
10L = 100 pA
INTERRUPT
REOUEST
(lNT REO)
VOH
VOL
IL
Output High Voltage
Output Low Voltage
Leakage Current
0.4
1
Volts
Volts
pA
Open Drain Output (1]
VSS
DATA. BUS DRIVE
(DBDR) •
VOH
VOL
IL
R~tPut High Voltage
QLitput low Voltage
Leakage Current
VSS
0.4
1
Volts
pA
EXTERNAL
INTERRUPT
(EXT INT)
VIH
VIL
VIC
IIH
IlL
IlL
Input
Input
Input
Input
Input
Input
1.2
15
10
-225
-500
Volts
Volts
Volts
pA
pA
pA
SYMBOL
DATA BUS
(DBO-OB7)
CLOCK LINES
(,WRIT~)
I/O PORT
(STANDARD
PULL-UP)
VIH
VIL
VOH
VOL
IIH
10L
VOH
.- VOH
VOL
VIH
VIL
IlL
IL
PARAMETER
TEST CONDITIONS
MIN.
SIGNAL
High Voltage
Low Voltage
Clamp Voltage
High Current
Low Current
LpVJ Current
Output High Voltage
OutP!Jt High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Leakage Current
I nput Low Current
VSS
3.9
VSS
VSS
VSS
VSS
10L = 1 mA
VIN = 6V
External Pull-up
3.5
-150
3.9
2.9
VSS
2.9
VSS
VDD
VDD
0.4
VOD
0.8
1
-1.6
10L = 2 mA
VIN = 6V
IIH = 185pA
VIN = VDD
VIN = 2V
VIN = VSS
Volts
Volts
Volts
Volts
Volts
10H = -30 pA
10H = -100 pA
10l = 2 mA
Internal Pull-up to VOO (3)
/lA
mA
VIN = 6V
VIN = O.4V (4)
Notes:
1. Pull-lip resistor to V DDDn CPU.
2. POliitive current is defined as conventional current flowing into the pin referenced.
3. Hysteresis input circuit 'provides additional 0.3V noise immunity while internal/external pull-up provides TTL compatibility.
4. Measured while I/O port is outputting a high level.
5. VSS = OV, VDD = +5V
6. Output device off.
± 5%, VGG = +12V ± 5%, T A = O°C to +70°C.
2-D30
3861 PIO
Table 7-5.
AC Characteristics: VSS
A Summary of 3861
PIO Signal AC Characteristics
= OV, Vee = +5V ± 5%, T A = 0
o
e to +70 e
Symbols in this table are used by all figures in Section 7.
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o0-
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
TEST
CONDITIONS
UNITS
a:
o(.)
~
P(ll
0.5
180
60
60
td8,
tr1
tr2·
tp r l
tp r 2
tp d l
tp d 2
tp d 3
tpd4
*t sp
!f> Period
!f> Pulse Width
!f> to WRITE + Delay
!f> to WRITE - Delay
WRITE to DB Input Delay
WR ITE Pulse Width
WRITE Period; Short
WRITE Period; Long
WRITE to ROMC Delay
WRITE to DB Output Delay
WRITE to DBDR - Delay
WRITE to DBDR + Delay
WRITE to INT REO - Delay
WRITE to INT REO + Delay
PRI IN to INT REO - Delay
PRI IN to INT REO + Delay
PRI IN to PRI OUT - Delay
PRI IN to PRI OUT + Delay
WRITE to PRI OUT + Delay
WRITE to PRI OUT - Delay
WRITE to Output Stable
*t su
*th
*t ex
I/O Set-up Time
I/O Hold Time
EXT INT Set-up Time
1.3
0
400
w
Z
PWl
tdl
td2
td4
PW2
PWS
PWL
td3
oal
td7
u)
w
~
oC/)
U
C/)
<
o/S
a:
C/)
o
::?i
<
c
<
@
P-180
250
225
2P!f>+1.0
P
pS
nS
nS
nS
pS
nS
550
nS
2P+850-td 2
nS
t r , tf = 50 nS typo
CL = 100 pf
CL = 100 pf
t r , tf
= 50 nS typo
4P
6P!f>
2P+100-td 2
2P+200
200
430
430
240
240
300
365
700
640
2.5
nS
nS
nS
nS
nS
nS
nS
.nS
nS
pS
CL
= 100 pf
Open Drain
CL = 100 pf (1)
CL = 100 pf [3]
CL = 100 pf [2]
CL = 100 pf
CL = 50 pf
CL = 50 pf
CL = 50 pf
CL = 50 pf
CL = 50 pf.
Standard Pull-up
pS
nS
nS
Notes:
1. Assume Priority In was enabled (PRI IN
=OJ
in previous F8 cycle before interr~pt is detected in the Pia.
2. PSU has interrupt pending before priority in is enabled.
3. Assume pin tied to INT REO input of the 3850 CPU.
*4. The parameters which are starred in the table above represent those which are most frequently of importance when
interfacing to an F8 system. Other parameters are typically those that are relevant only between F8 chips and not normally
of concern to the user.
5. Input and output capacitance is 3 to 5 pf typical on all pins except VDD. VGG. and VSS.
2-D31
3861 PIC
,
(/
r--_---'\
_________...JL __ __ ).'-___I'--_
_~\l..)
_
LONG CYCLE
STABLE
~----~----td7----------~
I~
~
OAT A BUS OUTPUT
STABLE
I
I-
-IX
~-----------td4------------~
DATA BUS INPUT
I
DBDR
(START OF
,DATA OUT)
,
DBDR (END OF
STABLE
i
I~
~----------td7--------~~
•
L
tda
DATA OUT IN
,"
SUBSEQUENT CYCLE)
Figure
'WRITE
7~3.
3861 PIO Data Bus Timing
"
r- =1
. j
'su
\~-----
----l
rJ>
CD
~
w
l-
.
.
..
..)
.
...
DMAREOl
DEVICE
1
DMACKl
I/)
r
I/)
..
..
DM~~E02
~
DEVICE
2
DMACK2
\N"
Figure 3-10. Using SC/MP in a System with Direct Memory Access
3-17
N'ow let us look at how the SC/MP bus-sharing logic might be used in a multiprocessor
system. It is in such a system that the CPU's bus-sharing logic can be most appreciated.
First, let us restate the rules which govern the conditions of the SC/MP ENOUT output
sign~1.
'
,
"
':,i
'
SC/MP IN
MULTIPROCESSOR
SYSTEMS
1)
ENOUTis always low while SC/MP is actually using the System Busses; that is, while the ENIN input and
, BREQ output are both high.
. .'
2) When SC/MP is not using the System Busses (either BREQ output or ENIN input loW), ENOUT is held in the
'
same state as the ENIN input.
The effect of these rules may not be immediately obvious. To see how they function to simplify bus-sharing, let
us construct a 'simple multiprocessor system consisting of two SC/MP CPUs and some memory.
VGG (-7V)
BREQ1
~----t~ ENIN1 ,
ENOUTl
t----.-... ENIN2
BREQ2
SC/M,P
#2
SC/MP
#1
SYSTEM BUSSES
MEMORY
t.::
There are three possible situations that can exist with this configuration.
1)
If one of the CPUs is currently using the bus. it is outputting a high on the BREG line. This automatically prevents
the other CPU from vy'ing for the bus until the BREQ'lire goes low upon completion of the bus access by the first
CPU.
'
2)
If neither CPU is currently using the bus. the BREG line is low. If one of the CPUs requires bus access. it can now
output.a high on the BREG !!Il~' Once again. this will prevent the other CPU from subsequently vyi~g for the bus.
Thus far there would seem to be no need for any control signals except the bidirectional BREQ line. However, it
is when t~e third possibl~ situation is encountered that the ENIN and E"!OU'! signals are needed.
3-18
3)
If both CPUs require bus access at the same time. each will test the BREQ line and. finding it low. will output a high
on BREQ. This simultaneous occurrence of requests for bus access is resolved by using the ENIN and ENOUT signals. The operation of these bus access signals to resolve this situation can be illustrated as follows:
, SC/MP #1 BUS
,ACCESS COMPLETE
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~
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oa..
SC/MP #2 'BUS
ACCESS COMPLETE
BREQl
a:
o
u
BREQ2
~
enw
~
o
II)
ENINl
U
II)
~
ENOUTl
olI
iii
Z
a:
o
ENIN2
al
II)
o
~
~
c
SC/MP #2 GRANTED
BUS ACCESS
BUS ACCESS
~
@
When the BREQ line goes high it applies a high input to the ENIN1 input of SC/MP #1. SinceBREQ 1 is also high at this
time. SC/MP #1 now has access to the bus and it outputs a low on ENOUT1. This is applied to the ENIN2 input to
SC/MP #2 and thus deniesbus,access by SC/MP #2. Notice that SC/MP #2 holds its BREQ2 output signal high even
though its request has not yet been granted. When SC/MP ,#1 has finished, its bus access. the BREQ 1 output returns
low. However. since the BREQ2 output is still high. ENIN1 remains high. This condition of BFlEQ1 low and ENIN1 high
causes the ENOUT1 signai to go high. thus enabling SC/MP .#2.
This arrang~~e~t allows the 'first CPU in a daisy-chain string to have the highest priority for bus access and also
automaticaliy allows any other CPU to gain immediate access to the busses whenever they become availabie.
Now that we have described the .wayin which the bus-sharing logic of the SC/MP CPU can be
SC/MP, CONTROL
used in a multiprocessor system.' let us continue just a bit further and describe a few more
TECHNIQUES IN
common considerations that you must deal with if you are designing a multiprocessor system.
MULTIPROCESSOR
We will limit this discussion primarjiy to hardware and control considerations since programAPPLICATIONS
ming in a multiprocessor system can become quite complex and is beyond the scope of this
book. However. the techniques we will describe here are the first step towards simplifying the programming for such a
"
system.
The first operation that you must deal with in any microcomputer system is initialization of the system. This
operation requires some additional thought when designing a multiprocessor system. Typically. one CPU will be
the primary or controlling CPU: how do you ensure that this CPU has control of the system when power is first applied?
Figure.3-11 illustrates an easy method of establishing system control upon initialization.The system reset signal
(NRST). which is generated at power-up. is applied to SC/MP #1. The FLAG 1 output from SC/MP #1 is then applied to
the NRST input of SC/MP #2. Since the FLAG1 line is connected to a bit in the CPU's Status register which is set to
zero onpower-up. SC/MP #2 will be held in a reset condition untii SC/MP #1 executes an instruction which sets that
bit (and thUS. the FLAG1 output line) high.
Of course. this method requires the FLAG1 output from SC/MP #1 to be dedicated to this initialization operation. If this
is a problem. you could use two separate initialization circuits with. for example. the RC time constant for the SC/MP
#2 circuitry being greater than that of the circuitry for SCiMP #1. This approach. however. does not provide the positive control of the first method we described.
3-19
Initialization
Circuit
-
7
NRST
SC/MP
#1
FLAG 1
~
21
~
NRST
SC/MP
#2
Figure 3-11. One Method of Initializing an SC/MP Multiprocessor System
Once the multiprocessor system has been initialized and is running, the bus-sharing logic that we've already described
will resolve contentions between the CPUs as far as access to System Busses is concerned. However, there might be
situations where we want to assure that one of the CPUs will be guaranteed immediate and extended access to
the System Busses. This can also be accomplished quite easily with SC/MP as illustrated in Figure 3-12.
SC/MP
#1
~
-
8
21
CONT
FLAG 1
SC/MP
#2
Figure 3-12. Forcing the Halt State in an SC/MP Multiprocessor System
3-20
In this illustration the FLAG 1 output of SC/MP #2 is inverted and applied to the CONT input of SC/MP #1. Now. if the
F1 bit in the Status register of SC/MP #2 is set to "1". SCiMP # 1 will be forced into the Halt state and is effectively
removed from the system until the F1 bit is reset under program control.
THE SC/MP RESET OPERATION
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An NRST low signal input to the SC/MP CPU initializes the microprocessor. While NRST is low. any in-process
operations are automatically aborted and the CPU's strobes and address and data lines are floated. NRST must be held
low for a minimum of two microcycles. After NRST goes high again. this is what happens:
1)
2)
3)
All of the programmable registers are cleared.
The first instruction is fetched from memory location 000116.
The Bus Request (BREO) for this first input/output ope~ation occurs within 6-1/2 microcycles after NRST goes high.
The NRST signal can be used at any time to reset the CPU, and must be used following power-up since SC/MP
may power up in a random condition. After power has first been applied to the CPU. you should allow approximately
100 milliseconds for the oscillator and internal clocks to stabilize before applying the NRST signal.
en
SC/MP SERIAL INPUT/OUTPUT OPERATIONS
a/I
The SC/MP CPU not only has two of its 40 pins designated primarily for serial input/output operations, it also
dedicates one instruction from its rather limited instruction set solely to serial I/O. Allocation of this amount of a
CPU's resources for this purpose would seem unwarranted with most microprocessors; however. keep in mind that
SCiMP is a very low-cost device and intended primarily for use in slow-speed applications. It is quite likely that SC/MP
will frequently be used to transfer data serially. so it is therefore not only reasonable but advantageous to provide
straightforward methods of performing these operations, Let us look now at how this is done with SC/MP.
<
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II:
o
IC
en
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<
@
In our description of SClMP's programmable registers. we described the Extension (E) register as an 8-bit register.
When the E register is used for serial I/O, it is actually a 9-bit register with connections to two of the device
pins as shown in the figure below.
SIN
Extension
Output
Register
Latch
~716151 . 131211Io~ sour
When the SC/MP SIO (Serial Input/Output) instruction is executed, the contents of the Extension register are
shifted right one bit positipn: the previous contents of bitO are'loaded into the output latch and output on the SOUT
pin. and the level (1 or 0) present at the SIN pin is loaded into bit 7 of the Extension register. The Extension register can
be loaded from. and its contents can be transferred to the Accumulator. A typical serial output operation would thus
consist of:
1)
2)
3)
Loading the Accumulator with the data byte that is to be transmitted.
Transferring the contents of the Accumulator into the Extension register.
Performing eight SIO'instructions to shift the contents of the Extension register into the output latch and out onto
the SOUT pin.
Of course. this sequence does not cover all the programming requirements for serial data transfers. For example. your
program must provide spme method of timing the bit transmission. This is easily accomplished with SC/MP by using
the Delay (DL Y) instruction. which can generate variable time delays ranging from 13 to 131.593 microcycles. For
asynchronous operations. one of the SC/MP Flags which are connected to device pins can be pulsed each time a new
bit is shifted out (or in) and one of the sense conditions inputs (SENSEA or SENSEB) can be tested to detect bit
received/ready.
.
.
3-21
THE SC/I\IIP INSTRUCTION SET
Table 3-4 lists the SC/MP instruction set.
Memory reference instructions are shown as having either full or limited addressing capability. Full addressing
capability is identified in the operand as follows:
It'
OISP
(X)
T'" , ' ,
If P""'"1. X "",d, '0"" .2 0,P3, ",d ;"d",d
addressing is specified
Must always be present. Specifies a program
relative displacement. '
--------If present. specifies auto-increment or autodecrement addressing.
Thus. the real options associated with full addressing capabHity are:
DISP
Direct. program relative' addressing
DISP(X)
Direct. indexed addressing
@DISP(X)ALJto-increment or auto-decrement addressing'
limited addressing capabilities do not include the auto-increment and auto-decrement feature. The operand field for
instructions with limited addressing capability is shown as follows:
'
rr
OISP
(X)
If pre""" X ,,,,,d,
'0' • I, .2 0' P3 ",d ;"d.,""
addressing is specified
Must always be present. Specifies a program .
relative displacement.
The serial I/O instruction inputs serial data via the high-order bit of the Extension register. and/or outputs serial data via
. the low-order bit of the Extension register.
"
The serial 110 instruction works as a on~-bit right shift of the Extension register contents. withbitO being s'hifted to the
SOUT pin and the SIN pin being shifted into bit 7. This has been illustrated along with the logic description.
It is worth noting that SC/MP has no Jump-to-Subroutine instruction: rather. the XPPC instruction is used to exchange
the contents of the Program Counter with the contents of a Pointer register. In very simple applications (and those are
the applications for which SC/MP is intended) this is a very effective scheme. Providing subroutines are not nested. a
subroutine's beginning address may be stored in a Pointer register. then execution of XPPC moves the subroutine's
starting address to the Program Counter. thereby executing the subroutine ~ but at the' same time. the Program
Counter contents are stored in the Pointer register. thus preserving the return address. At the conclusion of the
subroutine. execution of another XPPC instruction is all tha,t is needed to return from the subroutine. The only penalty
paid is that one Pointer register is out of service while the subroutine is being executed. If all Pointer registers are
needed by the subroutine. or if subroutines are nested. then the return address which is stored in the Pointer register
must be saved inmemory. In these more complicated applications. one of the Pointer registers will probably be used as
a Stack Pointer. 'and addresses will be saved on the Stack.
This type of subroutine access. while it may appear primitive to a minicomputer programmer. is very effective in simple
microcomputer applications.
The following symbols are used in Table 3-4.
AC
DATA
Accumulator
Carry status
An 8-bit binary data unit
DISP
E
The Extension register
C
An 8-bit signed binary displacement
3-22
EA
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a::
0
D-
a::
0
u
~
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I-
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U
0
CI)
CI)
<
~
w
za::
E
IE
O
PC
X
SIN
SOUT
SR
Z
@
X
0
CD
CI)
0
@DISP(X)
~
<
c
<
[ ]
@
[[ ]]
A
V
¥
Effective address. determined by the instruction. Options are:
DISP EA is [PC] + DISP
DISP(X) EA is [X] + DISP
@DISP(X) EA is [X] if DISP ~ O.
EA is [X] + DISP if DISP < 0;
in both cases [X]-[ X] + DISP after EA is calculated.
The ith bit of the Extension register
Interrupt Enable
Overflow status
Program Counter
One of the three Pointer registers
Serial Input pin
Serial Output pin
Status register
Zero status
Auto-increment flag
Bits y through z of a Pointer register. For example. P3 <7.0> represents the low-order byte of Pointer
register P3.
This designates the available addressing modes for the SC/MP. as described above. In all three of the addressing modes. if -128 is specified for DISP. the contents of the Extension register are used instead of
DISP.
Contents of location enclosed within brackets. If a register designation is enclosed within the brackets.
then the designated register's contents are specified. If a memory address is enclosed within the
brackets. then the contents of the addressed memory location are specified.
Implied memory addressing; the contents of the memory location designated by the contents of a
register.
Logical AND
Logical OR
Logical Exclusive-OR
Data is transferred in the direction of the arrow.
Data isexchanged between the two locations designated on either side of the arrow.
Under the heading of STATUSES in Table 3-4. an X indicates statuses which are modified in the course of the instruction's execution. If there is no X. it means that the status maintains the value it had before the instruction was executed.
.
3-23
Table 3-4. SC/MP Instruction Set Summary
STATUSES
TYPE
MNEMONIC
OPERAND(SI
OPERATION PERFORMED
BYTES
C
SIO
0
1
[E]-[E]
SOUT - [EO]
[E7l-SIN
Shift the Extension register rigHt one bit. Shift bit 0 of the Extension register to the output Pin
SOUTo Shift the data at input pin SIN into bit 7 of the Extension register.
[AC]-[EA]
load Accumulator from addressed memory location.
[EA]-[AC]
Store Accumulator contents in addressed memory location.
g
u..
w
lD
@
DISP(XI
2
ST
@
DISP(XI
2
ADD
@ DISP(XI
2
X
zw
DAD
@ DISP(XI
2
X
~~
CAD
@ DISP(XI
2
X
AND
@ DISP(XI
2
Add decimal to Accumulator the addressed memory iocation's contents with Carry,
[AC]-[AC]+ [EA]+ [C]
Add complement of addressed memory location's contents with Carry to AccumulatOr.
[AC]-[AC] A [EA]
OR
@ DISP(XI
2
AND Accumulator with addressed memory location's contents.
[AC]-[AC]V [EA]
XOR
@ DISP(XI
2
OR Accumulator with addressed memory location's contents.
[AC]-[AC]¥ [EA]
IlD
@ DISP(XI
2
DLD
@ DISP(XI
2
~~Q
«a:-
~ ~"~
W «
Q.
~
w
X
u
a: w
~ffi
>Q.
a:O
0>
~a:
wO
~~
"> w
a:~
«0
Oz
~«
u
w
en
~
0
w
X
[AC]-[AC]+ [EA]+ [C]
Add binary to AcciJmulator the addressed memory location's contents with carry.
[AC]-[AC] + [EA] + [C]
Exclusive-OR Accumulator with addressed memory location's contents.
[EA]-[EA]+l; [AC]-[EA]
Increment addressed memory iocation's contents, then load into Accumulator.
[EA]-[EA]-l; [AC]-[EA]
Decrement addressed memory location's contents, then load into Accumulator,
[AC]-DATA
Load immediata into Accumulator,
LDI
DATA
2
ADI
DATA
2
X
DAI
DATA
2
X
CAl
DATA
2
X
ANI
DATA
2
:E
:!
~"
a:
w
Q.
0
w
I-
«
0w
~
~
X
X
[AC]-[AC]+DATA+ [C]
Add binary immediete, Add Carry to result,
[AC]-[AC] + DATA + [C]
Decimal add immediate, Add Carry to result,
[AC]-[AC] + DATA [C]'
Add the contents of the Accumulator to the complement of the immediate data value, Add Car-
+
ry to result.
[AC]-[AC] A DATA
AND immediate.
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 3-4. SC/MP Instruction Set Summary (Continued)
STATUSES
TYPE
MN1MONIC
OPERAND'S)
BYTES
OPERATION PERFORMED
C
III
0
--
~
~
52
ORI
DATA
2
,~g
XRI
DATA
2
JMP
DISP(X)
2
I!!i
;y
[AC]-[AC] V DATA
OR immediate.
[AC]-[AC]¥DATA
Exclusive-OR immediate.
;I
D.
~
.,::l
[PC]-EA
Unco'nditional jump to effective address •
JP
DISP(X)
2
JZ
DISP(X)
2
JNZ
DISP(X)
2
If [AC] ~O; [PC]-EA
If the Accumulator contents are greater than O. lump to effective address.
If [AC] =0; [PC]-EA
If the Accumulator contents equal O. jl1rnp to effective address.
If [AC] =0; [PC]-EA
If the' Accumulator contents are not O. jump to effective address.
ZZ
02
D.t:
:EO
::lZ
w
"8
N
OJ
III
>
:E
0
LDE
[AC)-[E)
1
XPAL
X
1
XI>AH
X
1
XPPC
X
1
Load the contents of the Extension register into the Accumulator.
[AC]-[X<7.0>]
Exchange the contents of the Accumulator with the low order byte of the specified Pointer
register.
[AC)-[X<15.8>]
Exchange the contents of the Accumulator with the high order byte of the specified Pointer
register.
[PC)-[X]
1
Exchange the contents of the Program Counter with those of the specified Pointer register.
[AC)-[E)
a:
III
~
(/)
C;
a:
III
ci:
III
~
(/)
5
III
a:
XAE
Exchange the contents of the Accumulator with those of the Extension register.
W
~
cs:
ADE
1
X
DAE
1
X
CAE
1
X
X
a:
III
D.
0
a:
III
~
(/)
5
III
a:
~
I/)
5
a:
this result.
[AC)-[AC) + [E) + [C)
Add binary the contents of the Accumulator and the complement of the Extension register con-
ci:
III
III
X
[AC)-[AC]+ [E)+ [C)
Add binary the contents of the Accumulator and the contents 0; the Extension register. Add Ceirry to this result.
[AC)-[AC1+ [E1+ [C)
Add decimal the contents of the Extension register to those of the Accumulator. Add Carry to
ANE
1
tents. Add Carry to this result.
[AC)-[AC] 1\ [E)
AND the contents of the Accumulator with those of the Extension register..
Table 3~4. SC/MP Instruction .Set Summary (Continued)
STATUSES
TYPE
MNEMONIC
OPERANDiS)
BYTES
OPERATION PERFORMED
C
a
o
~I~:~~
(/)'(/)I~~
C;'Si~ !z
~a:IO 0
0
ORE
1
[AC]-[AC]V[E]
XRE
1
. OR the contents of the Accumulator with those of the Extension register.
[AC]-[AC1¥ [E)
Exclusive-OR the contents of the Accumulator with those of the Extension register.
g
O-·~·V
1
SR
~O~
Shift Accumulator contents right one bit. The high
iost.
w
SRl
~7
1
f-
w
110
W
f-
low order bit is
O~
Shift Accumulator contents right ~~e. bit. The Carry bit is shifted into the high order bit of the
Accumulator. The low order bit is lost.
,
~~=:
.
I PULL,U'
. i
l
0
' Vss
ENIN
NHDLD
IPU~~~
I
Vss
'
'
BRE'~l
Vss
r-::::-1
'INCLUDES JIG CAPACITANCE.
i
-1H~:g~T
-1'
..
~~~:2
.
Simulated Current Load
I
I
-1
VGG
....
a:
:::>
I
~...
-1 , - -
z
..
INPUT PROTECTION
~
'to
0.8
;
0.6
...
0.4
~~
0.2
~
2_____
·----,."",,-,.f.......!r--
IL ________________
-1
m·
NRDS
I
a:
Yss
xz~
2
VG~SS
. ~
Vss
I
,,1.
NWDS
-1
8
Vss
V
u
I
~
~
... ..
.. ..
C>
Z
Vss
C>
Z
~
60 70 BO
-20
100
AMBIENT TEMPERATURE I'C)
SC/MP Driver and Receiver Equivalent Circuits
TYPICAL PLOT OF NORMALIZED IGG lAND ISS)
VERSUS AMBIENT TEMPERATURE
DC POWER' IGG • vGG+ ISS· VSS
B~' BREa, ENIN, and ENOUT Timing
22
22
22
NADS
NRDS!NWDS'~~
Note 1: ENOUT goes high to indicate that SC/MP was granted access to bus (ENIN high) but is not using bus.
Note 2: ENOUT goes low in response to low ENIN input.
Note 3: SC/MP generates bus request; bus access not granted because ENIN low.
Note 4: ENIN goes high. Bus access now gran~ed and input/output cycie actually initiated. If ENIN is set low while SC/MP
has access to the bus, the address and data ports will go to the high-impedance (TRI-STATE@) state, but BREQwili remain
high. When ENIN is subsequently set high, the input/output cycle will begin again.
Note 5: I/O cycle completed. ENOUT goes high to indicate th2
INTE
DBIN
WR
SYNC
(VC C) + 5V
26
25
24
23
22
21
20
PIN NAME
All
A14
A13
A12
A15
A9
A8
A7
A6
A5
.4.4
A3
+ 12V (VDD )
A2
Al
AO
WAIT
READY
4>1
HLDA
DESCRIPTION
-AO - A15
-DO -
TYPE
Address Lines
07
Output. Tristate
Data Bus Lines
Bidirectional. Tristate
Machine Cycle Synchronizer
Output
-DBI~
Data Input Strobe
Output
;READY
"-WAIT
Data Input Stable
CPU In Wait State
SYNC
_
Input
-\iVA
Data Output Strobe
Output
Output
-HOLD
Enter Hold State
Input
-HLDA
Hold Acknowledge
Output
~INT
Interrupt Request
Interrupt Enable
Input
Output
4>1. 4>2
Reset CPU
Clock Signals
Input
VSS·VDD'vCC·VBB
Power and Ground
-INTE
-RESET
Inpu~
-These signals connect to the System Bus.
Figure 4-2. 8080A CPU Signals and Pin Assignments
CLOCK SIGNALS
Two clocks.' <1>1 and <1>2. provide the CPU with· its til"!ling ..
Figure 4-3 illustrates the way in which clock signals <1>1 and <1>2 are used to generate a machine cycle consisting
of fiye 'clock periods. A SYNC pulse identifies the first clock period of every machine cycle.
4>1
4>
JJl
t9
211
I
SYNC:
I
.
~
n
n~_. .n~___:
'1 ~ I ~r"'\-.-~: n
I:
i" '. . --"1_..1 . . . . . . ._.~"'.:',
n
Ii . . -~.I-----~. . . ----....---.-....,
I
_
.•.
'I
..
J
II
.
SYNC. pulse Identifies clock period T 1
Figure4-3. A Machine C'ycle Consisting of Five Clock Periods:'
4-8
I
A 9-segment clock is specified for the 8080A.where the <1>1 and <1>2 signals are generated out of 9 segments as
follows:
2
I
cw
1 pulse at the start of T2 to read status off the Data 8us. Timing is illustrated in Figure 4-4.
8080A
INSTRUCTION
STATUS
If you are using an 8228 System Controller, it will decode status output on the Data Bus
during T2. By combining this status information with 'the three control signals: WR. DBIN and HLDA. the 8228 System
Controller is able to generate a set of bus control signals which will interface' industry standard memory devices and external logic.
.
If you are not using an 8228 System Controller, then you must provide external logic that decodes the Data Bus
during <1>1 of T2. Your external logic must generate control signals which will be active during' subsequent clock
periods, at which time the Data Bus no longer holds status information. j;.
<1>1
<1>2
SYNC
. Status on
Data Bus
Strobe to read status off Data Bus
when <1>1 and SYNC are both high
Figure 4-4. Status Output During T2 of Every
Machine Cycle
4-10
Table 4-2 defines the statuses which may be output during clock' period T2. Table 4-3 defines the way in which
statuses should be interpreted to identify the various possible types of, machine cycles.
Table 4-2. Statuses Output Via the Data Lines Du~ing the Second
Clock Cycle of an 8080A Machine Cycle
DATA BUS
BIT
Q
III
SYMBOLS
HLTA
D3
Acknowledge signal for Halt instruction
a:
INTA*
DO
Acknowledge signal for INTERRUPT request. Signal should be used to gate a
Restart instruction onto the Data Bus when DBIN is active.
INP*
D6
Indicates that the Address Bus contains the address of an input device and
the input device shou Id be placed on the Data Bus when DBIN is active.
g
~
OUT
D4
en
en
Indicates that the Address Bus contains the address of an output device and
the Data Bus will contain the output data when WRis active.
oCt
MEMR*
D7
Designates that the Data Bus will be used for memory read data.
ail
M1
D5
Provides a signal to indicate that the CPU is in the fetch cycle for the first
byte of an instruction.
STACK
D2
Indicates that the Address Bus holds the pushdown stack address from the
, Stack Pointer.
WO
D1
Indicates that the operation in the current machine cycle will be a WRITE
memory or OUTPUT function (WO = 0). Otherwise a READ memory. INPUT
operation. or interrupt or Halt acknowledge will be executed.
~
a:
o
D.
o
CJ
~
en
III
III
Z
a:
oaI
en
o
~
oCt
Q
oCt
@
DEFINITION
*These three'status bits can be used to control the flow of data onto the 8080A Data Bus.
Table 4-3. Statuses Output on the Data Bus for
Various Types of Machine Cycle
TYPE OF MACHINE CYCLE
III
"....e
III
z
0
j:
:I:
~
~
<
....
iii
III
;:)
ID
<
....
<
e
(0)
a:
0
II.
~
III
;:)
....
....<
III
~
C.)
....
z
0
j:
C.)
;:)
a:
....
III
~
0
e
<
III
a:
>
a:
0
~
III
~
z
III
....
a:
~
>
a:
0
~
III
III
e
<
III
a:.
~
C.)
~
III
....
a:
~
~
C.)
<.
....
e
,<
III
a:
....
;:)
0.
~
III
III
~
....
a:
~
....
;:)
0.
....
;:)
III
III
"e
0. ....
"~e
a:o
a:z
.... z
.... 111
~
;:)~
III~
0
....~
0
~<
""C.)
2 triggers the SYNC high pulse'. identifying period T 1,
WAIT is low. since the CPU is not in the Wait state,
WR remains high since this is an instruction fetch cycle; data is not being writte,n to memory,
I . , . '
•
The leading edge of <1>2 is used to set selected Data Bus lines high. providing external logic with status
i.nformation as follows:
RlfWO (D1),
. The CPU is expecting data input.
M 1 (D5)
,This is an instruction fetch period.'
MEMR (D7) . Data input is expected from memory.
The leading ,edge 0(<1>2 is used to set the required
Period T2
memo~
address on the address lines AD to A 15.
External logic uses the <1>1 pulse of ti'me 'period T2 to read status off the Data Bus, The read status strobe
'
may be created as follows:
SY:~
'~D"--------READSTATUSSTROBE
________
Remember. if you are using an 8228 Syste'm Controller.' it reads and decodes status for you.
ImmediatelY after status has been output on the Data Bus. the Data Bus is free to receive the instruction
object code. The addr'ess for the instructio'n object code'will be on'the Address Bus; this address appears
on the Address Bus during T 1. beginning with the rising edge of <1>2, The fact that status has been output
and the Data Bus is free to receive the instruction,object code is indicated by DBIN being pulsed high.
The DBIN high pulse begins with the rising edge of <1>2 in T2 and lasts exactly one clock period.
Period T3
While DBIN is high. external logic must place the addressed instruction code on the Data Bus. The CPU
will store this data iii the 'Instruction register -whence the Control Unit interprets it as an instruction
code.
The Data Bus is floated at <1>2 during T3. This means that the Data Bus has been disconnected from the
CPU a~d can be used in any way by .Iogic external t~ the CPU. ,
.
Period T4
The Address Bus is floated at <1>2 during T4,
The 8080A uses', 2 and 3 byte instructions. Each byte of a multibyte instruction requires its own instruction
fetch. Exact timing for multibyte instructions is given later in this chapter. after the 8D8DA instruction set has been de..
scribed.
A MEMORY READ ,OR WRITE OPERATION
SO far as external logic is concerned. there is no difference between "read from memory" timing and instruction fetch
timing - ex~ept that the M 1 status (D5 on the Data Bus) is high during an instructio,", fetch only. Figure 4-5 therefore
applies to a memory read operation also.
Since a memory read operation is executed during time periods T" T2 andT3 of a,machine cycle, the presence
of a memory read operation in an instruction's execution sequenc~ will add one machine cycle to instruction execution time.
'
"
Figure 4-6 shows timing and signal sequences for a memory write opera~ion. The signal sequences are identical
to the instruction fetch sequence with the exception that DBIN remains low during T2 and T3, and different
status signals are output on the Data Bus during T,.
'
SEPARATE STACK MEMORY MODULES
One 8080A CPU can access two memory modules with overlapping memory, addresses: a stack memory
module and a nonstack memory module. Overlapping memory addresses can be used by the two memory modules.
since Stack status (D2 high at <1>1 in T2) can be used to select the stack memory. while lack of Sta~k status (D2 low at
<1>1 in T2) can be used to select nonstack memory. External logic must decode the' address as referencing stack or nonstack memory.
'
,
4-12
Note that the 8228 System Controller does not generate a STACK control signal. Nevertheless. if you wish. you may implement separate stack and nonstack memory. with overlapping addresses; this requires your own status decode logic
to isolate the Stack status. Such logic is quite simple. and may be illustrated as follo~s:
SY:: _ _ _ _ _.
w
~
a:
oQ.
a:
o
u
~
iii
.-----
D--[l>~
Q
-
Stack memory select
Nonstack memory select
The only disadvantage associated with having a separate stack memory is that nonstack instructions cannot reference
the stack memory.
w
~
g
T1
U)
U)
ct
<1>1
~
w
Z
a:
oCD
U)
o
~
ct
Q
ct
@
SYNC
READY.f\
I
I
I
WAITjr1l~I+-________-+__~______-p______~__~~____~~~__________~
DBIN
Di
(instruction I
AO
to A15
I .
I
I
I
External Logic
Read Status
Di - Signals
I·
I
I
I.
I
I
I
I
I
I
.1
I
I
1.. .....1------I Instruction Fetch -----~.~
I
-The NEC 8080A maintains the address on the Address Bus during T4 and T 5'
Figure 4-5. 8080A Instruction Fetch 'sequence
THE WAIT STATE
A Wait state may occur between clock periods T2 and T3. The Wait state frees external
logic or memory from having to operate at CPU speed. Wait state timing is illustrated in Figure
4-7 and Figure 4-8.
8080A
SLOW
MEMORIES
If READY is low during <1>2 of T2. the 8080A CPU will enter the Wait state following T2. The Wait
state consists of any number of clock periods during which the CPU performs no operations and maintains the levels of
all output signals. The Wait state ends when READY is input high. The CPU samples READY during every <1>2 pulse
within the Wait state; the Wait state will therefore end with the <1>1 pu Ise which follows a <1>2 p~ Ise during which
READY is sensed high.
4-13
Memory interface logic in any 8080A microcomputer system must be designed to anticipate that every memory
access either will, or will not require a Wait state.
If memory is as fast as the 8080A CPU, then READY will normally be held high, in anticipation of no Wait state. In
Figures 4-7 and 4-8 a broken line is used to represent this "READY normally high" case. Memory interface logic will
pull READY low in order to insert one or more Wait machine cycles only in special circumstances: memory interface
logic has until 1
_ _ _ _ _ _....1
c
w
~
a:
oa.
a:
o(J
!:
en
w
READY
Consider the sequence of signal transitions in the logic we have illustrated above. At each <1>1 clock pulse. tranSitions
will occur as follows:
l-
e:(
g
4>1
(I)
(I)
e:(
~
w
Z
a:
o
ca
01
--0-_.1
(I)
o
~
01-' 02
e:(
c
e:(
@
02
READY
It requires 01 and 02 to be high simultaneously for READY to be low; and that condition exists for a single clock pulse.
Observe that you can use READY to trigger a one-shot in order to create a low READY input of any duration.
T,
T3
T2
T4
T5
4>1
4>2
SYNC
READY
I
WAIT.f\. I
I
WRVI
I
I
I Status
. -••• "' ••• Represents alternate signal form for READY as described in text accompanying this figure.
Figure 4-7. The 8080A CPU Operating With Fast Memory and No Wait State
4-15
T2
WAIT
cfJl
cfJ2
SYNC,
READY
I
WAITJ\
I
1 - ,- - _. . . . ._ - . . . ,
(Write Only)
WRVI
I
- _ ••• "'... Represents alternate signal form for READY as described in text accompanying this figure.
READY is false at cfJ2 in T 2, so next cfJl pulse initiates a Wait state, with WAIT set high by the leading
edge of the cfJl pulse. When READY is high at a 1 ...I
mac~".
La"
cycle
of an instruction's
execution
I
..
HOLD state clock periods'
~
I"1 in T3. If a HOLD is requested during a write or output operation, then HLDA is set
high by the leading edge of <1>1 in the cycle following T3.
Note that even though HOLD is acknowledged and the Hold state is initiated in T3 during a read memory or input data
machine cycle, logic must still hold data steady on the Data Bus until the leading edge of <1>2 in T3. This is because
operations internal to the CPU will be executed normally during a HOLD. Operations internal to the CPU will only cease
if the Hold state lasts for more cycles than would normally ~e present before the onset of the next T 1 cycle.
al
CI)
o
:iE'
~
c
~
@
HOLD low will cause the end of the Hold state. HOLD low must coincide with the leading edge of <1>1 or <1>2, and will
terminate the Hold state at the <1>1 pulse of the next machine cycle's T 1 clock period. The 8080A CPU will signal the
end of the Hold state with HLDA false.
During the Hold state, the Data Bus and the Address Bus are floated. Floating begins at <1>2 in T3 for a read operation
and at <1>2 in the clock period following T3 otherwise.
Figures 4-9 and 4-10 illustrate some variations on the Hold state.
The NEC 8080A and the Intel 8080A differ when a Hold is 'requested during a DAD instruction's execution. The NEC 80BOA initiates the Hold as though a read operation was occurring,
while the Intel 8080A initiates the Hold operation as though a write operation was occurring.
NEC 8080A
HOLD
DIFFERENCES
M.chine Cycle N + 1
SYNC
HOLD
HLDA
H---t---I-f--+-+---+---+--
HOLD STATE
--+-----+----+----4!'-----j
Wi H--~~~~~-~~--~---~---+_--+_---+_---~---~--~
00 to 07
\V--+---+---+-'--t floating
f---'-----l---+---+- flo.ting·I
·optional, depending on instruction being executed
Figure 4-9A. Floating of Data and Address Busses at <1>2 in T3, for READ Operation Being Completed Prior
to Onset of Hold State
4-17
Figure 4-9B. Flo'ating of Data and Address Busses at <1>2 in T4. for a WRITE. or Any
Non-READ Operation (RI/WO=False)
Machine Cycle N + 1
Machine Cycle N
SYNC
HOLD
HLDA rt------r----t--~.----+~------~-----HOLDSTATE--~------~------~L~----_1
WR ~------r----r--~---+~------~------~------~~----~~------~----~
"""---+-------+------_+_~ floating
I
Figure 4-1 OA. Floating of Data and Address Busses for READ Operation in"a Three Clock
Period Machine Cycle
Machine Cycle N + 1
Machine Cycle N
SYNC
HOLD 1-+------1--+-----1-+--'
HLDA hr------r-lr----ri----~I.-+_~~~----~--HOLDSTATE ____~------~~L-----_1
WR Ht-------I--+----.J
DO to 01
Ao
to A,s
H:J'---.:......,-....
1--A----I------I-------1--_
Figure 4-1 OB. Floating of Data and Address Busses at <1>2 in T 1. for WRITE or Any Non-READ Operation Being
Completed Prior to Onset of Hold State
4-18
THE HALT STATE AND INSTRUCTION
The Halt state is similar to the Wait state, except that it is initiated by a Halt instruction.
Q
w
~
a::
o
Do
The Halt state is not initiated by READY low. although READY low is a necessary requirement for the onset of the Halt
state. This means that READY high cannot be used to terminate a Halt state. Instead. an interrupt request (lNT high)
must be used to terminate the Halt state.
Note that if interrupts have been inhibited, the interrupt request (lNT high) will never be acknowledged, and
the only way , to get out of a Halt state is to power down, then power up the CPU.
l
CJ
An anomaly of the Halt state is that the Data and Address Busses may be floated by entering th~ Hold state after entering the Halt state; that is. you can move into. and out of the Hold state while in the Halt state.
en
w
If the Hold state is entered after the Halt state. then the Hold state must be exited py setting HOLD low before exiting
the Halt state.
g
During a HALT. a hold request signaled by HOLD will not be acknowledged if an interrupt has been requested (lNT
high) but not acknowledged (lNTE high); i.e .. the CPU will not enter the Hold state in the time be~ween an interrupt
being requested and acknowledged. Once the interrupt has been acknowledged (lNTE 10wL the CPU may enter the
Hold state.
'
a::
o
,~
~
(I)
(I)
1 pu Ise. Since the Program Counter contains 0000. the first instruction executed following RESET will be the instruction stored in memory
"
'
,
location 0000) 6.
Interrupts remain disabled when program execution resumes.
When you power up any 8080A system you must simultaneously reset it. Powering up does not reset or change
anything within the 8080A. If you power u'p without resetting. then registers. including the Program Counter. will contain undefined data; thu~ program execution will immediately and erroneously begin at some random location of
memory.
Here are two possible reset on power up logic implementations:
First a simple logic sequence:
+ 5V
RESIN
8224
~
I
RESET
Next a more s:omplex. and more reliable one:
+5V
1.0
1.0
MH
MH
B
4
6
if
Vee
T~
1/674LS04
2
TR
555
. RESIN
OUT
8224
7
~- -
RESET
lo.,uF
lo. ,uf
--
--
--
Machine Cycle N t 1
N
T,
T2
11
\
READyJ\
'\I
)
/
V
DBIN
n
.(L
~
/\\
\
T,
T5
n
n
h
~
"": N + 2
T4
T3
U~
h
Ln 1~
SYNC
GND
ev
I +O.47UF
h
DIS
WAITJ\
W'RJ\
I
INT
\
l\,)
INTE
1--~.
,
\.,
D; Status
\~
I
DS~~~lt~
I
I
.J
I
floating
I
External Logic
Read Status
Do - Status
Inte;rupt Initiation
Figure 4~
11,
Interrupt Initiation §e'Quence
4-20
I
EXTERNAL INTERRUPTS
External logic may reque~tan i,nterrupt at any time by setting thelNT input hi~h. An interrupt request will only
be acknowledged if interrupts have been enabled. Normally the EI (Enable Interrupts) and 01 (Disable Interrupts) instructions are ~xecuted to enable and disable interrupts; however. interrupts are automatically disabled by the CPU
during the RESET condition. and following an interrupt ackhowledge.
cw
tiII:
Q
a..
II:
o
U
~
enw
~
g
en
en
The 8080A CPU outputs INTE high when interrupts have been enabled. and low when interrupts are dis~bled. If interrupts are enabled. then the 8080ACPU will acknowledge an interrupt request during the next T1 clock period. on the
rising edge of 2 in clock period T2:this is one clock period later than illustrated in Figure 4-11. Note that this difference in NEC 8080Aresponse applies only to the
interrupt acknowledge process occurring within a Halt state.
NEC 8080A
EXTERNAL
INTERRUPT
DIFFERENCES
WAIT AND HOLD CONDITIONS FOLLOWING
AN INTERRUPT
An interrupt cannot be a'cknowledged during a WAIT or HOLD condition. However. either of these conditions may occur following the interrupt acknowledge. For example. if there is insufficient time between <1>1 in T2 and <1>2 in T2 for
external logic to fetch the required RST or CALL instruction. more time may be acquired by using the READY signal to
generate a Wait state. as with any instruction's execution.
THE 8080A INSTRUCTION SET
Table 4-4 summarizes the 8080A instruction set; there is.a significant departure in instruction set philosophy
from the hypothetical microcomputer described in Volume I.
The 8080A is most efficiently programmed by making extensive use of the Stack and of subroutines. By providing a
variety of Jump-to-Subroutine on Condition. and Return-from-Subroutine on Condition instructions. the S080A allows
the execution of subroutines to become an integral part of programmed logic sequences.
a
Observe that the 8080A has number of 16-bit instructions: that is. instructions that operate on the 16~bit contents of
the BC. DE or HL registers. These include 16-bit increment and decrement. 16-bit add. and 16-bit data moves.
The 16-bit instruction XTHL' is particularly useful. since by allowing the top two Stack bytes to be exchanged with the
HL registers. an easy method is provided for switching addresses.
The DAA instruction modifies the A register contents to generate a binary coded decimal equivalent of t~e original binary value. If carries out of bit 3 or bit 7 result. these are reported in the Auxiliary Carry and Carry statuses. respectively.
See Volume I for a discussion of the decimal adjust operation.
There are a few differences be.tween NEC 8080Aand Intel80BOAinstruction execution.
For binary subtraction and BCD arithmetic the NEC 8080A performs operations in what is
theoretically the "correct" fashion - which diffe.rs. from the actual implementation of the Intel
8080A. Specifically. the NEC S080A has a SubtraCt status (SUB) which is set after any addition
is pei'formep.:Only the NEC 8080A has a Subtract st~tus.'
,
'
NEe 8080A
INSTRUCTION
SET ~
DIFFERENCES
The NEC 8080A correctly sets and resets the Auxiliary Carry status (AC) during subtract operations. identifying any
borrow by the low order digit as follows:
(f
,7
6
4
3
Borrow here sets AC
2
1
0...
X X X X X X X X
-.Y Y Y Y Y Y Y Y
Z, Z
Z
Z
Z
Z
Z
4-24
Z
Bit No.
X. Y and Z represent any binary digits.
Decimal subtraction for the Intel 8080A and NEC 8080A may be illustrated as follows. assuming the contents of
Register B are to be subtracted from the contents of Register C:
INTEL 8080A
MVI
A.99H
SUB
C
ADD
B
DAA
c
w
~
a:
o
D.
a:
o
u
~
en
w
NEC 8080A
MOV
A.B
SUB
C
DAA
In the instruction sequence illustrated above for the Inte18080A. you cannot use the Subtract instruction directly since
it works for binary arithmetic only. You must create the nine's complement of the subtrahend by subtracting it from 99.
Then you add the minuend to the nine's complement of the subtrahend. Finally you decimal adjust the result.
l-
In the case of the NEC 8080A you may use the Subtract instruction for either binary or BCD data.
U
For a complete discussion of decimal subtraction using the Intel 8080A. see 8080 Programming for Logic Design.
Chapter 7.
e(
oCI)
CI)
e(
o/S
w
Z
a:
o
III
The Carry and Auxiliary Carry statuses are also treated differently by the NEC and Intel 8080A. When Boolean
instructions are executed by the Intel 8080A, the Carry status IC) is always reset; the Auxiliary Carry status
lAC) is sometimes reset. The NEC 8080A leaves the Carry and Auxiliary Carry statuses alone when executing
Boolean instructions.
CI)
o
~
e(
o
e(
@
When the AMD 9080A executes Boolean instructions it always clears both the Carry and Auxiliary Carry
statuses.
THE BENCHMARK PROGRAM
Our ben~hmark program is coded for the 8080A as follows:
LOOP
LHLD
LXI
LDA
MOV
LDAX
INX
MOV
INX
DCR
JNZ
SHLD
TABLE
D.IOBUF
10CNT
B.A
D
D
M.A
H
B
LOOP
TABLE
;LOAD ADDRESS OF FIRST FREE TABLE BYTE IN HL
;LOAD STARTING ADDRESS OF 10BU'F IN DE
;LOAD I/O BUFFER LENGTH
;SAVE IN B
;LOAD NEXT I/O BYTE
;INCREMENT BUFFER ADDRESS
;STORE IN TABLE
;INCREMENT TABLE ADDRESS
;DECREMENT BYTE COUNT
;RETURN FOR MORE BYTES
;AT END. RESTORE ADDRESS OF FIRST FREE TABLE BYTE
The 8080A makes very few assumptions regarding the benchmark program.
The address of the first free byte in the data table is assumed to be stored in the first two bytes of the data table - addressed by the label TABLE. The immediate addressing instruction LHLD loads the contents of the first two bytes of the
data table into the Hand L registers. At the end of the program. the incremented table address is restored with the
direct addressing instruction SHLD.
Since the I/O buffer starting address does not change. an Immediate instruction is used to load this address into the DE
registers.
Since the number of occupied bytes in the 110 buffer may change. a direct addressing instruction. LDA. is used to load
this buffer length into the Accumulator. It is then moved to the B register. since the Accumulator is used to transfer
data within the program loop.
The 8080A program makes no assumptions regarding the location of either the I/O buffer. or the data table. but it does
assume that the table is not more than 256 bytes long.
These are the abbreviations used in Table 4-4:
A
The Accumulator
B
C
The B register}
The C register
These are sometimes treated as a register pair
D
The D register}
The E register
These are sometimes treated as a register pair
E
4-25
H
L
The H register}
The L register
This register pair provides the implied memory address
C
Carry status. In Table 4-4 C refers to Carry status. not to the C register.
AC
Auxiliary Carry status
Z
S
P
Zero status
SUB
Sign status
Parity status
Subtract status (present in the NEC 8080A only)
The Instruction register
12
13
Third object code byte
Second object code byte
PC
The Program Counter
SP
The Stack Pointer
PSW
The Program Status Word. which has bits assigned to status flags as follows:
7 6 5 4 3 2 1 0 ...._---- Bit
No.
IsIz ~x 1)(1 XI pix 1c I
T+~-04tt-~!. . .----
Unassigned
.....- - - - - - - - - S U B (NEe 80BOA only)
DATA
8-bit immediate data
DATA16
16-bit immediate data
DEV
An I/O device
REG
Register A. B. C. D. E. H or L
s
Source register
d
Destination register
M
Memory. address implied by HL
LABEL
A 16-bit address. specifying an instruction label
RP
A register pair: B for BC. D for DE. H for HL. SP for Stack Pointer
PORT
An I/O port. identified by a number between 0 and FF16
ADDR
[ ]
A 16-bit address. specifying a data memory byte
[[ ]]
n
Contents of location identified within brackets
Memory byte addressed by location identified within brackets
Complement of the contents of
Move data in direction of arrow
Exchange contents of locations on either side of arrow
+
Add
Subtract
A
AND
V
OR
V-
XOR
The letter C is used to identify Carry status. Although C also identifies one of the 8080A
registers. registers are always referenced generically in Table 4-4.
4-26
8080A
CARRY
STATUS
NOMENCLATURE
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 4-4. A Summary of 8080A/9080A Microcomputer Instruction Set
STATUSES
TYPE
MNEMONIC
OPERANO(S)
BYTES
OPERATION PERFqRMED
C
AC
Z
S
P
SUB'
IN
DEY
2
[A]-[DEV]
OUT
DEV
2
Input to A from device DEV (DEV
[DEV]-[A]
g
= 0 to 255)
Output from A to device DEV (DEV
= 0 to 255)
LDAX
RP
1
[A]-[[RP))
STAX
RP
1
load A using address implied by BC (RP
[[RP))-[A]
MOV
REG,M
1
Store A using implied addressing as for LDAX
[REG]-[[ H,Ll]
MOV
M,REG
1
lDA
ADDR
3
STA
ADDR
3
LHlD
ADDR
3
SHlD
ADDR
3
ADD
M
1
X
X
?C
X
X
0
[A]-[A] + [[H,l]]
ADC
M
1
X.
X
X
X
X
0
Add tp A
[A]-[A] + UH,L)] + [C)
SUB
M
1
X
X
X
X
X
1
Add with Carry to A
[A]-lA] - [[H,Ll]
u.w
SBB
M
1
X
X
X
X
X
1
Subtract from A
[A]-[A] - [[H,Li] - [C]
a:c(
>a:
a: w
00..
ANA
M
1
0"
?w·
X
X
X
XRA
M
1
0"
Ot""
X
X
X
ORA
M
1
0"
Ot""
X
X
X
CMP
M
1
X
X
X
X
X
1
O~ with A
[A] - [[ H,Ll1. Discard result but set flags.
INR
M
1
X"
X
X
X
0
Compare with A
[[H,Ll]-[[H,Lll+ 1
DCR
M
1
X··
X
X
X
1
Increment memory
[[H,L]]-[[H,l]]-l
w
u
2
w
>a:
a::f
c(w
~a:
->
a: a:
0..
0
load any register using address implied by Hl
[[ H,Ll]-[ REG]
Store any register using address implied by Hl
[A]-[ADDRl. i.e., [A]-[[13, 12))
~
w
~
= B) or DE (Rp = D)
load A, use direct addressing
[ADDR]-[Al. i.e., [[13, 12))-[A]
Store A. use direct addressing
[l]-[ADDRl. [H]-[ADDR+ 11. i.e., [Li-[[13,12]l. [H]-[[I3, 12]+ 1]
load Hand l registers, use direct addressing
[ADDR]-[Ll, [ADDR+ ll-[H] i.e., [[13,12))-[Ll. [[13,12]+ l]-[H]
Store Hand l registers, ·use direct addressing
-
w
u
2
w
a:
w_
w~
~o
w>
~~
>~
a:w
c(~
Subtract from A with borrow
[A]-[A] I\. [H,l))
AND with A
[A]-[A]¥ [[H,L))
Exclusive-OR with A
[A]-[A] V [[H,Ll]
02
0
u
w
II)
Decrement merr'ory
--
Table 4-4. 'A
S~m~ary
of'SOSOA/90S0A Microcomputer Instruction Set
(C~~tinued)
,
STATUSES
TYPE
MNEMONIC
OPERAND(S)
OPE~ATION
BYTES
C
LXI
RP,DATAI6
3
MVI
M,DATA
2
MVI
REG,DATA
2
JMP
ADDR
3
AC
Z
is
w
~,
~
,.
Q.
~
,:l
I
PCHL
:..,
CALL
ADDR
3
CC
ADDR
3
CNC
ADDR
3
CZ
ADDR
3
Z
CNZ
ADDR
3
:l"";'
t:;~
CP
ADDR
3
Zen
MOV
ds
AC
Z
S
P
SUB"
[REG]-[REG]
Move any register (5) to any register (d)
[D]--[H1. [E]--[LJ
Exchange DE with HL
[SP]-[HLJ
Transfer HL to SP
1
0
~
"a:
6
XCHG
1
SPHL
1
W
W
a:
ADD
REG
1
X
X
X
X
X
0
ADC
REG
1
X
X
X
X
X
0
SUB
REG
1
X
X
X
X
X
1
tn
SBB
REG
1
X
X
X
X
X
1
~~
ANA
REG
1
0"
xt
X
X
X
tn o
XRA
REG
1
0··
at""
X
X
X
ORA
REG
1
0··
at""
X
X
X
[A]-[A]+ [REG]
Add any register to A
[A]-[A] + [REG] + [e)
Add with Carry any register to A
[A]-[A] - [REG]
Subtract any register from A
[A]-[A] - [REG] - [e)
Subtract any register with borrow from A
[A]-[A] "[REG]
AND any register with A .
[A]-[A]¥-[REG]
Exclusive-OR any register with A
[A]-[A] v [REG]
eMP
REG
1
X·
X
X
X
X
1
[AI - [REG]. Discard result but set flags.
DAD
RP
1
·x
0
Compare any register with A
[H.LJ-[H.L]+ [RP]
Add to HL
INR
REG
1
X··
X
X
X
0
OCR
REG
1
X··
X
X
X
1
X··
X
X
X
a:
W
c:;~
ffi~
c:;
W
~
I
a:
W
o
CMA
1
OM
1
X
RLC
1
X
OR any register with A
[REG]-[REG] + 1
Increment any register
[REG]-[REG] - 1
Decrement any register
[A]-[A]
Complement A
a:
W
WI-
1-",
~ffi
~~
;·O . J I I I I I I I I iJ
Decimal adjust A
Rotate A left with branch carry
cOJ ..1 I I I I I I I ~
RRC
1
X
Rotate A right with branch carry
© ADAM OSBORNE &
.
ASSOCIATES. INCORPORATED
.
Table 4-4. A Summary of 8080A/9080AMicrocomputer Instruction Set (Continued)
STATUSES
TYPE
MNEMONIC
OPERAND(S)
BYTES
OPERATION PERFORMED
C
w
I-
~ww
0':
AC
Z
S
P
SUB·
LTI~- I I I I I I I I j:J
RAL
1
X
Rotate A left with'carry
RAR
1
X
_Rotate A right with carry
li{j
11.;:)
02
ffii=Z
I(/)0
52
w
a:;
INX
RP
1
DCX
RP
1
:-. I-
I I I I I I I
~
[RP]-[ RP] + 1
Increment RP. RP = BC. DE. HL or SP"
'[RP]-[RP] - 1
Decrement RP
~
u
~
PUSH
RP
1
POP
RP
1
[[SP]]-[RPJ. [SP]-[SP] - 2 }
Push RP contents onto stack
RP = BC. DE. HL or PSW
[RP]-[[SP]J. [SP]-[SP]+2
.
1
Pop stack into RP
[ H.Ll-- [[ SP]]
I-
(/)
XTHL
Exchange HL with top of stack
I11.
w
IZ
EI
1
Enable interrupts
1
Disable interrupts
1
Restart at addresses S·N. N = 0 through 7.
RST
(/)
;:)
N
STC
1
1
CMC
1
X
I~
l-
(/)
Statuses:
.
01
;:)
a:_
a:
-
[C]-l
Set Carry.
[C]-[C]
Complement Carry
NOP
1
N? operation
HLT
1
Halt
C
Ac
Z
S
P
X
0
Blank
Carry
Carry out of bit 3
Zero
Sign
ParityStatus set or reset
Status reset
- Status Set
Status unchanged
• . SUB status is present in NEC 8080A only
•.• NEC S080A does not modify these status flags
t The AMD 9080A always-resets
Ac to 0 for all Boolean instructions. The Intel 8085 sets Ac _to
instructions. and resets AC to 0 for all other Boolean instructions.
1 for all AND
Table 4-5. A ,Summary of Instruction Object Codes
and Execution Cycles
f
BYTES
CLOCK
PERIODS
FIGURE
OOXXOOOI
YYYY
3
10
4-22
Aci
'ADC
01dddsss
01110sss
1
4-13
ADC
1
7
4-16
01dddl10
OOdddll0
1
7
2
7
10110XXX
2
1
'I
M
DATA
B6
F6 YY
1
2
PORT
03
2
1
1
10
E9
llXXOOOl
l1XX010l
17
1
1
,~~
LXI
MOV
MVI
.
RP,DATA16
f
MOV
MOV
~~ t.
REG,REG
M:F~EG
'
.REG,M
REG,DATA
MVI
M,DATA
NOP
ORA
REG
ORA
ORI'
OUT
PCHL
pOP
PUSH
RP
RP
RAL
RAR
YY
36, YY
00
RC
RET
RLc
RM
RNC
\
YY
FIGURE
DATA
REG
CE yy
l0001XXX
2
1
7
4
4-15
ADD
M
REG
8E
l0000XXX
7
4
4-15
4-12
4-15 '
4-15
ADD
ADI
M
DATA
1
1
1
7
2
4-14
4-12
ANA
ANA
ANI
REG
M
DATA
7
4
7
4-15
4-15
10
4
C6 yy
10100XXX
A6
E6 yy
4
7
7
4-12
CALL
CD
ppqq
4-15
CC
CM
LABEL
LABEL
DC
ppqq
3
• 3
LABEL
FC ppqq
3
4-15
4-29
86
REG
11
4
4-18
4-12
CMP
CNC
M
LABEL
BE
04 ppqq
1
3
11/17
4-12
CNZ
CP
LABEL
LABEL
C4
3
11/17
F4
LABEL
DATA
LABEL
3
3
11/17
11/17
7
11/17
4
5/11
4-12
4-27
5/11
4-27
CPE
CPI
CPO
CZ
5/11
5/11
4-27
4-27
DAA
DAD
5/11
5/11
4
11
4-27
4-27
4-12
4-18
OCR
DCR
DCX
01
5/11
4
7
4-27
4-12
EI
HLT
4-15
4-15
IN
INR
PORT
REG
OOXXX100
4-25
4-13
4-23
INR
INX
JC
JM
JMP
M
RP
LABEL
OOXXOOll
DA ppqq
JNC
JNZ
LABEL
LABEL
JP
JPE
JPO
LABEL
LABEL
LABEL
LABEL
1
1
RRC
RST
RZ
N
EO
OF
l1XXXll1
SBB
REG
C8
l00IIXXX
1
1
SBB
M
SBI,
SHLD
SPHL
STA
DATA
ADDR
9E
DE YY
22 .ppqq
2
3
STAX
STC
RP
SUB
SUB
REG
M
SUI
XCHG
XRA
XRA
DATA
F9
1
1
1
7
16
'5(4)"
PPqq
OOOX0010
37 .
1
3
1
1
l0010XXX
96
1
1
4
7
2
7
4
4
32
06
YY
EB
10101XXX
AE
EE YY
E3
1
1
2
1·
4-~6
10
1
1
13
7
4
7
7
18(17)"
4-16
4-12
4-12
4-15
4-15
4-12
4-12
4-15
JZ
LOA
LOAX
4-15
4-21
LHLO
ppqq
YY
represents four hexadecimal digit memory address
represents two hexadecimal data digits
YYYY
X.
ddd '
represents four hexadecimal data digits
represents an optional binary digit
represents optiMal binary digits identifying a destination register
sss ,
represents optional binary digits identifying a source register
* The NEC 8080A has five instructions with unique execution times, defined above by
:'(N)* where N is the number of NEC 8080A instruction cycles.
4-32
LABEL
RP
REG
27
OOXX100l
OOXXX101
M
RP
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LABEL
ADDR
RP
ADDR
2
3
3
1
1
1
35
OOXX1011
F3
1
1
1
FB
76
DB YY
1
1
34
FA
C3
02
C2
F2
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ppqq
ppqq
ppqq
ppqq
ppqq
E2 ppqq
CA ppqq
3A ppqq
OOOX1010
2A ppqq
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2
1
1
1
3
3
3
3
3
3
3
3
3
3
1
3
4-26
4-26
1
1
1
PP<1q
ppqq
EC ppqq
FE yy
E4 ppqq
CC ppqq
4-12
4-15
4-15
11/17
4
3F
10111XXX
4-27
4-19
4-12
11/17
2F
1
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7
17
CMC
CMP
C9
07
F8
DO
RPE
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2
CMA
4
5/11
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1
1
1
4-13
4-19
5
1
FO
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1
1
1
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DATA
BYTES
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CO
ADDR
OBJECT CODE
" 5(4)"
INSTRUCTION'
08
RNZ
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XRI
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CLOCK
OBJECT CODE
INSTRUCTION
4
4
7
11/17
4
10(11)*
5
10
5
4
4
7
10
5
10
4-12
4-12
4-12
4-15
4-26
4-26
4-26
4-26
4-15
4-26
4-26
4-12
4-20
4-13
4-14
4-13
4-12
4-12
4-30
4-28
4-13
4-14
5
10
4-13
4-22
10
10
4-22
4-22
10
10
10
4-22
4-22
13
4-22
4-22
4-22
4-22
4-24
'7
16
4-15
4-17
10
10
10
INSTRUCTION EXECUTION TIMES AND CODES
Table 4-5 lists instructions in alphabetic order, showing object codes and execution times, expressed as
machine cycles.
c
w
~
oa..
a:
a:
o
o
~
enw
I-
et
(;
oCJ)
Where two instruction cycles are shown, the first is for "condition not met" whereas the second is for "condition met".
Detailed timing for instructions is provided by Figures 4-12 through 4-30. Table 4-5 identifies the timing diagram that
applies to each instruction.
Instruction object codes are represented as two hexadecimal digits for instructions without variations.
Instruction object codes are represented as eight binary digits for instructions with variations; the binary digit
representation of. variations is then identifiable.
The NEC 8080A has four instructions with execution times that differ from the Intel
8080A. These four instructions are the Register Move (MOVi. the Return (RET). the 16-bit Add
(DAD). and the Exchange instructions XTHL and SPHL.
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STC, CMC, CMA. Nap, RLC, RRC, RAL. RAR. XCHG, EI.
DI. DAA, ADD R, ADC R, SUB R, SSB R, ANA R, XRA R, ORA R, CMP R
4-33
NEC 8080A
INSTRUCTION
EXECUTION
TIME
DIFFERENCES
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POP. RET
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Figure 4-20. Signal Sequences and Timing for Instructions:
DAD
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XTHL
T4
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.
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MC2
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Figure 4-27. Signal Sequences and Timing for Instructions:
RNL RL RNC.
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Figure 4-28. Signal Sequences and Timing for Instructions:
IN
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Figure 4-29. Signal Sequences and Timing for Instructions:
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Figure 4-30. Signal Sequences~and Timing for Instructions:
.
HLT
Interrupt Terminates Halt
MC1
SUPPORT DEVICES THAT MAY BE USED
,
WITH THE 8080A
Of the microprocessors described in this book, none have a wider variety of support devices than the 8080A.
These support devices are described in the rest of Chapter 4 and in Volume III. Most of the devices described
were originally developed by Intel, although a few were not. Note that the 8224 Clock Generator and the 8228
System Controller devices are used so routinely with the 8080A that they frequently are looked upon as a three-chip
CPU. An exception to this three-chip concept is the TMS 5501 made by Texaslnstruments; it cannot be used with an
8228 System Controller.
A number of general-purpose support devices are described in Volume III. These are support devices that may be used
with any microprocessor and are specific to none.
One generalization that can be maderegarding 8080A support devices is that the 8080A is so well endowed with support logic that it will rarely make m~ch sens:e to use another micro'processor's support part in preference.
It is very difficult to use 6800 support devices with the 8080A because 6800 support devices require a synchronizing
strobe signal which is difficult to generate within an.8080A system.
. THE 8224 CLOCK GENERATOR AND DRIVER
The primary purpose of this device is to provide the 8080A CPU with its required <1>1 and <1>2 clock signals. Coincidentally, the 8080A READY and RESET inputs are created, with correct synchronization. Recall that these two
signals must be ~ynchronized with <1>2.
'
Logic implemented on the 8224 Clock Generator corresponds generally to the block labeled "Clock Logic" in
Figure 4-1. To be completely accurate, however, a small portion of the Bus Interface Logic should also be illustrated as provided by the 8224 device.
"
'
8224 CLOCK GENERATOR PINS AND SIGNALS
8224 pins and signals pre illustrated in Figure 4-31. Figure 4-33 illustrates the 8224 connected to an 8080A
CPU and
8228 System Controller.
an'
Signals may be divided between tilTling logic and control logic.
,
I
.
I
Clock frequency is controlled by a crystal connected to the XT AL 1 and XT AL2 pins. Crystal, 8224
frequency must be exactly nine times' the required clock frequency. The fastest clock period
CLOCK
SIGNALS
supported today is 250 nanoseconds, provided by the AMD 9080A. 500 nanosecond clock
periods are standard. Since crystal frequency has to be nine times the clock frequency, the usual, ..._ - -..
500 nanosecond clock will require an 18 MHz frequency crystal.
If an overtone mode crystal is employed, then it must be supported by an external LC network, connected to
the TANK input. This is standard'clock logic practice; microprocessor clock logic represents no special case, therefore
we will not discuss overtone· mode crystals further.
'
4-46
RESET
RESiN
RDYIN
READY
SYNC
1112 (TIL)
c
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a:
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STS'i'B
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GND
a:
o
-.. --- ----..
--
1
2
3
4
5
6
7
8
8224
16
15
14
13
12
11
- 10
9
------ ..
--.
---.
VCC
XTALl
XTAL2
TANK
OSC
1111
1112
VDD
~
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PIN NAME
w
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RDYIN
READY
SYNC
1112 (TTL)
STSTB
XTAL l,XTAL2
TANK
OSC
1111, 1112
ct
IllS
w
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a:
o
a:J
UJ
o
::!:
ct
c
ct
VCC,VDD,GND
@
Output
Input
Input
Output
Input
Output
Output
Input
Input
Output
Output
Control signal output to 8080A
Reset logic input
Ready logic input
Control signal output to 8080A
Control signal input from 8080A
TTL level duplicate of 1112
Sync signal output to 8228External crystal connections
Overtone crystal extra input
Crystal oscillator waveform
Clock signals to 8080A
Power and Ground
ReSiN
UJ
UJ
TYPE
DESCRIPTION
RESET
Figure 4-31. 8224 Clock Generator Signals and Pin Assignments
The principal clock-signals output are <1>1 and <1>2, as required by the 8080A CPU.-These tyvo clock signals are
derived from a divide-by-nine counter that defines <1>1 and <1>2 as follows:
<1>1
I
I
---1I
I
3
2
.
,
~
I
I
1112
I
I
I'
I
5
6
7
8
,
I
I
I
I
I
I
I
I
I
9
I
1
I
- I-
Two additional timing ?ignals are output:
The crystal oscillator frequency is output as OSC.
A TTL level duplicate of <1>2 is also output for general use within the microcomputer systen:t.
The RESET input signal required by the 8080A CPU is usually generated by special external logic to provide
sharp signal edges and synchronization with the <1>2 clock pulse. Consider one common use of RESET - to detect
power failure. A vague input may have to be converted into a crisp RESET as follows:
Threshold
Input (RESIN)
::::::::::-::-::-:-:::,~~~~~~.g~~_.;...__....._._I./~
__~__;._=.:_:.;_:.:_:.
1112
RESET
4-47
.The 8224 Clock Generator will accept a sloppy input, as illustrated above by RES I N, and in response will create
a sharp RESET output that conforms to the requirements of the 8080A CPU. A Schmitt trigger within the logic of
the ~224 clock chip creates the appropriate reset logic level change when RESIN falls below a threshold level.
RESET is also frequently connected to manually operated switches; this allows the microcomputer system to be reset
by human intervention. The following simple circuit creates the appropriate RESIN input to the 8224 Clock Generator
so that either power failure oran external switch may reset the CPU: '
Vee (Power
fail detect source)
~--------~--------------------------RESIN
--
--
. READY logic accepts an asynchronous RDYIN signal and creates a synchronous READY input to the 8080A
'CPU:
'
,
RO::
ry==
J\\_----(~~~._fL_:.
READY
Y
~
One further signal created by the 8224 Clock Generator is the status strobe signal STSTB, which is required by
the 8228 System Controller. This signal is of very little interest toa user since it simply accepts an 8080A SYNC output and converts it into the required 8228 STSTB input.
When comparing the 8080A microcomputer system with other devices, it would be inaccurate to dismiss the
822~ Clock Generator simply as an additional device - which must be added to an 8080A system, supplying
logic which is commonly found on competing CPU chips. Do not forget the reset logic capability provided by the
8224 Clock Generator,
"
it can be argued that the 8080A CPU creates an artificial restriction - that RESET and READY inputs must. be synchronized with <1>2; therefore the fact that the 8224 does this for you. simply eliminates a self imposed problem that
should never have been 'there in the first place, This reasoning has merit. but the ability' of the 8224 to receive a ragged
RESIN input is a valuable feature that should not be overlooked,
."
..'.,'
THE 8228 AN~ 8238 SYSTEM CONTROL~'ER AND BUS DRIVER
The 8228 System Controller consists of a bidirectional bus driver, plus control signal generation logic. The 8238
Sy~temControlier advances IIOW and MEMW to give large me'mories mo~e time 'to respond to a memory write.
BUS D~IVER LOGIC
Alarge number of memory and 1/0 devices may be connected directly to the 8228 bidirectional Data Bus; such
connection~'to the 8080A Data Bus would not be feasible. Remember. memory devices leak current even when
they are'notselected; therefore. even the passive load ofunselected memory devices connected directly to an 8080A
CPU will leak more currerit than is available,
"
4-48
When comparing the 8080A microcomputer system with an alternate microcomputer system, you should look
carefully at the fan out provided by the alternate CPU.
If the alternate CPU busses need to be buffered. then the 8228 System Controller becomes the equivalent 8080A
system device; as such it does not represent an economic liability,
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(/)
ct
all
If the alternate CPU busses do not need to be buffered. then the 8228 System Controller represents an additional
device. peculiar to the 8080A system.
CONTROL SIGNAL LOGIC
The 8228 combines the three 8080A control signals: WR, OBIN and HLOA, with the statuses output on the
Data Bus during T2 in order to generate bus control signals as follows:
MEMR status on 07 true. with DBIN true generates MEMR true
OUT status on 04 false. with WR true generates MEMW true
INP status on 06 true. with DBIN true generates IIOR true
OUT status on 04 true. with WR true generates I/OW true
INTA status on DO true generates iNTA true
w
Z
----..
a:
o
CD
(/)
o
~
ct
Q
ct
@
STSTB
HLDA
WR
DBIN
DB4
04
DB7
07
DB3
03
DB2
02
DBO
GND
--
-..- :....
--- ..
-- -..
------ :.--..
--- --
.::
~
PIN NAME
00- 07
DBO - DB7
STSTB
HLDA
WR
DBIN
IIOW
MEMW
I/OR
MEMR
INTA
BUSEN
VCC·GND
1
28
27
2
3
4
5
6
7
,8
..--
26
25
24
8228
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
-...-
-=- ..=
--...
-- ..
.. ..
..: :
... :.
--
DESCRIPTION
~
IIOW
MEMW
IIOR
MEMR
INTA
BUSEN
06
DB6
05
DB5
01
DBl
DO
TYPE
Data Bus connection to CPU
Data Bus to external logic
Status strobe input from 8224
Bidirectional
Bidirectional
Input
Hold acknowledge input from CPU
Data output strobe. input from CPU
Data input strobe. input from CPU
1/0 write control output
Memory write. control output
Input
Input
Input
I/O read control output
Memory read control output
Output
Output
Output
Input
Interrupt acknowledge control
DB Bus float/enable control input
Output
Output
Power and Ground
Figure 4-32, 8228 System Controller Signals and Pin Assignments
8228 SYSTEM CONTROLLER PINS AND SIGNALS
8228 pins and signals are illustrated in Figure 4-32.
DO through 07 represent the bidirectional Data Bus connection between the 8228 System Controller and the 8080A
CPU; it is referred to as the "Processor Data Bus",
OBO through OB7 represent the high fan out. bidirectional Data Bus accessed by external logic; it is referred to as the
"System Data Bus",
4-49
WR, DBIN and HLDA represent the control signals of the same name that are output by the 8080A CPU
All control bus signals use active low logic and may be defined as follows:
MEi\iiR -
a read from memory strobe
MEMW - a write to memory strobe
I/OR - a read from external I/O strobe
I/OW -
iNTA -
a write to external I/O strobe
interrupt acknowledge
Control signal timing .is given in Figure 4-34.
The interrupt acknowledge signallNTA has two special features which need to be explained. This signal may be
tied to a +12 Volt power supply through a 1 K Ohm resistor, in which case 8228 logic assumes that there is only one
possible interrupting source within the microcomputer system. Now the 8228 will automatically insert the object
code for an RST 7 instruction in response to the interrupt acknowledge. This means that external logic does not
need to supply the first post-interrupt instruction's object code. Of course, this means that all interrupt service'routines
effectively begin with the execution of an RST 7 instruction.
If external logic responds to the INTA low pulse by supplying the first byte of a CALL instruction's object code
(11001101), then the 8228 System Controller will automatically generate two more INTA low pulses for the
next tW..E..!!!achine cycles. See Figure 4-34 for i'i\iTA pulse timing within the machine cycle~ Now external logic can
use the INTA pulse as a memory deselect and an interrupt acknowledge logic select. Here is a very general illustration
of external logic that responds to an interrupt acknowledge by supplying the CPU with a three-byte CALL instruction's
object code:
INTA
t
from
8228
Any pulse
count logic
Select true on
first i'NTA pulse
i.
Select true
on second
iNTA pulse
Select true on third
i'NTA pulse
--
Data Bus to CPU
Program memory
select (High true)
.....
--
-.4-50
8-bit port,
holds 11001101
(a CALL instruction)
8-bit port,
holds Call
address, low
order byte
8-bit port,
holds Call
address, high
order byte
-
----
.
AO
GNO
+W
·W
+12V
C
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W
a:
0
Q.
a:
0
CJ
~
13
SYSTEM DMA REa.
1~
SYSTEM INT. REa.
16
INT. ENABlE
HOLO
INT
8080A
BUS
INTE
TANK
OSC
CI)
CI)
2(ml
ct
RDYIN
W
Z
a:
<1>1
<1>2
WAIT
READY
RESET
ReSiN
_000
_OBI
_DB2
_DBJ
_DB4
_OBS
_DOO
_OB7
05
+ 12V
+5V
GNO
S
19
De
07
SYNC
a:I
CI)
0
ct
MEMR
. SYSTEM
CONTllOL
STATUS STROBE
~W
imm
iToW
C
ct
@
Figure 4-33. A Standard. Three Device 8080A Microcomputer System
--
I
Instruction Fetch
I
Instruction
Execute
Data Out
.-c;-
MCl
T,
I,
T2
I-
II
Me2
T3
II
T4·
T,
I1_
T2
I
T3
READ1\1
I
rf\
WAIT
1
I
1:+-----~~._--~~--~~----~~~----_4--~--~--~~_P--
I
DBIN~+-_~~""'J
WR1J:I~--~-'--------~~--~~+-------P-~
~--~~
I
I
MEMRI
I
(I/OR or INTA) I
I
MEMW:------~~------~------~:-------+------~------~~,
orl/OW I
I
I
I
Figure 4-34: Timing for Control Signals Output by
the 8228 System Controller
4-51
}~,.
W}
0
~
ADDRESS
BUS
DBiN
HLOA
...
ct
olI
AO
AI
A2
A3
A4
A5
Ae
A7
AS
AS
AIO
All
A12
AI3
AI4
AIS
Wii
en
w
g
25
AI
A2
A3
A4
A5
Ae
A7
AS
A9
AIO
All
AU
AI3
AI4
AIS
BUS
CONTROL
BUS
Recall that the NEC 8080A generates three INT A low output pulses in response to a Call instruction object code being
returned during the interrupt acknowledge process. But the NEC 8228 System Controller does not assume that these
three low INTA pulses will occur. Thus the NEC 8228 System Controller may be used with an NEC 8080A or any
other 8080A.ln every case the NEC 8228 will generate three low INTA output pulses when external logic responds to
an interrupt acknowledge by providing a Call instruction object code.
The status strobe STSTB which is output by the 8224 Clock Generator is a variation of the SYNC output from the
8080A CPU. STSTB synchronizes the 8228 System Controller and is of no other concern to an 8080A user.
BUSEN is an external input to the 8228 System Controller. This is a very useful signal because it allows external
logic to float the Data Bus. When this signal is input low, the bidirectional bus driver logic of the 8228 System
Controller presents a high impedance to the external Data Bus, thus allowing external logic to gain access to
this bus.
Figure 4-33 illustrates the way in which the 8080A CPU normally combines with the 8224 Clock Generator and the
8228 System Controller. These three devices are frequently looked upon as a single entity.
THE 8259 PRIORITY INTERRUPT CONTROL UNIT (PICU)
This is a very flexible, programmable interrupt handling device; it provides a CALL instruction's object code in
response to three interrupt acknowledge (lNTA) signals; the 8228 System Controller responds to an interrupt
acknowledge in this fashion, as described earlier in this chapter. Therefore the 8259 PICU should be looked
upon as a companion to the three-chip (8080A, 8224, 8228) microprocessor system.
The 8259 PICU cannot be used with non-8080A systems.
A single 8259 PICU with an 8080A microcomputer system will handle up to eight external interrupts, providing
a variety of programmable interrupt priority arbitration schemes.
Alternatively, an 8080A microcomputer system may have a single 8259 PICU designated as a master, controlling up to eight additional 8259 PICUs designated as slaves. This allows a maximum of 64 levels of interrupt
priority. Priority arbitration schemes may be set independently for the master and for each slave, resulting in a
bewildering profusion of priority arbitration possibilities.
Use extreme caution before including master and slave PICUs within an 8080A microcomputer system. When
an application is implemented around a microprocessor with the general speed and performance characteristics
of an 8080A, then it is usually more efficient to handle numerous external request lines using multiple CPU configurations and/or programmed polling techniques, rather than interrupts.
The 8259 PICU is fabricated using NMOS technology; it is packaged in a 28-pin plastic DIP. All outputs are TTL
compatible.
With reference to the standard logic functions' illustration used throughout this book. the box marked "Interrupt
Priority Arbitration" represents the functions implemented by the 8259 PICU. But it is hard to equate the large number
of options provided by the 8259 PICU with the interrupt logic provided by other microcomputer systems. An application that needs the 8259 PICU would certainly not be satisfied by Interrupt Priority control logic provided by almost any
other device described in this book.
8259 PICU PINS AND SIGNALS
8259 PICU pins and signals are illustrated in Figure 4-35; we will summarize these signals, then discuss how
the PICU is used.
From the programmer's point of view, the 8259 PICU will be accessed either as two I/O ports, or as two memory 10cations.CS is a typical chip select and AO identifies one of two I/O ports or memory locations. The way you.
as a programmer. must interpret the function of each 8259 PICU I/O port or memory location depends on an intricate
logical sequence.
The two 8259 addressable locations are accessed via the Data Bus (DO - 07).
lOR and lOW are standard read and write control signals. If the 8259 PICU is being accessed as two I/O ports. then
these two signals will be connected to the IIOR and IIOW controls output by the 8228 System Controller; on the other
hand. if the 8259 PICU is being accessed as two memory locations. then lOR and lOW must be connected to the MEMR
and MEMW controls output by the 8228 System Controller.
External devices requesting interrupt service have their request signals connected to IRO - IR7. A high level on
anyone of these signals will be interpreted as an interrupt request. An interrupt request is passed on to the CPU via
the INT signal. This is illustrated in Figure 4-36.
4-52
In a configuration that includes master and slave 8259 PICUs external logic will connect to the interrupt request
signals (lRO - IR7) of the slave PICUs only. The INT outputs of the slave PICUs will be connected to the interrupt requests (lRO - IR7) of the master PICU. This is illustrated in Figure 4-37.
c
w
When more than one 8259 PICU is present in a system. SP identifies the master and slave units. SP high defines the
master. while SP low forces an 8259 PICU to operate as a slave. SP also determines the sense of the three cascade
lines (CO, C1, C2); these are output lines from the master and input lines to a slave.
~
a::
o
0.
The 8080A CPU provides the standard interrupt acknowledge via INTA. This interrupt acknowledge will be
received by all 8259 PICUs in the system. master or slave.
o
In a system that includes a master 8259 PICU only, the three bytes of a CALL instruction's object code are output via the Data Bus in response to the three INTA control signals arriving from the 8228 System Controller. The
second and third bytes of the CALL instruction's object code provide an address which is unique to the selected interrupt request.
a::
(.)
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ct
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o
(f)
(f)
ct
ell
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Z
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oen
(f)
o
~
In a configuration that includes master and slave 8259 PICUs, the master PICU outputs the first byte of a CALL
instruction's object code; the master also outputs a value between 000 and 111 via the three cascade lines
(CO - C2). This three-bit binary value identifies the interrupt request level being acknowledged - and therefore
the slave PICU being selected. The selected slave P.ICU provides the second and third bytes of the CALL'instruction's object code in response to the second and thi'rd II'.!TA pulses output by the 8228 System Controller.
Thus the slave PICU identifies the interrupt request I~V~! it is acknowledging.
The interrupt acknowledge logic of the 8259 PICU is referred to as "Vectoring". Let us examine 8259 vectoring
in more detail.
ct
ct
C
@
cs
1
lOW
2
28
' 27
3
26
4
25
24
-.,
i5R
D7
D6
D5
D4
-
..
5
.,
6
7
8
D3
D2
D1
DO
CO
C1
GND
--
9
10
11
AO
INTERRUPT
CONTROL
UNIT
-
INTA
IR7
IR6
IR5
23
PRIORITY
22
IR4
21
IR3
20
19
,18
17
12
13
16
14
15
"
-
IR2
--
IR1
IRO
INT
SP
a
C2
DESCRIPTION
PIN NAME
CS
8259
VCC
AO
Device Select
Identifies PICU as one of two
TYPE
Input
Input
I/O ports or memory locations
Tristate. Bidirectional
DO - D7
Data Bus
iOR
loW
Read control signal
Write control signal
Input
, Input
IRO -IR7
Interrupt request lines to PICU
'Input
INT
Interrupt request sent by PICU
Output
iNTA
SP
Interrupt acknowledge
Input
IdE:ntifies PICU as either master
Input
co - C2
or slave
Cascade lines select slave in
multiple PICU systems
VCC. GND
Output on master
Input on slave
Power and Ground
,Figure 4-35. 8259 Priority Interrupt Control Unit Signals And Pin Assignments
4-53
MEMR ori/OR
INT
MEMW
8228
or TfOi1J
SYSTEM
-
8080A
CPU
CONTROLLER
-
INTA
. ....
AO
DBO •• • "•••
A15
DB7
..
~O
,
--
-'
........
--
DO
.....
INT
ADDRESS:
DECODING
AO
~
CS
or07
07
iOR
~
8259
PRIORITY
INTERRUPT
CONTROL
-loW
iNTA
UNIT
"
IRO
DEVICE
0
. IIRl •••••• • ••••• ·1·IR6
DEVICE
1
DEVICE
6
IIR7
DEVICE
7
Figure 4-36. A System With One PICU
THE 8259 PICU INTERRUPT ACKNOWLEDGE VECTOR
Vectoring is a general term used to identify an interrupt acknowledge sequence which results in the immediate
identification of the interrupting external source. With a non-vectored interrupt acknowledge, the CPU must execute some instruction sequence whose sale purpose is to identify the source of the interrupt - and that assumes
,
'more than one possible external interrupting source. '
Recall that when an interrupt request is "acknowledged by a three-device 8080A microprocessor
system, the 8228 System Controller outputs a low pulse on the INTA control line. External logic
must interpret the low INTA pulse as a signal to bypass normal instruction fetch logic, and provide
the object code for the first instruction to be executed following the interrupt acknowledge. (If this
is new to you, refer to our discussion of the 8080A and 8228 devices.) If a CALL instruction's object code (CD16) is returned to the 8228 System Controller, then low INTA pulses are output for
4-54
------..
8080A
INTERRUPT
RESPONSE
USING CALL
INSTRUCTION
the next two machine cycles - thus making it easy for external logic to fetch all three bytes of a CALL instruction's object code. The 8259 PICU uses this 8228 logic to supply a three-byte CALL instruction's object code as the first
instruction executed following an interrupt acknowledge. But a ~ALL irstruction's object code is interpreted
thus:
.'
"
~
a:
o
~
D.
· ".-
-----..v~-----'./
16-bit address of called subroutine's
CALL
a:
Byte 3
Byte 2
Byte 1
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first executable instruction
:!!E
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~
There are two ways in which the 8259 PICU can compute the address portion of the CALL instruction object
code (bytes 2 and 3). These are the two options:
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en
en
«
oil
Option 1
Option 2
XXXXXXXXXXXYYYOO
XXXXXXXXXXYYYOOO
w
X
represents binary digits which are defined. under program control. to be a constant portion of the Call address,
a:
Y
represents binary digits which identify the interrupt priority level (000 through 111).
ca
en
Since the CALL is the first instruction executed following an interrupt acknowledge. it causes program logic to branch
to a memory location which is uniquely set aside for a single external interrupting source. Suppose you have selected
CALL instruction Option 1, as illustrated above. You would then Set aside. an area of memory for a jump table. as
follows:
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o
o
:!:
«
c
«
@
PROGRAM
MEMORY'
XXXXXXXXXXXYYYOO
o0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 - - - - -....-
3800
(3
JMP
} ADDR1
Unused
3804
(3
etc
JMP
} ADDR2
Unused
3808
(3
l
JMP
ADDR3
Unused
380C
(3
JMP
~ADDR'4
Unused
3810
(3
etc.
Memory addresses have been selected arbitrarily in. the illustration above.
4-55
Program logic does not have. to determine the source of an interrupt. You simply orlgrn separate interrupt service
routines at starting addresses specified by the Jump instructions in the jump table. This may be illustrated asfollows:
MORE
PROGRAM
MEMORY
PROGRAM
MEMORY
"1-r.t
OEOO
OEOl
(3
3800
80
OE02 ....----4
OF
OE03
OE04 t - - - - 4
'(3
3804
ADDR2
00
-
- .
'OF
~!l08- "'" (3
..
"
~OO
Of'
~
'.'
(3'
380C
80
00
The illustration above arbitrarily assumes that the interrupt request arriving at IR2 has its service routine origined at
OE0016. In this example. the address vector provided by the 8259 is 380816:
2
--'-
XXXXXXXXXXXYYYOO
0011100000001000
~
--...-.-- '-v-" '-.,-..'
3
8
0
8
MEMR or
C~U
JAO
AO
l
f'
.~
~'
I
ADDRESS
DECODING
4
too .. ·t
---
IVeel
~AO If~om
r----
8259
PICU
PICU
(Masterl
CS
~
~
~ B' (from Addres! Oecoding Iogicl
PICU
ISiavel
CO
INT
sp-r
t
L~
To level 7
8259
~ (fro!!l Address
INT
Slava
t
07
____ AO (from Address Busl
Addr.s. Busl
' Decoding)
ISlavel
IR6
To level 6
Slave
CS
I
IRO . . .
IR;:::::t'R5
DEVICE
0
DEVICE
•
5
I
"
DEVICE
14
II
IRO"
IR7
DEVICE.
21
V
,.
• DEVICES AT MASTER PlCU LEVEL 7
Figure 4-37.
A System
With Three PICUs -
4-56
DSO" ,.DB7
~
r-----.
CO
Cl
C2
8259
t
I-INTA
iNi'A
+ 5V.i!!.-
DO· . .
~
lOW
CS
j
D7 _
lOR
~
~
I
CONTROLLER
l
..
tDO .. ·tD7_
lOR
INT' '.
A15
8228
SYSTEM
iN'fA
•• , A15
t
iToR
MEMW o;TroW
~
8080A
I
'-
DEVICE
6
•
II
IR7
DEVICE
13
'V'
,;
DEVICES ZT'MASTER PICU LEVEL 6
One Master And Two SI?ves
At memory location 380816. the object code for the instruction:
JMP
ADDR2
takes us directly to the required interrupt service routine.
8259 PICU PRIORITY ARBITRATION OPTIONS
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Priority arbitration logic is used to determin~ which interrupt request will be acknowledged when two or more
interrupt requests exist simultaneously. The 8259 PICU allows interrupt priorities to be specified at two
levels - which need to be clearly separated and identified.
As discussed in Volume 1- 8asic ConceRts. interrupt priority arbitration usually applies to simultaneous interrupt requests: at the instant an interrupt is acknowledged. if more than one external requesting source is requesting an interrupt, priority arbitration logic decides which single interrupt request will be acknowledged. Once an interrupt
has been acknowledged. priority arbitration has nothing to do with whether the interrupt ser.vice routine can itself be
interrupted. or by whom.
, .
The 8259 PICU extends interrupt priorities to the service routines themselves. Once an interrupt has been
acknowledged. its service routine can only be interrupted by a higher priority interrupt.
If you are unsure of the difference between interrupt priority arbitration at the point when interrupts are acknowledged.
as against priority arbitration for the entire duration of an interrupt service routine. then refer to Volume I - 8asic Con£f3RtS. where this subject is covered thorough!y.
CD
(/)
o
Let us now look at the various priority arbitration options provided by the 8259 PICU.
~
The Fully Nested Mode is the default case. Interrupt priorities are set sequentially from 0 (highest) to 7 (lowest).
«
Q
«
@
As we will describe shortly. the 8259 PICU must be initialized by an appropriate instruction sequence before it can
be used in any way. Upon completing programmed initialization, Fully Nested Mode is ttle priority arbitration option in force. It takes additional instructions to specify a'ny other priority arbitration option.·
8259 PICU
In Fully Nested Mode. interrupt priorities will never change. An interrupt request arriving at an IR
INTERRUPT
line will never be acknowledged if an interrupt request exists at a higher priority line. or if an interSERVICE
rupt service routine is being executed in response to a higher priority interrupt request. Conversely. once an interrupt has been acknowledged. the interrupt service routine which is sUQseROUTINE
PRIORITIES
quently e.xecuted may be interrupted only by a higher priority interrupt. It makes no difference
whether interrupts have. or have not been disabled. the 8259 PICU will ignore all interrupt requests at priority levels below that of an interrupt service routine currently being executed. For example. suppose interrupts are being requested simultaneously at levels 2 and 5. The level 2 interrupt will be acknowledged and its interrupt
service routine will be executed. While the level 2 interrupt is being executed. the level 5 interrupt requeslwill be
denied by the 8259 PICU. whether or not interrupts have been disabled at the CPU. However. if an interrupt request arrives at priority level 1. the PICU will acknowledge this interrupt request. and will allow the level 2 interrupt service
. '
routine to be interrupted. This may be illustrated as f o l l o w s : '
".lioe,,?
Interrupts are requested
Denied - IR5 IR2 - acknowledged
I
Program
executing
An interrupt request at IR5.
if still pending. can now
be acknowledged
Ir'----.
New interrupt
request appears
at IRI
Interrupt is
IR2 request's
higher priority
than IR2. so
is acknowledged
service routine
is executed
IRI request's
service routine
is executed
4-57
It is very important to understand that the 8259 PICU extends interrupt priority logic beyond the interrupt
acknowledge. to the interrupt service routine itself. Standard priority arbitration logic does not extend to the interrupt
service routine. Thus. in the standard case if interrupts were being requested at prio~ities 2 and 5. then the priority level
2 request would be acknowledged. but the priority level 2 interrupt service routine could be interrupted by the level 5
interrupt request. unless all interrupts were disabled at th.e CPU - in which case pn interrupt request at level 1 would
also be denied.
'
If you do not want to extend interrupt priorities to the interrupt service routines. you can output a Special Mask Mode
comlTla~~ (which we will describe shortly) to selectively enable interrupt requests of lower priority than the currently
exec~ting interrupt service routine.
~otating Priority, Mode A is the next option. This differs from the Fully Nested Priority Mode.
which we just described. in that after being serviced. a request is immediately relegated to lowest
priority. This may be illustrated as follows:
8259 PICU
ROTATING
INTERRUPT
PRIORITIES
Priorities assigned to IR lines
'~
rLowest
7
IR7
IR2
IRS
Before first acknowledge
After first acknowledge
~fter
second acknowledge
.
"-
Highest
6
IR6
IRl
IR4
S
IRS·
IRO
IR3
4
IR4
IR7
IR2
3
IR3
IR6
IRl
2
IR2·
IRS·
IRO,
0
IRl
IR4
IR7
IRO
IR3
IR6
• id~f1tifies active interrupt r~quests.
In a microcomputer system that makes heavy use of interrupts, Rotating Run in Priority Mode A may be a necessary
replacement for the default Fully Nested Priority Mode. In the default case, the lowest priority levels may get little or no
service if there is heavy interrupt traffic. In an application that does not have a well defined hierarchy of interrupt
priorities. a rotation of priorities, as illustrated above, is superior - because it has the effect of giving every priority
level equal service.
Rotating Priority MoqeA is implemented as a sequence of single programmed events. The microprocessor outputs an
appropriate Control code to the 8259 PICU upon completing'every interrupt service routine. Thus Rotating Priority
Mode A is not a perman~ntly specified PICU condition: each rotation represents a single response to a single Control
l
code - unconnected to previous or future priority selections . For the moment. however, it is not necessary that you understand the programrnin~ techniques emp!oyed when selecting 8259 interrupt priority rrodes: that is a subject we
will cover after completing the description of all available priority options.
'
Rotating prio'rity lYIode B gi~es you some fle.xibility in determining future priorities. Now under program control
you can fix the next division between top and bottom pr!
'i<
I'
."",
>i
{
"
I
'.."'"
'/.'• , I tLogictoHandl~
>
Arithmetic and
·Logic Unit
>Interrupt~eq~est~
from
Exterriill Devices
Iii:
I
Clock Logic
:.':c
--
Accumulator
Registeris)
~;)
,:
Instruction Register ~
.'." .• '.'••.••
,..:.
Ii
:
,
>,.
~
~
Data Counteris)
Control Unit
I~
Stack Pointer
i,'
~ Program Counter
Direct Memory
Access Control
Logic
.,.,.."".
System Bus
(i."·:·
"'..':,
RAM Addressing
and .
ROM Addressing
and
Interface Logic
.....
,<:
·'···"·x>
Read Only
Memory
,(,'
.'.....".
Interface Logic
.....'.
)/i
·"··' •.·.·.',,·,,,·':":i'··""",··,·
(".
>
"
.. "
p"
Read/Write
MerTlOry
t
'. . "."y
"::'
i,.
,>
.'.,
'Figure 4-38. Logic of the TMS 5501 Multifunction InputlOutput Controller
4-68
~
Q
w
~
a:
o0.
V BB
VCC
1
40
XMT
2
39
Xl0
VOO
3
38
Vss
RCV
4
5
37
36
07
6
35
06
05
a:
o
-
04
CJ
~
03
en
w
02
l-
01
g
AO
e(
DO
fI.I
fI.I
e(
":'
-.
-- .
Al
ILl
A2
A3
a:
CE
!Xl
fI.I
SYNC
ell
Z
o
o
ct>1
~
.
~
~
7
34
8
33
9
32
XII
XI2
"'"-
XI3
XI4
-
XI5
XI6
XI7
~
10
TMS
5501
Xo7
31
30
.....
29
~
13
28
~
14
27
11
12
15
26
16
17
25
24
18
23
-
~
..
-
X06
XOs
X04
Xo3
X02
XOI
.
XOO
19
22
INT
SENS
20
21
11>2
~
e(
Q
e(
DESCRIPTION
,;; PIN NAME
@
TYPE
Bidirectional
DO - 07
XIO - XI7
Data Bus to CPU
Data Bus from external logic
Input
XOO - xo-;
Data Bus to external logic
Output
XMT
Transmit serial data line
Output
RCV
Receive serial data line
SENS
INT
External interrupt sense
Input
Input
Interrupt request
O~tput
CE
Chip Select
Input
AO - A3
Address Select
Input
SYNC
Synchronizing signal (SYNC) from 8080A
Ihput
11>1. ct>2
Clock inputs. same as to 80abA
Input
VBB·VCC·VOO·VSS
Power Supply (-5V. + 5V. + 12Vl and Ground
.
Figure 4-39. TMS 5501 Multifunction Input/Output Controller Signals
and Pin Assignments
Do not miss the significance of XO negative logic; whatever yo~ write to the TMS 5501 for
parallel output will be complemented. XO signals are the inverse of the output buffer contents.
Serial I/O data uses the XMT and RCV pins. XMT is used to transmit serial data. whereas RCV is
used to receive serial data. Note that RCV is negative-true signal. whereas XMT is a positive-true
Signal.
TMS 5501
OUTPUT
SIGNAL
INVERSION
a
..
'
.
\
External logic may request interrupt service either via the SENS input or via the XI7 input. A low-to-high transition on either signal constitutes an interrupt request. SENS is always part of external interrupt request logic; XI7 must
be programmed for this purpose - in which case the eight XI pins cannot be used to input 8-bit parallel data. .
Logic internal to the TMS 5501 may also generate interrupt requests. Whatever the source of the interrupt request. it is passed on to the CPU via the INT interrupt request signal.
The TMS 5501 is acc~ssed either as 16 I/O ports or 16 inemory locations. Addressing logic consists of a chip
select (CE) and four address select inputs (AO, A 1, A2 arid A3).
The TMS 5501 receives the SYNC timing pulse, and this requires special mention. While SYNC is high. the TMS
5501 decodes statuS off the Oat? Bus. therefore the 8228 System Controller is not needed.
Additional signals required by the TMS 5501 are the two 8080A clock signals <1>1 and <1>2. Slight clock signal
variations will confuse serial I/O logic which computes baud rates internally.
4-69
A feature of the TMS 5501 which you must note carefully is that it cannot handle Wait
states. Any TW clock periods in a machine cycle will cause the TMS 5501 to malfunction.
TMS 5501
WAIT STATE
There is a further unlikely ramification of the TMS 5501 inability to handle Wait states. If you are
accessing the TMS 5501 as 16 memory locations, then you cannot have a Halt instruction's object code in the
memory location immediately preceding the 16 TMS 5501 addresses. If you do. the Halt instruction will execute.
following which the Address Bus will contain the address of the next sequential memory location -which now is a
TMS 5501 address. Thus. the TMS 5501 becomes selected. But the TMS 5501 logic cannot cope with a sequence of
'undefined clock periods. which is exactly what will happen following a Halt instruction's execution. The net effect is
.that following a Halt. the TMS 5501 receiver buffer loaded flag will be inadvertently cleared.
Always make sure that the memory address directly preceding the 16 addresses assigned to a TMS 5501 remains
unused.
.
TMS 5501 DEVICE ACCESS
,
,i
Some of the 16 I/O port or memory addresses via which the TMS 5501 device is accessed are equivalent to
memory locations, but others are command identifiers. Table 4-7 defines the manner in which addresses are interpreted.
You will find the TMS 5501 far easier to use if you address it as 16 memory locations. because that will give you access
to memory referencing instructions.
When creating TMS 5501 select logic. any of the select schemes described earlier in this chapter will do -with one
addition. Include READY as part of the select logic; if READY is low. a Wait state will follow. and that will cause the
TMS 5501 to malfunction. By making READY high a necessary component of device select logic. you can avoid this
problem.
In the following discussion of individual TMS 5501 capabilities. we will use programming examples to show the effec. tiveness of including the TMS 5501 device within your memory rather than I/O space.
Table 4-7. TMS 5501 Address Interpretations
A3
A2
A1
AO
FUNCTION
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
Read assembled serial input data byte out of Receiver Buffer
Read parallel data input via XIO - XI7
Read RST instruction code. as a data byte. when polling interrupt requests
Read Status register contents to the CPU
Write command code to the TMS 5501
Load. serial I/O Control register. specifying baud rate and stop bits
Write data byte to serial transmit logic
Write data byte to parallel output port
Write out interrupt mask byte to selectively enable and disable interrupts
Write initial count to Interval Timer 1
Write initial count to Interval Timer 2
Write initial count to .Interval Timer 3
Write initial count to Interval Timer 4
Write initial count to Interval Timer 5
No Operation
No Operation
0
0
0
1
1
1
1
0
0
O·
0
1
1
1
1
i
0
;
1
1
.
.
TMS 5501 addressable locations 3, 4 and 5 are used for status. and controls which generally apply to serial I/O
and interrupt processing. We will define how these ports are used now. in advance of our discussion of TMS 5501
serial I/O and interrupt processing capabilities.
.
.
4-70
Locations 3 and 5 apply to serial I/O logic. Location 3 is a Status register whose bits are interpreted as follows:
7 6
5 4 3 2 1 0
~Bit No.
I I I I I I I I :
c
w
.
•
!(
ex:
oQ.
~
~
Serial I/O Status register (Address 3)
+
1 Framing error detected
1 Overrun
ex:
error detected
o
u
1 No serial data being received
en
w
1 Transmit Buffer empty
1 Receive Buffer ready to be read
~
!(
1 Intenupt pending
en
1 Start bit as been de'tected
g
en
1 Serial data character being received
~
all
w
Z
ex:
oID
en
o
~
~
C
~
@
Bits 0 and 1 are standard framing and overrun error indicators.
If a framing error is detected. Status register bit 0 will be set to 1 and will remain 1 until assembly of the next complete
serial data character has been completed.
If Receiver Buffer contents are not read while the next serial character is being input and assembled. an overrun error
will be reported in bit 1 of the Status register. This error indicator will be cleared as soon as the Status register contents
are read. or when a reset command is output. Remember. you have the time it takes to receive. and assemble one
character in which to read the previous character out of the Receiver Buffer. This is because receive logic includes a
double buffer. A character is assembled in a Receiver register: when completely assembled. it is shifted to a Receiver
Buffer and the next character is assembled in the Receiver register:
RcV
I
Byte N
Receiver
Byte N being
Register
assembled
I
\
\
Byte N + 1
Byt~
N + 1 being
assembled
Contents
Receiver
Buffer
Contents
Assembled Byte N.
Assembled Byte N - 1.
waiting to be read·
waiting to be read
Status bits 2,3,6 and 7 monitor the condition of the serial data input signal. During a break. that is. when no valid
serial data is being input. status bit 2 will be high. As soon as a start bit has been detected. status bit 2 will be reset low
and status bit 7 will be set high. When the first valid data bit is detected. status bit 6 is also set high. When the
received character has been assembled in the Receiver Buffer. and may be read by the CPU. status bits 7 and 6 are
reset and status bit 3 is set. This may be illustrated as follows:
End of first data character
RCV
M
M
D
Bit 2
Bit 3
Bit 6
Bit 7
4-71
D
M
Marking
A
Start bit
D
Data bits
P
Parity bit
0
Stop bits
Status bit 4 applies to serial transmit logic. As soon as the Transmit Buffer is ready to receive another byte of data.
status bit 4 will be set high. It will remain high until new data has been loaded into the Transmit Buffer.
Transmit logic. like receive logic. is double-buffered. A byte of data is held in a Transmitter register while being output
serially; meanwhile. the next data byte may be loaded into a Transmitter Buffer. Transmitter Buffer contents are automatically shifted to the Transmitter register when' serial output of a data byte is complete. This may be illustrated as
follows:
XMT
Transmitter
Register
I
I
\
Byte N
Byte N + 1
Byte N being
Byte N + 1 being
output serially
output serially
Write Byte N + 1 into
Write Byte N + 2 into
transmitter Buffer
Transmitter Buffer
during this time
during this time
\
Contents
Transmitter
Buffer
Contents
Status bit 4 is high from the insti:lntTransmitter Buffer contents are shifted into the Transmitter register. until a new
data byte is written into the Transmitter buffer.
Status bit 5 isset whenever the TMS5501has an unacknowledged interrupt request. While this status bit is very
important in sedall/O operations. it also may have application elsewhere; this bit therefore may be looked upon asan
exception within the Status register. in that it is the only status flag that does not apply strictly to serial 1/0 operations.
TMS 5501 addressable location 5 is also dedicated to serial I/O. Into this location you must load a control byte
which selects baud rate. and the number of stop bits. Register contents will be interpreted as follows:
..
7 6 5 .. 3 2..
~~~~~~
. 0 ~ Bit
No .
.....----Baud Rate Register (Address 5)
~~
...____. . ;. __ j
~ ~[;~}.
_ _ _ _ _ _ _ _ _ 1 = 2400 saud
---------- 1
'------------1
"'------------ 1
Baud rates based
on 2 mHz clock
= 4800 Baud
= 9600 Baud
= One
stop bit
o = Two stop bits
If more than one of bits 0 through 6 are high. then the highest indicated baud rate will be selected. If no baud rate bit is
high. then all serial transmit and receive logic will be inhibited.
·4-72
TMS 5501 addressable location 4 is a general command register. Its contents will be interpreted as follows:
7 6 5
.c
3 2 1 0
~ Bit No .
......-
~~~~~~~~
.... COntrol Register (Address 4)
Q
w
~---
-----1o
~
oQ.
a:
a:
o
u
~-----
1 = Device reset
= Output
= Output
Mark on idle
space on idle
1 = Select XI7 as lowest priority interrupt
o = Select interval timer 5 as lowest priority interrupt
~
~-------, = Enable TMS 5501 interrupt acknowledge
enw
o = Disable TMS 5501
~
(j
ofI)
interrupt acknowledge
~-------- 0 = Normal baud rate and interval timing
1
fI)
ct
= TMS 5501 11>1 intemal clocking runs eight times normal rate. which
11 multiplies all baud rates in the baud rate register by 8. allowing
high speed data transfers at rates up to 76.8 kilo baud
ell
----------0
w
Z
a:
o
21 decrements the interval timers every 8 microseconds
= Normal operation
1 = INT outputs a clock whose frequency depends on bit 4. If bit 4 is reset
m
(0). the output frequency is the system clock frequency divided by 128.
fI)
o
If bit 4 is set (11. the output frequency is the system clock frequency
divided by 16.
....- - - - - - - - - - - C a n have any value
~
ct
Q
ct
@
If your system does not require interrupts from the TMS 5501, you can set bit 5 high to derive a TTL compatible
clock from the INT output.
If the TMS 5501 device is reset by outputting 1 to bit 0, then the following events will occur:
1)
Serial receive logic enters the Hunt mode. Status bits 2.3.6 and 7 are all reset however. reset
will not clear the Receive Buffer contents.
2)
Serial transmit logic will output a high marking signal. Status bit 4 will be set high indicating that transmit logic is
ready to receive another data byte.
3)
The interrupt mask register is cleared with the exception of the Transmit Buffer interrupt. which is enabled. (Interrupt levels and interrupt masking are described shortly.)
All interval timers are halted.
4)
The Reset has no effect on any of the following:
- Parallel input and output port contents
- Interrupt acknowledge enable
- Interrupt Mask register contents
- Baud rate register contents
- Serial Transmit or Receive Buffer contents
. Control command bit 1. determines whether serial transmit logic will mark or space when not transmitting data.
A 1 in bit 1 will cause serial transmit logic to mark (output high) while a 0 in bit 1 will cause transmit logic to space
(output low).
If Reset conflicts with the break specification. then Reset will override and transmit logic will mark. irrespective of the
break bit specification.
The TMS 5501 can receive an interrupt request from one of nine different sources. Using the eight Restart instructions.
each interrupt request is assigned one of eight priorities. For this to be possible. two interrupt sources share the lowest
priority interrupt level (RST 7); these two sources are an external request arriving via XI7 and the Interval Timer 5 time
out interrupt request. You use bit 2 of the control command to select which requesting source will be active at
any time as the lowest priority interrupt.
Bit 3 of the control command is a master enable/disable for TMS 5501 interrupt logic. If this bit is output as O.
then TMS 5501 interrupt acknowledge logic is disabled - and that effectively disables the entire interru pt processing
system. Observe that with interrupt acknowledge logic disabled you can still use polling techniques in lieu of interrupt
processing.
4-73
Table 4-S. TMS 5501 Interrupt Logic and Priorities'
Interrupt
and Mask
Bit
Data Bus
Status
05
04
03
o (highest)
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
RST
Instruction'
Interrupting Source
•
1
2
3
4
5
6
7 (lowest)
1
1
1
1
RSTO
RST 1
RST 2
RST 3
RST'4
RST 5
RST 6
RST 7
f
Interval Timer 1
Interval Timer 2
External SENS interrupt request
Interval Timer 3
Serial I/O Receiver Buffer full
Serial I/O Transmitter Buffer full
Interval Timer 4
Interval Timer 5, or external XI7
interrupt request, whichever has
beeri selected by commant;! code
TMS 5501 INTERRUPT HANDLING
The TMS 5501 responds to nine different interrupt requests, with priorities as defined in Table 4-S.
When an interrupt is acknowledged, INT is output high by the TMS 5501. If the TMS 5501 INT output is connected
to the SOSOA INT input. then the SOSOA will acknowledge the interrupt by outputting D1 high at SYNC high. The TMS
5501 responds to this acknowledge by placing an RST instruction's object code on the Data Bus. as required by standard SOSOA timing. This is an utterly standard SOSOA interrupt request/acknowledge sequence.
Interrupts may be selectively disabled by writing a mask to TMS 5501 Register S: see Table 4-7. A 0 bit will disable
an interrupt: mask bits are related to priorities as follows:
7 6 5
4
3 2 1 0 ...........- - Bit
I 1 I I I I I I :
~
, ,
t'
No.
TMS 5501 Register 8
Interval Timer 1
Interval Timer 2
External SENS interrupt request
Interval Timer 3
Serial I/O Receiver Buffer full
Serial I/O Transmitter Buffer full
Interval Timer 4
Interval Timer 5 or external XI7 interrupt request
Note that TMS 5501 interrupt priorities apply to the request/acknowledge sequence only -which is the standard
passive interrupt priority arbitration sequence used in most microcomputer applications. Once an interrupt is
acknowledged and is being serviced by an interrupt service routine. it is up to the programmer to disable all interrupts.
or selected interrupts. if the interrupt service routine is not itself to get interrupted. If. for example. an interrupt were to
be acknowledged at priority 3 (Interval Timer 3). in the normal course of events the SOSOA CPU will disable all interrupts upon acknowledging any interrupt. Therefore the Interval Timer 3 interrupt service routine will deny any other interrupt request. whatever its priority. until the Interval Timer 3 service routine completes execution. If the Interval Timer
3 interrupt service routine were to immediately enable all interrupts. then any other·interrupt request would be
acknowledged. irrespective of priority.
If you want to ensure that only higher priority requests interrupt the Timer 3 service routine. then the Timer 3 service
routine must begin by outputting a mask to disable all lower level interrupts at the TMS 5501: then it must enable all
interrupts at the CPU. Here is the necessary instruction sequence:
MVI
EI
TMSS.07H
:OUTPUT MASK TO REGISTER S OF TMS 5501
:ENABLE INTERRUPTS
The mask output in this case has the value 07. since mask bits O. 1 and 2 only must be set to 1. enabling the highest
. ,
three interrupt priority levels.
4-74
Let us now look at the nonstandard features associated with TMS 5501 interrupt
handling logic. First of all. so long as there is an unacknowledged interrupt request. Status
register bit 5 is set to 1; next the RST instruction object code for the highest level interrupt
request is stored in TMS 5501 Register 2. This allows you to bypass normal interrupt processing logic and poll the TMS 5501 instead.
.
cw
~
ex:
o
Il.
ex:
o
CJ
~
en
w
~
o
U)
(3
U)
c(
TMS 5501
NONSTANDARD
FEATURES
In order to bypass interrupt logic. simply disconnect the TMS 5501 INT output from the 8080A INT input. You can still
identify interrupt requests occurring within the TMS 5501 by reading the TMS 5501 Status register. If bit 5 of the
Status register is 1. then one or more interrupt requests are active within the TMS 5501. In order to determine which is
the highest level active interrupt request. read the contents of TMS 5501 memory location 2. The RST instruction object code corresponding to the highest priority interrupt request will have been assembled in this location. Bits 3. 4 and
5 of the RST instruction object code identify the priority level. Thus you can determine which of the eight priority levels
was the highest active interrupt request. Here is a typical polling sequence:
;ASSUME THAT THE TMS 5501 ADDRESS SPACE CONSISTS OF 16 MEMORY
;LOCATIONS FROM 8000 THROUGH 800F. TMS5 IS THE SYMBOL ASSIGNED
:TO THE BASE ADDRESS
TMS5
EOU
8000H
all
w
Z
ex:
o
aI
U)
o
~
c(
c
c(
;TEST STATUS REGISTER FOR INTERRUPT PENDING
LOA
TMS5+3
;LOAD STATUS TO ACCUMULATOR
ANI
20H
;ISOLATE BIT 5
TMS5+2
;IF NOT ZERO. AN INTERRUPT HAS BEEN
JNZ
;REOUESTED
@
It is worth spending a minute looking at the three-instruction sequence illustrated above. The TMS 5501 Status register
contents are loaded into the Accumulator by the LOA instruction. The next instruction isolates bit 5. If bit 5 is 1. then
an interrupt has been requested. and the next instruction. a JNZ. branches program execution to a memory location
within the TMS 5501 itself. Will that work? Indeed. it will. The label TMS5+2 addresses TMS 5501 Register 2. which
contains an RST instruction's object code; this is the object code which would have been output in response to a normal interrupt acknowledge. What the JNZ instruction does is cause this RST instruction's object code to be executed
next; and that is precisely the logic sequence which a normal interrupt response would have implemented.
Notice that the very simple method we have illustrated for polling on status only works if the TMS 5501 can be addressed as memory locations rather than I/O ports.
TMS 5501 PARALLEL I/O OPERATIONS
It is very easy to handle simple parallel I/O. without handshaking, using the TMS 5501. This is equivalent to 8255
Mode 0 operation. TMS 5501 address 1 accesses the parallel 8-bit input port. while address 7 accesses a parallel 8-bit
output port (see Table 4-7). Assuming that the TMS 5501 is addressed as memory. input and output operations are
handled using any memory reference instructions.
A very limited amount of parallel I/O handshaking is available. The SENS interrupt input signal can be used by externallogic either to indicate that it has read output data. or to indicate that it has transmitted input data .. However. the
TMS 5501 device itself has no control~als which can be used to prompt external logic; that is to say. the TMS 5501
has no signal equivalent to the 8255 OBF control. When comparing the parallel I/O capabilities of the TMS 5501 with
the 8255. therefore. we conclude that 8255 Mode 0 operations can be duplicated without problems. but neither Mode
1 nor Mode 2 parallel I/O operations with handshaking can be duplicated. Only a primitive level of parallel I/O with
handshaking exists within the TMS 5501 and even this exists at the expense of external interrupt logic.
TMS 5501 SERIAL I/O OPERATION
A significant asynchronous, serial I/O capability is provided by the TMS 5501. Synchronous serial I/O is not supported.
There are very significant differences between the implementation of asynchronous serial I/O by the TMS
5501. as compared to the 8251 USART.
The TMS 5501 has separate serial transmit and receive pins (XMT and RCV). but it has no accompanying handshaking
control signals; instead 5th and 6th priority interrupts identify Receiver Buffer full and Transmit Buffer full. respectively. Bits 2. 3. 6 and 7 of the Status register (addressable location 3) identify the condition of a serial receive data
stream.
4-75
When using the TMS 5501. you have to continuously read in the contents of the Status register and test the condition
of appropriate status bits in order to implement standard serial receive logic: however. in the end you can implement
the same serial receive logic as is provided automatically by the 8251 USART. Here is the relationship between the
TMS 5501 and the 8251 USART controls:
8251 USART
TxRDY
TxE
TxC
RxRDY
RxC
SYNDET
TMS 5501 EQUIVALENT
Status register bit 4
None
Baud Rate register
Status register bit 3
Baud Rate register
None
Probably the most significant difference between TMS 5501 and 8251 USART control is the fact that TMS 5501 baud
rate is programmed by outputting an appropriate Control code. while it is clocked by rate signals input to the 8251
USART. The TMS 5501 advantage is that the TMS 5501 does not need external baud rate clock generation logic:
however there must be a very precise synchronization between the TMS 5501 and whatever external logic it is communicating with. Minor timing differences are no problem when using an 8251 USART since a clock signal can accompany the serial data stream. Minor timing differences can be intolerable when using the TMS 5501: a small difference
between TMS 5501 baud rate and external clock signals can generate very significant errors.
TMS 5501 INTERVAL TIMERS
The TMS 5501 has five programmable Interval Timers. Each timer can be loaded with an initial count ranging
from 01 (lowest) through FF16 (highest). Each Timer will decrement one count every 64 microseconds. As soon
as a programmable timer counts out to zero, it requests an interrupt. In our discussion of TMS 5501 interrupt logic.
we have defined the priority levels assigned to the various Interval Timers. Notice that Interval Timer priorities have
been spread across the range of priority levels. By using Interval Timer 1 or 2. you can be sure of precise time intervals.
since an interrupt request will be acknowledged with little or no delay. Timers 4 and 5. being the lowest priority. can be
used to generate less precise time intervals. It is conceivable that interrupt requests originating at these two timers
might have to wait a significant amount of time before being serviced - if there is any degree of interrupt traffic within
the microcomputer system.
Loading a 0 value into an Interval Timer causes an immediate interrupt request.
When a nonzero value is loaded into an Interval Timer. it starts to count down immediately. If a new value is loaded into
an Interval Timer while it is halfway through counting out. then the new value will be accepted: it will override the previous value and subsequently will be decremented. Therefore the Interval Timers are retriggerable.
Once an Interval Timer counts out. it halts.
4-76
DATA SHEETS
This section contains specific electrical and timing data for the following devices:
c
w
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o
D.
a:
• 8080A CPU
• 8224 Clock Device
• 8228 System Controller
·8259 PIC
• TMS 5501 I/O Controller
a:
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4-D1
BOBOA/BOBOA-1/BOBOA-2
ABSOLUTE MAXIMUM RATINGS·
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Temperature Under Bias . • . . . . . . . • . • O°C to +70° C
Storage Temperature ..•...•..•.•. -65°C to +150°C
All Input or Output Voltages
With Respect to VeB ....•..•... -0.3V to +20V
Vce , VOO and Vss With Respect to VBB
-0.3V to +20V
Power Dissipation .•..•••..•-..... ...•••. 1.5W
D.C. CHARACTERISTICS
= o°c
TA
to 70°C, VOO
Symbol
= +12V ± 5%, Vce = +5V ± 5%, VB B = -5V ± 5%, Vss = OV,
Typ.
Min.
Parameter
Unless Otherwise Note~.
Max.
Unit
Vss+0.8
V
Test Condition
VILC
Clock Input Low Voltage
VIHe
Clock Input High Voltage
9.0
Voo+l
V
VIL
Input Low Voltage
Vss-l
Vss+0.8
V
VIH
Input High Voltage
3.3
Vec+ 1
V
VOL
Output Low Voltage
VOH
Output High Voltage
100 (AV)
Avg. Power Supply Current (Voo)
40
70
mA
leC(AV)
Avg. Power Supply Current (Vce!
60
80
mA
IBB (AV)
Avg. Power Supply Current (VSB)
.01
1
mA
IlL
Input Leakage
±10
J.lA
Vss ~ VIN ~ Vce
ICL
Clock Leakage
±10
J.lA
Vss'~ VCLOCK ~ Voo
IOL(2]
Data Bus Leakage in Input Mode
-100
-2.0
J.lA
mA
Vss ~VIN ~Vss +0.8V
+10 .
-100
J.lA
IFL
Vss-l
0.45
V
Address and Data Bus Leakage
During HOLD
Symbol
Vce = VOO
} Op,,";oo
Tcy
= .48 J.lsec.
Vss +0.8V ~VIN ~Vcc
VAOOR/OATA
V AOOR/OATA
CAPACITANCE
TA = 25°C
} IOL = 1.9mA on all outputs,
IoH =-l50J.lA.
.
V
3.7
= Vee
= VSS + 0.45V
1.5
= Vss = OV, VBB = -5V
Parameter
...
Typ.
Max.
Unit
Ccf>
Clock Capacitance
17
25
pf
fc
CIN
I nput Capacitance
6
10
pf
Unmeasured Pins
COUT
Output Capacitance
10
20
pf
Returned to Vss
Test Condition
= 1 MHz
~
:J
c.>
~
t
iil
0.5
NOTES:
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When OBIN is high and VIN > VIH an internal active pull up will
be switched onto the Oata Bus.
3. A I supply (AT A = -0.45%1' c.
0
+25
+75
+50
AMBIENT TEMPERATURE (OC)
Figure 2. Typical Supply Current vs.
Temperature, Normallzed(JI
~:]----~
o
Vee
YIN
Figure 3. Data Bus Characteristic
During DBIN
Data sheets on pages 4-02 through 4-012 are reprinted by permission of Intel Corporation, Copyright 1978.
4-02
SOSOA/SOSOA-1/S0S0A-2
A.C. CHARACTERISTICS (8080A)
TA = o°c to lODC, VDD = +12V ± 5%, Vee = +5V ± 5%, VBB
= -5V
± 5%,
·2
Mu.
·1
Min.
·1
Min.
MIx.
Min.
·2
MIx.
Unll
0.48
2.0
0.32
2.0
0.38
2.0
"sec
50
0
25
0
50
nsec
Vss = OV, Unless Otherwise Noted
--'-'
PI,.mlllr
S,mbol
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Clock Period
TI.I Condition
Ir,l,
Clock Rise and Fall Time
0
oQ.
1",
"1 Pulse Width
60
50
60
nsec
o
u
t"2
"2 Pulse Wldlh
220
145
175
nsec
~
tDl
Delay "1 to "2
0
0
0
nsec
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w
tD2
De~ay "2 to "1
70
60
70
nsec
tD3
Delay "1 to "2 Leading Edges
60
60
70
g
IDA[21
A~dress
CI)
CI)
tDD[21
Data Output Delay From "2
toc[21
Signal Outpul Delay From "2 or ~ (SYNC, WR, WAIT, HLDA)
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DBIN Delay From "2
tDI[ll
Delay 'or Input Bus to Enter Input Mode
CI)
tDSl
Data Setup Time During "1 and DBIN
!ia:
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Output Delay From "2
150
175
nsec
220
180
200
nsec
120
25
nsec
200
110
140
25
25
130
tDF
tDF
10
30
120
nsec
140
nsec
tDF
nsec
}
CL"'OOpF
}
CL-50pF
nsec
20
:!:
ct
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WAVEFORMS
(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = B.OV
"0" = 1.0V; INPUTS "1" = 3.3V, "0" = O.BV; OUTPUTS "1" = 2.0V, "0" = O.BV.)
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1
-I toe
1-
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-
tOI
--1 -- --
J-
....., toHI-
. Pit"-r.-
-----4--
~
~ '0$14-
READY
~---
'f-tAW
I--too-
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-- -- ~--- ~-
_tOF-l
--- - -r"!."-.o!!,:(
-tow
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WAIT
-
HLDA
toc f--
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tRS toc-I
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HOLD
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I-to.:=r
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INT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
INTE
4-03
80S0A/8080A-1/8080A-2
A.C. CHARACTERISTICS (8080A)
oOe to 7oo e, VDD = +12V ± 5%, Vec = +5V ± 5%, VBB
TA =
= -5V
Plrlmetlr
Min.
Data Setup Time to "2 During DBIN
150
tDH (1 )
Data Holt time From "2 During DBIN
(1)
t1E (2)
INTE Output Delay From "2
tRS
RE~DY
SymbOl
tDS2
± 5%, Vss
= OV,
·1
Min.
MIx.
Mu.
·2
·2
Min.
MIX.
130
120
(1)
200
Unit
nsec
200
nsec
120
90
90
nsec
tHS
HOLD Se'up Time to "2
140
120
120
nsec
tiS
INT Setup Time During "2
120
100
100
nsec
tH
Hold Time From "2 (READY.Ir.H. HOLD)
0
0
0
tFD
Delay to Float During Hold (Address and Data Bus)
tAW2)
Address Stable Prior to WR
120
Te.t Condition
nsec
(1)
200
Setup Time During "2
·1
Unless Otherwise Noted
CL= 50 pF
nsec
120
120
nsec
1-
IS)
(5)
(5)
nsec
tDW 2)
OutP'!t Data Stable Prior 10 WR
(6)
(6)
(6)
nsec
tWD(2 )
Output Data Stable From WR
(7)
(7)
(7)
nsec
tWA (2 )
'Address Siable From WR
(7)
(7)
(7)
nsec
tHF(2 )
HLDAto Float Delay
IB)
[B)
[B)
nsec
twF (2)
WR to Float Delay
t AH (2)
Address Hold Time After DBIN During HLDA
.,
f\
(9)
(9)
(9)
nsec
-20
-20
-20
nsec
CL = 100 pF: Address. Data
CL = 50 pF: WR,HLDA,DBIN
1-
NOTES: (Parenthesis gives ·1. ·2 specifications. respectively)
1. Data input should be enabled with DB IN status. No bus conflict can then occur and data hold time is assured.
tDH = 50 ns or tDF. whichever is less.
2. Load Circuit .
+SV
'2
B080A
OUTPUT
A'5 Ao
3. ICY = tD3 + tr+2 + t+2 + t'+2 + t02 + tr+1 ~ ~80 ns (- 1:320 ns, - 2:3BO ns).
TYPICAL
~
OUTPUT DELAY VS.
~
CAPACITANCE
+20 .------.-----r-.--~--
0)'0 0
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>
syrJC:
~
0
....
OBIN
~
::>
..,
0
\/ill
·10
I
+10r.
REAllY
.l
CAPACITANCE Ipll
ICACTUAL - CSPEcl
WAIT
HOLD
~
-
HLDA
IN~
INTE
~
l,,,~
_Jt;-
toe ______
4. The following are relevant when interfacing the aOaOA to devices having VI H = 3.3V;
al Maximum output rise time from .av to 3.3V = lOOns @ CL = SPEC.
b) i)utput delay when measured to 3.0V • SPEC +60ns @ CL = SPEC.
c) If CL SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL
*
< CSPEC.
5. rAW = 2tCY - tD3 - tr+2 -140ns(-1:110ns. -2:130ns).
6. tow = ICY - tD3 - t r +2 - 170 ns (-1:150 ns, -: 2:170 ns).
If not HLDA. tWD = tWA = tD3 + tr2 +10ns. If HLDA. tWD = tWA = tWF.
tHF = tD3 + t"1>2 -SOns.
tWF = tD3 + tr2 -IOns
Data in must be stable for this period during DBIN ·T3. Both tDS1 and tDS2 must be satisfied.
Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
Hold signal must be stable for this period during T2 or TW when entering hold mode. and during T3. T 4, TS
and TWH when in hold mode. (External synchronization is not required.)
13: Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
recognized on the following instruction. (External synchronization is not required.)
14. This timing diagram shows timing relationships only: it does not represent any specific machine cycle.
7.
a.
9.
10.
11.
12.
4-04
8224
ABSOLUTE MAXIMUM RATINGS·
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·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
thoSe indicated in the operational sections of this specification is not implied. E~posure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias ............... O°C to 70°C
Storage Temparature .............. -65°C to 150°C
Supply Voltage. Vee ................ -0.5V to +7V
Supply Voltage. Voo .. : ........... -0.5V to +13.5V
Input Voltage ..................... -1.5V to +7V
Output Current ......... ; ............... 100inA
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D.C. CHARACTERISTICS
TA = O°C to 70°C; Vee = +5.0V ±5%; Voo = +12V ±5%.
Limits
Typ.
a:
c:a
Symbol
Max.
Units
o
IF
Input Current Loading
-.25
mA
VF = .45V
IA
Input Leakage Current
10
J1A
VA = 5.25V
Ve
Input Forward Clamp Voltage
1.0
V
Ie = -5mA
V 1L
Input "Low" Voltage
.8
V
Vee = 5.0V
VIH
Input "High" Voltage
2.6
2.0
V
Reset Input
All Other Inputs
VIWVIL
RESIN Input Hysteresis
.25
VOL
Output "Low" Voltage
o
Parameter
Min.
Test Conditions
CI)
~
«Q
«
@
VOH
Output "High" Voltage
4>" .4>2
READY. RESET
All Other Outputs
Ise (1 )
Output Short Circuit Current
(All Low Voltage Outputs Only)
Icc
100
V
Vee = 5.0V
.45
V
.45
V
(4)1.4>2). Ready, Reset, STSTB
IOL=2.5mA
All Other Outputs
iciL= 15mA
9.4
3.6
2.4
V
V
V
-60
mA
POI·'''· ~ ... pply Current
115
mA
Power Supply Current
12
mA
-10
Note: 1. Caution. 1 Pulse Width
2tcy _ 20ns
9
t4/2
cf>2 Pulse Width
5tcy _ 35ns
9
t01
cf>1 to cf>2 Delay
0
t02
cf>2 to cf>1 Delay
2tcy _ 14ns
9
t03
cf>1 to cf>2 Delay
2tcy
9
Max.
ns
CL = 20pF to 50pF
2tcy + 20ns
9
tA
cf>1 and cf>'j Rise Time
20
tF
cf>1 and cf>2 Fall Time'
20
t04/2
cf>2 to cf>2 (TTL. Delay
toss
-5
+15
cf>2 to STSTB Delay
6tcy _ 30ns
9
6tcy
9
tpw
STSTB Pulse Width
tcy _ 15ns
9
tOAS
RDYIN Setup Time to
Status Strobe
SOns _ 4tcy
9
tOAH
RDYIN Hold Time
After STSTB
tOA
RDYIN or RESIN to
cf>2 Delay
Test
Conditions
Units
ns
cf>2TTl,Cl=30
R1=300n
R2=600n
STSTB,Cl=15pF
R1 = 2K
R2 = 4K
4tcy
9
Ready & Reset
Cl=10pF
R1=2K
R2=4K
4tcy _ 25ns
9
tcy
9
tCLK
ClK Period
f max
Maximum Oscillating
Frequency
27
MHz
Cin
Input Capacitance
8
pF
Vcc=+5.0V
Voo=+12V
VSIAs=2.5V
f=.1 MHz
Vee
TEST
CIRCUIT
R,
INPUT
CL
~ND
4-06
Rz
GNO
8224
WAVEFORMS
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I-----~----~
1------102----1
a:
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(/)
(/)
SYNC
(FROM 8080A)
I
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~--_-IORH------
(/)
o
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RDYINOR RESIN
c<
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@
""\1,-----------"""'\.1, - - - - - - - - -
-------------------
- - - - - - - - - - - - - - - - - - - '\j:------+-----------------
READY OUT
~tDR
RESET OUT
VOLTAGE MEASUREMENT POINTS: ':>1.':>2 Logic "0" = 1.0V. Logic "1" = B.OV. All other signals measured at 1.5V.
EXAMPLE:
A.C. CHARACTERISTICS (For tCY == 488.28 ns)
TA = O°C to 70°C; VOO = +qV ±5%; Voo = +12V ±5%.
Symbol
Limits
Typ.
Units
Test Conditions
t.p1
<1>1
Pulse Width
89
ns
tCy=488.28ns
t4>2
<1>2
Pulse Width
236
ns
t01
Delay
0
ns
t02
Delay <1>2 to
Parameter
<1>1
to <1>2
<1>1
Min.
Max.
109
129
ns
t03
Delay
tr
Output Rise Time
20
ns
tf
Output Fall Time
20
ns
toss
<1>2
to STSTB Delay
296
326
ns
to':>2
tpw
<1>2
to
-5
+15
ns
Status Strobe Pulse Width
tORS
RDYIN SetupTimeto STSTB
tORH
tOR
fMAX
Oscillator Frequency
<1>1
<1>2
to <1>2 Leading Edges
(TTL) Delay
Loaded to
C L = 20 to 50pF
r- <1>1 & <1>2
ns
95
40
ns
-167
ns
RDYIN Hold Time after STSTB
217
ns
READY or RESET
to 4>2 Delay
192
ns
18.432
4-07
MHz
-
Ready & Reset Loaded
to 2mA/10pF
All measurements
referenced to 1.5V
unless specified
otherwise.
8228/8238
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ _O°C to 70°C
Storage Temperature .............. -65°C to 150°C
Supply Voltage, Vce ................ -0.5V to +7V
Input Voltage ..................... -1.5V to +7V
Output Current ......................... 100mA
D.C. CHARACTERISTICS
Symbol
TA = DoC to 70°C; Vce = 5V ±5%.
Parameter
Vi;
Input Clamp Voltage, All Inputs
IF
Input Load Current,
STSTB
-.
Limits
Min. Typ.(1) Max. .75
02& 06
00,01,0.i;b
& 07
s,
OBO·OB7
All Other Inputs
YTH
I~c
POW~~,S~bply Current
VbL
Output Low Voltage,
0.8
140
00.0 7
All Other Outputs
00.0 7
3.6
All Other Outputs
2.4
los
Short Circuit Current, All Outputs
101off)
Off State Output Current,
All Control Outputs
Note1:
500
pA
Vcc':'5.25V
750
pA
VF=0.45V
250
pA
100
pA
Vcc=5.25V
20
pA
VR =5.25V
100
pA
2.0
V
190
mA
.45
V
Vee=4.75V; 10L =2mA
.45
V
10L = 10mA
Vee=5V
Vee=5.25V
Output High Voltage,
VOH
liNT
Vee=4.75V; le==-5mA
250
Input Leakage Current
STSTB
Input_1~~eshold Voltage, All Inputs
Test Conditions
pA
All Other Inputs
IR
Unit
V
-1.0
3.8
15
4-08
10H = -1i'nA
Vce=5V -
100
pA
Vee=5.25V; VO=5.25
-100
pA
5
Typical values are for T A = 250 e and nominal supply voltages.
Vee=4.75V; IOH=-10pA
V
mA
90
I NTA Current
V
mA
Vo=.45V
-(See _Figure below)
8228/8238
WAVEFORMS
°a----J
SnT~AT..~~5T~RN08DE ------=j~~.------------~
\J
V
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.:
HLDA
'DC
u)
i -+
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iNTA.iOR.MEMR-------""i\
~
S~STEM BUS DURING ~EAD -
-
-
-
-
-
-
-
t- - - -
,.-r.------------I
(
.1, /'.. , - . . . . ; , : : . . . . - - - - - - - - - - - - 'HO
! . ! _ 'os :1-
DURING HLDA
g
.... 'RR
'OH ..,
~
t ~ - - - - - - - - - - - --
--- -- - - -t---I-l''Ao
I=~- ------- -----1- - - - - ~ - - - - - - - - - - - - - i, 'RE~ 1-
en
en
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ct
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I0IO IUS DURING READ· -
a::
oa:I
WR
o
IOWORMEMW
en
-
-
-
-
-
-
~
ct
C
ct
@
\....._ _-----1
SYSTEM BUS OUTPUTS -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
<1
>- - - - - - - - - - - - - -
I
I
VOLTAGE MEASUREMENT POINTS: 00.07 (when outputs) Logic "0"
at 1.SV.
-ADVANCED IOW/MEMW FOR 8238 ONLY.
A.C. CHARACTERISTICS
TA
=
0.8V, Logic "1"
=
3.0V. All other signals measured
= O°C to 70"C; Vee = 5V ±5%.
Limits
Symbol
Parameter·
tpw
Width of Status Strobe
tss
tSH
Min.
Max.
Units
22
ns
Setup Time, Status Inputs 00.07
8
ns
Hold Time, Status Inputs 00.07
5
toc
Delay from STSTB to any Control Signal
20
tRR
Condition
ns
60
ns
CL = l00pF
Delay from DBIN to Control Outputs
30
ns
CL = 100pF
tRE
Delay from DBIN to Enable/Disable 8080 Bus
45
ns
CL = 25pF
tRO
Delay from System Bus to 8080 Bus during Read
30
ns
CL:: 25pF
45
ns
CL = 100pF
30
ns
CL = 100pF
ns
CL = 100pF
30
ns
CL - 100pF
25
ns
twR
Delay from WR to Control Outputs
tWE
Delay to Enable System Bus DBo·DB7 after STSTB
two
Delay from 8080 Bus 00.07 to System Bus
DBo·DB7 during Write
5
5
40
tE
Delay from System Bus Enable to System Bus DBo·DB7
tHO
HLDA to Read Status Outputs
tos
Setup Time, System Bus Inputs to HLDA
10
ns
tOH
Hold Time, System Bus Inputs to HLDA
20
ns
4-09
CL = 100pF
8228/8238 AND 8259/8259-5
CAPACITANCE
This parameter is periodically sampled and not 100% tested.
Limits
Parameter
Symbol
Min.
Typ.ll1
Max.
Unit
CIN
I nput Capacitance
8
12
pF
GoUT
Output Capacitance
Control Signals
7
15
pF
I/O
I/O Capacitance
(0 or DB)
8
+12V
lKH ·10%
pF
15
8228
Test Conditions: NS: VSIAS = 2.5V, Vee=5.0V, TA = 25°C, f = 1MHz.
Note 2: For 00-07: Rl = 4Kn. R2 = ""n.
eL = 2SpF. For all other outputs:
Rl = soon. R2 = 1 Kn. eL = 100pF.
23
INTA
D---------l
Figure 1. INTA Test Circuit (for RST 7)
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ........ 0° C to 70° C
Storage Temperature .............. -65°Cto+150°C
Voltage On Any Pin
With Respect to Ground .............. -0.5 V to +7 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 Watt
'COMMENT:
Stresses above those listed under '"Absolute Maximum Ratings'"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied.
D.C. CHARACTERISTICS
(TA = o°c to 70°C; Vee = 5V ±S%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-.5
.8
V
VIH
Input High Voltage
2.0
Vee+. 5V
V
VOL
Output Low Voltage
.45
VOH
Output High Voltage
VOH-INT
Interrupt Output High Voltage
V
IOL = 2 mA
2.4
V
IOH = -400 /1A
2.4
V
IOH = -400 /1A
3.5
V
Input Leakage Current
.IILIIRO_7)
IlL
TEST CONDITIONS
for IRQ..7
Input Leakage Current
for Other Inputs
IOH = -50 /1A
-300
/1A
VIN = OV
10
/1A
VIN = Vee
10
/1A
VIN = Vee to OV
VOUT = 0.45V to Vee
IOFL
Output Float Leakage
±10
/1A
lee
Vee Supply Current
100
mA
CAPACITANCE
TA = 25°C; Vee = GND = ov
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
CIN
Input Capacitance
10
pF
fc = 1 MHz
CliO
I/O Capacitance
20
pF
Unmeasured pins returned to Vss
TYP.
4-010
TEST CONDITIONS
8259/8259-5
A.C. CHARACTERISTICS
(TA = o°c to 70°C; VCC = +5V ±5%, GND = OV)
Bus Parameters
cw
~
a:
oQ.
Read:
8259
PARAMETER
SYMBOL
a:
MIN.
o(J
tAR
CS/Ao Stable Before RD or INTA
~
tRA
CS/Ao Stable After RD or INTA
ui
w
~R
RD Pulse Width
~
g
tRO
Data Valid From RD/INTAI1
tOF
Data Float After RD/INTA
U)
U)
8259·5
MAX.
MIN.
50
MAX.
UNIT
50
ns
5
30
ns
420
300
ns
300
J
20
200
20
MAX.
MIN.
200
ns
100
ns
MAX.
UNIT
<
oil
w
2
Write:
a:
o
m
8259
U)
o
PARAMETER
SYMBOL
:!:
<
c
<
@
MIN.
8259·5
tAW
Ao Stable Before WR
50
50
ns
tWA
Ao Stable After WR
20
30
ns
tww
WR Pulse Width
400
300
ns
tow
Data Valid to WR (T. E.)
300
250
ns
two
Data Valid After WR
40
30
ns
Other Timings:
8259
PARAMETER
SYMBOL
Note 1:
MIN.
8259·5
MAX.
MIN.
MAX.
UNIT
tlW
Width of Interrupt Request Pulse
100
100
tiNT
INT t After IR t
400
350
ns
tiC
Cascade Line Stable After INTA t
400
400
ns
8259: CL = 1OOpF, 8259-5: CL = 150pF.
Input Waveforms for A.C. Tests
2.4
---""X::: >TEST~INTS <:::x. ___
0.45 _ _ _.I
-
4-011
ns
8259/8259-5
WAVEFORMS
Read Timing
Write Timing
ADDRESS BUS
ADDRESS BUS
----~'~----------------~--------~-~-------------
----~,~----~---------+--------~.'--------------
DATA BUS
flOWA
Other Timing
,: --);J f~-----------""""\\,-________
INTA
DB
Note: Interrupt Request must remain "H IGH" (at least) until leading edge of first INT A.
Read Status/Poll Mode
, ____...J!
~----------~
~-------------------------------
~'--+j---'I
:vzzzod
DAT. .
DOW,
rzz;zmzz~
4-012
DATA
I
womz;;mu
TMS 5501
TMS 5501 ELECTRICAL AND MECHANICAL SPECI FICATIONS
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE·AIR TEMPERATURE RANGE
(UNLESS OTHERWISE NOTED)Q
w
~
IX:
oD..
IX:
o
CJ
~
en
w
-0.3 V to 20 V
-0.3 V to 20 V
-0.3 V to 20 V
-0.3 V to 20 V
. . . . 1.1 W
O°C to 70°C
-65°C to 150°C
Supply voltage, V CC (see Note 1)
Supply voltage, VDD (see Note 1
Supply voltage, VSS (see Note 1)
All input and output voltages (see Note 1)
Continuous power dissipation
Operating free·air temperature range
Storage temperature range
~
g
CI)
CI)
ct
~
w
Z
·Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute·maximum·rated conditions for extended periods may affect
. device reliability.
NOTE 1: Under absolute maximum ratings voltage values are with respect to the normaliy most negative supply voltage, V BB (substrate).
Throughout the remainder of this data sheet, voltage values are with respect to VSS unless otherwise noted.
IX:
o
CD
CI)
o
RECOMMENDED OPERATING CONDITIONS
:!:
ct
Q
ct
NOM
MAX
Supply voltage, VSS
-4.75
-5
-5.25
V
@
Supply voltage, Vee
4.75
5
5.25
V
Supply voltage, VOO
11.4
12
12.6
V
MIN
Supply Voltage, VSS
V
0
High·level input voltage, VIH (all inputs except clocks)
3.3
Vee+ 1
High·level clock input voltage, VIH(2)
Delay time, clock 1 low to clock 2
tc(q,)
Clock cycle time
tr(q,)
ns
ns
300
ns
0
ns
td(q,2-cPl)
Delay time, clock 2 to clock 1
70
ns
td(q,l H-2)
Delay time, clock 1 high to clock 2 (time between leading edges)
80
ns
tsu(ad)
Address setup time
SO
ns
tsu(CE)
Chip-enable setup time
50
ns
tsu(da)
Data setup time
50
ns
tsu(sync)
Sync setup time
50
ns
tsu(XI)
External input setup time
50
ns
th(ad)
Address hold time
0
ns
th(CE)
Chip-enable hold time
10
ns
thIda)
Data hold time
10
ns
th(sync)
Sync hold time
10
ns
th(XI)
External input hold time
40
ns
tw(sens H)
Pulse width, sensor input high
SOD
ns
Ll
Pulse width, sensor input low
500
tw(sens
td(sens-intl
Delay time, sensor to interrupt (time between leading edges)
td(rst-intl
Delay time, RST instruction to interrupt (time between trailing edges)
4-D14
ns
2000
ns
500
ns
TMS 5501
SWITCHING CHARACTERISTICS OVER FULL RANGE OF RECOMMENDED
OPERATING CONDITIONS (SEE FIGURES 6 AND 7)
cw
.....
MIN
TEST CONDITIONS
PARAMETER
tpzx
Data bus output enable time
tpxz
Data bus output disable time to high-impedance state
tpD
External data output propagation delay time from q,2
MAX UNIT
CL'" 100 pF,
RL'" 1.3 kn
200
ns
180
ns
200
ns
<
a:
o11.
a:
o
3V
CJ
~
en
w
~
gen
TMS 5501
OUTPUT
en
<
-I
J
L ';'1.3kn
CL'" lOOpF
all
w
Z
a:
CL includes probe and Jig capacitance
In
LOAD CIRCUIT
o
en
o
~
<
c
<
@
...
.I--------tc(q,}-------~.I
~ ...... tf(q,}
I
I
I I
I.1
tdq,l--I 14"'I I.1 td(l/>l L-4>21
t w(q,ll
1/>1
-----.-r~1
~
t ( 1 1_.'
w 1/>2
I
I
1
!_I_'___Ip-_ _...-,~
-I
1/>2\_ _td_(_1/>1_H_-4>_2_1...
.:
CHIP
th(CEI~
I
tsu(dal
01
02-07
I.
W
INPUTS
I
1
I·
1
I
I
th(dal~1
I
I
:~
I
W< I
~
Hi-Z
I21TTl)
RDYIN
mm
-0B3
-0B4
'+12V
'+5V
-oae
-OBS
'GND
-087
'+ sv
_____.,.2.::-8_4-4
'GNO - - - " " ' : - - ' i
-Signals no longer needed or not present.
'BUSEN - - - - - -....~L
New 8085A signals: RST 5.5. RST 6.5. RST 7.5. TRAP. RESET OUT. SID. SOD
Shaded signals represent 8085A equivalents of 8080A.
24
SYSTEM
COHTAOl
____P ....------
Figure 5-3. A Comparison of SOS5A and SOSOA/S224/S22S Signal Interface
5-6
A COMPARISON OF SOS6A AND SOSOA SIGNALS
c
w
~
a:
oa.
No attempt has been made to maintain any kind of pin compatibility between the SOSSA and the SOSOA.
Nevertheless, as illustrated in Figure S-3, it is relatively simple to derive equivalent system busses when using
the SOSSA or SOSOA. But look at Figure 5-3 with an element of caution. Many logical combinations of 8085A signals
are shown reproducing 8080A signals: in reality you will never generate such logical combinations - a point which
will become clear as the chapter proceeds. The purpose of Figure S-3 is to illustrate the equivalence of the system
busses generated by the SOSSA and the SOSOA without indicating that creation of equivalent busses is desirable.
a:
o
The 8080A signals which are shown as having direct 8085A equivalents are either obvious. or will become so after you
.
have read this chapter.
ui
w
What is more interesting is to. look at the 8080A Signals which no longer exist and the new 8085A signals which have
.
been added.
o
~
~
g
en
en
~
CI1J
w
Z
a:
o
III
en
o
~
~
c
~
@
Let us first look at the signals which have been dropped.
There are the surplus power supplies -5V and +12V. plus the secondary power supplies required by the 8224 Clock
Generator and the 8228 System Controller. Elimination of these signals is self-evident.
INTE is an 8080A signal that indicates to external logic when interrupts have or have not been enabled internally by the
8080A. This signal is not very useful. since external logic cannot use the information it provides. Apart from illuminating an appropriate indicator on a minicomputer-like control panel. the INTE signal of the 8080A serves little useful purpose.
WAIT is a signal which is output high by the 8080A while Wait states are being inserted within a machine cycle. There
is little that external logic can do with this signal. therefore its elimination in the 8085A carries no penalty.
BUS EN is a control input to the 8228 System Controller: it causes the 8228 to float its output signals. This signal is no
longer required in the 8085A since the Hold state floats all equivalent 8085A output signals - with the exception of
INT A. which does not need to be floated.
.
The 8224 Clock Generator outputs two synchronizing clock signals reproduced by ClK: OSC has no equivalent 8085A signal.
OSC and <1>2 (TTL). <1>2 (TTL) is approximately
The TANK input to the 8224 Clock Generator allows overtones of the external crystal to be used. No such signal exists
with the 8085A - which simply means that you have to use the primary frequency of any crystal connected across the
X 1 and X2 inputs.
Seven new signals have been added to the· SOSSA; it would have been possible to provide separate Data and
Address Busses by eliminating these seven signals, plus the ALE control signal whose presence is a direct consequence of having multiplexed Data and Address Busses. Intel has chosen to provide the seven new signals. paying the
price of having multiplexed Data and Address Busses.
Let us examine the new signals.
RST 5.5. RST 6.5. RST 7.5 and TRAP represent additional interrupt request inputs. TRAP is a non-maskable. high
. priority interrupt: the other three interrupt requests are supported by hardware-implemented vectoring.
RESET OUT is a Reset signal output by the 8085A: it may be used to reset support devices around the 8085A.
SID and SOD are control signals which provide a primitive serial input and output capability. These signals can also be
used as a general purpose status input (SID) and a control output (SOD).
SOS5A TIMING AND.INSTRUCTION EXECUTION
An SOSSA instruction's execution is timed by a sequence of machine cycles, each of which is divided into clock
periods.
An instruction is executed in from one to five machine cycles labeled MC 1. MC2. MC3.
MC4 and MC5.
5-7
SOSSA
MACHINE CYCLES
The first machine cycle of any instruction's execution will have either four or six clock periods.
Subsequent machine cycles will have three clock periods only. This may be iliustrated as follows:
MCl
SOS5A
CLOCK
PERIODS
i··/i\
TlIT2IT3IT41:t~IT~;
Tl
T2
T3
Tl T2 T3
Tl
T21 T 3
Tl T2
T3
Where MC is shaded, the entire machine cycle is optional. Where T iss haded, the clock period is
optional within its machine cycle.
8085A machine cycles and clock periods are very similar to those ofthe 8080A. You will find in Table 5-1 that the
number of clock periods required to execute 8085A instructions is equal to the number of clock periods required by the
8080A to execute the same instructions, or differs by one clock period only.
THE CLOCK SIGNALS
The SOS5A times its machine cycles using this simple clock signal:
MC3 .
MC2
MCl
ClK
Although the SOS5A has no SYNC signal to identify the start of a new machine cycle, you can use the SOS5A
ALE signal for the same purpose, This signal is output true during the first clock period of every machine cycle - at
which time the ADO - AD7 lines are outputting address data. In addition, you can identify the first (instruction fetch) cycle of any instruction's execution. SO and S1 will both be output high during an instruction fetch machine cycle. Clock
periods and machine cycles may therefore be identified as follows:
MCl
Tl
CLK
T2
MC2
T3
I
I
IO/M.\
I
SO
51
AS - A15
Low-order
ADO -AD7
ALE
T1 identified
MC 1 identified
by SO = 1
and 51 = 1
5-8 .
MEMORY ACCESS SEQUENCES
SO far as external logic is concerned, there is very little difference between an instruction fetch, a memory
read, and a memory write. We will therefore examine timing for these operations together.
C
LU
Mel
~
oQ.
Me2
a:
Tl
a:
o
CJ
~
en
elK
LU
~
g
U)
U)
«
101M
so
I
I
ell
LU
Z
a:
oen
51
U)
o
~
ct·
c
«
@
ADO- AD7
..
P~ high-order byt~
I
---~
Input
I
i~struction
Unspecified
I
II
I
~
::;L-=;.=~t:;r-....,
object code
~
______ I
~I
______JI
..~
~.------
ALE
,I
latch low- I
order
I
address
byte
~~--""""~'r~--""""~/~
Instruction Fetch
' Instruction
Decode
Figure 5-4. A Four Clock Period Instruction Fetch Machine Cycle'
Let us first consider an instruction fetch. Timing is illustrated in Figure 5-4 for a four clock period machine cycle,
and in Figure' 5-5 for a six clock period machine cycle.
'
The most important aspect of the instruction fetch machine cycle is the fact that it will have either four or six clock
periods. as against three for all subsequent machine cycles. The instruction fetch machine cycle must have at least four
clock periods. since the fourth clock period is needed to decode the instruction object code which has been fetched .. If
the instruction requires no subsequent memory accesses. then a fifth and sixth clock period may be needed to perform
the internal operation specified by the fetched instruction. If additional memory accesses will be required. then the
"
fourth clock pe'riod of the first machine cycle is sufficient.'
At the end of the first clock period. ADO - AD7 is floated transiently: then it is turned around to act as a Data Input Bus.
RD is pulsed low to strobe data onto the Data Bus.
The memory read must occur within three clock periods. Since this is an instruction fetch machine cycle. the CPU will
place the input in .the Instruction register. If external logic requires more time to respond to the memory access. then it
can generate additional Wait clock periods. We will describe the 8085A Wait state shortly.
During the fourth clock period of the instruction fetch machine cycle the instruction object code is interpreted by logic
of the 8085A CPU. Fifth and sixth clock periods will be required by some instructions to execute required internal
operations.
5-9
MCl
Tl
T2
T3
I
Mel
T4
T5
T2
Tl
Te
T3
T4
ClK I
I
I
I·
loiM ~
I~--~----~--~----~----~--------~----~--------~
so
~
I
SlV~~----+---~--~--~--~~--+---~--~--~
I
AS - A15
I Unspecified
ADO-AD7
PC high-order byte
I
I
I
~~.j~~~~__~~---;I;-~-;I----~!;!:~ (·--I-~~I---'J:
order byte
I
I
RD,
I
I
Latch loworder
address
byte
'-~----~'r~""~~ '-~--"~'r~""~~
Instruction Fetch
Instruction decode
and execute
Figure 5-5. A Six Clock Period Instruction Fetch Machine Cycle
During the fourth and subsequent clock periods, ADO - AD7 is floated and A8 - A 15 contains unspecified data.
The fact that ADO - AD7 and A8 - A 15 are unknown data during the fourth and subsequent
clock periods of an instruction fetch machine cycle must be taken into account when you
create memory select and I/O device select l o g i c . ·
In Figures 5-4 and 5-5 SO and S1 are both high. identifying this as an instruction fetch machine
cycle. 101M is low since the instruction object code is to be fetched from memory. An instruction
fetch is thus equivalent toa memory read.
8085A
DEVICE
SELECT
LOGIC
The address of the memory location to be accessed is fetched from the Program Counter (PC) and is output on
ADO - AD7 {low-order byte) and AS - A 15 (high-order byte). The low-order byte of this memory address is stable on
ADO~ AD7 during the first clock period. ALE is pulsed high at this time. The trailing edge of ALE is designed to act
as a strobe signal which external logic can use to latch the low-order address byte off ADO - AD7. If you are using
one of the 808SA support devices (the 8155, the 8156 the 8344 or the or the 8755A), then the low-order byte
5-10
of the memory address is latched off the ADO - AD7 lines for you. If you are using standard memory devices,
then you must demultiplex ADO - AD7. Any simple latched buffer can be used for this purpose; here is an example of the 8212 I/O port being used as a demultiplexer:
c
w
!;(
A8 - A 15
a:
0
Q.
a:
0
u
ALE
~
u)
...w
oCt
OS2
U
0
Address
Bus
OSl
8085A
CI)
CI)
8212
oCt
o!I
w
Z
010
a:
0
Ol
CI)
.•
••
017
000
MO
CLR
'
AO-A7
007
0
~
oCt
c
oCt
@
ST8
~----~--------------~~-----VCC
Data Bus
You might argue that there is no harm done if memory or 1/0 devices select themselves
when the System Bus is supposed to be idle; if neither the read nor write strobe is present,
data transfer between the System Bus and the selected device ~annot ?ccur.
Unfortunately, the problem is not so simple.
MULTIPLE
DEVICE
SELECTS
AND BUS
LOADING
It is possible for more than one memory or I/O device to consider itself sf3lecteq while the bus is
idle; this may occur under the following conditions:
'
1)
2)
If I/O devices are being selected as I/O ports. then the Address Bus lines may select an I/O port while
'
simultaneously selecting a memory device.
In microcomputer systems that use only a small portion of the total allowed memory - and most microcomputer
systems fall into this category - memory select logic need not decode unique memory addresses. Here is an example of two 4096-byte memory modules. each of which uses a single line of the Address Bus in order to create
device selects:
A15
A14
All
AO
"
Y>
~-
-.. t
.,
-
-.....
.
..-.
..
:
.
5-11
CSl
Address to Memory
fModule 1
Address to Memory
} Module 2
Memory module 1 will be assigned the address space 800016 through 8FFF16. Memory module 2 will be assigned the
address space 400016 through 4FFF16. In reality a variety of other addresses will select memory modules 1 or 2. Addresses C00016 through CFFF16 will select memory modules 1 and 2.
A correctly written program will keep either A 15 or A 14 low; but while the System Bus is floating. both address lines
could be high - in which case both memory modules will become selected.
While signal levels on the Address Bus are changing state. memory and I/O devices may be transiently selected. Transient selection may occur during T1 as well as during T4. T5 and T6. Transient selection may leave more than one
memory or I/O device simultaneously selected for shoq periods of time.
If more than one memory or 1/0 device is simultaneously selected, excessive loads may be placed on the
System Bus: At best. these excessive loads will cause devices connected to the' System Bus to temporarily malfunction: 'at worst. device failures may result.
It is very important to prevent devices from being spuriously selected.
If you use RPIVI devices with multiple chip select inputs, you can prevent transient memory
selection'~y 'connecting the SOS5A RD output to one of the select (or enable) inputs. This
will ensure that the device responds only when a valid address is on the System Bus: therefore
only one ROM device will be 'selected at a time. Refer to Volume III for information on memory
devices.
.
The simplest w~y of preventing memory and 1/0 device selection is to use 101M, RD and
WR as cqntributors to' device select logic:
ADO
PREVENTING
TRANSIENT
SELECTION
PREVENTING
SIMULTANEOUS
SELECTION'
OF 1/0 AND
MEMORY
A15
Memory
Address
Decode
L~ic
AD -----c;;a
"WR-----c:.
s
~______
Memory
Select
10iM-----------'
A~5
AS
I/O Device
Select
Decode
Logic
AD -----4~
'WR-----4"
I/O device
select
10/M - - - - 4 : 1
5-12
Timing for the memory select illustrated above may be illustrated as
I
I
Q
w
~
a:
oc..
elK
101M
en
w
RDorWR
~
T2
,
Memory
Select
~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~
I
I
I
\
I
\
I
a:
1/0 device select logic timing differs only in the level of 101M.
t/)
!O/M distinguishes between memory and 110 devices. When AD or WA is low. memory or 1/0
:E
device addresses must be valid. Thus the logic illustrated above will guarantee that spurious
memory and 1/0 device selects never occur.
oID
o
~
Q
~
@
L
'1
CI/:I
w
Z
i\
I
I
I-
t/)
t/)
~
I
a:
o
u
g
T1
foll~ws:
But there is a problem associated with the solution illustrated; memory and i/O devices do not receive a valid select signal until early in the second clock period. This is unfortunate. since valid addresses are available early in the first clock
period. Delaying memory select logic until the second clock period may require Wait states to be added between clock
periods 2 and 3 - and that unnecessarily slows down CPU operations. If e>secution speed is not a problem to you. then
the simple select logic illustrated above will do. If execution speed is a problem, then you must replace:
D
WR.
Ri5 ____________
.
~------------
in the simple select logic with alternative logic that may be defined as follows:
ALE
RoorWR
s
5-13
S
The required S output may be generated using two flip-flops as follows:
~-------------s
a
0 ....- -...
VCC----t J
ALE ---<1I>CK
74107
RESET---...lI("'...........
AD
WR
----til.""'"
>----------~
If your system contains an 8085. rather than an 8085A. the first S output after a Reset will
occur before the address.lines are valid. Since ALE is tristate in the 8085. a falling edge occurs
when Reset goes off: at this time the address lines may still be floating. One solution is to connect the first J input above to the Q output of the following D·flip-flop:
a
VCC----f 0
ALE·-----I::~K
t---tl~
7474
CLR·
RESET
The flip-flop above prevents S from going high until after the first rising edge of ALE.
5-14
SELECT
PROBLEM
WITH 8085
MCl
Q
w
~
a:
oIl.
a:
o
I
elK I
I
:
~
\'-_ _ _....;._ _..:..-_~~
I~----------------~----------------~------I------
~
w
~
g
en
so
I
Sl
en
ct
a!I
w
Z
I
~/~ ~
CJ
iii
Mel
Me2
I
,r----~------~----~----~----~I~·----~------~----~
I
AS - A15
PC high-order'byte
a:
o
III
en
o
ADO- AD7
~
ct
Q
ct
ALE
@
RDI
I
Latch low·
order
address
byte
I
I
Latch low.
order
memory
address
'-'. . . .EB. .~. . . .~~
~. . . .aa...._~~
b~~.e__. . . .,~~.rrmz~ag..~~
Instruction Fetch'
Memory Read
Figure 5-6. A Memory Read Machine Cycle Following an Instruction Fetch
Let us now consider a memory read operation; timing is illustrated i,n Figure 5-6. So far as ex8085
ternal logic is concerned. the only difference between a memory read and an instruction fetch is
MEMORY
the SO and S1 signal levels; they are both high for an instruction fetch. but SO is low during a
READ TIMING
memory read. Also. the instruction fetch has four or six clock periods. while the memory read has·
three; but the extra instruction fetch clock periods occur after the memory access is completed. Therefore. so far as external logic is concerned. the extra clock periods of the instruction fetch machine cycle are irrelevant.
5-15
MCl
ClK
I
Mel
MC2
Tl
I I I
I
I
I
10iM
~
I
50
~
\
I
I
I
51
I
~
I
I
Unspecified
I/O evice select code
AS - A15
ADO - AD7
ALE
AD
order
Read I/O
port address
address
byte
from either
half of
......_ _- - - . . . . . ~...- -_ _ _~~
Ad!reSS
........
V".
Instruction' Fetch
Figure 5-7. An I/O
~ead
Machine
Figure 5-7 illustrates I/O read timing. Only the
Figure 5-6.
Bus
/
v~---..",
.' lIO Read
Cy~le Followi~g
101M signal
an Instruction Fetch
level in Figure 5-7 differs from
Memory write timing, illustrated in Figure 5-8, is very similar to memory read timing. The
principal difference is that during a memory write WR is output low. whereas during a memory
read RD'is output low. Also. during a memory write operation S 1 is output low while SO is out-·
put high.
.
.
An I/O write operation is illustrated in Figure 5-9. As compared to Figure 5:8. 10/Mis high in
Figure 5-9 during the write machine cycle: there are no other timing differences.
5-16
8085 I/O
READ TIMING
8085
MEMORY
WRITE TIMING
8085.1/0
WRITE TIMING
MCl
MCl
MC2
Tl
Tl
Q
w
I-
~,
0
a.
II:
0
ClK
IO/M~
U
I
~
en
w
SO
l-
en
en
w
Z
I
I
\
Sl :/
1r--........
~--------------~I
I
e(
~
~
I
e(
g
I
I
AS - A15
Address high-order byte
II:
0
ID
en
0
ADO - AD7
~
e(
Q
e(
@
latch loworder
Latch loworder
address
memory
byte
..........
~~
address
byte
....~~,.......~~
-~~ ~~--
Instruction Fetch
Memory Write
Figure 5-8. A Memory Write Machine Cycle Following an Instruction Fetch
5-17
T2
T2
elK
Mel
Me2
Mel
I
I
10/M
~
I
so
~
I
Sl
~
I
\
I
Unspecified
PC high-order byte
AS - A 15
I/O device select code
ADO - AD7
ALE
Latch loworder
port address
address
byte
from either
half of Address Bus
~~--""""~~~--""""~~~~""--''r~--''''~~
Instruction Fetch
I/O Write
Figure 5-9. An I/O Write Machine Cycle Following an Instruction Fetch
BUS IDLE MACHINE CYCLES
During a Bus Idle machine cycle no control signals change state on the System Bus.
There are three types of Bus Idle machine cycles:
8085A
BUS IDLE
MACHINE
CYCLE
1)
An instruction fetch Bus Idle machine cycle. The 8085A CPU acknowledges an interrupt from
TRAP. RST 5.5. RST 6.5. and RST 7.5 by generating a Restart instruction internally. No external instruction fetch operations occur; however. logic internal to the CPU requires time to
create the instruction object code. Therefore a Bus Idle instruction fetch machine cycle is executed. Timing is illustrated in Figure 5-17.
2)
The instruction execute Bus Idle machine cycle. Only the DAD instruction uses this machine cycle. The DAD instruction adds the contents of two CPU registers to two other CPU registers. It takes six clock periods for logic internal to the 8085 CPU to complete these operations. The six clock periods are generated via two instruction execute Bus Idle- machine cycles. Timing is illustrated in Figure 5-10.
Figure 5-10 shows a difference in operations between The 8085A and the earlier version. the
ALE GENERATION
8085. During an instruction execute Bus Idle machine cylce, the 8085A does not generIN 8085 AND
8085A
ate a high pulse on ALE. The 8085, however, pulses ALE high during every T1 of every
machine cycle - including instruction execute Bus Idle machine cycles.
- - - - - - - -....
3)
The Halt Bus Idle machine cycle. Following execution of a Halt instruction an indeterminate number of Bus Idle
machine cycles are executed for the duration of the Halt condition. Timing is illustrated in Figure 5-14.
5-18
The condition of the 101M, S1 and S2 signals during a Bus Idle machine cycle varies with the type of Bus Idle
machine cycle. These three signals will conform to instruction fetch level during an instruction fetch Bus Idle machine
cycle. During an instruction execute Bus Idle machine cycle. Memory Read signal levels are maintained. but the RD
control signal is not pulse low.
During a Halt Bus Idle machine cycle. 50 and 51 are both low but
101M.
along with other tristate signals. is floated.
cw
~
0::
o
Q.
0::
MCl
o
MC3
MC2
o
~
Tl
ui
w
~
g
I
fI)
fI)
~
o1J
w
Z
101M
~
I~--~~----------~----~------------~-----------
,
0::
o
m
fI)
o
~
~
SO :/
I
51
c
I
~~--~~--~----~----~--~----~----~--~
I
~
@
I
CLK I
AS-A15
Unspecified
1 1~______pc_l_h_i9_h_-O_rd_e_r_~_yt_e______~I..__..I~____PC~h-i9-h-.o-rd-e-r~~~t-e----~I------~
PC low- I
.Input DAD instruction
I
I
PC low-
i
I
I
I
ADO - AD7
ALE
I
·1
Latch loworder
address
byte
*SOS5A does not generate ALE; only SOS5 generates ALE during MC2 and MC3 of DAD.
~~..........~~~........--~~~~"""~'r~"""~~
Instruction Fetch
Bus Idle
Figure 5-10. A Bus Idle Machine Cycle Following an Instruction Fetch During
Execution of a DAD Instruction
5-19
Mel
Mel
Me2
I
I
101M
~
::
I~--~--------~-----I--------~----~--~----~I----~
so~I
S1
:'
)
~~--------------~----~
I
,r----+-----~----~----~I----.~'~----~----~----.-----+-----~
II
I
I Unspecified
I
AS -A15
Address high-ord':!r byte
'11
I
r---+---In-p-u~t:-da-t-a--~:~--~~
i
'}----I,
.
ALE
I
I
order
address
byte
order
address
.... .......... ........
byte
'-~--------~~~--
Instruction Fetch
--,~ '-~
~~~
~~
Memory Read with Wait States
Figure 5-11. Wait States Occurring in a Memory Read Machine Cycle
THE WAIT STATE
The 8085A will insert Wait states between clock periods T2 and T3 in a manner that is closely analogous to the
8080A. Timing is illustrated in Figure 5-11. which shows Wait states being inserted in a memory read cycle; a
Wait state inserted in any other memory reference or I/O machine cycle would differ only in the levels of control
signals.
The 8085A samples the READY line during T2. If READY is low during T2. then a Wait clock period will follow T2. The
READY line is sampled in the middle of each Wait clock period; Wait clock periods continue to be inserted until READY
is sampled high. As soon as READY is sampled high. the next clock period will be a T3 clock period - and normal program execution continues. This sampling may be illustrated as follows:
elK
READY
5-20
Wait states are used in an 8085A system exactly as described for the 8080A in Chapter 4 - to give slow memories and
I/O devices more time in order to respond to an access. Thus the discussion of Wait states provided in Chapter 4 applies equally to the 8085A.
In Chapter 4 a pair of 7474 flip-flops are shown creating a low READY pulse that generates a single Wait state in a
memory read machine cycle. For the 8085A the following variation applies:
cw
~
a:
oQ.
a:
o
u
~
SI - - - - I
IO/M---a
ALE - - - - c : I I
I--~ 01
>----II~~lK
Q1
7474'
1----------.. . 02
ClK (8085A)
>--..... ~ClK7474
en
w
~
U
o
en
en
~
oil
w
Z
a:
o
III
·CLK is rising edge triggered
o
·ClEAR is low level active
en
READY
::E
~
c
~
The circuit will operate with the following timing:
@
TW
If the cycle is a memory read (S = 1. SO = 0) or an instruction fetch (S 1 = 1. SO = 1). 01 will go high at the falling edge
of ALE. This will cause flip-flop 2 to go on at the next falling edge of the 8085A.clock. thereby forcing READY low. The
Iowan READY will clear flip-flop 1. so that READY will return high on the next falling edge of the 8085A clock.
THE SID AND SOD SIGNALS
The 8085A has two instructions which handle single-bit data.
The RIM instruction inputs data from the SID pin to the high-order bit of the Accumulator. The SIM instruction
. outputs the high-order bit of the Accumulator to the SOD pin.
You may use the RIM and SIM instructions in order to implement a primitive serial 1/0 capability. A more useful application of these instructions is to read single signal status and to output single-signal controls.
5-21
When the RIM instruction is executed. the SID signal level is sampled on the rising edge of the clock signal during clock
period T3 of the instruction fetch machine cycle. The high-order bit of the Accumulator is modified while the clock signal is high during T1 of the next instruction fetch machine cycle. Timing may be illustrated as follows:
'MCl
Mel
ClK
SID
A. Bit 7
When an SIM instruction is executed. the actual change in SOD signal level does not occur until T2 of the next instruction fetch machine cycle; that is to say execution of the SIM instruction overlaps with the next instruction fetch.
This may be illustrated as follows:
Mel
Mel
Following an SIM instruction fetch. the high-order bit of the Accumulator is sampled while the clock is low during T2 of
the next instruction fetch machine cycle. During the same clock period. the SOD signal level is modified to reflect the
contents of the high-order Accumulator bit. This overlap is feasible since neither the SOD signal nor the Accumulator
contents are modified while an instruction is being fetched. Note that SOD must be enabled before it can be accessed
or changed; you use bit 6 of the Accumulator to enable SOD. as detailed later in this chapter when we describe the
8085A instruction set.
5-22
Figure 5-12 illustrates SID and SOD signal timing during execution of a RIM instruction followed by a SIM instruction.
MCl
cw
MCl
MC1'
~
a::
oa.
a::
o
CJ
ClK
enw
SOD
~
~
g
en
en
SID
ct
oil
w
2
a::
A REG (BIT 7)
o
III
en
AS - A15
:!!
ct
c
ADO- AD7
o
ct
PC high-order byte
PC high-order byte
PC high-order byte
@
ALE
latch PC lowarder byte
latch PC loworder byte
latch PC loworder byte
Figure 5-12. A RIM Instruction Followed by a SIM Instruction
5-23
~~-----HOlD------~~
MCl
MCl
ClK
HOLD
HlDA
I
I
101M
I
1\
I '
I
~··-I··-·i·-··--'
I
I~----------------~I
I
~~
l
I
I
51
~
I
A8 - A 15
J
~
PC
~igh.order brte
PC low-1
ADO - AD 15 lorder
bYte~.~
I
ALE
~----------~
I
h
I
I
I
I
object code
~
~
. . . . ., . . . . . . . . . . . . . . . . . . . .
I
~
~
I
I
I
8085
~
I
............... ....... a .......
I
.............
I
llr.
'---i
~·----""""hll....
I
~
~
h
I
I
I
I
I
I
I
I
I
I
•
I
,. .... .............. ............. .........."
\
. ._ _ _ _ _ _ _ _. .
I
~
I
I
~D I
} ••I I. . . . . . . . .
Input instructIOn I
rl. .~~~~~. .~. . . . . . .~...........J
I
I
I
~
....- -.....---....---"""':\......"...-~............~..............jp---.....--~
I
I
Figure 5-13. A Hold State Following a Sill9le Machine Cycle Instruction Execution
THE HOLD STATE
The 8080A and the 8085A both USf3 the Hold state as a means of transiently floating the System Bus. During a
Hold, external logic gains bus control, usually to perform direct memory access operations.
External logic requests a' Hold state by inputting HOLD high. The microprocessor responds by entering the Hold state
an~ outputting HLDA high. During ~'Hold §tate the microprocessor floats all tristate signals.
In the 8085, an earlier version of the SOS5A. ALE is a tristate signal and is floated during the
Hold sta~e. In the 8085A, how~ver, ALE is kept low during H o l d . '
Both the SOSOA and the SOS5A initiate the Hold state at the conclusion of an instruction's execution. But there are si'gnificant differences b~tween Hold. state initiation logic for the SOS5A as
againstihe ~OSOA.
..
.
HOLD STATE
IN 8085 AND
~085A
The sosbA initiates a Hold state following T3 for a Read machine cycle, or following T4 for a Write machine cycle. Timi'l9is illustrated in Figure~ 4-9 and 4-10.
5-24
The SOS5A in contrast. has a fixed, two machine cycle sequence for Hold state initiation; it may be illustrated as
follows:
.
Tn - 1
Tn +
Tn
Tn
+ 2
Tn + 3
Q
w
~
a:
oa.
a:
o
(J
~
enw
~
(3
o
CI)
CI)
500 J.l.SEC
I
I
__________~_::1
1
~
L
.......----------------------
,I
I
,~
I
~
I
RESET OUT
1
~
1
I
ALE .1
l-
,
A8 - A15
,
lI
ADO - AD7
I
_.J_
I
ADDRESS RESET
TO All ZEROES
1
...............
,
I
I
1 8085 I
82; n. .:.__. ,._-_-_..l_-_-_-_._-_~..,
I
I
I,...
I
" , __""-_-J
-1
ADDRESS RESET
TO All ZEROES
..•.............•.........
.1." 1......... .
LI
*8085 floats ALE during Reset; 8085A does not do this.
Figure 5-1S. Power On and RESET IN Timing for the 8085A
5-31
I
~
___
THE RESET OPERATION
You reset an SOS5A by inputting a low signal via RESET IN.
When power is first turned on, the RESET IN pulse must last at least 500 nanoseconds (3 full clock cycles); no
further requirements are imposed on the RESET IN signal. Logic internal to the SOS5A will synchronize the
RESET IN pulse with the internal clock. Timing for a Reset following a powerup is given in Figure 5-1S.
Notice that a RESET OUT signal is provided. You can use this signal to reset other devices in the SOS5A
microcomputer system .
. When the SOS5A is reset the following events occur:
1)
2)
3)
4)
5)
The Program Counter is cleared; thus the first instruction executed following a reset must have its object code
stored in memory location O.
The Instruction register is cleared.
Interrupts are disabled.
The RST 7.5. RST 6.5 and RST 5.5 interrupts are masked out and thus disabled.
All tristate bus lines are floated. In the earlier 8085. ALE is tristate and thus floats during Reset. In the 8085A. ALE
is not tristate.
Table 5-1. A Summary of 8085A Instruction Object Codes and Execution Cycles
CLOCK PERIODS
INSTRUCTION
OBJECT CODE
8080A
ACI
DATA
AOC
REG
ADC
M
ADD
REG
ADD
M
ADI
DATA
ANA
ANA
REG
M
ANI
DATA
CALL
LABEL
CC
LABEL
CM
LABEL
yy
CE
8085A
BYTES
8085A
MACHINE CYCLES
2
7
7
13
l000lXXX
1
4
4
1
8E
1
7
7
l0000XXX
1
4
4
1.3
1
86
yy
C6
10100XXX
A6
E6
yy
ppqq
DC ppqq
FC ppqq
CD
1
7
7
13
2
7
7
13
1
1
4
4
7
1
13
2
7
7
7
I(l/;l,~ii
. . .• .• . • . . (• .
3
3
13
~.f, ~ ~
13i~~~~
h>,,:;;
..,'.•....••..• ,.;;.~.. c.:... . ....
....
CMA
2F
3
1
4
4
1
CMC
CMP
1
1
4
REG
3F
10111XXX
4
4
1
1
BE
1
7
7
13
ppqq
C4 ppqq
F4 ppqq
EC ppqq
3
CMP
M
CNC
LABEL
CNZ
LABEL
CP
LABEL
CPE
LABEL
CPI
DATA
CPO
LABEL
CZ
04
FE
YY
3
3
3
'2
4
'''.~!
j5
.f
I.··· I
I}
•••••••
. . /i;
7
7
13
3SS(
....
3
LABEL
ppqq
CC ppqq
27
1
4
4
1
DAD
RP
00XX100l
1
REG
OOXXX10l
1
10
4
177
OCR
10
5
OCR
M
35
1
10
10
135
DCX
01
RP
OOXX10ll
1
1
5
4
6
4
2
F3
EI
FB
1
4
4
1
HLT
76
1
4
4
1
2
10
10
134
10
10
135
E4
DAA
IN
PORT
INR
REG
DB
YY
OOXXX100
...
3
1
1
1
INR
M
34
1
INX
RP
OOXXOOll
1
JC
LABEL
DA
10
LABEL
FA
3
10
JMP
LABEL
3
10
10
JNC
LABEL
3
13.133
3
10
10
7/10
JNZ
JP
7/10
13. 1 33
LABEL
ppqq
ppqq
C3 ppqq
02 ppqq
C2 ppqq
F2 ppqq
3
JM
3
10
7/10
13. 1 33
LABEL
5-32
1
7/10
133
13. 133
133
Table 5-1. A Summary of 8085A Instruction Object Codes and Execution Cycles
(Continued)
, CLOCK PERIODS
INSTRUCTION
OBJECT CODE
7/10.
13'.133
10
7/10
13. 133
10
7/10
13
13
i
7
13
16
10
16
10
13333
LABEL
c(
a:
JZ
LABEL
0
LOA
ADDR
ppqq
ppqq
CA ppqq
3A ppqq
a:
LDAX
RP
OOOX10l0
(J
LHLD
LXI
ADDR
RP.DATAI6
2A ppqq
OOXXOOOI
0
SOSSA
MACHINE CYCLES
10
LABEl
JPO
!:
SOSSA
E2
JPE
t-
D.
8080A
EA
C
w
BYTES
13.133
333
133
YYYY
u)
w
MOV
REG.REG
c(
MOV
M.REG
MOV
REG.M
01dddl10
en
en
MVI
REG.DATA
OOdddl10
MVI
M.DATA
t-
g
01dddsss
01110sss
YY
c(
oll
36
ORA
REG
0
ORA
M
en
ORI
OUT,
DATA
F6
0
PORT
03
~
PCHL
C
POP
PUSH
a:
a:J
c(
c(
@
yy
00
NOP
w
Z
10110XXX
B6
yy
yy
E9 '
RP
RP
llXXOOOl
l1XX0101
17
RAL
IF
F8
RNC
DO
RNZ
CO
RP
FO
RPE
ES
RPO
EO
RCC
Rsr
N'
OF
l1XXXll1
SBB
REG
l0011XXX
SBB
M
STA
ADDR
32
ppqq
13
13
1335
STAX
RP
OOOX0010
7
7
15
C8
RZ
9E
SUB
REG
SUB
M
SUI
XCHG
DATA
XRA
REG
XRA
M
XRI
ppqq
YYYY
X
ddd
sss
4
l0010XXX
96
13
.1
06 yy
7
EB
4
4
10101XXX
4
4
DATA
XTHL
YY
4
37
STC
AE
13
1
13
EE yy
E3
Machine cycle types:
represents four hexadecimal digit memory address
represents two hexadecimal data digits
represents four hexadecimal data digits
1 - Four clock period instruction fetch (Figure 5-41
2 - Six clock period instruction fetch (Figure 5-51
3 - Memory read (Figure 5-61
4 -lio read (Figure 5-71
5 - Memory write (Figure 5-81
6 - I/O write (Figure 5-91
7 - Bus idle (Figure 5-101
represents an optional binary digit
represents optional binary digits identifying a destination register
represents optional binary digits identifying a l;Ource register
5-33
THE SOS5A INSTRUCTION SET
There are just three differences between the SOS5A and the SOSOA instruction sets:
1)
2)
3)
The 8085A has two additional instructions - RIM and SIM.
The number of clock periods required to execute instructions differs in some cases; Table 5-1 summarizes these
differences.
Following a Halt instruction's execution, the 8085A floats tristate bus lines in the ensuing Halt state; the 8080A
does not.
Because the SOS5A and SOSOA instruction sets are so similar, the same benchmark program applies to both
microprocessors. Refer to Chapter 4 for a discussion of this benchmark program.
Refer to Table 4·4 for a summary of the SOS5A instruction set. The only two SOS5A instructions not present in
Table 4·4 are the RIM and SIM instructions.
When the RIM instruction is executed, the following data is loaded into the Accumulator:
7 6 5 <4 3 2 1 0 ~ Bit
RIM
IIIIIJII·
No.
This data is loaded into the Accumulator
t
I
RST 5.5 interrupt mask }
RST 6.5 interrupt mask
RST 7.5 interrupt mask
o =enabled
1 =disabled
1 =enabled
M, aster interrupt enable
0= disabled
RST 5.5 interrupt status
RST 6.5 interrupt status
RST 7.5 interrupt status
1 = request pending
o = no request
SID signal level
Thus, the RIM instruction allows you to examine interrupt and external status.
When the SIM instruction is executed the contents of the Accumulator are interpreted as follows:
7 6 5
SIM
4
3 2 1 0
~Bit No.
I 1 I I II I I ,.
~
~
t•
This data must already be in the Accumulator
RST 5.5 maSk}
RST 65 m.ask
0 =. enable
1 = disable
RST 7.5 mask
o = ignore bits 0,
1 and 2
1 = mask as per bits 0, 1 and 2
1 = reset RST 75 latch so a leading edge will cause another
interrupt request
o = disable serial data out
1 = enable serial data out
This bit is transmitted to SOD pin if bit 6 is· 1
Thus the SIM instruction is used to selectively mask interrupts and to output a control signal via the SOD pin.
Note that if bit 6 of the Accumulator is 0 when the SIM instruction is executed, then the contents of bit 7 will not be
transferred to the SOD pin.
5-34
From our discussion of the 8085A reset. recall that following a reset RST 5.5. RST 6.5 and RST 7.5 are all disabled: also.
reset sets the SOD output to O. Thus. following a reset an RIM instruction would input the following data to the A~
cumulator:
RIM
cw
~
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oQ.
1""1.....- - Data loaded to the Accumulator
~~~--~~~~~
l I -_ _ _ _ Mask
1 bits disable interrupts
RST 7.5. RST 6.5 and RST 5.5
a:
o
' - - - - - - - - Master interrupt is disabled
u
~
- - - - - - - - - - These bits reflect the state of the
~ST 7.5. RST 6.5 and RST 5.5 inputs
en
w
~
' - - - - - - - - - - - - - - - This bit reflects the SID signal level
g
8085A MICROPROCESSOR SUPPORT DEVICES
(/)
(/)
c(
all
w
The 8085 has four special purpose multifunction support devices; they are described in this chapter.
a:
The 8085A can use any -5 version of the 8080A support devices described in Chapter 4 and Volume III. If you
Use the low-order eight 8085A address lines, you must de,multiplex the 8085A Address and Data Busses to use
8080A support devices.
Z
oCD
(/)
o
:!!
c(
c
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THE 8155/8156 STATIC READIWRITE MEMORY
WITH I/O PORTS AND TIMER
@
The 8155 and 8156 are custom circuits ~esigned specifically for the 8085A microprocessor. Each device provides 256 bytes of static read/writ~ memory, two or three parailel I/O ports, and a programmable timer. The
8155 and 8156 devices differ only in the active level of the chip enable signal.
Figure 5-1~ illustrates that part of general microcomputer system logic which has been implemented on the
8155 /8156 devices.
Figure 5-20 provides a functional diagram of 8155/8156 logic.
The 8155 or 8156 device is pa~kaged as a 40-pin DIP. It uses a single +5V power supply. All inputs and o~tputs
are TTL compatible.
8155/8156 DEVICE PINS AND SIGNALS
8155/8156 pins and signals are illustrated in Figure 5-21. Signals ni~y be divided into the following categories:
1)
2)
3)
CPU interface and control
Parallel I/O
Programmable Timer
We will first consider CPU interface and control signals.
ADO - AD7 cOlmect to a bidirectional, multiplexed Data and Address Bus. As illustrated in Figure 5-22. these pins
connect to the ADO - AD7 bus lines output by the 8085A microprocessor.
ALE is the Address Latch Enable control signal output by the 8085A microprocessor to identify addresses on the
multiplexed Data and Address Bus.
The 8155 or 8156 has both a memory space and an I/O address space. Whe~ 10/M is high, I/O port addresses are
decoded off ADO - AD7 on the high-to-Iow transition of ALE: this may be illustrated as follows:
ADO - AD7
ALE
101M
5-35
Clock Logic
..
....
Logic to Hantlle
InteH'upt Requests
" from
External, Devices
Arithmetic and
Logic Unit
--
Accumulator
Registerlsl
-
-,
~
....
Instruction Register ~
Control Unit
~
Data Counterlsl
~
Stack Pointer
,~
, 1.
..
1
(,
Interrupt Priority
Arbitration
Bus Interface
Logic
Direct Memory
Access Control
Logic
~ Program Counter
t
t
,~
~
~.
System ,Bus
I~
~
I)',
'ii}
"""
ROM Addressing
and
'Interface Logic
I/O Communication
~ Serial to Parallel
Interface Logic
\
,/1:1"
'"C
:-:
":"
~
"-
'0
"."""
:',
I,'"
.I
,,,'
I{,
i,
Programmqble
Timers
'i
"'.
}i
Read Only
Memory
i
....
,/
l
1
Figure 5-19, Logic of the 8155 and 8156 Multifundion Devices
When lo/iVi is low, the address strobed off,ADO- AD7 is interpreted as a memory address.
CE is active high hi the 8156 device; it is active low in the 8155. There is no other difference between the 8155
and 8156 devices.
The 8155 or 8156 device uses standard 8085A coritrol signals on its CPU interface. These signals are RD, WR,
ALE and 101M. Refer to the description of these control signals given in the 8085A section of this chapter.
5-36
101M
[j
256 x 8
STATIC
RAM
c
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PORT
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(J)
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ADO - AD7
CE (8155) or CE (8156)
ALE
AD
WR
PAO - PA7
B
8
>
PBO·P07
EJ
' TIMER
RESET
PCO - PC7
Vce (-+ 5V)
TIMER IN
Vss (OV)
TIMER OUT
01:1
w
Z
Figure 5-20. Logic Functions of the 81?5/8156 Device
a:
o
In
(J)
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.
1
40
Vec (+ 5V)
39
PC2
3
4
38
37
5
6
36
101M
7
34
CE (8155) or CE (8156)
8
AD
9
10
33
32
31
PC3
PC4
~
cc(
--
2
o
.
TIMER IN
. .RESET
PC5
TIMER OllT
_
.
\VA
ALE
ADO
ADl
-
AD2
11
8155
12
13
30
29
28
27
14
~
26
AD5
AD6
18
23
AD7
19
22
(GND)VSS
20
21
PIN NAME
PCl
PCO
PB7
35
15
16
17
AD3
AD4
""-
---.
..
--"..
-
PB6
PB5
PB4
PB3
PB2
PBl
PBO
PA7
~
PA6
25
24
..
'.
DESCRIPTION
PA5
PA4
PA3
PA2
PA
PAO
TYPE
MUltiplexed Address and Data Bus
Bidirectiomil
PAO - PA7
Eight 1/0 pins. designated as Port A
Bid~rectional
PBO - PB7
PCO - PC5
Eight 1/0 pins. designated as Port B
Six I/O pins. designated as Port C
Bidirectional
AD
iNA
Read from device control
Write to device control
Input
Input
101M
I/O ports or memory
ALE
Address latch enable
Input
RESET
System reset
Input
CE/CE
TIMER IN
Chip enable
Input
Timer clock
Input
TIMER OUT
Timer output signal
Output
"SS VCC
Ground. Power
ADO- AD7
sel~ct
B!dir~tional
Input
Figure 5-21. 8155/8156 Multifunction Device Signals and Pin Assignments
5-37
TIMER IN
elK
Device
TIMER OUT
select
logic
8085
8155
ADO - AD7
ALE ~----------""'0.1 ALE
RD'
WR
AD
WR
101M
101M
RESET OUT
RESET
Figure 5-.22 ... An 8155 Device Connected to an 8085A CPU Bus
Table 5-2. 8155/8156 Device Port C Pin Options
Pin
PCO
PC1
PC2
PC3
PC4
PC5
ALT 1
Input
Input
Input
Input
Input
Input
Port
Pon
Pon
Port
Pon
Pon
ALT 2
Output
Output
Output
Output
Output
Output
Port
Port
Port
Pon
Pon
Pon
ALT 3
A INTR (Pon A Interrupt)
A BF (Port A Buffer Full)
A Si'B (Pon A Strobe)
Output Port
Output Port
Output Port
~
J
ALT4
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A Si'B (Port A Strobe)
B INTR (Port B Interrupt!
B BF (Port B Buffer Full)
. B Si'B (Port B Strobe)
The 8155/8156 device is reset by a high input at the RESET pin. The Reset operation does not
clear memory or I/O locations within .the 8155/8156 device. Thus all memory locations contain zero. 1/0 ports are assigned to input mode and the CounterlTimer is stopped with an initial
zero value.
8155
DEVICE
RESET
8155/8; 56 PARALLEL INPUT/OUTPUT
The interface presented by the 8155/8156 device to external logic consists of three I/O ports and two signals
associated with CounterlTimer logic.
.
We will examine the I/O port logic and then the CounterlTimer logic.
1/0 Ports A and Bare 8-bit parallel ports; each may be defined as an input port or an output port.
1/0 Port C is a 6-bit parallel I/O port; it may be used to input or output parallel data. or Port C pins may support
handshaking control signals for Ports A and B. Table 5-2 defines the four ways in which 1/0 Port C may be used.
When I/O Ports A and B are used for simple parallel input or output, then their operation is
identical to Mode 0 as described in Chapter 4 for the 8255 PPI. Handshaking mode is identical to 8255 Mode 1. We will therefore discuss 8155 input and output with handshaking briefly.
For a more detailed discussion refer to the 8255 PPI description given in Volume III.
5-38
8155/81'56 I/O
MODE 0
8155/8156 I/O'
MODE 1
Input with handshaking may be illustrated as follows:
c
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oDo
a:
o
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~
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~
g
en
en
ct
D1:I
w
Z
a:
o
!Xl
en
o
~
ct
C
ct
@
An event sequence begins with external logic inputting parallel data to I/O Port A or B: external
logic must pulse STROBE low, at which time the parallel data is loaded into the I/O port buffer. This causes BF.
the Buffer Full signal. to go high.
External logic uses the BF signal as an indicator that no more data can be written.
As soon as the externally provided low STROBE pulse is over. the interrupt request signallNTR goes high. This allows
the 8085A to be interrupted once data has been loaded i~to the input buffer of the I/O port.
BF and INTR remain high until the CPU reads the contents of the I/O port. The read operation will be identified by a low
RD pulse input to the 8155/8156 device.INTR is reset at the beginning of the RD'pulse. while BF is reset at the end of
the RD pulse. BF therefore is high while data is waiting to be read and while data is being loaded into the I/O port buffer
or read out of the I/O port buffer. INTR is high only while data is waiting to be read.
BF and INTR have associated bits in the Status register of the 8155/8156 device.
You connect INTR to an 8085A interrupt request if you want an interrupt-driven system. You write a program
which polls the Status register of the 8155/8156 if you want to operate the system under program control.
Strobod output timing may be illustrated as follows:
In output mode the I/O port buffer is initially empty. which means that the CPU must transmit data to the I/O port.
Therefore INTR is initially high.
As soon as the CPU writes data to the I/O port. the interrupt request signallNTR is reset low: this occurs on the leading
edge of the WR pulse. On the trailing edge of the WR pulse BF is output high, telling external logic that data is in
the I/O port buffer and may be read.
.
External logiC strobes the data out by providing a low pulse at STROBE. The leading edge of STROBE resets BF
low. while the trailing edge of STROBE sets INTR high. causing the CPU to again output parallel data.
You connect INTR to an appropriate 8085A interrupt request pin if you want an interrupt-driven system. You
write a program to poll the Status register if you want to operate the 8155/8156 Linder program control.
A simple method of using the 8155/8.156 device parallel input/output with handshaking. in interrupt mode would be to
connect INTRA and INTRB to RST 5.5 and RST 6.5.
8155/8156 DEVICE ADDRESSING
Having discussed 8155/8156 device memory and I/O ports, we must now look at device addressing ..
The 8155/8156 has 256 bytes of static read/write memory which are addressed by ADO - AD7 while Chip Enable is
true. and 10/M = O.
5-39
The 8155/8156 has eight addressable I/O ports. ADO. AD1 and AD2 select I/O ports while Chip
Enable is true and 10/M = 1. These are the eight addressable I/O ports:
AD2
AD1
ADO
a
a
a
a
a
a
a
1
1
1
1
1
1
a
a
1
1
PORT
8155/8156
I/O PORT
ADDRESSES
Status/Command registers
Port A
Port B
Port C
CounterlTimer register. low-order byte
CounterlTimer register. high-order byte
Unused
Unused
1
a
1
a
1
a
1
Chip Enable is derived from A8 - A 15. which holds th~ high-order byte of a memory address. or the I/O device number.
Chip Enable thus defines the exact address and I/O space for the 8155/8156 device. Here is one possible configuration:
A15
A14
A13
A12
All
Al0
A9
AS
These lines
contribute
to CE
These lines
are ignored
J----
101111 1010 I
T
n
CE(S156)
I n I n I xI xI xI xI x'l xI xI x11"'II4t--- Valid memory addresses
t /
ADO - AD7. x can be 0 or 1
These bits are ignored. They may have
any value.
8155/8156 memory bytes will be selected by any memory addresses in the range 6n0016 through 6nFF16. "n" represents any digit in the range a through 7. Let us assume that programs access 8155/8156 memory bytes via addresses
in the range 600016 through 60FF16; we must further assume that addresses created by values of n in the range 1
through 7 never occur.
Now the same chip select that you use to define your memory address space is also going to define your I/O address space. Recall that the 8-bit I/O device number is output twice following execution of an I/O instruction - once
on the high-order eight address lines A8 - A 15 and again on the low-order Address/Data Bus lines ADO - AD7. Thus the
device select code which you generate from the eight high-order address lines for a memory address is the same device
select code which you generate for the 8155/8156 I/O space.
5-40
But whereas the 8155/8156 has 256 addressable memory locations, it has eight addressable I/O ports: I/O ports are
selected as follows:
TI'p.
~ Bit No ..
7 6 5 .. 3 2 1 0
I_.._- ~rt Num~'
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-
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CI)
CI)
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Z
a:
o
CE
If Chip Enable is true when A 15 - A 11 is 011002, then I/O port addresses will be 6016 through 6716.
Address lines A 15 - A 11 represent I/O device number bits 7 through 3. This is because the I/O device number is output
on A 15 - A8 following execution of an I/O instruction. It is therefore fortunate that we only used address lines
A 15 - A 11 to create Chip Enable. Had we used A8, A9 or A 10, the low-order three I/O device code bits would have
served a double purpose - with strange results.
Suppose A 10 = 0 is a prerequisite for device select logic to be true: these are the memory and I/O port selects which
will result:
III
CI)
o
Memory
I/O Port
~
Address
Address
<
Q
<
@
r
15 1413 1211 10 9
A........._ - - - -..,....r
8 7
6
54 3 2 1 0
:&1
,A..
7 6 5 4
3
2
"
1 0 . . . . - B i t No.
TI~' I, It" I'I~I~
Address bits
Don't care
Device Select
You can now address only four of the eight 8155/8156 I/O Ports. You cannot include address lines A8, A9 or
A 10 in the device select logic that you use for any 8155/8156 device; if you do, you will limit the I/O
capabilities of the device.
101M discriminates between exectuion of I/O instructions and memory reference instructions.
THE 8155/8156 COUNTER/TIMER
CounterlTimer logic consists of a 16-bit register, addressed as two 8-bit I/O ports, an input clock signal and an
output timer signal. This may be illustrated as follows:
....
~
r15 14
I/O Port
~~
..
I/O Port
100
101
'r
t: +. __
13 12 11 10 9 8 7 6
IIIII
~~
5 4 3 2
-~
,
1 0 :.....
- - - - Bit No.
"_::~~~~ '~~nt
I_I_I_I_I_.#"_'_.__
-
Timer mode
5-41
The low-order 14 bits of the Counter!Timer register must be initialized with a 14-bit binary value that will
decrement on low-to-high transitions of TIMER IN. If TIMER IN is connected to the 8085A clock output signal elK.
then the timer is computing real time. TIMER IN can alternatively be connected to any external logic in which case the
timer is counting external events.
The timer times out when it decrements to zero.
The two high-order bits of the Counter!Timer register define one of four ways in which the TIMER OUT signal
may be created.
' .
In Mode 0, TIMER OUT is high for the first half of the time interval and low for the second half of
the time interval. This may be illustrated as follows:
8155/8156
TIMER
MODE 0
TIMER IN
TIMER OUT
Timer
initial count
is N
STOP
START
If N is odd. the extra pulse will occur while TIMER OUT is high.,
In Mode 1, as in Mode O. TIMER OUT is high for the first half of theco~ilt and low for the' second half. However. the
timer is automatically reloaded with the initial value following each time out. creating a square wave which may be illustrated as follows:
\
TIMER OUT
Timer initial
f
\
l
f
f
Reload N
Reload N
count is N
START
Mode 2 outputs a single low clock pulse on the terminal count. then stops the timer. Timing may be illustrated as
follows:
'-----,.............,-_....
TIMER IN
....--..aqr---. .- -...- - - - - -.............- - - - . . . ,...- ... ,
TIMER OUT
Timer initial
. Decrement
Decrement
count is N
to Zero
START
STOP
Mode 3 is identical to Mode 2. except that when the timer times out 'the initial counter value is automatically reloaded .
. 5-42
8155/8156 CONTROL AND STATUS REGISTERS
The Control and Status registers of the 8155/8156 are used to control both timer and parallel I/O logic. Let us
now examine these registers.
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oen
The Control and Status registers of the 8155/8156 device are accessed via a single I/O port address. This is the
lowest of the 8155/8156 I/O port addresses. When you write to this address you access the Control register;
when you read from this address you access the Status register.
8155/8156 internal logic will interpret Control register bits as follows:
..
7 6
S .. 3 2 1 0
~Bit No.
. .__--Control register
~~~~~~~~
Port A definition }
.....- - - - P o r t B definition
en
<
oIS
w
Z
II:
. . . ------1
oa:I
en
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~
c<
= Input
1 = Output
See Table 5-2
....- - - - - - - - P o r t A interrupts
0 = Disable
....- - - - - - - - - P o r t · B interrupts
1 = Enable
<
@
Port C definition
00 =ALT 1
01 = ALT 3
10=ALT4
11 =ALT 2
0
....-----------<:
Timer control
00 = No effect on timer
01 = Stop timer immediately. if running
10 = Stop timer after next time out. if running
11 = Start timer immediately
Status register bits are set and reset as follows:
7 6· S .. 3 2 1 0 . . . . - Bit No.
'-1--- Status register
~I..r-I~~""""""",,,"""'"
~
_ _ _ Port A interrupt request
- - - - - Port A buffer full
' " - - - - - - - Port A interrupt enabled
1 = True
- - - - - - - - Port B interrupt request
0 = False
......- - - - - - - - Port B buffer full
......- - - - - - - - - P o r t B interrupt enabled
- - - - - - - - - - - - T i m e r interrupt. Set to 1 on time out. reset to 0 when
Status regist.er is read or a new count is started
8155/8156 DEVICE PROGRAMMING
Accessing 8155/8156 read/write memory is self-evident. If you execute a memory reference instruction that
specifies an address within the 8155/8156 address space. you will access an 8155/8156 memory byte.
Parallel I/O programming is also self-evident; you begin by outputting an appropriate code to the Control register jn
order to define the modes in which various ports will operate. and to enable or disable Mode 1 interrupts. Your only
caution at this time must be to ensure that the two high-order bits of the Control code are 0; this prevents initiation of
any timer operations.
If you are using I/O ports without handshaking, the Status register is not affected by I/O operations. No control
signals or status indicate that new data has been input to. or has been read from I/O ports.
If 'you are operating the 8155/8156 in handshaking mode under program control. then you must poll the Status register
in order to determine whether data is waiting to be read or must be written. Your program will consist of a series of input instructions which read status. followed by conditional branches that read or write data.
5-43
If you are operating the 8155/8156 parallel I/O in handshaking mode under interrupt control. then whenever data is
waiting to be read or must be written. the high INTR control signal will vector program execution to an appropriate interrupt service routine.
.
You can at any time read the contents of an I/O port that has been declared an output port. You will simply read
back whatever data was most recently written out to that 110 port. Reading the contents of an output port will have no
effect on handshaking control signals associated with that port.
Let us now examine programming associated with 8155/8156 CounterlTimer logic.
You must first initialize the .16-bit CounterlTimer register by outputting two bytes that specify timer mode and initial
count. The order in which you output these two bytes is unimportant.
Next you output an appropriate Control code in order to start the timer. When you output a Control code. remember not
to modify any control bits that define parallel I/O operations.
Here is an appropriate initialization instruction sequence:
MVI
OUT
MVI
OUT
MVI
OUT
A.80H
OC4H
A.60H
OC5H
A.OFAH
OCOH
LOAD 6080H AS AN INITIAL COUNTER
VALUE. SELECT COUNTER MODE 1
START TIMER
. This instruction sequence assumes that the 8155/8156 I/O port addresses are C016 through C516. The code FA16
output to the Control register starts the timer. and defines Port A as an input port. Port B as an output port. both in
handshaking mode with interrupts enabled.
You can at any time stop the counter. either immediately or following the next time-out. The following instructions will
stop the counter immediately:
MVI
OUT
A.7AH
COH
STOP THE TIMER IMMEDIATELY
The following instructions will stop the counter after the next time-out:
MVI
OUT
A.BAH
COH
STOP THE TIMER AFTER THE
NEXT TIME OUT
The Counter/Timer instruction sequences illustrated above contain a nonobvious propensity for programming
errors. We start the timer by outputting the code FA 16 to the Control register; we stop immediately by outputting the
code 7A16 and we stop the timer after the next time-out by outputting the code BA16. In reality. this is the code we are
outputting:
7 6 5 4 32 1 0 .......----Bit
I
I I 'Tl
IllT1
10 I tL....
No.
O
_+.
_'_ _
Port A input
Port B output
-
Port C ALT 4
Enable Ports A and B interrupts
Timer code:
11 = Start immediately
10 = Stop after next time out
01 = Stop immediately
Whenever you output Control codes to modify 8155/8156 timer operation. you must always remember to output bits 0
through 5 correctly. in order to maintain previously defined parallel I/O options. A commonly used programming
technique that frees you from having to remember the condition of irrelevant bits in a control word is to use
AND and OR masks. Consider this general purpose instruction sequence:
IN
ANI
(ORI
OUT
COH
3FH
COH
COH
INPUT PRESENT CONTROL CODE
CLEAR TIMER BITS
SET TIMER BITS)
RESTORE CONTROL CODE
5-44
This technique will not work with the 8155/8156 device, since you cannot read the contents of the Control
register. If you read from the address of the Control register, you will access the Status register. If you want to
use a masking technique. you must maintain the Control code in memory. Here is an instruction sequence that will
work:
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II:
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U
~
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w
!i
LDA
ANI
(ORI
OUT
STA
CONTRL
3FH
COH
COH
CONTRL
LOAD CONTROL CODE FROM MEMORY
CLEAR TIMER BITS
SET TIMER BITS)
OUTPUT CONTROL CODE TO 8155/8156
SAVE CONTROL CODE IN MEMORY.
Your instruction sequence will include the ANI mask to clear timer bits. or the ORI mask to set timer bits. but obviously
not both.
CONTRL is the label for
g
som~
read/write memory byte which always holds the current 8155/8156 Coritrol code.
THE 8355 READ ONLY MEMORY WITH I/O
(I)
(I)
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C
c(
@
The 8355 provides 2048 bytes of read-only memory and two 8-bit I/O ports. The device has been designed to
interface with the 8085A CPU.
Figure 5-23 illustrates that part of our general microcomputer system logic which has been implemented on the
8355 device.
'
.
"
The 8355 is packaged as a 40-pin DIP. It uses a single +5V power supply. All inputs and outputs are TTL-compatible. The device is implemented using"N-channei MOS technology.
Figure 5-24 fu~cti~~aiIY illustrates logic of the 8355 device. A simple 8085A-8155/8156-8355 configuration is
illustrated in Figure 5-26.
There are many similarities between the 8155/8156, which we have already described, and the 8355. Where
appropriate we will refer back to the 8155/8156 discussion for clarification of concepts.
8355 DEVICE PINS AND SIGNALS
8355 pins and signals are illustrated in Figure 5-25.
The 8355-8085A interface differs somewhat from the 8155/8156-8085A interface in that the 8355 has more
memory, fewer addressable I/O ports, plus the ability to address I/O ports within the memory space of the,
device.
Having 2048 bytes of addressable read-only memory. the 8355 requires eleven address pins. These are derived
from ADO-AD7 and A8-A 10.
Having only four addressable I/O ports. the 8355 I/O address logic decodes ADO and AD1 only. I/O ports are selected
as follows:
AD1
ADO
a
1
o
1
1
a
a
1
I/O PORT A
I/O PORT B
DATA DIRECTION REGISTER A
DATA DIRECTION REGISTER B
5-45
Clock Logic
...
Logic to Handle
Interrupt Requests
from
External Devices
~
~
Arithmetic and
Logic Unit
Instruction Register
,'"
-
Accumulator
Registerisl
.........
Control Unit,
...
Data Counterisl
~
r
~
Stack Pointer
~
Program Counter
r
Interrupt Priority
Arbitration
Bus Interface
Logic
,.
' Direct Memory
Access Control
Logic
,t
r
$
...
..
System 'Bus
~
. i.'iii,'..'
,•....
I/O Communication
Serial to Parallel
Interface Logic
~",
i,r;r~'
t
A
•
i.
;;
Iii
'.'i
f!)
~;
i'"
J
RAM Addressing
and
Interface Logic
_t_
,>/
Programmable
Timers
~
!
~
Read/Write
Memory
i.".
,.'C:}{i·<.'.".'."
,
Figure 5-23. Logic of the 8355 and 8755 Multifunction Devices
5-46
~
CLK
READY
Q
w
I-
<
II:
AOO- AD7
0
Q.
A
PAO - PA7
B
PBO - PB7
II:
0
U
~
AS-A10
en
w.
2Kx 8
I-
ROM
<
CE
U
Ce
0
U)
U)
101M
<
ALE
all
w
AD
iOW
z
II:
RESET
lOR
0
In
U)
0
~
<
Q
<
~-------- VCC (+ 5V)
@
L..._ _ _ _ _ _ _ _ _ _
Vss (OV)
Figure 5-24. Logic Functions of the 8355 Device
8355 device select logic must generate the chip enable signals CE and CE from the hve address lines A 11-A 15.
The discussion of select logic given for the 8155/8156 device applies also to the 8355.
If you select 8355 memory and I/O ports in their respective address spaces, the control signals ALE, RD, and
are used exactly as described for the 8155/8156 device.
10liVi
But you can also access 8355 I/O ports within the 8355 memory space using control signals lOW and lOR.
lOW and lOR are control signals which override 10/M and RD when accessing I/O ports.
Providing CE and CE are true. a low input on lOW will cause data on the Data Bus to be written into the I/O port
selected by ADO and AD1. irrespective of the 10/M level. Similarly. lOR low will cause the contents of the I/O port
selected by ADO and AD1 to be output on the Data Bus.
You can connect lOW directly to the WR control signal. and thus write into the four I/O ports of the 8355 device as
though they were the four low-order memory bytes. But connecting lOR to RD is not so straightforward. The 8355
device may receive a low input on lOR. to'gether with low inputs on RD and 101M; it will then attempt to read the contents of a read only memory byte and an I/O port at the same time. While elaborate schemes could be devised for
generating separate selects that map the four I/O ports into a memory space of its own. it is wisest to ignore the lOR
signal if you are using 8355 memory and I/O logic. Use lOR only when the 8355 is configured as two I/O portsand the 8355 memory is unused. lOFi and lOW are used in 8048 microcomputer systems; that is the principal
reason they were designed into the 8355 device.
5-47
rl------;~--40
39 ....r--......
CE
CE
CLK
RESET
VCC (+ 5V)
PB7
38
PB6
37 ............. PB5
READY
10/M
i5R
RD
iOW
10
ALE
ADO
ADl
11
12
13
14
15
AD2
AD3
AD4
AD5
8355
16
17
AD6
AD7
t-........- PB4
................ PB3
............. PB2
............. PBl
............. PBO
.....f--~ PA7
............29 ..............~
28
27 .............
26
25 ..............
PA6
PA5
PA4
PA3
PA2
PAl
24 .....1-....- PAO
23 .........__ Al0
A9
22
....1---A8
18'
19
20
(GND),(SS
36
35
34
33
32
31
30
;n
PIN NAME
TYPE
DESCRIPTION
ADO-AD7
AS -Al0
~AO - PA7
PBO - PB7
CLK
Multiplexed Address and Data Bus
Memory Address Unes
Eight I/O pins. designated as Port A
Eight I/O pins. designated as Port D
Read from device control
Read from I/O port control
Write to I/O port control
I/O ports or memory select
Address latch enable
System reset
Chip enables
Wait state request
TIming for Wait state request
VSS. VCC
Ground. Power
R5
iOR
loW
10/M
ALE
RESET
CE.Ce
READY
Bidirectional
Input
Bidirectional
Bidirectional
Input
Input
Input
Input
Input
Input
Input
Output. tristate
Input
Figure 5-25. 8355 Multifunction Device Signals and Pin Assignments
)A8-A15
~
~b~
RESETIN--HlDAHOlD _ _
["-
INTR _ _
I-t--
> ADO-AD7
•
•
f----
8085A
INTARST7.5_
RST6.5-RST5.5 _ _
!:·· ~~~DY
~
A8-A15
I
J
t
~
1 - ' IT
llElIJCE·
S£lECT
lOGIC
~¢:!> ~~ -
AD7
i-
X2
1 - RESET
_ 1 0 1WA
M
1I____
8155
.
LTIMERIN
~:"':~
PCO - PC5
I_AD
_ _ _ ALE
VCCL--
~
L
'----.I
~
DEVICE·
SELECT
LOGIC
PPAO-PA7
iOW
Ro
ALE
8355
AS -Al0
ADO - AD7
CE
CE
Figu re 5-26. An 8085A-8155/8156-8355 Microcomputer System
5-48
Poo - PB7
loR
READY
ClK
~ RESET
iO/M
~
------- ==
-·Complexity of device select logic depends on
the number of devices in the system.
Rii
101M
RESET OUT
f----
TRAP - - 5051-
ALE
WI!
PPoo-PB7
8355 READY LOGIC
The 8366 device has on-chip logic to create a READY signal that will insert one Wait state into the 8085A
machine cycle that references the 8355 device. 8355 READY signal timing may be illustrated as follows:
MC1
cw
~
a:
oD..
a:
o
(..)
Tw
ClK
~
en
w
~
g
CE·CE
en
en
ALE
ciJ
w
Z
READY
ct
........................................
I
a:
I
o
!Xl
I
I
en
o
~
ct
C
ct
@
The READY output is floated by the 8355 device while CE·CE is false.
READY is forced low by the combination of Chip Enable true while ALE is high: READY stays low until the first low-tohigh transition of CLK following the end of the ALE pulse. If you refer back to Figure 5-11. you will see that this READY
logic creates a single Wait state.
.
The problem with the READY logic illustrated above is that in order to have Chip Enable true while ALE is high. chip
enable logic must be tied directly to Address Bus lines. Refer to the timing diagram below and you will see that AOA 15 is stable while ALE is high.
But as we discussed earlier in this chapter. you can derive chip enable logic directly from A8-A 15 only in small 8085
microcomputer systems. When a large number of support devices are connected to the System Bus. you must
guarantee against spurious device selects by including control signals in the chip enable logic. Logic illustrated earlier
in this chapter shows how to create a chip select signal that is true between the trailing edge of ALE and the low-tohigh transition of RD or WR. The following chip enable timing results:
T1
T2
T3
I
~
ClK
I
I
),(
ALE
I
l
:
I
\
,I
I
~
I
I
I
AD orWR
CE
5-49
I
Timing illustrated above is theoretically the best guarantee against spurious selects: but it will not work if you want to
create a single Wait state when using an 8355 device. If Chip Enable (CEl goes true on the trailing edge of ALE. READY
will never be reset lciw:
MCl
I
'Tl
I
ClK
~
:L..J
1
T2
I
I
I
ALE
,
I
I
T3
I
I
T4
I
~
I
L
I
cE·EE 1
1_ _ _...".'-1
I:--_ _..,._....~
AD orWR I
,1
READY
.fl ..--------.
:
I
1
You can resolve this problem by simply inverting ALE as a clock input to the select logic flip-flop.
But when do you need to induce a Wait state?
8355 device timing is fast enough to respond to memory and I/O accesses without the inclusion of a Wait state. unless
you have buffers on the System Bus and the buffers introduce unacceptably long response delays. Therefore. ignore
the READY signal logic of the 8355 in small 8085Asystems and derive chip enable logic directly from the high-order
address lines A 11 ~A 15. In larger systems where buffers on the System Bus force the 8355 device to require a Wait
state. use READY logic of the 8355 device.
8355 I/O LOGIC
Let us now I~ok at the I/O logic of the 8355 device. This device has two I/O ports whose pins can be individually
assigned. to input or output. This assignment is made by loading appropriate Control codes into a Data Direction
register assocIated with each I/O port. A 1 in any bit position of the Data Direction register defines the associated 1/0
porfpirias an output pin. A 0 in any bit position defines the associated I/O port pin as an input pin. This may be illustrated ~as follows:
Data Direction
Register A:
(Port 2)
1
0
0
1
0
1
1
Data Direction
Register B
(Port 3)
I/O Port A
. (Port 0)
1
"
-
1
1
0
1
0
1
1
...
0
I/O Port B
(Port 1)
...
...-
...
Observe that the 8355 has no 1/0 with handshaking. For I/O with handshaking you should use the 8155/8156 or the
8255 devices.
5-50
THE 8755A ERASABLE PROGRAMMABLE READ
ONLY MEMORY WITH 1/0.
Q
w
~
a:
oa.
a:
o
o
~
u)
w
~
g
en
en
~
alS
w
Z
a:
o
m
en
o
The 8755A device provides 2048 bytes of erasable programmable read-only memory and two 8-bit I/O ports . .
The only difference between this dev.ice and the 8355, which we have just described, is the fact that the
8755A read-only memory is programmable and erasable. There are minor pin and signal variations supporting
..
the EPROM. These differences are identified in Figure 5-27.
The 8755A is a new version of an earlier device, the 8755. The only difference between the
two is the level of Vee during normal read operations: +5V on the current 8755A, but OV
on the earlier 8755.
This discussion of the 8755A device is limited to describing how you program the read-only memory. In all other ways.
the 8755A device is identical to the 8355.
There are two Chip Enable signals' on the 8755A device: CE is the standard chip enable. which must be true when the
8755 device is being accessed for any purpose. either in normal operation or when programming the read-only memo~
ry. CE is a high true signal.
.
The second Chip Enable signal. CE/PROG. is first held low. then is pulsed true only when you are programming the
read-only memory. You must apply a +25V pulse lasting between 50 and 100 milliseconds. beginning with the leading
edge of ALE. At this time. data will be written into the addressed read-only memory location. Timing may be illustrated
as f o l l o w s : '
.
~
~
Q
~
@
ClK
ADO - AD7
ALE
CE
I
26V
5V
OV
READY
I
DATA.
:----1
n
I
~
I
I
I
CE/PROG ,
VDD
,
I
ADDRESS
A
8755A
--------I
8755
\
You erase the programmable read-only memory by exposing it to ultraviolet light for a minimum of twenty minutes.
5-51
;·.···~~ANDCf
..
CE
ClK
RESET
VDD (+5Vor +25V) *
READY
10/M
-..
iO'R
R5
--'"
--
TOw
...
ALE
ADO
ADl
AD2
AD3
AD4
ADS
AD6
AD7
(GND) Vss
-
- -.
-- .
-- --
PIN NAME
1
40
2
39
3
4
38
37
5
6
7
35
34
6
33
9
10
32
36
..
"'"-
VCC (+5V)
--.
....
-- --- ..
PB7
PB6
. PB5
PB4
PB3
PB2
PBl
PBO
PA7
12
31
30
29
13
14
28
27
15
26
16
17
25
24
18
23
Al0
.19
22
21
A8
11
8755A
20
--
PA6
PA5
...
PA4
..
PA2
PA3
DESCRIPTION
, PAl
PAO
A9
TYPE
ADO - AD8
Multiplexed Address and Data Bus
Bidirectional
AS - Al0
PAO - PA7
Memory address lines
Eight I/O pins, designated as Port A
Input
PBO - PB7
Eight I/O pins. designated as Port B
Read from device control
Bidirectional
Input
iOR
iOW
Read from I/O port control
Input
Write to I/O port control
Input
10/M
I/O ports or memory select
Address·latch enable
Input-
Ri5
ALE
RESET
CE
PROG AND
READY
ClK
System reset
Chip enable
CE
Bidirectional
Input
Input
Input
PROM programming chip enable
Input
Wait state request
Timing for Wait state request
Output. tristate
Input
VDD
Programming voltage:
+ 25V to program
+ 5V in normal read operation*
VSS· VCC
Ground. Power
*VDD is OV in earlier 8755 read mode
Figure 5-27. 8755A Multifunction De·vice Signals and Pin Assignments
5-52
DATA SHEETS
This section contains specific electrical and timing data for the following devices:
• 8085A CPU
Q
w
~
a:
oD.
• 8155/8156 RAM/IO
• 8355 ROM/IO
• 8755A EPROM/IO
a:
u
o
~
en
w
~
g
en
~
all
w
Z
a:
o
Ul
en
o
~
c(
Q
c(
@
5-01
SOS5A
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O°Cto 70°C
Storage Temperature ..............-65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............ - 0.5 to + 7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . 1.5 Watt
*COMMENT: Stresses above thosh;stedUhfl.e(i<~'Absolute
Maximum Ratings" may cause per;a'n8ntdafn~'t() the
device. This is a stress rating only and iun~tiQ,,!if~p,~il
tion of the device at these or any other cond"tionfafjC?J#;\~
those indicated in the operational sections of titl$spe~j1J,i;,
cation is not implied. Exposure to absolute maximum"
rating conditions for extended periods may affect de~ice'
reliability.
D.C. CHARACTERISTICS
= o°c to 70°C; Vee = 5V ±5%; Vss = OV; unless otherwise specified)
(TA
Min.
Max.
Units
Input Low Voltage
-0.5
+0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
VOL
Output Low Voltage
0.45
V
IOl
VOH
Output High Voltage
V
IOH
= 2mA
= -400J.LA
= Vee
Symbol
V il
Parameter
2.4
Test Conditions
lee
Power Supply Current
170
mA
III
Input Leakage
±10
J.LA
Vin
IlO
Output Leakage
±10
J.LA
0.45V
VllR
Input Low Level, RESET
-0.5
+0.8
V
VIHR
VHy
2.4
Vee +0.5
V
Hysteresis, RESET
Input High Level, RESET
0.25
< V out < Vee
V
TIMING CHARACTERISTICS
Bus Timing Specification as a Tcye Dependent
tAL
tlA
tLl
t lCK
t Lc
tAD
tRO
tRAE
teA
tow
two
tcc
tCl
t ARy
t HACK
tHABF
tHABE
tAC
t1
t2
-
(1/2) T - 50
MIN
-
(1/2) T - 60
MIN
-
-
(1/2) T - 20
MIN
(1/2) T - 60
MIN
(1/2) T - 30
MIN
(5/2 + N) T - 225
(3/2 + N) T - 180
MAX
(1/2) T -10
MIN
MAX
(1/2) T - 40
MIN
(3/2 + N) T - 60
MIN
-
(1/2) T - 60
MIN
(3/2 + N) T - 80
MIN
-
(1/2) T-ll0
MIN
(3/2) T - 260
MAX
(1/2) T - 50
MIN
-
(1/2) T +50
MAX
(1/2) T + 50
MAX
-
(2/2) T - 50
MIN
-
(1/2) T - 80
MIN
(1/2) T - 40
MIN
(3/2) T - 80
tRV
NOTE: N is equal to the total WAIT states.
T = tCYC.
MIN
Data sheets on pages 5-02 through 5-018 reprinted by permission of Intel Corporation. Copyright 1978.
,5-02
. SOS5A
!;
(TA =o°c to 70°C' VCC
Parameter
A C CHARACTERISTICS
Symbol
= 5V +5%'
- '"SS-- OV)
i,
Max.
Units
TestJ;ol:ld itiot\f'i t,
2000
ns
See note;'1/2:~a~;4"5~y
TCYC
ClK Cycle Period
320
cw
t1
ClK low Time
80
ns
a:
t2
ClK High Time
120
ns
~
o
11.
tr, tf
ClK Rise and Fall Time
tAL
Address Valid Before Trailing Edge of ALE
110
tLA
Address Hold Time After ALE
100
ns
tLL
t LcK
ALE Width
140
ns
ALE low During ClK High
t LC
Trailing Edge of ALE to leading Edge of
Control
100
130
ns
en
en
w
Z
tAFA
a:
o(J
~
en
w
~
g
.,
<
a:
o
CO
en
o
:!:
<
c
<
@
30
Address Float After leading Edge of
, ,READ (lNTA)
ns
ns
0
ns
Valid Address to Valid Data In
575
ns
tAO
t ROH
READ (or INTA) to Valid Data
300
ns
0
ns
tAAE
Trailing Edge of READ to Re·Enabling
of Address
150
ns
tCA
Address (AB-A 15) Valid After Control
120
ns
tow
Data Valid to Trailing Edge of WR ITE
420
ns
two
Data Valid After Trailing Edge of WR ITE
ns
tce
Width of Control low (RD, WR, INTA)
100
400
tCL
Trailing Edge of Control to leading Edge
of ALE
50
ns
t AAy
t AyS
READY Valid From Address Valid
t AYH
READY Hold Time
t HACK
HlDA Valid to Trailing Edge of ClK
tHABF
Bus Float After HlDA
210
ns
tHABE
HlDA to Bus Enable
ns
tLOR
ALE to Valid Data In
210
460
TeYc
220
110
READY Setup Time to leading Edge of ClK
ns
ns
0
ns
110
ns
ns
400
ns
tAC
t HOS
Address Valid to leading Edge of Control
270
ns
HOLD Setup Time to Trailing Edge of ClK
ns
t HOH
HOLD Hold Time
170
0
INTR Setup Time to Falling Edge of ClK
160
ns
tiNS
= 320ns;
C L =150 pF
ns
' Control Trailing Edge to leading Edge of
Next Control
tAV
..
ns
tAO
Data Hold Time After READ ONTA)
"j",,:,;.t _
,',
Min.
ns
(M1, Tfonly). Also RSTand TRAP
INTR Hold Time
0
ns
tlNH
- 50 and 51.
NOTES: 1. AB-15 Address 5pecsapply to 101M,
2. For all output timing where CL '" 150pf use the following correction factors:
25pf <: CL < 150pf: -.10 nslpf
150pf < CL <: 300pf: +.30 ns/pf
3. Output timings are measured with purely capacitive load.
4. All timings are measured at output voltage VL = .av, VH - 2.0V, and 1.5V with 20ns rise and fall time on inputL
5. To calculate timing specifications at other values of TCYC use the table in Table 2.
6. L.E. - Leading Edge T.E ... Trailing Edge
5-03
SOS5A
WAVEFORMS
Figure 10. Clock Timing Waveform
Read Operation
T,
'AO------------
ALE
1-----+----- t RO - - - - - - -..,
- - - 'CC-·~---Ir--__j---
RD/INTA--+----++----.I
READY
Writs OpGn~tlon
T,
,'--_...-
''--_...-1
ADDRESS
I
)
1-
ADDRESS
r'll-
, tCA _
I
X
DATA OUT
~_llA---l ~
tow
X
-two-I
1/
ALE
.
I+-t Al -
I
tcc
II ....- t ---.
el
~tlC-1
f------
tAC - - - ' ARy · -
READY
tRYS
\
t RYH .1
I
1
Figure 11. 808SA Bus Timing
5-04
SOS5A
TZ
Q
w
\
!ta::
oa..
o
(J
~
en
w
!t
g
.J
\
t
HOLD
a::
THOLO
T3
/
ClK
/
.T
• I--IHA.F-I-
BUS
TI
~IHAIl-H
I.r'
H
(ADDRESS, CONTROLS)
,
,
r-IHACK"
f
HlDA
\
:~
"\
I HOS • + I HOH
T HOLO
1"10.
I
o
o
c:(
011
w
Z
a::
oIII
Figure 13. BO~5A Hold Timing I
o
o
~
c:(
Q
c:(
@
1 1 - - - - - BUS FLOATING'
------.1
ALE
Rol--------------t-----~----------------~
HOLD
HLOA________________-JI
'HACK
,"AIF
Figure 14. BOB5A Interrupt and Hold Timing
5-05
'IO!Q IS ALSO FLOATING DURING THIS TIME
8155/8156
ABSOLUTE MAXIMUM RATINGS·
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TemperatureUnderBias ................ 0°Cto+70°C
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin
WithRespecttoGround ............... -0.3Vto+7V
Power Dissipation ............................... 1.5W
D.C. CHARACTERISTICS
.ITA = O°C to 70°C; Vee = 5V ±·5%)
PARAMETER
MIN.
VIL
Input low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
0.45
V
IOL
V
IoH
SYMBOL
MAX.
UNITS
TEST CONDITIONS
IlL
Input leakage
±10
J.LA
= 2mA
= -400,uA
VIN = Vee to OV
ILO
Output leakage Current
±10
J.LA
0.45V ~VOUT ~Vec
IcC
Vee Supply Current
180
mA
IldCE)
Chip Enable
8155
8156
+100
-100
J.LA
J.LA
VOL
Output low Voltage
VOH
Output High Voltage
2.4
l~akage
.5-06
VIN
= Vee to OV'
8155/8156
A.C. CHARACTERISTICS
Q
w
(TA
=o°c to 70°C; Vcc =5V ± 5%)
MIN.
SYMBOL
PARAMETER
tAL
Address to Latch Set Up Time
tLA
Address Hold Time after Latch
a:
tlC
Latch to R EAD/WR ITE Control
a:
tRO
Valid Data Out Delay from READ Control
~
o
11.
o(J
MAX.
UNITS
80
ns
100
ns
170
V~!id
400
ns
ns
tAD
Address Stable to Data Out
tll
Latch Enable Width
tROF
Data Bus Float After READ
0
tCl
READtWRITE Control to Latch'Enable
20
ns
c(
tcc
READ/WRITE Control Width
250
ns
01:1
tow
Data In to WR ITE Set Up Time
150
ns
ns
~
en
w
~
g
II)
II)
w
Z
a:
o!XI
II)
o
~
c(
Q
c(
@
100
..
two
Data In Hold Time After WRITE
0
tRv
Recovery Time Between Controls
300
twp
WR ITE to Port Output
ns
100
ns
ns
tpR
Port Input Setup Time
70
ns
tRP
Port Input Hold Time
50
ns
tSBF
Strobe to Buffer Full
tss
Strobe Width
tRBE
400
ns
READ to Buffer Empty
400
ns
tSI
Strobe to INTR On
400
ns
tROI
READ to INTR Off
400
tpss
Port Setup Time to Strobe Strobe
50
tpHS
Port Hold Time After Strobe
120
tSBE
Strobe to Butter Empty
400
ns
tWBF
WR ITE to Buffer Full
400
ns
tWI
WR ITE to INTR Off
400
ns
tTL
TIMER-IN to TIMER-OUT Low
400
ns
tTH
TIMER-IN to TIMER-OUT High
49P
ns
tROE
Data Bus Enable from READ Control
200
ns
5-07
ns
ns
ns
<,
Note: For Timer Input Specification, see Figure 10.
,.
ns
400
10
TEST CONDITIONS
ns
50
,
ns
150 pF Load
8155/8156
WAVEFORMS
Read Cycle
CE (8155 )
\[-
,(
\
Jf-
~\
/
\
,(
\
OR
CE (8156 )
101M
..
X
tAD
J<-
)(
[-
~I\
H
-,(
~r-
l_ tRDE •
- tl l -
--'\
- - t RDF -
-tRD_
.
(-
-tle~
l----
Write Cycle
CE (8155)
~
DATA VALID
- tlA -
!----.tAl -
ALE
r-
ADDRESS
.
OR
CE (8156)
101M
ALE
Figure 7. 815518158 ReadlVlrlte Timing Diagrams
5-D8
t ee -
,~
~
-
~~
tel-
- . - · t RV -
8155/8156
Strobed ~np~t Mode
cw
~
£!F
a:
0
tSBF
D.
a:
0
(.)
~
en
w
~
g
INTR
(/)
(/)
c:(
a/J
RD
w
Z
a:
0
CD
(/)
0
t pHS
INPUT DATA
FROM PORT
~
c:(
cc:(
@
Strobed Output Mode
BF
STROBE
tWBF
INTR
tWI
WR
twp
OUTPUT DATA
TO PORT
Figure 8. Str~bed 110 Timing
5-09
8155/8156
Basic InPL!t M,ode
~
DATA BUS'
===-=-=-.=x. . .__________
Basic Output Mode
DATA BUS'
OUTPUT
'DATA BUS TIMING IS SHOWN IN FIGURE 7.
F~gure
9. Basic I/O Timing Diagram
LOAD COUNTER FROM CLR
I
2.
--I.
,..1
I
RELOAD COUNTER FROM CLR
I
.5
TIMER IN
'i"iMEi'iOuf
(PULSE)
TIMER 04T
(SQUARE WAVE)
~OTE',
\
\
...... (NOTE1I
__ ;..J"
...... _ _ _(NOTE')
_ _ _ _ _ ..1"
THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOI11ATIC
RELOAP MODE (M, MODE BIT·')
COUNTDOWN FROM 5 TO ,
tcvc
t, ANDtl
t,';'
t2
tTlANDtTH
320 nsec
JOnsec
80 nsec
'20 nsec
400 nsec
figure 10. Timer Output Waveform
'S-Dl0
MIN.
MAX.
MIN.
MIN.
MAX.
2
I,
-t
I
8355
ABSOLUTE MAXIMUM RATINGS·
cw
~
a:
oD..
a:
o
u
~
enw
~
g
C/)
C/)
-t
all
w
Z
a:
o
III
C/)
o
~
-t
C
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings"may cause permanent damage to the
device. This is ,a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Temperature Under Bias .•.............. O°C to +70°C
Storage Temperature ............... -65°Cto +150°C
Voltage on Any Pin
WithRespecttoGround ............... -0.3Vto+7V
Power Dissipation ............................. 1.5W
D.C. CHARACTERISTICS
(TA = o°c to 70°C; Vee = 5V
± 5%)
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
Vee = 5.0V
VIH
Input High Voltage
2.0
Vee+O· 5
V
Vec = 5.0V
VOL
Output Low Voltage
0.45
V
IoL=2mA
VOH
Output High Voltage
IlL
Input Leakage
ILO
Output
Icc
Vee Supply Current
leakag~
2.4
J,.LA
VIN = Vcc to OV
±10
pA
0.45V ~VOUT ~Vee
180
mA
10
Current
IoH = -400J,.LA
V
c(
@
A.C. CHARACTERISTICS
SYMBOL
(TA = o°c to 70°C; VCC = 5V
PARAMETER
± 5%)
MIN.
MAX.
UNITS
tCYC
Clock Cycle Time
320
ns
T1
ClK Pulse Width
, ,80
ns
T2
ClK Pulse Width
120
30
ClK Rise and Fall Time
tAL
Address to latch Set Up Time
tLA
tLC
tRO
Valid Data Out Delay from READ Control
170
ns
tAD
Address Stable to Data Out Valid
400
ns
100
ns
ns
50
ns
Address Hold Time after Latch
80
ns
Latch to READ/WRITE Control
100
ns
tLL
Latch Enable Width
tROF
Data Bus Float after READ
tCL
R EADIWR ITE Control to latch Enable
20
ns
tee
R EADIWR ITE Control Width
250
ns
100
ns
tow
Data In to WR ITE Set Up Time
150
ns
two
Data In Hold Time After WR ITE
10
ns
twp
WR ITE to Port Output
tpR
Port Input Set Up Time
50
tRP
Port Input Hold Time
50
tRYH
READY HOLD TIME
0
tARY
ADDRESS (CE) to READY
tRV
Recovery Time between Controls
tRI;lE
Data Out Delay from READ Control
400
ns
ns
ns
160
160
ns
ns
300
ns
10
ns
5-011
CLOAO = 150 pF
ns
tf,t r
0
TEST CONDITIONS
150 pF load
8355
WAVEFORMS
Figure 4. Clock SpeCification for 8355
tCYC
CLK
-\
\
/
A~,O
/
""-----_....
ADDRESS
101M
tAD
AD0-7
ADDRESS
DATA
(CE -1)'
(CE=O)
t LA -
ALE
tAL
R5
iOR
1 + - - - - - 'DW-----+I
tcc -------------~
Figure 5. ROM Read and 110 Read and Write
5-012
ir------t-----
8355
elK
Q
w
~
a:
ICE-1l. U:-E-OI
oa..
a:
o
U
~
ALE
u)
W
~
(j
o
en
en
oct
ell
w
Z
a:
Figure 6. Wait State Timing (READY 5 0)
o
In
en
o
~
oct
Q
oct
@
A. INPUT MODE
DATA"- BUS
---
--)<
-------
----------------------
B. OUTPUT MODE
GLITCH FREE
/OUTPUT
PORT
OUTPUT
~~iA*
=====)(10...._______...IX"'_____
*DATA BUS TIMING IS SHOWN IN FIGURE 3.
Figure 7. 110 Port Timing
5-D13
8755A
<<.<. . . )
·COMMENT: Stresses above those''1;~~~iJfJ
Maximum Ratings" may cause permanilnltJatrl
device. This is a stress rating only and f~;'c.·tt'wJ,.a
tion of the device at these or any other cond,'tl'o~hi II
those indicated in the operational sections of thisSRik/,.
cation is not implied. Exposure to absolute maxfrrwfn.
rating conditions for extended periods may affect devide
reliability.
ABSOLUTE MAXIMUM RATINGS·
TemperatureUnderBias .............. -10°C to +70°C
Storage Temperature ............... -65°C to +150°C
Voltage on Any Pin
.
With Respect to Ground ............... -0.5V to +7V
Power Dissipation ............................. 1.5W_
D.C. CHARACTERISTICS,
(TA
=o°c to 70°C; Vee =5V ± 5%)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High yoltage
2.0
Vee +0.5
V
VOL
Output low Voltage
VOH
Output High Voltage
IlL
Input leakage
ILO
Output leakage Current
Icc
Vce Supply Current
A.C. CHARACTERISTICS
p.A
= 2mA
= -400J.LA
VIN = Vee to OV
±10
J.LA
0.45V ~VOUT ~Vee
180
mA
V
0.45
IoL
V
2.4
10
(TA
TEST CONDITIONS
IoH
= o°c to 70°C; Vee = 5V ± 5%)
MAX.
UNITS
SYMBOL
PARAMETER
MIN.
tcvc
Clock Cycle Time
320
ns
T1
ClK Pulse Width
80
ns
T2
ClK Pulse Width
120
ns
30
ClK Rise and Fall Time
tAL
Address to Latch Set Up Time
50
ns
tLA
Address Hold Time after latch
80
ns
tLC
Latch to R EADIWR ITE Control
100
tRO
Valid Data Out Delay from READ Control
tAD
Address Stable to Data Out Valid
tLL
latch Enable Width
tROF:
Data Bus Float after READ
0
tCL
R EADIWR ITE Control to latch Enable
20
ns
ns
ns
170
ns
450
ns
100
ns
100
ns
tcc
READIWRITE Control Width
250
tow
Data In to WR ITE Set Up Time
150
ns
two
Data In Hold Time After WR ITE
30
ns
twp
WR ITE to Port Output
tPR
Port Input Set Up Time
50
tRP
Port Input Hold Time
50
tRVH
READY HOLD TIME
0
tARV
ADDRESS (CE) to READY
Recovery Time between Controls
tROE
Data Out Delay from READ Control
400
ns
ns
ns
160
ns
160
ns
300
ns
10
ns
5-D14
CLOAD = 150 pF
(See Figure 3)
ns
tf,tr
tRV
TEST CONDITIONS
150 pF load
8755A
WAVEFORMS
c
w
~
a:
oD..
a:
o
u
~
en
w
~
g
CI)
CI)
Figure 5. Clock Specification for 8755A
<
..,
w
Z
a:
oIII
CI)
o
A.. ,O
~
<
c
<
@
~
ADDRESS
:K
ADDRESS
tAD
AD()'7
)
r
ADDRESS
}·--~D
)-----(
DATA
ADDRESS
.>-
f-tll-
ALE
f
\0!-tAl_
(PROG)/CE
\~
CE
}r-
~tlA_
-'\
-~tlC_
--Jr-
tROF
I--tRDE
tow
-tRO
-
\
I-oJ
L-
~ t-two
,~
L-
tcc
I---tCltRV
Figure 6. PROM Read, 110 Read and Write Timing
Please note that ffi must remain low for the entire cycle.
This is due to the fact that the programming enable
function common to this pin will disrupt internal data bus
levels If CE1 is taken high during the read.
5-015
8755A
Input Mode
A. INPUT MODE
DATA- BUS
-
-- -
-
-)<
----- - -
Output Mode
-------------
B. OUTPUT MODE
GLITCH FREE
/OUTPUT
PORT
OUTPUT
====)<________X"'_____
~~iA- =
-DATA BUS TIMING IS SHOWN IN FIGURE 6.
Figure 7. 110 Port Timing
Figure 8. Walt ~tate Timing (READY = 0)
5-016
8755A
Q
w
D.C. SPECIFICATION FOR PROGRAMMING
a:
(TA
~
o
Q.
a:
o
o
=O.J C to 70°C; Vee =5V ±5%; Vss =OV)
SYMBOL
~
PARAMETER
enw
Voo
Programming Voltage
(during wri$e to EPROM)
g
lop
Prog Supply Current
~
MIN.
TYP.
MAX.
UNIT
24
25
26
V
15
30
mA
TYP.
MAX.
UNIT
en
en
ct
.;s
w
Z
a:
~
A.C ... SPECIFICATION FOR PROGRAMMING
o
(TA
en
=o°c to 70°C; Vee =5V ±5%; vss =OV)
~
ct
Q
ct
@
SYMBO·L.
PARAMETER
MIN.
tps
Data Setup Time
10
tPD
Data Hold Time
0
ns
ts
Prog Pulse
2
I1S
tH
Prog Pulse Hold Time
2
tpR
Prog Pulse Rise Time
0.01
2
tpF
Prog Pulse Fall Time
0-01
2
I1S
tPRG
Prog Pulse Width
A5'
50
msec
~etup
Time
5-017
ns
I1S
I1S
8755A
WAVEFORMS
FUNCTION PIN NO.
.I~.•.------
PROGRAM CYCLE
------'.~I.__
~ .!;~~;~
---VERIFY CYCLE- - - - ·......I:
.<~{
ALE
4
11
AlDO_7
12-19
A8·10
21·23
DATA TO BE
PROGRAMMED
CE
PROG/CE
~-----------------------
V OD
\J-• VERIFY CYCLE IS A REGULAR MEMORY READ CYCLE (WITH V DD
Figure 10. 87SS/87S5A Program Mode Timing Diagram
5-018
= +5V
FOR 8755A. V DD
= OV
FOR 8755.1
cw
Chapter ,6
oQ.
THE 8048 MICROCOMPUTER DEVICES
!ia:
a:
o(,)
:!!:
en
w
!i
~r
U)
U)
oCt
011
w
Z
a:
o
en
U)
o
~
oCt
C
oCt
@
The 8048 series microcomputers are single-chip 8-bit devices which have been developed by Intel to compete
in the market for low-cost, high-volume applications. This is a market where the 8080A, with its high chip
counts, does not do well. One version of the 8048, the 8748, is also likely to do exc'eptionally well in lowvolume, custom applications because it is very easy to use.
'
The 8048 looks like a one-chip 8080A with heavy' F8 influence. The F8 was the first 8-bit microprocessor to
bring the economics of low chip counts to the attention of the semicoriductor industry. It is therefore not
surprising to find an F8 influence in the 8048. (The F8has now been superceded by the 3870; both parts are described in Chapter 2.) .
,
It is intriguing to note that, in terms of general architectural organization, there are striking similarities between
the 8048 and the MCS6530 (which is described in Chapter 10).
The 8041 and 8021 are slave microcomputers of the 8048 family. On simple inspection the principal di1ference
between the '8948 ij(1d the 8041/8021 w'ould appear to be that the 8041/8021 cannot generate external
System Busses. In fact, there are non~obvious differences between the 8048 and the 8041/802'1; there are
further significant d!fferences between the 8041 and the 8021.
,.'
.
The 8048 is a simple. single-chip microcomputer that may be a stand-alone device. or part of a multi-microprocessor
configuration. As a stand-alone device. the 8048 mayor, may not have external additional logic. Thus. the 8048 is a
straightforward. low-end, low-cost microprocessor with less versatility than a device such as the 8085.
If you ~ontinue the philosophical progression from the 8085 to the 8048. you reach the 8021. This is a single-chip
microcomputer with no expansion capabilities, and very low-cost. If the 8021 exists in a multi-microprocessor configuration. then so far as the 8021 is concerned there is logic beyond'its perimeters. The fact that this logic contains
one or more microprocessors is quite immaterial to the manner in which the 802,. will be programm~d.
The 8041. in sharp contrast. is a slave microprocessor that assumes the presence of a master microprocessor 011 on~
side and extern'al logic on the other side. The 8041 thus becomes an interface and control part - which is how the
8041 should be considered. But you will observe that a large number of microprocessor support parts also act as interfaces between microprocessor. assumed to E3xist on one side. and some other logic. assumed to eXist on thE3 other
side. This is a very accurate parallel to draw. The 8041 is. in fact. a universal interface device. limited only by the speed
of the part and the amount of programmed logic that can be included in it. The 8041 can s.erve a wide variety of interface logic functions. Thus. when'ever you consider using a complex interface controller part, you should also consider using the 8041 as an alternative. Because.the 8041 is programmable. you can tailor it to meet. exactly. the requirements of the specific microprocessor on one side and specific logic on the other side, This is something you cannot do with dedicated controller parts such as floppy disk and CRT controllers. which must look generically. rather than
specifically. upon the CPU on one side and the device being controlled on the other side.
a
There is also an erasable programmable read-only memory version of the 8041; it is the 8741.
I'
•
8048 series microcomputers are summarized il'!Table 6-1.
The only support device described in this chapter is the 82431/0 Expander. In addition, the 8155, the 8355, and
the 8755 multifunction devices (which have~:'been desc~ibed in Chapter 5) can be used with 8048 family
microcomputers.
6-1
The prime source for the 8048 series rnicrocomputers is:
INTEL CORPORATION
3065 Bowers Avenue
Sa nta Cia ra. Ca Iiforn ia 95051
Second sources for the 8048 include:
ADVANCED MICRO DEVICES
901 Thompson Place
Sunnyvale. California 94086
SIGNETICS
811 East Arques Avenue
Sunnyvale;. California 94043 '
Neither of the8048 second sources are likely to have' sign,ificantProduct volumes until mid-1978,
Intersil plans to introduce a CMOS version of the 8048 ih early 1979,
The 8048 series microcomputers use 'a single +5V power supply. There are two versions of each microcomputer; one
uses a 2.5 microsecond clock while the other LJ~es 5 microsecond clock. 8048 instructions execute in either one or
two clock periods. The 8021 uses alb microqecond clock. A ~e~ version of the 8049 uses a 1 A JLsec clock, '
a
All 8048. '804~ and 8041 devices are p~'ckaged as 40-pin DI~s and ~flve TTL-compatible signals, 8021 devices are
.
'
packaged a,s 28-pin DIPs and have TTL-compatible signals,
Table 6-1. A Summaryof 8048 Series Microcomputers
ON CHIP MEMORY
R9M/EPROM
RAM
102~ROM
64
64
8048
8035
8035-8"
8748
8748-8
8049
; 8041
8741
8021
0
0
1024 EPROM
1024 EPROM
2048 ROM
1024 ROM
1024EPROM
802~
64
64
64
64
64
CYCLE
TIME
2.5p.sec
2.5p.sec
5.0 p.sec
2.5 p.sec
~.O p.sec
1024 ROM
64
64
lAp.sec
2.5 p.sec
2.5p.sec
10 p.sec
2048 ROM
64
10 p.sec
I/O PORTS
EXTERNAL
INTI;RRUPTS
TIMER
3x8 bits
1
Yes
3x8 bits
3x8 bits
3x8 bits
3x8 bits
1
1
1
Yes
Yes
Yes
Yes
3x8 bits
3x8 bits
3x8 bits
2x8 bits
lx4 bits
3x8 bits
1
1
0
0
0
1
PACKAGE
PINS
EXPANDABLE
ANALOG TO
DIGITAL
CONVERTER
28
N8
No
No
No
No
No
No
No
No
No
' No
' No
40
No
Yes
40
40
40
40
40
Yes
Yes
Yes
Yes
40
40
40
Yes,
Yes
Yes
Yes
Y~s
Yes
Yes
THE 8048, 8748,. 8049, 8749 AND 8035
,
MICROgo~~~frE~~"
For a description of an 8048, 8748, 8049, 8749, or 8035 device, read the following text; where ambiguities
may arise in your mind,:r~m~mber'these overriding rules:
..
1)
The 8049 is an 8048 with twice as much on-chip program memory. and. in newer models. higher execution speed,
are no other differences
betweenl
these
two parts.
'
There
,
, .
'
'.
2) , A~ 8035 is alJ 8048 with no on-chip program memory. There are no other differences between these two parts.
For a ~escription of an 8041,8741 or 8021 device, read the following'text, then read the specific device discussion tt,at ~ppears Ia.~er-'in this ch~Pt~r.
Functioj,~ ilT!plemented qn the tt1~e~ versions of the 8048 micr~c~mputer are illustrated in Figure 6-1. With the
exception of the 80~~, yo~ will see that complete microcomputer logic is provided within a single pac!
~
~
~
ex:
a..
~
--
A
"'I
1024 x ,8 Bits
'ROM (8048)
or EPROM
(8748)
0
DO - 07
ex:
.~ a..
0
en
::l
m
-.
Interrupt Request
.----..
System Reset
PROM/Expander strobe
CPU/Memory Separate
Read Strobe
Write Strobe
Test input or Timer output
Test or Event Counter input
-.
-
-...
~ ~
.
A
INT
,..
....
RESET
64 x 8 Bits
RAM
PROG
EA
~
XTAL1
~,
Accumulator
XTAL2
ALE
PSEN
--
......;.,
58
RO
WR
--- --.
--
. Arithmetic and
Logic Unit;
Control Unit
and Instruction
Register
Program
Status Word
,
---
"
~
ex:
0
a..
I--
Single Step
~
"
N
.<=::>
Program Memory Enable
"'V
~
I--
P20 - P27
Address Latch and Clock
f--'\
Program Counter
~
Program
Counter may
be output on
P23 - P20 plus
07 - DO
External Crystal {
.~
~
TO
T1
--
~
Counter /Timer
Figure 6-2. Functional Logic of the 8048.8049 .. 8748.
8749 and 8035 Microcomputers
6-4
Q
w
~
a:
oQ.
a:
o
o
~
en
w
~
All 8048 series microcomputers (with the exception of the 8021) have three 8-bit I/O ports.
For the 8048 series and 8049 series microcomputers, one of these ports, the Bus Port, is a
truly bidirectional I/O port with input and output strobes. Outputs can be statically latched.
while inputs are nonlatching. This means that external logic must hold input data true at Bus Port pins until the data
has been read. All eight pins of the Bus Port must be assigned either to input or output: you cannot mix input and output on the Bus Port.
Bus Port is used as the primary I/O port in a single-chip microcomputer system. In multiple-chip microcomputer
systems Bus Port serves as a multiplexed Address and Data Bus.
.
I/O Ports 1 and 2 are secondary I/O ports with characteristics that differ significantly from Bus Port. If you output
parallel data to I/O Port 1 or 2. it is latched and maintained at the I/O port until you next write data. But the only way
external logic can input data to I/O Port 1 or2 is by pulling individual pins from a high to a low level. Thus when a high
level is being output at any pin of I/O Port 1 or 2. external logic can pull this level low - and subsequently if the ~PU
reads back data from the I/O port it will read a bit value. This may be illustrated as follows:
a
g
CPU
CI)
CI)
c(
(2)
o!I
w
Z
External Logic
I/O Port
output
11110101 ----------I.~11110101
~
a:
oa1
Pull one pin low
,>--'-
CI)
0
- - 2
o
11010101
~
c(
Q
c(
CD
@
input
11010101 ..........- - - - - - - - - 11010101
External logic cannot create a high level at any pin of I/O Port 1 or 2 which is outputting a .Iow level.
Here is a summary of I/O Port 1 and 2 capabilities:
1)
You can at any time output parallel data to I/O Port 1 or 2. The data will be latched and held until the next output.
2). Individual pins of I/O Ports 1 and 2 can serve as input or output pins. When you output data to I/O Port 1 or 2. you
must output a 1 bit to any input pill. This may be illustrated as follows:
Data Output
X 1 1 X X 1 X 1 (x.;. 0 or.1)
7
6
5
4
0
I
1.1 01
0
I I
3)
--+
3
2
1
0
0
I
0
I
I I I I
~Bit
No.
~ I/O Port 1 or 2 (0 = Output. I = Input)
External logic writes to input pins of I/O Ports 1 and 2 by leaving low levels alone. and by pulling high levels low.
Figure 6-3 illustrates logic associated with each pin onto Ports 1 and 2 in all 8048 series
microcomputers.
Output data is latched by a Ootype flip-flop.
8048 SERIES
I/O PORT
PIN LOGIC
The Q and Q outputs of the Ootype flip-flop control a pair of gates on either side of the pin connec. .
tion. To provide fast switching times in 0-to-1 transitions. a relatively low impedance (~5K ohms) is switched in for approximately 500 nanoseconds whenever a 1 is output.
6-5
+5V
+SV
ORl.ANl--------------~
=50Kfl
INTE:RNAl ---4~"" D
Q 1-......---4
BUS
D
FLIP
FLOP
I/O PIN
PORT 1 AND 2·
QI---+-------"""1
elK
WRITE -~--f---~
PULSE
__- - -...
IN--------....I
INPUT BUFFER
Figure 6-3. 8048 I/O Ports 1 and 2 Pin Logic
Pins are continuously pulled upto +5V through a relatively high impedance (-50K ohms). When a 0 is output to the
D-type flip-flop. a low impedance (-3K ohms) overcomes the pull-up and provides TTL current sinking capability.
When a 'pin of I/O Port 1 or 2 is at a high level. external logic can sink the 50Kfl. pull-up. But when the pin is at a low
level. external logic cannot overcome the low impedance to ground; thus it cannot pull the pin up to a high level.
By placing an input buffer between the pin and the switching gates. pin logic allows the CPU to read current levels induced by external logic - but only while external logic is connected to the pin.
The buffer connecting the Q output of the D-type flip-flop to the D input is present to enable 8048 instructions that
mask I/O port data.
Later in this chapter we will iook at I/O ports in more detail. showing programming and design examples.
6-6
8048, 8748 AND 8035 MICROCOMPUTER PROGRAMMABLE REGISTERS
The 8048 series microcomputers have an 8-bit Accumulator, a 12-bit Program Counter and 64 bytes of
scratchpad memory. Scratch pad memory may be visualized either as read/write memory or as general purpose
registers.
c
The Accumulator, Program Counter and scratch pad memory may be illustrated as follows:
w
~
a:
o
D.
8 Bits
~
a:
o
CJ
~
enw
~
(3
o
CI)
CI)
c(
a!I
w
Z
02
R3
R4
03
General Purpose
04
Registers
R5
05
R6
R7·
06
a:
50 {
51 {
o
01
R2
CI)
oIII
00
RO1
Data Counters { R
09
OA
OB
~
c(
OC
cc(
52 {
@
53 {
00
OE
OF
'-0
11
12
54 {
55 {
5tack
13
14
56 {
15
16
57 {
17
18
Data Counters { RO'
Rl'
R2'
R3'
1B
Alternate General
R4'
1C
Purpose Registers
R5'
10
19
1A
R6'
1E
R7'
1F
20
·••
~'O
••
l3eneral 5cratchpad
3E
3F
~-t-t-"I-~I~-t-t-t-"I-..,..-r-..,.-"I
8-bit Accumulator
12-bit Program Counter "'........_ ' - - - " _..........._
6-7
............_
.............................
The Accumulator is the principal conduit for all data transfers. The Accumulator is' always one source and the
destination for Arithmetic or Boolean operations involving memory or registers.
Two sets of eight scratchpad bytes serve as secondary registers. At any time one set of general purpose registers
is selected while the other set of general purpose registers is not selected.
The first two general purpose registers of each set, RO and R1, act as Data Counters to address scratchpad
memory and external data memory. Thus you address scratchpad memory using implied memory addressing via
general purpose Register RO or R1: you can address anyone of the 64 scratchpad bytes. including the general purpose
registers. or even the Data Counter register itself.
In between the two sets of eight general purpose registers there is a 16-byte stack. The Stack Pointer is maintained in the Program Status Word: therefore we will defer our discussion of stack operations until we look at status.
8048 SERIES ADDRESSING MODES
The 8048 series microcomputers separate memory into program memory and data memory.
Without resorting to complex expansion schemes, you are limited to a maximum of 4096
program memory bytes and 320 data memory bytes.
8048 SERIES
MEMORY
SPACES
The 8048 and 8748 microcomputers have 1024 bytes of program memory on the CPU chip. The
8049 microcomputer has 2048 bytes of program memory on the CPU chip. More program memory. if present. must be
external to the CPU chip. The 8035 microcomputer has no on-chip p'rogram memory: it requires all program memory to
be external.
All 8048 series microcomputers provide 64 bytes of read/write data memory on the CPU chip. In addition. 256 bytes of
external data memory may be addressed. The external data memory space must be shared by external data memory and any external 1/0 ports - that is to say. I/O ports other than the microcomputer's own three I/O ports or 8243
Expander ports.
8048 series microcomputer address spaces and addressing modes are illustrated in Figure 6-4.
Let us first examine program memory addressing.
8048 SERIES
A single address space is used to access all of program memory. In the normal course of events
program memory is addressed via the 12-bit Program Counter. The high order Program
PROGRAM
Counter bit is isolated in Figure 6-4 because when the Program Counter is incremented only
MEMORY
ADDRESSING
bits 0 through 10 are affected. You must execute special instructions to modify the contents of
the high order Program Counter bit. Program memory is therefore effectively divided into two
memory banks. each containing up to 2048 bytes of program memory. You cannot branch. via Jump-on-Condition instructions. from one program memory bank to the other. nor can instructions stored in one program memory bank
directly access the other. You can switch completely from one program memory bank to the other by preceding a JMP.
CALL or RET instruction with a SEL MB instruction.
Two types of program memory addressing are available: you can read data from program memory and you can
execute Jump instructions.
You can unconditionally jump anywhere within the currently selected program memory bank: this may be illustrated as
follows:
These bits
replaced
PC
~~--------~~~------~"-
PROGRAM
MEMORY
Arbitrary
Memory
Address
010A
11000100
10111010
010B} JMP instruction
object code
010C
0100
06BA
06BB
New Address
06BC
06BO
6-8
Program Memory
0000
On 8048, 8748
and
8049 Chip
c
w
~
a:
oa..
Memory
Bank 0
03FF
0400
a:
o
u
I
I
I
~
enw
07FF
g
0800
11 : 10
~
,
r
On 8049
Chip
IA
9
8
7
6
5
4
3
2
I I I
........
0
I PC
S
CI)
CI)
~
#'"
~
w
Z
a:
o
Memory
Bank 1
OBFF
OCOO
al
CI)
o
~
~
c
OFFF _ _ _ _ _--'
~
@
00 ...- - - -.....
7
6
4
3
2
0
I I I I I I I I I:~
External
Data Memory
FF _ _ _ _ _..... /
00 ...- - - -.....
On Chip
Scratchpad
Memory
3F _ _ _ _ _ _J
A = Accumulator
PC = Program Counter
RO, R 1 are general purpose registers
in scratch pad memory
Figure 6-4. 8048 Series Microcomputers' Memory Addressing
6-9
Thus the JMP instruction stored in program memory bytes 010B16 and 010C16 causes program execution to jump to
location 06BA16.
You can also jump using a form of paged. indirect addressing. where the Accumulator points to an indirect address
stored in the current page of program memory. This may be illustrated as follows:
Arbitrary
Memory
Addresses
Program
Memory
t - - - - - I 013A
t - - - - - I 0138
Accumulator _ _......r------::::::::=--I'1-~C~8~..J 013C
I---...-.t
t - - -........
Program
Counter
I
1
~._
I
•
I
I
0130
013E
3 ~~::
~
58
....._ _...
~
I
I
I
I
0150
01CA
___J----~ 01C8
t-----f
...-JMPP@A
015C
~Jump here
01CC
01CO
All conditional Jump instructions allow you to branch within the current page of program memory only. This may be illustrated as follows:
Arbitrary
Memory
Address
Program
Memory
~~__--_~..II------fl ~ ~ _
P
I
I
J,mp he"
I . I
I
~
rogram A
AD
Counter ..._~._ _--'.
I
OAA8
I---...-.t
F6
OAAC}
I----...-.t
JC instruction
-----------t__12~C~OAAO
I---...-.t
condition is rriet
6-10
OAAE
You cali ~ead data from program memory, but there are no instructions which allow you to write data to program
memory. Instructions (other than immediate instructions) that read data from program memory use paged, implied addressing. There are two forms of paged, implied programming memory addressing; they may be illustrated as
follows:
.
cw
Arbitrary
Memory
Address,
a:
01AA
u
MOVP A,@A01ASI---_A_3_-t
~
a:
oa..
o
Program
Memory
Program
Memory
Program Counter
1------1
1----1
E3
1-------1
~
u)
w
1-----1
1-----1
~
U
o
en
Arbitrary
Memory
Address
01AA
01AS MOVP3 A,@A
01AC
01AD
en
oCt
clJ
013E
w
Z
o13F 1----.;.4;..;A_-I
o
0140
a:
III
en
1------1
1-----1
4A
1-----1
033E
033F
t - - - - - I 0340
1------1
o
~
oCt
oCt
C
@
The illustration above compares execution of the MOVP and MOVP3 instructions. These are the two instructions which
allow you to read a byte of data from program memory into the Accumulator. Both instructions load 4A into the Accumulator, as illustrated above.
When the MOVP instruction is executed, the program memory address is formed by concatenating the high-order four
bits of the Program Counter with the contents of the Accumulator:
Program Counter (X
' P
Q
f
When the MOVP3 instruction is executed, the program memory address is computed by appending the Accumulator
contents to 0011:
~ Accumulator
I
I
3
I
I
I
I
I
P
Q
I} Program Memory Address
Thus the MOVP instruction loads into the Accumulator the contents of a program memory byte within the current program page. The MOVP3 instruction loads into the Accumulator the contents of a byte from program memory page 3.
Note carefully that paged addressing of program memory carries with it the usual page boundary problems. The
program memory addressing modes which replace th·e low-order eight Program Counter bits keep the four high-order
Program Counter bits - after the Program Counter has been incremented.
.
Refer back to the JMPP @A instruction. This instruction is illustrated as being stored in program memory location
015B16. But suppose this instruction were stored in memory location 01 FF16; then after the JMPP ins~ruction is
fetched, t~e Program Counter will no longer contain 01 FF16, it will contain 020016. Now instead of jumping to program memory location 01CB16, you would jump to program memory location 02CB16.
This page boundary problem is common to all microcomputers that use absolute paged addressing. For a complete discussion of this problem refer to Volume I - Basic Concepts, Chapter 6.
6-11
Note that the 8048 has no instructions which write into program memory. If you want to write into program
memory you must have external logic which overlaps external program and data memory.
Let us now look at data memory addressing. First of all. notice that scratchpad memory and external data memory
have overlapping address spaces. Separate and distinct instructions access scratchpad memory as against external
data memory. External data memory does not represent a continuation of scratchpad memory. For example. there will
be memory bytes with addresses in the range 0016 through 3F16 in the scratchpad and in external data memory.
Implied memory addressing is the only addressing mode available to you when accessing data memory.
Instructions that access scratchpad memory take the scratchpad memory byte' address from the low-order six bits of
General Purpose Register RO or R1.
Instructions that access external data memory take the external data memory address from all eight bits of General Purpose Register RO or R1.
The eight general purpose registers within scratchpad memory can be addressed directly. We could argue that this
constitutes a limited scratchpad memory direct addressing capability: but in order to remain consistent with other
microcomputers described in this book. we will classify these direct accesses of general purpose registers as registerto-register operations rather than direct addressing of data memory.
A PROGRAM MEMORY MAP
The instruction set of the 8048 microcomputer is designed to allocate the on-chip program memory as follows:
3FF
} Data Tables
300
2FF
200
1FF
} Pro9"""
100
OFF;
:
.
007 ~ l
interrupt calls subroutine
r Ti~~r
ongmed here
003
000
~
} External interrupt calls subroutine
origined here
t
f
R~s~art calls subroutine
ongmed here
The MOVP3 instructions assume that the 256 byt~s of program memory with addresses 30016 - 3FF16 have been set
aside to hold tables of constant data.
Interrupt logic (which is described later) uses low memory locations O. 3 and 7 to origin interrupt service routines that
will be executed in response to a restart. an external interrupt or a timer interrupt. Jump instructions will normally be
located in these low program memory locations.
6-12
8048 SERIES STATUS
8048 series microcomputers have an 8-bit Program Status Word which may be illustrated as follows:
- - - - - - - - - - - - T h e s e four bits saved on Stack
~
j-'
cw
7
~
a:
6
5; 4: j
o -:4-- Bit
2
No.
r--P--~~~--~~--~~
Program Status Word
~
a:
o
(J
~
en
w
' - - - - - - - Stack Pointer
bank select
o = Scratch pad bytes 0-7 selected
1 = Scratch pad bytes 18-1 F selected
~
'----'---~----- Register
g
en
en
' - - - - - - - - - - - - - FO, software flag
' - - - - - - - - - - - - - - - A C , Auxiliary Carry
C, Carry
ct
clJ
w
Z
L----------______
a:
o
III
en
o
~
ct
C
ct
@
C and AC are the standard Carry ~nd Auxili~ry Carry statuses as defined in Volume I and used throughout this
book.
FO is a flag ~hich you set or reset using apprd~riate Status instructions. A conditional Jump instruc!ion tests the
level of Fa. Fa is not connected to external logic and cannot be modified or tested by external logic.
BS identifies which set of gen~~al purpose registers is currently selected. If BS is 0, then scratchpad byte~ a
through 7 are serving as general purpose registers. If BS is 1, then scratchpad bytes 1816 through 1F16 are serving as
general purpose registers.
The low-o~der three Pro~ram Status W~rd bits serve as a Stack Pointer. The 16 Stack bytes are treated as eight
16-bit registers, with the current top of Stack identified by the three low-order Program St~tus Word· bits.
A subroutine Call instruction pushes the Program Counter contents and the four high-order Program Status
Word bits onto the Stack as follows:
Program
Counter
I
P
Scratchpad
Memory
o .4--Bit No.
11
P
P
P
Q
Q
,0
Q
R
R
R
R
I
QQQQRRRR
SSSSPPPP
o .--SitNo.
7
PSW
Is
S
S
S
X
X
Lowest
Scratchpad
Address
jxxx
xxx+ 1
xi
7
In the illustration above. P. Q. R. S and X represent any binary digits.
6-13
o ...-Bit No.
T
Highest
Scratch pad
Address
Observe tHa~ the begirlhing of the Stack has the lowest scratchpad address. The order in which Program Status Word
.
and Program Counter contents are pushed onto the Stack is illustrated above. Here is a specific case:
000
PSW
{
001 ~
PC
Fl!1I
07
Full
08 ....-Beginning of Stack
Full
09
Full
OA
4A
OB
72
oc·
010 ~
12
-------G1
OD
<
OE
OF
100
10
;,
: !'
You need to know the exact order ih which data is stored Qn the Stack since the Stack is also accessible as general
scratch pad memory.
.
There are two ReHjrn-from~Subroutine instructions; one restores Program Counter contents only. the other restores
. Program Counter ~~d Program Status Word contents.
Since the Stack has eight 16-bit registers. subroutines may be nested eight deep. If you are using interrupts. thEm the
combined t6tal G,t sutHbutine nesting levels on either side of the interrupt must sum to 7 or less. For example. if the interrupt service' routine nests subroutines .t6 a maximum level of 3. then non-interrupt programs cannot nest
subroutines to a level greater than 4. The interrupt itself requires one Stack location.
8048 SERIES MICROCOMPUTER OPERATING MODES
8048 series microcomputers can operate in a variety of modes. Many signals serve more than one function, depending on the operating mode.
. ,
.
In order to clarify this potentially confusing' subje'ct, w'e will summarize 8048 series operating modes in the
para'graphs below, then we will summarize' deVice signals; these two summaries are followed by an in-depth
anaiysis of operating modes, illustrating timing and signal fUhctions.
IntEnnal execution'mode is the simplest case; .the _8048 ~eries microcomputers normally
operate in Internal Execution mode, at which time they execute programs without accessing external program memory or data memory. All iriformatio~ transfer with external logic occurs via. I/O ports or control signals. The 8035. having no i'nternal program memory. cannot operate in Internal Execution mode.
Expandable 8048 series microcomputers can access e)(ternal program and data memory. Having
exter.nal,program memory and/or data memory causes the ri1icroco~puter to output additional
control signals which identify extern'al program and data memory accesses. This is External
Memory Access mode. Memory addresses are output via the Bus Port and four pins of I/O Port 2;
bidirectional data transfers occur via the Bus Port. This may be illustrated as follows:
P20 - P23
....
.
8048
. 8748
8035
,;.
...
DBO - DB7
Address Bus
Jo..
}
) Data Bus
..
-;,
..,.
:.
6-14
RD
WR
PSEN
ALE
} Control B"
8048 SERIES
INTERNAL
EXECUTIOr,;
MODE
8048 SERIES
EXTERNAL
MEMORY
ACCESS MODE
External Memory Access mode represents the simplest case for the 8035 microcomputer. which has no on-chip program memory.
cw
The 8048 series microcomputers can be operated in Debug mode. In Debug mode the CPU is
disconnected from its internal program memory. All program memory accesses are deflected to
external program memory. This may be iliustrated as follows:
8048 AND
8748 DEBUG
MODE
t-
<
a:
0000
0
0.
a:
0
0
~
enw
t-
<
Internal
Program
Memory
External
Debug
Memory
(3
0
CI)
CI)
<
-
""
w
a:
03FF
..
Z
0
III
CI)
0
0400
:!!
c<
<
External
Program
Memory
@
OFFF
Since the 8035 has no internal program memory. it is always in "Debug mode."
You will use Debug mode to test microcomputer systems built around an 8048 series microcomputer. Typically. special
purpose test and verify programs will be maintained in external debug memory.
Single stepping is not really a mode, but is worth mentioning in connection with Debug
mode since it is a powerful debugging tool. In any of the operating modes you can apply a
Single Step signal (SS) which halts instruction execution following the next instruction fetch. This
allows you to execute programs one instruction at a time in order to locate errors or gain a better
understanding of event sequences.
The 8748 microcomputer contains Erasable Programmable Read Only Memory (EPROM). In
Programming mode you can program the EPROM.
Finally .. there is a Verify mode. In Verify mode you can read the contents of internal or external program memory as data. Verify mode is used in conjunction with Programming mode
to test data written into EPROMs. Verify mode can also be used on its own to examine the contents of program memory for any 8048 series microcomputer.
8048 SERIES
SINGLE
STEPPING
8748'
PROGRAMMING
MODE
8048 SERIES
VERIFY MODE
8048 SERIES MICROCOMPUTER PINS AND SIGNALS
Figure 6-5 illustrates pins and signals for the 8048 series microcomputers. We will briefly summarize functions
performed by signals before discussing how signals are used in different modes.
DBO - DB7 serves both as a bidirectional 1/0 port and as a multiplexed Address and Data Bus. When no external
data or program memory accesses are occurring. OBO - DB7 serves as a simple bidirectional I/O port or latch. During
external program or data memory accesses. DBO - DB7 serves as a bidirectional Data Bus as well as outputting the loworder eight bits of all memory addresses. Data inputs are not latched in bidirectional mode. External logic must hold input signal levels until the CPU has read input data.
6-'5
TO
XTAL1
XTAL2
RESET
SS
INT
EA
AD
PSEN
WR
ALE
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
(GND) VSS
1
2
..
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
8048
8748
8035
VCC (+5V)
40
.T1
39
P27
38
37 ...t--~~26
36 ...t--~P25
P24
35
34 .....1--~P17
P16
33
32 .....1--~P15
31 .......__~P14
30 .....I--~ P13
P12
29
28 .......--~P11
27 ....1--~P10
26
VDD
PROG
25
24 .....I--~ P23
P22
23
.~2 ....1--~P21
21
P20
PIN NAME
DESCRIPTION
TYPE
DBO - DB7
Bidirectional I/O port, Data Bus and
low-order eight Address Bus lines
I/O Port 1
..
I/O Port 2. P20 - P23 aiso serves as four \
high-order Address Bus lines
External clock signal and address
iatch enable
Data merllory read control
DatcLmemory write control
External program memory read control
External program memory access
Single step control
Interr·upt request
Test input, optional clock output
a~d. Program/Verify mode select
Test input, optional event counter input
System reset and EPROM address latch
Ground
+5V
+ 25V to,program 8748. + 5V standby·
for 8048 RAM
+ 25V input to program 8748. Control
output for 4-bit I/O
External crystal connections
Bidirectional, tristate
pio - P17
P20 - P27
ALE
fill
WR
PSEN
EA
SS
INT
TO
T1
RESET
VSS
VCC
VDD
PROG
XTAL1, XTAL2
Ouasibidirectional
Ouasibidirectional
Output
Output
Output
Output
Input
Input
IrJput
Bidirectional
Input
Input
Bidirectional
Figure 6-5. 8048. 8748 and 8035 Microcomputer Pins and Signals
6-16
P10 - P17 and P20 - P27 support I/O Ports 1 and 2, respectively. We described the characteristics of these two 1/0
ports earlier in this chapter. During external accesses of program memory the four high-order address lines are output
via P20 - P23.
Q
w
~
o
D.
ALE is a control signal which is pulsed high at the beginning of every instruction execution machine cycle. This
signal may be used as a clock by external logic. During external memory accesses. the trailing edge of ALE strobes
memory addresses being output.
a::
RD is a control signal which is pulsed low to strobe data from external data memory onto the Data Bus ..
a::
WR is a control signal which is strobed low when external data memory is to read data off the Data Bus.
o
PSEN is a control signal which is strobed low when external program memory is to place data on the Data Bus.
en
w
External logic inputs EA high in order to separate the CPU from internal program memory and force the microcom.
puter into Debug mode.
U
o
en
en
SS is input low in order to stop instruction execution following an instruction fetch: this allows you to singie step
through a program.
o
~
~
oct
~
w
Z
a::
m
o
en
o
~
oct
Q
oct
@
INT is the input for external interrupt requests. If the interrupt is enabled. a low input at INT causes a subroutine call
to program memory location 3 when the current instruction finishes execution.
TO is a test input which may be sampled by a conditional Jump instruction. TO is also used while selecting External
Program mode and Verify mode. The internal CPU clock signal can be output via TO.
T1 is a test input which can be sampled by a Jump-on-Condition instruction. T1 can also be used to input a signal
to Counter/Timer logic when it is serving as an event counter.
. RESET is a standard system reset input signal. The normal RESET signal should be output from
an open collector or active pUll-up:
8048,8748
AND 8035
RESET
~Vcc
~
1K
------------~~------------~l~------RESIT
The power-on RESET should be generated as follows:
r-----------~~C~----------~~----------_o~------RESIT
1Kil
::r:
1p.F
10V
There is an internal pull-up resistor which. in combination with an external 1~F capacitor. generates an adequate internal RESET pulse. If the RESET pulse is generated externally. then it must be held below 0.5V for at least 50 milliseconds.
This is what happens when you reset an 8048 series microcomputer:
1)
The Program Counter and the Program Status Word are cleared. This selects register bank 0 and program memory
bank O. Also. the first instruction executed following a Reset will be fetched from program memory location O.
2)
The Bus Port is floated.
3)
1/0 Ports 1 and 2 are set to Input mode.
4)
External interrupts are disabled.
5)
The counterltimer is stopped and TO is disconnected from the timer.
6)
The timer flag and internal flags F1 and FO are cleared.
6-17
An external crystal, if present. is connected across XTAL 1 and XTAL2. Typically a 6 MHz crystal will be used. You
can input a clock signal directly to XTAL 1. If you do. the input clock signal should have a frequency in the range of 1
MHz to 6 MHz. or 11 MHz for the 8049.
The 8048 series microcomputers use power supplies in a number of interesting ways.
Vee is the standard +5V power supply. VSS is the standard ground connection.
VDD is .an additional +5V standby power supply. This standby power supply will maintain the contents of
scratchpad memory when all other power has been removed. Typically VDD will be connected to a battery so that
when the system is powered down data can be preserved in scratchpad memory (8048 .. 8035l and 8049 only).
The 8748 and 8749 microcomputers use VDD and PROG in order to program the EPROM. While programming the
EPROM. a voltage of +25V is input at VDD. +25V pulses lasting 50 milliseconds are input at PROG. A single byte of
program memory will be written during a Single PROG +25V pulse.
PROGserves as a control strobe output to the 8243 Input/Output Expander during the execution of instructions
that reference the Expander ports. This function of PROG is described in more detail later in this chapter. when we describe the 8243 I/O Expander.
8048 SERIES TIMING AND INSTRUCTION EXECUTION
Let us begin our detailed analysis of 8048 series microcomputer operations by looking at basic instruction timing.
A master clock signal must be input via XTAL 1, or the clock signal may be generated internally by connecting a
crystal across XT Allor XT Al2. A 6 MHz crystal is recommended. This clock signal is divided by 3 to generate a
master synchronizing 2 MHz signal which is used throughout the microcomputer system. You can output this 2
MHz clock signal via the TO pin.
All -8 versions of 8048 series microcomputers operate at half speed; they use 3 MHz crystals and generate a 1
MHz master synchronizing signal.
InstriJctions execute in machine cycles. Every machine cycle has five clock periods.
Using a 2 MHz clock signal. therefore. each machine cycle will last 2.5 microseconds. Instructions execute in either one or two machine cycles.
INTERNAL EXECUTION MODE
8048 SERIES
MACHINE
CYCLES AND
CLOCK PERIODS
Figure 6-6 illustrates timing for the simplest case - execution of a single machine cycle instruction accessing internal program or data memory only. The only signal change seen beyond the microcomputer
chip itself is the ALE pulse - and the elK Signal. if you elect to output it via TO. The events which occur during each
clock period are illustrated in Figure 6-6; but remember. these operations are internal to the microcomputer. They are
beyond you r access or control.
Figure 6-6 also illustrates timing for instructions that execute in two machine cycles. but access only program and/or
data memory internal to the microcomputer chip. Once again external logic sees ALE. and optionally elK.
6-18
MCl
MCl
Tl
T5
Tl
T5
c
w
~
II:
oa..
(TO) ClK
II:
o(.)
~
ALE
en
w
~
<
(3
oCI)
Output instruction address
Increment PC,
Execute instruction
CI)
<
~
w
Decode instruction
Input instruction
Z
II:
oaI
Decode instruction
CI)
o
~
<
C
Figure 6-6. Execution of 8048 Single Machine Cycle Instructions
without any External Access
icept Resed are disabled until an RETR instruction is executed. Within an Externaior Timer interrupt
service routine you cannot'enable interrupts under program control. This maybe a problem if you are using the
timer and external interrupts in timer sensitive applications. If execution time for an external interrupt's service routine
extends over more than one counterltimer time out. then you will fa!! to detect one or more time outs. The simplest way
of resolving this problem is to make sure that your External interrupt 'service routines are very stiort - executing in 75%
of the counterltimer interval. or less. If this is not feasible. then you must monitor the counterltimer by testing its time
out flag rather than by using counterltimer interrupt logic. You can execute the JTF conditional Jump instruction at
frequent intervals within the main program and interrupt service routines. thus catching time outs irrespective of when
" "
,
they occur:
You cal"! re-enable interrupts within an interrupt service routine by executing a dummy RETR instruction. Here is
an appropriate instruction sequence:
START OF INTERRLJPT SERVICE ROUTINE
CALL
EN .
EN
ENAB
I
TCNTI
;RE-ENABLE INTERRUPTS
END OF INTERRUPT SERVICE ROUTINE
ENAB
RETR
En~bling i"terrup~s within a service routine, as illustrated above, is not recommended in' an 8048 microcomputer
system.
Two problems need to be resolved when using external interrupts in an 8048 series microcomputer system: an
interrupt acknowledge must be created, and in muitiplf! interrupt configurations we must be able to identify the
interrupting source. '
8048 series microcomputers have no interrupt acknowledge signal. An interrupt acknowledge signal must be created;
otherwise external logic does not know when to remove its interru'pt request. And if the interrupt request remains after
an RETR instruction executes. the interrupt will be reacknowledged. The only straightforward way of acknowledging an interrupt is to assign one of the I/O port pins to serve as an interrupt acknowledge signal. The extern'al interrupt service ro~tine will begin by outputting an appropriate low pin signal. Here is one possibility: '
ANL
ORL
P1.#7FH
P1.#80H
;RESET PIN 7 OF I/O PORT 1 LOW
;SET PIN 7 OF I/O PORT 1 HIGH
Here. the output at pin 7 of
Va Port 1 is a low pulse with a duration of two machine cycles (5.0 microseconds).
But remember. if you us~ an
I/O operations, '
!f0 port pin as an interrupt acknowledge. you cannot use the same pin to perform standard
6-28
lACK
(p17)
IACKO
P10
cw
.------+------+-----~------~----~------~----~~~17
9318
or
74148
!ia:
oQ.
a:
10
o(J
!:
P11
P12
en
w
!i
g
(/J
(/J
<
01:1
w
Z
a:
o
In
(/J
o
t----------!~ INT
to CPU
~
<
c
<
@
Figure 6-13. An Eight-Device Daisy Chained Interrupt Request/Acknowledge Scheme
If there are many external devices which can request interrupt service. then the most effective way of handling multiple
interrupts is via a daisy chain. Daisy chain logic has been discussed in Volume I - Basic Concepts. The acknowledged
device in the daisy chain must create a device code that is input to an I/o port. Figure 6-13 illustrates a scheme
whereby eight devices in a daisy chain may request interrupt service, and upon being acknowledged, the
selected device will input a unique code to I/O Port 1. The high-order bit of I/O Port 1 serves as an interrupt
acknowledge. I/O Port 1 bits O. 1 and 2 receive as inputs a 3-bit code identifying the acknowledged device.
.
The daisy chain logic in Figure 6-13 is created using a chain of eight AND gates and eight NAND gates. The AND g~tes
are chained in order of priority. with INTO h'aving the highest priority and INT? having the lowest priority. The first
NAND gate receives as its inputs INTO and the acknowledge signal output via pin? of I/O Port 1. Subsequent NAND
gates receive as their inputs an interrupt request signal. the acknowledge signal and the output of the previous AND
gate. The output of each NAND gate becomes an interrupt acknowledge signal which is low-true. Thus in Figure 6-13
there are eight low-true interrupt requests. represente~gnals INTO through INT? and there are eight low-true interrupt acknowledges. represented by IACKO through lACK? Each external device capable of requesting an interrupt
must output a low-true INTn which it removes upon receiving a low-true IACKn. For device 3 this may be illustrated as
follows:
'
------~_\--------;j
I
The eight interrupt request signals INTO through INT? are input to an AND gate. The AND gate generates a master lowtrue interrupt r.equest. INT. If anyone or more of the INTn signals are low. then the AND gate will output a low INT.
The eight interrupt acknowledge signals IACKO - lACK? are input to an 8-to-3 Decoder. The 8-to-3 Decoder will receive
seven high signals and one low signal. The one low signal will be identified by the decoder 3-bit output which is
transmitted to pins O. 1 and 2 of I/O Port 1.
6-29
This then is the event sequence associated with an interrupt request:
1)
INT is input low to the 8048.
2)
The interrupt is acknowledged by the CPU. which branches to an interrupt service routine.
3)
The first instruction of the interrupt service routine outputs a low level via pin 7 of I/O Porr1.
4)
The interrupt ser~ice routine receives back. via pins O. 1 and 2 of I/O Port 1. the device code for the acknowledged
device. You must make sure that the program being executed gives external logic time to return this code. You
may have to insert No Operation instructions to create the necessary time delay.
5)
A high level is output via pin 7 of I/O Port 1.
6)
Using the code input via pins 0.1 and 2 of I/O Port 1. branch to the appropriate interrupt service routine.
Here is the initial instruction sequence required by the logic of Figure 6-13:
ORG
3
;START OF INTERRUPT SERVICE ROUTINE
JMP
EXTINT
ORG
ANL
NOP
IN
ORL
ANL
JMPP
EXTINT
P1.#7FH
. A.P1
P1.#80H
A.#7
@A
;SET I/O PORT 1 PIN 7 LOW
;ALLOW SETTLING TIME
;INPUT PORT 1 CONTENTS
;SET I/O PORT 1 PIN 7 HIGH
. ;CLEAR ALL ACCUMULATOR BITS BAR O. 1 AND 2
;JUMP TO IDENTIFIED INTERRUPT SERVICE ROUTINE
Let us examine the interrupt service routine begInning instruction sequence illustrated above.
When an 8048 series microcomputer is initially reset. all I/O port pins output high levels. Thus you do not have to in~
itialize pin 7 of I/O Port 1 to a high level.
We actually identify one of eight device interrupt service routines by creating a 3-bit code in bits 1. 2 and 3 of the Accumulator. We then perform an-indirect Jump. This Jump instruction will branch to a location on the current page of
program memory; the address is fetched from the location in the current page addressed by the Accumulator contents.
We illustrated this addressing technique earlier in the chapter.
Given the instruction sequence illustrated above. the first eight program memory locations on the same page as the
JMPP instruction must be set aside for eight addresses; these are the starting addresses for the interrupt service
routines. This may be illustrated as follows:
.
-
EXTINT
ORG
DB
DB
DB
DB
DB
DB
DB
DB
ANL
#0300H
ISO
IS1
IS2
IS3
IS4
IS5
IS6
IS7
#7FH
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;ADDRESS OF INTERRUPT SERVICE
;SET I/O PORT 1 PIN 7 LOW
ROUTINE
ROUTINE
ROUTINE
ROUTINE
ROUTINE
ROUTINE
ROUTINE
ROUTINE
0
1
2
3
4
5
6
7
The daisy chained interrupt scheme discussed above can also be implemented using the circuit in Figure 6-14.
The advantage of this circuit is that it requires fewer chips than the circuit of Figure 6-13. As far as the 8048
program is concerned, however, the two circuits are identical.
'
The INT and device code inputs are generated in exactly the same way. However. an eight-line-to-three-line priority encoder (9318 or 74148) replaces the network of AND gates. As the function table for the encoder shows. the device code
output on lines A2. A 1 and AO is that of the highest priority request. The CPU enables the code outputs by sending the
acknowledge signal.
-6-30
IT
iAcKIP171
cw
!;i
a:
a:
GiA
ii,
CiS
,~
16
rue
EO
Gl
~
~
iNTi
jj
CJ
~
YO
745138
or
or
74148.
74LS138
i2
INT5
INT6
INT7
o
9318
14'
INT3
o
a.
'---
iNTo
C
B
A
A2
IT
iO
AI
AO
enw
VI
Vi
Y3
Y4
Ys
Ys
Y7
!;i
g
-
...
'---
en
en
.
'---
<
.---
~
G/J
w
Z
......J
a:
Pl0
Pl1
P12.
iNT
to CPU
o
III
en
o
~
<
c
c(
@
74LS138. 745138
9318. 74148 FUNCTION TABLE.
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE
Gl
G2°
C
B
A ,YO
X
H
L
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
H
H
L
H
H
H
L
L
L
L
L
L
L
L
OUTPUTS
INPUTS
SELECT
L
H
H
H
H
L
H
H
om = G2A v G2a
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
L
VI Vi Y3 Y4 Ys Y6
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H = high level.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
'H
H
H
H
H
H
H
L
H
H
H
L
H
H
H
L = low level.
y:; B iO i1 12 i3 i4 is 16 i7
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
A2
AI
AO
Gs
EO
H
L
H
H
H
.H
H
H
H
X
X
X
X
X
X
X
X
H
H
H
,H
H
X
X
X
X
X
X
L
H
H
H
X
X
H
X
X
H
X
X
H
X
L
H
L
H
H
L
L
H
L
H
H
H
L
L
X
L
H
L
H
H
H
H
H
H
H
X
X
X
X
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
L
X
X
X
H
X = irrelevant
Figure 6-14. A Low Chip Count Implementation of an Eight-Device Daisy Chained
Interrupt Request/Acknowledge Scheme
In Figure 6-13. a network of NAND gates generated the low-true interrupt acknowledge signal to inform the appropriate device that its interrupt was being serviced. In Figure 6-14. a three-line-to-eight-line decoder (745138 or 74LS138)
translates the device code output by the encoder and sets the corresponding acknowledge line low. as is shown in the
function table for the decoder.
Connecting the enable inputs as shown prevents spurious acknowledgements or phantom device codes. provided that
the CPU gives the external devices time for response and propagation delay.
6-31
THE 8048 MICROCOMPUTER SERIES
INSTRUCTION SET
Table 6-2 summarizes the instruction set for the 8048 series microcomputers. Instruction object codes and timing are given in Table 6-3. This instruction set reflects the specific architecture of 8048 series microcomputers. For example. there are separate I/O instructions to access the three on-chip I/O ports. as against 8243 Input/Output Expander
I/O ports. Also. there are separate instructions to access on-chip scratchpad read/write memory. as against external·
data memory.
The 8048 instruction set is probably more versatile than any other one-chip microcomputer instruction set described in this book. The only omission that may cause problems is the lack of an Overflow status; this will make
multibyte signed binary arithmetic harder to program.
THE BENCHMARK PROGRAM
The benchmark program we have been using in this book is not realistic for the 8048 with its limited data memory.
Using the 8048 you would not load data into some general depository. then transferit to a specific data table.
In order to provide some illustration of 8048 instructions. however. we will slightly modify the benchmark program and
move a number of data bytes from the top of scratchpad memory to a table in external data memory. Since the data in
scratchpad memory must have been input from an I/O port. we will assume that the number of scratchpad memory
bytes is stored in General Purpose Register R7. The table in external memory begins at a known location and the first table byte addresses the first free table location. Operations performed may be illustrated as follows:
External Data
Memory
Scratchpad
R0t-_ _--4
R1
~-------R2
R3
t-----4
~----4
R4
t----t
R5t-_ _--4
R6
I----t
R7
NN
I
I
I
I·.
I
I
~ \ . . - Last byte
t
_
I
I
I
I
_
of data table
~
~
RO indexes I
scratch pad ,I
-~x~x-11~~
...__ TBASE. 'start
I
/
transfer
performed
t
I
I
I
3F 1-----4
6-32
xx ...- First free byte
cw
~
a:
oD.
LOOP
a:
o
o
a;
en
w
~
MOV
MOVX
MOV
ADD
MOVX
MOV
MOV
MOVX
DEC
INC
DJNZ
;LOAD EXTERNAL TABLE BASE ADDRESS INTO RO
;LOAD ADDRESS OF FIRST FREE BYTE INTO A
;SAVE IN R1
;ADD NEW BYTE COUNT TO A
;RESTORE IN FIRST FREE BYTE OF EXTERNAL TABLE
;LOAD SCRATCHPAD ADDRESS INTO RO
;MOVE DATA FROM SCRATCHPAD TO A
;STORE IN EXTERNAL DATA TABLE
;DECREMENT RO
;INCREMENT R1
;DECREMENT R7. SKIP IF NOT ZERO
RO.#TBASE
A.@RO
R1.A
A.R7
@RO.A
RO.#3FH
A@RO
@R1.A
RO
R1
R7.LOOP
These are the abbreviations used in Table 6-2:
A
The Accumulator
g
A03
Accumulator bits 0-3
(J)
(J)
R
Register RO or R1
ail
w
Z
REG
Accumulator. RO. R1. R2. R3. R4. R5. R6 or R7
RN
Register RO. R1. R2. R3. R4. R5. R6 or R7
o
T
Timer/Counter
o
C
Carry status
~
AC
Auxiliary Carry status
MBO
Program memory bank 0
MB1
Program memory bank 1
«
a:
m
(J)
«c
«
@
MBN
MBO or MB1
The Instruction register
12
Second object code byte
PC
The Program Counter
PC10
The Program Counter. bits 0-10
PCL
The Program Counter. bits 0-7
PCH
The Program Counter. bits 8-11
SP
Stack Pointer: PSW bits O. 1 and 2
PSW
The Program Status Word which has bits assigned to status flags as follows:
6
S
PSW bit C. FO or F1
DATA
8-bit immediate data
DEV
An I/O device
PORT
I/O Port P1. P2 or BUS
5
4
3
2
o
"'-BitNo.
ADDR
An 11-bit address. specifying a data memory byte
ADDR8
The low-order eight bits of a memory address
[] -
Contents of location identified within brackets
[[ ]]
Scratch pad memory byte addressed by location identified within brackets
I []J
External memory byte addressed by location identified within brackets
([ ])
Program memory byte addressed by location identified within brackets
6-33
Move data in direction of arrow
Exchange contents of locations on either side of arrow
+
Add
Subtract
A
AND
V
OR
¥
Exclusive-OR
BUS
Bus I/O port
P1
I/O Port 1
P2
I/O Port 2
EP
8243 Expander Port P4. P5. P6 or P7
PN
P1 or P2
6-34
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 6-2, A Summary of 8048 Microcomputer Instruction Set
TYPE
MNEMONIC
OPERANDIS)
B021
B041'
B04B
B049
STATUS
OPERATION PERFORMED
BYTES
C
AC
ANl
PORT.#OATA
2
ANlD
EP.A
1
[P,ORT]-[PORT] A DATA
AND immediate data with I/O Port Pl. P2 or BUS
[EP]-[A03] A [EP]
IN
A.PN
1
AND expander port P4. P5. P6 or P7 with Accumulator bits 0 - 3
[A]--:-[PN]
IN
A.DBB
1
Input I/O Port PI or P2 to Accumulator
[A]-[BUS]
INS
A,BUS
1
[A]-[BUS]
MOVD
A.EP
1
Input BUS to Accumulator with strobe
[A03]-[EP]
MOVO
EP.A
1
Input expander port P4. P5. P6 or P7 to Accumulator bits 0 - 3
[EP]-[A03]
ORl
PORT.#OATA
2
Output Accumulator bits 0 - 3 to eKpander port P4. P5. P6 or P7
[PORTl-[PORT] V DATA
ORlO
EP.A
1
OR immediate data with I/O Port Pl. P2 or BUS
[EP]-[A03]V [EP]
OUT
OBB.A
1
OR Accumulator bits 0 - 3 with expander port P4. P5. P6 or P7
[BUS]-[A]
OUTL
PORT.A
1
Output from Accumulator to Data Bus buffer
[PORT]-[A]
Input to Accumulator from Data Bus,buffer
g
Output Accumulator contents to I/O Port Pl. P2 lor BUS B04B. 8049 onlyl
w
(.)
MOV
A.@R
1
[A]-[[Rll
'MOV
@lA.A
1
Load contents of scratchpad byte addressed by RO or R 1 into Accumulator
[[Rll-[A]
MOVP
f:.,.@lA
l
Store Accumulator contents in scratch pad byte addressed by RO or R1
[A]-I[PCH] [A]l
load into the Accumulator the'contents of the program memory byte addressed by the Accumulator and Program Counter bits B - 11.
[A]-(3 [A]l
Z
w
II:
w
~
MOVP3
A.@A
1
w
MOVX
A.@R
1
>
II:
MOVX
@R.A
1
XCH
A.@lR
1
XCHO
A.@lR
1
II:
>
II:
0
~
~
c:(
~
a:
Q.
load into the Accumulator the contents of the program memory byte with binary'~
w
XRL
1
OR contents of scratchpad byte addressed bV RO ()( Rt with Accumulat()(
[A)-[A)¥- [[RII
INC
1
Exclusive OR contents of scratchpad byte addressed bV RO ()( R1 with Accumulat()(
[[ RII-[[ RII": 1
(J
Z
W
a:
W ",w
w~
a:c(
>ffi
a: a..
00
~>
~O
a:
c(~
c-
z
0
scrat~hpad
byte addressed bV RO or Rl with Accumulat()(
Increment the contents of the scratchpad byte addressed bv RO ()( Rt
(J
w
II)
w
~
c(
C
w
~
MOV
2
[REG)-DATA
MOV
2
Load immediate data into Accumulator. ()( Register RO. Rt. R2. R3. R4. RS. R6 or R7
[[RIl-DATA
Load immediate data into scratchpad byte addressed bV RO ()( R1
[PC10)-ADDR
~
JMP
ADDR
2
JMPP
@lA
1
SEL
MOO
1
With the next JMP or CALL instruction. reset the high order bit ':If PC to O. thus selecting first 2K
program memory bytes.
SEL
MBI
1
With the n'ext JMP or CALL instruction. set high order bit of PC to 1. thus selecting second 2K
program memory bytes.
CALL
ADDR
2
STACK -STATUS + [PCI. [spl-[SPI + 1. [PCI-ADDR
Call subroutine at specified address.
RET
1
RETR
1
[PCI-STACK. [SPI-[SPI-l
Return from subroutine without restoring status
[PCI + STATUS -STACK. [spl-[SPI-l
Return from subroutine and restore status
Jump to instruction in current 2K block having label ADDR
[PC)-[PCH)[AI. [PCL)-( [PCH)[A))
Load into the eight low order Program Counter bits the contents of the program memory byte
addressed bV the Accumulator and the four hgih order Program Counter bits.
a..
~
.,:l
Z
a:
:l
~
w
a:
C
Z
c(
-'
-'
c(
(J
w
Z
~
:l
0
a:
CD
:l
II)
.'
X
X
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 6-2. A Summary of8048 Microcomputer Instruction Set (Continued)
TYPE
MNEMONIC
ADD
OPERANDIS)
A.#DATA
S021
X
S041
X
BYTES
X
1&1
!(
STATUS
S04S
S049
-
AC
2
X
x
2
X
X
a:
.ADDC
A#DATA
X
X
X
0
ANL
A.#DATA
X
X
X
2
ORL
A.#DATA
X
X
X
2
XRL
A.#DATA
X
X
X
2
DJNZ
RN.ADDRS
2
JBb
ADDRS
2
JC
AD DRS
2
JFO
ADDRS
2
JF1
ADDRB
2
JNC
ADDRS
2
JNI
ADDRB
2
JNIBF
·ADDRS
2
JNTO
ADDRS
2
JNTl
ADDRS
2
JNZ
ADDRS
2
JOBF
ADDRS
2
JTF
ADDRS
2
1&1
Q.
1&1
~
«
i3
OPERATION PERFORMED
C
[A1,-[A] + DATA
Add immediate data to Accumulator
[A]-[A]+DATA+ [e]
Add immediate data plus Carry to Accumulator
[A]-[A] 1\ DATA
AND immediate data with Accumulator contents
[A]-[A] V DATA
OR immediate data with' Accumulator contents
[A]-[A]¥DATA
Exclusive OR immediate data with Accumulator contents
1&1
~
~
Z
'0
;::
0
Z
0
CJ
Z
0
Q.
..
~
..,::l
JTO
ADDRS
2
JT1
ADDRS
2
JZ
ADDRS
2
[RN]-[RN]-l.lf [RN] ~O. [PCLl-ADDRS
Decrement Register RO. R1. R2. R3. R4. R5. R6 or R7.lf the result is not O. branch to ADDRS on _
the current program memory page.
[PCL]-ADDRS
Jump on current page if Accumulator bit b is 1. b must be O. 1.2.3.4.5.6 or 7
[PCL]-ADDRS
.:dump on current page if Carry is 1
[PCL]-ADDRS
Jump on current page if flag FO is 1
[PCL]-ADDRS
Jump on current page if flag F1 is 1
[PCL]-ADDRS
.Jump on current page if Carry is 0
[PCL]-"ADDRS
Jump on current page if interrupt request input is 0
[PCL]-ADDRS
. Jump if IBF flag is 0
[PCL] - ADDRS
• - Jump on current page if TO input is 0
[PCL] - ADDRS
Jump on current page if Tl input is 0
[PCL]--' ADDRS
-!ump on current page if Accumulator contents is nonzero
[PCL]-ADDRS
Jump if OBF flag is 1
[PCL)- ADDRS
Jump on current page if timer has timed out. that is. if timer flag is 1. The
by this instruction.
[PCL]-ADDRS
Jump on current page if TO input is 1
[PCL]-ADDRS
Jump -on current page if Tl input is 1
[PCL]-ADDRS
Jump on current page if Accumulator contents are zero
ti~r
flag is reset. to 0
Table 6-2. A Summary of 8048 Microcomputer Instruction Set (Continued)
TYPE
w
MNEMONIC
OPERAND(S)
8021
8041
8048
8049
STATUS
BYTES
OPERATION PERFORMED
C
AC
>
MOV
A,RN
[A)-[RN)
I-Ir
MOV
RNA
Move the contents of a general purpose register to the Accumulator
[RN)-[A)
alWill
XCH
ARN
Move the Accumulator contents to a general purpose register
[A)--[RN)
a: °::E
w
IIlW
Ira
w
Ir
Exchange the Accumulator contents with the contents of a general purpose"register
ADD
ARN
x
x
[A)-[A)+ [RN)
'AD DC
ARN
x
x
Add the contents of a general purpose register to the Accumulator
[A)-[A) + [RN) + [C)
ANL
ARN
Add the contents of a general purpose register, plus Carry, to the Accumulator
[A)-[A) A [RN)
ti°
ORL
A,RN
AND the contents of a general purpose register with the Accumulator
[A)-[A) V [RN)
Ir
XRL
ARN
OR the contents of a general purpose register with the Accumulator
[A)-[A)¥- [RN)
Ir
W
I-
III
·awI-w
Ir~
'Ir
Irw
Wll.
aw
Exclusive-OR the contents of a general purpose register with the Accumulator
Cf
w
00
CLR
A
(A)-O
CPL
A
Zero the Accumulator
[A)":"[A)
DEC
REG
Complement the Accumulator
Decimal adjust Accumulator contents
[REG)-[REG)-l
INC
REG
The 8021 can only decrement Accumulator contents.
[REG)-[REG) + 1
RL
A
RLC
A
RR
A
DAA
Decrement the contents of the Acrumulator or general purpose register.
w
I~
Ir
W
Increment the contents of the Accumulator or general purpose register
"Rotate Accumulator left
Il.
o
Ir
W
I-
III
aw
Ir
x
Rotate Accumulator left through Carry
EQ!itlf7f:tll !OJ
Rotate Accumulator right
© ADAM OSBORNE & ASSOCIATES. INCORPORATED
Table 6-2. A Summary of 8048 Microcomputer Instruction Set (Continued)
TYPE
MNEMONIC
OPERAND(S)
8021
8041
8048
8049
STATUS
BYTES
OPERATION PERFORMED
C
AC
X
RRC
A
1
SEL
SEl
RBO
RBl
1
1
Select register bank 0
Select register bank 1
SWAP
A
1
Swap Accumulator nibbles
Rotate Accumulator right through Carry
~l\fllI±I ~
C
w
:;)
z
~
Z
0
g
...ctw
a::
w
0..
0
a::
[AI
...w
til
(;
W
a::
II IIIIIII
,DIS
EN
DIS
EN
TCNTI
TCNTI
I
I
1
1
1
1
Disable timer interrupt
Enable timer interrupt
Disable external interrupt
Enable external interrupts
ENTO
, MOV
·CLK
A,T
1.
1
MOV
T,A
1
STOP
.STRT
STRT
TCNT
CNT
T
1
1
1
Enable timer output:on TO until next system reset
[AI-[TI
Read timer/counter
IlI-[AI
Load timer/counter
Stop timer/counter
Start counter
Start timer
CLR
CPl
MOV
S
S
A,PSW
1
1
1
0
MOV
'PSW,A
1
X
Clear PSW bit C, FO or Fl. 8021 can only clear Carry,
Complement PSW bit C, FO or Flo 8021 can only complement Carry.
[AI-[PSvit)
--
X
X
Move Program Status Word contents to the Accumulator
[PSWI-[AI
Move Accumulator contents to the Program Status Word
NOP
1
No Operation
The following symbols are used in Table 6-3:
bbb
.ee
Three bits designating which bit of the Accumulator is to be tested.
Two bits designating an 8243 Expander port:
00
01
10
11
k
MM
nnn
pp
qq
-'
-
P.4
P5
P6
P7
One bit selecting a memory or register bank:
o MBO or RBO
1 MBl or RBl
Eight bits of immediate data
Three bits designating one of the eight general purpose registers
Two bits designating one of the on-chip I/O ports:
.
00 - BUS
.
01 - Pl
10 - P2
Two bits designating either I/O Port 1 or I/O Port 2:
01 - Pl
10 - P2
One bit selecting a pointer register:
o - RO
1 - Rl
xxx
XX
The high-order three bits of a prowam memory address
T~r low-order eight bits of a progra~ memory address
6-40
Table 6-3. 8048 Series Instruction Set Object Codes
c
w
~
o
D..
a:
a:
o
o
~
enw
~
g
rn
rn
OBJECT CODE
BYTES
ADD
A.RN
01101nnn
1
1
ADD
A.~1,fl
0110000r
1
ADD
A.#DATA
03
MM
ADDC
01111nnn
ADDC
A.RN
A.((!,'fl
ADDC
A.#DATA
w
Z
a:
o
en
INSTRUCTION
CYCLES
2
JTO
'ADDR8
36
XX
'2
2
1
1
JTl
ADDR8
56
XX
2
2
0111000r
1
1
JZ
ADDR8
C6
XX
2
2
2
2
MOV
A.#DATA
23
MM
C7
2
2
1
1
lllllnnn
1
llll000r
1
1
42
1
1
1
ANl
A.RN
1
1
MOV
A.PSW
ANl
A.ql~
0101000r
1
1
MOV
ANl
A.#OATA
2
2
MOV
ANl
PORT.#DATA
53 MM
loo110pp
A.RN
A.ei:'R
2
2
MOV
A.T
MOV
PSW.A
07
1
ANlD
loolllee
1
2
MOV
RN.A
10101nnn
1
1
CAll
EP.A
AODR
'xxxl0loo
2
2
MOV
RN.#DATA
10111nn
2
2
ClR
A
27
1
MOV
ClR
C
97
1
1
1
MOV
1tlR.A
1tR.#DATA
1010000r
1011000r
ClR
Fl
A5
1
1
ClR
FO
85
1
1
MOV
T.A
62
1
1
CPl
A
37
1
1
A.EP
00001100
1
2
EP.A
A.{liA
ooflllee
1
2
A3
1
2
A.1tA
E3
1
2_
A.!IJR
;t(fl,A
l000000r
1
2
lOO1000r
1
2
00
1
1
1
1
MM
1
1
2
2
MM
A7
1
1
FO
95
1
1
MOVP
C
CPl
OA
Fl
B5
57
1
1
1
1
MOVP3
MOVX
A
1
MM
XX
C
@
2
2
CYCLES
2
CPl
c:(
2
2
1
CPl
c:(
86 XX
16 XX
AnDR8
ADDRII
~
o
BYTES
JOBF
JTF
MOVD
,MOVD
rn
MACHINE
OBJECT CODE
13 MM
01011nnn
c:(
all
MACHINE
INSTRUCTION
DEC
A
07
1
1
MOVX
DEC
RN
l1oo1nnn
1
1
NOP
DIS
I
15
1
1
ORl
A.RN
01oo1nnn
35
• 11101rrr
1
1
ORl
A.lOR
0100000r
1
1
2
2
ORl
A.#DATA
43
MM
2
2
ORl
PORT. # DATA
looo10pp
2
2
looo11ee
1
2
02
02
1
1
1
2
oo1110qq
83 •
1
2
1
2
1
1
2
1
1
DIS
DJNZ
TCNTI
' RN.ADDR8
XX
EN
I
05
1
1
EN
TCNTI
25
1
1
ORlD
EP.A
ENTO
ClK
75
1
1
IN
A.PN
oooolOqq
1
2
OUT
OUTl
DBB.A
BUS.A
IN
INC
A.DBB
A-
22
17
1
1
1
1
OUTl
PN.A
INC
RN
'ooollnnn
oool000r
A
08
1
2
'Rl
RLC
93
E7
INS
'fR
A.BUS
1
1
RETR
INC
1
1
A
F7
1
JBb
ADORa
bbbloo10
2
2
RR
A
77
1
1
RRC
A
1
1
XX
JC
ADORa
F6
JFO
ADORa
B6
JFl
JMP
ADDR8
ADDR
xx
xx
76 XX
:xxxOO100
JMPP
({IJA
ADORa
E6
ADORa
a6
B3
JNIBF
ADORa
06
JNTO
JNTI
ADORa
ADORa
26
46
JNZ
ADORa
96
xx
xx
xx
xx
xx
xx
RET
2
2
SEl
MBk
67
l11kOl0l
1
1
2
2
2
2
SEL
RBk
lfokOl0l
1
1
STOP
STRT
TCNT
CNT
65
45
1
1
1
1
STRT
T
55
1
1
2
2
2
SWAP
A
47
1
1
XCH
A.RN
A.fl:ll
oo101nnn
1
1
00loooor
1
1
2
2
oollooor
1
1
2
2
2
XCHD
XRL
A.fl'R
2
XRL
A.RN
A.'flCA
11011nnn
1101000r
1
1
1
1
XRL
A.#DATA
03
MM
2
2
2
2
XX
JNC
JNI
MM
1
2
2
2
2
XCH
THE 8041 SLAVE MICROCOMPUTER
This device is also referred to in Intel literature as a Universal Programmable Interface (UP!); it represents a simple variation of the 8048 microcomputer.
The 8741 is a slave variation of the 8748 microcomputer.
This discussion of the 8041 and 8741 slave microcomputers explains differences as compared to the 8048 and
8748; you should therefore read the following pages after reading the 8048 and 8748 descriptions.
6-41
AN 8041 FUNCTIONAL OVERVIEW
The principal difference between the 8048 and the 8041 is the fact that the 8041 Data Bus and I/O Port 0 are
used exclusively to communicate with a master microprocessor. The 8041 generate"s no external Address or
Data Bus. so on-chip 8041 program memory and scratchpad data memory cannot be expanded.
External interrupt logic. which is available on the 8048. is not available on an 8041; the 8041 uses this logic as
a handshaking interrupt for data input from the master microprocessor.
8048 and' a041 logic are compared functionally in Figure 6-15.
1024 x 8 Bits
8048 or
8041 = ROM
8748 or '
8741 = EPRQM
Arithmetic And
Logic Unit.
Control Unit
and Instruction
Register
Program
Status Word
System
rp'sl~t--__'" RESET
PROM/Expander strobe
CPU/Memory Separate
64 x 8 Bits
RAM
PROG
EA
----1~
XTAL 1
----1~
XTAL2
" Accumulator
~~~~~~~~~!~:~~~~~~~~~:~j~J~~~f'--~-iPS~NorAO
Steo--__... SS
Read suc>De .....i---i RD
Write strc)be .....f----i WR
Counter/ Timer
Test or event counter input
Figure 6-15. A Comparison of 8048 and 8041 Functional Logic
6-42
Communications between an 8041 and a master microprocessor are very limited. Data must be transferred byteby-byte under program control. with nearly all handshaking protocol being implemented via program logic. You must
therefore define the protocol within the logic of your 8041 and master microprocessor programs. A rigid protocol is
absolutely necessary, since the 8041 offers no protection against data transfer contentions.
8041 DATA BUS LOGIC
~
~
a:
oD..
8041 Data Bus logic may be illustrated conceptually as follows:
r-
a:
o
u
Data
Out
Buffer
""-
K
!:
'"
enw
A
....
J
I-
oCt
(3
o
C/)
C/)
oCt
~
w
a:
oen
Z
C/)
o
~
Master
Microprocessor
....
<'"
....
t..
or
...
Data
In
Buffer
'"
8041 LOGIC
y
oCt
C
oCt
@
Buffer
Status register
-
F1
A
J>.
FO
...
r
IBF
Connected
as follows:
....
F1
FO
IBF
OBF
}¢:::>
OBF
- Bit 3
-
Bit 2
Bit 1
Bit 0
In reality, the Data Out buffer and the Data In buffer are a single piece of logic; however, operations occur (to
some extent) as though there were two separate buffers.
A master microprocessor will access an 8041 as two 1/0 ports or two memory locations. These locations are identified via chip select (CS) and address (AO) input signals as follows:
CS
o
o
AO
0
Read from Data Out
buffer
Write to Data In buffer
{ and reset
F1 Buffer status to 0
Read from Buffer
Status register
Write to Data In buffer
{ and set
F 1 Buffer status to 1
6-43
"Read" and "Write" above refer to master microprocessor operations .
.The 8041 accesses the Data Bus buffer register as I/O Port O. The Status register is inaccessible to the 8041 as an
addressable I/O port however. there are specific 8041 instructions that access the FO and F1 Buffer Status bits .
.The four Buffer Status register bits may be defined as follows:
OBF is the output buffer full flag. This flag is automatically set to 1 when the 8041 outputs data
to the Data Out buffer. When the master microprocessor reads the contents of the Data Out
buffer: the OBF flag is reset to O.
8041
BUFFER
STATUS
REGISTER
IBF is the input buffer full flag. This flag is set to 1 when the master microprocessor writes data
into the Data In buffer. This flag is reset to 0 when the 8041 subsequently reads data from the Data In buffer.
FO is a general-purpose flag which can be set or reset by the 8041. The master microprocessor can sample FO by reading Buffer Status register contents.
F1 is another general-purpose flag which can be modified by the 8041. F1 is also set or reset to the level of AO
whenever the master microprocessor writes data into the Data I n buffer. The master microprocessor can sample F1 by
reading Buffer Status register contents.
When the master microprocessor reads buffer status. flags appear on the Data Bus lines as follows:
07
06
05
04
03
02
01
} Undef;"d
F1
FO
ISF
OSF
00
Whenever the 8041 outputs data to I/O Port O. the data is stored in the Data Out buffer and the OBF status flag is set to
1; when the master microprocessor subsequently reads the contents of the Data Out buffer. the OBF flag is reset to O.
When the master microprocessor writes to the 8041. the data is loaded into the Data In buffer. the IBF status is set to 1
and an interrupt request is generated within the 8041; this interrupt request replaces the external interrupt logic of the
8048. The IBF status is cleared when the 8041 subsequently reads the contents of the Data In buffer.
The FO flag is set or reset by the 8041 using appropriate instructions. There is no predefined manner in which this flag
is interpreted; your program logic can use this flag in any way.
The F1 flag is set to the level of the AO signal input whenever the master microprocessor writes a control byte into the
Data In buffer.- In reality. there is no difference between a control byte and a data byte; that is to say. thero is no predefined way in which the 8041 will interpret the contents of the Data In buffer based on the F1 flag level.
The master microprocessor reads data which has been output by the 8041; the master microprocessor cannot read
back data which it wrote to the 8041.
The 8041 inputs from I/O Port 0 data that was written by the master microprocessor; the 8041 cannot read back data
which it previously output to 110 Port O.
8041 1/0 PORTS ONE AND TWO
Physically. 8041 I/O Ports 1 and 2 have logic which is identical to the 8048. Thus the pseudo-bidirectional I/O port
characteristics described for the 8048 110 Ports 1 and 2 apply also to the 8041 110 Ports 1 and 2.
Note that the 8041 does not generate an external Address Bus. therefore I/O Port 2 pins P20 - P23 never output address information.
8041 AND 8741 PROGRAMMABLE REGISTERS
The 8041 and 8741 have a 1O-bit Program Counter. The 8048 and 8748 have a 12-bit Program Counter. These are the
only differences between the 8041 series and 8048 series programmable registers.
8041 AND 8741 ADDRESSING MODES
The 8041 and 8741 can address only on-chip memory. This includes the 1024 bytes of on-chip program memory and
64 bytes of on-chip scratchpad data memory. 8041 and 8741 addressing modes are identical to the 8048 and 8748
on-chip memory addressing modes. Of course. the 8048 and 8748 external memory addressing modes will not apply
to the 8041 or the 8741.
6-44
8041 AND 8741 STATUS
The 8041 and 8741 slave microcomputers have two Status registers. First, there is the Buffer Status register,
which is part of the Data Bus logic. We have already described this 4-bit Status register. The 8041 and 8741
also have the 8-bit Program Status Word described for the 8048 series microcomputers. 8041 and 8048 Program Status Words are identical.
~.
8041 AND 8741 SLAVE MICROCOMPUTER OPERATING MODES
~:
The 8041 and 8741 can be operated in Internal Execution mode and Debug mode; in addition, the 8741 can be
operated in Single Stepping mode, Programming mode and Verification mode. Neither the 8041 nor the 8741
can be operated in External Memory Access mode.
~
~
u;
~
en
w
~
8041 AND 8741 PINS AND SIGNALS
There are a few differences between 8041 and 8741 pins and signals, as compared to the 8048 and 8748.
Figure 6-16 defines 8041 and 8741 pins and signals; the four changed signals are shaded.
.
(j
o
(I)
(I)
oct
o!I
w
TO
a:
oct
oct
XTAL1
XTAL2
RESET
SS
CS
EA
@
Ro
Z
oIn
(I)
o
:!:
Q
AO
WR
SYNC
DBO
OBI
DB2
DB3
DB4
DB5
DBB
DB7
(GND) Vss
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
8041
8741
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vee (+5V)
Tl
P27
P26
P25
P24
P17
P16
P15
P14
P13
P12
Pll
Pl0
VDD
'PROG
P23
P22
P21
P20
PIN NAME
DESCRIPTION
TYPE
DBO - DB7
Bidirectional I/O port, Data Bus and
low-order eight Address Bus lines
I/O Port 1
I/O Port 2, P20 - P23 also serves as four
high-or~er .A~.~refj~Bu~ lines
Extemalclocksigl'lal
Data memory read control
Data
write control
Bidirectional, tristate
PIa - P17
P20 - P27
Ouasibidirectional
Ouasibidirectional
program memory access
Single step control
Test inpu(and
PrOgramlVerifYrn6i::ie.··sel~ct
Tl
RESET
VSS
Vee
VDD
PROG
XTAL1, XTAL2
Test input, optional event counter input
System reset and EPROM address latch
Ground
+5V
+ 25V to program 8741. + 5V standby
for 8041 RAM
+ 25V input to program 8741. Control
output for 4-bit I/O
Extemal crystal connections
Input
Input
Bidirectional
Figure 6-16. 8041 and 8741 Microcomputer Pins and Signals
6-45
CS and AO are the device select inputs which we have already described.
SYNC is an external synchronizing signal which is output once per machine cycle.
TO cannot be connected to the internal system clock; other uses of TO are the same for the 8041/8741 and the
804S/8748.
All other signals are identical to the 8048 and 8748 as previously described. Note. however. that no addresses are output on the DBO - DB7 pins or the P20 - P23 pins.
8041 SERIES TIMING AND INSTRUCTION EXECUTION
The 8041/8741 clock signals and instruction execution timing logic is identical to the 8048/8748. Of course. the 8041
and 8741 have no external memory reference instructions. therefore timing associated with these instructions will not
apply.
8741 SINGLE STEPPING AND PROGRAMMING MODE
Single Stepping and Programming modes of operation are available only with the 8741; the 8041 cannot be
operated in these modes.
There are, of necessity, some differences between 8741 and 8748 Single Stepping and Programming modes;
this is because the 8741 has no ALE signal and no output Address Bus.
In Single Stepping mode. the 8741 is stopped by applying a low SS input when SYNC is low.
The 8741 responds by stopping during the next instruction fetch. At this time. SYNC is maintained high. The address
of the next instruction to be accessed appears at 1/0 Port 1 and 'the low-order two bits of 1/0 Port 2. This condition is
maintained until SS is input high again. Timing may be illustrated as follows:
SYNC
-1
Pl0-P17----------------------------u-------------------~ ~--~~---------------PCO - PCg
P20-P21------------------__________R-__________________
~~---n------------------
There are also some minor differences between 8741 and 8748 Programming modes. The ten-step 8741 programming sequence is therefore given below. Differences as compared to the 8748 are shaded.
Initially +5V is input at VDD.g§. TO and EA. RESET and~.9 are held at ground. Under these conditions you
insert the 8741 into the programming socket. You must make certain to insert the 8741 correctly. If you
insert the 8741 incorrectly you will destroy it.
Step
1)
Step
2) TO is pulled to ground; this selects Programming mode.
Step 3) +25V is applied to EA. This.activates Programming mode.
Step 4) A 10-bit memory address is applied via DBO - DB7 and P20 - P21. Remember. there are 1024 bytes of program memory on the 8741 device. The low-order eight address bits are input via DBO - DB7 while the two
high-order address bits are input via P20 and P21.
Step
5) +5V is applied at RESET. This latches the address.
Step 6) The data to be written into the addressed programmed memory byte is input at DBO - DB7.
Step
7) In order to write the data into the addressed program memory byte apply +25V to VDD. then ground PROG.
then apply a +25V pulse at PROG; the +25V pulse at PROG must last at least 50 milliseconds.
Step 8) Now reduce VDD to +5V. Programming is complete and verification is about to begin.
Step
9) In order to verify the data just written. apply +5V to the TO input. This selects Verify mode.
Step 10) As soon as Verify mode has been selected. the data just written is output on DBO - DB7. You must read and
verify this data using appropriate external circuitry. Verification is now complete.
6-46
8041 INPUT/OUTPUT PROGRAMMING
The only differences between 8041/8741 and 8048/8748 input/output programming are those which result
from the uniq~e 8041 I/O Port 0 logic - which we have described.
8041 COUNTER/TIMER
OPERATIONS
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8041 series and 8048 series counter/timer operations are identical.
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The entire external interrupt logic of the 8048 has been converted in the 8041/8741 Data Bus handshaking interrupt logic. This interrupt request occurs every time a master microprocessor writes to either of the
8041/8741 addressable locations.
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In order to generate external interrupt logic at an 8041 or 8741 you must use the counterltimer. By loading the
counterltimer with an initial value of FF16 and operating the counterltimer in Counter mode, the first high-ta-Iow input
transition on T1 will generate a Timer interrupt request. Of course, you are using the counterltimer in this way, you
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cannot use it for any of its normal functions.
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8041 INTERRUPT LOGIC
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PROGRAMMING 8048-8041 DATA TRANSFERS
The only complexity associated with programming an 8041 involves data transfers between the 8041 and a
master microcomputer. Programming these data transfers is not straigh~forward.
We described earlier how there are separate data paths for data entering or leaving the 8041 via the Data Bus buffer.
Nevertheless, if a master· microcomputer attempts to write to the 8041/8741 while the 8041/8741 is
simultaneously outputting to I/O Port 0, then there will be an undefined result.,This is unfortunate, since there are
no signals or indicators of any kind allowing the master microcomputer to lock out the 8041/8741; nor can the
8041/8741 lock out the master microcomputer. Lock out logic rn~!it be implemented by you, via your program
logic. Program logic must also make sure that data written by ;'~:I master microcomputer has been read by the
8041/8741 before the master microcomputer writes any new data; similqrly, the 8041/8741 must make sure that any
data it has output to I/O Port 0 has been read by the master microcomputer before the 8041/8741 attempts to output
new data to 1/9 Port O.
Let us look at the programming steps required for error free data transfers between the 8041/8741 and a
master microcomputer. Programming examples assume an 8048 is the 'master microprocessor because the 8048 is
described in this chapter and has an instruction set that is similar to the 8041. In reality, the master microprocessor is
likely to be an 8085-type device.
The mastElr microcomputer can make sure that it does not overwrite data by testing both the IBF and the OBF flags;
that is to say, the master microcomputer will,not attempt to write data to the 8041/8741 if prior data it wrote is waiting
to be read by the 8041/8741, or if data output by the 8041/8741 is waiting to be read by the master microcomputer.
The following master microcomputer output instruction sequence will suffice:
.
MOV
MOVX
RRC
JC
RRC
JC
DEC
0,ADDR+1
;LOAD 8041 ADDRESS INTO 8048 REGISTER RO
A,@O
; LOAD STATUS
;TEST LOW ORDER (OBF) FLAG
;IF IT IS 1, DO NOT WRITE NEW DATA
;TEST NEXT BIT (lBF) FLAG
;IF IT IS 1, DATA IS WAITING TO BE READ
;OK TO OUTPUT
A
NEXT
A
READ
o
6-47
But this scheme does not prevent the master microcomputer and the 8041/8741 from simultaneously accessing the
Data Bus buffer. This must be guaranteed by 8041/8741 lock out logic. The 8041/8741 can use programming logic or
interrupt logic to lock out the master microcomputer. Using programming logic. the 8041/8741 will use the FO flag to
identify those time intervals when the master microcomputer is free to access the Data Bus buffer. Now any 8048
master microcomputer instruction sequence that accesses the 8041/8741 will first read 8041/8741 status and test the
Fa flag. If this flag is "false". no data transfer must occur. Continuing our master microprocessor instruction sequence.
this may be illustrated as follows:
MOV
TEST
READ
MOVX
RRC
JC
RRC
JC
RRC
JNC
DEC
MOV
MOVX
. JMP
RRC
JNC
DEC
MOVX
MOV
JMP
0.ADDR+1
;LOAD 8041 ADDRESS INTO 8048 REGISTER RO
A@O
A
;LOAD STATUS
;TEST LOW ORDER (OBF) FLAG
;IF IT IS 1. DO NOTWRITE NEW DATA
;TEST NEXT BIT OBF) FLAG
;IF IT IS 1. DATA IS WAITING TO BE READ
;TEST FO FLAG
;IF Fa IS a. MASTER IS LOCKED OUT
;FO IS 1 SO IT IS OK TO OUTPUT DATA
;LOAD DATA TO BE OUTPUT INTO ACCUMULATOR
;OUTPUT DATA TO 8041
NEXT
A
READ
A
TEST
o
A@1
@O.A
OUT
A
TEST
o
A@O
@1.A
OUT
;TEST FO FLAG
;IF FO IS O. MASTER IS LOCKED OUT
;FO IS 1 SO IT IS OK TO READ DATA
;INPUT DATA
;STORE IN SCRATCHPAD
The instructions above assume that scratchpad register R1 addresses the scratchpad byte out of which written data is
fetched. or into which read data is stored.
.
If there is heavy traffic between an 8041/8741 and a master microcomputer. then the 8041/8741 shou Id use interrupt
logic to identify times when a master microcomputer can either output data to the 8041/8741 or input data from the
8041/8741. To do this. one or two 8041/8741 110 port pins must be set aside as interrupt request generation lines.
Now the master microcomputer will not access the 8041/8741 except within an interrupt service routine which is initiated by an interrupt request arising from one of the t,wo dedicated 8041/8741 I/O port pins.
Data transfers from the 8041/8741 to the master microcomputer are easy to program. When the 8041/8741 writes to
I/O Port O. the OBF flag is set to 1 ; th is flag is reset to 0 when a master microcomputer reads data. Thus. the 8041/8741
simply tests the OBF status before outputting data; here are appropriate instructions:
CLR
JOBF
OUT
CPL
FO
NEXT
DBB.A
FO
;ZERO FO TO LOCK OUT THE MASTER MICROPROCESSOR
;TEST OBF FLAG
;IF IT IS ZERO. OUTPUT NEXT DATA BYTE
;SET FO TO ALLOW MASTER MICROPROCESSOR ACCESS
NEXT
6-48
The 8041 /8741'can respond to data arriving from the master microcomputer by using polling logic or interrupt logic. If
polling logic is used. then the 8041/8741 must test the IBF flag before reading any data that the master microcomputer
has output. In order to determine whether the master microprocessor has output data or a control code. the 8041/8741
must also check the F1 flag. Here is an appropriate instruction sequence:
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CLR
JNIBF
JF1
Fa
IN
CPL
A.DBB
Fa
:ZERO Fa TO LOCK OUT THE MASTER MICROPROCESSOR
:TEST FOR DATA WAITING TO BE READ
:DATA IS READY TO BE READ. TEST
: FOR DATA BYTE OR CONTROL BYTE
:READ DATA
:?ET Fa TO ALLOW MASTER MICROPROCESSOR ACCESS
IN
CpL'
A.DBB
Fa
:READ CONTROL CODE
:SET Fa TO ALLOW MASTER MICROPROCESSOR ACCESS
~EXT
CONT
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If 8041/8741 data input logic is interrupt driven. then external interrupts must be left enabled. Now as soon as the
master microcomputer outputs data to the 8041/8741. an interrupt request will occur. followed by a Call 3 instruction
being executed. Beginning at rnemory location 3. the following instruction sequence will initiate the data input interrupt service routine within the 8041/8741:
1
01(
qRG
JMP
3
DTIN
:JUMP TO DATA INPUT ROUTINE
DTIN·
CLR
JFl
IN
Fa
CONT
A.DBB
:ZERO Fa TO LOCK OUT MASTER MICROPROCESSOR
:TEST FOR DATA TYPE
:READ DATA
CONT
IN
A.DBB
:READ. CONTROL CODE
CPL
RET
Fa
:SET Fa TO ALLOW MASTER MICROPROCESSOR ACCESS
:RETURN FROM INTERRUPT SERVICE ROUTINE
@
The master microprocessor must not write to the 8041/8741 while data thatthe 8041/8741 has output is waiting to be
rea~j; similarly. the 8041/8741 cal1not output data fO the master microprocessor while data from the master
microprocessor is w~iting to be read by the 8041/8741. In each case. prior data will be overwritten and lost. In order to
prevent this from happening. you must have appropriate lock out logic. Fa is used for this pur~o~j3 abo,:,e.
THE 8041/~741
INSTRUCTION. SET
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The 8041/8741 instruction set differs from the 8048/8748 in minor ways only. Tables 6-2 and ~-3 therefore
.•. . .
.
summarize t~e instruction set for both the 8048 series and 8041 series microcomputers:
6-49
1024 x 8 Bits
RP~
Arithmetic and
Logic Unit,
Control Unit
and Instruction
Register
x 8 Bits
RAM
8021 has one
set: of registers
only
64
Count~r /Timer
Iii
All 8021 I/O port pins have
1:1
These signals
.
.
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uni~ue characteristics
ar~
not pres~nt in an 8021 .
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1::;1 8021 T1 characteristics are unique
Figure 6-17. A Comparison of 8048 and 8021 Functional Logic
6-50
THE 8021 SINGlE-CHIP MICROCOMPUTER
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The 8021 is a low-cost subset of the 8048,slngle-chip microcomputer. Unlike .the 8041, the 8021, is not
designed to operate as a slave microcomput~r. The 8021 is intended for high-volume, low-cost 'applications
with limited microcomputer logic requirements. The only easy way in which an 8021 can be expanded is by adding
an 82431nput/Output Expander. There is no simple way to increase either 8021 program memory or data memory. over
and above that which is internal to the 8021.
This discussion of the 8021 single-chip microcomputer explains differences as compared to the 8048 and 8748;
you should therefore read the following pages after reading the 8048 and 8748 descriptions ..
~
AN 8021 FU NCTIONAL OVERVIEW
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The principal difference between the 8048 and the 8q21 is the fact that the 8021 has no Data Bus, and 1/0 Port
o is simply another 1/0 port. Thus. the only way in whli:h an 8021 can communicate with logic beyond the chip Itself
is via its 1/0 ports. which have no accompanying handshaking control signals. In contrast. the 8041 has I/O Port 0 logic
designed for two-way communication between the 8041and a master microprocessor. The 8021 cannot distinguish
between a master microprocessor or any otrer external logic.
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The 8021 has no external interrupt logic and only one Test input.
Only two control signals are output by the 8021: a synchronizing 'clock signal and an 8243 Input/Output Expander
control strobe.
With these reduced capabilities. the 8021 is pa~kaged bs a 28-pin DIP, in contrast to other members of the 8048
series. which are 'packaged as 40-pin DIPs.
. The 8021 can be driven by a crystal oscillator with a maximum 3 MHz frequency. This is half the maximum frequency of the 8048 and 8041. but equivalent to the maximum frequency of the -8 parts. This3 MHz crystal generates
10-microsecond machine cycles. Thus. all 8021 instructions execute in either 10 or 20 microseconds.
Functionally, 8048 and 8021 logic are compared in Figure 6-17. 8021 pins and signals are illustrated in Figure
6-18.
802 i I/O PORT PINS
8021 1/0 port pins are referred to as quasi-bidirectional, a term we also use to describe 8048110 port pins. 8048
and 8021 1/0 port pin logic is identical.
.
THE T1 PIN
When you order an 8021 microcomputer, you can specify one of two configurations for the T1 pin. Electrically,
these maY'be illustrated as follows:
Option A
,,,
(Zero cross-over sensing)
Option B
(Pull-up resistor)
I
I
I
I
I
i Capacitor
CPU
Pin
13
Il-
Switch
CPU
External
logic
Pin
13
External
logic
Option A allows you to detect the zero cross-over point on Slow-moving input Signals. Option B. with the pUll-up. is
designed to sense fast changes such as contact switch~s.
6-51
P22
P23
PSEN
POQ
POl
P02
P03
P04
P05
P06
P07
ALE
•
T1
.. --
--
-.
1
2
3
4
5
..~ --..-
..-
~
--
--
-..
6
-..
--- -
7
8
9
10
11
12
13
14
.
- -..-
~
'-.
-
(GND) VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
. 8021
-
:.
'.-
..
...-
-
-:... ....-..
--
--
. ,;.
..
DESCRIPTION
PIN NAME
lib Port 0
POO - P07
Pl0 - P17
P20 - P23
I/O Port 1
1/.0 :port2 .
tlock,signal
8243 Control
Test iMput. optional
event counter
System reset
External crystal connections
Ground
Power
Ai.E
PSEN
Tl
RESET
XTAL1. XTAL2
VSS
VCC
Vcc (+5V)
P21
.P20
P17
P16
P15
P14
P13
P12
P11
~10
RESET
XTAL2
XTAL1
,TYPE
Ouasibidirectional
ciuasibidirectional
Ouasibidirectional
. Output
Output
Input
Input
Figure 6-18. 8021 Microcomputer Pins and Signals
THE 8021' RESET iNPUT
When the 8021 is reset, the same internal operations occur as described for the 8048; the, Program Counter and
Program Status Word are cleared and 1 is output to 1/9 port pins. However, 8021 reset logic has been modified so
that the 8021 can operate with noisy power supplies. You have one of two options. which may be illustrated as
follows:
Option A (Reset when power falls below 1.5V)
RESET
,
-r".' '.
,
~I- 0
VCC
Option B (Operate as long as power will drive chip)
1~
RESET .....
- - - - - -...
lJ.lF
lJ.lF
10V
10V
VCC
-In the case of Option A. you connect the diode between reset and ground to force a reset whenever power drops below
1.5V. Thus. operations will stop while power falls below 1.5V. but when normal power rl3turnsoperations will restart.
Since chip operations continue only as long as poWer remains high enough to maintain the contents of chip read/write
locatio·ns. this circuit guards against execution with faulty data. By removing the diode. as illustrated in Option B. this
reset feature is eliminated ahd the 8021 will operate as long as power is sufficient to drive logic internal to the chip.
THE 8021 CLOCK INPUTS
A crystal Resistor/Capacitor or inductor circuit can be connected to the XTL 1 and XTL2 pins to provide the
needed internal clock signal. The maximum external crystal frequency allowed is 3 MHz. This generates 10-microsecond machine cycles. All instructions execute in 1 or 2 machine cycles.
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THE 8021 TIMER/COUNTER
Logic associated with the 8021 timer/counter is identical to that which we have described for the 8048. The
contents of the Accumulator can be moved to the Counter/Timer register. which is subsequently incremented once every 32 crystal oscillations in Timer mode. or once every high-to-Iow transition of a T1 input in Counter mode. However.
there is no interrupt logic on the 8021, which means that a time-out will not cause an interrupt request to occur. You
must therefore test for a time-out under program control using the JTF (Branch-on-Timer Flag) instruction.
ui
8021 SCRATCHPAD MEMORY AND PROGRAMMING
~
In addition to the lack of interrupt logic, the 8021 has no Status register and data memory is simplified.
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Instead of having a Status register. the 8021 has a 3-bit Stack Pointer and a single Carry status flag.
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Data memory consists of eight general purpose registers in scratchpad bytes 0-7. plus a 16-byte Stack which uses
scratchpad bytes 8-1716. This stack allows subroutines to be nested to a level of 8. The 8021 does not have the second
set of eight registers located in scratchpad bytes 1816 - 1F16. as is available on the 8048 and the 8041.
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The 8021 instruction set is a subset of the 8048 instruction set. In Table 6-1. 8021 instructions are identified.
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THE 8243 INPUT/OUTPUT EXPANDER
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This support device expands I/O Port 2 of an 8041 or 8048 series microcomputer to four individually addressable 4-bit
I/O ports. The 8243 Input/Output Expander is particularly useful in numerical applications where data is transferred in
4-bit nibbles.
Figure 6-19 illustrates that part of our general microcomputer system logic which has been implemented on the 8243
Input/Output Expander.
The 8243 Input/Output Expander is packaged as a 24-pin DIP. It uses a single +5V power supply. All inputs and outputs are TTL-compatible. The device is implemented using N-channel MOS technology.
8243 INPUT/OUTPUT EXPANDE~ PINS AND SIGNALS
The 8243 Input/Output Expander pins and Signals are illustrated in Figure 6-20. Functional internal architecture is il' ,
lustrated in Figure 6-21.
P20 - P23 represent the 4-bit bidirectional I/O port or bus connection between the 8243 Input/Output Expander and
the 8048 series microcomputer. P20 - P23 must be connected to the low-order four pins of the microcomputer I/O Port
2. Figure 6-22 illustrates the 8243-8048 interface.
P40 - P43, P50 - P53, P60 - P63 and P70 - P73 provide four bidirectional I/O ports, referred to as Ports 4.5. 6 and
7. respectively. These are 4-bit ports via which data is transferred to or from external logic.
Data being output via one of these four ports IS latched and held in a low impedance state.
Data input is buffered. During a read operation 8243 I/O port pins are sampled then I/O port pins are floated.
while the read is being executed;
CS is the single chip select signal for the 8243 device. CS must be low for the device to be selected. There is no
specifically defined manner in which CS has to be created; in Figure 6-22 it is shown being decoded off the four highorder pins of I/O Port 2.
PROG is the single control strobe output by the 8048 series microcomputer to time 8243 events. On the falling
edge of PROG. data input via P20 - P23 is decoded as an I/O port select and operation specification. Resulting 8243
operations are strobed by the rising edge of PROG ..
I
There is no Reset input to the 8243. The device is reset when power is first applied, or when
18243 RESET
power input at the VCC pin drops below +1 volt. Following Reset. Port 2 is inlnput mode while
Ports 4. 5. 6 and 7 are floated. The 8243 device will exit the Reset mode on the first high-to-Iow transition of PROG.
6-53
Clock Logic
Logic to Handle
Interrupt Requests
from
External Devices
Arithmetic and
Logic Unit
Accumulator
Register(s)
,",
I
Instruction Register .........
....
..
Data Counter(s)
~
Stack Pointer
Control Unit
•
r
Interrupt Priority
Arbitration
Bus Interface
Logic
Direct Memory
Access Control
Logic
. . Program Counter
u
System Bus
•
...
I/O Communication
Serial to Parallel
Interface Logic
ROM Addressing
RAM Addressing
and
Interface Logic
and
Interface Logic
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Programmable
Timers
Read Only
Memory
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"---
01 t--WRITE
74107
CLK
PRE
~+5V
PROG
P22. P23
READ
WRITE
Figure 6-22. An 8243/8048 Configuration with External Logic Read and Write Strobes
6-57
)
...
AP70 - P73 ...
"
~
PROG
P20 - P23
Float
I
Instruction
\
1\
,
PNO - PN3
~I \
I
Float
Data Out
,
I
Old output data
Float
New output data
8243
device
decodes
instruction
Figure 6-23. Timing for Data Output to an 8243 Port Via
an MOVD. ORlD or ANlD Instruction
~
PROG
P20 - P23
PNO - PN3
Float
I
Old input data
'\
I\
Instruction
I
Float
1
0
\
Data·ln
New input data
~
Float
L
b
1
8243
device
decodes
instruction
Figure 6-24. Timing for Data Input from an 8243 Port
Timing for 8243 port accesses is illustrated in Figures 6-23 and 6-24.
In each case an instruction is output via P20 - P23 of the 8048 microcomputer on the high-to-Iow transition of
PROG. The instruction is decoded as follows:
P20
0
0
1
1
P21
0
1
0
1
8243 Port Selected
Port 4
Port 5
Port 6
Port 7
P22
0
0
1
1
P23
0
1
0
1
Function Defined
Read from Port
Write to Port
OR with Port
AND with Port
The actual I/O operation within the 8243 device is strobed by the subsequent low-to-high transition of PROG.
Observe that external logic must transmit data to an 8243 I/O port on the high-to-Iow transition of PROG. External logic
must read data output after the low-to-high transition of PROG. These signals to external logic are shown in Figure
6-22. Let us take a more careful look at this figure.
.
The 8243 device select CS is derived in some fashion from the four high-order lines of the 8048 I/O Port 2. The manner
in which we decode CS from these four lines is not relevant: however. the fact that we are generating CS in this fashion
means that any 8243 access instruction must be bracketed by instructions that select and then deselect the 8243
device.
It is not a good idea to leave the 8243 device selected when you are not accessing it: therefore do not leave high-order
bits of I/O Port 2 in a condition that would select the 8243 device while the device is supposed to be idle.
6-58
The PROG signal connecting the 8048 to the 8243 requires no explanation. The signal is output by the 8048 with timing required by the 8243.
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The READ and WRITE strobes created in Figure 6-22 identify the time at which external logic must either read data
from an I/O port. or write data to an I/O port however. the I/O port is not itself identified. The READ and WRITE strobes
would have to be qualified by P20 and P21 on the high-to-Iow transition of PROG in order to create READ and WRITE
strobes specific to any given I/O port. Here. for example. is the logic which would make READ and WRITE specific to I/O
Port 5:
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P20
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READ
~
READ 5
7474.
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Q ..........- - - - - 1
D
PROG
-X)-------ICLK
WRITE
CI/l
WRITE 5
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Referring to the timing in Figure 6-22. let us first look at the READ strobe. This signal must go true on the high-to-Iow
transition of PROG - but only if P22 and P23 are both low. READ can stay high until the device is deselected. providing external logic uses the low-to-high transition of READ or timing immediately thereafter. in order to place data at the
required I/O port - whence it can be read by the 8048. We obtained the required waveform by using the complement
of CS as a CLEAR input to the READ 7474 flip-flop. Thus while the 8243 device is not selected READ will be low. The
NOR of P22 and P23 becomes the D input to the READ flip-flop; this input will be high only when P22 and P23 are both
low - and that specifies a Read operation. On the high-to-Iow transition of PROG. PROG goes low-to-high. and that
clocks the READ flip-flop Q output high. READ subsequently stays high until CS goes high again. at which point the
READ flip-flop is cleared and READ goes low.
A 74107 master-slave flip-flop creates the WRITE pulse. The high-to-Iow transition of PROG marks the instant at which
P22 and P23 must be decoded to determine that a non-read operation is in progress. but the actuallow-to-high transition WRITE must not occur until the subsequent low-to-high transition of PROG.
The 74107 modifies the Q 1 output on the trailing edge of ClK. based on the JK inputs at the leading edge of ClK; thus
WRITE logic requirements are met.
6-59
DATA SHEETS
This section contains specific electrical and timing data for the following devices:
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8048/8748/8035 }
8049/8039
8041/8021
8243 liD Expander
One-Chip Microcomputers
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6-01
8048/8748/8035
ABSOLUTE MAXIMUM RATINGS·
Ambierit ,Temperature Under Bias ........... ooe to 70°C
Storaga Temperature ................... -65°C to +150 oe
Voltage On Any Pin With Respect
to Ground ............................. -0.5V to +7V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 Watt
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied.
D.C. AND OPERATING CHARACTERISTICS
Symbol
Parameter
TA = o°c to 70°C, VCC = V DD = +5V ±10%*, VSS= OV
Limits
Typ.
Min.
Unit
Max.
V IL
InpLlt Low Voltage
(All Extept XTALl, XTAL2)
-.5
.8
V
V IH
Input High Voltage
(All Except XTAL 1,XTAL2,RESET)
2.0
Vcc
V
3.0
Test Conditions'
V IH1
Input High Voltage (RESET,XTAL1)
Vcc
V
VOL
Oqtput Low Voltage
(BUS, RD, WR, PSEN, ALE)
.45
V
IOL = 2.?mA
V OL1
Output Low Voltage
(All Other Outputs Except PROG)
.45
V
IOL = 1.6mA
VOL2
Output Low Voltage (PROG)
.45
V
IOL = 1.0mA
V OH
OlJtpu!...!::!.ig~oltage
2.4
V
IOH = 100J..IA
2.4
V
IOH = 50J..IA
(BUS, RD, WR, PSEN, ALE)
VOH1
Output High Voltage
(All Other Outputs)
IlL
Input Leakage Current
(Tl, EA, INT)
±10
J.1A
VSS:!(VIN:!(VCC
IOL
Output Leakage Current (BUS, TO)
(High impedance State)
-10
J.1A
Vcc >VIN~VSS +.45
I DO
V DO Supply Current
10
20
mA
100+ Icc
Total Supply Current
65
135
mA
A.C. CHARACTERISTICS
Symbol
TA = o°c to 70°C, Vcc = VOO = +5V ±10%*, Vss= OV
Parameter
8048/8748
8035/8035L
Min. Max.
8748-8
8035-8
Min. Max.
Unit
Conditions (Note 1)
tLL
ALE Pulse Width
400
600
ns
tAL
Address Setup to ALE
150
150
ns
tLA
Ai:ldress Hold from ALE
80
80
ns
tcc
Control Pulse Width (PSEN, RD, WR)
900
1500
ns
tow
Data Setup before WR
500
640
ns
tWD
Data Hold After WR
120
120
ns
CL = 20pF
tCY
Cycle Time
2.5
4.17 15.0
J.1s
6 MHz XTAL
(3.6MHz XTAL for -8)
tOR
Data Hold
tRD
PSEN, RD to Data In
0
tAW
Address Setup to WR
tAD
Address Setup to Data In
tAFC
Address Float to RD, PSEN
*Standard 8748 and 8035 ±5%,
t 1 0%
available.
15.0
200
0
500
230
750
950
1450
0
Control Outputs:
aUSOutputs:
ns
ns
ns
260
0
Notel:
200
ns
ns
CL = 80 pF
CL=150p;, tCy=25fJs
Data sheets on pages 6-02 through 6-014 are reprinted by permission of Intel Corporation, Copyright 1978.
6-D2
8048/8748/8035
A.C. CHARACTERISTICS
TA
= O°C to 70°C, Vee = 5V±10%
- •..
C
Symbol
~o
tcp
Port. Control Setup Before Falling
Edge of PROG
110
c:
tpc
CJ
-.
tpR
Port Control. Hold After Falling
Edge of PROG
140
ns
PROG to Time P2 Ir)put Must Be Valid .
810
ns
LLI
Q.
o
~
en
LLI
Parameter
.. _.
Min.
Max.
Unit
ns
top
Output Data Setup Time
220
ns
tpo
Output Data Hold Time
65
ns
tPF
Input Data Hold Time
110
ns
<
tpp
PROG Pulse Width
c/J
LLI
tPL
c:
tLP
I-
<
(j
oC/)
C/)
Z
oen
1510
ns
Port 2 I/O Data Setup
400
ns
Port 2 I/O Data Hold
150
ns
C/)
o
~
<
C
<
@
WAVEFORMS
PORT 2 TIMING
A~E
J
\'--..........---~
EXPANDER
PORT
OUTPUT
PCH
EXPANDER
PORT
INPUT
PCH
PROG
6-D3
Test Conditions
8048/8748/8035·
WAVEFORMS
Instruction Fetch Fr~m External Program Memory
l:··~~-'-LL -=1·_·__ ._- ~y-ALE
J
----'I
'--_____;-1~-----'L
PSEN
BUS
INSTRUCTION
Read From External Data Memory
ALE
J
L
RD
BUS
Write to External Data MemorV
ALE
J
L
WR
BUS
WARNING:
An attempt to program a missocketed 8748 will result in severe
damage to the part_ An indication of a properly socketed part is the
appearance of the ALE clock output. The lack of this clock may
be used to disable the prqgrammer.
6-04
8048/8748/8035
Data show that constant exposure to room level flourescent lighting could erase the typical 8748 in approxmately 3 years while it would take approximately 1 week
to cause erasure when exposed to direct sunlight. If the
8748 is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels are available
from Intel which should be placed over the 8748 window
to prevent unintentional erasure.
Programming Options
The 8748 EPROM can be programmed by either of two
Intel products:
c
w
~
a::
o
D.
a::
·1. PROMPT-48 Microcomputer Design Aid, or
2. Universal PROM Programmer (UPP-101 or UPP-1021
peripheral of the Intelleci!!l Development System with a
UPP-848 Personality Card.
o
The recommended erasure procedure for the 8748 is exposure to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity X exposure time) for erasure should be a minimum of 15W-sec/cm 2 • The erasure time with this dosage
is approximately 15 to 20 minutes using an ultraviolet lamp
with a 12000tIW/cm 2 power rating. The 8748 should be
placed within one inch from the lamp tubes during erasure.
Some lamps have a' filter on their tubes and this filter
should be removed before erasure.
tJ
~
iii
w
I-
ct
8748 Erasure Characteristics
CI)
CI)
The erasure characteristics of the 8748 are such that
erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A).
It should be noted that sunlight and certain types of flourescent lamps have wavelengths in the 300()'4000A range.
g
ct
all
w
Z
a::
oCD
CI)
o
:!:
ct
c
ct
WAVEFORMS
Combination ProgramNerify Mode (EPROM's Only)
f---------
@
PROGRAM
--------'*0---
I~----PROGRAM----
TO
DBO-DB7
J--
---<
DATA TO BE
PROGRAMMED VALID
NEXT ADDR
VALID
x==
NEXT
ADDRESS
LAST
ADDRESS
.":~: ~= = = = = = = = = = =-I-O=~=~:OW~- 'U~_-~-:_- _--I
~
--,'-------_
__________________________
~--- --""'\.'-_____L..;........¥J
Verify Mode (ROM/EPROM)
TO.RESET
\ __-----11
~\\.-. _ _- - - J/
=>---
---<'-___A_~_~_~_Js_S
ADDRESS
(0-7) VALID
_
____________J)('__________A_D_D_R_E_SS_(8_-_9)_V_A_L_ID________
s
__JX'__~_~_~T_VD_A~_iD_A_'>_
-
-
-
-
-
-
N_E_X_T_AD_D_R_E_SS_V~A-L-ID--------------
___________
-
__
3. THE FOLLOWING CONDITIONS MUST BE MET:
TTL '1'
AOa TTL '0'
THIS CAN BE DON'E USING 10K RESISTORS TO Vee. Vss RESPECTIVELY.
4. Xl AND X2 DRIVEN BY 3 MHz CLOCK WILL GIVE 5 psec ICY. THIS IS GOOD
FOR -8 PARTS AS WELL AS NON -8 PARTS.
NOTES:
1. PROG MUST FLOAT IF EA IS LOW (i .•.• ~ 25V). OR IF TO
FOR THE 8041 PROG MUST ALWAYS FLOAT.
2. VEAH FOR 8041· 11.4V MIN .• 12.6V MAX.
__J)(~·
\'-----
cs=
5V FOR THE 8741.
6~D5
8048/8748/8035
AC TIMING SPECIFICATION FOR PROGRAMMING
TA-25°C+5°C
, Vcc=5V+5%
- , Voo=25V+1V
Min.
Parameter
Symbol
"
tAW
Address Setup,Time to RESET I
4tcy
tWA
Address Hold Time After RESET I
4tcy
tow
Data ,in Setup Time to PROG 1
4tcy
two
Data, in Hold Time After PROG I
4tcy
tPH
RESET Hold Time to Verify
4tcy
tvoow
Voo
4tcy
tVOOH
Voo Hold Time After PROG I
0
tpw
Program Pulse Width
50
trw
Test 0 Setup Time for Program Mode
41cy
41cy
twr
Test 0 Hold Time After Program Mode
too
Test btoData Out Delay
tww
RESET Pulse Width to Latch Address
41cy
tr.
tf
Max.
Unit
,':'
,
,Te.(eo~ffitl~';'/;';;:
<'"
60
MS
41cy
Voo and PROG Rise and Fall Times
0.5
tCY
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA 1
41cy
2.0
p's
p's
Note: If Test 0 is high too can be triggered by RESET I.
DC SPECIFICATION FOR PROGRAMMING
TA = 25°C ± 5°C, Vee = 5V ± 5%, Voo = 25V ± ,1V
Symbol
Parameter
Min.
Max.
Unit
VOOH
Voo Program Voltage High Level
24.0
26.0
V
VOOL
Voo Voltage Low Level
4.75
5.25
V
VPH
PROG Program Voltage High Level
21.5
24.5
V
VPL
PROG Voltage Low Level
0.2'
V
VEAH
EA Program or Verify Voltage High Level
VEAL
21,5
24.5
V
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
mA
IpROG
PROG High Voltage Supply Current
16.0
mA
lEA
EA High Voltage Supply Current
1.0
mA
6-06
Test Conditions
8049/8039
w
Ambient Temperature Under Bias ........ 0° C to 70° C
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin With
Respect to Ground ...................... -0.5V to +7V
Power Dissipation .... . . . . . . . . . . . . . . . . . . . . .. 1.5 Watt
·COMMENT: Stresses above those listed und9t "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
a:
o
u
D.C. AND OPERATING CHARACTERISTICS
TA
ABSOLUTE MAXIMUM RATINGS·
c
~
a:
oD.
= DoC to
70°C, Vee
= Voo = +5V ±1 0%. Vss = OV
~
u)
w
~
gen
Symbol
Limits
Parameter
Min.
Unit
Typ.
Test Conditions
Max.
VIL
Input Low Voltage
(All Except XTALl. XTAL2)
-0.5
0.8
VIH
w
Input High Voltage
(All Except XTALl. XTAL2. RESET)
2.0
Vee
V
a:
oCO
VIHl
Input High Voltage (R ESET. XTALl)
3.0
Vee
V
o
VOL
Output Low Voltage
(BUS. RD. WR. PSEN. ALE)
0.45
V
IOL
= 2.0mA
VOLl
Output Low Voltage
(All Other Outputs Except PROG)
0.45
V
IOL
= 1.6mA
VOH
Output High Voltage
(BUS. RD. WR. PSEN. ALE)
2.4
V
IoH
= 100J1A
VOHl
Output High Voltage
(All Other Out puts)
2.4
V
IOH
= 50J1A
IlL
Input Leaka~c Current
(Tl. EA. INT)
IOL
Output Leakage Current (Bus. TO)
(H}gh Impedance State)
100
Power Down Supply Current
en
<
all
Z
en
~
<
c
c(
@
±10
loo+lce Total Supply Current
A.C. CHARACTERISTICS
V
TA =
o°c to 70 n C.
J1A
VSS~VIN~Vee .
-10
J1A
Vee~VIN~VSS + 0.45
20
50
mA
TA
75
140
mA
TA = 25°C
Vee = Voo
= 25°C
= +5V ±10%. Vss = ov
8049/8039
Unit
Parameter
Symbol
Min.
Conditions
Max.
ns
tLL
ALE Pulse Width
400
tAL
Address Setll[J to ALE
150
ns
80
ns
tLA
Address Hold from ALE
tee
Control Pulse Width (PSEN. RD. WR)
900
ns
tow
Data Set·Up Before WR
500
ns
two
Data Hold After WR
120
ns
CL = 20 pF
tey
Cycle Time
2.5
15.0
J1S
6 MHz XTAL
tOR
Data Hold
0
200
ns
tRO
PSEN. RD to Data In
tAW
Address Setup to WR
500
tAD
Address Setup to Data In
tAFe
Address Float to RD. PSEN
A.C. TEST CONDITIONS
950
0
Control Outputs: CL = 00 pF
6-07
ns
ns
230
ns
ns
BUS Outputs: CL = 150 pF
tey = 2.5J1s
8049/8039
WAVEFORMS
Instruction Fetch From External Program Memory
I -tll--I
--------~y--------
ALE
J I. . ________. .
L
- tAFcl-ta;-i
----------~--~~
~--------------
BUS
INSTRUCTION
Read From External Data Memory
ALE
J
l-4--f(;C-1
RD
---------~I
'm
BUS
L
-----------
~I
-I I
".OATING
11- "'~
F L O A T I N G - - - I = - t - O - A - T - I N - G - ,- - -
.I-'A,,~I
Write To External Data Memory
ALE
J
I-tce
WR
-------.1
Itow
BUS
4-tAW_
6-08
L
8041/8741
ABSOLUTE MAXIMUM RATINGS*
c
w
~
oD.
c:
c:
o
AmbientTemperature Under Bias ........ O°C to 70°C
Storage Temperature .. . . . . . . . . . . . .. -65°C to +150°C
Voltage on Any Pin With
RespecttoGround ...................... 0.5Vto+7V
Power Dissipation .. . . . . . . . . . . . . . . . . . . . . . . .. 1.5 Watt
o
D.C. AND OPERATING CHARACTERISTICS
~
u)
w
TA
~
o
(I)
U
= O°C to 70°C, Vcc = Voo = +5V
CI/:I
w
Z
c:
o
±5%, Vss
= OV
Limits
Symbol
Parameter
Min.
Max.
Unit
VIL
Input Low Voltage(AIi
Except Xl. X2)
-0.5
O.B
V
VIH
Input High Voltage (All
Except Xl. X2 RESET)
2.0
Vcc
V
VIH2
Input High Voltage (Xl.
RESET)
3.0
Vcc
V
VOL
Output Low Voltage (Oo-D7.
Sync)
0.45
V
IOL
= 2.0
VOL2
Output Low Voltage (All
Other Outputs Except Prog)
0.45
V
IOL
= 1.6 mA
VOH
Output High Voltage (OO-D7)
2.4
V
IOH = -400J.lA
VOHI
Output High Voltage (All
Other OutputS)
2.4
V
IOH = -50J1.A
III
Input Leakage Current
(To. T,. RD. WR. CS. Ao. EA)
±10
pA
Vss
~
IOL
Output Leakage Current
(Oo-D7. High Z State)
±10
pA
Vss
+ 0.45 ~ VIN
100
Voo Supply Current
10
25
mA
65
135
mA
(I)
oct
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
In
Typ.
Test Conditions
(I)
o
~
oct
c
oct
@
Icc + 100 Total Supply Current
Output Low Voltage (Prog)
VOL3
rnA
VIN
~
Vee
V
IOl
IlI1
Low Input Source Current
PlO-P17 P20-P27
0.4
mA
Vll
= 1.0 mA
= O.BV
IlI2
Low Input Source Current
RESET.SS
0.2
mA
VIL
= O.BV
0.45
~
Vec
A.C. CHARACTERISTICS
TA
= O°C to 70°C, Vcc = Voo = +5V
±5%, Vss
= OV
DBB Read:
Symbol
Parameter
8741
Min.
8041
Max.
Min.
Max.
Units
tAR
CS, Ao Setup to RD ,
60
0
ns
tRA
CS, Ao Hold After RD t
30
0
ns
tRR
RD Pulse Width
tAD
CS, Ao to Data Out Delay
tRD
RD , to Data Out Delay
tOF
RD t to Data Float Delay
tRV
Recovery Time Between Reads
And/Or Write
tCY
Cycle Time
300
2)( tCY
250
370
200
10
ns
150
ns
150
ns
10
140
tCY
= 2.5,..s
ns
100
ns
1
1
,..S
2.5
2.5
,..S
6-D9
Test Conditions
6 M Hz Crystal
8041/8741
DBB Write:
Symbol
8741
Max.
Parameter
Min.
8041
Max.
Min.
Units'
tAW
CS, Ao Setup to WR ,
60
0
ns
tWA
CS, Ao Hold After WR t
30
0
ns
tww
tow
two
WR Pulse Width
300
. Data 'Setup to WR t
Data Hold After WR t
250
ns
250
2)( tCY
150
ns
30
0
ns
Test Conditions
tCY
= 2.5 ",s·
A.C. TEST CONDITIONS
DrDo Outputs
RL = 2.2k to Vss .
4.3k to Vee
CL
= 100 pF
WAVEFORMS
Read Operation -
Data Bus Buffer Register
(SYSTEM'S
ADDR ESS BUS)
~OR Ao
~---------------------
I---------.Rv----t-------I
I----·R.----I
(R EAD CDNTRO.l)
--.RO-I ."
DATA BUS
(OUTPUT)
Write Operation -
Cl: DR Ao
~
-
tDF
l
--"'<----""m"d>>------Data Bus Buffer Register
r
4~~.A-w---l1------.w-w------IJ--~~~A--~----------------- . .-f L. .
V
DATA
DATA BUS __________________
DATA
J \J--DATAVALID-" _ _ ~__________________
~_ _
MAY CHANGE
MAY CHANGE
~
!INPUT)
J'IJ
6-010
(SYSTEM'S
ADDR ESS BUS)
'w"''''''''''
8041/8741
8748 Erasure Characteristics
c
w
~
a:
oD..
a:
o
(J
~
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~
C3
oCI)
CI)
ct
""
w
The erasure characteristics of the 8748 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
room level fluorescent lighting could erase the typical
8748 in approximately 3 years while it would take approximately one week to cause erasure when exposed
to direct sunlight. If the 8748 is to be exposed to these
types of lighting conditions for extended periods of.
time, opaque labels are available from Int~1 which
should be placed over the 8748 window to prevent
unintentional erasure.
The recommended erasure procedure for the 8748 Is exposure to shortwave ultraviolet light which has a wavelength of 2537 A. The Integrated dose (I.e., UV Intensity
x exposure time) for erasure should be a minimum of 15
W-sec/cm 2• The erasure time with this dosage Is approxImately 15 to 20 minutes using an ultraviolet lamp with a
12,000 JAW/cm 2 power rating. The 8748 should be placed
within one inch of the lamp tubes during erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.
A.C. TIMING SPECIFICATION FOR PROGRAMMING
TA = 25°C ±5°C, Vee = 5V ±5%, Voo = 25V ±1V
Z
a:
oIII
Symbol
Min.
Parameter
Max.
Unit
60
MS
Telt Conditions
CI)
o
~
ct
ct
c
@
tAW
Address Setup Time to RESET I
4tcy
tWA
Address Hold Time After RESET I
4tcy
tow
Data in Setup Time to PROG I
4tcy
two
Data in Hold Time After PROG I
4tcy
tPH
RESET Hold Time to Verify
4tcy
tvoow
Voo
4tcy
tVOOH
Voo Hold Time After PROG I
0
tpw
Program Pulse Width
50
tTW
Test 0 Setup Time for Program Mode
4tcy
tWT
Test 0 Hold Time After Program Mode
4tcy
too
Test 0 to Data Out Delay
tww
RESET Pulse Width to Latch Address
4tcy
tr.lt
Voo and PROG Rise and Fall Times
0.5
tey
CPU Operation Cycle Time
5.0
tRE
RESET Setup Time Before EA I
4tcy
Note:
If
TEST 0 is high. too
can
4tcy
2.0
'"'s
'"'S
Min.
Max.
Unit
24.0
26.0
V
be triggered by RESET 1.
D.C. SPECIFICATION FOR PROGRAMMING
TA = 25°C ±5°C, Vee = 5V ±5%, Voo = 25V ±1V
Symbol
Parameter
VOOH
Voo Program Voltage High Level
VOOL
Voo Voltage Low Level
4.75
5.25
V
VPH
PROG Program Voltage High Level
21.5
24.5
V
0.2
V
21.5
24.5
V
VPL
PROG Voltage Low Level
VEAH
EA Program or Verify Voltage High Level
VEAL
EA Voltage Low Level
5.25
V
100
Voo High Voltage Supply Current
30.0
rnA
IPROG
PROG High Voltage Supply Current
16.0
rnA
lEA
EA High Voltage Supply Current
1.0
rnA
6-011
Test Conditions
8041/8741
WAVEFORMS
Combination ProgramlVerify Mode (EPROMs Only)
1 - - - - - - - - - PROGRAM
----------t--- VERIFY--~FI~'---- PROGRAM - - - - -
------"'\.
TO
DBO-DB7
PZO-P,
'J--.
DATA TO BE
PROGRAMMED VALID
--
-<
NEXT
ADDR
VALID
X=='
NEXT
ADDRESS
LAST
ADDRESS
, :~~: -~- -'- -'~ ~= - - ~ - - - - -~ -'- - - - -_'D-,_~ ·~ D~W~:Df,'~_-~·-,'_-_-'
-J---------------------
:~ ------""'\"'------l..;..._Jt "
1-1.
--''''--------
Veriiy Mode (ROM/EPROM)
VERIFY MODE (ROM/EPROMI
TO,RESET
DBO-DB7
Pzo-P,
~"'
.I/
________
\'--_----J/
J--
\'"----
NEXT
, ADDRESS
______-J)("'______
A_D_D_RE_S_S_(8_-_91_V_A_L_ID_ _ _ _ _
6-012
.I)(~_____N_E_X_T_A_D_D_R_ES_S_V_A_L_ID_ _ _ _ _ _ _ __
8243
'COMMENT: Stresses above thoselisted u~der ';Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional ~p(Jra.
tion of the device at these or any other conditions above.,
those indicated in the operational sections of this speci'i·} :':\'
cation is not implied. Exposure to absolute maximum,'
rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS·
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Ambient Temperature Under Bias . . . . . . . . . o°c to 70"C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt
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D.C. AND OPERATING CHARACTERISTICS
Max;
Units
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee+0 . 5
V
VOL1
Output Low Voltage Ports 4-7
Symbol
VIL
Parameter
Min.
Typ.
Test Conditions
0.45
V
IOL = 5 mA *
1
V
IOL = 20 mA
V
IOH= 240pA
VOL2
Output Low Voltage Port 7
VOH1
Output High Voltage Ports 4·7
2.4
11L1
Input Leakage Ports 4·7
-10
20
pA
Vin = Vee to OV
IIL2
Input Leakage Port 2, CS, PROG
-10
10
pA
Vin = Vee to OV
VOL3
Output Low Voltage Port 2
.45
V
ICC
Vee Supply Current
20
mA
VOH2
Output Voltage Port 2
IOL
Sum of all IOL from 16 Outputs
100
mA
10
2.4
IOL = 0.6 mA
IOH= 100pA
5 mA Each Pin
·See following graph for additional sink current capability.
A.C. CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Conditions
100
ns
80 pF Load
tA
Code Valid Before PROG
ts
Code Valid After PROG
60
ns
20 pF Load
te
Data Valid Before PROG
200
ns
80 pF Load
tD
Data Valid After PROG
20
ns
20 pF Load
tH
Floating After PROG
0
ns
20 pF Load
150
tK
PROG Negative Pulse Width
900
ns
tes
CS Valid Before/After PROG
50
ns
tpo
Ports 4-7 Valid After PROG
tLP1
Ports 4-7 Valid Before/After PROG
tAee
Port 2 Valid After PROG
700
100
100 pF Load
ns
750
6-013
ns
ns
80 pF Load
8243
WAVEFORMS
PROG
~-----------------tK----------------~
PORT 2
FLOAT
..
FLOAT
t ACC
OUTPUT
VAllO
PORT 2
~tpo
OUTPUT
VALID
PR EVIOUS OUTPUT VALID
PORTS 4·7
-
tiP
PORTS 4-7
INPUT VALID
tcs
6-014
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IX:
Chapter 7
ZILOG
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Zilog Z80 microcomputer devices have been designed as 8080A enhancements. In fact, the same individuals
responsible for designing the 8080A CPU at Intel designed the zao devices at Zilog. The 8085, described in
Chapter 5, is Intel's 8080A enhancement.
.
. .
The Z80 instruction set includes all 8080A instructions as a subset. In deference to rational necessity,
however, neither the Z80CPU, nor any of its support devices attempt to maintain pin-for-pin compatibility with
8080A counterparts. Compatibility is limited to instruction sets and general functional capabilities. A program
that has been written to drive. an 8080A microcomputer system will also drive the ZSO system - within certain limits; for example, a ROM device that has been created to: implement object programs for an 8080A
microcomputer system can be physically remo~ed and used in 'a Z80 system.
But Z80-8080A comp~tibility does extend ~omewhatfurther, since most support devices that have been
designed for the 8080A CPU will also work with a Zeo CPU; therefore in many cases you will be able to upgrade
an 8080A microcomputer system to a Z80, confining hardware' modifications to the CPU and its immediate interface o n l y . '
.
It is interesting to note that the Z80 pins and signal interface is far closer than the 80S5 to the three-chip S080A
configuration illustrated in 8QSOA chapter: Also, whereas the Z8Q instruction set is greatly expanded as compared to
the 8080A the 8085 instruction set 'contains just two new instructions. However, both the Z80 and the 8085 have
resolved the two most distressing problems associated wi~h the 8080A~ the three-chip 8080A CPU has in both cases
been reduced to one chip, and the three 8080Apower supplies have in both cases been reduced to a single +5V power
supply.
.
.
ZILOG, INC., manufacturers of the Z80, are located at:
10460 Bubb Road
Cupertino, California 95014
The official second source for Zilog products is:
MOSTEK, INC.
1215 West Crosby Road
Carrollton, Texas 75006
N-Channel MOS technology is used for all Z80 devices.
THE
Z80 LSI
TECHNOLOGY
zao CPU
Functions implemented on the ZSO CPU are illustrated in Figure 7-1. They represent "typical" CPU logic,
equivalent to the three devices: 8080A CPU, 8224 Clock and 8228 System Controller.
.
A SUMMARY OF ZSO/SOSOA DIFFERENCES
Weare going to summarize Z80/S080A differences before describing differences in detail. If you know the
SOSOA well, read on; if you do not, come back to this summary after reading the rest of the Z80.CPU description. We will also contrast the ZSO and the 80S5, where relevant
. .
,
For the programmer, the Z80 provides more registers and addressing modes t~an the 8080A, plus a much larger
instruction set.
Significant hardware features are a single power supply (+5V), a single system clock signal, an additional interrupt, and logic to refresh dynamic memories.
....
.
.
7-1
Direct Memory
Access Control
Interface Logic
Interface Logic
Programmable
Timers
Read Only
Memory .
Interface Logic
I/O Ports
Memory
Figure 7-1. Logic Functions of the Z80 CPU
The 8085 also has a single power supply and a single system clock signal. The 8085 has three additional interrupts. but
lacks logic to refresh dynamic memories.
I.s the ZBO CPU indeed the logical next BOBOA evolution?
Hardware aspects of the BOBOA represent its weakest features, as compared to principal current competitors.
Specifically. the fact that the 8080A is really a three-chip CPU is its biggest single problem: three chips are always
going to cost more than one. Next. the fact that the 8080A requires three power supplies (+5V. -5V and + 12V) is a very
negative feature for many users and the desirability of going to a single power supply is self-evident: the Z80 requires a
single +5Vpower supply. This is also true of the 8085.
The problems associated with condensing logic from three chips onto one chip are not so straightforward. Figure 7-2 illustrates the standard three-chip 8080A CpU. Let us assume that the three devices are to be condensed into a single
chip. Asterisks (*) have been placed by the signals which must be maintainf~d if the single chip is to be hardware compatible with the three chips it replaces. Forty-three signals are asterisked. therefore the standard 40-pin DIP cannot be
used. The 'problem is compounded by the fact that not all 8080A systems use an 8228 System Controller. Some 8080A
systems use an 8212 bidirectional 1/0 port to create control signals. A few' of the earliest 8080 systems use neither the
8228 System Controller. nor an 8212 1/0 port: rather external logic decodes the Data Bus when SYNC is true in order to
generate control signals; for example. that is how the TMS5501 works. We must therefore conclude that any attempt
7-2
to reduce three chips to cine will create a product that is not pin compatible with the 8080A: and. indeed. the Z80 is not
pin compatible. What Zilog has done is include as many hardware enhancements as possible within the confines of a
40-pin DIP that must be philosophically similar to the 8080A. without attempting any form of pin compatibility. Figure
7-2 identifies the correlation between Z80 signals and 8080A signals. Notice that there is a significant similarity.
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Figure 5-3 is equivalent to Figure 7-2. comparing 8085 and 8080A signals. Z80 signals are far closer to the 8080A
three-chip set than the 8085.
Here is a summary of the hardware differences:
1)
2)
Clock logic is entirely within the Z80.
3)
The complex. two clock signals of the 8080A have been replaced by a single clock signal.
4)
Automatic dynamic memory refresh logic has been included within the CPU.
5)
Read and write control signal philosophy has changed. The 8080A uses separate memory read. memory write. I/O
read and I/O write signals. The Z80 uses a general read and a general write. coupled with a memory select and an
I/O select. This means that if a Z80 CPU is to replace an 8080A CPU then additional logic will be required beyond
the Z80 CPU .. You will either have to combine the four Z80 control signals to generate 8080A equivalents. or you
will have to change the select and strobe logic for every I/O device. We will discuss this in more detail later.
6)
Address and Data Bus float timing associated with DMA operations have changed. The 8080A floats these busses
at the beginning of the third or fourth time period within the machine cycle during which a bus request occurs:
this initiates a Hold state. The Z80 has a more straightforward scheme: a Bus Request input signal causes the Data
and Address Busses to float at the beginning of the machine cycle: floating busses are acknowledged with a Bus
Acknowledge output signal.
7)
The Z80 has an additional interrupt request. In addition to.the RESET and normal 8080A interrupt request. the Z80
has a nonmaskable interrupt which is typically used to execute a short program that prepares for power failure.
once a power failure has been detected.
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The Z80 has reduced three power supplies to a single +5V power supply.
Now consider internal organization of the
zao in terms of instruction set compatibility and enhancement.
As illustrated by Table 7-3 the 8080A instruction set is. indeed. a subset of the Z80 instruction set. Unfortunately. the
Z80 uses completely new source program instruction mnemonics. therefore 8080A instructions carinot immediately be
identified. Technical Design Labs. Inc .. has an 8080-like Z80 assembly language .
2
20
.GND
• +6\1
II
·5V
+ 12V
21
13
1tmiiCi SYSTEM DMA REO
808010.
CPU
14
SYSTEM INT. REO.
NT. ENABlE
r,~[J1TAL
. .
14
TNW.~
~tt.
MNW~
.liESiN
.'2V~
.
INT-.
Ie
INTl·
Wi!
OBiN
. HLDA
1224
CLOCK
GENERATOR
DRIVER
10.0""1
10.1
IU
10.3
10.4
10.5
Ae
10.7
AS
22
15
II
10
4
I
5
4>1.·
W11'I"..;f
12
m
--2(7
19
DO
01
D2
03
D4
05
DB
07
4>2·
WArT·
READY·
RESET·.
SYNC·
STATUS STROBE
10.12
10.13
10.14
10.15 ...
,'-
L
17
21
~
~
~
~
~
13
8228
•
BIDIRECTIONAL.
BUS DRIVER •
~ ----,
DEN~.
1li'
•
Z80 equiv• . ,•. or new lign.ll.
Signlil reproduced by the zeo.
Signlil which mUlt be dupliclted by I
_
BUsAK
3'
~
•
17
GN
) ADDRESS BUS.
10.9
10.10
10.11
2[ 41
IS
.IV~
OND
HOlD·
• 10.0 125
2e
·10.1
27
·10.2
29
·10.3
30
·10.4
31
·10.5
32
·Ae
33
·10.7
34
·10.8
35
·10.9
I
·10.10
_AlL
·10.11
37
·10.12
J8
·10.13
JII
·10.14
J8
·10.15
SYSTlM
CONTROL
=t
\8
11
082
I
::
~
'11
20
7
'1 lORa MI
24
20
25
MREO RD
MREQ WR
lORa RO
7,KJ-"~
)DATABUh
085
DB8
017
iNTA
MEMR
MfMW
iiCiii
iiOw
~} TheM.,. zeo lignall
HALT
NMi
with no 808010.
counltlf'P8rt
... NPioclmont product.
Figure 7-2. The Standard 8080A Three-Chip System and Z80 Signal Equivalents
7-3
CONTROL BUS
There are very few unused object codes in the 8080A instruction set. The Z80 has therefore taken what few unused object codes there are. and used them to specify that an additional byte of object code. follows:
110111014-Spare 8080A object code
4-Specifies new Z80 object code follows
This results in most new Z80 instructions having 16-bit object codes; but simultaneously it means that a very large
number of new instructions can be added.
Any enhancement of the 8080A can include major changes within the CPU; providing the 8080A registers and status
flags remain as a subset of the new design. instruction compatibility remains. These are the principal enhancements
made by the Z80:
1)
The standard general purpose registers and status flags have been duplicated. This makes it very easy to handle
single-level interrupts. since general purpose register and Accumulator contents no longer need to be saved on the
Stack; instead. the program may simply switch to the alternate register set.
2)
Two Index registers have been added. This means that additional Z80 instructions can use indexed memory addressing.
2)
An Interrupt Vector register allows external logic the option of responding to an interrupt acknowledge by issuing
the equivalent of a Call instruction - which vectors program execution to a memory address which is dedicated
.
to the acknowledged external logic.
4)
A single Block Move instruction allows the contents of any number of contiguous memory bytes to be moved from
one area of memory to another. or between an area of memory and a single I/O port. You can also scan a block of
memory for a defined value by executing a Block Compare instruction.
5)
Instructions have been added to test or alter the condition of individual register and memory bits.
In contrast to the extensive enhancements of the Z80. the 8085 registers and status architecture are identical to the
8080A. There are only two additional instructions in the 8085 instruction set; however. the 8085. like the Z80. allows
Call instructions to be used when acknowledgi~g an interrupt - a particularly useful enhancement.
While on the surface the zao instruction set appears to be very powerful, note that instruction sets are very
subjective; right and wrong, good and bad are not easily defined. Let us look at some nonobvious features of the
zao instruction set.
.
.
First of all. the ex.ecution speed advantage that results from the new Z80 instructions is reduced by the fact that many
of these instructions require two bytes of object code. Some examples of Z80 instructions and equivalent 8080A instruction sequences with equivalent cycle times are given in Table 7-1.
Table 7-1. Comparisons of Z80 and 8080A
Instruction Execution Cycles
8080A
Z80
Instru ctions
LD
R.(lX
Cycles
+
d)
19
Instructions
LXI
DAD
MOV
H.d
IX
R;M
LD
RP.ADDR
20
LHLD
MOV
MOV
ADDR
C.L
B.H
SET
B.(HL)
15
MOV
ORI
tvlOV
A.M
MASK
·M.A
Cycles
10
10
227
16
5
'5
26
7
7
7
21
Also. a novice programmer may find the Z80 instruction set bewilderingly complex. At a time when the majority of potential microcomputer users are terrified by simple assembly language instruction sets. it is possible that users will
react negatively to an instruction set whose complexity (if not power) rivals that of many large minicomputers.
Many of the new Z80 instructions use direct. indexed memory addressing to perform operations which are otherwise
identical to existing 8080A instructions .. Now the zao has two new 16-bitlndex registers whose contents are added to
7-4
an a-bit displacement provided by the instruction code: this is the scheme adopted by the Motorola MC6aOO. This
scheme is inherently weaker than having a 16-bit. instruction-provided displacement. as implemented by the Signetics
2650. When the Index register is larger than the displacement. the Index register. in effect. becomes a base register.
When the Index register has the same size. or is smaller than the displacement. it is truly an Index register as described
in "Volume 1 - Basic Concepts". The Signetics 2650 implementation is more powerful.
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zao PROGRAMMABLE REGISTERS
We will now start looking at the Z80 CPU in detail, beginning with its programmable registers.
The Z80 has two sets of 8-bit programmable registers, and two Program Status Words. At any time one set of
programmable registers and one Program Status Word will be active and accessible.
In addition, the Z80 has a 16-bit Program Counter, a 16-bit Stack Pointer, two 16-bit Index registers, an 8-bit
Interrupt Vector and an 8-bit Memory Refresh register.
Figure 7-3 illustrates the Z80 registers. Within this figure, the 8080A registers' subset is shaded.
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These two 8-, bit registers
are sometimes treated ~
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Program Status Words
Primary Accumulators
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TsW'Il..J
t-~~-,-+-~~--t Secondary Accumulators/Data Counter
Secondary Accumulators/Data Counter
Secondary Accumulators/Data Counter
Stack Pointer
t---~:--::--~~-t. Program Counter
IV
Index Register X
Index Register V
Interrupt Vector
R
Memory Refresh Counter
IV
A'
B'
0'
H'
f
C'
E'
L'
Shaded registers represent the 8080A subset.'
Figure 7-3. zao Programmable Registers
The Z80 uses its Program Status Word, its A, B, C, 0, E, H, and L registers, plus the Stack Pointer and the Program Counter exactly as the 8080A uses these locations; therefore no additional discussion of these registers
is needed.
The Program Status Word, plus registers A, B, C, 0, E, Hand L are duplicated. Single zao instructions allow you to
switch access from one register set to another. or to exchange the contents of selected registers. At any time. one or
the other set of registers. but not both. is accessible.
There are two 16-bit Index registers, marked IXand IV. These are more accurately looked upon as base registers. as
will become apparent when we examine zao addressing modes.
The Interrupt Vector register performs a function'similar to the ICW2 byte of the 8259 PICU device (described
in the 8080A chapter). zao interrupt acknowledge logic gives you the option of initiating an interrupt service routine
with a Call instruction. where the high order address byte for the call is provided by the Interrupt Vector register. The
80a5 also provides this capability.
The Memory Refresh Counter register represents a feature of microcomputer systems which has been overlooked by everyone except Fairchild and Zilog. Dynamic memory devices will not hold their contents for very long.
irrespective of whether power is off or on. A dynamic memory must therefore be accessed at millisecond intervals.
Dynamic memory devices compensate for this short-coming by being very cheap - and dynamic refresh circuitry is
very simple. Using a technique akin to direct memory access. dynamic refresh circuitry will periodically access dynamic
memories. rewriting the contents of individual memory words on each access. About the only logic needed by dynamic
refresh is a counter via which it keeps track of its progress through the dynamic memory: that is the purpose of the zao
Memory Refresh Counter register. The zao also has 'a special DMA refresh control signal: therefore the zao provides
much of the dynamic refresh logic needed by dynamic memory devices.
7-5
zao ADDRESSING MODES
zao instructions use all of the aOaOA addressing modes; the ZaOalso has these two enhancements:
1)
A number of memory reference instructions use the IX and IV registers for indexed, or base relative addressing.
2)
There are some two-byte program relative Jump instructions ..
A memory reference instruction that uses the IX or IY register will include a single data displacement byte. The 8-bit value provided by the instruction object code is added to the 16-bit value
provided by the identified Index register in order to compute the effective memory address:
zao
INDEXED
ADDRESSING
PROGRAM
MEMORY
5d--
, ':::,IY
"
I
0. Cod,
"~~~ D;,~."me",
Effective Address
=
ppqq + dd
I
I
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•
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}
Memory
.
Reference
instruction
P. q and d represent any hexadecimal digits;
dd represents an 8-bit. signed binary value.
This is standard microcomputer indexed addressing and is less powerful than having the memory
reference instruction provide a 16-bit base address or displacement; for a discussion of these addressing modes see
"Volume 1 - Basic Concepts", Chapter 6.
.
The program relative. two-byte Jump instructions provided by the Z80 provide standard two-byte, program relative addressing. A single. 8-bit displacement is provided by the Jump instruction's object code: this 8-bit displacement is added. as a signed binary value, to the contents of the Program Counter - after the Program Counter has been incremented to point to the sequential instruction:
PROGRAM
MEMORY
Memory
Address
XX
ppqq-2
ppqq-l
ppqq
ppqq + 1
ppqq +2
Branch instruction op code ~
Displacement ~
dd
Program Counter
The next instruction object code will be fetched from memory location ppqq+2+dd. p. q. and d represent any hexadecimal digits. dd represents a signed binary. 8-bit value.
For a discussion of program relative addressing. see "Volume 1 - Basic Concepts"
The zao addressing enhancements are of significant value when comparing the zao to the aOaOA.
The value of the Index register comes not so much from having an additional addressing option. but rather IX and IY
allow an efficient programmer to husband his CPU register space more effectively. Look upon IX and IY as performing
memory addressing tasks which the 8080A would have to perform using the BC and DE registers. By freeing up the BC
and DE. registers for data manipulation, you can significantly reduce the number of memory reference instructions ex.
ecuted by the Z80.
7-6
The two-byte program relative Jump instruction is useful because in most programs 80% of the Jump instructions
branch to a memory location that is within 128 bytes of the Jump. That is the rationale for most microcomputers offering two-byte as well as three-byte Jump instructions.
zao STATUS
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The Z80 and 8080A both use the Program Status Word in order to storo status flags. These are the Z80 status
flags:
Carry (C)
Zero (Z)
Sign (S)
Parity/Overflow (P/O)
Auxiliary Carry (AC)
Subtract (N)
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Statuses are recorded in the Program Status Word by the Z80. as compared to the 8080A. as follows:
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No.
~ Bit No.
Is Iz IX est X Ip IX Ic ~ a080A Program Status Word
o
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3 2 1 0 ~ Bit
Is Iz IX rei X lij N Ic ~ zao Program Status Word
c(
The Parity/Overflow and Subtract statuses differ from the 8080A. All other statuses are the same. Note that
the Z80, like the 8080A, uses borrow philosophy for the Carry status when performing subtract operations. That is
to say. during a subtract operation. the Carry status takes the reciprocal value of any Carry out of the high-order bit. For
details see the 8080A Carry status descriptions given in the 8080A chapter.
The 8080A has a Parity status but no Overflow status. The Z80 uses a single status flag for both operations. which
makes a lot of sense. The Z80 Overflow status is absolutely standard. therefore only has meaning when signed binary
arithmetic is being performed - at which time the Parity status has no meaning. Within the Z80. therefore. this single
status is used by arithmetic operations to record overflow and by other operations to record parity. For a complete discussion of the Overflow status see "Volume 1 - Basic Concepts".
The Subtract status is used by the DAA instruction for BCD operations. to differentiate between decimal addition or
subtraction. The Subtract and Auxiliary Carry statuses cannot be used as conditions for program branching (conditional Jump. Call or Return instructions).
zao CPU
PINS AND SIGNALS
The Z80 CPU pins and signals are illustrated in Figure 7-4. Figure 7-2 providos the direct comparison between
Z80 CPU signals and the standard 8080A, 8228, 8224 three-chip systems.
Let us first look at the Data and Address Busses.
Ttle 16 address lines AO - A 15 output memory and I/O device addresses. The address lines are tristate: they may
be floated by the Z80 CPU. giving external logic control of the Address Bus. There is no difference between Z80 and
8080A Address Bus lines.
The Data Bus lines DO - D7 transmit bidirectional data into or out of the Z80 CPU. Like the Address Bus lines. the
Data Bus lines are tristate. The Z80 Data Bus lines do differ from the 8080A equivalont. The 8080A Data Bus is
multiplexed: status output on the Data Bus by the 8080A during the T2 clock period of very machine cycle is strobed
by the SYNC pulse. The Z80 does not multiplex the Data Bus in this way. The Z80 Data Bus lines operate at normal TTL
levels. whereas the 8080A Data Bus lines do not.
Control signals are described next; these may be divided into system control, CPU control
and Bus control. First we will describe the System control signals.
M1 identifies the instruction fetch machine cycle of an instruction's execution. Its function
is similar, but not identical to the 8080A SYNC pulse. The Z80 PIO device uses the low M1
pulse as a reset signal if it occurs without 10RO or RD simultaneously low.
Z80 SYSTEM
CONTROL
SIGNALS
MREO identifies any memory access operation in progress; it is a tristate control signal.
lORa identifies any I/O operation in progress. When 10RO is low. AO - A7 contain a valid I/O port address. lORa is
also used as an interrupt acknowledge; an interrupt is acknowledged by M 1 and lORa being output low - a u nique combination. since M1 is otherwise low only during an instruction fetch. which cannot address an I/O device.
7-7
RD is a tristate signal which indicates that the CPU wishes to read data from either memory or an I/O device. as
identified MREO or 10RO.
WR is a tristate control signal which indicates that the CPU wishes to write data to memory or an I/O device as indicated by MREO and 10RO. Some laO I/O devices have no WR input. These devices assume a Write operation when
10RO is low and RD is high. RD low specifies a Read operation.
The various ways in which the three control signals. M1. 10RO. and RD. may be interpreted are summarized in Table
7-5. which occurs in the description of the laO PIO device.
RFSH is a control signal used to refresh dynamic memories. When RFSH is output low. the current MREO signal
should be used to refresh dynamic memory. as addressed by the lower seven bits of the Address Bus. AO - A6.
Next we will describe CPU control signals.
All
1
40
2
39
3
4
38
A15
5
36
6
35
AS
7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A4
A12
~13
A14
D4
D3
~
--
--'"
8
D5
9
10
D6
+5V
D2
D7
DO
Dl
INT
NMi
HALT
37
-
--
ZOO
CPU
11
12
13
14
15
16
MREQ
17
18
·19
iORQ
20
Al0
A9
_
..
A8
A7
A6
A3
A2
Al
AO
GNO
..
RFSH .
.Ml
RESET
WSRQ
WAIT
WSAK
Wii
iID
PIN NAME
DESCRIPTION
TYPE
AO - A15
Address Bus
Trist
CPU clock
Output
Input
+5V.GND
Power and Ground
Figure 7-4. laO CPU Signals and Pin Assignments
7-8
HALT is output low following execution of a Halt instruction. The CPU now enters a Halt state
during which it continuously re-executes a NOP instruction in order to maintain memory refresh
activity. A Halt can only be terminated with an interrupt.
laO CPU
CONTROL
SIGNALS
c
w
WAIT is equivalent to the aOaOA READY input. External logic which cannot respond to a CPU
access request within the allowed time interval extends the time interval by pulling the WAIT input low. In response to
WAIT low. the Z80 enters a Wait state during which the CPU inserts an integral number of clock periods; taken
together. these clock periods constitute a Wait state.
o
a:
INT and NMI are t"\'o interrupt request inputs. The difference between these two signals is that NMI has higher
priority an~ cannot be disabled.
~
a:
oQ.
CJ
~
There are two Bus control signals.
en
w
RESET is a standard reset co!:'trol input. When the Z80 is reset. this is what happens:
g
The Program Counter. IV and
~
CI)
CI)
c(
ell
w
Z
a:
o
en
CI)
o
~
c(
cc(
@
R re~isters'
lao BUS
CONTROL
SIGNALS
contents are all set to zero.
Interrupt requests via INT'are disabled.
All tristate bus signals are floated.
BUSRQ and BUSAK are bus request and acknowledge signals. In order to perform any kind of DMA operation. external logic must acquire control of the microcomputer System Bus. This is done by inputting BUSRQ low; at the conclusion of the current machine cycle. the Z80 CPU will float all tristate bus lines and will acknowledge the bus request
by outputting BUSAK low.
zao -
8080A SIGNAL COMPATIBILITY
If you are designing a new product around the laO CPU, then questions of lao - aOaOA signal compatibility
are irrelevant; you will design for the CPU on hand.
If you are replacing an aOaOA with a laO, then it would be helpful to have some type of lookup table which
directly relates aOaOA signals to laO signals. Unfortunately, such a lookup table cannot easily be created. The
problem is that the Z80 is an implementation' of three devices; the 8080A CPU. the 8224 Clock. and 8228 System Controller; but there are very many 8080A configurations that do not include an 8228 System Controller.
Possibly the most important conceptual difference between the Z80 and 8080A involves read and write control signals.
The a228 System Controller develops four discrete control signals for memory read, memory write, I/O read and
I/O write. The zao has a general read and a 'general write, coupled with an I/O select and a memory select. By
adding iogic. it would be easy enough to generate the four discrete 8080A signals from the two Z80 signal pairs; here
is one elementary possibility:
.
MREa
AD
MREQ
WR
iORci
Ro
IORO
WR
zao·
aOaOA Equivalent
Signals
Signals
D
D
D
0
7-9
MEMR
MEMW
I/OR
I/OW
If your design allows it. however. it would be wiser to extend the Z80 philosophy to the various support devices surrounding the CPU. Recall from our discussion of 8080A supportdevices in Chapter 4 that every device requires separate device select and device access logic. For some arbitrary read operation. timing might be illustrated as follows:
Select
Read
\
______________________________
~r____\~
,
___________________
Strobe
With an 8080A scheme. select logic is decoded from Address Bus lines. while strobe logic depends on one of the four
control lines I/OR. I/OW. MEMR or MEMW. Using the Z80 philosophy. the memory select (MREO) or 1/0 select (lORO)
control, lines become part of the device select logic. while the read (RD) or write (WR) controls generate the strobe.
The zao has no interrupt acknowledge signal; rather it combines IORQ with M1 as follows:
IO:~ _______________~-------------Some Z~O support devices also check fora "Return-from-Interrupt" instruction object code appearing on the Data Bus
during an instruction fetch (when Ml and RD will both be low). This condition is used to reset interrupt priorities
among Z80 support devices.
.The aOaOA HOLD and HLDA signals are functionally reproduced by the zao BUSRQ and BUSAK signals.
The 8080A SYNC pulse has no direc't Z80 equivalent. Ml is pulsed low during an instruction fetch. or an interrupt
acknowledge. but it is not pulsed low during the initial time periods of an instruction's second or subsequent machine
cycles. Frequently the complement of M 1 can be used instead of SYNC to drive those 8080A peripheral devices
.
that require the SYNC pulse.
TheZaO has no signals equivalent to aOaOA INTE, WAIT or <1>2. There is also no signal equivalent to the a228
BUSEN.
If for any reason external logic must know when interrupts have been disabled internally by the CPU. then the Z80 will
be at a loss to provide any signal equivalent to the 8080A control signals. Remember INTE in an 8080A system tells external logic when the CPU has enabled or disabled all interrupts;since external logic can do nothing about interrupts
being disabled. and requesting an interrupt at this time does neither good nor harm. knowing that the condition exists
is generally irrelevant.
The single Z80 WAIT input serves the function of the 8080A READY input. Irrespective of when the WAIT is requested.
a Wait clock period will only be inserted between T2 and T3; moreover. as we will see shortly. there are certain Z80 instructions which automatically insert a Wait state. without waiting for external demand. You would need relatively
complex logic to decode instruction object codes. clock signal and the WAIT input if your Z80 system is to generate the
equivalent of an 8080A WAIT output. In all probability. it would be simpler to find an alternative scheme that did not
require a signal equivalent to the 8080A WAIT output.
The Z80 simply has no second clock equivalent to 8080A <1>2. Any device that needs clock signal <1>2 cannot easily be
used in Z80 configurations.
The 8228 BUSEN input is used by external logic to float the System Bus. In a Z80 system. CPU logic floats the System
Bus; therefore BUSEN becomes irrelevant.
The aOaOA CPU has no signals equivalent 'to zao RFSH, HALT and NMI.
RFSH applies to dynamic memory refresh only; it is irrelevant within the context of a Z80 - 8080A signal comparison.
NMI. being a nonmaskable interrupt request. also has no 8080A equivalent logic.
The zao HALT output needs some discussion. One of the more confusing aspects of the aOaOA is the interaction of Wait, Halt and Hold states. Let us look at these three states, comparing the zao and aOaOA configurations and in the process we will see the purpose of the zao HALT output.
The purpose of the Wait state is to elongate a memory reference machine cycle in deference to slow external memory
or I/O devices. The Wait state consists of one or more Wait clock periods inserted between T2 and T3 of a machine cycle. The 8080A and the Z80 handle Wait states in exactly the same way. except for the fact that the Z80 has no Wait
acknowledge output and under certain circumstances will automatically insert Wait clock periods.
7-10
The purpose of the Hold condition is to allow external logic to acquire control of the System Bus and perform Direct
Memory Access operations. Again both the Z80 and the 8080A have very similar Hold states. The only significant
difference is that the Z80 initiates a Hold state at the conclusion of a machine cycle. whereas the 8080A initiates the
Hold state during time period T3 or T 4. The 8228 System Controller also needs a high BUSEN input in order to float its
Data and Control Busses while the Z80 has no equivalent need.
Q
w
~
a:
oa.
a:
o
u
~
enw
The big difference between the Z80 and the 8080A comes within the Halt state. When the 8080A executes a Halt instruction. it goes into a Halt state. whi,ch differs from a Hold state. There are some complex interactions between Hold.
Halt. Wait and interrupts within 8080A systems. None of these complications exists in the Z80 system. since the Z80
has no Halt state. Afte~ executing a Halt instruction. the Z80 o~tputs HALT low. then proceeds to continuously execute
a NOP instruction. This allows dynamic memory refresh logic to continue operating. If you are replacing an aOaOA
with a zao, you must give careful attention to the Halt state. This is one condition where unexpected incompatibilities can arise.
~
g
zao TIMING AND INSTRUCTION EXECUTION
CI)
CI)
ct
IllS
w
Z
a:
o
m
CI)
o
:!!
ct
Q
ct
zao timing is conceptually similar to, but far simpler than aOaOA timing. Like the aOaOA,
the zao divides its instructions into machine cycles and clock periods. However. al1280 machine cycles consist of either three or four
clock periods. Some instructions always insert Wait clock periods. in which case five or six clock periods may be present ir"a machine cycle. Recall that 8080A machine cycles may,have three.,four or five clock periods.
The 808bA may require from one to five machine cycles in order to execute an instruction: Z80 instructions execute in
one to six machine cycles. If we shade optional machine cycles and clock periods. Z80 and 8080A instruction time subdivisions may be compared and illustrated as follows:
@
} 8080A
ackn~lfIledge
only
During input
or output
machine cycle'
only
7-11
zao clock signals are also far simpler than the aOaOA equivalent. Where the 8080A uses two clock signals the Z80
uses o'ne. Clock logic may be compared as follows:
Tl
T5
T3
T2
} OOOOA
Z80
INSTRUCTION FETCH EXECUTION SEQUENCES
As ~om'pared to the aoaOA, zao instructiol'! timing is '1larvelously simple. Gone is the SyNC pulse a~d the decoding cif Data Bus for status. Every instruction's timing' degenerat~s' into an instruction fetch, optionally followed by
memory orl/O read orwrite. Add to this a few variations for Wait sta'te, interrupt acknowledge and bus floating and you
are.done.'
. .
\,
,,'
..
.
,
.
-
.
'
Let us begin by looking at an instruction fetch. Timing is illustrated in Figure 7-5. Look at the instruction fetch timing
in the 8080A chapter to obtain an immediate comparison 9fthe Z80 and the 8080A.
~I--------- MCl Cycle ----'----~....~
T,
T,
AD - A15
MREQ
RD
MI
DBO - DB7
RFSH
Figure 7-5. Z80 Instruction Fetch Sequence
,
.
"
Referring to Figure 7-5; note that the instruction fetch cycle is identified by M1 output low during T1 and T2 (CD).
Since there is no status on the Data Bus to worry about. the Program Counter contents are output immediately on the
'
Address Bus and stay stable for the duration Qf T 1 and T2.
Since an instruction fetch is also a memory operation, MREO and RD controls are both output low. This occurs half-way
through T 1, at wh'ich time the Address Bus will stabilize. The falling edges of MREO i3nd RD can therefore be used to
select a memory device and strobe data out. The CPU polls data on the Data Bus at the rising edge of the T3 clock ((Z)).
7-12
Clock perods T3 and T 4 of the instruction fetch machine cycle are used by the Z80 CPU for internal operations.
These clock 'periods are also used to refresh dynamic memory. As soon as the Program Counter contents are taken off
the Address Bus (@l. the refresh address from the Refresh register is output on lines AO - A6 of the Address Bus. This
address stays on the Address Bus until the conclusion of T 4 (@).
cw
!;(
a:
oQ.
a:
o
u
~
enw
!;(
g
Since a memory refresh is a memory access operation. MREQ is again output low; however. it is accompanied by RFSH
rather than RD low. Thus memory reference logic does not attempt to read data during a refresh cycle.
A MEMORY READ OPERATION
,
.
,
Memory intenaqe logic respon~s to an instruction fetch and a memory read in exactly the same way. There are,
however, a few differeces between memory read and instruc~ion fetch timing. Memory read timing is illustrated
in Figure 7-~. The principal difference to note is that durin'g a memory read operation. the data is sampled on ,the falling
edge of the T3 clock pulse. wherea~ during an instruction fetch it is sampled on the rising edge of this clock pulse. Also
a normal memory read macbine cycle will consist of three clock periods. while the normal instruction fetch consists of
four «lock pe·rio·ds. R~mel"f1ber, al$9 t~at the Z80 identifies'i,lninstruction fetch machine cycle by outputting M 1 low during the firsttyvo clock periods of the instruction fetch machine cycle.
CI)
CI)
c(
....r . - - -
coli
Memory Read Cycle ----t~
w
Z
a:
oa:I
CI)
o
~
AO - A1S
c(
cc(
MREO
@
RD
-+------i------+--{
DATA BUS
(DO -- p71
Figure 7-6. Z80 Memory Read Timing
Memory Write Cycle
Tl
AO- A1S
n'
--"
T2
T3
\
\
,~
~
MEMORY AD DR
.}OIIIII"
.,
\
MREO
1
Co"'.
"
RD
\
WR
DATA BUS
J
OATA OUT
(DO - D7!
I
I
Figu're 7-7. Z80 Memory Write Timing
MEMORY WRITE
OPE~ATION
Figure 7-7 iIIu!)trates memory write' timing for the zao. Th~ only differences between memory read <:Ind memory
write timing are the obvious ones:' yvR is pulsed low for a write. and can be used as a strobe by memory interface
logic to read'd 9ta off the Data Bu~, '
. .
,
7-13
THE WAIT-STATE
a
Like the 808QA. the Z$O,JlIIQws Wait state to occur betyieen clock periods T2 and 1"3 of a machine cycle. The
Wait state frees external lo~!c or memory from having to,operate at CPU speed.
The Z80 CPU samples th~ WAIT input on the falling edge of $ during T2. Providing WAIT is Iowan the falling edge of
$ during~ait clock periods will be inserted. The number of Wait clock periods inserted depends strictly on how
long the WAlT inP4t is held low. As soon as the Z80 detects WAIT high on the falling edge of $. it will ir"!itiate T3 on
the next rising edge of $.
<
'
•
••
-
Note thft~ the Single'~ap "V~IT signal replaces the READY and WAIT aOaOA signals. As this would imply. no signal is output telling ext~rnallogic the Z80has entered the Wait state, In the event that external logic needs to know
whet"'~r or n~t a Y'aJt'state Ilas been entered, these a~e the rules:'
- .
1)
The Z80 will samp'le ,yv~IT 01') the f~lIin~' edge of $ in T2.
2)
ff WAllis low. then ,~he ~8R will continue to sample the yvAIT inP!Jt for all subsequent ,Wait state clock periods.
3)
The Z80 will not sample the WAIT input during any clock period other than 'T2 or a Wait state.
Figure 7-8 illustrates
.
. ,
I
.
I ,
Z80vyai~ st~'te
,
•
'
~ •• ,
timing.
AO - A15
~REa
RD
~AIT
Figure 7-8. Z80W~it State Ti,rnin9,
INPUT OR OUTPUT GENERATIQN
Timing
for zao input and .output gener~tion
is given in Figures 7·9 and 7·10.
.. '
. '
The important point to note is that Zilog has acknowledged the infrequency with which typical I/O logic can operate at
CPU speed. One Wait clock period is therefore automatically Inserted between T2imd T3 for all inm~t or output
machine cycles. Otherwise timing differs from men:qry read and write operations only in that 10RO is' output low
rather than MREO.
.
:
'
~
.,
Note that there is absolutely nothing to prevent you from'selecting I/O devices within the memory space. This is something we did con'sistently in the 8080A chapter when describing 8080A support devices. But if you adopt this design
policy. remelTlber that your I/O logic must execute at CPU speed. unless you rns~rt Waitstates.
7-14
Forced
Wait
State
~
T1
c
w
~
a:
o
Q.
a:
T2
Tw'
T1
T3
C/)
C/)
oCt
all
w
Z
AO - A15
a:
o
In
C/)
o
~
oCt
MREQ
RD
C
oCt
@
RFSH
Figure 7-14. Z80 Response to a Nonmaskable Interrupt Request
THE HALT INSTRUCTION
When a Halt instruction is executed by the Z80 CPU. a sequence of NOP instructions is executed until an interrupt request is received. Both maskable and nonmaskable interrupt request lines are sampled on the rising edge of during
T4 of every NOP instruction's machine cycle.
The Halt state will terminate when any interrupt request is detected. at which time the appropriate interrupt
acknowledge sequence will be initiated. as illustrated in Figures 7-13 and 7-14.
Note that the Z80 executes the sequence of NOP instructions during a Halt so that it can continue to generate dynamic
memory refresh signals.
Halt instruction timing is illustrated in Figure 7-15.
--M1
~~~~--------M1
---------~~~--- M1
HALT
iNT or
NMi
HALT INSTRUCTION
IS RECEIVED
DURING THIS
MEMORY CYCLE
Figure 7-15. Z80 Halt Instruction Timing
7-19
The following abbreviations are used in this chapter:
A.F.B.C.D.E.H.L
The 8-bit registers. A is the Accumulator and F is the Program' Status Word.
AF'.BC'.DE'.HL·
The alternative register pairs
addr
A 16-bit memory address
x(b)
Bit b of 8-bit register or memory location x
cond
Condition for program branching. Conditions are:
NZ - Non-Zero (Z=O)
Z
- Zero (Z=1)
NC - Non-carry (C=O)
C
- Carry (C=1)
PO - Parity Odd (P=O)
PE
- Parity Even (P=1)
- Sign Positive (S=O)
P
M
- Sign Negative (S=1)
data
An 8-bit binary data unit
data16
A 16-bit binary data unit
disp
An 8-bit signed binary address displacement
xx(HI)
The high-order 8 bits of a 16-bit quantity xx
IV
Interrupt vector register (8 bits)
IX.IY
The Index registers (16 bits each)
xy
Either one of the Index registers (IX or IY)
of .
LSB
Least Significant Bit (Bit
label
A 16-bit instruction memory address
xx(LO)
The low-order 8 bits of a 16-bit quantity xx
MSB
Most Significant Bit (Bit 7)
PC
Program Counter
port
An 8-bit I/O port address
pr
Any of the following register pairs:
BC
DE
HL
AF
R
The Refresh register (8 bits)
reg
Any of the following registers:
A
B
C
D
E
H
L
rp
Any of the following register pairs:
BC
DE
HL
SP
SP
Stack Pointer (16 bits)
7-20
Statuses
ow
~
a:
oD..
The following symbols are used in the status columns:
X
flag is affected by operation
(blank)
flag is not affected by operation
1
flag is set by operation
o
flag is reset by operation
?
flag is unknown after operation
P
flag shows parity status
flag shows overflow status
I
flag shows interrupt enabled/disabled status
a:
o
(J
~
ui
w
~
C3
o
CJ)
o
CJ)
ct
The Z80 has the following status flags:
C
Carry status
Z
Zero status
S
Sign status
P/O
Parity/Overflow status
Auxiliary Carry status
AC
Subtract status
N
[ ]
Contents of location enclosed within brackets. If a register designation is enclosed within the
brackets, then the designated register's contents are specified. If an I/O port number is enclosed
within the brackets, then the I/O port contents are specified. If a memory address is enclosed within
the brackets, then the contents of the addressed memory location are specified.
[[]]
Implied memory addressing: the contents of the memory location designated by the contents of a
register.
o
A
Logical AND
@
v
o1S
w
Z
a:
o
a:I
CJ)
o
~
ct
ct
Logical OR
Logical Exclusive-OR
Data is transferred in the direction of the arrow·
Data is exchanged between the two locations designated on· either side of the arrow.
The fixed part of an assembly language instruction is shown in UPPER CASE.
The variable part (immediate data, I/O device number, register name, label or address) is shown in lower case.
7-21
-Address Bus: AO-A7: [C)
A8-AI5: [B)
Table 7-2. A Summary of the Z80 Instruction Set
STATUS
TYPE
MNEMONIC
OPERAND IS)
OPERA TION PERFORMED
BYTES
C
g
~
Z
S
P/O
AC
N
IN
A.port
2
IN
reg.IC)
2
X
X
P
X
0
INIR
2
1
?
?
?
1
INDR
2
1
?
?
?
1
INI
2
X
7
7
7
1
INO
2
X
7
7
?
1
1
7
7
7
1
_.
OUT
portA
OUT
IC).reg
,-
2
2
2
OTiR
'.
[A]-[port]
Input to Accumulator from directly addressed I/O port.
Address Bus: AO-A7: port
A8-AI5: [A]
[reg]-[(C))
Input to register from I/O port addressed by the contents of C.If second byte is 70 16 only the flags. will be affected.
Repeat until [B]~:
[[HLll-[[C))
[B]-[B]-1
[HLl-[HLl+ 1
Trensfer a block of data fr~m I/O port addressed by contents of C to memory location addressed by contents of HL. going from low addresses to high. Contents of B serve as a count of
bytes remaining to be transferred.Repeat until [B]-o:
[[HL))-[[Cll
[B]-[B]-1
[HL]-[HL] - 1
Transfer a block of data from I/O port addressed by contents of C to memory location addressed by contents of HL. going from high addresses to low. Contents of B serve as a count of
bytes remaining to be transferred.·
[[HL))-[[C))
[B]-[B]-1
[HL]-[HL] + 1
Transfer II byte of datil from I/O port IIddrllsslld by contents of C to mllmory loclltion addressed
by contents of HL. Decrement bytll count and increment destination IIddress.·
[[HLll-[[C])
[B]-[B]-1
[HL]-[HLl-l
Transfer a byte of data from I/O port addressed by contents of C to memory location addressed
by contents of HL Decrement both byte count lind destination address.·
[port]-[A]
Output from Accumulator to directly addressed I/O port.
Address Bus: AO-A7: port
A8-AI5: [A]
[[C))-[reg]
Output from register to I/O port addressed by the contents of C.Repeat until [B] =();
[(C))-[[HL))
[B]-[B]-1
[H-Ll-[HL]+ 1
Transfer a block of data from memory location addressed by contents of HL to I/O port.addressed by contents of C, going from low memory to high. Contents of B serve as a count of
bytes remaining to be transferred.-
© ADAM OSBORNE &
·Address 8us: AO-A7: [C)
AB-A15: [8]
ASSOCIATES. INCORPORATED
Table 7-2. A Summary of the Z80 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERANDISI
OPERATION PERFORMED
BYTES
C
Z
S
PIO
AC
N
OTDR
2
1
7
7
7
1
Repeat until [8]=0:
[[C))-[[HL))
[8]-[8]-1
[HLl-[HLl- 1
Transfer a block of data from memory location addressed by contents of HL to I/O port addressed by contents of C. going from high memory to low. Contents of 8 serve as a count of
bytes remaining to be transferred.·
0UJ1
2
X
7
7
7
1
OUTO
2
X
7
7
7
1
[[C))-[[HL))
[8]-[8]-1
[HL]-[HLl + 1
Transfer a byte of data from memory location addressed by contents of HL to I/O port addressed by contents of C. Decrement byte count and increment so.uree address.·
[[C))-[[HL))
[8]-[8]-1
[HLl-[HL] - 1
Transfer a byte of data from memory location addressed by contents of HL to I/O port addressed by contents of C. Decrement bOth byte count and source address.·
'ii
II
:>
~c
0
g
g
LD
A.laddrl
3
LD
HL.laddrl
3
LD
rp.laddrl
xy.laddrl
4
0
LD
laddrl.A
3
a:
w
IL
w
a:
LD
laddrl.HL
3
>
a:
LD
laddrl.rp
laddrl.xy
4
::E
w
::E
LD
A.IBCI
A.IOEI
1
LD
reg.IHLI
.1
LD
(BCI.A
(DEI.A
(HLI.reg
1
1
. LD
reg.(xy + dis pI
3.
LD
(xy + displ.reg
3
w
zw
0
>
a:
""
::E
ii:
a.
LD
[A]-[addr]
Load Accumulator from directly addressed memory location.
[H]-[addr+ 11. [Ll-[addr]
Load HL·from directly addressed memory.
[rp(HIl]-[addr+ 11. [rp(LO))-[addr] or
[xy(HIl]-[addr+ 11. [xylLO))-[addr]
Load register pair or Index register from. directly addressed memory.
[addr]-[A]
Store Accumulator contents in directly addressed memory location.
[addr+ 1J-[Hl [addr]-[Ll
Store contents of HL to directly addressed memory location.
[addr+ 1J-[rp(HIlJ. [addrJ-[rp(LO)) or
[addr+ 1J-[xy(HIlJ. [addr]-[xylLO))
;'Store contents of register pair or Index register to directly addressed memory.
[A]-[[8C)) or [A]-[[DE))
Load Accumulator from memory location addressed by the contents of the specified register pair.
[reg] ..... [[ HL))
Load register from memory location addressed by COntents of HL.
[[BC))-[A] or [[DEJ]-[A]
Store Accumulator to memory location addreaaed by the contents of the specified register pair.
[[HL))-[reg]
Store register contents to memory location eddreaaed by the contents of HL
[reg]-[[xy] +disp]
Load regiSter from memory location using base relative addreaaing.
[[xy] + disp]-[ reg]
Store register to memory location addressed relative to contents of Index register.
Table 7-2. A Summary of theZ80 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(Sl
OPERATION PERFORMED
BYTES
C
LDIR
:r
u
a:
04:
w
Z
S
2
PIO
AC
N
0
0
0
LDDR
2
0
0
.0
LDI
2
X
0
0
!II
c
!II
Z
.04:
~
[DE]-[DE]+ 1
[HL}-[HLl + 1
[BC]-[BC]-l
Transfer a block of data from the memory location addressed by the contents of HL to the
memory location addressed by the contents of DE. going from low addresses to high. Contents
of BC serve as a count of bytes to be transferred.
Repeat until [BC)=O:
[[DEll-[[HLl],
[OE]-[DE]- 1
'[HLl-[HLl- 1
[BC]-[BC]- 1
Transfer' a block of data from the memory .location addressed by the contents of HL to the
~;-'-''ITlemory location addressed by the contents of DE. going from high addresses to low. Contents
of BC serve as a count of bytes to be transferred.
[[ DEll- [[ HLll
[OEl-[DE]+l
[HLl-[HLl+ 1
-[BC]-[BC]- 1
-Transfer one byt~ of data from the memory-location addressed by the-contents of HL to the
memory location addressed by the contents 'of DE. Increment 'source and destination addresses
Z
04:
a:
w
IL.
...a:
' Repeat until [BC]-C>:
[[DEll"';"[[H'Lll
LOD
2
CPIR
2
X
CPOR
2
X
X
0
0
X
X
X
1
X
X
X
1
u
0
...J
III
--and decrement byte count.
[[ DEll-[[ HLl]
[OE]-[DE]- 1
[HLl-[HL]- 1
'[BC]-[BC]- 1
Transfer one byte of data from'the memory location addressed by the contents of HL to the
memory location addressed by the contents of DE. Decrement source and destination addresses
and byte count,
Repeat until [A]=[[HLll or [BC]=O:
[A]- [[HLl] (only flags are affectedl
[HLl-[HLl+ 1
[BC]-[BC]- 1
Compare c<.>ntents- of Accumulator with those of memory block addressed by contents of HL.
going from low addresses to high. Stop when a match is found or when the byte count becomes
zero.
Repeat until [Al=[[HL]] or [BC]=O:
[A]- [[ HLll (only flags are affectedl
[HL]-[HL]- 1
"[BC]-[BC]- 1
Compare contents of Accumulator with those of memory block addressed by contents of HL.
going from high addresses to low. Stop when a match is found or when the byte count becomes
zero.
.© ADAM OSBORNE &
Table 7-2. A Summary of the
ASSOCIATES. INCORPORATED
zao Instruction Set (Continued)
STATUS
TYPE.
o
z-
. MNEMONIC
OPERAND(S)
BYTES ~---r--~--~~--~--~--~
PIO
AC
N
z
S
C
x
CPI
x
x
x
I A] - [[ HL]].(only flags are affected)
[HLl-[HL] + 1
[BC]-[BC]- 1
c(j
a:
:I
w.s
I&. ..
Compare contents of Accumulator with those of memory location addressed by contents of .HL.
o c
z8
c( - .
a:%
~u
CPO
x
x
x
x
x
X
0
X
Increment address and decrement byte count.
[Af- [[HL)) (only flags are affected)
[HLl-[HL] - 1
[BC]-[BC] - 1
Compare contents .of Accumulator with thOse of memory locatiOO addressed by contents of HL
Decrement address and byte count.
~a:
uC(
OW
..... 0
III
ADD
w
ADC
U
Z
w
a:
w
SUB
I&.
w
a:
>
a:
o
~
SBC
AND
w
~
>
a:
OR
c(
o
Z
XOR
o
U
w
o
OPERATION PERFORMED
CP
. (HL)
(xy+disp)
(HL)
1
o
o
1
(xy +disp)
(HLl
(XV + disp)
3
(HP
(xy+disp)
(HLl
(xy+ disp)
(HL)
1
(xy+disp)
(HLl
(xy+ disp)
(HLl
(xy+disp)
x
3
x
X
X
O.
X
x
X
X
0
X
o
X
X
p.
1
o
o
x·
X
P
1
o
o
X
X
P
1
o
x
X
X
0
X
1
X
X
o
X
3
1
3
X
X
o
X.
1
3
3
1
3
1
3
1
3
1
3
INC
(HLl
(xy+disp)
DEC
(HLl
(xy+disp)
o
[A]-[A]+[[HL)) or [A]-[A]+ [[xy]+disp]
Add to Accumulator using implied addressing or base relative addressing.
[A]-:-[A]+ [[HL))+Cor-[Ah-[A]+ [[xy]+disp]+C
Add with Carry using implied addressing or base relative addressing.
[A]-[A]- [[HL)) or [A]-[A] - [[xy]+disp]
Subtract from Accumulator using implied addressing or base relative addressing.
[A]-[A] - [[HLl- C or [A]-[A]- [[XV] +disp] - C
Subtract with Carry using implied addressing or base relative addressing.
CA]-[A] A [[HL)) or [A]-[A] A [[xy]+disp]
AND with Accumulator using implied addressing or base relative addressing
[A]-[A]V [[HLl] or [A]-[A]V [[xy]+disp]
OR with Accumulator using implied addressing or base relative addressing.
[A]-[ A].y. [[ HL)) or [A]-[ A]¥- [[ xy] + disp]
Exclusive-OR with Accumulator using implied addressing or base relative addressing.
[A] - [[HL)) or [A] - [[XV] + disp]
Compare with Accumulator using implied eddressing or base relative addressing. Only the flags
are affected.
[[HL))-[[HL)) + 1 or [[XV] + disp]-[[xy] +disp] + 1
Increment using implied addressing or base relative addressing.
[[HL))-[[HL))-l or '[[xy]+disp]-[[xy]+disp-]-l
Decrement using implied addressing or base relative addressing.
Table 7-2. A Summary of the
zao Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
RLC
RL
OPERAND(S)
OPERATION PERFORMED::
BYTES
C
Z
S
P/O
AC
N
X
x
P
0
0
(HL)
(xy+disp)
2
4
x
(HLl
(xy+disp)
2
4
X
~7
of:;]
CI
[[HL)) or [[xy]+disp]
Rotate contents of. memory location (implied or base relative addressing) left with branch Carry.
X
X
P
0
0
~7
Ot;]
CI
[[HL)) or [[XV] + disp]
.. O~
Rotata contants of memory location left through Carry.
III
S
RRC
0
(HL)
(xy+ disp)
2
4
X
X
X
P
0
0
[[HL)) or [(xyl+disp]
II:
Rotate contents of memory location right with brench Carry.
C
Z
or(
t:
RR
%
en
. (HL)
(xy+disp)
2
4
X
X
X
P
0
0
>-
III
:::E
!: o~
~7
. [[ HL)) or [( XV] + disp]
..
Rotate contents o(memory Icx:ation right through Carry.
II:
0
:::E
l;47
SLA
(HL)
(xy+ disp)
2
X
X
X
P
0
0
[§}-1----17
4
o t.-o
[[ HL)) or [[ xy] + disp]
Shift contents of memory location left and clear LSB (Arithmetic Shiftl.
SM
(HL) ,
(xy+disp)
2
4
X
X
X
P
0
0
~
"·O~
[[HL)) or ([xy] +disp]
..
Shift contents of memory location right and preserve MSB (Arithmetic Shift).
SRL
(HLl
(xy+ disp)
2
4,
X
X
X
.P,
0
0
O~7
O~
[[ HL)) or ([ xy] + disp]
Shift conte~ts of memory location right and clear MSB (Logical Shift).
III
LO
reg, data
2
Ior(
0
LO
III
:::E
~
Lb
rp,data16
XY,data16
(HL),data
(xy + disp),data:
3
4
2
4
[ reg]-- data
Load immediate into'Tegister,
. [rp]--dat~16 'or [xy]--data16
Load 16 bits of immediate data into register pair or Index register.
[[HL))--data or [[XV] +.disp]--data
, Load immediate into memory location using implied or base relative addressing.
© ADAM OSBORNE &
Table 7-2. A Summary of the
ASSOCIATES. INCORPORATED
zao Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
OPERATION PERFORMED
BYTES
C
Z
S
P/O
Ac
N
[PC]-Iabel
Jump to instruction at address represented 'by label.
[PC]-[ PC] + 2 + disp
,. Jump relative to present contents of Progrem Counter•
[PC]-[HL] or [PC]-[xy]
Jump to address contained in HL or Index register.
JP
label
3
JR·
disp .
2
JP
(HL)
Ixy)
1
2
CALL
label
3
CALL
RET
cond.label
3
RET
cond
1
ADD
data
2
X
X
X
0
X
0
ADC
data
2
X
X
X
0
X
0
SUB
data
2
X
X
X
0
X
1
0
SBC
data
2
X
X
X
0
X
1
'Q"
AND
data
2·
0
X
X
P
1
0
::!
~
OR
data
2
0
X
X
P
1
0
XOR
data
2
0
X
X
P
1
0
CP
data
2
X
X
X
0
X
1
D.
::!
..,:::I
,.
,.
. [(SP]-l]-[PC(HII]
[[SP]-2]-[ PC(lO)]
[SP]-[SP]-2
[PC]-Iabel
Jump to subroutine starting at address represented by labei.
Jump to subroutine if condition is satisfied; otherwise. continue in sequence.
[PC(LOI1-[[SP))
[PC(Hil1-[[sp]+ 1]
[SP]-[SP] + 2
Retum from subroutine.
Return from subroutine if condition is satisfied; otherwise. continue in sequence.
. ...J
...J
'" ...a:
i= a:
Z
u
w
:::I
Z
·W
:::I
0
0
III
'"
a: Z
:::I
II)
1
-....I
I
N
-....I
...
w
'a:"
w
Do
...w
1&1
[A]-[A] + data
Add immediate to Accumulator.
[A]-[A]+data+C
Add immediate with Carry.
[A]-[A]-data
Subtrect immediate from Accumulator.
[A]-[A] - data -.C
Subtract immediate with Cany.
[A]-[A] A data
AND immediate with Accumulaior.
[A]-[A] V data
OR immediate with Accumulator.
[A]-[A]¥data
Exclusive-OR immediate with Accumulator.
[A] - data
Compare immediate data with Accumulator contents; only the flags are affected.
Table 7-2. A Summary of the Z80 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
OPERATION PERFORMED
BYTES
C
JP
corid,label
3
0
JR
C,disp
2
eZ
JR
NC,disp
2
Z
JR
Z,disp
2
JR
NZ,disp
2
DJNZ
disp
2
Z
Z
s
PIO
AC
N
If cond, then [pe]-Iabel
Jump to instruction at address represented by label if the condition is true.
If C=l, then [PC]-[PC] +2+disp
Jump relative to contents of Program Counter if Carry flag is set.
IfC=(),then [PC]-[PC]+2+disp
Jump relative to contents of Program Counter if Carry flag is reset.
If Z=l, then [PC]-[PC]+2+disp
Jump relative to contents of Program Counter if Zero flag is set.
If Z=(), then [pc]-[ PC] + 2 + disp
i=
0
U
0
IL
~
:)
Jump relative to contents of Program Counter if Zero flag is reset.
[B]-[B]-l
If [B] J'oO, then [pc]-[PC]+2+disp
-,
Decrement contents of B and Jump relative to contents of Program Counter if result is not O.
~
N
OJ
LD
dst,src
1
LD
AN
2
X
X
I
0
0
w
LD
A,R
2
X
X
·1
0
0
0
~
LD
IV,A
2
I/)
LD
R,A
2
c::
. LD
SP,HL
1
LD
SP,xy
2
EX
DE,HL
1
EX
AF,AF
1
>
c::
w
I-
aw
ci:
w
I-
I/)
aw
c::
EXX
1
[dst]-[src]
Move contents of source register to destination register. Register designations src and dst may
each be A, B, C, D, E, H or L.
[A]-[IV]
Move contents of Interrupt Vector register to Accumulator.
[A]-[R]
Move contents of Refresh register to Accumulator.
[IV]-[A]
Load Interrupt Vector register from Accumulator.
[R]-[A]
Load Refresh register from Accumu!ator,
[SP]-[HLl
Move contents of HL to Stack Pointer.
[SP]-[xy]
Move contents of Index register to Stack Pointer.
[DE]-[HLl
Exchange contents of DE and HL,
[AF]-[AF]
Exchange program status and alternate program status.
eBeI) (,Bel)
[DE] [DE']
[HLl
[HL']
Exchange register pairs and alternate register pairs.
©
ADAM OSBORNE & ASSOCIATES. INCORPORATED
Table 7-2. A Summary of the Z80 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
.:(
a:
0
a:
ri:
au
l-
(/)
6au
a:
~
a:
N
X
X
X
0
X
0
X
X
X
0
X
0
X
~
X
0
X
X
X
X
0
X
0
X
X
P
0
X
X
P
0
X
X
P
,
,
,
X
X
X
0
X
,
7
0
, SUB
reg
SBC
reg
AND
reg
OR
reg
XOR
reg
CP
reg
ADD
HL,rp
ADC
HL,rp
2
X
X
X
0
7
0
SBC
HL,rp
2
X
X
X
0
7
,
ADD
IX.pp
2
X
7
0
ADD
lV,rr
2
X
7
0
1
X
CPL
,
NEG
2
X
INC
reg
a:
~
(/)
INC
6au
DEC
rp
xy
reg
au
AC
reg
OM
w
PIO
ADC
·6
au
a:
S
,
,
,
,
,
,
,
,
,
au
I-
(/)
Z
reg
au
IL
C
ADD
au
I-
'OPERATION PERFORMED
BYTES
IL
0
a:
DEC
rp
xy
,
,
2
,
2
X'
X
X
0
0
0
,
Increment register contents.
[rp]-[rp] +' or [Xy]-[xy] +'
Increment contents of register pair or'lndex register.
[reg]-[reg] - ,
, ,
,
0
X
X
X
0
X
0
X
AND contents of register with contents of Accumulator.
[A]-[A] V [reg]
OR contents of register with contents of Accumulator.
[A]-[A].y. [reg]
Exclusive-OR contents of register with contents of Accumulator.
[A] - [reg]
Compare contents of register with contents of Accumulator. Only the flags are affected.
[HL]-[HL]+ [rp]
'6-bit add register pair contents ,to contents of HL
[HL]-[HL]+ [rp]+C
'6-bit add with carry register pair contents to contents of HL
[HL]-[HL] - [rp] - C
'6-bit subtract with carry register pair contents from contents of HL
[IX]-:[IX]+ [pp]
'6-bit add register pair contents to contents of Index register IX (pp=BC, DE, IX, SP)
[IV]-[IV]+[rr]
'6-bitadd register pair contents to contents of Index register IV (rr-BC, DE, IV, SPI.
Decimal adjust Accumulator, assuming that Accumulator contents are the sum or difference of
BCD operands.
[A]-[A]
Complement Accumulator (ones complement).
[A]-["A] + 1
Negate Accumulator Itwos complement!.
[reg]-[regl+ ,
X
X
X
0
p
X
X
,
,
[A]-[A1+ [reg]
Add contents of register to Accumulator.
[Al-[A1+ [reg] + C
Add contents of register and carry to Accumulator.
[A]-[Aj - [reg]
Subtract contents of register from Accumulator.
[A]-[A] - [reg] ~ C
Subtract contents of register and carry fro~ 'AccumuJ8tor.
[A]-[A] A [reg]
Decrement register contents.
[rp]~[rp] - , or [xy]-[xy] - ,
Decrement contents of register pair or Index register.
Table 7-2. A Summary of the
zao Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
OPERATION PERFORMED
BYTES
C
1
RLCA
Z
S
PIO
X
Ac
N
0
0
@}-Lj 7
.
0
f4J
0
i+l
[A]
Rotate Accumulator left with branch Carry.
1
RLA
0
X
0
c:m:;=t 74
[A]
Rotate Accumulator left through Carry.
1
RRCA
0
X
0
... o~
L;:j 7
[A]
Rotate Accumulator right with branch Carry.
w
1
RRA
0
X
0
I-
0
cr
~
o
0
Z
«
RLC
reg
2
X
X
X
P
0
0
Iu..
l:
~7
(/)
w
I-
.---.:tIP
.
o~
...
o j:;J~.....
[reg]
Rotate contents of registe~ left with branch Carry.
cr
(/)
o
[A]
Rotate Accumulator right through Carry.
«
Iw
..
L;:j7
RL
reg
2
X
X
X
P
0
0
(;
w
LEJ+=j7
[reg]
Rotate contents of register left through Carry.
cr
RRC
reg
2
X
X
X
P
0
0
4.J7
~
O~
[reg]
Rotate contents of register right with branch Carry.
RR
reg
2
X
X
X
p
0
0
.. O~
L;:j7
[reg]
Rotate contents of register right through Carry.
SLA
reg
2
X
X
X
P
0
0
~7
..
o t----O
[reg]
... O~
Shift contents of register left and clear LSB (Arithmetic Shift).
SRA
reg
2
X
X
X
P
0
0
~
[reg]
Shift contents of register right and preserve MSB (Arithmetic Shift).
© ADAM OSBORNE &
Table 7-2. A Summary of the
ASSOCIATES. INCORPORATED
zao Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
SRL
OPERATION PERFORMED
BYTES
2
C
Z
S
PIO
AC
N
X
X
X
P
0
0
I-
<
I0
II:
0_
2"C
2
RLD
X
X
P
0
0
< g:
oI
.-@]
17
41 3
:
..
0
I
..
c
:E
0
Cl)g
II:
w
I-
CI)
(;
RRD
W
17
i
...413
~:
'
oI
([HLl]
[A]
Rotate one BCD digit left between the Accumulator and memory location (implied addressing).
Contents of the upper half of the Accumulator are not affected.
I- .!:
II..
.
o-.J 7
[reg]
Shift contents of register right and c~ear MSB (Logical Shih).
w
reg
2
X
X
P
0
0
II:
17
~I
413
:4 01
17
I
41 3
-:
01
([HL))
[A]
Rotate one BCD digit right b8tween the Accumulator and memory location (implied addre~ing).
Contents of the upper half of the Accumulator are not affected.
BIT
b,reg
2
X
?
?
1
0
BIT
b,(HL)
b,(xy + disp)
2
4
X
?
?
1
0
SET
b,reg
2
<
SET
b,(Hl)
b,(xy + disp)
2
4
iii
RES
b,reg
2
b,(HL)
b,(xy + disp)
2
4
PUSH
pr
xy
1
2
[[SP]-ll-[ priHl)]
[[SP)-2]-[priLO))
[SP]-[SP]-2
POP
pr
xy
1
2
Put contents of register pair or Index register on top of Stack and decrement Stack Pointer.
[priLO))-[[SP))
[priHIl]-[[SP] + 1]
[SP]-[SP1+2
EX
(SP).HL
1
2
2
0
~
<
..J
~
a..
2:
~
'1-
RES
~
u
<
ICI)
(SPl.xy
Z-oeg(b)
Zero flag contains complement of the selected register bit.
Z- ([HL))(b) or Z- ([)(y] +disp](b)
Zero flag contains complement of selected bit of the memory location (implied addressing or
base relative addressing).
reg(b)-l
Set indicated register bit.
[[HLl](b)-l or Hxy]+disp](b)-l
Set indicated bit of memory location (implied addressing or base relative addressing).
reg(b)-O
Reset indicated register bit.
[[HL))(b)-O or [[xy] +disp](b)-O
Reset indicated bit in memory location (i~plied addressing or base relative addressing).
Put contents of top of Stack in register pair or Index register and increment Stack Pointer.
[H]-[[SP] + 11
[Ll-[[SP))
Exchange contents of HL or Index register1md. top of Stack.
Table 7-2. A Summary of the Z80 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERANDISI
OPERATION PERFORMED
BYTES
C
01
EI
RST
n
Z
S
P/O
AC
N
Disable interrupts.
Enable interrupts.
[[ SP]-1 ] - [ PC(HIl]
[[SP]-2]-[PC(LO))
[SP]-[SP]-2
1
1
1
lll.
:J
[PC]-(8~n)16
Restart at designated location.
Return from interrupt.
Return from nonmaskable interrupt.
Set interrupt mode O. 1. or 2.
II:
II:
W
I-
~
RETI
RETN
1M
0
.-
2
2
2
1
2
CI)
SCF
1
1
0
0
C';""1
CCF
1
X
?
0
Set Carry flag.
C-C
Complement Carry flag.
NOP
HALT
1
1
:J
l-
e(
1-CI)
No operation - volatile memones are refreshed.
CPU halts. executes NOPs to refresh volatile memories.
Table 7-3. A Summary of Instruction Object Codes and Execution Cycles with 8080A Mnemonics
for Identical Instructions
INSTRUCTION
cw
~
a:
o
D.
ADC
ADC
ADC
data
(HL)
ADC
ADC
HL,rp
(lX+disp)
(lY+ disp)
~
ADC
ADD
ADD
reg
data
(HL)
ui
ADD
~
ADD
ADD
ADD
HL,rp
(lX+disp)
a:
o
(J
w
g
en
en
ct
cZI
w
Z
a:
o
III
en
o
~
IX,pp
(lY+disp)
ADD
IY,rr
ADD
AND
reg
data
(HL)
AND
AND
AND
AND
ct.
@
BIT
CALL
CALL
CALL
1
2
FD 8E vy
l000lxxx
3
2
19
15
FD 86 vy
3
2
A6
7
ADC
ADI
ADD
reg
4
7
7
7
data
DAD
M
rp
15
4
7
ADD
ANI
reg
data
4
7
7
ANA
M
7
ANA
reg
4
label
label
label
17
·,0.··/·. ·.•. .• ·• . • \
I
19
1
2
1
3
3
19
19
1
2
4
;2
b,(lX+ displ
01bbb110
DO CB vy
01bbb110
4
20
b,(lY+displ
FD CB vy
4
20
b,reg
01bbb110
CB
2
8
01bbbxxx
CD ppqq
DC ppqq
3
3
17
10/17
CALL
CC
04 ppqq
C4 ppqq
3
3
3
10/17
10/17
CM
CNC
3
3
10/17
10/17
10/17
CNZ
CP
CPE
label
liii. /.(.i .• l/t7·.·····•.. / .••i • •
3
3
1
2
1
10/17
10/17
4
CPO
CZ
label
label
..i>
CMC
CPI
data
CMP
M
7
7
CMP
reg
19
label
C,label
M,label
NC,label
NZ,label
P,label
Fe ppqq
E4 ppqq
CC ppqq
CCF
CP
CP
data
(HL)
CP
CP
(lX+disp)
CP
CPO
CPDR
CPI
reg
(lY+ disp)
3F
FEvy
BE
DO BE vy
FD BE vy
10111xxx
7
7
19
3
19
4
3
label
label
label
ED A9
ED B9
ED Al
2
16
21/16·
16
ED Bl
2F
2
21/16·
~
4
CMA
27
1
4
35
DD2B
DO 35vy
1
2
.3
DAA
OCR
M
FD 2B
2
lQ
rp
FD 35 vy
OOxx1011
3
1
23
6
reg
OOxxxl01
1
DCX
OCR
reg
disp
F3
10 vy
1
2
1
4
4
8/13
4
1
1
4.
4
1
19
23
CPL
OM
(HL)
IX
(lX+disp)
IY
(lY+ disp)
EI
FB
AF,AF'
08
OE.HL
(SP),HL
(SP),IX
EB
E3
DO E3
11
10
........
1'··.·.\i
4
1
2
2
CPIR
EX
EX
EX
EX
data
M
CB
PO,label
Z,label
DI
OJNZ
j
DO 86 vy
DO OOxxl00l
PE,label
DEC
19
4
1
7
11
CALL
CALL
CALL
DEC
DEC
3
3
1
FD OOxxl00l
l0000xxx
E6 vy
ACI
ADC
15
19
2
1
F4 ppqq
EC ppqq
DEC
DEC
DEC
DEC'
7
7
8080A
CLOCK
PERIODS
8080A
MNEMONIC
CLOCK
PERIODS
C6 vy
86
OOxxl00l
FD' A6 vy
10100xxx
BIT
CALL
2
8E
ED 01xxl0l0
DO 8E vy
(lY+disp)
BIT
CALL
CALL
CE vy
DO A6 vy
reg
b,(HL)
BIT
BYTES
(IX + disp)
ct
C
OBJECT CODE
,;
.
4
4
1/./"'"",
2. i'··
1••••. /.i<10/.( .•.••• · .....•
~3
2
7-33
rp
5
01
4
EI
4
XCHG
XTHL
rii.··
4
li.·•.
.....
_ ........_.....
External Devices
Accumulator
Registeris)
, ..............
"i
t
i
)
i
..•.......
i
'.'
l
i.···.
Instruction Register ~
,
~
~
Control Unit
Data Counteris)
•
i>
i.
,~
Stack Pointer
....
i
r(
11
i.
)i
Bus Interface
Logic
.....
•......
~
Direct Memory
Access Control
Logic
Program Counter
,
I
t
System Bus
'~
I
Programmable
i
f
ROM Addressing
and
Interface Logic
I/O Communication
Serial to Parallel
Interface Logic
I
",,'_ _
Ti_m_e_rs_--,r
I'1__
Read Only
...
I
. . /y . •. • . . }. • • .• .• .
M_e_m_o_ry_--,I'
~
J
...
t
r
RAM Addressing
and
Interface Logic
I
...
Read/W~ite
Memory
Figure 7-16, Logic Functions of the Z80 PIO
zao
PIO PINS AND SIGNALS
Z80PI0 pins and signals are illustrated in Figure 7-17. Signals are very straightforward: therefore their functions
will be summarized before we discuss device characteristics and operation.
let us first consider the PIO CPU interface.
All da'ta transfers
between the PIO and the CPU occur via the Data Bus, ~,"hich 'connects to pins DO' - 07.
For the PIO to be selected, a low input must be present at CEo There are two additional address lines. a/A SEl
selects Port A if low and Port B if high. For the selected I/O port, C/O SEl selects a data buffer when low and a
control buffer when high. Device select logic is summarized in Table 7-5.
7-46
Table 7-5.
zao PIO Select Logic
SIGNAL
CE
0
0
0
0
1
Q
w
~
a:
o0..
a:
o
CJ
!:
en
w
~
g
en
en
SELECTED LOCATION
B/A SEL C/D SEL
0
0
1
1
0
1
0
1
X
X
Port A data buffer
Port A control buffer
Port B data buffer
Port B control buffer
Device not selected
zao PIO device control logic is not straightforward. Of the control signals output by the zao CPU. three are input to the
PIO; M1. IORO. and RD. WR is not input to the PIO. Table 7-5 illustrates the way in which Z80 PIO interprets M1,
lORQ and RO. Observe that RD is being treated as a signal with two active states: low RD specifies a read operation.
whereas high AD specifies a write operation. This does not conform to the CPU. which treats RD and WR as signals
with a low active state only.
c(
Let us now look at the PIO external logic interface.
o!I
w
Z
AO - A 7 represent the eight bidirectional I/O Port A lines; I/O Port A is supported by two control signals, A ROY
and A STB.
.
a:
·0
CD
en
o
~
c(
Similarly, I/O Port B is implemented via the eight bidirectional lines BO - B7 and the two associated control lines
B ROY and B STB.
The I/O Port A and B control lines provide handshaking logic which we will describe shortly.
Q
c(
@
Now consider interrupt control signals.
lEI and lEO are standard daisy chain interrupt priority signals. When more than one PIO is present in a system. the
highest priority PIO will have lEI tied to +5V and will connect its lEO to the lEI for the next highest priority PIO in the
daisy chain:
No connection
+5V
lEI
lEO
. PIO
lEI
lEI
lEO
PIO
2
Highest
(first)
lEO
PlO
3
Second
Third
priority
priority
lEI
lEO
PIO
n
Lowest
priority
priority
If you are unsure of daisy chain priority networks. refer to Volume 1 for clarification.
INT is a standard interrupt request signal which is output by the zao PIO and must be connected as an input to the
zao CPU interrUpt request. Observe that there is no interrupt acknowledge line. since M1 and IORO simultaneously low
constitute an interrupt acknowledge and will thus be decoded by the zao PIO.
Clock, power, and ground signals are absolutely standard. The same clock signal is used by the PIO and the zao
CPU.
Observe that there is no Reset signal to the PIO. M 1 low with both RD and IORO high constitutes a reset. We will
describe the effect of a
PIO reset after discussing operating modes.
zao
7-47
D2
D7
D6
CE
C/O SEL
B/A SEL
A7
A6
A5
A4
GND
A3
A2
..,
.....
..
.
.
..
1
40
2
39
3
4
38
37
5
36
6
?
35
34
8
9
33
32
10
11
.
Z80
PIO
31
30
12
29
13
28
A1
14
27
AO
15
26
"'i3Silf
16
17
A RDY
18
25
24
23
DO
19
20
A STB
D1
'"
--
--
.,
D5
M1
iORci
RD
-'"
B7
--'"
B6
,;,
-
D3
D4
~
-
.
.
B5
B4
B3
B2
B1
BO
+5V
-...
iEi
-'"
iNT
22
lEO
21
B RDY
PIN NAME
DESCRIPTION
TYPE
DO - D7
Data Bus
Tristate. Bidirectional
CE
Device. Enable
Input
B/A SEL
Select Port A or Port B
Select Control or Data
Input
M1
Instruction fetch machine cycle
signal from CPU
Input
IORO
RD
Input/Output request from CPU
Input
Read cycle status from CPU
Input
Ad - A7
A RDY
Port A Bus
Tristate. Bidirectional
Register A Ready
Output
A STB
BO - B7
Port A strobe pulse.
Port B Bus
Register BReady
Input
Tristate. Bidirectional
Input
lEI
Port B strobe pulse
Interrupt enable in
..!§Q..
Interrupt enable out
Output
INT
Interrupt request
Output, Open-drain
<1>, + 5V,GND
ciock. Power and Ground
C/O SEL
B RDY
B STB
Input
Output
Input
Figure 7-17. Z80 PIO Signals and Pin Assignments
7-48
zao PIO OPERATING MODES
To the programmer, a Z80 PIO will be accessed as four addressable locations:
r----------,
I
I/O Port A logic
cw
I/O Port A
AO - A7
I/O Port A
~
a:
o
a.
Data
r-~~--~~~~-------A~B
I/O Port A
a:
o(J
t------~I
L.__~co:n~tr~o~I__~t__,--------~ARDY
~
en
~
U
o
I
w
Data 8us
DO - D7
IL-, __________ I
~
/'0----.. . ."
r----------,
I
I
I/O Port 8 logic
CI)
CI)
«
I/O Port 8
~
l.__~c~o~n:tr~ol~__.t-,----~.. 8RDY
w
Z
a:
o
al
I/O Port 8
CI)
o
Data
~
I/O Port 8
80 - 87
«c
«
@
By loading appropriate information into the Control regis~er you determine the mode in which the I/O port is to
operate.
.
The Z80 PIO has operating modes which are equivalent to those of the 8255 PPI, plus an additional mode which
the 8255 PPI" does not have. However. 8255 PPI Mode a provides 24 I/O lines. as against a maximum of 16 I/O lines
.
available with the Z80 PIO.
Zilog literature uses Mode O. Mode 1. Mode 2. and Mode 3 to describe the ways in which the Z8P PIO can operate: in
order to avoid confusion between mode designations as used by the Z80 PIO and the 8255 PPI. mode equivalences are
.
given in Table 7-6.
Table 7-6. Z80 PIO And 8255 Mode Equivalences
Z80 PIO
8255 PPI
INTERPRETATION
Mode 3*
Mode a
Mode 1
Mode 2
Mode 3
Mode a
Mode i
Mode 1
Mode 2
None
Simple input or output
Output with handshaking
Input with handshaking
Bidirectional I/O with handshaking
Poi"! pins individually assigned as controls
*Sp'ecial case of Mode 3
Let us now look at the Z80 PIO modes in more detail.
Output mode (Mode 0) allows Port A and/or Pqrt B to be used as a conduit for transferring data to external logic.
Figure 7-18 illustrates timing for Mode O. An output cycle is initiated when the CPU executes any Output instruction
accessing the I/O port. The Z80 PIO does not receive the WR pulse from the CPU. therefore it derives an equivalent signal by ANDing RD • CE • C/D • 10RG.
This pseudo write pu Ise (WR* in Figu re 7-18) is used to strobe data off the Data Bus and into the addressed I/O port's
Output register. After the pseudo write pulse goes high. on the next high-to-Iow transition of the clock pulse <1>. the
RDY control signal is output high to external logic. RDY remains high until external logic returns a low pulse on the STB
acknowledge. On the following high-to-Iow clock pulse transition. RDY returns low. The low-ta-high STB transition
also generates an interrupt request.
7-49
WR*
PORT OUTPUT
(8 BITS)
ROY
STB
INT
--~'---MODE 0 (OUTPUT) TIMING
W~·= RD
.'CE • C/O·
iORQ
Figure 7-18. Mode 0 (Output) Timing
The ROY and STB signal transition logic has been designed to let ROY create STB.1f you connect these two signals. the
ROY low-to-high transition becomes the STB low-to-high transition and ROY is strobed high for one clock pulse only.
This may be illustrated as follows:
ROY
I
STB
Timing for input mode (Mode 1) is illustrated in Figure 7-19. External logic initiates an input cycle by pulsing STB
low. This low pulse causes the Z80 Pia to load data from the I/O portpins into the port Input register. On the rising
edge of the STB pulse an interrupt request will be triggered.
On the falling edge of the clock pulse which follows STB input high. ROY will be output low informing external logic
that its data has been received but has not yet been read. ROY will remain low until the CPU has read the data. at which
time ROY will be returned high ..
It is up to external logic to ensure that data is not input to the.Z80 PIO while ROY is low. If external logic does input data to the Z80 Pia while ROY is low. then the previous data will be overwritten and lost -and no error status will
be reported.
In bidirectional mode (Mode 2), the control lines supporting I/O Ports A and B are both applied to bidirectional
data ~e~ng transferred via Port A; Port B must be set to bit control (Mode 3).
Figure 7-20 illustrates timing for bidirectional data transfers. This figure is simply a combination of Figures 7-18 and
7-19 where the A control lines apply to data output while the B control lines apply to data input. The only IJnique
feature of Figure 7-20 is that bidirectional data being output via Port A is stable only for the duration of the A STB low
pulse. This is necessary in bidirectional mode since the Port A pins must be ready to receive input data as soon as the
output operation has been completed.
'
Once again. it is up to external logic to make sure that it conforms with the ti~ing requirements of bidirectional mode
operation. External logic must read output data while A STB is low. If external logic does not read data at this time. the
data will not be read and the Z80 Pia will not report an error status to the CPU; there is no signal that external logic
sends back to the ZBO Pia following a successful read.
7-50
Also. it is up to external logic to make sure that it transmits data to Port A only while B ROY is high and A ROY is iow. If
external logic tries to input data while the Z80 PIO is outputting data. input data will not be accepted. If external logic
tries to input data before previously input data has been read. the previously input data will be lost and no error status
will be reported.
Q
w
~
oQ..
a:
o
a:
STB
~
PORT INPUT
(8 BITS)
en
w
ROY
u
~
g
INT
CI)
CI)
<
call
w
Z
a:
o
CD
CI)
o
Figure 7-19. Mode 1 (Input) Timing
~
<
<
@
Q
A ROY ________________
~
ASTB
PORT A
DATA BUS
INT
'BsTB
BRDY
WR·= RD • CE • C76 • IORQ
Figure 7-20. Port A. Mode 2 (Bidirectional) Timing
Control mode (Mode 3)does not use control signals. You must define every pin of an 1/0 port in Mode 3 as an input or an output pin. The section on programming the Z80 PIO explains how to do this. Timing associated with the actual transfer of data at a single pin is as illustrated in Figures 7-18 and 7-19. ignoring the RDY and STB signals. If all the
pins of a single port are defined in the same direction. then that port can beused for simple parallel input or output
(without handshaking).
zao PIC INTERRUPT SERVICING
The Z80 PIO ha's a single interrupt request line via which it transmits 'int~rruPt reque~ts to the CPU.
An interrupt request can originate from 1/0 Port A logic, or from I/O' Port B logic.
terrupt requests, 1/0 Port A logic has higher priority.
In the case of simultaneous in.
An interrupt request may be created in one of two ways. We have already seen in our discussion of Modes O. 1 and 2
that appropriate control signal transitions will activate the interrupt request line; that is the first way in which an interrupt request may occur. In Mode 3 you can program either liD port to generate an interrupt request based on the status
of Signals at individual 110 port pins; you can specify which 110 port pins will contribute to interrupt request logic and
what the pin states must be for the interrupt request to occur. In a microcomputer system that has more than one Z80
PIO. interrupt priorities are arbitrated using daisy chain logic as we have already described. But there is a significant
difference between priority arbitration within a Z80 system as compared to typical priority arbitration. Figure 7-21 il7
lustrates interrupt acknowledge timing.
7-51
LAST T
STATE
INT
-IO-R-O AND
,..-____ }
Mi INDICATE
INTERRUPT ACKNOWLEDGE
M1
lEO
lEI
Figure 7-21.
Int~rrupt
Acknowledge Timing
The zao PIO requires the CPU to execute an RETI instruction upon concluding an interrupt service routine.
Following an interrupt. an acknowledged Z80 PIO continously~cans the Data Bus whenever M 1 is pu Ised low. Until an
RETI instruction's object code is detected. the acknowledged Z80 PIO will continuously output lEO low. thus disabling
all lower priority Z80 PIOs. As soon as an RETI instruction's object code is detected on the Data Bus. the Z80 PIO will
output lEO high. thus 'enabling lower priority Z80 PIOs. What this means.is that interrupt priorities extend to the interrupt service routine as well as the interrupt request arbitration logic. Once an interrupt has been acknowledged. all
lower priority interrupt requests will be denied until the acknowledged interrupt service routine has completed execution and has executed an RETI instruction. However. higher priority interrupts can be acknowledged and in turn interrupt an executing service routine. This .is identical to the priority arbitration logic which we described for the 8259
. PICU.
You can. if you wish. enable lower priority interrupts by executing an RETI instruction before an interrupt service
routine has completed execution. But this requires that you execute an RETI instruction in order to return from a
subroutine within the interrupted service routine. This instruction sequence may be illustrated as follows:
;START OF INTERRUPT SERVICE ROUTINE
CALL
ENABLE
ENABLE
RET
RETI
;ENABLE ALL INTERRUPTS AT PIO DEVICES
;END OF INTERRUPT SERVICE ROUTINE
If you simply executed an RETI instruction shortly after entering an interrupt service routine. you would make a hasty
exit from the routine - before completing the tasks that have to be performed in response to the acknowledged interrupt..
PROGRAMMING THE
You program the
zao
PIO
zao PIO by outputting
a series of commands.
Let us start by identifying command format.
If the 0 bit of a command is low, then the receiving I/O port logic will interpret the command as an interrupt vector, with which it must respond to an interrupt acknowledge. assuming that the CPU is operating in interrupt Mode 2:
7 6 5 4.
3
I I I I· I
2
1 0 - - - - - Bit No.
I0 t-----
Command Byte
~""""""''''''''''-''''''''('''~---lnterrUPt
'-,
V
t
vector specified
" ' - - - - - - - - Output these eight bits when
an interrupt request is acknowledged
7-52
Do not confuse CPU interrupt modes with I/O port modes: they have nothing in common.
In order to define an I/O port's mode you must output a Control code to the I/O port's Control buffer. This is the
Control code format:
7 6 5 4 3 2 1 0 - - - - Bit
No.
Tr-rIX=~~~~~o~~:~coo,
Q
w
~
a:
o
Q.
I-------------00
~---
a:
o
(.)
~
Don't Care
III
0
e:(
Output, Mode
01 Input, Mode 1
U
10 Bidirectional, Mode2
w
l-
oCI)
11 Control, Mode 3
CI)
e:(
ciS
w
Z
a:
o
III
CI)
Observe that the same address, the I/O Port A or B Control buffer address, is used when outputting a Control code, an
interrupt vector, or a mode select. The low-order four bits of the Control code determine the way in which the Control
code will be interpreted. The following Control code will enable or disable interrupts:
o
::?!
e:(
Q
e:(
~Bit No.
7 6 5 4 3 2 1 0
.....11-- Control Code
@
~:t:=:o:~r:::-
- - - - - - Interrupt enable control
- - - - - - - - - - Don't Care
' -_ _ _ _ _ _ _ _ _ _--( 0 Disable interrupts
1 Enable interrupts
If a Mode Select Control code is output specifying that an I/O port will operate in Mode 3·, then the next byte
output is assumed to be a pin direction mask. 1 identifies an input pin, whereas 0 identifies an output pin. Here is a
sample instruction sequence:
LD
LD
OUT
LD
OUT
C,(PORTAC)
A,OCFH
(Cl.A
A.3AH
(Cl.A
:LOAD PORT A CONTROL ADDRESS INTO REGISTER C
:LOAD MODE 3 SELECT INTO ACCUMULATOR
:OUTPUT TO PORT A CONTROL REGISTER
:DEFINE PINS 5, 4, 3 AND 1 AS INPUTS,
:PINS 7, 6, 2 AND 0 AS OUTPUTS
If you set an I/O port to Mode 3, th~n you can define the conditions which will cause an interrupt request; you
do this by outputting the following interrupt Control code:
7 6
......f----Bit No.
5
...........--Control Code
~~~--~--~--~
- - - - - - - Interrupt control word
~
_______-<
1 if interrupt select mask follows
o otherwise
1 high input on selected pins is active
o low input on selected pins is active
1 AND selected pins for interrupt
o OR selected pins for interrupt
1 Enable interrupts
o Disable interrupts
7-53
When you output an interrupt Control code. as illustrated above. if bit 4 is 1. Z80 PIO logic will assume that the next
Contr.ol code output is an interrupt mask. An interrupt mask selects the pins that will contribute .to interrupt request
logic. A 0 bit selects a pin. while a 1 bit deselects the pin.
' .
.
Combining the various Control codes that have been described we can now illustrate a typical sequence of instructions
for accessing a Z80 PIO. Assume that PIO 1/0 port addresses are:
Port
Port
Port
Port
A
A
B
B
data
command
data
command
4
5
6
7
We are going to set I/O Port B to Mode 3. with an interrupt request triggered by either pin 6. 3 or 2 high. Pins 6.3. 2
and 1 will be input pins. while pins 7. 5. 4 and 0 are outputs. The Port B interrupt vector will be 04. Port A will be a
bidirectional 1/0 port with an interrupt vector of 02. Here is th'e initialization instruction sequence:
LD
OUT
LD
OUT
.LD
LD
OUT
LD
OUT
LD
OUT
LD
OUT
LD
OUT
A8FH
(5).A
A2
(5).A
C.7
AOCFH
(Cl,A
AAEH
(C).A
A4
(Cl.A
AOB7H
(Cl,A
AOB3H
(C).A
THE
;SET PORT A TO MODE 2
;OUTPUT INTERRUPT VECTOR
;SET PORT B ADDRESS IN C
;SET PORT B TO MODE 3
;OUTPUT PIN DIRECTION MASK
;OUTPUT INTERRUPT VECTOR
;OUTPUT INTERRUPT CONTROL WORD
;OUTPUT INTERRUPT MASK
zao CLOCK TIMER CIRCUIT ·(CTC)
The Z80 Clock Timer Circuit is a programmable device which contains four sets of timing logic. Each set of timinglogiccan 'be programmed independently as an interval timer or an external event counter.
The master Z80
'~ystem
clock is used by interval'timer logic. A time out may be ide'ntified
b~a'n inte~ruPt
request.
An external signal is used to trigger decrement logic when the timer is functioning as an event counter. An interrupt
may be requested when the predetermined number of evel!ts countout.
If you compare the Z80 CTC with the 8253 CounterlTimer described in Chapter 4. you will see that the Z80 CTC
has four sets of counter/timer logic as compared to the three sets of the 8253; however the 8253 has more programmable options. In addition to functioning as an event counter or an interval timer. the 8253 can be programmed to
generate a variety of square waves and pulse outputsignals.
The Z80 CTC is fabricated using N-channel depletion load technology. It is packaged as a 28-pin DIP. All pins are
TTL-level compatible.
zao eTC FUNCTIONAL ORGANIZATION
Before we examine pins, signals, and operating characterics of the Z80 CTC in detail, let us take an overall look
at device logic.
There are four counterltimer logic elements in a Z80 CTC; each is referred to as a "channel".
7-54
Each of the four counter/timer channels may be visualized as consisting of three a-bit registers and two control
signals. This may be illustrated as follows:
cw
~
a:
0
Q.
a:
0
CJ
~
enw
~.
g
en
en
~
o!I
w
z
III
:::>
co
-I
«
z
0
a:
w
en
~
a:
al
Channel 0 only
a-bit
Control
Register
t-
a-bit
Time Constant
Register
0
~
~
C
ClK/TRG
~
@
a-bit
Down Counter
Register
Control logic
An initial counter or timer constant is loaded into the Time Constant register. The value in the Time Constant
register is maintained unaltered until you write a new value into this register.
The initial Timer Constant is loaded into the Down Counter register at the beginning of a counter or timer operation; the contents of the Down Counter register are decremented. You can at any time read the contents of the Down
Counter register in order to determine how far a time interval or event counting sequence has progressed.
The Channel Control register contains a Control code which defines the channel's programmable options. There
are four Control registers. one for each of the four channels. Thus one channel's operations in no way influence operations for any other channel.
There is an Interrupt Vector register which is addressed as though it were part of channel 0 logic. This register
contains the address which is transmitted by the zao CTC upon receiving an interrupt acknowledge. The Z80
CTC assumes that the Z80 CPU is operating in Interrupt mode 2 - in which mode the device requesting an interrupt
responds to an acknowledge by providing the second byte of a subroutine address which the CPU will Call. For details
. refer to our earlier discussion of the Z80 CPU.
zao CTC PINS AND SIGNALS
zao CTC pins and signals are illustrated in Figure 7-22.
DO - 07 is the bidirectional Data Bus via which parallel data is transferred between the CPU and any register of the
Z80 CTC.
CE is the master chip select signal for the Z80 CTC. This signal must be low for the device to be selected .
. ·7-55
While CE is low.
eso and eS1
are used to select one of the four counter/timer logic channels as follows:
CS1
CSO
Channel
o
o
o
o
1
1
1
1
1
2
3
o
D4
1
18
D5
06
2
27
3
4
26
D2
D1
25
DO
5
24
6
23
-
D7
GND
R5
ZC/TOO
7
ZC/T01
8
9
ZC/T02
iO'RQ
lEO
INT
lEI
--
M1
Z80
CTC
22
.
--
21
20
D3
+5V
ClK/TRGO
ClK/TRG1
ClK/TRG2
CLK/TRG3
10
19
11
18
CSO
12
17
REsET
13
14
16
15
.L
CS1
CE
-
PIN NAME
DESCRIPTION
TYPE
DO-D7
CLK/TRGO,
Data Bus
Bidirectional. tristate
}
External Clock or timer trigger
Input
}
Zero Count or timeout indicator
Output
Instruction fetch machine cycle
Input
ClK/TR01.
ClK/TRG2.
ClK/TRG3.
ZC/TOO
ZC/T01
ZC/T02
Mi
signal from CPU
iORQ
Input/Output request from CPU
AD
Read cycle st. + 5V. GND
Clock. power and ground
Figure 7-22. ZBO-CTC Signals and Pin"Assignments
7-56
CSO and CS 1 select registers associated with counterltimer logic. to be accessed by read and write operations. The actual register which will be accessed is determined as follows:
Write to Channel
J•
Q
w
~
a:
o
Q.
•
•
~ ..
Read from channel
•
0
Bit No.
a:
o
o
X
Data written
enw
0 - - -....... X
7 6 5 4
3 2
~
•
•
Down Counter
= O. channel = 0
Select Interrupt
~
C3
o
Vector
en
en
~---~ X = 1. select Channel
Control register on
first access.
ct
oil
w
Z
....- - - -.....-If Y = 0 ~Select Time Constant register
I..:' '.
on next write
a:
o
III
en
If Y = 1 ~ Select Channel Control register
o
~gain
~
ct
Q
ct
on next write
(If Channel = O. select on next
write according to X.I
@
As the illustration above would imply. the Down Counter register is the only location of any channel whose contents
can be read. All other registers are write only locations.
When you write to a channel. bits 0 and 2 of the data byte being written determine the data destination as follows:
1)
If bit 0 is 0 and you are selecting channel O. then ,the data is written to the Interrupt Vector register.
2)
3)
4)
If bit 0 is 0 and you select channel 1. 2 or 3. the data destination is undefined.
If bit 0 is 1. then on the first access of any channel the data will be written to the Channel Control register.
If within the data byte written to a Channel Control register bit 0 is 1 and bit 2 is O. then the next data byte written
to this channel will be loaded into the Time Constant register. irrespective of whether bit 0 is 0 or 1. The data written will be interpreted as a time constant; select logic will immediately revert to selecting the Channel Control
register or the Interrupt Vector register on the next write. depending on the condition of bit 0 of the next data byte.
M 1. IORG and RD are three control signals input to the l80 CTC. Combinations of these three control signals control
logic within the zao CTC. as described for the zao PIO. An exception is the device Reset. The l80 CTC has its
own RESET input. The PIO decodes a Reset when M 1 is low while IORO and RD are high. With the exception of the
RESET function. Table 7-4 defines the manner in which the l80 CTC interprets M1. IORO, and RD signals.
Interrupt logic has three associated signals: lEI. lEO and INT. These signals operate exactly as described for the
l80 PIO.
The l80 CTC requests an interrupt with a low INT output.
lEI and lEO are used to implement daisy chain priority interrupt logic as described for the PIO.
Each of the four counter/timer channels has a CLK/TRG input control. This signal can be used to trigger timer logic;
it is also used as a decrement control by counter logic.
Counterltimer logic channels O. 1 and 2 have a lC/TO output. This signal is pulsed high on a time out or a count out.
When a low input is applied to the RESET pin. the zao CTC is reset. At this time all counterltimer logic is stopped.
INT is output high. lEO is output at the lEI level and the Data Bus is floated. Register contents are not cleared during a
' . ,
reset.
zao CTC OPERATING
MODES
The zao CTC is accessed by the CPU as four I/O ports or four memory locations. Timing for any CTC access conforms to descriptions given earlier in this chapter for the CPU.
Let us begin by looking at a counter/timer operating a~ a timer.
7-57
Using an appropriate Control code (described later) you select Timer mode for the channel and specify that an initial
time constant is to follow.
You load an initial constant into the Time Constant register, after which timer operations begin.
You have the option of using the CLKfTRG input to start the timer, in which case timer logic is initiated by external
logic. The alternative is to initiate the timer under program control. in which case the timer starts on the clock pulse
fo!lowing the Time Constant register being loaded.
When timer operations begin, the Time Constant register contents are transmitted to the Down Counter register. The
Down Counter register contents are decremented on every 16th system clock pu Ise, or On every 256th system clock
pulse. You make the selection via the Control code. Assuming a 500 nanosecond clock, therefore, the timer will decrement the Down Counter register contents every 8 microseconds, or every 128 microseconds.
When timer logic decrements the Down Counter register contents from 1 to 0 a time out occurs. At this time ZC/TO is
pulsed high, the Time Constant register contents are reloaded into the Down Counter register and timer logic starts
again. Thus timer logic, is free running; once started, the timer will run continuously until stopped by an appropriate
Control code.
Here is a timing example for a timer started under progr.am control and decrer:nenting the Down Counter register on every 16th clock pu Ise:
"1
2
3
..
15 16
15 16
15
16
2
4>
ZC/TO
INT
Output
Control
Output
Initial
Time Constant
to Down Counter
Decrement
Down Counter
Code
Time
Register. Start
Timer'
Register
Constant
Down Counter Register
Decrements from 1 to O.
Refoad Down Counter from
Time Constant Register and
restart timer
Here is a timing example for a timer,whose operations are initiated by CLKfTRG, where the Down Counterregister contents are decremented on every 256th clock pu IS8:
2
3
255 256
255 256
1
1
255
256
CLK/TRG
ZC/TO
INT
Output
Output
Time
Decrement
Down Counter
Restart
Control
Code
initial
Constant
to Down
Down Counter
Register
Register decrements
Timer
time
constant
" from 1 to O.
Counter
Reload Down
Register,
Counter from
Start
Time Constant
Timer
register
7-58
Observe that every time out is marked by a ZCITO high pulse. iNf is also output low providing interrupt logic is enabled
at the channel.
In the illustra'tion above ClKITRG is shown as a high true signal. You can specify ClK/TRG as a low true signal via the
Channel Control code; the timer will be initiated as follows:
Q
w
a:
o
u
~
en
w
~
U
o
II)
II)
ct
all
w
a:
2
o
In
II)
o
~
ct
Q
ct
@
2
Itl/
~
a:
oQ.
\
CLK/TRG
I
2~
\
I
\
I
For exact timing requirements see the data sheets at the end of this chapter.
. You can at any time write new data into the Time Constant register. If you do this while the timer is running. nothing
happens until the next time out: at that time the new Time Constant register contents will be transferred' to the Down
Counter register and subsequent time intervals win be computed based on the new Time Constant register contents.
If you are unfortunate enough to output data to the Time Constant register while a time out is in progress and the Time
Constant register contents are being transferred to the Down Counter register. then an undefined value will be loaded
into the Down Counter register; however. following the next time out the new value in the Time Constant register will
apply; that is to say. there will only be one undefined time interval.
Let us now look at a counter/timer operating as a counter.
Using an appropriate Control code (described later) you se'lect Counter mode for the channel and specify that an initial
time constant is to follow.
.You load an initial constant into the Time Constant register. after which counter operations begin.
When counter operations begin. the Time Constant register contents are transmitted to the Down Counter register. The
Down Counter register contents are decremented every time the ClKITRG input makes an active transition. Counter
logic begins on the first active transition of ClKITRG following data being loaded into the Time Constant register. The
active transition of ClKITRG may be s~l~cted under program control as low-to-high or high-to-Iow.
When counter logic decrements the Down Counter register contents from 1 to O. a count out occurs. At this time the
ZCITO si.gnal is pulsed high; an interruPl request occurs. providing the channel's interrupt logic has been enabled. The
Time Constant register contents are reloaded into the Down Counter register and counter operations begin again. That
is to say. counter logic is free running and V'/ill continue to re-execute until specifically stopped by an appropriate Control code. Counter logic timing may be illustrated as follows:
~
.1\.J\JVl....MA...
CLK/TRG
ZC/TO
Output
Control
Output
Initial
Code
Time
Start
Decrement
Down Counter
Restart
Counter
Down Counter
register
Colinter
~~gister •
decrements
Constant
from 1 to 0
7-59
zao CTC INTERRUPT LOGIC
1
Every zao CTC channel has its own interrupt logic. A channel's interrupt logic generates an interrupt request
when the channel counts out or times out. All interrupt requests are transmitted to the CPU via the INT output.
This is true if one, or more than one channel is requesting an interrupt. If more than one channel is requesting an
interrupt, then priorities are arbitrated as follows:
.'
Channel a
Channell
Channel 2
Channel 3
Highest Priority
Lowest Priority
Every channel's interrupt logic can be individually enabled or disabled under program control.
The zao CTC device's overall interrupt logic is identical to that which we have already described for the
PIO.
zao
The interrupt request is transmitted to the CPU via a low INT signal.
The CPU acknowledges the interrupt by outputting M 1 and IORO low as illustrated in the data sheets at the end of this
chapter.
The device requesting an interrupt which is highest in the daisy chain acknowledges the interrupt. Presuming this is a
Z80 CTC, the CTC places its interrupt vector on the Data Bus; it is assumed that the CPU is operating in Interruptmode
2. The Z80 CTC immediately outputs lEO low, disabling all devices below it in the daisy chain.
When an RETI instruction is executed, Z80 CTC logic sets lEO high again.
For more information on Z80 interrupt logic refer to discussions of this subject given earlier in the chapter for the Z80
CPU and the PIO.
PROGRAMMING THE
These
1)
2i
~re
zao CTC
the steps required to program a
zao CTC:
Output an interrupt "ector once, when initializing the zao CTC.
For each active counter/timer channel, output one or more Control codes. Control codes are used initially to
set counter/timer operating conditions and to load the Time Constant register. Subsequently Control codes
are used to start and stop the counter/timer, or to change the initial time conslant.
The interrupt vector is written to a counterltimer by outputting a byte of data to counterltimer channel
low order bit. The interrupt vector may be illustrated as fo'liows:
.. :
7 6
5 4
2
O~BitNo.
r-~~~~~~~
~~-- Interrupt Vector'
~~=~,..
' - - - - Must be 0 to identify Interrupt Vector
'------Ignored by
zao CTC which substitutes
bits as follows:
o 0 for Channel 0 interrupt
o 1 for Channel 1 interrupt
1 0 for Channel 2 interrupt
1 1 for Channel 3 interrupt
......- - - - - - - - - Address bits stored
7-60
a with a a in the
The Control code which must be output to each active channel will be interpreted as illustrated in Figure 7-23.
7 6 5 " 3 2 1 0 ~ Bit
I I I I I 1 1 11: c
...
ct·
w
.,
J
,
~
~
+
No.
Control code
Must be 1 to identify data as a Control code
a::
o0..
RESET
o(J
lOAD
a::
1 stops channel immediately or
leaves it running
o
~
enw
Next data output is a time constant to be loaded into
the Time Constant register. If counter/timer is not
CI)
CI)
running. do not start until time constant has been written.
No time constant follows.
TRIGGER
If timer is stopped. start on ClK/TRG
Timer Mode
Only"
o If timer is stopped. start on
ct
SLOPE
~
o
g
ciJ
w
Z
l
f
1 ClK/TRG positive edge triggered
o ClK/TRG negative edge triggered
RANGE
a::
1 Decrement Down counter every 256th pulseol Timer M~de
16th pulse.
Only
.
o Decrement Down counter every
o
1:0
MODE
CI)
o
~
IE
ct
ct
C
r
1 Counter mode
o Timer mode
Enable channel interrupt
o Disable channel interrupt
@
Figure 7-23. Z80 CTC Control Code Interpretation
Bit 0 must be 1 to identify the data as a Control code. If bit 0 is O. then the data is interpreted as an interrupt vector .
providing Channel 0 is addressed: the data is undefined otherwise.
Bitl is used to stop the channel when it is running. If bit 1 is O. then every time the channel times out the Down
Counter register is immediately reloaded from the Time Constant register contents and channel operations restart according to current options. If bit 1 is 1. the channel stops immediatel'y: the ZC/TO output is inactive and channel interrupt logic is di~abled. The channel must be restarted by outputting a new Control code.
Bit 2 is used to output time constants. If bit 2 is 1. then the next data output to the channel will be interpreted as a time
constant. If bit 2 is O. then the next data output to the channel will be interpreted as another Control code. or an interrupt vector. depending on the pit 0 value.
Bit 3 applies to Timer mode only: assuming that the timer is not running. it determines whether timer operations will be
initiated by the system clock signal <1>. or by ClK/TRG.
If bit 3 is 0 then timer qperations are initiated by system clock signal <1>; the timer will start on the next leading edge of
<1>. unless the current Contrql code specifies (via bit 2) that a new time constant is to be output. in which case the timer
will start on the rising edge of which immediately follows output of the time constant. Timing for thes'e two cases has
been illustrated ~arlief;
.
I
If bit 3 is 1. then the actiye tran~ition of the ClK/TRG signal initiates the timer. Once again. if bit 2 of the current Control code specifies that a 'new time constant is to be output then timer logic cannotbe started until this new time constant has been output. Tillling ha~ been illustrated earlier.
Bit 4 determines whether the low-to-high or the high-to-Iow transition of ClK/TRG is active. Assuming that bit 6 has
specified Timer mode and bit 3 has specified the timer will be triggered externally by ClK/TRG. the active transition of
ClK/TRG starts the timer. If bit.6 is not 0 or bit 3 is not 1. then the active transition of ClK/TRG decrements the counter.
If bit 4 specifies that a low-to-high transition of ClK/TRG will be active then ClK/TRG may be illustrated as follows:
-----.. .\" _____~---
~---_r;..
CLK/TRG _ _ _ _ _
If bit 4 specifies th~H the high-to-Iow transition of ClK/TRG will be active then ClK/TRG may be illustrated as follows:
ClK/TRG
--~
-c)I.________________..,1
7-61
Bit 5 applies to Timer mode only. If bit 5 is O. Down Counter register contents will be decremented every 16th system'
clock pulse (<1». If bit 5 is 1. the Down Counter register contents will be decremented every 256th system clock pulse
(<1».
Bit 6 determines whether the channel will be operated as a counter or a timer. If bit 6 is O. Timer mode is selected;
Counter mode is selected if bit 6 is 1.
Bit 7 is an interrupt enable/disable flag. If O. the channel's interrupt logic is disabled; if 1. the channel's interrupt logic
is enabled.
Let us now look at the programming example. Here are the assumed operating conditions for the
Z~O
CTC:
1)
Channel 0 is operating as a counter with an ,initial time constant of 8016 and interrupt logic enabled.
2)
Channel 1 is operating as a timer. It decrements on every 16th system clock pulse and has an initial time constant
of 4016; its interrupts are disabled and CLK/TRG starts the tiryler on its low-to-high transition.'
.
3)
Channel2 is operating as a timer. It decrements every 256th system clock pulse and has an initial time constant of
C816; its interrupts are enabled and the system clock starts the timer.
Channel 3 is inactive.
4)
The CPU is operating with interrupt logic in Mode 2. CTC interrupt service routine starting addresses are stored at
memory locations 2C4016. 2C4216 and 2C4416. The CTC is accessed as I/O ports B816. B916. BA16. and BB16.
Here is the appropriate CTC initiation instruction sequence:
LD
LD
A.2CH
I.A
;LOAD INTERRUPT VECTOR REGISTER OF CPU
1M
2
;SELECT CPU INTERRUPT MODE 2
;OUTPUT INTERRUPT VECTOR TO
;CHANNEL 0
LD
A.40H
OUT
(OB8H).A
;ST ART CHANNEL 0
LD
' A.OC5H
OUT
(OB8Hl.A
LD
A.80H
OUT
(OB8H).A
;START CHANNEL 1
LD
A.1DH
OUT
(OB9Hl.A
LD
A.40H
OUT
(OB9Hl.A
;ST ART CHANNEL 2
LD
A.OA5H
OUT
(OBAHl.A
LD
A.OC8H
OUT
(OBAHl.A
;OUTPUT THE CONTROL CODE TO CHANNEL 0
;OUTPUT THE INITIAL COUNT TO CHANNEL 0
;CHANNELO BEGINS OPERATING.
;OUTPUT THE CONTROL CODE TO CHANNEL 1
;OUTPUT THE INITIAL TIMER CONSTANT TO CHANNEL 1
;CHANNEL 1 BEGINS OPERATING. (IF TRANSITION OCCURS)
;OUTPUT THE CONTROL ~ODE TO CHANNEL 2
;OUTPUT THE INITIAL TIMER CONSTANT TO CHANNEL 2
;CHANNEL 2 BEGINS ORERATING
7-62
DATA SHEETS
This section contains specific electrical and timing data for the following devices:
c
w
~
a:
o0..
Z80 and Z80A CPU
Z80 and Z80A PIO
Z80 and Z80A eTC
a:
o
CJ
~
en
w
~
g
en
en
c:(
c1J
w
Z
a:
o
al
en
o
~
c:(
cc:(
@
7-D1
ZBO-CPU
Absolute Maximum Ratings
Spedfied operating range.
-6S·C to + ISO·C
-{).3V to +7V
Temperature Under Bias
Storage Temperature
Voltage On Any Pin
with Respect to Ground
Power Dissipation
·Comment
NOle
l.5W
Capacitance
Z80-CPU D.C. Characteristics
T A =o·C to 70·C. Vcc
=5V t
T A = 2Soc, f = 1 MHz,
unmeasured pins returned to ground
5% unless otherwise specified
Symbol
Parameter
Min.
Max.
Unit
VILC
Clock Input Low Vol .. ge
-0.3
0.45
V
VIHC
Cluck Input High Voltage
Vcc -.6
Vce+·3
V
V IL
Input Low Voltage
-0.3
0.8
V
VIH
Input HIgh Voltage
2.0
Vcc
V
0.4
V
Typ.
VOL
Output Low Voltage
VOH
Output High Voltage
ICC
P~wer
Supply Current
150
rnA
III
Input Leakage ('urrent
10
iJ A
I LOll
Tri·State Output Leakage Current in Float
10
iJA
ILOL
Tri·State Output Leakage Current in Float
-10
iJA
ILO
Data Bus Leakage ('urrent in Input Mode
tlO
iJA
~.4
V
Test Condition
IOH = -250iJ A
VOUT =O.4V
1\1
70 0r.
v\."\.' :; 5 V !
Parameter
VIL(,
P",k Input Luw
VIII(,
Ch.,k Input Iltg,h V"ltJge
Typ.
Max.
Unit
0.45
V
Vee -.6
V ec +·3
V
V IL
Input L"" V"ltage
-0.3
O.H
V
VIII
Inputlllgh VollJge
~.U
V( (
V
VOl
Output Lo" VoltJge
VOII
Outputll'g,1t V"ltJgc
1('('
PII"~r Supply ('lIITl'llt
III
Inpul Lt';JkJgl'
11.011
TU,SIJII' Output LI'JJ..Jgt:' ('urr1.'111 III
lUll.
11.1)
0.4
V
V
~.4
90
200
iliA
IU
iJA
10
iJ/\
TrI·StJt" Outpul I.eakage Current III Float
-10
iJA
IlJtJ ilu, Leakage ('urrent In Input Mode
tlO
iJA
('urrl'lll
FI\I;.t1
Max.
Unit
.~5
pF
/0
pF
('
CIN
Input Capacllanee
COUT
Output Capacitanee
pF
Z80-CPU
Ordering Information
C PS EM-
Ceramic
Plastic
Standard 5V t5%0· to.70·C •
Extended 5V '5% -40 to 85 C
Military 5V ;10%-55· to 125·C
= 2S°e, f = I MHz.
unmca,urcd pins relurncd tll ground
-0.3
Min.
V"lta~e
Parameler
Clock rapacltanee
TA
5'; unl~~~ other" 1St:' ~P~(1 fled
Symbol
Symbol
Capacitance
z8oA.cPU D.C. Characteristics
T A :; 0"'(,
For lNO-CPU all AC and DC characterIStics remain Ihe
same for the mlllli:UY grade puts except Icc'
Stresses above those listed under "Absolute
Maximum Rating" may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device
at these or any other condition above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
Test Condition
Symbol
Parameter
Ma,.
(',~
CI"d.
ClpJl.lld1h.:l'
35
pl'
CI ,-
IIIPUI
('.lrJI,:IIJlh.:\.'
,
1'1
('01'1
OlllPlit l'Jp,II.:II.IIh:l'
IU
I'F
IOL =I.~IIIA
Z80A-CPU
Ordering Information
(-Ceramic
P- Plastic
S - Standard 5V ±5% 0° to 70°C
We reprint data sheets on pages 7·02 through 7-013 by permission of Zilog. Incorporated.
7-02
Unit
Z80-CPU
A.C. Characteristics
TA
=oOe to 700e, Vee =+5V ± 5%, Unless Otherwise Noted.
c
w
~
o
11.
Sia nol
Symbol
a:
I,
a:
Iwl'I'1iI
Iw JLJ
o
11 ,1
u
~
IDIADI
IFIADI
iii
w
~
Ao-15
la~m
la":l
'~a
g
',,-a I
ct
IDIDI
IF IDI
IS4>1D1
ISI>II) + Iw(4)L) + Ir + If
J.JSCI.:
~OOO
30
Address Ouirul Delay
Dela) 10 Flual
Address Stable Pum 10 MRi'Q IMemmy ('ydel
Address Siable Pri,,, 10 JORO. RO or WR % (ydel
Add"ss SI.ble frum
~ I'O'RO or ~
Addn'ss Stable- FhHIl RD nr WR DUling Fluat
145
110
III
III
IJ.
141
!!!i.
Oala OUlpul Delay
Dela)· 10 Flual During Wrile ()'de
Da," SI>1Il + If-75
laci
PI
lea = t~'~L) + Ir - 40
;u
ou
141
leaf = Iw(>I>L) + Ir - 00
I~
151
Idem
6
(71
161
Idci
171
Icdf
181
Iw (MRL) = Ie - 40
19 1
I~MRH) = 1~>I>I1) + If- 30
230
z:
w
In
en
Any Hold Time fur Setup Time
o
~
IDLI> (MR)
IOHI>(1R)
10LI>(1R)
tOHI> (RO)
10LI> (RO)
IOHL) + Ir -80
IIU
. Ro Delay From Rising Edge of Clock. RD Low
jill Delay From Falling Edge of Clock.iP Low
WR Delay
WR Delay
=Ie - 210
191
Rising Edge of ('Joek.IORO Low
Falling Edge of Clock. 10RO Low
Rising Edge of Clock ,I ORO High
Falling Edge of Clock. IORO High
10L>I> (WR)
IOLI>H) + tf- 80
NOTES:
"1-""0
A. Data should bt eniibled t~U the ~data hus when RD IS a~tlve. DUring interrupt acknowledge data
should be enaobled when M I and IORO are both aocllve.
B. All (ontrol !llgnals are mternally synl.."hruI1lLCd.)() they may be totally asynchronous with re!lpel.."l
h) the duck.
C The Rl:.SET Signal mU!ll be al.."llv( for it nUllllnum of l dock (ydes.
O. Output lXlay V), Luaded ('apa(llan~e
TA = 70°C
Vce = +5V ±57<
Add 10nsec delay for each 50pf increase in load up 10 a maximum of 200pf for Ihe dala bus & I OOpf for
address & conlrollines
.
1'.. Although \Iall, hy deSign. t("sllng guarantee!l
1w(~H)
of
~OO IoIst'
maoxlmum
7-03
Load circuit for Output
Z80A-CPU
A.C. Characteristics
T A =oOe to 70°C. Vee
SianaJ
=+5V ± 5%. Unless Otherwise Noted.
Pan_t..
Min
Mill
Ie
Iw(H)
Iw(L)
Ir,r
Clock Period
Clock Pulse Widlh, Clock High
Clock Pulse Widlh, Clock Low
Clock Rise and Fall Time
.25
110
110
II ~I
IE]
2000
Ao-IS
10(AO)
IF(AO)
lacm
tltci
lea
leaf
Addre .. OulpUI Delay
Delay 10 Float
Addre .. Slab Ie Prior 10 MREQ (Memory Cycle)
Address Siable Prior 10 ~, 1m or WR (I/O Cycle)
Address Siable from im. WR. 10RO or JJIrnO
Addre .. Stable From Ro or WR During Floal
10(0)
IF(O)
IS(O)
ISi'(O)
Idem
Idei
ledf
Dala OuIPUI Delay
Delay 10 Floal During Wrile Cycle
Dala Selup Time to Rising Edge of Clock ,During MI Cycle
Dala Selup Time 10 Failing Edge of Clock Ouring M~ 10 MS
Data Slable Prior 10 WR (Memory Cycle)
.
Dala Slab Ie Prior 10 WIl. (1/0 Cycle)
Data Slab Ie From WR
IH
Any Hold Time for Selup Time
10Li'(MR)
10H (MR)
10Hi'(MR)
Iw(MRL)
Iw(MRH)
MREQ Delay From Falling Edge of Clock, MREQ Low
MREQ Delay From Rising Edge of Clock, MREQ High
0 _
0 7
JlrnJ
Symbol
Pulse Widlh, MREQ Low
Pulse Widlh, MREQ High
10RQ Delay
10RQ Delay
10RQ Delay
10RQ DeIlY
10L (RO)
10Li(RO)
10H (RO)
10Hi'(RO)
~
iW
WR
Mi
RFSH
JII
ISO
90
lS
SO
1'1
6
From
From
From
From
nstl.:
nsec
nsec
nsec
nsec
"sec
nsec
nsec
0
nsec
85
nstc
l!5
"sec
85
nstc
nsec
nsec
I~I
I~I
75
85
85
85
~Low
B!? Delay From Falling Edge of Clock.lID Low
nsec
nsec
nsec
85
nsec
9S
nsec
85
85
nsec
nsec
10L (WR)
10Li'(WR)
10Hi'(WR)
Iw{WRL)
~ Delay From Rising Edge of Clock, ~ Low
WR Delay From Falling Edge of Clock, WR Low
WR Delay Fr~ Falling Edge of Clock, WR High
Pulse Widlh, WR Low
65
80
80
nsec
nsec
nsec
nsec
10L(MI)
10H(MI)
Mi Delay From Rising Edge of Clock, Mi High
1101
MI Delay From Rising Edge of Clock, MI Low
100
100
~
Delay From Rising Edge of Clock. ~ Low
RFSH Delay From Rising Edge of Clock. RFSH High
nsec
nsec
130
120
nsec
300
nsec
n~c
WAIT
Is(WT)
WAIT SelUp Time 10 Falling Edge of Clock
HALT
10 (HT)
HALT Delay Time From Falling Edge of Clock
INT
IS (IT)
iNT Selup Time 10 Rising Edge of Clock
80
NMT
Iw(NML)
Pulse Widlh, NMI Low
80
nsec
BUSRQ
IS (BQ)
BUSRQ Selup Time 10 Rising Edge of Clock
SO
nstc
BiJSAK
10L(BA)
10H(BA)
BUSAK Delay From Rising Edge of Clock. BiJSAK Low
liiiSAK Delay From Falling Edge of Clock, BUSAK High
RESET
I,(RS)
RESET SelUp Time 10 Rising Edge of Clock
IF(C)
Delay 10 F10al (MREQ. IORQ, RD and WR)
Imr
"'I Siable Prior 10 IORQ (lnlerrupl Ack.)
CL '50pF
C = 50pf
L
70
r L•
(I)
laci' Ie -70
(3)
lea = 1w(L) + Ir - SO
(4)
Icaf = 1w(L) + Ir - 45
(5)
Idcm = Ic -170
(6)
tdci = tw(L) + tr - 170
(7)
tcdf = tw(L) + tr - 70
(8)
Iw (MRL)
(9)
Iw(MRH) = 1w(H) + If - 20
SOpF
CL ' SOpF
C = 50pF
L
CL = SOpF
CL
=50pF
CL =50pF
nsec
C =50pF
L
nsec
100
100
nsec
nstc
CL =50pF
nsec
60
80
IIII
nsec
nsec
NOTES:
A. Dala should be enabled onlo Ihe CPU data bus when RIi is aClive. During inlerrupl acknowledge dala
should be enabled when lIT and ~ are bOlh aclive.
B. All conlrol signals are inlernally synchronized, so Ihey may be 10lally asynchronous wilh respecI
10 Ihe dock.
C. The
signal must be aClive for a minimum of 3 clock cycles.
D. OUlPUI Delay vs. Loaded Capacilance
TA = 70°C
Vee = +5V t5%
Add IOnsec delay for each 50pf increase in load up to maximum of 200pf for data bus and 100pf for
address & control lines.
E. Although Sialic by design. lesling guaranlees 1w(H) of 200 "sec maximum
mrr
7-D4
lacm c tw(H) + If - 65
(2)
nsec
RO Delay From Rising Edge of Clock, RO High
Ro Deloy From Falling Edge of Clock, Ro High
10L(RF)
10H(RF)
(12) Ic = Iw(H) + tw(L) + Ir + t f
171
Rising Edge of Clock, 10RQ Low
Falling Edge of Clock, 10RQ Low
RiSing Edge of Clock, 10RQ High
Falling Edge of Clock, 10RQ High
Delay From Rising Edge of Clock,
r ..t Condition
nSte
nsec
nsec
nsec
nsec
nstc
nsec
IJJ
Iql
mtm Delay From FaUing Edge of Clock, MREO High
10L(lR)
10Li(IR)
IDH(IR)
10Hi'(IR)
iORO
.\()
110
90
Unit
~sec
Load eireuil for OUlPUI
C
Ie - 30
zao-cpu
A.C. Timing Diagram
cw
Timing measurements are made at the following
voltages, unless otherwise specified:
~
a:
oc.
"."
"0"
CLOCK
Vee -.6V
.4SV
OU1l'UT
.NPUT
FLOAT
2.0V
2.0V
f:.V
to.S V
.8 V
.8 V
a:
o
u
~
ui
w
~
g
A O-A15
(I)
(I)
~
all
w
Z
a:
o
en
(I)
IF (0)
o
~
~
c
~
@
_r--
7-05
ZSO-PIO
Absolute Maximum Ratings
·Comment
Stresses above those listed under --Absolute Maximum
Raling" may cause permanent damage to the device.
This is a stress rating only and runctional operation or
the device at these or any other condition above those
indicated in the operational sections or this specifica·
tion is not impl;ed. Exposure to absolute maximum
rating conditions for extended periods may arrect
device reliability.
Temperature Under Bias Specified operating range.
_05 0 C to + 1500 C
Storage Temperature
Voltage On Any Pin With
Respect To Ground
-0 ..1 V to +7 V
Power Dissipation
.6 W
Note:
Z80-PIO and Z80A-PIO
D.C. Characteristics
TA = 00 C to70° C. Vee = 5 V ± 5':;
UIlIeSS
All AC and DC characteristics remain the-same for
the military grade parts except Icc'
Icc = 130mA.
otherwise specified
Parameter
Min.
Max.
Unit
VILC
V IHC
Clock Input Low Voltage
-0 ..1
.45
V
Clock Input High Voltage
Vcc-.6
Vcc+.3
V
V IL
Illput Low Voltage
-0 ..1
O.X
VIII
Input High Voltage
2.0
Vl'l'
V
VOL
VOH
Output Low Voltage
0.4
V
10L = ~.O mA
V
1011 • -250 ~A
ICC
Power Supply Current
70
mA
III
Input Leakage Current
10
J.lA
VIN
ILOH
Tri·State Output Leakage Current in Float
10
J.lA
ILOL
Tri·State Output Leakage Current ill Float
-10
J.lA
VOUT =2.4 to Vec
VOUT = 0.4 V
ILD
Data Bus Leakage Current in Input Mode
±IO
J.lA
O';;V
10HD
Darlington Drive ('urrent
.l.X
mA
Symbol
Output High Voltage
2.4
-1.5
Test Condition
V
=0 to Vee
';;Vcc
IN
VOH - I.S V
REXT =JQO n
Port B Only
7-06
Z80-PIO
A.C. Characteristics
TA
=0 0 C to 700 C, Vcc =+5 V ± 5%, unless otherwise noted
SIGNAL
C
SYMBOL
PARAMETER
MIN
MAX
400
170
(I)
2000
2000
30
UNIT
COMMENTS
W
~
IX:
Ic
IW(HI
IW (
Clock: Capacitance
10
pF
Unme~sure~
(IN
COUT
Input
Ca~acitance
5
pF
Returned to Ground
10
pF
Symbol
O(lIput Capacitance
7-07
Pins
Z80A-PIO
A.C. Characteristics
TA = 0 0 C to 70 0 C; Vcc = +5 V ± 5%, unless otherwise noted
SIGNAL
SYMBOL
tc
IW(HI
IW(LI
tr,lf
CS,C£
ETC.
PARAMETER
Clock Period
Clock Pulse Width, Clock High
Clock Pulse Widlh, Clock Low
MIN
MAX
250
105
lOS
(1(
2000
2000
30
Clock Rise and Fall Times
Ih
Any Hold Time for Specified Set-Up Time
tS (CSI
Control Signal Set-Up Time to Rising
Edge
of
(~ O~ring
COMMENTS
UNIT
145
Read or Write Cycle
tOR (D)
tS (01
380
Dala Output Delay From Falling Edge of RD
101 (D)
MI Cycle
Data OUIPut Delay' from Falling Edge of iCiR'Q DU'ingINTA
Cycle
00.0 7
nsec
(2J
50
Data Set-Up Time to Rising Edge of (I' During Write or
CL' 50pF
(3J
250
110
tF (D)
Delay to Floating Bus (Output Buffer Disable Time)
lEI
ts (lEI)
lEI Sel·Up Time to Falling edge of lORa DuringlNTA Cycle
lEO
IDH (101
tDL (101
10M (10)
lEO Delay Time from Rising Edge of lEI
lEO Delay Time from Falling Edge of lEI
lEO Delay from Falling Edge of Mi (lnlerrupt Occurring Just
Prior 10 Mi I See Note A.
lORa
tS (lRI
i'O"RO Set-Up Time to Rising Edge of During Read or
140
160
130
190
[5J
(5J CL' 50pF
[5J
210
(51
115
Write Cycle.
Mi
Mi
tS (Mil
Mi
AD
tS (RDI
RD Set·Up Timeto Rising Edge of During R.ad or Ml
Cycle
115
ts (POI
tDS (POI
Port Data Set·Up Tim. to Ri.ing Edge of STROBE (Mode 1)
Port Data Ourput Delay from f.!linog Edge of ~
(Mode 21
Delay to Floating PorI O.ta Bus from Rising Edge of STROliE
(Mode 2)
Port Data Stable from Rising Edge of lORa During WR
Cycll (Mode 01
230
tWIST)
Pulse Width, STROBE
150
(4J
to (lTi
to (lTJI
i"N'T Delay time-from Rising Edge of STROBE
iNf Delay Time from Data Match During Mode 3 Operation
tDH (RY)
Ready Response Time
tDL (RYI
Ready Response Time from Rising Edge of STROBE
AO·A7·
BO·B7
tF (POI
tDI (POI
ASTB.
1i'ffi
iNT
ARDY,
BRDY
Set·Up Time to Rising Edge of During INTA or
Cycle See Note B
fro~
Rising Edge'of
90
IBO
(5(
lBO
440
3BO
j"Q"R'Q
tc.
410
t c+
360
nsec'
(5J
CL=50pF
(5J
NOTES:
A.
2.5 t c >(N.21 tDL (10). tOM (10). ts (lEI). TTL Buffer Delav, if any
B.
MT must be active
for a minimum of 2 clock periods to reset the PIO.
(lJ tc=tW('~HI.tW('~Ll.tr.tf
{2J
Increase tOR (0) by 10 nsec for each 50 pFincrease in loading up to 200 pFmax.
(3)
Increase tOI (O) by 10 nsec for each 50 pF increase in loading up to 200 pFmax.
(4J For Mode 2: tw (STI>ts (POI
IS) Increase these values by 2 nsec for each 10pF increase in loading up to 100 pFmax.
'7-08
ZBO-PIO
A.C. Timing Diagram
Timing measuremenU are made It the following voltlgeS, unless otherwise specified:
INPUT
FLqAT
~V
OUTPUT
Q
w
!ta:
"'"
Vee-.S
2.0V
2.0V
CLOCK
"0"
.
.45V
O.BV
O.BV
Parameter
Clock Capacitance
CIN
Input Capacitance
COUT
Output Capacitance
Max.
Unit
20
pF
Unmeasured Pins
5
pF
Returned to Ground
10
pF
7-D10
Test Condition
Z80-CTC
A.C. Characteristics
TA = 0° C to 70° C, Vee = +5 V ± 5%, unless otherwise noted
Signal
Symbol
Parameter
Min
Max
Unit
tc
tW(H)
Clock Period
400
[11
ns
Clock Pulse Width, Clock High
170
2000
ns
tW(l)
Clock Pulse Width, Clock low
170
2000
ns
tptf
Clock Rise and Fall Times
30
ns
o(J
tH
Any Hold Time for Specified Setup Time
~
tS(CS)
Control Signal Setup Time to Rising Edge of During Read
or Write Cycle
tDR(D)
Data Output Delay from Rising Edge of RD During Read
Cycle
1
tS(D)
Data Setup Time to Rising Edge of During Write or M1
Cycle
tDI(D)
Data Output Delay from Falling Edge of IORO During
INTA Cycle
w
Z
tF(D)
belay to Floating Bus (Output Buffer Disable Time)
o
m
tSOEI)
lEI Setup Time to Falling Edge of IORO During INTA
Cycle
cw
!ia:
oQ.
a:
en
w
CS, CE, etc.
!i
oo
(/)
(/)
ct
DO-D7
all
a:
lEI
(/)
o
:!:
ct
c
ct
@
lEG
'i'6'Ra
M1
RD
INT
Notes:
[1)
[2)
[3)
[4]
ns
160
ns
480
60
ns
340
ns
230
ns
200
(2)
ns
tDHOO)
lEO Delay Time from Rising Edge of lEI
220
ns
lEO Delay Time from Falling Edge of lEI
lEO Delay from Falling Edge of M1 Onterrupt Occurring
just Prior to. M1)
190
ns
300
ns
tSOR)
IORO Setup Time to Rising Edge of During Read or
Write Cycle
250
ns
tS(M1)
M1 Setup Time to Rising Edge of During INTA or M1
Cycle
210
ns
tSIRD)
RD Setup Time to Rising Edge of During Read or M1
Cycle
240
ns
tDCKOT)
tDOT)
INT Delay Time from Risihg Edge tJf ClK/TRG
2tcl
[2)
ns
tDlOO)
tDMOO)
[3)
[3]
[3)
Counter Mode
Timer Mode
tCICK)
Clock Period
tr,tf
tSICKI
tSITRI
Clock and Trigger Rise and Fall Times
Clock Setup Time to Rising Edge of for Immediate Count
Trigger Setup Time to Rising Edge of for Enabling of
Prescaler on Following RiSing Edge of
210
210
Counter Mode
Timer Mode
tWICTH)
Clock and Trigger High Pulse Width
200
Counter and
Timer Modes
tWICTll
Clock
200
Counter and
Timer Modes
tDHIZC)
ZC/TO Delay Time from Rising Ed~~ of <1>, ZC/TO High
190
tDlIZCI
ZC/TO Delay Time from Failing Edge of <1>: ZC/TO low
190
ClK/TRGO_3
ZC/ TO O_2
0
Comments
~nd
Counter Mode
2tcIl
,I
Trigger low Pulse Width
50
Counter and
Timer Modes
Counter and
Timer Modes
tc = twlH) + tW(ll + tr + tf.
Increase delay by 10 nsec for each 50 pF increase in loading, 200 pF maximum for data lines and 100 pF for control lines.
Increase delay by 2 nsec for each 10 pF increase in loading, 100 pF maximum
RESET must be active for a minimum of 3 clock cycles.
OUTPUT LOAD CIRCUIT
CR l - CR 4 lN9l4 OR EQUIVALENT
CL = 50 pF ON ALL PINS
:-. 7-011
Z80A-CTC
A.C. Characteristics
TA = 0° C to 70° C, Vee = +5 V ± 5%, u~less otherwise noted
Signal
Symbol
Min
Max
Unit
Clock Period
250
[1]
ns
Clock Pulse Width, Clock High
105
,2000
OS
twll)
Clock Pulse Width, Clock lo~
105
2000
tr;tf
Clock Rise and Fall Times
ns
ns
tSICS)
Control Signal Setup Time to Rising edge of During Read
or Write Cycle
tDR([»)
Data Output Delay from Falling Edge of RD During Read
Cycle
tSID)
Data Setup Time to Rising Edge of During Write or Ml
Cycle
tDlID)
Data Output Delay from Falling Edge bf IORG During
INTA Cycle
tFID)
Delay to Floating Bus IOutput Buffer Disable .Time)
tsIIEII
lEI Setup Time to Falling Edge of lORa During INTA
Cycle
00- 0 7
lEI
-'
tDH(lO)
tDl(lO)
lEO
30
Any Hold Time for Specifi~d Setup Ti:T,e',
tH
CS, CE,etc
Parameter
tc
tWIH)
tDM(lO)
0
ns
60
'ns
380
160
ns
110
ns
160
lEO Delay Time from Falling Edge of lEI
lEO Delay from Falling Edge of M1 (Interrupt Occurring
just Prior to M1 )
130
190
ns
ns
ns
iO'RQ
tsci>(lR)
lORa Setup Time to Rising Edge of During Read or
Write Cycle
115
ns
M1
tS(Ml)
Ml Setup Time to Rising Edge of During INTA or Ml
Cycle
90
ns
Ri5
tSIRD)
RD Setup Time to Rising Edge of During Re~d or Ml
Cycle
115
ns
iNf
tOCK(lT)
tD(lT)
INT DelayTime from Rising Edge of
tCICK)
Clock Period
trotf
tS(CK)
tS(TR)
Clock and Trigger Rise and Fall Times
ZC/TOO_2
Notes:
2tcl for Immediate Count
Trigger Setup Time to Rising Edge of for enabiing of
"Prescaler on Following Rising Edge of
Clock and Trigger High Pulse Width
tW(CTLI
Clock and Trigger low Pulse Width
tDHIZC)
'ZC/TO Delay Time'from Rising Edge of <1>, ZC/TO High
120
tDlIZC)
ZC/TO Delay Time from Rising Edge of <1>, ZC/TO low
120
CLK/TRGO_3
(2)
ns
"
lEO Delay Time from Rising Edge of lEI
INT Delay Time from Rising Edge of ClK/TRG
(2)
ns
50
140
ns
Comments
130
Counter Mode
Timer Mode
130'
120
Counter and
Timer Modes
120
Counter and
Timer Modes
Counter and
Timer Modes
Counter and
Timer Modes
[1] tc = twlH) + twlL1 + tr + tf.
•
'
, '
[2] Increase delay by 10 nsec for each 50 pF increase in loading, 200 pF maximum for data lines and 100 pF for control lines.
[3] Increase delay by 2 nsec for each 10 pF increase in loading, 100 'pF maxirnum.
[4] 'i"i'E'S"E'T must be active for a minimum of 3 clock cycles.
OUTPUT LOAD CIRCUIT
CR
2
CR 3
CR 4
CR 1 - CR 4 lN914 OR EOUIVALENT
"
CL = 50 pF ON ALL PINS
zaO-CTC
A.C. Timing Diagram
CLOCK
OUTPUT
Timing measurementS'are made at the following voltages, unless otherwise specified:
.SV
FLOAT
AV
±0.5V
...--t----tC(CK)I-+------i~1
eLKI
TRG0-3
(TIMER MODE)
ZC/TOO_2
7-013
.SV
2.0V
EIO
(COUNTER MODE)
"0"
.45V
INPUT
lEI
"'"
VCC - .6V
2.0V
Chapter 8
THE ZILOG Z8
This chapter will be provided at a later date as an update.
8-1
cw
Chapter 9
THE MOTOROLA MC6BOO
~
IX:
oa..
IX:
o
CJ
~
en
w
The MC6800 was developed by Motorola as an enhancement of the Intel 8008, at the same time that Intel was
developing the 8080A, also as an enhancement of the 8008.
g
When comparing the MC6800 to the 8080A, the most Important feature of the MC6800 is its relative
simplicity. Here are a few superficial, but illustrative comparisons between the two products:
~
VJ
VJ
ct
clJ
1)
w
Z
IX:
o
al
VJ
o
2)
:!:
ct
o
3)
ct
@
4)
5)
As compared to the 8080A. MC6800 timing is very simple. MC6800 instructions execute in two or more machine
cycles. all of which are identical in length. In contrast to the 8080A. which we described in Chapter 4. note that an
MC6800 machine cycle and clock period are one and the same thing - each MC6800 machine cycle has a single
clock period.
Whereas the 8080A has separate I/O instructions. the MC6800 includes memory and I/O within a single address
space. Thus all I/O devices are accessed as memory locations.
The MC6800 has a simpler set of control signals. therefore it does not mu Itiplex the Data Bus ~ and does not need
any device equivalent to the 8228 System Controller.
Whereas the 8080A requires three levels of power supply. the MC6800 uses just one - +5V.
The instruction set of the MC6800 is much easier to comprehend than that of the 8080A. The MC6800 has fewer
basic instruction types. with more memory addressing options: the 8080A. by way o(contrast. has a large number
of special. one-of-a-kind instructions.
It is very informative to extend the five comparisons above with the enhancements that Intel has made to the
8080A in order to come up with the 8085; Let us take the five pofnts one at a time.
1)
2)
3)
4)
5)
8085 instruction execution timing is far simpler than the 8080A. But MC6800 timing is still far simpler than the
8085.
The 8085 retains the separate memory and I/O spaces of the 8080A.
The 8085 has separate control signals which do not need to be demultiplexed off the Data Bus. as required by the
8080A. The price paid by the 8085 is a multiplexed Data and Address Bus. Neither the MC6800 nor the 8085 need
any device equivalent to the 8228 System Controller: however. the 8085 will need a bus demultiplexer in configurations that do not use the standard 8085 support devices.
The 8085. like the MC6800. has gone to a single +5V power supply.
The 8085 instruction set is almost identical to that of the 8080A.
An additional point worth noting is that the 8085 includes clock logic on the CPU chip. The MC6800 requires a separate clock logic chip.
Looking at the 8085, there are grounds for arguing that Intel has acknowledged that the MC6800 has some
desirable characteristics not present in the 8080A. In order to compete with the 8085, therefore, Motorola will
not be required to make MC6800 enhancements of the same magnitude as Intel made going from the 8080A to
the 8085. Specifically, these are the MC6800 characteristics which remain to be addressed by any MC6800
enhancement:
1)
2)
Clock logic must be moved on to the CPU chip.
Multifunction CPU and support devices must be developed so that Motorola can offer low chip count microcomputers.
Additional weaknesses of the MC6800 that have manifested themselves include:
1)
2)
An instruction set that makes excessive use of memory as a result of too few Index registers and a lack of data
mobility between registers of the CPU. This is a weakness that was identified in the first version of this book.
The synchronizing E signal. required by support devices of the MC6800. render these support devices useless in
any microcomputer system other than the MC6800. In contrast. 8080A support devices can be used widely in
microcomputer systems not based on the 8080A CPU.
9-1
Future Motorola plans address many of the points raised above. The MC6802. described in this chapter. is the first step
towards reducing chip counts in MC6800-based microcomputer systems. The MC6809 will be the new enhanced
MC6800. to compete with the 8085. The MC6809 will provide additional Index registers. plus instructions that move
data between Accumulators and Index registers. The MC6809 will have clock logic on the CPU chip.
MC6800 and MCS6500 support devices are interchangeable: that is to say. you can use MC6800 support devices (described in this chapter) with the MCS6500 microprocessor (described in Chapter 10) and you can use MCS6500 support devices (described in Chapter 10) with the MC6800 CPU.
Although MC6800 and MCS6500 support devices are interchangeable. they should not be used with other
microprocessors. with the exception of parts described in Volume 3.
These are the devices described in this chapter:
• The
• The
• The
• The
• The
• The
• The
• The
• The
• The
MC6800 CPU
MC6802 CPU with RAM
MC6870 series Clocks
MC6820 Peripheral Interface Adapter (PIA)
MC6850 Asynchronous Communications Interface Adapter (ACIA)
XC6852 Synchronous Serial Data Adapter (SSDA)
MC6828 Priority Interrupt Controller (PIC)
MC6840 Programmable CounterlTimer
MC6844 Direct Memory Access Controller
MC6846 Multifunction device - the second part in an MC6802-based two-chip microcomputer.
Devices described in Volume 3 include the MC6845 CRT controller, the MC6843 Floppy Disk controller and the
MC68488 General Purpose Interface Adapter.
Two new series of MC6800 parts offer higher speeds. Standard MC6800 parts use a 1 MHz
clock signal. "A" parts use a 1.5 MHz clock signal. while "B" parts use a 2 MHz clock signal. There
is. in addition. an MC6821 PIA which is identical to the MC6820 in operating characteristics. but
has different physical characteristics.
MOTOROLA
AAND B
SERIES PARTS
The principal MC6800 manufacturer is:
MOTOROLA INCORPORATED
Semiconductor Products Division
3501 Ed Bluestein Boulevard
Austin. TX 78721
The second sources are:
AMERICAN MICROSYSTEMS
3800 Homestead Road
Santa Clara. California 95051
FAIRCHILD SEMICONDUCTOR
464 Ellis Street
Mountain View. California 94040
HITACHI
Semiconductors And Integrated
Circuits Division of Hitachi LTD
1450 Josuihan-Cho-Kodaira-Shi
Tokyo. Japan
SESCOSEM
Thompson CSF
173 Haussmann Blvd.
Paris. France 75008
The MC6800 devices use a single +5V power supply. Using a one microsecond clock, instruction execution
times range from 2 to 12 microseconds. A one microsecond clock is the standard for MC6800 microcomputer
systems. 667 nanosecond clocks are standard for the 68AOO series while 500 nanosecond clocks are standard
for the 68BOO series.
All MC6800 devices have TTL compatible signals.
N-channel silicon gate, depletion load MOS technology is used for the MC6800.
9-2
THE MC6800 CPU
c
w
Functions implemented on the MC6800 CPU are illustrated in Figure 9-1; they represent typical CPU logic. As
compared to other microprocessors described in this book. the MC6800 might be considered deficient in requiring external clock logic; however. its principal competitor. the 8080A. requires external clock logic and Data 8us
demultiplexing logic.
~
oa..
The need for external clock logic simply reflects the fact that the MC6800 is one of the earlier microprocessors.
o
(J
The MC6800 has two Accumulators, a Status register, an Index register, a Stack Pointer and a Program
Counter. These may be illustrated as follows:
a:
a:
~
THE MC6S00 PROGRAMMABLE REGISTERS
enw
Accumulator A
8 bits
~
oCI)
U
Accumulator B
8 bits
CI)
Index Register X
16 bits
ct
ci/:I
w
Z
16 bits
Program Counter PC
o
16 bits
Stack Pointer SP
a:
IX!
CI)
Status Register
8 bits
o
~
ct
C
ct
@
The two Accumulators, A and 8, are both primary Accumulators. The only instructions which apply to one Accumulator. but not the other. are the instructions which move statuses between Accumulator A and the Status register
and the DAA (Decimal Adjust) instruction. /,i,.:
/" ~ ". I~.
.
The Index register is a typical microcomputer Index register, as described in Volume 1.
The MC6800 has a Stack implemented in;memory and indexed by the Stack Pointer, as described in Volume 1.
8ecause 'of the nature of the MC6800 instrucUon set. it is more realistic to look upon the MC6800 Stack Pointer as a
cross between a Stack Pointer and a Data Counter. Memory reference instructions make it very easy to store the contents of either the Stack Pointer or the Index r~gister in read/write memory; by maintaining a number of base page
memory locations as storage for these two Address registers. each can be put to multiple use.
The Program Counter is a typical
Pr()~ram
Counter, as described in Volume 1.
MC6S00 MEMORY ADDRESSING MODES
MC6800 memory reference instructions use direct
,.
. addressing and indexed addressing.
The MC6800 has an unusually large variety of three-byte memory referencing inst~uctions; a 16-bit direct address is provided by the second and third bytes of the instruction. Therefore, 65,536 bytes of memory can be
directly addressed. The commonly used memory reference instructions also have a base page, direct addressing
option; tHis is a two-byte instruction, with a one~byte address which can directly address anyone of the first
256 bytes ,:>f memory.
,.
All memory reference instructions are available with indexed addressing. Indexed addressing on the MC6800
differs from indexed addressing as described in Voiume 1. in that the one-byte displacement provided by the memory
reference instruction is added to the Index register as an unsigned 8-bit value:
Byte 1
Byte 2
....._ _
o_p_c_o_de_,_ _......_ _ _x_x_ _ _.....llnstruction
________
p_pq_q_ _ _ _ _ _---'llndex Register
Effective Address = ppqq + OOxx
P. q. and x represent any hexadecimal digits
MC6800 programs can use the Stack Pointer as an Address register. but two bytes of read/write memory must be
reserved for the current top of Stack address and interrupts mustoe disabled while the Stack Pointer is being used to
address data memory. A single instruction allows an address to be ioaded into the Stack Pointer; another single instruction allows the Stack Pointer contents to be stored in read/write memory. In most programs. the Stack is unused for
much of the time; therefore. given the low MC6800 overhead involved with swapping addresses between the Stack
Pointer and read/write memory. making dual use of the Stack Pointer is advisable.
9-3
I.
Clock Logic
..
i
Logic to Handle
Interrupt Requests
from
External Devices
)
......
(
.........
.......
Ii
'•..
:c:;~>
...................
.....
Ip~tr~stl?~flegl~!~~ r-
[J
:iii<
:
........
. ...
••••••
, .............. /..........
.
{
c··· •
.c:.
......
I·'· .......,.....
.......
.......
......
.....
C
..
........
.......
.
Ii>i
.
.·.·i . .
)
· · ·.· . t:
'"
t
..........
i·.·..··//
I .......
....
.....>
I
••••••
~
~
'
••or
~ ..
al
"lJ lltl
>
,
System Bus
t
j
I/O Communication
Serial to Para"el
Interface Logic
Programmable
Timers
ROM Addressing
and
Interface Logic
~
1\
...
......
;~
...
..
....
.......
(
...
....,
...
.......
i
.>
...
'.{
>""'.
...
···i
Interrupt Priority
Arbitration
i
......
.......
......
~
.....
i
:C • j<':'
L
I/O Ports
Interface Logic
Read Only
Memory
,
Direct Memory
Access Control
Logic
t
t
~
1
RAM Addressing
and
Interface Logic
t
1
I/O Ports
Read/Write
Memory
~
~
,t
Figure 9-1. Logic of the MC6800 CPU Device
Branch and Branch-on-Condition instructions use program relative, direct addressing; a single byte displacement
is treated as a signed binary number which is added to the Program Counter, after Program Counter contents have
been incremented to address the next sequential instruction. This allows displacements in the range + 129 to -126
bytes.
One note of caution: Motorola's MC6800 literature uses the term "implied addressing" to describe instructions that
identify one of the programmable registers. The closest thing the MC6800 has to implied addressing, as the term
is used in this book, is indexed addressing with a zero displacement.
9-4
~
HALT
2 clock input. in which case <1>2 and DBE are identical signals.
HALT. When this signal is input low. the CPU ceases execution at the end of the present instruction execution and
floats the entire System Bus.
Bus Available (BA). This line is output high when the Data and Address Busses have been floated following a HALT input only. When BA is low, the CPU is controlling the Data and Address Busses; information on these busses is
identified by the following two control signals:
Read/Write (R/W). Whl3n high. this signal indicates that the CPU wishes to read data off the Data Bus; when low. this
signal indicates that the CPU is outputting data on the Data Bus. The normal standby state for this Signal is "read"
(high).
Valid Memory Address (VMA). This Signal is output high whenever a valid address has been output on the Address
Bus.
THere are three interrUpt processing signals as follows:
IRQ. This signal is used to request an interrupt. If interrupts have been enabled and the CPU is not in the Halt state.
then it will ~cknowledge the interrupt at the end of the currently executing instruction.
Non-Maskable Interrupt (NMJ). This signal differs from IRO in that it cannot be inhibited. Typically. this input is used
for catastrophic iriterrupts such as power fail.
iiES"E'T. Thi?
is a typical reset signal.
Note that a number of control signals output by the MC6800 are only capable of driving one standard TTL load. Some
form of signal buffering and amplification will therefore b.e required in most systems.
9-6
MC6800 TIMING AND INSTRUCTION EXECUTION
MC6S00
CLOCK
SIGNALS
The MC6S00 uses a relatively simple combination of two clock signals to time events within
the microprocessor CPU and the microcomputer system in general. These two clock signals may
be illustrated as follows:
Q
w
~
a:
oa.
<1>1
____I
\...._ _ _"..,1
\
a:
o
(J
~
~
C3
o
en
en
c:(
01:1
w
Z
a:
o
I
\
(1)2
en
w
I
\
Observe that clock signals <111 and <112 both have high pulses which occur within the width of the
other clock signal's low pulse.
A further timing signal, given the symbol E, is used by support devices within an MC6S00 microcomputer
system. <111, <112 and E timing signals are generated by the clock logic devices described later in this chapter.
Each repeating pattern of <111 and <112 signals constitutes a single machine cycle:
to
en
o
~
~ One Machine
c:(
Q
c:(
Cycle
@
I
1
<1>1
<1>2
\
,
\
-I ...
One, Machine
Cycle
I
I'
I
\1I
I
--..f
MG6S00
MACHINE
CYCLE
I
~I
\
\
I
I
\:
I
I
I
MC6800 instructions require between two and eight machine cycles to execute. Interrupt instructions are an exception. requiring longer instruction execution times.
'
So far as external logic is concerned, there are only three types of machine cycles which can
occur during an instruction's execution:
1)
2)
3)
A read operation during which a byte of data must be input to the CPU.
A write operation during which a byte of data is output by the CPU.
An internal operation during which no activity occurs on the System Bus.
MC6S00
MACHINE
CYCLE
TYPES
All MC6S00 instructions have timing which is a simple concatenation of the three basic machine cycle types ..
Let us therefore begin by ,looking at these three basic machine cycles.
Figure 9-3 illustrates timing for a standard read machine cycle. Observe that in the normal
course of events. neither the Address nor the Data Busses are available for DMA operations. The
address output is stable for most of the machine cycle. Data needs to be stable for a short interval
of time late in the machine cycle. Exact timing is given in MC6800 data sheets at the end of this
chapter.
9-7
MC6S00
READ
MACHINE
CYCLE
<1>1
<1>2
R/iii
VMA
, AO - A15
Address Out
DO-D7 ________________________________~
In _.1
'--_Data
__
Figure 9-3. A Standard MC6800 Read Machine Cycle
Figure 9-4 illustrates a standard MC6800 write machine cycle. This machine cycle is not as
straightforward as the read. The address to which data is being written is stable on the Address
Bus for the duration of the machine cycles; however. the data being written is stable for a period
within the high DBE pulse. While DBE is low.. the Data Bus is floated.
<1>1
<1>2
R/W
VMA
~________________________~J
AO-A16------~----~
DBE
DO - D7
Data Out
Data Bus
floated
Figure 9-4. A Standard MC6800 Write Machine Cycle
9-8
MC6800
WRITE
MACHINE
CYCLE
Under normal circumstances, DBE is identical to <1>2:
~
2
37
DBE
Q
36
w
~
a:
oC1.
a:
o
2 pulse is too short for external logic to respond to the write. the slow external
logic can be accommodated in two ways. You can input a DBE signal to the CPU that has a
shorter low pulse and a longer high pulse. DBE and <1>2 are no longer identical signals:
C/)
C/)
MC6800 WAIT
STATE WITH
SLOW
MEMORY
c(
all
w
Z
a:
oCD
1
and <1>2 cannot be held constant for more than 9.5 Ilsec; the MC6800 is a dynamic device. and longer static clock
periods can result in loss of internal data.
During an internal operation's machine cycle, there is no activity on the System Bus. R/W is
in its normal high state and VMA is low.
Table 9-2 defines the way in which individual MC6800 instructions concatenate machine
cycles and use the System Bus during the course of instruction execution.
MC6800
INTERNAL
OPERATIONS
MACHINE
CYCLE
The VMA and DBE signals require special mention, because their significance can easily be
missed. External logic uses VMA as a signal identifying the address on the Address Bus as having
been placed there by the CPU. DBE similarly identifies that portion of a machine cycle when the CPU is active at one
end of the Data Bus. either transmitting or receiving data. And this is why these signals are so important: MC6800
microcomputer systems rely heavily on clock signal manipulation as a means of accommodating slow memories. implementing Direct Memory Access. or refreshing dynamic memory. On the next few pages we are going to see examples
of how this is done. So long as you understand that the VMA and DBE signals identify the unmanipulated portions of a
standard machine cycle. you will have no trouble'locating the time slices within which special operations such as
Direct Memory Access or dynamic memory refresh are occurring.
.
9-9
THE HOLD STATE, THE HALT STATE AND DIRECT MEMORY ACCESS
The H~ld state typically describes a CPU condition during which System Busses are floated, so that external
logic can perform Dire.ct Memory Access operations.
ThoughtheMC6Sd6 iiterature does not talk about a Hold state, this microprocessor does indeed have two
equivalent conditions.
You can fioatthe Address and Data Busses separately, using the TSC and DBE signals.
You can enter an MC6S00 Halt state, which is equivalent to our definition of a Hold state.
Let us begin by looking at the use of TSC and DBE signals.
The Three State Control signal (TSCl. if input high, will float the Address Bus and R/W line. VMA and BA are forced
low. The .unusual feature of the Three State .Control input is that when this signal is input high. you must
si'multaneously stop the clock by holding <1>1 high and <1>2 low. Timing is illustrated in Figure 9-5. Now the MC6800.
being dynamic device. will lose its data contents if the clock is stopped for more than 9.5 jl.sec. You must therefore
float the Address Bus just long enough to perform a single Direct Memory Access.
a
<1>1
<1>2
TSC
AO - A15
Addre,ss Bus.
A/Wand VMA
floated
Figure 9-5. TSC Floating the Address Bus
Just as the Three State Control input floats the Address Bus. so the Data Bus Enable input (DBE) floats the Data Bus.
When DBE is input low. the Data Bus is floated.
The clock devices. which are described later in this chapter. provide all necessary clock stretching logic.
There are two very important points to note regarding the use of Three State Control (TSC) and Data Bus Enable (DBE)
signals.
.
First of all. note carefully that the Bus Available (BA) Signal is held low when the busses are floated by the Three State
Control (TSC) and Data Bus Enable (DBE) signals. The purpose of the Bus Available signal is to indicate that the System
Bus is available during a Halt or Wait state. both of which we have yet to describe.
The second important feature of the Three State Control (TSC) and Data Bus Enable (DBE) signals is that they do indeed
float the System Bus in two halves. Now in many MC6800 systems <1>2 and DBE are the same signal: in such a configuration you will automatically float the Data Bus whenever you float the Address Bus. as illustrated in Figure 9-6.
Now consider the MC6S00 Halt state.
The Halt state of the MC6S00 is equivalent to the Hold state of the SOSOA. If a low HALT is input to the MC6800.
then upon conclusion of the current instruction's execution. the System Bus is floated. Timing is illustrated in Figure
9-7. Observe that the Bus Available Signal. BA. is output high: VMA is output low. The Address and Data Busses. and
the R/W control are floated.
In summary, the MC6S00 provides two means of performing Direct Memory Access operations. You can.use
the TSC and DBE inputs to gain control of the System Bus for as long as it takes to perform a single DMA access,or you can use the HALT input, following which external logic can gain control of the System Bus for as
long as you wish.
9-10
Ill1
Q
!l>2
w
l-
e(
a:
0
TSC
Q.
a:
0
u
~
enw
AO - A15
l-
e(
Address Bus.
g
R/W and VMA
(I)
(I)
floated
e(
!Ill
w
Z
a:
DBE,·!l>2
0
CD
(I)
0
~
DO - D7
e(
Q
e(
Data Bus
floated
@
Figure 9-6. TSC Floating the Address and Data Busses When DBE Is Tied to <1>2
Conceptually, the MC6800 scheme for implementing Direct Memory Access or dynamic memory refresh. is very
elegant. If you stretch the <1>1 and <1>2 clock signals, then you can transfer the normal CPU generated address,
and an extraneous address within one machine cycle. VMA identifies the CPU generated address. Within the
one machine cycle can perform two Data Bus transfers; the first is in response to the external address, while
the second is in response to the CPU address. Now DBE identifies the CPU response. This scheme may be illustr-
\
,
I
\
ated as follows:
I
!l>1 (Stretched)
!l>2 (Stretchedi. ,
AO - A 15
~
)
DMA Address
Normal Address
I
VMA
00- 07
(
( DMA Data·
\
1
( Normal Data
I
DBE\
)
.)
\
From this conceptually elegant beginning, some very complex design considerations can arise. Complexities
disappear, however, when standard 6800 support devices are used to implement direct memory access logic.
Specifically, you should use the Me6875 clock device in conjunction with the 6844 Direct Memory Access
controller.
9-11
Last
machine
cycle of
instruction
Next
I
instruction
fetch
execution :
Halt state during
which System Bus
is floated
Figure 9-7. System Bus Floating During the Halt State
INTERRUPT PROCESSING, RESET AND THE WAIT STATE
MC6800 microcomputer system interrupt logic. as implemented within the 6800 CPU. is based on polling
rather than vectoring. The MC6828 Priority Interrupt Control device. described later in this chapter. extends
CPU interrupt logic to provide vectored interrupt response. All normal interrupt requests. when acknowledged.
result in an indirect addressing Call to a single high memory address. If more than one device can request an interrupt.
then the basic assumption made is that the interrupt service routine will initially read the Status register contents of every device that might be requesting an interrupt and by testing appropriate status bits. the interrupt service routine
will determine which interrupt requests are active. If more than one interrupt request is active. interrupt service routine
logic must decide the .order in which interrupt requests will be acknowledged.
But be warned: this type of polling quickly becomes untenable as a means of controlling microcomputer systems
with multiple random interrupts. If you have more than two or three competing external interrupts. the time taken to
read Status register contents and arbitrate priority will become excessive. If your application demands numerous external interrupts. then you must resort to external hardware which implements interrupt vectoring. We will describe ways
in which this can be done.
If you casually look at a description of MC6800 interrupt logic. you may at first believe that some level of interrupt vectoring is provided. In reality. that is not the case.
9-12 '
The MC6800 sets aside the eight highest addressable memory locations for interrupt processing purposes. Four
16-bit addresses are stored in these eight memory locations, identifying the interrupt service routine's starting
address for the four possible sources of interrupt. This is how the eight memory locations are used:
cw
~
a:
o
FFFS
FFFA
FFFC
FFFE
and
and
and
and
FFF9
FFFB
FFFD
FFFF
Normal external interrupt
Software interrupt
Non-maskable interrupt
Reset (or restart)
0-
The lower address (FFFS. FFFA. FFFC. FFFE) holds the high order byte of the starting address.
~
In the event of simultaneous interrupt requests. this is the priority sequence during the
acknowledge process:
a:
o
o
u)
w
Highest
~
g
C/)
C/)
ct
a!I
w
Z
a:
o
III
Lowest
(1)
(2)
(3)
(4)
MC6800
INTERRUPT
PRIORITIES
Restart
Non-maskable interrupt
Software interrupt
Normal external interrupt
Only the lowest priority interrupt is normally used by the typical support device that is capable of requesting interrupt
service. The three higher priority interrupt levels represent special conditions and cannot be accessed by the standard
. external interrupt request.
We will begin our discussion of MC6800 interrupt processing by describing the four interrupts.
C/)
o
~
ct
c
ct
@
The normal external interrupt request is the standard interrupt present on all
microprocessors that support interrupts; it is equivalent to the SOSOA INT input. In very simple
systems. the addresses FFFS16' and FFF916 may indeed access real memory locations: in the
multiple interrupt MC6S00 microcomputer systems. FFF916 is more likely to select an S-bit buffer
within which an address vector is stored identifying the interrupting source. This is essentially
how the MC6S2S Priority Interrupt Controller (PIC) works.
MC6800
NORMAL
EXTERNAL
INTERRUPTS
A software interrupt is initiated by the execution of the SWI instruction. What theSWI instruction does is cause the MC6S00 to go through the complete logic of an interrupt request and
acknowledge. even though the interrupting source is within the CPU. Software interrupts are
typically used as a response to fatal errors occurring within program logic. Whenever your program logic encounters a situation that must not. or should not exist. the error condition is trapped
by executing an SWI instruction: this causes a call to some general purpose. error recovery program.
The non-maskable interrupt cannot be disabled. Otherwise it is identical to the normal external interrupt request. Note that the SOSOA has no non-maskable interrupt: however. the
Zilog ZSO and the SOS5 have incorporated this feature.
MC6800
SOFTWARE
INTERRUPT
MC6800
SWI
INSTRUCTION
MC6800
NON-MASKABLE
INTERRUPT
A Reset is treated as the highest priority interrupt in an MC6S00. How does the Reset differ from
the non-maskable interrupt? Conceptually. the non-maskable interrupt is going to be triggered by
a termination condition such as power failure. while the Reset is going to be triggered by an initiating condition such as power being turned on.
There are. some differences between the MC6800's response to a Reset as compared to any other interrupt request~
.
To contrast the two. we will look at the normal interrupt acknowledge sequence. and then we will look at a reset. Figure
9-S illustrates MC6800 response to a normal external interrupt, a software interrupt, or a non-maskable interrupt.ln each case. the interrupt request will be acknowledged upon completion of an instruction's execution. A normal
external interrupt will only be acknowledged providing interrupts have been enabled.
If more than one interrupt request exists. then the highest priority interrupt will be acknowledged.
Following the interrupt acknowledge. normal interrupts are disabled by the CPU. which then pushes onto the Stack the
contents of all internal registers. This process is illustrain Figure 9-S. The Program Counter is then loaded with the appropriate interrupt service routine starting address. which will be fetched from memory locations FFFS16 and FFF916.
FFFA16 and FFFB16 or FFFC16 and FFFD16.
9-13
----------------il
L
,
This is the
last,m8chi~e cycle for executio~ of the instruction during which
the interrupt was requested.
. .
.
__________~ ;.~;~~st~~~;~U:~~~;~;~:~~: ~~t:;~~:~~~;:~~~s;:~~:~~~~i~~~::UCC;~~
IC;~~I #21
pleted execution.
#4
#3
#5
#6
#7
'.
#8
#9
#10
,I'
#11
.
..
1
#12
1
#13
1
#14
1 #15
Address ......,....----......- -...... ' - - ' r BUI
IRQ or
NMi
Interrupt
Muk
------------------------------+----~
Data Bul ___J~_ _~_ _ _~_
_n_ _ __A_ _J~_ _~_ _ _~_ _J~_ _~~-~-----A-~~
__ __
~
_N
VMA
Figure 9-S. MC6S00 Interrupt Acknowledge Sequence
Referring to Figure 9-S. note thatan interrupt is acknowledged following the last machine cycle for the instruction during which the interrupt request occurred. During the first two machine cycles following the interrupt acknowledge. an
instru'ction fetch is executed. as it would have been had the interrupt not occurred. This instruction fetch is aborted
and will reoccur after the interrupt service routine has completed execution. Two machine cycles are expended performing this aborted instruction fetch.
Following the aborted instruction fetch. CPU registers' contents are pushed onto the Stack in the following order:,
• Lower half of ProgramCounter
• Upper half of Program Counter
• Lower half of Index register
• Upper half of Index register
• Accumulator A
• Accumulator B
• Status register
When the SOSOA acknowledges an interrupt. if CPU registers' contents are going to be saved on the Stack. you must
execute individual instructions 'to perform the operations which the MC6S00 performs automatically. The advantage of
the MC6S00's scheme is that it saves instruction execution time. The disadvantage of this scheme is that there are o"ccas ions when you do not need to bother saving registers' contents.
After all CPU registers' contents have been saved on the Stcick. the next two machine cycles are used to fetch an address from the appropriate two high memory bytes. This address is loaded into theProgram Counter. causing a branch
to the appropriate interrupt service routine.
'
'9-14
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+
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+
11m ~ 21m
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((
~
~
w
Z
a:
~ "" IndeterminatB
o
al
en
o
Figure 9-9. The Reset Sequence
~
~
c
~
@
We will now examine the MC6800 Reset operation.
The MC6800
RESET
illustrates Reset timing. First of all. note that RESET must be held low for at least
Figure
OPERATION
eight machine cycles to give the CPU sufficient response time. On thehigh-to-Iow transition of
RESET the CPU outputs VMA and SA low and R/W is high. On the subsequent low-to-high transition of RESET. maskable interrupts are disabled. then the contents of memory locations FFFE16 and FFFF16 are fetched
and loaded into the Program Counter. If RESET is not held low for a minimum of eight machine cycles. then when
RESET is input high again. indeterminate program execution may follow.
9-9
It is absolutely vital that the
RESET.
iiESET rise
time is less than 100 nanoseconds on the low-to-high transition of
We stated that the difference between a Reset and a non-maskable interrupt is that the Reset represents initiation conditions. This is illustrated in Figure 9-9. which includes the power supply level. When power is first turned on. the
MC6S00 will automatically trigger a Reset when power increases above +4.75 volts: this is in response to the normal
powering up sequence. The fact that Reset represents initiation conditions also explains why no CPU registers' contents are saved. as occurs with any other interrupt. Clearly. if we are initiating operations. there can be no prior
registers' contents to be saved. Therefore pushing registers' contents on the Stack would be pointless an'd impossible: it would be pointless because there is nothing to save: it would be impossible because when powering up. we
.
have no idea what the Stack Pointer contains.
Powering up an MC6800 microcomputer system represents a special Reset case. Those
MC6S00 microcomputer system devices that have an external Reset input control. expect this
control to be· '1eld low while power is being turned on for the first eight clock cycles following
power-up. When designing Reset logic be sure to keep this in mind.
MC6800
RESET
bURING
POWER UP
MC6S00 configurations using SOSOA s~pport devices are easy to design and commonly seen.
Necessary system bus logic is described later in this chapter. But if you have such a mixed configuration. be sure to
satisfy the separate and distinct Reset requirements of the MC6S00 CPU as against the SOSOA support devices.
9-15
Cycle
#1
I
#2
I
~
1
~4
1
#5
I
#6
I
#7
1
#8
1 #91
1
1
#10
n"
1
n+2
1
n+3
1
n+4
I
n+5
I
cP2
Address --.,-""""'\.
Bus
roo---. ,-"""""'\.,----. ,----..,--"""1
R/W
VMA
Interrupt
------------------------if-tff-----;.-----'
Mask
IRQ 0'
NMI
Data Bus
-------:..--------------------4..
~r~---~--------4_~
==)C=:::x=:::x==>C=::::x==)C=:)(::::=x:=J::::}-~~f------.:.1C=::::x==x:::=:J(~=)4
BA· _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _LJ
System
Bus
Floated
Figure 9-10. MC6S00 Wait Instruction Execution Sequence
We complete our discussion of the MC6800 interrupt logic with a discussion of the WAI
instruction, which puts the MC6800 into a "Wait-for-interrupt" state.
MC6800
WAIT STATE
A WAI instruction is executed when the CPU has nothing to do except wait for an interrupt. Rather than pushing registers' contents onto the Stack following the interrupt
acknowledge. as illustrated in Figure 9-S. the WAI instruction pushes registers' contents onto
the Stack while waiting for the interrupt. as illustrated in Figure 9-10. Thus some execution
time is saved.
MC6800
WAI
INSTRUCTION
Once all registers' contents have been pushed onto the Stack. the MC6S00 floats the System Bus in the Wait state.
This gives rise to another frequent use of the WAI instruction: block data transfers under DMA control.
Consider again the sequence of events which follows the WAI instruction execution:
1)
All registers' contents are pushed onto the Stack.
2) The System Bus is floated.
MC6800
USE OF
WAIT FOR
DMA
This is very convenient if you are going to transfer a large block of data via DMA. because you will announce the end of
the DMA transfer with· an interrupt request. This method of handling block DMA transfers has been discussed in
Volume I. Now when using an MC6S00 microcomputer system. all you need to do is initiate the actual DMA transfer by
executing a WAI instruction; knowing that once the DMA transfer has been completed. an interrupt will be requested
and program execution can continue.
THE MC6800 INSTRUCTION SET
. Table 9-1 summarizes the MC6800 instruction set; this instruction set is characterized by a heavy use of read/write
memory and a rich variety of instructions that are able to manipulate the contents of memory locations as though they
were programmable registers. Whereas the primary memory reference instructions offer base page direct addressing .
. extended direct addressing or indexed addressing. secondary memory reference instructions offer extended direct addressing and indexed addressing only. This simply means that secondary memory reference instructions use three-byte
direct addressing even when a base page byte must be accessed.
9-16
Of the microcomputers described in this chapter, the MC6S00 has one of the largest varieties of Branch-onCondition instructions. Note that these and the unconditional Branch instructions are the only MC6800 instructions
which use program relative direct addressing.
Q
w
~
II:
oQ.
II:
o
CJ
~
en
w
~
g
(I)
(I)
~
all
w
Z
II:
o
III
(I)
o
~
~
Q
~
When comparing the MC6S00 and SOSOA instruction sets, the conclusion we must draw is that the MC6800 is
going to have to rely on a large number of memory reference instructions. You are going to have to set up programs
with this in mind. As a result. relatively simple programs will make the MC6800 look better than the 8080A. because
the MC6800 has such a diverse variety of memory reference instructions. The moment a program starts to become
complicated. the large number of 8080A registers is quickly going to become an advantage. since the MC6800 will be
forced to execute memory reference instructions where the 8080A can use register-register instructions.
The SWI and WAI instructions within the interrupt instruction group are relatively unusual within microcomputer systems.
The SWI instruction initiates a normal interrupt sequence. taking the interrupt service routine's starting address from
memory locations FFFA16 and FFFB16.
The WAI instruction prepares for an interrupt by saving the contents of all registers and status on the Stack: the
System Bus is then floated while the CPU waits for an interrupt request to occur.
We have described both the SWI and WAI instructions in some detail earlier In this chapter.
The one set of instructions which are missing. and which would greatly enhance the MC6800 instruction set. are instructions that move data between the Accumulator and the Index register. or allow Accumulator contents to be added
to the Index register.
THE BENCHMARK PROGRAM
The benchmark program is coded for the MC6S00 as follows:
@
LOOP
STS
LDX
LDX
LDS
PULL
STAA
INX
DEC
BNE
STX
LDS
SSP
#T ABLE
O.X
#IOBUF
A
O.X
10CNT
LOOP
TABLE
SSP
SAVE STACK POINTER CONTENTS IN MEMORY
LOAD TABLE BASE ADDRESS INTO INDEX REGISTER
LOAD ADDRESS OF FIRST FREE TABLE BYTE
LOAD I/O BUFFER STARTING ADDRESS
LOAD NEXT BYTE INTO A
STORE IN NEXT FREE TABLE BYTE
INCREMENT INDEX REGISTER
DECREMENT I/O BYTE COUNT IN MEMORY
RETURN FOR MORE BYTES
STORE NEW ADDRESS FOR FIRST FREE TABLE BYTE
RELOAD ~TACK POINTER
The memory initialization for the MC6800 interpretation of the benchmark program is identical to the memory initialization for the 8080A benchmark program. The MC6800 assumes that there is some memory location in which the current
real Stack address can be stored. so that the Stack Pointer may be used as a Data Counter.
In Table 9-1. symbols are used as follows:
ACX
Either Accumulator A or Accumulator B
The registers:
A.B Accumulator
X Index register
PC Program Counter
Stack Pointer
SP
SR Status register
Statuses shown:
C
Carry status
Z
Zero status
S
Sign status
o Overflow status
I
Interrupt status
AC Auxiliary Carry status
Symbols in the STATUSES column:
(blank) operation does not affect status
X
operation affects status
o
flag is cleared by the operation
flag is set by the operation
1
9-17
ADRS
ADR16
B2
B3
DATA
DATA16
DISP
xx(HI)
xx(LO)
[ ]
[[ ]]
[ MEM]
An S-bit (l-byte) quantity which may be used to directly address the first 256 locations in memory. or may
be ah,S-bit unsigned displacement to be added to the Index register.
A 16-bit memory address
Instruction Byte 2
I nstruction Byte 3
An S-bit binary data unit
A 16-bit binary data unit
An S-bit signed binary address displacement
The high order S bits of the 16-bit quantity xx; for example. SP(HI) mean~ bits 15 - S of the Stack Pointer.
The low order S bits of the 16-bit quantity xx; for example. PC(LO) means bits 7 - 0 of the Program Counter.
Contents of location enclosed within brackets.
Implied memory addressing; the contents of the memory location designated by the contents of a register.
Symbol for memory location indicated by base page direct. extended direct. or indexed addressing.
That is:
[MEM] = [ADRS]
or
[ ADR16]
or
[[ X]+ADRS]
[M]
Symbol for memory location indicated by extended direct or indexed addressing. That is:
[M]=[ ADR16]
or
[[ X]+ADRS]
A
V
Logical. AND
Logical OR
Logical Exclusive-OR
Data is transferred in the direction of the arrow.
¥
9-18
© AD~M OSBORNE:& ASSOCIATES, INCORPORATED
Table 9-1. A Summary of the MC6800 Instruction Set
STATUS
TYPE
MNEMONIC
OPERAND(S)
OPERATION PERFORMED
_BYTES
Z
S
0
2
3
2
3·
2
3
X
X
X
X
X
X
°
°
°
C
g
LOA
0
STA
""
LOX
z
UI
U
Z
UI
ec
UI
II.
UI
ACX,ADRS
ACX;ADR16
ACX;ADRB
-ACX.ADR16
~ ADRB
ADR16
ec
>
ec
- STX
ADRB
ADR16
2
3
X
X
0
:IE
UI
:IE
>
ec
:IE
LOS
ADRB
AOR16
2
3
X
X
°
STS
ADRB
ADR16
2
3
X
X
°
ACX.ADRS
ACX.ADR16
ACX.ADRS
ACX.ADR16
ACX.ADRB
ACX.ADR16
ACX.ADRB
ACX.ADR16
ACX.ADRB
ACX.ADR16
ACC.ADRB
ACX.ADR16
ACX.ADRS
ACX.AOR16
ACX.ADRS
ACX,ADR16
ACX.ADRS
ACX.ADR16
ACRS
ADR16
2
3
2
3
AC
[ACX]-[MEM]
Load A or B using base page direct. extended direct. or indexed-addressing.
[MEM]-[ACX]
Store A or B using direct. extended. or indexed addressing.
[X(HIIJ-[MEMJ. [X(LplJ-[MEM+ 1)
Load Index register using direct. extended. or indexed addressing. Sign status reflects Index
register bit 15.
-[MEM]-[X(HlIl [MEM+ 1]-[X(LO))
-Store contents of Index register using direct. extended. or. index8ct addressing: Sign status
reflects Index register bit 15.
[SPlHII]-[MEMJ. [SPlLOIJ-[MEM+ 11
. load Stack Pointer using direct. extended. or indexed addressing. Sign status reflects Stack
Pointer bit 15.
[MEM]-[SPlHIIJ. [MEM + 11-[SPlLOIJ
0
""a:
Store contents of Stack Pointer using direct. extended. or indexed addressing. Sign status
reflects Stack Pointer bit 15.
A.
ADD
ADC
Q
I-
AND
A.
BIT
>
ec
0
:IE
CMP
~
EOR
~
UI
0
UI
UI
U
zUI
ORA
~-
SUB
ec
UI
ec
>
ec
0
:E
UI
:IE
>
ec
SBC
CPX
2
3
2
3
2
3
2
3
2
3
2
3
2
3
X
X
-X
X
X
X
X
X
X
X
X
X
X
X
°
°
.X
)(
X
X
X
0
X
X
°
X
X
X
X
X
X
X
X
X
X
X
0
l
0
1
X
X
°
°
X
X
X
X
2
3
c(
0
z
CLR
0
u
UI
III
COM
NEG
ADRS
ADR1S
ADRB
ADR1S
ADRB
ADR16
2
3
2
3
2
3
X
I
[ACX]-[ACX]+ [MEM]
Add to Accumulator A or B using base page direct. extended direct. or indexed addressing.
[ACX]-[ACX1+ [MEM]+C
Add with carry to Accumulator A or B using direct. extended. or indexed addressing.
[ACX]-[ACX] 1\ [MEM]
AND with Accumulator A or B using direct. extended. or indexed addressing.
[ACX] 1\ [MEM]
AND with Accumulator A or B. but only Status register is affected.
[ACX] - [MEM]
Compare with Accumulator A or B (only Status register is affected).
[ACX]-[ ACX]¥ [MEM]
Exclusive-OR with Accumulator A or B using direct. extended. or indexed addressing.
[ACX]-[ACX] V [MEM]
OR with Accumulator A or B uaing direct. extended. or-indexed addressing.
[ACX]-[ACX] - [MEM]
Subtract from Accumulator A- or B using direct, extanded. or indexed addressing.
[ACX]-[ACX] - [MEMl- C
Subtract with carry from Accumulator A or B using direct. extended. or indexed addressing.
[X(HII] - [MEMJ. [X(LO)) - [MEM+ 1]
- Compare with contents of Index register (only Status register is affeeted). Sign and Overflow
statuses reflect result on most significant byte.
IM]-OO..
Clear !!!!,mory location using extended or indexed addressing.
[M]-[M]
Complement contents of memory locltion (ones complement).
IM]-:-OO,.- 1M]
Negete contents of memory location (twos complement). Carry stltus is set if result is 00.. Ind
. reset otherwise. Overflow stltus is set if result is SO,. and reset otherwise.
STATUS
TYPE
MNEMONIC
OPERAND IS)
OPERATION PERFORMED
BYTES
C
DEC
INC
AC
Z
S
0
X
X
[M]-[M]-1
X
Decrement content$. of. memory location. using extended or indexed addressing. Overflow
status is set if .operand was BO,. before execution. and cleared otherwise.
[M]-[M]+1
ADRB
ADR16
2
3
X
ADRB
ADR16
2
3
X
ADRB
ADR16
2
3
X
I
Increment contents of memory location. using extended or indexed addressing. Overflow status
is set if operand was 7F 1. before exec\Jtion. and clearect otherwise.
iii
l-
e(
~7~
=
1&1
A.
ROL
0
>
=
0
~
X
X
X
X
0j41 .O-S¥C
[M]
Rotate contents of memory location left through carry.
1&1
~
~c
ROR
Zl&l
1&1::)
ADRB
ADR16
2
3
X
X
X
X,
cm=;:t7
[M]
=Z
~;::::
I&IZ
=0
>u
•
ot;J.o-s"o"C
Rotate contents of memory location right through carry.
ASL
=
0
~
ADRB
ADR16.
2
3
X
X·
X
~7
X
..
o t . - O.
o --S¥C
[M]
Arithmetic shift left. Bit 0 is set to 0,
1&1
.'q;
~
>
=
0
Z
0
U
ASR
e(
ADRB
ADR16
2
X
X
X
X
~
~
ot---.{]]
[M]
o --S¥C
Arithmetic shift right. Bit 7 stays the same.
1&1
en
0
X
TST
ADRB
Ab~16
2
3
0
X
X
0
[M]-OO,.
Test contents of memory location for zero or negative value.
'LOA
ACX.DATA
2
X
X
0
.LDX
DATA 16
3
X
X
0
LOS
DATA16
3
X
X
0
[ACX]-DATA
Load A or B immediate.
[X(HIl]-[B21. [X(LOI1-[B3]
Load Index register immediate. Sign status reflects Index register bit 15.
[SP(HIl]-[B21. [X(LO)]-[B3]
ADD
ACX.DATA
2
X
X
X
X
X
ADC
ACX.DATA
2
X
X
X
X
X
X
0
1&1
0---47
I-
Q
1&1
~
~,
(}t---.{I]
X
~DRB
~ogical
e(
~
2
3
X
ADR16
LSR
O-S¥C
shift right. Bit 7' is set to O.
Load Stack Pointer immediate. Sign status reflects Stack Pointer bit 15.
1&1
I- 1&1
e( I-
Q
e(
=
1&1
~ A.
0
1&1'
~
AND
ACX.DATA
2
X
+
[ACX]-[ACX] DATA
Add immediate to Accumulator A or B.
[ACX]-[ACX] + DATA + C
Add immediate with carry to Accumulator A or B.
[ACX]-[ACX] II DATA
AND immediate with Accumulator A or B.
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 9-1. A Summary of the MC6800 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
BYTES
BIT
ACX,DATA
2
CMP
ACX,DATA
2
OPERATION PERFORMED
C
Z
X
X
0
X
X
X
X
S
0
w
~
~wQ
EOR
ACX, DATA
2
X
X
0
oj
ORA
ACX,DATA
2
X
X
0
w!!:
~~
c(Z
-0
SUB
ACX,DATA
2
X
X
X
X
~
SBC
ACX,DATA
2
X
X
X
X
CPX
DATA16
3
X
X
X
JMP
ADRB
ADR16
2
3
JSR
ADR8
ADR16
2
3
BRA
DISP
2
BSR
DISP
2
BCC
8CS
BEQ
BGE
BGT
BHI
BLE
DI5P
DISP
DISP
DISP
DI5P
DISP
DI5P
DI5P
DISP
DISP
DISP
DISP
DISP
DI5P
2
2
2
2
2
2
2
2
2
2
2
2
2
2
~w
~g
~
~
~
j
~
Z
0
E
Q
Z
0
U
BLS
Z
0
BlT
BMI
BNE
BVC
BVS
BPl
'%
U
Z
c(
II:
CD
AC
I
[ACX] A DATA
AND immediate with
[ACX1-DATA
Acc~mulator
A or B,.but only the Status register is affecttld.
.
Compare immediate with Accumulator A or B (only the Status register is affected).
[ACX]-[ACX]"'t'-DATA
Exclusive-OR immediate with Accumulator A or B.
[ACX]-[ACX] V DATA
OR immediate with Accumulator A or B.
[ACX]-[ACX]-DATA
Subtract immediate from Accumulator A or B.
[ACX]-[ACX] - DATA - C
Subtract immediate with carry from Accumulator A or B.
[X(HII] - [B21. [X(lO)] - [B3]
Compare immediate with contents of Index register (only the Status register is affected). Sign
and Overflow status reflect result on most significant byte.
[PC]-[X] +ADRB or
[PC{HII]-[ B21. [PC{lO)]-[ B3]
Jump to indexed or extended address.
[[SP]F-[PC{lO)1. [[SP]-ll-[PC{HII], [SP]-[SP]-2
[PC]-[X] +AOR8 or.
[PC{HIll-[B21. [PC{lO)]-[B3]
Jump to subroutine (indexed or extended addressing).
[pc]-[ PC] + DISP + 2
Unconditional branch relative to present Program Counter contents.
[[SP]]-[PC{lO)J. [[SP]-ll-[PC{HIIJ. [SP]-[SP]-2,
[PC]-[PC] +DISP+ 2
Unconditional branch to subroutine located relative to present Program Counter contents.
[pc]-[ PCl+ DI5P + 2 if the given condition is true:
C = 0 (Branch if carry clear)
C·= 1 (Branch if carry set)
Z = 1 (Branch if equal to zero)
S J.l-O = 0 (Branch if greater than or equal to zero)
Z V (5 J.l-O) = 0 (Branch if greater than zero)
C V Z = 0 (Branch if Accumulator contents higher than comparand)
Z V (5 J.l-O) = 1 (Branch if less than or equal to zero)
C V Z .= 1 (Branch if Accumulator contents less than or same as comparand)
S J.l-O = 1 (Branch if less than zero)
5 = 1 (Branch if minus)
Z = 0 (Branch if not equal to zero)
= 0 (Branch if overflow clear)
= 1 (Branch if overflow set)
5 = 0 (Branch if plus)
o
o
Table 9:'1.A Summary of the MC6800 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND IS) ,
OPERATION PERFORMED
BYTES
C
a:
.~
!!
c:J
w ,w
a: >
Ii: 0
~ ::E
en
S
w
a:,
;;5
encn
SSw
ww Do
a:a:O
Z
S
0
TAB
1
X
X
0
TBA
1
X
X
0
tis
1
TSX
1
ABA
1
X
X
X
X
CBA
1
X
X
X
X
SBA
1
X
X
X
X
0
1
P
0
CLR
ACX
1
COM
ACX
1
,
X
X
0
NEG
ACX
1
X
X
X
X
X
.X
X
X
,X
X
DAA
DEC
:1
ACX
X
1
t-
DEX
1
0
iI::
w
t-
DES
1
w
Do
en
aw.
INC
ACX
X
X
X
X
INS
1
ROL
ACX
1
X
[A]-[Ah[B]
Add content. of Accumulators A and B.
[A]- [B)
Compare contents of Accumulators A and B. Only'the Status regi.ter i. affected.
[A]-[A] - (B)
Subtract content. of Accumulator B from tho~ of Accumulator A.
(ACX) -00,.
Clellr A~ator A or B.
(ACX)-(ACX)
, Complement cOlltent~ of Accumulator A or B lones complement!.
(ACX) -00,. - (ACX)
Negate cQntents of Accumulator A or B Itwos complement!. Carry'status is set if result is 00,.
and reset otherwise. Overflow status.is set if result is 'SO,. and reset otherwise.
Decimal adjust A. Convert contents of A (the binary sun:' of BCD operands) to BCD format. Carry
status is set if value of upper four bits is greater than 9, but not cleared if previouslY set.
[ACX)-(ACX) - 1
Decrement contents of Stack Pointer.
(ACX)-[ACX) + 1
Increme~t 'contents of Accumulator A or B. Overflow status is set if operand was 7F,. before execution, and cleared otherwise.
[X)-(X)+1
a:
1
[B]-'[A]
. Move Accumulator A contents to Accumulator B.
[A]-[B]
Move Accumulator B contents to Accumulator A.
[SP]-[Xi-l
Move Index register contents to Stack, Pointer and decrement.
[X]-[SP]+1
Move Stack Pointer contents to Index regiiter and increment.
Decrement contents of Index register.
(SP)~(SP) - 1
1
INX
I
Decr~ment contents of Accumulator A or B. OV,erflow status is set if operand was SO,. before
execution,and cleared otherwise,
(X)....:.(X) -!
w
<
a:
AC
X
Increment contents of Index register.
(SP)--(SP) + 1
Increment contents of Stack Pointer.
X
X
X
'X
L{tJ:;47
~
oj;]
(ACX)
Rotate Accumulator A or B left through carTy.
o
--S¥C
© ADAM OSBORNE &
ASSOCIATES. INCORPORATED
Table 9-1. A Summary of the MC6800 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
ROR
OPERAND IS)
ACX
OPERATION PERFORMED
BYTES
1
C
Z
S
0
X
X
X
X
I.e
I
L+{D+I7
S
'"Z
~
j:
Z
0
ASL
!c'"a:
'"0A.
ASR
C;
LSR
ACX
1
X
X
X
[J.-t7
X
'"a:
:It
U
...c
ACX
1
X
X
X
41
X
...
A.
~
...'"
!'
4
o~o.
o --s¥c
~o~.
o --S"V"C
[ACX)
Arithmetic shift right. Bit 7 stays the same.
ACX
1
TST
ACX
1
PSH
ACX
1
PUL
ACX
1
X
0
X
X
0
X
0--47
X
~O~
O-S"rC
Logical shift right .. Bit 7 is set to O.
, [ACX] - 00 1,
Test con.tents of Accumulator' A or B for zero or negative value.
0
[[SP))-[ACX]
[SP]-[SP] - 1
Push contents of Accumulator A or B onto top of Stack and decremimt Stack Pointer.
[SP]-[SP] + 1
[ACX]-[[SP))
. Increment Stack Pointer and pull Accumulator A or B from top of Stack.
[PC(HI)]-[[SP]+ 11. [PC(LO)]-[[SP}+2]. [SP]-[SP]+2
Return from subroutine. Pull PC from top of Stack and increment Stack Pointer.
C/)
a:
a:
o-S¥C
[ACX]
Arithmetic shift .left. Bit 0 is set 'to O.
Y
a:
~
C/)
• oj:;)
[ACX]
Rotate Accumulator A or B right through carry.
RTS
1
CLI
1
0
SEI
1
1
RTI
1
X
X
X
X
X
X
1-0
Clear interrupt mask to enable interrupts.
1":'"
Set interrupt mask to disabl~ interrupts.
[SR]-[[SP]+ 11.
lB] - [[ SP] + 2].
[A]-[[SP] + 3].
[X(HI)]-[[SP] + 41 •
[X(LO)]-[[SP] + 51.
[F'CtHI)]-[[SP] + 61.
[PC(LO)]-[[SP] + 71 •
[SP]-[SP]+7
Return from interrupt. Pull registers from Stack and increment Stack Pointer.
Table 9-1. A Summary of the MC6800 Instruction Set (Continued)
STATUS
TYPE
MNEMONIC
OPERAND(S)
BYTES
OPERATION
C
SWI
Z
S
0
AC
1
1
C
u.I
::I
z
Z
0
9
I-
WAI
1
1
CLC
1
0
SEC
1
1
CLV
1
0
SEV
1
1
TAP
1
TPA
1
NOP
1
u.I
I-
~
e/)
::I
I-
'"
l-
[[ sp]]-[ pcilO)).
[[SP]-l]-[PC(HIl1.
[[ SP]-2] - [X(lO)).
[[SP]-3]-[X(HIl1.
[[SP]-4]-[A1.
[[SP]-5]-[B1.
[[SP]-6]-[SR1.
[SP]-[SP]-7.
[PC(HIl]-[FFFA .. ]
[PC(LO))-[FFFB,~)
i=
a.
::I
a:
a:
PERFOR~ED
I
e/)
X
X
X
X
X
X
Software Interrupt: push registers onto Stack. decrement Stack Pointer. and jump to interrupt
subroutine.
[[SP]]-[PC(lO)).
[[SP]-l]-[PC(HIl1.
[[ SP]-2] - [X(lO)).
[[SP]-3]-[X(HIl1.
[[SP]-4)-[A1.
[[SP]-5)-[B1.
[[SP]-6)-[SR1.
[SP]-[SP]-7
Push registers onto Stack. decrement Stack Pointer. and wiat for interrupt. If [I) =1 when WAI is
executed. a non-maskable interrupt is required to exit the Wait state. Otherwise. [I] - 1 when
the interrupt occurs.
C-O
Clear carry
C-l
Set carry
0-0
Clear overflow status bit
0-1
Set overflow status bit
[SR]-[A]
Transfer contents of Accumulator A to Status register.
[A]-[SR]
Transfer contents of Status register to Accumulator A.
No Operation
MC6800 SUMMARY OF CYCLE BY CYCLE OPERATION
This table provides a detailed description of the information present on the Address Bus. Data Bus. Valid Memory Address line (VMA). and the Read/Write line (R/W) during each cycle for each instruction.
c
w
~
a:
oc..
This information is useful in comparing actual with expected results during debug of both software and hardware as
the control program is executed. The information is categorized in groups according to Addressing Mode and Number
of Cycles per instruction. (In general. instructions with the same Addressing Mode and Number of Cycles execute in the
same manner; exceptions are indicated in the table.)
a:
o(,J
~
enw
~
g
CI)
CI)
oct
oIS
w
Z
a:
oell
CI)
o
~
oct
C
oct
@
9-25
Table 9-2. Operation Summary
ADDRESS MODE
AND
INSTRUCTIONS
w
~
Code Addr_
Op~Addr... +l
Op cOde Addre .. + 2
Addra.. of Operand
Addre.. of Operend + 1
1
1
1
1
1
OpCode
Addre.. of Operand (High Order Bytel
Addra .. of Operand (Low Order Bylel
Operand Date (High Order Bylel
Operlnd Oete (Low Order Bytel
1
2
3
4
15
1
1
1
0
1
Op Cod. Addr_
Op Code Addr... + 1
Op Code Addr... + 2
Operend OOl1lnatlon Addr_
Operand Oel1lnatlon Addr_
1
1
1
1
OpCode
Destination Addr_ (High Order Bytel
Destination Addr... (Low Order Bytel
Irrlll""nt OIW (Notl 11
Daw from Accumulator
l'
2
3
4
Ii
6
1
1
1
1
Op Code Addra ..
Op Code Addr... + 1
Op Code Addrl .. + 2
.Addrl" of Operand
Addr_ of Operand
Addr_ of Operand
1
2
3
4
6
6
2
3
4
6
6
7
8
9
a
I/O
(Notl
31
1
1
1
a
1
1
1
1
1
1
1
1
a
a.
1
Op Code Add .....
Op Code Add..... + 1
Op Code Add ..... + 2
AddraII of O~nd
Add..... of Operand
Add .... of Operand + 1
Op Code Add ....
Op Code Add .... + 1
Op Code Add .... + 2
SubroutlneSwrtlng Addr...
Stack Pointer
Steck Pointer - 1
Steck Pointer - 2
Op Code Addr_ + 2
OP. Coda Addr_ + 2
a
1
1
1
1
1
a
1
1
1
1
0
0
OpCode
Addr... of Operand (High Order By tel
Addr_ of Operand (Low Order Bytil
Currant Operand Oem
Irrelevant Oaw (Notl 11
Naw Ope..nd Oltl (Note 31
OpCode
1
1
1
Addrl .. of Operlnd (High Order Bylil
Addr_ of Ope.. nd (Low Order Bylil
Irralo""nt OIW (NOli 11
Operand Dati (High Order By til
Operand Olta (Low Order Bytil
OpCodl
Addre.. of Subroutine (High Order By til
Addrl .. of Subroutlnl (Low Ordlr Bylil
Op'Code of Next Inl1ructlon
Return Add .... (Low Order Bytil
Raturn Addrl .. (High Order Byltl
Irrelevant Ooto (Note 11
Irrolavlnt Oato (Notl 11
Addre.. of Subroutine (Low Order Byte'
1
1
1
1
a.
a
Op Code Addr...
Op Code ·Addr... + 1
1
1
OpCode
Op Cod. of N.xt Inl1ructlon
4
1
2
3
4
1
1
0
Op Code Addr...
Op Code Addr... + 1
Previous Regll1er Contenll
New Regll1~r Contenll
1
1
1.
1
OpCode
Op Code of NlXt Inl1ructlon
Irrelevant Oltl (Note 11
Irrelavlnt Dote (Note 11
4
1
2
3
4
Op Code Addr_
Op Code Addr... + 1 .
1
1
Stack Pointer
Stack Pointer·- 1
a
a
1
OpCode
Op Code of Next Inl1ructlo\'l
Accumulator Oall
Accu";ulotor Dati
4
1
2
3
4
1
1
0
1
Op Code Addr_
Op Code Addr_ + 1
Stack Pointer
StICk Pointer + 1
1
'1
1
1
OpCode
Op Code of Next Inl1ructlon
Irrelevant Data (Note 11
Operond Data from Stack
4
1
2
3
4
1
1
Op Code Addro ..
Op Codl Addr_ + 1
Stack Pointer
New Index Regil1ar
1
1
1
1
OpCode
Op Code of Next Inl1ructlon
Irralevlnt Oato (Notl 1)
. Irrelevant Olta (Noto 1)
O!'CodeAdd....
Op Code Add .... + 1
Index Regil1ar
New Stack Pointer
1
1
1
1
OpCode
Op Cod~ of Next Inl1ructlon
Irralevant Data
2
(3
w
er
OpCode
Jump Addr_ (High Order Bytel
Jump Addr_ (LoW Order Bytel
1
1
PUL
~
,
DATA BUS
1
2
PSH
er
RIW
LINE
1
1
,
JSR
ABA OAA SEC
ASL DEC SEI
ASR INC SEV
C8A LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA
ADDRESS BUS
,
STAA
STAB
CI)
CI)
VMA
LINE
,
3
~
a:
o0.
CYCLE
NO.
.2
3
JMP
cw
011
w
Z
CYCLES
TSX
TXS
4
1
2
3
4
a
1
1
1
a
a
1
1
a
a
9-27
,rrelevant Data
~
I,:,
Table 9-2. Operation Summary (Continued)
ADDRESS MODE
VMA
LINE
AND
INSTRUCTIONS
ADDRESS BUS
Address of Ne~t Inrtruction (High
Order By tel
Address of Next Instruction (Low
Order By tel
Steck Pointer + 2
Op Code Address
Op Code Address + 1
WAI
Stack Pointer
Stack
Stack
Stack
Stack
Stack
Stack
cw
:)
Z
i=
1
2
3
4
5
6 (Note 41
.!=!
a:
w
Stack Pointer + 2
Stack Pointe, + 3
Stack Pointer + 4
~
Vl
5w
10
a:
r.i:
w
Stack Pointer + 5
Stack Pointer + 6
5w
a:
10
Stack Pointer + 7
Op Code Address
Op Code Address
SWI
OpCode
+.
1
Stack Pointer
Stack Pointer - 1
Stack Pointer - 2
10
11
Stack Pointer Stack Pointer Stack Pointer Stack Pointer Stack' Pointer Vector Address
3
4
5
6
7
FFFA
(He~1
12
Vector Address FFFB
(He~1
12
BCC
BCS
BEC
BGE
BGT
w
>
BHI
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BVC
BVS
BSR
«
-I
W
a:
Irrelevant Data (Note 11
Return Address (Low Order By tel
Return Address (High Order By tel
Inde~ Register (Low Order By tel
Inde~ Register (High Order By tel
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data (Note 11
Address of Subroutine (High Order
By tel
Address of Subroutine (Low Order
By tel
Op Code Address
Op Code Address + 1
Op Code Addre .. + 2
Branch Address
OpCode
Branch Offset
Irrelevant Data (Note 11
Irrelevant Data (Note II'
o p Code Address
Op Code
Branch Offset
Irrelevant Data (Note 11
Return Address (Low Order By tel
Return Address (High Order Bytel
Irrelevant Data (Note 11
Irrelevant Data (Note 11
Irrelevant Data (Note 11
Op Code Address + 1
Return Address of Main Program
Stack ·Pointer
i=
Index Register (High Order By tel
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Contents of Accu ...",lator A from Stack
Index Register from Stack (High Order
.Bytel
Inde~ Register from Stack (Low Order
By tel
Ne~t Instruction Address from Stack
(High Order By tel
Ne~t lAst ruction Addre.. from Stack
(Low Order By tel
~
Vl
Op Code
Op Code of Next Instruction
Return Addre .. (Low Order By tel
Return Addre .. (High Order By tel
Index Register (Low Order'Bytel
Op Code
Irrelevant Data (Note 21
Irrelevant Data INote 11
Contents of Condo Cod. Regilter from
Stack
Contents of Accumulator B from Steck
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
ATI
Z
0
.
Pointer Point~r Pointer Pointer Pointer Pointer -
DATA BUS
OpCode
Irrelevant Data (Note 21
Irrelevant Data ,(Note 11
Op Code Addr....
Op Code Address + 1
Steck Pointer
Stack Poimer + 1
ATS
RIW
LINE
Stack Pointer - 1
Stack Pointer - 2
Return Address of Main Program
Subroutine Address
Note 1.
If device which is addressed during this cycle uses VMA, then the Data Bus will go to the! high impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
Note 2.
Data il ignored by the MPU.
Note 3.
For TST, VMA· 0 and Operand data doel,not change.
Note 4.
While the MPU il waiting for the Interrupt, BUI Available will go high indicating the following states of the control lin.l: VMA il
low; Addresl BUI, RIW, and Data BUlare all in the high impedance Itlte.
9-28
The following codes a~e used in Table 9-3:
aa
ffi
~
:5
:5
Q.
pp
qq
x
o
~
yy
y
two bits choosing the address mode:
00 immediate data
01 base page direct addressing
10 indexed addressing
11 extended direct addressing
the second byte of a two- or three-byte instruction.
the third byte of a three-byte instruction.
one bit choosing the Accumulator:
0 Accumulator A
1 Accumulator B
two bits choosing the address mode:
00 (inherent addressing) Accumulator A
01 (inherent addressing) Accumulator B
10 indexed addressing
11 extended direct addressing
one bit choosing the address mode:
o indexed addressing
1 extended direct addressing
Two numbers in the "Machine Cycles" column (for example. 2 - 5) indicate that execution time depends on the addressing mode.
9-29
Table 9-3, MC6800 Instruction Set Object Codes
MNEMONIC
OPERANO(S)
ABA
ADC
ACX,
ADR8 or DATA
OBJECT
CODE
AND
ACX,
ADR8 or DATA
ADR16
ACX,
1
2
pp
qq
2
2-5
3
4
2
3
2-5
4
2
2-5
4
ASR
pp
qq
BeS
BEQ
BGE
BGT
BHI
BIT
ADR8
7
ADR16 or DATA16
3
6
01yyOlll
1
2
pp
qq
24 pp
25 pp
27 pp
2C pp
2
3
2
7
6
4
2
4
2
4
ADR16
ACX
ADR16
DISP
DISP
DISP
DISr
DISP
DISP
ACX,
ADR8 or DATA
BMI
DISP
DISP
BNE
BPL
DISP
DISP
B~A
DISP
BSR
DISP
BVC
DISP
DISP
4
ADR8
ADR16
2
3
2
2
2
2
i
2
2
2
PSH
ACX
4
PUL
4
6
2
pp
qq
2
3
2-5
4
01yyOOll
1
2
PP
qq
2
7
3
6
ACX
ADR8
ADR16
ADR8
4-6
3
1
1
3-5
2
7
34
2
3
1
09
1
ADR8
ADR16
qq
ADR16 or DATA16
DAA
ACX
DES
ACX,
ADR8 or DATA
ADR16
ACX
PP
qq
2
3
01yyOOOO
1
pp
qq
2
7
6
2
2
7
3
1
6
2
lxaal0l0
2
2
7
ROR
3
1
ADR8
ADR16
PP
qq
6
2
7
3
3B
1
6
10
39
10
1
1
5
2
2
3
2-5
4
ACX,
SEC
SEI
SEV
STA
~CX,
~DR8
ADR16
STS
ADR16
PP
qq
OD
1
2
OF
1
1
2
2
3
4-6
2
5-7
3
6
2
3
5-7
2
2-5
OB
lxaaOlll
PP
qq
PP
qq
llaallll
ADR8
ADRl6
ACX,
ADR8 or DATA
ADR16
2
4
lxaa0010
lOaallll
ADR8
SUB
PP
qq
PP
qq
·
·
·
2
5
6
lxaaOOOO
PP
qq
6
4
12
16
1
2
4
TAP
2
2
2-5
06
17
07
1
TBA
TPA
2
2
3
'1
4
TST
1
1
1
2
'i
7
INS
6
4
INX
08
1
4
= 00 is not
pp
qq
3
1
3
1
PP
qq
4-6
01yyOl00
3F
31
AD~16
3-5
PP
qq
01yyOll0
2
2
ADR8
2
3
1
pp
qq
SWI
TAB
lxaal000
01yyll00
3-5
4-6
ADR8
STX
2
PP
qq
19
01yyl0l0
pp
2
3
ADR16
ACX
ADR8 or DATA
lOaall00
CPX
pp
qq
4
ADR16
lxaaOOOl
4
1
SBC
1
2-5
01yyl00l
SSA
3
2
3
ROL
2
OA
pp
qq
1
2
7
9
lxaaOll0
00ll00lx
1
1
2
8
ACX
ACX
OC
pp
qq
2
3
4
RTS
ADR8
pp
qq
0011011x
4
2
2
3
2-5
2
1
4
2
Rn
29
2
3
3
1
4
4
1
ADR8 or DATA
ADR16
"OR8 or DATA
ADR16
4
4
pp
qq
01
~CX,
2-5
4
4
oe
ACX,
NOP
ORA
8
4
PP
PP
ADR16
ACX
4
4
2
28
ACX
ADR8
2
2
01yyllll
ADR16
·aa
PP
qq
2F PP
23 PP
2D PP
2B PP
26 PP
2A PP
20 PP
8D pp
NEG
CYCLES
llaalll0
ADR8
ADR16 or DATA16
2
ACX
CLI
INC
Pfl
pp
lxaaOl0l
11
CLC
DEX
EOR
2E
22
LDX
LSR
MACHINE
BYTE
lOaall10
LDS
2
BLT
DEC
ADR16
2
DISP
COM
ADR8 or DATA
pp
qq
BLS
CLV
CMP
ADR16
ACX,
01yyl000
BLE
CLR
ADR8
3
1
CODE
101V 11 0 1
JSR
ADR8
ADR16
DISP
BVS
CBA
ADR8
ADR16
LDA
OBJECT
011v1l 10
JMP
lxaaOl00
pp
qq
OPERAND(S)
ACX
ADR8
BCC
MNEMONIC
lxaal0ll
ADR8 or DATA
ADR16
ASL
CYCLES
lB
lxaal00l
ADR16
ADD
MACHINE
BYTE
ACX
01yyll0l
ADR8
PP
qq
ADR16
permitted,
9-30
4
2
2
7
4
TSX
30
3
1
TXS
WAI
35
1
4
3E
1
9
6
SUPPORT DEVICES THAT MAY BE USED WITH THE MC6800
Using 8080A support devices with the MC6800 is very straightforward in terms of control signals generated.
You must break out the single MC6800 R/W' control signal into separate RD and WR control signals. Other signal
interconnections are self-evident. Here is appropriate logic:
cw
-Et>O
g :
. rt>o
:
R/W ---II~""'-------
~
a:
oa..
a:
o(J
WR
~
enw
I-
oCt
C3
oCI)
MC6800
Signals
HALT
CI)
oCt
011
w
Z
a:
IRQ
o
Decode FFF9 on
CI)
o
Address Bus
~
oCt
VMA
III
AD
<1J2 ( T I l l - - - - + - - - - - - - - .
.
. BuSEN
o2 (TTL) 6870 series clocl< a~ follows:
ClR
<1J2(TIL)
Q
B
74lS123
A
9-31
ClK (8080AI
RESET------------------------~--------~
RESET
AODRESS
DECODE
CIRCUIT
A 1 1 - - - - - - - - -..... A1
AO
AO
MC6800
CPU
8251
or
8253
or
8255
..-----------.... ,''1 NMOS
R/W
~2NMOS~
__________
ClK·
~
<1>2 TTL
+ 5V.
100pF
5.6KU
........ "-('l'--~""v--+ 5V
MC6870
or
MC6871
or
ClR
220 ns
<
tw
< 300
ns
QI---------------__________- - J
B
MC6875
CLOCK
·8251 ONLY
74LS123
Figure 9-11. Use of 8080A Support Devices With MC6800 CPU
Figure 9-11 illustrates the interface for an 8251, an 8253 or an 8255 device connected to an MC6800 CPU.
Figure 9-12 provides the timing for 8080A support devices used with an MC6800 CPU.
The 8257 DMA device and the 8259 PICU should not be used in an MC6800 since MC6800 DMA and interrupt logic
are not compatible with these devices.
8085 support devices could be used with an MC6800 but would require that you multiplex the Data Bus and low
order eight Address Bus lines, as required by the 8155, 8355, and 8755. Extra logic needed to perform this bus
multiplexing would probably destroy the cost effectiveness of the 8085 support devices in an MC6800 system.
The only Z80 support device that is practical in an MC6800 system is the Z80 DMA devlce. This is because the
other Z80 support devices decode a Write state from a combination of the M1, INT, and RD control signals. The Z80
DMA device uses separate read and write control inputs: therefore it mqy be used with an MC6800 CPU. The logic
needed to create Z80 DMA control inputs from MC6800 con'trol signals is identical to the 8080A control signal logic illustrated above. The Z80 SIO device will probab!, not be effective in an MC6800 system: in preference, use specific
MC6800 serial 110 devices.
9.:.32
I
\
I
<1)2 NMOS
\
I
\
'1'2 TIL
\
~
•,
ct>1 NMOS
Q
w
~
a:
oa..
a:
o(J
~
enw
R/W. ADDR
VMA 6800
1
I }
\
le(
U
o(J)
DATA IN
r1 ~
6800
~~
(J)
e(
c1J
w
Z
I
DATA OUT
6800
,/
a:
o
m
(J)
o
R5 ORWR TO
I
II
{
8251. 8253. 8255
\ }
\,
1
~
e(
Q
e(
@
Figure 9-12. Timing for 8080A Support Devices Used With an MC6800 CPU
When using non-MC6800 support devices with the MC6800 CPU, remember that there is a particularly pernicious problem associated with MC6800 Reset logic on power-up. As discussed earlier in this chapter. the
MC6800 does not internally disable interrupt requests until the trailing low-to-high transition of the RESET signal. Thus
external devices capable of requesting an interrupt may randomly do so during the power on Reset sequence; and this
may result in an interrupt being acknowledged following the initial system Reset. rather than the expected system initialization program getting executed. You must make certain that all support devices capable of requesting an inter-.
rupt are disabled by the leading high-to-Iow transition of RESET during the power-up sequence.
THE MC6B02 CPU WITH READIWRITE MEMORY
The MC6802 is a combination of the MC6800 CPU, clock logic, and 128 bytes of read/write memory. Figure
9-13 illustrates logic of the MC6802 CPU device.
The actual CPU architecture and the instruction set of the MC6802 are identical to the MC6800 which we have already
described.
The 128 bytes of read/write memory which are present on the MC6802 chip are accessed by memory addresses
000016 through 007F16. The first 32 bytes of this read/write memory maybe protected during power down by a
special low power standby input.
MC6802 CPU pins and signals are illustrated in Figure 9-14. Pins and signals which differ from the MC6800 illustrated in Figure 9-2 are shaded. We will examine these new signals only.
Since clock logic is on the MC6802 chip. three pins are needed for this specific purpose. Normally a crystal will be
connected across XTAL 1 and XTAL2. A 4 MHz crystal should be used since the MC6802 has internal divide-by-four
logic to create a 1 MHz. system clock signal. (An inexpensive 3.58 MHz color burst crystal may also be used.) A TTL
level system clock signal is output via <1>2 (TTL).
You can. if you wish. drive the MC6802 using an external clock signal; this signal is input via XTAL2; it must not be
faster than 4 MHz. XTAL 1 should be left unconnected in this mode.
9-33
(,< I·'··
(
,....".
Logic to Handle
____ Interrupt Requests
---from
External Devices
.. \\....,','
Interrupt Priority
Arbitration
". . . . ii.i.ii
/i'..'·\
??
Direct Memory
Access Control
Logic
,,
'sIt
.···1 "if(
.. ,\,.)
,,:'.
'>' . \
...
... \.\""
System Bus
\ ....'
/
.&
~
~
,
~
ROM Aejdressing
and
Interface Logic
I/O Communication
Serial to Parallel
Interface Logic
• • • ··.~~~)~~dressing
I/O Ports
Interface Logic
•••••
1~:lri4it:;: Logic ~
·""·""'·"'·\\/\·1
,
Programmable
Timers
Read"Only
Memory
'. . ?t,·j'··. . . i.·'.·'. '
I,.'.'{·.'.'.,.~,e. ad. .1. Write
, j it) Memory
I/O Ports
C(i.ii
t,
.,.,.
Figure 9-13. Logic of the MC6802 CPU Device
In order to provide the clock stretching logic that is a standard part of MC6800 microcomputer system, a Memory
Ready (MR) signal is present. MR is normally high. In order to stretch <1>2, MR must make a high-to-Iow transition
while <1>2 is high: <1>2 then remains high untilMR makes a low-to-high transition. Timing may be illustrated as follows:
,
I
I
I
I
x·
<1>2
MR
1
I
I
I
I
I
I
I
200ns
I"
I
~I
I"
9-34
300ns
I
I
I
~I
Vss
c
w
~
a:
oQ.
a:
o
o
~
u)
w
~
g
CI)
CI)
ct
o!I
w
z
a:
o
m
CI)
o
~
ct
C
ct
@
HALT
MR
IRQ
VMA
NMI
BA
VCC
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
..-....
--- -
---
-----
-
--------
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 .
MC6802
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
---- --~
'a
..
..----..
------
---- -- .....
--- -..'
..--....
.-..
RESET
XTAL1
XTAL2
E
RE
YCC(~!J
R/W
.
DO
01
02
03
04
05
06
07
A15
A14
A13
A12
Vss
TYPE
PIN NAME
DESCRIPTION
·AO - A15
·00 - 07
·HALT
·MR
·RE
·R!W
·VMA
·BA
·IRQ
RESET
NMI
XTAL1.XTAL2
E
VSS.VCC
VCC (ST)
Output
Address Lines
Tristate. Bidirectional
Data Bus Lines
Input
Halt
Input
Memory Ready
Input
RAM Enable
Output
Read/Write
Output
Valid Memory Address
Output
Bus Available
Input
Interrupt Request
' Input
Reset
Input
Non-Maskable Interrupt
Crystal/Clock Connections Input
Output
Enable
Power
Standby Power
·These signals connect to the System Bus.
Figure 9-14. MC6802 CPU Signals and Pin Assignments
Two signals have been added to support the on-chip read/write memroy. RE is an enable signal for the on-chip
memory. RE must be input high for the on-chip memory to be accessed. If RE is low. on-chip memory cannot be written
into or read. While on-chip memory is disabled its address space is also disabled. and addresses in the range 000016
through 007F16 are deflected to external memory. Thus the address space 000016 through 007F16 is duplicated:
it accesses on-chip RAM when RE is high. but it accesses external RAM when RE is low.
.
The first 32 on-chip read/write memory bytes (with addresses 0000 through 001 F) can have the contents preserved by
applying +5V at the V CC standby pin when power is down on the MC6802. But to be of anY value. we must guarantee
that the contents of. these 32 read/write memory' locations are not destroyed during any power down sequence: in
other words. we must anticipate any power down. In order to preserve the contents of the 32 low-order read/write
memory bytes.RE must be input low at least three clock periods before power drops below +4.75V. This is easy
enough to dofor a scheduled power down: however. it is impossible during a non-scheduled power down - such as
might occur as the result of a power failure - unless power-down-interrupt circuitry is provided.
MC6800 signals which have been removed, going to the MC6802. include the clock inputs <1»1 and <1»2, plus the
bus control signals TSC and DBE.
Obviously. the clock inputs must be removed since clock logic is now on the CPU chip.
9-35
·
.
..
.
"
.
Removal of the System Bus control signals TSC and DBE reflects the fact that if you are going to need direct memory
access. you are not going to use the MC6802. Only larger microcomputer systems need direct memory access; for such
systems the MC6800 is available. The MC6802 is intended as half of a two-chip 6800 configuration. witr.in which
direct memory access would be meaningless.
If DMA is necessary with a 6802-based system. then the use of external tristate bus drivers will be necessary. Bus
Available (SA) and HALT are available on the 6802 for this purpose.
The MC6846 multi-function device is the other half of the two-chip microcomputer system. However, the
MC6846 can be used with the MC6800 CPU or the MC6802 CPU; therefore it is described later in this chapter
along with other 6800 support devices.
When HALT is input low, the MC6802 enters the Halt state at the end of the current instruction's execution. In the
Halt state the Data Bus is floated. Bus Available (BA) is output high. and 'valid memory address (VMA) is output low.
The Address Bus outputs the address of the instruction which will be executed when the halt condition ends. Timing
may be illustrated dS follows:
~One machine
,
I
I
<1>2
HALT
BA
VMA
00 - 07
AO - A15
Instruction
execution
ends here
The HALT input signal is level sensitive. The level of HALT is sensed 250 nanoseconds before the end of a machine cycle. If HALT is low at this time. then the low level is detected. If HALT makes a high-to-Iow transition within the last 250
nanoseconds ofa machine cycle. then it may not be detected. This may be illustrated as follows:
<1>2
--.J
I
I
\
I
I
I
,--.-;..---\
I
\,- - - - - - 1...- - I
I
I
I
I
HALT
HALT low not
detected here
9-36
,
I
1~50=-1
Halt low
detected here
I
I
I
~I
250 ns
.
Once a Halt has been detected. the current instruction completes execution before the Halt condition starts. In the
simplest case this may be illustrated as follows:
I
"
I
~2-1---~\~
cw
oD..
I
I
!;t
II:
I
__~/~~~\~__~/~--~\~__~
I
I
I
\
HALT
II:
~.·250ns
CJ
I
o
~
enw
!;t
g
CI).
CI)
c:(
.
. End. ot! HALT
instruction I
begin~
If a Halt transition occurs within the last 250 nanoseconds of a machine cycle. then the HALT will probably not be
detected until the next machine cycle. Assuming that the next machine cycle terminates an instruction's exeuction.
the Halt condition will begin as follows:
~
w
Z
II:
o
al
~2
CI)
o
~
I
I
\
I
I
I
I
I
I
I
}
......
\
I
I
~
c:(
cc:(
HALT
HALT low
: not detected
I
here
\1:j
I
I
I
250ns~
------,
I
I
I
@
,....................I,."'\ '
~
~
~
HALT low
detected
here
250ns
End of
instruction
The next machine cycle could be the first of a multi-machine cycle instruction. Now the Halt condition will begin as
follows:
~2
HALT
here
I
Next instruction
End of I.......
,
---executes in three - - -__
instruction :
machine cycles
:1~;~~j,~i[~;~~llmlllllll
.t!IHI~Ll~bElaln,s}.i.
Note that if the HALT transition had occurred a little earlier. the HALT condition would have begun a whole instruction
exeuction time sooner - three machine cycles sooner in the illustration above.
9-37
The HALT condition terminates on the machine cycle that follows HALT going high again. Once again the HALT signal
is sampled 250 nanoseconds before the end of the machine cycle. Thus the HALT may terminate within the machine
cycle where the HALT signal makes a low-to-high transition:
\
I
I
But the HALT 'cpndition hlay terminate one machine cycle later if the HALT signal makes its low~to-high transition
within the last 250 nanoseconds of a machine cYGle. This may be illustrated as follows:
I
.),
""'.,
,
<1>2
I
\
I
I
HALT
'"''
.'."·,··,i
Start next instruction's
iA
Al2
I
I
HALT
Th"
I
h;gh-to-~w :::,::.:Y
occurring too late, is I
not detected I
I
I
\~II_ _ _~_ _ _•
r- J",.;,
I
~
Th;,
I
never detected
~250ns
I
I
I
I
During the HALT condition no interrupts will be acknowledged. If any interrupt requests occur during a HALT condition, they simply stack up waiting for the end of the HALT condition.
There are also some differences in MC6802 interrupt and reset logic as compared to the
MC6800.
INTERRUPTS
DURING AN
MC6802 HALT
Motorola literature recommends that interrupt request inputs IRQ and MNI have a 3K ohm external resistor to
This may be illustrated as follows:
Vee
3.0Kfl
6802
IRQ or NMI .....t--t~--
9-38
Vee.
The MC6802 RESET input may be a stand-alone input or it may be tied to the RAM enable input (RE). Timing for the
RESET signal rise and fall differs in the two cases. as defined in the·9p.t~ sheets at the end of this chapter. Note that by
tying RESET to RE you cause the on-chip RAM to be enabled whenever the MC6802 is receiving power.
~
~
~
The MC~802, like the MC6800, does not disable interrupts until clo~e to the end of the reset sequence. Thus. if
you have non-6800 support devices connected to an MC6802. you must make certain that you have included logic that
prevents these !3Upport devices from requesting an interrupt until after the reset operation has gone to completion. If
you do not take this precaution. then following RESET you mClY vector to a support deyice's interrupt service routine
rather than ex~cuting the intended system initialization program.
Q.
a:
o
~
en
~
§
CI)
~
THE MC6870 TWO PHASE CLOCKS
Four clock logic:: devices supporting the MC6800 CPU are described. The MC6802 does not need any external
clock logic device~
The MC6~70A is' a very elementary device providing minimum clock signal~ needed with an MC6800
microcompute'r system. Its pin assignments are illustrated in Figure 9-15.
all
w
Z
a:
o
m
CI)
GND
1
24
3
22
o
~
ct
ct
C
@
ct>2 (TTL)
--
Vee (+ 5V)
(iJ2 (NMOS)
-
5
20
MC6870A
7
18
12
13
GND
-..
ct>1 (NMOS)
Pin Name
Description
Type
<1>1 (NMOS)
(1)1 Clock to MC6800
Output
<1>2 (NMOS)
(1)2 Clock to MC6800
Output.
ct>2 (TTLl
ct>2 Clock to microcomputer
Output
system
Vee. GND
Power and Ground
Figure 9-15. MC6870A Clock Device Pins and Signals
9-39
The first enhancement is provided by the Me6S71 A, illustrated in Figure 9-16, which adds clock signal stretching capabilities and a twice frequency clock output.
GND
MEMORY CLOCK
-
--
<1>2 (TTL )
Vcc (+ 5V )
<1>2 (NMOS)
--
1
24
3
22
5
20
...
.:..
2xfc
MEMORY READY
~
~
. MC6871A
7
18
12
13
GND
-
<1>1 (NMOS)
Pin Name
Description
Type
<1>1 (NMOS)
<1> 1 Clock to MC6800
Output
<1>2 (NMOS)
<1>2 Clock to MC6800
Output
<1>~ (TIL)
<1>2 Clock to microcomputer
Output
MEMORY CLOCK
Select to memory devices
Output
2xfc
Twice frequency clock
Output
'HOL5i
Stretch <1>1 high control
Input
MEMORY READY
Stretch <1>1 low control
Input
Vcc,GND
Power and Ground
system
.
,~Figure 9-16. MC6871A Clock Device Pins and Signals
.
The Me6S71 B, iIIustr'~.tY~Figure 9~17, is a. varia. tion of the Me6S71 A .
~
GND
<1>2
(TTL)
---
UNGATED
<1>2 (TTL )
Vcc (+ 5V )
<1>2 (NMOS)
24
3
22 ~
5
20
7
-
Pin Name
-.
1
MC68718
12
-
-
18
13
Description
2xfc
GND
------
<1>1 (NMOS)
Type
<1>1 (NMOS)
<1>1 Clock to MC6800
Output
<1>2 (NMOS)
<1>2 Clock to MC6800
Output
<1>2 (TTL)
<1>2 Clock to microcomputer
Output
system
<1>2 (TTL) UNGATED
Free-run~ing <1>2 (TTL)
2xfc
Twice frequency clock
Output
HOL51
HOL5'i
Stretch <1>1 high control
Input
Stretch <1>1 low control
Input
Vcc. GND
Power and Ground
Output
Figure 9-17. MC6871 B Clock Device Pins and Signals
9-40
...
--.
X1
X2
EXT IN
c
4xfc
!iII:
2xfc
MEM READY
w
o0.
'1>2 (TTL)
II:
o
GND
--
- ..
--
1
2
3
4
5
16
15
MC6875
6
7
14
13
12
11
10
-...
--leG--..
.-
:-
V cc (+5V)
'1>1 (NMOS)
RESET
'1>2 (NMOS)
SYs REs
REF GRANT
DMA/REF REO
9 ~ MEMORY CLOCK
8
U
~
iii
w
!i
t3
o
(/)
Pin Name
Description
Type
e1>1 (NMOS)
ct>1 Clock to MC6800
Output
'1>2 (NMOS)
ct>2 Clock to MC6800
Output
ct>2 Clock to micro~om-
Output
el>2 (TTL)
(/)
puter system
c:(
MEMORY CLOCK
Free-running ct>2 (TTL)
2xfc
Twice frequency clock
Output
Output
II:
4xfc
Four Times frequency clock
Output
al
DMA/REF REO
Stretch ct>1 high control
Input
REF GRANT
Stretch ct>1 high, acknowledge
Output
~
MEM READY
Stretch ct>1 low control
Input
c
c:(
SvS"RES
c:(
RESET
Asynchronous system reset control
Synchronous reset control
Output
EXT IN
External synchronization control
Input
X1. X2
External crystal connections
Vcc. GND
Power and Ground
ciJ
w
Z
o
(/)
o
@
Input
Figure 9-18. MC6875 Clock Device Pins and Signals
The MC6875 is the most versatile of the clock devices provided for the MC6800. It is illustrated in Figure 9-18.
Since these various clock logic devices represent essentially the same capabilities, but with increasing enhancements, we will describe logic and capabilities in the order of the device illustrations.
Much of the clock device logic we are going to describe stretches the <1>1 (NMOS) and <1>2 (NMOS) clock signals. But recall that stretching <1>1 (NMOS) and <1>2 (NMOS), in itself, is only half of the logic needed to stretch
the entire System Bus. Additionally, the MC6800 needs a high TSC input to float ,the Address and RIW Bus lines
while <1>1 (NMOS) is high. DBE must be input low in order to float the Data Bus lines while the clock is being
stretched with <1>1 (NMOS) low.
THE MCG870A CLOCK DEVICE
This is a minimum clock device; it outputs <1>1 (NMOS) and <1>2 (NMOS), the two clock signals required by an
MC6800 CPU.
<1>2 (TTL) is also generated. <1>2 (TTL) is used to synchronize support devices; it has sufficient load capacity to
drive five devices without signal buffering.
The MC6870A contains an internal crystal and oscillator: in its standard form clock Signals with a 1 MHz frequency are
generated. A variety of other clock frequencies can also be ordered.
THE MCG871 A CLOCK DEVICE
In addition to the standard signals output by the MC6870A. the MC6871 A provides two additional TTL output clock
signals and externally controlled pulse stretching capabilities.
9-41
HOLD1 is used to stretch the standard clock signals: <1>1 (NMOS), '<1>2 (NMOS) and <1>2 (TTP, which we described for the MC6870A Timing may be illustrated as follows:
<1>2 (NMOS) and <1>2 TTL
It is very important that HOLD 1 makes its active highcto-Iow transition during a <1>1 (NMOS) high state, Subsequently.
<1>1 (NMOS). <1>2 TTL clocks will be stretched until HOLD1 makes a I()w-to-high trahsition within the contraints desc~ibed below.
.
.
".
r.-----~
As illustrated above. HOLD1 stretches clocks with <1>1 (NMOS) high. If you refer back to our dis-MC6800
cussion of the MC6800. you will see that these clock levels identify the portion of a machine cycle
STRETCHING
when an address is being output. Typically. the clock will be stretched so that two addresses can
ADDRESS
be output: the first for a Direct Memory Access or dynamic memory r!3fresh operation:' the second
TIMING
for the normal address output which is required when any :instruction is executed. Device select
logic must discriminate between the two addresses being output: DMA or dynamic memory refresh logic must receive
. ,
the first address only. while memory or I/O devices receive the second address only.
Two additional clock signals are output by the MC6871A: 2xfc and MEMORY..Qb.Q£.K: they are not part of normal
memory addressing logic. therefore these two clock signals are not stretched by HOLD1.
2xfc is it twice frequency clock signal which can be used for various synchronization logic around an MC6800
microcomputer system.
MEMqRY CLOCK is identical in waveform to <1>2 TTL
e~cept
MEMORY CLOCK is not stretched by HOLD1.
HOLD1 must make its high-to-Iow transition while <1>1 (NMOS) is high. HOLD1 must subsequently make its low-to-high
transition 'while <1>1 (NMOS) would have been high. had it not been stretched. An asynchronous HQ~D~ request must
therefore be synchronized with <1>1 (NMOS) in order to' generate a valid HOLD1 clock input. This is asjmple logic
operation: here !s one pgsSi~ility:
+5V
1r
Asynchronous ~_ _ _ _ _ _ _--I
R . QLHOL01
10
HOLD reque~t
7402
1/274LS74
MEMORY CLOCK
-----01--
c~
2xfc
OMA or Refresh
Acknowledge
+5V
9-42
This circuit synchronizes the high-to-Iow and the low-to-high transition of HOLD1. The low-to-high clock transition occurs only during .eIl1 (NMOS) high time:
(1)1 (NMOS)
c
w
~
oa..
MEMORY CLOCK
a:
a:
o
o
2xfc
~
iii
w
~
(3
o
In
In
Observe that synchronization logic can create a time delay of up to one half clock cycle between the unsynchronized
and the synchronized HOLD signals changing state.
o!I
MEMORY READY also stretches clock l:Iignais. Timing may be illustrated as follows:
ct
w
Z
a:
o
ct>1 (NMOS)
In
In
o
~
ct
ct
(1)2 (NMOS!. ct>2 TTL
c
@
MEMORY READY
2xfc
Clock signal stretching begins with eIl2 (NMOS) high following the MEMORY READY high-to-Iow transition. Clock
stretching ends with the falling edge of 2xfc following the MEMORY READY low-to-high transiiibn. Observe that
MEMORY READY stretches MEMORY CLOCK: which HOLD.1 does not do. 2xfc. however. is not stretched. either by
HOLD1 or by MEMORY READY Also note that MEMORY READY does not require input synchronization. as does
HOLD1.
If you refer back to the timing diagrams which illustrate MC6800 instructions' execution. you will see that MEMORY
READY stretches cloc~ signals during the data access portion of a machine cycle. This is the part of the machine cycle
during which external memory has to respond to a CPU access; therefore. this is the portion of the tnachlne cycle
which must be stretched for slow memories - which is why MEMORY READY can be visualized as the signal which
slow memories must input low in order to .9clin the access time tHt3y require.
The MC6871A contains an internal crystal oscillator. In its standard for~. clock signals with a 1 MHz frequency
are generated. A variety of other clock frequencies can also be ordered.
THE MC6871 B CLOCK DEVICE
This device differ~ ,from the MC687iA
in two ways. MEMORY READY is replaced by HOLD2 and MEMORY
CLOCK is replaced by eIl2 (TTL) UNGATED. HOLD2 stretches clock signals with eIl1 (NMOS) low. just as MEMORY
READY did; however. like HOLD1. HOLD2 must have its active transitions synchronized with the clock output - in this
case with eIl2 high. eIl2(TTL) UNGATED. however. is not stretched. Timing may be illustrated as follows:
ct>2 TTL UNGATED
\
9-43
I
THE MC6875 CLOCK DEVICE'
This is the most sophisticated of the clock devices offered with the MC6800 microcomputer system. Its principal features are that it performs control input synchronization which must be handled externally by other
clock devices; also, the MC6875 allows external timing.
As we have already stated. clock signals are stretched with <1>1 and <1>2 low in order to allow a Direct Memory Access or
dynamic memory refresh address to be output The MC6875 DMA/REF REO input performs this clock stretching
operation, just as HOLD1 does, except that DMA/REF REO can be an asynchronous input. MC6875 internal logic
performs the synchronization operations wbich have to be handled externally for the MC6871 A and MC6871 B clocks.
In addition. the MC6875 outputs REF GRANT high while the clocks are being stretched with <1>1 (NMOS) high. External
DMA or dynamic memory refresh logic can use REF GRANT as an enable strobe:
MEMORY READY and MEMORY CLOCK are as described for the MC6871 A. MEMORY READY stretches clocks
with <1>1 (NMOS) low. MEMORY CLOCK fOllows <1>2 (NMOS) and is stretched by MEMORY READY but not by DMA/REF
REO.
.
The MC6875 clock signal outputs <1>1 (NMOS) and <1>2 (NMOS) have sufficient capacity to drive two MC6800
CPUs. 4xfc is an additional oscillator running at four times the <1>1 and <1>2 clock rates.
X1, X2 and EXT IN are three signals which allow MC6875 clock rates to be controlled externally.
You can optionally attach a crystal oscillator or an RC network to Xl. X2 as follows:
CRYSTAL OPERATION
RC OPERATION
You can also input an external clock signal to EXT IN, in which case the MC6875 will adopt the frequency of the
external signal. The external clock frequency must be four times the <1>1 and <1>2 clock frequency.
The MC6875 is able to take an asynchronous SYSTEM RESET input and convert it into a synchronous RESET,
which may be used throughout an MC6800 microcomputer system SYSTEM RESET can be any input Signal which is
processed through a Schmitt trigger to create a RESET output. as described for the 8224 clock device in Chapter 4.
SOME STANDARD CLOCK SIGNAL INTERFACE LOGIC
There are a number of very common ways in which MC6870 series clock signals are used within MC6800
microcomputer systems.
You will find that all of the support devices described in the rest of this chapter require an
enable synchronizing signal, given the symbol "E". This signal is usually generated as the
AND of the MC6800 VMA output and the <1>2 TTL clock output:
.
___
<1>2 TTL _ _ _....,~u_·
E
'VMA
~
MC6800
ENABLE
SIGNAL
GENERATION
The purpose of ANDing <1>2 with VMA is to make sure that devices receiving signal E are inhibited while VMA is lowat which time the CPU cannot be accessing the support device.
9-44
The HALT signal. which is used in MC6800 microcomputer systems to float the System Bus for
extended periods. must be a synchronous input. You can create a synchronous HALT from
an asynchronous HALT using <1>2 TTL as follows:
MC6800
SYNCHRONOUS
HALT
GENERATION
+5V
c
w
~
a:
o
Asynchronous HALT -----t15
a.
a:
o
o
Synchronous HALT
1/274LS74
~
u)
w
<1>2 TTL
'X)---f)CK
~
g
(/)
(/)
~
+5V
a1J
w
Z
a:
o
THE MC6820 AND MCS6520 PERIPHERAL INTERFACE ADAPTER
(PIA)
m
(/)
o
~
~
c
~
©
This part is manufactured as the MC6820 by the companies listed at the beginning of this chapter. MOS Technology and its second source companies (whose products are described in Chapter 10) manufacture the same
part, but call it the MCS6520.
The MC6820 PIA is a general purpose I/O device, designed for use within MC6800 microcomputer systems.
The MC6820 PIA provides 16 I/O pins, configured as two 8-bit I/O ports. We will refer to these as Port A and
Port B. Individual pins of each I/O port may be used separately as inputs or outputs. Each I/O port has two associated control signals, one of which is input only, while the other is bidirectional. The only differences between
I/O Ports A and B are in their electrical characteristics, and in their handshaking control capabilities. But these are
very significant differences. as we will explain shortly.
Figure 9-19 illustrates that part of our general microcomputer system logic which has been implemented on the
MC6820 PIA.
The MC6820 PIA is packaged as a 40-pin DIP. It uses a single +5V power supply. All inputs and outputs are TTL
compatible.
The device is implemented using N-channel silicon gate MOS technology.
THE MC6820 PIA PINS AND SIGNALS
The MC6820 pins and signals are illustrated in Figure 9-20. We will summarize signal functions before describing PIA operations.
Consider first the various Data Busses.
DO - 07 represents the bidirectional Data Bus via which all communications between the CPU and the MC6820
occur.
PAO - PA7 and PBO - PB7represent Data Busses connecting the two 8-bit I/O Ports A and B with external logic.
. The 16 I/O port pins may be looked upJn as 16 individual signal lines. or two 8-bit I/O busses. Each I/O port pin can be
individually assigned to input or output. but an individual pin cannot support bidirectional data transfers.
These are the differences between I/O Port A and B pins:
1)
Bits of I/O Port A may be set or reset at any time by voltage levels applied to associated pins. Irrespective of data
that may be in a bit position following a Read or Write operation. an I/O Port A bit will be reset to zero any time a
voltage of +O.8V or less is applied to a Port A pin. A 1 will be written into a Port A bit any time a voltage of +2V or
more is applied to the Port A pin. I/O Port B bit contents are not affected by voltage levels at I/O Port B pins. For example. suppose that a 1 has been output to bit 2 of I/O Ports A and B. Subsequently suppose that pin 2 of I/O Ports
A and B are drained excessively. so that voltage levels transiently drop to +O.5V. I/O Port A bit 2 will become O. but
I/O Port B bit 2 will retain a level of 1.
2)
As outputs. I/O Port B pins may be used as a source of up to 1 mA at +1.5V. to directly drive the base of a transistor
switch. This is not feasible using I/O Port A pins.
9-45
Clock Logic
'/...
Logic to ~a9~1~
...
Arithmetic and
Logic Unit
'nterru~:o~2;{f~j I· .:::\. . .>·.-_~
_
External Devices
--
Accumulator
Registerlsl
Instruction Register ~
-
Control Unit
'-----r---'
~
Data Counterlsl
Stack Pointer
II
Bus Interface
Logic
~ Program Counter
Direct Memory
Access Control
Logic
.,
t
System Bus
t
•
I/O Communication
. . Serial.to Parallel
Interface Logic
ROM Addressing
and
Interface Logic
RAM Addressing
and
Interface Logic
t
Programmable
Timers
Read Only
Memory
Read/Write
Memory
...
.~
~
..
Figure 9-19. Logic of the MC6820 PIA.
There are five device select pins.
CSO, CS1 and CS2 are three typical chip select signals. For an MC6820 device to be selected. CSO and CS 1 must
receive high inputs while CS2 simultaneously receives a low input. '
Providing CSO. CS1 and CS2 have selected an MC6820 device. RSO and RS1 address one offour memory locations.
Thus an MC6820 device will appear to a programmer as four memory locations.
Any of the standard schemes described in Volume I can be used to address an MC6820 PIA. There is nothing unusual
about the select logic with which you will assign four unique memory addresses to an MC6820.
The're are four timing and control signals which interface an MC6820 with external logic.
CA 1 and CA2 are control signals associated with I/O Port A. CA 1 is an input only signal and is usually used by external logic to request an interrupt. CA2 is a bidirectional control signal which is used to implement various types of
handshaking'logic.
CB1 and CB2 are the control signals which support I/O Port B.. These tw~ signals are analog'o~s to CA 1 and CA2.
although there are some differences in the handshaking logic associated with CB2 as compared to CA2.
9-46
Vss
PAO
PAl
PA2
PA3
PM
PA5
PA6
PA7
PBO
PBl
PB2
PBl
0
w
~
II:
0
a..
II:
0
u
~
en
w
I-
ct
g
PB4
(I)
(I)
PB5
PB6
PB7
CBl
CB2
ct
all
w
Z
II:
0
In
(I)
0
Vcc
--.. -......
-.-. --..-...-. ---..
- --~
-.-. ..-
--
..
..-
--- ....
- ..
---
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MC6820
PIA
(MCS6520)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
~
ct
Q
ct
@
- -..
----- -- ..
-- .-.. ..
---- .."'"-
.. .-
-----....
-..
-----
CAl
CA2
iROA
IROB
RSO
RSl
RESET
00
01
02
03
04
05
06
D7
E
CSl
CS2
CSO
R/W
Pin Name
Description
Type
00- 07
PAO - PA7
PBO - PB7
CSO. CSl. CS2
RSO. RSl
CAl
CA2
CBl
CB2
E
R/iii
iR'QA. IROB
Data Bus to CPU
Port A peripheral Data Bus
Port B peripheral Data Bus
Chip Select
Register Select
Interrupt input to Port A
Port A peripheral control
Interrupt input to Port B
Port B peripheral control
Device synchronization
Read/Write coritrol
Interrupt request
Reset
Power and Ground
Tristate. bidirectional
Input or Output
Tristate. Input or Output
Input
Input
Input
Input or .output
Input
Input or Output
Input
Input
RESeT
Vcc. Vss
Output
Input
Figure 9-20. MC6820 PIA Signals and Pin Assignments
There are two control signals associated with the MC6820 CPU interface.
E is the standard synchronization signal generated by the various MC6870 series clock devices. The trailing edge
of E pulses synchronizes all logic and timing within the MC6820. Manufacturer literature refers to E as a device enable
signal. but it is more accurately viewed as a device synchronization signal.
R/W is the standard RsadlWrite control signal output by the MC6800 CPU. When RIW is high. a Read operation is
specified; that is. data transfer from the MC6820 PIA. to the MC6800 CPU occurs. When R/W is low. a Write operation
is specified; that is. data transfer from the CPU to the PIA occurs.
There are two interrupt request signals, IROA and IROB. Under program control you can specify the conditions
under which an interrupt request can originate at logic associated with 1/0 Port A or 1/0 Port B. The actual interrupt request is transmitted to the MC6800 CPU via signallROA for 1/0 Port A logic. and via IROB for 1/0 Port B logic. Interrupt
requests originating at either signal will connect to the MC6800 IRO input.
.
RESET is a standard Reset input. When it is input low. the contents of all MC6820·registers will be set to zero.
9-47
ffiQA38~~---------------------------------------i
INTERRUPT
STATUS
CONTROL A
40 CAl
39 CA2
DO 33
01 32
0231
0330
04
OS
D6
07
DATA BUS
BUFFERS
(DBB)
29
28
27
26
OUTPUT BUS
BUS INPUT
REGISTER
(BIR)
PAO
PAl
OUTPUT
REGISTER A
(ORA)
4
PA2
PA3
PM
PA5
PA6
9
PA7
10 PBO
OUTPUT
REGISTER B
(ORB)
11
12
13
14
PBl
PB2
PB3
PB4
15 PB5
111 PB6
i7 PB7
INPUT BUS
CSO 22
CS124
CSi 23
RSO 36
CHIP
SELECT
AND
RS135
R/iN
RJW21
ENABLE 25
RESET 34
CONTROL
ffiIoB37------------------------------------------~
INTERRUPT
STATUS
CONTROL B
18 CBl
19 CB2
Figure 9-21. Functional Block Diagram for the MC6820 PIA
MC6820 OPERATIONS
As compared to the 8255 PPI. the MC6820 PIA has less formalized operating modes. The MC6820-to-externallogic interface consists of two I/O ports. each of which has two dedicated control lines. You have the option of assigning individual I/O port lines to input or output; as a completely separate operation you can use the two control lines to
perform a limited amount of handshaking and interrupt processing - or you can ignore the control lines, in
which case the I/O port is supporting simple input and/or output. Bidirectional I/O, equivalent to 8255 Mode 2,
is not available. Figure 9-21 generally represents MC6820 functional organization and Table 9-4 summarizes
the available operating modes.
9-48
Table 9-4. MC6820 Operating Modes
OPERATING MODE
c
MC6800 AVAILABILITY
Simple input
without handshaking
I/O Port A or B
Simple output
without handshaking
I/O Port A or B
Bidirectional I/O
without handshaking
Not available. but individual pins of
either I/O port may be separately
assigned to input or output
Input with
handshaking
I/O Port'A only
Output with
handshaking
I/O Port B only
Bidirectional I/O
with handshaking
Not Available
w
~
oa..
a:
a:
o(J
21:
Iii
w
~
g
en
en
~
015
w
Z
a:
oCD
en
o
~
~
c
~
@
Table 9-5. Addressing MC6820 Internal Registers
SELECT LINES
ADDRESSED LOCATION
RS1
RSO
0
1
0
0
0
0
1
1
X
7
f
0
0
5
4
2
3
1
o ...--Bit No.
I I I I I IX I I
J
I/O Port A Control register
0
I/O Port A DataDirection register
1
I/O Port A Data buffer
7
1
1
6
6
5
4
3
2
1
o
I I I I I IX I I
t
0
1
~BitNo.
I/O Port B Control register
J
I/O Port B Data Direction register
I/O Port B Data buffer
There are six addressable locations within an MC6820 PIA; they are shaded in Figure 9-21.
MC6820
Since there are only two register select lines. RSO and RS1. four unique addressable locations can
REGISTERS
be identified within the MC6820. Table 9-5 summarizes the manner in which the MC6820 uses
ADDRESSING
four addresses to access six locations. Logic defined in Table 9-5 requires that you first output a
Control code to each I/O port Control register: next you access either the I/O port Data Direction register. or the I/O port
Data Buffer. You use the same memory address to access an I/O port Data Direction register and I/O port Data Buffer.
Which location you access is determined by bit 2 of the I/O port's Control register.
9-49
You must precede any 1/0 port Data Direction register. cjrData Buffer access with a Control code. written to the 1/0
port's Control register. Once you have written a Control code to an 1/0 port Control register: you do not have to write
another ,Control, code for addressing purposes until you, wish to switch from accessing the 1/0 port Data Direction
register to the Data Buffer. or from accessing the Data Buffer to the Data Direction register.
.
To illustrate MC6820 addressing. suppose the four addresses C00016. C00116.C00216 and C00316 select an
MC6820. This is how addressable locations within the MC6820 would actually be selected if address line AO were connected to RSO and A 1 to RS1:
Address
Selected
, C00016 ' 1/0 Port A Data Direction register. if C00116CF1. bit 2 = 0
1/0 Port A Data buffer. if C00116. bit 2 = 1
C00116 1/0 Port A Control register
C00216 1/0 PortBData Direction register. if C00316. bit 2 = 0
1/0 Port B Data buffer. if C00316. bit ;2 = 1
C00316 1/0 Port B Control register
If you read from an 1/0 port data buffer. you input from the 1/0 port to the CPU; if you write to anllO port data buffer.
you output from the CPU to the 1/0 port.
The Data Direction registers identify each pin of an 1/0 port as being dedicated to either input or output. These are
write only registers. You must write a control word into each Data Direction register; a 0 in a bit position configures the
corresponding 1/0 port'pin as an input. While a 1'results in an output:
654
o
"'-BitNo.
I/O Port
Pins
, Observe that 1/0 Ports A arid B will both be configured as 8-bit input ports when the MC6820 is reset. since RESET
clears all internal registers.
"
'.
,
-
9-50
Control register interpretation is quite complex.
The two high-order bits of each Control register are read only locations. which record the status of
interrupt requests which may originate from either of two control lines associated with an I/O
port:
C
w
~
0:
0
D-
o:
u
0
~
en
...ctw
U
0
en
en
MC6820
CONTROL
CODES
Both interrupt requests are
~
I I I
output via
,t
6
5
4
3
2
iRciA
0 -4-BitNo.
I.--control Register A
Status of interrupt requests originating at CA2 logic
Status of interrupt requests originating at CA 1 logic
ct
all
w
Z
0:
0
III
en
0
~
ct
ct
c
@
Both interrupt requests are
J::
output via IROB
,t
6
I I I
5
4
3
0 ....--BitNo.
~ Control Register B
Status of interrupt requests originating at CB2 logic
Status of interrupt requests originating at CB 1 logic
The remaining six control bits may be written into or read: they define the way in which the I/O port will operate.
Figures 9-22 and 9-23 describe the Control register interpretation for I/O Ports A and B respectively: since the two Control register interpretations are very similar. the points of difference are shaded so that they are easy to spot.
Let us clarify the functions enabled by the two Control registers.
Each I/O port has its own interrupt request signal: IROA for I/O Port A and IROB for I/O Port B.
Each interrupt request signal has two separate sets of request logic. based on an interrupt request
originating with a CA 1/CB 1 signal transition. or a CA2/CB2 signal transition.
.
MC6820
INTERRUPT
LOGIC
Control register bit 0 enables or disables IROA/IROB. based on signal CA 1/CB 1 transitions only. Ouite independently.
Control register bit 3 enables or disables IROA/IROB based on transitions of signal CA2/CB2. However. Control register
bit 3 has an alternative interpretation: the one we have just described only applies if Control register bit 5 is O.
Interrupt requests are triggered by the "active transitions" of a control signal. The active transitions of control signals
may be a high-to-Iow. or a low-to-high transition: For CA1/CB1. the active transition is selected by Control register bit
1. For CA2/CB2. the active transition is selected by Control register bitA. but only if Control register bit 5 is O.
Irrespective of whether interrupt request signals IROA and IROB have been enabled or disabled. Control register bits 6
and 7 will report the interrupt request as a status. that is to say. if a condition exists where CA 1ICB 1 makes an interrupt
requesting active transition. then Control register bit 7 will be set to 1. Similarly. if control signal CA2/CB2 makes an interrupt requesting transition. then Control register bit 6 will be set to 1. Once set. Control register bits 6 and 7 will remain set until a Read operation addresses the Control register: at that time Control register bits 6 and 7 will both be
reset to O. while other bits of the Control register are left unaltered.
If Control register bit 5 is 1. then Control register bits 4 and 3 take on a second interpretation. If Control register bits 5
and 4 are both 1. then control signal CA2/CB2 will be output at all times with the level of control bit 3.
9-51
4
6
o
2
......-BitNo.
I/O Port A Control register
.......- - - 0 Disable IRMl
1 Enable IRQA1
' - - - - - - 0 Set bit 7 andIR%l(if enabled) on high-to-lowC~ltransition
1 Set bit 7 and IRQA 1 (if enabled) on low-to-high .CA 1.transition
1--_ _ _ _ _ _ 0 When RSO, RS1 =OO.select I/O PortA/Direction register
1 When RSO, RS1 =.00 select I/O Porth.Data buffer
o Disable IRM2
i:~~iig2~~:;g:::
}
B;t
00 Selectinp~t interrupt handshaking
}
01 Sele~tinputprogrammed handshaking
1X SetCA2to X
1--_ _ _ _ _ _ _ _ _ _ _ _ _
5~ 0
Bit 5 = 1
Status oflRQA2
' - - - - - - - - - - - - - - - - - Status of IRM 1
Figure 9-22. I/O Port A Control Register Interpretation
4
6
o
3
I I I I I I I I
.~~ ~~
~~
~
~
~~ ~
.......-BitNo.
t
I/O Port B Control register
' - - - - - 0 DisablelROB t
1 Enable IROB1
' - - - - - - - 0 Set bit 7 andl~()~l(if enabled) on high-to-low<::i3ltransition
1 Set bit 7 andlROB1 (if enabled) on low-to-highCBltransition
' - - - - - - - - 0 When RSO, RS1 =Cli select I/O Port~Direction register
1 When RSO, RS1 =.01 select I/O PortBData buffer
!:~~~:tl~~~~~:g::: } ~
B" 5
_I--------1..~ 00 Selecto~t~~t. interrupt handshaking
1---4II......
01 Sele.c. t . . . . o... ~.tpytProgrammed handshaking
1X SetC82 to X
' - - - - - - - - - - - - - - - Status oflROB2
Status oflRClB1
1--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Figure 9-23. I/O Port'S Control Register Interpretation
9-52 '
}
Bit 5
0 -
= 1~
If Control register bits 5 and 4 are 1 and 0 respoctively, thon Control rogistor bit 3
specifies an automatic handshaking signal sequenco. Let us doscribo these signal sequences.
MC6820
AUTOMATIC
HANDSHAKING
Input interrupt handshaking applies to I/O Port A only, and may be iIIustratod as follows:
cw
E
IX:
R/W
~
IX:
o0..
o
o
~
enw
----'
DO - 02
~
g
CI)
CI)
CA2
oct
011
w
Z
CAl
IX:
o
Active
CD
CI)
CAl
~
Transition
o
oct
C
oct
@
CA2 is output on the trailing edge of E. after the CPU has read the contents of the liD Port A data bllffer; this tells external logic that previously input data has been read and new data may now be input. External logic· receives CA2 low.
and upon transmitting new data to liD Port A. must cause an active interrupt requesting transition of input control signal CA 1. What constitutes an active transition will be determined by liD Port A Control register bit 1. When external
logic requests an interrupt via signal CA 1. CA2 will be set high again.
Input programmed handshaking applies only to I/O Port A, and may be illustrated as follows:
E
cso·csl-CSi
A/iN
DO - 07
CA2
Once again control signal CA2 is output low when liD Port A data buffer contents are read by the CPU. This tells external logic that previously input data has been read and new data may be input. External logic does not have to identify
newly transmitted data with an interrupt request; rather. CA2 will be resetas soon as the MC6820 is deselected. Using
programmed handshaking. external logic may use the CA2 low pulseas a Write strobe. causing new data to be input to
liD Port A.
9-53
Output interrupt handshaking applies only to 1/0 Port B, and may be illustrated as follows:
R/W
DO - 07
~
eB2
eBl
In this instance. control signal CB2 is outpUt Iowan the high-to-Iow transition of E following a Write to I/O Port A Data
buffer. In other words. CB2 tells external logic that new data has been output to.I/O Port B and is ready to be read. Externallogic tells the MC6B20 that 110 Port B contents have been read by making an interrupt requesting active transition of the CB 1 signal. Once again. I/O Port B Control register bit 1 will determine what constitutes an active transition
of the CB 1 signal. Program logic can use an interrupt to branch to a program which outputs the next byte of data to I/O
Port B.
Output programmed handshaking applies only to 1/0 Port B, and may be illustrated as follows:
CSO ·cs 1-CS2
R/W
DO - 07
eB2
CB2 makes a high-to-Iow transition when data is written into the I/O Port B data buffer. just as occurred with output interrupt handshaking. However. CB2 will automatically be set to 1 as soon as the MC6B20 is deselected. External logic
can use the CB2 low pulse asa strobe. causing it to read the contents of I/O Port B.
Many other handshaking protocols may be created under program control. The four automatic protocols described
above are simply four situations which can be specified. and which will subsequently occur without further program intervention. But remember. you can modify the level of control signal CA2/CB2 any time by outputting a Control code
with bits 5 and 4 both set to 1: CA2/CB2 will then take the level of Control code bit 3. You can also determine the conditions which will cause an interrupt request as a result of any control signal transition.
9-54
THE MC6850 ASYNCHRONOUS COMMUNICATIONS
INTERFACE ADAPTER (ACIA)
c
w
~
a:
oQ.
a:
o
u
The MC6800 microcomputer system provides separate devices supporting synchronous .and asynchronous
serial I/O. The MC6850, which we are about to describe, provides asynchronous serial 110. The MC6852, which we will
describe next. supports synchronous serial liD.
Taken together; the MC6850 and MC6852 devices are approximately equivalent to the 8251 USART. The 8251
is a general purpose 8080 device that can be used with a variety of microcomputers. Refer to Volume 3 for a description of 8251' s.
~
Figure 9-24 illustrates that part of our general microcomputer system logic which is provided by the MC6850
and MC6852 devices.
l-
Having separate synchronous and asynchronous serial I/O devices has advantages and disadvantages, when
compared to the 8251 USART which provides both sets of logic on a single device. In a microcomputer system that
uses either asynchronous or synchronous serial liD, but not both, separate devices are better, because they come in
smaller packages and require less space on a PC card. If your microcomputer system uses both synchronous and
asynchronous serial liD, then a single device will be more economical.
enw
e(
oo
CI)
CI)
e(
all
w
a:
Z
o
III
CI)
o
:!:
e(
ce(
@
When comparing the MC6850 with tile 8251, you will find that the 8251 offers more asynchronous serial I/O
options, but it is harder to program. In fact. you must program the 8251 defensively: 8251 statuses and control signals simply prompt your program logic, but actually do nothing within the 8251 USART itself. When using the MC6850
and MC685,2, that is not the case: these two devices are much easier to program.
The MC6850 ACIA is packaged as a 24-pin DIP. It is fabricated using N-channel silicon gate technology.
A single +5V power supply is required.
In the discussion of the MC6850 that follows we will frequently refer to the 8251 USART description in Volume 3. If
you are unfamiliar with asynchronous sl:trial I/O devices in general, see Chapter 5 of Volume 1, then read the
description of the 8251 USART which is given in Volume 3.
THE MC6850 ACIA PINS AND SIGNALS
MC6850 ACIA pins and signals are illustrated in Figure 9-25. Signals may be divided into the following four
categories:
.
1)
2)
3)
4)
CPU interface and control sign~is
Serial inpLit
Serial output
Modem control
We will first consider CPU interface and control signals.
DO - 07 constitutes an 8-bit bidiroctional Data Bus connecting the MC6850 with the CPU.
When data is output to the MC6850 by the CPU, either a byte of parallel data or a Control code will be transmitted.
A byte of paraliel data will be serialized and transmitted according to the protocol which has been selected under program control.
Either data or status may be input from the MC6850 ACIA to the CPU via the Data Bus. Data consists of an 8-bit parallel
data unit extracted from the serial input data stream. Status consists of the contents of the ACIA Status register.
The Status register of the MC6850 ACIA is very important. because the MC6850 uses status flags where the 8251
uses control signals to monitor serial data transfer logic.
The MC6850 ACIA is accessed~the CPU as two memory locations. MC6850 select logic consists of the three chip
select signals CSO, CS1 and CS2; manufacturers' literature also refers to the enable signal E as being part of the
chip select logic; however, E is more accurately visualized as an internal synchronization signal.
For the MC6850 ACIA to be selected, CSO and CS1 must be input high while CS2 is simultaneously input low. Once
selected, the register select signal RS determines which of the two addressable locations within the MC6850
ACIA will be accessed. When RS is low, a Read will access the ACIA Status register, while a Write will access the
ACIA Control register. When RS is high, ACIA data buffers will be addressed.
While the MC6850 ACIA is selected, internal logic is synchronized on the trailing edge of the E signal. E is a standard
output of the various MC6870 clock devices used to synchronize support logic throughout an MC6800 microcorylputer
system.
9-55
Clock Logic
,..
~
Arithmetic ~nd
Logic Unit
Accumulator
Registerisl'
Data Counterisl
Stack Pointer
Program Counter
System Bus
I/O Ports
Interface Logic
Interface Logic
Programmable
Timers
Read Only
Memory
I/O Ports
Figure 9-24. Logic of the MC6850 ACIA or MC6852 SSDA Devices
RIW is the control input which determines whether a Read or Write operation is In Ilrogress. When Riw is high.
the CPU is reading data out of the MC6850. When R/W is low. the CPU is writing data to the MC6850.
The MC6850 has no RESET input; a Control code is used as a master Reset. When power is first detected within
the MC6850. internal logic automatically initiates a Reset sequence. Subsequently. before initializing the MC6850 for
serial data transfer you should again reset the device by inputting a Reset Control code.
9':'56
VS.S--~
RxD--"'~
RxCLK - -.....
TxCLK - -.....
c
RTs~-~
w
~
a:
o0.
TxD ....~--t
t---I
rna ....
a:
CSO - -.....
CS2-~~
o
(J
~
CS1 - -.......
iii
RS ----!. .
w
~
VDD
g
en
en
oCt
o1J
2
3
4
5
6
7
8
9
10
11
12
D5
D4
D6
D7
E
R/W
Type
DO - D7
Tristate, bidirectional
Input
Input
Input
Input
Input
Register Select
R/W
Read/Write control
Transmit Oock
Transmit Data
Receive Oock
C
TxCLK
TxD
@
RxCLK
RxD
oCt
17
16
15
14
13
Description
E
~
D3
Data Bus to CPU
Chip Select
Internal synchronization
RS
oCt
19
Pin Name
en
o
DO
D2
MC6850
ACIA
CSO, CS1, CS2
ocg
0C5
D1
w
a:
Z
CTS
24
23
22
Output
Input
Receive Data
Clear To Send
Request To Send
CTS
RTS
5a5
iRQ
Data Carrier Detect
Interrupt request
VDD, Vss
Power and Ground
Input
Input
Output
Input
Output
Figure 9-25. MC6850 ACIA Signals and Pin Assignments
""C6850 DATA TRANSFER AND CONTROL OPERATIONS
There are a number of buffers through which data flows in and out of the MC6850 ACIA. These data flows may
be illustrated as follows:
I
Parallel
Data In
Parallel
Control
Code
Data Out
Status
Control/Status
Address
Data Address
Buffer
RA
Buffer
TA
Register
Register
RB
TB
Serial
data
input
Serial
data
output
Control
Register
9-57
Status
Register
Buffer names in the illustration above conform with terminology used for the 8251 in Volume 3; this will make
it easier. for you to compare the two devices.
Like the 8251. the MC6850 has double buffered serial input and output logic. As described for the 8251. while a data
byte is being serialized and output from Buffer TB, you must simultaneously write the next data byte to Buffer
TA. Also, while a serial data byte is being assembled in Buffer RB, you must read the previously assenibled data
byte out of Buffer RA.
Unlike the 8251. the MC6850 has a separate Control register. You can therefore write Control codes and read status
at any time without fear of scrambling data waiting to be transmitted.
.
As compared to the 8251. the MC6850 has very elementary serial I/O logic.
TxCLK is an externally provided clock signal which times the serial, asynchronous data
.
stream which is output via TxD.
Similarly, RxCLK is an externally provided clock signal which times the serial, asynchronous
data stream which is input via RxD.
MC6850
SERIAL I/O
DATA AND
CONTROL
SIGNALS
There are no control signals accompanying serial I/O data; rather. a single interrupt request
signal is shared by all transmit and receive conditions. You have to write an interrupt service routine which reads the
contents of the MC6850 Status register. and thus determine which one of the many serial data transfer interrupt request conditioris has occurred.
The fact that you must execute instructions to duplicate the logic which the 8251 provides with its TxRDY. RxRDY and
TxE signals will certainly make an MC6800 microcomputer system less attractive in an application that makes hi3avy
use of serial I/O. Conversely. the MC6800 system will appear more attractive in simple applications. since you have less
interface circuitry to be concerned with.
.
Three modem control signals are provided: Clear To Send (CTS)' Request To Send (RTS),
and Data Carrier Detect (DCD). CTS and RTS are identical to the signals with the same names
described in Volume 1. Chapter 5 for the general case. and in Volume 3 for the 8251.
RTS is output by the MC6850 under program control when the MC6850 is ready to transmit data.
A full duplex line turns RTS around and sends it back as CTS; a half duplex line returns CTS after
line turnaround has occurred.
,...---...
MC6850
MODEM
CONTROL
SIGNALS
The MC6850 has no bata Set Ready (DSR) signal; this is the signal which many serial I/O devices tra~~mit to modems
or any external receiving logic when ready to commence with serial data communications. When using an MC6850.
RTS must serve double duty. additionally substituting for DSR.
Even though the MC6850 has only three of the normal four control signals, these signals work Hard within the
MC6850.
The DCD input must be low for serial transmit logic within the MC6850 to be enabled. This is true also of the equivalent
8251 DSR signal: however. if the DCD signal makes a low-to-high transition. the MC6850 will generate an interrupt request. thus effectively halting serial data output. A low-to-high DCD transition implies that the modem has. for sOr1)e
reason. disconnected itself; any further data transfer will be lost. In the case of the 8251. if a modem disconnects itself
and DSR goes high. this cOr;Jdition will be reflected in a Status register flag. but unless the CPU executes instructions to
read the Status register and test for this condition. the 8251 will continue transmitting data - even though the receiving end is dead.
The MC6850 uses CTS high to prevent the Status register from reporting a "Transmit Register Empty" condition. The
MC6800 CPU determines when to send another byte of data to the MC6850 by testing the Status register. and looking
for a "Transmit Register Empty" condition. If this condition never gets reported. no data will ever be uselessly transmitted. Contrast this with 8251 logic. where a misprogrammed 8251 can and will continue to transmit data after CTS has
gone high.
9-58
· MC6850 ACIA CONTROL CODES AND STATUS FLAGS
Let us now examine the way in which the MC6850 Control and Status registers are interpreted.
Here is the Control register interpretation:
7
cw
6
4
3
o
----......
~BitNo.
Control register
~
o
Il.
a:
a:
o(J
~
enw
I-
ct
U
L..-_ _ _
00 Isosynchronous,+l clock rate
01 -;-16 clock rate
10-:-64 clock rate
11 Master Reset
1 . . . - - - - - - - - - 0 0 0 7 bits, even parity, 2 stop bits
o
001 7 bits, odd parity, 2 stop bits
ct
D!I
010 7 bits, even parity, 1 stop bit
011 7 bits, odd parity, 1 stop bit
w
100 8 bits, no parity, 2 stop bits
(I)
(I)
Z
a:
oa:I
(I)
o
~
ct
c
ct
@
101 8 bits, no parity, 1 stop bit
110 8 bits, even parity, 1 stop bit
111 8 bits, odd parity, 1 stop bit
L-------------OO
01
10
11
RTS low, disable transmit interrupt logic
FITS low, enable transmit interrupt logic
RTS high,·disable transmit interrupt logic
FiTS low, disable transmit interrupt logic, output
break level
......--------------0 Disable receive interrupt logic
1 Enable receive interrupt logic
The CPU neither sends nor receives the parity bit. The MC6850 adds the parity bit to transmitted data and strips or
resets the parity bit in received data before it goes to the CPU.
Control register bits 0 and 1 determine the data transfer clock rate. Recall that serial data is usually transmitted or
received at 1116th or 1/64th of the clock rate, TxCLK or RxCLK. Transferring serial data at the exact clock rate is refer..
red 'to as isosynchronous data transfer.
The master reset Control code substitutes for the normal reset input signal. which the
MC6850 lacks. A master reset clears all MC6850 registers, with the exception of Status register
bit 3, which is unaltered.
MC6850
SYSTEM
RESET
Control register bits 2,3 and 4 identify data bit. stop bit and parity options. Compared to the 8251,
MC6850 options are somewhat limited: five and six data bits are not provided and you cannot select 1.5 stop bits.
Control register bits 5 and 6 are transmit logic control bits. Control register bit 7 is a receive
logic control bit.
Transmit logic consists of the RTS modem control and various transmit conditions that can cause
an interrupt request.
MC6850
SERIAL 1/0
CONTROL
LOGIC
Receive control logic consists of various receive conditions that can cause an interrupt request.
Interrupt logic of the MC6850 is an integral part of status logic. Conditions that can result in
an interrupt request are therefore summarized below along with a definition of Status
register bits.'A "r is placed in those bit positions that can result in an interrupt request from
transmit logic. An "R". is placed in those bit positions that can result in an interrupt request from
receive logic. Status register bit pos!tions that have neither a "r nor an "R" identify conditions that do not result in interrupt requests.
In those bit positions containing a "r or an "R", a 1 causes an interrupt request to occur. OCO (bit 3) is an exception:
here it is the transition from 0 to 1 that causes an interrupt request. In each case, the interrupt request will only occur if
interrupt logic has been enabled. If you look back at the Control register, you will see that transmit and receive interrupt
logic can be enabled and disabled separately. Control register bits 5 and 6 determine whether transmit interrupt logic is
enabled, while Control register bit 7 determines whether receive interrupt logic is enabled, Note that the condition of
Status register bit 3 can also disable a TORE interrupt request.
9-59
When an interrupt request occurs. the requesting condition is clearedin various ways depending upon where the request originated.
. '
'.
.
..
.' .
.
An RDRF
or if a reset Control code is output.
'. interrupt requ~st will be cleared if the CPU re~dsdata fro~ the .MC6850.
,
..
.
'
A TORE interrupt request will be cleared by writing data to the MC6850 or by issuing a reset Control code.
Interrupts requested by DCD or OVRN are cleared by reading the Status register after the error condition has occurred.
and then reading the Data register. A Master Reset will also clear these interrupt requests.
Let us now take a closer look at the Status register itself. This is how register bits are interpreted:
Status register
'-----RDRF. Receive Data register full
'------TDRE. Transmit Data register empty
L...-------DCD. Data Carrier Detect signal status
L-----'---'---CTS. Clear To Sendsign&1 status
.......- - - - - - - - - · F E . Framing Error
.......- - - - - - - - - - - O V R N . Receiver overrun error
L . . . - - - - - - - - - - - - - P E . Parity Error
L - - - - - - - - - - - - - - - - I R Q . Interrupt request
(1 in a bit' position represents "true" condition for bits 7. 6,. 5. 4;'1 and 0.1
Status register bit 0, Receive Data Register Full, goes to 1 when a byte of assembled data is transferred from
Receive register RB to Receive register RA. Bit 0 is cleared as soon as the CPU reads the contents of Register RA. The
DCD modem control signal. when high. forces Status register bit 0 to stay low so that the CpU 'will not attempt to read
nonexistent data.
.
.
°
Status register bit 1, Transmit Data Register Empty~ goes from to .1 as soon as data is transferred from .Register TA
data' into RegisterTA.
'. '.
. to Register TB. This bit is reset to 0 as soon as the CPU writes another bit
of
Status register bit 2, Data Carrier Detect, is used by the MC6800 to determine the status of external logic communicating with the MC6850. When DCD makes a low-to-high transition. an interrupt request is generated and Status
register bit 2 goes high. Bit 2 remains high until the Status register contents are read by the CPU after DCD has gone
low again. A Reset will also set Status register bit 2 to O. If the CPU reads the Status register while DCD .is' high. then
subsequently Status register bit 2 will track the DCD level; however. another interrupt will not be requested. It is the
. actuallow-to-high transition of the DCD signal which causes an interrupt request. not a high level of Status register bit
2.
.
. . . .
' ..
Status register bit 3, Clear To Send, tracks the CTS modem control input. MC6850 logic uses Status register bit 3 to
inhibit serial data transfer when external receiving logic is not ready to receive the serial data. When CTS is high.
Status register bit 1 will be' held low. A TORE interrupt request cannot occur. and program logic which :tests Status
register bit 1 will not transmit another data byte to Register TA until it detects a 1 in Status register bit 1. Thus. for as
long as'CTS is high. serial transmit logic will be inhibited. '
Status register bits'4, 5 and 6 report framing, overrun and parity errors, respectively. Recall that ~ framing error is
reported when start 'and sto'p bits do not correctly frame a data character; a fra'ming error refers to the data byte currently waiting to be read out of RA. An overrun error is reported if the CPU does not read Register RA contents before a
byte of data is transferred from Register RB to Register RA. A parity error is reported if parity has been:enabled by Control register bits 2. 3 and 4. but the wrong parity is detected,
'
A framing or parity error is automatically reset as soon as the erroneous data is read out of Register RA. or is overwrit~n.
'
An overrun error is cleared by reading data from the t'0C6850,
9-60
Status register bit 7, Interrupt Request, is 1 whenever there is an unacknowledged interrupt request pending at the
MC6850 device. One method that an MC6800 will use to determine the source of an interrupt request is to read device
Status registers. If the MC6850 has no other method of identifying itself to the CPU when requesting an interrupt. then
the CPU determines whether the MC6850 was the requesting device by reading the contents of the MC6850 Status
register and testing the condition of bit 7.
c
W
~
a:
oQ.
a:
o
CJ
:!::
en
'W
~
g
CI)
CI)
ct
o!I
w
Z
a:
o
In
CI)
o
~
THE MC6852 SYNCHRONOUS SERIAL DATA
ADAPTER (SSDA)
The MC6852 SSDA provides MC6800 microcomputer systems with synchronous serial I/O logic.
The MC6852 SSDA may be looked upon as a companion device to the MC6850 ACIA which we have just described. Taken together, these two devices provide MC6800 microcomputer systems with total serial I/O
capability.
Figure 9-24 illustrates that 'part of our general microcomputer system logic which is provided by the MC6850
and MC6852 devices.
The most striking difference between the MC6850 and the MC6852 is their respective capabilities. Whereas
the MC6850 offers fewer asynchronous serial I/O options than the 8251 USART (described in Volume 3), the
MC6852 offers significantly more synchronous serial I/O options. Moreover, the MC6852 provides additional
serial I/O options without the penalty of defensive programming which is demanded by the 8251 USART
ct'
The MC6852 SSDA is packaged as a 24-pin DIP. It is fabricated using N-channel silicon gate technology.
ct
A single +5V power supply is required.
C
@
In the discussion of the MC6852 that follows, we will frequently refer to the 8251",U5ART description given in
Volume 3. If you are unfamiliar with synchronous serial I/O devices in general, see Chapter 5 of Volume 1, then
read the description of the'8251 USART which is given in Volume 3.
MC6852 SSDA PINS AND SIGNALS
MC6852 SSDA pins and signals are illustrated in Figure 9-26. Most of these signals are identical to those illustrated in Figure 9-25 for the MC6850, therefore we will only describe four signals which differ.
The MC6852 has a master Reset input, which. when input low. logically resets the MC6852. We will define how a
Reset occurs after describing the MC6852 controls and status flags affected by a Reset.
The Data Carrier Detect (DCD) modem control inputperforms two functions. The normal function of DCD is to
serve as a control signal transmitted by an external data carrier which is ready to transmit serial data to the MC6852
SSDA. Both the high-to-Iow and the low-to-high transitions of DCD have additional significance. The high-to-Iow signal transition can optionally be used as an external synchronization indicator. while a subsequent low-to-high transition is an error indicator. signaling an unexpected disconnect:
RxCLK
RxD
Rising edge of RxCLK following falling edge of
0C0 can serve as external synchronization. marking the start of data bits incoming on RxD.
An untimely low-to-high transition of DCD
means the transmitter got disconnected unexpectedly.
Using the high-to-Iow DCD pulse for external synchronization is a programmable option. The error condition reported if
DCD makes an unexpected low-to-high transition is not a programmable option: it is a permanent part'of the MC6852
error detection logic.
9-61
Vss
RxD
RxCLK
TxCLK
SM/DTR
TxD
iiill
TUF
'RESET
CS
RS
VDD
..
.-..
p
-
--- ..
...-.
1
2
3
4
5
6
7
8
9
10
11
12
MC6852
SSDA
24
23
22
21
20
19
18
17
16
15
14
13
--------..
--
---..
a=s
..
Dc5
.....
Dl
D2
..p
..
..
p
.....
p
DO
D3
D4
D5
D6
D7
E
R/Vi
Pin Name
Description
Type
DO - D7
Data Bus to CPU
Cs"
Chip Select
Internal synchronization
Tristate. bidirectional
Input
Input'
E
Register Select
Read1Write control
Transmit Oock
RS
R/W
TxCLK
TxD
RxCLK
RxD
iRQ
Transmit Data
Receive Oock
Receive Data
Master Reset
Data Carrier Detect
Clear To Send
Sync Match/Data Terminal Ready
Transmitter Underflow
Interrupt request
VDD. Vss
Power and Ground
REsET
DcD
ffi
SM/DTR
TUF
Input
Input
Input
Output
Input
Input
Input
Input
Input
Output
Output
Output
Figure 9-26. MC6852 SSDA Signals and Pin Assignments
Clear To Send (CTS) is the modem control signal which is normally input by external receiving logiC. indicating that
the MC6852 may begin transmitting serial data. like DCD. the CTS high-to-Iow transition can be used to synchronize
the beginning of data transmission: the low-to-high transition of CTS is an error indicator. Once again. using the highto-low CTS pulse to provide external transmit synchronization is a programmable option. However. an untimely low-tobi9..tJ transition of CTS is an error indicator only if internal synchronization is being used. Therefore. if the high-to-Iow
CTS transition is active. then the low-to-high subsequent transition must be inactive: conversely. if the high-to-Iow
CTS transition is inactive. then a subsequent low-to-high transition will be active. This is because the high-to-Iow transition. if active. means that external synchronization has been selected - in which case the disconnect error logic is inactive.
Note that whereas the CTS signal low-to-high transition is only active during internal synchronization operations. the
DCD low-to-high transition is active at all times, This means that external logic disconnecting itself during a serial
transmit operation will only cause an error to be indicated if external synchronization has been selected. On the
other hand, during a serial receive operation, if external logic disconnects itself, an error will be indicated
whether internal or external synchronization has been selected.
Since DCD and CTS can both be used for external synchronization. as we might expect. DTR also serves a double
function. Under normal circumstances. DTR will be output low by the MC6852 when it is ready either to transmit. or to
receive serial data. If the MC6852 has output DTR low before transmitting serial data. then the receiving data carrier
will turn DTR around and send back a high-to-Iow DCD pulse as we illustrated. If you have selected external synchronization under program control. then you can additionally program DTR to output a single high pulse as soon as
9-62
synchronization has been detected. This may be illustrated as follows:
XC6852 wants to
Q
Data carrier says it is
XC6852 says it has detected
ready to transmit data
external synchronization
SM/DTR
w
!ta:
oD..
a:
o
o
~
enw
RxCLK
le:(
(3
o
RxD
U)
U)
e:(
c1:I
Rising edge of RxCLK following falling edge of
An untimely low-to-high transition of DCD
Z
a:'
DCD can serve as extemal synchronization, mark-
means the transmitter got disconnected unex-
III
ing the start of data bits incoming on RxD.
pectedly.
w
o
U)
o
~
e:(
Q
e:(
@
Because DTR also acts as a Sync Match acknowledge. it is referred to as SM/DTR.
When the MC6852 transmits serial data, it transmits the least significant bit first. The
MC6852 also expects to receive the least significant bit first when receiving serial data.
MC6852
SERIALIZATION
SEQUENCE
Transmitter Underflow (TUF) is the fourth unique MC6852 signal. This signal is output when an underflow condition occurs during serial synchronous data transmission. Recall.that during serial synchronous data transmission. if
serial transmit logic finds no data ready to be output. then in order to maintain synchronization. a break character or a
Sync characterwill be output. A break character is a continuous high level. equivalent to FF16. A Sync character will
have some predefined binary pattern. Providing you have programmed the MC6852 to output Sync characters when
no valid data is ready for serial transmission. the MC6852 will precede each Sync character with a high TUF pulse. External receive logic can use a high TUF pu Ise as an indicator that the next received character is a Sync and can be discarded.
MC6852 DATA TRANSFER AND CONTROL OPERATIONS
Like the MC6850, the MC6852 SSDA is accessed via two memory addr~sses; however, these two memory addresses are shared by seven locations within the MC6852, which results in a complex set of data flows, as illustrated in Figure 9-27.
These are the seven addressable locations of the MC6852:
1)
2)
3)
4)
5. 6. and 7)
Data input - a read only location.
Data output - a write only location.
Status register - a read only location.
Sync Code register - a write only location.
Three Control registers -
all are write only locations.
Data input and data output are self-evident apart from being triple buffered - and we will discuss the implications of
triple buffering shortly - there is nothing unusual about MC6852 data input or output.
The Status register is absolutely standard.
The three 8-bit Control registers provide the MC6852 with a substantial variety of control options. as compared to
the MC6850. which was somewhat limited in this respect.
The Sync Code register stores the 8-bit synchronization character code: this is the character which must appear at
the beginning of any synchronous serial data stream and may also be transmitted when data is unavailable during a
normal transmit sequence.
9-63
Status
Out
Write
Data
Control
Code 1
Parallel
Data In
Higher Address
Lower Address'
Control
Code 1
5
6
Status
X
X
4
3
2
0
Buffer
RA
II
...
'-v-
-
J-~--------" XX=OO
Byte Received
Buffer
RT
Control
Code 2
Byte Received
-·
++
·· XX~I~
,+
Control
Code 3
Buffer
RB
Sync
Code
Shift
Register
Byte to transmit
_...:.._ _...z.._
Buffer
TT
Byte to transmit
Buffer
TB
. Shift
Register
Figure 9-27. Data Flows Within an MC6852 SSDA
9-64
Serial
Data
Output
Serial
Data
input
cw
!ia:
o
Of the seven addressable locations. two are read only. while five are write only. Each memory address can ac::cess
two locations, providing one is exclusively read only, while the other is exclusively write only. Since there are
just two read only locations. one is assigned to each memory address. Since there are five write only Idcations. one
(Control Code 1) is assigned to the lower address. which leaves four assigned to the higher address; the two high-order
bits of Control Code 1 are used to select one of the four write only locations assigned to the higher address. While this
may look like a complex scheme. in reality it is not: all it means is that you have to observe a rigid programming sequence when using an MC6852. In fact. understanding the MC6852 depends completely on understanding the Control
and Status registers; therefore we wiil describe these registers first. then look at data transfer sequences.
a:
MC6852 STATUS REGISTER
u
The MC6862 Status register may be illustrated as follows:
D.
o
~
en
w
!i
g
en
en
ct
.a
MC6852 Status register
w
Z
a:
o
III
en
o
:E
ct
c
ct
@
' - - - - - RDA. Receive data available; read RA
L - - - - - T D A . Transmit data register available; write to TA
' - - - - - - - - DC~. Data Carrier Detect signal status
L-----....;.-.--CTS. Clear To Send signal status
' - - - - - - - - - - - T U F . Transmitter' 'Und~rflow error indicator
L - - - - - - - - - - - O V R N . Overrun error indicator
L -_ _ _ _ _ _ _ _ _ _ _ _
'
PE. Parity Error indicator
L - - - - - - - - - - - - - - - I R Q . Interrupt request status
(1 in a bit position represents "true" condition for bits 7, 6. 5, 4. 1 and 0.)
Conditions that may generate interrupts are marked with letters In appropriate Status, register bit positions. An
interrupt request initiated by an error condition is represented by the letter E. Interrupt requests originating at transmit
.
or receive logic are represented by the letters T and R. respectively.
Status register bit 0 (RDA) indicates when the MC6862 Status register has a byte of data
ready to be read. Similarly Status register bit 1 (TDA) indicates when the MC6862 is ready
to receive another byte of data which will be output as a serial data stream.
As indicated in Figure 9-27. MC6852 transmit and receive logic is triple buffered. This differs from
the MC6850 which uses double buffering .
MC6852
TRIPLE
DATA
BUFFERS
. You Ccln use the triple buffering of the MC6862 in one of two ways which you select using appropriate Control
register codes.
You can select a single byte option, in which case as soon as a single byte of data can be written to Buffer TA or read
from Buffer RA. the appropriate status flag will be set -and if interrupts are enabled. an interrupt request will be made
to the CPU. The program controlling MC6852 operation must respond by reading or writing a single byte of data. A
byte of data written to Buffer TA will automatically be rippled through Buffer TT to Buffer TB. whence it will output as a
serial data stream. Data arriving at Buffer RB will be rippled through Buffer RT to Buffer RA. whence it must be read by
the CPU.
if you select the two byte option under program control, then no status flags will be set. nor will interrupt requests
occur untiLtwo of the three 8-bit buffers are empty. Thus. status bit 0 will be set and a receive interrupt request will occur when Buffers RA and RT are both full. Under program control you must. at this time. read two bytes of data. So long
as a Single pulse of the timing E signal separates the two read commands. MC6852 logic will transfer Buffer RT contents to Buffer RA so that the second read accesses what had been in Buffer RT. In fact. you should read RA contents.
then status. then RA contents again. If there are errors associated with the data byte in RT. they will not be reported until RT contents have been transferred to RA.
9-65
·
.
When using the tWo byte option with transmit logic, Status register bit 1 will not be set and the appropriate interrupt
request will not occur until Buffers TA and TT-are both empty. At this time the executing program must write two bytes
of data to the higher MC6852 address, while Control code 1, bits 7 and 6 are both 1. The first byte of data written to the
higher MC6852 addr'e.ss will store dat~ in BufferTf.. The next pulse of the E clock will transfer the content§ df BufferTA
to Buffer TT. The second write will again load Buffer TA whose previous contents are now in Buffer TT,
Status register bits 2 an~ 3 are associ&t,ed with signals DCDand CTS, respectively. If DCD or CTS makes a low-tohigh transition, then Its corresponding Status register bit will iatch high - that is, it will maintain a level of 1 until it is
reset by the CPU. Once bit ,2 (or 3) has. been reset. it will track DCD (or CTS) until the ne'xt low-to-high transition.
Note that in Sync mode; if Status register bit 3 is 1, then Status register bit 1 will be held at
MC6852 suppresses subsequent transmit iogic.
0; this is how the
Status register bits 4, 5 and 6 indicate Underflow, Overrun or Parity errors, respectively.
An Underflow error occurs when transmit logiC; does not have a byte of data ready to transmit and has to insert a Sync
character. The Underflow error is reported just before the SyhC character is transmitted. When Status register bit 4 is
set. the TUF signal is simultaneously pulsed;high.
An Overrun error occurs when a byte of data is written into BuffEd' RA before prior buffer contents have been read. An
Overrun error therefore indicates that a single byte of data has been lost.
A Parity error indicates that a Parity option has been selected, but the wrohg Parity was detected for the data byte currently in Buffer RA.
These three error conditions are completely standard;'however, the way they are handled within the MC6852
is not standard. When anyone of these error conditions occurs, the appropriate Status register bit will be set and
simultaneously an interrupt request will be generated, providing you have ehabled these three error interrupts.
An error status is not cleared automatically. To clear Status register bits 4,5 or 6, you have to read Status register contents, then issue an appropriate Control code to reset the selected bit.
We can summarize the fUnctions performedtlY MC6852 Status register bits by looking at the manner in which
each bit is set or reset; then we can separately examine the way in which interrupt logic is assbciated with
each status bit position.
Table 9-6 summarizes the conditions which cause each bit to be set and then reset. Table 9-7 summarizes interrupt requests associated with each status bit, indicating the way the interrupt is enabled or disabled and the way in
which an interrupt request occurs. You wili find Table 9-7 following the three Control registers' description, because interruptlogic is equally dependent upon the Status register's contents and the three Control registers' contents.
THE MC6852 CONTROL REGISTERS
Now 'consider the three MC6852 Control registers.
.
,
Control register 1 is normally the first to be ~ccessedand h'as to be written into in cirder to select any other write only
MC6852 location, Control register 1 format may be illustrated as fdllows:
6
4
3
2
o
+-=-Bit No.
r-~~~--~~~~~
MC6852 Contr~1 Register 1
'-----RxRS. Reset and inhibit receive logic
L..------TxRS. Reset and inhibit transmit logic
'--------STSYNC. Strip SYNC characters when detected
I...---------CLSYNC. Inhibit all SYNC character logic
" - - - - - - - - - - - T I E . Enable transmit data interrupts
' - - - - - - - - - - - - - R I E . Enable receive data interrupts
00 Select Control Code 2
01 Select contr,ol Code 3
10 Select Sync Code
11 Select Transmit Buffer TA
(1 in a bit position represents "true" condition for bits 5, 4, 3, 2, 1 and 0.)
9-66'
}
High address
write
. select
Control register 1, bits 0 and 1 reset and inhibit receive and transmit logic, respectively. You use these two Control reg!ster bits in order to disable transmit and receive logic while modifying the contents of any Control register or
the Sync register..
o
w
~
oQ.
a:
a:
o
u
~
iii
Control register 1, bits 0 and 1 are very impc;»rtant. It is easy to miss the significance of these two control bits. If
you alw<;lYs inhibit transmit and receive logic before modifying the contents of Control or Sync register? you can make
sure that spurious data is n'e)!er transmitted or received. The 8251 USART described in Volume 3. does flOt have any inhibit logic of this type; and as resl:llt. you have to adopt elaborate precautions to avoid data transmission errors.
a
While transmit and receive logic is inhibited. Status register bits 2 and 3 will still track the DCD and CTS signals;
however. no gat~ transfers will occur and interrupts associated with the inhibited logic will be disabled.
Using Control register 1. bits a and 1 to inhibit transmit and/or receive logic also affects Status register bits and inter-.
;
rupt requests. as summarized in Tables 9-6 and 9-7.
w
Table 9-6. MC6852 Status Register Bit Set/Reset Conditions
le:(
g
(I)
(I)
'"
e:(
all
w
RDA - B!t 0
Z
1)
(I)
o
~
TDA- Bit 1
e:(
o
RESET
If Control register 2 bit 2 is 1. when
Buffer RA is full.
if Control register 2 bit 2 is O. when
Buffers RA and RT are full.
1)
2)
Write 1 in Control regis~er 1 bit O.
Read Buffer RA contents.
1)
It' Contr.ol register ~ ~it 2 is 1 when
Buffer T A is empty. "
1)
2)
If Control register 2 bit 2 is 0 when
BHtfer:;; TA and TT are empty.
1 occurs in Status register bit 5.
together with 0 in Control register 3 bit O.
Write 1 in Control register 1 bit 1.
Write into Buffer TA.
2)
a:
oCD
..
SET
&TATUS
2)
3)
e:(
A low-ta-high DCD input transition when
Control register 1 bit 0 is O.
@
'Dc5 - Bit
2
1)
2)
A low-to-high CTS input transition when
Control regi~ter 1 bit 1 is O.
CTS - Bit 3
1)
2)
Head~tatus register. then read Buffer
RA. Status will subsequently go low
when DcDinput goes low.
Write 1 into Control register 1 bit O.
Status will subsequently go low when
i5CD input goes low.
Write 1 to Control register 3 bit 2.
Status will subsequently go low when
CTs input goes low.
Write 1 into Control register bit 1.
Status will subsequently go low when
ffi input goes low.
TUF - Bit 4
Underflow when Control register 3 bit 0 is 0
'and Control register 2 bit 6 is 1.
1)
2)
Buffer RT contents is transferred to Buffer
RA before Bu~fer RA contents is read by CPU.
1)
OVRN - Bit 5
Read'Status register. then read Buffer RA.
2)
Write 1 imo Control register 1 bit
PE- Bit 6
Parity error for data in RA'. providing Control
register 2 bits 3. 4 and 5 identify a parity option.
1)
2)
Read data out of Buffer RA.
Write'1 into Control register 1 bit O.
IR,Q- Bit 7
Any interrupt request occurs.
No active interrupt requests exist.
9-67
Write 1 into Control register 3 bit 3.
Write 1 into Control register 1 bit 1.
O.
Table 9-7. MC6852 Interrupt Summary
INT~RRUPT
RDA -
TDA -
REQUEST
ENABLE
Read Buffer
RA or Buffers RA
and RT contents
Control register 1 bits 0 and 5 must be
o and 1 respectively
Write into
Control' register 1 bits 1 and 4 must be
o and 1 respectively.
Buffer TA or flA
and IT
"
DCD :- Transmitting
data carrier'
disconnected
Status register bit 0 = 1
"
Status register bit 1 = 1.
This will not occur if Status register
i?it 3
. .Control register 2 bit 7 must be .1
= 1.
On low-to-high transi1ion of PCD .
CTS -
Receiving
external logic
disconnected
Control register 2 bit 7 must be 1.
On low-to-high transition of CTS.
TUF -
Transmit
underflow has
occurred
Control register 2 bit 7 must be 1.
Status register bit 4 = 1.
Control register 2 bit 7 must be 1.
St!ltus register bit 5
= 1.
Control register 2 bit 7 must be 1
. Status register bit 6
= 1.
OVRN -
~E
-
Receive
overrun error
has occurred
Parity Error
:
Control register 1, bit 5 allows you to enable or disable receive data interrupt logic. Control register 1, bit 4
allows you to enable or disable tran~mit data interrupt logic.
There is no connection between Control register 1. bits a and 1. and Control register 1. bits 4 and 5. Obviously. if
transmit or receive logic has been inhibited. then it makes no difference whether interrupt logic has been enabled or
disabled; in either case an interrupt cannot occur. However. if transmit or receive logic is enabled. then interrupt logic
may be separately enabled or disabled.
.
.
Control register 1, bits 2 and 3 deter"1i(1e the way the Sync character will be handled. If Control register 1 bit 2 is
high. thEln all Sync characters in a serial receive data stream will be stripped. so that only non-Sync characters are read
by the CPU. If Control register 1.. bit 2 is low. then the entire data stream will be transmitted to the CPU. including data
and ~ync characters. Note that the initial Sync character is always stripped:
Control register 1, bit ~ allows you to completely inhibit all Sync character logic. Now the Sync character will be
cleared. and the MC6852 must use external synchronization.
Control register bits 6 and 7 determine which write only location will be accessed when the CPU writes to the
~~gh'er memory location of the MC68~2 ..
9-68
Now consider Control registers 2 an'd 3, which are best looked upon as a single 12-bit control unit. These two
Control. registers may be illustrated as follows:
--·-7
6
5
4
3
2
0
~BitNo.
MC6852 Control Register 2 '
Q
w
~
<
a:
0
a.
00 Output continuous high at SM/DTR
0
01 Output a high pulse at SM/DTR upon detecting a Sync match
10 Output continuous low at SM/DTR
11 Ou~put a continuous low at SM/DTR and inhibit Sync match",
a:
0
~
enw
o Read/Write data two bytes at a time
~
<
1 Read/Write data one byte at a time
(3
0
000
001
010
. 011
II)
II)
<
ol:J
w
Z
a:
Select
Select
Select
Select
6
6
7
8
data
data
data
data
bits
bits
bits
bits
plus even parity
plus odd parity
and no parity
and no parity,
100 Select 7 data bits and even parity
101' Select 7 data bits and odd parity
110 Select 8 data bits an'd even parity
0
In
II)
0
~
111 Select 8 data bits and odd parity
Q
o Transmit break code (all
<
<
@
1 bits) on underflow
1 Transmit Sync character on underflow
o Inhibit all error interrupt requests
1'1.
1 Enable all error interrupt requests
j(
7
6
4
3
2
0 .-BitNo;
MC6852 Control Register 3
o Select internal Sync mode
1 Select external Sync mode
o Select two Sync characters
1 Select one Sync character
1 Clear CTS interrupt request
1 Clear transmitter underflow interrupt request
Unassigned
Control register 2, bits 0 and 1, and.Control register 3, bits 0, 1, 2 and 3 are used to define synchronization logic.
Control register 3 .•bit 0 is used to determine whether internal or external synchronization will be employed. If internal
synchronization is selected. then Control register 3. bit 1 determines whether one or two Sync characters must precede
a serial data stream for initial synchronization to occur.
Control register 2. bits 0 and 1 must now be set so that SM/DTR logic conforms to the synchronization options selected
by Control register 3. bits 0 and 1. You also use Control register 2. bits 0 and 1 to select the signal level that will be output for a standard DTR modem control.
Control register 2, bits 2,- 3, 4, 5 and 6 define the data transfer options.
Recall that when the CPU reads received data. or writes data to be transmitted. data may be read and written one byte
at a time. or two bytes at a time. We discussed this option when describing Status register bits 0 and 1. You select the
one byte or two byte mode via Control register 2, bit 2.
Control register 2, bits 3, 4 and 5 allow you to define the number of data bits per word, and parity options. These
are standard selections which have been described in detail in Volume 1. Chapter 5. Notice that the MC6852 provides
a much wider variety of data and parity options than the MC6850.
9-69
Sontrol register 2. bit 6 determines the response of MC6852 transmit logic when no data is ready to be transmitted. If
Control register 2. bit 6 is O. then a break code will be output on underflow; if this bit is 1. then a Sync character code
will be output on underflow. Remember. an Underflow error will be reported in the Status register only if you transmit
Sync character codes on Underflow. Therefore. Control register 2. bit 6 must be 1 if Underflow errors are to be reported
in the Status register. Recall that an underflow error is reported before a Sync character is transmitted; also. the underflow error status is accompanied by a high TUF output signal pulse.
MC6852
Along with Control register 1, bits 4 and 5, which we have already described, Control
INTERRUPT
register 2, bit 7 and Control register 3, bits 2 and 3 apply to MC6852 interrupt logic.
lOGIC
MC6852 interrupt logic is quite complex. There are a number of interrupt sources and no standard
procedure for enabling. disabling. acknowledging or processing different in'terrupt requests.
Rather than describing the Control register bits that pertain to interrupts. therefore. various interrupt options provided by the MC6852 are summarized in Table '9-7.
PROGRAMMING THE MC6852
let us now look at the normal sequence of events when programming the MC6852.
First the MC6852 must be initialized. Initialization begins by resetting the MC6852 using the RESET control input.
When the MC6852 is reset this is what happens:
1)
2)
3)
4)
5)
MC6852
Control Register 1. bits 0 and 1 are set to 1. inhibiting transmit and receive logic.
RESET
Control register 2. bits 0 and 1 are reset to O. causing SM/OTR to be output high.
OPERATION
Control register 2. bit 7 is reset to O. disabling OCO andCTS interrupt requests. and all error
interrupt requests.
Control register 3. bit 0 is reset to O. selecting internal synchronous mode.
Status register bit 1 is cleared and held low so that the CPU never reads a status that requests data be written to
the MC6852.
Control register bits affected by the RESET control input cannot be modified until RESET goes high again.
Following device Reset. you must load Control registers 1. 2 and 3 and the Sync Code register. The only caution concerns Control register 1; remember. Control register 1. bits 6 and 7 must be modified so that you can access Control
registers 2 and 3 and the Sync Code register. When modifying Control register bits 6 and 7. be sure not to inadvertently
modify the remaining six bits of Control register 1.
Once the MC6852 has been initialized, you are ready to start transmitting or receiving data.
The only complications associated with transmitting or receiving data involve the way in which you select the programmable options of this device. There is nothing intrinSically different or complicated about the MC6852. as compared to any other synchronous serial I/O device. These are the only rules to observe:
1)
2)
3)
Always inhibit transmit and receive logic via Control register 1. bits 0 and 1 before modifying the contents of any
Control register or the Sync register.
Unless you have enabled error interrupts. always precede any data read or write operation by reading the contents
of the Status register and checking for errors ..
Remember, the MC6852 transmits serial data least significant bit first. This is the inverse of IBM format;
and it is up to you to invert the data stream when usinga~ MC6852 with external IBM protocol logic.
9-70
Clock Logic
Q
ILl
...
Accumulator
Register(s)
Arithmetic and
Logic Unit
c(
a:
0
Q.
a:
0
0
~
Data Counter(s)
enILl
...
g
c(
Stack Pointer
CI)
CI)
c(
oil
ILl
Z
a:
Program Counter
0
Direct Memory
Access Control
10
CI)
0
~
c(
Q
c(
@
Interface Logic
Interface Logic
Programmable
Timers
Read Only
Memory
I/O Ports
Interface Logic
I/O Ports
Figure 9-28. Logic of the MC6828 Priority Interrupt Controller
THE MCS607 (OR MC6S2S) PRIORITY INTERRUPT
CONTROLLER (PIC)
This Priority Interrupt Controller ha.s two part numbers, identifying the fact that it is a bipolar part, and also compatible with the NMOS family of the MC6800 microcomputer devices. We will use the part identification
MC6828 in the discussion that follows.
The MC6828 Priority Interrupt Controller processes up to eight external interrupt requests, creating a vectored
response to an interrupt acknowledge. Interrupt priorities are determined by pin connections, but under program control you can set a priority I.evel below which all interrupts are inhibited.
Figure 9-28 illustrates that part of our general microcomputer system logic which is provided by the MC6828
PIC.
9-71
The MC6828 PIC canriot be compared to the 8259 PICU which is available with 8080A microcomputer
systems. The briefest inspection of the two devices will indicate that the 8259 offers a significantly wider range of options - which can be a good thing or a bad thing. As we have often stated. an excessive dependence on interrupt processing in microcomputer .applications is hard to justify; in all probability the more limited capabilities of the MC6828
will adequately serve the needs of any reasonable microcomputer application.
The MC6828 is packaged as a 24-pin DIP. It is fabricated using bipolar LSI technology.
A single +5V power supply is required.
Me6828 PINS AND SIGNALS
MC6828 pins and signals are illustrated in Figure 9-29.
In order to understand this device, you must first look at the 'way in which it is used within an MC6800
microcomputer system.
..
. CS1
STRETCH
cso
iNa
iN1
iN2
iN3
iN4
INS
---..-.----
iNS
iN7
GND
Pin Name
1
2
3
4
5
6
7
MC8507
MC6828
PIC
8
9
10
11
12
VCC
24
23
22
21
20
19
18
17
16
15
14
13
-
..
-..
-.--.
-.-.
iRci
Z4
Z3
Z2
Zl
E
R/w
-----
A1
A2
A3
A4
Type
Description
A1 - A4
Zl - Z4
Input
Output
Input
Input
Input
Input
Output
Output
Termination of system Address Bus lines A 1-A4
Continuation of system Address bus lines A 1-A4
External interrupt requests
Device Select
Read/Write control
Device Enable
. Clock stretching signal
Interrupt request
Power and Ground
iNa-iN]
CSo. CS1
R/W
E
STRETCH
iFffi
VCC.GND
Figure 9-29. MC6828 Signals and Pin Assignments
Recall that when any standard external interrupt is acknowledged by an MC6800 CPU. the CPU will fetch the starting
address for the interrupt service routine from memory locations FFF816 and FFF916. These two addresses may be illustrated as follows:
15
14
13
12
11
10
9
8
7
6
5
4
3
o
2
o
0
'-BitNo.
I I
X
t
....
- -~-Address
.. 0 for FFF8
1 for FFF9
9-72
The MC6828 PIC is positioned serially, preceding the external memory device which is to be selected by the
addressesFFF816 and FFF916' Address lI.nesA1, A2, A3 and A4 terminate at the MC6828. Logic within the
MC6828 appropriately manipulates these four address lines and outputs some value which may differ from the
input value. This may be illustrated as follows:
Q
w
!(
a:
0
0..
a:
0
(,)
~
en
w
!(
g
CI)
CI)
<
alJ
w
Z
a:
0
m
CI)
0
:!
<
Q
<
@
Address
transmitted
by CPU
A15
A14
A13
A12
All
Ala
AS
A8
A7
A6
A5
A4
A3
A2
. Al
AO
Address
received
by memory
----------------------------------------~
1
a
a
X
1 .
Y}
Y
Y
Y
X·
Address
lines
modified
by. MC6828
--
.....
~
MC6828
'---
Thus. what the MC6828 does is extend the two addresses FFF816 and FFF916 into 16 addresses. FFE816 through
FFF716·
.
The CPU knows nothing about the address manipulation which istaking place within the MC6828. So far as the CPU is
concerned. upon acknowledging an external interrupt. it reads two bytes of data from memory locations FFF816 and
FFF916: the fact that there are eight possible responses to these two addresses is of no concern to the CPU.
.
Conceptually. the MC6828 is acting as an 8-way switch. The CPU addresses the switch by its "stem". via a single address. The actual conduit for the transfer of two bytes of data depends on the switch position at the time the CPU accesses the switch stem: and the switch position is going to be determined by the highest priority active interrupt request. This may be illustrated as follows:
-
FFF8. FFF9
-
IN7:- .
IN6 :::
IN5 ,..
iN4~
im~
iNi-=
. iNi:
N _
TNO"'-
FFF6. FFF7
FFF4. FFF5
FFF2. FFF3
FFFO. FFFl
FFEE. FFEF
FFEC. FFED
FFEA. FFEB
FFEB. FFE9
Let us now look at the device pins and signals.
A 1 - A4 represents the termination of System Address Bus lines A 1 - A4 at the MC6828.
The continuation of the four address lines is via pins Z1 - Z4.
The eight external interrupt requests are connected to INO - IN7. Interrupt priorities are in ascending level, from
INO which has lowest priority through IN7 which has highest priority.
Device select logic consists of CSO and CS1. For this device to be selected. csa must be low while CS1 is high.
There are additional select requirements that depend on the operation being performed. as we will describe shortly.
9-73
RIW is the read/write control output by.the MC6800 CPU.
E is the standard enable signal required by all support devices of an MC6800 microcomputer system. You can
extend the response time available to the MC6828 by extending the E input.
A STRETCH output is created and can be connected directly to the clock device of the microcomputer system in
order to provide as much response time as needed by the MC6828.
The actual interrupt request which generates the entire response process occurs via the IRO output from the MC6828.
This output will normally be connected to the MC6800 IRO input.
THE INTERRUPT ACKNOWLEDGE PROCESS
When anyone of the eight interrupt request lines INO -IN7 is low, an interrupt request is generated via IRQ.
This interrupt request is passed on to the M,C6800 CPU.
As is normal. the MC6800. upon acknowledging the interrupt request. will perform two read operations; during these
read operations the contents of memory locations FFF816 and FFF916 are read. The MC6800 CPU interprets the contents of these two memory locations as a 16-bit address. identifying the beginning of the interrupt service routine
which is to be executed following the acknowledge.
When the MC6800 CPU is reading the contents of memory locations FFF816 and FFF916, these are the signal
levels for the control and select inputs to the MC6828:
R/W
1
CSO
o
CS1
A4
A3
1
1
1
A2
A1
o
o
The MC6828 interprets the signal combination RIW·CSO·CS1·A1.A2.A3·A4, as a special select, causing it to
output binary data on the Z1, Z2, Z3 and Z4 pins representing the highest priority active interrupt request occu rring on any of the interrupt request pins INO -IN7. Table 9-8 defines the binary data output corresponding to each interru pt level.
If RIW is high, CSO is low and CS1 is high, but A 1, A2, A3, A4 are not 0011, then the MC6828 will simply output, via Z1 - Z4, whatever is being input via A 1 - A4. Also, when the MC6828 is not selected, A 1 - A4 is simply
output via Z1 - Z4, whatever values are input via A 1 - A4: that is to say, 0011 input to A1- A4 will be output via
Z1 - Z4 if the MC6828 is not selected. Thus. the presence of the MC6828 on the A 1 - A4 address lines of the Address Bus will be transparent until either the address FFF816 or the address FFF916 appears on the Address Bus.
In order to guarantee that the MC6828 remains synchronized with the rest of the MC6800 microcomputer system.
logic internal to the MC6828 uses the E synchronization signal as part of internal enable logic. The way in which
the E synchronization signal is used is of no particular concern to you. as an MC6828 user. Providing the E synchronization Signal which drives the rest of the MC6800 microcomputer system also drives the MC6828. problems will not
arise.
Table 9-8. MC6828 Address Vectors Created for Eight Priority Interrupt Requests
PRIORITY
PIN
Z4
Z3
Z2
Z1
Highest 7
6
5
4
3
2
1
Lowest 0
IN7
IN6
IN5
IN4
IN3
IN2
1
1
1
1
0
0
0
O·
0
0
0
0
1
l'
1
1
1
1
1
0
1
0
1
0
1
0
TNT
INO
0
0
1
1
0
0
9-74
EFFECTIVE ADDRESSES
FFF6
FFF4
FFF2
FFFO
FFEE
FFEC
FFEA
FFE8
and
and
and
and
and
and
and
and
FFF7
FFF5
FFF3
FFF1
FFEF
FFED
FFEB
FFE9
INTERRUPT PRIORITIES
Q
w
~
a:
oIl..
a:
o
CJ
~
enw
~
(3
o(I)
(I)
ct
all
w
Z
Table 9-8 defines the priorities that will be applied to simultaneous interrupt requests occurring at pins INO IN7. This table also indicates ~he exact memory addresses which will be created by the MC6828 in response to
each of the interrupt requests. In order to use the MC6828 PIC in an MC6800 microcomputer system. 16 bytes of
PROM or ROM. selected by the addresses given in Table 9-8 must be connected to the MC6828. Within these 16 bytes
of'PROM or ROM. you must store the starting addresses for the eight interrupt service routines which are going to be
executed following acknowledgement of each possible external interrupt request. For example. suppose that interrupt
req'uests arriving at the IN5 pin of the MC6828 must be serviced by an interrupt service routine whose first executable
instructi"on i~ stored in memory location 2E0016. The value 2E0016 must then be stored if! the two PROM or ROM bytE!s
select~d by memory addresses FFF216 and FFF316, Remember. the high-order byte of an address is always stored at
the lower address. Thus 2E16 will be storeg in memory location FFF216 while 0016 is stored in memory location
FFF31~·
.
In simple configurations the 16 bytes of PROM or ROM selected by the MC6828 will be part of the MC6800 address
space; the MC6828 simply sits on the Address Bus. Logic may be illustrated as follows:
A1S
AS
A4
a:
o
CD
(I)
o
~
ct
Q
ct
Al
AO
VMA
R/W
<1>2 (E)
I~Q
@
· ..·-..
··· -
···
···
=
:.
A4
Al
~
-
=.
-
...
'U'
,-. CSO
. ...
. ..
---
INO
IN7
···
.
Z4 ~
Zl ~
IRQ
Al
A4
MC6828
CSl
<1>2 (E)
R/W
.+..... ~
Chip select logic generates CSO as the NAND of address lines A5 through A 15; thus. the MC6828 will be selected only
when these address lines are all high. VMA is used to generate select line CS 1. Since VMA is high only while a valid
memory address is being output. valid select logic is completed. Address lines A4 through A 1 physically terminate at
the MC6828. which re-generates them via the Z4 through Z1 outputs. Z4 through Z1 will exactly reflect A4 through
A 1. unless the MC6828 is selected and A4 through A 1 is 1100. Thus. the presence of the MC6828 will add a slight propagation delay on the Address Bus. but otherwise it will have no effect on addresses being transmitted until FFF816 or
FFF916 appear.
9-75
It is also possible to move the MC6828 PIC out of the main Address Bus path, in which case its 16 bytes of PROM
or ROM 'are 60t within the main microcomputer address space. This scheme may be illustrated as follows:
A15
A5
A4
A3
A2
A1
AO
VMA
R/W
<1>2 (E)
IRQ
·· .-
···
..
MC6800
SYSTEM
BUS
:
.:.=
..
-..,
-..
L,. CSO
.-
A1
Z1
'- A2
Z4
..
.-
--..-
..-..
· :...
· .....
ROM
ENABLE
AO
A1
A4
SEPARATE
ROM
ENABLE
AND
ADDRESS
LOGIC
A3
MC6828
A4
CS1
<1>2 (E)
Riw
IRQ
.
+...... ~
INO~----------------------------~
IN7~'----------------------------------~
In the ah6ve'scheme it is only necessary that memory addresses FFF816 and FFF16 be reserved for the MC6828 PIC:
This is be~aus.e A4, A3, A2 and A1 contribute to CSO logic; they must be 1100 for CSO to be low. CS 1 is generated ,by
thehigh'VMA'pulse, Address Bus lines A 1, A2, A3 and A4 now branch to form a new five-line Address Bus -AO with,
Z1 thro~gh;Z4. This five-line Address Bus is input to a separate ROM or PROM which is enabled by the same logic'that'
enabIJS"the'MC6828.
'
If you move the MC6828 PIC out of the main Address Bus. then you can have more than one MC6828 device'within a
single MC6800 microcomputer system. Each MC6828 device must have its own 32 byte$ of PROM or ROM. and device
priority must be established by conditioning lower priority MC6828 select logic with higher priority interrupt request
logic. This may be illustrated as follows:
:'
A15
0
w
I-
ct
a:
0
Q.,
a:
0
u
~
enw
I-
ct
A5
M
A3
A2
Al
AD
VMA
IRQ
.. ..-..
···
-..
:.
00'
U
0
(/)
(/)
~
a:
0
a:I
(/)
"r
'r$
ct
w
Z
...t,
un
A
'.:---...
~-
--
0
::!
ct
0
ct
@
-:-;,
:::
-..
t:1)
--
.-
If
CSO } Highest priority
CSl
MC6828
iRQ
CSO} Second highest
fS 1
priority MC6828
IRQ
~
"
Anyone interrupt request being true at a higher priority MC6828 PIC will suppress the high VMA pulse and automatically prevent a lower priority MC6828 PIC from being selected.
INTERRUPT INHIBIT LOGIC
The Mf:6828 provides a very elementary level of interrupt inhibit logic. You can output a mask to the MC6828
identifying a priority level below which all interrupts will be inhibited.
Now the mask is written out to the MC6828 in a very unusual way.
Recall that the MC6828 requires memory addresses FFE816 through FFF916 to access PROM or ROM. Any attempt to
write into these memory addresses will be ignored. The MC6828 takes advantage of this fact by trapping attempts to
write into memory locations FFE816 through FFF916. That is to say. when R/W is low while CSO is low and CS 1, IS high.
the MC6828 considers itself selected. but it interprets the four address lines A 1. A2. A3. A4 as data. defining the mask
level below which interrupts will be inhibited, Table 9-9 defines the way in which the mask specified by address
lines' A 1, A2, A3 and A4 will be interpreted.
', ' ,
9-77
Table 9-9. MC6828 Interrupt Masks -
Their Creation and Interpretation
Which will inhibit
all interrupts. including
and below:
and Address Bus
lines A 1-A4 will
have this value:
Write anything
to this address:
FFEO or FFE1
FFE2 or FFE3
FFE4 or FFE5
FFE6 or FFE7
FFE8 or FFE9
FFEA or FFEB
FFE<:; of FFED
FFEE or FFEF
FFFO through· FFFF
0000
0001
0010
0011
0100
0101
0110
0111
1000 through 1111
All interrupts enabled
IN1
IN2
IN3
IN4
IN5
IN6
IN7
All interrupts disabled
THE MC6840 PROGRAMMABLE COUNTER/TIMER
This is a programmable device which contains three sets of counter/timer logic. Each set of counter/timer logic
can be programmed independently to perform a vari9ty of time interval, pulse width measurement and signal
generation operations.
The MC6840 programmabie counter/timer is described in this chapter rather than in Volume 3 because, like
other 6800 support devi~es, it requires the enable clock signal as an input..
The MC6840 is somewha.t more versatile than the 8253 programmable counter/timer, which was first developed
as an Intel 8080 support"aevice; the 8253 counterltimer is described in Volume 3. Within an MC6800 or MCS6500
microcomputer system. the 8253 is probably preferable to the MC6840; this is because capabilities of the MC6840 are
not sufficiently superior to the 8253 to compensate for the enable clock signal and its attendant synchronization problems
.
The MC6840 is fabricated using N-channe! silicon gate depletion load technology; it is packaged as a 28-pin DIP.
THE MC6840 COUNTER/TIMER PINS AND SIGNALS
MC6840 counter/timer pins and signals are illustrated in Figure 9-30. These pins and signals are described in
conjunction with a general discussion of the MC6f;140 organization
logic and capabilities.
!,.
•
t ' . ' . .
"
Each of the three sets of timer logic has a 16-bit Counter, a 16-bit Latch and three control signals, illustrated as
follows:'
. ' , .
IRQ~~--------------------------------------------------------------------------------~---------------~--------------------------
Data In
C
Clock (Decrement Control)
Counter/
Timer
Logic
Data Out
0
Output
G
<1>2 (E)
Data In
Gate/Control
l..-----------------------------:-----------------------------------------,..',i.i(.·•. re~Jist~~r/ iii
9-78
Shaded registers
are addressable
(GND) Vss
G2
2
02
3
4
c
C2
~
G3
03
w
a:
a
0
a..
a:
RESET
IRQ
0
CJ
~
RSO
RS1
RS2
R/W
enw
I-
<
C3
0
VCC
C/)
C/)
5
6
7
8
9
10
11
12
13
14
MC6840
28
27
Ci
26
25
24
G1
01
23
22
21
20
19
18
17
16
15
,J:.:
DO
01
02
03
04
05
06
07
<1>2 (E)
CS1
CSO
<
o/l
w
Z
PIN NAME
DESCRIPTION
TYPE
0
DO - 07
C1
01
G1
C2
02
G2
C3
03
G3
RSO, RS1, RS2
CSO, CS1
R/W
RESET
IRQ
<1>2 (E)
Data Bus
Timer 1 clock
Timer 1 output
Timer i gate
Timer 2 clock
Timer 2 output
Timer 2 gate
Timer 3 clock
Timer 3 output
Timer 3 gate
Register select
Chip select
Read/Write control
System reset
Interrupt request
Clock input
Power and Ground
Tristate, bidirectional
Input
Output
Input
Inp~t
Output
Input
Input
Output
Input
If'!put
Input
Input
Input
Output
Input
a:
ell
C/)
0
~
<
<
@
c
VCC,VSS
Figure 9-30. MC6840 CounterlTirner Signals a~d Pin Assignments
When any counter or timer operation is initialized, the 16-bit Latch contents are loaded
into the associated 16-bit Counter. The Counter is then decremented either on high-to-Iow
transitions of the external clock signal (Cl. or on high-to-Iow transitions 'of the int~rnal <1>2
clock signal; selecting one or the other is a programmable option. Thisrnay be illustrated as
follows:
MC6840
COUNTER/TIMER
INITIALIZATION
Initialize
<1>2 or C
i
--1
+
XXXX
from
Latch
to Counter
I
\
+
XXXX-1
in
Counter
I
\
4
XXXX-2
in
Co~~ter
I
L
+
XXXX-3
in
Counter
XXXX represents any initial 16-bit value.
If the external clock signal is used to decrement the counter/timer, then it is being used as an event counter; if
the internal synchronization clock is used to decrement the counter/timer, the!" it is being used as a tim~r.
The external signals
quences.
C and G are
sampled on the trailing edge of ~. This has important synchronization conse-
9-79
Timing for external clock signal
C or G may
be illustrated 'as follows:
MC6840
EXTERNAL
SIGI'IAL
TIMING
1
I
<1>2 (E)
\
1
I~------
1
I
.y,:
CorG
I
I
_~-II""-------':\
'
~
:i;;r.
I '
.
~'
I
One machine cycle
' C must be stable low before start
of machine cycle, and must not
start returning high until after end
of machine cycle.
Thus. external clock signal frequencies may vary from Q (DC) to somewhere less than half of the internal <1>2 clock frequency.
It is very important that external signal timing conform to the illustration above. If insufficient setup time is provided. MC6840 logic will possibly recognize the initial high-to-Iow signal transition twice: once assuming that the
setup time just made it. and again assuming that it did n~t;· this may be illustrated as follows: .
,
\
1
<1>2 (E)
I
I
I
\
~
C orG
sign~i.
C or G ~ mllY be detected ' ~ or
<1>2 (E)
Actual
\)'ffi O'~ffi
..J___
:)
~ detected
here or here
C or G
A similar problem may occur on the trailing edge of the external
This may be illustrated as follows:
This may result in clock pulses being missed.
'
G. - l
~/h';
1
1
1
I
C or G' - - - - - - - . \
h'f i =v
may be detected
0'
1
I
I
______________- - J
I
Some or all of
these four Cor G
interpretations !
are possibl~ /
L
,.....----------:"-----------
1
I·~
I
,I~------~
- - - - - - -I
-----l\
\
'I
------~\-------~--------I
,
1
,I
I
I
I
1
I
I
I
I
\
9-80
I
I
Any transition of the
C or G input signals is not recognized by internal MC6840 logic for four CSl
VMA
A15
A3
:~
Select
Logic·
~CSO
~RS2
~RSl
A2
Al
AO
... RSO
--..-
~
Signals output
by the MC6800
CPU
Signals input to
the MC6840
Counter /Timer
a
Once the MC6840 has been selected. the level of the RIW signal determines whether a read (R/W high) or write
(R/W low) operation is to occur. If R/W is low. the CPU will write into the selected MC6840 location: if R/W is high.
.
the contents of the selected MC6840 location will be read.
Any data transferred to or from the MC6840 is transferred via the Data Bus. The MC6840 Data Bus connection is
three-state: when a read or a write operation is not in progress. the MC6840 disconnects itself from the Data Bus.
The MC6840 is reset by applying a low input signal to the RESET pin. Necessary reset timing may be illustrated as follows:
9-81
IMC6840 RESETI
RESET signal timing requirements are the same as the C and G requirements which we just described. The RESET is
recognized by internal logic two clock pulses after a low level is ~e~ected.
Following a valid reset. all Latches are loaded with the value FF16. and this value is transferred to the Counter registers.
All Control registers are reset to O. with the exception of Control Register 1 bit O. which is set to 1. This is a system initialization bit which we will describe later. The Status register is als6 cleared. Thus. following a reset. those programmable options which are selected by 0 bits in the Control registers will be enabled.
MC6840 ADDRESSING
.
.
Addressable locations within the MC6840 are all read-only or write-only locations. Table 9-10 identifies MC6840 add~essable ,locations.'
Table 9-10. MC6840 Addressable Locations
Operations
Register Selected
Label
Address
R!W=O (Write)
R/W'=1 (Read)
RS2
RS1
RSO
0
0
0
DEV
Write to Control Register 3
if Control Register 2. bit 0 is 0
Write to Control Register 1
if Control Register 2. bit 0 is 1
No operation
0
0
1
DEV+ 1
Write to Control Register 2
Read Status register
0
1
0
DEV+2
Write to MSB register
Read Counter Register 1
0
1
1
DEV+3
Write to Latches 1
Read LSB register
1
0
0
DEV+4
Write to MSB register
Read Counter Register 2
1
0
1
DEV+5
Write to Latches 2
Read LSB register
1
1
0
DEV+6
Write to MSB register
Read Counter Register 3
1
1
1
DEV+7
Write to Latches 3
Read LSB register
'.
There are sgme nonobvious aspects to r'v1C6840 addressing. We will first look at write addresses.
If we number the three counterltimer logic elements 1. 2 and' 3. counterltimer logic element 2 has a unique write-only
a(jdress for its Control register. (I~ is address DEV+ 1). Counterltimer elements 1 and 3 share a single write-only address
(DEV) .. The level of Control register 2 bit o determines whether Control Register 1 or 3 will be selected by addr~ss DEV.
This may be illustrated as follows:
"
' ,
.
7
Address DEV + 1
Address DEV
6
5
4
3
2
o ....--BitNo.
,J----.
~,,_.&.._...&I_..a..__~...._ .....-",I___
Control Register 2
------------..;,.c--~;~---1:~ Co~trol Register 3
! -
9-82
Control Register 1
Following a device reset. Control Register 2. bit 0 will be O. Therefore. initially Control Register 3 will be selected by address DEV. Thus. you will normally access Control registers in the sequence 3. 2. 1. as follows:
1)
Select address DEV. access Control Register 3.
2)
Select address DEV+ 1. access Control Register 2. Set Control Register 2. bit 0 to 1.
c
3)
Select address DEV. access Control Register 1.
~
a:
oa..
Three write addresses select an "MSB" register. All three write addresses select the same temporary "Most Significant
Byte" buffer. This buffer allows 16 data bits to be written into anyone of the three 16-bit latches when a single 8-bit
write is executed. This may be illustrated as follows:
w
a:
o
o
ui
w
O~
7
~
MSB buffer
~
g
CI)
CI)
L / ' I - - - - - - - - - - - y Write Address
....----_--1
15
oCt
Bit No.
'v----------~
o ..
B 7
all
w
Z
Latches 1
MSB
LSB
a:
o
en
DEV + 2, DEV + 4, DEV + 6
Bit No.
L / ' I - - - , Write Address
Iv-----"DEV+3
CI)
o
o ..
15
~
oCt
C
oCt
Latches 2
MSB
LSB
Bit No.
1 / ' - - - - , Write Address
'\r---~ DEV + 5
@
Latches 3
O~
B 7
15
MSB
LSB
. . . .- - -_ _ _ _ _
~
Bit No.
1 / , - - - . . Write Address
_ _ _ _ _ _ _ _ _ __ _ JIv--~DEV+7
MSB means Most Significant Byte
LSB means Least Significant Byte
9-83
The Most Significant Byte (MSB) buffer allows the MC6840 to be accessed by MC6800 16-bit write instructions. You
can. for example. use an STX or STS instruction to transfer the contents 'of the Index register or the Stack Pointer tathe
selected MC6840 location. There are three MC6840 locations which can receive a 16-bit data value: they are the three
counterltimer latches illustrated above as Latches 1. Latches 2 and Latches 3. You address these counter/timer latches
via their associated Most Significant Byte buffer address. Now when you output a 16-bit value (for example. from the
Index register). first the high-order byte is transferred to the Most Significant Byte (MSB) buffer. For Latches 2 this may
be illustrated as follows:
15
o
87
. STX
MSB Buffer
O~BitNo.
8 7
Latches 1
DEV+3
15
8 7
15
8
o ....-..Bit No.
Latches 2
DEV+5
o
7
Latches 3
DEV+7
9-84
~BitNo.
DEV+4
Then the low-order byte' is transferred to the low-order byte of the addressed counterltimer latches. while
simultaneously the Most Significant Byte (MSB) buffer contents are transferred to the high-order byte of the addressed
counterltimer latches. This may be illustrated as follows:
15
cw
CPU "d., R.g'''.'
!ia:
I
fl.
a:
0
CJ
~
MSB Buffer
...ct
g
.a
o '--BitNo.
8 7
CI)
CI)
ct
Latches 1
w
Z
DEV+3
a:
0
III
CI)
0
~
ct
C
ct
0
STX
0
en
w
8 7
Latches 2
@
O...-BitNo.
8 7
Latches 3
DEV+7
9-85
DEV+4
You can. of course. access counterltimer latches using single byte instructions. You could. for example. transfer a 16bit value one byte at a time from Accumulator A. via the following instruction sequence:
LDA
STA
LDA
STA
A.#HI
A.DEV+4
A.#LO
A.DEV+5
LOAD ADDRESS HIGH-ORDER BYTE AS IMMEDIATE DATA
STORE IN MSB BUFFER
LOAD ADDRESS LOW-ORDER BYTE AS IMMEDIATE DATA
WRITE 11 DATA BITS TO LATCHES 2
This instruction sequence may be illustrated as follows:
7
O"--BitNo.
7
MSB Buffer
DEV + 2. DEV + 4
DEV+6
15
8
O,--BitNo.
7
Latches 1
DEV+3
15
8
04--BitNo.
7
DEV+5
8
O~BitNo.
7
Latches 3
. DEV+ 7
#HI
Memory
9-86
o
o
c
w
I-
<
a:
0
a.
MSB Buffer
a:
0
0
~
en
w
o ..-.- Bit No.
B 7
I-
<
(;
0
CI)
CI)
OEV+3
<
011
w
Z
a:
0
15
O~BitNo.
B 7
Latches 2
III
CI)
OEV+5
0
:!:
<
<
@
15
c
8
o '--BitNo.
7
Latches 3
OEV+7
Memory
0
LOA A.#LO
7
o .......-BitNo.
MSB Buffer
o . - - B i t No.
Latches 1
OEV+3
0 ...-BitNo.
1)
Latches 2
OEV+5
o .--BitNo.
Latches 3
OEV+7
#LO Memory
9-87
7
o
MSB Buffer
O.--BitNo..
Latches 1
p-------------~----------~
Latches 2
Latches 3
oev+ 7
Memory
As illustrated by the instruction sequence above. you must first transfer the high-order byte of data to the Most Significant Byte (MSB) buffer. then you must transfer the low-order byte of data to the timer/counter Latches address: when
you write to the timer/counter Latches address. the data moves into the low-order byte of the timer/counter Latches.
while simultaneously the Most Significant Byte buffer contents are transferred to the high-order byte of the
timer/counter Latches.
There are seven read-only locations within the MC6840.
Address DEV does not select any read-only location.
Address DEV+1 reads the contents of a Status register: this register records time out and interrupt request status for
the three sets of counterltimer logic. The Status register is described later. .
9-88
The remaining six read-only addresses are used to read the contents of the counter/timer counters in a manner that is
analogous to the way in which you write into the cou~ter/timer latches. This m~y be i~lustr~Wd as folloyvs:
Bit No.
~7
0
LSB Buffer
0
w
~
II:
0
a..
BitNo.~:15
8 7
0
II:
0
0
Counter 1
~
ui
.g
w
«
Adejress:
DEV+2
. 8 7
Bit No.----' 15
0
CI)
CI)
Count~r 2
«
011
w
z
Address:
0
Bit No.----' 15
·DEV+.4
II:
m
8
7
0
CI)
0
~
«c
«
Counter 3
Address:
DEV+6
@
?-89
The three addresses which select the Least Significant Byte (LSB) buffer once again address the Si3me location. Consider the LDX' instruction which loads a 16-bit data value into the CPU Index register. When' this instruction addresses
an MC6840 counter/timer. you first read a Countj3r regi~lgr high-order byte into the Index register high-order byte
while simultaneously transferring the Counter register low-order by tEl into the Least Significant Byte (LSB) buffer. For
Counter 2 this may be illustrated as follows:
15
8
o
7
LSB Buffer
Bit N o . - - " 15
8
7
Co~nter
Address:
1
DEY,;-':
Counter 2
Address:
Bit No.----" 15
8
7
Counter 3
Address:
DEV'..:j.y
9-90
The Least Significant Byte (LSB) buffer contents are then transferred to the low-order Index register byte:
15
0
8' 7
Q
w
~
II:
0
a.
II:
0
LSB Buffer
(J
~
en
w
~
BitNo.~15
~
g
8.7
Counter 1
CI)
CI)
~
Address:
oil
w
Z
DEV+2
II:
0
III
CI)
Counter 2
0
~
~
Q
~
Address:
Bit N o . - . - 15
~
Counter 3
Address:
DEV+6
You c~n. of course. read Counter register contents one byte at~ time. but you must make sure that you read the highorder byte mst by addressing the counter itself: ,then you must ~ead the low-order byte by addressing the next addressable location. This may be illustrated for Counter 2 by the following instruction sequence: '
LOA
LOA
A.DEV+4
B.DEV+5
LOAD dbuNTEA HIGHcdRDER BYTE TO ACCUMULATOR A
LOAD COUNTER LOW-ORDER BYTE TO ACCUMULATOR B
ThEm! are some' ways of getting into
tro~ble, whe~ acc~;sing
the .MC6840.
As illustrated for Counter read and Latch write oper~tions. whe~ 'reading or writing to the MC6840 you must first s~lect
an even address location. and ,then address the next sequential lobation. If, you write first toah odd address; you will
transfer into the seiected latches eight bits of data plus whatever happens to be in the Most Significant Byte buffer.
If you read first from an odd address. you will read whatev~r happens ,to be in the Least Significant Byte (LSB) buffer.
You must never access the MC6840 with an instructiori that modifies the contents of a memory location; these instructions read the contents of the addressed memory location to the CPU. modify its contents. and then write the contents
back to the same. addressed memory location. For an increment memory instruction:,
INC
bEV+4
9-91
this may be i1lust~ated as follows:
Step 1
To CPU and
increrneht
Bit No.
MSB Buffer
DEV+2.DEV+4.
DEV+6
Bit No.
LSB Buffer
DEV+3. DEV+5
DEV+7.
Bit No.:
Latches 1
DEV+3
o
Counter 1
~~----------~-------------
Bit No.
15
Latches 2
Counter 2
~it No.
Latches 3
O·
Counter 3
Bit No.
Step 2
Incremented
value from
CPU
cw
~
a:
oa.
a:
Bit No
o
u
~
enw
MSB Buffer
~
DEV + 2. DEV + 4
DEV+6
g
CI)
CI)
~
LSB Buffer
CI/:I
w
a:
DEV + 3. DEV + 5
DEV+7
Z
o
m
CI)
o
~
~
15
c
Bit No
<:
@
Latches 1
DEV+3
Bit No
Counter 1
15
Bit No
Latches 2
DEV+5
15
DEV+4
8
7
o
Bit No
Counter 2
15
Bit No
Latches 3
o
Counter 3
9-93
Bit No
As illustrated above. the same address accesses different MC6840 locations on a read or write: you will read the contents of one location. modify them. and write them back to a totally different location. Therefore. when accessing the
MC6840 under program control. you must be sure not to use instructions that modify memory: use only instructions
that read from memory or write to memory.
ivlC6840 COUNTER/TIMER PROGRAMMABLE OPTIONS
We will begin our discussion of the MC6840 counter/timer options by describing the Control code which must
be written into each Control register. Subsequently, the various operating modes will be discussed along with
appropriate examples.
MC6840
CONTROL
REGISTERS
This is the general format for the Control code:
3
6
o ,,--SitNo.
2
I I I I I I I I
.~
j~
.•
I~
I
~
.
~
Control Register
I~
Control Register 1 - 0
1
Control Register 2 - 0
1
Control Register 3 - 0
1
No operation
Initialize all counter/timers
Write address 0 selects Control Register 3
'Write address 0 selects Control Register 1
No operation
Select +8 prescalar for Counter/Timer 3
o - Select external clock
1 - Select internal <1>2 clock
0- Select 16-bit counting mode
1 - Select 8-bit counting mode
o - Continuous or Single-shot mode
o - With programmed start
1 - Without programmed start
o - Select Continuous mode
1 - Select Single-shot mode
01 - Frequency Comparison mode
11 - Pulse width Comparison mode
o - Interrupt or Gate pulse shorter
1 - Interrupt on time out shorter
o - Disable interrupts
1 - Enable interrupts
o -: Disable Output signal
1 - Enable Output signal
Bits 0 of the three Control registers are unusual in that they have different interpretations for the three Control registers.
Control Register 1. bit 0 is a system initialization bit. System initialization is identical to a
system reset. with the exception that latches are not effective. Thus. as soon as a 1 is written
to Control Register 1. bit O. all three counterltimers are stopped. the contents of all three
Latches are transferred to their associated Counter registers. the Status register is cleared. and
all Control register bits (with the 'exception of Control Register 1 bit 0) are reset to O.
MC6840
PROGRAMMED
INITIALIZATION
Control Register 2. bit 0 is an addressing bit. When this bit is O. a write to the lowest MC6840 address (DEV) will access
Control Register 3: when this bit is 1. a write to address DEV will select Control Register 1. This was graphically illustrated in our earlier discussion of MC6840 addressing.
9-94
a
Control Register 3. bit is unique to counter/timer 3. When this bit is 1. every eighth clock pulse
will be active at cQunterltimer 3. This may be illustrated as follows:
c
w
~
o0.
MC6840
DIVIDE-BYEIGHT CLOCK
Actual <1>2 or C
a:
a:
o
o
I
--------~--~--~------------------~~
~
I'
n'
Effective <1>2 or C
3
2
Iii
4
I
5
I
7
6
I
8
fL
I~------------~----~~----~
4
3
2
I
5
6
7
w
~
g
(I)
(I)
ct
ail
w
Z
a:
oaI
(I)
o
:E
ct
c
ct
@
Control register bits 1 through 7 serve identical functions. but apply only to one set of counter/timer logic.
Each of the three counter/timer logic elements operates quite independently. and is in no way influenced by
conditions at either of the other counter/timer elements.
Control register bit 1 determines whether Counter register contents will be decremented by external clock signal (C) transitions., or by the internal <1>2 clock. In either case the counter,will be decremented on high-to-Iow clock
transitions.
Control register bit 2 determines the way in which the Counter register will decrement.
There are two options: 16-bit counting mode and 8-bit counting mode. In 16-bit counting
mode. the 16-bit counter contents are treated as a single 16-bit entity. Once an initial value has
been loaded into the counter. it decrements on each active clock transition. When the clock
decrements to O. a time out occurs. This may be illustrated as follows:
20rC
'Jn n~wn ~
U'
-.......,
Ilill.talize.
Load latches
contents into
Counter
L
_e •••• ____ e o _ e o _ e .
MC6840
16-BIT
COUNTING
MODE
~
~
V'
Decrement Counter on
each clock pulse. This
may occur automatically.
or following another initialization
Decrement Counter
on each clock
pulse
Counter
decrements
to 0
Reload
Counter
with Latches
contents
.... ......
~~
~~~
~~
This is a time out
There are a variety of ways in which you initialize a counter/timer. These are programmable options which depend on
the selected operating mode - which we will describe .Iater.
'
A time out occurs after a Counter register decrernents toO. On the next clock pulse the Counter register is reloaded
with the contents of the latches. Under program control you can determine whether a time out will be marked by an interrupt request. and whether the counter/timer will stop or run continuously.
9-95
In 8-bit counting mode the high-order and low-order bytes of the counter are treated as separate
entities. On each active clock transition the low-order counter byte is decremented; when the loworder byte decrements from 1 to O. nothing happens. On the next active transition of the clock.
the low-order byte is reloaded from the low-order byte of the latch and the high-order byte is
decremented. This may be illustrated as follows:
~,--------~~~--------~~
Decrement Counter loworder byte on each clock
pulse
Initialize. Load
latches contents
into Counter.
Counter low-order byte
decrements to 0
Decrement Counter highorder byte and re-Ioad
Counter low-order byte from
latch
MC6840
8-BIT
COUNTING
MODE
'-....._ -.....'V,.---",/
Decrement Counter loworder byte on each clock
pulse
Counter low-order byte
decrements to 0
Counter high-order byte
decrements to 0 last time
and now contains O. Reload
both Counter bytes from
latches
~'-------~~~--------"'~
,
This is a time out
Initialization logic. time out logic and programmable options are identical in 16-bit and 8~bit modes. What differs are
the events between initialization and time out. .
We can contrast 8-bit and 16-bit modes aecrement logic by looking at what happens after an initial value of 040A16
has been loaded into a counter/timer latch. In 16-bit mode a time out will occur after 101110 clock pulses. Assuming a
1 microsecond clock. a time out will occur every 1.011 milliseconds:
040A16 = 101010
Time out occurs one clock pulse later. that is. after 101110 pulses
101110 microseconds = 1.011 milliseconds'
,
In 8-bit mode a time out will occur after 55 clock pulses, With reference to the 8-bit mode illustrated above. let us see
how we derive this value.
The low-order Counter register byte contains OA16. which is equal to 1010, It takes 1010 clock pulses to decrement
the low-order byte to O. On th'e, 11 th clock pulse the high-order byte is decremented. while the low-order byte is
reloaded from the low-order byte of the latches. The high-order byte is therefore decremented once every N+1 clock
pulses. where N is the initial value which is loaded into the Counter register low-order byte.
The Counter register high-order byte decrements to O. On the next attempt to decrement the Counter register highorder byte. if it already contains O. a time out occurs. Thus. the Counter register high-order byte is decremented M+1
times. where M is the initial Counter register high-order byte contents .. Thus. you can compute the number of clock
pulses until a time out occurs in 8-bit mode via the followin'g 'equatiqn:
'"
(M+1) * (N+1)
where M is the initial Counter register high-order byte contents and N ,is the initial Counter register low-order byte contents.
For each counter/timer you can selilct one of eight operating methods via Control registers bits 3, 4 and 5.
For any MC6840 operating mode, interrupts and/or the output signal (0) mayor may not be enabled.
If interrupts have been enabled (via Control register bit 6). then on every time out (and for certain
other special conditions) an interrupt request will be made to the CPU by outputting a low IRO signal. Simultaneously. appropriate Status flags are set in a Status register. If interrupts are disabled.
the Status register bit settings occur. but no interrupt request is output via IRO.
9-96
-MC6840
----,
INTERRUPT
ENABLE
If the output signal (0) is enabled. then during Continuous and Single Shot operating modes an
output signal is generated. The output signal (0) is not used in frequency comparison and pulse
width comparison operating modes.
The Status register of the MC6840 reports time outs and interrupt request status. Status
register bits are interpreted as follows:
Q
w
6
~
oQ.
5
4
3
2
o
MC6840
OUTPUT
SIGNAL
ENABLE
STATUS
REGISTER
......-BitNo.
a:
Status Register
a:
u
o
~
Counter/TImer 1} 1 = Interrupt or time
Counter/TImer 2
out condition
.
0 = No interrupt or
~------ Counter/Timer 3
time out condition.
L--_ _ _ _ _ _ _ _ _ _ Not Assigned
en
w
L--_ _ _ _
~
g
en
en
~------------- 1 - Active interrupt pending
c(
o - No active interrupt pending
alS
w
Z
a:
The MC6840 Status register is a read-only location accessed via the address DEV+ 1. as shown in Table 9-10.
m
There are some nonobvious consequences of Status register organization. We will therefore describe the in.
dividual Status register bits and then the way in 'which they should be used.
o
en
o
:!:
c(
Q
c(
@
Status register bits 0, 1 and 2 will be set to 1 if an interrupt condition exists at counter/timer 1, 2 or 3, respectively. This will occur whether or not interrupts have been enabled. For example. if a time out occurs at counterltimer
2. then Status register bit 1 will be set. irrespective of whether counterltimer 2 interrupts have or have not been
enabled via Control Register 2. bit 6. Thus. Status register bits O. 1 and 2 do not report an interrupt pending from a
counterltimer: rather. they report the existence of a condition capable of generating an interrupt request. Status
register bit 7 indicates the presence of a valid interrupt request. Status register bit 7 will be set to 1 if a valid interrupt request has been generated by one or more of the counter/timers. That is to say. if Status register bit O. 1 or 2 he..:.
been set to 1 while the associated Control register bit 6 is 1. then Status register bit 7 will be set to 1. This may be il.,
lustrated via the following logical equation:
S7, = (SO. C16) + (S1 • C26) + (S2 • C36)
In theequation above. SO~ S1. S2 and S7 represent Status register bit~ O. 1. 2 and 7. respectively. C 16. C26 and C36'
represent bit .6 of Control Registers 1. 2 and 3. respectively .• and + signs represent logical AND and OR operations.
respectively.
'
Now. in an MC6800 microcomputer system that is using vectored interrupt acknowledge logic. Status register bit 7 is
useless. This is because the'vectoring logic associated with the interrupt acknowledge allows the executing program to
branch directly to an interrupt service routine dedicated to this particular MC6840 device. For example. in an MC6800
microcomputer system that includes an MC6828 Priority Interrupt Controller (PIC). the interrupt request line from the
MC6840 would terminate at one of the MC6828 interrupt request pins: the MC6840 interrupt service routine's start
address would be fetched by the MC6828 PIC following an interrupt acknowledge..
Upon acknowledging the interrupt request. the MC6800 knows that this particular MC6840's interrupt has been
acknowledged: therefore the high-order Status register bit contains no useful information. In MC6800 microcomputer
systems that use polling logic following an interrupt acknowledge. the interrupt acknowledge process will begin with a
general purpose interrupt service routine that reads the contents of every device Status register - checking for devices
with an active interrupt request. Now Status register bit 7 of the MC6840 is useful. The initial general purpose interrupt
service routine will read the contents of the MC6840 Status register and check bit 7. If this bit is 1. then an active interrupt request exists. Here is an appropriate instruction sequence:
LDA
BIT
BNE
LOA
A.DEV+1
A.#80H
MC6840
A.NEXT
READ STATUS REGISTER
TEST HIGH-ORDER BIT
IF NOT O. BRANCH TO SERVICE ROUTINE
READ NEXT DEVICE'S STATUS REGISTER
You cannot use the MC6800 Status register to create interrupt request priorities within the MC6840. One or
more counterltimer int~rrupts must be enabled via the Control register bit 6 for an interrupt request to be generated.
but if more than one counter/timer can generate an interrupt request. you have no way of determining which
counterltimer generated the interrupt request. Suppose. for example. that only counterltimer 1 has its interrupt request logic enabled via Control Register 1. bit 6. Now if a time out (or other condition capable of generating an interrupt
9-97
request) occurs at counterltimer 2, and then at counter/timer 3, and then at counter/timer 1, this is how Status register
bits will be set:
Comment
Event
Status Register
Counter/Timer 2
times out
I0 I0 I0 I0 I 0 I0 I 1 I0 I
Counter/Timer 2 interrupts are disabled so there is
no interrupt request and Status register bit 7 is 0,
Counter/Timer 3
times out
I I0 I 0 I0 I 0 I I I I
Counter /Timer 3 interrupts are disabled so there is
no interrupt request and Status register bit 7 is O.
Counter/Timer 1
times out
I
Counter/Timer 1 interrupts are enabled so there is
an interrupt request and Status register bit 7 is 1.
1
0
1
1
0
I 0 I 0 10 I 0 I I I
1
1
1
I
An interrupt request is generated only after counterltimer 1 encounters an interrupt condition, but there is no way of
reading the Status register in order to find out what happened. All the Status register. says is .that all three
counterltimers have active interrupt conditions and at least one of them has its interrupt request logic enabled. Program logic within the interrupt service routine must therefore take care of arbitrating priorities between the three
counter/timer elements of an MC6840 counter/timer. Therefore, use the MC6840 interrupt enable/disable logic to
select the counter/timers that can cause an interrupt request to occur, but make sure that your MC6840 interrupt service routine uses program logic to arbitrate interrupt priorities between the three counter/timer elements.
Status register bits are reset to 0 by a reset operation (RESET is input low) or by a general initialization (Control Register
1 bit 0 is 1). Logic that resets individual Status register bits has been carefully designed to avoid missing interrupt requests. In order to reset Status register bit 0, 1 or 2 to 0, you must read the Status register and then read the particular
counterltimer's Counter register. This may be illustrated for counterltimer 2 as follows:
LDA
LDX
A.DEV+1
DEV+4
READ STATUS REGISTER CONTENTS
READ COUNTER 2 CONTENTS AND RESET STATUS REGISTER BIT 1 TO 0
By reading the contents of one particular Counter register, you also identify the Status register bit to be reset. If all
Status register bits were reset when you read Status register contents. you might miss pending interrupts that you are
not currently processing.
You can also reset individual Status register bits by writing to a counterltimer's counter latches, providing the
counter/timer's Control register bit4 is 0 - which results in the counterltimer being initialized when data is written to
the counterltimer's latches.
Let us now look at each of the operating modes in turn. Options are defined by the Control register, whose bits
we have already described. Table 9-11 provides an options summary.
We will first examine Continuous mode.
9-98
© ADAM OSBORNE & ASSOCIATES. INCORPORATED
Table 9-11. A Summary ofMC6840 Options and Control Register Settings
Options
Control Code Options
Mode
Initialize
Counter
16-Bit
8-Bit
Continuous
XXOXOOXX
XXOX01XX
XX010XXX
XXOOOXXX
One Shot
XX1XOOXX
XX1XOlXX .
XX110XXX
.. XX100XXX
Gl+R
Gl+W+R
Enabled
1XOXOXxx...
1X1XOXXX
Disabled
OXOXOXXX
. OX1XOXXX
Enabled
.~
. Disabled
Special Conditions
Clock
Internal
External
"
i;XlOXOXXX
XOOXOXXX
XXOXOX1X
XXOXOXOX
8-bit counter with L=O generates 16bit waveform. N =0 generates square.
wave output with half clock frequency
X11XOXXX
X01XOXXX
XX1XOX1X
XX1XOXOX
Land M=O in 8-bit mode or N=Oin 16bit mode disables output
G pulse versus TO.·
Frequency.
Comparison.
Gless
Pulse Width
Comparison
Interrupts
Output
Output signal is not significant in these
modes. W is always part of initialization
Gmore
XXX010XX
XXX011XX
NA
NA
XXOO1XXX
. XX101XXX
X1X01XXX
XOX01XXX
XXX01X1X
XXX01XOX
XXX110XX
XXX111XX
NA
NA
:XX011XXX
XX111XXX
X1X11XXX
XOX11XXX
XXX11X1X
XXX11XOX
G 1refers to --"L on G input
W refers to a write into counter/timer latches
N is the 16-bit value written into counter/timer latches; it has a high-order byte- 1M) and a low-order byte IL)
. NA means not applicable
Table 9-12, MC6844 DMAC Register Addresses
Address
:
r'
['",,4
,
Accessed Location,
A3
A2
A1
AO
Label
"
0
0
0
0
0
OEV
Channel 0 Address register, high-order byte
,,··O"'~;'
0
0
0
1
OEV+ 1
Channel 0 Address register, low-order byte
0
0
0
1
0
OEV+2
Channel 0 Byte Count register, high-order byte
0
0
1
1
OEV-I:3
Channel 0 Byte Count register, low-order byte
0
0
1
0
0
OEV+4
Channel 1 Address register, high-order byte
0
0
1
0
1
OEV+5
Channel 1 Address register, low-order byte
0
:
0
1
1
0
OEV+6
Channel 1 Byte Count register, high-order byte
..
0
1
1
1
OEV+7
Channel 1 Byte Count register, low-order byte
0
1
0
0
0
OEV+8
Channel 2 Address register, high-order byte
o ' 'I~i
1
0
0
1
OEV+9
Channel 2 Address register, low-order byte
0
1
0
1
0
OEV+A
Channel 2 Byte Count register, high-order byte
t, ()
1
0
1
1
OEV+B
0
1
1
0
0
OEV+C
0
0
'"
,
~
Channel 2 'BYte Count register, low-order byte
'Channel 3 Address register, high-order byte
0
1
1
0
1
OEV+O
Channel 3 Address register, low-order byte
"t 0
1
1
1
0
OEV+E
Channel 3 Byte Count register, high-order byte
Channel 3 Byte Count register, low-order byte
\0
,1
"
'·,1'1
,1
\"1
, ,
1
1"
1
",r.,
\",
i
'
,
1
1
1
1
OEV+F
0
0
0
0
OEV+ 10
Channel 0 Control register
0
0
0
1
OEV+ 11
Channel' 1 Control register
0
0
1
0
OEV+ 12
Ch~nnel
0
0
1
1
OEV+ 13
Channel 3 Control register
0
1
0
0
OEV+ 14
Priority Control register
0
1
0
OEV+ 15
Interrupt Control register
0
1
1
1
0,
OEV+ 16
Data Chain Control regist~r
2 Control register
In Continuous Operating mode with 16-bit counting. a time out will occur after N+1 active
clock transitions; recall that you may select the internal <1>2 clock, or the external clock (C): In each
case the high-to-Iow transition of the selected clock is an active transition, If the outpu't signal (0)
is disabled. then Continuous Operating mode with 16-bit counting simply generates a time out every N+1 active clock transition, This may be illustrated as follows:
.
2
<1>2 or C
3
N-1
N
MC6840
CONTINUOUS
MODE
N+1
J\J\..J1J\.. _____ J\.J1JVL __ _
!J +"!v
Initialize. Load N into
Counter register
Decrement· Counter
+L 1
Time
Out
If irter~u:Pts are enabled for the cQu.nter/timer wh~ch tin;es out. then ,the time out causes an interrupt request t~ be
transmitted to the CPU and appropriate Status register bits are set. If Interrupts are not enabled. then the appropriate
Stcitus.register bit is set. but no interrupt request is transmitted. to the CPU,
In Continuous Operating mode with 16-bit counting. if the output signal (0) is enabled'.' then this signal will change
level on each time out. thus creating a square wave. Here is the exact waveform:
N
2
N
N+l
~
a:
oa..
N+l
__...f\.J\.Jl._..
< I > 2 0 r c . n r \ J l . _ ••
cw
N
N+l
o
a:
o
tJ
~
en
w
~
~
lriiiialize.
Load N from
latches into
Counter .
g
(I)
(I)
ct
alJ
w
Z
a:
o
aJ
Decrement
Counter
register
Time but
and
initialize
again
Time out
and initialize
again
Decrement)
Counter
register
Decrement
Counter
register
Time out
and
initialize
again.
II') Continuous mode. observe that following each time out the value held in the counter latches (N in the illustration
above) is transferred to the Counter register. If the output signal 0 is enabled. therefore. the following square wave is
generated:
.
(I)
o
~
0
ct
C
ct
J
\
I '
I
I
@
P
I
I
p
TO
TO
TO
I
\
I
r
_I _
I
I
\
I
-1--
~P
I
_I_
I
I
I
I
_I_
p
p
-I'-
P~
TO
TO
TO
I
TO
TO identifies a time out. P represents the time interval between time outs; it is equal to (N+ 1)*t where N is the initial
16-bit value loaded irlto the Couhter register and t is the time interval between active transitions of the clock (<1>2 or C).
In Continuous Operating mode with 8-bit counting. the interval to time out is (N+1) * (M+1) clock transitions. where
M is the initial Counter register byte and N is the initial low-order Cpunter register byte. We have already described this
time out logic. If the output signal (0) is disabled. then a time out will occur after the appropriate number of active clock
transitions. When the time out occurs. an interrupt will be requested via IRQ if interrupts are enabled for this
counter/timer by setting its Control register bit 6 to 1. Simultaneously. appropriate Status register bits will beset. If interrupts are disabled. then a Status register bit will be set. but rio interrupt request will occur. If the output signal (0) is
enabled. then it generates pulses as follows:
~
~
~
~
~
~
~
N
~+
2
2orC
N+l
N
3
N+2 N+3
~
,+
~
+
~
+
~
~
+
+
+
+
+
+
~
'.1VVVl_.1VVVl.J\...JlJlll.
o
'\,.,r
u
..
r .•••
v~--
Decrement Counter
register.
low-order byte
Initialize.
Load MN
into Counter
register
. . . . . . .__....v--
".~
Decrement Counter
register in 8-bit
'mode
Decrement Counter
register
low-order byte
Decrement
Counter register
high-order byte.
It is O. Reload'
low-order byte
from latches
Decrement
Counter register
high-order byte
and reload
low-order byte
from iatches
9-101
Decrement
Counter
register in
8-bit mode
Time out.
Reload both
bytes of Counter
register from
latches
Thus. in 8-bit counting mode you use the low-order Counter register byte to define the pulse width. and you use the
high-order Counter register byte to define the interval between pulses. This may be illustrated as follows:
0
\
n
I
n
I
,....
_1
P
·i
P
4
.,
I
I
P
4
TO
TO
TO
rL
I
I
I
I
w
w
w
TO
In the illustration above. TO identifies atime out.P represents the time interval between time outs. In 8-bit counting
mode P is equal to (M+ 1)* (N+ 1) * 1. where M is the initial value for the high-order byte of the Counter register. N is the
initial value for the low-order byte of the Counter register. and t is the time Interval between active transitions of the
clock (<1>2 of C). W represents the time interval of the high 0 pulse; it is equal to N * T. Suppose. for example. OAOC 16 is
the initial value loaded into the Counter register which is being operated in 8-bit counting mode. 0 will generate a
pulse output where the high pulse is 1210 clock periods long and the frequency is 14310 clock periods:
,
0\
I
TO
I
-\
I
\
I
TO
I
i
I
I
I
I
TO
I
~I
i
"--
l
I
I
v
There are some further options available to you when operating the MC6840 in Conti~uous mode.
Having loaded the counter latches by writing out data to the appropriate address,
there are two ways in which you can initialize the counter. A high-to-Iow transition of
the Gate (G) input will always start the counter:
<1>2 or C ,
\
I
G
~
___-",
Initialize
9-102
MC6840 HARDWARE
INITIALIZATION
\
You can always initialize any counterltimer via its Gate input (3) as illustrated above. Once a counterltimer has been initialized via i.ts Gate input (G). G mUst remain low. If (3 goes high at any time this will stop the counterltimer immediately. When IT subsequently makes a high-to-Iow transition. the counterltimer will be re-initialized. This may be illustrated as follows:
cw
!(
0::
oa.
0::
<1>2 or C
G
o(J
~
ui
w
e:(
g
en
en
e:(
oil
w
Z
0::
o
rD
en
o
:!:
e:('
c
e:(
@
Initialize. Reload OAOC 16
from latches into Counter
Stop. Assume 020416 currently in Counter. This value is
lost
Initialize. Assume OAOC16 is
loaded from latches into
Counter
l-
Note carefully that the Gate signal (G) going high does not suspend counterltimer operations: it stops these operations.
then restarts them with are-initialization.
You can also initialize a counter/timer under program control. Programmed initialization is an option. whereas hardware initialization via the Gate input (G) is always available. whether or not programmed initialization has been
selected. You select programmed initialization via bit 4 of the counterltimer element's Control register.
If Control register bit 4 is O. then the process of writing a 16-bit value to the counter/timer's latches will start the associated counter/timer logic. That is to say. as soon as the 16-bit value has been written to the latches. this value is
transferred to the 16-bit Counter register and the counter begins operation.
MC6840
DIVIDE
BY 8 MODE
When using counter/timer 3 only, you can select a "divide by 8" mode; this is done by setting Control Register 3. bit a to 1. Now every eighth active clock transition (of either the internal
<1>2 clock or the external clock) will be considered active. as illustrated earlier. All other options remain available when operating counterltimer 3 in "divide-by-S" mode. The clock has effectively
been slowed down by a factor of S - and that is all.
When operating in Continuous mode with 8-bit counting, two special options that depend on the initial value loaded into the latches are available. If the low-order byte of the
initial counter value is O. then. as we might expect. there is no high output signal (0) pulse
(assuming that the output signal is enabled); however. on each time out the output signal
changes levels to create a square wave that is similar to a 16-bit counting. This may be illustrated as follows:
\~ ___~I
I
\
0
I
I
1--
p
TO
MC6840
CONTINUOUS
8-BIT COUNTING
SQUARE WAVE
OPTION
I
I
I
I
"'1"
TO
-I-
p
I
I
--I
p
TO
TO
MC6840
CONTINUOUS
MODE WITH
o INITIAL
VALUE
When operating in Continuous mode with either S-bit or 16-bit counting. if the initial value loaded
into the latches is O. then Counter registers are not decremented and a square wave is output with
half the clock frequency. This may be illustrated as follows:
<1>2 or C
---1
o
--..J
\
I
\
\
I
\
I
I
I
I
I
I
TO
TO
TO
I
9-103
I
L
Time outs occur on every transition of O. Since interrupts could not possibly be serviced every other clock pulse. they
should be disabled (by having 0 in Control Registets 1 to 6) for any counter/timer element operating in the form illustrated above.
Note again that in any operating mode, continuous or otherwise, when the external clock
(C) is selected, you are in fact counting events, Hot time. Although all of our illustrations show
a synchronous clock signal with all active transitions evenly spaced. in reality active transitions
could be quite rahdciin. This may be illustrated as fbllows:
MC6840
EVENT
COUNTING
n1~1
C--1
COUNT
COUNT
COUNT
COUNT
If random timing is present on the external clock (C). then wave forms. if output via the output signal (0). will not be
uniform. This is something you may wish to use when counting external events. You could. for example. use continuous operating mode with 8-bit counting to count a fixed numbe~ of events. but to signal shortly before this fixed
number of events has occurred.
Suppose you wish to count 100 events. with a signal identifying the 90th event. This could be done loading 090916 as
the initial Counter register value:
TO
Event Numbers ......
\-------------~
+4
+
I
\
a
~
+
90
100
90
0
TO
I
I
100
The low-to-high 0 signal transition must now be used to generate an interrupt request. Time Out (TO) interrupt requests mayor may not be disabled.
Note again that the three sets of counter/timer logic are totally independent of each other. The manner in which
you operate one set of counter/timer logic has no bearing whatsoever on the manner in which you operate
either' of the other two sets of counter/timer logic.
The primary difference between one shot mode and continuous mode is that following the
first time out the output signal (0), if enabled, is disabled. In single shot. 16-bit counting
mode. the output signal (0) docs not make its lo\'v-to-high transition until he end of the first clock
pulse. This may be illustrated as follows:
-----FU
<1>2 or C
r----------
a
MC6840
ONE SHOT
MODE
----~
Initialize
Time out
Re-initialize
Time out
In single shot. 8-bit counting mode. the output ~ignal is simply disabled after the first time out. The counterltimer continues to run and time outs continue to be generated. but the output signal (0) remains disabled until the counterltimer
is re-initialized.
Another difference between One shot mode and continuous mode is that in one shot mode you do not stop the
counterltimer by inputting the Gate signal (G) high. Recall that in continuous mode. if the counter/timer has been initialized by inputting a high-to-Iow Gate (G) pulse. you can stop the counterltimer at any time by inputting the Gate signal (G) high again. This property of the IT input applies only in continuous mode.
9-104
Notice that the two special continuous mode conditions that result when the low-order Counter register byte is initially
o or the entire Counter register contents are initially 0 do not apply in one shot mode. This is because in continuous
mode nothing happens to the output signal until the end of the first time out. at which time in one shot mode the output signal is disabled anyway.
Q
w
~
oIl..
II:
II:
o
CJ
~
MC6840 frequency comparison and pulse width measurement modes are almost identical;
they differ only in the active levels of the G input. The frequency comparison and pulse width
measurement modes both compare the time interval of a pulse. input via the IT signal. with the
time interval to a time out. In frequency comparison mode a highG pulse is measured.
You can select frequency comparison mode with Gate pulse by having 001 in control register
bits 5. 4. and 3 as described earlier; then an interrupt request will be generated if the G signal
makes a high-to-Iow transition before a time out occurs. This may be illustrated as follows:
en
w
I-
ct
<1>2 or C
_J\.J\JL
G
--~
(3
oCI)
CI)
ct
call
MC6840
FREQUENCY
COMPARISON
AND PULSE
WIDTH
MEASUREMENT
MODE 5
w
Z
II:
oIn
CI)
o
:E
ct
c
ct
@
Initialize
Time out,
no interrupt
Re-initialize
Request interrupt since time
out has not occurred
As illustrated above. if the G signal makes its high-to-Iow transition after the time out occurs.
then no interrupt is requested.
The Counter register is reloaded from the latches and continues to decrement. but time outs do cause interrupt requests or Status register bit settings. Until the counter/timer is re-initialized by a high-to-Iow transition of the G input
signal. it continues to run freely as though it were in continuous mode. but time outs lose their significance. Once the
counterltimer is re-initialized by a high-to-Iow G transition. then frequency comparison logic begins again.
If following an initialization or re-initialization the G input does make a high-to-Iow transition before a time out occurs.
then an interrupt will be requested and the counterltimer logic is stopped; it cannot be re-initialized until the interrupt
has been cleared. Clearing interrupts is described in conjunction with our discussion of the Status register. Once an interrupt has been cleared. then on the next high-to-Iow transition of the gate input. counterltimer logic will be re-initialized.
In other words. between the time an interrupt request occurs and the interrupt is serviced. high-to-Iow transitions of
the IT input are ignored.
Observe that you can select either 8-bit or 16-bit counting modes in order to generate time outs when operating'the
MC6840 in frequency comparison or pulse width measurement modes.
You select frequency comparison mode with time out shorter by loading 101 into bits 5, 4, and 3 of the Control
register. Now an interrupt request will occur if the G input makes its high-to-Iow transition after the time out has occurred. We can compare the previous illustration for frequency comparison mode with Gate pulse shorter. using the illustration below for frequency comparison mode with time out shorter:
Time out
.JlJU
<1>2 or C
---j
G
Initialize
Request interrupt since time
out precedes Gate high-tolow pulse
9-105
Re-initialize
Gate high-to-Iow pulse precedes time out. No interrupt
request occurred
Once again, if an interrupt occurs the counter/timer will stop, It cannot be restarted until the interrupt is cleared and
the G input makes a high-to-Iow transition,
Pulse width comparison modes are identical to frequency comparison modes, with the exception that once'a
counter/timer is operating, low-to-high transitions of the gate input are active. The frequency comparison
modes may ,therefore be reproduced for pulse width comparison equivalents, as follows.
First. here is pulse width comparison mode with Gate pulse shorter:
_nnJ
<1>2 or C
G
Initialize
Time out,
no
interrupt
Re-initialize
Request interrupt since time
out has not occurred
Next. here is pulse width comparison mode with time out shorter:
<1>2 or C
G
Initialize
Requ~st interrupt since time
out precedes Gate high-tolow pulse
Re-initialize
Gate high-to-Iow pulse precedes time out. No interrupt
request
Notice that in pulse, width comparison mode, initialization and re-initializatioh require a high-to-Iow
although the end of the G pulse is marke'(j by a low-to-high'G transition,
G transition.
THE MC6844 DIRECT MEMORY ACCESS COf\JTROLLER'
The MC6844 Direct Memory Access controller provides MC6800-based microcomputer systems with logic to
support four direct memory access channels. This device has been designed to work with the unique timing
logic of MC6800 and MCS6500 microcomputer systems; it, should therefore be used with MC6800 and
MCS6500 microcomputer systems only. That is why, the MC6844 is described in this chapter rather than in
Volume 3.
From our discussion of the MC6800 CPU, recall that this microprocessor alloVlfs its system clock to be stretched
s,C? that direct memory access operations may be intermingled with normal instruction execution. Alternatively,
the MC6800 may be put into a Halt state during which the CPU disconnects itself from the system busses; externallogic then accesses memory by mimicking CPU signals on the Address, Data and Control Busses. Logic of
the MC6844 DMA controller allows you to perform Direct Memory Access operations using either clock
stretching or Halt state techniques.
Two noteworthy features of the 8256 DMA controller, described in Chapter 4, are also available with the
MC6844 DMA controller. These noteworthy features are:
1)
The ability to assign permanent priorities to the four DMA channels or to rotate priorities on a round-robin
basis.
2)
By reducing the number of DMA channels to three, one DMA channel can be used for the recursive DMA
transfer of fixed length or chained records.
Figure 9-31 illustrates that part of our general microcomputer system logic which has been implemented on the
MC6844 DMA controller device.
9-106
Clock Logic
Q
w
Ie(
a:
0
na:
Logic to Handle
Interrupt Requests
from
External Devices
Accumulator
Registens)
0
0
~
Data Countens)
u)
w
le(
g
Stack Pointer
(/l
(/l
e(
G!I
w
Z
a:
0
ID
Interrupt Priority
Arbitration
Program Counter
(/l
0
~
e(
Q
e(
System Bus
@
Interface Logic
Interface Logic
. Programmable
Timers
Read Only
Memory
I/O Ports
Interface Logic
I/O Ports
Figu re 9-31. Logic of the MC6844 DMA Controller
The MC6844 DMA controller chip is fabricated using N-channel silicon gate MOS technology. It is packaged as
a 40-pin ceramic or plastic DIP. All signals are TTL-compatible.
MC6844 DMA CONTROLLER PINS AND SIGNALS
Figure 9-32 summarizes MC6844 DMA pins and signals. Many of these signals have MC6800 counterparts;
therefore we will describe them within the context of a general MC6844 device discussion.
9-107
(GNO)VSS
CS/TxAKB
R/YV
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VDD
....
....-.. -- ....
.
---- -.....
---- -
--~
....
---
--..
---..
1
40
2
3
4
39
38
37
5
6
7
36
35
34
8
9
10
11
33
32
31
MC6844
OMA
CONTROLLER
30
12
13
14
15
16
17
29
28
27
26
25
24
18
19
20
23
22
21
.-
-----
----
--.
.--.
..
---.... ..
---- -.... --.
---- .--..
--- _a
2DMA
RES
DGRNT
ORQT
ORQH
TxAKA
TxSTB
IRQ/OENO
TxRQO
TxRQ1
TxRQ2
TxRQ3
DO
01
02
03
04
05
06
07
PIN NAME
DESCRIPTION
TYPE
DO - 07
AO - A4
A5 - A15
R/W
IRQ/DENO
ORQH
ORQT
DGRNT
CS/TxAKB
TxAKA
TxSTB
TxRQO - TxRQ3
2DMA
RES
Bidirectional Data Bus
Four low-order Address Bus lines and Register Select lines
Address Bus lines
Read/Write Control
Interrupt request and end of OMA indicator
DMA Hold Request
DMA Clock Stretch Request
DMA Acknowledge
Chip Select and Device Acknowledge
Device Acknowledge
DMA I/O Device Strobe
OMA Service Request
Clock Input .
System Reset
Power and Ground
Tristate, bidirectional
Tristate, bidirectional
Output
Bidirectional
Output
Output
Output
Input
Bidirectional
Output
Output
Input
Input
Input
VSS' VOO
Figure 9-32. MC6844 DMA Controller Signals and Pin Assignments
9-108
MC6844 ADDRESSABLE REGISTERS
Logic associated with each DMA channel consists of a 16-bit Address register, a 16-bit Byte Count register and
an 8-bit Control register. There are three additional registers which are shared by the four DMA channels. These
are a Priority Control register, an Interrupt Control register and a Data Chain Definition register. These may be illustrated as follows:
c
w
S-bit Control
~
o
Do
a:
~--------------------~
u)
w
S-bit Priority
~_ _ _ _.... Control register
I
~
g
U)
o
Cha~nel 1
Registers
I
These three
Control Registers
apply to all four
DMA channels
16-bit Byte Count
~-------------------~
S-bit Interrupt
_ _ _ _ _ _ Control register
I
'1
S-bit Control
}
16-bit Byte Count
Cha~nel 2
Registers
16-bit Address
I
.......-----------1-
::!:
«
c
«
@
}
16-bit Address
«
oa:I
S-bit Control
t---------------I.
U)
U)
w
Z
Registers
16-bit Address
!:
a:
Cha~nel 0
I
t---------------I-
a:
o
o
all
}
16-bit Byte Count
---------------------~
S-bit Data Chain
Definition register
I
~_ _ _ _--'
S-bit Control
16-bit Byte Count
I
t---------------I.
}
Cha~nel 3
Registers
16-bit Address
---------------------~
The transfer of any block of data via DMA begins with an initial memory address. byte count and DMA mode being
specified via the registers illustrated above. As each byte of data is'transferred. the method of data transfer is controlled
by options selected via the Control register. The Address register identifies the memory location which will be accessed
during the DMA transfer; Address register contents may either be incremented or decremented following each DMA
transfer. The Byte Count register contents are always decremented following each data transfer. and the DMA operation ends when the Byte Count register contents reach O.
The MC6844 DMA controller is accessed by the CPU under program control as 23 memory locations. Individual
memory locations are selected via address lines AO - A4, as defined in Table 9-12. When writing into or reading
out of 16-bit registers. you will usually use the LDX and STX instruction; that is to say. the most efficient method of
transferring 16-bit data between the CPU and MC6844 DMA controller is via the CPU Index register.
r-------_
Note carefully that addresses given in Table 9-12 apply only when the CPU accesses the MC6844 DMAC
MC6844 DMAC under program control to initialize a DMA transfer or to monitor DMA DATA BUS
operations. These memory addresses have no significance to actual DMA logic. Furthermore. the MC6844 DMAC
Data Bus connection to the MC6844 DMA controller plays no part during a DMA operation. Data ADDRESS BUS
is transferred between the CPU and the MC6844 DMAC, via the Data Bus (DO - 07) only
while the CPU is accessing MC6844 addressable locations under program control. Actual
data transfers between an external device and memory occur via the microcomputer system Data Bus. completely
bypassing the Data Bus connection to the MC6844 DMA device. However. during DMA data transfers. addresses and
control signals are output from the MC6844 DMAC to the System Bus via the Address Bus lines AO - A 15 and appropriate control Signal outputs. This is standard DMA logic. If you do not understand these DMA operations. see the discussion of direct memory access given in Volume 1 before proceeding further with this description of the MC6844 DMAC
device.
MC6844
The CPU may access the MC6844 DMAC under program control at any time by simply executing
an instruction which references one of the 23 memory addresses set aside for the MC6844 DMAC
DMAC
device. The MC6844 DMAC is selected by a low CS pulse. This low pulse must be generated by
DEVICE
appropriately decoding Address Bus lines A5 through A 15. together with VMA. VMA must conSELECT
tribute to MC6844 device select logic to guarantee that spurious selections do not occur during a
DMA transfer or while the Address Bus is floated. In this context it is important that only a VMA Signal output by the
9-109
MC6800 CPU be used by MC6844 device select logic. During a DMA operation. the MC6844 DMAC generates its own
VMA equivalent via TxSTB. TxSTB must be excluded from MC6844 device select logic. Here is one possibility:
..------
T~~! -------tlT~D
"System" VMA
MC6844. SELECT - - - - - - - - '
CONTRIBUTION
Depending on the number of active MC6844 DMA channels, CS may become a bidirectional signal; TxAKB is
output via the same pin as the CS input. In this case remember that CS must be generated as an open collector
gate output.
.
We will discuss the individual MC6844 addressable locations and the way in which you will program them after
describing MC6844 operating modes.
MC6844DMA TRANSFER MODES
You can select, under program control, one of three modes via which DMA transfers will occur for each of the
four MC6844 DMA channels. You can mix and match' separate and distinct modes for each of the four channels
in any way since each channel has its own Control register.
We will begin our discussion of modes by looking at all three modes superficially before examining each one in detail.
First there is Three-State Control, Cycle Stealing mode. In this mode the MC6800 CPU clock is stretched with <1>2
low while the MC6844 device transfers a single byte of data via direct memory access. This may be illustrated as
follows:
<1>1
<1>2
<1>2 (DMA)
Transfer one
byte of data.
via DMA
Normal program execution
Normal program execution
We have discussed clock stretching logic of the MC6800 microco'mputer earlier in this chapter.
The second and third MC6844 DMA transfer modes both force the MC6800 CPU into a Halt state which floats
the System Bus. The Halt state may last long enough for a single byte of data to be transferred via direct memory
9-110
access. in which case the mode is referred to as Halt, Steal mode. This may be illustrated as follows:
<1>1
cw
~
oDo
<1>2
a:
Normal program execution
a:
o
Halt long enough
to transfer one
byte of data
via DMA
CJ
~
iii
w
~
g
(I)
(I)
Normal program execution
The Halt state may be maintained for as long as it takes to transfer an entire block of data; that is to say. until a channel's Byte Count register decrements to O. This is referred to as Halt Burst mode.
c(
MC6844 DMAC THREE-STATE CONTROL, CYCLE STEALING MODE
"'
Let us now look at the different DMA modes in detail beginning with the three-state control cycle stealing
mode. Timing for this mode is given in Figure 9-33 and appropriate pin connections are given in Figure 9~34.
w
Z
a:
o
III
(I)
c
o
C
U
D
U
c
c
c
~
c(
c
<1>1
c(
@
<1>2
<1>2 (DMA)
TxRQN
DROT
DGRNT
'iXSTB .
TxAKA.TxAKB
AO - A15
R/W
C - CPU operations machine cycle
U - Unused machine cycle
D - DMA machine cycle
Figure 9-33. Timing for Three State Control. Cycle Stealing Direct Memory Access wi!h the MC6844
9-111
c
--.
_.
HALT
IRO
en
0
6
6
~
;e:
~
N
0&
~
-
07
;:: AO
;;.. Al
;;. A2
A3
A4
A5
•
••
VMA
BA
TSC
DBE
R/W
···
.--:.
. .-
j~
~
~
.~
--
,
~
.....A5
.~
<1>2 (TTL)
R/W
A15
lit CS
-
--
+
DMA/REF REO
REF GRANT
BA
SYSTEM
VMA
r- .
RESET
DMA/REF REO
A15
HALT
.~
SELECT~:
DEVICE
LOGIC
Ii
'---",
DO
: :.
-
MC6800
CPU
en
0
.---
~
--
MEMORY CLOCK_
MC6875
CLOCK
ii CS/TxAKB
DROT
REF GRANT
--:..-
j
AO
A4
DGRNT
A15
DO
<1>2 (DMA)
MC6844
TxAKB
TxAKA
TxSTB
~
-.
.
-..
.
07
DMAC R/W ~
IRO/DEND
TxAKA
TxSTB
TxRQO
-
REF
GRANT
bO-
DEND
TxROO
TXR03 14d------..,...------=---TXR03
...
Figure 9-34. An MC6844 DMAC Connected for Three State Control. Cycle Stealing Direct Memory Access
A DMA operation begins when an external device makes a DMA access request by inputting a
MC6844 DMAC
high signal via one of the four inputs TxROO through TxR03. This input to the MC6844 DMAC
TxRON, DQRT
may be asynchronous. The MC6844 responds by outputting DROT low. This low output must
DGRNT SIGNALS
be connected to the MC6875 clock CMA/REF REO input. This connection causes the MC6875
MC6844 DMAC
clock device to stretch the <1>1 and <1>2 clocks at the end of the next machine cycle - with <1>1
high and <1>2 low. The onset of the stretched clocks is identified by the MC6875 device output-' <1>2 DMA CLOCK
ting REF GRANT high. This signal must be input to the MC6844 DGRNT pin. The DMA data
transfer now occurs. taking three machine cycles to transfer one byte of data. Machine cycles are timed by <1>2 DMA.
which is the memory clock output of the MC6875 device. Recall that when the MC6875 clock device receives a low input via DMA/REF REO it does not stretch the memory clock output. The MC6844 DMAC needs a <1>2 DMA input only
while a DMA data transfer is in progress. <1>2 DMA is therefore frequently the AND of MEMORY CLOCK and REF
GRANT:
REFGRANT-----~~&_---------DGRNT
MEMORY CLOCK
------:--u-~------<1>2DMA
9-112
ow
~
a:
oQ.
a:
o
o
~
u)
As soon as clock stretching begins. the MC6800 CPU must float the System Bus. This may be done by inputting the
REF GRANT signal to the MC6800 TSC pin as well as to the MC6844 DGRNT pin. Now REF GRANT input to TSC will
cause the MC6800 CPU to float its Address Bus and three-state control signals. If DBE is connected to <1>2. as is usually
the case. then the low <1>2 signal will automatically cause the MC6800 CPU to float the Data Bus. Now as soon as REF
GRANT goes high. the MC6800 CPU is disconnected from the System Bus and the MC6844 DMAC can become bus
master.
The MC6844 DMAC takes control of the System Bus for three machine cycles. during which it
transfers a single byte of data. The first and third machine cycles represent setup time. The actual
DMA transfer occurs during the second machine cycle. For the memory end of the DMA transfer.
the MC6844 DMAC outputs a memory address via the Address Bus. For the I/O device end of the
DMA transfer. the DMAC identifies the direct memory access channel being acknowledged via
the output signals TxAKA and TxAKB. as follows:
w
TxAKB
TxAKA
g
o
0
1
1
0
1
~
o
(/)
(/)
c(
ell
ILl
Z
a:
o
CD
(/)
o
:E
c(
o
c(
@
1
MC6844
DMAC
TxAKA AND
TxAKB
SIGNALS
Acknowledged
TxROO
TxROl
TxR02
TxR03
Timing for signals output by the MC6844 DMAC conform to normal MC6800 System Bus timing for a memory read or
memory write operation.
The low TxSTB pulse substitutes for VMA at the memory and I/O device ends of the DMA. transfer.
: The direction of the DMA transfer is defined by the level of the R/W signal: the interpretation of
this signal conforms to normal memory read and write operations:
MC6844
DMAC
fiSTS
SIGNAL
R/W low causes data to flow from the I/O device to memory.
RIW high causes data to flow from memory to the I/O device.
Data may flow freely across the Data Bus during the direct memory access operation. since both the MC6800 CPU and
the MC6844 DMAC are disconnected from the Data Bus at this time.
As each byte of data is transferred. the Byte Count register contents for the selected DMA channel
are decremented; but the Address register contents may be either incremented or decremented.
depending on the Control register option selected. When the Byte Count register contents decrement to O. a low pulse is output via IRO/DEND. This pulse can be used to generate an interrupt at
the MC6800 CPU and/or it may be used to tell the external device that the current data transfer
has gone to completion.
MC6844
DMAC
iRQ/DEND
SIGNAL
The interrupt request output IRO/DEND will pulse low when the Byte Count register decrements to 0 only if interrupts
have been enabled for this DMA channel via its Interrupt Control register. If interrupts have been enabled. it is a good
idea to guard against spurious interrupt requests by conditioning IRO/DEND with the DGRNT high pulse. The interrupt
request input to the MC6800 CPU should be an open collector signal generated as follows:
~___'f - - - - - - -
DGRNT _ _ _ _ _ _
IRQ
(open collector)
IRQ/DEND
The DEND signal output to I/O devices may be ANDed with REF GRANT or with TxSTB. An AND with TxSTB is illustrated in Figure 9-34.
.
Assuming that the acknowledged DMA channel is transferring data at less than maximum speed. it must use the low
TxSTB strobe to remove its TxRON high request. If the channel keeps its TxRON DMA request active. then the next
DMA transfer will occur during the next machine cycle. Using Three-State Control. cycle stealing direct memory access. therefore. it is possible to transfer a byte of data during every machine cycle;. however. each machine cycle will
have its length increased by three machine cycles. Thus. any executing program will be reduced to executing at one
quarter of its normal execution speed.
MC6844 DMAC HALT MODES
The next DMA operating mode we are going to look at is the Halt Cycle Stealing mode. In this mode the CPU is
halted for three machine cycles. during which a single byte of data is transferred. Timing is illustrated in Figure 9-35
and appropriate pin connections are illustrated in Figure 9-36.
9-113
C
C
C
U
o
U
C
C
<1>1
<1>2
TxRQN
BA-OGRNT
VMA
TxAKA,TxAKB
------------------------~~~--------~~~~--------------~
R/W
AO - A15
DO - 07
C - CPU operations machine cycle
U - Unused machine cycle,
o - OMA machine cycle
Figure 9-35. Timing for Halt. Cycle Stealing Direct Memory Access
with the MC6844
A DMA transfer is initiated by one of the four DMA request signals TxRO through TxR3 going high.
These signals are sampled on the rising edge of <1>2. The MC6844 responds to a high DMA
transfer request by outputting DROH low. In the Halt. Cycle Stealing mode, DROH must be input
as the MC6800 CPU halt request. As explained earlier in this chapter, when a low input occurs at
HALT, the MC6800 CPU complet~s executing its current instruction, then enters a Halt state, During the Halt state, VMA is output low while the Address and Data Busses, along with the R/W
control signal. are floated. In Figure 9-35 the Halt state is shown beginning one full machine cycle
after DROH goes low.
MC6844 DMAC
TxRO - TxR3
SIGNALS
MC6844 DMAC
DRQH SIGNAL
The MC6800 CPU indicates the onset of the Halt state by outputting BA high. This output
MC6844 DMAC
becomes the DGRNT input to the MC6844. Once DGRNT goes high, the MC6844 assumes
DGRNT, TxSTB,
control of the System Bus. TxSTB is pulsed low as a substitute for the VMA signal. The address
TxAKA AND
of the memory location to be accessed during the DMA transfer is output on the Address Bus
TxAKB SIGNALS
along with the R/W, which indicates the direction of the DMA data transfer (as described for
three-state control cycle stealing mode). The DMA channel being acknowledged is identified via the TxAKA and TxAKB
signals, which are decoded as described earlier.
9-114
--.-..
• __ DO
·
-
c
w
!;(
a:
oc.
MC6800
CPU
• ; -:.
07
AO
;,;.
A1
~----------------------~j~--~+----------------~~A2
~------------------------~--~+----------------~~A3
~------------------------~~~+----------------~"A4
__
~--------------------~~~j-4-+--------------.~"A5
~~:____________________~J~~~+-____________~.~~~ A15
a:
o
o
~
enw
!;(
(3
oen
en
ct
olS
w
a:
Z
oIn
en
o
DEVICE SELECT
LOGIC
Ii
SYSTEM
VMA
' - - -......- - - ' A15
CS
:!:
ct
c
ct
-_.
e---------~~~~~--~~--------~..
RESEft
@
CLOCK
I...-.
~
L---,-~
oRQH
oGRNT
-+--------~
O--------~~
CS/TxAKB
TxAKB
TxAKA
TxSTB
AO~.
A4
_.
A15
•
_.
<1>2 (oMA)
MC6844
.....:-1-=-.______~
oMAC 07 ~O.
R/'iiiWJ 1oI_d---------...J
IRQ/oENo
~oENo
TxAKA~--------------~
TxSTB~--------------~
TxRQO~~~:----------------------~:--
TxRQ3 _
TxRQO
TxRQ3
Figure 9-36. An MC6844 DMAC Connected for Halt. Cycle Stealing or Halt Burst
Direct Memory Access
MC6844 DMAC
The VMA signal used by the system must now be the OR of VMA and TxSTB. The external
device whose DMA request has been acknowledged must detect the low TxSTB signal and use
TxSTB SIGNAL
it to reset its DMA request. If the DMA request is still active after a single byte of data has been
transferred via DMA. then a single instruction will be executed before the next byte of data is transferred via direct
memory access. One instruction will be executed even if TxRON remains high. because in Halt Cycle Stealing mode the
MC6844 will return its DROH Signal high as soon as a single byte of data has been transferred via direct memory access. This will free the CPU. to execute another instruction. and while this new instruction is being executed the whole
timing process illustrated in Figure 9-35 will begin again.
When the Byte Count register contents decrement to O. the IRO/DEND signal will output low. As was the case for
Three-State Control Cycle Stealing mode. this signal can be used to request an interrupt and/or to identify the end of a
data transfer block to external logic. It is a good idea to condition interrupt requests and DEND outputs with TxSTB in
'
order to avoid generating spurious signals.
The third and last MC6844 DMA mode is the Halt Burst mode. This differs from Halt Cycle Stealing mode in that
once a Halt condition has been initiated. it is maintained while data is transferred via direct memory access until the
Byte Count register has decremented to O. Thus. Halt Burst mode timing will differ from Figure 9-35 only in that DROH
will remain low until the channel's Byte Count register decrements to O. This will happen irrespective of the level on the
DMA request line TxRON. Note that. as illustrated in Figure 9-35. one byte of data will be transferred via direct memory
access in three machine cycles. even when operating in Halt Burst mode. Pin connections for Halt Burst mode are as il.
lustrated in Figure 9-36.
9-115
COMPARING MC6844 DMAC MODES
You will use Three-State Control. Cycle Stealing mode when program execution time is critical but data transfer rates
are not.
You will use Halt-Cycle Stealing mode when data transfer rates are not critical. program execution time is important
and you do not have an MC6875 clock device.
You will use Halt Burst mode when data transfer rates are criticai and program execution time is not.
Table 9-13 summarizes maximum data transfer rates for the three modes. A /-Lsec machine cycle time is assumed.
Table 9-13. MC6844 DMAC Modes' Response Times and Transfer Rates
Mode
Response Time
(/-Lsec)
Maximum Transfer Rate
KHz
TSC Steal
Halt Steal
Halt Burst
2.5 to 3.5
3.5 to 15.5
2.5 to 3.5
250
200 - 67
1000
USING AN MC6844 DMAC WITH MIXED MODES
If you are going to use Three-State Control and Halt modes with a single MC6S44 DMAC device. the only
special precaution ne~dedi~ to generate DGRNT as the OR of BA and REF GRANT.
The Three-State Control and Halt modes have separate DMA request lines. DROT and DROH. respectively: therefore no
special logic is needed to handle DMA requests using mixed modes.
THE MC6844
CONT~OL
REGISTERS AND OPERATING OPTIONS·
As summarized in Table 9-12. the MC6S44 DMAChas a number of programmable Control registers. which are
used to select the DMA transfer modes which we have already described. plus additional operating options.
'-M-C-6S"'44---'
The best place to begin a discussion of Control registers is with the Enable/Priority Control
ENABLE/
register. Bit settings for this register may be illustrated as follows:
PRIORITY
654
3
o 4--BitNo.
CONTROL
REGISTER
Enable/Priority Control Register
f
Channel OJ
L--_ _ _ _
L........_ _ _ _ _ _
Channel 1
Channel 2
0 - Disable Channel.
1 ~ Enable channel
"----------Channel 3
'------------Unused
~-------------
0 - Fixed priority
1 - Rotating priority
Each DMA channel that is to be active must have a 1 placed in its enable bit within the Enable/Priority Control register.
A 0 in any channel's enable bit will disable the channel. It is important to understand that if a channel is disabled. this
simply means that DMA requests arriving via the associated TxRON input will be ignored. Disabling a DMA channel
has no effect on your ability to write into the channel's registers or read from the channel's registers.
If more than one DMA channel is enabled. then two or more DMA requests can occur
simultaneously. You arbitrate priority in one of two ways. If bit 7 of the Enable/Priority Control
register is O. the following fixed priorities will always be used:
Highest Priority:
Lowest Priority:
Channel
Channel
Channel
Channel
9-116
0
1
2
3
MC6S44
FIXED DMA
PRIORITY
ARBITRATION
c
Rotating priority may be selected by writing a 1 into bit 7 of the Enable/Priority Control
register. Rotating priority initializes the four channels with the fixed priority illustrated above.
As soon as any DMA channel has been serviced. however. it becomes the lowest priority channel - and associated channels are rotated in a round-robin fashion. In order to illustrate rotating priority mode. let us assume that DMA Channel 2 is serviced and then DMA Channel 0 is
serviced. This is how priorities would be assigned:
UJ
Initial Priority:
Highest Priority:
~
0:
ono:
o
CJ
Lowest Priority:
~
en
UJ
~
Highest Priority:
en
~
UJ
Lowest Priority:
0:
Highest Priority:
o
IX!
en
o
~
Lowest Priority:
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@
Channel
Channel
Channel
Channel
3
0
1
2
Channel
Channel
Channel
Channel
1
2
3
0
Channel 0 is serviced. These are the new priorities:
Z
cc(
0
1
2
3
Channel 2 is serviced. These are the new priorities:
g
o!I
Channel
Channel
Channel
Channel
MC6844
ROTATING
DATA
PRIORITY
ARBITRATION
The next Control register we will look at is the Data Chaining Control register. because this also
contributes to channel enable logic. Data Chaining Control register bit assignments may be illustrated as follows:
7
6
4
2
o
-4--BitNo.
MC6844
DATA
CHAINING
CONTROL
REGISTER
Data Chaining Control Register
' - - - - 0 - Disable data chaining function
1 - Enable data chaining function
~-----
00 - Chain Channel 3 to Channel 0
01 - Chain Channel 3 to Channell
10 - Chain Channel 3 to Channel 2
11 - Illegal
' - - - - - - - - - - 0 - Select 2 channel mode
1 - Select 4 channel mode
'------------Unused
Bit 3 of the Data Chaining Control register is. in fact. an enable/disable bit for the TxAKB output function associated with the CS/TxAKB signal. TxAKB is disabled if the Data Chaining
Control register bit 3 is O. This is referred to as Two-Channel mode. because with only TxAKA
enabled it is only possible to acknowledge DMA requests from channels 0 or 1. This may be illustrated as follows:
TxSTB
TxAKA'
rt;;=D______
~
9-117
SELECT 1
SELECT 0
MC6844 DMAC
TWO-CHANNEL
MODE
If the Data Chaining Control register bit 3 is 1, then the TxAKB signal is active, allowing
anyone of the four DMA channels to be acknowledged. This is referred to as Four-Channel
mode, and may be illustrated as follows:
MC6844 DMAC
FOUR-CHANNEL
MODE
TxSTB-------------------------~~r--------------------------~
C
TxAKA-----------------------------------------------~~
A
YO
SELECT 0
Y1
SELECT 1
Y2
SELECT 2
Y3
SELECT 3
74155
CS/TxAKB~----------------------------------------_e~~
B
G
CS-------I
DGRNT----------~
-
(open collector
gate here)
The logic above uses the TxSTB pu Ise as a strobe for a 2-to-4 decoder. The four decoder outputs become individual
select lines for the four devices capable of requesting DMA access.
In order to rotate CS/TxAKB requirements. chip select creation logic is shown. This logic has nothing to do with generationof the Select 0 through Select 3 lines: however. unless the chip select input portion of the CS/TxAKB signal is correctly generated. TxAKB will either be held at ground or pulled to a level of 1. in which case the four~channel select
logic will not work. .
It is very important to note that there is no direct connection between the logic of the Data Chaining Control register bit
3 and the Enable/Priority Control register bits 0 through 3. Whether you select Two-Channel mode or Four-Channel
mode via bit 3 of the Data Chaining Control register. you can independently enable or disable each of the individual
channels via Enable/Priority Control register bits 0 through 3. Clearly. there are certain combinations which are not
reasonable. Options may be illustrated as follows:
Data Chaining
Control Register
Bit 3
Enable/Priority Control Register
Bit3
Bit 2
Bit 1
BitO
0
0
0
0
0
Select Two-Channel mode. but channels 0 and 1 are
disabled.
0
0
0
0
0
0
0
1
1
0
Select Two-Channel mode. but only channel 0 or
channel 1 is enabled.
0
0
0
1
1
Normal Two-Channel mode with both channels active.
0
0
1
X
X
0
1
1
X
X
In Two-Channel mode you can enable channels 2 and
3. Their DMA requests will be accepted via TxR02
and TxR03. but DMA requests will not· be
acknowledged via TxAKB. Channels 0 and/or 1 must
be enabled.
1
0
0
X
X
Four-Channel mode with channels 2 and 3 disabled
makes no sense. Use Two-Channel mode instead.
1
0
1
X
X
Four-Channel mode with channel 2 and/or 3 enabled.
and any enable/disable combination for channels 0
and 1 is alright.
1
1
1
X
X
-
9-118
If you enable data chaining by writing a 1 into the Data Chaining Control register bit 0, then
DMA operations at channel 0, 1 or 2 become continuous. Via bits 1 and 2 of the Data Chaining
Control register. you select channel O. 1 or 2 to operate in Chained mode.
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a:
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en
o
~
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MC6844
DATA
CHAINING
Chained mode simply means that as soon as the selected channel's Byte Count register decrements to O. the selected channel's Byte Count and Address registers will be reloaded with values stored in the Channel
3 Byte Count and Address registers. Suppose. for example. you want to continuously transfer. via direct memory access. 256 bytes of data. The data is to flow via Channel 0 to memory. with the data being loaded in memory locations
OA0016 through OAFF16. To perform this task you would store 00FF16 in the Channel 3 Byte Count register. and
OA0016 in the Channel 3 Address register. lyIJe assume that the Address register is going to be incremented.) Every
DMA transfer will begin with 00FF16 being loaded into the Channel 0 Byte Count register from the Channel 3 Byte
Count register. while OA0016 is loaded into the Channel 0 Address register from the Channel 3 Address register. This is
an automatic operation which requires no program intervention once data chaining has been enabled. Thus. DMA
transfer via Channel 0 will continue endlessly with the DMA transfer rate determined by the DMA mode selected.
It is important to note that a data chaining specification is to MC6844 DMAC logic an isolated event. The fact that data
chaining has been enabled does not automatically disable DMA Channel3 logic. You must do this by writing 0 into the
Enable/Priority Control register bit 3. Also. if you specify chaining. you in no way affect the manner in which registers
can be accessed. You can write into Channel 3 registers. or you can read the contents of Channel 3 registers. This can
be very useful. If 256 bytes of data are continuously bOeing read into memory locations OA0016 through OAFF16. it
wou Id take complex program logic to access all data that gets written into this buffer before the data gets overwritten
on the next DMA pass.
A better way would be to have two buffers: for example. the first from OA0016 through OAFF16 and the second from
OB0016 through OBFF16. Now. following each end of block interrupt. you would write the new address into the Chan-'
nel 3 Address register. This is illustrated in Figure 9-37.
There are some nonobvious aspects of Figure 9-37.
Observe that when you are initializing the MC6844 operating in Chained mode. you must load initial addresses and
byte counts in Channel 3 Address and Byte Count registers as well as in the Address and Byte Count register for the
chained channel. The actual chaining operating does not occur until the chained channel's Byte Count register decrements to O. When you start the chained channel. the first DMA operation uses initial Byte Count and Address values
loaded into the chained channel's Byte Count and Address registers. After the first end-of-block interrupt. the byte
count and address values loaded into the Channel 3 registers will be transferred to the chained channel registers for
the next operation.
Let us now consider the Channel Control register which is associated with each DMA channel. Channel Control register bit assignments may be illustrated as follows:
7
6
5
4
3
2
o
~BitNo.
MC6844
CHANNEL
CONTROL
REGISTERS
Channel Control register
L..-_ _ _ _ _ _ _
0 - Increment Address register
1 - Decrement Address register
' - - - - - - - - - - - - - Unused
0- DOne}
.
1 _ Busy Read-only, Status bit
o - Not end of DMA block l
1 - End of DMA block
f
Read-only, DEND
status bit
Channel Control register bit 0 simply reflects the level which will be output on the RIW pin during DMA operations that is to say. while R/W is an output from the MC6844 DMAC. Channel Control register bit 0 has no effect on R/W
while the MC6800 CPU is accessing the MC6844 DMAC under program control. The level of the R/W Signal during a
DMA operation determines whether data will be transferred from the I/O device to memory (R/W is low). or from
memory to the I/O device (R/W is high). Since each DMA channel has its own Control register and therefore its own
Control register bit O. channels may be programmed independently to generate DMA transfers in either direction.
9-119
C
,
Start
)
,
Load 00FF16 into Channel 0 and Channel 3 Byte
Count registers
Load OAOO16 into Channel 0 Address register
t
,
Load 0800 16 into Channel 3 Address register
Start Channel 0
_ l
--""J
Channel 0 Interrupt. 080016 is transferred from
Channel 3 Address register to Channel 0 Address
register. OOFF16 is loaded from Channel 3 Byte
Count register to Channel 0 Byte Count register
,
Load OAOO16 into Channel 3 Address register
l
Process data in buffer OAOO16 through OAFF16
l
Channel 0 Interrupt. OAOO16 is transferred from
Channel 3 Address register to Channel 0 Address
register. OOFF16 is loaded from Channel 3 Byte
Count register to Channel 0 Byte Count register
+
Load 080016 into Channel 3 Address register
l
Process data in buffer 080016 through OBFF16
I
Figure 9-37, Logic for MC6844 DMAC with Channel 3 Chained to Channel'O and Data Flowing
into Alternate Memory Buffers
9-120
Channel Control register bits 1 and 2 are used to select one of the three DMA transfer modes which we have just described.
Channel Control register bit 3 determines whether the channel's Address register contents will be incremented or
decremented following each DMA transfer. Thus you can perform a DMA operation specifying the highest address or
the lowest address of a memory buffer as the starting address.·
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w
Channel Control register bits 4 and 5 are unassigned.
a:
Channel Control register bits 6 and.7 are read-only status bits which should be looked at in conjunction with the Interrupt Control register. Interrupt Control register bits are assigned as
follows:
~
a:
o
0.
o
(J
°
65432
~
MC6844
INTERRUPT
CONTROL
REGISTER
-4--BitNo.
iii
w
Interrupt Control register
~
g
en
en
°-
ChannelO}
......- - - - Channel 1
Disable interrupt request
' - - - - - - - - Channel 2
1 - Enable interrupt request
~
all
w
Z
......- - - - - - - C h a n n e I 3
a:
ocg
......- - - - - - - - - - Unused
No interrupt request pending
1 - Interrupt request pending
. . . -------------°-
en
o
~
~
c
~
@
You can. at any time. examine a DMA channel to find out if it is "busy" or if it is "done". If "busy". the channel is in the
middle of transferring a block of data. If "done". the channel is currently idle. You determine a channel's status by reading the contents of the Channel Control register and examining the level of bit 6.
When you reach the end of a data block. that is. a DMA channel's Byte Count register decrements to O. the channel's
Control register bit 7 will be set to 1. If the channel's interrupt logic has been enabled via bit O. 1.2 or 3 of the Interrupt
Control register. then an interrupt request will occur via a low output at IRQ/DEND. This interrupt request will not occur
if thechannel's interrupt logic has been disabled within the Interrupt Control register.
If an interrupt request does occur. then bit 7 of the Interrupt Control register will be set to 1.
Irrespective of whether a channel's interrupt logic has or has not been disabled. the channel's Control register bit 7 Vfill
be set to 1 when the channel's Byte Count register decrements to O.
Bit 7 of the Channel Control register remains set to 1 until the CPU reads the contents of the Channel Control register.
The process of reading the Channel Control register contents automatically resets bit 7 to O.
The Interrupt Control register bit 7 is reset to 0 as soon as the Channel Control register for the DMA channel requesting
the interrupt is read by the CPU.
Suppose. for example. Channels 0 and 1 are active. with Channel 0 interrupts enabled and Channel 1 interrupts disabled. Here are appropriate Interrupt Control register settings:
76543210
76543210
I ° I° I° I° 10/110/11 01 1101 11 10 I ° I° I °101110/ 110/11 0/11
°
,01010101010101
Interrupt
Control
Register
Channel 1
Control
Register
Channel
Control
Register
°
765432
011 means the bit may be 0 or 1.
Now suppose Channel 1 becomes active. Its Control register Busy bit will be set:
6
5
4
3
2
°
1
°
1
°
10/110/110/110/11
I °1 °
°
Channel
Control
Register
6
1
I° I
5
4
3
2
°
I° I° 10/110/110/110/11
Channel 1
Control
Register
9-121
6
5
4
3
10101010101
Interrupt
Control
Register
2
°
° I° I
Next. suppo~e Channel
a becomes active. The Channel a Busy bit will. also be set:
6.(0543
2
1
0
I 0 11}'1 0 10 10/110/110/110/11
6
5
4
3
2
1
6
0
4
3
o
2
10 10 10 10 \0\0\0\
o
Interrupt
Control
Register
Channel 1
Control
Register
Channel 0
Control
Register
When the Ch~nnel , DMA operation ends. no interrupt request will occur. since the Channel' interrupt.logic has been
disabled. Thus. the Chclnnel 1 Control register Busy bit will be reset to the DEND bit will be set to' and the Interrupt
Control register will not change:
a.,
7
6'i5
4
3
2
1
0
765
10 11 J0 10 \0/110/1101110/ 11 !i11'a;1
0
4
10
32· 1
6
0
10/110/110/110/11
4
3
2
0
10101010101010
I·
Interrupt
Control
Register
Channel 1
Control
Register
Channel 0
Control
Register,
5
As soon as toe CPU read~ the contents of the Channel , Con~rol registe'r, the Channell DEND bit (bit 7) will be reset to
a.
.
'
Suppose Channel a now reaches the end of a data block; it will request an interrupt. The Channel a Control register's
Busy bit will,be reset to O. the DEND bit will be set to 1.cwd the activ~ interrupt request bit of the Interrupt Control
register will ?Iso be set to:4': ,I
. '
~-'
7
,;
654
.
321
7'
0
l)ll.Q:l,o I 0 10/110/110/110/g
·.Chann~1
6
4
3 '. 2
1 '0
11:1 0 10 10 10 10 10 1
o·
Interrupt
Control
Register
Control
Regist~r
Reading the contents of the Cha,nriel a Control register ~illreset the' Ch~nnel 0 DEND bit (bit 7). Reading the Channel 0
Control regi$ter contents will also reset the Interrupt Control register bit 7. since the Channel 0' interrupt request
caused this bit to be set. Reading the Channel' Control register will have no effect on the I nterrupt Control register bit
7. since Cha!,mel , dld not cause the interrupt request to: be generateq.
',', .
If more than one active interrupt is present. then your program must arbi.trate priorities by examining the DENO status
of each channel's Control register. Also. bit 7 of the Interrupt Control register will be reset when you read the contents
of the Control register for the first channel to request an jnterrupt.· For example. suppose all channel interrupts have
been enabled. and Channel O. then Channel 2. then Channel' request .interrupts- before the CPU acknowledges an
interrupt. The CPU can determine which channels have requested interrupts by reading Control register contents for
Channels O. 1 and 2. But it is the act of reading Channel 0 Control register contents that will reset bit 7 of the Interrupt
Control register.
RESETTING THE MC6844 DMAC
The MC6844 DMAC is reset when a low signal is input at the Reset pin. When the MC6844 DMACis reset, all
Control registers have their contents reset to O. Address and Byte Count registers' contents, however, are not
altered.
PROGRAMMING THE MC6844 DMAC
Programming the MC6844 DMAC is quite straightforward.
The first step is initialization. If you have reset the MC6844. then all Control registers' contents will be 0 - in which
case all DMA requests and interrupt requests have been disabled. If,yOU have not reset the MC6844 DMAC. then you
should do so under program control by OU1Putti'ng 0 tQ the Enable/Ptiority Control register and the Interrupt Control
register.
Once the MC6844 DMAC has been disabled, then 100tlalize channe,1 Address and Byte Count registers by loading appropri.ate initl~1 values into these registers.
;
Next, definEt the DMA operating modes by loading a~propriat~,.cQges into the channel Control registers for the
.,:
enabled cha~nels. and into the D~ta Chain Cpntrol register.
9-122
Initialization is now complete. You start OMA channels by outputting an appropriate code to the Interrupt Control
register and then to the Enable/Priority Control register.
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Monitoring DMA operations while they are in progress is also quite straightforward. Normally you will wait until
the end of a OMA transfer is signaled by an interrupt request. at which time if more than one channel could have requested the interrupt. the interrupt service routine arbitrates priorities by reading all active channel Control registers'
contents. The interrupt service routine must now respond to the active interrupt request according to the requirements
of your program logic. This mayor may not require restarting the same channel or another channel.
You can monitor DMA operations while they are in progress by reading the contents of Address and Byte Count
registers while a DMA operation is in progress. However. this is something you should only do while operating a
DMA channel in one of the Halt modes. If you read register contents on the fly while operating in Three-State
Control mode. you may read the wrong answer. and determining what the right reading should be is not easy. This
is because an instruction that reads 16 bits of data executes in two machine cycles. If this read operation occurs while a,
Three-State Control. Cycle Stealing OMA transfer is occurring. this is what happens:
'
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011
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I LDX
I
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I
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I
I
I
n,--_
Inn
I
Increment
16 bits to
032A16
I
I
I
high-
I order I
I byte I
I '
Increment
16 bits to
032816
Read I
low- I
order I
byte I
I
Next I
instr. I
f~tch I
I
Increment
16 bits to
032C16
~.
03?
,
ct ..
In the illustration above. an LOX instruction loads the contents of a 16-bit register (we will assume it is the Channel Address register) into the Index register of the CPU. First the high-order byte of the Address register (03) is transferred to
the high-order byte of the Index register. At the end of this machine cycle. however. the Address register is incremented. Now. you may say that this is no problem since you have read the valid Address register contents as they were
at the end of the LOX instruction's execution. But unfortunately there is a special case. Suppose the Address register
contained 020016 and was decrementing. Now you will read 02FF when 01 FF was the correct value:
I
I
I
~2JiJ1.
II
I LDX I
I instr. I
I fetch I
I
I
I
I
!
Decrement
16 bits to
020016
I
I
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r1
I
I
I Read I
I high- I
I order I
I byte I
Decrement
16 bits to
01FF16
I
Read I
low- I
order I
byte I
!
Decrement
16 bits to
01FE16
4'
I = I )r.FF
I
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n---
Next I
instr. I
fetch I
I
I
I
The error illustrated above cannot occur when operating OMA in a Halt mode. since the OMA transfer occurs in between instruction executions. Thus. the contents of any 16-bit registers within the MC6844 OMAC will not change
while an LOX instruction is being executed. because no OMA transfer can occur until the LOX instruction has completed execution.
You can. if you wish. write into any MC6844 OMAC register at any time. For example. you can write into an Address or
Byte Count register for a channel that is busy. Once again. you can get into trouble if you write into Address or Byte
Count registers for a channel that is operating in Three-State Control. Cycle Stealing mode. since you will write the loworder byte. all 16 bits may be incremented or decremented. and then you will write the high-order byte; and who
knows what the results will be. Writing into registers on the fly will not cause error's if you are operating in one of the
Halt modes.
, 9-123
THE MC6846 MULTIFUNCTION SUPPORT DEVICE
The MC6846 multifunction support device is designed to work with the MC6802 as a two-chip microcomputer.
However, the MC6846 can be used just as easily in any other MC6800 microcomputer system.
Figure 9-38 illustrates that part of our microcomputer system logic which is implemented on the MC6846
multifunction device. This device provides 2048 bytes of read-only memory, a single 8-bit para"ell/O port with
handshaking control signals, and a counter/timer.
'
The MC6846 multifunction device is packaged as a 40-pin DIP. It uses a single +5V power supply. A" inputs and
outputs are TTL-compatible.
The device is implemented using N-channel silicon gate depletion load technology.
MC6846 MULTIFUNCTION DEVICE PINS AND SIGNALS
MC6846 pins and signals are illustrated in Figure 9-39,
The device select lines CSO and CS1 work in two ways: they activate the MC6846, and they select which function is in use - ROM or I/O and counter/timer. The user specifies as a mask option two active combinations of
CSO and CS1 levels: one to enable the ROM and one to enable the I/O and counter/timer. For example. you might
wish to enable ROM when CS 1 is high and CSO is low. and enable the 1/0 and counterltimer when both select lines are
high, This combination would then disable the MC6846 when CS1 is low.
When ROM is' selected, the eleven lines AO - A 10 will address one of the 2048 bytes of read-only memory.
These 2048 memory bytes may be located anywhere in the memory space.
In addition to CSO and CS1. certain of the address lines are used to select the I/O and counter/timer functions.
Lines A5. A4. and A3 must be low to select the 1/0 and counterltimer operations. You select as a mask option what
level at line A6 enables I/O and the counterltimer. and whether or not one of the lines A 10. A9. A8. and A7 must be
high to enable these functions. Here is how address lines are used to select 1/0 and the counterltimer:
A 10 A9 A8 A7 A6
A5
A4
A3
A2 A 1 A O . . . - Address Lines
L...-_ _ _ _
L -_ _ _ _ _ _ _ _ _
Internal register address
(See Table 9-14)
These three lines must be low to select I/O and counter/timer
' - - - - - - - - - - - - - User decides whether high or low selects I/O and
counter/timer
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ All four "don't care" or user may assign one line on which a
high level selects I/O and the counter/timer
Once an MC6846 has been selected as an I/O device, address lines AO, A1, and A2 select one of seven
registers in eight I/O addressable locations. Table 9-14 ,identifies the locations accessed with each address. Note
that addresses 0 and 4 access the same location,
Table 9-14. MC6846 1/0 Addressable Locations
Address Line
Internal Register Selected
A2
A1
AO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Composite Status register
Peripheral Control register
Data Direction register
Peripheral Data register
Composite Status register
Timer Control register
Timer register (high-order byte)
Timer register (low-order byte)
9-124
Clock Logic
c
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IX:
oa..
Logic to Handle
Interrupt Requests
from
External Devices
Accumulator
Registerts)
IX:
o
U
~
Data Counterts)
enw
~
g
Stack Pointer
U)
U)
ct
oCS
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Z
IX:
o
Interrupt Priority
Arbitration
Program Counter
CD
U)
o
~
ct
C
ct
©
Figure 9-38. Logic of the MC6846 Multifunction Device
9-125
Direct Memory
Access Control
(GND) VSS
---
A7
A6
A5
--
A4
CSO
R/W
DO
Dl
D2
D3
D4
D5
D6
-..
..- - ..
--- --- ......
--.. --
~
1
2
3
4
5
6
7
8
9
-..
10
-..
11
12
13
14
-.
~
MC6846
D7
15
CSl
--.. 16
CTG ---I> 17
CTC
18
CTO
19
20
E
-
--
40
----
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
--
21
--- ..
----
..
-- ..
-.. --.
--- .--.
-- -..
.-
-~
A8
A9
AlO
RES
IRQ
CP2
CPl
AO
Al
A2
A3
VCC
PP?
PP6
PP5
PP4
PP3
PP2
PPl
PPO
PIN NAME
DESCRIPTION
TYPE
csa, CSl
Device select
Address lines
Data lines
Read/Write
Device synchronization
I/O Port lines
Interrupt/Strobe
Peripheral Control
Counter/timer output
External clock for counter/timer
Counter/timer gate
Interrupt request
fleset
Power and Ground
Input
Input
Bidirectional
Input
Input
Bidirectional
Input
Input or Output
Output
Input
Input
Output
Input
AO - Al0
DO - D7
R/W
E
PPO - PP7
CPl
CP2
CTO
CTC
CTG
IRQ
RES
VCC, VSS
Figure 9-39. MC6846 Multifunction Device Signals and Pin Assignments
9-126
All data transfers between the CPU and the MC6846 device occur via the bidirectional Data Bus (DO - 07). This
is a three-state Data Bus: when the device is not selected the MC6846 holds these lines in the high-impedance state.
The R/W control determines whether data will flow into the MC6846 (a Write operation with RtW low) or from
the MC6846 (a Read operation with RIW high).
stand~rd
c
E is the
!;(
The 8-bit parallel 110 port of the MC6846 is very similar to I/O Port B of an MC6820 Peripheral Interface Adapter (PIAl.
Differences are described later. Lines PPO - PP7 constitute an 8-bit bidirectional parallel I/O port. Control lines CP1
and C~2 are the ~wo handshakin,g and interrupt control signals associated with the parallel I/O port.
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IX:
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IX:
o
o
~
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oo
(I)
(I)
oCt
a!I
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IX:
oCD
(I)
o
~
oCt
C
oCt
©
synchronizing clock signal used throughout an MC6800 microcomputer system.
The counter/timer of the MC6846 is very similar to counter/timer 3 of the MC6840 counterltimer, which has
been described earlier in this chapter. CTO is the output signal, CTC is the external clock and CT~ is the gato in-
put
.
Interrupt requests originating from the parallel I/O logic of the counter/timer logic are output via IRQ.
The device is reset by inputting a low level at RES. The actual operation of the reset logic is described after the
registers which it affects have been discussed.
MC6846 COUNTER/TIMER LOGIC
Before reading this section. you should be familiar with the MC6840 counter/timer device described earlier in this
chapter. We are only going to examine the differences between counter/~jmer logic of the MC6846 and channel
3 of the MC6840. Note ttlat channel 3'of the MC6840, like the counter/timer logic of the MC6846, can be operated in divide-by-ejght mode.
The MC6846 counter/timer has its own Control register, Most Significant Byte register, and Least Significant
Byte register. As illustrated in Table 9-13. these three registers are accessed via addresses DEV+5. DEV+6. and
DEV+ 7 respectively. The counter/timer logic does not have its own Status register; this is shared with I/O port
logic.'
.
The counterltimer Control register address is not the same as any of the three addresses set aside for Control registers
of the MC6840. The Most Significant Byte register and Least Significant Byte register addresses. however. are the same
as two addresses allocated to these two registers by the MC6840.
Bits of the MC6846 counterltimer Control register are not assigned in the same way as they are for any MC6840 Control register. Here are the counter/timer Control register bit assignmel'!ts for the MC6846:
65432
o
",-BitNo.
Counter/Timer Control register
' - - - - - 0 Enable timer
1 I;'reset counter
' - - - - - - - 0 Timer uses CTC as clock input
1 Timer uses E as clock input
1.-_ _ _ _ _ _ 0 Use input clock frequency
1 Use input frequency divided by 8
!----------- Select operating mode:
~
000 Continuous (program initiated)
00 1 Cascaded single-shot
010 Continuous
011 Normal single-shot
_ _ _ _ _ _ _ _ _ _ _ _ _ Frequency comparison:
100 CTG changes before counter times out
101 Counter times out before CTG changes
Pulse width comparison:
110 CTG changes before counter times out
111 Counter times out before CTG changes
~-------------- 0 Mask timer interrupt
1 Enable timer interrupt
oSet CTa low
.' l except during cascaded
1 Enable coun~er ou~put single-shot operation
9-127
r
BitO is the internal reset bit. This is the same as bit 0 of the Control register of MC6840 counterltimer logic 1.
Bit 1 determines whether the external clock (CTC) 'or the system clock (cI>2, viaE) will be the timing signal. This is the
same as in MC6840 Control registers.
Bit 2 enables or disables the divide-by-eight prescaler; bit 0 of counterltimer 3's Control register performs the same
task in the MC6840.
Bit 6 enables or disables interrupt logic, and bit 7 enables or disables the output signal for thecounterltimer as described for the MC6840.
Control register bits 3, 4 and 5 determine the operating mode of the counterltimer. There is just one difference between the interpretation of these three bits in the MC6846 as compared to the interpretation of these three bits in the
MC6840. The MC6846 has no program-initiated sillgle-shot mode. Only a high-to-Iow transition of the gate input will
initiate single-shot mode. This missing variation of'Single-shot mode is replaced by a cascade mode. In the cascade
mode, Control registElr bit 7 is connected to the output signal CTO. When Control register bit 7 is 0, the output signal is
set low on the next timeout;' when Control register bit 7 is 1, the next timeout sets the output signal high. This is called
a "cascade" mode because it allows you, under program 'control. to count timeouts which generate interrupt requests
in the usual way and then, under program control. to change'the level of the output based on the time interval computed via timeouts.
'
'
MC6846 I/O PORT LOGIC
Before reading this section, you should be familiar with the MC6820 PIA described earlier in this chapter. We are only
going to examine t~e differences between I/O port logic of the M~6846 and I/O Port B of the MC6820.
The MC6846 I/O Port can provide programmed handshaking on either input or output.
.
.
, ' I !
Any of the data lines PPO - PP7 can directly drive the base of a Darlin9t~n NP!'I transistor. The control line CP2
al~o has this capability.
. ,
The MC6846 I/O Port has its own Control register, Data Direction regist~r, and Peripheral Data register. As illustrated in Table 9-13, these three registers are accessed via addresses DEV+ 1, DEV+2, and DEV+3 respectively. The
I/O port logic does not have its own Status register; this is shared with the counter/timer logic. We will describe
the Composite Status register later on.
In the MC6846, the Data Direction register and the Peripl1eral Data register have separat~ addresses., Recall that
in the MC6820 PIA these two registers share one address, an'd Bit 2 of the Control register determines which location is
accessed by that address. "
. , '
Bits of the MC6846 Peripheral Control register are not assigned in the ~ame way as they are for either of the MC6820
Control registers. Here are the Peripheral Control register bit assignmenls for the MC6846:
i I I I I I I I
j~
.~
j~
.~
~
~~
,
o
432
6
~
.....--BitNo.
Peripheral Control register
o Disable CP1 interrupt
, 1 Enable CP1 interrl!pt
o CP1
high-to-Iow transition generates interrupt request
1 CP1 low-to-high trarisition generates interrupt request
000 not latch input data
1 Latch input data on active tram.ition of CP1
CP2I, '"pot
o Disable CP2 interrupt
}
1 Enable CP2 interrupt
Bit 5 = 0 -
o CP2 high-to-Iow transition generates interrupt request
--
-~
1 CP2 low-to-high transition generates interrupt request
CP2 is output
00 CP2 serves as an interrupt acknowledge
01 CP2 serves as an input/outPUl acknowledge
1x set CP2 to x
Not used
o Normal 0Peration
1 Reset I/O port
9-128
\
f .
(Blt5=1~
•
If Bit 0 is set to 1. then an active transition (as defined in Bit 1) at CP1 will set IRO low. Bits 0 and 1 are used in the same
way in the Control registers of the MC6820.
.
Bit 2 selects the input latch function. When bit 2 is set. an active transition at CP1 will latch data input on lines PPO PP7. The MC6820 does not provide an input latch function.
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Bits 3.4. and 5 control the CP2 line in the same way that MC6820 Control Register B bits 3.4. and 5 control line CB2 of
that device.
Bit 6 is not used in the MC6846.
a:
Bit 7 serves as an internal reset for the I/O port. The CPU may set this bit by writing a 1 into it. but it will also be set automatically when the MC6846 receives a low level at the reset input. RES. You clear bit 7 by writing a 0 to it during a
CPU write to the Peripheral Control register.
.
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~
The interrupt flags for both the timer/counter and the I/O port appear in the Composite
Status register, which the CPU accesses via either of the addresses DEVor DEV+4. This register
is a read-only location.
en
en
Here are the bit assignments for the Composite Status register:
all
6
o(.)
!:
g
MC6846
COMPOSITE
STATUS
REGISTER
c:(
4
3
2
1
0 ~Bit No.
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Composite Status register
a:
o
CD
en
o
""----- Timer interrupt
~
c:(
Q
c:(
~----
CPl interrupt
" " - - - - - - - - - CP2 interrupt
""--_ _ _ _ _ _ _ _ _ _ Not Used
@
" " - - - - - - - - - - - - - - - Composite interrupt
Note that interrupt conditions will appear in bits O. 1. and 2 of the Composite Status register.
whether or not interrupts are enabled in the corresponding Control register.
A counter/timer interrupt will set bit 0 of the Composite Status register. Any of the following actions will reset the
counterltimer interrupt flag to 0:
•
•
•
•
Timer reset' via either Timer Control register bit 7 or RES input
Initializing ~he counter
Writing to the timer latches in Frequency Comparison mode or Pulse Width Comparison mode
Reading the Timer register after reading the Composite Status register while the timer interrupt bit was set. That is.
the following sequence resets bit 0 of the Composite Status register: bit 0 is set by the counterltimer interrupt: the
CPU reads the Composite Status register (location DEVor DEV+4): then the CPU reads the Timer register (locations
DEV+6 and DEV+ 7).
Interrupt transitions at CP1 and CP2 will set bits 1 and 2. respectively. of the Composite Status register. Each of these
bits will be reset to 0 by a Read or Write to the Peripheral Data register (location DEV+31. but only if the flag was
already set when the CPU last read the Composite Status register. This is analogous to the fourth counterltimer flag
reset condition described above.
Bit 7 yvill be set to 1 only when IRO is set low: that is. anyone of the three interrupt bits described above will set bit 7.
but only if that interrupt has been enabled in the appropriate Control register bit. Bit 7 will be 0 only when all three of
bits O. 1. and 2 are reset to O.
Bits 3. 4. and 5 of the Composite Status register are not used.
The Data Direction register and the Peripheral Data register work in the same way as those in the MC6820 do.
MC6846 DEVICE RESET
When the MC6846 receives a low level on RES, all the I/O and counterltimer logic enters the Reset state. I n addition. the I/O port and the counter/timer can be reset individually via the internal reset bits of their respective
Control registers - bit 0 of the Timer Control register and bit 7 of the Peripheral Control register.
9-129
These are the results of a counter/timer reset:
• The counter latches take on the maximum count (65.536). This occurs only during external reset (RES low).
• The counter clock is disabled.
• Bits 1 through 6 of the Timer Control register are reset to O. as are the output line CTa and the interrupt flag (bit 0 of
the Composite Status register).
The net effect is that the counter/timer becomes inactive until the CPU writes a 0 to bit 0 of the Timer Control
register.
These are the results of an I/O port reset:
• All bits of the Peripheral Data register and Data Direction register are reset to O. as are the interrupt flags (bits 1 and 2
of the Composite Status register) .
.• Bits 6 through 0 of the Peripheral Control register are reset to O.
The net effect is that the port is in input mode, and its interrupts are disabled.
9-130
DATA SHEETS
This section contains specific electrical and timing data for the following devices:
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~
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gen
• MC6800 CPU
• MC6802 CPU/RAM
• MC6870A Clock
• MC6871 A Clock
• MC6871 B Clock
• MC6820 PIA
• MC6850 ACIA
• MC6852 SSDA
• MC6840 PTM
• MC6844 DMAC
• MC6846 ROM-I/O-Timer
en
c:(
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_9-01
MC6800
.
TABLE 1 - MAXIMUM RATINGS
Symbol
Value
VCC
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range-TL to TH
MC6800, MC68AOO, MC68BOO
MC6800C, MC68AOOC
MC6800BOCS, MC6800COCS
TA
Rating
Supply Voltage
Storage Temperature Range
TstQ
Thermal Resistance
(}JA
Plastic Package
Ceram ic Package
o to +70
-40 to +85
-55 to +125
-55 to +150
Unit
°c
This device contains circuitry to protect the
inputs against damage due to high static voltages
or electric fields; however, it is advised that
normal precautions be· taken to avoid application of any voltage higher than maximum
rated voltages to this high impedance circuit.
°c
°C/W
70
50
TABLE 2 - ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, ± 5%, VSS = 0, TA = TL to TH unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Logic
¢1,<:>2
VIH
VIHC
VSS + 2.0
VCC -0.6
-
Vdc
-
VCC
VCC + 0.3
Logic
<:>1,<:>2
VIL
VILC
VSS - 0.3
Vss - 0.3
-
VSS + 0.8
Vss + 0.4
Vdc
-
1.0
2.5
100
-
2.0
Characteristic
Input High Voltage
Input Low Voltage
Input Leakage Current
(Vin = 0 to 5.25 V, VCC
(V in = 0 to 5.25 V, VCC
}JAdc
lin
= max)
= 0.0 V)
Logic·
<1>1,<:>2
Three·State (Off State) Input Current
(Vin = 0.4 to 2.4 V, VCC = max)
Output High Voltage
(ILoad = -205 }JAdc, VCC
(ILoad = -145 }JAdc, VCC
(I Load = -100 }JAdc, VCC
ITSI
-
-
VSS + 2.4
VSS + 2.4
VSS + 2.4
-
10
100
00-07
AO-A15,R/W,VMA
BA
V CC
= min)
VOL
Power Dissipation
Po
Capacitance
(Vin = 0, T A
Cin
= 25 0 C, f = 1.0 MHz)
AO-A15,R/W,VMA
-
-
-
-
-
VSS + 0.4
0.5
1.0
-
25
45
10
6.5
35
70
12.5
10
-
-
12
-
Cout
-
Vdc
W
pF
-
<:>1
¢2
00-07
Logic Inputs
}JAdc
Vdc
VOH
= min)
= min)
= min)
= 1.6 mAdc,
Output Low Voltage (I Load
00-07
AO-A15,R/W
-
pF
TABLE 3 - CLOCK TIMING (VCC = 5.0 V, ± 5%, VSS = 0, TA = TL to TH unless otherwise noted)
Symbol
Min
Typ
Max
Unit
MC6800
MC68AOO
MC68BOO
f
0.1
0.1
0.1
-
1.0
1.5
2.0
MHz
MC6800
MC68AOO
MC68BOO
teyc
1.000
0.666
0.500
10
10
10
}JS
PW¢H
400
230
180
9500
9500
9500
ns
tut
900
600
440
-
ns
Ch aracteristics
Frequency of Operation
Cycle Time (Figure 1)
Clock Pulse Width
(Measured at VCC - 0.6 V)
<:>1,¢2 - MC6800
¢1,<:>2 - MC68AOO
¢1,¢2 - MC68BOO
Total ¢1 and <1>2 Up Time
MC6800
MC68AOO
MC68BOO
Rise and Fall Times
(Measured between VSS + 0.4 and VCC - 0.6)
t¢r, t¢f
Delay Time or Clock Separation (Figure 1)
(Measured at VOV = VSS + 0.6 V @ tr = tf';; 100 ns)
(Measured at VOV = VSS + 1.0 V@ tr = tf';; 35 n5)
®
td
0
0
-
-
-
100
9100
ns
ns
9100
MOTOROLA Semiconductor Products Inc.
Data sheets on pages 9-D2 through 9-D30 reprinted by permission of Motorola Semiconductor Products, Inc.
9-D2
Me6S00
TABLE 4 - READ/WRITE TIMING (Reference Figures 2 through 6)
MC6S00
Characteristic
Symbol
Address Delay
C = 90 pF
C =30 pF
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Peripheral Read Access Time
o
Input Data Hold Time
CJ
Output Data Hold Time
en
Address Hold Time
(Address. R/W. VMA)
~
Enable High Time for DBE Input
a:
~
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C/)
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o
III
C/)
o
~
c(
Typ
Max
Min
Typ
-
-
270
250
-
-
-
60
tAD
MC6SBOO
MC6SAOO
Min
Min
Typ
180
165
-
-
250
ns
-
40
-
10
25
30
50
-
ns
10
-
220
-
-
ns
200
-
-
160
ns
-
110
-
100
ns
ns
tace
-
tDSR
100
tH
10
-
tH
10
25
tAH
30
50
tEH
450
tDDW
-
-
200
-
-
-
140
-
100
-
-
100
-
-
250
270
-
120
-
165
270
-
-
-
75
25
-
-
25
-
530
-
360
Max
Uh~":
Max
ns
- 150
135
tac = tut - (tAD + tDSR)
Data Setup Time (Read)
Data Delay Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and
Fall Time
Bus Available Delay
Three-State Delay
Data Bus Enable Down Time
During <1>1 Up Time
Data Bus Enable Rise and
Fall Times
tpcs
tPCr. tpC!
tBA
tTSD
tDBE
150
-
tDBEr. tDBEf
-
-
-
10
-
10
25
30
50
-
280
225
-
-',
-
C
c(
@
FIGURE 1 - CLOCK TIMING WAVEFORM
Aeference Tables 2 and 3
FIGURE 2 - READ DATA FROM MEMORY OR PERIPHERALS
,...., Start of Cycle
<1>1
<1>2
A/Vii
Address
From MPU
Data
2.0 V --:=~_====;,
From Memory ------------------:::::~\'
or Peripherals
0.8 V --="""i'""===;;:;;1~
K\\\\,§\i
®
Data Not Valid
MOTOROLA Semiconductor Products Inc.
9-03
-
ns
-
ns
ns
ns
25
ns
135
220
-
ns
ns
MC6800
FIGURE 3 - WRITE IN MEMORY OR PERIPHERALS
, - - Start of Cycle
_____________________ tCYC ____________________
~
~
4>1
4>2
R/W
Address
FromMPU~~~~~~~~i-~
______~________________________-4~~
VMA _____-I'""~
~----------tEH----------~~
DBE
Data
From MPU -----------------j--O:::::S~'"
~~~
Data Valid
Data Not Valid
FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY
versus CAPACITIVE LOADING (TDDW)
600
. 500
FIGURE 5 - TYPICAL READIWRITE. VMA. AND ADDRESS
OUTPUT DELAY versus CAPACITIVE LOADING (TAD)
600
10H =-205 jJA rnax@ 2.4 V
10L = 1.6 rnA rnax@0.4V
VCC=5.0V
TA = 25°C
500
vr 400
400
]
10H =-145 jJA rnax@2.4 V
10L = 1.6 rnA rnax@0.4 V
VCC = 5.0 V
TA = 25°C
UJ
UJ
::;;
::;;
;:: 300
>
g
200
, 100
--100
k-I-"
-- --
;::
> 300
.-f.;--
g
200
100
.------ -I-"
-- ---
......-.-- V
....-
300
400
500
100
600
200
300
400
CL LOAD CAPACITANCE (pF)
CL LOAD CAPACITANCE (pF)
®.
I
CL includes stray capacitance
CL includes stray capacitance
200
VMA
Address, RNI-- f - -
MOTOROLA Semiconductor Products·lnc..
9-04
500
600
M~OOO
.
FIGURE; 6 - BUS TIMING TE;ST LOADS
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TEST CONDITIONS
II:
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Test Point
o--......_....---toI~t--.
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The dynam Ie test load for the Data Bus Is
130 pF and one standard TTL load as shown.
The Address, RIW, and VMA outputs are tested
under two conditions to allow optimum opera·
tlon in both buffered and unbuffered systems.
The resistor (R) Is chosen to Insure specified
load currents during VOH measurement.
Notice that the Data Bus lines, the Address
lines, the Interrupt Request line, and the DBE
line are all specified and tested to guarantee
0.4 V of dynamic noise immunity at both
"1" and "0" logic levels.
MMD6150
or Equiv.
R
l-
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e:(
MMD 7000
or Equlv.
g
CI)
CI)
e:(
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C = 130 pF for 00-07, E
- 90 pF for AO-A15, R/W, and VMA
(Except tAD2)
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= 30 pF for AO-A 15, R/W, and VMA •
oCD
(tAD2 only)
= 30 pF for BA
II:
CI)
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R= 11.7knforDO-D7
= 16.5 kn for AO-A15, RIW, and VMA
= 24 kn for BA
@
9-05
-
v
MC6800\
,
I,
FIGURE 12 - THREE STATE CONTROL TIMING
Cycle
#1
"2
#3
=4
=5
:=7
=6
=8
=9
System
cJ>1
MPU ,/.1
Address
Bus
RfW
VMA
Data
Bus
c,')2 - DBE
.TSC
--J f4"'- tTSE
tTSE
~
FIGURE 13 - HALT AND SINGLE INSTRUCTION EXECUTION FOR SYSTEM DEBUG
lnst;uction
Fetch
tSA
BA
VMA
__________________-J!
jJ
I
I
Instruction
Execute
I
\I:....._ _ _ _ _-J(
~-----l\-----~{ff---------'I
X . . . .__. . .) -
R/Vil ~-------Iffl----------/,---.....
Fetch.
Address
Bus
Data
Bus
Execute
~~~1(----'-------------~~-----------«Addr M+l)(~____-J)
------1r-,,----y--~----------------~~----------------~
Inst
y
Inst
X
Note: Midrange waveform indicates
high impedance state.
®
MOTOROLA Semiconductor Products Inc.
9-D6
MC6802
.
'
' . '
MAXIMUM RATINGS
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w
Rating
Supply Voltage
Symbol
Value
Unit
VCC
-0.3 to +7.0
Vdc
Vin
-0.3 to +7.0
Vdc
~
a:
oD..
Operating Temperature Range
TA
Oto+70
°c
Storage Temperature Range
T stg
-55 to +150
°c
o
Thermal Resistance
IJJA
70
°C/W
a:
o
Input Voltage
This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica·
tion of any. voltage higher than maximum rated
voltages to this high impedance circuit.
~
enw
~
ELECTRICAL CHARACTERISTICS (VCC= 5.0 V ± 5%, VSS = 0, TA = 0 to 70 0 C unles otherwise noted.!
CI)
CI)
Input High Voltage
Logic, EXtal
Input Low Voltage
Logic, EXtal,
I nput Leakage Current
(Vin = 0 to 5.25 V, VCC = max)
Logic·
g
<
all
w
2
a:
o
m
CI)
o
~
<
C
<
@
Characteristic
Max
Unit
-
VCC
VCC
Vdc
-
VSS + 0.8
Vdc
2.5
/lAdc
Min
VIH
VSS + 2.0
VSS + 4.0
.-
VIL
VSS - 0.3
lin
-
1.0
VSS + 2.4
VSS + 2.4
VSS + 2.4
-
'ReSet
Output High Voltage
(I Load = -205/lAdc, VCC = min)
(I Load = -145/lAdc, VCC = min)
(I Load = -100/lAdc, VCC = min)
Typ
Symbol
I1eSet
Vdc
VOH
00·07
AO·A 15, R/Vi, VMA, E
BA
-
-
-
Output Low Voltage
(I Load = 1.6 mAdc, VCC = min)
VOL
-
-
VSS + 0.4
Power Dissipation
PO""
-
0.600
1.2
Capacitance #
(V in = 0, TA = 25 0 C, f ='1.0 MHz)
-
AO-A15, R/Vi. VMA
Cout
f
Frequency of Operation (Input Clock 74)
(Cry~tal Frequency)
fXtal
Clock Timing
Cycle Time
Clock Pulse Width
(Measured at 2.4 V)
W
pF
Cin
00-07
Logic Inputs, EXtal
Vdc
12.5
10
-
10
6,5
-
-
12
pF
0.1
1.0
-
1.0
4.0
MHz
tcyc
1.0
-
10
/lS
PWq,Hs
PWcpL
450
-
4500
ns
-
-
25
ns
Fall Time
(Measured between VSS + 0.4 V and VSS - 2.4 V)
tcp
"Except IRQ and NMI, which require 3 kn pullup load resistors for wire-OR capability at optimum operation. Does not include EXtal and
Xtal, which are crystal inputs.
"In power·down mode, maximum power dissipation is less than 40 mW.
#Capacitances are periodically sampled rather than 100% tested.
READ/WRITE TIMING (Figures 2 through 6; Load Circuit of Figure 4)
Symbol
Min
Typ
Max
Address Delay
tAD
-
-
270
ns
Peripheral Read Access Time
tacc
-
-
530
ns
tacc = tut - (tAD + tOSR)
Data Setup Time (Read)
-
ns
-
ns
Characteristic
Unit
tOSR
100
Input Data Hold Time
tH
10
Output Data Hold Time
tH
20
tAH
20
-
toow
-
165
225
ns
tpcs
tPCr, tpCf
200
-
100
ns
ns
Address Hold Time (Address, R/W, VMA)
Data Delay Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured between 0.8 V and 2.0 V)
®
MOTOROLA
-
~ern;conductor Products
9-D7
Inc.
ns
ns
MC6802
.
FIGURE 2 - READ DATA FROM MEMORY OR PERIPHERALS
Address
From MPU
Data
From MPU
2:!~~~~"":::"-""""'t-------------------4-~~-
2.0 V
or Peripherals
----::::::;;;;...J.-==='*'''-
--------------------------------c:~~~
O.B V --=~-=;=:::::;;;;;:;;;~~
t\\\%\\'f Data Not Valid
FIGURE 3 - WRITE DATA IN MEMORY OR PERIPHERALS
R/Vi
Address
FromMPU~~~~~~~~~~-----+_--~-------~~~
.J.._-----H,
Data
2.4 V _ _
From MPU----------'--------------f--0-.4-V~~-~"~r__ _ _ _ _1_f
~~
~
Data Not Valid
FIGURE 4 - BUS TIMING TEST LOAD
4.75 V
c -
=
=
R =
=
=
®
130 pF for 00-07, E
90 pF for AO·A15, RiW, and VMA
30 pF for BA
11.7 kn for 00-07, E
16.5 kn for AO·A15, RiW, and VMA
24 kn for BA
Test Point 0-.............--1'.....- . MMD6150
"
or Equiv.
c;~
R
V
"
MMD7000
or Equlv.
MOTOROLA Serniconducf:or Producf:s Inc.
9-08
r.
•
MC6802
' .
FIGURE 5 - TYPICAL DATA BUS OUTPUT DELAY
versul CAPACITIVE LOADING
600
Q
w
~
a:
oB-
500
a:
...
~
:Ii!
o(,)
enw
~
g
FIGURE 6 - TYPICAL READIWRITE. VMA. AND
ADDRESS OUTPUT DELAY versulCAPACITIVE LOADING
600
IOH 1=-20~ jJA m!x@2.14 V
IOL' 1.6 mA max@0.4V
VCC' 5.0 V
TA' 2S·C
500
...
400
2.~
l
IOH 1=_14S jJA m!x @ V
10 L • 1.6 mA max @0.4 V
VCC = 5.0 V
TA' 2S"C
400
w
w
;:: 300
;::
>- 300
Address. VMA
:Ii!
>-
g
'.
,
-
200
I--
I--
,.....
100
CI)
CI)
-
-I--
g
200
100
<
-- -_V
I-~
k- f--
r--
CL includes stray capacitance
100
oC5
w
200
300
400
500
CL includes stray capacitance
600
200
100
CL LOAD CAPACITANCE (pF)
Z
RNi
300
400
500
600
CL, LOAD CAPACITANCE (pF)
a:
oIII
CI)
o
~
<
Q
<
@
FIGURE 10 - POWER-UP AND RESET TIMING
Vee
E
20ms
Min
~tPes
>4.0V
,-------------~~------~1-~~-----1--O.S V
Reset
Option 1
(See Note below)
20 ms
Min
:-=-------------
Reset
'
rL
OV
0.8 V
RE - - - - - - - - ) -
VMA
---------,~
®
Option 2
I
I
II
tper";;100ns
II
See Figure 11 for
Power Down condition
I
~~I------------\_-----
NOTE: If option 1 is chosen, Reset and RE pins can be tied together.
MOTOROLA Se,"iconduc1:or Produc1:s Inc.
9-09
MC6802
F.IGURE 11 - POWER·DOWN SEQUENCE
VCC
tpCf 0;;;;100 ns
2.0 V
RE
FIGURE 13 - MEMORY READY CONTROL FUNCTION
A - SETUP
B -
_____2_.~;r~--------------~1I
~
0;;;;200n$
RELEASE
\0.4V ;/2;;;'300n$
tPCf 0;;;;100 ns
tPCr 0;;;;100 n$
MR
®
MOTOROLA
Sernicond!.!cto~ P~ad!.!ete
9-010
Ine.
MC6870A
+5V DC
GND
limited function microprocessor clock
250 kHz
to 2.5 MHz
~
MC6870A
~~ ~I
~2
~2
L . . ._ _ _- - - '
NMOS
NMOS
TTL
cw
~
0:
on-
specifications
DIMENSIONS
o:
PIN
o
(J
1
GND
~
3
Ne
en
w
5
0, TTL
7
v" (+5VDC)
12
13
0, NMOS
0, NMOS
18
GND
20
NC
w
22
NC
0:
24
NC
~
g
en
en
ct
PIN II LOCATION
_~~;;;;;;:~~\ i" .t"...
.221, .0'01
•u
nnn
1fL.Q20~ .010
--015071(01." PINS)
Rating
Supply Voltage
Operaling Temperalure Range
Siorage Temperalure
Power Supply Drain (max.)
CONNECTION
,005
Z
ocg
~;eC~~i~~;~;~al~',~%~~;'~tve
V/o
::!:.Ul
NMOS Oulputl at 1.0 MHz Operation"
Hl,H
Pulse Widlh (meas. al
V,,= -.3V de level)
T0 , H
Logic Levels
VOLC
VQt", NMOS
MC6~
HOLl) 1
HOLD 2
80 1120 1 160
I
I 5
I 50
I
I
I
NOle. A.II dlmenSlon •• re In Inches
WAVEFORM TIMING•
ALL TIME IN NANOSECONDS.
pi
ttl
pi
-.2
+.4
Vdc
-.2
+.4
Vdc
TEST DIAGRAM
InfO spec.lled lesl load
"Musl be eltternally held at "'" level (2 4V min. S OV mall, lit nol used
···Apply the tollowlng parameters for freQuenCies other Ihan 1 MHz
ro,H=O 5 (P.140) ns
T02H=O 5 (P.IOD) ns
h:(P'60) ns
where P=desl1ed period of operation In nanoseconds
.
L------(H5Lo1
'-------(HOLD2
CIIL - M.4.)(CAPACITY50pF
C,.MQ~
-
~22fFl6A48 ~A~...~~i;~~~IFIED
THAT SIMULATES THE MOTOROLA
Rs-(22n) SIMULATES
REAL PART Of MPU
Me6S00 MPU INPuT
·~~:l~~ ~~~g !TM.UIS\~~El
~~~~~~i~s~g"DC MAX I
MOTOROLA INC.
2553 N. Edgington
COMPONENT PRODUCTS DEPT.
Franklin Park, III. 60131
9-013
312/451-1000
.1 MC6820
ELECTRICAL CHARACTERISTICS (Vcc = 5 0 V ±5% vss
=0
TA
=0
to 70 0 C unless otherwise noted )
Symbol
Typ
Min
Max
Unit
Vdc
-
VCC
VCC
VSS + 0.4
V!;!; + 0.8
-
1.0
2.5
I'Adc
'TSI
-
2.0
10
I'Adc
PAO·PA7, CA2
I'H
-100
-250
-
I'Adc
PAO·PA7, CA2
I,L
-
-1.0
-1.6
mAdc
VSS + 2.4
VSS + 2.4
-
-
-
-
VSS + 0.4
Vdc
-205
-100
-
-
-
/JAdc
/JAdc
Characteristic
Input High Voltage
Enable
Other Inputs
VIH
VSS + 2.4
VSS + 2.0
-
Input Low Voltage
Enable
Other Inputs
VIL
VSS -0.3
VSS -0.3
lin
00·07, PBO·PB7, CB2
Input High Current
(V,H = 2.4 Vdc)
Input Low Current
(VIL = 0.4 Vdcl
Output High Voltage
(I Load - -205 I'Adc, Enable Pulse Width < 25 I's)
(I Load = -100 /JAdc, Enable Pulse Width <25I's)
R/W,Reset, RSO, RS1, CSO, CS1, CS2, CAl,
Input Leakage Current
(Vin = 0 to 5.25 Vdc)
Three·State (Off State) Input Current
(Vin = 0.4 to 2.4 Vdc)
-
Vdc
CB1, Enable
VOH
00·07
Other Outputs
Output Low Voltage
(I Load = 1.6 mAdc, Enable Pulse Width < 25 /Js)
Output High Current (Sourcing)
(VOH = 2.4 Vdc)
VOL
IOH
00·07
Other Outputs
(VO = 1.5 Vdc, the current for driving other than TTL, e.g.,
Darlington Base)
PBO·PB7, CB2
Output Low Current (Sinking)
(VOL = 0.4 Vdc)
Output Leakage Current (Off State)
(VOH = 2.4 Vdc)
Power Dissipation
IROA,IROB
Input Capacitance
(Vin = 0, TA = 25 0 C, f
Enable
= 1.0 MHz)
00·07
PAO·PA7, PBO·PB7, CA2, CB2
P./W, Reset, RSO, RS1, CSO, CS1, CS2, CAl, CBl
Output Capacitance
(V in = 0, TA = 25 0 C, f = 1.0 MHz)
Peripheral Data Setup Time (F igure 1)
IROA,IROB
PBO·PB7
-1.0
Vdc
-
-2.5
-10
mAdc
IOL
1.6
-
-
mAdc
ILOH
-
1.0
10
/JAdc
Po
-
Cin
-
-
650
20
12.5
10
7.5
mW
pF
5.0
10
pF
Cout
-
-
-
-
-
-
-
tPDSU
200
ns
tCA2
-
-
-
Delay Time, Enable negative transition to CA2 negative transition
(Figure 2, 3)
1.0
/JS
Delay Time, Enable negative transition to CA2 positive transition
(Figure 2)
tRSl
-
-
1.0
/JS
Rise and Fall Times for CA 1 and CA2 input signals (Figure 3)
tr,tf
-
-
1.0
I'S
Delay Time from CA 1 active transition to CA2 positive transition
(Figure 3)
tRS2
-
-
2.0
I'S
tpDW
-
-
1.0
I'S
tCMOS
-
-
2.0
I'S
Delay Time, Enable positive transition to CB2 negative transition
(Figure 6, 7)
tCB2
-
-
1.0
I'S
Delay Time, Peripheral Data valid to CB2 negative transition
(Figure 5)
tDC
20
-
-
ns
Delay Time, Enable positive transition to CB2 positive transition
(Figure 6)
tRSl
-
-
1.0
I'S
-
1.0
I'S
2.0
I'S
1.6
/JS
-
I'S
Delay Time, Enable negative transition to Peripheral Data valid
(Figures 4, 5)
Delay Time, Enable negative transition to Peripheral CMOS Data Valid
(VCC - 30% VCC, Figure 4; Figure 12 Load C)
PAO·PA7, CA2
Rise and Fall Time for CBl and CB2 input signals (Figure 7)
tr,tf
-
Delay Time, CB 1 active transition to CB2 positive transition
(Figure 7)
tRS2
-
Interrupt Release Time, TFiQA and IROB (Figure 8)
Reset Low Time· (Figure 9)
tlR
-
tRL
2.0
-
·The Reset line must be high a minimum of 1.0 I'S before addressing the FlA.
@
MOTOROLA Semiconductor Products Inc. _ _ _ _ _ _ _.....J
9-014
MC6820
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
-0.3 to +7.0
-0.3 to +7.0
Vdc
Storage Temperature Range
VCC
Vin
TA
T stg
a:
o
u
Thermal Resistance
°JA
en
w
BUS TIMING CHARACTERISTICS
Q
Supply Voltage
w
Input Voltage
a:
Operating Temperature Range
~
oQ.
~
~
(I)
(I)
Enable Pulse Width, High
Enable Pulse Width, Low
a:
Data Hold Time
o
(I)
Address Hold Time
Rise and Fall Time for Enable input
~
WRITE (Figures 11 and 12)
Q
ct
ct
@
82.5
°C/W
Min
1.0
leycE
PWEH
PWEL
w
oCO
°c
Symbol
Setup Time, Address and R!W valid to Enable positive transition
Data Delay Time
Z
°c
-55 to +150
Characteristic
Enable Cycle Time
o!I
Vdc
o to +70
READ (Figures 10 and 12)
g
ct
This device contains circuitry to protect the
inputs against c.amage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
10
tAH
10
-
Enable Cycle Time
Enable Pulse Width, High
leycE
PWEH
0.45
Enable Pulse Width, Low
PWEL
,",s
-
-
320
-
195
tAH
tEr, tEf
10
10
-
-
,",S
ns
ns
ns
ns
25
ns
-
,",s
,",s
25
-
,",s
-
ns
ns
25
ns
ns
ns
FIGURE 2 - CA2 DELAY TIME
(Read Mode; CRA·5 = CRA·3 = I:CRA-4 = 0)
PAO-PA7=12.0 V
PBO-PB7
._...;;0.;.;.8;...V.;....-_ _ _ _ _ __
Enable
0.4 V
tCA2
tPDSUt:
'-'2-.4-V---L
Enable
25
-
0.43
160
tDSW
tH
FIGURE 1 - PERIPHERAL DATA SETUP TIME
(Read Mode)
. .
Unit
,",s
1.0
tAS
Address Hold Time
Rise and Fall Time for Enable input
-
-
tDDR
tH
tEr, tEt
Data Hold Time
Max
-
0.45
0.43
160
tAS
Setup Time, Address and R!W valid to Enable positive transition
Data Setup Time
Typ
CA2
./
_ _ _ _----I
{v
P'
2.4 V
.• Assumes part was deselected during
the previous E pulse.
FIGURE 3 - CA2 DELAY TIME
(Read Mode; CRA-5 = 1, CRA-3 = CRA-4
Enable
= 0)
0.4 V
"
CA1
N
M2.0V.
ft~0';...8_V_ __
2L~RS2
1 .4V
2
_ _ _ _--_t_C_A......
CA2
0.4 V
@
MOTORO.LA Semiconductor Products Inc. - - - - - - - - '
9-015
MC6820
FIGURE 5 - PERIPHERAL DATA AND CB2 DELAY TIMES
(Write Mode; CRB-5 .. CRB·3 ,. 1, CRB-4 ·01
FIGURE 4 - PERIPHERAL CMOS DATA DELAY TIMES
(Write Mode; CRA·5 = CRA·3 ~ 1, CRA-4 01
g
Enable
PBO·PB7
tDC-j
CB2
2.
4V
'L.-
CB2 Note: CB2 goes low as a result of the
positive transition of Enable.
FIGURE 6 - CB2 DELAY TIME
(Write Mode; CRB·5" CRB·3" 1, CRB-4"
FIGURE 7 - CB2 DELAY TIME
(Write Mode; CRB·5" 1, CRB·3" CRB-4 ,. 01
01
CBl
2.4J!v~·
CB2
tCB2
l--------'
CB2
"Assumes part was deselected during the
previous E pulse.
FIGURE 8 -
~
2 7 -' - R
S . 2""
" ,.
2.4 V
0.4 V
'
iRa RELEASE TIME
FIGURE 9 -
RE'SEf LOW TIME
'4V
~
Enable
_
---..
Reset
r---tRL~
r-
~
tlR
.2.4F
V
IRQ _ _ _ _ _ _ _- J
"The Reset line must be a VIH for a minimum of
1.0 IlS before addressing the PIA.
FIGURE 11 - BUS WRITE TIMING CHARACTERISTICS
(Write Information into PIA)
FIGURE 10 - BUS READ TIMING CHARACTERISTICS
(Read Information from PIAl
'-------- @
,
"Assumes part was deselected during
any previous E pulse.
MOTOROLA SenJiconductor Products Inc. - - - - - - - - - '
9-016
MC6850
MAXIMUM RATINGS
. Symbol
Valua
. Unit
Supply Voltage
VCC
-0.3 to +7.0
Vdc
Input Voltage
OperatinCl Temperature Range
Vln
TA
-0.3 to +7.0
Vdc
o to +70
Storage Temperature Range
TstQ
-55 to +150
°c
°c
Thermal Resistance
liJA
82.5
'!C/W
R~lng
c
w
~
a:
oa..
a:
o
(J
~
en
w
~
g
CI)
CI)
ct
olI
w
Z
a:
o
m
CI)
o
~
ct
c
ct
@
ELECTRICAL CHARACTERISTICS (VCC - 5 0 V 15% VSS
Characteristic
a
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad·
vised that normal precautions be taken to
avoid application of any voltage higher
than maximum rated voltages to this highimpedance circuit.
0 T A - 0 to 70 0 C unless otherwise noted,)
Typ
Min
Symbol
Max
Unit
Vdc
1.0
VCC
VSS + 0.8
2.5
IlAdc
-
2.0
10
IlAdc
VSS + 2.4
VSS + 2.4
-
-
Input High Voltage
VIH
VSS + 2.0
Input Low Voltage
VIL
VSS -0.3
-
lin
-
R/W,CSO,CS 1,CS2,Enabie
Input Leakage Current
(V in = 0 to 5.25 Vdc)
Three-State (Off State) Input Current
(Vin a 0.4 to 2.4 Vdc)
00-07
ITSI
Output High Voltage
(I Load - -205 IlAdc, Enable Pulse Width <25 IlS)
(I Load a -100 IlAdc, Enable Pulse Width <25Ils)
00-07
VOH
Tx Data, RTS
Vdc
VOL
-
ILOH
-
Power Dissipation
Po
Input Capacitance
00-07
(Vin = 0, T A = 25 0 C, f = 1.0 MHz)
E Tx Clk. Rx Clk, R/W, RS, Rx Data, CSO, CS1, CS2, CTS. DCD
Cin
Output Capacitance
(Vin = 0, TA = 25 0 C, f = 1.0 MHz)
Minimum Clock Pulse Width, Low (Figure 1)
Minimum Clock Pulse Width, High (Figure 2)
RTS, Tx Data
IRQ
C out
+16, +64 Modes
Output Low Voltage
(I Load = 1.6 mAdc, Enable Pulse Width <25 IlS)
IRQ
Output Leakage Current (Off State)
(VOH = 2.4 Vdc)
+16, +64 Modes
+1 Mode
+16, +64 Modes
Clock Frequency
Clock-to-Data Delay for Transmitter (Figure 3)
Vdc
1.0
10
IlAdc
-
300
525
mW
-
10
7.0
12.5
7.5
-
-
10
5.0
pF
-
PWCL
PWCH
600
.:...
-
-
ns
600
fC
-
500
800
kHz
tTDD
-
-
1.0
IlS
-
ns
-
pF
-
+1 Mode
tRDSU
500
Receive Data Hold Time (Figure 5)
+1 Mode
tRDH
500
tRTS
tr,tf
Input Transition Times (ExcePt Enable)
-
-
tlR
Request-to-Send Delay Time (Figure 6)
-
VSS + 0.4
Receive Data Setup Time (Figure 4)
Interrupt Request Release Time (Figure 6)
Vdc
ns
-
ns
1.2
IlS
1.0
IlS
1.0"
IlS
"1.0 IlS or 10% of the pulse width. whichever is smaller.
BUS TIMING CHARACTERISTICS
READ (Figures 7 and 9)
Characteristic
Enabhi Cycle Time
Symbol
Min
Typ
tcycE
PWEH
1.0
-
Enable Pulse Width, Low
Setup Time, Address and R/W valid to Enable positive transition
PWEL
0.45
0.43
tAS
160
Data Delay Time
tDDR
tH
10
tAH
10
tEr, tEf
-
-
tcycE
PWEH
1.0
-
0.45
Enable Pulse Width, Low
Setup Time, Address and R/W valid to Enable positive transition
PWEL
0.43
tAS
160
Data Setup Time
tDSW
tH
195
tAH
10
tEr, tEf
-
Enable Pulse Width, High
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable input .
WRITE (Figure 8 and 9)
Enable Cycle Time
Enable Pulse Width, High
Data Hold Time
Address Hold Time
RiSe and Fall Time for Enable input
@
-
10
-
Max
-
Unit
:lb
IlS
-
IlS
ns
320
ns
IlS
ns
ns
25
ns
IlS
25
IlS
-
-
IlS
ns
-
-
ns
25
ns
ns
ns
MOTOROLA SenJiconduct:or Product:s Inc. _ _ _ _ _ _ _......1
9-017
MC6850
FIGURE 2 - CLOCK PULSE WIDTH. HIGH·STATE
FIGURE 1 - CLOCK PULSE WIDTH. LOW·STATE
Tx Clk
Tx Clk
or
Ax Clk
Ax Clk
FIGURE 4 - RECEIVE DATA SETUP TIME
(+1 Mode)
FIGURE 3 - TR"ANSMIT DATA OUTPUT DELAY
TxClk
~
Tx Data
--------..~ro-2:-;-:-----
0.8 V
AXDat~2'OV
--------------------
/
r:::
0.8V
~
'RD'"
Ax Clock
_ _ _ _¥0.8V
FIGURE 5 - RECEIVE DATA HOLD TIME
(+1 Mode)
FIGURE 6 - REQUEST·TO·SEND DELAY AND
INTERRUPT·REQUEST RELEASE TIMES
Enable
ATS
tlA-L
IRQ
FIGURE 7 - BUS READ TIMING CHARACTERISTICS
(Read information from ACIA)
________~
_ ___Jj22.4.4
V
FIGURE 8 - BUS WRITE TIMING CHARACTERISTICS
(Write information into ACIA)
Enable
AS,CS,A/W
Data Bus
@
MOTOROLA Setniconductor Products Inc. _ _ _ _ _ _ _..J
9-018
,
MC6852
.
.
,
~
' . . ' ,
MAXIMUM RATINGS
Rating
0'
w
~,
0::'
oa.
0::
o
Symbol
Supply Voltage
Input Voltage
V.lu.
-0.3 to +7.0
VCC
Yin
TA
T stg
Operating Temperature Range
Storage Temperature Range
Thermal Resistance
-0.3 to +7.0
o to +70
°C
OC
-55 to +150
70
()JA
This device contains circuitry to protect
the inputt against damage due to high
static voltages or electric fields; however,
is is advised that normal precautions be
taken to avoid epplicatlon of any voltage
higher than maximum ratad voltages to
this hlgh-Impedanca circuit.
Unit
Vdc
Vdc
Ocm
U
~
iii
ELECTRICAL CHARACTERISTICS (VCC
w
~
g
en
en
c(
all
w
Z
0::
o
m
en
o
~
c(
o
c(
@
= 5.0 V ±5%, VSS = 0, T A = 0 to 70 0 C unless otherwise noted.l
Characteristic
Input High Voltage
Input Low Voltage
Symbol
Min
Typ
Max
Unit
VIH
VIL
lin
VSS + 2.0
-
-
-
1.0
VSS + 0.8
2.5
Vdc
Vdc
SlAde
-
2.0
10
SlAde'
VSS + 2.4
-
-
VSS + 2.4
Tx Clk, Rx Clk, Rx Data, Enable,
Input Leakage Current
(Vin = 0 to 5.25 Vdc)
Reset, RS, RIW, CS, OCD, CTS
00-07
Three-State (Off State) Input Current
(Vin = 0.4 to 2.4 Vck, VCC = 5.25 Vdc)
Output High Voltage
00-07
il Load = -205 SlAdc, Enable Pulse Width <25/As)
ULoad = -100 SlAdc, Enable Pulse Width <25/As) _ _
Tx Data, OTR, TUF
Output Low Voltage
(lLn..n = 1.6 mAdc, Enable Pulse Width <25/As)
IRQ
Output Leakage Current (Off State)
(VOH = 2.4 Vdc)
Power Dissipation
I nput Capacitance
00-07
(Vin = 0, T A = 25 0 C, f = 1.0 MHz)
All Other Inputs
Output Capacitance
Tx Data, SM/OTR, TUF
IRQ
(Vin = 0, TA = 25 0 C, f = 1.0 MHz)
Minimum Clock Pulse Width, Low (Figure 1)
Minimum Clock Pulse Width, High (Figure 2)
Clock Frequency
PWCL
PWCH
fC
700
700
Recaive Data Setup Time (Figure 3, 7)
Receive Data Hold Time (Figure 3)
Sync Match Delay Time (Figure 3)
Clock-to-Oata Delay for Transmitter (Figure 4)
Transmitter Underflow (Figure 4,6)
OTR Delay Time (Figure 5)
tROSU
tROH
tSM
tTOO
tTUF
tOTR
350
Interrupt Request Release Time (Figure 5)
Reset Minimum Pulse Width
CTS Setup Time (Figure 6)
OCO Setup Time (Figure 7)
Input Rise and Fall Times (except Enable)
(0.8 V to 2.0 V)
'1.0 SlS or 10",(, of the pulse width, whichever is smaller.
FIGURE 1 - CLOCK PULSE WIDTH, LOW-STATE
ITSI
VOH
Vdc
-
VOL
-
-
VSS+0.4
Vdc
ILOH
-
1.0
10
SlAdc
Po
-
300
525
mW
pF
-
-
12.5
7.5
10
5.0
Cin
Cout
350
-
-
-
-
-
-
600
-
-
-
1.0
1.0
1.0
1.0
-
1.2
-
IIR
tR ...
1.0
-
-
tCTS
toco
tr.tf
-
-
200
500
1.0'
-
pF
ns
ns
kHz
ns
FIGURE 2 - CLOCK PULSE WIDTH. HIGH-STATE
-PWCL-
TXClk~
or
'
Rx Clk
O.BV
V-
TXClk~
or
2.0V
'
Rx Clk
~L
-PWCH-
MOTOROLA Semiconductor Products Inc.
9-019
ns
/AS
/AS
/AS
/AS
/AS
/AS
ns
ns
/AS
MC6852
'.
.
.
.
.
BUS TIMING CHARACTERISTICS
READ IF'Igures 8 an d 101
Symbol
Min
Typ
Max
Unit
Enable Cyele Time
teyeE
PWEH
25
En~ble
PWEL
tAH
10
10
-
IlS
Enable Pulse Width, High
1.0
0.45
0.43
160
tEr, tEf
-
-
Enable Cycle Time
teyeE
Enable Pulse Width, High
PWEH
Enable Pulse Width, Low
PWEL
1.0
0.45
0.43
160
-
Characteristic
Pulse Width, Low
Setup Time, Address and R/W valid to Enable positive transition
Data Delay Time
tAS
tDDR
tH
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable input
-
-
Il s
IlS
ns
320
ns
-
ns
25
ns
-
,IlS
ns
WRITE (Figures 9 and 101
Setup Time, Address and R/W valid to Enable positive transition
tAS
Data S!ltup lime
tDSW
Data Hold lime
tH
Address Hold Time
tAH
Rise and Fall Time for Enable input
tEr, tEf
195
10
10
-
25
-
Il S
I'S
ns
ns
-
ns
25
ns
ns
FIGURE 3 - RECEIVE DATA SETUP'AND HOLD TIMES AND SYNC MATCH DELAY TIME
DO
Rx Clk
Rx
Data
Number of bits in character
~=
Don't care
0.4 V
Sync Match
t-----~ ~e~l~dClk--_~
FIGURE 4 - TRANSMIT DATA OUTPUT DELAY AND
TRANSMITTER UNDERFLOW DELAY TIME
FIGURE 5 - DATA TERMINAL READY AND INTERRUPT
REQUEST RELEASE TIMES
2.0 V
Enable
tlR
---J}--~__' 2.4 V
TUF _______________- J
_________
n
=
Number of bits in character
®
MOTOROLA Semiconductor Products Inc.
9-020
.
,
, MC6852.
•
~
•
FIGURE 6
c
'f
,
CLEAR-TO-5END SETUP TIME
\
I
FIGURE 7 - DATA CARRIER DETECT SETUP TIME
w
!ia:
o0.
a:
o(.)
~
ui
w
!i
C3
oC/)
Tx elk
O.B V
Rx elk
--Ir
C/)
«
olJ
w
Z
Tx oata _ _ _ _ _ _ _ _ _ _ _
a:
)fUlV
Rx Data _ _ _ _ _ _ _....'~ V
DO
DO
o
III
C/)
o
~
«c
«
FIGURE 8 - BUS READ TIMING CHARACTERISTICS
(Read information from SSDAI
FIGURE 9 - BUS WRITE TIMING CHARACTERISTICS
(Write information..,into SSDAI
@
Enabl.
Data
BUI
FIGURE 10 - BUS TIMING TEST LOADS
Load B
(IRQ Onlvl
Load A
(00-07, OTR, Tx Data, TUF)
RL
...
R
a
3 k
MMD6150
~, or Equiv.
~,
~,
e
= 2.5 k
-+
Test Point 0-:........_--I0Il
..........
Test Point
MM07000
or Equiv.
130 pF for 00-07
pF for OTR, Tx Data, and TUF
R
= 11.7
k!1 for 00-07
= 24 k!1 for OTR, Tx'Oata, and TUF
~ 30
®
~roo"
5'OV
5.0 V
MOTOROLA Semiconductor Products Inc.
9-D21
.
MC6840
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
-0.3 to +7.0
Vdc
Input Voltage
Vin
-0.3 to +7.0
Vdc
Operating Temperature Range
TA
o to +70
°c
Supply Voltage
Storage Temperature Range
Tstg
liJA
Thermal Resistance
. ELECTRICAL CHARACTERISTICS
This device contains. circitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum
rated voltages to this high-impedance circuit.
-55to+150
°c
82.5
°C/W
(Vee = 5.0 V ±5%, VSS = 0, TA = 0 to 70 0 e unless otherwise noted)
Max
Unit
VCC
Vdc
Symbol
Min
Typ
Input High Voltage
VIH
VSS +2.0
Input Low Voltage
VIL
VSS -0.3
-
VSS +0.8
lin
-
1.0
2.5
J..tAdc
ITSI
-
2.0
10
J..tAdc
VSS +2.4
VSS +2.4
-
-
-
-
-
-
VSS +0.4
VSS+0.4
Characteristic
Input Leakage Current
(Vin = 0 to 5.25 V)
Three-State (Off State) Input Current
(Vin = 0.4 to 2.4 V)
00-07
Output High Voltage
(I'oad = -205 J..tA)
(I'oad = -200 J..tA) .
Vdc
VOH
00-07
Other Outputs
Output Low Voltage
(I load = 1.6 mAl
(I load = 3.2 mAl
VOL
00-07
01-03,IRQ
Vdc
ILOH
-
1.0
10
J..tAdc
Power Dissipation
Po
-
-
550
mW
Input Capacitance
(V in = 0, TA = 25 0 C, f = 1.0 MHz)
Cin
-
-
-
12.5
7.5
-
-
-
-.
5.0
10
Symbol
Min
Max
Unit
J..ts
Output Leakage Current (Off State)
(VOH = 2.4 Vdc)
IRQ
Output Capacitance
(V in = 0, TA = 25 0 C, f = 1.0 MHz)
00-07
All others
pF
pF
Cout
IRQ
01,02,03
BUSTIMINGCHARACTERISTICS
Characteristic
READ (See Figures 2 and 8)
Enable Cycle Time
tcycE
1.0
10
Enable Pulse Width, High
PWEH
0.45
4.5
Enable Pulse Width, Low
PWEL
0.43
J..ts
tAS
160
-
Data Delay Time
to DR
-
320
ns
Data Hold Time
tH
10
-
ns
tAH
10
-
ns
tEr, tEf
-
25
ns
Setup Time, Address and R/W valid to enable positive transition
Address~old
Time
Rise and Fall Time for Enable input
J..ts
ns
WRITE (See Figures 3 and 8)
Enable Cycle Time
tcycE
1.0
10
J..ts
Enable Pulse Width, High
PWEH
0.45
4.5
J..ts
Enable Pulse Width, Low
PWEL
. 0.43
Setup Time, Address and R/W valid to enable positive transition
tAS
160
Data Setup"Time
tDSW
195
Data Hold Time
tH
10
tAH
tEr, TEf
Address Hold Time
Rise and Fall Time for Enable input
®
J..ts
ns
ns
ns
10
-
-
25
ns
MOTOROLA Serniconducf:or.Producf:s
9-022
-
In~.·
ns
MC6840
'
.... t
_
...
""
........
___ " " .
~,
"
.!."
. . . . '''''
'"
_
-
. .
......." ' " . .
•
"
,
•
•
cw
~
a:
oQ.
a:
o
u
AC OPERATING CHARACTERISTICS
Characteristic
Symbol
C, G and Reset
Input Rise and Fall Times
Input Pulse Width Low (Figure 4)
e, G and Reset
e,G
e, G and Reset
~
Input Pulse Width High (Figure 5)
u)
w
Input Setup Time (Figure 6)
(Synchronous Mode) -
C3 (-;-8 Prescaler Mode only)
gen
Input Hold Time (Figure 6)
(Synchronous Mode)
-C3
~
en
c:(
o!I
w
2:
e, G and Reset
(+8 Prescaler Mode only)
Output Delay, 01-03 (Figure 7)
(VOH = 2.4 V, Load A)
(VOH = 2.4 V, Load C)
(VOH = 0.7 VDD, Load C)
TTL
MOS
CMOS
a:
Interrupt Release Time
IJl
't r and tf .; 1 x Pulse Width or 1.0 IlS, whichever is smaller.
o
en
Min
tr,tf
PWL
tcycE + tsu + thd
PWH
tcycE + tSi . + thd
~
tsu
200
thd
50
-
-
-
tco
tcm
tcmos
-
tlR
Max
Unit
1.0'
IlS
-
ns
-
ns
-
ns
700
450
2.0
ns
ns
IlS
1.6
IlS
ns
o
:E
c:(
cc:(
@
FIGURE 2 - BUS READ TIMING CHARACTERISTICS
(Read Information from PTM)
FIGURE 3 - BUS WRITE TIMING CHARACTERISTICS
(Write Information into PTM)
FIGURE 5 - INPUT PULSE WIDTH HIGH
FIGURE 4 - INPUT PULSE WIDTH LOW
C1-C3
C1-C3
G1-G3
Gi-G3
Reset
®
MOTOROLA Serniconduc-tor Produc-ts' Inc.
9-023
MC6840
FIGURE 6 - INPUT SETUP AND HOLD TIMES
FIGURE 7 - OUTPUT DELAY
Enable
C1-C3, G1-G3,
RESE'f
FIGURE 8 - IRQ RELEASE TIME
,",,,·t.,"~,
TAO _
_ _ _ _ _ _ _ _---J
_
2.4 V
FIGURE 9 - BUS TIMING TEST LOADS
Load A
(00-07)
Load B
(01,02,03)
5.0 V
VCC
RL= 2.5 k
130 pF;;;;; .
RL= 1.25 k
MM06150
....
Test Point
~,
11.7 k
~
,
........
Test Point
or Equiv.
11.7 k
40 pF
MMO 7000
or Equiv.
~
-=
":::-
MM06150
~,
,
I
~
-=
of device under test
or Equiv.
MM07000
or Equiv.
Load C
(IRQ Only)
5.0 V
Test Point
d"
Load 0
(CMOS Load)
Test Point
,,,,, I
®
1
r"
MOTOROLA Semiconductor Products Inc.
9-024
MC6844
'.'-, '··-'V". ..
,,' . ...;. ' . .
" ...' ~.',
"
',-
"
0
' .
"'"
••
•
cw
!ia:
o0.
a:
o
o
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC·
-0.3 to +7.0
Vdc
Vin'
-0.3 to +7.0
Vdc
TA
o to +70
Storage Temperature Range
Tstg
-55 to +150
°c
uc
Thermal Resistance
ROJA
82.5
uC/W
Supply Voltage
~
Input Voltage
en
w
Operating Temperature Range
!i
g
CI)
CI)
Permanent device damage may occur
if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should
be reuricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to
higher than recommended voltages for
extended periods of time could affect
device reliability.
'In respect to Vss.
c(
o!I
w
Z
RECOMMENDED OPERATING CONDITIONS
a:
o
a:I
Symbol
Value
Unit
Power Supply Voltage
VCC
+4.75 to +5.25
Vdc
Input Voltage
VIL
VIH
-0.3 to +0.8
2.0 to VCC
Vdc
Operating Ambient Temperature Range
TA
o to +70
uC
Rating
CI)
o
~
c(
c
c(
@
ELE.CTRICAL CHARACTERISTICS (VCC - 5.0 V ± 5%, VSS
=
0, TA
= -20 to +75 0 C unless otherwise noted)
Symbol
Min
Typ
Input High Voltage
VIH
VSS +2.0
Input Low Voltage
VIL
VSS -0.3
VSS +0.8
Vdc
lin
-
-
2.5
/JAde
ITSI
-10
-
10
/JAde
VSS +2.4
VSS +2.4
VSS +2.4
-
-
Characteristic
Input Leakage Current
(Vin = 0 to 5.25 V)
TXIRQO-3,2 DMA, RES, DGRNT
Three-State Leakage Current
(Vin ~ 0,4 to 2.4 V)
AO-A15, RIW
00-07
Output High Voltage
(I Load = -205 /JAde)
(I Load = -145 /JAde)
(lLoad = -100 /JAde)
Unit
Vdc
Vdc
VOH
00-07
AO-15, R/Vii
All Others
Max
VCC
-
-
VOL
-
-
VSS +0.4
ICSS
-
10
-
Power Dissipation
Po
-
500
-
Capacitance
(V in ~O, TA = 25 0 C, f = 1.0 MHz)
Cin
-
-
Output Low Voltage
(lLoad = 1.6 mAde)
Source Current
(Vin = 0 Vdc, Figure 10)
Cs/Tx AKB
2DMA
00-07, Cs, AO-A4, R/Vii
All Others
Cout
®
Vdc
-
-
MOTOROLA Semiconductor Products Inc.
9-D25
mW
pF
20
12.5
10
12
pF
",.
MC6844 .
.
.
\.
"',
.-
~
" .
.
_, .
BUS TIMING CHARACTERISTICS (Load Condition Figure 11)
·1
Characteristic
Symbol
Min
Max
Unit
READ TIMING (Figure 4)
Address Setup Time
AO-A4~RIW,CS
tAS
160
-
ns
Address Input Hold Time
AO-A4, RIW, CS
tAHI
10
ns
Data Delay Time'
00-07
tOOR
-
320
ns
Data Access Time
00-07
tACC
-
480
ns
Data Output Hold Time
00-07
tOHR
10
-
ns
WRITE TIMING (Figure 4)
Address Setup Time
AO-A4,RIW,CS
tAS
160
Address Input Hold Time
AO-A4, RIW,CS
tAHI
10
Data Setup Time
00-07
tosw
195
Data Input Hold Time
00-07
tOHW
10
-
Symbol'
Min
Max
Unit
tCYC
PWH
PWL
1000
-
ns
Pulse Width-High
Low
450
430
-
Rise and Fall Time
t¢r,t¢f
-
25
Tx RQ Setup Time (Figure 5)
¢2 OMA Rising Edge
¢2 OMA Falling Edge
tTQSl
tTQS2
120
210
-
Tx RQ Hold Time (Figure 5)
¢2 OMA Rising Edge
¢2 OMA Falling Edge
tTQHl
tTQS2
20
20
OGRNT Setup Time (Figure 6)
tOGS
155
OGRNT Hold Time (Figure 6)
tOGH
10
ns
ns
ns -.
ns
CLOCK TIMING
Characteristic
¢2 OMA (See Figure 4)
Cycle Time
ns
ns
OMA TIMING (Load Condition Figure 11)
ns
ns
Address Output Delay Time (Figure 15)
tAD
-
AO-15, R/W
Tx STB
tAHO
30
35
AO-A15, RIW
tATSO
AO-A15, RIW, Tx STB
Address Output Hold Time (Figure 15)
Address Three-State Delay Time (Figure 8)
Address Three-State Recovery Time (Figure 8)
Delay Time (Figure 7)
tATSR
ORQH,ORQT
tOQO
Tx AK Delay Time
¢2 OMA Rising Edge (Figure 7)
OGRNT Rising Edge (Figure 10)
tTKOl
tTK02
IRQ/DENO Delay Time
¢2 OMA Falling Edge (Figure 8)
OGRNT Rising Edge (Figure 10)
tOEOl
tOE02
®
-
-
-
-
270
-
ns
ns
ns
ns
700
ns
400
ns
375
ns
ns
400
190
ns
-
-
300
190
MOTOROLA, Semiconductor Products Inc. ,
9-026
MC6844
.
'"
..... .
•
.•
..' ,
cw
~
a:
oA-
FIGURE 4 - READ/WRITE OPERATION SEQUENCE
FIGURE 7 -
DiffiH. DRQT. TxAK OUTPUT TIMING
a:
o
tJ>2DMA
CJ
~
enw
~
g
U)
U)
ct
tJ>2DMA
AO-A4 (Input)
R/ON (Input)
TxAKA
CS/Tx AKB (Output) _ _ _ _ _....J -,:.;:;.;...;.....;...._ _ __
Cs (Input)
011
w
Z
a:
FIGURE 8 - ADDRESS. IRO/DEND OUTPUT TIMING
oCD
U)
o
:IE
(Write Operation)
ct
c
ct
AO-A15 (Output)
R/ON (Output), Tx STB _ _+-J
@
.,.~~-------r
FIGURE 5 - Tx RQ INPUT TIMING
FIGURE 9 - ADDRESS THREE·STATE TIMING
tJ>2DMA
(or DGRNT)
AO-A15, RM
FIGURE 6 - DGRNT INPUT TIMING
Satup Timing
:::
F
tJ>2DMA~
DGRNT
._
tJ>2DMA
(or DGRNT)
~
~~l-tDGS
FIGURE 10 - Tx AKB, IRO/DEND
OUTPUT TIMING FROM DGRNT INPUT
jO.8V
'DGH
DGRNT
_ _ _ _ _ _.....JI
0.8 V
Hold Timing
tJ>2DMA
tATSD~
---------2-
2.4 V
AO-A15, R/ON
2.0 V
0.8 V
®
K=
DGRNT
CS/Tx AKB (Output)
MOTOROLA Semiconductor Products Inc.
9-027
0.4 V
'"
MC6844 '
..,..
•.
.
•
.
.
.
,
.
.
'-
FIGURE 12 - Cs/TxAKB
SOURCE CURRENT TEST CIRCUIT
FIGURE 11 - TEST LOADS
1---------------,
5.0 V
01
Test Point
...
~
o-...._-~I_
e
R
I
.Vee
2.5 k
02
TxAKB
03
I
04
Meter
C=pF
Rckn
00-07
130
11.7
Test Pin
AO-A15, R/W
90
16.5
eS/Tx AKB
50
24
Others
30
24
Vss
Enable
es
Input
L- _ _ _ _ _ _ _ _ _ _ _ _
9-028
..J
MC6846
....
A'.
•
__
_."!
....,.
~"
, I
_
MAXIMUM RATINGS
Rating
Q
w
~
a:
oQ.
a:
o
o
Symbol
SupplV Voltage
Input Voltage
Operating Tempera!uni Range
Storage Temperature Range
VCC
Vin
TA
T stg
Thermal Resistance
°JA
Value
-0.3 to +7.0
-0.3 to +7.0
o to +70
-55 to +150
70
Unit
Vdc
Vdc
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
is is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high·impedance circuit.
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oC
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ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 5%, VSS = 0, TA = 0 to 70 0 C unless otherwise noted.l
Characteristic
Input High Voltage
All Inputs
All Inputs
Input Low Voltage
Clock Overshoot/Undershoot - Input High Level
- Input Low Level
Input Leakage Current
RlW, Reset, CSO, CSl
(Vin = 0 to 5.25 Vdc)
CP1, CTG, CTC. E. AO-Al0
Three-State (Off State) Input Current
00-07
(Vin 004 to 204 Vdc)
PPO-PP7. CP2
Output High Voltage
(I Load = -205 !lAde.)
00-07
(I Load = -200 !lAdc)
Other Outputs
Output Low Voltage
(I Load = 1.6 mAde)
(I Load = 3_2 mAde)
Output High Current (Sourcing)
(VOH = 204 Vdc)
Min
TVp
Max
Unit
VIH
-
VIL
VOS
VSS + 2.0
VSS -0.3
VCC -0.5
VSS -0.5
Vdc
Vdc
Vdc
lin
-
1.0
VCC
VSS + O.B
VCC + 0.5
VSS + 0.5
2.5
!lAdc
ITSI
-
2_0
10
!lAdc
VSS + 204
VSS + 204
-
-
-
-
VSS + 004
VSS + 004
-205
-200
-
-
-
-
-1.0
-
-10
1.6
3.2
-
-
ILOH
-
-
10
/lAde
Po
-
-
mW
pF
-
1000
20
12.5
10
7.5
0.1
5.0
10
1.0
pF
f
-
MHz
"leveE
1.0
!lS
2
-
-
tRL
tlR
VOL
-
Vdc
VOH
00-07
Other Outputs
Vdc
/lAde
IOH
00-07
Other Outputs
(VO = 1.5 Vdc, the current for driving other than TTL, e.g .•
Darlington Base)
CP2. PPO-PP7
Output Low Current (Sinking)
(VOL = 004 Vdc)
00-07
Other Outputs
IRQ
Output Leakage Current (Off State)
(VOH = 204 Vdc)
Power Dissipation
Capacitance
(Vin = O. TA = 25 0 C. f = 1.0 MHz)
00-07
PPO-PP7. CP2
AO-Al0. RiW. Reset. CSO. CS1. CPl. CTC. CTG
IRQ
PPO-PP7. CP2. CTO
Frequencv of Operation
Clock Timing
Cvcle Time
Reset Low Time
Interrupt Release
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MC6846
READ/WRITETIMING (Figures 3 and 4)
Characteristic
Enable Pulse Width, Low
Enable Pulse Width, High
Set Up Time (Address eso, CS1, Rm)
Data Delay Time
Data Hold Time
Address Hold Time
Rise and Fall Time
Data Set Up Time
"
Symbol
Min
Typ
Max
PWEL
PWEH
430
430
160
-
-
-
-
320
10
10
-
-
tAS
tDDR
tH
Unit
ns
ns
ns
ns
195
-
25
tDSW
-
ns,
ns
ns
ns
Symbol
Min
Typ
Max
Unit
tPDSU
tPr' tpc
200
-
-
ns
1.0
IlS
1.0
IlS
tAH
tEf,tEr
-
-
BUS TIMING
Peripheral 1/0 LInes
Characteristic
Peripheral Data Setup
Rise and Fall Times CP1, CP2
Delay Time E to CP2 Fall
tCP2
tDC
Delay Tme 1/0 Data CP2 Fall
Delay Time E to CP2 Rise
,Delay Time CPl to CP2 Rise
Peripheral Data Delay
Peripheral Data Setup Time for Latch
tRSl
tRS2
tPDW
tpsu
tPDH
Peripheral Data Hold Time for Latch
Timer-Counter Lines
Input Rise and Fall Time
,!nput Pulse Width High
(Asynchronous Mode)
Input Pulse Width Low
(Asychronous Mode)
Input Setup Time
(Synchronous Mode)
Input Hold Time
(Synchronous Mode)
Output Delay
CTC and CTG
20
-
-
-
100
15
-
-
-
ns
1.0
2.0
1.0
IlS
-
ns
ns
IlS
IlS
tCR, tCF
!eyc + 250
-
100
tPWH
-
ns
ns
tPWL
t cyc + 250
-
-
ns
tsu
200
-
ns
thd
60
-
-
tCTO
-
-
1.0
FIGURE 3 - BUS READ TIMING
Read Information from MC6846)
ns
IlS
FIGURE 4 - BUS WRITE TIMING
(Write Information from MPU)
Am, A, CS
Data Bus
Aiw,A,CS
FIGURE 5 - PERIPHERAL PORT LATCH SETUP AND HOLD TIME
Data Bu.
PPO·PP7
2.0 V
CPl
0.8 V
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Chapter 10
THE MOS TECHNOLOGY MCS6500
In many ways the MCS6500 microcomputer systems can be compared to the Zilog zao, which we described in
Chapter 7. Just as the zao is an enhancement of the aOaOA, which is described in Chapter 4, so MOS Technology's products are enhancements of the MC6aOO, which we described in Chapter 9.
But there are some interesting conceptual differences between the way MOS Technology went about enhancing the MC6aOO, as compared to the product enhancement philosophy adopted by Zilog.
The zao is indeed an enhancement of the aOaOA, but only to the extent that the aOabA instruction set is a
subset of the zao instruction set; there are architectural similarities between the zao and the aOaOA, but
System Bus philosophies are markedly different. It would be hard to look upon the zao as simply another mem~
ber of the aOaOA ,family of microcomputer devices.
The MCS6500 product line, by way of contrast, can be looked upon as a CPU whose philosophical concepts
agree closely with the MC6aOO product line -without being in any way compatible, either in terms of instruction set or System Bus philosophy. While on the surface it may appear as though MCS6500 CPUs represent some
form of an MC6800 superset. this is not the case. System Busses are sufficiently different that you could not consider
replacing an MC6800 CPU with an MCS6500 equivalent. leaving other logic unaltered. Instruction sets are similar. but
deceptively so. In reality. the instruction sets are sufficiently different that converting an MC6800 source program to its
MCS6500 equivalent is nosimple task. It would be completely impossible to take an MC6800 program ROM and use it
to drive an MCS6500 CPU. Recall that you can take an 8080A program ROM and use it to drive a Z80 CPU.
Since this chapter is devoted to the MOS Technology product line, let us begin by summarizing the components
of this product line, and the principal CPU enhancements that have been made.
The MaS Technology devices described in this chapter consist of nine CPUs. plus two support circuits. A third support
circuit is described in Chapter 9.
The nine CPUs share the same instruction set and addressing modes. but have minor differences in packaging and
system interface. Table 10-1 summarizes the nine CPUs.
The two support circuits which are described in this chapter are the MCS6522 Peripheral Interface Adapter and the
MCS6530 combination logic device. Another PIA. the MCS6520 PIA. is identical to the MC6852 PIA; for a description
of this device see Chapter 9.
MCS6500 support devices are described in this chapter rather than in Volume 3, because, like the MC6aOO, the
MCS6500 relies on a synchronizing clock signal. While it would be possible to use MCS6500 support devices
with other microprocessors, the extra 'Iogic needed in order to create MCS6500 compatible bus interfaces
would not be sufficiently rewarded by the specific capabilities of the support parts themselves. MCS6500 support devices can be used with MC6800 microprocessors and. conversely. MC6800 support devices can be used with
the MCS6500 CPU.
In order to enhance the MC6aOO CPU, MOS Technology made a number of useful yet obvious instruction set
changes; they also made a number of subjective architectural changes which might have significant impact in
particular applications, but which in general result in products that adhere quite closely to MC6aOO philosophy.
The most important enhancement that MOS Technology has made is to develop a whole family of CPU devices.
The second most important feature of the MCS6500 line of CPU devices is the fact that the MCS650X series
CPUs contain on-chip clock logic; therefore. when using these CPUs.you do not need an MC6870 series clock device.
However. you will need an external crystal oscillator or RC network - which is typical of any microprocessor with onchip clock logic.
Another important feature of all MCS6500 series CPUs is that you cannot float the Address and Data Busses
separately during <1>1 high and <1>1 low clock pulses, and there is no HALT condition. Also, you cannot stretch
clock pulses. Slow memories are accommodated in the more traditional manner. by allowing you to insert extra
machine cycles. equivalent to 8080A Wait states.
10-1
If you are making extensive use of clock stretching. or DMA data transfers during Halt states. in an MC6800 microcomputer system. switching to an MCS6500 CPU will require considerable system redesign.
In order to refresh dynamic memory in an MCS6500 system, you must "steal" machine cycles by inserting Wait
states, as you would for slow memories.
MOS Technology, the principal manufacturer of the MCS6500 product line, is located at:
MOS TECHNOLOGY. INC.
950 Rittenhouse Road
Norristown. PA 19401
Second sources are:
SYNERTEK. INC.
1901 Old Middlefield Way
Mountain View. CA 94043
ROCKWELL INTERNATIONAL
Microcomputer Division
337 Miraloma Avenue
Anaheim. CA 92803
The MCS6S00 devices use a single +5V power supply. Using a 1 microsecond clock, instruction execution
times range from 2 to 12 microseconds.
All MCS6500 devices have TTL compatible signals.
N-channel, silicon gate, depletion load MOS technology is used for MCS6500 devices.
THE MCS6500 SERIES CPUs
Functions implemented on each of the MCS6500 CPUs are illustrated in Figure 10-1. As this figure would imply,
capabilities offered by the various MCS6500 CPUs differ in scope rather than function.
Table 10-1. A Comparison of MCS6500 Series and the MC6800 CPU Devices
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6503
6504
6505
6506
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AO-A15
AO-All
AO-A12
AO-All
AO-All
AO-A15
00-07
00-07
00-07
00-07
00-07
00-07
6513
6514
6515
MC6800
AO-All
AO-All
AO-All
AO-A15
00-07
00-07
00-07
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CPU PINS 'AND SIGNAls
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28
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40
·The second name is the name used by MC6800 literature for the same signal.
This is the on-chip-clock version of the 6512.
This is the on-chip-clock version of the 6513.
This is the on-chip-clock version of the 6514.
This is the on-chip-clock version of the 6515.
On-chip-clock version. 4K memory.
1. <1>2
DBO - DB7
ABO- AB15
ROY
Input
Input
Output
Tristate. bidirectional
Output
Data Bus
Address Bus
Singl~ cycle contr~1
Set Overflow flag
Identify op code fetch cycle
Power and Ground
SO
SYNC
VCC.VSS
Input
Input
Output
Figure 10-2. MCS~502 Signals and Pin Assignments
RESET
Vss
rna
NMi
VCC
ABO
ABI
AB2
AB3
AB4
AB5
AB6
AB7
AB8
8
9
10
11
12
13
14
MCS6503
.28
27
26
25
24
23
22
21
20
19
18
17
16
15
<1>2
2
DBO- DB7
ABO-ABll
Vcc. Vss
Reset
CPU clock
System clock
Data Bus
Address Bus
Power and Ground
Figure 10-3. MCS6503 Signals and Pin Assignments
10-8
RESET
28
Vss
27
<1>0
26
R/W
25
24
DBl
rna
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5
AB1
6
7
AB2
AB3
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8
23
MCS6504
AB4
0
0
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Vee
ABO
w
4(
22
21
20
10
<1>2
000
DB2
DB3
DB4
DB5
000
ABS
AB6
AB7
11
12
17
DB7
AB12
AB8
AB9
13
14
16
15
AB11
AB10
19
18
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Pin Name
Description
Type
4(
R/W
GIS
iRa
RESeT
Read/Write control
Interrupt request
Reset
Output
Input
Input
CPU clock
System clock
Input
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III
<1>2
0
DBO~DB7
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4(
Q
Output
Tristate. bidirectional
ABO-AB12
Data Bus
Address Bus
VCe. Vss
Power and Ground
Output
4(
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Figure 10-4. MCS6504 Signals and Pin Assignments
ReSET
28
Vss
ROY
IRQ
27
26
25
3
4
24
5
6
VCC
ABO
AB1
AB2
MCS6505
·AB3
AB4
ABS
AB6
9
.20
10
11
19
18
17
12
13
14
·AB7
ABS
23
22
·21
'<1>2
<1>0
R/W
000
DBl
DB2
DB3
DB4
DB5
DB6
DB7
16
AB11
AB10
15
AB9
Type
Pin Name
Description
R/W
Read/Write control
Output
iRci
RESET
Interrupt request
Input
Reset
<1>0
CPU clock
System clock
Input
Input
Output
<1>2
ROY
Data Bus
Address Bus
::;ingle cycle control
VCC. Vss
Power and Ground
DBO - DB7
ABO-AB11
Tristate •. bidirectional
Output
Input
Figure 10-5. MCS6505 Signals and Pin Assignments
10-9
· R'ESEi'
<1>2
Vss
<1>1
IRQ
VCC
ABO
ABI
27
c1JO
26
25
24
R/Vii
23
MCS6506
AB2
AB3
AB4
10
AB5
AB6
AB7
11
AB8
14
22
DB3
21
20
DB4
19
18
17
12
DBO
OBI
DB2
DB5
·DB6
DB7
ABll
16
AB10
15
AB9
Pin Name
Description
Type
R/Vii
Read/Write control
Interrupt request
Output
Input
c1JO
<1>1. <1>2
Reset
CPU clock
System clocks
Input
Input
OBO - DB7
Data Bus
ABO - ABll
Address Bus
Power and Ground
iRci
RESET
VCC.VSS
Output
Tristate. bidirectional
Output
Figure 10-6. MCS6506 Signals and Pin Assignments
1
2
40
39
3
38
37
36
35
4
5
6
7
8
9
10
11
12
13
34
33
32
MCS6512
31
30
29
28
27
14
2~
15
16
25
24
17
23
22
21
18
19
20
Pin Name
Description
Type
DBE
Output
Input
NMi
Data Bus Enable
Read/Write control
Interrupt request
Non.maskable interrupt
RESET
Reset
<1>1. <1>2
R/Vii
IRQ
Input
Input
Input
Input
<1>2 (OUT)
CPU clocks
System clock
DBO- DB7
Data Bus
ABO-ABI5
ROY
Address Bus
Single cycle control
Tristate. bidirectional
Output
Input
SO
SYNC
Set Overflow flag
Identify op code fetch cycle
Output
VCC.VSS
Power and Ground
Output
Input
Figure 10-7. MCS6512 Signals and Pin Assignments
10-10
Vss
2
«1>1
rna
R/W
4
DBO
ABO
5
6
AB1
7
OBI
OB2
OBJ
Vce
AB2
ABJ
AB4
AB5
AB6
AB7
ABS
MCS6515
10
11
12
13
14
0B4
OBS
OB6
OB7
AB11
AB10
AB9
Pin Name
Description
TVpe
R/W
iRa
Read/Write control
Intemipt request
Output
Input
RESET
«1>1. «1>2
Reset
CPU clockS •
Inp.ut
Input
OBO - OB7'
ABO-AB11
ROY
Data Bus
Address B'us
VCC.VSS
Single cycle control
Power and Ground
. Tristate•. bidirectional
Output
Input
Figure 10-10. MCS6515 Signals and Pin Assignments
DATA BUS ENABLE (DBE). Only the MCS6512 CPU supports this signal. This signal is input low in order to float the
Data Bus. DBE is frequently tied to the <1>2 clock input. in which case <1>2 and DBE are identical signals.
READIWRITE (R/W). When high. this signal indicates that the CPU wishes to read data off the Data Bus: when low.
this signal indicates that the CPU is outputting data on the Data Bus. Thencirrrial standby state for this signal is "read"
(high).
.
INTERRUPT REQUEST (IRQ). This signal is used by external logic to request an interrupt. If interrupts have been
enabled. then the CPU will acknowledge an interrupt at the end of the currently executing instruction. There is a small
difference between MCS6500 and MC6800 interrupt acknowledge logic. The MC6S00 cannot acknowledge an interrupt while it is in the Halt state. The MCS6500 has no Halt state, therefore this situation cannot arise.
NONMASKABLE INTERRUPT (i"iviJ). This signal differs from IRQ in that it cannot be inhibited. Typically this input is
used for catastrophic interrupts such as power failure.
..
RESET. This is a typical RESET signal. Reset logic within an MCS6500 microcomputer system is identical to Reset logic
within an MC6800 microcomputer system.
Next consider MC6S00 signals which are the same on some MCS6500 CPUs, but not on others.
The clock signals <1>1 and <1>2 are identical to MC6S00 clock signals for the MCS651X series CPUs. These CPUs
require external clock signals whose waveforms are identical to the MC6800. The MCS650X series CPUs have clock·
logic on the CPU chip; these CPUs output <1>2; the MCS6502 and the MCS6506 output <1>1 as well.
The Data Bus of the MCS6500 series CPUs is identical to that of the MC6S00. The' Data Bus is a tristate. 8-bit
bidirectional bus via which data is transferred between memory and all MCS6500 microcomputer system devices.
However, only the MCS6512 has a DBE input for external control of the bus. On MCS6500 CPUs other than the
MCS6512. an internal Data Bus Enable is connected to <1>2; in these devices the Data Bus is always floated during the
first part of a machine cycle.
.
We will now look at the CPU signals which are unique to the MCS6500 microcomputer system.
The Address Bus in MCS6500 microcomputer systems is not a tristate bus and cannot be floated. Also. the 28-pin
MCS6500 series CPUs have either 12 or 13 Address Bus lines. allowing a total memory space of either 4K or 8K bytes.
The Address Bus is used in the normal way by the CPU to output memory addresses.
READY (RDY) is an input control signal which. in MCS6500 microcomputer systems. performs the task of MC6800
TSC. DBE and HALT signals. The RDY input causes the equivalent of a Wait machine cycle to be inserted within the
normal machine cycle sequence. In order to generate a Wait machine cycle. RDY must make a high-to-Iow transition
10-12
during a ~1 high clock pulse in any machine cycle other than a write. We will illustrate the use of the ROY signal. and
discuss a number of its non-obvious ramifications. following this summary description of MCS6500 signals.
The Set Overflow flag (SO) signal can be used to set to 1 the Overflow bit of the Status register. When the SO input makes a high-to-Iow transition. the Overflow status is set to 1. The SO input can make a high-to-Iow transition at
any time: this is an asynchronous input.
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You cannot use the SO input signql to reset the Overflow bit of the Status register to O.
The SYNC signal is used to identify instruction fetch machine cycles. There are a number of important uses for this
signal. which we will discuss along with general instruction timing.
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MCS6500 CPUs execute instructions using exactly the same clock signals, machine cycles and machine cycle
types as described for the MC6800 in Chapter 8 . '
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Recall that the two clock
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signal~'; ~1 and ~2, define machine cycles as follows:
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1
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Machine
Machine
Cycle 2
Cycle 3
I
So far as external logic is concerned, there are only three types of machine cycles which can occur during an in~":
struction's execution: . '
1)
2)
3)
A read operation during which a byte of data must be input to the CPU.
A write operation during which a byte of data is output by the CPU.
An internal operation during which no activ~ty ~ccurs on the Sy§tem ~us.
As was the case with the MC6800, all MCS6500 instructions have timing which is a simple concatenation of
the three basic machine cycle types. See Figures 9-3 and 9-4 and the accompanying text in Chapter 9 for a
description of these three basic machine cycles.
'
Instruction execution differences between the MC6800 and MCS6500 arise only when we depart from simple instruction execution logic. The MCS6500 SYNC signal is'also a difference to be noted: the SYNC signal identifies MCS6500
machine cycles during which any instruction object code is being fetGhed. SYNC timing may be illustrated as follows:
<1>1
4>2
SYNC
Instruction
fetch machine
cycle
MCS6500 CPUs do not allow the ~1 and ~2 clocks to be stretched. nor do they allow the Address Bus to be floated:
some MCS6500 CPU versions do not allow the Data Bus to be floated. Also. there is no Halt state. The single ROY sig-
nal is used to interface slow memories, to refresh dynamic memories or to perform Direct Memory Access
operations.
10-13
What the ROY input signal does is allow you to insert one or more Wait machine cycles in
between two normal instruction execution machine cycles:
MCS6500
WAIT
STATE
I
....~
1 high clock pulse. This
transition may occur during any nonwrite machine cycle. Timing may be illustrated as follows: