16 Bit MCU And DSC Programmer’s Reference Manual PIC24F Programmer's

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16-bit MCU and DSC Programmer’s Reference Manual
High-Performance Microcontrollers (MCU)
and Digital Signal Controllers (DSC)

© 2009 Microchip Technology Inc.

DS70157D

Note the following details of the code protection feature on Microchip devices:
•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

•

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS70157D-page 2

© 2009 Microchip Technology Inc.

Table of Contents
PAGE
SECTION 1. INTRODUCTION

5

Introduction ......................................................................................................................................................... 6
Manual Objective ................................................................................................................................................ 6
Development Support ......................................................................................................................................... 6
Style and Symbol Conventions ........................................................................................................................... 7
Instruction Set Symbols ...................................................................................................................................... 8
Related Documents ............................................................................................................................................. 9

SECTION 2. PROGRAMMER’S MODEL

11

16-bit MCU and DSC Core Architecture Overview ............................................................................................ 12
Programmer’s Model ......................................................................................................................................... 14
Working Register Array ..................................................................................................................................... 17
Default Working Register (WREG) .................................................................................................................... 17
Software Stack Frame Pointer .......................................................................................................................... 18

SECTION 3. INSTRUCTION SET OVERVIEW

29

Introduction ....................................................................................................................................................... 30
Instruction Set Overview ................................................................................................................................... 30
Instruction Set Summary Tables ....................................................................................................................... 32

SECTION 4. INSTRUCTION SET DETAILS

41

Data Addressing Modes .................................................................................................................................... 42
Program Addressing Modes .............................................................................................................................. 51
Instruction Stalls ................................................................................................................................................ 52
Byte Operations ................................................................................................................................................ 54
Word Move Operations ..................................................................................................................................... 56
Using 10-bit Literal Operands ........................................................................................................................... 59
Software Stack Pointer and Frame Pointer ....................................................................................................... 60
Conditional Branch Instructions ........................................................................................................................ 65
Z Status Bit ........................................................................................................................................................ 66
Assigned Working Register Usage .................................................................................................................... 67
DSP Data Formats (dsPIC30F and dsPIC33F Devices) ................................................................................... 70
Accumulator Usage (dsPIC30F and dsPIC33F Devices) .................................................................................. 72
Accumulator Access (dsPIC30F and dsPIC33F Devices) ................................................................................. 73
DSP MAC Instructions (dsPIC30F and dsPIC33F Devices) ............................................................................. 74
DSP Accumulator Instructions (dsPIC30F and dsPIC33F Devices) ................................................................. 78
Scaling Data with the FBCL Instruction (dsPIC30F and dsPIC33F Devices) .................................................... 79
Normalizing the Accumulator with the FBCL Instruction (dsPIC30F and dsPIC33F Devices) .......................... 81

SECTION 5. INSTRUCTION DESCRIPTIONS

83

Instruction Symbols ........................................................................................................................................... 84
Instruction Encoding Field Descriptors Introduction .......................................................................................... 84
Instruction Description Example ........................................................................................................................ 88
Instruction Descriptions ..................................................................................................................................... 89

SECTION 6. REFERENCE

357

Instruction Bit Map .......................................................................................................................................... 358
Instruction Set Summary Table ....................................................................................................................... 360
Revision History .............................................................................................................................................. 367

© 2009 Microchip Technology Inc.

DS70157D-page 3

16-bit MCU and DSC Programmer’s Reference Manual
SECTION 7. INDEX

369

SECTION 8. WORLDWIDE SALES AND SERVICE

374

DS70157D-page 4

© 2009 Microchip Technology Inc.

1
Introduction

Section 1. Introduction
HIGHLIGHTS
This section of the manual contains the following topics:
1.1
1.2
1.3
1.4
1.5
1.6

Introduction ....................................................................................................................... 6
Manual Objective .............................................................................................................. 6
Development Support ....................................................................................................... 6
Style and Symbol Conventions ......................................................................................... 7
Instruction Set Symbols .................................................................................................... 8
Related Documents .......................................................................................................... 9

© 2009 Microchip Technology Inc.

DS70157D-page 5

16-bit MCU and DSC Programmer’s Reference Manual
1.1

INTRODUCTION
Microchip Technology’s focus is on products that meet the needs of the embedded control
market. We are a leading supplier of:
•
•
•
•
•
•

8-bit general purpose microcontrollers (PIC® MCUs)
16-bit Digital Signal Controllers (dsPIC® DSCs)
16-bit and 32-bit Microcontrollers (MCUs)
Speciality and standard nonvolatile memory devices
Security devices (KEELOQ® Security ICs)
Application-specific standard products

Please request a Microchip Product Selector Guide for a listing of all the interesting products that
we have to offer. This literature can be obtained from your local sales office or downloaded from
the Microchip web site (www.microchip.com).

1.2

MANUAL OBJECTIVE
This manual is a software developer’s reference for the 16-bit MCU and DSC device families.
This manual describes the Instruction Set in detail and also provides general information to assist
the user in developing software for the 16-bit MCU and DSC families.
This manual does not include detailed information about the core, peripherals, system integration
or device-specific information. The user should refer to the specific device family reference
manual for information about the core, peripherals and system integration. For device-specific
information, the user should refer to the individual data sheets. The information that can be found
in the data sheets includes:
•
•
•
•

Device memory map
Device pinout and packaging details
Device electrical specifications
List of peripherals included on the device

Code examples are given throughout this manual. These examples are valid for any device in
the 16-bit MCU and DSC families.

1.3

DEVELOPMENT SUPPORT
Microchip offers a wide range of development tools that allow users to efficiently develop and
debug application code. Microchip’s development tools can be broken down into four categories:
•
•
•
•

Code generation
Hardware/Software debug
Device programmer
Product evaluation boards

Information about the latest tools, product briefs and user guides can be obtained from the
Microchip web site (www.microchip.com) or from your local Microchip Sales Office.
Microchip offers other reference tools to speed the development cycle. These include:
•
•
•
•
•

Application Notes
Reference Designs
Microchip web site
Local Sales Offices with Field Application Support
Corporate Support Line

The Microchip web site also lists other sites that may be useful references.

DS70157D-page 6

© 2009 Microchip Technology Inc.

Section 1. Introduction
1.4

1

STYLE AND SYMBOL CONVENTIONS

Table 1-1:

Document Conventions

Symbol or Term

Description

set

To force a bit/register to a value of logic ‘1’.

clear

To force a bit/register to a value of logic ‘0’.

Reset

1.
2.

0xnnnn

Designates the number ‘nnnn’ in the hexadecimal number system. These
conventions are used in the code examples. For example, 0x013F or
0xA800.

: (colon)

Used to specify a range or the concatenation of registers/bits/pins.
One example is ACCAU:ACCAH:ACCAL, which is the concatenation of
three registers to form the 40-bit Accumulator.
Concatenation order (left-right) usually specifies a positional relationship
(MSb to LSb, higher to lower).

<>

Specifies bit locations in a particular register.
One example is SR<7:5> (or IPL<2:0>), which specifies the register and
associated bits or bit positions.

To force a register/bit to its default state.
A condition in which the device places itself after a device Reset
occurs. Some bits will be forced to ‘0’ (such as interrupt enable bits),
while others will be forced to ‘1’ (such as the I/O data direction bits).

LSb, MSb

Indicates the Least Significant or Most Significant bit in a field.

LSB, MSB

Indicates the Least/Most Significant Byte in a field of bits.

lsw, msw

Indicates the least/most significant word in a field of bits.

Courier Font

Used for code examples, binary numbers and for Instruction Mnemonics
in the text.

Times New
Used for equations and variables.
Roman Font, Italic
Times New
Roman Font,
Bold Italic

Used in explanatory text for items called out from a figure, equation or
example.

Note:

A Note presents information that we want to re-emphasize, either to help
you avoid a common pitfall, or make you aware of operating differences
between some device family members. In most instances, a Note is used
in a shaded box (as illustrated below); however, when referenced in a
table, a Note will appear at the bottom of the associated table (see
Table 1-2).
Note:

© 2009 Microchip Technology Inc.

This is a Note in a shaded note box.

DS70157D-page 7

Introduction

Throughout this document, certain style and font format conventions are used. Most format
conventions imply that a distinction should be made for the emphasized text. The MCU industry
has many symbols and non-conventional word definitions/abbreviations. Table 1-1 provides a
description of the conventions used in this document.

16-bit MCU and DSC Programmer’s Reference Manual
1.5

INSTRUCTION SET SYMBOLS
The Summary Tables in Section 3.2 “Instruction Set Overview” and Section 6.2 “Instruction
Set Summary Table”, and the instruction descriptions in Section 5.4 “Instruction
Descriptions” utilize the symbols shown in Table 1-2.
Table 1-2:
Symbol(1)

Symbols Used in Instruction Summary Tables and Descriptions
Description

Optional field or operation
[text]
The location addressed by text
(text)
The contents of text
#text
The literal defined by text
a ∈ [b, c, d] “a” must be in the set of [b, c, d]

Register bit field
{label:}
Optional label name
Acc
Accumulator A or Accumulator B
AWB
Accumulator Write Back
{ }

bit4
4-bit wide bit position (0:7 in Byte mode, 0:15 in Word mode)
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address
lit1
1-bit literal (0:1)
lit4
4-bit literal (0:15)
lit5
5-bit literal (0:31)
lit8
8-bit literal (0:255)
lit10
10-bit literal (0:255 in Byte mode, 0:1023 in Word mode)
lit14
14-bit literal (0:16383)
lit16
16-bit literal (0:65535)
lit23
23-bit literal (0:8388607)
Slit4
Signed 4-bit literal (-8:7)
Slit6
Signed 6-bit literal (-32:31) (range is limited to -16:16)
Slit10
Signed 10-bit literal (-512:511)
Slit16
Signed 16-bit literal (-32768:32767)
TOS
Top-of-Stack
Wb
Base working register
Wd
Destination working register (direct and indirect addressing)
Wm, Wn
Working register divide pair (dividend, divisor)
Wm * Wm
Working register multiplier pair (same source register)
Wm * Wn
Working register multiplier pair (different source registers)
Wn
Both source and destination working register (direct addressing)
Wnd
Destination working register (direct addressing)
Wns
Source working register (direct addressing)
WREG
Default working register (assigned to W0)
Ws
Source working register (direct and indirect addressing)
Wx
Source Addressing mode and working register for X data bus prefetch
Wxd
Destination working register for X data bus prefetch
Wy
Source Addressing mode and working register for Y data bus prefetch
Wyd
Destination working register for Y data bus prefetch
Note 1: The range of each symbol is instruction dependent. Refer to Section
5. “Instruction Descriptions” for the specific instruction range.

DS70157D-page 8

© 2009 Microchip Technology Inc.

Section 1. Introduction
1.6

1

RELATED DOCUMENTS

1.6.1

Third-Party Documentation

There are several documents available from third-party sources around the world. Microchip
does not review these documents for technical accuracy. However, they may be a helpful source
for understanding the operation of Microchip16-bit MCU and DSC devices. Please refer to the
Microchip web site (www.microchip.com) for third-party documentation related to the 16-bit MCU
and DSC families.

© 2009 Microchip Technology Inc.

DS70157D-page 9

Introduction

Microchip, as well as other sources, offer additional documentation which can aid in your
development with 16-bit MCUs and DSCs. These lists contain the most common documentation,
but other documents may also be available. Please check the Microchip web site
(www.microchip.com) for the latest published technical documentation.

16-bit MCU and DSC Programmer’s Reference Manual
NOTES:

DS70157D-page 10

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
HIGHLIGHTS

2

This section of the manual contains the following topics:
16-bit MCU and DSC Core Architecture Overview ......................................................... 12
Programmer’s Model....................................................................................................... 14
Working Register Array ................................................................................................... 17
Default Working Register (WREG) ................................................................................. 17
Software Stack Frame Pointer ........................................................................................ 18

© 2009 Microchip Technology Inc.

DS70157D-page 11

Programmer’s
Model

2.1
2.2
2.3
2.4
2.5

16-bit MCU and DSC Programmer’s Reference Manual
2.1

16-BIT MCU AND DSC CORE ARCHITECTURE OVERVIEW
This section provides an overview of the 16-bit architecture features and capabilities for the
following families of devices:
• 16-bit Microcontrollers (MCUs):
- PIC24F
- PIC24H
• 16-bit Digital Signal Controllers (DSCs):
- dsPIC30F
- dsPIC33F

2.1.1

Features Specific to 16-bit MCU and DSC Core

The core of the 16-bit MCU and DSC devices is a 16-bit (data) modified Harvard architecture with
an enhanced instruction set. The core has a 24-bit instruction word, with an 8-bit Op code field.
The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program
memory space. An instruction prefetch mechanism is used to help maintain throughput and
provides predictable execution. The majority of instructions execute in a single cycle.

2.1.1.1

REGISTERS

The 16-bit MCU and DSC devices have sixteen, 16-bit working registers. Each of the working
registers can act as a data, address or offset register. The 16th working register (W15) operates
as a software Stack Pointer for interrupts and calls.

2.1.1.2

INSTRUCTION SET

The instruction set is almost identical for the 16-bit MCU and DSC architectures. The instruction
set includes many Addressing modes and was designed for optimum C compiler efficiency.

2.1.1.3

DATA SPACE ADDRESSING

The data space can be addressed as 32K words or 64 Kbytes. The upper 32 Kbytes of the data
space memory map can optionally be mapped into program space at any 16K program word
boundary, a feature known as Program Space Visibility (PSV). The program to data space
mapping feature lets any instruction access program space as if it were the data space, which is
useful for storing data coefficients.

2.1.1.4

ADDRESSING MODES

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct,
Register Indirect and Register Offset Addressing modes. Each instruction is associated with a
predefined Addressing mode group, depending upon its functional requirements. As many as 7
Addressing modes are supported for each instruction.
For most instructions, the CPU is capable of executing a data (or program data) memory read, a
working register (data) read, a data memory write and a program (instruction) memory read per
instruction cycle. As a result, 3-operand instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.

2.1.1.5

ARITHMETIC AND LOGIC UNIT

A high-speed, 17-bit by 17-bit multiplier is included to significantly enhance the core arithmetic
capability and throughput. The multiplier supports Signed, Unsigned, and Mixed mode, 16-bit by
16-bit, or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle.
The 16-bit Arithmetic Logic Unit (ALU) is enhanced with integer divide assist hardware that
supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT
instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit
(or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19
cycles to complete, but are interruptible at any cycle boundary.

DS70157D-page 12

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
2.1.1.6

EXCEPTION PROCESSING

The 16-bit MCU and DSC devices have a vectored exception scheme with support for up to 8
sources of non-maskable traps and up to 118 interrupt sources. In both families, each interrupt
source can be assigned to one of seven priority levels.

2.1.2

dsPIC30F and dsPIC33F Features

In addition to the information provided in 2.1.1 “Features Specific to 16-bit MCU and DSC
Core”, this section describes the DSP enhancements that are available in the dsPIC30F and
dsPIC33F families of devices.

2.1.2.1

PROGRAMMING LOOP CONSTRUCTS

DSP INSTRUCTION CLASS

The DSP class of instructions are seamlessly integrated into the architecture and execute from
a single execution unit.

2.1.2.3

DATA SPACE ADDRESSING

The data space is split into two blocks, referred to as X and Y data memory. Each memory block
has its own independent Address Generation Unit (AGU). The MCU class of instructions operate
solely through the X memory AGU, which accesses the entire memory map as one linear data
space. The DSP dual source class of instructions operates through the X and Y AGUs, which
splits the data address space into two parts. The X and Y data space boundary is arbitrary and
device-specific.

2.1.2.4

MODULO AND BIT-REVERSED ADDRESSING

Overhead free circular buffers (modulo addressing) are supported in both X and Y address
spaces. The modulo addressing removes the software boundary checking overhead for DSP
algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class
of instructions. The X AGU also supports bit-reverse addressing, to greatly simplify input or
output data reordering for radix-2 FFT algorithms.

2.1.2.5

DSP ENGINE

The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit
saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of
shifting a 40-bit value, up to 16 bits right, or up to 16 bits left, in a single cycle. The DSP
instructions operate seamlessly with all other instructions and have been designed for optimal
real-time performance. The MAC instruction and other associated instructions can concurrently
fetch two data operands from memory while multiplying two working registers. This requires that
the data space be split for these instructions and linear for all others. This is achieved in a
transparent and flexible manner through dedicating certain working registers to each address
space.

2.1.2.6

EXCEPTION PROCESSING

The dsPIC30F devices have a vectored exception scheme with support for up to 8 sources of
non-maskable traps and up to 54 interrupt sources. The dsPIC33F devices have a similar
exception scheme, but supports up to 118 interrupt sources. In both families, each interrupt
source can be assigned to one of seven priority levels.

© 2009 Microchip Technology Inc.

DS70157D-page 13

Programmer’s
Model

Overhead free program loop constructs are supported using the DO instruction, which is
interruptible.

2.1.2.2

2

16-bit MCU and DSC Programmer’s Reference Manual
2.2

PROGRAMMER’S MODEL
Figure 2-1 through Figure 2-2 show the programmer’s model diagrams for the 16-bit MCU and
DSC families of devices.

Figure 2-1:

PIC24F and PIC24H Programmer’s Model Diagram
15

0
W0/WREG

DIV and MUL
Result Registers

PUSH.S Shadow

W1
Legend

W2
W3
W4
W5
W6
W7

Working Registers

W8
W9
W10
W11
W12
W13
W14/Frame Pointer
W15/Stack Pointer

Stack Pointer Limit Register

SPLIM
22

0
Program Counter
0

7
TABPAG
TBLPAG

Data Table Page Address

7

0
PSVPAG

Program Space Visibility Page Address
15

0
RCOUNT

REPEAT Loop Counter

15

0
CPU Core Control Register

CORCON
—

—

—

—

—

SRH

DS70157D-page 14

—

—

DC

IPL2 IPL1 IPL0 RA

N

OV

Z

C

Status Register

SRL

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
Figure 2-2:

dsPIC30F and dsPIC33F Programmer’s Model Diagram
15

0
W0/WREG

DIV and MUL
Result Registers

PUSH.S Shadow

W1

DO Shadow

W2
W3

Legend

W4
MAC Operand
Registers

W5

2

W6
W7

Programmer’s
Model

Working Registers

W8
W9

MAC Address
Registers

W10
W11
W12/MAC Offset
W13/MAC Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register

SPLIM
39

15

31

0

ACCA

DSP
Accumulators

ACCB

22

0
Program Counter
0

7
TABPAG
TBLPAG
7

Data Table Page Address
0

PSVPAG

Program Space Visibility Page Address
15

0
RCOUNT

REPEAT Loop Counter

15

0
DCOUNT

DO Loop Counter

22

0
DOSTART

DO Loop Start Address

22

0
DO Loop End Address

DOEND
15

0
CPU Core Control Register

CORCON
OA

OB

SA

SB OAB SAB DA
SRH

© 2009 Microchip Technology Inc.

DC

IPL2 IPL1 IPL0 RA

N

OV

Z

C

Status Register

SRL

DS70157D-page 15

16-bit MCU and DSC Programmer’s Reference Manual
All registers in the programmer’s model are memory mapped and can be manipulated directly by
the instruction set. A description of each register is provided in Table 2-1.
Note:

Unless otherwise specified, the Programmer’s Model Register Descriptions in
Table 2-1 apply to all MCU and DSC device families.

Table 2-1:

Programmer’s Model Register Descriptions

Register
CORCON

CPU Core Configuration register

PC

23-bit Program Counter

PSVPAG

Program Space Visibility Page Address register

RCOUNT

Repeat Loop Count register

SPLIM

Stack Pointer Limit Value register

SR

ALU and DSP Engine STATUS register

TBLPAG

Table Memory Page Address register

W0-W15

Working register array

ACCA,

ACCB(1)

40-bit DSP Accumulators

DCOUNT(1)

DO Loop Count register

DOEND(1)

DO Loop End Address register

DOSTART(1)

DO Loop Start Address register

Note 1:

DS70157D-page 16

Description

This register is only available on dsPIC30F and dsPIC33F devices.

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
2.3

WORKING REGISTER ARRAY
The 16 working (W) registers can function as data, address or offset registers. The function of a
W register is determined by the instruction that accesses it.
Byte instructions, which target the working register array, only affect the Least Significant Byte
(LSB) of the target register. Since the working registers are memory mapped, the Least and Most
Significant Bytes (MSBs) can be manipulated through byte-wide data memory space accesses.

2.4

DEFAULT WORKING REGISTER (WREG)

File register instructions that also utilize a working register do not specify the working register that
is to be used for the instruction. Instead, a default working register (WREG) is used for these file
register instructions. Working register, W0, is assigned to be the WREG. The WREG assignment
is not programmable.

© 2009 Microchip Technology Inc.

DS70157D-page 17

2
Programmer’s
Model

The instruction set can be divided into two instruction types: working register instructions and file
register instructions. The working register instructions use the working register array as data
values, or as addresses that point to a memory location. In contrast, file register instructions
operate on a specific memory address contained in the instruction opcode.

16-bit MCU and DSC Programmer’s Reference Manual
2.5

SOFTWARE STACK FRAME POINTER
A frame is a user-defined section of memory in the stack, used by a function to allocate memory
for local variables. W14 has been assigned for use as a Stack Frame Pointer with the link (LNK)
and unlink (ULNK) instructions. However, if a Stack Frame Pointer and the LNK and ULNK
instructions are not used, W14 can be used by any instruction in the same manner as all other
W registers. See 4.7.2 “Software Stack Frame Pointer” for detailed information about the
Frame Pointer.

2.5.1

Software Stack Pointer

W15 serves as a dedicated Software Stack Pointer, and will be automatically modified by function
calls, exception processing and returns. However, W15 can be referenced by any instruction in
the same manner as all other W registers. This simplifies reading, writing and manipulating the
Stack Pointer. Refer to 4.7.1 “Software Stack Pointer” for detailed information about the Stack
Pointer.

2.5.2

Stack Pointer Limit Register (SPLIM)

The SPLIM is a 16-bit register associated with the Stack Pointer. It is used to prevent the Stack
Pointer from overflowing and accessing memory beyond the user allocated region of stack
memory. Refer to 4.7.3 “Stack Pointer Overflow” for detailed information about the SPLIM.

2.5.3

Accumulator A, Accumulator B (dsPIC30F and dsPIC33F
Devices)

Accumulator A (ACCA) and Accumulator B (ACCB) are 40-bit wide registers, utilized by DSP
instructions to perform mathematical and shifting operations. Each accumulator is composed of
3 memory mapped registers:
• AccxU (bits 39-32)
• AccxH (bits 31-16)
• AccxL (bits 15-0)
Refer to 4.12 “Accumulator Usage (dsPIC30F and dsPIC33F Devices)” for details on using
ACCA and ACCB.

2.5.4

Program Counter

The Program Counter (PC) is 23 bits wide. Instructions are addressed in the 4M x 24-bit user
program memory space by PC<22:1>, where PC<0> is always set to ‘0’ to maintain instruction
word alignment and provide compatibility with data space addressing. This means that during
normal instruction execution, the PC increments by 2.
Program memory located at 0x800000 and above is utilized for device configuration data, Unit ID
and Device ID. This region is not available for user code execution and the PC can not access
this area. However, one may access this region of memory using table instructions. For details
on accessing the configuration data, Unit ID and Device ID, refer to the specific device family
reference manual.

2.5.5

TBLPAG Register

The TBLPAG register is used to hold the upper 8 bits of a program memory address during table
read and write operations. Table instructions are used to transfer data between program memory
space and data memory space. For details on accessing program memory with the table
instructions, refer to the specific device family reference manual.

2.5.6

PSVPAG Register (PIC24F, PIC24H, dsPIC30F and dsPIC33F)

Program space visibility allows the user to map a 32 Kbyte section of the program memory space
into the upper 32 Kbytes of data address space. This feature allows transparent access of
constant data through instructions that operate on data memory. The PSVPAG register selects
the 32 Kbyte region of program memory space that is mapped to the data address space. For
details on program space visibility, refer to the specific device family reference manual.

DS70157D-page 18

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
2.5.7

RCOUNT Register

The 14-bit RCOUNT register contains the loop counter for the REPEAT instruction. When a
REPEAT instruction is executed, RCOUNT is loaded with the repeat count of the instruction,
either “lit14” for the “REPEAT #lit14” instruction, or the contents of Wn for the “REPEAT Wn”
instruction. The REPEAT loop will be executed RCOUNT + 1 time.
Note 1: If a REPEAT loop is executing and gets interrupted, RCOUNT may be cleared by
the Interrupt Service Routine to break out of the REPEAT loop when the foreground
code is re-entered.

2.5.8

DCOUNT Register (dsPIC30F and dsPIC33F Devices)

The 14-bit DCOUNT register contains the loop counter for hardware DO loops. When a DO
instruction is executed, DCOUNT is loaded with the loop count of the instruction, either “lit14” for
the “DO #lit14,Expr” instruction, or the 14 Least Significant bits of Ws for the “DO Ws,Expr”
instruction. The DO loop will be executed DCOUNT + 1 time.

2.5.9

DOSTART Register (dsPIC30F and dsPIC33F Devices)

The DOSTART register contains the starting address for a hardware DO loop. When a DO
instruction is executed, DOSTART is loaded with the address of the instruction following the DO
instruction. This location in memory is the start of the DO loop. When looping is activated,
program execution continues with the instruction stored at the DOSTART address after the last
instruction in the DO loop is executed. This mechanism allows for zero overhead looping.

2.5.10

DOEND Register (dsPIC30F and dsPIC33F Devices)

The DOEND register contains the ending address for a hardware DO loop. When a DO instruction
is executed, DOEND is loaded with the address specified by the expression in the DO instruction.
This location in memory specifies the last instruction in the DO loop. When looping is activated
and the instruction stored at the DOEND address is executed, program execution will continue
from the DO loop start address (stored in the DOSTART register).

2.5.11

STATUS Register

The 16-bit STATUS register, maintains status information for instructions which have most
recently been executed. Operation Status bits exist for MCU operations, loop operations and
DSP operations. Additionally, the STATUS register contains the CPU Interrupt Priority Level bits,
IPL<2:0>, which are used for interrupt processing.
Depending on the MCU and DSC family, the following register descriptions are provided:
• Register 2-1 for PIC24F and PIC24H devices
• Register 2-2 for dsPIC30F and dsPIC33F devices

2.5.11.1

MCU ALU STATUS BITS

The MCU operation Status bits are either affected or used by the majority of instructions in the
instruction set. Most of the logic, math, rotate/shift and bit instructions modify the MCU Status bits
after execution, and the conditional Branch instructions use the state of individual Status bits to
determine the flow of program execution. All conditional branch instructions are listed in
4.8 “Conditional Branch Instructions”.
The Carry, Zero, Overflow, Negative and Digit Carry (C, Z, OV, N and DC) bits are used to show
the immediate status of the MCU ALU. They indicate when an operation has resulted in a Carry,
Zero, Overflow, Negative result and Digit Carry, respectively. When a subtract operation is
performed, the C flag is used as a Borrow flag.

© 2009 Microchip Technology Inc.

DS70157D-page 19

2
Programmer’s
Model

2: Refer to the specific device family reference manual for complete details about
REPEAT loops.

16-bit MCU and DSC Programmer’s Reference Manual
The Z status bit is a special zero status bit that is useful for extended precision arithmetic. The Z
bit functions like a normal Z flag for all instructions except those that use a carry or borrow input
(ADDC, CPB, SUBB and SUBBR). See 4.9 “Z Status Bit” for usage of the Z status bit.
Note 1: All MCU bits are shadowed during execution of the PUSH.S instruction and they are
restored on execution of the POP.S instruction.
2: All MCU bits, except the DC flag (which is not in the SRL), are stacked during
exception processing (see 4.7.1 “Software Stack Pointer”).

2.5.11.2

LOOP STATUS BITS

The REPEAT Active (RA) bit is used to indicate when looping is active. The RA flag indicates that
a REPEAT instruction is being executed, and it is only affected by the REPEAT instructions. The
RA flag is set to ‘1’ when the instruction being repeated begins execution, and it is cleared when
the instruction being repeated completes execution for the last time.
Since the RA flag is also read-only, it may not be directly cleared. However, if a REPEAT or its
target instruction is interrupted, the Interrupt Service Routine may clear the RA flag of the SRL,
which resides on the stack. This action will disable looping once program execution returns from
the Interrupt Service Routine, because the restored RA will be ‘0’.

2.5.11.2.1 DO Active (DA) bit (dsPIC30F and dsPIC33F Devices)
The DO Active (DA) bit is used to indicate when looping is active. The DO instructions affect the
DA flag, which indicates that a DO loop is active. The DA flag is set to ‘1’ when the first instruction
of the DO loop is executed, and it is cleared when the last instruction of the loop completes final
execution.
The DA flag is read-only. This means that looping may not be initiated by writing a ‘1’ to DA, nor
looping may be terminated by writing a ‘0’ to DA. If a DO loop must be terminated prematurely,
the EDT bit, CORCON<11>, should be used.

2.5.11.3

DSP ALU STATUS BITS (dsPIC30F AND dsPIC33F DEVICES)

The high byte of the STATUS Register (SRH) is used by the DSP class of instructions, and it is
modified when data passes through one of the adders. The SRH provides status information
about overflow and saturation for both accumulators. The Saturate A, Saturate B, Overflow A and
Overflow B (SA, SB, OA, OB) bits provide individual accumulator status, while the Saturate AB
and Overflow AB (SAB, OAB) bits provide combined accumulator status. The SAB and OAB bits
provide the software developer efficiency in checking the register for saturation or overflow.
The OA and OB bits are used to indicate when an operation has generated an overflow into the
guard bits (bits 32 through 39) of the respective accumulator. This condition can only occur when
the processor is in Super Saturation mode, or if saturation is disabled. It indicates that the
operation has generated a number which cannot be represented with the lower 31 bits of the
accumulator.
The SA and SB bits are used to indicate when an operation has generated an overflow out of the
Most Significant bit of the respective accumulator. The SA and SB bits are active, regardless of
the Saturation mode (Disabled, Normal or Super) and may be considered “sticky”. Namely, once
the SA or SB is set to ‘1’, it can only be cleared manually by software, regardless of subsequent
DSP operations. When required, it is recommended that the bits be cleared with the BCLR
instruction.
For convenience, the OA and OB bits are logically ORed together to form the OAB flag, and the
SA and SB bits are logically ORed to form the SAB flag. These cumulative status bits provide
efficient overflow and saturation checking when an algorithm is implemented, which utilizes both
accumulators. Instead of interrogating the OA and the OB bits independently for arithmetic
overflows, a single check of OAB may be performed. Likewise, when checking for saturation,
SAB may be examined instead of checking both the SA and SB bits. Note that clearing the SAB
flag will clear both the SA and SB bits.

DS70157D-page 20

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
2.5.11.4

INTERRUPT PRIORITY LEVEL STATUS BITS

The three Interrupt Priority Level (IPL) bits of the SRL, SR<7:5>, and the IPL3 bit, CORCON<3>,
set the CPU’s IPL which is used for exception processing. Exceptions consist of interrupts and
hardware traps. Interrupts have a user-defined priority level between 0 and 7, while traps have a
fixed priority level between 8 and 15. The fourth Interrupt Priority Level bit, IPL3, is a special IPL
bit that may only be read or cleared by the user. This bit is only set when a hardware trap is
activated and it is cleared after the trap is serviced.
The CPU’s IPL identifies the lowest level exception which may interrupt the processor. The
interrupt level of a pending exception must always be greater than the CPU’s IPL for the CPU to
process the exception. This means that if the IPL is 0, all exceptions at priority Level 1 and above
may interrupt the processor. If the IPL is 7, only hardware traps may interrupt the processor.

2

When an exception is serviced, the IPL is automatically set to the priority level of the exception
being serviced, which will disable all exceptions of equal and lower priority. However, since the
IPL field is read/write, one may modify the lower three bits of the IPL in an Interrupt Service
Routine to control which exceptions may preempt the exception processing. Since the SRL is
stacked during exception processing, the original IPL is always restored after the exception is
serviced. If required, one may also prevent exceptions from nesting by setting the NSTDIS bit,
INTCON1<15>.

Programmer’s
Model

Note:

2.5.12

Refer to the specific device family reference manual for complete details on
exception processing.

Core Control Register

For all MCU and DSC devices, the 16-bit CPU Core Control (CORCON) register, is used to set
the configuration of the CPU. This register provides the ability to map program space into data
space.
In addition to setting CPU modes, the CORCON register contains status information about the
IPL<3> status bit, which indicates if a trap exception is being processed.
Depending on the MCU and DSC family, the following CORCON register descriptions are
provided:
• Register 2-3 for PIC24F and PIC24H devices
• Register 2-4 for dsPIC30F and dsPIC33F devices

2.5.12.1

dsPIC30F AND dsPIC33F SPECIFIC BITS

In addition to setting CPU modes, the following features are available through the CORCON
register:
•
•
•
•
•
•

Set the ACCA and ACCB saturation enable
Set the Data Space Write Saturation mode
Set the Accumulator Saturation and Rounding modes
Set the Multiplier mode for DSP operations
Terminate DO loops prematurely
Provide status information about the DO loop nesting level (DL<2:0>)

© 2009 Microchip Technology Inc.

DS70157D-page 21

16-bit MCU and DSC Programmer’s Reference Manual
2.5.13

Shadow Registers

A shadow register is used as a temporary holding register and can transfer its contents to or from
the associated host register upon some event. Some of the registers in the programmer’s model
have a shadow register, which is utilized during the execution of a DO, POP.S, or PUSH.S
instruction. Shadow register usage is shown in Table 2-2.
Note:

The DO instruction is only available in dsPIC30F and dsPIC33F devices.

Table 2-2:

Automatic Shadow Register Usage
DO(1)

POP.S/PUSH.S

DCOUNT(1)

Yes

—

DOSTART(1)

Yes

—

DOEND(1)

Yes

—

STATUS Register – DC, N, OV, Z and C bits

—

Yes

W0-W3

—

Yes

Location

Note 1:

The DO shadow registers are only available in dsPIC30F and dsPIC33F devices.

For dsPIC30F and dsPIC33F devices, since the DCOUNT, DOSTART and DOEND registers are
shadowed, the ability to nest DO loops without additional overhead is provided. Since all shadow
registers are one register deep, up to one level of DO loop nesting is possible. Further nesting of
DO loops is possible in software, with support provided by the DO Loop Nesting Level Status bits
(CORCON<10:8>) in the CORCON register.
Note:

DS70157D-page 22

All shadow registers are one register deep and are not directly accessible.
Additional shadowing may be performed in software using the software stack.

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
Register 2-1:

SR: CPU Status Register (PIC24H and PIC24F Devices)

U-0

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

—

—

—

DC

bit 15

bit 8

R/W-0

R/W-0

R/W-0

IPL<2:0>(1,2)

R-0

R/W-0

R/W-0

R/W-0

R/W-0

RA

N

OV

Z

C

bit 7

bit 0
U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

C = Clearable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented: Read as ‘0’

bit 8

DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data
of the result occurred
0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized data
of the result occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15). User interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)

bit 4

RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress

bit 3

N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)

bit 2

OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred

bit 1

Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0

C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> status bits are read only when NSTDIS = 1 (INTCON1<15>).

© 2009 Microchip Technology Inc.

DS70157D-page 23

Programmer’s
Model

Legend:

2

16-bit MCU and DSC Programmer’s Reference Manual
Register 2-2:

SR: CPU STATUS Register (dsPIC30F and dsPIC33F Devices)

R-0

R-0

R/C-0

R/C-0

R-0

R/C-0

R-0

R/W-0

OA

OB

SA(1,2)

SB(1,2)

OAB

SAB(1,2,3)

DA(4)

DC

bit 15

bit 8

R/W-0

R/W-0
IPL<2:0>

R/W-0

(5)

R-0
RA

R/W-0
N

R/W-0

R/W-0

OV

Z

R/W-0

(6)

bit 7

C
bit 0

Legend:
R = Readable bit

W = Writable bit

C = Clearable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

OA: Accumulator A Overflow bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed

bit 14

OB: Accumulator B Overflow bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed

bit 13

SA: Accumulator A Saturation bit(1,2)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated

bit 12

SB: Accumulator B Saturation bit(1,2)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated

bit 11

OAB: OA || OB Combined Accumulator Overflow bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed

bit 10

SAB: SA || SB Combined Accumulator bit(1,2,3)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulators A or B are saturated

bit 9

DA: DO Loop Active bit(4)
1 = DO loop in progress
0 = DO loop not in progress

bit 8

DC: MCU ALU Half Carry bit
1 = A carry-out from the Most Significant bit of the lower nibble occurred
0 = No carry-out from the Most Significant bit of the lower nibble occurred

Note 1: This bit may be read or cleared, but not set.
2: Once this bit is set, it must be cleared manually by software.
3: Clearing this bit will clear SA and SB.
4: This bit is read-only.
5: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1.
6: Refer to 4.9 “Z Status Bit” for operation with the ADDC, CPB, SUBB and SUBBR instructions.

DS70157D-page 24

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
Register 2-2:

SR: CPU STATUS Register (dsPIC30F and dsPIC33F Devices) (Continued)
IPL<2:0>: Interrupt Priority Level bits(5)
111 = CPU Interrupt Priority Level is 7 (15). User interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)

bit 4

RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress

bit 3

N: MCU ALU Negative bit
1 = The result of the operation was negative
0 = The result of the operation was not negative

bit 2

OV: MCU ALU Overflow bit
1 = Overflow occurred
0 = No overflow occurred

bit 1

Z: MCU ALU Zero bit(6)
1 = The result of the operation was zero
0 = The result of the operation was not zero

bit 0

C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit occurred
0 = No carry-out from the Most Significant bit occurred

2
Programmer’s
Model

bit 7-5

Note 1: This bit may be read or cleared, but not set.
2: Once this bit is set, it must be cleared manually by software.
3: Clearing this bit will clear SA and SB.
4: This bit is read-only.
5: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1.
6: Refer to 4.9 “Z Status Bit” for operation with the ADDC, CPB, SUBB and SUBBR instructions.

© 2009 Microchip Technology Inc.

DS70157D-page 25

16-bit MCU and DSC Programmer’s Reference Manual
Register 2-3:

CORCON: Core Control Register (PIC24F and PIC24H Devices)

U-0

U-0

U-0

U-0

U-0

U-0

U-0

U-0

—

—

—

—

—

—

—

—

bit 15

bit 8

U-0

U-0

—

U-0

—

—

U-0
—

R/C-0
IPL3

(1,2)

R/W-0

U-0

U-0

PSV

—

—

bit 7

bit 0

Legend:

C = Clearable bit

R = Readable bit

W = Writable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

U = Unimplemented bit, read as ‘0’
bit 15-4

Unimplemented: Read as ‘0’

bit 3

IPL3: Interrupt Priority Level 3 Status bit(1,2)
1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated)
0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated)

bit 2

PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space

bit 1-0

Unimplemented: Do not use

Note 1: This bit may be read or cleared, but not set.
2: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

DS70157D-page 26

© 2009 Microchip Technology Inc.

Section 2. Programmer’s Model
Register 2-4:

CORCON: Core Control Register (dsPIC30F and dsPIC33F Devices)

U

U

U

R/W-0

R(0)/W-0

—

—

—

US

EDT(1)

R-0

R-0

R/W-0

DL<2:0>(2,3)

bit 15

bit 8

R/W-0

R/W-0

SATA

SATB

R/W-1
SATDW

R/W-0
ACCSAT

R/C-0
(4,5)

IPL3

R/W-0

R/W-0

R/W-0

PSV

RND

IF

bit 7

bit 0
C = Clearable bit

R = Readable bit

W = Writable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

U = Unimplemented bit, read as ‘0’
bit 15-13

Unimplemented: Do not use

bit 12

US: Unsigned or Signed Multiplier Mode Select bit
1 = Unsigned mode enabled for DSP multiply operations
0 = Signed mode enabled for DSP multiply operations

bit 11

EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current iteration
0 = No effect

bit 10-8

DL<2:0>: DO Loop Nesting Level Status bits(2,3)
111 = DO looping is nested at 7 levels
110 = DO looping is nested at 6 levels
110 = DO looping is nested at 5 levels
110 = DO looping is nested at 4 levels
011 = DO looping is nested at 3 levels
010 = DO looping is nested at 2 levels
001 = DO looping is active, but not nested (just 1 level)
000 = DO looping is not active

bit 7

SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled

bit 6

SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled

bit 5

SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled

bit 4

ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (Super Saturation)
0 = 1.31 saturation (Normal Saturation)

bit 3

IPL3: Interrupt Priority Level 3 Status bit(4,5)
1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated)
0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated)

Note 1: This bit will always read ‘0’.
2: DL<2:1> are read-only.
3: The first two levels of DO loop nesting are handled by hardware.
4: This bit may be read or cleared, but not set.
5: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

© 2009 Microchip Technology Inc.

DS70157D-page 27

Programmer’s
Model

Legend:

2

16-bit MCU and DSC Programmer’s Reference Manual
Register 2-4:

CORCON: Core Control Register (dsPIC30F and dsPIC33F Devices) (Continued)

bit 2

PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space

bit 1

RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled

bit 0

IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply operations
0 = Fractional mode enabled for DSP multiply operations

Note 1: This bit will always read ‘0’.
2: DL<2:1> are read-only.
3: The first two levels of DO loop nesting are handled by hardware.
4: This bit may be read or cleared, but not set.
5: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

DS70157D-page 28

© 2009 Microchip Technology Inc.

Section 3. Instruction Set Overview
HIGHLIGHTS
This section of the manual contains the following major topics:
3.1
3.2
3.3

Introduction ..................................................................................................................... 30
Instruction Set Overview ................................................................................................. 30
Instruction Set Summary Tables ..................................................................................... 32

3
Instruction Set
Overview

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual
3.1

INTRODUCTION
The 16-bit MCU and DSC instruction set provides a broad suite of instructions, which supports
traditional microcontroller applications and a class of instructions, which supports math intensive
applications. Since almost all of the functionality of the PIC® MCU instruction set has been
maintained, this hybrid instruction set allows a friendly DSP migration path for users already
familiar with the PIC microcontroller.

3.2

INSTRUCTION SET OVERVIEW
Depending on the device family, the 16-bit MCU and DSC instruction set contains up to 83
instructions, which can be grouped into the functional categories shown in Table 3-1. Table 1-2
defines the symbols used in the instruction summary tables, Table 3-2 through Table 3-11. These
tables define the syntax, description, storage and execution requirements for each instruction.
Storage requirements are represented in 24-bit instruction words and execution requirements
are represented in instruction cycles.
Table 3-1:

Instruction Groups
Functional Group

Summary Table

Page Number

Move Instructions

Table 3-2

3-32

Math Instructions

Table 3-3

3-32

Logic Instructions

Table 3-4

3-34

Rotate/Shift Instructions

Table 3-5

3-35

Bit Instructions

Table 3-6

3-36

Compare/Skip Instructions

Table 3-7

3-37

Program Flow Instructions

Table 3-8

3-38

Shadow/Stack Instructions

Table 3-9

3-39

Control Instructions

Table 3-10

3-39

DSP Instructions(1)

Table 3-11

3-39

Note 1:

DSP instructions are only available in the dsPIC30F and dsPIC33F device families.

Most instructions have several different Addressing modes and execution flows, which require
different instruction variants. For instance, depending on the device family, there are up to six
unique ADD instructions and each instruction variant has its own instruction encoding. Instruction
format descriptions and specific instruction operation are provided in Section 5. “Instruction
Descriptions”. Additionally, a composite alphabetized instruction set table is provided in
Section 6. “Reference”.

DS70157D-page 30

© 2009 Microchip Technology Inc.

Section 3. Instruction Set Overview
3.2.1

Multi-Cycle Instructions

As the instruction summary tables show, most instructions execute in a single cycle, with the
following exceptions:
Note:

The DO and DIVF instructions are only available in the dsPIC30F and dsPIC33F
device families.

• Instructions DO, MOV.D, POP.D, PUSH.D, TBLRDH, TBLRDL, TBLWTH and TBLWTL
require 2 cycles to execute.
• Instructions DIV.S, DIV.U and DIVF are single-cycle instructions, which should be executed 18 consecutive times as the target of a REPEAT instruction.
• Instructions that change the program counter also require 2 cycles to execute, with the
extra cycle executed as a NOP. SKIP instruction, which skips over a 2-word instruction,
requires 3 instruction cycles to execute, with 2 cycles executed as a NOP.
• The RETFIE, RETLW and RETURN are a special case of an instruction that changes the
program counter. These execute in 3 cycles, unless an exception is pending and then they
execute in 2 cycles.
Note:

Multi-Word Instructions

As defined by Table 3-2: “Move Instructions”, almost all instructions consume one instruction
word (24 bits), with the exception of the CALL, DO and GOTO instructions, which are Program
Flow Instructions, listed in Table 3-8. These instructions require two words of memory because
their opcodes embed large literal operands.

© 2009 Microchip Technology Inc.

DS70157D-page 31

3
Instruction Set
Overview

3.2.2

Instructions that access program memory as data, using Program Space Visibility
(PSV), will incur a one or two cycle delay for all 16-bit MCU and DSC devices. When
the target instruction of a REPEAT loop accesses program memory as data, only the
first execution of the target instruction is subject to the delay. See the specific device
family reference manual for details.

16-bit MCU and DSC Programmer’s Reference Manual
3.3

INSTRUCTION SET SUMMARY TABLES

Table 3-2:

Move Instructions
Words

Cycles

Page
Number

Swap Wns and Wnd

1

1

5-203

Assembly Syntax
EXCH

Description

Wns,Wnd
(1)

MOV

f {,WREG}

Move f to destination

1

1

5-233

MOV

WREG,f

Move WREG to f

1

1

5-234

MOV

f,Wnd

Move f to Wnd

1

1

5-235

MOV

Wns,f

Move Wns to f

1

1

5-236

MOV.B

#lit8,Wnd

Move 8-bit literal to Wnd

1

1

5-237

MOV

#lit16,Wnd

Move 16-bit literal to Wnd

1

1

5-238

MOV

[Ws+Slit10],Wnd

Move [Ws + signed 10-bit offset] to Wnd

1

1

5-239

MOV

Wns,[Wd+Slit10]

Move Wns to [Wd + signed 10-bit offset]

1

1

5-240

MOV

Ws,Wd

Move Ws to Wd

1

1

5-241

MOV.D

Ws,Wnd

Move double Ws to Wnd:Wnd + 1

1

2

5-243

MOV.D

Wns,Wd

Move double Wns:Wns + 1 to Wd

1

2

5-243

SWAP

Wn

Wn = byte or nibble swap Wn

1

1

5-340

TBLRDH

Ws,Wd

Read high program word to Wd

1

2

5-341

TBLRDL

Ws,Wd

Read low program word to Wd

1

2

5-343

TBLWTH

Ws,Wd

Write Ws to high program word

1

2

5-345

TBLWTL

Ws,Wd

Write Ws to low program word

1

2

5-347

Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
Table 3-3:

Math Instructions

Assembly Syntax

Description

Words

Cycles

Page
Number

ADD

f {,WREG}(1)

Destination = f + WREG

1

1

5-89

ADD

#lit10,Wn

Wn = lit10 + Wn

1

1

5-90

ADD

Wb,#lit5,Wd

Wd = Wb + lit5

1

1

5-91

ADD

Wb,Ws,Wd

Wd = Wb + Ws

1

1

5-93

ADDC

f {,WREG}(1)

Destination = f + WREG + (C)

1

1

5-98

ADDC

#lit10,Wn

Wn = lit10 + Wn + (C)

1

1

5-99

ADDC

Wb,#lit5,Wd

Wd = Wb + lit5 + (C)

1

1

5-100

ADDC

Wb,Ws,Wd

Wd = Wb + Ws + (C)

1

1

5-102

DAW.B

Wn

Wn = decimal adjust Wn

1

1

5-183

DEC

f {,WREG}(1)

Destination = f – 1

1

1

5-184

DEC

Ws,Wd

Wd = Ws – 1

1

1

5-185

DEC2

f {,WREG}(1)

Destination = f – 2

1

1

5-186

DEC2

Ws,Wd

Wd = Ws – 2

1

1

5-187

DIV.S

Wm, Wn

Signed 16/16-bit integer divide

1

18(2)

5-189

DIV.SD

Wm, Wn

Signed 32/16-bit integer divide

1

18(2)

5-189

DIV.U

Wm, Wn

Unsigned 16/16-bit integer divide

1

18(2)

5-191

Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
2: The divide instructions must be preceded with a “REPEAT #17” instruction, such that they are executed
18 consecutive times.

DS70157D-page 32

© 2009 Microchip Technology Inc.

Section 3. Instruction Set Overview
Table 3-3:

Math Instructions (Continued)

Assembly Syntax
DIV.UD

Description
Unsigned 32/16-bit integer divide

Wm, Wn

Words

Cycles

Page
Number

1

18(2)

5-191

(2)

Wm, Wn

Signed 16/16-bit fractional divide

1

18

INC

f {,WREG}(1)

Destination = f + 1

1

1

5-212

INC

Ws,Wd

Wd = Ws + 1

1

1

5-213

INC2

f {,WREG}(1)

Destination = f + 2

1

1

5-214

INC2

Ws,Wd

Wd = Ws + 2

1

1

5-215

MUL

f

W3:W2 = f * WREG

1

1

5-255

MUL.SS

Wb,Ws,Wnd

{Wnd + 1,Wnd} = signed(Wb) * signed(Ws)

1

1

5-256

MUL.SU

Wb,#lit5,Wnd

{Wnd + 1,Wnd} = signed(Wb) * unsigned(lit5)

1

1

5-258

MUL.SU

Wb,Ws,Wnd

{Wnd + 1,Wnd} = signed(Wb) * unsigned(Ws)

1

1

5-260

MUL.SU

Wb,#lit5,Wnd

{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)

1

1

5-260

MUL.US

Wb,Ws,Wnd

{Wnd + 1,Wnd} = unsigned(Wb) * signed(Ws)

1

1

5-262

MUL.UU

Wb,Ws,Wnd

{Wnd + 1,Wnd} = unsigned(Wb) * unsigned(Ws)

1

1

5-265

MUL.UU

Wb,#lit5,Wnd

{Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5)

1

1

5-264

SE

Ws,Wnd

Wnd = signed-extended Ws

1

1

5-309

SUB

f {,WREG}(1)

Destination = f – WREG

1

1

5-319

SUB

#lit10,Wn

Wn = Wn – lit10

1

1

5-320

SUB

Wb,#lit5,Wd

Wd = Wb – lit5

1

1

5-321

SUB

Wb,Ws,Wd

Wd = Wb – Ws

1

1

5-322

SUBB

f {,WREG}(1)

Destination = f – WREG – (C)

1

1

5-325

SUBB

#lit10,Wn

Wn = Wn – lit10 – (C)

1

1

5-326

SUBB

Wb,Ws,Wd

Wd = Wb – Ws – (C)

1

1

5-329

(1)

5-193

SUBBR

f {,WREG}

Destination = WREG – f – (C)

1

1

5-331

SUBBR

Wb,#lit5,Wd

Wd = lit5 – Wb – (C)

1

1

5-332

SUBBR

Wb,Ws,Wd

Wd = Ws – Wb – (C)

1

1

5-334

SUBR

f {,WREG}(1)

Destination = WREG – f

1

1

5-336

SUBR

Wb,#lit5,Wd

Wd = lit5 – Wb

1

1

5-337

SUBR

Wb,Ws,Wd

Wd = Ws – Wb

1

1

5-338

ZE

Ws,Wnd

Wnd = zero-extended Ws

1

1

5-355

Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
2: The divide instructions must be preceded with a “REPEAT #17” instruction, such that they are executed
18 consecutive times.

© 2009 Microchip Technology Inc.

DS70157D-page 33

3
Instruction Set
Overview

DIVF

16-bit MCU and DSC Programmer’s Reference Manual
Table 3-4:

Logic Instructions

Assembly Syntax

Description

Words

Cycles

Page
Number

1

1

5-104

AND

f {,WREG}(1)

Destination = f .AND. WREG

AND

#lit10,Wn

Wn = lit10 .AND. Wn

1

1

5-105

AND

Wb,#lit5,Wd

Wd = Wb .AND. lit5

1

1

5-106

AND

Wb,Ws,Wd

Wd = Wb .AND. Ws

1

1

5-107

CLR

f

f = 0x0000

1

1

5-163

CLR

WREG

WREG = 0x0000

1

1

5-163

CLR

Wd

Wd = 0x0000

1

1

5-164

COM

f {,WREG}(1)

Destination = f

1

1

5-168

COM

Ws,Wd

Wd = Ws

1

1

5-169

(1)

IOR

f {,WREG}

Destination = f .IOR. WREG

1

1

5-216

IOR

#lit10,Wn

Wn = lit10 .IOR. Wn

1

1

5-217

IOR

Wb,#lit5,Wd

Wd = Wb .IOR. lit5

1

1

5-218

IOR

Wb,Ws,Wd

Wd = Wb .IOR. Ws

1

1

5-219

NEG

f {,WREG}(1)

Destination = f + 1

1

1

5-267

NEG

Ws,Wd

Wd = Ws + 1

1

1

5-268

SETM

f

f = 0xFFFF

1

1

5-310

SETM

WREG

WREG = 0xFFFF

1

1

5-310

SETM

Wd

Wd = 0xFFFF

1

1

5-311
5-350

{,WREG}(1)

XOR

f

Destination = f .XOR. WREG

1

1

XOR

#lit10,Wn

Wn = lit10 .XOR. Wn

1

1

5-351

XOR

Wb,#lit5,Wd

Wd = Wb .XOR. lit5

1

1

5-352

XOR

Wb,Ws,Wd

Wd = Wb .XOR. Ws

1

1

5-353

Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.

DS70157D-page 34

© 2009 Microchip Technology Inc.

Section 3. Instruction Set Overview
Table 3-5:

Rotate/Shift Instructions

Assembly Syntax
{,WREG}(1)

Description

Words

Cycles

Page #

ASR

f

Destination = arithmetic right shift f

1

1

5-109

ASR

Ws,Wd

Wd = arithmetic right shift Ws

1

1

5-111

ASR

Wb,#lit4,Wnd

Wnd = arithmetic right shift Wb by lit4

1

1

5-113

ASR

Wb,Wns,Wnd

Wnd = arithmetic right shift Wb by Wns

1

1

5-114

{,WREG}(1)

LSR

f

Destination = logical right shift f

1

1

5-224

LSR

Ws,Wd

Wd = logical right shift Ws

1

1

5-225

LSR

Wb,#lit4,Wnd

Wnd = logical right shift Wb by lit4

1

1

5-227

LSR

Wb,Wns,Wnd

Wnd = logical right shift Wb by Wns

1

1

5-228

Destination = rotate left through Carry f

1

1

5-293

Wd = rotate left through Carry Ws

1

1

5-294

Destination = rotate left (no Carry) f

1

1

5-296

Wd = rotate left (no Carry) Ws

1

1

5-297

{,WREG}(1)

RLC

f

RLC

Ws,Wd
{,WREG}(1)

RLNC

f

RLNC

Ws,Wd
{,WREG}(1)

f

Destination = rotate right through Carry f

1

1

5-299

RRC

Ws,Wd

Wd = rotate right through Carry Ws

1

1

5-300

RRNC

f {,WREG}(1)

Destination = rotate right (no Carry) f

1

1

5-302

RRNC

Ws,Wd

Wd = rotate right (no Carry) Ws

1

1

5-303

SL

f {,WREG}(1)

Destination = left shift f

1

1

5-314

SL

Ws,Wd

Wd = left shift Ws

1

1

5-315

SL

Wb,#lit4,Wnd

Wnd = left shift Wb by lit4

1

1

5-317

SL

Wb,Wns,Wnd

Wnd = left shift Wb by Wns

1

1

5-318

Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.

© 2009 Microchip Technology Inc.

DS70157D-page 35

3
Instruction Set
Overview

RRC

16-bit MCU and DSC Programmer’s Reference Manual
Table 3-6:

Bit Instructions

Assembly Syntax

Description

Words

Cycles

Page
Number

1

1

5-115

BCLR

f,#bit4

Bit clear f

BCLR

Ws,#bit4

Bit clear Ws

1

1

5-116

BSET

f,#bit4

Bit set f

1

1

5-140

BSET

Ws,#bit4

Bit set Ws

1

1

5-141

BSW.C

Ws,Wb

Write C bit to Ws

1

1

5-142

BSW.Z

Ws,Wb

Write Z bit to Ws

1

1

5-142

BTG

f,#bit4

Bit toggle f

1

1

5-144

BTG

Ws,#bit4

Bit toggle Ws

1

1

5-145

BTST

f,#bit4

Bit test f

1

1

5-153

BTST.C

Ws,#bit4

Bit test Ws to C

1

1

5-154

BTST.Z

Ws,#bit4

Bit test Ws to Z

1

1

5-154

BTST.C

Ws,Wb

Bit test Ws to C

1

1

5-155

BTST.Z

Ws,Wb

Bit test Ws to Z

1

1

5-155

BTSTS

f,#bit4

Bit test f then set f

1

1

5-157

BTSTS.C

Ws,#bit4

Bit test Ws to C then set Ws

1

1

5-158

BTSTS.Z

Ws,#bit4

Bit test Ws to Z then set Ws

1

1

5-158

FBCL

Ws,Wnd

Find bit change from left (MSb) side

1

1

5-204

FF1L

Ws,Wnd

Find first one from left (MSb) side

1

1

5-206

FF1R

Ws,Wnd

Find first one from right (LSb) side

1

1

5-208

DS70157D-page 36

© 2009 Microchip Technology Inc.

Section 3. Instruction Set Overview
Table 3-7:

Compare/Skip Instructions

Assembly Syntax

Description

Words

Cycles(1)

Page
Number

BTSC

f,#bit4

Bit test f, skip if clear

1

1 (2 or 3)

5-146

BTSC

Ws,#bit4

Bit test Ws, skip if clear

1

1 (2 or 3)

5-148

BTSS

f,#bit4

Bit test f, skip if set

1

1 (2 or 3)

5-150

BTSS

Ws,#bit4

Bit test Ws, skip if set

1

1 (2 or 3)

5-151

CP

f

Compare (f – WREG)

1

1

5-170

CP

Wb,#lit5

Compare (Wb – lit5)

1

1

5-171

CP

Wb,Ws

Compare (Wb – Ws)

1

1

5-172

CP0

f

Compare (f – 0x0000)

1

1

5-173

CP0

Ws

Compare (Ws – 0x0000)

1

1

5-174

CPB

f

Compare with Borrow (f – WREG – C)

1

1

5-175

CPB

Wb,#lit5

Compare with Borrow (Wb – lit5 – C)

1

1

5-176

Wb,Ws

Compare with Borrow (Wb – Ws – C)

1

1

5-177

Wb, Wn

Compare (Wb – Wn), skip if =

1

1 (2 or 3)

5-179

CPSGT

Wb, Wn

Compare (Wb – Wn), skip if >

1

1 (2 or 3)

5-180

CPSLT

Wb, Wn

Compare (Wb – Wn), skip if <

1

1 (2 or 3)

5-181

CPSNE

Wb, Wn

Compare (Wb – Wn), skip if ≠

1

1 (2 or 3)

5-182

Note 1: Conditional skip instructions execute in 1 cycle if the skip is not taken, 2 cycles if the skip is taken over a
one-word instruction and 3 cycles if the skip is taken over a two-word instruction.

© 2009 Microchip Technology Inc.

DS70157D-page 37

3
Instruction Set
Overview

CPB
CPSEQ

16-bit MCU and DSC Programmer’s Reference Manual
Table 3-8:

Program Flow Instructions

Assembly Syntax

Description

Words

Cycles

Page
Number

2

5-117
5-118

BRA

Expr

Branch unconditionally

1

BRA

Wn

Computed branch

1

2

BRA

C,Expr

Branch if Carry (no Borrow)

1

1 (2)(1)

5-119

(1)

5-121

BRA

GE,Expr

Branch if greater than or equal

1

1 (2)

BRA

GEU,Expr

Branch if unsigned greater than or equal

1

1 (2)(1)

5-122

BRA

GT,Expr

Branch if greater than

1

1 (2)(1)

5-123

(1)

BRA

GTU,Expr

Branch if unsigned greater than

1

1 (2)

5-124

BRA

LE,Expr

Branch if less than or equal

1

1 (2)(1)

5-125

BRA

LEU,Expr

Branch if unsigned less than or equal

1

1 (2)(1)

5-126

(1)

BRA

LT,Expr

Branch if less than

1

1 (2)

5-127

BRA

LTU,Expr

Branch if unsigned less than

1

1 (2)(1)

5-128

BRA

N,Expr

Branch if Negative

1

1 (2)(1)

5-129

(1)

BRA

NC,Expr

Branch if not Carry (Borrow)

1

1 (2)

5-130

BRA

NN,Expr

Branch if not Negative

1

1 (2)(1)

5-131

BRA

NOV,Expr

Branch if not Overflow

1

1 (2)(1)

5-132

(2)(1)

5-133

BRA

NZ,Expr

Branch if not Zero

1

1

BRA

OA,Expr

Branch if Accumulator A Overflow

1

1 (2)(1)

5-134

BRA

OB,Expr

Branch if Accumulator B Overflow

1

1 (2)(1)

5-135

(2)(1)

5-136

BRA

OV,Expr

Branch if Overflow

1

1

BRA

SA,Expr

Branch if Accumulator A Saturate

1

1 (2)(1)

5-137

BRA

SB,Expr

Branch if Accumulator B Saturate

1

1 (2)(1)

5-138

(2)(1)

BRA

Z,Expr

Branch if Zero

1

CALL

Expr

Call subroutine

2

2

5-159

CALL

Wn

Call indirect subroutine

1

2

5-161

DO

#lit14,Expr(3)

Do code through PC + Expr, (lit14 + 1) times

2

2

5-195

DO

Wn,Expr(3)

Do code through PC + Expr, (Wn + 1) times

2

2

5-197

GOTO

Expr

Go to address

2

2

5-210

GOTO

Wn

Go to address indirectly

1

2

5-211

RCALL

Expr

Relative call

1

2

5-281

RCALL

Wn

Computed call

1

2

5-283

REPEAT

#lit14

Repeat next instruction (lit14 + 1) times

1

1

5-285

REPEAT

Wn

Repeat next instruction (Wn + 1) times

1

1

5-286

Return from interrupt enable

1

3 (2)(2)

5-290

Return with lit10 in Wn

1

3 (2)(2)

5-291

Return from subroutine

1

3 (2)(2)

5-292

RETFIE
RETLW

#lit10,Wn

RETURN

1

5-139

Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken, or 2 cycles if the branch is
taken.
2: RETURN instructions execute in 3 cycles, but if an exception is pending, they execute in 2 cycles.
3: This instruction is only available in dsPIC30F and dsPIC33F devices.

DS70157D-page 38

© 2009 Microchip Technology Inc.

Section 3. Instruction Set Overview
Table 3-9:

Shadow/Stack Instructions

Assembly Syntax

Description

Words

Cycles

Page
Number

1

1

5-223

LNK

#lit14

Link Frame Pointer

POP

f

POP TOS to f

1

1

5-272

POP

Wd

POP TOS to Wd

1

1

5-273

POP.D

Wnd

Double POP from TOS to Wnd:Wnd + 1

1

2

5-274

POP shadow registers

1

1

5-275

POP.S
PUSH

f

PUSH f to TOS

1

1

5-276

PUSH

Ws

PUSH Ws to TOS

1

1

5-277

PUSH.D

Wns

PUSH double Wns:Wns + 1 to TOS

1

2

5-278

PUSH.S

PUSH shadow registers

1

1

5-279

ULNK

Unlink Frame Pointer

1

1

5-349

Words

Cycles

Page
Number

Clear Watchdog Timer

1

1

5-167

Disable interrupts for (lit14 + 1) instruction cycles

1

1

5-188

NOP

No operation

1

1

5-270

NOPR

No operation

1

1

5-271

Table 3-10:

Control Instructions

Assembly Syntax
CLRWDT

PWRSAV

#lit14

#lit1

RESET
Table 3-11:

Enter Power-saving mode lit1

1

1

5-280

Software device Reset

1

1

5-288

Words

Cycles

Page
Number

DSP Instructions (dsPIC30F and dsPIC33F Devices)
Assembly Syntax

Description

ADD

Acc

Add accumulators

1

1

5-95

ADD

Ws,#Slit4,Acc

16-bit signed add to Acc

1

1

5-96

CLR

Acc,Wx,Wxd,Wy,Wyd,AWB

Clear Acc

1

1

5-165

ED

Wm*Wm,Acc,Wx,Wy,Wxd

Euclidean distance
(no accumulate)

1

1

5-199

EDAC

Wm*Wm,Acc,Wx,Wy,Wxd

Euclidean distance

1

1

5-201

LAC

Ws,#Slit4,Acc

Load Acc

1

1

5-221

MAC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and accumulate

1

1

5-229

MAC

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Square and accumulate

1

1

5-231

MOVSAC

Acc,Wx,Wxd,Wy,Wyd,AWB

Move Wx to Wxd and Wy to Wyd

1

1

5-245

MPY

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

Multiply Wn by Wm to Acc

1

1

5-247

MPY

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Square to Acc

1

1

5-249

MPY.N

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

-(Multiply Wn by Wm) to Acc

1

1

5-251

MSC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and subtract from Acc

1

1

5-253

NEG

Acc

Negate Acc

1

1

5-269

SAC

Acc,#Slit4,Wd

Store Acc

1

1

5-305

SAC.R

Acc,#Slit4,Wd

Store rounded Acc

1

1

5-307

SFTAC

Acc,#Slit6

Arithmetic shift Acc by Slit6

1

1

5-312

SFTAC

Acc,Wn

Arithmetic shift Acc by (Wn)

1

1

5-313

SUB

Acc

Subtract accumulators

1

1

5-324

© 2009 Microchip Technology Inc.

DS70157D-page 39

3
Instruction Set
Overview

DISI

Description

16-bit MCU and DSC Programmer’s Reference Manual
NOTES:

DS70157D-page 40

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
HIGHLIGHTS
This section of the manual contains the following major topics:
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17

Data Addressing Modes.................................................................................................. 42
Program Addressing Modes ........................................................................................... 51
Instruction Stalls.............................................................................................................. 52
Byte Operations .............................................................................................................. 54
Word Move Operations ................................................................................................... 56
Using 10-bit Literal Operands ......................................................................................... 59
Software Stack Pointer and Frame Pointer ..................................................................... 60
Conditional Branch Instructions ...................................................................................... 65
Z Status Bit...................................................................................................................... 66
Assigned Working Register Usage ................................................................................. 67
DSP Data Formats (dsPIC30F and dsPIC33F Devices)................................................. 70
Accumulator Usage (dsPIC30F and dsPIC33F Devices) ............................................... 72
Accumulator Access (dsPIC30F and dsPIC33F Devices) .............................................. 73
DSP MAC Instructions (dsPIC30F and dsPIC33F Devices) ........................................... 74
DSP Accumulator Instructions (dsPIC30F and dsPIC33F Devices) ............................... 78
Scaling Data with the FBCL Instruction (dsPIC30F and dsPIC33F Devices) ................. 79
Normalizing the Accumulator with the FBCL Instruction (dsPIC30F and dsPIC33F
Devices) .......................................................................................................................... 81

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

DS70157D-page 41

16-bit MCU and DSC Programmer’s Reference Manual
4.1

DATA ADDRESSING MODES
The 16-bit MCU and DSC devices support three native Addressing modes for accessing data
memory, along with several forms of immediate addressing. Data accesses may be performed
using file register, register direct or register indirect addressing, and immediate addressing
allows a fixed value to be used by the instruction.
File register addressing provides the ability to operate on data stored in the lower 8K of data
memory (Near RAM), and also move data between the working registers and the entire 64K data
space. Register direct addressing is used to access the 16 memory mapped working registers,
W0:W15. Register indirect addressing is used to efficiently operate on data stored in the entire
64K data space, using the contents of the working registers as an effective address. Immediate
addressing does not access data memory, but provides the ability to use a constant value as an
instruction operand. The address range of each mode is summarized in Table 4-1.
Table 4-1:

16-Bit MCU and DSC Addressing Modes

Addressing Mode

0x0000-0x1FFF (see Note)

Register Direct

0x0000-0x001F (working register array W0:W15)

Register Indirect

0x0000-0xFFFF

Immediate

N/A (constant value)

Note:

4.1.1

Address Range

File Register

The address range for the File Register MOV is 0x0000-0xFFFE.

File Register Addressing
File register addressing is used by instructions which use a predetermined data address as an
operand for the instruction. The majority of instructions that support file register addressing
provide access to the lower 8 Kbytes of data memory, which is called the Near RAM. However,
the MOV instruction provides access to all 64 Kbytes of memory using file register addressing.
This allows the loading of the data from any location in data memory to any working register, and
store the contents of any working register to any location in data memory. It should be noted that
file register addressing supports both byte and word accesses of data memory, with the
exception of the MOV instruction, which accesses all 64K of memory as words. Examples of file
register addressing are shown in Example 4-1.
Most instructions, which support file register addressing, perform an operation on the specified
file register and the default working register WREG (see 2.4 “Default Working Register
(WREG)”). If only one operand is supplied in the instruction, WREG is an implied operand and
the operation results are stored back to the file register. In these cases, the instruction is
effectively a read-modify-write instruction. However, when both the file register and WREG are
specified in the instruction, the operation results are stored in WREG and the contents of the file
register are unchanged. Sample instructions which show the interaction between the file register
and WREG are shown in Example 4-2.
Note:

DS70157D-page 42

Instructions which support file register addressing use ‘f’ as an operand in the
instruction summary tables of Section 3. “Instruction Set Overview”.

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
Example 4-1:
DEC

File Register Addressing
0x1000

; decrement data stored at 0x1000

Before Instruction:
Data Memory 0x1000 = 0x5555

After Instruction:
Data Memory 0x1000 = 0x5554
MOV

0x27FE, W0

; move data stored at 0x27FE to W0

Before Instruction:
W0 = 0x5555
Data Memory 0x27FE = 0x1234

After Instruction:
W0 = 0x1234
Data Memory 0x27FE = 0x1234

Example 4-2:
AND

File Register Addressing and WREG
0x1000

; AND 0x1000 with WREG, store to 0x1000

Before Instruction:
W0 (WREG) = 0x332C
Data Memory 0x1000 = 0x5555

After Instruction:
W0 (WREG) = 0x332C
Data Memory 0x1000 = 0x1104
AND

0x1000, WREG

; AND 0x1000 with WREG, store to WREG

Before Instruction:
W0 (WREG) = 0x332C
Data Memory 0x1000 = 0x5555

After Instruction:
W0 (WREG) = 0x1104
Data Memory 0x1000 = 0x5555

Register Direct Addressing

Register direct addressing is used to access the contents of the 16 working registers (W0:W15).
The Register Direct Addressing mode is fully orthogonal, which allows any working register to be
specified for any instruction that uses register direct addressing, and it supports both byte and
word accesses. Instructions which employ register direct addressing use the contents of the
specified working register as data to execute the instruction, therefore this Addressing mode is
useful only when data already resides in the working register core. Sample instructions which
utilize register direct addressing are shown in Example 4-3.
Another feature of register direct addressing is that it provides the ability for dynamic flow control.
Since variants of the DO and REPEAT instruction support register direct addressing, flexible
looping constructs may be generated using these instructions.
Note:

© 2009 Microchip Technology Inc.

Instructions which must use register direct addressing, use the symbols Wb, Wn,
Wns and Wnd in the summary tables of Section 3. “Instruction Set Overview”.
Commonly, register direct addressing may also be used when register indirect
addressing may be used. Instructions which use register indirect addressing, use
the symbols Wd and Ws in the summary tables of Section 3. “Instruction Set
Overview”.

DS70157D-page 43

Instruction Set
Details

4.1.2

4

16-bit MCU and DSC Programmer’s Reference Manual
Example 4-3:
EXCH

Register Direct Addressing

W2, W3

; Exchange W2 and W3

Before Instruction:
W2 = 0x3499
W3 = 0x003D

After Instruction:
W2 = 0x003D
W3 = 0x3499

IOR

#0x44, W0

; Inclusive-OR 0x44 and W0

Before Instruction:
W0 = 0x9C2E

After Instruction:
W0 = 0x9C6E
SL

W6, W7, W8

; Shift left W6 by W7, and store to W8

Before Instruction:
W6 = 0x000C
W7 = 0x0008
W8 = 0x1234

After Instruction:
W6 = 0x000C
W7 = 0x0008
W8 = 0x0C00

4.1.3

Register Indirect Addressing

Register indirect addressing is used to access any location in data memory by treating the
contents of a working register as an Effective Address (EA) to data memory. Essentially, the
contents of the working register become a pointer to the location in data memory which is to be
accessed by the instruction.
This Addressing mode is powerful, because it also allows one to modify the contents of the
working register, either before or after the data access is made, by incrementing or decrementing
the EA. By modifying the EA in the same cycle that an operation is being performed, register
indirect addressing allows for the efficient processing of data that is stored sequentially in
memory. The modes of indirect addressing supported by the 16-bit MCU and DSC devices are
shown in Table 4-2.
Table 4-2:

Indirect Addressing Modes

Indirect Mode
No Modification

Syntax
[Wn]

Function
(Byte Instruction)
EA = [Wn]

Function
(Word Instruction)
EA = [Wn]

Description
The contents of Wn forms the EA.

Pre-Increment

[++Wn]

EA = [Wn + = 1]

EA = [Wn + = 2]

Wn is pre-incremented to form the EA.

Pre-Decrement

[--Wn]

EA = [Wn – = 1]

EA = [Wn – = 2]

Wn is pre-decremented to form the EA.

Post-Increment

[Wn++]

EA = [Wn]+ = 1

EA = [Wn]+ = 2

The contents of Wn forms the EA, then
Wn is post-incremented.

EA = [Wn] – = 1

EA = [Wn] – = 2

The contents of Wn forms the EA, then
Wn is post-decremented.

EA = [Wn + Wb]

The sum of Wn and Wb forms the EA.
Wn and Wb are not modified.

Post-Decrement [Wn--]
Register Offset

DS70157D-page 44

[Wn+Wb] EA = [Wn + Wb]

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
Table 4-2 shows that four Addressing modes modify the EA used in the instruction, and this
allows the following updates to be made to the working register: post-increment, post-decrement,
pre-increment and pre-decrement. Since all EAs must be given as byte addresses, support is
provided for Word mode instructions by scaling the EA update by 2. Namely, in Word mode,
pre/post-decrements subtract 2 from the EA stored in the working register, and
pre/post-increments add 2 to the EA. This feature ensures that after an EA modification is made,
the EA will point to the next adjacent word in memory. Example 4-4 shows how indirect
addressing may be used to update the EA.
Table 4-2 also shows that the Register Offset mode addresses data which is offset from a base
EA stored in a working register. This mode uses the contents of a second working register to form
the EA by adding the two specified working registers. This mode does not scale for Word mode
instructions, but offers the complete offset range of 64 Kbytes. Note that neither of the working
registers used to form the EA are modified. Example 4-5 shows how register offset indirect
addressing may be used to access data memory.
Note:

The MOV with offset instructions (see pages 5-239 and 5-240) provides a literal
addressing offset ability to be used with indirect addressing. In these instructions,
the EA is formed by adding the contents of a working register to a signed 10-bit
literal. Example 4-6 shows how these instructions may be used to move data to and
from the working register array.

Example 4-4:
MOV.B

Indirect Addressing with Effective Address Update
[W0++], [W13--]

; byte move [W0] to [W13]
; post-inc W0, post-dec W13

Before Instruction:
W0 = 0x2300
W13 = 0x2708
Data Memory 0x2300 = 0x7783
Data Memory 0x2708 = 0x904E

After Instruction:
W0 = 0x2301
W13 = 0x2707
Data Memory 0x2300 = 0x7783
Data Memory 0x2708 = 0x9083
ADD

W1, [--W5], [++W8]

4

Before Instruction:
W1 =
W5 =
W8 =
Data
Data

0x0800
0x2200
0x2400
Memory 0x21FE = 0x7783
Memory 0x2402 = 0xAACC

After Instruction:
W1 =
W5 =
W8 =
Data
Data

© 2009 Microchip Technology Inc.

0x0800
0x21FE
0x2402
Memory 0x21FE = 0x7783
Memory 0x2402 = 0x7F83

DS70157D-page 45

Instruction Set
Details

; pre-dec W5, pre-inc W8
; add W1 to [W5], store in [W8]

16-bit MCU and DSC Programmer’s Reference Manual
Example 4-5:
MOV.B

Indirect Addressing with Register Offset
[W0+W1], [W7++]

; byte move [W0+W1] to W7, post-inc W7

Before Instruction:
W0 =
W1 =
W7 =
Data
Data

0x2300
0x01FE
0x1000
Memory 0x24FE = 0x7783
Memory 0x1000 = 0x11DC

After Instruction:
W0 =
W1 =
W7 =
Data
Data

0x2300
0x01FE
0x1001
Memory 0x24FE = 0x7783
Memory 0x1000 = 0x1183

LAC

[W0+W8], A

; load ACCA with [W0+W8]
; (sign-extend and zero-backfill)

Before Instruction:
W0 =
W8 =
ACCA
Data

0x2344
0x0008
= 0x00 7877 9321
Memory 0x234C = 0xE290

After Instruction:
W0 =
W8 =
ACCA
Data

0x2344
0x0008
= 0xFF E290 0000
Memory 0x234C = 0xE290

Example 4-6:
MOV

Move with Literal Offset Instructions
[W0+0x20], W1

; move [W0+0x20] to W1

Before Instruction:
W0 = 0x1200
W1 = 0x01FE
Data Memory 0x1220 = 0xFD27

After Instruction:
W0 = 0x1200
W1 = 0xFD27
Data Memory 0x1220 = 0xFD27
MOV

W4, [W8-0x300]

; move W4 to [W8-0x300]

Before Instruction:
W4 = 0x3411
W8 = 0x2944
Data Memory 0x2644 = 0xCB98

After Instruction:
W4 = 0x3411
W8 = 0x2944
Data Memory 0x2644 = 0x3411

DS70157D-page 46

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.1.3.1

REGISTER INDIRECT ADDRESSING AND THE INSTRUCTION SET

The Addressing modes presented in Table 4-2 demonstrate the Indirect Addressing mode
capability of the 16-bit MCU and DSC devices. Due to operation encoding and functional
considerations, not every instruction which supports indirect addressing supports all modes
shown in Table 4-2. The majority of instructions which use indirect addressing support the No
Modify, Pre-Increment, Pre-Decrement, Post-Increment and Post-Decrement Addressing
modes. The MOV instructions, and several accumulator-based DSP instructions (dsPIC30F and
dsPIC33F devices only), are also capable of using the Register Offset Addressing mode.
Note:

Instructions which use register indirect addressing use the operand symbols Wd
and Ws in the summary tables of Section 3. “Instruction Set Overview”.

4.1.3.2

DSP MAC INDIRECT ADDRESSING MODES (dsPIC30F AND dsPIC33F
DEVICES)

A special class of Indirect Addressing modes is utilized by the DSP MAC instructions. As is
described later in 4.14 “DSP MAC Instructions (dsPIC30F and dsPIC33F Devices)”, the DSP
MAC class of instructions are capable of performing two fetches from memory using effective
addressing. Since DSP algorithms frequently demand a broader range of address updates, the
Addressing modes offered by the DSP MAC instructions provide greater range in the size of the
effective address update which may be made. Table 4-3 shows that both X and Y prefetches
support Post-Increment and Post-Decrement Addressing modes, with updates of 2, 4 and 6
bytes. Since DSP instructions only execute in Word mode, no provisions are made for odd sized
EA updates.
Table 4-3:

DSP MAC Indirect Addressing Modes
Addressing Mode

X Memory

Y Memory

Indirect with no modification

EA = [Wx]

EA = [Wy]

Indirect with Post-Increment by 2

EA = [Wx] + = 2

EA = [Wy] + = 2

Indirect with Post-Increment by 4

EA = [Wx] + = 4

EA = [Wy] + = 4

Indirect with Post-Increment by 6

EA = [Wx] + = 6

EA = [Wy] + = 6

Indirect with Post-Decrement by 2

EA = [Wx] – = 2

EA = [Wy] – = 2

Indirect with Post-Decrement by 4

EA = [Wx] – = 4

EA = [Wy] – = 4

Indirect with Post-Decrement by 6

EA = [Wx] – = 6

EA = [Wy] – = 6

Indirect with Register Offset

EA = [W9 + W12]

EA = [W11 + W12]

4.1.3.3

As described in 4.14 “DSP MAC Instructions (dsPIC30F and dsPIC33F
Devices)”, only W8 and W9 may be used to access X Memory, and only W10 and
W11 may be used to access Y Memory.

MODULO AND BIT-REVERSED ADDRESSING MODES (dsPIC30F AND
dsPIC33F DEVICES)

The 16-bit DSC architecture provides support for two special Register Indirect Addressing
modes, which are commonly used to implement DSP algorithms. Modulo (or circular) addressing
provides an automated means to support circular data buffers in X and/or Y memory. Modulo
buffers remove the need for software to perform address boundary checks, which can improve
the performance of certain algorithms. Similarly, bit-reversed addressing allows one to access
the elements of a buffer in a nonlinear fashion. This Addressing mode simplifies data re-ordering
for radix-2 FFT algorithms and provides a significant reduction in FFT processing time.
Both of these Addressing modes are powerful features of the dsPIC30F and dsPIC33F
architectures, which can be exploited by any instruction that uses indirect addressing. Refer to
the specific device family reference manual for details on using modulo and bit-reversed
addressing.

© 2009 Microchip Technology Inc.

DS70157D-page 47

Instruction Set
Details

Note:

4

16-bit MCU and DSC Programmer’s Reference Manual
4.1.4

Immediate Addressing

In immediate addressing, the instruction encoding contains a predefined constant operand,
which is used by the instruction. This Addressing mode may be used independently, but it is more
frequently combined with the File Register, Direct and Indirect Addressing modes. The size of
the immediate operand which may be used varies with the instruction type. Constants of size
1-bit (#lit1), 4-bit (#bit4, #lit4 and #Slit4), 5-bit (#lit5), 6-bit (#Slit6), 8-bit (#lit8), 10-bit (#lit10
and #Slit10), 14-bit (#lit14) and 16-bit (#lit16) may be used. Constants may be signed or
unsigned and the symbols #Slit4, #Slit6 and #Slit10 designate a signed constant. All other
immediate constants are unsigned. Table 4-4 shows the usage of each immediate operand in the
instruction set.
Note:
Table 4-4:

The 6-bit (#Slit6) operand is only available in dsPIC30F and dsPIC33F devices.
Immediate Operands in the Instruction Set

Operand

Instruction Usage

#lit1

PWRSAV

#bit4

BCLR, BSET, BTG, BTSC, BTSS, BTST, BTST.C, BTST.Z, BTSTS,
BTSTS.C, BTSTS.Z

#lit4

ASR, LSR, SL

#Slit4

ADD, LAC, SAC, SAC.R

#lit5

ADD, ADDC, AND, CP, CPB, IOR, MUL.SU, MUL.UU, SUB, SUBB,
SUBBR, SUBR, XOR

#Slit6(1)

SFTAC

#lit8

MOV.B, CP, CPB

#lit10

ADD, ADDC, AND, CP, CPB, IOR, RETLW, SUB, SUBB, XOR

#Slit10

MOV

#lit14

DISI, DO(1), LNK, REPEAT

#lit16

MOV

Note 1:

This operand or instruction is only available in dsPIC30F and dsPIC33F devices.

The syntax for immediate addressing requires that the number sign (#) must immediately
precede the constant operand value. The “#” symbol indicates to the assembler that the quantity
is a constant. If an out-of-range constant is used with an instruction, the assembler will generate
an error. Several examples of immediate addressing are shown in Example 4-7.

DS70157D-page 48

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
Example 4-7:

Immediate Addressing

PWRSAV #1

; Enter IDLE mode

ADD.B

; Add 0x10 to W0 (byte mode)

#0x10, W0

Before Instruction:
W0 = 0x12A9

After Instruction:
W0 = 0x12B9

XOR

W0, #1, [W1++]

; Exclusive-OR W0 and 0x1
; Store the result to [W1]
; Post-increment W1

Before Instruction:
W0 = 0xFFFF
W1 = 0x0890
Data Memory 0x0890 = 0x0032

After Instruction:
W0 = 0xFFFF
W1 = 0x0892
Data Memory 0x0890 = 0xFFFE

4.1.5

Data Addressing Mode Tree

The Data Addressing modes of the PIC24F and PIC24H families are summarized in Figure 4-1.
Figure 4-1:

Data Addressing Mode Tree (PIC24F and PIC24H)
Immediate
File Register
Data Addressing Modes

Direct
Indirect

No Modification
Pre-Increment

4

Pre-Decrement
Post-Increment

Literal Offset
Register Offset

The Data Addressing modes of the dsPIC30F and dsPIC33F are summarized in Figure 4-2.

© 2009 Microchip Technology Inc.

DS70157D-page 49

Instruction Set
Details

Post-Decrement

16-bit MCU and DSC Programmer’s Reference Manual
Figure 4-2:

Data Addressing Mode Tree (dsPIC30F and dsPIC33F)
Immediate
File Register
Basic
Direct
Indirect

No Modification
Pre-Increment
Pre-Decrement
Post-Increment
Post-Decrement
Literal Offset

Data Addressing Modes

Register Offset
Direct

DSP MAC

No Modification
Post-Increment (2, 4 and 6)
Indirect

Post-Decrement (2, 4 and 6)
Register Offset

DS70157D-page 50

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.2

PROGRAM ADDRESSING MODES
The 16-bit MCU and DSC devices have a 23-bit Program Counter (PC). The PC addresses the
24-bit wide program memory to fetch instructions for execution, and it may be loaded in several
ways. For byte compatibility with the table read and table write instructions, each instruction word
consumes two locations in program memory. This means that during serial execution, the PC is
loaded with PC + 2.
Several methods may be used to modify the PC in a non-sequential manner, and both absolute
and relative changes may be made to the PC. The change to the PC may be from an immediate
value encoded in the instruction, or a dynamic value contained in a working register. In dsPIC30F
and dsPIC33F devices, when DO looping is active, the PC is loaded with the address stored in
the DOSTART register, after the instruction at the DOEND address is executed. For exception
handling, the PC is loaded with the address of the exception handler, which is stored in the
interrupt vector table. When required, the software stack is used to return scope to the foreground
process from where the change in program flow occurred.
Table 4-5 summarizes the instructions which modify the PC. When performing function calls, it is
recommended that RCALL be used instead of CALL, since RCALL only consumes 1 word of
program memory.

Table 4-5:

Methods of Modifying Program Flow

Condition/Instruction

PC Modification

Software Stack Usage

PC = PC + 2

None

BRA Expr(1)
(Branch Unconditionally)

PC = PC + 2*Slit16

None

BRA Condition, Expr(1)
(Branch Conditionally)

PC = PC + 2 (condition false)
PC = PC + 2 * Slit16 (condition true)

None

CALL Expr(1)
(Call Subroutine)

PC = lit23

PC + 4 is PUSHed on the stack(2)

CALL Wn
(Call Subroutine Indirect)

PC = Wn

PC + 2 is PUSHed on the stack(2)

GOTO Expr(1)
(Unconditional Jump)

PC = lit23

None

GOTO Wn
(Unconditional Indirect Jump)

PC = Wn

None

RCALL Expr(1)
(Relative Call)

PC = PC + 2 * Slit16

PC + 2 is PUSHed on the stack(2)

RCALL Wn
(Computed Relative Call)

PC = PC + 2 * Wn

PC + 2 is PUSHed on the stack(2)

Exception Handling

PC = address of the exception handler PC + 2 is PUSHed on the stack(3)
(read from vector table)

PC = Target REPEAT instruction
(REPEAT Looping)

PC not modified (if REPEAT active)

None

PC = DOEND address(4)
(DO Looping)

PC = DOSTART (if DO active)

None

Note 1:
2:
3:
4:

For BRA, CALL and GOTO, the Expr may be a label, absolute address or expression, which is resolved by
the linker to a 16-bit or 23-bit value (Slit16 or lit23). See Section 5. “Instruction Descriptions” for details.
After CALL or RCALL is executed, RETURN or RETLW will POP the Top-of-Stack (TOS) back into the PC.
After an exception is processed, RETFIE will POP the Top-of-Stack (TOS) back into the PC.
This condition/instruction is only available in dsPIC30F and dsPIC33F devices.

© 2009 Microchip Technology Inc.

DS70157D-page 51

4
Instruction Set
Details

Sequential Execution

16-bit MCU and DSC Programmer’s Reference Manual
4.3

INSTRUCTION STALLS
In order to maximize the data space EA calculation and operand fetch time, the X data space
read and write accesses are partially pipelined. A consequence of this pipelining is that address
register data dependencies may arise between successive read and write operations using
common registers.
‘Read After Write’ (RAW) dependencies occur across instruction boundaries and are detected by
the hardware. An example of a RAW dependency would be a write operation that modifies W5,
followed by a read operation that uses W5 as an Address Pointer. The contents of W5 will not be
valid for the read operation until the earlier write completes. This problem is resolved by stalling
the instruction execution for one instruction cycle, which allows the write to complete before the
next read is started.

4.3.1

RAW Dependency Detection

During the instruction pre-decode, the core determines if any address register dependency is
imminent across an instruction boundary. The stall detection logic compares the W register
(if any) used for the destination EA of the instruction currently being executed with the W register
to be used by the source EA (if any) of the prefetched instruction. When a match between the
destination and source registers is identified, a set of rules are applied to decide whether or not
to stall the instruction by one cycle. Table 4-6 lists various RAW conditions which cause an
instruction execution stall.
Table 4-6:

Raw Dependency Rules (Detection by Hardware)

Destination
Address Mode Using Wn

Source Address Mode
Using Wn

Examples(2)
(Wn = W2)

Stall
Required?

Direct

Direct

No Stall

ADD.W
MOV.W

W0, W1, W2
W2, W3

Indirect

Direct

No Stall

ADD.W
MOV.W

W0, W1, [W2]
W2, W3

Indirect

Indirect

No Stall

ADD.W
MOV.W

W0, W1, [W2]
[W2], W3

Indirect

Indirect with pre/post-modification

No Stall

ADD.W
MOV.W

W0, W1, [W2]
[W2++], W3

No Stall

ADD.W
MOV.W

W0, W1, [W2++]
W2, W3

Indirect with pre/post-modification Direct
Direct

Indirect

Stall(1)

ADD.W
MOV.W

W0, W1, W2
[W2], W3

Direct

Indirect with pre/post-modification

Stall(1)

ADD.W
MOV.W

W0, W1, W2
[W2++], W3

Indirect

Indirect

Stall(1)

ADD.W
MOV.W

W0, W1, [W2](2)
[W2], W3(2)

Indirect

Indirect with pre/post-modification

Stall(1)

ADD.W W0, W1, [W2](2)
MOV.W [W2++], W3(2)

Indirect with pre/post-modification Indirect

Stall(1)

ADD.W
MOV.W

W0, W1, [W2++]
[W2], W3

Indirect with pre/post-modification Indirect with pre/post-modification

Stall(1)

ADD.W
MOV.W

W0, W1, [W2++]
[W2++], W3

Note 1:
2:

When stalls are detected, one cycle is added to the instruction execution time.
For these examples, the contents of W2 = the mapped address of W2 (0x0004).

DS70157D-page 52

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.3.2

Instruction Stalls and Exceptions

In order to maintain deterministic operation, instruction stalls are allowed to happen, even if they
occur immediately prior to exception processing.

4.3.3

Instruction Stalls and Instructions that Change Program Flow

CALL and RCALL write to the stack using W15 and may, therefore, be subject to an instruction
stall if the source read of the subsequent instruction uses W15.
GOTO, RETFIE and RETURN instructions are never subject to an instruction stall because they
do not perform write operations to the working registers.

4.3.4

Instruction Stalls and DO/REPEAT Loops

Instructions operating in a DO or REPEAT loop are subject to instruction stalls, just like any other
instruction. Stalls may occur on loop entry, loop exit and also during loop processing.
Note:

4.3.5

DO loops are only available in dsPIC30F and dsPIC33F devices.

Instruction Stalls and PSV

Instructions operating in PSV address space are subject to instruction stalls, just like any other
instruction. Should a data dependency be detected in the instruction immediately following the
PSV data access, the second cycle of the instruction will initiate a stall. Should a data
dependency be detected in the instruction immediately before the PSV data access, the last
cycle of the previous instruction will initiate a stall.
Note:

Refer to the specific device family reference manual for more detailed information
about RAW instruction stalls.

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

DS70157D-page 53

16-bit MCU and DSC Programmer’s Reference Manual
4.4

BYTE OPERATIONS
Since the data memory is byte addressable, most of the base instructions may operate in either
Byte mode or Word mode. When these instructions operate in Byte mode, the following rules
apply:
• All direct working register references use the Least Significant Byte of the 16-bit working
register and leave the Most Significant Byte (MSB) unchanged
• All indirect working register references use the data byte specified by the 16-bit address
stored in the working register
• All file register references use the data byte specified by the byte address
• The STATUS Register is updated to reflect the result of the byte operation
It should be noted that data addresses are always represented as byte addresses. Additionally,
the native data format is little-endian, which means that words are stored with the Least
Significant Byte at the lower address, and the Most Significant Byte at the adjacent, higher
address (as shown in Figure 4-3). Example 4-8 shows sample byte move operations and
Example 4-9 shows sample byte math operations.
Note:

Instructions that operate in Byte mode must use the “.b” or “.B” instruction
extension to specify a byte instruction. For example, the following two instructions
are valid forms of a byte clear operation:
CLR.b
CLR.B

Example 4-8:
MOV.B

W0
W0

Sample Byte Move Operations
#0x30, W0

; move the literal byte 0x30 to W0

Before Instruction:
W0 = 0x5555

After Instruction:
W0 = 0x5530
MOV.B

0x1000, W0

; move the byte at 0x1000 to W0

Before Instruction:
W0 = 0x5555
Data Memory 0x1000 = 0x1234

After Instruction:
W0 = 0x5534
Data Memory 0x1000 = 0x1234
MOV.B

W0, 0x1001

; byte move W0 to address 0x1001

Before Instruction:
W0 = 0x1234
Data Memory 0x1000 = 0x5555

After Instruction:
W0 = 0x1234
Data Memory 0x1000 = 0x3455
MOV.B

W0, [W1++]

; byte move W0 to [W1], then post-inc W1

Before Instruction:
W0 = 0x1234
W1 = 0x1001
Data Memory 0x1000 = 0x5555

After Instruction:
W0 = 0x1234
W1 = 0x1002
Data Memory 0x1000 = 0x3455

DS70157D-page 54

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
Example 4-9:
CLR.B

Sample Byte Math Operations
[W6--]

; byte clear [W6], then post-dec W6

Before Instruction:
W6 = 0x1001
Data Memory 0x1000 = 0x5555

After Instruction:
W6 = 0x1000
Data Memory 0x1000 = 0x0055
SUB.B

W0, #0x10, W1

; byte subtract literal 0x10 from W0
; and store to W1

Before Instruction:
W0 = 0x1234
W1 = 0xFFFF

After Instruction:
W0 = 0x1234
W1 = 0xFF24
ADD.B

W0, W1, [W2++]

; byte add W0 and W1, store to [W2]
; and post-inc W2

Before Instruction:
W0 =
W1 =
W2 =
Data

0x1234
0x5678
0x1000
Memory 0x1000 = 0x5555

After Instruction:
W0 =
W1 =
W2 =
Data

0x1234
0x5678
0x1001
Memory 0x1000 = 0x55AC

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

DS70157D-page 55

16-bit MCU and DSC Programmer’s Reference Manual
4.5

WORD MOVE OPERATIONS
Even though the data space is byte addressable, all move operations made in Word mode must
be word-aligned. This means that for all source and destination operands, the Least Significant
address bit must be ‘0’. If a word move is made to or from an odd address, an address error
exception is generated. Likewise, all double words must be word-aligned. Figure 4-3 shows how
bytes and words may be aligned in data memory. Example 4-10 contains several legal word
move operations.
When an exception is generated due to a misaligned access, the exception is taken after the
instruction executes. If the illegal access occurs from a data read, the operation will be allowed
to complete, but the Least Significant bit of the source address will be cleared to force word
alignment. If the illegal access occurs during a data write, the write will be inhibited. Example 4-11
contains several illegal word move operations.
Figure 4-3:

Data Alignment in Memory

0x1001

b0

0x1000

0x1003

b1

0x1005

b3

b2

0x1004

0x1007

b5

b4

0x1006

0x1009

b7

b6

0x1008

b8

0x100A

0x100B

0x1002

Legend:
b0 – byte stored at 0x1000
b1 – byte stored at 0x1003
b3:b2 – word stored at 0x1005:1004 (b2 is LSB)
b7:b4 – double word stored at 0x1009:0x1006 (b4 is LSB)
b8 – byte stored at 0x100A
Note:

Instructions that operate in Word mode are not required to use an instruction
extension. However, they may be specified with an optional “.w” or “.W” extension,
if desired. For example, the following instructions are valid forms of a word clear
operation:
CLR
CLR.w
CLR.W

DS70157D-page 56

W0
W0
W0

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
Example 4-10:
MOV

Legal Word Move Operations

#0x30, W0

; move the literal word 0x30 to W0

Before Instruction:
W0 = 0x5555

After Instruction:
W0 = 0x0030
MOV

0x1000, W0

; move the word at 0x1000 to W0

Before Instruction:
W0 = 0x5555
Data Memory 0x1000 = 0x1234

After Instruction:
W0 = 0x1234
Data Memory 0x1000 = 0x1234
MOV

[W0], [W1++]

; word move [W0] to [W1],
; then post-inc W1

Before Instruction:
W0 =
W1 =
Data
Data

0x1234
0x1000
Memory 0x1000 = 0x5555
Memory 0x1234 = 0xAAAA

After Instruction:
W0 =
W1 =
Data
Data

0x1234
0x1002
Memory 0x1000 = 0xAAAA
Memory 0x1234 = 0xAAAA

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

DS70157D-page 57

16-bit MCU and DSC Programmer’s Reference Manual
Example 4-11:
MOV

Illegal Word Move Operations

0x1001, W0

; move the word at 0x1001 to W0

Before Instruction:
W0 = 0x5555
Data Memory 0x1000 = 0x1234
Data Memory 0x1002 = 0x5678

After Instruction:
W0 = 0x1234
Data Memory 0x1000 = 0x1234
Data Memory 0x1002 = 0x5678

ADDRESS ERROR TRAP GENERATED
(source address is misaligned, so MOV is performed)
MOV

W0, 0x1001

; move W0 to the word at 0x1001

Before Instruction:
W0 = 0x1234
Data Memory 0x1000 = 0x5555
Data Memory 0x1002 = 0x6666

After Instruction:
W0 = 0x1234
Data Memory 0x1000 = 0x5555
Data Memory 0x1002 = 0x6666

ADDRESS ERROR TRAP GENERATED
(destination address is misaligned, so MOV is not performed)
MOV

[W0], [W1++]

; word move [W0] to [W1],
; then post-inc W1

Before Instruction:
W0 =
W1 =
Data
Data
Data

0x1235
0x1000
Memory 0x1000 = 0x1234
Memory 0x1234 = 0xAAAA
Memory 0x1236 = 0xBBBB

After Instruction:
W0 =
W1 =
Data
Data
Data

0x1235
0x1002
Memory 0x1000 = 0xAAAA
Memory 0x1234 = 0xAAAA
Memory 0x1236 = 0xBBBB

ADDRESS ERROR TRAP GENERATED
(source address is misaligned, so MOV is performed)

DS70157D-page 58

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.6

USING 10-BIT LITERAL OPERANDS
Several instructions that support Byte and Word mode have 10-bit operands. For byte
instructions, a 10-bit literal is too large to use. So when 10-bit literals are used in Byte mode, the
range of the operand must be reduced to 8 bits or the assembler will generate an error. Table 4-7
shows that the range of a 10-bit literal is 0:1023 in Word mode and 0:255 in Byte mode.
Instructions which employ 10-bit literals in Byte and Word mode are: ADD, ADDC, AND, IOR,
RETLW, SUB, SUBB and XOR. Example 4-12 shows how positive and negative literals are used in
Byte mode for the ADD instruction.
Table 4-7:

10-bit Literal Coding

Literal Value

Word Mode
kk kkkk kkkk

Byte Mode
kkkk kkkk

0

00 0000 0000

0000 0000

1

00 0000 0001

0000 0001

2

00 0000 0010

0000 0010

127

00 0111 1111

0111 1111

128

00 1000 0000

1000 0000

255

00 1111 1111

1111 1111

256

01 0000 0000

N/A

512

10 0000 0000

N/A

1023

11 1111 1111

N/A

Example 4-12:
ADD.B
ADD.B
ADD.B
ADD.B
ADD.B
ADD.B
ADD.B

Note:

;
;
;
;
;
;
;

add 128 (or -128) to W0
ERROR... Illegal syntax for byte mode
add 255 (or -1) to W0
ERROR... Illegal syntax for byte mode
add 15 to W0
add 127 to W0
ERROR... Illegal syntax for byte mode

Using a literal value greater than 127 in Byte mode is functionally identical to using
the equivalent negative two’s complement value, since the Most Significant bit of the
byte is set. When operating in Byte mode, the Assembler will accept either a positive
or negative literal value (i.e., #-10).

DS70157D-page 59

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

Using 10-bit Literals for Byte Operands

#0x80, W0
#0x380, W0
#0xFF, W0
#0x3FF, W0
#0xF, W0
#0x7F, W0
#0x100, W0

16-bit MCU and DSC Programmer’s Reference Manual
4.7

SOFTWARE STACK POINTER AND FRAME POINTER
4.7.1

Software Stack Pointer

The 16-bit MCU and DSC devices feature a software stack which facilitates function calls and
exception handling. W15 is the default Stack Pointer (SP) and after any Reset, it is initialized to
0x0800. This ensures that the SP will point to valid RAM and permits stack availability for
exceptions, which may occur before the SP is set by the user software. The user may reprogram
the SP during initialization to any location within data space.
The SP always points to the first available free word (Top-of-Stack) and fills the software stack,
working from lower addresses towards higher addresses. It pre-decrements for a stack POP
(read) and post-increments for a stack PUSH (write).
The software stack is manipulated using the PUSH and POP instructions. The PUSH and POP
instructions are the equivalent of a MOV instruction, with W15 used as the destination pointer. For
example, the contents of W0 can be PUSHed onto the Top-of-Stack (TOS) by:
PUSH W0

This syntax is equivalent to:
MOV W0,[W15++]

The contents of the TOS can be returned to W0 by:
POP W0

This syntax is equivalent to:
MOV [--W15],W0

During any CALL instruction, the PC is PUSHed onto the stack, such that when the subroutine
completes execution, program flow may resume from the correct location. When the PC is
PUSHed onto the stack, PC<15:0> is PUSHed onto the first available stack word, then
PC<22:16> is PUSHed. When PC<22:16> is PUSHed, the Most Significant 7 bits of the PC are
zero-extended before the PUSH is made, as shown in Figure 4-4. During exception processing,
the Most Significant 7 bits of the PC are concatenated with the lower byte of the STATUS
register (SRL) and IPL<3>, CORCON<3>. This allows the primary STATUS register contents
and CPU Interrupt Priority Level to be automatically preserved during interrupts.
Note:

In order to protect against misaligned stack accesses, W15<0> is always clear.

Figure 4-4:

Stack Operation for CALL Instruction

0x0000

Stack Grows Towards
Higher Address

15

0

PC<15:0>
0x0

W15 (before CALL)

PC<22:16>
Top-of-Stack

W15 (after CALL)

0xFFFE
Note:

DS70157D-page 60

For exceptions, the upper nine bits of the second PUSHed word contains
the SRL and IPL<3>.

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.7.1.1

STACK POINTER EXAMPLE

Figure 4-5 through Figure 4-8 show how the software stack is modified for the code snippet
shown in Example 4-13. Figure 4-5 shows the software stack before the first PUSH has executed.
Note that the SP has the initialized value of 0x0800. Furthermore, the example loads 0x5A5A
and 0x3636 to W0 and W1, respectively. The stack is PUSHed for the first time in Figure 4-6 and
the value contained in W0 is copied to TOS. W15 is automatically updated to point to the next
available stack location, and the new TOS is 0x0802. In Figure 4-7, the contents of W1 are
PUSHed onto the stack, and the new TOS becomes 0x0804. In Figure 4-8, the stack is POPed,
which copies the last PUSHed value (W1) to W3. The SP is decremented during the POP
operation, and at the end of the example, the final TOS is 0x0802.
Example 4-13:
MOV
MOV
PUSH
PUSH
POP

Figure 4-5:

Stack Pointer Usage

#0x5A5A, W0
#0x3636, W1
W0
W1
W3

;
;
;
;
;

Load W0
Load W1
Push W0
Push W1
Pop TOS

with 0x5A5A
with 0x3636
to TOS (see Figure 4-5)
to TOS (see Figure 4-7)
to W3 (see Figure 4-8)

Stack Pointer Before the First PUSH
0x0000
0x0800



W15 (SP)

0xFFFE
W0 = 0x5A5A
W1 = 0x3636
W15 = 0x0800

Figure 4-6:

Stack Pointer After “PUSH W0” Instruction

4

0x0000
5A5A


W15 (SP)

Instruction Set
Details

0x0800
0x0802

0xFFFE
W0 = 0x5A5A
W1 = 0x3636
W15 = 0x0802

© 2009 Microchip Technology Inc.

DS70157D-page 61

16-bit MCU and DSC Programmer’s Reference Manual
Figure 4-7:

Stack Pointer After “PUSH W1” Instruction
0x0000
0x0800
0x0802
0x0804

5A5A
3636


W15 (SP)

0xFFFE
W0 = 0x5A5A
W1 = 0x3636
W15 = 0x0804

Figure 4-8:

Stack Pointer After “POP W3” Instruction
0x0000
0x0800
0x0802
0x0804

5A5A


W15 (SP)

0xFFFE
W0 = 0x5A5A
W1 = 0x3636
W3 = 0x3636
W15 = 0x0802
Note: The contents of 0x802, the new TOS, remain unchanged (0x3636).

4.7.2

Software Stack Frame Pointer

A Stack Frame is a user-defined section of memory residing in the software stack. It is used to
allocate memory for temporary variables which a function uses, and one Stack Frame may be
created for each function. W14 is the default Stack Frame Pointer (FP) and it is initialized to
0x0000 on any Reset. If the Stack Frame Pointer is not used, W14 may be used like any other
working register.
The link (LNK) and unlink (ULNK) instructions provide Stack Frame functionality. The LNK
instruction is used to create a Stack Frame. It is used during a call sequence to adjust the SP,
such that the stack may be used to store temporary variables utilized by the called function. After
the function completes execution, the ULNK instruction is used to remove the Stack Frame
created by the LNK instruction. The LNK and ULNK instructions must always be used together to
avoid stack overflow.

DS70157D-page 62

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.7.2.1

STACK FRAME POINTER EXAMPLE

Figure 4-9 through Figure 4-11 show how a Stack Frame is created and removed for the code
snippet shown in Example 4-14. This example demonstrates how a Stack Frame operates and
is not indicative of the code generated by the compiler. Figure 4-9 shows the stack condition at
the beginning of the example, before any registers are PUSHed to the stack. Here, W15 points
to the first free stack location (TOS) and W14 points to a portion of stack memory allocated for
the routine that is currently executing.
Before calling the function “COMPUTE”, the parameters of the function (W0, W1 and W2) are
PUSHed on the stack. After the “CALL COMPUTE” instruction is executed, the PC changes to the
address of “COMPUTE” and the return address of the function “TASKA” is placed on the stack
(Figure 4-10). Function “COMPUTE” then uses the “LNK #4” instruction to PUSH the calling
routine’s Frame Pointer value onto the stack and the new Frame Pointer will be set to point to the
current Stack Pointer. Then, the literal 4 is added to the Stack Pointer address in W15, which
reserves memory for two words of temporary data (Figure 4-11).
Inside the function “COMPUTE”, the FP is used to access the function parameters and temporary
(local) variables. [W14 + n] will access the temporary variables used by the routine and [W14 – n]
is used to access the parameters. At the end of the function, the ULNK instruction is used to copy
the Frame Pointer address to the Stack Pointer and then POP the calling subroutine’s Frame
Pointer back to the W14 register. The ULNK instruction returns the stack back to the state shown
in Figure 4-10.
A RETURN instruction will return to the code that called the subroutine. The calling code is
responsible for removing the parameters from the stack. The RETURN and POP instructions
restore the stack to the state shown in Figure 4-9.
Example 4-14:
TASKA:
...
PUSH
PUSH
PUSH
CALL
POP
POP
POP
...

W0
W1
W2
COMPUTE
W2
W1
W0

;
;
;
;
;
;
;

Push parameter 1
Push parameter 2
Push parameter 3
Call COMPUTE function
Pop parameter 3
Pop parameter 2
Pop parameter 1

4
; Stack FP, allocate 4 bytes for local variables
; Free allocated memory, restore original FP
; Return to TASKA

Stack at the Beginning of Example 4-14
0x0000
0x0800
Frame
of
TASKA

W14 (FP)



W15 (SP)

0xFFFE

© 2009 Microchip Technology Inc.

DS70157D-page 63

Instruction Set
Details

COMPUTE:
LNK
#4
...
ULNK
RETURN

Figure 4-9:

Frame Pointer Usage

16-bit MCU and DSC Programmer’s Reference Manual
Figure 4-10:

Stack After “CALLCOMPUTE” Executes
0x0000
0x0800
Frame
of
TASKA
Parameter 1
Parameter 2
Parameter 3
PC<15:0>
0:PC<22:16>


W14 (FP)

W15 (SP)

0xFFFE

Figure 4-11:

Stack After “LNK #4” Executes
0x0000
0x0800
Frame
of
TASKA
Parameter 1
Parameter 2
Parameter 3
PC<15:0>
0:PC<22:16>
FP of TASKA
Temp Word 1
Temp Word 2


W14 (FP)
W15 (SP)

0xFFFE

4.7.3

Stack Pointer Overflow

There is a stack limit register (SPLIM) associated with the Stack Pointer that is reset to 0x0000.
SPLIM is a 16-bit register, but SPLIM<0> is fixed to ‘0’, because all stack operations must be
word-aligned.
The stack overflow check will not be enabled until a word write to SPLIM occurs, after which time
it can only be disabled by a device Reset. All effective addresses generated using W15 as a
source or destination are compared against the value in SPLIM. Should the effective address be
greater than the contents of SPLIM, then a stack error trap is generated.
If stack overflow checking has been enabled, a stack error trap will also occur if the W15 effective
address calculation wraps over the end of data space (0xFFFF).
Refer to the specific device family reference manual for more information on the stack error trap.

4.7.4

Stack Pointer Underflow

The stack is initialized to 0x0800 during Reset. A stack error trap will be initiated should the Stack
Pointer address ever be less than 0x0800.
Note:

DS70157D-page 64

Locations in data space between 0x0000 and 0x07FF are, in general, reserved for
core and peripheral Special Function Registers (SFRs).

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.8

Conditional Branch Instructions
Conditional branch instructions are used to direct program flow, based on the contents of the
STATUS register. These instructions are generally used in conjunction with a Compare class
instruction, but they may be employed effectively after any operation that modifies the STATUS
register.
The compare instructions CP,
CP0 and CPB, perform a subtract operation
(minuend – subtrahend), but do not actually store the result of the subtraction. Instead, compare
instructions just update the flags in the STATUS register, such that an ensuing conditional branch
instruction may change program flow by testing the contents of the updated STATUS register. If
the result of the STATUS register test is true, the branch is taken. If the result of the STATUS
register test is false, the branch is not taken.
The conditional branch instructions supported by the dsPIC30F and dsPIC33F devices are
shown in Table 4-8. This table identifies the condition in the STATUS register which must be true
for the branch to be taken. In some cases, just a single bit is tested (as in BRA C), while in other
cases, a complex logic operation is performed (as in BRA GT). For dsPIC30F and dsPIC33F
devices, it is worth noting that both signed and unsigned conditional tests are supported, and that
support is provided for DSP algorithms with the OA, OB, SA and SB condition mnemonics.
Table 4-8:

Conditional Branch Instructions

Condition
Mnemonic(1)
C

Description

Status Test

Carry (not Borrow)

C

GE

Signed greater than or equal

(N&&OV) || (N&&OV)

GEU(2)

Unsigned greater than or equal

C

GT

Signed greater than

(Z&&N&&OV) || (Z&&N&&OV)

GTU

Unsigned greater than

C&&Z

LE

Signed less than or equal

Z || (N&&OV) || (N&&OV)

LEU

Unsigned less than or equal

C || Z

LT

Signed less than

(N&&OV) || (N&&OV)

LTU(3)

Unsigned less than

C

N

Negative

N

NC

Not Carry (Borrow)

C

NN

Not Negative

N

NOV

Not Overflow

OV

Not Zero

Z

OA(4)

Accumulator A overflow

OA

OB(4)

Accumulator B overflow

OB

OV

Overflow

OV

SA(4)

Accumulator A saturate

SA

SB(4)

Accumulator B saturate

SB

Zero

Z

Z
Note 1:
2:
3:
4:
Note:

© 2009 Microchip Technology Inc.

Instruction Set
Details

NZ

4

Instructions are of the form: BRA mnemonic, Expr.
GEU is identical to C and will reverse assemble to BRA C, Expr.
LTU is identical to NC and will reverse assemble to BRA NC, Expr.
This condition is only available in dsPIC30F and dsPIC33F devices.
The “Compare and Skip” instructions (CPBEQ, CPBGT, CPBLT, CPBNE, CPSEQ,
CPSGT, CPSLT and CPSNE) do not modify the STATUS register.

DS70157D-page 65

16-bit MCU and DSC Programmer’s Reference Manual
4.9

Z STATUS BIT
The Z Status bit is a special zero Status bit that is useful for extended precision arithmetic. The
Z bit functions like a normal Z flag for all instructions, except those that use the carry/borrow input
(ADDC, CPB, SUBB and SUBBR). For the ADDC, CPB, SUBB and SUBBR instructions, the Z bit can
only be cleared and never set. If the result of one of these instructions is non-zero, the Z bit will
be cleared and will remain cleared, regardless of the result of subsequent ADDC, CPB, SUBB or
SUBBR operations. This allows the Z bit to be used for performing a simple zero check on the
result of a series of extended precision operations.
A sequence of instructions working on multi-precision data (starting with an instruction with no
carry/borrow input), will automatically logically AND the successive results of the zero test. All
results must be zero for the Z flag to remain set at the end of the sequence of operations. If the
result of the ADDC, CPB, SUBB or SUBBR instruction is non-zero, the Z bit will be cleared and
remain cleared for all subsequent ADDC, CPB, SUBB or SUBBR instructions. Example 4-15 shows
how the Z bit operates for a 32-bit addition. It shows how the Z bit is affected for a 32-bit addition
implemented with an ADD/ADDC instruction sequence. The first example generates a zero result
for only the most significant word, and the second example generates a zero result for both the
least significant word and most significant word.
Example 4-15:

‘Z’ Status bit Operation for 32-Bit Addition

; Add two doubles (W0:W1 and W2:W3)
; Store the result in W5:W4
ADD
W0, W2, W4
; Add LSWord and store to W4
ADDC
W1, W3, W5
; Add MSWord and store to W5

Before 32-bit Addition (zero result for the most significant word):
W0
W1
W2
W3
W4
W5
SR

=
=
=
=
=
=
=

0x2342
0xFFF0
0x39AA
0x0010
0x0000
0x0000
0x0000

After 32-bit Addition:
W0
W1
W2
W3
W4
W5
SR

=
=
=
=
=
=
=

0x2342
0xFFF0
0x39AA
0x0010
0x5CEC
0x0000
0x0201 (DC,C=1)

Before 32-bit Addition (zero result for the least significant word and most significant word):
W0
W1
W2
W3
W4
W5
SR

=
=
=
=
=
=
=

0xB76E
0xFB7B
0x4892
0x0484
0x0000
0x0000
0x0000

After 32-bit Addition:
W0
W1
W2
W3
W4
W5
SR

DS70157D-page 66

=
=
=
=
=
=
=

0xB76E
0xFB7B
0x4892
0x0485
0x0000
0x0000
0x0103 (DC,Z,C=1)

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.10

ASSIGNED WORKING REGISTER USAGE
The 16 working registers of the 16-bit MCU and DSC devices provide a large register set for
efficient code generation and algorithm implementation. In an effort to maintain an instruction set
that provides advanced capability, a stable run-time environment and backwards compatibility
with earlier Microchip processor cores, some working registers have a pre-assigned usage.
Table 4-9 summarizes these working register assignments. For the dsPIC30F and dsPIC33F,
additional details are provided in subsections 4.10.1 “Implied DSP Operands (dsPIC30F and
dsPIC33F Devices)” through 4.10.3 “PIC® Microcontroller Compatibility”.
Table 4-9:

Special Working Register Assignments

Register

Special Assignment

W0

Default WREG, Divide Quotient

W1

Divide Remainder

W2

“MUL f” Product least significant word

W3

“MUL f” Product most significant word

W4

MAC Operand(1)

W5

MAC Operand(1)

W6

MAC Operand(1)

W7

MAC Operand(1)

W8

MAC Prefetch Address (X Memory)(1)

W9

MAC Prefetch Address (X Memory)(1)

W10

MAC Prefetch Address (Y Memory)(1)

W11

MAC Prefetch Address (Y Memory)(1)

W12

MAC Prefetch Offset(1)

W13

MAC Write Back Destination(1)

W14

Frame Pointer

W15

Stack Pointer

Note 1:

4.10.1

This assignment is only applicable in dsPIC30F and dsPIC33F devices.

Implied DSP Operands (dsPIC30F and dsPIC33F Devices)

•
•
•
•

W4-W7 are used for arithmetic operands
W8-W11 are used for prefetch addresses (pointers)
W12 is used for the prefetch register offset index
W13 is used for the accumulator Write Back destination

These restrictions only apply to the DSP MAC class of instructions, which utilize working
registers and have prefetch ability (described in 4.15 “DSP Accumulator Instructions
(dsPIC30F and dsPIC33F Devices)”). The affected instructions are CLR, ED, EDAC, MAC,
MOVSAC, MPY, MPY.N and MSC.
The DSP Accumulator class of instructions (described in 4.15 “DSP Accumulator Instructions
(dsPIC30F and dsPIC33F Devices)”) are not required to follow the working register assignments
in Table 4-9 and may freely use any working register when required.

© 2009 Microchip Technology Inc.

DS70157D-page 67

4
Instruction Set
Details

To assist instruction encoding and maintain uniformity among the DSP class of instructions,
some working registers have pre-assigned functionality. For all DSP instructions which have
prefetch ability, the following 10 register assignments must be adhered to:

16-bit MCU and DSC Programmer’s Reference Manual
4.10.2

Implied Frame and Stack Pointer

To accommodate software stack usage, W14 is the implied Frame Pointer (used by the LNK and
ULNK instructions) and W15 is the implied Stack Pointer (used by the CALL, LNK, POP, PUSH,
RCALL, RETFIE, RETLW, RETURN, TRAP and ULNK instructions). Even though W14 and W15
have this implied usage, they may still be used as generic operands in any instruction, with the
exceptions outlined in 4.10.1 “Implied DSP Operands (dsPIC30F and dsPIC33F Devices)”. If
W14 and W15 must be used for other purposes (it is strongly advised that they remain reserved
for the Frame and Stack Pointer), extreme care must be taken such that the run-time
environment is not corrupted.

4.10.3

PIC® Microcontroller Compatibility

4.10.3.1

DEFAULT WORKING REGISTER WREG

To ease the migration path for users of the Microchip 8-bit PIC MCU families, the 16-bit MCU and
DSC devices have matched the functionality of the PIC MCU instruction sets as closely as
possible. One major difference between the 16-bit MCU and DSC and the 8-bit PIC MCU
processors is the number of working registers provided. The 8-bit PIC MCU families only provide
one 8-bit working register, while the 16-bit MCU and DSC families provide sixteen, 16-bit working
registers. To accommodate for the one working register of the 8-bit PIC MCU, the 16-bit MCU
and DSC device instruction set has designated one working register to be the default working
register for all legacy file register instructions. The default working register is set to W0, and it is
used by all instructions which use file register addressing.
Additionally, the syntax used by the 16-bit MCU and DSC device assembler to specify the default
working register is similar to that used by the 8-bit PIC MCU assembler. As shown in the detailed
instruction descriptions in Section 5. “Instruction Descriptions”, “WREG” must be used to
specify the default working register. Example 4-16 shows several instructions which use WREG.
Example 4-16:
ADD
ASR
CLR.B
DEC
MOV
SETM
XOR

4.10.3.2

Using the Default Working Register WREG

RAM100
RAM100, WREG
WREG
RAM100, WREG
WREG, RAM100
WREG
RAM100

;
;
;
;
;
;
;

add RAM100 and WREG, store in RAM100
shift RAM100 right, store in WREG
clear the WREG LS Byte
decrement RAM100, store in WREG
move WREG to RAM100
set all bits in the WREG
XOR RAM100 and WREG, store in RAM100

PRODH:PRODL REGISTER PAIR

Another significant difference between the Microchip 8-bit PIC MCU and 16-bit MCU and DSC
architectures is the multiplier. Some PIC MCU families support an 8-bit x 8-bit multiplier, which
places the multiply product in the PRODH:PRODL register pair. The 16-bit MCU and DSC
devices have a 17-bit x 17-bit multiplier, which may place the result into any two successive
working registers (starting with an even register), or an accumulator.
Despite this architectural difference, the 16-bit MCU and DSC devices still support the legacy file
register multiply instruction (MULWF) with the “MUL{.B} f” instruction (described on page 5-255).
Supporting the legacy MULWF instruction has been accomplished by mapping the
PRODH:PRODL registers to the working register pair W3:W2. This means that when “MUL{.B}
f” is executed in Word mode, the multiply generates a 32-bit product which is stored in W3:W2,
where W3 has the most significant word of the product and W2 has the least significant word of
the product. When “MUL{.B} f” is executed in Byte mode, the 16-bit product is stored in W2,
and W3 is unaffected. Examples of this instruction are shown in Example 4-17.

DS70157D-page 68

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
Example 4-17:
MUL.B

Unsigned f and WREG Multiply (Legacy MULWF Instruction)

0x100

; (0x100)*WREG (byte mode), store to W2

Before Instruction:
W0 (WREG) = 0x7705
W2 = 0x1235
W3 = 0x1000
Data Memory 0x0100 = 0x1255

After Instruction:
W0 (WREG) = 0x7705
W2 = 0x01A9
W3 = 0x1000
Data Memory 0x0100 = 0x1255
MUL

0x100

; (0x100)*WREG (word mode), store to W3:W2

Before Instruction:
W0 (WREG) = 0x7705
W2 = 0x1235
W3 = 0x1000
Data Memory 0x0100 = 0x1255

After Instruction:
W0 (WREG) = 0x7705
W2 = 0xDEA9
W3 = 0x0885
Data Memory 0x0100 = 0x1255

4.10.3.3

MOVING DATA WITH WREG

The “MOV{.B} f {,WREG}” instruction (described on page 5-145) and “MOV{.B} WREG, f”
instruction (described on page 5-146) allow for byte or word data to be moved between file
register memory and the WREG (working register W0). These instructions provide equivalent
functionality to the legacy Microchip PIC MCU MOVF and MOVWF instructions.
The “MOV{.B} f {,WREG}” and “MOV{.B} WREG, f” instructions are the only MOV instructions
which support moves of byte data to and from file register memory. Example 4-18 shows several
MOV instruction examples using the WREG.
Note:

Example 4-18:
MOV.B
MOV
MOV.B
MOV

© 2009 Microchip Technology Inc.

Moving Data with WREG

0x1001, WREG
0x1000, WREG
WREG, TBLPAG
WREG, 0x804

;
;
;
;

move
move
move
move

the
the
the
the

byte
word
byte
word

stored
stored
stored
stored

at
at
at
at

location 0x1001 to W0
location 0x1000 to W0
W0 to the TBLPAG register
W0 to location 0x804

DS70157D-page 69

4
Instruction Set
Details

When moving word data between file register memory and the working register
array, the “MOV Wns, f” and “MOV f, Wnd” instructions allow any working register
(W0:W15) to be used as the source or destination register, not just WREG.

16-bit MCU and DSC Programmer’s Reference Manual
4.11

DSP DATA FORMATS (dsPIC30F AND dsPIC33F DEVICES)
4.11.1

Integer and Fractional Data

The dsPIC30F and dsPIC33F devices support both integer and fractional data types. Integer
data is inherently represented as a signed two’s complement value, where the Most Significant
bit is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integer
is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF),
including ‘0’. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to
2,147,483,647 (0x7FFF FFFF).
Fractional data is represented as a two’s complement number, where the Most Significant bit is
defined as a sign bit, and the radix point is implied to lie just after the sign bit. This format is
commonly referred to as 1.15 (or Q15) format, where 1 is the number of bits used to represent
the integer portion of the number, and 15 is the number of bits used to represent the fractional
portion. The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to
(1 – 21-N). For a 16-bit fraction, the 1.15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF),
including 0.0 and it has a precision of 3.05176x10-5. In Normal Saturation mode, the 32-bit
accumulators use a 1.31 format, which enhances the precision to 4.6566x10-10.
Super Saturation mode expands the dynamic range of the accumulators by using the 8 bits of
the Upper Accumulator register (ACCxU) as guard bits. Guard bits are used if the value stored
in the accumulator overflows beyond the 32nd bit, and they are useful for implementing DSP
algorithms. This mode is enabled when the ACCSAT bit (CORCON<4>), is set to ‘1’ and it
expands the accumulators to 40 bits. The accumulators then support an integer range of
-5.498x1011 (0x80 0000 0000) to 5.498x1011 (0x7F FFFF FFFF). In Fractional mode, the guard
bits of the accumulator do not modify the location of the radix point and the 40-bit accumulators
use a 9.31 fractional format. Note that all fractional operation results are stored in the 40-bit
Accumulator, justified with a 1.31 radix point. As in Integer mode, the guard bits merely increase
the dynamic range of the accumulator. 9.31 fractions have a range of -256.0 (0x80 0000 0000)
to (256.0 – 4.65661x10-10) (0x7F FFFF FFFF). Table 4-10 identifies the range and precision of
integers and fractions on the dsPIC30F/33F devices for 16-bit, 32-bit and 40-bit registers.
It should be noted that, with the exception of DSP multiplies, the ALU operates identically on
integer and fractional data. Namely, an addition of two integers will yield the same result (binary
number) as the addition of two fractional numbers. The only difference is how the result is
interpreted by the user. However, multiplies performed by DSP operations are different. In these
instructions, data format selection is made by the IF bit, CORCON<0>, and it must be set
accordingly (‘0’ for Fractional mode, ‘1’ for Integer mode). This is required because of the implied
radix point used by dsPIC30F/33F fractional numbers. In Integer mode, multiplying two 16-bit
integers produces a 32-bit integer result. However, multiplying two 1.15 values generates a 2.30
result. Since the dsPIC30F and dsPIC33F devices use a 1.31 format for the accumulators, a DSP
multiply in Fractional mode also includes a left shift of one bit to keep the radix point properly
aligned. This feature reduces the resolution of the DSP multiplier to 2-30, but has no other effect
on the computation (e.g., 0.5 x 0.5 = 0.25).
Table 4-10:

dsPIC30F/33F Data Ranges

Register Size

DS70157D-page 70

Integer Range

Fraction Range

Fraction Resolution

16-bit

-32768 to 32767

-1.0 to (1.0 – 2-15)

3.052 x 10-5

32-bit

-2,147,483,648 to
2,147,483,647

-1.0 to (1.0 – 2-31)

4.657 x 10-10

40-bit

-549,755,813,888 to
549,755,813,887

-256.0 to (256.0 – 2-31)

4.657 x 10-10

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.11.2

Integer and Fractional Data Representation

Having a working knowledge of how integer and fractional data are represented on the dsPIC30F
and dsPIC33F is fundamental to working with the device. Both integer and fractional data treat
the Most Significant bit as a sign bit, and the binary exponent decreases by one as the bit position
advances toward the Least Significant bit. The binary exponent for an N-bit integer starts at (N-1)
for the Most Significant bit, and ends at ‘0’ for the Least Significant bit. For an N-bit fraction, the
binary exponent starts at ‘0’ for the Most Significant bit, and ends at (1-N) for the Least Significant
bit (as shown in Figure 4-12 for a positive value and in Figure 4-13 for a negative value).
Conversion between integer and fractional representations can be performed using simple
division and multiplication. To go from an N-bit integer to a fraction, divide the integer value by
2N-1. Likewise, to convert an N-bit fraction to an integer, multiply the fractional value by 2N-1.
Figure 4-12:

Different Representations of 0x4001

Integer:
0

1

-215 214

0

213

0

0

0

0

0

0

0

0

0

0

0

0

212 . . . . . .

1

20

0x4001 = 214 + 20 = 16384 + 1 = 16385
1.15 Fractional:
0

1

-20 . 2-1

0

2-2

0

0

0

0

0

0

0

0

0

0

0

0

2-3 . . . . . .

1

2-15

Implied Radix Point
0x4001 = 2-1 + 2-15 = 0.5 + .000030518 = 0.500030518
Figure 4-13:

Different Representations of 0xC002

4

Integer:
1
1

-215 214

0
0

213

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

1
1

212 . . . . . .

0
0

20

0xC002 = -215 + 214 + 21= -32768 + 16384 + 2 = -16382
1.15 Fractional:
1

1

-20 . 2-1

0

2-2

0

0

0

0

0

0

0

0

0

0

2-3 . . . . . .

0

1

0

2-15

Implied Radix Point
0xC002 = -20 + 2-1 + 2-14 = -1.0 + 0.5 + 0.000061035 = -0.499938965

© 2009 Microchip Technology Inc.

DS70157D-page 71

Instruction Set
Details

1
1

16-bit MCU and DSC Programmer’s Reference Manual
4.12

ACCUMULATOR USAGE (dsPIC30F AND dsPIC33F DEVICES)
Accumulators A and B are utilized by DSP instructions to perform mathematical and shifting
operations. Since the accumulators are 40 bits wide and the X and Y data paths are only 16 bits,
the method to load and store the accumulators must be understood.
Item A in Figure 4-14 shows that each 40-bit Accumulator (ACCA and ACCB) consists of an 8-bit
Upper register (ACCxU), a 16-bit High register (ACCxH) and a 16-bit Low register (ACCxL). To
address the bus alignment requirement and provide the ability for 1.31 math, ACCxH is used as
a destination register for loading the accumulator (with the LAC instruction), and also as a source
register for storing the accumulator (with the SAC.R instruction). This is represented by Item B,
Figure 4-14, where the upper and lower portions of the accumulator are shaded. In reality, during
accumulator loads, ACCxL is zero backfilled and ACCxU is sign-extended to represent the sign
of the value loaded in ACCxH.
When Normal (31-bit) Saturation is enabled, DSP operations (such as ADD, MAC, MSC, etc.)
utilize solely ACCxH:ACCxL (Item C in Figure 4-14) and ACCxU is only used to maintain the sign
of the value stored in ACCxH:ACCxL. For instance, when a MPY instruction is executed, the
result is stored in ACCxH:ACCxL, and the sign of the result is extended through ACCxU.
When Super Saturation is enabled, all registers of the accumulator may be used (Item D in
Figure 4-14) and the results of DSP operations are stored in ACCxU:ACCxH:ACCxL. The benefit
of ACCxU is that it increases the dynamic range of the accumulator, as described in
4.11.1 “Integer and Fractional Data”. Refer to Table 4-10 to see the range of values which may
be stored in the accumulator when in Normal and Super Saturation modes.
Figure 4-14:

Accumulator Alignment and Usage

A)

ACCxU
39

.

32 31 30

ACCxL

ACCxH
16

15

0

Implied Radix Point (between bits 31 and 30)

B)

C)

D)

A)
B)
C)
D)

DS70157D-page 72

40-bit Accumulator consists of ACCxU:ACCxH:ACCxL
Load and Store operations
Operations in Normal Saturation mode
Operations in Super Saturation mode

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.13

ACCUMULATOR ACCESS (dsPIC30F AND dsPIC33F DEVICES)
The six registers of Accumulator A and Accumulator B are memory mapped like any other
Special Function Register. This feature allows them to be accessed with file register or indirect
addressing, using any instruction which supports such addressing. However, it is recommended
that the DSP instructions LAC, SAC and SAC.R be used to load and store the accumulators,
since they provide sign-extension, shifting and rounding capabilities. LAC, SAC and SAC.R
instruction details are provided in Section 5. “Instruction Descriptions”.
Note:

For convenience, ACCAU and ACCBU are sign-extended to 16 bits. This provides
the flexibility to access these registers using either Byte or Word mode (when file
register or indirect addressing is used).

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

DS70157D-page 73

16-bit MCU and DSC Programmer’s Reference Manual
4.14

DSP MAC INSTRUCTIONS (dsPIC30F AND dsPIC33F DEVICES)
The DSP Multiply and Accumulate (MAC) operations are a special suite of instructions which
provide the most efficient use of the dsPIC30F and dsPIC33F architectures. The DSP MAC
instructions, shown in Table 4-11, utilize both the X and Y data paths of the CPU core, which
enables these instructions to perform the following operations all in one cycle:
• two reads from data memory using prefetch working registers (MAC Prefetches)
• two updates to prefetch working registers (MAC Prefetch Register Updates)
• one mathematical operation with an accumulator (MAC Operations)
In addition, four of the ten DSP MAC instructions are also capable of performing an operation with
one accumulator, while storing out the rounded contents of the alternate accumulator. This
feature is called accumulator Write Back (WB) and it provides flexibility for the software
developer. For instance, the accumulator WB may be used to run two algorithms concurrently, or
efficiently process complex numbers, among other things.
Table 4-11:

DSP MAC Instructions

Instruction

Description

Accumulator WB?

CLR

Clear accumulator

Yes

ED

Euclidean distance (no accumulate)

No

EDAC

Euclidean distance

No

MAC

Multiply and accumulate

Yes

MAC

Square and accumulate

No

MOVSAC

Move from X and Y bus

Yes

MPY

Multiply to accumulator

No

MPY

Square to accumulator

No

MPY.N

Negative multiply to accumulator

No

MSC

Multiply and subtract

Yes

4.14.1

MAC Prefetches

Prefetches (or data reads) are made using the effective address stored in the working register.
The two prefetches from data memory must be specified using the working register assignments
shown in Table 4-9. One read must occur from the X data bus using W8 or W9, and one read
must occur from the Y data bus using W10 or W11. The allowed destination registers for both
prefetches are W4-W7.
As shown in Table 4-3, one special Addressing mode exists for the MAC class of instructions. This
mode is the Register Offset Addressing mode and utilizes W12. In this mode, the prefetch is
made using the effective address of the specified working register, plus the 16-bit signed value
stored in W12. Register Offset Addressing may only be used in the X space with W9, and in the
Y-space with W11.

4.14.2

MAC Prefetch Register Updates

After the MAC prefetches are made, the effective address stored in each prefetch working register
may be modified. This feature enables efficient single-cycle processing for data stored
sequentially in X and Y memory. Since all DSP instructions execute in Word mode, only even
numbered updates may be made to the effective address stored in the working register.
Allowable address modifications to each prefetch register are -6, -4, -2, 0 (no update), +2, +4 and
+6. This means that effective address updates may be made up to 3 words in either direction.
When the Register Offset Addressing mode is used, no update is made to the base prefetch
register (W9 or W11), or the offset register (W12).

DS70157D-page 74

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.14.3

MAC Operations

The mathematical operations performed by the MAC class of DSP instructions center around
multiplying the contents of two working registers and either adding or storing the result to either
Accumulator A or Accumulator B. This is the operation of the MAC, MPY, MPY.N and MSC
instructions. Table 4-9 shows that W4-W7 must be used for data source operands in the MAC
class of instructions. W4-W7 may be combined in any fashion, and when the same working
register is specified for both operands, a square or square and accumulate operation is
performed.
For the ED and EDAC instructions, the same multiplicand operand must be specified by the
instruction, because this is the definition of the Euclidean Distance operation. Another unique
feature about this instruction is that the values prefetched from X and Y memory are not actually
stored in W4-W7. Instead, only the difference of the prefetched data words is stored in W4-W7.
The two remaining MAC class instructions, CLR and MOVSAC, are useful for initiating or completing
a series of MAC or EDAC instructions and do not use the multiplier. CLR has the ability to clear
Accumulator A or B, prefetch two values from data memory and store the contents of the other
accumulator. Similarly, MOVSAC has the ability to prefetch two values from data memory and store
the contents of either accumulator.

4.14.4

MAC Write Back

The write back ability of the MAC class of DSP instructions facilitates efficient processing of
algorithms. This feature allows one mathematical operation to be performed with one
accumulator, and the rounded contents of the other accumulator to be stored in the same cycle.
As indicated in Table 4-9, register W13 is assigned for performing the write back, and two
Addressing modes are supported: Direct and Indirect with Post-Increment.
The CLR, MOVSAC and MSC instructions support accumulator Write Back, while the ED, EDAC,
MPY and MPY.N instructions do not support accumulator Write Back. The MAC instruction, which
multiplies two working registers which are not the same, also supports accumulator Write Back.
However, the square and accumulate MAC instruction does not support accumulator Write Back
(see Table 4-11).

4.14.5

MAC Syntax

The syntax of the MAC class of instructions can have several formats, which depend on the
instruction type and the operation it is performing, with respect to prefetches and accumulator
Write Back. With the exception of the CLR and MOVSAC instructions, all MAC class instructions
must specify a target accumulator along with two multiplicands, as shown in Example 4-19.
Base MAC Syntax

Instruction Set
Details

Example 4-19:

; MAC with no prefetch
MAC W4*W5, A

; MAC with no prefetch
MAC W7*W7, B
Multiply W7*W7, Accumulate to ACCB

© 2009 Microchip Technology Inc.

4

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16-bit MCU and DSC Programmer’s Reference Manual
If a prefetch is used in the instruction, the assembler is capable of discriminating the X or Y data
prefetch based on the register used for the effective address. [W8] or [W9] specifies the X
prefetch and [W10] or [W11] specifies the Y prefetch. Brackets around the working register are
required in the syntax, and they designate that indirect addressing is used to perform the
prefetch. When address modification is used, it must be specified using a minus-equals or
plus-equals “C”-like syntax (i.e., “[W8] – = 2” or “[W8] + = 6”). When Register Offset Addressing
is used for the prefetch, W12 is placed inside the brackets ([W9 + W12] for X prefetches and [W11
+ W12] for Y prefetches). Each prefetch operation must also specify a prefetch destination
register (W4-W7). In the instruction syntax, the destination register appears before the prefetch
register. Legal forms of prefetch are shown in Example 4-20.
Example 4-20:

MAC Prefetch Syntax

; MAC with X only prefetch
MAC W5*W6, A, [W8]+=2, W5
ACCA=ACCA+W5*W6
X([W8]+=2)→ W5
; MAC with Y only prefetch
MAC W5*W5, B, [W11+W12], W5

ACCB=ACCB+W5*W5
Y([W11+W12])→ W5

; MAC with X/Y prefetch
MAC W6*W7, B, [W9], W6,

[W10]+=4, W7
ACCB=ACCB+W6*W7
X([W9])→ W6
Y([W10]+=4)→ W7

If an accumulator Write Back is used in the instruction, it is specified last. The Write Back must
use the W13 register, and allowable forms for the Write Back are “W13” for direct addressing and
“[W13] + = 2” for indirect addressing with post-increment. By definition, the accumulator not used
in the mathematical operation is stored, so the Write Back accumulator is not specified in the
instruction. Legal forms of accumulator Write Back (WB) are shown in Example 4-21.

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Section 4. Instruction Set Details
Example 4-21:

MAC Accumulator WB Syntax

; CLR with direct WB of ACCB
CLR A,

W13
0 → ACCA
ACCB → W13

; MAC with indirect WB of ACCB
MAC W4*W5, A

[W13]+=2
ACCA=ACCA+W4*W5
ACCB → [W13]+=2

; MAC with Y prefetch, direct WB of ACCA
MAC W4*W5, B,

[W10]+=2, W4,

W13
ACCB=ACCB+W4*W5
Y([W10]+=2)→ W4
ACCA → W13

Putting it all together, an MSC instruction which performs two prefetches and a write back is
shown in Example 4-22.
Example 4-22:

MSC Instruction with Two Prefetches and Accumulator Write Back

; MSC with X/Y prefetch, indirect WB of ACCA
MSC W6*W7, B, [W8]+=2, W6, [W10]-=6, W7 [W13]+=2
ACCB=ACCB-W6*W7

4

X([W8]+=2)→W6
ACCA→[W13]+=2

© 2009 Microchip Technology Inc.

DS70157D-page 77

Instruction Set
Details

Y([W10]-=6)→W7

16-bit MCU and DSC Programmer’s Reference Manual
4.15

DSP ACCUMULATOR INSTRUCTIONS (dsPIC30F AND dsPIC33F
DEVICES)
The DSP Accumulator instructions do not have prefetch or accumulator WB ability, but they do
provide the ability to add, negate, shift, load and store the contents of either 40-bit Accumulator.
In addition, the ADD and SUB instructions allow the two accumulators to be added or subtracted
from each other. DSP Accumulator instructions are shown in Table 4-12 and instruction details
are provided in Section 5. “Instruction Descriptions”.
Table 4-12:
Instruction

DS70157D-page 78

DSP Accumulator Instructions
Description

Accumulator WB?

ADD

Add accumulators

No

ADD

16-bit signed accumulator add

No

LAC

Load accumulator

No

NEG

Negate accumulator

No

SAC

Store accumulator

No

SAC.R

Store rounded accumulator

No

SFTAC

Arithmetic shift accumulator by Literal

No

SFTAC

Arithmetic shift accumulator by (Wn)

No

SUB

Subtract accumulators

No

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.16

SCALING DATA WITH THE FBCL INSTRUCTION (dsPIC30F AND dsPIC33F
DEVICES)
To minimize quantization errors that are associated with data processing using DSP instructions,
it is important to utilize the complete numerical result of the operations. This may require scaling
data up to avoid underflow (i.e., when processing data from a 12-bit ADC), or scaling data down
to avoid overflow (i.e., when sending data to a 10-bit DAC). The scaling, which must be
performed to minimize quantization error, depends on the dynamic range of the input data which
is operated on, and the required dynamic range of the output data. At times, these conditions
may be known beforehand and fixed scaling may be employed. In other cases, scaling conditions
may not be fixed or known, and then dynamic scaling must be used to process data.
The FBCL instruction (Find First Bit Change Left) can efficiently be used to perform dynamic
scaling, because it determines the exponent of a value. A fixed point or integer value’s exponent
represents the amount which the value may be shifted before overflowing. This information is
valuable, because it may be used to bring the data value to “full scale”, meaning that its numeric
representation utilizes all the bits of the register it is stored in.
The FBCL instruction determines the exponent of a word by detecting the first bit change starting
from the value’s sign bit and working towards the LSB. Since the dsPIC DSC device’s barrel
shifter uses negative values to specify a left shift, the FBCL instruction returns the negated
exponent of a value. If the value is being scaled up, this allows the ensuing shift to be performed
immediately with the value returned by FBCL. Additionally, since the FBCL instruction only
operates on signed quantities, FBCL produces results in the range of -15:0. When the FBCL
instruction returns ‘0’, it indicates that the value is already at full scale. When the instruction
returns -15, it indicates that the value cannot be scaled (as is the case with 0x0 and 0xFFFF).
Table 4-13 shows word data with various dynamic ranges, their exponents, and the value after
scaling each data to maximize the dynamic range. Example 4-23 shows how the FBCL
instruction may be used for block processing.
Table 4-13:

Scaling Examples

Word Value

Exponent

Full Scale Value
(Word Value << Exponent)

0x0001

14

0x4000

0x0002

13

0x4000

0x0004

12

0x4000

6

0x4000

6

0x7FC0

0x0806

3

0x4030

0x2007

1

0x400E

0x4800

0

0x4800

0x7000

0

0x7000

0x8000

0

0x8000

0x900A

0

0x900A

0xE001

2

0x8004

0xFF07

7

0x8380

Note:

4
Instruction Set
Details

0x0100
0x01FF

For the word values 0x0000 and 0xFFFF, the FBCL instruction returns -15.

As a practical example, assume that block processing is performed on a sequence of data with
very low dynamic range stored in 1.15 fractional format. To minimize quantization errors, the data
may be scaled up to prevent any quantization loss which may occur as it is processed. The FBCL
instruction can be executed on the sample with the largest magnitude to determine the optimal
scaling value for processing the data. Note that scaling the data up is performed by left shifting
the data. This is demonstrated with the code snippet below.

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual
Example 4-23:

Scaling with FBCL

; assume W0 contains the largest absolute value of the data block
; assume W4 points to the beginning of the data block
; assume the block of data contains BLOCK_SIZE words
; determine the exponent to use for scaling
FBCL
W0, W2
; store exponent in W2
; scale
DO
LAC
SFTAC
SCALE:
SAC

the entire data block before processing
#(BLOCK_SIZE-1), SCALE
[W4], A
; move the next data sample to ACCA
A, W2
; shift ACCA by W2 bits
A, [W4++]

; store scaled input (overwrite original)

; now process the data
; (processing block goes here)

DS70157D-page 80

© 2009 Microchip Technology Inc.

Section 4. Instruction Set Details
4.17

NORMALIZING THE ACCUMULATOR WITH THE FBCL INSTRUCTION
(dsPIC30F AND dsPIC33F DEVICES)
The process of scaling a quantized value for its maximum dynamic range is known as
normalization (the data in the third column in Table 4-13 contains normalized data). Accumulator
normalization is a technique used to ensure that the accumulator is properly aligned before
storing data from the accumulator, and the FBCL instruction facilitates this function.
The two 40-bit accumulators each have 8 guard bits from the ACCxU register, which expands the
dynamic range of the accumulators from 1.31 to 9.31, when operating in Super Saturation mode
(see 4.11.1 “Integer and Fractional Data”). However, even in Super Saturation mode, the Store
Rounded Accumulator (SAC.R) instruction only stores 16-bit data (in 1.15 format) from ACCxH,
as described in 4.12 “Accumulator Usage (dsPIC30F and dsPIC33F Devices)”. Under certain
conditions, this may pose a problem.
Proper data alignment for storing the contents of the accumulator may be achieved by scaling
the accumulator down if ACCxU is in use, or scaling the accumulator up if all of the ACCxH bits
are not being used. To perform such scaling, the FBCL instruction must operate on the ACCxU
byte and it must operate on the ACCxH word. If a shift is required, the ALU’s 40-bit shifter is
employed, using the SFTAC instruction to perform the scaling. Example 4-24 contains a code
snippet for accumulator normalization.
Example 4-24:

Normalizing with FBCL

; assume an operation in ACCA has just completed (SR intact)
; assume the processor is in super saturation mode
; assume ACCAH is defined to be the address of ACCAH (0x24)
MOV
#ACCAH, W5
BRA
OA, FBCL_GUARD
FBCL_HI:
FBCL
[W5], W0
BRA
SHIFT_ACC
FBCL_GUARD:
FBCL
[++W5], W0
ADD.B
W0, #15, W0
SHIFT_ACC:
SFTAC
A, W0

; W5 points to ACCAH
; if overflow we right shift
; extract exponent for left shift
; branch to the shift
; extract exponent for right shift
; adjust the sign for right shift
; shift ACCA to normalize

4
Instruction Set
Details

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual
NOTES:

DS70157D-page 82

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
HIGHLIGHTS
This section of the manual contains the following major topics:
5.1
5.2
5.3
5.4

Instruction Symbols......................................................................................................... 84
Instruction Encoding Field Descriptors Introduction........................................................ 84
Instruction Description Example ..................................................................................... 88
Instruction Descriptions................................................................................................... 89

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual
5.1

Instruction Symbols
All the symbols used in Section 5.4 “Instruction Descriptions” are listed in Table 1-2.

5.2

Instruction Encoding Field Descriptors Introduction
All instruction encoding field descriptors used in Section 5.4 “Instruction Descriptions” are
shown in Table 5-2 through Table 5-12.
Table 5-1:

Instruction Encoding Field Descriptors
Field

Description
A

(1)

aa(1)
B
bbbb
D
dddd
f ffff ffff ffff
fff ffff ffff ffff
ffff ffff ffff ffff
ggg
hhh
iiii(1)
jjjj(1)
k
kkkk
kk kkkk
kkkk kkkk
kk kkkk kkkk
kk kkkk kkkk kkkk
kkkk kkkk kkkk kkkk
mm
mmm
nnnn nnnn nnnn nnn0
nnn nnnn
nnnn nnnn nnnn nnnn
ppp
qqq
rrrr
ssss
tttt
vvvv
W

Accumulator selection bit: 0 = ACCA; 1 = CCB
Accumulator Write Back mode (see Table 5-12)
Byte mode selection bit: 0 = word operation; 1 = byte operation
4-bit bit position select: 0000 = LSB; 1111 = MSB
Destination address bit: 0 = result stored in WREG;
1 = result stored in file register
Wd destination register select: 0000 = W0; 1111 = W15
13-bit register file address (0x0000 to 0x1FFF)
15-bit register file word address (implied 0 LSB)
(0x0000 to 0xFFFE)
16-bit register file byte address (0x0000 to 0xFFFF)
Register Offset Addressing mode for Ws source register
(see Table 5-4)
Register Offset Addressing mode for Wd destination register
(see Table 5-5)
Prefetch X Operation (see Table 5-6)
Prefetch Y Operation (see Table 5-8)
1-bit literal field, constant data or expression
4-bit literal field, constant data or expression
6-bit literal field, constant data or expression
8-bit literal field, constant data or expression
10-bit literal field, constant data or expression
14-bit literal field, constant data or expression
16-bit literal field, constant data or expression
Multiplier source select with same working registers
(see Table 5-10)
Multiplier source select with different working registers
(see Table 5-11)
23-bit program address for CALL and GOTO instructions

16-bit program offset field for relative branch/call instructions
Addressing mode for Ws source register (see Table 5-2)
Addressing mode for Wd destination register (see Table 5-3)
Barrel shift count
Ws source register select: 0000 = W0; 1111 = W15
Dividend select, most significant word
Dividend select, least significant word
Double Word mode selection bit: 0 = word operation;
1 = double word operation
wwww
Wb base register select: 0000 = W0; 1111 = W15
xx(1)
Prefetch X Destination (see Table 5-7)
xxxx xxxx xxxx xxxx
16-bit unused field (don’t care)
yy(1)
Prefetch Y Destination (see Table 5-9)
z
Bit test destination: 0 = C flag bit; 1 = Z flag bit
Note 1: This field is only available in dsPIC30F and dsPIC33F devices.

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© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Table 5-2:

Addressing Modes for Ws Source Register
Addressing Mode

ppp

Source Operand

000

Register Direct

001

Indirect

[Ws]

010

Indirect with Post-Decrement

[Ws--]

011

Indirect with Post-Increment

[Ws++]

100

Indirect with Pre-Decrement

[--Ws]

101

Indirect with Pre-Increment

[++Ws]

11x

Unused

Table 5-3:

Ws

Addressing Modes for Wd Destination Register
Addressing Mode

qqq

Destination Operand

000

Register Direct

Wd

001

Indirect

[Wd]

010

Indirect with Post-Decrement

[Wd--]

011

Indirect with Post-Increment

[Wd++]

100

Indirect with Pre-Decrement

[--Wd]

101

Indirect with Pre-Increment

[++Wd]

11x

Unused (an attempt to use this Addressing mode will force a RESET instruction)

Table 5-4:

Offset Addressing Modes for Ws Source Register (with Register Offset)
Addressing Mode

ggg

Source Operand

000

Register Direct

Ws

001

Indirect

[Ws]

010

Indirect with Post-Decrement

[Ws--]

011

Indirect with Post-Increment

[Ws++]

100

Indirect with Pre-Decrement

[--Ws]

101

Indirect with Pre-Increment

[++Ws]

11x

Indirect with Register Offset

[Ws+Wb]

Table 5-5:

Offset Addressing Modes for Wd Destination Register
(with Register Offset)
Addressing Mode

hhh

Source Operand

000

Register Direct

Wd

001

Indirect

[Wd]

010

Indirect with Post-Decrement

[Wd--]

011

Indirect with Post-Increment

[Wd++]

100

Indirect with Pre-Decrement

[--Wd]

101

Indirect with Pre-Increment

[++Wd]

11x

Indirect with Register Offset

[Wd+Wb]

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual
Table 5-6:

X Data Space Prefetch Operation (dsPIC30F and dsPIC33F)
Operation

iiii
0000

Wxd = [W8]

0001

Wxd = [W8], W8 = W8 + 2

0010

Wxd = [W8], W8 = W8 + 4

0011

Wxd = [W8], W8 = W8 + 6

0100

No Prefetch for X Data Space

0101

Wxd = [W8], W8 = W8 – 6

0110

Wxd = [W8], W8 = W8 – 4

0111

Wxd = [W8], W8 = W8 – 2

1000

Wxd = [W9]

1001

Wxd = [W9], W9 = W9 + 2

1010

Wxd = [W9], W9 = W9 + 4

1011

Wxd = [W9], W9 = W9 + 6

1100

Wxd = [W9 + W12]

1101

Wxd = [W9], W9 = W9 – 6

1110

Wxd = [W9], W9 = W9 – 4

1111

Wxd = [W9], W9 = W9 – 2

Table 5-7:

X Data Space Prefetch Destination (dsPIC30F and dsPIC33F)
Wxd

xx
00

W4

01

W5

10

W6

11

W7

Table 5-8:

Y Data Space Prefetch Operation (dsPIC30F and dsPIC33F)
Operation

jjjj

DS70157D-page 86

0000

Wyd = [W10]

0001

Wyd = [W10], W10 = W10 + 2

0010

Wyd = [W10], W10 = W10 + 4

0011

Wyd = [W10], W10 = W10 + 6

0100

No Prefetch for Y Data Space

0101

Wyd = [W10], W10 = W10 – 6

0110

Wyd = [W10], W10 = W10 – 4

0111

Wyd = [W10], W10 = W10 – 2

1000

Wyd = [W11]

1001

Wyd = [W11], W11 = W11 + 2

1010

Wyd = [W11], W11 = W11 + 4

1011

Wyd = [W11], W11 = W11 + 6

1100

Wyd = [W11 + W12]

1101

Wyd = [W11], W11 = W11 – 6

1110

Wyd = [W11], W11 = W11 – 4

1111

Wyd = [W11], W11 = W11 – 2

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Table 5-9:

Y Data Space Prefetch Destination (dsPIC30F and dsPIC33F)
Wyd

yy
00

W4

01

W5

10

W6

11

W7

Table 5-10:

MAC or MPY Source Operands (Same Working Register) (dsPIC30F and
dsPIC33F)
Multiplicands

mm
00

W4 * W4

01

W5 * W5

10

W6 * W6

11

W7 * W7

Table 5-11:

MAC or MPY Source Operands (Different Working Register) (dsPIC30F and
dsPIC33F)
Multiplicands

mmm
000

W4 * W5

001

W4 * W6

010

W4 * W7

011

Invalid

100

W5 * W6

101

W5 * W7

110

W6 * W7

111

Invalid

Table 5-12:

MAC Accumulator Write Back Selection (dsPIC30F and dsPIC33F)
Write Back Selection

aa
00

W13 = Other Accumulator (Direct Addressing)

01

[W13] + = 2 = Other Accumulator (Indirect Addressing with Post-Increment)

10

No Write Back

11

Invalid

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual
5.3

Instruction Description Example
The example description below is for the fictitious instruction FOO. The following example
instruction was created to demonstrate how the table fields (syntax, operands, operation, etc.)
are used to describe the instructions presented in Section 5.4 “Instruction Descriptions”.

FOO
Implemented in:

The Header field summarizes what the instruction does
PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

Cells marked with an ‘X’ indicate the instruction is implemented for that
device family.

DS70157D-page 88

Syntax:

The Syntax field consists of an optional label, the instruction mnemonic, any
optional extensions which exist for the instruction and the operands for the
instruction. Most instructions support more than one operand variant to
support the various dsPIC30F/dsPIC33F Addressing modes. In these
circumstances, all possible instruction operands are listed beneath each
other (as in the case of op2a, op2b and op2c above). Optional operands are
enclosed in braces.

Operands:

The Operands field describes the set of values which each of the operands
may take. Operands may be accumulator registers, file registers, literal
constants (signed or unsigned), or working registers.

Operation:

The Operation field summarizes the operation performed by the instruction.

Status Affected:

The Status Affected field describes which bits of the STATUS Register are
affected by the instruction. Status bits are listed by bit position in
descending order.

Encoding:

The Encoding field shows how the instruction is bit encoded. Individual bit
fields are explained in the Description field, and complete encoding details
are provided in Table 5.2.

Description:

The Description field describes in detail the operation performed by the
instruction. A key for the encoding bits is also provided.

Words:

The Words field contains the number of program words that are used to
store the instruction in memory.

Cycles:

The Cycles field contains the number of instruction cycles that are required
to execute the instruction.

Examples:

The Examples field contains examples that demonstrate how the instruction
operates. “Before” and “After” register snapshots are provided, which allow
the user to clearly understand what operation the instruction performs.

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
5.4

Instruction Descriptions

ADD

Add f to WREG

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) + (WREG) → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

ADD{.B}

1011

0100

f

{,WREG}

0BDf

ffff

ffff

ffff

Add the contents of the default working register WREG to the contents of
the file register, and place the result in the destination register. The
optional WREG operand determines the destination register. If WREG is
specified, the result is stored in WREG. If WREG is not specified, the
result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

ADD.B

RAM100

Before
Instruction
WREG CC80
RAM100 FFC0
SR
0000

Example 2:

ADD

; Add WREG to RAM100 (Byte mode)

After
Instruction
WREG CC80
RAM100 FF40
SR
0005 (OV, C = 1)

RAM200, WREG

Before
Instruction
WREG CC80
RAM200 FFC0
SR 0000

; Add RAM200 to WREG (Word mode)

After
Instruction
WREG CC40
RAM200 FFC0
SR 0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

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16-bit MCU and DSC Programmer’s Reference Manual

ADD

Add Literal to Wn

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

lit10 + (Wn) → Wn

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

ADD{.B}

1011

0000

#lit10,

Wn

0Bkk

kkkk

kkkk

dddd

Add the 10-bit unsigned literal operand to the contents of the working
register Wn, and place the result back into the working register Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an unsigned
value [0:255]. See Section 4.6 “Using 10-bit Literal Operands”
for information on using 10-bit literal operands in Byte mode.

Words:

1

Cycles:

1

Example 1:

ADD.B

#0xFF, W7

Before
Instruction
W7 12C0
SR
0000

Example 2:

ADD

Before
Instruction
W1 12C0
SR
0000

DS70157D-page 90

; Add -1 to W7 (Byte mode)

After
Instruction
W7 12BF
SR 0009 (N, C = 1)

#0xFF, W1

; Add 255 to W1 (Word mode)

After
Instruction
W1 13BF
SR 0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ADD

Add Wb to Short Literal

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ADD{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb) + lit5 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

0100

0www

wBqq

qddd

d11k

kkkk

Add the contents of the base register Wb to the 5-bit unsigned short literal
operand, and place the result in the destination register Wd. Register
direct addressing must be used for Wb. Either register direct or indirect
addressing may be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

ADD.B

Before
Instruction
W0
2290
W7 12C0
SR
0000

W0, #0x1F, W7

; Add W0 and 31 (Byte mode)
; Store the result in W7

After
Instruction
W0 2290
W7 12AF
SR 0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 91

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

ADD

Before
Instruction
W3
6006
W4
1000
Data 0FFE DDEE
Data 1000 DDEE
SR
0000

DS70157D-page 92

W3, #0x6, [--W4]

; Add W3 and 6 (Word mode)
; Store the result in [--W4]

After
Instruction
W3 6006
W4 0FFE
Data 0FFE 600C
Data 1000 DDEE
SR 0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ADD

Add Wb to Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ADD{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb) + (Ws) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

0100

0www

Wb,

Ws,

wBqq

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Add the contents of the source register Ws and the contents of the base
register Wb, and place the result in the destination register Wd. Register
direct addressing must be used for Wb. Either register direct or indirect
addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

ADD.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W5, W6, W7

Before
Instruction
W5
AB00
W6
0030
W7
FFFF
SR
0000

; Add W5 to W6, store result in W7
; (Byte mode)

After
Instruction
W5
AB00
W6
0030
W7
FF30
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 93

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

ADD

Before
Instruction
W5
AB00
W6
0030
W7
FFFF
SR
0000

DS70157D-page 94

W5, W6, W7

; Add W5 to W6, store result in W7
; (Word mode)

After
Instruction
W5
AB00
W6
0030
W7
AB30
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ADD

Add Accumulators

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

A000

0000

Syntax:

{label:}

Operands:

Acc ∈ [A,B]

Operation:

If (Acc = A):
(ACCA) + (ACCB) → ACCA
Else:
(ACCA) + (ACCB) → ACCB

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

ADD

dsPIC30F

1100

Description:

1011

Acc

0000

0000

Add the contents of Accumulator A to the contents of Accumulator B and
place the result in the selected accumulator. This instruction performs a
40-bit addition.
The ‘A’ bit specifies the destination accumulator.

Words:

1

Cycles:

1

Example 1:

ADD

ACCA
ACCB
SR
Example 2:

ADD

ACCA
ACCB
SR

A

Before
Instruction
00 0022 3300
00 1833 4558
0000
B

Before
Instruction
00 E111 2222
00 7654 3210
0000

; Add ACCB to ACCA

ACCA
ACCB
SR

After
Instruction
00 1855 7858
00 1833 4558
0000

; Add ACCA to ACCB
; Assume Super Saturation mode enabled
; (ACCSAT = 1, SATA = 1, SATB = 1)

ACCA
ACCB
SR

After
Instruction
00 E111 2222
01 5765 5432
4800 (OB, OAB = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 95

16-bit MCU and DSC Programmer’s Reference Manual

ADD

16-Bit Signed Add to Accumulator

Implemented in:

Syntax:

PIC24F

{label:}

PIC24H

ADD

dsPIC30F

dsPIC33F

X

X

Ws,

{#Slit4,}

Acc

[Ws],
[Ws++],
[Ws--],
[--Ws],
[++Ws],
[Ws+Wb],
Operands:

Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]
Slit4 ∈ [-8 ... +7]
Acc ∈ [A,B]

Operation:

ShiftSlit4(Extend(Ws)) + (Acc) → Acc

Status Affected: OA, OB, OAB, SA, SB, SAB
Encoding:
Description:

1100

1001

Awww

wrrr

rggg

ssss

Add a 16-bit value specified by the source working register to the most
significant word of the selected accumulator. The source operand may
specify the direct contents of a working register or an effective address. The
value specified is added to the most significant word of the accumulator by
sign-extending and zero backfilling the source operand prior to the operation.
The value added to the accumulator may also be shifted by a 4-bit signed
literal before the addition is made.
The ‘A’ bit specifies the destination accumulator.
The ‘w’ bits specify the offset register Wb.
The ‘r’ bits encode the optional shift.
The ‘g’ bits select the source Address mode.
The ‘s’ bits specify the source register Ws.
Note:

Words:

1

Cycles:

1

Example 1:

ADD

W0
ACCA
SR

DS70157D-page 96

Positive values of operand Slit4 represent an arithmetic shift right
and negative values of operand Slit4 represent an arithmetic shift
left. The contents of the source register are not affected by Slit4.

W0, #2, A

Before
Instruction
8000
00 7000 0000
0000

; Add W0 right-shifted by 2 to ACCA

W0
ACCA
SR

After
Instruction
8000
00 5000 0000
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Example 2:

ADD

W5
ACCA
Data 2000
SR

[W5++], A

Before
Instruction
2000
00 0067 2345
5000
0000

; Add the effective value of W5 to ACCA
; Post-increment W5

W5
ACCA
Data 2000
SR

After
Instruction
2002
00 5067 2345
5000
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 97

16-bit MCU and DSC Programmer’s Reference Manual

ADDC

Add f to WREG with Carry

Implemented in:

PIC24F

PIC24H

X

X

dsPIC30F dsPIC33F
X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) + (WREG) + (C) → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

1011

ADDC{.B} f

X

0100

{,WREG}

1BDf

ffff

ffff

ffff

Add the contents of the default working register WREG, the contents of
the file register and the Carry bit and place the result in the destination
register. The optional WREG operand determines the destination
register. If WREG is specified, the result is stored in WREG. If WREG is
not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

ADDC.B

RAM100

; Add WREG and C bit to RAM100
; (Byte mode)

Before
After
Instruction
Instruction
WREG CC60
WREG CC60
RAM100
8006
RAM100 8067
SR
0001 (C=1)
SR 0000
Example 2:

ADDC

RAM200, WREG

; Add RAM200 and C bit to the WREG
; (Word mode)

Before
After
Instruction
Instruction
WREG
5600
WREG 8A01
RAM200
3400
RAM200 3400
SR
0001 (C=1)
SR 000C (N, OV = 1)

DS70157D-page 98

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ADDC

Add Literal to Wn with Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

lit10 + (Wn) + (C) → Wn

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

1011

ADDC{.B}

0000

#lit10,

1Bkk

Wn

kkkk

kkkk

dddd

Add the 10-bit unsigned literal operand, the contents of the working
register Wn and the Carry bit, and place the result back into the working
register Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an
unsigned value [0:255]. See Section 4.6 “Using 10-bit Literal
Operands” for information on using 10-bit literal operands in
Byte mode.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

ADDC.B

#0xFF, W7

Before
Instruction
W7 12C0
SR
0000 (C = 0)

Example 2:

ADDC

#0xFF, W1

Before
Instruction
W1 12C0
SR
0001 (C = 1)

; Add -1 and C bit to W7 (Byte mode)

After
Instruction
W7 12BF
SR 0009 (N,C = 1)

; Add 255 and C bit to W1 (Word mode)

After
Instruction
W1 13C0
SR 0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 99

16-bit MCU and DSC Programmer’s Reference Manual

ADDC

Add Wb to Short Literal with Carry

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ADDC{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb) + lit5 + (C) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

0100

1www

wBqq

qddd

d11k

kkkk

Add the contents of the base register Wb, the 5-bit unsigned short literal
operand and the Carry bit, and place the result in the destination register
Wd. Register direct addressing must be used for Wb. Register direct or
indirect addressing may be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

ADDC.B

W0, #0x1F, [W7]

Before
Instruction
W0 CC80
W7
12C0
Data 12C0
B000
SR
0000 (C = 0)

DS70157D-page 100

; Add W0, 31 and C bit (Byte mode)
; Store the result in [W7]

After
Instruction
W0 CC80
W7 12C0
Data 12C0 B09F
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Example 2:

ADDC

W3, #0x6, [--W4]

Before
Instruction
W3 6006
W4 1000
Data 0FFE DDEE
Data 1000 DDEE
SR 0001 (C = 1)

W3
W4
Data 0FFE
Data 1000
SR

; Add W3, 6 and C bit (Word mode)
; Store the result in [--W4]

After
Instruction
6006
0FFE
600D
DDEE
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 101

16-bit MCU and DSC Programmer’s Reference Manual

ADDC

Add Wb to Ws with Carry

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ADDC{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb) + (Ws) + (C) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

0100

Wb,

1www

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Add the contents of the source register Ws, the contents of the base
register Wb and the Carry bit, and place the result in the destination
register Wd. Register direct addressing must be used for Wb. Either
register direct or indirect addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

ADDC.B

W0,[W1++],[W2++]

; Add W0, [W1] and C bit (Byte mode)
; Store the result in [W2]
; Post-increment W1, W2

Before
After
Instruction
Instruction
W0 CC20
W0 CC20
W1 0800
W1 0801
W2 1000
W2 1001
Data 0800 AB25
Data 0800 AB25
Data 1000 FFFF
Data 1000 FF46
SR 0001 (C = 1)
SR 0000

DS70157D-page 102

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Example 2:

ADDC

W3,[W2++],[W1++]

; Add W3, [W2] and C bit (Word mode)
; Store the result in [W1]
; Post-increment W1, W2

Before
After
Instruction
Instruction
W1 1000
W1
1002
W2 2000
W2
2002
W3 0180
W3
0180
Data 1000 8000
Data 1000
2681
Data 2000 2500
Data 2000
2500
SR 0001 (C = 1)
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 103

16-bit MCU and DSC Programmer’s Reference Manual

AND

AND f and WREG

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f).AND.(WREG) → destination designated by D

Status Affected:

N, Z

Encoding:
Description:

AND{.B}

1011

0110

f

{,WREG}

0BDf

ffff

ffff

ffff

Compute the logical AND operation of the contents of the default working
register WREG and the contents of the file register, and place the result in
the destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

AND.B

RAM100

Before
Instruction
WREG CC80
RAM100 FFC0
SR
0000
Example 2:

AND

RAM200, WREG

Before
Instruction
WREG CC80
RAM200 12C0
SR
0000

DS70157D-page 104

; AND WREG to RAM100 (Byte mode)

After
Instruction
WREG CC80
RAM100 FF80
SR 0008 (N = 1)
; AND RAM200 to WREG (Word mode)

After
Instruction
WREG 0080
RAM200 12C0
SR 0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

AND

AND Literal and Wd

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

lit10.AND.(Wn) → Wn

Status Affected:

N, Z

Encoding:
Description:

AND{.B}

1011

0010

#lit10,

0Bkk

Wn

kkkk

kkkk

dddd

Compute the logical AND operation of the 10-bit literal operand and the
contents of the working register Wn and place the result back into the
working register Wn. Register direct addressing must be used for Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an unsigned
value [0:255]. See Section 4.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte
mode.

Words:

1

Cycles:

1

Example 1:

AND.B

#0x83, W7

Before
Instruction
W7 12C0
SR
0000
Example 2:

AND

#0x333, W1

Before
Instruction
W1 12D0
SR
0000

; AND 0x83 to W7 (Byte mode)

After
Instruction
W7
1280
SR
0008 (N = 1)
; AND 0x333 to W1 (Word mode)

After
Instruction
W1
0210
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 105

16-bit MCU and DSC Programmer’s Reference Manual

AND

AND Wb and Short Literal

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

AND{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb).AND.lit5 → Wd

Status Affected:

N, Z

Encoding:

0110

Description:

0www

wBqq

qddd

d11k

kkkk

Compute the logical AND operation of the contents of the base register
Wb and the 5-bit literal and place the result in the destination register Wd.
Register direct addressing must be used for Wb. Either register direct or
indirect addressing may be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

AND.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0,#0x3,[W1++]

Before
Instruction
W0 23A5
W1
2211
Data 2210
9999
SR
0000
Example 2:

AND

Before
Instruction
W0
6723
W1
7878
SR
0000

DS70157D-page 106

; AND W0 and 0x3 (Byte mode)
; Store to [W1]
; Post-increment W1

After
Instruction
W0 23A5
W1 2212
Data 2210 0199
SR 0000

W0,#0x1F,W1

; AND W0 and 0x1F (Word mode)
; Store to W1

After
Instruction
W0 6723
W1 0003
SR 0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

AND

And Wb and Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

AND{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb).AND.(Ws) → Wd

Status Affected:

N, Z

Encoding:

0110

Description:

Wb,

0www

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Compute the logical AND operation of the contents of the source register
Ws and the contents of the base register Wb, and place the result in the
destination register Wd. Register direct addressing must be used for Wb.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

AND.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, W1 [W2++]

Before
Instruction
W0 AA55
W1
2211
W2
1001
Data 1000 FFFF
SR
0000

; AND W0 and W1, and
; store to [W2] (Byte mode)
; Post-increment W2

After
Instruction
W0 AA55
W1
2211
W2
1002
Data 1000
11FF
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 107

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

AND

W0, [W1++], W2 ; AND W0 and [W1], and
; store to W2 (Word mode)
; Post-increment W1

Before
Instruction
W0
AA55
W1
1000
W2
55AA
Data 1000
2634
SR
0000

DS70157D-page 108

After
Instruction
W0
AA55
W1
1002
W2
2214
Data 1000
2634
SR
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ASR

Arithmetic Shift Right f

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ASR{.B}

f

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
(f<7>) → Dest<7>
(f<7>) → Dest<6>
(f<6:1>) → Dest<5:0>
(f<0>) → C
For word operation:
(f<15>) → Dest<15>
(f<15>) → Dest<14>
(f<14:1>) → Dest<13:0>
(f<0>) → C

{,WREG}

C

Status Affected:

N, Z, C

Encoding:

1101

Description:

0101

1BDf

ffff

ffff

ffff

Shift the contents of the file register one bit to the right and place the result
in the destination register. The Least Significant bit of the file register is
shifted into the Carry bit of the STATUS Register. After the shift is performed, the result is sign-extended. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in
WREG. If WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ’1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

ASR.B

RAM400, WREG

© 2009 Microchip Technology Inc.

After
Instruction
WREG
0611
RAM400
0823
SR
0001 (C = 1)

5
Instruction
Descriptions

Before
Instruction
WREG
0600
RAM400
0823
SR
0000

; ASR RAM400 and store to WREG
; (Byte mode)

DS70157D-page 109

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

ASR

RAM200

Before
Instruction
RAM200
8009
SR
0000

DS70157D-page 110

; ASR RAM200 (Word mode)

After
Instruction
RAM200 C004
SR
0009 (N, C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ASR

Arithmetic Shift Right Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ASR{.B}

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
(Ws<7>) → Wd<7>
(Ws<7>) → Wd<6>
(Ws<6:1>) → Wd<5:0>
(Ws<0>) → C
For word operation:
(Ws<15>) → Wd<15>
(Ws<15>) → Wd<14>
(Ws<14:1>) → Wd<13:0>
(Ws<0>) → C
C

Status Affected:

N, Z, C

Encoding:
Description:

1101

0001

1Bqq

qddd

dppp

ssss

Shift the contents of the source register Ws one bit to the right and place the
result in the destination register Wd. The Least Significant bit of Ws is
shifted into the Carry bit of the STATUS register. After the shift is performed,
the result is sign-extended. Either register direct or indirect addressing may
be used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 111

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

ASR.B

[W0++], [W1++]

Before
Instruction
W0
0600
W1
0801
Data 600
2366
Data 800
FFC0
SR
0000

Example 2:

ASR

W12, W13

Before
Instruction
W12 AB01
W13
0322
SR
0000

DS70157D-page 112

; ASR [W0] and store to [W1]
(Byte mode)
; Post-increment W0 and W1

After
Instruction
W0
0601
W1
0802
Data 600
2366
Data 800 33C0
SR
0000

; ASR W12 and store to W13
(Word mode)

After
Instruction
W12 AB01
W13 D580
SR 0009 (N, C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

ASR

Arithmetic Shift Right by Short Literal

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit4 ∈ [0...15]
Wnd ∈ [W0 ... W15]

Operation:

lit4<3:0> → Shift_Val
Wb<15> → Wnd<15:15-Shift_Val + 1>
Wb<15:Shift_Val> → Wnd<15-Shift_Val:0>

Status Affected:

N, Z

Encoding:

1101

Description:

ASR

1110

Wb,

1www

#lit4,

wddd

Wnd

d100

kkkk

Arithmetic shift right the contents of the source register Wb by the 4-bit
unsigned literal, and store the result in the destination register Wnd. After
the shift is performed, the result is sign-extended. Direct addressing must
be used for Wb and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand.
Note:

Words:

1

Cycles:

1

Example 1:

ASR

This instruction operates in Word mode only.

W0, #0x4, W1

Before
Instruction
W0
060F
W1
1234
SR
0000
Example 2:

ASR

W0, #0x6, W1

Before
Instruction
W0
80FF
W1
0060
SR
0000
Example 3:

ASR

W0, #0xF, W1

© 2009 Microchip Technology Inc.

After
Instruction
W0 060F
W1
0060
SR
0000
; ASR W0 by 6 and store to W1

After
Instruction
W0 80FF
W1 FE03
SR
0008 (N = 1)
; ASR W0 by 15 and store to W1

After
Instruction
W0
70FF
W1
0000
SR
0002 (Z = 1)

5
Instruction
Descriptions

Before
Instruction
W0
70FF
W1 CC26
SR
0000

; ASR W0 by 4 and store to W1

DS70157D-page 113

16-bit MCU and DSC Programmer’s Reference Manual

ASR

Arithmetic Shift Right by Wns

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wns ∈ [W0 ...W15]
Wnd ∈ [W0 ... W15]

Operation:

Wns<3:0> → Shift_Val
Wb<15> → Wnd<15:15-Shift_Val + 1>
Wb<15:Shift_Val> → Wnd<15-Shift_Val:0>

Status Affected:

N, Z

Encoding:

ASR

1101

1110

Wns,

1www

Wnd

wddd

d000

ssss

Description:

Arithmetic shift right the contents of the source register Wb by the 4 Least
Significant bits of Wns (up to 15 positions) and store the result in the
destination register Wnd. After the shift is performed, the result is
sign-extended. Direct addressing must be used for Wb, Wns and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: If Wns is greater than 15, Wnd = 0x0 if Wb is positive, and
Wnd = 0xFFFF if Wb is negative.

Words:

1

Cycles:

1

Example 1:

ASR

W0, W5, W6

Before
Instruction
W0
80FF
W5
0004
W6
2633
SR
0000
Example 2:

ASR

W0, W5, W6

Before
Instruction
W0
6688
W5
000A
W6
FF00
SR
0000
Example 3:

ASR

W11, W12, W13

Before
Instruction
W11
8765
W12
88E4
W13
A5A5
SR
0000

DS70157D-page 114

Wb,

; ASR W0 by W5 and store to W6

After
Instruction
W0
80FF
W5
0004
W6
F80F
SR
0000
; ASR W0 by W5 and store to W6

After
Instruction
W0
6688
W5
000A
W6
0019
SR
0000
; ASR W11 by W12 and store to W13

After
Instruction
W11
8765
W12
88E4
W13
F876
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BCLR

Bit Clear f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for byte operation

Operation:

0 → f

Status Affected:

None

Encoding:

1010

Description:

BCLR{.B}

1001

f,

#bit4

bbbf

ffff

ffff

fffb

Clear the bit in the file register f specified by ‘bit4’. Bit numbering begins
with the Least Significant bit (bit 0) and advances to the Most Significant
bit (bit 7 for byte operations, bit 15 for word operations).
The ‘b’ bits select value bit4 of the bit position to be cleared.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BCLR.B 0x800, #0x7

Before
Instruction
Data 0800
66EF
SR
0000
Example 2:

BCLR

After
Instruction
Data 0800
666F
SR
0000

0x400, #0x9

Before
Instruction
Data 0400
AA55
SR
0000

; Clear bit 7 in 0x800

; Clear bit 9 in 0x400

After
Instruction
Data 0400
A855
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 115

16-bit MCU and DSC Programmer’s Reference Manual

BCLR

Bit Clear in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BCLR{.B}

Ws,

#bit4

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

0 → Ws

Status Affected:

None

Encoding:

1010

Description:

0001

bbbb

0B00

0ppp

ssss

Clear the bit in register Ws specified by ‘bit4’. Bit numbering begins with
the Least Significant bit (bit 0) and advances to the Most Significant bit (bit
7 for byte operations, bit 15 for word operations). Register direct or indirect addressing may be used for Ws.
The ‘b’ bits select value bit4 of the bit position to be cleared.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the source/destination register.
The ‘p’ bits select the source Address mode.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the source
register address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BCLR.B W2, #0x2

; Clear bit 3 in W2

Before
Instruction
W2
F234
SR
0000
Example 2:

BCLR

[W0++], #0x0

Before
Instruction
W0
2300
Data 2300
5607
SR
0000

DS70157D-page 116

After
Instruction
W2
F230
SR
0000
; Clear bit 0 in [W0]
; Post-increment W0

After
Instruction
W0
2302
Data 2300
5606
SR
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA

Branch Unconditionally

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation:

(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

BRA

0011

Expr

0111

nnnn

nnnn

nnnn

nnnn

Description:

The program will branch unconditionally, relative to the next PC. The offset
of the branch is the two’s complement number ‘2 * Slit16’, which supports
branches up to 32K instructions forward or backward. The Slit16 value is
resolved by the linker from the supplied label, absolute address or
expression. After the branch is taken, the new address will be (PC + 2) + 2 *
Slit16, since the PC will have incremented to fetch the next instruction.
The ‘n’ bits are a signed literal that specifies the number of program words
offset from (PC + 2).

Words:

1

Cycles:

2

Example 1:

002000 HERE:
002002
002004
002006
002008
00200A THERE:
00200C

PC
SR
Example 2:

Example 3:

BRA
. .
. .
. .
. .
. .
. .

THERE+0x2
.
.
.
.
.
.

; Branch to THERE+0x2

After
Instruction
PC
00 200C
SR
0000
BRA 0x1366
. . .
. . .

5

; Branch to 0x1366

Instruction
Descriptions

© 2009 Microchip Technology Inc.

Before
Instruction
00 2000
0000

; Branch to THERE

After
Instruction
PC
00 200A
SR
0000

Before
Instruction
00 2000
0000

002000 HERE:
002002
002004

PC
SR

THERE
.
.
.
.
.
.

Before
Instruction
00 2000
0000

002000 HERE:
002002
002004
002006
002008
00200A THERE:
00200C

PC
SR

BRA
. .
. .
. .
. .
. .
. .

After
Instruction
PC
00 1366
SR
0000

DS70157D-page 117

16-bit MCU and DSC Programmer’s Reference Manual

BRA

Computed Branch

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0110

0000

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]

Operation:

(PC + 2) + (2 * Wn) → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

BRA

0000

Description:

0001

Wn

0000

ssss

The program branches unconditionally, relative to the next PC. The offset
of the branch is the sign-extended 17-bit value (2 * Wn), which supports
branches up to 32K instructions forward or backward. After this instruction
executes, the new PC will be (PC + 2) + 2 * Wn, since the PC will have
incremented to fetch the next instruction.
The ‘s’ bits select the source register.

Words:

1

Cycles:

2

Example 1:

002000 HERE:
002002
...
...
002108
00210A TABLE7:
00210C

PC
W7
SR

DS70157D-page 118

Before
Instruction
00 2000
0084
0000

.
.
.
.
.
.

BRA W7
. .
. .
. .
. .
. .
. .

; Branch forward (2+2*W7)

After
Instruction
PC
00 210A
W7
0084
SR
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA C

Branch if Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = C
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:
Description:

0011

BRA

0001

C,

Expr

nnnn

nnnn

nnnn

nnnn

If the Carry flag bit is ‘1’, then the program will branch relative to the next PC.
The offset of the branch is the two’s complement number ‘2 * Slit16’, which
supports branches up to 32K instructions forward or backward. The Slit16
value is resolved by the linker from the supplied label, absolute address or
expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since the
PC will have incremented to fetch the next instruction. The instruction then
becomes a two-cycle instruction, with a NOP executed in the second cycle.
The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC + 2) in
instruction words.

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000
002002
002004
002006
002008
00200A
00200C
00200E

PC
SR

HERE:
NO_C:

CARRY:
THERE:

; If C is set, branch to CARRY
; Otherwise... continue

BRA C, CARRY
. . .
. . .
GOTO THERE
. . .
. . .
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

After
Instruction
00 2008
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 119

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

002000
002002
002004
002006
002008
00200A
00200C
00200E

PC
SR
Example 3:

Example 4:

THERE:

HERE:
NO_C:

CARRY:
THERE:

PC
SR

PC
SR

...
...
...
...
...
...
BRA C, CARRY
...

Before
Instruction
00 623C
0001 (C = 1)

After
Instruction
00 2002
0000
; If C is set, branch to CARRY
; Otherwise... continue

BRA C, CARRY
...
...
GOTO THERE
...
...
...
...

Before
Instruction
00 6230
0001 (C = 1)

006230 START:
006232
006234 CARRY:
006236
006238
00623A
00623C HERE:
00623E

PC
SR

DS70157D-page 120

CARRY:

; If C is set, branch to CARRY
; Otherwise... continue

BRA C, CARRY
...
...
GOTO THERE
...
...
...
...

Before
Instruction
00 2000
0000

006230
006232
006234
006236
006238
00623A
00623C
00623E

PC
SR

HERE:
NO_C:

After
Instruction
00 6238
0001 (C = 1)

; If C is set, branch to CARRY
; Otherwise... continue

PC
SR

After
Instruction
00 6234
0001 (C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA GE

Branch if Signed Greater Than or Equal

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = (N&&OV)||(!N&&!OV)
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

GE,

1101

Expr

nnnn

nnnn

nnnn

nnnn

If the logical expression (N&&OV)||(!N&&!OV) is true, then the program
will branch relative to the next PC. The offset of the branch is the two’s
complement number ‘2 * Slit16’, which supports branches up to 32K
instructions forward or backward. The Slit16 value is resolved by the
linker from the supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC + 2)
in instruction words.
Note:

The assembler will convert the specified label into the offset to
be used.

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

007600 LOOP:
007602
007604
007606
007608 HERE:
00760A NO_GE:

PC
SR
Example 2:

; If GE, branch to LOOP
; Otherwise... continue

After
Instruction
PC
00 7600
SR
0000
. .
. .
. .
. .
BRA
. .

.
.
.
.
GE, LOOP
.

Before
Instruction
00 7608
0008 (N = 1)

5
; If GE, branch to LOOP
; Otherwise... continue

After
Instruction
PC
00 760A
SR
0008 (N = 1)

DS70157D-page 121

Instruction
Descriptions

© 2009 Microchip Technology Inc.

.
.
.
.
GE, LOOP
.

Before
Instruction
00 7608
0000

007600 LOOP:
007602
007604
007606
007608 HERE:
00760A NO_GE:

PC
SR

. .
. .
. .
. .
BRA
. .

16-bit MCU and DSC Programmer’s Reference Manual

BRA GEU

Branch if Unsigned Greater Than or Equal

Implemented in:

PIC24F

PIC24H

X

X

X

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16 offset that supports an offset
range of [-32768 ... +32767] program words.

Operation:

Condition = C
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None
0011

Description:

0001

GEU,

X

Syntax:

Encoding:

BRA

dsPIC30F dsPIC33F

nnnn

Expr

nnnn

nnnn

nnnn

If the Carry flag is ‘1’, then the program will branch relative to the next
PC. The offset of the branch is the two’s complement number ‘2 *
Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label,
absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16,
since the PC will have incremented to fetch the next instruction. The
instruction then becomes a two-cycle instruction, with a NOP executed
in the second cycle.
The ‘n’ bits are a 16-bit signed literal that specify the offset from
(PC + 2) in instruction words.
Note:

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_GEU:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 122

This instruction is identical to the BRA C, Expr (Branch if
Carry) instruction and has the same encoding. It will reverse
assemble as BRA C, Slit16.

BRA GEU, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If C is set, branch
; to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0001 (C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA GT

Branch if Signed Greater Than

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = (!Z&&N&&OV)||(!Z&&!N&&!OV)
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1100

GT,

Expr

nnnn

nnnn

nnnn

nnnn

If the logical expression (!Z&&N&&OV)||(!Z&&!N&&!OV) is true, then the
program will branch relative to the next PC. The offset of the branch is the
two’s complement number ‘2 * Slit16’, which supports branches up to 32K
instructions forward or backward. The Slit16 value is resolved by the
linker from the supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC + 2)
in instruction words.

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_GT:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA GT, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If GT, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 123

16-bit MCU and DSC Programmer’s Reference Manual

BRA GTU

Branch if Unsigned Greater Than

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = (C&&!Z)
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1110

GTU,

Expr

nnnn

nnnn

nnnn

nnnn

If the logical expression (C&&!Z) is true, then the program will branch
relative to the next PC. The offset of the branch is the two’s complement
number ‘2 * Slit16’, which supports branches up to 32K instructions
forward or backward. The Slit16 value is resolved by the linker from the
supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_GTU:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 124

BRA GTU, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If GTU, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0001 (C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA LE

Branch if Signed Less Than or Equal

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = Z||(N&&!OV)||(!N&&OV)
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

0100

LE,

Expr

nnnn

nnnn

nnnn

nnnn

If the logical expression (Z||(N&&!OV)||(!N&&OV)) is true, then the
program will branch relative to the next PC. The offset of the branch is the
two’s complement number ‘2 * Slit16’, which supports branches up to 32K
instructions forward or backward. The Slit16 value is resolved by the linker
from the supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_LE:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA LE, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If LE, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 125

16-bit MCU and DSC Programmer’s Reference Manual

BRA LEU

Branch if Unsigned Less Than or Equal

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = !C||Z
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

0110

LEU,

nnnn

Expr

nnnn

nnnn

nnnn

If the logical expression (!C||Z) is true, then the program will branch
relative to the next PC. The offset of the branch is the two’s complement
number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the
supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_LEU:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 126

BRA LEU, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If LEU, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0001 (C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA LT

Branch if Signed Less Than

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = (N&&!OV)||(!N&&OV)
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

0101

LT,

Expr

nnnn

nnnn

nnnn

nnnn

If the logical expression ( (N&&!OV)||(!N&&OV) ) is true, then the program
will branch relative to the next PC. The offset of the branch is the two’s
complement number ‘2 * Slit16’, which supports branches up to 32K
instructions forward or backward. The Slit16 value is resolved by the
linker from the supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_LT:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA LT, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

; If LT, branch to BYPASS
; Otherwise... continue

After
Instruction
PC
00 2002
SR
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 127

16-bit MCU and DSC Programmer’s Reference Manual

BRA LTU

Branch if Unsigned Less Than

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = !C
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1001

LTU,

nnnn

Expr

nnnn

nnnn

nnnn

If the Carry flag is ‘0’, then the program will branch relative to the next PC.
The offset of the branch is the two’s complement number ‘2 * Slit16’,
which supports branches up to 32K instructions forward or backward. The
Slit16 value is resolved by the linker from the supplied label, absolute
address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).
Note:

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_LTU:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 128

This instruction is identical to the BRA NC, Expr (Branch if Not
Carry) instruction and has the same encoding. It will reverse
assemble as BRA NC, Slit16.

BRA LTU, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If LTU, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
0001 (C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA N

Branch if Negative

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = N
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register.

Status Affected:

None

Encoding:

0011

Description:

BRA

0011

N,

Expr

nnnn

nnnn

nnnn

nnnn

If the Negative flag is ‘1’, then the program will branch relative to the next
PC. The offset of the branch is the two’s complement number ‘2 * Slit16’,
which supports branches up to 32K instructions forward or backward. The
Slit16 value is resolved by the linker from the supplied label, absolute
address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_N:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA N, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0008 (N = 1)

PC
SR

; If N, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 129

16-bit MCU and DSC Programmer’s Reference Manual

BRA NC

Branch if Not Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = !C
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1001

NC,

nnnn

Expr

nnnn

nnnn

nnnn

If the Carry flag is ‘0’, then the program will branch relative to the next PC.
The offset of the branch is the two’s complement number ‘2 * Slit16’, which
supports branches up to 32K instructions forward or backward. The Slit16
value is resolved by the linker from the supplied label, absolute address or
expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_NC:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 130

BRA NC, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0001 (C = 1)

PC
SR

; If NC, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
0001 (C = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA NN

Branch if Not Negative

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = !N
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1011

NN,

Expr

nnnn

nnnn

nnnn

nnnn

If the Negative flag is ‘0’, then the program will branch relative to the next
PC. The offset of the branch is the two’s complement number ‘2 * Slit16’,
which supports branches up to 32K instructions forward or backward. The
Slit16 value is resolved by the linker from the supplied label, absolute
address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_NN:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

Before
Instruction
00 2000
0000

BRA NN, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

PC
SR

; If NN, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 131

16-bit MCU and DSC Programmer’s Reference Manual

BRA NOV

Branch if Not Overflow

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = !OV
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1000

NOV,

nnnn

Expr

nnnn

nnnn

nnnn

If the Overflow flag is ‘0’, then the program will branch relative to the next
PC. The offset of the branch is the two’s complement number ‘2 * Slit16’,
which supports branches up to 32K instructions forward or backward. The
Slit16 value is resolved by the linker from the supplied label, absolute
address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_NOV:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 132

BRA NOV, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0008 (N = 1)

PC
SR

; If NOV, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0008 (N = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA NZ

Branch if Not Zero

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = !Z
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

1010

NZ,

Expr

nnnn

nnnn

nnnn

nnnn

If the Z flag is ‘0’, then the program will branch relative to the next PC. The
offset of the branch is the two’s complement number ‘2 * Slit16’, which
supports branches up to 32K instructions forward or backward. The Slit16
value is resolved by the linker from the supplied label, absolute address or
expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_NZ:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA NZ, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0002 (Z = 1)

PC
SR

; If NZ, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
0002 (Z = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 133

16-bit MCU and DSC Programmer’s Reference Manual

BRA OA

Branch if Overflow Accumulator A

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = OA
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

BRA

dsPIC30F

1100

OA,

nnnn

Expr

nnnn

nnnn

nnnn

If the Overflow Accumulator A flag is ‘1’, then the program will branch
relative to the next PC. The offset of the branch is the two’s complement
number ‘2 * Slit16’, which supports branches up to 32K instructions
forward or backward. The Slit16 value is resolved by the linker from the
supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).
Note:

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_OA:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 134

The assembler will convert the specified label into the offset to
be used.

BRA OA, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
PC
8800 (OA, OAB = 1) SR

; If OA, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
8800 (OA, OAB = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA OB

Branch if Overflow Accumulator B

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = OB
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

BRA

dsPIC30F

1101

OB,

nnnn

Expr

nnnn

nnnn

nnnn

If the Overflow Accumulator B flag is ‘1’, then the program will branch
relative to the next PC. The offset of the branch is the two’s complement
number ‘2 * Slit16’, which supports branches up to 32K instructions
forward or backward. The Slit16 value is resolved by the linker from the
supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_OB:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA OB, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
PC
8800 (OA, OAB = 1) SR

; If OB, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
8800 (OA, OAB = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 135

16-bit MCU and DSC Programmer’s Reference Manual

BRA OV

Branch if Overflow

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = OV
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0011

Description:

BRA

0000

OV,

nnnn

Expr

nnnn

nnnn

nnnn

If the Overflow flag is ‘1’, then the program will branch relative to the next
PC. The offset of the branch is the two’s complement number ‘2 * Slit16’,
which supports branches up to 32K instructions forward or backward. The
Slit16 value is resolved by the linker from the supplied label, absolute
address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_OV
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 136

BRA OV, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0002 (Z = 1)

PC
SR

; If OV, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
0002 (Z = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA SA

Branch if Saturation Accumulator A

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = SA
If (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

BRA

dsPIC30F

1110

SA,

nnnn

Expr

nnnn

nnnn

nnnn

If the Saturation Accumulator A flag is ‘1’, then the program will branch
relative to the next PC. The offset of the branch is the two’s complement
number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_SA:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA SA, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
PC
2400 (SA, SAB = 1) SR

; If SA, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
2400 (SA, SAB = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 137

16-bit MCU and DSC Programmer’s Reference Manual

BRA SB

Branch if Saturation Accumulator B

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].

Operation:

Condition = SB
if (Condition)
(PC + 2) + 2 * Slit16→ PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

BRA

dsPIC30F

1111

SB,

Expr

nnnn

nnnn

nnnn

nnnn

If the Saturation Accumulator B flag is ‘1’, then the program will branch
relative to the next PC. The offset of the branch is the two’s complement
number ‘2 * Slit16’, which supports branches up to 32K instructions
forward or backward. The Slit16 value is resolved by the linker from the
supplied label, absolute address or expression.
If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words:

1

Cycles:

1 (2 if branch taken)

Example 1:

002000 HERE:
002002 NO_SB:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

DS70157D-page 138

Before
Instruction
00 2000
0000

BRA SB, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

PC
SR

; If SB, branch to BYPASS
; Otherwise... continue

After
Instruction
00 2002
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BRA Z

Branch if Zero

Implemented in:

PIC24F
X

PIC24H
X

dsPIC33F
X

Z,

Expr

Syntax:

{label:}

Operands:

Expr may be a label, absolute address or expression.
Expr is resolved by the linker to a Slit16, where
Slit16 ∈ [-32768 ... +32767].
Condition = Z
if (Condition)
(PC + 2) + 2 * Slit16 → PC
NOP → Instruction Register
None
0011
0010
nnnn
nnnn
nnnn
nnnn
If the Zero flag is ‘1’, then the program will branch relative to the next PC.
The offset of the branch is the two’s complement number ‘2 * Slit16’, which
supports branches up to 32K instructions forward or backward. The Slit16
value is resolved by the linker from the supplied label, absolute address or
expression.

Operation:

Status Affected:
Encoding:
Description:

BRA

dsPIC30F
X

If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since
the PC will have incremented to fetch the next instruction. The instruction
then becomes a two-cycle instruction, with a NOP executed in the second
cycle.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 2).
1
1 (2 if branch taken)

Words:
Cycles:
Example 1:

002000 HERE:
002002 NO_Z:
002004
002006
002008
00200A
00200C BYPASS:
00200E

PC
SR

BRA Z, BYPASS
. . .
. . .
. . .
. . .
GOTO THERE
. . .
. . .

Before
Instruction
00 2000
0002 (Z = 1)

PC
SR

; If Z, branch to BYPASS
; Otherwise... continue

After
Instruction
00 200C
0002 (Z = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 139

16-bit MCU and DSC Programmer’s Reference Manual

BSET

Bit Set f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

1 → f

Status Affected:

None

Encoding:

1010

Description:

BSET{.B}

1000

f,

#bit4

bbbf

ffff

ffff

fffb

Set the bit in the file register ‘f’ specified by ‘bit4’. Bit numbering begins
with the Least Significant bit (bit 0) and advances to the Most Significant
bit (bit 7 for byte operations, bit 15 for word operations).
The ‘b’ bits select value bit4 of the bit position to be set.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BSET.B

0x601, #0x3

Before
Instruction
Data 0600
F234
SR
0000
Example 2:

BSET

DS70157D-page 140

After
Instruction
Data 0600 FA34
SR 0000

0x444, #0xF

Before
Instruction
Data 0444
5604
SR
0000

; Set bit 3 in 0x601

; Set bit 15 in 0x444

After
Instruction
Data 0444 D604
SR 0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BSET

Bit Set in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BSET{.B}

Ws,

#bit4

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

1 → Ws

Status Affected:

None

Encoding:
Description:

1010

0000

bbbb

0B00

0ppp

ssss

Set the bit in register Ws specified by ‘bit4’. Bit numbering begins with the
Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7
for byte operations, bit 15 for word operations). Register direct or indirect
addressing may be used for Ws.
The ‘b’ bits select value bit4 of the bit position to be cleared.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source/destination register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the source
register address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BSET.B W3, #0x7

; Set bit 7 in W3

Before
Instruction
W3
0026
SR
0000
Example 2:

BSET

[W4++], #0x0

5

; Set bit 0 in [W4]
; Post-increment W4

Instruction
Descriptions

Before
Instruction
W4
6700
Data 6700
1734
SR
0000

© 2009 Microchip Technology Inc.

After
Instruction
W3 00A6
SR
0000

After
Instruction
W4
6702
Data 6700
1735
SR
0000

DS70157D-page 141

16-bit MCU and DSC Programmer’s Reference Manual

BSW

Bit Write in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BSW.C
BSW.Z

Ws,

Wb

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],

Operands:

Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]

Operation:

For “.C” operation:
C → Ws<(Wb)>
For “.Z” operation (default):
Z → Ws<(Wb)>

Status Affected:

None

Encoding:
Description:

1010

1101

Zwww

w000

0ppp

ssss

The (Wb) bit in register Ws is written with the value of the C or Z flag from
the STATUS register. Bit numbering begins with the Least Significant bit
(bit 0) and advances to the Most Significant bit (bit 15) of the working
register. Only the four Least Significant bits of Wb are used to determine
the destination bit number. Register direct addressing must be used for
Wb, and either register direct, or indirect addressing may be used for Ws.
The ‘Z’ bit selects the C or Z flag as source.
The ‘w’ bits select the address of the bit select register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

BSW.C

W2, W3

This instruction only operates in Word mode. If no extension is
provided, the “.Z” operation is assumed.

; Set bit W3 in W2 to the value
; of the C bit

Before
After
Instruction
Instruction
W2
F234
W2 7234
W3
111F
W3
111F
SR
0002 (Z = 1, C = 0) SR 0002 (Z = 1, C = 0)

DS70157D-page 142

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Example 2:

BSW.Z

W2, W3

; Set bit W3 in W2 to the complement
; of the Z bit

Before
After
Instruction
Instruction
W2
E235
W2
E234
W3
0550
W3
0550
SR
0002 (Z = 1, C = 0) SR
0002 (Z = 1, C = 0)
Example 3:

BSW.C

[++W0], W6

; Set bit W6 in [W0++] to the value
; of the C bit

Before
After
Instruction
Instruction
W0
1000
W0
1002
W6
34A3
W6 34A3
Data 1002
2380
Data 1002
2388
SR
0001 (Z = 0, C = 1) SR
0001 (Z = 0, C = 1)
Example 4:

BSW

[W1--], W5

; Set bit W5 in [W1] to the
; complement of the Z bit
; Post-decrement W1

Before
After
Instruction
Instruction
W1
1000
W1 0FFE
W5
888B
W5 888B
Data 1000 C4DD
Data 1000 CCDD
SR
0001 (C = 1)
SR
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 143

16-bit MCU and DSC Programmer’s Reference Manual

BTG

Bit Toggle f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

(f) → (f)

Status Affected:

None

Encoding:

1010

Description:

BTG{.B}

1010

f,

#bit4

bbbf

ffff

ffff

fffb

Bit ‘bit4’ in file register ‘f’ is toggled (complemented). For the bit4
operand, bit numbering begins with the Least Significant bit (bit 0) and
advances to the Most Significant bit (bit 7 for byte operation, bit 15 for
word operation) of the byte.
The ‘b’ bits select value bit4, the bit position to toggle.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BTG.B

0x1001, #0x4

Before
Instruction
Data 1000
F234
SR
0000
Example 2:

BTG

DS70157D-page 144

After
Instruction
Data 1000 E234
SR
0000

0x1660, #0x8

Before
Instruction
Data 1660
5606
SR
0000

; Toggle bit 4 in 0x1001

; Toggle bit 8 in RAM660

After
Instruction
Data 1660
5706
SR
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BTG

Bit Toggle in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BTG{.B}

Ws,

#bit4

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

(Ws) → Ws

Status Affected:

None

Encoding:

1010

Description:

0010

bbbb

0B00

0ppp

ssss

Bit ‘bit4’ in register Ws is toggled (complemented). For the bit4 operand,
bit numbering begins with the Least Significant bit (bit 0) and advances to
the Most Significant bit (bit 7 for byte operations, bit 15 for word
operations). Register direct or indirect addressing may be used for Ws.
The ‘b’ bits select value bit4, the bit position to test.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the source/destination register.
The ‘p’ bits select the source Address mode.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the source
register address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BTG

W2, #0x0

; Toggle bit 0 in W2

Before
Instruction
W2
F234
SR
0000
Example 2:

BTG

[W0++], #0x0

5

; Toggle bit 0 in [W0]
; Post-increment W0

Instruction
Descriptions

Before
Instruction
W0
2300
Data 2300
5606
SR
0000

© 2009 Microchip Technology Inc.

After
Instruction
W2
F235
SR
0000

After
Instruction
W0
2302
Data 2300
5607
SR
0000

DS70157D-page 145

16-bit MCU and DSC Programmer’s Reference Manual

BTSC

Bit Test f, Skip if Clear

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

Test (f), skip if clear

Status Affected:

None

Encoding:

1010

Description:

BTSC{.B}

1111

f,

#bit4

bbbf

ffff

ffff

fffb

Bit ‘bit4’ in the file register is tested. If the tested bit is ‘0’, the next
instruction (fetched during the current instruction execution) is discarded
and on the next cycle, a NOP is executed instead. If the tested bit is ‘1’,
the next instruction is executed as normal. In either case, the contents of
the file register are not changed. For the bit4 operand, bit numbering
begins with the Least Significant bit (bit 0) and advances to the Most
Significant bit (bit 7 for byte operations, bit 15 for word operations).
The ‘b’ bits select value bit4, the bit position to test.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1 (2 or 3)

Example 1:

002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A

PC
Data 1200
SR

DS70157D-page 146

Before
Instruction
00 2000
264F
0000

BTSC.B
GOTO
. . .
. . .
. . .
. . .

0x1201, #2
BYPASS

; If bit 2 of 0x1201 is 0,
; skip the GOTO

After
Instruction
PC
00 2002
Data 1200
264F
SR
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Example 2:

002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A

PC
Data 0804
SR

Before
Instruction
00 2000
2647
0000

BTSC
GOTO
. . .
. . .
. . .
. . .

0x804, #14
BYPASS

; If bit 14 of 0x804 is 0,
; skip the GOTO

After
Instruction
PC
00 2004
Data 0804
2647
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 147

16-bit MCU and DSC Programmer’s Reference Manual

BTSC

Bit Test Ws, Skip if Clear

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BTSC

Ws,

#bit4

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]

Operands:
Operation:

Test (Ws), skip if clear

Status Affected:

None

Encoding:

1010

Description:

0111

bbbb

0000

0ppp

ssss

Bit ‘bit4’ in Ws is tested. If the tested bit is ‘0’, the next instruction (fetched
during the current instruction execution) is discarded and on the next
cycle, a NOP is executed instead. If the tested bit is ‘1’, the next instruction
is executed as normal. In either case, the contents of Ws are not changed.
For the bit4 operand, bit numbering begins with the Least Significant bit
(bit 0) and advances to the Most Significant bit (bit 15) of the word. Either
register direct or indirect addressing may be used for Ws.
The ‘b’ bits select value bit4, the bit position to test.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1 (2 or 3 if the next instruction is skipped)

Example 1:

002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A

PC
W0
SR

DS70157D-page 148

This instruction operates in Word mode only.

Before
Instruction
00 2000
264F
0000

BTSC
GOTO
. . .
. . .
. . .
. . .

W0, #0x0
BYPASS

; If bit 0 of W0 is 0,
; skip the GOTO

After
Instruction
PC
00 2002
W0
264F
SR
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions
Example 2:

002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A

PC
W6
SR
Example 3:

Before
Instruction
00 2000
264F
0000

003400 HERE:
003402
003404
003406
003408 BYPASS:
00340A

PC
W6
Data 1800
SR

BTSC
GOTO
. . .
. . .
. . .
. . .

Before
Instruction
00 3400
1800
1000
0000

PC
W6
SR
BTSC
GOTO
. . .
. . .
. . .
. . .

; If bit 15 of W6 is 0,
; skip the GOTO

W6, #0xF
BYPASS

After
Instruction
00 2004
264F
0000

[W6++], #0xC
BYPASS

PC
W6
Data 1800
SR

; If bit 12 of [W6] is 0,
; skip the GOTO
; Post-increment W6

After
Instruction
00 3402
1802
1000
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 149

16-bit MCU and DSC Programmer’s Reference Manual

BTSS

Bit Test f, Skip if Set

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

Test (f), skip if set

Status Affected:

None

Encoding:

BTSS{.B}

1010

Description:

1110

f,

#bit4

bbbf

ffff

ffff

fffb

Bit ‘bit4’ in the file register ‘f’ is tested. If the tested bit is ‘1’, the next
instruction (fetched during the current instruction execution) is discarded
and on the next cycle, a NOP is executed instead. If the tested bit is ‘0’, the
next instruction is executed as normal. In either case, the contents of the
file register are not changed. For the bit4 operand, bit numbering begins
with the Least Significant bit (bit 0) and advances to the Most Significant
bit (bit 7 for byte operation, bit 15 for word operation).
The ‘b’ bits select value bit4, the bit position to test.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1 (2 or 3 if the next instruction is skipped)

Example 1:

007100 HERE:
007102
007104

PC
Data 1400
SR
Example 2:

DS70157D-page 150

Before
Instruction
00 7100
0280
0000

007100 HERE:
007102
007104
007106 BYPASS:

PC
Data 0890
SR

BTSS.B
CLR
. . .

Before
Instruction
00 7100
00FE
0000

0x1401, #0x1
WREG

PC
Data 1400
SR
BTSS
GOTO
. . .
. . .

After
Instruction
00 7104
0280
0000

0x890, #0x9
BYPASS

PC
Data 0890
SR

; If bit 1 of 0x1401 is 1,
; don’t clear WREG

; If bit 9 of 0x890 is 1,
; skip the GOTO

After
Instruction
00 7102
00FE
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BTSS

Bit Test Ws, Skip if Set

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BTSS

Ws,

#bit4

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]

Operation:

Test (Ws), skip if set.

Status Affected:

None

Encoding:

1010

Description:

0110

bbbb

0000

0ppp

ssss

Bit ‘bit4’ in Ws is tested. If the tested bit is ‘1’, the next instruction (fetched
during the current instruction execution) is discarded and on the next
cycle, a NOP is executed instead. If the tested bit is ‘0’, the next instruction
is executed as normal. In either case, the contents of Ws are not changed.
For the bit4 operand, bit numbering begins with the Least Significant bit
(bit 0) and advances to the Most Significant bit (bit 15) of the word. Either
register direct or indirect addressing may be used for Ws.
The ‘b’ bits select the value bit4, the bit position to test.
The ‘s’ bits select the source register.
The ‘p’ bits select the source Address mode.
Note:

This instruction operates in Word mode only.

Words:

1

Cycles:

1 (2 or 3 if the next instruction is skipped)

Example 1:

002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A

PC
W0
SR

Before
Instruction
00 2000
264F
0000

BTSS
GOTO
. . .
. . .
. . .
. . .

W0, #0x0
BYPASS

; If bit 0 of W0 is 1,
; skip the GOTO

After
Instruction
PC
00 2004
W0
264F
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 151

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

002000 HERE:
002002
002004
002006
002008 BYPASS:
00200A

PC
W6
SR
Example 3:

DS70157D-page 152

Before
Instruction
00 2000
264F
0000

003400 HERE:
003402
003404
003406
003408 BYPASS:
00340A

PC
W6
Data 1800
SR

BTSS
GOTO
. . .
. . .
. . .
. . .

Before
Instruction
00 3400
1800
1000
0000

PC
W6
SR
BTSS
GOTO
. . .
. . .
. . .
. . .

; If bit 15 of W6 is 1,
; skip the GOTO

W6, #0xF
BYPASS

After
Instruction
00 2002
264F
0000

[W6++], 0xC
BYPASS

PC
W6
Data 1800
SR

; If bit 12 of [W6] is 1,
; skip the GOTO
; Post-increment W6

After
Instruction
00 3404
1802
1000
0000

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BTST

Bit Test f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

(f) → Z

Status Affected:

Z

Encoding:

1010

Description:

BTST{.B}

1011

f,

#bit4

bbbf

ffff

ffff

fffb

Bit ‘bit4’ in file register ‘f’ is tested and the complement of the tested bit is
stored to the Z flag in the STATUS register. The contents of the file
register are not changed. For the bit4 operand, bit numbering begins with
the Least Significant bit (bit 0) and advances to the Most Significant bit
(bit 7 for byte operation, bit 15 for word operation).
The ‘b’ bits select value bit4, the bit position to be tested.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.

Words:

1

Cycles:

1

Example 1:

BTST.B

0x1201, #0x3

Before
Instruction
Data 1200
F7FF
SR
0000
Example 2:

BTST

; Set Z = complement of
; bit 3 in 0x1201

After
Instruction
Data 1200 F7FF
SR
0002 (Z = 1)

0x1302, #0x7

; Set Z = complement of
; bit 7 in 0x1302

Before
After
Instruction
Instruction
Data 1302
F7FF
Data 1302 F7FF
SR
0002 (Z = 1)
SR 0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 153

16-bit MCU and DSC Programmer’s Reference Manual

BTST

Bit Test in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BTST.C

Ws,

BTST.Z

[Ws],

#bit4

[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]

Operation:

For “.C” operation:
(Ws) → C
For “.Z” operation (default):
(Ws) → Z

Status Affected:

Z or C

Encoding:
Description:

1010

0011

bbbb

Z000

0ppp

ssss

Bit ‘bit4’ in register Ws is tested. If the “.Z” option of the instruction is
specified, the complement of the tested bit is stored to the Zero flag in the
STATUS register. If the “.C” option of the instruction is specified, the value
of the tested bit is stored to the Carry flag in the STATUS register. In either
case, the contents of Ws are not changed.
For the bit4 operand, bit numbering begins with the Least Significant bit
(bit 0) and advances to the Most Significant bit (bit 15) of the word. Either
register direct or indirect addressing may be used for Ws.
The ‘b’ bits select value bit4, the bit position to test.
The ‘Z’ bit selects the C or Z flag as destination.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

BTST.C

This instruction only operates in Word mode. If no extension is
provided, the “.Z” operation is assumed.

[W0++], #0x3

; Set C = bit 3 in [W0]
; Post-increment W0

Before
After
Instruction
Instruction
W0
1200
W0
1202
Data 1200
FFF7
Data 1200 FFF7
SR
0001 (C = 1)
SR
0000
Example 2:

BTST.Z

W0, #0x7

Before
Instruction
W0
F234
SR
0000

DS70157D-page 154

; Set Z = complement of bit 7 in W0

After
Instruction
W0
F234
SR
0002 (Z = 1)

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BTST

Bit Test in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BTST.C
BTST.Z

Ws,

Wb

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],

Operands:

Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]

Operation:

For “.C” operation:
(Ws)<(Wb)> → C
For “.Z” operation (default):
(Ws)<(Wb)> → Z

Status Affected:

Z or C

Encoding:
Description:

1010

0101

Zwww

w000

0ppp

ssss

The (Wb) bit in register Ws is tested. If the “.C” option of the instruction is
specified, the value of the tested bit is stored to the Carry flag in the
STATUS register. If the “.Z” option of the instruction is specified, the
complement of the tested bit is stored to the Zero flag in the STATUS
register. In either case, the contents of Ws are not changed.
Only the four Least Significant bits of Wb are used to determine the bit
number. Bit numbering begins with the Least Significant bit (bit 0) and
advances to the Most Significant bit (bit 15) of the working register.
Register direct or indirect addressing may be used for Ws.
The ‘Z’ bit selects the C or Z flag as destination.
The ‘w’ bits select the address of the bit select register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

BTST.C

This instruction only operates in Word mode. If no extension is
provided, the “.Z” operation is assumed.

W2, W3

© 2009 Microchip Technology Inc.

After
Instruction
W2 F234
W3 2368
SR 0000

5
Instruction
Descriptions

Before
Instruction
W2
F234
W3
2368
SR
0001 (C = 1)

; Set C = bit W3 of W2

DS70157D-page 155

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

BTST.Z

[W0++], W1

; Set Z = complement of
; bit W1 in [W0],
; Post-increment W0

Before
After
Instruction
Instruction
W0
1200
W0 1202
W1 CCC0
W1 CCC0
Data 1200
6243
Data 1200 6243
SR
0002 (Z = 1)
SR 0000

DS70157D-page 156

© 2009 Microchip Technology Inc.

Section 5. Instruction Descriptions

BTSTS

Bit Test/Set f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191] for byte operation
f ∈ [0 ... 8190] (even only) for word operation
bit4 ∈ [0 ... 7] for byte operation
bit4 ∈ [0 ... 15] for word operation

Operation:

(f) → Z
1 → (f)

Status Affected:

Z

Encoding:

1010

Description:

BTSTS{.B} f,

1100

#bit4

bbbf

ffff

ffff

fffb

Bit ‘bit4’ in file register ‘f’ is tested and the complement of the tested bit is
stored to the Zero flag in the STATUS register. The tested bit is then set
to ‘1’ in the file register. For the bit4 operand, bit numbering begins with
the Least Significant bit (bit 0) and advances to the Most Significant bit
(bit 7 for byte operations, bit 15 for word operations).
The ‘b’ bits select value bit4, the bit position to test/set.
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: When this instruction operates in Word mode, the file register
address must be word-aligned.
3: When this instruction operates in Byte mode, ‘bit4’ must be
between 0 and 7.
4: The file register ‘f’ must not be the CPU Status (SR) register.

Words:

1

Cycles:

1

Example 1:

BTSTS.B

0x1201, #0x3 ; Set Z = complement of bit 3 in 0x1201,
; then set bit 3 of 0x1201 = 1

Before
Instruction
Data 1200
F7FF
SR
0000
Example 2:

BTSTS

After
Instruction
Data 1200 FFFF
SR
0002 (Z = 1)

0x808, #15

; Set Z = complement of bit 15 in 0x808,
; then set bit 15 of 0x808 = 1

5

© 2009 Microchip Technology Inc.

Instruction
Descriptions

Before
After
Instruction
Instruction
RAM300
8050
RAM300
8050
SR
0002 (Z = 1)
SR
0000

DS70157D-page 157

16-bit MCU and DSC Programmer’s Reference Manual

BTSTS

Bit Test/Set in Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

BTSTS.C
BTSTS.Z

Ws,

#bit4

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],

Operands:

Ws ∈ [W0 ... W15]
bit4 ∈ [0 ... 15]

Operation:

For “.C” operation:
(Ws) → C
1 → Ws
For “.Z” operation (default):
(Ws) → Z
1 → Ws

Status Affected:

Z or C

Encoding:
Description:

1010

0100

bbbb

Z000

0ppp

ssss

Bit ‘bit4’ in register Ws is tested. If the “.Z” option of the instruction is
specified, the complement of the tested bit is stored to the Zero flag in the
STATUS register. If the “.C” option of the instruction is specified, the value
of the tested bit is stored to the Carry flag in the STATUS register. In both
cases, the tested bit in Ws is set to ‘1’.
The ‘b’ bits select the value bit4, the bit position to test/set.
The ‘Z’ bit selects the C or Z flag as destination.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction only operates in Word mode. If no extension is
provided, the “.Z” operation is assumed.
2: If Ws is used as a pointer, it must not contain the address of the
CPU Status (SR) register.

Words:

1

Cycles:

1

Example 1:

BTSTS.C

[W0++], #0x3

; Set C = bit 3 in [W0]
; Set bit 3 in [W0] = 1
; Post-increment W0

Before
After
Instruction
Instruction
W0
1200
W0
1202
Data 1200
FFF7
Data 1200
FFFF
SR
0001 (C = 1)
SR
0000
Example 2:

BTSTS.Z

W0, #0x7

Before
Instruction
W0
F234
SR
0000

DS70157D-page 158

; Set Z = complement of bit 7
; in W0, and set bit 7 in W0 = 1

After
Instruction
W0 F2BC
SR
0002 (Z = 1)

© 2009 Microchip Technology Inc.

CALL

Call Subroutine

Implemented in:

PIC24F
X

PIC24H
X

dsPIC33F
X

Syntax:

{label:}

Operands:

Expr may be a label or expression (but not a literal).
Expr is resolved by the linker to a lit23, where lit23 ∈ [0 ... 8388606].
(PC) + 4 → PC
(PC<15:0>) → (TOS)
(W15) + 2 → W15
(PC<23:16>) → (TOS)
(W15) + 2 → W15
lit23 → PC
NOP → Instruction Register
None

Operation:

Status Affected:
Encoding:
1st word
2nd word
Description:

CALL

dsPIC30F
X
Expr

0000
0010
nnnn
nnnn
nnnn
nnn0
0000
0000
0000
0000
0nnn
nnnn
Direct subroutine call over the entire 4-Mbyte instruction program
memory range. Before the CALL is made, the 24-bit return address
(PC + 4) is PUSHed onto the stack. After the return address is
stacked, the 23-bit value ‘lit23’ is loaded into the PC.
The ‘n’ bits form the target address.
Note:

Words:
Cycles:

The linker will resolve the specified expression into the lit23 to
be used.

2
2

Example 1:

026000
026004
.
.
026844 _FIR:
026846

PC
W15
Data A268
Data A26A
SR

Before
Instruction
02 6000
A268
FFFF
FFFF
0000

CALL
MOV
...
...
MOV
...

_FIR
W0, W1

#0x400, W2

PC
W15
Data A268
Data A26A
SR

; Call _FIR subroutine

; _FIR subroutine start

After
Instruction
02 6844
A26C
6004
0002
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 159

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

072000
072004
.
077A28 _G66:
077A2A
077A2C

PC
W15
Data 9004
Data 9006
SR

DS70157D-page 160

Before
Instruction
07 2000
9004
FFFF
FFFF
0000

CALL
MOV
...
INC
...

_G66
W0, W1

; call routine _G66

W6, [W7++]

; routine start

PC
W15
Data 9004
Data 9006
SR

After
Instruction
07 7A28
9008
2004
0007
0000

© 2009 Microchip Technology Inc.

CALL

Call Indirect Subroutine

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0000

0000

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]

Operation:

(PC) + 2 → PC
(PC<15:0>) → TOS
(W15) + 2 → W15
(PC<23:16>) → TOS
(W15) + 2 → W15
0 → PC<22:16>
(Wn<15:1>) → PC<15:1>
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

CALL

Wn

0001

0000

ssss

Indirect subroutine call over the first 32K instructions of program memory.
Before the CALL is made, the 24-bit return address (PC + 2) is PUSHed
onto the stack. After the return address is stacked, Wn<15:1> is loaded
into PC<15:1> and PC<22:16> is cleared. Since PC<0> is always ‘0’,
Wn<0> is ignored.
The ‘s’ bits select the source register.

Words:

1

Cycles:

2

Example
1:

001002
001004
.
001600 _BOOT:
001602
.

PC
W0
W15
Data 6F00
Data 6F02
SR

Before
Instruction
00 1002
1600
6F00
FFFF
FFFF
0000

CALL W0
...
...
MOV #0x400, W2
MOV #0x300, W6
...

PC
W0
W15
Data 6F00
Data 6F02
SR

; Call BOOT subroutine indirectly
; using W0
; _BOOT starts here

After
Instruction
00 1600
1600
6F04
1004
0000
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 161

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

004200
004202
.
005500 _TEST:
005502
.

PC
W7
W15
Data 6F00
Data 6F02
SR

DS70157D-page 162

Before
Instruction
00 4200
5500
6F00
FFFF
FFFF
0000

CALL
...
...
INC
DEC
...

W7

; Call TEST subroutine indirectly
; using W7

W1, W2
W1, W3

; _TEST starts here
;

PC
W7
W15
Data 6F00
Data 6F02
SR

After
Instruction
00 5500
5500
6F04
4202
0000
0000

© 2009 Microchip Technology Inc.

CLR

Clear f or WREG

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

CLR{.B}

f
WREG

Operands:

f ∈ [0 ... 8191]

Operation:

0 → destination designated by D

Status Affected:

None

Encoding:
Description:

1110

1111

0BDf

ffff

ffff

ffff

Clear the contents of a file register or the default working register WREG.
If WREG is specified, the WREG is cleared. Otherwise, the specified file
register ‘f’ is cleared.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

CLR.B

RAM200

Before
Instruction
RAM200 8009
SR 0000
Example 2:

CLR

WREG

Before
Instruction
WREG
0600
SR
0000

; Clear RAM200 (Byte mode)

After
Instruction
RAM200 8000
SR 0000
; Clear WREG (Word mode)

After
Instruction
WREG
0000
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 163

16-bit MCU and DSC Programmer’s Reference Manual

CLR

Clear Wd

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

CLR{.B}

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wd ∈ [W0 ... W15]

Operation:

0 → Wd

Status Affected:

None

Encoding:

1110

Description:

1011

0Bqq

qddd

d000

0000

Clear the contents of register Wd. Either register direct or indirect
addressing may be used for Wd.
The ‘B’ bit select byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
Note:

Words:

1

Cycles:

1

Example 1:

CLR.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W2

Before
Instruction
W2 3333
SR 0000
Example 2:

CLR

[W0++]

Before
Instruction
W0
2300
Data 2300
5607
SR
0000

DS70157D-page 164

; Clear W2 (Byte mode)

After
Instruction
W2 3300
SR 0000
; Clear [W0]
; Post-increment W0

After
Instruction
W0
2302
Data 2300
0000
SR
0000

© 2009 Microchip Technology Inc.

CLR

Clear Accumulator, Prefetch Operands

Implemented in:

Syntax:
{label:}

PIC24F

CLR

PIC24H

Acc

dsPIC30F

dsPIC30F

X

X

{,[Wx],Wxd}

{,[Wy],Wyd}

{,AWB}

{,[Wx] + = kx,Wxd} {,[Wy] + = ky,Wyd}
{,[Wx] – = kx,Wxd} {,[Wy] – = ky,Wyd}
{,[W9 + W12],Wxd} {,[W11 + W12],Wyd}
Operands:

Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]
AWB ∈ [W13, [W13] + = 2]

Operation:

0 → Acc(A or B)
([Wx]) → Wxd; (Wx) +/– kx → Wx
([Wy]) → Wyd; (Wy) +/– ky → Wy
(Acc(B or A)) rounded → AWB

Status Affected:

OA, OB, SA, SB

Encoding:
Description:

1100

0011

A0xx

yyii

iijj

jjaa

Clear all 40 bits of the specified accumulator, optionally prefetch
operands in preparation for a MAC type instruction and optionally store
the non-specified accumulator results. This instruction clears the respective overflow and saturate flags (either OA, SA or OB, SB).
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations,
which support indirect and register offset addressing, as described in
Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional
register direct or indirect store of the convergently rounded contents of
the “other” accumulator, as described in Section 4.14.4 “MAC Write
Back”.
The ‘A’ bit selects the other accumulator used for write back.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
The ‘a’ bits select the accumulator Write Back destination.

Words:

1

Cycles:

1

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 165

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

CLR

W4
W8
W13
ACCA
ACCB
Data 2000
SR
Example
2:

CLR

W6
W7
W8
W10
W13
ACCA
ACCB
Data 2000
Data 3000
Data 4000
SR

DS70157D-page 166

A, [W8]+=2, W4, W13

Before
Instruction
F001
2000
C623
00 0067 2345
00 5420 3BDD
1221
0000

; Clear ACCA
; Load W4 with [W8], post-inc W8
; Store ACCB to W13

W4
W8
W13
ACCA
ACCB
Data 2000
SR

After
Instruction
1221
2002
5420
00 0000 0000
00 5420 3BDD
1221
0000

B, [W8]+=2, W6, [W10]+=2, W7, [W13]+=2

Before
Instruction
F001
C783
2000
3000
4000
00 0067 2345
00 5420 ABDD
1221
FF80
FFC3
0000

W6
W7
W8
W10
W13
ACCA
ACCB
Data 2000
Data 3000
Data 4000
SR

;
;
;
;
;

Clear ACCB
Load W6 with [W8]
Load W7 with [W10]
Save ACCA to [W13]
Post-inc W8,W10,W13

After
Instruction
1221
FF80
2002
3002
4002
00 0067 2345
00 0000 0000
1221
FF80
0067
0000

© 2009 Microchip Technology Inc.

CLRWDT

Clear Watchdog Timer

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0110

0000

Syntax:

{label:}

Operands:

None

Operation:

0 → WDT count register
0 → WDT prescaler A count
0 → WDT prescaler B count

Status Affected:

None

Encoding:

CLRWDT

1111

1110

0000

0000

Description:

Clear the contents of the Watchdog Timer count register and the
prescaler count registers. The Watchdog Prescaler A and Prescaler B
settings, set by configuration fuses in the FWDT, are not changed.

Words:

1

Cycles:

1

Example 1:

CLRWDT

; Clear Watchdog Timer

Before
Instruction
SR 0000

After
Instruction
SR 0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 167

16-bit MCU and DSC Programmer’s Reference Manual

COM

Complement f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) → destination designated by D

Status Affected:

N, Z

Encoding:
Description:

COM{.B}

1110

1110

f

{,WREG}

1BDf

ffff

ffff

ffff

Compute the 1’s complement of the contents of the file register and place
the result in the destination register. The optional WREG operand
determines the destination register. If WREG is specified, the result is
stored in WREG. If WREG is not specified, the result is stored in the file
register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

COM.b

RAM200

Before
Instruction
RAM200 80FF
SR 0000
Example 2:

COM

After
Instruction
RAM200 8000
SR 0002 (Z)

RAM400, WREG

Before
Instruction
WREG
1211
RAM400
0823
SR
0000

DS70157D-page 168

; COM RAM200 (Byte mode)

; COM RAM400 and store to WREG
; (Word mode)

After
Instruction
WREG F7DC
RAM400
0823
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

COM

Complement Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

COM{.B}

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) → Wd

Status Affected:

N, Z

Encoding:

1110

Description:

1010

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

1Bqq

qddd

dppp

ssss

Compute the 1’s complement of the contents of the source register Ws
and place the result in the destination register Wd. Either register direct or
indirect addressing may be used for both Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

COM.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

[W0++], [W1++]

Before
Instruction
W0
2301
W1
2400
Data 2300
5607
Data 2400
ABCD
SR
0000
Example 2:

COM

W0, [W1++]

© 2009 Microchip Technology Inc.

After
Instruction
W0
2302
W1
2401
Data 2300
5607
Data 2400
ABA9
SR
0008 (N = 1)
; COM W0 and store to [W1] (Word mode)
; Post-increment W1

After
Instruction
W0
D004
W1
1002
Data 1000
2FFB
SR
0000

5
Instruction
Descriptions

Before
Instruction
W0
D004
W1
1000
Data 1000
ABA9
SR
0000

; COM [W0] and store to [W1] (Byte mode)
; Post-increment W0, W1

DS70157D-page 169

16-bit MCU and DSC Programmer’s Reference Manual

CP

Compare f with WREG, Set Status Flags

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0B0f

ffff

Syntax:

{label:}

Operands:

f ∈ [0 ...8191]

Operation:

(f) – (WREG)

Status Affected:

DC, N, OV, Z, C

Encoding:

CP{.B}

1110

Description:

0011

f

ffff

ffff

Compute (f) – (WREG) and update the STATUS register. This instruction
is equivalent to the SUBWF instruction, but the result of the subtraction is
not stored.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

CP.B

RAM400

Before
Instruction
WREG
8823
RAM400
0823
SR
0000
Example 2:

CP

0x1200

Before
Instruction
WREG
2377
Data 1200
2277
SR
0000

DS70157D-page 170

; Compare RAM400 with WREG (Byte mode)

After
Instruction
WREG
8823
RAM400
0823
SR
0002 (Z = 1)
; Compare (0x1200) with WREG (Word mode)

After
Instruction
WREG
2377
Data 1200
2277
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

CP

Compare Wb with lit5, Set Status Flags

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]

Operation:

(Wb) – lit5

Status Affected:

DC, N, OV, Z, C

Encoding:

CP{.B}

1110

Description:

0001

Wb,

0www

#lit5

wB00

011k

kkkk

Compute (Wb) – lit5, and update the STATUS register. This instruction is
equivalent to the SUB instruction, but the result of the subtraction is not
stored. Register direct addressing must be used for Wb.
The ‘w’ bits select the address of the Wb base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

CP.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W4, #0x12

Before
Instruction
W4
7711
SR
0000
Example 2:

CP

W4, #0x12

Before
Instruction
W4
7713
SR
0000

; Compare W4 with 0x12 (Byte mode)

After
Instruction
W4
7711
SR
0008 (N = 1)
; Compare W4 with 0x12 (Word mode)

After
Instruction
W4
7713
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 171

16-bit MCU and DSC Programmer’s Reference Manual

CP

Compare Wb with Ws, Set Status Flags

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

CP{.B}

Wb,

Ws
[Ws]
[Ws++]
[Ws--]
[++Ws]
[--Ws]

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]

Operands:
Operation:

(Wb) – (Ws)

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

0001

0www

wB00

0ppp

ssss

Compute (Wb) – (Ws), and update the STATUS register. This instruction is
equivalent to the SUB instruction, but the result of the subtraction is not
stored. Register direct addressing must be used for Wb. Register direct or
indirect addressing may be used for Ws.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the address of the Ws source register.
Note:

Words:

1

Cycles:

1

Example 1:

CP.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, [W1++]

Before
Instruction
W0 ABA9
W1
2000
Data 2000
D004
SR
0000
Example 2:

CP

W5, W6

Before
Instruction
W5
2334
W6
8001
SR
0000

DS70157D-page 172

; Compare [W1] with W0 (Byte mode)
; Post-increment W1

After
Instruction
W0 ABA9
W1
2001
Data 2000
D004
SR
0008 (N = 1)
; Compare W6 with W5 (Word mode)

After
Instruction
W5
2334
W6
8001
SR
000C (N, OV = 1)

© 2009 Microchip Technology Inc.

CP0

Compare f with 0x0, Set Status Flags

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0B0f

ffff

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) – 0x0

Status Affected:

DC, N, OV, Z, C

Encoding:

CP0{.B}

1110

Description:

0010

f

ffff

ffff

Compute (f) – 0x0 and update the STATUS register. The result of the
subtraction is not stored.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘f’ bits select the address of the file register.
Note:

Words:

1

Cycles:

1

Example 1:

CP0.B

RAM100

Before
Instruction
RAM100
44C3
SR
0000
Example 2:

CP0

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

0x1FFE

Before
Instruction
Data 1FFE
0001
SR
0000

; Compare RAM100 with 0x0 (Byte mode)

After
Instruction
RAM100
44C3
SR
0008 (N = 1)
; Compare (0x1FFE) with 0x0 (Word mode)

After
Instruction
Data 1FFE
0001
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 173

16-bit MCU and DSC Programmer’s Reference Manual

CP0

Compare Ws with 0x0, Set Status Flags

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

CP0{.B}

Ws
[Ws]
[Ws++]
[Ws--]
[++Ws]
[--Ws]

Operands:

Ws ∈ [W0 ... W15]

Operation:

(Ws) – 0x0000

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

0000

0000

0B00

0ppp

ssss

Compute (Ws) – 0x0000 and update the STATUS register. The result of
the subtraction is not stored. Register direct or indirect addressing may be
used for Ws.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the address of the Ws source register.
Note:

Words:

1

Cycles:

1

Example 1:

CP0.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

[W4--]

Before
Instruction
W4
1001
Data 1000
0034
SR
0000
Example 2:

CP0

[--W5]

Before
Instruction
W5
2400
Data 23FE
9000
SR
0000

DS70157D-page 174

; Compare [W4] with 0 (Byte mode)
; Post-decrement W4

After
Instruction
W4
1000
Data 1000
0034
SR
0002 (Z = 1)
; Compare [--W5] with 0 (Word mode)

After
Instruction
W5
23FE
Data 23FE
9000
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

CPB

Compare f with WREG using Borrow, Set Status Flags

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

1B0f

ffff

Syntax:

{label:}

Operands:

f ∈ [0 ...8191]

Operation:

(f) – (WREG) – (C)

Status Affected:

DC, N, OV, Z, C

Encoding:

CPB{.B}

1110

0011

f

ffff

ffff

Compute (f) – (WREG) – (C), and update the STATUS register. This
instruction is equivalent to the SUBB instruction, but the result of the
subtraction is not stored.

Description:

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.
Words:

1

Cycles:

1

Example 1:

CPB.B

RAM400

Before
Instruction
WREG
8823
RAM400
0823
SR
0000
Example 2:

CPB

0x1200

; Compare RAM400 with WREG using C (Byte mode)

After
Instruction
WREG
8823
RAM400
0823
SR
0008 (N = 1)
; Compare (0x1200) with WREG using C (Word mode)

Before
After
Instruction
Instruction
WREG
2377
WREG
2377
Data 1200
2377
Data 1200
2377
SR
0001 (C = 1)
SR
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 175

16-bit MCU and DSC Programmer’s Reference Manual

CPB

Compare Wb with lit5 using Borrow, Set Status Flags

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]

Operation:

(Wb) – lit5 – (C)

Status Affected:

DC, N, OV, Z, C

Encoding:

CPB{.B}

1110

Description:

Wb,

0001

1www

#lit5

wB00

011k

kkkk

Compute (Wb) – lit5 – (C), and update the STATUS register. This
instruction is equivalent to the SUBB instruction, but the result of the
subtraction is not stored. Register direct addressing must be used for Wb.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits provide the literal operand, a five bit integer number.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

CPB.B

W4, #0x12

Before
Instruction
W4
7711
SR
0001 (C = 1)
Example 2:

CPB.B

W4, #0x12

Before
Instruction
W4
7711
SR
0000
Example 3:

CPB

W12, #0x1F

Before
Instruction
W12
0020
SR
0002 (Z = 1)
Example 4:

CPB

W12, #0x1F

Before
Instruction
W12
0020
SR
0003 (Z, C = 1)

DS70157D-page 176

; Compare W4 with 0x12 using C (Byte mode)

After
Instruction
W4
7711
SR
0008 (N = 1)
; Compare W4 with 0x12 using C (Byte mode)

After
Instruction
W4
7711
SR
0008 (N = 1)
; Compare W12 with 0x1F using C (Word mode)

After
Instruction
W12
0020
SR
0003 (Z, C = 1)
; Compare W12 with 0x1F using C (Word mode)

After
Instruction
W12
0020
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

CPB

Compare Ws with Wb using Borrow, Set Status Flags

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

CPB{.B}

Wb,

Ws
[Ws]
[Ws++]
[Ws--]
[++Ws]
[--Ws]

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]

Operation:

(Wb) – (Ws) – (C)

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

1110

0001

1www

wB00

0ppp

ssss

Compute (Wb) – (Ws) – (C), and update the STATUS register. This
instruction is equivalent to the SUBB instruction, but the result of the
subtraction is not stored. Register direct addressing must be used for Wb.
Register direct or indirect addressing may be used for Ws.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the address of the Ws source register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

CPB.B

W0, [W1++]

; Compare [W1] with W0 using C (Byte mode)
; Post-increment W1

Before
After
Instruction
Instruction
W0 ABA9
W0 ABA9
W1
1000
W1
1001
Data 1000 D0A9
Data 1000 D0A9
SR
0002 (Z = 1)
SR
0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 177

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

CPB.B

W0, [W1++]

; Compare [W1] with W0 using C (Byte mode)
; Post-increment W1

Before
After
Instruction
Instruction
W0 ABA9
W0 ABA9
W1
1000
W1
1001
Data 1000
D0A9
Data 1000
D0A9
SR
0001 (C = 1)
SR
0001 (C = 1)
Example 3:

CPB

W4, W5

Before
Instruction
W4
4000
W5
3000
SR
0001 (C = 1)

DS70157D-page 178

; Compare W5 with W4 using C (Word mode)

After
Instruction
W4
4000
W5
3000
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

CPSEQ

Compare Wb with Wn, Skip if Equal (Wb = Wn)

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wn ∈ [W0 ... W15]

Operation:

(Wb) – (Wn)
Skip if (Wb) = (Wn)

Status Affected:

None

Encoding:

CPSEQ{.B} Wb,

1110

Description:

0111

Wn

1www

wB00

0000

ssss

Compare the contents of Wb with the contents of Wn by performing the
subtraction (Wb) – (Wn), but do not store the result. If (Wb) = (Wn), the
next instruction (fetched during the current instruction execution) is
discarded and on the next cycle, a NOP is executed instead. If
(Wb) ≠ (Wn), the next instruction is executed as normal.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the address of the Ws source register.
Note:

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

Words:

1

Cycles:

1 (2 or 3 if skip taken)

Example 1:

002000 HERE:CPSEQ.BW0, W1; If W0 = W1 (Byte mode),
002002GOTOBYPASS; skip the GOTO
002004
. . .
002006
. . .
002008 BYPASS: . . .
00200A
. . .

PC
W0
W1
SR
Example 2:

018000 HERE:
018002
018006
018008

PC
W0
W1
SR
CPSEQ
CALL
...
...

Before
Instruction
01 8000
3344
3344
0002 (Z = 1)

After
Instruction
00 2002
1001
1000
0000

W4, W8; If W4 = W8 (Word mode),
_FIR; skip the subroutine call

5
PC
W4
W8
SR

After
Instruction
01 8006
3344
3344
0002 (Z = 1)

Instruction
Descriptions

PC
W4
W8
SR

© 2009 Microchip Technology Inc.

Before
Instruction
00 2000
1001
1000
0000

DS70157D-page 179

16-bit MCU and DSC Programmer’s Reference Manual

CPSGT

Signed Compare Wb with Wn, Skip if Greater Than (Wb > Wn)

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wn ∈ [W0 ... W15]

Operation:

(Wb) – (Wn)
Skip if (Wb) > (Wn)

Status Affected:

None

Encoding:

CPSGT{.B}

1110

Description:

Wb,

0110

Wn

0www

wB00

0000

ssss

Compare the contents of Wb with the contents of Wn by performing the
subtraction (Wb) – (Wn), but do not store the result. If (Wb) > (Wn), the
next instruction (fetched during the current instruction execution) is
discarded and on the next cycle, a NOP is executed instead. Otherwise,
the next instruction is executed as normal.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the address of the Ws source register.
Note:

Words:

1

Cycles:

1 (2 or 3 if skip taken)

Example 1:

002000 HERE:
002002
002006
002008
00200A BYPASS
00200C

PC
W0
W1
SR
Example 2:

CPSGT.B
GOTO
. . .
. . .
. . .
. . .

W0, W1; If W0 > W1 (Byte mode),
BYPASS; skip the GOTO

Before
Instruction
00 2000
00FF
26FE
0009 (N, C = 1)

018000 HERE:
018002
018006
018008

PC
W4
W5
SR

DS70157D-page 180

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

CPSGT
CALL
...
...

Before
Instruction
01 8000
2600
2600
0004 (OV = 1)

PC
W0
W1
SR

After
Instruction
00 2006
00FF
26FE
0009 (N, C = 1)

W4, W5; If W4 > W5 (Word mode),
_FIR; skip the subroutine call

PC
W4
W5
SR

After
Instruction
01 8002
2600
2600
0004 (OV = 1)

© 2009 Microchip Technology Inc.

CPSLT

Signed Compare Wb with Wn, Skip if Less Than (Wb < Wn)

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wn ∈ [W0 ... W15]

Operation:

(Wb) – (Wn)
Skip if (Wb) < (Wn)

Status Affected:

None

Encoding:

CPSLT{.B}

1110

Description:

0110

Wb,

Wn

1www

wB00

0000

ssss

Compare the contents of Wb with the contents of Wn by performing the
subtraction (Wb) – (Wn), but do not store the result. If (Wb) < (Wn), the
next instruction (fetched during the current instruction execution) is
discarded and on the next cycle, a NOP is executed instead. Otherwise, the
next instruction is executed as normal.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the address of the Ws source register.
Note:

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

Words:

1

Cycles:

1 (2 or 3 if skip taken)

Example 1:

002000 HERE:
002002
002006
002008
00200A BYPASS:
00200C

PC
W8
W9
SR
Example 2:

CPSLT
CALL
. . .
. . .

Before
Instruction
01 8000
2600
3000
0000

W8, W9; If W8 < W9 (Byte mode),
BYPASS; skip the GOTO

PC
W8
W9
SR

After
Instruction
00 2002
00FF
26FE
0008 (N = 1)

W3, W6; If W3 < W6 (Word mode),
_FIR; skip the subroutine call

5
PC
W3
W6
SR

After
Instruction
01 8006
2600
3000
0000

Instruction
Descriptions

© 2009 Microchip Technology Inc.

Before
Instruction
00 2000
00FF
26FE
0008 (N = 1)

018000 HERE:
018002
018006
018008

PC
W3
W6
SR

CPSLT.B
GOTO
. . .
. . .
. . .
. . .

DS70157D-page 181

16-bit MCU and DSC Programmer’s Reference Manual

CPSNE

Signed Compare Wb with Wn, Skip if Not Equal (Wb ≠ Wn)

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wn ∈ [W0 ... W15]

Operation:

(Wb) – (Wn)
Skip if (Wb) ≠ (Wn)

Status Affected:

None

Encoding:

CPSNE{.B} Wb,

1110

Description:

0111

Wn

0www

wB00

0000

ssss

Compare the contents of Wb with the contents of Wn by performing the
subtraction (Wb) – (Wn), but do not store the result. If (Wb) ≠ (Wn), the next
instruction (fetched during the current instruction execution) is discarded
and on the next cycle, a NOP is executed instead. Otherwise, the next
instruction is executed as normal.
The ‘w’ bits select the address of the Wb source register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the address of the Ws source register.
Note:

Words:

1

Cycles:

1 (2 or 3 if skip taken)

Example 1:

002000 HERE:
002002
002006
002008
00200A BYPASS:
00200C

PC
W2
W3
SR
Example 2:

CPSNE.B
GOTO
. . .
. . .
. . .
. . .

Before
Instruction
00 2000
00FF
26FE
0001 (C = 1)

018000 HERE:
018002
018006
018008

PC
W0
W8
SR

DS70157D-page 182

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

Before
Instruction
01 8000
3000
3000
0000

CPSNE
CALL
...
...

W2, W3 ; If W2 != W3 (Byte mode),
BYPASS ; skip the GOTO

PC
W2
W3
SR

After
Instruction
00 2006
00FF
26FE
0001 (C = 1)

W0, W8 ; If W0 != W8 (Word mode),
_FIR ; skip the subroutine call

PC
W0
W8
SR

After
Instruction
01 8002
3000
3000
0000

© 2009 Microchip Technology Inc.

DAW.B

Decimal Adjust Wn

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0100

0000

Syntax:

{label:}

DAW.B

Wn

Operands:

Wn ∈ [W0 ... W15]

Operation:

If (Wn<3:0> > 9) or (DC = 1)
(Wn<3:0>) + 6 → Wn<3:0>
Else
(Wn<3:0>) → Wn<3:0>
If (Wn<7:4> > 9) or (C = 1)
(Wn<7:4>) + 6 → Wn<7:4>
Else
(Wn<7:4>) → Wn<7:4>

Status Affected:

C

Encoding:
Description:

1111

1101

0000

ssss

Adjust the Least Significant Byte in Wn to produce a binary coded decimal
(BCD) result. The Most Significant Byte of Wn is not changed, and the
Carry flag is used to indicate any decimal rollover. Register direct
addressing must be used for Wn.
The ‘s’ bits select the source/destination register.
Note 1: This instruction is used to correct the data format after two
packed BCD bytes have been added.
2: This instruction operates in Byte mode only and the .B
extension must be included with the opcode.

Words:

1

Cycles:

1

Example 1:

DAW.B

W0

; Decimal adjust W0

Before
Instruction
W0 771A
SR
0002 (DC = 1)
Example 2:

DAW.B

W3

Before
Instruction
W3 77AA
SR
0000

After
Instruction
W0
7720
SR
0002 (DC = 1)

; Decimal adjust W3

After
Instruction
W3
7710
SR
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 183

16-bit MCU and DSC Programmer’s Reference Manual

DEC

Decrement f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) – 1 → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:

DEC{.B}

1110

Description:

1101

f

{,WREG}

0BDf

ffff

ffff

ffff

Subtract one from the contents of the file register and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

DEC.B

0x200

Before
Instruction
Data 200 80FF
SR
0000
Example 2:

DEC

After
Instruction
Data 200 80FE
SR
0009 (N, C = 1)

RAM400, WREG

Before
Instruction
WREG
1211
RAM400
0823
SR
0000

DS70157D-page 184

; Decrement (0x200) (Byte mode)

; Decrement RAM400 and store to WREG
; (Word mode)

After
Instruction
WREG
0822
RAM400
0823
SR
0000

© 2009 Microchip Technology Inc.

DEC

Decrement Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

DEC{.B}

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operands:
Operation:

(Ws) – 1 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

1001

0Bqq

qddd

dppp

ssss

Subtract one from the contents of the source register Ws and place the
result in the destination register Wd. Either register direct or indirect
addressing may be used by Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

DEC.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

[W7++], [W8++]

Before
Instruction
W7
2301
W8
2400
Data 2300
5607
Data 2400 ABCD
SR
0000
Example 2:

DEC

W5, [W6++]

© 2009 Microchip Technology Inc.

After
Instruction
W7
2302
W8
2401
Data 2300
5607
Data 2400
AB55
SR
0000
; Decrement W5 and store to [W6] (Word mode)
; Post-increment W6

After
Instruction
W5
D004
W6
2002
Data 2000
D003
SR
0009 (N, C = 1)

5
Instruction
Descriptions

Before
Instruction
W5
D004
W6
2000
Data 2000 ABA9
SR
0000

; DEC [W7] and store to [W8] (Byte mode)
; Post-increment W7, W8

DS70157D-page 185

16-bit MCU and DSC Programmer’s Reference Manual

DEC2

Decrement f by 2

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) – 2 → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:

DEC2{.B}

1110

Description:

1101

f

{,WREG}

1BDf

ffff

ffff

ffff

Subtract two from the contents of the file register and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note:

Words:

1

Cycles:

1

Example 1:

DEC2.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

0x200

Before
Instruction
Data 200 80FF
SR
0000
Example 2:

DEC2

After
Instruction
Data 200 80FD
SR
0009 (N, C = 1)

RAM400, WREG

Before
Instruction
WREG
1211
RAM400
0823
SR
0000

DS70157D-page 186

; Decrement (0x200) by 2 (Byte mode)

; Decrement RAM400 by 2 and
; store to WREG (Word mode)

After
Instruction
WREG
0821
RAM400
0823
SR
0000

© 2009 Microchip Technology Inc.

DEC2

Decrement Ws by 2

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

DEC2{.B}

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) – 2 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

1001

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

1Bqq

qddd

dppp

ssss

Subtract two from the contents of the source register Ws and place the
result in the destination register Wd. Either register direct or indirect
addressing may be used by Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

DEC2.B [W7--], [W8--]; DEC [W7] by 2, store to [W8] (Byte mode)
; Post-decrement W7, W8

Before
Instruction
W7
2301
W8
2400
Data 2300
0107
Data 2400 ABCD
SR
0000
Example 2:

DEC2

W5, [W6++]

© 2009 Microchip Technology Inc.

; DEC W5 by 2, store to [W6] (Word mode)
; Post-increment W6

After
Instruction
W5
D004
W6
1002
Data 1000
D002
SR
0009 (N, C = 1)

5
Instruction
Descriptions

Before
Instruction
W5
D004
W6
1000
Data 1000 ABA9
SR
0000

After
Instruction
W7
2300
W8
23FF
Data 2300
0107
Data 2400
ABFF
SR
0008 (N = 1)

DS70157D-page 187

16-bit MCU and DSC Programmer’s Reference Manual

DISI

Disable Interrupts Temporarily

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit14 ∈ [0 ... 16383]

Operation:

lit14 → DISICNT
1 → DISI
Disable interrupts for (lit14 + 1) cycles

Status Affected:

None

Encoding:

1111

Description:

Words:

1

Cycles:

1

Example 1:

#lit14

1100

00kk

kkkk

kkkk

kkkk

Disable interrupts of priority 0 through priority 6 for (lit14 + 1) instruction
cycles. Priority 0 through priority 6 interrupts are disabled starting in the
cycle that DISI executes, and remain disabled for the next (lit 14) cycles.
The lit14 value is written to the DISICNT register, and the DISI flag
(INTCON2<14>) is set to ‘1’. This instruction can be used before
executing time critical code, to limit the effects of interrupts.
Note:

This instruction does not prevent priority 7 interrupts and traps
from running. See the specific device family reference manual
for details.

002000 HERE:
002002
002004

PC
DISICNT
INTCON2
SR

DS70157D-page 188

DISI

Before
Instruction
00 2000
0000
0000
0000

DISI

#100

; Disable interrupts for 101 cycles
; next 100 cycles protected by DISI

. . .

PC
DISICNT
INTCON2
SR

After
Instruction
00 2002
0100
4000 (DISI = 1)
0000

© 2009 Microchip Technology Inc.

DIV.S
Implemented in:

Syntax:

Signed Integer Divide
PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

DIV.S{W}

Wm, Wn

DIV.SD

Wm, Wn

Operands:

Wm ∈ [W0 ... W15] for word operation
Wm ∈ [W0, W2, W4 ... W14] for double operation
Wn ∈ [W2 ... W15]

Operation:

For word operation (default):
Wm → W0
If (Wm<15> = 1):
0xFFFF → W1
Else:
0x0 → W1
W1:W0 / Wn → W0
Remainder → W1
For double operation (DIV.SD):
Wm + 1:Wm → W1:W0
W1:W0 / Wn → W0
Remainder → W1

Status Affected:
Encoding:
Description:

N, OV, Z, C
1101

1000

0ttt

tvvv

vW00

ssss

Iterative, signed integer divide, where the dividend is stored in Wm (for a
16-bit by 16-bit divide) or Wm + 1:Wm (for a 32-bit by 16-bit divide) and
the divisor is stored in Wn. In the default word operation, Wm is first
copied to W0 and sign-extended through W1 to perform the operation. In
the double operation, Wm + 1:Wm is first copied to W1:W0. The 16-bit
quotient of the divide operation is stored in W0, and the 16-bit remainder
is stored in W1.
This instruction must be executed 18 times using the REPEAT instruction
(with an iteration count of 17) to generate the correct quotient and
remainder. The N flag will be set if the remainder is negative and cleared
otherwise. The OV flag will be set if the divide operation resulted in an
overflow and cleared otherwise. The Z flag will be set if the remainder is
‘0’ and cleared otherwise. The C flag is used to implement the divide
algorithm and its final value should not be used.
The ‘t’ bits select the most significant word of the dividend for the double
operation. These bits are clear for the word operation.
The ‘v’ bits select the least significant word of the dividend.
The ‘W’ bit selects the dividend size (‘0’ for 16-bit, ‘1’ for 32-bit).
The ‘s’ bits select the divisor register.

© 2009 Microchip Technology Inc.

DS70157D-page 189

5
Instruction
Descriptions

Note 1: The extension .D in the instruction denotes a double word
(32-bit) dividend rather than a word dividend. You may use a
.W extension to denote a word operation, but it is not required.
2: Unexpected results will occur if the quotient can not be
represented in 16 bits. When this occurs for the double
operation (DIV.SD), the OV status bit will be set and the
quotient and remainder should not be used. For the word
operation (DIV.S), only one type of overflow may occur
(0x8000/0xFFFF = + 32768 or 0x00008000), which allows the
OV status bit to interpret the result.
3: Dividing by zero will initiate an arithmetic error trap during the
first cycle of execution.
4: This instruction is interruptible on each instruction cycle
boundary.

16-bit MCU and DSC Programmer’s Reference Manual
Words:

1

Cycles:

18 (plus 1 for REPEAT execution)

Example 1:

REPEAT #17
DIV.S W3, W4

Before
Instruction
W0
5555
W1
1234
W3
3000
W4
0027
SR
0000
Example 2:

REPEAT
DIV.SD

#17
W0, W12

Before
Instruction
W0
2500
W1
FF42
W12
2200
SR
0000

DS70157D-page 190

; Execute DIV.S 18 times
; Divide W3 by W4
; Store quotient to W0, remainder to W1

After
Instruction
W0
013B
W1
0003
W3
3000
W4
0027
SR
0000
; Execute DIV.SD 18 times
; Divide W1:W0 by W12
; Store quotient to W0, remainder to W1

After
Instruction
W0
FA6B
W1
EF00
W12
2200
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

DIV.U

Unsigned Integer Divide

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

DIV.U{W}

Wm, Wn

DIV.UD

Wm, Wn

Operands:

Wm ∈ [W0 ... W15] for word operation
Wm ∈ [W0, W2, W4 ... W14] for double operation
Wn ∈ [W2 ... W15]

Operation:

For word operation (default):
Wm → W0
0x0 → W1
W1:W0/Wn → W0
Remainder → W1
For double operation (DIV.UD):
Wm + 1:Wm → W1:W0
W1:W0/Wns → W0
Remainder → W1

Status Affected:

N, OV, Z, C

Encoding:
Description:

1101

1000

1ttt

tvvv

vW00

ssss

Iterative, unsigned integer divide, where the dividend is stored in Wm (for
a 16-bit by 16-bit divide), or Wm + 1:Wm (for a 32-bit by 16-bit divide) and
the divisor is stored in Wn. In the word operation, Wm is first copied to W0
and W1 is cleared to perform the divide. In the double operation,
Wm + 1:Wm is first copied to W1:W0. The 16-bit quotient of the divide
operation is stored in W0, and the 16-bit remainder is stored in W1.
This instruction must be executed 18 times using the REPEAT instruction
(with an iteration count of 17) to generate the correct quotient and
remainder. The N flag will always be cleared. The OV flag will be set if the
divide operation resulted in an overflow and cleared otherwise. The Z flag
will be set if the remainder is ‘0’ and cleared otherwise. The C flag is used
to implement the divide algorithm and its final value should not be used.
The ‘t’ bits select the most significant word of the dividend for the double
operation. These bits are clear for the word operation.
The ‘v’ bits select the least significant word of the dividend.
The ‘W’ bit selects the dividend size (‘0’ for 16-bit, ‘1’ for 32-bit).
The ‘s’ bits select the divisor register.

Words:

1

Cycles:

18 (plus 1 for REPEAT execution)

© 2009 Microchip Technology Inc.

DS70157D-page 191

5
Instruction
Descriptions

Note 1: The extension .D in the instruction denotes a double word
(32-bit) dividend rather than a word dividend. You may use a .W
extension to denote a word operation, but it is not required.
2: Unexpected results will occur if the quotient can not be
represented in 16 bits. This may only occur for the double
operation (DIV.UD). When an overflow occurs, the OV status
bit will be set and the quotient and remainder should not be
used.
3: Dividing by zero will initiate an arithmetic error trap during the
first cycle of execution.
4: This instruction is interruptible on each instruction cycle
boundary.

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

REPEAT #17
DIV.U W2, W4

Before
Instruction
W0
5555
W1
1234
W2
8000
W4
0200
SR
0000
Example 2:

REPEAT
DIV.UD

#17
W10, W12

Before
Instruction
W0
5555
W1
1234
W10
2500
W11
0042
W12
2200
SR
0000

DS70157D-page 192

; Execute DIV.U 18 times
; Divide W2 by W4
; Store quotient to W0, remainder to W1

After
Instruction
W0
0040
W1
0000
W2
8000
W4
0200
SR
0002 (Z = 1)
; Execute DIV.UD 18 times
; Divide W11:W10 by W12
; Store quotient to W0, remainder to W1

After
Instruction
W0
01F2
W1
0100
W10
2500
W11
0042
W12
2200
SR
0000

© 2009 Microchip Technology Inc.

DIVF

Fractional Divide

Implemented in:

PIC24F

PIC24H

Syntax:

{label:}

Operands:

Wm ∈ [W0 ... W15]
Wn ∈ [W2 ... W15]

Operation:

0x0 → W0
Wm → W1
W1:W0/Wn → W0
Remainder → W1

Status Affected:

N, OV, Z, C

Encoding:
Description:

1101

DIVF

1001

dsPIC30F

dsPIC33F

X

X

Wm, Wn

0ttt

t000

0000

ssss

Iterative, signed fractional 16-bit by 16-bit divide, where the dividend is
stored in Wm and the divisor is stored in Wn. To perform the operation,
W0 is first cleared and Wm is copied to W1. The 16-bit quotient of the
divide operation is stored in W0, and the 16-bit remainder is stored in W1.
The sign of the remainder will be the same as the sign of the dividend.
This instruction must be executed 18 times using the REPEAT instruction
(with an iteration count of 17) to generate the correct quotient and
remainder. The N flag will be set if the remainder is negative and cleared
otherwise. The OV flag will be set if the divide operation resulted in an
overflow and cleared otherwise. The Z flag will be set if the remainder is
‘0’ and cleared otherwise. The C flag is used to implement the divide
algorithm and its final value should not be used.
The ‘t’ bits select the dividend register.
The ‘s’ bits select the divisor register.
Note 1: For the fractional divide to be effective, Wm must be less than
Wn. If Wm is greater than or equal to Wn, unexpected results
will occur because the fractional result will be greater than or
equal to 1.0. When this occurs, the OV status bit will be set and
the quotient and remainder should not be used.
2: Dividing by zero will initiate an arithmetic error trap during the
first cycle of execution.
3: This instruction is interruptible on each instruction cycle
boundary.

Words:

1

Cycles:

18 (plus 1 for REPEAT execution)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 193

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

REPEAT
DIVF

#17
W8, W9

Before
Instruction
W0
8000
W1
1234
W8
1000
W9
4000
SR
0000
Example 2:

REPEAT #17
DIVF
W8, W9

Before
Instruction
W0
8000
W1
1234
W8
1000
W9
8000
SR
0000
Example 3:

REPEAT #17
DIVF
W0, W1

Before
Instruction
W0
8002
W1
8001
SR
0000

DS70157D-page 194

; Execute DIVF 18 times
; Divide W8 by W9
; Store quotient to W0, remainder to W1

After
Instruction
W0
2000
W1
0000
W8
1000
W9
4000
SR
0002 (Z = 1)
; Execute DIVF 18 times
; Divide W8 by W9
; Store quotient to W0, remainder to W1

After
Instruction
W0
F000
W1
0000
W8
1000
W9
8000
SR
0002 (Z = 1)
; Execute DIVF 18 times
; Divide W0 by W1
; Store quotient to W0, remainder to W1

After
Instruction
W0
7FFE
W1
8002
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

DO
Implemented in:

Initialize Hardware Loop Literal
PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

lit14 ∈ [0 ... 16383]
Expr may be an absolute address, label or expression.
Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation:

PUSH DO shadows (DCOUNT, DOEND, DOSTART)
(lit14) → DCOUNT
(PC) + 4 → PC
(PC) → DOSTART
(PC) + (2 * Slit16) → DOEND
Increment DL<2:0> (CORCON<10:8>)

Status Affected:

DA

Encoding:
Description:

DO

dsPIC30F

#lit14,

Expr

0000

1000

00kk

kkkk

kkkk

kkkk

0000

0000

nnnn

nnnn

nnnn

nnnn

Initiate a no overhead hardware DO loop, which is executed (lit14 + 1)
times. The DO loop begins at the address following the DO instruction, and
ends at the address 2 * Slit16 instruction words away. The 14-bit count
value (lit14) supports a maximum loop count value of 16384, and the 16-bit
offset value (Slit16) supports offsets of 32K instruction words in both
directions.
When this instruction executes, DCOUNT, DOSTART and DOEND are first
PUSHed into their respective shadow registers, and then updated with the
new DO loop parameters specified by the instruction. The DO level count,
DL<2:0> (CORCON<8:10>), is then incremented. After the DO loop
completes execution, the PUSHed DCOUNT, DOSTART and DOEND
registers are restored, and DL<2:0> is decremented.
The ‘k’ bits specify the loop count.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from the PC to the last instruction executed in the loop.
Special Features, Restrictions:
The following features and restrictions apply to the DO instruction.
1. Using a loop count of ‘0’ will result in the loop being executed one
time.
2. Using a loop size of -2, -1 or 0 is invalid. Unexpected results may
occur if these offsets are used.
3. The very last two instructions of the DO loop can NOT be:
• an instruction which changes program control flow
• a DO or REPEAT instruction
Unexpected results may occur if any of these instructions are used.
4.

DS70157D-page 195

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

If a hard trap occurs in the second to last instruction or third to last
instruction of a DO loop, the loop will not function properly. The hard
trap includes exceptions of priority level 13 through level 15,
inclusive.
Note 1: The DO instruction is interruptible and supports 1 level of
hardware nesting. Nesting up to an additional 5 levels may be
provided in software by the user. See the specific device family
reference manual for details.
2: The linker will convert the specified expression into the offset to
be used.

16-bit MCU and DSC Programmer’s Reference Manual
Words:

2

Cycles:

2

Example 1:

002000 LOOP6:
002004
002006
002008
00200A END6:
00200C

PC
DCOUNT
DOSTART
DOEND
CORCON
SR
Example 2:

Before
Instruction
00 2000
0000
FF FFFF
FF FFFF
0000
0001 (C = 1)

PC
DCOUNT
DOSTART
DOEND
CORCON
SR

After
Instruction
00 2004
0005
00 2004
00 200A
0100 (DL = 1)
0201 (DA, C = 1)

01C000 LOOP12: DO #0x160, END12; Init DO loop (353 reps)
01C004
DEC W1, W2; First instruction in loop
01C006
. . .
01C008
. . .
01C00A
. . .
01C00C
. . .
01C00E
. . .
01C010
CALL _FIR88; Call the FIR88 subroutine
01C014 END12: NOP; Last instruction in loop
; (Required NOP filler)

PC
DCOUNT
DOSTART
DOEND
CORCON
SR

DS70157D-page 196

DO
#5, END6; Initiate DO loop (6 reps)
ADD
W1, W2, W3; First instruction in loop
. . .
. . .
SUB
W2, W3, W4; Last instruction in loop
. . .

Before
Instruction
01 C000
0000
FF FFFF
FF FFFF
0000
0008 (N = 1)

PC
DCOUNT
DOSTART
DOEND
CORCON
SR

After
Instruction
01 C004
0160
01 C004
01 C014
0100 (DL = 1)
0208 (DA, N = 1)

© 2009 Microchip Technology Inc.

DO

Initialize Hardware Loop Wn

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]
Expr may be an absolute address, label or expression.
Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation:

PUSH Shadows (DCOUNT, DOEND, DOSTART)
(Wn) → DCOUNT
(PC) + 4 → PC
(PC) → DOSTART
(PC) + (2 * Slit16) → DOEND
Increment DL<2:0> (CORCON<10:8>)

Status Affected:

DA

Encoding:
Description:

DO

dsPIC30F

Wn,

Expr

0000

1000

1000

0000

0000

ssss

0000

0000

nnnn

nnnn

nnnn

nnnn

Initiate a no overhead hardware DO loop, which is executed (Wn + 1) times.
The DO loop begins at the address following the DO instruction, and ends at
the address 2 * Slit16 instruction words away. The lower 14 bits of Wn
support a maximum count value of 16384, and the 16-bit offset value
(Slit16) supports offsets of 32K instruction words in both directions.
When this instruction executes, DCOUNT, DOSTART and DOEND are first
PUSHed into their respective shadow registers, and then updated with the
new DO loop parameters specified by the instruction. The DO level count,
DL<2:0> (CORCON<8:10>), is then incremented. After the DO loop
completes execution, the PUSHed DCOUNT, DOSTART and DOEND
registers are restored, and DL<2:0> is decremented.
The ‘s’ bits specify the register Wn that contains the loop count.
The ‘n’ bits are a signed literal that specifies the number of instructions
offset from (PC + 4), which is the last instruction executed in the loop.
Special Features, Restrictions:
The following features and restrictions apply to the DO instruction.
1. Using a loop count of ‘0’ will result in the loop being executed one
time.
2. Using an offset of -2, -1 or 0 is invalid. Unexpected results may occur
if these offsets are used.
3. The very last two instructions of the DO loop can NOT be:
• an instruction which changes program control flow
• a DO or REPEAT instruction
Unexpected results may occur if these last instructions are used.

Words:

2

Cycles:

2

© 2009 Microchip Technology Inc.

DS70157D-page 197

5
Instruction
Descriptions

Note 1: The DO instruction is interruptible and supports 1 level of nesting.
Nesting up to an additional 5 levels may be provided in software
by the user. See the specific device family reference manual for
details.
2: The linker will convert the specified expression into the offset to
be used.

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

002000 LOOP6:
002004
002006
002008
00200A
00200C
00200E
002010 END6:

PC
W0
DCOUNT
DOSTART
DOEND
CORCON
SR
Example 2:

DS70157D-page 198

Before
Instruction
00 2000
0012
0000
FF FFFF
FF FFFF
0000
0000

002000 LOOPA:
002004
002006
002008
00200A
002010 ENDA:

PC
W7
DCOUNT
DOSTART
DOEND
CORCON
SR

DO
ADD
. . .
. . .
. . .
REPEAT
SUB
NOP

Before
Instruction
00 2000
E00F
0000
FF FFFF
FF FFFF
0000
0000

W0, END6
; Initiate DO loop (W0 reps)
W1, W2, W3 ; First instruction in loop

#6
W2, W3, W4
; Last instruction in loop
; (Required NOP filler)

PC
W0
DCOUNT
DOSTART
DOEND
CORCON
SR
DO
SWAP
. . .
. . .
. . .
MOV

W7, ENDA
W0

After
Instruction
00 2004
0012
0012
00 2004
00 2010
0100 (DL = 1)
0080 (DA = 1)
; Initiate DO loop (W7 reps)
; First instruction in loop

W1, [W2++] ; Last instruction in loop

PC
W7
DCOUNT
DOSTART
DOEND
CORCON
SR

After
Instruction
00 2004
E00F
200F
00 2004
00 2010
0100 (DL = 1)
0080 (DA = 1)

© 2009 Microchip Technology Inc.

ED

Euclidean Distance (No Accumulate)

Implemented in:

Syntax:

PIC24F

{label:} ED

PIC24H

dsPIC30F

dsPIC33F

X

X

Wm * Wm, Acc,

[Wx],

[Wy],

Wxd

[Wx] + = kx, [Wy] + = ky,
[Wx] – = kx, [Wy] – = ky,
[W9 +
W12],

[W11 +
W12],

Operands:

Acc ∈ [A,B]
Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]
Wxd ∈ [W4 ... W7]

Operation:

(Wm) * (Wm) → Acc(A or B)
([Wx] – [Wy]) → Wxd
(Wx) + kx → Wx
(Wy) + ky → Wy

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

1111

Description:

00mm

A1xx

00ii

iijj

jj11

Compute the square of Wm, and optionally compute the difference of the
prefetch values specified by [Wx] and [Wy]. The results of Wm * Wm are
sign-extended to 40 bits and stored in the specified accumulator. The
results of [Wx] – [Wy] are stored in Wxd, which may be the same as Wm.
Operands Wx, Wxd and Wyd specify the prefetch operations which
support indirect and register offset addressing as described in
Section 4.14.1 “MAC Prefetches”.
The ‘m’ bits select the operand register Wm for the square.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch difference Wxd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.

Words:

1

Cycles:

1

Example 1:

ED

© 2009 Microchip Technology Inc.

Before
Instruction
009A
1100
2300
00 3D0A 0000
007F
0028
0000

W4
W8
W10
ACCA
Data 1100
Data 2300
SR

;
;
;
;

Square W4 to ACCA
[W8]-[W10] to W4
Post-increment W8
Post-decrement W10

After
Instruction
0057
1102
22FE
00 0000 5CA4
007F
0028
0000

DS70157D-page 199

5
Instruction
Descriptions

W4
W8
W10
ACCA
Data 1100
Data 2300
SR

W4*W4, A, [W8]+=2, [W10]-=2, W4

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

ED

W5
W9
W11
W12
ACCB
Data 1200
Data 2508
SR

DS70157D-page 200

W5*W5, B, [W9]+=2, [W11+W12], W5 ; Square W5 to ACCB
; [W9]-[W11+W12] to W5
; Post-increment W9

Before
Instruction
43C2
1200
2500
0008
00 28E3 F14C
6A7C
2B3D
0000

W5
W9
W11
W12
ACCB
Data 1200
Data 2508
SR

After
Instruction
3F3F
1202
2500
0008
00 11EF 1F04
6A7C
2B3D
0000

© 2009 Microchip Technology Inc.

EDAC

Euclidean Distance

Implemented in:

PIC24F

PIC24H

dsPIC30F dsPIC33F
X

Syntax:

{label:} EDAC

Wm * Wm, Acc,

X
[Wx],

[Wy],

[Wx] + =
kx,

[Wy] + = ky,

Wxd

[Wx] – = kx, [Wy] – = ky,
[W9 +
W12],

[W11 +
W12],

Operands:

Acc ∈ [A,B]
Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]
Wxd ∈ [W4 ... W7]

Operation:

(Acc(A or B)) + (Wm) * (Wm) → Acc(A or B)
([Wx] – [Wy]) → Wxd
(Wx) + kx → Wx
(Wy) + ky → Wy

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

1111

Description:

00mm

A1xx

00ii

iijj

jj10

Compute the square of Wm, and also the difference of the prefetch
values specified by [Wx] and [Wy]. The results of Wm * Wm are
sign-extended to 40 bits and added to the specified accumulator. The
results of [Wx] – [Wy] are stored in Wxd, which may be the same as Wm.
Operands Wx, Wxd and Wyd specify the prefetch operations which
support indirect and register offset addressing as described in
Section 4.14.1 “MAC Prefetches”.
The ‘m’ bits select the operand register Wm for the square.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch difference Wxd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.

Words:

1

Cycles:

1

Example 1:

EDAC

© 2009 Microchip Technology Inc.

Before
Instruction
009A
1100
2300
00 3D0A 3D0A
007F
0028
0000

W4
W8
W10
ACCA
Data 1100
Data 2300
SR

;
;
;
;
;

Square W4 and
add to ACCA
[W8]-[W10] to W4
Post-increment W8
Post-decrement W10

After
Instruction
0057
1102
22FE
00 3D0A 99AE
007F
0028
0000

5
Instruction
Descriptions

W4
W8
W10
ACCA
Data 1100
Data 2300
SR

W4*W4, A, [W8]+=2, [w10]-=2, W4

DS70157D-page 201

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

EDAC W5*W5, B, [w9]+=2, [W11+W12], W5

W5
W9
W11
W12
ACCB
Data 1200
Data 2508
SR

DS70157D-page 202

Before
Instruction
43C2
1200
2500
0008
00 28E3 F14C
6A7C
2B3D
0000

W5
W9
W11
W12
ACCB
Data 1200
Data 2508
SR

;
;
;
;

Square W5 and
add to ACCB
[W9]-[W11+W12] to W5
Post-increment W9

After
Instruction
3F3F
1202
2500
0008
00 3AD3 1050
6A7C
2B3D
0000

© 2009 Microchip Technology Inc.

EXCH

Exchange Wns and Wnd

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wns ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]

Operation:

(Wns) ↔ (Wnd)

Status Affected:

None

Encoding:

EXCH

1111

Description:

1101

Wns,

0000

Wnd

0ddd

d000

ssss

Exchange the word contents of two working registers. Register direct
addressing must be used for Wns and Wnd.
The ‘d’ bits select the address of the first register.
The ‘s’ bits select the address of the second register.
Note:

Words:

1

Cycles:

1

Example 1:

EXCH

W1
W9
SR
Example 2:

EXCH

W4
W5
SR

This instruction only executes in Word mode.

W1, W9

Before
Instruction
55FF
A3A3
0000
W4, W5

Before
Instruction
ABCD
4321
0000

; Exchange the contents of W1 and W9

After
Instruction
W1
A3A3
W9
55FF
SR
0000
; Exchange the contents of W4 and W5

After
Instruction
W4
4321
W5
ABCD
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 203

16-bit MCU and DSC Programmer’s Reference Manual

FBCL

Find First Bit Change from Left

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

FBCL

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]

Operation:

Max_Shift = 15
Sign = (Ws) & 0x8000
Temp = (Ws) << 1
Shift = 0
While ( (Shift < Max_Shift) && ( (Temp & 0x8000) == Sign) )
Temp = Temp << 1
Shift = Shift + 1
-Shift → (Wnd)

Status Affected:

C

Encoding:
Description:

1101

1111

0000

0ddd

dppp

ssss

Find the first occurrence of a one (for a positive value), or zero (for a
negative value), starting from the Most Significant bit after the sign bit of
Ws and working towards the Least Significant bit of the word operand. The
bit number result is sign-extended to 16 bits and placed in Wnd.
The next Most Significant bit after the sign bit is allocated bit number 0 and
the Least Significant bit is allocated bit number -14. This bit ordering
allows for the immediate use of Wd with the SFTAC instruction for scaling
values up. If a bit change is not found, a result of -15 is returned and the C
flag is set. When a bit change is found, the C flag is cleared.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

FBCL

W1, W9

Before
Instruction
W1
55FF
W9
FFFF
SR
0000

DS70157D-page 204

This instruction operates in Word mode only.

; Find 1st bit change from left in W1
; and store result to W9

After
Instruction
W1
55FF
W9
0000
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

FBCL

W1, W9

Before
Instruction
W1 FFFF
W9 BBBB
SR
0000
Example 3:

FBCL

[W1++], W9

Before
Instruction
W1
2000
W9 BBBB
Data 2000
FF0A
SR
0000

; Find 1st bit change from left in W1
; and store result to W9

After
Instruction
W1 FFFF
W9 FFF1
SR 0001 (C = 1)
; Find 1st bit change from left in [W1]
; and store result to W9
; Post-increment W1

After
Instruction
W1 2002
W9 FFF9
Data 2000 FF0A
SR 0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 205

16-bit MCU and DSC Programmer’s Reference Manual

FF1L

Find First One from Left

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

FF1L

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]

Operation:

Max_Shift = 17
Temp = (Ws)
Shift = 1
While ( (Shift < Max_Shift) && !(Temp & 0x8000) )
Temp = Temp << 1
Shift = Shift + 1
If (Shift == Max_Shift)
0 → (Wnd)
Else
Shift → (Wnd)

Status Affected:

C

Encoding:
Description:

1100

1111

1000

0ddd

dppp

ssss

Finds the first occurrence of a ‘1’ starting from the Most Significant bit of
Ws and working towards the Least Significant bit of the word operand.
The bit number result is zero-extended to 16 bits and placed in Wnd.
Bit numbering begins with the Most Significant bit (allocated number 1)
and advances to the Least Significant bit (allocated number 16). A result
of zero indicates a ‘1’ was not found, and the C flag will be set. If a ‘1’ is
found, the C flag is cleared.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

FF1L

W2, W5

Before
Instruction
W2
000A
W5 BBBB
SR
0000

DS70157D-page 206

This instruction operates in Word mode only.

; Find the 1st one from the left in W2
; and store result to W5

After
Instruction
W2
000A
W5
000D
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

FF1L

[W2++], W5

Before
Instruction
W2
2000
W5 BBBB
Data 2000
0000
SR
0000

; Find the 1st one from the left in [W2]
; and store the result to W5
; Post-increment W2

After
Instruction
W2
2002
W5
0000
Data 2000
0000
SR
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 207

16-bit MCU and DSC Programmer’s Reference Manual

FF1R

Find First One from Right

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

FF1R

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]

Operation:

Max_Shift = 17
Temp = (Ws)
Shift = 1
While ( (Shift < Max_Shift) && !(Temp & 0x1) )
Temp = Temp >> 1
Shift = Shift + 1
If (Shift == Max_Shift)
0 → (Wnd)
Else
Shift → (Wnd)

Status Affected:

C

Encoding:
Description:

1100

1111

0000

0ddd

dppp

ssss

Finds the first occurrence of a ‘1’ starting from the Least Significant bit of
Ws and working towards the Most Significant bit of the word operand. The
bit number result is zero-extended to 16 bits and placed in Wnd.
Bit numbering begins with the Least Significant bit (allocated number 1)
and advances to the Most Significant bit (allocated number 16). A result of
zero indicates a ‘1’ was not found, and the C flag will be set. If a ‘1’ is
found, the C flag is cleared.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

FF1R

W1, W9

Before
Instruction
W1
000A
W9 BBBB
SR
0000

DS70157D-page 208

This instruction operates in Word mode only.

; Find the 1st one from the right in W1
; and store the result to W9

After
Instruction
W1
000A
W9
0002
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

FF1R

[W1++], W9

Before
Instruction
W1
2000
W9 BBBB
Data 2000
8000
SR
0000

; Find the 1st one from the right in [W1]
; and store the result to W9
; Post-increment W1

After
Instruction
W1
2002
W9
0010
Data 2000
8000
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 209

16-bit MCU and DSC Programmer’s Reference Manual

GOTO

Unconditional Jump

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

GOTO

Operands:

Expr may be label or expression (but not a literal).
Expr is resolved by the linker to a lit23, where lit23 ∈ [0 ... 8388606].

Operation:

lit23 → PC
NOP → Instruction Register

Status Affected:

None

Expr

Encoding:
1st word

0000

0100

nnnn

nnnn

nnnn

nnn0

2nd word

0000

0000

0000

0000

0nnn

nnnn

Description:

Unconditional jump to anywhere within the 4M instruction word program
memory range. The PC is loaded with the 23-bit literal specified in the
instruction. Since the PC must always reside on an even address boundary,
lit23<0> is ignored.
The ‘n’ bits form the target address.
Note:

Words:

2

Cycles:

2

Example 1:

026000
GOTO
026004
MOV
.
...
.
...
027844 _THERE: MOV
027846
...

PC
SR
Example 2:

Before
Instruction
02 6000
0000

; Jump to _THERE

_THERE
W0, W1

#0x400, W2

Before
Instruction
02 6000
0000

000100 _code:
.
026000
026004

PC
SR

DS70157D-page 210

The linker will resolve the specified expression into the lit23 to be
used.

PC
SR
...
...
GOTO
...

; Code execution
; resumes here

After
Instruction
02 7844
0000
; start of code

_code+2

; Jump to _code+2

PC
SR

After
Instruction
00 0102
0000

© 2009 Microchip Technology Inc.

GOTO

Unconditional Indirect Jump

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0100

0000

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]

Operation:

0 → PC<22:16>
(Wn<15:1>) → PC<15:1>
0 → PC<0>
NOP → Instruction Register

Status Affected:

None

Encoding:

GOTO

0000

Description:

Wn

0001

0000

ssss

Unconditional indirect jump within the first 32K words of program memory.
Zero is loaded into PC<22:16> and the value specified in (Wn) is loaded
into PC<15:1>. Since the PC must always reside on an even address
boundary, Wn<0> is ignored.
The ‘s’ bits select the source register.

Words:

1

Cycles:

2

Example 1:

006000
GOTO
006002
MOV
.
...
.
...
007844 _THERE: MOV
007846
...

W4
PC
SR

Before
Instruction
7844
00 6000
0000

; Jump unconditionally
; to 16-bit value in W4

W4
W0, W1

#0x400, W2

W4
PC
SR

; Code execution
; resumes here

After
Instruction
7844
00 7844
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 211

16-bit MCU and DSC Programmer’s Reference Manual

INC

Increment f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) + 1 → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

INC{.B}

1100

f

{,WREG}

0BDf

ffff

ffff

ffff

Add one to the contents of the file register, and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

INC.B

0x1000

; Increment 0x1000 (Byte mode)

Before
Instruction
Data 1000
8FFF
SR
0000
Example 2:

INC

0x1000, WREG

Before
Instruction
WREG ABCD
Data 1000 8FFF
SR
0000

DS70157D-page 212

After
Instruction
Data 1000
8F00
SR
0101 (DC, C = 1)
; Increment 0x1000 and store to WREG
; (Word mode)

After
Instruction
WREG
9000
Data 1000
8FFF
SR
0108 (DC, N = 1)

© 2009 Microchip Technology Inc.

INC

Increment Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

INC{.B}

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) + 1 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

1000

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

0Bqq

qddd

dppp

ssss

Add 1 to the contents of the source register Ws and place the result in the
destination register Wd. Register direct or indirect addressing may be
used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

INC.B

W1, [++W2]

Before
Instruction
W1
FF7F
W2
2000
Data 2000 ABCD
SR
0000
Example 2:

INC

W1, W2

; Pre-increment W2
; Increment W1 and store to W2
; (Byte mode)

After
Instruction
W1
FF7F
W2
2001
Data 2000
80CD
SR
010C (DC, N, OV = 1)
; Increment W1 and store to W2
; (Word mode)

5
Instruction
Descriptions

Before
Instruction
W1
FF7F
W2
2000
SR
0000

© 2009 Microchip Technology Inc.

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

After
Instruction
W1
FF7F
W2
FF80
SR
0108 (DC, N = 1)

DS70157D-page 213

16-bit MCU and DSC Programmer’s Reference Manual

INC2

Increment f by 2

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) + 2 → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

INC2{.B}

1110

1100

f

{,WREG}

1BDf

ffff

ffff

ffff

Add 2 to the contents of the file register and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note:

Words:

1

Cycles:

1

Example 1:

INC2.B

0x1000

Before
Instruction
Data 1000
8FFF
SR
0000
Example 2:

INC2

; Increment 0x1000 by 2
; (Byte mode)

After
Instruction
Data 1000
8F01
SR
0101 (DC, C = 1)

0x1000, WREG

Before
Instruction
WREG ABCD
Data 1000
8FFF
SR
0000

DS70157D-page 214

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

; Increment 0x1000 by 2 and store to WREG
; (Word mode)

After
Instruction
WREG
9001
Data 1000
8FFF
SR
0108 (DC, N = 1)

© 2009 Microchip Technology Inc.

INC2

Increment Ws by 2

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

INC2{.B}

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) + 2 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

1110

1000

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

1Bqq

qddd

dppp

ssss

Add 2 to the contents of the source register Ws and place the result in the
destination register Wd. Register direct or indirect addressing may be used
for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

INC2.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W1, [++W2]

Before
Instruction
W1
FF7F
W2
2000
Data 2000 ABCD
SR
0000
Example 2:

INC2

W1, W2

© 2009 Microchip Technology Inc.

After
Instruction
W1
FF7F
W2
2001
Data 2000
81CD
SR
010C (DC, N, OV = 1)
; Increment W1 by 2 and store to W2
; (word mode)

5
Instruction
Descriptions

Before
Instruction
W1
FF7F
W2
2000
SR
0000

; Pre-increment W2
; Increment by 2 and store to W1
; (Byte mode)

After
Instruction
W1
FF7F
W2
FF81
SR
0108 (DC, N = 1)

DS70157D-page 215

16-bit MCU and DSC Programmer’s Reference Manual

IOR

Inclusive OR f and WREG

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f).IOR.(WREG) → destination designated by D

Status Affected:

N, Z

Encoding:

1011

Description:

IOR{.B}

f

0111

{,WREG}

0BDf

ffff

ffff

ffff

Compute the logical inclusive OR operation of the contents of the working
register WREG and the contents of the file register and place the result in
the destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG. If
WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

IOR.B

0x1000

Before
Instruction
WREG
1234
Data 1000
FF00
SR
0000
Example 2:

IOR

0x1000, WREG

; IOR WREG to (0x1000) (Byte mode)
; (Byte mode)

After
Instruction
WREG
1234
Data 1000
FF34
SR
0000
; IOR (0x1000) to WREG
; (Word mode)

Before
After
Instruction
Instruction
WREG
1234
WREG
1FBF
Data 1000
0FAB
Data 1000
0FAB
SR
0008 (N = 1)
SR
0000

DS70157D-page 216

© 2009 Microchip Technology Inc.

IOR

Inclusive OR Literal and Wn

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

lit10.IOR.(Wn) → Wn

Status Affected:

N, Z

Encoding:

IOR{.B}

1011

Description:

0011

#lit10,

Wn

0Bkk

kkkk

kkkk

dddd

Compute the logical inclusive OR operation of the 10-bit literal operand
and the contents of the working register Wn and place the result back into
the working register Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an unsigned
value [0:255]. See Section 4.6 “Using 10-bit Literal Operands”
for information on using 10-bit literal operands in Byte mode.

Words:

1

Cycles:

1

Example 1:

IOR.B #0xAA, W9

Before
Instruction
W9
1234
SR
0000
Example 2:

IOR

#0x2AA, W4

Before
Instruction
W4
A34D
SR
0000

; IOR 0xAA to W9
; (Byte mode)

After
Instruction
W9
12BE
SR
0008 (N = 1)
; IOR 0x2AA to W4
; (Word mode)

After
Instruction
W4
A3EF
SR
0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 217

16-bit MCU and DSC Programmer’s Reference Manual

IOR

Inclusive OR Wb and Short Literal

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

IOR{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb).IOR.lit5 → Wd

Status Affected:

N, Z

Encoding:
Description:

0111

0www

wBqq

qddd

d11k

kkkk

Compute the logical inclusive OR operation of the contents of the base
register Wb and the 5-bit literal operand and place the result in the
destination register Wd. Register direct addressing must be used for Wb.
Either register direct or indirect addressing may be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

IOR.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W1, #0x5, [W9++]

Before
Instruction
W1 AAAA
W9
2000
Data 2000
0000
SR
0000
Example 2:

IOR

W1, #0x0, W9

Before
Instruction
W1
0000
W9
A34D
SR
0000

DS70157D-page 218

; IOR W1 and 0x5 (Byte mode)
; Store to [W9]
; Post-increment W9

After
Instruction
W1 AAAA
W9
2001
Data 2000
00AF
SR
0008 (N = 1)
; IOR W1 with 0x0 (Word mode)
; Store to W9

After
Instruction
W1
0000
W9
0000
SR
0002 (Z = 1)

© 2009 Microchip Technology Inc.

IOR

Inclusive OR Wb and Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

IOR{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb).IOR.(Ws) → Wd

Status Affected:

N, Z

Encoding:
Description:

0111

Wb,

0www

Ws,

wBqq

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Compute the logical inclusive OR operation of the contents of the source
register Ws and the contents of the base register Wb, and place the result in
the destination register Wd. Register direct addressing must be used for Wb.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

IOR.B

W1, [W5++], [W9++]

; IOR W1 and [W5] (Byte mode)
; Store result to [W9]
; Post-increment W5 and W9

After
Instruction
W1 AAAA
W5
2001
W9
2401
Data 2000
1155
Data 2400
00FF
SR
0008 (N = 1)

5
Instruction
Descriptions

Before
Instruction
W1 AAAA
W5
2000
W9
2400
Data 2000
1155
Data 2400
0000
SR
0000

© 2009 Microchip Technology Inc.

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

DS70157D-page 219

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

IOR

W1
W5
W9
SR

DS70157D-page 220

W1, W5, W9

Before
Instruction
AAAA
5555
A34D
0000

; IOR W1 and W5 (Word mode)
; Store the result to W9

After
Instruction
W1 AAAA
W5
5555
W9
FFFF
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

LAC

Load Accumulator

Implemented in:

Syntax:

PIC24F

{label:}

PIC24H

LAC

dsPIC30F

dsPIC33F

X

X

Ws,

{#Slit4,}

Acc

[Ws],
[Ws++],
[Ws--],
[--Ws],
[++Ws],
[Ws+Wb],
Operands:

Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]
Slit4 ∈ [-8 ... +7]
Acc ∈ [A,B]

Operation:

ShiftSlit4(Extend(Ws)) → Acc(A or B)

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:
Description:

1100

1010

Awww

wrrr

rggg

ssss

Read the contents of the source register, optionally perform a signed 4-bit
shift and store the result in the specified accumulator. The shift range is -8:7,
where a negative operand indicates an arithmetic left shift and a positive
operand indicates an arithmetic right shift. The data stored in the source
register is assumed to be 1.15 fractional data and is automatically
sign-extended (through bit 39) and zero-backfilled (bits [15:0]), prior to
shifting.
The ‘A’ bit specifies the destination accumulator.
The ‘w’ bits specify the offset register Wb.
The ‘r’ bits encode the accumulator pre-shift.
The ‘g’ bits select the source Address mode.
The ‘s’ bits specify the source register Ws.
Note:

Words:

1

Cycles:

1

Example 1:

LAC

© 2009 Microchip Technology Inc.

[W4++], #-3, B

Before
Instruction
2000
00 5125 ABCD
1221
0000

;
;
;
;
;

Load ACCB with [W4] << 3
Contents of [W4] do not change
Post increment W4
Assume saturation disabled
(SATB = 0)

W4
ACCB
Data 2000
SR

After
Instruction
2002
FF 9108 0000
1221
4800 (OB, OAB = 1)

DS70157D-page 221

5
Instruction
Descriptions

W4
ACCB
Data 2000
SR

If the operation moves more than sign-extension data into the
upper Accumulator register (AccxU), or causes a saturation, the
appropriate overflow and saturation bits will be set.

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

DS70157D-page 222

LAC

[--W2], #7, A

W2
ACCA
Data 4000
Data 4002
SR

Before
Instruction
4002
00 5125 ABCD
9108
1221
0000

;
;
;
;
;

Pre-decrement W2
Load ACCA with [W2] >> 7
Contents of [W2] do not change
Assume saturation disabled
(SATA = 0)

W2
ACCA
Data 4000
Data 4002
SR

After
Instruction
4000
FF FF22 1000
9108
1221
0000

© 2009 Microchip Technology Inc.

LNK

Allocate Stack Frame

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit14 ∈ [0 ... 16382]

Operation:

(W14) → (TOS)
(W15) + 2 → W15
(W15) → W14
(W15) + lit14 → W15

Status Affected:

None

Encoding:

1111

Description:

LNK

1010

#lit14

00kk

kkkk

kkkk

kkk0

This instruction allocates a Stack Frame of size lit14 bytes for a
subroutine calling sequence. The Stack Frame is allocated by PUSHing
the contents of the Frame Pointer (W14) onto the stack, storing the
updated Stack Pointer (W15) to the Frame Pointer and then incrementing
the Stack Pointer by the unsigned 14-bit literal operand. This instruction
supports a maximum Stack Frame of 16382 bytes.
The ‘k’ bits specify the size of the Stack Frame.
Note:

Words:

1

Cycles:

1

Example 1:

LNK

W14
W15
Data 2000
SR

#0xA0

Since the Stack Pointer can only reside on a word boundary,
lit14 must be even.

; Allocate a stack frame of 160 bytes

Before
Instruction
2000
2000
0000
0000

W14
W15
Data 2000
SR

After
Instruction
2002
20A2
2000
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 223

16-bit MCU and DSC Programmer’s Reference Manual

LSR

Logical Shift Right f

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

LSR{.B}

f

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
0 → Dest<7>
(f<7:1>) → Dest<6:0>
(f<0>) → C
For word operation:
0 → Dest<15>
(f<15:1>) → Dest<14:0>
(f<0>) → C
C

0

Status Affected:

N, Z, C

Encoding:

1101

Description:

{,WREG}

0101

0BDf

ffff

ffff

ffff

Shift the contents of the file register one bit to the right and place the result
in the destination register. The Least Significant bit of the file register is
shifted into the Carry bit of the STATUS register. Zero is shifted into the
Most Significant bit of the destination register.
The optional WREG operand determines the destination register. If WREG
is specified, the result is stored in WREG. If WREG is not specified, the
result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

LSR.B

0x600

; Logically shift right (0x600) by one
; (Byte mode)

Before
Instruction
Data 600
55FF
SR
0000
Example 2:

LSR

0x600, WREG

Before
Instruction
Data 600
55FF
WREG
0000
SR
0000

DS70157D-page 224

After
Instruction
Data 600
557F
SR
0001 (C = 1)
; Logically shift right (0x600) by one
; Store to WREG
; (Word mode)

After
Instruction
Data 600
55FF
WREG
2AFF
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

LSR

Logical Shift Right Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

LSR{.B}

Ws,
[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
0 → Wd<7>
(Ws<7:1>) → Wd<6:0>
(Ws<0>) → C
For word operation:
0 → Wd<15>
(Ws<15:1>) → Wd<14:0>
(Ws<0>) → C
C

0

Status Affected:

N, Z, C

Encoding:
Description:

Wd

1101

0001

0Bqq

qddd

dppp

ssss

Shift the contents of the source register Ws one bit to the right, and place
the result in the destination register Wd. The Least Significant bit of Ws is
shifted into the Carry bit of the STATUS register. Zero is shifted into the
Most Significant bit of Wd. Either register direct or indirect addressing
may be used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

LSR.B

W0, W1

© 2009 Microchip Technology Inc.

5

; LSR W0 (Byte mode)
; Store result to W1

Instruction
Descriptions

Before
Instruction
W0
FF03
W1
2378
SR
0000

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

After
Instruction
W0
FF03
W1
2301
SR
0001 (C = 1)

DS70157D-page 225

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

LSR

W0, W1

Before
Instruction
W0
8000
W1
2378
SR
0000

DS70157D-page 226

; LSR W0 (Word mode)
; Store the result to W1

After
Instruction
W0
8000
W1
4000
SR
0000

© 2009 Microchip Technology Inc.

LSR

Logical Shift Right by Short Literal

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit4 ∈ [0 ... 15]
Wnd ∈ [W0 ... W15]

Operation:

lit4<3:0> → Shift_Val
0 → Wnd<15:15-Shift_Val + 1>
Wb<15:Shift_Val> → Wnd<15-Shift_Val:0>

Status Affected:

N, Z

Encoding:

1101

Description:

LSR

1110

Wb,

0www

#lit4,

Wnd

wddd

d100

kkkk

Logical shift right the contents of the source register Wb by the 4-bit
unsigned literal and store the result in the destination register Wnd. Direct
addressing must be used for Wb and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand.
Note:

Words:

1

Cycles:

1

Example 1:

LSR

This instruction operates in Word mode only.

W4, #14, W5

Before
Instruction
W4
C800
W5
1200
SR
0000
Example 2:

LSR

W4, #1, W5

Before
Instruction
W4
0505
W5
F000
SR
0000

; LSR W4 by 14
; Store result to W5

After
Instruction
W4
C800
W5
0003
SR
0000
; LSR W4 by 1
; Store result to W5

After
Instruction
W4
0505
W5
0282
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 227

16-bit MCU and DSC Programmer’s Reference Manual

LSR

Logical Shift Right by Wns

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wns ∈ [W0 ...W15]
Wnd ∈ [W0 ... W15]

Operation:

Wns<4:0> → Shift_Val
0 → Wnd<15:15-Shift_Val + 1>
Wb<15:Shift_Val> → Wnd<15 - Shift_Val:0>

Status Affected:

N, Z

Encoding:

1101

Description:

LSR

1110

Wb,

0www

Wns,

Wnd

wddd

d000

ssss

Logical shift right the contents of the source register Wb by the 5 Least
Significant bits of Wns (only up to 15 positions) and store the result in the
destination register Wnd. Direct addressing must be used for Wb and
Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: If Wns is greater than 15, Wnd will be loaded with 0x0.

Words:

1

Cycles:

1

Example 1:

LSR

W0, W1, W2

Before
Instruction
W0
C00C
W1
0001
W2
2390
SR
0000
Example 2:

LSR

W5, W4, W3

Before
Instruction
W3
DD43
W4
000C
W5
0800
SR
0000

DS70157D-page 228

; LSR W0 by W1
; Store result to W2

After
Instruction
W0
C00C
W1
0001
W2
6006
SR
0000
; LSR W5 by W4
; Store result to W3

After
Instruction
W3
0000
W4
000C
W5
0800
SR
0002 (Z = 1)

© 2009 Microchip Technology Inc.

MAC

Multiply and Accumulate

Implemented in:

PIC24F

PIC24H

dsPIC30F dsPIC33F
X

Syntax:

{label:} MAC

Wm*Wn, Acc {,[Wx], Wxd}

X
{,[Wy], Wyd}

{,AWB}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx,
Wxd}

{,[Wy] – = ky, Wyd}

{,[W9 + W12],
Wxd}

{,[W11 + W12],
Wyd}

Operands:

Wm * Wn ∈ [W4 * W5, W4 * W6, W4 * W7, W5 * W6, W5 * W7, W6 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]
AWB ∈ [W13, [W13] + = 2]

Operation:

(Acc(A or B)) + (Wm) * (Wn) → Acc(A or B)
([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy
(Acc(B or A)) rounded → AWB

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:
Description:

1100

0mmm

A0xx

yyii

iijj

jjaa

Multiply the contents of two working registers, optionally prefetch
operands in preparation for another MAC type instruction and optionally
store the unspecified accumulator results. The 32-bit result of the signed
multiply is sign-extended to 40 bits and added to the specified
accumulator.
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations,
which support indirect and register offset addressing, as described in
Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional
store of the “other” accumulator, as described in
Section 4.14.4 “MAC Write Back”.
The ‘m’ bits select the operand registers Wm and Wn for the multiply.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
The ‘a’ bits select the accumulator Write Back destination.
Note:

Words:

1

Cycles:

1

The IF bit, CORCON<0>, determines if the multiply is
fractional or an integer.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 229

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

MAC W4*W5, A, [W8]+=6, W4, [W10]+=2, W5
; Multiply W4*W5 and add to ACCA
; Fetch [W8] to W4, Post-increment W8 by 6
; Fetch [W10] to W5, Post-increment W10 by 2
; CORCON = 0x00C0 (fractional multiply, normal saturation)

W4
W5
W8
W10
ACCA
Data 0A00
Data 1800
CORCON
SR
Example 2:

W4
W5
W8
W10
ACCA
Data 0A00
Data 1800
CORCON
SR

After
Instruction
2567
909C
0A06
1802
00 472D 2400
2567
909C
00C0
0000

MAC W4*W5, A, [W8]-=2, W4, [W10]+=2, W5, W13
; Multiply W4*W5 and add to ACCA
; Fetch [W8] to W4, Post-decrement W8 by 2
; Fetch [W10] to W5, Post-increment W10 by 2
; Write Back ACCB to W13
; CORCON = 0x00D0 (fractional multiply, super saturation)

W4
W5
W8
W10
W13
ACCA
ACCB
Data 0A00
Data 1800
CORCON
SR

DS70157D-page 230

Before
Instruction
A022
B900
0A00
1800
00 1200 0000
2567
909C
00C0
0000

Before
Instruction
1000
3000
0A00
1800
2000
23 5000 2000
00 0000 8F4C
5BBE
C967
00D0
0000

W4
W5
W8
W10
W13
ACCA
ACCB
Data 0A00
Data 1800
CORCON
SR

After
Instruction
5BBE
C967
09FE
1802
0001
23 5600 2000
00 0000 1F4C
5BBE
C967
00D0
8800 (OA, OAB = 1)

© 2009 Microchip Technology Inc.

MAC

Square and Accumulate

Implemented in:

PIC24F

PIC24H

dsPIC30F dsPIC33F
X

Syntax:

{label:} MAC

X

Wm*Wm, Acc {,[Wx], Wxd}

{,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands:

Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]

Operation:

(Acc(A or B)) + (Wm) * (Wm) → Acc(A or B)
([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:
Description:

1111

00mm

A0xx

yyii

iijj

jj00

Square the contents of a working register, optionally prefetch operands in
preparation for another MAC type instruction and optionally store the
unspecified accumulator results. The 32-bit result of the signed multiply is
sign-extended to 40 bits and added to the specified accumulator.
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations,
which support indirect and register offset addressing, as described in
Section 4.14.1 “MAC Prefetches”.
The ‘m’ bits select the operand register Wm for the square.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
Note:

Words:

1

Cycles:

1

The IF bit, CORCON<0>, determines if the multiply is fractional
or an integer.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 231

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

MAC W4*W4, B, [W9+W12], W4, [W10]-=2, W5
; Square W4 and add to ACCB
; Fetch [W9+W12] to W4
; Fetch [W10] to W5, Post-decrement W10 by 2
; CORCON = 0x00C0 (fractional multiply, normal saturation)

W4
W5
W9
W10
W12
ACCB
Data 0C20
Data 1900
CORCON
SR
Example 2:

W4
W5
W9
W10
W12
ACCB
Data 0C20
Data 1900
CORCON
SR

After
Instruction
A230
650B
0C00
18FE
0020
00 67CD 0908
A230
650B
00C0
0000

MAC W7*W7, A, [W11]-=2, W7
; Square W7 and add to ACCA
; Fetch [W11] to W7, Post-decrement W11 by 2
; CORCON = 0x00D0 (fractional multiply, super saturation)

W7
W11
ACCA
Data 2000
CORCON
SR

DS70157D-page 232

Before
Instruction
A022
B200
0C00
1900
0020
00 2000 0000
A230
650B
00C0
0000

Before
Instruction
76AE
2000
FE 9834 4500
23FF
00D0
0000

W7
W11
ACCA
Data 2000
CORCON
SR

After
Instruction
23FF
1FFE
FF 063E 0188
23FF
00D0
8800 (OA, OAB = 1)

© 2009 Microchip Technology Inc.

MOV

Move f to Destination

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) → destination designated by D

Status Affected:

N, Z

Encoding:

1011

Description:

MOV{.B}

1111

f

{,WREG}

1BDf

ffff

ffff

ffff

Move the contents of the specified file register to the destination register.
The optional WREG operand determines the destination register. If
WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored back to the file register and the only effect is
to modify the STATUS register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: When moving word data from file register memory, the “MOV f
to Wnd” (page 5-147) instruction allows any working register
(W0:W15) to be the destination register.

Words:

1

Cycles:

1

Example 1:

MOV.B

TMR0, WREG

Before
Instruction
WREG (W0)
9080
TMR0
2355
SR
0000
Example 2:

MOV

0x800

Before
Instruction
Data 0800 B29F
SR
0000

; move (TMR0) to WREG (Byte mode)

After
Instruction
WREG (W0)
9055
TMR0
2355
SR
0000
; update SR based on (0x800) (Word mode)

After
Instruction
Data 0800 B29F
SR
0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 233

16-bit MCU and DSC Programmer’s Reference Manual

MOV

Move WREG to f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(WREG) → f

Status Affected:

None

Encoding:

1011

Description:

MOV{.B}

0111

WREG,

f

1B1f

ffff

ffff

ffff

Move the contents of the default working register WREG into the
specified file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
2: The WREG is set to working register W0.
3: When moving word data from the working register array to file
register memory, the “MOV Wns to f” (page 5-148) instruction
allows any working register (W0:W15) to be the source register.

Words:

1

Cycles:

1

Example 1:

MOV.B

WREG, 0x801

Before
Instruction
WREG (W0)
98F3
Data 0800
4509
SR
0000
Example 2:

MOV

DS70157D-page 234

After
Instruction
WREG (W0)
98F3
Data 0800
F309
SR
0008 (N = 1)

WREG, DISICNT

Before
Instruction
WREG (W0)
00A0
DISICNT
0000
SR
0000

; move WREG to 0x801 (Byte mode)

; move WREG to DISICNT

After
Instruction
WREG (W0)
00A0
DISICNT
00A0
SR
0000

© 2009 Microchip Technology Inc.

MOV

Move f to Wnd

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 65534]
Wnd ∈ [W0 ... W15]

Operation:

(f) → Wnd

Status Affected:

None

Encoding:

1000

Description:

MOV

f,

0fff

Wnd

ffff

ffff

ffff

dddd

Move the word contents of the specified file register to Wnd. The file
register may reside anywhere in the 32K words of data memory, but must
be word-aligned. Register direct addressing must be used for Wnd.
The ‘f’ bits select the address of the file register.
The ‘d’ bits select the destination register.
Note 1: This instruction operates on word operands only.
2: Since the file register address must be word-aligned, only the
upper 15 bits of the file register address are encoded (bit 0 is
assumed to be ‘0’).
3: To move a byte of data from file register memory, the “MOV f
to Destination” instruction (page 5-145) may be used.

Words:

1

Cycles:

1

Example 1:

MOV

CORCON, W12

Before
Instruction
W12
78FA
CORCON
00F0
SR
0000
Example 2:

MOV

After
Instruction
W12
00F0
CORCON
00F0
SR
0000

0x27FE, W3

Before
Instruction
W3
0035
Data 27FE ABCD
SR
0000

; move CORCON to W12

; move (0x27FE) to W3

After
Instruction
W3 ABCD
Data 27FE ABCD
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 235

16-bit MCU and DSC Programmer’s Reference Manual

MOV

Move Wns to f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 65534]
Wns ∈ [W0 ... W15]

Operation:

(Wns) → f

Status Affected:

None

Encoding:

1000

Description:

MOV

1fff

Wns,

f

ffff

ffff

ffff

ssss

Move the word contents of the working register Wns to the specified file
register. The file register may reside anywhere in the 32K words of data
memory, but must be word-aligned. Register direct addressing must be
used for Wn.
The ‘f’ bits select the address of the file register.
The ‘s’ bits select the source register.
Note 1: This instruction operates on word operands only.
2: Since the file register address must be word-aligned, only the
upper 15 bits of the file register address are encoded (bit 0 is
assumed to be ‘0’).
3: To move a byte of data to file register memory, the “MOV WREG
to f” instruction (page 5-146) may be used.

Words:

1

Cycles:

1

Example 1:

MOV

W4, XMDOSRT

Before
Instruction
W4
1200
XMODSRT
1340
SR
0000
Example 2:

MOV

DS70157D-page 236

After
Instruction
W4
1200
XMODSRT
1200
SR
0000

W8, 0x1222

Before
Instruction
W8
F200
Data 1222
FD88
SR
0000

; move W4 to XMODSRT

; move W8 to data address 0x1222

After
Instruction
W8
F200
Data 1222
F200
SR
0000

© 2009 Microchip Technology Inc.

MOV.B

Move 8-bit Literal to Wnd

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

MOV.B

Operands:

lit8 ∈ [0 ... 255]
Wnd ∈ [W0 ... W15]

Operation:

lit8 → Wnd

Status Affected:

None

Encoding:
Description:

1011

0011

#lit8,

Wnd

1100

kkkk

kkkk

dddd

The unsigned 8-bit literal ‘k’ is loaded into the lower byte of Wnd. The
upper byte of Wnd is not changed. Register direct addressing must be
used for Wnd.
The ‘k’ bits specify the value of the literal.
The ‘d’ bits select the address of the working register.
Note:

Words:

1

Cycles:

1

Example 1:

MOV.B

This instruction operates in Byte mode and the .B extension
must be provided.

#0x17, W5

Before
Instruction
W5
7899
SR
0000
Example 2:

MOV.B

#0xFE, W9

Before
Instruction
W9
AB23
SR
0000

; load W5 with #0x17 (Byte mode)

After
Instruction
W5
7817
SR
0000
; load W9 with #0xFE (Byte mode)

After
Instruction
W9
ABFE
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 237

16-bit MCU and DSC Programmer’s Reference Manual

MOV

Move 16-bit Literal to Wnd

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit16 ∈ [-32768 ... 65535]
Wnd ∈ [W0 ... W15]

Operation:

lit16 → Wnd

Status Affected:

None

Encoding:

MOV

0010

Description:

kkkk

#lit16,

Wnd

kkkk

kkkk

kkkk

dddd

The 16-bit literal ‘k’ is loaded into Wnd. Register direct addressing must
be used for Wnd.
The ‘k’ bits specify the value of the literal.
The ‘d’ bits select the address of the working register.
Note 1: This instruction operates only in Word mode.
2: The literal may be specified as a signed value [-32768:32767],
or unsigned value [0:65535].

Words:

1

Cycles:

1

Example 1:

MOV

#0x4231, W13

Before
Instruction
W13
091B
SR
0000
Example 2:

Example 3:

MOV

#0x4, W2

After
Instruction
W13
4231
SR
0000
; load W2 with #0x4

Before
Instruction
W2
B004
SR
0000

After
Instruction
W2
0004
SR
0000

MOV

; load W8 with #-1000

#-1000, W8

Before
Instruction
W8
23FF
SR
0000

DS70157D-page 238

; load W13 with #0x4231

After
Instruction
W8
FC18
SR
0000

© 2009 Microchip Technology Inc.

MOV

Move [Ws with offset] to Wnd

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Ws ∈ [W0 ... W15]
Slit10 ∈ [-512 ... 511] for byte operation
Slit10 ∈ [-1024 ... 1022] (even only) for word operation
Wnd ∈ [W0 ... W15]

Operation:

[Ws + Slit10] → Wnd

Status Affected:

None

Encoding:

1001

Description:

MOV{.B}

0kkk

[Ws + Slit10], Wnd

kBkk

kddd

dkkk

ssss

The contents of [Ws + Slit10] are loaded into Wnd. In Word mode, the
range of Slit10 is increased to [-1024 ... 1022] and Slit10 must be even to
maintain word address alignment. Register indirect addressing must be
used for the source, and direct addressing must be used for Wnd.
The ‘k’ bits specify the value of the literal.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
2: In Byte mode, the range of Slit10 is not reduced as specified in
Section 4.6 “Using 10-bit Literal Operands”, since the literal
represents an address offset from Ws.

Words:

1

Cycles:

1

Example 1:

MOV.B

[W8+0x13], W10

Before
Instruction
W8
1008
W10
4009
Data 101A
3312
SR
0000
Example 2:

MOV

; load W2 with [W4+0x3E8]
; (Word mode)

5

After
Instruction
W2
5634
W4
0800
Data 0BE8
5634
SR
0000

Instruction
Descriptions

© 2009 Microchip Technology Inc.

After
Instruction
W8
1008
W10
4033
Data 101A
3312
SR
0000

[W4+0x3E8], W2

Before
Instruction
W2
9088
W4
0800
Data 0BE8
5634
SR
0000

; load W10 with [W8+0x13]
; (Byte mode)

DS70157D-page 239

16-bit MCU and DSC Programmer’s Reference Manual

MOV

Move Wns to [Wd with offset]

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wns ∈ [W0 ... W15]
Slit10 ∈ [-512 ... 511] in Byte mode
Slit10 ∈ [-1024 ... 1022] (even only) in Word mode
Wd ∈ [W0 ... W15]

Operation:

(Wns) → [Wd + Slit10]

Status Affected:

None

Encoding:

1001

Description:

MOV{.B}

1kkk

Wns,

[Wd + Slit10]

kBkk

kddd

dkkk

ssss

The contents of Wns are stored to [Wd + Slit10]. In Word mode, the range
of Slit10 is increased to [-1024 ... 1022] and Slit10 must be even to
maintain word address alignment. Register direct addressing must be
used for Wns, and indirect addressing must be used for the destination.
The ‘k’ bits specify the value of the literal.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘d’ bits select the destination register.
The ‘s’ bits select the address of the destination register.
Note 1: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
2: In Byte mode, the range of Slit10 is not reduced as specified in
Section 4.6 “Using 10-bit Literal Operands”, since the literal
represents an address offset from Wd.

Words:

1

Cycles:

1

Example 1:

MOV.B

W0, [W1+0x7]

Before
Instruction
W0
9015
W1
1800
Data 1806
2345
SR
0000
Example 2:

MOV

DS70157D-page 240

After
Instruction
W0
9015
W1
1800
Data 1806
1545
SR
0000

W11, [W1-0x400]

Before
Instruction
W1
1000
W11
8813
Data 0C00
FFEA
SR
0000

; store W0 to [W1+0x7]
; (Byte mode)

; store W11 to [W1-0x400]
; (Word mode)

After
Instruction
W1
1000
W11
8813
Data 0C00
8813
SR
0000

© 2009 Microchip Technology Inc.

MOV

Move Ws to Wd

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

MOV{.B}

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[--Ws],

[--Wd]

[++Ws],

[++Wd]

[Ws + Wb], [Wd + Wb]
Operands:

Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) → Wd

Status Affected:

None

Encoding:
Description:

0111

1www

wBhh

hddd

dggg

ssss

Move the contents of the source register into the destination register.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘w’ bits define the offset register Wb.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘h’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘g’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.
2: When Register Offset Addressing mode is used for both the
source and destination, the offset must be the same because
the ‘w’ encoding bits are shared by Ws and Wd.
3: The instruction “PUSH Ws” translates to MOV Ws, [W15++].
4: The instruction “POP Wd” translates to MOV [--W15], Wd.

Words:

1

Cycles:

1

Example 1:

MOV.B

[W0--], W4

© 2009 Microchip Technology Inc.

After
Instruction
W0
0A00
W4
2989
Data 0A00
8988
SR
0000

5
Instruction
Descriptions

Before
Instruction
W0
0A01
W4
2976
Data 0A00
8988
SR
0000

; Move [W0] to W4 (Byte mode)
; Post-decrement W0

DS70157D-page 241

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

MOV

[W6++], [W2+W3]

Before
Instruction
W2
0800
W3
0040
W6
1228
Data 0840
9870
Data 1228
0690
SR
0000

DS70157D-page 242

; Move [W6] to [W2+W3] (Word mode)
; Post-increment W6

After
Instruction
W2
0800
W3
0040
W6
122A
Data 0840
0690
Data 1228
0690
SR
0000

© 2009 Microchip Technology Inc.

MOV.D

Double Word Move from Source to Wnd

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

MOV.D

Wns,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Wns ∈ [W0, W2, W4 ... W14]
Ws ∈ [W0 ... W15]
Wnd ∈ [W0, W2, W4 ... W14]

Operation:

For direct addressing of source:
Wns → Wnd
Wns + 1 → Wnd + 1
For indirect addressing of source:
See Description

Status Affected:

None

Encoding:
Description:

1011

1110

0000

0ddd

0ppp

ssss

Move the double word specified by the source to a destination working
register pair (Wnd:Wnd + 1). If register direct addressing is used for the
source, the contents of two successive working registers (Wns:Wns + 1)
are moved to Wnd:Wnd + 1. If indirect addressing is used for the source,
Ws specifies the effective address for the least significant word of the
double word. Any pre/post-increment or pre/post-decrement will adjust Ws
by 4 bytes to accommodate for the double word.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the address of the first source register.
Note 1: This instruction only operates on double words. See Figure 4-3
for information on how double words are aligned in memory.
2: Wnd must be an even working register.
3: The instruction “POP.D Wnd” translates to MOV.D [--W15],
Wnd.

Words:

1

Cycles:

2

Example 1:

MOV.D

W2, W6

© 2009 Microchip Technology Inc.

5

After
Instruction
W2
12FB
W3
9877
W6
12FB
W7
9877
SR
0000

Instruction
Descriptions

Before
Instruction
W2
12FB
W3
9877
W6
9833
W7
FCC6
SR
0000

; Move W2 to W6 (Double mode)

DS70157D-page 243

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

MOV.D

[W7--], W4

Before
Instruction
W4
B012
W5
FD89
W7
0900
Data 0900
A319
Data 0902
9927
SR
0000

DS70157D-page 244

; Move [W7] to W4 (Double mode)
; Post-decrement W7

After
Instruction
W4
A319
W5
9927
W7
08FC
Data 0900
A319
Data 0902
9927
SR
0000

© 2009 Microchip Technology Inc.

MOVSAC

Prefetch Operands and Store Accumulator

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X
Syntax:

{label:} MOVSAC

Acc

{,[Wx], Wxd}

X
{,[Wy], Wyd}

{,AWB}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands:

Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]
AWB ∈ [W13, [W13] + = 2]

Operation:

([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy
(Acc(B or A)) rounded → AWB

Status Affected:

None

Encoding:
Description:

1100

0111

A0xx

yyii

iijj

jjaa

Optionally prefetch operands in preparation for another MAC type
instruction and optionally store the unspecified accumulator results. Even
though an accumulator operation is not performed in this instruction, an
accumulator must be specified to designate which accumulator to write
back.
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations
which support indirect and register offset addressing, as described in
Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional
store of the “other” accumulator, as described in
Section 4.14.4 “MAC Write Back”.
The ‘A’ bit selects the other accumulator used for write back.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
The ‘a’ bits select the accumulator Write Back destination.

Words:

1

Cycles:

1

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 245

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

MOVSAC
; Fetch
; Fetch
; Store

W6
W7
W9
W11
W13
ACCA
Data 0800
Data 1900
SR
Example 2:

DS70157D-page 246

Before
Instruction
A022
B200
0800
1900
0020
00 3290 5968
7811
B2AF
0000

MOVSAC
; Fetch
; Fetch
; Store

W4
W6
W9
W11
W12
W13
ACCB
Data 1200
Data 2024
Data 2300
SR

B, [W9], W6, [W11]+=4, W7, W13
[W9] to W6
[W11] to W7, Post-increment W11 by 4
ACCA to W13

W6
W7
W9
W11
W13
ACCA
Data 0800
Data 1900
SR

After
Instruction
7811
B2AF
0800
1904
3290
00 3290 5968
7811
B2AF
0000

A, [W9]-=2, W4, [W11+W12], W6, [W13]+=2
[W9] to W4, Post-decrement W9 by 2
[W11+W12] to W6
ACCB to [W13], Post-increment W13 by 2

Before
Instruction
76AE
2000
1200
2000
0024
2300
00 9834 4500
BB00
52CE
23FF
0000

W4
W6
W9
W11
W12
W13
ACCB
Data 1200
Data 2024
Data 2300
SR

After
Instruction
BB00
52CE
11FE
2000
0024
2302
00 9834 4500
BB00
52CE
9834
0000

© 2009 Microchip Technology Inc.

MPY

Multiply Wm by Wn to Accumulator

Implemented in:

Syntax:

PIC24F

{label:} MPY

PIC24H

Wm * Wn,
Acc

dsPIC30F

dsPIC33F

X

X

{,[Wx], Wxd}

{,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands:

Wm * Wn ∈ [W4 * W5, W4 * W6, W4 * W7, W5 * W6, W5 * W7, W6 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]
AWB ∈ [W13], [W13] + = 2

Operation:

(Wm) * (Wn) → Acc(A or B)
([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:
Description:

1100

0mmm

A0xx

yyii

iijj

jj11

Multiply the contents of two working registers, optionally prefetch
operands in preparation for another MAC type instruction and optionally
store the unspecified accumulator results. The 32-bit result of the signed
multiply is sign-extended to 40 bits and stored to the specified
accumulator.
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations
which support indirect and register offset addressing, as described in
Section 4.14.1 “MAC Prefetches”.
The ‘m’ bits select the operand registers Wm and Wn for the multiply:
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
Note:

Words:

1

Cycles:

1

The IF bit, CORCON<0>, determines if the multiply is
fractional or an integer.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 247

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

MPY
;
;
;
;

W4
W5
W6
W7
W8
W10
ACCA
Data 1780
Data 2400
CORCON
SR
Example 2:

Before
Instruction
C000
9000
0800
B200
1780
2400
FF F780 2087
671F
E3DC
0000
0000

W4
W5
W6
W7
W8
W10
ACCA
Data 1780
Data 2400
CORCON
SR

After
Instruction
C000
9000
671F
E3DC
1782
23FE
00 3800 0000
671F
E3DC
0000
0000

MPY W6*W7, B, [W8]+=2, W4, [W10]-=2, W5
; Multiply W6*W7 and store to ACCB
; Fetch [W8] to W4, Post-increment W8 by 2
; Fetch [W10] to W5, Post-decrement W10 by 2
; CORCON = 0x0000 (fractional multiply, no saturation)

W4
W5
W6
W7
W8
W10
ACCB
Data 1782
Data 23FE
CORCON
SR

DS70157D-page 248

W4*W5, A, [W8]+=2, W6, [W10]-=2, W7

Multiply W4*W5 and store to ACCA
Fetch [W8] to W6, Post-increment W8 by 2
Fetch [W10] to W7, Post-decrement W10 by 2
CORCON = 0x0000 (fractional multiply, no saturation)

Before
Instruction
C000
9000
671F
E3DC
1782
23FE
00 9834 4500
8FDC
0078
0000
0000

W4
W5
W6
W7
W8
W10
ACCB
Data 1782
Data 23FE
CORCON
SR

After
Instruction
8FDC
0078
671F
E3DC
1784
23FC
FF E954 3748
8FDC
0078
0000
0000

© 2009 Microchip Technology Inc.

MPY

Square to Accumulator

Implemented in:

Syntax:

PIC24F

{label:} MPY

PIC24H

dsPIC30F

dsPIC33F

X

X

Wm * Wm, Acc {,[Wx], Wxd}

{,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands:

Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]

Operation:

(Wm) * (Wm) → Acc(A or B)
([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

1111

Description:

00mm

A0xx

yyii

iijj

jj01

Square the contents of a working register, optionally prefetch operands in
preparation for another MAC type instruction and optionally store the
unspecified accumulator results. The 32-bit result of the signed multiply is
sign-extended to 40 bits and stored in the specified accumulator.
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations
which support indirect and register offset addressing, as described in
Section 4.14.1 “MAC Prefetches”.
The ‘m’ bits select the operand register Wm for the square.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
Note:

Words:

1

Cycles:

1

Example 1:

MPY

The IF bit, CORCON<0>, determines if the multiply is
fractional or an integer.

W6*W6, A, [W9]+=2, W6

; Square W6 and store to ACCA
; Fetch [W9] to W6, Post-increment W9 by 2
; CORCON = 0x0000 (fractional multiply, no saturation)

© 2009 Microchip Technology Inc.

W6
W9
ACCA
Data 0900
CORCON
SR

After
Instruction
B865
0902
00 4FB2 0000
B865
0000
0000

5
Instruction
Descriptions

W6
W9
ACCA
Data 0900
CORCON
SR

Before
Instruction
6500
0900
00 7C80 0908
B865
0000
0000

DS70157D-page 249

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

MPY W4*W4, B, [W9+W12], W4, [W10]+=2, W5
; Square W4 and store to ACCB
; Fetch [W9+W12] to W4
; Fetch [W10] to W5, Post-increment W10 by 2
; CORCON = 0x0000 (fractional multiply, no saturation)

W4
W5
W9
W10
W12
ACCB
Data 1600
Data 1B00
CORCON
SR

DS70157D-page 250

Before
Instruction
E228
9000
1700
1B00
FF00
00 9834 4500
8911
F678
0000
0000

W4
W5
W9
W10
W12
ACCB
Data 1600
Data 1B00
CORCON
SR

After
Instruction
8911
F678
1700
1B02
FF00
00 06F5 4C80
8911
F678
0000
0000

© 2009 Microchip Technology Inc.

MPY.N

Multiply -Wm by Wn to Accumulator

Implemented in:

Syntax:

PIC24F

{label:} MPY.N

PIC24H

dsPIC30F

dsPIC33F

X

X

Wm * Wn, Acc {,[Wx], Wxd}

{,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands:

Wm * Wn ∈ [W4 * W5; W4 * W6; W4 * W7; W5 * W6; W5 * W7; W6 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]

Operation:

-(Wm) * (Wn) → Acc(A or B)
([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy

Status Affected:

OA, OB, OAB

Encoding:
Description:

1100

0mmm

A1xx

yyii

iijj

jj11

Multiply the contents of a working register by the negative of the contents
of another working register, optionally prefetch operands in preparation for
another MAC type instruction and optionally store the unspecified
accumulator results. The 32-bit result of the signed multiply is
sign-extended to 40 bits and stored to the specified accumulator.
The ‘m’ bits select the operand registers Wm and Wn for the multiply.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
Note:

Words:

1

Cycles:

1

The IF bit, CORCON<0>, determines if the multiply is fractional
or an integer.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 251

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

MPY.N
;
;
;
;

W4
W5
W8
W10
ACCA
Data 0B00
Data 2000
CORCON
SR
Example 2:

MPY.N
;
;
;
;

Before
Instruction
3023
1290
0B00
2000
00 0000 2387
0054
660A
0001
0000

W4
W5
W8
W10
ACCA
Data 0B00
Data 2000
CORCON
SR

After
Instruction
0054
660A
0B02
2002
FF FC82 7650
0054
660A
0001
0000

W4*W5, A, [W8]+=2, W4, [W10]+=2, W5

Multiply W4*W5, negate the result and store to ACCA
Fetch [W8] to W4, Post-increment W8 by 2
Fetch [W10] to W5, Post-increment W10 by 2
CORCON = 0x0000 (fractional multiply, no saturation)

W4
W5
W8
W10
ACCA
Data 0B00
Data 2000
CORCON
SR

DS70157D-page 252

W4*W5, A, [W8]+=2, W4, [W10]+=2, W5

Multiply W4*W5, negate the result and store to ACCA
Fetch [W8] to W4, Post-increment W8 by 2
Fetch [W10] to W5, Post-increment W10 by 2
CORCON = 0x0001 (integer multiply, no saturation)

Before
Instruction
3023
1290
0B00
2000
00 0000 2387
0054
660A
0000
0000

W4
W5
W8
W10
ACCA
Data 0B00
Data 2000
CORCON
SR

After
Instruction
0054
660A
0B02
2002
FF F904 ECA0
0054
660A
0000
0000

© 2009 Microchip Technology Inc.

MSC

Multiply and Subtract from Accumulator

Implemented in:

Syntax:

PIC24F

{label:} MSC

PIC24H

dsPIC30F

dsPIC33F

X

X

Wm * Wn, Acc {,[Wx], Wxd}

{,[Wy], Wyd}

{,AWB}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}
{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}
{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}
Operands:

Wm * Wn ∈ [W4 * W5, W4 * W6, W4 * W7, W5 * W6, W5 * W7, W6 * W7]
Acc ∈ [A,B]
Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]
Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]
AWB ∈ [W13, [W13] + = 2]

Operation:

(Acc(A or B)) − (Wm) * (Wn) → Acc(A or B)
([Wx]) → Wxd; (Wx) + kx → Wx
([Wy]) → Wyd; (Wy) + ky → Wy
(Acc(B or A)) rounded → AWB

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:
Description:

1100

0mmm

A1xx

yyii

iijj

jjaa

Multiply the contents of two working registers, optionally prefetch
operands in preparation for another MAC type instruction and optionally
store the unspecified accumulator results. The 32-bit result of the signed
multiply is sign-extended to 40 bits and subtracted from the specified
accumulator.
Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations
which support indirect and register offset addressing as described in
Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional
store of the “other” accumulator as described in
Section 4.14.4 “MAC Write Back”.
The ‘m’ bits select the operand registers Wm and Wn for the multiply.
The ‘A’ bit selects the accumulator for the result.
The ‘x’ bits select the prefetch Wxd destination.
The ‘y’ bits select the prefetch Wyd destination.
The ‘i’ bits select the Wx prefetch operation.
The ‘j’ bits select the Wy prefetch operation.
The ‘a’ bits select the accumulator Write Back destination.
Note:

Words:

1

Cycles:

1

The IF bit, CORCON<0>, determines if the multiply is
fractional or an integer.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 253

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

MSC
;
;
;
;

W6
W7
W8
W10
ACCA
Data 0C00
Data 1C00
CORCON
SR
Example 2:

MSC
;
;
;
;

Before
Instruction
9051
7230
0C00
1C00
00 0567 8000
D309
100B
0001
0000

W6
W7
W8
W10
ACCA
Data 0C00
Data 1C00
CORCON
SR

After
Instruction
D309
100B
0BFC
1BFC
00 3738 5ED0
D309
100B
0001
0000

W4*W5, B, [W11+W12], W5, W13

Multiply W4*W5 and subtract the result from ACCB
Fetch [W11+W12] to W5
Write Back ACCA to W13
CORCON = 0x0000 (fractional multiply, no saturation)

W4
W5
W11
W12
W13
ACCA
ACCB
Data 2000
CORCON
SR

DS70157D-page 254

W6*W7, A, [W8]-=4, W6, [W10]-=4, W7

Multiply W6*W7 and subtract the result from ACCA
Fetch [W8] to W6, Post-decrement W8 by 4
Fetch [W10] to W7, Post-decrement W10 by 4
CORCON = 0x0001 (integer multiply, no saturation)

Before
Instruction
0500
2000
1800
0800
6233
00 3738 5ED0
00 1000 0000
3579
0000
0000

W4
W5
W11
W12
W13
ACCA
ACCB
Data 2000
CORCON
SR

After
Instruction
0500
3579
1800
0800
3738
00 3738 5ED0
00 0EC0 0000
3579
0000
0000

© 2009 Microchip Technology Inc.

MUL

Integer Unsigned Multiply f and WREG

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
(WREG)<7:0> * (f)<7:0> → W2
For word operation:
(WREG) * (f) → W2:W3

Status Affected:

None

Encoding:

1011

Description:

MUL{.B}

1100

f

0B0f

ffff

ffff

ffff

Multiply the default working register WREG with the specified file
register and place the result in the W2:W3 register pair. Both operands
and the result are interpreted as unsigned integers. If this instruction is
executed in Byte mode, the 16-bit result is stored in W2. In Word mode,
the most significant word of the 32-bit result is stored in W3, and the
least significant word of the 32-bit result is stored in W2.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: The IF bit, CORCON<0>, has no effect on this operation.
4: This is the only instruction, which provides for an 8-bit
multiply.

Words:

1

Cycles:

1

Example 1:

MUL.B

0x800

Before
Instruction
WREG (W0)
9823
W2
FFFF
W3
FFFF
Data 0800
2690
SR
0000
Example 2:

MUL

TMR1

© 2009 Microchip Technology Inc.

After
Instruction
WREG (W0)
9823
W2
13B0
W3
FFFF
Data 0800
2690
SR
0000
; Multiply (TMR1)*WREG (Word mode)

5

After
Instruction
WREG (W0)
F001
W2
C287
W3
2F5E
TMR1
3287
SR
0000

Instruction
Descriptions

Before
Instruction
WREG (W0)
F001
W2
0000
W3
0000
TMR1
3287
SR
0000

; Multiply (0x800)*WREG (Byte mode)

DS70157D-page 255

16-bit MCU and DSC Programmer’s Reference Manual

MUL.SS

Integer 16x16-bit Signed Multiply

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

MUL.SS

Wb,

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wnd ∈ [W0, W2, W4 ... W12]

Operation:

signed (Wb) * signed (Ws) → Wnd:Wnd + 1

Status Affected:

None

Encoding:
Description:

1011

1001

1www

wddd

dppp

ssss

Multiply the contents of Wb with the contents of Ws, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in
Wnd + 1. Both source operands and the result Wnd are interpreted as
two’s complement signed integers. Register direct addressing must be
used for Wb and Wnd. Register direct or register indirect addressing
may be used for Ws.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-2 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit, CORCON<0>, has no effect on this operation.

Words:

1

Cycles:

1

Example 1:

MUL.SS

W0, W1, W12

Before
Instruction
W0
9823
W1
67DC
W12
FFFF
W13
FFFF
SR
0000

DS70157D-page 256

; Multiply W0*W1
; Store the result to W12:W13

After
Instruction
W0
9823
W1
67DC
W12
D314
W13 D5DC
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

MUL.SS

W2, [--W4], W0

Before
Instruction
W0
FFFF
W1
FFFF
W2
0045
W4
27FE
Data 27FC
0098
SR
0000

; Pre-decrement W4
; Multiply W2*[W4]
; Store the result to W0:W1

After
Instruction
W0
28F8
W1
0000
W2
0045
W4
27FC
Data 27FC
0098
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 257

16-bit MCU and DSC Programmer’s Reference Manual

MUL.SU

Integer 16x16-bit Signed-Unsigned Short Literal Multiply

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wnd ∈ [W0, W2, W4 ... W12]

Operation:

signed (Wb) * unsigned lit5 → Wnd:Wnd + 1

Status Affected:

None

Encoding:
Description:

1011

MUL.SU

1001

Wb,

0www

#lit5,

Wnd

wddd

d11k

kkkk

Multiply the contents of Wb with the 5-bit literal, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in Wnd + 1.
The Wb operand and the result Wnd are interpreted as a two’s
complement signed integer. The literal is interpreted as an unsigned integer. Register direct addressing must be used for Wb and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘k’ bits define a 5-bit unsigned integer literal.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-3 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit, CORCON<0>, has no effect on this operation.

Words:

1

Cycles:

1

Example 1:

MUL.SU

W0, #0x1F, W2

Before
Instruction
W0
C000
W2
1234
W3
C9BA
SR
0000

DS70157D-page 258

; Multiply W0 by literal 0x1F
; Store the result to W2:W3

After
Instruction
W0
C000
W2
4000
W3
FFF8
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

MUL.SU

W2, #0x10, W0

Before
Instruction
W0 ABCD
W1
89B3
W2
F240
SR
0000

; Multiply W2 by literal 0x10
; Store the result to W0:W1

After
Instruction
W0
2400
W1
000F
W2
F240
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 259

16-bit MCU and DSC Programmer’s Reference Manual

MUL.SU

Integer 16x16-bit Signed-Unsigned Multiply

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

MUL.SU

Wb,

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wnd ∈ [W0, W2, W4 ... W12]

Operation:

signed (Wb) * unsigned (Ws) → Wnd:Wnd + 1

Status Affected:

None

Encoding:
Description:

1011

1001

0www

wddd

dppp

ssss

Multiply the contents of Wb with the contents of Ws, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in Wnd + 1.
The Wb operand and the result Wnd are interpreted as a two’s
complement signed integer. The Ws operand is interpreted as an
unsigned integer. Register direct addressing must be used for Wb and
Wnd. Register direct or register indirect addressing may be used for Ws.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-3 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit, CORCON<0>, has no effect on this operation.

Words:

1

Cycles:

1

Example 1:

MUL.SU

W8, [W9], W0

Before
Instruction
W0
68DC
W1
AA40
W8
F000
W9
178C
Data 178C
F000
SR
0000

DS70157D-page 260

; Multiply W8*[W9]
; Store the result to W0:W1

After
Instruction
W0
0000
W1
F100
W8
F000
W9
178C
Data 178C
F000
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

MUL.SU

W2, [++W3], W4

Before
Instruction
W2
0040
W3
0280
W4
1819
W5
2021
Data 0282
0068
SR
0000

; Pre-Increment W3
; Multiply W2*[W3]
; Store the result to W4:W5

After
Instruction
W2
0040
W3
0282
W4
1A00
W5
0000
Data 0282
0068
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 261

16-bit MCU and DSC Programmer’s Reference Manual

MUL.US

Integer 16x16-bit Unsigned-Signed Multiply

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

MUL.US

Wb,

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wnd ∈ [W0, W2, W4 ... W12]

Operation:

unsigned (Wb) * signed (Ws) → Wnd:Wnd + 1

Status Affected:

None

Encoding:
Description:

1011

1000

1www

wddd

dppp

ssss

Multiply the contents of Wb with the contents of Ws, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in Wnd + 1.
The Wb operand is interpreted as an unsigned integer. The Ws operand
and the result Wnd are interpreted as a two’s complement signed
integer. Register direct addressing must be used for Wb and Wnd.
Register direct or register indirect addressing may be used for Ws.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-3 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit, CORCON<0>, has no effect on this operation.

Words:

1

Cycles:

1

Example 1:

MUL.US

W0, [W1], W2

Before
Instruction
W0
C000
W1
2300
W2
00DA
W3
CC25
Data 2300
F000
SR
0000

DS70157D-page 262

; Multiply W0*[W1] (unsigned-signed)
; Store the result to W2:W3

After
Instruction
W0
C000
W1
2300
W2
0000
W3
F400
Data 2300
F000
SR
0000

© 2009 Microchip Technology Inc.

Example 2:

MUL.US

W6, [W5++], W10 ; Mult. W6*[W5] (unsigned-signed)
; Store the result to W10:W11
; Post-Increment W5

Before
Instruction
W5
0C00
W6
FFFF
W10
0908
W11
6EEB
Data 0C00
7FFF
SR
0000

After
Instruction
W5
0C02
W6
FFFF
W10
8001
W11
7FFE
Data 0C00
7FFF
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 263

16-bit MCU and DSC Programmer’s Reference Manual

MUL.UU

Integer 16x16-bit Unsigned Short Literal Multiply

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wnd ∈ [W0, W2, W4 ... W12]

Operation:

unsigned (Wb) * unsigned lit5 → Wnd:Wnd + 1

Status Affected:

None

Encoding:
Description:

1011

MUL.UU

1000

Wb,

0www

#lit5,

Wnd

wddd

d11k

kkkk

Multiply the contents of Wb with the 5-bit literal, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in Wnd + 1.
Both operands and the result are interpreted as unsigned integers.
Register direct addressing must be used for Wb and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘k’ bits define a 5-bit unsigned integer literal.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-3 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit, CORCON<0>, has no effect on this operation.

Words:

1

Cycles:

1

Example 1:

MUL.UU

W0, #0xF, W12

Before
Instruction
W0
2323
W12
4512
W13
7821
SR
0000
Example 2:

MUL.UU

W7, #0x1F, W0

Before
Instruction
W0
780B
W1
3805
W7
F240
SR
0000

DS70157D-page 264

; Multiply W0 by literal 0xF
; Store the result to W12:W13

After
Instruction
W0
2323
W12
0F0D
W13
0002
SR
0000
; Multiply W7 by literal 0x1F
; Store the result to W0:W1

After
Instruction
W0
55C0
W1
001D
W7
F240
SR
0000

© 2009 Microchip Technology Inc.

MUL.UU

Integer 16x16-bit Unsigned Multiply

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

MUL.UU

Wb,

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wnd ∈ [W0, W2, W4 ... W12]

Operation:

unsigned (Wb) * unsigned (Ws) → Wnd:Wnd + 1

Status Affected:

None

Encoding:
Description:

1011

1000

0www

wddd

dppp

ssss

Multiply the contents of Wb with the contents of Ws, and store the 32-bit
result in two successive working registers. The least significant word of
the result is stored in Wnd (which must be an even numbered working
register), and the most significant word of the result is stored in
Wnd + 1. Both source operands and the result are interpreted as
unsigned integers. Register direct addressing must be used for Wb and
Wnd. Register direct or indirect addressing may be used for Ws.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the address of the lower destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: Since the product of the multiplication is 32 bits, Wnd must be
an even working register. See Figure 4-3 for information on
how double words are aligned in memory.
3: Wnd may not be W14, since W15<0> is fixed to zero.
4: The IF bit, CORCON<0>, has no effect on this operation.

Words:

1

Cycles:

1

Example 1:

MUL.UU

W4, W0, W2

© 2009 Microchip Technology Inc.

After
Instruction
W0
FFFF
W2
0001
W3
FFFE
W4
FFFF
SR
0000

5
Instruction
Descriptions

Before
Instruction
W0
FFFF
W2
2300
W3
00DA
W4
FFFF
SR
0000

; Multiply W4*W0 (unsigned-unsigned)
; Store the result to W2:W3

DS70157D-page 265

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

MUL.UU W0, [W1++], W4

Before
Instruction
W0
1024
W1
2300
W4
9654
W5 BDBC
Data 2300
D625
SR
0000

DS70157D-page 266

; Mult. W0*[W1] (unsigned-unsigned)
; Store the result to W4:W5
; Post-Increment W1

After
Instruction
W0
1024
W1
2302
W4
6D34
W5
0D80
Data 2300
D625
SR
0000

© 2009 Microchip Technology Inc.

NEG

Negate f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) + 1 → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

NEG{.B}

1110

f

{,WREG}

0BDf

ffff

ffff

ffff

Compute the two’s complement of the contents of the file register and
place the result in the destination register. The optional WREG operand
determines the destination register. If WREG is specified, the result is
stored in WREG. If WREG is not specified, the result is stored in the file
register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

NEG.B

0x880, WREG

Before
Instruction
WREG (W0)
9080
Data 0880
2355
SR
0000
Example 2:

NEG

0x1200

Before
Instruction
Data 1200
8923
SR
0000

; Negate (0x880) (Byte mode)
; Store result to WREG

After
Instruction
WREG (W0) 90AB
Data 0880
2355
SR
0008 (N = 1)
; Negate (0x1200) (Word mode)

After
Instruction
Data 1200 76DD
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 267

16-bit MCU and DSC Programmer’s Reference Manual

NEG

Negate Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

NEG{.B}

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) + 1 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

1110

Description:

1010

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

0Bqq

qddd

dppp

ssss

Compute the two’s complement of the contents of the source register Ws
and place the result in the destination register Wd. Either register direct
or indirect addressing may be used for both Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

NEG.B

W3, [W4++]

Before
Instruction
W3
7839
W4
1005
Data 1004
2355
SR
0000
Example 2:

NEG

; Negate W3 and store to [W4] (Byte mode)
; Post-increment W4

After
Instruction
W3
7839
W4
1006
Data 1004 C755
SR
0008 (N = 1)

[W2++], [--W4]

Before
Instruction
W2
0900
W4
1002
Data 0900
870F
Data 1000
5105
SR
0000

DS70157D-page 268

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

; Pre-decrement W4 (Word mode)
; Negate [W2] and store to [W4]
; Post-increment W2

After
Instruction
W2
0902
W4
1000
Data 0900
870F
Data 1000
78F1
SR
0000

© 2009 Microchip Technology Inc.

NEG

Negate Accumulator

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

A001

0000

Syntax:

{label:}

Operands:

Acc ∈ [A,B]

Operation:

If (Acc = A):
-ACCA → ACCA
Else:
-ACCB → ACCB

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

NEG

dsPIC30F

1100

Description:

1011

Acc

0000

0000

Compute the two’s complement of the contents of the specified
accumulator. Regardless of the Saturation mode, this instruction
operates on all 40 bits of the accumulator.
The ‘A’ bit specifies the selected accumulator.

Words:

1

Cycles:

1

Example 1:

NEG

ACCA
CORCON
SR
Example 2:

NEG

ACCB
CORCON
SR

A

; Negate ACCA
; Store result to ACCA
; CORCON = 0x0000 (no saturation)

Before
Instruction
00 3290 59C8
0000
0000
B

ACCA
CORCON
SR

After
Instruction
FF CD6F A638
0000
0000

; Negate ACCB
; Store result to ACCB
; CORCON = 0x00C0 (normal saturation)

Before
Instruction
FF F230 10DC
00C0
0000

ACCB
CORCON
SR

After
Instruction
00 0DCF EF24
00C0
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 269

16-bit MCU and DSC Programmer’s Reference Manual

NOP

No Operation

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0000

xxxx

xxxx

Syntax:

{label:}

Operands:

None

Operation:

No Operation

Status Affected:

None

Encoding:

0000

Description:

NOP

xxxx

xxxx

No Operation is performed.
The ‘x’ bits can take any value.

Words:

1

Cycles:

1

Example 1:

NOP

PC
SR
Example 2:

DS70157D-page 270

Before
Instruction
00 1092
0000

NOP

PC
SR

; execute no operation

After
Instruction
PC
00 1094
SR
0000

; execute no operation

Before
Instruction
00 08AE
0000

After
Instruction
PC
00 08B0
SR
0000

© 2009 Microchip Technology Inc.

NOPR

No Operation

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

xxxx

xxxx

Syntax:

{label:}

Operands:

None

Operation:

No Operation

Status Affected:

None

Encoding:

1111

Description:

NOPR

1111

xxxx

xxxx

No Operation is performed.
The ‘x’ bits can take any value.

Words:

1

Cycles:

1

Example 1:

NOPR

PC
SR
Example 2:

Before
Instruction
00 2430
0000

NOPR

PC
SR

; execute no operation

After
Instruction
PC
00 2432
SR
0000

; execute no operation

Before
Instruction
00 1466
0000

After
Instruction
PC
00 1468
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 271

16-bit MCU and DSC Programmer’s Reference Manual

POP

Pop TOS to f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

ffff

ffff

Syntax:

{label:}

Operands:

f ∈ [0 ... 65534]

Operation:

(W15) – 2 → W15
(TOS) → f

Status Affected:

None

Encoding:

1111

Description:

POP

1001

f

ffff

fff0

The Stack Pointer (W15) is pre-decremented by 2 and the Top-of-Stack
(TOS) word is written to the specified file register, which may reside
anywhere in the lower 32K words of data memory.
The ‘f’ bits select the address of the file register.
Note 1: This instruction operates in Word mode only.
2: The file register address must be word-aligned.

Words:

1

Cycles:

1

Example 1:

POP

0x1230

Before
Instruction
W15
1006
Data 1004 A401
Data 1230
2355
SR
0000
Example 2:

POP

0x880

Before
Instruction
W15
2000
Data 0880 E3E1
Data 1FFE A090
SR
0000

DS70157D-page 272

; Pop TOS to 0x1230

After
Instruction
W15
1004
Data 1004 A401
Data 1230 A401
SR
0000
; Pop TOS to 0x880

After
Instruction
W15 1FFE
Data 0880 A090
Data 1FFE A090
SR
0000

© 2009 Microchip Technology Inc.

POP

Pop TOS to Wd

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

POP

Wd
[Wd]
[Wd++]
[Wd--]
[--Wd]
[++Wd]
[Wd+Wb]

Operands:

Wd ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]

Operation:

(W15) – 2 → W15
(TOS) → Wd

Status Affected:

None

Encoding:

0111

Description:

1www

w0hh

hddd

d100

1111

The Stack Pointer (W15) is pre-decremented by 2 and the Top-of-Stack
(TOS) word is written to Wd. Either register direct or indirect addressing
may be used for Wd.
The ‘w’ bits define the offset register Wb.
The ‘h’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
Note 1: This instruction operates in Word mode only.
2: This instruction is a specific version of the “MOV Ws, Wd”
instruction (MOV [--W15], Wd). It reverse assembles as
MOV.

Words:

1

Cycles:

1

Example 1:

POP

W4

Before
Instruction
W4 EDA8
W15
1008
Data 1006 C45A
SR
0000
Example 2:

After
Instruction
W4 C45A
W15
1006
Data 1006 C45A
SR
0000

[++W10]

; Pre-increment W10
; Pop TOS to [W10]

Before
Instruction
W10 0E02
W15
1766
Data 0E04 E3E1
Data 1764 C7B5
SR
0000

After
Instruction
W10 0E04
W15
1764
Data 0E04 C7B5
Data 1764 C7B5
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

POP

; Pop TOS to W4

DS70157D-page 273

16-bit MCU and DSC Programmer’s Reference Manual

POP.D

Double Pop TOS to Wnd:Wnd+1

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wnd ∈ [W0, W2, W4, ... W14]

Operation:

(W15) – 2 → W15
(TOS) → Wnd + 1
(W15) – 2 → W15
(TOS) → Wnd

Status Affected:

None

Encoding:

1011

Description:

POP.D

1110

Wnd

0000

0ddd

0100

1111

A double word is POPped from the Top-of-Stack (TOS) and stored to
Wnd:Wnd + 1. The most significant word is stored to Wnd + 1, and the
least significant word is stored to Wnd. Since a double word is POPped,
the Stack Pointer (W15) gets decremented by 4.
The ‘d’ bits select the address of the destination register pair.
Note 1: This instruction operates on double words. See Figure 4-3 for
information on how double words are aligned in memory.
2: Wnd must be an even working register.
3: This instruction is a specific version of the “MOV.D Ws, Wnd”
instruction (MOV.D [--W15], Wnd). It reverse assembles as
MOV.D.

Words:

1

Cycles:

2

Example 1:

POP.D

W6

Before
Instruction
W6 07BB
W7 89AE
W15
0850
Data 084C
3210
Data 084E
7654
SR
0000
Example 2:

POP.D

W0

Before
Instruction
W0 673E
W1 DD23
W15 0BBC
Data 0BB8 791C
Data 0BBA D400
SR
0000

DS70157D-page 274

; Double pop TOS to W6

After
Instruction
W6
3210
W7
7654
W15 084C
Data 084C
3210
Data 084E
7654
SR
0000
; Double pop TOS to W0

After
Instruction
W0 791C
W1 D400
W15 0BB8
Data 0BB8 791C
Data 0BBA D400
SR
0000

© 2009 Microchip Technology Inc.

POP.S

Pop Shadow Registers

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

1000

0000

Syntax:

{label:}

Operands:

None

Operation:

POP shadow registers

Status Affected:

DC, N, OV, Z, C

Encoding:

1111

Description:

POP.S

1110

0000

0000

The values in the shadow registers are copied into their respective
primary registers. The following registers are affected: W0-W3, and the
C, Z, OV, N and DC STATUS register flags.
Note 1: The shadow registers are not directly accessible. They may
only be accessed with PUSH.S and POP.S.
2: The shadow registers are only one-level deep.

Words:

1

Cycles:

1

Example 1:

POP.S

; Pop the shadow registers
; (See PUSH.S Example 1 for contents of shadows)

Before
Instruction
W0 07BB
W1 03FD
W2
9610
W3
7249
SR 00E0 (IPL = 7)
Note:

After
Instruction
W0
0000
W1
1000
W2
2000
W3
3000
SR 00E1 (IPL = 7, C = 1)

After instruction execution, contents of shadow registers are NOT modified.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 275

16-bit MCU and DSC Programmer’s Reference Manual

PUSH

Push f to TOS

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

ffff

ffff

Syntax:

{label:}

Operands:

f ∈ [0 ... 65534]

Operation:

(f) → (TOS)
(W15) + 2 → W15

Status Affected:

None

Encoding:

1111

Description:

PUSH

1000

f

ffff

fff0

The contents of the specified file register are written to the Top-of-Stack
(TOS) location and then the Stack Pointer (W15) is incremented by 2.
The file register may reside anywhere in the lower 32K words of data
memory.
The ‘f’ bits select the address of the file register.
Note 1: This instruction operates in Word mode only.
2: The file register address must be word-aligned.

Words:

1

Cycles:

1

Example 1:

PUSH

0x2004

Before
Instruction
W15 0B00
Data 0B00 791C
Data 2004 D400
SR
0000
Example 2:

PUSH

0xC0E

Before
Instruction
W15
0920
Data 0920
0000
Data 0C0E 67AA
SR
0000

DS70157D-page 276

; Push (0x2004) to TOS

After
Instruction
W15 0B02
Data 0B00 D400
Data 2004 D400
SR
0000
; Push (0xC0E) to TOS

After
Instruction
W15
0922
Data 0920 67AA
Data 2004 67AA
SR
0000

© 2009 Microchip Technology Inc.

PUSH

Push Ws to TOS

Implemented in:

Syntax:

PIC24F

PIC24H

X

X

{label:}

PUSH

dsPIC30F dsPIC33F
X

X

Ws
[Ws]
[Ws++]
[Ws--]
[--Ws]
[++Ws]
[Ws+Wb]

Operands:

Ws ∈ [W0 ... W15]
Wb ∈ [W0 ... W15]

Operation:

(Ws) → (TOS)
(W15) + 2 → W15

Status Affected:

None

Encoding:

0111

Description:

1www

w001

1111

1ggg

ssss

The contents of Ws are written to the Top-of-Stack (TOS) location and
then the Stack Pointer (W15) is incremented by 2.
The ‘w’ bits define the offset register Wb.
The ‘g’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: This instruction is a specific version of the “MOV Ws, Wd”
instruction (MOV Ws, [W15++]). It reverse assembles as
MOV.

Words:

1

Cycles:

1

Example 1:

PUSH

W2

Before
Instruction
W2
6889
W15
1566
Data 1566
0000
SR
0000
Example 2:

PUSH

[W5+W10]

© 2009 Microchip Technology Inc.

After
Instruction
W2
6889
W15
1568
Data 1566
6889
SR
0000
; Push [W5+W10] to TOS

5

After
Instruction
W5
1200
W10
0044
W15
0808
Data 0806 B20A
Data 1244 B20A
SR
0000

Instruction
Descriptions

Before
Instruction
W5
1200
W10
0044
W15
0806
Data 0806
216F
Data 1244 B20A
SR
0000

; Push W2 to TOS

DS70157D-page 277

16-bit MCU and DSC Programmer’s Reference Manual

PUSH.D

Double Push Wns:Wns+1 to TOS

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

1001

1111

Syntax:

{label:}

Operands:

Wns ∈ [W0, W2, W4 ... W14]

Operation:

(Wns) → (TOS)
(W15) + 2 → W15
(Wns + 1) → (TOS)
(W15) + 2 → W15

Status Affected:

None

Encoding:
Description:

1011

PUSH.D

1110

Wns

1000

sss0

A double word (Wns:Wns + 1) is PUSHed to the Top-of-Stack (TOS).
The least significant word (Wns) is PUSHed to the TOS first, and the
most significant word (Wns + 1) is PUSHed to the TOS last. Since a
double word is PUSHed, the Stack Pointer (W15) gets incremented by 4.
The ‘s’ bits select the address of the source register pair.
Note 1: This instruction operates on double words. See Figure 4-3 for
information on how double words are aligned in memory.
2: Wns must be an even working register.
3: This instruction is a specific version of the “MOV.D Wns, Wd”
instruction (MOV.D Wns, [W15++]). It reverse assembles as
MOV.D.

Words:

1

Cycles:

2

Example 1:

PUSH.D

W6

Before
Instruction
W6 C451
W7
3380
W15
1240
Data 1240 B004
Data 1242
0891
SR
0000
Example 2:

PUSH.D

W10

Before
Instruction
W10 80D3
W11
4550
W15 0C08
Data 0C08 79B5
Data 0C0A 008E
SR
0000

DS70157D-page 278

; Push W6:W7 to TOS

After
Instruction
W6 C451
W7
3380
W15
1244
Data 1240 C451
Data 1242
3380
SR
0000
; Push W10:W11 to TOS

After
Instruction
W10 80D3
W11
4550
W15 0C0C
Data 0C08 80D3
Data 0C0A
4550
SR
0000

© 2009 Microchip Technology Inc.

PUSH.S

Push Shadow Registers

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

1010

0000

Syntax:

{label:}

Operands:

None

Operation:

PUSH shadow registers

Status Affected:

None

Encoding:

PUSH.S

1111

Description:

1110

0000

0000

The contents of the primary registers are copied into their respective
shadow registers. The following registers are shadowed: W0-W3, and
the C, Z, OV, N and DC STATUS register flags.
Note 1: The shadow registers are not directly accessible. They may
only be accessed with PUSH.S and POP.S.
2: The shadow registers are only one-level deep.

Words:

1

Cycles:

1

Example 1:

PUSH.S

; Push primary registers into shadow registers

Before
Instruction
W0
0000
W1
1000
W2
2000
W3
3000
SR
0001 (C = 1)
Note:

After
Instruction
W0
0000
W1
1000
W2
2000
W3
3000
SR
0001 (C = 1)

After an instruction execution, contents of the shadow registers are updated.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 279

16-bit MCU and DSC Programmer’s Reference Manual

PWRSAV

Enter Power-Saving Mode

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0100

0000

Syntax:

{label:}

Operands:

lit1 ∈ [0,1]

Operation:

0 → WDT count register
0 → WDT prescaler A count
0 → WDT prescaler B count
0 → WDTO (RCON<4>)
0 → SLEEP (RCON<3>)
0 → IDLE (RCON<2>)
If (lit1 = 0):
Enter Sleep mode
Else:
Enter Idle mode

Status Affected:

None

Encoding:
Description:

1111

PWRSAV

1110

#lit1

0000

000k

Place the processor into the specified Power Saving mode. If lit1 = ‘0’,
Sleep mode is entered. In Sleep mode, the clock to the CPU and
peripherals are shutdown. If an on-chip oscillator is being used, it is also
shutdown. If lit1 = ‘1’, Idle mode is entered. In Idle mode, the clock to the
CPU shuts down, but the clock source remains active and the
peripherals continue to operate.
This instruction resets the Watchdog Timer Count register and the
Prescaler Count registers. In addition, the WDTO, Sleep and Idle flags of
the Reset System and Control (RCON) register are reset.
Note 1: The processor will exit from Idle or Sleep through an interrupt,
processor Reset or Watchdog Time-out. See the specific
device data sheet for details.
2: If awakened from Idle mode, Idle (RCON<2>) is set to ‘1’ and
the clock source is applied to the CPU.
3: If awakened from Sleep mode, Sleep (RCON<3>) is set to ‘1’
and the clock source is started.
4: If awakened from a Watchdog Time-out, WDTO (RCON<4>)
is set to ‘1’.

Words:

1

Cycles:

1

Example 1:

PWRSAV

#0

; Enter SLEEP mode

Before
Instruction
SR
0040 (IPL = 2)
Example 2:

PWRSAV

#1

; Enter IDLE mode

Before
Instruction
SR
0020 (IPL = 1)

DS70157D-page 280

After
Instruction
SR
0040 (IPL = 2)

After
Instruction
SR
0020 (IPL = 1)

© 2009 Microchip Technology Inc.

RCALL

Relative Call

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

RCALL

Operands:

Expr may be an absolute address, label or expression.
Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... 32767].

Operation:

(PC) + 2 → PC
(PC<15:0>) → (TOS)
(W15) + 2 → W15
(PC<22:16>) → (TOS)
(W15) + 2 → W15
(PC) + (2 * Slit16) → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

0111

Expr

nnnn

nnnn

nnnn

nnnn

Relative subroutine call with a range of 32K program words forward or back
from the current PC. Before the call is made, the return address (PC + 2) is
PUSHed onto the stack. After the return address is stacked, the
sign-extended 17-bit value (2 * Slit16) is added to the contents of the PC
and the result is stored in the PC.
The ‘n’ bits are a signed literal that specifies the size of the relative call (in
program words) from (PC + 2).
Note:

Words:

1

Cycles:

2

Example 1:

When possible, this instruction should be used instead of CALL,
since it only consumes one word of program memory.

012004
012006
.
.
012458 _Task1:
01245A

PC
W15
Data 0810
Data 0812
SR

Before
Instruction
01 2004
0810
FFFF
FFFF
0000

RCALL
ADD
...
...
SUB
...

_Task1
W0, W1, W2

; Call _Task1

W0, W2, W3

; _Task1 subroutine

PC
W15
Data 0810
Data 0812
SR

After
Instruction
01 2458
0814
2006
0001
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 281

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

00620E
006210
.
.
007000 _Init:
007002

PC
W15
Data 0C50
Data 0C52
SR

DS70157D-page 282

Before
Instruction
00 620E
0C50
FFFF
FFFF
0000

RCALL
MOV
...
...
CLR
...

_Init
W0, [W4++]

; Call _Init

W2

; _Init subroutine

PC
W15
Data 0C50
Data 0C52
SR

After
Instruction
00 7000
0C54
6210
0000
0000

© 2009 Microchip Technology Inc.

RCALL

Computed Relative Call

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0010

0000

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]

Operation:

(PC) + 2 → PC
(PC<15:0>) → (TOS)
(W15) + 2 → W15
(PC<22:16>) → (TOS)
(W15) + 2 → W15
(PC) + (2 * (Wn)) → PC
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

RCALL

0001

Wn

0000

ssss

Computed, relative subroutine call specified by the working register Wn. The
range of the call is 32K program words forward or back from the current PC.
Before the call is made, the return address (PC + 2) is PUSHed onto the
stack. After the return address is stacked, the sign-extended 17-bit value (2 *
(Wn)) is added to the contents of the PC and the result is stored in the PC.
Register direct addressing must be used for Wn.
The ‘s’ bits select the source register.

Words:

1

Cycles:

2

Example 1:

00FF8C
00FF8E
.
.
010008
01000A
01000C

PC
W6
W15
Data 1004
Data 1006
SR

EX1:

Before
Instruction
01 000A
FFC0
1004
98FF
2310
0000

INC
...
...
...

W2, W3

; Destination of RCALL

RCALL
MOVE

W6
W4, [W10]

; RCALL with W6

PC
W6
W15
Data 1004
Data 1006
SR

After
Instruction
00 FF8C
FFC0
1008
000C
0001
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 283

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

000302
000304
.
.
000450
000452

PC
W2
W15
Data 1004
Data 1006
SR

DS70157D-page 284

EX2:

Before
Instruction
00 0302
00A6
1004
32BB
901A
0000

RCALL
FF1L
...
...
CLR
...

W2
W0, W1

; RCALL with W2

W2

; Destination of RCALL

PC
W2
W15
Data 1004
Data 1006
SR

After
Instruction
00 0450
00A6
1008
0304
0000
0000

© 2009 Microchip Technology Inc.

REPEAT

Repeat Next Instruction ‘lit14+1’ Times

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit14 ∈ [0 ... 16383]

Operation:

(lit14) → RCOUNT
(PC) + 2 → PC
Enable Code Looping

Status Affected:

RA

Encoding:

0000

Description:

REPEAT

1001

#lit14

00kk

kkkk

kkkk

kkkk

Repeat the instruction immediately following the REPEAT instruction
(lit14 + 1) times. The repeated instruction (or target instruction) is held in
the instruction register for all iterations and is only fetched once.
When this instruction executes, the RCOUNT register is loaded with the
repeat count value specified in the instruction. RCOUNT is decremented
with each execution of the target instruction. When RCOUNT equals
zero, the target instruction is executed one more time, and then normal
instruction execution continues with the instruction following the target
instruction.
The ‘k’ bits are an unsigned literal that specifies the loop count.
Special Features, Restrictions:
1. When the repeat literal is ‘0’, REPEAT has the effect of a NOP and
the RA bit is not set.
2. The target REPEAT instruction can NOT be:
• an instruction that changes program flow
• a DO, DISI, LNK, MOV.D, PWRSAV, REPEAT or UNLK instruction
• a 2-word instruction
Unexpected results may occur if these target instructions are used.
Note:

Words:

1

Cycles:

1

Example 1:

000452
000454

PC
RCOUNT
SR
Example 2:

REPEAT
CLR

Before
Instruction
00 089E
0000
0000

; Execute ADD 10 times
; Vector update

After
Instruction
PC
00 0454
RCOUNT
0009
SR
0010 (RA = 1)
#0x3FF
[W6++]

5

; Execute CLR 1024 times
; Clear the scratch space

After
Instruction
PC
00 08A0
RCOUNT
03FF
SR
0010 (RA = 1)

DS70157D-page 285

Instruction
Descriptions

© 2009 Microchip Technology Inc.

REPEAT #9
ADD
[W0++], W1, [W2++]

Before
Instruction
00 0452
0000
0000

00089E
0008A0

PC
RCOUNT
SR

The REPEAT and target instruction are interruptible.

16-bit MCU and DSC Programmer’s Reference Manual

REPEAT

Repeat Next Instruction Wn+1 Times

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

1000

0000

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]

Operation:

(Wn<13:0>) → RCOUNT
(PC) + 2 → PC
Enable Code Looping

Status Affected:

RA

Encoding:

0000

Description:

REPEAT

1001

Wn

0000

ssss

Repeat the instruction immediately following the REPEAT instruction
(Wn<13:0>) times. The instruction to be repeated (or target instruction)
is held in the instruction register for all iterations and is only fetched
once.
When this instruction executes, the RCOUNT register is loaded with the
lower 14 bits of Wn. RCOUNT is decremented with each execution of
the target instruction. When RCOUNT equals zero, the target instruction
is executed one more time, and then normal instruction execution
continues with the instruction following the target instruction.
The ‘s’ bits specify the Wn register that contains the repeat count.
Special Features, Restrictions:
1. When (Wn) = 0, REPEAT has the effect of a NOP and the RA bit is
not set.
2. The target REPEAT instruction can NOT be:
• an instruction that changes program flow
• a DO, DISI, LNK, MOV.D, PWRSAV, REPEAT or ULNK instruction
• a 2-word instruction
Unexpected results may occur if these target instructions are used.
Note:

Words:

1

Cycles:

1

Example 1:

000A26
000A28

PC
W4
RCOUNT
SR

DS70157D-page 286

REPEAT
COM

Before
Instruction
00 0A26
0023
0000
0000

The REPEAT and target instruction are interruptible.

W4
[W0++], [W2++]

; Execute COM (W4+1) times
; Vector complement

PC
W4
RCOUNT
SR

After
Instruction
00 0A28
0023
0023
0010 (RA = 1)

© 2009 Microchip Technology Inc.

Example 2:

00089E
0008A0

PC
W10
RCOUNT
SR

REPEAT
TBLRDL

Before
Instruction
00 089E
00FF
0000
0000

W10
; Execute TBLRD (W10+1) times
[W2++], [W3++] ; Decrement (0x840)

After
Instruction
PC
00 08A0
W10
00FF
RCOUNT
00FF
SR
0010 (RA = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 287

16-bit MCU and DSC Programmer’s Reference Manual

RESET

Reset

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

None

Operation:

Force all registers that are affected by a MCLR Reset to their Reset
condition.
1 → SWR (RCON<6>)
0 → PC

Status Affected:

OA, OB, OAB, SA, SB, SAB, DA, DC, IPL<2:0>, RA, N, OV, Z, C

Encoding:
Description:

1111

1110

0000

0000

0000

0000

This instruction provides a way to execute a software Reset. All core and
peripheral registers will take their power-on value. The PC will be set to
‘0’, the location of the RESET GOTO instruction. The SWR bit,
RCON<6>, will be set to ‘1’ to indicate that the RESET instruction was
executed.
Note:

DS70157D-page 288

RESET

Words:

1

Cycles:

1

Refer to the specific device family reference manual for the
power-on value of all registers.

© 2009 Microchip Technology Inc.

Example 1:

00202A

PC
W0
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
SPLIM
TBLPAG
PSVPAG
CORCON
RCON
SR

RESET

; Execute software RESET

Before
After
Instruction
Instruction
00 202A
PC
00 0000
8901
W0
0000
08BB
W1
0000
B87A
W2
0000
872F
W3
0000
C98A
W4
0000
AAD4
W5
0000
981E
W6
0000
1809
W7
0000
C341
W8
0000
90F4
W9
0000
F409
W10
0000
1700
W11
0000
1008
W12
0000
6556
W13
0000
231D
W14
0000
1704
W15
0800
1800
SPLIM
0000
007F
TBLPAG
0000
0001
PSVPAG
0000
00F0
CORCON
0020 (SATDW = 1)
0000
RCON
0040 (SWR = 1)
0021 (IPL, C = 1)
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 289

16-bit MCU and DSC Programmer’s Reference Manual

RETFIE

Return from Interrupt

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

None

Operation:

(W15) - 2 → W15
(TOS<15:8>) → (SR<7:0>)
(TOS<7>) → (IPL3, CORCON<3>)
(TOS<6:0>) → (PC<22:16>)
(W15) - 2 → W15
(TOS<15:0>) → (PC<15:0>)
NOP → Instruction Register

Status Affected:

IPL<3:0>, RA, N, OV, Z, C

Encoding:

0000

Description:

RETFIE

0110

0100

0000

0000

0000

Return from Interrupt Service Routine. The stack is POPped, which
loads the low byte of the STATUS register, IPL<3> (CORCON<3>) and
the Most Significant Byte of the PC. The stack is POPped again, which
loads the lower 16 bits of the PC.
Note 1: Restoring IPL<3> and the low byte of the STATUS register
restores the Interrupt Priority Level to the level before the execution was processed.
2: Before RETFIE is executed, the appropriate interrupt flag
must be cleared in software to avoid recursive interrupts.

Words:

1

Cycles:

3 (2 if exception pending)

Example 1:

000A26

PC
W15
Data 0830
Data 0832
CORCON
SR
Example 2:

DS70157D-page 290

Before
Instruction
00 0A26
0834
0230
8101
0001
0000

008050

PC
W15
Data 0922
Data 0924
CORCON
SR

RETFIE

RETFIE

Before
Instruction
00 8050
0926
7008
0300
0000
0000

; Return from ISR

PC
W15
Data 0830
Data 0832
CORCON
SR

After
Instruction
01 0230
0830
0230
8101
0001
0081 (IPL = 4, C = 1)

; Return from ISR

PC
W15
Data 0922
Data 0924
CORCON
SR

After
Instruction
00 7008
0922
7008
0300
0000
0003 (Z, C = 1)

© 2009 Microchip Technology Inc.

RETLW

Return with Literal in Wn

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

(W15) – 2 → W15
(TOS) → (PC<22:16>)
(W15) – 2 → W15
(TOS) → (PC<15:0>)
lit10 → Wn

Status Affected:

None

Encoding:

0000

Description:

RETLW{.B} #lit10,

0101

0Bkk

Wn

kkkk

kkkk

dddd

Return from subroutine with the specified, unsigned 10-bit literal stored
in Wn. The software stack is POPped twice to restore the PC and the
signed literal is stored in Wn. Since two POPs are made, the Stack
Pointer (W15) is decremented by 4.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the value of the literal.
The ‘d’ bits select the destination register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an unsigned
value [0:255]. See Section 4.6 “Using 10-bit Literal Operands”
for information on using 10-bit literal operands in Byte mode.

Words:

1

Cycles:

3 (2 if exception pending)

Example 1:

000440

PC
W0
W15
Data 1984
Data 1986
SR
Example 2:

RETLW

Before
Instruction
00 050A
0993
1200
7008
0001
0000

; Return with 0xA in W0

PC
W0
W15
Data 1984
Data 1986
SR
#0x230, W2

After
Instruction
00 7006
980A
1984
7006
0000
0000

; Return with 0x230 in W2

PC
W2
W15
Data 11FC
Data 11FE
SR

After
Instruction
01 7008
0230
11FC
7008
0001
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

Before
Instruction
00 0440
9846
1988
7006
0000
0000

00050A

PC
W2
W15
Data 11FC
Data 11FE
SR

RETLW.B #0xA, W0

DS70157D-page 291

16-bit MCU and DSC Programmer’s Reference Manual

RETURN

Return

Implemented in:

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

0000

0000

Syntax:

{label:}

Operands:

None

Operation:

(W15) – 2 → W15
(TOS) → (PC<22:16>)
(W15) – 2 → W15
(TOS) → (PC<15:0>)
NOP → Instruction Register

Status Affected:

None

Encoding:

0000

Description:

RETURN

0110

1

Cycles:

3 (2 if exception pending)
001A06

PC
W15
Data 1244
Data 1246
SR
Example 2:

0000

0000

Return from subroutine. The software stack is POPped twice to restore
the PC. Since two POPs are made, the Stack Pointer (W15) is
decremented by 4.

Words:

Example 1:

RETURN

Before
Instruction
00 1A06
1248
0004
0001
0000

005404

PC
W15
Data 0906
Data 0908
SR

DS70157D-page 292

PIC24F

RETURN

Before
Instruction
00 5404
090A
0966
0000
0000

; Return from subroutine

PC
W15
Data 1244
Data 1246
SR

After
Instruction
01 0004
1244
0004
0001
0000

; Return from subroutine

PC
W15
Data 0906
Data 0908
SR

After
Instruction
00 0966
0906
0966
0000
0000

© 2009 Microchip Technology Inc.

RLC

Rotate Left f through Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

RLC{.B}

f

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
(C) → Dest<0>
(f<6:0>) → Dest<7:1>
(f<7>) → C
For word operation:
(C) → Dest<0>
(f<14:0>) → Dest<15:1>
(f<15>) → C

{,WREG}

C

Status Affected:

N, Z, C

Encoding:

1101

Description:

0110

1BDf

ffff

ffff

ffff

Rotate the contents of the file register f one bit to the left through the
Carry flag and place the result in the destination register. The Carry flag
of the STATUS Register is shifted into the Least Significant bit of the
destination, and it is then overwritten with the Most Significant bit of Ws.
The optional WREG operand determines the destination register. If
WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for f, ‘1’ for WREG).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

RLC.B

0x1233

Before
Instruction
Data 1232 E807
SR
0000
Example 2:

RLC

0x820, WREG

; Rotate Left w/ C (0x1233) (Byte mode)

After
Instruction
Data 1232 D007
SR
0009 (N, C = 1)

5

; Rotate Left w/ C (0x820) (Word mode)
; Store result in WREG

Instruction
Descriptions

Before
After
Instruction
Instruction
WREG (W0)
5601
WREG (W0) 42DD
Data 0820 216E
Data 0820 216E
SR
0001 (C = 1)
SR
0000 (C = 0)

© 2009 Microchip Technology Inc.

DS70157D-page 293

16-bit MCU and DSC Programmer’s Reference Manual

RLC

Rotate Left Ws through Carry

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

RLC{.B}

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
(C) → Wd<0>
(Ws<6:0>) → Wd<7:1>
(Ws<7>) → C
For word operation:
(C) → Wd<0>
(Ws<14:0>) → Wd<15:1>
(Ws<15>) → C
C

Status Affected:

N, Z, C

Encoding:

1101

Description:

0010

1Bqq

qddd

dppp

ssss

Rotate the contents of the source register Ws one bit to the left through
the Carry flag and place the result in the destination register Wd. The
Carry flag of the STATUS register is shifted into the Least Significant bit
of Wd, and it is then overwritten with the Most Significant bit of Ws.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

RLC.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, W3

Before
Instruction
W0
9976
W3
5879
SR
0001 (C = 1)

DS70157D-page 294

; Rotate Left w/ C (W0) (Byte mode)
; Store the result in W3

After
Instruction
W0
9976
W3 58ED
SR
0009 (N = 1)

© 2009 Microchip Technology Inc.

Example 2:

RLC

[W2++], [W8]

; Rotate Left w/ C [W2] (Word mode)
; Post-increment W2
; Store result in [W8]

Before
After
Instruction
Instruction
W2
2008
W2 200A
W8 094E
W8 094E
Data 094E
3689
Data 094E
8082
Data 2008 C041
Data 2008 C041
SR
0001 (C = 1)
SR
0009 (N, C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 295

16-bit MCU and DSC Programmer’s Reference Manual

RLNC

Rotate Left f without Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
(f<6:0>) → Dest<7:1>
(f<7>) → Dest<0>
For word operation:
(f<14:0>) → Dest<15:1>
(f<15>) → Dest<0>

Status Affected:

N, Z

Encoding:

RLNC{.B}

1101

Description:

0110

f

{,WREG}

0BDf

ffff

ffff

ffff

Rotate the contents of the file register f one bit to the left and place the
result in the destination register. The Most Significant bit of f is stored in
the Least Significant bit of the destination, and the Carry flag is not
affected.
The optional WREG operand determines the destination register. If
WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

RLNC.B

0x1233

Before
Instruction
Data 1232 E807
SR
0000
Example 2:

RLNC

; Rotate Left (0x1233) (Byte mode)

After
Instruction
Data 1233 D107
SR
0008 (N = 1)

0x820, WREG

; Rotate Left (0x820) (Word mode)
; Store result in WREG

Before
After
Instruction
Instruction
WREG (W0)
5601
WREG (W0) 42DC
Data 0820 216E
Data 0820 216E
SR
0001 (C = 1)
SR
0000 (C = 0)

DS70157D-page 296

© 2009 Microchip Technology Inc.

RLNC

Rotate Left Ws without Carry

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

RLNC{.B}

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
(Ws<6:0>) → Wd<7:1>
(Ws<7>) → Wd<0>
For word operation:
(Ws<14:0>) → Wd<15:1>
(Ws<15>) → Wd<0>

Status Affected:

N, Z

Encoding:
Description:

1101

0010

0Bqq

qddd

dppp

ssss

Rotate the contents of the source register Ws one bit to the left and place
the result in the destination register Wd. The Most Significant bit of Ws is
stored in the Least Significant bit of Wd, and the Carry flag is not
affected. Either register direct or indirect addressing may be used for Ws
and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for byte, ‘1’ for word).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

RLNC.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, W3

© 2009 Microchip Technology Inc.

After
Instruction
W0
9976
W3 58EC
SR
0009 (N, C = 1)

Instruction
Descriptions

Before
Instruction
W0
9976
W3
5879
SR
0001 (C = 1)

5

; Rotate Left (W0) (Byte mode)
; Store the result in W3

DS70157D-page 297

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

RLNC

[W2++], [W8] ; Rotate Left [W2] (Word mode)
; Post-increment W2
; Store result in [W8]

Before
After
Instruction
Instruction
W2
2008
W2 200A
W8 094E
W8 094E
Data 094E
3689
Data 094E
8083
Data 2008 C041
Data 2008 C041
SR
0001 (C = 1)
SR
0009 (N, C = 1)

DS70157D-page 298

© 2009 Microchip Technology Inc.

RRC

Rotate Right f through Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

RRC{.B}

f

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
(C) → Dest<7>
(f<7:1>) → Dest<6:0>
(f<0>) → C
For word operation:
(C) → Dest<15>
(f<15:1>) → Dest<14:0>
(f<0>) → C

{,WREG}

C

Status Affected:

N, Z, C

Encoding:

1101

Description:

0111

1BDf

ffff

ffff

ffff

Rotate the contents of the file register f one bit to the right through the
Carry flag and place the result in the destination register. The Carry flag
of the STATUS Register is shifted into the Most Significant bit of the
destination, and it is then overwritten with the Least Significant bit of Ws.
The optional WREG operand determines the destination register. If
WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for byte, ‘1’ for word).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

RRC.B

0x1233

Before
Instruction
Data 1232 E807
SR
0000
Example 2:

RRC

0x820, WREG

; Rotate Right w/ C (0x1233) (Byte mode)

After
Instruction
Data 1232
7407
SR
0000
; Rotate Right w/ C (0x820) (Word mode)
; Store result in WREG

Instruction
Descriptions

Before
After
Instruction
Instruction
WREG (W0)
5601
WREG (W0) 90B7
Data 0820 216E
Data 0820 216E
SR
0001 (C = 1)
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

5

DS70157D-page 299

16-bit MCU and DSC Programmer’s Reference Manual

RRC

Rotate Right Ws through Carry

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

RRC{.B}

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
(C) → Wd<7>
(Ws<7:1>) → Wd<6:0>
(Ws<0>) → C
For word operation:
(C) → Wd<15>
(Ws<15:1>) → Wd<14:0>
(Ws<0>) → C
C

Status Affected:

N, Z, C

Encoding:

1101

Description:

0011

1Bqq

qddd

dppp

ssss

Rotate the contents of the source register Ws one bit to the right through
the Carry flag and place the result in the destination register Wd. The
Carry flag of the STATUS Register is shifted into the Most Significant bit
of Wd, and it is then overwritten with the Least Significant bit of Ws.
Either register direct or indirect addressing may be used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

RRC.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, W3

Before
Instruction
W0
9976
W3
5879
SR
0001 (C = 1)

DS70157D-page 300

; Rotate Right w/ C (W0) (Byte mode)
; Store the result in W3

After
Instruction
W0
9976
W3 58BB
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

Example 2:

RRC

[W2++], [W8]

; Rotate Right w/ C [W2] (Word mode)
; Post-increment W2
; Store result in [W8]

Before
After
Instruction
Instruction
W2
2008
W2 200A
W8 094E
W8 094E
Data 094E
3689
Data 094E E020
Data 2008 C041
Data 2008 C041
SR
0001 (C = 1)
SR
0009 (N, C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 301

16-bit MCU and DSC Programmer’s Reference Manual

RRNC

Rotate Right f without Carry

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
(f<7:1>) → Dest<6:0>
(f<0>) → Dest<7>
For word operation:
(f<15:1>) → Dest<14:0>
(f<0>) → Dest<15>

Status Affected:

N, Z

Encoding:

RRNC{.B}

1101

Description:

0111

f

{,WREG}

0BDf

ffff

ffff

ffff

Rotate the contents of the file register f one bit to the right and place the
result in the destination register. The Least Significant bit of f is stored in
the Most Significant bit of the destination, and the Carry flag is not
affected.
The optional WREG operand determines the destination register. If
WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

RRNC.B

0x1233

Before
Instruction
Data 1232 E807
SR
0000
Example 2:

RRNC

; Rotate Right (0x1233) (Byte mode)

After
Instruction
Data 1232
7407
SR
0000

0x820, WREG

; Rotate Right (0x820) (Word mode)
; Store result in WREG

Before
After
Instruction
Instruction
WREG (W0)
5601
WREG (W0) 10B7
Data 0820 216E
Data 0820 216E
SR
0001 (C = 1)
SR
0001 (C = 1)

DS70157D-page 302

© 2009 Microchip Technology Inc.

RRNC

Rotate Right Ws without Carry

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

RRNC{.B}

Ws,
[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
(Ws<7:1>) → Wd<6:0>
(Ws<0>) → Wd<7>
For word operation:
(Ws<15:1>) → Wd<14:0>
(Ws<0>) → Wd<15>

Status Affected:

N, Z

Encoding:
Description:

1101

0011

Wd

0Bqq

qddd

dppp

ssss

Rotate the contents of the source register Ws one bit to the right and
place the result in the destination register Wd. The Least Significant bit
of Ws is stored in the Most Significant bit of Wd, and the Carry flag is not
affected. Either register direct or indirect addressing may be used for Ws
and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

RRNC.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, W3

© 2009 Microchip Technology Inc.

After
Instruction
W0
9976
W3 583B
SR
0001 (C = 1)

5
Instruction
Descriptions

Before
Instruction
W0
9976
W3
5879
SR
0001 (C = 1)

; Rotate Right (W0) (Byte mode)
; Store the result in W3

DS70157D-page 303

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

RRNC

[W2++], [W8]

Before
Instruction
W2
2008
W8 094E
Data 094E
3689
Data 2008 C041
SR
0000

DS70157D-page 304

; Rotate Right [W2] (Word mode)
; Post-increment W2
; Store result in [W8]

After
Instruction
W2 200A
W8 094E
Data 094E E020
Data 2008 C041
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

SAC

Store Accumulator

Implemented in:

PIC24F

Syntax:

{label:}

PIC24H

SAC

dsPIC30F

dsPIC33F

X

X

Acc,

{#Slit4,}

Wd
[Wd]
[Wd++]
[Wd--]
[--Wd]
[++Wd]
[Wd + Wb]

Operands:

Acc ∈ [A,B]
Slit4 ∈ [-8 ... +7]
Wb, Wd ∈ [W0 ... W15]

Operation:

ShiftSlit4(Acc) (optional)
(Acc[31:16]) → Wd

Status Affected:

None

Encoding:

1100

Description:

1100

Awww

wrrr

rhhh

dddd

Perform an optional, signed 4-bit shift of the specified accumulator, then
store the shifted contents of ACCxH (Acc[31:16]) to Wd. The shift range
is -8:7, where a negative operand indicates an arithmetic left shift and a
positive operand indicates an arithmetic right shift. Either register direct
or indirect addressing may be used for Wd.
The ‘A’ bit specifies the source accumulator.
The ‘w’ bits specify the offset register Wb.
The ‘r’ bits encode the optional accumulator pre-shift.
The ‘h’ bits select the destination Address mode.
The ‘d’ bits specify the destination register Wd.
Note 1: This instruction does not modify the contents of Acc.
2: This instruction stores the truncated contents of Acc. The
instruction SAC.R may be used to store the rounded
accumulator contents.
3: If Data Write saturation is enabled (SATDW, CORCON<5>,
= 1), the value stored to Wd is subject to saturation after the
optional shift is performed.

Words:

1

Cycles:

1

Example 1:

SAC A, #4, W5
; Right shift ACCA by 4
; Store result to W5
; CORCON = 0x0010 (SATDW = 1)

© 2009 Microchip Technology Inc.

W5
ACCA
CORCON
SR

After
Instruction
0120
00 120F FF00
0010
0000

Instruction
Descriptions

W5
ACCA
CORCON
SR

Before
Instruction
B900
00 120F FF00
0010
0000

5

DS70157D-page 305

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

SAC B, #-4, [W5++]
; Left shift ACCB by 4
; Store result to [W5], Post-increment W5
; CORCON = 0x0010 (SATDW = 1)

W5
ACCB
Data 2000
CORCON
SR

DS70157D-page 306

Before
Instruction
2000
FF C891 8F4C
5BBE
0010
0000

W5
ACCB
Data 2000
CORCON
SR

After
Instruction
2002
FF C891 1F4C
8000
0010
0000

© 2009 Microchip Technology Inc.

SAC.R

Store Rounded Accumulator

Implemented in:

Syntax:

PIC24F

{label:}

PIC24H

SAC.R

dsPIC30F

dsPIC33F

X

X

Acc,

{#Slit4,}

Wd
[Wd]
[Wd++]
[Wd--]
[--Wd]
[++Wd]
[Wd + Wb]

Operands:

Acc ∈ [A,B]
Slit4 ∈ [-8 ... +7]
Wb ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

ShiftSlit4(Acc) (optional)
Round(Acc)
(Acc[31:16]) → Wd

Status Affected:

None

Encoding:
Description:

1100

1101

Awww

wrrr

rhhh

dddd

Perform an optional, signed 4-bit shift of the specified accumulator, then
store the rounded contents of ACCxH (Acc[31:16]) to Wd. The shift
range is -8:7, where a negative operand indicates an arithmetic left shift
and a positive operand indicates an arithmetic right shift. The Rounding
mode (Conventional or Convergent) is set by the RND bit,
CORCON<1>. Either register direct or indirect addressing may be used
for Wd.
The ‘A’ bit specifies the source accumulator.
The ‘w’ bits specify the offset register Wb.
The ‘r’ bits encode the optional accumulator pre-shift.
The ‘h’ bits select the destination Address mode.
The ‘d’ bits specify the destination register Wd.
Note 1: This instruction does not modify the contents of the Acc.
2: This instruction stores the rounded contents of Acc. The
instruction SAC may be used to store the truncated
accumulator contents.
3: If Data Write saturation is enabled (SATDW, CORCON<5>,
= 1), the value stored to Wd is subject to saturation after the
optional shift is performed.

Words:

1

Cycles:

1

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 307

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

SAC.R A, #4, W5
; Right shift ACCA by 4
; Store rounded result to W5
; CORCON = 0x0010 (SATDW = 1)

W5
ACCA
CORCON
SR
Example 2:

W5
ACCA
CORCON
SR

After
Instruction
0121
00 120F FF00
0010
0000

SAC.R B, #-4, [W5++]
; Left shift ACCB by 4
; Store rounded result to [W5], Post-increment W5
; CORCON = 0x0010 (SATDW = 1)

W5
ACCB
Data 2000
CORCON
SR

DS70157D-page 308

Before
Instruction
B900
00 120F FF00
0010
0000

Before
Instruction
2000
FF F891 8F4C
5BBE
0010
0000

W5
ACCB
Data 2000
CORCON
SR

After
Instruction
2002
FF F891 8F4C
8919
0010
0000

© 2009 Microchip Technology Inc.

SE

Sign-Extend Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SE

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]

Operation:

Ws<7:0> → Wnd<7:0>
If (Ws<7> = 1):
0xFF → Wnd<15:8>
Else:
0 → Wnd<15:8>

Status Affected:

N, Z, C

Encoding:

1111

Description:

1011

0000

0ddd

dppp

ssss

Sign-extend the byte in Ws and store the 16-bit result in Wnd. Either
register direct or indirect addressing may be used for Ws, and register
direct addressing must be used for Wnd. The C flag is set to the
complement of the N flag.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This operation converts a byte to a word, and it uses no .B or
.W extension.
2: The source Ws is addressed as a byte operand, so any
address modification is by ‘1’.

Words:

1

Cycles:

1

Example 1:

SE

W3, W4

; Sign-extend W3 and store to W4

Before
Instruction
W3
7839
W4
1005
SR
0000
Example 2:

SE

[W2++], W12

© 2009 Microchip Technology Inc.

; Sign-extend [W2] and store to W12
; Post-increment W2

After
Instruction
W2
0901
W12 FF8F
Data 0900
008F
SR
0008 (N = 1)

5
Instruction
Descriptions

Before
Instruction
W2
0900
W12
1002
Data 0900
008F
SR
0000

After
Instruction
W3
7839
W4
0039
SR
0001 (C = 1)

DS70157D-page 309

16-bit MCU and DSC Programmer’s Reference Manual

SETM

Set f or WREG

Implemented in:

Syntax:

PIC24F

{label:}

PIC24H

SETM{.B}

dsPIC30F

dsPIC33F

X

X

f
WREG

Operands:

f ∈ [0 ... 8191]

Operation:

For byte operation:
0xFF → destination designated by D
For word operation:
0xFFFF → destination designated by D

Status Affected:

None

Encoding:

1110

Description:

1111

1BDf

ffff

ffff

ffff

All the bits of the specified register are set to ‘1’. If WREG is specified,
the bits of WREG are set. Otherwise, the bits of the specified file register
are set.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

SETM.B

0x891

Before
Instruction
Data 0890
2739
SR
0000
Example 2:

SETM

WREG

Before
Instruction
WREG (W0)
0900
SR
0000

DS70157D-page 310

; Set 0x891 (Byte mode)

After
Instruction
Data 0890 FF39
SR
0000
; Set WREG (Word mode)

After
Instruction
WREG (W0) FFFF
SR
0000

© 2009 Microchip Technology Inc.

SETM

Set Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SETM{.B}

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wd ∈ [W0 ... W15]

Operation:

For byte operation:
0xFF → Wd for byte operation
For word operation:
0xFFFF → Wd for word operation

Status Affected:

None

Encoding:

1110

Description:

1011

1Bqq

qddd

d000

0000

All the bits of the specified register are set to ‘1’. Either register direct or
indirect addressing may be used for Wd.
The ‘B’ bits selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.

Words:

1

Cycles:

1

Example 1:

SETM.B

Note:

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W13

; Set W13 (Byte mode)

Before
Instruction
W13
2739
SR
0000
Example 2:

SETM

[--W6]

© 2009 Microchip Technology Inc.

; Pre-decrement W6 (Word mode)
; Set [W6]

After
Instruction
W6 124E
Data 124E FFFF
SR
0000

5
Instruction
Descriptions

Before
Instruction
W6
1250
Data 124E 3CD9
SR
0000

After
Instruction
W13 27FF
SR
0000

DS70157D-page 311

16-bit MCU and DSC Programmer’s Reference Manual

SFTAC

Arithmetic Shift Accumulator by Slit6

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Acc ∈ [A,B]
Slit6 ∈ [-16 ... 16]

Operation:

Shiftk(Acc) → Acc

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

1100

Description:

SFTAC

dsPIC30F

1000

Acc,

A000

#Slit6

0000

01kk

kkkk

Arithmetic shift the 40-bit contents of the specified accumulator by the
signed, 6-bit literal and store the result back into the accumulator. The
shift range is -16:16, where a negative operand indicates a left shift and a
positive operand indicates a right shift. Any bits which are shifted out of
the accumulator are lost.
The ‘A’ bit selects the accumulator for the result.
The ‘k’ bits determine the number of bits to be shifted.
Note 1: If saturation is enabled for the target accumulator (SATA,
CORCON<7> or SATB, CORCON<6>), the value stored to
the accumulator is subject to saturation.
2: If the shift amount is greater than 16 or less than -16, no
modification will be made to the accumulator, and an
arithmetic trap will occur.

Words:

1

Cycles:

1

Example 1:

SFTAC A, #12
; Arithmetic right shift ACCA by 12
; Store result to ACCA
; CORCON = 0x0080 (SATA = 1)

ACCA
CORCON
SR
Example 2:

ACCA
CORCON
SR

After
Instruction
00 0001 20FF
0080
0000

SFTAC B, #-10
; Arithmetic left shift ACCB by 10
; Store result to ACCB
; CORCON = 0x0040 (SATB = 1)

ACCB
CORCON
SR

DS70157D-page 312

Before
Instruction
00 120F FF00
0080
0000

Before
Instruction
FF FFF1 8F4C
0040
0000

ACCB
CORCON
SR

After
Instruction
FF C63D 3000
0040
0000

© 2009 Microchip Technology Inc.

SFTAC

Arithmetic Shift Accumulator by Wb

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

Syntax:

{label:}

Operands:

Acc ∈ [A,B]
Wb ∈ [W0 ... W15]

Operation:

Shift(Wb)(Acc) → Acc

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

1100

Description:

SFTAC

dsPIC30F

1000

Acc,

A000

Wb

0000

0000

ssss

Arithmetic shift the 40-bit contents of the specified accumulator and store
the result back into the accumulator. The Least Significant 6 bits of Wb
are used to specify the shift amount. The shift range is -16:16, where a
negative value indicates a left shift and a positive value indicates a right
shift. Any bits which are shifted out of the accumulator are lost.
The ‘A’ bit selects the accumulator for the source/destination.
The ‘s’ bits select the address of the shift count register.
Note 1: If saturation is enabled for the target accumulator (SATA,
CORCON<7> or SATB, CORCON<6>), the value stored to
the accumulator is subject to saturation.
2: If the shift amount is greater than 16 or less than -16, no
modification will be made to the accumulator, and an
arithmetic trap will occur.

Words:

1

Cycles:

1

Example 1:

SFTAC A, W0
; Arithmetic shift ACCA by (W0)
; Store result to ACCA
; CORCON = 0x0000 (saturation disabled)

W0
ACCA
CORCON
SR
Example 2:

W0
ACCA
CORCON
SR

After
Instruction
FFFC
03 20FA B090
0000
8800 (OA, OAB = 1)

SFTAC B, W12
; Arithmetic shift ACCB by (W12)
; Store result to ACCB
; CORCON = 0x0040 (SATB = 1)

Before
Instruction
000F
FF FFF1 8F4C
0040
0000

W12
ACCB
CORCON
SR

5
After
Instruction
000F
FF FFFF FFE3
0040
0000

Instruction
Descriptions

W12
ACCB
CORCON
SR

© 2009 Microchip Technology Inc.

Before
Instruction
FFFC
00 320F AB09
0000
0000

DS70157D-page 313

16-bit MCU and DSC Programmer’s Reference Manual

SL

Shift Left f

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

SL{.B}

Operands:

f ∈ [0... 8191]

Operation:

For byte operation:
(f<7>) → (C)
(f<6:0>) → Dest<7:1>
0 → Dest<0>
For word operation:
(f<15>) → (C)
(f<14:0>) → Dest<15:1>
0 → Dest<0>
C

Status Affected:

{,WREG}

0

N, Z, C

Encoding:

1101

Description:

f

0100

0BDf

ffff

ffff

ffff

Shift the contents of the file register one bit to the left and place the result
in the destination register. The Most Significant bit of the file register is
shifted into the Carry bit of the STATUS register, and zero is shifted into
the Least Significant bit of the destination register.
The optional WREG operand determines the destination register. If
WREG is specified, the result is stored in WREG. If WREG is not
specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

SL.B

0x909

Before
Instruction
Data 0908
9439
SR
0000
Example 2:

SL

After
Instruction
Data 0908
0839
SR
0001 (C = 1)

0x1650, WREG

Before
Instruction
WREG (W0)
0900
Data 1650
4065
SR
0000

DS70157D-page 314

; Shift left (0x909) (Byte mode)

; Shift left (0x1650) (Word mode)
; Store result in WREG

After
Instruction
WREG (W0) 80CA
Data 1650
4065
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

SL

Shift Left Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SL{.B}

Ws,
[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
(Ws<7>) → C
(Ws<6:0>) → Wd<7:1>
0 → Wd<0>
For word operation:
(Ws<15>) → C
(Ws<14:0>) → Wd<15:1>
0 → Wd<0>
C

Status Affected:

Wd

0

N, Z, C

Encoding:

1101

Description:

0000

0Bqq

qddd

dppp

ssss

Shift the contents of the source register Ws one bit to the left and place
the result in the destination register Wd. The Most Significant bit of Ws is
shifted into the Carry bit of the STATUS register, and ‘0’ is shifted into the
Least Significant bit of Wd. Either register direct or indirect addressing
may be used for Ws and Wd.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

SL.B

W3, W4

© 2009 Microchip Technology Inc.

5

; Shift left W3 (Byte mode)
; Store result to W4

Instruction
Descriptions

Before
Instruction
W3 78A9
W4
1005
SR
0000

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

After
Instruction
W3 78A9
W4
1052
SR
0001 (C = 1)

DS70157D-page 315

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

SL

[W2++], [W12]

Before
Instruction
W2
0900
W12
1002
Data 0900
800F
Data 1002
6722
SR
0000

DS70157D-page 316

; Shift left [W2] (Word mode)
; Store result to [W12]
; Post-increment W2

After
Instruction
W2
0902
W12
1002
Data 0900
800F
Data 1002 001E
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

SL

Shift Left by Short Literal

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
lit4 ∈ [0...15]
Wnd ∈ [W0 ... W15]

Operation:

lit4<3:0> → Shift_Val
Wnd<15:Shift_Val> = Wb<15-Shift_Val:0>
Wd = 0

Status Affected:

N, Z

Encoding:

1101

Description:

SL

Wb,

1101

#lit4,

0www

wddd

Wnd

d100

kkkk

Shift left the contents of the source register Wb by the 4-bit unsigned
literal and store the result in the destination register Wnd. Any bits
shifted out of the source register are lost. Direct addressing must be
used for Wb and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

SL

W2, #4, W2

Before
Instruction
W2 78A9
SR
0000
Example 2:

SL

W3, #12, W8

Before
Instruction
W3
0912
W8
1002
SR
0000

This instruction operates in Word mode only.

; Shift left W2 by 4
; Store result to W2

After
Instruction
W2 8A90
SR
0008 (N = 1)
; Shift left W3 by 12
; Store result to W8

After
Instruction
W3
0912
W8
2000
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 317

16-bit MCU and DSC Programmer’s Reference Manual

SL

Shift Left by Wns

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

Wb ∈ [W0 ... W15]
Wns ∈ [W0 ...W15]
Wnd ∈ [W0 ... W15]

Operation:

Wns<4:0> → Shift_Val
Wnd<15:Shift_Val> = Wb<15 – Shift_Val:0>
Wd = 0

Status Affected:

N, Z

Encoding:

1101

Description:

SL

Wb,

1101

0www

Wns,

Wnd

wddd

d000

ssss

Shift left the contents of the source register Wb by the 5 Least Significant
bits of Wns (only up to 15 positions) and store the result in the destination register Wnd. Any bits shifted out of the source register are lost.
Register direct addressing must be used for Wb, Wns and Wnd.
The ‘w’ bits select the address of the base register.
The ‘d’ bits select the destination register.
The ‘s’ bits select the source register.
Note 1: This instruction operates in Word mode only.
2: If Wns is greater than 15, Wnd will be loaded with 0x0.

Words:

1

Cycles:

1

Example 1:

SL

W0, W1, W2

Before
Instruction
W0 09A4
W1
8903
W2 78A9
SR
0000
Example 2:

SL

W4, W5, W6

Before
Instruction
W4 A409
W5 FF01
W6
0883
SR
0000

DS70157D-page 318

; Shift left W0 by W1<0:4>
; Store result to W2

After
Instruction
W0 09A4
W1
8903
W2 4D20
SR
0000
; Shift left W4 by W5<0:4>
; Store result to W6

After
Instruction
W4 A409
W5 FF01
W6
4812
SR
0000

© 2009 Microchip Technology Inc.

SUB

Subtract WREG from f

Implemented in:

PIC24F

PIC24H

X

X

X

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) – (WREG) → destination designated by D

Status Affected:

DC, N, OV, Z, C
1011

Description:

0101

f

X

Syntax:

Encoding:

SUB{.B}

dsPIC30F dsPIC33F

{,WREG}

0BDf

ffff

ffff

ffff

Subtract the contents of the default working register WREG from the
contents of the specified file register, and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

SUB.B 0x1FFF

; Sub. WREG from (0x1FFF) (Byte mode)
; Store result to 0x1FFF

Before
Instruction
WREG (W0)
7804
Data 1FFE
9439
SR
0000
Example 2:

SUB

0xA04, WREG

Before
Instruction
WREG (W0)
6234
Data 0A04
4523
SR
0000

After
Instruction
WREG (W0)
7804
Data 1FFE
9039
SR
0009 (N, C = 1)
; Sub. WREG from (0xA04) (Word mode)
; Store result to WREG

After
Instruction
WREG (W0) E2EF
Data 0A04
4523
SR
0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 319

16-bit MCU and DSC Programmer’s Reference Manual

SUB

Subtract Literal from Wn

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

(Wn) – lit10 → Wn

Status Affected:

DC, N, OV, Z, C

Encoding:

SUB{.B}

1011

Description:

0001

#lit10,

0Bkk

Wn

kkkk

kkkk

dddd

Subtract the 10-bit unsigned literal operand from the contents of the
working register Wn, and store the result back in the working register
Wn. Register direct addressing must be used for Wn.
The ‘B’ bit selects byte or word operation.
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an unsigned
value [0:255]. See Section 4.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte
mode.

Words:

1

Cycles:

1

Example 1:

SUB.B

#0x23, W0

Before
Instruction
W0
7804
SR
0000
Example 2:

SUB

#0x108, W4

Before
Instruction
W4
6234
SR
0000

DS70157D-page 320

; Sub. 0x23 from W0 (Byte mode)
; Store result to W0

After
Instruction
W0 78E1
SR
0008 (N = 1)
; Sub. 0x108 from W4 (Word mode)
; Store result to W4

After
Instruction
W4 612C
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

SUB

Subtract Short Literal from Wb

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUB{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb) – lit5 → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0101

Description:

0www

wBqq

qddd

d11k

kkkk

Subtract the 5-bit unsigned literal operand from the contents of the base
register Wb, and place the result in the destination register Wd. Register
direct addressing must be used for Wb. Register direct or indirect
addressing must be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

SUB.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W4, #0x10, W5

Before
Instruction
W4
1782
W5
7804
SR
0000
Example 2:

SUB

; Sub. 0x8 from W0 (Word mode)
; Store result to [W2]
; Post-increment W2

After
Instruction
W0
F230
W2
2006
Data 2004
F228
SR
0009 (N, C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

After
Instruction
W4
1782
W5
7872
SR
0005 (OV, C = 1)

W0, #0x8, [W2++]

Before
Instruction
W0
F230
W2
2004
Data 2004 A557
SR
0000

; Sub. 0x10 from W4 (Byte mode)
; Store result to W5

DS70157D-page 321

16-bit MCU and DSC Programmer’s Reference Manual

SUB

Subtract Ws from Wb

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUB{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb) – (Ws) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0101

Description:

0www

Wb,

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Subtract the contents of the source register Ws from the contents of the
base register Wb and place the result in the destination register Wd.
Register direct addressing must be used for Wb. Either register direct or
indirect addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

SUB.B

W0, W1, W0

Before
Instruction
W0
1732
W1
7844
SR
0000

DS70157D-page 322

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

; Sub. W1 from W0 (Byte mode)
; Store result to W0

After
Instruction
W0 17EE
W1
7844
SR
0108 (DC, N = 1)

© 2009 Microchip Technology Inc.

Example 2:

SUB

W7, [W8++], [W9++]

Before
Instruction
W7
2450
W8
1808
W9
2020
Data 1808 92E4
Data 2020 A557
SR
0000

;
;
;
;

Sub. [W8] from W7 (Word mode)
Store result to [W9]
Post-increment W8
Post-increment W9

After
Instruction
W7
2450
W8 180A
W9
2022
Data 1808 92E4
Data 2020 916C
SR 010C (DC, N, OV = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 323

16-bit MCU and DSC Programmer’s Reference Manual

SUB

Subtract Accumulators

Implemented in:

PIC24F

PIC24H

dsPIC33F

X

X

A011

0000

Syntax:

{label:}

Operands:

Acc ∈ [A,B]

Operation:

If (Acc = A):
ACCA – ACCB → ACCA
Else:
ACCB – ACCA → ACCB

Status Affected:

OA, OB, OAB, SA, SB, SAB

Encoding:

SUB

dsPIC30F

1100

Description:

1011

Acc

0000

0000

Subtract the contents of the unspecified accumulator from the contents
of Acc, and store the result back into Acc. This instruction performs a
40-bit subtraction.
The ‘A’ bit specifies the destination accumulator.

Words:

1

Cycles:

1

Example 1:

SUB

A

Before
Instruction
76 120F 098A
23 F312 BC17
0000
0000

ACCA
ACCB
CORCON
SR
Example 2:

SUB

ACCA
ACCB
CORCON
SR

DS70157D-page 324

; Subtract ACCB from ACCA
; Store the result to ACCA
; CORCON = 0x0000 (no saturation)

B

ACCA
ACCB
CORCON
SR

After
Instruction
52 1EFC 4D73
23 F312 BC17
0000
1100 (OA, OB = 1)

; Subtract ACCA from ACCB
; Store the result to ACCB
; CORCON = 0x0040 (SATB = 1)

Before
Instruction
FF 9022 2EE1
00 2456 8F4C
0040
0000

ACCA
ACCB
CORCON
SR

After
Instruction
FF 9022 2EE1
00 7FFF FFFF
0040
1400 (SB, SAB = 1)

© 2009 Microchip Technology Inc.

SUBB

Subtract WREG and Carry bit from f

Implemented in:

PIC24F

PIC24H

X

X

X

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f) – (WREG) – (C) → destination designated by D

Status Affected:

DC, N, OV, Z, C

Description:

1011

0101

f

X

Syntax:

Encoding:

SUBB{.B}

dsPIC30F dsPIC33F

{,WREG}

1BDf

ffff

ffff

ffff

Subtract the contents of the default working register WREG and the
Borrow flag (Carry flag inverse, C) from the contents of the specified file
register and place the result in the destination register. The optional
WREG operand determines the destination register. If WREG is
specified, the result is stored in WREG. If WREG is not specified, the
result is stored in the file register
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBB.B 0x1FFF

; Sub. WREG and C from (0x1FFF) (Byte mode)
; Store result to 0x1FFF

Before
Instruction
WREG (W0)
7804
Data 1FFE
9439
SR
0000
Example 2:

SUBB 0xA04, WREG

Before
Instruction
WREG (W0)
6234
Data 0A04
6235
SR
0000

After
Instruction
WREG (W0)
7804
Data 1FFE
8F39
SR
0008 (N = 1)
; Sub. WREG and C from (0xA04) (Word mode)
; Store result to WREG

After
Instruction
WREG (W0)
0000
Data 0A04
6235
SR
0001 (C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 325

16-bit MCU and DSC Programmer’s Reference Manual

SUBB

Subtract Wn from Literal with Borrow

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

(Wn) – lit10 – (C) → Wn

Status Affected:

DC, N, OV, Z, C

Encoding:

SUBB{.B}

1011

Description:

0001

#lit10,

1Bkk

Wn

kkkk

kkkk

dddd

Subtract the unsigned 10-bit literal operand and the Borrow flag (Carry
flag inverse, C) from the contents of the working register Wn, and store
the result back in the working register Wn. Register direct addressing
must be used for Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .w extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an
unsigned value [0:255]. See Section 4.6 “Using 10-bit Literal
Operands” for information on using 10-bit literal operands in
Byte mode.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBB.B

#0x23, W0

Before
Instruction
W0
7804
SR
0000
Example 2:

SUBB

#0x108, W4

Before
Instruction
W4
6234
SR
0001 (C = 1)

DS70157D-page 326

; Sub. 0x23 and C from W0 (Byte mode)
; Store result to W0

After
Instruction
W0 78E0
SR
0108 (DC, N = 1)
; Sub. 0x108 and C from W4 (Word mode)
; Store result to W4

After
Instruction
W4 612C
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

SUBB

Subtract Short Literal from Wb with Borrow

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUBB{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb) – lit5 – (C) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0101

Description:

1www

wBqq

qddd

d11k

kkkk

Subtract the 5-bit unsigned literal operand and the Borrow flag (Carry
flag inverse, C) from the contents of the base register Wb and place the
result in the destination register Wd. Register direct addressing must be
used for Wb. Either register direct or indirect addressing may be used for
Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBB.B

W4, #0x10, W5

Before
Instruction
W4
1782
W5
7804
SR
0000

; Sub. 0x10 and C from W4 (Byte mode)
; Store result to W5

After
Instruction
W4
1782
W5
7871
SR
0005 (OV, C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 327

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

SUBB

W0, #0x8, [W2++]

; Sub. 0x8 and C from W0 (Word mode)
; Store result to [W2]
; Post-increment W2

Before
After
Instruction
Instruction
W0
0009
W0
0009
W2
2004
W2
2006
Data 2004 A557
Data 2004
0000
SR
0020 (Z = 1)
SR
0103 (DC, Z, C = 1)

DS70157D-page 328

© 2009 Microchip Technology Inc.

SUBB

Subtract Ws from Wb with Borrow

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUBB{.B}

Wb,

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb) – (Ws) – (C) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0101

Description:

1www

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Subtract the contents of the source register Ws and the Borrow flag
(Carry flag inverse, C) from the contents of the base register Wb, and
place the result in the destination register Wd. Register direct addressing
must be used for Wb. Register direct or indirect addressing may be used
for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBB.B

W0, W1, W0

Before
Instruction
W0
1732
W1
7844
SR
0000

; Sub. W1 and C from W0 (Byte mode)
; Store result to W0

After
Instruction
W0 17ED
W1
7844
SR
0108 (DC, N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 329

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

SUBB

W7,[W8++],[W9++] ;
;
;
;

Before
Instruction
W7
2450
W8
1808
W9
2022
Data 1808 92E4
Data 2022 A557
SR
0000

DS70157D-page 330

Sub. [W8] and C from W7 (Word mode)
Store result to [W9]
Post-increment W8
Post-increment W9

After
Instruction
W7
2450
W8 180A
W9
2024
Data 1808 92E4
Data 2022 916C
SR 010C (DC, N, OV = 1)

© 2009 Microchip Technology Inc.

SUBBR

Subtract f from WREG with Borrow

Implemented in:

PIC24F

PIC24H

X

X

dsPIC30F dsPIC33F
X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(WREG) – (f) – (C) → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:
Description:

1011

SUBBR{.B} f

X

1101

{,WREG}

1BDf

ffff

ffff

ffff

Subtract the contents of the specified file register f and the Borrow flag
(Carry flag inverse, C) from the contents of WREG, and place the result
in the destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.
3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBBR.B 0x803

; Sub. (0x803) and C from WREG (Byte mode)
; Store result to 0x803

Before
After
Instruction
Instruction
WREG (W0)
7804
WREG (W0)
7804
Data 0802
9439
Data 0802
6F39
SR
0002 (Z = 1)
SR
0000
Example 2:

SUBBR 0xA04, WREG ; Sub. (0xA04) and C from WREG (Word mode)
; Store result to WREG

Before
Instruction
WREG (W0)
6234
Data 0A04
6235
SR
0000

After
Instruction
WREG (W0) FFFE
Data 0A04
6235
SR
0008 (N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 331

16-bit MCU and DSC Programmer’s Reference Manual

SUBBR

Subtract Wb from Short Literal with Borrow

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUBBR{.B} Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

lit5 – (Wb) – (C) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0001

Description:

1www

wBqq

qddd

d11k

kkkk

Subtract the contents of the base register Wb and the Borrow flag (Carry
flag inverse, C) from the 5-bit unsigned literal and place the result in the
destination register Wd. Register direct addressing must be used for Wb.
Register direct or indirect addressing must be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBBR.B

W0, #0x10, W1 ; Sub. W0 and C from 0x10 (Byte mode)
; Store result to W1

Before
Instruction
W0
F310
W1 786A
SR
0003 (Z, C = 1)

DS70157D-page 332

After
Instruction
W0
F310
W1
7800
SR
0103 (DC, Z, C = 1)

© 2009 Microchip Technology Inc.

Example 2:

SUBBR

W0, #0x8, [W2++] ; Sub. W0 and C from 0x8 (Word mode)
; Store result to [W2]
; Post-increment W2

Before
After
Instruction
Instruction
W0
0009
W0
0009
W2
2004
W2
2006
Data 2004 A557
Data 2004 FFFE
SR
0020 (Z = 1)
SR
0108 (DC, N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 333

16-bit MCU and DSC Programmer’s Reference Manual

SUBBR

Subtract Wb from Ws with Borrow

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUBBR{.B} Wb,

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) – (Wb) – (C) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0001

Description:

1www

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Subtract the contents of the base register Wb and the Borrow flag (Carry
flag inverse, C) from the contents of the source register Ws and place
the result in the destination register Wd. Register direct addressing must
be used for Wb. Register direct or indirect addressing may be used for
Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These
instructions can only clear Z.

Words:

1

Cycles:

1

Example 1:

SUBBR.B

W0, W1, W0

Before
Instruction
W0
1732
W1
7844
SR
0000

DS70157D-page 334

; Sub. W0 and C from W1 (Byte mode)
; Store result to W0

After
Instruction
W0
1711
W1
7844
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

Example 2:

SUBBR W7,[W8++],[W9++] ;
;
;
;

Before
Instruction
W7
2450
W8
1808
W9
2022
Data 1808 92E4
Data 2022 A557
SR
0000

Sub. W7 and C from [W8] (Word mode)
Store result to [W9]
Post-increment W8
Post-increment W9

After
Instruction
W7
2450
W8 180A
W9
2024
Data 1808 92E4
Data 2022 6E93
SR
0005 (OV, C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 335

16-bit MCU and DSC Programmer’s Reference Manual

SUBR

Subtract f from WREG

Implemented in:

PIC24F

PIC24H

X

X

dsPIC30F dsPIC33F
X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(WREG) – (f) → destination designated by D

Status Affected:

DC, N, OV, Z, C

Encoding:

SUBR{.B} f

X

1011

Description:

1101

{,WREG}

0BDf

ffff

ffff

ffff

Subtract the contents of the specified file register from the contents of
the default working register WREG, and place the result in the
destination register. The optional WREG operand determines the
destination register. If WREG is specified, the result is stored in WREG.
If WREG is not specified, the result is stored in the file register
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

SUBR.B

0x1FFF

Before
Instruction
WREG (W0)
7804
Data 1FFE
9439
SR
0000
Example 2:

SUBR

After
Instruction
WREG (W0)
7804
Data 1FFE
7039
SR
0000

0xA04, WREG

Before
Instruction
WREG (W0)
6234
Data 0A04
6235
SR
0000

DS70157D-page 336

; Sub. (0x1FFF) from WREG (Byte mode)
; Store result to 0x1FFF

; Sub. (0xA04) from WREG (Word mode)
; Store result to WREG

After
Instruction
WREG (W0) FFFF
Data 0A04
6235
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

SUBR

Subtract Wb from Short Literal

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUBR{.B}

Wb,

#lit5

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

lit5 – (Wb) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0001

Description:

0www

wBqq

qddd

d11k

kkkk

Subtract the contents of the base register Wb from the unsigned 5-bit
literal operand, and place the result in the destination register Wd.
Register direct addressing must be used for Wb. Either register direct or
indirect addressing may be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a five-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

SUBR.B

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

W0, #0x10, W1

Before
Instruction
W0
F310
W1 786A
SR
0000
Example 2:

SUBR

; Sub. W0 from 0x8 (Word mode)
; Store result to [W2]
; Post-increment W2

After
Instruction
W0
0009
W2
2006
Data 2004 FFFF
SR
0108 (DC, N = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

After
Instruction
W0
F310
W1
7800
SR
0103 (DC, Z, C = 1)

W0, #0x8, [W2++]

Before
Instruction
W0
0009
W2
2004
Data 2004 A557
SR
0000

; Sub. W0 from 0x10 (Byte mode)
; Store result to W1

DS70157D-page 337

16-bit MCU and DSC Programmer’s Reference Manual

SUBR

Subtract Wb from Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

SUBR{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Ws) – (Wb) → Wd

Status Affected:

DC, N, OV, Z, C

Encoding:

0001

Description:

0www

Wb,

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Subtract the contents of the base register Wb from the contents of the
source register Ws and place the result in the destination register Wd.
Register direct addressing must be used for Wb. Either register direct or
indirect addressing may be used for Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

SUBR.B

W0, W1, W0

Before
Instruction
W0
1732
W1
7844
SR
0000

DS70157D-page 338

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

; Sub. W0 from W1 (Byte mode)
; Store result to W0

After
Instruction
W0
1712
W1
7844
SR
0001 (C = 1)

© 2009 Microchip Technology Inc.

Example 2:

SUBR

W7, [W8++], [W9++]

Before
Instruction
W7
2450
W8
1808
W9
2022
Data 1808 92E4
Data 2022 A557
SR
0000

;
;
;
;

Sub. W7 from [W8] (Word mode)
Store result to [W9]
Post-increment W8
Post-increment W9

After
Instruction
W7
2450
W8 180A
W9
2024
Data 1808 92E4
Data 2022 6E94
SR
0005 (OV, C = 1)

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 339

16-bit MCU and DSC Programmer’s Reference Manual

SWAP

Byte or Nibble Swap Wn

Implemented in:

PIC24F

PIC24H

X

X

dsPIC30F dsPIC33F
X

X

1B00

0000

Syntax:

{label:}

Operands:

Wn ∈ [W0 ... W15]

Operation:

For byte operation:
(Wn)<7:4> ↔ (Wn)<3:0>
For word operation:
(Wn)<15:8> ↔ (Wn)<7:0>

Status Affected:

None

Encoding:

SWAP{.B} Wn

1111

Description:

1101

0000

ssss

Swap the contents of the working register Wn. In Word mode, the two
bytes of Wn are swapped. In Byte mode, the two nibbles of the Least
Significant Byte of Wn are swapped, and the Most Significant Byte of
Wn is unchanged. Register direct addressing must be used for Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘s’ bits select the address of the working register.
Note:

Words:

1

Cycles:

1

Example 1:

SWAP.B

W0

Before
Instruction
W0 AB87
SR
0000
Example 2:

SWAP

W0

Before
Instruction
W0
8095
SR
0000

DS70157D-page 340

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

; Nibble swap (W0)

After
Instruction
W0 AB78
SR
0000
; Byte swap (W0)

After
Instruction
W0
9580
SR
0000

© 2009 Microchip Technology Inc.

TBLRDH

Table Read High

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

TBLRDH{.B} [Ws],

Wd

[Ws++],

[Wd]

[Ws--],

[Wd++]

[++Ws],

[Wd--]

[--Ws],

[++Wd]
[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
If (LSB(Ws) = 1)
0 → Wd
Else
Program Mem [(TBLPAG),(Ws)] <23:16> → Wd
For word operation:
Program Mem [(TBLPAG),(Ws)] <23:16> → Wd <7:0>
0 → Wd <15:8>

Status Affected:

None

Encoding:
Description:

1011

1010

1Bqq

qddd

dppp

ssss

Read the contents of the most significant word of program memory and
store it to the destination register Wd. The target word address of program
memory is formed by concatenating the 8-bit Table Pointer register,
TBLPAG<7:0>, with the effective address specified by Ws. Indirect
addressing must be used for Ws, and either register direct or indirect
addressing may be used for Wd.
In Word mode, zero is stored to the Most Significant Byte of the destination
register (due to non-existent program memory) and the third program
memory byte (PM<23:16>) at the specified program memory address is
stored to the Least Significant Byte of the destination register.
In Byte mode, the source address depends on the contents of Ws. If Ws is
not word-aligned, zero is stored to the destination register (due to
non-existent program memory). If Ws is word-aligned, the third program
memory byte (PM<23:16>) at the specified program memory address is
stored to the destination register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

1

Cycles:

2

© 2009 Microchip Technology Inc.

DS70157D-page 341

5
Instruction
Descriptions

Words:

The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

TBLRDH.B

W0
W1
Data 0F70
Program 01 0812
TBLPAG
SR
Example 2:

DS70157D-page 342

Before
Instruction
0812
0F71
0944
EF 2042
0001
0000

TBLRDH

W6
W8
Program 00 3406
TBLPAG
SR

[W0], [W1++]

W0
W1
Data 0F70
Program 01 0812
TBLPAG
SR

[W6++], W8

Before
Instruction
3406
65B1
29 2E40
0000
0000

; Read PM (TBLPAG:[W0]) (Byte mode)
; Store to [W1]
; Post-increment W1

After
Instruction
0812
0F72
EF44
EF 2042
0001
0000

; Read PM (TBLPAG:[W6]) (Word mode)
; Store to W8
; Post-increment W6

W6
W8
Program 00 3406
TBLPAG
SR

After
Instruction
3408
0029
29 2E40
0000
0000

© 2009 Microchip Technology Inc.

TBLRDL

Table Read Low

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

TBLRDL{.B} [Ws],

Wd

[Ws++],

[Wd]

[Ws--],

[Wd++]

[++Ws],

[Wd--]

[--Ws],

[++Wd]
[--Wd]

Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
If (LSB(Ws) = 1)
Program Mem [(TBLPAG),(Ws)] <15:8> → Wd
Else
Program Mem [(TBLPAG),(Ws)] <7:0> → Wd
For word operation:
Program Mem [(TBLPAG),(Ws)] <15:0> → Wd

Status Affected:

None

Encoding:
Description:

1011

1010

0Bqq

qddd

dppp

ssss

Read the contents of the least significant word of program memory and
store it to the destination register Wd. The target word address of program
memory is formed by concatenating the 8-bit Table Pointer register,
TBLPAG<7:0>, with the effective address specified by Ws. Indirect
addressing must be used for Ws, and either register direct or indirect
addressing may be used for Wd.
In Word mode, the lower 2 bytes of program memory are stored to the
destination register. In Byte mode, the source address depends on the
contents of Ws. If Ws is not word-aligned, the second byte of the program
memory word (PM<15:7>) is stored to the destination register. If Ws is
word-aligned, the first byte of the program memory word (PM<7:0>) is
stored to the destination register.
The ‘B’ bit selects byte or word operation (‘0’ for word mode, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

2

The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a
word move, but it is not required.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 343

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

TBLRDL.B

W0
W1
Data 0F70
Program 01 0812
TBLPAG
SR
Example 2:

DS70157D-page 344

Before
Instruction
0813
0F71
0944
EF 2042
0001
0000

TBLRDL

W6
W8
Data 1202
Program 00 3406
TBLPAG
SR

[W0++], W1

W0
W1
Data 0F70
Program 01 0812
TBLPAG
SR

[W6], [W8++]

Before
Instruction
3406
1202
658B
29 2E40
0000
0000

; Read PM (TBLPAG:[W0]) (Byte mode)
; Store to W1
; Post-increment W0

After
Instruction
0814
0F20
EF44
EF 2042
0001
0000

; Read PM (TBLPAG:[W6]) (Word mode)
; Store to W8
; Post-increment W8

W6
W8
Data 1202
Program 00 3406
TBLPAG
SR

After
Instruction
3408
1204
2E40
29 2E40
0000
0000

© 2009 Microchip Technology Inc.

TBLWTH

Table Write High

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

TBLWTH{.B} Ws,

[Wd]

[Ws],

[Wd++]

[Ws++],

[Wd--]

[Ws--],

[++Wd]

[++Ws],

[--Wd]

[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
If (LSB(Wd) = 1)
NOP
Else
(Ws) → Program Mem [(TBLPAG),(Wd)]<23:16>
For word operation:
(Ws)<7:0> → Program Mem [(TBLPAG),(Wd)] <23:16>

Status Affected:

None

Encoding:
Description:

1011

1011

1Bqq

qddd

dppp

ssss

Store the contents of the working source register Ws to the most significant
word of program memory. The destination word address of program memory is formed by concatenating the 8-bit Table Pointer register,
TBLPAG<7:0>, with the effective address specified by Wd. Either direct or
indirect addressing may be used for Ws, and indirect addressing must be
used for Wd.
Since program memory is 24 bits wide, this instruction can only write to the
upper byte of program memory (PM<23:16>). This may be performed using
a Wd that is word-aligned in Byte mode or Word mode. If Byte mode is
used with a Wd that is not word-aligned, no operation is performed.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

2

The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a word
move, but it is not required.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 345

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

TBLWTH.B

W0
W1
Data 0812
Program 01 0F70
TBLPAG
SR

Before
Instruction
0812
0F70
0944
EF 2042
0001
0000

Note:

Example 2:

Note:

DS70157D-page 346

; Write [W0]... (Byte mode)
; to PM Latch High (TBLPAG:[W1])
; Post-increment W0

W0
W1
Data 0812
Program 01 0F70
TBLPAG
SR

After
Instruction
0812
0F70
EF44
44 2042
0001
0000

Only the Program Latch is written to. The contents of program memory
are not updated until the Flash memory is programmed using the
procedure described in the specific device family reference manual.

TBLWTH

W6
W8
Program 00 0870
TBLPAG
SR

[W0++], [W1]

W6, [W8++]

Before
Instruction
0026
0870
22 3551
0000
0000

; Write W6... (Word mode)
; to PM Latch High (TBLPAG:[W8])
; Post-increment W8

W6
W8
Program 00 0870
TBLPAG
SR

After
Instruction
0026
0872
26 3551
0000
0000

Only the Program Latch is written to. The contents of program memory
are not updated until the Flash memory is programmed using the
procedure described in the specific device family reference manual.

© 2009 Microchip Technology Inc.

TBLWTL

Table Write Low

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

TBLWTL{.B} Ws,

[Wd]

[Ws],

[Wd++]

[Ws++],

[Wd--]

[Ws--],

[++Wd]

[++Ws],

[--Wd]

[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

For byte operation:
If (LSB(Wd)=1)
(Ws) → Program Mem [(TBLPAG),(Wd)] <15:8>
Else
(Ws) → Program Mem [(TBLPAG),(Wd)] <7:0>
For word operation:
(Ws) → Program Mem [(TBLPAG),(Wd)] <15:0>

Status Affected:

None

Encoding:
Description:

1011

1011

0Bqq

qddd

dppp

ssss

Store the contents of the working source register Ws to the least significant
word of program memory. The destination word address of program
memory is formed by concatenating the 8-bit Table Pointer register,
TBLPAG<7:0>, with the effective address specified by Wd. Either direct or
indirect addressing may be used for Ws, and indirect addressing must be
used for Wd.
In Word mode, Ws is stored to the lower 2 bytes of program memory. In
Byte mode, the Least Significant bit of Wd determines the destination byte.
If Wd is not word-aligned, Ws is stored to the second byte of program
memory (PM<15:8>). If Wd is word-aligned, Ws is stored to the first byte of
program memory (PM<7:0>).
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

2

The extension .B in the instruction denotes a byte move rather
than a word move. You may use a .W extension to denote a word
move, but it is not required.

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 347

16-bit MCU and DSC Programmer’s Reference Manual
Example 1:

TBLWTL.B

W0
W1
Program 00 1224
TBLPAG
SR

Before
Instruction
6628
1225
78 0080
0000
0000

Note:

Example 2:

Note:

DS70157D-page 348

; Write W0... (Byte mode)
; to PM Latch Low (TBLPAG:[W1])
; Post-increment W1

W0
W1
Program 01 1224
TBLPAG
SR

After
Instruction
6628
1226
78 2880
0000
0000

Only the Program Latch is written to. The contents of program memory
are not updated until the Flash memory is programmed using the
procedure described in the specific device family reference manual.

TBLWTL

W6
W8
Data 1600
Program 01 7208
TBLPAG
SR

W0, [W1++]

[W6], [W8]

Before
Instruction
1600
7208
0130
09 0002
0001
0000

; Write [W6]... (Word mode)
; to PM Latch Low (TBLPAG:[W8])
; Post-increment W8

W6
W8
Data 1600
Program 01 7208
TBLPAG
SR

After
Instruction
1600
7208
0130
09 0130
0001
0000

Only the Program Latch is written to. The contents of program memory
are not updated until the Flash memory is programmed using the
procedure described in the specific device family reference manual.

© 2009 Microchip Technology Inc.

ULNK

De-allocate Stack Frame

Implemented in:

PIC24F

PIC24H

X

X

Syntax:

{label:}

Operands:

None

Operation:

W14 → W15
(W15) – 2 → W15
(TOS) → W14

Status Affected:

None

Encoding:

1111

dsPIC30F dsPIC33F
X

X

1000

0000

ULNK

1010

0000

0000

Description:

This instruction de-allocates a Stack Frame for a subroutine calling
sequence. The Stack Frame is de-allocated by setting the Stack Pointer
(W15) equal to the Frame Pointer (W14), and then POPping the stack
to reset the Frame Pointer (W14).

Words:

1

Cycles:

1

Example 1:

ULNK

; Unlink the stack frame

Before
Instruction
W14
2002
W15
20A2
Data 2000
2000
SR
0000
Example 2:

ULNK

After
Instruction
W14
2000
W15
2000
Data 2000
2000
SR
0000

; Unlink the stack frame

Before
Instruction
W14
0802
W15
0812
Data 0800
0800
SR
0000

After
Instruction
W14
0800
W15
0800
Data 0800
0800
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 349

16-bit MCU and DSC Programmer’s Reference Manual

XOR

Exclusive OR f and WREG

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

f ∈ [0 ... 8191]

Operation:

(f).XOR.(WREG) → destination designated by D

Status Affected:

N, Z

Encoding:

XOR{.B}

1011

Description:

0110

f

{,WREG}

1BDf

ffff

ffff

ffff

Compute the logical exclusive OR operation of the contents of the
default working register WREG and the contents of the specified file
register and place the result in the destination register. The optional
WREG operand determines the destination register. If WREG is
specified, the result is stored in WREG. If WREG is not specified, the
result is stored in the file register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).
The ‘f’ bits select the address of the file register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: The WREG is set to working register W0.

Words:

1

Cycles:

1

Example 1:

XOR.B

0x1FFF

Before
Instruction
WREG (W0)
7804
Data 1FFE
9439
SR
0000
Example 2:

XOR

After
Instruction
WREG (W0)
7804
Data 1FFE
9039
SR
0008 (N = 1)

0xA04, WREG

Before
Instruction
WREG (W0)
6234
Data 0A04 A053
SR
0000

DS70157D-page 350

; XOR (0x1FFF) and WREG (Byte mode)
; Store result to 0x1FFF

; XOR (0xA04) and WREG (Word mode)
; Store result to WREG

After
Instruction
WREG (W0) C267
Data 0A04 A053
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

XOR

Exclusive OR Literal and Wn

Implemented in:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

Syntax:

{label:}

Operands:

lit10 ∈ [0 ... 255] for byte operation
lit10 ∈ [0 ... 1023] for word operation
Wn ∈ [W0 ... W15]

Operation:

lit10.XOR.(Wn) → Wn

Status Affected:

N, Z

Encoding:

1011

Description:

XOR{.B}

0010

#lit10,

1Bkk

Wn

kkkk

kkkk

dddd

Compute the logical exclusive OR operation of the unsigned 10-bit literal
operand and the contents of the working register Wn and store the result
back in the working register Wn. Register direct addressing must be
used for Wn.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘k’ bits specify the literal operand.
The ‘d’ bits select the address of the working register.
Note 1: The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.
2: For byte operations, the literal must be specified as an unsigned
value [0:255]. See Section 4.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte
mode.

Words:

1

Cycles:

1

Example 1:

XOR.B

#0x23, W0

Before
Instruction
W0
7804
SR
0000
Example 2:

XOR

#0x108, W4

Before
Instruction
W4
6134
SR
0000

; XOR 0x23 and W0 (Byte mode)
; Store result to W0

After
Instruction
W0
7827
SR
0000
; XOR 0x108 and W4 (Word mode)
; Store result to W4

After
Instruction
W4 603C
SR
0000

5
Instruction
Descriptions

© 2009 Microchip Technology Inc.

DS70157D-page 351

16-bit MCU and DSC Programmer’s Reference Manual

XOR

Exclusive OR Wb and Short Literal

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

XOR{.B}

Wb,

#lit5,

Wd
[Wd]
[Wd++]
[Wd--]
[++Wd]
[--Wd]

Operands:

Wb ∈ [W0 ... W15]
lit5 ∈ [0 ... 31]
Wd ∈ [W0 ... W15]

Operation:

(Wb).XOR.lit5 → Wd

Status Affected:

N, Z

Encoding:

0110

Description:

1www

wBqq

qddd

d11k

kkkk

Compute the logical exclusive OR operation of the contents of the base
register Wb and the unsigned 5-bit literal operand and place the result in
the destination register Wd. Register direct addressing must be used for
Wb. Either register direct or indirect addressing may be used for Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘k’ bits provide the literal operand, a 5-bit integer number.
Note:

Words:

1

Cycles:

1

Example 1:

XOR.B

W4, #0x16, W5

Before
Instruction
W4
C822
W5
1200
SR
0000
Example 2:

XOR

; XOR W4 and 0x14 (Byte mode)
; Store result to W5

After
Instruction
W4
C822
W5
1234
SR
0000

W2, #0x1F, [W8++]

Before
Instruction
W2
8505
W8
1004
Data 1004
6628
SR
0000

DS70157D-page 352

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

; XOR W2 by 0x1F (Word mode)
; Store result to [W8]
; Post-increment W8

After
Instruction
W2
8505
W8
1006
Data 1004
851A
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

XOR

Exclusive OR Wb and Ws

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

XOR{.B}

Operands:

Wb ∈ [W0 ... W15]
Ws ∈ [W0 ... W15]
Wd ∈ [W0 ... W15]

Operation:

(Wb).XOR.(Ws) → Wd

Status Affected:

N, Z

Encoding:

0110

Description:

1www

Wb,

wBqq

Ws,

Wd

[Ws],

[Wd]

[Ws++],

[Wd++]

[Ws--],

[Wd--]

[++Ws],

[++Wd]

[--Ws],

[--Wd]

qddd

dppp

ssss

Compute the logical exclusive OR operation of the contents of the source
register Ws and the contents of the base register Wb, and place the
result in the destination register Wd. Register direct addressing must be
used for Wb. Either register direct or indirect addressing may be used for
Ws and Wd.
The ‘w’ bits select the address of the base register.
The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note:

Words:

1

Cycles:

1

Example 1:

XOR.B

W1, [W5++], [W9++]

; XOR W1 and [W5] (Byte mode)
; Store result to [W9]
; Post-increment W5 and W9

After
Instruction
W1 AAAA
W5
2001
W9
2601
Data 2000
115A
Data 2600
00F0
SR
0008 (N = 1)

5
Instruction
Descriptions

Before
Instruction
W1 AAAA
W5
2000
W9
2600
Data 2000
115A
Data 2600
0000
SR
0000

© 2009 Microchip Technology Inc.

The extension .B in the instruction denotes a byte operation
rather than a word operation. You may use a .W extension to
denote a word operation, but it is not required.

DS70157D-page 353

16-bit MCU and DSC Programmer’s Reference Manual
Example 2:

XOR

W1, W5, W9

Before
Instruction
W1 FEDC
W5
1234
W9
A34D
SR
0000

DS70157D-page 354

; XOR W1 and W5 (Word mode)
; Store the result to W9

After
Instruction
W1 FEDC
W5
1234
W9
ECE8
SR
0008 (N = 1)

© 2009 Microchip Technology Inc.

ZE

Zero-Extend Wn

Implemented in:

Syntax:

PIC24F

PIC24H

dsPIC30F

dsPIC33F

X

X

X

X

{label:}

ZE

Ws,

Wnd

[Ws],
[Ws++],
[Ws--],
[++Ws],
[--Ws],
Operands:

Ws ∈ [W0 ... W15]
Wnd ∈ [W0 ... W15]

Operation:

Ws<7:0> → Wnd<7:0>
0 → Wnd<15:8>

Status Affected:

N, Z, C

Encoding:

1111

Description:

1011

10qq

qddd

dppp

ssss

Zero-extend the Least Significant Byte in source working register Ws to
a 16-bit value and store the result in the destination working register
Wnd. Either register direct or indirect addressing may be used for Ws,
and register direct addressing must be used for Wnd. The N flag is
cleared and the C flag is set, because the zero-extended word is always
positive.
The ‘q’ bits select the destination Address mode.
The ‘d’ bits select the destination register.
The ‘p’ bits select the source Address mode.
The ‘s’ bits select the source register.
Note 1: This operation converts a byte to a word, and it uses no .B or
.W extension.
2: The source Ws is addressed as a byte operand, so any
address modification is by ‘1’.

Words:

1

Cycles:

1

Example 1:

ZE

W3, W4

; zero-extend W3
; Store result to W4

Before
Instruction
W3
7839
W4
1005
SR
0000
Example 2:

ZE

[W2++], W12

© 2009 Microchip Technology Inc.

5

; Zero-extend [W2]
; Store to W12
; Post-increment W2

Instruction
Descriptions

Before
Instruction
W2
0900
W12
1002
Data 0900
268F
SR
0000

After
Instruction
W3
7839
W4
0039
SR
0001 (C = 1)

After
Instruction
W2
0901
W12
008F
Data 0900
268F
SR
0001 (C = 1)

DS70157D-page 355

16-bit MCU and DSC Programmer’s Reference Manual
NOTES:

DS70157D-page 356

© 2009 Microchip Technology Inc.

6
Reference

Section 6. Reference
HIGHLIGHTS
This section of the manual contains the following major topics:
6.1
6.2
6.3

Instruction Bit Map ........................................................................................................ 358
Instruction Set Summary Table ..................................................................................... 360
Revision History ............................................................................................................ 367

© 2009 Microchip Technology Inc.

DS70157D-page 357

16-bit MCU and DSC Programmer’s Reference Manual
6.1

INSTRUCTION BIT MAP
Instruction encoding for the 16-bit MCU and DSC family devices is summarized in Table 6-1. This
table contains the encoding for the Most Significant Byte (MSB) of each instruction. The first
column in the table represents bits 23:20 of the opcode, and the first row of the table represents
bits 19:16 of the opcode. The first byte of the opcode is formed by taking the first column bit value
and appending the first row bit value. For instance, the MSB of the PUSH instruction (last row,
ninth column) is encoded with 11111000b (0xF8).
Note:

DS70157D-page 358

The complete opcode for each instruction may be determined by the instruction
descriptions in Section 5. “Instruction Descriptions”, using Table 5-1 through
Table 5-12.

© 2009 Microchip Technology Inc.

Instruction Encoding
Opcode<19:16>
0000

0000

NOP

0001
BRA
CALL
GOTO
RCALL

0010

0011

CALL

—

0100
GOTO

0101
RETLW

0110
RETFIE
RETURN

0111

1000

RCALL

DO(1)

1011

1100

1101

1110

1111

REPEAT

—

—

BRA(1)

BRA(1)

BRA(1)

(OA)

(OB)

(SA)

BRA(1)
(SB)

BRA
(GT)

BRA
(GE)

BRA
(GTU)

—

MOV
BRA
(OV)

BRA
(C)

BRA
(Z)

BRA
(N)

BRA
(LE)

BRA
(LT)

BRA
(LEU)

BRA

BRA (NOV)

BRA
(NC)

BRA
(NZ)

BRA
(NN)

0100

ADD

ADDC

0101

SUB

SUBB

0110

AND

XOR

0111

IOR

MOV
MOV

1000

MOV

1001
1010

BSET

BCLR

BTG

BTST

BTSTS

BTST

BTSS

BTSC

BSET

BCLR

BTG

BTST

BTSTS

BSW

BTSS

BTSC

1011

ADD
ADDC

SUB
SUBB

AND
XOR

IOR
MOV

ADD
ADDC

SUB
SUBB

AND
XOR

IOR
MOV

MUL.US
MUL.UU

MUL.SS
MUL.SU

TBLRDH
TBLRDL

TBLWTH
TBLWTL

MUL

SUB
SUBB

MOV.D

MOV

MOVSAC(1)

SFTAC(1)

ADD(1)

LAC(1)

ADD(1)
NEG(1)
SUB(1)

SAC(1)

SAC.R(1)

—

FF1L(1)
FF1R(1)

MAC(1)
MPY(1)
MPY.N(1)
MSC(1)

1100

CLRAC(1)

MAC(1)
MPY(1)
MPY.N(1)
MSC(1)

SL

ASR
LSR

RLC
RLNC

RRC
RRNC

SL

ASR
LSR

RLC
RLNC

RRC
RRNC

DIV.S
DIV.U

DIVF(2)

—

—

—

SL

ASR
LSR

FBCL

1110

CP0

CP
CPB

CP0

CP
CPB

—

—

CPSGT
CPSLT

CPSEQ
CPSNE

INC
INC2

DEC
DEC2

COM
NEG

CLR
SETM

INC
INC2

DEC
DEC2

COM
NEG

CLR
SETM

—

—

—

—

PUSH

POP

LNK
ULNK

SE
ZE

DISI

DAW
EXCH
SWAP

CLRWDT
PWRSAV
POP.S
PUSH.S
RESET

NOPR

1:

ED(1)
EDAC(1)
MAC(1)
MPY(1)

This instruction is only available in dsPIC30F and dsPIC33F family devices.

DS70157D-page 359

Section 6. Reference

1101

1111

Note

1010

SUBBR

0010
0011

1001

SUBR

0001

Opcode<23:20>

© 2009 Microchip Technology Inc.

Table 6-1:

6

Reference

INSTRUCTION SET SUMMARY TABLE
The complete 16-bit MCU and DSC device instruction set is summarized in Table 6-2. This table contains an alphabetized listing of the
instruction set. It includes instruction assembly syntax, description, size (in 24-bit words), execution time (in instruction cycles), affected
status bits and the page number in which the detailed description can be found. Table 1-2 identifies the symbols that are used in the
Instruction Set Summary Table.

Table 6-2:

Instruction Set Summary Table
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

Page
Number

DC

N

OV

Z

C

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

5-89

ADD

f {,WREG}

Destination = f + WREG

1

1

—

—

—

—

—

—

ADD

#lit10,Wn

Wn = lit10 + Wn

1

1

—

—

—

—

—

—

ADD

Wb,#lit5,Wd

Wd = Wb + lit5

1

1

—

—

—

—

—

—

ADD

Wb,Ws,Wd

Wd = Wb + Ws

1

1

—

—

—

—

—

—

ADD

Acc

(2)

Add accumulators

1

1

Ú
Ú

×
×

—

5-95

1

×
×

—

1

×
×

—

16-bit signed add to accumulator

Ú
Ú

—

Ws,#Slit4,Acc

Ú
Ú

—

ADD

—

—

—

—

—

5-96

ADDC

f {,WREG}

Destination = f + WREG + (C)

1

1

—

—

—

—

—

—

#lit10,Wn

Wn = lit10 + Wn + (C)

1

1

—

—

—

—

—

—

ADDC

Wb,#lit5,Wd

Wd = Wb + lit5 + (C)

1

1

—

—

—

—

—

—

ADDC

Wb,Ws,Wd

Wd = Wb + Ws + (C)

1

1

—

—

—

—

—

—

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

AND

f {,WREG}

Destination = f .AND. WREG

1

1

—

—

—

—

—

—

—

AND

#lit10,Wn

Wn = lit10 .AND. Wn

1

1

—

—

—

—

—

—

—

AND

Wb,#lit5,Wd

Wd = Wb .AND. lit5

1

1

—

—

—

—

—

—

—

AND

Wb,Ws,Wd

Wd = Wb .AND. Ws

1

1

—

—

—

—

—

—

—

ASR

f {,WREG}

Destination = arithmetic right shift f

1

1

—

—

—

—

—

—

—

ASR

Ws,Wd

Wd = arithmetic right shift Ws

1

1

—

—

—

—

—

—

—

—

Ø
Ø
Ø
Ø
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

5-98

ADDC

Ú
Ú
Ú
Ú

5-90
5-91
5-93

© 2009 Microchip Technology Inc.

ASR

Wb,#lit4,Wnd

Wnd = arithmetic right shift Wb by lit4

1

1

—

—

—

—

—

—

—

ASR

Wb,Wns,Wnd

Wnd = arithmetic right shift Wb by Wns

1

1

—

—

—

—

—

—

—

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

BCLR

f,#bit4

Bit clear f

1

1

—

—

—

—

—

—

—

—

—

—

—

5-115

BCLR

Ws,#bit4

Bit clear Ws

1

1

—

—

—

—

—

—

—

—

—

—

—

5-116

BRA

Expr

Branch unconditionally

1

2

—

—

—

—

—

—

—

—

—

—

—

5-117

BRA

Wn

Computed branch

1

2

—

—

—

—

—

—

—

—

—

—

—

5-118

BRA

C,Expr

Branch if Carry

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-119

BRA

GE,Expr

Branch if greater than or equal

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-121

BRA

GEU,Expr

Branch if Carry

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-122

BRA

GT,Expr

Branch if greater than

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-123

BRA

GTU,Expr

Branch if unsigned greater than

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-124

Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

— unchanged

—
—
—
—
—
—
—

5-99
5-100
5-102

—

5-104

—

5-105

—

5-106

—

5-107

Ú
Ú

5-109

—

5-113

—

5-114

5-111

16-bit MCU and DSC Programmer’s Reference Manual

DS70157D-page 360

6.2

Instruction Set Summary Table (Continued)
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

DC

N

OV

Z

C

Page
Number

BRA

LE,Expr

Branch if less than or equal

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-125

BRA

LEU,Expr

Branch if unsigned less than or equal

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-126

BRA

LT,Expr

Branch if less than

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-127

BRA

LTU,Expr

Branch if not Carry

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-128

BRA

N,Expr

Branch if Negative

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-129

BRA

NC,Expr

Branch if not Carry

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-130

BRA

NN,Expr

Branch if not Negative

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-131

BRA

NOV,Expr

Branch if not Overflow

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-132

BRA

NZ,Expr

Branch if not Zero

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-133
5-134

OA,Expr(2)

Branch if Accumulator A overflow

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

OB,Expr(2)

Branch if Accumulator B overflow

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-135

BRA

OV,Expr

Branch if Overflow

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-136

BRA

SA,Expr(2)

Branch if Accumulator A saturated

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-137

BRA

SB,Expr(2)

Branch if Accumulator B saturated

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-138

BRA

Z,Expr

Branch if Zero

1

1 (2)

—

—

—

—

—

—

—

—

—

—

—

5-139

BSET

f,#bit4

Bit set f

1

1

—

—

—

—

—

—

—

—

—

—

—

5-140

BSET

Ws,#bit4

Bit set Ws

1

1

—

—

—

—

—

—

—

—

—

—

—

5-141

BSW.C

Ws,Wb

Write C bit to Ws

1

1

—

—

—

—

—

—

—

—

—

—

—

5-142

BSW.Z

Ws,Wb

Write Z bit to Ws

1

1

—

—

—

—

—

—

—

—

—

—

—

5-142

BTG

f,#bit4

Bit toggle f

1

1

—

—

—

—

—

—

—

—

—

—

—

5-144

BTG

Ws,#bit4

Bit toggle Ws

1

1

—

—

—

—

—

—

—

—

—

—

—

5-145

BTSC

f,#bit4

Bit test f, skip if clear

1

1
(2 or 3)

—

—

—

—

—

—

—

—

—

—

—

5-146

BTSC

Ws,#bit4

Bit test Ws, skip if clear

1

1
(2 or 3)

—

—

—

—

—

—

—

—

—

—

—

5-148

BTSS

f,#bit4

Bit test f, skip if set

1

1
(2 or 3)

—

—

—

—

—

—

—

—

—

—

—

5-150

BTSS

Ws,#bit4

Bit test Ws, skip if set

1

1
(2 or 3)

—

—

—

—

—

—

—

—

—

—

—

5-151

DS70157D-page 361

BTST

f,#bit4

Bit test f

1

1

—

—

—

—

—

—

—

—

—

Ú

—

5-153

BTST.C

Ws,#bit4

Bit test Ws to C

1

1

—

—

—

—

—

—

—

—

—

—

Ú

5-154

BTST.Z

Ws,#bit4

Bit test Ws to Z

1

1

—

—

—

—

—

—

—

—

—

Ú

—

5-154

BTST.C

Ws,Wb

Bit test Ws to C

1

1

—

—

—

—

—

—

—

—

—

—

Ú

5-155

BTST.Z

Ws,Wb

Bit test Ws to Z

1

1

—

—

—

—

—

—

—

—

—

—

5-155

BTSTS

f,#bit4

Bit test then set f

1

1

—

—

—

—

—

—

—

—

—

Ú
Ú

—

5-157

Bit test Ws to C then set

1

1

—

—

—

—

—

—

—

—

—

—

Ú

5-158

BTSTS.C Ws,#bit4
Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

— unchanged

Section 6. Reference

BRA
BRA

6

Reference

© 2009 Microchip Technology Inc.

Table 6-2:

Instruction Set Summary Table (Continued)
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

DC

N

OV

Z

C

Page
Number

BTSTS.Z Ws,#bit4

Bit test Ws to Z then set

1

1

—

—

—

—

—

—

—

—

—

Ú

—

5-158

CALL

Expr

Call subroutine

2

2

—

—

—

—

—

—

—

—

—

—

—

5-159

CALL

Wn

Call indirect subroutine

1

2

—

—

—

—

—

—

—

—

—

—

—

5-161

CLR

f

f = 0x0000

1

1

—

—

—

—

—

—

—

—

—

—

—

5-163

CLR

WREG

WREG = 0x0000

1

1

—

—

—

—

—

—

—

—

—

—

—

5-163

CLR

Wd

Wd = 0

1

1

—

—

—

—

—

—

—

—

—

—

—

5-164

CLR

Acc,Wx,Wxd,Wy,Wyd,AWB(2)

Clear accumulator

1

1

0

0

0

0

0

0

—

—

—

—

—

5-165

Clear Watchdog Timer

1

1

—

—

—

—

—

—

—

—

—

—

—

5-167

1

1

—

—

—

—

—

—

—

—

—

5-168

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ø
Ø
Ø

CLRWDT

© 2009 Microchip Technology Inc.

COM

f {,WREG}

Destination = f

COM

Ws,Wd

Wd = Ws

1

1

—

—

—

—

—

—

—

CP

f

Compare (f – WREG)

1

1

—

—

—

—

—

—

CP

Wb,#lit5

Compare (Wb – lit5)

1

1

—

—

—

—

—

—

CP

Wb,Ws

Compare (Wb – Ws)

1

1

—

—

—

—

—

—

Ú
Ú
Ú

CP0

f

Compare (f – 0x0000)

1

1

—

—

—

—

—

—

1

CP0

Ws

Compare (Ws – 0x0000)

1

1

—

—

—

—

—

—

1

CPB

f

Compare with borrow (f – WREG – C)

1

1

—

—

—

—

—

—

CPB

Wb,#lit5

Compare with borrow (Wb – lit5 – C)

1

1

—

—

—

—

—

—

CPB

Wb,Ws

Compare with borrow (Wb – Ws – C)

1

1

—

—

—

—

—

—

Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

CPSEQ

Wb, Wn

Compare (Wb with Wn), skip if =

1

1
(2 or 3)

—

—

—

—

—

—

—

—

—

CPSGT

Wb, Wn

Signed Compare (Wb with Wn), skip if >

1

1
(2 or 3)

—

—

—

—

—

—

—

—

CPSLT

Wb, Wn

Signed Compare (Wb with Wn), skip if <

1

1
(2 or 3)

—

—

—

—

—

—

—

CPSNE

Wb, Wn

Signed Compare (Wb with Wn), skip if ≠

1

1
(2 or 3)

—

—

—

—

—

—

DAW.B

Wn

Wn = decimal adjust Wn

1

1

—

—

—

—

—

DEC

f {,WREG}

Destination = f – 1

1

1

—

—

—

—

—

DEC

Ws,Wd

Wd = Ws – 1

1

1

—

—

—

—

—

—

DEC2

f {,WREG}

Destination = f – 2

1

1

—

—

—

—

—

—

DEC2

Ws,Wd

Wd = Ws – 2

1

1

—

—

—

—

—

DISI

#lit14

Disable interrupts for lit14 instruction cycles

1

1

—

—

—

—

DIV.S

Wm, Wn

Signed 16/16-bit integer divide

1

18

—

—

—

DIV.SD

Wm, Wn

Signed 32/16-bit integer divide

1

18

—

—

—

Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

—

5-169

Ú
Ú
Ú

5-170

1

5-173

1

5-174

Ú
Ú
Ú

5-175

—

—

5-179

—

—

—

5-180

—

—

—

—

5-181

—

—

—

—

—

5-182

—

—

—

—

—

—

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú

5-183

—

—

—

—

—

—

—

—

5-188

—

—

—

—

—

—

—

Ú
Ú

Ú
Ú

Ú
Ú

5-189

—

Ú
Ú

— unchanged

—

5-171
5-172

5-176
5-177

5-184
5-185
5-186
5-187

5-189

16-bit MCU and DSC Programmer’s Reference Manual

DS70157D-page 362

Table 6-2:

Instruction Set Summary Table (Continued)
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

DC

OV

Z

C

Ú
Ú
Ú

5-191

5-195

DIV.U

Wm, Wn

Unsigned 16/16-bit integer divide

1

18

—

—

—

—

—

—

—

0

0

DIV.UD

Wm, Wn

Unsigned 32/16-bit integer divide

1

18

—

—

—

—

—

—

—

0

DIVF

Wm, Wn(2)

Signed 16/16-bit fractional divide

1

18

—

—

—

—

—

—

—

Ú

Ú
Ú

Ú
Ú
Ú

(2)

Page
Number

N

5-191
5-193

DO

#lit14, Expr

Do code to PC + Expr, (lit14 + 1) times

2

2

—

—

—

—

—

—

—

—

—

—

—

DO

Wn, Expr(2)

Do code to PC + Expr, (Wn + 1) times

2

2

—

—

—

—

—

—

—

—

—

—

—

5-197

ED

Wm*Wm,Acc,Wx,Wy,Wxd(2)

Euclidean distance (no accumulate)

1

1

×
×

5-199

1

Ú
Ú

—

1

×
×

—

Euclidean distance

×
×

—

Wm*Wm,Acc,Wx,Wy,Wxd(2)

Ú
Ú

—

EDAC

Ú
Ú

—
—

—

—

—

—

5-201

EXCH

Wns,Wnd

Swap Wns and Wnd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-203

FBCL

Ws,Wnd

Find bit change from left (MSb) side

1

1

—

—

—

—

—

—

—

—

—

—

5-204

FF1L

Ws,Wnd

Find first one from left (MSb) side

1

1

—

—

—

—

—

—

—

—

—

—

FF1R

Ws,Wnd

Find first one from right (LSb) side

1

1

—

—

—

—

—

—

—

—

—

—

Ú
Ú
Ú

GOTO

Expr

Go to address

2

2

—

—

—

—

—

—

—

—

—

—

—

5-210

GOTO

Wn

Go to address indirectly

1

2

—

—

—

—

—

—

—

—

—

—

—

5-211

INC

f {,WREG}

Destination = f + 1

1

1

—

—

—

—

—

—

Ws,Wd

Wd = Ws + 1

1

1

—

—

—

—

—

—

INC2

f {,WREG}

Destination = f + 2

1

1

—

—

—

—

—

—

INC2

Ws,Wd

Wd = Ws + 2

1

1

—

—

—

—

—

—

Ú
Ú
Ú
Ú

f {,WREG}

Destination = f .IOR. WREG

1

1

—

—

—

—

—

—

—

—

5-216

IOR

#lit10,Wn

Wn = lit10 .IOR. Wn

1

1

—

—

—

—

—

—

—

—

5-217

IOR

Wb,#lit5,Wd

Wd = Wb .IOR. lit5

1

1

—

—

—

—

—

—

—

—

5-218

IOR

Wb,Ws,Wd

Wd = Wb .IOR. Ws

1

1

—

—

—

—

—

—

—

—

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

IOR

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

5-212

INC

Ú
Ú
Ú
Ú

—

5-219
5-221

(2)

—
—
—

5-206
5-208

5-213
5-214
5-215

Ws,#Slit4, Acc

Load accumulator

1

1

Ú

Ú

×

×

Ú

×

—

—

—

—

—

LNK

#lit14

Link Frame Pointer

1

1

—

—

—

—

—

—

—

—

—

—

—

5-223

LSR

f {,WREG}

Destination = logical right shift f

1

1

—

—

—

—

—

—

—

0

—

Ws,Wd

Wd = logical right shift Ws

1

1

—

—

—

—

—

—

—

0

—

Ú
Ú

5-224

LSR
LSR

Wb,#lit4,Wnd

Wnd = logical right shift Wb by lit4

1

1

—

—

—

—

—

—

—

—

5-227

LSR

Wb,Wns,Wnd

Wnd = logical right shift Wb by Wns

1

1

—

—

—

—

—

—

—

Ú
Ú

—
—

Ú
Ú
Ú
Ú

—

5-228

(2)

5-225

DS70157D-page 363

MAC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB

Multiply and accumulate

1

1

Ú
Ú

×
×

—

5-229

1

×
×

—

1

×
×

—

Square and accumulate

Ú
Ú

—

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(2)

Ú
Ú

—

MAC

—

—

—

—

—

5-231

MOV

f {,WREG}

Move f to destination

1

1

—

—

—

—

—

—

—

Ú

—

Ú

—

5-233

MOV

WREG,f

Move WREG to f

1

1

—

—

—

—

—

—

—

—

—

—

—

5-234

MOV

f,Wnd

Move f to Wnd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-235

Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

— unchanged

Section 6. Reference

LAC

6

Reference

© 2009 Microchip Technology Inc.

Table 6-2:

Instruction Set Summary Table (Continued)
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

DC

N

OV

Z

C

Page
Number
5-236

MOV

Wns,f

Move Wns to f

1

1

—

—

—

—

—

—

—

—

—

—

—

MOV.B

#lit8,Wnd

Move 8-bit unsigned literal to Wnd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-237

MOV

#lit16,Wnd

Move 16-bit literal to Wnd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-238

MOV

[Ws+Slit10],Wnd

Move [Ws + Slit10] to Wnd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-239

MOV

Wns,[Wd+Slit10]

Move Wns to [Wd + Slit10]

1

1

—

—

—

—

—

—

—

—

—

—

—

5-240

MOV

Ws,Wd

Move Ws to Wd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-241

MOV.D

Wns,Wnd

Move double Wns to Wnd:Wnd + 1

1

2

—

—

—

—

—

—

—

—

—

—

—

5-243

MOV.D

Wns,Wnd

Move double Wns:Wns + 1 to Wnd

1

2

—

—

—

—

—

—

—

—

—

—

—

5-243

MOVSAC

Acc,Wx,Wxd,Wy,Wyd,AWB(2)

Move [Wx] to Wxd, and [Wy] to Wyd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-245

MPY

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(2)

Multiply Wn by Wm to accumulator

1

1

×
×

—

5-247

1

Ú
Ú

—

1

×
×

—

Square to accumulator

×
×

—

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(2)

Ú
Ú

—

MPY

Ú
Ú

—

—

—

—

—

5-249

MPY.N

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(2)

-(Multiply Wn by Wm) to accumulator

1

1

0

0

—

—

0

—

—

—

—

—

—

5-251

MSC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(2)

Multiply and subtract from accumulator

1

1

Ú

Ú

×

×

Ú

×

—

—

—

—

—

5-253

MUL

f

W3:W2 = f * WREG

1

1

—

—

—

—

—

—

—

—

—

—

—

5-255

MUL.SS

Wb,Ws,Wnd

{Wnd + 1,Wnd} = signed(Wb) * signed(Ws)

1

1

—

—

—

—

—

—

—

—

—

—

—

5-256

MUL.SU

Wb,#lit5,Wnd

{Wnd + 1,Wnd} = signed(Wb) * unsigned(lit5)

1

1

—

—

—

—

—

—

—

—

—

—

—

5-258

MUL.SU

Wb,Ws,Wnd

{Wnd + 1,Wnd} = signed(Wb) * unsigned(Ws)

1

1

—

—

—

—

—

—

—

—

—

—

—

5-260

MUL.US

Wb,Ws,Wnd

{Wnd + 1,Wnd} = unsigned(Wb) * signed(Ws)

1

1

—

—

—

—

—

—

—

—

—

—

—

5-262

MUL.UU

Wb,#lit5,Wnd

{Wnd + 1,Wnd} = unsigned(Wb) * unsigned(lit5)

1

1

—

—

—

—

—

—

—

—

—

—

—

5-264

MUL.UU

Wb,Ws,Wnd

{Wnd + 1,Wnd} = unsigned(Wb) * unsigned(Ws)

1

1

—

—

—

—

—

—

—

—

—

—

—

5-265

NEG

f {,WREG}

Destination = f + 1

1

1

—

—

—

—

—

—

Ws,Wd

Wd = Ws + 1

1

1

—

—

—

—

—

—

Ú
Ú

Ú
Ú

Ú
Ú

Ú
Ú

5-267

NEG

Ú
Ú

NEG

Acc(2)

Negate accumulator

1

1

Ú

Ú

×

×

Ú

×

—

—

—

—

—

5-269

No operation

1

1

—

—

—

—

—

—

—

—

—

—

—

5-270
5-271

NOP

5-268

No operation

1

1

—

—

—

—

—

—

—

—

—

—

—

POP

f

POP TOS to f

1

1

—

—

—

—

—

—

—

—

—

—

—

5-272

POP

Wd

POP TOS to Wd

1

1

—

—

—

—

—

—

—

—

—

—

—

5-273

POP.D

Wnd

POP double from TOS to Wnd:Wnd + 1

1

2

—

—

—

—

—

—

—

—

—

—

—

5-274

POP shadow registers

1

1

—

—

—

—

—

—

Ú

Ú

Ú

Ú

Ú

5-275

NOPR

© 2009 Microchip Technology Inc.

POP.S
PUSH

f

PUSH f to TOS

1

1

—

—

—

—

—

—

—

—

—

—

—

5-276

PUSH

Ws

PUSH Ws to TOS

1

1

—

—

—

—

—

—

—

—

—

—

—

5-277

PUSH.D

Wns

PUSH double Wns:Wns + 1 to TOS

1

2

—

—

—

—

—

—

—

—

—

—

—

5-278

PUSH shadow registers

1

1

—

—

—

—

—

—

—

—

—

—

—

5-279

—

—

—

—

—

—

—

—

5-280

—

—

—

—

—

—

—

—

5-281

PUSH.S
PWRSAV

#lit1

Enter Power-saving mode

1

1

—

—

—

RCALL

Expr

Relative call

1

2

—

—

—

Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

— unchanged

16-bit MCU and DSC Programmer’s Reference Manual

DS70157D-page 364

Table 6-2:

Instruction Set Summary Table (Continued)
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

DC

N

OV

Z

C

Page
Number

RCALL

Wn

Computed call

1

2

—

—

—

—

—

—

—

—

—

—

—

5-283

REPEAT

#lit14

Repeat next instruction (lit14 + 1) times

1

1

—

—

—

—

—

—

—

—

—

—

—

5-285

REPEAT

Wn

5-286

Repeat next instruction (Wn + 1) times

1

1

—

—

—

—

—

—

—

—

—

—

—

RESET

Software device Reset

1

1

—

—

—

—

—

—

—

—

—

—

—

5-288

RETFIE

Return from interrupt enable

1

3 (2)

—

—

—

—

—

—

—

Ú

Ú

Ú

Ú

5-290

Return with lit10 in Wn

1

3 (2)

—

—

—

—

—

—

—

—

—

—

—

5-291

Return from subroutine

1

3 (2)

—

—

—

—

—

—

—

—

—

—

—

5-292

f {,WREG}

Destination = rotate left through Carry f

1

1

—

—

—

—

—

—

—

—

Ws,Wd

Wd = rotate left through Carry Ws

1

1

—

—

—

—

—

—

—

Ú
Ú

RLNC

f {,WREG}

Destination = rotate left (no Carry) f

1

1

—

—

—

—

—

—

—

—

5-296

RLNC

Ws,Wd

Wd = rotate left (no Carry) Ws

1

1

—

—

—

—

—

—

—

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

5-293

RLC

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

—

5-297

Ú
Ú

5-299

—

5-302

—

5-303

RETLW

#lit10,Wn

RETURN
RLC

RRC

f {,WREG}

Destination = rotate right through Carry f

1

1

—

—

—

—

—

—

—

RRC

Ws,Wd

Wd = rotate right through Carry Ws

1

1

—

—

—

—

—

—

—

RRNC

f {,WREG}

Destination = rotate right (no Carry) f

1

1

—

—

—

—

—

—

—

RRNC

Ws,Wd

Wd = rotate right (no Carry) Ws

1

1

—

—

—

—

—

—

—

(2)

—
—
—
—
—
—
—

5-294

5-300

Acc,#Slit4,Wd

Store accumulator

1

1

—

—

—

—

—

—

—

—

—

—

—

5-305

Acc,#Slit4,Wd(2)

Store rounded Accumulator

1

1

—

—

—

—

—

—

—

—

—

—

—

5-307

SE

Ws,Wd

Wd = sign-extended Ws

1

1

—

—

—

—

—

—

—

Ú

—

Ú

Ú

5-309

SETM

f

f = 0xFFFF

1

1

—

—

—

—

—

—

—

—

—

—

—

5-310

SETM

WREG

WREG = 0xFFFF

1

1

—

—

—

—

—

—

—

—

—

—

—

5-310

SETM

Ws

Ws = 0xFFFF

1

1

—

—

—

—

—

—

—

—

—

—

—

5-311

SFTAC

Acc,#Slit6(2)

Arithmetic shift accumulator by Slit6

1

1

×
×

—

5-312

1

Ú
Ú

—

1

×
×

—

Arithmetic shift accumulator by (Wb)

×
×

—

Acc,Wb(2)

Ú
Ú

—

SFTAC

Ú
Ú

—

—

—

—

—

5-313

SL

f {,WREG}

Destination = arithmetic left shift f

1

1

—

—

—

—

—

—

—

Ws,Wd

Wd = arithmetic left shift Ws

1

1

—

—

—

—

—

—

—

Ú
Ú

SL

Wb,#lit4,Wnd

Wnd = left shift Wb by lit4

1

1

—

—

—

—

—

—

—

—

5-317

SL

Wb,Wns,Wnd

Wnd = left shift Wb by Wns

1

1

—

—

—

—

—

—

—

SUB

f {,WREG}

Destination = f – WREG

1

1

—

—

—

—

—

—

SUB

#lit10,Wn

Wn = Wn – lit10

1

1

—

—

—

—

—

—

SUB

Wb,#lit5,Wd

Wd = Wb – lit5

1

1

—

—

—

—

—

—

SUB

Wb,Ws,Wd

Wd = Wb – Ws

1

1

—

—

—

—

—

—

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

5-314

SL

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

—

SUB

Acc(2)

Subtract accumulators

1

1

Ú

Ú

×

×

Ú

×

—

—

—

—

Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

—
—
—

5-315

—

5-318

Ú
Ú
Ú
Ú

5-319

—

5-324

5-320
5-321
5-322

— unchanged

Section 6. Reference

DS70157D-page 365

SAC
SAC.R

6

Reference

© 2009 Microchip Technology Inc.

Table 6-2:

Instruction Set Summary Table (Continued)
Assembly Syntax
Mnemonic, Operands

Description

Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) SAB(1,2)

SUBB

f {,WREG}

Destination = f – WREG – (C)

1

1

—

—

—

—

—

—

SUBB

#lit10,Wn

Wn = Wn – lit10 – (C)

1

1

—

—

—

—

—

—

SUBB

Wb,#lit5,Wd

Wd = Wb – lit5 – (C)

1

1

—

—

—

—

—

—

SUBB

Wb,Ws,Wd

Wd = Wb – Ws – (C)

1

1

—

—

—

—

—

—

SUBBR

f {,WREG}

Destination = WREG – f – (C)

1

1

—

—

—

—

—

—

SUBBR

Wb,#lit5,Wd

Wd = lit5 – Wb – (C)

1

1

—

—

—

—

—

—

SUBBR

Wb,Ws,Wd

Wd = Ws – Wb – (C)

1

1

—

—

—

—

—

—

SUBR

f {,WREG}

Destination = WREG – f

1

1

—

—

—

—

—

—

SUBR

Wb,#lit5,Wd

Wd = lit5 – Wb

1

1

—

—

—

—

—

—

SUBR

Wb,Ws,Wd

Wd = Ws – Wb

1

1

—

—

—

—

—

—

DC

N

OV

Z

C

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

Ø
Ø
Ø
Ø
Ø
Ø
Ø
Ú
Ú
Ú

Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú
Ú

Page
Number
5-325
5-326
5-327
5-329
5-331
5-332
5-334
5-336
5-337
5-338

SWAP

Wn

Wn = byte or nibble swap Wn

1

1

—

—

—

—

—

—

—

—

—

—

—

5-340

TBLRDH

Ws,Wd

Read high program word to Wd

1

2

—

—

—

—

—

—

—

—

—

—

—

5-341

TBLRDL

Ws,Wd

Read low program word to Wd

1

2

—

—

—

—

—

—

—

—

—

—

—

5-343

TBLWTH

Ws,Wd

Write Ws to high program word

1

2

—

—

—

—

—

—

—

—

—

—

—

5-345

TBLWTL

Ws,Wd

Write Ws to low program word

1

2

—

—

—

—

—

—

—

—

—

—

—

5-347

Unlink Frame Pointer

1

1

—

—

—

—

—

—

—

—

—

—

—

5-349

XOR

f {,WREG}

Destination = f .XOR. WREG

1

1

—

—

—

—

—

—

—

—

5-350

#lit10,Wn

Wn = lit10 .XOR. Wn

1

1

—

—

—

—

—

—

—

—

5-351

XOR

Wb,#lit5,Wd

Wd = Wb .XOR. lit5

1

1

—

—

—

—

—

—

—

—

5-352

XOR

Wb,Ws,Wd

Wd = Wb .XOR. Ws

1

1

—

—

—

—

—

—

—

ZE

Ws,Wnd

Wnd = zero-extended Ws

1

1

—

—

—

—

—

—

—

0

—

Ú
Ú
Ú
Ú
Ú

—

XOR

Ú
Ú
Ú
Ú

ULNK

Legend:
Note 1:
2:

Ú set or cleared; Ø may be cleared, but never set; × may be set, but never cleared; ‘1’ always set; ‘0’ always cleared;
SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.
This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

— unchanged

—
—
—

—

5-353

1

5-355

© 2009 Microchip Technology Inc.

16-bit MCU and DSC Programmer’s Reference Manual

DS70157D-page 366

Table 6-2:

Section 6. Reference
6.3

6

REVISION HISTORY
This is the initial released version of this document.

Revision B
This revision incorporates all known errata at the time of this document update.

Revision C (February 2008)
This revision includes the following corrections and updates:
• Instruction Updates:
- Updated BRA Instruction (see “BRA”)
- Updated DIVF Instruction (see “DIVF”)
- Updated DO Instruction (see “DO”)
- Updated SUB instruction (see “SUB”)

Revision D (November 2009)
This revision includes the following corrections and updates:
• Document renamed from dsPIC30F/33F Programmer’s Reference Manual to 16-bit MCU
and DSC Programmer’s Reference Manual
• Document has been completely redesigned to accommodate all current 16-bit families:
dsPIC30F, dsPIC33F, PIC24F and PIC24H

© 2009 Microchip Technology Inc.

DS70157D-page 367

Reference

Revision A

16-bit MCU and DSC Programmer’s Reference Manual
NOTES:

DS70157D-page 368

© 2009 Microchip Technology Inc.

Index
INDEX
A
Accumulator A, Accumulator B ........................................... 18
Accumulator Access ........................................................... 73
Accumulator Usage............................................................. 72
Addressing Modes for Wd Destination Register ................. 85
Addressing Modes for Ws Source Register ........................ 85
Assigned Working Register Usage ..................................... 67

B
Byte Operations .................................................................. 54

C

D
Data Addressing Mode Tree ............................................... 49
Data Addressing Modes...................................................... 42
DCOUNT Register .............................................................. 19
Default Working Register (WREG) ............................... 17, 68
Development Support ........................................................... 6
DOEND Register................................................................. 19
DOSTART Register ............................................................ 19
DSP Accumulator Instructions ............................................ 78
DSP Data Formats .............................................................. 70
DSP MAC Indirect Addressing Modes ................................ 47
DSP MAC Instructions ........................................................ 74
dsPIC30F/33F Overview ..................................................... 12

F
File Register Addressing ..................................................... 42

I
Immediate Addressing ........................................................ 48
Operands in the Instruction Set .................................. 48
Implied DSP Operands ....................................................... 67

© 2009 Microchip Technology Inc.

DS70157D-page 369

Index

Code Examples
’Z’ Status bit Operation for 32-bit Addition .................. 66
Base MAC Syntax....................................................... 75
File Register Addressing............................................. 43
File Register Addressing and WREG.......................... 43
Frame Pointer Usage.................................................. 63
Illegal Word Move Operations..................................... 58
Immediate Addressing ................................................ 49
Indirect Addressing with Effective Address Update .... 45
Indirect Addressing with Register Offset..................... 46
Legal Word Move Operations ..................................... 57
MAC Accumulator WB Syntax .................................... 77
MAC Prefetch Syntax.................................................. 76
Move with Literal Offset Instructions ........................... 46
MSC Instruction with Two Prefetches and Accumulator
Write Back .......................................................... 77
Normalizing with FBCL ............................................... 81
Register Direct Addressing ......................................... 44
Sample Byte Math Operations .................................... 55
Sample Byte Move Operations ................................... 54
Scaling with FBCL....................................................... 80
Stack Pointer Usage ................................................... 61
Unsigned f and WREG Multiply (Legacy MULWF Instruction) ..................................................................... 69
Using 10-bit Literals for Byte Operands ...................... 59
Using the Default Working Register WREG................ 68
Conditional Branch Instructions .......................................... 65
Core Control Register ......................................................... 21

Implied Frame and Stack Pointer ....................................... 67
Instruction Bit Map ............................................................ 358
Instruction Description Example ......................................... 88
Instruction Descriptions ...................................................... 89
ADD (16-bit Signed Add to Accumulator) ................... 96
ADD (Add Accumulators) ........................................... 95
ADD (Add f to WREG) ................................................ 89
ADD (Add Literal to Wn) ............................................. 90
ADD (Add Wb to Short Literal) ................................... 91
ADD (Add Wb to Ws).................................................. 93
ADDC (Add f to WREG with Carry) ............................ 98
ADDC (Add Literal to Wn with Carry) ......................... 99
ADDC (Add Wb to Short Literal with Carry).............. 100
ADDC (Add Wb to Ws with Carry)............................ 102
AND (AND f and WREG).......................................... 104
AND (AND Literal and Wd)....................................... 105
AND (AND Wb and Short Literal) ............................. 106
AND (AND Wb and Ws) ........................................... 107
ASR (Arithmetic Shift Right by Short Literal) ............ 113
ASR (Arithmetic Shift Right by Wns) ........................ 114
ASR (Arithmetic Shift Right f) ................................... 109
ASR (Arithmetic Shift Right Ws) ............................... 111
BCLR (Bit Clear in Ws)............................................. 116
BCLR.B (Bit Clear f) ................................................. 115
BRA (Branch Unconditionally) .................................. 117
BRA (Computed Branch).......................................... 118
BRA C (Branch if Carry) ........................................... 119
BRA GE (Branch if Signed Greater Than or Equal) . 121
BRA GEU (Branch if Unsigned Greater Than or Equal).
122
BRA GT (Branch if Signed Greater Than) ................ 123
BRA GTU (Branch if Unsigned Greater Than) ......... 124
BRA LE (Branch if Signed Less Than or Equal)....... 125
BRA LEU (Branch if Unsigned Less Than or Equal) 126
BRA LT (Branch if Signed Less Than) ..................... 127
BRA LTU (Branch if Not Carry) ................................ 130
BRA LTU (Branch if Unsigned Less Than)............... 128
BRA N (Branch if Negative)...................................... 129
BRA NN (Branch if Not Negative)............................. 131
BRA NOV (Branch if Not Overflow) .......................... 132
BRA NZ (Branch if Not Zero).................................... 133
BRA OA (Branch if Overflow Accumulator A)........... 134
BRA OB (Branch if Overflow Accumulator B)........... 135
BRA OV (Branch if Overflow) ................................... 136
BRA SA (Branch if Saturation Accumulator A) ......... 137
BRA SB (Branch if Saturation Accumulator B) ......... 138
BRA Z (Branch if Zero) ............................................. 139
BSET (Bit Set f) ........................................................ 140
BSET (Bit Set in Ws) ................................................ 141
BSW (Bit Write in Ws) .............................................. 142
BTG (Bit Toggle f)..................................................... 144
BTG (Bit Toggle in Ws)............................................. 145
BTSC (Bit Test f, Skip if Clear) ................................. 146
BTSC (Bit Test Ws, Skip if Clear)............................. 148
BTSS (Bit Test f, Skip if Set) .................................... 150
BTSS (Bit Test Ws, Skip if Set) ................................ 151
BTST (Bit Test f)....................................................... 153
BTST (Bit Test in Ws)....................................... 154, 155
BTSTS (Bit Test/Set f) .............................................. 157
BTSTS (Bit Test/Set in Ws) ...................................... 158
CALL (Call Indirect Subroutine)................................ 161
CALL (Call Subroutine)............................................. 159
CLR (Clear Accumulator, Prefetch Operands) ......... 165
CLR (Clear f or WREG) ............................................ 163
CLR (Clear Wd) ........................................................ 164

16-bit MCU and DSC Programmer’s Reference Manual
CLRWDT (Clear Watchdog Timer) ........................... 167
COM (Complement f) ................................................ 168
COM (Complement Ws)............................................ 169
CP (Compare f with WREG, Set Status Flags) ......... 170
CP (Compare Wb with lit5, Set Status Flags) ........... 171
CP (Compare Wb with Ws, Set Status Flags) .......... 172
CP0 (Compare f with 0x0, Set Status Flags) ............ 173
CP0 (Compare Ws with 0x0, Set Status Flags) ........ 174
CPB (Compare f with WREG using Borrow, Set Status
Flags) ................................................................ 175
CPB (Compare Wb with lit5 using Borrow, Set Status
Flags) ................................................................ 176
CPB (Compare Ws with Wb using Borrow, Set Status
Flags) ................................................................ 177
CPSEQ (Compare Wb with Wn, Skip if Equal) ......... 179
CPSGT (Signed Compare Wb with Wn, Skip if Greater
Than)................................................................. 180
CPSLT (Signed Compare Wb with Wn, Skip if Less
Than)................................................................. 181
CPSNE (Signed Compare Wb with Wn, Skip if Not
Equal)................................................................ 182
DAW.B (Decimal Adjust Wn) .................................... 183
DEC (Decrement f) ................................................... 184
DEC (Decrement Ws) ............................................... 185
DEC2 (Decrement f by 2).......................................... 186
DEC2 (Decrement Ws by 2) ..................................... 187
DISI (Disable Interrupts Temporarily) ....................... 188
DIV.S (Signed Integer Divide) ................................... 189
DIV.U (Unsigned Integer Divide)............................... 191
DIVF (Fractional Divide)............................................ 193
DO (Initialize Hardware Loop Literal) ........................ 195
DO (Initialize Hardware Loop Wn) ............................ 197
ED (Euclidean Distance, No Accumulate) ................ 199
EDAC (Euclidean Distance) ...................................... 201
EXCH (Exchange Wns and Wnd) ............................. 203
FBCL (Find First Bit Change from Left) .................... 204
FF1L (Find First One from Left) ................................ 206
FF1R (Find First One from Right) ............................. 208
GOTO (Unconditional Indirect Jump)........................ 211
GOTO (Unconditional Jump) .................................... 210
INC (Increment f) ...................................................... 212
INC (Increment Ws) .................................................. 213
INC2 (Increment f by 2)............................................. 214
INC2 (Increment Ws by 2) ........................................ 215
IOR (Inclusive OR f and WREG)............................... 216
IOR (Inclusive OR Literal and Wn)............................ 217
IOR (Inclusive OR Wb and Short Literal) .................. 218
IOR (Inclusive OR Wb and Ws) ................................ 219
LAC (Load Accumulator)........................................... 221
LNK (Allocate Stack Frame) ..................................... 223
LSR (Logical Shift Right by Short Literal) ................. 227
LSR (Logical Shift Right by Wns).............................. 228
LSR (Logical Shift Right f)......................................... 224
LSR (Logical Shift Right Ws) .................................... 225
MAC (Multiply and Accumulate)................................ 229
MAC (Square and Accumulate) ................................ 231
MOV (Move 16-bit Literal to Wn) .............................. 238
MOV (Move f to Destination)..................................... 233
MOV (Move f to Wnd) ............................................... 235
MOV (Move Wns to [Wd with offset]) ........................ 240
MOV (Move Wns to f) ............................................... 236
MOV (Move WREG to f) ........................................... 234
MOV (Move Ws to Wd) ............................................. 241
MOV (Move Ws with offset to Wnd) .......................... 239
MOV.B (Move 8-bit Literal to Wnd) ........................... 237
MOV.D (Double-Word Move from Source to Wnd) ... 243

DS70157D-page 370

MOVSAC (Prefetch Operands and Store Accumulator) .
245
MPY (Multiply Wm by Wn to Accumulator)............... 247
MPY (Square to Accumulator) .................................. 249
MPY.N (Multiply -Wm by Wn to Accumulator) .......... 251
MSC (Multiply and Subtract from Accumulator)........ 253
MUL (Integer Unsigned Multiply f and WREG) ......... 255
MUL.SS (Integer 16x16-bit Signed Multiply)............. 256
MUL.SU (Integer 16x16-bit Signed-Unsigned Multiply) ..
260
MUL.SU (Integer 16x16-bit Signed-Unsigned Short Literal Multiply) ........................................................ 258
MUL.US (Integer 16x16-bit Unsigned-Signed Multiply) ..
262
MUL.UU (Integer 16x16-bit Unsigned Multiply) ........ 265
MUL.UU (Integer 16x16-bit Unsigned Short Literal Multiply).................................................................... 264
NEG (Negate Accumulator) ...................................... 269
NEG (Negate f) ......................................................... 267
NEG (Negate Ws)..................................................... 268
NOP (No Operation) ................................................. 270
NOPR (No Operation)............................................... 271
POP (Pop TOS to f) .................................................. 272
POP (Pop TOS to Wd).............................................. 273
POP.D (Double Pop TOS to Wnd/
Wnd+1) ............................................................. 274
POP.S (Pop Shadow Registers)............................... 275
PUSH (Push f to TOS).............................................. 276
PUSH (Push Ws to TOS).......................................... 277
PUSH.D (Double Push Wns/
Wns+1 to TOS)................................................. 278
PUSH.S (Push Shadow Registers)........................... 279
PWRSAV (Enter Power Saving Mode) ..................... 280
RCALL (Computed Relative Call) ............................. 283
RCALL (Relative Call)............................................... 281
REPEAT (Repeat Next Instruction ’lit14’ Times) ...... 285
REPEAT (Repeat Next Instruction Wn Times) ......... 286
RESET (Reset) ......................................................... 288
RETFIE (Return from Interrupt) ................................ 290
RETLW (Return with Literal in Wn)........................... 291
RETURN (Return)..................................................... 292
RLC (Rotate Left f through Carry)............................. 293
RLC (Rotate Left Ws through Carry) ........................ 294
RLNC (Rotate Left f without Carry)........................... 296
RLNC (Rotate Left Ws without Carry)....................... 297
RRC (Rotate Right f through Carry).......................... 299
RRC (Rotate Right Ws through Carry) ..................... 300
RRNC (Rotate Right f without Carry)........................ 302
RRNC (Rotate Right Ws without Carry).................... 303
SAC (Store Accumulator) ......................................... 305
SAC.R (Store Rounded Accumulator) ...................... 307
SE (Sign-Extend Ws)................................................ 309
SETM (Set f or WREG)............................................. 310
SETM (Set Ws)......................................................... 311
SFTAC (Arithmetic Shift Accumulator by Slit5)......... 312
SFTAC (Arithmetic Shift Accumulator by Wb) .......... 313
SL (Shift Left by Short Literal)................................... 317
SL (Shift Left by Wns)............................................... 318
SL (Shift Left f).......................................................... 314
SL (Shift Left Ws)...................................................... 315
SUB (Subtract Accumulators)................................... 324
SUB (Subtract Literal from Wn) ................................ 320
SUB (Subtract Short Literal from Wb)....................... 321
SUB (Subtract WREG from f) ................................... 319
SUB (Subtract Ws from Wb)..................................... 322
SUBB (Subtract Short Literal from Wb with Borrow) 327
SUBB (Subtract Wn from Literal with Borrow) .......... 326

© 2009 Microchip Technology Inc.

Index

© 2009 Microchip Technology Inc.

WREG .......................................................................... 8
Ws ................................................................................ 8
Wx ................................................................................ 8
Wxd .............................................................................. 8
Wy ................................................................................ 8
Wyd .............................................................................. 8
Instruction Stalls ................................................................. 52
DO/REPEAT Loops .................................................... 53
Exceptions .................................................................. 53
Instructions that Change Program Flow ..................... 53
PSV ............................................................................ 53
RAW Dependency Detection...................................... 52
Instruction Symbols ............................................................ 84
Integer and Fractional Data ................................................ 70
Representation ........................................................... 71
Interrupt Priority Level......................................................... 21
Introduction ........................................................................... 6

M
MAC
Operations .................................................................. 75
Prefetch Register Updates ......................................... 74
Prefetches .................................................................. 74
Syntax......................................................................... 75
Write Back .................................................................. 75
MAC Accumulator Write Back Selection............................. 87
MAC or MPY Source Operands (Different Working Register)
87
MAC or MPY Source Operands (Same Working Register) 87
Manual Objective .................................................................. 6
Modulo and Bit-Reversed Addressing Modes .................... 47
Multi-Cycle Instructions....................................................... 31
Multi-Word Instructions ....................................................... 31

N
Normalizing the Accumulator with the FBCL Instruction..... 81

O
Offset Addressing Modes for Wd Destination Register (with
Register Offset) .......................................................... 85
Offset Addressing Modes for Ws Source Register (with Register Offset) ................................................................. 85

P
PIC® Microcontroller Compatibility ..................................... 68
PRODH
PRODL Register Pair ................................................. 68
Program Addressing Modes ............................................... 51
Methods of Modifying Flow......................................... 51
Program Counter ................................................................ 18
Programmer’s Model .......................................................... 14
Diagram ...................................................................... 15
Register Descriptions ................................................. 16
PSVPAG Register............................................................... 18

DS70157D-page 371

Index

SUBB (Subtract WREG and Carry bit from f) ........... 325
SUBB (Subtract Ws from Wb with Borrow)............... 329
SUBBR (Subtract f from WREG with Borrow)........... 331
SUBBR (Subtract Wb from Short Literal with Borrow) ....
332
SUBBR (Subtract Wb from Ws with Borrow) ............ 334
SUBR (Subtract f from WREG)................................. 336
SUBR (Subtract Wb from Short Literal) .................... 337
SUBR (Subtract Wb from Ws) .................................. 338
SWAP (Byte or Nibble Swap Wn) ............................. 340
TBLRDH (Table Read High) ..................................... 341
TBLRDL (Table Read Low)....................................... 343
TBLWTH (Table Write High) ..................................... 345
TBLWTL (Table Write Low) ...................................... 347
ULNK (De-allocate Stack Frame) ............................. 349
XOR (Exclusive OR f and WREG) ............................ 350
XOR (Exclusive OR Literal and Wn) ......................... 351
XOR (Exclusive OR Wb and Short Literal) ............... 352
XOR (Exclusive OR Wb and Ws).............................. 353
ZE (Zero-Extend Wn)................................................ 355
Instruction Encoding Field Descriptors Introduction............ 84
Instruction Set Overview ..................................................... 30
Bit Instructions ............................................................ 36
Compare/Skip Instructions.......................................... 37
Control Instructions ..................................................... 39
DSP Instructions ......................................................... 39
dsPIC30F/33F Instruction Groups .............................. 30
Logic Instructions ........................................................ 34
Math Instructions......................................................... 32
Move Instructions........................................................ 32
Program Flow Instructions .......................................... 38
Rotate/Shift Instructions.............................................. 35
Shadow/Stack Instructions.......................................... 39
Instruction Set Summary Table......................................... 360
Instruction Set Symbols ........................................................ 8
(text).............................................................................. 8
[text] .............................................................................. 8
{ }................................................................................... 8
{label:} ........................................................................... 8
#text .............................................................................. 8
............................................................................ 8
Acc ................................................................................ 8
AWB.............................................................................. 8
bit4 ................................................................................ 8
Expr............................................................................... 8
f ..................................................................................... 8
lit1 ................................................................................. 8
lit10 ............................................................................... 8
lit14 ............................................................................... 8
lit16 ............................................................................... 8
lit23 ............................................................................... 8
lit4 ................................................................................. 8
lit5 ................................................................................. 8
lit8 ................................................................................. 8
Slit10 ............................................................................. 8
Slit16 ............................................................................. 8
Slit4 ............................................................................... 8
Slit5 ............................................................................... 8
TOS............................................................................... 8
Wb................................................................................. 8
Wd................................................................................. 8
Wm, Wn ........................................................................ 8
Wm*Wm........................................................................ 8
Wm*Wn......................................................................... 8
Wn................................................................................. 8
Wnd............................................................................... 8
Wns............................................................................... 8

16-bit MCU and DSC Programmer’s Reference Manual
R

T

RCOUNT Register .............................................................. 19
Register Direct Addressing ................................................. 43
Register Indirect Addressing ............................................... 44
Modes ......................................................................... 44
Register Indirect Addressing and the Instruction Set .......... 47
Registers
CORCON (Core Control) Register ........................ 26, 27
SR (CPU Status) ......................................................... 23
SR (Status) Register ................................................... 24
Related Documents............................................................... 9

TBLPAG Register ............................................................... 18
Third Party Documentation ................................................... 9

S
Scaling Data with the FBCL Instruction............................... 79
Scaling Examples ....................................................... 79
Shadow Registers ............................................................... 22
Automatic Usage......................................................... 22
Software Stack Frame Pointer ...................................... 18, 62
Example ...................................................................... 63
Overflow ...................................................................... 64
Underflow .................................................................... 64
Software Stack Pointer.................................................. 18, 60
Example ...................................................................... 61
Stack Pointer Limit Register (SPLIM).................................. 18
Status Register.................................................................... 19
DSP ALU Status Bits .................................................. 20
Loop Status Bits .......................................................... 20
MCU ALU Status Bits.................................................. 19
Style and Symbol Conventions ............................................. 7
Document Conventions................................................. 7

DS70157D-page 372

U
Using 10-bit Literal Operands ............................................. 59
10-bit Literal Coding.................................................... 59

W
Word Move Operations....................................................... 56
Data Alignment in Memory ......................................... 56
Working Register Array....................................................... 17

X
X Data Space Prefetch Destination .................................... 86
X Data Space Prefetch Operation ...................................... 86

Y
Y Data Space Prefetch Destination .................................... 87
Y Data Space Prefetch Operation ...................................... 86

Z
Z Status Bit ......................................................................... 66

© 2009 Microchip Technology Inc.

Index
NOTES:

Index

© 2009 Microchip Technology Inc.

DS70157D-page 373

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DS70157D-page 374

© 2009 Microchip Technology Inc.
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