PIC32 FRM Section 8. Interrupts Family Reference Manual, Sect. 08

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Section 8. Interrupts
HIGHLIGHTS
This section of the manual contains the following topics:
Introduction................................................................................................................ 8-2
Control Registers ....................................................................................................... 8-3
Operation................................................................................................................... 8-9
Single Vector Mode ................................................................................................. 8-11
Multi-Vector Mode.................................................................................................... 8-12
Interrupt Vector Address Calculation ....................................................................... 8-13
Interrupt Priorities .................................................................................................... 8-14
Interrupts and Register Sets .................................................................................... 8-15
Interrupt Processing ................................................................................................ 8-16
External Interrupts ................................................................................................... 8-20
Temporal Proximity Interrupt Coalescing ................................................................. 8-21
Effects of Interrupts After Reset............................................................................... 8-22
Operation in Power-Saving and Debug Modes ....................................................... 8-22
Related Application Notes ....................................................................................... 8-23
Revision History....................................................................................................... 8-24

DS61108F-page 8-1

8
Interrupts

8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15

PIC32 Family Reference Manual
Note:

This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “Interrupt Controller” chapter in
the current device data sheet to check whether this document supports the device
you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com

8.1

INTRODUCTION
The PIC32 generates interrupt requests in response to interrupt events from peripheral modules.
The Interrupt module exists external to the CPU logic and prioritizes the interrupt events before
presenting them to the CPU.
The PIC32 Interrupts module includes the following features:
•
•
•
•
•
•
•
•

Up to 96 interrupt sources
Up to 64 interrupt vectors
Single and Multi-Vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Seven user-selectable priority levels for each vector
Four user-selectable subpriority levels within each priority
User-configurable shadow set based on priority level. (This feature is not available on all
devices; refer to the specific device data sheet for availability.)
• Software can generate any interrupt
• User-configurable Interrupt Vector Table (IVT) location
• User-configurable interrupt vector spacing
Figure 8-1 shows the block diagram of the Interrupt Controller module.

Interrupt Requests

Figure 8-1:

Interrupt Controller Module

Vector Number

Interrupt Controller

CPU Core

Priority Level

Shadow Set Number

Note:

Several of the registers cited in this section are not in the Interrupt Controller
module. These registers (and bits) are associated with the CPU. Refer to Section
2. “CPU” (DS61113) for more details.
To avoid confusion, a typographic distinction is made for registers in the CPU. The
register names in this section, and all other sections of this manual, are signified by
uppercase letters only (except for cases in which variables are used). CPU register
names are signified by upper and lowercase letters. For example, INTSTAT is an
Interrupts register; whereas, IntCtl is a CPU register.

DS61108F-page 8-2

Section 8. Interrupts
8.2

CONTROL REGISTERS
Note:

Each PIC32 device variant may have one or more Interrupt sources, and depending
on the device variant, the number of sources may be different. An ‘x’ used in the
names of control/status bits and registers denotes that there are multiple registers,
which have the same function, that can define these interrupt sources. Refer to the
specific device data sheet for more details.

The Interrupts module consists of the following Special Function Registers (SFRs):
•
•
•
•
•
•

INTCON: Interrupt Control Register
INTSTAT: Interrupt Status Register
IPTMR: Interrupt Proximity Timer Register
IFSx: Interrupt Flag Status Register(1)
IECx: Interrupt Enable Control Register(1)
IPCx: Interrupt Priority Control Register(1)

Table 8-1 summarizes all Interrupts-related registers. Corresponding registers appear after the
summary, followed by a detailed description of each register.
Table 8-1:

Interrupts Register Summary
Bit
Range

Name
INTCON(1,2,3)

IPTMR(1,2,3)

Bit
30/22/14/6

Bit
29/21/13/5

Bit
28/20/12/4

Bit
27/19/11/3

Bit
26/18/10/2

Bit
25/17/9/1

31:24

—

23:16

—

SS0

15:8

—

MVEC

—

7:0

—

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

31:24

—

23:16

—

15:8

—

7:0

—

31:24

IPTMR<31:24>

23:16

IPTMR<23:16>

15:8

IPTMR<15:8>

IECx(1,2,3)

IPCx(1,2,3)

Legend:
Note 1:

SRIPL<2:0>

IPTMR<7:0>

31:24

IFS31

IFS30

IFS29

IFS28

IFS27

IFS26

IFS25

IFS24

23:16

IFS23

IFS22

IFS21

IFS20

IFS19

IFS18

IFS17

IFS16

15:8

IFS15

IFS14

IFS13

IFS12

IFS11

IFS10

IFS09

IFS08

7:0

IFS07

IFS06

IFS05

IFS04

IFS03

IFS02

IFS01

IFS00

31:24

IEC31

IEC30

IEC29

IEC28

IEC27

IEC26

IEC25

IEC24

23:16

IEC23

IEC22

IEC21

IEC20

IEC19

IEC18

IEC17

IEC16

15:8

IEC15

IEC14

IEC13

IEC12

IEC11

IEC10

IEC09

IEC08

7:0

IEC07

IEC06

IEC05

IEC04

IEC03

IEC02

IEC01

IEC00

31:24

—

IP03<2:0>

IS03<1:0>

23:16

—

IP02<2:0>

IS02<1:0>

15:8

—

IP01<2:0>

IS01<1:0>

7:0

—

IP00<2:0>

IS00<1:0>

— = unimplemented, read as ‘0’.
This register has an associated Clear register at an offset of 0x4 bytes. These registers have the same name with CLR appended to the
end of the register name (e.g., INTCONCLR). Writing a ‘1’ to any bit position in the Clear register will clear valid bits in the associated
register. Reads from the Clear register should be ignored.
This register has an associated Set register at an offset of 0x8 bytes. These registers have the same name with SET appended to the
end of the register name (e.g., INTCONSET). Writing a ‘1’ to any bit position in the Set register will set valid bits in the associated register.
Reads from the Set register should be ignored.
This register has an associated Invert register at an offset of 0xC bytes. These registers have the same name with INV appended to the
end of the register name (e.g., INTCONINV). Writing a ‘1’ to any bit position in the Invert register will invert valid bits in the associated
register. Reads from the Invert register should be ignored.

TPC<2:0>

VEC<5:0>

7:0
IFSx(1,2,3)

Bit
24/16/8/0

DS61108F-page 8-3

Interrupts

INTSTAT(1,2,3)

Bit
31/23/15/7

PIC32 Family Reference Manual
Register 8-1:
INTCON: Interrupt Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0

Bit
26/18/10/2

Bit
25/17/9/1

Bit
24/16/8/0
U-0

U-0

—

U-0

R/W-0

—

SS0

U-0

R/W-0

U-0

R/W-0

—

MVEC

—

U-0

R/W-0

—

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR:(‘0’, ‘1’, x = Unknown)

U = Unimplemented bit

TPC<2:0>

P = Programmable bit

bit 31-17 Unimplemented: Read as ‘0’
bit 16
SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
bit 15-13 Unimplemented: Read as ‘0’
bit 12
MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode
bit 11
Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer‘
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3
INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2
INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1
INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0
INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge

DS61108F-page 8-4

Section 8. Interrupts
Register 8-2:
INTSTAT: Interrupt Status Register
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0

Bit
26/18/10/2

Bit
25/17/9/1

Bit
24/16/8/0
U-0

U-0

—

U-0

—

U-0

R-0

—

U-0

R-0

—

SRIPL<2:0>(1)
R-0

R-0

VEC<5:0>(1)

Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR:(‘0’, ‘1’, x = Unknown)

U = Unimplemented bit

P = Programmable bit

bit 31-11 Unimplemented: Read as ‘0’
bit 10-8 SRIPL<2:0>: Requested Priority Level bits for Single Vector Mode bits(1)
000-111 = The priority level of the latest interrupt presented to the CPU
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
VEC<5:0>: Interrupt Vector bits(1)
00000-11111 = The interrupt vector that is presented to the CPU
This value should only be used when the interrupt controller is configured for Single Vector mode.

Register 8-3:
IPTMR: Interrupt Proximity Timer Register
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0

R/W-0

Bit
25/17/9/1

Bit
24/16/8/0

R/W-0

IPTMR<31:24>
R/W-0

R/W-0

IPTMR<23:16>
R/W-0

R/W-0

IPTMR<15:8>
R/W-0

R/W-0

IPTMR<7:0>

Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR:(‘0’, ‘1’, x = Unknown)
bit 31-0

R/W-0

Bit
26/18/10/2

U = Unimplemented bit

P = Programmable bit

IPTMR<31:0>: Interrupt Proximity Timer Reload bits
Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity Timer is
triggered by an interrupt event.

DS61108F-page 8-5

Interrupts

Note 1:

PIC32 Family Reference Manual
Register 8-4:
IFSx: Interrupt Flag Status Register(1)
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0

Bit
26/18/10/2

Bit
25/17/9/1

Bit
24/16/8/0

R/W-0

IFS31

IFS30

IFS29

IFS28

IFS27

IFS26

IFS25

IFS24

R/W-0

IFS23

IFS22

IFS21

IFS20

IFS19

IFS18

IFS17

IFS16

R/W-0

IFS15

IFS14

IFS13

IFS12

IFS11

IFS10

IFS09

IFS08

R/W-0

IFS07

IFS06

IFS05

IFS04

IFS03

IFS02

IFS01

IFS00

Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR:(‘0’, ‘1’, x = Unknown)

U = Unimplemented bit

P = Programmable bit

bit 31-0

IFS31-IFS00: Interrupt Flag Status bits
1 = Interrupt request has occurred
0 = No interrupt request has occurred

Note 1:

This register represents a generic definition of the IFSx register. Refer to the “Interrupts” chapter in the
specific device data sheet to learn exact bit definitions.

Register 8-5:
IECx: Interrupt Enable Control Register(1)
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0

Bit
26/18/10/2

Bit
25/17/9/1

Bit
24/16/8/0

R/W-0

IEC31

IEC30

IEC29

IEC28

IEC27

IEC26

IEC25

IEC24

R/W-0

IEC23

IEC22

IEC21

IEC20

IEC19

IEC18

IEC17

IEC16

R/W-0

IEC15

IEC14

IEC13

IEC12

IEC11

IEC10

IEC09

IEC08

R/W-0

IEC07

IEC06

IEC05

IEC04

IEC03

IEC02

IEC01

IEC00

Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR:(‘0’, ‘1’, x = Unknown)

U = Unimplemented bit

P = Programmable bit

bit 31-0

IEC31-IEC00: Interrupt Enable Control bits
1 = Interrupt is enabled
0 = Interrupt is disabled

Note 1:

This register represents a generic definition of the IFSx register. Refer to the “Interrupts” chapter in the
specific device data sheet to learn exact bit definitions.

DS61108F-page 8-6

Section 8. Interrupts
Register 8-6:
IPCx: Interrupt Priority Control Register(1)
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0

U-0

—

U-0

—

U-0

—

U-0

—

Legend:
R = Readable bit
W = Writable bit
-n = Bit Value at POR:(‘0’, ‘1’, x = Unknown)

R/W-0

Bit
26/18/10/2

Bit
25/17/9/1

Bit
24/16/8/0

R/W-0

IP03<2:0>
R/W-0

R/W-0

IS03<1:0>
R/W-0

IP02<2:0>
R/W-0

R/W-0

IP00<2:0>

U = Unimplemented bit

R/W-0

IS02<1:0>
R/W-0

IP01<2:0>
R/W-0

R/W-0

IS01<1:0>
R/W-0

R/W-0

IS00<1:0>

P = Programmable bit

bit 31-29 Unimplemented: Read as ‘0’
bit 28-26 IP03<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
110 = Interrupt priority is 6
101 = Interrupt priority is 5
100 = Interrupt priority is 4
011 = Interrupt priority is 3
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS03<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpiority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP02<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
110 = Interrupt priority is 6
101 = Interrupt priority is 5
100 = Interrupt priority is 4
011 = Interrupt priority is 3
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS02<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 15-13 Unimplemented: Read as ‘0’

Interrupts

Note 1:

This register represents a generic definition of the IPCx register. Refer to the “Interrupts” chapter in the
specific device data sheet to learn exact bit definitions.

DS61108F-page 8-7

PIC32 Family Reference Manual
Register 8-6:
IPCx: Interrupt Priority Control Register(1) (Continued)
bit 12-10 IP01<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
110 = Interrupt priority is 6
101 = Interrupt priority is 5
100 = Interrupt priority is 4
011 = Interrupt priority is 3
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 9-8
IS01<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
bit 7-5
Unimplemented: Read as ‘0’
bit 4-2
IP00<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
110 = Interrupt priority is 6
101 = Interrupt priority is 5
100 = Interrupt priority is 4
011 = Interrupt priority is 3
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 1-0
IS00<1:0>: Interrupt Subpriority bits
11 = Interrupt subpriority is 3
10 = Interrupt subpriority is 2
01 = Interrupt subpriority is 1
00 = Interrupt subpriority is 0
Note 1:

This register represents a generic definition of the IPCx register. Refer to the “Interrupts” chapter in the
specific device data sheet to learn exact bit definitions.

DS61108F-page 8-8

Section 8. Interrupts
8.3

OPERATION
The interrupt controller is responsible for preprocessing an Interrupt Request (IRQ) from a
number of on-chip peripherals and presenting them in the appropriate order to the processor.
Figure 8-2 depicts the interrupt process within the PIC32 device. The interrupt controller is
designed to receive up to 96 IRQs from the processor core, on-chip peripherals capable of
generating interrupts, and five external inputs. All IRQs are sampled on the rising edge of the
SYSCLK and latched in associated IFSx registers. A pending IRQ is indicated by the flag bit
being equal to ‘1’ in an IFSx register. The pending IRQ will not cause further processing if the
corresponding IECx bit in the Interrupt Enable register is clear. The IECx bits act to mask the
interrupt flag. If the interrupt is enabled, all IRQs are encoded into a 6 bit wide vector number.
The 6-bit vector results in 0 to 63 unique interrupt vector numbers. Since there are more IRQs
than available vector numbers, some IRQs share common vector numbers. Each vector number
is assigned an interrupt-priority-level and a shadow-set number. The priority level is determined
by the IPCx register setting of associated vector. In Multi-Vector mode, the user can select a priority level to receive a dedicated shadow register set. In Single Vector mode, all interrupts may
receive a dedicated shadow set. The interrupt controller selects the highest priority IRQ among
all pending IRQs and presents the associated vector number, priority-level and shadow-set
number to the processor core.

The INTSTAT register contains the VEC<5:0> (INTSTAT<5:0>) and SRIPL<2:0> bits
(INTSTAT<10:8>) of the current pending interrupt. This may not be the same as the interrupt that
caused the core to diverge from normal execution.
The processor returns to the previous state when the Exception Return (ERET) instruction is
executed. ERET clears the EXL bit, restores the Program Counter, and reverts the current
shadow set to the previous one.
The PIC32 interrupt controller can be configured to operate in one of following modes:
• Single Vector mode – all interrupt requests will be serviced at one vector address (mode
out of reset)
• Multi-Vector mode – interrupt requests will be serviced at the calculated vector address

Notes: Reconfiguring the Interrupt Controller module from Vector to Multi-Vector mode (or
vice-versa), during run-time, is strongly discouraged. Changing interrupt controller
modes after initialization may result in an undefined behavior.
The M4K® processor core supports several different interrupt processing modes.
The interrupt controller is designed to work in External Interrupt Controller mode.

DS61108F-page 8-9

8
Interrupts

The processor core samples the presented vector information between the “E” and “M” stages
of the pipeline. If the vector’s priority level presented to the core is greater than the current priority
indicated by the CPU Interrupt Priority bits, IPL<2:0> (Status<12:10>), the interrupt is serviced;
otherwise, it will remain pending until the current priority is less than the interrupt’s priority. When
servicing an interrupt, the processor core pushes the Program Counter into the Exception Program Counter (EPC) register in the CPU and sets the Exception Level (EXL) bit (Status<1>) in
the CPU. The EXL bit disables further interrupts until the application explicitly re-enables them
by clearing the EXL bit. Next, it branches to the vector address calculated from the presented
vector number.

PIC32 Family Reference Manual
Figure 8-2:

Interrupt Process
LATCH

COMPARE

RIPL
>
IPL

StatusIPL

ENCODE

GENERATE

Any Request

•

Interrupt Request

StatusIE

Shadow Set Number

Note 1:

IntCtlVS

Offset
Generator

Requested IPL

CauseRIPL

Vector Number

SRSCtlEICSS

Interrupt Module

Interrupt Sources

Interrupt Exception
Load
Fields

Exception Vector Offset

Shadow Set Number

The SRSCtl, Cause, Status and IntCtl registers are CPU registers and are described in Section 2. “CPU”
(DS61113) of the “PIC32 Family Reference Manual”.

DS61108F-page 8-10

Section 8. Interrupts
8.4

SINGLE VECTOR MODE
On any form of reset, the interrupt controller initializes to Single Vector mode. When the MVEC
bit (INTCON<12>) is ‘0’, the interrupt controller operates in Single Vector mode. In this mode, the
CPU always vectors to the same address.
Note:

Users familiar with the MIPS32® architecture must note that the M4K® core in PIC32
devices is still operating in External Interrupt Controller (EIC) mode. The PIC32
device achieves Single Vector mode by forcing all IRQs to use a vector number of
0x00. Because the M4K core always operates in EIC mode, the single vector
behavior through “Interrupt Compatibility mode” as defined by the MIPS32
architecture is not recommended.

To configure the CPU in PIC32 Single Vector mode, the following CPU registers (IntCtl, Cause
and Status) and the INTCON register must be configured as follows:
•
•
•
•
•
•
•
Example 8-1:
/*

EBase ≠ 00000
VS<4:0> bits (IntCtl<9:5>) ≠ 00000
IV bit (Cause<23>) = 1
EXL bit (Status<1>) = 0
BEV bit (Status<22>) = 0
MVEC bit (INTCON<12>) = 0
IE bit (Status<0>) = 1

Single Vector Mode Initialization

Set the CP0 registers for single-vector interrupt
Place EBASE at 0xBD000000

*/
unsigned int temp_CP0;

// Temporary register for CP0 reg storing

asm volatile("di");

// Disable all interrupts

temp_CP0 = _CP0_GET_STATUS();
temp_CP0 |= 0x00400000;
_CP0_SET_STATUS(temp_CP0);

// Get Status
// Set the BEV bit
// Update Status

_CP0_SET_EBASE(0xBD000000);
_CP0_SET_INTCTL(0x00000020);

// Set an EBase value of 0xBD000000
// Set the Vector Spacing of 32 bytes

temp_CP0 = _CP0_GET_CAUSE();
temp_CP0 |= 0x00800000;
_CP0_SET_CAUSE(temp_CP0);

// Get Cause
// Set IV
// Update Cause

temp_CP0 = _CP0_GET_STATUS();
temp_CP0 &= 0xFFBFFFFD;
_CP0_SET_STATUS(temp_CP0);

// Get Status
// Clear BEV and EXL
// Update Status

INTCONCLR = 0x800;

// Clear the MVEC bit

asm volatile("ei");

// Enable all interrupts

DS61108F-page 8-11

Interrupts

This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly

PIC32 Family Reference Manual
8.5

MULTI-VECTOR MODE
When the MVEC bit (INTCON<12>) is ‘1’, the interrupt controller operates in Multi-Vector mode.
In this mode, the CPU vectors to the unique address for each vector number. Each vector is
located at a specific offset, with respect to a base address specified by the Exception Base
(EBase) register in the CPU. The individual vector address offset is determined by the vector
space that is specified by the VS<4:0> bits (IntCtl<9:5>). The EBase and IntCtl registers are CPU
registers. For more information on the CPU registers, refer to Section 2. “CPU” (DS61113).
To configure the CPU in PIC32 Multi-Vector mode, the following CPU registers (IntCtl, Cause and
Status) and the INTCON register must be configured as follows:
•
•
•
•
•
•
•

Example 8-2:
/*

EBase ≠ 00000
VS<4:0> bits (IntCtl<9:5>) ≠ 00000
IV bit (Cause<23>) = 1
EXL bit (Status<1>) = 0
BEV bit (Status<22>) = 0
MVEC bit (INTCON<12>) = 1
IE bit (Status<0>) = 1

Multi-Vector Mode Initialization

Set the CP0 registers for multi-vector interrupt
Place EBASE at 0xBD000000
This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly
*/
unsigned int temp_CP0;

// Temporary register for CP0 reg storing

asm volatile("di");

// Disable all interrupts

temp_CP0 = _CP0_GET_STATUS();
temp_CP0 |= 0x00400000;
_CP0_SET_STATUS(temp_CP0);

// Get Status
// Set the BEV bit
// Update Status

_CP0_SET_EBASE(0xBD000000);
_CP0_SET_INTCTL(0x00000020);

// Set an EBase value of 0xBD000000
// Set the Vector Spacing of 32 bytes

temp_CP0 = _CP0_GET_CAUSE();
temp_CP0 |= 0x00800000;
_CP0_SET_CAUSE(temp_CP0);

// Get Cause
// Set IV
// Update Cause

temp_CP0 = _CP0_GET_STATUS();
temp_CP0 &= 0xFFBFFFFD;
_CP0_SET_STATUS(temp_CP0);

// Get Status
// Clear BEV and EXL
// Update Status

INTCONSET = 0x800;

// Set the MVEC bit

asm volatile("ei");

// Enable all interrupts

DS61108F-page 8-12

Section 8. Interrupts
8.6

INTERRUPT VECTOR ADDRESS CALCULATION
The vector address for a particular interrupt depends on how the interrupt controller is
configured. If the interrupt controller is configured for Single Vector mode (see 8.4 “Single Vector Mode”), all interrupt vectors use the same vector address. When it is configured for
Multi-Vector mode (see 8.5 “Multi-Vector Mode”), each interrupt vector has a unique vector
address.
On all forms of Reset, the processor enters in Bootstrap mode with the BEV control bit
(Status<22>) set. While the processor is in Bootstrap mode, all interrupts are disabled and all
general exceptions are redirected to one interrupt vector address, 0xBFC00380. When
configuring the interrupt controller to the desired mode of operation, several registers must
be set to specific values (see 8.4 “Single Vector Mode” and 8.5 “Multi-Vector Mode”)
before the BEV bit is cleared. For more information on the Status and EBase registers, refer
to Section 2. “CPU” (DS61113)
The vector address of a given interrupt is calculated using the Exception Base register
(EBase<31:12>) , which provides a 4 KB page-aligned base address value located in the kernel
segment (KSEG) address space.

8.6.1

Multi-Vector Mode Address Calculation

The Multi-Vector mode address is calculated by using the EBase and VS (IntCtl<9:5>) values.
The IntCtl and Status registers are located in the CPU. The VS bits provide the spacing between
adjacent vector addresses. Allowable vector spacing values are 32, 64, 128, 256 and 512 bytes.
Modifications to EBase and VS values are only allowed when the BEV bit (Status<22>) is ‘1’ in
the CPU. Example 8-3 shows how a multi-vector address is calculated for a given vector.
Note:

Example 8-3:

Vector Address for Vector Number 16

vector address = vector number X (VS << 5) + 0x200 + vector base.
Exception Base is 0xBD000000
Vector Spacing(VS) is 2, which is 64(0x40)
vector address(T4) = 0x10 X 0x40 + 0x200 + 0xBD000000
vector address(T4) = 0xBD000600

8.6.2

Single Vector Mode Address Calculation

The Single Vector mode address is calculated by using the EBase<17:0> bits (EBase<29:12>).
In Single Vector mode, the interrupt controller always presents a vector number of ‘0’. The exact
formula for Single Vector mode is as follows:
Equation 8-1:

Single Vector Mode Address Calculation
Single Vector Address = EBase + 0x200

DS61108F-page 8-13

Interrupts

The Multi-Vector mode address calculation depends on the interrupt vector number.
Each PIC32 device family may have its own set of vector numbers depending on its
feature set. For vector numbers associated with each interrupt source, refer to the
specific device data sheet.

PIC32 Family Reference Manual
8.7

INTERRUPT PRIORITIES
8.7.1

Interrupt Group Priority

The user is able to assign a group priority to each of the interrupt vectors. The group priority level
bits are located in the IPCx register. Each IPCx register contains group priority bits for four
interrupt vectors. The user-selectable priority levels range from 1 (the lowest priority) to 7 (the
highest). If an interrupt priority is set to zero, the interrupt vector is disabled for both interrupt and
wake-up purposes. Interrupt vectors with a higher priority level preempt lower priority interrupts.
The user must move the RIPL<2:0> bits (Cause<12:10>) into the IPL<2:0> bits (Status<12:10>)
before re-enabling interrupts. For more information on the Cause and Status registers, refer to
Section 2. “CPU” (DS61113). This action will disable all lower priority interrupts until the
completion of the Interrupt Service Routine (ISR).
Note:

The Interrupt Service Routine must clear the associated interrupt flag in the IFSx
register before lowering the interrupt priority level to avoid recursive interrupts.

Example 8-4:

Setting Group Priority Level

/*
The following code example will set the priority to level 2.
Multi-Vector initialization must be performed (See Example 8-2)
*/
IPC0CLR = 0x0000001C;
// clear the priority level
IPC0SET = 0x00000008;
// set priority level to 2

8.7.2

Interrupt Subpriority

The user can assign a subpriority level within each group priority. The subpriority will not cause
preemption of an interrupt in the same priority; rather, if two interrupts with the same priority are
pending, the interrupt with the highest subpriority will be handled first. The subpriority bits are
located in the IPCx register. Each IPCx register contains subpriority bits for four of the interrupt
vectors. These bits define the subpriority within the priority level of the vector. The
user-selectable subpriority levels range from 0 (the lowest subpriority) to 3 (the highest).
Example 8-5:
/*

Setting Subpriority Level

The following code example will set the subpriority to level 2.
Multi-Vector initialization must be performed (See Example 8-2)
*/
IPC0CLR = 0x00000003;
IPC0SET = 0x00000002;

8.7.3

// clear the subpriority level
// set the subpriority to 2

Interrupt Natural Priority

When multiple interrupts are assigned to same group priority and subpriority, they are prioritized
by their natural priority. The natural priority is a fixed priority scheme, where the highest natural
priority starts at the lowest interrupt vector, meaning that interrupt vector 0 is the highest and
interrupt vector 63 is the lowest natural priority. See the Interrupt Vector Table (IVT) in the specific
device data sheet to learn the natural priority order of each IRQ.

DS61108F-page 8-14

Section 8. Interrupts
8.8

INTERRUPTS AND REGISTER SETS
The PIC32 family of devices employs two register sets, a primary register set for normal program
execution and a shadow register set for highest priority interrupt processing. Register set
selection is automatically performed by the interrupt controller. The exact method of register set
selection varies by the interrupt controller modes of operation.
In Single Vector and Multi-Vector modes of operation, the CSS bit in the SRSCtl register provides
the current number of the register set in use, while the PSS bit provides the number of the previous register set. The SRSCtl register is a CPU register, refer to Section 2. “CPU” (DS61113)
for details. This information is useful to determine if the Stack and Global Data Pointers should
be copied to the new register set, or not. If the current and previous register set are different, the
interrupt handler prologue may need to copy the Stack and Global Data Pointers from one set to
another. Most C compilers supporting the PIC32 family of devices automatically generate the
necessary interrupt prologue code to handle this operation.

8.8.1

In Single Vector mode, the SS0 bit (INTCON<16>) determines which register set will be used. If
the SS0 bit is ‘1’, the interrupt controller will instruct the CPU to use the second register set for
all interrupts. If the SS0 bit is ‘0’, the interrupt controller will instruct the CPU to use the first register set. Unlike Multi-Vector mode, there is no linkage between register set and interrupt priority.
The application decides whether the second shadow set will be used at all.

8.8.2

DS61108F-page 8-15

8
Interrupts

When a priority level interrupt matches a shadow set priority, the interrupt controller instructs the
CPU to use the shadow set. For all other interrupt priorities, the interrupt controller instructs the
CPU to use the primary register set. The interrupt priority that uses the shadow set will not need
to perform any context save and restore. This results in increased code throughput and
decreases interrupt latency.

PIC32 Family Reference Manual
8.9

INTERRUPT PROCESSING
When the priority of a requested interrupt is greater than the current CPU priority, the interrupt
request is taken and the CPU branches to the vector address associated with the requested
interrupt. Depending on the priority of the interrupt, the prologue and epilogue of the interrupt
handler must perform certain tasks before executing any useful code. Example 8-1 and
Example 8-2 provide recommended prologues and epilogues.

8.9.1

Interrupt Processing in Single Vector Mode

When the interrupt controller is configured in Single Vector mode, all of the interrupt requests are
serviced at the same vector address. The interrupt handler routine must generate a prologue and
an epilogue to properly configure, save and restore all of the core registers, along with General
Purpose Registers. At a worst case, all of the modifiable General Purpose Registers must be
saved and restored by the prologue and the epilogue.

8.9.1.1

SINGLE VECTOR MODE PROLOGUE

When entering the interrupt handler routine, the interrupt controller must first save the current
priority and exception PC counter from IPL<2:0> bits (Status<12:10>) and the ErrorEPC register,
respectively, on the stack. If the routine is presented a new register set, the previous register set’s
stack register must be copied to the current set’s stack register. Then the requested priority may
be stored in the IPL from the RIPL<2:0> bits (Cause<12:10>), Exception Level (EXL) bit
(Status<1>) and Error Level (ERL) bit (Status<2>) are cleared, and the Master Interrupt Enable
bit (Status<0>) is set. Finally, the General Purpose Registers will be saved on the stack. The
Cause, Status, ErrorEPC are the CPU registers and for more information on these registers, refer
to Section 2. “CPU” (DS61113).
Example 8-6:
rdpgpr
mfc0
mfc0
srl
addiu
sw
mfc0
sw
ins
ins
mtc0
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
addu

Single Vector Interrupt Handler Prologue in Assembly Code

sp, sp
k0, Cause
k1, EPC
k0, k0, 0xa
sp, sp, -76
k1, 0(sp)
k1, Status
k1, 4(sp)
k1, k0, 10, 6
k1,zero, 1, 4
k1, Status
s8, 8(sp)
a0, 12(sp)
a1, 16(sp)
a2, 20(sp)
a3, 24(sp)
v0, 28(sp)
v1, 32(sp)
t0, 36(sp)
t1, 40(sp)
t2, 44(sp)
t3, 48(sp)
t4, 52(sp)
t5, 56(sp)
t6, 60(sp)
t7, 64(sp)
t8, 68(sp)
t9, 72(sp)
s8, sp, zero

// start interrupt handler code here

DS61108F-page 8-16

Section 8. Interrupts
8.9.1.2

SINGLE VECTOR MODE EPILOGUE

Single Vector Interrupt Handler Epilogue in Assembly Code

// end of interrupt handler code

8.9.2

sp,
t9,
t8,
t7,
t6,
t5,
t4,
t3,
t2,
t1,
t0,
v1,
v0,
a3,
a2,
a1,
a0,
s8,

s8, zero
72(sp)
68(sp)
64(sp)
60(sp)
56(sp)
52(sp)
48(sp)
44(sp)
40(sp)
36(sp)
32(sp)
28(sp)
24(sp)
20(sp)
16(sp)
12(sp)
8(sp)

k0,
k0,
k0,
k0,

0(sp)
EPC
4(sp)
Status

8
Interrupts

addu
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
di
lw
mtc0
lw
mtc0
eret

Interrupt Processing in Multi-Vector Mode

When the interrupt controller is configured in Multi-Vector mode, the interrupt requests are
serviced at the calculated vector addresses. The interrupt handler routine must generate a
prologue and an epilogue to properly configure, save and restore all of the core registers, along
with General Purpose Registers. At a worst case, all of the modifiable General Purpose Registers
must be saved and restored by the prologue and epilogue. If the interrupt priority is set to receive
it’s own General Purpose Register set, the prologue and epilogue will not need to save or restore
any of the modifiable General Purpose Registers, thus providing the lowest latency.

8.9.2.1

MULTI-VECTOR MODE PROLOGUE

When entering the interrupt handler routine, the Interrupt Service Routine must first save the
current priority and exception PC counter from IPL<2:0> bits (Status<12:10>) and the ErrorEPC
register, respectively, on the stack. If the routine is presented a new register set, the previous
register set’s stack register must be copied to the current set’s stack register. Then the requested
priority may be stored in the IPL from RIPL<2:0> bits (Cause<12:10>), EXL bit (Status<1>) and
ERL bit (Status<2>) are cleared, and the Master Interrupt Enable bit (Status<0>) is set. If the
interrupt handler is not presented a new General Purpose Register set, these resisters will be
saved on the stack. Cause and Status are CPU registers; refer to Section 2. “CPU” (DS61113)
for more details.

DS61108F-page 8-17

PIC32 Family Reference Manual
Example 8-8:
rdpgpr
mfc0
mfc0
srl
addiu
sw
mfc0
sw
ins
ins
mtc0
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
sw
addu

Prologue Without a Dedicated General Purpose Register Set in
Assembly Code

// start interrupt handler code here

Example 8-9:
rdpgpr
mfc0
mfc0
srl
addiu
sw
mfc0
sw
ins
ins
mtc0
addu

Prologue With a Dedicated General Purpose Register Set in Assembly
Code

sp, sp
k0, Cause
k1, EPC
k0, k0, 0xa
sp, sp, -76
k1, 0(sp)
k1, Status
k1, 4(sp)
k1, k0, 10, 6
k1,zero, 1, 4
k1, Status
s8, sp, zero

// start interrupt handler code here

DS61108F-page 8-18

Section 8. Interrupts
8.9.2.2

MULTI-VECTOR MODE EPILOGUE

After completing all useful code of the interrupt handler routine, the original state of the Status
and ErrorEPC registers, along with the General Purpose Registers saved on the stack, must be
restored. The Status and ErrorEPC registers are located in the CPU; refer to Section 2. “CPU”
(DS61113) for more details.
Example 8-10:

Epilogue Without a Dedicated General Purpose Register Set in
Assembly Code

// end of interrupt handler code
sp,
t9,
t8,
t7,
t6,
t5,
t4,
t3,
t2,
t1,
t0,
v1,
v0,
a3,
a2,
a1,
a0,
s8,

s8, zero
72(sp)
68(sp)
64(sp)
60(sp)
56(sp)
52(sp)
48(sp)
44(sp)
40(sp)
36(sp)
32(sp)
28(sp)
24(sp)
20(sp)
16(sp)
12(sp)
8(sp)

k0,
k0,
k0,
k0,

0(sp)
EPC
4(sp)
Status

Example 8-11:

8
Interrupts

addu
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
lw
di
lw
mtc0
lw
mtc0
eret

Epilogue With a Dedicated General Purpose Register Set in Assembly
Code

// end of interrupt handler code
addu
di
lw
mtc0
lw
mtc0
eret

sp, s8, zero
k0,
k0,
k0,
k0,

0(sp)
EPC
4(sp)
Status

DS61108F-page 8-19

PIC32 Family Reference Manual
8.10

EXTERNAL INTERRUPTS
The interrupt controller supports five external interrupt-request signals (INT4-INT0). These inputs
are edge sensitive, they require a low-to-high or a high-to-low transition to create an interrupt
request. The INTCON register has five bits that select the polarity of the edge detection circuitry:
•
•
•
•
•

INT4EP (INTCON<4>)
INT3EP (INTCON<3>)
INT2EP (INTCON<2>)
INT1EP (INTCON<1>)
INT0EP (INTCON<0>)
Note:

Changing the external interrupt polarity may trigger an interrupt request. It is
recommended that before changing the polarity, the user disables that interrupt,
changes the polarity, clears the interrupt flag and re-enables the interrupt.

Example 8-12:
/*

Setting External Interrupt Polarity

The following code example will set INT3 to trigger on a high-to-low
transition edge. The CPU must be set up for either multi or single vector
interrupts to handle external interrupts
*/
IEC0CLR = 0x00008000;
// disable INT3
INTCONCLR = 0x00000008;
// clear the bit for falling edge trigger
IFS0CLR = 0x00008000;
// clear the interrupt flag
IEC0SET = 0x00008000;
// enable INT3

DS61108F-page 8-20

Section 8. Interrupts
8.11

TEMPORAL PROXIMITY INTERRUPT COALESCING
The PIC32 CPU responds to interrupt events as if they are all immediately critical because the
interrupt controller asserts the interrupt request to the CPU when the interrupt request occurs.
The CPU immediately recognizes the interrupt if the current CPU priority is lower than the pending priority. Entering and exiting an ISR consumes clock cycles for saving and restoring context.
Events are asynchronous with respect to the main program and have a limited possibility of
occurring simultaneously or close together in time. This prevents the ability of a shared ISR to
process multiple interrupts at a time.
The Temporal Proximity Interrupt uses the interrupt proximity timer, IPTMR, to create a temporal
window in which a group of interrupts of the same, or lower priority will be held off. This provides
an opportunity to queue these interrupt requests and process them using tail-chaining multiple
IRQs in a single ISR.
Figure 8-3 shows a block diagram of the temporal proximity interrupt coalescing. The interrupt
priority group level that triggers the temporal proximity timer is set up in the TPC<2:0> bits
(INTCON<10:8>). The TPC bits select the interrupt group priority value, and those values below,
that will trigger the temporal proximity timer to be reset and loaded with the value in the IPTMR
register. After the timer is loaded with the value in the IPTMR register, reads to the IPTMR will
indicate the current state of the timer. The timer decrements to zero on the rising edge of the
System Clock, SYSCLK. When the timer decrements to zero, the queued interrupt requests are
serviced if IPL<2:0> bits (Status<12:10>) are less than RIPL<2:0> bits (Cause<12:10>).
Figure 8-3:

Temporal Proximity Interrupt Coalescing Block Diagram

First
Interrupt
Detect

Interrupt
Registers

Proximity
Timer

Time
Out

Queued
Interrupt
Request

The user can activate temporal proximity interrupt coalescing by performing the following steps:
1.
2.

Set the TPC to the preferred priority level. (Setting TPC to zero will disable the proximity
timer).
Load the preferred 32-bit value to the IPTMR register.

The interrupt proximity timer will trigger when an interrupt request of a priority equal, or lower,
matches the TPC value.
Example 8-13:

Temporal Proximity Interrupt Coalescing Example

/*
The following code example will set the Temporal Proximity Coalescing to
trigger on interrupt priority level of 3 or below and the temporal timer to
be set to 0x12345678.
*/
INTCONCLR = 0x00000700;
IPTMRCLR = 0xFFFFFFFF;
INTCONSET = 0x00000300;
IPTMR = 0x12345678;

//
//
//
//

clear TPC
clear the timer
set TPC->3
set the timer to 0x12345678

DS61108F-page 8-21

Interrupts

INTCON
Latency
Value

PIC32 Family Reference Manual
8.12

EFFECTS OF INTERRUPTS AFTER RESET
8.12.1

Device Reset

All interrupt controller registers are forced to their reset states upon a Device Reset.

8.12.2

Power-on Reset

All interrupt controller registers are forced to their reset states upon a Power-on Reset.

8.12.3

Watchdog Timer Reset

All interrupt controller registers are forced to their reset states upon a Watchdog Timer Reset.

8.13

OPERATION IN POWER-SAVING AND DEBUG MODES
8.13.1

Interrupt Operation in Sleep Mode

During Sleep mode, the interrupt controller will only recognize interrupts from peripherals that
can operate in Sleep mode. Peripherals such as RTCC, Change Notice, External Interrupts, ADC
and SPI Slave can continue to operate in Sleep mode and interrupts from these peripherals can
be used to wake-up the device. An interrupt with its Interrupt Enable bit set may switch the device
to either Run or Idle mode, subject to its Interrupt Enable bit status and priority level. An interrupt
event with its Interrupt Enable bit cleared or a priority of zero will not be recognized by the interrupt controller and cannot change device status. If the priority of the interrupt request is higher
than the current processor priority level, the device will switch to Run mode and processor will
execute the corresponding interrupt request. If the proximity timer is enabled and the pending
interrupt priority is less than the temporal proximity priority, the processor does not remain in
sleep. It transitions to idle and then goes to run, once the TPT times out. If the priority of the interrupt request is less than, or equal to, the current processor priority level, the device will switch to
Idle mode and the processor will remain halted.

8.13.2

Interrupt Operation in Idle Mode

During Idle mode, interrupt events, with their respective Interrupt Enable bits set, may switch the
device to Run mode subject to its Interrupt Enable bit status and priority level. An interrupt event
with its Interrupt Enable bit cleared or a priority of zero will not be recognized by the interrupt controller and cannot change device status. If the priority of the interrupt request is higher than the
current CPU priority level, the device will switch to Run mode and the CPU will execute the
corresponding interrupt request. If the proximity timer is enabled and the pending interrupt
priority is less than the temporal proximity priority, the device will remain in Idle and the processor
will not take the interrupt until after the proximity time has expired. If the priority of the interrupt
request is less than, or equal to, the current CPU priority level, the device will remain in Idle
mode. The corresponding Interrupt Flag bits will remain set and the interrupt request will remain
pending.

8.13.3

Interrupt Operation in Debug Mode

While the CPU is executing in Debug Exception mode (i.e., the application is halted), all interrupts, regardless of their priority level, are not taken and they will remain pending. Once the CPU
exits Debug Exception mode, all pending interrupts will be taken in their order of priority.

DS61108F-page 8-22

Section 8. Interrupts
8.14

RELATED APPLICATION NOTES
This section lists application notes that are related to this section of the manual. These
application notes may not be written specifically for the PIC32 device family, but the concepts are
pertinent and could be used with modification and possible limitations. The current application
notes related to the Interrupts module are:
Title

Application Note #

No related application notes at this time.

Note:

N/A

Please visit the Microchip web site (www.microchip.com) for additional application
notes and code examples for the PIC32 family of devices.

8
Interrupts

DS61108F-page 8-23

PIC32 Family Reference Manual
8.15

REVISION HISTORY
Revision A (August 2007)
This is the initial released version of this document.

Revision B (October 2007)
Updated document to remove Confidential status.

Revision C (April 2008)
Revised status to Preliminary; Revised U-0 to r-x.

Revision D (June 2008)
Revise Register 8-1, FRZ note; Revise Examples 8-1 and 8-2; Change Reserved bits from
“Maintain as” to “Write”.

Revision E (July 2009)
This revision includes the following updates:
• Minor updates to text and formatting have been implemented throughout the document
• Interrupts Register Summary (Table 8-1):
- Removed all references to the Clear, Set and Invert registers
- Added the Address Offset column
- Added Notes 1, 2 and 3, which describe the Clear, Set and Invert registers
• Added Notes describing the Clear, Set and Invert registers to the following registers:
- INTCON
- INTSTAT
- IPTMR
- IFSx
- IPCx
• Updated the note at the beginning of Section 8.2 “Control Registers”
• Updated the second sentence of the second paragraph in Section 8.3 “Operation” to clarify
the IRQ sources
• Updated the first paragraph of Section 8.8.2 “Register Set Selection in Multi-Vector Mode”
• Updated the answer to Question 2 in Section 8.14 “Design Tips”

Revision F (July 2011)
• Added a Note at the beginning of the section, which provides information on the
complementary documentation
• Changed all occurrences of PIC32MX to PIC32
• Updated all r-x bits as U-0 bits in Register 8-1 through Register 8-6
• Updated the RIPL bit as the SRIPL bit in Register 8-2
• Updated Example 8-1 and Example 8-2
• Updated Temporal Proximity Timer register (TPTMR) as Interrupt Proximity Timer register
(IPTMR) in Register 8-3
• Added a sentence in the third paragraph of section 8.11 “Temporal Proximity Interrupt
Coalescing” about timer decrementing to zero on the rising edge of the SYSCLK
• Modifications to register formatting and minor updates have been made throughout the
document
• Removed Section 8.14 “Design Tips”

DS61108F-page 8-24

Note the following details of the code protection feature on Microchip devices:
•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

•

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
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dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.

ISBN: 978-1-61341-375-3
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS61108F-page 8-25

Worldwide Sales and Service
AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com

Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431

India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632

Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829

India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513

France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79

Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122

Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44

Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509

Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889

Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340

China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500

Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934

China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189

Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859

China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431

Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068

China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470

Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069

China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205

Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850

China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066

Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370

China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393

Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305

China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760

Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102

China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118

Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350

Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820

China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049

DS61108F-page 8 -26

Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781

Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302

05/02/11

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Title                           : PIC32 FRM - Section 8. Interrupts
Creator                         : Microchip Technology Inc.
Description                     : PIC32 Family Reference Manual, FRM, Section 8, Interrupts
Subject                         : PIC32 Family Reference Manual, FRM, Section 8, Interrupts, 61108, DS61108, 61108A, DS61108A, 61108B, DS61108B, 61108C, DS61108C, 61108D, DS61108D, 61108E, DS61108E, 61108F, DS61108F
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Author                          : Microchip Technology Inc.
Keywords                        : PIC32 Family Reference Manual, FRM, Section 8, Interrupts, 61108, DS61108, 61108A, DS61108A, 61108B, DS61108B, 61108C, DS61108C, 61108D, DS61108D, 61108E, DS61108E, 61108F, DS61108F

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PIC32 FRM Section 8. Interrupts Family Reference Manual, Sect. 08

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