PIC32 FRM Section 13. Parallel Master Port (PMP) Family Reference Manual, Sect. 13
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- Section 13. Parallel Master Port (PMP)
- Highlights
- 13.1 Introduction
- 13.2 Control Registers
- 13.2.1 PMP SFRs Summary
- Table 13-1: PMP SFRs Summary
- Register 13-1: PMCON: Parallel Port Control Register (Continued)
- Register 13-2: PMMODE: Parallel Port Mode Register (Continued)
- Register 13-3: PMADDR: Parallel Port Address Register
- Register 13-4: PMDOUT: Parallel Port Data Output Register
- Register 13-5: PMDIN: Parallel Port Data Input Register
- Register 13-6: PMAEN: Parallel Port Pin Enable Register
- Register 13-7: PMSTAT: Parallel Port Status Register (Slave modes only)
- 13.3 Master Modes of Operation
- 13.3.1 Parallel Master Port Configuration Options
- Table 13-2: Chip Select Control
- Table 13-3: Pin Polarity Configuration
- Table 13-4: Address INC/DEC Control
- Figure 13-2: Read Operation, Wait States Enabled
- Table 13-5: Address Multiplex Configurations
- Figure 13-3: Demultiplexed Addressing Mode
- Figure 13-4: Demultiplexed Addressing Example
- Figure 13-5: Partial Multiplexed Addressing Mode
- Figure 13-6: Partial Multiplexed Addressing Example
- Figure 13-7: Fully Multiplexed Addressing Mode (8-bit Bus)
- Figure 13-8: Fully Multiplexed Address Example (8-bit Bus)
- Figure 13-9: Fully Multiplexed Addressing Mode (16-bit Bus)
- Figure 13-10: Fully Multiplexed Addressing Example (16-bit Bus)
- 13.3.2 Master Mode Configuration
- Example 13-1: Initialization for Master Mode 2, Demultiplexed Address, 16-bit Data
- 13.3.3 Read Operation
- Figure 13-11: Example Read Sequence Demonstrating ‘Dummy’ Read Operation
- 13.3.4 Write Operation
- 13.3.5 Master Mode Interrupts
- 13.3.6 Parallel Master Port Status – The BUSY Bit
- Example 13-2: Example Code: Polling the BUSY Bit Flag
- 13.3.7 Addressing Considerations
- Figure 13-12: PMP Chip Select Address Maps
- 13.3.8 Master Mode Timing
- Table 13-6: PMP Read/Write Cycle Times(1)
- Figure 13-13: 8-bit, 16-bit Read Operations, ADRMUX = 00, No Wait States
- Figure 13-14: 8-bit, 16-bit Read Operations, ADRMUX = 00, Wait States Enabled
- Figure 13-15: 8-bit, 16-bit Write Operations, ADRMUX = 00, No Wait States
- Figure 13-16: 8-bit, 16-bit Write Operations, ADRMUX = 00, Wait States Enabled
- Figure 13-17: 8-bit, 16-bit Read Operations, ADRMUX = 01, No Wait States
- Figure 13-18: 8-bit, 16-bit Read Operations, ADRMUX = 01, Wait States Enabled
- Figure 13-19: 8-bit, 16-bit Write Operations, ADRMUX = 01, No Wait States
- Figure 13-20: 8-bit, 16-bit Write Operations, ADRMUX = 01, Wait States Enabled
- Figure 13-21: 8-bit, 16-bit Read Operations, ADRMUX = 10, No Wait States
- Figure 13-22: 8-bit, 16-bit Read Operations, ADRMUX = 10, Wait States Enabled
- Figure 13-23: 8-bit, 16-bit Write Operations, ADRMUX = 10, No Wait States
- Figure 13-24: 8-bit, 16-bit Write Operations, ADRMUX = 10, Wait States Enabled
- Figure 13-25: 16-bit Read Operation, ADRMUX = 11, No Wait States
- Figure 13-26: 16-bit Read Operation, ADRMUX = 11, Wait States Enabled
- Figure 13-27: 16-bit Write Operation, ADRMUX = 11, No Wait States
- Figure 13-28: 16-bit Write Operation, ADRMUX = 11, Wait States Enabled
- 13.4 Slave Modes of Operation
- Table 13-7: Slave Mode Selection
- Table 13-8: Slave Mode Pin Polarity Configuration
- 13.4.1 Legacy Slave Port Mode
- Figure 13-29: Parallel Master/Slave Connection Example
- Example 13-3: Legacy Parallel Slave Port Initialization (Example Code)
- 13.4.2 Buffered Parallel Slave Port Mode
- Figure 13-30: Parallel Master/Slave Connection Buffered Example
- Example 13-4: Buffered Parallel Slave Port Initialization (Example Code)
- 13.4.3 Addressable Buffered Parallel Slave Port Mode
- Table 13-9: Slave Mode Buffer Addresses
- Figure 13-31: Parallel Master/Slave Connection Addressed Buffer Example
- Example 13-5: Addressable Parallel Slave Port Initialization (Example Code)
- 13.4.4 Slave Mode Read and Write Timing Diagrams
- Figure 13-32: Parallel Slave Port Write Operation
- Figure 13-33: Parallel Slave Port Write Operation – Buffer Full, Overflow Condition
- Figure 13-34: Parallel Slave Port Read Operation
- Figure 13-35: Parallel Slave Port Read Operation – Buffer Empty, Underflow Condition
- 13.5 Interrupts
- 13.6 Operation in Power-Saving and Debug Modes
- 13.7 Effects of Various Resets
- 13.8 Parallel Master Port Applications
- 13.8.1 Demultiplexed Memory or Peripheral
- Figure 13-36: Demultiplexed Addressing, 8-bit Data (Up to 15-bit Address)
- Figure 13-37: Demultiplexed Addressing, 16-bit Data (Up to 15-bit Address)
- 13.8.2 Partial Multiplexed Memory or Peripheral
- Figure 13-38: Partial Multiplexed Addressing, 8-bit Data (Up to 15-bit Address)
- Figure 13-39: Partial Multiplexed Addressing, 8-bit Data
- Figure 13-40: Partial Multiplexed Addressing, 16-bit Data (Up to 15-bit Address)
- 13.8.3 Full Multiplexed Memory or Peripheral
- Figure 13-41: Fully Multiplexed Addressing, 8-bit Data (Up to 15-bit Address)
- Figure 13-42: Fully Multiplexed Addressing, 16-bit Data (Up to 15-bit Address)
- Figure 13-43: Fully Multiplexed Addressing, 16-bit Data (Up to 15-bit Address), Example 2
- 13.8.4 8-bit LCD Controller Example
- Figure 13-44: Demultiplexed Addressing, 8-bit Data, LCD Controller
- 13.9 Parallel Slave Port Application
- 13.10 Direct Memory Access Support
- 13.11 I/O Pin Control
- 13.12 Design Tips
- 13.13 Related Application Notes
- 13.14 Revision History
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