PX18_1103A_Progr_Sep56 PX18 1103A Progr Sep56
PX18_1103A_Progr_Sep56 PX18_1103A_Progr_Sep56
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UNIVAC SCIENTIFIC
GENERAL-PURPOSE COMPUTER
SYSTEM
PROGRAMMING
PX 18
SEPTEMBER 1956
DIVISION OF SPERRY RAND CORPORATION
TABLE OF CONTENTS
Page
PX 33
INTRODUCTION
PX 34
DESCRIPTION OF THE COMPUTER
l.
2.
3.
4.
5.
6.
PX 35
. ..· ·
General
.
Principal. Registers·
a. X Register.
b. Q Register.
·
c. Accumulator
·
Storage Devices
a. Addressed Storage Locations
b. Magnetic Drum Storage System. ·
c. Magnetic Core Storage System.
d. A and Q as Storage Media.
Control Components
a. Program Address Counter
b. Program Control Registers ·
c. Master Clock.
d. Main Pulse Distributor. ·
e. Main Control Translator
f. Command Timing Circuits
g. Program Interrupt Control ·
Representation of Numerical Values.
Arithmetic Operations
·
a. General .
b. Addition and Subtraction.
c. Multiply Sequence
d. Divide Sequence ••
· ·
····
·
·
··
····
·
· · · · ·· ·· ·· · · · ·· · ·· · · · ·
· · ·
·
····
··
· ········ ..
·
····
····
·····
·········
····
····· ····
····
·
· ···········
····· ····
·····
····
. · · · · ·· ·· ··
·······..
· ·····
·
····
··· ·
1
4
4
4
4
5
5
6
8
8
8
8
9
9
10
10
10
10
11
12
12
14
16
18
REPERTOIRE OF INSTRUCTIONS
1.
2.
General. • • • • . • .
. •••
Presentation of Instructions • • . • • .
a. Transmissive Instructions •.
b. Replace. Instructions
c. Split Instructions • • . •
d. Q-Controlled Ins truct ions •
• • • •
e. Sequenced Instructions • . • • • . . •
f. One-Way Conditional Jump Instructions.
g. Two-Way Conditional Jump Instructions ••
h. One-Way Unconditional Jump Instructions
i. External Equipment Instructions • • • •
j. Stop Instructions . • . • • . • • • • • •
PX 36
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
PX 37
INSTRUCTION EXECUTION TIMES
PX 18
i
1
2
2
4
4
5
5
6
7
7
8
9
TABLE OF CONTENTS (cont.)
Page
PX 38
INPUT AND OUTPUT SYSTEMS
l.
.······
,~
2.
3.
4.
5.
.
.
•
6.
7.
···
· · · · 11
····
· ·
· · · · 22
····
6
····
6
···· 8
· ·
·
· · · · · · · · · · 10
·· ·· ··
10
· ·······
12
· 16
····
····
····
16
····
··
16
·
22
····
· · · · · · · · · 32
32
· 34
··· ····
· · · · · · · · · 36
···
··
·····
· · · · 39
·····
42
········
42
····· ····
48
····
·
·
······
· · · · · 58
61
· · · · · · · · 67
········
·
·
····
General
· ..
a. Standard Equipment.
b. Optional Equipment. ·
Information Transfer.
Photoelectric Paper Tape Reader
General
:::t.
··
· ·
b. Programming for Input
·
(~
Operation
·
·
High-Speed Paper Tape Punch
·
Electric Typewriter ·
Punched Card Input/Output Sy.s tern.
Genera 1
i:l.
b. Programming for Input and Output.
I~
Operation
Univac Line Printer
;a. General
·
Jo. Programming for Output.
·
IC.
Format Switchboard. ·
d. Operation
·
Magnetic Tape System .•
;a.
General Description
lb. Operation Theory.
c. Tape Operat ion Timir.g
d. Operation
e. Improper Programminr or Operation
0
PX 39
OPE&~TING
l.
2.
3.
4.
THE COMPUTER
.· ···
··
General
·
Operation
8.
General
·
b. Normal Mode of Operclt ion.
c. Test Mode of Operation.
d. Jump and Stop Selections.
·
e. Manual Interrupt Selection.
·
.Restoration of Operation After Stops.
·
a. Programmed Stops.
b. Force Stop.
·
c. Emergency Stops
·
·
d. Fault Conditions.
·
Manual Reading and Writing.
a. Manual Writing from the Q Register.
b. Manual Reading from the Q Register.
c. Program Correction.
d. Manual Block Trans fE~r
····
····
·· ·
·
··
····
···
·······
········
·
······
······ ···········
·· ··
···
·····
· · · ·· · · · · · · · · · ··
·
·
···
··
······
··
··
····
· ·· · · · · · ·
·
· ·
PX 18
ii
1
4
4
4
7
8
8
9
9
9
9
10
12
12
13
14
14
TABLE OF CONTENTS (cont.)
Page
PX 40 CODING FOR THE COMPUTER
1.
2.
Summary of Machine Characteristics
Writing a Program.
·
a. Introduction
·
b. Instruction Notation
c. Loops.
;,
d. Subroutines. ·
e. Relative Addressing.
f. Mechanics of Coding. ·
g. Debugging a Program.
···
h. Operating Procedure.
·
Number Notation.
a. Introduction · · ·
· ·
b. Radix Conversion
·
·
c. Scaling.
·
·
·
·
·
·
d. Multiple Precision
·
e. Choice of Number Notation.
Notes on the Instructions in the Univac
Scientific Repertoire.
· ·
a. Operations Involving the Accumulator
b. Shift Instructions
· · Operations.
·
c. Round Off and, Scale ·Down
d. Accumulative Overflow.
·
··
e. Divide Overflow.
f. Repeat Instruction
·······
· ····
·
.··
3.
4.
PX 41
·
········
····
·····
········
····
····
·
··· ····
····
····
····
········
·
··
·····
····
·····
·
· · ·····
·
· ··· ·····
·····
····
··
·
······
········
·············
······
····
··
·
··
····
· ····
·
·····
· ·
1
7
7
7
8
10
21
23
26
33
36
36
37
41
45
45
45
46
48
50
51
52
53
APPENDIX A - NUMBER SYSTEMS
1.
2.
3.
..· ·····
······
General.
Change of Base ·
a. Conversion of Integers
b. Conversion of Fractions.
Representation of Signed Numbers
·
· · ·..
4
7
·········
PX 42 APPENDIX B - TABLE OF POWERS OF TWO
PX 43 APPENDIX C - DECIMAL TO OCTAL CONVERSION TABLE
PX 18
iii
1
3
10
LIST OF ILLUSTRATIONS
Figure
PX 34
1.
PX 38
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
PX 39
1.
2.
3.
4.
PX 40
1.
Page
DESCRIPTION OF THE COMPUTER
Simplified Block Diagram of the Univac Scientific
General-Purpose Computer System • • • . . • • •
3
INPUT AND OUTPUT SYSTEMS
Photoelectric Paper Tape Reader •
High-Speed Paper Tape Punch . •
Electric Typewriter • • • • • • . • • . .
Card Unit, Punch Card Input/Output System •.
Tabulating Card Fields, Columns, and Rows.
An Example of Punched Card Alphabetical and
Digital Representation. . . • . . . • .
. ••.
Univac Line Printer . • • . . . . . . . . • . • . . • . .
Optional Format for Line Printer Output • • . . . • • • .
Write Sequence. • . • . . . • • .
. .•.•
Read Forward Backward Sequence. .
. . . •
Move Forward or Backward Sequence .
7
11
13
· 17
18
19
· 33
· 40
· 54
· 55
• 56
OPERATING THE COMPUTER
Supervisory
Supervisory
supervisory
Supervisory
Control
Control
Control
Control
Panel,
Panel,
Panel,
Panel,
Overall View •
Center Section .
Right Section ••
Left Section •.
2
3
5
6
CODING FOR THE COMPUTER
Programmer's Simplified Block Diagram • . . . • . . . . . .
PX 18
v
4
INTRODUCTION
A computer is a device whic6 is capable of (1) accepting data and instructions to perform operations on this data, (2) executing the specified operations, and (3) producing the results of the operations. More specifically, a
general-purpose digital computer is capable of executing the basic arithmetic
operations, performing internal data handling operations and logical operations,
receiving data from a source external to the computer, and transmitting data to
external media of representation.
Any problem which can be solved by numerical
technique& can be handled and solved by computer operations. The given problem
must be analyzed and resolved into a collection of smaller problems, each of
which can be solved by the application of the basic computer operations.
A general-purpose digital computer comprises electrical circuits, electronic
and magnetic devices, and an associated power supply. Data which is to be
manipulated internally is given a numerical representation.
Such numbers are
represented internally by a state or a condition of a component of the computer.
Operations are performed upon the data by applying signals, effecting a change
in its condition, to the device which holds the numerically coded data.
The
function assigned to such a signal is determined according to the change
effected in the condition of the component. Data manipulations are performed
by an ordered sequence of such impulses upon the components of the computer.
The instigation of these impulses, and the regulation of the order in which
they are initiated, are the functions of the control portions of a computer.
An operation (permissible to a particular computer) occurs when a portion
of control detects a directive to begin the pre-determined sequence of steps
necessary to effect the operation. Major directives (computer instructions)
are given the computer in a prescribed coded numerical form by the operator of
the computer. These directives, and the data which is to be manipulated in a
computer operation, may be set aside within the computer, temporarily or for
later use, in the storage section.
When the information is needed, it is recalled from storage and placed in the appropriate section of the computer.
If
an arithmetic or logical operation is indicated, data is placed in the arithmetic section of the computer. Here the desired manipulations of the numbers
are effected, and temporary storage for results is provided.
The i(l)t outeut portion of the computer consists of the components necessary to
prOVIde insertion of coded data and directives into the computer
and (2) present externally the results of computations carried out by the
computer.
The power system of the computer provides regulated voltages to the four
major sections of the computer discussed above.
Discussions of computer systems have led to the establishment of a computer
"language". Certain basic terms in this language are discussed subsequently.
PX 33
1
INT~ODUCTION
STAGE
- Electronic device which may be in unique states (conditions).
The number of the ~tates possible to the device determines the
radix of the number system allowable to representation by the
computer. It is possible for a stage in the Univac Scientific
to have two unique stable states: a state which is assigned
to represent "0", End a state which is assigned to represent
"1". Thus, the racix of the number system used in the Univac
Scientific is two; the number system is the binary system.
A 'stage may receivE~ as input electrical signals (pulses) which
set it to its "1" state, set it to its "0" state, or reverse
its present state. Signals derived 'from the stage indicate
the state of the stage and are interpreted as a "1" olltput
or a "ott output. This simple system of input and output to
and from a bi-stable stage provides a means of adding, subtracting, and directly complementing binary numbers.
REGISTER
- A quantity of stages. The regulation number of stages determines the modulus cf the number system allowable to representation by the computer system. The nature of a register allows
its use as a storage device for information. Frequently, other
storage devices for information are also referred to as
"registers".
ADDRESS
- A coded number which designates specifically some particular
computer register or other internal storage location or device.
Information is referenced by its address. Portions of computer
control are responsible for directing information to or from
an addressed location.
BIT
- A binary digit, "0" or "1", represented in the computer by a
state of a bi-stable medium of representation.
WORD
OPERAND
Information coded for computer representation as a series of
bits.
The normal word length is considered to be 36 bits.
- A word representing co~ed data which is involved in computer
operations or results from computer operations.
INSTRUCTION- A 36 bit word which is a coded directive to the control section
to initiate and oversee n prescribed sequence of steps necessary to effect a particular arithmetic, logical, nr input
output operation. Portions of a computer instruction deSIgnate the operands which are involved in, and necessary for,
the execution of the particular operation.
OPERATION
CODE
- The coded portion of the instruction which "describes" to
computer control which particular operation is to be executed.
INSTRUCTION- An explanation of wl1at the execution of each instruction
FUNCTION
accomplishes, with the locations specified of (1) any operands
used during this ex(~cution and (2) any pertinent results derived from this exe<~ution.
PROGRAM
- A sequence of coded computer instructions and necessary
operands for the solution of a problem.
fiX 33
2
INTRODUCTION
INPUT OUTPUT - systems providing the means of communication between the
computer and the operator. Input and output operations
involve units of external equipment control, certain of the
computer registers, and portions of the computer control
section.
STORAGE
- consists of devices in which information is set aside for
immediate or future use. Each storage location in the
Univac Scientific has a unique. address. Each location in
the storage section of the computer is an arrangement of 36
bistable elements; hence, each location "is capable of
storing 36 binary digits.
AHITHMETIC
- a section where arithmetical and logical operations are
performed and operands and results temporarily stored.
CONTROL
- consists of components which direct the operations of the
computer.
PX 33
3
DESCRIPTION OF THE COMPUTER
1.
GENERAL
The basic concept of the solution of a problem on a computer is presented
in the following paragraphs. First, the computer instructions and their functions must be studied in order to gain a thorough understanding of the capabilities and restrictions of each instruction. When this has been achieved, the
problem to be solved is reduced to a sequence of simplified steps, the arithmetic and logical operations of which can be solved by application of the
instructions. The Univac Scientific has in its repertoire 41 instructions,
each of which is represented by 36 bits, i35 ... iO. The left-most six bits of
an instruction, i35 ... i30, represent its operation code. The remaining 30 bits
are grouped as i29 ... i15 and i14 •.. iO. These bits are designated as the u
address portion and v address portion of the instruction, respectively. These
are the portions of the instruction which represent the operands (by referencing
their location in storage, for the most part) with which the operation is concerned. A program is prepared by arranging the instructions in the order in
which their operations are desired.
The instructions are not written in binary
but are coded in octal, each octal digit representing three binary digits. Thus,
twelve octal digits represent an instruction; two digits represent the operation
code; five digits, the u addr~ss; and five digits, the v address. For example,
the instruction termed "Transmit Positive", whose function is in general
"Replace the information at a certain specified location v with the information
from another specified location u," is coded abstractly as 11 uv. With specific
locations assigned to u and v, for instance, those with the numerical assignments of 01000 and 00100, the instruction is written in octal as
11 01000 00100.
This represents the binary notation of
001001000001000000000000000001000000.
This instruction, as coded, directs the computer to "replace the content of
location 00100 with the content of location OlOOa'.
When the program has been prepared, the coded list of instructions, operands,
and any other data comprising it, are prepared for "loading", i.e., entrance
into the computer. An input procedure results in the program being stored in
the computer at a series of consecutive locations, the first of which must be
specified during the input procedure. Each instruction and operand which was
coded as a 12 octal digit number is stored at an individual location as a 36
binary digit number. Operands referenced by instructions must be stored at the
address specified by the instruction. For instance, the information to be
transferred from one location to another by the Transmit Positive instruction,
coded as 11 01000 00100, must actually be in storage at the location addressed
as 01000. During its execution, a program is usually in storage in a "rapid
PX 34
1
DESCRIPTIO~
OF THE COMPUTER
access" (high speed) type of storaqe, but it mayor may not be placed there
initially during the loading process. Rapid access storage allows the fastest
possible execution of a program SiJ1Ce it provides the quickest acquisition of
a word from storage when it is needed.
The order in which the instructions are taken from storage and executed is
regulated by the computer control :;ection. Instructions are chosen for execution according to the content of a IS-bit register in the control section.
This register holds the storage address of the instruction to be executed. To
start the execution of a program', the address of the instruction to be first
executed is placed in this register. A controlled series of electrical impulses
then (1) "review" the state of the components of the register, determining its
content, (2) direct the process of referencing this location, (3) detect the
information stored at this address, and (4) transfer it to a 36-bit register in
control reserved for holding an ins,truction during its execution. An instruction remains in this register until it is replaced by the instruction to be
executed next. The address of thi~ instruction is again taken from the 15-bit
address register. This 15-bit control register has a "counting" facility.
Normally, the number represented ir. the register is advanced by one after each
reference to storage is made. This procedure results in the automatic acquisition of instructions for execution from consecutive storage locations.
The presence of the 36 bits of an instruction in the control register reserved for it, authorizes and enables control to direct the execution of the
instruction. The particular state of the six left-most stages of the register
(those holding the operation code of the instruction) allows a certain sequence
of pulses to be released to a portion of the control circuitry~ Each pulse in
this sequence initiates a series of pre-determined operations. The particular
series inaugurated depends upon the combination of bits comprising the operation code. When, during the series of operations, the information at the
u or v addressed portion of the instruction is needed, a review occurs of the
states of the stages 29 through 15, or 14 through 0, of the register holding
the instruction. The process then is to determine this address, reference it,
and transfer the data from this location to the regis.ter where the data is
needed.
All computer operations depend primarily on sequences of pulses originating
in the control section. The pulses are :issued regularly from a "clock source"
at the rate of one every two microsecond~;. Their release, and the time of their
release, to various portions of the control section and to other sections of
the computer depends upon the current status of computer operation. This
conditional initiation of any sort of a computer operation effects an orderly
progression of the steps involved in the execution of an instruction and a
series of instructions.
The basic functional make-up of the Univac Scientific General-Purpose Computer System is illustrated i.n Figu:re 1 in which the major sections, input
output, arithmetic, storage, and cO.ltrol are delineated. A brief discussion of
some of the components of the storage, arithmetic, and control sections follows
in the subsequent paragraphs. A discussion of the input output systems is found
later in the text.
PX 34
DESCRIPTION OF THE COMPUTER
PHOTO ELECTRIC
TAPE READER
HIGH SPEED
PUNCH
ELECTRIC
TYPEWRITER
,11
TYPEWRITER
REGISTER
HIGH SPEED
PUNCH REGISTER
I
INPUT OUTPUT
REGISTER A
OPTIONAL
INPUT OUTPUT
EQUIPMENT
I
INPUT
OUTPUT
SYSTEMS
INPUT OUTPUT
REGISTER B
I~
I~
ACCU M ULATOR
Q
REGISTER
ARITHMETIC
-
--"-
X
REGISTER
MAGNETIC CORE
MAGNETIC DRUM
CO NTROL
Solid lines connecting blocks indicate the routing of binary information.
Dashed lines carry binary information used for storage reference purposes.
Information may be routed in both directions unless arrows on a line indi.cate
a one-way transfer.
Lines which carry control signals between the above blocks are not shown
on this diagram.
Figure 1.
Simplified Block Diagram of the Univac Scientific
General-Purpose Computer System
PX 34
3
DESCRIPTION OF TIlE COMPUTER
2.
PRINCIPAL REGISTERS
A large quantity of registers, PJ~oviding static storage of information, is
necessary in the computer to facilit;)te the enumerable computer operations.
The number of stages comprising a relJister depends upon the function that is
served by the register. For instance, a register intended to hold a computer
instruction consists of 36 stages; a register intended to hold a 15 binary
digit address consists of 15 stages. Operations which use in some fashion the
content of a register affect all the stages 6f the register simultaneously.
This is described as the "parallel mode" of operation, as opposed to the "serial
mode". In the serial mode of operat.ion any sampling, setting, or reversing the
states of the stages of a register, Ilroceeds cyclicly one stage at a time.
In addition to the various contrcll registers which are involved in the
execution of an instruction, there are three other principal registers which
are involved quite frequently. These registers are listed below~
a.
X REGISTER. - The X Register is used during the execution of any
instruction whose u or v add)~ess references an addressable location.
The information addressed by u or v is transmitted from its location
to the X Register, and from -:he X Register to the desired position in
the computer. Thus the X Reuister serves as a transmission register
for most internal routing of information. In addition the X Register
functions as a component of the arithmetic section of the computer.
For the corresponding arithmetic register, the X Register holds the
addend, subtrahend, multiplieand, and divisor.
In general, the X Register, abbreviated as X, is a 36-stage register
capable of temporary storage of 36 bits of information.
b.
Q REGISTER. - The Q Register functions as a component of the arithmetic
section and also serves as an addressable storage device. The Q
Register, designated as Q, cc)mprises 36 stages, affording temporary
storage to 36 bits of information.
For the corresponding arithmetic operations, the Q Register holds the
multiplier, quotient, and 10~Jical multiplier. The Q Register derives
its nomenclature from the us{~ of this register for the assembly of the
quotient during a div ide operation.
The Q Register has "shift left" with "end-around shift" facilities.
When a "shift left once" operation is completed, each stage of the
register is in the state whieh was reflected by the stage immediately
to the right of it before the operation began. The right-most stage
of the register is set to the state of the left-most stage. In other
words, the binary digits held in a register are displaced to the left,
as many places as is specified by the shift operation, with the leftmost bi t being shifted in a eircular fashion to the right end of the
register.
c.
ACCUMULATOR. - The Accumulator functions as a component of the arithmetic section and also serve~; as an addressable storage device. The
Accumulator, referred to by the letter A, comprises 72 stages,
~~4
PX
4
DESCRIPTION OF THE COMPUTER
affording temporary storage to 72 bits of information. Because the
Accumulator is capable of holding twice the number of bits of an
ordinary storage register, it is often referred to as a "double-length"
register. The left-most 36 stages of the Accumulator are referred to
collectively as AL; the right-most 36, as AR.
For the corresponding arithmetic operations, the Accumulator holds the
sum, difference, product, dividend, and (at the end of a divide operation) remainder. The Accumulator derives its nomenclature from the use
of this register for the accumulation of sums. The double length
feature of this register allows the formation of sums of more than 36
bits. It also allows the formation of the full product of any two
36 bit numbers, regardless of their numerical value; and conversely,
it allows the formation of a quotient whose numerical value is the
greatest possible (in absolute value) to represent in a 36-bit register.
The Accumulator also has the "circular shift left" property described
for the Q Register. The 72 bits held in the register are displaced to
the left, as many places as is specified by the shift operation, with
the left-most bit being shifted in a circular fashion to the right end
of the register.
The contents of a register, i.e., the bits represented by the states of its
stages, is designated by enclosing the symbol for the register in parenthesis.
For example, the 36-bit content of the X Register is denoted as (X); the content of the 36 right-hand stages of the Accumulator is denoted as (AR).
3.
STORAGE DEVICES
The information which is held in storage consists of instructions which are
to be executed and the operands needed by these instructions for their execution.
The location of each instruction or operand is referred to as its "address".
a~
ADDRESSED STORAGE LOCATIONS. - There are four classes of storage locations which are individually addressed:
Magnetic Drum Storage, MD; Magnetic
Core Storage System, MCS; the Accumulator, A; and the Q Register, Q. These
classes have the following addresses assigned to them:
Storage Class
MCS-O
MCS-l
MCS-2
Illegal Addresses
Q
A
MD
MD
MD
MD
(Group
(Group
(Group
(Group
4)
5)
6)
7)
Octal Equivalents
of Addresses
00000-07777
10000-17777
20000-27777
30000-30777
31000-31777
32000-37777
40000-47777
50000-57777
60000-67777
70000-77777
PX 34
5
Storage Space:
Number of Words
4096
4096 optional
4096 optional
1
1 double length
4096
4096
4096
4096
DESCRIPTICN OF THE COMPUTER
The banks of Magnetic Core StoraJe, MCS-l and MCS-2, are optional to the
computer system. If this storage is not provided, the addresses assigned to
MCS-l and/or MCS-2 are illegal addresses.
Additional storage, in which the information is not individually addressed,
is provided by up to ten Uniservo magnetic tape units.
Information is acquired from storage in MCS, MD, A, or Q by first determining the storage class of the address of the instruction or operand desired.
Following this, the address is translnitted to the locating control of the proper
storage class where the specific storage location is found (if the storage class
is MC or MD).
Then the information at this location is transmitted to the
X Register. Operations of this kind are referred to as "reading" operations.
"Writing" operations, or the transfer of :lnformation to a storage location, are
accomplished in a similar manner with the information in the X Register being
placed at a storage address as located by the control circuitry~
b. MAGNETIC DRUM STORAGE SYSTEM (MDL - The Magnetic Drum Storage System
provides medium-access binary storage. Digital information is stored in the
form of magnetized areas on the surface of a continuously rotating cylinder
called a magnetic drum.
The medium of storage is a magnetized bipole having
either of two polarity orientations in the lateral (or peripheral) direction.
For all practical purposes, information recorded on the drum is stored permanently.
It may, however, be removed by special erase techniques, or it may
be replaced by/simply writing new information over it. Reading from the drum
does not in any way alter the contents of the location read.
Each individual storage location is identified by specifying its angular
and axial coordinates on the drum surface. The 36 bits of a word are stored at
36 individual axial positions on the drum. A drum group has angular storage
space available in normal drum operation for 4096 36-bit words.
A total of
four drum groups results in an MD storage capacity of 16,384 words.
When a
word or a portion of a word is to be transmitted to or from the magnetic drum,
all the bits to be transmitted are handled simultaneously, i.e., in parallel.
Information may be recorded or read in ,any given area only once during each
drum revolution, resulting in a maximum access time of 34 millisec6nds.
The first octal digit of an MD address (4, 5, 6, or 7) specifies the drum
group or axial location of a word. The remaining four octal digits specify the
angular address (0 through 7777 octal) of the word in the designated group.
The angular locations during a revolution of the drum are counted and recorded
by the Angular Index Counter. An MD reference made during a computer operation
is translated according to a chosen "interlace", and held in an address interlace chassis~ When coincidence is detected between these two MD addresses, the
reading or writing operation occurs. According to the pre-selected interlace,
the reading or writing occurs at a regulated interval from the actual drum
location originally referenced. Interlaces of 4, 8, 16, 32, or 64 are available.
The address held in the address interlace chassis is the modular product (in
binary) of the angular portion of the MD address referenced, and the power of
two specified by the interlace. If an interlace of four is chosen, coincidence
occurs between consecutive MD references and the address of every fourth MD
location, etc. For example, if an interlace of eight is chosen, an MD reference
listed below in the left-hand column results in the selection of the MD location
PX 34
6
DESCRIPTION OF THE COMPUTER
listed below in the right-hand column.
Original Reference
As held in the
Address Interlace Chassis
40000
40001
40002
40000
40010
40020
40777
41000
41001
47770
40001
40011
41777
47771
47000
47001
40007
40017
47777
47777
The variable interlace system allows the selection of the minimum computer
time for consecutive MD read and write operations.
The time required for one
drum revolution is 34 milliseconds. Thus, the time which elapses between the
positioning of physically adjacent drum locations for read or write operations
is approximately eight microseconds. An interlace of "1" would mean that
references to two consecutive MD addresses would have to be made in less than
eight microseconds for the drum to be properly positioned for the second read
or write operation before a complete drum revolution has ensued. If the
references are made in less than 32 microseconds, a four interlace effects the
minimum time possible for the MD read or write operations. The interlace which
is in effect is indicated by an illuminated light on the upper right section of
the Supervisory Control Panel of the computer.
The preceding paragraphs were written with the normally addressable MD
storage locations in mind. Each drum group has, in addition to the previously
mentioned 4096 locations for storage, a "reserve space" of 160 locations which
are not normally addressable. Communication is established with these locations,
and broken with the rest of the drum locations, by setting the NORMAL/ABNORMAL
DRUM switch on the lower right section of the Supervisory Control Panel to
ABNORMAL. This will allow the detection of coincidence with reserve space locations zero through 0237 (octal). When the normally addressed portion of the
drum is in position for reading or writing, the Angular Index Counter counts
from zero to 7777 (octal) but no coincidence tests are made. When the reserve
PX 34
7
DESCRIPTION OF THE COMPUTER
space on the drum is in position for reading or writing, the Angular Index
Counter counts from zero to 0237 (oct.al) and checks for coincidence with
addresses in the address interlace chassis. The MD references made for
Abnormal drum reading or writing must be properly coded so that their form in
the interlace chassis will be octal --0000 through -0237. (The first octal digit
may be 4, 5, 6, or 7 depending upon the drum group to be addressed.)
c. MAGNETIC CORE STORAG~ SYSTEM (MCS). - Each bank of the Magnetic Core
Storage System provides rapid-access storage for 4096 36-bit words. Each core
is a bistable element capable of stOl~ing a "1" or a "0", dependent upon the
direction of magnetization of the core. The cores are arranged in a 64 x 64
matrix with 36 such matrices. The 36 digits of a given word are represented
by the state of 36 corresponding cores, one in each of the 36 matrices. Reading
and writing operations of a word, or portion of a word, are performed in a
parallel mode with a simultaneous tr~lnsmission of bits. Certain sequences of
pulses on wires through the cores, p]~oducing magnetizing forces of a certain
polarity, are used to perform the reading and writing operations.
Reading
from MC does not in any way alter the contents of the location read.
Magnetic Core Storage is non-volatile; comparable to non-volatile storage
in the Magnetic Drum Storage System.
d. A AND Q AS STORAGE MEDIA. - The Accumulator and Q Register are available
as temporary storage registers since they may be addressed. The Q Register is
normally addressed as octal 31000 al":hough any of the addresses 31000-31777 are
permissible. Similarly, the Accumulator is normally addressed as 32000 with the
addresses 32000-37777 being permissible.
4.
CONTROL COMPONENTS.
Each of the function groupings of the computer, input and output, storage,
and arithmetic, has individual control systems which direct the operations of
the section under their influence. 'rhese control systems are in turn directed
in their operations by the main computer control. This overall influence
exerted by computer control is necessary for time-wise reasons: an established
sequence of internal actions is essential for the processing of any coded information.
The computer control initiates and superintends these patterns of
actions during their performance.
The main control section receives the instructions which the computer is
to carry out; it interprets them, and directs their execution with the operands
specified. The computer must be man~ally started, but can be either automatically or manually stopped. (In addition to being automatically controlled by a
program of instructions, the computer can be manually controlled from the
Supervisory Control Panel which contains all the necessary controls and indicators for manually operating the equipment.)
The principal components of the control section are as follows.
a. PROGHAM ADDRESS COUNTER. - The Program Address Counter, PAK, is a 15stage additive register. During computation PAK generates the consecutive
addresses of the programmed instructions to be executed. The address in PAK is
normally referred to each time an instruction word is to be obtained from the
PX 34
DESCRIPTION OF THE COMPUTER
computer memory. The starting address for a computation may be manually inserted into PAK before the START (operation) button is pushed. If this is done,
computation will begin by picking up the instruction stored at that address.
If PAK is not manually pre-set, it will automatically be set to MD address
40000Q During the normal termination of an instruction, the next instruction
to be executed (the address of which is held at that time in PAK) is extracted
from storage; and the content of PAK is advanced by one. Thus, during the
termination of the instruction at address y, the instruction at y + I (the
address held in PAK) is extracted from storage, and PAK is advanced to y + 2.
If the instruction at address y indicated that the sequential acquisition of
instructions be disrupted by a jump to an instruction not stored at a consecutive address, this instruction's address is inserted into PAK previous to the
termination operations.
The program interrupt feature of the Univac Scientific, discussed in a
later paragraph, interrupts the normal process of acquiring the address of the
next instruction from PAK.
The generation of consecutive binary numbers in PAK is restricted by the
following conditions in its physical structure. There is no communication
between the stages PAKl2 and PAKII unless the stage PAKl4 contains a value of
one. Thus, PAKl2 will not be affected by the advance of PAK after the contents
of PAKII ..• PAKO reach the value of 212_1 (7777 octal). The next advance of
PAK, after such a value is reached, results in the contents of the stages
PAKII •.• PAKO being changed to zeroes. If PAKl4 does contain a one, the contents of PAK may be increased until the contents of PAKl3 ••• PAKO reach the
value of 2 14 -1. Then, since ~here is no communication between the stages
PAKl3 .•• PAKO being changed to zeros with the value of one being left un. disturbed in PAKI4. This "closed loop" system effects the generation of successive MCS addresses in PAK as follows: the addresses of each bank of MC can be
advanced to (octal) -7777, with the next advance of PAK resulting in its contents becoming (octal) -0000. If any of the Magnetic Drum addresses, regardless
of the group, are represented in PAK, the addresses can be generated consecutively to 77777 with the next advance of PAK resulting in its contents becoming
40000.
b. PROGRAM CONTROL REGISTERS. - The Program Control Registers, PCR, receive
each instruction and temporarily store it during its execution. The registers
consist of the Main Control Register, MCR, the U Address Counter, UAK, and the
V Address Counter, VAK. Each instruction sent to PCR consists of a 6-bit operation code which is stored in MCR, a IS-bit u address portion which is stored in
UAK, and a IS-bit v address portion which is stored in VAK. Each instruction is
obtained from some 36-bit storage location as specified by the Program Address
Counter, PAK. The physical structures of UAK and VAK are similar to that of
PAK. An additional restriction on the generation of consecutive binary numbers
in UAK and VAK is as follows.
If an A or Q address is in UAK or VAK, it is
not possible to advance the content of the stages zero through eight of UAK or
VAK beyond 29 -1 (octal 777). Thus, A or Q addresses are generated from octal
32000 to 32777 to 32000 and from octal 31000 to 31777 to 31000, respectively.
The generation of consecutive MC and MD addresses is the same as in PAK.
c~
MASTER CLOCK. - All the activities which take place within the computer,
except for certain ones in the output sections, are synchronized by a central
PX 34
9
DESCRIPTION OF THE COMPUTER
timing system, called the Master Clock. During NORMAL computer operation, the
clock generates 500 kc clock pulses based on timing pulses from the Magnetic
Drum Storage System, and after exerting certain controlling influences over
them, supplies them to circuits throughout the computer. During TEST operations,
a 500 kc oscillator may be used instead of the drum as the basic source of
timing pulses.
d. MAIN PULSE DISTRIBUTOR. - The Main' Pulse Distributor, MPD, receives
clock pulses and distributes them ill sequences of from four to eight pulses to
the Command Timing Circuits. The d:lstributor supplies each of the pulses
sequentially on its e.igbt output lines. In an eight pulse cycle, all of the
output lines are used, and the pulses are designated, in the order of their
generation, MPO through MP7. The s(!lection of a particular cycle is made on
the basis of the operation code held in the Main Control Register, MCR. Each
code selects the sequence which will permit the performance of the generation
in the least possible time.
e. MAIN CONTROL TRANSLATOR. - The principal translator of the Main Control
Translator, MGT, receives a 6-bit operation code from the Main Control Register
and produces accordingly a single operation code ftenable". In the COluluand
Timing Circuits, the enable from MC:~ is used in the selection of the sequence
of commands which are needed to exeeute the instruction currently in the Main
Control Register. In the Main Pulse Distributor, the MCT enable is used in the
selection of the sequence of main pulses required for the operation.
f. COMMAND TIMING CIRCUITS. - The Command Timing Circuits, CTC, produce a
discrete sequence of commands which execute the specified operation.
The commands initiated are chosen by combilling the operation code enable from the Main
Control Translator and the pulse cy(:le received from the Main Pulse Distributor.
A pulse cycle consists of two or more of the pulses MPO through MPS, and MP6
and MP7. It initiates the commands which execute the operation on pulses MPO
through MPS; reads the instruction to be executed next from storage into the
X Register on MP6; then transfers the instruction from X to PCR on MP7.
g. PROGHAM INTERRUPT CONTROL •.. An interrupt selection interferes wi th the
execution of the normal termination commands occurring on MP6. The normal
termination commands take the addreHs of the next instruction to be executed
from PAK and then advance PAK. Witll the interrupt in effect, the address 00002
in Rapid Access Storage, F3, is cho~jen as the address of the next instruction
to be executed. This instruction i~i read from storage to the X Register. On
MP7 the normal transfer of the content of X to PCR is made. This puts the
instruction at F3 in position for execution and leaves the address in PAK undisturbed. Thus, for example, if the interrupt becomes effective during the
execution of an instruction at address y, the address y + 1 in PAK (or u or v
if the instruction being executed calls for a jump) is undisturbed during MP6,
and (F3) is taken as the next instrllction. By appropriate programming, the
content of PAK may be inserted in a temporary storage location and later referred to in such a way as to return operation to the instruction stored at the
address in PAK.
The selection of an interrupt i~; effective only on an MP6 generated during
the normal termination commands. Tl1is means that the selection of an interrupt
during the repeated execution of an instruction is not effective until the
PX 34
10
DESCRIPTION OF THE COMPUTER
repeating is brought to a conclusion, either by the execution of the instruction
n times or by the occurrence of a jump. (This is discussed in more detail under
the Repeat instruction, Sequential Presentation of Instructions section.) The
interrupt selection may be made manually from the Supervisory Control Panel or
as a function of input output operations. Selecting an interrupt option during
input output operations is discussed later in the Input Output section.
Briefly, an interrupt selection may be made for input output operations by
appropriate programming or a manual setting on the piece of external equipment
involved.
5.
REPRESENTATION OF NUMERICAL VALUES
The bi-stable characteristic of the elements of the computer dictates the
use of binary number notation in the representation of information. However,
the computer cannot determine whether an array of bits is an instruction,
data with numerical value, or data coded in some arbitrary fashion. If an
array of digits is confronted in a register normally reserved for holding an
instruction, the computer will try to treat it as an instruction; if an array
of bits is confronted in an arithmetic operation, the computer will deal with
it as having numerical value.
The computer treatment of an array of bits in arithmetic operations assumes
the assignment of a numerical value to the bits as follows: the left-most bit
of an array determines the sign of the number;
a "1" designates a negative
value; a "0" designates a positive value.
The remaining bits of the array
determine the absolute value of the number.
One's complement notation is used for expressing the negative of a quantity.
The one's complement of a binary digit is the digit subtracted from the value
of one. The one's complement of a digit represented by the state of a bi-stable
element is formed by merely reversing the state of the element. In a number
system which includes all the possible combinations of "O's" and "l's" from
000 ••. 000 to III ••• Ill, positive quantities are represented by the combinations in which the left-most bit is zero, 000 ••• 000 to 011 ••• Ill. The
negatives of these quantities are represented by their one's complement, the
combinations in which the left-most bi t is one, III ••• III to 100 ••• 000.
This left-most bit is termed the sign-bit of the number.
The bits representing a number are held in an arrangement of bi-stable
elements, such as the stages of a register. The designation of the left-most
element of k elements is given the subscript k-l; the designation of the
adjacent element is given the subscript k-2; and continuing to the right, the
designation of the right-most element is given the subscript O. For example,
the 36 stages of the Q Register are designated as Q35, Q34, ••• , Ql, QO. In
general, the stage Sk-l of a k stage register holds the sign bit of a number,
and the absolute value of the number is determined by the contents of
stages Sk-2' .•• '~O.
If the sign bit is "0", the bits in stages Sk-2, .... ,SO
are the coefficients ai of a binary number ak_22k-2 + ak_32k-3 +..• a 12 l + a020.
If the sign bit is "1", the one's complement of the bits in stages Sk-2, .... ,SO
are the coefficients of the absolute value of the number. (The term "most
significant bit" is given to the first digit from the left which differs from
the digits to its left~) The values possible to represent in k bi-stable
elements are in the range with the limits of ± (2 k- l -l), inclusive. In a
PX 34
11
DESCHIPTION OF THE COMPUTER
36 stage register, the limits are ±C2.35_1); in the 72-stage Accumulator, the
limits are ±C271_1). The modulus of 1 number system represented by k stages is
2k. However~ if "plus zero" and "minus zero" are treated as a unique quantity,
as is the case in the Univac Scientific, the modulus is 2k -l.
The assumption of the binary point to the right of the right-most bit means
that all numbers are considered ,as integers. This does not mean, however, that
numerical operations are restricted tl) integers only or to integers in these
ranges. A binary number s may be exp:ress edt as s = s 12 s2 • If s 1 and s2 may be
expressed as integers with values in the range appropriate for their placement
in the computer, sl and s2 may represent in the computer the number s. Numerical operations involving sand t (t = t 2 t 2) are performed machine-wise by the
1
proper arithmetical procedures involving sl and tl," and s2 and t2. Fractions
may be represented machine-wise by integral values of sl and s2; s2 being
negative.
If s is scaled to its maximum representation by 36 bits such that
235 >lsIf~ 234 , the number s is said to be "normalized tt •
To summarize the preceding discus:;ion, numerical quantities, represented
in the computer by k hi-stable elements, are integers of a binary number system.
A negative number N of this system is represented in one's complement notation
as 2k_1 - INI. The range of integer:; I possible to represent in a 36 stage
register is
in the
6.
72-s~age
Accumulator,
ARITHMETIC OPERATIONS.
a. GENERAL. - The modulus of the one's complement binary system, as
involved in arithmetic operations in ~~he computer, is 2k_l where kis the
number of stages in the registers involved in the operations. If the registers
involved in the operations consist of 36 stages, the modulus of the number system
is 236 _1. If the Accumulator is involved in the operations, the modulus of the
system is 272 _1. This modulus of 2k_:l (instead of 2k) results from the generation during arithmetic operations of 8 unique representation of zero, i.e.,
each bi-stable element in the "0" state.
The generation of a negative zero
representation, i.e., each bi-stable element in the "1" state, is not possible.
When an instruction necessitates 1~he transmittal to the Accumulator of a
36-bit integer, the conditions are establi~hed during the operation that change
the modulus of the integer from 236 _1 to 2 2_ 1• This is effected by assuming
the existence of 36 bits to the left of the sign-bit. This "72-bit" integer
is then transmitted to the Accumulato]~. The final modular contents of A reflects the value of the "72-bit" inteuer according to the nature of the transmitting operation. If it is desired that the one's complement signed value of
the 36-bit integer be retained, the Ol)eration assumes that each of the simulated
36 left-hand bits has the value of the sign bit. Such an extension of a 36-bit
number is designated as a double lengt.h extension, D(L), where L is the location
address of the 36-bit number and (L) is the content of that address. If it is
desired that the value of the machine expression of the 36-bit integer be left
undisturbed by the transmitting opera1.ion, the value of the sign-bit of (L) is
disregarded, and the assumption is made that 36 zeroes exist to the left of the
sign-bit of the number. This "72-bittt number is designated as SCL), a split
double-length extension.
PX 34
12
DESCRIPTION OF THE COMPUTER
When one of the above transmissions to the Accumulator is required, the 36bit integer is first placed in the X register (by the operations of whichever
instruction is being executed).
(The only means of information transfer to or
from A is via X.)
Then, according to the instruction being executed, a machine
sequence is performed which adds or subtracts one of the double length extensions to or from the content of the Accumulator.
Most of the arithmetic operations in the computer are accomplished by combinations of such computer commands as listed below. The commands themselves,
which are internal computer directives, are instigated as the result of computer
control interpreting a particular instruction operation code. Some of the more
commonly used commands are as follows:
Clear X
Complement X
Clear Q
Shift Q
Clear
Clear
Clear
Shift
A
AR
AL
A
Commands which direct transmissions between X, Q, and A
A series of subcommands which in different combinations accomplish the
following:
Add D(X) to A
Subtract D(X) from A
Split Add X to A, i.e., Add S(X) to A
Split Subtract X from A, i.e., Subtract S(X) from A
(1)
CLEAR X, Q, OR A. - Commands which direct the clearance of any
register result in each stage of the register being set to its
zero state.
(2)
COMPLEMENT X. - The command which directs the complementation of
the cOntent of the X Register reverses the state of each stage of
the register. The complement of the content of X is denoted as (X'l
(3)
SHIFT Q OR A. - These commands effect the left shift of the bits
in the register the number of places prescribed by the instruction
and established internally in a shift counter. A shift left of k
places is equivalent to a right shift of 36-k or 72-k places. A
left shift effects a modular multiplication by a power of two.
A "right shift" is equivalent to a modular division by a power of
two. The word modular is emphasized because of the circular
shifting feature which effects the shift of the bit represented in
the left-most stage to the right-most stage.
The operations of addition and subtraction are treated subsequently.
PX 34
13
DESCR 1PT 10:'1 OF THE COMPUTER
b. ADDITION AND SUBTRACTION. - The fundamental arithmetic operation of
the computer is subtraction. The Accumulator is termed a subtractive Accumulator
because all additions and subtractio.ls arE- performed by a subtractive process.
The ini,tia 1 c.ontent of A, (A) i, is the minuend, and the fina 1 content of A,
(A)f' is the remainder. This subtral~tive process is used as the basis of all
arithmetic operations involving addition and subtraction. This prevents, as
the result of an arithmetic operation, the representation of zero by a one in
each stage of the Accumulator.
The process of subtraction neces:~itates an ability to borrow from a lefthand digit or digits. Machine-wise ·this is made possible by the parallel construction of the stages of the ACCUmlJlator. The end-around borrow as ,discussed
in Appendix A. of this volume, is a feature of subtraction in the Accumulator:
a borrow propagated past the stage A'71 is applied to the stage AO.
The number to be added to, or subtracted from, the content <:>f the Accumulator is placed in the X Register. Thl~n, according to the operation desired, a
sequence of actions occurs which lea 1res in the Accumulator the desired answer.
If a subtraction sequence is execute(l, the remainder is reflected in the final
content of the Accumulator as the initial content of the Accumulator minus one
of the double-length extensions of the content of X, i.e.,
(A). - D(X)
1
or
If an addition sequence is executed, the sum is reflected in the final content of the Accumulator as the initial content of the accumulator minus the
complement of one of the double-length extensions of the content of X, i.e.,
(A) •
D(X )'
(A)·1
S (X) t
1
or
=
•
Any references in this text to the acldition of a number to the Accumulator
should thus be interpreted as the pr(tcess of subtracting the complement of the
number from the Accumulator.
Actually, the machine subtraction sequences use procedures of an addition
sequence after an appropriate complementation of (X).
The general procedures of the fOtlr addition and subtraction sequences are
listed below with examples of the opE!rations given to the left. The examples
use an X Register of four stages and an Accumulator of eight stages. These
sequences use the same internal subcommands in different combinations according
to the operation desired and the content of the X Register.
PX 34
14
DESCRIPTION OF THE COMPUTER
ADD X TO A
Assume the existence of D(X)
Subtract complement of D(X) from A
SPLIT ADD X TO A
Assume the existence of S(X)
Subtract complement of S(X) from A
(A )i
(X) 1.
D(X)i
D(X)i'
= 0000
=
= 1111
= 0000
0110
1100
1100
0011
minus
(A)f
=
0000
0000
0000
0110
0011
0011
(A) 1.
(X) 1.
S(X )i
S(X) i '
= 0000
=
= 0000
= 1111
0110
1100
1100
0011
0000
1111
0001
0001
0110
0011
0011
1
0010
(A) 1.
= 0000
(X )i
=
(X' ).1 =
D(X' ). = 0000
D(X' )~, = 1111
1
0110
1100
0011
0011
1100
0000
1111
0000
= 0000
0110
1100
1010
1
1001
(A) 1.
= 0000
(X) 1.
=
S(X)i
= 0000
S(X)·· = 1111
[S(X) ~.] • = 0000
0110
1100
1100
0011
1100
0000
0000
1111
0110
1100
1010
1
1001
minus
borrow
(A)f
SUBTRACT X FROM A
Complement (X)
Assume the existence of D(X)
Subtract complement of D(X) from A
=
minus
borrow
(A)f
SPLIT SUBTRACT X FROM A
Asstime the existence of S(X)
Complement S(X)
Subtract complement of S(X) from A
minus
borrow
(A)f
PX 34
15
=
1111
(:=+6 )
(:=-3 )
(:=+3 )
(:=+6 )
(:=+12 )
(:=+18)
(:=+6 )
(:=-3 )
(:=+9 )
(==+6 )
(:=+12 )
(==-6 )
DESCRIPTI01~
OF THE COMPUTER
c. MULTIPLY SEQUENCE. - Multiplication performed machine-wise uses the
shifting facilities of the Accumulator and the Q Register, and the Add X to A
sequence.
The execution of an instruction which orders a machine multiplication places the multiplier in the Q Register, Q, places the multiplicand in the
X Register, X, and forms the product in the Accumulator, A.
The product is
formed by adding the multiplicand, or D(X) machine-wise, the appropriate number
of times, as determined by the ~its of the multiplier, (Q), into the Accumulator.
The procedure is as follows.
Repeat 36 times:
Shift (A) left one place.
If the current (Q~15) is 1, add D(X) to.(AL
Shift (Q) left one place.
1.
2.
3.
The result would be the formation of the sum
{{CQ35 • O(Xl)
2
+ Q34
• O(Xl}
2
+ ... + Ql
• O(Xl} 2
+ QO • O(Xl.
Thus, the multiplication of a number in X by a number in Q results in a sum in
the Accumulator of
An example of the multiplication process follows, using four bit Q and X
registers and an eight bit Accumulat,)r. The machine-wise formation of a sum by
complementation and subtraction is n,)t shown.
(X)
(Q)
= 0011,
= 0101,
multiplicand of decimal 3
multiplier of decimal 5
Stages of A
initial content of A
o
0
0
0
000
o
0
0
0
o
o
shift (A) left
add D(X) to (A)
000
0 0 0 0
0 0 1 1
001 1
0
0
0
o
1
shift (A) left
o
o
o
0
0
0
0
0
0
0
0
0
o
1
100
o 0 0 0
shift (A) left
0
,~--;;....
1
0 1
III
0
shift (A) left
add D(X) to (A)
final content of A
(product = decimal 15)
1
1
The procedures above form the pr(~uct of the actual binary numbers in Q and
If the multiplier and multiplicand are positive, the product formed by the
process, (Q)(X), will be the desired product. If the multiplier, Mq , is negative, the content of Q is 236 - 1 - IMql , ahd the product formed by the
x.
PX 34
16
DESCRIPTION OF THE COMPUTER
computer ~~ 236 (X) - (X) - 1M I(X). Since the product desired is - I Mql (X),
a correctiv~. of ~he product f~rmed by the computer is necessary. The correction.
-2 36 (X) + (X), is made during the Multiply Sequence by (1), subtracting O(X)
from A before the first performance of "Shift A left one place" (providinu the
correction -2 36 (X) since a shift left of 36 places follows the subtraction);
and (2), adding D(X) to (A) after the last performance of "Shift Q left one
place", providing the correction +(X).
An example of multiplication with a negative multiplier is given below.
o
0 0 0
o 000
1 1 1 1
1 1 1 1
(X)
= 0011,
multiplicand of decimal 3
(Q)
= 1010,
multiplicand of decimal -5
000 0
001 1
1 100
initial content of A
subtract D(X) from (A)
1 001
shift (A) left
add D(X) to (A)
000 0
1 1 1 1
o0 1 1
1 1 1 1
100 1
shift (A) left
1 1 1 1
o
o
o
shift (A) left
add D(X) to (A)
o 000
1 1 1 1
1 110
000
o
1 III
1 100
0 1 1
0 1 1
1 1 0
110 1
o0 1 1
o0 0 0
shift (A) left
add D(X) to (A)
final content of A
(product = -15)
A multiplication with a negative multiplicand requires no correction. A
multiplication with both multiplier and multiplicand negative requires the same
correction cited above.
If the instruction being executed is such that the product of (Q) and (X)
is to be added to a number already in the Accumulator, the content of A is
shifted 36 places to the left preceding any of the multiply operations. This
positions the most significant digits of (A) in AR in readiness for the additions of the multiplicand toA and the shifting operations. Prior to the actual
multiplication operations of the MultiRly Sequence, the initial content of A is
tested for the condition 271 > I(A)il~270. If this is evidenced by (A)35 f:. (A)34'
an A Fault is indicated on the Supervisory Control Panel, and machine operations
are stopped. This condition indicates the possibility of an "overflow" during
the Multiply Sequence, i.e., the modular sums resulting from the additions of
D(X) to (A) may reach the positive or negative value capacity of A,2 71 - 1 or
1 - 271; and, as the result of continuing additions, become a number,
S :: 1 - 271 or S~ 271 - 1, thus destroying the cumulative effect desired.
PX 34
17
DESCRIPTION OF THE COMPUTER
d, DIVIDE SEQUENCE. - The machillB proeess of division, as ordered by the
Divide instruction, employs the Accum~lator, the X Register, and the Q Register
in such a manner that
The 72-bit dividend is initially contained in the Accumulator; the divisor is
placed in the X Register, and the quotient. is formed in the Q Register with the
remainder of the division left in A. The division process utilizes the shifting
facilities of Q and A and the operations which add and subtract D(X) into A.
In general, the steps of the Divide Sequence are as follows.
1.
Shift (A) left 36 places.
Repeat the following steps 36 tines:
2.
Shift (A) left once
3.
Set (QO) to zero or one
4.
Add or subtract D(X) into A
5.
Shift Q left one.
The operation performed insteps 3 and 4 is determined by a relationship between
appropriate digits of the dividend and divisor.
The basic pri~ciple of the Divide Sequence is as follows: decrease a postive dividend ~~ the product of the divisor and descending powers of two, beginning with 2 J, until a negative number results; increase this remainder by
the product of the divisor and successive descending powers of two until a
positive number results; decrease this number, etc. Continue this procedure
until the product of the divisor and 20 has been added or subtracted, yielding
the final remainder. Note that the product mentioned above may in itself be
positive or negative depending on the sign of the divisor. Each time a product
is subtracted r a one is inserted in the right-most stage of the Q aegister and
subsequently shifted left once; and each time a product is added, the contents
of Q, as it stands, are shifted left once. After the final shifting of those
bits inserted in Q, the register will contain a correct value of the quotient
although a negative final remainder as derived above may necessitate an increase
or decrease in the value of the quotient. If the final remainder of the above
procedure is negative, the remainder is increased by the absolute value of the
divisor and the quotient adjusted accordingly by increasing or decreasing its
value by one.
The examples below illustrate the basic principle of the Divide Sequence.
The examples use four bit Q and X registers and an eight bit Accumulator. The
machine processes of shifting the bits in the Accumulator and the Q Register,
which facilitate the division machinewise, are not shown. Also, the machinewise formation of sums and differences by complementation and subtraction is
not shown.
PX 34
10
DESCRIPTION OF THE COMPUTER
Exam121e 1
Dividend is 0000 1110, (A ).Divisor is 0100, (X)
0000
010
1110
0001
1111
0000
0000
0000
0000
1110
0000
1101
0000
1101
1000
0110
0100
0010
(=14)
(= 4)
+14
-( +32)
-18
+(+16)
plus D(X) -22
- 2
+(+ 8)
plus D(X) _21
+ 6
-(+ 4)
minus D(X) - 20
+ 2
Remainder =
Dividend
3=
minus D(X)-2
In this example the quotient is derived as follows: the divisor- is such that
it may be subtracted from ·the dividend 23 -22_21+2 0 times, or in binary
1000
-0100
-0010
+0001
0011
(=3)
which is the content of the Q Register after the final shifting of the bits
inserted into it_ Thus, the final results of this division are
Quotient is 0011, (Q)f
Remainder is 0000 0010, (A)f
(::;3)
(=2 )
Example 2
(=14)
(=-3)
Dividend.is 0000 1110, (A) 1Divisor is 1100, (X)
0000
1110
1111
1111
0000
1111
1111
1111
1111
1110
0111
0101
0011
0010
1001
1011
1100
1110
Dividend
plus D(X)-2 3
=
+14
+(-24)
-10
minus D(X)-22
-( -12)
+ 2
plus D(X) -21
+(-6)
-4
minus D(X)-2 0
-(-3)
Remainder =
-1
In this example the quotient is derived as f~llows:
the divisor is such that
it may be subtracted from the dividend -2 3+2 -21+20 times, or in binary
-1000
+0100
-0010
+0001
1010
(=-5)
PX 34
19
DESCRIPTION OF THE COMPUTER
which is the content of the Q Register after the final shifting of the bits
inserted into it. Thus, the results of the division process thus far are
Quotient is 1010,
(Q)
Remainder is 1111 1110, (A)
(=-5)
(=-1)
but, since the remainder resulting from this division is negative, the value of
the divisor is subtracted from it, and the quotient is subsequently increased
by a value of one.
Thus, the final results of the division process are a
Quotient of 1011,
(Q)1'
Remainder of 0000 0010, (A)f
(=-4)
(=+2)
If the dividend is negative, the procedure for dividing is essentially the
same, with the dividend being first increased to a positive number, then decreased, etc.
During the division sequence (but before the quotient is adjusted for a
negative remainder, if such is the case) machine divide checks are made which
determine if the value of the quotient should be an integer which would exceed
the capacity, 235 -l~ I ~1-225, of the Q Hegister. If such is the case, an A
Fault is indicated on the Supervisory Control Panel, and the machine operations
are stopped.
Since these divide checks are made before any final adjustments to a
(negative) remainder and quotient, the division process as illustrated previously,
but with a negative dividend, could result in an inaccurate value for the
quotient if a negative remainder was left during a division in which the
quotient was 235 _1 or 1-235. To take care of such cases in such a way that the
division will be stopped by a divide check, an initial correction and an end
correction are made during all divisions with negative dividends. These are
illustrated by the following example in which the division without the initial
correction (which decreases the dividend by the value of the divisor) would
result in an inaccurate quotient. The division in the example below would not
be carried to completion but would be stopped, as is shown, by the occurrence
of the divide check A-Fault.
Example 3
Dividend is 1110 1001, (A).I
(=-22)
(=-3)
Divisor is 1100, (X)
Dividend
1110 1001
-22
1111 Il0q
~lus DeX),initial correction +(- 3)
1110 0110
-25
_ (-24)
rrinus D(X)·2 3
1110 DIll.
1111 lII()
- 1
-( -12)
minus D(X)-2 2
1111 001~
0000 1011
+11
20
DESCRIPTION OF THE COMPUTER
In this division the process would be stopped, after the subtraction of
D(X) ·22 from the previous remainder, since the quotient derived thus far
would indicate that the divisor can be subtracted from the dividend 23 + 22 +
(±21 ±2 0 ) times, the value of which in all cases exceeds the value possible to
the quotient.
If this division were performed by the Divide Sequence wi thout
initial correction above, it would proceed as follows:
1110
1110
0000
1111
1111
1111
1111
1111
1111
1001
0111
0010
0011
0101
1001
1011
1100
1110
Dividend
minus D(X) .2 3
plus D(X) • 22
minus D(X ). 21
minus D(X ). 20
makin~J
the
-22
-( -24)
-+ 2
+( -12)
-10
-(- 6)
- 4
-(- 3)
- 1 •
Thus, the division indicates that the divisor can be subtracted +2 3 _2 2+2 1+2 0
(=7) times from the dividend leaving a remainder of -1. The correction to the
quotient for this negative remainder would be
plus
(=7)
0111
Quotient, (Q)
1
10nO
Incorrect value of quotient (=-7)
Thus, the final contents of the Q Register would be the number above with no
indication of the overflow of the modular value allowable to the quotient.
PX 34
21
REPERTOIRE OF INSTRUCTIONS
1.
GENERAL
The logic of the Univac Scientific computer is specified as a two-address
logic. This means t~at two references are provided for the execution of an
operation, and an instruction to perform this operation is coded accordingly.
The references may be the addresses of operands or other instructions in
storage, the address at which a result is to be stored, or they may have a
special designation as noted subsequently.
An instruction word in the computer consists of 36 bits, i35
the following composition:
Operation code, O.C.
i 35 ••• i 30 , six bits
First execution address, u
i29 ••• i15, 15 bits
iO' with
Second execution address, v
A programmed instruction is coded using octal notation.
by octal digits as follows:
-O.C. (i35··· i 30)
It is represented
'two octal digits
u
(i 29 ···i 15 )
five octal digits representing the bits u 14. • • Uo
v
(i14··· i O)
five octal digits representing the bits v 14. • • Vo
According to the function of the instruction, the portions u and v of the word,
represented in octa 1 notation, may be d'es ignated as follows:
j
one-digit octal number as represented by the left-most binary digits
of u, u14, u13, u12
n
four-digit octal number as represented by the binary digits ull'
u 10' ••• Uo
k
number of shifts as represented by the right-most binary digits of
v, v6, v5' ••• vO; or in one case, as represented by the right-most
binary digits of u, u6' u5, ••• , uO.
The functions of the instructions in which j, n, and k occur in place of a
storage address will explain their purpose.
Following are other symbols used in the explanation of the functions of the
instructions.
PX 35
1
REPEHTOIHE OF INSTRUCTIONS
a.
Parentheses are used to denote content(s) of, thus:
(u)
(Q)
(A)
(AU)
(A L )
b.
= 36-bit
= 36-bit
= 72-bit
= 36-bit
= 36-bit
word
word
word
word
word
at
in
in
in
in
address u
Q
A
AR
AL
Lower case letters:
qn is the bit represented by the stage Qn,
35~n~O
an is the bit representeel by the stage An,
71~ n~O
c. A prime denotes a complement; such as (Q)' is the complement of the
36-bit word in Q.
d.
Double length extensions:
D(u) is a 72-bit word whose right-hand 36 bits are (u) and whose
left-hand 36 bi1s are all alike and equal to the left-most bit of (u).
S(u) is a 72-bit word whose right-hand 36 bits are (u) and whose
left-hand 36 bits are all zeros.
D(Q), D(X), seQ), and
sex)
are similarly defined.
L(Q)(u) is a 72-bit word whose left-hand 36 bits are zeros and each
of whose right-hand 36 bits is detelmined by the bit-by-bit product of the
corresponding bits of (u) and (Q).
L(Q)'(v) is a 72-bit wore: whose left-hand 36 bits are zeros and each
of whose right-hand 36 bits is determined by the bit-by-bit product of the
corresponding bits of (v) and the c(mplement of (Q).
2.
PRESENTATION OF INSTRUCTIONS.
The Ijsting of the Univac Scientific repertoire of instructions which
follows has the instructions groupee. according to a basic similarity in their
functions or operations. The simil~.rity may be due to the use which is made of
the u and v address portions of the instruction, or it may be because a group
of instructions uses complex inte-rn~.l sequences. The instructions are presented
with their functions, octal codes, ~.nd the alphabetic notations which represent
them.
a. TRANSMISSIVE INSTRUCTIONS. _. This group of instructions uses the u
address portion of the instruction as an "acquisition" address (with one
exception), lNhich designates the location from which information is to be
obtained. This information may the~ be involved in some sort of operation,
depending upon the function of the ~'articular instruction.
The v address
portion of the instruction specifies the location to which the information
from u, or the information resulting from any operation executed, is transmitted.
3~)
PX
2
REPERTOIRE OF INSTRUCTIONS
The original content of the location specified by u is not disturbed in any
way by the acquisition of information from the location. The original content
of the location specified by v is replaced by the information transmitted to it.
The instructions are as follows.
lluv:
TRANSMIT POSITIVE (TPuv):
Replace (v) with (u).
12uv:
TRANSMIT MAGNITUDE (TMuv): Replace (v) with the absolute magnitude
of (u).
13uv:
TRANSMIT NEGATIVE (TNuv):
15uv:
TRANSMIT U ADDRESS (TUuv): Replace the IS bits of (v) designated by
(v29 ••• vlS) with the corresponding bits of (u), leaving the remaining
21 bits of (v) undisturbed.
.
16uv:
TRANSMIT V ADDRESS (TVuv): Replace the right-hand IS bits of (v)
designa'ted by (v14 ••• vO) with the corresponding bits of (u), leaving
the remaining 21 bits of (v) undisturbed.
Replace (v) with the complement of (u).
22jkv: LEFT TRANSMIT (LTjkv): Left circular shift (A) by k places, k being
u6 ••• uo.
Then replace (v) with (A L) if j = 0, or replace (v) with
(AR) if j = 1.
35uv:
ADD AND TRANSMIT (ATuv):
Add -D(u) to (A).
Then replace (v) with
(A R ).
36uv:
SUBTRACT AND TRANSMIT (STuv):
(v) with (A R).
Subtract D(u) from (A).
Then replace
The first five instructions listed, TPuv, TMuv, TNuv, TUuv, and TVuv, do
not involve 'any of the arithmetic registers except the X Register in their
execution (unless u or v is A or Q). The information is acquired from u and
placed in X where it mayor may not be manipulated according to the function of
the instruction. The desired content of X is then transmitted to the vaddressed location. The instructions TUuv and TVuv are intended for the modification of the u and v address portions of other instructions in storage.
The remaining three instructions in the list, LTjkv, ATuv, STuv, involve
the Accumulator in their execution whether it is addressed or not. The Left
Transmit instruction provides the only means of coding a transmission directly
from AL. Any other transmissions made from A to a 36-bit storage location take
the content of the 36-r igh t -mas t stages of A, (AR).
The sum or difference formed in the Accumulator by ATuv or STuv is not disturbed by the transmission of (AR) to v. The 36-bit number stored in v may be
interpreted as a different quantity than the sum or difference left in A if
"overflow" occurred during the addition or subtraction into the sign-bit stage
A35. The quantity in A must be ~ 235 -1 in absolute value if it is to reflect
the sum or difference correctly in a 36-bit storage location. If the sum or
difference is used directly from A in further operations, an overflow past
the stage A34 need not be disturbing. In this case, a check should be made for
an overflow past the stage A70, i.e., the sum should be ~ 271_1 in absolute value.
35
PX
3
REPERTOIRE OF INSTRUCTIONS
b. REPLACE INSTRUCTIONS. - This group of instructions uses the u-address
portion of the instruction as an acquisition address and later places information back at the u-addressed location, destroying its original content. The
v-addressed portions of the instruction are used to reference operands ~r hold
a shift count ..
The instructions are as follows.
21uv:
HEPLACE ADD (RAuv): Form in A the sum of D(u) and D(v).
replace (u) with (A R).
Then
23uv:
HEPLACE SUBTRACT (RSuv): Form in A the difference D(u) minus D(v).
Then replace (u) with (AR).
27uv:
CONTROLLED COMPLEMENT (CC;uv): Replace (A R) with (u) leaving (AL)
undisturbed. Then complement those bits of (AR) that correspond to
ones in (v). then replace (u) with (AR).
54uk:
LEFT SHIFT IN A (rAuk): Replace (A) wi th D( u). Then left circular
s:Pift (A) by k places and replace (u) with (AR). If u is the address
of the Accumulator, the first step is omitted, so that the initial
content of A is shifted.
55uk:
LEFT SHIFT IN Q (LQuk): Replace (Q) with (u). Then left circular
shi.ft (Q) by k places and replace (u) with (Q).
The content of A is left undisturbed by the transmission of (AR) to u as
effected by the first four instructions above. The content of Q is undisturbed
by the transmission to u during the Left Shift in Q instruction.
The sum or difference formed by RAuv or RSuv must be ~
235 _1 in absolute
value if the quantity stored at a 36-bit location u is to reflect the proper
value.
Note that the function of instrl1ction CCuv may be thought of as "Replace
the content of u with the bit-by-bit sum of (u) and (v), disregarding any
carries propagated".
c. SPLIT INSTRUCTIONS. - The following group of instructions uses the
u address of the instruction as an ~lcquisition address and assumes in the X
Register the split extension of the content of the specified location. SeX)
is then added or subtracted into the accumulator after which the content of.A
may be shifted. These instructions make it possible to effect a change in
(AR) without disturbing (AL).
The instructions are as follows.
31uk:
SPLIT POSITIVE ENTRY (SPuk): Form S(U) in A. Then left circular
shift (A) by k places, k being v6 ••• vO and vI4 ••• v7 being zero.
32uk:
SPLIT ADD (SAuk): Add S(u) to (A). Then left circular shift (A)
by k places, k being v6 ••• vO and vI4 ••• v7 being zero.
PX 3!5
4
REPERTOIRE OF INSTRUCTIONS
3auk:
SPLIT NEGATIVE ENTRY (SNuk): Form in A the complement of S(u).
Then left circular shift (A) by k places, k being v6 ••• vO and
vI4 ••• v7 being zero.
34uk:
SPLIT SUBTRACT (SSuk): Subtract S(u) from (A). Then left circular
shift (A) by k places, k being v6 ••• vo and vI4 ••• v7 being zero.
d. Q-CONTROll..ED INSTRUCTIONS. - These instructions use the u address as an
acquisition address and transmit to the v-addressed location the final content
of ARe The final content of AR is effected by the content of the Q Register
which is used as a tt~ask". The "l's" in the information acquired from the
u-addressed location are retained only when there are "l's" in the corresponding
stages of Q.
The instructions are:
5Iuv:
Q-CONTROLLED TRANSMIT (QTuv):
replace (v) with (AR).
Form in A the number L(Q)( u).
52uv;
Q-CONTROLLED ADD (QAuv):
replace (v) with (AR).
53uv:
Q-CONTROLLED SUBSTITUTE (QSuv): Form in Q the quantity L(Q)(u)
plus L(Q)'(v). Then replace (v) with (AR). This effects the replacement of selected bits of (v) with the corresponding bits of (u)
in those places corresponding to one's in Q.
Add to (A) the number UQ )(u).
Then
Then
e. SEQUENCED INSTRUCTIONS. - The following instructions use complex
sequences of computer operations.
7luv:
MULTIPLY (MPuv): Form in A the 72-bit product of (u) and (v),
leaving in Q t~e multiplier (u).
72uv:
MULTIPLY ADD (MAuv): Add to (A) the 72-bit product of (u) and (v),
leaving in Q the multiplier ,(u).
73uv:
DIVIDE (DVuv): Divide the 72-bit number in A by (u), putting the
quotient in Q, and leaving in A a non-negative remainder R. Then
replace (v) by (Q). The quotient and remainder are defined by:
(A ) i = (u) • (Q) + R, wher e 0 S R < I(u )I. (A ) ide not est he in i t i a 1
content of A.
74uv:
SCALE FACTOR (SFuv); Replace (A) with D(u) (unless u is A). Then
left circular shift (A) by 36 places and continue shifting until
a34 ~ a 35 • Replace the right-hand 15 bits of (v) with the number of
left circular shifts, k, which would be necessary to return (A) to
its original position.
75jnw: REPEAT (RPjnw): This instruction calls for the next instruction,
which will be called NIuv, to be executed n times, its "u" and nv tt
addresses being modified or not according to the value of j. Normally n executions are made and the progra~ is continued by the
execution of the inst~uction stored at a fixed address FI, 00000 or
40001. The procedure is:
PX 35
5
HEPERTOIHE OF INSTRUCTIONS
(1)
Replace the right-hand 15 bits of (Fl) with the address w
(2)
Execute
(3)
If
If
If
If
(4)
On completing n executions, take (Fl) as the next instruction.
(5)
If the repeated instruction is a jump or stop instruction, the
occurrence of a jump or stop terminates the repetition. In addition, if NIuv is a Threshold Jump or an Equality Jump, and the
jump to address v occurs, (Q) is replaced by the quantity, j,
n-r where r is the number of executions that has taken place.
NIuv, the next instruction in the program n times
j = 0, do not change u and v
j = 1, add one to v after each execution
j = 2, add one to u after each execution
j = 3, add one to u and v after each execution.
The instructions MPuv and MAuv use the Multiply Sequence explained in the
section General Description, Arithmetic Operations. Note the overflow indication feature of the Multiply Add instrw~tion.
If an overflow (into the signbit stage, A71) of the sum of the product of u and v and the c~rrent cOntent
of A is possible, a computer fault is incurred. The computer fault is indicated by the illumination of a light on the Supervisory Control Panel.
The Divide instruction use~ the Divide Sequence, also explained in the
section General Description, Arithmetic Operations.
The Scale Factor instruction is useful in ttnormalizing" a number, i.e.,
scaling a number to its maximum representation in 36 stages so that the most
significant bit is held in the stage adjacent to the stage holding the sign bit.
The Repeat instruction is an Extremely useful feature of the computer.
Consider, for example, its effectiveness in performing a "block" transfer, i.e.,
the transfer of a group of words from their storage at one set of consecutive
locat ions to another set of consec;utive locat ions.
The instruct ion Transmit
Positive (TPuv) causes the word at, address u to be transmitted to address v.
The simple two-instruction routin€~
RP
TP
3,n
ul
Transfer n words (Ul)~ vI'
(u2) -+- v2, ••• , (un) -..... vn
effects a block transfer of n worc[s from register ul through un to registers
vI through v n • If the transmission are from registers ui in Magnetic Drum
Storage to registers vi in Rapid tlccess Storage, the transfer rate is about
31,000 words per second.
Another example of the effectiveness of the Repeat instruction is provided
by its use preceding a Multiply Acld instruction to form the product accumulation
of a l b l + a2 b2 + a3 b3 + an bn •
f. ONE-WAY CONDITIONAL JUMP INSTRUCTIONS. - These instructions acquire a
word from the location specified 11Y the u address and, if a condition involving'
this word is satisfied, effect a jump to the instruction at the location specified by the v address.
PX 35
6
REPERTOIRE OF INSTRUCTIONS
The instructions are as follows.
4luv:
INDEX JUMP (IJuv): Form in A the diff"erence D(u) minus one. Then
if a7l is one, continue the present sequence of instructions; if a7l
is zero, replace (u) with (AR) and take (v) as NI.
42uv:
THRESHOLD JUMP (TJuv): If D(u) is greater than (A), take (v) as NI;
if not, continue the present sequence. In either case, leave (A) in
its initial state.
43uv:
EQUALITY JUMP (EJuv): If D(u) equals (A), take (v) as NI; if not,
continue the present sequence. In either case leave (A) in its
initial state.
Note- that a positive quantity acquired from u by the Index Jump instruction,
and decreased by the value of one, is retur-ned to storage in u until the quantity becomes negative. This provides a means of "counting", and (u) is sometimes referred to as a "counter".
This feature is extremely useful in performing an iterative cycle which is to be repeated a prescribed number of times.
The instructions TJuv and EJuv are made more useful by the feature which
leaves the content of A in its initial state after the comparison tests' are made.
g~
TWO-WAY CONDITIONAL JUMP INSTRUCTIONS. - These instructions use both the
, u- and v-addressed portions of the instruction to specify an instruction to be
executed next. the direction of the jump depends on the condition of a quantity
which is tested in the Accumulator or the Q Register. Since either the u and
v address is available to be used as an acquisition address, the ,quantity must
be placed in A or Q previous to the execution of one of these jump instruction$.
These instructions are ts follows.
44uv:
Q' JUMP (QJuv): If q35 is one, take (u) as NI; if q35 is zero, take
(v) as NI. Then, in either case, left circular shift (Q) by one
place.
46uv:
SIGN JUMP (SJuv):
take (v) as NI.
4'7uv:
ZERO JUMP (ZJuv): If (A) IS not zero, take (u) as NI;
zero, take (v) as NI.
If a7l is one, take (u) as NI;
if a 7l is zero,
if (A) is
Note that a zero condition (of q35' a 7l , or the content of A) always causes
a jump to the v-addressed instruction.
,
h. ONE-WAY UNCONDITIONAL JUMP INSTRUCTIONS. - This group of instructions
does not depend upon some condition being iatisfied by a machine word to cause
a jump.
The instructions are as follows.
14--:
INTERPRET (IP--): Let Y represent the address from which CI was
obtained. Replace the right-hand 15 bits of (F l ) with the quantity
Y + 1. Then take (F 2 ) as NI.
PX 35
7
REPERTOIRE OF INSTRUCTIONS
37uv:
RETURN JUMP (RJuv): Let y represent the address from which CI was
obtained. Replace the rj.ght-hand 15 bits of (u) with the quantity
y + 1. Then take (v) as NI.
45jv:
M~NUALLY
SELECTIVE JUMP (MJjv): If the number j is 0, take (v) as
NI. If j is 1, 2, or 3, and the correspondingly numbered MJ
selecting switch on the control panel is ~et to "jump", take (v) as
NI; if this switch is not set to "jump", continue the present
sequence.
Note that the jump instituted by the Manual Jump instruction with a j of
1, 2, or 3 is conditional with regard to a manual selection.
The Return Jump instruction pro\'ides a means of (1) interrupting the
sequence of instructions being executed currently and (2) returning to this
sequence after jumping out of it.
This is effected if the instruction at u is
a Manual Jump instruction, and it if; executed at some time following the execution of the instruction at v.
The execution of the Interpret
F~
Return Jump with u FI and v
=
=
~~nstruction
is equivalent to executing a
i. EXTERNAL EQUIPMENT INSTRUCTIONS. - The following instructions provide
for input to and output from the cortputer. Input information is transmitted to
the location specified by the v add]~ess of an input instruction; during output
operations, the information to be 1~ransrnitted to external equipment is acquired
from the v-addressed location. The use of these instructions is explained in
detail in the section of this· volume, Input and Output Systems.
The instructions are as follows"
61-v:
PRINT (PR-v): Replace (TWR) with the right-hand six bits of (v).
Cause the typewriter to perform the operation specified by the 6-bit
code.
63jv:
PUNCH (PUjv): Replace (HPR) with the right-hand six bits of (v).
Gause the punch to respond to (HPR). If j = 0, omit seventh level
hole, if j = 1, include :;eventh level hole.
17-v:
EXTERNAL FUNCTION (EF-v): As indicated by (v) select a unit of
external equipment and instruct it to perform the designated function.
'16jv:
EXTERNAL READ (ERjv):
and zeros in v3S ••• v8;
77jv:
EXTERNAL WRITE (EWjv): If j =: 0, replace (IDA) with the right-hand
eight bits of (v), if j ::: 1, replace (lOB) with (v).
j = 0, replace (v) with (lOA) in v7 ••• vO
if j =: 1, replace (v) with (lOB).
1:[
PX 35
REPERTOIRE OF INSTRUCTIONS
j. STOP INSTRUCTIONS. - The following instructions cause a stop of
computer operation and are self-explanatory:
56jv:
MANUALLY SELECTIVE STOP (MSjv): If j is 0, stop computer operation,
indicating the stop by the illumination of a light on the Supervisory Control Panel.
If j is 1, 2, or 3 and the correspondingly
numbered MS selecting switch is set to ttstoptt, stop computer operation, indicating the stop by the illumination of "a light on the
Supervisory Control Panel. Whether or not a stop occurs, (v) is NI.
57--:
PROGRAM STOP (PS--): Stop computer operation, indicating the stop
by the illumination of a light on the Supervisory Control Panel.
PX 35
9
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
In the following pages the instructions are presented with their representative octal operation codes in numerical order. The purpose of this
presentation is to give the programmer a simplified representation of the
detailed operations which the computer performs during, and necessary to, the
execution of each instruction. The events listed under each instruction occur
as a result of the c9ntrol section receiving and sensing the operation code of
the instruction. These events do not necessarily designate a machine.operation
but represent the actions taken by the machine in executing an instruction.
The order in which these events are listed is in accordance, for the most part,
with the time-wise sequence of machine operations which they represent. In
some instructions the desire for a simplified presentation overruled the desire
for a sequential presentation if such was not necessary for accuracy in determining the contents of the various registers at any time during the execution
of the instruption. The deviations from machine operation sequences in any of
the presentations do not cause a misrepresentation of th"e actual operations of
the machine.
The columns in which the events are listed differentiate the events in accordance with their primary function in the execution of the instruction. An
event listed in the Procurement of Operands column brings an operand out of
storage (MC, Mfr, Q. or A) into the X Register in preparation for some operation
upon it or placement in another register. An event listed in the Operations
column may describe arithmetic and/or logical machine operations or may be the
clearance of a register in preparation for such operations. An event listed
in the third column, Storage of Results, indicates the final placement of a
result of actions described in the first and/or second columns.
The symbols and abbreviations used in the presentation of the instructions
have been listed previously except for those listed below. The definitions
of the following notations do not explain machine operations but the effect of
machine operations.
C1ear A R e pIa c e
Clear X
Replace
Complement PAK Replace
Complement X Replace
F l---=~ PAK
jn~PAK
PAK~X
the
the
the
the
con ten t s 0 f e a c h s tag e 0 f the A( C urn u1a tor wit h a z er o.
contents of each stage of the X Register with a zero.
contents of each stage of PAK with its complement.
contents of each stage of X with its complement.
Replace the contents of the 15 stages of the Program Address
Counter with the MC or MD storage address as designated by
u or v.
A special case of the above with the MC address specified as
being octal 00000, (or MD address 40001).
Replace the contents of the 15 stages of PAK with the bits
designated as jn.
Replace the contents of the 15 stages of PAK with the contents
of the right-most stages of the X Register.
Replace the contents of the 15 right-most stages of the X
Register (X ... X )' with the address held in PAK.
o
14
PX 36
1
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
w~X
(IDA )-+-X
(IOB)+X
(PAK)~X
Replace the contents of the 15 right-most stages of the X
Register, (X 14 ... X ), with the address designated as w.
o
Replace the contents of the right-most stages of the X
Register with the shift count k.
Replace the contents of the eight right-most stages of X
with (IDA).
Replace the contents of the 36 stages of X with (lOB)
Replace the contents of the 36 stages of X with the contents
of the address held in PAK.'
(u)-+X
If u is an Me or MD address, replace the contents of the X
Register with the contents of the MC or lVlD location specified
by u.
If u is an address of the Q Register, replace the contents of
the X Register with the contents of the Q Register. If u is
an address of the Accumulator, replace the contents of the
X Register with the contents of AR Inless otherwise noted.
If v is the address of an MC or MD location or Q or A, replacement operations occur as above with v being the transmitting register.
( X)~IOA
Replace the contents of the eight stages of lOA with the
contents of the right-most eight stages of the X Register.
Replace the contents of the 36 stages of lOB with the contents
of the X Register.
Replace the contents of the 36 stages of PCR with the contents
of the X Register.
(X)-+ lOB
(X)-. u
If u is an MC or MD address, re~lace the contents of the MC
or MD location specified by u with the contents of the X
Register.
If u is an address of the Q Register, replace the contents of
Q with the contents of the X Register.
If u or v is an address of the Accumulator, replacement
operations do not occur except in instructions 11, 12, 13,
22, 55, 73, and 76. In these instructions, the replacement
is performed by Clear A and Add D(X) to A. A replacement
operation (X) ........ A occurring in the instructions not listed
above would effect undesirable alterations in the contents of
A.
If v is the address of an MC or MD location or Q or A, replacement operations occur as above with v being the receiving
register.
If the receiving r,~gister has an MC or MD address, replace
with the contents of the stages Xn .•. Xn l only the contents
of the correspondiBg stages of the 2 receiving register,leaving
the remaining stagl~s undisturbed. A partial replacement of Q
or A is not permissible.
A special case of the above with the stages of X being specifiel as being the :right--most 15 and the MC address specified
as being 00000 (or MD address 40001).
PX
~36
2
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
The contents of the transmitting register are not disturbed in any of the above
replacement operations.
It should be remembered that the Add D(X) to (A) and Add S(X) to (A)
operations cited are performed machine-wise by complementation and subtraetion.
PX 36
3
SEQUENTIAL PRESEyrATION OF INSTRUCTIONS
Instruction Reference Events
The events listed below normally conclude the execution of all computer
instructions, except the Repeat instruction, when they are not immediately
preceded by the Repeat instruction. Also, a number of instructions which are
preceded by the Repeat instruction are terminated by these events. (Refer
to the Repeat instruction and the Termination of a Repeat Sequence.) It is
understood that these events follow in sequential order the events listed
for each appropriate instruction. As a result, the execution of the current
instruction is terminated, and the cDmputer is prepared for the execution of
the next instruction whose address is acquired from PAK, the Program Address
Counter. This address is determined according to the function of the current
instruction if this function indicates that the normal sequence of instructions be interrupted. The contents Df the location whose address is held in
PAK is placed in PCR, the Program Control Register, where it is interpreted
as the next instruction to be executed.
OPERATIONS
PROCUREMENT
OF OPERANDS
-----::::
STORAGE
OF RESULTS
d
( PAK~·X
Advance PAK by one
<.
Interrupt Termination Sequence
The Pr 0 9ram I nt err up t f eat ureo f the 1] n i v a c Sci en t i f i cpr 0 v ide s "a me a ns "0 f
interrupting the usual acquisition of instructions as depicted above. When the
"interrupt" becomes effective, the first two events listed above do not occur;
instead the first instruction which is normally terminated by the instruction
reference events above is terminated by the following events:
(00002 }-.... X
(X)~
PCR.
These steps set the instruction at F3 (00002) into peR as the next instruction
to be executed and leave the address of the instruction normally executed next
in PAK. If the instruction at F3 is a Return Jump instruction, the address at
PAK is stored at some appropriate computer location u before the jump to the
v address of RJuv is made.
If the Repeat instruction, or an instruction preceded by the Repeat instruction, is being executed when the "interrupt" is selected, the events above terminate the instruction stored at Fl unless a jump (or stop) is called for during the Repeat Sequence. If this IS the case, the events above terminate the
jump instruction, and the address to which the jump was to be made remains in
PAK.
PX 36
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
11
Transmit Positive, TPuv
Replace (v) with (u)
PHOCUREMENT
OF OPERANDS
OPERATIONS
STORAG,E
OF RESULTS
(u)~X
(X)---+v
If v is A
Clear A
Add D(X) to
PX 36
5
(A)
SEQUENTIAL PRESENrATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
12
Transmit Absolute Magnitude, TMuv
Replace (v) with the absolute magnitude of (u)
PROCUREMENT
OF OPERANDS
OPEEATIONS
STORAGE
OF RESULTS
Complement (X) if negative
(X)-+-v
If vis A,
Clear A
Add D(X) to (A)
PX 36
6
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
13
Transmit Negative, TNuv
Replace (v) with the complement of (u)
-PROCUREMENT
OF OPERANDS
OPERATIONS
STORAGE
OF RESULTS
(u)~X
Complement (X)
(x)~v
If v is A,
Clear A
Add D(X) to
PX 36
7
(A)
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
14
Interpret, IP
Let Y represent the address from which CI was obtained.
the right-hand 15 bits of (Fl) with the quantity Y + 1.
take (F2) as the next instruction.
Replace
Then
Fl is storage address COOOO, F2 is storage address 00001.
PROCUREMENT
OF OPERANDS
OPE RAT I O:\JS
Clear X
PAK (i.e., Y +
1)~X
Set PAK to F2
PX 36
o
STORAGE
OF RESULTS
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
INSTRUCTION:
FUNCTION:
Transmit U Address, TUuv
Replace the 15 bits of (v) designated by (v29 ... v15) with the
corresponding bits of (u), leaving the remaining 21 bits of (v)
undisturbed.
PROCUREMENT
OF OPERANDS
OPERATIONS
STORAGE.
OF RESULTS
(u)-~X
(X29· .. X15)---+ v
v = Q or A
not permissible
PX 36
9
SEQUENTIAL
PRESEI~TATION
OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
16
Transmit V Address, TVuv
Replace the right-hand 15 bits of (v) dEsignated by (V14 ... VO)
with the correspondinu bits of (u), leaving the remaining 21 bits
of (v) undisturbed.
----
PROCUREMENT
OF OPERANDS
1--------------
-----------.--------------r------------.
OPEFATIONS
STORAGE
OF RESULTS
----------..---------------+----------~
(u) -+X
(X14.· .XO)-+v
v = Q or A
not permissible
PX
~-)6
10
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
17
External Function, EF-v
As indicated by (v) select a unit of external equipment and instruct it to perform the designated function.
PROCUREMENT
OF OPERANDS
OPERATIONS
(v)~X
If previous operations involving
(lOB) are completed (X) ~IOB
According to (lOB).
select external equIpment
and instruct it to perform
a function.
PX 36
11
STORAGE
OF RESULTS
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
21
Replace Add, HAuv
Form in A the sum of D(u) and D(v).
PROCUREMENT
OF OPERANDS
OPERATIONS
Then replace (u) with (AR)·
STORAGE
OF RESULTS
Clear A
Add D(X) to
(A)
Add D(X) to (A)
L ____
(X)-+ u
Omit if u is A
PX :36
12
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION,:
22
Left Transmi t, LTj kv
FUNCTION: Left circular shift (A) by k places, k being u6 •.• uO. Then replace
(v) with (AL) if j=O, or replace (v) with (AR) if j=l.
PROCUREMENT
OF OPERANDS
OPERATIONS
STORAGE
OF RESULTS
Shift (A) left k places
If j is 0, (AL)
~
X
If j is 1, (A R)
~
X
X~v
If v is A
Clear A
Add D where they are
present in corresponding
(X5· •• XO)
Perform typewrit.er operation as
specified by (TWR).
40
STORAGE
OF RESULTS
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERAT ION CODE:
6:3
INSTRUCTION:
Punch, PUjv
FUNCTION:
Replace (HPR) with the right-hand six bits of (v). Cause
the punch to respond to (HPR). If j = 0, omit seventh
level hole; if j = I include seventh level hole.
PROCUREMENT
OF OPERANDS
STORAGE
OF RESULTS
OPERATIONS
-(v) -+X
If HPR is clear, place a
HPR6 if j = 1 and place
(HPRS ..• HPRO) where they
present in corresponding
Punch (HPR)
PX 36
41
one in
ones in
are
(XS· · · XO)
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
71
INSTRUCTION:
Multiply, MPuv
FUNCTION:
Form in A the 72-bit product of (u) and (v), leaving in Q
the multiplier (u).
PROCUREMENT
OF OPERANDS
OPERATIONS
(u)~X
Clear A
(X)-~Q
(v) ~x
Form in A the product of (Q) and
(X)
PX 36
42
STORAGE
OF RESULTS
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
72
INSTRUCTION:
Multiply Add, MAuv
FUNCTION:
Add to (A) the 72-bit product of (u) and (v), leaving in Q
the multiplier (u).
PROCUREMENT
OF' OPERANDS
OPERATIONS
STORAGE
OF RESULTS
-(Ul)---+X
(X)~Q
Shift (A) left 36 places
(v)~X
Add to (A) shifted the product
of (Q) and (X)
--
PX 36
43
SEQUENTIAL PRESE\JTATION OF INSTRUCTIONS
OPERATION CODE:
73
INSTRUCTION:
Divide, DVuv
FUNCTION:
Divide the 72-bit nL.mber in A by eu), putting the quotient in
Q, and leaving in A a non-negative remainder, R. Then replace
(v) by (Q). The quctient and ~emainder are defined by
( A) i = (u). ( Q) +R wh ere 0 ~ R < I( u) I. (A ) ide not est he
initial contents of A.
PROCUREMENT
OF OPERANDS
STORAGE
OF RESULTS
OPERATIONS
(u) - + X
Clear Q
Divide (A) by (X), placing the
quotient in Q and leaving R in A
(Q) -+X
J
______
_
(X)~v
If v is A,
Clear A
Add D(X) to
_ _ _ _ _ _ _ _
PX 36
44
(A)
------L.---~
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
74
INSTRUCTION:
Scale Factor, SFuv
FUNCTION:
Replace (A) with D(u) unless u is A. Then left circular shift
(A) 36 places and continue shifting until a35 ~ a34. Replace
the righthand 15 bits of (v) with the number of left shifts,
k, necessary to return the final contents of A, or (A)f, to
the original position. The range of k if u is A is O~ k ~~ 71 .
if u is MC, MD, or Q, k may be 0 or 37S k S 71. Effectively,
the initial contents of A, or (A)i, which may be D(u) or D(Q)
after the above replacement, are positioned in AR (with the
sign bit represented by A35 and the most significant bit by
A34) so that (A)f = (A)i.2S. If OSkS36, the Scale Factor
s = -k; if 37S k S 71, s = 72 -k. Note that for 0 < k S 36,
thi s posi t ioning scales (A) i "down"; for 37S k ::= 71, (A) i
are scaled "up". If k = 0, (A)i were properly positioned
before any shifting operations; if k = 37, (A)i are all
ones or zero.
I
PROCUREMENT
OF OPERANDS
OPERATIONS
STORAGE
OF RES ULTS
Clear X
(u)~ X
Omit if u is A
Clear A
Omit if u is A
Add D(X) to A
Shift (A) left 36 places and
continue shifting until a35 ~ a34
Clear X
k~X
(X14 ... XO) -~v
v = Q or A not
permissi ble
PX 36
45
SEQUENTIAL PRESE~TATION OF INSTRUCTIONS
OPERATION CODE:
75
INSTR UCT I ON:
Repeat, RPjnw
FUNCTION:
This instruction calls for the next instruction, NIuv, to be
executed n times, 0~;n~2.L2-1, its u and v addresses
being modified or not according to the value of j. Normally
n executions are made, and the program is continued by the
execution of the instruction stored at a fixed address Fl·
The instruction usually stored at FI is MJjv, calling for a
jump to its v address, which according to the workings of the
Repeat instruction means that (w) of RPjnw will be taken as
the next instruction t~ be executed.
The u and v addresses of the repeated instruction are advanced
according to the value of j as follows.
If j = 0, neither the u nor the v execution address of
the repeated instruction is advanced.
j = 1, the
v execution address of the repeated instruction is advanced after each execution.
j = 2, the u execution address of the repeated instruction is advanced after each execution.
j = 3, both the u and v
execution addresses of the
repeated instruction are advanced after each
execution.
During a repeat sequence, PAK is used as a counter to record
the number of times the instruction is executed.
PROCUREMENT
OF OPERANDS
DPERATIONS
Clear X
W~X
(PAK)
jn
-~
~
X
PAK
Complement PAl(
(X) -+ peR
Begin Repeat !iequence:
Advance (PAID and investigate
its content!;.
If n = 0, pl~oceed to Normal
Rt~peat Termination
If n :f 0, execute NI n times,*
advancing u and v addresses according to j
*See Exceptions, discussed later.
PX 36
46
STORAGE
OF RESULTS
SEQUENTIAL PRESENTATION ,OF INSTRUCTIONS
Intermediate Steps following each execution of an instruction whose repeat is
possible.
FUNCTION:
Test for n executions of repeated instruction. Proceed to Normal
Repeat Termination if n executions have occurred. If not, repeat
instruction.
PROCUREMENT
OF OPERANDS
OPERATIONS
STORAGE
OF RESULTS
Advance PAK by one
Test PAK for condition indicating
n executions of repeated instruction and proceed accordingly.
Normal Repeat Termination
FUNCTION:
ExceptiOI:J
Terminate the repeat sequence when an instruction has been executed
n times by taking (F l ) as the next instruction. (See
(F l)---'X
(X)~PCR
I
Abnormalities:
1. If the fixed address Fl is not a Jump instruction, the address of the
instruction to be executed fol owing the instruction stored in Fl is determined
by the modified complement of j from the Repeat instruction. Thls is the
number that remains stored in PAK at the end of a repeat sequence that has a
Normal Termination. If, in 75jnw, j was 0, the address will be 40000; if j
was 1, the address will be 70000; if j was 2, the address will be 60000; if
j was 3, the address will be 50000.
2..
In addition to values j = 0, 1, 2, and 3, the value j in 75jnw may also
be 4, 5, 6, or 7. An· instruction following a Repeat instruction where j = 4, 5,
6, or 7 will be repeated indefinitely unless its execution produces a jump or
stop operation or a jump termination. If these latter conditions do not occur
the u and v execution addresses of the repeated instruction will be advanced
depending on j; if j = 4, neither address is advanced; if j = 5, the v address
is advanced; if j = 6, the u address is advanced; if j = 7, both addresses are
advanced. If u or v are MD addresses, they may be advanced from 40000 through
77777, and the next advance signal after 77777 will start the address sequence
over from 40000. If u or v are MC, Q, or A addresses, they may be advanced 4095,
511 and 511 addresses from their respective first addresses, and the next advance signal will start their address sequence over from their respective first
address.
3. If a Repeat instruction is immediately followed by a second Repeat instruction, the second will supersede the first, and the address of the repeated
instruction is determined by the number stored in PAK. This address is the
complement of "jn-l" which remains stored in PAK from the first Repeat instruction.
PX 36
47
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
TERMINATION OF A REPEAT SEQUENCE
The first step of the Repeat Sequence is to determine whether the value of
n in the Repeat instruction is zero or not. If n is zero (indicating that no
execution of the instruction following the Repeat instruction is to be made),
the attempted Repeat Sequence is immediately terminated according to the Normal
Repeat Termination. If n f:. 0, the instruc:ion, regardless of what it is, is
executed. The Repeat Sequence is concluded by a Normal Repeat Termination,
after n executions, except when the instruction following RPjnw is one of the
following.
Exceptions:
(1) If the Interpret (14--), Return Jump (37uv), Q Jump (44uv), Sign Jump
(46uv), Zero Jump (47uv), Manually Selected Stop (56jv), or Program Stop (57--)
instruction is to be executed after a Repeat instruction, the attempted Repeat
Sequence is automatically terminated. These instructions are thus executed as
if no Repeat instruction preceded them and terminated by the normal Instruction
Reference Events.
(2) If either the Index Jump (4Iuv) or Manually Selected Jump (45jv) is
to be executed following a Repeat instruction, they may be repeated n times
as specified if no jump operation is called for in the course of their execution. If a jump operation is called for, :he instruction is terminated according to the normal Instruction Reference Events, and the content of the jump
address is taken for the NI. (No count of the number of times the instruction
was executed is retained, however.) If no jump operation is called for in n
executions of these instructicins, a Normal Repeat Termination is executed and
(F )
is taken for the NI.
l
(3) If either the Threshold Jump (42uv) or the Equality Jump (43uv) is to
be executed following a Repeat instruction, they can be repeated or not depending on whether or not in their execution the threshold or equality conditions
are reached and a jump operation is called for. If a jump operation is called
for before or exactly after n executions, the Repeat Sequence of these instructions is term:inated by a' special Jump Termination (see the following page.
Note that the Jump Termination is followed by the normal Instruction Reference
Events.) The Jump Termination stores the quantity j, n-r in Q and takes the
contents of the jump address for the ~I. The (Q) can then be used to determine
how many times the instruction was executed. If n executions of these instructions are performed and the threshold or equality conditions requiring a jump
do not occur, the repeat sequence of these instructions is terminated by the
Normal Repeat Termination and (F l ) is taken for the NI.
(4) If the "interrupt" is selected during the execution of a Repeat instruction or an instruction being repeated, the Interrupt Termination sequence
concludes the execution of those instructions in paragraphs (1), (2) and (3)
above which are stated to be concluded by the normal Instruction Reference
Events. When the content of FL is taken as the next instruction, the Interrupt
Termination sequence concludes the execution of the instruction at Fl.
The Interrupt Termination sequence referred to is found on the page listing
the normal Instruction Reference Events.
PX 36
4U
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
Jump Termination for repeated instructions 42uv and 43uv.
FUNCTION:
When a jump condition, as specified by one of the instructions
above, is reached before or immediately after n executions, the
steps listed below, followed by the normal Instruction Reference
Events, terminate the execution of the instruction.
PROCUREMENT
OF' OPERANDS
OPERATIONS
(PAK)--+X
(X)--+Q
v--+PAK
PX 36
49
STORAGE
OF RESULTS
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
76
External Read, ERjv
If j = 0, replace (v7 ... YO) with (lOA) and (v35 ... v8 ) with zeros;
if j = 1, replace (v) witl (lOB). (This instruction must be preceded by an External Function instructing the equipment to transmit
information to lOB.)
PROCUREMENT
OF OPERANDS
OPERATIONS
STORAGE
OF RESULTS
Clear X
If IDA or lOB has received informat:Lon from external equipment
(IDA) or (IOB)--..X
Clear lOA or lOB
(X)--.v
If v is A,
Clear A
Add D(X) to A
If lOA is involved, note that when v is a 36-bit register, the eight right-most
bits of v are (lOA) and the left-most 28 bits are zeros; when v is A, the
eight right-most bits of A are (lOA) and the remaining 64 bits are zeros.
PX 36
50
SEQUENTIAL PRESENTATION OF INSTRUCTIONS
OPERATION CODE:
INSTRUCTION:
FUNCTION:
External Write, EWjv
If j = 0, replace (lOA) with the right-hand eight bits of (v); if
j = 1, replace (lOB) with (v). Notify external equipment of this
transmission to lOA or lOB. (This instruction must be preceded by
an External Function. instructing the equipment to sense the information from lOA or lOB.)
PROCUREMENT
OF OPERANDS
OPERATIONS
(v) --'X
If previous operations involving
(lOA) or (lOB) are completed or lOB
Transmit (lOA) or (lOB) to
external equipment
(X)~IOA
PX 36
51
STORAGE
OF RESULTS
77
INSTRUCTION EXECUTION TIMES
, OPERATION CODE:
INSTRUCTION:
Q-Jump, ,QJuv
Sign Jump, SJuv
NON-REPEATED
u
REPEATED*
or v
u or v
MC
9
MC
3
A
sec
A
SCC
Q
Q
OPERATION CODE:
INSTRUCTION:
Manual Jump, MJjv
NON-REPEATED
v
I
MC
A
9
SCC
REPEATED~~
v
Q
MC
I
A
SCC
3
JUMP
v
44
46
JUMP~:~
irrelevant
v
9
irrelevant
5N
NO JUMP
NO JUMP
*See preliminary discussion
PX 37
13
Q
45
INSTRUCTION EXECUTION TIMES
On the following pages the instructions are presented with accompanying
tables which give the time required for the execution of each instruction, the
execution being repeated or not repeated. The time required for the execution
of an instruction is dependent upon the storage references, where such are
made, by the u and/o'r v addresses. The tables for the instructions, with such
references applicable and practical, list individually the execution tImes of
each instruction with its u and/or v addresses referencing an MC register, the
Accumulator, or the Q Register. (All execution times assume that the instructions are stored in MC.) The specified times are measured, unless otherwise
stated, from MPO to MPO. Each number in a table is the number of clock ..Q.ulse
periods (two microseconds each) required for the execution of a particular coded
instruction.
Included in the determination of the computer time for an instruction repeated n times are the times required by the Repeat instruction and, in most
cases, the instruction stored at Fl. This total time is given by the sum,
27+R +p, where Rn is the execution time of the instruction repeated n times and
p isnthe execution time of the instruction stored at Fl. If n is zero, R is
zero and, in all cases, the total computer time is 27 + p and the next in~truc
tion is taken from Fl.
When certain of the instructions are repeated, the total computer time does
not include the time p. These instructions are Interpret 14--; Return Jump,
37uv; Q-Jump, 44uv; Sign Jump, 46uv; Zero Jump, 47uv: Manually Selective Stop,
56uv; and Program Stop, 57--. These instructions are executed only once at t~
most regardless of an n 1. The next instructions to be executed will not be
taken from Fl.
Other exceptions to including the time p in the total computer time are
made under certain conditions when the following instructions are repeated:
Index Jump, 41uv; Manually Selective Jump, 45jv; Threshold Jump, 42uv; and
Equality Jump, 43uv. The time p is not added when, during the repeated n
executions of these instructions, the jump requirement is met before or during
the nth execution of the instruction. The occurrence of the jump eliminates the
procedure of taking the next instruction to be executed from Fl·
Execution times for repeating certain of the instructions are not given if
a repeat of such instructions has no practical use.
The following notations are used in the tables of execution times.
SCC
Storage Class Control indicates the coded u and/or v
addresses being used are not permissible.
Execution time not given for a possible instruction
at a Q address.
PX 37
1
INSTRUCTIOI~
N
EXECUTION TIMES
Number of executions of the repeated instruction.
(Ui)
Denotes bit in stage i, (:35
addressed as u.
(Ui)j
Contents of ui
ms
Milliseconds.
d~ring
~
i
~
0), of register
repeat j, j = I ... N.
.?X 37
2
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
11
Transmit Positive, TPuv
INSTRUCTION:
REPEATED
NON-REPEATED
v
MC
A
Q
MC
19
17
15
MC
12N+l
A
15
14
12
A
8N +1
Q
16
15
13
Q
9N +1
MC
OPERATION CODE:
INSTRUCTION:
Transmit Magnitude, TMuv
NON-REPEATED
REPEATED
v
v
u
MC
A
Q
u
MC
MC
19
18
16
MC
12N+1
A
16
15
13
A
9N+l
Q
17
16
14
Q
10N+l
PX 37
3
12
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
13
Transmit Negative, TNuv
NON-REPEATED
REPEATED
v
MC
A
Q
u
MC
19
17
15
MC
A
15
14
12
A
8N+l
Q
16
15
13
Q
9N+1
MC
12N+l
OPERATION CODEINSTRUCTION:
Interpret, IP-NON-REPEATED
u and v irrelevant
15
PX 37
4
14
INSTRUCTION EXECUTION TIMES
OPERATION CODE::
INSTRUCTION:
15
16
Transmit U Address, TUuv
Transmit V Address, TVuv
NON-REPEATED
REPEATED
MC
A
Q
MC
19
see
see
Me
A
15
sce
sec
A
8N+l
Q
16
see
see
Q
9N+l
MC
12N+l
A
Q
see
see
1
OPERATION eODE:
INSTRueTION:
External Function, EF-v
NON-REPEATED
Me
A
Q
14
11
12
computer operating time,
not including a lockout
time if lOB is currently
in use for output operations.
PX 37
5
17
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Replace Add, RAuv
NON-REPEATED
REPEATED
Me
A
Q
30
27
28
MC
A
23
20
21
A
18N
Q
25
22
23
Q
19N
MC
21
MC
A
Q
23N+l 20N+l 21N+l
OPERATION CODE: 22
INSTRUCTION:
Left Transmit, LTjkv
NON-REPEATED
REPEATED
j
16+k 15+k
MC
v
MC- - -A- - Q- - - -v- - 13+k
(9+k)N+l
OPERATION CODE:
INSTRUCTION:
Replace Subtract, RSuv
NON-REPEATED
REPEATED
MC
A
Q
MC
:n
28
29
MC
A
24
21
22
A
19N
Q
26
23
24
Q
20N
MC
PX 37
A
Q
24N+l 21N+l 22N+l
23
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Controlled Complement, CCuv
NON-REPEATED
REPEATED
MC
A
Q
MC
26
23
24
MC
A
19
16
17
A
14N
Q
21
18
19
Q
15N
MC
A
Q
19N+l 16N+l 17N+l
OPERATION CODE:
INSTRUCTION:
27
Split Positive Entry, SPuk
Split Add, SAuk
NON-REPEATED
MC
16 + k
A
13 + k
Q
14 + k
REPEATED
MC
(10 + k) N
where k is not altered by
the Repeat Sequence. For
k=O and 1 use value of
k=2.
PX 37
7
31
32
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Split Negative Entry, SNuk
Split Subtract, SSuk
NON-REPEATED
MC
17 + k
A
14
Q
15 + k
REPEATED
MC
+ k
(11 + k) N
where k is not altered by
the Repeat Sequence. For
k=O and 1, use value of
k=2.
OPERATION CODE:
INSTRUCTION:
33
34
Add and Transmit, ATllV
NON-REPEATED
REPEATED
MC
MC
22
18
19
A
19
15
16
Q
20
16
17
PX 37
A
MC
15N+1 13N
A
12N+1
Q
13N+ 1
Q
13N
35
INSTRUCTION EXECUTION TDIES
OPERATION eODE:
36
Subtract and Transmit, STuv
INSTRUCTION:
REPEATED
NON-REPEAT
Me
Me
A
Q
A
Me
23
19
20
Me
16N+l 14N
A
20
16
17
A
13N+l
Q
21
17
18
Q
14N+l
Q
14N
OPERATION eODE:
Return Jump, RJuv
INSTRUeTION:
NON-REPEATED
Me
A
Me
18
see
A
see
see
Q
see
see
REPEATED~c
Me
A
Me
12
see
see
A
sec
see
sec
see
Q
sec
see
see
Q
OSee preliminary discussion
PX 37
9
Q
37
INSTRUCTION'EXECUTION TIMES
OPERATION CODE:
41
Index Jump, IJu\r
INSTRUCTION:
REPEATED*
NON-REPEATED
MC
A
MC
~~7
SCC
A
20
Q
22
MC
A
MC
18r+3
SCC
SCC
A
14
SCC
SCC
Q
16
SCC
Q
Q
where r = number of executions
up to the occurrence of the jump .
.JUMP~~
NON-REPEATED
REPEATED
irrelevant
irrelevant
MC
22
MC
18N
A
19
A
15N
Q
20
Q
16N
NO JUMP
*See preliminary discussion
PX 3'7
10
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Threshold Jump, TJuv
NON-REPEATED
"
42
REPEATED~:~
v
u
MC
A
MC
21
SCC
MC
15r+5
SCC
A
18
SCC
A
17
SCC
Q
19
SCC
Q
18
SCC
MC
Q
A
Q
where r = number of executions
up to the occurrence of the jump.
The jump will occur during the
first execution if u is A or Q.,
JUMP*
NON-REPEATED
REPEATED
irrelevant
irrelevant
MC
21
MC
15N
A
18
A
12N
Q
19
Q
13N
NO JUMP
*See preliminary
discu~sion
PX 37
11
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
43
Equality Jump, EJuv
NON-REPEATED
REPEATED~!~
MC
MC
A
MC
27
SCC
MC
2lr+5
SCC
A
24
SCC
A
23
SCC
-
Q
25
SCC
Q
24
SCC
-
Q
A
Q
where r = number of executions
up to the occurrence of the jump.
The jump will occur during the
first execution if u is A or Q.
REPEATED
NON-REPEATED
irrelevant
irrelevant
MC
27
MC
2lN
A
24
A
18N
Q
25
Q
19N
NO .JUMP
*See preliminary discussion
PX 37
12
INSTRUCTICIN EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Zero Jump, ZJuv
REPEATED~:~
NON-REPEATED
u or v
u or v
MC
15
MC
9
A
SCC
A
SCC
Q
Q
OPERATION CODE:
INSTRUCTION:
47
Q-Controlled Trapsmit
l
QTuv
REPEATED
NON-REPEATED
MC
A
Me
A
Q
Me
22
18
19
Me
15N+1 13N
A
19
15
16
A
12N+1
Q
20
16
17
Q
13N+-1
*See preliminary discussion
PX :37
14
Q
13N
51
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Q-Controlled Add, QAuv
NON-REPEATED
REPEATED
MC
A
Q
MC
23
19
20
MC
16N+1 14N
A
20
16
17
A
13N+1
Q
21
17
18
Q
14N+l
MC
A
Q
14N
OPERATION CODE:
INSTRUCTION:
52
Q-Controlled Substitute, QSuv
REPEATED
NON-REPEATED
Me
MC
A
Q
Me
37
30
32
Me
30N+1 25N
A
34
27
29
A
27N +1
Q
35
28
30
Q
28N +1
PX 37
15
A
Q
26N
53
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
54
Le ft S h i ft inA, LA uk
NON-REPEATED
Q
A
MC
MC
22 + k
18 + k
19 + k
A
16 + k
L6 + k
SCC
Q
18 + k
SCC
18 + k
REPEATED
MC
(15
+
k) N+1
where k is not altered by the Repea": Sequence.
*v is coded with bits v~ ••• vo repre;ienting k and bits v14 ••. v7 completing an MC,
A, or Q address. If v IS an A address, (u) shifted remain in A; if v is a Q
address, the final (AR) are transmi":ted to Q.
PX ~~7
16
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
55
Left Shift in Q, LQuk
NON-REPEATED
MC
A
Q
MC
21 + k
20 + k
18 + k
A
18 + k
18 + k
sec
Q
17 + k
sec
17 + k
REPEATED
MC
Me
(14 + k ) N+1
where k is not altered by the Repeat Sequence.
~~where v is coded with bits v6.· .v
o representing k and hi ts v14 ••. v7 completing
an Me, A~ or Q address. If v is an A address, (u) shifted are transmitted tiQ A;
if v is a Q address, (u) shifted remain in Q.
PX 37
17
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
56
Manually Selective Stop, MSjv
NON-REPEATED
Vf,C
Q
- ..._A
- - - -Q- - - - -
---
sec
9
NO STOP
v
irrelevant
-5
STOP
OPERATION CODE:
INSTRUCTION:
Program Stop, PS·--
NON-REPEATED
u and v irrelevant
u and v irrelevant
-6
1
*See preliminary discussion
PX
~i7
1U
57
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Print, PR-v
Punch, PUjv
NON-REPEATED
v
61
63
REPEATED
MC
A
Q
17
15
16
~
I
computer operating time,
not including a possible
lockout time due to external equipment cycle
times of Approximately 105 ms for
typewriter
16.7 ms for Punch
13N
A
Q
ION
lIN
computer operating time,
not including lockout
times due to external
equipment cycle times.
Approximate overall
times in ms:
Maximum Punch 16.7 (N-l)+12.5
Typewriter l05N
Minimum Punch 16.7(N-l)
Typewriter 105 (N-l)
(cycle times listed are
not maximum lockout times)
PX 37
19
INSTRUCTIO~I
EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Multiply, MPuv
NON-REPEATED
MC
MC
A
Q
-----------~)8
55
56
A
~)5
52
53
Q
~)6
53
54
35
+ 7 (u35 )
each plus 2(u o ) +4L (u·)
1
i=l
REPEATED
Subtract 36 from corresponding execution times
of Multiply Add instruction.
PX 37
20
71
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Multiply Add, MAuv
NON-REPEATED
Add 36 to corresponding execution times of Multiply instruction.
REPEATED
MC
A
Q
MC
88N
85N
86N
A
85N
82N
83N
Q
86N
83N
84N
Minimum times where (u3S)j
and (uO)j are zeroes and the
additional time required for
(U34 ... ul)j of ones is given
by the summation below the
table.
N ( ,LUi
34 )
each plus 4.~
J =1
1 =1
j
MC
A
Q
MC
237N
234N
233N
A
234N
23lN 232N
Q
235N
232N 233N
Maximum times where
(u35 ... uO)j are all ones.
If the contents of (u3S ... uO)j are known:
U
= MC,
v = MC
88 N +
u
= Q,
j~l
{2(UQ)j + 7(u3S) j + 4
v = Q
35
84N + N{ 2(qO) + 7(q35) + 4 ~
i=l
PX 37
21
~l
(ui) j}
72
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
Divide, DVuv
NON-REPEATED
MC
A
Q
241
240
238
REPEATED
MC
N
MC
MC
234 N + 4
2:
(a 71 )j +1
j=l
A
238
237
235
Q
239
238
236
add to each 4(a71)
Maximum time (in case of a preliminary negative remainder)
NON-REPEATED
Me
A
Q
2~m
237
235
REPEATED
MC
N
MC
MC
I
231N + 4
2:
j=l
A
2~15
234
232
Q
2~~,6
235
233
add to each 4(a71)
Minimum time
PX :37
'>
2 ,-
73
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
74
Scale Factor, SFuv
NON-REPEATED
REPEATED
if v=A or Q, SCC fault
MC
MC
+Y
MC
61
A
58 + Y
Q
1 59 +
MC
(54 + Y )N+1
y
where Y = (36-k) mod 72 and k is the scale factor 0 S k S 71.
k = 37, use value of k = 38.
For
OPERATION CODE:
INSTRUCTION
NON-REPEATED~:~
REPEATED
If the RP instruction is
repeated, the second one
takes precedence over the
first.
27 + Rn + p
where p is the execution time
of the terminal jump at Fl and
Rn is the execution time of the
repeated instruction.
(If n = 0, Rn = 0)
*See preliminary discussion
PX 37
23
75
INSTRUCTION EXECUTION TIMES
OPERATION CODE:
INSTRUCTION:
76
External Read, ERjv
REPEATED
NON-REPEATED
MC
A
Q
MC
I ~Ie::'
14
12
8N+l
computer operating time,
not including a lockout
time if lOB, or lOA, has
not yet received the information being "read".
computer operating time,
not including lockout
times.
OPERATION CODE:
INSTRUCTION:
External Write EWjv
NON-REPEATED
REPEATED
MC
A
Q
MC
A
Q
14
11
12
ION
7N
8N
computer operating time,
not including a lockout
t:ime if lOB, or lOA, is
currently in use for output ope rat ions.
computer operating time,
not including lockout
times.
PX 37
24
77
INPUT AND OUTPUT SYSTEMS
1.
GENERAL.
The Input and Output Systems of the Univac Scientific computer provide the
means of communication between the computer and the operator. To achieve this
communication three things are essential to each input or output system: a
medium for external representation of information; external equipment which is
capable of (for output) receiving information internally represented and presenting it -in its particular external medium of representation, or (for input)
sensing external information as it is represented by its particular medium of
representation and presenting it to the computer; a means of transmitting and
controlling this transfer of information between the external equipment and the
computer.
a. STANDARD EQUIPMENT. - The Univac Scientific Computer System includes
equipment which utilizes punched paper tape as a means of presenting and receiving information.
The Photoelectric Paper Tape Reader senses information
punched on paper tape and presents it to the computer; the High Speed Paper
Tape Punch receives information from the computer and presents it externally
on punched paper tape. The Electric Typewriter is used to create punched paper
tape coded to represent typewriter functions and characters. This code is presented to the computer using the tape reader. Typewriter coded information
within the computer is presented externally through the typewriter which senses
the code and performs accordingly the typewriter function.
Typed copy is prepared on standard 8 1/2 by 11 inch typewriter paper and may consist of letters,
numbers, signs or symbols, and punctuation marks, spaced in any chosen typewriter format.
Paper tape is described in rows and columns: a single column of positions
across the width of a tape is called a frame; frames are divided parallel to
the length of the tape into seven levels.
Six of these levels are used primarily to represent information to be placed in computer storage; the seventh
is used to present loading directions to the computer.
A hole punched in any
of the six lower levels represents a o~e; the absence of a hole represents a
zero.
The tape is thus coded according to binary number notation although the
digit grouping may represent decimal numbers, bioctal numbers, or typewriter
codes. If the tape is punched to represent a 36-bit operand, i35 .•. i O ' the
bits representing the word are positioned on the tape as follows:
LOADING
.
.
LEVELS
7
CODE
.
.
L35 1. 29 I. 23
1.17
L"
'-5
6
2
DIRECTION OF
00000000000
(FEED HOLES)
TAPE MOVEMENT
3
4
5
PX 38
1
INFUT AND OUTPUT SYSTEMS
As shown, six frames are needed to represent a 36-bit word.
If the word
is a bioctal-coded computer instruction, the digits punched on tape represent
the operation code and u and v addresses of the instruction as follows.
o.
'''''J~
/
',,'1;)"
/
',,~"
--------u -
C.
...... ·--·-·---v-·-----+-
_._-_._+-
---_.'~rV
. ..,:')0
/
'''~
·'..l/"
'''~
-
-
(OCTAL CODING)
/
/
.~~
-
'",t14
''vt'!"
b. OPTIONAL EQUIPMENT. - Other input and/or output equipment which is
optional with the computer system represents information externally on punched
tabulating cards, magnetic tape, or as printed copy.
c.
INFORMATION TRANSFER.
(1) INPUT OUTPUT REGISTERS. - Information transmission in and out of
the computer is performe.d as a function of coded computer instructions. It is
routed via a buffer (temporary storage) register and the X Register in its
transmission between external equipment and an addressed computer location.
The buffer registers used are determined by the selection of external
equipment for receiving or loading information.
The buffer registers are: the High Speed Punch Register, HPR; the Typewriter Register, TWR: the Input-Output Register A, lOA; the Input-Output
Register B, lOB.
Since HPR and TWR each provide communication with a specific
piece of external equipment, a discussion of these registers is included in the
discussion of the proper external equipment. The Input-Output Registers A and
B are, respectively, eight stage and 36 stage registers. They are used to provide communication between the computer and the input and/or output equipment
for which no specific buffer register has been provided.
(2) EXTERNAL INSTRUCTIONS. - Info:rmation transfer to external equipment,
via the buffer registers, is initiated by computer instructions which direct
the flow of information from an addressed computer location, via the X Register,
to the buffer register.
The presence of the information in the buffer register
allows, under the proper conditions, the external equipment to sense the content
of the buffer register and to translate this information and present it externally. Information transfer via the buffer registers from external equipment
to the computer is similarly directed by a computer instruction. The information is routed under the proper conditions from the external equipment, via a
buffer register and the X Register, to an addressed computer location.
The
information as represented externally is translated appropriately to its machine
representation.
The computer instructions which direct the flow of information are:
2
INPUT AND OUTPUT SYSTEMS
PUNCH, PUjv, operation code 63
Addressed computer location
~
X Register
~
HPR-+ Punch
PRINT, PR-v, operation code 61
Addressed computer location""':X Register -+TWR -;..Typewriter
EXTERNAL WRITE, EWjv, operation code 77
Addressed computer location
equipment
~
X Register -+ lOA or lOB -+ external
EXTERNAL READ, ERjv, operation code 76
External equipment -+ lOA or lOB -+ X l1egister -;. addressed computer
location.
Since no reference to a specific piece of external equipment is made by
the External Read and Write instructions which use the lOA and lOB buffer
registers for information transfer, a means of selecting the appropriate piece
of equipment must also be provided. The External Function instruction, EF-v,
uses the lOB register for this purpose. This instruction places ones, as
located at address v, in selected stages of lOB and directs lOB Control to
then interpret the content of lOB and to accordingly select and initiate a
function of external equipment.
EXTERNAL FUNCTION, EF-v, operation code 17
Addressed computer location ~X Register~ lOB
Initiate external equipment function according to (lOB)
(3) LOCKOUT CONDITIONS. - During the execution of each of these
external equipment instructions, a "lockout" test is made to see if a previous
use, if such is the case, of the particular register involved is completed.
This is necessary before the current instruction can be completed and before
the next instruction can be placed in computer control in readiness for its
execution. If the necessary requirements are not met, a lockout condition
exists which effectively stops computer operating time.
For output operations a lockout condition exists if the control circuitry
of the particular buffer register being referenced by the output instruction
has not yet received an indication that the register has been cleared of
previous information being routed to external equipment. The condition continues to exist, temporarily stopping computer operations, until the register
is cleared, after which the current information may be received by it (machine
operations being resumed), and the execution of the instruction completed. The
steps involved in an output operation are sequential within the groups as
listed below.
PX 38
3
INPUT AND OUTPUT SYSTEMS
Under computer control (for output)
Content of computer register ~X register
TEST FOR LOCKOUT
(X) -+ buffer register, INITIATE LOCKOUT
Under external equipment control (for output)
Sense content of buffer regi.ster
Resume signal-Clear buffer register, NULLIFY LOCKOur INITIATION or
CLEAR LOCKOUT IF ESTABLISHED
Computer operations continue after the initiate lockout step unless a
second computer output operation in,rolving the same register is begun before
the resume signals from external equipment control are received by the computer.
If this is the case, the LOCKOUT condition is ESTABLISHED and computer operation
is halted at the test lockout step. Computer operation is resumed at its stopping point when the resume signals ilre received from external equipment.
For input operations a lockout condition exists if the control circuitry
of the particular buffer register being referenced by the input instruction
has not yet received an indication t.hat the register has received the input
information from external equipment. This condition continues to exist, temporarily stopping computer operations, until the information is received, after
which computer operations are resumed and the instruction completed. The steps
involved in an input operation are ~equential within the groups as listed below.
Under external equipment control,
(for input)
Input information ~ buffer register
NULLIFY LOCKOUT IN IT IAT ION or CLEAR LOCKOUT IF ESTABLISHED
Under computer control
(for
in~,ut)
TEST FOR LOCKOUT
Content of buffer register -:~ X
Clear buffer register, INITJATE LOCKOUT
Content of X...;.. computer storage •
During input operations, a LOCKOUT condition is ESTABLISHED if the computer
instruction for input is sensed by computer control before the input information
is received by the buffer register referenced by the instruction. If the input
information is received by the buffE~r register before the execution of the input
instruction is begun, the lockout irlitiation condition (left by any previous
execution of an input instruction rE'ferencing the same register) is nullified,
and the input instruction may be eXE'cuted without lockout delay; but if an
input instruction (referencing a re{rister whose previous clearance set up a
lockout initiation condition) is attempted before input information is received
by the buffer register, a lockout is establiShed. In this case, computer operations are halted at the test lockout step and resumed when the input information
is received.
PX 3(3
4
INPUT AND OUTPUT SYSTEMS
(4) INPUT OUTPUT COMPUTER FAULTS. - Certain conditions may arise
during input and output operations which could cause erroneous transmissions
to and from external equipment. These conditions do not result in lockouts but
cause camputer,faults which halt computer operation. These faults ~esult from
operations involving the Input Output Registers A and B and are indicated on
the Supervisory Control Panel, lower left portion of the center section. Since
they are classified as Type B computer faults (explained in the section,
Operating the Computer), they are also indicated on the control panel in the
center section, lower righthand corner, as an lOB fault.
These faults, listed subsequently, are generated because of timing requirements which have not been taken into consideration or because of faulty external
equipment.
An lOB (or IDA) Read Fault, Class I, occurs if information is received by
lOB (IDA) from external equipment before the control circuitry of the register
has received a signal to dispose of information placed there during previous
input operations. In other words, if the steps
Under external equipment control (for input)
Input information~ buffer register
NULLIFY LOCKOUT INITIATION or CLEAR LOCKOUT IF ESTABLISHED
occur a second time before the steps
Under computer control (for input)
TEST FOR LOCKOUT
Content of buffer register~ X
Clear buffer register, INITIATE LOCKOUT
Content of X~ Computer storage,
an rOB (lOA) Read Fault, Class I, is generated.
An lOB (or lOA) Read Fault, Class II, occurs if lOB (or lOA) receives information from external equipment before the control circuitry of the buffer
register has received an indication that previous output operations involving
it have been completed.
In other words, if the steps
Under computer control (for output)
Content of computer register~X register
TEST FOR LOCKOUT
(X)~uffer register, INITIATE LOCKOUT
are followed by the steps
Under external equipment control (for input)
Input information ~ buffer register
NULLIFY LOCKOUT INITIATION or CLEAR LOCKOUT IF ESTABLISHED,
an rOB (lOA) Read Fault, Class II, is generated.
PX 38
5
INPUT AND OUTPUT SYSTEMS
d. PROGRJ\M INTERRUPT FEATURE. - The program interrupt feature, discussed
previously in the General Description and Sequential Presentation of Instructions sections, permits signals from external equipment to activate the interrupt control and provides automatic :interruption of a computer program when the
external equipment is ready to communicate with the computer. The instruction
at F3, which is acquired for executic)n by the interrupt feature, could provide
a jump (Return Jump) to a subroijtine which is coded for input or output operations involving the piece of external equipment which instigated the interrupt.
Upon completion of the subroutine, a jump would be programmed, returning operation to the program which was interrupted.
This use of the interrupt allows to a certain extent a disregard of the
timing restrictions intrinsic to input and output operations from and to that
external equipment which may send an interrupt signal to the computer. Those
pieces of external equipment which m~iy thus generate the interrupt signal do
so (with the proper conditions) each time the equipment is ready to receive or
transmit information.
The interruption of the current program must be accomplished, and the input or output SUbI'outine must be executed, within the time
allowed by the external equipment fOI the computer processing of information.
Factors could be present in the progIam being currently executed by the computer
which could cause a delay of the interrupt being carried out and consequently
delay the necessary input or output operations from being executed within the
time limit. Such factors could be an extensive repeat sequence in process at
the time the interrupt is activated, or a reference to a drum address which
could require up to the maximum access time of 34 milliseconds.
In order for the interrupt signal to be sent to computer (interrupt) control,
an interrupt line (where it is provided) must be activated in the piece of
external equipment itself.
This is done by a switch-setting on the equipment,
or by programming an External Function instruction with an lOB Select Interrupt
bi t.
2.
PHOTOELECTRIC PAPER TAPE READER.
a. GENERAL. - The Photoelectric Paper Tape Reader (shown in Figure 1), in
conjunction with the lOA and lOB registers and associated control circuitry,
provides a means of input of information to the computer. The media of information representation is seven-level punched paper tape. The tape reader has a
single reading station composed of a column of seven photocells associated with
the seven levels of a tape frame as the tape moves through the reader. (Also
punched in the tape are feed holes, p3rallel to the length of the tape, between
levels two and three.)
The six (or seven) bi ts representl~d by each frame are sensed s imul taneous ly
and transmitted to the six (or seven) lower order stages of lOA. The representation of ones in the tape frame is ac'cually transmitted by a signal received by
the correspond ing stage of lOA. The :C'epres enta t ions of zeros are "transmi t ted"
by the absence of such a signal. Thu:; lOA must initially be clear for an accurate
representation of the contents of a fl:ame before such transmissions occur. The
transfer of information from lOA to an addressed computer location, via the X
Register, is accomplished by programm:Lng an External Read instruction, ERjv with
j = 0, to be executed each time lOA rnceives the contents of a frame from the
tape reader.
I I X 3U
{]
INPUT AND OUTPUT SYSTEMS
Figure 1.
Photoelectric Paper Tape Reader
PX 38
7
INPUT AND OUTPUT SYSTEMS
The six lower levels of the punched tape (6, 1, ••• , 5) contain information
to be placed at an addressed computer location and may contain loading instructions directing the insertion of information into storage; or the seventh level
of the tape may be punched to effect the proper disposal in the computer of the
information in the lower six levels. In either case the loading directions in
the sixth or seventh levels of consecutive frames must be interpreted within the
computer to achieve the designated storage of information.
Typical coding, as punched in the seventh level of a tape, for loading
directions is shown on the following diagram. Sprocket or feed holes are not
shown on this diagram.
IN'SERT
ADDRESS
•
ENTER
DATA
__ 1__
J - J-•
•
I
I
I
I
I
I
I
I
I
(,14 I
I
-:L'
•
,
! !
LI2LS
Lo
- ,-...............
CHECK
ADDRESS
_--1'
.
.
-J ETC,_C-- L~
•
~35
,,
\..5 \..35
i.1I
!
----
ENTER
DATA
"\
FIRST
WORD
,,
ill I
I I
I I
SECOND
WORD
I I
,,
,,
,,
"
t..o
• •
v5
•
",
1.,0
'
I I
1.,14 I I
: I I
•
• •• J
1.,12 1I61"O
These distributions of holes, ab represented by "one's" in the computer, are
interpreted as follows.
(1)
INSERT ADDRESS.- The adclress designated by i 14 ••• iO to be placed
at an clddressed location WhICh will serve as a
"dummy" PAK.
(2)
ENTER DATAe -
(3)
CHECK ADDRESS. - The address designated by iI4 ••• iO should be id~n
tical 1.0 the address currently held in the "dummy"
PAK.
The first word, i::\5 ••• iO' is to be placed at the
addres~: held in tfie above "dummy" PAK.
Success ive
words Hre to be placed at consecutive addresses.
b. PROGRAMMING FOR INPUT. - Information loading from the tape reader is
controlled by using the External Function instruction to place bits in selected
stages of lOB. The three stages in ~lhich a combination of ones must be placed
are, with their corresponding interpretations, as follows.
IOB33
Select Tape Reader
IOB 16
Start
Tape Header
lOB 15
Stop
Tape Reader
PX 3;9
0
INPUT AND OUTPUT SYSTEMS
The "Select Tape Reader" stage must contain a one for all operations affecting
the tape reader. The combinations of one's in lOB which effect control of the
tape reader are as follows.
Start (Free Run) - IOB33 and IOB16 coded as EF-v,(v) being 10 00002 00000
(octal). This combination causes the reader to start and continue running with
the six (or seven) bits of each consecutive tape frame being transmitted to IDA.
Stop - IOB33 and IOB15, coded as EF-v, (v)
This combination causes the reader to stop upon
six (or seven) bits of the tape frame sensed by
the interpretation, by the control circuitry of
being 10 00001 00000 (Octal).
the transmission to IDA of the
the reader immediately followiry
the reader, of (lOB) as a stop.
Step Tape Reader - IOB33 , IOB16, and IOB15, coded as EF-v, (v) being 10
00003 00000 (octal). This combination causes the reader to start, transmit to
IDA the six (or seven) bits of the first frame of tape it senses, and stop.
The normal rate of tape speed through the reader is approximately 200 frames
per second, but, as a function of line voltage, it may be ~s high as 230 frames
per second. Thus the time interval between the sensing of successive frames of
tape may vary from 4.3 to 5 milliseconds.
Timing factors to be taken into
consideration for the three controlled operations of the tape reader are as
follows.
(1)
Start (Free Run). - Information is being transmitted from the tape
to IDA at the rate of one frame every 4.3 milliseconds (assuming
for synchronization the shortest time). The contents of IDA should
be transmitted to the X Register, using the External Read instruction, at corresponding time intervals for the most efficient use of
computer time. The execution of the External Read instruction
clears IDA after its contents have been transmitted to X. If
another External Read is programmed before the contents of the next
frame have been received from the reader, machine operations are
temporarily halted by a lockout condition until IDA receives information. If information is transmitted to IDA from the tape reader
before IDA has been cleared of the contents of the preceding tape
frame, a B Fault occurs and is indicated by the 10 Fault light on
the Supervisory Control Panel.
(2)
Stop. - To insure that the reader is stopped so that the next tape
frame whose contents are transmitted to IDA is the last frame desired to be sensed by the reader, the External Function instruction
coded for a reader stop should be programmed to be executed at
least one millisecond before the sensing of the last desired frame.
This can be done by programming it timewise to follow within three
milliseconds of the previous External Read. After the reader is
stopped, an External Read instruction must be programmed to transmit the contents of IDA to the X Register.
If the stop is made
during tape loading operations and IDA will not be used before the
reader is again started, the External Read may be programmed to
precede the start instruction.
If the stop instruction is not
executed before the transmis s ion to IDA of th.e contents of the las t
desired frame, and a read instruction is not programmed to transmit
this content of IDA to X, a B Fault will be indicated. The computer
will be stopped when IDA is to receive the contents of the next
frame which must be sensed before a stop will actually occur.
PX 33
9
INPUT AND OUTPUT SYSTEMS
When a stop occurs, a three millisecond time delay, allowing the
reader to stop physically, is generated in the reader control circuitry. This time delay prevents the reader_from being started for
three milliseconds. Thus, a start instruction, if programmed to be
executed during this period, is not effective until the three millisecond period has elapsed.
(3)
Step. - During step operctions the first frame sensed by the reader
is the frame which allows the reader stop to be performed.
The
contents of the first tape frame are transmitted to the lOA register. Thus, consecutively programmed step instructions must each be
followed by an External Ii:ead instruction with the first preceded by
an External Read if lOA js not initially clear. There is a fivemillisecond time lapse bE'tween successive frames at the operating
speed of the reader. A three-millisecond delay is generated by the
stop reader operation, arrl approximately a one-millisecond delay is
generated by the reader start operation. Therefore, approximately
nine milliseconds are cor.sumed in a step instruction.
c. OPERATION. - Manual operations necessary to the functioning of the
Photoelectric Tape Reader consist of j.nserting the tape to be read in the tape
passage of the reader and depressing momentarily the Start button on the reader
itself or the Tape Reader Start buttofl on the lower left section of the Supervisory Control Panel of the computer. Depressing either of these buttons turns
on the reader power; similarly, deprE~ssing either the Stop button on the reader
or the control panel turns off the reclder power. After the reader power is on,
an input routine for the reader may bE! initiated which includes instructions to
start the reader, read the (lOA) to ae:dressed computer locations, and process
the information being loaded accordin~r to the coded loading directions.
3.
HIGH-SPEED PAPER TAPE PUNCH.
The High-Speed (Paper Tape) Punch output system consists of the High-Speed
Punch Register, HPR, the High-Speed Punch Control, and the punch (as shown in
Figure 2) which presents information on seven-level punched paper tape at the
rate of 60 frames per second. The Hi{rh-Speed Punch Register is a seven-stage
buffer register which temporarily stores digits in their transmission between
the computer and the punch.
The high-speed punch control circuitry senses the
contents of HPR and energizes the puneh to perforate the tape frame in the levels
whose corresponding stages in HPR con1;ain representations of ones. After information is received from HPR, the tape is advanced through the punch by one
frame, placing the next tape frame in position to receive information.
The transmission of information to the punch is initiated by the coded computer Punch instruction, PUjv, operat:Lon code 63. This instruction directs the
transmission, via the X Register, of the contents of the right-hand six stages
of v to the first six stages of HPR. Actually, only the representations of ones
in stages X5 ..• X are transmitted to the corresponding stages of HPR~ A j of
one is transmittQd directly to the selrenth stage of HPR. According to the contents of HPR6 ••• HPRO' holes may be punched in the corresponding tape levels,
7, 6, 1, •.. , 5. To transmit from address v a word of 36 bits so that each
group of six bits is punched in its cc)rrect relative tape position, the Punch
instruction must be executed six time~i, each execution being preceded by a
PX 30
10
INPUT AND OUTPUT SYSTEMS
Figure 2.
High Speed Paper Tape Punch
PX 38
11
INPUT AND OUTPUT SYSTEMS
Shift instruction. The word must be shifted at the v address of PUjv six times,
the first shift operation positioning the six most significant bits of the word
in the six right-most stages of v, and each succeeding shift operation positioning the next most significant S:LX bits in the right-most stages of v.
The High-Speed Paper Tape Punch is ready for operation when the tape is
properly positioned in the punch with a "leader" of blank tape preceding the
first punching position. This leader may be fed through the punch by depressing
either the tape feed button on the (~omputer control panel or on the punch. The
punch is started in continuous cyclns of operation by setting both the toggle
switch on the punch and the tape punch toggle switch on the lower left section
of the Supervisory Control Panel of the computer to their ON positions. Either
switch in its OFF position prohibit~; punch operation. The time duration of a
punch cycle is 16.7 milliseconds.
The first punch instruction initiated during
a punch cycle n does not make an efJ:ective punch refereJ;lce, (HPR)------- Punch,
until the beginning of the next cyc:le and requires the first 12.5 ms of this
succeeding cycle, n + 1, for the conpletion of its punch reference. Thus HPR
is not ready to receive additional output information until the last 4.2 ms of
the cycle n + 1. If a second punch instruction is initiated before such an
indication of readiness is given to HPR, a computer lockout w~ll occur stopping
the computer until 4.2 ms before thn beginning of cycle n + 2. If the second
punch instruction immediately folloHed, During cycle n, the first punch instruction, the lockout time is 12.5 ms pIus the unexpired time of cycle n after the
lockout period ·effected by the second punch begins. Thus, if the first punch
instruction was initiated immediateIy after the beginning of cycle n, a lockout
time of approximately 29 ms would oecur (12.5 plus almost 16.7). This is the
maximum lockout time possible. The punch reference made by the second Punch
instruction will not be completed uutil the first 12.5 ms of cycle n + 2 have
elapsed. If Punch instructions are programmed to be executed at 16.7 ms
intervals, a computer lockout may b{~ effected by the second instruction, but
the execution of successive Punch instructions will be in synchr.onization with
the punch cycles because of the actual stopping of computer operating time.
4.
ELECTRIC TYPEWRITER.
The Electric Typewriter output ~;ystem consists of the Typewriter Register,
TWR, the Typewriter Control, and the Electric Typewriter, as shown in Figure 3.
The Typewriter produces typewritten manuscript with letters in upper and/or
lower case, numbers of the decimal ~;ystem typed on the same level as letters
or elevated above this level as exp()nents, and a variety of characters such as
a plus sign (+), a minus sign (-) , and a comma (,), etc. These letters,
numbers, and characters are typed in a format determined by the response of
the typewriter control circuitry to six-bit codes which are interpreted as,
and actuate the typewriter to, such physical operations as space, carriage
return and tabulator. Incidental to a carriage return is a line spacing operation, the number of spaces between consecutive lines being determined by the
manually set line spacer on the typtMriter.
The tabulator operation also
requires a manual setting; the 'intt!rpretation of the tab code as such releases
the carriage to move ~o a predetermj.ned manual tab setting. A shift-up operation positions the type bars for upper case typing. To resume typing in lower
case a shift-down operation must be executed.
PX 3[1
12
INPUT AND OUTPUT SYSTEMS
Letters and numbers are also typed, as directed by the Typewriter Control,
in response to six-bit codes with ecch code representing a single letter or
number. To type a letter in upper c.ase or a number as an exponent, the type
bars must be shifted to their upper case position before the typewriter responds
to the letter or number code. Two characters are represented by a single code.
The character which is typed is determined by the location of the type bars in
their upper or lower case position.
A list of the typewriter codes, given as two-digit octal numbers, is presented with their associated typewriter functions in Table 1. If an illegal
code is sent to the typewriter, an A Fault will occur, which is indicated by
the Print fault light on the Supervisory Control Panel.
The computer is
stopped in its operations at the point when its control receives a signal from
the typewriter control that an illegal code has been detected. The computer may
be restarted from where it ceased operations by first pushing the CLEAR A FAULT
button and then by pushing the START button on the computer.
This insures that
the illegal code is cleared from TWH.
Typewriter operations for output are initiated by the computer instruction
Print, PR-v, operation code 61. This instruction directs the transmission, via
the X Register, of the contents of the right-hand six stages of v to the six
stages of the Typewriter Register.
TWR serves as a buffer register for information being transmitted from the computer to the typewriter. Actually, only
the representations of ones in stages Xs
Xo are transmitted to the corresponding stages of TWR. The typewriter control circuitry senses the representation of a six-bit code in TWR and in so doing causes the typewriter to type a
single letter, number, or character or perform a single typewriter operation.
For example, to typ~ the single upper case letter M, the following two instructions would be programmed.
p
••
5
v 0) is 100 III
61-v, (v5
v ()) is 000 III
61-v,
(v
A movement left of the carriage ])y one space to reposition it for the next
typing operation occurs automaticall:v after each typing of a letter, number, or
character.
The speed of the typewriter allows it to type approximately nine characters
second.
Thus, a timing period of approximately 105 ms will elapse between
consecutive prints by the typewriter"
(Coded typewriter functions require a
longer timing period for their completion.) If successive Print instructions
are programmed to be executed in les:i time, a lockout condition will exist until
the control circuitry of TWR receive:i an indication that the typewriter is ready
to receive another six-bit code. The maximum lockout time for the typewriter
is dependent upon which phase of the typewriter cycle is being executed currently
when a test lockout reference of a sllccessive Print instruction is made.
pe~
Manual preparation of the typewr~.ter for operation consists of inserting
paper, setting the OFF-ON switch to the right of the typewriter keyboard to
the ON position, and selecting the ON LINE switch position.
PX 3[;
14
INPUT AND OUTPUT SYSTEMS
TABLE 1.
TYPEWRITER CODES
The upper case, UC, or lower case, LC, character is typed according
to the position of the type bars.
Type Letter
LC
UC
A
a
B
b
C
D
E
c
F
:
G
H
I
J
K
L
M
N
1
0
0
p
p
q
r
Q
R
S
T
U
V
W
Octal
d
e
f
g
h
1
j
k
m
n
s
t
u
v
X
y
w
x
Y
Z
z
Type Number
UC
LC
I!
30
23
16
22
20
26
13
05
14
32
36
11
07
06
03
15
35
12
24
01
34
17
31
27
25
21
1
52
74
70
64
62
66
72
60
33
37
1
2
2
3
:3
"5
It.
e
6
7
8
9
0
5
7
e
9
0
Perform Typewriter Operation
Octal
I
II
Space
Shift up
Shift down
Back space
Car. return
Tabulator
Color Shift
Code delete
Stop
-- --
Octal
04
47
57
61
45
51
02
77
43
ii
II
~:.=:.=::.=-":~
Type Symbol
LC
UC
-
(Superscript
Minus)
-
Octal
(Hyphen or
Minus)
56
(Equals)
44
(Multiply)
=
/
(Virgule)
+ (P Ius)
54
(
(Open Parens)
,
(Comma)
46
)
(Close Pa rens)
•
(Period)
42
-
(Underline)
r
(Absolute;
50
~
PX 30
15
INPUT AND OUTPUT SYSTEMS
5.
PUNCHED CARD INPUT/OUTPUT SYSTEM.
a. GENEill\L. - The Punched Card Input/Output equipment, in conjunction with
the lOA and lOB registers and associated control circuitry,provides a means of
input to and output from the Univac Scientific computer.
The input/output
card equipment comprises the Card Unit, shown in Figure 4, and the Card Unit
Control.. The media of informatio'n representation is 80-column tabulating cards,
in which holes are punched in specified patterns.
These cards may be punched
or read at a rate of 120 cards per minute.
The Card Unit, a~ used with the lnivac Scientific, utilizes a left-hand
channel for punching cards and a right-hand channel for reading cards, Punched
cards whose information content is to be transmitted to the computer are routed
through the "read" channel of the Card Unit; blank cards which are to receive
information and to be punched accordingly are routed through the "write" channel.
Cards to be routed through the read channel are placed in the card read feed
hopper and received, after their advancement through the channel, by the read
receiving stacker.
Cards to be routed through the write channel are placed in
the card punch feed hopper and received, after their advancement through the
channel, by the punch receiving stac~er.
The tabulating card used by the Card Unit is divided into 12 horizontal
rows and 80 vertical columns with grc1ups of these columns being designated as
Fields I, II, and III as shown in the diagram of an unpunched card in Figure 5.
A rectangular hole, or index, may be punched at the intersection of any row and
column.
If the input or output information is coded to represent binary words,
each row may be punched to represent two 36-bit words plus six additional bits
of information.
(A hole represents a one; the absence of a hole denotes a
zero.) Tabulating cards may also be punched in a pattern to represent alphabetical and digital characters. An optic,nal punched pattern of letters and decimal
digits is shown in Figure 6.
b. PROGRi\MMING FOR INPUT AND OUTPUT. - Information is transmitted to or
from the cards in response to progranmed External Function and External Write
or External Read instructions.
A sE:ries of three of these EW or ER instructions, programmed consecutively, dire:ct the transmission of each row of information, via X, between addressed comI,uter locations and the Input-Output Registers, IDA and lOB. The sequence of information flow is as follows.
To transmit information from the computer to a tabulating card, the group
of following External Write instructions, preceded by appropriately coded
External Function instructions, is executed twelve times, once for each card row.
EWjv, j .- 0
EWjv, j .- 1
EWjv, j - 1
(X)~ IOA~
(X)-~IOB~
(X ~ ---;.. IOB~
Field III
Field I
Field II
Row 9, 8, •.• 0, 11, 12
To transmit information from a punched tabulating card to the computer, the
group of following External Read inst.ructions, preceded by appropriately coded
External Function instructions, is e}~cuted twelve times, once for each card
row.
PX 38
16
":j
1<
FIELD
L-
1-1'
I
I~
to
s::
('t)
1'1
I
.
I
C.,11
1-:3
Q.)
0'"
s::
......
Q.)
c-+
1-1.
::s
to
C""':l
ROW 12
ROW II
ROW
0
ROW
......
CO
>< cl.
W
CO
;;0"
I
1:'11:'11"'\
.-,.-, ....
rlc.L.U
m
>E
I
I
1
I
H
:z
I
I
'"C
1000 000 00 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 ~o 0 0 000 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n0 Q 00000000 00000000
I,. f l I 4 , , 1 • t It 11 !1 13 14 I' '5 11" " 20 2' Z2
n:M
25 3 17 21 l'9 JII '.' ];' 13 M 315
". __ • 4.
Q
Cl M 4I!i • Q 41
~ SJ 5. V ~ 54 sa SIl 51 51 9
• II 12 &3 64
~"
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INPUT AND OUTPUT SYSTEMS
ERjv, j -- 0
ERjv, j -- I
ERjv, j -- I
Row 9, 8, •.• 0, 11, 12
Field III~(IOA)~ X
Field I ---=--(IOB)--+ X
Field II---:=- (IOB)~ X
Information transmission between lOA and Field III is optional and may be
omitted by not executing EW or ER with j = 0 and by manually setting a switch
on the Card Unit Control cabinet to its "Out" position.
For reading and writing
of all three fields the position of this switch, called the Enable Field III
switch, is in its "Normal" setting.
Preceding any reading and writing operations by the punched card system. at
least one External Function instruction must be executed to start the Card
Unit, position the cards for reading and/or punching (these two conditions may
be established also by manual operation), and establish the condition necessary
for a read and/or write. The External Function EF-v transmits representations
of ones to certain stages of lOB, then, according to the selected stages, the
following signals are sensed by the card system.
lOBO
Read
lOBI
IOB 2
IOB 3
IOB 4
lOBS
IOB7
IOB 35
Punch
Pick Reader Card
Pick Punch Card
Stop (and Drop Selections)
Run Free
Interrupt
Start Cycle
Start Cycle - This selection must be present in each EF-v to make any of
the other selections effective. A signal from IOB35 engages the drive mechanism
of the Card Unit and causes one "cycle" of operation.
The time consumption of
each cycle is 500 milliseconds with each eycle consisting of a sequence of 18
cycle points of approximately 27.8 milliseconds each. The cycle points are
numbered in the order 14, 15, 16, 17, lB, 9, 8, ..• 1, 0, 11, 12, 13, (14).
Interrupt - With the Interrupt switch on the Card Unit Control cabinet set
to "By Command", a selection of IOB7 energizes an interrupt line in the card
equipment so that an interrupt signal is ;5ent to the computer (interrupt) control
when the conditions are established for reading and/or writing a card row. This
occurs each time a card row is in position for reading and/or writing (i.e.,
at the beginning of cycle points 9, 8, .•. , 1, 0, 11, 12) if the Start (or Run
Free) and Read and/or Punch selections are effective.
The first External Read
instruction must be executed within 10 milliseconds after the interrupt signal
is sent to the computer. The first External Write instruction must be executed
within 1.5 milliseconds after the interrupt signal is sent to the computer.
The interrupt selection may be made by setting the INTERRUPT switch on the
punched card equipment to its "Locked In" position. With this setting the
interrupt line in the equipment is energized (without the IOB 7 selection) under
the conditions mentioned above.
PX ~30
20
INPUT AND OUTPUT SYSTEMS
Run Free - A selection of IOB5 causes continuous cycle operation by retaining in effect the Start selection, along with other selections made simultaneously with the Run Free, until a Stop signal is received by the execution
of another programmed EF-v.
Stop - A selection of IOB4 permits only one more cycle of operation with
the selections effective that were made by the previous EF-v; i.e., the stop
is sensed after point zero which allows another complete cycle before the Stop
is effected.
Pick Punch Card - A selection of IOB3 causes the bottom-most card in the
punch card feed hopper to be withdrawn from the hopper and placed in the punch
channel.
This selection is also necessary for the first advancement of the
card through the channel.
Pick Reader Card - A selection of IOB2 causes the bottom-most card in the
read card feed hopper to be withdrawn from the hopper and placed in the read
channel. This selection is also necessary for the first advancement of the
card through the channel.
Punch - A selection of lOBI enables the punch mechanism to receive information from lOB (and lOA) and prepares it to punch this information on a card
during the next cycle.
Read - A selection of lOBO enables the brushes used for reading to sense
the information in each row of a card as it passes beneath them.
After these lOB select signals are received by the punch card equipment
they are held in effect for one cycle of operation (or a number of cycles if a
Run Free Select was chosen) by the control circuitry so that lOB may be cleared
for information transmission.
After a card is picked and withdrawn from either the punch card feed hopper
or the read card feed nopper. it may advance through a series of five positions
or "stations" in the read channel or punch channel.
A Pick Reader Card selection or a Pick Punch Card selection places a card in either Read Station 1 or
Punch Station 1.
A Pick Punch Card Selection or Pick Read Card selection is
necessary also to advance a card in the channel from Station I to Station 2.
These operations may be initiated by programming External Function instructions
with bits in the appropriate stages of lOB or by manually operating switl(~hes
on the Card Unit itself.
After a card is in Station 2, in either the punch
or read channels, four more cycles of operation are necessary to advance the
card through the channel and into its final position in the receiving stacker.
Each cycle of operation advances cards in both channels if they are in or past
Station 2 to the next station.
Punch Station 3 in the punch channel contains the punch mechanism. After a
card is in Punch Station 2, one cycle of operation is needed to advance the
card to the punching position. During the cycle whieh advances the card from
Punch Station 2 to Punch Station 3, the information to be punched must be received from lOB (and lOA). More explicitly, during each cycle point 9, H, •••
1, 0, 11. 12, of 27.8 milliseconds, the series of three (or two) External Write
instructions should be executed consecutively, and the Punch select signal must
FX 38
21
INPUT AND OUTFUT SYSTEMS
be in effect. With these conditions information to be punched (in the correspondingly numbered card rows 9, 8, ••• , 0, 11, 12) can be transmitted to the
punch mechanism. At the beginning of the next cycle, automatic punching of a
complete card occurs before the card is advanced to Station 4. Outlines of
programming for punching of consecutive cards are given in Tables 2 and 3.
Read Station 2 in the read channel contains the brushes used for sensiny
the cards. During the cycle of operation in which the card is advanced through
the read station, the information may be read, a row at a time, as the card
is advanced past the read brushes.
This information must be transmitted to
computer storage from lOB (and lOA) as it is received.
More explicitly, during
each point 9, 8, ••• 1, 0, 11, 12 of 27.8 milliseconds, the series of three (or
two) External Read instructions should be executed consecutively, and the Read
select signal must be in effect.
This enables the transmission to addressed
storage locations of the information of the correspondingly numbered rows
9, 8,
1, 0, 11, 12. Outlines of programming for reading of consecutive
cards are given in Tables 4 and 5.
An outline of programming for simultaneous reading and writing of consecutive cards is given in Table 6 and on the page preceding it. The transmission
of Field III in any of the programs may be eliminated by not executing the
External Read or Write instructions with j = and by setting the Enable
Field III switch properly.
°
c.
OPERATION.
(1) COMPUTER CONTROLLED. - The equipment is prepared for controlled
operation, after power is applied at the Card Unit Control Cabinet, by following
the steps below.
Step 1 -
If only 72-card columns are to be read or punched, set the FIELD
III switch (SOl) to the "Out" position. If 80 columns are to be
read or punched, set this switch to the "Normal" position.
Step 2 -
If card reading is to b~ performed, place the deck of cards to be
read into the right-hand feed hopper of the Card Unit. If card
punching is to be performed, place a deck of cardl in the lefthand feed hopper. Place the metal weights on top of the decks.
In either hopper t cards are placed face (printed side) down, so
that the "9" edge enters the channel first.
Step 3 -
Set the toggle switches on the Card unit in the following manner.
DUPL.
PUNCH
MOTOR
DC
HEAD
READ
PICK PUNCH
STANDBY
PIC~
away from operator
away from operator
left
left
away from operator
towards operator
towards operator
towards operator
After these steps have been performed, the punched card program may be
started in the computer.
]>x 38
22
INPUT AND OUTPUT SYSTEMS
TABLE 2.
WRITE - SINGLE OR CONSECUTIVE CARDS
The computer instructions below withdraw two cards from the punch card
feed hopper, position the first card for punching and punch information in it,
and continue advancing it through the punch channel until it reaches its
final position in the receiving stacker. (The second card withdrawn from the
hopper is left in the first station.) Other instructions may be programmed
and executed during and between each cycle of operation of the card equipment
providing that the timing requirements noted are met.
EF-v
(v)
EF-v
(v)
EF-v
(v)
= Start
Pick Punch Card
= Start
1 cycle
Pick Punch Card
= Start
Punch
Within 140.5 ms of the start of this cycle the
execution of the following three instructions
should be initiated:
EW,O,v
EW,l,v
EW,l,v
1 cycle
}
1 cycle
Repeat for each card row, each repetition being
initiated not later than 1.5 ms after the beginning of the corresponding point.
= Start
= Start
(punching occurs)
EF-v
(v)
EF-v
(v)
EF-v
(v) = Start
(channel cleared of last punched card)
1 cycle
1 cycle
1 cycle
To transmit information to n consecutive cards, without selecting the Run
Free bit, include a Pick Punch Card bit in (v) of the third External Funntion
instruction above. Repeat the third EF-v instruction and the group of fucternal
Writes occurring in that cycle n times. Then,at the conclusion of the program
above, the nth or last punched card will be found in the punch stacker with
cards remaining in the first and fifth punch stations.
PX 38
23
INPUT AND OUTPUT SYSTEMS
TABLE: 3.
WRITE -. FREE RUN
The complJlter instructions below withdraw singly a sufficient number of
cards from the punch card feed hopper to hold the information to be punched,
position them for punching and .punch information in them, and continue advancing them through the punch channl~l unt.il the last card punched reaches
its final position in the receiving stacker. (Unpunched cards are left in
the first and! fifth stat ions.) Othe r inst. ruct ions may be programmed and executed durin~r and hetweel1 each cycle of operat ion of the card equipment providing the tim'ing requirEments are met.
Number n is the number of cards required t.o hold the information to be written.
EF-v
(v)
= Start
1 cycle
Pick Punch Card
-
EF-v
(v)
= Start
1 cycle
Pick Punch Card
-
EF-v
(v)
= Start
Free Run
Pick Punch Card
Punch
Wi. thin 140.5 ms of the st,lrt of: this cycle the execution
01.. the following three in st ruct.ions should be initiated~
EW,O,v
EW,l,v
EW, 1, v
}
(v) = Start
Stop
(punching of n-J. card occurs)
Wi. thin 140.5 ms of the start of~ this cycle the execution
01:. the following three in struct.ions should be initiated .
EF-v
EW,O,v
EW, 1, v
EW, 1, v
peat for each card row, each repetition being initiRe
at
ed not later than 1.5 ms aftE ~r the beginning of the
ccIrresponding point.
Th e repetitive group of R~ternE11 Write instructions must
be programmed n-l times, '~ach ~Jroup being executed timewi. se within the cycle which enEIbles the punching.
}
repeated
n-l cycles
1 cycle
Re peat for each card row, each repetition being initiat ed not later than 1.5 ms aftE ~r the beginning of the
C(trresponding point.
EF-v
(v)
= Start
1 cycle
EF-v
(v)
= Start
1 cycle
EF-v
(v) = Start
(nth card placecl in receiving stacker)
(nth card punchE ~d )
.?X 3S
24
1 cycle
INPUT AND OUTPUT SYSTEMS
TABLE 4.
READ - SINGLE OR CONSECUTIVE CARDS
The computer instructions below withdraw two cards from the read card
feed hopper, position the first card for reading,
transmit its contents
to the computer, and continue advancing it through the read channel until it
reaches its final position in the receiving stacker. (The second card withdrawn from the hopper is left in the first station.) Other instructions may
be programmed and executed durina and between each cycle of operation of the
card equipment providing the timing requirements are met.
(v)
EF-v
= Start
I cycle
Pick Read Card
(v)
EF-v
= Start
Pick Read Card
Read
Within 149.0 ms of the start of this cycle the
execution of the following three instructions
should be initiated.
ER,O,v
ER, 1, v
ER, 1, v
}
1 cycle
Repeat for each card row, each repetition being
initiated not later than 10 ms after the beginning of the corresponding point.
EF-v
(v)
EF-v
. (v)
EF-v
(v)
EF-v
(v)
= Start
= Start
= Start
= Start
I cycle
I
cycle
1 cycle
~---.-
I
cycle
(channel cleared of last read card)
To transmit information from n consecutive cards, without selecting the
Run Free bit, repeat the second External Function instruction above and the
group of External Reads occurring in that cycle n times. Then at the conclusion of the program above, the nth or last read card will be found in the
read stacker with an n + I card remaining in the first read station.
PX 38
25
INPUT ANC OUTPUT SYSTEMS
TABLE 5.
READ - FREE RUN
The computer instructions below withdraw singly from the read card feed
hopper the cards to be read, position them for reading and transmit their
information content to the computer, and continue advancing them through the
read channel until the last card read reaches its final position in the receiving stacker. (A card is left in the first station.) Other instructions
may be programmed and executed between and durinQ' each cycle of oPAration of
the card equipment providing the timing requirements are met.
Number n is the number of cards to be read from.
(v)
EF-v
= Start
1 cycle
Pick Read Card
(v)
EF-v
= Sta.rt
Free Run
Pick Read Card
Read
With in 149. U ms of '~he st art of this cycle the
execution of the followin.g three instructions
should be initiated
ER,O,v
ER,l,v
ER,l,v
}
Repeat for each card row, each repetition being
initiated not later than 10 ms after the beginning of the corresponding point.
The repetitive group of External Read instructions must be programmed n-l times, each group
being executed timevlise within the cycle which
enables the reading.
n-l cycles
(v) = Start
Stop
(reading of nth card)
EF-v
Within 149.0 ms of the start of thi s cycle the
execution of the following three instructions
should be initiated
ER,O,v
ER,l,v
ER,l,v
repeated
f
1 cycle
Repeat for each card row, each repetition being
initiated not later than 10 ms after the beginning of the correspcnding point.
EF-v
(v)
= Start
1 cycle
EF-v
(v)
= Start
1 cycle
EF-v
(v) = Start
1 cycle
EF-v
(v)
= Start
1 cycle
(nth card placed in receiving stacker)
INPUT AND OUTPUT SYSTEMS
SIMULTANEOUS READ AND WRITE - SINGLE OR CONSECUTIVE CARDS
The outlined progr~ms for reading and writing single or consecutive cards
simultaneously may be deduced by interposing the two outlined programs for
read and write, single or consecutive cards. A composite of the selections
made in both programs in each individual cycle would be selected for one cycle
of the simultaneous operations.
If it is desired that the reading occur
during the same cycle that the information to be punched is being received by
the card equipment, the second cycle of operation of the program for writing
should be interposed with the first cycle of operation of the reading program.
External Read instructions immediately follow External Write instructions
when both occur during the same cycle.
The same timing considerations must be given the simultaneous performance
of reading and writing as when they occur individually. Other instructions
may be programmed and executed between and during each cycle of operation
providing the timing requirements are met.
PX 38
27
INPUT AND OUTPUT SYSTEMS
TABLE
6.
SIMULTANEOUS READ Al\D
PUNCH -
FREE
RUN
The computer instructions below withdraw cards from the read card feed
hopper and punch card feed hopper, position them for reading and writin~
perform the information transmittal, and continue advancing them through their
individual channels until the last cards read and punched reach their final
positions in the receiving stackers. Other instructions may be programmed and
executed between and during each cycle of operation of the card equipment providing the timing requirements are met.
Number n is the number of cards to be read from and the number of cards required to hold the information to be written.
(v) = Start
Pick Pun ch Card
EF-v
1 cycle
~------.------.-----------------~----------------------~------------~----------~
EF-v
(v)
= Sta.rt
Pick Pun ch Card
Pick Rea d Card
EF-v
(v)
= Start
Free Run
Pick Rea d Card
Read
Pick Pun ch Card
Punch
1 cycle
Within 140.5 ms of the start of this cycle the
execution of the follcwing six instructions
should be initiated.
EW
EW 0 ,v
l,v
EW 1, v
ER 0 v
ER l'v
ER l', v
.
Repeat for each card lOW, each repetition being
initiated not later than 1.5 ms bfter the beginning of the corresponding point.
The repetitive ~Iroup of External Read and External Write instructions must be programmed
n-l times, each group being executed timewise
within the cycle which enables the reading and
writing.
PX 38
28
repeated
n-l cycles
INPUT AND OUTPUT SYSTEMS
TABLE 6.
EF-v
SIMULTANEOUS READ AND PUNCH - FREE RUN
(v)
= Start
Stop
Within 140.5 ms of the start of this cycle the
execution of the following six instructions
should be initiated .
EW,O,v
EW ,1, v
EW ,1, v
Ell ,O,v
ER ,1, v
ER ,1, v
.
1
c:ycle
Repeat for each card row, each repetition being
initiated not later than 1.5 ms after the beginning of the corresponding point.
EF-v
(v)
EF-v
(v)
EF-v
(v)
EF-v
(v)
= Start
= Start
= Start
1 c,ycle
1 c.ycle
1 cycle
(nth card placed in write receiving
stacker)
= Start
(nth card placed in read receiving
stacker)
PX 38
29
1 cycle
INPUT AND OUTPUT SYSTEMS
(2) MANUAL OPERATION. - The punched card system may be operated manually
by switches and pushbuttons on the panel located below the feed hoppers. The
procedures are as followse
(a) TO START. - If cards are in the feed hoppeLs and it is desired
to drive the card equipment through one or more card cycles, press the START
pushbutton.
If the START button is pressed and released immediately, the card equipment
will drive through one complete card cycle. If the button is held down, the
equipment will run continuously.
(b) TO PICK PUNCH CARDS. - If it is desired to feed cards into the
punching channel, set toggle switch PICK PUNCH CARDS to the ON position (away
from the operator), then hold down t:le START pushbut ton unti I the des ired number
of cards have been inserted.
(c) TO PICK READ CARDS. - If it is desired to feed cards into the
reading channel, set toggle switch PICK RI:AD CARDS to the ON position (away
from the operator), then hold down th.e START pushbutton until the desired number
of cards have been inserted.
(d) TO STOP. - To stop the card equipment during a controlled run
so that cards may be added to the feed hoppers, etc., either set toggle switch
STANDBY to the ON position (away from the operator) or press and hold down the
red STOP pushbutton.
This causes the card equipment to stop at the end of the
current card cycle so that the computer program is temporarily halted. If the
toggle switch is reset or the red STOP pushbutton is released the system resumes normal operation.
To clear cards from either channel, remove the cards from the hopper, set
the PICK READ CARD or PICK PUNCH CARD switch to its ON position if a card is in
Station I, and depress the CLEAR and START buttons until the channel is clear.
(3) FAULTS. - When certain faults occur in the system, the card equipment stops.
certain of these faults result in B Fault computer stops which
allow the equipment to complete its current cycle before it stops. A few of
these faults are described below.
(a) OVERHEAT. - If the temperature in any portion of the Card Unit
Control cabinet rises above 10ooF, a computer A Fault stop occurs, and the
amber OVERHEAT indicator on the end of the control cabinet glows.
The Overheat
fault in itself will not cause a card equipment stop, but it may lead to a No
Information A Fault which causes a B Fault computer stop and a card equipment
stop.
(b) NO INFORMATION. - If the eomputer program specifies that
punching and/or reading is to be executed but insufficient or tardy External
instructions are being executed, a B Fault computer stop occurs and the amber
NO INFORMATION indicator on the end of the Card Unit Control cabinet glows.
The computer program must be restarted from the beginning if this occurs.
PX 3U
30
(c) VOLTAGE FAULT. - If power to the card equipment drive motor
fails, the VOLTAGE FAULT indicator on the end of the Card Unit Control cabinet
glows.
The fault may be produced by faulty wiring or by blown fuses.
(d) NO CARD IN READER. - If card reading is supposed to occur and
no card is present in the reading station, a B Fault computer stop is produced
and the NO CARD IN READER indicator on the Card Unit Control cabinet glows.
This fault may be caused by failure to feed cards or by errors in the computer
program. When the source of error is removed, the computer program must be restarted from the beginning.
(e) NO CARD IN PUNCH. - If card punching is supposed to occur in
the next cycle and no card will be present beneath the punch die, a B Fault
computer stop is produced and the NO CARD IN PUNCH indicator on the Card Unit
Control cabinet glows.
This fault may be caused by a feed failure or by errors
in the computer program. When the source of error is removed, the computer
program must be restarted from the beginning.
(f) PUNCH JAM. - If a card jams under the edge of the punching die,
the card equipment stops, all voltages to it are dropped, and the small red JAM
indicator on the Card Unit cabinet glows. If this occurs, shut off the equipment power.
(g) STOP. - A stop light on the Card Unit Control cabinet glows
and the card equipment stops if any of the following occur.
1
Read stacker full.
2
Write stacker full.
~
Read feed hopper empty.
i
Punch feed hopper empty.
~
The Stop button is pressed.
Q
STANDBY switch is thrown to forward position (away from
operator)
7
A Punch Jam occurs.
Note that all of these stops except 1 permit resumption of operation without
loss of data. For stops caused by ~ or i, move the STANDBY switch to the forward position during refill of input hoppers. (During the manual operation
which clears the channels, the depression of the CLEAR button causes a bypass of
the circuitry which normally causes an equipment stop when the feed hoppers are
empty.) Note that during card reading or card punching operations, the hopper
not being used for such operations must contain at least one card to prevent
the occurrence of the stop caused by ~ or 1 above.
PX 30
31
INPUT AND )UTPUT SYSTEMS
6.
UNIVAC LINE PRINTER.
a. GENERJlIL. - The Univac Line Printer equipment, in conjunction with the
lOB register and associated lOB control circuitry, provides a means of output
from the UnivClc Scientific Computer.
The Univac Line Printer equipment,
enclosed in a single cabinet (shown in Figure 7), comprises a Format Switchboard,
an External Control Panel, a cqrriage and platen assembly, print wheels, and
associated control mechanisms.
The medium of information representation is
printed paper on which the printed characters may be decimal numbers, letters,
a period, and a minus sign.
The paper is positioned in the printer on a
carriage similar to a typewriter carriage.
The characters chosen to be printed
on one line across the width of the paper are printed almost simultaneously,
with the design of the Line Printer allowing the printing of 150 such lines per
minute.
The spacing between lines is automatic, if so desired, during contdnuous printing of lines and may be manually set for one, two, or three spaces.
In addition, paper shifts (without printing) of multiples of three, six, and
nine spaces may be initiated by a sin'Jle computer instruction. Each line may
have any of the allowable characters printed in any of 92 columnar positions.
Each column has an associated print ~leel on which 35 characters are available
for printing. Each of the 34 numbers and letters below are present on each
print wheel. The period is present 0.1 the even-numbered print wheels 2, 4, 6,
etc., and the minus sign is present 0.1 the odd-numbered print wheels 1, 3, 5,
etc., thus allowing a period and a mi.lus sign to be printed in every other
columnar position on a line.
The ch:3racters to be printed in given columnar
positions on a given line are chosen :3ccording to an associated II-row, 92column coded i.mage as assumed in the <~omputer.
An image has the following coding for available characters.
ROW
CHARACTER
o
_
123456789ABCDEFGHJKLMNPQRSTUVWXYZor
--
11
I
- e-'
o
I
I
f
2
3
4
5
6
-
.
I
I
I
I
I
I
--I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
7
8
9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PX 30
32
I
I
I
I
I
I
I
INPUT AND OUTPUT SYSTEMS
Note:
Blank spaces denote zeros in the image as stored
in the computer.
The absence of "l'sft ill a column of the image results
in a space in the corresponding position on the paper;
or, if a mechanical setting is made on the printer, a
zero is printed in this position, provided that a print
selection was made for the position immediately to the
left. A maximum of approximately nine consecutive zeros
in a group may be printed in this fashion.
b. PROGRAMMING FOR OUTPUT. - Information is transmitted to the printer in
response to programmed External Function and External Write instructions. Each
row of the image is formed in the computer by positioning at three addressed
computer locations the bits for that row which are part of the code of the
characters to be printed.
Thus, 33 addressed locations are required to represent an image. The image is divided into three fields:
Field I consists
of the first or left-most 36 columns; Field II, the second 36 columns; and
Field III, the third or right-most 20 columns.
Three External Write instructions, which must be programmed consecutively, transmit the coded information
of each row of the image to the lOB Register, or, as follows.
lOB;
EWjv
( v ) ----to- X, (X)
EWjv
(v) ---..
X, (X) ------ lOB;
EWjv
( v)
X, (X) --+- lOB;
---II..-
----p-
( v 3c..J
VOl being Field I of Row r
VOl being Field II of Row r
v 16) being Field III of Row r
The three instructions are repeated for each of the 11 rows, the rows being
transmitted in the order r = 9, 8, ••• 1, 0, 11. All three instructions must be
executed even though there may not be information in all three fields to be
printed.
Between successive External Write instructions, the current content of lOB
must be transmitted to the Line Printer, allowing lOB to be cleared. Programming
a properly coded External Function instruction to precede the External Write
instructions initiates the operation of the Line Printer, allowing it to receive
information from lOB. Thus, for controlled operations of the Line Printer, the
External Function instruction places "ones" in selected stages of lOB.
The
stages selected, with the operations of the Line Printer which are initiated by
the EF instruetion and the presence of ones in these stages, are listed below.
10834 - Start (master bit)
Gauses one cycle of operation of the Line Printer and the aut0
matic advance of the paper lr 2, or 3 spaces unless the Stop
Paper or the Jump selection was also made.
lOB 13 -
4
~rump
Gauses the paper to advance nine spaces during a cycle of operation. (No printing permissible during this cycle)
PX 38
34
INPUT AND OUTPUT SYSTEMS
IOB12 - Skip
Causes the paper to advance according to the Format Switchboard
settings. (A Print selection is not permissible in an EF instruction which includes the Skip bit. )
IOBll - Interrupt
IOBIO - Print
Permits one line of characters (an 11 row image) to be sensed and
printed during a cycle of operation.
IOB 9
- Stop Paper
Stops the automatic advance of the paper during a cycle of operation.
Each cycle of operation of the Line Printer is divided into 15 points:
(9, 8, ••• , 1, 0, 11 ••• 14, 15), each point being 26.67 milliseconds in duration. During each of the 11 points (9, 8, ••• , I, 0, 11) of the cycle, a row
of the image is sensed by the printer provided three External Write instructions
are executed during this time and the lOB Print (and lOB Start) selections were
made by a previous External Function instruction. If these selections are in
effect, the series of transmissions to the Line Printer effected by the 33
External Write instructions positions the chosen print wheels. The characters
in position for printing are printed on paper sometime during or after the cycle
point six.
The automatic paper advance occurs before cycle point six.
The
number of spaces the paper is automatically advanced is determined by a switch
setting on the Format Switchboard which is discussed later.
Time factors that must be taken into consideration in programming for Line
Printer output are pointed out in the following program outline. A time lag
due to inertia when the printer is initially started may occur which will delay
the execution of the first 'point of the cycle of operation.
Note that an
External Write of Field I for Row 9 should immediately follow the External
Function instruction which starts the printer and, for Rows 8, ••• 0, lIt should
occur before or during the early part of the corresponding ten points.
Other
computer instructions may be programmed and executed between cycles and during
cycle points in t~e remaining available computer time.
To advance the paper and print one line
EF-v
(v)
= Start
Line Printer
Print
Within 1.5 ms of the beginning of the point the first EW
must be executed
EWjv
EWjv
EWjv
Other instructions
Write Field I
Write Field II
Write Field III
point 9,
26 .. 67 ms
PX 38
35
INPUT AND OUTPUT SYSTEMS
Within 1.5 ms of the beginning of each point, the first
EW must be executed
EWjv
EWjv
EWjv
Other instructions
Wrfte Field I
Write Field II
\'Iri te Fie ld I II
Repeat for
points 8, 7
• •• 0; each
26.67 ms
Within 1.5 ms of the beginning of the point, the first
EW must be executed
EWjv
EWjv
EWjv
Other instructions
Write Field I
Write Field II
Write Field III
point II,
26.67 ms
}
Other instructions
points 12, 13
14, IS, each
26.67 ms
Continuous printing of lines may be programmed by repeating the preceding
program the desired number of times with the instruction initiating each repeating cycle being programmed during point 12 of the preceding cycle. Thus,
for continuous operation of the Line Printer, the External Function instruction
to initiate a new cycle must be executed within 50 milliseconds of the Write
Field III instruction for row 11.
The selection of the Interrupt bit, IOBII, facilitates programming for
output to the Line Printer. A selection of IOBll' in the External Function
instruction in which IOB 34 , Start, and IOBIO, Print, are also selected
energizes an interrupt line in the printer so that an interrupt signal is sent
to the computer (interrupt) control each time a row of the card image is to be
sensed, i.e. at the beginning of cycle points 9, 8, ••• ,1, 0, 11. The first
External Write instruction must be executed within 1.5 milliseconds after the
interrupt signal is sent to the computer.
f
The interrupt selection may also be made by setting the interrupt switch
on the Line Printer to its ON position. With this setting the interrupt line
in the printer is energized as above when a Start and Print selection is made.
c. FORMAT SWITCHBOARD. - By. making the appropriate switch settings on the
Format Switchboard, the printing of lines in accordance with a chosen format
may be accomplished without executing External Function instructions to initiate
individual spacing operations of one, two, three, or nine lines. Skips of one,
two, three, six or nine spaces during one printer cycle, or consecutive skips
of these spacings during successive printer cycles, may be initiated by a
single computer instruction, after which the computer is free to execute any
other instructions.
PX 30
36
INPUT AND OUTPUT SYSTEMS
The ten columns of switches on the Format Switchboard provide a format
"count" control of available spacing operations. A spacing operation depends
upon the switch settings in the column corresponding to the format count.
The functions of the three portions of the switchboard:
and Multiply, and their switches, are explained below.
Control, Space,
(1) CONTROL. - A switcn in the Hold setting holds computer control of
spacing in effect until an External Function instruction containing Start
and Skip lOB Select bits is executed and the next format count position has an
Advance switch setting.
A printer cycle of operation initiated by such an EF
instruction is necessary to make the transition from computer control to
format control.
A switch in the Advance setting, in conjunction with Skip and
Start bits in the preceding EF, releases computer control of spacing, advances
the pape~ in the printer according to switch settings on the Space and Multiply
portions of the switchboard, and advances the format control count to the next
position. Adjacent switch settings of Advance in the Control portion will
automatically continue the format control count across the switchboard (to the
next count position with a Hold switch setting) with spacing occurring according
to the corresponding switch settings in Space and Multiply. (Spacing occurring
for a count position which has an Advance switch setting is defined as being
under "format spacing control rt.) A switch in the Clear setting advances the
format control count to the next count position disregarding any switch
settings in the Space and Multiply positions.
Switch settings of Advance or Clear in the first format control count
position, i.e., "home" count position, are not effective as described above.
This position has effectively an "automatic" Hold switch setting.
(2) SPACE. - Spacing between lines is affected by settings on the
Format Switchboard during both computer controlled and format controlled
spacings.
Under computer control the paper is advanced the number of spaces
according to the switch settings in the Space portion only of the Switchboard.
Under format spacing control the paper is advanced (with the exception noted
below) the number of spaces according to the switch settings in both the Space
and Multiply portions of the switchboard.
(3) MULTIPLY. - Under format spacing control the paper is advanced one,
two, or three spaces (according to the Space setting) if a Multiply switch is
in the OFF pOSition (unless a Stop Paper bit is in effect); or three, six, or
nine spaces (each space setting multiplied by three) if a Multiply switch is
in the ON position.
Note that the change from computer control to format spacing control requires one printer cycle, i.e., advancing from a Hold switchboard setting to
the first Advance switchboard setting requires a cycle of operation instigated
by an EF instruction with the Start and Skip bits. During this cycle of operation, the paper is advanced automatically one, two, or three spaces. This
spacing action must be considered in making switchboard settings in the Advance
switchboard position in order to effect the desired overall skip of spaces. The
Stop Paper bit could be programmed in the EF instruction which causes the change
to format control. However, if this is done, the Stop Paper bit effects paper
shift action under format spacing control (until the next Hold setting) as
PX 38
37
INFUT AND OUTPUT SYSTEMS
follows: if the Multiply switch is OJi'Fr no paper spacing results for that
particular format count position; if the Multiply switch is ON, a paper skip
of three, six, or nine spaces results for that particular count position.
The following listings show optio.lal spacings available under computer control and format control of spacing. If no spacing is to occur under format
spacing control, the forma t control c·)unt should be in the home count pos i tion.
(This is insured by depressing the Cl,~ar Control button for at least two
seconds.) The format switchboard settings under computer control below are for
this home position or any count position which has a Hold switch setting.
Under Computer Control
FORMAT SWITCHBOARD SETTINGS
CONTROL
SPACE
MULTIPLY
FUNCTION
lOB SELECT BITS
1.
Start, advance paper,
Hnd print (if desired)
Star t
Print (if desired)
Hold
1,2,or 3
2~
Start, stop advance of
Star·t,Stop Paper
paper,and print (if desired) Print (if desired)
Hold
1,2,or 3*
3.
Start and jump 9 spaces
without printing
Hold
1,2, or
Start, Jump
3~:c
OFF*
OFF*
Note that before printing the first line, the paper must be adjusted one,
two, or three spaces ahead of the position in which the first printing is desired unless the EF instruction contains a Stop Paper bit.
Under Format Spacing Control
FUNCTION
lOB SEWCT
BITS~:;~:;
FORMAT SWITCHBOARD SETTINGS
CONTROL
SPACE
MULTIPLY
4.
Single,Double, or Triple
Start, Skip
Space. advance format control
count to next position.
Advance
1,2,or 3
5.
Space six or nine,advance
format control count to
next position.
Start, Skip
Advance
2 or 3
ON
6.
No spacing, advance format
control count to next
positiono
Start, Skip
Clear
1,2,3*
OFF*
.'.".
These switch settings are not effective in setting up the function .
OFF
Included in a previous EF used for the transition from computer controlled
operation to format spacinu control. The effect of a Stop Paper bit included in this instruction is not shown here.
Functions I, 2, 3, 4, and 5 require timewise one print cycle.
Function 6 settings continuously across the board require a maximum of one
second to clear to the "home" position.
I'X 30
30
INPUT AND OUTPUT SYSTEMS
An optional format for Line Printer output is illustrated in Figure 8.
The form length used is 66 spaces, generally the number of spaces on the folded
pack paper commonly used. The following listing shows the selections necessary
to achieve the printing of a page in this format. (Each External Function
instruction must be followed by the appropriately coded External Write instructions. )
In this case a Stop Paper bit was included in the EF instructions
which effect the change from computer control to format control. Since the
paper skips desired under format control are multiples of three, the Multiply
switch in the Advance count positions is ON; hence the stop paper bit in effect
will not hinder the desired paper spacing action from occurring.
FORMAT
CONTHOL
"COUNT"
I
FORMAT SWITCHBOARD SETTINGS
CONTROL
HOLD
SPACE
1
SPACES
ADVANCED
MULTIPLY
OFF
18
lOB SELECT BITS
(In a total of 27 coded
EF-v instructions)
Start, Print (repeat this
coded EF 18 times)
Start, Stop Paper, Skip
2
ADVANCE
3
ON
9
3
ADVANCE
3
ON
9
4
HOLD
3
OFF
21
Start, Print (repeat this
coded EF 7 times)
Start, Stop Paper, Skip
5
ADVANCE
3
ON
9
6
CLEAR
1
OFF
o
7
CLEAR
1
OFF
o
8
CLEAR
1
OFF
o
9
CLEAR
1
OFF
o
10
CLEAR
I
OFF
o
Total of 66
spaces
d. OPERATION. - The procedures listed below should be followed to initiate
use of the Univac' Line Printer.
(1)
Set the Main Power switch on the External Control Panel to ON.
(2)
Check that the Stop switch on the External Control Panel is OFF.
(3)
Depress the Clear button on the External Control Panel.
PX 38
39
INPUT AND OUTPUT SYSTEMS
FORMAT
CONTROL
COUNT
1----------- 9
---- - - -
r
HPACES
----------1
--.-----.~ - - ~ - - - -------
18 LINES
PRINTfm
SINGLE
SPACE
2-~
(f)
l.&J
U
~
(f)
18
3-~
4-~
BPACES
CD
CD
-----------t----------TRIPLE:'! SPACE
--- 7
LINES
PRINTI~D
---------- 9
TRIPLE
SPACE - - -
If'
:,PACES - - - - - - - - - - - 1
________________1__________ _
Figure 8,
Optional Format for Line Printer Output
PX 38
40
:r:
I(!)
Z
l.&J
..J
INPUT AND OUTPUT SYSTEMS
(4)
Depress the Clear Control button on the Format Switchboard for at
least two seconds.
(5)
Insert paper in the platen assembly.
The following conditions require that the Clear Control on the Format Switchboard be depressed for at least two seconds to insure that the format control
count is back in the home position. These conditions are as follows:
(1)
Paper is being changed
(2)
A fault occurs
(3)
The format is changed
(4)
An improper program is scheduled.
During the operation of the Line printer four types of faults may occur
which are indicated visually by a light on the printer or a FAULT indication on
the Supervisory Control Panel of the computer. These faults are as follows:
(1)
NO PAPER FAULT. - If the paper in the Line Printer is almost
depleted, a fault circuit stops the computer and gives a No Paper
fault indication on the printer control panel. Pressing the Clear
button on the printer clears the fault. Starting computations anew
will initiate a second fault condition. Since a No Paper fault
occurs slightly before the end of the paper has passed the printing
position, several more lines, depending on the spacing, may be
printed. This fault becomes effective after the current cycle is
completed, thus no information will be lost.
(2)
MECHANI.CAL JAM FAULT. - If the printer stops before completing a
cycle, a B Fault stops the computer and printer and is indicated by
the 10 light on the Supervisory Control Panel. There is a possibility that this fault may be cleared by pressing the Master Clear
button on the computer.
(3)
NO INFORMATION FAULT. - If lOB does not contain the Field I portion
of a row (i.e., the first EW instruction has not been executed)
within 1.5 milliseconds after the start of a cycle point, a B Fault
occurs. The Line Printer completes the cycle before stopping but
will print erroneously since no further EW instructions occur within the cycle.
(4)
OVERHEAT FAULT. - This fault will cause an A Fault computer stop.
Operations may be resumed temporarily without loss of information
by setting the BYPASS INTERLOCK switch on the Supervisory Control
Panel, pressing the CLEAR A FAULT button, and pressing the START
button on the computer.
PX 38
41
INPUT AND OOTPUT SYSTEMS
7.
MAGNETIC TAPE SYSTEM
a. GENERAL DESCRIPTION. - The Magnetic Tape System of the Univac Scientific
Computer System comprises a number of Uniservo tape handling mechanisms, which
are located externally to the computer, and an electronic control section which
is located in the computer structure.
The number of Uniservos used is optional
up to a maximum of ten functional units.
By means of manual selections the
unit designations may be assigned in any manner to the functional units. Use
of the Uniservo units makes possible off-line processing of information by a
variety of Univ~c peripheral equipments.
For input to the Univac Scientific, information may be recorded on tape in
three forms:
Fixed Block Length Recording
Variable Block Length Recording
Continuous Data Input Recording
Output information from the Univac Scientific may be recorded on tape in the
Fixed Block Length Recording form and the Variable Block Length Recording form.
The Fixed Block Length mode is standard with the Magnetic Tape System.
Optional Control circuitry may be added to provide both the Variable Block
Length mode and the Continuous Data Input mode.
The Variable Block Length mode reads and records information on tape in
blocks of variable length.
A block of information is recognized by a oneinch space preceding it and following it :in which no information is recorded.
The length of the block is limited only in that the data input from it must not
exceed the capacity of high speed storagen
The Continuous Data Input mode reads information recorded continuously on
the tape with the only limitation on the length of a "block" of information
being the length of the tape. This form of recording is useful for real time
observations which will not permit interruptions to format the information in
fixed or variable block lengths. Data input from tape recorded in this manner
would need be interrupted when the capacity of high speed storage is reached.
The Fixed Block Length mode reads and records information on the tape in
blocks of fixed length. The remainder of the remarks in this description apply
in particular to this mode of operating.
(1) TAPE CHARACTERISTICS. - Unitape is the metallic tape used by the
tape handling equipment in recording and reading information. Information is
recorded as magnetized areas in eight channels across the width of the tape.
Data bits are recorded in six of these channels; one channel contains parity
check bits on the six data channels; and one channel contains sprocket, or
timing, signals.
A Uniservo is a unit of tape handling equipment. A Uniservo comprises a
read/write head, an erase head, a bad spot (in the tape) detector, and tape
handling mechanism such as the tape reel mount, reel drives, etc. In a reading
42
INPUT AND OUTPUT SYSTEMS
operation the read/write head detects ttl's" recorded on the forward or backward
moving tape; in a writing operation the read/write head records both "D's" and
"l's" on the forward moving tape. During a writing operation the erase head is
also activated such that the tape in its passage through the erase head has
"D's" written on it. The bad spot detector enables the Uniservo to interrupt
reading, moving, or writing operations until the undesirable tape area passes
the read/write head.
A tape speed of 100 inches per second is 'standard.
of a reel of tape is 1500 feet.
The approximate length
A column of eight binary digits across the width of a tape is termed a line;
the six data binary digits, a hexabit character. Lines are recorded on the tape
at a density of 128 lines per inch (standard) or 50 lines per inch.
A block consists of 720 consecutive lines;
a blockette consists of 120
consecutive lines. A "dead space" (in which no information is recorded) of 1.0
inch (standard) or 2.4 inches exists between blocks; a dead space of zero, 0.1,
or 1.0 inches exists between the six blockettes of a block. The optional recording formats are selected by program control in accordance with the intended
future use of the recorded tape, possibly with Univac auxiliary equipment.
When a stop of tape movement occurs, the tape is halted in the dead space
between blocks. Blockettes and blocks are recognized by the tape control section by counting the timing signals recorded on the tape. A timing device,
actuated in the last blockette, signifies the end of a block if the interval
between timing signals exceeds a certain length of time. The detection of the
end of a block in combination with a stop signal causes a halt of tape movement.
In terms of a 36-bit computer word, six lines are necessary for recording
one word. A block comprises 120 computer words; a blocket te comprises ~~O computer words. Thus, approximately 326,000 computer words may be stored on a
1500-foot reel of tape. The maximum transfer rate of information between the
computer and the tapes is approximately 1810 words per second.
This is assuming
a free-running tape, one-inch block spacing, and zero blockette spacing.
Average magnetic tape times for other block and blockette spacings are shown
in Table 7.
(2) PROGRAMMING TAPE OPERATIONS. - A programmed External Function
instruction (IT-V) initiates the various readirig, writing, and positioning
operations of the Uniservos. Coded information provided by the External Function instruction includes the following:
(a)
(b)
(c)
(d)
(e)
specification of optional recording mode if available
designation of the selected Uniservo
type of tape operation to be performed
type of recording format for writing, i.e., block and
blockette spacing and recording pulse density.
number of blocks to be moved without reading or writing.
The External Function instruction transfers the content of its v-address to
the Input/Output Register, lOB. The 36-bit word thus introduced into 1013 designates the magnetic tape operation to be performed. The "Select Magnetic Tape u
PX 38
43
TABLE 7
AVERAGE MAGNETIC TAPE TIMES
To estimate running times of programs using magnetic tapes
Recording Density
(lines per inch)
128
128
128
128
128
128
Block Space
(inches)
1
1
1
2.4
2.4
2.4
Blockette Space
(inches)
none
0.1
1.0
none
0.1
1.0
Block Length
(including block space
in inches)
6.625
7.125
11.625
8.025
8.525
13.025
i
Rate
Block Period* (36-bi t lAJOrds
(milliseconds) per second)
66.25
71.25
116.25
80.25
85.25
130.25
1811
1684
1032
1495
1408
921
H
:2:
""0
c::
1-3
::t>
50
~
~()
--
~
..t::..
..t::..
50
50
50
50
~
0
1
none
1
()
1
2.4
2.4
2.4
.........1
1.0
none
0.1
1.0
15.4
1
~
.LV.
0
,I
20.4
16.8
17.3
21.8
154.0
,r::n (\
779
...,t=t=
.LvI. V
lo.Jo.J
204.0
168.0
173.0
218.0
588
714
694
550
:2:
0
-..
a
H
"'"0
c::
H
C/).
I- 720 count is detected, the 720 check failure is
stopping action or error indication is effected.
>
A change in the bias level needs to be programmed only when an incorrect
reading operation h~s occurred.
Reading forward and backward at the high and
low bias levels may accomplish a correct reading of the block. It is not
permissible to program any other tape operation in the instruction which specifies a change in bias.
The return to the normal reading bias level must also
be programmed unless a computer Master Clear occurs which also accomplishes this.
Both the Rewind and Rewind with Interlock operations cause the tape on the
Uniservo specified to be positioned to its leader position. A Uniservo whose
tape has been rewound with interlock cannot be referenced effectively until the
Uniservo door interlock switch has been opened and closed. This occurs when
the Uniservo is provided with another tape.
After the Rewind and Rewind with Interlock operations are through their
initiation phase, another tape operation on a different Uniservo may be started.
Thus, any number of Uniservos may be rewinding concurrently. If a tape operation is desired on a Uniservo which is rewinding when this tape operation is
initiated, the tape operation is held up until the rewinding is completed.
Then, if the tape has not been rewound with interlock the tape operation is
resumed and completed.
It is not possible to execute correctly a second tape operation on any
Uniservo while a previous one is still in progress unless the tape operation in
progress is a rewind operation.
(2) GLOSSARY. - The following glossary lists terms pertaining to the
magnetic tape system. A brief description is given of the primary function of
the principal registers and counters involved in tape control.
Figures 9, 10, and 11, following ~he glossary, illustrate the use of the
registers and counters and the sequence of events, in write, read, and move
operations.
Read/Write head - Binary digits are represented in channels across the width of
the tape as areas magnetized in opposite directions. In a writing operation areas in the channels on the forward moving tape are magnetized in
the "0" direction except when pulses are received by the read/write head
from tape control in which case areas are magnetized in the "1" direction.
In a reading operation the read/write head, as it detects in the
channels the areas magnetized in the "1" direction, directs pulses to be
sent to tape control. Accurate detection occurs when the backward or forward moving tape has reached its free-running rate (100 inches per second).
Erase head - during a writing operation, the erase head magnetizes in the "0"
direction the entire width of the tape in its passage 'under the erase head.
The position of the erase head several inches ~rom the read/write head is
such that the traversal of the tape in a forward direction is first under
the erase head and then under the read/write head. This guarantees a
"clean" portion of the tape on which to write.
PX 38
51
INPrT AND OUTPUT SYSTEMS
Tape Leader - the plastic length of the tape which precedes the metallic length
of the tape on which information can be recorded.
Ringed tape - A tape reel fitted with a ring which prevents writing on this tape
and in so doing provides indication of this condition. This feature is to
be made available in the near future.
Writing Oscillator - emits pulses at the rate of one approximately every 80 ~s
(for writ.ing 128 lines/inch) or one every 200 ~s (for writing 50 lines/inch).
The rate depends upon the selection made for density of lines in a writing
operation. An oscillator pulse (in conjunction with other conditions)
initiates the writing of a line.
Sprocket Pulse - formed by sensing the sprocket channel as a line of tape moves
past the read/write head in a reading or moving operation. After a short
delay the sprocket pulse is instrumental in a reading operation in routing
the information read from that line of tape to the computer. In a moving
operation each sprocket pulse is used to form a count of lines moved.
Parity bit - recorded on each line of tape during a writing operation and used
as a check on the accuracy of reading each line of tape. The parity bit
generated during writing a character (six data bits) is a "1" if the number
of "1 'sIt :in the character is even and a "0" if the number of "1 'sIt is odd.
The sum of the data bits and the parity bit should be odd.
Bad Spot Control
Bad Spot on tape - Areas on the tape on which no recording should be attempted
are marked as "bad spots". Holes punched in the tape preceding, following,
and in the bad spot area are sensed by photoelectric tape readers during
tape movement.
During a reading operation, Bad Spot Control interprets the
position of these holes and temporarily stops any transmissions from tape
until the bad spot is passed; during a moving operation Bad Spot Control
stops temporarily the counting procedure of the lines moved; during a
writing operation, Bad Spot Control temporarily stops oscillator pulses from
initiating the writing of a line.
Reading Bias .- the voltage applied to the :cead/wri te head when reading from the
tape. By changing the bias level to higher or lower than normal, the read/
write head responds to weaker than normal signals on the tape or ignores objectionable "noise" factors on the tape.
Tape Control Register (TCR) - a 12-bit register in the tape control system which
receives the bits in IOB23-" IOB'12 when the bit in IOB31 is "1" (Select
Magnetic Tape bit).
The actual transmission lOB to TCR is held up (i.e.,
TCR is "locked out") until the tape control system signals that it is ready
to receive another operation code. The presence of operation bits in TCR
enables the various tape operations.
Block Counter (BK) - a 12-bit register in the tape control system which receives
the bits in 10Bll ••• IOB O on an lOB to TCR transmission as described above.
The content of BK is used to regulate the number of blocks (n) moved in a
Mo e Forward or Mo e Backward operation.
PX 38
52
INPUT AND OUTPUT SYSTEMS
Tape Register (TR) - a 36 bit register in the tape control system through which
words are routed in their transmission between tape and lOB. In a writing
operation six-bit segments of a word in TR (placed there by an Externcll
Write instruction) are positioned in TR5 ••• 0 and consequently written on
tape. In a reading operation, a word is assembled in TR until six lines
have been received; the transmission TR to lOB then occurs.
Align Input Register (AIR) - a seven bit register which receives six data bits
and the parity bit from a line of tape passing under the read/write.he~d
in a read or move operation.
In a reading operation the delayed sprocket
pulse formed by sensing the sprocket channel in the same line of tape causes
the transmission AIR5 ••. 0 to TR35 ••• 30. AIR is then cleared.
Tape Shift Counter (TSK) - a counter which regulates the shifting in TR of the
six aata bits of a line. On the completion of the shift of six bits (one
line) t a TSK Itend carry" is propagated which is interpreted as an "advance
LK" signal by the Line Counter; TSK is then cleared.
Line Counter (LK) - a counter which controls during reading and writing the
shifting in TR of the six lines of a word. In a reading operation, when
six lines have been assembled in TR, LK propagates a signal to effect
TR to lOB; an "advance WK" signal is sent to the Word Counter, and Til and
ft
[j{ are "cleared •
In a writing operation when six lines have been written
on tape from TR5 ••• 0, LK propagates a signal which clears TR and enables
the transmission lOB to TR (if lOB has been filled by an EW instruction);
an "advance WK" signal is sent to the Word Counter, and U( is "cleared".
In a moving operation U( is advanced by the receipt of a delayed
sprocket pulse. When six lines have been "moved", an "advance WK" silgnal
is sent to the Word Counter and LK is cleared.
Word Gounter (WK) - counts the number of words read, written, or moved until a
blockette count is reached; i.e., when a 20 word count is reached, an
"advance BTK" is sent to the Blockette Counter and WK is "cleared".
Blockette Counter (BTK) - counts the number of blockettes read, written, or
moved until a block count is reached; i.e., when a six blockette count is
reached, a "BTK end carry" is sent to various portions of tape control, and
BTK is "cleared". A BTK end carry is used during a moving operation to
subtract Itl" from the Block Counter.
PX 38
53
INPUT AND OUTPUT SYSTEMS
Start W r i t e - - - - - - - - - - - - - - - - - - l
I
delay fort block spacing
during tape acceleration
I
delay for spacing _____
between blocks
I
delay for spacing,
if any, between--------4
blockettes
I
I
.
re3 dy to wrIte
.~
I
'V
on next effective
OSCILLATOR PULSE:~
~
Check for No Information-- -~ - OR
Determine par.ity bit
I
Shift TR left 6 times
Write parity, sproc.ket,
r--~-"
and TR5." • 0
if EW executed:
if no EW:
Advance LK
lOB to TR
Set Stop enable
1_ _ _ _ _ _ _ _ _ _. .
Clear lOB
in TCR
I
I
line shifts
#
6
lOB Resume
Initiate fault
I
LK end carry---- - - - - - - ______ ---.J
(one word written)
1/
Clear TR
Advance HK
:/- 20 words
1
WK end carry
(20 words written)
Advance I1TK
:/- 720 words
BTf: end carry
(1 block written)
no stop
enable
Initiate Stop
*
Oscillator pulses do not effect any writing initiation during any of the delays
quoted and during the time the tape is moving througQ a bad spot. During a stop
initiation, oscillator pulses are made temporarily ineffectual by virtue of the
delay (for the inter-block space) caused by a BTl( end carry. During this
delay, a Master Clear from Stop Control renders them ineffectual until the
next Write Sequence.
Figure 9. Write Sequence
PX 38
54
INPUT AND OUTPUT SYSTEMS
Start Read/Move
No Stop
Read~Move
from Bad Spot Control
1
'f
Delayed Sprocket Pulse AND
Start Read/Move (initial or
from Bad Spot Control)
(AIR to TR 35 ••• 30 )
'"
Shift TR left six times
OR
Shift TR right six times
if error,
Che ck pa r it Y bi t -----r-e-a--=d-y-e-r-r-o-r--+i-nd-=-I-::-·c-a-t-;"iOiil
Advance LK
I
I
line shifts left ~ 6
OR
line shifts right ~5
I
'II
I
1 word (6 lines) in TR
LK end ca,rry
,
TR to lOB
lOB Read Acknowledge
Clear TR
Advance Word Counter
~
20 words read
I
'720 words read
BTK end carry
I
I.
receIve
I,
721 st
sprocket
pu\se
I
~
I
~ 6 blockettes
Block spacing detected
Indicate fault
I
I
I
20 words read
'~WK end carry
Advance Blockette Counter
1\
= 5
rsTK
I
I
W
Check for
L- __________ ~o~~able
f
I
~
;{~
I
II
.1.
V
lOA Read
Acknowledge
Set
lOA
I
I
~---i------
no stop, read next block
,II
any stop
Initiate Stop
Figure 10. Read Forward Backward Sequence
(Delayed sprocket pulse approximately 40 ~s after tape line to AIR)
PX 38
55
II
Indicate
faul t
j
INPUT AND OUTPUT SYSTEMS
Start Read/Move
-~~.--.-------..---------~
:-.--------'
No Stop Read/Move from Bad Spot Control
Delayed Sprocket Pulse AND
Start Reat/Move (initial or
from Bad Spot Control)
Advance LinJ Counter
line shifts left f. 6
1
LK end carry
I
Advance Word Counter
1
-:f 20 words
WK end carry
~
Advance Blockette Counter
=5
r BTl(
-:f 6 bl ocket tes
BTK end carry ---------1
Block spacing detected
(1 block moved)
,
~!mulate B~~K end carr_y ___ __ _
recei ve 721 st
'L_
-,
sprocket pul se
'f
t
Back Block Counter
BK -:f 0
Indicate fault
I
i
BK = 0
(n blocks moved)
II
W
t------~
Initiate Stop
Figure 11. Move Forward or Backward Sequence
(Delayed sprocket pulse approxirrately 40 J-Ls after tape line to AIR)
PX 38
~}6
INPUT AND OUTPUT SYSTEMS
a
A BTK end carry and a Stop enable initiates a tape stop
4
A stop initiation prevents a-nother lOB to TCR transmission
during which TCR is cleared.
for approximately 10 ms.
[Note that an, lOB to TCR transmiss ion can occur immediately
after the last BTK end carry (unless a Read or Write One
Block and Stop operation was programmed). Since TCR is not
yet cleared, no operation except a Stop should be programmed
immediately after reading or writing n (> 1) blocks
1
Move Uniservo j !! blocks, n> 0
1
When and if j is avai lable', the TCR lockout is set and
the lOB Resume is given.
2
BTK end carry clears the TCR lockout (T5K end carry resets
it) but lOB to TCR transmission is not allowed until TCR
is cleared, removing the Move enable.
~
A BTK end carry from the nth block and a Move enable from
TCR initiates a tape stop during which TCR is cleared.
Stop Reading or Writing of !! (>
1)
blocks
(Uniservo designation and read or write enable remain in TCR
from the read or write operation to be terminated.)
1
Since J IS availabl~, the TCR lockout is set and the lOB
Resume given.
2
The Stop enable now in TCR with the previous BTK end
carry initiates a tape stop during which TCR is cleared
and TCR lockout cleared. However, the stop initiation
prevents another lOB to TCR transmission for approximately
10 ms.
Rewind j or Rewind j with interlock
1
When and if j is available,TCR lockout is set and lOB
Resume is given.
£
When Rewind init iation is completed, TCR lockout is eleared
and TCR is cleared.
Bias Change
1
TCR lockout is not s,et
2
Bias Change completion after approximately 20 ms effects
lOB Resume and Clear TCR.
PX 38
57
INPUT AN]) ooTPUT SYSTEMS
c.
TAPE OPERATION TIMING.
(1) GENERAL. - Before a study is undertaken of the available computation times during tape operations, it is helpful to review the conditions which
are necessary during tape operations before
(a) An External Function, External Write, or External Read instruction can be executed following an EF tape instruction and
(b) the transmission lOB to TCR can occur after an EF tape instruction is exeeuted. (lOB is automatically cleared immediately after this transmission. )
The transmission X to 1013 during the execution of an EF or EW instruction is
not possible after the execution of a previous EF instruction until an lOB
Resume is recei~ed by lOB Control. (A lockout condition is established by lOB
when a sec~~d X to lOB transmission is attempted before an lOB Resume is received
from external equipment.
This prevents the use of lOB for a second output
operation before the first is completed.) No wait for an lOB Resume is necessary when an ER instruction follows an EF instruction since the attempted
execution of an ER instruction sets up an lOB lockout until information is received from external equipment (and this transmission is not received until a
tape operation is underway). An IeB Resume generated by tape control after an
EF instruction indicates that tape control has accepted the current content of
TCR as a tape operation.
Since this lOB Resume allows the loading of lOB by
8 second EF
instruction or an EW instruction, TCR must be protected against
receiving another lOB to Tca trans~ission until the first tape operation is
completed. This protection is provided by setting the "TCR Lockout" before
giving the lOB Resume. Then, since these transmissions are blocked, lOB may be
loaded safely by another EF or an EW (or an ER).
Since a Bias Change operation
does not effect a TCR lockout, it does not generate an lOB Resume until the
change of bias is completed.
After an EF tape instruction has been executed, the TCR lockout set up by
the previous tape operation must be removed before the operation code currently
in lOB can be transmitted to TCR. (In some cases, the removal of the TCR
lockout is not sufficient to allow the lOB to TCR transmission.)
It should be noted that if TCR has not been cleared previous to an lOB to
TCR transmission, the logical sum of lOB and the current content of TCR are
formed in TCR.
This is not allowable except when an EF stop instruction is
programmed to terminate a Read or VWrite operation.
The occurrence of these signals, lOB Resume, set TCR lockout, clear TCR
lockout, and clear TCR, during each of the legitimate tape operations is pointed
out below.
gead or. Writ~ Uniservo j (and stop)
1
When and if j is available, the TCR lockout is
set and the lOB Resume is given.
:~
A BTK end carry clears the TCR lockout. (TSK end
carry, if reading or writing is continued, resets
it. )
l'X 30
INPUT AND OUTPUT SYSTEMS
(2) AVAILABLE COMPUTATION TIMES.
(a) A tape operation becomes effective when the operation specification, as placed in lOB by an External Fun~tion instruction, is transmitted
to TCH. This transmission may not occur immediately after the execution of an
EF instruction.
The initiation of a tape stop on any Uniservo causes a Stop
Initiation delay which prevents for 10 ms the following:
lOB to TCR trans.,..
mission, lOB to BK transmission, and Clear lOB signal. Consequently, the emission of the lOB Resume signal is also detailed until this time, and lonqer it
a Change Bias operation is being initiated. During this 10 ms, an External
Function instruction may be executed but the tape operation is not initiated.
The attempt to execute an External Read or External Write instructio~, if a
read or write operation is to be initiated, or a second EF instruction,
establishes an lOB lockout condition until the lOB Resume is emitted.
(b) Between an External Function instruction for a read or write
operation on Uniservo jand the first External Read or External Write. It is
assumed that Uniservo j is immediately available.
Possible Stop Initiation delay*
Writing operation
10 ms (maximum)
Reading Operation
10 ms (maximum)
The following delays are incurred after a read or write operation is initiated,
but before a word is transmitted to lOB (in reading) or (in writing) before
tape control assumes a word has been received from lOB.
Tape Direction delays
normal
if movement is to be in
opposite direction from
previous movement
2.5 ms
2.5 ms
600 ms
600 ms
Leader delays
if tape is on leader
1500 ms
Block Spacing Delays
for one inch block spacing
for 2.4 inch block spacing
7.5 IllS
14.5 ms
1000
ms
5. 0 ms
5. 0 ms
t:~:~~
~:~~:~
The delays listed are "progressive", i.e., they are not initiated simultaneously.
The delays listed detain signals internal to the tape control system with the
exception of the block spacing delays listed for a reading operation.
*
If the EF Read or Write instruction immediately follows an EF Stop instruction
or the last ER or EW of a previous Read or Writ~ One Block and Stop operation.
See paragraph (a).
~:~~:; Actual reading of the tape does not begin until the tape is moving through
the read/write head at its free-running speed. The times quoted above are
acceleration times for the tape to reach this rate. These delays assume no
variation from a tape speed of 100 inches per second and are minimum times
for this speed.
The times of 7.5 or 14.5 are allowable assuming that block
spacing is exactly 1.0 or 2.4 inches and that tape movement is stopped exactly
in the middle of the block spacing. Only when the block spacing is known to
be consistently 2.4 inches can the 14.5 ms time be used.
PX 38
59
INPUT AND OUTPUT SYSTEMS
(c) Between successive External Read instructions or successive
External Write instructions:
at a recording density of 128 lines per inch
at a recording density of 50 lines per inch
436 microseconds
1168 microseconds
Tape moves at a rate of 100 inches per second. Therefore, for a recording
density of 128 lines per inch, 36-b:~t words are transferred to lOB (or sensed
from lOB) at the rate of one word every 468 microseconds (104 • 6/128 microseconds). When the execution time for the External Read (or External Write)
instruction is subtracted from this time, 436 microseconds remain for computation. The available computation times for other recording densities are
similarly computed.
(d) During the time a b:lock or blockette spacing is moving past
the read/write head:
Writing oQeration~:c Reading OQeration**
One inch inter -b lock or
9.968 ms
7.468 ms
inter-blockette space
2.4 inch inter-block space
0.1 inch inter-blockette space
23.968 ms
17.968 ms
.968 ms
.718 ms
(e) A maximum computation time of 250 microseconds can be used for
other than tape operations between the External Read or Write instruction which
reads the last word in the last bloek and the External Function instruction
which initiates a tape stop.
(f) Computation time available after a Move Forward or Move Backward
operation becomes effective (on lOB to TeR, lOB to BK). Another EF tape instruction may be executed immediate:~y but it will not become effective until
after times listed below.
Tape Direction delays
minimum 2.5 ms or
maximum 600 ms if tape movement is to
be in opposite direction from last
movement.
During a writing operation the writing pulses are cut off for 10,24, or 1 ms.
These times minus the .032 ms execution time of the External Write instruction yield the times quoted above.
** Again the reading rate is dependent on the tape speed and the length of the
inter-block and inter-blockette ~;paces.
It is ample to allow for a 25%
deviation in the length of spaces between blockettes and between blocks.
Thus, the minimum available computation time, assuming tape motion at the
rate of 100 inches per second ancl a space of 0.75 inches in length, is computed to be (7500 -.32) microseconds while a "one inch" block space is moving
by the read/write head.
PX 3b
60
INPUT AND OUTPUT SYSTEMS
Leader delay
or
Acceleration time*
1000 ms if tape positioned on leader
5 ms if tape not positioned on leader
Free-running time* for n blocks:
Block rate
recording density 128 lines/inch
recording density 50 lines/inch
Inter-block space rate
one inch inter-block space
2.4 inch inter-block space
Stop Ini tiation delay
n x 56.25 ms
n x 144.00 ms
(n-l) x 7.468 ms
(n-l) x 17.968 ms
10 ms
(g) Computation time available after a Rewind or Rewind with
Interlock operation becomes effective (on lOB to TCR). Another EF tape instruction may be executed immediately but the lOB to TCR transmission for this- operation is not allowed until after the times listed below:
Minimum 10 ms or
Maximum 600 ms if tape movement is to be in opposite direction from last
movement
In addition to the times quoted above, if the tape instruction follo~Ting a
Rewind instruction references the same Uniservo, this next instruction will not
become effective until the rewinding is completed. Maximum rewinding time is
approximately three minutes. In this case, this time also could be used ~dvan
tageously for other computations not referencing lOB.
(h) Computation time available after a Change Bias operation becomes
effective. The attempt to execute immediately another External Function instruction establishes an lOB lockout condition. There is a 20 ms delay after the
initiation of a bias change before another EF instruction can be executed to
its completion.
d.
OPERATION.
(I) OPERATION INDICATORS. - Tape operation is reflected by the condition
of indicators on the Uniservos, the tape control cabinet, and the left section of
the computer control panel. These indicators and their reactions to tape operation and tape operation faults are discussed in the following paragraphs.
(a) UNISERVO. - The "Ready" indicator (green) is between the tape
reel panel doors, upper center section of the Uniservo. This indicator is
illuminated when the Uniservo interlock circuit is energized; i.e., when power
has been applied to the Uniservo, when the tape reel panel door switch is set to
its ON position, and when the Forward Limit, Mylar Detector, Left Tape Loop, and
Right Tape Loop switches are in their normally closed position. If this indicator
is not illuminated, the Uniservo is not ready for operation.
* Assuming no variation from a tape speed of 100 inches per second.
PX 38
61
INPUT AND OUTPUT SYSTEMS
A failure to have the interlock eircuit not energized because power has not
been applied to the Uniservos would not usually occur. Power is normally applied
to the Uniservos (and the tape control system) at the same time power is turned
on for the computer. Normally, if it is noted that the "Ready" indicator is not
illuminated, the interlock circuit ili not energized because one of the switches
in the circuit is open. The condition which caused the switch to be opened must
be corrected before any operation on the unit can be undertaken. If operation
is attempted on a unit in which the :interlock circuit is not energized, a computer B-Fault condition is incurred. The interlock switches and the conditions
which cause them to open are discussed in the following paragraphs.
The tape ree 1 pane 1 door swi tch :is located immed i ate ly be low the "Ready"
indicator. This interlock switch mu:;t be set to OFF to open the left tape reel
panel door and cannot be returned to its ON position until the door is closed.
Effectively, then, opening the Uniser'ro door causes the "Heady" indicator to be
dropped.
The door must be closed and the door switch reset to ON before the
interlock circuit is energized.
A Mylar shim, or buffer tape, is inserted between the read-write head and
the metallic recording tape.
This ]llastic tape serves to reduce both tape
wear and friction. When this tape i:5 broken or the supply is exhausted, the
Mylar detector interlock switch is opened, dropping the "Ready" indicator. The
replacement of the Mylar tape by maiJltenance procedures closes this interlock
switch.
The Forward Limit interlock swit,~h is opened when the magnetic tape moves
into its "leader n area on its far end, i.e., the left-hand tape reel is depleted
and the right-hand tape reel c:ontain;) all of the tape. (The Forward Limit switch
is opened when the "rubber bumpers" ,)n the "leader" on the far end of the tape
are detected). To close this switch and energize the Uniservo interlock circuit,
the tape must be rewound past its "l(~ader'~ position. This is accomplished by
opening the panel door and manually "turning the reel in the counter-clockwise
direction several times (until the switch no longer makes contact with the rubber
Dumpers). The complete rewind ing 0 f the tape onto the left -hand ree 1 can then
be accomplished by the normal rewind operation which can be instigated manually
from the computer control panel or uader program control.
The Right and Left Tape Loop switches are opened when the tape loops are
out of normal position. This could be caused by tape breakage or possibly could
result from faulty operation of control circuits in the Uniservo. Maintenance
procedures are necessary to correct these conditions.
De-energizing the Uniservo interlock eircuit could also be caused by blowing
a fuse. A blown fuse in theUniservo cabinet is shown by the illumination of
the Fuse indicator.
Inside the right-hand tape reel ,joor, above the tape reel mounting, are
indicators labeled Rewind Interlock and Fault, Fuse and Temp.
The Fuse indicator is illuminate,j by H blown fuse.
This indicates that
some part of the Uniservo is i~perative and the Uniservo interlock circuit may
be de-energized. Detection and replacement of the blown fuse are maintenance
procedures.
PX 3U
62
INPUT AND OUTPUT SYSTEMS
The Temp. indicator is illuminated when a temperature rise above 120°F is
detected in the Uniservo. This condition causes a computer A Fault and illuminates the Temp indicator in the A Fault Group on the computer control panel.
Computer operation is halted by an A Fault condition.
Operation is resumed
after corrective maintenance by depressing the Clear A Fault button (unless a
B-Fault has resulted from tape reading or writing occurring at the time of the
computer stop. If this is the case, either (I), the MT fault indicator in the
B-Fault group on the computer control panel. and the No Information fault indicator in tape control cabinet are illuminated, or (2), the 10 fault indicator
in the B-Fault group on the computer control panel is illuminated).
The Rewind Interlock indicator is illuminated when the magnetic tape has
been rewound with interlock on the left-hand tape reel.
This condition indicates that the tape on this Uniservo should be replaced before this unit is used
again. Opening the door to replace this tape drops the "Ready" condition of
this unit (because the door switch must be set to OFF) and drops the rewound with
interlock condition.
Inside the right-hand tape reel door, above the tape reel mounting, are
indicators labeled Clutch, Stop (red) and Go (green). The Go indicator is
illuminated by the signal which is sent to the tape drive mechanism to pull in
the clutch and start tape movement.
This indicator remains illuminated until
a stop tape signal is received by the tape drive mechanism to operate the brake,
thus releasing the clutch.
At this time the Stop indicator is illuminated and
remains illuminated until the tape is re-started or until power is dropped from
the unit.
(b) TAPE CONTROL CABINET. - This cabinet is located immediately to
the left of the Power Supply Cabinet. Located inside the right-hand door are
tape fault indicators and the Logical Number Selection switches. Each Uniservo
is physically defined by one of the numbers 1, 2, ••• 10, depending upon the
number of Uniservos installed.
For instance, if an installation has eight
Uniservos, it would be expected that the numbers 1 ••• 8 would define the eight
units. The Logical Number selection switches are labeled Uniservo 1, Uniservo 2,
etc. ~ncircling the switches are the numbers 1 through 10. A Uniservo is
assigned a logical designation by turning the appropriate selection switch so
that the white line on the switch is in line with the number desired. The
n1.lmbers available for logical assignment depends upon the number of Uniservos
installed, i.e., if eight Uniservos are installed, any of these units may be
logically assigned any of the numbers one through eight. Thus, if the eight
Uniservos at an installation are physically defined as Uniservos 1 •.• 8, the
switches labeled Uniservo 9 and Uniservo 10 should be set to the logical designations of 9 and 10. It is not allowable for two switches to be set to the
same logical designation even though some of the switches define a non-existent
Uniservo.
The tape fault indicators (red) above the Logical Number Selection switches
are labeled. No Information, Sprocket Error, Selection Error, and Uniservo
Interlock. These indicators are illuminated by the detection of one of these
tape faults. These faults also cause the illumination of the MT indicator in
the B-Fault group on the computer control panel and cause a computer B-Fault stop.
PX 38
63
lNPUT AND OUTPUT SYSTEMS
The logical number Selection Error is caused at any time the computer is in
operation by setting two Logical Number Selection switches to the same number,
i.e., givin~r two "Uniservos" the same 10Uicai designation. The fault occurs regardless of whether or not the "Uniservo" is non-existent or out of service for
maintenance reasons.
This fault must be corrected before computer operation
can be resumed. Correcting the selection causes the Selection Error fault light
to be extinguished. Operation is resumed by depressing the Master Clear Button
(which drops the B-Fault light), making the desired selections on the computer
control panel, and depressing the computer Start button.
In order to prevent a Selection Error fault from occurring at the time of
making a logical number designation change, the computer operation must be
stopped.
Depressing the Force Stop button on the computer control panel will
allow a setting to be made safely.
Computation is re-started by depressing
the Start Button.
The Uniservo Interlock Fault is caused by referencing for a tape operation
a unit in which the interlock circuit is de-energized.
This condition is
shown on the unit referenced by the extinguishment of the "Ready" indicator.
The causes of this condition have already been discussed in the paragraphs discussing the "Ready" indicator and Uniservo interlock circuit. Computer operation can be resumed by depressing the Master Clear button, which extinguishes
both the MT and Uniservo Interlock indicators, making the desired selections
on the control panel, and depressing the Start button; but, if the cause of
the Uniservo Interlock fault is not corrected and the same unit is again referenced, the B-Fault will re-occur.
Correcting the Uniservo Int~rlock fault
during a B-Fault Stop extinguishes both the Uniservo Interlock indicator and
the MT fault indicator. Operation is resumed by depressing the Master Clear
button (which drops the B-Fault indicator), making the desired selections on
the control panel, and depressing the Start button.
The No Information and Sprocket Error faults are discussed later in the
fault section. These faults can be cleared, and their indicators, the MT Fault
indicator, and the B-Fault indicator are extinguished, by depressing the Master
Clear button on the computer.
When the occurrence of an MT B-Fault is noted, observing the condition of
the tape fault indicators in the tape control cabinet is an aid to diagnosing
the cause of the fault. Before the cabinet door is opened, the Bypass Cabinet
Interlock key in the Test Switch group, right section of the computer control
panel, must be turned to its Abnormal position.
The failure to do this before
opening a cabinet door causes an emergency power drop to the computer system,
and maintenance procedures are necessary to resume operation.
(c) SUPERVISORY CONTROL PANEL. - Represented on the left section
of the Supervisory Control Panel are components of the tape control system.
The banks of lights which assist the operator in manual operation of the Uniservos and aid in diagnosing certain of the fault conditions and computer operation "delays" are those labeled TCR, Tape Control Register, TR, Tape Register,
and BK, Block Counter.
The button labeled MT Test Start Step in the MT Test.
Writing Rate group is depressed to manually initiate a tape operation. The
illumination of one of the indicat()rs labeled MT Read Bias, high or low, shows
the selection of a read bias other than normal.
PX
64
~HJ
INPUT AND OUTPUT SYSTEMS
The bank of lights labeled Center Drive Control, Start and Stop, indicate
tape movement on the Uniservos. An indicat~r in the top row is illuminated by
an "operate clutch" signal to a particular unit; this indicator is extinguished
by an "operate brake" signal which illuminates the indicator in the bottom row.
The numbers below the ten pairs of indicators, between the "set" buttons (black)
and "clear" buttons (white) are the physical definitions of the Uniservos. If
the need for an immediate stop.of tape movement should arise, this can be
effected, if the computer is not in operation at the time or if operation is in
the Test mode, by depressing the "clear" button for the appropriate Uniservo.
(Depressing the computer Force Stop button stops operation.)
(2) PREPARATION FOR OPERATION. - The procedure for preparing for tape
operation under program control or manual control is as follows (assuming that
the Uniservos have been properly fitted with tape reels):
(a)
Determine whether those Logical Number Selection switches in
the tape control cabinet which physically define instalied
Uniservos have been set to the logical number designations used
in the program.
NOTE
(The numbers which can be used for logical designations
cannot exceed the number of installed Uniservos.) If
any logical designations are to be changed and the computer is in operation, the Force Stop button must be
depressed before making the switch changes to prevent
the occurrence of a Selection Error.
(b)
Check for the illumination of the green "Ready" indicators on
the Uniservos to be used. If this indicator is not illuminated,
the "not ready" condition must be corrected before this unit
can be used. Assuming that power has been applied to the
Uniservos, the attempt to use any unit not ready causes a
Uniservo Interlock B-Fault.
(c)
Check for the illumination of the Rewound Interlock indicators
on the Uniservos to be used.
This condition should be eliminated before attempting any operation on the Unisetvo. A tape
reference to a Uniservo which has a Rewound Interlock condition
causes a computer stall, and until this tape refer~nce is removed from tape control the attempt to eliminate the Rewound
Interlock condition causes a Uniservo Interlock B-F~ult.
The procedure to replace any rewound tape is as follows:
(a)
Turn the door switch to its OFF position and open the left
tape reel panel door.
(b)
The small spring clip connecting the magnetic tape and the
leader should be positioned immediately below the tape reel.
This connection is broken by spreading the sides of the spring
clip, thereby releasing its prongs from the small cylindrical
ending of the leader.
PX 38
65
INPUT AND OUTPUT SYSTEMS
(c) Pu 11 forward the ho:.ding latch on t he tape ree 1 mounting. This
releases a locking pin directly under the knob from its position
in one of the slots in the inner circumference of the tape reel.
Hemove the tape ree~. from the tape reel mounting.
(d) Place another rewound tape on the tape reel mounting so that
the tape winding is in the clockwise direction. Return the
holding latch to it~; closed position, first positioning the
tape reel so that the locking pin is inserted into any of the
slots in the inner circumference of the tape reel.
(e) Connect the magnetic tape to its leader by inserting the prongs
of the spring clip jn the cylindrical ending of the leader.
(f) Turn the tape reel counterclockwise until any tape slack is
taken up.
(g) Close the panel dool' and set the door switch to its ON position.
(3) MANUAL OPERATION. - To initiate tape operations from the computer
control panel, the computer must be set to operate in the Test mode. The operations which can be successfully comrlleted after a manual initiation are Rewind,
To initiate one
Rewind Interlock, Move Forward and Backward, and Change Bias.
of these operations, set the desirec: operation code and Uniservo selection
(except for a Change Bias operation) in TCR by depressing the appropriate "set"
(black) buttons.
(The white button is depressed to clear the register.)
Manual settings may be made any time the computer is not in operation and when
operation is in the Test mode. If ~I Move operation is desired, the number n
of blocks to be moved in inserted in BK. Depressing the MT Test Start Step
button then causes the specified tape operation.
At the completion of the Move F(lrward, Move Backward, and Change Bias
operations, the Tape COiltrol Register and the Block Counter are automatically
cleared. If the bias is changed to high or low, one of the bias indicators
(red) in the MT Test Writing Rate group is illuminated.
If a manual rewind
operation is performed, TCR is cleared when the rewind operation is initiated.
The failure of the registers to be cleared as expected after attempting a
manual operation could be due to one of the following reasons: (1) The Test
mode of operation was not selected; (2) for a rewind or move operation, no
Uniservo selection was made in TCR (Ir the Uniservo specified is not available;
(3) for a move operation, the block count set in TCR was greater than the
nmmber of blocks available for moving on the tape. This is evidenced by a reduced block count # 0 in BK and a Urliservo Interlock B-Fault if the move was
in a forward direction.
If a manual Move Forward or Move Backward operation is attempted without
inserting a block count in BK, TeR is cleared and no tape movement is initiated.
PX 38
66
INFUT AND OUTPUT SYSTEMS
e.
IMPROPER PROGRAMMING OR OPERATION.
(1) GENERAL. - Consideration must be given to the effects of improper·
programming and operation errors on both tape operation and computer operation.
In general, a program should run correctly if the equipment has been prepared
properly, the Uniservo designated is available, a legitimate tape operation has
been specified, the correct number of External Reads and External Writes have
been coded, a Stop has been coded to terminate a Read or Write operation, and
the timing restrictions have been noted in coding, in particular, the External
Read instructions, External Write instructions, and an EF Stop instruction. A
disregard for these requirements may result in an operation "delay" (a temporary
halt of operation) whic'h (1) may not be immediately noticed or l(2) may'cause
indirectly a computer fault; or a disregard for these requirements may cause
directly a computer fault. Any time computer operation is stopped, tape operation should be stopped to prevent the possibility of a "runaway" tape, i. e., a
tape which moves free of control to its "leader" pos i tion on the far end.
If erroneous operation is detected by the tape control system after tape
movement has been initiated, the tape control system effects the tape stop and
initiates a B-Fault computer stop. The tape stop occurs at the end of the block
(i.e., midway of the next interblock space) which was being read, written, or
moved at the time of the fault detection.
At the time the "stop tape" signal
is sent to the Uniservo, the Tape Register, Tape Control Register and tape
counters are cleared.
In some cases, the execution of computer instructions
may continue until the time of the actual computer stop, approximately 80 ms
after the detection of the tape fault. If this is the case, and an External
Function instruction for a tape operation is executed during this time, the
possiblity exists of starting another tape movement.
If this next EF instruction executed is an EF Stop (Read or Write) instruction, the lack of a Un:iservo
designation in TCR prevents the initiation of tape movement and effects an lOB
lockout condition.
For this reason, it is important that an EF stop instruction does not specify any particular Uniservo. If tape movement is started
erroneously, depressing the computer Master Clear button stops the tape movement.
(To stop tape movement without clearing any of the registers on the computer
control panel, a button in the Center D.rive Control can be depressed as described
in subparagraph entitled Supervisory Control Panel, Operation.)
When computer operation is stopped by a computer A-Fault, a B-Fault, a
Force Stop, or a Manually Selective programmed stop, any tape movement in progress at the time of the actual operation stop is halted (1) during a rewind
operation, at the completion of the rewind;
(2) during a move operation, at
the completion of the move; (3) during a read or write operation at the end of
the current block being read or written. This block is not read completely or
written correctly to completion since the appropriate number of External Reads
and External Writes are not executed.
In diagnosing the cause of an operation delay or computer fault, noting the
condition of the following indicators is helpful.
(a)
On the Supervisory Control Panel:
The registers in Magnetic Tape Control, in particular, TR, TCR, BK.
The lOB Register, located above TR.
PX 38
67
INPUT AND OUTPUT SYSTEMS
The Program Control Register (PCR) and Program Address Counter (PAK)
both located in the centE~r section of the control panel. At any
time,PCR holds the instrL~ction being executed and PAK holds the
address of the next instruction to be executed.
The 10 and MT fault indic;ators in the B Fault group, lower center
section of the control peinel. The illumination of the 10 fault
indicator indicates the occurrence of one of the lOB (or lOA)
external faults shown in the External Fault group, lower left section
of the control panel. Tbe illumination of the MT fault indicator
shows the occurrence of some other fault originating in the tape
system.
The Temp fault indicator in the A-Fault group.
An lOB lockout condition is shown by (1) the illumination of the
top-most light in the column labeled Wait External in the Pulse
Distribution Control group, center section of the control panel, and
(2) the presence of an EF:,EW or EF instruction in PCR.
1
(b)
The indicators on the Unj.servos:
Temp.
(c)
The Fault indicators in the tape control cabinet: No Information,
Sprocket Error, Selection Error, and Uniservo Interlock.
Note:
Ready, Rewind Interlock Fuse, and
The door of the Tape Control Cabinet
must not be opened without first
turning the Bypass Cabinet Door Interlock key (in the Test Disconnect switches,
right section of the computer control panel)
to it~: Abnormal position.
(2) TAPE OPERATION FAULTS. - The operation errors which may occur during
tape operation are listed below and cliscussed in detail subsequently.
Parity Check Error:
effects a stop of tape movement; caused by a reading
or recordinu error.
Temperature Fault:
effects a computer A-Fault;
equipment fault.
Uniservo Interlock:
effects a
equipment
c(~puter
operations error or
No Information:
effects a
c(~puter
10 Read Fault:
computer B-Fault; programming error.
Selection Error;
effects computer B-Fault;
operator's error
Sprocket Error:
effects computer B-Fault;
recording error
B-Fault;
f(lUlt~
613
B-Fault; programming error.
INPUT AND OUTPUT SYSTEMS
The detection of a parity check error does not effect a computer fault but
does effect a stop of tape movement.
At the completion of reading every block,
a check is made to determine if a parity error occurred in reading any of the
720 lines in the block. If one or more errors occurred, a "1" is set into stage
o of lOA and a tape stop is initiated. If no error was detected, only the lOA
Read Acknowledge signal is sent to lOA. Thus, lOA must be "read" and its content tested after reading every block. Computation .continues depending upon the
result of the test. If a parity check error is indicated, the block can be reread in the opposite direction, and read and re-read at the different bias levels.
If none of these passes effect a correct reading, a computer stop can be programmed to indicate the unsuccessful attempt to read the block correctly.
(a)
UNISER'lTO TEMPERATURE FAULT.
Indications: Illumination of the Temp A Fault indicator on
the computer control panel. Illumination 6f the Temp Fault indicator on a
Uniservo.
Diagnosis: The temperature.fault results from a temperature
rise above 120°F in any Uniservo. The occurrence of a Temp Fault during tape
operation does not interfere with the tape operation unless reading or writing
is occurring at the time of the computer stop. If this is the case, a computer
B Fault is also incurred. This is evidenced by the illumination of the MT
Fault indicator on the computer control panel and the No Information fault
. indicator in the Tape Control Cabinet, or the illumination of the lOB Fault
indicator on the computer control panel.
Resumption of Operation: If a B Fault has not occurred,
turning the Bypass Temperature Interlock key to its Abnormal position after the
computer stop has occurred allows resumption of the program in the Test mode
after the Clear A Fault button is depressed.
However, this procedure should
be undertaken with caution. To resume computation in the Normal mode, the Temp
fault must be corrected. The correction of the fault extinguishes the Temp
Fault indicator on the Uniservo. Operation is then resumed by depressing the
Clear A Fault button which extinguishes the Temp Fault indicator on the computer control panel.
If ~ B Fault condition exists, the A Fault is cleared by one of the procedures above; clearing the B Fault condition requires the depression of the
Master Clear button.
Operation is resumed according to the type of read or
write fault incurred. These faults are discussed subsequently.
(b) UNISERVO INTERLOCK FAULT
Indications: Illumination of MT fault indicator and B Fault
indicator in B Fault group, computer control panel. Illumination of Uniservo
Interlock fault indicator in tape control cabinet.
The "Ready" light on the
Uniservo in use at the time is extinguished.
Diagnosis: This fault is caused when a Uniservo interlock
circuit is de-energized and this particular Uniservo is referenced for tape
operation.
The conditions which cause the Uniservo interlock circuit to be
de-energized and the correction of these conditions are discussed in the
PX 38
69
INPUT AND OUTPUT SYSTEMS
Operation section in the paragraphs describing the "Ready" indicator on Uniservo
and the Uniservo interlock circui~. If the not ready condition is detected by
the attempt to initiate a tape operation, tape movement is not started. The
execution of computer instruction:; may continue until the time of the computer
fault stop. During this time, if External Write instructions are executed,
"writing" is performed on the stationary tape; if External Read instructions
are programmed to be executed, an lOB lockout condition is established.
If the Uniservo interlock cireuit is de-energized after a tape operation
and tape movement have been initi~ited, the execution of instructions continues
until the time of the computer fallit stop. Tape movement is stopped by virtue
of the drop of power on the circu:Lt.
Resumption of Operation: Depressing the computer Master Clear button
extinguishes the fault indicators and allows the resumption of operation. Correction of the fault condition is not necessary to resume operation, but if the
same Uniservo is referenced again, the fault will re-occur.
(c) NO INFORMATION FAIJLT: The failurp to have a word transferred
from the computer to TR results ill a NO INFORr.~.TION FAULT.
Indications: On the computer contro-I panel MT B fault indicator
is illuminated.
In the tape control cabinet, No Information fault indicator is
illuminated.
TCll is cleared by the fau It stop but may be filled by the execution of another EF tape instruction ~fore the computer is stopped. Tape movement is stopped at the end of the block being written when the error occurs.The
Computer is stopped approximately 80 ms after the completion of writing the
block in which the fault was deteeted.
Diagnosis:
This fault is caused by the failure to provide
120 External Writes to write a bl()ck or by the failure to execute in time an
External Write.
When this fault is detected by tape control, the stop code
bits are set in TCR and a B fault is initiated.
If the fault is caused by prouramming too few External Write instructions,
the bits of the missing words are written as zeros.
If the No Information fault i~: caused by the failure to execute an External
Write in time, the data bits of the lines written on tape at that particular
time will be zeros until the EW is executed; then, the transmission lOB to TR
occurs and the remainder of the lines written is taken from the current content
of TR.
If the block being written wh€~n the fault is incurred is not the last block
programmed to be written, the attE'mpt to execute the next group of External
Writes will cause an lOB lockout c:ondition. If this block was the last block
to be written in this particular writing operation, the execution of computer
instructions, including any Exterr.al Function instruction, may continue until
the time of the computer fault stop.
Resumption of Operation: All fault indicators are extinguished
by depressing the Master Clear button. After remaking selections, operation can
be resumed by depressing the Start button.
PX 3U
70
INPUT AND OUTPUT SYSTEMS
(d) 10 READ (lOB I) FAULT, i.e., Failure to execute a sufficient
number of External Reads: where 120 n·j (j=l •.. ), ERts programmed and an EF
stop programmed to terminate presumably the reading of the nth block: Fa:ilure
to execute an External Read in time.
Indications: Illumination of the lOB fault indicator and the
lOB I fault indicator. Tape movement is stopped at the end of the block being
read when the error occurs.
TCR is cleared by the fault stop but may be
filled by the execution of another EF tape instruction before the computer is
stopped. The computer is stopped approximately 80 ms after the fault is
detected.
Diagnosis: Each word received by lOB from the Tape Register
should be removed from lOB by an External Read instruction before the next
transmission from TR occurs.
If a second transmission occurs before lOB is
cleared by an ER, an lOB I computer B Fault is incurred. In a tape reading
operation this fault is caused by the failure to execute the sufficient number
of ERts, or it could occur when an ER is programmed to be executed too late.
If two or more External Reads are not programmed for reading a single block
or reading the last of a series of blocks, the tape is stopped at the end of
this block but computer instructions continue to be executed. The execution of
an External Function instruction during this time will transmit tape operation
codes to lOB which has not been cleared.
Thus, lOB will contain the logical
sum of its previous contents and the tape operation code, and these bits are
transmitted to TCR.
No prediction can be made as to whether or not a tape
operation will be initiated since both the operation code and the Uniservo
selection may have been changed.
If two or more External Reads are not programmed for reading any but the
last of a series of blocks, tape movement is stopped at the end of the block
and the execution of the second ER for the next block sets up an lOB lockout
condition which stops the execution of further instructions until the time of
the computer stop. (The execution of the first ER for the next block transmits
to storage from lOB the logical sum of the last two words of the last block. )
The lack (in the program) of one External Read in reading a single block
or the last of a series of blocks does not cause directly a computer fault;
but since lOB is not cleared before another EF instruction is executed at any
future time, the bits transferred from lOB to TCR at that time may not specify
the desired tape operation.
Again, a tape operation mayor may not be
initiated. If an EF Stop Read instruction is executed, the logical sum of lOB
and the specification of the read operation (currently in TCR) is formed in TCR.
If the Uniservo selection is changed, tape movement on this Uniservo is ~ot
stopped and tape movement on another Uniservo may be started.
The lack (in the program) of an External Read in reading any particular
block but the last could cause an lOB I fault at the beginning of the next block
or could be interpreted as a missing ER for the last block of the series.
If an External Read is not executed in time during the reading of any
block, tape movement is stopped at the end of this block and an lOB lockout
condition is caused by the execution of the "extra" ER at the end of this block.
This stops the execution of any further computer instructions until the computer
fault stop.
PX 38
71
INPUT AND OUTPUT SYSTEMS
Resumption of Operation: All fault indicators are extinguished
by depressinlJ the Master Clear button. Operation is resumed after remaking
basic selections by depressing the Start button.
(e) SELECTION ERROR
FAUL~.
Indications: Illumination of the MT and B fault indicators on
the computer control panel and the Selection Error indicator in the tape control
cabinet.
Diagnosis: This fault is caused by setting two of the Logical
Number Selection switches to the sarre number at any time the computer is in
actual operation. Any changes in logical designations should be made during a
computer stop.
Resumption of Operation: Operation cannot be resumed until the
logical designations are corrected. When this is done, the Selection Error
indicator is extinguished.
Depressing the Master Clear button extinguishes the
B fault indicator and allows resumption of operation.
. in moving,
(f) SPROCKET ERROH FAULT:
,. 720 line count.
In reading, > 720 or <
Indications: IVIT B Fault indicator illuminated.
indicator in tape control cabinet illuminated.
720 line count;
Sprocket Error
Tape movement is stopped at the end of the block recorded with the improper
A computer fault stop occurs approximately 80 ms after the
number of lines.
detection of the fault.
Diagnosis: A sprocket error results from (1) the detection of
a block spacing before a count of 7~:0 lines has been accumulated in reading or
moving, and (2) the reception of a sprocket signal from the tape after a 720
line count has been accumulated in reading or moving and before the block spacing
is detected. The detection of a < 720 line count during moving is ignored:
this condition propagates a "false" 720 line count to the tape control system.
During a reading operation, a < 720 line count means that an "extra"
External Read is executed at the ent. of the block. The execution of this ER
establishes an lOB lockout condition which prevents the execution of further
instructions until the computer is s.topped.
This lockout condition is indicated by an ER instruction in PCR.
During a reading operation if ~l > 720 line count occurs in a block which
is not the last of a group of block~: being read, the execution of an External
Read after tape movement is stopped establishes an lOB lockout condition and
prevents the execution of further irlstructions until the computer stop. If a
> 720 line count occurs in the J.ast block being read, another External
Function instruction may be executed before the computer stop occurs, and
another tape movement could be initiated. An additional word is sent to lOB
for each extra six lines recorded on tape, if such should be the case.
Then,
since lOB is not cleared before the computer fault stop, if an EF instruction
is executed, the logical sum of lOB and the tape operation specification is sent
to TCR.
t
PX 38
72
INPUT AND OUTPUT SYSTEMS
When a > 720 line count is detected during moving, computer instructions
may continue to be executed until the time of the computer stop.
Resumption of Operation:
Depression of the Master Clear button
extinguishes all fault indicators.
Operation may be resumed after remaking
basic selections by depressing the Start button.
PX 38
73
OPERATING THE COMPUTER
1.
GENERAL.
The Univac Scientific computer is set into operation by certain combinations
of selections made on the Supervisory Control Panel. An overall view of the
Supervisory Control Panel is presented in Figure 1.
The computer may be set
into high speed operation, or, if it is desired to manually superintend the
internal actions of the- computer and/or have a visual presentation of these
internal actions, step operation may be chosen. Those internal operations which
are represented on the Supervisory Control Panel, or which occur in components
of the computer represented on the Supervisory Control Panel, have as their
visual counterpart the occurrence of lights in the corresponding designated
positions. Thus, the contents of any of the registers represented may be noted
by interpreting the double rows of lights into a bioctal code as follows:
a light in the upper row represents a binary one in the stage as numbered; and
a light in the lower row represents a binary zero in that stage. Thus, each
group of three columns of lights represents an octal number.
In addition to the ability to oversee the operations of the computer as it
executes a program already internally stored, operations may be performed upon
information placed in the computer by manually setting it in the counterparts
of the proper registers on the Supervisory Control Panel.
The small button at
the lower right end of each register is depressed to clear the register
(lighting the lower row indicators);
the small button below each column of
two lights is depressed to place a "I" in the chosen st~ge of the register
(lighting the upper row indicator).
By following the proper procedure, the
contents of these registers may then be used as desired in computer operations.
Also, by following the proper procedure, instructions may be manually placed
in the computer by inserting them in the Supervisory Control Panel counterpart
of the PROGRAM CONTHOL-REGISTER (MCR, UAK, and VAK), and setting the MAIN PULSE
DISTRIBUTOR to zero.
If MPD is set at six, the first instruction to be executed
is taken from the address shown in PAK (as automatically or manually set).
In discussing the operating selections which are made on the Supervisory
Control Panel, the "group" designations listed below will be used.
Each group
is represented on the control panel by a set of pushbuttons, switches, and/or
indicator lights enclosed in white lines. As they are located on the lower
center section of the Supervisory Control Panel, Figure 2, from left to right,
the groups are:
Operating Rate Group
Selective Jumps Group
Selective Stops Group
Program Interrupt Control Group
Operating Group
B Fault Group (upper)
A Fault Group (lower)
PX 39
I
OPERATING THE COMPUTER
o
Figure 1.
Supervisory Control Panel, Overall View
PX 39
2
OPERATING THE COMPUTER
.u
., .!
1.J~~~;~
iel '. i
o
Figure 2.
Supervisory Control Panel, Center Section
PX 39
3
OPERATIl\G THE COMPUTER
As located on the· right section of the Supervisory Control Panel, Figure 3,
Test Switch Group.
As located on the left section of the Supervisory Control Panel,
MT Disconnect Switch Group.
2.
Figure 4,
OPERATION.
a. GENEHAL. - Computer operation is in one of two modes: NORMAL or TEST.
For each mode, selections are made rr.anually by depressing buttons and setting
switches. The NORMAL mode is automatically selected unless the TEST/NORMAL
swi tch (Test Swi tch Group) is set tel TEST, or the MD NORMAL/ABNORMAL 'Swi tch
(Test Switch Group) is set to ABNORN~L. Depression of any of the buttons in
the Operating Rate Group also places the computer in the TEST mode. Operation
at high speed is automatic in either the NORMAL or TEST modes.
If high speed
operation is not desired, a manual selection of step operation is necessary,
i.e., one of the three buttons labeled MANUAL STEP, or either of the buttons
labeled AUTOMATIC STEP (Operating RClte Group). (The depression of one of these
buttons automatically selects the TEST mode of operation regardless of the
TEST/NORMAL switch being set to NORMAL. )
The AUTOMATIC STEP RATE switch controls the time rate at which Automatic Step Operation or Automatic Step Clock
operations are performed.
This timing control is applied to the rate at which
instructions are executed if AUTOMATIC STEP OPERATION is selected. If
AUTOMATIC STEP CLOCK is selected, the clock pulse rate is regulated accordingly.
Timing during Manual Step operation~; is controlled by the selection of CLOCK,
DISTRIBUTOR, or OPERATION, and the filanual depression of the STEP button in the
Operating Group.
Each depre~sion of the STEP button releases, respectively,
one clock pulse, one distributor putse, or the sequence of pulses necessary to
the execution of one instruction. Hepression of the RELEASE button in the
Operating Rate Group releases any snlection made and returns the computer to
HIGH SPEED and to the NORMAL mode unless the TEST/NORMAL switch was actually
set to TEST.
Operation in the NORMAL
switches in the Test Switch
to their abnormal condition
mination of both the NORMAL
(Operating Group).
b.
mode is not possible if any of the disconnect
Group, or MT Disconnect Switch Group, are positioned
setting.. This condition is indicated by the illuindicator light and ABNORMAL condition light
NORMAL MODE OF OPERATION.
(1)
HIGH SPEED and NORMAL indicator lights are illuminated (Operating
and Operating Rate Groups).
(2)
Depress the MASTER CLEAR button (Operating Group).
(3)
Depress any SELECT JUMP or STOP buttons called for by the program.
The associated indicators will illuminate.
(4)
Depress the START button (Operating Group). The OPERATING indicator light is illuminat(~d and the lights in Step (a) remain
illuminated.
PX 39
4
OPERATING THE COMPUTER
o
Figure 3.
Supervisory Control Panel, Right Section
PX 39
5
OPERATING Tfm COMPUTER
o
Figure 4.
Supervisory Control Panel, Left Section
PX 39
6
OPERATING THE COMPUTER
If the OPERATING indicator does not illuminate in step (4), check the
ABNORMAL CONDITION indicator in the Operating Group. If this is illuminated,
one of the disconnect switches is set to its ABNORMAL position. Setting this
switch to its NORMAL position will extinguish the ABNORMAL CONDITION indicator
and allow a NORMAL mode start.
The depression of the MASTER CLEAR button in step (2) sets PAKto 40000 and
MPD to 6. Unless other selections are made by manually depressing buttons on
the control panel, the first instruction to be executed will be taken from drum
address 40000. Any other manual selections may be made also where buttons are
provided after depressing the MASTER CLEAR button and before depressing the
START button. After the START button has been depressed, no selections can be
made until a computer stop.
If the NORMAL indicator is not illuminated in step (1), the TEST indicator
will be illuminated indicating one of the following conditions:
(1)
If the HIGH SPEED indicator is not illuminated, one of the
MANUAL or AUTOMATIC STEP indicators is illuminated. Depressing
the RELEASE button in the Operating Rate Group illuminates the
NORMAL indicator.
(2)
The TEST/NORMAL switch or the MD NORMAL/ABNORMAL switch (Test Switch
Group) is in its "up" position. Setting these switches to their
"down" positions illuminates the NORMAL indicator.
All these conditions allow a computer start, but in the TEST mode.
Operation in the NORMAL mode is halted by an A Fault, B Fault, Force Stop,
or a programmed stop.
Indication of the operation halt is given by the drop of
the OPERATING indicator light.
If the fault is caused by the selection of an
abnormal condition during operation, the ABNORMAL CONDITION indicator will be
illuminated.
c.
TEST MODE OF OPERATION.
(1)
Depress the MASTER CLEAR button (Operating Group).
(2)
Select the TEST mode by setting the TEST/NORMAL switch to TEST or
the MD NORMAL/ABNORMAL switch to ABNORMAL (Test Switch Group). The
TEST indicator (Operating Group) is illuminated, the NORMAL indicator
is extinguished, and the HIGH SPEED indicator (Operating Group)
remains illuminated.
(3)
If other than high speed operation is desired, depress one of the
MANUAL or AUTOMATIC STEP buttons (Operating Rate Group). The appropriate indicator is illuminated. (Depression of any of these buttons
yields an automatic selection of the TEST mode regardless of whether
the TEST/NORMAL switch is set to TEST. )
(4)
Depress any SELECT JUMP or STOP buttons called for by the program.
(5)
Depress the START button (Operating Group).
is illuminated.
(6)
Depress the STEP button (Operating Group) if necessary.
PX 39
7
The OPERATING indicator
OPERATI'JG THE COMPUTER
If any of the disconnect switches in the Test Switch Group or the MT Disconnect Switch Group are set to thE~ir ABNORMAL position, the ABNORMAL indicators
(Operating Group and Test Switch Group) are illuminated.
The depression of the MASTER ClEAR button sets PAK to 40000 and MPD to 6.
Unless other selections are made by manually depressing buttons on the control
panel, the first instruction to be executed will be taken from drum address
40000, or, if the MD NORMAL/ABNORMAL switch is set to ABNORMAL, from the
reserve space on the drum. Any ottler manual selections can be made where
buttons are provided after depressing the MASTER CLEAR button. Manual selections can be made from the control panel while in the TEST mode when the computer is in actual operation.
OnE~ exception to this is that PAK cannot be
changed manually when the OPERATING indicator is illuminated.
To change a selection in the Operating Rate Group, computer operation must
be at a halt (the OPERATING indicat.or is extinguished); then, depressing the
RELEASE button cancels the previous: selection made and allows a new choice of
an operating rate.
Operation is halted by an A Fault, B Fault, Force Stop, or a programmed
stop and is indicated by the drop of the OPERATING indicator light.
d. JUMP AND STOP SELECTIONS •.. The manual selections necessary to effect
a programmed Manually Selective Jump, instruction 45 jv, with j = 1,2, or 3,
are made by depressing SELECT JUMP buttons in the Selective Jumps Group.
To
be effective the selections must bE~ made while the computer is not in actual
operation (when the OPERATING indicator is extinguished), either NORMAL or
TEST mode.
An effective manual s:election is indicated by the illumination
of the SELECTIVE JUMP, 1, 2, and/or 3 indicator.
To nullify a selection, the
appropriate RELEASE JUMP button is depressed.
This also must be done when the
computer is not in actual operation.
The manual selections necessary to effect a programmed Manually Selective
Stop, instruction 56 jv, with j = 1, 2, or 3, are made by depressing SELECT
STOP buttons in the Selective Stops. Group. A stop selection may be made during
actual computer operation, NORMAL or TEST mode, and is indicated by the illumination of the light immediately above the button depressed.
When a stop
occurs, it is indicated by the illumination of a SELECTIVE STOP light. (A
Manually Selective Stop instruction with j = 0 requires no manual selection.)
To cancel a stop selection, the appropriate RELEASE STOP button is depressed.
The release of a stop selection may also be made during actual computer operation, NORMAL or TEST mode.
A FORCE STOP selection made by depressing the button so entitled in the
Operating Group halts computer operation in either the TEST or NORMAL mode.
A force stop is indicated by the illumination of the FORCE STOP indicator light.
e. MANUAL INTERRUPT SELECTION. - An interrupt may be initiated manually by
depressing buttons in the Program Interrupt Control Group.
Two selections are
necessary to activate a line to thE! interrupt control of the computer.
Depressing the ENABLE button allows the line to be energized and illuminates the
INDICATE ENABLE LIGHT.
Depressinu the INITIATE button when the enable is
indicated by the light momentarily energizes the line. When the line is
PX 39
8
OPERATING THE COMPUTER
energized a signal is sent to the Program Interrupt Control to effect the
interrupt during the execution of the next instruction which ordinarily would
be concluded by the normal termination commands. Each time an interrupt is
desired, the INITIATE button must be depressed and the INDICATE ENABLE indicator
must be illuminated. Each time the line to the Program Interrupt Control is
energized, the INDICATE ENABLE light is extinguished. Also, depressing the
RELEASE button extinguishes the INDICATE ENABLE light and renders it impossible
to energize the interrupt line by depressing the INITIATE button.
3.
RESTORATION OF OPERATION AFTER STOPS.
The computer ceases operation at the occurrence of a programmed STOP, a
FORCE STOP, an EMERGENCY OFF, or a fault condition. The stops by classes are
discussed subsequently, and the steps necessary to resume operation noted.
a.
PROGRAMMED STOPS
(1) MANUALLY SELECTIVE STOP. -The Manually Selective Stop instruction
(56jv) stops the computer operation if the programmed j (0,1,2, or 3) agrees
with the selection made on the Supervisory Control Panel (no button selection
is provided for j = 0; the computer will always stop in this case). Whether
or not a stop occurs at the execution of this in$truction, the next instruction
will be taken from the v adpress.
When a stop occurs, the OPERATING indicator
is extinguished and the appropriate SELECTIVE STOP indicator (red) is illuminated ..
To resume operation, depress the START button.
(2) FINAL STOP. - The Program Stop instruction (57--) indicates the end
of the program. The SELECT STOP indicators and SELECTIVE JUMP indicators, if
illuminated, will remain illuminated, and the FINAL STOP indicator (Selective
Stops Group) is illuminated.
To resume operation, it is necessary to depress
the MASTER CLEAR button and follow the procedure for initiating computation in
one of the two computer modes.
b. FORCE STOP. - An unscheduled stop of the computer can be effected by
depressing the FORCE STOP button (Operating Group). The OPERATING indicator
is extinguished and the FORCE STOP indicator (Operating Group) is illuminated.
After the condition which prompted the stop has been corrected, operation is
resumed by pressing the START button. During operation if it is desired to
change any selection in the Operating Rate Group or Selective Jumps Groups,
depressing the FORCE STOP button allows the RELEASE buttons in either of these
groups to be depressed and a new selection to be made.
c.
EMERGENCY STOPS.
(1) MANUAL EMERGENCY STOP. - In cases of extreme emergency, such as a
fire, pressing the EMERGENCY OFF button on the Supervisory Control Panel removes
all voltages from the equipment. Since all power is removed, a program in process is halted and cannot be immediately resumed.
Since such a stop could
destroy information, it may be well to reload the program and data into the
sys~em after proper operation is restored by maintenance procedures.
(2) AUTOMATIC .EMERGENCY STOPS. - This s top, a Is 0 ca lIs
procedures to restore proper operation.'
PX 39
9
for rna intenance
OPERATING THE COMPUTER
d.
FAULT CONDITIONS.
(1) A FAULT. - An A Fault results in a computer stop which extinguishes
the OPERATING indicator and illuminates an A Fault indicator. The specific
fault is indicated by the illuminat~,on of one of the following indicators, the
first six of which are in the A Fault Group on the panel:
DIVIDE
SCC (Storage Class Control)
PRINT
TEMP. (Low
TE~perature
- 100°F)
WATER
OVERFLOW (only possible on Multiply Add instruction,
7~~ uv)
ABNORMAL CONDITION - Indicated by lights in Operating
Group and Test Switch Group
The A Fault does not alter the prog]~am in process so that after appropriate
corrective action, the operation can be resumed.
Generally, a DIVIDE,SCC, PUINT, or OVERFLOW fault indication is derived
from a program error.
First, check the appropriate instructions or operands.
If these are correct, an actual machine malfunction is the cause and should be
isolated and corrected.
Operation may be resumed after the Divide, Print, and
Overflow faults by depressing the CLEAR A FAULT button and then the START
button. If the program requires that the cause of these faults be corrected
before continuing the program, operation can be resumed (after the fault correction) with the instruction which caused the fault by inserting the address
of this instruction in PAK, setting MPD to 6, and depressing the START button.
An SCC fault results from
the particular circumstances.
the CLEAR A FAULT button, but
the condition that caused the
storage should be corrected.
the faulty instruction can be
sumed by depressing the START
a reference to some address not permissible under
The J\ Fault condition is cleared by depressing
operation cannot be resumed without correcting
fault" In most cases the faulty instruction in
After this has been accomplished, the address of
inserted in PAK, MPD set to 6, and operation rebut ton.
The TEMP. indication is the reslllt of a high air temperature at some point.
The high air temperature is indicated by the illumination of one of the amber
indicators mounted above the cabinet doors.
Corrective measures should be
applied immediately unless the urgency for problem results dictates that the
BYPASS TEMPERATURE INTERLOCK key sW:ltch should be turned. This allows the
problem to be continued despite the over-,temperature condition. The WATER
indication necessitates correcting il water pressure fault (over-pressure or
under-pressure condition) before the program can be resumed.
PK 39
10
OPERATING THE COMPUTER
If any of the disconnect switches is accidently or intentionally set to the
"up" position after operation has been initiated (in Normal mode only), the
ABNORMAL CONDITION indicators in the Test Switch Group and the Operating Group
are illuminated, and an A Fault condition occurs and stops computation. Movement of the switch to the normal position will correct the condition.
Operation is resumed after the correction of the Temperature, Water, and
Abnormal Condition faults by depressing the START button.
(2) B FAULT. - The B Fault results in a stop which manifests iself
much like a Program Stop in that it is necessary to MASTER CLEAR and restart
the program. The B FAULT indicator, and one of the indicators listed below,
are illuminated in the B Fault Group.
MCT (Main Control Translator)
VOLTAGE
10 (Input-Output)
MT (Magnetic Tape)
MATRIX DRIVE (An MC Fault)
The 10 fault indicates incorrect input/output procedure or faulty operation
of external equipment.
The illumination of the 10 Fault indicator and lOne of
the EXTERNAL FAULT indicators located on the left section of the control panel
indicates the improper use of IDA or lOB. The EXTERNAL FAULT indicators are
as follows:
IDA 1 Read
lOB 1 Read
IDA 2 Read
lOB 2 Read
These faults occur when there has been no indication that the particular register involved is ready for the information being received by it. If the fault
is due to an error in program timing considerations, an lOB 1 Read fault indicates that an External Read to transmit input information in lOB to X has not
been executed before additional input information is received by lOB from
external equipment; and an lOB 2 Read fault indicates that the external equipment has not received the information placed in lOB by an External Write or
External Function instruction before lOB receives input information from
external equipment.
The IDA 1 Read and IDA 2 Read faults indicate similar
conditions involving the IDA register.
The 10 fault, in conjunction with one of the External Faults above, generally indicates a program timing error. An 10 fault resulting from one of the
External Faults is cleared by depressing the MASTER CLEAR button. This extinguishes all the associated fault indicators and enables a restart of the program.
An 10 fault without one of the IDA/lOB faults could also result from a program
error. A check of the fault indicator lights on the external equipment being
used should reveal the nature of the fault. Faults originating in external
PX 39
11
OPERATING THE COMPUTER
equipment because of an incorrect program are cleared by depressing the MASTER
CLEAR button. This extinguishes both the 10 indicator and the B FAULT indicator
and allows a program restart.
FauIts arising from the improper operation of
external equipment are cleared by correcting the condition instigating the fault
and then depressing the MASTER CLEAH button.
The Master Clear extinguishes the
B FAULT indicator.
If the 10 fault indicator is still illuminated, the source
of the fault has not been removed and restarting the program will yield the
same fault stop.
Generally an MCT fault is due to a program error (an illegal operation
codeL
In this case the program in storage or the input tape should be
checked for accuracy.
If no errors are thus discovered, a machine malfunction
is indicated and must be corrected.
If the fault is due to a program error,
the MCT as well as the B FAULT indieators are cleared by a MASTER CLEAR.
The VOLTAGE, or MATRIX DRIVE indication necessitates corrective maintenance,
and an MT indication may require co:~rective maintenance, depending upon the
type of MT fault. The MT faults are discussed in the Input and Output section
of this volume and are explained in full in the volume supplied with the
Magnetic Tape System. The VOLTAGE, MATRIX DRIVE, and some of the MT faults
require correction at the source.
After these are cleared the specific fault
indicator will be extinguished, and the B FAULT indicator will be extinguished
by a MASTER CLEAR, allowing a program restart.
To summarize, in general, when a fault is caused by an improper program,
its fault indicator as well as the 13 FAULT indicator is extinguished by depressing the MASTER CLEAR button. If a fault is caused by a machine malfunction,
its fault indicator is extinguished by the correction of the fault, and the
MASTER CLEAH extinguishes the B FAULT indicator.
Since there may have been errors introduced to the program in process at
the time of the fault, it is necessary that a MASTER CLEAR be selected and computation be started anew.
If the content of any addresses have been altered
by the instructions during execution of that part of a program which was completed before the fault, it would be well to reload the computer before
attempting computation.
4.
MANUAL HEADING AND WRITING.
The following procedures in TEST mode are frequently used to manually
check portions of a stored program or enter a program into storage.
Also
included is a procedure for manually transferring a program from Magnetic Drum
Storage to Magnetic Core storage.
a~
MANUAL WRITING FROM THE Q REGISTER. - The procedure below can be used
to alter an existing program in storage or to insert a new program into storage
without using a tape reader. The new words are entered into storage via the
Q Register by the following steps.
Step l.
Step 2.
Depress ~~STER CLEAR (Operating Group)
Select MANUAL STEP OPERATION (Operating Rate
Group.
PX 39
12
OPERATING THE COMPUTER
Step
Step
Step
Step
Step
Step
3.
4.
5.
6.
7.
8.
Set MPD
Set MCR
Set UAK
Set VAK
Depress
Depress
to 0
to 75 (Repeat instruction)
to 50000 (set j to 5)
to 00000
START button (Operating Group)
STEP button (Operating Group)
Steps 4 through 8 set up an unterminated Repeat Sequence. Since j is 5,
only the v address will be advanced at the end of each storage reference.
Step
Step
Step
Step
Step
Step
Step
9.
10.
II.
12.
13.
14.
15.
Clear PCR (Clear MeR, UAK, and VAK)
Set MCR to 11 (Transmit Positive instruction)
Set UAK to Q address
Set VAK to first address to be written into
Set up in Q Register word to be written
Press STEP button
Clear Q Register
Steps 10 through 14 manually enter the word set up in Q at the selected
v address.
To continue writing in consecutive addresses, repeat steps 13, 14,
and 15 for each word to be written. If only a single word is to be written,
steps 4 through 9 and step 15 can be omitted since a Repeat operation is not
needed.
b. MANUAL READING ~O THE Q REGISTER. - The procedure below transmits the
contents of chosen storage registers to the Q Register with the words at consecutive addresses being displayed on the Supervisory Control Panel.
Step
Step
Step
Step
Step
Step
Step
Step
1.
2.
3.
4.
5.
6.
7.
8.
Depress MASTER CLEAR (Operating Group)
Select MANUAL STEP OPERATION (Operating Rate Group)
Set MPD to 0
Set MCR to 75 (Repeat instruction)
Set UAK to 60000 (set j to 6 )
Set VAK to 00000
Depress START button (Operating Group)
Depress STEP button (Operating Group)
Steps 4 through 8 set up an unterminated Repeat Sequence. Since j is 6,
only the u address will be advanced at the end of each storage reference.
Step
Step
Step
Step
Step
9.
10.
II.
12.
13.
Clear PCR (Clear MCR, UAK, and VAK)
Set MCR to 11 (Transmit Positive instruction)
Set UAK to addr~ss of first word to be read
Set VAK to'Q address
Depress STEP button
Steps 10 through 13 manually read the word at the selected u address to
the Q register where it is displayed for observation. Each time the STEP button
is pressed, a word from a consecutive u address will be displayed in Q. If
only a single word is to be read, steps 4 through 9 can be omitted since a
Repeat operation is not needed.
PX 39
13
OPERATING THE COMPUTER
c. PROGRAM CORRECTION. - If, in reading to the Q Register, an incorrect
word is noted, the following procedure is used to insert the correct word at
the proper address. (This procedure can be used whether or not a Repeat
sequence is being used in the manual reading.)
Step
Step
Step
Step
Step
Step
Step
Step
1.
:2.
:3.
4.
:5.
6.
7.
8.
Depress FORCE STOP button (Operating Group)
Clear Q
Clear UAK and VAK
Set UAK to Q address
Set VAK to address to be written into
Set up in Q Register word to be written
Depress START buttcln (Operating Group)
Depress STEP butto~ (Operating Group)
Steps 1 through 8 enter the correct word into storage.
reading process:
Step
Step
Step
Step
To return to the
9.
Clear UAK and VAK
10. Set UAK to next address to be read from
11. Set VAK to Q addres s
12. Depress STEP but tor,
Steps 9 through 12 return control. to the manual reading procedure.
d. MANUAL BLOCK TRANSFER. - To €~ffect a manual block transfer from
Magnetic Drum Storage to Magnetic Cote Storage, the following steps should be
performed.
Step
Step
Step
Step
Step
1.
:2.
3.
4.
:5.
Step 6.
Step 7.
Step 8.
Depress MASTER CLEJ\R (Operating Group)
Select MANUAL STEP OPERATION (Operating Rate Group)
Set MPD to 0
Set MCR to 75 (Rep€!at instruction)
Set UAK to 3n (set j to 3 and n to the number of words to be
transferred)
Set VAK to a w address containing a 56jv instruction
Depre"ss START button (Operating Group)
Depress STEP buttorl (Operating Group)
Steps 4 through 8 set up a terminated Repeat Sequence.
Since j is 3,
both the u address and the v address will be advanced at the end of each
storage reference.
Step
Step
Step
Step
Step
Step
Step
9.
10.
11.
12.
13.
14.
15.
Depress FORCE STOP button
Release MANUAL STEP OPERATION
Clear PCR (Clear MCR, UAK, and VAK)
Set MeR to 11 (Transmit Positive instruction)
Set UAK to initial MD address
Set VAK to initial Me address
Depress START button
PX 39
14
CODING FOR THE COMPUTER
I.
SUMMARY OF MACHINE CHARACTERISTICS.
GENERAL
Parallel mode of operation
Internal binary number system
Two address logic
WORD LENGTH
36 bits (binary digits)
NUMBER NOTATION
ttl's complement" binary system
PARALLEL ACCESS
REGISTERS
(ARITHMETIC
SECTION)
A
AR
AL
Q
X
72-bit Accumulator (A71' A70, ••. ,AO)
rightmost 36 bits of A (least significant)
leftmost 36 bits of A (most significant)
36-bit shifting register (Q35' Q34, ••• ,QO)
36-bit exchange register (X35, X34, •.. ,XO)
PARALLEL ACCESS
STORAGE
(INDIVIDUALLY
ADDRESSED)
RAS
4,096 words of Rapid Access Storage
12,288 words optionally available
16,384 words of Magnetic Drum Storage
ARRANGEMENT OF
MAGNETIC DRUM
STORAGE, MD
4,096 bits on each track
4,096 words on a group of 36 tracks
4 groups of tracks, giving 16,384 words
Variable interlace between the Storage Address
Register and angular location counter permits choice
of the angular interval between memory locations
having consecutive addresses.
ALLOCATION OF
ADDRESSES
RAS
MD
Q
A
MD
FIXED ADDRESS
ALLOCATION
Fl
F2
F3
00000-07777
10000-17777
20000-27777
30000-30777
31000-31777
32000-37777
40000-77777
00000
40001
00001
00002
(octal)
(octal)
(octal)
(octal)
(octal)
(octal)
(octal)
(octal)
(octal)
(octal)
(octal)
in
in
in
in
PX 40
1
4,096 words
4,096 words optional
4,096 words optional
illegal addresses
1 word
1 double length word
16,384 words
RAS, Rapid Access Storage or
Storage
RAS
HAS
MD
GODING FOR THE COMPUTER
COMPOSITION
OF AN
INSTRUCTION
WORD
Instruction word
Operation code
First execution address, u
Second execution address, v
SECTIONS OF
ADDRESSES
j
n
k
36
6
15
15
bits
bits
bits
bits
(i35,
(i35,
(i29,
(i14,
i34'
i34.
i28.
i13,
· .. ,
·.. ,
·.. ,
• • • t
iO)
i30)
i15)
iO)
one-digit octal number represented by u14, u13, u12.
four-digit octal number represented by ull' uIO' •.. , uO.
number of shifts, represented by v6, v5, ... , vo or u6,
uS, • • .,
uo·
NOTATION FOR
CONTENTS Of
REGISTERS-
Brackets are
(u)=36-bit
(Q)=36-bit
(A)=72-bit
(AR)=36-bit
(AL)=36-bit
DOUBLE -LENGTH
EXTENSIONS
D(u)=72-bit word whose right-hand 36 bits are (u) and
whose left-hand 36 bits are all alike and equal to
the left-most bit of (u).
S (u )=72- bi t wOI'd whos e right-hand 36 bi t s are (u) and
whose left-hand 36 bits are all zero.
D(Q), D(X), seQ), and sex) are similarly defined
L(Q)(u)=72-bit word whose left-hand 36 bits are zeros and
each of whose right-hand 36 bits is given by the bitby-bit product of the corresponding bits of (u) and (Q).
L(Q')(v)=72-bit word whose left-hand 36 bits are zeros
and each of ~hose right-hand 36 bits is given by the
bit-by-bit product of the corresponding bits of (v)
and the complement of (Q).
CONTROL REGISTERS
PAK Program Address Counter
SAR Storage Address Register
PeR Program Control Register
MCR Main Control Register
UAK U Address Counter
VAK V Address Counter
PROG RAM SEQUENCE
CONTROL
The complete operation for the execution of a computer
instruction consists of two parts.
Part one - the execution of the current instruction, CIa
Part t'wo - the acquisition of the next instruction, NI.
used
word
word
word
word
word
to
at
in
in
in
in
denote "contents of".
address u~
Q.
A.
AR.
ALo
Thus:
At the start of part one, the Program Control Registers
already contain CI as the result of the second part of
the previous operation, and (PAK) is y plus 1, where y
is the address from which CI was acquired.
During part two, NI is acquired from the address held in
PAK at the end of part one, and (PAK) is then increased
by one.
PX 40
2
CODING FOR THE COMPUTER
Thus, provided that CI does not call for a change in (PAK),
NI will be acquired from address y plus 1. In a normal
program sequence, successive instructions are obtained
from consecutive addresses.
A departure from the normal sequence is caJ led a "j ump't,
and is achieved by altering (PAK) during part one of an
operation. Instructions that call for a change in (PAK)
are called "jump" instructions.
INPUT-OUTPUT
REGISTERS
lOA
lOB
TWR
HPR
An in-out register of 8 stages.
An in-out register of 36 stages.
A typewriter register of 6 stages.
A high-speed punch register of 7 stages.
INPUT DEVICES
Photoelectric Paper Tape Reader
Punched Card Input-Output System
Other optional peripheral equipment
OUTPUT DEVICES
Electric Typewriter
High-Speed Paper Tape Punch
Punched Card Input/Output System
Univac Line Printer
Other optional peripheral equipment
PX 40
3
CODING FOR THE COMPUTER
X REGISTER
:36
BITS
HIGH SPEED
PAPER TAPE
PUNCH
GENERAL
OUTPUT
UNITS
Figure 1.
E LECTR IC
TYPEWRITER
Programmer's Simplified Block Diagram
PX 40
4
CODING FOR THE COMPUTER
TABLE 1.
REPERTOIRE OF INSTRUCTIONS
TPuv
11
TRANSMIT POSITIVE .
TMuv
12 TRANSMIT MAGNITUDE
I(u)~ v
TNuv
13 TRANSMIT NEGATIVE .
(u)'~ v
IPxx
14
TUuv
15 TRANSMIT U ADDRESS
(u29-15)~ v29-15
TVuv
16 TRANSMIT V ADDRESS
(u14-0)~ v14-0
EF-v
17 EXTERNAL FUNCTION.
Select Ext. Equipment and perform (v)
RAuv
21
[(u)
INTERPRET. . . .
REPLACE ADD .
u
LTj kv 22
LEFT
RSuv
REPLACE SUBTRACT
[(u) - (v~ u
CCuv 27
CONTROLLED COMPLEMENT .
[( u)
SPuk
31
SPLIT POSITIVE ENTRY
S(u)~A,
SAuk
32
SPLIT ADD . . . . • • .
(A) + S(u), Shift (A) by k
SNuk
33
SPLIT NEGATIVE ENTRY
[S(u~ '--.+A, Shift (A) by k
SSuk
34
SPLIT SUBTRACT
(A) - S( u), Shift (A) by k
ATuv
35 ADD AND TRANSMIT
[(A)
STuv
36 SUBTRACT AND TRANSMIT .
[(A) - D( v
RJuv
37
RETURN JUMP .
Y+
IJuv
41
INDEX JUMP
[D(U)-~~ At (A)f +, (A)f~u, take (v)
TJuv
42
THRESHOLD JUMP
(u) > (A), take (v) as NI
EJuv
43
EQUALITY JUMP
(u) =(A), take (v) as NI
QJuv
44
Q
23
TRANSMIT
+ (V~~
JUMP
Shift (A) by k;j=O, (AL)f~v;j=l, (AR)f--;'V
.
(±)
(v
~-?
U
Shift (A) by k
+ D(u)J~ v
l~u,
)]--7 v
take (v) as NI
(Q)+, take (v); (Q)-, take
. • . .
(u);
(Q) left 1
MJj v 45
MANUALLY SELECTIVE JUMP
j=O, or j=l,2,3, & MJS=, take (v)
SJuv
46
SIGN JUMP •
(A)-, take (u); (A)+, take
ZJuv
47 ZERO JUMP .
(A) # 0, take
PX 40
5
(u);
(v)
(A)=O, take (v)
CODING FOR THE COMPUTER
TABLE 1.
REPERTOIRE OF INSTRUCTIONS (CONCL'D)
L(Q)(u)--+v
QTuv 51
Q-CONTROLLED TRANSMIT .
QA uv
52
Q-CONTROLLED ADD
QSuv
53 Q-CONTROLLED SUBSTITUTE
[(L(Q)(u) + L(Q)'(v)]-.V
LAuk
54
D(u)--+A, Shift (A) by k, (A)f-+u
LQuk
55 LEFT SHIFT IN Q .
(u )--'Q, Shift (Q) by k, (Q) f--+u
MSjv
56
MANUALLY SELECTIVE STOP. .
j=O, stop; j=1,2,3, & MSS=, stop
FS--
57
FINAL STOP
Stop and indicate
PR-v
61
PRINT.
Typewriter performs code in v5-0
PUjv
63
PUNCH.
Punch (v5-0); j=l, 7th level also
MPuv
71
MULTIPLY
(u)(v) =
MAuv
72
MULTIPLY ADD
(A)i + (u)(v)
DVuv
73
DIVIDE
(A)i =
SFuv
74
SCALE FACTOR
Shift D(u) in A until
RPj nw 75
REPEAT
Execute Nl "n" times, jump to Fl
ERj v 76
EXTE RNAL READ . .
EWjv
[(A) + L(Q)( u)J ~ v
. . .
LEFT SHIFT IN A .
. . .
. . .
77 EXTERNAL WRITE
(A)
(u)
= (A)f
(Q)+(A)f,
(Q)~
v; (A)f=+R
A34~A35' (SK)~
=
j:=0, ( I OA )~ v; j 1, (lOB ) ~ v
j=O,
PX 40
6
(v)~IOA;
j=l,
(v)~IOB
v
CODING FOR THE COMPUTER
2.
WRITING A PROGRAM.
a. INTRODUCTION. - The word "coding" is usually used to indicate the
preparation of the explicit list of instructions that a computer must execute
in order to solve a particular problem. The person who does the coding may be
referred to as a "coder". The resultant list of instructions is referred to as
either a "routine" or, if the coded,product is part of a larger one, a "subroutine". Sometimes the term "programming" is used to refer to the process
described above as coding. Ordinarily, however, "programming" refers to a more
inclusive process, which includes not only the coding but the final stages of
formulation of the problem for the computer; i.e., the numerical analysis, the
-selection of computational procedures, the specification of input-output
formats, etc.
b. INSTRUCTION NOTATION. - In the following text the mnemonic notation
is used to indicate the operation code of an instruction. For example, ''TP''
is used instead of "11" to indicate the Transmit Positive instruction; "MP"
is used instead of "71", etc. The address portions of the instruction are
indicated by octal numbers. For example, the composite symbol
TP
01012
01013
denotes the Transmit Positive instruction calling for the transmission of the
contents of address 01012 to address 01013. If this were written in octal, it
would appear as
11 01012 01013.
In binary, it would appear as
001 001 000 001 000 001 010 000 001 000 001 011.
As illustrated above, it would be impractical to code using the binary system. For this reason, and because the conversion of numbers from base 2 to
base 8, and vice versa, is immediate, the octal number system is used in coding.
When preparing a routine, not only the instructions which are to be executed must be specified, but also the placement of these instructions in the
computer must be indicated. The storage location of an instruction in the
computer is referred to as the storage address of the instruction. It is
customary to indicate this address to the left of the notation for the instruction, as follows:
01010
TP
01012
01013.
It is common practice when displaying routines for exposition to give some
explanatory comment to the right of the instruction. In the following routine
the left column contains the location in storage. The central column contains
the contents of that location; for instance, an instruction or datum. The
right column indicates the author's reason for including this word in the routine.
PX 40
7
CODING FOR THE COMPUTER
Routine for replacing the data at 00101, 00102,
by the first backward difference of this data.
00110
00010
RS
00110
001)7
form backward difference
00011
RS
00010
00015
decrease (00010)
00012
EJ
00014
000)0
has (00010) reached (00014)1
00013
MJ
00000
00010
00014
RS
00100
00077
terminal dummy instruction
00015
00
00001
00001
constant (address decrement)
c. LOOPS. - The above is an example of a routine which has a "loop".
The loop in this case consists of the three instructions at 00010, 00011 and
00012. The first of these forms one of the backward differences and stores it
where the minuend of the subtraction was. The second instruction, the Replace
Subtract at address 00011, then modifies the instruction which forms the backward difference by decreasing both ·)f its addresses by 1. Thus, the next time
the loop is traversed and a backward difference is formed,it will be the
difference of the contents of the d,~creased addresses. The next instruction,
the Equality Jump, tests to see whether or not the loop has been traversed a
sufficient number of times. If equality exists between the most recently
modified content of address 00010 and the dummy instruction at address 00014,
the task has been completed and an (~xi t occurs to address 00000. If equali ty
does not exist, the next instructio:n at address 00013 is executed. This instruction provides a jump back to the be{linning of the loop at 00010, and the
whole process is repeated once more.
The above example illustrates O:le very important facet of coding; a number of the instructions in any rout.ine are always involved only indirectly
with the desired results. In this example, only one instruction, the first,
produces directly the first backwarlj difference. The others are concerned
with keeping the process going, advancing addresses, and testing to see if
the process has been completed. Sw~h instructions are frequently referred
to as "housekeeping" instructions. The functions of address modification,
terminal testing, and jump provisions are referred to as "housekeeping"
functions.
It is common practice to indicate the fact that certain instructions are
altered during the course of the coonputation by putting brackets around the
instruction or that part of it which is altered. Thus, the first line of the
above example could have properly been written as
00010
00110
or as
00010
RS
PX 40
8
00107]
CODING FOR THE COMPUTER
'The latter is less preferable then the former because it suggests that the addresses are independently modified, which is not true in this case. Bracketing the so-called modified instructions, or modified addresses, serves to call
attention to the fact that at some later time during the computation, the addresses may not be as they appear on the page. In particular, in the example
above, at the end of the subroutine the addresses at 00010 will have been modified to agree with those appearing at storage address 00014.
Addresses which are modified within a loop should generally be set to their
desired initial values by instructions prefacing each loop, i.e., the process
of "prestoration"; or by instructions following each loop, i.e, the process
of "restoration". (Restoration is less preferable than prestoration because
the restoration instructions may not be executed if a computer fault is incurred
during th~ loop.) If this is done the routine can be used any number of times
while it is in the memory without reloading it from a permanent storage device.
Note that the above example does not meet these specifications. Below is the
same example coded with such "self-restoring U properties. In this routine the
loop consists of the instructions at 00010, 00011, and 00012. Note that a different means is provided to terminate the loop. Note also the use of boxing
to indicate a loop,and the use of a straight line, following an unconditional
jump, to indicate a break in the sequential acquisition of the next instruction
to be executed.
Routine for replacing the data at 00101,00102, . . . , 00110
by the first backward difference of this data.
00006
TP
00017
00016
Prestore counter, (00016)
00007
TP
00014
00010
Prestore (00010)
00010
. 1[00
00000
00000]
Form backward difference
00011
RS
00010
00015
Decrease (00010)
00012
IJ
00016
00010]
All differences £ormed?
00013
MJ
00000
00000
Exit
00014
RS
00110
00107
Initial contents of 00010
00015
00
00001
00001
Constant (address decrement)
00016
00
00000
00000
Counter, initially n-l.
00017
00
00000
00006
Constant, n-l, initial value
of counter.
In this case the termination test is performed by an Index Jump instruction
which is executed after each traversal of the loop. Execution of the Index
Jump at address 00012 causes a "1" to be subtracted from the contents of 00016
and a test to be made to see if the result is negative. If the result is not
negative, a jump to address 00010 is made for another traversal of the loop.
Memory location 00016 is called a "counter" since it contains at each stop a
count-down tally of the number of traversals of the loop. If the Index Jump
instruction is at the end of a loop (which is to be traversed n times), this
counter should have an initial value of n-l. The quantity is a constant
PX 40
9
GODING FOR THE COMPUTER
stored at location 00017. Entry (If the routine at address 00006 causes this
quantity n-l to be transferred to the counter at location 00016. The termination test could also have been co(~d at the beginning of the loop. In this
case, h'owever, the ini tial value oT the counter should be "n" to effect n
traversals of the loop.
When the termination test indicates that the loop has been traversed n
times, the execution of the Index Jump instruction at address 00012 does not
cause a jump but allows the next instruction to be taken from 00013. The exit
instruction, a Manual Jump, is stored here.
Any of the conditional jumps, Index Jump, Threshold Jump, Equality Jump,
Q Jump, Sign Jump, or Zero Jump, (:an be used as the decision instruction to
determine the number of times a loop has been traversed.
In summary, a loop consists of four elements.
d.
(1)
A series of self-restoring operations which set up the loop for
the first traversal. These initial "housekeeping" instructions
place in a "counter" a number which determines the number of
times, n, that the computer will traverse the loop. The instructions also set in the routine the initial addresses of any
data referenced by the instructions within the loop.
(2)
The computational in~;tructions which lead to the sol ution of the
particular problem.
(3)
The "housekeeping" instructions which advance/decrease the addresses which referellce the data so that successive loop computations are performed on successive data.
(4)
The "housekeeping" instructions which advance/decrease the
counter, and the decj,sion instruction(s) which test the counter
to determine if the loop has been traversed n times.
SUBROUTINES.
(1) INTRODUCTION. - A portion of a routine which is complete in itself and can be isolated from the context of the larger routine is known as a
"subroutine". A subroutine is a ~;elf-contained list of instructions for executing some particular operation. If it contains the calculations necessary
to compute a function such as~, sine x, tan x, etc., it should be coded in
such a way that it may be used in a number of routines wherever such a function
is desired.
(2) SUBROUTINES WITH PARAMETERS. - In the case of subroutines which
are to be used in many different programs, absolute addresses may not be assigned to certain quantities~ These addresses are regarded as parameters of
the subroutine and chosen in accordance with the main program. In such a case
it is conventional to write, in lieu of an absolute address, some designation
for the quanti ty itself enclosed in braces. Thus, "{x}" means "the address
at which the quantity x is stored". For example, the instruction for
PX 40
10
CODING FOR THE COMPUTER
transmitting x to address 01033 would be written
TP
{x}
01033.
The following subroutine for adding two vectors together exemplifies the
use of parameters. The two vectors are denoted by x and y with coordinates
xi and Yi, respectively. The sum vector is denoted by z with coordinate zi.
Thus, it is necessary to form the sums
i = 1, 2, 3,
n.
00100
TP
00114
00117
set counter to n-l
00101
TU
00112
00104
set in {Xl}
00102
TU
00113
00105
set in {Yl}
00103
TV
00112
00105
set in {Zl}
00104
form
[{ Xi}]
[{:i}]}
00105
AT
[{y i}]
00106
RA
00104
00116 }
00107
RA
00105
00115
00110
IJ
00117
001041
termination test
00111
MJ
00000
[00000]
exit
00112
00
00113
00
00114
00
00115
Zi = xi + Yi
Advance i by 1
constant
00000
constant
00000
n-l
constant
00
00001
00001
constant
00116
00
00001
00000
constant
00117
00
[00000
00000]
counter
This subroutine assumes that tabular values of xi and Yi are stored in
consecutive order somewhere in the memory and that a table of values of zi
is to be stored in consecutive order in the memory. The constants located
at 00112 and 00113 are, in effect, parameters of this subroutine because
these constants give the addresses of xl and Yl, and the address where zl
is to be stored.
Another parameter of this subroutine is the terminal value of i (i=l, 2, 3,
- - -, n). The subroutine has a loop from 00104 to 00110 which needs to be
traversed n times.
PX 40
11
CODING FOR THE COMPUTER
(3) SUBROUTINE ENTRANCE Al\'D EXIT. - To make use of a subroutine, the
main routine must provide a jump tc the correct entry point of the subroutine,
and the subroutine must provide an exit back to the main routine. In the subroutine for adding two vectors the entry address is 00100. The v address
portion of the Manual Jump instruction at 00111 must be set to a jump-out address in the main routine.
The simplest method of entering a subroutine is to use the Return Jump instruction. To enter the above subroutine the instruction RJ 00111 00100 would
be written at address y in the main routine. Execution of this instruction
causes the quantity y + 1 to be placed in the v-address portion of 00111 and
the contents of 00100 to be taken as the next instruction. Thus, a return to
the main routine at address y + 1 is provided upon completion of the subroutine.
In this way the subroutine may be entered from many different points in the
main routine.
If a subroutine has parameters, these must be set up before it is executed.
The parameters may be inserted by instructions in the main routine. Thus, in
the subroutine for adding two vectors, the contents of addresses 00112 and
00113 could have been entered by instructions in the main routine. If the
parameters occur in many different instructions throughout a subroutine, the
subroutine itself will contain the instructions for inserting the parameters
in all necessary locations. Again in the subroutine for adding two vectors,
instructions 00100 through 00103 distribute the parameters throughout the
routine. Since each parameter is used only once, it would be as easy for the
main routine to set the parameters directly in addresses 00104 and 00105 as
to place them in addresses 00112 and 00113. However, when a parameter occurs
more than once in a subroutine, it is better that the main program insert the
parameter in a single location and the subroutine distribute it from there.
This avoids the possibility of a programner omitting some of the parameter
settings.
A convenient means of repeatedly executing a subroutine with a different
parameter each time is illustrated next. The subroutine is referenced by a
Return Jump instruction followed irrmediately by the list of parameters. Following the last parameter is the next instruction to be executed after the
repeated use of the subroutine.
Y
37
y+l
y+2
00
00
y+k
y+k+l
00
NI
Here the parameters ai and ni, i = 1, •. I, k, are for the following subroutine
for punching n + 1 consecutive words at addresses aj' j=i, i+l, ... , i+ni"
PX 40
12
CODING FOR THE COMPUTER
Subroutine for Punching n + 1 Consecutive Words
00010
MJ
00000
[00000]
00011
SP
00010
00017
Extrance
00012
TU
A
0001'3
y+l--'
00013
TP
00014
QT
00036
00015
ZJ
00016
00021 }
00016
SP
00013
00071
00017
TV
A
00010
00020
MJ
00000
00010
to exit instruction
00021
TU
Q
00023
ai~u
00022
TV
Q
00037
ni~00037
If (A)=O, this is a parameter; go to 00021
A
00025
If (A)#O, this is NI; go to 00016
}
Q
TP
address of 00013. (y+l) = PI
Q
00023
00024
Exit
j+k+l~v
( aj
address of 00010
address of 00023
)~ Q;
j
= 1,
i + 1, - - -, i +n i
00040
00041
set counter to punch 5 frames
Q
00006
shift to punch next two octal digits
00026
PU
00000
Q
00027
IJ
00041
0002 5 1
have 5 frames been punched?
00030
LQ
Q
00006
shift to punch last two octal digits
00031
PU
Q
Q
00032
RA
00023
00042
increase (00023) to picI<: up next word
00033
IJ
00037
000231
have ni+1 words been punched?
00034
RA
00013
00042
increase (00013) to pick up next parameter
00035
MJ
00000
00013
return to pick up next parameter
00036
77
00000
00000
mask to detect parameter
00037
[00
00000
00040
00
00000
00004
initial value of counter, 00041
00041
[00
00000
oooooJ
counter for number of frames per word
00042
00
00001
00000
constant to augment u address
punch
punch with 7th level to show end of word
counter for number of words to be punched
PX 40
13
CODING FOR THE COMPUTER
The Return Jump instruction at address y places y + 1 in the v-address
portion of 00010. Therefore the subroutine can recover from 00010 the address
of the first parameter, Pl. Instructions 00014 and 00015 test the content of
y + 1 to see if it is a parameter o~ if it is the next instruction. This test
is based on the fact that there is 110 operation code "00". When "NI" is detected, the exit in 00010 is to y+k+l.
Note that this device permits listing any number k of parameters. The
mechanics may easily be varied to accomod.ate sets of parameters of any form,
e.g., sets of parameters which occupy more than one word. Different methods
of detecting the end of the parameter list are possible.
The Univac Scientific instruction repertoire includes the Interpret
instruction for referencing subrout:Lnes with parameters. An Interpret instruction at address y places y + 1 in the v address of Fl and takes (F2) as
the next instruction. In other words, the operation code of the Interpret
instruction in itself indicates the same operation as the instruction
RJ 00000 00001. The advantage of the Interpret instruction lies in the availability of 10 octal digits in which ~nformation may be stored. Address F2
contains a jump to a subroutine whieh uses the information in the Interpret
instruction as parameters for its operation. The subroutine can set up its
own exit from the v address of Flo
Frequently, complex systems of pseudo-coding are built around the Interpret
instruction. These "interpretive systems" simplify the job of progranuning for
a computer because of the use of pSE!udo-instructions whose functions define
operations which are actually carried out by a series of ordinary machine instructions. Such series of stored instructions are in the form of stored
subroutines, the operations of which are initiated by the interpretation of
the pseudo-instructions.
Chief among the Interpretive sy~:tems are those providing for arithmetic
operations on floating binary point numbers. (See subparagraph c.) In a
typical system, the Interpret instruction is composed as follows, each character denoting an octal digit:
IP
RA
Here the pseudo-code "RAIt refers to the Replace Add subroutine, corresponding
to the machine operation of Replace Add, for floating binary point numbers.
Each of the operand addresses u and v has four octal digits rather than five.
Since only four octal digits are needed to span the range of addresses in RAS,
this is not a severe restriction. The interpretation routine deciphers the
third and fourth octal digits, in tt.is case RA, to determine which of the subroutines in the system is to be executed.
(4) LIBRARY OF SUBROUTINES. - In any computational laboratory having
a Univac Scientific, there is a library of subroutines which can be used to
calculate the frequently encounteret mathematical or logical operations required
by the partilCular laborator}'. These are then available for any progranuner to use
in coding his own programs. In addition to saving coding time, library routines
have the advantage of being "debugged" and thoroughly tested. Presumably, more
effort has gone into their design than could be afforded by individual
PX 40
14
CODING FOR THE COMPUTER
programmers. On the other hand, library routines may be more general then
necessary for a particular program, and hence wasteful of time and storage.
Subroutines may be grouped into three basic categories. The following listing is intended to give the beginning coder an idea of the type of subroutines
that would be contained in a typical library of subroutines. This list is by
no means intended to be complete.
(a) COMPUTATIONAL SUBROUTINES.
Basic arithmetic:
Floating point add, multiply, divide, etc.
Complex number operations
Multiple precision routines
Function evaluation:
Trigonometric, sin x, cos x, tan x, etc.
Exponential, f(x) = x a , aX, etc.
Square 'root
Hyperbolic functions
Numerical Analysis:
Solution of n simultaneous equations
Matrix operations
Numerical integration
Numerical differentiation
Logical:
Sorting
Collating
Boolean algebra
(b) SERVICE SUBROUTINES AND/OR ROUTINES.
Compilers
Assembly
Programming aids (debugging sUbroutines)
Machine testing routines
(c) INPUT-OUTPUT SUBROUTINES.
Punch card (read and punch)
Paper type (read and type)
Editing (typewriter, paper tape, or card output)
The need to become thoroughly familiar with the available library of subroutines cannot be over-emphasized. An understanding of what each subroutine
will accomplish and the requirements for its use is important.
PX 40
15
CODING FOn THE COMPUTER
(5) ASSEMBLY OF SUBROUTINES. - If each of the library subroutines
were coded for a specific location in the computer memory, a programmer wishing
to use subroutines would be faced with two unpleasant alternatives: (1) code
his main routine around the fixed locations of the subroutines, or (2) manually
recode the subroutines to operate from locations which he chooses.
Instead, the practice is to adopt some standard form for subroutines and
to use an "assembly program" to convert the standard form of the subroutine
to coding suitable for execution at a specified location.
The simplest of these assembly routines assumes that the standard form of
the subroutine is already at the desired location. It remains for the assembly
routine to modify addresses (within the instructions of the subroutine) relative to that location.
A more sophisticated assembly routine provides not only for address modification but for transfer of the subroutine to a designated location from a
library file on magnetic tape or magnetic drum.
Furthermore, there are in use "compiling" routines which relieve the programmer of assigning storage locations to subroutines. The programmer need
only refer to a subroutine by means of an identifying index. The compiler
routine then arranges the subroutines in storage and modifies all subroutine
references to provide for a jump to the assigned location.
One standard form for subroutines in use at several computer installations
is as follows .
(a)
The initial address of each subroutine is address 01000
in rapid access storage. The service routines (assembly,
compiling, etc.) treat address 01000 as a "relative" address.
(b)
The first instruction of the subroutine provides for the
"alarm" exit. Most subroutines are coded to detect the
unexpected or undesirable, such as entry with an out-ofrange argument or incorrect parameters. When such is
detected, a jump to 01000 occurs. At 01000 is the
instruction
37
76000
76002
which provides entrance to an "Alarm Print Routine". This
routine prints (A), (Q), and the address of the instruction
at which the alarm condition occurred.
(c)
The second instruction provides for the normal exit from the
subroutine. The address of this instruction, 01001, is the
u address of the RJuv instruction used to enter the subroutine. This instruction is a Manually Selective jump,
coded:
MJ
01001
PX 40
16
O(=j)
CODING FOR THE COMPUTER
Actually the v address of this instruction of 30000 is an unallowable address which will cause an SCC computer fault if the
jump to 30000 occurs. Normally the RJ instruction used to enter
the subroutine would replace the v address of the'MJ instruction with y+l. However, if the RJ instruction had been incorrectly coded, or the subroutine had been entered without an RJ
instruction or w·ithout first changing the v address of (01001),
the computer would be stopped after executing the subroutine
when (01001) is taken as the next instruction. Thus would an
incorrect entrance into the subroutine be indicated.
(d)
The third instruction of the subroutine (01002), is the entry
line into the subroutine. This address, 01002, is the v address
of the RJ instruction used to enter the subroutine. If more
than one entry into a subroutine is necessary, instructions referencing the various desired entry points in the subroutine
are usually stored at consecutive memory positions beginning
with the third line of the subroutine.
(e)
A jump instruction must be placed at the end of the subroutine
computations to cause a jump to 01001, the normal exit line of
the subroutine.
(f)
All instructions and "modifiable" operands should be placed in
consecutive memory positions. "Modifiable" operands are any
words referencing storage locations of the subroutine which
would be changed upon translation of the subroutine. The
"unmodifiable" operands should be stored directly following
the above, at consecutive locations.
(g)
The subroutine must contain all the housekeeping instructions
that make it self-restoring.
The Square Root Routine given below is a routine coded in the standard
form just described. This routine is to be entered with the argument in the
Accumulator. The square root of that argument is in the Accumulator upon
exiting from the routine. Note the jump at 01002 to the alarm exit should
the argument be negative, and the jump at 01007 to the alarm exit should the
argument be put-of-range.
Routine for Evaluating the Square Root of N
Entrance conditions:
(AL)
(A R)
(AR)
Exit conditions:
=0
= N = N· 2 34
=VN =~N·2l7
The method used here is the Newton-Raphson iteration
Xn+l
=
Xn + 1/2
[~n - Xn]
tl
(=
Xn +
~ Xn)
= 1/2 ~n +
The first approximation is Xo = 235 _1 and convergence is assumed when A X~~ o.
PX 40
17
CODING FOR THE COMPUTER
01000
37
76000
76002
Alarm Exit
01001
45
00000
[30000 ]
Normal Exit
01002
46
01000
01003
Entrance; N . 2 34 negative?~Alarm
OlO03
11
01016
00005
2 35 _1-+( t5)
01004
11
A
00003
N . 234~( t3)
·01005
43
01016
01001
N . 234 ::: 235 - 1 ~ Exi t
01006
36
00003
A
01007
47
01000
01010
(A)
i
01010
31
00003
00041
1/2
N.
01011
73
00005
00004
1/2 N/xi . 23~(Q), (t4)
01012
54
00005
00107
1/2 xi· 2 3~ (A), ( t5 )
01013
'23
Q
00005
(1/2 N/xi - 1/2 xi) . 2 34-+(Q)::: ~ X
01014
21
00005
00004
1/2 Xi . 2 34 + 1/2 N/xi . 2 34=
(xi+ l ) 2 34 --.(t5)
01015
44
01010
01001
~x
01016
37
77777
77777
235 _1
N . 234
O--+Alarm
268~(A)
negative, Repeat loop
Note the use of addresses 00003, 00004, 00005 (t3, t4, t5) as temporary
storage for partial results obtained during computation.
Most routines require working storages such as these during their operation. Upon completion of the routine the contents of these locations are no
longer of use. A single location may be used several times in the same routine for temporary storage of different quantit~~s. For instance, in this routine 00005 contains successively xi, 1/2 xi . 2
and xi+l . 234. Since it is
possible for many different subroutines to use the same locations for temporary storage, it is conventional to reserve an area of the memory for temporary
storage. Several installations have reserved HAS locations 00000-00037 for
this use.
In this routine the WOrds in whieh addresses are to be modified when the
subroutine is assembled are in 01000 to 01015. The word in 01016 is a constant and is not to be modified.
An example follows of an assembl~' routine which is suitable for modifying
subroutines in the previously given ~itandard form. Recall that each subroutine to be assembled must be coded in absolute form as if its initial instruction were at address 01000. In actual fact the subroutine is placed in
PX 40
18
CODING FOR THE COMPUTER
RAS at any location selected by the coder. It is the function of the assembly
routine to modify all addresses that. are dependent on the location of the subroutine. The assembly routine must be informed of the actual RAS addresses of
the initial instruction of each subroutine and of the number n of successive
instructions to be modified in each case. It will then scan (s+j-l) instructions, j=l, 2, ... n, altering the u and v addresses of the instructions by
adding s-01000 to them when necessary.
A particular address will be modified if, and only if, the 10th bit from the
right in its 15 bit array is a one; i.e., if it is of the form XXX XXIXXX XXX
xxx. For RAS addresse's this means that all addresses of the form Olxxx (x an
arbitrary octal digit) and only such addresses will be modified. Thus,' addresses of temporary storage such as those described previously (addresses 00000
through 00037) will not be altered. Since n successive instructions are modified starting with the initial one, constants should be stored at addresses
01000 + n and following.
The routine below will assembly k subroutines in succession.
that the parameters for each, ni and si, are of the form
It is assumed
00
and are stored consecutively at addresses 00121 + i, i = 1, 2, ... k.
00121+k+l must contain 0 to indicate the end of the parameter list.
Address
Address Modification Routine
= (00121
00100
11
[00122 J
A
00101
47
00102
00000
Exit -- All modified
00102
73
00073
00005
(00005) = ni
00103
16
A
00112
(00112)v
36
00121
00006
(00006) = si -01000
00105
: 41
00005
00110
Exit for next subroutine
00106
21
00100
00073
Advance i by one
00107
45
00000
00100
Jump to 00100
00110
16
00112
00116
(00116)v
00111
11
00040
00007
(00007)
00112
21
00007
[00000 ]
00113
55
A
00033
00114
51
00075
Q
00104
t-------------------- --------
PX 40
19
(A)
+ i)
= si
= (00112)v
= zero
(00007) =(Sj)i
Shift right nine binary digits
(Q) = 00 00001 00001
CODING {'OR THE COMPUTER
= increment to (Sj)i
(Sj)i = modified initial
00115
71
Q
00006
00116
35
00007
[00000]
00117
21
00112
00074
s j advanced by one
00120
45
00000
0010§.1
Jump to 00105
00121
00
00000
01000
Constant 1000 octal
(A)
Note the references to addresses 00040, 00073, 00074, 00075.
these addresses are commonly used constants.
00040
00
00000
00000
00073
00
00001
00000
00074
00
00000
00001
00075
00
00001
00001
(s j ) i
The contents of
A computer installation will sometimes reserve an area of RAS for a "constant
pool tt, i. e., a collection of frequer:tly used constants. All subroutines can
then refer to the constant pool rather than having each contain its own constants. This results in a conSiderable saving of storage space when many subroutines are used. In the particule.r case of this assembly routine, it is
assumed that there is a constant pool at addresses 00040 through 00077.
In the case of routines, such as the assembly routine, which are to be
used by many different persons, it is important that the routine be accompanied
by complete and easily understood operating instructions. The operating instructions for the previous assembl) routine are given below.
Operatin'g Instructions for the Assembly Modification Routine.
1 Only suitably coded subroutines may be assembled.
A subroutine
is suitably coded if it satisfies the following conditions.
a
It is written in absolute form as if the initial instruction
were located at address 01000 .
..Q All addresses independent of the location of the routine are
of the form XXX XXO xxx xxx xxx .
.Q.
All addresses to be modified are of the form
xxx
XXI XXX XXX XXX.
d All subroutine constar.ts follow immediately the last instruction.
Z
To use this routine:
A
Load all subroutines to be modified in their proper locations
in RAS
PX 40
20
CODING FOR THE COMPUTER
b Load this assembly program in 00100-00121
£
Load the constant pool in 00040-00077
d Load the parameters
00
n°1
i
s').
= 1,
2, ••• k
for all k subroutines into addresses 00121+i, i
= 1,
.•• , k
e
Load zero into address 00121 + k + 1
f
Provide for the proper exit in the u address of 00101 and
enter at address 00102.
The assembly routine which has been described is an example of a service
routine designed to relieve a coder of part of the work in preparing a program
for execution by the computer. The text following describes a coding technique (simplifying the job of coding) which is possible because of another
type of service routine.
e. RELATIVE ADDRESSING. - In coding routines it is often preferable
not to assign absolute memory locations to quantities referred to in the program.
For instance, it may be convenient to postpone the assignment of absolute addresses to data, constants, tempora~y storage and the like, until the coding
of the entire problem has been completed. Similarly, it may not be desirable
to assign locations to subroutines until coding is completed and it is known
what the storage requirements are for each of the sections of the program.
It is possible to postpone the assignment of absolute addresses by coding
with "relative" addresses. For instance the instruction
01010
11
01012
01013
which is coded with absolute addresses 01010, 01012, and 01013 might be written
with relative addresses as
CIO
11
C12
C13.
In this case, the addresses are relative to the address C. The alphabetic
character C· could denote any address allowable in the Univac Scientific. For
example, it could be assigned the address 01000. The numerals following an
alphabetic character in a relative addressing scheme usually are interpreted
as being additive i.e., if C denotes 01000, then C12 denotes 01012, etc. Almost
any of the alphabetic characters are usually allowable in most relative addressing schemes. A few exceptions are the reservations of the letter A, denoting
the Accumulator, and the letter Q, denoting the Q register. Other exceptions
to the use of alphabetic characters need not concern the beginning coder. The
allowable characters depend upon the conventions in use at a particular computer
establishment.
PX 40
21
CODING FOR THE COMPUTER
Each new alphabetic character used in a program may indicate a new "region tt
in the storaue of the computer. In fact, a greater number of regions may be
accomodated by using combinations of alphabetic,or alphabetic and numeric
characters. By using relative addresses it becomes comparatively simple to
assign segments of a problem to various regions with the routines assigned
to each region performing a separate calculation or function.
As an example of a routine coded with relative addresses, consider the
following.
Compute the function f(Y)f where f(y)
Assume that y+7
= 5y-2
.
y+7
of 0 and IY+71<2 35 •
Function
Instruction
(Program of
instruct.ions)
Operation
code
u address
v address
Cl
TP
fl
A
C2
AT
El
C3
TN
E3
C4
MA
E2
fl
Form 5y-2 in A
C5
DV
f2
f3
Place the result of
5y-2/y+7 in f3
C6
PS
0
0
El
0
0
7
E2
0
0
5
E3
0
0
2
f2
A
Place y in A
Place y + 7 in f2
Place -2 in A
Stop
(Constant Storage)
Constants
(Temporary Storage)
Variable y
fl
f2
0
0
0
Temporary storage
holding y+7
f3
0
0
0
Temporary storage
holding f(y)
PX 40
22
CODING FOR THE COMPUTER
After a program is coded with relative addresses, it must be converted to
absolute addresses before execution by the computer. The computer may be used
to perform this conversion. ''Translation'' routines have been written which not
only convert relative addresses to absolute addresses but which also convert
decimal information to computer binary representations. Frequently these translation routines include an assembly subroutine.
f.
MECHANICS OF CODING.
(1) FLOW DIAGRAMS. - After it has been established that a particular
problem can be soh,~d'by the computer, it is necessary to formulate the problem
in terms of the language of the Univac Scientific computer. A program of instructions, and the necessary data needed for the solution of the problem must
be devised.
A "flow diagram" is helpful in facilitating the coding or programming of
the problem. A flow diagram or flow chart indicates the ttflow" or steps in
the computation which lead to hhe solutions of the particular problem.
A basic flow diagram usually lists the series of simple arithmetic steps
which are to be performed by the computer. It is imperative that the coder
be thoroughly familiar with the overall operations and peculiarities of each
computer instruction so that he can construct the outline with regard to the
capabilities of the computer. A description of each instruction is presented
in the section of,this volume entitled Sequential Presentation of Instructions.
Tabular informati6n on'theinstructions and the contents of the arithmetic
registers before and after the execution of each instruction is presented in
the volume entitleq "Content of Registers".
Usually more than one flow diagram'is formed for the more complicated
problems. The first flow outline may be nothing more than equations in mathematical language, written in the sequence in which they will be computed, together with brief explanations of the steps involved. The second flow chart
usually formulates the flow of computation as the problem will be computed on
the computer. This chart will usuall~ contain the instructions necessary for
the data input, the instructions that operate on the input data to obtain the
solutions, and the necessary instructions for the output of the re~lts.
Many times the problems are of such a nature that the second type of flow
diagram will consist of many charts and/or diagrams, each a more detailed presentation of the preceding charts.
To facilitate the task of forming flow diagrams and to allow other programmers to understand a particular flow diagram, certain symbol,s have been
more or less standardized. The following list of symbols is by no means complete, but is intended to give the coder an example of the basic symbols used
in drawing the second type.of flow chart.
PX 40
23
CODING FOR THE COMPUTER
(a)
LINES OF FLOW.
-{]
A solid line with an arrow touching the next element of the flow diagram
is usually used to indicate the path to be followed by the co,mputer; or more
precisely, the path to be followed by the coder who is formulating the computer
instructions from the flow diagram.
(b)
OPERATION SYMBOL.
-0
A+B
OR
ADD ATO B
The rectangular box usually con'tains a statement about a computer or mathematical operation. The contents Qf the box may be a simple statement or a
mathematical expression.
(c)
DECISION SYMBOL.
A!R
B
DOES A EQUAL
' \ =-{]
sF
:1=
The symbol above is used to ind:icate a two-way decision.
sometimes written as
This symbol is
where the letters EJ designate the use of the Equality Jump instruction to
make the decision in the computer.
PX 40
24
CODING FOR THE COMPUTER
( d)
CONNECTORS AND "REMafE CONNECTORS.
----~--------~
>0
®
To ~liminate as much as possible the crossing of lines of flow on a diagram, the above symbols are used to indicate a destination not easily reached
in the diagram. Thus, the flow can be broken at a convenient point by terminating itiri an arbitrary symbol which can be used to initiate the flow in
another region of the paper.
(e) EXAMPLE. - To illustrate the use of the above symbols, consider the following problem.
Compute the function f(xi) where
n
i = 1, 2, 3, ... , n
f(Xi) =1:
i
For this problem, it is assumed that b, c, d, and xi are integers and are contained in the computer in the Rapid Access Storage. Also, it is assumed that
Xi
+
d
"1
xi
+
d
1< 2 35
0
The function f(xi) is stored at the location whose address is ei .. The symbol
(i) indicates the storage of the "i" term.
FLOW DIAGRAM
I I -i
Start
m-C"';;"A I 1[(A) +
~(Q)~ei
__------IK0
Set (i) =
i
+
b •
xJ-A HfA)/( l-:>Q I~---'-"'~G
eo
l~i)
=
PX 40
25
CODING FOR THE COMPUTER
(2) CODING STEPS. - In sur~ary, there are usually four phases in
the preparation of a coded cornputeJ~ program:
(a)
The construction of a "flow diagram" or outline which shows
the general computational steps to be accomplished;
(b)
The creation of a program, written in terms of computer
instructions, us:~ng numeric or alphabetic symbols to indicate operation codes and the u and v address portions of
the instructions:
(c)
If the program created in Step 2 is coded in octal, the
program is ready for execution after being put onto some
input medium and loaded into the computer. If the program
is coded in symbolic notation, it must be translated into
a binary representation before it can be automatically
executed by the computer. Service programs for this translation may be used to facilitate this process by allowing
the computer to perform the conversion;
(d)
The "debugging" (computer check-out) of the final program
by means of trial runs on the computer.
The last phase - debugging - is def;cribed in the following paragraphs.
g.
DEBUGGING A PROGRAM.
(1) INTRODUCTION. - After the coded program has been written out
completely and the manuscript carefully reviewed, the program must be put on
some input medium for loading into the computer. The input mediums and the
devices which transfer information from these mediums to the computer memory
are described in the section Input and Output of this volume.
Once the program has been stored in the computer in binary form, either
directly from the input medium or by means of some translation routine, it is
ready for execution by the computer. However, if the program is lengthy, it
is likely that the coded program as stored has errors. Three common types of
errors are:
(a)
Tape or card pre~aration errors made in the preparation of
the program for input;
(b)
Coding errors, such as listing incorrect or incomplete
addresses, transposition of digits in the addresses or
operation codes, transcription errors, etc;
(c)
Logical errors; incomplete or erroneous methods used to obtain the solution(s).
"Debugging" is the term appliec to the process of locating errors in a
program and correcting them. Debugging a program ksually involves a series of
trail runs of the program on the computer. Each time the program fails to run
properly, the failure must be analyzed and the error corrected. Frequently one
can immediately discover the error, correct it manually from the control console,
PX 40
26
CODING FOR THE COMPUTER
and proceed with the next trial run. At other times the detection of errors
is more difficult and requires a thoughtful reconsideration of the program,
keeping in mind any clues as to the origin of the error which may have been
provided during the run. Error detection may be facilitated by the use of
service routines coded expressly for this purpose.
The methods that can be employed to debug a program will vary widely from
installation to installation depending on the nature of the programs, the service routines available, the availability of computer time, and the personal
preference of the individual for one procedure over another. The following
remarks suggest possible patterns to follow in debugging.
(2) TAPE OR CARD PREPARATION ERRORS. - This type of error can be
minimized by systematic checking of all input tapes and cards before their information is read into the computer. The usual method that is used to prepare
input paper tapes is listed below. (A similar routine is used in punched card
preparation.)
I
A paper tape is, punched from the coder's manuscript using
the Flexowriter.
£ The resulting typed manuscript from the typewriter is
discarded.
3 A new typed manuscript is prepared from the punched paper
tape.
4 This typed manuscript is compared with the coder's manuscript to detect errors in punching.
5 All detected punching errors are corrected and a new
corrected tape is prepared.
6
From the corrected punched tape a new manuscript is obtained
which should be retained by the coder to use while debugging.
7
If seven-level codings are used they should be sight-checked
before an attempt is made to read the tape into the computer.
(3) MANUAL DEBUGGING. - Manual debugging is the process which is
used to locate errors in a program by controlling the operations of the program
from the Supervisory Control Panel and visually checking these operations as they
occur and are indicated on the control panel. Although manual debugging does
not make efficient use of computer time, it can, if done correctly, reduce the
overall time required to debug a program because of the versatility afforded
by a tlthinking" programmer at the control panel.
After loading the program in the computer, a run at high speed is usually
tried. (For a discussion of the various speeds at which the computer may run,
see the section Operating the Computer. Many of the suggestions for program
debugging require a knowledge of operating the computer from the control console.
This is also described in Operating the Computer.) This run may show the program to be free of errors, in which case there is no debugging to be done; or
this run at high speed may end immediately with a computer fault. Frequently
an MCT (Main Control Translator) fault or SCC (Storage Class Control) fault will
PX 40
27
CODING FOR THE COMPUTER
arise. The former indicates an illegal operation code; the latter an illegal
address. (Computer faults are described in Operating the Computer.)
When a fault occurs, the contents of PAK (Program Address Counter) should
first be noted. This will almost always indicate the exact location of the
erroneous instruction.
The SCC fault usually arises from eit.her a transcription error, a punching
error, or incorrect modification of an instruction by the program. These
faults are ordinarily easy to correct. An MeT fault may be caused by a punching or transcription error. Frequently it will result from an erroneous program jump. In this case the address in PAK may indicate that the jump was to
an area which is not occupied by th,~ pronram. This fault must be traced to
the instruction which caused the jwnp.
The computer may also stop on a DIVIDE fault or an OVERFLOW fault. Erroneous coding may cause these faultS, or they may be the result of an error in
judgement concerning the range of the numbers involved in the computation.
Obviously, the first phase of dl~bugging is to correct the program so that
it will run without computer faults.
Although the program is running without incurring computer faults, errors
in its execution may still be detected. For instance, the program may be
coded to produce output but no prin'ting or punching occurs. Correction of
this type of error may be facilitatl~d by observation of the monitoring oscilloscope located on the upper center section of the Supervisory Control Panel.
This oscilloscope displays a point for each of the 4096 registers in RAS every
time one of the registers is referenced. If, while debugging a program, the
scope displays a distinct non-terminatinn repeated pattern (one dot or many)
for a questionable period of time, it can be assumed that the computer is
executing an erroneous "loop". This usually means that one or more of the
"decision" instructions has an incorrect jump reference causing a return to
itself or to a series of instructions which lead back to the incorrectlyaddressed jump instruction.
It may be possible to detect from the oscilloscope the area in which such
a loop is operating; or it may be desirable to FORCE STOP the computer, select
MANUAL STEP OPERATION, and, by executing one instruction at a time, trace the
operation through the loop. By noting each jump to a new address and traversing the loop at least once, the incorrect jump will probably be located.
Thus, the second phase of debugging is to eliminate any non-terminating
loops.
After these two phases of debugging a program have been completed, output
from the corrected program will revaal if the program is being executed properly. If the output format is in error, an investigation of that portion of
the program devoted to output is necessary. This may be accomplished by entering the output routine with a typical result and, if the output routine is
short, executing the routine one instruction at a time, observing the results
at each step. If the output routin~ is eomplicated, it will probably be necessary to inspect the manuscript of the coded output routine, using the
PX 40
28
CODING FOR THE COMPUTER
erroneous results as a guide in looking for the trouble. (Output routines from
the subroutine library would not be expected to cause any difficulty.)
In summary, the third phase of debugging is to correct any output routines
used in the program.
Since frequent output during the running of a program is a positive indication of proper or improper running, it is often convenient to provide for output of partial results of computation. Since these results are of no interest
when the program is known to be running properly, and since any output from the
computer is time consuming, routines providing such output should be entered
via an optional jump. During the debugging process the optional jump switches
may be "ont' to provide the output for monitoring purposes. After the program
is completely checked, the optional jump switches may be "off", thus eliminating the intermediate output. An intermediate printout may even be of value
when the program is in actual use. If normal output is very infrequen~ or onto
a medium which is not easily read, an operator may wish to occasionally sample
the intermediate output as a check on the program's operation.
Since the problem in debugging a program is to isolate each of the errors,
it is desirable to have the coding arranged in small segments. The coder
should be sufficiently familiar with his program to anticipate the results of
each of the segments of the computation. In particular, he should be able to
recognize an incorrect result.
A convenient way to examine the results of these program segments is to
terminate each with an OPTIONAL STOP. Like the optional jumps described above,
these stops may be "ont' while the program is being debugged and then tloff" when
the program has been checked out. If optional stops have been coded in the
program, the program may be executed from one stop to another until trouble is
encountered. Then, because it is known in which segment the error lies, that
section may be re-run on MANUAL STEP OPERATION.
The points in a program at which these optional stops and jumps are placed
are called "breakpoints".
Thus, the fourth phase of debugging makes use of programmed breakpoints to
isolate errors.
The instructions for optional stop and optional jump each provide three
selections which incur the jump possibility. Although the number of options
may be increased by combinations of the selections, an option at all desirable
breakpoints can not be provided in a lengthy program. Regardless of how
judiciously the breakpoints have been selected, in an actual debugging process,
a breakpoint is often desired where an option for one has not been coded in
the program. In this case it is possible to superimpose a breakpoint on the
program. If a stop, for instance, is desired at address a and addresses b
and b+l are unused, the instruction at a may be replaced with the instruction
56
00000
PX 40
29
b.
COD ING FOR THE COMPUTER
The program instruction which was in a is then stored in b, and the instruction
45
00000
a+l
is stored in b+l.
Thus, the fifth phase of debugging is to insert breakpoints if programmed
breakpoints are inadequate.
Thus far the process of debuggi:llg has been described in terms of the programmer himself manually debugging :lis routine.
It cannot be overemphasized th::it in order to do manual debugging, the coder
must be thoroughly familiar wi th th,e problem, its coding, and in addi tion,
with the_peculiarities of the computer.
(4) DEBUGGING WITH SERVICE ROUTINES. - A number of service routines
exist which facilitate the process of program debugging. Consider phase 1 of
the process of debugging, the elimination of computer faults. Two types of
errors may be hard to find: (1) an SCC fault arising from improper modification of an instruction and (2) an M:T fault arising from an incorrect jump.
The search for either of these errors may be facilitated by an "address sort tt
routine. Such a routine scans all instructions of the program for a given
address. Any instruction containing that address is printed with its location.
In case one the trouble may be located by a search for references to the
modified instruction; the faulty jump iri case two may be located by a search
for referenees to (PAK)-l at the time of the MeT fault.
A serviee routine of use in eliminating faulty loops is a "jump trace"
routine. A "trace" or "automonitor" is a routine which executes interpretively all the instructions of a program which is being debugged. As each
instruction is executed, the instruction itself and its address are printed
out together with (A), (Q), (u), and (v), In the case of a jump trace routine,
print-out occurs only if the instruction is a jump. With this print-out, the
sequence of jumps in a program can be followed, and those which are incorrect
can be noted.
When a program has been run, a "memory dump" will often reveal the operations which occurred during the run. A memory dump routine lists octal printouts of the contents of those memory locations containing the program. The
examination of indices, temporary storage, modified instructions, etc., usually reveals the portions of the program which were improperly executed. This
aids in locating the improper modif'ications of the program and recovering partial results. A "changed word post-mortem" routine is a selective memory dump
in which only those words which have been changed in the course of running a
program are printed. A changed word post-mortem routine requires that the
original program ~ loaded be stor€~d in the memory. After the program is run,
a word-by-word comp~rison is made of the original program and the executed
program. The advantages of a chanued word post-mortem routine-over a memory
dump routine are that it operates faster, and there is less print-out to be
examined. The memory dump, by vir1.ue of printing all the program, gives
evidence of misloading or punching errors which may not be detected by a
PX 40
30
CODING FOR THE COMPUTER
changed word post-mortem.
The use of breakpoints in debugging a program can be facilitated by any
one of several "breakpoint routines". The simplest of these merely replaees
selected instructions with manual stops and stores separately the instructions
and the jumps back into the program. Upon reaching one of these stops in the
program, the programmer may examine the contents of certain locations which
contain partial results, or manually step through the next part of the program.
A more elaborate breakpoint routine may provide for automatic print-out of the
contents of certain registers at a breakpoint. Usually these print-outs are
either in octal or decimal notation. It is also possibl~ to invoke at a
breakpoint a trace routine which prints the results of each of the neoct few
instructions. A great saving in time is effected by using these sampling and
tracing routines at a breakpoint rather than manually examining the results
at that point.
The debugging service routines which have been described are of two types,
"static H and "dynamic". The static type is employed after a program has been
run and has stopped. The memory jump and address sort routines are examples
of static routines. The dynamic routines operate in conjunction with the program as it is run. These may be "executive" routines which execute interpretively the program instructions and provide printouts of the results, i.e.,
trace routines; or they may be routines to which control is transferred at
specific breakpoints, i.e., sampling routines. The static debugging routines
usually require less computer time for their operation than the dynamic type.
Therefore, in practice they are used more often although more information can
be obtained from the dynamic type.
(5) ERROR CORRECTION. - It may be possible during the debugging process to correct a routine manually by making simple alterations in the contents
of certain memory locations. After these corrections have been made a new input paper tape or punched card is usually needed for reloading the corrected
version of the routine. To obtain the corrected version, which is in the
memory of the computer, a "punch storage for reload" or "bioctal dump" service
routine may be used. This produces a paper tape or deck of punched cards containing the program coded in octal with appropriate insert and check addresses.
In order to conserve computer time while making a number of manual corrections from the Supervisory Control Panel, the following method is suggested:
Depress MASTER CLEAR button
Select MANUAL STEP OPERATION
Set MPD to 3
Set MCT to 75 (Repeat instruction)
PX 40
31
CODING FOR THE COMPUTER
Set UAK to 70000 (set j to 7)
Set VAK to 00000
Set X to 11 10000 v, where v is the first address to be
written into.
Depress START button
Depress STEP button
Set in Q Register the word to be wri tten }
Repeat Manually
Depress STEP button
Clear Q Register
It should be noted that a j of 7 is being used which sets up an unterminated
repeat sequence with both the u and v addresses of the repeated instruction
being advanced upon each execution. Since this is the case it becomes comparatively simple to read back into Q for checking purposes the words just written.
This procedure is
Clear UAK
Set UAK to u where u is the first address which was written into.
Clear VAK
Set VAK to 10000
Depress START button '}
Repeat Manually
Depress STEP button ,
If the data that is to be written or to be read is not in consecutive memory locations u the following steps must be added at the end of both of the
above repeated steps.
Clear VAK (UAK if reading)
Set VAK (UAK if reading) to the address to be written into or
read from.
The process of program debugging has been described in terms of the programmer himself operating the computer. Manual debugging clearly requires a
thorough knowledge of the program. However, the service routines may be applied by an operator with perhaps instructions from the programmer. The extent to which programmers will operate the computer for program debugging
will vary from one installation to the next.
PX 40
32
CODING FOR THE COMPUTER
hD OPERATING PROCEDURE. - The service routines which have been described
as aids in debugging should be available for use whenever trouble arises.
Since the need for these routines cannot always be anticipated, it is desirable
that they be at all times in the computer memory. Many installations have reserved areas on the magnetic drum and/or magnetic tape for permanent storage
of the service library. Except when necessary, programs are not stored in
these areas. This practice eliminates the need for frequent reloading of the
servIce routines.
In addition to the service routines for debugging there are service routines which facilitate operating the computer. Chief among these, in the case
of a computer with a Photoelectric Paper Tape Reader, is the program for reading
information from paper tape. Such a program may be coded to accept information
punched in any form whatsoever. In particular, the program might be designed
to load ~ioctal tapes with the 7th level control configurations described in
the section Input and Output Systems.
Routine for Loading Bioctal Tapes with
~
Paper Tape Reader
00000
45
00000
00006
Jump to start
00001
45
30000
00003
Optional jump to bypass stop
00002
17
00005
00002
Stop reader
00003
11
00035
40000
Enter data
00004
21
00003
00037
Advance address
00005
45
30000
00007
Optional jump to bypass start
00006
17
00006
00006
Start reader
00007
76
00000
Q
00010
31
00035
00006
00011
52
00027
00035
00012
31
00036
00001
00013
52
00030
Q
00014
51
00030
00036
00015
43
00032
00001
Test for enter data
00016
43
00031
00021
Test for insert address
00017
43
00033
00023
Test for check address
00020
45
00000
00007
PX 40
33
Read to Q
Isolate data levels
Isolate seventh level
CODING FOR THE COMPUTER
Insert address
00021
16
00035
00003
00022
45
00000
00007
00023
11
00003
A
00024
36
00034
A
00025
43
00035
00007
00026
57
77777
7777'7
00027
00
00000
00077
Data levels mask
00030
00
00000
17700
Seventh level mask
00031
00
00000
11100
Insert address code
00032
00
00000
10100
Enter data code
00033
00
00000
10500
Check address code
00034
II
00035
00000
Constant for check address
Check address
00035
Word assembly
00036
Instruction code assembly
00037
00
00000
00001
Constant for advance address
If the program to be loaded is short enough to allow the storage of a
copy, it is helpful to have an "image" of the program stored on the magnetic
drum (MD). Usually the image on MD contains the two extra instructions
RP
TP
jn
MD
w
RAS
which cause the program to be transferred to RAS at the start of the computationso Thus, whenever it is necessary to restart the program, the unaltered
version of the program may be transferred from MD without reloading the computer from paper tape or cards. This drum image is also available for use by
service routines such as a "changed word post-mortem" routine.
A paper tape loading routine may be used which automatically provides such
a drum image of the program. Of greater importance, such a loading routine permits loading anywhere in HAS; the previously listed loading routine does not
allow RAS addresses 00000 through 00037 to be loaded. Provided that the loading routine contains an "end of tape" detection, the loading routine may be
supplemented to operate under the following conditions:
PX 40
34
CODING FOR THE COMPUTER
(a) The loading routine is stored on the magnetic drum,
(b) The loading routine proper is prefixed with instructions
which,
(1)
store the current contents of RAS as a drum image, and
(2)
"bootstrap" the loading routine proper into RAS for
operation.
(c) All data being loaded into RAS under control of the loadinlg
routine is in fact loaded in the drum image.
(d) Upon detecting "end of tape", control is transferred to suffixed instructions (on the drum) which transfer the drum
image to HAS and stop the computer.
The coding for such a bootstrap operation follows.
LO
11
00000
70000
Ll
75
37777
L3
L2
11
00001
70001
L3
75
3
00000
L4
11
L5
00000
L5
45
00000
Lx
n
store Fl
)
store (RAS) in drum image
70000 - 77777
}
transfer loading routine proper
to RAS for operation
entrance to loading routine in HAS
L6
loading routine proper
Ln+4
Ln+5
75
37777
Ln+7
Ln+6
11
70001
00001
Ln+7
11
70000
00000
Ln+lO
56
00000
LO
transfer of drum
image to RAS
I
stop; re-entry to loading routine.
It is desirable that a bootstrap procedure similar to this be used with
most service routines so that operation of the service routine does not destroy the status quo of RAS.
Another practice which many consider helpful is to "erase" the computer
memory before loading a program for debugging. This means that erroneous
jumps to an address not used by the program result immediately in an MeT fault.
Also program sections separated by erased portions of RAS are easily recognized
in a memory dump. This erasing, or writing of zeros in every location, may be
PX 40
35
GODING FOR THE COMPUTER
effected by a repeated Transmit Positive instruction from Q with (Q) = O. This
may b~ set up manually, as previously explained, or included in the service
library.
Frequently service librarys include routines to simplify manually reading
informatIon out of storage or writing information into storage. If these
routines print out the word read or entered, a written record is provided of
all corrections made in the course of running a program.
When a library of subroutines is kept on magnetic tape, the service library
usually includes a routine to extract the subroutines from file. Input translation routines may also be in the service library.
It is important that a programmer be thoroughly familiar with any service
routines in use at his installation. There are restrictions to the use of
many of these routines of which he must be aware. For instance, the ffRoutine
for Loading Bioctal Tapes with a Paper Tape Reader" cited previously does not
permit lciading in addresses 00000-00037.
Before coding any routine, a progrannner should acquaint himself with the
operating conventions of his installation. He should know such particulars
as the following:
3.
(a)
The service routines available and the facilities and restrictions of each;
(b)
The input translation routines in existence,
(c)
The procedures necessary in order to use library subroutines:
their assembly, their reference to a constant pool, a temporary storage pool, an alarm print, etc., and
(d)
The areas, if any, of the computer memory which are reserved
for special purposes.
NUMBER NOTATION.
a. INT:RODUCTION. - Because thE theory of operation of the computer is
based on binary logic, the coder sh.ould become thoroughly familiar with one's
complement binary arithmetic. The following list of publications is
recommended as references to suppl€,ment the discussion of binary arithmetic
presented in the section General Description and Appendix A of this volume.
(1)
Stifler, W. W. Jr., (ed), High Speed Computing Devices by the
staff of Engineering Research Associates, pp. 74-99,
(McGraw-Hi 11, New York, 1950).
(2)
Richards, R. K., Arithmetic Operations in Digital Computers,
pp. 1-22, (D. Van No~;trand Co., Inc., New York, 1955),
(3)
Uspensky, J. V.,
Elen~ntary
PX 40
36
Number Theory, (McGraW-Hill, 1939).
CODING FOR THE COMPUTER
As stated previously, for conveni~nce octal, instead of binary notation, is
used to describe computer words and addresses. It should be remembered, however, that the logic of computer operation is based on the binary system.
b. RADIX CONVERSION. - In most problems the data for a program is .presented in some form other than binary. In particular, data is frequently decimal.
In Appendix A procedures for converting numbers from one radix (base) to another
are described. It is usually desired that the computer perform the necessary
radix conversions of input and output data.
If, for example, the computer were used for a problem involving large
amounts of decimal data, an efficient method for converting from decimal to
binary would be necessary. A "scalar product routine", such as that which
follows, could be used for this conversion provided it is known that all
decimal data are integers.
Let N be the desired binary number; then
N = aO + 10al + 10 2 a2 + ••• + 10n an •
To form this scalar product, the individual products of the binary-coded
decimal digits of the decimal number and their corresponding powers of ten,
binary-coded, are ~ccumulated.
Routine to Convert Decimal Integers to Binary Integers.
el
RS
A
A
e2
RP
3,n+l
e4
e3
MA
Clear A to zero
Form N
Next instruction
e4
ul
1
u2
12
10'
Powers of ten coded
in binary.
un+l
vI
v2
Binary - coded decimal digits
vn+l
PX 40
37
CODING FOil THE COMPUTER
The result N (in binary) appears :in the Accumulator.
The reverse operation, conversion from binary to decimal, can be accomplished with a repeated division. Assuming that the positive integral number N
to be converted to decimal is contained in the Accumulator, the steps are:
fl
RP
3,n+1
f3
f2
DV
ul
vI
Form binary - coded decimal digits
Next instruction
f3
ul
Powers of
ten coded in binary
un
un+l
12
10'
1
vI
v2
Binary - coded decimal digits
vn+l
al
The Divide instruction (DVuv) causes t:le number in the 72-bit Accumulator to
be divided by the number at address u. The quotient is deposited at address v,
and a posi tive remainder is left in t:le Accumulator. In the above example,
descending powers of ten are brought in as successive divisors of the diminishing remainder, then the series of quotients are the binary-coded digits of the
decimal representation of the number initially contained in the Accumulator,
These quotients are depositied at a series of consecutive addresses vI, v2' ...
vn+l·
To illustrate binary to decimal integer conversion, consider the following.
Convert n binary words from any n consecutive memory locations to decimal,
and print these decimal integers on the typewriter with appropriate sign.
This subroutine assumes that the Q reqister, upon entry into the subroutine,
contains a code word which specifies the number n and the address of the first
binary number; i.e .•
(Q)
= 00 xxxxx -----
where ----- specifies the number nand xxxxx specifies the address of the first
datum.
:?x
40
38
CODING FOR THE COMPUTER
YO
MJ
o
30000
YI
PR
o
b 6
Shift typewriter to lower case
Y2
TU
Q
Y7
Set in initial location of data
Y3
TV
Q
b 2
Set in counter n
Y4
IJ
b2
Y6
Test n:
Y5
MJ
o
Y0
Exit - completion of routine
Y6
PR
o
b 1
Perform carriage return
Y7
TP
x·1
A
Place ith number to be printed in A
YIO
SJ
Yll
Y14
Test sign of number
YII
PR
o
b 3
Print negative sign
Y12
TM
A
A
Put absolute value of number in A
Y13
MJ
o
y15
Skip next instruction
Y14
PR
o
b 4
Print plus sign
Y15
PR
o
b 5
Print space
Yl6
RP
3,13
Y20
Y17
DV
b7
Y22
Y20
RP
2,13
Y22
Y21
RA
Y22
b 0
Y22
o
Y23
o
Y24
o
Y25
o
Y26
o
Y27
o
Y30
o
Y31
Y33
o
o
o
Y34
o
Y32
Exit line of subroutine
}
if n=O, no numbers are pri.nted
Form binary-ooded
decimal digits
Form print instructions
Print 11 decimal digits for each number.
(Initially the binary-coded decimal digits
are stored here until they are replaced
by the appropriate print instructions.)
PX 40
39
CODING FOR THE COMPUTER
CODING FOR THE COMPUTER
Attention is called to the four instructions (YI7), (Y20), (Y21) and (Y22).
The first two of these instructions form by repeated divisions the binary-·
coded decimal digits of each number to be printed. The second pair of instructions add to each of these binary-coded decimal digits a dummy print instruction which addresses in its v address portion the starting address of a table
of typewriter codes for the digits 0 through 9. For example, suppose that
the first binary-coded decimal digit is a five. This is stored at Y22 as the
result of the first division. ·Then, as a result of the Replace Add instruction atY21, the content of Y22 could be replaced by PR 0 dS. Thus, when this
instruction is executed by the computer, the digit "S" would be printed by the
typewriter.
c. SCALING. - It should be emphasized that the above routines are for
binary/decimal conversion of integers. Words in the Univac Scientific are
considered to be integers in the sense that the computer has been designed so
that for ~ll arithmetic operations the binary point is thought to be to the
right of the right-most bit. This does not mean, however, that only computations with integral numbers can be performed in the computer.
Whenever a problem involves a quantity s which either (a) exceeds the
range of integers which may be represented in a 36 bi t wor~ (1-2 35 S s S 23 s -1),
or (b) has a fractional part, that quantity s m~y be repr6sented as s = SI·2s2,
where sl is an integer within the range of a computer word. The quantity 2 s 2
is called a "scale factor", sl is called the "mantissa" of the number s, and
s2 is called the tlcharacteristic" ~f s. A positive characteristic is used to
represent integers outside the range (1-2 3S , 23S -1); a ntgative characteristic
is used to express numbers with fractional parts.
Thus, in a computer operating upon integers, the machine representation
of a number is the actual value of the number multiplied ("scaled") by some
constant 21 •. It must be remembered that when the machine executes an arithmetic operation involving scaled numbers, the scaling ma change. Suppose
sm and tm are the machine representations, each scaled 2 0, of se and tee The
result rm of a Multiply instruction MP {sm} {tm} is then the machine representation of re = se • te scaled 240 :
2
t m = t e • 220
It may then be necessary to "scale down" rm so that its machine representation
does not exceed the capacity of a 36 bit word. Thus the choice of scaling for
a number depends not only on the number of fractional bits to be represented
but also on the machine restriction of 36 bits per word. In general the coder
must consider three things in scaling.
(a)
All numbers must be scaled so that the "machine representations" of these numbers are integers.
(b)
The routine should be coded so that the scaling is always
known.
(c)
Frequent rescaling may be necessary in the routine if the
values of the numbers are not to exceed the capacity of a
computer word.
PX 40
41
CODING F'OR THE COMPUTER
In many computations involving s~aled numbers, the desire to retain the maximum amount of "precision''', i.e., maximum number of significant bits, create a
problem. To solve this problem, the Dumbers that enter into the calculations,
as well as the numbers resulting from these calculations, are "normalized". A
normalized number is a number which has been scaled up in a 36-bit register so
that the left-most stage of the register contains the sign bit of the number with
the most siglllificagt bit of the number contained in the next adjacent stage, i.e.,
the number n is 2 3 > n ~234.
The following are examples of no:rmalized numbers:
30 00000 00000 is 00 00000 00003, (+3) normalized,
47 77'777 77777 is 77 7'7777 7'7774, (-3) normalized.
Numbers are normalized easily in the [nivac Scientific by using the Scale
Factor (SFuv) instruction. This instruction normalizes the number (u)i in AR
and stores the number indicating the left shifts necessary to restore the number
(u)f to its original state. This sh:Lft count k is stored in the v portion of
the register whose address is given by the v of the Scale Factor instruction.
In case the u address of the Scale Factor instruction is the Accumulator
the relationship between the initial and final contents of the Accumulator is
as follows:
(A)f = (A)i . 2 s where s is the scale factor.
The relationship between sand k is
s=-kifOSk'S36
s = '"l2-k if 37 S k ~ 71
If k = 0, (A)i was properly positioned before shifting.
If k = 37, (A)i is all ones or zeroes.
To illustrate the use of the Scale Factor instruction, consider the problem of normalizing the' product of two numbers Xm and Ym where these numbers
are themselves scaled machine copies as follows:
Xm = x • 2 r
Ym = Y • 25.
The routine would be as follows:
Cl
MP
vI
v2
form product
C2
SF
A
tl
normalize
C3
TP
A
t2
place normalized product in t2
PX 40
42
(A)
CODING FOR THE COMPUTER
C4
TP
tl
A
place k in A
C5
TJ
t3
C7
is k < 37?
C6
RA
v3
t4
add 7210 to (v3)
C7
RS
v3
tl
subtract k from (v3)
next instruction
ClO
tl
o
k, (zero initially)
t2
o
normalized product
t3
45
constant, 3710
t4
110
constant, 7210
vI
xm
v2
Ym
v3
r + s initially.
The product formed by the first instruction is
(VI) . (v2)
= xm
. 'Ym = x . y . 2r+s.
The remaining instructions form the product
(t2) = x · y · 2(V3)f
r + s - k if k < 37'
r + s + 72-k if
k~37.
An overall relationship would be expressed as follows:
X'
Y = (v 1 ) . (v2) . 2 - ( v3 ) i
= (t 2 )
. 2- ( v3 )f •
It should be noted that the 21 leftmost stages of tl must initially contain
zero since the Scale Factor instruction writes only into the lower order 15
stages of tl.
If a routine is coded such that only the mantissas of scaled numbers are
stored in the computer and operated upon by the program, the routine is said
to be coded in fixed point. In this case the programmer must himself keep an
account of the characteristics associated with each mantissa at every step of
the computation. The programmer must also be aware of the size of the mantissas and scale them down when there is danger of exceeding the capacity of
PX 40
43
CODING FOR THE COMPUTER
a computer word. On the other hand, if the mantissas are carried in normalized
form, the result of every arithmetic operation must be normalized.
The programmer must be exceedingly careful in the record which he keeps of
the characteristics. A mistake may result in his having to rescale the problem from that point on. This accounting is generally listed on the coding
sheets. The characteristic is recorded beside each instruction which changes
the scaling of a mantissa. Great care must also be exercised in judging the
magnitude of the mantissas. If unanticipated overflow occurs, the problem may
have to be rescaled.
It is evident that the fixed point coding of a problem can be complex;
consequently it is sometimes preferable to store in the computer the characteristics as well as the mantissas and use subroutines which, before each arithmetic operation, effect the scaling of the mantissas on the basis of their associated characteristics. The result of each arithmetic operation is then stored
as a mantissa with associated characteristic. This manner of coding is known
as floati,ng p'oint coding. Various schemes may be used for the storage of the
mantissa and characteristic of a floating point number. If the mantissa and
characteristic are stored at separate locations, the floating point number is
said to be "unpacked"; if the mantissa and characteristic are stored together
at one location, the number is said to be in "packed" form. A common floating
point packed form for the Univac Scientific allows 28 bits for the mantissa and
eight bits for the characteristic. Generally the mantissa is normalized although
this is not necessary. Should one wish to retain an indication of the number of
significant bits in the results, the mantissas may be carried unnormalized.
As an example of one floating point packed form which has been used on the
Univac Scientific, consider the following representation of the number s by the
components sl and s2 of 28 bits and eight bits, respectively.
If s f. 0
1> I Sll?!
If s = 0
sl = s2 + 128 = 0
1/2, 256> s2 + 128?! 0
The number s is represented in the computer by sl • 235 and s2 + 128, the
machine forms of its mantissa and characteristic. Note that the mantissa is
normalized. When the characteristic is represented in this way, as s2 + 128,
it is said to be a "biased" characteristic. (The characteristic might also
be represented by eight bits as a "signed" characteristic, 128 ~ s2 2: -128.)
The packed representation of the number s is positioned at a location as
follows:
8 bits
28 bits
[norma~-iz-e-d-I
biased
characteristic
mantIssa
------------------~
The choice of a representation for floating point numbers is influenced by
many considerations which may vary from installation to installation.
Elaborate systems of subroutines have been developed to perform arithmetic
operations with floating point numbers. The price which the programmer pays
PX 40
44
CODING FOR THE COMPUTER
for relief from the complexities of fixed point scaling is increased execution
time for the arithmetic operations. For instance, with a floating point system
which uses a packed representation, the execution times for the operations of
addition, multiplication, and division may be on the order of 60 times that of
the corresponding machine operations. Floating point operations with unpacked
operands are considerably faster. Here the multiples of the increase in time
over the computer operations are approximately 20, 3, and 3 for addition, multiplication, and division, respectively. In general, floating point coding is
used to reduce the elapsed time between receipt of a problem and the production
of answers. Floating point notation is particularly useful in problems in
which the numbers involved vary widely and where only crude predictions can be
made of the amount of variation.
d. MULTIPLE PRECISION. - In addition to scaling in order to modify the
range of numbers which may be represented in the computer, it is possible to
extend the range by representing numbers in a double precision, triple pre~
cision or, in general, n-precision form. In this case two, three, or n computer words are used for the storage of a single number. For example, two
locations are reserved in storage to represent a double precision number. The
representation may be (AL) and(A R) when the number is in the Accumulator. The
addition of two numbers so represented is easy and fast using the Split instructions. In the case of multiplication or division, an, end correction must
be provided for each word whose sign bit is "1". Another method is to select
a positive constant k and represent a double precision number N as
N=q· k+r
with a side condition on r to require unicity. Both q and r are single precision numbers. For example, let k = 234 with O~ r< 234. With this representation addition is slower but multiplication and division are markedly
easier.
Similar schemes may be used for n-preclslon computing. Again, a number of
considerations enter in the choice of a representation of multiple precision
numbers.
e. CHOICE OF NUMBER NOTATION. - In choosing the number representation
to be used in solving a given problem on the computer, the accuracy which is
required is first considered. If a large number of significant bits is demanded, a multiple precision representation may be required. Secondly, the
choice between a fixed point and a floating point notation is made ~n the basis
of running time on the computer versus programming time. Floating point routines are frequently used to simplify the coding of "one shot" programs (the
program is to be used once) where the emphasis is on elapsed time from problem
formulation to solution. Generally if a program is to be run repeatedly, it
is coded in fixed point in order to minimize the running time.
4.
NOTES ON THE INSTRUCTIONS IN THE UNIVAC SCIENTIFIC REPERTOIRE.
In the following paragraphs, pecularities, tricks, and pitfalls which con~
front a programmer are discussed. In almost all cases the unusual circumstances
which must be noted are due to particular features of the computer logic.
Certain of these features create problems which are not immediately obvious.
PX 40
45
COD ING FOR THE COMPUTER
a.
OPERATIONS INVOLVING THE ACCUMULATOR.
(1) NEGATIVE ZERO. - Sinc€ the basic arithmetic operation of the
Univac Scientific is subtraction and the "l's" complement number system is used,
negative zero (72 "ones" in the Accumulator) cannot be generated by any series
of arithmetilc operations. Consider the operations performed by the instructions
below;
CI
C2
RA
el
RS
A
el
e2
e3
7'7 77777 77776
00 00000 00001
77 77777 77777
form sum
form difference
e2
e3
-1 in decimal
+1 in decimal
-0 in decimal.
Using, for exemplary purposes, single length registers of four bits and an
Accumulator of eight bits, the operations can be shown as follows:
Contents of
Accumulator
0000 0000
0000 0001
1111 1111
clear A
"add D(el)" by subtracting D(el)'
_ _ _.-,;1
end around borrow
1111
1111
0000
0000
1111
0000
"add D(e2)" by subtractin~} D(e2)'
result of executing (Cl)
transmit (AR) to X, then clear (A)
"add D(X)" by subtracting D(X)'
1110
1110
0000
0000
1111
0001
1
0000 0000
1111 1111
0000 0001
]l
0000 0000
Operations of
RA at Cl
Operations of
RS at C2.
end around borrow
subtract D
(e:~)
end around borrow
result after executing (C2)
Continuing the above example, negative zero may be formed in the Accumulator
using one of the "logical" instructions:
C3
S ..C')
e3
C4
CC
A
o
e3
form - (2 36 -1) in A
forn negative zero in A
i. e. ,
0000 0000
0000 1111
1111 0001
1.
1111 0000
result after executing (C2)
form (A) - S(e3)
end around borrow
result of executing (C3)
PX 40
46
Operations of
SS at C3
CODING FOR THE COMPUTER
1111
1111
1111
1111
0000
0000
1111
1111
transmit (AR) to X, then clear (AR)
form logical sum of (X) and (AR)
form logical sum of (AR) and (e3)
result after executing (C4)
}
Operations of
CC at C4 •
Negative zero can be generated in the Accumulator by other series of instructions eoncluded by the Controlled Complement instruction (CCuv). Note that
in the above example the content of e3 (nQrmally considered a negative zero,
mod 2 36 -1) was considered as 2 36 _1 (mod 21~-1). Such is the case when any of
the "split" or "logical" instructions are used.
If the above routine is continued with the execution of the following instruction, note that the content of the Accumulator (all "ones") must be considered as zero.
C5
LA
A
k
shift (A) left k places
i. e. ,
1111 1111
result after executing (C4)
1111
1111
0000
0000
0000
do not clear (A), but clear (X)
It'and D(X)" to A by subtracting D(X)' from A } Operations of
(A) is now all zeros
LA at C5
shift (A) left k places
result after executing (C5)
1111
1111
0000
0000
0000
Thus, if the content of the Accumulator is all «one's", its content must
be considered to be all zeros except in the following cases.
If either an Equality Jump or Threshold Jump instruction is executed with
the content of the Accumulator all one's, the result of testing (A) is as
follows.
If (u) is 236 _1 (negative zero),
EJuv shows an equality, takes (v) as NI
TJuv results in a positive (A), continues present sequence
If (u) is all zeros (positive zero),
EJuv does not show an equality, continues sequence
TJuv results in a negative (A), takes (v) as NI
In none of these cases will the content of A be restored to negative zero.
The Accumulator will be set to all zeros after the execution of any of these
instructions.
If a Zero Jump (ZJuv) is executed when the content of the Accumulator is all
one's, (A) tests as not being equal to zero, but as the result of executing the
ZJ the Accumulator is set to all zeros.
PX 40
47
CODING FOR THE COMPUTER
(2) SINGLE OR DOUBLE LENGTH EXTENSIONS. - A common error involving
transmissions to the Accumulator and a subsequent testing of its contents is
illustrated by the following example:
Cl
C2
a
SP
EJ
el
e2
40
40
00000 00000
00000 00000
ent.er variable in A
convare (A) and (e2)
C3
el
e2
variable (here shown as a constant)
a c:onstant.
After (Cl) is executed, (A) is 00 00000 00000 40 00000 00000. The
EJ at C2 tests to determine if (A) and D (e2) are equal which is not true in
this case sin,ce D(e2) = 77 77777 77777 40 00000 00000. A correct method of
testing for the equality of these two values, (el) and (e2), 'could be coded
as follows:
Cl
C2
TP
EJ
el
e2
a
C3
By using the Transmit Positive instruction, the double length extension of (el)
is formed in the Accumulator.
(3) COMMON PITFALLS. _. Many instructions make use of the Accumulator
without explicitly referencing it as one of the execution addresses.
It should be remembered that the initial contents of the Accumulator may
be destroyed when executing certain of these instructions which use the
Accumulator. In certain cases this may lead to erroneous results when the
Accumulator is used as the u or v address of the instruction. A study of the
section Sequential Listing of Instructions will indicate the peculiarities
arising from such situations. The volume entitled Content of Registers
presents in tabular form the results of such peculiarities.
Similar peculiarities result frorr addressing the Q Register as u or v of
an instruction.
b. SHIFT INSTRUCTIONS. - All shifts performed are left end-around shifts.
When a shift is performed the left-mast portion of the number shifted in the
Accumulator (or Q register) becomes the right-most portion of the number. It
should be remembered that a left shift of 19k" places is equivalent to a
modular multiplication by 2k. Depending upon the significance attached to the
sign-bit, the modular value of the shifted number will be in the range of the
signed numbtrs possible to represent in the register or in the range of the
system of binary numbers directly represented in the register. If a significant "1" (or "0" if the number has a negative representation) is shifted into
PX 40
48
CODING FOR THE COMPUTER
the sign-bit position of the register, the "sign" of the shifted number must
be regarded as opposite in sign to the initial number unl~ss the shifted
number is referenced for later use by one of the Split instructions.
The mathematical statement expressing a left shift of (u) by k is
(u)-2 k - [(u).2 k- n1] 2m + (u)·2 k- m
where the brackets mean the greatest integer contained in the register and
m = 72 for the Accumulator where k ~ 72
m = 36 for the QRegister where k ~ 36.
An equivalen~ right shift can be obtained from a left shift by observing
that a tight shift of k places = m-k left shifts.
When the v address portions of the Left Shift in A, LAuk, and Left Shift in
Q, LQuk, instructions contain ones in o~her than positions v6 ••• vO, transmission
back to the u address of the shifted quantity contained in A or Q can be stopped~
The peculiarities resulting from such a condition are discussed in the section
Sequential Listing of Instructions_
This property of these shift instructions is useful whenever it is desired
to le~ve the original content of u undisturbed. For example, consider the
instruction LA 01000 32002.
The operations resulting from this instruction are:
Clear A
o
(01000)~
A
(A) is shifted two places to the left
The shifted result is not transmitted to 01000 but left in A.
An operation possible for some u addressed HAS locations is:
Transmit (positive) to A and Q the content of u after (u)
has been shifted k places to the left; e.g.,
LQ
01100
32005
or also
PX 40
49
LA
00100
31005
CODING FOll THE COMPUTER
The following operations result from these instructions:
(OOlOO)~
(Q)
or
(A)
(00100)
or
Q
-~
A
is shifted 5 places to the left
A short summary showing the results of coding the 54uk and 55uk instructions for transmissions to A or Q of u.(= HAS) shifted is given below.
u address
v address
Shifted (HAS) transmitted
00000-00777
01000-01777
02000-07777
30--··
30--··
30---·
(Fault, illegal address)
to Q
to A
00000-01777
02000-07777
31---·
31---·
to Q
to A
00000-07777
32---·
to A
If the u address is an MD addres~; when using this property of the Shift
instructions (A) or (Q) is returned to the drum but not to the original
address; e.g.,
41234
LA
32011
resulting in
Clear A
(A) js shifted 9 places to the left
c. tfROUND OFF" AND "SCALE DOWN" OPERATIONS. - During the course of many
arithmetic operations it becomes necessary to change the scaling of a number.
A simple method of scaling a number clown would be to perform a left shift of
k places equivalent to the desired rjght shift. For example, the instructions
below multiply two numbers, (u) and IqmJ~ 234 where qm =
or
1 >
Iq I~
(Q)
1/2.
In the above example it was tacitly assumed that the magnitude of b was greater
than the magnitude of c. If this were not the case, the result of executing
(f2) would cause a divide overflow since
2
36
I
35
> qml~ 2 •
f.. REPEAT INSTRUCTION. - Because of the complexity of the Repeat instruction, the details of the repeat operation are restated below.
(1)
FORMAT OF REPEAT INSTRUCTION. - The Repeat instruction has the
form RPjnw. The normal values of j are 0 through 3 and determine the advance
of the execution addresses of the repeated instruction as follows.
if j=O, neither the u nor v address portion of the repeated
instruction is advanced.
if j=l, the v address of the repeated instruction is advanced by one after each execution.
if j=2, the u address of the repeated instruction is advanced by one after each execution.
if j=3, both the u and v addresses of the repeated instruc-
tion are advanced by one after each execution.
The advance of the addresses occurs only in the Program Control Register
(PCR) where the repeated instruction is held during the repeat operations.
Therefore, the original form of the repeated instruction in storage is
unaltered.
The value n determines the number of times the repeated instruction is to
be executed. This value can vary through the range 0 through 4095 (decimal).
If n is zero, the repeat operations are terminated without execution of the
"repeated" instruction.
PX 40
53
CODING FOR THE COMPUTER
The "repeat termination address", w, replaces the v address portion of
fixed address FI (00000 or 40001) during the execution of the RP instruction.
(Normally, Fl contains an MJjv instruction with a j of 0.) This feature provides the means of fljumping out" of the repeated operations after n executions
of the repeated instruction.
(2) REPEATED NON-JUMP INSTHUCTION. - The repeated instruction is
held in the Program Control Registers (PCR) and is executed n times. After
the nth execution, a jump to Fl occurs. Because this instruction is usually
an MJjv with a j of zero and a v of w, it produces a jump to the address originally specified by w of the RP instruction.
(3) REPEATED JUMP INSTRUCTION. - If the repeated instruction is a
Threshold Jump (TJ) or Equality Jump (EJ), the jump to w may not occur. The
repeated instruction is held in PCR and is executed not more than n times. If
n executions occur with no jump condition being fulfilled, the normal termination, consisting of a jump to FI , followed by a jump to w, occurs. However,
if any execution of the repeated instruction fulfills a jump condition, the
value j, n-r is stored in the v portion of Q(where j = j of RP instruction;
and n-r = n of RP instruction minus r, the number of executions performed),
and a jump is made to the address specified by v of the TJ or EJ instruction.
Similar circumstances are created by the Index Jump and Manually Selective
Jump instructions with the exception that no indication of the number of executions is given by a storage in Q.
Other instructions (Interpret, Return Jump, Q Jump, Sign Jump, Zero Jump,
Manually Selective Stop, and Prograrr: Stop) produce a jump or stop on the first
execution, and thus behave as if no RP instruction preceded them.
(4) EXAMPLES USING THE REPEAT INSTRUCTION. - In many problems which
are programmed for computer execution, it is important that the most efficient
use of operating time and storage capacity be made. The Repeat instruction,
an unusual logical feature of the Univac Scientifi~ makes it possible to
realize a sizeable reduction in the time spent referring to storage for instructions and in the storage space devoted to holding instructions. By
using the RP instruction, long sequences of operations can be governed by only
two or three instructional references to storage. This is evidenced by the
following examples.
PX 40
54
CODING FOR THE COMPUTER
Consider the accumulation of products, such as,
S = alb l + a2 b2 + •.. + anb n =
i~
aibi
The Multiply Add instruction (MAuv) c~uses the product of the numbers located
in storage with the addresses u and v to be added to the number already in the
Accumulator, leaving the total result in the 72-bit Accumulator. If the MA
instruction is repeated as shown below, the scalar product of two n-vectors
is generated.
dl
RS
A
A
d2
RP
3,n
d4
d3
MA
ul
vI
d4
ul
Clear Accumulator to zero
}
Form sum of products
S
= (ul)
(vI) + (u2) (v2) + ... + (un)(vn)
Next instruction
al
Vector a
un
an
vI
bl
Vector b
vn
bn
Note the instruction at dl which clears the Accumulator to insure that its
initial content is zero.
Care should be taken that the contents of FI are not inadvertently altered
during a block transfer of n words to Rapid Access Storage. This pitfall is
illustrated by the following example:
RP
TP
30400
50000
w
07600
The sequence of events which occurs during the execution of these instructions
is as follows:
(a) Replace the lower order 15 bits of (FI) with the address w
(b) Proceed to transmit the contents of
PX 40
55
CODING rOR THE COMPUTER
50000 to 07600
50001 to 07601
50177 to 0777'7
50200 to 00000
50377 to 0017'7
(c) Extract the next instruction to be executed from address Fl.
Note that the contents of the addre:is 00000, (F l ), have been replaced by the
contents of address 50200 during the repeated transmissive operations. Because of this, the desired jump to wo no longer exists at this address.
The following example illustrates further the care that must be exercised
when using the Repeat instruction.
00100
00101
HP
TP
30200
45000
00303
00200
The operations performed by thi:, pair of instructions are:
(a)
(b)
Replace the lower order 15 bits of (Fl) with the address
00303
Proceed to transm:i t the contents of
45000 to 00200
45001 to 00201
45102 to 00302
45103 to 00303
45177 to 00377
(c)
(5) The
order 15 bits of
address w of the
sequence extract
Extract the next instruction to be executed from address Fl.
Note that in this example the original contents of 00303 have
been replaced by the contents of address 45103. Therefore,
the next instruction to be executed after the jump to 00303
is the instruction whic:h was originally stored at 45103.
initial operations of the RP instruction replace the lowest
(Fl), the contents of the address 00000 (or 40001), with the
RPjnw instruction. The terminating operations of the repeat
the next instruction to be executed from the address Fl
PX 40
56
CODING FOR THE COMPUTER
(unless the repeated instruction called for a jump to v). The instruction contained in Fl is normally a jump instruction (usually an MJjv) referencing its
vaddress~ the address w written in by the RP.
However, if the instruction
contained in Fl is not a jump instruction, or if it is a conditional jump
(IJ, MJ, TJ or EJ) where the jump condition is not" fulfilled, the next instruction to be executed after the execution of the instruction at Fl is
taken from one of the following addresses:
If
If
If
If
j
j
j
j
was
was
was
was
0, NI
I, NI
2, NI
3, NI
from
from
from
from
address
address
address
address
40000
70000
60000
50000 •
These are the addresses that are left in the Program Address Counter (PAK)
after the gp instruction, because of the use of PAK as the counter for the number of executions to be performed on the repeated instruction.
(7) PRINT AND PUNCH INSTRUCTION, PR-v AND PUjv. - Because of the operands of the Print and Punch instructions requiring only a six bit storage space,
these instructions can be coded so that a savings of storage space is effected.
The v address of PUjv or PR-v may reference any instruction whose v address
references the Accumulator or Q Register, or whose v address portion is not
used in the instruction, e.g., AMjn-, BMjn-, or PS--. For example, note the
following instructions:
01001
PR
00000
01050
01050
MP
00010
31052
Print the number ttl"
Note that only one character is printed or punched with each output reference. In order to print or punch out in octal a 36 bit word, twelve Print or
Punch instructions would be needed.
To illustrate the use of these instructions, consider the following routine
which prints out on the typewriter one word in octal.
Cl
PR
0
elO
Print carriage return
C2
LQ
dl
3
Shift word to be printed 3 places
to the left
C3
QT
d2
A
Mask out 3 bits or one octal digit.
C4
AT
d3
C5
Compute print instruction which is NI.
C5
PR
0
ei
Print one octal digit.
C6
IJ
d4
C2
Test for end, if not finished go to C2
C7
PS
End.
PX .40
57
CODING FOR THE COMPUTER
d1
xx
xxxxx
xxxxx
Number to be printed
d2
00
00000
00007
Mask
d3
PR
a
eO
d4
00
00000
00013
Counter, n-1
eO
00
00000
00037
(0)
e1
00
00000
00052
(1 )
e2
00
00000
00074
(2)
e3
00
00000
00070
(3)
e4
00
00000
00064
(4 )
e5
00
00000
00062
(5)
e6
00
00000
00066
(6)
e7
00
00000
00072
(7)
e10
00
00000
00045
PX 40
58
Dummy command
= 1110
F1exowriter codes for
the digits a through 7.
F1exowriter code for
carriage return.
APPENDIX A
NUMBER SYSTEMS
PX 41
NUMBER SYSTEMS
1.
GENERAL
Any positive integer N can be expressed in the form
N = Anrn + An_lr n- l + ... + Alrl + AOrO
where 0 ~ Ai < rand r is any integer greater than 1.
the base or radix of the number system.
The integer r is called
The only radix values that need to
be considered for programming for the UNIVAC SCIENTIFIC are 10, 8 and 2.
The
number systems with these radices are called decimal, octal, and binary systerns, respectively.
An integer N expressed as a number in the usual decimal notation implies
that the number is a refinement of a polynomial in powers of 10 with coefficients which satisfy the relation 0 ~ Ai < 10.
the polynomial N
= 3.102
+ 0.10 1 + 8.100 .
= 308 implies
integer N = 1011
For example, N
Accordingly, an
in the binary system with OS Ai < 2 may be expressed as the polynomial
N = 1.2 3 + 0.2 2 + 1.2 1 + 1.2 0 (= 11 decimal); and an integer N = 126 in the
octal system with 05Ai< 8 may be expressed as the polynomial
N
=
1.82 + 2.8 1 + 6.8 0
(=
86 decimal).
Because electronic and magnetic circuits consist primarily of bi-stable
elements, the computer uses the binary representation in all internal manipulations of numbers.
As will be seen later, there is a very simple relation-
ship between the binary and octal representations of a number.
Since conver-
sion between these two systems is almost immediate and since the octal notation
is shorter, programs are encoded with octal notation representing binary numbers.
It is desirable for people who prepare programs for the computer to be
PX 41
1
NlJ;\1BER SYSTEMS
familiar wIth methods of converting numbers from decimal to binary to octal
fonn and vice versa.
When the base of a number is not apparent from the con-
text, it will be specified by a subscript as shown in the following example:
34 10 = 428
=:
1000102
PX 41
NUMBER SYSTEMS
2.
CHANGE OF BASE
Since the manual conversion of numbers from one system to another involves
the arithmetic operations of addition and multiplication, it is necessary to
know the sums and products of certain pairs of integers expressed in the octal
and binary systems.
In doing arithmetic operations by hand, the ability to
remember the sums and products of pairs of decimal digits is utilized, although
these sums and products are tabulated in decimal addition and multiplication
Similar tables presented below are necessary for arithmetic operations
tables.
with octal and binary digits.
OCTAL ADDITION TABLE
OCTAL MULTIPLICATION TABLE
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
10
1 0
1
2
3
4
5
6
7
10
11
2
0
2
4
6
10
12
14
16
10
11
12
3
0
3
6
11
14
17
22
25
10
11
12
13
4
0
4
10
14
20
24
30
34
10
11
12
13
14
5
0
5
12
17
24
31
36
43
10
11
12
13
14
15
6
0
6
14
22
30
36
44
52
11
12
13
14
15
16
7
0
7
16
25
34
43
52
61
0
1
2
3
4
5
6
7
0
0
1.
2
3
4
5
6
7
1
1
2
3
4
5
6
7
2
2
3
4
5
6
7
3
3
4
5
6
7
4
4
5
6
7
5 5
6
7
6
6
7
7 7
10
0
The addition table and the multiplication table for binary numbers are
shown below
BINARY ADD IT ION TABLE
0
0
1
BINARY MULTIPLICATION TABLE
0
1
~
1
0
10
1
PX 41
3
1
~
o
1
NUMBER SYSTEMS
a.
CONVERSION OF INTEGERS. - The simplest way of changing a binary or
octal integer to its decimal equivalent is to expand it to, and evaluate the
sum of the terms of, the polynomial expression given on a previous page.
conversion from decimal to octal or binary presents more of a problem.
methods are given which can be used for these conversions.
The
Two
The first of these
is as follows:
(1)
Given two integers N and Ow the latter being positive, it can be
shown that there exist unique integers Q and R such that N
OS R< D.
= QD
+ R where
This is, of course, true regardless of the choice of base used in
expressing N.
Hence, if NIO and NS are the decimal and octal expressions for
the same integer and if 010 and Da are the decimal and octal expressions for
another (positive) integer, we can compare the two equations
N10
= QlO· 0 10
Na
-- Qa'Da + Ra_ OS Ra< Da
+ RIO, 0 S RIO < 010
and conclude that QIO = Qa and RIO = Rao
This fact is used in the process of
converting an integer from base 10 to base a in the following way:
The decimal
expressions for an integer N expressed as NlO and Na are
NIO = dnlO n + dn_llon~l + ... + dllO + dO, OSdi < 10
Na
= emam
+ em-. la m- l +
0
••
+ ela + eO, OSei < a
Dividing the polynomials by decimal a gives the same remainder in either case,
but from the second expression, it is obvious that this remainder is eO while
the quotient is ema m- l + e m_.la m- 2
+ e2 a + e lo Dividing this quotient by a
gives the new quotient ema m- 2 + ... e3 a + e2 and the new remainder el' Continuing division results in the successive remainders eO, el, e2' "', em which
are the
di~Jits
of Na in reverse order.
In a numerical case, the successive
PX 41
NUMBER SYSTEMS
divisions of NIO by decimal 8 yield remainders which are actually the decimal
equivalents of the digits eO, el' ... , em.
To illustrate this method, the number expressed as 1492 in decimal notation
is changed to its octal equivalent as follows:
Decimal Expression
Octal Equivalent
82 1492 ,
Remainder 4
4
8 ) 186,
Remainder 2
2
8~
Remainder 7
7
8.~
Remainder 2
2
0
Thus 149210 = 2724 8
Conversion of an integer N from base 8 to base 10 can be carried out in a
similar fashion by dividing N8 by 128
(=
1010) to yield the octal equivalents
of the digits of NIO.
The conversion of an integer N from base 10 to base 2 or from base 2 to
base 10 can be discussed according to the method outlined above with NIO
and
N2 represented as follows:
NIO = dnlO n + ... + dllO + dO, OSdi <10
N2
= b k2 k
+ ... + b 12 + bO t 0 S b i < 2
NIO would be divided by 2 to yield the decimal equivalents of the digits of
N2, and N2 would be divided by 1010
(=
10 10) to yield the binary equivalents
of the digits of NIO.
(2) The method that follows has the advantage that it yields the desired digits in normal order, but it has the disadvantage that it requires a
knowledge of the values of powers of one base in terms of another.
PX 41
5
This method
NUMBER SYSTEMS
requires the procedure below:
Given a number Nr to express as Nb = anb n + an_lb n- l + ..• + alb l + aOb O, the
coefficients an •.. ao, .Q:S ai < b, may be found as follows:
1.
Determine the highest power n such that b n+l > N r-
Then, let N r
= Nn .
Divide Nn by bn , yielding the quotient an and the remainder
Nn--l = an_lb n- l + ... + aOb O•
2.
Repeat the divisions of Ni (i = n, n-l, .•. , 0) by b i until the last
division yields the quotient aO.
3.
A quotient (or coefficient) ai may be zero and must be represented in
its proper order in the final result.
As an example of this method the number expressed decimally as 137 is changed
to its octal equivalent as follows:
Nn = anb n + an_1b n-l +
r = 10, b = S,
137
9
1
= 2.64
= l·S
= 1.1
Nr
+ aOb
° = Nb
=N n = 137. n = 2 (S3> 137)
+ 9
+ 1
a 1 = 1, NO = 1
+ 0
aO = 1
The coefficients derived above arE' the digits of NS ; thus NIO = 137 = NS
(3)
= 211.
Although it would be possible to use the above methods in convert-
ing an integer from base S to bas€' 2 and vice versa, it is easier to convert by
inspection.
This can be done because of simple relationship, discussed sub-
sequently, between NS and N2, dep€~ndent upon the fact that 23
= S.
The equi valent polynomials f01' an integer N expressed as NS and N2 are
NS = emS m + em_ISm- l +
+ e2S2 + elS l + eOSO, OSei
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